From 2825189542c13a103e123b01d904d7a0f817ef44 Mon Sep 17 00:00:00 2001 From: Wayne Lin Date: Mon, 3 Oct 2022 15:07:07 +0800 Subject: [PATCH] Add NuMaker-HMI-MA35D1 and RTP porting. --- bsp/nuvoton/README.md | 24 +- bsp/nuvoton/docs/LVGL_Notes.md | 1 + .../libraries/m031/rtt_port/drv_uart.c | 4 +- .../libraries/m2354/rtt_port/drv_usbhost.c | 115 +- .../libraries/m460/rtt_port/drv_ccap.c | 22 +- .../libraries/m460/rtt_port/drv_usbhost.c | 133 +- .../libraries/m480/rtt_port/drv_usbhost.c | 130 +- .../ma35/CMSIS/Include/arm_common_tables.h | 136 + .../ma35/CMSIS/Include/arm_const_structs.h | 79 + .../libraries/ma35/CMSIS/Include/arm_math.h | 7154 ++++++++++++ .../ma35/CMSIS/Include/cmsis_armcc.h | 734 ++ .../ma35/CMSIS/Include/cmsis_armcc_V6.h | 1804 ++++ .../libraries/ma35/CMSIS/Include/cmsis_gcc.h | 1377 +++ .../libraries/ma35/CMSIS/Include/core_cm0.h | 798 ++ .../ma35/CMSIS/Include/core_cm0plus.h | 914 ++ .../libraries/ma35/CMSIS/Include/core_cm3.h | 1763 +++ .../libraries/ma35/CMSIS/Include/core_cm4.h | 1937 ++++ .../libraries/ma35/CMSIS/Include/core_cm7.h | 2535 +++++ .../ma35/CMSIS/Include/core_cmFunc.h | 87 + .../ma35/CMSIS/Include/core_cmInstr.h | 87 + .../ma35/CMSIS/Include/core_cmSimd.h | 96 + .../libraries/ma35/CMSIS/Include/core_sc000.h | 926 ++ .../libraries/ma35/CMSIS/Include/core_sc300.h | 1745 +++ bsp/nuvoton/libraries/ma35/CMSIS/SConscript | 14 + .../Device/Nuvoton/MA35D1/Include/NuMicro.h | 15 + .../Device/Nuvoton/MA35D1/Include/adc_reg.h | 378 + .../Device/Nuvoton/MA35D1/Include/canfd_reg.h | 1709 +++ .../Device/Nuvoton/MA35D1/Include/ccap_reg.h | 453 + .../Device/Nuvoton/MA35D1/Include/clk_reg.h | 2596 +++++ .../Nuvoton/MA35D1/Include/crypto_reg.h | 7135 ++++++++++++ .../Nuvoton/MA35D1/Include/ddr32phy_reg.h | 9569 +++++++++++++++++ .../Device/Nuvoton/MA35D1/Include/disp_reg.h | 1432 +++ .../Device/Nuvoton/MA35D1/Include/dpm_reg.h | 315 + .../Device/Nuvoton/MA35D1/Include/eadc_reg.h | 2278 ++++ .../Device/Nuvoton/MA35D1/Include/ebi_reg.h | 428 + .../Device/Nuvoton/MA35D1/Include/ecap_reg.h | 389 + .../Device/Nuvoton/MA35D1/Include/epwm_reg.h | 4978 +++++++++ .../Device/Nuvoton/MA35D1/Include/gfx_reg.h | 382 + .../Device/Nuvoton/MA35D1/Include/gmac_reg.h | 2606 +++++ .../Device/Nuvoton/MA35D1/Include/gpio_reg.h | 1221 +++ .../Nuvoton/MA35D1/Include/hsusbd_reg.h | 3108 ++++++ .../Nuvoton/MA35D1/Include/hsusbh_reg.h | 597 + .../Device/Nuvoton/MA35D1/Include/hwsem_reg.h | 452 + .../Device/Nuvoton/MA35D1/Include/i2c_reg.h | 453 + .../Device/Nuvoton/MA35D1/Include/i2s_reg.h | 704 ++ .../Device/Nuvoton/MA35D1/Include/kpi_reg.h | 409 + .../Device/Nuvoton/MA35D1/Include/ks_reg.h | 473 + .../Device/Nuvoton/MA35D1/Include/ma35d1.h | 1050 ++ .../Device/Nuvoton/MA35D1/Include/nfi_reg.h | 2850 +++++ .../Device/Nuvoton/MA35D1/Include/otp_reg.h | 346 + .../Device/Nuvoton/MA35D1/Include/pdma_reg.h | 1020 ++ .../Device/Nuvoton/MA35D1/Include/plm_reg.h | 76 + .../Device/Nuvoton/MA35D1/Include/qei_reg.h | 314 + .../Device/Nuvoton/MA35D1/Include/qspi_reg.h | 661 ++ .../Device/Nuvoton/MA35D1/Include/rtc_reg.h | 1318 +++ .../Device/Nuvoton/MA35D1/Include/sc_reg.h | 972 ++ .../Device/Nuvoton/MA35D1/Include/sdh_reg.h | 2670 +++++ .../Device/Nuvoton/MA35D1/Include/spi_reg.h | 893 ++ .../Device/Nuvoton/MA35D1/Include/ssmcc_reg.h | 932 ++ .../Device/Nuvoton/MA35D1/Include/sspcc_reg.h | 2625 +++++ .../Device/Nuvoton/MA35D1/Include/sys_reg.h | 5816 ++++++++++ .../Nuvoton/MA35D1/Include/system_ma35d1.h | 65 + .../Device/Nuvoton/MA35D1/Include/timer_reg.h | 1069 ++ .../Device/Nuvoton/MA35D1/Include/trng_reg.h | 922 ++ .../Device/Nuvoton/MA35D1/Include/uart_reg.h | 1061 ++ .../Nuvoton/MA35D1/Include/umctl2_reg.h | 3918 +++++++ .../Device/Nuvoton/MA35D1/Include/usbh_reg.h | 796 ++ .../Device/Nuvoton/MA35D1/Include/wdt_reg.h | 179 + .../Device/Nuvoton/MA35D1/Include/whc_reg.h | 1034 ++ .../Device/Nuvoton/MA35D1/Include/wwdt_reg.h | 147 + .../MA35D1/Source/ARM/startup_ma35d1_subm.s | 488 + .../MA35D1/Source/GCC/startup_ma35d1_subm.S | 352 + .../MA35D1/Source/IAR/startup_ma35d1_subm.s | 430 + .../MA35D1/Source/system_ma35d1_subm.c | 67 + bsp/nuvoton/libraries/ma35/Device/SConscript | 22 + bsp/nuvoton/libraries/ma35/README.md | 38 + bsp/nuvoton/libraries/ma35/SConscript | 15 + .../libraries/ma35/StdDriver/SConscript | 13 + .../libraries/ma35/StdDriver/inc/nu_adc.h | 287 + .../libraries/ma35/StdDriver/inc/nu_canfd.h | 476 + .../libraries/ma35/StdDriver/inc/nu_ccap.h | 175 + .../libraries/ma35/StdDriver/inc/nu_clk.h | 622 ++ .../libraries/ma35/StdDriver/inc/nu_disp.h | 205 + .../libraries/ma35/StdDriver/inc/nu_eadc.h | 630 ++ .../libraries/ma35/StdDriver/inc/nu_ebi.h | 350 + .../libraries/ma35/StdDriver/inc/nu_ecap.h | 453 + .../libraries/ma35/StdDriver/inc/nu_epwm.h | 643 ++ .../libraries/ma35/StdDriver/inc/nu_gpio.h | 600 ++ .../libraries/ma35/StdDriver/inc/nu_hwsem.h | 174 + .../libraries/ma35/StdDriver/inc/nu_i2c.h | 296 + .../libraries/ma35/StdDriver/inc/nu_i2s.h | 351 + .../libraries/ma35/StdDriver/inc/nu_kpi.h | 169 + .../libraries/ma35/StdDriver/inc/nu_pdma.h | 421 + .../libraries/ma35/StdDriver/inc/nu_qei.h | 388 + .../libraries/ma35/StdDriver/inc/nu_qspi.h | 379 + .../libraries/ma35/StdDriver/inc/nu_rtc.h | 224 + .../libraries/ma35/StdDriver/inc/nu_sc.h | 266 + .../libraries/ma35/StdDriver/inc/nu_scuart.h | 265 + .../libraries/ma35/StdDriver/inc/nu_sdh.h | 121 + .../libraries/ma35/StdDriver/inc/nu_spi.h | 607 ++ .../libraries/ma35/StdDriver/inc/nu_ssmcc.h | 73 + .../libraries/ma35/StdDriver/inc/nu_sspcc.h | 384 + .../libraries/ma35/StdDriver/inc/nu_sys.h | 1855 ++++ .../libraries/ma35/StdDriver/inc/nu_timer.h | 522 + .../ma35/StdDriver/inc/nu_timer_pwm.h | 745 ++ .../libraries/ma35/StdDriver/inc/nu_uart.h | 489 + .../libraries/ma35/StdDriver/inc/nu_wdt.h | 214 + .../libraries/ma35/StdDriver/inc/nu_whc.h | 279 + .../libraries/ma35/StdDriver/inc/nu_wwdt.h | 150 + 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bsp/nuvoton/libraries/ma35/rtt_port/drv_adc.c | 615 ++ bsp/nuvoton/libraries/ma35/rtt_port/drv_adc.h | 63 + .../libraries/ma35/rtt_port/drv_canfd.c | 660 ++ .../libraries/ma35/rtt_port/drv_ccap.c | 489 + .../libraries/ma35/rtt_port/drv_ccap.h | 49 + .../libraries/ma35/rtt_port/drv_common.c | 437 + .../libraries/ma35/rtt_port/drv_common.h | 83 + .../libraries/ma35/rtt_port/drv_disp.c | 450 + .../libraries/ma35/rtt_port/drv_eadc.c | 154 + .../libraries/ma35/rtt_port/drv_ecap.c | 287 + .../libraries/ma35/rtt_port/drv_epwm.c | 210 + .../ma35/rtt_port/drv_epwm_capture.c | 289 + .../libraries/ma35/rtt_port/drv_gpio.c | 341 + .../libraries/ma35/rtt_port/drv_gpio.h | 40 + bsp/nuvoton/libraries/ma35/rtt_port/drv_i2c.c | 409 + bsp/nuvoton/libraries/ma35/rtt_port/drv_i2c.h | 36 + bsp/nuvoton/libraries/ma35/rtt_port/drv_i2s.c | 637 ++ bsp/nuvoton/libraries/ma35/rtt_port/drv_i2s.h | 96 + .../libraries/ma35/rtt_port/drv_pdma.c | 1265 +++ .../libraries/ma35/rtt_port/drv_pdma.h | 87 + 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.../libraries/ma35/rtt_port/drv_usbhost.c | 950 ++ bsp/nuvoton/libraries/ma35/rtt_port/drv_wdt.c | 372 + .../libraries/ma35/rtt_port/gmac/SConscript | 13 + .../libraries/ma35/rtt_port/gmac/drv_gmac.c | 801 ++ .../libraries/ma35/rtt_port/gmac/mii.c | 144 + .../libraries/ma35/rtt_port/gmac/mii.h | 233 + .../ma35/rtt_port/gmac/synopGMAC_Dev.c | 2961 +++++ .../ma35/rtt_port/gmac/synopGMAC_Dev.h | 1715 +++ .../ma35/rtt_port/gmac/synopGMAC_Host.h | 38 + .../gmac/synopGMAC_network_interface.c | 628 ++ .../gmac/synopGMAC_network_interface.h | 54 + .../ma35/rtt_port/gmac/synopGMAC_plat.c | 78 + .../ma35/rtt_port/gmac/synopGMAC_plat.h | 44 + .../ma35/rtt_port/gmac/synopGMAC_types.h | 31 + .../libraries/ma35/rtt_port/nu_clock_init.c | 398 + .../libraries/n9h30/rtt_port/drv_adc.c | 34 +- .../libraries/n9h30/rtt_port/drv_usbhost.c | 120 +- .../nu_packages/CCAP_Sensors/ccap_demo.c | 44 +- .../nu_packages/CCAP_Sensors/ccap_sensor.c | 9 +- .../nu_packages/CCAP_Sensors/ccap_sensor.h | 2 +- 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36 + .../nuwriter_scripts/nuwriter.py | 1938 ++++ .../nuwriter_ddr_download_and_run.bat | 8 + .../nuwriter_leave_ibr_download_and_run.bat | 8 + .../nuwriter_leave_ibr_sd_pack.bat | 5 + .../nuwriter_nand_programming.bat | 7 + .../nuwriter_sd_programming.bat | 8 + .../nuwriter_spinand_programming.bat | 7 + .../nuwriter_scripts/pack-nand.json | 21 + .../nuwriter_scripts/pack-sd.json | 20 + .../nuwriter_scripts/xusbcom.py | 154 + .../numaker-hmi-ma35d1/preload/Makefile | 68 + .../preload/Makefile.leave_ibr | 69 + .../numaker-hmi-ma35d1/preload/SConscript | 14 + .../numaker-hmi-ma35d1/preload/entry_point.S | 109 + .../numaker-hmi-ma35d1/preload/env_build.bat | 9 + .../numaker-hmi-ma35d1/preload/leave_ibr.ASM | 53 + .../numaker-hmi-ma35d1/preload/preload.ASM | 228 + .../numaker-hmi-ma35d1/preload/preload.ld | 113 + .../numaker-hmi-ma35d1/preload/transcode.py | 41 + bsp/nuvoton/numaker-hmi-ma35d1/rtconfig.py | 77 + bsp/nuvoton/numaker-iot-m467/.config | 5 +- .../numaker-iot-m467/applications/mnt.c | 19 +- bsp/nuvoton/numaker-m032ki/.config | 2 + bsp/nuvoton/numaker-m467hj/.config | 2 + bsp/nuvoton/numaker-m467hj/board/board_dev.c | 2 +- 334 files changed, 168700 insertions(+), 343 deletions(-) create mode 100644 bsp/nuvoton/libraries/ma35/CMSIS/Include/arm_common_tables.h create mode 100644 bsp/nuvoton/libraries/ma35/CMSIS/Include/arm_const_structs.h create mode 100644 bsp/nuvoton/libraries/ma35/CMSIS/Include/arm_math.h create mode 100644 bsp/nuvoton/libraries/ma35/CMSIS/Include/cmsis_armcc.h create mode 100644 bsp/nuvoton/libraries/ma35/CMSIS/Include/cmsis_armcc_V6.h create mode 100644 bsp/nuvoton/libraries/ma35/CMSIS/Include/cmsis_gcc.h create mode 100644 bsp/nuvoton/libraries/ma35/CMSIS/Include/core_cm0.h create mode 100644 bsp/nuvoton/libraries/ma35/CMSIS/Include/core_cm0plus.h create mode 100644 bsp/nuvoton/libraries/ma35/CMSIS/Include/core_cm3.h create mode 100644 bsp/nuvoton/libraries/ma35/CMSIS/Include/core_cm4.h create mode 100644 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100644 bsp/nuvoton/numaker-hmi-ma35d1/nuwriter_scripts/xusbcom.py create mode 100644 bsp/nuvoton/numaker-hmi-ma35d1/preload/Makefile create mode 100644 bsp/nuvoton/numaker-hmi-ma35d1/preload/Makefile.leave_ibr create mode 100644 bsp/nuvoton/numaker-hmi-ma35d1/preload/SConscript create mode 100644 bsp/nuvoton/numaker-hmi-ma35d1/preload/entry_point.S create mode 100644 bsp/nuvoton/numaker-hmi-ma35d1/preload/env_build.bat create mode 100644 bsp/nuvoton/numaker-hmi-ma35d1/preload/leave_ibr.ASM create mode 100644 bsp/nuvoton/numaker-hmi-ma35d1/preload/preload.ASM create mode 100644 bsp/nuvoton/numaker-hmi-ma35d1/preload/preload.ld create mode 100644 bsp/nuvoton/numaker-hmi-ma35d1/preload/transcode.py create mode 100644 bsp/nuvoton/numaker-hmi-ma35d1/rtconfig.py diff --git a/bsp/nuvoton/README.md b/bsp/nuvoton/README.md index c3548b8813..7cbf783135 100644 --- a/bsp/nuvoton/README.md +++ b/bsp/nuvoton/README.md @@ -1,14 +1,16 @@ # Nuvoton BSP Description + Current supported BSP shown in below table: -| **BSP Folder** | **Board Name** | -| ------------------------- | -------------------------- | -| [numaker-iot-m487](numaker-iot-m487) | Nuvoton NuMaker-IoT-M487 | -| [numaker-pfm-m487](numaker-pfm-m487) | Nuvoton NuMaker-PFM-M487 | -| [nk-980iot](nk-980iot) | Nuvoton NK-980IOT | -| [numaker-m2354](numaker-m2354) | Nuvoton NuMaker-M2354 | -| [nk-rtu980](nk-rtu980) | Nuvoton NK-RTU980 | -| [nk-n9h30](nk-n9h30) | Nuvoton NK-N9H30 | -| [numaker-m032ki](numaker-m032ki) | Nuvoton NuMaker-M032KI | -| [numaker-m467hj](numaker-m467hj) | Nuvoton NuMaker-M467HJ | -| [numaker-iot-m467](numaker-iot-m467) | Nuvoton NuMaker-IoT-M467 | +| **Board Name** | **CPU Architecture** | **BSP Folder** | +| ------------------------- | ------------------------- | -------------------------- | +| NuMaker-IoT-M487 | CORTEX-M4 | [numaker-iot-m487](numaker-iot-m487) | +| NuMaker-PFM-M487 | CORTEX-M4 | [numaker-pfm-m487](numaker-pfm-m487) | +| NK-980IOT | ARM926EJS | [nk-980iot](nk-980iot) | +| NuMaker-M2354 | CORTEX-M23 | [numaker-m2354](numaker-m2354) | +| NK-RTU980 | ARM926EJS | [nk-rtu980](nk-rtu980) | +| NK-N9H30 | CORTEX-M4 | [nk-n9h30](nk-n9h30) | +| NuMaker-M032KI | CORTEX-M0 | [numaker-m032ki](numaker-m032ki) | +| NuMaker-M467HJ | CORTEX-M4 | [numaker-m467hj](numaker-m467hj) | +| NuMaker-IoT-M467 | CORTEX-M4 | [numaker-iot-m467](numaker-iot-m467) | +| NuMaker-HMI-MA35D1 | CORTEX-A35, CORTEX-M4 | [numaker-hmi-ma35d1](numaker-hmi-ma35d1), [ma35-rtp](ma35-rtp) | diff --git a/bsp/nuvoton/docs/LVGL_Notes.md b/bsp/nuvoton/docs/LVGL_Notes.md index 9245f92804..1ccadd838c 100644 --- a/bsp/nuvoton/docs/LVGL_Notes.md +++ b/bsp/nuvoton/docs/LVGL_Notes.md @@ -12,6 +12,7 @@ Current supported LVGL running environment on Nuvoton's boards shown in below ta | numaker-m032ki | Widgets | Nu-TFT v1.3 | config_lvgl | | numaker-m467hj | Widgets | NuMaker-TFT-LCD43 v1.0 | config_lvgl | | numaker-iot-m467 | Widgets | Nu-TFT v1.3 | config_lvgl | +| numaker-hmi-ma35d1 | Widgets | No | .config | ## Download related packages diff --git a/bsp/nuvoton/libraries/m031/rtt_port/drv_uart.c b/bsp/nuvoton/libraries/m031/rtt_port/drv_uart.c index e8743850ba..58e0ffc4db 100644 --- a/bsp/nuvoton/libraries/m031/rtt_port/drv_uart.c +++ b/bsp/nuvoton/libraries/m031/rtt_port/drv_uart.c @@ -516,7 +516,7 @@ static rt_err_t nu_pdma_uart_rx_config(struct rt_serial_device *serial, uint8_t nu_pdma_uart_rx_cb, (void *)serial, NU_PDMA_EVENT_TRANSFER_DONE | NU_PDMA_EVENT_TIMEOUT); - if ( result != RT_EOK ) + if (result != RT_EOK) { goto exit_nu_pdma_uart_rx_config; } @@ -527,7 +527,7 @@ static rt_err_t nu_pdma_uart_rx_config(struct rt_serial_device *serial, uint8_t (uint32_t)pu8Buf, i32TriggerLen, 1000); //Idle-timeout, 1ms - if ( result != RT_EOK ) + if (result != RT_EOK) { goto exit_nu_pdma_uart_rx_config; } diff --git a/bsp/nuvoton/libraries/m2354/rtt_port/drv_usbhost.c b/bsp/nuvoton/libraries/m2354/rtt_port/drv_usbhost.c index e54580d671..abee7c2a77 100644 --- a/bsp/nuvoton/libraries/m2354/rtt_port/drv_usbhost.c +++ b/bsp/nuvoton/libraries/m2354/rtt_port/drv_usbhost.c @@ -21,6 +21,13 @@ #include "usb.h" #include "usbh_lib.h" +#define LOG_TAG "drv.usbhost" +#define DBG_ENABLE +#define DBG_SECTION_NAME LOG_TAG +#define DBG_LEVEL LOG_LVL_DBG +#define DBG_COLOR +#include + #if !defined(NU_USBHOST_HUB_POLLING_INTERVAL) #define NU_USBHOST_HUB_POLLING_INTERVAL (100) #endif @@ -60,6 +67,7 @@ typedef struct nu_port_dev UDEV_T *pUDev; EP_INFO_T *apsEPInfo[NU_MAX_USBH_PIPE]; struct urequest asSetupReq[NU_MAX_USBH_PIPE]; + uint32_t u32SentLength[NU_MAX_USBH_PIPE]; struct rt_completion utr_completion; int port_num; rt_bool_t bEnumDone; @@ -426,22 +434,30 @@ static int nu_int_xfer( int timeouts) { int ret; - int retry = 3; - while (retry > 0) + while (1) { ret = usbh_int_xfer(psUTR); - if (ret == 0) + if (ret < 0) + return ret; + + if (rt_completion_wait(&(psPortDev->utr_completion), timeouts) != 0) + { + RT_DEBUG_LOG(RT_DEBUG_USB, ("Request %08x Timeout in %d ms!!\n", psUTR, timeouts)); + usbh_quit_utr(psUTR); + + rt_completion_init(&(psPortDev->utr_completion)); + rt_thread_mdelay(1); + } + else + { + + RT_DEBUG_LOG(RT_DEBUG_USB, ("Transferring done %08x\n", psUTR)); + usbh_quit_utr(psUTR); break; - - RT_DEBUG_LOG(RT_DEBUG_USB, ("nu_int_xfer ERROR: failed to submit interrupt request\n")); - rt_thread_delay((pipe->ep.bInterval * RT_TICK_PER_SECOND / 1000) > 0 ? (pipe->ep.bInterval * RT_TICK_PER_SECOND / 1000) : 1); - retry --; + } } - if (ret < 0) - return ret; - return 0; } @@ -453,30 +469,6 @@ static void xfer_done_cb(UTR_T *psUTR) rt_completion_done(&(psPortDev->utr_completion)); } -static void int_xfer_done_cb(UTR_T *psUTR) -{ - upipe_t pipe = (upipe_t)psUTR->context; - - if (psUTR->status != 0) - { - RT_DEBUG_LOG(RT_DEBUG_USB, ("Interrupt xfer failed %d\n", psUTR->status)); - goto exit_int_xfer_done_cb; - } - - if (pipe->callback != RT_NULL) - { - struct uhost_msg msg; - msg.type = USB_MSG_CALLBACK; - msg.content.cb.function = pipe->callback; - msg.content.cb.context = pipe; - rt_usbh_event_signal(&s_sUSBHDev.uhcd, &msg); - } - -exit_int_xfer_done_cb: - - free_utr(psUTR); -} - static int nu_pipe_xfer(upipe_t pipe, rt_uint8_t token, void *buffer, int nbytes, int timeouts) { S_NU_RH_PORT_CTRL *psPortCtrl; @@ -510,6 +502,7 @@ static int nu_pipe_xfer(upipe_t pipe, rt_uint8_t token, void *buffer, int nbytes { struct urequest *psSetup = (struct urequest *)buffer_nonch; RT_ASSERT(buffer_nonch != RT_NULL); + psPortCtrl->asHubPortDev->u32SentLength[pipe->pipe_index] = 0; /* Read data from USB device. */ if (psSetup->request_type & USB_REQ_TYPE_DIR_IN) @@ -531,10 +524,31 @@ static int nu_pipe_xfer(upipe_t pipe, rt_uint8_t token, void *buffer, int nbytes //token == USBH_PID_DATA if (buffer_nonch && ((pipe->ep.bEndpointAddress & USB_DIR_MASK) == USB_DIR_IN)) { + struct urequest *psSetup = &psPortCtrl->asHubPortDev->asSetupReq[pipe->pipe_index]; + /* Read data from USB device. */ //Trigger USBHostLib Ctril_Xfer - ret = nu_ctrl_xfer(psPortDev, &psPortCtrl->asHubPortDev->asSetupReq[pipe->pipe_index], buffer_nonch, timeouts); - if (ret != nbytes) + /* + * Workaround: HCD driver can readback all bytes of setup.wLength, but not support single packet transferring. + */ + if (psPortCtrl->asHubPortDev->u32SentLength[pipe->pipe_index] == 0) + { + ret = nu_ctrl_xfer(psPortDev, psSetup, buffer_nonch, timeouts); + psPortCtrl->asHubPortDev->u32SentLength[pipe->pipe_index] = ret; + } + else + { + if (psPortCtrl->asHubPortDev->u32SentLength[pipe->pipe_index] < nbytes) + { + ret = 0; + } + else + { + psPortCtrl->asHubPortDev->u32SentLength[pipe->pipe_index] -= nbytes; + ret = nbytes; + } + } + if (ret <= 0) goto exit_nu_pipe_xfer; } else @@ -579,9 +593,6 @@ static int nu_pipe_xfer(upipe_t pipe, rt_uint8_t token, void *buffer, int nbytes } else if (pipe->ep.bmAttributes == USB_EP_ATTR_INT) { - psUTR->func = int_xfer_done_cb; - psUTR->context = pipe; - if (nu_int_xfer(pipe, psPortDev, psUTR, timeouts) < 0) { RT_DEBUG_LOG(RT_DEBUG_USB, ("nu_pipe_xfer ERROR: int transfer failed\n")); @@ -591,7 +602,7 @@ static int nu_pipe_xfer(upipe_t pipe, rt_uint8_t token, void *buffer, int nbytes { i32XferLen = nbytes; } - goto exit2_nu_pipe_xfer; + goto exit_nu_pipe_xfer; } else if (pipe->ep.bmAttributes == USB_EP_ATTR_ISOC) { @@ -630,20 +641,17 @@ failreport_nu_pipe_xfer: i32XferLen = psUTR->xfer_len; +exit_nu_pipe_xfer: + //Call callback if (pipe->callback != RT_NULL) { pipe->callback(pipe); } -exit_nu_pipe_xfer: - if (psUTR) free_utr(psUTR); -exit2_nu_pipe_xfer: - - NU_USBHOST_UNLOCK(); return i32XferLen; @@ -851,12 +859,19 @@ int nu_usbh_register(void) psUHCD->num_ports = NU_MAX_USBH_PORT; #if !defined(BSP_USING_OTG) - SYS_UnlockReg(); + { + uint32_t u32RegLockBackup; - /* Set OTG as USB Host role */ - SYS->USBPHY = SYS_USBPHY_OTGPHYEN_Msk | SYS_USBPHY_SBO_Msk | (0x1 << SYS_USBPHY_USBROLE_Pos); + u32RegLockBackup = SYS_IsRegLocked(); + if (u32RegLockBackup) + SYS_UnlockReg(); - SYS_LockReg(); + /* Set OTG as USB Host role */ + SYS->USBPHY = SYS_USBPHY_OTGPHYEN_Msk | SYS_USBPHY_SBO_Msk | (0x1 << SYS_USBPHY_USBROLE_Pos); + + if (u32RegLockBackup) + SYS_LockReg(); + } #endif @@ -875,6 +890,6 @@ int nu_usbh_register(void) return 0; } -INIT_DEVICE_EXPORT(nu_usbh_register); +INIT_APP_EXPORT(nu_usbh_register); #endif diff --git a/bsp/nuvoton/libraries/m460/rtt_port/drv_ccap.c b/bsp/nuvoton/libraries/m460/rtt_port/drv_ccap.c index 3a7e680911..986d10b174 100644 --- a/bsp/nuvoton/libraries/m460/rtt_port/drv_ccap.c +++ b/bsp/nuvoton/libraries/m460/rtt_port/drv_ccap.c @@ -208,6 +208,22 @@ static rt_err_t ccap_pipe_configure(nu_ccap_t psNuCcap, ccap_view_info_t psViewI { uint32_t u32Offset = 0; uint32_t u32WM, u32WN, u32HM, u32HN; + uint32_t u32Div = 0; + + if (psCcapConf->sPipeInfo_Planar.u32PixFmt == CCAP_PAR_PLNFMT_YUV422) + { + /* U/V farm size equals Y/2 farm size */ + u32Div = 2; + } + else if (psCcapConf->sPipeInfo_Planar.u32PixFmt == CCAP_PAR_PLNFMT_YUV420) + { + /* U/V farm size equals Y/4 farm size */ + u32Div = 4; + } + else + { + goto fail_ccap_pipe_configure; + } /* Set System Memory Planar Y Base Address Register */ CCAP_SetPlanarYBuf(psNuCcap->base, (uint32_t)psCcapConf->sPipeInfo_Planar.pu8FarmAddr + u32Offset); @@ -217,7 +233,7 @@ static rt_err_t ccap_pipe_configure(nu_ccap_t psNuCcap, ccap_view_info_t psViewI /* Set System Memory Planar U Base Address Register */ CCAP_SetPlanarUBuf(psNuCcap->base, (uint32_t)psCcapConf->sPipeInfo_Planar.pu8FarmAddr + u32Offset); - u32Offset += ((psCcapConf->sPipeInfo_Planar.u32Height * psCcapConf->sPipeInfo_Planar.u32Width) / 2); + u32Offset += ((psCcapConf->sPipeInfo_Planar.u32Height * psCcapConf->sPipeInfo_Planar.u32Width) / u32Div); /* Set System Memory Planar V Base Address Register */ CCAP_SetPlanarVBuf(psNuCcap->base, (uint32_t)psCcapConf->sPipeInfo_Planar.pu8FarmAddr + u32Offset); @@ -258,6 +274,10 @@ static rt_err_t ccap_pipe_configure(nu_ccap_t psNuCcap, ccap_view_info_t psViewI u32PipeEnabling); return RT_EOK; + +fail_ccap_pipe_configure: + + return -RT_ERROR; } static rt_err_t ccap_open(rt_device_t dev, rt_uint16_t oflag) diff --git a/bsp/nuvoton/libraries/m460/rtt_port/drv_usbhost.c b/bsp/nuvoton/libraries/m460/rtt_port/drv_usbhost.c index 8d7d264f85..68c2116882 100644 --- a/bsp/nuvoton/libraries/m460/rtt_port/drv_usbhost.c +++ b/bsp/nuvoton/libraries/m460/rtt_port/drv_usbhost.c @@ -23,6 +23,13 @@ #include "usb.h" #include "usbh_lib.h" +#define LOG_TAG "drv.usbhost" +#define DBG_ENABLE +#define DBG_SECTION_NAME LOG_TAG +#define DBG_LEVEL LOG_LVL_DBG +#define DBG_COLOR +#include + #if !defined(NU_USBHOST_HUB_POLLING_INTERVAL) #define NU_USBHOST_HUB_POLLING_INTERVAL (100) #endif @@ -62,6 +69,7 @@ typedef struct nu_port_dev UDEV_T *pUDev; EP_INFO_T *apsEPInfo[NU_MAX_USBH_PIPE]; struct urequest asSetupReq[NU_MAX_USBH_PIPE]; + uint32_t u32SentLength[NU_MAX_USBH_PIPE]; struct rt_completion utr_completion; int port_num; rt_bool_t bEnumDone; @@ -445,22 +453,30 @@ static int nu_int_xfer( int timeouts) { int ret; - int retry = 3; - while (retry > 0) + while (1) { ret = usbh_int_xfer(psUTR); - if (ret == 0) + if (ret < 0) + return ret; + + if (rt_completion_wait(&(psPortDev->utr_completion), timeouts) != 0) + { + RT_DEBUG_LOG(RT_DEBUG_USB, ("Request %08x Timeout in %d ms!!\n", psUTR, timeouts)); + usbh_quit_utr(psUTR); + + rt_completion_init(&(psPortDev->utr_completion)); + rt_thread_mdelay(1); + } + else + { + + RT_DEBUG_LOG(RT_DEBUG_USB, ("Transferring done %08x\n", psUTR)); + usbh_quit_utr(psUTR); break; - - RT_DEBUG_LOG(RT_DEBUG_USB, ("nu_int_xfer ERROR: failed to submit interrupt request\n")); - rt_thread_delay((pipe->ep.bInterval * RT_TICK_PER_SECOND / 1000) > 0 ? (pipe->ep.bInterval * RT_TICK_PER_SECOND / 1000) : 1); - retry --; + } } - if (ret < 0) - return ret; - return 0; } @@ -472,30 +488,6 @@ static void xfer_done_cb(UTR_T *psUTR) rt_completion_done(&(psPortDev->utr_completion)); } -static void int_xfer_done_cb(UTR_T *psUTR) -{ - upipe_t pipe = (upipe_t)psUTR->context; - - if (psUTR->status != 0) - { - RT_DEBUG_LOG(RT_DEBUG_USB, ("Interrupt xfer failed %d\n", psUTR->status)); - goto exit_int_xfer_done_cb; - } - - if (pipe->callback != RT_NULL) - { - struct uhost_msg msg; - msg.type = USB_MSG_CALLBACK; - msg.content.cb.function = pipe->callback; - msg.content.cb.context = pipe; - rt_usbh_event_signal(&s_sUSBHDev.uhcd, &msg); - } - -exit_int_xfer_done_cb: - - free_utr(psUTR); -} - static int nu_pipe_xfer(upipe_t pipe, rt_uint8_t token, void *buffer, int nbytes, int timeouts) { S_NU_RH_PORT_CTRL *psPortCtrl; @@ -529,6 +521,7 @@ static int nu_pipe_xfer(upipe_t pipe, rt_uint8_t token, void *buffer, int nbytes { struct urequest *psSetup = (struct urequest *)buffer_nonch; RT_ASSERT(buffer_nonch != RT_NULL); + psPortCtrl->asHubPortDev->u32SentLength[pipe->pipe_index] = 0; /* Read data from USB device. */ if (psSetup->request_type & USB_REQ_TYPE_DIR_IN) @@ -550,10 +543,31 @@ static int nu_pipe_xfer(upipe_t pipe, rt_uint8_t token, void *buffer, int nbytes //token == USBH_PID_DATA if (buffer_nonch && ((pipe->ep.bEndpointAddress & USB_DIR_MASK) == USB_DIR_IN)) { + struct urequest *psSetup = &psPortCtrl->asHubPortDev->asSetupReq[pipe->pipe_index]; + /* Read data from USB device. */ //Trigger USBHostLib Ctril_Xfer - ret = nu_ctrl_xfer(psPortDev, &psPortCtrl->asHubPortDev->asSetupReq[pipe->pipe_index], buffer_nonch, timeouts); - if (ret != nbytes) + /* + * Workaround: HCD driver can readback all bytes of setup.wLength, but not support single packet transferring. + */ + if (psPortCtrl->asHubPortDev->u32SentLength[pipe->pipe_index] == 0) + { + ret = nu_ctrl_xfer(psPortDev, psSetup, buffer_nonch, timeouts); + psPortCtrl->asHubPortDev->u32SentLength[pipe->pipe_index] = ret; + } + else + { + if (psPortCtrl->asHubPortDev->u32SentLength[pipe->pipe_index] < nbytes) + { + ret = 0; + } + else + { + psPortCtrl->asHubPortDev->u32SentLength[pipe->pipe_index] -= nbytes; + ret = nbytes; + } + } + if (ret <= 0) goto exit_nu_pipe_xfer; } else @@ -598,9 +612,6 @@ static int nu_pipe_xfer(upipe_t pipe, rt_uint8_t token, void *buffer, int nbytes } else if (pipe->ep.bmAttributes == USB_EP_ATTR_INT) { - psUTR->func = int_xfer_done_cb; - psUTR->context = pipe; - if (nu_int_xfer(pipe, psPortDev, psUTR, timeouts) < 0) { RT_DEBUG_LOG(RT_DEBUG_USB, ("nu_pipe_xfer ERROR: int transfer failed\n")); @@ -610,7 +621,7 @@ static int nu_pipe_xfer(upipe_t pipe, rt_uint8_t token, void *buffer, int nbytes { i32XferLen = nbytes; } - goto exit2_nu_pipe_xfer; + goto exit_nu_pipe_xfer; } else if (pipe->ep.bmAttributes == USB_EP_ATTR_ISOC) { @@ -649,20 +660,17 @@ failreport_nu_pipe_xfer: i32XferLen = psUTR->xfer_len; +exit_nu_pipe_xfer: + //Call callback if (pipe->callback != RT_NULL) { pipe->callback(pipe); } -exit_nu_pipe_xfer: - if (psUTR) free_utr(psUTR); -exit2_nu_pipe_xfer: - - NU_USBHOST_UNLOCK(); return i32XferLen; @@ -859,7 +867,6 @@ int nu_usbh_register(void) { rt_err_t res; uhcd_t psUHCD; - uint32_t u32RegLockBackup; psUHCD = (uhcd_t)&s_sUSBHDev.uhcd; @@ -869,28 +876,32 @@ int nu_usbh_register(void) psUHCD->ops = &nu_uhcd_ops; psUHCD->num_ports = NU_MAX_USBH_PORT; + #if !defined(BSP_USING_HSOTG) - u32RegLockBackup = SYS_IsRegLocked(); - SYS_UnlockReg(); + { + uint32_t u32RegLockBackup; + + u32RegLockBackup = SYS_IsRegLocked(); + if (u32RegLockBackup) + SYS_UnlockReg(); #if defined(BSP_USING_HSUSBH) - /* Set USB Host role */ - SYS->USBPHY = (SYS->USBPHY & ~SYS_USBPHY_HSUSBROLE_Msk) | (0x1u << SYS_USBPHY_HSUSBROLE_Pos); - SYS->USBPHY |= SYS_USBPHY_HSUSBEN_Msk | SYS_USBPHY_SBO_Msk; - rt_thread_delay(20); - SYS->USBPHY |= SYS_USBPHY_HSUSBACT_Msk; - + /* Set USB Host role */ + SYS->USBPHY = (SYS->USBPHY & ~SYS_USBPHY_HSUSBROLE_Msk) | (0x1u << SYS_USBPHY_HSUSBROLE_Pos); + SYS->USBPHY |= SYS_USBPHY_HSUSBEN_Msk | SYS_USBPHY_SBO_Msk; + rt_thread_delay(20); + SYS->USBPHY |= SYS_USBPHY_HSUSBACT_Msk; #endif #if defined(BSP_USING_USBH) - /* Set USB Host role */ - SYS->USBPHY = (SYS->USBPHY & ~SYS_USBPHY_USBROLE_Msk) | (0x1u << SYS_USBPHY_USBROLE_Pos); - SYS->USBPHY |= SYS_USBPHY_USBEN_Msk | SYS_USBPHY_SBO_Msk ; + /* Set USB Host role */ + SYS->USBPHY = (SYS->USBPHY & ~SYS_USBPHY_USBROLE_Msk) | (0x1u << SYS_USBPHY_USBROLE_Pos); + SYS->USBPHY |= SYS_USBPHY_USBEN_Msk | SYS_USBPHY_SBO_Msk ; #endif - if (u32RegLockBackup) - SYS_LockReg(); - + if (u32RegLockBackup) + SYS_LockReg(); + } #endif @@ -909,6 +920,6 @@ int nu_usbh_register(void) return 0; } -INIT_DEVICE_EXPORT(nu_usbh_register); +INIT_APP_EXPORT(nu_usbh_register); #endif diff --git a/bsp/nuvoton/libraries/m480/rtt_port/drv_usbhost.c b/bsp/nuvoton/libraries/m480/rtt_port/drv_usbhost.c index 0df76a63ad..cf910fcc7e 100644 --- a/bsp/nuvoton/libraries/m480/rtt_port/drv_usbhost.c +++ b/bsp/nuvoton/libraries/m480/rtt_port/drv_usbhost.c @@ -23,6 +23,13 @@ #include "usb.h" #include "usbh_lib.h" +#define LOG_TAG "drv.usbhost" +#define DBG_ENABLE +#define DBG_SECTION_NAME LOG_TAG +#define DBG_LEVEL LOG_LVL_DBG +#define DBG_COLOR +#include + #if !defined(NU_USBHOST_HUB_POLLING_INTERVAL) #define NU_USBHOST_HUB_POLLING_INTERVAL (100) #endif @@ -62,6 +69,7 @@ typedef struct nu_port_dev UDEV_T *pUDev; EP_INFO_T *apsEPInfo[NU_MAX_USBH_PIPE]; struct urequest asSetupReq[NU_MAX_USBH_PIPE]; + uint32_t u32SentLength[NU_MAX_USBH_PIPE]; struct rt_completion utr_completion; int port_num; rt_bool_t bEnumDone; @@ -416,7 +424,6 @@ static int nu_bulk_xfer( rt_kprintf("psUTR->bIsTransferDone: %08x\n", psUTR->bIsTransferDone); rt_kprintf("psUTR->status: %08x\n", psUTR->status); rt_kprintf("psUTR->td_cnt: %08x\n", psUTR->td_cnt); - return -1; } return 0; @@ -429,22 +436,30 @@ static int nu_int_xfer( int timeouts) { int ret; - int retry = 3; - while (retry > 0) + while (1) { ret = usbh_int_xfer(psUTR); - if (ret == 0) + if (ret < 0) + return ret; + + if (rt_completion_wait(&(psPortDev->utr_completion), timeouts) != 0) + { + RT_DEBUG_LOG(RT_DEBUG_USB, ("Request %08x Timeout in %d ms!!\n", psUTR, timeouts)); + usbh_quit_utr(psUTR); + + rt_completion_init(&(psPortDev->utr_completion)); + rt_thread_mdelay(1); + } + else + { + + RT_DEBUG_LOG(RT_DEBUG_USB, ("Transferring done %08x\n", psUTR)); + usbh_quit_utr(psUTR); break; - - RT_DEBUG_LOG(RT_DEBUG_USB, ("nu_int_xfer ERROR: failed to submit interrupt request\n")); - rt_thread_delay((pipe->ep.bInterval * RT_TICK_PER_SECOND / 1000) > 0 ? (pipe->ep.bInterval * RT_TICK_PER_SECOND / 1000) : 1); - retry --; + } } - if (ret < 0) - return ret; - return 0; } @@ -456,30 +471,6 @@ static void xfer_done_cb(UTR_T *psUTR) rt_completion_done(&(psPortDev->utr_completion)); } -static void int_xfer_done_cb(UTR_T *psUTR) -{ - upipe_t pipe = (upipe_t)psUTR->context; - - if (psUTR->status != 0) - { - RT_DEBUG_LOG(RT_DEBUG_USB, ("Interrupt xfer failed %d\n", psUTR->status)); - goto exit_int_xfer_done_cb; - } - - if (pipe->callback != RT_NULL) - { - struct uhost_msg msg; - msg.type = USB_MSG_CALLBACK; - msg.content.cb.function = pipe->callback; - msg.content.cb.context = pipe; - rt_usbh_event_signal(&s_sUSBHDev.uhcd, &msg); - } - -exit_int_xfer_done_cb: - - free_utr(psUTR); -} - static int nu_pipe_xfer(upipe_t pipe, rt_uint8_t token, void *buffer, int nbytes, int timeouts) { S_NU_RH_PORT_CTRL *psPortCtrl; @@ -513,6 +504,7 @@ static int nu_pipe_xfer(upipe_t pipe, rt_uint8_t token, void *buffer, int nbytes { struct urequest *psSetup = (struct urequest *)buffer_nonch; RT_ASSERT(buffer_nonch != RT_NULL); + psPortCtrl->asHubPortDev->u32SentLength[pipe->pipe_index] = 0; /* Read data from USB device. */ if (psSetup->request_type & USB_REQ_TYPE_DIR_IN) @@ -534,10 +526,31 @@ static int nu_pipe_xfer(upipe_t pipe, rt_uint8_t token, void *buffer, int nbytes //token == USBH_PID_DATA if (buffer_nonch && ((pipe->ep.bEndpointAddress & USB_DIR_MASK) == USB_DIR_IN)) { + struct urequest *psSetup = &psPortCtrl->asHubPortDev->asSetupReq[pipe->pipe_index]; + /* Read data from USB device. */ //Trigger USBHostLib Ctril_Xfer - ret = nu_ctrl_xfer(psPortDev, &psPortCtrl->asHubPortDev->asSetupReq[pipe->pipe_index], buffer_nonch, timeouts); - if (ret != nbytes) + /* + * Workaround: HCD driver can readback all bytes of setup.wLength, but not support single packet transferring. + */ + if (psPortCtrl->asHubPortDev->u32SentLength[pipe->pipe_index] == 0) + { + ret = nu_ctrl_xfer(psPortDev, psSetup, buffer_nonch, timeouts); + psPortCtrl->asHubPortDev->u32SentLength[pipe->pipe_index] = ret; + } + else + { + if (psPortCtrl->asHubPortDev->u32SentLength[pipe->pipe_index] < nbytes) + { + ret = 0; + } + else + { + psPortCtrl->asHubPortDev->u32SentLength[pipe->pipe_index] -= nbytes; + ret = nbytes; + } + } + if (ret <= 0) goto exit_nu_pipe_xfer; } else @@ -582,9 +595,6 @@ static int nu_pipe_xfer(upipe_t pipe, rt_uint8_t token, void *buffer, int nbytes } else if (pipe->ep.bmAttributes == USB_EP_ATTR_INT) { - psUTR->func = int_xfer_done_cb; - psUTR->context = pipe; - if (nu_int_xfer(pipe, psPortDev, psUTR, timeouts) < 0) { RT_DEBUG_LOG(RT_DEBUG_USB, ("nu_pipe_xfer ERROR: int transfer failed\n")); @@ -594,7 +604,7 @@ static int nu_pipe_xfer(upipe_t pipe, rt_uint8_t token, void *buffer, int nbytes { i32XferLen = nbytes; } - goto exit2_nu_pipe_xfer; + goto exit_nu_pipe_xfer; } else if (pipe->ep.bmAttributes == USB_EP_ATTR_ISOC) { @@ -633,20 +643,17 @@ failreport_nu_pipe_xfer: i32XferLen = psUTR->xfer_len; +exit_nu_pipe_xfer: + //Call callback if (pipe->callback != RT_NULL) { pipe->callback(pipe); } -exit_nu_pipe_xfer: - if (psUTR) free_utr(psUTR); -exit2_nu_pipe_xfer: - - NU_USBHOST_UNLOCK(); return i32XferLen; @@ -852,25 +859,32 @@ int nu_usbh_register(void) psUHCD->ops = &nu_uhcd_ops; psUHCD->num_ports = NU_MAX_USBH_PORT; + #if !defined(BSP_USING_HSOTG) - SYS_UnlockReg(); + { + uint32_t u32RegLockBackup; + + u32RegLockBackup = SYS_IsRegLocked(); + if (u32RegLockBackup) + SYS_UnlockReg(); #if defined(BSP_USING_HSUSBH) - /* Set USB Host role */ - SYS->USBPHY = (SYS->USBPHY & ~SYS_USBPHY_HSUSBROLE_Msk) | (0x1u << SYS_USBPHY_HSUSBROLE_Pos); - SYS->USBPHY |= SYS_USBPHY_HSUSBEN_Msk | SYS_USBPHY_SBO_Msk; - rt_thread_delay(20); - SYS->USBPHY |= SYS_USBPHY_HSUSBACT_Msk; - + /* Set USB Host role */ + SYS->USBPHY = (SYS->USBPHY & ~SYS_USBPHY_HSUSBROLE_Msk) | (0x1u << SYS_USBPHY_HSUSBROLE_Pos); + SYS->USBPHY |= SYS_USBPHY_HSUSBEN_Msk | SYS_USBPHY_SBO_Msk; + rt_thread_delay(20); + SYS->USBPHY |= SYS_USBPHY_HSUSBACT_Msk; #endif #if defined(BSP_USING_USBH) - /* Set USB Host role */ - SYS->USBPHY = (SYS->USBPHY & ~SYS_USBPHY_USBROLE_Msk) | (0x1u << SYS_USBPHY_USBROLE_Pos); - SYS->USBPHY |= SYS_USBPHY_USBEN_Msk | SYS_USBPHY_SBO_Msk ; + /* Set USB Host role */ + SYS->USBPHY = (SYS->USBPHY & ~SYS_USBPHY_USBROLE_Msk) | (0x1u << SYS_USBPHY_USBROLE_Pos); + SYS->USBPHY |= SYS_USBPHY_USBEN_Msk | SYS_USBPHY_SBO_Msk ; #endif - SYS_LockReg(); + if (u32RegLockBackup) + SYS_LockReg(); + } #endif @@ -889,6 +903,6 @@ int nu_usbh_register(void) return 0; } -INIT_DEVICE_EXPORT(nu_usbh_register); +INIT_APP_EXPORT(nu_usbh_register); #endif diff --git a/bsp/nuvoton/libraries/ma35/CMSIS/Include/arm_common_tables.h b/bsp/nuvoton/libraries/ma35/CMSIS/Include/arm_common_tables.h new file mode 100644 index 0000000000..03153851b8 --- /dev/null +++ b/bsp/nuvoton/libraries/ma35/CMSIS/Include/arm_common_tables.h @@ -0,0 +1,136 @@ +/* ---------------------------------------------------------------------- +* Copyright (C) 2010-2014 ARM Limited. All rights reserved. +* +* $Date: 19. October 2015 +* $Revision: V.1.4.5 a +* +* Project: CMSIS DSP Library +* Title: arm_common_tables.h +* +* Description: This file has extern declaration for common tables like Bitreverse, reciprocal etc which are used across different functions +* +* Target Processor: Cortex-M4/Cortex-M3 +* +* Redistribution and use in source and binary forms, with or without +* modification, are permitted provided that the following conditions +* are met: +* - Redistributions of source code must retain the above copyright +* notice, this list of conditions and the following disclaimer. +* - Redistributions in binary form must reproduce the above copyright +* notice, this list of conditions and the following disclaimer in +* the documentation and/or other materials provided with the +* distribution. +* - Neither the name of ARM LIMITED nor the names of its contributors +* may be used to endorse or promote products derived from this +* software without specific prior written permission. +* +* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS +* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE +* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, +* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, +* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; +* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER +* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT +* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN +* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +* POSSIBILITY OF SUCH DAMAGE. +* -------------------------------------------------------------------- */ + +#ifndef _ARM_COMMON_TABLES_H +#define _ARM_COMMON_TABLES_H + +#include "arm_math.h" + +extern const uint16_t armBitRevTable[1024]; +extern const q15_t armRecipTableQ15[64]; +extern const q31_t armRecipTableQ31[64]; +/* extern const q31_t realCoefAQ31[1024]; */ +/* extern const q31_t realCoefBQ31[1024]; */ +extern const float32_t twiddleCoef_16[32]; +extern const float32_t twiddleCoef_32[64]; +extern const float32_t twiddleCoef_64[128]; +extern const float32_t twiddleCoef_128[256]; +extern const float32_t twiddleCoef_256[512]; +extern const float32_t twiddleCoef_512[1024]; +extern const float32_t twiddleCoef_1024[2048]; +extern const float32_t twiddleCoef_2048[4096]; +extern const float32_t twiddleCoef_4096[8192]; +#define twiddleCoef twiddleCoef_4096 +extern const q31_t twiddleCoef_16_q31[24]; +extern const q31_t twiddleCoef_32_q31[48]; +extern const q31_t twiddleCoef_64_q31[96]; +extern const q31_t twiddleCoef_128_q31[192]; +extern const q31_t twiddleCoef_256_q31[384]; +extern const q31_t twiddleCoef_512_q31[768]; +extern const q31_t twiddleCoef_1024_q31[1536]; +extern const q31_t twiddleCoef_2048_q31[3072]; +extern const q31_t twiddleCoef_4096_q31[6144]; +extern const q15_t twiddleCoef_16_q15[24]; +extern const q15_t twiddleCoef_32_q15[48]; +extern const q15_t twiddleCoef_64_q15[96]; +extern const q15_t twiddleCoef_128_q15[192]; +extern const q15_t twiddleCoef_256_q15[384]; +extern const q15_t twiddleCoef_512_q15[768]; +extern const q15_t twiddleCoef_1024_q15[1536]; +extern const q15_t twiddleCoef_2048_q15[3072]; +extern const q15_t twiddleCoef_4096_q15[6144]; +extern const float32_t twiddleCoef_rfft_32[32]; +extern const float32_t twiddleCoef_rfft_64[64]; +extern const float32_t twiddleCoef_rfft_128[128]; +extern const float32_t twiddleCoef_rfft_256[256]; +extern const float32_t twiddleCoef_rfft_512[512]; +extern const float32_t twiddleCoef_rfft_1024[1024]; +extern const float32_t twiddleCoef_rfft_2048[2048]; +extern const float32_t twiddleCoef_rfft_4096[4096]; + + +/* floating-point bit reversal tables */ +#define ARMBITREVINDEXTABLE__16_TABLE_LENGTH ((uint16_t)20 ) +#define ARMBITREVINDEXTABLE__32_TABLE_LENGTH ((uint16_t)48 ) +#define ARMBITREVINDEXTABLE__64_TABLE_LENGTH ((uint16_t)56 ) +#define ARMBITREVINDEXTABLE_128_TABLE_LENGTH ((uint16_t)208 ) +#define ARMBITREVINDEXTABLE_256_TABLE_LENGTH ((uint16_t)440 ) +#define ARMBITREVINDEXTABLE_512_TABLE_LENGTH ((uint16_t)448 ) +#define ARMBITREVINDEXTABLE1024_TABLE_LENGTH ((uint16_t)1800) +#define ARMBITREVINDEXTABLE2048_TABLE_LENGTH ((uint16_t)3808) +#define ARMBITREVINDEXTABLE4096_TABLE_LENGTH ((uint16_t)4032) + +extern const uint16_t armBitRevIndexTable16[ARMBITREVINDEXTABLE__16_TABLE_LENGTH]; +extern const uint16_t armBitRevIndexTable32[ARMBITREVINDEXTABLE__32_TABLE_LENGTH]; +extern const uint16_t armBitRevIndexTable64[ARMBITREVINDEXTABLE__64_TABLE_LENGTH]; +extern const uint16_t armBitRevIndexTable128[ARMBITREVINDEXTABLE_128_TABLE_LENGTH]; +extern const uint16_t armBitRevIndexTable256[ARMBITREVINDEXTABLE_256_TABLE_LENGTH]; +extern const uint16_t armBitRevIndexTable512[ARMBITREVINDEXTABLE_512_TABLE_LENGTH]; +extern const uint16_t armBitRevIndexTable1024[ARMBITREVINDEXTABLE1024_TABLE_LENGTH]; +extern const uint16_t armBitRevIndexTable2048[ARMBITREVINDEXTABLE2048_TABLE_LENGTH]; +extern const uint16_t armBitRevIndexTable4096[ARMBITREVINDEXTABLE4096_TABLE_LENGTH]; + +/* fixed-point bit reversal tables */ +#define ARMBITREVINDEXTABLE_FIXED___16_TABLE_LENGTH ((uint16_t)12 ) +#define ARMBITREVINDEXTABLE_FIXED___32_TABLE_LENGTH ((uint16_t)24 ) +#define ARMBITREVINDEXTABLE_FIXED___64_TABLE_LENGTH ((uint16_t)56 ) +#define ARMBITREVINDEXTABLE_FIXED__128_TABLE_LENGTH ((uint16_t)112 ) +#define ARMBITREVINDEXTABLE_FIXED__256_TABLE_LENGTH ((uint16_t)240 ) +#define ARMBITREVINDEXTABLE_FIXED__512_TABLE_LENGTH ((uint16_t)480 ) +#define ARMBITREVINDEXTABLE_FIXED_1024_TABLE_LENGTH ((uint16_t)992 ) +#define ARMBITREVINDEXTABLE_FIXED_2048_TABLE_LENGTH ((uint16_t)1984) +#define ARMBITREVINDEXTABLE_FIXED_4096_TABLE_LENGTH ((uint16_t)4032) + +extern const uint16_t armBitRevIndexTable_fixed_16[ARMBITREVINDEXTABLE_FIXED___16_TABLE_LENGTH]; +extern const uint16_t armBitRevIndexTable_fixed_32[ARMBITREVINDEXTABLE_FIXED___32_TABLE_LENGTH]; +extern const uint16_t armBitRevIndexTable_fixed_64[ARMBITREVINDEXTABLE_FIXED___64_TABLE_LENGTH]; +extern const uint16_t armBitRevIndexTable_fixed_128[ARMBITREVINDEXTABLE_FIXED__128_TABLE_LENGTH]; +extern const uint16_t armBitRevIndexTable_fixed_256[ARMBITREVINDEXTABLE_FIXED__256_TABLE_LENGTH]; +extern const uint16_t armBitRevIndexTable_fixed_512[ARMBITREVINDEXTABLE_FIXED__512_TABLE_LENGTH]; +extern const uint16_t armBitRevIndexTable_fixed_1024[ARMBITREVINDEXTABLE_FIXED_1024_TABLE_LENGTH]; +extern const uint16_t armBitRevIndexTable_fixed_2048[ARMBITREVINDEXTABLE_FIXED_2048_TABLE_LENGTH]; +extern const uint16_t armBitRevIndexTable_fixed_4096[ARMBITREVINDEXTABLE_FIXED_4096_TABLE_LENGTH]; + +/* Tables for Fast Math Sine and Cosine */ +extern const float32_t sinTable_f32[FAST_MATH_TABLE_SIZE + 1]; +extern const q31_t sinTable_q31[FAST_MATH_TABLE_SIZE + 1]; +extern const q15_t sinTable_q15[FAST_MATH_TABLE_SIZE + 1]; + +#endif /* ARM_COMMON_TABLES_H */ diff --git a/bsp/nuvoton/libraries/ma35/CMSIS/Include/arm_const_structs.h b/bsp/nuvoton/libraries/ma35/CMSIS/Include/arm_const_structs.h new file mode 100644 index 0000000000..4d02617344 --- /dev/null +++ b/bsp/nuvoton/libraries/ma35/CMSIS/Include/arm_const_structs.h @@ -0,0 +1,79 @@ +/* ---------------------------------------------------------------------- +* Copyright (C) 2010-2014 ARM Limited. All rights reserved. +* +* $Date: 19. March 2015 +* $Revision: V.1.4.5 +* +* Project: CMSIS DSP Library +* Title: arm_const_structs.h +* +* Description: This file has constant structs that are initialized for +* user convenience. For example, some can be given as +* arguments to the arm_cfft_f32() function. +* +* Target Processor: Cortex-M4/Cortex-M3 +* +* Redistribution and use in source and binary forms, with or without +* modification, are permitted provided that the following conditions +* are met: +* - Redistributions of source code must retain the above copyright +* notice, this list of conditions and the following disclaimer. +* - Redistributions in binary form must reproduce the above copyright +* notice, this list of conditions and the following disclaimer in +* the documentation and/or other materials provided with the +* distribution. +* - Neither the name of ARM LIMITED nor the names of its contributors +* may be used to endorse or promote products derived from this +* software without specific prior written permission. +* +* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS +* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE +* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, +* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, +* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; +* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER +* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT +* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN +* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +* POSSIBILITY OF SUCH DAMAGE. +* -------------------------------------------------------------------- */ + +#ifndef _ARM_CONST_STRUCTS_H +#define _ARM_CONST_STRUCTS_H + +#include "arm_math.h" +#include "arm_common_tables.h" + +extern const arm_cfft_instance_f32 arm_cfft_sR_f32_len16; +extern const arm_cfft_instance_f32 arm_cfft_sR_f32_len32; +extern const arm_cfft_instance_f32 arm_cfft_sR_f32_len64; +extern const arm_cfft_instance_f32 arm_cfft_sR_f32_len128; +extern const arm_cfft_instance_f32 arm_cfft_sR_f32_len256; +extern const arm_cfft_instance_f32 arm_cfft_sR_f32_len512; +extern const arm_cfft_instance_f32 arm_cfft_sR_f32_len1024; +extern const arm_cfft_instance_f32 arm_cfft_sR_f32_len2048; +extern const arm_cfft_instance_f32 arm_cfft_sR_f32_len4096; + +extern const arm_cfft_instance_q31 arm_cfft_sR_q31_len16; +extern const arm_cfft_instance_q31 arm_cfft_sR_q31_len32; +extern const arm_cfft_instance_q31 arm_cfft_sR_q31_len64; +extern const arm_cfft_instance_q31 arm_cfft_sR_q31_len128; +extern const arm_cfft_instance_q31 arm_cfft_sR_q31_len256; +extern const arm_cfft_instance_q31 arm_cfft_sR_q31_len512; +extern const arm_cfft_instance_q31 arm_cfft_sR_q31_len1024; +extern const arm_cfft_instance_q31 arm_cfft_sR_q31_len2048; +extern const arm_cfft_instance_q31 arm_cfft_sR_q31_len4096; + +extern const arm_cfft_instance_q15 arm_cfft_sR_q15_len16; +extern const arm_cfft_instance_q15 arm_cfft_sR_q15_len32; +extern const arm_cfft_instance_q15 arm_cfft_sR_q15_len64; +extern const arm_cfft_instance_q15 arm_cfft_sR_q15_len128; +extern const arm_cfft_instance_q15 arm_cfft_sR_q15_len256; +extern const arm_cfft_instance_q15 arm_cfft_sR_q15_len512; +extern const arm_cfft_instance_q15 arm_cfft_sR_q15_len1024; +extern const arm_cfft_instance_q15 arm_cfft_sR_q15_len2048; +extern const arm_cfft_instance_q15 arm_cfft_sR_q15_len4096; + +#endif diff --git a/bsp/nuvoton/libraries/ma35/CMSIS/Include/arm_math.h b/bsp/nuvoton/libraries/ma35/CMSIS/Include/arm_math.h new file mode 100644 index 0000000000..dd69a3e32f --- /dev/null +++ b/bsp/nuvoton/libraries/ma35/CMSIS/Include/arm_math.h @@ -0,0 +1,7154 @@ +/* ---------------------------------------------------------------------- +* Copyright (C) 2010-2015 ARM Limited. All rights reserved. +* +* $Date: 20. October 2015 +* $Revision: V1.4.5 b +* +* Project: CMSIS DSP Library +* Title: arm_math.h +* +* Description: Public header file for CMSIS DSP Library +* +* Target Processor: Cortex-M7/Cortex-M4/Cortex-M3/Cortex-M0 +* +* Redistribution and use in source and binary forms, with or without +* modification, are permitted provided that the following conditions +* are met: +* - Redistributions of source code must retain the above copyright +* notice, this list of conditions and the following disclaimer. +* - Redistributions in binary form must reproduce the above copyright +* notice, this list of conditions and the following disclaimer in +* the documentation and/or other materials provided with the +* distribution. +* - Neither the name of ARM LIMITED nor the names of its contributors +* may be used to endorse or promote products derived from this +* software without specific prior written permission. +* +* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS +* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE +* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, +* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, +* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; +* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER +* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT +* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN +* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +* POSSIBILITY OF SUCH DAMAGE. + * -------------------------------------------------------------------- */ + +/** + \mainpage CMSIS DSP Software Library + * + * Introduction + * ------------ + * + * This user manual describes the CMSIS DSP software library, + * a suite of common signal processing functions for use on Cortex-M processor based devices. + * + * The library is divided into a number of functions each covering a specific category: + * - Basic math functions + * - Fast math functions + * - Complex math functions + * - Filters + * - Matrix functions + * - Transforms + * - Motor control functions + * - Statistical functions + * - Support functions + * - Interpolation functions + * + * The library has separate functions for operating on 8-bit integers, 16-bit integers, + * 32-bit integer and 32-bit floating-point values. + * + * Using the Library + * ------------ + * + * The library installer contains prebuilt versions of the libraries in the Lib folder. + * - arm_cortexM7lfdp_math.lib (Little endian and Double Precision Floating Point Unit on Cortex-M7) + * - arm_cortexM7bfdp_math.lib (Big endian and Double Precision Floating Point Unit on Cortex-M7) + * - arm_cortexM7lfsp_math.lib (Little endian and Single Precision Floating Point Unit on Cortex-M7) + * - arm_cortexM7bfsp_math.lib (Big endian and Single Precision Floating Point Unit on Cortex-M7) + * - arm_cortexM7l_math.lib (Little endian on Cortex-M7) + * - arm_cortexM7b_math.lib (Big endian on Cortex-M7) + * - arm_cortexM4lf_math.lib (Little endian and Floating Point Unit on Cortex-M4) + * - arm_cortexM4bf_math.lib (Big endian and Floating Point Unit on Cortex-M4) + * - arm_cortexM4l_math.lib (Little endian on Cortex-M4) + * - arm_cortexM4b_math.lib (Big endian on Cortex-M4) + * - arm_cortexM3l_math.lib (Little endian on Cortex-M3) + * - arm_cortexM3b_math.lib (Big endian on Cortex-M3) + * - arm_cortexM0l_math.lib (Little endian on Cortex-M0 / CortexM0+) + * - arm_cortexM0b_math.lib (Big endian on Cortex-M0 / CortexM0+) + * + * The library functions are declared in the public file arm_math.h which is placed in the Include folder. + * Simply include this file and link the appropriate library in the application and begin calling the library functions. The Library supports single + * public header file arm_math.h for Cortex-M7/M4/M3/M0/M0+ with little endian and big endian. Same header file will be used for floating point unit(FPU) variants. + * Define the appropriate pre processor MACRO ARM_MATH_CM7 or ARM_MATH_CM4 or ARM_MATH_CM3 or + * ARM_MATH_CM0 or ARM_MATH_CM0PLUS depending on the target processor in the application. + * + * Examples + * -------- + * + * The library ships with a number of examples which demonstrate how to use the library functions. + * + * Toolchain Support + * ------------ + * + * The library has been developed and tested with MDK-ARM version 5.14.0.0 + * The library is being tested in GCC and IAR toolchains and updates on this activity will be made available shortly. + * + * Building the Library + * ------------ + * + * The library installer contains a project file to re build libraries on MDK-ARM Tool chain in the CMSIS\\DSP_Lib\\Source\\ARM folder. + * - arm_cortexM_math.uvprojx + * + * + * The libraries can be built by opening the arm_cortexM_math.uvprojx project in MDK-ARM, selecting a specific target, and defining the optional pre processor MACROs detailed above. + * + * Pre-processor Macros + * ------------ + * + * Each library project have differant pre-processor macros. + * + * - UNALIGNED_SUPPORT_DISABLE: + * + * Define macro UNALIGNED_SUPPORT_DISABLE, If the silicon does not support unaligned memory access + * + * - ARM_MATH_BIG_ENDIAN: + * + * Define macro ARM_MATH_BIG_ENDIAN to build the library for big endian targets. By default library builds for little endian targets. + * + * - ARM_MATH_MATRIX_CHECK: + * + * Define macro ARM_MATH_MATRIX_CHECK for checking on the input and output sizes of matrices + * + * - ARM_MATH_ROUNDING: + * + * Define macro ARM_MATH_ROUNDING for rounding on support functions + * + * - ARM_MATH_CMx: + * + * Define macro ARM_MATH_CM4 for building the library on Cortex-M4 target, ARM_MATH_CM3 for building library on Cortex-M3 target + * and ARM_MATH_CM0 for building library on Cortex-M0 target, ARM_MATH_CM0PLUS for building library on Cortex-M0+ target, and + * ARM_MATH_CM7 for building the library on cortex-M7. + * + * - __FPU_PRESENT: + * + * Initialize macro __FPU_PRESENT = 1 when building on FPU supported Targets. Enable this macro for M4bf and M4lf libraries + * + *
+ * CMSIS-DSP in ARM::CMSIS Pack + * ----------------------------- + * + * The following files relevant to CMSIS-DSP are present in the ARM::CMSIS Pack directories: + * |File/Folder |Content | + * |------------------------------|------------------------------------------------------------------------| + * |\b CMSIS\\Documentation\\DSP | This documentation | + * |\b CMSIS\\DSP_Lib | Software license agreement (license.txt) | + * |\b CMSIS\\DSP_Lib\\Examples | Example projects demonstrating the usage of the library functions | + * |\b CMSIS\\DSP_Lib\\Source | Source files for rebuilding the library | + * + *
+ * Revision History of CMSIS-DSP + * ------------ + * Please refer to \ref ChangeLog_pg. + * + * Copyright Notice + * ------------ + * + * Copyright (C) 2010-2015 ARM Limited. All rights reserved. + */ + + +/** + * @defgroup groupMath Basic Math Functions + */ + +/** + * @defgroup groupFastMath Fast Math Functions + * This set of functions provides a fast approximation to sine, cosine, and square root. + * As compared to most of the other functions in the CMSIS math library, the fast math functions + * operate on individual values and not arrays. + * There are separate functions for Q15, Q31, and floating-point data. + * + */ + +/** + * @defgroup groupCmplxMath Complex Math Functions + * This set of functions operates on complex data vectors. + * The data in the complex arrays is stored in an interleaved fashion + * (real, imag, real, imag, ...). + * In the API functions, the number of samples in a complex array refers + * to the number of complex values; the array contains twice this number of + * real values. + */ + +/** + * @defgroup groupFilters Filtering Functions + */ + +/** + * @defgroup groupMatrix Matrix Functions + * + * This set of functions provides basic matrix math operations. + * The functions operate on matrix data structures. For example, + * the type + * definition for the floating-point matrix structure is shown + * below: + * 
+ *     typedef struct
+ *     {
+ *       uint16_t numRows;     // number of rows of the matrix.
+ *       uint16_t numCols;     // number of columns of the matrix.
+ *       float32_t *pData;     // points to the data of the matrix.
+ *     } arm_matrix_instance_f32;
+ *
+ * There are similar definitions for Q15 and Q31 data types. + * + * The structure specifies the size of the matrix and then points to + * an array of data. The array is of size numRows X numCols + * and the values are arranged in row order. That is, the + * matrix element (i, j) is stored at: + * 
+ *     pData[i*numCols + j]
+ *
+ * + * \par Init Functions + * There is an associated initialization function for each type of matrix + * data structure. + * The initialization function sets the values of the internal structure fields. + * Refer to the function arm_mat_init_f32(), arm_mat_init_q31() + * and arm_mat_init_q15() for floating-point, Q31 and Q15 types, respectively. + * + * \par + * Use of the initialization function is optional. However, if initialization function is used + * then the instance structure cannot be placed into a const data section. + * To place the instance structure in a const data + * section, manually initialize the data structure. For example: + * 
+ * arm_matrix_instance_f32 S = {nRows, nColumns, pData};
+ * arm_matrix_instance_q31 S = {nRows, nColumns, pData};
+ * arm_matrix_instance_q15 S = {nRows, nColumns, pData};
+ *
+ * where nRows specifies the number of rows, nColumns + * specifies the number of columns, and pData points to the + * data array. + * + * \par Size Checking + * By default all of the matrix functions perform size checking on the input and + * output matrices. For example, the matrix addition function verifies that the + * two input matrices and the output matrix all have the same number of rows and + * columns. If the size check fails the functions return: + * 
+ *     ARM_MATH_SIZE_MISMATCH
+ *
+ * Otherwise the functions return + * 
+ *     ARM_MATH_SUCCESS
+ *
+ * There is some overhead associated with this matrix size checking. + * The matrix size checking is enabled via the \#define + * 
+ *     ARM_MATH_MATRIX_CHECK
+ *
+ * within the library project settings. By default this macro is defined + * and size checking is enabled. By changing the project settings and + * undefining this macro size checking is eliminated and the functions + * run a bit faster. With size checking disabled the functions always + * return ARM_MATH_SUCCESS. + */ + +/** + * @defgroup groupTransforms Transform Functions + */ + +/** + * @defgroup groupController Controller Functions + */ + +/** + * @defgroup groupStats Statistics Functions + */ +/** + * @defgroup groupSupport Support Functions + */ + +/** + * @defgroup groupInterpolation Interpolation Functions + * These functions perform 1- and 2-dimensional interpolation of data. + * Linear interpolation is used for 1-dimensional data and + * bilinear interpolation is used for 2-dimensional data. + */ + +/** + * @defgroup groupExamples Examples + */ +#ifndef _ARM_MATH_H +#define _ARM_MATH_H + +/* ignore some GCC warnings */ +#if defined ( __GNUC__ ) + #pragma GCC diagnostic push + #pragma GCC diagnostic ignored "-Wsign-conversion" + #pragma GCC diagnostic ignored "-Wconversion" + #pragma GCC diagnostic ignored "-Wunused-parameter" +#endif + +#define __CMSIS_GENERIC /* disable NVIC and Systick functions */ + +#if defined(ARM_MATH_CM7) + #include "core_cm7.h" +#elif defined (ARM_MATH_CM4) + #include "core_cm4.h" +#elif defined (ARM_MATH_CM3) + #include "core_cm3.h" +#elif defined (ARM_MATH_CM0) + #include "core_cm0.h" + #define ARM_MATH_CM0_FAMILY +#elif defined (ARM_MATH_CM0PLUS) + #include "core_cm0plus.h" + #define ARM_MATH_CM0_FAMILY +#else + #error "Define according the used Cortex core ARM_MATH_CM7, ARM_MATH_CM4, ARM_MATH_CM3, ARM_MATH_CM0PLUS or ARM_MATH_CM0" +#endif + +#undef __CMSIS_GENERIC /* enable NVIC and Systick functions */ +#include "string.h" +#include "math.h" +#ifdef __cplusplus +extern "C" +{ +#endif + + +/** + * @brief Macros required for reciprocal calculation in Normalized LMS + */ + +#define DELTA_Q31 (0x100) +#define DELTA_Q15 0x5 +#define INDEX_MASK 0x0000003F +#ifndef PI +#define PI 3.14159265358979f +#endif + +/** + * @brief Macros required for SINE and COSINE Fast math approximations + */ + +#define FAST_MATH_TABLE_SIZE 512 +#define FAST_MATH_Q31_SHIFT (32 - 10) +#define FAST_MATH_Q15_SHIFT (16 - 10) +#define CONTROLLER_Q31_SHIFT (32 - 9) +#define TABLE_SIZE 256 +#define TABLE_SPACING_Q31 0x400000 +#define TABLE_SPACING_Q15 0x80 + +/** + * @brief Macros required for SINE and COSINE Controller functions + */ +/* 1.31(q31) Fixed value of 2/360 */ +/* -1 to +1 is divided into 360 values so total spacing is (2/360) */ +#define INPUT_SPACING 0xB60B61 + +/** + * @brief Macro for Unaligned Support + */ +#ifndef UNALIGNED_SUPPORT_DISABLE +#define ALIGN4 +#else +#if defined (__GNUC__) +#define ALIGN4 __attribute__((aligned(4))) +#else +#define ALIGN4 __align(4) +#endif +#endif /* #ifndef UNALIGNED_SUPPORT_DISABLE */ + +/** + * @brief Error status returned by some functions in the library. + */ + +typedef enum +{ + ARM_MATH_SUCCESS = 0, /**< No error */ + ARM_MATH_ARGUMENT_ERROR = -1, /**< One or more arguments are incorrect */ + ARM_MATH_LENGTH_ERROR = -2, /**< Length of data buffer is incorrect */ + ARM_MATH_SIZE_MISMATCH = -3, /**< Size of matrices is not compatible with the operation. */ + ARM_MATH_NANINF = -4, /**< Not-a-number (NaN) or infinity is generated */ + ARM_MATH_SINGULAR = -5, /**< Generated by matrix inversion if the input matrix is singular and cannot be inverted. */ + ARM_MATH_TEST_FAILURE = -6 /**< Test Failed */ +} arm_status; + +/** + * @brief 8-bit fractional data type in 1.7 format. + */ +typedef int8_t q7_t; + +/** + * @brief 16-bit fractional data type in 1.15 format. + */ +typedef int16_t q15_t; + +/** + * @brief 32-bit fractional data type in 1.31 format. + */ +typedef int32_t q31_t; + +/** + * @brief 64-bit fractional data type in 1.63 format. + */ +typedef int64_t q63_t; + +/** + * @brief 32-bit floating-point type definition. + */ +typedef float float32_t; + +/** + * @brief 64-bit floating-point type definition. + */ +typedef double float64_t; + +/** + * @brief definition to read/write two 16 bit values. + */ +#if defined __CC_ARM +#define __SIMD32_TYPE int32_t __packed +#define CMSIS_UNUSED __attribute__((unused)) + +#elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) +#define __SIMD32_TYPE int32_t +#define CMSIS_UNUSED __attribute__((unused)) + +#elif defined __GNUC__ +#define __SIMD32_TYPE int32_t +#define CMSIS_UNUSED __attribute__((unused)) + +#elif defined __ICCARM__ +#define __SIMD32_TYPE int32_t __packed +#define CMSIS_UNUSED + +#elif defined __CSMC__ +#define __SIMD32_TYPE int32_t +#define CMSIS_UNUSED + +#elif defined __TASKING__ +#define __SIMD32_TYPE __unaligned int32_t +#define CMSIS_UNUSED + +#else +#error Unknown compiler +#endif + +#define __SIMD32(addr) (*(__SIMD32_TYPE **) & (addr)) +#define __SIMD32_CONST(addr) ((__SIMD32_TYPE *)(addr)) +#define _SIMD32_OFFSET(addr) (*(__SIMD32_TYPE *) (addr)) +#define __SIMD64(addr) (*(int64_t **) & (addr)) + +#if defined (ARM_MATH_CM3) || defined (ARM_MATH_CM0_FAMILY) +/** + * @brief definition to pack two 16 bit values. + */ +#define __PKHBT(ARG1, ARG2, ARG3) ( (((int32_t)(ARG1) << 0) & (int32_t)0x0000FFFF) | \ + (((int32_t)(ARG2) << ARG3) & (int32_t)0xFFFF0000) ) +#define __PKHTB(ARG1, ARG2, ARG3) ( (((int32_t)(ARG1) << 0) & (int32_t)0xFFFF0000) | \ + (((int32_t)(ARG2) >> ARG3) & (int32_t)0x0000FFFF) ) + +#endif + + +/** +* @brief definition to pack four 8 bit values. +*/ +#ifndef ARM_MATH_BIG_ENDIAN + +#define __PACKq7(v0,v1,v2,v3) ( (((int32_t)(v0) << 0) & (int32_t)0x000000FF) | \ + (((int32_t)(v1) << 8) & (int32_t)0x0000FF00) | \ + (((int32_t)(v2) << 16) & (int32_t)0x00FF0000) | \ + (((int32_t)(v3) << 24) & (int32_t)0xFF000000) ) +#else + +#define __PACKq7(v0,v1,v2,v3) ( (((int32_t)(v3) << 0) & (int32_t)0x000000FF) | \ + (((int32_t)(v2) << 8) & (int32_t)0x0000FF00) | \ + (((int32_t)(v1) << 16) & (int32_t)0x00FF0000) | \ + (((int32_t)(v0) << 24) & (int32_t)0xFF000000) ) + +#endif + + +/** + * @brief Clips Q63 to Q31 values. + */ +static __INLINE q31_t clip_q63_to_q31( + q63_t x) +{ + return ((q31_t)(x >> 32) != ((q31_t) x >> 31)) ? + ((0x7FFFFFFF ^ ((q31_t)(x >> 63)))) : (q31_t) x; +} + +/** + * @brief Clips Q63 to Q15 values. + */ +static __INLINE q15_t clip_q63_to_q15( + q63_t x) +{ + return ((q31_t)(x >> 32) != ((q31_t) x >> 31)) ? + ((0x7FFF ^ ((q15_t)(x >> 63)))) : (q15_t)(x >> 15); +} + +/** + * @brief Clips Q31 to Q7 values. + */ +static __INLINE q7_t clip_q31_to_q7( + q31_t x) +{ + return ((q31_t)(x >> 24) != ((q31_t) x >> 23)) ? + ((0x7F ^ ((q7_t)(x >> 31)))) : (q7_t) x; +} + +/** + * @brief Clips Q31 to Q15 values. + */ +static __INLINE q15_t clip_q31_to_q15( + q31_t x) +{ + return ((q31_t)(x >> 16) != ((q31_t) x >> 15)) ? + ((0x7FFF ^ ((q15_t)(x >> 31)))) : (q15_t) x; +} + +/** + * @brief Multiplies 32 X 64 and returns 32 bit result in 2.30 format. + */ + +static __INLINE q63_t mult32x64( + q63_t x, + q31_t y) +{ + return ((((q63_t)(x & 0x00000000FFFFFFFF) * y) >> 32) + + (((q63_t)(x >> 32) * y))); +} + +/* + #if defined (ARM_MATH_CM0_FAMILY) && defined ( __CC_ARM ) + #define __CLZ __clz + #endif + */ +/* note: function can be removed when all toolchain support __CLZ for Cortex-M0 */ +#if defined (ARM_MATH_CM0_FAMILY) && ((defined (__ICCARM__)) ) +static __INLINE uint32_t __CLZ( + q31_t data); + +static __INLINE uint32_t __CLZ( + q31_t data) +{ + uint32_t count = 0; + uint32_t mask = 0x80000000; + + while ((data & mask) == 0) + { + count += 1u; + mask = mask >> 1u; + } + + return (count); +} +#endif + +/** + * @brief Function to Calculates 1/in (reciprocal) value of Q31 Data type. + */ + +static __INLINE uint32_t arm_recip_q31( + q31_t in, + q31_t *dst, + q31_t *pRecipTable) +{ + q31_t out; + uint32_t tempVal; + uint32_t index, i; + uint32_t signBits; + + if (in > 0) + { + signBits = ((uint32_t)(__CLZ(in) - 1)); + } + else + { + signBits = ((uint32_t)(__CLZ(-in) - 1)); + } + + /* Convert input sample to 1.31 format */ + in = (in << signBits); + + /* calculation of index for initial approximated Val */ + index = (uint32_t)(in >> 24); + index = (index & INDEX_MASK); + + /* 1.31 with exp 1 */ + out = pRecipTable[index]; + + /* calculation of reciprocal value */ + /* running approximation for two iterations */ + for (i = 0u; i < 2u; i++) + { + tempVal = (uint32_t)(((q63_t) in * out) >> 31); + tempVal = 0x7FFFFFFFu - tempVal; + /* 1.31 with exp 1 */ + /* out = (q31_t) (((q63_t) out * tempVal) >> 30); */ + out = clip_q63_to_q31(((q63_t) out * tempVal) >> 30); + } + + /* write output */ + *dst = out; + + /* return num of signbits of out = 1/in value */ + return (signBits + 1u); +} + + +/** + * @brief Function to Calculates 1/in (reciprocal) value of Q15 Data type. + */ +static __INLINE uint32_t arm_recip_q15( + q15_t in, + q15_t *dst, + q15_t *pRecipTable) +{ + q15_t out = 0; + uint32_t tempVal = 0; + uint32_t index = 0, i = 0; + uint32_t signBits = 0; + + if (in > 0) + { + signBits = ((uint32_t)(__CLZ(in) - 17)); + } + else + { + signBits = ((uint32_t)(__CLZ(-in) - 17)); + } + + /* Convert input sample to 1.15 format */ + in = (in << signBits); + + /* calculation of index for initial approximated Val */ + index = (uint32_t)(in >> 8); + index = (index & INDEX_MASK); + + /* 1.15 with exp 1 */ + out = pRecipTable[index]; + + /* calculation of reciprocal value */ + /* running approximation for two iterations */ + for (i = 0u; i < 2u; i++) + { + tempVal = (uint32_t)(((q31_t) in * out) >> 15); + tempVal = 0x7FFFu - tempVal; + /* 1.15 with exp 1 */ + out = (q15_t)(((q31_t) out * tempVal) >> 14); + /* out = clip_q31_to_q15(((q31_t) out * tempVal) >> 14); */ + } + + /* write output */ + *dst = out; + + /* return num of signbits of out = 1/in value */ + return (signBits + 1); +} + + +/* + * @brief C custom defined intrinisic function for only M0 processors + */ +#if defined(ARM_MATH_CM0_FAMILY) +static __INLINE q31_t __SSAT( + q31_t x, + uint32_t y) +{ + int32_t posMax, negMin; + uint32_t i; + + posMax = 1; + for (i = 0; i < (y - 1); i++) + { + posMax = posMax * 2; + } + + if (x > 0) + { + posMax = (posMax - 1); + + if (x > posMax) + { + x = posMax; + } + } + else + { + negMin = -posMax; + + if (x < negMin) + { + x = negMin; + } + } + return (x); +} +#endif /* end of ARM_MATH_CM0_FAMILY */ + + +/* + * @brief C custom defined intrinsic function for M3 and M0 processors + */ +#if defined (ARM_MATH_CM3) || defined (ARM_MATH_CM0_FAMILY) + +/* + * @brief C custom defined QADD8 for M3 and M0 processors + */ +static __INLINE uint32_t __QADD8( + uint32_t x, + uint32_t y) +{ + q31_t r, s, t, u; + + r = __SSAT(((((q31_t)x << 24) >> 24) + (((q31_t)y << 24) >> 24)), 8) & (int32_t)0x000000FF; + s = __SSAT(((((q31_t)x << 16) >> 24) + (((q31_t)y << 16) >> 24)), 8) & (int32_t)0x000000FF; + t = __SSAT(((((q31_t)x << 8) >> 24) + (((q31_t)y << 8) >> 24)), 8) & (int32_t)0x000000FF; + u = __SSAT(((((q31_t)x) >> 24) + (((q31_t)y) >> 24)), 8) & (int32_t)0x000000FF; + + return ((uint32_t)((u << 24) | (t << 16) | (s << 8) | (r))); +} + + +/* + * @brief C custom defined QSUB8 for M3 and M0 processors + */ +static __INLINE uint32_t __QSUB8( + uint32_t x, + uint32_t y) +{ + q31_t r, s, t, u; + + r = __SSAT(((((q31_t)x << 24) >> 24) - (((q31_t)y << 24) >> 24)), 8) & (int32_t)0x000000FF; + s = __SSAT(((((q31_t)x << 16) >> 24) - (((q31_t)y << 16) >> 24)), 8) & (int32_t)0x000000FF; + t = __SSAT(((((q31_t)x << 8) >> 24) - (((q31_t)y << 8) >> 24)), 8) & (int32_t)0x000000FF; + u = __SSAT(((((q31_t)x) >> 24) - (((q31_t)y) >> 24)), 8) & (int32_t)0x000000FF; + + return ((uint32_t)((u << 24) | (t << 16) | (s << 8) | (r))); +} + + +/* + * @brief C custom defined QADD16 for M3 and M0 processors + */ +static __INLINE uint32_t __QADD16( + uint32_t x, + uint32_t y) +{ + /* q31_t r, s; without initialisation 'arm_offset_q15 test' fails but 'intrinsic' tests pass! for armCC */ + q31_t r = 0, s = 0; + + r = __SSAT(((((q31_t)x << 16) >> 16) + (((q31_t)y << 16) >> 16)), 16) & (int32_t)0x0000FFFF; + s = __SSAT(((((q31_t)x) >> 16) + (((q31_t)y) >> 16)), 16) & (int32_t)0x0000FFFF; + + return ((uint32_t)((s << 16) | (r))); +} + + +/* + * @brief C custom defined SHADD16 for M3 and M0 processors + */ +static __INLINE uint32_t __SHADD16( + uint32_t x, + uint32_t y) +{ + q31_t r, s; + + r = (((((q31_t)x << 16) >> 16) + (((q31_t)y << 16) >> 16)) >> 1) & (int32_t)0x0000FFFF; + s = (((((q31_t)x) >> 16) + (((q31_t)y) >> 16)) >> 1) & (int32_t)0x0000FFFF; + + return ((uint32_t)((s << 16) | (r))); +} + + +/* + * @brief C custom defined QSUB16 for M3 and M0 processors + */ +static __INLINE uint32_t __QSUB16( + uint32_t x, + uint32_t y) +{ + q31_t r, s; + + r = __SSAT(((((q31_t)x << 16) >> 16) - (((q31_t)y << 16) >> 16)), 16) & (int32_t)0x0000FFFF; + s = __SSAT(((((q31_t)x) >> 16) - (((q31_t)y) >> 16)), 16) & (int32_t)0x0000FFFF; + + return ((uint32_t)((s << 16) | (r))); +} + + +/* + * @brief C custom defined SHSUB16 for M3 and M0 processors + */ +static __INLINE uint32_t __SHSUB16( + uint32_t x, + uint32_t y) +{ + q31_t r, s; + + r = (((((q31_t)x << 16) >> 16) - (((q31_t)y << 16) >> 16)) >> 1) & (int32_t)0x0000FFFF; + s = (((((q31_t)x) >> 16) - (((q31_t)y) >> 16)) >> 1) & (int32_t)0x0000FFFF; + + return ((uint32_t)((s << 16) | (r))); +} + + +/* + * @brief C custom defined QASX for M3 and M0 processors + */ +static __INLINE uint32_t __QASX( + uint32_t x, + uint32_t y) +{ + q31_t r, s; + + r = __SSAT(((((q31_t)x << 16) >> 16) - (((q31_t)y) >> 16)), 16) & (int32_t)0x0000FFFF; + s = __SSAT(((((q31_t)x) >> 16) + (((q31_t)y << 16) >> 16)), 16) & (int32_t)0x0000FFFF; + + return ((uint32_t)((s << 16) | (r))); +} + + +/* + * @brief C custom defined SHASX for M3 and M0 processors + */ +static __INLINE uint32_t __SHASX( + uint32_t x, + uint32_t y) +{ + q31_t r, s; + + r = (((((q31_t)x << 16) >> 16) - (((q31_t)y) >> 16)) >> 1) & (int32_t)0x0000FFFF; + s = (((((q31_t)x) >> 16) + (((q31_t)y << 16) >> 16)) >> 1) & (int32_t)0x0000FFFF; + + return ((uint32_t)((s << 16) | (r))); +} + + +/* + * @brief C custom defined QSAX for M3 and M0 processors + */ +static __INLINE uint32_t __QSAX( + uint32_t x, + uint32_t y) +{ + q31_t r, s; + + r = __SSAT(((((q31_t)x << 16) >> 16) + (((q31_t)y) >> 16)), 16) & (int32_t)0x0000FFFF; + s = __SSAT(((((q31_t)x) >> 16) - (((q31_t)y << 16) >> 16)), 16) & (int32_t)0x0000FFFF; + + return ((uint32_t)((s << 16) | (r))); +} + + +/* + * @brief C custom defined SHSAX for M3 and M0 processors + */ +static __INLINE uint32_t __SHSAX( + uint32_t x, + uint32_t y) +{ + q31_t r, s; + + r = (((((q31_t)x << 16) >> 16) + (((q31_t)y) >> 16)) >> 1) & (int32_t)0x0000FFFF; + s = (((((q31_t)x) >> 16) - (((q31_t)y << 16) >> 16)) >> 1) & (int32_t)0x0000FFFF; + + return ((uint32_t)((s << 16) | (r))); +} + + +/* + * @brief C custom defined SMUSDX for M3 and M0 processors + */ +static __INLINE uint32_t __SMUSDX( + uint32_t x, + uint32_t y) +{ + return ((uint32_t)(((((q31_t)x << 16) >> 16) * (((q31_t)y) >> 16)) - + ((((q31_t)x) >> 16) * (((q31_t)y << 16) >> 16)))); +} + +/* + * @brief C custom defined SMUADX for M3 and M0 processors + */ +static __INLINE uint32_t __SMUADX( + uint32_t x, + uint32_t y) +{ + return ((uint32_t)(((((q31_t)x << 16) >> 16) * (((q31_t)y) >> 16)) + + ((((q31_t)x) >> 16) * (((q31_t)y << 16) >> 16)))); +} + + +/* + * @brief C custom defined QADD for M3 and M0 processors + */ +static __INLINE int32_t __QADD( + int32_t x, + int32_t y) +{ + return ((int32_t)(clip_q63_to_q31((q63_t)x + (q31_t)y))); +} + + +/* + * @brief C custom defined QSUB for M3 and M0 processors + */ +static __INLINE int32_t __QSUB( + int32_t x, + int32_t y) +{ + return ((int32_t)(clip_q63_to_q31((q63_t)x - (q31_t)y))); +} + + +/* + * @brief C custom defined SMLAD for M3 and M0 processors + */ +static __INLINE uint32_t __SMLAD( + uint32_t x, + uint32_t y, + uint32_t sum) +{ + return ((uint32_t)(((((q31_t)x << 16) >> 16) * (((q31_t)y << 16) >> 16)) + + ((((q31_t)x) >> 16) * (((q31_t)y) >> 16)) + + (((q31_t)sum)))); +} + + +/* + * @brief C custom defined SMLADX for M3 and M0 processors + */ +static __INLINE uint32_t __SMLADX( + uint32_t x, + uint32_t y, + uint32_t sum) +{ + return ((uint32_t)(((((q31_t)x << 16) >> 16) * (((q31_t)y) >> 16)) + + ((((q31_t)x) >> 16) * (((q31_t)y << 16) >> 16)) + + (((q31_t)sum)))); +} + + +/* + * @brief C custom defined SMLSDX for M3 and M0 processors + */ +static __INLINE uint32_t __SMLSDX( + uint32_t x, + uint32_t y, + uint32_t sum) +{ + return ((uint32_t)(((((q31_t)x << 16) >> 16) * (((q31_t)y) >> 16)) - + ((((q31_t)x) >> 16) * (((q31_t)y << 16) >> 16)) + + (((q31_t)sum)))); +} + + +/* + * @brief C custom defined SMLALD for M3 and M0 processors + */ +static __INLINE uint64_t __SMLALD( + uint32_t x, + uint32_t y, + uint64_t sum) +{ + /* return (sum + ((q15_t) (x >> 16) * (q15_t) (y >> 16)) + ((q15_t) x * (q15_t) y)); */ + return ((uint64_t)(((((q31_t)x << 16) >> 16) * (((q31_t)y << 16) >> 16)) + + ((((q31_t)x) >> 16) * (((q31_t)y) >> 16)) + + (((q63_t)sum)))); +} + + +/* + * @brief C custom defined SMLALDX for M3 and M0 processors + */ +static __INLINE uint64_t __SMLALDX( + uint32_t x, + uint32_t y, + uint64_t sum) +{ + /* return (sum + ((q15_t) (x >> 16) * (q15_t) y)) + ((q15_t) x * (q15_t) (y >> 16)); */ + return ((uint64_t)(((((q31_t)x << 16) >> 16) * (((q31_t)y) >> 16)) + + ((((q31_t)x) >> 16) * (((q31_t)y << 16) >> 16)) + + (((q63_t)sum)))); +} + + +/* + * @brief C custom defined SMUAD for M3 and M0 processors + */ +static __INLINE uint32_t __SMUAD( + uint32_t x, + uint32_t y) +{ + return ((uint32_t)(((((q31_t)x << 16) >> 16) * (((q31_t)y << 16) >> 16)) + + ((((q31_t)x) >> 16) * (((q31_t)y) >> 16)))); +} + + +/* + * @brief C custom defined SMUSD for M3 and M0 processors + */ +static __INLINE uint32_t __SMUSD( + uint32_t x, + uint32_t y) +{ + return ((uint32_t)(((((q31_t)x << 16) >> 16) * (((q31_t)y << 16) >> 16)) - + ((((q31_t)x) >> 16) * (((q31_t)y) >> 16)))); +} + + +/* + * @brief C custom defined SXTB16 for M3 and M0 processors + */ +static __INLINE uint32_t __SXTB16( + uint32_t x) +{ + return ((uint32_t)(((((q31_t)x << 24) >> 24) & (q31_t)0x0000FFFF) | + ((((q31_t)x << 8) >> 8) & (q31_t)0xFFFF0000))); +} + +#endif /* defined (ARM_MATH_CM3) || defined (ARM_MATH_CM0_FAMILY) */ + + +/** + * @brief Instance structure for the Q7 FIR filter. + */ +typedef struct +{ + uint16_t numTaps; /**< number of filter coefficients in the filter. */ + q7_t *pState; /**< points to the state variable array. The array is of length numTaps+blockSize-1. */ + q7_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps.*/ +} arm_fir_instance_q7; + +/** + * @brief Instance structure for the Q15 FIR filter. + */ +typedef struct +{ + uint16_t numTaps; /**< number of filter coefficients in the filter. */ + q15_t *pState; /**< points to the state variable array. The array is of length numTaps+blockSize-1. */ + q15_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps.*/ +} arm_fir_instance_q15; + +/** + * @brief Instance structure for the Q31 FIR filter. + */ +typedef struct +{ + uint16_t numTaps; /**< number of filter coefficients in the filter. */ + q31_t *pState; /**< points to the state variable array. The array is of length numTaps+blockSize-1. */ + q31_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps. */ +} arm_fir_instance_q31; + +/** + * @brief Instance structure for the floating-point FIR filter. + */ +typedef struct +{ + uint16_t numTaps; /**< number of filter coefficients in the filter. */ + float32_t *pState; /**< points to the state variable array. The array is of length numTaps+blockSize-1. */ + float32_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps. */ +} arm_fir_instance_f32; + + +/** + * @brief Processing function for the Q7 FIR filter. + * @param[in] S points to an instance of the Q7 FIR filter structure. + * @param[in] pSrc points to the block of input data. + * @param[out] pDst points to the block of output data. + * @param[in] blockSize number of samples to process. + */ +void arm_fir_q7( + const arm_fir_instance_q7 *S, + q7_t *pSrc, + q7_t *pDst, + uint32_t blockSize); + + +/** + * @brief Initialization function for the Q7 FIR filter. + * @param[in,out] S points to an instance of the Q7 FIR structure. + * @param[in] numTaps Number of filter coefficients in the filter. + * @param[in] pCoeffs points to the filter coefficients. + * @param[in] pState points to the state buffer. + * @param[in] blockSize number of samples that are processed. + */ +void arm_fir_init_q7( + arm_fir_instance_q7 *S, + uint16_t numTaps, + q7_t *pCoeffs, + q7_t *pState, + uint32_t blockSize); + + +/** + * @brief Processing function for the Q15 FIR filter. + * @param[in] S points to an instance of the Q15 FIR structure. + * @param[in] pSrc points to the block of input data. + * @param[out] pDst points to the block of output data. + * @param[in] blockSize number of samples to process. + */ +void arm_fir_q15( + const arm_fir_instance_q15 *S, + q15_t *pSrc, + q15_t *pDst, + uint32_t blockSize); + + +/** + * @brief Processing function for the fast Q15 FIR filter for Cortex-M3 and Cortex-M4. + * @param[in] S points to an instance of the Q15 FIR filter structure. + * @param[in] pSrc points to the block of input data. + * @param[out] pDst points to the block of output data. + * @param[in] blockSize number of samples to process. + */ +void arm_fir_fast_q15( + const arm_fir_instance_q15 *S, + q15_t *pSrc, + q15_t *pDst, + uint32_t blockSize); + + +/** + * @brief Initialization function for the Q15 FIR filter. + * @param[in,out] S points to an instance of the Q15 FIR filter structure. + * @param[in] numTaps Number of filter coefficients in the filter. Must be even and greater than or equal to 4. + * @param[in] pCoeffs points to the filter coefficients. + * @param[in] pState points to the state buffer. + * @param[in] blockSize number of samples that are processed at a time. + * @return The function returns ARM_MATH_SUCCESS if initialization was successful or ARM_MATH_ARGUMENT_ERROR if + * numTaps is not a supported value. + */ +arm_status arm_fir_init_q15( + arm_fir_instance_q15 *S, + uint16_t numTaps, + q15_t *pCoeffs, + q15_t *pState, + uint32_t blockSize); + + +/** + * @brief Processing function for the Q31 FIR filter. + * @param[in] S points to an instance of the Q31 FIR filter structure. + * @param[in] pSrc points to the block of input data. + * @param[out] pDst points to the block of output data. + * @param[in] blockSize number of samples to process. + */ +void arm_fir_q31( + const arm_fir_instance_q31 *S, + q31_t *pSrc, + q31_t *pDst, + uint32_t blockSize); + + +/** + * @brief Processing function for the fast Q31 FIR filter for Cortex-M3 and Cortex-M4. + * @param[in] S points to an instance of the Q31 FIR structure. + * @param[in] pSrc points to the block of input data. + * @param[out] pDst points to the block of output data. + * @param[in] blockSize number of samples to process. + */ +void arm_fir_fast_q31( + const arm_fir_instance_q31 *S, + q31_t *pSrc, + q31_t *pDst, + uint32_t blockSize); + + +/** + * @brief Initialization function for the Q31 FIR filter. + * @param[in,out] S points to an instance of the Q31 FIR structure. + * @param[in] numTaps Number of filter coefficients in the filter. + * @param[in] pCoeffs points to the filter coefficients. + * @param[in] pState points to the state buffer. + * @param[in] blockSize number of samples that are processed at a time. + */ +void arm_fir_init_q31( + arm_fir_instance_q31 *S, + uint16_t numTaps, + q31_t *pCoeffs, + q31_t *pState, + uint32_t blockSize); + + +/** + * @brief Processing function for the floating-point FIR filter. + * @param[in] S points to an instance of the floating-point FIR structure. + * @param[in] pSrc points to the block of input data. + * @param[out] pDst points to the block of output data. + * @param[in] blockSize number of samples to process. + */ +void arm_fir_f32( + const arm_fir_instance_f32 *S, + float32_t *pSrc, + float32_t *pDst, + uint32_t blockSize); + + +/** + * @brief Initialization function for the floating-point FIR filter. + * @param[in,out] S points to an instance of the floating-point FIR filter structure. + * @param[in] numTaps Number of filter coefficients in the filter. + * @param[in] pCoeffs points to the filter coefficients. + * @param[in] pState points to the state buffer. + * @param[in] blockSize number of samples that are processed at a time. + */ +void arm_fir_init_f32( + arm_fir_instance_f32 *S, + uint16_t numTaps, + float32_t *pCoeffs, + float32_t *pState, + uint32_t blockSize); + + +/** + * @brief Instance structure for the Q15 Biquad cascade filter. + */ +typedef struct +{ + int8_t numStages; /**< number of 2nd order stages in the filter. Overall order is 2*numStages. */ + q15_t *pState; /**< Points to the array of state coefficients. The array is of length 4*numStages. */ + q15_t *pCoeffs; /**< Points to the array of coefficients. The array is of length 5*numStages. */ + int8_t postShift; /**< Additional shift, in bits, applied to each output sample. */ +} arm_biquad_casd_df1_inst_q15; + +/** + * @brief Instance structure for the Q31 Biquad cascade filter. + */ +typedef struct +{ + uint32_t numStages; /**< number of 2nd order stages in the filter. Overall order is 2*numStages. */ + q31_t *pState; /**< Points to the array of state coefficients. The array is of length 4*numStages. */ + q31_t *pCoeffs; /**< Points to the array of coefficients. The array is of length 5*numStages. */ + uint8_t postShift; /**< Additional shift, in bits, applied to each output sample. */ +} arm_biquad_casd_df1_inst_q31; + +/** + * @brief Instance structure for the floating-point Biquad cascade filter. + */ +typedef struct +{ + uint32_t numStages; /**< number of 2nd order stages in the filter. Overall order is 2*numStages. */ + float32_t *pState; /**< Points to the array of state coefficients. The array is of length 4*numStages. */ + float32_t *pCoeffs; /**< Points to the array of coefficients. The array is of length 5*numStages. */ +} arm_biquad_casd_df1_inst_f32; + + +/** + * @brief Processing function for the Q15 Biquad cascade filter. + * @param[in] S points to an instance of the Q15 Biquad cascade structure. + * @param[in] pSrc points to the block of input data. + * @param[out] pDst points to the block of output data. + * @param[in] blockSize number of samples to process. + */ +void arm_biquad_cascade_df1_q15( + const arm_biquad_casd_df1_inst_q15 *S, + q15_t *pSrc, + q15_t *pDst, + uint32_t blockSize); + + +/** + * @brief Initialization function for the Q15 Biquad cascade filter. + * @param[in,out] S points to an instance of the Q15 Biquad cascade structure. + * @param[in] numStages number of 2nd order stages in the filter. + * @param[in] pCoeffs points to the filter coefficients. + * @param[in] pState points to the state buffer. + * @param[in] postShift Shift to be applied to the output. Varies according to the coefficients format + */ +void arm_biquad_cascade_df1_init_q15( + arm_biquad_casd_df1_inst_q15 *S, + uint8_t numStages, + q15_t *pCoeffs, + q15_t *pState, + int8_t postShift); + + +/** + * @brief Fast but less precise processing function for the Q15 Biquad cascade filter for Cortex-M3 and Cortex-M4. + * @param[in] S points to an instance of the Q15 Biquad cascade structure. + * @param[in] pSrc points to the block of input data. + * @param[out] pDst points to the block of output data. + * @param[in] blockSize number of samples to process. + */ +void arm_biquad_cascade_df1_fast_q15( + const arm_biquad_casd_df1_inst_q15 *S, + q15_t *pSrc, + q15_t *pDst, + uint32_t blockSize); + + +/** + * @brief Processing function for the Q31 Biquad cascade filter + * @param[in] S points to an instance of the Q31 Biquad cascade structure. + * @param[in] pSrc points to the block of input data. + * @param[out] pDst points to the block of output data. + * @param[in] blockSize number of samples to process. + */ +void arm_biquad_cascade_df1_q31( + const arm_biquad_casd_df1_inst_q31 *S, + q31_t *pSrc, + q31_t *pDst, + uint32_t blockSize); + + +/** + * @brief Fast but less precise processing function for the Q31 Biquad cascade filter for Cortex-M3 and Cortex-M4. + * @param[in] S points to an instance of the Q31 Biquad cascade structure. + * @param[in] pSrc points to the block of input data. + * @param[out] pDst points to the block of output data. + * @param[in] blockSize number of samples to process. + */ +void arm_biquad_cascade_df1_fast_q31( + const arm_biquad_casd_df1_inst_q31 *S, + q31_t *pSrc, + q31_t *pDst, + uint32_t blockSize); + + +/** + * @brief Initialization function for the Q31 Biquad cascade filter. + * @param[in,out] S points to an instance of the Q31 Biquad cascade structure. + * @param[in] numStages number of 2nd order stages in the filter. + * @param[in] pCoeffs points to the filter coefficients. + * @param[in] pState points to the state buffer. + * @param[in] postShift Shift to be applied to the output. Varies according to the coefficients format + */ +void arm_biquad_cascade_df1_init_q31( + arm_biquad_casd_df1_inst_q31 *S, + uint8_t numStages, + q31_t *pCoeffs, + q31_t *pState, + int8_t postShift); + + +/** + * @brief Processing function for the floating-point Biquad cascade filter. + * @param[in] S points to an instance of the floating-point Biquad cascade structure. + * @param[in] pSrc points to the block of input data. + * @param[out] pDst points to the block of output data. + * @param[in] blockSize number of samples to process. + */ +void arm_biquad_cascade_df1_f32( + const arm_biquad_casd_df1_inst_f32 *S, + float32_t *pSrc, + float32_t *pDst, + uint32_t blockSize); + + +/** + * @brief Initialization function for the floating-point Biquad cascade filter. + * @param[in,out] S points to an instance of the floating-point Biquad cascade structure. + * @param[in] numStages number of 2nd order stages in the filter. + * @param[in] pCoeffs points to the filter coefficients. + * @param[in] pState points to the state buffer. + */ +void arm_biquad_cascade_df1_init_f32( + arm_biquad_casd_df1_inst_f32 *S, + uint8_t numStages, + float32_t *pCoeffs, + float32_t *pState); + + +/** + * @brief Instance structure for the floating-point matrix structure. + */ +typedef struct +{ + uint16_t numRows; /**< number of rows of the matrix. */ + uint16_t numCols; /**< number of columns of the matrix. */ + float32_t *pData; /**< points to the data of the matrix. */ +} arm_matrix_instance_f32; + + +/** + * @brief Instance structure for the floating-point matrix structure. + */ +typedef struct +{ + uint16_t numRows; /**< number of rows of the matrix. */ + uint16_t numCols; /**< number of columns of the matrix. */ + float64_t *pData; /**< points to the data of the matrix. */ +} arm_matrix_instance_f64; + +/** + * @brief Instance structure for the Q15 matrix structure. + */ +typedef struct +{ + uint16_t numRows; /**< number of rows of the matrix. */ + uint16_t numCols; /**< number of columns of the matrix. */ + q15_t *pData; /**< points to the data of the matrix. */ +} arm_matrix_instance_q15; + +/** + * @brief Instance structure for the Q31 matrix structure. + */ +typedef struct +{ + uint16_t numRows; /**< number of rows of the matrix. */ + uint16_t numCols; /**< number of columns of the matrix. */ + q31_t *pData; /**< points to the data of the matrix. */ +} arm_matrix_instance_q31; + + +/** + * @brief Floating-point matrix addition. + * @param[in] pSrcA points to the first input matrix structure + * @param[in] pSrcB points to the second input matrix structure + * @param[out] pDst points to output matrix structure + * @return The function returns either + * ARM_MATH_SIZE_MISMATCH or ARM_MATH_SUCCESS based on the outcome of size checking. + */ +arm_status arm_mat_add_f32( + const arm_matrix_instance_f32 *pSrcA, + const arm_matrix_instance_f32 *pSrcB, + arm_matrix_instance_f32 *pDst); + + +/** + * @brief Q15 matrix addition. + * @param[in] pSrcA points to the first input matrix structure + * @param[in] pSrcB points to the second input matrix structure + * @param[out] pDst points to output matrix structure + * @return The function returns either + * ARM_MATH_SIZE_MISMATCH or ARM_MATH_SUCCESS based on the outcome of size checking. + */ +arm_status arm_mat_add_q15( + const arm_matrix_instance_q15 *pSrcA, + const arm_matrix_instance_q15 *pSrcB, + arm_matrix_instance_q15 *pDst); + + +/** + * @brief Q31 matrix addition. + * @param[in] pSrcA points to the first input matrix structure + * @param[in] pSrcB points to the second input matrix structure + * @param[out] pDst points to output matrix structure + * @return The function returns either + * ARM_MATH_SIZE_MISMATCH or ARM_MATH_SUCCESS based on the outcome of size checking. + */ +arm_status arm_mat_add_q31( + const arm_matrix_instance_q31 *pSrcA, + const arm_matrix_instance_q31 *pSrcB, + arm_matrix_instance_q31 *pDst); + + +/** + * @brief Floating-point, complex, matrix multiplication. + * @param[in] pSrcA points to the first input matrix structure + * @param[in] pSrcB points to the second input matrix structure + * @param[out] pDst points to output matrix structure + * @return The function returns either + * ARM_MATH_SIZE_MISMATCH or ARM_MATH_SUCCESS based on the outcome of size checking. + */ +arm_status arm_mat_cmplx_mult_f32( + const arm_matrix_instance_f32 *pSrcA, + const arm_matrix_instance_f32 *pSrcB, + arm_matrix_instance_f32 *pDst); + + +/** + * @brief Q15, complex, matrix multiplication. + * @param[in] pSrcA points to the first input matrix structure + * @param[in] pSrcB points to the second input matrix structure + * @param[out] pDst points to output matrix structure + * @return The function returns either + * ARM_MATH_SIZE_MISMATCH or ARM_MATH_SUCCESS based on the outcome of size checking. + */ +arm_status arm_mat_cmplx_mult_q15( + const arm_matrix_instance_q15 *pSrcA, + const arm_matrix_instance_q15 *pSrcB, + arm_matrix_instance_q15 *pDst, + q15_t *pScratch); + + +/** + * @brief Q31, complex, matrix multiplication. + * @param[in] pSrcA points to the first input matrix structure + * @param[in] pSrcB points to the second input matrix structure + * @param[out] pDst points to output matrix structure + * @return The function returns either + * ARM_MATH_SIZE_MISMATCH or ARM_MATH_SUCCESS based on the outcome of size checking. + */ +arm_status arm_mat_cmplx_mult_q31( + const arm_matrix_instance_q31 *pSrcA, + const arm_matrix_instance_q31 *pSrcB, + arm_matrix_instance_q31 *pDst); + + +/** + * @brief Floating-point matrix transpose. + * @param[in] pSrc points to the input matrix + * @param[out] pDst points to the output matrix + * @return The function returns either ARM_MATH_SIZE_MISMATCH + * or ARM_MATH_SUCCESS based on the outcome of size checking. + */ +arm_status arm_mat_trans_f32( + const arm_matrix_instance_f32 *pSrc, + arm_matrix_instance_f32 *pDst); + + +/** + * @brief Q15 matrix transpose. + * @param[in] pSrc points to the input matrix + * @param[out] pDst points to the output matrix + * @return The function returns either ARM_MATH_SIZE_MISMATCH + * or ARM_MATH_SUCCESS based on the outcome of size checking. + */ +arm_status arm_mat_trans_q15( + const arm_matrix_instance_q15 *pSrc, + arm_matrix_instance_q15 *pDst); + + +/** + * @brief Q31 matrix transpose. + * @param[in] pSrc points to the input matrix + * @param[out] pDst points to the output matrix + * @return The function returns either ARM_MATH_SIZE_MISMATCH + * or ARM_MATH_SUCCESS based on the outcome of size checking. + */ +arm_status arm_mat_trans_q31( + const arm_matrix_instance_q31 *pSrc, + arm_matrix_instance_q31 *pDst); + + +/** + * @brief Floating-point matrix multiplication + * @param[in] pSrcA points to the first input matrix structure + * @param[in] pSrcB points to the second input matrix structure + * @param[out] pDst points to output matrix structure + * @return The function returns either + * ARM_MATH_SIZE_MISMATCH or ARM_MATH_SUCCESS based on the outcome of size checking. + */ +arm_status arm_mat_mult_f32( + const arm_matrix_instance_f32 *pSrcA, + const arm_matrix_instance_f32 *pSrcB, + arm_matrix_instance_f32 *pDst); + + +/** + * @brief Q15 matrix multiplication + * @param[in] pSrcA points to the first input matrix structure + * @param[in] pSrcB points to the second input matrix structure + * @param[out] pDst points to output matrix structure + * @param[in] pState points to the array for storing intermediate results + * @return The function returns either + * ARM_MATH_SIZE_MISMATCH or ARM_MATH_SUCCESS based on the outcome of size checking. + */ +arm_status arm_mat_mult_q15( + const arm_matrix_instance_q15 *pSrcA, + const arm_matrix_instance_q15 *pSrcB, + arm_matrix_instance_q15 *pDst, + q15_t *pState); + + +/** + * @brief Q15 matrix multiplication (fast variant) for Cortex-M3 and Cortex-M4 + * @param[in] pSrcA points to the first input matrix structure + * @param[in] pSrcB points to the second input matrix structure + * @param[out] pDst points to output matrix structure + * @param[in] pState points to the array for storing intermediate results + * @return The function returns either + * ARM_MATH_SIZE_MISMATCH or ARM_MATH_SUCCESS based on the outcome of size checking. + */ +arm_status arm_mat_mult_fast_q15( + const arm_matrix_instance_q15 *pSrcA, + const arm_matrix_instance_q15 *pSrcB, + arm_matrix_instance_q15 *pDst, + q15_t *pState); + + +/** + * @brief Q31 matrix multiplication + * @param[in] pSrcA points to the first input matrix structure + * @param[in] pSrcB points to the second input matrix structure + * @param[out] pDst points to output matrix structure + * @return The function returns either + * ARM_MATH_SIZE_MISMATCH or ARM_MATH_SUCCESS based on the outcome of size checking. + */ +arm_status arm_mat_mult_q31( + const arm_matrix_instance_q31 *pSrcA, + const arm_matrix_instance_q31 *pSrcB, + arm_matrix_instance_q31 *pDst); + + +/** + * @brief Q31 matrix multiplication (fast variant) for Cortex-M3 and Cortex-M4 + * @param[in] pSrcA points to the first input matrix structure + * @param[in] pSrcB points to the second input matrix structure + * @param[out] pDst points to output matrix structure + * @return The function returns either + * ARM_MATH_SIZE_MISMATCH or ARM_MATH_SUCCESS based on the outcome of size checking. + */ +arm_status arm_mat_mult_fast_q31( + const arm_matrix_instance_q31 *pSrcA, + const arm_matrix_instance_q31 *pSrcB, + arm_matrix_instance_q31 *pDst); + + +/** + * @brief Floating-point matrix subtraction + * @param[in] pSrcA points to the first input matrix structure + * @param[in] pSrcB points to the second input matrix structure + * @param[out] pDst points to output matrix structure + * @return The function returns either + * ARM_MATH_SIZE_MISMATCH or ARM_MATH_SUCCESS based on the outcome of size checking. + */ +arm_status arm_mat_sub_f32( + const arm_matrix_instance_f32 *pSrcA, + const arm_matrix_instance_f32 *pSrcB, + arm_matrix_instance_f32 *pDst); + + +/** + * @brief Q15 matrix subtraction + * @param[in] pSrcA points to the first input matrix structure + * @param[in] pSrcB points to the second input matrix structure + * @param[out] pDst points to output matrix structure + * @return The function returns either + * ARM_MATH_SIZE_MISMATCH or ARM_MATH_SUCCESS based on the outcome of size checking. + */ +arm_status arm_mat_sub_q15( + const arm_matrix_instance_q15 *pSrcA, + const arm_matrix_instance_q15 *pSrcB, + arm_matrix_instance_q15 *pDst); + + +/** + * @brief Q31 matrix subtraction + * @param[in] pSrcA points to the first input matrix structure + * @param[in] pSrcB points to the second input matrix structure + * @param[out] pDst points to output matrix structure + * @return The function returns either + * ARM_MATH_SIZE_MISMATCH or ARM_MATH_SUCCESS based on the outcome of size checking. + */ +arm_status arm_mat_sub_q31( + const arm_matrix_instance_q31 *pSrcA, + const arm_matrix_instance_q31 *pSrcB, + arm_matrix_instance_q31 *pDst); + + +/** + * @brief Floating-point matrix scaling. + * @param[in] pSrc points to the input matrix + * @param[in] scale scale factor + * @param[out] pDst points to the output matrix + * @return The function returns either + * ARM_MATH_SIZE_MISMATCH or ARM_MATH_SUCCESS based on the outcome of size checking. + */ +arm_status arm_mat_scale_f32( + const arm_matrix_instance_f32 *pSrc, + float32_t scale, + arm_matrix_instance_f32 *pDst); + + +/** + * @brief Q15 matrix scaling. + * @param[in] pSrc points to input matrix + * @param[in] scaleFract fractional portion of the scale factor + * @param[in] shift number of bits to shift the result by + * @param[out] pDst points to output matrix + * @return The function returns either + * ARM_MATH_SIZE_MISMATCH or ARM_MATH_SUCCESS based on the outcome of size checking. + */ +arm_status arm_mat_scale_q15( + const arm_matrix_instance_q15 *pSrc, + q15_t scaleFract, + int32_t shift, + arm_matrix_instance_q15 *pDst); + + +/** + * @brief Q31 matrix scaling. + * @param[in] pSrc points to input matrix + * @param[in] scaleFract fractional portion of the scale factor + * @param[in] shift number of bits to shift the result by + * @param[out] pDst points to output matrix structure + * @return The function returns either + * ARM_MATH_SIZE_MISMATCH or ARM_MATH_SUCCESS based on the outcome of size checking. + */ +arm_status arm_mat_scale_q31( + const arm_matrix_instance_q31 *pSrc, + q31_t scaleFract, + int32_t shift, + arm_matrix_instance_q31 *pDst); + + +/** + * @brief Q31 matrix initialization. + * @param[in,out] S points to an instance of the floating-point matrix structure. + * @param[in] nRows number of rows in the matrix. + * @param[in] nColumns number of columns in the matrix. + * @param[in] pData points to the matrix data array. + */ +void arm_mat_init_q31( + arm_matrix_instance_q31 *S, + uint16_t nRows, + uint16_t nColumns, + q31_t *pData); + + +/** + * @brief Q15 matrix initialization. + * @param[in,out] S points to an instance of the floating-point matrix structure. + * @param[in] nRows number of rows in the matrix. + * @param[in] nColumns number of columns in the matrix. + * @param[in] pData points to the matrix data array. + */ +void arm_mat_init_q15( + arm_matrix_instance_q15 *S, + uint16_t nRows, + uint16_t nColumns, + q15_t *pData); + + +/** + * @brief Floating-point matrix initialization. + * @param[in,out] S points to an instance of the floating-point matrix structure. + * @param[in] nRows number of rows in the matrix. + * @param[in] nColumns number of columns in the matrix. + * @param[in] pData points to the matrix data array. + */ +void arm_mat_init_f32( + arm_matrix_instance_f32 *S, + uint16_t nRows, + uint16_t nColumns, + float32_t *pData); + + + +/** + * @brief Instance structure for the Q15 PID Control. + */ +typedef struct +{ + q15_t A0; /**< The derived gain, A0 = Kp + Ki + Kd . */ +#ifdef ARM_MATH_CM0_FAMILY + q15_t A1; + q15_t A2; +#else + q31_t A1; /**< The derived gain A1 = -Kp - 2Kd | Kd.*/ +#endif + q15_t state[3]; /**< The state array of length 3. */ + q15_t Kp; /**< The proportional gain. */ + q15_t Ki; /**< The integral gain. */ + q15_t Kd; /**< The derivative gain. */ +} arm_pid_instance_q15; + +/** + * @brief Instance structure for the Q31 PID Control. + */ +typedef struct +{ + q31_t A0; /**< The derived gain, A0 = Kp + Ki + Kd . */ + q31_t A1; /**< The derived gain, A1 = -Kp - 2Kd. */ + q31_t A2; /**< The derived gain, A2 = Kd . */ + q31_t state[3]; /**< The state array of length 3. */ + q31_t Kp; /**< The proportional gain. */ + q31_t Ki; /**< The integral gain. */ + q31_t Kd; /**< The derivative gain. */ +} arm_pid_instance_q31; + +/** + * @brief Instance structure for the floating-point PID Control. + */ +typedef struct +{ + float32_t A0; /**< The derived gain, A0 = Kp + Ki + Kd . */ + float32_t A1; /**< The derived gain, A1 = -Kp - 2Kd. */ + float32_t A2; /**< The derived gain, A2 = Kd . */ + float32_t state[3]; /**< The state array of length 3. */ + float32_t Kp; /**< The proportional gain. */ + float32_t Ki; /**< The integral gain. */ + float32_t Kd; /**< The derivative gain. */ +} arm_pid_instance_f32; + + + +/** + * @brief Initialization function for the floating-point PID Control. + * @param[in,out] S points to an instance of the PID structure. + * @param[in] resetStateFlag flag to reset the state. 0 = no change in state 1 = reset the state. + */ +void arm_pid_init_f32( + arm_pid_instance_f32 *S, + int32_t resetStateFlag); + + +/** + * @brief Reset function for the floating-point PID Control. + * @param[in,out] S is an instance of the floating-point PID Control structure + */ +void arm_pid_reset_f32( + arm_pid_instance_f32 *S); + + +/** + * @brief Initialization function for the Q31 PID Control. + * @param[in,out] S points to an instance of the Q15 PID structure. + * @param[in] resetStateFlag flag to reset the state. 0 = no change in state 1 = reset the state. + */ +void arm_pid_init_q31( + arm_pid_instance_q31 *S, + int32_t resetStateFlag); + + +/** + * @brief Reset function for the Q31 PID Control. + * @param[in,out] S points to an instance of the Q31 PID Control structure + */ + +void arm_pid_reset_q31( + arm_pid_instance_q31 *S); + + +/** + * @brief Initialization function for the Q15 PID Control. + * @param[in,out] S points to an instance of the Q15 PID structure. + * @param[in] resetStateFlag flag to reset the state. 0 = no change in state 1 = reset the state. + */ +void arm_pid_init_q15( + arm_pid_instance_q15 *S, + int32_t resetStateFlag); + + +/** + * @brief Reset function for the Q15 PID Control. + * @param[in,out] S points to an instance of the q15 PID Control structure + */ +void arm_pid_reset_q15( + arm_pid_instance_q15 *S); + + +/** + * @brief Instance structure for the floating-point Linear Interpolate function. + */ +typedef struct +{ + uint32_t nValues; /**< nValues */ + float32_t x1; /**< x1 */ + float32_t xSpacing; /**< xSpacing */ + float32_t *pYData; /**< pointer to the table of Y values */ +} arm_linear_interp_instance_f32; + +/** + * @brief Instance structure for the floating-point bilinear interpolation function. + */ +typedef struct +{ + uint16_t numRows; /**< number of rows in the data table. */ + uint16_t numCols; /**< number of columns in the data table. */ + float32_t *pData; /**< points to the data table. */ +} arm_bilinear_interp_instance_f32; + +/** +* @brief Instance structure for the Q31 bilinear interpolation function. +*/ +typedef struct +{ + uint16_t numRows; /**< number of rows in the data table. */ + uint16_t numCols; /**< number of columns in the data table. */ + q31_t *pData; /**< points to the data table. */ +} arm_bilinear_interp_instance_q31; + +/** +* @brief Instance structure for the Q15 bilinear interpolation function. +*/ +typedef struct +{ + uint16_t numRows; /**< number of rows in the data table. */ + uint16_t numCols; /**< number of columns in the data table. */ + q15_t *pData; /**< points to the data table. */ +} arm_bilinear_interp_instance_q15; + +/** +* @brief Instance structure for the Q15 bilinear interpolation function. +*/ +typedef struct +{ + uint16_t numRows; /**< number of rows in the data table. */ + uint16_t numCols; /**< number of columns in the data table. */ + q7_t *pData; /**< points to the data table. */ +} arm_bilinear_interp_instance_q7; + + +/** + * @brief Q7 vector multiplication. + * @param[in] pSrcA points to the first input vector + * @param[in] pSrcB points to the second input vector + * @param[out] pDst points to the output vector + * @param[in] blockSize number of samples in each vector + */ +void arm_mult_q7( + q7_t *pSrcA, + q7_t *pSrcB, + q7_t *pDst, + uint32_t blockSize); + + +/** + * @brief Q15 vector multiplication. + * @param[in] pSrcA points to the first input vector + * @param[in] pSrcB points to the second input vector + * @param[out] pDst points to the output vector + * @param[in] blockSize number of samples in each vector + */ +void arm_mult_q15( + q15_t *pSrcA, + q15_t *pSrcB, + q15_t *pDst, + uint32_t blockSize); + + +/** + * @brief Q31 vector multiplication. + * @param[in] pSrcA points to the first input vector + * @param[in] pSrcB points to the second input vector + * @param[out] pDst points to the output vector + * @param[in] blockSize number of samples in each vector + */ +void arm_mult_q31( + q31_t *pSrcA, + q31_t *pSrcB, + q31_t *pDst, + uint32_t blockSize); + + +/** + * @brief Floating-point vector multiplication. + * @param[in] pSrcA points to the first input vector + * @param[in] pSrcB points to the second input vector + * @param[out] pDst points to the output vector + * @param[in] blockSize number of samples in each vector + */ +void arm_mult_f32( + float32_t *pSrcA, + float32_t *pSrcB, + float32_t *pDst, + uint32_t blockSize); + + +/** + * @brief Instance structure for the Q15 CFFT/CIFFT function. + */ +typedef struct +{ + uint16_t fftLen; /**< length of the FFT. */ + uint8_t ifftFlag; /**< flag that selects forward (ifftFlag=0) or inverse (ifftFlag=1) transform. */ + uint8_t bitReverseFlag; /**< flag that enables (bitReverseFlag=1) or disables (bitReverseFlag=0) bit reversal of output. */ + q15_t *pTwiddle; /**< points to the Sin twiddle factor table. */ + uint16_t *pBitRevTable; /**< points to the bit reversal table. */ + uint16_t twidCoefModifier; /**< twiddle coefficient modifier that supports different size FFTs with the same twiddle factor table. */ + uint16_t bitRevFactor; /**< bit reversal modifier that supports different size FFTs with the same bit reversal table. */ +} arm_cfft_radix2_instance_q15; + +/* Deprecated */ +arm_status arm_cfft_radix2_init_q15( + arm_cfft_radix2_instance_q15 *S, + uint16_t fftLen, + uint8_t ifftFlag, + uint8_t bitReverseFlag); + +/* Deprecated */ +void arm_cfft_radix2_q15( + const arm_cfft_radix2_instance_q15 *S, + q15_t *pSrc); + + +/** + * @brief Instance structure for the Q15 CFFT/CIFFT function. + */ +typedef struct +{ + uint16_t fftLen; /**< length of the FFT. */ + uint8_t ifftFlag; /**< flag that selects forward (ifftFlag=0) or inverse (ifftFlag=1) transform. */ + uint8_t bitReverseFlag; /**< flag that enables (bitReverseFlag=1) or disables (bitReverseFlag=0) bit reversal of output. */ + q15_t *pTwiddle; /**< points to the twiddle factor table. */ + uint16_t *pBitRevTable; /**< points to the bit reversal table. */ + uint16_t twidCoefModifier; /**< twiddle coefficient modifier that supports different size FFTs with the same twiddle factor table. */ + uint16_t bitRevFactor; /**< bit reversal modifier that supports different size FFTs with the same bit reversal table. */ +} arm_cfft_radix4_instance_q15; + +/* Deprecated */ +arm_status arm_cfft_radix4_init_q15( + arm_cfft_radix4_instance_q15 *S, + uint16_t fftLen, + uint8_t ifftFlag, + uint8_t bitReverseFlag); + +/* Deprecated */ +void arm_cfft_radix4_q15( + const arm_cfft_radix4_instance_q15 *S, + q15_t *pSrc); + +/** + * @brief Instance structure for the Radix-2 Q31 CFFT/CIFFT function. + */ +typedef struct +{ + uint16_t fftLen; /**< length of the FFT. */ + uint8_t ifftFlag; /**< flag that selects forward (ifftFlag=0) or inverse (ifftFlag=1) transform. */ + uint8_t bitReverseFlag; /**< flag that enables (bitReverseFlag=1) or disables (bitReverseFlag=0) bit reversal of output. */ + q31_t *pTwiddle; /**< points to the Twiddle factor table. */ + uint16_t *pBitRevTable; /**< points to the bit reversal table. */ + uint16_t twidCoefModifier; /**< twiddle coefficient modifier that supports different size FFTs with the same twiddle factor table. */ + uint16_t bitRevFactor; /**< bit reversal modifier that supports different size FFTs with the same bit reversal table. */ +} arm_cfft_radix2_instance_q31; + +/* Deprecated */ +arm_status arm_cfft_radix2_init_q31( + arm_cfft_radix2_instance_q31 *S, + uint16_t fftLen, + uint8_t ifftFlag, + uint8_t bitReverseFlag); + +/* Deprecated */ +void arm_cfft_radix2_q31( + const arm_cfft_radix2_instance_q31 *S, + q31_t *pSrc); + +/** + * @brief Instance structure for the Q31 CFFT/CIFFT function. + */ +typedef struct +{ + uint16_t fftLen; /**< length of the FFT. */ + uint8_t ifftFlag; /**< flag that selects forward (ifftFlag=0) or inverse (ifftFlag=1) transform. */ + uint8_t bitReverseFlag; /**< flag that enables (bitReverseFlag=1) or disables (bitReverseFlag=0) bit reversal of output. */ + q31_t *pTwiddle; /**< points to the twiddle factor table. */ + uint16_t *pBitRevTable; /**< points to the bit reversal table. */ + uint16_t twidCoefModifier; /**< twiddle coefficient modifier that supports different size FFTs with the same twiddle factor table. */ + uint16_t bitRevFactor; /**< bit reversal modifier that supports different size FFTs with the same bit reversal table. */ +} arm_cfft_radix4_instance_q31; + +/* Deprecated */ +void arm_cfft_radix4_q31( + const arm_cfft_radix4_instance_q31 *S, + q31_t *pSrc); + +/* Deprecated */ +arm_status arm_cfft_radix4_init_q31( + arm_cfft_radix4_instance_q31 *S, + uint16_t fftLen, + uint8_t ifftFlag, + uint8_t bitReverseFlag); + +/** + * @brief Instance structure for the floating-point CFFT/CIFFT function. + */ +typedef struct +{ + uint16_t fftLen; /**< length of the FFT. */ + uint8_t ifftFlag; /**< flag that selects forward (ifftFlag=0) or inverse (ifftFlag=1) transform. */ + uint8_t bitReverseFlag; /**< flag that enables (bitReverseFlag=1) or disables (bitReverseFlag=0) bit reversal of output. */ + float32_t *pTwiddle; /**< points to the Twiddle factor table. */ + uint16_t *pBitRevTable; /**< points to the bit reversal table. */ + uint16_t twidCoefModifier; /**< twiddle coefficient modifier that supports different size FFTs with the same twiddle factor table. */ + uint16_t bitRevFactor; /**< bit reversal modifier that supports different size FFTs with the same bit reversal table. */ + float32_t onebyfftLen; /**< value of 1/fftLen. */ +} arm_cfft_radix2_instance_f32; + +/* Deprecated */ +arm_status arm_cfft_radix2_init_f32( + arm_cfft_radix2_instance_f32 *S, + uint16_t fftLen, + uint8_t ifftFlag, + uint8_t bitReverseFlag); + +/* Deprecated */ +void arm_cfft_radix2_f32( + const arm_cfft_radix2_instance_f32 *S, + float32_t *pSrc); + +/** + * @brief Instance structure for the floating-point CFFT/CIFFT function. + */ +typedef struct +{ + uint16_t fftLen; /**< length of the FFT. */ + uint8_t ifftFlag; /**< flag that selects forward (ifftFlag=0) or inverse (ifftFlag=1) transform. */ + uint8_t bitReverseFlag; /**< flag that enables (bitReverseFlag=1) or disables (bitReverseFlag=0) bit reversal of output. */ + float32_t *pTwiddle; /**< points to the Twiddle factor table. */ + uint16_t *pBitRevTable; /**< points to the bit reversal table. */ + uint16_t twidCoefModifier; /**< twiddle coefficient modifier that supports different size FFTs with the same twiddle factor table. */ + uint16_t bitRevFactor; /**< bit reversal modifier that supports different size FFTs with the same bit reversal table. */ + float32_t onebyfftLen; /**< value of 1/fftLen. */ +} arm_cfft_radix4_instance_f32; + +/* Deprecated */ +arm_status arm_cfft_radix4_init_f32( + arm_cfft_radix4_instance_f32 *S, + uint16_t fftLen, + uint8_t ifftFlag, + uint8_t bitReverseFlag); + +/* Deprecated */ +void arm_cfft_radix4_f32( + const arm_cfft_radix4_instance_f32 *S, + float32_t *pSrc); + +/** + * @brief Instance structure for the fixed-point CFFT/CIFFT function. + */ +typedef struct +{ + uint16_t fftLen; /**< length of the FFT. */ + const q15_t *pTwiddle; /**< points to the Twiddle factor table. */ + const uint16_t *pBitRevTable; /**< points to the bit reversal table. */ + uint16_t bitRevLength; /**< bit reversal table length. */ +} arm_cfft_instance_q15; + +void arm_cfft_q15( + const arm_cfft_instance_q15 *S, + q15_t *p1, + uint8_t ifftFlag, + uint8_t bitReverseFlag); + +/** + * @brief Instance structure for the fixed-point CFFT/CIFFT function. + */ +typedef struct +{ + uint16_t fftLen; /**< length of the FFT. */ + const q31_t *pTwiddle; /**< points to the Twiddle factor table. */ + const uint16_t *pBitRevTable; /**< points to the bit reversal table. */ + uint16_t bitRevLength; /**< bit reversal table length. */ +} arm_cfft_instance_q31; + +void arm_cfft_q31( + const arm_cfft_instance_q31 *S, + q31_t *p1, + uint8_t ifftFlag, + uint8_t bitReverseFlag); + +/** + * @brief Instance structure for the floating-point CFFT/CIFFT function. + */ +typedef struct +{ + uint16_t fftLen; /**< length of the FFT. */ + const float32_t *pTwiddle; /**< points to the Twiddle factor table. */ + const uint16_t *pBitRevTable; /**< points to the bit reversal table. */ + uint16_t bitRevLength; /**< bit reversal table length. */ +} arm_cfft_instance_f32; + +void arm_cfft_f32( + const arm_cfft_instance_f32 *S, + float32_t *p1, + uint8_t ifftFlag, + uint8_t bitReverseFlag); + +/** + * @brief Instance structure for the Q15 RFFT/RIFFT function. + */ +typedef struct +{ + uint32_t fftLenReal; /**< length of the real FFT. */ + uint8_t ifftFlagR; /**< flag that selects forward (ifftFlagR=0) or inverse (ifftFlagR=1) transform. */ + uint8_t bitReverseFlagR; /**< flag that enables (bitReverseFlagR=1) or disables (bitReverseFlagR=0) bit reversal of output. */ + uint32_t twidCoefRModifier; /**< twiddle coefficient modifier that supports different size FFTs with the same twiddle factor table. */ + q15_t *pTwiddleAReal; /**< points to the real twiddle factor table. */ + q15_t *pTwiddleBReal; /**< points to the imag twiddle factor table. */ + const arm_cfft_instance_q15 *pCfft; /**< points to the complex FFT instance. */ +} arm_rfft_instance_q15; + +arm_status arm_rfft_init_q15( + arm_rfft_instance_q15 *S, + uint32_t fftLenReal, + uint32_t ifftFlagR, + uint32_t bitReverseFlag); + +void arm_rfft_q15( + const arm_rfft_instance_q15 *S, + q15_t *pSrc, + q15_t *pDst); + +/** + * @brief Instance structure for the Q31 RFFT/RIFFT function. + */ +typedef struct +{ + uint32_t fftLenReal; /**< length of the real FFT. */ + uint8_t ifftFlagR; /**< flag that selects forward (ifftFlagR=0) or inverse (ifftFlagR=1) transform. */ + uint8_t bitReverseFlagR; /**< flag that enables (bitReverseFlagR=1) or disables (bitReverseFlagR=0) bit reversal of output. */ + uint32_t twidCoefRModifier; /**< twiddle coefficient modifier that supports different size FFTs with the same twiddle factor table. */ + q31_t *pTwiddleAReal; /**< points to the real twiddle factor table. */ + q31_t *pTwiddleBReal; /**< points to the imag twiddle factor table. */ + const arm_cfft_instance_q31 *pCfft; /**< points to the complex FFT instance. */ +} arm_rfft_instance_q31; + +arm_status arm_rfft_init_q31( + arm_rfft_instance_q31 *S, + uint32_t fftLenReal, + uint32_t ifftFlagR, + uint32_t bitReverseFlag); + +void arm_rfft_q31( + const arm_rfft_instance_q31 *S, + q31_t *pSrc, + q31_t *pDst); + +/** + * @brief Instance structure for the floating-point RFFT/RIFFT function. + */ +typedef struct +{ + uint32_t fftLenReal; /**< length of the real FFT. */ + uint16_t fftLenBy2; /**< length of the complex FFT. */ + uint8_t ifftFlagR; /**< flag that selects forward (ifftFlagR=0) or inverse (ifftFlagR=1) transform. */ + uint8_t bitReverseFlagR; /**< flag that enables (bitReverseFlagR=1) or disables (bitReverseFlagR=0) bit reversal of output. */ + uint32_t twidCoefRModifier; /**< twiddle coefficient modifier that supports different size FFTs with the same twiddle factor table. */ + float32_t *pTwiddleAReal; /**< points to the real twiddle factor table. */ + float32_t *pTwiddleBReal; /**< points to the imag twiddle factor table. */ + arm_cfft_radix4_instance_f32 *pCfft; /**< points to the complex FFT instance. */ +} arm_rfft_instance_f32; + +arm_status arm_rfft_init_f32( + arm_rfft_instance_f32 *S, + arm_cfft_radix4_instance_f32 *S_CFFT, + uint32_t fftLenReal, + uint32_t ifftFlagR, + uint32_t bitReverseFlag); + +void arm_rfft_f32( + const arm_rfft_instance_f32 *S, + float32_t *pSrc, + float32_t *pDst); + +/** + * @brief Instance structure for the floating-point RFFT/RIFFT function. + */ +typedef struct +{ + arm_cfft_instance_f32 Sint; /**< Internal CFFT structure. */ + uint16_t fftLenRFFT; /**< length of the real sequence */ + float32_t *pTwiddleRFFT; /**< Twiddle factors real stage */ +} arm_rfft_fast_instance_f32 ; + +arm_status arm_rfft_fast_init_f32( + arm_rfft_fast_instance_f32 *S, + uint16_t fftLen); + +void arm_rfft_fast_f32( + arm_rfft_fast_instance_f32 *S, + float32_t *p, float32_t *pOut, + uint8_t ifftFlag); + +/** + * @brief Instance structure for the floating-point DCT4/IDCT4 function. + */ +typedef struct +{ + uint16_t N; /**< length of the DCT4. */ + uint16_t Nby2; /**< half of the length of the DCT4. */ + float32_t normalize; /**< normalizing factor. */ + float32_t *pTwiddle; /**< points to the twiddle factor table. */ + float32_t *pCosFactor; /**< points to the cosFactor table. */ + arm_rfft_instance_f32 *pRfft; /**< points to the real FFT instance. */ + arm_cfft_radix4_instance_f32 *pCfft; /**< points to the complex FFT instance. */ +} arm_dct4_instance_f32; + + +/** + * @brief Initialization function for the floating-point DCT4/IDCT4. + * @param[in,out] S points to an instance of floating-point DCT4/IDCT4 structure. + * @param[in] S_RFFT points to an instance of floating-point RFFT/RIFFT structure. + * @param[in] S_CFFT points to an instance of floating-point CFFT/CIFFT structure. + * @param[in] N length of the DCT4. + * @param[in] Nby2 half of the length of the DCT4. + * @param[in] normalize normalizing factor. + * @return arm_status function returns ARM_MATH_SUCCESS if initialization is successful or ARM_MATH_ARGUMENT_ERROR if fftLenReal is not a supported transform length. + */ +arm_status arm_dct4_init_f32( + arm_dct4_instance_f32 *S, + arm_rfft_instance_f32 *S_RFFT, + arm_cfft_radix4_instance_f32 *S_CFFT, + uint16_t N, + uint16_t Nby2, + float32_t normalize); + + +/** + * @brief Processing function for the floating-point DCT4/IDCT4. + * @param[in] S points to an instance of the floating-point DCT4/IDCT4 structure. + * @param[in] pState points to state buffer. + * @param[in,out] pInlineBuffer points to the in-place input and output buffer. + */ +void arm_dct4_f32( + const arm_dct4_instance_f32 *S, + float32_t *pState, + float32_t *pInlineBuffer); + + +/** + * @brief Instance structure for the Q31 DCT4/IDCT4 function. + */ +typedef struct +{ + uint16_t N; /**< length of the DCT4. */ + uint16_t Nby2; /**< half of the length of the DCT4. */ + q31_t normalize; /**< normalizing factor. */ + q31_t *pTwiddle; /**< points to the twiddle factor table. */ + q31_t *pCosFactor; /**< points to the cosFactor table. */ + arm_rfft_instance_q31 *pRfft; /**< points to the real FFT instance. */ + arm_cfft_radix4_instance_q31 *pCfft; /**< points to the complex FFT instance. */ +} arm_dct4_instance_q31; + + +/** + * @brief Initialization function for the Q31 DCT4/IDCT4. + * @param[in,out] S points to an instance of Q31 DCT4/IDCT4 structure. + * @param[in] S_RFFT points to an instance of Q31 RFFT/RIFFT structure + * @param[in] S_CFFT points to an instance of Q31 CFFT/CIFFT structure + * @param[in] N length of the DCT4. + * @param[in] Nby2 half of the length of the DCT4. + * @param[in] normalize normalizing factor. + * @return arm_status function returns ARM_MATH_SUCCESS if initialization is successful or ARM_MATH_ARGUMENT_ERROR if N is not a supported transform length. + */ +arm_status arm_dct4_init_q31( + arm_dct4_instance_q31 *S, + arm_rfft_instance_q31 *S_RFFT, + arm_cfft_radix4_instance_q31 *S_CFFT, + uint16_t N, + uint16_t Nby2, + q31_t normalize); + + +/** + * @brief Processing function for the Q31 DCT4/IDCT4. + * @param[in] S points to an instance of the Q31 DCT4 structure. + * @param[in] pState points to state buffer. + * @param[in,out] pInlineBuffer points to the in-place input and output buffer. + */ +void arm_dct4_q31( + const arm_dct4_instance_q31 *S, + q31_t *pState, + q31_t *pInlineBuffer); + + +/** + * @brief Instance structure for the Q15 DCT4/IDCT4 function. + */ +typedef struct +{ + uint16_t N; /**< length of the DCT4. */ + uint16_t Nby2; /**< half of the length of the DCT4. */ + q15_t normalize; /**< normalizing factor. */ + q15_t *pTwiddle; /**< points to the twiddle factor table. */ + q15_t *pCosFactor; /**< points to the cosFactor table. */ + arm_rfft_instance_q15 *pRfft; /**< points to the real FFT instance. */ + arm_cfft_radix4_instance_q15 *pCfft; /**< points to the complex FFT instance. */ +} arm_dct4_instance_q15; + + +/** + * @brief Initialization function for the Q15 DCT4/IDCT4. + * @param[in,out] S points to an instance of Q15 DCT4/IDCT4 structure. + * @param[in] S_RFFT points to an instance of Q15 RFFT/RIFFT structure. + * @param[in] S_CFFT points to an instance of Q15 CFFT/CIFFT structure. + * @param[in] N length of the DCT4. + * @param[in] Nby2 half of the length of the DCT4. + * @param[in] normalize normalizing factor. + * @return arm_status function returns ARM_MATH_SUCCESS if initialization is successful or ARM_MATH_ARGUMENT_ERROR if N is not a supported transform length. + */ +arm_status arm_dct4_init_q15( + arm_dct4_instance_q15 *S, + arm_rfft_instance_q15 *S_RFFT, + arm_cfft_radix4_instance_q15 *S_CFFT, + uint16_t N, + uint16_t Nby2, + q15_t normalize); + + +/** + * @brief Processing function for the Q15 DCT4/IDCT4. + * @param[in] S points to an instance of the Q15 DCT4 structure. + * @param[in] pState points to state buffer. + * @param[in,out] pInlineBuffer points to the in-place input and output buffer. + */ +void arm_dct4_q15( + const arm_dct4_instance_q15 *S, + q15_t *pState, + q15_t *pInlineBuffer); + + +/** + * @brief Floating-point vector addition. + * @param[in] pSrcA points to the first input vector + * @param[in] pSrcB points to the second input vector + * @param[out] pDst points to the output vector + * @param[in] blockSize number of samples in each vector + */ +void arm_add_f32( + float32_t *pSrcA, + float32_t *pSrcB, + float32_t *pDst, + uint32_t blockSize); + + +/** + * @brief Q7 vector addition. + * @param[in] pSrcA points to the first input vector + * @param[in] pSrcB points to the second input vector + * @param[out] pDst points to the output vector + * @param[in] blockSize number of samples in each vector + */ +void arm_add_q7( + q7_t *pSrcA, + q7_t *pSrcB, + q7_t *pDst, + uint32_t blockSize); + + +/** + * @brief Q15 vector addition. + * @param[in] pSrcA points to the first input vector + * @param[in] pSrcB points to the second input vector + * @param[out] pDst points to the output vector + * @param[in] blockSize number of samples in each vector + */ +void arm_add_q15( + q15_t *pSrcA, + q15_t *pSrcB, + q15_t *pDst, + uint32_t blockSize); + + +/** + * @brief Q31 vector addition. + * @param[in] pSrcA points to the first input vector + * @param[in] pSrcB points to the second input vector + * @param[out] pDst points to the output vector + * @param[in] blockSize number of samples in each vector + */ +void arm_add_q31( + q31_t *pSrcA, + q31_t *pSrcB, + q31_t *pDst, + uint32_t blockSize); + + +/** + * @brief Floating-point vector subtraction. + * @param[in] pSrcA points to the first input vector + * @param[in] pSrcB points to the second input vector + * @param[out] pDst points to the output vector + * @param[in] blockSize number of samples in each vector + */ +void arm_sub_f32( + float32_t *pSrcA, + float32_t *pSrcB, + float32_t *pDst, + uint32_t blockSize); + + +/** + * @brief Q7 vector subtraction. + * @param[in] pSrcA points to the first input vector + * @param[in] pSrcB points to the second input vector + * @param[out] pDst points to the output vector + * @param[in] blockSize number of samples in each vector + */ +void arm_sub_q7( + q7_t *pSrcA, + q7_t *pSrcB, + q7_t *pDst, + uint32_t blockSize); + + +/** + * @brief Q15 vector subtraction. + * @param[in] pSrcA points to the first input vector + * @param[in] pSrcB points to the second input vector + * @param[out] pDst points to the output vector + * @param[in] blockSize number of samples in each vector + */ +void arm_sub_q15( + q15_t *pSrcA, + q15_t *pSrcB, + q15_t *pDst, + uint32_t blockSize); + + +/** + * @brief Q31 vector subtraction. + * @param[in] pSrcA points to the first input vector + * @param[in] pSrcB points to the second input vector + * @param[out] pDst points to the output vector + * @param[in] blockSize number of samples in each vector + */ +void arm_sub_q31( + q31_t *pSrcA, + q31_t *pSrcB, + q31_t *pDst, + uint32_t blockSize); + + +/** + * @brief Multiplies a floating-point vector by a scalar. + * @param[in] pSrc points to the input vector + * @param[in] scale scale factor to be applied + * @param[out] pDst points to the output vector + * @param[in] blockSize number of samples in the vector + */ +void arm_scale_f32( + float32_t *pSrc, + float32_t scale, + float32_t *pDst, + uint32_t blockSize); + + +/** + * @brief Multiplies a Q7 vector by a scalar. + * @param[in] pSrc points to the input vector + * @param[in] scaleFract fractional portion of the scale value + * @param[in] shift number of bits to shift the result by + * @param[out] pDst points to the output vector + * @param[in] blockSize number of samples in the vector + */ +void arm_scale_q7( + q7_t *pSrc, + q7_t scaleFract, + int8_t shift, + q7_t *pDst, + uint32_t blockSize); + + +/** + * @brief Multiplies a Q15 vector by a scalar. + * @param[in] pSrc points to the input vector + * @param[in] scaleFract fractional portion of the scale value + * @param[in] shift number of bits to shift the result by + * @param[out] pDst points to the output vector + * @param[in] blockSize number of samples in the vector + */ +void arm_scale_q15( + q15_t *pSrc, + q15_t scaleFract, + int8_t shift, + q15_t *pDst, + uint32_t blockSize); + + +/** + * @brief Multiplies a Q31 vector by a scalar. + * @param[in] pSrc points to the input vector + * @param[in] scaleFract fractional portion of the scale value + * @param[in] shift number of bits to shift the result by + * @param[out] pDst points to the output vector + * @param[in] blockSize number of samples in the vector + */ +void arm_scale_q31( + q31_t *pSrc, + q31_t scaleFract, + int8_t shift, + q31_t *pDst, + uint32_t blockSize); + + +/** + * @brief Q7 vector absolute value. + * @param[in] pSrc points to the input buffer + * @param[out] pDst points to the output buffer + * @param[in] blockSize number of samples in each vector + */ +void arm_abs_q7( + q7_t *pSrc, + q7_t *pDst, + uint32_t blockSize); + + +/** + * @brief Floating-point vector absolute value. + * @param[in] pSrc points to the input buffer + * @param[out] pDst points to the output buffer + * @param[in] blockSize number of samples in each vector + */ +void arm_abs_f32( + float32_t *pSrc, + float32_t *pDst, + uint32_t blockSize); + + +/** + * @brief Q15 vector absolute value. + * @param[in] pSrc points to the input buffer + * @param[out] pDst points to the output buffer + * @param[in] blockSize number of samples in each vector + */ +void arm_abs_q15( + q15_t *pSrc, + q15_t *pDst, + uint32_t blockSize); + + +/** + * @brief Q31 vector absolute value. + * @param[in] pSrc points to the input buffer + * @param[out] pDst points to the output buffer + * @param[in] blockSize number of samples in each vector + */ +void arm_abs_q31( + q31_t *pSrc, + q31_t *pDst, + uint32_t blockSize); + + +/** + * @brief Dot product of floating-point vectors. + * @param[in] pSrcA points to the first input vector + * @param[in] pSrcB points to the second input vector + * @param[in] blockSize number of samples in each vector + * @param[out] result output result returned here + */ +void arm_dot_prod_f32( + float32_t *pSrcA, + float32_t *pSrcB, + uint32_t blockSize, + float32_t *result); + + +/** + * @brief Dot product of Q7 vectors. + * @param[in] pSrcA points to the first input vector + * @param[in] pSrcB points to the second input vector + * @param[in] blockSize number of samples in each vector + * @param[out] result output result returned here + */ +void arm_dot_prod_q7( + q7_t *pSrcA, + q7_t *pSrcB, + uint32_t blockSize, + q31_t *result); + + +/** + * @brief Dot product of Q15 vectors. + * @param[in] pSrcA points to the first input vector + * @param[in] pSrcB points to the second input vector + * @param[in] blockSize number of samples in each vector + * @param[out] result output result returned here + */ +void arm_dot_prod_q15( + q15_t *pSrcA, + q15_t *pSrcB, + uint32_t blockSize, + q63_t *result); + + +/** + * @brief Dot product of Q31 vectors. + * @param[in] pSrcA points to the first input vector + * @param[in] pSrcB points to the second input vector + * @param[in] blockSize number of samples in each vector + * @param[out] result output result returned here + */ +void arm_dot_prod_q31( + q31_t *pSrcA, + q31_t *pSrcB, + uint32_t blockSize, + q63_t *result); + + +/** + * @brief Shifts the elements of a Q7 vector a specified number of bits. + * @param[in] pSrc points to the input vector + * @param[in] shiftBits number of bits to shift. A positive value shifts left; a negative value shifts right. + * @param[out] pDst points to the output vector + * @param[in] blockSize number of samples in the vector + */ +void arm_shift_q7( + q7_t *pSrc, + int8_t shiftBits, + q7_t *pDst, + uint32_t blockSize); + + +/** + * @brief Shifts the elements of a Q15 vector a specified number of bits. + * @param[in] pSrc points to the input vector + * @param[in] shiftBits number of bits to shift. A positive value shifts left; a negative value shifts right. + * @param[out] pDst points to the output vector + * @param[in] blockSize number of samples in the vector + */ +void arm_shift_q15( + q15_t *pSrc, + int8_t shiftBits, + q15_t *pDst, + uint32_t blockSize); + + +/** + * @brief Shifts the elements of a Q31 vector a specified number of bits. + * @param[in] pSrc points to the input vector + * @param[in] shiftBits number of bits to shift. A positive value shifts left; a negative value shifts right. + * @param[out] pDst points to the output vector + * @param[in] blockSize number of samples in the vector + */ +void arm_shift_q31( + q31_t *pSrc, + int8_t shiftBits, + q31_t *pDst, + uint32_t blockSize); + + +/** + * @brief Adds a constant offset to a floating-point vector. + * @param[in] pSrc points to the input vector + * @param[in] offset is the offset to be added + * @param[out] pDst points to the output vector + * @param[in] blockSize number of samples in the vector + */ +void arm_offset_f32( + float32_t *pSrc, + float32_t offset, + float32_t *pDst, + uint32_t blockSize); + + +/** + * @brief Adds a constant offset to a Q7 vector. + * @param[in] pSrc points to the input vector + * @param[in] offset is the offset to be added + * @param[out] pDst points to the output vector + * @param[in] blockSize number of samples in the vector + */ +void arm_offset_q7( + q7_t *pSrc, + q7_t offset, + q7_t *pDst, + uint32_t blockSize); + + +/** + * @brief Adds a constant offset to a Q15 vector. + * @param[in] pSrc points to the input vector + * @param[in] offset is the offset to be added + * @param[out] pDst points to the output vector + * @param[in] blockSize number of samples in the vector + */ +void arm_offset_q15( + q15_t *pSrc, + q15_t offset, + q15_t *pDst, + uint32_t blockSize); + + +/** + * @brief Adds a constant offset to a Q31 vector. + * @param[in] pSrc points to the input vector + * @param[in] offset is the offset to be added + * @param[out] pDst points to the output vector + * @param[in] blockSize number of samples in the vector + */ +void arm_offset_q31( + q31_t *pSrc, + q31_t offset, + q31_t *pDst, + uint32_t blockSize); + + +/** + * @brief Negates the elements of a floating-point vector. + * @param[in] pSrc points to the input vector + * @param[out] pDst points to the output vector + * @param[in] blockSize number of samples in the vector + */ +void arm_negate_f32( + float32_t *pSrc, + float32_t *pDst, + uint32_t blockSize); + + +/** + * @brief Negates the elements of a Q7 vector. + * @param[in] pSrc points to the input vector + * @param[out] pDst points to the output vector + * @param[in] blockSize number of samples in the vector + */ +void arm_negate_q7( + q7_t *pSrc, + q7_t *pDst, + uint32_t blockSize); + + +/** + * @brief Negates the elements of a Q15 vector. + * @param[in] pSrc points to the input vector + * @param[out] pDst points to the output vector + * @param[in] blockSize number of samples in the vector + */ +void arm_negate_q15( + q15_t *pSrc, + q15_t *pDst, + uint32_t blockSize); + + +/** + * @brief Negates the elements of a Q31 vector. + * @param[in] pSrc points to the input vector + * @param[out] pDst points to the output vector + * @param[in] blockSize number of samples in the vector + */ +void arm_negate_q31( + q31_t *pSrc, + q31_t *pDst, + uint32_t blockSize); + + +/** + * @brief Copies the elements of a floating-point vector. + * @param[in] pSrc input pointer + * @param[out] pDst output pointer + * @param[in] blockSize number of samples to process + */ +void arm_copy_f32( + float32_t *pSrc, + float32_t *pDst, + uint32_t blockSize); + + +/** + * @brief Copies the elements of a Q7 vector. + * @param[in] pSrc input pointer + * @param[out] pDst output pointer + * @param[in] blockSize number of samples to process + */ +void arm_copy_q7( + q7_t *pSrc, + q7_t *pDst, + uint32_t blockSize); + + +/** + * @brief Copies the elements of a Q15 vector. + * @param[in] pSrc input pointer + * @param[out] pDst output pointer + * @param[in] blockSize number of samples to process + */ +void arm_copy_q15( + q15_t *pSrc, + q15_t *pDst, + uint32_t blockSize); + + +/** + * @brief Copies the elements of a Q31 vector. + * @param[in] pSrc input pointer + * @param[out] pDst output pointer + * @param[in] blockSize number of samples to process + */ +void arm_copy_q31( + q31_t *pSrc, + q31_t *pDst, + uint32_t blockSize); + + +/** + * @brief Fills a constant value into a floating-point vector. + * @param[in] value input value to be filled + * @param[out] pDst output pointer + * @param[in] blockSize number of samples to process + */ +void arm_fill_f32( + float32_t value, + float32_t *pDst, + uint32_t blockSize); + + +/** + * @brief Fills a constant value into a Q7 vector. + * @param[in] value input value to be filled + * @param[out] pDst output pointer + * @param[in] blockSize number of samples to process + */ +void arm_fill_q7( + q7_t value, + q7_t *pDst, + uint32_t blockSize); + + +/** + * @brief Fills a constant value into a Q15 vector. + * @param[in] value input value to be filled + * @param[out] pDst output pointer + * @param[in] blockSize number of samples to process + */ +void arm_fill_q15( + q15_t value, + q15_t *pDst, + uint32_t blockSize); + + +/** + * @brief Fills a constant value into a Q31 vector. + * @param[in] value input value to be filled + * @param[out] pDst output pointer + * @param[in] blockSize number of samples to process + */ +void arm_fill_q31( + q31_t value, + q31_t *pDst, + uint32_t blockSize); + + +/** + * @brief Convolution of floating-point sequences. + * @param[in] pSrcA points to the first input sequence. + * @param[in] srcALen length of the first input sequence. + * @param[in] pSrcB points to the second input sequence. + * @param[in] srcBLen length of the second input sequence. + * @param[out] pDst points to the location where the output result is written. Length srcALen+srcBLen-1. + */ +void arm_conv_f32( + float32_t *pSrcA, + uint32_t srcALen, + float32_t *pSrcB, + uint32_t srcBLen, + float32_t *pDst); + + +/** + * @brief Convolution of Q15 sequences. + * @param[in] pSrcA points to the first input sequence. + * @param[in] srcALen length of the first input sequence. + * @param[in] pSrcB points to the second input sequence. + * @param[in] srcBLen length of the second input sequence. + * @param[out] pDst points to the block of output data Length srcALen+srcBLen-1. + * @param[in] pScratch1 points to scratch buffer of size max(srcALen, srcBLen) + 2*min(srcALen, srcBLen) - 2. + * @param[in] pScratch2 points to scratch buffer of size min(srcALen, srcBLen). + */ +void arm_conv_opt_q15( + q15_t *pSrcA, + uint32_t srcALen, + q15_t *pSrcB, + uint32_t srcBLen, + q15_t *pDst, + q15_t *pScratch1, + q15_t *pScratch2); + + +/** + * @brief Convolution of Q15 sequences. + * @param[in] pSrcA points to the first input sequence. + * @param[in] srcALen length of the first input sequence. + * @param[in] pSrcB points to the second input sequence. + * @param[in] srcBLen length of the second input sequence. + * @param[out] pDst points to the location where the output result is written. Length srcALen+srcBLen-1. + */ +void arm_conv_q15( + q15_t *pSrcA, + uint32_t srcALen, + q15_t *pSrcB, + uint32_t srcBLen, + q15_t *pDst); + + +/** + * @brief Convolution of Q15 sequences (fast version) for Cortex-M3 and Cortex-M4 + * @param[in] pSrcA points to the first input sequence. + * @param[in] srcALen length of the first input sequence. + * @param[in] pSrcB points to the second input sequence. + * @param[in] srcBLen length of the second input sequence. + * @param[out] pDst points to the block of output data Length srcALen+srcBLen-1. + */ +void arm_conv_fast_q15( + q15_t *pSrcA, + uint32_t srcALen, + q15_t *pSrcB, + uint32_t srcBLen, + q15_t *pDst); + + +/** + * @brief Convolution of Q15 sequences (fast version) for Cortex-M3 and Cortex-M4 + * @param[in] pSrcA points to the first input sequence. + * @param[in] srcALen length of the first input sequence. + * @param[in] pSrcB points to the second input sequence. + * @param[in] srcBLen length of the second input sequence. + * @param[out] pDst points to the block of output data Length srcALen+srcBLen-1. + * @param[in] pScratch1 points to scratch buffer of size max(srcALen, srcBLen) + 2*min(srcALen, srcBLen) - 2. + * @param[in] pScratch2 points to scratch buffer of size min(srcALen, srcBLen). + */ +void arm_conv_fast_opt_q15( + q15_t *pSrcA, + uint32_t srcALen, + q15_t *pSrcB, + uint32_t srcBLen, + q15_t *pDst, + q15_t *pScratch1, + q15_t *pScratch2); + + +/** + * @brief Convolution of Q31 sequences. + * @param[in] pSrcA points to the first input sequence. + * @param[in] srcALen length of the first input sequence. + * @param[in] pSrcB points to the second input sequence. + * @param[in] srcBLen length of the second input sequence. + * @param[out] pDst points to the block of output data Length srcALen+srcBLen-1. + */ +void arm_conv_q31( + q31_t *pSrcA, + uint32_t srcALen, + q31_t *pSrcB, + uint32_t srcBLen, + q31_t *pDst); + + +/** + * @brief Convolution of Q31 sequences (fast version) for Cortex-M3 and Cortex-M4 + * @param[in] pSrcA points to the first input sequence. + * @param[in] srcALen length of the first input sequence. + * @param[in] pSrcB points to the second input sequence. + * @param[in] srcBLen length of the second input sequence. + * @param[out] pDst points to the block of output data Length srcALen+srcBLen-1. + */ +void arm_conv_fast_q31( + q31_t *pSrcA, + uint32_t srcALen, + q31_t *pSrcB, + uint32_t srcBLen, + q31_t *pDst); + + +/** +* @brief Convolution of Q7 sequences. +* @param[in] pSrcA points to the first input sequence. +* @param[in] srcALen length of the first input sequence. +* @param[in] pSrcB points to the second input sequence. +* @param[in] srcBLen length of the second input sequence. +* @param[out] pDst points to the block of output data Length srcALen+srcBLen-1. +* @param[in] pScratch1 points to scratch buffer(of type q15_t) of size max(srcALen, srcBLen) + 2*min(srcALen, srcBLen) - 2. +* @param[in] pScratch2 points to scratch buffer (of type q15_t) of size min(srcALen, srcBLen). +*/ +void arm_conv_opt_q7( + q7_t *pSrcA, + uint32_t srcALen, + q7_t *pSrcB, + uint32_t srcBLen, + q7_t *pDst, + q15_t *pScratch1, + q15_t *pScratch2); + + +/** + * @brief Convolution of Q7 sequences. + * @param[in] pSrcA points to the first input sequence. + * @param[in] srcALen length of the first input sequence. + * @param[in] pSrcB points to the second input sequence. + * @param[in] srcBLen length of the second input sequence. + * @param[out] pDst points to the block of output data Length srcALen+srcBLen-1. + */ +void arm_conv_q7( + q7_t *pSrcA, + uint32_t srcALen, + q7_t *pSrcB, + uint32_t srcBLen, + q7_t *pDst); + + +/** + * @brief Partial convolution of floating-point sequences. + * @param[in] pSrcA points to the first input sequence. + * @param[in] srcALen length of the first input sequence. + * @param[in] pSrcB points to the second input sequence. + * @param[in] srcBLen length of the second input sequence. + * @param[out] pDst points to the block of output data + * @param[in] firstIndex is the first output sample to start with. + * @param[in] numPoints is the number of output points to be computed. + * @return Returns either ARM_MATH_SUCCESS if the function completed correctly or ARM_MATH_ARGUMENT_ERROR if the requested subset is not in the range [0 srcALen+srcBLen-2]. + */ +arm_status arm_conv_partial_f32( + float32_t *pSrcA, + uint32_t srcALen, + float32_t *pSrcB, + uint32_t srcBLen, + float32_t *pDst, + uint32_t firstIndex, + uint32_t numPoints); + + +/** + * @brief Partial convolution of Q15 sequences. + * @param[in] pSrcA points to the first input sequence. + * @param[in] srcALen length of the first input sequence. + * @param[in] pSrcB points to the second input sequence. + * @param[in] srcBLen length of the second input sequence. + * @param[out] pDst points to the block of output data + * @param[in] firstIndex is the first output sample to start with. + * @param[in] numPoints is the number of output points to be computed. + * @param[in] pScratch1 points to scratch buffer of size max(srcALen, srcBLen) + 2*min(srcALen, srcBLen) - 2. + * @param[in] pScratch2 points to scratch buffer of size min(srcALen, srcBLen). + * @return Returns either ARM_MATH_SUCCESS if the function completed correctly or ARM_MATH_ARGUMENT_ERROR if the requested subset is not in the range [0 srcALen+srcBLen-2]. + */ +arm_status arm_conv_partial_opt_q15( + q15_t *pSrcA, + uint32_t srcALen, + q15_t *pSrcB, + uint32_t srcBLen, + q15_t *pDst, + uint32_t firstIndex, + uint32_t numPoints, + q15_t *pScratch1, + q15_t *pScratch2); + + +/** + * @brief Partial convolution of Q15 sequences. + * @param[in] pSrcA points to the first input sequence. + * @param[in] srcALen length of the first input sequence. + * @param[in] pSrcB points to the second input sequence. + * @param[in] srcBLen length of the second input sequence. + * @param[out] pDst points to the block of output data + * @param[in] firstIndex is the first output sample to start with. + * @param[in] numPoints is the number of output points to be computed. + * @return Returns either ARM_MATH_SUCCESS if the function completed correctly or ARM_MATH_ARGUMENT_ERROR if the requested subset is not in the range [0 srcALen+srcBLen-2]. + */ +arm_status arm_conv_partial_q15( + q15_t *pSrcA, + uint32_t srcALen, + q15_t *pSrcB, + uint32_t srcBLen, + q15_t *pDst, + uint32_t firstIndex, + uint32_t numPoints); + + +/** + * @brief Partial convolution of Q15 sequences (fast version) for Cortex-M3 and Cortex-M4 + * @param[in] pSrcA points to the first input sequence. + * @param[in] srcALen length of the first input sequence. + * @param[in] pSrcB points to the second input sequence. + * @param[in] srcBLen length of the second input sequence. + * @param[out] pDst points to the block of output data + * @param[in] firstIndex is the first output sample to start with. + * @param[in] numPoints is the number of output points to be computed. + * @return Returns either ARM_MATH_SUCCESS if the function completed correctly or ARM_MATH_ARGUMENT_ERROR if the requested subset is not in the range [0 srcALen+srcBLen-2]. + */ +arm_status arm_conv_partial_fast_q15( + q15_t *pSrcA, + uint32_t srcALen, + q15_t *pSrcB, + uint32_t srcBLen, + q15_t *pDst, + uint32_t firstIndex, + uint32_t numPoints); + + +/** + * @brief Partial convolution of Q15 sequences (fast version) for Cortex-M3 and Cortex-M4 + * @param[in] pSrcA points to the first input sequence. + * @param[in] srcALen length of the first input sequence. + * @param[in] pSrcB points to the second input sequence. + * @param[in] srcBLen length of the second input sequence. + * @param[out] pDst points to the block of output data + * @param[in] firstIndex is the first output sample to start with. + * @param[in] numPoints is the number of output points to be computed. + * @param[in] pScratch1 points to scratch buffer of size max(srcALen, srcBLen) + 2*min(srcALen, srcBLen) - 2. + * @param[in] pScratch2 points to scratch buffer of size min(srcALen, srcBLen). + * @return Returns either ARM_MATH_SUCCESS if the function completed correctly or ARM_MATH_ARGUMENT_ERROR if the requested subset is not in the range [0 srcALen+srcBLen-2]. + */ +arm_status arm_conv_partial_fast_opt_q15( + q15_t *pSrcA, + uint32_t srcALen, + q15_t *pSrcB, + uint32_t srcBLen, + q15_t *pDst, + uint32_t firstIndex, + uint32_t numPoints, + q15_t *pScratch1, + q15_t *pScratch2); + + +/** + * @brief Partial convolution of Q31 sequences. + * @param[in] pSrcA points to the first input sequence. + * @param[in] srcALen length of the first input sequence. + * @param[in] pSrcB points to the second input sequence. + * @param[in] srcBLen length of the second input sequence. + * @param[out] pDst points to the block of output data + * @param[in] firstIndex is the first output sample to start with. + * @param[in] numPoints is the number of output points to be computed. + * @return Returns either ARM_MATH_SUCCESS if the function completed correctly or ARM_MATH_ARGUMENT_ERROR if the requested subset is not in the range [0 srcALen+srcBLen-2]. + */ +arm_status arm_conv_partial_q31( + q31_t *pSrcA, + uint32_t srcALen, + q31_t *pSrcB, + uint32_t srcBLen, + q31_t *pDst, + uint32_t firstIndex, + uint32_t numPoints); + + +/** + * @brief Partial convolution of Q31 sequences (fast version) for Cortex-M3 and Cortex-M4 + * @param[in] pSrcA points to the first input sequence. + * @param[in] srcALen length of the first input sequence. + * @param[in] pSrcB points to the second input sequence. + * @param[in] srcBLen length of the second input sequence. + * @param[out] pDst points to the block of output data + * @param[in] firstIndex is the first output sample to start with. + * @param[in] numPoints is the number of output points to be computed. + * @return Returns either ARM_MATH_SUCCESS if the function completed correctly or ARM_MATH_ARGUMENT_ERROR if the requested subset is not in the range [0 srcALen+srcBLen-2]. + */ +arm_status arm_conv_partial_fast_q31( + q31_t *pSrcA, + uint32_t srcALen, + q31_t *pSrcB, + uint32_t srcBLen, + q31_t *pDst, + uint32_t firstIndex, + uint32_t numPoints); + + +/** + * @brief Partial convolution of Q7 sequences + * @param[in] pSrcA points to the first input sequence. + * @param[in] srcALen length of the first input sequence. + * @param[in] pSrcB points to the second input sequence. + * @param[in] srcBLen length of the second input sequence. + * @param[out] pDst points to the block of output data + * @param[in] firstIndex is the first output sample to start with. + * @param[in] numPoints is the number of output points to be computed. + * @param[in] pScratch1 points to scratch buffer(of type q15_t) of size max(srcALen, srcBLen) + 2*min(srcALen, srcBLen) - 2. + * @param[in] pScratch2 points to scratch buffer (of type q15_t) of size min(srcALen, srcBLen). + * @return Returns either ARM_MATH_SUCCESS if the function completed correctly or ARM_MATH_ARGUMENT_ERROR if the requested subset is not in the range [0 srcALen+srcBLen-2]. + */ +arm_status arm_conv_partial_opt_q7( + q7_t *pSrcA, + uint32_t srcALen, + q7_t *pSrcB, + uint32_t srcBLen, + q7_t *pDst, + uint32_t firstIndex, + uint32_t numPoints, + q15_t *pScratch1, + q15_t *pScratch2); + + +/** + * @brief Partial convolution of Q7 sequences. + * @param[in] pSrcA points to the first input sequence. + * @param[in] srcALen length of the first input sequence. + * @param[in] pSrcB points to the second input sequence. + * @param[in] srcBLen length of the second input sequence. + * @param[out] pDst points to the block of output data + * @param[in] firstIndex is the first output sample to start with. + * @param[in] numPoints is the number of output points to be computed. + * @return Returns either ARM_MATH_SUCCESS if the function completed correctly or ARM_MATH_ARGUMENT_ERROR if the requested subset is not in the range [0 srcALen+srcBLen-2]. + */ +arm_status arm_conv_partial_q7( + q7_t *pSrcA, + uint32_t srcALen, + q7_t *pSrcB, + uint32_t srcBLen, + q7_t *pDst, + uint32_t firstIndex, + uint32_t numPoints); + + +/** + * @brief Instance structure for the Q15 FIR decimator. + */ +typedef struct +{ + uint8_t M; /**< decimation factor. */ + uint16_t numTaps; /**< number of coefficients in the filter. */ + q15_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps.*/ + q15_t *pState; /**< points to the state variable array. The array is of length numTaps+blockSize-1. */ +} arm_fir_decimate_instance_q15; + +/** + * @brief Instance structure for the Q31 FIR decimator. + */ +typedef struct +{ + uint8_t M; /**< decimation factor. */ + uint16_t numTaps; /**< number of coefficients in the filter. */ + q31_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps.*/ + q31_t *pState; /**< points to the state variable array. The array is of length numTaps+blockSize-1. */ +} arm_fir_decimate_instance_q31; + +/** + * @brief Instance structure for the floating-point FIR decimator. + */ +typedef struct +{ + uint8_t M; /**< decimation factor. */ + uint16_t numTaps; /**< number of coefficients in the filter. */ + float32_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps.*/ + float32_t *pState; /**< points to the state variable array. The array is of length numTaps+blockSize-1. */ +} arm_fir_decimate_instance_f32; + + +/** + * @brief Processing function for the floating-point FIR decimator. + * @param[in] S points to an instance of the floating-point FIR decimator structure. + * @param[in] pSrc points to the block of input data. + * @param[out] pDst points to the block of output data + * @param[in] blockSize number of input samples to process per call. + */ +void arm_fir_decimate_f32( + const arm_fir_decimate_instance_f32 *S, + float32_t *pSrc, + float32_t *pDst, + uint32_t blockSize); + + +/** + * @brief Initialization function for the floating-point FIR decimator. + * @param[in,out] S points to an instance of the floating-point FIR decimator structure. + * @param[in] numTaps number of coefficients in the filter. + * @param[in] M decimation factor. + * @param[in] pCoeffs points to the filter coefficients. + * @param[in] pState points to the state buffer. + * @param[in] blockSize number of input samples to process per call. + * @return The function returns ARM_MATH_SUCCESS if initialization is successful or ARM_MATH_LENGTH_ERROR if + * blockSize is not a multiple of M. + */ +arm_status arm_fir_decimate_init_f32( + arm_fir_decimate_instance_f32 *S, + uint16_t numTaps, + uint8_t M, + float32_t *pCoeffs, + float32_t *pState, + uint32_t blockSize); + + +/** + * @brief Processing function for the Q15 FIR decimator. + * @param[in] S points to an instance of the Q15 FIR decimator structure. + * @param[in] pSrc points to the block of input data. + * @param[out] pDst points to the block of output data + * @param[in] blockSize number of input samples to process per call. + */ +void arm_fir_decimate_q15( + const arm_fir_decimate_instance_q15 *S, + q15_t *pSrc, + q15_t *pDst, + uint32_t blockSize); + + +/** + * @brief Processing function for the Q15 FIR decimator (fast variant) for Cortex-M3 and Cortex-M4. + * @param[in] S points to an instance of the Q15 FIR decimator structure. + * @param[in] pSrc points to the block of input data. + * @param[out] pDst points to the block of output data + * @param[in] blockSize number of input samples to process per call. + */ +void arm_fir_decimate_fast_q15( + const arm_fir_decimate_instance_q15 *S, + q15_t *pSrc, + q15_t *pDst, + uint32_t blockSize); + + +/** + * @brief Initialization function for the Q15 FIR decimator. + * @param[in,out] S points to an instance of the Q15 FIR decimator structure. + * @param[in] numTaps number of coefficients in the filter. + * @param[in] M decimation factor. + * @param[in] pCoeffs points to the filter coefficients. + * @param[in] pState points to the state buffer. + * @param[in] blockSize number of input samples to process per call. + * @return The function returns ARM_MATH_SUCCESS if initialization is successful or ARM_MATH_LENGTH_ERROR if + * blockSize is not a multiple of M. + */ +arm_status arm_fir_decimate_init_q15( + arm_fir_decimate_instance_q15 *S, + uint16_t numTaps, + uint8_t M, + q15_t *pCoeffs, + q15_t *pState, + uint32_t blockSize); + + +/** + * @brief Processing function for the Q31 FIR decimator. + * @param[in] S points to an instance of the Q31 FIR decimator structure. + * @param[in] pSrc points to the block of input data. + * @param[out] pDst points to the block of output data + * @param[in] blockSize number of input samples to process per call. + */ +void arm_fir_decimate_q31( + const arm_fir_decimate_instance_q31 *S, + q31_t *pSrc, + q31_t *pDst, + uint32_t blockSize); + +/** + * @brief Processing function for the Q31 FIR decimator (fast variant) for Cortex-M3 and Cortex-M4. + * @param[in] S points to an instance of the Q31 FIR decimator structure. + * @param[in] pSrc points to the block of input data. + * @param[out] pDst points to the block of output data + * @param[in] blockSize number of input samples to process per call. + */ +void arm_fir_decimate_fast_q31( + arm_fir_decimate_instance_q31 *S, + q31_t *pSrc, + q31_t *pDst, + uint32_t blockSize); + + +/** + * @brief Initialization function for the Q31 FIR decimator. + * @param[in,out] S points to an instance of the Q31 FIR decimator structure. + * @param[in] numTaps number of coefficients in the filter. + * @param[in] M decimation factor. + * @param[in] pCoeffs points to the filter coefficients. + * @param[in] pState points to the state buffer. + * @param[in] blockSize number of input samples to process per call. + * @return The function returns ARM_MATH_SUCCESS if initialization is successful or ARM_MATH_LENGTH_ERROR if + * blockSize is not a multiple of M. + */ +arm_status arm_fir_decimate_init_q31( + arm_fir_decimate_instance_q31 *S, + uint16_t numTaps, + uint8_t M, + q31_t *pCoeffs, + q31_t *pState, + uint32_t blockSize); + + +/** + * @brief Instance structure for the Q15 FIR interpolator. + */ +typedef struct +{ + uint8_t L; /**< upsample factor. */ + uint16_t phaseLength; /**< length of each polyphase filter component. */ + q15_t *pCoeffs; /**< points to the coefficient array. The array is of length L*phaseLength. */ + q15_t *pState; /**< points to the state variable array. The array is of length blockSize+phaseLength-1. */ +} arm_fir_interpolate_instance_q15; + +/** + * @brief Instance structure for the Q31 FIR interpolator. + */ +typedef struct +{ + uint8_t L; /**< upsample factor. */ + uint16_t phaseLength; /**< length of each polyphase filter component. */ + q31_t *pCoeffs; /**< points to the coefficient array. The array is of length L*phaseLength. */ + q31_t *pState; /**< points to the state variable array. The array is of length blockSize+phaseLength-1. */ +} arm_fir_interpolate_instance_q31; + +/** + * @brief Instance structure for the floating-point FIR interpolator. + */ +typedef struct +{ + uint8_t L; /**< upsample factor. */ + uint16_t phaseLength; /**< length of each polyphase filter component. */ + float32_t *pCoeffs; /**< points to the coefficient array. The array is of length L*phaseLength. */ + float32_t *pState; /**< points to the state variable array. The array is of length phaseLength+numTaps-1. */ +} arm_fir_interpolate_instance_f32; + + +/** + * @brief Processing function for the Q15 FIR interpolator. + * @param[in] S points to an instance of the Q15 FIR interpolator structure. + * @param[in] pSrc points to the block of input data. + * @param[out] pDst points to the block of output data. + * @param[in] blockSize number of input samples to process per call. + */ +void arm_fir_interpolate_q15( + const arm_fir_interpolate_instance_q15 *S, + q15_t *pSrc, + q15_t *pDst, + uint32_t blockSize); + + +/** + * @brief Initialization function for the Q15 FIR interpolator. + * @param[in,out] S points to an instance of the Q15 FIR interpolator structure. + * @param[in] L upsample factor. + * @param[in] numTaps number of filter coefficients in the filter. + * @param[in] pCoeffs points to the filter coefficient buffer. + * @param[in] pState points to the state buffer. + * @param[in] blockSize number of input samples to process per call. + * @return The function returns ARM_MATH_SUCCESS if initialization is successful or ARM_MATH_LENGTH_ERROR if + * the filter length numTaps is not a multiple of the interpolation factor L. + */ +arm_status arm_fir_interpolate_init_q15( + arm_fir_interpolate_instance_q15 *S, + uint8_t L, + uint16_t numTaps, + q15_t *pCoeffs, + q15_t *pState, + uint32_t blockSize); + + +/** + * @brief Processing function for the Q31 FIR interpolator. + * @param[in] S points to an instance of the Q15 FIR interpolator structure. + * @param[in] pSrc points to the block of input data. + * @param[out] pDst points to the block of output data. + * @param[in] blockSize number of input samples to process per call. + */ +void arm_fir_interpolate_q31( + const arm_fir_interpolate_instance_q31 *S, + q31_t *pSrc, + q31_t *pDst, + uint32_t blockSize); + + +/** + * @brief Initialization function for the Q31 FIR interpolator. + * @param[in,out] S points to an instance of the Q31 FIR interpolator structure. + * @param[in] L upsample factor. + * @param[in] numTaps number of filter coefficients in the filter. + * @param[in] pCoeffs points to the filter coefficient buffer. + * @param[in] pState points to the state buffer. + * @param[in] blockSize number of input samples to process per call. + * @return The function returns ARM_MATH_SUCCESS if initialization is successful or ARM_MATH_LENGTH_ERROR if + * the filter length numTaps is not a multiple of the interpolation factor L. + */ +arm_status arm_fir_interpolate_init_q31( + arm_fir_interpolate_instance_q31 *S, + uint8_t L, + uint16_t numTaps, + q31_t *pCoeffs, + q31_t *pState, + uint32_t blockSize); + + +/** + * @brief Processing function for the floating-point FIR interpolator. + * @param[in] S points to an instance of the floating-point FIR interpolator structure. + * @param[in] pSrc points to the block of input data. + * @param[out] pDst points to the block of output data. + * @param[in] blockSize number of input samples to process per call. + */ +void arm_fir_interpolate_f32( + const arm_fir_interpolate_instance_f32 *S, + float32_t *pSrc, + float32_t *pDst, + uint32_t blockSize); + + +/** + * @brief Initialization function for the floating-point FIR interpolator. + * @param[in,out] S points to an instance of the floating-point FIR interpolator structure. + * @param[in] L upsample factor. + * @param[in] numTaps number of filter coefficients in the filter. + * @param[in] pCoeffs points to the filter coefficient buffer. + * @param[in] pState points to the state buffer. + * @param[in] blockSize number of input samples to process per call. + * @return The function returns ARM_MATH_SUCCESS if initialization is successful or ARM_MATH_LENGTH_ERROR if + * the filter length numTaps is not a multiple of the interpolation factor L. + */ +arm_status arm_fir_interpolate_init_f32( + arm_fir_interpolate_instance_f32 *S, + uint8_t L, + uint16_t numTaps, + float32_t *pCoeffs, + float32_t *pState, + uint32_t blockSize); + + +/** + * @brief Instance structure for the high precision Q31 Biquad cascade filter. + */ +typedef struct +{ + uint8_t numStages; /**< number of 2nd order stages in the filter. Overall order is 2*numStages. */ + q63_t *pState; /**< points to the array of state coefficients. The array is of length 4*numStages. */ + q31_t *pCoeffs; /**< points to the array of coefficients. The array is of length 5*numStages. */ + uint8_t postShift; /**< additional shift, in bits, applied to each output sample. */ +} arm_biquad_cas_df1_32x64_ins_q31; + + +/** + * @param[in] S points to an instance of the high precision Q31 Biquad cascade filter structure. + * @param[in] pSrc points to the block of input data. + * @param[out] pDst points to the block of output data + * @param[in] blockSize number of samples to process. + */ +void arm_biquad_cas_df1_32x64_q31( + const arm_biquad_cas_df1_32x64_ins_q31 *S, + q31_t *pSrc, + q31_t *pDst, + uint32_t blockSize); + + +/** + * @param[in,out] S points to an instance of the high precision Q31 Biquad cascade filter structure. + * @param[in] numStages number of 2nd order stages in the filter. + * @param[in] pCoeffs points to the filter coefficients. + * @param[in] pState points to the state buffer. + * @param[in] postShift shift to be applied to the output. Varies according to the coefficients format + */ +void arm_biquad_cas_df1_32x64_init_q31( + arm_biquad_cas_df1_32x64_ins_q31 *S, + uint8_t numStages, + q31_t *pCoeffs, + q63_t *pState, + uint8_t postShift); + + +/** + * @brief Instance structure for the floating-point transposed direct form II Biquad cascade filter. + */ +typedef struct +{ + uint8_t numStages; /**< number of 2nd order stages in the filter. Overall order is 2*numStages. */ + float32_t *pState; /**< points to the array of state coefficients. The array is of length 2*numStages. */ + float32_t *pCoeffs; /**< points to the array of coefficients. The array is of length 5*numStages. */ +} arm_biquad_cascade_df2T_instance_f32; + +/** + * @brief Instance structure for the floating-point transposed direct form II Biquad cascade filter. + */ +typedef struct +{ + uint8_t numStages; /**< number of 2nd order stages in the filter. Overall order is 2*numStages. */ + float32_t *pState; /**< points to the array of state coefficients. The array is of length 4*numStages. */ + float32_t *pCoeffs; /**< points to the array of coefficients. The array is of length 5*numStages. */ +} arm_biquad_cascade_stereo_df2T_instance_f32; + +/** + * @brief Instance structure for the floating-point transposed direct form II Biquad cascade filter. + */ +typedef struct +{ + uint8_t numStages; /**< number of 2nd order stages in the filter. Overall order is 2*numStages. */ + float64_t *pState; /**< points to the array of state coefficients. The array is of length 2*numStages. */ + float64_t *pCoeffs; /**< points to the array of coefficients. The array is of length 5*numStages. */ +} arm_biquad_cascade_df2T_instance_f64; + + +/** + * @brief Processing function for the floating-point transposed direct form II Biquad cascade filter. + * @param[in] S points to an instance of the filter data structure. + * @param[in] pSrc points to the block of input data. + * @param[out] pDst points to the block of output data + * @param[in] blockSize number of samples to process. + */ +void arm_biquad_cascade_df2T_f32( + const arm_biquad_cascade_df2T_instance_f32 *S, + float32_t *pSrc, + float32_t *pDst, + uint32_t blockSize); + + +/** + * @brief Processing function for the floating-point transposed direct form II Biquad cascade filter. 2 channels + * @param[in] S points to an instance of the filter data structure. + * @param[in] pSrc points to the block of input data. + * @param[out] pDst points to the block of output data + * @param[in] blockSize number of samples to process. + */ +void arm_biquad_cascade_stereo_df2T_f32( + const arm_biquad_cascade_stereo_df2T_instance_f32 *S, + float32_t *pSrc, + float32_t *pDst, + uint32_t blockSize); + + +/** + * @brief Processing function for the floating-point transposed direct form II Biquad cascade filter. + * @param[in] S points to an instance of the filter data structure. + * @param[in] pSrc points to the block of input data. + * @param[out] pDst points to the block of output data + * @param[in] blockSize number of samples to process. + */ +void arm_biquad_cascade_df2T_f64( + const arm_biquad_cascade_df2T_instance_f64 *S, + float64_t *pSrc, + float64_t *pDst, + uint32_t blockSize); + + +/** + * @brief Initialization function for the floating-point transposed direct form II Biquad cascade filter. + * @param[in,out] S points to an instance of the filter data structure. + * @param[in] numStages number of 2nd order stages in the filter. + * @param[in] pCoeffs points to the filter coefficients. + * @param[in] pState points to the state buffer. + */ +void arm_biquad_cascade_df2T_init_f32( + arm_biquad_cascade_df2T_instance_f32 *S, + uint8_t numStages, + float32_t *pCoeffs, + float32_t *pState); + + +/** + * @brief Initialization function for the floating-point transposed direct form II Biquad cascade filter. + * @param[in,out] S points to an instance of the filter data structure. + * @param[in] numStages number of 2nd order stages in the filter. + * @param[in] pCoeffs points to the filter coefficients. + * @param[in] pState points to the state buffer. + */ +void arm_biquad_cascade_stereo_df2T_init_f32( + arm_biquad_cascade_stereo_df2T_instance_f32 *S, + uint8_t numStages, + float32_t *pCoeffs, + float32_t *pState); + + +/** + * @brief Initialization function for the floating-point transposed direct form II Biquad cascade filter. + * @param[in,out] S points to an instance of the filter data structure. + * @param[in] numStages number of 2nd order stages in the filter. + * @param[in] pCoeffs points to the filter coefficients. + * @param[in] pState points to the state buffer. + */ +void arm_biquad_cascade_df2T_init_f64( + arm_biquad_cascade_df2T_instance_f64 *S, + uint8_t numStages, + float64_t *pCoeffs, + float64_t *pState); + + +/** + * @brief Instance structure for the Q15 FIR lattice filter. + */ +typedef struct +{ + uint16_t numStages; /**< number of filter stages. */ + q15_t *pState; /**< points to the state variable array. The array is of length numStages. */ + q15_t *pCoeffs; /**< points to the coefficient array. The array is of length numStages. */ +} arm_fir_lattice_instance_q15; + +/** + * @brief Instance structure for the Q31 FIR lattice filter. + */ +typedef struct +{ + uint16_t numStages; /**< number of filter stages. */ + q31_t *pState; /**< points to the state variable array. The array is of length numStages. */ + q31_t *pCoeffs; /**< points to the coefficient array. The array is of length numStages. */ +} arm_fir_lattice_instance_q31; + +/** + * @brief Instance structure for the floating-point FIR lattice filter. + */ +typedef struct +{ + uint16_t numStages; /**< number of filter stages. */ + float32_t *pState; /**< points to the state variable array. The array is of length numStages. */ + float32_t *pCoeffs; /**< points to the coefficient array. The array is of length numStages. */ +} arm_fir_lattice_instance_f32; + + +/** + * @brief Initialization function for the Q15 FIR lattice filter. + * @param[in] S points to an instance of the Q15 FIR lattice structure. + * @param[in] numStages number of filter stages. + * @param[in] pCoeffs points to the coefficient buffer. The array is of length numStages. + * @param[in] pState points to the state buffer. The array is of length numStages. + */ +void arm_fir_lattice_init_q15( + arm_fir_lattice_instance_q15 *S, + uint16_t numStages, + q15_t *pCoeffs, + q15_t *pState); + + +/** + * @brief Processing function for the Q15 FIR lattice filter. + * @param[in] S points to an instance of the Q15 FIR lattice structure. + * @param[in] pSrc points to the block of input data. + * @param[out] pDst points to the block of output data. + * @param[in] blockSize number of samples to process. + */ +void arm_fir_lattice_q15( + const arm_fir_lattice_instance_q15 *S, + q15_t *pSrc, + q15_t *pDst, + uint32_t blockSize); + + +/** + * @brief Initialization function for the Q31 FIR lattice filter. + * @param[in] S points to an instance of the Q31 FIR lattice structure. + * @param[in] numStages number of filter stages. + * @param[in] pCoeffs points to the coefficient buffer. The array is of length numStages. + * @param[in] pState points to the state buffer. The array is of length numStages. + */ +void arm_fir_lattice_init_q31( + arm_fir_lattice_instance_q31 *S, + uint16_t numStages, + q31_t *pCoeffs, + q31_t *pState); + + +/** + * @brief Processing function for the Q31 FIR lattice filter. + * @param[in] S points to an instance of the Q31 FIR lattice structure. + * @param[in] pSrc points to the block of input data. + * @param[out] pDst points to the block of output data + * @param[in] blockSize number of samples to process. + */ +void arm_fir_lattice_q31( + const arm_fir_lattice_instance_q31 *S, + q31_t *pSrc, + q31_t *pDst, + uint32_t blockSize); + + +/** + * @brief Initialization function for the floating-point FIR lattice filter. + * @param[in] S points to an instance of the floating-point FIR lattice structure. + * @param[in] numStages number of filter stages. + * @param[in] pCoeffs points to the coefficient buffer. The array is of length numStages. + * @param[in] pState points to the state buffer. The array is of length numStages. + */ +void arm_fir_lattice_init_f32( + arm_fir_lattice_instance_f32 *S, + uint16_t numStages, + float32_t *pCoeffs, + float32_t *pState); + + +/** + * @brief Processing function for the floating-point FIR lattice filter. + * @param[in] S points to an instance of the floating-point FIR lattice structure. + * @param[in] pSrc points to the block of input data. + * @param[out] pDst points to the block of output data + * @param[in] blockSize number of samples to process. + */ +void arm_fir_lattice_f32( + const arm_fir_lattice_instance_f32 *S, + float32_t *pSrc, + float32_t *pDst, + uint32_t blockSize); + + +/** + * @brief Instance structure for the Q15 IIR lattice filter. + */ +typedef struct +{ + uint16_t numStages; /**< number of stages in the filter. */ + q15_t *pState; /**< points to the state variable array. The array is of length numStages+blockSize. */ + q15_t *pkCoeffs; /**< points to the reflection coefficient array. The array is of length numStages. */ + q15_t *pvCoeffs; /**< points to the ladder coefficient array. The array is of length numStages+1. */ +} arm_iir_lattice_instance_q15; + +/** + * @brief Instance structure for the Q31 IIR lattice filter. + */ +typedef struct +{ + uint16_t numStages; /**< number of stages in the filter. */ + q31_t *pState; /**< points to the state variable array. The array is of length numStages+blockSize. */ + q31_t *pkCoeffs; /**< points to the reflection coefficient array. The array is of length numStages. */ + q31_t *pvCoeffs; /**< points to the ladder coefficient array. The array is of length numStages+1. */ +} arm_iir_lattice_instance_q31; + +/** + * @brief Instance structure for the floating-point IIR lattice filter. + */ +typedef struct +{ + uint16_t numStages; /**< number of stages in the filter. */ + float32_t *pState; /**< points to the state variable array. The array is of length numStages+blockSize. */ + float32_t *pkCoeffs; /**< points to the reflection coefficient array. The array is of length numStages. */ + float32_t *pvCoeffs; /**< points to the ladder coefficient array. The array is of length numStages+1. */ +} arm_iir_lattice_instance_f32; + + +/** + * @brief Processing function for the floating-point IIR lattice filter. + * @param[in] S points to an instance of the floating-point IIR lattice structure. + * @param[in] pSrc points to the block of input data. + * @param[out] pDst points to the block of output data. + * @param[in] blockSize number of samples to process. + */ +void arm_iir_lattice_f32( + const arm_iir_lattice_instance_f32 *S, + float32_t *pSrc, + float32_t *pDst, + uint32_t blockSize); + + +/** + * @brief Initialization function for the floating-point IIR lattice filter. + * @param[in] S points to an instance of the floating-point IIR lattice structure. + * @param[in] numStages number of stages in the filter. + * @param[in] pkCoeffs points to the reflection coefficient buffer. The array is of length numStages. + * @param[in] pvCoeffs points to the ladder coefficient buffer. The array is of length numStages+1. + * @param[in] pState points to the state buffer. The array is of length numStages+blockSize-1. + * @param[in] blockSize number of samples to process. + */ +void arm_iir_lattice_init_f32( + arm_iir_lattice_instance_f32 *S, + uint16_t numStages, + float32_t *pkCoeffs, + float32_t *pvCoeffs, + float32_t *pState, + uint32_t blockSize); + + +/** + * @brief Processing function for the Q31 IIR lattice filter. + * @param[in] S points to an instance of the Q31 IIR lattice structure. + * @param[in] pSrc points to the block of input data. + * @param[out] pDst points to the block of output data. + * @param[in] blockSize number of samples to process. + */ +void arm_iir_lattice_q31( + const arm_iir_lattice_instance_q31 *S, + q31_t *pSrc, + q31_t *pDst, + uint32_t blockSize); + + +/** + * @brief Initialization function for the Q31 IIR lattice filter. + * @param[in] S points to an instance of the Q31 IIR lattice structure. + * @param[in] numStages number of stages in the filter. + * @param[in] pkCoeffs points to the reflection coefficient buffer. The array is of length numStages. + * @param[in] pvCoeffs points to the ladder coefficient buffer. The array is of length numStages+1. + * @param[in] pState points to the state buffer. The array is of length numStages+blockSize. + * @param[in] blockSize number of samples to process. + */ +void arm_iir_lattice_init_q31( + arm_iir_lattice_instance_q31 *S, + uint16_t numStages, + q31_t *pkCoeffs, + q31_t *pvCoeffs, + q31_t *pState, + uint32_t blockSize); + + +/** + * @brief Processing function for the Q15 IIR lattice filter. + * @param[in] S points to an instance of the Q15 IIR lattice structure. + * @param[in] pSrc points to the block of input data. + * @param[out] pDst points to the block of output data. + * @param[in] blockSize number of samples to process. + */ +void arm_iir_lattice_q15( + const arm_iir_lattice_instance_q15 *S, + q15_t *pSrc, + q15_t *pDst, + uint32_t blockSize); + + +/** + * @brief Initialization function for the Q15 IIR lattice filter. + * @param[in] S points to an instance of the fixed-point Q15 IIR lattice structure. + * @param[in] numStages number of stages in the filter. + * @param[in] pkCoeffs points to reflection coefficient buffer. The array is of length numStages. + * @param[in] pvCoeffs points to ladder coefficient buffer. The array is of length numStages+1. + * @param[in] pState points to state buffer. The array is of length numStages+blockSize. + * @param[in] blockSize number of samples to process per call. + */ +void arm_iir_lattice_init_q15( + arm_iir_lattice_instance_q15 *S, + uint16_t numStages, + q15_t *pkCoeffs, + q15_t *pvCoeffs, + q15_t *pState, + uint32_t blockSize); + + +/** + * @brief Instance structure for the floating-point LMS filter. + */ +typedef struct +{ + uint16_t numTaps; /**< number of coefficients in the filter. */ + float32_t *pState; /**< points to the state variable array. The array is of length numTaps+blockSize-1. */ + float32_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps. */ + float32_t mu; /**< step size that controls filter coefficient updates. */ +} arm_lms_instance_f32; + + +/** + * @brief Processing function for floating-point LMS filter. + * @param[in] S points to an instance of the floating-point LMS filter structure. + * @param[in] pSrc points to the block of input data. + * @param[in] pRef points to the block of reference data. + * @param[out] pOut points to the block of output data. + * @param[out] pErr points to the block of error data. + * @param[in] blockSize number of samples to process. + */ +void arm_lms_f32( + const arm_lms_instance_f32 *S, + float32_t *pSrc, + float32_t *pRef, + float32_t *pOut, + float32_t *pErr, + uint32_t blockSize); + + +/** + * @brief Initialization function for floating-point LMS filter. + * @param[in] S points to an instance of the floating-point LMS filter structure. + * @param[in] numTaps number of filter coefficients. + * @param[in] pCoeffs points to the coefficient buffer. + * @param[in] pState points to state buffer. + * @param[in] mu step size that controls filter coefficient updates. + * @param[in] blockSize number of samples to process. + */ +void arm_lms_init_f32( + arm_lms_instance_f32 *S, + uint16_t numTaps, + float32_t *pCoeffs, + float32_t *pState, + float32_t mu, + uint32_t blockSize); + + +/** + * @brief Instance structure for the Q15 LMS filter. + */ +typedef struct +{ + uint16_t numTaps; /**< number of coefficients in the filter. */ + q15_t *pState; /**< points to the state variable array. The array is of length numTaps+blockSize-1. */ + q15_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps. */ + q15_t mu; /**< step size that controls filter coefficient updates. */ + uint32_t postShift; /**< bit shift applied to coefficients. */ +} arm_lms_instance_q15; + + +/** + * @brief Initialization function for the Q15 LMS filter. + * @param[in] S points to an instance of the Q15 LMS filter structure. + * @param[in] numTaps number of filter coefficients. + * @param[in] pCoeffs points to the coefficient buffer. + * @param[in] pState points to the state buffer. + * @param[in] mu step size that controls filter coefficient updates. + * @param[in] blockSize number of samples to process. + * @param[in] postShift bit shift applied to coefficients. + */ +void arm_lms_init_q15( + arm_lms_instance_q15 *S, + uint16_t numTaps, + q15_t *pCoeffs, + q15_t *pState, + q15_t mu, + uint32_t blockSize, + uint32_t postShift); + + +/** + * @brief Processing function for Q15 LMS filter. + * @param[in] S points to an instance of the Q15 LMS filter structure. + * @param[in] pSrc points to the block of input data. + * @param[in] pRef points to the block of reference data. + * @param[out] pOut points to the block of output data. + * @param[out] pErr points to the block of error data. + * @param[in] blockSize number of samples to process. + */ +void arm_lms_q15( + const arm_lms_instance_q15 *S, + q15_t *pSrc, + q15_t *pRef, + q15_t *pOut, + q15_t *pErr, + uint32_t blockSize); + + +/** + * @brief Instance structure for the Q31 LMS filter. + */ +typedef struct +{ + uint16_t numTaps; /**< number of coefficients in the filter. */ + q31_t *pState; /**< points to the state variable array. The array is of length numTaps+blockSize-1. */ + q31_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps. */ + q31_t mu; /**< step size that controls filter coefficient updates. */ + uint32_t postShift; /**< bit shift applied to coefficients. */ +} arm_lms_instance_q31; + + +/** + * @brief Processing function for Q31 LMS filter. + * @param[in] S points to an instance of the Q15 LMS filter structure. + * @param[in] pSrc points to the block of input data. + * @param[in] pRef points to the block of reference data. + * @param[out] pOut points to the block of output data. + * @param[out] pErr points to the block of error data. + * @param[in] blockSize number of samples to process. + */ +void arm_lms_q31( + const arm_lms_instance_q31 *S, + q31_t *pSrc, + q31_t *pRef, + q31_t *pOut, + q31_t *pErr, + uint32_t blockSize); + + +/** + * @brief Initialization function for Q31 LMS filter. + * @param[in] S points to an instance of the Q31 LMS filter structure. + * @param[in] numTaps number of filter coefficients. + * @param[in] pCoeffs points to coefficient buffer. + * @param[in] pState points to state buffer. + * @param[in] mu step size that controls filter coefficient updates. + * @param[in] blockSize number of samples to process. + * @param[in] postShift bit shift applied to coefficients. + */ +void arm_lms_init_q31( + arm_lms_instance_q31 *S, + uint16_t numTaps, + q31_t *pCoeffs, + q31_t *pState, + q31_t mu, + uint32_t blockSize, + uint32_t postShift); + + +/** + * @brief Instance structure for the floating-point normalized LMS filter. + */ +typedef struct +{ + uint16_t numTaps; /**< number of coefficients in the filter. */ + float32_t *pState; /**< points to the state variable array. The array is of length numTaps+blockSize-1. */ + float32_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps. */ + float32_t mu; /**< step size that control filter coefficient updates. */ + float32_t energy; /**< saves previous frame energy. */ + float32_t x0; /**< saves previous input sample. */ +} arm_lms_norm_instance_f32; + + +/** + * @brief Processing function for floating-point normalized LMS filter. + * @param[in] S points to an instance of the floating-point normalized LMS filter structure. + * @param[in] pSrc points to the block of input data. + * @param[in] pRef points to the block of reference data. + * @param[out] pOut points to the block of output data. + * @param[out] pErr points to the block of error data. + * @param[in] blockSize number of samples to process. + */ +void arm_lms_norm_f32( + arm_lms_norm_instance_f32 *S, + float32_t *pSrc, + float32_t *pRef, + float32_t *pOut, + float32_t *pErr, + uint32_t blockSize); + + +/** + * @brief Initialization function for floating-point normalized LMS filter. + * @param[in] S points to an instance of the floating-point LMS filter structure. + * @param[in] numTaps number of filter coefficients. + * @param[in] pCoeffs points to coefficient buffer. + * @param[in] pState points to state buffer. + * @param[in] mu step size that controls filter coefficient updates. + * @param[in] blockSize number of samples to process. + */ +void arm_lms_norm_init_f32( + arm_lms_norm_instance_f32 *S, + uint16_t numTaps, + float32_t *pCoeffs, + float32_t *pState, + float32_t mu, + uint32_t blockSize); + + +/** + * @brief Instance structure for the Q31 normalized LMS filter. + */ +typedef struct +{ + uint16_t numTaps; /**< number of coefficients in the filter. */ + q31_t *pState; /**< points to the state variable array. The array is of length numTaps+blockSize-1. */ + q31_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps. */ + q31_t mu; /**< step size that controls filter coefficient updates. */ + uint8_t postShift; /**< bit shift applied to coefficients. */ + q31_t *recipTable; /**< points to the reciprocal initial value table. */ + q31_t energy; /**< saves previous frame energy. */ + q31_t x0; /**< saves previous input sample. */ +} arm_lms_norm_instance_q31; + + +/** + * @brief Processing function for Q31 normalized LMS filter. + * @param[in] S points to an instance of the Q31 normalized LMS filter structure. + * @param[in] pSrc points to the block of input data. + * @param[in] pRef points to the block of reference data. + * @param[out] pOut points to the block of output data. + * @param[out] pErr points to the block of error data. + * @param[in] blockSize number of samples to process. + */ +void arm_lms_norm_q31( + arm_lms_norm_instance_q31 *S, + q31_t *pSrc, + q31_t *pRef, + q31_t *pOut, + q31_t *pErr, + uint32_t blockSize); + + +/** + * @brief Initialization function for Q31 normalized LMS filter. + * @param[in] S points to an instance of the Q31 normalized LMS filter structure. + * @param[in] numTaps number of filter coefficients. + * @param[in] pCoeffs points to coefficient buffer. + * @param[in] pState points to state buffer. + * @param[in] mu step size that controls filter coefficient updates. + * @param[in] blockSize number of samples to process. + * @param[in] postShift bit shift applied to coefficients. + */ +void arm_lms_norm_init_q31( + arm_lms_norm_instance_q31 *S, + uint16_t numTaps, + q31_t *pCoeffs, + q31_t *pState, + q31_t mu, + uint32_t blockSize, + uint8_t postShift); + + +/** + * @brief Instance structure for the Q15 normalized LMS filter. + */ +typedef struct +{ + uint16_t numTaps; /**< Number of coefficients in the filter. */ + q15_t *pState; /**< points to the state variable array. The array is of length numTaps+blockSize-1. */ + q15_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps. */ + q15_t mu; /**< step size that controls filter coefficient updates. */ + uint8_t postShift; /**< bit shift applied to coefficients. */ + q15_t *recipTable; /**< Points to the reciprocal initial value table. */ + q15_t energy; /**< saves previous frame energy. */ + q15_t x0; /**< saves previous input sample. */ +} arm_lms_norm_instance_q15; + + +/** + * @brief Processing function for Q15 normalized LMS filter. + * @param[in] S points to an instance of the Q15 normalized LMS filter structure. + * @param[in] pSrc points to the block of input data. + * @param[in] pRef points to the block of reference data. + * @param[out] pOut points to the block of output data. + * @param[out] pErr points to the block of error data. + * @param[in] blockSize number of samples to process. + */ +void arm_lms_norm_q15( + arm_lms_norm_instance_q15 *S, + q15_t *pSrc, + q15_t *pRef, + q15_t *pOut, + q15_t *pErr, + uint32_t blockSize); + + +/** + * @brief Initialization function for Q15 normalized LMS filter. + * @param[in] S points to an instance of the Q15 normalized LMS filter structure. + * @param[in] numTaps number of filter coefficients. + * @param[in] pCoeffs points to coefficient buffer. + * @param[in] pState points to state buffer. + * @param[in] mu step size that controls filter coefficient updates. + * @param[in] blockSize number of samples to process. + * @param[in] postShift bit shift applied to coefficients. + */ +void arm_lms_norm_init_q15( + arm_lms_norm_instance_q15 *S, + uint16_t numTaps, + q15_t *pCoeffs, + q15_t *pState, + q15_t mu, + uint32_t blockSize, + uint8_t postShift); + + +/** + * @brief Correlation of floating-point sequences. + * @param[in] pSrcA points to the first input sequence. + * @param[in] srcALen length of the first input sequence. + * @param[in] pSrcB points to the second input sequence. + * @param[in] srcBLen length of the second input sequence. + * @param[out] pDst points to the block of output data Length 2 * max(srcALen, srcBLen) - 1. + */ +void arm_correlate_f32( + float32_t *pSrcA, + uint32_t srcALen, + float32_t *pSrcB, + uint32_t srcBLen, + float32_t *pDst); + + +/** +* @brief Correlation of Q15 sequences +* @param[in] pSrcA points to the first input sequence. +* @param[in] srcALen length of the first input sequence. +* @param[in] pSrcB points to the second input sequence. +* @param[in] srcBLen length of the second input sequence. +* @param[out] pDst points to the block of output data Length 2 * max(srcALen, srcBLen) - 1. +* @param[in] pScratch points to scratch buffer of size max(srcALen, srcBLen) + 2*min(srcALen, srcBLen) - 2. +*/ +void arm_correlate_opt_q15( + q15_t *pSrcA, + uint32_t srcALen, + q15_t *pSrcB, + uint32_t srcBLen, + q15_t *pDst, + q15_t *pScratch); + + +/** + * @brief Correlation of Q15 sequences. + * @param[in] pSrcA points to the first input sequence. + * @param[in] srcALen length of the first input sequence. + * @param[in] pSrcB points to the second input sequence. + * @param[in] srcBLen length of the second input sequence. + * @param[out] pDst points to the block of output data Length 2 * max(srcALen, srcBLen) - 1. + */ + +void arm_correlate_q15( + q15_t *pSrcA, + uint32_t srcALen, + q15_t *pSrcB, + uint32_t srcBLen, + q15_t *pDst); + + +/** + * @brief Correlation of Q15 sequences (fast version) for Cortex-M3 and Cortex-M4. + * @param[in] pSrcA points to the first input sequence. + * @param[in] srcALen length of the first input sequence. + * @param[in] pSrcB points to the second input sequence. + * @param[in] srcBLen length of the second input sequence. + * @param[out] pDst points to the block of output data Length 2 * max(srcALen, srcBLen) - 1. + */ + +void arm_correlate_fast_q15( + q15_t *pSrcA, + uint32_t srcALen, + q15_t *pSrcB, + uint32_t srcBLen, + q15_t *pDst); + + +/** + * @brief Correlation of Q15 sequences (fast version) for Cortex-M3 and Cortex-M4. + * @param[in] pSrcA points to the first input sequence. + * @param[in] srcALen length of the first input sequence. + * @param[in] pSrcB points to the second input sequence. + * @param[in] srcBLen length of the second input sequence. + * @param[out] pDst points to the block of output data Length 2 * max(srcALen, srcBLen) - 1. + * @param[in] pScratch points to scratch buffer of size max(srcALen, srcBLen) + 2*min(srcALen, srcBLen) - 2. + */ +void arm_correlate_fast_opt_q15( + q15_t *pSrcA, + uint32_t srcALen, + q15_t *pSrcB, + uint32_t srcBLen, + q15_t *pDst, + q15_t *pScratch); + + +/** + * @brief Correlation of Q31 sequences. + * @param[in] pSrcA points to the first input sequence. + * @param[in] srcALen length of the first input sequence. + * @param[in] pSrcB points to the second input sequence. + * @param[in] srcBLen length of the second input sequence. + * @param[out] pDst points to the block of output data Length 2 * max(srcALen, srcBLen) - 1. + */ +void arm_correlate_q31( + q31_t *pSrcA, + uint32_t srcALen, + q31_t *pSrcB, + uint32_t srcBLen, + q31_t *pDst); + + +/** + * @brief Correlation of Q31 sequences (fast version) for Cortex-M3 and Cortex-M4 + * @param[in] pSrcA points to the first input sequence. + * @param[in] srcALen length of the first input sequence. + * @param[in] pSrcB points to the second input sequence. + * @param[in] srcBLen length of the second input sequence. + * @param[out] pDst points to the block of output data Length 2 * max(srcALen, srcBLen) - 1. + */ +void arm_correlate_fast_q31( + q31_t *pSrcA, + uint32_t srcALen, + q31_t *pSrcB, + uint32_t srcBLen, + q31_t *pDst); + + +/** + * @brief Correlation of Q7 sequences. + * @param[in] pSrcA points to the first input sequence. + * @param[in] srcALen length of the first input sequence. + * @param[in] pSrcB points to the second input sequence. + * @param[in] srcBLen length of the second input sequence. + * @param[out] pDst points to the block of output data Length 2 * max(srcALen, srcBLen) - 1. + * @param[in] pScratch1 points to scratch buffer(of type q15_t) of size max(srcALen, srcBLen) + 2*min(srcALen, srcBLen) - 2. + * @param[in] pScratch2 points to scratch buffer (of type q15_t) of size min(srcALen, srcBLen). + */ +void arm_correlate_opt_q7( + q7_t *pSrcA, + uint32_t srcALen, + q7_t *pSrcB, + uint32_t srcBLen, + q7_t *pDst, + q15_t *pScratch1, + q15_t *pScratch2); + + +/** + * @brief Correlation of Q7 sequences. + * @param[in] pSrcA points to the first input sequence. + * @param[in] srcALen length of the first input sequence. + * @param[in] pSrcB points to the second input sequence. + * @param[in] srcBLen length of the second input sequence. + * @param[out] pDst points to the block of output data Length 2 * max(srcALen, srcBLen) - 1. + */ +void arm_correlate_q7( + q7_t *pSrcA, + uint32_t srcALen, + q7_t *pSrcB, + uint32_t srcBLen, + q7_t *pDst); + + +/** + * @brief Instance structure for the floating-point sparse FIR filter. + */ +typedef struct +{ + uint16_t numTaps; /**< number of coefficients in the filter. */ + uint16_t stateIndex; /**< state buffer index. Points to the oldest sample in the state buffer. */ + float32_t *pState; /**< points to the state buffer array. The array is of length maxDelay+blockSize-1. */ + float32_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps.*/ + uint16_t maxDelay; /**< maximum offset specified by the pTapDelay array. */ + int32_t *pTapDelay; /**< points to the array of delay values. The array is of length numTaps. */ +} arm_fir_sparse_instance_f32; + +/** + * @brief Instance structure for the Q31 sparse FIR filter. + */ +typedef struct +{ + uint16_t numTaps; /**< number of coefficients in the filter. */ + uint16_t stateIndex; /**< state buffer index. Points to the oldest sample in the state buffer. */ + q31_t *pState; /**< points to the state buffer array. The array is of length maxDelay+blockSize-1. */ + q31_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps.*/ + uint16_t maxDelay; /**< maximum offset specified by the pTapDelay array. */ + int32_t *pTapDelay; /**< points to the array of delay values. The array is of length numTaps. */ +} arm_fir_sparse_instance_q31; + +/** + * @brief Instance structure for the Q15 sparse FIR filter. + */ +typedef struct +{ + uint16_t numTaps; /**< number of coefficients in the filter. */ + uint16_t stateIndex; /**< state buffer index. Points to the oldest sample in the state buffer. */ + q15_t *pState; /**< points to the state buffer array. The array is of length maxDelay+blockSize-1. */ + q15_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps.*/ + uint16_t maxDelay; /**< maximum offset specified by the pTapDelay array. */ + int32_t *pTapDelay; /**< points to the array of delay values. The array is of length numTaps. */ +} arm_fir_sparse_instance_q15; + +/** + * @brief Instance structure for the Q7 sparse FIR filter. + */ +typedef struct +{ + uint16_t numTaps; /**< number of coefficients in the filter. */ + uint16_t stateIndex; /**< state buffer index. Points to the oldest sample in the state buffer. */ + q7_t *pState; /**< points to the state buffer array. The array is of length maxDelay+blockSize-1. */ + q7_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps.*/ + uint16_t maxDelay; /**< maximum offset specified by the pTapDelay array. */ + int32_t *pTapDelay; /**< points to the array of delay values. The array is of length numTaps. */ +} arm_fir_sparse_instance_q7; + + +/** + * @brief Processing function for the floating-point sparse FIR filter. + * @param[in] S points to an instance of the floating-point sparse FIR structure. + * @param[in] pSrc points to the block of input data. + * @param[out] pDst points to the block of output data + * @param[in] pScratchIn points to a temporary buffer of size blockSize. + * @param[in] blockSize number of input samples to process per call. + */ +void arm_fir_sparse_f32( + arm_fir_sparse_instance_f32 *S, + float32_t *pSrc, + float32_t *pDst, + float32_t *pScratchIn, + uint32_t blockSize); + + +/** + * @brief Initialization function for the floating-point sparse FIR filter. + * @param[in,out] S points to an instance of the floating-point sparse FIR structure. + * @param[in] numTaps number of nonzero coefficients in the filter. + * @param[in] pCoeffs points to the array of filter coefficients. + * @param[in] pState points to the state buffer. + * @param[in] pTapDelay points to the array of offset times. + * @param[in] maxDelay maximum offset time supported. + * @param[in] blockSize number of samples that will be processed per block. + */ +void arm_fir_sparse_init_f32( + arm_fir_sparse_instance_f32 *S, + uint16_t numTaps, + float32_t *pCoeffs, + float32_t *pState, + int32_t *pTapDelay, + uint16_t maxDelay, + uint32_t blockSize); + + +/** + * @brief Processing function for the Q31 sparse FIR filter. + * @param[in] S points to an instance of the Q31 sparse FIR structure. + * @param[in] pSrc points to the block of input data. + * @param[out] pDst points to the block of output data + * @param[in] pScratchIn points to a temporary buffer of size blockSize. + * @param[in] blockSize number of input samples to process per call. + */ +void arm_fir_sparse_q31( + arm_fir_sparse_instance_q31 *S, + q31_t *pSrc, + q31_t *pDst, + q31_t *pScratchIn, + uint32_t blockSize); + + +/** + * @brief Initialization function for the Q31 sparse FIR filter. + * @param[in,out] S points to an instance of the Q31 sparse FIR structure. + * @param[in] numTaps number of nonzero coefficients in the filter. + * @param[in] pCoeffs points to the array of filter coefficients. + * @param[in] pState points to the state buffer. + * @param[in] pTapDelay points to the array of offset times. + * @param[in] maxDelay maximum offset time supported. + * @param[in] blockSize number of samples that will be processed per block. + */ +void arm_fir_sparse_init_q31( + arm_fir_sparse_instance_q31 *S, + uint16_t numTaps, + q31_t *pCoeffs, + q31_t *pState, + int32_t *pTapDelay, + uint16_t maxDelay, + uint32_t blockSize); + + +/** + * @brief Processing function for the Q15 sparse FIR filter. + * @param[in] S points to an instance of the Q15 sparse FIR structure. + * @param[in] pSrc points to the block of input data. + * @param[out] pDst points to the block of output data + * @param[in] pScratchIn points to a temporary buffer of size blockSize. + * @param[in] pScratchOut points to a temporary buffer of size blockSize. + * @param[in] blockSize number of input samples to process per call. + */ +void arm_fir_sparse_q15( + arm_fir_sparse_instance_q15 *S, + q15_t *pSrc, + q15_t *pDst, + q15_t *pScratchIn, + q31_t *pScratchOut, + uint32_t blockSize); + + +/** + * @brief Initialization function for the Q15 sparse FIR filter. + * @param[in,out] S points to an instance of the Q15 sparse FIR structure. + * @param[in] numTaps number of nonzero coefficients in the filter. + * @param[in] pCoeffs points to the array of filter coefficients. + * @param[in] pState points to the state buffer. + * @param[in] pTapDelay points to the array of offset times. + * @param[in] maxDelay maximum offset time supported. + * @param[in] blockSize number of samples that will be processed per block. + */ +void arm_fir_sparse_init_q15( + arm_fir_sparse_instance_q15 *S, + uint16_t numTaps, + q15_t *pCoeffs, + q15_t *pState, + int32_t *pTapDelay, + uint16_t maxDelay, + uint32_t blockSize); + + +/** + * @brief Processing function for the Q7 sparse FIR filter. + * @param[in] S points to an instance of the Q7 sparse FIR structure. + * @param[in] pSrc points to the block of input data. + * @param[out] pDst points to the block of output data + * @param[in] pScratchIn points to a temporary buffer of size blockSize. + * @param[in] pScratchOut points to a temporary buffer of size blockSize. + * @param[in] blockSize number of input samples to process per call. + */ +void arm_fir_sparse_q7( + arm_fir_sparse_instance_q7 *S, + q7_t *pSrc, + q7_t *pDst, + q7_t *pScratchIn, + q31_t *pScratchOut, + uint32_t blockSize); + + +/** + * @brief Initialization function for the Q7 sparse FIR filter. + * @param[in,out] S points to an instance of the Q7 sparse FIR structure. + * @param[in] numTaps number of nonzero coefficients in the filter. + * @param[in] pCoeffs points to the array of filter coefficients. + * @param[in] pState points to the state buffer. + * @param[in] pTapDelay points to the array of offset times. + * @param[in] maxDelay maximum offset time supported. + * @param[in] blockSize number of samples that will be processed per block. + */ +void arm_fir_sparse_init_q7( + arm_fir_sparse_instance_q7 *S, + uint16_t numTaps, + q7_t *pCoeffs, + q7_t *pState, + int32_t *pTapDelay, + uint16_t maxDelay, + uint32_t blockSize); + + +/** + * @brief Floating-point sin_cos function. + * @param[in] theta input value in degrees + * @param[out] pSinVal points to the processed sine output. + * @param[out] pCosVal points to the processed cos output. + */ +void arm_sin_cos_f32( + float32_t theta, + float32_t *pSinVal, + float32_t *pCosVal); + + +/** + * @brief Q31 sin_cos function. + * @param[in] theta scaled input value in degrees + * @param[out] pSinVal points to the processed sine output. + * @param[out] pCosVal points to the processed cosine output. + */ +void arm_sin_cos_q31( + q31_t theta, + q31_t *pSinVal, + q31_t *pCosVal); + + +/** + * @brief Floating-point complex conjugate. + * @param[in] pSrc points to the input vector + * @param[out] pDst points to the output vector + * @param[in] numSamples number of complex samples in each vector + */ +void arm_cmplx_conj_f32( + float32_t *pSrc, + float32_t *pDst, + uint32_t numSamples); + +/** + * @brief Q31 complex conjugate. + * @param[in] pSrc points to the input vector + * @param[out] pDst points to the output vector + * @param[in] numSamples number of complex samples in each vector + */ +void arm_cmplx_conj_q31( + q31_t *pSrc, + q31_t *pDst, + uint32_t numSamples); + + +/** + * @brief Q15 complex conjugate. + * @param[in] pSrc points to the input vector + * @param[out] pDst points to the output vector + * @param[in] numSamples number of complex samples in each vector + */ +void arm_cmplx_conj_q15( + q15_t *pSrc, + q15_t *pDst, + uint32_t numSamples); + + +/** + * @brief Floating-point complex magnitude squared + * @param[in] pSrc points to the complex input vector + * @param[out] pDst points to the real output vector + * @param[in] numSamples number of complex samples in the input vector + */ +void arm_cmplx_mag_squared_f32( + float32_t *pSrc, + float32_t *pDst, + uint32_t numSamples); + + +/** + * @brief Q31 complex magnitude squared + * @param[in] pSrc points to the complex input vector + * @param[out] pDst points to the real output vector + * @param[in] numSamples number of complex samples in the input vector + */ +void arm_cmplx_mag_squared_q31( + q31_t *pSrc, + q31_t *pDst, + uint32_t numSamples); + + +/** + * @brief Q15 complex magnitude squared + * @param[in] pSrc points to the complex input vector + * @param[out] pDst points to the real output vector + * @param[in] numSamples number of complex samples in the input vector + */ +void arm_cmplx_mag_squared_q15( + q15_t *pSrc, + q15_t *pDst, + uint32_t numSamples); + + +/** + * @ingroup groupController + */ + +/** + * @defgroup PID PID Motor Control + * + * A Proportional Integral Derivative (PID) controller is a generic feedback control + * loop mechanism widely used in industrial control systems. + * A PID controller is the most commonly used type of feedback controller. + * + * This set of functions implements (PID) controllers + * for Q15, Q31, and floating-point data types. The functions operate on a single sample + * of data and each call to the function returns a single processed value. + * S points to an instance of the PID control data structure. in + * is the input sample value. The functions return the output value. + * + * \par Algorithm: + * 
+ *    y[n] = y[n-1] + A0 * x[n] + A1 * x[n-1] + A2 * x[n-2]
+ *    A0 = Kp + Ki + Kd
+ *    A1 = (-Kp ) - (2 * Kd )
+ *    A2 = Kd
+ * + * \par + * where \c Kp is proportional constant, \c Ki is Integral constant and \c Kd is Derivative constant + * + * \par + * \image html PID.gif "Proportional Integral Derivative Controller" + * + * \par + * The PID controller calculates an "error" value as the difference between + * the measured output and the reference input. + * The controller attempts to minimize the error by adjusting the process control inputs. + * The proportional value determines the reaction to the current error, + * the integral value determines the reaction based on the sum of recent errors, + * and the derivative value determines the reaction based on the rate at which the error has been changing. + * + * \par Instance Structure + * The Gains A0, A1, A2 and state variables for a PID controller are stored together in an instance data structure. + * A separate instance structure must be defined for each PID Controller. + * There are separate instance structure declarations for each of the 3 supported data types. + * + * \par Reset Functions + * There is also an associated reset function for each data type which clears the state array. + * + * \par Initialization Functions + * There is also an associated initialization function for each data type. + * The initialization function performs the following operations: + * - Initializes the Gains A0, A1, A2 from Kp,Ki, Kd gains. + * - Zeros out the values in the state buffer. + * + * \par + * Instance structure cannot be placed into a const data section and it is recommended to use the initialization function. + * + * \par Fixed-Point Behavior + * Care must be taken when using the fixed-point versions of the PID Controller functions. + * In particular, the overflow and saturation behavior of the accumulator used in each function must be considered. + * Refer to the function specific documentation below for usage guidelines. + */ + +/** + * @addtogroup PID + * @{ + */ + +/** + * @brief Process function for the floating-point PID Control. + * @param[in,out] S is an instance of the floating-point PID Control structure + * @param[in] in input sample to process + * @return out processed output sample. + */ +static __INLINE float32_t arm_pid_f32( + arm_pid_instance_f32 *S, + float32_t in) +{ + float32_t out; + + /* y[n] = y[n-1] + A0 * x[n] + A1 * x[n-1] + A2 * x[n-2] */ + out = (S->A0 * in) + + (S->A1 * S->state[0]) + (S->A2 * S->state[1]) + (S->state[2]); + + /* Update state */ + S->state[1] = S->state[0]; + S->state[0] = in; + S->state[2] = out; + + /* return to application */ + return (out); + +} + +/** + * @brief Process function for the Q31 PID Control. + * @param[in,out] S points to an instance of the Q31 PID Control structure + * @param[in] in input sample to process + * @return out processed output sample. + * + * Scaling and Overflow Behavior: + * \par + * The function is implemented using an internal 64-bit accumulator. + * The accumulator has a 2.62 format and maintains full precision of the intermediate multiplication results but provides only a single guard bit. + * Thus, if the accumulator result overflows it wraps around rather than clip. + * In order to avoid overflows completely the input signal must be scaled down by 2 bits as there are four additions. + * After all multiply-accumulates are performed, the 2.62 accumulator is truncated to 1.32 format and then saturated to 1.31 format. + */ +static __INLINE q31_t arm_pid_q31( + arm_pid_instance_q31 *S, + q31_t in) +{ + q63_t acc; + q31_t out; + + /* acc = A0 * x[n] */ + acc = (q63_t) S->A0 * in; + + /* acc += A1 * x[n-1] */ + acc += (q63_t) S->A1 * S->state[0]; + + /* acc += A2 * x[n-2] */ + acc += (q63_t) S->A2 * S->state[1]; + + /* convert output to 1.31 format to add y[n-1] */ + out = (q31_t)(acc >> 31u); + + /* out += y[n-1] */ + out += S->state[2]; + + /* Update state */ + S->state[1] = S->state[0]; + S->state[0] = in; + S->state[2] = out; + + /* return to application */ + return (out); +} + + +/** + * @brief Process function for the Q15 PID Control. + * @param[in,out] S points to an instance of the Q15 PID Control structure + * @param[in] in input sample to process + * @return out processed output sample. + * + * Scaling and Overflow Behavior: + * \par + * The function is implemented using a 64-bit internal accumulator. + * Both Gains and state variables are represented in 1.15 format and multiplications yield a 2.30 result. + * The 2.30 intermediate results are accumulated in a 64-bit accumulator in 34.30 format. + * There is no risk of internal overflow with this approach and the full precision of intermediate multiplications is preserved. + * After all additions have been performed, the accumulator is truncated to 34.15 format by discarding low 15 bits. + * Lastly, the accumulator is saturated to yield a result in 1.15 format. + */ +static __INLINE q15_t arm_pid_q15( + arm_pid_instance_q15 *S, + q15_t in) +{ + q63_t acc; + q15_t out; + +#ifndef ARM_MATH_CM0_FAMILY + __SIMD32_TYPE *vstate; + + /* Implementation of PID controller */ + + /* acc = A0 * x[n] */ + acc = (q31_t) __SMUAD((uint32_t)S->A0, (uint32_t)in); + + /* acc += A1 * x[n-1] + A2 * x[n-2] */ + vstate = __SIMD32_CONST(S->state); + acc = (q63_t)__SMLALD((uint32_t)S->A1, (uint32_t) * vstate, (uint64_t)acc); +#else + /* acc = A0 * x[n] */ + acc = ((q31_t) S->A0) * in; + + /* acc += A1 * x[n-1] + A2 * x[n-2] */ + acc += (q31_t) S->A1 * S->state[0]; + acc += (q31_t) S->A2 * S->state[1]; +#endif + + /* acc += y[n-1] */ + acc += (q31_t) S->state[2] << 15; + + /* saturate the output */ + out = (q15_t)(__SSAT((acc >> 15), 16)); + + /* Update state */ + S->state[1] = S->state[0]; + S->state[0] = in; + S->state[2] = out; + + /* return to application */ + return (out); +} + +/** + * @} end of PID group + */ + + +/** + * @brief Floating-point matrix inverse. + * @param[in] src points to the instance of the input floating-point matrix structure. + * @param[out] dst points to the instance of the output floating-point matrix structure. + * @return The function returns ARM_MATH_SIZE_MISMATCH, if the dimensions do not match. + * If the input matrix is singular (does not have an inverse), then the algorithm terminates and returns error status ARM_MATH_SINGULAR. + */ +arm_status arm_mat_inverse_f32( + const arm_matrix_instance_f32 *src, + arm_matrix_instance_f32 *dst); + + +/** + * @brief Floating-point matrix inverse. + * @param[in] src points to the instance of the input floating-point matrix structure. + * @param[out] dst points to the instance of the output floating-point matrix structure. + * @return The function returns ARM_MATH_SIZE_MISMATCH, if the dimensions do not match. + * If the input matrix is singular (does not have an inverse), then the algorithm terminates and returns error status ARM_MATH_SINGULAR. + */ +arm_status arm_mat_inverse_f64( + const arm_matrix_instance_f64 *src, + arm_matrix_instance_f64 *dst); + + + +/** + * @ingroup groupController + */ + +/** + * @defgroup clarke Vector Clarke Transform + * Forward Clarke transform converts the instantaneous stator phases into a two-coordinate time invariant vector. + * Generally the Clarke transform uses three-phase currents Ia, Ib and Ic to calculate currents + * in the two-phase orthogonal stator axis Ialpha and Ibeta. + * When Ialpha is superposed with Ia as shown in the figure below + * \image html clarke.gif Stator current space vector and its components in (a,b). + * and Ia + Ib + Ic = 0, in this condition Ialpha and Ibeta + * can be calculated using only Ia and Ib. + * + * The function operates on a single sample of data and each call to the function returns the processed output. + * The library provides separate functions for Q31 and floating-point data types. + * \par Algorithm + * \image html clarkeFormula.gif + * where Ia and Ib are the instantaneous stator phases and + * pIalpha and pIbeta are the two coordinates of time invariant vector. + * \par Fixed-Point Behavior + * Care must be taken when using the Q31 version of the Clarke transform. + * In particular, the overflow and saturation behavior of the accumulator used must be considered. + * Refer to the function specific documentation below for usage guidelines. + */ + +/** + * @addtogroup clarke + * @{ + */ + +/** + * + * @brief Floating-point Clarke transform + * @param[in] Ia input three-phase coordinate a + * @param[in] Ib input three-phase coordinate b + * @param[out] pIalpha points to output two-phase orthogonal vector axis alpha + * @param[out] pIbeta points to output two-phase orthogonal vector axis beta + */ +static __INLINE void arm_clarke_f32( + float32_t Ia, + float32_t Ib, + float32_t *pIalpha, + float32_t *pIbeta) +{ + /* Calculate pIalpha using the equation, pIalpha = Ia */ + *pIalpha = Ia; + + /* Calculate pIbeta using the equation, pIbeta = (1/sqrt(3)) * Ia + (2/sqrt(3)) * Ib */ + *pIbeta = ((float32_t) 0.57735026919 * Ia + (float32_t) 1.15470053838 * Ib); +} + + +/** + * @brief Clarke transform for Q31 version + * @param[in] Ia input three-phase coordinate a + * @param[in] Ib input three-phase coordinate b + * @param[out] pIalpha points to output two-phase orthogonal vector axis alpha + * @param[out] pIbeta points to output two-phase orthogonal vector axis beta + * + * Scaling and Overflow Behavior: + * \par + * The function is implemented using an internal 32-bit accumulator. + * The accumulator maintains 1.31 format by truncating lower 31 bits of the intermediate multiplication in 2.62 format. + * There is saturation on the addition, hence there is no risk of overflow. + */ +static __INLINE void arm_clarke_q31( + q31_t Ia, + q31_t Ib, + q31_t *pIalpha, + q31_t *pIbeta) +{ + q31_t product1, product2; /* Temporary variables used to store intermediate results */ + + /* Calculating pIalpha from Ia by equation pIalpha = Ia */ + *pIalpha = Ia; + + /* Intermediate product is calculated by (1/(sqrt(3)) * Ia) */ + product1 = (q31_t)(((q63_t) Ia * 0x24F34E8B) >> 30); + + /* Intermediate product is calculated by (2/sqrt(3) * Ib) */ + product2 = (q31_t)(((q63_t) Ib * 0x49E69D16) >> 30); + + /* pIbeta is calculated by adding the intermediate products */ + *pIbeta = __QADD(product1, product2); +} + +/** + * @} end of clarke group + */ + +/** + * @brief Converts the elements of the Q7 vector to Q31 vector. + * @param[in] pSrc input pointer + * @param[out] pDst output pointer + * @param[in] blockSize number of samples to process + */ +void arm_q7_to_q31( + q7_t *pSrc, + q31_t *pDst, + uint32_t blockSize); + + + +/** + * @ingroup groupController + */ + +/** + * @defgroup inv_clarke Vector Inverse Clarke Transform + * Inverse Clarke transform converts the two-coordinate time invariant vector into instantaneous stator phases. + * + * The function operates on a single sample of data and each call to the function returns the processed output. + * The library provides separate functions for Q31 and floating-point data types. + * \par Algorithm + * \image html clarkeInvFormula.gif + * where pIa and pIb are the instantaneous stator phases and + * Ialpha and Ibeta are the two coordinates of time invariant vector. + * \par Fixed-Point Behavior + * Care must be taken when using the Q31 version of the Clarke transform. + * In particular, the overflow and saturation behavior of the accumulator used must be considered. + * Refer to the function specific documentation below for usage guidelines. + */ + +/** + * @addtogroup inv_clarke + * @{ + */ + +/** +* @brief Floating-point Inverse Clarke transform +* @param[in] Ialpha input two-phase orthogonal vector axis alpha +* @param[in] Ibeta input two-phase orthogonal vector axis beta +* @param[out] pIa points to output three-phase coordinate a +* @param[out] pIb points to output three-phase coordinate b +*/ +static __INLINE void arm_inv_clarke_f32( + float32_t Ialpha, + float32_t Ibeta, + float32_t *pIa, + float32_t *pIb) +{ + /* Calculating pIa from Ialpha by equation pIa = Ialpha */ + *pIa = Ialpha; + + /* Calculating pIb from Ialpha and Ibeta by equation pIb = -(1/2) * Ialpha + (sqrt(3)/2) * Ibeta */ + *pIb = -0.5f * Ialpha + 0.8660254039f * Ibeta; +} + + +/** + * @brief Inverse Clarke transform for Q31 version + * @param[in] Ialpha input two-phase orthogonal vector axis alpha + * @param[in] Ibeta input two-phase orthogonal vector axis beta + * @param[out] pIa points to output three-phase coordinate a + * @param[out] pIb points to output three-phase coordinate b + * + * Scaling and Overflow Behavior: + * \par + * The function is implemented using an internal 32-bit accumulator. + * The accumulator maintains 1.31 format by truncating lower 31 bits of the intermediate multiplication in 2.62 format. + * There is saturation on the subtraction, hence there is no risk of overflow. + */ +static __INLINE void arm_inv_clarke_q31( + q31_t Ialpha, + q31_t Ibeta, + q31_t *pIa, + q31_t *pIb) +{ + q31_t product1, product2; /* Temporary variables used to store intermediate results */ + + /* Calculating pIa from Ialpha by equation pIa = Ialpha */ + *pIa = Ialpha; + + /* Intermediate product is calculated by (1/(2*sqrt(3)) * Ia) */ + product1 = (q31_t)(((q63_t)(Ialpha) * (0x40000000)) >> 31); + + /* Intermediate product is calculated by (1/sqrt(3) * pIb) */ + product2 = (q31_t)(((q63_t)(Ibeta) * (0x6ED9EBA1)) >> 31); + + /* pIb is calculated by subtracting the products */ + *pIb = __QSUB(product2, product1); +} + +/** + * @} end of inv_clarke group + */ + +/** + * @brief Converts the elements of the Q7 vector to Q15 vector. + * @param[in] pSrc input pointer + * @param[out] pDst output pointer + * @param[in] blockSize number of samples to process + */ +void arm_q7_to_q15( + q7_t *pSrc, + q15_t *pDst, + uint32_t blockSize); + + + +/** + * @ingroup groupController + */ + +/** + * @defgroup park Vector Park Transform + * + * Forward Park transform converts the input two-coordinate vector to flux and torque components. + * The Park transform can be used to realize the transformation of the Ialpha and the Ibeta currents + * from the stationary to the moving reference frame and control the spatial relationship between + * the stator vector current and rotor flux vector. + * If we consider the d axis aligned with the rotor flux, the diagram below shows the + * current vector and the relationship from the two reference frames: + * \image html park.gif "Stator current space vector and its component in (a,b) and in the d,q rotating reference frame" + * + * The function operates on a single sample of data and each call to the function returns the processed output. + * The library provides separate functions for Q31 and floating-point data types. + * \par Algorithm + * \image html parkFormula.gif + * where Ialpha and Ibeta are the stator vector components, + * pId and pIq are rotor vector components and cosVal and sinVal are the + * cosine and sine values of theta (rotor flux position). + * \par Fixed-Point Behavior + * Care must be taken when using the Q31 version of the Park transform. + * In particular, the overflow and saturation behavior of the accumulator used must be considered. + * Refer to the function specific documentation below for usage guidelines. + */ + +/** + * @addtogroup park + * @{ + */ + +/** + * @brief Floating-point Park transform + * @param[in] Ialpha input two-phase vector coordinate alpha + * @param[in] Ibeta input two-phase vector coordinate beta + * @param[out] pId points to output rotor reference frame d + * @param[out] pIq points to output rotor reference frame q + * @param[in] sinVal sine value of rotation angle theta + * @param[in] cosVal cosine value of rotation angle theta + * + * The function implements the forward Park transform. + * + */ +static __INLINE void arm_park_f32( + float32_t Ialpha, + float32_t Ibeta, + float32_t *pId, + float32_t *pIq, + float32_t sinVal, + float32_t cosVal) +{ + /* Calculate pId using the equation, pId = Ialpha * cosVal + Ibeta * sinVal */ + *pId = Ialpha * cosVal + Ibeta * sinVal; + + /* Calculate pIq using the equation, pIq = - Ialpha * sinVal + Ibeta * cosVal */ + *pIq = -Ialpha * sinVal + Ibeta * cosVal; +} + + +/** + * @brief Park transform for Q31 version + * @param[in] Ialpha input two-phase vector coordinate alpha + * @param[in] Ibeta input two-phase vector coordinate beta + * @param[out] pId points to output rotor reference frame d + * @param[out] pIq points to output rotor reference frame q + * @param[in] sinVal sine value of rotation angle theta + * @param[in] cosVal cosine value of rotation angle theta + * + * Scaling and Overflow Behavior: + * \par + * The function is implemented using an internal 32-bit accumulator. + * The accumulator maintains 1.31 format by truncating lower 31 bits of the intermediate multiplication in 2.62 format. + * There is saturation on the addition and subtraction, hence there is no risk of overflow. + */ +static __INLINE void arm_park_q31( + q31_t Ialpha, + q31_t Ibeta, + q31_t *pId, + q31_t *pIq, + q31_t sinVal, + q31_t cosVal) +{ + q31_t product1, product2; /* Temporary variables used to store intermediate results */ + q31_t product3, product4; /* Temporary variables used to store intermediate results */ + + /* Intermediate product is calculated by (Ialpha * cosVal) */ + product1 = (q31_t)(((q63_t)(Ialpha) * (cosVal)) >> 31); + + /* Intermediate product is calculated by (Ibeta * sinVal) */ + product2 = (q31_t)(((q63_t)(Ibeta) * (sinVal)) >> 31); + + + /* Intermediate product is calculated by (Ialpha * sinVal) */ + product3 = (q31_t)(((q63_t)(Ialpha) * (sinVal)) >> 31); + + /* Intermediate product is calculated by (Ibeta * cosVal) */ + product4 = (q31_t)(((q63_t)(Ibeta) * (cosVal)) >> 31); + + /* Calculate pId by adding the two intermediate products 1 and 2 */ + *pId = __QADD(product1, product2); + + /* Calculate pIq by subtracting the two intermediate products 3 from 4 */ + *pIq = __QSUB(product4, product3); +} + +/** + * @} end of park group + */ + +/** + * @brief Converts the elements of the Q7 vector to floating-point vector. + * @param[in] pSrc is input pointer + * @param[out] pDst is output pointer + * @param[in] blockSize is the number of samples to process + */ +void arm_q7_to_float( + q7_t *pSrc, + float32_t *pDst, + uint32_t blockSize); + + +/** + * @ingroup groupController + */ + +/** + * @defgroup inv_park Vector Inverse Park transform + * Inverse Park transform converts the input flux and torque components to two-coordinate vector. + * + * The function operates on a single sample of data and each call to the function returns the processed output. + * The library provides separate functions for Q31 and floating-point data types. + * \par Algorithm + * \image html parkInvFormula.gif + * where pIalpha and pIbeta are the stator vector components, + * Id and Iq are rotor vector components and cosVal and sinVal are the + * cosine and sine values of theta (rotor flux position). + * \par Fixed-Point Behavior + * Care must be taken when using the Q31 version of the Park transform. + * In particular, the overflow and saturation behavior of the accumulator used must be considered. + * Refer to the function specific documentation below for usage guidelines. + */ + +/** + * @addtogroup inv_park + * @{ + */ + +/** +* @brief Floating-point Inverse Park transform +* @param[in] Id input coordinate of rotor reference frame d +* @param[in] Iq input coordinate of rotor reference frame q +* @param[out] pIalpha points to output two-phase orthogonal vector axis alpha +* @param[out] pIbeta points to output two-phase orthogonal vector axis beta +* @param[in] sinVal sine value of rotation angle theta +* @param[in] cosVal cosine value of rotation angle theta +*/ +static __INLINE void arm_inv_park_f32( + float32_t Id, + float32_t Iq, + float32_t *pIalpha, + float32_t *pIbeta, + float32_t sinVal, + float32_t cosVal) +{ + /* Calculate pIalpha using the equation, pIalpha = Id * cosVal - Iq * sinVal */ + *pIalpha = Id * cosVal - Iq * sinVal; + + /* Calculate pIbeta using the equation, pIbeta = Id * sinVal + Iq * cosVal */ + *pIbeta = Id * sinVal + Iq * cosVal; +} + + +/** + * @brief Inverse Park transform for Q31 version + * @param[in] Id input coordinate of rotor reference frame d + * @param[in] Iq input coordinate of rotor reference frame q + * @param[out] pIalpha points to output two-phase orthogonal vector axis alpha + * @param[out] pIbeta points to output two-phase orthogonal vector axis beta + * @param[in] sinVal sine value of rotation angle theta + * @param[in] cosVal cosine value of rotation angle theta + * + * Scaling and Overflow Behavior: + * \par + * The function is implemented using an internal 32-bit accumulator. + * The accumulator maintains 1.31 format by truncating lower 31 bits of the intermediate multiplication in 2.62 format. + * There is saturation on the addition, hence there is no risk of overflow. + */ +static __INLINE void arm_inv_park_q31( + q31_t Id, + q31_t Iq, + q31_t *pIalpha, + q31_t *pIbeta, + q31_t sinVal, + q31_t cosVal) +{ + q31_t product1, product2; /* Temporary variables used to store intermediate results */ + q31_t product3, product4; /* Temporary variables used to store intermediate results */ + + /* Intermediate product is calculated by (Id * cosVal) */ + product1 = (q31_t)(((q63_t)(Id) * (cosVal)) >> 31); + + /* Intermediate product is calculated by (Iq * sinVal) */ + product2 = (q31_t)(((q63_t)(Iq) * (sinVal)) >> 31); + + + /* Intermediate product is calculated by (Id * sinVal) */ + product3 = (q31_t)(((q63_t)(Id) * (sinVal)) >> 31); + + /* Intermediate product is calculated by (Iq * cosVal) */ + product4 = (q31_t)(((q63_t)(Iq) * (cosVal)) >> 31); + + /* Calculate pIalpha by using the two intermediate products 1 and 2 */ + *pIalpha = __QSUB(product1, product2); + + /* Calculate pIbeta by using the two intermediate products 3 and 4 */ + *pIbeta = __QADD(product4, product3); +} + +/** + * @} end of Inverse park group + */ + + +/** + * @brief Converts the elements of the Q31 vector to floating-point vector. + * @param[in] pSrc is input pointer + * @param[out] pDst is output pointer + * @param[in] blockSize is the number of samples to process + */ +void arm_q31_to_float( + q31_t *pSrc, + float32_t *pDst, + uint32_t blockSize); + +/** + * @ingroup groupInterpolation + */ + +/** + * @defgroup LinearInterpolate Linear Interpolation + * + * Linear interpolation is a method of curve fitting using linear polynomials. + * Linear interpolation works by effectively drawing a straight line between two neighboring samples and returning the appropriate point along that line + * + * \par + * \image html LinearInterp.gif "Linear interpolation" + * + * \par + * A Linear Interpolate function calculates an output value(y), for the input(x) + * using linear interpolation of the input values x0, x1( nearest input values) and the output values y0 and y1(nearest output values) + * + * \par Algorithm: + * 
+ *       y = y0 + (x - x0) * ((y1 - y0)/(x1-x0))
+ *       where x0, x1 are nearest values of input x
+ *             y0, y1 are nearest values to output y
+ *
+ * + * \par + * This set of functions implements Linear interpolation process + * for Q7, Q15, Q31, and floating-point data types. The functions operate on a single + * sample of data and each call to the function returns a single processed value. + * S points to an instance of the Linear Interpolate function data structure. + * x is the input sample value. The functions returns the output value. + * + * \par + * if x is outside of the table boundary, Linear interpolation returns first value of the table + * if x is below input range and returns last value of table if x is above range. + */ + +/** + * @addtogroup LinearInterpolate + * @{ + */ + +/** + * @brief Process function for the floating-point Linear Interpolation Function. + * @param[in,out] S is an instance of the floating-point Linear Interpolation structure + * @param[in] x input sample to process + * @return y processed output sample. + * + */ +static __INLINE float32_t arm_linear_interp_f32( + arm_linear_interp_instance_f32 *S, + float32_t x) +{ + float32_t y; + float32_t x0, x1; /* Nearest input values */ + float32_t y0, y1; /* Nearest output values */ + float32_t xSpacing = S->xSpacing; /* spacing between input values */ + int32_t i; /* Index variable */ + float32_t *pYData = S->pYData; /* pointer to output table */ + + /* Calculation of index */ + i = (int32_t)((x - S->x1) / xSpacing); + + if (i < 0) + { + /* Iniatilize output for below specified range as least output value of table */ + y = pYData[0]; + } + else if ((uint32_t)i >= S->nValues) + { + /* Iniatilize output for above specified range as last output value of table */ + y = pYData[S->nValues - 1]; + } + else + { + /* Calculation of nearest input values */ + x0 = S->x1 + i * xSpacing; + x1 = S->x1 + (i + 1) * xSpacing; + + /* Read of nearest output values */ + y0 = pYData[i]; + y1 = pYData[i + 1]; + + /* Calculation of output */ + y = y0 + (x - x0) * ((y1 - y0) / (x1 - x0)); + + } + + /* returns output value */ + return (y); +} + + +/** +* +* @brief Process function for the Q31 Linear Interpolation Function. +* @param[in] pYData pointer to Q31 Linear Interpolation table +* @param[in] x input sample to process +* @param[in] nValues number of table values +* @return y processed output sample. +* +* \par +* Input sample x is in 12.20 format which contains 12 bits for table index and 20 bits for fractional part. +* This function can support maximum of table size 2^12. +* +*/ +static __INLINE q31_t arm_linear_interp_q31( + q31_t *pYData, + q31_t x, + uint32_t nValues) +{ + q31_t y; /* output */ + q31_t y0, y1; /* Nearest output values */ + q31_t fract; /* fractional part */ + int32_t index; /* Index to read nearest output values */ + + /* Input is in 12.20 format */ + /* 12 bits for the table index */ + /* Index value calculation */ + index = ((x & (q31_t)0xFFF00000) >> 20); + + if (index >= (int32_t)(nValues - 1)) + { + return (pYData[nValues - 1]); + } + else if (index < 0) + { + return (pYData[0]); + } + else + { + /* 20 bits for the fractional part */ + /* shift left by 11 to keep fract in 1.31 format */ + fract = (x & 0x000FFFFF) << 11; + + /* Read two nearest output values from the index in 1.31(q31) format */ + y0 = pYData[index]; + y1 = pYData[index + 1]; + + /* Calculation of y0 * (1-fract) and y is in 2.30 format */ + y = ((q31_t)((q63_t) y0 * (0x7FFFFFFF - fract) >> 32)); + + /* Calculation of y0 * (1-fract) + y1 *fract and y is in 2.30 format */ + y += ((q31_t)(((q63_t) y1 * fract) >> 32)); + + /* Convert y to 1.31 format */ + return (y << 1u); + } +} + + +/** + * + * @brief Process function for the Q15 Linear Interpolation Function. + * @param[in] pYData pointer to Q15 Linear Interpolation table + * @param[in] x input sample to process + * @param[in] nValues number of table values + * @return y processed output sample. + * + * \par + * Input sample x is in 12.20 format which contains 12 bits for table index and 20 bits for fractional part. + * This function can support maximum of table size 2^12. + * + */ +static __INLINE q15_t arm_linear_interp_q15( + q15_t *pYData, + q31_t x, + uint32_t nValues) +{ + q63_t y; /* output */ + q15_t y0, y1; /* Nearest output values */ + q31_t fract; /* fractional part */ + int32_t index; /* Index to read nearest output values */ + + /* Input is in 12.20 format */ + /* 12 bits for the table index */ + /* Index value calculation */ + index = ((x & (int32_t)0xFFF00000) >> 20); + + if (index >= (int32_t)(nValues - 1)) + { + return (pYData[nValues - 1]); + } + else if (index < 0) + { + return (pYData[0]); + } + else + { + /* 20 bits for the fractional part */ + /* fract is in 12.20 format */ + fract = (x & 0x000FFFFF); + + /* Read two nearest output values from the index */ + y0 = pYData[index]; + y1 = pYData[index + 1]; + + /* Calculation of y0 * (1-fract) and y is in 13.35 format */ + y = ((q63_t) y0 * (0xFFFFF - fract)); + + /* Calculation of (y0 * (1-fract) + y1 * fract) and y is in 13.35 format */ + y += ((q63_t) y1 * (fract)); + + /* convert y to 1.15 format */ + return (q15_t)(y >> 20); + } +} + + +/** + * + * @brief Process function for the Q7 Linear Interpolation Function. + * @param[in] pYData pointer to Q7 Linear Interpolation table + * @param[in] x input sample to process + * @param[in] nValues number of table values + * @return y processed output sample. + * + * \par + * Input sample x is in 12.20 format which contains 12 bits for table index and 20 bits for fractional part. + * This function can support maximum of table size 2^12. + */ +static __INLINE q7_t arm_linear_interp_q7( + q7_t *pYData, + q31_t x, + uint32_t nValues) +{ + q31_t y; /* output */ + q7_t y0, y1; /* Nearest output values */ + q31_t fract; /* fractional part */ + uint32_t index; /* Index to read nearest output values */ + + /* Input is in 12.20 format */ + /* 12 bits for the table index */ + /* Index value calculation */ + if (x < 0) + { + return (pYData[0]); + } + index = (x >> 20) & 0xfff; + + if (index >= (nValues - 1)) + { + return (pYData[nValues - 1]); + } + else + { + /* 20 bits for the fractional part */ + /* fract is in 12.20 format */ + fract = (x & 0x000FFFFF); + + /* Read two nearest output values from the index and are in 1.7(q7) format */ + y0 = pYData[index]; + y1 = pYData[index + 1]; + + /* Calculation of y0 * (1-fract ) and y is in 13.27(q27) format */ + y = ((y0 * (0xFFFFF - fract))); + + /* Calculation of y1 * fract + y0 * (1-fract) and y is in 13.27(q27) format */ + y += (y1 * fract); + + /* convert y to 1.7(q7) format */ + return (q7_t)(y >> 20); + } +} + +/** + * @} end of LinearInterpolate group + */ + +/** + * @brief Fast approximation to the trigonometric sine function for floating-point data. + * @param[in] x input value in radians. + * @return sin(x). + */ +float32_t arm_sin_f32( + float32_t x); + + +/** + * @brief Fast approximation to the trigonometric sine function for Q31 data. + * @param[in] x Scaled input value in radians. + * @return sin(x). + */ +q31_t arm_sin_q31( + q31_t x); + + +/** + * @brief Fast approximation to the trigonometric sine function for Q15 data. + * @param[in] x Scaled input value in radians. + * @return sin(x). + */ +q15_t arm_sin_q15( + q15_t x); + + +/** + * @brief Fast approximation to the trigonometric cosine function for floating-point data. + * @param[in] x input value in radians. + * @return cos(x). + */ +float32_t arm_cos_f32( + float32_t x); + + +/** + * @brief Fast approximation to the trigonometric cosine function for Q31 data. + * @param[in] x Scaled input value in radians. + * @return cos(x). + */ +q31_t arm_cos_q31( + q31_t x); + + +/** + * @brief Fast approximation to the trigonometric cosine function for Q15 data. + * @param[in] x Scaled input value in radians. + * @return cos(x). + */ +q15_t arm_cos_q15( + q15_t x); + + +/** + * @ingroup groupFastMath + */ + + +/** + * @defgroup SQRT Square Root + * + * Computes the square root of a number. + * There are separate functions for Q15, Q31, and floating-point data types. + * The square root function is computed using the Newton-Raphson algorithm. + * This is an iterative algorithm of the form: + * 
+ *      x1 = x0 - f(x0)/f'(x0)
+ *
+ * where x1 is the current estimate, + * x0 is the previous estimate, and + * f'(x0) is the derivative of f() evaluated at x0. + * For the square root function, the algorithm reduces to: + * 
+ *     x0 = in/2                         [initial guess]
+ *     x1 = 1/2 * ( x0 + in / x0)        [each iteration]
+ *
+ */ + + +/** + * @addtogroup SQRT + * @{ + */ + +/** + * @brief Floating-point square root function. + * @param[in] in input value. + * @param[out] pOut square root of input value. + * @return The function returns ARM_MATH_SUCCESS if input value is positive value or ARM_MATH_ARGUMENT_ERROR if + * in is negative value and returns zero output for negative values. + */ +static __INLINE arm_status arm_sqrt_f32( + float32_t in, + float32_t *pOut) +{ + if (in >= 0.0f) + { + +#if (__FPU_USED == 1) && defined ( __CC_ARM ) + *pOut = __sqrtf(in); +#elif (__FPU_USED == 1) && (defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)) + *pOut = __builtin_sqrtf(in); +#elif (__FPU_USED == 1) && defined(__GNUC__) + *pOut = __builtin_sqrtf(in); +#elif (__FPU_USED == 1) && defined ( __ICCARM__ ) && (__VER__ >= 6040000) + __ASM("VSQRT.F32 %0,%1" : "=t"(*pOut) : "t"(in)); +#else + *pOut = sqrtf(in); +#endif + + return (ARM_MATH_SUCCESS); + } + else + { + *pOut = 0.0f; + return (ARM_MATH_ARGUMENT_ERROR); + } +} + + +/** + * @brief Q31 square root function. + * @param[in] in input value. The range of the input value is [0 +1) or 0x00000000 to 0x7FFFFFFF. + * @param[out] pOut square root of input value. + * @return The function returns ARM_MATH_SUCCESS if input value is positive value or ARM_MATH_ARGUMENT_ERROR if + * in is negative value and returns zero output for negative values. + */ +arm_status arm_sqrt_q31( + q31_t in, + q31_t *pOut); + + +/** + * @brief Q15 square root function. + * @param[in] in input value. The range of the input value is [0 +1) or 0x0000 to 0x7FFF. + * @param[out] pOut square root of input value. + * @return The function returns ARM_MATH_SUCCESS if input value is positive value or ARM_MATH_ARGUMENT_ERROR if + * in is negative value and returns zero output for negative values. + */ +arm_status arm_sqrt_q15( + q15_t in, + q15_t *pOut); + +/** + * @} end of SQRT group + */ + + +/** + * @brief floating-point Circular write function. + */ +static __INLINE void arm_circularWrite_f32( + int32_t *circBuffer, + int32_t L, + uint16_t *writeOffset, + int32_t bufferInc, + const int32_t *src, + int32_t srcInc, + uint32_t blockSize) +{ + uint32_t i = 0u; + int32_t wOffset; + + /* Copy the value of Index pointer that points + * to the current location where the input samples to be copied */ + wOffset = *writeOffset; + + /* Loop over the blockSize */ + i = blockSize; + + while (i > 0u) + { + /* copy the input sample to the circular buffer */ + circBuffer[wOffset] = *src; + + /* Update the input pointer */ + src += srcInc; + + /* Circularly update wOffset. Watch out for positive and negative value */ + wOffset += bufferInc; + if (wOffset >= L) + wOffset -= L; + + /* Decrement the loop counter */ + i--; + } + + /* Update the index pointer */ + *writeOffset = (uint16_t)wOffset; +} + + + +/** + * @brief floating-point Circular Read function. + */ +static __INLINE void arm_circularRead_f32( + int32_t *circBuffer, + int32_t L, + int32_t *readOffset, + int32_t bufferInc, + int32_t *dst, + int32_t *dst_base, + int32_t dst_length, + int32_t dstInc, + uint32_t blockSize) +{ + uint32_t i = 0u; + int32_t rOffset, dst_end; + + /* Copy the value of Index pointer that points + * to the current location from where the input samples to be read */ + rOffset = *readOffset; + dst_end = (int32_t)(dst_base + dst_length); + + /* Loop over the blockSize */ + i = blockSize; + + while (i > 0u) + { + /* copy the sample from the circular buffer to the destination buffer */ + *dst = circBuffer[rOffset]; + + /* Update the input pointer */ + dst += dstInc; + + if (dst == (int32_t *) dst_end) + { + dst = dst_base; + } + + /* Circularly update rOffset. Watch out for positive and negative value */ + rOffset += bufferInc; + + if (rOffset >= L) + { + rOffset -= L; + } + + /* Decrement the loop counter */ + i--; + } + + /* Update the index pointer */ + *readOffset = rOffset; +} + + +/** + * @brief Q15 Circular write function. + */ +static __INLINE void arm_circularWrite_q15( + q15_t *circBuffer, + int32_t L, + uint16_t *writeOffset, + int32_t bufferInc, + const q15_t *src, + int32_t srcInc, + uint32_t blockSize) +{ + uint32_t i = 0u; + int32_t wOffset; + + /* Copy the value of Index pointer that points + * to the current location where the input samples to be copied */ + wOffset = *writeOffset; + + /* Loop over the blockSize */ + i = blockSize; + + while (i > 0u) + { + /* copy the input sample to the circular buffer */ + circBuffer[wOffset] = *src; + + /* Update the input pointer */ + src += srcInc; + + /* Circularly update wOffset. Watch out for positive and negative value */ + wOffset += bufferInc; + if (wOffset >= L) + wOffset -= L; + + /* Decrement the loop counter */ + i--; + } + + /* Update the index pointer */ + *writeOffset = (uint16_t)wOffset; +} + + +/** + * @brief Q15 Circular Read function. + */ +static __INLINE void arm_circularRead_q15( + q15_t *circBuffer, + int32_t L, + int32_t *readOffset, + int32_t bufferInc, + q15_t *dst, + q15_t *dst_base, + int32_t dst_length, + int32_t dstInc, + uint32_t blockSize) +{ + uint32_t i = 0; + int32_t rOffset, dst_end; + + /* Copy the value of Index pointer that points + * to the current location from where the input samples to be read */ + rOffset = *readOffset; + + dst_end = (int32_t)(dst_base + dst_length); + + /* Loop over the blockSize */ + i = blockSize; + + while (i > 0u) + { + /* copy the sample from the circular buffer to the destination buffer */ + *dst = circBuffer[rOffset]; + + /* Update the input pointer */ + dst += dstInc; + + if (dst == (q15_t *) dst_end) + { + dst = dst_base; + } + + /* Circularly update wOffset. Watch out for positive and negative value */ + rOffset += bufferInc; + + if (rOffset >= L) + { + rOffset -= L; + } + + /* Decrement the loop counter */ + i--; + } + + /* Update the index pointer */ + *readOffset = rOffset; +} + + +/** + * @brief Q7 Circular write function. + */ +static __INLINE void arm_circularWrite_q7( + q7_t *circBuffer, + int32_t L, + uint16_t *writeOffset, + int32_t bufferInc, + const q7_t *src, + int32_t srcInc, + uint32_t blockSize) +{ + uint32_t i = 0u; + int32_t wOffset; + + /* Copy the value of Index pointer that points + * to the current location where the input samples to be copied */ + wOffset = *writeOffset; + + /* Loop over the blockSize */ + i = blockSize; + + while (i > 0u) + { + /* copy the input sample to the circular buffer */ + circBuffer[wOffset] = *src; + + /* Update the input pointer */ + src += srcInc; + + /* Circularly update wOffset. Watch out for positive and negative value */ + wOffset += bufferInc; + if (wOffset >= L) + wOffset -= L; + + /* Decrement the loop counter */ + i--; + } + + /* Update the index pointer */ + *writeOffset = (uint16_t)wOffset; +} + + +/** + * @brief Q7 Circular Read function. + */ +static __INLINE void arm_circularRead_q7( + q7_t *circBuffer, + int32_t L, + int32_t *readOffset, + int32_t bufferInc, + q7_t *dst, + q7_t *dst_base, + int32_t dst_length, + int32_t dstInc, + uint32_t blockSize) +{ + uint32_t i = 0; + int32_t rOffset, dst_end; + + /* Copy the value of Index pointer that points + * to the current location from where the input samples to be read */ + rOffset = *readOffset; + + dst_end = (int32_t)(dst_base + dst_length); + + /* Loop over the blockSize */ + i = blockSize; + + while (i > 0u) + { + /* copy the sample from the circular buffer to the destination buffer */ + *dst = circBuffer[rOffset]; + + /* Update the input pointer */ + dst += dstInc; + + if (dst == (q7_t *) dst_end) + { + dst = dst_base; + } + + /* Circularly update rOffset. Watch out for positive and negative value */ + rOffset += bufferInc; + + if (rOffset >= L) + { + rOffset -= L; + } + + /* Decrement the loop counter */ + i--; + } + + /* Update the index pointer */ + *readOffset = rOffset; +} + + +/** + * @brief Sum of the squares of the elements of a Q31 vector. + * @param[in] pSrc is input pointer + * @param[in] blockSize is the number of samples to process + * @param[out] pResult is output value. + */ +void arm_power_q31( + q31_t *pSrc, + uint32_t blockSize, + q63_t *pResult); + + +/** + * @brief Sum of the squares of the elements of a floating-point vector. + * @param[in] pSrc is input pointer + * @param[in] blockSize is the number of samples to process + * @param[out] pResult is output value. + */ +void arm_power_f32( + float32_t *pSrc, + uint32_t blockSize, + float32_t *pResult); + + +/** + * @brief Sum of the squares of the elements of a Q15 vector. + * @param[in] pSrc is input pointer + * @param[in] blockSize is the number of samples to process + * @param[out] pResult is output value. + */ +void arm_power_q15( + q15_t *pSrc, + uint32_t blockSize, + q63_t *pResult); + + +/** + * @brief Sum of the squares of the elements of a Q7 vector. + * @param[in] pSrc is input pointer + * @param[in] blockSize is the number of samples to process + * @param[out] pResult is output value. + */ +void arm_power_q7( + q7_t *pSrc, + uint32_t blockSize, + q31_t *pResult); + + +/** + * @brief Mean value of a Q7 vector. + * @param[in] pSrc is input pointer + * @param[in] blockSize is the number of samples to process + * @param[out] pResult is output value. + */ +void arm_mean_q7( + q7_t *pSrc, + uint32_t blockSize, + q7_t *pResult); + + +/** + * @brief Mean value of a Q15 vector. + * @param[in] pSrc is input pointer + * @param[in] blockSize is the number of samples to process + * @param[out] pResult is output value. + */ +void arm_mean_q15( + q15_t *pSrc, + uint32_t blockSize, + q15_t *pResult); + + +/** + * @brief Mean value of a Q31 vector. + * @param[in] pSrc is input pointer + * @param[in] blockSize is the number of samples to process + * @param[out] pResult is output value. + */ +void arm_mean_q31( + q31_t *pSrc, + uint32_t blockSize, + q31_t *pResult); + + +/** + * @brief Mean value of a floating-point vector. + * @param[in] pSrc is input pointer + * @param[in] blockSize is the number of samples to process + * @param[out] pResult is output value. + */ +void arm_mean_f32( + float32_t *pSrc, + uint32_t blockSize, + float32_t *pResult); + + +/** + * @brief Variance of the elements of a floating-point vector. + * @param[in] pSrc is input pointer + * @param[in] blockSize is the number of samples to process + * @param[out] pResult is output value. + */ +void arm_var_f32( + float32_t *pSrc, + uint32_t blockSize, + float32_t *pResult); + + +/** + * @brief Variance of the elements of a Q31 vector. + * @param[in] pSrc is input pointer + * @param[in] blockSize is the number of samples to process + * @param[out] pResult is output value. + */ +void arm_var_q31( + q31_t *pSrc, + uint32_t blockSize, + q31_t *pResult); + + +/** + * @brief Variance of the elements of a Q15 vector. + * @param[in] pSrc is input pointer + * @param[in] blockSize is the number of samples to process + * @param[out] pResult is output value. + */ +void arm_var_q15( + q15_t *pSrc, + uint32_t blockSize, + q15_t *pResult); + + +/** + * @brief Root Mean Square of the elements of a floating-point vector. + * @param[in] pSrc is input pointer + * @param[in] blockSize is the number of samples to process + * @param[out] pResult is output value. + */ +void arm_rms_f32( + float32_t *pSrc, + uint32_t blockSize, + float32_t *pResult); + + +/** + * @brief Root Mean Square of the elements of a Q31 vector. + * @param[in] pSrc is input pointer + * @param[in] blockSize is the number of samples to process + * @param[out] pResult is output value. + */ +void arm_rms_q31( + q31_t *pSrc, + uint32_t blockSize, + q31_t *pResult); + + +/** + * @brief Root Mean Square of the elements of a Q15 vector. + * @param[in] pSrc is input pointer + * @param[in] blockSize is the number of samples to process + * @param[out] pResult is output value. + */ +void arm_rms_q15( + q15_t *pSrc, + uint32_t blockSize, + q15_t *pResult); + + +/** + * @brief Standard deviation of the elements of a floating-point vector. + * @param[in] pSrc is input pointer + * @param[in] blockSize is the number of samples to process + * @param[out] pResult is output value. + */ +void arm_std_f32( + float32_t *pSrc, + uint32_t blockSize, + float32_t *pResult); + + +/** + * @brief Standard deviation of the elements of a Q31 vector. + * @param[in] pSrc is input pointer + * @param[in] blockSize is the number of samples to process + * @param[out] pResult is output value. + */ +void arm_std_q31( + q31_t *pSrc, + uint32_t blockSize, + q31_t *pResult); + + +/** + * @brief Standard deviation of the elements of a Q15 vector. + * @param[in] pSrc is input pointer + * @param[in] blockSize is the number of samples to process + * @param[out] pResult is output value. + */ +void arm_std_q15( + q15_t *pSrc, + uint32_t blockSize, + q15_t *pResult); + + +/** + * @brief Floating-point complex magnitude + * @param[in] pSrc points to the complex input vector + * @param[out] pDst points to the real output vector + * @param[in] numSamples number of complex samples in the input vector + */ +void arm_cmplx_mag_f32( + float32_t *pSrc, + float32_t *pDst, + uint32_t numSamples); + + +/** + * @brief Q31 complex magnitude + * @param[in] pSrc points to the complex input vector + * @param[out] pDst points to the real output vector + * @param[in] numSamples number of complex samples in the input vector + */ +void arm_cmplx_mag_q31( + q31_t *pSrc, + q31_t *pDst, + uint32_t numSamples); + + +/** + * @brief Q15 complex magnitude + * @param[in] pSrc points to the complex input vector + * @param[out] pDst points to the real output vector + * @param[in] numSamples number of complex samples in the input vector + */ +void arm_cmplx_mag_q15( + q15_t *pSrc, + q15_t *pDst, + uint32_t numSamples); + + +/** + * @brief Q15 complex dot product + * @param[in] pSrcA points to the first input vector + * @param[in] pSrcB points to the second input vector + * @param[in] numSamples number of complex samples in each vector + * @param[out] realResult real part of the result returned here + * @param[out] imagResult imaginary part of the result returned here + */ +void arm_cmplx_dot_prod_q15( + q15_t *pSrcA, + q15_t *pSrcB, + uint32_t numSamples, + q31_t *realResult, + q31_t *imagResult); + + +/** + * @brief Q31 complex dot product + * @param[in] pSrcA points to the first input vector + * @param[in] pSrcB points to the second input vector + * @param[in] numSamples number of complex samples in each vector + * @param[out] realResult real part of the result returned here + * @param[out] imagResult imaginary part of the result returned here + */ +void arm_cmplx_dot_prod_q31( + q31_t *pSrcA, + q31_t *pSrcB, + uint32_t numSamples, + q63_t *realResult, + q63_t *imagResult); + + +/** + * @brief Floating-point complex dot product + * @param[in] pSrcA points to the first input vector + * @param[in] pSrcB points to the second input vector + * @param[in] numSamples number of complex samples in each vector + * @param[out] realResult real part of the result returned here + * @param[out] imagResult imaginary part of the result returned here + */ +void arm_cmplx_dot_prod_f32( + float32_t *pSrcA, + float32_t *pSrcB, + uint32_t numSamples, + float32_t *realResult, + float32_t *imagResult); + + +/** + * @brief Q15 complex-by-real multiplication + * @param[in] pSrcCmplx points to the complex input vector + * @param[in] pSrcReal points to the real input vector + * @param[out] pCmplxDst points to the complex output vector + * @param[in] numSamples number of samples in each vector + */ +void arm_cmplx_mult_real_q15( + q15_t *pSrcCmplx, + q15_t *pSrcReal, + q15_t *pCmplxDst, + uint32_t numSamples); + + +/** + * @brief Q31 complex-by-real multiplication + * @param[in] pSrcCmplx points to the complex input vector + * @param[in] pSrcReal points to the real input vector + * @param[out] pCmplxDst points to the complex output vector + * @param[in] numSamples number of samples in each vector + */ +void arm_cmplx_mult_real_q31( + q31_t *pSrcCmplx, + q31_t *pSrcReal, + q31_t *pCmplxDst, + uint32_t numSamples); + + +/** + * @brief Floating-point complex-by-real multiplication + * @param[in] pSrcCmplx points to the complex input vector + * @param[in] pSrcReal points to the real input vector + * @param[out] pCmplxDst points to the complex output vector + * @param[in] numSamples number of samples in each vector + */ +void arm_cmplx_mult_real_f32( + float32_t *pSrcCmplx, + float32_t *pSrcReal, + float32_t *pCmplxDst, + uint32_t numSamples); + + +/** + * @brief Minimum value of a Q7 vector. + * @param[in] pSrc is input pointer + * @param[in] blockSize is the number of samples to process + * @param[out] result is output pointer + * @param[in] index is the array index of the minimum value in the input buffer. + */ +void arm_min_q7( + q7_t *pSrc, + uint32_t blockSize, + q7_t *result, + uint32_t *index); + + +/** + * @brief Minimum value of a Q15 vector. + * @param[in] pSrc is input pointer + * @param[in] blockSize is the number of samples to process + * @param[out] pResult is output pointer + * @param[in] pIndex is the array index of the minimum value in the input buffer. + */ +void arm_min_q15( + q15_t *pSrc, + uint32_t blockSize, + q15_t *pResult, + uint32_t *pIndex); + + +/** + * @brief Minimum value of a Q31 vector. + * @param[in] pSrc is input pointer + * @param[in] blockSize is the number of samples to process + * @param[out] pResult is output pointer + * @param[out] pIndex is the array index of the minimum value in the input buffer. + */ +void arm_min_q31( + q31_t *pSrc, + uint32_t blockSize, + q31_t *pResult, + uint32_t *pIndex); + + +/** + * @brief Minimum value of a floating-point vector. + * @param[in] pSrc is input pointer + * @param[in] blockSize is the number of samples to process + * @param[out] pResult is output pointer + * @param[out] pIndex is the array index of the minimum value in the input buffer. + */ +void arm_min_f32( + float32_t *pSrc, + uint32_t blockSize, + float32_t *pResult, + uint32_t *pIndex); + + +/** + * @brief Maximum value of a Q7 vector. + * @param[in] pSrc points to the input buffer + * @param[in] blockSize length of the input vector + * @param[out] pResult maximum value returned here + * @param[out] pIndex index of maximum value returned here + */ +void arm_max_q7( + q7_t *pSrc, + uint32_t blockSize, + q7_t *pResult, + uint32_t *pIndex); + + +/** + * @brief Maximum value of a Q15 vector. + * @param[in] pSrc points to the input buffer + * @param[in] blockSize length of the input vector + * @param[out] pResult maximum value returned here + * @param[out] pIndex index of maximum value returned here + */ +void arm_max_q15( + q15_t *pSrc, + uint32_t blockSize, + q15_t *pResult, + uint32_t *pIndex); + + +/** + * @brief Maximum value of a Q31 vector. + * @param[in] pSrc points to the input buffer + * @param[in] blockSize length of the input vector + * @param[out] pResult maximum value returned here + * @param[out] pIndex index of maximum value returned here + */ +void arm_max_q31( + q31_t *pSrc, + uint32_t blockSize, + q31_t *pResult, + uint32_t *pIndex); + + +/** + * @brief Maximum value of a floating-point vector. + * @param[in] pSrc points to the input buffer + * @param[in] blockSize length of the input vector + * @param[out] pResult maximum value returned here + * @param[out] pIndex index of maximum value returned here + */ +void arm_max_f32( + float32_t *pSrc, + uint32_t blockSize, + float32_t *pResult, + uint32_t *pIndex); + + +/** + * @brief Q15 complex-by-complex multiplication + * @param[in] pSrcA points to the first input vector + * @param[in] pSrcB points to the second input vector + * @param[out] pDst points to the output vector + * @param[in] numSamples number of complex samples in each vector + */ +void arm_cmplx_mult_cmplx_q15( + q15_t *pSrcA, + q15_t *pSrcB, + q15_t *pDst, + uint32_t numSamples); + + +/** + * @brief Q31 complex-by-complex multiplication + * @param[in] pSrcA points to the first input vector + * @param[in] pSrcB points to the second input vector + * @param[out] pDst points to the output vector + * @param[in] numSamples number of complex samples in each vector + */ +void arm_cmplx_mult_cmplx_q31( + q31_t *pSrcA, + q31_t *pSrcB, + q31_t *pDst, + uint32_t numSamples); + + +/** + * @brief Floating-point complex-by-complex multiplication + * @param[in] pSrcA points to the first input vector + * @param[in] pSrcB points to the second input vector + * @param[out] pDst points to the output vector + * @param[in] numSamples number of complex samples in each vector + */ +void arm_cmplx_mult_cmplx_f32( + float32_t *pSrcA, + float32_t *pSrcB, + float32_t *pDst, + uint32_t numSamples); + + +/** + * @brief Converts the elements of the floating-point vector to Q31 vector. + * @param[in] pSrc points to the floating-point input vector + * @param[out] pDst points to the Q31 output vector + * @param[in] blockSize length of the input vector + */ +void arm_float_to_q31( + float32_t *pSrc, + q31_t *pDst, + uint32_t blockSize); + + +/** + * @brief Converts the elements of the floating-point vector to Q15 vector. + * @param[in] pSrc points to the floating-point input vector + * @param[out] pDst points to the Q15 output vector + * @param[in] blockSize length of the input vector + */ +void arm_float_to_q15( + float32_t *pSrc, + q15_t *pDst, + uint32_t blockSize); + + +/** + * @brief Converts the elements of the floating-point vector to Q7 vector. + * @param[in] pSrc points to the floating-point input vector + * @param[out] pDst points to the Q7 output vector + * @param[in] blockSize length of the input vector + */ +void arm_float_to_q7( + float32_t *pSrc, + q7_t *pDst, + uint32_t blockSize); + + +/** + * @brief Converts the elements of the Q31 vector to Q15 vector. + * @param[in] pSrc is input pointer + * @param[out] pDst is output pointer + * @param[in] blockSize is the number of samples to process + */ +void arm_q31_to_q15( + q31_t *pSrc, + q15_t *pDst, + uint32_t blockSize); + + +/** + * @brief Converts the elements of the Q31 vector to Q7 vector. + * @param[in] pSrc is input pointer + * @param[out] pDst is output pointer + * @param[in] blockSize is the number of samples to process + */ +void arm_q31_to_q7( + q31_t *pSrc, + q7_t *pDst, + uint32_t blockSize); + + +/** + * @brief Converts the elements of the Q15 vector to floating-point vector. + * @param[in] pSrc is input pointer + * @param[out] pDst is output pointer + * @param[in] blockSize is the number of samples to process + */ +void arm_q15_to_float( + q15_t *pSrc, + float32_t *pDst, + uint32_t blockSize); + + +/** + * @brief Converts the elements of the Q15 vector to Q31 vector. + * @param[in] pSrc is input pointer + * @param[out] pDst is output pointer + * @param[in] blockSize is the number of samples to process + */ +void arm_q15_to_q31( + q15_t *pSrc, + q31_t *pDst, + uint32_t blockSize); + + +/** + * @brief Converts the elements of the Q15 vector to Q7 vector. + * @param[in] pSrc is input pointer + * @param[out] pDst is output pointer + * @param[in] blockSize is the number of samples to process + */ +void arm_q15_to_q7( + q15_t *pSrc, + q7_t *pDst, + uint32_t blockSize); + + +/** + * @ingroup groupInterpolation + */ + +/** + * @defgroup BilinearInterpolate Bilinear Interpolation + * + * Bilinear interpolation is an extension of linear interpolation applied to a two dimensional grid. + * The underlying function f(x, y) is sampled on a regular grid and the interpolation process + * determines values between the grid points. + * Bilinear interpolation is equivalent to two step linear interpolation, first in the x-dimension and then in the y-dimension. + * Bilinear interpolation is often used in image processing to rescale images. + * The CMSIS DSP library provides bilinear interpolation functions for Q7, Q15, Q31, and floating-point data types. + * + * Algorithm + * \par + * The instance structure used by the bilinear interpolation functions describes a two dimensional data table. + * For floating-point, the instance structure is defined as: + * 
+ *   typedef struct
+ *   {
+ *     uint16_t numRows;
+ *     uint16_t numCols;
+ *     float32_t *pData;
+ * } arm_bilinear_interp_instance_f32;
+ *
+ * + * \par + * where numRows specifies the number of rows in the table; + * numCols specifies the number of columns in the table; + * and pData points to an array of size numRows*numCols values. + * The data table pTable is organized in row order and the supplied data values fall on integer indexes. + * That is, table element (x,y) is located at pTable[x + y*numCols] where x and y are integers. + * + * \par + * Let (x, y) specify the desired interpolation point. Then define: + * 
+ *     XF = floor(x)
+ *     YF = floor(y)
+ *
+ * \par + * The interpolated output point is computed as: + * 
+ *  f(x, y) = f(XF, YF) * (1-(x-XF)) * (1-(y-YF))
+ *           + f(XF+1, YF) * (x-XF)*(1-(y-YF))
+ *           + f(XF, YF+1) * (1-(x-XF))*(y-YF)
+ *           + f(XF+1, YF+1) * (x-XF)*(y-YF)
+ *
+ * Note that the coordinates (x, y) contain integer and fractional components. + * The integer components specify which portion of the table to use while the + * fractional components control the interpolation processor. + * + * \par + * if (x,y) are outside of the table boundary, Bilinear interpolation returns zero output. + */ + +/** + * @addtogroup BilinearInterpolate + * @{ + */ + + +/** +* +* @brief Floating-point bilinear interpolation. +* @param[in,out] S points to an instance of the interpolation structure. +* @param[in] X interpolation coordinate. +* @param[in] Y interpolation coordinate. +* @return out interpolated value. +*/ +static __INLINE float32_t arm_bilinear_interp_f32( + const arm_bilinear_interp_instance_f32 *S, + float32_t X, + float32_t Y) +{ + float32_t out; + float32_t f00, f01, f10, f11; + float32_t *pData = S->pData; + int32_t xIndex, yIndex, index; + float32_t xdiff, ydiff; + float32_t b1, b2, b3, b4; + + xIndex = (int32_t) X; + yIndex = (int32_t) Y; + + /* Care taken for table outside boundary */ + /* Returns zero output when values are outside table boundary */ + if (xIndex < 0 || xIndex > (S->numRows - 1) || yIndex < 0 || yIndex > (S->numCols - 1)) + { + return (0); + } + + /* Calculation of index for two nearest points in X-direction */ + index = (xIndex - 1) + (yIndex - 1) * S->numCols; + + + /* Read two nearest points in X-direction */ + f00 = pData[index]; + f01 = pData[index + 1]; + + /* Calculation of index for two nearest points in Y-direction */ + index = (xIndex - 1) + (yIndex) * S->numCols; + + + /* Read two nearest points in Y-direction */ + f10 = pData[index]; + f11 = pData[index + 1]; + + /* Calculation of intermediate values */ + b1 = f00; + b2 = f01 - f00; + b3 = f10 - f00; + b4 = f00 - f01 - f10 + f11; + + /* Calculation of fractional part in X */ + xdiff = X - xIndex; + + /* Calculation of fractional part in Y */ + ydiff = Y - yIndex; + + /* Calculation of bi-linear interpolated output */ + out = b1 + b2 * xdiff + b3 * ydiff + b4 * xdiff * ydiff; + + /* return to application */ + return (out); +} + + +/** +* +* @brief Q31 bilinear interpolation. +* @param[in,out] S points to an instance of the interpolation structure. +* @param[in] X interpolation coordinate in 12.20 format. +* @param[in] Y interpolation coordinate in 12.20 format. +* @return out interpolated value. +*/ +static __INLINE q31_t arm_bilinear_interp_q31( + arm_bilinear_interp_instance_q31 *S, + q31_t X, + q31_t Y) +{ + q31_t out; /* Temporary output */ + q31_t acc = 0; /* output */ + q31_t xfract, yfract; /* X, Y fractional parts */ + q31_t x1, x2, y1, y2; /* Nearest output values */ + int32_t rI, cI; /* Row and column indices */ + q31_t *pYData = S->pData; /* pointer to output table values */ + uint32_t nCols = S->numCols; /* num of rows */ + + /* Input is in 12.20 format */ + /* 12 bits for the table index */ + /* Index value calculation */ + rI = ((X & (q31_t)0xFFF00000) >> 20); + + /* Input is in 12.20 format */ + /* 12 bits for the table index */ + /* Index value calculation */ + cI = ((Y & (q31_t)0xFFF00000) >> 20); + + /* Care taken for table outside boundary */ + /* Returns zero output when values are outside table boundary */ + if (rI < 0 || rI > (S->numRows - 1) || cI < 0 || cI > (S->numCols - 1)) + { + return (0); + } + + /* 20 bits for the fractional part */ + /* shift left xfract by 11 to keep 1.31 format */ + xfract = (X & 0x000FFFFF) << 11u; + + /* Read two nearest output values from the index */ + x1 = pYData[(rI) + (int32_t)nCols * (cI) ]; + x2 = pYData[(rI) + (int32_t)nCols * (cI) + 1]; + + /* 20 bits for the fractional part */ + /* shift left yfract by 11 to keep 1.31 format */ + yfract = (Y & 0x000FFFFF) << 11u; + + /* Read two nearest output values from the index */ + y1 = pYData[(rI) + (int32_t)nCols * (cI + 1) ]; + y2 = pYData[(rI) + (int32_t)nCols * (cI + 1) + 1]; + + /* Calculation of x1 * (1-xfract ) * (1-yfract) and acc is in 3.29(q29) format */ + out = ((q31_t)(((q63_t) x1 * (0x7FFFFFFF - xfract)) >> 32)); + acc = ((q31_t)(((q63_t) out * (0x7FFFFFFF - yfract)) >> 32)); + + /* x2 * (xfract) * (1-yfract) in 3.29(q29) and adding to acc */ + out = ((q31_t)((q63_t) x2 * (0x7FFFFFFF - yfract) >> 32)); + acc += ((q31_t)((q63_t) out * (xfract) >> 32)); + + /* y1 * (1 - xfract) * (yfract) in 3.29(q29) and adding to acc */ + out = ((q31_t)((q63_t) y1 * (0x7FFFFFFF - xfract) >> 32)); + acc += ((q31_t)((q63_t) out * (yfract) >> 32)); + + /* y2 * (xfract) * (yfract) in 3.29(q29) and adding to acc */ + out = ((q31_t)((q63_t) y2 * (xfract) >> 32)); + acc += ((q31_t)((q63_t) out * (yfract) >> 32)); + + /* Convert acc to 1.31(q31) format */ + return ((q31_t)(acc << 2)); +} + + +/** +* @brief Q15 bilinear interpolation. +* @param[in,out] S points to an instance of the interpolation structure. +* @param[in] X interpolation coordinate in 12.20 format. +* @param[in] Y interpolation coordinate in 12.20 format. +* @return out interpolated value. +*/ +static __INLINE q15_t arm_bilinear_interp_q15( + arm_bilinear_interp_instance_q15 *S, + q31_t X, + q31_t Y) +{ + q63_t acc = 0; /* output */ + q31_t out; /* Temporary output */ + q15_t x1, x2, y1, y2; /* Nearest output values */ + q31_t xfract, yfract; /* X, Y fractional parts */ + int32_t rI, cI; /* Row and column indices */ + q15_t *pYData = S->pData; /* pointer to output table values */ + uint32_t nCols = S->numCols; /* num of rows */ + + /* Input is in 12.20 format */ + /* 12 bits for the table index */ + /* Index value calculation */ + rI = ((X & (q31_t)0xFFF00000) >> 20); + + /* Input is in 12.20 format */ + /* 12 bits for the table index */ + /* Index value calculation */ + cI = ((Y & (q31_t)0xFFF00000) >> 20); + + /* Care taken for table outside boundary */ + /* Returns zero output when values are outside table boundary */ + if (rI < 0 || rI > (S->numRows - 1) || cI < 0 || cI > (S->numCols - 1)) + { + return (0); + } + + /* 20 bits for the fractional part */ + /* xfract should be in 12.20 format */ + xfract = (X & 0x000FFFFF); + + /* Read two nearest output values from the index */ + x1 = pYData[((uint32_t)rI) + nCols * ((uint32_t)cI) ]; + x2 = pYData[((uint32_t)rI) + nCols * ((uint32_t)cI) + 1]; + + /* 20 bits for the fractional part */ + /* yfract should be in 12.20 format */ + yfract = (Y & 0x000FFFFF); + + /* Read two nearest output values from the index */ + y1 = pYData[((uint32_t)rI) + nCols * ((uint32_t)cI + 1) ]; + y2 = pYData[((uint32_t)rI) + nCols * ((uint32_t)cI + 1) + 1]; + + /* Calculation of x1 * (1-xfract ) * (1-yfract) and acc is in 13.51 format */ + + /* x1 is in 1.15(q15), xfract in 12.20 format and out is in 13.35 format */ + /* convert 13.35 to 13.31 by right shifting and out is in 1.31 */ + out = (q31_t)(((q63_t) x1 * (0xFFFFF - xfract)) >> 4u); + acc = ((q63_t) out * (0xFFFFF - yfract)); + + /* x2 * (xfract) * (1-yfract) in 1.51 and adding to acc */ + out = (q31_t)(((q63_t) x2 * (0xFFFFF - yfract)) >> 4u); + acc += ((q63_t) out * (xfract)); + + /* y1 * (1 - xfract) * (yfract) in 1.51 and adding to acc */ + out = (q31_t)(((q63_t) y1 * (0xFFFFF - xfract)) >> 4u); + acc += ((q63_t) out * (yfract)); + + /* y2 * (xfract) * (yfract) in 1.51 and adding to acc */ + out = (q31_t)(((q63_t) y2 * (xfract)) >> 4u); + acc += ((q63_t) out * (yfract)); + + /* acc is in 13.51 format and down shift acc by 36 times */ + /* Convert out to 1.15 format */ + return ((q15_t)(acc >> 36)); +} + + +/** +* @brief Q7 bilinear interpolation. +* @param[in,out] S points to an instance of the interpolation structure. +* @param[in] X interpolation coordinate in 12.20 format. +* @param[in] Y interpolation coordinate in 12.20 format. +* @return out interpolated value. +*/ +static __INLINE q7_t arm_bilinear_interp_q7( + arm_bilinear_interp_instance_q7 *S, + q31_t X, + q31_t Y) +{ + q63_t acc = 0; /* output */ + q31_t out; /* Temporary output */ + q31_t xfract, yfract; /* X, Y fractional parts */ + q7_t x1, x2, y1, y2; /* Nearest output values */ + int32_t rI, cI; /* Row and column indices */ + q7_t *pYData = S->pData; /* pointer to output table values */ + uint32_t nCols = S->numCols; /* num of rows */ + + /* Input is in 12.20 format */ + /* 12 bits for the table index */ + /* Index value calculation */ + rI = ((X & (q31_t)0xFFF00000) >> 20); + + /* Input is in 12.20 format */ + /* 12 bits for the table index */ + /* Index value calculation */ + cI = ((Y & (q31_t)0xFFF00000) >> 20); + + /* Care taken for table outside boundary */ + /* Returns zero output when values are outside table boundary */ + if (rI < 0 || rI > (S->numRows - 1) || cI < 0 || cI > (S->numCols - 1)) + { + return (0); + } + + /* 20 bits for the fractional part */ + /* xfract should be in 12.20 format */ + xfract = (X & (q31_t)0x000FFFFF); + + /* Read two nearest output values from the index */ + x1 = pYData[((uint32_t)rI) + nCols * ((uint32_t)cI) ]; + x2 = pYData[((uint32_t)rI) + nCols * ((uint32_t)cI) + 1]; + + /* 20 bits for the fractional part */ + /* yfract should be in 12.20 format */ + yfract = (Y & (q31_t)0x000FFFFF); + + /* Read two nearest output values from the index */ + y1 = pYData[((uint32_t)rI) + nCols * ((uint32_t)cI + 1) ]; + y2 = pYData[((uint32_t)rI) + nCols * ((uint32_t)cI + 1) + 1]; + + /* Calculation of x1 * (1-xfract ) * (1-yfract) and acc is in 16.47 format */ + out = ((x1 * (0xFFFFF - xfract))); + acc = (((q63_t) out * (0xFFFFF - yfract))); + + /* x2 * (xfract) * (1-yfract) in 2.22 and adding to acc */ + out = ((x2 * (0xFFFFF - yfract))); + acc += (((q63_t) out * (xfract))); + + /* y1 * (1 - xfract) * (yfract) in 2.22 and adding to acc */ + out = ((y1 * (0xFFFFF - xfract))); + acc += (((q63_t) out * (yfract))); + + /* y2 * (xfract) * (yfract) in 2.22 and adding to acc */ + out = ((y2 * (yfract))); + acc += (((q63_t) out * (xfract))); + + /* acc in 16.47 format and down shift by 40 to convert to 1.7 format */ + return ((q7_t)(acc >> 40)); +} + +/** + * @} end of BilinearInterpolate group + */ + + +/* SMMLAR */ +#define multAcc_32x32_keep32_R(a, x, y) \ + a = (q31_t) (((((q63_t) a) << 32) + ((q63_t) x * y) + 0x80000000LL ) >> 32) + +/* SMMLSR */ +#define multSub_32x32_keep32_R(a, x, y) \ + a = (q31_t) (((((q63_t) a) << 32) - ((q63_t) x * y) + 0x80000000LL ) >> 32) + +/* SMMULR */ +#define mult_32x32_keep32_R(a, x, y) \ + a = (q31_t) (((q63_t) x * y + 0x80000000LL ) >> 32) + +/* SMMLA */ +#define multAcc_32x32_keep32(a, x, y) \ + a += (q31_t) (((q63_t) x * y) >> 32) + +/* SMMLS */ +#define multSub_32x32_keep32(a, x, y) \ + a -= (q31_t) (((q63_t) x * y) >> 32) + +/* SMMUL */ +#define mult_32x32_keep32(a, x, y) \ + a = (q31_t) (((q63_t) x * y ) >> 32) + + +#if defined ( __CC_ARM ) +/* Enter low optimization region - place directly above function definition */ +#if defined( ARM_MATH_CM4 ) || defined( ARM_MATH_CM7) +#define LOW_OPTIMIZATION_ENTER \ + _Pragma ("push") \ + _Pragma ("O1") +#else +#define LOW_OPTIMIZATION_ENTER +#endif + +/* Exit low optimization region - place directly after end of function definition */ +#if defined( ARM_MATH_CM4 ) || defined( ARM_MATH_CM7) +#define LOW_OPTIMIZATION_EXIT \ + _Pragma ("pop") +#else +#define LOW_OPTIMIZATION_EXIT +#endif + +/* Enter low optimization region - place directly above function definition */ +#define IAR_ONLY_LOW_OPTIMIZATION_ENTER + +/* Exit low optimization region - place directly after end of function definition */ +#define IAR_ONLY_LOW_OPTIMIZATION_EXIT + +#elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) +#define LOW_OPTIMIZATION_ENTER +#define LOW_OPTIMIZATION_EXIT +#define IAR_ONLY_LOW_OPTIMIZATION_ENTER +#define IAR_ONLY_LOW_OPTIMIZATION_EXIT + +#elif defined(__GNUC__) +#define LOW_OPTIMIZATION_ENTER __attribute__(( optimize("-O1") )) +#define LOW_OPTIMIZATION_EXIT +#define IAR_ONLY_LOW_OPTIMIZATION_ENTER +#define IAR_ONLY_LOW_OPTIMIZATION_EXIT + +#elif defined(__ICCARM__) +/* Enter low optimization region - place directly above function definition */ +#if defined( ARM_MATH_CM4 ) || defined( ARM_MATH_CM7) +#define LOW_OPTIMIZATION_ENTER \ + _Pragma ("optimize=low") +#else +#define LOW_OPTIMIZATION_ENTER +#endif + +/* Exit low optimization region - place directly after end of function definition */ +#define LOW_OPTIMIZATION_EXIT + +/* Enter low optimization region - place directly above function definition */ +#if defined( ARM_MATH_CM4 ) || defined( ARM_MATH_CM7) +#define IAR_ONLY_LOW_OPTIMIZATION_ENTER \ + _Pragma ("optimize=low") +#else +#define IAR_ONLY_LOW_OPTIMIZATION_ENTER +#endif + +/* Exit low optimization region - place directly after end of function definition */ +#define IAR_ONLY_LOW_OPTIMIZATION_EXIT + +#elif defined(__CSMC__) +#define LOW_OPTIMIZATION_ENTER +#define LOW_OPTIMIZATION_EXIT +#define IAR_ONLY_LOW_OPTIMIZATION_ENTER +#define IAR_ONLY_LOW_OPTIMIZATION_EXIT + +#elif defined(__TASKING__) +#define LOW_OPTIMIZATION_ENTER +#define LOW_OPTIMIZATION_EXIT +#define IAR_ONLY_LOW_OPTIMIZATION_ENTER +#define IAR_ONLY_LOW_OPTIMIZATION_EXIT + +#endif + + +#ifdef __cplusplus +} +#endif + + +#if defined ( __GNUC__ ) + #pragma GCC diagnostic pop +#endif + +#endif /* _ARM_MATH_H */ + +/** + * + * End of file. + */ diff --git a/bsp/nuvoton/libraries/ma35/CMSIS/Include/cmsis_armcc.h b/bsp/nuvoton/libraries/ma35/CMSIS/Include/cmsis_armcc.h new file mode 100644 index 0000000000..7b85e336fe --- /dev/null +++ b/bsp/nuvoton/libraries/ma35/CMSIS/Include/cmsis_armcc.h @@ -0,0 +1,734 @@ +/**************************************************************************//** + * @file cmsis_armcc.h + * @brief CMSIS Cortex-M Core Function/Instruction Header File + * @version V4.30 + * @date 20. October 2015 + ******************************************************************************/ +/* Copyright (c) 2009 - 2015 ARM LIMITED + + All rights reserved. + Redistribution and use in source and binary forms, with or without + modification, are permitted provided that the following conditions are met: + - Redistributions of source code must retain the above copyright + notice, this list of conditions and the following disclaimer. + - Redistributions in binary form must reproduce the above copyright + notice, this list of conditions and the following disclaimer in the + documentation and/or other materials provided with the distribution. + - Neither the name of ARM nor the names of its contributors may be used + to endorse or promote products derived from this software without + specific prior written permission. + * + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE + LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + POSSIBILITY OF SUCH DAMAGE. + ---------------------------------------------------------------------------*/ + + +#ifndef __CMSIS_ARMCC_H +#define __CMSIS_ARMCC_H + + +#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION < 400677) + #error "Please use ARM Compiler Toolchain V4.0.677 or later!" +#endif + +/* ########################### Core Function Access ########################### */ +/** \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_RegAccFunctions CMSIS Core Register Access Functions + @{ + */ + +/* intrinsic void __enable_irq(); */ +/* intrinsic void __disable_irq(); */ + +/** + \brief Get Control Register + \details Returns the content of the Control Register. + \return Control Register value + */ +__STATIC_INLINE uint32_t __get_CONTROL(void) +{ + register uint32_t __regControl __ASM("control"); + return (__regControl); +} + + +/** + \brief Set Control Register + \details Writes the given value to the Control Register. + \param [in] control Control Register value to set + */ +__STATIC_INLINE void __set_CONTROL(uint32_t control) +{ + register uint32_t __regControl __ASM("control"); + __regControl = control; +} + + +/** + \brief Get IPSR Register + \details Returns the content of the IPSR Register. + \return IPSR Register value + */ +__STATIC_INLINE uint32_t __get_IPSR(void) +{ + register uint32_t __regIPSR __ASM("ipsr"); + return (__regIPSR); +} + + +/** + \brief Get APSR Register + \details Returns the content of the APSR Register. + \return APSR Register value + */ +__STATIC_INLINE uint32_t __get_APSR(void) +{ + register uint32_t __regAPSR __ASM("apsr"); + return (__regAPSR); +} + + +/** + \brief Get xPSR Register + \details Returns the content of the xPSR Register. + \return xPSR Register value + */ +__STATIC_INLINE uint32_t __get_xPSR(void) +{ + register uint32_t __regXPSR __ASM("xpsr"); + return (__regXPSR); +} + + +/** + \brief Get Process Stack Pointer + \details Returns the current value of the Process Stack Pointer (PSP). + \return PSP Register value + */ +__STATIC_INLINE uint32_t __get_PSP(void) +{ + register uint32_t __regProcessStackPointer __ASM("psp"); + return (__regProcessStackPointer); +} + + +/** + \brief Set Process Stack Pointer + \details Assigns the given value to the Process Stack Pointer (PSP). + \param [in] topOfProcStack Process Stack Pointer value to set + */ +__STATIC_INLINE void __set_PSP(uint32_t topOfProcStack) +{ + register uint32_t __regProcessStackPointer __ASM("psp"); + __regProcessStackPointer = topOfProcStack; +} + + +/** + \brief Get Main Stack Pointer + \details Returns the current value of the Main Stack Pointer (MSP). + \return MSP Register value + */ +__STATIC_INLINE uint32_t __get_MSP(void) +{ + register uint32_t __regMainStackPointer __ASM("msp"); + return (__regMainStackPointer); +} + + +/** + \brief Set Main Stack Pointer + \details Assigns the given value to the Main Stack Pointer (MSP). + \param [in] topOfMainStack Main Stack Pointer value to set + */ +__STATIC_INLINE void __set_MSP(uint32_t topOfMainStack) +{ + register uint32_t __regMainStackPointer __ASM("msp"); + __regMainStackPointer = topOfMainStack; +} + + +/** + \brief Get Priority Mask + \details Returns the current state of the priority mask bit from the Priority Mask Register. + \return Priority Mask value + */ +__STATIC_INLINE uint32_t __get_PRIMASK(void) +{ + register uint32_t __regPriMask __ASM("primask"); + return (__regPriMask); +} + + +/** + \brief Set Priority Mask + \details Assigns the given value to the Priority Mask Register. + \param [in] priMask Priority Mask + */ +__STATIC_INLINE void __set_PRIMASK(uint32_t priMask) +{ + register uint32_t __regPriMask __ASM("primask"); + __regPriMask = (priMask); +} + + +#if (__CORTEX_M >= 0x03U) || (__CORTEX_SC >= 300U) + +/** + \brief Enable FIQ + \details Enables FIQ interrupts by clearing the F-bit in the CPSR. + Can only be executed in Privileged modes. + */ +#define __enable_fault_irq __enable_fiq + + +/** + \brief Disable FIQ + \details Disables FIQ interrupts by setting the F-bit in the CPSR. + Can only be executed in Privileged modes. + */ +#define __disable_fault_irq __disable_fiq + + +/** + \brief Get Base Priority + \details Returns the current value of the Base Priority register. + \return Base Priority register value + */ +__STATIC_INLINE uint32_t __get_BASEPRI(void) +{ + register uint32_t __regBasePri __ASM("basepri"); + return (__regBasePri); +} + + +/** + \brief Set Base Priority + \details Assigns the given value to the Base Priority register. + \param [in] basePri Base Priority value to set + */ +__STATIC_INLINE void __set_BASEPRI(uint32_t basePri) +{ + register uint32_t __regBasePri __ASM("basepri"); + __regBasePri = (basePri & 0xFFU); +} + + +/** + \brief Set Base Priority with condition + \details Assigns the given value to the Base Priority register only if BASEPRI masking is disabled, + or the new value increases the BASEPRI priority level. + \param [in] basePri Base Priority value to set + */ +__STATIC_INLINE void __set_BASEPRI_MAX(uint32_t basePri) +{ + register uint32_t __regBasePriMax __ASM("basepri_max"); + __regBasePriMax = (basePri & 0xFFU); +} + + +/** + \brief Get Fault Mask + \details Returns the current value of the Fault Mask register. + \return Fault Mask register value + */ +__STATIC_INLINE uint32_t __get_FAULTMASK(void) +{ + register uint32_t __regFaultMask __ASM("faultmask"); + return (__regFaultMask); +} + + +/** + \brief Set Fault Mask + \details Assigns the given value to the Fault Mask register. + \param [in] faultMask Fault Mask value to set + */ +__STATIC_INLINE void __set_FAULTMASK(uint32_t faultMask) +{ + register uint32_t __regFaultMask __ASM("faultmask"); + __regFaultMask = (faultMask & (uint32_t)1); +} + +#endif /* (__CORTEX_M >= 0x03U) || (__CORTEX_SC >= 300U) */ + + +#if (__CORTEX_M == 0x04U) || (__CORTEX_M == 0x07U) + +/** + \brief Get FPSCR + \details Returns the current value of the Floating Point Status/Control register. + \return Floating Point Status/Control register value + */ +__STATIC_INLINE uint32_t __get_FPSCR(void) +{ +#if (__FPU_PRESENT == 1U) && (__FPU_USED == 1U) + register uint32_t __regfpscr __ASM("fpscr"); + return (__regfpscr); +#else + return (0U); +#endif +} + + +/** + \brief Set FPSCR + \details Assigns the given value to the Floating Point Status/Control register. + \param [in] fpscr Floating Point Status/Control value to set + */ +__STATIC_INLINE void __set_FPSCR(uint32_t fpscr) +{ +#if (__FPU_PRESENT == 1U) && (__FPU_USED == 1U) + register uint32_t __regfpscr __ASM("fpscr"); + __regfpscr = (fpscr); +#endif +} + +#endif /* (__CORTEX_M == 0x04U) || (__CORTEX_M == 0x07U) */ + + + +/*@} end of CMSIS_Core_RegAccFunctions */ + + +/* ########################## Core Instruction Access ######################### */ +/** \defgroup CMSIS_Core_InstructionInterface CMSIS Core Instruction Interface + Access to dedicated instructions + @{ +*/ + +/** + \brief No Operation + \details No Operation does nothing. This instruction can be used for code alignment purposes. + */ +#define __NOP __nop + + +/** + \brief Wait For Interrupt + \details Wait For Interrupt is a hint instruction that suspends execution until one of a number of events occurs. + */ +#define __WFI __wfi + + +/** + \brief Wait For Event + \details Wait For Event is a hint instruction that permits the processor to enter + a low-power state until one of a number of events occurs. + */ +#define __WFE __wfe + + +/** + \brief Send Event + \details Send Event is a hint instruction. It causes an event to be signaled to the CPU. + */ +#define __SEV __sev + + +/** + \brief Instruction Synchronization Barrier + \details Instruction Synchronization Barrier flushes the pipeline in the processor, + so that all instructions following the ISB are fetched from cache or memory, + after the instruction has been completed. + */ +#define __ISB() do {\ + __schedule_barrier();\ + __isb(0xF);\ + __schedule_barrier();\ + } while (0U) + +/** + \brief Data Synchronization Barrier + \details Acts as a special kind of Data Memory Barrier. + It completes when all explicit memory accesses before this instruction complete. + */ +#define __DSB() do {\ + __schedule_barrier();\ + __dsb(0xF);\ + __schedule_barrier();\ + } while (0U) + +/** + \brief Data Memory Barrier + \details Ensures the apparent order of the explicit memory operations before + and after the instruction, without ensuring their completion. + */ +#define __DMB() do {\ + __schedule_barrier();\ + __dmb(0xF);\ + __schedule_barrier();\ + } while (0U) + +/** + \brief Reverse byte order (32 bit) + \details Reverses the byte order in integer value. + \param [in] value Value to reverse + \return Reversed value + */ +#define __REV __rev + + +/** + \brief Reverse byte order (16 bit) + \details Reverses the byte order in two unsigned short values. + \param [in] value Value to reverse + \return Reversed value + */ +#ifndef __NO_EMBEDDED_ASM +__attribute__((section(".rev16_text"))) __STATIC_INLINE __ASM uint32_t __REV16(uint32_t value) +{ + rev16 r0, r0 + bx lr +} +#endif + +/** + \brief Reverse byte order in signed short value + \details Reverses the byte order in a signed short value with sign extension to integer. + \param [in] value Value to reverse + \return Reversed value + */ +#ifndef __NO_EMBEDDED_ASM +__attribute__((section(".revsh_text"))) __STATIC_INLINE __ASM int32_t __REVSH(int32_t value) +{ + revsh r0, r0 + bx lr +} +#endif + + +/** + \brief Rotate Right in unsigned value (32 bit) + \details Rotate Right (immediate) provides the value of the contents of a register rotated by a variable number of bits. + \param [in] value Value to rotate + \param [in] value Number of Bits to rotate + \return Rotated value + */ +#define __ROR __ror + + +/** + \brief Breakpoint + \details Causes the processor to enter Debug state. + Debug tools can use this to investigate system state when the instruction at a particular address is reached. + \param [in] value is ignored by the processor. + If required, a debugger can use it to store additional information about the breakpoint. + */ +#define __BKPT(value) __breakpoint(value) + + +/** + \brief Reverse bit order of value + \details Reverses the bit order of the given value. + \param [in] value Value to reverse + \return Reversed value + */ +#if (__CORTEX_M >= 0x03U) || (__CORTEX_SC >= 300U) +#define __RBIT __rbit +#else +__attribute__((always_inline)) __STATIC_INLINE uint32_t __RBIT(uint32_t value) +{ + uint32_t result; + int32_t s = 4 /*sizeof(v)*/ * 8 - 1; /* extra shift needed at end */ + + result = value; /* r will be reversed bits of v; first get LSB of v */ + for (value >>= 1U; value; value >>= 1U) + { + result <<= 1U; + result |= value & 1U; + s--; + } + result <<= s; /* shift when v's highest bits are zero */ + return (result); +} +#endif + + +/** + \brief Count leading zeros + \details Counts the number of leading zeros of a data value. + \param [in] value Value to count the leading zeros + \return number of leading zeros in value + */ +#define __CLZ __clz + + +#if (__CORTEX_M >= 0x03U) || (__CORTEX_SC >= 300U) + +/** + \brief LDR Exclusive (8 bit) + \details Executes a exclusive LDR instruction for 8 bit value. + \param [in] ptr Pointer to data + \return value of type uint8_t at (*ptr) + */ +#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION < 5060020) + #define __LDREXB(ptr) ((uint8_t ) __ldrex(ptr)) +#else + #define __LDREXB(ptr) _Pragma("push") _Pragma("diag_suppress 3731") ((uint8_t ) __ldrex(ptr)) _Pragma("pop") +#endif + + +/** + \brief LDR Exclusive (16 bit) + \details Executes a exclusive LDR instruction for 16 bit values. + \param [in] ptr Pointer to data + \return value of type uint16_t at (*ptr) + */ +#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION < 5060020) + #define __LDREXH(ptr) ((uint16_t) __ldrex(ptr)) +#else + #define __LDREXH(ptr) _Pragma("push") _Pragma("diag_suppress 3731") ((uint16_t) __ldrex(ptr)) _Pragma("pop") +#endif + + +/** + \brief LDR Exclusive (32 bit) + \details Executes a exclusive LDR instruction for 32 bit values. + \param [in] ptr Pointer to data + \return value of type uint32_t at (*ptr) + */ +#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION < 5060020) + #define __LDREXW(ptr) ((uint32_t ) __ldrex(ptr)) +#else + #define __LDREXW(ptr) _Pragma("push") _Pragma("diag_suppress 3731") ((uint32_t ) __ldrex(ptr)) _Pragma("pop") +#endif + + +/** + \brief STR Exclusive (8 bit) + \details Executes a exclusive STR instruction for 8 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + \return 0 Function succeeded + \return 1 Function failed + */ +#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION < 5060020) + #define __STREXB(value, ptr) __strex(value, ptr) +#else + #define __STREXB(value, ptr) _Pragma("push") _Pragma("diag_suppress 3731") __strex(value, ptr) _Pragma("pop") +#endif + + +/** + \brief STR Exclusive (16 bit) + \details Executes a exclusive STR instruction for 16 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + \return 0 Function succeeded + \return 1 Function failed + */ +#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION < 5060020) + #define __STREXH(value, ptr) __strex(value, ptr) +#else + #define __STREXH(value, ptr) _Pragma("push") _Pragma("diag_suppress 3731") __strex(value, ptr) _Pragma("pop") +#endif + + +/** + \brief STR Exclusive (32 bit) + \details Executes a exclusive STR instruction for 32 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + \return 0 Function succeeded + \return 1 Function failed + */ +#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION < 5060020) + #define __STREXW(value, ptr) __strex(value, ptr) +#else + #define __STREXW(value, ptr) _Pragma("push") _Pragma("diag_suppress 3731") __strex(value, ptr) _Pragma("pop") +#endif + + +/** + \brief Remove the exclusive lock + \details Removes the exclusive lock which is created by LDREX. + */ +#define __CLREX __clrex + + +/** + \brief Signed Saturate + \details Saturates a signed value. + \param [in] value Value to be saturated + \param [in] sat Bit position to saturate to (1..32) + \return Saturated value + */ +#define __SSAT __ssat + + +/** + \brief Unsigned Saturate + \details Saturates an unsigned value. + \param [in] value Value to be saturated + \param [in] sat Bit position to saturate to (0..31) + \return Saturated value + */ +#define __USAT __usat + + +/** + \brief Rotate Right with Extend (32 bit) + \details Moves each bit of a bitstring right by one bit. + The carry input is shifted in at the left end of the bitstring. + \param [in] value Value to rotate + \return Rotated value + */ +#ifndef __NO_EMBEDDED_ASM +__attribute__((section(".rrx_text"))) __STATIC_INLINE __ASM uint32_t __RRX(uint32_t value) +{ + rrx r0, r0 + bx lr +} +#endif + + +/** + \brief LDRT Unprivileged (8 bit) + \details Executes a Unprivileged LDRT instruction for 8 bit value. + \param [in] ptr Pointer to data + \return value of type uint8_t at (*ptr) + */ +#define __LDRBT(ptr) ((uint8_t ) __ldrt(ptr)) + + +/** + \brief LDRT Unprivileged (16 bit) + \details Executes a Unprivileged LDRT instruction for 16 bit values. + \param [in] ptr Pointer to data + \return value of type uint16_t at (*ptr) + */ +#define __LDRHT(ptr) ((uint16_t) __ldrt(ptr)) + + +/** + \brief LDRT Unprivileged (32 bit) + \details Executes a Unprivileged LDRT instruction for 32 bit values. + \param [in] ptr Pointer to data + \return value of type uint32_t at (*ptr) + */ +#define __LDRT(ptr) ((uint32_t ) __ldrt(ptr)) + + +/** + \brief STRT Unprivileged (8 bit) + \details Executes a Unprivileged STRT instruction for 8 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + */ +#define __STRBT(value, ptr) __strt(value, ptr) + + +/** + \brief STRT Unprivileged (16 bit) + \details Executes a Unprivileged STRT instruction for 16 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + */ +#define __STRHT(value, ptr) __strt(value, ptr) + + +/** + \brief STRT Unprivileged (32 bit) + \details Executes a Unprivileged STRT instruction for 32 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + */ +#define __STRT(value, ptr) __strt(value, ptr) + +#endif /* (__CORTEX_M >= 0x03U) || (__CORTEX_SC >= 300U) */ + +/*@}*/ /* end of group CMSIS_Core_InstructionInterface */ + + +/* ################### Compiler specific Intrinsics ########################### */ +/** \defgroup CMSIS_SIMD_intrinsics CMSIS SIMD Intrinsics + Access to dedicated SIMD instructions + @{ +*/ + +#if (__CORTEX_M >= 0x04U) /* only for Cortex-M4 and above */ + +#define __SADD8 __sadd8 +#define __QADD8 __qadd8 +#define __SHADD8 __shadd8 +#define __UADD8 __uadd8 +#define __UQADD8 __uqadd8 +#define __UHADD8 __uhadd8 +#define __SSUB8 __ssub8 +#define __QSUB8 __qsub8 +#define __SHSUB8 __shsub8 +#define __USUB8 __usub8 +#define __UQSUB8 __uqsub8 +#define __UHSUB8 __uhsub8 +#define __SADD16 __sadd16 +#define __QADD16 __qadd16 +#define __SHADD16 __shadd16 +#define __UADD16 __uadd16 +#define __UQADD16 __uqadd16 +#define __UHADD16 __uhadd16 +#define __SSUB16 __ssub16 +#define __QSUB16 __qsub16 +#define __SHSUB16 __shsub16 +#define __USUB16 __usub16 +#define __UQSUB16 __uqsub16 +#define __UHSUB16 __uhsub16 +#define __SASX __sasx +#define __QASX __qasx +#define __SHASX __shasx +#define __UASX __uasx +#define __UQASX __uqasx +#define __UHASX __uhasx +#define __SSAX __ssax +#define __QSAX __qsax +#define __SHSAX __shsax +#define __USAX __usax +#define __UQSAX __uqsax +#define __UHSAX __uhsax +#define __USAD8 __usad8 +#define __USADA8 __usada8 +#define __SSAT16 __ssat16 +#define __USAT16 __usat16 +#define __UXTB16 __uxtb16 +#define __UXTAB16 __uxtab16 +#define __SXTB16 __sxtb16 +#define __SXTAB16 __sxtab16 +#define __SMUAD __smuad +#define __SMUADX __smuadx +#define __SMLAD __smlad +#define __SMLADX __smladx +#define __SMLALD __smlald +#define __SMLALDX __smlaldx +#define __SMUSD __smusd +#define __SMUSDX __smusdx +#define __SMLSD __smlsd +#define __SMLSDX __smlsdx +#define __SMLSLD __smlsld +#define __SMLSLDX __smlsldx +#define __SEL __sel +#define __QADD __qadd +#define __QSUB __qsub + +#define __PKHBT(ARG1,ARG2,ARG3) ( ((((uint32_t)(ARG1)) ) & 0x0000FFFFUL) | \ + ((((uint32_t)(ARG2)) << (ARG3)) & 0xFFFF0000UL) ) + +#define __PKHTB(ARG1,ARG2,ARG3) ( ((((uint32_t)(ARG1)) ) & 0xFFFF0000UL) | \ + ((((uint32_t)(ARG2)) >> (ARG3)) & 0x0000FFFFUL) ) + +#define __SMMLA(ARG1,ARG2,ARG3) ( (int32_t)((((int64_t)(ARG1) * (ARG2)) + \ + ((int64_t)(ARG3) << 32U) ) >> 32U)) + +#endif /* (__CORTEX_M >= 0x04) */ +/*@} end of group CMSIS_SIMD_intrinsics */ + + +#endif /* __CMSIS_ARMCC_H */ diff --git a/bsp/nuvoton/libraries/ma35/CMSIS/Include/cmsis_armcc_V6.h b/bsp/nuvoton/libraries/ma35/CMSIS/Include/cmsis_armcc_V6.h new file mode 100644 index 0000000000..6d8f998d84 --- /dev/null +++ b/bsp/nuvoton/libraries/ma35/CMSIS/Include/cmsis_armcc_V6.h @@ -0,0 +1,1804 @@ +/**************************************************************************//** + * @file cmsis_armcc_V6.h + * @brief CMSIS Cortex-M Core Function/Instruction Header File + * @version V4.30 + * @date 20. October 2015 + ******************************************************************************/ +/* Copyright (c) 2009 - 2015 ARM LIMITED + + All rights reserved. + Redistribution and use in source and binary forms, with or without + modification, are permitted provided that the following conditions are met: + - Redistributions of source code must retain the above copyright + notice, this list of conditions and the following disclaimer. + - Redistributions in binary form must reproduce the above copyright + notice, this list of conditions and the following disclaimer in the + documentation and/or other materials provided with the distribution. + - Neither the name of ARM nor the names of its contributors may be used + to endorse or promote products derived from this software without + specific prior written permission. + * + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE + LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + POSSIBILITY OF SUCH DAMAGE. + ---------------------------------------------------------------------------*/ + + +#ifndef __CMSIS_ARMCC_V6_H +#define __CMSIS_ARMCC_V6_H + + +/* ########################### Core Function Access ########################### */ +/** \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_RegAccFunctions CMSIS Core Register Access Functions + @{ + */ + +/** + \brief Enable IRQ Interrupts + \details Enables IRQ interrupts by clearing the I-bit in the CPSR. + Can only be executed in Privileged modes. + */ +__attribute__((always_inline)) __STATIC_INLINE void __enable_irq(void) +{ + __ASM volatile("cpsie i" : : : "memory"); +} + + +/** + \brief Disable IRQ Interrupts + \details Disables IRQ interrupts by setting the I-bit in the CPSR. + Can only be executed in Privileged modes. + */ +__attribute__((always_inline)) __STATIC_INLINE void __disable_irq(void) +{ + __ASM volatile("cpsid i" : : : "memory"); +} + + +/** + \brief Get Control Register + \details Returns the content of the Control Register. + \return Control Register value + */ +__attribute__((always_inline)) __STATIC_INLINE uint32_t __get_CONTROL(void) +{ + uint32_t result; + + __ASM volatile("MRS %0, control" : "=r"(result)); + return (result); +} + + +#if (__ARM_FEATURE_CMSE == 3U) +/** + \brief Get Control Register (non-secure) + \details Returns the content of the non-secure Control Register when in secure mode. + \return non-secure Control Register value + */ +__attribute__((always_inline)) __STATIC_INLINE uint32_t __TZ_get_CONTROL_NS(void) +{ + uint32_t result; + + __ASM volatile("MRS %0, control_ns" : "=r"(result)); + return (result); +} +#endif + + +/** + \brief Set Control Register + \details Writes the given value to the Control Register. + \param [in] control Control Register value to set + */ +__attribute__((always_inline)) __STATIC_INLINE void __set_CONTROL(uint32_t control) +{ + __ASM volatile("MSR control, %0" : : "r"(control) : "memory"); +} + + +#if (__ARM_FEATURE_CMSE == 3U) +/** + \brief Set Control Register (non-secure) + \details Writes the given value to the non-secure Control Register when in secure state. + \param [in] control Control Register value to set + */ +__attribute__((always_inline)) __STATIC_INLINE void __TZ_set_CONTROL_NS(uint32_t control) +{ + __ASM volatile("MSR control_ns, %0" : : "r"(control) : "memory"); +} +#endif + + +/** + \brief Get IPSR Register + \details Returns the content of the IPSR Register. + \return IPSR Register value + */ +__attribute__((always_inline)) __STATIC_INLINE uint32_t __get_IPSR(void) +{ + uint32_t result; + + __ASM volatile("MRS %0, ipsr" : "=r"(result)); + return (result); +} + + +#if (__ARM_FEATURE_CMSE == 3U) +/** + \brief Get IPSR Register (non-secure) + \details Returns the content of the non-secure IPSR Register when in secure state. + \return IPSR Register value + */ +__attribute__((always_inline)) __STATIC_INLINE uint32_t __TZ_get_IPSR_NS(void) +{ + uint32_t result; + + __ASM volatile("MRS %0, ipsr_ns" : "=r"(result)); + return (result); +} +#endif + + +/** + \brief Get APSR Register + \details Returns the content of the APSR Register. + \return APSR Register value + */ +__attribute__((always_inline)) __STATIC_INLINE uint32_t __get_APSR(void) +{ + uint32_t result; + + __ASM volatile("MRS %0, apsr" : "=r"(result)); + return (result); +} + + +#if (__ARM_FEATURE_CMSE == 3U) +/** + \brief Get APSR Register (non-secure) + \details Returns the content of the non-secure APSR Register when in secure state. + \return APSR Register value + */ +__attribute__((always_inline)) __STATIC_INLINE uint32_t __TZ_get_APSR_NS(void) +{ + uint32_t result; + + __ASM volatile("MRS %0, apsr_ns" : "=r"(result)); + return (result); +} +#endif + + +/** + \brief Get xPSR Register + \details Returns the content of the xPSR Register. + \return xPSR Register value + */ +__attribute__((always_inline)) __STATIC_INLINE uint32_t __get_xPSR(void) +{ + uint32_t result; + + __ASM volatile("MRS %0, xpsr" : "=r"(result)); + return (result); +} + + +#if (__ARM_FEATURE_CMSE == 3U) +/** + \brief Get xPSR Register (non-secure) + \details Returns the content of the non-secure xPSR Register when in secure state. + \return xPSR Register value + */ +__attribute__((always_inline)) __STATIC_INLINE uint32_t __TZ_get_xPSR_NS(void) +{ + uint32_t result; + + __ASM volatile("MRS %0, xpsr_ns" : "=r"(result)); + return (result); +} +#endif + + +/** + \brief Get Process Stack Pointer + \details Returns the current value of the Process Stack Pointer (PSP). + \return PSP Register value + */ +__attribute__((always_inline)) __STATIC_INLINE uint32_t __get_PSP(void) +{ + register uint32_t result; + + __ASM volatile("MRS %0, psp" : "=r"(result)); + return (result); +} + + +#if (__ARM_FEATURE_CMSE == 3U) +/** + \brief Get Process Stack Pointer (non-secure) + \details Returns the current value of the non-secure Process Stack Pointer (PSP) when in secure state. + \return PSP Register value + */ +__attribute__((always_inline)) __STATIC_INLINE uint32_t __TZ_get_PSP_NS(void) +{ + register uint32_t result; + + __ASM volatile("MRS %0, psp_ns" : "=r"(result)); + return (result); +} +#endif + + +/** + \brief Set Process Stack Pointer + \details Assigns the given value to the Process Stack Pointer (PSP). + \param [in] topOfProcStack Process Stack Pointer value to set + */ +__attribute__((always_inline)) __STATIC_INLINE void __set_PSP(uint32_t topOfProcStack) +{ + __ASM volatile("MSR psp, %0" : : "r"(topOfProcStack) : "sp"); +} + + +#if (__ARM_FEATURE_CMSE == 3U) +/** + \brief Set Process Stack Pointer (non-secure) + \details Assigns the given value to the non-secure Process Stack Pointer (PSP) when in secure state. + \param [in] topOfProcStack Process Stack Pointer value to set + */ +__attribute__((always_inline)) __STATIC_INLINE void __TZ_set_PSP_NS(uint32_t topOfProcStack) +{ + __ASM volatile("MSR psp_ns, %0" : : "r"(topOfProcStack) : "sp"); +} +#endif + + +/** + \brief Get Main Stack Pointer + \details Returns the current value of the Main Stack Pointer (MSP). + \return MSP Register value + */ +__attribute__((always_inline)) __STATIC_INLINE uint32_t __get_MSP(void) +{ + register uint32_t result; + + __ASM volatile("MRS %0, msp" : "=r"(result)); + return (result); +} + + +#if (__ARM_FEATURE_CMSE == 3U) +/** + \brief Get Main Stack Pointer (non-secure) + \details Returns the current value of the non-secure Main Stack Pointer (MSP) when in secure state. + \return MSP Register value + */ +__attribute__((always_inline)) __STATIC_INLINE uint32_t __TZ_get_MSP_NS(void) +{ + register uint32_t result; + + __ASM volatile("MRS %0, msp_ns" : "=r"(result)); + return (result); +} +#endif + + +/** + \brief Set Main Stack Pointer + \details Assigns the given value to the Main Stack Pointer (MSP). + \param [in] topOfMainStack Main Stack Pointer value to set + */ +__attribute__((always_inline)) __STATIC_INLINE void __set_MSP(uint32_t topOfMainStack) +{ + __ASM volatile("MSR msp, %0" : : "r"(topOfMainStack) : "sp"); +} + + +#if (__ARM_FEATURE_CMSE == 3U) +/** + \brief Set Main Stack Pointer (non-secure) + \details Assigns the given value to the non-secure Main Stack Pointer (MSP) when in secure state. + \param [in] topOfMainStack Main Stack Pointer value to set + */ +__attribute__((always_inline)) __STATIC_INLINE void __TZ_set_MSP_NS(uint32_t topOfMainStack) +{ + __ASM volatile("MSR msp_ns, %0" : : "r"(topOfMainStack) : "sp"); +} +#endif + + +/** + \brief Get Priority Mask + \details Returns the current state of the priority mask bit from the Priority Mask Register. + \return Priority Mask value + */ +__attribute__((always_inline)) __STATIC_INLINE uint32_t __get_PRIMASK(void) +{ + uint32_t result; + + __ASM volatile("MRS %0, primask" : "=r"(result)); + return (result); +} + + +#if (__ARM_FEATURE_CMSE == 3U) +/** + \brief Get Priority Mask (non-secure) + \details Returns the current state of the non-secure priority mask bit from the Priority Mask Register when in secure state. + \return Priority Mask value + */ +__attribute__((always_inline)) __STATIC_INLINE uint32_t __TZ_get_PRIMASK_NS(void) +{ + uint32_t result; + + __ASM volatile("MRS %0, primask_ns" : "=r"(result)); + return (result); +} +#endif + + +/** + \brief Set Priority Mask + \details Assigns the given value to the Priority Mask Register. + \param [in] priMask Priority Mask + */ +__attribute__((always_inline)) __STATIC_INLINE void __set_PRIMASK(uint32_t priMask) +{ + __ASM volatile("MSR primask, %0" : : "r"(priMask) : "memory"); +} + + +#if (__ARM_FEATURE_CMSE == 3U) +/** + \brief Set Priority Mask (non-secure) + \details Assigns the given value to the non-secure Priority Mask Register when in secure state. + \param [in] priMask Priority Mask + */ +__attribute__((always_inline)) __STATIC_INLINE void __TZ_set_PRIMASK_NS(uint32_t priMask) +{ + __ASM volatile("MSR primask_ns, %0" : : "r"(priMask) : "memory"); +} +#endif + + +#if ((__ARM_ARCH_7M__ == 1U) || (__ARM_ARCH_7EM__ == 1U) || (__ARM_ARCH_8M__ == 1U)) /* ToDo: ARMCC_V6: check if this is ok for cortex >=3 */ + +/** + \brief Enable FIQ + \details Enables FIQ interrupts by clearing the F-bit in the CPSR. + Can only be executed in Privileged modes. + */ +__attribute__((always_inline)) __STATIC_INLINE void __enable_fault_irq(void) +{ + __ASM volatile("cpsie f" : : : "memory"); +} + + +/** + \brief Disable FIQ + \details Disables FIQ interrupts by setting the F-bit in the CPSR. + Can only be executed in Privileged modes. + */ +__attribute__((always_inline)) __STATIC_INLINE void __disable_fault_irq(void) +{ + __ASM volatile("cpsid f" : : : "memory"); +} + + +/** + \brief Get Base Priority + \details Returns the current value of the Base Priority register. + \return Base Priority register value + */ +__attribute__((always_inline)) __STATIC_INLINE uint32_t __get_BASEPRI(void) +{ + uint32_t result; + + __ASM volatile("MRS %0, basepri" : "=r"(result)); + return (result); +} + + +#if (__ARM_FEATURE_CMSE == 3U) +/** + \brief Get Base Priority (non-secure) + \details Returns the current value of the non-secure Base Priority register when in secure state. + \return Base Priority register value + */ +__attribute__((always_inline)) __STATIC_INLINE uint32_t __TZ_get_BASEPRI_NS(void) +{ + uint32_t result; + + __ASM volatile("MRS %0, basepri_ns" : "=r"(result)); + return (result); +} +#endif + + +/** + \brief Set Base Priority + \details Assigns the given value to the Base Priority register. + \param [in] basePri Base Priority value to set + */ +__attribute__((always_inline)) __STATIC_INLINE void __set_BASEPRI(uint32_t value) +{ + __ASM volatile("MSR basepri, %0" : : "r"(value) : "memory"); +} + + +#if (__ARM_FEATURE_CMSE == 3U) +/** + \brief Set Base Priority (non-secure) + \details Assigns the given value to the non-secure Base Priority register when in secure state. + \param [in] basePri Base Priority value to set + */ +__attribute__((always_inline)) __STATIC_INLINE void __TZ_set_BASEPRI_NS(uint32_t value) +{ + __ASM volatile("MSR basepri_ns, %0" : : "r"(value) : "memory"); +} +#endif + + +/** + \brief Set Base Priority with condition + \details Assigns the given value to the Base Priority register only if BASEPRI masking is disabled, + or the new value increases the BASEPRI priority level. + \param [in] basePri Base Priority value to set + */ +__attribute__((always_inline)) __STATIC_INLINE void __set_BASEPRI_MAX(uint32_t value) +{ + __ASM volatile("MSR basepri_max, %0" : : "r"(value) : "memory"); +} + + +#if (__ARM_FEATURE_CMSE == 3U) +/** + \brief Set Base Priority with condition (non_secure) + \details Assigns the given value to the non-secure Base Priority register when in secure state only if BASEPRI masking is disabled, + or the new value increases the BASEPRI priority level. + \param [in] basePri Base Priority value to set + */ +__attribute__((always_inline)) __STATIC_INLINE void __TZ_set_BASEPRI_MAX_NS(uint32_t value) +{ + __ASM volatile("MSR basepri_max_ns, %0" : : "r"(value) : "memory"); +} +#endif + + +/** + \brief Get Fault Mask + \details Returns the current value of the Fault Mask register. + \return Fault Mask register value + */ +__attribute__((always_inline)) __STATIC_INLINE uint32_t __get_FAULTMASK(void) +{ + uint32_t result; + + __ASM volatile("MRS %0, faultmask" : "=r"(result)); + return (result); +} + + +#if (__ARM_FEATURE_CMSE == 3U) +/** + \brief Get Fault Mask (non-secure) + \details Returns the current value of the non-secure Fault Mask register when in secure state. + \return Fault Mask register value + */ +__attribute__((always_inline)) __STATIC_INLINE uint32_t __TZ_get_FAULTMASK_NS(void) +{ + uint32_t result; + + __ASM volatile("MRS %0, faultmask_ns" : "=r"(result)); + return (result); +} +#endif + + +/** + \brief Set Fault Mask + \details Assigns the given value to the Fault Mask register. + \param [in] faultMask Fault Mask value to set + */ +__attribute__((always_inline)) __STATIC_INLINE void __set_FAULTMASK(uint32_t faultMask) +{ + __ASM volatile("MSR faultmask, %0" : : "r"(faultMask) : "memory"); +} + + +#if (__ARM_FEATURE_CMSE == 3U) +/** + \brief Set Fault Mask (non-secure) + \details Assigns the given value to the non-secure Fault Mask register when in secure state. + \param [in] faultMask Fault Mask value to set + */ +__attribute__((always_inline)) __STATIC_INLINE void __TZ_set_FAULTMASK_NS(uint32_t faultMask) +{ + __ASM volatile("MSR faultmask_ns, %0" : : "r"(faultMask) : "memory"); +} +#endif + + +#endif /* ((__ARM_ARCH_7M__ == 1U) || (__ARM_ARCH_8M__ == 1U)) */ + + +#if (__ARM_ARCH_8M__ == 1U) + +/** + \brief Get Process Stack Pointer Limit + \details Returns the current value of the Process Stack Pointer Limit (PSPLIM). + \return PSPLIM Register value + */ +__attribute__((always_inline)) __STATIC_INLINE uint32_t __get_PSPLIM(void) +{ + register uint32_t result; + + __ASM volatile("MRS %0, psplim" : "=r"(result)); + return (result); +} + + +#if (__ARM_FEATURE_CMSE == 3U) && (__ARM_ARCH_PROFILE == 'M') /* ToDo: ARMCC_V6: check predefined macro for mainline */ +/** + \brief Get Process Stack Pointer Limit (non-secure) + \details Returns the current value of the non-secure Process Stack Pointer Limit (PSPLIM) when in secure state. + \return PSPLIM Register value + */ +__attribute__((always_inline)) __STATIC_INLINE uint32_t __TZ_get_PSPLIM_NS(void) +{ + register uint32_t result; + + __ASM volatile("MRS %0, psplim_ns" : "=r"(result)); + return (result); +} +#endif + + +/** + \brief Set Process Stack Pointer Limit + \details Assigns the given value to the Process Stack Pointer Limit (PSPLIM). + \param [in] ProcStackPtrLimit Process Stack Pointer Limit value to set + */ +__attribute__((always_inline)) __STATIC_INLINE void __set_PSPLIM(uint32_t ProcStackPtrLimit) +{ + __ASM volatile("MSR psplim, %0" : : "r"(ProcStackPtrLimit)); +} + + +#if (__ARM_FEATURE_CMSE == 3U) && (__ARM_ARCH_PROFILE == 'M') /* ToDo: ARMCC_V6: check predefined macro for mainline */ +/** + \brief Set Process Stack Pointer (non-secure) + \details Assigns the given value to the non-secure Process Stack Pointer Limit (PSPLIM) when in secure state. + \param [in] ProcStackPtrLimit Process Stack Pointer Limit value to set + */ +__attribute__((always_inline)) __STATIC_INLINE void __TZ_set_PSPLIM_NS(uint32_t ProcStackPtrLimit) +{ + __ASM volatile("MSR psplim_ns, %0\n" : : "r"(ProcStackPtrLimit)); +} +#endif + + +/** + \brief Get Main Stack Pointer Limit + \details Returns the current value of the Main Stack Pointer Limit (MSPLIM). + \return MSPLIM Register value + */ +__attribute__((always_inline)) __STATIC_INLINE uint32_t __get_MSPLIM(void) +{ + register uint32_t result; + + __ASM volatile("MRS %0, msplim" : "=r"(result)); + + return (result); +} + + +#if (__ARM_FEATURE_CMSE == 3U) && (__ARM_ARCH_PROFILE == 'M') /* ToDo: ARMCC_V6: check predefined macro for mainline */ +/** + \brief Get Main Stack Pointer Limit (non-secure) + \details Returns the current value of the non-secure Main Stack Pointer Limit(MSPLIM) when in secure state. + \return MSPLIM Register value + */ +__attribute__((always_inline)) __STATIC_INLINE uint32_t __TZ_get_MSPLIM_NS(void) +{ + register uint32_t result; + + __ASM volatile("MRS %0, msplim_ns" : "=r"(result)); + return (result); +} +#endif + + +/** + \brief Set Main Stack Pointer Limit + \details Assigns the given value to the Main Stack Pointer Limit (MSPLIM). + \param [in] MainStackPtrLimit Main Stack Pointer Limit value to set + */ +__attribute__((always_inline)) __STATIC_INLINE void __set_MSPLIM(uint32_t MainStackPtrLimit) +{ + __ASM volatile("MSR msplim, %0" : : "r"(MainStackPtrLimit)); +} + + +#if (__ARM_FEATURE_CMSE == 3U) && (__ARM_ARCH_PROFILE == 'M') /* ToDo: ARMCC_V6: check predefined macro for mainline */ +/** + \brief Set Main Stack Pointer Limit (non-secure) + \details Assigns the given value to the non-secure Main Stack Pointer Limit (MSPLIM) when in secure state. + \param [in] MainStackPtrLimit Main Stack Pointer value to set + */ +__attribute__((always_inline)) __STATIC_INLINE void __TZ_set_MSPLIM_NS(uint32_t MainStackPtrLimit) +{ + __ASM volatile("MSR msplim_ns, %0" : : "r"(MainStackPtrLimit)); +} +#endif + +#endif /* (__ARM_ARCH_8M__ == 1U) */ + + +#if ((__ARM_ARCH_7EM__ == 1U) || (__ARM_ARCH_8M__ == 1U)) /* ToDo: ARMCC_V6: check if this is ok for cortex >=4 */ + +/** + \brief Get FPSCR + \details eturns the current value of the Floating Point Status/Control register. + \return Floating Point Status/Control register value + */ +#define __get_FPSCR __builtin_arm_get_fpscr +#if 0 +__attribute__((always_inline)) __STATIC_INLINE uint32_t __get_FPSCR(void) +{ +#if (__FPU_PRESENT == 1U) && (__FPU_USED == 1U) + uint32_t result; + + __ASM volatile(""); /* Empty asm statement works as a scheduling barrier */ + __ASM volatile("VMRS %0, fpscr" : "=r"(result)); + __ASM volatile(""); + return (result); +#else + return (0); +#endif +} +#endif + +#if (__ARM_FEATURE_CMSE == 3U) +/** + \brief Get FPSCR (non-secure) + \details Returns the current value of the non-secure Floating Point Status/Control register when in secure state. + \return Floating Point Status/Control register value + */ +__attribute__((always_inline)) __STATIC_INLINE uint32_t __TZ_get_FPSCR_NS(void) +{ +#if (__FPU_PRESENT == 1U) && (__FPU_USED == 1U) + uint32_t result; + + __ASM volatile(""); /* Empty asm statement works as a scheduling barrier */ + __ASM volatile("VMRS %0, fpscr_ns" : "=r"(result)); + __ASM volatile(""); + return (result); +#else + return (0); +#endif +} +#endif + + +/** + \brief Set FPSCR + \details Assigns the given value to the Floating Point Status/Control register. + \param [in] fpscr Floating Point Status/Control value to set + */ +#define __set_FPSCR __builtin_arm_set_fpscr +#if 0 +__attribute__((always_inline)) __STATIC_INLINE void __set_FPSCR(uint32_t fpscr) +{ +#if (__FPU_PRESENT == 1U) && (__FPU_USED == 1U) + __ASM volatile(""); /* Empty asm statement works as a scheduling barrier */ + __ASM volatile("VMSR fpscr, %0" : : "r"(fpscr) : "vfpcc"); + __ASM volatile(""); +#endif +} +#endif + +#if (__ARM_FEATURE_CMSE == 3U) +/** + \brief Set FPSCR (non-secure) + \details Assigns the given value to the non-secure Floating Point Status/Control register when in secure state. + \param [in] fpscr Floating Point Status/Control value to set + */ +__attribute__((always_inline)) __STATIC_INLINE void __TZ_set_FPSCR_NS(uint32_t fpscr) +{ +#if (__FPU_PRESENT == 1U) && (__FPU_USED == 1U) + __ASM volatile(""); /* Empty asm statement works as a scheduling barrier */ + __ASM volatile("VMSR fpscr_ns, %0" : : "r"(fpscr) : "vfpcc"); + __ASM volatile(""); +#endif +} +#endif + +#endif /* ((__ARM_ARCH_7EM__ == 1U) || (__ARM_ARCH_8M__ == 1U)) */ + + + +/*@} end of CMSIS_Core_RegAccFunctions */ + + +/* ########################## Core Instruction Access ######################### */ +/** \defgroup CMSIS_Core_InstructionInterface CMSIS Core Instruction Interface + Access to dedicated instructions + @{ +*/ + +/* Define macros for porting to both thumb1 and thumb2. + * For thumb1, use low register (r0-r7), specified by constraint "l" + * Otherwise, use general registers, specified by constraint "r" */ +#if defined (__thumb__) && !defined (__thumb2__) + #define __CMSIS_GCC_OUT_REG(r) "=l" (r) + #define __CMSIS_GCC_USE_REG(r) "l" (r) +#else + #define __CMSIS_GCC_OUT_REG(r) "=r" (r) + #define __CMSIS_GCC_USE_REG(r) "r" (r) +#endif + +/** + \brief No Operation + \details No Operation does nothing. This instruction can be used for code alignment purposes. + */ +#define __NOP __builtin_arm_nop + +/** + \brief Wait For Interrupt + \details Wait For Interrupt is a hint instruction that suspends execution until one of a number of events occurs. + */ +#define __WFI __builtin_arm_wfi + + +/** + \brief Wait For Event + \details Wait For Event is a hint instruction that permits the processor to enter + a low-power state until one of a number of events occurs. + */ +#define __WFE __builtin_arm_wfe + + +/** + \brief Send Event + \details Send Event is a hint instruction. It causes an event to be signaled to the CPU. + */ +#define __SEV __builtin_arm_sev + + +/** + \brief Instruction Synchronization Barrier + \details Instruction Synchronization Barrier flushes the pipeline in the processor, + so that all instructions following the ISB are fetched from cache or memory, + after the instruction has been completed. + */ +#define __ISB() __builtin_arm_isb(0xF); + +/** + \brief Data Synchronization Barrier + \details Acts as a special kind of Data Memory Barrier. + It completes when all explicit memory accesses before this instruction complete. + */ +#define __DSB() __builtin_arm_dsb(0xF); + + +/** + \brief Data Memory Barrier + \details Ensures the apparent order of the explicit memory operations before + and after the instruction, without ensuring their completion. + */ +#define __DMB() __builtin_arm_dmb(0xF); + + +/** + \brief Reverse byte order (32 bit) + \details Reverses the byte order in integer value. + \param [in] value Value to reverse + \return Reversed value + */ +#define __REV __builtin_bswap32 + + +/** + \brief Reverse byte order (16 bit) + \details Reverses the byte order in two unsigned short values. + \param [in] value Value to reverse + \return Reversed value + */ +#define __REV16 __builtin_bswap16 /* ToDo: ARMCC_V6: check if __builtin_bswap16 could be used */ +#if 0 +__attribute__((always_inline)) __STATIC_INLINE uint32_t __REV16(uint32_t value) +{ + uint32_t result; + + __ASM volatile("rev16 %0, %1" : __CMSIS_GCC_OUT_REG(result) : __CMSIS_GCC_USE_REG(value)); + return (result); +} +#endif + + +/** + \brief Reverse byte order in signed short value + \details Reverses the byte order in a signed short value with sign extension to integer. + \param [in] value Value to reverse + \return Reversed value + */ +/* ToDo: ARMCC_V6: check if __builtin_bswap16 could be used */ +__attribute__((always_inline)) __STATIC_INLINE int32_t __REVSH(int32_t value) +{ + int32_t result; + + __ASM volatile("revsh %0, %1" : __CMSIS_GCC_OUT_REG(result) : __CMSIS_GCC_USE_REG(value)); + return (result); +} + + +/** + \brief Rotate Right in unsigned value (32 bit) + \details Rotate Right (immediate) provides the value of the contents of a register rotated by a variable number of bits. + \param [in] op1 Value to rotate + \param [in] op2 Number of Bits to rotate + \return Rotated value + */ +__attribute__((always_inline)) __STATIC_INLINE uint32_t __ROR(uint32_t op1, uint32_t op2) +{ + return (op1 >> op2) | (op1 << (32U - op2)); +} + + +/** + \brief Breakpoint + \details Causes the processor to enter Debug state. + Debug tools can use this to investigate system state when the instruction at a particular address is reached. + \param [in] value is ignored by the processor. + If required, a debugger can use it to store additional information about the breakpoint. + */ +#define __BKPT(value) __ASM volatile ("bkpt "#value) + + +/** + \brief Reverse bit order of value + \details Reverses the bit order of the given value. + \param [in] value Value to reverse + \return Reversed value + */ +/* ToDo: ARMCC_V6: check if __builtin_arm_rbit is supported */ +__attribute__((always_inline)) __STATIC_INLINE uint32_t __RBIT(uint32_t value) +{ + uint32_t result; + +#if ((__ARM_ARCH_7M__ == 1U) || (__ARM_ARCH_7EM__ == 1U) || (__ARM_ARCH_8M__ == 1U)) /* ToDo: ARMCC_V6: check if this is ok for cortex >=3 */ + __ASM volatile("rbit %0, %1" : "=r"(result) : "r"(value)); +#else + int32_t s = 4 /*sizeof(v)*/ * 8 - 1; /* extra shift needed at end */ + + result = value; /* r will be reversed bits of v; first get LSB of v */ + for (value >>= 1U; value; value >>= 1U) + { + result <<= 1U; + result |= value & 1U; + s--; + } + result <<= s; /* shift when v's highest bits are zero */ +#endif + return (result); +} + + +/** + \brief Count leading zeros + \details Counts the number of leading zeros of a data value. + \param [in] value Value to count the leading zeros + \return number of leading zeros in value + */ +#define __CLZ __builtin_clz + + +#if ((__ARM_ARCH_7M__ == 1U) || (__ARM_ARCH_7EM__ == 1U) || (__ARM_ARCH_8M__ == 1U)) /* ToDo: ARMCC_V6: check if this is ok for cortex >=3 */ + +/** + \brief LDR Exclusive (8 bit) + \details Executes a exclusive LDR instruction for 8 bit value. + \param [in] ptr Pointer to data + \return value of type uint8_t at (*ptr) + */ +#define __LDREXB (uint8_t)__builtin_arm_ldrex + + +/** + \brief LDR Exclusive (16 bit) + \details Executes a exclusive LDR instruction for 16 bit values. + \param [in] ptr Pointer to data + \return value of type uint16_t at (*ptr) + */ +#define __LDREXH (uint16_t)__builtin_arm_ldrex + + +/** + \brief LDR Exclusive (32 bit) + \details Executes a exclusive LDR instruction for 32 bit values. + \param [in] ptr Pointer to data + \return value of type uint32_t at (*ptr) + */ +#define __LDREXW (uint32_t)__builtin_arm_ldrex + + +/** + \brief STR Exclusive (8 bit) + \details Executes a exclusive STR instruction for 8 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + \return 0 Function succeeded + \return 1 Function failed + */ +#define __STREXB (uint32_t)__builtin_arm_strex + + +/** + \brief STR Exclusive (16 bit) + \details Executes a exclusive STR instruction for 16 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + \return 0 Function succeeded + \return 1 Function failed + */ +#define __STREXH (uint32_t)__builtin_arm_strex + + +/** + \brief STR Exclusive (32 bit) + \details Executes a exclusive STR instruction for 32 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + \return 0 Function succeeded + \return 1 Function failed + */ +#define __STREXW (uint32_t)__builtin_arm_strex + + +/** + \brief Remove the exclusive lock + \details Removes the exclusive lock which is created by LDREX. + */ +#define __CLREX __builtin_arm_clrex + + +/** + \brief Signed Saturate + \details Saturates a signed value. + \param [in] value Value to be saturated + \param [in] sat Bit position to saturate to (1..32) + \return Saturated value + */ +/*#define __SSAT __builtin_arm_ssat*/ +#define __SSAT(ARG1,ARG2) \ +({ \ + int32_t __RES, __ARG1 = (ARG1); \ + __ASM ("ssat %0, %1, %2" : "=r" (__RES) : "I" (ARG2), "r" (__ARG1) ); \ + __RES; \ + }) + + +/** + \brief Unsigned Saturate + \details Saturates an unsigned value. + \param [in] value Value to be saturated + \param [in] sat Bit position to saturate to (0..31) + \return Saturated value + */ +#define __USAT __builtin_arm_usat +#if 0 +#define __USAT(ARG1,ARG2) \ +({ \ + uint32_t __RES, __ARG1 = (ARG1); \ + __ASM ("usat %0, %1, %2" : "=r" (__RES) : "I" (ARG2), "r" (__ARG1) ); \ + __RES; \ + }) +#endif + + +/** + \brief Rotate Right with Extend (32 bit) + \details Moves each bit of a bitstring right by one bit. + The carry input is shifted in at the left end of the bitstring. + \param [in] value Value to rotate + \return Rotated value + */ +__attribute__((always_inline)) __STATIC_INLINE uint32_t __RRX(uint32_t value) +{ + uint32_t result; + + __ASM volatile("rrx %0, %1" : __CMSIS_GCC_OUT_REG(result) : __CMSIS_GCC_USE_REG(value)); + return (result); +} + + +/** + \brief LDRT Unprivileged (8 bit) + \details Executes a Unprivileged LDRT instruction for 8 bit value. + \param [in] ptr Pointer to data + \return value of type uint8_t at (*ptr) + */ +__attribute__((always_inline)) __STATIC_INLINE uint8_t __LDRBT(volatile uint8_t *ptr) +{ + uint32_t result; + + __ASM volatile("ldrbt %0, %1" : "=r"(result) : "Q"(*ptr)); + return ((uint8_t) result); /* Add explicit type cast here */ +} + + +/** + \brief LDRT Unprivileged (16 bit) + \details Executes a Unprivileged LDRT instruction for 16 bit values. + \param [in] ptr Pointer to data + \return value of type uint16_t at (*ptr) + */ +__attribute__((always_inline)) __STATIC_INLINE uint16_t __LDRHT(volatile uint16_t *ptr) +{ + uint32_t result; + + __ASM volatile("ldrht %0, %1" : "=r"(result) : "Q"(*ptr)); + return ((uint16_t) result); /* Add explicit type cast here */ +} + + +/** + \brief LDRT Unprivileged (32 bit) + \details Executes a Unprivileged LDRT instruction for 32 bit values. + \param [in] ptr Pointer to data + \return value of type uint32_t at (*ptr) + */ +__attribute__((always_inline)) __STATIC_INLINE uint32_t __LDRT(volatile uint32_t *ptr) +{ + uint32_t result; + + __ASM volatile("ldrt %0, %1" : "=r"(result) : "Q"(*ptr)); + return (result); +} + + +/** + \brief STRT Unprivileged (8 bit) + \details Executes a Unprivileged STRT instruction for 8 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + */ +__attribute__((always_inline)) __STATIC_INLINE void __STRBT(uint8_t value, volatile uint8_t *ptr) +{ + __ASM volatile("strbt %1, %0" : "=Q"(*ptr) : "r"((uint32_t)value)); +} + + +/** + \brief STRT Unprivileged (16 bit) + \details Executes a Unprivileged STRT instruction for 16 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + */ +__attribute__((always_inline)) __STATIC_INLINE void __STRHT(uint16_t value, volatile uint16_t *ptr) +{ + __ASM volatile("strht %1, %0" : "=Q"(*ptr) : "r"((uint32_t)value)); +} + + +/** + \brief STRT Unprivileged (32 bit) + \details Executes a Unprivileged STRT instruction for 32 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + */ +__attribute__((always_inline)) __STATIC_INLINE void __STRT(uint32_t value, volatile uint32_t *ptr) +{ + __ASM volatile("strt %1, %0" : "=Q"(*ptr) : "r"(value)); +} + +#endif /* ((__ARM_ARCH_7M__ == 1U) || (__ARM_ARCH_7EM__ == 1U) || (__ARM_ARCH_8M__ == 1U)) */ + + +#if (__ARM_ARCH_8M__ == 1U) + +/** + \brief Load-Acquire (8 bit) + \details Executes a LDAB instruction for 8 bit value. + \param [in] ptr Pointer to data + \return value of type uint8_t at (*ptr) + */ +__attribute__((always_inline)) __STATIC_INLINE uint8_t __LDAB(volatile uint8_t *ptr) +{ + uint32_t result; + + __ASM volatile("ldab %0, %1" : "=r"(result) : "Q"(*ptr)); + return ((uint8_t) result); +} + + +/** + \brief Load-Acquire (16 bit) + \details Executes a LDAH instruction for 16 bit values. + \param [in] ptr Pointer to data + \return value of type uint16_t at (*ptr) + */ +__attribute__((always_inline)) __STATIC_INLINE uint16_t __LDAH(volatile uint16_t *ptr) +{ + uint32_t result; + + __ASM volatile("ldah %0, %1" : "=r"(result) : "Q"(*ptr)); + return ((uint16_t) result); +} + + +/** + \brief Load-Acquire (32 bit) + \details Executes a LDA instruction for 32 bit values. + \param [in] ptr Pointer to data + \return value of type uint32_t at (*ptr) + */ +__attribute__((always_inline)) __STATIC_INLINE uint32_t __LDA(volatile uint32_t *ptr) +{ + uint32_t result; + + __ASM volatile("lda %0, %1" : "=r"(result) : "Q"(*ptr)); + return (result); +} + + +/** + \brief Store-Release (8 bit) + \details Executes a STLB instruction for 8 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + */ +__attribute__((always_inline)) __STATIC_INLINE void __STLB(uint8_t value, volatile uint8_t *ptr) +{ + __ASM volatile("stlb %1, %0" : "=Q"(*ptr) : "r"((uint32_t)value)); +} + + +/** + \brief Store-Release (16 bit) + \details Executes a STLH instruction for 16 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + */ +__attribute__((always_inline)) __STATIC_INLINE void __STLH(uint16_t value, volatile uint16_t *ptr) +{ + __ASM volatile("stlh %1, %0" : "=Q"(*ptr) : "r"((uint32_t)value)); +} + + +/** + \brief Store-Release (32 bit) + \details Executes a STL instruction for 32 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + */ +__attribute__((always_inline)) __STATIC_INLINE void __STL(uint32_t value, volatile uint32_t *ptr) +{ + __ASM volatile("stl %1, %0" : "=Q"(*ptr) : "r"((uint32_t)value)); +} + + +/** + \brief Load-Acquire Exclusive (8 bit) + \details Executes a LDAB exclusive instruction for 8 bit value. + \param [in] ptr Pointer to data + \return value of type uint8_t at (*ptr) + */ +#define __LDAEXB (uint8_t)__builtin_arm_ldaex + + +/** + \brief Load-Acquire Exclusive (16 bit) + \details Executes a LDAH exclusive instruction for 16 bit values. + \param [in] ptr Pointer to data + \return value of type uint16_t at (*ptr) + */ +#define __LDAEXH (uint16_t)__builtin_arm_ldaex + + +/** + \brief Load-Acquire Exclusive (32 bit) + \details Executes a LDA exclusive instruction for 32 bit values. + \param [in] ptr Pointer to data + \return value of type uint32_t at (*ptr) + */ +#define __LDAEX (uint32_t)__builtin_arm_ldaex + + +/** + \brief Store-Release Exclusive (8 bit) + \details Executes a STLB exclusive instruction for 8 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + \return 0 Function succeeded + \return 1 Function failed + */ +#define __STLEXB (uint32_t)__builtin_arm_stlex + + +/** + \brief Store-Release Exclusive (16 bit) + \details Executes a STLH exclusive instruction for 16 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + \return 0 Function succeeded + \return 1 Function failed + */ +#define __STLEXH (uint32_t)__builtin_arm_stlex + + +/** + \brief Store-Release Exclusive (32 bit) + \details Executes a STL exclusive instruction for 32 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + \return 0 Function succeeded + \return 1 Function failed + */ +#define __STLEX (uint32_t)__builtin_arm_stlex + +#endif /* (__ARM_ARCH_8M__ == 1U) */ + +/*@}*/ /* end of group CMSIS_Core_InstructionInterface */ + + +/* ################### Compiler specific Intrinsics ########################### */ +/** \defgroup CMSIS_SIMD_intrinsics CMSIS SIMD Intrinsics + Access to dedicated SIMD instructions + @{ +*/ + +#if (__ARM_FEATURE_DSP == 1U) /* ToDo: ARMCC_V6: This should be ARCH >= ARMv7-M + SIMD */ + +__attribute__((always_inline)) __STATIC_INLINE uint32_t __SADD8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile("sadd8 %0, %1, %2" : "=r"(result) : "r"(op1), "r"(op2)); + return (result); +} + +__attribute__((always_inline)) __STATIC_INLINE uint32_t __QADD8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile("qadd8 %0, %1, %2" : "=r"(result) : "r"(op1), "r"(op2)); + return (result); +} + +__attribute__((always_inline)) __STATIC_INLINE uint32_t __SHADD8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile("shadd8 %0, %1, %2" : "=r"(result) : "r"(op1), "r"(op2)); + return (result); +} + +__attribute__((always_inline)) __STATIC_INLINE uint32_t __UADD8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile("uadd8 %0, %1, %2" : "=r"(result) : "r"(op1), "r"(op2)); + return (result); +} + +__attribute__((always_inline)) __STATIC_INLINE uint32_t __UQADD8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile("uqadd8 %0, %1, %2" : "=r"(result) : "r"(op1), "r"(op2)); + return (result); +} + +__attribute__((always_inline)) __STATIC_INLINE uint32_t __UHADD8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile("uhadd8 %0, %1, %2" : "=r"(result) : "r"(op1), "r"(op2)); + return (result); +} + + +__attribute__((always_inline)) __STATIC_INLINE uint32_t __SSUB8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile("ssub8 %0, %1, %2" : "=r"(result) : "r"(op1), "r"(op2)); + return (result); +} + +__attribute__((always_inline)) __STATIC_INLINE uint32_t __QSUB8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile("qsub8 %0, %1, %2" : "=r"(result) : "r"(op1), "r"(op2)); + return (result); +} + +__attribute__((always_inline)) __STATIC_INLINE uint32_t __SHSUB8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile("shsub8 %0, %1, %2" : "=r"(result) : "r"(op1), "r"(op2)); + return (result); +} + +__attribute__((always_inline)) __STATIC_INLINE uint32_t __USUB8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile("usub8 %0, %1, %2" : "=r"(result) : "r"(op1), "r"(op2)); + return (result); +} + +__attribute__((always_inline)) __STATIC_INLINE uint32_t __UQSUB8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile("uqsub8 %0, %1, %2" : "=r"(result) : "r"(op1), "r"(op2)); + return (result); +} + +__attribute__((always_inline)) __STATIC_INLINE uint32_t __UHSUB8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile("uhsub8 %0, %1, %2" : "=r"(result) : "r"(op1), "r"(op2)); + return (result); +} + + +__attribute__((always_inline)) __STATIC_INLINE uint32_t __SADD16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile("sadd16 %0, %1, %2" : "=r"(result) : "r"(op1), "r"(op2)); + return (result); +} + +__attribute__((always_inline)) __STATIC_INLINE uint32_t __QADD16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile("qadd16 %0, %1, %2" : "=r"(result) : "r"(op1), "r"(op2)); + return (result); +} + +__attribute__((always_inline)) __STATIC_INLINE uint32_t __SHADD16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile("shadd16 %0, %1, %2" : "=r"(result) : "r"(op1), "r"(op2)); + return (result); +} + +__attribute__((always_inline)) __STATIC_INLINE uint32_t __UADD16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile("uadd16 %0, %1, %2" : "=r"(result) : "r"(op1), "r"(op2)); + return (result); +} + +__attribute__((always_inline)) __STATIC_INLINE uint32_t __UQADD16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile("uqadd16 %0, %1, %2" : "=r"(result) : "r"(op1), "r"(op2)); + return (result); +} + +__attribute__((always_inline)) __STATIC_INLINE uint32_t __UHADD16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile("uhadd16 %0, %1, %2" : "=r"(result) : "r"(op1), "r"(op2)); + return (result); +} + +__attribute__((always_inline)) __STATIC_INLINE uint32_t __SSUB16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile("ssub16 %0, %1, %2" : "=r"(result) : "r"(op1), "r"(op2)); + return (result); +} + +__attribute__((always_inline)) __STATIC_INLINE uint32_t __QSUB16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile("qsub16 %0, %1, %2" : "=r"(result) : "r"(op1), "r"(op2)); + return (result); +} + +__attribute__((always_inline)) __STATIC_INLINE uint32_t __SHSUB16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile("shsub16 %0, %1, %2" : "=r"(result) : "r"(op1), "r"(op2)); + return (result); +} + +__attribute__((always_inline)) __STATIC_INLINE uint32_t __USUB16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile("usub16 %0, %1, %2" : "=r"(result) : "r"(op1), "r"(op2)); + return (result); +} + +__attribute__((always_inline)) __STATIC_INLINE uint32_t __UQSUB16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile("uqsub16 %0, %1, %2" : "=r"(result) : "r"(op1), "r"(op2)); + return (result); +} + +__attribute__((always_inline)) __STATIC_INLINE uint32_t __UHSUB16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile("uhsub16 %0, %1, %2" : "=r"(result) : "r"(op1), "r"(op2)); + return (result); +} + +__attribute__((always_inline)) __STATIC_INLINE uint32_t __SASX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile("sasx %0, %1, %2" : "=r"(result) : "r"(op1), "r"(op2)); + return (result); +} + +__attribute__((always_inline)) __STATIC_INLINE uint32_t __QASX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile("qasx %0, %1, %2" : "=r"(result) : "r"(op1), "r"(op2)); + return (result); +} + +__attribute__((always_inline)) __STATIC_INLINE uint32_t __SHASX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile("shasx %0, %1, %2" : "=r"(result) : "r"(op1), "r"(op2)); + return (result); +} + +__attribute__((always_inline)) __STATIC_INLINE uint32_t __UASX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile("uasx %0, %1, %2" : "=r"(result) : "r"(op1), "r"(op2)); + return (result); +} + +__attribute__((always_inline)) __STATIC_INLINE uint32_t __UQASX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile("uqasx %0, %1, %2" : "=r"(result) : "r"(op1), "r"(op2)); + return (result); +} + +__attribute__((always_inline)) __STATIC_INLINE uint32_t __UHASX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile("uhasx %0, %1, %2" : "=r"(result) : "r"(op1), "r"(op2)); + return (result); +} + +__attribute__((always_inline)) __STATIC_INLINE uint32_t __SSAX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile("ssax %0, %1, %2" : "=r"(result) : "r"(op1), "r"(op2)); + return (result); +} + +__attribute__((always_inline)) __STATIC_INLINE uint32_t __QSAX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile("qsax %0, %1, %2" : "=r"(result) : "r"(op1), "r"(op2)); + return (result); +} + +__attribute__((always_inline)) __STATIC_INLINE uint32_t __SHSAX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile("shsax %0, %1, %2" : "=r"(result) : "r"(op1), "r"(op2)); + return (result); +} + +__attribute__((always_inline)) __STATIC_INLINE uint32_t __USAX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile("usax %0, %1, %2" : "=r"(result) : "r"(op1), "r"(op2)); + return (result); +} + +__attribute__((always_inline)) __STATIC_INLINE uint32_t __UQSAX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile("uqsax %0, %1, %2" : "=r"(result) : "r"(op1), "r"(op2)); + return (result); +} + +__attribute__((always_inline)) __STATIC_INLINE uint32_t __UHSAX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile("uhsax %0, %1, %2" : "=r"(result) : "r"(op1), "r"(op2)); + return (result); +} + +__attribute__((always_inline)) __STATIC_INLINE uint32_t __USAD8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile("usad8 %0, %1, %2" : "=r"(result) : "r"(op1), "r"(op2)); + return (result); +} + +__attribute__((always_inline)) __STATIC_INLINE uint32_t __USADA8(uint32_t op1, uint32_t op2, uint32_t op3) +{ + uint32_t result; + + __ASM volatile("usada8 %0, %1, %2, %3" : "=r"(result) : "r"(op1), "r"(op2), "r"(op3)); + return (result); +} + +#define __SSAT16(ARG1,ARG2) \ +({ \ + uint32_t __RES, __ARG1 = (ARG1); \ + __ASM ("ssat16 %0, %1, %2" : "=r" (__RES) : "I" (ARG2), "r" (__ARG1) ); \ + __RES; \ + }) + +#define __USAT16(ARG1,ARG2) \ +({ \ + uint32_t __RES, __ARG1 = (ARG1); \ + __ASM ("usat16 %0, %1, %2" : "=r" (__RES) : "I" (ARG2), "r" (__ARG1) ); \ + __RES; \ + }) + +__attribute__((always_inline)) __STATIC_INLINE uint32_t __UXTB16(uint32_t op1) +{ + uint32_t result; + + __ASM volatile("uxtb16 %0, %1" : "=r"(result) : "r"(op1)); + return (result); +} + +__attribute__((always_inline)) __STATIC_INLINE uint32_t __UXTAB16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile("uxtab16 %0, %1, %2" : "=r"(result) : "r"(op1), "r"(op2)); + return (result); +} + +__attribute__((always_inline)) __STATIC_INLINE uint32_t __SXTB16(uint32_t op1) +{ + uint32_t result; + + __ASM volatile("sxtb16 %0, %1" : "=r"(result) : "r"(op1)); + return (result); +} + +__attribute__((always_inline)) __STATIC_INLINE uint32_t __SXTAB16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile("sxtab16 %0, %1, %2" : "=r"(result) : "r"(op1), "r"(op2)); + return (result); +} + +__attribute__((always_inline)) __STATIC_INLINE uint32_t __SMUAD(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile("smuad %0, %1, %2" : "=r"(result) : "r"(op1), "r"(op2)); + return (result); +} + +__attribute__((always_inline)) __STATIC_INLINE uint32_t __SMUADX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile("smuadx %0, %1, %2" : "=r"(result) : "r"(op1), "r"(op2)); + return (result); +} + +__attribute__((always_inline)) __STATIC_INLINE uint32_t __SMLAD(uint32_t op1, uint32_t op2, uint32_t op3) +{ + uint32_t result; + + __ASM volatile("smlad %0, %1, %2, %3" : "=r"(result) : "r"(op1), "r"(op2), "r"(op3)); + return (result); +} + +__attribute__((always_inline)) __STATIC_INLINE uint32_t __SMLADX(uint32_t op1, uint32_t op2, uint32_t op3) +{ + uint32_t result; + + __ASM volatile("smladx %0, %1, %2, %3" : "=r"(result) : "r"(op1), "r"(op2), "r"(op3)); + return (result); +} + +__attribute__((always_inline)) __STATIC_INLINE uint64_t __SMLALD(uint32_t op1, uint32_t op2, uint64_t acc) +{ + union llreg_u + { + uint32_t w32[2]; + uint64_t w64; + } llr; + llr.w64 = acc; + +#ifndef __ARMEB__ /* Little endian */ + __ASM volatile("smlald %0, %1, %2, %3" : "=r"(llr.w32[0]), "=r"(llr.w32[1]): "r"(op1), "r"(op2), "0"(llr.w32[0]), "1"(llr.w32[1])); +#else /* Big endian */ + __ASM volatile("smlald %0, %1, %2, %3" : "=r"(llr.w32[1]), "=r"(llr.w32[0]): "r"(op1), "r"(op2), "0"(llr.w32[1]), "1"(llr.w32[0])); +#endif + + return (llr.w64); +} + +__attribute__((always_inline)) __STATIC_INLINE uint64_t __SMLALDX(uint32_t op1, uint32_t op2, uint64_t acc) +{ + union llreg_u + { + uint32_t w32[2]; + uint64_t w64; + } llr; + llr.w64 = acc; + +#ifndef __ARMEB__ /* Little endian */ + __ASM volatile("smlaldx %0, %1, %2, %3" : "=r"(llr.w32[0]), "=r"(llr.w32[1]): "r"(op1), "r"(op2), "0"(llr.w32[0]), "1"(llr.w32[1])); +#else /* Big endian */ + __ASM volatile("smlaldx %0, %1, %2, %3" : "=r"(llr.w32[1]), "=r"(llr.w32[0]): "r"(op1), "r"(op2), "0"(llr.w32[1]), "1"(llr.w32[0])); +#endif + + return (llr.w64); +} + +__attribute__((always_inline)) __STATIC_INLINE uint32_t __SMUSD(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile("smusd %0, %1, %2" : "=r"(result) : "r"(op1), "r"(op2)); + return (result); +} + +__attribute__((always_inline)) __STATIC_INLINE uint32_t __SMUSDX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile("smusdx %0, %1, %2" : "=r"(result) : "r"(op1), "r"(op2)); + return (result); +} + +__attribute__((always_inline)) __STATIC_INLINE uint32_t __SMLSD(uint32_t op1, uint32_t op2, uint32_t op3) +{ + uint32_t result; + + __ASM volatile("smlsd %0, %1, %2, %3" : "=r"(result) : "r"(op1), "r"(op2), "r"(op3)); + return (result); +} + +__attribute__((always_inline)) __STATIC_INLINE uint32_t __SMLSDX(uint32_t op1, uint32_t op2, uint32_t op3) +{ + uint32_t result; + + __ASM volatile("smlsdx %0, %1, %2, %3" : "=r"(result) : "r"(op1), "r"(op2), "r"(op3)); + return (result); +} + +__attribute__((always_inline)) __STATIC_INLINE uint64_t __SMLSLD(uint32_t op1, uint32_t op2, uint64_t acc) +{ + union llreg_u + { + uint32_t w32[2]; + uint64_t w64; + } llr; + llr.w64 = acc; + +#ifndef __ARMEB__ /* Little endian */ + __ASM volatile("smlsld %0, %1, %2, %3" : "=r"(llr.w32[0]), "=r"(llr.w32[1]): "r"(op1), "r"(op2), "0"(llr.w32[0]), "1"(llr.w32[1])); +#else /* Big endian */ + __ASM volatile("smlsld %0, %1, %2, %3" : "=r"(llr.w32[1]), "=r"(llr.w32[0]): "r"(op1), "r"(op2), "0"(llr.w32[1]), "1"(llr.w32[0])); +#endif + + return (llr.w64); +} + +__attribute__((always_inline)) __STATIC_INLINE uint64_t __SMLSLDX(uint32_t op1, uint32_t op2, uint64_t acc) +{ + union llreg_u + { + uint32_t w32[2]; + uint64_t w64; + } llr; + llr.w64 = acc; + +#ifndef __ARMEB__ /* Little endian */ + __ASM volatile("smlsldx %0, %1, %2, %3" : "=r"(llr.w32[0]), "=r"(llr.w32[1]): "r"(op1), "r"(op2), "0"(llr.w32[0]), "1"(llr.w32[1])); +#else /* Big endian */ + __ASM volatile("smlsldx %0, %1, %2, %3" : "=r"(llr.w32[1]), "=r"(llr.w32[0]): "r"(op1), "r"(op2), "0"(llr.w32[1]), "1"(llr.w32[0])); +#endif + + return (llr.w64); +} + +__attribute__((always_inline)) __STATIC_INLINE uint32_t __SEL(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile("sel %0, %1, %2" : "=r"(result) : "r"(op1), "r"(op2)); + return (result); +} + +__attribute__((always_inline)) __STATIC_INLINE int32_t __QADD(int32_t op1, int32_t op2) +{ + int32_t result; + + __ASM volatile("qadd %0, %1, %2" : "=r"(result) : "r"(op1), "r"(op2)); + return (result); +} + +__attribute__((always_inline)) __STATIC_INLINE int32_t __QSUB(int32_t op1, int32_t op2) +{ + int32_t result; + + __ASM volatile("qsub %0, %1, %2" : "=r"(result) : "r"(op1), "r"(op2)); + return (result); +} + +#define __PKHBT(ARG1,ARG2,ARG3) \ +({ \ + uint32_t __RES, __ARG1 = (ARG1), __ARG2 = (ARG2); \ + __ASM ("pkhbt %0, %1, %2, lsl %3" : "=r" (__RES) : "r" (__ARG1), "r" (__ARG2), "I" (ARG3) ); \ + __RES; \ + }) + +#define __PKHTB(ARG1,ARG2,ARG3) \ +({ \ + uint32_t __RES, __ARG1 = (ARG1), __ARG2 = (ARG2); \ + if (ARG3 == 0) \ + __ASM ("pkhtb %0, %1, %2" : "=r" (__RES) : "r" (__ARG1), "r" (__ARG2) ); \ + else \ + __ASM ("pkhtb %0, %1, %2, asr %3" : "=r" (__RES) : "r" (__ARG1), "r" (__ARG2), "I" (ARG3) ); \ + __RES; \ + }) + +__attribute__((always_inline)) __STATIC_INLINE uint32_t __SMMLA(int32_t op1, int32_t op2, int32_t op3) +{ + int32_t result; + + __ASM volatile("smmla %0, %1, %2, %3" : "=r"(result): "r"(op1), "r"(op2), "r"(op3)); + return (result); +} + +#endif /* (__ARM_FEATURE_DSP == 1U) */ +/*@} end of group CMSIS_SIMD_intrinsics */ + + +#endif /* __CMSIS_ARMCC_V6_H */ diff --git a/bsp/nuvoton/libraries/ma35/CMSIS/Include/cmsis_gcc.h b/bsp/nuvoton/libraries/ma35/CMSIS/Include/cmsis_gcc.h new file mode 100644 index 0000000000..815df3ea75 --- /dev/null +++ b/bsp/nuvoton/libraries/ma35/CMSIS/Include/cmsis_gcc.h @@ -0,0 +1,1377 @@ +/**************************************************************************//** + * @file cmsis_gcc.h + * @brief CMSIS Cortex-M Core Function/Instruction Header File + * @version V4.30 + * @date 20. October 2015 + ******************************************************************************/ +/* Copyright (c) 2009 - 2015 ARM LIMITED + + All rights reserved. + Redistribution and use in source and binary forms, with or without + modification, are permitted provided that the following conditions are met: + - Redistributions of source code must retain the above copyright + notice, this list of conditions and the following disclaimer. + - Redistributions in binary form must reproduce the above copyright + notice, this list of conditions and the following disclaimer in the + documentation and/or other materials provided with the distribution. + - Neither the name of ARM nor the names of its contributors may be used + to endorse or promote products derived from this software without + specific prior written permission. + * + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE + LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + POSSIBILITY OF SUCH DAMAGE. + ---------------------------------------------------------------------------*/ + + +#ifndef __CMSIS_GCC_H +#define __CMSIS_GCC_H + +/* ignore some GCC warnings */ +#if defined ( __GNUC__ ) + #pragma GCC diagnostic push + #pragma GCC diagnostic ignored "-Wsign-conversion" + #pragma GCC diagnostic ignored "-Wconversion" + #pragma GCC diagnostic ignored "-Wunused-parameter" +#endif + + +/* ########################### Core Function Access ########################### */ +/** \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_RegAccFunctions CMSIS Core Register Access Functions + @{ + */ + +/** + \brief Enable IRQ Interrupts + \details Enables IRQ interrupts by clearing the I-bit in the CPSR. + Can only be executed in Privileged modes. + */ +__attribute__((always_inline)) __STATIC_INLINE void __enable_irq(void) +{ + __ASM volatile("cpsie i" : : : "memory"); +} + + +/** + \brief Disable IRQ Interrupts + \details Disables IRQ interrupts by setting the I-bit in the CPSR. + Can only be executed in Privileged modes. + */ +__attribute__((always_inline)) __STATIC_INLINE void __disable_irq(void) +{ + __ASM volatile("cpsid i" : : : "memory"); +} + + +/** + \brief Get Control Register + \details Returns the content of the Control Register. + \return Control Register value + */ +__attribute__((always_inline)) __STATIC_INLINE uint32_t __get_CONTROL(void) +{ + uint32_t result; + + __ASM volatile("MRS %0, control" : "=r"(result)); + return (result); +} + + +/** + \brief Set Control Register + \details Writes the given value to the Control Register. + \param [in] control Control Register value to set + */ +__attribute__((always_inline)) __STATIC_INLINE void __set_CONTROL(uint32_t control) +{ + __ASM volatile("MSR control, %0" : : "r"(control) : "memory"); +} + + +/** + \brief Get IPSR Register + \details Returns the content of the IPSR Register. + \return IPSR Register value + */ +__attribute__((always_inline)) __STATIC_INLINE uint32_t __get_IPSR(void) +{ + uint32_t result; + + __ASM volatile("MRS %0, ipsr" : "=r"(result)); + return (result); +} + + +/** + \brief Get APSR Register + \details Returns the content of the APSR Register. + \return APSR Register value + */ +__attribute__((always_inline)) __STATIC_INLINE uint32_t __get_APSR(void) +{ + uint32_t result; + + __ASM volatile("MRS %0, apsr" : "=r"(result)); + return (result); +} + + +/** + \brief Get xPSR Register + \details Returns the content of the xPSR Register. + + \return xPSR Register value + */ +__attribute__((always_inline)) __STATIC_INLINE uint32_t __get_xPSR(void) +{ + uint32_t result; + + __ASM volatile("MRS %0, xpsr" : "=r"(result)); + return (result); +} + + +/** + \brief Get Process Stack Pointer + \details Returns the current value of the Process Stack Pointer (PSP). + \return PSP Register value + */ +__attribute__((always_inline)) __STATIC_INLINE uint32_t __get_PSP(void) +{ + register uint32_t result; + + __ASM volatile("MRS %0, psp\n" : "=r"(result)); + return (result); +} + + +/** + \brief Set Process Stack Pointer + \details Assigns the given value to the Process Stack Pointer (PSP). + \param [in] topOfProcStack Process Stack Pointer value to set + */ +__attribute__((always_inline)) __STATIC_INLINE void __set_PSP(uint32_t topOfProcStack) +{ + __ASM volatile("MSR psp, %0\n" : : "r"(topOfProcStack) : "sp"); +} + + +/** + \brief Get Main Stack Pointer + \details Returns the current value of the Main Stack Pointer (MSP). + \return MSP Register value + */ +__attribute__((always_inline)) __STATIC_INLINE uint32_t __get_MSP(void) +{ + register uint32_t result; + + __ASM volatile("MRS %0, msp\n" : "=r"(result)); + return (result); +} + + +/** + \brief Set Main Stack Pointer + \details Assigns the given value to the Main Stack Pointer (MSP). + + \param [in] topOfMainStack Main Stack Pointer value to set + */ +__attribute__((always_inline)) __STATIC_INLINE void __set_MSP(uint32_t topOfMainStack) +{ + __ASM volatile("MSR msp, %0\n" : : "r"(topOfMainStack) : "sp"); +} + + +/** + \brief Get Priority Mask + \details Returns the current state of the priority mask bit from the Priority Mask Register. + \return Priority Mask value + */ +__attribute__((always_inline)) __STATIC_INLINE uint32_t __get_PRIMASK(void) +{ + uint32_t result; + + __ASM volatile("MRS %0, primask" : "=r"(result)); + return (result); +} + + +/** + \brief Set Priority Mask + \details Assigns the given value to the Priority Mask Register. + \param [in] priMask Priority Mask + */ +__attribute__((always_inline)) __STATIC_INLINE void __set_PRIMASK(uint32_t priMask) +{ + __ASM volatile("MSR primask, %0" : : "r"(priMask) : "memory"); +} + + +#if (__CORTEX_M >= 0x03U) + +/** + \brief Enable FIQ + \details Enables FIQ interrupts by clearing the F-bit in the CPSR. + Can only be executed in Privileged modes. + */ +__attribute__((always_inline)) __STATIC_INLINE void __enable_fault_irq(void) +{ + __ASM volatile("cpsie f" : : : "memory"); +} + + +/** + \brief Disable FIQ + \details Disables FIQ interrupts by setting the F-bit in the CPSR. + Can only be executed in Privileged modes. + */ +__attribute__((always_inline)) __STATIC_INLINE void __disable_fault_irq(void) +{ + __ASM volatile("cpsid f" : : : "memory"); +} + + +/** + \brief Get Base Priority + \details Returns the current value of the Base Priority register. + \return Base Priority register value + */ +__attribute__((always_inline)) __STATIC_INLINE uint32_t __get_BASEPRI(void) +{ + uint32_t result; + + __ASM volatile("MRS %0, basepri" : "=r"(result)); + return (result); +} + + +/** + \brief Set Base Priority + \details Assigns the given value to the Base Priority register. + \param [in] basePri Base Priority value to set + */ +__attribute__((always_inline)) __STATIC_INLINE void __set_BASEPRI(uint32_t value) +{ + __ASM volatile("MSR basepri, %0" : : "r"(value) : "memory"); +} + + +/** + \brief Set Base Priority with condition + \details Assigns the given value to the Base Priority register only if BASEPRI masking is disabled, + or the new value increases the BASEPRI priority level. + \param [in] basePri Base Priority value to set + */ +__attribute__((always_inline)) __STATIC_INLINE void __set_BASEPRI_MAX(uint32_t value) +{ + __ASM volatile("MSR basepri_max, %0" : : "r"(value) : "memory"); +} + + +/** + \brief Get Fault Mask + \details Returns the current value of the Fault Mask register. + \return Fault Mask register value + */ +__attribute__((always_inline)) __STATIC_INLINE uint32_t __get_FAULTMASK(void) +{ + uint32_t result; + + __ASM volatile("MRS %0, faultmask" : "=r"(result)); + return (result); +} + + +/** + \brief Set Fault Mask + \details Assigns the given value to the Fault Mask register. + \param [in] faultMask Fault Mask value to set + */ +__attribute__((always_inline)) __STATIC_INLINE void __set_FAULTMASK(uint32_t faultMask) +{ + __ASM volatile("MSR faultmask, %0" : : "r"(faultMask) : "memory"); +} + +#endif /* (__CORTEX_M >= 0x03U) */ + + +#if (__CORTEX_M == 0x04U) || (__CORTEX_M == 0x07U) + +/** + \brief Get FPSCR + \details Returns the current value of the Floating Point Status/Control register. + \return Floating Point Status/Control register value + */ +__attribute__((always_inline)) __STATIC_INLINE uint32_t __get_FPSCR(void) +{ +#if (__FPU_PRESENT == 1U) && (__FPU_USED == 1U) + uint32_t result; + + /* Empty asm statement works as a scheduling barrier */ + __ASM volatile(""); + __ASM volatile("VMRS %0, fpscr" : "=r"(result)); + __ASM volatile(""); + return (result); +#else + return (0); +#endif +} + + +/** + \brief Set FPSCR + \details Assigns the given value to the Floating Point Status/Control register. + \param [in] fpscr Floating Point Status/Control value to set + */ +__attribute__((always_inline)) __STATIC_INLINE void __set_FPSCR(uint32_t fpscr) +{ +#if (__FPU_PRESENT == 1U) && (__FPU_USED == 1U) + /* Empty asm statement works as a scheduling barrier */ + __ASM volatile(""); + __ASM volatile("VMSR fpscr, %0" : : "r"(fpscr) : "vfpcc"); + __ASM volatile(""); +#endif +} + +#endif /* (__CORTEX_M == 0x04U) || (__CORTEX_M == 0x07U) */ + + + +/*@} end of CMSIS_Core_RegAccFunctions */ + + +/* ########################## Core Instruction Access ######################### */ +/** \defgroup CMSIS_Core_InstructionInterface CMSIS Core Instruction Interface + Access to dedicated instructions + @{ +*/ + +/* Define macros for porting to both thumb1 and thumb2. + * For thumb1, use low register (r0-r7), specified by constraint "l" + * Otherwise, use general registers, specified by constraint "r" */ +#if defined (__thumb__) && !defined (__thumb2__) + #define __CMSIS_GCC_OUT_REG(r) "=l" (r) + #define __CMSIS_GCC_USE_REG(r) "l" (r) +#else + #define __CMSIS_GCC_OUT_REG(r) "=r" (r) + #define __CMSIS_GCC_USE_REG(r) "r" (r) +#endif + +/** + \brief No Operation + \details No Operation does nothing. This instruction can be used for code alignment purposes. + */ +__attribute__((always_inline)) __STATIC_INLINE void __NOP(void) +{ + __ASM volatile("nop"); +} + + +/** + \brief Wait For Interrupt + \details Wait For Interrupt is a hint instruction that suspends execution until one of a number of events occurs. + */ +__attribute__((always_inline)) __STATIC_INLINE void __WFI(void) +{ + __ASM volatile("wfi"); +} + + +/** + \brief Wait For Event + \details Wait For Event is a hint instruction that permits the processor to enter + a low-power state until one of a number of events occurs. + */ +__attribute__((always_inline)) __STATIC_INLINE void __WFE(void) +{ + __ASM volatile("wfe"); +} + + +/** + \brief Send Event + \details Send Event is a hint instruction. It causes an event to be signaled to the CPU. + */ +__attribute__((always_inline)) __STATIC_INLINE void __SEV(void) +{ + __ASM volatile("sev"); +} + + +/** + \brief Instruction Synchronization Barrier + \details Instruction Synchronization Barrier flushes the pipeline in the processor, + so that all instructions following the ISB are fetched from cache or memory, + after the instruction has been completed. + */ +__attribute__((always_inline)) __STATIC_INLINE void __ISB(void) +{ + __ASM volatile("isb 0xF"::: "memory"); +} + + +/** + \brief Data Synchronization Barrier + \details Acts as a special kind of Data Memory Barrier. + It completes when all explicit memory accesses before this instruction complete. + */ +__attribute__((always_inline)) __STATIC_INLINE void __DSB(void) +{ + __ASM volatile("dsb 0xF"::: "memory"); +} + + +/** + \brief Data Memory Barrier + \details Ensures the apparent order of the explicit memory operations before + and after the instruction, without ensuring their completion. + */ +__attribute__((always_inline)) __STATIC_INLINE void __DMB(void) +{ + __ASM volatile("dmb 0xF"::: "memory"); +} + + +/** + \brief Reverse byte order (32 bit) + \details Reverses the byte order in integer value. + \param [in] value Value to reverse + \return Reversed value + */ +__attribute__((always_inline)) __STATIC_INLINE uint32_t __REV(uint32_t value) +{ +#if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 5) + return __builtin_bswap32(value); +#else + uint32_t result; + + __ASM volatile("rev %0, %1" : __CMSIS_GCC_OUT_REG(result) : __CMSIS_GCC_USE_REG(value)); + return (result); +#endif +} + + +/** + \brief Reverse byte order (16 bit) + \details Reverses the byte order in two unsigned short values. + \param [in] value Value to reverse + \return Reversed value + */ +__attribute__((always_inline)) __STATIC_INLINE uint32_t __REV16(uint32_t value) +{ + uint32_t result; + + __ASM volatile("rev16 %0, %1" : __CMSIS_GCC_OUT_REG(result) : __CMSIS_GCC_USE_REG(value)); + return (result); +} + + +/** + \brief Reverse byte order in signed short value + \details Reverses the byte order in a signed short value with sign extension to integer. + \param [in] value Value to reverse + \return Reversed value + */ +__attribute__((always_inline)) __STATIC_INLINE int32_t __REVSH(int32_t value) +{ +#if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 8) + return (short)__builtin_bswap16(value); +#else + int32_t result; + + __ASM volatile("revsh %0, %1" : __CMSIS_GCC_OUT_REG(result) : __CMSIS_GCC_USE_REG(value)); + return (result); +#endif +} + + +/** + \brief Rotate Right in unsigned value (32 bit) + \details Rotate Right (immediate) provides the value of the contents of a register rotated by a variable number of bits. + \param [in] value Value to rotate + \param [in] value Number of Bits to rotate + \return Rotated value + */ +__attribute__((always_inline)) __STATIC_INLINE uint32_t __ROR(uint32_t op1, uint32_t op2) +{ + return (op1 >> op2) | (op1 << (32U - op2)); +} + + +/** + \brief Breakpoint + \details Causes the processor to enter Debug state. + Debug tools can use this to investigate system state when the instruction at a particular address is reached. + \param [in] value is ignored by the processor. + If required, a debugger can use it to store additional information about the breakpoint. + */ +#define __BKPT(value) __ASM volatile ("bkpt "#value) + + +/** + \brief Reverse bit order of value + \details Reverses the bit order of the given value. + \param [in] value Value to reverse + \return Reversed value + */ +__attribute__((always_inline)) __STATIC_INLINE uint32_t __RBIT(uint32_t value) +{ + uint32_t result; + +#if (__CORTEX_M >= 0x03U) || (__CORTEX_SC >= 300U) + __ASM volatile("rbit %0, %1" : "=r"(result) : "r"(value)); +#else + int32_t s = 4 /*sizeof(v)*/ * 8 - 1; /* extra shift needed at end */ + + result = value; /* r will be reversed bits of v; first get LSB of v */ + for (value >>= 1U; value; value >>= 1U) + { + result <<= 1U; + result |= value & 1U; + s--; + } + result <<= s; /* shift when v's highest bits are zero */ +#endif + return (result); +} + + +/** + \brief Count leading zeros + \details Counts the number of leading zeros of a data value. + \param [in] value Value to count the leading zeros + \return number of leading zeros in value + */ +#define __CLZ __builtin_clz + + +#if (__CORTEX_M >= 0x03U) || (__CORTEX_SC >= 300U) + +/** + \brief LDR Exclusive (8 bit) + \details Executes a exclusive LDR instruction for 8 bit value. + \param [in] ptr Pointer to data + \return value of type uint8_t at (*ptr) + */ +__attribute__((always_inline)) __STATIC_INLINE uint8_t __LDREXB(volatile uint8_t *addr) +{ + uint32_t result; + +#if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 8) + __ASM volatile("ldrexb %0, %1" : "=r"(result) : "Q"(*addr)); +#else + /* Prior to GCC 4.8, "Q" will be expanded to [rx, #0] which is not + accepted by assembler. So has to use following less efficient pattern. + */ + __ASM volatile("ldrexb %0, [%1]" : "=r"(result) : "r"(addr) : "memory"); +#endif + return ((uint8_t) result); /* Add explicit type cast here */ +} + + +/** + \brief LDR Exclusive (16 bit) + \details Executes a exclusive LDR instruction for 16 bit values. + \param [in] ptr Pointer to data + \return value of type uint16_t at (*ptr) + */ +__attribute__((always_inline)) __STATIC_INLINE uint16_t __LDREXH(volatile uint16_t *addr) +{ + uint32_t result; + +#if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 8) + __ASM volatile("ldrexh %0, %1" : "=r"(result) : "Q"(*addr)); +#else + /* Prior to GCC 4.8, "Q" will be expanded to [rx, #0] which is not + accepted by assembler. So has to use following less efficient pattern. + */ + __ASM volatile("ldrexh %0, [%1]" : "=r"(result) : "r"(addr) : "memory"); +#endif + return ((uint16_t) result); /* Add explicit type cast here */ +} + + +/** + \brief LDR Exclusive (32 bit) + \details Executes a exclusive LDR instruction for 32 bit values. + \param [in] ptr Pointer to data + \return value of type uint32_t at (*ptr) + */ +__attribute__((always_inline)) __STATIC_INLINE uint32_t __LDREXW(volatile uint32_t *addr) +{ + uint32_t result; + + __ASM volatile("ldrex %0, %1" : "=r"(result) : "Q"(*addr)); + return (result); +} + + +/** + \brief STR Exclusive (8 bit) + \details Executes a exclusive STR instruction for 8 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + \return 0 Function succeeded + \return 1 Function failed + */ +__attribute__((always_inline)) __STATIC_INLINE uint32_t __STREXB(uint8_t value, volatile uint8_t *addr) +{ + uint32_t result; + + __ASM volatile("strexb %0, %2, %1" : "=&r"(result), "=Q"(*addr) : "r"((uint32_t)value)); + return (result); +} + + +/** + \brief STR Exclusive (16 bit) + \details Executes a exclusive STR instruction for 16 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + \return 0 Function succeeded + \return 1 Function failed + */ +__attribute__((always_inline)) __STATIC_INLINE uint32_t __STREXH(uint16_t value, volatile uint16_t *addr) +{ + uint32_t result; + + __ASM volatile("strexh %0, %2, %1" : "=&r"(result), "=Q"(*addr) : "r"((uint32_t)value)); + return (result); +} + + +/** + \brief STR Exclusive (32 bit) + \details Executes a exclusive STR instruction for 32 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + \return 0 Function succeeded + \return 1 Function failed + */ +__attribute__((always_inline)) __STATIC_INLINE uint32_t __STREXW(uint32_t value, volatile uint32_t *addr) +{ + uint32_t result; + + __ASM volatile("strex %0, %2, %1" : "=&r"(result), "=Q"(*addr) : "r"(value)); + return (result); +} + + +/** + \brief Remove the exclusive lock + \details Removes the exclusive lock which is created by LDREX. + */ +__attribute__((always_inline)) __STATIC_INLINE void __CLREX(void) +{ + __ASM volatile("clrex" ::: "memory"); +} + + +/** + \brief Signed Saturate + \details Saturates a signed value. + \param [in] value Value to be saturated + \param [in] sat Bit position to saturate to (1..32) + \return Saturated value + */ +#define __SSAT(ARG1,ARG2) \ +({ \ + uint32_t __RES, __ARG1 = (ARG1); \ + __ASM ("ssat %0, %1, %2" : "=r" (__RES) : "I" (ARG2), "r" (__ARG1) ); \ + __RES; \ + }) + + +/** + \brief Unsigned Saturate + \details Saturates an unsigned value. + \param [in] value Value to be saturated + \param [in] sat Bit position to saturate to (0..31) + \return Saturated value + */ +#define __USAT(ARG1,ARG2) \ +({ \ + uint32_t __RES, __ARG1 = (ARG1); \ + __ASM ("usat %0, %1, %2" : "=r" (__RES) : "I" (ARG2), "r" (__ARG1) ); \ + __RES; \ + }) + + +/** + \brief Rotate Right with Extend (32 bit) + \details Moves each bit of a bitstring right by one bit. + The carry input is shifted in at the left end of the bitstring. + \param [in] value Value to rotate + \return Rotated value + */ +__attribute__((always_inline)) __STATIC_INLINE uint32_t __RRX(uint32_t value) +{ + uint32_t result; + + __ASM volatile("rrx %0, %1" : __CMSIS_GCC_OUT_REG(result) : __CMSIS_GCC_USE_REG(value)); + return (result); +} + + +/** + \brief LDRT Unprivileged (8 bit) + \details Executes a Unprivileged LDRT instruction for 8 bit value. + \param [in] ptr Pointer to data + \return value of type uint8_t at (*ptr) + */ +__attribute__((always_inline)) __STATIC_INLINE uint8_t __LDRBT(volatile uint8_t *addr) +{ + uint32_t result; + +#if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 8) + __ASM volatile("ldrbt %0, %1" : "=r"(result) : "Q"(*addr)); +#else + /* Prior to GCC 4.8, "Q" will be expanded to [rx, #0] which is not + accepted by assembler. So has to use following less efficient pattern. + */ + __ASM volatile("ldrbt %0, [%1]" : "=r"(result) : "r"(addr) : "memory"); +#endif + return ((uint8_t) result); /* Add explicit type cast here */ +} + + +/** + \brief LDRT Unprivileged (16 bit) + \details Executes a Unprivileged LDRT instruction for 16 bit values. + \param [in] ptr Pointer to data + \return value of type uint16_t at (*ptr) + */ +__attribute__((always_inline)) __STATIC_INLINE uint16_t __LDRHT(volatile uint16_t *addr) +{ + uint32_t result; + +#if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 8) + __ASM volatile("ldrht %0, %1" : "=r"(result) : "Q"(*addr)); +#else + /* Prior to GCC 4.8, "Q" will be expanded to [rx, #0] which is not + accepted by assembler. So has to use following less efficient pattern. + */ + __ASM volatile("ldrht %0, [%1]" : "=r"(result) : "r"(addr) : "memory"); +#endif + return ((uint16_t) result); /* Add explicit type cast here */ +} + + +/** + \brief LDRT Unprivileged (32 bit) + \details Executes a Unprivileged LDRT instruction for 32 bit values. + \param [in] ptr Pointer to data + \return value of type uint32_t at (*ptr) + */ +__attribute__((always_inline)) __STATIC_INLINE uint32_t __LDRT(volatile uint32_t *addr) +{ + uint32_t result; + + __ASM volatile("ldrt %0, %1" : "=r"(result) : "Q"(*addr)); + return (result); +} + + +/** + \brief STRT Unprivileged (8 bit) + \details Executes a Unprivileged STRT instruction for 8 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + */ +__attribute__((always_inline)) __STATIC_INLINE void __STRBT(uint8_t value, volatile uint8_t *addr) +{ + __ASM volatile("strbt %1, %0" : "=Q"(*addr) : "r"((uint32_t)value)); +} + + +/** + \brief STRT Unprivileged (16 bit) + \details Executes a Unprivileged STRT instruction for 16 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + */ +__attribute__((always_inline)) __STATIC_INLINE void __STRHT(uint16_t value, volatile uint16_t *addr) +{ + __ASM volatile("strht %1, %0" : "=Q"(*addr) : "r"((uint32_t)value)); +} + + +/** + \brief STRT Unprivileged (32 bit) + \details Executes a Unprivileged STRT instruction for 32 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + */ +__attribute__((always_inline)) __STATIC_INLINE void __STRT(uint32_t value, volatile uint32_t *addr) +{ + __ASM volatile("strt %1, %0" : "=Q"(*addr) : "r"(value)); +} + +#endif /* (__CORTEX_M >= 0x03U) || (__CORTEX_SC >= 300U) */ + +/*@}*/ /* end of group CMSIS_Core_InstructionInterface */ + + +/* ################### Compiler specific Intrinsics ########################### */ +/** \defgroup CMSIS_SIMD_intrinsics CMSIS SIMD Intrinsics + Access to dedicated SIMD instructions + @{ +*/ + +#if (__CORTEX_M >= 0x04U) /* only for Cortex-M4 and above */ + +__attribute__((always_inline)) __STATIC_INLINE uint32_t __SADD8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile("sadd8 %0, %1, %2" : "=r"(result) : "r"(op1), "r"(op2)); + return (result); +} + +__attribute__((always_inline)) __STATIC_INLINE uint32_t __QADD8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile("qadd8 %0, %1, %2" : "=r"(result) : "r"(op1), "r"(op2)); + return (result); +} + +__attribute__((always_inline)) __STATIC_INLINE uint32_t __SHADD8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile("shadd8 %0, %1, %2" : "=r"(result) : "r"(op1), "r"(op2)); + return (result); +} + +__attribute__((always_inline)) __STATIC_INLINE uint32_t __UADD8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile("uadd8 %0, %1, %2" : "=r"(result) : "r"(op1), "r"(op2)); + return (result); +} + +__attribute__((always_inline)) __STATIC_INLINE uint32_t __UQADD8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile("uqadd8 %0, %1, %2" : "=r"(result) : "r"(op1), "r"(op2)); + return (result); +} + +__attribute__((always_inline)) __STATIC_INLINE uint32_t __UHADD8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile("uhadd8 %0, %1, %2" : "=r"(result) : "r"(op1), "r"(op2)); + return (result); +} + + +__attribute__((always_inline)) __STATIC_INLINE uint32_t __SSUB8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile("ssub8 %0, %1, %2" : "=r"(result) : "r"(op1), "r"(op2)); + return (result); +} + +__attribute__((always_inline)) __STATIC_INLINE uint32_t __QSUB8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile("qsub8 %0, %1, %2" : "=r"(result) : "r"(op1), "r"(op2)); + return (result); +} + +__attribute__((always_inline)) __STATIC_INLINE uint32_t __SHSUB8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile("shsub8 %0, %1, %2" : "=r"(result) : "r"(op1), "r"(op2)); + return (result); +} + +__attribute__((always_inline)) __STATIC_INLINE uint32_t __USUB8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile("usub8 %0, %1, %2" : "=r"(result) : "r"(op1), "r"(op2)); + return (result); +} + +__attribute__((always_inline)) __STATIC_INLINE uint32_t __UQSUB8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile("uqsub8 %0, %1, %2" : "=r"(result) : "r"(op1), "r"(op2)); + return (result); +} + +__attribute__((always_inline)) __STATIC_INLINE uint32_t __UHSUB8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile("uhsub8 %0, %1, %2" : "=r"(result) : "r"(op1), "r"(op2)); + return (result); +} + + +__attribute__((always_inline)) __STATIC_INLINE uint32_t __SADD16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile("sadd16 %0, %1, %2" : "=r"(result) : "r"(op1), "r"(op2)); + return (result); +} + +__attribute__((always_inline)) __STATIC_INLINE uint32_t __QADD16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile("qadd16 %0, %1, %2" : "=r"(result) : "r"(op1), "r"(op2)); + return (result); +} + +__attribute__((always_inline)) __STATIC_INLINE uint32_t __SHADD16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile("shadd16 %0, %1, %2" : "=r"(result) : "r"(op1), "r"(op2)); + return (result); +} + +__attribute__((always_inline)) __STATIC_INLINE uint32_t __UADD16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile("uadd16 %0, %1, %2" : "=r"(result) : "r"(op1), "r"(op2)); + return (result); +} + +__attribute__((always_inline)) __STATIC_INLINE uint32_t __UQADD16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile("uqadd16 %0, %1, %2" : "=r"(result) : "r"(op1), "r"(op2)); + return (result); +} + +__attribute__((always_inline)) __STATIC_INLINE uint32_t __UHADD16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile("uhadd16 %0, %1, %2" : "=r"(result) : "r"(op1), "r"(op2)); + return (result); +} + +__attribute__((always_inline)) __STATIC_INLINE uint32_t __SSUB16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile("ssub16 %0, %1, %2" : "=r"(result) : "r"(op1), "r"(op2)); + return (result); +} + +__attribute__((always_inline)) __STATIC_INLINE uint32_t __QSUB16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile("qsub16 %0, %1, %2" : "=r"(result) : "r"(op1), "r"(op2)); + return (result); +} + +__attribute__((always_inline)) __STATIC_INLINE uint32_t __SHSUB16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile("shsub16 %0, %1, %2" : "=r"(result) : "r"(op1), "r"(op2)); + return (result); +} + +__attribute__((always_inline)) __STATIC_INLINE uint32_t __USUB16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile("usub16 %0, %1, %2" : "=r"(result) : "r"(op1), "r"(op2)); + return (result); +} + +__attribute__((always_inline)) __STATIC_INLINE uint32_t __UQSUB16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile("uqsub16 %0, %1, %2" : "=r"(result) : "r"(op1), "r"(op2)); + return (result); +} + +__attribute__((always_inline)) __STATIC_INLINE uint32_t __UHSUB16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile("uhsub16 %0, %1, %2" : "=r"(result) : "r"(op1), "r"(op2)); + return (result); +} + +__attribute__((always_inline)) __STATIC_INLINE uint32_t __SASX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile("sasx %0, %1, %2" : "=r"(result) : "r"(op1), "r"(op2)); + return (result); +} + +__attribute__((always_inline)) __STATIC_INLINE uint32_t __QASX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile("qasx %0, %1, %2" : "=r"(result) : "r"(op1), "r"(op2)); + return (result); +} + +__attribute__((always_inline)) __STATIC_INLINE uint32_t __SHASX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile("shasx %0, %1, %2" : "=r"(result) : "r"(op1), "r"(op2)); + return (result); +} + +__attribute__((always_inline)) __STATIC_INLINE uint32_t __UASX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile("uasx %0, %1, %2" : "=r"(result) : "r"(op1), "r"(op2)); + return (result); +} + +__attribute__((always_inline)) __STATIC_INLINE uint32_t __UQASX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile("uqasx %0, %1, %2" : "=r"(result) : "r"(op1), "r"(op2)); + return (result); +} + +__attribute__((always_inline)) __STATIC_INLINE uint32_t __UHASX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile("uhasx %0, %1, %2" : "=r"(result) : "r"(op1), "r"(op2)); + return (result); +} + +__attribute__((always_inline)) __STATIC_INLINE uint32_t __SSAX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile("ssax %0, %1, %2" : "=r"(result) : "r"(op1), "r"(op2)); + return (result); +} + +__attribute__((always_inline)) __STATIC_INLINE uint32_t __QSAX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile("qsax %0, %1, %2" : "=r"(result) : "r"(op1), "r"(op2)); + return (result); +} + +__attribute__((always_inline)) __STATIC_INLINE uint32_t __SHSAX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile("shsax %0, %1, %2" : "=r"(result) : "r"(op1), "r"(op2)); + return (result); +} + +__attribute__((always_inline)) __STATIC_INLINE uint32_t __USAX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile("usax %0, %1, %2" : "=r"(result) : "r"(op1), "r"(op2)); + return (result); +} + +__attribute__((always_inline)) __STATIC_INLINE uint32_t __UQSAX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile("uqsax %0, %1, %2" : "=r"(result) : "r"(op1), "r"(op2)); + return (result); +} + +__attribute__((always_inline)) __STATIC_INLINE uint32_t __UHSAX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile("uhsax %0, %1, %2" : "=r"(result) : "r"(op1), "r"(op2)); + return (result); +} + +__attribute__((always_inline)) __STATIC_INLINE uint32_t __USAD8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile("usad8 %0, %1, %2" : "=r"(result) : "r"(op1), "r"(op2)); + return (result); +} + +__attribute__((always_inline)) __STATIC_INLINE uint32_t __USADA8(uint32_t op1, uint32_t op2, uint32_t op3) +{ + uint32_t result; + + __ASM volatile("usada8 %0, %1, %2, %3" : "=r"(result) : "r"(op1), "r"(op2), "r"(op3)); + return (result); +} + +#define __SSAT16(ARG1,ARG2) \ +({ \ + int32_t __RES, __ARG1 = (ARG1); \ + __ASM ("ssat16 %0, %1, %2" : "=r" (__RES) : "I" (ARG2), "r" (__ARG1) ); \ + __RES; \ + }) + +#define __USAT16(ARG1,ARG2) \ +({ \ + uint32_t __RES, __ARG1 = (ARG1); \ + __ASM ("usat16 %0, %1, %2" : "=r" (__RES) : "I" (ARG2), "r" (__ARG1) ); \ + __RES; \ + }) + +__attribute__((always_inline)) __STATIC_INLINE uint32_t __UXTB16(uint32_t op1) +{ + uint32_t result; + + __ASM volatile("uxtb16 %0, %1" : "=r"(result) : "r"(op1)); + return (result); +} + +__attribute__((always_inline)) __STATIC_INLINE uint32_t __UXTAB16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile("uxtab16 %0, %1, %2" : "=r"(result) : "r"(op1), "r"(op2)); + return (result); +} + +__attribute__((always_inline)) __STATIC_INLINE uint32_t __SXTB16(uint32_t op1) +{ + uint32_t result; + + __ASM volatile("sxtb16 %0, %1" : "=r"(result) : "r"(op1)); + return (result); +} + +__attribute__((always_inline)) __STATIC_INLINE uint32_t __SXTAB16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile("sxtab16 %0, %1, %2" : "=r"(result) : "r"(op1), "r"(op2)); + return (result); +} + +__attribute__((always_inline)) __STATIC_INLINE uint32_t __SMUAD(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile("smuad %0, %1, %2" : "=r"(result) : "r"(op1), "r"(op2)); + return (result); +} + +__attribute__((always_inline)) __STATIC_INLINE uint32_t __SMUADX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile("smuadx %0, %1, %2" : "=r"(result) : "r"(op1), "r"(op2)); + return (result); +} + +__attribute__((always_inline)) __STATIC_INLINE uint32_t __SMLAD(uint32_t op1, uint32_t op2, uint32_t op3) +{ + uint32_t result; + + __ASM volatile("smlad %0, %1, %2, %3" : "=r"(result) : "r"(op1), "r"(op2), "r"(op3)); + return (result); +} + +__attribute__((always_inline)) __STATIC_INLINE uint32_t __SMLADX(uint32_t op1, uint32_t op2, uint32_t op3) +{ + uint32_t result; + + __ASM volatile("smladx %0, %1, %2, %3" : "=r"(result) : "r"(op1), "r"(op2), "r"(op3)); + return (result); +} + +__attribute__((always_inline)) __STATIC_INLINE uint64_t __SMLALD(uint32_t op1, uint32_t op2, uint64_t acc) +{ + union llreg_u + { + uint32_t w32[2]; + uint64_t w64; + } llr; + llr.w64 = acc; + +#ifndef __ARMEB__ /* Little endian */ + __ASM volatile("smlald %0, %1, %2, %3" : "=r"(llr.w32[0]), "=r"(llr.w32[1]): "r"(op1), "r"(op2), "0"(llr.w32[0]), "1"(llr.w32[1])); +#else /* Big endian */ + __ASM volatile("smlald %0, %1, %2, %3" : "=r"(llr.w32[1]), "=r"(llr.w32[0]): "r"(op1), "r"(op2), "0"(llr.w32[1]), "1"(llr.w32[0])); +#endif + + return (llr.w64); +} + +__attribute__((always_inline)) __STATIC_INLINE uint64_t __SMLALDX(uint32_t op1, uint32_t op2, uint64_t acc) +{ + union llreg_u + { + uint32_t w32[2]; + uint64_t w64; + } llr; + llr.w64 = acc; + +#ifndef __ARMEB__ /* Little endian */ + __ASM volatile("smlaldx %0, %1, %2, %3" : "=r"(llr.w32[0]), "=r"(llr.w32[1]): "r"(op1), "r"(op2), "0"(llr.w32[0]), "1"(llr.w32[1])); +#else /* Big endian */ + __ASM volatile("smlaldx %0, %1, %2, %3" : "=r"(llr.w32[1]), "=r"(llr.w32[0]): "r"(op1), "r"(op2), "0"(llr.w32[1]), "1"(llr.w32[0])); +#endif + + return (llr.w64); +} + +__attribute__((always_inline)) __STATIC_INLINE uint32_t __SMUSD(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile("smusd %0, %1, %2" : "=r"(result) : "r"(op1), "r"(op2)); + return (result); +} + +__attribute__((always_inline)) __STATIC_INLINE uint32_t __SMUSDX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile("smusdx %0, %1, %2" : "=r"(result) : "r"(op1), "r"(op2)); + return (result); +} + +__attribute__((always_inline)) __STATIC_INLINE uint32_t __SMLSD(uint32_t op1, uint32_t op2, uint32_t op3) +{ + uint32_t result; + + __ASM volatile("smlsd %0, %1, %2, %3" : "=r"(result) : "r"(op1), "r"(op2), "r"(op3)); + return (result); +} + +__attribute__((always_inline)) __STATIC_INLINE uint32_t __SMLSDX(uint32_t op1, uint32_t op2, uint32_t op3) +{ + uint32_t result; + + __ASM volatile("smlsdx %0, %1, %2, %3" : "=r"(result) : "r"(op1), "r"(op2), "r"(op3)); + return (result); +} + +__attribute__((always_inline)) __STATIC_INLINE uint64_t __SMLSLD(uint32_t op1, uint32_t op2, uint64_t acc) +{ + union llreg_u + { + uint32_t w32[2]; + uint64_t w64; + } llr; + llr.w64 = acc; + +#ifndef __ARMEB__ /* Little endian */ + __ASM volatile("smlsld %0, %1, %2, %3" : "=r"(llr.w32[0]), "=r"(llr.w32[1]): "r"(op1), "r"(op2), "0"(llr.w32[0]), "1"(llr.w32[1])); +#else /* Big endian */ + __ASM volatile("smlsld %0, %1, %2, %3" : "=r"(llr.w32[1]), "=r"(llr.w32[0]): "r"(op1), "r"(op2), "0"(llr.w32[1]), "1"(llr.w32[0])); +#endif + + return (llr.w64); +} + +__attribute__((always_inline)) __STATIC_INLINE uint64_t __SMLSLDX(uint32_t op1, uint32_t op2, uint64_t acc) +{ + union llreg_u + { + uint32_t w32[2]; + uint64_t w64; + } llr; + llr.w64 = acc; + +#ifndef __ARMEB__ /* Little endian */ + __ASM volatile("smlsldx %0, %1, %2, %3" : "=r"(llr.w32[0]), "=r"(llr.w32[1]): "r"(op1), "r"(op2), "0"(llr.w32[0]), "1"(llr.w32[1])); +#else /* Big endian */ + __ASM volatile("smlsldx %0, %1, %2, %3" : "=r"(llr.w32[1]), "=r"(llr.w32[0]): "r"(op1), "r"(op2), "0"(llr.w32[1]), "1"(llr.w32[0])); +#endif + + return (llr.w64); +} + +__attribute__((always_inline)) __STATIC_INLINE uint32_t __SEL(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile("sel %0, %1, %2" : "=r"(result) : "r"(op1), "r"(op2)); + return (result); +} + +__attribute__((always_inline)) __STATIC_INLINE int32_t __QADD(int32_t op1, int32_t op2) +{ + int32_t result; + + __ASM volatile("qadd %0, %1, %2" : "=r"(result) : "r"(op1), "r"(op2)); + return (result); +} + +__attribute__((always_inline)) __STATIC_INLINE int32_t __QSUB(int32_t op1, int32_t op2) +{ + int32_t result; + + __ASM volatile("qsub %0, %1, %2" : "=r"(result) : "r"(op1), "r"(op2)); + return (result); +} + +#define __PKHBT(ARG1,ARG2,ARG3) \ +({ \ + uint32_t __RES, __ARG1 = (ARG1), __ARG2 = (ARG2); \ + __ASM ("pkhbt %0, %1, %2, lsl %3" : "=r" (__RES) : "r" (__ARG1), "r" (__ARG2), "I" (ARG3) ); \ + __RES; \ + }) + +#define __PKHTB(ARG1,ARG2,ARG3) \ +({ \ + uint32_t __RES, __ARG1 = (ARG1), __ARG2 = (ARG2); \ + if (ARG3 == 0) \ + __ASM ("pkhtb %0, %1, %2" : "=r" (__RES) : "r" (__ARG1), "r" (__ARG2) ); \ + else \ + __ASM ("pkhtb %0, %1, %2, asr %3" : "=r" (__RES) : "r" (__ARG1), "r" (__ARG2), "I" (ARG3) ); \ + __RES; \ + }) + +__attribute__((always_inline)) __STATIC_INLINE uint32_t __SMMLA(int32_t op1, int32_t op2, int32_t op3) +{ + int32_t result; + + __ASM volatile("smmla %0, %1, %2, %3" : "=r"(result): "r"(op1), "r"(op2), "r"(op3)); + return (result); +} + +#endif /* (__CORTEX_M >= 0x04) */ +/*@} end of group CMSIS_SIMD_intrinsics */ + + +#if defined ( __GNUC__ ) + #pragma GCC diagnostic pop +#endif + +#endif /* __CMSIS_GCC_H */ diff --git a/bsp/nuvoton/libraries/ma35/CMSIS/Include/core_cm0.h b/bsp/nuvoton/libraries/ma35/CMSIS/Include/core_cm0.h new file mode 100644 index 0000000000..81e63175d7 --- /dev/null +++ b/bsp/nuvoton/libraries/ma35/CMSIS/Include/core_cm0.h @@ -0,0 +1,798 @@ +/**************************************************************************//** + * @file core_cm0.h + * @brief CMSIS Cortex-M0 Core Peripheral Access Layer Header File + * @version V4.30 + * @date 20. October 2015 + ******************************************************************************/ +/* Copyright (c) 2009 - 2015 ARM LIMITED + + All rights reserved. + Redistribution and use in source and binary forms, with or without + modification, are permitted provided that the following conditions are met: + - Redistributions of source code must retain the above copyright + notice, this list of conditions and the following disclaimer. + - Redistributions in binary form must reproduce the above copyright + notice, this list of conditions and the following disclaimer in the + documentation and/or other materials provided with the distribution. + - Neither the name of ARM nor the names of its contributors may be used + to endorse or promote products derived from this software without + specific prior written permission. + * + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE + LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + POSSIBILITY OF SUCH DAMAGE. + ---------------------------------------------------------------------------*/ + + +#if defined ( __ICCARM__ ) + #pragma system_include /* treat file as system include file for MISRA check */ +#elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) + #pragma clang system_header /* treat file as system include file */ +#endif + +#ifndef __CORE_CM0_H_GENERIC +#define __CORE_CM0_H_GENERIC + +#include + +#ifdef __cplusplus +extern "C" { +#endif + +/** + \page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions + CMSIS violates the following MISRA-C:2004 rules: + + \li Required Rule 8.5, object/function definition in header file.
+ Function definitions in header files are used to allow 'inlining'. + + \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.
+ Unions are used for effective representation of core registers. + + \li Advisory Rule 19.7, Function-like macro defined.
+ Function-like macros are used to allow more efficient code. + */ + + +/******************************************************************************* + * CMSIS definitions + ******************************************************************************/ +/** + \ingroup Cortex_M0 + @{ + */ + +/* CMSIS CM0 definitions */ +#define __CM0_CMSIS_VERSION_MAIN (0x04U) /*!< [31:16] CMSIS HAL main version */ +#define __CM0_CMSIS_VERSION_SUB (0x1EU) /*!< [15:0] CMSIS HAL sub version */ +#define __CM0_CMSIS_VERSION ((__CM0_CMSIS_VERSION_MAIN << 16U) | \ + __CM0_CMSIS_VERSION_SUB ) /*!< CMSIS HAL version number */ + +#define __CORTEX_M (0x00U) /*!< Cortex-M Core */ + + +#if defined ( __CC_ARM ) +#define __ASM __asm /*!< asm keyword for ARM Compiler */ +#define __INLINE __inline /*!< inline keyword for ARM Compiler */ +#define __STATIC_INLINE static __inline + +#elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) +#define __ASM __asm /*!< asm keyword for ARM Compiler */ +#define __INLINE __inline /*!< inline keyword for ARM Compiler */ +#define __STATIC_INLINE static __inline + +#elif defined ( __GNUC__ ) +#define __ASM __asm /*!< asm keyword for GNU Compiler */ +#define __INLINE inline /*!< inline keyword for GNU Compiler */ +#define __STATIC_INLINE static inline + +#elif defined ( __ICCARM__ ) +#define __ASM __asm /*!< asm keyword for IAR Compiler */ +#define __INLINE inline /*!< inline keyword for IAR Compiler. Only available in High optimization mode! */ +#define __STATIC_INLINE static inline + +#elif defined ( __TMS470__ ) +#define __ASM __asm /*!< asm keyword for TI CCS Compiler */ +#define __STATIC_INLINE static inline + +#elif defined ( __TASKING__ ) +#define __ASM __asm /*!< asm keyword for TASKING Compiler */ +#define __INLINE inline /*!< inline keyword for TASKING Compiler */ +#define __STATIC_INLINE static inline + +#elif defined ( __CSMC__ ) +#define __packed +#define __ASM _asm /*!< asm keyword for COSMIC Compiler */ +#define __INLINE inline /*!< inline keyword for COSMIC Compiler. Use -pc99 on compile line */ +#define __STATIC_INLINE static inline + +#else +#error Unknown compiler +#endif + +/** __FPU_USED indicates whether an FPU is used or not. + This core does not support an FPU at all +*/ +#define __FPU_USED 0U + +#if defined ( __CC_ARM ) +#if defined __TARGET_FPU_VFP +#error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" +#endif + +#elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) +#if defined __ARM_PCS_VFP +#error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" +#endif + +#elif defined ( __GNUC__ ) +#if defined (__VFP_FP__) && !defined(__SOFTFP__) +#error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" +#endif + +#elif defined ( __ICCARM__ ) +#if defined __ARMVFP__ +#error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" +#endif + +#elif defined ( __TMS470__ ) +#if defined __TI_VFP_SUPPORT__ +#error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" +#endif + +#elif defined ( __TASKING__ ) +#if defined __FPU_VFP__ +#error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" +#endif + +#elif defined ( __CSMC__ ) +#if ( __CSMC__ & 0x400U) +#error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" +#endif + +#endif + +#include "core_cmInstr.h" /* Core Instruction Access */ +#include "core_cmFunc.h" /* Core Function Access */ + +#ifdef __cplusplus +} +#endif + +#endif /* __CORE_CM0_H_GENERIC */ + +#ifndef __CMSIS_GENERIC + +#ifndef __CORE_CM0_H_DEPENDANT +#define __CORE_CM0_H_DEPENDANT + +#ifdef __cplusplus +extern "C" { +#endif + +/* check device defines and use defaults */ +#if defined __CHECK_DEVICE_DEFINES +#ifndef __CM0_REV +#define __CM0_REV 0x0000U +#warning "__CM0_REV not defined in device header file; using default!" +#endif + +#ifndef __NVIC_PRIO_BITS +#define __NVIC_PRIO_BITS 2U +#warning "__NVIC_PRIO_BITS not defined in device header file; using default!" +#endif + +#ifndef __Vendor_SysTickConfig +#define __Vendor_SysTickConfig 0U +#warning "__Vendor_SysTickConfig not defined in device header file; using default!" +#endif +#endif + +/* IO definitions (access restrictions to peripheral registers) */ +/** + \defgroup CMSIS_glob_defs CMSIS Global Defines + + IO Type Qualifiers are used + \li to specify the access to peripheral variables. + \li for automatic generation of peripheral register debug information. +*/ +#ifdef __cplusplus +#define __I volatile /*!< Defines 'read only' permissions */ +#else +#define __I volatile const /*!< Defines 'read only' permissions */ +#endif +#define __O volatile /*!< Defines 'write only' permissions */ +#define __IO volatile /*!< Defines 'read / write' permissions */ + +/* following defines should be used for structure members */ +#define __IM volatile const /*! Defines 'read only' structure member permissions */ +#define __OM volatile /*! Defines 'write only' structure member permissions */ +#define __IOM volatile /*! Defines 'read / write' structure member permissions */ + +/*@} end of group Cortex_M0 */ + + + +/******************************************************************************* + * Register Abstraction + Core Register contain: + - Core Register + - Core NVIC Register + - Core SCB Register + - Core SysTick Register + ******************************************************************************/ +/** + \defgroup CMSIS_core_register Defines and Type Definitions + \brief Type definitions and defines for Cortex-M processor based devices. +*/ + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_CORE Status and Control Registers + \brief Core Register type definitions. + @{ + */ + +/** + \brief Union type to access the Application Program Status Register (APSR). + */ +typedef union +{ + struct + { + uint32_t _reserved0: 28; /*!< bit: 0..27 Reserved */ + uint32_t V: 1; /*!< bit: 28 Overflow condition code flag */ + uint32_t C: 1; /*!< bit: 29 Carry condition code flag */ + uint32_t Z: 1; /*!< bit: 30 Zero condition code flag */ + uint32_t N: 1; /*!< bit: 31 Negative condition code flag */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} APSR_Type; + +/* APSR Register Definitions */ +#define APSR_N_Pos 31U /*!< APSR: N Position */ +#define APSR_N_Msk (1UL << APSR_N_Pos) /*!< APSR: N Mask */ + +#define APSR_Z_Pos 30U /*!< APSR: Z Position */ +#define APSR_Z_Msk (1UL << APSR_Z_Pos) /*!< APSR: Z Mask */ + +#define APSR_C_Pos 29U /*!< APSR: C Position */ +#define APSR_C_Msk (1UL << APSR_C_Pos) /*!< APSR: C Mask */ + +#define APSR_V_Pos 28U /*!< APSR: V Position */ +#define APSR_V_Msk (1UL << APSR_V_Pos) /*!< APSR: V Mask */ + + +/** + \brief Union type to access the Interrupt Program Status Register (IPSR). + */ +typedef union +{ + struct + { + uint32_t ISR: 9; /*!< bit: 0.. 8 Exception number */ + uint32_t _reserved0: 23; /*!< bit: 9..31 Reserved */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} IPSR_Type; + +/* IPSR Register Definitions */ +#define IPSR_ISR_Pos 0U /*!< IPSR: ISR Position */ +#define IPSR_ISR_Msk (0x1FFUL /*<< IPSR_ISR_Pos*/) /*!< IPSR: ISR Mask */ + + +/** + \brief Union type to access the Special-Purpose Program Status Registers (xPSR). + */ +typedef union +{ + struct + { + uint32_t ISR: 9; /*!< bit: 0.. 8 Exception number */ + uint32_t _reserved0: 15; /*!< bit: 9..23 Reserved */ + uint32_t T: 1; /*!< bit: 24 Thumb bit (read 0) */ + uint32_t _reserved1: 3; /*!< bit: 25..27 Reserved */ + uint32_t V: 1; /*!< bit: 28 Overflow condition code flag */ + uint32_t C: 1; /*!< bit: 29 Carry condition code flag */ + uint32_t Z: 1; /*!< bit: 30 Zero condition code flag */ + uint32_t N: 1; /*!< bit: 31 Negative condition code flag */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} xPSR_Type; + +/* xPSR Register Definitions */ +#define xPSR_N_Pos 31U /*!< xPSR: N Position */ +#define xPSR_N_Msk (1UL << xPSR_N_Pos) /*!< xPSR: N Mask */ + +#define xPSR_Z_Pos 30U /*!< xPSR: Z Position */ +#define xPSR_Z_Msk (1UL << xPSR_Z_Pos) /*!< xPSR: Z Mask */ + +#define xPSR_C_Pos 29U /*!< xPSR: C Position */ +#define xPSR_C_Msk (1UL << xPSR_C_Pos) /*!< xPSR: C Mask */ + +#define xPSR_V_Pos 28U /*!< xPSR: V Position */ +#define xPSR_V_Msk (1UL << xPSR_V_Pos) /*!< xPSR: V Mask */ + +#define xPSR_T_Pos 24U /*!< xPSR: T Position */ +#define xPSR_T_Msk (1UL << xPSR_T_Pos) /*!< xPSR: T Mask */ + +#define xPSR_ISR_Pos 0U /*!< xPSR: ISR Position */ +#define xPSR_ISR_Msk (0x1FFUL /*<< xPSR_ISR_Pos*/) /*!< xPSR: ISR Mask */ + + +/** + \brief Union type to access the Control Registers (CONTROL). + */ +typedef union +{ + struct + { + uint32_t _reserved0: 1; /*!< bit: 0 Reserved */ + uint32_t SPSEL: 1; /*!< bit: 1 Stack to be used */ + uint32_t _reserved1: 30; /*!< bit: 2..31 Reserved */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} CONTROL_Type; + +/* CONTROL Register Definitions */ +#define CONTROL_SPSEL_Pos 1U /*!< CONTROL: SPSEL Position */ +#define CONTROL_SPSEL_Msk (1UL << CONTROL_SPSEL_Pos) /*!< CONTROL: SPSEL Mask */ + +/*@} end of group CMSIS_CORE */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC) + \brief Type definitions for the NVIC Registers + @{ + */ + +/** + \brief Structure type to access the Nested Vectored Interrupt Controller (NVIC). + */ +typedef struct +{ + __IOM uint32_t ISER[1U]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */ + uint32_t RESERVED0[31U]; + __IOM uint32_t ICER[1U]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */ + uint32_t RSERVED1[31U]; + __IOM uint32_t ISPR[1U]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */ + uint32_t RESERVED2[31U]; + __IOM uint32_t ICPR[1U]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register */ + uint32_t RESERVED3[31U]; + uint32_t RESERVED4[64U]; + __IOM uint32_t IP[8U]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register */ +} NVIC_Type; + +/*@} end of group CMSIS_NVIC */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SCB System Control Block (SCB) + \brief Type definitions for the System Control Block Registers + @{ + */ + +/** + \brief Structure type to access the System Control Block (SCB). + */ +typedef struct +{ + __IM uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */ + __IOM uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Register */ + uint32_t RESERVED0; + __IOM uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register */ + __IOM uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */ + __IOM uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */ + uint32_t RESERVED1; + __IOM uint32_t SHP[2U]; /*!< Offset: 0x01C (R/W) System Handlers Priority Registers. [0] is RESERVED */ + __IOM uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State Register */ +} SCB_Type; + +/* SCB CPUID Register Definitions */ +#define SCB_CPUID_IMPLEMENTER_Pos 24U /*!< SCB CPUID: IMPLEMENTER Position */ +#define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */ + +#define SCB_CPUID_VARIANT_Pos 20U /*!< SCB CPUID: VARIANT Position */ +#define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */ + +#define SCB_CPUID_ARCHITECTURE_Pos 16U /*!< SCB CPUID: ARCHITECTURE Position */ +#define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB CPUID: ARCHITECTURE Mask */ + +#define SCB_CPUID_PARTNO_Pos 4U /*!< SCB CPUID: PARTNO Position */ +#define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */ + +#define SCB_CPUID_REVISION_Pos 0U /*!< SCB CPUID: REVISION Position */ +#define SCB_CPUID_REVISION_Msk (0xFUL /*<< SCB_CPUID_REVISION_Pos*/) /*!< SCB CPUID: REVISION Mask */ + +/* SCB Interrupt Control State Register Definitions */ +#define SCB_ICSR_NMIPENDSET_Pos 31U /*!< SCB ICSR: NMIPENDSET Position */ +#define SCB_ICSR_NMIPENDSET_Msk (1UL << SCB_ICSR_NMIPENDSET_Pos) /*!< SCB ICSR: NMIPENDSET Mask */ + +#define SCB_ICSR_PENDSVSET_Pos 28U /*!< SCB ICSR: PENDSVSET Position */ +#define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */ + +#define SCB_ICSR_PENDSVCLR_Pos 27U /*!< SCB ICSR: PENDSVCLR Position */ +#define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */ + +#define SCB_ICSR_PENDSTSET_Pos 26U /*!< SCB ICSR: PENDSTSET Position */ +#define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */ + +#define SCB_ICSR_PENDSTCLR_Pos 25U /*!< SCB ICSR: PENDSTCLR Position */ +#define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */ + +#define SCB_ICSR_ISRPREEMPT_Pos 23U /*!< SCB ICSR: ISRPREEMPT Position */ +#define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */ + +#define SCB_ICSR_ISRPENDING_Pos 22U /*!< SCB ICSR: ISRPENDING Position */ +#define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */ + +#define SCB_ICSR_VECTPENDING_Pos 12U /*!< SCB ICSR: VECTPENDING Position */ +#define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */ + +#define SCB_ICSR_VECTACTIVE_Pos 0U /*!< SCB ICSR: VECTACTIVE Position */ +#define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/) /*!< SCB ICSR: VECTACTIVE Mask */ + +/* SCB Application Interrupt and Reset Control Register Definitions */ +#define SCB_AIRCR_VECTKEY_Pos 16U /*!< SCB AIRCR: VECTKEY Position */ +#define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */ + +#define SCB_AIRCR_VECTKEYSTAT_Pos 16U /*!< SCB AIRCR: VECTKEYSTAT Position */ +#define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */ + +#define SCB_AIRCR_ENDIANESS_Pos 15U /*!< SCB AIRCR: ENDIANESS Position */ +#define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /*!< SCB AIRCR: ENDIANESS Mask */ + +#define SCB_AIRCR_SYSRESETREQ_Pos 2U /*!< SCB AIRCR: SYSRESETREQ Position */ +#define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */ + +#define SCB_AIRCR_VECTCLRACTIVE_Pos 1U /*!< SCB AIRCR: VECTCLRACTIVE Position */ +#define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */ + +/* SCB System Control Register Definitions */ +#define SCB_SCR_SEVONPEND_Pos 4U /*!< SCB SCR: SEVONPEND Position */ +#define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */ + +#define SCB_SCR_SLEEPDEEP_Pos 2U /*!< SCB SCR: SLEEPDEEP Position */ +#define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */ + +#define SCB_SCR_SLEEPONEXIT_Pos 1U /*!< SCB SCR: SLEEPONEXIT Position */ +#define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */ + +/* SCB Configuration Control Register Definitions */ +#define SCB_CCR_STKALIGN_Pos 9U /*!< SCB CCR: STKALIGN Position */ +#define SCB_CCR_STKALIGN_Msk (1UL << SCB_CCR_STKALIGN_Pos) /*!< SCB CCR: STKALIGN Mask */ + +#define SCB_CCR_UNALIGN_TRP_Pos 3U /*!< SCB CCR: UNALIGN_TRP Position */ +#define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */ + +/* SCB System Handler Control and State Register Definitions */ +#define SCB_SHCSR_SVCALLPENDED_Pos 15U /*!< SCB SHCSR: SVCALLPENDED Position */ +#define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */ + +/*@} end of group CMSIS_SCB */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SysTick System Tick Timer (SysTick) + \brief Type definitions for the System Timer Registers. + @{ + */ + +/** + \brief Structure type to access the System Timer (SysTick). + */ +typedef struct +{ + __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */ + __IOM uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */ + __IOM uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register */ + __IM uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */ +} SysTick_Type; + +/* SysTick Control / Status Register Definitions */ +#define SysTick_CTRL_COUNTFLAG_Pos 16U /*!< SysTick CTRL: COUNTFLAG Position */ +#define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */ + +#define SysTick_CTRL_CLKSOURCE_Pos 2U /*!< SysTick CTRL: CLKSOURCE Position */ +#define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */ + +#define SysTick_CTRL_TICKINT_Pos 1U /*!< SysTick CTRL: TICKINT Position */ +#define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */ + +#define SysTick_CTRL_ENABLE_Pos 0U /*!< SysTick CTRL: ENABLE Position */ +#define SysTick_CTRL_ENABLE_Msk (1UL /*<< SysTick_CTRL_ENABLE_Pos*/) /*!< SysTick CTRL: ENABLE Mask */ + +/* SysTick Reload Register Definitions */ +#define SysTick_LOAD_RELOAD_Pos 0U /*!< SysTick LOAD: RELOAD Position */ +#define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/) /*!< SysTick LOAD: RELOAD Mask */ + +/* SysTick Current Register Definitions */ +#define SysTick_VAL_CURRENT_Pos 0U /*!< SysTick VAL: CURRENT Position */ +#define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/) /*!< SysTick VAL: CURRENT Mask */ + +/* SysTick Calibration Register Definitions */ +#define SysTick_CALIB_NOREF_Pos 31U /*!< SysTick CALIB: NOREF Position */ +#define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */ + +#define SysTick_CALIB_SKEW_Pos 30U /*!< SysTick CALIB: SKEW Position */ +#define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */ + +#define SysTick_CALIB_TENMS_Pos 0U /*!< SysTick CALIB: TENMS Position */ +#define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/) /*!< SysTick CALIB: TENMS Mask */ + +/*@} end of group CMSIS_SysTick */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_CoreDebug Core Debug Registers (CoreDebug) + \brief Cortex-M0 Core Debug Registers (DCB registers, SHCSR, and DFSR) are only accessible over DAP and not via processor. + Therefore they are not covered by the Cortex-M0 header file. + @{ + */ +/*@} end of group CMSIS_CoreDebug */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_core_bitfield Core register bit field macros + \brief Macros for use with bit field definitions (xxx_Pos, xxx_Msk). + @{ + */ + +/** + \brief Mask and shift a bit field value for use in a register bit range. + \param[in] field Name of the register bit field. + \param[in] value Value of the bit field. + \return Masked and shifted value. +*/ +#define _VAL2FLD(field, value) ((value << field ## _Pos) & field ## _Msk) + +/** + \brief Mask and shift a register value to extract a bit filed value. + \param[in] field Name of the register bit field. + \param[in] value Value of register. + \return Masked and shifted bit field value. +*/ +#define _FLD2VAL(field, value) ((value & field ## _Msk) >> field ## _Pos) + +/*@} end of group CMSIS_core_bitfield */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_core_base Core Definitions + \brief Definitions for base addresses, unions, and structures. + @{ + */ + +/* Memory mapping of Cortex-M0 Hardware */ +#define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */ +#define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */ +#define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */ +#define SCB_BASE (SCS_BASE + 0x0D00UL) /*!< System Control Block Base Address */ + +#define SCB ((SCB_Type *) SCB_BASE ) /*!< SCB configuration struct */ +#define SysTick ((SysTick_Type *) SysTick_BASE ) /*!< SysTick configuration struct */ +#define NVIC ((NVIC_Type *) NVIC_BASE ) /*!< NVIC configuration struct */ + + +/*@} */ + + + +/******************************************************************************* + * Hardware Abstraction Layer + Core Function Interface contains: + - Core NVIC Functions + - Core SysTick Functions + - Core Register Access Functions + ******************************************************************************/ +/** + \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference +*/ + + + +/* ########################## NVIC functions #################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_NVICFunctions NVIC Functions + \brief Functions that manage interrupts and exceptions via the NVIC. + @{ + */ + +/* Interrupt Priorities are WORD accessible only under ARMv6M */ +/* The following MACROS handle generation of the register offset and byte masks */ +#define _BIT_SHIFT(IRQn) ( ((((uint32_t)(int32_t)(IRQn)) ) & 0x03UL) * 8UL) +#define _SHP_IDX(IRQn) ( (((((uint32_t)(int32_t)(IRQn)) & 0x0FUL)-8UL) >> 2UL) ) +#define _IP_IDX(IRQn) ( (((uint32_t)(int32_t)(IRQn)) >> 2UL) ) + + +/** + \brief Enable External Interrupt + \details Enables a device-specific interrupt in the NVIC interrupt controller. + \param [in] IRQn External interrupt number. Value cannot be negative. + */ +__STATIC_INLINE void NVIC_EnableIRQ(IRQn_Type IRQn) +{ + NVIC->ISER[0U] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL)); +} + + +/** + \brief Disable External Interrupt + \details Disables a device-specific interrupt in the NVIC interrupt controller. + \param [in] IRQn External interrupt number. Value cannot be negative. + */ +__STATIC_INLINE void NVIC_DisableIRQ(IRQn_Type IRQn) +{ + NVIC->ICER[0U] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL)); +} + + +/** + \brief Get Pending Interrupt + \details Reads the pending register in the NVIC and returns the pending bit for the specified interrupt. + \param [in] IRQn Interrupt number. + \return 0 Interrupt status is not pending. + \return 1 Interrupt status is pending. + */ +__STATIC_INLINE uint32_t NVIC_GetPendingIRQ(IRQn_Type IRQn) +{ + return ((uint32_t)(((NVIC->ISPR[0U] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); +} + + +/** + \brief Set Pending Interrupt + \details Sets the pending bit of an external interrupt. + \param [in] IRQn Interrupt number. Value cannot be negative. + */ +__STATIC_INLINE void NVIC_SetPendingIRQ(IRQn_Type IRQn) +{ + NVIC->ISPR[0U] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL)); +} + + +/** + \brief Clear Pending Interrupt + \details Clears the pending bit of an external interrupt. + \param [in] IRQn External interrupt number. Value cannot be negative. + */ +__STATIC_INLINE void NVIC_ClearPendingIRQ(IRQn_Type IRQn) +{ + NVIC->ICPR[0U] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL)); +} + + +/** + \brief Set Interrupt Priority + \details Sets the priority of an interrupt. + \note The priority cannot be set for every core interrupt. + \param [in] IRQn Interrupt number. + \param [in] priority Priority to set. + */ +__STATIC_INLINE void NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority) +{ + if ((int32_t)(IRQn) < 0) + { + SCB->SHP[_SHP_IDX(IRQn)] = ((uint32_t)(SCB->SHP[_SHP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) | + (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn))); + } + else + { + NVIC->IP[_IP_IDX(IRQn)] = ((uint32_t)(NVIC->IP[_IP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) | + (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn))); + } +} + + +/** + \brief Get Interrupt Priority + \details Reads the priority of an interrupt. + The interrupt number can be positive to specify an external (device specific) interrupt, + or negative to specify an internal (core) interrupt. + \param [in] IRQn Interrupt number. + \return Interrupt Priority. + Value is aligned automatically to the implemented priority bits of the microcontroller. + */ +__STATIC_INLINE uint32_t NVIC_GetPriority(IRQn_Type IRQn) +{ + + if ((int32_t)(IRQn) < 0) + { + return ((uint32_t)(((SCB->SHP[_SHP_IDX(IRQn)] >> _BIT_SHIFT(IRQn)) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS))); + } + else + { + return ((uint32_t)(((NVIC->IP[ _IP_IDX(IRQn)] >> _BIT_SHIFT(IRQn)) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS))); + } +} + + +/** + \brief System Reset + \details Initiates a system reset request to reset the MCU. + */ +__STATIC_INLINE void NVIC_SystemReset(void) +{ + __DSB(); /* Ensure all outstanding memory accesses included + buffered write are completed before reset */ + SCB->AIRCR = ((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | + SCB_AIRCR_SYSRESETREQ_Msk); + __DSB(); /* Ensure completion of memory access */ + + for (;;) /* wait until reset */ + { + __NOP(); + } +} + +/*@} end of CMSIS_Core_NVICFunctions */ + + + +/* ################################## SysTick function ############################################ */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_SysTickFunctions SysTick Functions + \brief Functions that configure the System. + @{ + */ + +#if (__Vendor_SysTickConfig == 0U) + +/** + \brief System Tick Configuration + \details Initializes the System Timer and its interrupt, and starts the System Tick Timer. + Counter is in free running mode to generate periodic interrupts. + \param [in] ticks Number of ticks between two interrupts. + \return 0 Function succeeded. + \return 1 Function failed. + \note When the variable __Vendor_SysTickConfig is set to 1, then the + function SysTick_Config is not included. In this case, the file device.h + must contain a vendor-specific implementation of this function. + */ +__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks) +{ + if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk) + { + return (1UL); /* Reload value impossible */ + } + + SysTick->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */ + NVIC_SetPriority(SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */ + SysTick->VAL = 0UL; /* Load the SysTick Counter Value */ + SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk | + SysTick_CTRL_TICKINT_Msk | + SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */ + return (0UL); /* Function successful */ +} + +#endif + +/*@} end of CMSIS_Core_SysTickFunctions */ + + + + +#ifdef __cplusplus +} +#endif + +#endif /* __CORE_CM0_H_DEPENDANT */ + +#endif /* __CMSIS_GENERIC */ diff --git a/bsp/nuvoton/libraries/ma35/CMSIS/Include/core_cm0plus.h b/bsp/nuvoton/libraries/ma35/CMSIS/Include/core_cm0plus.h new file mode 100644 index 0000000000..aa0ca4ae65 --- /dev/null +++ b/bsp/nuvoton/libraries/ma35/CMSIS/Include/core_cm0plus.h @@ -0,0 +1,914 @@ +/**************************************************************************//** + * @file core_cm0plus.h + * @brief CMSIS Cortex-M0+ Core Peripheral Access Layer Header File + * @version V4.30 + * @date 20. October 2015 + ******************************************************************************/ +/* Copyright (c) 2009 - 2015 ARM LIMITED + + All rights reserved. + Redistribution and use in source and binary forms, with or without + modification, are permitted provided that the following conditions are met: + - Redistributions of source code must retain the above copyright + notice, this list of conditions and the following disclaimer. + - Redistributions in binary form must reproduce the above copyright + notice, this list of conditions and the following disclaimer in the + documentation and/or other materials provided with the distribution. + - Neither the name of ARM nor the names of its contributors may be used + to endorse or promote products derived from this software without + specific prior written permission. + * + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE + LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + POSSIBILITY OF SUCH DAMAGE. + ---------------------------------------------------------------------------*/ + + +#if defined ( __ICCARM__ ) + #pragma system_include /* treat file as system include file for MISRA check */ +#elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) + #pragma clang system_header /* treat file as system include file */ +#endif + +#ifndef __CORE_CM0PLUS_H_GENERIC +#define __CORE_CM0PLUS_H_GENERIC + +#include + +#ifdef __cplusplus +extern "C" { +#endif + +/** + \page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions + CMSIS violates the following MISRA-C:2004 rules: + + \li Required Rule 8.5, object/function definition in header file.
+ Function definitions in header files are used to allow 'inlining'. + + \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.
+ Unions are used for effective representation of core registers. + + \li Advisory Rule 19.7, Function-like macro defined.
+ Function-like macros are used to allow more efficient code. + */ + + +/******************************************************************************* + * CMSIS definitions + ******************************************************************************/ +/** + \ingroup Cortex-M0+ + @{ + */ + +/* CMSIS CM0+ definitions */ +#define __CM0PLUS_CMSIS_VERSION_MAIN (0x04U) /*!< [31:16] CMSIS HAL main version */ +#define __CM0PLUS_CMSIS_VERSION_SUB (0x1EU) /*!< [15:0] CMSIS HAL sub version */ +#define __CM0PLUS_CMSIS_VERSION ((__CM0PLUS_CMSIS_VERSION_MAIN << 16U) | \ + __CM0PLUS_CMSIS_VERSION_SUB ) /*!< CMSIS HAL version number */ + +#define __CORTEX_M (0x00U) /*!< Cortex-M Core */ + + +#if defined ( __CC_ARM ) +#define __ASM __asm /*!< asm keyword for ARM Compiler */ +#define __INLINE __inline /*!< inline keyword for ARM Compiler */ +#define __STATIC_INLINE static __inline + +#elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) +#define __ASM __asm /*!< asm keyword for ARM Compiler */ +#define __INLINE __inline /*!< inline keyword for ARM Compiler */ +#define __STATIC_INLINE static __inline + +#elif defined ( __GNUC__ ) +#define __ASM __asm /*!< asm keyword for GNU Compiler */ +#define __INLINE inline /*!< inline keyword for GNU Compiler */ +#define __STATIC_INLINE static inline + +#elif defined ( __ICCARM__ ) +#define __ASM __asm /*!< asm keyword for IAR Compiler */ +#define __INLINE inline /*!< inline keyword for IAR Compiler. Only available in High optimization mode! */ +#define __STATIC_INLINE static inline + +#elif defined ( __TMS470__ ) +#define __ASM __asm /*!< asm keyword for TI CCS Compiler */ +#define __STATIC_INLINE static inline + +#elif defined ( __TASKING__ ) +#define __ASM __asm /*!< asm keyword for TASKING Compiler */ +#define __INLINE inline /*!< inline keyword for TASKING Compiler */ +#define __STATIC_INLINE static inline + +#elif defined ( __CSMC__ ) +#define __packed +#define __ASM _asm /*!< asm keyword for COSMIC Compiler */ +#define __INLINE inline /*!< inline keyword for COSMIC Compiler. Use -pc99 on compile line */ +#define __STATIC_INLINE static inline + +#else +#error Unknown compiler +#endif + +/** __FPU_USED indicates whether an FPU is used or not. + This core does not support an FPU at all +*/ +#define __FPU_USED 0U + +#if defined ( __CC_ARM ) +#if defined __TARGET_FPU_VFP +#error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" +#endif + +#elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) +#if defined __ARM_PCS_VFP +#error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" +#endif + +#elif defined ( __GNUC__ ) +#if defined (__VFP_FP__) && !defined(__SOFTFP__) +#error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" +#endif + +#elif defined ( __ICCARM__ ) +#if defined __ARMVFP__ +#error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" +#endif + +#elif defined ( __TMS470__ ) +#if defined __TI_VFP_SUPPORT__ +#error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" +#endif + +#elif defined ( __TASKING__ ) +#if defined __FPU_VFP__ +#error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" +#endif + +#elif defined ( __CSMC__ ) +#if ( __CSMC__ & 0x400U) +#error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" +#endif + +#endif + +#include "core_cmInstr.h" /* Core Instruction Access */ +#include "core_cmFunc.h" /* Core Function Access */ + +#ifdef __cplusplus +} +#endif + +#endif /* __CORE_CM0PLUS_H_GENERIC */ + +#ifndef __CMSIS_GENERIC + +#ifndef __CORE_CM0PLUS_H_DEPENDANT +#define __CORE_CM0PLUS_H_DEPENDANT + +#ifdef __cplusplus +extern "C" { +#endif + +/* check device defines and use defaults */ +#if defined __CHECK_DEVICE_DEFINES +#ifndef __CM0PLUS_REV +#define __CM0PLUS_REV 0x0000U +#warning "__CM0PLUS_REV not defined in device header file; using default!" +#endif + +#ifndef __MPU_PRESENT +#define __MPU_PRESENT 0U +#warning "__MPU_PRESENT not defined in device header file; using default!" +#endif + +#ifndef __VTOR_PRESENT +#define __VTOR_PRESENT 0U +#warning "__VTOR_PRESENT not defined in device header file; using default!" +#endif + +#ifndef __NVIC_PRIO_BITS +#define __NVIC_PRIO_BITS 2U +#warning "__NVIC_PRIO_BITS not defined in device header file; using default!" +#endif + +#ifndef __Vendor_SysTickConfig +#define __Vendor_SysTickConfig 0U +#warning "__Vendor_SysTickConfig not defined in device header file; using default!" +#endif +#endif + +/* IO definitions (access restrictions to peripheral registers) */ +/** + \defgroup CMSIS_glob_defs CMSIS Global Defines + + IO Type Qualifiers are used + \li to specify the access to peripheral variables. + \li for automatic generation of peripheral register debug information. +*/ +#ifdef __cplusplus +#define __I volatile /*!< Defines 'read only' permissions */ +#else +#define __I volatile const /*!< Defines 'read only' permissions */ +#endif +#define __O volatile /*!< Defines 'write only' permissions */ +#define __IO volatile /*!< Defines 'read / write' permissions */ + +/* following defines should be used for structure members */ +#define __IM volatile const /*! Defines 'read only' structure member permissions */ +#define __OM volatile /*! Defines 'write only' structure member permissions */ +#define __IOM volatile /*! Defines 'read / write' structure member permissions */ + +/*@} end of group Cortex-M0+ */ + + + +/******************************************************************************* + * Register Abstraction + Core Register contain: + - Core Register + - Core NVIC Register + - Core SCB Register + - Core SysTick Register + - Core MPU Register + ******************************************************************************/ +/** + \defgroup CMSIS_core_register Defines and Type Definitions + \brief Type definitions and defines for Cortex-M processor based devices. +*/ + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_CORE Status and Control Registers + \brief Core Register type definitions. + @{ + */ + +/** + \brief Union type to access the Application Program Status Register (APSR). + */ +typedef union +{ + struct + { + uint32_t _reserved0: 28; /*!< bit: 0..27 Reserved */ + uint32_t V: 1; /*!< bit: 28 Overflow condition code flag */ + uint32_t C: 1; /*!< bit: 29 Carry condition code flag */ + uint32_t Z: 1; /*!< bit: 30 Zero condition code flag */ + uint32_t N: 1; /*!< bit: 31 Negative condition code flag */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} APSR_Type; + +/* APSR Register Definitions */ +#define APSR_N_Pos 31U /*!< APSR: N Position */ +#define APSR_N_Msk (1UL << APSR_N_Pos) /*!< APSR: N Mask */ + +#define APSR_Z_Pos 30U /*!< APSR: Z Position */ +#define APSR_Z_Msk (1UL << APSR_Z_Pos) /*!< APSR: Z Mask */ + +#define APSR_C_Pos 29U /*!< APSR: C Position */ +#define APSR_C_Msk (1UL << APSR_C_Pos) /*!< APSR: C Mask */ + +#define APSR_V_Pos 28U /*!< APSR: V Position */ +#define APSR_V_Msk (1UL << APSR_V_Pos) /*!< APSR: V Mask */ + + +/** + \brief Union type to access the Interrupt Program Status Register (IPSR). + */ +typedef union +{ + struct + { + uint32_t ISR: 9; /*!< bit: 0.. 8 Exception number */ + uint32_t _reserved0: 23; /*!< bit: 9..31 Reserved */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} IPSR_Type; + +/* IPSR Register Definitions */ +#define IPSR_ISR_Pos 0U /*!< IPSR: ISR Position */ +#define IPSR_ISR_Msk (0x1FFUL /*<< IPSR_ISR_Pos*/) /*!< IPSR: ISR Mask */ + + +/** + \brief Union type to access the Special-Purpose Program Status Registers (xPSR). + */ +typedef union +{ + struct + { + uint32_t ISR: 9; /*!< bit: 0.. 8 Exception number */ + uint32_t _reserved0: 15; /*!< bit: 9..23 Reserved */ + uint32_t T: 1; /*!< bit: 24 Thumb bit (read 0) */ + uint32_t _reserved1: 3; /*!< bit: 25..27 Reserved */ + uint32_t V: 1; /*!< bit: 28 Overflow condition code flag */ + uint32_t C: 1; /*!< bit: 29 Carry condition code flag */ + uint32_t Z: 1; /*!< bit: 30 Zero condition code flag */ + uint32_t N: 1; /*!< bit: 31 Negative condition code flag */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} xPSR_Type; + +/* xPSR Register Definitions */ +#define xPSR_N_Pos 31U /*!< xPSR: N Position */ +#define xPSR_N_Msk (1UL << xPSR_N_Pos) /*!< xPSR: N Mask */ + +#define xPSR_Z_Pos 30U /*!< xPSR: Z Position */ +#define xPSR_Z_Msk (1UL << xPSR_Z_Pos) /*!< xPSR: Z Mask */ + +#define xPSR_C_Pos 29U /*!< xPSR: C Position */ +#define xPSR_C_Msk (1UL << xPSR_C_Pos) /*!< xPSR: C Mask */ + +#define xPSR_V_Pos 28U /*!< xPSR: V Position */ +#define xPSR_V_Msk (1UL << xPSR_V_Pos) /*!< xPSR: V Mask */ + +#define xPSR_T_Pos 24U /*!< xPSR: T Position */ +#define xPSR_T_Msk (1UL << xPSR_T_Pos) /*!< xPSR: T Mask */ + +#define xPSR_ISR_Pos 0U /*!< xPSR: ISR Position */ +#define xPSR_ISR_Msk (0x1FFUL /*<< xPSR_ISR_Pos*/) /*!< xPSR: ISR Mask */ + + +/** + \brief Union type to access the Control Registers (CONTROL). + */ +typedef union +{ + struct + { + uint32_t nPRIV: 1; /*!< bit: 0 Execution privilege in Thread mode */ + uint32_t SPSEL: 1; /*!< bit: 1 Stack to be used */ + uint32_t _reserved1: 30; /*!< bit: 2..31 Reserved */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} CONTROL_Type; + +/* CONTROL Register Definitions */ +#define CONTROL_SPSEL_Pos 1U /*!< CONTROL: SPSEL Position */ +#define CONTROL_SPSEL_Msk (1UL << CONTROL_SPSEL_Pos) /*!< CONTROL: SPSEL Mask */ + +#define CONTROL_nPRIV_Pos 0U /*!< CONTROL: nPRIV Position */ +#define CONTROL_nPRIV_Msk (1UL /*<< CONTROL_nPRIV_Pos*/) /*!< CONTROL: nPRIV Mask */ + +/*@} end of group CMSIS_CORE */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC) + \brief Type definitions for the NVIC Registers + @{ + */ + +/** + \brief Structure type to access the Nested Vectored Interrupt Controller (NVIC). + */ +typedef struct +{ + __IOM uint32_t ISER[1U]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */ + uint32_t RESERVED0[31U]; + __IOM uint32_t ICER[1U]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */ + uint32_t RSERVED1[31U]; + __IOM uint32_t ISPR[1U]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */ + uint32_t RESERVED2[31U]; + __IOM uint32_t ICPR[1U]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register */ + uint32_t RESERVED3[31U]; + uint32_t RESERVED4[64U]; + __IOM uint32_t IP[8U]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register */ +} NVIC_Type; + +/*@} end of group CMSIS_NVIC */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SCB System Control Block (SCB) + \brief Type definitions for the System Control Block Registers + @{ + */ + +/** + \brief Structure type to access the System Control Block (SCB). + */ +typedef struct +{ + __IM uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */ + __IOM uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Register */ +#if (__VTOR_PRESENT == 1U) + __IOM uint32_t VTOR; /*!< Offset: 0x008 (R/W) Vector Table Offset Register */ +#else + uint32_t RESERVED0; +#endif + __IOM uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register */ + __IOM uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */ + __IOM uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */ + uint32_t RESERVED1; + __IOM uint32_t SHP[2U]; /*!< Offset: 0x01C (R/W) System Handlers Priority Registers. [0] is RESERVED */ + __IOM uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State Register */ +} SCB_Type; + +/* SCB CPUID Register Definitions */ +#define SCB_CPUID_IMPLEMENTER_Pos 24U /*!< SCB CPUID: IMPLEMENTER Position */ +#define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */ + +#define SCB_CPUID_VARIANT_Pos 20U /*!< SCB CPUID: VARIANT Position */ +#define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */ + +#define SCB_CPUID_ARCHITECTURE_Pos 16U /*!< SCB CPUID: ARCHITECTURE Position */ +#define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB CPUID: ARCHITECTURE Mask */ + +#define SCB_CPUID_PARTNO_Pos 4U /*!< SCB CPUID: PARTNO Position */ +#define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */ + +#define SCB_CPUID_REVISION_Pos 0U /*!< SCB CPUID: REVISION Position */ +#define SCB_CPUID_REVISION_Msk (0xFUL /*<< SCB_CPUID_REVISION_Pos*/) /*!< SCB CPUID: REVISION Mask */ + +/* SCB Interrupt Control State Register Definitions */ +#define SCB_ICSR_NMIPENDSET_Pos 31U /*!< SCB ICSR: NMIPENDSET Position */ +#define SCB_ICSR_NMIPENDSET_Msk (1UL << SCB_ICSR_NMIPENDSET_Pos) /*!< SCB ICSR: NMIPENDSET Mask */ + +#define SCB_ICSR_PENDSVSET_Pos 28U /*!< SCB ICSR: PENDSVSET Position */ +#define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */ + +#define SCB_ICSR_PENDSVCLR_Pos 27U /*!< SCB ICSR: PENDSVCLR Position */ +#define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */ + +#define SCB_ICSR_PENDSTSET_Pos 26U /*!< SCB ICSR: PENDSTSET Position */ +#define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */ + +#define SCB_ICSR_PENDSTCLR_Pos 25U /*!< SCB ICSR: PENDSTCLR Position */ +#define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */ + +#define SCB_ICSR_ISRPREEMPT_Pos 23U /*!< SCB ICSR: ISRPREEMPT Position */ +#define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */ + +#define SCB_ICSR_ISRPENDING_Pos 22U /*!< SCB ICSR: ISRPENDING Position */ +#define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */ + +#define SCB_ICSR_VECTPENDING_Pos 12U /*!< SCB ICSR: VECTPENDING Position */ +#define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */ + +#define SCB_ICSR_VECTACTIVE_Pos 0U /*!< SCB ICSR: VECTACTIVE Position */ +#define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/) /*!< SCB ICSR: VECTACTIVE Mask */ + +#if (__VTOR_PRESENT == 1U) +/* SCB Interrupt Control State Register Definitions */ +#define SCB_VTOR_TBLOFF_Pos 8U /*!< SCB VTOR: TBLOFF Position */ +#define SCB_VTOR_TBLOFF_Msk (0xFFFFFFUL << SCB_VTOR_TBLOFF_Pos) /*!< SCB VTOR: TBLOFF Mask */ +#endif + +/* SCB Application Interrupt and Reset Control Register Definitions */ +#define SCB_AIRCR_VECTKEY_Pos 16U /*!< SCB AIRCR: VECTKEY Position */ +#define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */ + +#define SCB_AIRCR_VECTKEYSTAT_Pos 16U /*!< SCB AIRCR: VECTKEYSTAT Position */ +#define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */ + +#define SCB_AIRCR_ENDIANESS_Pos 15U /*!< SCB AIRCR: ENDIANESS Position */ +#define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /*!< SCB AIRCR: ENDIANESS Mask */ + +#define SCB_AIRCR_SYSRESETREQ_Pos 2U /*!< SCB AIRCR: SYSRESETREQ Position */ +#define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */ + +#define SCB_AIRCR_VECTCLRACTIVE_Pos 1U /*!< SCB AIRCR: VECTCLRACTIVE Position */ +#define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */ + +/* SCB System Control Register Definitions */ +#define SCB_SCR_SEVONPEND_Pos 4U /*!< SCB SCR: SEVONPEND Position */ +#define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */ + +#define SCB_SCR_SLEEPDEEP_Pos 2U /*!< SCB SCR: SLEEPDEEP Position */ +#define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */ + +#define SCB_SCR_SLEEPONEXIT_Pos 1U /*!< SCB SCR: SLEEPONEXIT Position */ +#define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */ + +/* SCB Configuration Control Register Definitions */ +#define SCB_CCR_STKALIGN_Pos 9U /*!< SCB CCR: STKALIGN Position */ +#define SCB_CCR_STKALIGN_Msk (1UL << SCB_CCR_STKALIGN_Pos) /*!< SCB CCR: STKALIGN Mask */ + +#define SCB_CCR_UNALIGN_TRP_Pos 3U /*!< SCB CCR: UNALIGN_TRP Position */ +#define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */ + +/* SCB System Handler Control and State Register Definitions */ +#define SCB_SHCSR_SVCALLPENDED_Pos 15U /*!< SCB SHCSR: SVCALLPENDED Position */ +#define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */ + +/*@} end of group CMSIS_SCB */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SysTick System Tick Timer (SysTick) + \brief Type definitions for the System Timer Registers. + @{ + */ + +/** + \brief Structure type to access the System Timer (SysTick). + */ +typedef struct +{ + __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */ + __IOM uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */ + __IOM uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register */ + __IM uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */ +} SysTick_Type; + +/* SysTick Control / Status Register Definitions */ +#define SysTick_CTRL_COUNTFLAG_Pos 16U /*!< SysTick CTRL: COUNTFLAG Position */ +#define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */ + +#define SysTick_CTRL_CLKSOURCE_Pos 2U /*!< SysTick CTRL: CLKSOURCE Position */ +#define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */ + +#define SysTick_CTRL_TICKINT_Pos 1U /*!< SysTick CTRL: TICKINT Position */ +#define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */ + +#define SysTick_CTRL_ENABLE_Pos 0U /*!< SysTick CTRL: ENABLE Position */ +#define SysTick_CTRL_ENABLE_Msk (1UL /*<< SysTick_CTRL_ENABLE_Pos*/) /*!< SysTick CTRL: ENABLE Mask */ + +/* SysTick Reload Register Definitions */ +#define SysTick_LOAD_RELOAD_Pos 0U /*!< SysTick LOAD: RELOAD Position */ +#define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/) /*!< SysTick LOAD: RELOAD Mask */ + +/* SysTick Current Register Definitions */ +#define SysTick_VAL_CURRENT_Pos 0U /*!< SysTick VAL: CURRENT Position */ +#define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/) /*!< SysTick VAL: CURRENT Mask */ + +/* SysTick Calibration Register Definitions */ +#define SysTick_CALIB_NOREF_Pos 31U /*!< SysTick CALIB: NOREF Position */ +#define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */ + +#define SysTick_CALIB_SKEW_Pos 30U /*!< SysTick CALIB: SKEW Position */ +#define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */ + +#define SysTick_CALIB_TENMS_Pos 0U /*!< SysTick CALIB: TENMS Position */ +#define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/) /*!< SysTick CALIB: TENMS Mask */ + +/*@} end of group CMSIS_SysTick */ + +#if (__MPU_PRESENT == 1U) +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_MPU Memory Protection Unit (MPU) + \brief Type definitions for the Memory Protection Unit (MPU) + @{ + */ + +/** + \brief Structure type to access the Memory Protection Unit (MPU). + */ +typedef struct +{ + __IM uint32_t TYPE; /*!< Offset: 0x000 (R/ ) MPU Type Register */ + __IOM uint32_t CTRL; /*!< Offset: 0x004 (R/W) MPU Control Register */ + __IOM uint32_t RNR; /*!< Offset: 0x008 (R/W) MPU Region RNRber Register */ + __IOM uint32_t RBAR; /*!< Offset: 0x00C (R/W) MPU Region Base Address Register */ + __IOM uint32_t RASR; /*!< Offset: 0x010 (R/W) MPU Region Attribute and Size Register */ +} MPU_Type; + +/* MPU Type Register Definitions */ +#define MPU_TYPE_IREGION_Pos 16U /*!< MPU TYPE: IREGION Position */ +#define MPU_TYPE_IREGION_Msk (0xFFUL << MPU_TYPE_IREGION_Pos) /*!< MPU TYPE: IREGION Mask */ + +#define MPU_TYPE_DREGION_Pos 8U /*!< MPU TYPE: DREGION Position */ +#define MPU_TYPE_DREGION_Msk (0xFFUL << MPU_TYPE_DREGION_Pos) /*!< MPU TYPE: DREGION Mask */ + +#define MPU_TYPE_SEPARATE_Pos 0U /*!< MPU TYPE: SEPARATE Position */ +#define MPU_TYPE_SEPARATE_Msk (1UL /*<< MPU_TYPE_SEPARATE_Pos*/) /*!< MPU TYPE: SEPARATE Mask */ + +/* MPU Control Register Definitions */ +#define MPU_CTRL_PRIVDEFENA_Pos 2U /*!< MPU CTRL: PRIVDEFENA Position */ +#define MPU_CTRL_PRIVDEFENA_Msk (1UL << MPU_CTRL_PRIVDEFENA_Pos) /*!< MPU CTRL: PRIVDEFENA Mask */ + +#define MPU_CTRL_HFNMIENA_Pos 1U /*!< MPU CTRL: HFNMIENA Position */ +#define MPU_CTRL_HFNMIENA_Msk (1UL << MPU_CTRL_HFNMIENA_Pos) /*!< MPU CTRL: HFNMIENA Mask */ + +#define MPU_CTRL_ENABLE_Pos 0U /*!< MPU CTRL: ENABLE Position */ +#define MPU_CTRL_ENABLE_Msk (1UL /*<< MPU_CTRL_ENABLE_Pos*/) /*!< MPU CTRL: ENABLE Mask */ + +/* MPU Region Number Register Definitions */ +#define MPU_RNR_REGION_Pos 0U /*!< MPU RNR: REGION Position */ +#define MPU_RNR_REGION_Msk (0xFFUL /*<< MPU_RNR_REGION_Pos*/) /*!< MPU RNR: REGION Mask */ + +/* MPU Region Base Address Register Definitions */ +#define MPU_RBAR_ADDR_Pos 8U /*!< MPU RBAR: ADDR Position */ +#define MPU_RBAR_ADDR_Msk (0xFFFFFFUL << MPU_RBAR_ADDR_Pos) /*!< MPU RBAR: ADDR Mask */ + +#define MPU_RBAR_VALID_Pos 4U /*!< MPU RBAR: VALID Position */ +#define MPU_RBAR_VALID_Msk (1UL << MPU_RBAR_VALID_Pos) /*!< MPU RBAR: VALID Mask */ + +#define MPU_RBAR_REGION_Pos 0U /*!< MPU RBAR: REGION Position */ +#define MPU_RBAR_REGION_Msk (0xFUL /*<< MPU_RBAR_REGION_Pos*/) /*!< MPU RBAR: REGION Mask */ + +/* MPU Region Attribute and Size Register Definitions */ +#define MPU_RASR_ATTRS_Pos 16U /*!< MPU RASR: MPU Region Attribute field Position */ +#define MPU_RASR_ATTRS_Msk (0xFFFFUL << MPU_RASR_ATTRS_Pos) /*!< MPU RASR: MPU Region Attribute field Mask */ + +#define MPU_RASR_XN_Pos 28U /*!< MPU RASR: ATTRS.XN Position */ +#define MPU_RASR_XN_Msk (1UL << MPU_RASR_XN_Pos) /*!< MPU RASR: ATTRS.XN Mask */ + +#define MPU_RASR_AP_Pos 24U /*!< MPU RASR: ATTRS.AP Position */ +#define MPU_RASR_AP_Msk (0x7UL << MPU_RASR_AP_Pos) /*!< MPU RASR: ATTRS.AP Mask */ + +#define MPU_RASR_TEX_Pos 19U /*!< MPU RASR: ATTRS.TEX Position */ +#define MPU_RASR_TEX_Msk (0x7UL << MPU_RASR_TEX_Pos) /*!< MPU RASR: ATTRS.TEX Mask */ + +#define MPU_RASR_S_Pos 18U /*!< MPU RASR: ATTRS.S Position */ +#define MPU_RASR_S_Msk (1UL << MPU_RASR_S_Pos) /*!< MPU RASR: ATTRS.S Mask */ + +#define MPU_RASR_C_Pos 17U /*!< MPU RASR: ATTRS.C Position */ +#define MPU_RASR_C_Msk (1UL << MPU_RASR_C_Pos) /*!< MPU RASR: ATTRS.C Mask */ + +#define MPU_RASR_B_Pos 16U /*!< MPU RASR: ATTRS.B Position */ +#define MPU_RASR_B_Msk (1UL << MPU_RASR_B_Pos) /*!< MPU RASR: ATTRS.B Mask */ + +#define MPU_RASR_SRD_Pos 8U /*!< MPU RASR: Sub-Region Disable Position */ +#define MPU_RASR_SRD_Msk (0xFFUL << MPU_RASR_SRD_Pos) /*!< MPU RASR: Sub-Region Disable Mask */ + +#define MPU_RASR_SIZE_Pos 1U /*!< MPU RASR: Region Size Field Position */ +#define MPU_RASR_SIZE_Msk (0x1FUL << MPU_RASR_SIZE_Pos) /*!< MPU RASR: Region Size Field Mask */ + +#define MPU_RASR_ENABLE_Pos 0U /*!< MPU RASR: Region enable bit Position */ +#define MPU_RASR_ENABLE_Msk (1UL /*<< MPU_RASR_ENABLE_Pos*/) /*!< MPU RASR: Region enable bit Disable Mask */ + +/*@} end of group CMSIS_MPU */ +#endif + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_CoreDebug Core Debug Registers (CoreDebug) + \brief Cortex-M0+ Core Debug Registers (DCB registers, SHCSR, and DFSR) are only accessible over DAP and not via processor. + Therefore they are not covered by the Cortex-M0+ header file. + @{ + */ +/*@} end of group CMSIS_CoreDebug */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_core_bitfield Core register bit field macros + \brief Macros for use with bit field definitions (xxx_Pos, xxx_Msk). + @{ + */ + +/** + \brief Mask and shift a bit field value for use in a register bit range. + \param[in] field Name of the register bit field. + \param[in] value Value of the bit field. + \return Masked and shifted value. +*/ +#define _VAL2FLD(field, value) ((value << field ## _Pos) & field ## _Msk) + +/** + \brief Mask and shift a register value to extract a bit filed value. + \param[in] field Name of the register bit field. + \param[in] value Value of register. + \return Masked and shifted bit field value. +*/ +#define _FLD2VAL(field, value) ((value & field ## _Msk) >> field ## _Pos) + +/*@} end of group CMSIS_core_bitfield */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_core_base Core Definitions + \brief Definitions for base addresses, unions, and structures. + @{ + */ + +/* Memory mapping of Cortex-M0+ Hardware */ +#define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */ +#define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */ +#define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */ +#define SCB_BASE (SCS_BASE + 0x0D00UL) /*!< System Control Block Base Address */ + +#define SCB ((SCB_Type *) SCB_BASE ) /*!< SCB configuration struct */ +#define SysTick ((SysTick_Type *) SysTick_BASE ) /*!< SysTick configuration struct */ +#define NVIC ((NVIC_Type *) NVIC_BASE ) /*!< NVIC configuration struct */ + +#if (__MPU_PRESENT == 1U) +#define MPU_BASE (SCS_BASE + 0x0D90UL) /*!< Memory Protection Unit */ +#define MPU ((MPU_Type *) MPU_BASE ) /*!< Memory Protection Unit */ +#endif + +/*@} */ + + + +/******************************************************************************* + * Hardware Abstraction Layer + Core Function Interface contains: + - Core NVIC Functions + - Core SysTick Functions + - Core Register Access Functions + ******************************************************************************/ +/** + \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference +*/ + + + +/* ########################## NVIC functions #################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_NVICFunctions NVIC Functions + \brief Functions that manage interrupts and exceptions via the NVIC. + @{ + */ + +/* Interrupt Priorities are WORD accessible only under ARMv6M */ +/* The following MACROS handle generation of the register offset and byte masks */ +#define _BIT_SHIFT(IRQn) ( ((((uint32_t)(int32_t)(IRQn)) ) & 0x03UL) * 8UL) +#define _SHP_IDX(IRQn) ( (((((uint32_t)(int32_t)(IRQn)) & 0x0FUL)-8UL) >> 2UL) ) +#define _IP_IDX(IRQn) ( (((uint32_t)(int32_t)(IRQn)) >> 2UL) ) + + +/** + \brief Enable External Interrupt + \details Enables a device-specific interrupt in the NVIC interrupt controller. + \param [in] IRQn External interrupt number. Value cannot be negative. + */ +__STATIC_INLINE void NVIC_EnableIRQ(IRQn_Type IRQn) +{ + NVIC->ISER[0U] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL)); +} + + +/** + \brief Disable External Interrupt + \details Disables a device-specific interrupt in the NVIC interrupt controller. + \param [in] IRQn External interrupt number. Value cannot be negative. + */ +__STATIC_INLINE void NVIC_DisableIRQ(IRQn_Type IRQn) +{ + NVIC->ICER[0U] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL)); +} + + +/** + \brief Get Pending Interrupt + \details Reads the pending register in the NVIC and returns the pending bit for the specified interrupt. + \param [in] IRQn Interrupt number. + \return 0 Interrupt status is not pending. + \return 1 Interrupt status is pending. + */ +__STATIC_INLINE uint32_t NVIC_GetPendingIRQ(IRQn_Type IRQn) +{ + return ((uint32_t)(((NVIC->ISPR[0U] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); +} + + +/** + \brief Set Pending Interrupt + \details Sets the pending bit of an external interrupt. + \param [in] IRQn Interrupt number. Value cannot be negative. + */ +__STATIC_INLINE void NVIC_SetPendingIRQ(IRQn_Type IRQn) +{ + NVIC->ISPR[0U] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL)); +} + + +/** + \brief Clear Pending Interrupt + \details Clears the pending bit of an external interrupt. + \param [in] IRQn External interrupt number. Value cannot be negative. + */ +__STATIC_INLINE void NVIC_ClearPendingIRQ(IRQn_Type IRQn) +{ + NVIC->ICPR[0U] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL)); +} + + +/** + \brief Set Interrupt Priority + \details Sets the priority of an interrupt. + \note The priority cannot be set for every core interrupt. + \param [in] IRQn Interrupt number. + \param [in] priority Priority to set. + */ +__STATIC_INLINE void NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority) +{ + if ((int32_t)(IRQn) < 0) + { + SCB->SHP[_SHP_IDX(IRQn)] = ((uint32_t)(SCB->SHP[_SHP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) | + (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn))); + } + else + { + NVIC->IP[_IP_IDX(IRQn)] = ((uint32_t)(NVIC->IP[_IP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) | + (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn))); + } +} + + +/** + \brief Get Interrupt Priority + \details Reads the priority of an interrupt. + The interrupt number can be positive to specify an external (device specific) interrupt, + or negative to specify an internal (core) interrupt. + \param [in] IRQn Interrupt number. + \return Interrupt Priority. + Value is aligned automatically to the implemented priority bits of the microcontroller. + */ +__STATIC_INLINE uint32_t NVIC_GetPriority(IRQn_Type IRQn) +{ + + if ((int32_t)(IRQn) < 0) + { + return ((uint32_t)(((SCB->SHP[_SHP_IDX(IRQn)] >> _BIT_SHIFT(IRQn)) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS))); + } + else + { + return ((uint32_t)(((NVIC->IP[ _IP_IDX(IRQn)] >> _BIT_SHIFT(IRQn)) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS))); + } +} + + +/** + \brief System Reset + \details Initiates a system reset request to reset the MCU. + */ +__STATIC_INLINE void NVIC_SystemReset(void) +{ + __DSB(); /* Ensure all outstanding memory accesses included + buffered write are completed before reset */ + SCB->AIRCR = ((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | + SCB_AIRCR_SYSRESETREQ_Msk); + __DSB(); /* Ensure completion of memory access */ + + for (;;) /* wait until reset */ + { + __NOP(); + } +} + +/*@} end of CMSIS_Core_NVICFunctions */ + + + +/* ################################## SysTick function ############################################ */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_SysTickFunctions SysTick Functions + \brief Functions that configure the System. + @{ + */ + +#if (__Vendor_SysTickConfig == 0U) + +/** + \brief System Tick Configuration + \details Initializes the System Timer and its interrupt, and starts the System Tick Timer. + Counter is in free running mode to generate periodic interrupts. + \param [in] ticks Number of ticks between two interrupts. + \return 0 Function succeeded. + \return 1 Function failed. + \note When the variable __Vendor_SysTickConfig is set to 1, then the + function SysTick_Config is not included. In this case, the file device.h + must contain a vendor-specific implementation of this function. + */ +__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks) +{ + if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk) + { + return (1UL); /* Reload value impossible */ + } + + SysTick->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */ + NVIC_SetPriority(SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */ + SysTick->VAL = 0UL; /* Load the SysTick Counter Value */ + SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk | + SysTick_CTRL_TICKINT_Msk | + SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */ + return (0UL); /* Function successful */ +} + +#endif + +/*@} end of CMSIS_Core_SysTickFunctions */ + + + + +#ifdef __cplusplus +} +#endif + +#endif /* __CORE_CM0PLUS_H_DEPENDANT */ + +#endif /* __CMSIS_GENERIC */ diff --git a/bsp/nuvoton/libraries/ma35/CMSIS/Include/core_cm3.h b/bsp/nuvoton/libraries/ma35/CMSIS/Include/core_cm3.h new file mode 100644 index 0000000000..337c324442 --- /dev/null +++ b/bsp/nuvoton/libraries/ma35/CMSIS/Include/core_cm3.h @@ -0,0 +1,1763 @@ +/**************************************************************************//** + * @file core_cm3.h + * @brief CMSIS Cortex-M3 Core Peripheral Access Layer Header File + * @version V4.30 + * @date 20. October 2015 + ******************************************************************************/ +/* Copyright (c) 2009 - 2015 ARM LIMITED + + All rights reserved. + Redistribution and use in source and binary forms, with or without + modification, are permitted provided that the following conditions are met: + - Redistributions of source code must retain the above copyright + notice, this list of conditions and the following disclaimer. + - Redistributions in binary form must reproduce the above copyright + notice, this list of conditions and the following disclaimer in the + documentation and/or other materials provided with the distribution. + - Neither the name of ARM nor the names of its contributors may be used + to endorse or promote products derived from this software without + specific prior written permission. + * + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE + LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + POSSIBILITY OF SUCH DAMAGE. + ---------------------------------------------------------------------------*/ + + +#if defined ( __ICCARM__ ) + #pragma system_include /* treat file as system include file for MISRA check */ +#elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) + #pragma clang system_header /* treat file as system include file */ +#endif + +#ifndef __CORE_CM3_H_GENERIC +#define __CORE_CM3_H_GENERIC + +#include + +#ifdef __cplusplus +extern "C" { +#endif + +/** + \page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions + CMSIS violates the following MISRA-C:2004 rules: + + \li Required Rule 8.5, object/function definition in header file.
+ Function definitions in header files are used to allow 'inlining'. + + \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.
+ Unions are used for effective representation of core registers. + + \li Advisory Rule 19.7, Function-like macro defined.
+ Function-like macros are used to allow more efficient code. + */ + + +/******************************************************************************* + * CMSIS definitions + ******************************************************************************/ +/** + \ingroup Cortex_M3 + @{ + */ + +/* CMSIS CM3 definitions */ +#define __CM3_CMSIS_VERSION_MAIN (0x04U) /*!< [31:16] CMSIS HAL main version */ +#define __CM3_CMSIS_VERSION_SUB (0x1EU) /*!< [15:0] CMSIS HAL sub version */ +#define __CM3_CMSIS_VERSION ((__CM3_CMSIS_VERSION_MAIN << 16U) | \ + __CM3_CMSIS_VERSION_SUB ) /*!< CMSIS HAL version number */ + +#define __CORTEX_M (0x03U) /*!< Cortex-M Core */ + + +#if defined ( __CC_ARM ) +#define __ASM __asm /*!< asm keyword for ARM Compiler */ +#define __INLINE __inline /*!< inline keyword for ARM Compiler */ +#define __STATIC_INLINE static __inline + +#elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) +#define __ASM __asm /*!< asm keyword for ARM Compiler */ +#define __INLINE __inline /*!< inline keyword for ARM Compiler */ +#define __STATIC_INLINE static __inline + +#elif defined ( __GNUC__ ) +#define __ASM __asm /*!< asm keyword for GNU Compiler */ +#define __INLINE inline /*!< inline keyword for GNU Compiler */ +#define __STATIC_INLINE static inline + +#elif defined ( __ICCARM__ ) +#define __ASM __asm /*!< asm keyword for IAR Compiler */ +#define __INLINE inline /*!< inline keyword for IAR Compiler. Only available in High optimization mode! */ +#define __STATIC_INLINE static inline + +#elif defined ( __TMS470__ ) +#define __ASM __asm /*!< asm keyword for TI CCS Compiler */ +#define __STATIC_INLINE static inline + +#elif defined ( __TASKING__ ) +#define __ASM __asm /*!< asm keyword for TASKING Compiler */ +#define __INLINE inline /*!< inline keyword for TASKING Compiler */ +#define __STATIC_INLINE static inline + +#elif defined ( __CSMC__ ) +#define __packed +#define __ASM _asm /*!< asm keyword for COSMIC Compiler */ +#define __INLINE inline /*!< inline keyword for COSMIC Compiler. Use -pc99 on compile line */ +#define __STATIC_INLINE static inline + +#else +#error Unknown compiler +#endif + +/** __FPU_USED indicates whether an FPU is used or not. + This core does not support an FPU at all +*/ +#define __FPU_USED 0U + +#if defined ( __CC_ARM ) +#if defined __TARGET_FPU_VFP +#error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" +#endif + +#elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) +#if defined __ARM_PCS_VFP +#error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" +#endif + +#elif defined ( __GNUC__ ) +#if defined (__VFP_FP__) && !defined(__SOFTFP__) +#error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" +#endif + +#elif defined ( __ICCARM__ ) +#if defined __ARMVFP__ +#error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" +#endif + +#elif defined ( __TMS470__ ) +#if defined __TI_VFP_SUPPORT__ +#error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" +#endif + +#elif defined ( __TASKING__ ) +#if defined __FPU_VFP__ +#error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" +#endif + +#elif defined ( __CSMC__ ) +#if ( __CSMC__ & 0x400U) +#error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" +#endif + +#endif + +#include "core_cmInstr.h" /* Core Instruction Access */ +#include "core_cmFunc.h" /* Core Function Access */ + +#ifdef __cplusplus +} +#endif + +#endif /* __CORE_CM3_H_GENERIC */ + +#ifndef __CMSIS_GENERIC + +#ifndef __CORE_CM3_H_DEPENDANT +#define __CORE_CM3_H_DEPENDANT + +#ifdef __cplusplus +extern "C" { +#endif + +/* check device defines and use defaults */ +#if defined __CHECK_DEVICE_DEFINES +#ifndef __CM3_REV +#define __CM3_REV 0x0200U +#warning "__CM3_REV not defined in device header file; using default!" +#endif + +#ifndef __MPU_PRESENT +#define __MPU_PRESENT 0U +#warning "__MPU_PRESENT not defined in device header file; using default!" +#endif + +#ifndef __NVIC_PRIO_BITS +#define __NVIC_PRIO_BITS 4U +#warning "__NVIC_PRIO_BITS not defined in device header file; using default!" +#endif + +#ifndef __Vendor_SysTickConfig +#define __Vendor_SysTickConfig 0U +#warning "__Vendor_SysTickConfig not defined in device header file; using default!" +#endif +#endif + +/* IO definitions (access restrictions to peripheral registers) */ +/** + \defgroup CMSIS_glob_defs CMSIS Global Defines + + IO Type Qualifiers are used + \li to specify the access to peripheral variables. + \li for automatic generation of peripheral register debug information. +*/ +#ifdef __cplusplus +#define __I volatile /*!< Defines 'read only' permissions */ +#else +#define __I volatile const /*!< Defines 'read only' permissions */ +#endif +#define __O volatile /*!< Defines 'write only' permissions */ +#define __IO volatile /*!< Defines 'read / write' permissions */ + +/* following defines should be used for structure members */ +#define __IM volatile const /*! Defines 'read only' structure member permissions */ +#define __OM volatile /*! Defines 'write only' structure member permissions */ +#define __IOM volatile /*! Defines 'read / write' structure member permissions */ + +/*@} end of group Cortex_M3 */ + + + +/******************************************************************************* + * Register Abstraction + Core Register contain: + - Core Register + - Core NVIC Register + - Core SCB Register + - Core SysTick Register + - Core Debug Register + - Core MPU Register + ******************************************************************************/ +/** + \defgroup CMSIS_core_register Defines and Type Definitions + \brief Type definitions and defines for Cortex-M processor based devices. +*/ + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_CORE Status and Control Registers + \brief Core Register type definitions. + @{ + */ + +/** + \brief Union type to access the Application Program Status Register (APSR). + */ +typedef union +{ + struct + { + uint32_t _reserved0: 27; /*!< bit: 0..26 Reserved */ + uint32_t Q: 1; /*!< bit: 27 Saturation condition flag */ + uint32_t V: 1; /*!< bit: 28 Overflow condition code flag */ + uint32_t C: 1; /*!< bit: 29 Carry condition code flag */ + uint32_t Z: 1; /*!< bit: 30 Zero condition code flag */ + uint32_t N: 1; /*!< bit: 31 Negative condition code flag */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} APSR_Type; + +/* APSR Register Definitions */ +#define APSR_N_Pos 31U /*!< APSR: N Position */ +#define APSR_N_Msk (1UL << APSR_N_Pos) /*!< APSR: N Mask */ + +#define APSR_Z_Pos 30U /*!< APSR: Z Position */ +#define APSR_Z_Msk (1UL << APSR_Z_Pos) /*!< APSR: Z Mask */ + +#define APSR_C_Pos 29U /*!< APSR: C Position */ +#define APSR_C_Msk (1UL << APSR_C_Pos) /*!< APSR: C Mask */ + +#define APSR_V_Pos 28U /*!< APSR: V Position */ +#define APSR_V_Msk (1UL << APSR_V_Pos) /*!< APSR: V Mask */ + +#define APSR_Q_Pos 27U /*!< APSR: Q Position */ +#define APSR_Q_Msk (1UL << APSR_Q_Pos) /*!< APSR: Q Mask */ + + +/** + \brief Union type to access the Interrupt Program Status Register (IPSR). + */ +typedef union +{ + struct + { + uint32_t ISR: 9; /*!< bit: 0.. 8 Exception number */ + uint32_t _reserved0: 23; /*!< bit: 9..31 Reserved */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} IPSR_Type; + +/* IPSR Register Definitions */ +#define IPSR_ISR_Pos 0U /*!< IPSR: ISR Position */ +#define IPSR_ISR_Msk (0x1FFUL /*<< IPSR_ISR_Pos*/) /*!< IPSR: ISR Mask */ + + +/** + \brief Union type to access the Special-Purpose Program Status Registers (xPSR). + */ +typedef union +{ + struct + { + uint32_t ISR: 9; /*!< bit: 0.. 8 Exception number */ + uint32_t _reserved0: 15; /*!< bit: 9..23 Reserved */ + uint32_t T: 1; /*!< bit: 24 Thumb bit (read 0) */ + uint32_t IT: 2; /*!< bit: 25..26 saved IT state (read 0) */ + uint32_t Q: 1; /*!< bit: 27 Saturation condition flag */ + uint32_t V: 1; /*!< bit: 28 Overflow condition code flag */ + uint32_t C: 1; /*!< bit: 29 Carry condition code flag */ + uint32_t Z: 1; /*!< bit: 30 Zero condition code flag */ + uint32_t N: 1; /*!< bit: 31 Negative condition code flag */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} xPSR_Type; + +/* xPSR Register Definitions */ +#define xPSR_N_Pos 31U /*!< xPSR: N Position */ +#define xPSR_N_Msk (1UL << xPSR_N_Pos) /*!< xPSR: N Mask */ + +#define xPSR_Z_Pos 30U /*!< xPSR: Z Position */ +#define xPSR_Z_Msk (1UL << xPSR_Z_Pos) /*!< xPSR: Z Mask */ + +#define xPSR_C_Pos 29U /*!< xPSR: C Position */ +#define xPSR_C_Msk (1UL << xPSR_C_Pos) /*!< xPSR: C Mask */ + +#define xPSR_V_Pos 28U /*!< xPSR: V Position */ +#define xPSR_V_Msk (1UL << xPSR_V_Pos) /*!< xPSR: V Mask */ + +#define xPSR_Q_Pos 27U /*!< xPSR: Q Position */ +#define xPSR_Q_Msk (1UL << xPSR_Q_Pos) /*!< xPSR: Q Mask */ + +#define xPSR_IT_Pos 25U /*!< xPSR: IT Position */ +#define xPSR_IT_Msk (3UL << xPSR_IT_Pos) /*!< xPSR: IT Mask */ + +#define xPSR_T_Pos 24U /*!< xPSR: T Position */ +#define xPSR_T_Msk (1UL << xPSR_T_Pos) /*!< xPSR: T Mask */ + +#define xPSR_ISR_Pos 0U /*!< xPSR: ISR Position */ +#define xPSR_ISR_Msk (0x1FFUL /*<< xPSR_ISR_Pos*/) /*!< xPSR: ISR Mask */ + + +/** + \brief Union type to access the Control Registers (CONTROL). + */ +typedef union +{ + struct + { + uint32_t nPRIV: 1; /*!< bit: 0 Execution privilege in Thread mode */ + uint32_t SPSEL: 1; /*!< bit: 1 Stack to be used */ + uint32_t _reserved1: 30; /*!< bit: 2..31 Reserved */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} CONTROL_Type; + +/* CONTROL Register Definitions */ +#define CONTROL_SPSEL_Pos 1U /*!< CONTROL: SPSEL Position */ +#define CONTROL_SPSEL_Msk (1UL << CONTROL_SPSEL_Pos) /*!< CONTROL: SPSEL Mask */ + +#define CONTROL_nPRIV_Pos 0U /*!< CONTROL: nPRIV Position */ +#define CONTROL_nPRIV_Msk (1UL /*<< CONTROL_nPRIV_Pos*/) /*!< CONTROL: nPRIV Mask */ + +/*@} end of group CMSIS_CORE */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC) + \brief Type definitions for the NVIC Registers + @{ + */ + +/** + \brief Structure type to access the Nested Vectored Interrupt Controller (NVIC). + */ +typedef struct +{ + __IOM uint32_t ISER[8U]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */ + uint32_t RESERVED0[24U]; + __IOM uint32_t ICER[8U]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */ + uint32_t RSERVED1[24U]; + __IOM uint32_t ISPR[8U]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */ + uint32_t RESERVED2[24U]; + __IOM uint32_t ICPR[8U]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register */ + uint32_t RESERVED3[24U]; + __IOM uint32_t IABR[8U]; /*!< Offset: 0x200 (R/W) Interrupt Active bit Register */ + uint32_t RESERVED4[56U]; + __IOM uint8_t IP[240U]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register (8Bit wide) */ + uint32_t RESERVED5[644U]; + __OM uint32_t STIR; /*!< Offset: 0xE00 ( /W) Software Trigger Interrupt Register */ +} NVIC_Type; + +/* Software Triggered Interrupt Register Definitions */ +#define NVIC_STIR_INTID_Pos 0U /*!< STIR: INTLINESNUM Position */ +#define NVIC_STIR_INTID_Msk (0x1FFUL /*<< NVIC_STIR_INTID_Pos*/) /*!< STIR: INTLINESNUM Mask */ + +/*@} end of group CMSIS_NVIC */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SCB System Control Block (SCB) + \brief Type definitions for the System Control Block Registers + @{ + */ + +/** + \brief Structure type to access the System Control Block (SCB). + */ +typedef struct +{ + __IM uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */ + __IOM uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Register */ + __IOM uint32_t VTOR; /*!< Offset: 0x008 (R/W) Vector Table Offset Register */ + __IOM uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register */ + __IOM uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */ + __IOM uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */ + __IOM uint8_t SHP[12U]; /*!< Offset: 0x018 (R/W) System Handlers Priority Registers (4-7, 8-11, 12-15) */ + __IOM uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State Register */ + __IOM uint32_t CFSR; /*!< Offset: 0x028 (R/W) Configurable Fault Status Register */ + __IOM uint32_t HFSR; /*!< Offset: 0x02C (R/W) HardFault Status Register */ + __IOM uint32_t DFSR; /*!< Offset: 0x030 (R/W) Debug Fault Status Register */ + __IOM uint32_t MMFAR; /*!< Offset: 0x034 (R/W) MemManage Fault Address Register */ + __IOM uint32_t BFAR; /*!< Offset: 0x038 (R/W) BusFault Address Register */ + __IOM uint32_t AFSR; /*!< Offset: 0x03C (R/W) Auxiliary Fault Status Register */ + __IM uint32_t PFR[2U]; /*!< Offset: 0x040 (R/ ) Processor Feature Register */ + __IM uint32_t DFR; /*!< Offset: 0x048 (R/ ) Debug Feature Register */ + __IM uint32_t ADR; /*!< Offset: 0x04C (R/ ) Auxiliary Feature Register */ + __IM uint32_t MMFR[4U]; /*!< Offset: 0x050 (R/ ) Memory Model Feature Register */ + __IM uint32_t ISAR[5U]; /*!< Offset: 0x060 (R/ ) Instruction Set Attributes Register */ + uint32_t RESERVED0[5U]; + __IOM uint32_t CPACR; /*!< Offset: 0x088 (R/W) Coprocessor Access Control Register */ +} SCB_Type; + +/* SCB CPUID Register Definitions */ +#define SCB_CPUID_IMPLEMENTER_Pos 24U /*!< SCB CPUID: IMPLEMENTER Position */ +#define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */ + +#define SCB_CPUID_VARIANT_Pos 20U /*!< SCB CPUID: VARIANT Position */ +#define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */ + +#define SCB_CPUID_ARCHITECTURE_Pos 16U /*!< SCB CPUID: ARCHITECTURE Position */ +#define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB CPUID: ARCHITECTURE Mask */ + +#define SCB_CPUID_PARTNO_Pos 4U /*!< SCB CPUID: PARTNO Position */ +#define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */ + +#define SCB_CPUID_REVISION_Pos 0U /*!< SCB CPUID: REVISION Position */ +#define SCB_CPUID_REVISION_Msk (0xFUL /*<< SCB_CPUID_REVISION_Pos*/) /*!< SCB CPUID: REVISION Mask */ + +/* SCB Interrupt Control State Register Definitions */ +#define SCB_ICSR_NMIPENDSET_Pos 31U /*!< SCB ICSR: NMIPENDSET Position */ +#define SCB_ICSR_NMIPENDSET_Msk (1UL << SCB_ICSR_NMIPENDSET_Pos) /*!< SCB ICSR: NMIPENDSET Mask */ + +#define SCB_ICSR_PENDSVSET_Pos 28U /*!< SCB ICSR: PENDSVSET Position */ +#define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */ + +#define SCB_ICSR_PENDSVCLR_Pos 27U /*!< SCB ICSR: PENDSVCLR Position */ +#define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */ + +#define SCB_ICSR_PENDSTSET_Pos 26U /*!< SCB ICSR: PENDSTSET Position */ +#define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */ + +#define SCB_ICSR_PENDSTCLR_Pos 25U /*!< SCB ICSR: PENDSTCLR Position */ +#define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */ + +#define SCB_ICSR_ISRPREEMPT_Pos 23U /*!< SCB ICSR: ISRPREEMPT Position */ +#define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */ + +#define SCB_ICSR_ISRPENDING_Pos 22U /*!< SCB ICSR: ISRPENDING Position */ +#define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */ + +#define SCB_ICSR_VECTPENDING_Pos 12U /*!< SCB ICSR: VECTPENDING Position */ +#define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */ + +#define SCB_ICSR_RETTOBASE_Pos 11U /*!< SCB ICSR: RETTOBASE Position */ +#define SCB_ICSR_RETTOBASE_Msk (1UL << SCB_ICSR_RETTOBASE_Pos) /*!< SCB ICSR: RETTOBASE Mask */ + +#define SCB_ICSR_VECTACTIVE_Pos 0U /*!< SCB ICSR: VECTACTIVE Position */ +#define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/) /*!< SCB ICSR: VECTACTIVE Mask */ + +/* SCB Vector Table Offset Register Definitions */ +#if (__CM3_REV < 0x0201U) /* core r2p1 */ +#define SCB_VTOR_TBLBASE_Pos 29U /*!< SCB VTOR: TBLBASE Position */ +#define SCB_VTOR_TBLBASE_Msk (1UL << SCB_VTOR_TBLBASE_Pos) /*!< SCB VTOR: TBLBASE Mask */ + +#define SCB_VTOR_TBLOFF_Pos 7U /*!< SCB VTOR: TBLOFF Position */ +#define SCB_VTOR_TBLOFF_Msk (0x3FFFFFUL << SCB_VTOR_TBLOFF_Pos) /*!< SCB VTOR: TBLOFF Mask */ +#else +#define SCB_VTOR_TBLOFF_Pos 7U /*!< SCB VTOR: TBLOFF Position */ +#define SCB_VTOR_TBLOFF_Msk (0x1FFFFFFUL << SCB_VTOR_TBLOFF_Pos) /*!< SCB VTOR: TBLOFF Mask */ +#endif + +/* SCB Application Interrupt and Reset Control Register Definitions */ +#define SCB_AIRCR_VECTKEY_Pos 16U /*!< SCB AIRCR: VECTKEY Position */ +#define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */ + +#define SCB_AIRCR_VECTKEYSTAT_Pos 16U /*!< SCB AIRCR: VECTKEYSTAT Position */ +#define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */ + +#define SCB_AIRCR_ENDIANESS_Pos 15U /*!< SCB AIRCR: ENDIANESS Position */ +#define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /*!< SCB AIRCR: ENDIANESS Mask */ + +#define SCB_AIRCR_PRIGROUP_Pos 8U /*!< SCB AIRCR: PRIGROUP Position */ +#define SCB_AIRCR_PRIGROUP_Msk (7UL << SCB_AIRCR_PRIGROUP_Pos) /*!< SCB AIRCR: PRIGROUP Mask */ + +#define SCB_AIRCR_SYSRESETREQ_Pos 2U /*!< SCB AIRCR: SYSRESETREQ Position */ +#define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */ + +#define SCB_AIRCR_VECTCLRACTIVE_Pos 1U /*!< SCB AIRCR: VECTCLRACTIVE Position */ +#define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */ + +#define SCB_AIRCR_VECTRESET_Pos 0U /*!< SCB AIRCR: VECTRESET Position */ +#define SCB_AIRCR_VECTRESET_Msk (1UL /*<< SCB_AIRCR_VECTRESET_Pos*/) /*!< SCB AIRCR: VECTRESET Mask */ + +/* SCB System Control Register Definitions */ +#define SCB_SCR_SEVONPEND_Pos 4U /*!< SCB SCR: SEVONPEND Position */ +#define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */ + +#define SCB_SCR_SLEEPDEEP_Pos 2U /*!< SCB SCR: SLEEPDEEP Position */ +#define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */ + +#define SCB_SCR_SLEEPONEXIT_Pos 1U /*!< SCB SCR: SLEEPONEXIT Position */ +#define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */ + +/* SCB Configuration Control Register Definitions */ +#define SCB_CCR_STKALIGN_Pos 9U /*!< SCB CCR: STKALIGN Position */ +#define SCB_CCR_STKALIGN_Msk (1UL << SCB_CCR_STKALIGN_Pos) /*!< SCB CCR: STKALIGN Mask */ + +#define SCB_CCR_BFHFNMIGN_Pos 8U /*!< SCB CCR: BFHFNMIGN Position */ +#define SCB_CCR_BFHFNMIGN_Msk (1UL << SCB_CCR_BFHFNMIGN_Pos) /*!< SCB CCR: BFHFNMIGN Mask */ + +#define SCB_CCR_DIV_0_TRP_Pos 4U /*!< SCB CCR: DIV_0_TRP Position */ +#define SCB_CCR_DIV_0_TRP_Msk (1UL << SCB_CCR_DIV_0_TRP_Pos) /*!< SCB CCR: DIV_0_TRP Mask */ + +#define SCB_CCR_UNALIGN_TRP_Pos 3U /*!< SCB CCR: UNALIGN_TRP Position */ +#define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */ + +#define SCB_CCR_USERSETMPEND_Pos 1U /*!< SCB CCR: USERSETMPEND Position */ +#define SCB_CCR_USERSETMPEND_Msk (1UL << SCB_CCR_USERSETMPEND_Pos) /*!< SCB CCR: USERSETMPEND Mask */ + +#define SCB_CCR_NONBASETHRDENA_Pos 0U /*!< SCB CCR: NONBASETHRDENA Position */ +#define SCB_CCR_NONBASETHRDENA_Msk (1UL /*<< SCB_CCR_NONBASETHRDENA_Pos*/) /*!< SCB CCR: NONBASETHRDENA Mask */ + +/* SCB System Handler Control and State Register Definitions */ +#define SCB_SHCSR_USGFAULTENA_Pos 18U /*!< SCB SHCSR: USGFAULTENA Position */ +#define SCB_SHCSR_USGFAULTENA_Msk (1UL << SCB_SHCSR_USGFAULTENA_Pos) /*!< SCB SHCSR: USGFAULTENA Mask */ + +#define SCB_SHCSR_BUSFAULTENA_Pos 17U /*!< SCB SHCSR: BUSFAULTENA Position */ +#define SCB_SHCSR_BUSFAULTENA_Msk (1UL << SCB_SHCSR_BUSFAULTENA_Pos) /*!< SCB SHCSR: BUSFAULTENA Mask */ + +#define SCB_SHCSR_MEMFAULTENA_Pos 16U /*!< SCB SHCSR: MEMFAULTENA Position */ +#define SCB_SHCSR_MEMFAULTENA_Msk (1UL << SCB_SHCSR_MEMFAULTENA_Pos) /*!< SCB SHCSR: MEMFAULTENA Mask */ + +#define SCB_SHCSR_SVCALLPENDED_Pos 15U /*!< SCB SHCSR: SVCALLPENDED Position */ +#define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */ + +#define SCB_SHCSR_BUSFAULTPENDED_Pos 14U /*!< SCB SHCSR: BUSFAULTPENDED Position */ +#define SCB_SHCSR_BUSFAULTPENDED_Msk (1UL << SCB_SHCSR_BUSFAULTPENDED_Pos) /*!< SCB SHCSR: BUSFAULTPENDED Mask */ + +#define SCB_SHCSR_MEMFAULTPENDED_Pos 13U /*!< SCB SHCSR: MEMFAULTPENDED Position */ +#define SCB_SHCSR_MEMFAULTPENDED_Msk (1UL << SCB_SHCSR_MEMFAULTPENDED_Pos) /*!< SCB SHCSR: MEMFAULTPENDED Mask */ + +#define SCB_SHCSR_USGFAULTPENDED_Pos 12U /*!< SCB SHCSR: USGFAULTPENDED Position */ +#define SCB_SHCSR_USGFAULTPENDED_Msk (1UL << SCB_SHCSR_USGFAULTPENDED_Pos) /*!< SCB SHCSR: USGFAULTPENDED Mask */ + +#define SCB_SHCSR_SYSTICKACT_Pos 11U /*!< SCB SHCSR: SYSTICKACT Position */ +#define SCB_SHCSR_SYSTICKACT_Msk (1UL << SCB_SHCSR_SYSTICKACT_Pos) /*!< SCB SHCSR: SYSTICKACT Mask */ + +#define SCB_SHCSR_PENDSVACT_Pos 10U /*!< SCB SHCSR: PENDSVACT Position */ +#define SCB_SHCSR_PENDSVACT_Msk (1UL << SCB_SHCSR_PENDSVACT_Pos) /*!< SCB SHCSR: PENDSVACT Mask */ + +#define SCB_SHCSR_MONITORACT_Pos 8U /*!< SCB SHCSR: MONITORACT Position */ +#define SCB_SHCSR_MONITORACT_Msk (1UL << SCB_SHCSR_MONITORACT_Pos) /*!< SCB SHCSR: MONITORACT Mask */ + +#define SCB_SHCSR_SVCALLACT_Pos 7U /*!< SCB SHCSR: SVCALLACT Position */ +#define SCB_SHCSR_SVCALLACT_Msk (1UL << SCB_SHCSR_SVCALLACT_Pos) /*!< SCB SHCSR: SVCALLACT Mask */ + +#define SCB_SHCSR_USGFAULTACT_Pos 3U /*!< SCB SHCSR: USGFAULTACT Position */ +#define SCB_SHCSR_USGFAULTACT_Msk (1UL << SCB_SHCSR_USGFAULTACT_Pos) /*!< SCB SHCSR: USGFAULTACT Mask */ + +#define SCB_SHCSR_BUSFAULTACT_Pos 1U /*!< SCB SHCSR: BUSFAULTACT Position */ +#define SCB_SHCSR_BUSFAULTACT_Msk (1UL << SCB_SHCSR_BUSFAULTACT_Pos) /*!< SCB SHCSR: BUSFAULTACT Mask */ + +#define SCB_SHCSR_MEMFAULTACT_Pos 0U /*!< SCB SHCSR: MEMFAULTACT Position */ +#define SCB_SHCSR_MEMFAULTACT_Msk (1UL /*<< SCB_SHCSR_MEMFAULTACT_Pos*/) /*!< SCB SHCSR: MEMFAULTACT Mask */ + +/* SCB Configurable Fault Status Register Definitions */ +#define SCB_CFSR_USGFAULTSR_Pos 16U /*!< SCB CFSR: Usage Fault Status Register Position */ +#define SCB_CFSR_USGFAULTSR_Msk (0xFFFFUL << SCB_CFSR_USGFAULTSR_Pos) /*!< SCB CFSR: Usage Fault Status Register Mask */ + +#define SCB_CFSR_BUSFAULTSR_Pos 8U /*!< SCB CFSR: Bus Fault Status Register Position */ +#define SCB_CFSR_BUSFAULTSR_Msk (0xFFUL << SCB_CFSR_BUSFAULTSR_Pos) /*!< SCB CFSR: Bus Fault Status Register Mask */ + +#define SCB_CFSR_MEMFAULTSR_Pos 0U /*!< SCB CFSR: Memory Manage Fault Status Register Position */ +#define SCB_CFSR_MEMFAULTSR_Msk (0xFFUL /*<< SCB_CFSR_MEMFAULTSR_Pos*/) /*!< SCB CFSR: Memory Manage Fault Status Register Mask */ + +/* SCB Hard Fault Status Register Definitions */ +#define SCB_HFSR_DEBUGEVT_Pos 31U /*!< SCB HFSR: DEBUGEVT Position */ +#define SCB_HFSR_DEBUGEVT_Msk (1UL << SCB_HFSR_DEBUGEVT_Pos) /*!< SCB HFSR: DEBUGEVT Mask */ + +#define SCB_HFSR_FORCED_Pos 30U /*!< SCB HFSR: FORCED Position */ +#define SCB_HFSR_FORCED_Msk (1UL << SCB_HFSR_FORCED_Pos) /*!< SCB HFSR: FORCED Mask */ + +#define SCB_HFSR_VECTTBL_Pos 1U /*!< SCB HFSR: VECTTBL Position */ +#define SCB_HFSR_VECTTBL_Msk (1UL << SCB_HFSR_VECTTBL_Pos) /*!< SCB HFSR: VECTTBL Mask */ + +/* SCB Debug Fault Status Register Definitions */ +#define SCB_DFSR_EXTERNAL_Pos 4U /*!< SCB DFSR: EXTERNAL Position */ +#define SCB_DFSR_EXTERNAL_Msk (1UL << SCB_DFSR_EXTERNAL_Pos) /*!< SCB DFSR: EXTERNAL Mask */ + +#define SCB_DFSR_VCATCH_Pos 3U /*!< SCB DFSR: VCATCH Position */ +#define SCB_DFSR_VCATCH_Msk (1UL << SCB_DFSR_VCATCH_Pos) /*!< SCB DFSR: VCATCH Mask */ + +#define SCB_DFSR_DWTTRAP_Pos 2U /*!< SCB DFSR: DWTTRAP Position */ +#define SCB_DFSR_DWTTRAP_Msk (1UL << SCB_DFSR_DWTTRAP_Pos) /*!< SCB DFSR: DWTTRAP Mask */ + +#define SCB_DFSR_BKPT_Pos 1U /*!< SCB DFSR: BKPT Position */ +#define SCB_DFSR_BKPT_Msk (1UL << SCB_DFSR_BKPT_Pos) /*!< SCB DFSR: BKPT Mask */ + +#define SCB_DFSR_HALTED_Pos 0U /*!< SCB DFSR: HALTED Position */ +#define SCB_DFSR_HALTED_Msk (1UL /*<< SCB_DFSR_HALTED_Pos*/) /*!< SCB DFSR: HALTED Mask */ + +/*@} end of group CMSIS_SCB */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SCnSCB System Controls not in SCB (SCnSCB) + \brief Type definitions for the System Control and ID Register not in the SCB + @{ + */ + +/** + \brief Structure type to access the System Control and ID Register not in the SCB. + */ +typedef struct +{ + uint32_t RESERVED0[1U]; + __IM uint32_t ICTR; /*!< Offset: 0x004 (R/ ) Interrupt Controller Type Register */ +#if ((defined __CM3_REV) && (__CM3_REV >= 0x200U)) + __IOM uint32_t ACTLR; /*!< Offset: 0x008 (R/W) Auxiliary Control Register */ +#else + uint32_t RESERVED1[1U]; +#endif +} SCnSCB_Type; + +/* Interrupt Controller Type Register Definitions */ +#define SCnSCB_ICTR_INTLINESNUM_Pos 0U /*!< ICTR: INTLINESNUM Position */ +#define SCnSCB_ICTR_INTLINESNUM_Msk (0xFUL /*<< SCnSCB_ICTR_INTLINESNUM_Pos*/) /*!< ICTR: INTLINESNUM Mask */ + +/* Auxiliary Control Register Definitions */ + +#define SCnSCB_ACTLR_DISFOLD_Pos 2U /*!< ACTLR: DISFOLD Position */ +#define SCnSCB_ACTLR_DISFOLD_Msk (1UL << SCnSCB_ACTLR_DISFOLD_Pos) /*!< ACTLR: DISFOLD Mask */ + +#define SCnSCB_ACTLR_DISDEFWBUF_Pos 1U /*!< ACTLR: DISDEFWBUF Position */ +#define SCnSCB_ACTLR_DISDEFWBUF_Msk (1UL << SCnSCB_ACTLR_DISDEFWBUF_Pos) /*!< ACTLR: DISDEFWBUF Mask */ + +#define SCnSCB_ACTLR_DISMCYCINT_Pos 0U /*!< ACTLR: DISMCYCINT Position */ +#define SCnSCB_ACTLR_DISMCYCINT_Msk (1UL /*<< SCnSCB_ACTLR_DISMCYCINT_Pos*/) /*!< ACTLR: DISMCYCINT Mask */ + +/*@} end of group CMSIS_SCnotSCB */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SysTick System Tick Timer (SysTick) + \brief Type definitions for the System Timer Registers. + @{ + */ + +/** + \brief Structure type to access the System Timer (SysTick). + */ +typedef struct +{ + __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */ + __IOM uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */ + __IOM uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register */ + __IM uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */ +} SysTick_Type; + +/* SysTick Control / Status Register Definitions */ +#define SysTick_CTRL_COUNTFLAG_Pos 16U /*!< SysTick CTRL: COUNTFLAG Position */ +#define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */ + +#define SysTick_CTRL_CLKSOURCE_Pos 2U /*!< SysTick CTRL: CLKSOURCE Position */ +#define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */ + +#define SysTick_CTRL_TICKINT_Pos 1U /*!< SysTick CTRL: TICKINT Position */ +#define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */ + +#define SysTick_CTRL_ENABLE_Pos 0U /*!< SysTick CTRL: ENABLE Position */ +#define SysTick_CTRL_ENABLE_Msk (1UL /*<< SysTick_CTRL_ENABLE_Pos*/) /*!< SysTick CTRL: ENABLE Mask */ + +/* SysTick Reload Register Definitions */ +#define SysTick_LOAD_RELOAD_Pos 0U /*!< SysTick LOAD: RELOAD Position */ +#define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/) /*!< SysTick LOAD: RELOAD Mask */ + +/* SysTick Current Register Definitions */ +#define SysTick_VAL_CURRENT_Pos 0U /*!< SysTick VAL: CURRENT Position */ +#define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/) /*!< SysTick VAL: CURRENT Mask */ + +/* SysTick Calibration Register Definitions */ +#define SysTick_CALIB_NOREF_Pos 31U /*!< SysTick CALIB: NOREF Position */ +#define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */ + +#define SysTick_CALIB_SKEW_Pos 30U /*!< SysTick CALIB: SKEW Position */ +#define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */ + +#define SysTick_CALIB_TENMS_Pos 0U /*!< SysTick CALIB: TENMS Position */ +#define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/) /*!< SysTick CALIB: TENMS Mask */ + +/*@} end of group CMSIS_SysTick */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_ITM Instrumentation Trace Macrocell (ITM) + \brief Type definitions for the Instrumentation Trace Macrocell (ITM) + @{ + */ + +/** + \brief Structure type to access the Instrumentation Trace Macrocell Register (ITM). + */ +typedef struct +{ + __OM union + { + __OM uint8_t u8; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 8-bit */ + __OM uint16_t u16; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 16-bit */ + __OM uint32_t u32; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 32-bit */ + } PORT [32U]; /*!< Offset: 0x000 ( /W) ITM Stimulus Port Registers */ + uint32_t RESERVED0[864U]; + __IOM uint32_t TER; /*!< Offset: 0xE00 (R/W) ITM Trace Enable Register */ + uint32_t RESERVED1[15U]; + __IOM uint32_t TPR; /*!< Offset: 0xE40 (R/W) ITM Trace Privilege Register */ + uint32_t RESERVED2[15U]; + __IOM uint32_t TCR; /*!< Offset: 0xE80 (R/W) ITM Trace Control Register */ + uint32_t RESERVED3[29U]; + __OM uint32_t IWR; /*!< Offset: 0xEF8 ( /W) ITM Integration Write Register */ + __IM uint32_t IRR; /*!< Offset: 0xEFC (R/ ) ITM Integration Read Register */ + __IOM uint32_t IMCR; /*!< Offset: 0xF00 (R/W) ITM Integration Mode Control Register */ + uint32_t RESERVED4[43U]; + __OM uint32_t LAR; /*!< Offset: 0xFB0 ( /W) ITM Lock Access Register */ + __IM uint32_t LSR; /*!< Offset: 0xFB4 (R/ ) ITM Lock Status Register */ + uint32_t RESERVED5[6U]; + __IM uint32_t PID4; /*!< Offset: 0xFD0 (R/ ) ITM Peripheral Identification Register #4 */ + __IM uint32_t PID5; /*!< Offset: 0xFD4 (R/ ) ITM Peripheral Identification Register #5 */ + __IM uint32_t PID6; /*!< Offset: 0xFD8 (R/ ) ITM Peripheral Identification Register #6 */ + __IM uint32_t PID7; /*!< Offset: 0xFDC (R/ ) ITM Peripheral Identification Register #7 */ + __IM uint32_t PID0; /*!< Offset: 0xFE0 (R/ ) ITM Peripheral Identification Register #0 */ + __IM uint32_t PID1; /*!< Offset: 0xFE4 (R/ ) ITM Peripheral Identification Register #1 */ + __IM uint32_t PID2; /*!< Offset: 0xFE8 (R/ ) ITM Peripheral Identification Register #2 */ + __IM uint32_t PID3; /*!< Offset: 0xFEC (R/ ) ITM Peripheral Identification Register #3 */ + __IM uint32_t CID0; /*!< Offset: 0xFF0 (R/ ) ITM Component Identification Register #0 */ + __IM uint32_t CID1; /*!< Offset: 0xFF4 (R/ ) ITM Component Identification Register #1 */ + __IM uint32_t CID2; /*!< Offset: 0xFF8 (R/ ) ITM Component Identification Register #2 */ + __IM uint32_t CID3; /*!< Offset: 0xFFC (R/ ) ITM Component Identification Register #3 */ +} ITM_Type; + +/* ITM Trace Privilege Register Definitions */ +#define ITM_TPR_PRIVMASK_Pos 0U /*!< ITM TPR: PRIVMASK Position */ +#define ITM_TPR_PRIVMASK_Msk (0xFUL /*<< ITM_TPR_PRIVMASK_Pos*/) /*!< ITM TPR: PRIVMASK Mask */ + +/* ITM Trace Control Register Definitions */ +#define ITM_TCR_BUSY_Pos 23U /*!< ITM TCR: BUSY Position */ +#define ITM_TCR_BUSY_Msk (1UL << ITM_TCR_BUSY_Pos) /*!< ITM TCR: BUSY Mask */ + +#define ITM_TCR_TraceBusID_Pos 16U /*!< ITM TCR: ATBID Position */ +#define ITM_TCR_TraceBusID_Msk (0x7FUL << ITM_TCR_TraceBusID_Pos) /*!< ITM TCR: ATBID Mask */ + +#define ITM_TCR_GTSFREQ_Pos 10U /*!< ITM TCR: Global timestamp frequency Position */ +#define ITM_TCR_GTSFREQ_Msk (3UL << ITM_TCR_GTSFREQ_Pos) /*!< ITM TCR: Global timestamp frequency Mask */ + +#define ITM_TCR_TSPrescale_Pos 8U /*!< ITM TCR: TSPrescale Position */ +#define ITM_TCR_TSPrescale_Msk (3UL << ITM_TCR_TSPrescale_Pos) /*!< ITM TCR: TSPrescale Mask */ + +#define ITM_TCR_SWOENA_Pos 4U /*!< ITM TCR: SWOENA Position */ +#define ITM_TCR_SWOENA_Msk (1UL << ITM_TCR_SWOENA_Pos) /*!< ITM TCR: SWOENA Mask */ + +#define ITM_TCR_DWTENA_Pos 3U /*!< ITM TCR: DWTENA Position */ +#define ITM_TCR_DWTENA_Msk (1UL << ITM_TCR_DWTENA_Pos) /*!< ITM TCR: DWTENA Mask */ + +#define ITM_TCR_SYNCENA_Pos 2U /*!< ITM TCR: SYNCENA Position */ +#define ITM_TCR_SYNCENA_Msk (1UL << ITM_TCR_SYNCENA_Pos) /*!< ITM TCR: SYNCENA Mask */ + +#define ITM_TCR_TSENA_Pos 1U /*!< ITM TCR: TSENA Position */ +#define ITM_TCR_TSENA_Msk (1UL << ITM_TCR_TSENA_Pos) /*!< ITM TCR: TSENA Mask */ + +#define ITM_TCR_ITMENA_Pos 0U /*!< ITM TCR: ITM Enable bit Position */ +#define ITM_TCR_ITMENA_Msk (1UL /*<< ITM_TCR_ITMENA_Pos*/) /*!< ITM TCR: ITM Enable bit Mask */ + +/* ITM Integration Write Register Definitions */ +#define ITM_IWR_ATVALIDM_Pos 0U /*!< ITM IWR: ATVALIDM Position */ +#define ITM_IWR_ATVALIDM_Msk (1UL /*<< ITM_IWR_ATVALIDM_Pos*/) /*!< ITM IWR: ATVALIDM Mask */ + +/* ITM Integration Read Register Definitions */ +#define ITM_IRR_ATREADYM_Pos 0U /*!< ITM IRR: ATREADYM Position */ +#define ITM_IRR_ATREADYM_Msk (1UL /*<< ITM_IRR_ATREADYM_Pos*/) /*!< ITM IRR: ATREADYM Mask */ + +/* ITM Integration Mode Control Register Definitions */ +#define ITM_IMCR_INTEGRATION_Pos 0U /*!< ITM IMCR: INTEGRATION Position */ +#define ITM_IMCR_INTEGRATION_Msk (1UL /*<< ITM_IMCR_INTEGRATION_Pos*/) /*!< ITM IMCR: INTEGRATION Mask */ + +/* ITM Lock Status Register Definitions */ +#define ITM_LSR_ByteAcc_Pos 2U /*!< ITM LSR: ByteAcc Position */ +#define ITM_LSR_ByteAcc_Msk (1UL << ITM_LSR_ByteAcc_Pos) /*!< ITM LSR: ByteAcc Mask */ + +#define ITM_LSR_Access_Pos 1U /*!< ITM LSR: Access Position */ +#define ITM_LSR_Access_Msk (1UL << ITM_LSR_Access_Pos) /*!< ITM LSR: Access Mask */ + +#define ITM_LSR_Present_Pos 0U /*!< ITM LSR: Present Position */ +#define ITM_LSR_Present_Msk (1UL /*<< ITM_LSR_Present_Pos*/) /*!< ITM LSR: Present Mask */ + +/*@}*/ /* end of group CMSIS_ITM */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_DWT Data Watchpoint and Trace (DWT) + \brief Type definitions for the Data Watchpoint and Trace (DWT) + @{ + */ + +/** + \brief Structure type to access the Data Watchpoint and Trace Register (DWT). + */ +typedef struct +{ + __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) Control Register */ + __IOM uint32_t CYCCNT; /*!< Offset: 0x004 (R/W) Cycle Count Register */ + __IOM uint32_t CPICNT; /*!< Offset: 0x008 (R/W) CPI Count Register */ + __IOM uint32_t EXCCNT; /*!< Offset: 0x00C (R/W) Exception Overhead Count Register */ + __IOM uint32_t SLEEPCNT; /*!< Offset: 0x010 (R/W) Sleep Count Register */ + __IOM uint32_t LSUCNT; /*!< Offset: 0x014 (R/W) LSU Count Register */ + __IOM uint32_t FOLDCNT; /*!< Offset: 0x018 (R/W) Folded-instruction Count Register */ + __IM uint32_t PCSR; /*!< Offset: 0x01C (R/ ) Program Counter Sample Register */ + __IOM uint32_t COMP0; /*!< Offset: 0x020 (R/W) Comparator Register 0 */ + __IOM uint32_t MASK0; /*!< Offset: 0x024 (R/W) Mask Register 0 */ + __IOM uint32_t FUNCTION0; /*!< Offset: 0x028 (R/W) Function Register 0 */ + uint32_t RESERVED0[1U]; + __IOM uint32_t COMP1; /*!< Offset: 0x030 (R/W) Comparator Register 1 */ + __IOM uint32_t MASK1; /*!< Offset: 0x034 (R/W) Mask Register 1 */ + __IOM uint32_t FUNCTION1; /*!< Offset: 0x038 (R/W) Function Register 1 */ + uint32_t RESERVED1[1U]; + __IOM uint32_t COMP2; /*!< Offset: 0x040 (R/W) Comparator Register 2 */ + __IOM uint32_t MASK2; /*!< Offset: 0x044 (R/W) Mask Register 2 */ + __IOM uint32_t FUNCTION2; /*!< Offset: 0x048 (R/W) Function Register 2 */ + uint32_t RESERVED2[1U]; + __IOM uint32_t COMP3; /*!< Offset: 0x050 (R/W) Comparator Register 3 */ + __IOM uint32_t MASK3; /*!< Offset: 0x054 (R/W) Mask Register 3 */ + __IOM uint32_t FUNCTION3; /*!< Offset: 0x058 (R/W) Function Register 3 */ +} DWT_Type; + +/* DWT Control Register Definitions */ +#define DWT_CTRL_NUMCOMP_Pos 28U /*!< DWT CTRL: NUMCOMP Position */ +#define DWT_CTRL_NUMCOMP_Msk (0xFUL << DWT_CTRL_NUMCOMP_Pos) /*!< DWT CTRL: NUMCOMP Mask */ + +#define DWT_CTRL_NOTRCPKT_Pos 27U /*!< DWT CTRL: NOTRCPKT Position */ +#define DWT_CTRL_NOTRCPKT_Msk (0x1UL << DWT_CTRL_NOTRCPKT_Pos) /*!< DWT CTRL: NOTRCPKT Mask */ + +#define DWT_CTRL_NOEXTTRIG_Pos 26U /*!< DWT CTRL: NOEXTTRIG Position */ +#define DWT_CTRL_NOEXTTRIG_Msk (0x1UL << DWT_CTRL_NOEXTTRIG_Pos) /*!< DWT CTRL: NOEXTTRIG Mask */ + +#define DWT_CTRL_NOCYCCNT_Pos 25U /*!< DWT CTRL: NOCYCCNT Position */ +#define DWT_CTRL_NOCYCCNT_Msk (0x1UL << DWT_CTRL_NOCYCCNT_Pos) /*!< DWT CTRL: NOCYCCNT Mask */ + +#define DWT_CTRL_NOPRFCNT_Pos 24U /*!< DWT CTRL: NOPRFCNT Position */ +#define DWT_CTRL_NOPRFCNT_Msk (0x1UL << DWT_CTRL_NOPRFCNT_Pos) /*!< DWT CTRL: NOPRFCNT Mask */ + +#define DWT_CTRL_CYCEVTENA_Pos 22U /*!< DWT CTRL: CYCEVTENA Position */ +#define DWT_CTRL_CYCEVTENA_Msk (0x1UL << DWT_CTRL_CYCEVTENA_Pos) /*!< DWT CTRL: CYCEVTENA Mask */ + +#define DWT_CTRL_FOLDEVTENA_Pos 21U /*!< DWT CTRL: FOLDEVTENA Position */ +#define DWT_CTRL_FOLDEVTENA_Msk (0x1UL << DWT_CTRL_FOLDEVTENA_Pos) /*!< DWT CTRL: FOLDEVTENA Mask */ + +#define DWT_CTRL_LSUEVTENA_Pos 20U /*!< DWT CTRL: LSUEVTENA Position */ +#define DWT_CTRL_LSUEVTENA_Msk (0x1UL << DWT_CTRL_LSUEVTENA_Pos) /*!< DWT CTRL: LSUEVTENA Mask */ + +#define DWT_CTRL_SLEEPEVTENA_Pos 19U /*!< DWT CTRL: SLEEPEVTENA Position */ +#define DWT_CTRL_SLEEPEVTENA_Msk (0x1UL << DWT_CTRL_SLEEPEVTENA_Pos) /*!< DWT CTRL: SLEEPEVTENA Mask */ + +#define DWT_CTRL_EXCEVTENA_Pos 18U /*!< DWT CTRL: EXCEVTENA Position */ +#define DWT_CTRL_EXCEVTENA_Msk (0x1UL << DWT_CTRL_EXCEVTENA_Pos) /*!< DWT CTRL: EXCEVTENA Mask */ + +#define DWT_CTRL_CPIEVTENA_Pos 17U /*!< DWT CTRL: CPIEVTENA Position */ +#define DWT_CTRL_CPIEVTENA_Msk (0x1UL << DWT_CTRL_CPIEVTENA_Pos) /*!< DWT CTRL: CPIEVTENA Mask */ + +#define DWT_CTRL_EXCTRCENA_Pos 16U /*!< DWT CTRL: EXCTRCENA Position */ +#define DWT_CTRL_EXCTRCENA_Msk (0x1UL << DWT_CTRL_EXCTRCENA_Pos) /*!< DWT CTRL: EXCTRCENA Mask */ + +#define DWT_CTRL_PCSAMPLENA_Pos 12U /*!< DWT CTRL: PCSAMPLENA Position */ +#define DWT_CTRL_PCSAMPLENA_Msk (0x1UL << DWT_CTRL_PCSAMPLENA_Pos) /*!< DWT CTRL: PCSAMPLENA Mask */ + +#define DWT_CTRL_SYNCTAP_Pos 10U /*!< DWT CTRL: SYNCTAP Position */ +#define DWT_CTRL_SYNCTAP_Msk (0x3UL << DWT_CTRL_SYNCTAP_Pos) /*!< DWT CTRL: SYNCTAP Mask */ + +#define DWT_CTRL_CYCTAP_Pos 9U /*!< DWT CTRL: CYCTAP Position */ +#define DWT_CTRL_CYCTAP_Msk (0x1UL << DWT_CTRL_CYCTAP_Pos) /*!< DWT CTRL: CYCTAP Mask */ + +#define DWT_CTRL_POSTINIT_Pos 5U /*!< DWT CTRL: POSTINIT Position */ +#define DWT_CTRL_POSTINIT_Msk (0xFUL << DWT_CTRL_POSTINIT_Pos) /*!< DWT CTRL: POSTINIT Mask */ + +#define DWT_CTRL_POSTPRESET_Pos 1U /*!< DWT CTRL: POSTPRESET Position */ +#define DWT_CTRL_POSTPRESET_Msk (0xFUL << DWT_CTRL_POSTPRESET_Pos) /*!< DWT CTRL: POSTPRESET Mask */ + +#define DWT_CTRL_CYCCNTENA_Pos 0U /*!< DWT CTRL: CYCCNTENA Position */ +#define DWT_CTRL_CYCCNTENA_Msk (0x1UL /*<< DWT_CTRL_CYCCNTENA_Pos*/) /*!< DWT CTRL: CYCCNTENA Mask */ + +/* DWT CPI Count Register Definitions */ +#define DWT_CPICNT_CPICNT_Pos 0U /*!< DWT CPICNT: CPICNT Position */ +#define DWT_CPICNT_CPICNT_Msk (0xFFUL /*<< DWT_CPICNT_CPICNT_Pos*/) /*!< DWT CPICNT: CPICNT Mask */ + +/* DWT Exception Overhead Count Register Definitions */ +#define DWT_EXCCNT_EXCCNT_Pos 0U /*!< DWT EXCCNT: EXCCNT Position */ +#define DWT_EXCCNT_EXCCNT_Msk (0xFFUL /*<< DWT_EXCCNT_EXCCNT_Pos*/) /*!< DWT EXCCNT: EXCCNT Mask */ + +/* DWT Sleep Count Register Definitions */ +#define DWT_SLEEPCNT_SLEEPCNT_Pos 0U /*!< DWT SLEEPCNT: SLEEPCNT Position */ +#define DWT_SLEEPCNT_SLEEPCNT_Msk (0xFFUL /*<< DWT_SLEEPCNT_SLEEPCNT_Pos*/) /*!< DWT SLEEPCNT: SLEEPCNT Mask */ + +/* DWT LSU Count Register Definitions */ +#define DWT_LSUCNT_LSUCNT_Pos 0U /*!< DWT LSUCNT: LSUCNT Position */ +#define DWT_LSUCNT_LSUCNT_Msk (0xFFUL /*<< DWT_LSUCNT_LSUCNT_Pos*/) /*!< DWT LSUCNT: LSUCNT Mask */ + +/* DWT Folded-instruction Count Register Definitions */ +#define DWT_FOLDCNT_FOLDCNT_Pos 0U /*!< DWT FOLDCNT: FOLDCNT Position */ +#define DWT_FOLDCNT_FOLDCNT_Msk (0xFFUL /*<< DWT_FOLDCNT_FOLDCNT_Pos*/) /*!< DWT FOLDCNT: FOLDCNT Mask */ + +/* DWT Comparator Mask Register Definitions */ +#define DWT_MASK_MASK_Pos 0U /*!< DWT MASK: MASK Position */ +#define DWT_MASK_MASK_Msk (0x1FUL /*<< DWT_MASK_MASK_Pos*/) /*!< DWT MASK: MASK Mask */ + +/* DWT Comparator Function Register Definitions */ +#define DWT_FUNCTION_MATCHED_Pos 24U /*!< DWT FUNCTION: MATCHED Position */ +#define DWT_FUNCTION_MATCHED_Msk (0x1UL << DWT_FUNCTION_MATCHED_Pos) /*!< DWT FUNCTION: MATCHED Mask */ + +#define DWT_FUNCTION_DATAVADDR1_Pos 16U /*!< DWT FUNCTION: DATAVADDR1 Position */ +#define DWT_FUNCTION_DATAVADDR1_Msk (0xFUL << DWT_FUNCTION_DATAVADDR1_Pos) /*!< DWT FUNCTION: DATAVADDR1 Mask */ + +#define DWT_FUNCTION_DATAVADDR0_Pos 12U /*!< DWT FUNCTION: DATAVADDR0 Position */ +#define DWT_FUNCTION_DATAVADDR0_Msk (0xFUL << DWT_FUNCTION_DATAVADDR0_Pos) /*!< DWT FUNCTION: DATAVADDR0 Mask */ + +#define DWT_FUNCTION_DATAVSIZE_Pos 10U /*!< DWT FUNCTION: DATAVSIZE Position */ +#define DWT_FUNCTION_DATAVSIZE_Msk (0x3UL << DWT_FUNCTION_DATAVSIZE_Pos) /*!< DWT FUNCTION: DATAVSIZE Mask */ + +#define DWT_FUNCTION_LNK1ENA_Pos 9U /*!< DWT FUNCTION: LNK1ENA Position */ +#define DWT_FUNCTION_LNK1ENA_Msk (0x1UL << DWT_FUNCTION_LNK1ENA_Pos) /*!< DWT FUNCTION: LNK1ENA Mask */ + +#define DWT_FUNCTION_DATAVMATCH_Pos 8U /*!< DWT FUNCTION: DATAVMATCH Position */ +#define DWT_FUNCTION_DATAVMATCH_Msk (0x1UL << DWT_FUNCTION_DATAVMATCH_Pos) /*!< DWT FUNCTION: DATAVMATCH Mask */ + +#define DWT_FUNCTION_CYCMATCH_Pos 7U /*!< DWT FUNCTION: CYCMATCH Position */ +#define DWT_FUNCTION_CYCMATCH_Msk (0x1UL << DWT_FUNCTION_CYCMATCH_Pos) /*!< DWT FUNCTION: CYCMATCH Mask */ + +#define DWT_FUNCTION_EMITRANGE_Pos 5U /*!< DWT FUNCTION: EMITRANGE Position */ +#define DWT_FUNCTION_EMITRANGE_Msk (0x1UL << DWT_FUNCTION_EMITRANGE_Pos) /*!< DWT FUNCTION: EMITRANGE Mask */ + +#define DWT_FUNCTION_FUNCTION_Pos 0U /*!< DWT FUNCTION: FUNCTION Position */ +#define DWT_FUNCTION_FUNCTION_Msk (0xFUL /*<< DWT_FUNCTION_FUNCTION_Pos*/) /*!< DWT FUNCTION: FUNCTION Mask */ + +/*@}*/ /* end of group CMSIS_DWT */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_TPI Trace Port Interface (TPI) + \brief Type definitions for the Trace Port Interface (TPI) + @{ + */ + +/** + \brief Structure type to access the Trace Port Interface Register (TPI). + */ +typedef struct +{ + __IOM uint32_t SSPSR; /*!< Offset: 0x000 (R/ ) Supported Parallel Port Size Register */ + __IOM uint32_t CSPSR; /*!< Offset: 0x004 (R/W) Current Parallel Port Size Register */ + uint32_t RESERVED0[2U]; + __IOM uint32_t ACPR; /*!< Offset: 0x010 (R/W) Asynchronous Clock Prescaler Register */ + uint32_t RESERVED1[55U]; + __IOM uint32_t SPPR; /*!< Offset: 0x0F0 (R/W) Selected Pin Protocol Register */ + uint32_t RESERVED2[131U]; + __IM uint32_t FFSR; /*!< Offset: 0x300 (R/ ) Formatter and Flush Status Register */ + __IOM uint32_t FFCR; /*!< Offset: 0x304 (R/W) Formatter and Flush Control Register */ + __IM uint32_t FSCR; /*!< Offset: 0x308 (R/ ) Formatter Synchronization Counter Register */ + uint32_t RESERVED3[759U]; + __IM uint32_t TRIGGER; /*!< Offset: 0xEE8 (R/ ) TRIGGER */ + __IM uint32_t FIFO0; /*!< Offset: 0xEEC (R/ ) Integration ETM Data */ + __IM uint32_t ITATBCTR2; /*!< Offset: 0xEF0 (R/ ) ITATBCTR2 */ + uint32_t RESERVED4[1U]; + __IM uint32_t ITATBCTR0; /*!< Offset: 0xEF8 (R/ ) ITATBCTR0 */ + __IM uint32_t FIFO1; /*!< Offset: 0xEFC (R/ ) Integration ITM Data */ + __IOM uint32_t ITCTRL; /*!< Offset: 0xF00 (R/W) Integration Mode Control */ + uint32_t RESERVED5[39U]; + __IOM uint32_t CLAIMSET; /*!< Offset: 0xFA0 (R/W) Claim tag set */ + __IOM uint32_t CLAIMCLR; /*!< Offset: 0xFA4 (R/W) Claim tag clear */ + uint32_t RESERVED7[8U]; + __IM uint32_t DEVID; /*!< Offset: 0xFC8 (R/ ) TPIU_DEVID */ + __IM uint32_t DEVTYPE; /*!< Offset: 0xFCC (R/ ) TPIU_DEVTYPE */ +} TPI_Type; + +/* TPI Asynchronous Clock Prescaler Register Definitions */ +#define TPI_ACPR_PRESCALER_Pos 0U /*!< TPI ACPR: PRESCALER Position */ +#define TPI_ACPR_PRESCALER_Msk (0x1FFFUL /*<< TPI_ACPR_PRESCALER_Pos*/) /*!< TPI ACPR: PRESCALER Mask */ + +/* TPI Selected Pin Protocol Register Definitions */ +#define TPI_SPPR_TXMODE_Pos 0U /*!< TPI SPPR: TXMODE Position */ +#define TPI_SPPR_TXMODE_Msk (0x3UL /*<< TPI_SPPR_TXMODE_Pos*/) /*!< TPI SPPR: TXMODE Mask */ + +/* TPI Formatter and Flush Status Register Definitions */ +#define TPI_FFSR_FtNonStop_Pos 3U /*!< TPI FFSR: FtNonStop Position */ +#define TPI_FFSR_FtNonStop_Msk (0x1UL << TPI_FFSR_FtNonStop_Pos) /*!< TPI FFSR: FtNonStop Mask */ + +#define TPI_FFSR_TCPresent_Pos 2U /*!< TPI FFSR: TCPresent Position */ +#define TPI_FFSR_TCPresent_Msk (0x1UL << TPI_FFSR_TCPresent_Pos) /*!< TPI FFSR: TCPresent Mask */ + +#define TPI_FFSR_FtStopped_Pos 1U /*!< TPI FFSR: FtStopped Position */ +#define TPI_FFSR_FtStopped_Msk (0x1UL << TPI_FFSR_FtStopped_Pos) /*!< TPI FFSR: FtStopped Mask */ + +#define TPI_FFSR_FlInProg_Pos 0U /*!< TPI FFSR: FlInProg Position */ +#define TPI_FFSR_FlInProg_Msk (0x1UL /*<< TPI_FFSR_FlInProg_Pos*/) /*!< TPI FFSR: FlInProg Mask */ + +/* TPI Formatter and Flush Control Register Definitions */ +#define TPI_FFCR_TrigIn_Pos 8U /*!< TPI FFCR: TrigIn Position */ +#define TPI_FFCR_TrigIn_Msk (0x1UL << TPI_FFCR_TrigIn_Pos) /*!< TPI FFCR: TrigIn Mask */ + +#define TPI_FFCR_EnFCont_Pos 1U /*!< TPI FFCR: EnFCont Position */ +#define TPI_FFCR_EnFCont_Msk (0x1UL << TPI_FFCR_EnFCont_Pos) /*!< TPI FFCR: EnFCont Mask */ + +/* TPI TRIGGER Register Definitions */ +#define TPI_TRIGGER_TRIGGER_Pos 0U /*!< TPI TRIGGER: TRIGGER Position */ +#define TPI_TRIGGER_TRIGGER_Msk (0x1UL /*<< TPI_TRIGGER_TRIGGER_Pos*/) /*!< TPI TRIGGER: TRIGGER Mask */ + +/* TPI Integration ETM Data Register Definitions (FIFO0) */ +#define TPI_FIFO0_ITM_ATVALID_Pos 29U /*!< TPI FIFO0: ITM_ATVALID Position */ +#define TPI_FIFO0_ITM_ATVALID_Msk (0x3UL << TPI_FIFO0_ITM_ATVALID_Pos) /*!< TPI FIFO0: ITM_ATVALID Mask */ + +#define TPI_FIFO0_ITM_bytecount_Pos 27U /*!< TPI FIFO0: ITM_bytecount Position */ +#define TPI_FIFO0_ITM_bytecount_Msk (0x3UL << TPI_FIFO0_ITM_bytecount_Pos) /*!< TPI FIFO0: ITM_bytecount Mask */ + +#define TPI_FIFO0_ETM_ATVALID_Pos 26U /*!< TPI FIFO0: ETM_ATVALID Position */ +#define TPI_FIFO0_ETM_ATVALID_Msk (0x3UL << TPI_FIFO0_ETM_ATVALID_Pos) /*!< TPI FIFO0: ETM_ATVALID Mask */ + +#define TPI_FIFO0_ETM_bytecount_Pos 24U /*!< TPI FIFO0: ETM_bytecount Position */ +#define TPI_FIFO0_ETM_bytecount_Msk (0x3UL << TPI_FIFO0_ETM_bytecount_Pos) /*!< TPI FIFO0: ETM_bytecount Mask */ + +#define TPI_FIFO0_ETM2_Pos 16U /*!< TPI FIFO0: ETM2 Position */ +#define TPI_FIFO0_ETM2_Msk (0xFFUL << TPI_FIFO0_ETM2_Pos) /*!< TPI FIFO0: ETM2 Mask */ + +#define TPI_FIFO0_ETM1_Pos 8U /*!< TPI FIFO0: ETM1 Position */ +#define TPI_FIFO0_ETM1_Msk (0xFFUL << TPI_FIFO0_ETM1_Pos) /*!< TPI FIFO0: ETM1 Mask */ + +#define TPI_FIFO0_ETM0_Pos 0U /*!< TPI FIFO0: ETM0 Position */ +#define TPI_FIFO0_ETM0_Msk (0xFFUL /*<< TPI_FIFO0_ETM0_Pos*/) /*!< TPI FIFO0: ETM0 Mask */ + +/* TPI ITATBCTR2 Register Definitions */ +#define TPI_ITATBCTR2_ATREADY_Pos 0U /*!< TPI ITATBCTR2: ATREADY Position */ +#define TPI_ITATBCTR2_ATREADY_Msk (0x1UL /*<< TPI_ITATBCTR2_ATREADY_Pos*/) /*!< TPI ITATBCTR2: ATREADY Mask */ + +/* TPI Integration ITM Data Register Definitions (FIFO1) */ +#define TPI_FIFO1_ITM_ATVALID_Pos 29U /*!< TPI FIFO1: ITM_ATVALID Position */ +#define TPI_FIFO1_ITM_ATVALID_Msk (0x3UL << TPI_FIFO1_ITM_ATVALID_Pos) /*!< TPI FIFO1: ITM_ATVALID Mask */ + +#define TPI_FIFO1_ITM_bytecount_Pos 27U /*!< TPI FIFO1: ITM_bytecount Position */ +#define TPI_FIFO1_ITM_bytecount_Msk (0x3UL << TPI_FIFO1_ITM_bytecount_Pos) /*!< TPI FIFO1: ITM_bytecount Mask */ + +#define TPI_FIFO1_ETM_ATVALID_Pos 26U /*!< TPI FIFO1: ETM_ATVALID Position */ +#define TPI_FIFO1_ETM_ATVALID_Msk (0x3UL << TPI_FIFO1_ETM_ATVALID_Pos) /*!< TPI FIFO1: ETM_ATVALID Mask */ + +#define TPI_FIFO1_ETM_bytecount_Pos 24U /*!< TPI FIFO1: ETM_bytecount Position */ +#define TPI_FIFO1_ETM_bytecount_Msk (0x3UL << TPI_FIFO1_ETM_bytecount_Pos) /*!< TPI FIFO1: ETM_bytecount Mask */ + +#define TPI_FIFO1_ITM2_Pos 16U /*!< TPI FIFO1: ITM2 Position */ +#define TPI_FIFO1_ITM2_Msk (0xFFUL << TPI_FIFO1_ITM2_Pos) /*!< TPI FIFO1: ITM2 Mask */ + +#define TPI_FIFO1_ITM1_Pos 8U /*!< TPI FIFO1: ITM1 Position */ +#define TPI_FIFO1_ITM1_Msk (0xFFUL << TPI_FIFO1_ITM1_Pos) /*!< TPI FIFO1: ITM1 Mask */ + +#define TPI_FIFO1_ITM0_Pos 0U /*!< TPI FIFO1: ITM0 Position */ +#define TPI_FIFO1_ITM0_Msk (0xFFUL /*<< TPI_FIFO1_ITM0_Pos*/) /*!< TPI FIFO1: ITM0 Mask */ + +/* TPI ITATBCTR0 Register Definitions */ +#define TPI_ITATBCTR0_ATREADY_Pos 0U /*!< TPI ITATBCTR0: ATREADY Position */ +#define TPI_ITATBCTR0_ATREADY_Msk (0x1UL /*<< TPI_ITATBCTR0_ATREADY_Pos*/) /*!< TPI ITATBCTR0: ATREADY Mask */ + +/* TPI Integration Mode Control Register Definitions */ +#define TPI_ITCTRL_Mode_Pos 0U /*!< TPI ITCTRL: Mode Position */ +#define TPI_ITCTRL_Mode_Msk (0x1UL /*<< TPI_ITCTRL_Mode_Pos*/) /*!< TPI ITCTRL: Mode Mask */ + +/* TPI DEVID Register Definitions */ +#define TPI_DEVID_NRZVALID_Pos 11U /*!< TPI DEVID: NRZVALID Position */ +#define TPI_DEVID_NRZVALID_Msk (0x1UL << TPI_DEVID_NRZVALID_Pos) /*!< TPI DEVID: NRZVALID Mask */ + +#define TPI_DEVID_MANCVALID_Pos 10U /*!< TPI DEVID: MANCVALID Position */ +#define TPI_DEVID_MANCVALID_Msk (0x1UL << TPI_DEVID_MANCVALID_Pos) /*!< TPI DEVID: MANCVALID Mask */ + +#define TPI_DEVID_PTINVALID_Pos 9U /*!< TPI DEVID: PTINVALID Position */ +#define TPI_DEVID_PTINVALID_Msk (0x1UL << TPI_DEVID_PTINVALID_Pos) /*!< TPI DEVID: PTINVALID Mask */ + +#define TPI_DEVID_MinBufSz_Pos 6U /*!< TPI DEVID: MinBufSz Position */ +#define TPI_DEVID_MinBufSz_Msk (0x7UL << TPI_DEVID_MinBufSz_Pos) /*!< TPI DEVID: MinBufSz Mask */ + +#define TPI_DEVID_AsynClkIn_Pos 5U /*!< TPI DEVID: AsynClkIn Position */ +#define TPI_DEVID_AsynClkIn_Msk (0x1UL << TPI_DEVID_AsynClkIn_Pos) /*!< TPI DEVID: AsynClkIn Mask */ + +#define TPI_DEVID_NrTraceInput_Pos 0U /*!< TPI DEVID: NrTraceInput Position */ +#define TPI_DEVID_NrTraceInput_Msk (0x1FUL /*<< TPI_DEVID_NrTraceInput_Pos*/) /*!< TPI DEVID: NrTraceInput Mask */ + +/* TPI DEVTYPE Register Definitions */ +#define TPI_DEVTYPE_MajorType_Pos 4U /*!< TPI DEVTYPE: MajorType Position */ +#define TPI_DEVTYPE_MajorType_Msk (0xFUL << TPI_DEVTYPE_MajorType_Pos) /*!< TPI DEVTYPE: MajorType Mask */ + +#define TPI_DEVTYPE_SubType_Pos 0U /*!< TPI DEVTYPE: SubType Position */ +#define TPI_DEVTYPE_SubType_Msk (0xFUL /*<< TPI_DEVTYPE_SubType_Pos*/) /*!< TPI DEVTYPE: SubType Mask */ + +/*@}*/ /* end of group CMSIS_TPI */ + + +#if (__MPU_PRESENT == 1U) +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_MPU Memory Protection Unit (MPU) + \brief Type definitions for the Memory Protection Unit (MPU) + @{ + */ + +/** + \brief Structure type to access the Memory Protection Unit (MPU). + */ +typedef struct +{ + __IM uint32_t TYPE; /*!< Offset: 0x000 (R/ ) MPU Type Register */ + __IOM uint32_t CTRL; /*!< Offset: 0x004 (R/W) MPU Control Register */ + __IOM uint32_t RNR; /*!< Offset: 0x008 (R/W) MPU Region RNRber Register */ + __IOM uint32_t RBAR; /*!< Offset: 0x00C (R/W) MPU Region Base Address Register */ + __IOM uint32_t RASR; /*!< Offset: 0x010 (R/W) MPU Region Attribute and Size Register */ + __IOM uint32_t RBAR_A1; /*!< Offset: 0x014 (R/W) MPU Alias 1 Region Base Address Register */ + __IOM uint32_t RASR_A1; /*!< Offset: 0x018 (R/W) MPU Alias 1 Region Attribute and Size Register */ + __IOM uint32_t RBAR_A2; /*!< Offset: 0x01C (R/W) MPU Alias 2 Region Base Address Register */ + __IOM uint32_t RASR_A2; /*!< Offset: 0x020 (R/W) MPU Alias 2 Region Attribute and Size Register */ + __IOM uint32_t RBAR_A3; /*!< Offset: 0x024 (R/W) MPU Alias 3 Region Base Address Register */ + __IOM uint32_t RASR_A3; /*!< Offset: 0x028 (R/W) MPU Alias 3 Region Attribute and Size Register */ +} MPU_Type; + +/* MPU Type Register Definitions */ +#define MPU_TYPE_IREGION_Pos 16U /*!< MPU TYPE: IREGION Position */ +#define MPU_TYPE_IREGION_Msk (0xFFUL << MPU_TYPE_IREGION_Pos) /*!< MPU TYPE: IREGION Mask */ + +#define MPU_TYPE_DREGION_Pos 8U /*!< MPU TYPE: DREGION Position */ +#define MPU_TYPE_DREGION_Msk (0xFFUL << MPU_TYPE_DREGION_Pos) /*!< MPU TYPE: DREGION Mask */ + +#define MPU_TYPE_SEPARATE_Pos 0U /*!< MPU TYPE: SEPARATE Position */ +#define MPU_TYPE_SEPARATE_Msk (1UL /*<< MPU_TYPE_SEPARATE_Pos*/) /*!< MPU TYPE: SEPARATE Mask */ + +/* MPU Control Register Definitions */ +#define MPU_CTRL_PRIVDEFENA_Pos 2U /*!< MPU CTRL: PRIVDEFENA Position */ +#define MPU_CTRL_PRIVDEFENA_Msk (1UL << MPU_CTRL_PRIVDEFENA_Pos) /*!< MPU CTRL: PRIVDEFENA Mask */ + +#define MPU_CTRL_HFNMIENA_Pos 1U /*!< MPU CTRL: HFNMIENA Position */ +#define MPU_CTRL_HFNMIENA_Msk (1UL << MPU_CTRL_HFNMIENA_Pos) /*!< MPU CTRL: HFNMIENA Mask */ + +#define MPU_CTRL_ENABLE_Pos 0U /*!< MPU CTRL: ENABLE Position */ +#define MPU_CTRL_ENABLE_Msk (1UL /*<< MPU_CTRL_ENABLE_Pos*/) /*!< MPU CTRL: ENABLE Mask */ + +/* MPU Region Number Register Definitions */ +#define MPU_RNR_REGION_Pos 0U /*!< MPU RNR: REGION Position */ +#define MPU_RNR_REGION_Msk (0xFFUL /*<< MPU_RNR_REGION_Pos*/) /*!< MPU RNR: REGION Mask */ + +/* MPU Region Base Address Register Definitions */ +#define MPU_RBAR_ADDR_Pos 5U /*!< MPU RBAR: ADDR Position */ +#define MPU_RBAR_ADDR_Msk (0x7FFFFFFUL << MPU_RBAR_ADDR_Pos) /*!< MPU RBAR: ADDR Mask */ + +#define MPU_RBAR_VALID_Pos 4U /*!< MPU RBAR: VALID Position */ +#define MPU_RBAR_VALID_Msk (1UL << MPU_RBAR_VALID_Pos) /*!< MPU RBAR: VALID Mask */ + +#define MPU_RBAR_REGION_Pos 0U /*!< MPU RBAR: REGION Position */ +#define MPU_RBAR_REGION_Msk (0xFUL /*<< MPU_RBAR_REGION_Pos*/) /*!< MPU RBAR: REGION Mask */ + +/* MPU Region Attribute and Size Register Definitions */ +#define MPU_RASR_ATTRS_Pos 16U /*!< MPU RASR: MPU Region Attribute field Position */ +#define MPU_RASR_ATTRS_Msk (0xFFFFUL << MPU_RASR_ATTRS_Pos) /*!< MPU RASR: MPU Region Attribute field Mask */ + +#define MPU_RASR_XN_Pos 28U /*!< MPU RASR: ATTRS.XN Position */ +#define MPU_RASR_XN_Msk (1UL << MPU_RASR_XN_Pos) /*!< MPU RASR: ATTRS.XN Mask */ + +#define MPU_RASR_AP_Pos 24U /*!< MPU RASR: ATTRS.AP Position */ +#define MPU_RASR_AP_Msk (0x7UL << MPU_RASR_AP_Pos) /*!< MPU RASR: ATTRS.AP Mask */ + +#define MPU_RASR_TEX_Pos 19U /*!< MPU RASR: ATTRS.TEX Position */ +#define MPU_RASR_TEX_Msk (0x7UL << MPU_RASR_TEX_Pos) /*!< MPU RASR: ATTRS.TEX Mask */ + +#define MPU_RASR_S_Pos 18U /*!< MPU RASR: ATTRS.S Position */ +#define MPU_RASR_S_Msk (1UL << MPU_RASR_S_Pos) /*!< MPU RASR: ATTRS.S Mask */ + +#define MPU_RASR_C_Pos 17U /*!< MPU RASR: ATTRS.C Position */ +#define MPU_RASR_C_Msk (1UL << MPU_RASR_C_Pos) /*!< MPU RASR: ATTRS.C Mask */ + +#define MPU_RASR_B_Pos 16U /*!< MPU RASR: ATTRS.B Position */ +#define MPU_RASR_B_Msk (1UL << MPU_RASR_B_Pos) /*!< MPU RASR: ATTRS.B Mask */ + +#define MPU_RASR_SRD_Pos 8U /*!< MPU RASR: Sub-Region Disable Position */ +#define MPU_RASR_SRD_Msk (0xFFUL << MPU_RASR_SRD_Pos) /*!< MPU RASR: Sub-Region Disable Mask */ + +#define MPU_RASR_SIZE_Pos 1U /*!< MPU RASR: Region Size Field Position */ +#define MPU_RASR_SIZE_Msk (0x1FUL << MPU_RASR_SIZE_Pos) /*!< MPU RASR: Region Size Field Mask */ + +#define MPU_RASR_ENABLE_Pos 0U /*!< MPU RASR: Region enable bit Position */ +#define MPU_RASR_ENABLE_Msk (1UL /*<< MPU_RASR_ENABLE_Pos*/) /*!< MPU RASR: Region enable bit Disable Mask */ + +/*@} end of group CMSIS_MPU */ +#endif + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_CoreDebug Core Debug Registers (CoreDebug) + \brief Type definitions for the Core Debug Registers + @{ + */ + +/** + \brief Structure type to access the Core Debug Register (CoreDebug). + */ +typedef struct +{ + __IOM uint32_t DHCSR; /*!< Offset: 0x000 (R/W) Debug Halting Control and Status Register */ + __OM uint32_t DCRSR; /*!< Offset: 0x004 ( /W) Debug Core Register Selector Register */ + __IOM uint32_t DCRDR; /*!< Offset: 0x008 (R/W) Debug Core Register Data Register */ + __IOM uint32_t DEMCR; /*!< Offset: 0x00C (R/W) Debug Exception and Monitor Control Register */ +} CoreDebug_Type; + +/* Debug Halting Control and Status Register Definitions */ +#define CoreDebug_DHCSR_DBGKEY_Pos 16U /*!< CoreDebug DHCSR: DBGKEY Position */ +#define CoreDebug_DHCSR_DBGKEY_Msk (0xFFFFUL << CoreDebug_DHCSR_DBGKEY_Pos) /*!< CoreDebug DHCSR: DBGKEY Mask */ + +#define CoreDebug_DHCSR_S_RESET_ST_Pos 25U /*!< CoreDebug DHCSR: S_RESET_ST Position */ +#define CoreDebug_DHCSR_S_RESET_ST_Msk (1UL << CoreDebug_DHCSR_S_RESET_ST_Pos) /*!< CoreDebug DHCSR: S_RESET_ST Mask */ + +#define CoreDebug_DHCSR_S_RETIRE_ST_Pos 24U /*!< CoreDebug DHCSR: S_RETIRE_ST Position */ +#define CoreDebug_DHCSR_S_RETIRE_ST_Msk (1UL << CoreDebug_DHCSR_S_RETIRE_ST_Pos) /*!< CoreDebug DHCSR: S_RETIRE_ST Mask */ + +#define CoreDebug_DHCSR_S_LOCKUP_Pos 19U /*!< CoreDebug DHCSR: S_LOCKUP Position */ +#define CoreDebug_DHCSR_S_LOCKUP_Msk (1UL << CoreDebug_DHCSR_S_LOCKUP_Pos) /*!< CoreDebug DHCSR: S_LOCKUP Mask */ + +#define CoreDebug_DHCSR_S_SLEEP_Pos 18U /*!< CoreDebug DHCSR: S_SLEEP Position */ +#define CoreDebug_DHCSR_S_SLEEP_Msk (1UL << CoreDebug_DHCSR_S_SLEEP_Pos) /*!< CoreDebug DHCSR: S_SLEEP Mask */ + +#define CoreDebug_DHCSR_S_HALT_Pos 17U /*!< CoreDebug DHCSR: S_HALT Position */ +#define CoreDebug_DHCSR_S_HALT_Msk (1UL << CoreDebug_DHCSR_S_HALT_Pos) /*!< CoreDebug DHCSR: S_HALT Mask */ + +#define CoreDebug_DHCSR_S_REGRDY_Pos 16U /*!< CoreDebug DHCSR: S_REGRDY Position */ +#define CoreDebug_DHCSR_S_REGRDY_Msk (1UL << CoreDebug_DHCSR_S_REGRDY_Pos) /*!< CoreDebug DHCSR: S_REGRDY Mask */ + +#define CoreDebug_DHCSR_C_SNAPSTALL_Pos 5U /*!< CoreDebug DHCSR: C_SNAPSTALL Position */ +#define CoreDebug_DHCSR_C_SNAPSTALL_Msk (1UL << CoreDebug_DHCSR_C_SNAPSTALL_Pos) /*!< CoreDebug DHCSR: C_SNAPSTALL Mask */ + +#define CoreDebug_DHCSR_C_MASKINTS_Pos 3U /*!< CoreDebug DHCSR: C_MASKINTS Position */ +#define CoreDebug_DHCSR_C_MASKINTS_Msk (1UL << CoreDebug_DHCSR_C_MASKINTS_Pos) /*!< CoreDebug DHCSR: C_MASKINTS Mask */ + +#define CoreDebug_DHCSR_C_STEP_Pos 2U /*!< CoreDebug DHCSR: C_STEP Position */ +#define CoreDebug_DHCSR_C_STEP_Msk (1UL << CoreDebug_DHCSR_C_STEP_Pos) /*!< CoreDebug DHCSR: C_STEP Mask */ + +#define CoreDebug_DHCSR_C_HALT_Pos 1U /*!< CoreDebug DHCSR: C_HALT Position */ +#define CoreDebug_DHCSR_C_HALT_Msk (1UL << CoreDebug_DHCSR_C_HALT_Pos) /*!< CoreDebug DHCSR: C_HALT Mask */ + +#define CoreDebug_DHCSR_C_DEBUGEN_Pos 0U /*!< CoreDebug DHCSR: C_DEBUGEN Position */ +#define CoreDebug_DHCSR_C_DEBUGEN_Msk (1UL /*<< CoreDebug_DHCSR_C_DEBUGEN_Pos*/) /*!< CoreDebug DHCSR: C_DEBUGEN Mask */ + +/* Debug Core Register Selector Register Definitions */ +#define CoreDebug_DCRSR_REGWnR_Pos 16U /*!< CoreDebug DCRSR: REGWnR Position */ +#define CoreDebug_DCRSR_REGWnR_Msk (1UL << CoreDebug_DCRSR_REGWnR_Pos) /*!< CoreDebug DCRSR: REGWnR Mask */ + +#define CoreDebug_DCRSR_REGSEL_Pos 0U /*!< CoreDebug DCRSR: REGSEL Position */ +#define CoreDebug_DCRSR_REGSEL_Msk (0x1FUL /*<< CoreDebug_DCRSR_REGSEL_Pos*/) /*!< CoreDebug DCRSR: REGSEL Mask */ + +/* Debug Exception and Monitor Control Register Definitions */ +#define CoreDebug_DEMCR_TRCENA_Pos 24U /*!< CoreDebug DEMCR: TRCENA Position */ +#define CoreDebug_DEMCR_TRCENA_Msk (1UL << CoreDebug_DEMCR_TRCENA_Pos) /*!< CoreDebug DEMCR: TRCENA Mask */ + +#define CoreDebug_DEMCR_MON_REQ_Pos 19U /*!< CoreDebug DEMCR: MON_REQ Position */ +#define CoreDebug_DEMCR_MON_REQ_Msk (1UL << CoreDebug_DEMCR_MON_REQ_Pos) /*!< CoreDebug DEMCR: MON_REQ Mask */ + +#define CoreDebug_DEMCR_MON_STEP_Pos 18U /*!< CoreDebug DEMCR: MON_STEP Position */ +#define CoreDebug_DEMCR_MON_STEP_Msk (1UL << CoreDebug_DEMCR_MON_STEP_Pos) /*!< CoreDebug DEMCR: MON_STEP Mask */ + +#define CoreDebug_DEMCR_MON_PEND_Pos 17U /*!< CoreDebug DEMCR: MON_PEND Position */ +#define CoreDebug_DEMCR_MON_PEND_Msk (1UL << CoreDebug_DEMCR_MON_PEND_Pos) /*!< CoreDebug DEMCR: MON_PEND Mask */ + +#define CoreDebug_DEMCR_MON_EN_Pos 16U /*!< CoreDebug DEMCR: MON_EN Position */ +#define CoreDebug_DEMCR_MON_EN_Msk (1UL << CoreDebug_DEMCR_MON_EN_Pos) /*!< CoreDebug DEMCR: MON_EN Mask */ + +#define CoreDebug_DEMCR_VC_HARDERR_Pos 10U /*!< CoreDebug DEMCR: VC_HARDERR Position */ +#define CoreDebug_DEMCR_VC_HARDERR_Msk (1UL << CoreDebug_DEMCR_VC_HARDERR_Pos) /*!< CoreDebug DEMCR: VC_HARDERR Mask */ + +#define CoreDebug_DEMCR_VC_INTERR_Pos 9U /*!< CoreDebug DEMCR: VC_INTERR Position */ +#define CoreDebug_DEMCR_VC_INTERR_Msk (1UL << CoreDebug_DEMCR_VC_INTERR_Pos) /*!< CoreDebug DEMCR: VC_INTERR Mask */ + +#define CoreDebug_DEMCR_VC_BUSERR_Pos 8U /*!< CoreDebug DEMCR: VC_BUSERR Position */ +#define CoreDebug_DEMCR_VC_BUSERR_Msk (1UL << CoreDebug_DEMCR_VC_BUSERR_Pos) /*!< CoreDebug DEMCR: VC_BUSERR Mask */ + +#define CoreDebug_DEMCR_VC_STATERR_Pos 7U /*!< CoreDebug DEMCR: VC_STATERR Position */ +#define CoreDebug_DEMCR_VC_STATERR_Msk (1UL << CoreDebug_DEMCR_VC_STATERR_Pos) /*!< CoreDebug DEMCR: VC_STATERR Mask */ + +#define CoreDebug_DEMCR_VC_CHKERR_Pos 6U /*!< CoreDebug DEMCR: VC_CHKERR Position */ +#define CoreDebug_DEMCR_VC_CHKERR_Msk (1UL << CoreDebug_DEMCR_VC_CHKERR_Pos) /*!< CoreDebug DEMCR: VC_CHKERR Mask */ + +#define CoreDebug_DEMCR_VC_NOCPERR_Pos 5U /*!< CoreDebug DEMCR: VC_NOCPERR Position */ +#define CoreDebug_DEMCR_VC_NOCPERR_Msk (1UL << CoreDebug_DEMCR_VC_NOCPERR_Pos) /*!< CoreDebug DEMCR: VC_NOCPERR Mask */ + +#define CoreDebug_DEMCR_VC_MMERR_Pos 4U /*!< CoreDebug DEMCR: VC_MMERR Position */ +#define CoreDebug_DEMCR_VC_MMERR_Msk (1UL << CoreDebug_DEMCR_VC_MMERR_Pos) /*!< CoreDebug DEMCR: VC_MMERR Mask */ + +#define CoreDebug_DEMCR_VC_CORERESET_Pos 0U /*!< CoreDebug DEMCR: VC_CORERESET Position */ +#define CoreDebug_DEMCR_VC_CORERESET_Msk (1UL /*<< CoreDebug_DEMCR_VC_CORERESET_Pos*/) /*!< CoreDebug DEMCR: VC_CORERESET Mask */ + +/*@} end of group CMSIS_CoreDebug */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_core_bitfield Core register bit field macros + \brief Macros for use with bit field definitions (xxx_Pos, xxx_Msk). + @{ + */ + +/** + \brief Mask and shift a bit field value for use in a register bit range. + \param[in] field Name of the register bit field. + \param[in] value Value of the bit field. + \return Masked and shifted value. +*/ +#define _VAL2FLD(field, value) ((value << field ## _Pos) & field ## _Msk) + +/** + \brief Mask and shift a register value to extract a bit filed value. + \param[in] field Name of the register bit field. + \param[in] value Value of register. + \return Masked and shifted bit field value. +*/ +#define _FLD2VAL(field, value) ((value & field ## _Msk) >> field ## _Pos) + +/*@} end of group CMSIS_core_bitfield */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_core_base Core Definitions + \brief Definitions for base addresses, unions, and structures. + @{ + */ + +/* Memory mapping of Cortex-M3 Hardware */ +#define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */ +#define ITM_BASE (0xE0000000UL) /*!< ITM Base Address */ +#define DWT_BASE (0xE0001000UL) /*!< DWT Base Address */ +#define TPI_BASE (0xE0040000UL) /*!< TPI Base Address */ +#define CoreDebug_BASE (0xE000EDF0UL) /*!< Core Debug Base Address */ +#define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */ +#define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */ +#define SCB_BASE (SCS_BASE + 0x0D00UL) /*!< System Control Block Base Address */ + +#define SCnSCB ((SCnSCB_Type *) SCS_BASE ) /*!< System control Register not in SCB */ +#define SCB ((SCB_Type *) SCB_BASE ) /*!< SCB configuration struct */ +#define SysTick ((SysTick_Type *) SysTick_BASE ) /*!< SysTick configuration struct */ +#define NVIC ((NVIC_Type *) NVIC_BASE ) /*!< NVIC configuration struct */ +#define ITM ((ITM_Type *) ITM_BASE ) /*!< ITM configuration struct */ +#define DWT ((DWT_Type *) DWT_BASE ) /*!< DWT configuration struct */ +#define TPI ((TPI_Type *) TPI_BASE ) /*!< TPI configuration struct */ +#define CoreDebug ((CoreDebug_Type *) CoreDebug_BASE) /*!< Core Debug configuration struct */ + +#if (__MPU_PRESENT == 1U) +#define MPU_BASE (SCS_BASE + 0x0D90UL) /*!< Memory Protection Unit */ +#define MPU ((MPU_Type *) MPU_BASE ) /*!< Memory Protection Unit */ +#endif + +/*@} */ + + + +/******************************************************************************* + * Hardware Abstraction Layer + Core Function Interface contains: + - Core NVIC Functions + - Core SysTick Functions + - Core Debug Functions + - Core Register Access Functions + ******************************************************************************/ +/** + \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference +*/ + + + +/* ########################## NVIC functions #################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_NVICFunctions NVIC Functions + \brief Functions that manage interrupts and exceptions via the NVIC. + @{ + */ + +/** + \brief Set Priority Grouping + \details Sets the priority grouping field using the required unlock sequence. + The parameter PriorityGroup is assigned to the field SCB->AIRCR [10:8] PRIGROUP field. + Only values from 0..7 are used. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set. + \param [in] PriorityGroup Priority grouping field. + */ +__STATIC_INLINE void NVIC_SetPriorityGrouping(uint32_t PriorityGroup) +{ + uint32_t reg_value; + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + + reg_value = SCB->AIRCR; /* read old register configuration */ + reg_value &= ~((uint32_t)(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk)); /* clear bits to change */ + reg_value = (reg_value | + ((uint32_t)0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | + (PriorityGroupTmp << 8U)); /* Insert write key and priorty group */ + SCB->AIRCR = reg_value; +} + + +/** + \brief Get Priority Grouping + \details Reads the priority grouping field from the NVIC Interrupt Controller. + \return Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field). + */ +__STATIC_INLINE uint32_t NVIC_GetPriorityGrouping(void) +{ + return ((uint32_t)((SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos)); +} + + +/** + \brief Enable External Interrupt + \details Enables a device-specific interrupt in the NVIC interrupt controller. + \param [in] IRQn External interrupt number. Value cannot be negative. + */ +__STATIC_INLINE void NVIC_EnableIRQ(IRQn_Type IRQn) +{ + NVIC->ISER[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL)); +} + + +/** + \brief Disable External Interrupt + \details Disables a device-specific interrupt in the NVIC interrupt controller. + \param [in] IRQn External interrupt number. Value cannot be negative. + */ +__STATIC_INLINE void NVIC_DisableIRQ(IRQn_Type IRQn) +{ + NVIC->ICER[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL)); +} + + +/** + \brief Get Pending Interrupt + \details Reads the pending register in the NVIC and returns the pending bit for the specified interrupt. + \param [in] IRQn Interrupt number. + \return 0 Interrupt status is not pending. + \return 1 Interrupt status is pending. + */ +__STATIC_INLINE uint32_t NVIC_GetPendingIRQ(IRQn_Type IRQn) +{ + return ((uint32_t)(((NVIC->ISPR[(((uint32_t)(int32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); +} + + +/** + \brief Set Pending Interrupt + \details Sets the pending bit of an external interrupt. + \param [in] IRQn Interrupt number. Value cannot be negative. + */ +__STATIC_INLINE void NVIC_SetPendingIRQ(IRQn_Type IRQn) +{ + NVIC->ISPR[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL)); +} + + +/** + \brief Clear Pending Interrupt + \details Clears the pending bit of an external interrupt. + \param [in] IRQn External interrupt number. Value cannot be negative. + */ +__STATIC_INLINE void NVIC_ClearPendingIRQ(IRQn_Type IRQn) +{ + NVIC->ICPR[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL)); +} + + +/** + \brief Get Active Interrupt + \details Reads the active register in NVIC and returns the active bit. + \param [in] IRQn Interrupt number. + \return 0 Interrupt status is not active. + \return 1 Interrupt status is active. + */ +__STATIC_INLINE uint32_t NVIC_GetActive(IRQn_Type IRQn) +{ + return ((uint32_t)(((NVIC->IABR[(((uint32_t)(int32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); +} + + +/** + \brief Set Interrupt Priority + \details Sets the priority of an interrupt. + \note The priority cannot be set for every core interrupt. + \param [in] IRQn Interrupt number. + \param [in] priority Priority to set. + */ +__STATIC_INLINE void NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority) +{ + if ((int32_t)(IRQn) < 0) + { + SCB->SHP[(((uint32_t)(int32_t)IRQn) & 0xFUL) - 4UL] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); + } + else + { + NVIC->IP[((uint32_t)(int32_t)IRQn)] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); + } +} + + +/** + \brief Get Interrupt Priority + \details Reads the priority of an interrupt. + The interrupt number can be positive to specify an external (device specific) interrupt, + or negative to specify an internal (core) interrupt. + \param [in] IRQn Interrupt number. + \return Interrupt Priority. + Value is aligned automatically to the implemented priority bits of the microcontroller. + */ +__STATIC_INLINE uint32_t NVIC_GetPriority(IRQn_Type IRQn) +{ + + if ((int32_t)(IRQn) < 0) + { + return (((uint32_t)SCB->SHP[(((uint32_t)(int32_t)IRQn) & 0xFUL) - 4UL] >> (8U - __NVIC_PRIO_BITS))); + } + else + { + return (((uint32_t)NVIC->IP[((uint32_t)(int32_t)IRQn)] >> (8U - __NVIC_PRIO_BITS))); + } +} + + +/** + \brief Encode Priority + \details Encodes the priority for an interrupt with the given priority group, + preemptive priority value, and subpriority value. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set. + \param [in] PriorityGroup Used priority group. + \param [in] PreemptPriority Preemptive priority value (starting from 0). + \param [in] SubPriority Subpriority value (starting from 0). + \return Encoded priority. Value can be used in the function \ref NVIC_SetPriority(). + */ +__STATIC_INLINE uint32_t NVIC_EncodePriority(uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority) +{ + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + uint32_t PreemptPriorityBits; + uint32_t SubPriorityBits; + + PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp); + SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS)); + + return ( + ((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) | + ((SubPriority & (uint32_t)((1UL << (SubPriorityBits)) - 1UL))) + ); +} + + +/** + \brief Decode Priority + \details Decodes an interrupt priority value with a given priority group to + preemptive priority value and subpriority value. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS) the smallest possible priority group is set. + \param [in] Priority Priority value, which can be retrieved with the function \ref NVIC_GetPriority(). + \param [in] PriorityGroup Used priority group. + \param [out] pPreemptPriority Preemptive priority value (starting from 0). + \param [out] pSubPriority Subpriority value (starting from 0). + */ +__STATIC_INLINE void NVIC_DecodePriority(uint32_t Priority, uint32_t PriorityGroup, uint32_t *const pPreemptPriority, uint32_t *const pSubPriority) +{ + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + uint32_t PreemptPriorityBits; + uint32_t SubPriorityBits; + + PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp); + SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS)); + + *pPreemptPriority = (Priority >> SubPriorityBits) & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL); + *pSubPriority = (Priority) & (uint32_t)((1UL << (SubPriorityBits)) - 1UL); +} + + +/** + \brief System Reset + \details Initiates a system reset request to reset the MCU. + */ +__STATIC_INLINE void NVIC_SystemReset(void) +{ + __DSB(); /* Ensure all outstanding memory accesses included + buffered write are completed before reset */ + SCB->AIRCR = (uint32_t)((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | + (SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) | + SCB_AIRCR_SYSRESETREQ_Msk); /* Keep priority group unchanged */ + __DSB(); /* Ensure completion of memory access */ + + for (;;) /* wait until reset */ + { + __NOP(); + } +} + +/*@} end of CMSIS_Core_NVICFunctions */ + + + +/* ################################## SysTick function ############################################ */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_SysTickFunctions SysTick Functions + \brief Functions that configure the System. + @{ + */ + +#if (__Vendor_SysTickConfig == 0U) + +/** + \brief System Tick Configuration + \details Initializes the System Timer and its interrupt, and starts the System Tick Timer. + Counter is in free running mode to generate periodic interrupts. + \param [in] ticks Number of ticks between two interrupts. + \return 0 Function succeeded. + \return 1 Function failed. + \note When the variable __Vendor_SysTickConfig is set to 1, then the + function SysTick_Config is not included. In this case, the file device.h + must contain a vendor-specific implementation of this function. + */ +__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks) +{ + if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk) + { + return (1UL); /* Reload value impossible */ + } + + SysTick->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */ + NVIC_SetPriority(SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */ + SysTick->VAL = 0UL; /* Load the SysTick Counter Value */ + SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk | + SysTick_CTRL_TICKINT_Msk | + SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */ + return (0UL); /* Function successful */ +} + +#endif + +/*@} end of CMSIS_Core_SysTickFunctions */ + + + +/* ##################################### Debug In/Output function ########################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_core_DebugFunctions ITM Functions + \brief Functions that access the ITM debug interface. + @{ + */ + +extern volatile int32_t ITM_RxBuffer; /*!< External variable to receive characters. */ +#define ITM_RXBUFFER_EMPTY 0x5AA55AA5U /*!< Value identifying \ref ITM_RxBuffer is ready for next character. */ + + +/** + \brief ITM Send Character + \details Transmits a character via the ITM channel 0, and + \li Just returns when no debugger is connected that has booked the output. + \li Is blocking when a debugger is connected, but the previous character sent has not been transmitted. + \param [in] ch Character to transmit. + \returns Character to transmit. + */ +__STATIC_INLINE uint32_t ITM_SendChar(uint32_t ch) +{ + if (((ITM->TCR & ITM_TCR_ITMENA_Msk) != 0UL) && /* ITM enabled */ + ((ITM->TER & 1UL) != 0UL)) /* ITM Port #0 enabled */ + { + while (ITM->PORT[0U].u32 == 0UL) + { + __NOP(); + } + ITM->PORT[0U].u8 = (uint8_t)ch; + } + return (ch); +} + + +/** + \brief ITM Receive Character + \details Inputs a character via the external variable \ref ITM_RxBuffer. + \return Received character. + \return -1 No character pending. + */ +__STATIC_INLINE int32_t ITM_ReceiveChar(void) +{ + int32_t ch = -1; /* no character available */ + + if (ITM_RxBuffer != ITM_RXBUFFER_EMPTY) + { + ch = ITM_RxBuffer; + ITM_RxBuffer = ITM_RXBUFFER_EMPTY; /* ready for next character */ + } + + return (ch); +} + + +/** + \brief ITM Check Character + \details Checks whether a character is pending for reading in the variable \ref ITM_RxBuffer. + \return 0 No character available. + \return 1 Character available. + */ +__STATIC_INLINE int32_t ITM_CheckChar(void) +{ + + if (ITM_RxBuffer == ITM_RXBUFFER_EMPTY) + { + return (0); /* no character available */ + } + else + { + return (1); /* character available */ + } +} + +/*@} end of CMSIS_core_DebugFunctions */ + + + + +#ifdef __cplusplus +} +#endif + +#endif /* __CORE_CM3_H_DEPENDANT */ + +#endif /* __CMSIS_GENERIC */ diff --git a/bsp/nuvoton/libraries/ma35/CMSIS/Include/core_cm4.h b/bsp/nuvoton/libraries/ma35/CMSIS/Include/core_cm4.h new file mode 100644 index 0000000000..e9d5044f4c --- /dev/null +++ b/bsp/nuvoton/libraries/ma35/CMSIS/Include/core_cm4.h @@ -0,0 +1,1937 @@ +/**************************************************************************//** + * @file core_cm4.h + * @brief CMSIS Cortex-M4 Core Peripheral Access Layer Header File + * @version V4.30 + * @date 20. October 2015 + ******************************************************************************/ +/* Copyright (c) 2009 - 2015 ARM LIMITED + + All rights reserved. + Redistribution and use in source and binary forms, with or without + modification, are permitted provided that the following conditions are met: + - Redistributions of source code must retain the above copyright + notice, this list of conditions and the following disclaimer. + - Redistributions in binary form must reproduce the above copyright + notice, this list of conditions and the following disclaimer in the + documentation and/or other materials provided with the distribution. + - Neither the name of ARM nor the names of its contributors may be used + to endorse or promote products derived from this software without + specific prior written permission. + * + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE + LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + POSSIBILITY OF SUCH DAMAGE. + ---------------------------------------------------------------------------*/ + + +#if defined ( __ICCARM__ ) + #pragma system_include /* treat file as system include file for MISRA check */ +#elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) + #pragma clang system_header /* treat file as system include file */ +#endif + +#ifndef __CORE_CM4_H_GENERIC +#define __CORE_CM4_H_GENERIC + +#include + +#ifdef __cplusplus +extern "C" { +#endif + +/** + \page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions + CMSIS violates the following MISRA-C:2004 rules: + + \li Required Rule 8.5, object/function definition in header file.
+ Function definitions in header files are used to allow 'inlining'. + + \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.
+ Unions are used for effective representation of core registers. + + \li Advisory Rule 19.7, Function-like macro defined.
+ Function-like macros are used to allow more efficient code. + */ + + +/******************************************************************************* + * CMSIS definitions + ******************************************************************************/ +/** + \ingroup Cortex_M4 + @{ + */ + +/* CMSIS CM4 definitions */ +#define __CM4_CMSIS_VERSION_MAIN (0x04U) /*!< [31:16] CMSIS HAL main version */ +#define __CM4_CMSIS_VERSION_SUB (0x1EU) /*!< [15:0] CMSIS HAL sub version */ +#define __CM4_CMSIS_VERSION ((__CM4_CMSIS_VERSION_MAIN << 16U) | \ + __CM4_CMSIS_VERSION_SUB ) /*!< CMSIS HAL version number */ + +#define __CORTEX_M (0x04U) /*!< Cortex-M Core */ + + +#if defined ( __CC_ARM ) +#define __ASM __asm /*!< asm keyword for ARM Compiler */ +#define __INLINE __inline /*!< inline keyword for ARM Compiler */ +#define __STATIC_INLINE static __inline + +#elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) +#define __ASM __asm /*!< asm keyword for ARM Compiler */ +#define __INLINE __inline /*!< inline keyword for ARM Compiler */ +#define __STATIC_INLINE static __inline + +#elif defined ( __GNUC__ ) +#define __ASM __asm /*!< asm keyword for GNU Compiler */ +#define __INLINE inline /*!< inline keyword for GNU Compiler */ +#define __STATIC_INLINE static inline + +#elif defined ( __ICCARM__ ) +#define __ASM __asm /*!< asm keyword for IAR Compiler */ +#define __INLINE inline /*!< inline keyword for IAR Compiler. Only available in High optimization mode! */ +#define __STATIC_INLINE static inline + +#elif defined ( __TMS470__ ) +#define __ASM __asm /*!< asm keyword for TI CCS Compiler */ +#define __STATIC_INLINE static inline + +#elif defined ( __TASKING__ ) +#define __ASM __asm /*!< asm keyword for TASKING Compiler */ +#define __INLINE inline /*!< inline keyword for TASKING Compiler */ +#define __STATIC_INLINE static inline + +#elif defined ( __CSMC__ ) +#define __packed +#define __ASM _asm /*!< asm keyword for COSMIC Compiler */ +#define __INLINE inline /*!< inline keyword for COSMIC Compiler. Use -pc99 on compile line */ +#define __STATIC_INLINE static inline + +#else +#error Unknown compiler +#endif + +/** __FPU_USED indicates whether an FPU is used or not. + For this, __FPU_PRESENT has to be checked prior to making use of FPU specific registers and functions. +*/ +#if defined ( __CC_ARM ) +#if defined __TARGET_FPU_VFP +#if (__FPU_PRESENT == 1U) +#define __FPU_USED 1U +#else +#error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" +#define __FPU_USED 0U +#endif +#else +#define __FPU_USED 0U +#endif + +#elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) +#if defined __ARM_PCS_VFP +#if (__FPU_PRESENT == 1) +#define __FPU_USED 1U +#else +#warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" +#define __FPU_USED 0U +#endif +#else +#define __FPU_USED 0U +#endif + +#elif defined ( __GNUC__ ) +#if defined (__VFP_FP__) && !defined(__SOFTFP__) +#if (__FPU_PRESENT == 1U) +#define __FPU_USED 1U +#else +#error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" +#define __FPU_USED 0U +#endif +#else +#define __FPU_USED 0U +#endif + +#elif defined ( __ICCARM__ ) +#if defined __ARMVFP__ +#if (__FPU_PRESENT == 1U) +#define __FPU_USED 1U +#else +#error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" +#define __FPU_USED 0U +#endif +#else +#define __FPU_USED 0U +#endif + +#elif defined ( __TMS470__ ) +#if defined __TI_VFP_SUPPORT__ +#if (__FPU_PRESENT == 1U) +#define __FPU_USED 1U +#else +#error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" +#define __FPU_USED 0U +#endif +#else +#define __FPU_USED 0U +#endif + +#elif defined ( __TASKING__ ) +#if defined __FPU_VFP__ +#if (__FPU_PRESENT == 1U) +#define __FPU_USED 1U +#else +#error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" +#define __FPU_USED 0U +#endif +#else +#define __FPU_USED 0U +#endif + +#elif defined ( __CSMC__ ) +#if ( __CSMC__ & 0x400U) +#if (__FPU_PRESENT == 1U) +#define __FPU_USED 1U +#else +#error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" +#define __FPU_USED 0U +#endif +#else +#define __FPU_USED 0U +#endif + +#endif + +#include "core_cmInstr.h" /* Core Instruction Access */ +#include "core_cmFunc.h" /* Core Function Access */ +#include "core_cmSimd.h" /* Compiler specific SIMD Intrinsics */ + +#ifdef __cplusplus +} +#endif + +#endif /* __CORE_CM4_H_GENERIC */ + +#ifndef __CMSIS_GENERIC + +#ifndef __CORE_CM4_H_DEPENDANT +#define __CORE_CM4_H_DEPENDANT + +#ifdef __cplusplus +extern "C" { +#endif + +/* check device defines and use defaults */ +#if defined __CHECK_DEVICE_DEFINES +#ifndef __CM4_REV +#define __CM4_REV 0x0000U +#warning "__CM4_REV not defined in device header file; using default!" +#endif + +#ifndef __FPU_PRESENT +#define __FPU_PRESENT 0U +#warning "__FPU_PRESENT not defined in device header file; using default!" +#endif + +#ifndef __MPU_PRESENT +#define __MPU_PRESENT 0U +#warning "__MPU_PRESENT not defined in device header file; using default!" +#endif + +#ifndef __NVIC_PRIO_BITS +#define __NVIC_PRIO_BITS 4U +#warning "__NVIC_PRIO_BITS not defined in device header file; using default!" +#endif + +#ifndef __Vendor_SysTickConfig +#define __Vendor_SysTickConfig 0U +#warning "__Vendor_SysTickConfig not defined in device header file; using default!" +#endif +#endif + +/* IO definitions (access restrictions to peripheral registers) */ +/** + \defgroup CMSIS_glob_defs CMSIS Global Defines + + IO Type Qualifiers are used + \li to specify the access to peripheral variables. + \li for automatic generation of peripheral register debug information. +*/ +#ifdef __cplusplus +#define __I volatile /*!< Defines 'read only' permissions */ +#else +#define __I volatile const /*!< Defines 'read only' permissions */ +#endif +#define __O volatile /*!< Defines 'write only' permissions */ +#define __IO volatile /*!< Defines 'read / write' permissions */ + +/* following defines should be used for structure members */ +#define __IM volatile const /*! Defines 'read only' structure member permissions */ +#define __OM volatile /*! Defines 'write only' structure member permissions */ +#define __IOM volatile /*! Defines 'read / write' structure member permissions */ + +/*@} end of group Cortex_M4 */ + + + +/******************************************************************************* + * Register Abstraction + Core Register contain: + - Core Register + - Core NVIC Register + - Core SCB Register + - Core SysTick Register + - Core Debug Register + - Core MPU Register + - Core FPU Register + ******************************************************************************/ +/** + \defgroup CMSIS_core_register Defines and Type Definitions + \brief Type definitions and defines for Cortex-M processor based devices. +*/ + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_CORE Status and Control Registers + \brief Core Register type definitions. + @{ + */ + +/** + \brief Union type to access the Application Program Status Register (APSR). + */ +typedef union +{ + struct + { + uint32_t _reserved0: 16; /*!< bit: 0..15 Reserved */ + uint32_t GE: 4; /*!< bit: 16..19 Greater than or Equal flags */ + uint32_t _reserved1: 7; /*!< bit: 20..26 Reserved */ + uint32_t Q: 1; /*!< bit: 27 Saturation condition flag */ + uint32_t V: 1; /*!< bit: 28 Overflow condition code flag */ + uint32_t C: 1; /*!< bit: 29 Carry condition code flag */ + uint32_t Z: 1; /*!< bit: 30 Zero condition code flag */ + uint32_t N: 1; /*!< bit: 31 Negative condition code flag */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} APSR_Type; + +/* APSR Register Definitions */ +#define APSR_N_Pos 31U /*!< APSR: N Position */ +#define APSR_N_Msk (1UL << APSR_N_Pos) /*!< APSR: N Mask */ + +#define APSR_Z_Pos 30U /*!< APSR: Z Position */ +#define APSR_Z_Msk (1UL << APSR_Z_Pos) /*!< APSR: Z Mask */ + +#define APSR_C_Pos 29U /*!< APSR: C Position */ +#define APSR_C_Msk (1UL << APSR_C_Pos) /*!< APSR: C Mask */ + +#define APSR_V_Pos 28U /*!< APSR: V Position */ +#define APSR_V_Msk (1UL << APSR_V_Pos) /*!< APSR: V Mask */ + +#define APSR_Q_Pos 27U /*!< APSR: Q Position */ +#define APSR_Q_Msk (1UL << APSR_Q_Pos) /*!< APSR: Q Mask */ + +#define APSR_GE_Pos 16U /*!< APSR: GE Position */ +#define APSR_GE_Msk (0xFUL << APSR_GE_Pos) /*!< APSR: GE Mask */ + + +/** + \brief Union type to access the Interrupt Program Status Register (IPSR). + */ +typedef union +{ + struct + { + uint32_t ISR: 9; /*!< bit: 0.. 8 Exception number */ + uint32_t _reserved0: 23; /*!< bit: 9..31 Reserved */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} IPSR_Type; + +/* IPSR Register Definitions */ +#define IPSR_ISR_Pos 0U /*!< IPSR: ISR Position */ +#define IPSR_ISR_Msk (0x1FFUL /*<< IPSR_ISR_Pos*/) /*!< IPSR: ISR Mask */ + + +/** + \brief Union type to access the Special-Purpose Program Status Registers (xPSR). + */ +typedef union +{ + struct + { + uint32_t ISR: 9; /*!< bit: 0.. 8 Exception number */ + uint32_t _reserved0: 7; /*!< bit: 9..15 Reserved */ + uint32_t GE: 4; /*!< bit: 16..19 Greater than or Equal flags */ + uint32_t _reserved1: 4; /*!< bit: 20..23 Reserved */ + uint32_t T: 1; /*!< bit: 24 Thumb bit (read 0) */ + uint32_t IT: 2; /*!< bit: 25..26 saved IT state (read 0) */ + uint32_t Q: 1; /*!< bit: 27 Saturation condition flag */ + uint32_t V: 1; /*!< bit: 28 Overflow condition code flag */ + uint32_t C: 1; /*!< bit: 29 Carry condition code flag */ + uint32_t Z: 1; /*!< bit: 30 Zero condition code flag */ + uint32_t N: 1; /*!< bit: 31 Negative condition code flag */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} xPSR_Type; + +/* xPSR Register Definitions */ +#define xPSR_N_Pos 31U /*!< xPSR: N Position */ +#define xPSR_N_Msk (1UL << xPSR_N_Pos) /*!< xPSR: N Mask */ + +#define xPSR_Z_Pos 30U /*!< xPSR: Z Position */ +#define xPSR_Z_Msk (1UL << xPSR_Z_Pos) /*!< xPSR: Z Mask */ + +#define xPSR_C_Pos 29U /*!< xPSR: C Position */ +#define xPSR_C_Msk (1UL << xPSR_C_Pos) /*!< xPSR: C Mask */ + +#define xPSR_V_Pos 28U /*!< xPSR: V Position */ +#define xPSR_V_Msk (1UL << xPSR_V_Pos) /*!< xPSR: V Mask */ + +#define xPSR_Q_Pos 27U /*!< xPSR: Q Position */ +#define xPSR_Q_Msk (1UL << xPSR_Q_Pos) /*!< xPSR: Q Mask */ + +#define xPSR_IT_Pos 25U /*!< xPSR: IT Position */ +#define xPSR_IT_Msk (3UL << xPSR_IT_Pos) /*!< xPSR: IT Mask */ + +#define xPSR_T_Pos 24U /*!< xPSR: T Position */ +#define xPSR_T_Msk (1UL << xPSR_T_Pos) /*!< xPSR: T Mask */ + +#define xPSR_GE_Pos 16U /*!< xPSR: GE Position */ +#define xPSR_GE_Msk (0xFUL << xPSR_GE_Pos) /*!< xPSR: GE Mask */ + +#define xPSR_ISR_Pos 0U /*!< xPSR: ISR Position */ +#define xPSR_ISR_Msk (0x1FFUL /*<< xPSR_ISR_Pos*/) /*!< xPSR: ISR Mask */ + + +/** + \brief Union type to access the Control Registers (CONTROL). + */ +typedef union +{ + struct + { + uint32_t nPRIV: 1; /*!< bit: 0 Execution privilege in Thread mode */ + uint32_t SPSEL: 1; /*!< bit: 1 Stack to be used */ + uint32_t FPCA: 1; /*!< bit: 2 FP extension active flag */ + uint32_t _reserved0: 29; /*!< bit: 3..31 Reserved */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} CONTROL_Type; + +/* CONTROL Register Definitions */ +#define CONTROL_FPCA_Pos 2U /*!< CONTROL: FPCA Position */ +#define CONTROL_FPCA_Msk (1UL << CONTROL_FPCA_Pos) /*!< CONTROL: FPCA Mask */ + +#define CONTROL_SPSEL_Pos 1U /*!< CONTROL: SPSEL Position */ +#define CONTROL_SPSEL_Msk (1UL << CONTROL_SPSEL_Pos) /*!< CONTROL: SPSEL Mask */ + +#define CONTROL_nPRIV_Pos 0U /*!< CONTROL: nPRIV Position */ +#define CONTROL_nPRIV_Msk (1UL /*<< CONTROL_nPRIV_Pos*/) /*!< CONTROL: nPRIV Mask */ + +/*@} end of group CMSIS_CORE */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC) + \brief Type definitions for the NVIC Registers + @{ + */ + +/** + \brief Structure type to access the Nested Vectored Interrupt Controller (NVIC). + */ +typedef struct +{ + __IOM uint32_t ISER[8U]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */ + uint32_t RESERVED0[24U]; + __IOM uint32_t ICER[8U]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */ + uint32_t RSERVED1[24U]; + __IOM uint32_t ISPR[8U]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */ + uint32_t RESERVED2[24U]; + __IOM uint32_t ICPR[8U]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register */ + uint32_t RESERVED3[24U]; + __IOM uint32_t IABR[8U]; /*!< Offset: 0x200 (R/W) Interrupt Active bit Register */ + uint32_t RESERVED4[56U]; + __IOM uint8_t IP[240U]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register (8Bit wide) */ + uint32_t RESERVED5[644U]; + __OM uint32_t STIR; /*!< Offset: 0xE00 ( /W) Software Trigger Interrupt Register */ +} NVIC_Type; + +/* Software Triggered Interrupt Register Definitions */ +#define NVIC_STIR_INTID_Pos 0U /*!< STIR: INTLINESNUM Position */ +#define NVIC_STIR_INTID_Msk (0x1FFUL /*<< NVIC_STIR_INTID_Pos*/) /*!< STIR: INTLINESNUM Mask */ + +/*@} end of group CMSIS_NVIC */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SCB System Control Block (SCB) + \brief Type definitions for the System Control Block Registers + @{ + */ + +/** + \brief Structure type to access the System Control Block (SCB). + */ +typedef struct +{ + __IM uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */ + __IOM uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Register */ + __IOM uint32_t VTOR; /*!< Offset: 0x008 (R/W) Vector Table Offset Register */ + __IOM uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register */ + __IOM uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */ + __IOM uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */ + __IOM uint8_t SHP[12U]; /*!< Offset: 0x018 (R/W) System Handlers Priority Registers (4-7, 8-11, 12-15) */ + __IOM uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State Register */ + __IOM uint32_t CFSR; /*!< Offset: 0x028 (R/W) Configurable Fault Status Register */ + __IOM uint32_t HFSR; /*!< Offset: 0x02C (R/W) HardFault Status Register */ + __IOM uint32_t DFSR; /*!< Offset: 0x030 (R/W) Debug Fault Status Register */ + __IOM uint32_t MMFAR; /*!< Offset: 0x034 (R/W) MemManage Fault Address Register */ + __IOM uint32_t BFAR; /*!< Offset: 0x038 (R/W) BusFault Address Register */ + __IOM uint32_t AFSR; /*!< Offset: 0x03C (R/W) Auxiliary Fault Status Register */ + __IM uint32_t PFR[2U]; /*!< Offset: 0x040 (R/ ) Processor Feature Register */ + __IM uint32_t DFR; /*!< Offset: 0x048 (R/ ) Debug Feature Register */ + __IM uint32_t ADR; /*!< Offset: 0x04C (R/ ) Auxiliary Feature Register */ + __IM uint32_t MMFR[4U]; /*!< Offset: 0x050 (R/ ) Memory Model Feature Register */ + __IM uint32_t ISAR[5U]; /*!< Offset: 0x060 (R/ ) Instruction Set Attributes Register */ + uint32_t RESERVED0[5U]; + __IOM uint32_t CPACR; /*!< Offset: 0x088 (R/W) Coprocessor Access Control Register */ +} SCB_Type; + +/* SCB CPUID Register Definitions */ +#define SCB_CPUID_IMPLEMENTER_Pos 24U /*!< SCB CPUID: IMPLEMENTER Position */ +#define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */ + +#define SCB_CPUID_VARIANT_Pos 20U /*!< SCB CPUID: VARIANT Position */ +#define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */ + +#define SCB_CPUID_ARCHITECTURE_Pos 16U /*!< SCB CPUID: ARCHITECTURE Position */ +#define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB CPUID: ARCHITECTURE Mask */ + +#define SCB_CPUID_PARTNO_Pos 4U /*!< SCB CPUID: PARTNO Position */ +#define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */ + +#define SCB_CPUID_REVISION_Pos 0U /*!< SCB CPUID: REVISION Position */ +#define SCB_CPUID_REVISION_Msk (0xFUL /*<< SCB_CPUID_REVISION_Pos*/) /*!< SCB CPUID: REVISION Mask */ + +/* SCB Interrupt Control State Register Definitions */ +#define SCB_ICSR_NMIPENDSET_Pos 31U /*!< SCB ICSR: NMIPENDSET Position */ +#define SCB_ICSR_NMIPENDSET_Msk (1UL << SCB_ICSR_NMIPENDSET_Pos) /*!< SCB ICSR: NMIPENDSET Mask */ + +#define SCB_ICSR_PENDSVSET_Pos 28U /*!< SCB ICSR: PENDSVSET Position */ +#define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */ + +#define SCB_ICSR_PENDSVCLR_Pos 27U /*!< SCB ICSR: PENDSVCLR Position */ +#define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */ + +#define SCB_ICSR_PENDSTSET_Pos 26U /*!< SCB ICSR: PENDSTSET Position */ +#define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */ + +#define SCB_ICSR_PENDSTCLR_Pos 25U /*!< SCB ICSR: PENDSTCLR Position */ +#define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */ + +#define SCB_ICSR_ISRPREEMPT_Pos 23U /*!< SCB ICSR: ISRPREEMPT Position */ +#define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */ + +#define SCB_ICSR_ISRPENDING_Pos 22U /*!< SCB ICSR: ISRPENDING Position */ +#define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */ + +#define SCB_ICSR_VECTPENDING_Pos 12U /*!< SCB ICSR: VECTPENDING Position */ +#define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */ + +#define SCB_ICSR_RETTOBASE_Pos 11U /*!< SCB ICSR: RETTOBASE Position */ +#define SCB_ICSR_RETTOBASE_Msk (1UL << SCB_ICSR_RETTOBASE_Pos) /*!< SCB ICSR: RETTOBASE Mask */ + +#define SCB_ICSR_VECTACTIVE_Pos 0U /*!< SCB ICSR: VECTACTIVE Position */ +#define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/) /*!< SCB ICSR: VECTACTIVE Mask */ + +/* SCB Vector Table Offset Register Definitions */ +#define SCB_VTOR_TBLOFF_Pos 7U /*!< SCB VTOR: TBLOFF Position */ +#define SCB_VTOR_TBLOFF_Msk (0x1FFFFFFUL << SCB_VTOR_TBLOFF_Pos) /*!< SCB VTOR: TBLOFF Mask */ + +/* SCB Application Interrupt and Reset Control Register Definitions */ +#define SCB_AIRCR_VECTKEY_Pos 16U /*!< SCB AIRCR: VECTKEY Position */ +#define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */ + +#define SCB_AIRCR_VECTKEYSTAT_Pos 16U /*!< SCB AIRCR: VECTKEYSTAT Position */ +#define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */ + +#define SCB_AIRCR_ENDIANESS_Pos 15U /*!< SCB AIRCR: ENDIANESS Position */ +#define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /*!< SCB AIRCR: ENDIANESS Mask */ + +#define SCB_AIRCR_PRIGROUP_Pos 8U /*!< SCB AIRCR: PRIGROUP Position */ +#define SCB_AIRCR_PRIGROUP_Msk (7UL << SCB_AIRCR_PRIGROUP_Pos) /*!< SCB AIRCR: PRIGROUP Mask */ + +#define SCB_AIRCR_SYSRESETREQ_Pos 2U /*!< SCB AIRCR: SYSRESETREQ Position */ +#define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */ + +#define SCB_AIRCR_VECTCLRACTIVE_Pos 1U /*!< SCB AIRCR: VECTCLRACTIVE Position */ +#define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */ + +#define SCB_AIRCR_VECTRESET_Pos 0U /*!< SCB AIRCR: VECTRESET Position */ +#define SCB_AIRCR_VECTRESET_Msk (1UL /*<< SCB_AIRCR_VECTRESET_Pos*/) /*!< SCB AIRCR: VECTRESET Mask */ + +/* SCB System Control Register Definitions */ +#define SCB_SCR_SEVONPEND_Pos 4U /*!< SCB SCR: SEVONPEND Position */ +#define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */ + +#define SCB_SCR_SLEEPDEEP_Pos 2U /*!< SCB SCR: SLEEPDEEP Position */ +#define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */ + +#define SCB_SCR_SLEEPONEXIT_Pos 1U /*!< SCB SCR: SLEEPONEXIT Position */ +#define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */ + +/* SCB Configuration Control Register Definitions */ +#define SCB_CCR_STKALIGN_Pos 9U /*!< SCB CCR: STKALIGN Position */ +#define SCB_CCR_STKALIGN_Msk (1UL << SCB_CCR_STKALIGN_Pos) /*!< SCB CCR: STKALIGN Mask */ + +#define SCB_CCR_BFHFNMIGN_Pos 8U /*!< SCB CCR: BFHFNMIGN Position */ +#define SCB_CCR_BFHFNMIGN_Msk (1UL << SCB_CCR_BFHFNMIGN_Pos) /*!< SCB CCR: BFHFNMIGN Mask */ + +#define SCB_CCR_DIV_0_TRP_Pos 4U /*!< SCB CCR: DIV_0_TRP Position */ +#define SCB_CCR_DIV_0_TRP_Msk (1UL << SCB_CCR_DIV_0_TRP_Pos) /*!< SCB CCR: DIV_0_TRP Mask */ + +#define SCB_CCR_UNALIGN_TRP_Pos 3U /*!< SCB CCR: UNALIGN_TRP Position */ +#define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */ + +#define SCB_CCR_USERSETMPEND_Pos 1U /*!< SCB CCR: USERSETMPEND Position */ +#define SCB_CCR_USERSETMPEND_Msk (1UL << SCB_CCR_USERSETMPEND_Pos) /*!< SCB CCR: USERSETMPEND Mask */ + +#define SCB_CCR_NONBASETHRDENA_Pos 0U /*!< SCB CCR: NONBASETHRDENA Position */ +#define SCB_CCR_NONBASETHRDENA_Msk (1UL /*<< SCB_CCR_NONBASETHRDENA_Pos*/) /*!< SCB CCR: NONBASETHRDENA Mask */ + +/* SCB System Handler Control and State Register Definitions */ +#define SCB_SHCSR_USGFAULTENA_Pos 18U /*!< SCB SHCSR: USGFAULTENA Position */ +#define SCB_SHCSR_USGFAULTENA_Msk (1UL << SCB_SHCSR_USGFAULTENA_Pos) /*!< SCB SHCSR: USGFAULTENA Mask */ + +#define SCB_SHCSR_BUSFAULTENA_Pos 17U /*!< SCB SHCSR: BUSFAULTENA Position */ +#define SCB_SHCSR_BUSFAULTENA_Msk (1UL << SCB_SHCSR_BUSFAULTENA_Pos) /*!< SCB SHCSR: BUSFAULTENA Mask */ + +#define SCB_SHCSR_MEMFAULTENA_Pos 16U /*!< SCB SHCSR: MEMFAULTENA Position */ +#define SCB_SHCSR_MEMFAULTENA_Msk (1UL << SCB_SHCSR_MEMFAULTENA_Pos) /*!< SCB SHCSR: MEMFAULTENA Mask */ + +#define SCB_SHCSR_SVCALLPENDED_Pos 15U /*!< SCB SHCSR: SVCALLPENDED Position */ +#define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */ + +#define SCB_SHCSR_BUSFAULTPENDED_Pos 14U /*!< SCB SHCSR: BUSFAULTPENDED Position */ +#define SCB_SHCSR_BUSFAULTPENDED_Msk (1UL << SCB_SHCSR_BUSFAULTPENDED_Pos) /*!< SCB SHCSR: BUSFAULTPENDED Mask */ + +#define SCB_SHCSR_MEMFAULTPENDED_Pos 13U /*!< SCB SHCSR: MEMFAULTPENDED Position */ +#define SCB_SHCSR_MEMFAULTPENDED_Msk (1UL << SCB_SHCSR_MEMFAULTPENDED_Pos) /*!< SCB SHCSR: MEMFAULTPENDED Mask */ + +#define SCB_SHCSR_USGFAULTPENDED_Pos 12U /*!< SCB SHCSR: USGFAULTPENDED Position */ +#define SCB_SHCSR_USGFAULTPENDED_Msk (1UL << SCB_SHCSR_USGFAULTPENDED_Pos) /*!< SCB SHCSR: USGFAULTPENDED Mask */ + +#define SCB_SHCSR_SYSTICKACT_Pos 11U /*!< SCB SHCSR: SYSTICKACT Position */ +#define SCB_SHCSR_SYSTICKACT_Msk (1UL << SCB_SHCSR_SYSTICKACT_Pos) /*!< SCB SHCSR: SYSTICKACT Mask */ + +#define SCB_SHCSR_PENDSVACT_Pos 10U /*!< SCB SHCSR: PENDSVACT Position */ +#define SCB_SHCSR_PENDSVACT_Msk (1UL << SCB_SHCSR_PENDSVACT_Pos) /*!< SCB SHCSR: PENDSVACT Mask */ + +#define SCB_SHCSR_MONITORACT_Pos 8U /*!< SCB SHCSR: MONITORACT Position */ +#define SCB_SHCSR_MONITORACT_Msk (1UL << SCB_SHCSR_MONITORACT_Pos) /*!< SCB SHCSR: MONITORACT Mask */ + +#define SCB_SHCSR_SVCALLACT_Pos 7U /*!< SCB SHCSR: SVCALLACT Position */ +#define SCB_SHCSR_SVCALLACT_Msk (1UL << SCB_SHCSR_SVCALLACT_Pos) /*!< SCB SHCSR: SVCALLACT Mask */ + +#define SCB_SHCSR_USGFAULTACT_Pos 3U /*!< SCB SHCSR: USGFAULTACT Position */ +#define SCB_SHCSR_USGFAULTACT_Msk (1UL << SCB_SHCSR_USGFAULTACT_Pos) /*!< SCB SHCSR: USGFAULTACT Mask */ + +#define SCB_SHCSR_BUSFAULTACT_Pos 1U /*!< SCB SHCSR: BUSFAULTACT Position */ +#define SCB_SHCSR_BUSFAULTACT_Msk (1UL << SCB_SHCSR_BUSFAULTACT_Pos) /*!< SCB SHCSR: BUSFAULTACT Mask */ + +#define SCB_SHCSR_MEMFAULTACT_Pos 0U /*!< SCB SHCSR: MEMFAULTACT Position */ +#define SCB_SHCSR_MEMFAULTACT_Msk (1UL /*<< SCB_SHCSR_MEMFAULTACT_Pos*/) /*!< SCB SHCSR: MEMFAULTACT Mask */ + +/* SCB Configurable Fault Status Register Definitions */ +#define SCB_CFSR_USGFAULTSR_Pos 16U /*!< SCB CFSR: Usage Fault Status Register Position */ +#define SCB_CFSR_USGFAULTSR_Msk (0xFFFFUL << SCB_CFSR_USGFAULTSR_Pos) /*!< SCB CFSR: Usage Fault Status Register Mask */ + +#define SCB_CFSR_BUSFAULTSR_Pos 8U /*!< SCB CFSR: Bus Fault Status Register Position */ +#define SCB_CFSR_BUSFAULTSR_Msk (0xFFUL << SCB_CFSR_BUSFAULTSR_Pos) /*!< SCB CFSR: Bus Fault Status Register Mask */ + +#define SCB_CFSR_MEMFAULTSR_Pos 0U /*!< SCB CFSR: Memory Manage Fault Status Register Position */ +#define SCB_CFSR_MEMFAULTSR_Msk (0xFFUL /*<< SCB_CFSR_MEMFAULTSR_Pos*/) /*!< SCB CFSR: Memory Manage Fault Status Register Mask */ + +/* SCB Hard Fault Status Register Definitions */ +#define SCB_HFSR_DEBUGEVT_Pos 31U /*!< SCB HFSR: DEBUGEVT Position */ +#define SCB_HFSR_DEBUGEVT_Msk (1UL << SCB_HFSR_DEBUGEVT_Pos) /*!< SCB HFSR: DEBUGEVT Mask */ + +#define SCB_HFSR_FORCED_Pos 30U /*!< SCB HFSR: FORCED Position */ +#define SCB_HFSR_FORCED_Msk (1UL << SCB_HFSR_FORCED_Pos) /*!< SCB HFSR: FORCED Mask */ + +#define SCB_HFSR_VECTTBL_Pos 1U /*!< SCB HFSR: VECTTBL Position */ +#define SCB_HFSR_VECTTBL_Msk (1UL << SCB_HFSR_VECTTBL_Pos) /*!< SCB HFSR: VECTTBL Mask */ + +/* SCB Debug Fault Status Register Definitions */ +#define SCB_DFSR_EXTERNAL_Pos 4U /*!< SCB DFSR: EXTERNAL Position */ +#define SCB_DFSR_EXTERNAL_Msk (1UL << SCB_DFSR_EXTERNAL_Pos) /*!< SCB DFSR: EXTERNAL Mask */ + +#define SCB_DFSR_VCATCH_Pos 3U /*!< SCB DFSR: VCATCH Position */ +#define SCB_DFSR_VCATCH_Msk (1UL << SCB_DFSR_VCATCH_Pos) /*!< SCB DFSR: VCATCH Mask */ + +#define SCB_DFSR_DWTTRAP_Pos 2U /*!< SCB DFSR: DWTTRAP Position */ +#define SCB_DFSR_DWTTRAP_Msk (1UL << SCB_DFSR_DWTTRAP_Pos) /*!< SCB DFSR: DWTTRAP Mask */ + +#define SCB_DFSR_BKPT_Pos 1U /*!< SCB DFSR: BKPT Position */ +#define SCB_DFSR_BKPT_Msk (1UL << SCB_DFSR_BKPT_Pos) /*!< SCB DFSR: BKPT Mask */ + +#define SCB_DFSR_HALTED_Pos 0U /*!< SCB DFSR: HALTED Position */ +#define SCB_DFSR_HALTED_Msk (1UL /*<< SCB_DFSR_HALTED_Pos*/) /*!< SCB DFSR: HALTED Mask */ + +/*@} end of group CMSIS_SCB */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SCnSCB System Controls not in SCB (SCnSCB) + \brief Type definitions for the System Control and ID Register not in the SCB + @{ + */ + +/** + \brief Structure type to access the System Control and ID Register not in the SCB. + */ +typedef struct +{ + uint32_t RESERVED0[1U]; + __IM uint32_t ICTR; /*!< Offset: 0x004 (R/ ) Interrupt Controller Type Register */ + __IOM uint32_t ACTLR; /*!< Offset: 0x008 (R/W) Auxiliary Control Register */ +} SCnSCB_Type; + +/* Interrupt Controller Type Register Definitions */ +#define SCnSCB_ICTR_INTLINESNUM_Pos 0U /*!< ICTR: INTLINESNUM Position */ +#define SCnSCB_ICTR_INTLINESNUM_Msk (0xFUL /*<< SCnSCB_ICTR_INTLINESNUM_Pos*/) /*!< ICTR: INTLINESNUM Mask */ + +/* Auxiliary Control Register Definitions */ +#define SCnSCB_ACTLR_DISOOFP_Pos 9U /*!< ACTLR: DISOOFP Position */ +#define SCnSCB_ACTLR_DISOOFP_Msk (1UL << SCnSCB_ACTLR_DISOOFP_Pos) /*!< ACTLR: DISOOFP Mask */ + +#define SCnSCB_ACTLR_DISFPCA_Pos 8U /*!< ACTLR: DISFPCA Position */ +#define SCnSCB_ACTLR_DISFPCA_Msk (1UL << SCnSCB_ACTLR_DISFPCA_Pos) /*!< ACTLR: DISFPCA Mask */ + +#define SCnSCB_ACTLR_DISFOLD_Pos 2U /*!< ACTLR: DISFOLD Position */ +#define SCnSCB_ACTLR_DISFOLD_Msk (1UL << SCnSCB_ACTLR_DISFOLD_Pos) /*!< ACTLR: DISFOLD Mask */ + +#define SCnSCB_ACTLR_DISDEFWBUF_Pos 1U /*!< ACTLR: DISDEFWBUF Position */ +#define SCnSCB_ACTLR_DISDEFWBUF_Msk (1UL << SCnSCB_ACTLR_DISDEFWBUF_Pos) /*!< ACTLR: DISDEFWBUF Mask */ + +#define SCnSCB_ACTLR_DISMCYCINT_Pos 0U /*!< ACTLR: DISMCYCINT Position */ +#define SCnSCB_ACTLR_DISMCYCINT_Msk (1UL /*<< SCnSCB_ACTLR_DISMCYCINT_Pos*/) /*!< ACTLR: DISMCYCINT Mask */ + +/*@} end of group CMSIS_SCnotSCB */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SysTick System Tick Timer (SysTick) + \brief Type definitions for the System Timer Registers. + @{ + */ + +/** + \brief Structure type to access the System Timer (SysTick). + */ +typedef struct +{ + __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */ + __IOM uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */ + __IOM uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register */ + __IM uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */ +} SysTick_Type; + +/* SysTick Control / Status Register Definitions */ +#define SysTick_CTRL_COUNTFLAG_Pos 16U /*!< SysTick CTRL: COUNTFLAG Position */ +#define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */ + +#define SysTick_CTRL_CLKSOURCE_Pos 2U /*!< SysTick CTRL: CLKSOURCE Position */ +#define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */ + +#define SysTick_CTRL_TICKINT_Pos 1U /*!< SysTick CTRL: TICKINT Position */ +#define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */ + +#define SysTick_CTRL_ENABLE_Pos 0U /*!< SysTick CTRL: ENABLE Position */ +#define SysTick_CTRL_ENABLE_Msk (1UL /*<< SysTick_CTRL_ENABLE_Pos*/) /*!< SysTick CTRL: ENABLE Mask */ + +/* SysTick Reload Register Definitions */ +#define SysTick_LOAD_RELOAD_Pos 0U /*!< SysTick LOAD: RELOAD Position */ +#define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/) /*!< SysTick LOAD: RELOAD Mask */ + +/* SysTick Current Register Definitions */ +#define SysTick_VAL_CURRENT_Pos 0U /*!< SysTick VAL: CURRENT Position */ +#define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/) /*!< SysTick VAL: CURRENT Mask */ + +/* SysTick Calibration Register Definitions */ +#define SysTick_CALIB_NOREF_Pos 31U /*!< SysTick CALIB: NOREF Position */ +#define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */ + +#define SysTick_CALIB_SKEW_Pos 30U /*!< SysTick CALIB: SKEW Position */ +#define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */ + +#define SysTick_CALIB_TENMS_Pos 0U /*!< SysTick CALIB: TENMS Position */ +#define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/) /*!< SysTick CALIB: TENMS Mask */ + +/*@} end of group CMSIS_SysTick */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_ITM Instrumentation Trace Macrocell (ITM) + \brief Type definitions for the Instrumentation Trace Macrocell (ITM) + @{ + */ + +/** + \brief Structure type to access the Instrumentation Trace Macrocell Register (ITM). + */ +typedef struct +{ + __OM union + { + __OM uint8_t u8; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 8-bit */ + __OM uint16_t u16; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 16-bit */ + __OM uint32_t u32; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 32-bit */ + } PORT [32U]; /*!< Offset: 0x000 ( /W) ITM Stimulus Port Registers */ + uint32_t RESERVED0[864U]; + __IOM uint32_t TER; /*!< Offset: 0xE00 (R/W) ITM Trace Enable Register */ + uint32_t RESERVED1[15U]; + __IOM uint32_t TPR; /*!< Offset: 0xE40 (R/W) ITM Trace Privilege Register */ + uint32_t RESERVED2[15U]; + __IOM uint32_t TCR; /*!< Offset: 0xE80 (R/W) ITM Trace Control Register */ + uint32_t RESERVED3[29U]; + __OM uint32_t IWR; /*!< Offset: 0xEF8 ( /W) ITM Integration Write Register */ + __IM uint32_t IRR; /*!< Offset: 0xEFC (R/ ) ITM Integration Read Register */ + __IOM uint32_t IMCR; /*!< Offset: 0xF00 (R/W) ITM Integration Mode Control Register */ + uint32_t RESERVED4[43U]; + __OM uint32_t LAR; /*!< Offset: 0xFB0 ( /W) ITM Lock Access Register */ + __IM uint32_t LSR; /*!< Offset: 0xFB4 (R/ ) ITM Lock Status Register */ + uint32_t RESERVED5[6U]; + __IM uint32_t PID4; /*!< Offset: 0xFD0 (R/ ) ITM Peripheral Identification Register #4 */ + __IM uint32_t PID5; /*!< Offset: 0xFD4 (R/ ) ITM Peripheral Identification Register #5 */ + __IM uint32_t PID6; /*!< Offset: 0xFD8 (R/ ) ITM Peripheral Identification Register #6 */ + __IM uint32_t PID7; /*!< Offset: 0xFDC (R/ ) ITM Peripheral Identification Register #7 */ + __IM uint32_t PID0; /*!< Offset: 0xFE0 (R/ ) ITM Peripheral Identification Register #0 */ + __IM uint32_t PID1; /*!< Offset: 0xFE4 (R/ ) ITM Peripheral Identification Register #1 */ + __IM uint32_t PID2; /*!< Offset: 0xFE8 (R/ ) ITM Peripheral Identification Register #2 */ + __IM uint32_t PID3; /*!< Offset: 0xFEC (R/ ) ITM Peripheral Identification Register #3 */ + __IM uint32_t CID0; /*!< Offset: 0xFF0 (R/ ) ITM Component Identification Register #0 */ + __IM uint32_t CID1; /*!< Offset: 0xFF4 (R/ ) ITM Component Identification Register #1 */ + __IM uint32_t CID2; /*!< Offset: 0xFF8 (R/ ) ITM Component Identification Register #2 */ + __IM uint32_t CID3; /*!< Offset: 0xFFC (R/ ) ITM Component Identification Register #3 */ +} ITM_Type; + +/* ITM Trace Privilege Register Definitions */ +#define ITM_TPR_PRIVMASK_Pos 0U /*!< ITM TPR: PRIVMASK Position */ +#define ITM_TPR_PRIVMASK_Msk (0xFUL /*<< ITM_TPR_PRIVMASK_Pos*/) /*!< ITM TPR: PRIVMASK Mask */ + +/* ITM Trace Control Register Definitions */ +#define ITM_TCR_BUSY_Pos 23U /*!< ITM TCR: BUSY Position */ +#define ITM_TCR_BUSY_Msk (1UL << ITM_TCR_BUSY_Pos) /*!< ITM TCR: BUSY Mask */ + +#define ITM_TCR_TraceBusID_Pos 16U /*!< ITM TCR: ATBID Position */ +#define ITM_TCR_TraceBusID_Msk (0x7FUL << ITM_TCR_TraceBusID_Pos) /*!< ITM TCR: ATBID Mask */ + +#define ITM_TCR_GTSFREQ_Pos 10U /*!< ITM TCR: Global timestamp frequency Position */ +#define ITM_TCR_GTSFREQ_Msk (3UL << ITM_TCR_GTSFREQ_Pos) /*!< ITM TCR: Global timestamp frequency Mask */ + +#define ITM_TCR_TSPrescale_Pos 8U /*!< ITM TCR: TSPrescale Position */ +#define ITM_TCR_TSPrescale_Msk (3UL << ITM_TCR_TSPrescale_Pos) /*!< ITM TCR: TSPrescale Mask */ + +#define ITM_TCR_SWOENA_Pos 4U /*!< ITM TCR: SWOENA Position */ +#define ITM_TCR_SWOENA_Msk (1UL << ITM_TCR_SWOENA_Pos) /*!< ITM TCR: SWOENA Mask */ + +#define ITM_TCR_DWTENA_Pos 3U /*!< ITM TCR: DWTENA Position */ +#define ITM_TCR_DWTENA_Msk (1UL << ITM_TCR_DWTENA_Pos) /*!< ITM TCR: DWTENA Mask */ + +#define ITM_TCR_SYNCENA_Pos 2U /*!< ITM TCR: SYNCENA Position */ +#define ITM_TCR_SYNCENA_Msk (1UL << ITM_TCR_SYNCENA_Pos) /*!< ITM TCR: SYNCENA Mask */ + +#define ITM_TCR_TSENA_Pos 1U /*!< ITM TCR: TSENA Position */ +#define ITM_TCR_TSENA_Msk (1UL << ITM_TCR_TSENA_Pos) /*!< ITM TCR: TSENA Mask */ + +#define ITM_TCR_ITMENA_Pos 0U /*!< ITM TCR: ITM Enable bit Position */ +#define ITM_TCR_ITMENA_Msk (1UL /*<< ITM_TCR_ITMENA_Pos*/) /*!< ITM TCR: ITM Enable bit Mask */ + +/* ITM Integration Write Register Definitions */ +#define ITM_IWR_ATVALIDM_Pos 0U /*!< ITM IWR: ATVALIDM Position */ +#define ITM_IWR_ATVALIDM_Msk (1UL /*<< ITM_IWR_ATVALIDM_Pos*/) /*!< ITM IWR: ATVALIDM Mask */ + +/* ITM Integration Read Register Definitions */ +#define ITM_IRR_ATREADYM_Pos 0U /*!< ITM IRR: ATREADYM Position */ +#define ITM_IRR_ATREADYM_Msk (1UL /*<< ITM_IRR_ATREADYM_Pos*/) /*!< ITM IRR: ATREADYM Mask */ + +/* ITM Integration Mode Control Register Definitions */ +#define ITM_IMCR_INTEGRATION_Pos 0U /*!< ITM IMCR: INTEGRATION Position */ +#define ITM_IMCR_INTEGRATION_Msk (1UL /*<< ITM_IMCR_INTEGRATION_Pos*/) /*!< ITM IMCR: INTEGRATION Mask */ + +/* ITM Lock Status Register Definitions */ +#define ITM_LSR_ByteAcc_Pos 2U /*!< ITM LSR: ByteAcc Position */ +#define ITM_LSR_ByteAcc_Msk (1UL << ITM_LSR_ByteAcc_Pos) /*!< ITM LSR: ByteAcc Mask */ + +#define ITM_LSR_Access_Pos 1U /*!< ITM LSR: Access Position */ +#define ITM_LSR_Access_Msk (1UL << ITM_LSR_Access_Pos) /*!< ITM LSR: Access Mask */ + +#define ITM_LSR_Present_Pos 0U /*!< ITM LSR: Present Position */ +#define ITM_LSR_Present_Msk (1UL /*<< ITM_LSR_Present_Pos*/) /*!< ITM LSR: Present Mask */ + +/*@}*/ /* end of group CMSIS_ITM */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_DWT Data Watchpoint and Trace (DWT) + \brief Type definitions for the Data Watchpoint and Trace (DWT) + @{ + */ + +/** + \brief Structure type to access the Data Watchpoint and Trace Register (DWT). + */ +typedef struct +{ + __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) Control Register */ + __IOM uint32_t CYCCNT; /*!< Offset: 0x004 (R/W) Cycle Count Register */ + __IOM uint32_t CPICNT; /*!< Offset: 0x008 (R/W) CPI Count Register */ + __IOM uint32_t EXCCNT; /*!< Offset: 0x00C (R/W) Exception Overhead Count Register */ + __IOM uint32_t SLEEPCNT; /*!< Offset: 0x010 (R/W) Sleep Count Register */ + __IOM uint32_t LSUCNT; /*!< Offset: 0x014 (R/W) LSU Count Register */ + __IOM uint32_t FOLDCNT; /*!< Offset: 0x018 (R/W) Folded-instruction Count Register */ + __IM uint32_t PCSR; /*!< Offset: 0x01C (R/ ) Program Counter Sample Register */ + __IOM uint32_t COMP0; /*!< Offset: 0x020 (R/W) Comparator Register 0 */ + __IOM uint32_t MASK0; /*!< Offset: 0x024 (R/W) Mask Register 0 */ + __IOM uint32_t FUNCTION0; /*!< Offset: 0x028 (R/W) Function Register 0 */ + uint32_t RESERVED0[1U]; + __IOM uint32_t COMP1; /*!< Offset: 0x030 (R/W) Comparator Register 1 */ + __IOM uint32_t MASK1; /*!< Offset: 0x034 (R/W) Mask Register 1 */ + __IOM uint32_t FUNCTION1; /*!< Offset: 0x038 (R/W) Function Register 1 */ + uint32_t RESERVED1[1U]; + __IOM uint32_t COMP2; /*!< Offset: 0x040 (R/W) Comparator Register 2 */ + __IOM uint32_t MASK2; /*!< Offset: 0x044 (R/W) Mask Register 2 */ + __IOM uint32_t FUNCTION2; /*!< Offset: 0x048 (R/W) Function Register 2 */ + uint32_t RESERVED2[1U]; + __IOM uint32_t COMP3; /*!< Offset: 0x050 (R/W) Comparator Register 3 */ + __IOM uint32_t MASK3; /*!< Offset: 0x054 (R/W) Mask Register 3 */ + __IOM uint32_t FUNCTION3; /*!< Offset: 0x058 (R/W) Function Register 3 */ +} DWT_Type; + +/* DWT Control Register Definitions */ +#define DWT_CTRL_NUMCOMP_Pos 28U /*!< DWT CTRL: NUMCOMP Position */ +#define DWT_CTRL_NUMCOMP_Msk (0xFUL << DWT_CTRL_NUMCOMP_Pos) /*!< DWT CTRL: NUMCOMP Mask */ + +#define DWT_CTRL_NOTRCPKT_Pos 27U /*!< DWT CTRL: NOTRCPKT Position */ +#define DWT_CTRL_NOTRCPKT_Msk (0x1UL << DWT_CTRL_NOTRCPKT_Pos) /*!< DWT CTRL: NOTRCPKT Mask */ + +#define DWT_CTRL_NOEXTTRIG_Pos 26U /*!< DWT CTRL: NOEXTTRIG Position */ +#define DWT_CTRL_NOEXTTRIG_Msk (0x1UL << DWT_CTRL_NOEXTTRIG_Pos) /*!< DWT CTRL: NOEXTTRIG Mask */ + +#define DWT_CTRL_NOCYCCNT_Pos 25U /*!< DWT CTRL: NOCYCCNT Position */ +#define DWT_CTRL_NOCYCCNT_Msk (0x1UL << DWT_CTRL_NOCYCCNT_Pos) /*!< DWT CTRL: NOCYCCNT Mask */ + +#define DWT_CTRL_NOPRFCNT_Pos 24U /*!< DWT CTRL: NOPRFCNT Position */ +#define DWT_CTRL_NOPRFCNT_Msk (0x1UL << DWT_CTRL_NOPRFCNT_Pos) /*!< DWT CTRL: NOPRFCNT Mask */ + +#define DWT_CTRL_CYCEVTENA_Pos 22U /*!< DWT CTRL: CYCEVTENA Position */ +#define DWT_CTRL_CYCEVTENA_Msk (0x1UL << DWT_CTRL_CYCEVTENA_Pos) /*!< DWT CTRL: CYCEVTENA Mask */ + +#define DWT_CTRL_FOLDEVTENA_Pos 21U /*!< DWT CTRL: FOLDEVTENA Position */ +#define DWT_CTRL_FOLDEVTENA_Msk (0x1UL << DWT_CTRL_FOLDEVTENA_Pos) /*!< DWT CTRL: FOLDEVTENA Mask */ + +#define DWT_CTRL_LSUEVTENA_Pos 20U /*!< DWT CTRL: LSUEVTENA Position */ +#define DWT_CTRL_LSUEVTENA_Msk (0x1UL << DWT_CTRL_LSUEVTENA_Pos) /*!< DWT CTRL: LSUEVTENA Mask */ + +#define DWT_CTRL_SLEEPEVTENA_Pos 19U /*!< DWT CTRL: SLEEPEVTENA Position */ +#define DWT_CTRL_SLEEPEVTENA_Msk (0x1UL << DWT_CTRL_SLEEPEVTENA_Pos) /*!< DWT CTRL: SLEEPEVTENA Mask */ + +#define DWT_CTRL_EXCEVTENA_Pos 18U /*!< DWT CTRL: EXCEVTENA Position */ +#define DWT_CTRL_EXCEVTENA_Msk (0x1UL << DWT_CTRL_EXCEVTENA_Pos) /*!< DWT CTRL: EXCEVTENA Mask */ + +#define DWT_CTRL_CPIEVTENA_Pos 17U /*!< DWT CTRL: CPIEVTENA Position */ +#define DWT_CTRL_CPIEVTENA_Msk (0x1UL << DWT_CTRL_CPIEVTENA_Pos) /*!< DWT CTRL: CPIEVTENA Mask */ + +#define DWT_CTRL_EXCTRCENA_Pos 16U /*!< DWT CTRL: EXCTRCENA Position */ +#define DWT_CTRL_EXCTRCENA_Msk (0x1UL << DWT_CTRL_EXCTRCENA_Pos) /*!< DWT CTRL: EXCTRCENA Mask */ + +#define DWT_CTRL_PCSAMPLENA_Pos 12U /*!< DWT CTRL: PCSAMPLENA Position */ +#define DWT_CTRL_PCSAMPLENA_Msk (0x1UL << DWT_CTRL_PCSAMPLENA_Pos) /*!< DWT CTRL: PCSAMPLENA Mask */ + +#define DWT_CTRL_SYNCTAP_Pos 10U /*!< DWT CTRL: SYNCTAP Position */ +#define DWT_CTRL_SYNCTAP_Msk (0x3UL << DWT_CTRL_SYNCTAP_Pos) /*!< DWT CTRL: SYNCTAP Mask */ + +#define DWT_CTRL_CYCTAP_Pos 9U /*!< DWT CTRL: CYCTAP Position */ +#define DWT_CTRL_CYCTAP_Msk (0x1UL << DWT_CTRL_CYCTAP_Pos) /*!< DWT CTRL: CYCTAP Mask */ + +#define DWT_CTRL_POSTINIT_Pos 5U /*!< DWT CTRL: POSTINIT Position */ +#define DWT_CTRL_POSTINIT_Msk (0xFUL << DWT_CTRL_POSTINIT_Pos) /*!< DWT CTRL: POSTINIT Mask */ + +#define DWT_CTRL_POSTPRESET_Pos 1U /*!< DWT CTRL: POSTPRESET Position */ +#define DWT_CTRL_POSTPRESET_Msk (0xFUL << DWT_CTRL_POSTPRESET_Pos) /*!< DWT CTRL: POSTPRESET Mask */ + +#define DWT_CTRL_CYCCNTENA_Pos 0U /*!< DWT CTRL: CYCCNTENA Position */ +#define DWT_CTRL_CYCCNTENA_Msk (0x1UL /*<< DWT_CTRL_CYCCNTENA_Pos*/) /*!< DWT CTRL: CYCCNTENA Mask */ + +/* DWT CPI Count Register Definitions */ +#define DWT_CPICNT_CPICNT_Pos 0U /*!< DWT CPICNT: CPICNT Position */ +#define DWT_CPICNT_CPICNT_Msk (0xFFUL /*<< DWT_CPICNT_CPICNT_Pos*/) /*!< DWT CPICNT: CPICNT Mask */ + +/* DWT Exception Overhead Count Register Definitions */ +#define DWT_EXCCNT_EXCCNT_Pos 0U /*!< DWT EXCCNT: EXCCNT Position */ +#define DWT_EXCCNT_EXCCNT_Msk (0xFFUL /*<< DWT_EXCCNT_EXCCNT_Pos*/) /*!< DWT EXCCNT: EXCCNT Mask */ + +/* DWT Sleep Count Register Definitions */ +#define DWT_SLEEPCNT_SLEEPCNT_Pos 0U /*!< DWT SLEEPCNT: SLEEPCNT Position */ +#define DWT_SLEEPCNT_SLEEPCNT_Msk (0xFFUL /*<< DWT_SLEEPCNT_SLEEPCNT_Pos*/) /*!< DWT SLEEPCNT: SLEEPCNT Mask */ + +/* DWT LSU Count Register Definitions */ +#define DWT_LSUCNT_LSUCNT_Pos 0U /*!< DWT LSUCNT: LSUCNT Position */ +#define DWT_LSUCNT_LSUCNT_Msk (0xFFUL /*<< DWT_LSUCNT_LSUCNT_Pos*/) /*!< DWT LSUCNT: LSUCNT Mask */ + +/* DWT Folded-instruction Count Register Definitions */ +#define DWT_FOLDCNT_FOLDCNT_Pos 0U /*!< DWT FOLDCNT: FOLDCNT Position */ +#define DWT_FOLDCNT_FOLDCNT_Msk (0xFFUL /*<< DWT_FOLDCNT_FOLDCNT_Pos*/) /*!< DWT FOLDCNT: FOLDCNT Mask */ + +/* DWT Comparator Mask Register Definitions */ +#define DWT_MASK_MASK_Pos 0U /*!< DWT MASK: MASK Position */ +#define DWT_MASK_MASK_Msk (0x1FUL /*<< DWT_MASK_MASK_Pos*/) /*!< DWT MASK: MASK Mask */ + +/* DWT Comparator Function Register Definitions */ +#define DWT_FUNCTION_MATCHED_Pos 24U /*!< DWT FUNCTION: MATCHED Position */ +#define DWT_FUNCTION_MATCHED_Msk (0x1UL << DWT_FUNCTION_MATCHED_Pos) /*!< DWT FUNCTION: MATCHED Mask */ + +#define DWT_FUNCTION_DATAVADDR1_Pos 16U /*!< DWT FUNCTION: DATAVADDR1 Position */ +#define DWT_FUNCTION_DATAVADDR1_Msk (0xFUL << DWT_FUNCTION_DATAVADDR1_Pos) /*!< DWT FUNCTION: DATAVADDR1 Mask */ + +#define DWT_FUNCTION_DATAVADDR0_Pos 12U /*!< DWT FUNCTION: DATAVADDR0 Position */ +#define DWT_FUNCTION_DATAVADDR0_Msk (0xFUL << DWT_FUNCTION_DATAVADDR0_Pos) /*!< DWT FUNCTION: DATAVADDR0 Mask */ + +#define DWT_FUNCTION_DATAVSIZE_Pos 10U /*!< DWT FUNCTION: DATAVSIZE Position */ +#define DWT_FUNCTION_DATAVSIZE_Msk (0x3UL << DWT_FUNCTION_DATAVSIZE_Pos) /*!< DWT FUNCTION: DATAVSIZE Mask */ + +#define DWT_FUNCTION_LNK1ENA_Pos 9U /*!< DWT FUNCTION: LNK1ENA Position */ +#define DWT_FUNCTION_LNK1ENA_Msk (0x1UL << DWT_FUNCTION_LNK1ENA_Pos) /*!< DWT FUNCTION: LNK1ENA Mask */ + +#define DWT_FUNCTION_DATAVMATCH_Pos 8U /*!< DWT FUNCTION: DATAVMATCH Position */ +#define DWT_FUNCTION_DATAVMATCH_Msk (0x1UL << DWT_FUNCTION_DATAVMATCH_Pos) /*!< DWT FUNCTION: DATAVMATCH Mask */ + +#define DWT_FUNCTION_CYCMATCH_Pos 7U /*!< DWT FUNCTION: CYCMATCH Position */ +#define DWT_FUNCTION_CYCMATCH_Msk (0x1UL << DWT_FUNCTION_CYCMATCH_Pos) /*!< DWT FUNCTION: CYCMATCH Mask */ + +#define DWT_FUNCTION_EMITRANGE_Pos 5U /*!< DWT FUNCTION: EMITRANGE Position */ +#define DWT_FUNCTION_EMITRANGE_Msk (0x1UL << DWT_FUNCTION_EMITRANGE_Pos) /*!< DWT FUNCTION: EMITRANGE Mask */ + +#define DWT_FUNCTION_FUNCTION_Pos 0U /*!< DWT FUNCTION: FUNCTION Position */ +#define DWT_FUNCTION_FUNCTION_Msk (0xFUL /*<< DWT_FUNCTION_FUNCTION_Pos*/) /*!< DWT FUNCTION: FUNCTION Mask */ + +/*@}*/ /* end of group CMSIS_DWT */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_TPI Trace Port Interface (TPI) + \brief Type definitions for the Trace Port Interface (TPI) + @{ + */ + +/** + \brief Structure type to access the Trace Port Interface Register (TPI). + */ +typedef struct +{ + __IOM uint32_t SSPSR; /*!< Offset: 0x000 (R/ ) Supported Parallel Port Size Register */ + __IOM uint32_t CSPSR; /*!< Offset: 0x004 (R/W) Current Parallel Port Size Register */ + uint32_t RESERVED0[2U]; + __IOM uint32_t ACPR; /*!< Offset: 0x010 (R/W) Asynchronous Clock Prescaler Register */ + uint32_t RESERVED1[55U]; + __IOM uint32_t SPPR; /*!< Offset: 0x0F0 (R/W) Selected Pin Protocol Register */ + uint32_t RESERVED2[131U]; + __IM uint32_t FFSR; /*!< Offset: 0x300 (R/ ) Formatter and Flush Status Register */ + __IOM uint32_t FFCR; /*!< Offset: 0x304 (R/W) Formatter and Flush Control Register */ + __IM uint32_t FSCR; /*!< Offset: 0x308 (R/ ) Formatter Synchronization Counter Register */ + uint32_t RESERVED3[759U]; + __IM uint32_t TRIGGER; /*!< Offset: 0xEE8 (R/ ) TRIGGER */ + __IM uint32_t FIFO0; /*!< Offset: 0xEEC (R/ ) Integration ETM Data */ + __IM uint32_t ITATBCTR2; /*!< Offset: 0xEF0 (R/ ) ITATBCTR2 */ + uint32_t RESERVED4[1U]; + __IM uint32_t ITATBCTR0; /*!< Offset: 0xEF8 (R/ ) ITATBCTR0 */ + __IM uint32_t FIFO1; /*!< Offset: 0xEFC (R/ ) Integration ITM Data */ + __IOM uint32_t ITCTRL; /*!< Offset: 0xF00 (R/W) Integration Mode Control */ + uint32_t RESERVED5[39U]; + __IOM uint32_t CLAIMSET; /*!< Offset: 0xFA0 (R/W) Claim tag set */ + __IOM uint32_t CLAIMCLR; /*!< Offset: 0xFA4 (R/W) Claim tag clear */ + uint32_t RESERVED7[8U]; + __IM uint32_t DEVID; /*!< Offset: 0xFC8 (R/ ) TPIU_DEVID */ + __IM uint32_t DEVTYPE; /*!< Offset: 0xFCC (R/ ) TPIU_DEVTYPE */ +} TPI_Type; + +/* TPI Asynchronous Clock Prescaler Register Definitions */ +#define TPI_ACPR_PRESCALER_Pos 0U /*!< TPI ACPR: PRESCALER Position */ +#define TPI_ACPR_PRESCALER_Msk (0x1FFFUL /*<< TPI_ACPR_PRESCALER_Pos*/) /*!< TPI ACPR: PRESCALER Mask */ + +/* TPI Selected Pin Protocol Register Definitions */ +#define TPI_SPPR_TXMODE_Pos 0U /*!< TPI SPPR: TXMODE Position */ +#define TPI_SPPR_TXMODE_Msk (0x3UL /*<< TPI_SPPR_TXMODE_Pos*/) /*!< TPI SPPR: TXMODE Mask */ + +/* TPI Formatter and Flush Status Register Definitions */ +#define TPI_FFSR_FtNonStop_Pos 3U /*!< TPI FFSR: FtNonStop Position */ +#define TPI_FFSR_FtNonStop_Msk (0x1UL << TPI_FFSR_FtNonStop_Pos) /*!< TPI FFSR: FtNonStop Mask */ + +#define TPI_FFSR_TCPresent_Pos 2U /*!< TPI FFSR: TCPresent Position */ +#define TPI_FFSR_TCPresent_Msk (0x1UL << TPI_FFSR_TCPresent_Pos) /*!< TPI FFSR: TCPresent Mask */ + +#define TPI_FFSR_FtStopped_Pos 1U /*!< TPI FFSR: FtStopped Position */ +#define TPI_FFSR_FtStopped_Msk (0x1UL << TPI_FFSR_FtStopped_Pos) /*!< TPI FFSR: FtStopped Mask */ + +#define TPI_FFSR_FlInProg_Pos 0U /*!< TPI FFSR: FlInProg Position */ +#define TPI_FFSR_FlInProg_Msk (0x1UL /*<< TPI_FFSR_FlInProg_Pos*/) /*!< TPI FFSR: FlInProg Mask */ + +/* TPI Formatter and Flush Control Register Definitions */ +#define TPI_FFCR_TrigIn_Pos 8U /*!< TPI FFCR: TrigIn Position */ +#define TPI_FFCR_TrigIn_Msk (0x1UL << TPI_FFCR_TrigIn_Pos) /*!< TPI FFCR: TrigIn Mask */ + +#define TPI_FFCR_EnFCont_Pos 1U /*!< TPI FFCR: EnFCont Position */ +#define TPI_FFCR_EnFCont_Msk (0x1UL << TPI_FFCR_EnFCont_Pos) /*!< TPI FFCR: EnFCont Mask */ + +/* TPI TRIGGER Register Definitions */ +#define TPI_TRIGGER_TRIGGER_Pos 0U /*!< TPI TRIGGER: TRIGGER Position */ +#define TPI_TRIGGER_TRIGGER_Msk (0x1UL /*<< TPI_TRIGGER_TRIGGER_Pos*/) /*!< TPI TRIGGER: TRIGGER Mask */ + +/* TPI Integration ETM Data Register Definitions (FIFO0) */ +#define TPI_FIFO0_ITM_ATVALID_Pos 29U /*!< TPI FIFO0: ITM_ATVALID Position */ +#define TPI_FIFO0_ITM_ATVALID_Msk (0x3UL << TPI_FIFO0_ITM_ATVALID_Pos) /*!< TPI FIFO0: ITM_ATVALID Mask */ + +#define TPI_FIFO0_ITM_bytecount_Pos 27U /*!< TPI FIFO0: ITM_bytecount Position */ +#define TPI_FIFO0_ITM_bytecount_Msk (0x3UL << TPI_FIFO0_ITM_bytecount_Pos) /*!< TPI FIFO0: ITM_bytecount Mask */ + +#define TPI_FIFO0_ETM_ATVALID_Pos 26U /*!< TPI FIFO0: ETM_ATVALID Position */ +#define TPI_FIFO0_ETM_ATVALID_Msk (0x3UL << TPI_FIFO0_ETM_ATVALID_Pos) /*!< TPI FIFO0: ETM_ATVALID Mask */ + +#define TPI_FIFO0_ETM_bytecount_Pos 24U /*!< TPI FIFO0: ETM_bytecount Position */ +#define TPI_FIFO0_ETM_bytecount_Msk (0x3UL << TPI_FIFO0_ETM_bytecount_Pos) /*!< TPI FIFO0: ETM_bytecount Mask */ + +#define TPI_FIFO0_ETM2_Pos 16U /*!< TPI FIFO0: ETM2 Position */ +#define TPI_FIFO0_ETM2_Msk (0xFFUL << TPI_FIFO0_ETM2_Pos) /*!< TPI FIFO0: ETM2 Mask */ + +#define TPI_FIFO0_ETM1_Pos 8U /*!< TPI FIFO0: ETM1 Position */ +#define TPI_FIFO0_ETM1_Msk (0xFFUL << TPI_FIFO0_ETM1_Pos) /*!< TPI FIFO0: ETM1 Mask */ + +#define TPI_FIFO0_ETM0_Pos 0U /*!< TPI FIFO0: ETM0 Position */ +#define TPI_FIFO0_ETM0_Msk (0xFFUL /*<< TPI_FIFO0_ETM0_Pos*/) /*!< TPI FIFO0: ETM0 Mask */ + +/* TPI ITATBCTR2 Register Definitions */ +#define TPI_ITATBCTR2_ATREADY_Pos 0U /*!< TPI ITATBCTR2: ATREADY Position */ +#define TPI_ITATBCTR2_ATREADY_Msk (0x1UL /*<< TPI_ITATBCTR2_ATREADY_Pos*/) /*!< TPI ITATBCTR2: ATREADY Mask */ + +/* TPI Integration ITM Data Register Definitions (FIFO1) */ +#define TPI_FIFO1_ITM_ATVALID_Pos 29U /*!< TPI FIFO1: ITM_ATVALID Position */ +#define TPI_FIFO1_ITM_ATVALID_Msk (0x3UL << TPI_FIFO1_ITM_ATVALID_Pos) /*!< TPI FIFO1: ITM_ATVALID Mask */ + +#define TPI_FIFO1_ITM_bytecount_Pos 27U /*!< TPI FIFO1: ITM_bytecount Position */ +#define TPI_FIFO1_ITM_bytecount_Msk (0x3UL << TPI_FIFO1_ITM_bytecount_Pos) /*!< TPI FIFO1: ITM_bytecount Mask */ + +#define TPI_FIFO1_ETM_ATVALID_Pos 26U /*!< TPI FIFO1: ETM_ATVALID Position */ +#define TPI_FIFO1_ETM_ATVALID_Msk (0x3UL << TPI_FIFO1_ETM_ATVALID_Pos) /*!< TPI FIFO1: ETM_ATVALID Mask */ + +#define TPI_FIFO1_ETM_bytecount_Pos 24U /*!< TPI FIFO1: ETM_bytecount Position */ +#define TPI_FIFO1_ETM_bytecount_Msk (0x3UL << TPI_FIFO1_ETM_bytecount_Pos) /*!< TPI FIFO1: ETM_bytecount Mask */ + +#define TPI_FIFO1_ITM2_Pos 16U /*!< TPI FIFO1: ITM2 Position */ +#define TPI_FIFO1_ITM2_Msk (0xFFUL << TPI_FIFO1_ITM2_Pos) /*!< TPI FIFO1: ITM2 Mask */ + +#define TPI_FIFO1_ITM1_Pos 8U /*!< TPI FIFO1: ITM1 Position */ +#define TPI_FIFO1_ITM1_Msk (0xFFUL << TPI_FIFO1_ITM1_Pos) /*!< TPI FIFO1: ITM1 Mask */ + +#define TPI_FIFO1_ITM0_Pos 0U /*!< TPI FIFO1: ITM0 Position */ +#define TPI_FIFO1_ITM0_Msk (0xFFUL /*<< TPI_FIFO1_ITM0_Pos*/) /*!< TPI FIFO1: ITM0 Mask */ + +/* TPI ITATBCTR0 Register Definitions */ +#define TPI_ITATBCTR0_ATREADY_Pos 0U /*!< TPI ITATBCTR0: ATREADY Position */ +#define TPI_ITATBCTR0_ATREADY_Msk (0x1UL /*<< TPI_ITATBCTR0_ATREADY_Pos*/) /*!< TPI ITATBCTR0: ATREADY Mask */ + +/* TPI Integration Mode Control Register Definitions */ +#define TPI_ITCTRL_Mode_Pos 0U /*!< TPI ITCTRL: Mode Position */ +#define TPI_ITCTRL_Mode_Msk (0x1UL /*<< TPI_ITCTRL_Mode_Pos*/) /*!< TPI ITCTRL: Mode Mask */ + +/* TPI DEVID Register Definitions */ +#define TPI_DEVID_NRZVALID_Pos 11U /*!< TPI DEVID: NRZVALID Position */ +#define TPI_DEVID_NRZVALID_Msk (0x1UL << TPI_DEVID_NRZVALID_Pos) /*!< TPI DEVID: NRZVALID Mask */ + +#define TPI_DEVID_MANCVALID_Pos 10U /*!< TPI DEVID: MANCVALID Position */ +#define TPI_DEVID_MANCVALID_Msk (0x1UL << TPI_DEVID_MANCVALID_Pos) /*!< TPI DEVID: MANCVALID Mask */ + +#define TPI_DEVID_PTINVALID_Pos 9U /*!< TPI DEVID: PTINVALID Position */ +#define TPI_DEVID_PTINVALID_Msk (0x1UL << TPI_DEVID_PTINVALID_Pos) /*!< TPI DEVID: PTINVALID Mask */ + +#define TPI_DEVID_MinBufSz_Pos 6U /*!< TPI DEVID: MinBufSz Position */ +#define TPI_DEVID_MinBufSz_Msk (0x7UL << TPI_DEVID_MinBufSz_Pos) /*!< TPI DEVID: MinBufSz Mask */ + +#define TPI_DEVID_AsynClkIn_Pos 5U /*!< TPI DEVID: AsynClkIn Position */ +#define TPI_DEVID_AsynClkIn_Msk (0x1UL << TPI_DEVID_AsynClkIn_Pos) /*!< TPI DEVID: AsynClkIn Mask */ + +#define TPI_DEVID_NrTraceInput_Pos 0U /*!< TPI DEVID: NrTraceInput Position */ +#define TPI_DEVID_NrTraceInput_Msk (0x1FUL /*<< TPI_DEVID_NrTraceInput_Pos*/) /*!< TPI DEVID: NrTraceInput Mask */ + +/* TPI DEVTYPE Register Definitions */ +#define TPI_DEVTYPE_MajorType_Pos 4U /*!< TPI DEVTYPE: MajorType Position */ +#define TPI_DEVTYPE_MajorType_Msk (0xFUL << TPI_DEVTYPE_MajorType_Pos) /*!< TPI DEVTYPE: MajorType Mask */ + +#define TPI_DEVTYPE_SubType_Pos 0U /*!< TPI DEVTYPE: SubType Position */ +#define TPI_DEVTYPE_SubType_Msk (0xFUL /*<< TPI_DEVTYPE_SubType_Pos*/) /*!< TPI DEVTYPE: SubType Mask */ + +/*@}*/ /* end of group CMSIS_TPI */ + + +#if (__MPU_PRESENT == 1U) +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_MPU Memory Protection Unit (MPU) + \brief Type definitions for the Memory Protection Unit (MPU) + @{ + */ + +/** + \brief Structure type to access the Memory Protection Unit (MPU). + */ +typedef struct +{ + __IM uint32_t TYPE; /*!< Offset: 0x000 (R/ ) MPU Type Register */ + __IOM uint32_t CTRL; /*!< Offset: 0x004 (R/W) MPU Control Register */ + __IOM uint32_t RNR; /*!< Offset: 0x008 (R/W) MPU Region RNRber Register */ + __IOM uint32_t RBAR; /*!< Offset: 0x00C (R/W) MPU Region Base Address Register */ + __IOM uint32_t RASR; /*!< Offset: 0x010 (R/W) MPU Region Attribute and Size Register */ + __IOM uint32_t RBAR_A1; /*!< Offset: 0x014 (R/W) MPU Alias 1 Region Base Address Register */ + __IOM uint32_t RASR_A1; /*!< Offset: 0x018 (R/W) MPU Alias 1 Region Attribute and Size Register */ + __IOM uint32_t RBAR_A2; /*!< Offset: 0x01C (R/W) MPU Alias 2 Region Base Address Register */ + __IOM uint32_t RASR_A2; /*!< Offset: 0x020 (R/W) MPU Alias 2 Region Attribute and Size Register */ + __IOM uint32_t RBAR_A3; /*!< Offset: 0x024 (R/W) MPU Alias 3 Region Base Address Register */ + __IOM uint32_t RASR_A3; /*!< Offset: 0x028 (R/W) MPU Alias 3 Region Attribute and Size Register */ +} MPU_Type; + +/* MPU Type Register Definitions */ +#define MPU_TYPE_IREGION_Pos 16U /*!< MPU TYPE: IREGION Position */ +#define MPU_TYPE_IREGION_Msk (0xFFUL << MPU_TYPE_IREGION_Pos) /*!< MPU TYPE: IREGION Mask */ + +#define MPU_TYPE_DREGION_Pos 8U /*!< MPU TYPE: DREGION Position */ +#define MPU_TYPE_DREGION_Msk (0xFFUL << MPU_TYPE_DREGION_Pos) /*!< MPU TYPE: DREGION Mask */ + +#define MPU_TYPE_SEPARATE_Pos 0U /*!< MPU TYPE: SEPARATE Position */ +#define MPU_TYPE_SEPARATE_Msk (1UL /*<< MPU_TYPE_SEPARATE_Pos*/) /*!< MPU TYPE: SEPARATE Mask */ + +/* MPU Control Register Definitions */ +#define MPU_CTRL_PRIVDEFENA_Pos 2U /*!< MPU CTRL: PRIVDEFENA Position */ +#define MPU_CTRL_PRIVDEFENA_Msk (1UL << MPU_CTRL_PRIVDEFENA_Pos) /*!< MPU CTRL: PRIVDEFENA Mask */ + +#define MPU_CTRL_HFNMIENA_Pos 1U /*!< MPU CTRL: HFNMIENA Position */ +#define MPU_CTRL_HFNMIENA_Msk (1UL << MPU_CTRL_HFNMIENA_Pos) /*!< MPU CTRL: HFNMIENA Mask */ + +#define MPU_CTRL_ENABLE_Pos 0U /*!< MPU CTRL: ENABLE Position */ +#define MPU_CTRL_ENABLE_Msk (1UL /*<< MPU_CTRL_ENABLE_Pos*/) /*!< MPU CTRL: ENABLE Mask */ + +/* MPU Region Number Register Definitions */ +#define MPU_RNR_REGION_Pos 0U /*!< MPU RNR: REGION Position */ +#define MPU_RNR_REGION_Msk (0xFFUL /*<< MPU_RNR_REGION_Pos*/) /*!< MPU RNR: REGION Mask */ + +/* MPU Region Base Address Register Definitions */ +#define MPU_RBAR_ADDR_Pos 5U /*!< MPU RBAR: ADDR Position */ +#define MPU_RBAR_ADDR_Msk (0x7FFFFFFUL << MPU_RBAR_ADDR_Pos) /*!< MPU RBAR: ADDR Mask */ + +#define MPU_RBAR_VALID_Pos 4U /*!< MPU RBAR: VALID Position */ +#define MPU_RBAR_VALID_Msk (1UL << MPU_RBAR_VALID_Pos) /*!< MPU RBAR: VALID Mask */ + +#define MPU_RBAR_REGION_Pos 0U /*!< MPU RBAR: REGION Position */ +#define MPU_RBAR_REGION_Msk (0xFUL /*<< MPU_RBAR_REGION_Pos*/) /*!< MPU RBAR: REGION Mask */ + +/* MPU Region Attribute and Size Register Definitions */ +#define MPU_RASR_ATTRS_Pos 16U /*!< MPU RASR: MPU Region Attribute field Position */ +#define MPU_RASR_ATTRS_Msk (0xFFFFUL << MPU_RASR_ATTRS_Pos) /*!< MPU RASR: MPU Region Attribute field Mask */ + +#define MPU_RASR_XN_Pos 28U /*!< MPU RASR: ATTRS.XN Position */ +#define MPU_RASR_XN_Msk (1UL << MPU_RASR_XN_Pos) /*!< MPU RASR: ATTRS.XN Mask */ + +#define MPU_RASR_AP_Pos 24U /*!< MPU RASR: ATTRS.AP Position */ +#define MPU_RASR_AP_Msk (0x7UL << MPU_RASR_AP_Pos) /*!< MPU RASR: ATTRS.AP Mask */ + +#define MPU_RASR_TEX_Pos 19U /*!< MPU RASR: ATTRS.TEX Position */ +#define MPU_RASR_TEX_Msk (0x7UL << MPU_RASR_TEX_Pos) /*!< MPU RASR: ATTRS.TEX Mask */ + +#define MPU_RASR_S_Pos 18U /*!< MPU RASR: ATTRS.S Position */ +#define MPU_RASR_S_Msk (1UL << MPU_RASR_S_Pos) /*!< MPU RASR: ATTRS.S Mask */ + +#define MPU_RASR_C_Pos 17U /*!< MPU RASR: ATTRS.C Position */ +#define MPU_RASR_C_Msk (1UL << MPU_RASR_C_Pos) /*!< MPU RASR: ATTRS.C Mask */ + +#define MPU_RASR_B_Pos 16U /*!< MPU RASR: ATTRS.B Position */ +#define MPU_RASR_B_Msk (1UL << MPU_RASR_B_Pos) /*!< MPU RASR: ATTRS.B Mask */ + +#define MPU_RASR_SRD_Pos 8U /*!< MPU RASR: Sub-Region Disable Position */ +#define MPU_RASR_SRD_Msk (0xFFUL << MPU_RASR_SRD_Pos) /*!< MPU RASR: Sub-Region Disable Mask */ + +#define MPU_RASR_SIZE_Pos 1U /*!< MPU RASR: Region Size Field Position */ +#define MPU_RASR_SIZE_Msk (0x1FUL << MPU_RASR_SIZE_Pos) /*!< MPU RASR: Region Size Field Mask */ + +#define MPU_RASR_ENABLE_Pos 0U /*!< MPU RASR: Region enable bit Position */ +#define MPU_RASR_ENABLE_Msk (1UL /*<< MPU_RASR_ENABLE_Pos*/) /*!< MPU RASR: Region enable bit Disable Mask */ + +/*@} end of group CMSIS_MPU */ +#endif + + +#if (__FPU_PRESENT == 1U) +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_FPU Floating Point Unit (FPU) + \brief Type definitions for the Floating Point Unit (FPU) + @{ + */ + +/** + \brief Structure type to access the Floating Point Unit (FPU). + */ +typedef struct +{ + uint32_t RESERVED0[1U]; + __IOM uint32_t FPCCR; /*!< Offset: 0x004 (R/W) Floating-Point Context Control Register */ + __IOM uint32_t FPCAR; /*!< Offset: 0x008 (R/W) Floating-Point Context Address Register */ + __IOM uint32_t FPDSCR; /*!< Offset: 0x00C (R/W) Floating-Point Default Status Control Register */ + __IM uint32_t MVFR0; /*!< Offset: 0x010 (R/ ) Media and FP Feature Register 0 */ + __IM uint32_t MVFR1; /*!< Offset: 0x014 (R/ ) Media and FP Feature Register 1 */ +} FPU_Type; + +/* Floating-Point Context Control Register Definitions */ +#define FPU_FPCCR_ASPEN_Pos 31U /*!< FPCCR: ASPEN bit Position */ +#define FPU_FPCCR_ASPEN_Msk (1UL << FPU_FPCCR_ASPEN_Pos) /*!< FPCCR: ASPEN bit Mask */ + +#define FPU_FPCCR_LSPEN_Pos 30U /*!< FPCCR: LSPEN Position */ +#define FPU_FPCCR_LSPEN_Msk (1UL << FPU_FPCCR_LSPEN_Pos) /*!< FPCCR: LSPEN bit Mask */ + +#define FPU_FPCCR_MONRDY_Pos 8U /*!< FPCCR: MONRDY Position */ +#define FPU_FPCCR_MONRDY_Msk (1UL << FPU_FPCCR_MONRDY_Pos) /*!< FPCCR: MONRDY bit Mask */ + +#define FPU_FPCCR_BFRDY_Pos 6U /*!< FPCCR: BFRDY Position */ +#define FPU_FPCCR_BFRDY_Msk (1UL << FPU_FPCCR_BFRDY_Pos) /*!< FPCCR: BFRDY bit Mask */ + +#define FPU_FPCCR_MMRDY_Pos 5U /*!< FPCCR: MMRDY Position */ +#define FPU_FPCCR_MMRDY_Msk (1UL << FPU_FPCCR_MMRDY_Pos) /*!< FPCCR: MMRDY bit Mask */ + +#define FPU_FPCCR_HFRDY_Pos 4U /*!< FPCCR: HFRDY Position */ +#define FPU_FPCCR_HFRDY_Msk (1UL << FPU_FPCCR_HFRDY_Pos) /*!< FPCCR: HFRDY bit Mask */ + +#define FPU_FPCCR_THREAD_Pos 3U /*!< FPCCR: processor mode bit Position */ +#define FPU_FPCCR_THREAD_Msk (1UL << FPU_FPCCR_THREAD_Pos) /*!< FPCCR: processor mode active bit Mask */ + +#define FPU_FPCCR_USER_Pos 1U /*!< FPCCR: privilege level bit Position */ +#define FPU_FPCCR_USER_Msk (1UL << FPU_FPCCR_USER_Pos) /*!< FPCCR: privilege level bit Mask */ + +#define FPU_FPCCR_LSPACT_Pos 0U /*!< FPCCR: Lazy state preservation active bit Position */ +#define FPU_FPCCR_LSPACT_Msk (1UL /*<< FPU_FPCCR_LSPACT_Pos*/) /*!< FPCCR: Lazy state preservation active bit Mask */ + +/* Floating-Point Context Address Register Definitions */ +#define FPU_FPCAR_ADDRESS_Pos 3U /*!< FPCAR: ADDRESS bit Position */ +#define FPU_FPCAR_ADDRESS_Msk (0x1FFFFFFFUL << FPU_FPCAR_ADDRESS_Pos) /*!< FPCAR: ADDRESS bit Mask */ + +/* Floating-Point Default Status Control Register Definitions */ +#define FPU_FPDSCR_AHP_Pos 26U /*!< FPDSCR: AHP bit Position */ +#define FPU_FPDSCR_AHP_Msk (1UL << FPU_FPDSCR_AHP_Pos) /*!< FPDSCR: AHP bit Mask */ + +#define FPU_FPDSCR_DN_Pos 25U /*!< FPDSCR: DN bit Position */ +#define FPU_FPDSCR_DN_Msk (1UL << FPU_FPDSCR_DN_Pos) /*!< FPDSCR: DN bit Mask */ + +#define FPU_FPDSCR_FZ_Pos 24U /*!< FPDSCR: FZ bit Position */ +#define FPU_FPDSCR_FZ_Msk (1UL << FPU_FPDSCR_FZ_Pos) /*!< FPDSCR: FZ bit Mask */ + +#define FPU_FPDSCR_RMode_Pos 22U /*!< FPDSCR: RMode bit Position */ +#define FPU_FPDSCR_RMode_Msk (3UL << FPU_FPDSCR_RMode_Pos) /*!< FPDSCR: RMode bit Mask */ + +/* Media and FP Feature Register 0 Definitions */ +#define FPU_MVFR0_FP_rounding_modes_Pos 28U /*!< MVFR0: FP rounding modes bits Position */ +#define FPU_MVFR0_FP_rounding_modes_Msk (0xFUL << FPU_MVFR0_FP_rounding_modes_Pos) /*!< MVFR0: FP rounding modes bits Mask */ + +#define FPU_MVFR0_Short_vectors_Pos 24U /*!< MVFR0: Short vectors bits Position */ +#define FPU_MVFR0_Short_vectors_Msk (0xFUL << FPU_MVFR0_Short_vectors_Pos) /*!< MVFR0: Short vectors bits Mask */ + +#define FPU_MVFR0_Square_root_Pos 20U /*!< MVFR0: Square root bits Position */ +#define FPU_MVFR0_Square_root_Msk (0xFUL << FPU_MVFR0_Square_root_Pos) /*!< MVFR0: Square root bits Mask */ + +#define FPU_MVFR0_Divide_Pos 16U /*!< MVFR0: Divide bits Position */ +#define FPU_MVFR0_Divide_Msk (0xFUL << FPU_MVFR0_Divide_Pos) /*!< MVFR0: Divide bits Mask */ + +#define FPU_MVFR0_FP_excep_trapping_Pos 12U /*!< MVFR0: FP exception trapping bits Position */ +#define FPU_MVFR0_FP_excep_trapping_Msk (0xFUL << FPU_MVFR0_FP_excep_trapping_Pos) /*!< MVFR0: FP exception trapping bits Mask */ + +#define FPU_MVFR0_Double_precision_Pos 8U /*!< MVFR0: Double-precision bits Position */ +#define FPU_MVFR0_Double_precision_Msk (0xFUL << FPU_MVFR0_Double_precision_Pos) /*!< MVFR0: Double-precision bits Mask */ + +#define FPU_MVFR0_Single_precision_Pos 4U /*!< MVFR0: Single-precision bits Position */ +#define FPU_MVFR0_Single_precision_Msk (0xFUL << FPU_MVFR0_Single_precision_Pos) /*!< MVFR0: Single-precision bits Mask */ + +#define FPU_MVFR0_A_SIMD_registers_Pos 0U /*!< MVFR0: A_SIMD registers bits Position */ +#define FPU_MVFR0_A_SIMD_registers_Msk (0xFUL /*<< FPU_MVFR0_A_SIMD_registers_Pos*/) /*!< MVFR0: A_SIMD registers bits Mask */ + +/* Media and FP Feature Register 1 Definitions */ +#define FPU_MVFR1_FP_fused_MAC_Pos 28U /*!< MVFR1: FP fused MAC bits Position */ +#define FPU_MVFR1_FP_fused_MAC_Msk (0xFUL << FPU_MVFR1_FP_fused_MAC_Pos) /*!< MVFR1: FP fused MAC bits Mask */ + +#define FPU_MVFR1_FP_HPFP_Pos 24U /*!< MVFR1: FP HPFP bits Position */ +#define FPU_MVFR1_FP_HPFP_Msk (0xFUL << FPU_MVFR1_FP_HPFP_Pos) /*!< MVFR1: FP HPFP bits Mask */ + +#define FPU_MVFR1_D_NaN_mode_Pos 4U /*!< MVFR1: D_NaN mode bits Position */ +#define FPU_MVFR1_D_NaN_mode_Msk (0xFUL << FPU_MVFR1_D_NaN_mode_Pos) /*!< MVFR1: D_NaN mode bits Mask */ + +#define FPU_MVFR1_FtZ_mode_Pos 0U /*!< MVFR1: FtZ mode bits Position */ +#define FPU_MVFR1_FtZ_mode_Msk (0xFUL /*<< FPU_MVFR1_FtZ_mode_Pos*/) /*!< MVFR1: FtZ mode bits Mask */ + +/*@} end of group CMSIS_FPU */ +#endif + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_CoreDebug Core Debug Registers (CoreDebug) + \brief Type definitions for the Core Debug Registers + @{ + */ + +/** + \brief Structure type to access the Core Debug Register (CoreDebug). + */ +typedef struct +{ + __IOM uint32_t DHCSR; /*!< Offset: 0x000 (R/W) Debug Halting Control and Status Register */ + __OM uint32_t DCRSR; /*!< Offset: 0x004 ( /W) Debug Core Register Selector Register */ + __IOM uint32_t DCRDR; /*!< Offset: 0x008 (R/W) Debug Core Register Data Register */ + __IOM uint32_t DEMCR; /*!< Offset: 0x00C (R/W) Debug Exception and Monitor Control Register */ +} CoreDebug_Type; + +/* Debug Halting Control and Status Register Definitions */ +#define CoreDebug_DHCSR_DBGKEY_Pos 16U /*!< CoreDebug DHCSR: DBGKEY Position */ +#define CoreDebug_DHCSR_DBGKEY_Msk (0xFFFFUL << CoreDebug_DHCSR_DBGKEY_Pos) /*!< CoreDebug DHCSR: DBGKEY Mask */ + +#define CoreDebug_DHCSR_S_RESET_ST_Pos 25U /*!< CoreDebug DHCSR: S_RESET_ST Position */ +#define CoreDebug_DHCSR_S_RESET_ST_Msk (1UL << CoreDebug_DHCSR_S_RESET_ST_Pos) /*!< CoreDebug DHCSR: S_RESET_ST Mask */ + +#define CoreDebug_DHCSR_S_RETIRE_ST_Pos 24U /*!< CoreDebug DHCSR: S_RETIRE_ST Position */ +#define CoreDebug_DHCSR_S_RETIRE_ST_Msk (1UL << CoreDebug_DHCSR_S_RETIRE_ST_Pos) /*!< CoreDebug DHCSR: S_RETIRE_ST Mask */ + +#define CoreDebug_DHCSR_S_LOCKUP_Pos 19U /*!< CoreDebug DHCSR: S_LOCKUP Position */ +#define CoreDebug_DHCSR_S_LOCKUP_Msk (1UL << CoreDebug_DHCSR_S_LOCKUP_Pos) /*!< CoreDebug DHCSR: S_LOCKUP Mask */ + +#define CoreDebug_DHCSR_S_SLEEP_Pos 18U /*!< CoreDebug DHCSR: S_SLEEP Position */ +#define CoreDebug_DHCSR_S_SLEEP_Msk (1UL << CoreDebug_DHCSR_S_SLEEP_Pos) /*!< CoreDebug DHCSR: S_SLEEP Mask */ + +#define CoreDebug_DHCSR_S_HALT_Pos 17U /*!< CoreDebug DHCSR: S_HALT Position */ +#define CoreDebug_DHCSR_S_HALT_Msk (1UL << CoreDebug_DHCSR_S_HALT_Pos) /*!< CoreDebug DHCSR: S_HALT Mask */ + +#define CoreDebug_DHCSR_S_REGRDY_Pos 16U /*!< CoreDebug DHCSR: S_REGRDY Position */ +#define CoreDebug_DHCSR_S_REGRDY_Msk (1UL << CoreDebug_DHCSR_S_REGRDY_Pos) /*!< CoreDebug DHCSR: S_REGRDY Mask */ + +#define CoreDebug_DHCSR_C_SNAPSTALL_Pos 5U /*!< CoreDebug DHCSR: C_SNAPSTALL Position */ +#define CoreDebug_DHCSR_C_SNAPSTALL_Msk (1UL << CoreDebug_DHCSR_C_SNAPSTALL_Pos) /*!< CoreDebug DHCSR: C_SNAPSTALL Mask */ + +#define CoreDebug_DHCSR_C_MASKINTS_Pos 3U /*!< CoreDebug DHCSR: C_MASKINTS Position */ +#define CoreDebug_DHCSR_C_MASKINTS_Msk (1UL << CoreDebug_DHCSR_C_MASKINTS_Pos) /*!< CoreDebug DHCSR: C_MASKINTS Mask */ + +#define CoreDebug_DHCSR_C_STEP_Pos 2U /*!< CoreDebug DHCSR: C_STEP Position */ +#define CoreDebug_DHCSR_C_STEP_Msk (1UL << CoreDebug_DHCSR_C_STEP_Pos) /*!< CoreDebug DHCSR: C_STEP Mask */ + +#define CoreDebug_DHCSR_C_HALT_Pos 1U /*!< CoreDebug DHCSR: C_HALT Position */ +#define CoreDebug_DHCSR_C_HALT_Msk (1UL << CoreDebug_DHCSR_C_HALT_Pos) /*!< CoreDebug DHCSR: C_HALT Mask */ + +#define CoreDebug_DHCSR_C_DEBUGEN_Pos 0U /*!< CoreDebug DHCSR: C_DEBUGEN Position */ +#define CoreDebug_DHCSR_C_DEBUGEN_Msk (1UL /*<< CoreDebug_DHCSR_C_DEBUGEN_Pos*/) /*!< CoreDebug DHCSR: C_DEBUGEN Mask */ + +/* Debug Core Register Selector Register Definitions */ +#define CoreDebug_DCRSR_REGWnR_Pos 16U /*!< CoreDebug DCRSR: REGWnR Position */ +#define CoreDebug_DCRSR_REGWnR_Msk (1UL << CoreDebug_DCRSR_REGWnR_Pos) /*!< CoreDebug DCRSR: REGWnR Mask */ + +#define CoreDebug_DCRSR_REGSEL_Pos 0U /*!< CoreDebug DCRSR: REGSEL Position */ +#define CoreDebug_DCRSR_REGSEL_Msk (0x1FUL /*<< CoreDebug_DCRSR_REGSEL_Pos*/) /*!< CoreDebug DCRSR: REGSEL Mask */ + +/* Debug Exception and Monitor Control Register Definitions */ +#define CoreDebug_DEMCR_TRCENA_Pos 24U /*!< CoreDebug DEMCR: TRCENA Position */ +#define CoreDebug_DEMCR_TRCENA_Msk (1UL << CoreDebug_DEMCR_TRCENA_Pos) /*!< CoreDebug DEMCR: TRCENA Mask */ + +#define CoreDebug_DEMCR_MON_REQ_Pos 19U /*!< CoreDebug DEMCR: MON_REQ Position */ +#define CoreDebug_DEMCR_MON_REQ_Msk (1UL << CoreDebug_DEMCR_MON_REQ_Pos) /*!< CoreDebug DEMCR: MON_REQ Mask */ + +#define CoreDebug_DEMCR_MON_STEP_Pos 18U /*!< CoreDebug DEMCR: MON_STEP Position */ +#define CoreDebug_DEMCR_MON_STEP_Msk (1UL << CoreDebug_DEMCR_MON_STEP_Pos) /*!< CoreDebug DEMCR: MON_STEP Mask */ + +#define CoreDebug_DEMCR_MON_PEND_Pos 17U /*!< CoreDebug DEMCR: MON_PEND Position */ +#define CoreDebug_DEMCR_MON_PEND_Msk (1UL << CoreDebug_DEMCR_MON_PEND_Pos) /*!< CoreDebug DEMCR: MON_PEND Mask */ + +#define CoreDebug_DEMCR_MON_EN_Pos 16U /*!< CoreDebug DEMCR: MON_EN Position */ +#define CoreDebug_DEMCR_MON_EN_Msk (1UL << CoreDebug_DEMCR_MON_EN_Pos) /*!< CoreDebug DEMCR: MON_EN Mask */ + +#define CoreDebug_DEMCR_VC_HARDERR_Pos 10U /*!< CoreDebug DEMCR: VC_HARDERR Position */ +#define CoreDebug_DEMCR_VC_HARDERR_Msk (1UL << CoreDebug_DEMCR_VC_HARDERR_Pos) /*!< CoreDebug DEMCR: VC_HARDERR Mask */ + +#define CoreDebug_DEMCR_VC_INTERR_Pos 9U /*!< CoreDebug DEMCR: VC_INTERR Position */ +#define CoreDebug_DEMCR_VC_INTERR_Msk (1UL << CoreDebug_DEMCR_VC_INTERR_Pos) /*!< CoreDebug DEMCR: VC_INTERR Mask */ + +#define CoreDebug_DEMCR_VC_BUSERR_Pos 8U /*!< CoreDebug DEMCR: VC_BUSERR Position */ +#define CoreDebug_DEMCR_VC_BUSERR_Msk (1UL << CoreDebug_DEMCR_VC_BUSERR_Pos) /*!< CoreDebug DEMCR: VC_BUSERR Mask */ + +#define CoreDebug_DEMCR_VC_STATERR_Pos 7U /*!< CoreDebug DEMCR: VC_STATERR Position */ +#define CoreDebug_DEMCR_VC_STATERR_Msk (1UL << CoreDebug_DEMCR_VC_STATERR_Pos) /*!< CoreDebug DEMCR: VC_STATERR Mask */ + +#define CoreDebug_DEMCR_VC_CHKERR_Pos 6U /*!< CoreDebug DEMCR: VC_CHKERR Position */ +#define CoreDebug_DEMCR_VC_CHKERR_Msk (1UL << CoreDebug_DEMCR_VC_CHKERR_Pos) /*!< CoreDebug DEMCR: VC_CHKERR Mask */ + +#define CoreDebug_DEMCR_VC_NOCPERR_Pos 5U /*!< CoreDebug DEMCR: VC_NOCPERR Position */ +#define CoreDebug_DEMCR_VC_NOCPERR_Msk (1UL << CoreDebug_DEMCR_VC_NOCPERR_Pos) /*!< CoreDebug DEMCR: VC_NOCPERR Mask */ + +#define CoreDebug_DEMCR_VC_MMERR_Pos 4U /*!< CoreDebug DEMCR: VC_MMERR Position */ +#define CoreDebug_DEMCR_VC_MMERR_Msk (1UL << CoreDebug_DEMCR_VC_MMERR_Pos) /*!< CoreDebug DEMCR: VC_MMERR Mask */ + +#define CoreDebug_DEMCR_VC_CORERESET_Pos 0U /*!< CoreDebug DEMCR: VC_CORERESET Position */ +#define CoreDebug_DEMCR_VC_CORERESET_Msk (1UL /*<< CoreDebug_DEMCR_VC_CORERESET_Pos*/) /*!< CoreDebug DEMCR: VC_CORERESET Mask */ + +/*@} end of group CMSIS_CoreDebug */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_core_bitfield Core register bit field macros + \brief Macros for use with bit field definitions (xxx_Pos, xxx_Msk). + @{ + */ + +/** + \brief Mask and shift a bit field value for use in a register bit range. + \param[in] field Name of the register bit field. + \param[in] value Value of the bit field. + \return Masked and shifted value. +*/ +#define _VAL2FLD(field, value) ((value << field ## _Pos) & field ## _Msk) + +/** + \brief Mask and shift a register value to extract a bit filed value. + \param[in] field Name of the register bit field. + \param[in] value Value of register. + \return Masked and shifted bit field value. +*/ +#define _FLD2VAL(field, value) ((value & field ## _Msk) >> field ## _Pos) + +/*@} end of group CMSIS_core_bitfield */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_core_base Core Definitions + \brief Definitions for base addresses, unions, and structures. + @{ + */ + +/* Memory mapping of Cortex-M4 Hardware */ +#define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */ +#define ITM_BASE (0xE0000000UL) /*!< ITM Base Address */ +#define DWT_BASE (0xE0001000UL) /*!< DWT Base Address */ +#define TPI_BASE (0xE0040000UL) /*!< TPI Base Address */ +#define CoreDebug_BASE (0xE000EDF0UL) /*!< Core Debug Base Address */ +#define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */ +#define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */ +#define SCB_BASE (SCS_BASE + 0x0D00UL) /*!< System Control Block Base Address */ + +#define SCnSCB ((SCnSCB_Type *) SCS_BASE ) /*!< System control Register not in SCB */ +#define SCB ((SCB_Type *) SCB_BASE ) /*!< SCB configuration struct */ +#define SysTick ((SysTick_Type *) SysTick_BASE ) /*!< SysTick configuration struct */ +#define NVIC ((NVIC_Type *) NVIC_BASE ) /*!< NVIC configuration struct */ +#define ITM ((ITM_Type *) ITM_BASE ) /*!< ITM configuration struct */ +#define DWT ((DWT_Type *) DWT_BASE ) /*!< DWT configuration struct */ +#define TPI ((TPI_Type *) TPI_BASE ) /*!< TPI configuration struct */ +#define CoreDebug ((CoreDebug_Type *) CoreDebug_BASE) /*!< Core Debug configuration struct */ + +#if (__MPU_PRESENT == 1U) +#define MPU_BASE (SCS_BASE + 0x0D90UL) /*!< Memory Protection Unit */ +#define MPU ((MPU_Type *) MPU_BASE ) /*!< Memory Protection Unit */ +#endif + +#if (__FPU_PRESENT == 1U) +#define FPU_BASE (SCS_BASE + 0x0F30UL) /*!< Floating Point Unit */ +#define FPU ((FPU_Type *) FPU_BASE ) /*!< Floating Point Unit */ +#endif + +/*@} */ + + + +/******************************************************************************* + * Hardware Abstraction Layer + Core Function Interface contains: + - Core NVIC Functions + - Core SysTick Functions + - Core Debug Functions + - Core Register Access Functions + ******************************************************************************/ +/** + \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference +*/ + + + +/* ########################## NVIC functions #################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_NVICFunctions NVIC Functions + \brief Functions that manage interrupts and exceptions via the NVIC. + @{ + */ + +/** + \brief Set Priority Grouping + \details Sets the priority grouping field using the required unlock sequence. + The parameter PriorityGroup is assigned to the field SCB->AIRCR [10:8] PRIGROUP field. + Only values from 0..7 are used. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set. + \param [in] PriorityGroup Priority grouping field. + */ +__STATIC_INLINE void NVIC_SetPriorityGrouping(uint32_t PriorityGroup) +{ + uint32_t reg_value; + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + + reg_value = SCB->AIRCR; /* read old register configuration */ + reg_value &= ~((uint32_t)(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk)); /* clear bits to change */ + reg_value = (reg_value | + ((uint32_t)0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | + (PriorityGroupTmp << 8U)); /* Insert write key and priorty group */ + SCB->AIRCR = reg_value; +} + + +/** + \brief Get Priority Grouping + \details Reads the priority grouping field from the NVIC Interrupt Controller. + \return Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field). + */ +__STATIC_INLINE uint32_t NVIC_GetPriorityGrouping(void) +{ + return ((uint32_t)((SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos)); +} + + +/** + \brief Enable External Interrupt + \details Enables a device-specific interrupt in the NVIC interrupt controller. + \param [in] IRQn External interrupt number. Value cannot be negative. + */ +__STATIC_INLINE void NVIC_EnableIRQ(IRQn_Type IRQn) +{ + NVIC->ISER[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL)); +} + + +/** + \brief Disable External Interrupt + \details Disables a device-specific interrupt in the NVIC interrupt controller. + \param [in] IRQn External interrupt number. Value cannot be negative. + */ +__STATIC_INLINE void NVIC_DisableIRQ(IRQn_Type IRQn) +{ + NVIC->ICER[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL)); +} + + +/** + \brief Get Pending Interrupt + \details Reads the pending register in the NVIC and returns the pending bit for the specified interrupt. + \param [in] IRQn Interrupt number. + \return 0 Interrupt status is not pending. + \return 1 Interrupt status is pending. + */ +__STATIC_INLINE uint32_t NVIC_GetPendingIRQ(IRQn_Type IRQn) +{ + return ((uint32_t)(((NVIC->ISPR[(((uint32_t)(int32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); +} + + +/** + \brief Set Pending Interrupt + \details Sets the pending bit of an external interrupt. + \param [in] IRQn Interrupt number. Value cannot be negative. + */ +__STATIC_INLINE void NVIC_SetPendingIRQ(IRQn_Type IRQn) +{ + NVIC->ISPR[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL)); +} + + +/** + \brief Clear Pending Interrupt + \details Clears the pending bit of an external interrupt. + \param [in] IRQn External interrupt number. Value cannot be negative. + */ +__STATIC_INLINE void NVIC_ClearPendingIRQ(IRQn_Type IRQn) +{ + NVIC->ICPR[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL)); +} + + +/** + \brief Get Active Interrupt + \details Reads the active register in NVIC and returns the active bit. + \param [in] IRQn Interrupt number. + \return 0 Interrupt status is not active. + \return 1 Interrupt status is active. + */ +__STATIC_INLINE uint32_t NVIC_GetActive(IRQn_Type IRQn) +{ + return ((uint32_t)(((NVIC->IABR[(((uint32_t)(int32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); +} + + +/** + \brief Set Interrupt Priority + \details Sets the priority of an interrupt. + \note The priority cannot be set for every core interrupt. + \param [in] IRQn Interrupt number. + \param [in] priority Priority to set. + */ +__STATIC_INLINE void NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority) +{ + if ((int32_t)(IRQn) < 0) + { + SCB->SHP[(((uint32_t)(int32_t)IRQn) & 0xFUL) - 4UL] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); + } + else + { + NVIC->IP[((uint32_t)(int32_t)IRQn)] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); + } +} + + +/** + \brief Get Interrupt Priority + \details Reads the priority of an interrupt. + The interrupt number can be positive to specify an external (device specific) interrupt, + or negative to specify an internal (core) interrupt. + \param [in] IRQn Interrupt number. + \return Interrupt Priority. + Value is aligned automatically to the implemented priority bits of the microcontroller. + */ +__STATIC_INLINE uint32_t NVIC_GetPriority(IRQn_Type IRQn) +{ + + if ((int32_t)(IRQn) < 0) + { + return (((uint32_t)SCB->SHP[(((uint32_t)(int32_t)IRQn) & 0xFUL) - 4UL] >> (8U - __NVIC_PRIO_BITS))); + } + else + { + return (((uint32_t)NVIC->IP[((uint32_t)(int32_t)IRQn)] >> (8U - __NVIC_PRIO_BITS))); + } +} + + +/** + \brief Encode Priority + \details Encodes the priority for an interrupt with the given priority group, + preemptive priority value, and subpriority value. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set. + \param [in] PriorityGroup Used priority group. + \param [in] PreemptPriority Preemptive priority value (starting from 0). + \param [in] SubPriority Subpriority value (starting from 0). + \return Encoded priority. Value can be used in the function \ref NVIC_SetPriority(). + */ +__STATIC_INLINE uint32_t NVIC_EncodePriority(uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority) +{ + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + uint32_t PreemptPriorityBits; + uint32_t SubPriorityBits; + + PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp); + SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS)); + + return ( + ((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) | + ((SubPriority & (uint32_t)((1UL << (SubPriorityBits)) - 1UL))) + ); +} + + +/** + \brief Decode Priority + \details Decodes an interrupt priority value with a given priority group to + preemptive priority value and subpriority value. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS) the smallest possible priority group is set. + \param [in] Priority Priority value, which can be retrieved with the function \ref NVIC_GetPriority(). + \param [in] PriorityGroup Used priority group. + \param [out] pPreemptPriority Preemptive priority value (starting from 0). + \param [out] pSubPriority Subpriority value (starting from 0). + */ +__STATIC_INLINE void NVIC_DecodePriority(uint32_t Priority, uint32_t PriorityGroup, uint32_t *const pPreemptPriority, uint32_t *const pSubPriority) +{ + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + uint32_t PreemptPriorityBits; + uint32_t SubPriorityBits; + + PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp); + SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS)); + + *pPreemptPriority = (Priority >> SubPriorityBits) & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL); + *pSubPriority = (Priority) & (uint32_t)((1UL << (SubPriorityBits)) - 1UL); +} + + +/** + \brief System Reset + \details Initiates a system reset request to reset the MCU. + */ +__STATIC_INLINE void NVIC_SystemReset(void) +{ + __DSB(); /* Ensure all outstanding memory accesses included + buffered write are completed before reset */ + SCB->AIRCR = (uint32_t)((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | + (SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) | + SCB_AIRCR_SYSRESETREQ_Msk); /* Keep priority group unchanged */ + __DSB(); /* Ensure completion of memory access */ + + for (;;) /* wait until reset */ + { + __NOP(); + } +} + +/*@} end of CMSIS_Core_NVICFunctions */ + + + +/* ################################## SysTick function ############################################ */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_SysTickFunctions SysTick Functions + \brief Functions that configure the System. + @{ + */ + +#if (__Vendor_SysTickConfig == 0U) + +/** + \brief System Tick Configuration + \details Initializes the System Timer and its interrupt, and starts the System Tick Timer. + Counter is in free running mode to generate periodic interrupts. + \param [in] ticks Number of ticks between two interrupts. + \return 0 Function succeeded. + \return 1 Function failed. + \note When the variable __Vendor_SysTickConfig is set to 1, then the + function SysTick_Config is not included. In this case, the file device.h + must contain a vendor-specific implementation of this function. + */ +__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks) +{ + if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk) + { + return (1UL); /* Reload value impossible */ + } + + SysTick->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */ + NVIC_SetPriority(SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */ + SysTick->VAL = 0UL; /* Load the SysTick Counter Value */ + SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk | + SysTick_CTRL_TICKINT_Msk | + SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */ + return (0UL); /* Function successful */ +} + +#endif + +/*@} end of CMSIS_Core_SysTickFunctions */ + + + +/* ##################################### Debug In/Output function ########################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_core_DebugFunctions ITM Functions + \brief Functions that access the ITM debug interface. + @{ + */ + +extern volatile int32_t ITM_RxBuffer; /*!< External variable to receive characters. */ +#define ITM_RXBUFFER_EMPTY 0x5AA55AA5U /*!< Value identifying \ref ITM_RxBuffer is ready for next character. */ + + +/** + \brief ITM Send Character + \details Transmits a character via the ITM channel 0, and + \li Just returns when no debugger is connected that has booked the output. + \li Is blocking when a debugger is connected, but the previous character sent has not been transmitted. + \param [in] ch Character to transmit. + \returns Character to transmit. + */ +__STATIC_INLINE uint32_t ITM_SendChar(uint32_t ch) +{ + if (((ITM->TCR & ITM_TCR_ITMENA_Msk) != 0UL) && /* ITM enabled */ + ((ITM->TER & 1UL) != 0UL)) /* ITM Port #0 enabled */ + { + while (ITM->PORT[0U].u32 == 0UL) + { + __NOP(); + } + ITM->PORT[0U].u8 = (uint8_t)ch; + } + return (ch); +} + + +/** + \brief ITM Receive Character + \details Inputs a character via the external variable \ref ITM_RxBuffer. + \return Received character. + \return -1 No character pending. + */ +__STATIC_INLINE int32_t ITM_ReceiveChar(void) +{ + int32_t ch = -1; /* no character available */ + + if (ITM_RxBuffer != ITM_RXBUFFER_EMPTY) + { + ch = ITM_RxBuffer; + ITM_RxBuffer = ITM_RXBUFFER_EMPTY; /* ready for next character */ + } + + return (ch); +} + + +/** + \brief ITM Check Character + \details Checks whether a character is pending for reading in the variable \ref ITM_RxBuffer. + \return 0 No character available. + \return 1 Character available. + */ +__STATIC_INLINE int32_t ITM_CheckChar(void) +{ + + if (ITM_RxBuffer == ITM_RXBUFFER_EMPTY) + { + return (0); /* no character available */ + } + else + { + return (1); /* character available */ + } +} + +/*@} end of CMSIS_core_DebugFunctions */ + + + + +#ifdef __cplusplus +} +#endif + +#endif /* __CORE_CM4_H_DEPENDANT */ + +#endif /* __CMSIS_GENERIC */ diff --git a/bsp/nuvoton/libraries/ma35/CMSIS/Include/core_cm7.h b/bsp/nuvoton/libraries/ma35/CMSIS/Include/core_cm7.h new file mode 100644 index 0000000000..f2877865b1 --- /dev/null +++ b/bsp/nuvoton/libraries/ma35/CMSIS/Include/core_cm7.h @@ -0,0 +1,2535 @@ +/**************************************************************************//** + * @file core_cm7.h + * @brief CMSIS Cortex-M7 Core Peripheral Access Layer Header File + * @version V4.30 + * @date 20. October 2015 + ******************************************************************************/ +/* Copyright (c) 2009 - 2015 ARM LIMITED + + All rights reserved. + Redistribution and use in source and binary forms, with or without + modification, are permitted provided that the following conditions are met: + - Redistributions of source code must retain the above copyright + notice, this list of conditions and the following disclaimer. + - Redistributions in binary form must reproduce the above copyright + notice, this list of conditions and the following disclaimer in the + documentation and/or other materials provided with the distribution. + - Neither the name of ARM nor the names of its contributors may be used + to endorse or promote products derived from this software without + specific prior written permission. + * + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE + LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + POSSIBILITY OF SUCH DAMAGE. + ---------------------------------------------------------------------------*/ + + +#if defined ( __ICCARM__ ) + #pragma system_include /* treat file as system include file for MISRA check */ +#elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) + #pragma clang system_header /* treat file as system include file */ +#endif + +#ifndef __CORE_CM7_H_GENERIC +#define __CORE_CM7_H_GENERIC + +#include + +#ifdef __cplusplus +extern "C" { +#endif + +/** + \page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions + CMSIS violates the following MISRA-C:2004 rules: + + \li Required Rule 8.5, object/function definition in header file.
+ Function definitions in header files are used to allow 'inlining'. + + \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.
+ Unions are used for effective representation of core registers. + + \li Advisory Rule 19.7, Function-like macro defined.
+ Function-like macros are used to allow more efficient code. + */ + + +/******************************************************************************* + * CMSIS definitions + ******************************************************************************/ +/** + \ingroup Cortex_M7 + @{ + */ + +/* CMSIS CM7 definitions */ +#define __CM7_CMSIS_VERSION_MAIN (0x04U) /*!< [31:16] CMSIS HAL main version */ +#define __CM7_CMSIS_VERSION_SUB (0x1EU) /*!< [15:0] CMSIS HAL sub version */ +#define __CM7_CMSIS_VERSION ((__CM7_CMSIS_VERSION_MAIN << 16U) | \ + __CM7_CMSIS_VERSION_SUB ) /*!< CMSIS HAL version number */ + +#define __CORTEX_M (0x07U) /*!< Cortex-M Core */ + + +#if defined ( __CC_ARM ) +#define __ASM __asm /*!< asm keyword for ARM Compiler */ +#define __INLINE __inline /*!< inline keyword for ARM Compiler */ +#define __STATIC_INLINE static __inline + +#elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) +#define __ASM __asm /*!< asm keyword for ARM Compiler */ +#define __INLINE __inline /*!< inline keyword for ARM Compiler */ +#define __STATIC_INLINE static __inline + +#elif defined ( __GNUC__ ) +#define __ASM __asm /*!< asm keyword for GNU Compiler */ +#define __INLINE inline /*!< inline keyword for GNU Compiler */ +#define __STATIC_INLINE static inline + +#elif defined ( __ICCARM__ ) +#define __ASM __asm /*!< asm keyword for IAR Compiler */ +#define __INLINE inline /*!< inline keyword for IAR Compiler. Only available in High optimization mode! */ +#define __STATIC_INLINE static inline + +#elif defined ( __TMS470__ ) +#define __ASM __asm /*!< asm keyword for TI CCS Compiler */ +#define __STATIC_INLINE static inline + +#elif defined ( __TASKING__ ) +#define __ASM __asm /*!< asm keyword for TASKING Compiler */ +#define __INLINE inline /*!< inline keyword for TASKING Compiler */ +#define __STATIC_INLINE static inline + +#elif defined ( __CSMC__ ) +#define __packed +#define __ASM _asm /*!< asm keyword for COSMIC Compiler */ +#define __INLINE inline /*!< inline keyword for COSMIC Compiler. Use -pc99 on compile line */ +#define __STATIC_INLINE static inline + +#else +#error Unknown compiler +#endif + +/** __FPU_USED indicates whether an FPU is used or not. + For this, __FPU_PRESENT has to be checked prior to making use of FPU specific registers and functions. +*/ +#if defined ( __CC_ARM ) +#if defined __TARGET_FPU_VFP +#if (__FPU_PRESENT == 1U) +#define __FPU_USED 1U +#else +#error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" +#define __FPU_USED 0U +#endif +#else +#define __FPU_USED 0U +#endif + +#elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) +#if defined __ARM_PCS_VFP +#if (__FPU_PRESENT == 1) +#define __FPU_USED 1U +#else +#warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" +#define __FPU_USED 0U +#endif +#else +#define __FPU_USED 0U +#endif + +#elif defined ( __GNUC__ ) +#if defined (__VFP_FP__) && !defined(__SOFTFP__) +#if (__FPU_PRESENT == 1U) +#define __FPU_USED 1U +#else +#error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" +#define __FPU_USED 0U +#endif +#else +#define __FPU_USED 0U +#endif + +#elif defined ( __ICCARM__ ) +#if defined __ARMVFP__ +#if (__FPU_PRESENT == 1U) +#define __FPU_USED 1U +#else +#error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" +#define __FPU_USED 0U +#endif +#else +#define __FPU_USED 0U +#endif + +#elif defined ( __TMS470__ ) +#if defined __TI_VFP_SUPPORT__ +#if (__FPU_PRESENT == 1U) +#define __FPU_USED 1U +#else +#error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" +#define __FPU_USED 0U +#endif +#else +#define __FPU_USED 0U +#endif + +#elif defined ( __TASKING__ ) +#if defined __FPU_VFP__ +#if (__FPU_PRESENT == 1U) +#define __FPU_USED 1U +#else +#error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" +#define __FPU_USED 0U +#endif +#else +#define __FPU_USED 0U +#endif + +#elif defined ( __CSMC__ ) +#if ( __CSMC__ & 0x400U) +#if (__FPU_PRESENT == 1U) +#define __FPU_USED 1U +#else +#error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" +#define __FPU_USED 0U +#endif +#else +#define __FPU_USED 0U +#endif + +#endif + +#include "core_cmInstr.h" /* Core Instruction Access */ +#include "core_cmFunc.h" /* Core Function Access */ +#include "core_cmSimd.h" /* Compiler specific SIMD Intrinsics */ + +#ifdef __cplusplus +} +#endif + +#endif /* __CORE_CM7_H_GENERIC */ + +#ifndef __CMSIS_GENERIC + +#ifndef __CORE_CM7_H_DEPENDANT +#define __CORE_CM7_H_DEPENDANT + +#ifdef __cplusplus +extern "C" { +#endif + +/* check device defines and use defaults */ +#if defined __CHECK_DEVICE_DEFINES +#ifndef __CM7_REV +#define __CM7_REV 0x0000U +#warning "__CM7_REV not defined in device header file; using default!" +#endif + +#ifndef __FPU_PRESENT +#define __FPU_PRESENT 0U +#warning "__FPU_PRESENT not defined in device header file; using default!" +#endif + +#ifndef __MPU_PRESENT +#define __MPU_PRESENT 0U +#warning "__MPU_PRESENT not defined in device header file; using default!" +#endif + +#ifndef __ICACHE_PRESENT +#define __ICACHE_PRESENT 0U +#warning "__ICACHE_PRESENT not defined in device header file; using default!" +#endif + +#ifndef __DCACHE_PRESENT +#define __DCACHE_PRESENT 0U +#warning "__DCACHE_PRESENT not defined in device header file; using default!" +#endif + +#ifndef __DTCM_PRESENT +#define __DTCM_PRESENT 0U +#warning "__DTCM_PRESENT not defined in device header file; using default!" +#endif + +#ifndef __NVIC_PRIO_BITS +#define __NVIC_PRIO_BITS 3U +#warning "__NVIC_PRIO_BITS not defined in device header file; using default!" +#endif + +#ifndef __Vendor_SysTickConfig +#define __Vendor_SysTickConfig 0U +#warning "__Vendor_SysTickConfig not defined in device header file; using default!" +#endif +#endif + +/* IO definitions (access restrictions to peripheral registers) */ +/** + \defgroup CMSIS_glob_defs CMSIS Global Defines + + IO Type Qualifiers are used + \li to specify the access to peripheral variables. + \li for automatic generation of peripheral register debug information. +*/ +#ifdef __cplusplus +#define __I volatile /*!< Defines 'read only' permissions */ +#else +#define __I volatile const /*!< Defines 'read only' permissions */ +#endif +#define __O volatile /*!< Defines 'write only' permissions */ +#define __IO volatile /*!< Defines 'read / write' permissions */ + +/* following defines should be used for structure members */ +#define __IM volatile const /*! Defines 'read only' structure member permissions */ +#define __OM volatile /*! Defines 'write only' structure member permissions */ +#define __IOM volatile /*! Defines 'read / write' structure member permissions */ + +/*@} end of group Cortex_M7 */ + + + +/******************************************************************************* + * Register Abstraction + Core Register contain: + - Core Register + - Core NVIC Register + - Core SCB Register + - Core SysTick Register + - Core Debug Register + - Core MPU Register + - Core FPU Register + ******************************************************************************/ +/** + \defgroup CMSIS_core_register Defines and Type Definitions + \brief Type definitions and defines for Cortex-M processor based devices. +*/ + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_CORE Status and Control Registers + \brief Core Register type definitions. + @{ + */ + +/** + \brief Union type to access the Application Program Status Register (APSR). + */ +typedef union +{ + struct + { + uint32_t _reserved0: 16; /*!< bit: 0..15 Reserved */ + uint32_t GE: 4; /*!< bit: 16..19 Greater than or Equal flags */ + uint32_t _reserved1: 7; /*!< bit: 20..26 Reserved */ + uint32_t Q: 1; /*!< bit: 27 Saturation condition flag */ + uint32_t V: 1; /*!< bit: 28 Overflow condition code flag */ + uint32_t C: 1; /*!< bit: 29 Carry condition code flag */ + uint32_t Z: 1; /*!< bit: 30 Zero condition code flag */ + uint32_t N: 1; /*!< bit: 31 Negative condition code flag */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} APSR_Type; + +/* APSR Register Definitions */ +#define APSR_N_Pos 31U /*!< APSR: N Position */ +#define APSR_N_Msk (1UL << APSR_N_Pos) /*!< APSR: N Mask */ + +#define APSR_Z_Pos 30U /*!< APSR: Z Position */ +#define APSR_Z_Msk (1UL << APSR_Z_Pos) /*!< APSR: Z Mask */ + +#define APSR_C_Pos 29U /*!< APSR: C Position */ +#define APSR_C_Msk (1UL << APSR_C_Pos) /*!< APSR: C Mask */ + +#define APSR_V_Pos 28U /*!< APSR: V Position */ +#define APSR_V_Msk (1UL << APSR_V_Pos) /*!< APSR: V Mask */ + +#define APSR_Q_Pos 27U /*!< APSR: Q Position */ +#define APSR_Q_Msk (1UL << APSR_Q_Pos) /*!< APSR: Q Mask */ + +#define APSR_GE_Pos 16U /*!< APSR: GE Position */ +#define APSR_GE_Msk (0xFUL << APSR_GE_Pos) /*!< APSR: GE Mask */ + + +/** + \brief Union type to access the Interrupt Program Status Register (IPSR). + */ +typedef union +{ + struct + { + uint32_t ISR: 9; /*!< bit: 0.. 8 Exception number */ + uint32_t _reserved0: 23; /*!< bit: 9..31 Reserved */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} IPSR_Type; + +/* IPSR Register Definitions */ +#define IPSR_ISR_Pos 0U /*!< IPSR: ISR Position */ +#define IPSR_ISR_Msk (0x1FFUL /*<< IPSR_ISR_Pos*/) /*!< IPSR: ISR Mask */ + + +/** + \brief Union type to access the Special-Purpose Program Status Registers (xPSR). + */ +typedef union +{ + struct + { + uint32_t ISR: 9; /*!< bit: 0.. 8 Exception number */ + uint32_t _reserved0: 7; /*!< bit: 9..15 Reserved */ + uint32_t GE: 4; /*!< bit: 16..19 Greater than or Equal flags */ + uint32_t _reserved1: 4; /*!< bit: 20..23 Reserved */ + uint32_t T: 1; /*!< bit: 24 Thumb bit (read 0) */ + uint32_t IT: 2; /*!< bit: 25..26 saved IT state (read 0) */ + uint32_t Q: 1; /*!< bit: 27 Saturation condition flag */ + uint32_t V: 1; /*!< bit: 28 Overflow condition code flag */ + uint32_t C: 1; /*!< bit: 29 Carry condition code flag */ + uint32_t Z: 1; /*!< bit: 30 Zero condition code flag */ + uint32_t N: 1; /*!< bit: 31 Negative condition code flag */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} xPSR_Type; + +/* xPSR Register Definitions */ +#define xPSR_N_Pos 31U /*!< xPSR: N Position */ +#define xPSR_N_Msk (1UL << xPSR_N_Pos) /*!< xPSR: N Mask */ + +#define xPSR_Z_Pos 30U /*!< xPSR: Z Position */ +#define xPSR_Z_Msk (1UL << xPSR_Z_Pos) /*!< xPSR: Z Mask */ + +#define xPSR_C_Pos 29U /*!< xPSR: C Position */ +#define xPSR_C_Msk (1UL << xPSR_C_Pos) /*!< xPSR: C Mask */ + +#define xPSR_V_Pos 28U /*!< xPSR: V Position */ +#define xPSR_V_Msk (1UL << xPSR_V_Pos) /*!< xPSR: V Mask */ + +#define xPSR_Q_Pos 27U /*!< xPSR: Q Position */ +#define xPSR_Q_Msk (1UL << xPSR_Q_Pos) /*!< xPSR: Q Mask */ + +#define xPSR_IT_Pos 25U /*!< xPSR: IT Position */ +#define xPSR_IT_Msk (3UL << xPSR_IT_Pos) /*!< xPSR: IT Mask */ + +#define xPSR_T_Pos 24U /*!< xPSR: T Position */ +#define xPSR_T_Msk (1UL << xPSR_T_Pos) /*!< xPSR: T Mask */ + +#define xPSR_GE_Pos 16U /*!< xPSR: GE Position */ +#define xPSR_GE_Msk (0xFUL << xPSR_GE_Pos) /*!< xPSR: GE Mask */ + +#define xPSR_ISR_Pos 0U /*!< xPSR: ISR Position */ +#define xPSR_ISR_Msk (0x1FFUL /*<< xPSR_ISR_Pos*/) /*!< xPSR: ISR Mask */ + + +/** + \brief Union type to access the Control Registers (CONTROL). + */ +typedef union +{ + struct + { + uint32_t nPRIV: 1; /*!< bit: 0 Execution privilege in Thread mode */ + uint32_t SPSEL: 1; /*!< bit: 1 Stack to be used */ + uint32_t FPCA: 1; /*!< bit: 2 FP extension active flag */ + uint32_t _reserved0: 29; /*!< bit: 3..31 Reserved */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} CONTROL_Type; + +/* CONTROL Register Definitions */ +#define CONTROL_FPCA_Pos 2U /*!< CONTROL: FPCA Position */ +#define CONTROL_FPCA_Msk (1UL << CONTROL_FPCA_Pos) /*!< CONTROL: FPCA Mask */ + +#define CONTROL_SPSEL_Pos 1U /*!< CONTROL: SPSEL Position */ +#define CONTROL_SPSEL_Msk (1UL << CONTROL_SPSEL_Pos) /*!< CONTROL: SPSEL Mask */ + +#define CONTROL_nPRIV_Pos 0U /*!< CONTROL: nPRIV Position */ +#define CONTROL_nPRIV_Msk (1UL /*<< CONTROL_nPRIV_Pos*/) /*!< CONTROL: nPRIV Mask */ + +/*@} end of group CMSIS_CORE */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC) + \brief Type definitions for the NVIC Registers + @{ + */ + +/** + \brief Structure type to access the Nested Vectored Interrupt Controller (NVIC). + */ +typedef struct +{ + __IOM uint32_t ISER[8U]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */ + uint32_t RESERVED0[24U]; + __IOM uint32_t ICER[8U]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */ + uint32_t RSERVED1[24U]; + __IOM uint32_t ISPR[8U]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */ + uint32_t RESERVED2[24U]; + __IOM uint32_t ICPR[8U]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register */ + uint32_t RESERVED3[24U]; + __IOM uint32_t IABR[8U]; /*!< Offset: 0x200 (R/W) Interrupt Active bit Register */ + uint32_t RESERVED4[56U]; + __IOM uint8_t IP[240U]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register (8Bit wide) */ + uint32_t RESERVED5[644U]; + __OM uint32_t STIR; /*!< Offset: 0xE00 ( /W) Software Trigger Interrupt Register */ +} NVIC_Type; + +/* Software Triggered Interrupt Register Definitions */ +#define NVIC_STIR_INTID_Pos 0U /*!< STIR: INTLINESNUM Position */ +#define NVIC_STIR_INTID_Msk (0x1FFUL /*<< NVIC_STIR_INTID_Pos*/) /*!< STIR: INTLINESNUM Mask */ + +/*@} end of group CMSIS_NVIC */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SCB System Control Block (SCB) + \brief Type definitions for the System Control Block Registers + @{ + */ + +/** + \brief Structure type to access the System Control Block (SCB). + */ +typedef struct +{ + __IM uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */ + __IOM uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Register */ + __IOM uint32_t VTOR; /*!< Offset: 0x008 (R/W) Vector Table Offset Register */ + __IOM uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register */ + __IOM uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */ + __IOM uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */ + __IOM uint8_t SHPR[12U]; /*!< Offset: 0x018 (R/W) System Handlers Priority Registers (4-7, 8-11, 12-15) */ + __IOM uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State Register */ + __IOM uint32_t CFSR; /*!< Offset: 0x028 (R/W) Configurable Fault Status Register */ + __IOM uint32_t HFSR; /*!< Offset: 0x02C (R/W) HardFault Status Register */ + __IOM uint32_t DFSR; /*!< Offset: 0x030 (R/W) Debug Fault Status Register */ + __IOM uint32_t MMFAR; /*!< Offset: 0x034 (R/W) MemManage Fault Address Register */ + __IOM uint32_t BFAR; /*!< Offset: 0x038 (R/W) BusFault Address Register */ + __IOM uint32_t AFSR; /*!< Offset: 0x03C (R/W) Auxiliary Fault Status Register */ + __IM uint32_t ID_PFR[2U]; /*!< Offset: 0x040 (R/ ) Processor Feature Register */ + __IM uint32_t ID_DFR; /*!< Offset: 0x048 (R/ ) Debug Feature Register */ + __IM uint32_t ID_AFR; /*!< Offset: 0x04C (R/ ) Auxiliary Feature Register */ + __IM uint32_t ID_MFR[4U]; /*!< Offset: 0x050 (R/ ) Memory Model Feature Register */ + __IM uint32_t ID_ISAR[5U]; /*!< Offset: 0x060 (R/ ) Instruction Set Attributes Register */ + uint32_t RESERVED0[1U]; + __IM uint32_t CLIDR; /*!< Offset: 0x078 (R/ ) Cache Level ID register */ + __IM uint32_t CTR; /*!< Offset: 0x07C (R/ ) Cache Type register */ + __IM uint32_t CCSIDR; /*!< Offset: 0x080 (R/ ) Cache Size ID Register */ + __IOM uint32_t CSSELR; /*!< Offset: 0x084 (R/W) Cache Size Selection Register */ + __IOM uint32_t CPACR; /*!< Offset: 0x088 (R/W) Coprocessor Access Control Register */ + uint32_t RESERVED3[93U]; + __OM uint32_t STIR; /*!< Offset: 0x200 ( /W) Software Triggered Interrupt Register */ + uint32_t RESERVED4[15U]; + __IM uint32_t MVFR0; /*!< Offset: 0x240 (R/ ) Media and VFP Feature Register 0 */ + __IM uint32_t MVFR1; /*!< Offset: 0x244 (R/ ) Media and VFP Feature Register 1 */ + __IM uint32_t MVFR2; /*!< Offset: 0x248 (R/ ) Media and VFP Feature Register 1 */ + uint32_t RESERVED5[1U]; + __OM uint32_t ICIALLU; /*!< Offset: 0x250 ( /W) I-Cache Invalidate All to PoU */ + uint32_t RESERVED6[1U]; + __OM uint32_t ICIMVAU; /*!< Offset: 0x258 ( /W) I-Cache Invalidate by MVA to PoU */ + __OM uint32_t DCIMVAC; /*!< Offset: 0x25C ( /W) D-Cache Invalidate by MVA to PoC */ + __OM uint32_t DCISW; /*!< Offset: 0x260 ( /W) D-Cache Invalidate by Set-way */ + __OM uint32_t DCCMVAU; /*!< Offset: 0x264 ( /W) D-Cache Clean by MVA to PoU */ + __OM uint32_t DCCMVAC; /*!< Offset: 0x268 ( /W) D-Cache Clean by MVA to PoC */ + __OM uint32_t DCCSW; /*!< Offset: 0x26C ( /W) D-Cache Clean by Set-way */ + __OM uint32_t DCCIMVAC; /*!< Offset: 0x270 ( /W) D-Cache Clean and Invalidate by MVA to PoC */ + __OM uint32_t DCCISW; /*!< Offset: 0x274 ( /W) D-Cache Clean and Invalidate by Set-way */ + uint32_t RESERVED7[6U]; + __IOM uint32_t ITCMCR; /*!< Offset: 0x290 (R/W) Instruction Tightly-Coupled Memory Control Register */ + __IOM uint32_t DTCMCR; /*!< Offset: 0x294 (R/W) Data Tightly-Coupled Memory Control Registers */ + __IOM uint32_t AHBPCR; /*!< Offset: 0x298 (R/W) AHBP Control Register */ + __IOM uint32_t CACR; /*!< Offset: 0x29C (R/W) L1 Cache Control Register */ + __IOM uint32_t AHBSCR; /*!< Offset: 0x2A0 (R/W) AHB Slave Control Register */ + uint32_t RESERVED8[1U]; + __IOM uint32_t ABFSR; /*!< Offset: 0x2A8 (R/W) Auxiliary Bus Fault Status Register */ +} SCB_Type; + +/* SCB CPUID Register Definitions */ +#define SCB_CPUID_IMPLEMENTER_Pos 24U /*!< SCB CPUID: IMPLEMENTER Position */ +#define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */ + +#define SCB_CPUID_VARIANT_Pos 20U /*!< SCB CPUID: VARIANT Position */ +#define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */ + +#define SCB_CPUID_ARCHITECTURE_Pos 16U /*!< SCB CPUID: ARCHITECTURE Position */ +#define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB CPUID: ARCHITECTURE Mask */ + +#define SCB_CPUID_PARTNO_Pos 4U /*!< SCB CPUID: PARTNO Position */ +#define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */ + +#define SCB_CPUID_REVISION_Pos 0U /*!< SCB CPUID: REVISION Position */ +#define SCB_CPUID_REVISION_Msk (0xFUL /*<< SCB_CPUID_REVISION_Pos*/) /*!< SCB CPUID: REVISION Mask */ + +/* SCB Interrupt Control State Register Definitions */ +#define SCB_ICSR_NMIPENDSET_Pos 31U /*!< SCB ICSR: NMIPENDSET Position */ +#define SCB_ICSR_NMIPENDSET_Msk (1UL << SCB_ICSR_NMIPENDSET_Pos) /*!< SCB ICSR: NMIPENDSET Mask */ + +#define SCB_ICSR_PENDSVSET_Pos 28U /*!< SCB ICSR: PENDSVSET Position */ +#define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */ + +#define SCB_ICSR_PENDSVCLR_Pos 27U /*!< SCB ICSR: PENDSVCLR Position */ +#define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */ + +#define SCB_ICSR_PENDSTSET_Pos 26U /*!< SCB ICSR: PENDSTSET Position */ +#define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */ + +#define SCB_ICSR_PENDSTCLR_Pos 25U /*!< SCB ICSR: PENDSTCLR Position */ +#define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */ + +#define SCB_ICSR_ISRPREEMPT_Pos 23U /*!< SCB ICSR: ISRPREEMPT Position */ +#define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */ + +#define SCB_ICSR_ISRPENDING_Pos 22U /*!< SCB ICSR: ISRPENDING Position */ +#define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */ + +#define SCB_ICSR_VECTPENDING_Pos 12U /*!< SCB ICSR: VECTPENDING Position */ +#define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */ + +#define SCB_ICSR_RETTOBASE_Pos 11U /*!< SCB ICSR: RETTOBASE Position */ +#define SCB_ICSR_RETTOBASE_Msk (1UL << SCB_ICSR_RETTOBASE_Pos) /*!< SCB ICSR: RETTOBASE Mask */ + +#define SCB_ICSR_VECTACTIVE_Pos 0U /*!< SCB ICSR: VECTACTIVE Position */ +#define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/) /*!< SCB ICSR: VECTACTIVE Mask */ + +/* SCB Vector Table Offset Register Definitions */ +#define SCB_VTOR_TBLOFF_Pos 7U /*!< SCB VTOR: TBLOFF Position */ +#define SCB_VTOR_TBLOFF_Msk (0x1FFFFFFUL << SCB_VTOR_TBLOFF_Pos) /*!< SCB VTOR: TBLOFF Mask */ + +/* SCB Application Interrupt and Reset Control Register Definitions */ +#define SCB_AIRCR_VECTKEY_Pos 16U /*!< SCB AIRCR: VECTKEY Position */ +#define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */ + +#define SCB_AIRCR_VECTKEYSTAT_Pos 16U /*!< SCB AIRCR: VECTKEYSTAT Position */ +#define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */ + +#define SCB_AIRCR_ENDIANESS_Pos 15U /*!< SCB AIRCR: ENDIANESS Position */ +#define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /*!< SCB AIRCR: ENDIANESS Mask */ + +#define SCB_AIRCR_PRIGROUP_Pos 8U /*!< SCB AIRCR: PRIGROUP Position */ +#define SCB_AIRCR_PRIGROUP_Msk (7UL << SCB_AIRCR_PRIGROUP_Pos) /*!< SCB AIRCR: PRIGROUP Mask */ + +#define SCB_AIRCR_SYSRESETREQ_Pos 2U /*!< SCB AIRCR: SYSRESETREQ Position */ +#define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */ + +#define SCB_AIRCR_VECTCLRACTIVE_Pos 1U /*!< SCB AIRCR: VECTCLRACTIVE Position */ +#define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */ + +#define SCB_AIRCR_VECTRESET_Pos 0U /*!< SCB AIRCR: VECTRESET Position */ +#define SCB_AIRCR_VECTRESET_Msk (1UL /*<< SCB_AIRCR_VECTRESET_Pos*/) /*!< SCB AIRCR: VECTRESET Mask */ + +/* SCB System Control Register Definitions */ +#define SCB_SCR_SEVONPEND_Pos 4U /*!< SCB SCR: SEVONPEND Position */ +#define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */ + +#define SCB_SCR_SLEEPDEEP_Pos 2U /*!< SCB SCR: SLEEPDEEP Position */ +#define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */ + +#define SCB_SCR_SLEEPONEXIT_Pos 1U /*!< SCB SCR: SLEEPONEXIT Position */ +#define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */ + +/* SCB Configuration Control Register Definitions */ +#define SCB_CCR_BP_Pos 18U /*!< SCB CCR: Branch prediction enable bit Position */ +#define SCB_CCR_BP_Msk (1UL << SCB_CCR_BP_Pos) /*!< SCB CCR: Branch prediction enable bit Mask */ + +#define SCB_CCR_IC_Pos 17U /*!< SCB CCR: Instruction cache enable bit Position */ +#define SCB_CCR_IC_Msk (1UL << SCB_CCR_IC_Pos) /*!< SCB CCR: Instruction cache enable bit Mask */ + +#define SCB_CCR_DC_Pos 16U /*!< SCB CCR: Cache enable bit Position */ +#define SCB_CCR_DC_Msk (1UL << SCB_CCR_DC_Pos) /*!< SCB CCR: Cache enable bit Mask */ + +#define SCB_CCR_STKALIGN_Pos 9U /*!< SCB CCR: STKALIGN Position */ +#define SCB_CCR_STKALIGN_Msk (1UL << SCB_CCR_STKALIGN_Pos) /*!< SCB CCR: STKALIGN Mask */ + +#define SCB_CCR_BFHFNMIGN_Pos 8U /*!< SCB CCR: BFHFNMIGN Position */ +#define SCB_CCR_BFHFNMIGN_Msk (1UL << SCB_CCR_BFHFNMIGN_Pos) /*!< SCB CCR: BFHFNMIGN Mask */ + +#define SCB_CCR_DIV_0_TRP_Pos 4U /*!< SCB CCR: DIV_0_TRP Position */ +#define SCB_CCR_DIV_0_TRP_Msk (1UL << SCB_CCR_DIV_0_TRP_Pos) /*!< SCB CCR: DIV_0_TRP Mask */ + +#define SCB_CCR_UNALIGN_TRP_Pos 3U /*!< SCB CCR: UNALIGN_TRP Position */ +#define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */ + +#define SCB_CCR_USERSETMPEND_Pos 1U /*!< SCB CCR: USERSETMPEND Position */ +#define SCB_CCR_USERSETMPEND_Msk (1UL << SCB_CCR_USERSETMPEND_Pos) /*!< SCB CCR: USERSETMPEND Mask */ + +#define SCB_CCR_NONBASETHRDENA_Pos 0U /*!< SCB CCR: NONBASETHRDENA Position */ +#define SCB_CCR_NONBASETHRDENA_Msk (1UL /*<< SCB_CCR_NONBASETHRDENA_Pos*/) /*!< SCB CCR: NONBASETHRDENA Mask */ + +/* SCB System Handler Control and State Register Definitions */ +#define SCB_SHCSR_USGFAULTENA_Pos 18U /*!< SCB SHCSR: USGFAULTENA Position */ +#define SCB_SHCSR_USGFAULTENA_Msk (1UL << SCB_SHCSR_USGFAULTENA_Pos) /*!< SCB SHCSR: USGFAULTENA Mask */ + +#define SCB_SHCSR_BUSFAULTENA_Pos 17U /*!< SCB SHCSR: BUSFAULTENA Position */ +#define SCB_SHCSR_BUSFAULTENA_Msk (1UL << SCB_SHCSR_BUSFAULTENA_Pos) /*!< SCB SHCSR: BUSFAULTENA Mask */ + +#define SCB_SHCSR_MEMFAULTENA_Pos 16U /*!< SCB SHCSR: MEMFAULTENA Position */ +#define SCB_SHCSR_MEMFAULTENA_Msk (1UL << SCB_SHCSR_MEMFAULTENA_Pos) /*!< SCB SHCSR: MEMFAULTENA Mask */ + +#define SCB_SHCSR_SVCALLPENDED_Pos 15U /*!< SCB SHCSR: SVCALLPENDED Position */ +#define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */ + +#define SCB_SHCSR_BUSFAULTPENDED_Pos 14U /*!< SCB SHCSR: BUSFAULTPENDED Position */ +#define SCB_SHCSR_BUSFAULTPENDED_Msk (1UL << SCB_SHCSR_BUSFAULTPENDED_Pos) /*!< SCB SHCSR: BUSFAULTPENDED Mask */ + +#define SCB_SHCSR_MEMFAULTPENDED_Pos 13U /*!< SCB SHCSR: MEMFAULTPENDED Position */ +#define SCB_SHCSR_MEMFAULTPENDED_Msk (1UL << SCB_SHCSR_MEMFAULTPENDED_Pos) /*!< SCB SHCSR: MEMFAULTPENDED Mask */ + +#define SCB_SHCSR_USGFAULTPENDED_Pos 12U /*!< SCB SHCSR: USGFAULTPENDED Position */ +#define SCB_SHCSR_USGFAULTPENDED_Msk (1UL << SCB_SHCSR_USGFAULTPENDED_Pos) /*!< SCB SHCSR: USGFAULTPENDED Mask */ + +#define SCB_SHCSR_SYSTICKACT_Pos 11U /*!< SCB SHCSR: SYSTICKACT Position */ +#define SCB_SHCSR_SYSTICKACT_Msk (1UL << SCB_SHCSR_SYSTICKACT_Pos) /*!< SCB SHCSR: SYSTICKACT Mask */ + +#define SCB_SHCSR_PENDSVACT_Pos 10U /*!< SCB SHCSR: PENDSVACT Position */ +#define SCB_SHCSR_PENDSVACT_Msk (1UL << SCB_SHCSR_PENDSVACT_Pos) /*!< SCB SHCSR: PENDSVACT Mask */ + +#define SCB_SHCSR_MONITORACT_Pos 8U /*!< SCB SHCSR: MONITORACT Position */ +#define SCB_SHCSR_MONITORACT_Msk (1UL << SCB_SHCSR_MONITORACT_Pos) /*!< SCB SHCSR: MONITORACT Mask */ + +#define SCB_SHCSR_SVCALLACT_Pos 7U /*!< SCB SHCSR: SVCALLACT Position */ +#define SCB_SHCSR_SVCALLACT_Msk (1UL << SCB_SHCSR_SVCALLACT_Pos) /*!< SCB SHCSR: SVCALLACT Mask */ + +#define SCB_SHCSR_USGFAULTACT_Pos 3U /*!< SCB SHCSR: USGFAULTACT Position */ +#define SCB_SHCSR_USGFAULTACT_Msk (1UL << SCB_SHCSR_USGFAULTACT_Pos) /*!< SCB SHCSR: USGFAULTACT Mask */ + +#define SCB_SHCSR_BUSFAULTACT_Pos 1U /*!< SCB SHCSR: BUSFAULTACT Position */ +#define SCB_SHCSR_BUSFAULTACT_Msk (1UL << SCB_SHCSR_BUSFAULTACT_Pos) /*!< SCB SHCSR: BUSFAULTACT Mask */ + +#define SCB_SHCSR_MEMFAULTACT_Pos 0U /*!< SCB SHCSR: MEMFAULTACT Position */ +#define SCB_SHCSR_MEMFAULTACT_Msk (1UL /*<< SCB_SHCSR_MEMFAULTACT_Pos*/) /*!< SCB SHCSR: MEMFAULTACT Mask */ + +/* SCB Configurable Fault Status Register Definitions */ +#define SCB_CFSR_USGFAULTSR_Pos 16U /*!< SCB CFSR: Usage Fault Status Register Position */ +#define SCB_CFSR_USGFAULTSR_Msk (0xFFFFUL << SCB_CFSR_USGFAULTSR_Pos) /*!< SCB CFSR: Usage Fault Status Register Mask */ + +#define SCB_CFSR_BUSFAULTSR_Pos 8U /*!< SCB CFSR: Bus Fault Status Register Position */ +#define SCB_CFSR_BUSFAULTSR_Msk (0xFFUL << SCB_CFSR_BUSFAULTSR_Pos) /*!< SCB CFSR: Bus Fault Status Register Mask */ + +#define SCB_CFSR_MEMFAULTSR_Pos 0U /*!< SCB CFSR: Memory Manage Fault Status Register Position */ +#define SCB_CFSR_MEMFAULTSR_Msk (0xFFUL /*<< SCB_CFSR_MEMFAULTSR_Pos*/) /*!< SCB CFSR: Memory Manage Fault Status Register Mask */ + +/* SCB Hard Fault Status Register Definitions */ +#define SCB_HFSR_DEBUGEVT_Pos 31U /*!< SCB HFSR: DEBUGEVT Position */ +#define SCB_HFSR_DEBUGEVT_Msk (1UL << SCB_HFSR_DEBUGEVT_Pos) /*!< SCB HFSR: DEBUGEVT Mask */ + +#define SCB_HFSR_FORCED_Pos 30U /*!< SCB HFSR: FORCED Position */ +#define SCB_HFSR_FORCED_Msk (1UL << SCB_HFSR_FORCED_Pos) /*!< SCB HFSR: FORCED Mask */ + +#define SCB_HFSR_VECTTBL_Pos 1U /*!< SCB HFSR: VECTTBL Position */ +#define SCB_HFSR_VECTTBL_Msk (1UL << SCB_HFSR_VECTTBL_Pos) /*!< SCB HFSR: VECTTBL Mask */ + +/* SCB Debug Fault Status Register Definitions */ +#define SCB_DFSR_EXTERNAL_Pos 4U /*!< SCB DFSR: EXTERNAL Position */ +#define SCB_DFSR_EXTERNAL_Msk (1UL << SCB_DFSR_EXTERNAL_Pos) /*!< SCB DFSR: EXTERNAL Mask */ + +#define SCB_DFSR_VCATCH_Pos 3U /*!< SCB DFSR: VCATCH Position */ +#define SCB_DFSR_VCATCH_Msk (1UL << SCB_DFSR_VCATCH_Pos) /*!< SCB DFSR: VCATCH Mask */ + +#define SCB_DFSR_DWTTRAP_Pos 2U /*!< SCB DFSR: DWTTRAP Position */ +#define SCB_DFSR_DWTTRAP_Msk (1UL << SCB_DFSR_DWTTRAP_Pos) /*!< SCB DFSR: DWTTRAP Mask */ + +#define SCB_DFSR_BKPT_Pos 1U /*!< SCB DFSR: BKPT Position */ +#define SCB_DFSR_BKPT_Msk (1UL << SCB_DFSR_BKPT_Pos) /*!< SCB DFSR: BKPT Mask */ + +#define SCB_DFSR_HALTED_Pos 0U /*!< SCB DFSR: HALTED Position */ +#define SCB_DFSR_HALTED_Msk (1UL /*<< SCB_DFSR_HALTED_Pos*/) /*!< SCB DFSR: HALTED Mask */ + +/* SCB Cache Level ID Register Definitions */ +#define SCB_CLIDR_LOUU_Pos 27U /*!< SCB CLIDR: LoUU Position */ +#define SCB_CLIDR_LOUU_Msk (7UL << SCB_CLIDR_LOUU_Pos) /*!< SCB CLIDR: LoUU Mask */ + +#define SCB_CLIDR_LOC_Pos 24U /*!< SCB CLIDR: LoC Position */ +#define SCB_CLIDR_LOC_Msk (7UL << SCB_CLIDR_LOC_Pos) /*!< SCB CLIDR: LoC Mask */ + +/* SCB Cache Type Register Definitions */ +#define SCB_CTR_FORMAT_Pos 29U /*!< SCB CTR: Format Position */ +#define SCB_CTR_FORMAT_Msk (7UL << SCB_CTR_FORMAT_Pos) /*!< SCB CTR: Format Mask */ + +#define SCB_CTR_CWG_Pos 24U /*!< SCB CTR: CWG Position */ +#define SCB_CTR_CWG_Msk (0xFUL << SCB_CTR_CWG_Pos) /*!< SCB CTR: CWG Mask */ + +#define SCB_CTR_ERG_Pos 20U /*!< SCB CTR: ERG Position */ +#define SCB_CTR_ERG_Msk (0xFUL << SCB_CTR_ERG_Pos) /*!< SCB CTR: ERG Mask */ + +#define SCB_CTR_DMINLINE_Pos 16U /*!< SCB CTR: DminLine Position */ +#define SCB_CTR_DMINLINE_Msk (0xFUL << SCB_CTR_DMINLINE_Pos) /*!< SCB CTR: DminLine Mask */ + +#define SCB_CTR_IMINLINE_Pos 0U /*!< SCB CTR: ImInLine Position */ +#define SCB_CTR_IMINLINE_Msk (0xFUL /*<< SCB_CTR_IMINLINE_Pos*/) /*!< SCB CTR: ImInLine Mask */ + +/* SCB Cache Size ID Register Definitions */ +#define SCB_CCSIDR_WT_Pos 31U /*!< SCB CCSIDR: WT Position */ +#define SCB_CCSIDR_WT_Msk (1UL << SCB_CCSIDR_WT_Pos) /*!< SCB CCSIDR: WT Mask */ + +#define SCB_CCSIDR_WB_Pos 30U /*!< SCB CCSIDR: WB Position */ +#define SCB_CCSIDR_WB_Msk (1UL << SCB_CCSIDR_WB_Pos) /*!< SCB CCSIDR: WB Mask */ + +#define SCB_CCSIDR_RA_Pos 29U /*!< SCB CCSIDR: RA Position */ +#define SCB_CCSIDR_RA_Msk (1UL << SCB_CCSIDR_RA_Pos) /*!< SCB CCSIDR: RA Mask */ + +#define SCB_CCSIDR_WA_Pos 28U /*!< SCB CCSIDR: WA Position */ +#define SCB_CCSIDR_WA_Msk (1UL << SCB_CCSIDR_WA_Pos) /*!< SCB CCSIDR: WA Mask */ + +#define SCB_CCSIDR_NUMSETS_Pos 13U /*!< SCB CCSIDR: NumSets Position */ +#define SCB_CCSIDR_NUMSETS_Msk (0x7FFFUL << SCB_CCSIDR_NUMSETS_Pos) /*!< SCB CCSIDR: NumSets Mask */ + +#define SCB_CCSIDR_ASSOCIATIVITY_Pos 3U /*!< SCB CCSIDR: Associativity Position */ +#define SCB_CCSIDR_ASSOCIATIVITY_Msk (0x3FFUL << SCB_CCSIDR_ASSOCIATIVITY_Pos) /*!< SCB CCSIDR: Associativity Mask */ + +#define SCB_CCSIDR_LINESIZE_Pos 0U /*!< SCB CCSIDR: LineSize Position */ +#define SCB_CCSIDR_LINESIZE_Msk (7UL /*<< SCB_CCSIDR_LINESIZE_Pos*/) /*!< SCB CCSIDR: LineSize Mask */ + +/* SCB Cache Size Selection Register Definitions */ +#define SCB_CSSELR_LEVEL_Pos 1U /*!< SCB CSSELR: Level Position */ +#define SCB_CSSELR_LEVEL_Msk (7UL << SCB_CSSELR_LEVEL_Pos) /*!< SCB CSSELR: Level Mask */ + +#define SCB_CSSELR_IND_Pos 0U /*!< SCB CSSELR: InD Position */ +#define SCB_CSSELR_IND_Msk (1UL /*<< SCB_CSSELR_IND_Pos*/) /*!< SCB CSSELR: InD Mask */ + +/* SCB Software Triggered Interrupt Register Definitions */ +#define SCB_STIR_INTID_Pos 0U /*!< SCB STIR: INTID Position */ +#define SCB_STIR_INTID_Msk (0x1FFUL /*<< SCB_STIR_INTID_Pos*/) /*!< SCB STIR: INTID Mask */ + +/* SCB D-Cache Invalidate by Set-way Register Definitions */ +#define SCB_DCISW_WAY_Pos 30U /*!< SCB DCISW: Way Position */ +#define SCB_DCISW_WAY_Msk (3UL << SCB_DCISW_WAY_Pos) /*!< SCB DCISW: Way Mask */ + +#define SCB_DCISW_SET_Pos 5U /*!< SCB DCISW: Set Position */ +#define SCB_DCISW_SET_Msk (0x1FFUL << SCB_DCISW_SET_Pos) /*!< SCB DCISW: Set Mask */ + +/* SCB D-Cache Clean by Set-way Register Definitions */ +#define SCB_DCCSW_WAY_Pos 30U /*!< SCB DCCSW: Way Position */ +#define SCB_DCCSW_WAY_Msk (3UL << SCB_DCCSW_WAY_Pos) /*!< SCB DCCSW: Way Mask */ + +#define SCB_DCCSW_SET_Pos 5U /*!< SCB DCCSW: Set Position */ +#define SCB_DCCSW_SET_Msk (0x1FFUL << SCB_DCCSW_SET_Pos) /*!< SCB DCCSW: Set Mask */ + +/* SCB D-Cache Clean and Invalidate by Set-way Register Definitions */ +#define SCB_DCCISW_WAY_Pos 30U /*!< SCB DCCISW: Way Position */ +#define SCB_DCCISW_WAY_Msk (3UL << SCB_DCCISW_WAY_Pos) /*!< SCB DCCISW: Way Mask */ + +#define SCB_DCCISW_SET_Pos 5U /*!< SCB DCCISW: Set Position */ +#define SCB_DCCISW_SET_Msk (0x1FFUL << SCB_DCCISW_SET_Pos) /*!< SCB DCCISW: Set Mask */ + +/* Instruction Tightly-Coupled Memory Control Register Definitions */ +#define SCB_ITCMCR_SZ_Pos 3U /*!< SCB ITCMCR: SZ Position */ +#define SCB_ITCMCR_SZ_Msk (0xFUL << SCB_ITCMCR_SZ_Pos) /*!< SCB ITCMCR: SZ Mask */ + +#define SCB_ITCMCR_RETEN_Pos 2U /*!< SCB ITCMCR: RETEN Position */ +#define SCB_ITCMCR_RETEN_Msk (1UL << SCB_ITCMCR_RETEN_Pos) /*!< SCB ITCMCR: RETEN Mask */ + +#define SCB_ITCMCR_RMW_Pos 1U /*!< SCB ITCMCR: RMW Position */ +#define SCB_ITCMCR_RMW_Msk (1UL << SCB_ITCMCR_RMW_Pos) /*!< SCB ITCMCR: RMW Mask */ + +#define SCB_ITCMCR_EN_Pos 0U /*!< SCB ITCMCR: EN Position */ +#define SCB_ITCMCR_EN_Msk (1UL /*<< SCB_ITCMCR_EN_Pos*/) /*!< SCB ITCMCR: EN Mask */ + +/* Data Tightly-Coupled Memory Control Register Definitions */ +#define SCB_DTCMCR_SZ_Pos 3U /*!< SCB DTCMCR: SZ Position */ +#define SCB_DTCMCR_SZ_Msk (0xFUL << SCB_DTCMCR_SZ_Pos) /*!< SCB DTCMCR: SZ Mask */ + +#define SCB_DTCMCR_RETEN_Pos 2U /*!< SCB DTCMCR: RETEN Position */ +#define SCB_DTCMCR_RETEN_Msk (1UL << SCB_DTCMCR_RETEN_Pos) /*!< SCB DTCMCR: RETEN Mask */ + +#define SCB_DTCMCR_RMW_Pos 1U /*!< SCB DTCMCR: RMW Position */ +#define SCB_DTCMCR_RMW_Msk (1UL << SCB_DTCMCR_RMW_Pos) /*!< SCB DTCMCR: RMW Mask */ + +#define SCB_DTCMCR_EN_Pos 0U /*!< SCB DTCMCR: EN Position */ +#define SCB_DTCMCR_EN_Msk (1UL /*<< SCB_DTCMCR_EN_Pos*/) /*!< SCB DTCMCR: EN Mask */ + +/* AHBP Control Register Definitions */ +#define SCB_AHBPCR_SZ_Pos 1U /*!< SCB AHBPCR: SZ Position */ +#define SCB_AHBPCR_SZ_Msk (7UL << SCB_AHBPCR_SZ_Pos) /*!< SCB AHBPCR: SZ Mask */ + +#define SCB_AHBPCR_EN_Pos 0U /*!< SCB AHBPCR: EN Position */ +#define SCB_AHBPCR_EN_Msk (1UL /*<< SCB_AHBPCR_EN_Pos*/) /*!< SCB AHBPCR: EN Mask */ + +/* L1 Cache Control Register Definitions */ +#define SCB_CACR_FORCEWT_Pos 2U /*!< SCB CACR: FORCEWT Position */ +#define SCB_CACR_FORCEWT_Msk (1UL << SCB_CACR_FORCEWT_Pos) /*!< SCB CACR: FORCEWT Mask */ + +#define SCB_CACR_ECCEN_Pos 1U /*!< SCB CACR: ECCEN Position */ +#define SCB_CACR_ECCEN_Msk (1UL << SCB_CACR_ECCEN_Pos) /*!< SCB CACR: ECCEN Mask */ + +#define SCB_CACR_SIWT_Pos 0U /*!< SCB CACR: SIWT Position */ +#define SCB_CACR_SIWT_Msk (1UL /*<< SCB_CACR_SIWT_Pos*/) /*!< SCB CACR: SIWT Mask */ + +/* AHBS Control Register Definitions */ +#define SCB_AHBSCR_INITCOUNT_Pos 11U /*!< SCB AHBSCR: INITCOUNT Position */ +#define SCB_AHBSCR_INITCOUNT_Msk (0x1FUL << SCB_AHBPCR_INITCOUNT_Pos) /*!< SCB AHBSCR: INITCOUNT Mask */ + +#define SCB_AHBSCR_TPRI_Pos 2U /*!< SCB AHBSCR: TPRI Position */ +#define SCB_AHBSCR_TPRI_Msk (0x1FFUL << SCB_AHBPCR_TPRI_Pos) /*!< SCB AHBSCR: TPRI Mask */ + +#define SCB_AHBSCR_CTL_Pos 0U /*!< SCB AHBSCR: CTL Position*/ +#define SCB_AHBSCR_CTL_Msk (3UL /*<< SCB_AHBPCR_CTL_Pos*/) /*!< SCB AHBSCR: CTL Mask */ + +/* Auxiliary Bus Fault Status Register Definitions */ +#define SCB_ABFSR_AXIMTYPE_Pos 8U /*!< SCB ABFSR: AXIMTYPE Position*/ +#define SCB_ABFSR_AXIMTYPE_Msk (3UL << SCB_ABFSR_AXIMTYPE_Pos) /*!< SCB ABFSR: AXIMTYPE Mask */ + +#define SCB_ABFSR_EPPB_Pos 4U /*!< SCB ABFSR: EPPB Position*/ +#define SCB_ABFSR_EPPB_Msk (1UL << SCB_ABFSR_EPPB_Pos) /*!< SCB ABFSR: EPPB Mask */ + +#define SCB_ABFSR_AXIM_Pos 3U /*!< SCB ABFSR: AXIM Position*/ +#define SCB_ABFSR_AXIM_Msk (1UL << SCB_ABFSR_AXIM_Pos) /*!< SCB ABFSR: AXIM Mask */ + +#define SCB_ABFSR_AHBP_Pos 2U /*!< SCB ABFSR: AHBP Position*/ +#define SCB_ABFSR_AHBP_Msk (1UL << SCB_ABFSR_AHBP_Pos) /*!< SCB ABFSR: AHBP Mask */ + +#define SCB_ABFSR_DTCM_Pos 1U /*!< SCB ABFSR: DTCM Position*/ +#define SCB_ABFSR_DTCM_Msk (1UL << SCB_ABFSR_DTCM_Pos) /*!< SCB ABFSR: DTCM Mask */ + +#define SCB_ABFSR_ITCM_Pos 0U /*!< SCB ABFSR: ITCM Position*/ +#define SCB_ABFSR_ITCM_Msk (1UL /*<< SCB_ABFSR_ITCM_Pos*/) /*!< SCB ABFSR: ITCM Mask */ + +/*@} end of group CMSIS_SCB */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SCnSCB System Controls not in SCB (SCnSCB) + \brief Type definitions for the System Control and ID Register not in the SCB + @{ + */ + +/** + \brief Structure type to access the System Control and ID Register not in the SCB. + */ +typedef struct +{ + uint32_t RESERVED0[1U]; + __IM uint32_t ICTR; /*!< Offset: 0x004 (R/ ) Interrupt Controller Type Register */ + __IOM uint32_t ACTLR; /*!< Offset: 0x008 (R/W) Auxiliary Control Register */ +} SCnSCB_Type; + +/* Interrupt Controller Type Register Definitions */ +#define SCnSCB_ICTR_INTLINESNUM_Pos 0U /*!< ICTR: INTLINESNUM Position */ +#define SCnSCB_ICTR_INTLINESNUM_Msk (0xFUL /*<< SCnSCB_ICTR_INTLINESNUM_Pos*/) /*!< ICTR: INTLINESNUM Mask */ + +/* Auxiliary Control Register Definitions */ +#define SCnSCB_ACTLR_DISITMATBFLUSH_Pos 12U /*!< ACTLR: DISITMATBFLUSH Position */ +#define SCnSCB_ACTLR_DISITMATBFLUSH_Msk (1UL << SCnSCB_ACTLR_DISITMATBFLUSH_Pos) /*!< ACTLR: DISITMATBFLUSH Mask */ + +#define SCnSCB_ACTLR_DISRAMODE_Pos 11U /*!< ACTLR: DISRAMODE Position */ +#define SCnSCB_ACTLR_DISRAMODE_Msk (1UL << SCnSCB_ACTLR_DISRAMODE_Pos) /*!< ACTLR: DISRAMODE Mask */ + +#define SCnSCB_ACTLR_FPEXCODIS_Pos 10U /*!< ACTLR: FPEXCODIS Position */ +#define SCnSCB_ACTLR_FPEXCODIS_Msk (1UL << SCnSCB_ACTLR_FPEXCODIS_Pos) /*!< ACTLR: FPEXCODIS Mask */ + +#define SCnSCB_ACTLR_DISFOLD_Pos 2U /*!< ACTLR: DISFOLD Position */ +#define SCnSCB_ACTLR_DISFOLD_Msk (1UL << SCnSCB_ACTLR_DISFOLD_Pos) /*!< ACTLR: DISFOLD Mask */ + +#define SCnSCB_ACTLR_DISMCYCINT_Pos 0U /*!< ACTLR: DISMCYCINT Position */ +#define SCnSCB_ACTLR_DISMCYCINT_Msk (1UL /*<< SCnSCB_ACTLR_DISMCYCINT_Pos*/) /*!< ACTLR: DISMCYCINT Mask */ + +/*@} end of group CMSIS_SCnotSCB */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SysTick System Tick Timer (SysTick) + \brief Type definitions for the System Timer Registers. + @{ + */ + +/** + \brief Structure type to access the System Timer (SysTick). + */ +typedef struct +{ + __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */ + __IOM uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */ + __IOM uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register */ + __IM uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */ +} SysTick_Type; + +/* SysTick Control / Status Register Definitions */ +#define SysTick_CTRL_COUNTFLAG_Pos 16U /*!< SysTick CTRL: COUNTFLAG Position */ +#define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */ + +#define SysTick_CTRL_CLKSOURCE_Pos 2U /*!< SysTick CTRL: CLKSOURCE Position */ +#define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */ + +#define SysTick_CTRL_TICKINT_Pos 1U /*!< SysTick CTRL: TICKINT Position */ +#define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */ + +#define SysTick_CTRL_ENABLE_Pos 0U /*!< SysTick CTRL: ENABLE Position */ +#define SysTick_CTRL_ENABLE_Msk (1UL /*<< SysTick_CTRL_ENABLE_Pos*/) /*!< SysTick CTRL: ENABLE Mask */ + +/* SysTick Reload Register Definitions */ +#define SysTick_LOAD_RELOAD_Pos 0U /*!< SysTick LOAD: RELOAD Position */ +#define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/) /*!< SysTick LOAD: RELOAD Mask */ + +/* SysTick Current Register Definitions */ +#define SysTick_VAL_CURRENT_Pos 0U /*!< SysTick VAL: CURRENT Position */ +#define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/) /*!< SysTick VAL: CURRENT Mask */ + +/* SysTick Calibration Register Definitions */ +#define SysTick_CALIB_NOREF_Pos 31U /*!< SysTick CALIB: NOREF Position */ +#define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */ + +#define SysTick_CALIB_SKEW_Pos 30U /*!< SysTick CALIB: SKEW Position */ +#define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */ + +#define SysTick_CALIB_TENMS_Pos 0U /*!< SysTick CALIB: TENMS Position */ +#define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/) /*!< SysTick CALIB: TENMS Mask */ + +/*@} end of group CMSIS_SysTick */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_ITM Instrumentation Trace Macrocell (ITM) + \brief Type definitions for the Instrumentation Trace Macrocell (ITM) + @{ + */ + +/** + \brief Structure type to access the Instrumentation Trace Macrocell Register (ITM). + */ +typedef struct +{ + __OM union + { + __OM uint8_t u8; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 8-bit */ + __OM uint16_t u16; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 16-bit */ + __OM uint32_t u32; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 32-bit */ + } PORT [32U]; /*!< Offset: 0x000 ( /W) ITM Stimulus Port Registers */ + uint32_t RESERVED0[864U]; + __IOM uint32_t TER; /*!< Offset: 0xE00 (R/W) ITM Trace Enable Register */ + uint32_t RESERVED1[15U]; + __IOM uint32_t TPR; /*!< Offset: 0xE40 (R/W) ITM Trace Privilege Register */ + uint32_t RESERVED2[15U]; + __IOM uint32_t TCR; /*!< Offset: 0xE80 (R/W) ITM Trace Control Register */ + uint32_t RESERVED3[29U]; + __OM uint32_t IWR; /*!< Offset: 0xEF8 ( /W) ITM Integration Write Register */ + __IM uint32_t IRR; /*!< Offset: 0xEFC (R/ ) ITM Integration Read Register */ + __IOM uint32_t IMCR; /*!< Offset: 0xF00 (R/W) ITM Integration Mode Control Register */ + uint32_t RESERVED4[43U]; + __OM uint32_t LAR; /*!< Offset: 0xFB0 ( /W) ITM Lock Access Register */ + __IM uint32_t LSR; /*!< Offset: 0xFB4 (R/ ) ITM Lock Status Register */ + uint32_t RESERVED5[6U]; + __IM uint32_t PID4; /*!< Offset: 0xFD0 (R/ ) ITM Peripheral Identification Register #4 */ + __IM uint32_t PID5; /*!< Offset: 0xFD4 (R/ ) ITM Peripheral Identification Register #5 */ + __IM uint32_t PID6; /*!< Offset: 0xFD8 (R/ ) ITM Peripheral Identification Register #6 */ + __IM uint32_t PID7; /*!< Offset: 0xFDC (R/ ) ITM Peripheral Identification Register #7 */ + __IM uint32_t PID0; /*!< Offset: 0xFE0 (R/ ) ITM Peripheral Identification Register #0 */ + __IM uint32_t PID1; /*!< Offset: 0xFE4 (R/ ) ITM Peripheral Identification Register #1 */ + __IM uint32_t PID2; /*!< Offset: 0xFE8 (R/ ) ITM Peripheral Identification Register #2 */ + __IM uint32_t PID3; /*!< Offset: 0xFEC (R/ ) ITM Peripheral Identification Register #3 */ + __IM uint32_t CID0; /*!< Offset: 0xFF0 (R/ ) ITM Component Identification Register #0 */ + __IM uint32_t CID1; /*!< Offset: 0xFF4 (R/ ) ITM Component Identification Register #1 */ + __IM uint32_t CID2; /*!< Offset: 0xFF8 (R/ ) ITM Component Identification Register #2 */ + __IM uint32_t CID3; /*!< Offset: 0xFFC (R/ ) ITM Component Identification Register #3 */ +} ITM_Type; + +/* ITM Trace Privilege Register Definitions */ +#define ITM_TPR_PRIVMASK_Pos 0U /*!< ITM TPR: PRIVMASK Position */ +#define ITM_TPR_PRIVMASK_Msk (0xFUL /*<< ITM_TPR_PRIVMASK_Pos*/) /*!< ITM TPR: PRIVMASK Mask */ + +/* ITM Trace Control Register Definitions */ +#define ITM_TCR_BUSY_Pos 23U /*!< ITM TCR: BUSY Position */ +#define ITM_TCR_BUSY_Msk (1UL << ITM_TCR_BUSY_Pos) /*!< ITM TCR: BUSY Mask */ + +#define ITM_TCR_TraceBusID_Pos 16U /*!< ITM TCR: ATBID Position */ +#define ITM_TCR_TraceBusID_Msk (0x7FUL << ITM_TCR_TraceBusID_Pos) /*!< ITM TCR: ATBID Mask */ + +#define ITM_TCR_GTSFREQ_Pos 10U /*!< ITM TCR: Global timestamp frequency Position */ +#define ITM_TCR_GTSFREQ_Msk (3UL << ITM_TCR_GTSFREQ_Pos) /*!< ITM TCR: Global timestamp frequency Mask */ + +#define ITM_TCR_TSPrescale_Pos 8U /*!< ITM TCR: TSPrescale Position */ +#define ITM_TCR_TSPrescale_Msk (3UL << ITM_TCR_TSPrescale_Pos) /*!< ITM TCR: TSPrescale Mask */ + +#define ITM_TCR_SWOENA_Pos 4U /*!< ITM TCR: SWOENA Position */ +#define ITM_TCR_SWOENA_Msk (1UL << ITM_TCR_SWOENA_Pos) /*!< ITM TCR: SWOENA Mask */ + +#define ITM_TCR_DWTENA_Pos 3U /*!< ITM TCR: DWTENA Position */ +#define ITM_TCR_DWTENA_Msk (1UL << ITM_TCR_DWTENA_Pos) /*!< ITM TCR: DWTENA Mask */ + +#define ITM_TCR_SYNCENA_Pos 2U /*!< ITM TCR: SYNCENA Position */ +#define ITM_TCR_SYNCENA_Msk (1UL << ITM_TCR_SYNCENA_Pos) /*!< ITM TCR: SYNCENA Mask */ + +#define ITM_TCR_TSENA_Pos 1U /*!< ITM TCR: TSENA Position */ +#define ITM_TCR_TSENA_Msk (1UL << ITM_TCR_TSENA_Pos) /*!< ITM TCR: TSENA Mask */ + +#define ITM_TCR_ITMENA_Pos 0U /*!< ITM TCR: ITM Enable bit Position */ +#define ITM_TCR_ITMENA_Msk (1UL /*<< ITM_TCR_ITMENA_Pos*/) /*!< ITM TCR: ITM Enable bit Mask */ + +/* ITM Integration Write Register Definitions */ +#define ITM_IWR_ATVALIDM_Pos 0U /*!< ITM IWR: ATVALIDM Position */ +#define ITM_IWR_ATVALIDM_Msk (1UL /*<< ITM_IWR_ATVALIDM_Pos*/) /*!< ITM IWR: ATVALIDM Mask */ + +/* ITM Integration Read Register Definitions */ +#define ITM_IRR_ATREADYM_Pos 0U /*!< ITM IRR: ATREADYM Position */ +#define ITM_IRR_ATREADYM_Msk (1UL /*<< ITM_IRR_ATREADYM_Pos*/) /*!< ITM IRR: ATREADYM Mask */ + +/* ITM Integration Mode Control Register Definitions */ +#define ITM_IMCR_INTEGRATION_Pos 0U /*!< ITM IMCR: INTEGRATION Position */ +#define ITM_IMCR_INTEGRATION_Msk (1UL /*<< ITM_IMCR_INTEGRATION_Pos*/) /*!< ITM IMCR: INTEGRATION Mask */ + +/* ITM Lock Status Register Definitions */ +#define ITM_LSR_ByteAcc_Pos 2U /*!< ITM LSR: ByteAcc Position */ +#define ITM_LSR_ByteAcc_Msk (1UL << ITM_LSR_ByteAcc_Pos) /*!< ITM LSR: ByteAcc Mask */ + +#define ITM_LSR_Access_Pos 1U /*!< ITM LSR: Access Position */ +#define ITM_LSR_Access_Msk (1UL << ITM_LSR_Access_Pos) /*!< ITM LSR: Access Mask */ + +#define ITM_LSR_Present_Pos 0U /*!< ITM LSR: Present Position */ +#define ITM_LSR_Present_Msk (1UL /*<< ITM_LSR_Present_Pos*/) /*!< ITM LSR: Present Mask */ + +/*@}*/ /* end of group CMSIS_ITM */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_DWT Data Watchpoint and Trace (DWT) + \brief Type definitions for the Data Watchpoint and Trace (DWT) + @{ + */ + +/** + \brief Structure type to access the Data Watchpoint and Trace Register (DWT). + */ +typedef struct +{ + __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) Control Register */ + __IOM uint32_t CYCCNT; /*!< Offset: 0x004 (R/W) Cycle Count Register */ + __IOM uint32_t CPICNT; /*!< Offset: 0x008 (R/W) CPI Count Register */ + __IOM uint32_t EXCCNT; /*!< Offset: 0x00C (R/W) Exception Overhead Count Register */ + __IOM uint32_t SLEEPCNT; /*!< Offset: 0x010 (R/W) Sleep Count Register */ + __IOM uint32_t LSUCNT; /*!< Offset: 0x014 (R/W) LSU Count Register */ + __IOM uint32_t FOLDCNT; /*!< Offset: 0x018 (R/W) Folded-instruction Count Register */ + __IM uint32_t PCSR; /*!< Offset: 0x01C (R/ ) Program Counter Sample Register */ + __IOM uint32_t COMP0; /*!< Offset: 0x020 (R/W) Comparator Register 0 */ + __IOM uint32_t MASK0; /*!< Offset: 0x024 (R/W) Mask Register 0 */ + __IOM uint32_t FUNCTION0; /*!< Offset: 0x028 (R/W) Function Register 0 */ + uint32_t RESERVED0[1U]; + __IOM uint32_t COMP1; /*!< Offset: 0x030 (R/W) Comparator Register 1 */ + __IOM uint32_t MASK1; /*!< Offset: 0x034 (R/W) Mask Register 1 */ + __IOM uint32_t FUNCTION1; /*!< Offset: 0x038 (R/W) Function Register 1 */ + uint32_t RESERVED1[1U]; + __IOM uint32_t COMP2; /*!< Offset: 0x040 (R/W) Comparator Register 2 */ + __IOM uint32_t MASK2; /*!< Offset: 0x044 (R/W) Mask Register 2 */ + __IOM uint32_t FUNCTION2; /*!< Offset: 0x048 (R/W) Function Register 2 */ + uint32_t RESERVED2[1U]; + __IOM uint32_t COMP3; /*!< Offset: 0x050 (R/W) Comparator Register 3 */ + __IOM uint32_t MASK3; /*!< Offset: 0x054 (R/W) Mask Register 3 */ + __IOM uint32_t FUNCTION3; /*!< Offset: 0x058 (R/W) Function Register 3 */ + uint32_t RESERVED3[981U]; + __OM uint32_t LAR; /*!< Offset: 0xFB0 ( W) Lock Access Register */ + __IM uint32_t LSR; /*!< Offset: 0xFB4 (R ) Lock Status Register */ +} DWT_Type; + +/* DWT Control Register Definitions */ +#define DWT_CTRL_NUMCOMP_Pos 28U /*!< DWT CTRL: NUMCOMP Position */ +#define DWT_CTRL_NUMCOMP_Msk (0xFUL << DWT_CTRL_NUMCOMP_Pos) /*!< DWT CTRL: NUMCOMP Mask */ + +#define DWT_CTRL_NOTRCPKT_Pos 27U /*!< DWT CTRL: NOTRCPKT Position */ +#define DWT_CTRL_NOTRCPKT_Msk (0x1UL << DWT_CTRL_NOTRCPKT_Pos) /*!< DWT CTRL: NOTRCPKT Mask */ + +#define DWT_CTRL_NOEXTTRIG_Pos 26U /*!< DWT CTRL: NOEXTTRIG Position */ +#define DWT_CTRL_NOEXTTRIG_Msk (0x1UL << DWT_CTRL_NOEXTTRIG_Pos) /*!< DWT CTRL: NOEXTTRIG Mask */ + +#define DWT_CTRL_NOCYCCNT_Pos 25U /*!< DWT CTRL: NOCYCCNT Position */ +#define DWT_CTRL_NOCYCCNT_Msk (0x1UL << DWT_CTRL_NOCYCCNT_Pos) /*!< DWT CTRL: NOCYCCNT Mask */ + +#define DWT_CTRL_NOPRFCNT_Pos 24U /*!< DWT CTRL: NOPRFCNT Position */ +#define DWT_CTRL_NOPRFCNT_Msk (0x1UL << DWT_CTRL_NOPRFCNT_Pos) /*!< DWT CTRL: NOPRFCNT Mask */ + +#define DWT_CTRL_CYCEVTENA_Pos 22U /*!< DWT CTRL: CYCEVTENA Position */ +#define DWT_CTRL_CYCEVTENA_Msk (0x1UL << DWT_CTRL_CYCEVTENA_Pos) /*!< DWT CTRL: CYCEVTENA Mask */ + +#define DWT_CTRL_FOLDEVTENA_Pos 21U /*!< DWT CTRL: FOLDEVTENA Position */ +#define DWT_CTRL_FOLDEVTENA_Msk (0x1UL << DWT_CTRL_FOLDEVTENA_Pos) /*!< DWT CTRL: FOLDEVTENA Mask */ + +#define DWT_CTRL_LSUEVTENA_Pos 20U /*!< DWT CTRL: LSUEVTENA Position */ +#define DWT_CTRL_LSUEVTENA_Msk (0x1UL << DWT_CTRL_LSUEVTENA_Pos) /*!< DWT CTRL: LSUEVTENA Mask */ + +#define DWT_CTRL_SLEEPEVTENA_Pos 19U /*!< DWT CTRL: SLEEPEVTENA Position */ +#define DWT_CTRL_SLEEPEVTENA_Msk (0x1UL << DWT_CTRL_SLEEPEVTENA_Pos) /*!< DWT CTRL: SLEEPEVTENA Mask */ + +#define DWT_CTRL_EXCEVTENA_Pos 18U /*!< DWT CTRL: EXCEVTENA Position */ +#define DWT_CTRL_EXCEVTENA_Msk (0x1UL << DWT_CTRL_EXCEVTENA_Pos) /*!< DWT CTRL: EXCEVTENA Mask */ + +#define DWT_CTRL_CPIEVTENA_Pos 17U /*!< DWT CTRL: CPIEVTENA Position */ +#define DWT_CTRL_CPIEVTENA_Msk (0x1UL << DWT_CTRL_CPIEVTENA_Pos) /*!< DWT CTRL: CPIEVTENA Mask */ + +#define DWT_CTRL_EXCTRCENA_Pos 16U /*!< DWT CTRL: EXCTRCENA Position */ +#define DWT_CTRL_EXCTRCENA_Msk (0x1UL << DWT_CTRL_EXCTRCENA_Pos) /*!< DWT CTRL: EXCTRCENA Mask */ + +#define DWT_CTRL_PCSAMPLENA_Pos 12U /*!< DWT CTRL: PCSAMPLENA Position */ +#define DWT_CTRL_PCSAMPLENA_Msk (0x1UL << DWT_CTRL_PCSAMPLENA_Pos) /*!< DWT CTRL: PCSAMPLENA Mask */ + +#define DWT_CTRL_SYNCTAP_Pos 10U /*!< DWT CTRL: SYNCTAP Position */ +#define DWT_CTRL_SYNCTAP_Msk (0x3UL << DWT_CTRL_SYNCTAP_Pos) /*!< DWT CTRL: SYNCTAP Mask */ + +#define DWT_CTRL_CYCTAP_Pos 9U /*!< DWT CTRL: CYCTAP Position */ +#define DWT_CTRL_CYCTAP_Msk (0x1UL << DWT_CTRL_CYCTAP_Pos) /*!< DWT CTRL: CYCTAP Mask */ + +#define DWT_CTRL_POSTINIT_Pos 5U /*!< DWT CTRL: POSTINIT Position */ +#define DWT_CTRL_POSTINIT_Msk (0xFUL << DWT_CTRL_POSTINIT_Pos) /*!< DWT CTRL: POSTINIT Mask */ + +#define DWT_CTRL_POSTPRESET_Pos 1U /*!< DWT CTRL: POSTPRESET Position */ +#define DWT_CTRL_POSTPRESET_Msk (0xFUL << DWT_CTRL_POSTPRESET_Pos) /*!< DWT CTRL: POSTPRESET Mask */ + +#define DWT_CTRL_CYCCNTENA_Pos 0U /*!< DWT CTRL: CYCCNTENA Position */ +#define DWT_CTRL_CYCCNTENA_Msk (0x1UL /*<< DWT_CTRL_CYCCNTENA_Pos*/) /*!< DWT CTRL: CYCCNTENA Mask */ + +/* DWT CPI Count Register Definitions */ +#define DWT_CPICNT_CPICNT_Pos 0U /*!< DWT CPICNT: CPICNT Position */ +#define DWT_CPICNT_CPICNT_Msk (0xFFUL /*<< DWT_CPICNT_CPICNT_Pos*/) /*!< DWT CPICNT: CPICNT Mask */ + +/* DWT Exception Overhead Count Register Definitions */ +#define DWT_EXCCNT_EXCCNT_Pos 0U /*!< DWT EXCCNT: EXCCNT Position */ +#define DWT_EXCCNT_EXCCNT_Msk (0xFFUL /*<< DWT_EXCCNT_EXCCNT_Pos*/) /*!< DWT EXCCNT: EXCCNT Mask */ + +/* DWT Sleep Count Register Definitions */ +#define DWT_SLEEPCNT_SLEEPCNT_Pos 0U /*!< DWT SLEEPCNT: SLEEPCNT Position */ +#define DWT_SLEEPCNT_SLEEPCNT_Msk (0xFFUL /*<< DWT_SLEEPCNT_SLEEPCNT_Pos*/) /*!< DWT SLEEPCNT: SLEEPCNT Mask */ + +/* DWT LSU Count Register Definitions */ +#define DWT_LSUCNT_LSUCNT_Pos 0U /*!< DWT LSUCNT: LSUCNT Position */ +#define DWT_LSUCNT_LSUCNT_Msk (0xFFUL /*<< DWT_LSUCNT_LSUCNT_Pos*/) /*!< DWT LSUCNT: LSUCNT Mask */ + +/* DWT Folded-instruction Count Register Definitions */ +#define DWT_FOLDCNT_FOLDCNT_Pos 0U /*!< DWT FOLDCNT: FOLDCNT Position */ +#define DWT_FOLDCNT_FOLDCNT_Msk (0xFFUL /*<< DWT_FOLDCNT_FOLDCNT_Pos*/) /*!< DWT FOLDCNT: FOLDCNT Mask */ + +/* DWT Comparator Mask Register Definitions */ +#define DWT_MASK_MASK_Pos 0U /*!< DWT MASK: MASK Position */ +#define DWT_MASK_MASK_Msk (0x1FUL /*<< DWT_MASK_MASK_Pos*/) /*!< DWT MASK: MASK Mask */ + +/* DWT Comparator Function Register Definitions */ +#define DWT_FUNCTION_MATCHED_Pos 24U /*!< DWT FUNCTION: MATCHED Position */ +#define DWT_FUNCTION_MATCHED_Msk (0x1UL << DWT_FUNCTION_MATCHED_Pos) /*!< DWT FUNCTION: MATCHED Mask */ + +#define DWT_FUNCTION_DATAVADDR1_Pos 16U /*!< DWT FUNCTION: DATAVADDR1 Position */ +#define DWT_FUNCTION_DATAVADDR1_Msk (0xFUL << DWT_FUNCTION_DATAVADDR1_Pos) /*!< DWT FUNCTION: DATAVADDR1 Mask */ + +#define DWT_FUNCTION_DATAVADDR0_Pos 12U /*!< DWT FUNCTION: DATAVADDR0 Position */ +#define DWT_FUNCTION_DATAVADDR0_Msk (0xFUL << DWT_FUNCTION_DATAVADDR0_Pos) /*!< DWT FUNCTION: DATAVADDR0 Mask */ + +#define DWT_FUNCTION_DATAVSIZE_Pos 10U /*!< DWT FUNCTION: DATAVSIZE Position */ +#define DWT_FUNCTION_DATAVSIZE_Msk (0x3UL << DWT_FUNCTION_DATAVSIZE_Pos) /*!< DWT FUNCTION: DATAVSIZE Mask */ + +#define DWT_FUNCTION_LNK1ENA_Pos 9U /*!< DWT FUNCTION: LNK1ENA Position */ +#define DWT_FUNCTION_LNK1ENA_Msk (0x1UL << DWT_FUNCTION_LNK1ENA_Pos) /*!< DWT FUNCTION: LNK1ENA Mask */ + +#define DWT_FUNCTION_DATAVMATCH_Pos 8U /*!< DWT FUNCTION: DATAVMATCH Position */ +#define DWT_FUNCTION_DATAVMATCH_Msk (0x1UL << DWT_FUNCTION_DATAVMATCH_Pos) /*!< DWT FUNCTION: DATAVMATCH Mask */ + +#define DWT_FUNCTION_CYCMATCH_Pos 7U /*!< DWT FUNCTION: CYCMATCH Position */ +#define DWT_FUNCTION_CYCMATCH_Msk (0x1UL << DWT_FUNCTION_CYCMATCH_Pos) /*!< DWT FUNCTION: CYCMATCH Mask */ + +#define DWT_FUNCTION_EMITRANGE_Pos 5U /*!< DWT FUNCTION: EMITRANGE Position */ +#define DWT_FUNCTION_EMITRANGE_Msk (0x1UL << DWT_FUNCTION_EMITRANGE_Pos) /*!< DWT FUNCTION: EMITRANGE Mask */ + +#define DWT_FUNCTION_FUNCTION_Pos 0U /*!< DWT FUNCTION: FUNCTION Position */ +#define DWT_FUNCTION_FUNCTION_Msk (0xFUL /*<< DWT_FUNCTION_FUNCTION_Pos*/) /*!< DWT FUNCTION: FUNCTION Mask */ + +/*@}*/ /* end of group CMSIS_DWT */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_TPI Trace Port Interface (TPI) + \brief Type definitions for the Trace Port Interface (TPI) + @{ + */ + +/** + \brief Structure type to access the Trace Port Interface Register (TPI). + */ +typedef struct +{ + __IOM uint32_t SSPSR; /*!< Offset: 0x000 (R/ ) Supported Parallel Port Size Register */ + __IOM uint32_t CSPSR; /*!< Offset: 0x004 (R/W) Current Parallel Port Size Register */ + uint32_t RESERVED0[2U]; + __IOM uint32_t ACPR; /*!< Offset: 0x010 (R/W) Asynchronous Clock Prescaler Register */ + uint32_t RESERVED1[55U]; + __IOM uint32_t SPPR; /*!< Offset: 0x0F0 (R/W) Selected Pin Protocol Register */ + uint32_t RESERVED2[131U]; + __IM uint32_t FFSR; /*!< Offset: 0x300 (R/ ) Formatter and Flush Status Register */ + __IOM uint32_t FFCR; /*!< Offset: 0x304 (R/W) Formatter and Flush Control Register */ + __IM uint32_t FSCR; /*!< Offset: 0x308 (R/ ) Formatter Synchronization Counter Register */ + uint32_t RESERVED3[759U]; + __IM uint32_t TRIGGER; /*!< Offset: 0xEE8 (R/ ) TRIGGER */ + __IM uint32_t FIFO0; /*!< Offset: 0xEEC (R/ ) Integration ETM Data */ + __IM uint32_t ITATBCTR2; /*!< Offset: 0xEF0 (R/ ) ITATBCTR2 */ + uint32_t RESERVED4[1U]; + __IM uint32_t ITATBCTR0; /*!< Offset: 0xEF8 (R/ ) ITATBCTR0 */ + __IM uint32_t FIFO1; /*!< Offset: 0xEFC (R/ ) Integration ITM Data */ + __IOM uint32_t ITCTRL; /*!< Offset: 0xF00 (R/W) Integration Mode Control */ + uint32_t RESERVED5[39U]; + __IOM uint32_t CLAIMSET; /*!< Offset: 0xFA0 (R/W) Claim tag set */ + __IOM uint32_t CLAIMCLR; /*!< Offset: 0xFA4 (R/W) Claim tag clear */ + uint32_t RESERVED7[8U]; + __IM uint32_t DEVID; /*!< Offset: 0xFC8 (R/ ) TPIU_DEVID */ + __IM uint32_t DEVTYPE; /*!< Offset: 0xFCC (R/ ) TPIU_DEVTYPE */ +} TPI_Type; + +/* TPI Asynchronous Clock Prescaler Register Definitions */ +#define TPI_ACPR_PRESCALER_Pos 0U /*!< TPI ACPR: PRESCALER Position */ +#define TPI_ACPR_PRESCALER_Msk (0x1FFFUL /*<< TPI_ACPR_PRESCALER_Pos*/) /*!< TPI ACPR: PRESCALER Mask */ + +/* TPI Selected Pin Protocol Register Definitions */ +#define TPI_SPPR_TXMODE_Pos 0U /*!< TPI SPPR: TXMODE Position */ +#define TPI_SPPR_TXMODE_Msk (0x3UL /*<< TPI_SPPR_TXMODE_Pos*/) /*!< TPI SPPR: TXMODE Mask */ + +/* TPI Formatter and Flush Status Register Definitions */ +#define TPI_FFSR_FtNonStop_Pos 3U /*!< TPI FFSR: FtNonStop Position */ +#define TPI_FFSR_FtNonStop_Msk (0x1UL << TPI_FFSR_FtNonStop_Pos) /*!< TPI FFSR: FtNonStop Mask */ + +#define TPI_FFSR_TCPresent_Pos 2U /*!< TPI FFSR: TCPresent Position */ +#define TPI_FFSR_TCPresent_Msk (0x1UL << TPI_FFSR_TCPresent_Pos) /*!< TPI FFSR: TCPresent Mask */ + +#define TPI_FFSR_FtStopped_Pos 1U /*!< TPI FFSR: FtStopped Position */ +#define TPI_FFSR_FtStopped_Msk (0x1UL << TPI_FFSR_FtStopped_Pos) /*!< TPI FFSR: FtStopped Mask */ + +#define TPI_FFSR_FlInProg_Pos 0U /*!< TPI FFSR: FlInProg Position */ +#define TPI_FFSR_FlInProg_Msk (0x1UL /*<< TPI_FFSR_FlInProg_Pos*/) /*!< TPI FFSR: FlInProg Mask */ + +/* TPI Formatter and Flush Control Register Definitions */ +#define TPI_FFCR_TrigIn_Pos 8U /*!< TPI FFCR: TrigIn Position */ +#define TPI_FFCR_TrigIn_Msk (0x1UL << TPI_FFCR_TrigIn_Pos) /*!< TPI FFCR: TrigIn Mask */ + +#define TPI_FFCR_EnFCont_Pos 1U /*!< TPI FFCR: EnFCont Position */ +#define TPI_FFCR_EnFCont_Msk (0x1UL << TPI_FFCR_EnFCont_Pos) /*!< TPI FFCR: EnFCont Mask */ + +/* TPI TRIGGER Register Definitions */ +#define TPI_TRIGGER_TRIGGER_Pos 0U /*!< TPI TRIGGER: TRIGGER Position */ +#define TPI_TRIGGER_TRIGGER_Msk (0x1UL /*<< TPI_TRIGGER_TRIGGER_Pos*/) /*!< TPI TRIGGER: TRIGGER Mask */ + +/* TPI Integration ETM Data Register Definitions (FIFO0) */ +#define TPI_FIFO0_ITM_ATVALID_Pos 29U /*!< TPI FIFO0: ITM_ATVALID Position */ +#define TPI_FIFO0_ITM_ATVALID_Msk (0x3UL << TPI_FIFO0_ITM_ATVALID_Pos) /*!< TPI FIFO0: ITM_ATVALID Mask */ + +#define TPI_FIFO0_ITM_bytecount_Pos 27U /*!< TPI FIFO0: ITM_bytecount Position */ +#define TPI_FIFO0_ITM_bytecount_Msk (0x3UL << TPI_FIFO0_ITM_bytecount_Pos) /*!< TPI FIFO0: ITM_bytecount Mask */ + +#define TPI_FIFO0_ETM_ATVALID_Pos 26U /*!< TPI FIFO0: ETM_ATVALID Position */ +#define TPI_FIFO0_ETM_ATVALID_Msk (0x3UL << TPI_FIFO0_ETM_ATVALID_Pos) /*!< TPI FIFO0: ETM_ATVALID Mask */ + +#define TPI_FIFO0_ETM_bytecount_Pos 24U /*!< TPI FIFO0: ETM_bytecount Position */ +#define TPI_FIFO0_ETM_bytecount_Msk (0x3UL << TPI_FIFO0_ETM_bytecount_Pos) /*!< TPI FIFO0: ETM_bytecount Mask */ + +#define TPI_FIFO0_ETM2_Pos 16U /*!< TPI FIFO0: ETM2 Position */ +#define TPI_FIFO0_ETM2_Msk (0xFFUL << TPI_FIFO0_ETM2_Pos) /*!< TPI FIFO0: ETM2 Mask */ + +#define TPI_FIFO0_ETM1_Pos 8U /*!< TPI FIFO0: ETM1 Position */ +#define TPI_FIFO0_ETM1_Msk (0xFFUL << TPI_FIFO0_ETM1_Pos) /*!< TPI FIFO0: ETM1 Mask */ + +#define TPI_FIFO0_ETM0_Pos 0U /*!< TPI FIFO0: ETM0 Position */ +#define TPI_FIFO0_ETM0_Msk (0xFFUL /*<< TPI_FIFO0_ETM0_Pos*/) /*!< TPI FIFO0: ETM0 Mask */ + +/* TPI ITATBCTR2 Register Definitions */ +#define TPI_ITATBCTR2_ATREADY_Pos 0U /*!< TPI ITATBCTR2: ATREADY Position */ +#define TPI_ITATBCTR2_ATREADY_Msk (0x1UL /*<< TPI_ITATBCTR2_ATREADY_Pos*/) /*!< TPI ITATBCTR2: ATREADY Mask */ + +/* TPI Integration ITM Data Register Definitions (FIFO1) */ +#define TPI_FIFO1_ITM_ATVALID_Pos 29U /*!< TPI FIFO1: ITM_ATVALID Position */ +#define TPI_FIFO1_ITM_ATVALID_Msk (0x3UL << TPI_FIFO1_ITM_ATVALID_Pos) /*!< TPI FIFO1: ITM_ATVALID Mask */ + +#define TPI_FIFO1_ITM_bytecount_Pos 27U /*!< TPI FIFO1: ITM_bytecount Position */ +#define TPI_FIFO1_ITM_bytecount_Msk (0x3UL << TPI_FIFO1_ITM_bytecount_Pos) /*!< TPI FIFO1: ITM_bytecount Mask */ + +#define TPI_FIFO1_ETM_ATVALID_Pos 26U /*!< TPI FIFO1: ETM_ATVALID Position */ +#define TPI_FIFO1_ETM_ATVALID_Msk (0x3UL << TPI_FIFO1_ETM_ATVALID_Pos) /*!< TPI FIFO1: ETM_ATVALID Mask */ + +#define TPI_FIFO1_ETM_bytecount_Pos 24U /*!< TPI FIFO1: ETM_bytecount Position */ +#define TPI_FIFO1_ETM_bytecount_Msk (0x3UL << TPI_FIFO1_ETM_bytecount_Pos) /*!< TPI FIFO1: ETM_bytecount Mask */ + +#define TPI_FIFO1_ITM2_Pos 16U /*!< TPI FIFO1: ITM2 Position */ +#define TPI_FIFO1_ITM2_Msk (0xFFUL << TPI_FIFO1_ITM2_Pos) /*!< TPI FIFO1: ITM2 Mask */ + +#define TPI_FIFO1_ITM1_Pos 8U /*!< TPI FIFO1: ITM1 Position */ +#define TPI_FIFO1_ITM1_Msk (0xFFUL << TPI_FIFO1_ITM1_Pos) /*!< TPI FIFO1: ITM1 Mask */ + +#define TPI_FIFO1_ITM0_Pos 0U /*!< TPI FIFO1: ITM0 Position */ +#define TPI_FIFO1_ITM0_Msk (0xFFUL /*<< TPI_FIFO1_ITM0_Pos*/) /*!< TPI FIFO1: ITM0 Mask */ + +/* TPI ITATBCTR0 Register Definitions */ +#define TPI_ITATBCTR0_ATREADY_Pos 0U /*!< TPI ITATBCTR0: ATREADY Position */ +#define TPI_ITATBCTR0_ATREADY_Msk (0x1UL /*<< TPI_ITATBCTR0_ATREADY_Pos*/) /*!< TPI ITATBCTR0: ATREADY Mask */ + +/* TPI Integration Mode Control Register Definitions */ +#define TPI_ITCTRL_Mode_Pos 0U /*!< TPI ITCTRL: Mode Position */ +#define TPI_ITCTRL_Mode_Msk (0x1UL /*<< TPI_ITCTRL_Mode_Pos*/) /*!< TPI ITCTRL: Mode Mask */ + +/* TPI DEVID Register Definitions */ +#define TPI_DEVID_NRZVALID_Pos 11U /*!< TPI DEVID: NRZVALID Position */ +#define TPI_DEVID_NRZVALID_Msk (0x1UL << TPI_DEVID_NRZVALID_Pos) /*!< TPI DEVID: NRZVALID Mask */ + +#define TPI_DEVID_MANCVALID_Pos 10U /*!< TPI DEVID: MANCVALID Position */ +#define TPI_DEVID_MANCVALID_Msk (0x1UL << TPI_DEVID_MANCVALID_Pos) /*!< TPI DEVID: MANCVALID Mask */ + +#define TPI_DEVID_PTINVALID_Pos 9U /*!< TPI DEVID: PTINVALID Position */ +#define TPI_DEVID_PTINVALID_Msk (0x1UL << TPI_DEVID_PTINVALID_Pos) /*!< TPI DEVID: PTINVALID Mask */ + +#define TPI_DEVID_MinBufSz_Pos 6U /*!< TPI DEVID: MinBufSz Position */ +#define TPI_DEVID_MinBufSz_Msk (0x7UL << TPI_DEVID_MinBufSz_Pos) /*!< TPI DEVID: MinBufSz Mask */ + +#define TPI_DEVID_AsynClkIn_Pos 5U /*!< TPI DEVID: AsynClkIn Position */ +#define TPI_DEVID_AsynClkIn_Msk (0x1UL << TPI_DEVID_AsynClkIn_Pos) /*!< TPI DEVID: AsynClkIn Mask */ + +#define TPI_DEVID_NrTraceInput_Pos 0U /*!< TPI DEVID: NrTraceInput Position */ +#define TPI_DEVID_NrTraceInput_Msk (0x1FUL /*<< TPI_DEVID_NrTraceInput_Pos*/) /*!< TPI DEVID: NrTraceInput Mask */ + +/* TPI DEVTYPE Register Definitions */ +#define TPI_DEVTYPE_MajorType_Pos 4U /*!< TPI DEVTYPE: MajorType Position */ +#define TPI_DEVTYPE_MajorType_Msk (0xFUL << TPI_DEVTYPE_MajorType_Pos) /*!< TPI DEVTYPE: MajorType Mask */ + +#define TPI_DEVTYPE_SubType_Pos 0U /*!< TPI DEVTYPE: SubType Position */ +#define TPI_DEVTYPE_SubType_Msk (0xFUL /*<< TPI_DEVTYPE_SubType_Pos*/) /*!< TPI DEVTYPE: SubType Mask */ + +/*@}*/ /* end of group CMSIS_TPI */ + + +#if (__MPU_PRESENT == 1U) +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_MPU Memory Protection Unit (MPU) + \brief Type definitions for the Memory Protection Unit (MPU) + @{ + */ + +/** + \brief Structure type to access the Memory Protection Unit (MPU). + */ +typedef struct +{ + __IM uint32_t TYPE; /*!< Offset: 0x000 (R/ ) MPU Type Register */ + __IOM uint32_t CTRL; /*!< Offset: 0x004 (R/W) MPU Control Register */ + __IOM uint32_t RNR; /*!< Offset: 0x008 (R/W) MPU Region RNRber Register */ + __IOM uint32_t RBAR; /*!< Offset: 0x00C (R/W) MPU Region Base Address Register */ + __IOM uint32_t RASR; /*!< Offset: 0x010 (R/W) MPU Region Attribute and Size Register */ + __IOM uint32_t RBAR_A1; /*!< Offset: 0x014 (R/W) MPU Alias 1 Region Base Address Register */ + __IOM uint32_t RASR_A1; /*!< Offset: 0x018 (R/W) MPU Alias 1 Region Attribute and Size Register */ + __IOM uint32_t RBAR_A2; /*!< Offset: 0x01C (R/W) MPU Alias 2 Region Base Address Register */ + __IOM uint32_t RASR_A2; /*!< Offset: 0x020 (R/W) MPU Alias 2 Region Attribute and Size Register */ + __IOM uint32_t RBAR_A3; /*!< Offset: 0x024 (R/W) MPU Alias 3 Region Base Address Register */ + __IOM uint32_t RASR_A3; /*!< Offset: 0x028 (R/W) MPU Alias 3 Region Attribute and Size Register */ +} MPU_Type; + +/* MPU Type Register Definitions */ +#define MPU_TYPE_IREGION_Pos 16U /*!< MPU TYPE: IREGION Position */ +#define MPU_TYPE_IREGION_Msk (0xFFUL << MPU_TYPE_IREGION_Pos) /*!< MPU TYPE: IREGION Mask */ + +#define MPU_TYPE_DREGION_Pos 8U /*!< MPU TYPE: DREGION Position */ +#define MPU_TYPE_DREGION_Msk (0xFFUL << MPU_TYPE_DREGION_Pos) /*!< MPU TYPE: DREGION Mask */ + +#define MPU_TYPE_SEPARATE_Pos 0U /*!< MPU TYPE: SEPARATE Position */ +#define MPU_TYPE_SEPARATE_Msk (1UL /*<< MPU_TYPE_SEPARATE_Pos*/) /*!< MPU TYPE: SEPARATE Mask */ + +/* MPU Control Register Definitions */ +#define MPU_CTRL_PRIVDEFENA_Pos 2U /*!< MPU CTRL: PRIVDEFENA Position */ +#define MPU_CTRL_PRIVDEFENA_Msk (1UL << MPU_CTRL_PRIVDEFENA_Pos) /*!< MPU CTRL: PRIVDEFENA Mask */ + +#define MPU_CTRL_HFNMIENA_Pos 1U /*!< MPU CTRL: HFNMIENA Position */ +#define MPU_CTRL_HFNMIENA_Msk (1UL << MPU_CTRL_HFNMIENA_Pos) /*!< MPU CTRL: HFNMIENA Mask */ + +#define MPU_CTRL_ENABLE_Pos 0U /*!< MPU CTRL: ENABLE Position */ +#define MPU_CTRL_ENABLE_Msk (1UL /*<< MPU_CTRL_ENABLE_Pos*/) /*!< MPU CTRL: ENABLE Mask */ + +/* MPU Region Number Register Definitions */ +#define MPU_RNR_REGION_Pos 0U /*!< MPU RNR: REGION Position */ +#define MPU_RNR_REGION_Msk (0xFFUL /*<< MPU_RNR_REGION_Pos*/) /*!< MPU RNR: REGION Mask */ + +/* MPU Region Base Address Register Definitions */ +#define MPU_RBAR_ADDR_Pos 5U /*!< MPU RBAR: ADDR Position */ +#define MPU_RBAR_ADDR_Msk (0x7FFFFFFUL << MPU_RBAR_ADDR_Pos) /*!< MPU RBAR: ADDR Mask */ + +#define MPU_RBAR_VALID_Pos 4U /*!< MPU RBAR: VALID Position */ +#define MPU_RBAR_VALID_Msk (1UL << MPU_RBAR_VALID_Pos) /*!< MPU RBAR: VALID Mask */ + +#define MPU_RBAR_REGION_Pos 0U /*!< MPU RBAR: REGION Position */ +#define MPU_RBAR_REGION_Msk (0xFUL /*<< MPU_RBAR_REGION_Pos*/) /*!< MPU RBAR: REGION Mask */ + +/* MPU Region Attribute and Size Register Definitions */ +#define MPU_RASR_ATTRS_Pos 16U /*!< MPU RASR: MPU Region Attribute field Position */ +#define MPU_RASR_ATTRS_Msk (0xFFFFUL << MPU_RASR_ATTRS_Pos) /*!< MPU RASR: MPU Region Attribute field Mask */ + +#define MPU_RASR_XN_Pos 28U /*!< MPU RASR: ATTRS.XN Position */ +#define MPU_RASR_XN_Msk (1UL << MPU_RASR_XN_Pos) /*!< MPU RASR: ATTRS.XN Mask */ + +#define MPU_RASR_AP_Pos 24U /*!< MPU RASR: ATTRS.AP Position */ +#define MPU_RASR_AP_Msk (0x7UL << MPU_RASR_AP_Pos) /*!< MPU RASR: ATTRS.AP Mask */ + +#define MPU_RASR_TEX_Pos 19U /*!< MPU RASR: ATTRS.TEX Position */ +#define MPU_RASR_TEX_Msk (0x7UL << MPU_RASR_TEX_Pos) /*!< MPU RASR: ATTRS.TEX Mask */ + +#define MPU_RASR_S_Pos 18U /*!< MPU RASR: ATTRS.S Position */ +#define MPU_RASR_S_Msk (1UL << MPU_RASR_S_Pos) /*!< MPU RASR: ATTRS.S Mask */ + +#define MPU_RASR_C_Pos 17U /*!< MPU RASR: ATTRS.C Position */ +#define MPU_RASR_C_Msk (1UL << MPU_RASR_C_Pos) /*!< MPU RASR: ATTRS.C Mask */ + +#define MPU_RASR_B_Pos 16U /*!< MPU RASR: ATTRS.B Position */ +#define MPU_RASR_B_Msk (1UL << MPU_RASR_B_Pos) /*!< MPU RASR: ATTRS.B Mask */ + +#define MPU_RASR_SRD_Pos 8U /*!< MPU RASR: Sub-Region Disable Position */ +#define MPU_RASR_SRD_Msk (0xFFUL << MPU_RASR_SRD_Pos) /*!< MPU RASR: Sub-Region Disable Mask */ + +#define MPU_RASR_SIZE_Pos 1U /*!< MPU RASR: Region Size Field Position */ +#define MPU_RASR_SIZE_Msk (0x1FUL << MPU_RASR_SIZE_Pos) /*!< MPU RASR: Region Size Field Mask */ + +#define MPU_RASR_ENABLE_Pos 0U /*!< MPU RASR: Region enable bit Position */ +#define MPU_RASR_ENABLE_Msk (1UL /*<< MPU_RASR_ENABLE_Pos*/) /*!< MPU RASR: Region enable bit Disable Mask */ + +/*@} end of group CMSIS_MPU */ +#endif + + +#if (__FPU_PRESENT == 1U) +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_FPU Floating Point Unit (FPU) + \brief Type definitions for the Floating Point Unit (FPU) + @{ + */ + +/** + \brief Structure type to access the Floating Point Unit (FPU). + */ +typedef struct +{ + uint32_t RESERVED0[1U]; + __IOM uint32_t FPCCR; /*!< Offset: 0x004 (R/W) Floating-Point Context Control Register */ + __IOM uint32_t FPCAR; /*!< Offset: 0x008 (R/W) Floating-Point Context Address Register */ + __IOM uint32_t FPDSCR; /*!< Offset: 0x00C (R/W) Floating-Point Default Status Control Register */ + __IM uint32_t MVFR0; /*!< Offset: 0x010 (R/ ) Media and FP Feature Register 0 */ + __IM uint32_t MVFR1; /*!< Offset: 0x014 (R/ ) Media and FP Feature Register 1 */ + __IM uint32_t MVFR2; /*!< Offset: 0x018 (R/ ) Media and FP Feature Register 2 */ +} FPU_Type; + +/* Floating-Point Context Control Register Definitions */ +#define FPU_FPCCR_ASPEN_Pos 31U /*!< FPCCR: ASPEN bit Position */ +#define FPU_FPCCR_ASPEN_Msk (1UL << FPU_FPCCR_ASPEN_Pos) /*!< FPCCR: ASPEN bit Mask */ + +#define FPU_FPCCR_LSPEN_Pos 30U /*!< FPCCR: LSPEN Position */ +#define FPU_FPCCR_LSPEN_Msk (1UL << FPU_FPCCR_LSPEN_Pos) /*!< FPCCR: LSPEN bit Mask */ + +#define FPU_FPCCR_MONRDY_Pos 8U /*!< FPCCR: MONRDY Position */ +#define FPU_FPCCR_MONRDY_Msk (1UL << FPU_FPCCR_MONRDY_Pos) /*!< FPCCR: MONRDY bit Mask */ + +#define FPU_FPCCR_BFRDY_Pos 6U /*!< FPCCR: BFRDY Position */ +#define FPU_FPCCR_BFRDY_Msk (1UL << FPU_FPCCR_BFRDY_Pos) /*!< FPCCR: BFRDY bit Mask */ + +#define FPU_FPCCR_MMRDY_Pos 5U /*!< FPCCR: MMRDY Position */ +#define FPU_FPCCR_MMRDY_Msk (1UL << FPU_FPCCR_MMRDY_Pos) /*!< FPCCR: MMRDY bit Mask */ + +#define FPU_FPCCR_HFRDY_Pos 4U /*!< FPCCR: HFRDY Position */ +#define FPU_FPCCR_HFRDY_Msk (1UL << FPU_FPCCR_HFRDY_Pos) /*!< FPCCR: HFRDY bit Mask */ + +#define FPU_FPCCR_THREAD_Pos 3U /*!< FPCCR: processor mode bit Position */ +#define FPU_FPCCR_THREAD_Msk (1UL << FPU_FPCCR_THREAD_Pos) /*!< FPCCR: processor mode active bit Mask */ + +#define FPU_FPCCR_USER_Pos 1U /*!< FPCCR: privilege level bit Position */ +#define FPU_FPCCR_USER_Msk (1UL << FPU_FPCCR_USER_Pos) /*!< FPCCR: privilege level bit Mask */ + +#define FPU_FPCCR_LSPACT_Pos 0U /*!< FPCCR: Lazy state preservation active bit Position */ +#define FPU_FPCCR_LSPACT_Msk (1UL /*<< FPU_FPCCR_LSPACT_Pos*/) /*!< FPCCR: Lazy state preservation active bit Mask */ + +/* Floating-Point Context Address Register Definitions */ +#define FPU_FPCAR_ADDRESS_Pos 3U /*!< FPCAR: ADDRESS bit Position */ +#define FPU_FPCAR_ADDRESS_Msk (0x1FFFFFFFUL << FPU_FPCAR_ADDRESS_Pos) /*!< FPCAR: ADDRESS bit Mask */ + +/* Floating-Point Default Status Control Register Definitions */ +#define FPU_FPDSCR_AHP_Pos 26U /*!< FPDSCR: AHP bit Position */ +#define FPU_FPDSCR_AHP_Msk (1UL << FPU_FPDSCR_AHP_Pos) /*!< FPDSCR: AHP bit Mask */ + +#define FPU_FPDSCR_DN_Pos 25U /*!< FPDSCR: DN bit Position */ +#define FPU_FPDSCR_DN_Msk (1UL << FPU_FPDSCR_DN_Pos) /*!< FPDSCR: DN bit Mask */ + +#define FPU_FPDSCR_FZ_Pos 24U /*!< FPDSCR: FZ bit Position */ +#define FPU_FPDSCR_FZ_Msk (1UL << FPU_FPDSCR_FZ_Pos) /*!< FPDSCR: FZ bit Mask */ + +#define FPU_FPDSCR_RMode_Pos 22U /*!< FPDSCR: RMode bit Position */ +#define FPU_FPDSCR_RMode_Msk (3UL << FPU_FPDSCR_RMode_Pos) /*!< FPDSCR: RMode bit Mask */ + +/* Media and FP Feature Register 0 Definitions */ +#define FPU_MVFR0_FP_rounding_modes_Pos 28U /*!< MVFR0: FP rounding modes bits Position */ +#define FPU_MVFR0_FP_rounding_modes_Msk (0xFUL << FPU_MVFR0_FP_rounding_modes_Pos) /*!< MVFR0: FP rounding modes bits Mask */ + +#define FPU_MVFR0_Short_vectors_Pos 24U /*!< MVFR0: Short vectors bits Position */ +#define FPU_MVFR0_Short_vectors_Msk (0xFUL << FPU_MVFR0_Short_vectors_Pos) /*!< MVFR0: Short vectors bits Mask */ + +#define FPU_MVFR0_Square_root_Pos 20U /*!< MVFR0: Square root bits Position */ +#define FPU_MVFR0_Square_root_Msk (0xFUL << FPU_MVFR0_Square_root_Pos) /*!< MVFR0: Square root bits Mask */ + +#define FPU_MVFR0_Divide_Pos 16U /*!< MVFR0: Divide bits Position */ +#define FPU_MVFR0_Divide_Msk (0xFUL << FPU_MVFR0_Divide_Pos) /*!< MVFR0: Divide bits Mask */ + +#define FPU_MVFR0_FP_excep_trapping_Pos 12U /*!< MVFR0: FP exception trapping bits Position */ +#define FPU_MVFR0_FP_excep_trapping_Msk (0xFUL << FPU_MVFR0_FP_excep_trapping_Pos) /*!< MVFR0: FP exception trapping bits Mask */ + +#define FPU_MVFR0_Double_precision_Pos 8U /*!< MVFR0: Double-precision bits Position */ +#define FPU_MVFR0_Double_precision_Msk (0xFUL << FPU_MVFR0_Double_precision_Pos) /*!< MVFR0: Double-precision bits Mask */ + +#define FPU_MVFR0_Single_precision_Pos 4U /*!< MVFR0: Single-precision bits Position */ +#define FPU_MVFR0_Single_precision_Msk (0xFUL << FPU_MVFR0_Single_precision_Pos) /*!< MVFR0: Single-precision bits Mask */ + +#define FPU_MVFR0_A_SIMD_registers_Pos 0U /*!< MVFR0: A_SIMD registers bits Position */ +#define FPU_MVFR0_A_SIMD_registers_Msk (0xFUL /*<< FPU_MVFR0_A_SIMD_registers_Pos*/) /*!< MVFR0: A_SIMD registers bits Mask */ + +/* Media and FP Feature Register 1 Definitions */ +#define FPU_MVFR1_FP_fused_MAC_Pos 28U /*!< MVFR1: FP fused MAC bits Position */ +#define FPU_MVFR1_FP_fused_MAC_Msk (0xFUL << FPU_MVFR1_FP_fused_MAC_Pos) /*!< MVFR1: FP fused MAC bits Mask */ + +#define FPU_MVFR1_FP_HPFP_Pos 24U /*!< MVFR1: FP HPFP bits Position */ +#define FPU_MVFR1_FP_HPFP_Msk (0xFUL << FPU_MVFR1_FP_HPFP_Pos) /*!< MVFR1: FP HPFP bits Mask */ + +#define FPU_MVFR1_D_NaN_mode_Pos 4U /*!< MVFR1: D_NaN mode bits Position */ +#define FPU_MVFR1_D_NaN_mode_Msk (0xFUL << FPU_MVFR1_D_NaN_mode_Pos) /*!< MVFR1: D_NaN mode bits Mask */ + +#define FPU_MVFR1_FtZ_mode_Pos 0U /*!< MVFR1: FtZ mode bits Position */ +#define FPU_MVFR1_FtZ_mode_Msk (0xFUL /*<< FPU_MVFR1_FtZ_mode_Pos*/) /*!< MVFR1: FtZ mode bits Mask */ + +/* Media and FP Feature Register 2 Definitions */ + +/*@} end of group CMSIS_FPU */ +#endif + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_CoreDebug Core Debug Registers (CoreDebug) + \brief Type definitions for the Core Debug Registers + @{ + */ + +/** + \brief Structure type to access the Core Debug Register (CoreDebug). + */ +typedef struct +{ + __IOM uint32_t DHCSR; /*!< Offset: 0x000 (R/W) Debug Halting Control and Status Register */ + __OM uint32_t DCRSR; /*!< Offset: 0x004 ( /W) Debug Core Register Selector Register */ + __IOM uint32_t DCRDR; /*!< Offset: 0x008 (R/W) Debug Core Register Data Register */ + __IOM uint32_t DEMCR; /*!< Offset: 0x00C (R/W) Debug Exception and Monitor Control Register */ +} CoreDebug_Type; + +/* Debug Halting Control and Status Register Definitions */ +#define CoreDebug_DHCSR_DBGKEY_Pos 16U /*!< CoreDebug DHCSR: DBGKEY Position */ +#define CoreDebug_DHCSR_DBGKEY_Msk (0xFFFFUL << CoreDebug_DHCSR_DBGKEY_Pos) /*!< CoreDebug DHCSR: DBGKEY Mask */ + +#define CoreDebug_DHCSR_S_RESET_ST_Pos 25U /*!< CoreDebug DHCSR: S_RESET_ST Position */ +#define CoreDebug_DHCSR_S_RESET_ST_Msk (1UL << CoreDebug_DHCSR_S_RESET_ST_Pos) /*!< CoreDebug DHCSR: S_RESET_ST Mask */ + +#define CoreDebug_DHCSR_S_RETIRE_ST_Pos 24U /*!< CoreDebug DHCSR: S_RETIRE_ST Position */ +#define CoreDebug_DHCSR_S_RETIRE_ST_Msk (1UL << CoreDebug_DHCSR_S_RETIRE_ST_Pos) /*!< CoreDebug DHCSR: S_RETIRE_ST Mask */ + +#define CoreDebug_DHCSR_S_LOCKUP_Pos 19U /*!< CoreDebug DHCSR: S_LOCKUP Position */ +#define CoreDebug_DHCSR_S_LOCKUP_Msk (1UL << CoreDebug_DHCSR_S_LOCKUP_Pos) /*!< CoreDebug DHCSR: S_LOCKUP Mask */ + +#define CoreDebug_DHCSR_S_SLEEP_Pos 18U /*!< CoreDebug DHCSR: S_SLEEP Position */ +#define CoreDebug_DHCSR_S_SLEEP_Msk (1UL << CoreDebug_DHCSR_S_SLEEP_Pos) /*!< CoreDebug DHCSR: S_SLEEP Mask */ + +#define CoreDebug_DHCSR_S_HALT_Pos 17U /*!< CoreDebug DHCSR: S_HALT Position */ +#define CoreDebug_DHCSR_S_HALT_Msk (1UL << CoreDebug_DHCSR_S_HALT_Pos) /*!< CoreDebug DHCSR: S_HALT Mask */ + +#define CoreDebug_DHCSR_S_REGRDY_Pos 16U /*!< CoreDebug DHCSR: S_REGRDY Position */ +#define CoreDebug_DHCSR_S_REGRDY_Msk (1UL << CoreDebug_DHCSR_S_REGRDY_Pos) /*!< CoreDebug DHCSR: S_REGRDY Mask */ + +#define CoreDebug_DHCSR_C_SNAPSTALL_Pos 5U /*!< CoreDebug DHCSR: C_SNAPSTALL Position */ +#define CoreDebug_DHCSR_C_SNAPSTALL_Msk (1UL << CoreDebug_DHCSR_C_SNAPSTALL_Pos) /*!< CoreDebug DHCSR: C_SNAPSTALL Mask */ + +#define CoreDebug_DHCSR_C_MASKINTS_Pos 3U /*!< CoreDebug DHCSR: C_MASKINTS Position */ +#define CoreDebug_DHCSR_C_MASKINTS_Msk (1UL << CoreDebug_DHCSR_C_MASKINTS_Pos) /*!< CoreDebug DHCSR: C_MASKINTS Mask */ + +#define CoreDebug_DHCSR_C_STEP_Pos 2U /*!< CoreDebug DHCSR: C_STEP Position */ +#define CoreDebug_DHCSR_C_STEP_Msk (1UL << CoreDebug_DHCSR_C_STEP_Pos) /*!< CoreDebug DHCSR: C_STEP Mask */ + +#define CoreDebug_DHCSR_C_HALT_Pos 1U /*!< CoreDebug DHCSR: C_HALT Position */ +#define CoreDebug_DHCSR_C_HALT_Msk (1UL << CoreDebug_DHCSR_C_HALT_Pos) /*!< CoreDebug DHCSR: C_HALT Mask */ + +#define CoreDebug_DHCSR_C_DEBUGEN_Pos 0U /*!< CoreDebug DHCSR: C_DEBUGEN Position */ +#define CoreDebug_DHCSR_C_DEBUGEN_Msk (1UL /*<< CoreDebug_DHCSR_C_DEBUGEN_Pos*/) /*!< CoreDebug DHCSR: C_DEBUGEN Mask */ + +/* Debug Core Register Selector Register Definitions */ +#define CoreDebug_DCRSR_REGWnR_Pos 16U /*!< CoreDebug DCRSR: REGWnR Position */ +#define CoreDebug_DCRSR_REGWnR_Msk (1UL << CoreDebug_DCRSR_REGWnR_Pos) /*!< CoreDebug DCRSR: REGWnR Mask */ + +#define CoreDebug_DCRSR_REGSEL_Pos 0U /*!< CoreDebug DCRSR: REGSEL Position */ +#define CoreDebug_DCRSR_REGSEL_Msk (0x1FUL /*<< CoreDebug_DCRSR_REGSEL_Pos*/) /*!< CoreDebug DCRSR: REGSEL Mask */ + +/* Debug Exception and Monitor Control Register Definitions */ +#define CoreDebug_DEMCR_TRCENA_Pos 24U /*!< CoreDebug DEMCR: TRCENA Position */ +#define CoreDebug_DEMCR_TRCENA_Msk (1UL << CoreDebug_DEMCR_TRCENA_Pos) /*!< CoreDebug DEMCR: TRCENA Mask */ + +#define CoreDebug_DEMCR_MON_REQ_Pos 19U /*!< CoreDebug DEMCR: MON_REQ Position */ +#define CoreDebug_DEMCR_MON_REQ_Msk (1UL << CoreDebug_DEMCR_MON_REQ_Pos) /*!< CoreDebug DEMCR: MON_REQ Mask */ + +#define CoreDebug_DEMCR_MON_STEP_Pos 18U /*!< CoreDebug DEMCR: MON_STEP Position */ +#define CoreDebug_DEMCR_MON_STEP_Msk (1UL << CoreDebug_DEMCR_MON_STEP_Pos) /*!< CoreDebug DEMCR: MON_STEP Mask */ + +#define CoreDebug_DEMCR_MON_PEND_Pos 17U /*!< CoreDebug DEMCR: MON_PEND Position */ +#define CoreDebug_DEMCR_MON_PEND_Msk (1UL << CoreDebug_DEMCR_MON_PEND_Pos) /*!< CoreDebug DEMCR: MON_PEND Mask */ + +#define CoreDebug_DEMCR_MON_EN_Pos 16U /*!< CoreDebug DEMCR: MON_EN Position */ +#define CoreDebug_DEMCR_MON_EN_Msk (1UL << CoreDebug_DEMCR_MON_EN_Pos) /*!< CoreDebug DEMCR: MON_EN Mask */ + +#define CoreDebug_DEMCR_VC_HARDERR_Pos 10U /*!< CoreDebug DEMCR: VC_HARDERR Position */ +#define CoreDebug_DEMCR_VC_HARDERR_Msk (1UL << CoreDebug_DEMCR_VC_HARDERR_Pos) /*!< CoreDebug DEMCR: VC_HARDERR Mask */ + +#define CoreDebug_DEMCR_VC_INTERR_Pos 9U /*!< CoreDebug DEMCR: VC_INTERR Position */ +#define CoreDebug_DEMCR_VC_INTERR_Msk (1UL << CoreDebug_DEMCR_VC_INTERR_Pos) /*!< CoreDebug DEMCR: VC_INTERR Mask */ + +#define CoreDebug_DEMCR_VC_BUSERR_Pos 8U /*!< CoreDebug DEMCR: VC_BUSERR Position */ +#define CoreDebug_DEMCR_VC_BUSERR_Msk (1UL << CoreDebug_DEMCR_VC_BUSERR_Pos) /*!< CoreDebug DEMCR: VC_BUSERR Mask */ + +#define CoreDebug_DEMCR_VC_STATERR_Pos 7U /*!< CoreDebug DEMCR: VC_STATERR Position */ +#define CoreDebug_DEMCR_VC_STATERR_Msk (1UL << CoreDebug_DEMCR_VC_STATERR_Pos) /*!< CoreDebug DEMCR: VC_STATERR Mask */ + +#define CoreDebug_DEMCR_VC_CHKERR_Pos 6U /*!< CoreDebug DEMCR: VC_CHKERR Position */ +#define CoreDebug_DEMCR_VC_CHKERR_Msk (1UL << CoreDebug_DEMCR_VC_CHKERR_Pos) /*!< CoreDebug DEMCR: VC_CHKERR Mask */ + +#define CoreDebug_DEMCR_VC_NOCPERR_Pos 5U /*!< CoreDebug DEMCR: VC_NOCPERR Position */ +#define CoreDebug_DEMCR_VC_NOCPERR_Msk (1UL << CoreDebug_DEMCR_VC_NOCPERR_Pos) /*!< CoreDebug DEMCR: VC_NOCPERR Mask */ + +#define CoreDebug_DEMCR_VC_MMERR_Pos 4U /*!< CoreDebug DEMCR: VC_MMERR Position */ +#define CoreDebug_DEMCR_VC_MMERR_Msk (1UL << CoreDebug_DEMCR_VC_MMERR_Pos) /*!< CoreDebug DEMCR: VC_MMERR Mask */ + +#define CoreDebug_DEMCR_VC_CORERESET_Pos 0U /*!< CoreDebug DEMCR: VC_CORERESET Position */ +#define CoreDebug_DEMCR_VC_CORERESET_Msk (1UL /*<< CoreDebug_DEMCR_VC_CORERESET_Pos*/) /*!< CoreDebug DEMCR: VC_CORERESET Mask */ + +/*@} end of group CMSIS_CoreDebug */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_core_bitfield Core register bit field macros + \brief Macros for use with bit field definitions (xxx_Pos, xxx_Msk). + @{ + */ + +/** + \brief Mask and shift a bit field value for use in a register bit range. + \param[in] field Name of the register bit field. + \param[in] value Value of the bit field. + \return Masked and shifted value. +*/ +#define _VAL2FLD(field, value) ((value << field ## _Pos) & field ## _Msk) + +/** + \brief Mask and shift a register value to extract a bit filed value. + \param[in] field Name of the register bit field. + \param[in] value Value of register. + \return Masked and shifted bit field value. +*/ +#define _FLD2VAL(field, value) ((value & field ## _Msk) >> field ## _Pos) + +/*@} end of group CMSIS_core_bitfield */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_core_base Core Definitions + \brief Definitions for base addresses, unions, and structures. + @{ + */ + +/* Memory mapping of Cortex-M4 Hardware */ +#define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */ +#define ITM_BASE (0xE0000000UL) /*!< ITM Base Address */ +#define DWT_BASE (0xE0001000UL) /*!< DWT Base Address */ +#define TPI_BASE (0xE0040000UL) /*!< TPI Base Address */ +#define CoreDebug_BASE (0xE000EDF0UL) /*!< Core Debug Base Address */ +#define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */ +#define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */ +#define SCB_BASE (SCS_BASE + 0x0D00UL) /*!< System Control Block Base Address */ + +#define SCnSCB ((SCnSCB_Type *) SCS_BASE ) /*!< System control Register not in SCB */ +#define SCB ((SCB_Type *) SCB_BASE ) /*!< SCB configuration struct */ +#define SysTick ((SysTick_Type *) SysTick_BASE ) /*!< SysTick configuration struct */ +#define NVIC ((NVIC_Type *) NVIC_BASE ) /*!< NVIC configuration struct */ +#define ITM ((ITM_Type *) ITM_BASE ) /*!< ITM configuration struct */ +#define DWT ((DWT_Type *) DWT_BASE ) /*!< DWT configuration struct */ +#define TPI ((TPI_Type *) TPI_BASE ) /*!< TPI configuration struct */ +#define CoreDebug ((CoreDebug_Type *) CoreDebug_BASE) /*!< Core Debug configuration struct */ + +#if (__MPU_PRESENT == 1U) +#define MPU_BASE (SCS_BASE + 0x0D90UL) /*!< Memory Protection Unit */ +#define MPU ((MPU_Type *) MPU_BASE ) /*!< Memory Protection Unit */ +#endif + +#if (__FPU_PRESENT == 1U) +#define FPU_BASE (SCS_BASE + 0x0F30UL) /*!< Floating Point Unit */ +#define FPU ((FPU_Type *) FPU_BASE ) /*!< Floating Point Unit */ +#endif + +/*@} */ + + + +/******************************************************************************* + * Hardware Abstraction Layer + Core Function Interface contains: + - Core NVIC Functions + - Core SysTick Functions + - Core Debug Functions + - Core Register Access Functions + ******************************************************************************/ +/** + \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference +*/ + + + +/* ########################## NVIC functions #################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_NVICFunctions NVIC Functions + \brief Functions that manage interrupts and exceptions via the NVIC. + @{ + */ + +/** + \brief Set Priority Grouping + \details Sets the priority grouping field using the required unlock sequence. + The parameter PriorityGroup is assigned to the field SCB->AIRCR [10:8] PRIGROUP field. + Only values from 0..7 are used. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set. + \param [in] PriorityGroup Priority grouping field. + */ +__STATIC_INLINE void NVIC_SetPriorityGrouping(uint32_t PriorityGroup) +{ + uint32_t reg_value; + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + + reg_value = SCB->AIRCR; /* read old register configuration */ + reg_value &= ~((uint32_t)(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk)); /* clear bits to change */ + reg_value = (reg_value | + ((uint32_t)0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | + (PriorityGroupTmp << 8U)); /* Insert write key and priorty group */ + SCB->AIRCR = reg_value; +} + + +/** + \brief Get Priority Grouping + \details Reads the priority grouping field from the NVIC Interrupt Controller. + \return Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field). + */ +__STATIC_INLINE uint32_t NVIC_GetPriorityGrouping(void) +{ + return ((uint32_t)((SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos)); +} + + +/** + \brief Enable External Interrupt + \details Enables a device-specific interrupt in the NVIC interrupt controller. + \param [in] IRQn External interrupt number. Value cannot be negative. + */ +__STATIC_INLINE void NVIC_EnableIRQ(IRQn_Type IRQn) +{ + NVIC->ISER[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL)); +} + + +/** + \brief Disable External Interrupt + \details Disables a device-specific interrupt in the NVIC interrupt controller. + \param [in] IRQn External interrupt number. Value cannot be negative. + */ +__STATIC_INLINE void NVIC_DisableIRQ(IRQn_Type IRQn) +{ + NVIC->ICER[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL)); +} + + +/** + \brief Get Pending Interrupt + \details Reads the pending register in the NVIC and returns the pending bit for the specified interrupt. + \param [in] IRQn Interrupt number. + \return 0 Interrupt status is not pending. + \return 1 Interrupt status is pending. + */ +__STATIC_INLINE uint32_t NVIC_GetPendingIRQ(IRQn_Type IRQn) +{ + return ((uint32_t)(((NVIC->ISPR[(((uint32_t)(int32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); +} + + +/** + \brief Set Pending Interrupt + \details Sets the pending bit of an external interrupt. + \param [in] IRQn Interrupt number. Value cannot be negative. + */ +__STATIC_INLINE void NVIC_SetPendingIRQ(IRQn_Type IRQn) +{ + NVIC->ISPR[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL)); +} + + +/** + \brief Clear Pending Interrupt + \details Clears the pending bit of an external interrupt. + \param [in] IRQn External interrupt number. Value cannot be negative. + */ +__STATIC_INLINE void NVIC_ClearPendingIRQ(IRQn_Type IRQn) +{ + NVIC->ICPR[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL)); +} + + +/** + \brief Get Active Interrupt + \details Reads the active register in NVIC and returns the active bit. + \param [in] IRQn Interrupt number. + \return 0 Interrupt status is not active. + \return 1 Interrupt status is active. + */ +__STATIC_INLINE uint32_t NVIC_GetActive(IRQn_Type IRQn) +{ + return ((uint32_t)(((NVIC->IABR[(((uint32_t)(int32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); +} + + +/** + \brief Set Interrupt Priority + \details Sets the priority of an interrupt. + \note The priority cannot be set for every core interrupt. + \param [in] IRQn Interrupt number. + \param [in] priority Priority to set. + */ +__STATIC_INLINE void NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority) +{ + if ((int32_t)(IRQn) < 0) + { + SCB->SHPR[(((uint32_t)(int32_t)IRQn) & 0xFUL) - 4UL] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); + } + else + { + NVIC->IP[((uint32_t)(int32_t)IRQn)] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); + } +} + + +/** + \brief Get Interrupt Priority + \details Reads the priority of an interrupt. + The interrupt number can be positive to specify an external (device specific) interrupt, + or negative to specify an internal (core) interrupt. + \param [in] IRQn Interrupt number. + \return Interrupt Priority. + Value is aligned automatically to the implemented priority bits of the microcontroller. + */ +__STATIC_INLINE uint32_t NVIC_GetPriority(IRQn_Type IRQn) +{ + + if ((int32_t)(IRQn) < 0) + { + return (((uint32_t)SCB->SHPR[(((uint32_t)(int32_t)IRQn) & 0xFUL) - 4UL] >> (8U - __NVIC_PRIO_BITS))); + } + else + { + return (((uint32_t)NVIC->IP[((uint32_t)(int32_t)IRQn)] >> (8U - __NVIC_PRIO_BITS))); + } +} + + +/** + \brief Encode Priority + \details Encodes the priority for an interrupt with the given priority group, + preemptive priority value, and subpriority value. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set. + \param [in] PriorityGroup Used priority group. + \param [in] PreemptPriority Preemptive priority value (starting from 0). + \param [in] SubPriority Subpriority value (starting from 0). + \return Encoded priority. Value can be used in the function \ref NVIC_SetPriority(). + */ +__STATIC_INLINE uint32_t NVIC_EncodePriority(uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority) +{ + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + uint32_t PreemptPriorityBits; + uint32_t SubPriorityBits; + + PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp); + SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS)); + + return ( + ((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) | + ((SubPriority & (uint32_t)((1UL << (SubPriorityBits)) - 1UL))) + ); +} + + +/** + \brief Decode Priority + \details Decodes an interrupt priority value with a given priority group to + preemptive priority value and subpriority value. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS) the smallest possible priority group is set. + \param [in] Priority Priority value, which can be retrieved with the function \ref NVIC_GetPriority(). + \param [in] PriorityGroup Used priority group. + \param [out] pPreemptPriority Preemptive priority value (starting from 0). + \param [out] pSubPriority Subpriority value (starting from 0). + */ +__STATIC_INLINE void NVIC_DecodePriority(uint32_t Priority, uint32_t PriorityGroup, uint32_t *const pPreemptPriority, uint32_t *const pSubPriority) +{ + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + uint32_t PreemptPriorityBits; + uint32_t SubPriorityBits; + + PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp); + SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS)); + + *pPreemptPriority = (Priority >> SubPriorityBits) & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL); + *pSubPriority = (Priority) & (uint32_t)((1UL << (SubPriorityBits)) - 1UL); +} + + +/** + \brief System Reset + \details Initiates a system reset request to reset the MCU. + */ +__STATIC_INLINE void NVIC_SystemReset(void) +{ + __DSB(); /* Ensure all outstanding memory accesses included + buffered write are completed before reset */ + SCB->AIRCR = (uint32_t)((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | + (SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) | + SCB_AIRCR_SYSRESETREQ_Msk); /* Keep priority group unchanged */ + __DSB(); /* Ensure completion of memory access */ + + for (;;) /* wait until reset */ + { + __NOP(); + } +} + +/*@} end of CMSIS_Core_NVICFunctions */ + + +/* ########################## FPU functions #################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_FpuFunctions FPU Functions + \brief Function that provides FPU type. + @{ + */ + +/** + \brief get FPU type + \details returns the FPU type + \returns + - \b 0: No FPU + - \b 1: Single precision FPU + - \b 2: Double + Single precision FPU + */ +__STATIC_INLINE uint32_t SCB_GetFPUType(void) +{ + uint32_t mvfr0; + + mvfr0 = SCB->MVFR0; + if ((mvfr0 & 0x00000FF0UL) == 0x220UL) + { + return 2UL; /* Double + Single precision FPU */ + } + else if ((mvfr0 & 0x00000FF0UL) == 0x020UL) + { + return 1UL; /* Single precision FPU */ + } + else + { + return 0UL; /* No FPU */ + } +} + + +/*@} end of CMSIS_Core_FpuFunctions */ + + + +/* ########################## Cache functions #################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_CacheFunctions Cache Functions + \brief Functions that configure Instruction and Data cache. + @{ + */ + +/* Cache Size ID Register Macros */ +#define CCSIDR_WAYS(x) (((x) & SCB_CCSIDR_ASSOCIATIVITY_Msk) >> SCB_CCSIDR_ASSOCIATIVITY_Pos) +#define CCSIDR_SETS(x) (((x) & SCB_CCSIDR_NUMSETS_Msk ) >> SCB_CCSIDR_NUMSETS_Pos ) + + +/** + \brief Enable I-Cache + \details Turns on I-Cache + */ +__STATIC_INLINE void SCB_EnableICache(void) +{ +#if (__ICACHE_PRESENT == 1U) + __DSB(); + __ISB(); + SCB->ICIALLU = 0UL; /* invalidate I-Cache */ + SCB->CCR |= (uint32_t)SCB_CCR_IC_Msk; /* enable I-Cache */ + __DSB(); + __ISB(); +#endif +} + + +/** + \brief Disable I-Cache + \details Turns off I-Cache + */ +__STATIC_INLINE void SCB_DisableICache(void) +{ +#if (__ICACHE_PRESENT == 1U) + __DSB(); + __ISB(); + SCB->CCR &= ~(uint32_t)SCB_CCR_IC_Msk; /* disable I-Cache */ + SCB->ICIALLU = 0UL; /* invalidate I-Cache */ + __DSB(); + __ISB(); +#endif +} + + +/** + \brief Invalidate I-Cache + \details Invalidates I-Cache + */ +__STATIC_INLINE void SCB_InvalidateICache(void) +{ +#if (__ICACHE_PRESENT == 1U) + __DSB(); + __ISB(); + SCB->ICIALLU = 0UL; + __DSB(); + __ISB(); +#endif +} + + +/** + \brief Enable D-Cache + \details Turns on D-Cache + */ +__STATIC_INLINE void SCB_EnableDCache(void) +{ +#if (__DCACHE_PRESENT == 1U) + uint32_t ccsidr; + uint32_t sets; + uint32_t ways; + + SCB->CSSELR = (0U << 1U) | 0U; /* Level 1 data cache */ + __DSB(); + + ccsidr = SCB->CCSIDR; + + /* invalidate D-Cache */ + sets = (uint32_t)(CCSIDR_SETS(ccsidr)); + do + { + ways = (uint32_t)(CCSIDR_WAYS(ccsidr)); + do + { + SCB->DCISW = (((sets << SCB_DCISW_SET_Pos) & SCB_DCISW_SET_Msk) | + ((ways << SCB_DCISW_WAY_Pos) & SCB_DCISW_WAY_Msk)); +#if defined ( __CC_ARM ) + __schedule_barrier(); +#endif + } + while (ways--); + } + while (sets--); + __DSB(); + + SCB->CCR |= (uint32_t)SCB_CCR_DC_Msk; /* enable D-Cache */ + + __DSB(); + __ISB(); +#endif +} + + +/** + \brief Disable D-Cache + \details Turns off D-Cache + */ +__STATIC_INLINE void SCB_DisableDCache(void) +{ +#if (__DCACHE_PRESENT == 1U) + uint32_t ccsidr; + uint32_t sets; + uint32_t ways; + + SCB->CSSELR = (0U << 1U) | 0U; /* Level 1 data cache */ + __DSB(); + + ccsidr = SCB->CCSIDR; + + SCB->CCR &= ~(uint32_t)SCB_CCR_DC_Msk; /* disable D-Cache */ + + /* clean & invalidate D-Cache */ + sets = (uint32_t)(CCSIDR_SETS(ccsidr)); + do + { + ways = (uint32_t)(CCSIDR_WAYS(ccsidr)); + do + { + SCB->DCCISW = (((sets << SCB_DCCISW_SET_Pos) & SCB_DCCISW_SET_Msk) | + ((ways << SCB_DCCISW_WAY_Pos) & SCB_DCCISW_WAY_Msk)); +#if defined ( __CC_ARM ) + __schedule_barrier(); +#endif + } + while (ways--); + } + while (sets--); + + __DSB(); + __ISB(); +#endif +} + + +/** + \brief Invalidate D-Cache + \details Invalidates D-Cache + */ +__STATIC_INLINE void SCB_InvalidateDCache(void) +{ +#if (__DCACHE_PRESENT == 1U) + uint32_t ccsidr; + uint32_t sets; + uint32_t ways; + + SCB->CSSELR = (0U << 1U) | 0U; /* Level 1 data cache */ + __DSB(); + + ccsidr = SCB->CCSIDR; + + /* invalidate D-Cache */ + sets = (uint32_t)(CCSIDR_SETS(ccsidr)); + do + { + ways = (uint32_t)(CCSIDR_WAYS(ccsidr)); + do + { + SCB->DCISW = (((sets << SCB_DCISW_SET_Pos) & SCB_DCISW_SET_Msk) | + ((ways << SCB_DCISW_WAY_Pos) & SCB_DCISW_WAY_Msk)); +#if defined ( __CC_ARM ) + __schedule_barrier(); +#endif + } + while (ways--); + } + while (sets--); + + __DSB(); + __ISB(); +#endif +} + + +/** + \brief Clean D-Cache + \details Cleans D-Cache + */ +__STATIC_INLINE void SCB_CleanDCache(void) +{ +#if (__DCACHE_PRESENT == 1U) + uint32_t ccsidr; + uint32_t sets; + uint32_t ways; + + SCB->CSSELR = (0U << 1U) | 0U; /* Level 1 data cache */ + __DSB(); + + ccsidr = SCB->CCSIDR; + + /* clean D-Cache */ + sets = (uint32_t)(CCSIDR_SETS(ccsidr)); + do + { + ways = (uint32_t)(CCSIDR_WAYS(ccsidr)); + do + { + SCB->DCCSW = (((sets << SCB_DCCSW_SET_Pos) & SCB_DCCSW_SET_Msk) | + ((ways << SCB_DCCSW_WAY_Pos) & SCB_DCCSW_WAY_Msk)); +#if defined ( __CC_ARM ) + __schedule_barrier(); +#endif + } + while (ways--); + } + while (sets--); + + __DSB(); + __ISB(); +#endif +} + + +/** + \brief Clean & Invalidate D-Cache + \details Cleans and Invalidates D-Cache + */ +__STATIC_INLINE void SCB_CleanInvalidateDCache(void) +{ +#if (__DCACHE_PRESENT == 1U) + uint32_t ccsidr; + uint32_t sets; + uint32_t ways; + + SCB->CSSELR = (0U << 1U) | 0U; /* Level 1 data cache */ + __DSB(); + + ccsidr = SCB->CCSIDR; + + /* clean & invalidate D-Cache */ + sets = (uint32_t)(CCSIDR_SETS(ccsidr)); + do + { + ways = (uint32_t)(CCSIDR_WAYS(ccsidr)); + do + { + SCB->DCCISW = (((sets << SCB_DCCISW_SET_Pos) & SCB_DCCISW_SET_Msk) | + ((ways << SCB_DCCISW_WAY_Pos) & SCB_DCCISW_WAY_Msk)); +#if defined ( __CC_ARM ) + __schedule_barrier(); +#endif + } + while (ways--); + } + while (sets--); + + __DSB(); + __ISB(); +#endif +} + + +/** + \brief D-Cache Invalidate by address + \details Invalidates D-Cache for the given address + \param[in] addr address (aligned to 32-byte boundary) + \param[in] dsize size of memory block (in number of bytes) +*/ +__STATIC_INLINE void SCB_InvalidateDCache_by_Addr(uint32_t *addr, int32_t dsize) +{ +#if (__DCACHE_PRESENT == 1U) + int32_t op_size = dsize; + uint32_t op_addr = (uint32_t)addr; + int32_t linesize = 32U; /* in Cortex-M7 size of cache line is fixed to 8 words (32 bytes) */ + + __DSB(); + + while (op_size > 0) + { + SCB->DCIMVAC = op_addr; + op_addr += linesize; + op_size -= linesize; + } + + __DSB(); + __ISB(); +#endif +} + + +/** + \brief D-Cache Clean by address + \details Cleans D-Cache for the given address + \param[in] addr address (aligned to 32-byte boundary) + \param[in] dsize size of memory block (in number of bytes) +*/ +__STATIC_INLINE void SCB_CleanDCache_by_Addr(uint32_t *addr, int32_t dsize) +{ +#if (__DCACHE_PRESENT == 1) + int32_t op_size = dsize; + uint32_t op_addr = (uint32_t) addr; + int32_t linesize = 32U; /* in Cortex-M7 size of cache line is fixed to 8 words (32 bytes) */ + + __DSB(); + + while (op_size > 0) + { + SCB->DCCMVAC = op_addr; + op_addr += linesize; + op_size -= linesize; + } + + __DSB(); + __ISB(); +#endif +} + + +/** + \brief D-Cache Clean and Invalidate by address + \details Cleans and invalidates D_Cache for the given address + \param[in] addr address (aligned to 32-byte boundary) + \param[in] dsize size of memory block (in number of bytes) +*/ +__STATIC_INLINE void SCB_CleanInvalidateDCache_by_Addr(uint32_t *addr, int32_t dsize) +{ +#if (__DCACHE_PRESENT == 1U) + int32_t op_size = dsize; + uint32_t op_addr = (uint32_t) addr; + int32_t linesize = 32U; /* in Cortex-M7 size of cache line is fixed to 8 words (32 bytes) */ + + __DSB(); + + while (op_size > 0) + { + SCB->DCCIMVAC = op_addr; + op_addr += linesize; + op_size -= linesize; + } + + __DSB(); + __ISB(); +#endif +} + + +/*@} end of CMSIS_Core_CacheFunctions */ + + + +/* ################################## SysTick function ############################################ */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_SysTickFunctions SysTick Functions + \brief Functions that configure the System. + @{ + */ + +#if (__Vendor_SysTickConfig == 0U) + +/** + \brief System Tick Configuration + \details Initializes the System Timer and its interrupt, and starts the System Tick Timer. + Counter is in free running mode to generate periodic interrupts. + \param [in] ticks Number of ticks between two interrupts. + \return 0 Function succeeded. + \return 1 Function failed. + \note When the variable __Vendor_SysTickConfig is set to 1, then the + function SysTick_Config is not included. In this case, the file device.h + must contain a vendor-specific implementation of this function. + */ +__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks) +{ + if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk) + { + return (1UL); /* Reload value impossible */ + } + + SysTick->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */ + NVIC_SetPriority(SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */ + SysTick->VAL = 0UL; /* Load the SysTick Counter Value */ + SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk | + SysTick_CTRL_TICKINT_Msk | + SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */ + return (0UL); /* Function successful */ +} + +#endif + +/*@} end of CMSIS_Core_SysTickFunctions */ + + + +/* ##################################### Debug In/Output function ########################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_core_DebugFunctions ITM Functions + \brief Functions that access the ITM debug interface. + @{ + */ + +extern volatile int32_t ITM_RxBuffer; /*!< External variable to receive characters. */ +#define ITM_RXBUFFER_EMPTY 0x5AA55AA5U /*!< Value identifying \ref ITM_RxBuffer is ready for next character. */ + + +/** + \brief ITM Send Character + \details Transmits a character via the ITM channel 0, and + \li Just returns when no debugger is connected that has booked the output. + \li Is blocking when a debugger is connected, but the previous character sent has not been transmitted. + \param [in] ch Character to transmit. + \returns Character to transmit. + */ +__STATIC_INLINE uint32_t ITM_SendChar(uint32_t ch) +{ + if (((ITM->TCR & ITM_TCR_ITMENA_Msk) != 0UL) && /* ITM enabled */ + ((ITM->TER & 1UL) != 0UL)) /* ITM Port #0 enabled */ + { + while (ITM->PORT[0U].u32 == 0UL) + { + __NOP(); + } + ITM->PORT[0U].u8 = (uint8_t)ch; + } + return (ch); +} + + +/** + \brief ITM Receive Character + \details Inputs a character via the external variable \ref ITM_RxBuffer. + \return Received character. + \return -1 No character pending. + */ +__STATIC_INLINE int32_t ITM_ReceiveChar(void) +{ + int32_t ch = -1; /* no character available */ + + if (ITM_RxBuffer != ITM_RXBUFFER_EMPTY) + { + ch = ITM_RxBuffer; + ITM_RxBuffer = ITM_RXBUFFER_EMPTY; /* ready for next character */ + } + + return (ch); +} + + +/** + \brief ITM Check Character + \details Checks whether a character is pending for reading in the variable \ref ITM_RxBuffer. + \return 0 No character available. + \return 1 Character available. + */ +__STATIC_INLINE int32_t ITM_CheckChar(void) +{ + + if (ITM_RxBuffer == ITM_RXBUFFER_EMPTY) + { + return (0); /* no character available */ + } + else + { + return (1); /* character available */ + } +} + +/*@} end of CMSIS_core_DebugFunctions */ + + + + +#ifdef __cplusplus +} +#endif + +#endif /* __CORE_CM7_H_DEPENDANT */ + +#endif /* __CMSIS_GENERIC */ diff --git a/bsp/nuvoton/libraries/ma35/CMSIS/Include/core_cmFunc.h b/bsp/nuvoton/libraries/ma35/CMSIS/Include/core_cmFunc.h new file mode 100644 index 0000000000..ed3c190107 --- /dev/null +++ b/bsp/nuvoton/libraries/ma35/CMSIS/Include/core_cmFunc.h @@ -0,0 +1,87 @@ +/**************************************************************************//** + * @file core_cmFunc.h + * @brief CMSIS Cortex-M Core Function Access Header File + * @version V4.30 + * @date 20. October 2015 + ******************************************************************************/ +/* Copyright (c) 2009 - 2015 ARM LIMITED + + All rights reserved. + Redistribution and use in source and binary forms, with or without + modification, are permitted provided that the following conditions are met: + - Redistributions of source code must retain the above copyright + notice, this list of conditions and the following disclaimer. + - Redistributions in binary form must reproduce the above copyright + notice, this list of conditions and the following disclaimer in the + documentation and/or other materials provided with the distribution. + - Neither the name of ARM nor the names of its contributors may be used + to endorse or promote products derived from this software without + specific prior written permission. + * + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE + LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + POSSIBILITY OF SUCH DAMAGE. + ---------------------------------------------------------------------------*/ + + +#if defined ( __ICCARM__ ) + #pragma system_include /* treat file as system include file for MISRA check */ +#elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) + #pragma clang system_header /* treat file as system include file */ +#endif + +#ifndef __CORE_CMFUNC_H + #define __CORE_CMFUNC_H + + + /* ########################### Core Function Access ########################### */ + /** \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_RegAccFunctions CMSIS Core Register Access Functions + @{ + */ + + /*------------------ RealView Compiler -----------------*/ + #if defined ( __CC_ARM ) + #include "cmsis_armcc.h" + + /*------------------ ARM Compiler V6 -------------------*/ + #elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) + #include "cmsis_armcc_V6.h" + + /*------------------ GNU Compiler ----------------------*/ + #elif defined ( __GNUC__ ) + #include "cmsis_gcc.h" + + /*------------------ ICC Compiler ----------------------*/ + #elif defined ( __ICCARM__ ) + #include + + /*------------------ TI CCS Compiler -------------------*/ + #elif defined ( __TMS470__ ) + #include + + /*------------------ TASKING Compiler ------------------*/ + #elif defined ( __TASKING__ ) + /* + * The CMSIS functions have been implemented as intrinsics in the compiler. + * Please use "carm -?i" to get an up to date list of all intrinsics, + * Including the CMSIS ones. + */ + + /*------------------ COSMIC Compiler -------------------*/ + #elif defined ( __CSMC__ ) + #include + + #endif + + /*@} end of CMSIS_Core_RegAccFunctions */ + +#endif /* __CORE_CMFUNC_H */ diff --git a/bsp/nuvoton/libraries/ma35/CMSIS/Include/core_cmInstr.h b/bsp/nuvoton/libraries/ma35/CMSIS/Include/core_cmInstr.h new file mode 100644 index 0000000000..a334984f5d --- /dev/null +++ b/bsp/nuvoton/libraries/ma35/CMSIS/Include/core_cmInstr.h @@ -0,0 +1,87 @@ +/**************************************************************************//** + * @file core_cmInstr.h + * @brief CMSIS Cortex-M Core Instruction Access Header File + * @version V4.30 + * @date 20. October 2015 + ******************************************************************************/ +/* Copyright (c) 2009 - 2015 ARM LIMITED + + All rights reserved. + Redistribution and use in source and binary forms, with or without + modification, are permitted provided that the following conditions are met: + - Redistributions of source code must retain the above copyright + notice, this list of conditions and the following disclaimer. + - Redistributions in binary form must reproduce the above copyright + notice, this list of conditions and the following disclaimer in the + documentation and/or other materials provided with the distribution. + - Neither the name of ARM nor the names of its contributors may be used + to endorse or promote products derived from this software without + specific prior written permission. + * + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE + LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + POSSIBILITY OF SUCH DAMAGE. + ---------------------------------------------------------------------------*/ + + +#if defined ( __ICCARM__ ) + #pragma system_include /* treat file as system include file for MISRA check */ +#elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) + #pragma clang system_header /* treat file as system include file */ +#endif + +#ifndef __CORE_CMINSTR_H + #define __CORE_CMINSTR_H + + + /* ########################## Core Instruction Access ######################### */ + /** \defgroup CMSIS_Core_InstructionInterface CMSIS Core Instruction Interface + Access to dedicated instructions + @{ + */ + + /*------------------ RealView Compiler -----------------*/ + #if defined ( __CC_ARM ) + #include "cmsis_armcc.h" + + /*------------------ ARM Compiler V6 -------------------*/ + #elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) + #include "cmsis_armcc_V6.h" + + /*------------------ GNU Compiler ----------------------*/ + #elif defined ( __GNUC__ ) + #include "cmsis_gcc.h" + + /*------------------ ICC Compiler ----------------------*/ + #elif defined ( __ICCARM__ ) + #include + + /*------------------ TI CCS Compiler -------------------*/ + #elif defined ( __TMS470__ ) + #include + + /*------------------ TASKING Compiler ------------------*/ + #elif defined ( __TASKING__ ) + /* + * The CMSIS functions have been implemented as intrinsics in the compiler. + * Please use "carm -?i" to get an up to date list of all intrinsics, + * Including the CMSIS ones. + */ + + /*------------------ COSMIC Compiler -------------------*/ + #elif defined ( __CSMC__ ) + #include + + #endif + + /*@}*/ /* end of group CMSIS_Core_InstructionInterface */ + +#endif /* __CORE_CMINSTR_H */ diff --git a/bsp/nuvoton/libraries/ma35/CMSIS/Include/core_cmSimd.h b/bsp/nuvoton/libraries/ma35/CMSIS/Include/core_cmSimd.h new file mode 100644 index 0000000000..590ebee9d5 --- /dev/null +++ b/bsp/nuvoton/libraries/ma35/CMSIS/Include/core_cmSimd.h @@ -0,0 +1,96 @@ +/**************************************************************************//** + * @file core_cmSimd.h + * @brief CMSIS Cortex-M SIMD Header File + * @version V4.30 + * @date 20. October 2015 + ******************************************************************************/ +/* Copyright (c) 2009 - 2015 ARM LIMITED + + All rights reserved. + Redistribution and use in source and binary forms, with or without + modification, are permitted provided that the following conditions are met: + - Redistributions of source code must retain the above copyright + notice, this list of conditions and the following disclaimer. + - Redistributions in binary form must reproduce the above copyright + notice, this list of conditions and the following disclaimer in the + documentation and/or other materials provided with the distribution. + - Neither the name of ARM nor the names of its contributors may be used + to endorse or promote products derived from this software without + specific prior written permission. + * + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE + LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + POSSIBILITY OF SUCH DAMAGE. + ---------------------------------------------------------------------------*/ + + +#if defined ( __ICCARM__ ) + #pragma system_include /* treat file as system include file for MISRA check */ +#elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) + #pragma clang system_header /* treat file as system include file */ +#endif + +#ifndef __CORE_CMSIMD_H +#define __CORE_CMSIMD_H + +#ifdef __cplusplus +extern "C" { +#endif + + +/* ################### Compiler specific Intrinsics ########################### */ +/** \defgroup CMSIS_SIMD_intrinsics CMSIS SIMD Intrinsics + Access to dedicated SIMD instructions + @{ +*/ + +/*------------------ RealView Compiler -----------------*/ +#if defined ( __CC_ARM ) +#include "cmsis_armcc.h" + +/*------------------ ARM Compiler V6 -------------------*/ +#elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) +#include "cmsis_armcc_V6.h" + +/*------------------ GNU Compiler ----------------------*/ +#elif defined ( __GNUC__ ) +#include "cmsis_gcc.h" + +/*------------------ ICC Compiler ----------------------*/ +#elif defined ( __ICCARM__ ) +#include + +/*------------------ TI CCS Compiler -------------------*/ +#elif defined ( __TMS470__ ) +#include + +/*------------------ TASKING Compiler ------------------*/ +#elif defined ( __TASKING__ ) +/* + * The CMSIS functions have been implemented as intrinsics in the compiler. + * Please use "carm -?i" to get an up to date list of all intrinsics, + * Including the CMSIS ones. + */ + +/*------------------ COSMIC Compiler -------------------*/ +#elif defined ( __CSMC__ ) +#include + +#endif + +/*@} end of group CMSIS_SIMD_intrinsics */ + + +#ifdef __cplusplus +} +#endif + +#endif /* __CORE_CMSIMD_H */ diff --git a/bsp/nuvoton/libraries/ma35/CMSIS/Include/core_sc000.h b/bsp/nuvoton/libraries/ma35/CMSIS/Include/core_sc000.h new file mode 100644 index 0000000000..793c28f09b --- /dev/null +++ b/bsp/nuvoton/libraries/ma35/CMSIS/Include/core_sc000.h @@ -0,0 +1,926 @@ +/**************************************************************************//** + * @file core_sc000.h + * @brief CMSIS SC000 Core Peripheral Access Layer Header File + * @version V4.30 + * @date 20. October 2015 + ******************************************************************************/ +/* Copyright (c) 2009 - 2015 ARM LIMITED + + All rights reserved. + Redistribution and use in source and binary forms, with or without + modification, are permitted provided that the following conditions are met: + - Redistributions of source code must retain the above copyright + notice, this list of conditions and the following disclaimer. + - Redistributions in binary form must reproduce the above copyright + notice, this list of conditions and the following disclaimer in the + documentation and/or other materials provided with the distribution. + - Neither the name of ARM nor the names of its contributors may be used + to endorse or promote products derived from this software without + specific prior written permission. + * + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE + LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + POSSIBILITY OF SUCH DAMAGE. + ---------------------------------------------------------------------------*/ + + +#if defined ( __ICCARM__ ) + #pragma system_include /* treat file as system include file for MISRA check */ +#elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) + #pragma clang system_header /* treat file as system include file */ +#endif + +#ifndef __CORE_SC000_H_GENERIC +#define __CORE_SC000_H_GENERIC + +#include + +#ifdef __cplusplus +extern "C" { +#endif + +/** + \page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions + CMSIS violates the following MISRA-C:2004 rules: + + \li Required Rule 8.5, object/function definition in header file.
+ Function definitions in header files are used to allow 'inlining'. + + \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.
+ Unions are used for effective representation of core registers. + + \li Advisory Rule 19.7, Function-like macro defined.
+ Function-like macros are used to allow more efficient code. + */ + + +/******************************************************************************* + * CMSIS definitions + ******************************************************************************/ +/** + \ingroup SC000 + @{ + */ + +/* CMSIS SC000 definitions */ +#define __SC000_CMSIS_VERSION_MAIN (0x04U) /*!< [31:16] CMSIS HAL main version */ +#define __SC000_CMSIS_VERSION_SUB (0x1EU) /*!< [15:0] CMSIS HAL sub version */ +#define __SC000_CMSIS_VERSION ((__SC000_CMSIS_VERSION_MAIN << 16U) | \ + __SC000_CMSIS_VERSION_SUB ) /*!< CMSIS HAL version number */ + +#define __CORTEX_SC (000U) /*!< Cortex secure core */ + + +#if defined ( __CC_ARM ) +#define __ASM __asm /*!< asm keyword for ARM Compiler */ +#define __INLINE __inline /*!< inline keyword for ARM Compiler */ +#define __STATIC_INLINE static __inline + +#elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) +#define __ASM __asm /*!< asm keyword for ARM Compiler */ +#define __INLINE __inline /*!< inline keyword for ARM Compiler */ +#define __STATIC_INLINE static __inline + +#elif defined ( __GNUC__ ) +#define __ASM __asm /*!< asm keyword for GNU Compiler */ +#define __INLINE inline /*!< inline keyword for GNU Compiler */ +#define __STATIC_INLINE static inline + +#elif defined ( __ICCARM__ ) +#define __ASM __asm /*!< asm keyword for IAR Compiler */ +#define __INLINE inline /*!< inline keyword for IAR Compiler. Only available in High optimization mode! */ +#define __STATIC_INLINE static inline + +#elif defined ( __TMS470__ ) +#define __ASM __asm /*!< asm keyword for TI CCS Compiler */ +#define __STATIC_INLINE static inline + +#elif defined ( __TASKING__ ) +#define __ASM __asm /*!< asm keyword for TASKING Compiler */ +#define __INLINE inline /*!< inline keyword for TASKING Compiler */ +#define __STATIC_INLINE static inline + +#elif defined ( __CSMC__ ) +#define __packed +#define __ASM _asm /*!< asm keyword for COSMIC Compiler */ +#define __INLINE inline /*!< inline keyword for COSMIC Compiler. Use -pc99 on compile line */ +#define __STATIC_INLINE static inline + +#else +#error Unknown compiler +#endif + +/** __FPU_USED indicates whether an FPU is used or not. + This core does not support an FPU at all +*/ +#define __FPU_USED 0U + +#if defined ( __CC_ARM ) +#if defined __TARGET_FPU_VFP +#error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" +#endif + +#elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) +#if defined __ARM_PCS_VFP +#error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" +#endif + +#elif defined ( __GNUC__ ) +#if defined (__VFP_FP__) && !defined(__SOFTFP__) +#error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" +#endif + +#elif defined ( __ICCARM__ ) +#if defined __ARMVFP__ +#error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" +#endif + +#elif defined ( __TMS470__ ) +#if defined __TI_VFP_SUPPORT__ +#error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" +#endif + +#elif defined ( __TASKING__ ) +#if defined __FPU_VFP__ +#error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" +#endif + +#elif defined ( __CSMC__ ) +#if ( __CSMC__ & 0x400U) +#error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" +#endif + +#endif + +#include "core_cmInstr.h" /* Core Instruction Access */ +#include "core_cmFunc.h" /* Core Function Access */ + +#ifdef __cplusplus +} +#endif + +#endif /* __CORE_SC000_H_GENERIC */ + +#ifndef __CMSIS_GENERIC + +#ifndef __CORE_SC000_H_DEPENDANT +#define __CORE_SC000_H_DEPENDANT + +#ifdef __cplusplus +extern "C" { +#endif + +/* check device defines and use defaults */ +#if defined __CHECK_DEVICE_DEFINES +#ifndef __SC000_REV +#define __SC000_REV 0x0000U +#warning "__SC000_REV not defined in device header file; using default!" +#endif + +#ifndef __MPU_PRESENT +#define __MPU_PRESENT 0U +#warning "__MPU_PRESENT not defined in device header file; using default!" +#endif + +#ifndef __NVIC_PRIO_BITS +#define __NVIC_PRIO_BITS 2U +#warning "__NVIC_PRIO_BITS not defined in device header file; using default!" +#endif + +#ifndef __Vendor_SysTickConfig +#define __Vendor_SysTickConfig 0U +#warning "__Vendor_SysTickConfig not defined in device header file; using default!" +#endif +#endif + +/* IO definitions (access restrictions to peripheral registers) */ +/** + \defgroup CMSIS_glob_defs CMSIS Global Defines + + IO Type Qualifiers are used + \li to specify the access to peripheral variables. + \li for automatic generation of peripheral register debug information. +*/ +#ifdef __cplusplus +#define __I volatile /*!< Defines 'read only' permissions */ +#else +#define __I volatile const /*!< Defines 'read only' permissions */ +#endif +#define __O volatile /*!< Defines 'write only' permissions */ +#define __IO volatile /*!< Defines 'read / write' permissions */ + +/* following defines should be used for structure members */ +#define __IM volatile const /*! Defines 'read only' structure member permissions */ +#define __OM volatile /*! Defines 'write only' structure member permissions */ +#define __IOM volatile /*! Defines 'read / write' structure member permissions */ + +/*@} end of group SC000 */ + + + +/******************************************************************************* + * Register Abstraction + Core Register contain: + - Core Register + - Core NVIC Register + - Core SCB Register + - Core SysTick Register + - Core MPU Register + ******************************************************************************/ +/** + \defgroup CMSIS_core_register Defines and Type Definitions + \brief Type definitions and defines for Cortex-M processor based devices. +*/ + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_CORE Status and Control Registers + \brief Core Register type definitions. + @{ + */ + +/** + \brief Union type to access the Application Program Status Register (APSR). + */ +typedef union +{ + struct + { + uint32_t _reserved0: 28; /*!< bit: 0..27 Reserved */ + uint32_t V: 1; /*!< bit: 28 Overflow condition code flag */ + uint32_t C: 1; /*!< bit: 29 Carry condition code flag */ + uint32_t Z: 1; /*!< bit: 30 Zero condition code flag */ + uint32_t N: 1; /*!< bit: 31 Negative condition code flag */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} APSR_Type; + +/* APSR Register Definitions */ +#define APSR_N_Pos 31U /*!< APSR: N Position */ +#define APSR_N_Msk (1UL << APSR_N_Pos) /*!< APSR: N Mask */ + +#define APSR_Z_Pos 30U /*!< APSR: Z Position */ +#define APSR_Z_Msk (1UL << APSR_Z_Pos) /*!< APSR: Z Mask */ + +#define APSR_C_Pos 29U /*!< APSR: C Position */ +#define APSR_C_Msk (1UL << APSR_C_Pos) /*!< APSR: C Mask */ + +#define APSR_V_Pos 28U /*!< APSR: V Position */ +#define APSR_V_Msk (1UL << APSR_V_Pos) /*!< APSR: V Mask */ + + +/** + \brief Union type to access the Interrupt Program Status Register (IPSR). + */ +typedef union +{ + struct + { + uint32_t ISR: 9; /*!< bit: 0.. 8 Exception number */ + uint32_t _reserved0: 23; /*!< bit: 9..31 Reserved */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} IPSR_Type; + +/* IPSR Register Definitions */ +#define IPSR_ISR_Pos 0U /*!< IPSR: ISR Position */ +#define IPSR_ISR_Msk (0x1FFUL /*<< IPSR_ISR_Pos*/) /*!< IPSR: ISR Mask */ + + +/** + \brief Union type to access the Special-Purpose Program Status Registers (xPSR). + */ +typedef union +{ + struct + { + uint32_t ISR: 9; /*!< bit: 0.. 8 Exception number */ + uint32_t _reserved0: 15; /*!< bit: 9..23 Reserved */ + uint32_t T: 1; /*!< bit: 24 Thumb bit (read 0) */ + uint32_t _reserved1: 3; /*!< bit: 25..27 Reserved */ + uint32_t V: 1; /*!< bit: 28 Overflow condition code flag */ + uint32_t C: 1; /*!< bit: 29 Carry condition code flag */ + uint32_t Z: 1; /*!< bit: 30 Zero condition code flag */ + uint32_t N: 1; /*!< bit: 31 Negative condition code flag */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} xPSR_Type; + +/* xPSR Register Definitions */ +#define xPSR_N_Pos 31U /*!< xPSR: N Position */ +#define xPSR_N_Msk (1UL << xPSR_N_Pos) /*!< xPSR: N Mask */ + +#define xPSR_Z_Pos 30U /*!< xPSR: Z Position */ +#define xPSR_Z_Msk (1UL << xPSR_Z_Pos) /*!< xPSR: Z Mask */ + +#define xPSR_C_Pos 29U /*!< xPSR: C Position */ +#define xPSR_C_Msk (1UL << xPSR_C_Pos) /*!< xPSR: C Mask */ + +#define xPSR_V_Pos 28U /*!< xPSR: V Position */ +#define xPSR_V_Msk (1UL << xPSR_V_Pos) /*!< xPSR: V Mask */ + +#define xPSR_T_Pos 24U /*!< xPSR: T Position */ +#define xPSR_T_Msk (1UL << xPSR_T_Pos) /*!< xPSR: T Mask */ + +#define xPSR_ISR_Pos 0U /*!< xPSR: ISR Position */ +#define xPSR_ISR_Msk (0x1FFUL /*<< xPSR_ISR_Pos*/) /*!< xPSR: ISR Mask */ + + +/** + \brief Union type to access the Control Registers (CONTROL). + */ +typedef union +{ + struct + { + uint32_t _reserved0: 1; /*!< bit: 0 Reserved */ + uint32_t SPSEL: 1; /*!< bit: 1 Stack to be used */ + uint32_t _reserved1: 30; /*!< bit: 2..31 Reserved */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} CONTROL_Type; + +/* CONTROL Register Definitions */ +#define CONTROL_SPSEL_Pos 1U /*!< CONTROL: SPSEL Position */ +#define CONTROL_SPSEL_Msk (1UL << CONTROL_SPSEL_Pos) /*!< CONTROL: SPSEL Mask */ + +/*@} end of group CMSIS_CORE */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC) + \brief Type definitions for the NVIC Registers + @{ + */ + +/** + \brief Structure type to access the Nested Vectored Interrupt Controller (NVIC). + */ +typedef struct +{ + __IOM uint32_t ISER[1U]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */ + uint32_t RESERVED0[31U]; + __IOM uint32_t ICER[1U]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */ + uint32_t RSERVED1[31U]; + __IOM uint32_t ISPR[1U]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */ + uint32_t RESERVED2[31U]; + __IOM uint32_t ICPR[1U]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register */ + uint32_t RESERVED3[31U]; + uint32_t RESERVED4[64U]; + __IOM uint32_t IP[8U]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register */ +} NVIC_Type; + +/*@} end of group CMSIS_NVIC */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SCB System Control Block (SCB) + \brief Type definitions for the System Control Block Registers + @{ + */ + +/** + \brief Structure type to access the System Control Block (SCB). + */ +typedef struct +{ + __IM uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */ + __IOM uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Register */ + __IOM uint32_t VTOR; /*!< Offset: 0x008 (R/W) Vector Table Offset Register */ + __IOM uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register */ + __IOM uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */ + __IOM uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */ + uint32_t RESERVED0[1U]; + __IOM uint32_t SHP[2U]; /*!< Offset: 0x01C (R/W) System Handlers Priority Registers. [0] is RESERVED */ + __IOM uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State Register */ + uint32_t RESERVED1[154U]; + __IOM uint32_t SFCR; /*!< Offset: 0x290 (R/W) Security Features Control Register */ +} SCB_Type; + +/* SCB CPUID Register Definitions */ +#define SCB_CPUID_IMPLEMENTER_Pos 24U /*!< SCB CPUID: IMPLEMENTER Position */ +#define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */ + +#define SCB_CPUID_VARIANT_Pos 20U /*!< SCB CPUID: VARIANT Position */ +#define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */ + +#define SCB_CPUID_ARCHITECTURE_Pos 16U /*!< SCB CPUID: ARCHITECTURE Position */ +#define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB CPUID: ARCHITECTURE Mask */ + +#define SCB_CPUID_PARTNO_Pos 4U /*!< SCB CPUID: PARTNO Position */ +#define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */ + +#define SCB_CPUID_REVISION_Pos 0U /*!< SCB CPUID: REVISION Position */ +#define SCB_CPUID_REVISION_Msk (0xFUL /*<< SCB_CPUID_REVISION_Pos*/) /*!< SCB CPUID: REVISION Mask */ + +/* SCB Interrupt Control State Register Definitions */ +#define SCB_ICSR_NMIPENDSET_Pos 31U /*!< SCB ICSR: NMIPENDSET Position */ +#define SCB_ICSR_NMIPENDSET_Msk (1UL << SCB_ICSR_NMIPENDSET_Pos) /*!< SCB ICSR: NMIPENDSET Mask */ + +#define SCB_ICSR_PENDSVSET_Pos 28U /*!< SCB ICSR: PENDSVSET Position */ +#define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */ + +#define SCB_ICSR_PENDSVCLR_Pos 27U /*!< SCB ICSR: PENDSVCLR Position */ +#define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */ + +#define SCB_ICSR_PENDSTSET_Pos 26U /*!< SCB ICSR: PENDSTSET Position */ +#define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */ + +#define SCB_ICSR_PENDSTCLR_Pos 25U /*!< SCB ICSR: PENDSTCLR Position */ +#define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */ + +#define SCB_ICSR_ISRPREEMPT_Pos 23U /*!< SCB ICSR: ISRPREEMPT Position */ +#define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */ + +#define SCB_ICSR_ISRPENDING_Pos 22U /*!< SCB ICSR: ISRPENDING Position */ +#define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */ + +#define SCB_ICSR_VECTPENDING_Pos 12U /*!< SCB ICSR: VECTPENDING Position */ +#define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */ + +#define SCB_ICSR_VECTACTIVE_Pos 0U /*!< SCB ICSR: VECTACTIVE Position */ +#define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/) /*!< SCB ICSR: VECTACTIVE Mask */ + +/* SCB Interrupt Control State Register Definitions */ +#define SCB_VTOR_TBLOFF_Pos 7U /*!< SCB VTOR: TBLOFF Position */ +#define SCB_VTOR_TBLOFF_Msk (0x1FFFFFFUL << SCB_VTOR_TBLOFF_Pos) /*!< SCB VTOR: TBLOFF Mask */ + +/* SCB Application Interrupt and Reset Control Register Definitions */ +#define SCB_AIRCR_VECTKEY_Pos 16U /*!< SCB AIRCR: VECTKEY Position */ +#define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */ + +#define SCB_AIRCR_VECTKEYSTAT_Pos 16U /*!< SCB AIRCR: VECTKEYSTAT Position */ +#define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */ + +#define SCB_AIRCR_ENDIANESS_Pos 15U /*!< SCB AIRCR: ENDIANESS Position */ +#define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /*!< SCB AIRCR: ENDIANESS Mask */ + +#define SCB_AIRCR_SYSRESETREQ_Pos 2U /*!< SCB AIRCR: SYSRESETREQ Position */ +#define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */ + +#define SCB_AIRCR_VECTCLRACTIVE_Pos 1U /*!< SCB AIRCR: VECTCLRACTIVE Position */ +#define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */ + +/* SCB System Control Register Definitions */ +#define SCB_SCR_SEVONPEND_Pos 4U /*!< SCB SCR: SEVONPEND Position */ +#define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */ + +#define SCB_SCR_SLEEPDEEP_Pos 2U /*!< SCB SCR: SLEEPDEEP Position */ +#define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */ + +#define SCB_SCR_SLEEPONEXIT_Pos 1U /*!< SCB SCR: SLEEPONEXIT Position */ +#define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */ + +/* SCB Configuration Control Register Definitions */ +#define SCB_CCR_STKALIGN_Pos 9U /*!< SCB CCR: STKALIGN Position */ +#define SCB_CCR_STKALIGN_Msk (1UL << SCB_CCR_STKALIGN_Pos) /*!< SCB CCR: STKALIGN Mask */ + +#define SCB_CCR_UNALIGN_TRP_Pos 3U /*!< SCB CCR: UNALIGN_TRP Position */ +#define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */ + +/* SCB System Handler Control and State Register Definitions */ +#define SCB_SHCSR_SVCALLPENDED_Pos 15U /*!< SCB SHCSR: SVCALLPENDED Position */ +#define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */ + +/*@} end of group CMSIS_SCB */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SCnSCB System Controls not in SCB (SCnSCB) + \brief Type definitions for the System Control and ID Register not in the SCB + @{ + */ + +/** + \brief Structure type to access the System Control and ID Register not in the SCB. + */ +typedef struct +{ + uint32_t RESERVED0[2U]; + __IOM uint32_t ACTLR; /*!< Offset: 0x008 (R/W) Auxiliary Control Register */ +} SCnSCB_Type; + +/* Auxiliary Control Register Definitions */ +#define SCnSCB_ACTLR_DISMCYCINT_Pos 0U /*!< ACTLR: DISMCYCINT Position */ +#define SCnSCB_ACTLR_DISMCYCINT_Msk (1UL /*<< SCnSCB_ACTLR_DISMCYCINT_Pos*/) /*!< ACTLR: DISMCYCINT Mask */ + +/*@} end of group CMSIS_SCnotSCB */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SysTick System Tick Timer (SysTick) + \brief Type definitions for the System Timer Registers. + @{ + */ + +/** + \brief Structure type to access the System Timer (SysTick). + */ +typedef struct +{ + __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */ + __IOM uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */ + __IOM uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register */ + __IM uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */ +} SysTick_Type; + +/* SysTick Control / Status Register Definitions */ +#define SysTick_CTRL_COUNTFLAG_Pos 16U /*!< SysTick CTRL: COUNTFLAG Position */ +#define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */ + +#define SysTick_CTRL_CLKSOURCE_Pos 2U /*!< SysTick CTRL: CLKSOURCE Position */ +#define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */ + +#define SysTick_CTRL_TICKINT_Pos 1U /*!< SysTick CTRL: TICKINT Position */ +#define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */ + +#define SysTick_CTRL_ENABLE_Pos 0U /*!< SysTick CTRL: ENABLE Position */ +#define SysTick_CTRL_ENABLE_Msk (1UL /*<< SysTick_CTRL_ENABLE_Pos*/) /*!< SysTick CTRL: ENABLE Mask */ + +/* SysTick Reload Register Definitions */ +#define SysTick_LOAD_RELOAD_Pos 0U /*!< SysTick LOAD: RELOAD Position */ +#define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/) /*!< SysTick LOAD: RELOAD Mask */ + +/* SysTick Current Register Definitions */ +#define SysTick_VAL_CURRENT_Pos 0U /*!< SysTick VAL: CURRENT Position */ +#define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/) /*!< SysTick VAL: CURRENT Mask */ + +/* SysTick Calibration Register Definitions */ +#define SysTick_CALIB_NOREF_Pos 31U /*!< SysTick CALIB: NOREF Position */ +#define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */ + +#define SysTick_CALIB_SKEW_Pos 30U /*!< SysTick CALIB: SKEW Position */ +#define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */ + +#define SysTick_CALIB_TENMS_Pos 0U /*!< SysTick CALIB: TENMS Position */ +#define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/) /*!< SysTick CALIB: TENMS Mask */ + +/*@} end of group CMSIS_SysTick */ + +#if (__MPU_PRESENT == 1U) +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_MPU Memory Protection Unit (MPU) + \brief Type definitions for the Memory Protection Unit (MPU) + @{ + */ + +/** + \brief Structure type to access the Memory Protection Unit (MPU). + */ +typedef struct +{ + __IM uint32_t TYPE; /*!< Offset: 0x000 (R/ ) MPU Type Register */ + __IOM uint32_t CTRL; /*!< Offset: 0x004 (R/W) MPU Control Register */ + __IOM uint32_t RNR; /*!< Offset: 0x008 (R/W) MPU Region RNRber Register */ + __IOM uint32_t RBAR; /*!< Offset: 0x00C (R/W) MPU Region Base Address Register */ + __IOM uint32_t RASR; /*!< Offset: 0x010 (R/W) MPU Region Attribute and Size Register */ +} MPU_Type; + +/* MPU Type Register Definitions */ +#define MPU_TYPE_IREGION_Pos 16U /*!< MPU TYPE: IREGION Position */ +#define MPU_TYPE_IREGION_Msk (0xFFUL << MPU_TYPE_IREGION_Pos) /*!< MPU TYPE: IREGION Mask */ + +#define MPU_TYPE_DREGION_Pos 8U /*!< MPU TYPE: DREGION Position */ +#define MPU_TYPE_DREGION_Msk (0xFFUL << MPU_TYPE_DREGION_Pos) /*!< MPU TYPE: DREGION Mask */ + +#define MPU_TYPE_SEPARATE_Pos 0U /*!< MPU TYPE: SEPARATE Position */ +#define MPU_TYPE_SEPARATE_Msk (1UL /*<< MPU_TYPE_SEPARATE_Pos*/) /*!< MPU TYPE: SEPARATE Mask */ + +/* MPU Control Register Definitions */ +#define MPU_CTRL_PRIVDEFENA_Pos 2U /*!< MPU CTRL: PRIVDEFENA Position */ +#define MPU_CTRL_PRIVDEFENA_Msk (1UL << MPU_CTRL_PRIVDEFENA_Pos) /*!< MPU CTRL: PRIVDEFENA Mask */ + +#define MPU_CTRL_HFNMIENA_Pos 1U /*!< MPU CTRL: HFNMIENA Position */ +#define MPU_CTRL_HFNMIENA_Msk (1UL << MPU_CTRL_HFNMIENA_Pos) /*!< MPU CTRL: HFNMIENA Mask */ + +#define MPU_CTRL_ENABLE_Pos 0U /*!< MPU CTRL: ENABLE Position */ +#define MPU_CTRL_ENABLE_Msk (1UL /*<< MPU_CTRL_ENABLE_Pos*/) /*!< MPU CTRL: ENABLE Mask */ + +/* MPU Region Number Register Definitions */ +#define MPU_RNR_REGION_Pos 0U /*!< MPU RNR: REGION Position */ +#define MPU_RNR_REGION_Msk (0xFFUL /*<< MPU_RNR_REGION_Pos*/) /*!< MPU RNR: REGION Mask */ + +/* MPU Region Base Address Register Definitions */ +#define MPU_RBAR_ADDR_Pos 8U /*!< MPU RBAR: ADDR Position */ +#define MPU_RBAR_ADDR_Msk (0xFFFFFFUL << MPU_RBAR_ADDR_Pos) /*!< MPU RBAR: ADDR Mask */ + +#define MPU_RBAR_VALID_Pos 4U /*!< MPU RBAR: VALID Position */ +#define MPU_RBAR_VALID_Msk (1UL << MPU_RBAR_VALID_Pos) /*!< MPU RBAR: VALID Mask */ + +#define MPU_RBAR_REGION_Pos 0U /*!< MPU RBAR: REGION Position */ +#define MPU_RBAR_REGION_Msk (0xFUL /*<< MPU_RBAR_REGION_Pos*/) /*!< MPU RBAR: REGION Mask */ + +/* MPU Region Attribute and Size Register Definitions */ +#define MPU_RASR_ATTRS_Pos 16U /*!< MPU RASR: MPU Region Attribute field Position */ +#define MPU_RASR_ATTRS_Msk (0xFFFFUL << MPU_RASR_ATTRS_Pos) /*!< MPU RASR: MPU Region Attribute field Mask */ + +#define MPU_RASR_XN_Pos 28U /*!< MPU RASR: ATTRS.XN Position */ +#define MPU_RASR_XN_Msk (1UL << MPU_RASR_XN_Pos) /*!< MPU RASR: ATTRS.XN Mask */ + +#define MPU_RASR_AP_Pos 24U /*!< MPU RASR: ATTRS.AP Position */ +#define MPU_RASR_AP_Msk (0x7UL << MPU_RASR_AP_Pos) /*!< MPU RASR: ATTRS.AP Mask */ + +#define MPU_RASR_TEX_Pos 19U /*!< MPU RASR: ATTRS.TEX Position */ +#define MPU_RASR_TEX_Msk (0x7UL << MPU_RASR_TEX_Pos) /*!< MPU RASR: ATTRS.TEX Mask */ + +#define MPU_RASR_S_Pos 18U /*!< MPU RASR: ATTRS.S Position */ +#define MPU_RASR_S_Msk (1UL << MPU_RASR_S_Pos) /*!< MPU RASR: ATTRS.S Mask */ + +#define MPU_RASR_C_Pos 17U /*!< MPU RASR: ATTRS.C Position */ +#define MPU_RASR_C_Msk (1UL << MPU_RASR_C_Pos) /*!< MPU RASR: ATTRS.C Mask */ + +#define MPU_RASR_B_Pos 16U /*!< MPU RASR: ATTRS.B Position */ +#define MPU_RASR_B_Msk (1UL << MPU_RASR_B_Pos) /*!< MPU RASR: ATTRS.B Mask */ + +#define MPU_RASR_SRD_Pos 8U /*!< MPU RASR: Sub-Region Disable Position */ +#define MPU_RASR_SRD_Msk (0xFFUL << MPU_RASR_SRD_Pos) /*!< MPU RASR: Sub-Region Disable Mask */ + +#define MPU_RASR_SIZE_Pos 1U /*!< MPU RASR: Region Size Field Position */ +#define MPU_RASR_SIZE_Msk (0x1FUL << MPU_RASR_SIZE_Pos) /*!< MPU RASR: Region Size Field Mask */ + +#define MPU_RASR_ENABLE_Pos 0U /*!< MPU RASR: Region enable bit Position */ +#define MPU_RASR_ENABLE_Msk (1UL /*<< MPU_RASR_ENABLE_Pos*/) /*!< MPU RASR: Region enable bit Disable Mask */ + +/*@} end of group CMSIS_MPU */ +#endif + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_CoreDebug Core Debug Registers (CoreDebug) + \brief SC000 Core Debug Registers (DCB registers, SHCSR, and DFSR) are only accessible over DAP and not via processor. + Therefore they are not covered by the SC000 header file. + @{ + */ +/*@} end of group CMSIS_CoreDebug */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_core_bitfield Core register bit field macros + \brief Macros for use with bit field definitions (xxx_Pos, xxx_Msk). + @{ + */ + +/** + \brief Mask and shift a bit field value for use in a register bit range. + \param[in] field Name of the register bit field. + \param[in] value Value of the bit field. + \return Masked and shifted value. +*/ +#define _VAL2FLD(field, value) ((value << field ## _Pos) & field ## _Msk) + +/** + \brief Mask and shift a register value to extract a bit filed value. + \param[in] field Name of the register bit field. + \param[in] value Value of register. + \return Masked and shifted bit field value. +*/ +#define _FLD2VAL(field, value) ((value & field ## _Msk) >> field ## _Pos) + +/*@} end of group CMSIS_core_bitfield */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_core_base Core Definitions + \brief Definitions for base addresses, unions, and structures. + @{ + */ + +/* Memory mapping of SC000 Hardware */ +#define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */ +#define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */ +#define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */ +#define SCB_BASE (SCS_BASE + 0x0D00UL) /*!< System Control Block Base Address */ + +#define SCnSCB ((SCnSCB_Type *) SCS_BASE ) /*!< System control Register not in SCB */ +#define SCB ((SCB_Type *) SCB_BASE ) /*!< SCB configuration struct */ +#define SysTick ((SysTick_Type *) SysTick_BASE ) /*!< SysTick configuration struct */ +#define NVIC ((NVIC_Type *) NVIC_BASE ) /*!< NVIC configuration struct */ + +#if (__MPU_PRESENT == 1U) +#define MPU_BASE (SCS_BASE + 0x0D90UL) /*!< Memory Protection Unit */ +#define MPU ((MPU_Type *) MPU_BASE ) /*!< Memory Protection Unit */ +#endif + +/*@} */ + + + +/******************************************************************************* + * Hardware Abstraction Layer + Core Function Interface contains: + - Core NVIC Functions + - Core SysTick Functions + - Core Register Access Functions + ******************************************************************************/ +/** + \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference +*/ + + + +/* ########################## NVIC functions #################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_NVICFunctions NVIC Functions + \brief Functions that manage interrupts and exceptions via the NVIC. + @{ + */ + +/* Interrupt Priorities are WORD accessible only under ARMv6M */ +/* The following MACROS handle generation of the register offset and byte masks */ +#define _BIT_SHIFT(IRQn) ( ((((uint32_t)(int32_t)(IRQn)) ) & 0x03UL) * 8UL) +#define _SHP_IDX(IRQn) ( (((((uint32_t)(int32_t)(IRQn)) & 0x0FUL)-8UL) >> 2UL) ) +#define _IP_IDX(IRQn) ( (((uint32_t)(int32_t)(IRQn)) >> 2UL) ) + + +/** + \brief Enable External Interrupt + \details Enables a device-specific interrupt in the NVIC interrupt controller. + \param [in] IRQn External interrupt number. Value cannot be negative. + */ +__STATIC_INLINE void NVIC_EnableIRQ(IRQn_Type IRQn) +{ + NVIC->ISER[0U] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL)); +} + + +/** + \brief Disable External Interrupt + \details Disables a device-specific interrupt in the NVIC interrupt controller. + \param [in] IRQn External interrupt number. Value cannot be negative. + */ +__STATIC_INLINE void NVIC_DisableIRQ(IRQn_Type IRQn) +{ + NVIC->ICER[0U] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL)); +} + + +/** + \brief Get Pending Interrupt + \details Reads the pending register in the NVIC and returns the pending bit for the specified interrupt. + \param [in] IRQn Interrupt number. + \return 0 Interrupt status is not pending. + \return 1 Interrupt status is pending. + */ +__STATIC_INLINE uint32_t NVIC_GetPendingIRQ(IRQn_Type IRQn) +{ + return ((uint32_t)(((NVIC->ISPR[0U] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); +} + + +/** + \brief Set Pending Interrupt + \details Sets the pending bit of an external interrupt. + \param [in] IRQn Interrupt number. Value cannot be negative. + */ +__STATIC_INLINE void NVIC_SetPendingIRQ(IRQn_Type IRQn) +{ + NVIC->ISPR[0U] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL)); +} + + +/** + \brief Clear Pending Interrupt + \details Clears the pending bit of an external interrupt. + \param [in] IRQn External interrupt number. Value cannot be negative. + */ +__STATIC_INLINE void NVIC_ClearPendingIRQ(IRQn_Type IRQn) +{ + NVIC->ICPR[0U] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL)); +} + + +/** + \brief Set Interrupt Priority + \details Sets the priority of an interrupt. + \note The priority cannot be set for every core interrupt. + \param [in] IRQn Interrupt number. + \param [in] priority Priority to set. + */ +__STATIC_INLINE void NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority) +{ + if ((int32_t)(IRQn) < 0) + { + SCB->SHP[_SHP_IDX(IRQn)] = ((uint32_t)(SCB->SHP[_SHP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) | + (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn))); + } + else + { + NVIC->IP[_IP_IDX(IRQn)] = ((uint32_t)(NVIC->IP[_IP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) | + (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn))); + } +} + + +/** + \brief Get Interrupt Priority + \details Reads the priority of an interrupt. + The interrupt number can be positive to specify an external (device specific) interrupt, + or negative to specify an internal (core) interrupt. + \param [in] IRQn Interrupt number. + \return Interrupt Priority. + Value is aligned automatically to the implemented priority bits of the microcontroller. + */ +__STATIC_INLINE uint32_t NVIC_GetPriority(IRQn_Type IRQn) +{ + + if ((int32_t)(IRQn) < 0) + { + return ((uint32_t)(((SCB->SHP[_SHP_IDX(IRQn)] >> _BIT_SHIFT(IRQn)) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS))); + } + else + { + return ((uint32_t)(((NVIC->IP[ _IP_IDX(IRQn)] >> _BIT_SHIFT(IRQn)) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS))); + } +} + + +/** + \brief System Reset + \details Initiates a system reset request to reset the MCU. + */ +__STATIC_INLINE void NVIC_SystemReset(void) +{ + __DSB(); /* Ensure all outstanding memory accesses included + buffered write are completed before reset */ + SCB->AIRCR = ((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | + SCB_AIRCR_SYSRESETREQ_Msk); + __DSB(); /* Ensure completion of memory access */ + + for (;;) /* wait until reset */ + { + __NOP(); + } +} + +/*@} end of CMSIS_Core_NVICFunctions */ + + + +/* ################################## SysTick function ############################################ */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_SysTickFunctions SysTick Functions + \brief Functions that configure the System. + @{ + */ + +#if (__Vendor_SysTickConfig == 0U) + +/** + \brief System Tick Configuration + \details Initializes the System Timer and its interrupt, and starts the System Tick Timer. + Counter is in free running mode to generate periodic interrupts. + \param [in] ticks Number of ticks between two interrupts. + \return 0 Function succeeded. + \return 1 Function failed. + \note When the variable __Vendor_SysTickConfig is set to 1, then the + function SysTick_Config is not included. In this case, the file device.h + must contain a vendor-specific implementation of this function. + */ +__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks) +{ + if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk) + { + return (1UL); /* Reload value impossible */ + } + + SysTick->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */ + NVIC_SetPriority(SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */ + SysTick->VAL = 0UL; /* Load the SysTick Counter Value */ + SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk | + SysTick_CTRL_TICKINT_Msk | + SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */ + return (0UL); /* Function successful */ +} + +#endif + +/*@} end of CMSIS_Core_SysTickFunctions */ + + + + +#ifdef __cplusplus +} +#endif + +#endif /* __CORE_SC000_H_DEPENDANT */ + +#endif /* __CMSIS_GENERIC */ diff --git a/bsp/nuvoton/libraries/ma35/CMSIS/Include/core_sc300.h b/bsp/nuvoton/libraries/ma35/CMSIS/Include/core_sc300.h new file mode 100644 index 0000000000..eaece43eb2 --- /dev/null +++ b/bsp/nuvoton/libraries/ma35/CMSIS/Include/core_sc300.h @@ -0,0 +1,1745 @@ +/**************************************************************************//** + * @file core_sc300.h + * @brief CMSIS SC300 Core Peripheral Access Layer Header File + * @version V4.30 + * @date 20. October 2015 + ******************************************************************************/ +/* Copyright (c) 2009 - 2015 ARM LIMITED + + All rights reserved. + Redistribution and use in source and binary forms, with or without + modification, are permitted provided that the following conditions are met: + - Redistributions of source code must retain the above copyright + notice, this list of conditions and the following disclaimer. + - Redistributions in binary form must reproduce the above copyright + notice, this list of conditions and the following disclaimer in the + documentation and/or other materials provided with the distribution. + - Neither the name of ARM nor the names of its contributors may be used + to endorse or promote products derived from this software without + specific prior written permission. + * + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE + LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + POSSIBILITY OF SUCH DAMAGE. + ---------------------------------------------------------------------------*/ + + +#if defined ( __ICCARM__ ) + #pragma system_include /* treat file as system include file for MISRA check */ +#elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) + #pragma clang system_header /* treat file as system include file */ +#endif + +#ifndef __CORE_SC300_H_GENERIC +#define __CORE_SC300_H_GENERIC + +#include + +#ifdef __cplusplus +extern "C" { +#endif + +/** + \page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions + CMSIS violates the following MISRA-C:2004 rules: + + \li Required Rule 8.5, object/function definition in header file.
+ Function definitions in header files are used to allow 'inlining'. + + \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.
+ Unions are used for effective representation of core registers. + + \li Advisory Rule 19.7, Function-like macro defined.
+ Function-like macros are used to allow more efficient code. + */ + + +/******************************************************************************* + * CMSIS definitions + ******************************************************************************/ +/** + \ingroup SC3000 + @{ + */ + +/* CMSIS SC300 definitions */ +#define __SC300_CMSIS_VERSION_MAIN (0x04U) /*!< [31:16] CMSIS HAL main version */ +#define __SC300_CMSIS_VERSION_SUB (0x1EU) /*!< [15:0] CMSIS HAL sub version */ +#define __SC300_CMSIS_VERSION ((__SC300_CMSIS_VERSION_MAIN << 16U) | \ + __SC300_CMSIS_VERSION_SUB ) /*!< CMSIS HAL version number */ + +#define __CORTEX_SC (300U) /*!< Cortex secure core */ + + +#if defined ( __CC_ARM ) +#define __ASM __asm /*!< asm keyword for ARM Compiler */ +#define __INLINE __inline /*!< inline keyword for ARM Compiler */ +#define __STATIC_INLINE static __inline + +#elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) +#define __ASM __asm /*!< asm keyword for ARM Compiler */ +#define __INLINE __inline /*!< inline keyword for ARM Compiler */ +#define __STATIC_INLINE static __inline + +#elif defined ( __GNUC__ ) +#define __ASM __asm /*!< asm keyword for GNU Compiler */ +#define __INLINE inline /*!< inline keyword for GNU Compiler */ +#define __STATIC_INLINE static inline + +#elif defined ( __ICCARM__ ) +#define __ASM __asm /*!< asm keyword for IAR Compiler */ +#define __INLINE inline /*!< inline keyword for IAR Compiler. Only available in High optimization mode! */ +#define __STATIC_INLINE static inline + +#elif defined ( __TMS470__ ) +#define __ASM __asm /*!< asm keyword for TI CCS Compiler */ +#define __STATIC_INLINE static inline + +#elif defined ( __TASKING__ ) +#define __ASM __asm /*!< asm keyword for TASKING Compiler */ +#define __INLINE inline /*!< inline keyword for TASKING Compiler */ +#define __STATIC_INLINE static inline + +#elif defined ( __CSMC__ ) +#define __packed +#define __ASM _asm /*!< asm keyword for COSMIC Compiler */ +#define __INLINE inline /*!< inline keyword for COSMIC Compiler. Use -pc99 on compile line */ +#define __STATIC_INLINE static inline + +#else +#error Unknown compiler +#endif + +/** __FPU_USED indicates whether an FPU is used or not. + This core does not support an FPU at all +*/ +#define __FPU_USED 0U + +#if defined ( __CC_ARM ) +#if defined __TARGET_FPU_VFP +#error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" +#endif + +#elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) +#if defined __ARM_PCS_VFP +#error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" +#endif + +#elif defined ( __GNUC__ ) +#if defined (__VFP_FP__) && !defined(__SOFTFP__) +#error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" +#endif + +#elif defined ( __ICCARM__ ) +#if defined __ARMVFP__ +#error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" +#endif + +#elif defined ( __TMS470__ ) +#if defined __TI_VFP_SUPPORT__ +#error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" +#endif + +#elif defined ( __TASKING__ ) +#if defined __FPU_VFP__ +#error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" +#endif + +#elif defined ( __CSMC__ ) +#if ( __CSMC__ & 0x400U) +#error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" +#endif + +#endif + +#include "core_cmInstr.h" /* Core Instruction Access */ +#include "core_cmFunc.h" /* Core Function Access */ + +#ifdef __cplusplus +} +#endif + +#endif /* __CORE_SC300_H_GENERIC */ + +#ifndef __CMSIS_GENERIC + +#ifndef __CORE_SC300_H_DEPENDANT +#define __CORE_SC300_H_DEPENDANT + +#ifdef __cplusplus +extern "C" { +#endif + +/* check device defines and use defaults */ +#if defined __CHECK_DEVICE_DEFINES +#ifndef __SC300_REV +#define __SC300_REV 0x0000U +#warning "__SC300_REV not defined in device header file; using default!" +#endif + +#ifndef __MPU_PRESENT +#define __MPU_PRESENT 0U +#warning "__MPU_PRESENT not defined in device header file; using default!" +#endif + +#ifndef __NVIC_PRIO_BITS +#define __NVIC_PRIO_BITS 4U +#warning "__NVIC_PRIO_BITS not defined in device header file; using default!" +#endif + +#ifndef __Vendor_SysTickConfig +#define __Vendor_SysTickConfig 0U +#warning "__Vendor_SysTickConfig not defined in device header file; using default!" +#endif +#endif + +/* IO definitions (access restrictions to peripheral registers) */ +/** + \defgroup CMSIS_glob_defs CMSIS Global Defines + + IO Type Qualifiers are used + \li to specify the access to peripheral variables. + \li for automatic generation of peripheral register debug information. +*/ +#ifdef __cplusplus +#define __I volatile /*!< Defines 'read only' permissions */ +#else +#define __I volatile const /*!< Defines 'read only' permissions */ +#endif +#define __O volatile /*!< Defines 'write only' permissions */ +#define __IO volatile /*!< Defines 'read / write' permissions */ + +/* following defines should be used for structure members */ +#define __IM volatile const /*! Defines 'read only' structure member permissions */ +#define __OM volatile /*! Defines 'write only' structure member permissions */ +#define __IOM volatile /*! Defines 'read / write' structure member permissions */ + +/*@} end of group SC300 */ + + + +/******************************************************************************* + * Register Abstraction + Core Register contain: + - Core Register + - Core NVIC Register + - Core SCB Register + - Core SysTick Register + - Core Debug Register + - Core MPU Register + ******************************************************************************/ +/** + \defgroup CMSIS_core_register Defines and Type Definitions + \brief Type definitions and defines for Cortex-M processor based devices. +*/ + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_CORE Status and Control Registers + \brief Core Register type definitions. + @{ + */ + +/** + \brief Union type to access the Application Program Status Register (APSR). + */ +typedef union +{ + struct + { + uint32_t _reserved0: 27; /*!< bit: 0..26 Reserved */ + uint32_t Q: 1; /*!< bit: 27 Saturation condition flag */ + uint32_t V: 1; /*!< bit: 28 Overflow condition code flag */ + uint32_t C: 1; /*!< bit: 29 Carry condition code flag */ + uint32_t Z: 1; /*!< bit: 30 Zero condition code flag */ + uint32_t N: 1; /*!< bit: 31 Negative condition code flag */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} APSR_Type; + +/* APSR Register Definitions */ +#define APSR_N_Pos 31U /*!< APSR: N Position */ +#define APSR_N_Msk (1UL << APSR_N_Pos) /*!< APSR: N Mask */ + +#define APSR_Z_Pos 30U /*!< APSR: Z Position */ +#define APSR_Z_Msk (1UL << APSR_Z_Pos) /*!< APSR: Z Mask */ + +#define APSR_C_Pos 29U /*!< APSR: C Position */ +#define APSR_C_Msk (1UL << APSR_C_Pos) /*!< APSR: C Mask */ + +#define APSR_V_Pos 28U /*!< APSR: V Position */ +#define APSR_V_Msk (1UL << APSR_V_Pos) /*!< APSR: V Mask */ + +#define APSR_Q_Pos 27U /*!< APSR: Q Position */ +#define APSR_Q_Msk (1UL << APSR_Q_Pos) /*!< APSR: Q Mask */ + + +/** + \brief Union type to access the Interrupt Program Status Register (IPSR). + */ +typedef union +{ + struct + { + uint32_t ISR: 9; /*!< bit: 0.. 8 Exception number */ + uint32_t _reserved0: 23; /*!< bit: 9..31 Reserved */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} IPSR_Type; + +/* IPSR Register Definitions */ +#define IPSR_ISR_Pos 0U /*!< IPSR: ISR Position */ +#define IPSR_ISR_Msk (0x1FFUL /*<< IPSR_ISR_Pos*/) /*!< IPSR: ISR Mask */ + + +/** + \brief Union type to access the Special-Purpose Program Status Registers (xPSR). + */ +typedef union +{ + struct + { + uint32_t ISR: 9; /*!< bit: 0.. 8 Exception number */ + uint32_t _reserved0: 15; /*!< bit: 9..23 Reserved */ + uint32_t T: 1; /*!< bit: 24 Thumb bit (read 0) */ + uint32_t IT: 2; /*!< bit: 25..26 saved IT state (read 0) */ + uint32_t Q: 1; /*!< bit: 27 Saturation condition flag */ + uint32_t V: 1; /*!< bit: 28 Overflow condition code flag */ + uint32_t C: 1; /*!< bit: 29 Carry condition code flag */ + uint32_t Z: 1; /*!< bit: 30 Zero condition code flag */ + uint32_t N: 1; /*!< bit: 31 Negative condition code flag */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} xPSR_Type; + +/* xPSR Register Definitions */ +#define xPSR_N_Pos 31U /*!< xPSR: N Position */ +#define xPSR_N_Msk (1UL << xPSR_N_Pos) /*!< xPSR: N Mask */ + +#define xPSR_Z_Pos 30U /*!< xPSR: Z Position */ +#define xPSR_Z_Msk (1UL << xPSR_Z_Pos) /*!< xPSR: Z Mask */ + +#define xPSR_C_Pos 29U /*!< xPSR: C Position */ +#define xPSR_C_Msk (1UL << xPSR_C_Pos) /*!< xPSR: C Mask */ + +#define xPSR_V_Pos 28U /*!< xPSR: V Position */ +#define xPSR_V_Msk (1UL << xPSR_V_Pos) /*!< xPSR: V Mask */ + +#define xPSR_Q_Pos 27U /*!< xPSR: Q Position */ +#define xPSR_Q_Msk (1UL << xPSR_Q_Pos) /*!< xPSR: Q Mask */ + +#define xPSR_IT_Pos 25U /*!< xPSR: IT Position */ +#define xPSR_IT_Msk (3UL << xPSR_IT_Pos) /*!< xPSR: IT Mask */ + +#define xPSR_T_Pos 24U /*!< xPSR: T Position */ +#define xPSR_T_Msk (1UL << xPSR_T_Pos) /*!< xPSR: T Mask */ + +#define xPSR_ISR_Pos 0U /*!< xPSR: ISR Position */ +#define xPSR_ISR_Msk (0x1FFUL /*<< xPSR_ISR_Pos*/) /*!< xPSR: ISR Mask */ + + +/** + \brief Union type to access the Control Registers (CONTROL). + */ +typedef union +{ + struct + { + uint32_t nPRIV: 1; /*!< bit: 0 Execution privilege in Thread mode */ + uint32_t SPSEL: 1; /*!< bit: 1 Stack to be used */ + uint32_t _reserved1: 30; /*!< bit: 2..31 Reserved */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} CONTROL_Type; + +/* CONTROL Register Definitions */ +#define CONTROL_SPSEL_Pos 1U /*!< CONTROL: SPSEL Position */ +#define CONTROL_SPSEL_Msk (1UL << CONTROL_SPSEL_Pos) /*!< CONTROL: SPSEL Mask */ + +#define CONTROL_nPRIV_Pos 0U /*!< CONTROL: nPRIV Position */ +#define CONTROL_nPRIV_Msk (1UL /*<< CONTROL_nPRIV_Pos*/) /*!< CONTROL: nPRIV Mask */ + +/*@} end of group CMSIS_CORE */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC) + \brief Type definitions for the NVIC Registers + @{ + */ + +/** + \brief Structure type to access the Nested Vectored Interrupt Controller (NVIC). + */ +typedef struct +{ + __IOM uint32_t ISER[8U]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */ + uint32_t RESERVED0[24U]; + __IOM uint32_t ICER[8U]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */ + uint32_t RSERVED1[24U]; + __IOM uint32_t ISPR[8U]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */ + uint32_t RESERVED2[24U]; + __IOM uint32_t ICPR[8U]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register */ + uint32_t RESERVED3[24U]; + __IOM uint32_t IABR[8U]; /*!< Offset: 0x200 (R/W) Interrupt Active bit Register */ + uint32_t RESERVED4[56U]; + __IOM uint8_t IP[240U]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register (8Bit wide) */ + uint32_t RESERVED5[644U]; + __OM uint32_t STIR; /*!< Offset: 0xE00 ( /W) Software Trigger Interrupt Register */ +} NVIC_Type; + +/* Software Triggered Interrupt Register Definitions */ +#define NVIC_STIR_INTID_Pos 0U /*!< STIR: INTLINESNUM Position */ +#define NVIC_STIR_INTID_Msk (0x1FFUL /*<< NVIC_STIR_INTID_Pos*/) /*!< STIR: INTLINESNUM Mask */ + +/*@} end of group CMSIS_NVIC */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SCB System Control Block (SCB) + \brief Type definitions for the System Control Block Registers + @{ + */ + +/** + \brief Structure type to access the System Control Block (SCB). + */ +typedef struct +{ + __IM uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */ + __IOM uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Register */ + __IOM uint32_t VTOR; /*!< Offset: 0x008 (R/W) Vector Table Offset Register */ + __IOM uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register */ + __IOM uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */ + __IOM uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */ + __IOM uint8_t SHP[12U]; /*!< Offset: 0x018 (R/W) System Handlers Priority Registers (4-7, 8-11, 12-15) */ + __IOM uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State Register */ + __IOM uint32_t CFSR; /*!< Offset: 0x028 (R/W) Configurable Fault Status Register */ + __IOM uint32_t HFSR; /*!< Offset: 0x02C (R/W) HardFault Status Register */ + __IOM uint32_t DFSR; /*!< Offset: 0x030 (R/W) Debug Fault Status Register */ + __IOM uint32_t MMFAR; /*!< Offset: 0x034 (R/W) MemManage Fault Address Register */ + __IOM uint32_t BFAR; /*!< Offset: 0x038 (R/W) BusFault Address Register */ + __IOM uint32_t AFSR; /*!< Offset: 0x03C (R/W) Auxiliary Fault Status Register */ + __IM uint32_t PFR[2U]; /*!< Offset: 0x040 (R/ ) Processor Feature Register */ + __IM uint32_t DFR; /*!< Offset: 0x048 (R/ ) Debug Feature Register */ + __IM uint32_t ADR; /*!< Offset: 0x04C (R/ ) Auxiliary Feature Register */ + __IM uint32_t MMFR[4U]; /*!< Offset: 0x050 (R/ ) Memory Model Feature Register */ + __IM uint32_t ISAR[5U]; /*!< Offset: 0x060 (R/ ) Instruction Set Attributes Register */ + uint32_t RESERVED0[5U]; + __IOM uint32_t CPACR; /*!< Offset: 0x088 (R/W) Coprocessor Access Control Register */ + uint32_t RESERVED1[129U]; + __IOM uint32_t SFCR; /*!< Offset: 0x290 (R/W) Security Features Control Register */ +} SCB_Type; + +/* SCB CPUID Register Definitions */ +#define SCB_CPUID_IMPLEMENTER_Pos 24U /*!< SCB CPUID: IMPLEMENTER Position */ +#define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */ + +#define SCB_CPUID_VARIANT_Pos 20U /*!< SCB CPUID: VARIANT Position */ +#define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */ + +#define SCB_CPUID_ARCHITECTURE_Pos 16U /*!< SCB CPUID: ARCHITECTURE Position */ +#define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB CPUID: ARCHITECTURE Mask */ + +#define SCB_CPUID_PARTNO_Pos 4U /*!< SCB CPUID: PARTNO Position */ +#define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */ + +#define SCB_CPUID_REVISION_Pos 0U /*!< SCB CPUID: REVISION Position */ +#define SCB_CPUID_REVISION_Msk (0xFUL /*<< SCB_CPUID_REVISION_Pos*/) /*!< SCB CPUID: REVISION Mask */ + +/* SCB Interrupt Control State Register Definitions */ +#define SCB_ICSR_NMIPENDSET_Pos 31U /*!< SCB ICSR: NMIPENDSET Position */ +#define SCB_ICSR_NMIPENDSET_Msk (1UL << SCB_ICSR_NMIPENDSET_Pos) /*!< SCB ICSR: NMIPENDSET Mask */ + +#define SCB_ICSR_PENDSVSET_Pos 28U /*!< SCB ICSR: PENDSVSET Position */ +#define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */ + +#define SCB_ICSR_PENDSVCLR_Pos 27U /*!< SCB ICSR: PENDSVCLR Position */ +#define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */ + +#define SCB_ICSR_PENDSTSET_Pos 26U /*!< SCB ICSR: PENDSTSET Position */ +#define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */ + +#define SCB_ICSR_PENDSTCLR_Pos 25U /*!< SCB ICSR: PENDSTCLR Position */ +#define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */ + +#define SCB_ICSR_ISRPREEMPT_Pos 23U /*!< SCB ICSR: ISRPREEMPT Position */ +#define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */ + +#define SCB_ICSR_ISRPENDING_Pos 22U /*!< SCB ICSR: ISRPENDING Position */ +#define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */ + +#define SCB_ICSR_VECTPENDING_Pos 12U /*!< SCB ICSR: VECTPENDING Position */ +#define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */ + +#define SCB_ICSR_RETTOBASE_Pos 11U /*!< SCB ICSR: RETTOBASE Position */ +#define SCB_ICSR_RETTOBASE_Msk (1UL << SCB_ICSR_RETTOBASE_Pos) /*!< SCB ICSR: RETTOBASE Mask */ + +#define SCB_ICSR_VECTACTIVE_Pos 0U /*!< SCB ICSR: VECTACTIVE Position */ +#define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/) /*!< SCB ICSR: VECTACTIVE Mask */ + +/* SCB Vector Table Offset Register Definitions */ +#define SCB_VTOR_TBLBASE_Pos 29U /*!< SCB VTOR: TBLBASE Position */ +#define SCB_VTOR_TBLBASE_Msk (1UL << SCB_VTOR_TBLBASE_Pos) /*!< SCB VTOR: TBLBASE Mask */ + +#define SCB_VTOR_TBLOFF_Pos 7U /*!< SCB VTOR: TBLOFF Position */ +#define SCB_VTOR_TBLOFF_Msk (0x3FFFFFUL << SCB_VTOR_TBLOFF_Pos) /*!< SCB VTOR: TBLOFF Mask */ + +/* SCB Application Interrupt and Reset Control Register Definitions */ +#define SCB_AIRCR_VECTKEY_Pos 16U /*!< SCB AIRCR: VECTKEY Position */ +#define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */ + +#define SCB_AIRCR_VECTKEYSTAT_Pos 16U /*!< SCB AIRCR: VECTKEYSTAT Position */ +#define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */ + +#define SCB_AIRCR_ENDIANESS_Pos 15U /*!< SCB AIRCR: ENDIANESS Position */ +#define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /*!< SCB AIRCR: ENDIANESS Mask */ + +#define SCB_AIRCR_PRIGROUP_Pos 8U /*!< SCB AIRCR: PRIGROUP Position */ +#define SCB_AIRCR_PRIGROUP_Msk (7UL << SCB_AIRCR_PRIGROUP_Pos) /*!< SCB AIRCR: PRIGROUP Mask */ + +#define SCB_AIRCR_SYSRESETREQ_Pos 2U /*!< SCB AIRCR: SYSRESETREQ Position */ +#define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */ + +#define SCB_AIRCR_VECTCLRACTIVE_Pos 1U /*!< SCB AIRCR: VECTCLRACTIVE Position */ +#define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */ + +#define SCB_AIRCR_VECTRESET_Pos 0U /*!< SCB AIRCR: VECTRESET Position */ +#define SCB_AIRCR_VECTRESET_Msk (1UL /*<< SCB_AIRCR_VECTRESET_Pos*/) /*!< SCB AIRCR: VECTRESET Mask */ + +/* SCB System Control Register Definitions */ +#define SCB_SCR_SEVONPEND_Pos 4U /*!< SCB SCR: SEVONPEND Position */ +#define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */ + +#define SCB_SCR_SLEEPDEEP_Pos 2U /*!< SCB SCR: SLEEPDEEP Position */ +#define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */ + +#define SCB_SCR_SLEEPONEXIT_Pos 1U /*!< SCB SCR: SLEEPONEXIT Position */ +#define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */ + +/* SCB Configuration Control Register Definitions */ +#define SCB_CCR_STKALIGN_Pos 9U /*!< SCB CCR: STKALIGN Position */ +#define SCB_CCR_STKALIGN_Msk (1UL << SCB_CCR_STKALIGN_Pos) /*!< SCB CCR: STKALIGN Mask */ + +#define SCB_CCR_BFHFNMIGN_Pos 8U /*!< SCB CCR: BFHFNMIGN Position */ +#define SCB_CCR_BFHFNMIGN_Msk (1UL << SCB_CCR_BFHFNMIGN_Pos) /*!< SCB CCR: BFHFNMIGN Mask */ + +#define SCB_CCR_DIV_0_TRP_Pos 4U /*!< SCB CCR: DIV_0_TRP Position */ +#define SCB_CCR_DIV_0_TRP_Msk (1UL << SCB_CCR_DIV_0_TRP_Pos) /*!< SCB CCR: DIV_0_TRP Mask */ + +#define SCB_CCR_UNALIGN_TRP_Pos 3U /*!< SCB CCR: UNALIGN_TRP Position */ +#define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */ + +#define SCB_CCR_USERSETMPEND_Pos 1U /*!< SCB CCR: USERSETMPEND Position */ +#define SCB_CCR_USERSETMPEND_Msk (1UL << SCB_CCR_USERSETMPEND_Pos) /*!< SCB CCR: USERSETMPEND Mask */ + +#define SCB_CCR_NONBASETHRDENA_Pos 0U /*!< SCB CCR: NONBASETHRDENA Position */ +#define SCB_CCR_NONBASETHRDENA_Msk (1UL /*<< SCB_CCR_NONBASETHRDENA_Pos*/) /*!< SCB CCR: NONBASETHRDENA Mask */ + +/* SCB System Handler Control and State Register Definitions */ +#define SCB_SHCSR_USGFAULTENA_Pos 18U /*!< SCB SHCSR: USGFAULTENA Position */ +#define SCB_SHCSR_USGFAULTENA_Msk (1UL << SCB_SHCSR_USGFAULTENA_Pos) /*!< SCB SHCSR: USGFAULTENA Mask */ + +#define SCB_SHCSR_BUSFAULTENA_Pos 17U /*!< SCB SHCSR: BUSFAULTENA Position */ +#define SCB_SHCSR_BUSFAULTENA_Msk (1UL << SCB_SHCSR_BUSFAULTENA_Pos) /*!< SCB SHCSR: BUSFAULTENA Mask */ + +#define SCB_SHCSR_MEMFAULTENA_Pos 16U /*!< SCB SHCSR: MEMFAULTENA Position */ +#define SCB_SHCSR_MEMFAULTENA_Msk (1UL << SCB_SHCSR_MEMFAULTENA_Pos) /*!< SCB SHCSR: MEMFAULTENA Mask */ + +#define SCB_SHCSR_SVCALLPENDED_Pos 15U /*!< SCB SHCSR: SVCALLPENDED Position */ +#define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */ + +#define SCB_SHCSR_BUSFAULTPENDED_Pos 14U /*!< SCB SHCSR: BUSFAULTPENDED Position */ +#define SCB_SHCSR_BUSFAULTPENDED_Msk (1UL << SCB_SHCSR_BUSFAULTPENDED_Pos) /*!< SCB SHCSR: BUSFAULTPENDED Mask */ + +#define SCB_SHCSR_MEMFAULTPENDED_Pos 13U /*!< SCB SHCSR: MEMFAULTPENDED Position */ +#define SCB_SHCSR_MEMFAULTPENDED_Msk (1UL << SCB_SHCSR_MEMFAULTPENDED_Pos) /*!< SCB SHCSR: MEMFAULTPENDED Mask */ + +#define SCB_SHCSR_USGFAULTPENDED_Pos 12U /*!< SCB SHCSR: USGFAULTPENDED Position */ +#define SCB_SHCSR_USGFAULTPENDED_Msk (1UL << SCB_SHCSR_USGFAULTPENDED_Pos) /*!< SCB SHCSR: USGFAULTPENDED Mask */ + +#define SCB_SHCSR_SYSTICKACT_Pos 11U /*!< SCB SHCSR: SYSTICKACT Position */ +#define SCB_SHCSR_SYSTICKACT_Msk (1UL << SCB_SHCSR_SYSTICKACT_Pos) /*!< SCB SHCSR: SYSTICKACT Mask */ + +#define SCB_SHCSR_PENDSVACT_Pos 10U /*!< SCB SHCSR: PENDSVACT Position */ +#define SCB_SHCSR_PENDSVACT_Msk (1UL << SCB_SHCSR_PENDSVACT_Pos) /*!< SCB SHCSR: PENDSVACT Mask */ + +#define SCB_SHCSR_MONITORACT_Pos 8U /*!< SCB SHCSR: MONITORACT Position */ +#define SCB_SHCSR_MONITORACT_Msk (1UL << SCB_SHCSR_MONITORACT_Pos) /*!< SCB SHCSR: MONITORACT Mask */ + +#define SCB_SHCSR_SVCALLACT_Pos 7U /*!< SCB SHCSR: SVCALLACT Position */ +#define SCB_SHCSR_SVCALLACT_Msk (1UL << SCB_SHCSR_SVCALLACT_Pos) /*!< SCB SHCSR: SVCALLACT Mask */ + +#define SCB_SHCSR_USGFAULTACT_Pos 3U /*!< SCB SHCSR: USGFAULTACT Position */ +#define SCB_SHCSR_USGFAULTACT_Msk (1UL << SCB_SHCSR_USGFAULTACT_Pos) /*!< SCB SHCSR: USGFAULTACT Mask */ + +#define SCB_SHCSR_BUSFAULTACT_Pos 1U /*!< SCB SHCSR: BUSFAULTACT Position */ +#define SCB_SHCSR_BUSFAULTACT_Msk (1UL << SCB_SHCSR_BUSFAULTACT_Pos) /*!< SCB SHCSR: BUSFAULTACT Mask */ + +#define SCB_SHCSR_MEMFAULTACT_Pos 0U /*!< SCB SHCSR: MEMFAULTACT Position */ +#define SCB_SHCSR_MEMFAULTACT_Msk (1UL /*<< SCB_SHCSR_MEMFAULTACT_Pos*/) /*!< SCB SHCSR: MEMFAULTACT Mask */ + +/* SCB Configurable Fault Status Register Definitions */ +#define SCB_CFSR_USGFAULTSR_Pos 16U /*!< SCB CFSR: Usage Fault Status Register Position */ +#define SCB_CFSR_USGFAULTSR_Msk (0xFFFFUL << SCB_CFSR_USGFAULTSR_Pos) /*!< SCB CFSR: Usage Fault Status Register Mask */ + +#define SCB_CFSR_BUSFAULTSR_Pos 8U /*!< SCB CFSR: Bus Fault Status Register Position */ +#define SCB_CFSR_BUSFAULTSR_Msk (0xFFUL << SCB_CFSR_BUSFAULTSR_Pos) /*!< SCB CFSR: Bus Fault Status Register Mask */ + +#define SCB_CFSR_MEMFAULTSR_Pos 0U /*!< SCB CFSR: Memory Manage Fault Status Register Position */ +#define SCB_CFSR_MEMFAULTSR_Msk (0xFFUL /*<< SCB_CFSR_MEMFAULTSR_Pos*/) /*!< SCB CFSR: Memory Manage Fault Status Register Mask */ + +/* SCB Hard Fault Status Register Definitions */ +#define SCB_HFSR_DEBUGEVT_Pos 31U /*!< SCB HFSR: DEBUGEVT Position */ +#define SCB_HFSR_DEBUGEVT_Msk (1UL << SCB_HFSR_DEBUGEVT_Pos) /*!< SCB HFSR: DEBUGEVT Mask */ + +#define SCB_HFSR_FORCED_Pos 30U /*!< SCB HFSR: FORCED Position */ +#define SCB_HFSR_FORCED_Msk (1UL << SCB_HFSR_FORCED_Pos) /*!< SCB HFSR: FORCED Mask */ + +#define SCB_HFSR_VECTTBL_Pos 1U /*!< SCB HFSR: VECTTBL Position */ +#define SCB_HFSR_VECTTBL_Msk (1UL << SCB_HFSR_VECTTBL_Pos) /*!< SCB HFSR: VECTTBL Mask */ + +/* SCB Debug Fault Status Register Definitions */ +#define SCB_DFSR_EXTERNAL_Pos 4U /*!< SCB DFSR: EXTERNAL Position */ +#define SCB_DFSR_EXTERNAL_Msk (1UL << SCB_DFSR_EXTERNAL_Pos) /*!< SCB DFSR: EXTERNAL Mask */ + +#define SCB_DFSR_VCATCH_Pos 3U /*!< SCB DFSR: VCATCH Position */ +#define SCB_DFSR_VCATCH_Msk (1UL << SCB_DFSR_VCATCH_Pos) /*!< SCB DFSR: VCATCH Mask */ + +#define SCB_DFSR_DWTTRAP_Pos 2U /*!< SCB DFSR: DWTTRAP Position */ +#define SCB_DFSR_DWTTRAP_Msk (1UL << SCB_DFSR_DWTTRAP_Pos) /*!< SCB DFSR: DWTTRAP Mask */ + +#define SCB_DFSR_BKPT_Pos 1U /*!< SCB DFSR: BKPT Position */ +#define SCB_DFSR_BKPT_Msk (1UL << SCB_DFSR_BKPT_Pos) /*!< SCB DFSR: BKPT Mask */ + +#define SCB_DFSR_HALTED_Pos 0U /*!< SCB DFSR: HALTED Position */ +#define SCB_DFSR_HALTED_Msk (1UL /*<< SCB_DFSR_HALTED_Pos*/) /*!< SCB DFSR: HALTED Mask */ + +/*@} end of group CMSIS_SCB */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SCnSCB System Controls not in SCB (SCnSCB) + \brief Type definitions for the System Control and ID Register not in the SCB + @{ + */ + +/** + \brief Structure type to access the System Control and ID Register not in the SCB. + */ +typedef struct +{ + uint32_t RESERVED0[1U]; + __IM uint32_t ICTR; /*!< Offset: 0x004 (R/ ) Interrupt Controller Type Register */ + uint32_t RESERVED1[1U]; +} SCnSCB_Type; + +/* Interrupt Controller Type Register Definitions */ +#define SCnSCB_ICTR_INTLINESNUM_Pos 0U /*!< ICTR: INTLINESNUM Position */ +#define SCnSCB_ICTR_INTLINESNUM_Msk (0xFUL /*<< SCnSCB_ICTR_INTLINESNUM_Pos*/) /*!< ICTR: INTLINESNUM Mask */ + +/*@} end of group CMSIS_SCnotSCB */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SysTick System Tick Timer (SysTick) + \brief Type definitions for the System Timer Registers. + @{ + */ + +/** + \brief Structure type to access the System Timer (SysTick). + */ +typedef struct +{ + __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */ + __IOM uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */ + __IOM uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register */ + __IM uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */ +} SysTick_Type; + +/* SysTick Control / Status Register Definitions */ +#define SysTick_CTRL_COUNTFLAG_Pos 16U /*!< SysTick CTRL: COUNTFLAG Position */ +#define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */ + +#define SysTick_CTRL_CLKSOURCE_Pos 2U /*!< SysTick CTRL: CLKSOURCE Position */ +#define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */ + +#define SysTick_CTRL_TICKINT_Pos 1U /*!< SysTick CTRL: TICKINT Position */ +#define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */ + +#define SysTick_CTRL_ENABLE_Pos 0U /*!< SysTick CTRL: ENABLE Position */ +#define SysTick_CTRL_ENABLE_Msk (1UL /*<< SysTick_CTRL_ENABLE_Pos*/) /*!< SysTick CTRL: ENABLE Mask */ + +/* SysTick Reload Register Definitions */ +#define SysTick_LOAD_RELOAD_Pos 0U /*!< SysTick LOAD: RELOAD Position */ +#define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/) /*!< SysTick LOAD: RELOAD Mask */ + +/* SysTick Current Register Definitions */ +#define SysTick_VAL_CURRENT_Pos 0U /*!< SysTick VAL: CURRENT Position */ +#define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/) /*!< SysTick VAL: CURRENT Mask */ + +/* SysTick Calibration Register Definitions */ +#define SysTick_CALIB_NOREF_Pos 31U /*!< SysTick CALIB: NOREF Position */ +#define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */ + +#define SysTick_CALIB_SKEW_Pos 30U /*!< SysTick CALIB: SKEW Position */ +#define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */ + +#define SysTick_CALIB_TENMS_Pos 0U /*!< SysTick CALIB: TENMS Position */ +#define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/) /*!< SysTick CALIB: TENMS Mask */ + +/*@} end of group CMSIS_SysTick */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_ITM Instrumentation Trace Macrocell (ITM) + \brief Type definitions for the Instrumentation Trace Macrocell (ITM) + @{ + */ + +/** + \brief Structure type to access the Instrumentation Trace Macrocell Register (ITM). + */ +typedef struct +{ + __OM union + { + __OM uint8_t u8; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 8-bit */ + __OM uint16_t u16; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 16-bit */ + __OM uint32_t u32; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 32-bit */ + } PORT [32U]; /*!< Offset: 0x000 ( /W) ITM Stimulus Port Registers */ + uint32_t RESERVED0[864U]; + __IOM uint32_t TER; /*!< Offset: 0xE00 (R/W) ITM Trace Enable Register */ + uint32_t RESERVED1[15U]; + __IOM uint32_t TPR; /*!< Offset: 0xE40 (R/W) ITM Trace Privilege Register */ + uint32_t RESERVED2[15U]; + __IOM uint32_t TCR; /*!< Offset: 0xE80 (R/W) ITM Trace Control Register */ + uint32_t RESERVED3[29U]; + __OM uint32_t IWR; /*!< Offset: 0xEF8 ( /W) ITM Integration Write Register */ + __IM uint32_t IRR; /*!< Offset: 0xEFC (R/ ) ITM Integration Read Register */ + __IOM uint32_t IMCR; /*!< Offset: 0xF00 (R/W) ITM Integration Mode Control Register */ + uint32_t RESERVED4[43U]; + __OM uint32_t LAR; /*!< Offset: 0xFB0 ( /W) ITM Lock Access Register */ + __IM uint32_t LSR; /*!< Offset: 0xFB4 (R/ ) ITM Lock Status Register */ + uint32_t RESERVED5[6U]; + __IM uint32_t PID4; /*!< Offset: 0xFD0 (R/ ) ITM Peripheral Identification Register #4 */ + __IM uint32_t PID5; /*!< Offset: 0xFD4 (R/ ) ITM Peripheral Identification Register #5 */ + __IM uint32_t PID6; /*!< Offset: 0xFD8 (R/ ) ITM Peripheral Identification Register #6 */ + __IM uint32_t PID7; /*!< Offset: 0xFDC (R/ ) ITM Peripheral Identification Register #7 */ + __IM uint32_t PID0; /*!< Offset: 0xFE0 (R/ ) ITM Peripheral Identification Register #0 */ + __IM uint32_t PID1; /*!< Offset: 0xFE4 (R/ ) ITM Peripheral Identification Register #1 */ + __IM uint32_t PID2; /*!< Offset: 0xFE8 (R/ ) ITM Peripheral Identification Register #2 */ + __IM uint32_t PID3; /*!< Offset: 0xFEC (R/ ) ITM Peripheral Identification Register #3 */ + __IM uint32_t CID0; /*!< Offset: 0xFF0 (R/ ) ITM Component Identification Register #0 */ + __IM uint32_t CID1; /*!< Offset: 0xFF4 (R/ ) ITM Component Identification Register #1 */ + __IM uint32_t CID2; /*!< Offset: 0xFF8 (R/ ) ITM Component Identification Register #2 */ + __IM uint32_t CID3; /*!< Offset: 0xFFC (R/ ) ITM Component Identification Register #3 */ +} ITM_Type; + +/* ITM Trace Privilege Register Definitions */ +#define ITM_TPR_PRIVMASK_Pos 0U /*!< ITM TPR: PRIVMASK Position */ +#define ITM_TPR_PRIVMASK_Msk (0xFUL /*<< ITM_TPR_PRIVMASK_Pos*/) /*!< ITM TPR: PRIVMASK Mask */ + +/* ITM Trace Control Register Definitions */ +#define ITM_TCR_BUSY_Pos 23U /*!< ITM TCR: BUSY Position */ +#define ITM_TCR_BUSY_Msk (1UL << ITM_TCR_BUSY_Pos) /*!< ITM TCR: BUSY Mask */ + +#define ITM_TCR_TraceBusID_Pos 16U /*!< ITM TCR: ATBID Position */ +#define ITM_TCR_TraceBusID_Msk (0x7FUL << ITM_TCR_TraceBusID_Pos) /*!< ITM TCR: ATBID Mask */ + +#define ITM_TCR_GTSFREQ_Pos 10U /*!< ITM TCR: Global timestamp frequency Position */ +#define ITM_TCR_GTSFREQ_Msk (3UL << ITM_TCR_GTSFREQ_Pos) /*!< ITM TCR: Global timestamp frequency Mask */ + +#define ITM_TCR_TSPrescale_Pos 8U /*!< ITM TCR: TSPrescale Position */ +#define ITM_TCR_TSPrescale_Msk (3UL << ITM_TCR_TSPrescale_Pos) /*!< ITM TCR: TSPrescale Mask */ + +#define ITM_TCR_SWOENA_Pos 4U /*!< ITM TCR: SWOENA Position */ +#define ITM_TCR_SWOENA_Msk (1UL << ITM_TCR_SWOENA_Pos) /*!< ITM TCR: SWOENA Mask */ + +#define ITM_TCR_DWTENA_Pos 3U /*!< ITM TCR: DWTENA Position */ +#define ITM_TCR_DWTENA_Msk (1UL << ITM_TCR_DWTENA_Pos) /*!< ITM TCR: DWTENA Mask */ + +#define ITM_TCR_SYNCENA_Pos 2U /*!< ITM TCR: SYNCENA Position */ +#define ITM_TCR_SYNCENA_Msk (1UL << ITM_TCR_SYNCENA_Pos) /*!< ITM TCR: SYNCENA Mask */ + +#define ITM_TCR_TSENA_Pos 1U /*!< ITM TCR: TSENA Position */ +#define ITM_TCR_TSENA_Msk (1UL << ITM_TCR_TSENA_Pos) /*!< ITM TCR: TSENA Mask */ + +#define ITM_TCR_ITMENA_Pos 0U /*!< ITM TCR: ITM Enable bit Position */ +#define ITM_TCR_ITMENA_Msk (1UL /*<< ITM_TCR_ITMENA_Pos*/) /*!< ITM TCR: ITM Enable bit Mask */ + +/* ITM Integration Write Register Definitions */ +#define ITM_IWR_ATVALIDM_Pos 0U /*!< ITM IWR: ATVALIDM Position */ +#define ITM_IWR_ATVALIDM_Msk (1UL /*<< ITM_IWR_ATVALIDM_Pos*/) /*!< ITM IWR: ATVALIDM Mask */ + +/* ITM Integration Read Register Definitions */ +#define ITM_IRR_ATREADYM_Pos 0U /*!< ITM IRR: ATREADYM Position */ +#define ITM_IRR_ATREADYM_Msk (1UL /*<< ITM_IRR_ATREADYM_Pos*/) /*!< ITM IRR: ATREADYM Mask */ + +/* ITM Integration Mode Control Register Definitions */ +#define ITM_IMCR_INTEGRATION_Pos 0U /*!< ITM IMCR: INTEGRATION Position */ +#define ITM_IMCR_INTEGRATION_Msk (1UL /*<< ITM_IMCR_INTEGRATION_Pos*/) /*!< ITM IMCR: INTEGRATION Mask */ + +/* ITM Lock Status Register Definitions */ +#define ITM_LSR_ByteAcc_Pos 2U /*!< ITM LSR: ByteAcc Position */ +#define ITM_LSR_ByteAcc_Msk (1UL << ITM_LSR_ByteAcc_Pos) /*!< ITM LSR: ByteAcc Mask */ + +#define ITM_LSR_Access_Pos 1U /*!< ITM LSR: Access Position */ +#define ITM_LSR_Access_Msk (1UL << ITM_LSR_Access_Pos) /*!< ITM LSR: Access Mask */ + +#define ITM_LSR_Present_Pos 0U /*!< ITM LSR: Present Position */ +#define ITM_LSR_Present_Msk (1UL /*<< ITM_LSR_Present_Pos*/) /*!< ITM LSR: Present Mask */ + +/*@}*/ /* end of group CMSIS_ITM */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_DWT Data Watchpoint and Trace (DWT) + \brief Type definitions for the Data Watchpoint and Trace (DWT) + @{ + */ + +/** + \brief Structure type to access the Data Watchpoint and Trace Register (DWT). + */ +typedef struct +{ + __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) Control Register */ + __IOM uint32_t CYCCNT; /*!< Offset: 0x004 (R/W) Cycle Count Register */ + __IOM uint32_t CPICNT; /*!< Offset: 0x008 (R/W) CPI Count Register */ + __IOM uint32_t EXCCNT; /*!< Offset: 0x00C (R/W) Exception Overhead Count Register */ + __IOM uint32_t SLEEPCNT; /*!< Offset: 0x010 (R/W) Sleep Count Register */ + __IOM uint32_t LSUCNT; /*!< Offset: 0x014 (R/W) LSU Count Register */ + __IOM uint32_t FOLDCNT; /*!< Offset: 0x018 (R/W) Folded-instruction Count Register */ + __IM uint32_t PCSR; /*!< Offset: 0x01C (R/ ) Program Counter Sample Register */ + __IOM uint32_t COMP0; /*!< Offset: 0x020 (R/W) Comparator Register 0 */ + __IOM uint32_t MASK0; /*!< Offset: 0x024 (R/W) Mask Register 0 */ + __IOM uint32_t FUNCTION0; /*!< Offset: 0x028 (R/W) Function Register 0 */ + uint32_t RESERVED0[1U]; + __IOM uint32_t COMP1; /*!< Offset: 0x030 (R/W) Comparator Register 1 */ + __IOM uint32_t MASK1; /*!< Offset: 0x034 (R/W) Mask Register 1 */ + __IOM uint32_t FUNCTION1; /*!< Offset: 0x038 (R/W) Function Register 1 */ + uint32_t RESERVED1[1U]; + __IOM uint32_t COMP2; /*!< Offset: 0x040 (R/W) Comparator Register 2 */ + __IOM uint32_t MASK2; /*!< Offset: 0x044 (R/W) Mask Register 2 */ + __IOM uint32_t FUNCTION2; /*!< Offset: 0x048 (R/W) Function Register 2 */ + uint32_t RESERVED2[1U]; + __IOM uint32_t COMP3; /*!< Offset: 0x050 (R/W) Comparator Register 3 */ + __IOM uint32_t MASK3; /*!< Offset: 0x054 (R/W) Mask Register 3 */ + __IOM uint32_t FUNCTION3; /*!< Offset: 0x058 (R/W) Function Register 3 */ +} DWT_Type; + +/* DWT Control Register Definitions */ +#define DWT_CTRL_NUMCOMP_Pos 28U /*!< DWT CTRL: NUMCOMP Position */ +#define DWT_CTRL_NUMCOMP_Msk (0xFUL << DWT_CTRL_NUMCOMP_Pos) /*!< DWT CTRL: NUMCOMP Mask */ + +#define DWT_CTRL_NOTRCPKT_Pos 27U /*!< DWT CTRL: NOTRCPKT Position */ +#define DWT_CTRL_NOTRCPKT_Msk (0x1UL << DWT_CTRL_NOTRCPKT_Pos) /*!< DWT CTRL: NOTRCPKT Mask */ + +#define DWT_CTRL_NOEXTTRIG_Pos 26U /*!< DWT CTRL: NOEXTTRIG Position */ +#define DWT_CTRL_NOEXTTRIG_Msk (0x1UL << DWT_CTRL_NOEXTTRIG_Pos) /*!< DWT CTRL: NOEXTTRIG Mask */ + +#define DWT_CTRL_NOCYCCNT_Pos 25U /*!< DWT CTRL: NOCYCCNT Position */ +#define DWT_CTRL_NOCYCCNT_Msk (0x1UL << DWT_CTRL_NOCYCCNT_Pos) /*!< DWT CTRL: NOCYCCNT Mask */ + +#define DWT_CTRL_NOPRFCNT_Pos 24U /*!< DWT CTRL: NOPRFCNT Position */ +#define DWT_CTRL_NOPRFCNT_Msk (0x1UL << DWT_CTRL_NOPRFCNT_Pos) /*!< DWT CTRL: NOPRFCNT Mask */ + +#define DWT_CTRL_CYCEVTENA_Pos 22U /*!< DWT CTRL: CYCEVTENA Position */ +#define DWT_CTRL_CYCEVTENA_Msk (0x1UL << DWT_CTRL_CYCEVTENA_Pos) /*!< DWT CTRL: CYCEVTENA Mask */ + +#define DWT_CTRL_FOLDEVTENA_Pos 21U /*!< DWT CTRL: FOLDEVTENA Position */ +#define DWT_CTRL_FOLDEVTENA_Msk (0x1UL << DWT_CTRL_FOLDEVTENA_Pos) /*!< DWT CTRL: FOLDEVTENA Mask */ + +#define DWT_CTRL_LSUEVTENA_Pos 20U /*!< DWT CTRL: LSUEVTENA Position */ +#define DWT_CTRL_LSUEVTENA_Msk (0x1UL << DWT_CTRL_LSUEVTENA_Pos) /*!< DWT CTRL: LSUEVTENA Mask */ + +#define DWT_CTRL_SLEEPEVTENA_Pos 19U /*!< DWT CTRL: SLEEPEVTENA Position */ +#define DWT_CTRL_SLEEPEVTENA_Msk (0x1UL << DWT_CTRL_SLEEPEVTENA_Pos) /*!< DWT CTRL: SLEEPEVTENA Mask */ + +#define DWT_CTRL_EXCEVTENA_Pos 18U /*!< DWT CTRL: EXCEVTENA Position */ +#define DWT_CTRL_EXCEVTENA_Msk (0x1UL << DWT_CTRL_EXCEVTENA_Pos) /*!< DWT CTRL: EXCEVTENA Mask */ + +#define DWT_CTRL_CPIEVTENA_Pos 17U /*!< DWT CTRL: CPIEVTENA Position */ +#define DWT_CTRL_CPIEVTENA_Msk (0x1UL << DWT_CTRL_CPIEVTENA_Pos) /*!< DWT CTRL: CPIEVTENA Mask */ + +#define DWT_CTRL_EXCTRCENA_Pos 16U /*!< DWT CTRL: EXCTRCENA Position */ +#define DWT_CTRL_EXCTRCENA_Msk (0x1UL << DWT_CTRL_EXCTRCENA_Pos) /*!< DWT CTRL: EXCTRCENA Mask */ + +#define DWT_CTRL_PCSAMPLENA_Pos 12U /*!< DWT CTRL: PCSAMPLENA Position */ +#define DWT_CTRL_PCSAMPLENA_Msk (0x1UL << DWT_CTRL_PCSAMPLENA_Pos) /*!< DWT CTRL: PCSAMPLENA Mask */ + +#define DWT_CTRL_SYNCTAP_Pos 10U /*!< DWT CTRL: SYNCTAP Position */ +#define DWT_CTRL_SYNCTAP_Msk (0x3UL << DWT_CTRL_SYNCTAP_Pos) /*!< DWT CTRL: SYNCTAP Mask */ + +#define DWT_CTRL_CYCTAP_Pos 9U /*!< DWT CTRL: CYCTAP Position */ +#define DWT_CTRL_CYCTAP_Msk (0x1UL << DWT_CTRL_CYCTAP_Pos) /*!< DWT CTRL: CYCTAP Mask */ + +#define DWT_CTRL_POSTINIT_Pos 5U /*!< DWT CTRL: POSTINIT Position */ +#define DWT_CTRL_POSTINIT_Msk (0xFUL << DWT_CTRL_POSTINIT_Pos) /*!< DWT CTRL: POSTINIT Mask */ + +#define DWT_CTRL_POSTPRESET_Pos 1U /*!< DWT CTRL: POSTPRESET Position */ +#define DWT_CTRL_POSTPRESET_Msk (0xFUL << DWT_CTRL_POSTPRESET_Pos) /*!< DWT CTRL: POSTPRESET Mask */ + +#define DWT_CTRL_CYCCNTENA_Pos 0U /*!< DWT CTRL: CYCCNTENA Position */ +#define DWT_CTRL_CYCCNTENA_Msk (0x1UL /*<< DWT_CTRL_CYCCNTENA_Pos*/) /*!< DWT CTRL: CYCCNTENA Mask */ + +/* DWT CPI Count Register Definitions */ +#define DWT_CPICNT_CPICNT_Pos 0U /*!< DWT CPICNT: CPICNT Position */ +#define DWT_CPICNT_CPICNT_Msk (0xFFUL /*<< DWT_CPICNT_CPICNT_Pos*/) /*!< DWT CPICNT: CPICNT Mask */ + +/* DWT Exception Overhead Count Register Definitions */ +#define DWT_EXCCNT_EXCCNT_Pos 0U /*!< DWT EXCCNT: EXCCNT Position */ +#define DWT_EXCCNT_EXCCNT_Msk (0xFFUL /*<< DWT_EXCCNT_EXCCNT_Pos*/) /*!< DWT EXCCNT: EXCCNT Mask */ + +/* DWT Sleep Count Register Definitions */ +#define DWT_SLEEPCNT_SLEEPCNT_Pos 0U /*!< DWT SLEEPCNT: SLEEPCNT Position */ +#define DWT_SLEEPCNT_SLEEPCNT_Msk (0xFFUL /*<< DWT_SLEEPCNT_SLEEPCNT_Pos*/) /*!< DWT SLEEPCNT: SLEEPCNT Mask */ + +/* DWT LSU Count Register Definitions */ +#define DWT_LSUCNT_LSUCNT_Pos 0U /*!< DWT LSUCNT: LSUCNT Position */ +#define DWT_LSUCNT_LSUCNT_Msk (0xFFUL /*<< DWT_LSUCNT_LSUCNT_Pos*/) /*!< DWT LSUCNT: LSUCNT Mask */ + +/* DWT Folded-instruction Count Register Definitions */ +#define DWT_FOLDCNT_FOLDCNT_Pos 0U /*!< DWT FOLDCNT: FOLDCNT Position */ +#define DWT_FOLDCNT_FOLDCNT_Msk (0xFFUL /*<< DWT_FOLDCNT_FOLDCNT_Pos*/) /*!< DWT FOLDCNT: FOLDCNT Mask */ + +/* DWT Comparator Mask Register Definitions */ +#define DWT_MASK_MASK_Pos 0U /*!< DWT MASK: MASK Position */ +#define DWT_MASK_MASK_Msk (0x1FUL /*<< DWT_MASK_MASK_Pos*/) /*!< DWT MASK: MASK Mask */ + +/* DWT Comparator Function Register Definitions */ +#define DWT_FUNCTION_MATCHED_Pos 24U /*!< DWT FUNCTION: MATCHED Position */ +#define DWT_FUNCTION_MATCHED_Msk (0x1UL << DWT_FUNCTION_MATCHED_Pos) /*!< DWT FUNCTION: MATCHED Mask */ + +#define DWT_FUNCTION_DATAVADDR1_Pos 16U /*!< DWT FUNCTION: DATAVADDR1 Position */ +#define DWT_FUNCTION_DATAVADDR1_Msk (0xFUL << DWT_FUNCTION_DATAVADDR1_Pos) /*!< DWT FUNCTION: DATAVADDR1 Mask */ + +#define DWT_FUNCTION_DATAVADDR0_Pos 12U /*!< DWT FUNCTION: DATAVADDR0 Position */ +#define DWT_FUNCTION_DATAVADDR0_Msk (0xFUL << DWT_FUNCTION_DATAVADDR0_Pos) /*!< DWT FUNCTION: DATAVADDR0 Mask */ + +#define DWT_FUNCTION_DATAVSIZE_Pos 10U /*!< DWT FUNCTION: DATAVSIZE Position */ +#define DWT_FUNCTION_DATAVSIZE_Msk (0x3UL << DWT_FUNCTION_DATAVSIZE_Pos) /*!< DWT FUNCTION: DATAVSIZE Mask */ + +#define DWT_FUNCTION_LNK1ENA_Pos 9U /*!< DWT FUNCTION: LNK1ENA Position */ +#define DWT_FUNCTION_LNK1ENA_Msk (0x1UL << DWT_FUNCTION_LNK1ENA_Pos) /*!< DWT FUNCTION: LNK1ENA Mask */ + +#define DWT_FUNCTION_DATAVMATCH_Pos 8U /*!< DWT FUNCTION: DATAVMATCH Position */ +#define DWT_FUNCTION_DATAVMATCH_Msk (0x1UL << DWT_FUNCTION_DATAVMATCH_Pos) /*!< DWT FUNCTION: DATAVMATCH Mask */ + +#define DWT_FUNCTION_CYCMATCH_Pos 7U /*!< DWT FUNCTION: CYCMATCH Position */ +#define DWT_FUNCTION_CYCMATCH_Msk (0x1UL << DWT_FUNCTION_CYCMATCH_Pos) /*!< DWT FUNCTION: CYCMATCH Mask */ + +#define DWT_FUNCTION_EMITRANGE_Pos 5U /*!< DWT FUNCTION: EMITRANGE Position */ +#define DWT_FUNCTION_EMITRANGE_Msk (0x1UL << DWT_FUNCTION_EMITRANGE_Pos) /*!< DWT FUNCTION: EMITRANGE Mask */ + +#define DWT_FUNCTION_FUNCTION_Pos 0U /*!< DWT FUNCTION: FUNCTION Position */ +#define DWT_FUNCTION_FUNCTION_Msk (0xFUL /*<< DWT_FUNCTION_FUNCTION_Pos*/) /*!< DWT FUNCTION: FUNCTION Mask */ + +/*@}*/ /* end of group CMSIS_DWT */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_TPI Trace Port Interface (TPI) + \brief Type definitions for the Trace Port Interface (TPI) + @{ + */ + +/** + \brief Structure type to access the Trace Port Interface Register (TPI). + */ +typedef struct +{ + __IOM uint32_t SSPSR; /*!< Offset: 0x000 (R/ ) Supported Parallel Port Size Register */ + __IOM uint32_t CSPSR; /*!< Offset: 0x004 (R/W) Current Parallel Port Size Register */ + uint32_t RESERVED0[2U]; + __IOM uint32_t ACPR; /*!< Offset: 0x010 (R/W) Asynchronous Clock Prescaler Register */ + uint32_t RESERVED1[55U]; + __IOM uint32_t SPPR; /*!< Offset: 0x0F0 (R/W) Selected Pin Protocol Register */ + uint32_t RESERVED2[131U]; + __IM uint32_t FFSR; /*!< Offset: 0x300 (R/ ) Formatter and Flush Status Register */ + __IOM uint32_t FFCR; /*!< Offset: 0x304 (R/W) Formatter and Flush Control Register */ + __IM uint32_t FSCR; /*!< Offset: 0x308 (R/ ) Formatter Synchronization Counter Register */ + uint32_t RESERVED3[759U]; + __IM uint32_t TRIGGER; /*!< Offset: 0xEE8 (R/ ) TRIGGER */ + __IM uint32_t FIFO0; /*!< Offset: 0xEEC (R/ ) Integration ETM Data */ + __IM uint32_t ITATBCTR2; /*!< Offset: 0xEF0 (R/ ) ITATBCTR2 */ + uint32_t RESERVED4[1U]; + __IM uint32_t ITATBCTR0; /*!< Offset: 0xEF8 (R/ ) ITATBCTR0 */ + __IM uint32_t FIFO1; /*!< Offset: 0xEFC (R/ ) Integration ITM Data */ + __IOM uint32_t ITCTRL; /*!< Offset: 0xF00 (R/W) Integration Mode Control */ + uint32_t RESERVED5[39U]; + __IOM uint32_t CLAIMSET; /*!< Offset: 0xFA0 (R/W) Claim tag set */ + __IOM uint32_t CLAIMCLR; /*!< Offset: 0xFA4 (R/W) Claim tag clear */ + uint32_t RESERVED7[8U]; + __IM uint32_t DEVID; /*!< Offset: 0xFC8 (R/ ) TPIU_DEVID */ + __IM uint32_t DEVTYPE; /*!< Offset: 0xFCC (R/ ) TPIU_DEVTYPE */ +} TPI_Type; + +/* TPI Asynchronous Clock Prescaler Register Definitions */ +#define TPI_ACPR_PRESCALER_Pos 0U /*!< TPI ACPR: PRESCALER Position */ +#define TPI_ACPR_PRESCALER_Msk (0x1FFFUL /*<< TPI_ACPR_PRESCALER_Pos*/) /*!< TPI ACPR: PRESCALER Mask */ + +/* TPI Selected Pin Protocol Register Definitions */ +#define TPI_SPPR_TXMODE_Pos 0U /*!< TPI SPPR: TXMODE Position */ +#define TPI_SPPR_TXMODE_Msk (0x3UL /*<< TPI_SPPR_TXMODE_Pos*/) /*!< TPI SPPR: TXMODE Mask */ + +/* TPI Formatter and Flush Status Register Definitions */ +#define TPI_FFSR_FtNonStop_Pos 3U /*!< TPI FFSR: FtNonStop Position */ +#define TPI_FFSR_FtNonStop_Msk (0x1UL << TPI_FFSR_FtNonStop_Pos) /*!< TPI FFSR: FtNonStop Mask */ + +#define TPI_FFSR_TCPresent_Pos 2U /*!< TPI FFSR: TCPresent Position */ +#define TPI_FFSR_TCPresent_Msk (0x1UL << TPI_FFSR_TCPresent_Pos) /*!< TPI FFSR: TCPresent Mask */ + +#define TPI_FFSR_FtStopped_Pos 1U /*!< TPI FFSR: FtStopped Position */ +#define TPI_FFSR_FtStopped_Msk (0x1UL << TPI_FFSR_FtStopped_Pos) /*!< TPI FFSR: FtStopped Mask */ + +#define TPI_FFSR_FlInProg_Pos 0U /*!< TPI FFSR: FlInProg Position */ +#define TPI_FFSR_FlInProg_Msk (0x1UL /*<< TPI_FFSR_FlInProg_Pos*/) /*!< TPI FFSR: FlInProg Mask */ + +/* TPI Formatter and Flush Control Register Definitions */ +#define TPI_FFCR_TrigIn_Pos 8U /*!< TPI FFCR: TrigIn Position */ +#define TPI_FFCR_TrigIn_Msk (0x1UL << TPI_FFCR_TrigIn_Pos) /*!< TPI FFCR: TrigIn Mask */ + +#define TPI_FFCR_EnFCont_Pos 1U /*!< TPI FFCR: EnFCont Position */ +#define TPI_FFCR_EnFCont_Msk (0x1UL << TPI_FFCR_EnFCont_Pos) /*!< TPI FFCR: EnFCont Mask */ + +/* TPI TRIGGER Register Definitions */ +#define TPI_TRIGGER_TRIGGER_Pos 0U /*!< TPI TRIGGER: TRIGGER Position */ +#define TPI_TRIGGER_TRIGGER_Msk (0x1UL /*<< TPI_TRIGGER_TRIGGER_Pos*/) /*!< TPI TRIGGER: TRIGGER Mask */ + +/* TPI Integration ETM Data Register Definitions (FIFO0) */ +#define TPI_FIFO0_ITM_ATVALID_Pos 29U /*!< TPI FIFO0: ITM_ATVALID Position */ +#define TPI_FIFO0_ITM_ATVALID_Msk (0x3UL << TPI_FIFO0_ITM_ATVALID_Pos) /*!< TPI FIFO0: ITM_ATVALID Mask */ + +#define TPI_FIFO0_ITM_bytecount_Pos 27U /*!< TPI FIFO0: ITM_bytecount Position */ +#define TPI_FIFO0_ITM_bytecount_Msk (0x3UL << TPI_FIFO0_ITM_bytecount_Pos) /*!< TPI FIFO0: ITM_bytecount Mask */ + +#define TPI_FIFO0_ETM_ATVALID_Pos 26U /*!< TPI FIFO0: ETM_ATVALID Position */ +#define TPI_FIFO0_ETM_ATVALID_Msk (0x3UL << TPI_FIFO0_ETM_ATVALID_Pos) /*!< TPI FIFO0: ETM_ATVALID Mask */ + +#define TPI_FIFO0_ETM_bytecount_Pos 24U /*!< TPI FIFO0: ETM_bytecount Position */ +#define TPI_FIFO0_ETM_bytecount_Msk (0x3UL << TPI_FIFO0_ETM_bytecount_Pos) /*!< TPI FIFO0: ETM_bytecount Mask */ + +#define TPI_FIFO0_ETM2_Pos 16U /*!< TPI FIFO0: ETM2 Position */ +#define TPI_FIFO0_ETM2_Msk (0xFFUL << TPI_FIFO0_ETM2_Pos) /*!< TPI FIFO0: ETM2 Mask */ + +#define TPI_FIFO0_ETM1_Pos 8U /*!< TPI FIFO0: ETM1 Position */ +#define TPI_FIFO0_ETM1_Msk (0xFFUL << TPI_FIFO0_ETM1_Pos) /*!< TPI FIFO0: ETM1 Mask */ + +#define TPI_FIFO0_ETM0_Pos 0U /*!< TPI FIFO0: ETM0 Position */ +#define TPI_FIFO0_ETM0_Msk (0xFFUL /*<< TPI_FIFO0_ETM0_Pos*/) /*!< TPI FIFO0: ETM0 Mask */ + +/* TPI ITATBCTR2 Register Definitions */ +#define TPI_ITATBCTR2_ATREADY_Pos 0U /*!< TPI ITATBCTR2: ATREADY Position */ +#define TPI_ITATBCTR2_ATREADY_Msk (0x1UL /*<< TPI_ITATBCTR2_ATREADY_Pos*/) /*!< TPI ITATBCTR2: ATREADY Mask */ + +/* TPI Integration ITM Data Register Definitions (FIFO1) */ +#define TPI_FIFO1_ITM_ATVALID_Pos 29U /*!< TPI FIFO1: ITM_ATVALID Position */ +#define TPI_FIFO1_ITM_ATVALID_Msk (0x3UL << TPI_FIFO1_ITM_ATVALID_Pos) /*!< TPI FIFO1: ITM_ATVALID Mask */ + +#define TPI_FIFO1_ITM_bytecount_Pos 27U /*!< TPI FIFO1: ITM_bytecount Position */ +#define TPI_FIFO1_ITM_bytecount_Msk (0x3UL << TPI_FIFO1_ITM_bytecount_Pos) /*!< TPI FIFO1: ITM_bytecount Mask */ + +#define TPI_FIFO1_ETM_ATVALID_Pos 26U /*!< TPI FIFO1: ETM_ATVALID Position */ +#define TPI_FIFO1_ETM_ATVALID_Msk (0x3UL << TPI_FIFO1_ETM_ATVALID_Pos) /*!< TPI FIFO1: ETM_ATVALID Mask */ + +#define TPI_FIFO1_ETM_bytecount_Pos 24U /*!< TPI FIFO1: ETM_bytecount Position */ +#define TPI_FIFO1_ETM_bytecount_Msk (0x3UL << TPI_FIFO1_ETM_bytecount_Pos) /*!< TPI FIFO1: ETM_bytecount Mask */ + +#define TPI_FIFO1_ITM2_Pos 16U /*!< TPI FIFO1: ITM2 Position */ +#define TPI_FIFO1_ITM2_Msk (0xFFUL << TPI_FIFO1_ITM2_Pos) /*!< TPI FIFO1: ITM2 Mask */ + +#define TPI_FIFO1_ITM1_Pos 8U /*!< TPI FIFO1: ITM1 Position */ +#define TPI_FIFO1_ITM1_Msk (0xFFUL << TPI_FIFO1_ITM1_Pos) /*!< TPI FIFO1: ITM1 Mask */ + +#define TPI_FIFO1_ITM0_Pos 0U /*!< TPI FIFO1: ITM0 Position */ +#define TPI_FIFO1_ITM0_Msk (0xFFUL /*<< TPI_FIFO1_ITM0_Pos*/) /*!< TPI FIFO1: ITM0 Mask */ + +/* TPI ITATBCTR0 Register Definitions */ +#define TPI_ITATBCTR0_ATREADY_Pos 0U /*!< TPI ITATBCTR0: ATREADY Position */ +#define TPI_ITATBCTR0_ATREADY_Msk (0x1UL /*<< TPI_ITATBCTR0_ATREADY_Pos*/) /*!< TPI ITATBCTR0: ATREADY Mask */ + +/* TPI Integration Mode Control Register Definitions */ +#define TPI_ITCTRL_Mode_Pos 0U /*!< TPI ITCTRL: Mode Position */ +#define TPI_ITCTRL_Mode_Msk (0x1UL /*<< TPI_ITCTRL_Mode_Pos*/) /*!< TPI ITCTRL: Mode Mask */ + +/* TPI DEVID Register Definitions */ +#define TPI_DEVID_NRZVALID_Pos 11U /*!< TPI DEVID: NRZVALID Position */ +#define TPI_DEVID_NRZVALID_Msk (0x1UL << TPI_DEVID_NRZVALID_Pos) /*!< TPI DEVID: NRZVALID Mask */ + +#define TPI_DEVID_MANCVALID_Pos 10U /*!< TPI DEVID: MANCVALID Position */ +#define TPI_DEVID_MANCVALID_Msk (0x1UL << TPI_DEVID_MANCVALID_Pos) /*!< TPI DEVID: MANCVALID Mask */ + +#define TPI_DEVID_PTINVALID_Pos 9U /*!< TPI DEVID: PTINVALID Position */ +#define TPI_DEVID_PTINVALID_Msk (0x1UL << TPI_DEVID_PTINVALID_Pos) /*!< TPI DEVID: PTINVALID Mask */ + +#define TPI_DEVID_MinBufSz_Pos 6U /*!< TPI DEVID: MinBufSz Position */ +#define TPI_DEVID_MinBufSz_Msk (0x7UL << TPI_DEVID_MinBufSz_Pos) /*!< TPI DEVID: MinBufSz Mask */ + +#define TPI_DEVID_AsynClkIn_Pos 5U /*!< TPI DEVID: AsynClkIn Position */ +#define TPI_DEVID_AsynClkIn_Msk (0x1UL << TPI_DEVID_AsynClkIn_Pos) /*!< TPI DEVID: AsynClkIn Mask */ + +#define TPI_DEVID_NrTraceInput_Pos 0U /*!< TPI DEVID: NrTraceInput Position */ +#define TPI_DEVID_NrTraceInput_Msk (0x1FUL /*<< TPI_DEVID_NrTraceInput_Pos*/) /*!< TPI DEVID: NrTraceInput Mask */ + +/* TPI DEVTYPE Register Definitions */ +#define TPI_DEVTYPE_MajorType_Pos 4U /*!< TPI DEVTYPE: MajorType Position */ +#define TPI_DEVTYPE_MajorType_Msk (0xFUL << TPI_DEVTYPE_MajorType_Pos) /*!< TPI DEVTYPE: MajorType Mask */ + +#define TPI_DEVTYPE_SubType_Pos 0U /*!< TPI DEVTYPE: SubType Position */ +#define TPI_DEVTYPE_SubType_Msk (0xFUL /*<< TPI_DEVTYPE_SubType_Pos*/) /*!< TPI DEVTYPE: SubType Mask */ + +/*@}*/ /* end of group CMSIS_TPI */ + + +#if (__MPU_PRESENT == 1U) +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_MPU Memory Protection Unit (MPU) + \brief Type definitions for the Memory Protection Unit (MPU) + @{ + */ + +/** + \brief Structure type to access the Memory Protection Unit (MPU). + */ +typedef struct +{ + __IM uint32_t TYPE; /*!< Offset: 0x000 (R/ ) MPU Type Register */ + __IOM uint32_t CTRL; /*!< Offset: 0x004 (R/W) MPU Control Register */ + __IOM uint32_t RNR; /*!< Offset: 0x008 (R/W) MPU Region RNRber Register */ + __IOM uint32_t RBAR; /*!< Offset: 0x00C (R/W) MPU Region Base Address Register */ + __IOM uint32_t RASR; /*!< Offset: 0x010 (R/W) MPU Region Attribute and Size Register */ + __IOM uint32_t RBAR_A1; /*!< Offset: 0x014 (R/W) MPU Alias 1 Region Base Address Register */ + __IOM uint32_t RASR_A1; /*!< Offset: 0x018 (R/W) MPU Alias 1 Region Attribute and Size Register */ + __IOM uint32_t RBAR_A2; /*!< Offset: 0x01C (R/W) MPU Alias 2 Region Base Address Register */ + __IOM uint32_t RASR_A2; /*!< Offset: 0x020 (R/W) MPU Alias 2 Region Attribute and Size Register */ + __IOM uint32_t RBAR_A3; /*!< Offset: 0x024 (R/W) MPU Alias 3 Region Base Address Register */ + __IOM uint32_t RASR_A3; /*!< Offset: 0x028 (R/W) MPU Alias 3 Region Attribute and Size Register */ +} MPU_Type; + +/* MPU Type Register Definitions */ +#define MPU_TYPE_IREGION_Pos 16U /*!< MPU TYPE: IREGION Position */ +#define MPU_TYPE_IREGION_Msk (0xFFUL << MPU_TYPE_IREGION_Pos) /*!< MPU TYPE: IREGION Mask */ + +#define MPU_TYPE_DREGION_Pos 8U /*!< MPU TYPE: DREGION Position */ +#define MPU_TYPE_DREGION_Msk (0xFFUL << MPU_TYPE_DREGION_Pos) /*!< MPU TYPE: DREGION Mask */ + +#define MPU_TYPE_SEPARATE_Pos 0U /*!< MPU TYPE: SEPARATE Position */ +#define MPU_TYPE_SEPARATE_Msk (1UL /*<< MPU_TYPE_SEPARATE_Pos*/) /*!< MPU TYPE: SEPARATE Mask */ + +/* MPU Control Register Definitions */ +#define MPU_CTRL_PRIVDEFENA_Pos 2U /*!< MPU CTRL: PRIVDEFENA Position */ +#define MPU_CTRL_PRIVDEFENA_Msk (1UL << MPU_CTRL_PRIVDEFENA_Pos) /*!< MPU CTRL: PRIVDEFENA Mask */ + +#define MPU_CTRL_HFNMIENA_Pos 1U /*!< MPU CTRL: HFNMIENA Position */ +#define MPU_CTRL_HFNMIENA_Msk (1UL << MPU_CTRL_HFNMIENA_Pos) /*!< MPU CTRL: HFNMIENA Mask */ + +#define MPU_CTRL_ENABLE_Pos 0U /*!< MPU CTRL: ENABLE Position */ +#define MPU_CTRL_ENABLE_Msk (1UL /*<< MPU_CTRL_ENABLE_Pos*/) /*!< MPU CTRL: ENABLE Mask */ + +/* MPU Region Number Register Definitions */ +#define MPU_RNR_REGION_Pos 0U /*!< MPU RNR: REGION Position */ +#define MPU_RNR_REGION_Msk (0xFFUL /*<< MPU_RNR_REGION_Pos*/) /*!< MPU RNR: REGION Mask */ + +/* MPU Region Base Address Register Definitions */ +#define MPU_RBAR_ADDR_Pos 5U /*!< MPU RBAR: ADDR Position */ +#define MPU_RBAR_ADDR_Msk (0x7FFFFFFUL << MPU_RBAR_ADDR_Pos) /*!< MPU RBAR: ADDR Mask */ + +#define MPU_RBAR_VALID_Pos 4U /*!< MPU RBAR: VALID Position */ +#define MPU_RBAR_VALID_Msk (1UL << MPU_RBAR_VALID_Pos) /*!< MPU RBAR: VALID Mask */ + +#define MPU_RBAR_REGION_Pos 0U /*!< MPU RBAR: REGION Position */ +#define MPU_RBAR_REGION_Msk (0xFUL /*<< MPU_RBAR_REGION_Pos*/) /*!< MPU RBAR: REGION Mask */ + +/* MPU Region Attribute and Size Register Definitions */ +#define MPU_RASR_ATTRS_Pos 16U /*!< MPU RASR: MPU Region Attribute field Position */ +#define MPU_RASR_ATTRS_Msk (0xFFFFUL << MPU_RASR_ATTRS_Pos) /*!< MPU RASR: MPU Region Attribute field Mask */ + +#define MPU_RASR_XN_Pos 28U /*!< MPU RASR: ATTRS.XN Position */ +#define MPU_RASR_XN_Msk (1UL << MPU_RASR_XN_Pos) /*!< MPU RASR: ATTRS.XN Mask */ + +#define MPU_RASR_AP_Pos 24U /*!< MPU RASR: ATTRS.AP Position */ +#define MPU_RASR_AP_Msk (0x7UL << MPU_RASR_AP_Pos) /*!< MPU RASR: ATTRS.AP Mask */ + +#define MPU_RASR_TEX_Pos 19U /*!< MPU RASR: ATTRS.TEX Position */ +#define MPU_RASR_TEX_Msk (0x7UL << MPU_RASR_TEX_Pos) /*!< MPU RASR: ATTRS.TEX Mask */ + +#define MPU_RASR_S_Pos 18U /*!< MPU RASR: ATTRS.S Position */ +#define MPU_RASR_S_Msk (1UL << MPU_RASR_S_Pos) /*!< MPU RASR: ATTRS.S Mask */ + +#define MPU_RASR_C_Pos 17U /*!< MPU RASR: ATTRS.C Position */ +#define MPU_RASR_C_Msk (1UL << MPU_RASR_C_Pos) /*!< MPU RASR: ATTRS.C Mask */ + +#define MPU_RASR_B_Pos 16U /*!< MPU RASR: ATTRS.B Position */ +#define MPU_RASR_B_Msk (1UL << MPU_RASR_B_Pos) /*!< MPU RASR: ATTRS.B Mask */ + +#define MPU_RASR_SRD_Pos 8U /*!< MPU RASR: Sub-Region Disable Position */ +#define MPU_RASR_SRD_Msk (0xFFUL << MPU_RASR_SRD_Pos) /*!< MPU RASR: Sub-Region Disable Mask */ + +#define MPU_RASR_SIZE_Pos 1U /*!< MPU RASR: Region Size Field Position */ +#define MPU_RASR_SIZE_Msk (0x1FUL << MPU_RASR_SIZE_Pos) /*!< MPU RASR: Region Size Field Mask */ + +#define MPU_RASR_ENABLE_Pos 0U /*!< MPU RASR: Region enable bit Position */ +#define MPU_RASR_ENABLE_Msk (1UL /*<< MPU_RASR_ENABLE_Pos*/) /*!< MPU RASR: Region enable bit Disable Mask */ + +/*@} end of group CMSIS_MPU */ +#endif + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_CoreDebug Core Debug Registers (CoreDebug) + \brief Type definitions for the Core Debug Registers + @{ + */ + +/** + \brief Structure type to access the Core Debug Register (CoreDebug). + */ +typedef struct +{ + __IOM uint32_t DHCSR; /*!< Offset: 0x000 (R/W) Debug Halting Control and Status Register */ + __OM uint32_t DCRSR; /*!< Offset: 0x004 ( /W) Debug Core Register Selector Register */ + __IOM uint32_t DCRDR; /*!< Offset: 0x008 (R/W) Debug Core Register Data Register */ + __IOM uint32_t DEMCR; /*!< Offset: 0x00C (R/W) Debug Exception and Monitor Control Register */ +} CoreDebug_Type; + +/* Debug Halting Control and Status Register Definitions */ +#define CoreDebug_DHCSR_DBGKEY_Pos 16U /*!< CoreDebug DHCSR: DBGKEY Position */ +#define CoreDebug_DHCSR_DBGKEY_Msk (0xFFFFUL << CoreDebug_DHCSR_DBGKEY_Pos) /*!< CoreDebug DHCSR: DBGKEY Mask */ + +#define CoreDebug_DHCSR_S_RESET_ST_Pos 25U /*!< CoreDebug DHCSR: S_RESET_ST Position */ +#define CoreDebug_DHCSR_S_RESET_ST_Msk (1UL << CoreDebug_DHCSR_S_RESET_ST_Pos) /*!< CoreDebug DHCSR: S_RESET_ST Mask */ + +#define CoreDebug_DHCSR_S_RETIRE_ST_Pos 24U /*!< CoreDebug DHCSR: S_RETIRE_ST Position */ +#define CoreDebug_DHCSR_S_RETIRE_ST_Msk (1UL << CoreDebug_DHCSR_S_RETIRE_ST_Pos) /*!< CoreDebug DHCSR: S_RETIRE_ST Mask */ + +#define CoreDebug_DHCSR_S_LOCKUP_Pos 19U /*!< CoreDebug DHCSR: S_LOCKUP Position */ +#define CoreDebug_DHCSR_S_LOCKUP_Msk (1UL << CoreDebug_DHCSR_S_LOCKUP_Pos) /*!< CoreDebug DHCSR: S_LOCKUP Mask */ + +#define CoreDebug_DHCSR_S_SLEEP_Pos 18U /*!< CoreDebug DHCSR: S_SLEEP Position */ +#define CoreDebug_DHCSR_S_SLEEP_Msk (1UL << CoreDebug_DHCSR_S_SLEEP_Pos) /*!< CoreDebug DHCSR: S_SLEEP Mask */ + +#define CoreDebug_DHCSR_S_HALT_Pos 17U /*!< CoreDebug DHCSR: S_HALT Position */ +#define CoreDebug_DHCSR_S_HALT_Msk (1UL << CoreDebug_DHCSR_S_HALT_Pos) /*!< CoreDebug DHCSR: S_HALT Mask */ + +#define CoreDebug_DHCSR_S_REGRDY_Pos 16U /*!< CoreDebug DHCSR: S_REGRDY Position */ +#define CoreDebug_DHCSR_S_REGRDY_Msk (1UL << CoreDebug_DHCSR_S_REGRDY_Pos) /*!< CoreDebug DHCSR: S_REGRDY Mask */ + +#define CoreDebug_DHCSR_C_SNAPSTALL_Pos 5U /*!< CoreDebug DHCSR: C_SNAPSTALL Position */ +#define CoreDebug_DHCSR_C_SNAPSTALL_Msk (1UL << CoreDebug_DHCSR_C_SNAPSTALL_Pos) /*!< CoreDebug DHCSR: C_SNAPSTALL Mask */ + +#define CoreDebug_DHCSR_C_MASKINTS_Pos 3U /*!< CoreDebug DHCSR: C_MASKINTS Position */ +#define CoreDebug_DHCSR_C_MASKINTS_Msk (1UL << CoreDebug_DHCSR_C_MASKINTS_Pos) /*!< CoreDebug DHCSR: C_MASKINTS Mask */ + +#define CoreDebug_DHCSR_C_STEP_Pos 2U /*!< CoreDebug DHCSR: C_STEP Position */ +#define CoreDebug_DHCSR_C_STEP_Msk (1UL << CoreDebug_DHCSR_C_STEP_Pos) /*!< CoreDebug DHCSR: C_STEP Mask */ + +#define CoreDebug_DHCSR_C_HALT_Pos 1U /*!< CoreDebug DHCSR: C_HALT Position */ +#define CoreDebug_DHCSR_C_HALT_Msk (1UL << CoreDebug_DHCSR_C_HALT_Pos) /*!< CoreDebug DHCSR: C_HALT Mask */ + +#define CoreDebug_DHCSR_C_DEBUGEN_Pos 0U /*!< CoreDebug DHCSR: C_DEBUGEN Position */ +#define CoreDebug_DHCSR_C_DEBUGEN_Msk (1UL /*<< CoreDebug_DHCSR_C_DEBUGEN_Pos*/) /*!< CoreDebug DHCSR: C_DEBUGEN Mask */ + +/* Debug Core Register Selector Register Definitions */ +#define CoreDebug_DCRSR_REGWnR_Pos 16U /*!< CoreDebug DCRSR: REGWnR Position */ +#define CoreDebug_DCRSR_REGWnR_Msk (1UL << CoreDebug_DCRSR_REGWnR_Pos) /*!< CoreDebug DCRSR: REGWnR Mask */ + +#define CoreDebug_DCRSR_REGSEL_Pos 0U /*!< CoreDebug DCRSR: REGSEL Position */ +#define CoreDebug_DCRSR_REGSEL_Msk (0x1FUL /*<< CoreDebug_DCRSR_REGSEL_Pos*/) /*!< CoreDebug DCRSR: REGSEL Mask */ + +/* Debug Exception and Monitor Control Register Definitions */ +#define CoreDebug_DEMCR_TRCENA_Pos 24U /*!< CoreDebug DEMCR: TRCENA Position */ +#define CoreDebug_DEMCR_TRCENA_Msk (1UL << CoreDebug_DEMCR_TRCENA_Pos) /*!< CoreDebug DEMCR: TRCENA Mask */ + +#define CoreDebug_DEMCR_MON_REQ_Pos 19U /*!< CoreDebug DEMCR: MON_REQ Position */ +#define CoreDebug_DEMCR_MON_REQ_Msk (1UL << CoreDebug_DEMCR_MON_REQ_Pos) /*!< CoreDebug DEMCR: MON_REQ Mask */ + +#define CoreDebug_DEMCR_MON_STEP_Pos 18U /*!< CoreDebug DEMCR: MON_STEP Position */ +#define CoreDebug_DEMCR_MON_STEP_Msk (1UL << CoreDebug_DEMCR_MON_STEP_Pos) /*!< CoreDebug DEMCR: MON_STEP Mask */ + +#define CoreDebug_DEMCR_MON_PEND_Pos 17U /*!< CoreDebug DEMCR: MON_PEND Position */ +#define CoreDebug_DEMCR_MON_PEND_Msk (1UL << CoreDebug_DEMCR_MON_PEND_Pos) /*!< CoreDebug DEMCR: MON_PEND Mask */ + +#define CoreDebug_DEMCR_MON_EN_Pos 16U /*!< CoreDebug DEMCR: MON_EN Position */ +#define CoreDebug_DEMCR_MON_EN_Msk (1UL << CoreDebug_DEMCR_MON_EN_Pos) /*!< CoreDebug DEMCR: MON_EN Mask */ + +#define CoreDebug_DEMCR_VC_HARDERR_Pos 10U /*!< CoreDebug DEMCR: VC_HARDERR Position */ +#define CoreDebug_DEMCR_VC_HARDERR_Msk (1UL << CoreDebug_DEMCR_VC_HARDERR_Pos) /*!< CoreDebug DEMCR: VC_HARDERR Mask */ + +#define CoreDebug_DEMCR_VC_INTERR_Pos 9U /*!< CoreDebug DEMCR: VC_INTERR Position */ +#define CoreDebug_DEMCR_VC_INTERR_Msk (1UL << CoreDebug_DEMCR_VC_INTERR_Pos) /*!< CoreDebug DEMCR: VC_INTERR Mask */ + +#define CoreDebug_DEMCR_VC_BUSERR_Pos 8U /*!< CoreDebug DEMCR: VC_BUSERR Position */ +#define CoreDebug_DEMCR_VC_BUSERR_Msk (1UL << CoreDebug_DEMCR_VC_BUSERR_Pos) /*!< CoreDebug DEMCR: VC_BUSERR Mask */ + +#define CoreDebug_DEMCR_VC_STATERR_Pos 7U /*!< CoreDebug DEMCR: VC_STATERR Position */ +#define CoreDebug_DEMCR_VC_STATERR_Msk (1UL << CoreDebug_DEMCR_VC_STATERR_Pos) /*!< CoreDebug DEMCR: VC_STATERR Mask */ + +#define CoreDebug_DEMCR_VC_CHKERR_Pos 6U /*!< CoreDebug DEMCR: VC_CHKERR Position */ +#define CoreDebug_DEMCR_VC_CHKERR_Msk (1UL << CoreDebug_DEMCR_VC_CHKERR_Pos) /*!< CoreDebug DEMCR: VC_CHKERR Mask */ + +#define CoreDebug_DEMCR_VC_NOCPERR_Pos 5U /*!< CoreDebug DEMCR: VC_NOCPERR Position */ +#define CoreDebug_DEMCR_VC_NOCPERR_Msk (1UL << CoreDebug_DEMCR_VC_NOCPERR_Pos) /*!< CoreDebug DEMCR: VC_NOCPERR Mask */ + +#define CoreDebug_DEMCR_VC_MMERR_Pos 4U /*!< CoreDebug DEMCR: VC_MMERR Position */ +#define CoreDebug_DEMCR_VC_MMERR_Msk (1UL << CoreDebug_DEMCR_VC_MMERR_Pos) /*!< CoreDebug DEMCR: VC_MMERR Mask */ + +#define CoreDebug_DEMCR_VC_CORERESET_Pos 0U /*!< CoreDebug DEMCR: VC_CORERESET Position */ +#define CoreDebug_DEMCR_VC_CORERESET_Msk (1UL /*<< CoreDebug_DEMCR_VC_CORERESET_Pos*/) /*!< CoreDebug DEMCR: VC_CORERESET Mask */ + +/*@} end of group CMSIS_CoreDebug */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_core_bitfield Core register bit field macros + \brief Macros for use with bit field definitions (xxx_Pos, xxx_Msk). + @{ + */ + +/** + \brief Mask and shift a bit field value for use in a register bit range. + \param[in] field Name of the register bit field. + \param[in] value Value of the bit field. + \return Masked and shifted value. +*/ +#define _VAL2FLD(field, value) ((value << field ## _Pos) & field ## _Msk) + +/** + \brief Mask and shift a register value to extract a bit filed value. + \param[in] field Name of the register bit field. + \param[in] value Value of register. + \return Masked and shifted bit field value. +*/ +#define _FLD2VAL(field, value) ((value & field ## _Msk) >> field ## _Pos) + +/*@} end of group CMSIS_core_bitfield */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_core_base Core Definitions + \brief Definitions for base addresses, unions, and structures. + @{ + */ + +/* Memory mapping of Cortex-M3 Hardware */ +#define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */ +#define ITM_BASE (0xE0000000UL) /*!< ITM Base Address */ +#define DWT_BASE (0xE0001000UL) /*!< DWT Base Address */ +#define TPI_BASE (0xE0040000UL) /*!< TPI Base Address */ +#define CoreDebug_BASE (0xE000EDF0UL) /*!< Core Debug Base Address */ +#define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */ +#define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */ +#define SCB_BASE (SCS_BASE + 0x0D00UL) /*!< System Control Block Base Address */ + +#define SCnSCB ((SCnSCB_Type *) SCS_BASE ) /*!< System control Register not in SCB */ +#define SCB ((SCB_Type *) SCB_BASE ) /*!< SCB configuration struct */ +#define SysTick ((SysTick_Type *) SysTick_BASE ) /*!< SysTick configuration struct */ +#define NVIC ((NVIC_Type *) NVIC_BASE ) /*!< NVIC configuration struct */ +#define ITM ((ITM_Type *) ITM_BASE ) /*!< ITM configuration struct */ +#define DWT ((DWT_Type *) DWT_BASE ) /*!< DWT configuration struct */ +#define TPI ((TPI_Type *) TPI_BASE ) /*!< TPI configuration struct */ +#define CoreDebug ((CoreDebug_Type *) CoreDebug_BASE) /*!< Core Debug configuration struct */ + +#if (__MPU_PRESENT == 1U) +#define MPU_BASE (SCS_BASE + 0x0D90UL) /*!< Memory Protection Unit */ +#define MPU ((MPU_Type *) MPU_BASE ) /*!< Memory Protection Unit */ +#endif + +/*@} */ + + + +/******************************************************************************* + * Hardware Abstraction Layer + Core Function Interface contains: + - Core NVIC Functions + - Core SysTick Functions + - Core Debug Functions + - Core Register Access Functions + ******************************************************************************/ +/** + \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference +*/ + + + +/* ########################## NVIC functions #################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_NVICFunctions NVIC Functions + \brief Functions that manage interrupts and exceptions via the NVIC. + @{ + */ + +/** + \brief Set Priority Grouping + \details Sets the priority grouping field using the required unlock sequence. + The parameter PriorityGroup is assigned to the field SCB->AIRCR [10:8] PRIGROUP field. + Only values from 0..7 are used. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set. + \param [in] PriorityGroup Priority grouping field. + */ +__STATIC_INLINE void NVIC_SetPriorityGrouping(uint32_t PriorityGroup) +{ + uint32_t reg_value; + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + + reg_value = SCB->AIRCR; /* read old register configuration */ + reg_value &= ~((uint32_t)(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk)); /* clear bits to change */ + reg_value = (reg_value | + ((uint32_t)0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | + (PriorityGroupTmp << 8U)); /* Insert write key and priorty group */ + SCB->AIRCR = reg_value; +} + + +/** + \brief Get Priority Grouping + \details Reads the priority grouping field from the NVIC Interrupt Controller. + \return Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field). + */ +__STATIC_INLINE uint32_t NVIC_GetPriorityGrouping(void) +{ + return ((uint32_t)((SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos)); +} + + +/** + \brief Enable External Interrupt + \details Enables a device-specific interrupt in the NVIC interrupt controller. + \param [in] IRQn External interrupt number. Value cannot be negative. + */ +__STATIC_INLINE void NVIC_EnableIRQ(IRQn_Type IRQn) +{ + NVIC->ISER[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL)); +} + + +/** + \brief Disable External Interrupt + \details Disables a device-specific interrupt in the NVIC interrupt controller. + \param [in] IRQn External interrupt number. Value cannot be negative. + */ +__STATIC_INLINE void NVIC_DisableIRQ(IRQn_Type IRQn) +{ + NVIC->ICER[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL)); +} + + +/** + \brief Get Pending Interrupt + \details Reads the pending register in the NVIC and returns the pending bit for the specified interrupt. + \param [in] IRQn Interrupt number. + \return 0 Interrupt status is not pending. + \return 1 Interrupt status is pending. + */ +__STATIC_INLINE uint32_t NVIC_GetPendingIRQ(IRQn_Type IRQn) +{ + return ((uint32_t)(((NVIC->ISPR[(((uint32_t)(int32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); +} + + +/** + \brief Set Pending Interrupt + \details Sets the pending bit of an external interrupt. + \param [in] IRQn Interrupt number. Value cannot be negative. + */ +__STATIC_INLINE void NVIC_SetPendingIRQ(IRQn_Type IRQn) +{ + NVIC->ISPR[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL)); +} + + +/** + \brief Clear Pending Interrupt + \details Clears the pending bit of an external interrupt. + \param [in] IRQn External interrupt number. Value cannot be negative. + */ +__STATIC_INLINE void NVIC_ClearPendingIRQ(IRQn_Type IRQn) +{ + NVIC->ICPR[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL)); +} + + +/** + \brief Get Active Interrupt + \details Reads the active register in NVIC and returns the active bit. + \param [in] IRQn Interrupt number. + \return 0 Interrupt status is not active. + \return 1 Interrupt status is active. + */ +__STATIC_INLINE uint32_t NVIC_GetActive(IRQn_Type IRQn) +{ + return ((uint32_t)(((NVIC->IABR[(((uint32_t)(int32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); +} + + +/** + \brief Set Interrupt Priority + \details Sets the priority of an interrupt. + \note The priority cannot be set for every core interrupt. + \param [in] IRQn Interrupt number. + \param [in] priority Priority to set. + */ +__STATIC_INLINE void NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority) +{ + if ((int32_t)(IRQn) < 0) + { + SCB->SHP[(((uint32_t)(int32_t)IRQn) & 0xFUL) - 4UL] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); + } + else + { + NVIC->IP[((uint32_t)(int32_t)IRQn)] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); + } +} + + +/** + \brief Get Interrupt Priority + \details Reads the priority of an interrupt. + The interrupt number can be positive to specify an external (device specific) interrupt, + or negative to specify an internal (core) interrupt. + \param [in] IRQn Interrupt number. + \return Interrupt Priority. + Value is aligned automatically to the implemented priority bits of the microcontroller. + */ +__STATIC_INLINE uint32_t NVIC_GetPriority(IRQn_Type IRQn) +{ + + if ((int32_t)(IRQn) < 0) + { + return (((uint32_t)SCB->SHP[(((uint32_t)(int32_t)IRQn) & 0xFUL) - 4UL] >> (8U - __NVIC_PRIO_BITS))); + } + else + { + return (((uint32_t)NVIC->IP[((uint32_t)(int32_t)IRQn)] >> (8U - __NVIC_PRIO_BITS))); + } +} + + +/** + \brief Encode Priority + \details Encodes the priority for an interrupt with the given priority group, + preemptive priority value, and subpriority value. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set. + \param [in] PriorityGroup Used priority group. + \param [in] PreemptPriority Preemptive priority value (starting from 0). + \param [in] SubPriority Subpriority value (starting from 0). + \return Encoded priority. Value can be used in the function \ref NVIC_SetPriority(). + */ +__STATIC_INLINE uint32_t NVIC_EncodePriority(uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority) +{ + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + uint32_t PreemptPriorityBits; + uint32_t SubPriorityBits; + + PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp); + SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS)); + + return ( + ((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) | + ((SubPriority & (uint32_t)((1UL << (SubPriorityBits)) - 1UL))) + ); +} + + +/** + \brief Decode Priority + \details Decodes an interrupt priority value with a given priority group to + preemptive priority value and subpriority value. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS) the smallest possible priority group is set. + \param [in] Priority Priority value, which can be retrieved with the function \ref NVIC_GetPriority(). + \param [in] PriorityGroup Used priority group. + \param [out] pPreemptPriority Preemptive priority value (starting from 0). + \param [out] pSubPriority Subpriority value (starting from 0). + */ +__STATIC_INLINE void NVIC_DecodePriority(uint32_t Priority, uint32_t PriorityGroup, uint32_t *const pPreemptPriority, uint32_t *const pSubPriority) +{ + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + uint32_t PreemptPriorityBits; + uint32_t SubPriorityBits; + + PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp); + SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS)); + + *pPreemptPriority = (Priority >> SubPriorityBits) & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL); + *pSubPriority = (Priority) & (uint32_t)((1UL << (SubPriorityBits)) - 1UL); +} + + +/** + \brief System Reset + \details Initiates a system reset request to reset the MCU. + */ +__STATIC_INLINE void NVIC_SystemReset(void) +{ + __DSB(); /* Ensure all outstanding memory accesses included + buffered write are completed before reset */ + SCB->AIRCR = (uint32_t)((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | + (SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) | + SCB_AIRCR_SYSRESETREQ_Msk); /* Keep priority group unchanged */ + __DSB(); /* Ensure completion of memory access */ + + for (;;) /* wait until reset */ + { + __NOP(); + } +} + +/*@} end of CMSIS_Core_NVICFunctions */ + + + +/* ################################## SysTick function ############################################ */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_SysTickFunctions SysTick Functions + \brief Functions that configure the System. + @{ + */ + +#if (__Vendor_SysTickConfig == 0U) + +/** + \brief System Tick Configuration + \details Initializes the System Timer and its interrupt, and starts the System Tick Timer. + Counter is in free running mode to generate periodic interrupts. + \param [in] ticks Number of ticks between two interrupts. + \return 0 Function succeeded. + \return 1 Function failed. + \note When the variable __Vendor_SysTickConfig is set to 1, then the + function SysTick_Config is not included. In this case, the file device.h + must contain a vendor-specific implementation of this function. + */ +__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks) +{ + if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk) + { + return (1UL); /* Reload value impossible */ + } + + SysTick->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */ + NVIC_SetPriority(SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */ + SysTick->VAL = 0UL; /* Load the SysTick Counter Value */ + SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk | + SysTick_CTRL_TICKINT_Msk | + SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */ + return (0UL); /* Function successful */ +} + +#endif + +/*@} end of CMSIS_Core_SysTickFunctions */ + + + +/* ##################################### Debug In/Output function ########################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_core_DebugFunctions ITM Functions + \brief Functions that access the ITM debug interface. + @{ + */ + +extern volatile int32_t ITM_RxBuffer; /*!< External variable to receive characters. */ +#define ITM_RXBUFFER_EMPTY 0x5AA55AA5U /*!< Value identifying \ref ITM_RxBuffer is ready for next character. */ + + +/** + \brief ITM Send Character + \details Transmits a character via the ITM channel 0, and + \li Just returns when no debugger is connected that has booked the output. + \li Is blocking when a debugger is connected, but the previous character sent has not been transmitted. + \param [in] ch Character to transmit. + \returns Character to transmit. + */ +__STATIC_INLINE uint32_t ITM_SendChar(uint32_t ch) +{ + if (((ITM->TCR & ITM_TCR_ITMENA_Msk) != 0UL) && /* ITM enabled */ + ((ITM->TER & 1UL) != 0UL)) /* ITM Port #0 enabled */ + { + while (ITM->PORT[0U].u32 == 0UL) + { + __NOP(); + } + ITM->PORT[0U].u8 = (uint8_t)ch; + } + return (ch); +} + + +/** + \brief ITM Receive Character + \details Inputs a character via the external variable \ref ITM_RxBuffer. + \return Received character. + \return -1 No character pending. + */ +__STATIC_INLINE int32_t ITM_ReceiveChar(void) +{ + int32_t ch = -1; /* no character available */ + + if (ITM_RxBuffer != ITM_RXBUFFER_EMPTY) + { + ch = ITM_RxBuffer; + ITM_RxBuffer = ITM_RXBUFFER_EMPTY; /* ready for next character */ + } + + return (ch); +} + + +/** + \brief ITM Check Character + \details Checks whether a character is pending for reading in the variable \ref ITM_RxBuffer. + \return 0 No character available. + \return 1 Character available. + */ +__STATIC_INLINE int32_t ITM_CheckChar(void) +{ + + if (ITM_RxBuffer == ITM_RXBUFFER_EMPTY) + { + return (0); /* no character available */ + } + else + { + return (1); /* character available */ + } +} + +/*@} end of CMSIS_core_DebugFunctions */ + + + + +#ifdef __cplusplus +} +#endif + +#endif /* __CORE_SC300_H_DEPENDANT */ + +#endif /* __CMSIS_GENERIC */ diff --git a/bsp/nuvoton/libraries/ma35/CMSIS/SConscript b/bsp/nuvoton/libraries/ma35/CMSIS/SConscript new file mode 100644 index 0000000000..dc4b1082e8 --- /dev/null +++ b/bsp/nuvoton/libraries/ma35/CMSIS/SConscript @@ -0,0 +1,14 @@ +import rtconfig +Import('RTT_ROOT') +from building import * + +# get current directory +group = [] + +if GetDepend('USE_MA35D1_SUBM'): + cwd = GetCurrentDir() + src = [] + path = [cwd + '/Include',] + group = DefineGroup('CMSIS', src, depend = [''], CPPPATH = path) + +Return('group') diff --git a/bsp/nuvoton/libraries/ma35/Device/Nuvoton/MA35D1/Include/NuMicro.h b/bsp/nuvoton/libraries/ma35/Device/Nuvoton/MA35D1/Include/NuMicro.h new file mode 100644 index 0000000000..6701a455c8 --- /dev/null +++ b/bsp/nuvoton/libraries/ma35/Device/Nuvoton/MA35D1/Include/NuMicro.h @@ -0,0 +1,15 @@ +/**************************************************************************//** + * @file NuMicro.h + * @brief NuMicro peripheral access layer header file. + * + * SPDX-License-Identifier: Apache-2.0 + * @copyright (C) 2020 Nuvoton Technology Corp. All rights reserved. + *****************************************************************************/ +#ifndef __NUMICRO_H__ +#define __NUMICRO_H__ + +#include "ma35d1.h" + +#endif /* __NUMICRO_H__ */ + + diff --git a/bsp/nuvoton/libraries/ma35/Device/Nuvoton/MA35D1/Include/adc_reg.h b/bsp/nuvoton/libraries/ma35/Device/Nuvoton/MA35D1/Include/adc_reg.h new file mode 100644 index 0000000000..4637bb5d19 --- /dev/null +++ b/bsp/nuvoton/libraries/ma35/Device/Nuvoton/MA35D1/Include/adc_reg.h @@ -0,0 +1,378 @@ +/**************************************************************************//** + * @file adc.h + * @brief ADC driver header file + * + * SPDX-License-Identifier: Apache-2.0 + * @copyright (C) 2020~2021 Nuvoton Technology Corp. All rights reserved. + *****************************************************************************/ + +#ifndef __ADC_REG_H__ +#define __ADC_REG_H__ + +#if defined ( __CC_ARM ) + #pragma anon_unions +#endif + +/** + @addtogroup REGISTER Control Register + @{ +*/ + +/** + @addtogroup ADC Analog to Digital Converter(ADC) + Memory Mapped Structure for ADC Controller +@{ */ + +typedef struct +{ + + + /** + * @var ADC_T::CTL + * Offset: 0x00 ADC Control + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[0] |ADEN |ADC Power Control + * | | |0 = Power down ADC. + * | | |1 = Power on ADC. + * |[8] |MST |Menu Start Conversion + * | | |0 = Functional menu not started. + * | | |1 = Start all enable bit in ADC_CONF register. + * | | |Note: This bit is set by software and cleared by hardware when all the tasks listed in ADC_CONF are done. + * |[9] |PEDEEN |Pen Down Event Enable Bit + * | | |0 = Pen down event interrupt Disabled. + * | | |1 = Pen down event interrupt Enabled. + * |[11] |WKTEN |Touch Wake Up Enable Bit + * | | |0 = Touch wake-up Disabled. + * | | |1 = Touch wake-up Enabled. + * |[16] |WMSWCH |Wire Mode Switch for 5-wire/4-wire Configuration + * | | |0 = 4-wire mode. + * | | |1 = 5-wire mode. + * @var ADC_T::CONF + * Offset: 0x04 ADC Configure + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[0] |TEN |Touch Detection Enable Bit + * | | |0 = Touch detection function Disabled. + * | | |1 = Touch detection function Enabled. + * |[1] |ZEN |Press Measure Enable Bit + * | | |1 = Press measure function Disabled. + * | | |1 = Press measure function Enabled. + * |[2] |NACEN |Normal A/D Conversion Enable Bit + * | | |ADC normal conversion function enable + * | | |0 = Normal A/D Conversion Disabled. + * | | |1 = Normal A/D Conversion Enabled. + * |[7:6] |REFSEL |ADC Reference Select + * | | |ADC reference voltage select when ADC operate in normal conversion. + * | | |00 = AGND33 vs VREF input. + * | | |01 = YM vs YP. + * | | |10 = XM vs XP. + * | | |11 = AGND33 vs AVDD33. + * |[14:12] |CHSEL |Channel Selection + * | | |ADC input channel selection. + * | | |000 = VREF. + * | | |001 = A1. + * | | |010 = A2. + * | | |011 = VSENSE. + * | | |100 = YM. + * | | |101 = YP. + * | | |110 = XM. + * | | |111 = XP. + * |[20] |TMAVDIS |Display T Mean Average Disable Bit + * | | |Touch mean average for X and Y function disable bit. + * | | |0 = Touch mean average for X and Y function Enabled. + * | | |1 = Touch mean average for X and Y function Disabled. + * |[21] |ZMAVDIS |Display Z Mean Average Disable Bit + * | | |Pressure mean average for Z1 and Z2 function disable bit. + * | | |0 = Pressure mean average for Z1 and Z2 function Enabled. + * | | |1 = Pressure mean average for Z1 and Z2 function Disabled. + * |[22] |SPEED |Speed Mode Selection + * | | |0 = All ADC channels set to high speed mode. + * | | |1 = All ADC channels set to low speed mode. + * @var ADC_T::IER + * Offset: 0x08 ADC Interrupt Enable Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[0] |MIEN |Menu Interrupt Enable Bit + * | | |Function menu complete interrupt enable. + * | | |0 = Menu interrupt Disabled. + * | | |1 = Menu interrupt Enabled. + * |[2] |PEDEIEN |Pen Down Event Interrupt Enable Bit + * | | |0 = Pen down event detection interrupt Disabled. + * | | |1 = Pen down event detection interrupt Enabled. + * |[3] |WKTIEN |Wake Up Touch Interrupt Enable Bit + * | | |0 = Wake up touch detection interrupt Disabled. + * | | |1 = Wake up touch detection interrupt Enabled. + * |[6] |PEUEIEN |Pen Up Event Interrupt Enable Bit + * | | |0 = Pen up event detection interrupt Disabled. + * | | |1 = Pen up event detection interrupt Enabled. + * @var ADC_T::ISR + * Offset: 0x0C ADC Interrupt Status Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[0] |MF |Menu Complete Flag + * | | |Function menu complete status indicator. + * | | |Note: Set by hardware and write 1 to clear this bit. + * |[2] |PEDEF |Pen Down Event Flag + * | | |Pen down event status indicator. + * | | |Note: Set by hardware and write 1 to clear this bit. + * |[4] |PEUEF |Pen Up Event Flag + * | | |Pen up event status indicator. + * | | |Note: Set by hardware and write 1 to clear this bit. + * |[8] |TF |Touch Conversion Finish + * | | |Functional menu touch detection conversion finish. + * | | |Note: Set by hardware and write 1 to clear this bit. + * |[9] |ZF |Press Conversion Finish + * | | |Functional menu press measure conversion finish. + * | | |Note: Set by hardware and write 1 to clear this bit. + * |[10] |NACF |Normal AD Conversion Finish + * | | |Functional menu normal AD conversion finish. + * | | |Note: Set by hardware and write 1 to clear this bit. + * |[17] |INTTC |Interrupt Signal for Touch Screen Touching Detection + * | | |This signal is directly from analog macro without de-bouncing and can be used to determine the pen down touch event together with PEDEF (ADC_ISR[2]) flag. + * @var ADC_T::WKISR + * Offset: 0x10 ADC Wake-up interrupt Status Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[1] |WPEDEF |Wake Up Pen Down Event Flag + * | | |Pen down event wake up status indicator. + * @var ADC_T::XYDATA + * Offset: 0x20 ADC Touch X,Y Position Data + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[11:0] |XDATA |ADC X Data + * | | |When TEN (ADC_CONF[0]) is set, the touch x-position will be stored in this register. + * | | |Note: If the TMAVDIS (ADC_CONF[20]) = 0, both x and y position are the results of the mean average of x and y in ADC_XYSORT0 ~ ADC_XYSORT3. + * |[27:16] |YDATA |ADC Y Data + * | | |When TEN (ADC_CONF[0]) is set, the touch y-position will be stored in this register. + * | | |Note: If the TMAVDIS (ADC_CONF[20]) = 0, both x and y position are the results of the mean average of x and y in ADC_XYSORT0 ~ ADC_XYSORT3. + * @var ADC_T::ZDATA + * Offset: 0x24 ADC Touch Z Pressure Data + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[11:0] |Z1DATA |ADC Z1 Data + * | | |When ZEN (ADC_CONF[1]) is set; the touch pressure measure Z1 will be stored in this register. + * | | |Note: If the ZMAVDIS (ADC_CONF[21]) = 0, both Z1 and Z2 data is the results of the mean average of Z1 and Z2 in ADC_ZSORT0 ~ ADC_ZSORT3. + * |[27:16] |Z2DATA |ADC Z2 Data + * | | |When ZEN (ADC_CONF[1]) is set; the touch pressure measure Z2 will be stored in this register. + * | | |Note: If the ZMAVDIS (ADC_CONF[21]) = 0, both Z1 and Z2 data is the results of the mean average of Z1 and Z2 in ADC_ZSORT0 ~ ADC_ZSORT3. + * @var ADC_T::DATA + * Offset: 0x28 ADC Normal Conversion Data + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[11:0] |ADCDATA |ADC Data + * | | |When NACEN (ADC_CONF[2]) is enabled, the AD converting result with corresponding channel is stored in this register. + * @var ADC_T::XYSORT0 + * Offset: 0x1F4 ADC Touch XY Position Mean Value Sort 0 + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[11:0] |XSORT0 |X Position Sort Data 0 + * | | |X position mean average sort data 0. + * |[27:16] |YSORT0 |Y Position Sort Data 0 + * | | |Y position mean average sort data 0. + * @var ADC_T::XYSORT1 + * Offset: 0x1F8 ADC Touch XY Position Mean Value Sort 1 + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[11:0] |XSORT1 |X Position Sort Data 1 + * | | |X position mean average sort data 1. + * |[27:16] |YSORT1 |Y Position Sort Data 1 + * | | |Y position mean average sort data 1. + * @var ADC_T::XYSORT2 + * Offset: 0x1FC ADC Touch XY Position Mean Value Sort 2 + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[11:0] |XSORT2 |X Position Sort Data 2 + * | | |X position mean average sort data 2. + * |[27:16] |YSORT2 |Y Position Sort Data 2 + * | | |Y position mean average sort data 2. + * @var ADC_T::XYSORT3 + * Offset: 0x200 ADC Touch XY Position Mean Value Sort 3 + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[11:0] |XSORT3 |X Position Sort Data 3 + * | | |X position mean average sort data 3. + * |[27:16] |YSORT3 |Y Position Sort Data 3 + * | | |Y position mean average sort data 3. + * @var ADC_T::ZSORT0 + * Offset: 0x204 ADC Touch Z Pressure Mean Value Sort 0 + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[11:0] |Z1SORT0 |Z1 Position Sort Data 0 + * | | |Z1 position Mean average sort data 0. + * |[27:16] |Z2SORT0 |Z2 Position Sort Data 0 + * | | |Z2 position Mean average sort data 0. + * @var ADC_T::ZSORT1 + * Offset: 0x208 ADC Touch Z Pressure Mean Value Sort 1 + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[11:0] |Z1SORT1 |Z1 Position Sort Data 1 + * | | |Z1 position Mean average sort data 1. + * |[27:16] |Z2SORT1 |Z2 Position Sort Data 1 + * | | |Z2 position Mean average sort data 1. + * @var ADC_T::ZSORT2 + * Offset: 0x20C ADC Touch Z Pressure Mean Value Sort 2 + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[11:0] |Z1SORT2 |Z1 Position Sort Data 2 + * | | |Z1 position Mean average sort data 2. + * |[27:16] |Z2SORT2 |Z2 Position Sort Data 2 + * | | |Z2 position Mean average sort data 2. + * @var ADC_T::ZSORT3 + * Offset: 0x210 ADC Touch Z Pressure Mean Value Sort 3 + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[11:0] |Z1SORT3 |Z1 Position Sort Data 3 + * | | |Z1 position Mean average sort data 3. + * |[27:16] |Z2SORT3 |Z2 Position Sort Data 3 + * | | |Z2 position Mean average sort data 3. + */ + __IO uint32_t CTL; /*!< [0x0000] ADC Control */ + __IO uint32_t CONF; /*!< [0x0004] ADC Configure */ + __IO uint32_t IER; /*!< [0x0008] ADC Interrupt Enable Register */ + __IO uint32_t ISR; /*!< [0x000c] ADC Interrupt Status Register */ + __I uint32_t WKISR; /*!< [0x0010] ADC Wake-up interrupt Status Register */ + __I uint32_t RESERVE0[3]; + __I uint32_t XYDATA; /*!< [0x0020] ADC Touch X,Y Position Data */ + __I uint32_t ZDATA; /*!< [0x0024] ADC Touch Z Pressure Data */ + __I uint32_t DATA; /*!< [0x0028] ADC Normal Conversion Data */ + __I uint32_t RESERVE1[114]; + __I uint32_t XYSORT[4]; /*!< [0x01f4~0x0200] ADC Touch XY Position Mean Value Sort Register */ + __I uint32_t ZSORT0[4]; /*!< [0x0204~0x0210] ADC Touch Z Pressure Mean Value Sort Register */ + +} ADC_T; + +/** + @addtogroup ADC_CONST ADC Bit Field Definition + Constant Definitions for ADC Controller +@{ */ + +#define ADC_CTL_ADEN_Pos (0) /*!< ADC_T::CTL: ADEN Position */ +#define ADC_CTL_ADEN_Msk (0x1ul << ADC_CTL_ADEN_Pos) /*!< ADC_T::CTL: ADEN Mask */ + +#define ADC_CTL_MST_Pos (8) /*!< ADC_T::CTL: MST Position */ +#define ADC_CTL_MST_Msk (0x1ul << ADC_CTL_MST_Pos) /*!< ADC_T::CTL: MST Mask */ + +#define ADC_CTL_PEDEEN_Pos (9) /*!< ADC_T::CTL: PEDEEN Position */ +#define ADC_CTL_PEDEEN_Msk (0x1ul << ADC_CTL_PEDEEN_Pos) /*!< ADC_T::CTL: PEDEEN Mask */ + +#define ADC_CTL_WKTEN_Pos (11) /*!< ADC_T::CTL: WKTEN Position */ +#define ADC_CTL_WKTEN_Msk (0x1ul << ADC_CTL_WKTEN_Pos) /*!< ADC_T::CTL: WKTEN Mask */ + +#define ADC_CTL_WMSWCH_Pos (16) /*!< ADC_T::CTL: WMSWCH Position */ +#define ADC_CTL_WMSWCH_Msk (0x1ul << ADC_CTL_WMSWCH_Pos) /*!< ADC_T::CTL: WMSWCH Mask */ + +#define ADC_CONF_TEN_Pos (0) /*!< ADC_T::CONF: TEN Position */ +#define ADC_CONF_TEN_Msk (0x1ul << ADC_CONF_TEN_Pos) /*!< ADC_T::CONF: TEN Mask */ + +#define ADC_CONF_ZEN_Pos (1) /*!< ADC_T::CONF: ZEN Position */ +#define ADC_CONF_ZEN_Msk (0x1ul << ADC_CONF_ZEN_Pos) /*!< ADC_T::CONF: ZEN Mask */ + +#define ADC_CONF_NACEN_Pos (2) /*!< ADC_T::CONF: NACEN Position */ +#define ADC_CONF_NACEN_Msk (0x1ul << ADC_CONF_NACEN_Pos) /*!< ADC_T::CONF: NACEN Mask */ + +#define ADC_CONF_REFSEL_Pos (6) /*!< ADC_T::CONF: REFSEL Position */ +#define ADC_CONF_REFSEL_Msk (0x3ul << ADC_CONF_REFSEL_Pos) /*!< ADC_T::CONF: REFSEL Mask */ + +#define ADC_CONF_CHSEL_Pos (12) /*!< ADC_T::CONF: CHSEL Position */ +#define ADC_CONF_CHSEL_Msk (0x7ul << ADC_CONF_CHSEL_Pos) /*!< ADC_T::CONF: CHSEL Mask */ + +#define ADC_CONF_TMAVDIS_Pos (20) /*!< ADC_T::CONF: TMAVDIS Position */ +#define ADC_CONF_TMAVDIS_Msk (0x1ul << ADC_CONF_TMAVDIS_Pos) /*!< ADC_T::CONF: TMAVDIS Mask */ + +#define ADC_CONF_ZMAVDIS_Pos (21) /*!< ADC_T::CONF: ZMAVDIS Position */ +#define ADC_CONF_ZMAVDIS_Msk (0x1ul << ADC_CONF_ZMAVDIS_Pos) /*!< ADC_T::CONF: ZMAVDIS Mask */ + +#define ADC_CONF_SPEED_Pos (22) /*!< ADC_T::CONF: SPEED Position */ +#define ADC_CONF_SPEED_Msk (0x1ul << ADC_CONF_SPEED_Pos) /*!< ADC_T::CONF: SPEED Mask */ + +#define ADC_IER_MIEN_Pos (0) /*!< ADC_T::IER: MIEN Position */ +#define ADC_IER_MIEN_Msk (0x1ul << ADC_IER_MIEN_Pos) /*!< ADC_T::IER: MIEN Mask */ + +#define ADC_IER_PEDEIEN_Pos (2) /*!< ADC_T::IER: PEDEIEN Position */ +#define ADC_IER_PEDEIEN_Msk (0x1ul << ADC_IER_PEDEIEN_Pos) /*!< ADC_T::IER: PEDEIEN Mask */ + +#define ADC_IER_WKTIEN_Pos (3) /*!< ADC_T::IER: WKTIEN Position */ +#define ADC_IER_WKTIEN_Msk (0x1ul << ADC_IER_WKTIEN_Pos) /*!< ADC_T::IER: WKTIEN Mask */ + +#define ADC_IER_PEUEIEN_Pos (6) /*!< ADC_T::IER: PEUEIEN Position */ +#define ADC_IER_PEUEIEN_Msk (0x1ul << ADC_IER_PEUEIEN_Pos) /*!< ADC_T::IER: PEUEIEN Mask */ + +#define ADC_ISR_MF_Pos (0) /*!< ADC_T::ISR: MF Position */ +#define ADC_ISR_MF_Msk (0x1ul << ADC_ISR_MF_Pos) /*!< ADC_T::ISR: MF Mask */ + +#define ADC_ISR_PEDEF_Pos (2) /*!< ADC_T::ISR: PEDEF Position */ +#define ADC_ISR_PEDEF_Msk (0x1ul << ADC_ISR_PEDEF_Pos) /*!< ADC_T::ISR: PEDEF Mask */ + +#define ADC_ISR_PEUEF_Pos (4) /*!< ADC_T::ISR: PEUEF Position */ +#define ADC_ISR_PEUEF_Msk (0x1ul << ADC_ISR_PEUEF_Pos) /*!< ADC_T::ISR: PEUEF Mask */ + +#define ADC_ISR_TF_Pos (8) /*!< ADC_T::ISR: TF Position */ +#define ADC_ISR_TF_Msk (0x1ul << ADC_ISR_TF_Pos) /*!< ADC_T::ISR: TF Mask */ + +#define ADC_ISR_ZF_Pos (9) /*!< ADC_T::ISR: ZF Position */ +#define ADC_ISR_ZF_Msk (0x1ul << ADC_ISR_ZF_Pos) /*!< ADC_T::ISR: ZF Mask */ + +#define ADC_ISR_NACF_Pos (10) /*!< ADC_T::ISR: NACF Position */ +#define ADC_ISR_NACF_Msk (0x1ul << ADC_ISR_NACF_Pos) /*!< ADC_T::ISR: NACF Mask */ + +#define ADC_ISR_INTTC_Pos (17) /*!< ADC_T::ISR: INTTC Position */ +#define ADC_ISR_INTTC_Msk (0x1ul << ADC_ISR_INTTC_Pos) /*!< ADC_T::ISR: INTTC Mask */ + +#define ADC_WKISR_WPEDEF_Pos (1) /*!< ADC_T::WKISR: WPEDEF Position */ +#define ADC_WKISR_WPEDEF_Msk (0x1ul << ADC_WKISR_WPEDEF_Pos) /*!< ADC_T::WKISR: WPEDEF Mask */ + +#define ADC_XYDATA_XDATA_Pos (0) /*!< ADC_T::XYDATA: XDATA Position */ +#define ADC_XYDATA_XDATA_Msk (0xffful << ADC_XYDATA_XDATA_Pos) /*!< ADC_T::XYDATA: XDATA Mask */ + +#define ADC_XYDATA_YDATA_Pos (16) /*!< ADC_T::XYDATA: YDATA Position */ +#define ADC_XYDATA_YDATA_Msk (0xffful << ADC_XYDATA_YDATA_Pos) /*!< ADC_T::XYDATA: YDATA Mask */ + +#define ADC_ZDATA_Z1DATA_Pos (0) /*!< ADC_T::ZDATA: Z1DATA Position */ +#define ADC_ZDATA_Z1DATA_Msk (0xffful << ADC_ZDATA_Z1DATA_Pos) /*!< ADC_T::ZDATA: Z1DATA Mask */ + +#define ADC_ZDATA_Z2DATA_Pos (16) /*!< ADC_T::ZDATA: Z2DATA Position */ +#define ADC_ZDATA_Z2DATA_Msk (0xffful << ADC_ZDATA_Z2DATA_Pos) /*!< ADC_T::ZDATA: Z2DATA Mask */ + +#define ADC_DATA_ADCDATA_Pos (0) /*!< ADC_T::DATA: ADCDATA Position */ +#define ADC_DATA_ADCDATA_Msk (0xffful << ADC_DATA_ADCDATA_Pos) /*!< ADC_T::DATA: ADCDATA Mask */ + +#define ADC_XYSORT_XSORT_Pos (0) /*!< ADC_T::XYSORT: XSORT Position */ +#define ADC_XYSORT_XSORT_Msk (0xffful << ADC_XYSORT_XSORT_Pos) /*!< ADC_T::XYSORT: XSORT Mask */ + +#define ADC_XYSORT_YSORT_Pos (16) /*!< ADC_T::XYSORT: YSORT Position */ +#define ADC_XYSORT_YSORT_Msk (0xffful << ADC_XYSORT_YSORT_Pos) /*!< ADC_T::XYSORT: YSORT Mask */ + +#define ADC_ZSORT_Z1SORT_Pos (0) /*!< ADC_T::ZSORT: Z1SORT Position */ +#define ADC_ZSORT_Z1SORT_Msk (0xffful << ADC_ZSORT_Z1SORT_Pos) /*!< ADC_T::ZSORT: Z1SORT Mask */ + +#define ADC_ZSORT_Z2SORT_Pos (16) /*!< ADC_T::ZSORT: Z2SORT Position */ +#define ADC_ZSORT_Z2SORT_Msk (0xffful << ADC_ZSORT_Z2SORT_Pos) /*!< ADC_T::ZSORT: Z2SORT Mask */ + +/**@}*/ /* ADC_CONST */ +/**@}*/ /* end of ADC register group */ +/**@}*/ /* end of REGISTER group */ + +#if defined ( __CC_ARM ) + #pragma no_anon_unions +#endif + +#endif //__ADC_REG_H__ + + diff --git a/bsp/nuvoton/libraries/ma35/Device/Nuvoton/MA35D1/Include/canfd_reg.h b/bsp/nuvoton/libraries/ma35/Device/Nuvoton/MA35D1/Include/canfd_reg.h new file mode 100644 index 0000000000..e4595d878a --- /dev/null +++ b/bsp/nuvoton/libraries/ma35/Device/Nuvoton/MA35D1/Include/canfd_reg.h @@ -0,0 +1,1709 @@ +/**************************************************************************//** + * @file canfd_reg.h + * @brief CANFD register definition header file + * + * SPDX-License-Identifier: Apache-2.0 + * @copyright (C) 2020 Nuvoton Technology Corp. All rights reserved. + *****************************************************************************/ + +#ifndef __CANFD_REG_H__ +#define __CANFD_REG_H__ + +#if defined ( __CC_ARM ) + #pragma anon_unions +#endif + +/** + @addtogroup REGISTER Control Register + @{ +*/ + +/** + @addtogroup Controller Area Network with Feasibility Data Rate (CAN FD) + Memory Mapped Structure for CAN FD Controller +@{ */ + +typedef struct +{ + + + /** + * @var CANFD_T::DBTP + * Offset: 0x0C Data Bit Timing & Prescaler Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[3:0] |DSJW |Data Re-Synchronization Jump Width + * | | |Valid values are 0 to 15 + * | | |The actual interpretation by the hardware of this value is such that one more than the programmed value is used + * | | |tSJW = (DSJW + 1) x tq. + * |[7:4] |DTSEG2 |Data time segment after sample point + * | | |Valid values are 0 to 15 + * | | |The actual interpretation by the hardware of this value is such that one more than the programmed value is used + * | | |tBS2 = (DTSEG2 + 1) x tq. + * |[12:8] |DTSEG1 |Data time segment before sample point + * | | |Valid values are 0 to 31 + * | | |The actual interpretation by the hardware of this value is such that one more than the programmed value is used + * | | |tBS1 = (DTSEG1 + 1) x tq. + * |[20:16] |DBRP |Data Bit Rate Prescaler + * | | |The value by which the oscillator frequency is divided for generating the bit time quanta + * | | |The bit time is built up from a multiple of this quanta + * | | |Valid values for the Bit Rate Prescaler are 0 to 31 + * | | |When TDC = '1', the range is limited to 0,1 + * | | |The actual interpretation by the hardware of this value is such that one more than the value programmed here is used. + * |[23] |TDC |Transmitter Delay Compensation + * | | |0 =Transmitter Delay Compensation Disabled. + * | | |1 =Transmitter Delay Compensation Enabled. + * @var CANFD_T::TEST + * Offset: 0x10 Test Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[4] |LBCK |Loop Back Mode + * | | |0 = Reset value, Loop Back Mode Disabled. + * | | |1 = Loop Back Mode Enabled (refer to section 6.33.5.1 TEST Mode). + * |[6:5] |TX |Control of Transmit Pin + * | | |00 = Reset value, CANx_TXD controlled by the CAN Core, updated at the end of the CAN bit time. + * | | |01 = Sample Point can be monitored at pin CANx_TXD. + * | | |10 = Dominant ('0') level at pin CANx_TXD. + * | | |11 = Recessive ('1') level at pin CANx_TXD. + * |[7] |RX |Receive Pin + * | | |Monitors the actual value of pin CANx_RXD + * | | |0 = The CAN bus is dominant (CANx_RXD = 0). + * | | |1 = The CAN bus is recessive (CANx_RXD = 1). + * @var CANFD_T::RWD + * Offset: 0x14 RAM Watchdog + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[7:0] |WDC |Watchdog Configuration + * | | |Start value of the Message RAM Watchdog Counter. With the reset value of 00 the counter is disabled. + * |[15:8] |WDV |Watchdog Value + * | | |Actual Message RAM Watchdog Counter Value. + * @var CANFD_T::CCCR + * Offset: 0x18 CC Control Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[0] |INIT |Initialization + * | | |0 = Normal Operation. + * | | |1 = Initialization is started. + * | | |Note: Due to the synchronization mechanism between the two clock domains, there may be a delay until the value written to INIT can be read back + * | | |Therefore the programmer has to assure that the previous value written to INIT has been accepted by reading INIT before setting INIT to a new value. + * |[1] |CCE |Configuration Change Enable + * | | |0 = The CPU has no write access to the protected configuration registers. + * | | |1 = The CPU has write access to the protected configuration registers (while CANFD_INIT (CANFD_CCCR[0]) = 1). + * |[2] |ASM |Restricted Operation Mode + * | | |Bit ASM can only be set by the Host when both CCE and INIT are set to 1 + * | | |The bit can be reset by the software at any time + * | | |This bit will be set automatically set to 1 when the Tx handler was not able to read data from the message RAM in time + * | | |For a description of the Restricted Operation Mode refer to Restricted Operation Mode. + * | | |0 = Normal CAN operation. + * | | |1 = Restricted Operation Mode active. + * |[3] |CSA |Clock Stop Acknowledge + * | | |0 = No clock stop acknowledged. + * | | |1 = The Controller may be set in power down by stopping AHB clock and CAN Core clock. + * |[4] |CSR |Clock Stop Request + * | | |0 = No clock stop is requested. + * | | |1 = Clock stop requested + * | | |When clock stop is requested, first INIT and then CSA will be set after all pending transfer requests have been completed and the CAN bus reached idle. + * |[5] |MON |Bus Monitoring Mode + * | | |Bit MON can only be set by the Host when both CCE and INIT are set to 1 + * | | |The bit can be reset by the Host at any time. + * | | |0 = Bus Monitoring Mode Disabled. + * | | |1 = Bus Monitoring Mode Enabled. + * |[6] |DAR |Disable Automatic Retransmission + * | | |0 = Automatic retransmission of messages not transmitted successfully Enabled. + * | | |1 = Automatic retransmission Disabled. + * |[7] |TEST |Test Mode Enable + * | | |0 = Normal operation, register TEST holds reset values. + * | | |1 = Test Mode, write access to register TEST enabled. + * |[8] |FDOE |FD Operation Enable + * | | |0 = FD operation Disabled. + * | | |1 = FD operation Enabled. + * |[9] |BRSE |Bit Rate Switch Enable + * | | |0 = Bit rate switching for transmissions Disabled. + * | | |1 = Bit rate switching for transmissions Enabled. + * | | |Note: When CAN FD operation is disabled FDOE = 0, BRSE is not evaluated. + * |[12] |PXHD |Protocol Exception Handling Disable + * | | |0 = Protocol exception handling Enabled. + * | | |1 = Protocol exception handling Disabled. + * | | |Note: When protocol exception handling is disabled, the controller will transmit an error frame when it detects a protocol exception condition. + * |[13] |EFBI |Edge Filtering during Bus Integration + * | | |0 = Edge filtering Disabled. + * | | |1 = Two consecutive dominant tq required to detect an edge f or hard synchronization. + * |[14] |TXP |Transmit Pause + * | | |If this bit is set, the CAN FD controller pauses for two CAN bit times before starting the next transmission after itself has successfully transmitted a frame (refer to section 6.33.5.5). + * | | |0 = Transmit pause Disabled. + * | | |1 = Transmit pause Enabled. + * |[15] |NISO |Non ISO Operation + * | | |If this bit is set, the CAN FD controller uses the CAN FD frame format as specified by the Bosch CAN FD Specification V1.0. + * | | |0 = CAN FD frame format according to ISO 11898-1:2015. + * | | |1 = CAN FD frame format according to Bosch CAN FD Specification V1.0. + * @var CANFD_T::NBTP + * Offset: 0x1C Nominal Bit Timing & Prescaler Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[6:0] |NTSEG2 |Nominal Time Segment after Sample Point + * | | |0x01-0x7F Valid values are 1 to 127 + * | | |The actual interpretation by the hardware of this value is such that one more than the programmed value is used + * | | |tBS2 = (NTSEG2 + 1) x tq. + * | | |Note: With a CAN Core clock (cclk) of 8 MHz, the reset value of 0x06000A03 configures the controller for a bit rate of 500 kBit/s. + * |[15:8] |NTSEG1 |Nominal Time Segment before Sample Point + * | | |Valid values are 1 to 255 + * | | |The actual interpretation by the hardware of this value is such that one more than the programmed value is used + * | | |tBS1 = (NTSEG1 + 1) x tq. + * |[24:16] |NBRP |Nominal Bit Rate Prescaler + * | | |The value by which the oscillator frequency is divided for generating the bit time quanta + * | | |The bit time is built up from a multiple of this quanta + * | | |Valid values for the Bit Rate Prescaler are 0 to 511 + * | | |The actual interpretation by the hardware of this value is such that one more than the value programmed here is used + * |[31:25] |NSJW |Nominal Re-Synchronization Jump Width + * | | |Valid values are 0 to 127, which should be smaller than NTSEG2 + * | | |The actual interpretation by the hardware of this value is such that one more than the value programmed here is used + * | | |tSJW = (NSJW + 1) x tq. + * @var CANFD_T::TSCC + * Offset: 0x20 Timestamp Counter Configuration + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[1:0] |TSS |Timestamp Select + * | | |00 = Timestamp counter value always 0x0000. + * | | |01 = Timestamp counter value incremented according to TCP. + * | | |10 = Reserved. + * | | |11 = Same as '00'. + * |[19:16] |TCP |Timestamp Counter Prescaler + * | | |Configures the timestamp and timeout counters time unit in multiples of CAN bit times [ 1u202616 ] + * | | |The actual interpretation by the hardware of this value is such that one more than the value programmed here is used. + * @var CANFD_T::TSCV + * Offset: 0x24 Timestamp Counter Value + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[15:0] |TSC |Timestamp Counter + * | | |The internal Timestamp Counter value is captured on start of frame (both Rx and Tx) + * | | |When CANFD_TSS (TSCC[[1:0]) = 2'b01, the Timestamp Counter is incremented in multiples of CAN bit times [ 1...16 ] depending on the configuration of CANFD_TCP (CANFD_TSCC[19:16]) + * | | |A wrap around sets interrupt flag CANFD_IR (CANFD_IR[16]) + * | | |Write access resets the counter to 0. + * | | |Note: A "around" is a change of the Timestamp Counter value from non-zero to 0 not caused by write access to CANFD_TSCV. + * @var CANFD_T::TOCC + * Offset: 0x28 Timeout Counter Configuration + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[0] |ETOC |Enable Timeout Counter + * | | |0 = Timeout Counter Disabled. + * | | |1 = Timeout Counter Enabled. + * | | |Note: For use of timeout function with CAN FD refer to section 6.33.5.3. + * |[2:1] |TOS |Timeout Select + * | | |When operating in Continuous mode, a write to CANFD_TOCV presets the counter to the value configured by CANFD_TOP (TOCC[31:16]) and continues down-counting + * | | |When the Timeout Counter is controlled by one of the FIFOs, an empty FIFO presets the counter to the value configured by CANFD_TOP (TOCC[31:16]) + * | | |Down-counting is started when the first FIFO element is stored. + * | | |00 = Continuous operation. + * | | |01 = Timeout controlled by Tx Event FIFO. + * | | |10 = Timeout controlled by Rx FIFO 0. + * | | |11 = Timeout controlled by Rx FIFO 1. + * |[31:16] |TOP |Timeout Period + * | | |Start value of the Timeout Counter (down-counter). Configures the Timeout Period. + * @var CANFD_T::TOCV + * Offset: 0x2C Timeout Counter Value + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[15:0] |TOC |Timeout Counter + * | | |The filed is decremented in multiples of CAN bit times [ 1...16 ] depending on the configuration of TCP (CANFD_TSCC[19:16]) + * | | |When decremented to 0, interrupt flag TOO (CANFD_IR[18]) is set and the timeout counter is stopped + * | | |Start and reset/restart conditions are configured via TOS (CANFD_TOCC[1:0]). + * @var CANFD_T::ECR + * Offset: 0x40 Error Counter Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[7:0] |TEC |Transmit Error Counter + * | | |Actual state of the Transmit Error Counter, values between 0 and 255. + * | | |Note: When ASM (CANFD_CCCR[2]) is set, the CAN protocol controller does not increment TEC and REC when a CAN protocol error is detected, but CEL is still incremented. + * |[14:8] |REC |Receive Error Counter + * | | |Actual state of the Receive Error Counter, values between 0 and 127. + * |[15] |RP |Receive Error Passive + * | | |0 = The Receive Error Counter is below the error passive level of 128. + * | | |1 = The Receive Error Counter has reached the error passive level of 128. + * |[23:16] |CEL |CAN Error Logging + * | | |The counter is incremented each time when a CAN protocol error causes the 8-bit Transmit Error Counter TEC or the 7-bit Receive Error Counter REC to be incremented + * | | |The counter is also incremented when the Bus_Off limit is reached + * | | |It is not incremented when only RP is set without changing REC + * | | |The increment of CEL follows after the increment of REC or TEC. + * | | |The counter is reset by read access to CEL + * | | |The counter stops at 0xFF; the next increment of TEC or REC sets interrupt flag ELO (CANFD_IR[22]). + * @var CANFD_T::PSR + * Offset: 0x44 Protocol Status Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[2:0] |LEC |Last Error Code + * | | |The LEC indicates the type of the last error to occur on the CAN bus + * | | |This field will be cleared to 0 when a message has been transferred (reception or transmission) without error. + * | | |000 = No Error: No error occurred since LEC has been reset by successful reception or transmission. + * | | |001 = Stuff Error: More than 5 equal bits in a sequence have occurred in a part of a received message where this is not allowed. + * | | |010 = Form Error: A fixed format part of a received frame has the wrong format. + * | | |011 = AckError: The message transmitted by the CANFD CONTROLLER was not acknowledged by another node. + * | | |100 = Bit1Error: During the transmission of a message (with the exception of the arbitration field), the device wanted to send a recessive level (bit of logical value 1), but the monitored bus value was dominant. + * | | |101 = Bit0Error : During the transmission of a message (or acknowledge bit, or active error flag, or overload flag), the device wanted to send a dominant level (data or identifier bit logical value 0), but the monitored bus value was recessive + * | | |During Bus_Off recovery this status is set each time a sequence of 11 recessive bits has been monitored + * | | |This enables the CPU to monitor the proceeding of the Bus_Off recovery sequence (indicating the bus is not stuck at dominant or continuously disturbed). + * | | |110 = CRCError: The CRC check sum of a received message was incorrect + * | | |The CRC of an incoming message does not match with the CRC calculated from the received data. + * | | |111 = NoChange: Any read access to the Protocol Status Register re-initializes the LEC to 7.When the LEC shows the value 7, no CAN bus event was detected since the last CPU read access to the Protocol Status Register. + * |[4:3] |ACT |Activity + * | | |Monitors the module's CAN communication state. + * | | |00 = Synchronizing - node is synchronizing on CAN communication. + * | | |01 = Idle - node is neither receiver nor transmitter. + * | | |10 = Receiver - node is operating as receiver. + * | | |11 = Transmitter - node is operating as transmitter. + * |[5] |EP |Error Passive + * | | |0 = The CAN FD controller is in the Error_Active state + * | | |It normally takes part in bus communication and sends an active error flag when an error has been detected. + * | | |1 = The CAN FD controller is in the Error_Passive state. + * |[6] |EW |Warning Status + * | | |0 = Both error counters are below the Error_Warning limit of 96. + * | | |1 = At least one of error counter has reached the Error_Warning limit of 96. + * |[7] |BO |Bus_Off Status + * | | |0 = The CAN FD controller is not Bus_Off. + * | | |1 = The CAN FD controller is in Bus_Off state. + * |[10:8] |DLEC |Data Phase Last Error Code + * | | |Type of last error that occurred in the data phase of a CAN FD format frame with its BRS flag set + * | | |Coding is the same as for LEC + * | | |This field will be cleared to 0 when a CAN FD format frame with its BRS flag set has been transferred (reception or transmission) without error. + * |[11] |RESI |ESI flag of last received CAN FD Message + * | | |This bit is set together with RFDF, independent of acceptance filtering. + * | | |0 = Last received CAN FD message did not have its ESI flag set. + * | | |1 = Last received CAN FD message had its ESI flag set. + * |[12] |RBRS |BRS flag of last received CAN FD Message + * | | |This bit is set together with RFDF, independent of acceptance filtering. + * | | |0 = Last received CAN FD message did not have its BRS flag set. + * | | |1 = Last received CAN FD message had its BRS flag set. + * | | |Note: Byte access: Reading byte 0 will reset RBRS, reading bytes 3/2/1 has no impact. + * |[13] |RFDF |Received a CAN FD Message + * | | |This bit is set independent of acceptance filtering. + * | | |0 = Since this bit was reset by the CPU, no CAN FD message has been received. + * | | |1 = Message in CAN FD format with FDF flag set has been received. + * | | |Note: Byte access: Reading byte 0 will reset RFDF, reading bytes 3/2/1 has no impact. + * |[14] |PXE |Protocol Exception Event + * | | |0 = No protocol exception event occurred since last read access. + * | | |1 = Protocol exception event occurred. + * |[22:16] |TDCV |Transmitter Delay Compensation Value + * | | |Position of the secondary sample point, defined by the sum of the measured delay from CANx_TXD to CANx_RXD and TDCO (TDCR[[14:8]) + * | | |The SSP position is, in the data phase, the number of minimum time quata (mtq) between the start of the transmitted bit and the secondary sample point + * | | |Valid values are 0 to 127 mtq. + * @var CANFD_T::TDCR + * Offset: 0x48 Transmitter Delay Compensation Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[6:0] |TDCF |Transmitter Delay Compensation Filter Window Length + * | | |Defines the minimum value for the SSP position, dominant edges on CANx_RXD that would result in an earlier SSP position are ignored for transmitter delay measurement + * | | |The feature is enabled when TDCF is configured to a value greater than TDCO + * | | |Valid values are 0 to 127 mtq. + * |[14:8] |TDCO |Transmitter Delay Compensation SSP Offset + * | | |Offset value defining the distance between the measured delay from CANx_TXD to CANx_RXD and the secondary sample point + * | | |Valid values are 0 to 127 mtq. + * @var CANFD_T::IR + * Offset: 0x50 Interrupt Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[0] |RF0N |Rx FIFO 0 New Message + * | | |0 = No new message written to Rx FIFO 0. + * | | |1 = New message written to Rx FIFO 0. + * |[1] |RF0W |Rx FIFO 0 Watermark Reached + * | | |0 = Rx FIFO 0 fill level below watermark. + * | | |1 = Rx FIFO 0 fill level reached watermark. + * |[2] |RF0F |Rx FIFO 0 Full + * | | |0 = Rx FIFO 0 not full. + * | | |1 = Rx FIFO 0 full. + * |[3] |RF0L |Rx FIFO 0 Message Lost + * | | |0 = No Rx FIFO 0 message lost. + * | | |1 = Rx FIFO 0 message lost, also set after write attempt to Rx FIFO 0 of size zero. + * |[4] |RF1N |Rx FIFO 1 New Message + * | | |0 = No new message written to Rx FIFO 1. + * | | |1 = New message written to Rx FIFO 1. + * |[5] |RF1W |Rx FIFO 1 Watermark Reached + * | | |0 = Rx FIFO 1 fill level below watermark. + * | | |1 = Rx FIFO 1 fill level reached watermark. + * |[6] |RF1F |Rx FIFO 1 Full + * | | |0 = Rx FIFO 1 not full. + * | | |1 = Rx FIFO 1 full. + * |[7] |RF1L |Rx FIFO 1 Message Lost + * | | |0 = No Rx FIFO 1 message lost. + * | | |1 = Rx FIFO 1 message lost, also set after write attempt to Rx FIFO 1 of size zero. + * |[8] |HPM |High Priority Message + * | | |0 = No high priority message received. + * | | |1 = High priority message received. + * |[9] |TC |Transmission Completed + * | | |0 = No transmission completed. + * | | |1 = Transmission completed. + * |[10] |TCF |Transmission Cancellation Finished + * | | |0 = No transmission cancellation finished. + * | | |1 = Transmission cancellation finished. + * |[11] |TFE |Tx FIFO Empty + * | | |0 = Tx FIFO non-empty. + * | | |1 = Tx FIFO empty. + * |[12] |TEFN |Tx Event FIFO New Entry + * | | |0 = Tx Event FIFO unchanged. + * | | |1 = Tx Handler wrote Tx Event FIFO element. + * |[13] |TEFW |Tx Event FIFO Watermark Reached + * | | |0 = Tx Event FIFO fill level below watermark. + * | | |1 = Tx Event FIFO fill level reached watermark. + * |[14] |TEFF |Tx Event FIFO Full + * | | |0 = Tx Event FIFO not full. + * | | |1 = Tx Event FIFO full. + * |[15] |TEFL |Tx Event FIFO Element Lost + * | | |0 = No Tx Event FIFO element lost. + * | | |1 = Tx Event FIFO element lost, also set after write attempt to Tx Event FIFO of size zero. + * |[16] |TSW |Timestamp Wraparound + * | | |0 = No timestamp counter wrap-around. + * | | |1 = Timestamp counter wrapped around. + * |[17] |MRAF |Message RAM Access Failure + * | | |The flag is set, when the Rx Handler + * | | |Has not completed acceptance filtering or storage of an accepted message until the arbitration field of the following message has been received + * | | |In this case acceptance filtering or message storage is aborted and the Rx Handler starts processing of the following message. + * | | |Was not able to write a message to the Message RAM. In this case message storage is aborted. + * | | |In both cases the FIFO put index is not updated resp + * | | |The New Data flag for a dedicated Rx Buffer is not set, a partly stored message is overwritten when the next message is stored to this location. + * | | |The flag is also set when the Tx Handler was not able to read a message from the Message RAM in time + * | | |In this case message transmission is aborted + * | | |In case of a Tx Handler access failure the CAN FD controller is switched into Restricted Operation Mode (refer to Restricted Operation Mode) + * | | |To leave Restricted Operation Mode, the Host CPU has to reset CANFD_ASM (CANFD_CCCR[2]). + * | | |0 = No Message RAM access failure occurred. + * | | |1 = Message RAM access failure occurred. + * |[18] |TOO |Timeout Occurred + * | | |0 = No timeout. + * | | |1 = Timeout reached. + * |[19] |DRX |Message stored to Dedicated Rx Buffer + * | | |The flag is set whenever a received message has been stored into a dedicated Rx Buffer. + * | | |0 = No Rx Buffer updated. + * | | |1 = At least one received message stored into an Rx Buffer. + * |[22] |ELO |Error Logging Overflow + * | | |0 = CAN Error Logging Counter did not overflow. + * | | |1 = Overflow of CAN Error Logging Counter occurred. + * |[23] |EP |Error Passive + * | | |0 = Error_Passive status unchanged. + * | | |1 = Error_Passive status changed. + * |[24] |EW |Warning Status + * | | |0 = Error_Warning status unchanged. + * | | |1 = Error_Warning status changed. + * |[25] |BO |Bus_Off Status + * | | |0 = Bus_Off status unchanged. + * | | |1 = Bus_Off status changed. + * |[26] |WDI |Watchdog Interrupt + * | | |0 = No Message RAM Watchdog event occurred. + * | | |1 = Message RAM Watchdog event due to missing READY. + * |[27] |PEA |Protocol Error in Arbitration Phase + * | | |0 = No protocol error in arbitration phase. + * | | |1 = Protocol error in arbitration phase detected (CANFD_LEC (CANFD_PSR[2:0]) no equal 0 or 7). + * | | |Note: Nominal bit time is used. + * |[28] |PED |Protocol Error in Data Phase + * | | |0 = No protocol error in data phase. + * | | |1 = Protocol error in data phase detected (DLEC (CANFD_PSR[10:8]) no equal 0 or 7). + * | | |Note: Data bit time is used. + * |[29] |ARA |Access to Reserved Address + * | | |0 = No access to reserved address occurred. + * | | |1 = Access to reserved address occurred. + * @var CANFD_T::IE + * Offset: 0x54 Interrupt Enable + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[0] |RF0NE |Rx FIFO 0 New Message Interrupt Enable + * | | |0 = Interrupt Disabled. + * | | |1 = Interrupt Enabled. + * |[1] |RF0WE |Rx FIFO 0 Watermark Reached Interrupt Enable + * | | |0 = Interrupt Disabled. + * | | |1 = Interrupt Enabled. + * |[2] |RF0FE |Rx FIFO 0 Full Interrupt Enable + * | | |0 = Interrupt Disabled. + * | | |1 = Interrupt Enabled. + * |[3] |RF0LE |Rx FIFO 0 Message Lost Interrupt Enable + * | | |0 = Interrupt Disabled. + * | | |1 = Interrupt Enabled. + * |[4] |RF1NE |Rx FIFO 1 New Message Interrupt Enable + * | | |0 = Interrupt Disabled. + * | | |1 = Interrupt Enabled. + * |[5] |RF1WE |Rx FIFO 1 Watermark Reached Interrupt Enable + * | | |0 = Interrupt Disabled. + * | | |1 = Interrupt Enabled. + * |[6] |RF1FE |Rx FIFO 1 Full Interrupt Enable + * | | |0 = Interrupt Disabled. + * | | |1 = Interrupt Enabled. + * |[7] |RF1LE |Rx FIFO 1 Message Lost Interrupt Enable + * | | |0 = Interrupt Disabled. + * | | |1 = Interrupt Enabled. + * |[8] |HPME |High Priority Message Interrupt Enable + * | | |0 = Interrupt Disabled. + * | | |1 = Interrupt Enabled. + * |[9] |TCE |Transmission Completed Interrupt Enable + * | | |0 = Interrupt Disabled. + * | | |1 = Interrupt Enabled. + * |[10] |TCFE |Transmission Cancellation Finished Interrupt Enable + * | | |0 = Interrupt Disabled. + * | | |1 = Interrupt Enabled. + * |[11] |TFEE |Tx FIFO Empty Interrupt Enable + * | | |0 = Interrupt Disabled. + * | | |1 = Interrupt Enabled. + * |[12] |TEFNE |Tx Event FIFO New Entry Interrupt Enable + * | | |0 = Interrupt Disabled. + * | | |1 = Interrupt Enabled. + * |[13] |TEFWE |Tx Event FIFO Watermark Reached Interrupt Enable + * | | |0 = Interrupt Disabled. + * | | |1 = Interrupt Enabled. + * |[14] |TEFFE |Tx Event FIFO Full Interrupt Enable + * | | |0 = Interrupt Disabled. + * | | |1 = Interrupt Enabled. + * |[15] |TEFLE |Tx Event FIFO Event Lost Interrupt Enable + * | | |0 = Interrupt Disabled. + * | | |1 = Interrupt Enabled. + * |[16] |TSWE |Timestamp Wraparound Interrupt Enable + * | | |0 = Interrupt Disabled. + * | | |1 = Interrupt Enabled. + * |[17] |MRAFE |Message RAM Access Failure Interrupt Enable + * | | |0 = Interrupt Disabled. + * | | |1 = Interrupt Enabled. + * |[18] |TOOE |Timeout Occurred Interrupt Enable + * | | |0 = Interrupt Disabled. + * | | |1 = Interrupt Enabled. + * |[19] |DRXE |Message stored to Dedicated Rx Buffer Interrupt Enable + * | | |0 = Interrupt Disabled. + * | | |1 = Interrupt Enabled. + * |[20] |BECE |Bit Error Corrected Interrupt Enable + * | | |0 = Interrupt Disabled. + * | | |1 = Interrupt Enabled. + * |[21] |BEUE |Bit Error Uncorrected Interrupt Enable + * | | |0 = Interrupt Disabled. + * | | |1 = Interrupt Enabled. + * |[22] |ELOE |Error Logging Overflow Interrupt Enable + * | | |0 = Interrupt Disabled. + * | | |1 = Interrupt Enabled. + * |[23] |EPE |Error Passive Interrupt Enable + * | | |0 = Interrupt Disabled. + * | | |1 = Interrupt Enabled. + * |[24] |EWE |Warning Status Interrupt Enable + * | | |0 = Interrupt Disabled. + * | | |1 = Interrupt Enabled. + * |[25] |BOE |Bus_Off Status Interrupt Enable + * | | |0 = Interrupt Disabled. + * | | |1 = Interrupt Enabled. + * |[26] |WDIE |Watchdog Interrupt Enable + * | | |0 = Interrupt Disabled. + * | | |1 = Interrupt Enabled. + * |[27] |PEAE |Protocol Error in Arbitration Phase Enable + * | | |0 = Interrupt Disabled. + * | | |1 = Interrupt Enabled. + * |[28] |PEDE |Protocol Error in Data Phase Enable + * | | |0 = Interrupt Disabled. + * | | |1 = Interrupt Enabled. + * |[29] |ARAE |Access to Reserved Address Enable + * | | |0 = Interrupt Disabled. + * | | |1 = Interrupt Enabled. + * @var CANFD_T::ILS + * Offset: 0x58 Interrupt Line Select + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[0] |RF0NL |Rx FIFO 0 New Message Interrupt Line + * | | |0 = Interrupt assigned to CAN interrupt line 0. + * | | |1 = Interrupt assigned to CAN interrupt line 1. + * |[1] |RF0WL |Rx FIFO 0 Watermark Reached Interrupt Line + * | | |0 = Interrupt assigned to CAN interrupt line 0. + * | | |1 = Interrupt assigned to CAN interrupt line 1. + * |[2] |RF0FL |Rx FIFO 0 Full Interrupt Line + * | | |0 = Interrupt assigned to CAN interrupt line 0. + * | | |1 = Interrupt assigned to CAN interrupt line 1. + * |[3] |RF0LL |Rx FIFO 0 Message Lost Interrupt Line + * | | |0 = Interrupt assigned to CAN interrupt line 0. + * | | |1 = Interrupt assigned to CAN interrupt line 1. + * |[4] |RF1NL |Rx FIFO 1 New Message Interrupt Line + * | | |0 = Interrupt assigned to CAN interrupt line 0. + * | | |1 = Interrupt assigned to CAN interrupt line 1. + * |[5] |RF1WL |Rx FIFO 1 Watermark Reached Interrupt Line + * | | |0 = Interrupt assigned to CAN interrupt line 0. + * | | |1 = Interrupt assigned to CAN interrupt line 1. + * |[6] |RF1FL |Rx FIFO 1 Full Interrupt Line + * | | |0 = Interrupt assigned to CAN interrupt line 0. + * | | |1 = Interrupt assigned to CAN interrupt line 1. + * |[7] |RF1LL |Rx FIFO 1 Message Lost Interrupt Line + * | | |0 = Interrupt assigned to CAN interrupt line 0. + * | | |1 = Interrupt assigned to CAN interrupt line 1. + * |[8] |HPML |High Priority Message Interrupt Line + * | | |0 = Interrupt assigned to CAN interrupt line 0. + * | | |1 = Interrupt assigned to CAN interrupt line 1. + * |[9] |TCL |Transmission Completed Interrupt Line + * | | |0 = Interrupt assigned to CAN interrupt line 0. + * | | |1 = Interrupt assigned to CAN interrupt line 1. + * |[10] |TCFL |Transmission Cancellation Finished Interrupt Line + * | | |0 = Interrupt assigned to CAN interrupt line 0. + * | | |1 = Interrupt assigned to CAN interrupt line 1. + * |[11] |TFEL |Tx FIFO Empty Interrupt Line + * | | |0 = Interrupt assigned to CAN interrupt line 0. + * | | |1 = Interrupt assigned to CAN interrupt line 1. + * |[12] |TEFNL |Tx Event FIFO New Entry Interrupt Line + * | | |0 = Interrupt assigned to CAN interrupt line 0. + * | | |1 = Interrupt assigned to CAN interrupt line 1. + * |[13] |TEFWL |Tx Event FIFO Watermark Reached Interrupt Line + * | | |0 = Interrupt assigned to CAN interrupt line 0. + * | | |1 = Interrupt assigned to CAN interrupt line 1. + * |[14] |TEFFL |Tx Event FIFO Full Interrupt Line + * | | |0 = Interrupt assigned to CAN interrupt line 0. + * | | |1 = Interrupt assigned to CAN interrupt line 1. + * |[15] |TEFLL |Tx Event FIFO Event Lost Interrupt Line + * | | |0 = Interrupt assigned to CAN interrupt line 0. + * | | |1 = Interrupt assigned to CAN interrupt line 1. + * |[16] |TSWL |Timestamp Wraparound Interrupt Line + * | | |0 = Interrupt assigned to CAN interrupt line 0. + * | | |1 = Interrupt assigned to CAN interrupt line 1. + * |[17] |MRAFL |Message RAM Access Failure Interrupt Line + * | | |0 = Interrupt assigned to CAN interrupt line 0. + * | | |1 = Interrupt assigned to CAN interrupt line 1. + * |[18] |TOOL |Timeout Occurred Interrupt Line + * | | |0 = Interrupt assigned to CAN interrupt line 0. + * | | |1 = Interrupt assigned to CAN interrupt line 1. + * |[19] |DRXL |Message stored to Dedicated Rx Buffer Interrupt Line + * | | |0 = Interrupt assigned to CAN interrupt line 0. + * | | |1 = Interrupt assigned to CAN interrupt line 1. + * |[22] |ELOL |Error Logging Overflow Interrupt Line + * | | |0 = Interrupt assigned to CAN interrupt line 0. + * | | |1 = Interrupt assigned to CAN interrupt line 1. + * |[23] |EPL |Error Passive Interrupt Line + * | | |0 = Interrupt assigned to CAN interrupt line 0. + * | | |1 = Interrupt assigned to CAN interrupt line 1. + * |[24] |EWL |Warning Status Interrupt Line + * | | |0 = Interrupt assigned to CAN interrupt line 0. + * | | |1 = Interrupt assigned to CAN interrupt line 1. + * |[25] |BOL |Bus_Off Status Interrupt Line + * | | |0 = Interrupt assigned to CAN interrupt line 0. + * | | |1 = Interrupt assigned to CAN interrupt line 1. + * |[26] |WDIL |Watchdog Interrupt Line + * | | |0 = Interrupt assigned to CAN interrupt line 0. + * | | |1 = Interrupt assigned to CAN interrupt line 1. + * |[27] |PEAL |Protocol Error in Arbitration Phase Line + * | | |0 = Interrupt assigned to CAN interrupt line 0. + * | | |1 = Interrupt assigned to CAN interrupt line 1. + * |[28] |PEDL |Protocol Error in Data Phase Line + * | | |0 = Interrupt assigned to CAN interrupt line 0. + * | | |1 = Interrupt assigned to CAN interrupt line 1. + * |[29] |ARAL |Access to Reserved Address Line + * | | |0 = Interrupt assigned to CAN interrupt line 0. + * | | |1 = Interrupt assigned to CAN interrupt line 1. + * @var CANFD_T::ILE + * Offset: 0x5C Interrupt Line Enable + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[0] |ENT0 |Enable Interrupt Line 0 + * | | |0 = Interrupt line canfd_int0 Disabled. + * | | |1 = Interrupt line canfd_int0 Enabled. + * |[1] |ENT1 |Enable Interrupt Line 1 + * | | |0 = Interrupt line canfd_int1 Disabled. + * | | |1 = Interrupt line canfd_int1 Enabled. + * @var CANFD_T::GFC + * Offset: 0x80 Global Filter Configuration + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[0] |RRFE |Reject Remote Frames Extended + * | | |0 = Filter remote frames with 29-bit extended IDs. + * | | |1 = Reject all remote frames with 29-bit extended IDs. + * |[1] |RRFS |Reject Remote Frames Standard + * | | |0 = Filter remote frames with 11-bit standard IDs. + * | | |1 = Reject all remote frames with 11-bit standard IDs. + * |[3:2] |ANFE |Accept Non-matching Frames Extended + * | | |Defines how received messages with 29-bit IDs that do not match any element of the filter list are treated. + * | | |00 = Accept in Rx FIFO 0. + * | | |01 = Accept in Rx FIFO 1. + * | | |10 = Reject. + * | | |11 = Reject. + * |[5:4] |ANFS |Accept Non-matching Frames Standard + * | | |Defines how received messages with 11-bit IDs that do not match any element of the filter list are treated. + * | | |00 = Accept in Rx FIFO 0. + * | | |01 = Accept in Rx FIFO 1. + * | | |10 = Reject. + * | | |11 = Reject. + * @var CANFD_T::SIDFC + * Offset: 0x84 Standard ID Filter Configuration + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[15:2] |FLSSA |Filter List Standard Start Address + * | | |Start address of standard Message ID filter list (32-bit word address, refer to Figure 6.33-11). + * |[23:16] |LSS |List Size Standard + * | | |0 = No standard Message ID filter. + * | | |1-128 = Number of standard Message ID filter elements. + * | | |>128 = Values greater than 128 are interpreted as 128. + * @var CANFD_T::XIDFC + * Offset: 0x88 Extended ID Filter Configuration + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[15:2] |FLESA |Filter List Extended Start Address + * | | |Start address of extended Message ID filter list (32-bit word address, refer to Figure 6.33-11). + * |[22:16] |LSE |List Size Extended + * | | |0 = No extended Message ID filter. + * | | |1-64 = Number of extended Message ID filter elements. + * | | |>64 = Values greater than 64 are interpreted as 64. + * @var CANFD_T::XIDAM + * Offset: 0x90 Extended ID AND Mask + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[28:0] |EIDM |Extended ID Mask + * | | |For acceptance filtering of extended frames the Extended ID AND Mask is ANDed with the Message ID of a received frame + * | | |Intended for masking of 29-bit IDs in SAE J1939 + * | | |With the reset value of all bits set to one the mask is not active. + * @var CANFD_T::HPMS + * Offset: 0x94 High Priority Message Status + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[5:0] |BIDX |Buffer Index + * | | |Index of Rx FIFO element to which the message was stored. Only valid when MSI[1] = 1. + * |[7:6] |MSI |Message Storage Indicator + * | | |00 = No FIFO selected. + * | | |01 = FIFO message lost. + * | | |10 = Message stored in FIFO 0. + * | | |11 = Message stored in FIFO 1. + * |[14:8] |FIDX |Filter Index + * | | |Index of matching filter element. Range is 0 to CANFD_SIDFC.LSS - 1 or CANFD_XIDFC.LSE - 1 + * |[15] |FLST |Filter List + * | | |Indicates the filter list of the matching filter element. + * | | |0 = Standard Filter List. + * | | |1 = Extended Filter List. + * @var CANFD_T::NDAT1 + * Offset: 0x98 New Data 1 + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[31:0] |NDn |New Data + * | | |The register holds the New Data flags of Rx Buffers 0 to 31 + * | | |The flags are set when the respective Rx Buffer has been updated from a received frame + * | | |The flags remain set until the Host clears them + * | | |A flag is cleared by writing a 1 to the corresponding bit position + * | | |Writing a 0 has no effect + * | | |A hard reset will clear the register. + * | | |0 = Rx Buffer not updated. + * | | |1 = Rx Buffer updated from new message. + * @var CANFD_T::NDAT2 + * Offset: 0x9C New Data 2 + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[31:0] |NDn |New Data + * | | |The register holds the New Data flags of Rx Buffers 32 to 63 + * | | |The flags are set when the respective Rx Buffer has been updated from a received frame + * | | |The flags remain set until the Host clears them + * | | |A flag is cleared by writing a 1 to the corresponding bit position + * | | |Writing a 0 has no effect + * | | |A hard reset will clear the register. + * | | |0 = Rx Buffer not updated. + * | | |1 = Rx Buffer updated from new message. + * @var CANFD_T::RXF0C + * Offset: 0xA0 Rx FIFO 0 Configuration + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[15:2] |F0SA |Rx FIFO 0 Start Address + * | | |Start address of Rx FIFO 0 in Message RAM (32-bit word address). + * |[22:16] |F0S |Rx FIFO 0 Size + * | | |0 = No Rx FIFO 0. + * | | |1-64 = Number of Rx FIFO 0 elements. + * | | |>64 = Values greater than 64 are interpreted as 64. + * | | |The Rx FIFO 0 elements are indexed from 0 to F0S-1 + * |[30:24] |F0WM |Rx FIFO 0 Watermark + * | | |0 = Watermark interrupt Disabled. + * | | |1-64 = Level for Rx FIFO 0 watermark interrupt (CANFD_IR.RF0W). + * | | |>64 = Watermark interrupt Disabled. + * |[31] |F0OM |FIFO 0 Operation Mode + * | | |FIFO 0 can be operated in blocking or in overwrite mode (refer to Rx FIFOs). + * | | |0 = FIFO 0 blocking mode. + * | | |1 = FIFO 0 overwrite mode. + * @var CANFD_T::RXF0S + * Offset: 0xA4 Rx FIFO 0 Status + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[6:0] |F0FL |Rx FIFO 0 Fill Level + * | | |Number of elements stored in Rx FIFO 0, range 0 to 64 + * |[13:8] |F0GI |Rx FIFO 0 Get Index + * | | |Rx FIFO 0 read index pointer, range 0 to 63. + * |[21:16] |F0PI |Rx FIFO 0 Put Index + * | | |Rx FIFO 0 write index pointer, range 0 to 63. + * |[24] |F0F |Rx FIFO 0 Full + * | | |0 = Rx FIFO 0 not full. + * | | |1 = Rx FIFO 0 full. + * |[25] |RF0L |Rx FIFO 0 Message Lost + * | | |This bit is a copy of interrupt flag CANFD_IR.RF0L + * | | |When CANFD_IR.RF0L is reset, this bit is also reset + * | | |0 = No Rx FIFO 0 message lost. + * | | |1 = Rx FIFO 0 message lost, also set after write attempt to Rx FIFO 0 of size zero. + * | | |Note: Overwriting the oldest message when F0OM (CANFD_RXF0C[31]) = 1 will not set this flag. + * @var CANFD_T::RXF0A + * Offset: 0xA8 Rx FIFO 0 Acknowledge + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[5:0] |F0A |Rx FIFO 0 Acknowledge Index + * | | |After the Host has read a message or a sequence of messages from Rx FIFO 0 it has to write the buffer index of the last element read from Rx FIFO 0 to F0AI + * | | |This will set the Rx FIFO 0 Get Index F0GI (CANFD_RXF0S[13:8]) to F0AI (CANFD_RXF0A[5:0]) + 1 and update the FIFO 0 Fill Level CANFD_RXF0S.F0FL. + * @var CANFD_T::RXBC + * Offset: 0xAC Rx Buffer Configuration + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[15:2] |RBSA |Rx Buffer Start Address + * | | |Configures the start address of the Rx Buffers section in the Message RAM (32-bit word address). + * @var CANFD_T::RXF1C + * Offset: 0xB0 Rx FIFO 1 Configuration + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[15:2] |F1SA |Rx FIFO 1 Start Address + * | | |Start address of Rx FIFO 1 in Message RAM (32-bit word address, refer to Figure 6.33-11). + * |[22:16] |F1S |Rx FIFO 1 Size + * | | |0 = No Rx FIFO 1. + * | | |1-64 = Number of Rx FIFO 1 elements. + * | | |>64 = Values greater than 64 are interpreted as 64. + * | | |The Rx FIFO 1 elements are indexed from 0 to F1S - 1 + * |[30:24] |F1WM |Rx FIFO 1 Watermark + * | | |0 = Watermark interrupt Disabled. + * | | |1-64 = Level for Rx FIFO 1 watermark interrupt (CANFD_IR.RF1W). + * | | |>64 = Watermark interrupt Disabled. + * |[31] |F1OM |FIFO 1 Operation Mode + * | | |FIFO 1 can be operated in blocking or in overwrite mode (refer to Rx FIFOs). + * | | |0 = FIFO 1 blocking mode. + * | | |1 = FIFO 1 overwrite mode. + * @var CANFD_T::RXF1S + * Offset: 0xB4 Rx FIFO 1 Status + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[6:0] |F1FL |Rx FIFO 1 Fill Level + * | | |Number of elements stored in Rx FIFO 1, range 0 to 64 + * |[13:8] |F1G |Rx FIFO 1 Get Index + * | | |Rx FIFO 1 read index pointer, range 0 to 63. + * |[21:16] |F1P |Rx FIFO 1 Fill Level + * | | |Number of elements stored in Rx FIFO 1, range 0 to 64. + * |[24] |F1F |Rx FIFO 1 Full + * | | |0 = Rx FIFO 1 not full. + * | | |1 = Rx FIFO 1 full. + * |[25] |RF1L |Rx FIFO 1 Message Lost + * | | |This bit is a copy of interrupt flag CANFD_IR.RF1L + * | | |When CANFD_IR.RF1L is reset, this bit is also reset + * | | |0 = No Rx FIFO 1 message lost. + * | | |1 = Rx FIFO 1 message lost, also set after write attempt to Rx FIFO 1 of size zero. + * | | |Note: Overwriting the oldest message when F1OM (CANFD_RXF1C[31]) = 1 will not set this flag. + * @var CANFD_T::RXF1A + * Offset: 0xB8 Rx FIFO 1 Acknowledge + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[5:0] |F1A |Rx FIFO 1 Acknowledge Index + * | | |After the Host has read a message or a sequence of messages from Rx FIFO 1 it has to write the buffer index of the last element read from Rx FIFO 1 to F1AI + * | | |This will set the Rx FIFO 1 Get Index F1GI (CANFD_RXF1S[13:8]) to F1AI (CANFD_RXF1A[5:0]) + 1 and update the FIFO 1 Fill Level F1FL (CANFD_RXF1S[6:0]). + * @var CANFD_T::RXESC + * Offset: 0xBC Rx Buffer / FIFO Element Size Configuration + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[2:0] |F0DS |Rx FIFO 0 Data Field Size + * | | |000 = 8 byte data field. + * | | |001 = 12 byte data field. + * | | |010 = 16 byte data field. + * | | |011 = 20 byte data field. + * | | |100 = 24 byte data field. + * | | |101 = 32 byte data field. + * | | |110 = 48 byte data field. + * | | |111 = 64 byte data field. + * | | |Note: In case the data field size of an accepted CAN frame exceeds the data field size configured for the matching Rx Buffer or Rx FIFO, only the number of bytes as configured by CANFD_RXESC are stored to the Rx Buffer resp + * | | |Rx FIFO element + * | | |The rest of the frame data field is ignored. + * |[6:4] |F1DS |Rx FIFO 1 Data Field Size + * | | |000 = 8 byte data field. + * | | |001 = 12 byte data field. + * | | |010 = 16 byte data field. + * | | |011 = 20 byte data field. + * | | |100 = 24 byte data field. + * | | |101 = 32 byte data field. + * | | |110 = 48 byte data field. + * | | |111 = 64 byte data field. + * |[10:8] |RBDS |Rx Buffer Data Field Size + * | | |000 = 8 byte data field. + * | | |001 = 12 byte data field. + * | | |010 = 16 byte data field. + * | | |011 = 20 byte data field. + * | | |100 = 24 byte data field. + * | | |101 = 32 byte data field. + * | | |110 = 48 byte data field. + * | | |111 = 64 byte data field. + * @var CANFD_T::TXBC + * Offset: 0xC0 Tx Buffer Configuration + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[15:2] |TBSA |Tx Buffers Start Address + * | | |Start address of Tx Buffers section in Message RAM (32-bit word address, refer to Figure 6.33-11). + * | | |Note: The sum of TFQS and NDTB may be not greater than 32 + * | | |There is no check for erroneous configurations + * | | |The Tx Buffers section in the Message RAM starts with the dedicated Tx Buffers. + * |[21:16] |NDTB |Number of Dedicated Transmit Buffers + * | | |0 = No Dedicated Tx Buffers. + * | | |1-32 = Number of Dedicated Tx Buffers. + * | | |>32 = Values greater than 32 are interpreted as 32. + * |[29:24] |TFQS |Transmit FIFO/Queue Size + * | | |0 = No Tx FIFO/Queue. + * | | |1-32 = Number of Tx Buffers used for Tx FIFO/Queue. + * | | |>32 = Values greater than 32 are interpreted as 32. + * |[30] |TFQM |Tx FIFO/Queue Mode + * | | |0 = Tx FIFO operation. + * | | |1 = Tx Queue operation. + * @var CANFD_T::TXFQS + * Offset: 0xC4 Tx FIFO/Queue Status + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[5:0] |TFFL |Tx FIFO Free Level + * | | |Number of consecutive free Tx FIFO elements starting from TFGI, range 0 to 32 + * | | |Read as 0 when Tx Queue operation is configured (TFQM (CANFD_TXBC[3]) = 1). + * | | |Note: In case of mixed configurations where dedicated Tx Buffers are combined with a Tx FIFO or a Tx Queue, the Put and Get Indices indicate the number of the Tx Buffer starting with the first dedicated Tx Buffers. + * | | |Example: For a configuration of 12 dedicated Tx Buffers and a Tx FIFO of 20 Buffers a Put Index of 15 points to the fourth buffer of the Tx FIFO. + * |[12:8] |TFG |Tx FIFO Get Index + * | | |Tx FIFO read index pointer, range 0 to 31 + * | | |Read as 0 when Tx Queue operation is configured (TFQM (CANFD_TXBC[30]) = 1). + * |[20:16] |TFQP |Tx FIFO/Queue Put Index + * | | |Tx FIFO/Queue write index pointer, range 0 to 31. + * |[21] |TFQF |Tx FIFO/Queue Full + * | | |0 = Tx FIFO/Queue not full. + * | | |1 = Tx FIFO/Queue full. + * @var CANFD_T::TXESC + * Offset: 0xC8 Tx Buffer Element Size Configuration + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[2:0] |TBDS |Tx Buffer Data Field Size + * | | |000 = 8 byte data field. + * | | |001 = 12 byte data field. + * | | |010 = 16 byte data field. + * | | |011 = 20 byte data field. + * | | |100 = 24 byte data field. + * | | |101 = 32 byte data field. + * | | |110 = 48 byte data field. + * | | |111 = 64 byte data field. + * | | |Note: In case the data length code DLC of a Tx Buffer element is configured to a value higher than the Tx Buffer data field size CANFD_TXESC.TBDS, the bytes not defined by the Tx Buffer are transmitted as 0xCC (padding bytes). + * @var CANFD_T::TXBRP + * Offset: 0xCC Tx Buffer Request Pending + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[31:0] |TRPn |Transmission Request Pending Each Tx Buffer has its own Transmission Request Pending bit The bits are set via register CANFD_TXBAR The bits are reset after a requested transmission has completed or has been cancelled via register CANFD_TXBCR + * | | |CANFD_TXBRP bits are set only for those Tx Buffers configured via CANFD_TXBC + * | | |After a CANFD_TXBRP bit has been set, a Tx scan (refer to section 6.33.5.5, Tx Handling) is started to check for the pending Tx request with the highest priority (Tx Buffer with lowest Message ID). + * | | |A cancellation request resets the corresponding transmission request pending bit of register CANFD_TXBRP + * | | |In case a transmission has already been started when a cancellation is requested, this is done at the end of the transmission, regardless whether the transmission was successful or not + * | | |The cancellation request bits are reset directly after the corresponding CANFD_TXBRP bit has been reset. + * | | |After a cancellation has been requested, a finished cancellation is signaled via CANFD_TXBCF + * | | |- after successful transmission together with the corresponding CANFD_TXBTO bit + * | | |- when the transmission has not yet been started at the point of cancellation + * | | |- when the transmission has been aborted due to lost arbitration + * | | |- when an error occurred during frame transmission + * | | |In DAR mode all transmissions are automatically cancelled if they are not successful + * | | |The corresponding CANFD_TXBCF bit is set for all unsuccessful transmissions. + * | | |0 = No transmission request pending. + * | | |1 = Transmission request pending. + * | | |Note: CANFD_TXBRP bits which are set while a Tx scan is in progress are not considered during this particular Tx scan + * | | |In case a cancellation is requested for such a Tx Buffer, this Add Request is cancelled immediately, the corresponding CANFD_TXBRP bit is reset. + * @var CANFD_T::TXBAR + * Offset: 0xD0 Tx Buffer Add Request + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[31:0] |ARn |Add Request Each Tx Buffer has its own Add Request bit Writing a 1 will set the corresponding Add Request bit; writing a 0 has no impact This enables the Host to set transmission requests for multiple Tx Buffers with one write to CANFD_TXBAR CANFD_TXBAR bits are set only for those Tx Buffers configured via CANFD_TXBC + * | | |When no Tx scan is running, the bits are reset immediately, else the bits remain set until the Tx scan process has completed + * | | |0 = No transmission request added. + * | | |1 = Transmission requested added. + * | | |Note: If an add request is applied for a Tx Buffer with pending transmission request (corresponding CANFD_TXBRP bit already set), this add request is ignored. + * @var CANFD_T::TXBCR + * Offset: 0xD4 Tx Buffer Cancellation Request + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[31:0] |CRn |Cancellation Request + * | | |Each Tx Buffer has its own Cancellation Request bit + * | | |Writing a 1 will set the corresponding Cancellation Request bit; writing a 0 has no impact + * | | |This enables the Host to set cancellation requests for multiple Tx Buffers with one write to CANFD_TXBCR + * | | |CANFD_TXBCR bits are set only for those Tx Buffers configured via CANFD_TXBC + * | | |The bits remain set until the corresponding bit of CANFD_TXBRP is reset. + * | | |0 = No cancellation pending. + * | | |1 = Cancellation pending. + * @var CANFD_T::TXBTO + * Offset: 0xD8 Tx Buffer Transmission Occurred + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[31:0] |TOn |Transmission Occurred + * | | |Each Tx Buffer has its own Transmission Occurred bit + * | | |The bits are set when the corresponding CANFD_TXBRP bit is cleared after a successful transmission + * | | |The bits are reset when a new transmission is requested by writing a 1 to the corresponding bit of register CANFD_TXBAR. + * | | |0 = No transmission occurred. + * | | |1 = Transmission occurred. + * @var CANFD_T::TXBCF + * Offset: 0xDC Tx Buffer Cancellation Finished + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[31:0] |CFn |Cancellation Finished + * | | |Each Tx Buffer has its own Cancellation Finished bit + * | | |The bits are set when the corresponding CANFD_TXBRP bit is cleared after a cancellation was requested via CANFD_TXBCR + * | | |In case the corresponding CANFD_TXBRP bit was not set at the point of cancellation, CF is set immediately + * | | |The bits are reset when a new transmission is requested by writing a 1 to the corresponding bit of register CANFD_TXBAR. + * | | |0 = No transmit buffer cancellation. + * | | |1 = Transmit buffer cancellation finished. + * @var CANFD_T::TXBTIE + * Offset: 0xE0 Tx Buffer Transmission Interrupt Enable + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[31:0] |TIEn |Transmission Interrupt Enable + * | | |Each Tx Buffer has its own Transmission Interrupt Enable bit. + * | | |0 = Transmission interrupt Disabled. + * | | |1 = Transmission interrupt Enabled. + * @var CANFD_T::TXBCIE + * Offset: 0xE4 Tx Buffer Cancellation Finished Interrupt Enable + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[31:0] |CFIEn |Cancellation Finished Interrupt Enable + * | | |Each Tx Buffer has its own Cancellation Finished Interrupt Enable bit. + * | | |0 = Cancellation finished interrupt Disabled. + * | | |1 = Cancellation finished interrupt Enabled. + * @var CANFD_T::TXEFC + * Offset: 0xF0 Tx Event FIFO Configuration + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[15:2] |EFSA |Event FIFO Start Address + * | | |Start address of Tx Event FIFO in Message RAM (32-bit word address, refer to Figure 6.33-11). + * |[21:16] |EFS |Event FIFO Size + * | | |0 = Tx Event FIFO Disabled. + * | | |1-32 = Number of Tx Event FIFO elements. + * | | |>32 = Values greater than 32 are interpreted as 32. + * | | |The Tx Event FIFO elements are indexed from 0 to EFS - 1 + * |[29:24] |EFWN |Event FIFO Watermark + * | | |0 = Watermark interrupt Disabled. + * | | |1-32 = Level for Tx Event FIFO watermark interrupt (TEFW (CANFD_IR[13])). + * | | |>32 = Watermark interrupt Disabled. + * @var CANFD_T::TXEFS + * Offset: 0xF4 Tx Event FIFO Status + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[5:0] |EFFL |Event FIFO Fill Level + * | | |Number of elements stored in Tx Event FIFO, range 0 to 32 + * |[12:8] |EFG |Event FIFO Get Index + * | | |Tx Event FIFO read index pointer, range 0 to 31 + * |[20:16] |EFP |Event FIFO Put Index + * | | |Tx Event FIFO write index pointer, range 0 to 31 + * |[24] |EFF |Event FIFO Full + * | | |0 = Tx Event FIFO not full. + * | | |1 = Tx Event FIFO full. + * |[25] |TEFL |Tx Event FIFO Element Lost + * | | |This bit is a copy of interrupt flag TEFL (CANFD_IR[15]). When TEFL is reset, this bit is also reset. + * | | |0 = No Tx Event FIFO element lost. + * | | |1 = Tx Event FIFO element lost, also set after write attempt to Tx Event FIFO of size zero. + * @var CANFD_T::TXEFA + * Offset: 0xF8 Tx Event FIFO Acknowledge + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[4:0] |EFA |Event FIFO Acknowledge Index + * | | |After the Host has read an element or a sequence of elements from the Tx Event FIFO it has to write the index of the last element read from Tx Event FIFO to EFAI + * | | |This will set the Tx Event FIFO Get Index EFGI (CANFD_TXEFS[12:8]) to EFAI + 1 and update the Event FIFO Fill Level EFFL (CANFD_TXEFS[5:0]) + */ + __I uint32_t RESERVE0[3]; + __IO uint32_t DBTP; /*!< [0x000c] Data Bit Timing & Prescaler Register */ + __IO uint32_t TEST; /*!< [0x0010] Test Register */ + __IO uint32_t RWD; /*!< [0x0014] RAM Watchdog */ + __IO uint32_t CCCR; /*!< [0x0018] CC Control Register */ + __IO uint32_t NBTP; /*!< [0x001c] Nominal Bit Timing & Prescaler Register */ + __IO uint32_t TSCC; /*!< [0x0020] Timestamp Counter Configuration */ + __IO uint32_t TSCV; /*!< [0x0024] Timestamp Counter Value */ + __IO uint32_t TOCC; /*!< [0x0028] Timeout Counter Configuration */ + __IO uint32_t TOCV; /*!< [0x002c] Timeout Counter Value */ + __I uint32_t RESERVE1[4]; + __IO uint32_t ECR; /*!< [0x0040] Error Counter Register */ + __IO uint32_t PSR; /*!< [0x0044] Protocol Status Register */ + __IO uint32_t TDCR; /*!< [0x0048] Transmitter Delay Compensation Register */ + __I uint32_t RESERVE2[1]; + __IO uint32_t IR; /*!< [0x0050] Interrupt Register */ + __IO uint32_t IE; /*!< [0x0054] Interrupt Enable */ + __IO uint32_t ILS; /*!< [0x0058] Interrupt Line Select */ + __IO uint32_t ILE; /*!< [0x005c] Interrupt Line Enable */ + __I uint32_t RESERVE3[8]; + __IO uint32_t GFC; /*!< [0x0080] Global Filter Configuration */ + __IO uint32_t SIDFC; /*!< [0x0084] Standard ID Filter Configuration */ + __IO uint32_t XIDFC; /*!< [0x0088] Extended ID Filter Configuration */ + __I uint32_t RESERVE4[1]; + __IO uint32_t XIDAM; /*!< [0x0090] Extended ID AND Mask */ + __I uint32_t HPMS; /*!< [0x0094] High Priority Message Status */ + __IO uint32_t NDAT1; /*!< [0x0098] New Data 1 */ + __IO uint32_t NDAT2; /*!< [0x009c] New Data 2 */ + __IO uint32_t RXF0C; /*!< [0x00a0] Rx FIFO 0 Configuration */ + __I uint32_t RXF0S; /*!< [0x00a4] Rx FIFO 0 Status */ + __IO uint32_t RXF0A; /*!< [0x00a8] Rx FIFO 0 Acknowledge */ + __IO uint32_t RXBC; /*!< [0x00ac] Rx Buffer Configuration */ + __IO uint32_t RXF1C; /*!< [0x00b0] Rx FIFO 1 Configuration */ + __I uint32_t RXF1S; /*!< [0x00b4] Rx FIFO 1 Status */ + __IO uint32_t RXF1A; /*!< [0x00b8] Rx FIFO 1 Acknowledge */ + __IO uint32_t RXESC; /*!< [0x00bc] Rx Buffer / FIFO Element Size Configuration */ + __IO uint32_t TXBC; /*!< [0x00c0] Tx Buffer Configuration */ + __I uint32_t TXFQS; /*!< [0x00c4] Tx FIFO/Queue Status */ + __IO uint32_t TXESC; /*!< [0x00c8] Tx Buffer Element Size Configuration */ + __I uint32_t TXBRP; /*!< [0x00cc] Tx Buffer Request Pending */ + __IO uint32_t TXBAR; /*!< [0x00d0] Tx Buffer Add Request */ + __IO uint32_t TXBCR; /*!< [0x00d4] Tx Buffer Cancellation Request */ + __I uint32_t TXBTO; /*!< [0x00d8] Tx Buffer Transmission Occurred */ + __I uint32_t TXBCF; /*!< [0x00dc] Tx Buffer Cancellation Finished */ + __IO uint32_t TXBTIE; /*!< [0x00e0] Tx Buffer Transmission Interrupt Enable */ + __IO uint32_t TXBCIE; /*!< [0x00e4] Tx Buffer Cancellation Finished Interrupt Enable */ + __I uint32_t RESERVE5[2]; + __IO uint32_t TXEFC; /*!< [0x00f0] Tx Event FIFO Configuration */ + __I uint32_t TXEFS; /*!< [0x00f4] Tx Event FIFO Status */ + __IO uint32_t TXEFA; /*!< [0x00f8] Tx Event FIFO Acknowledge */ + +} CANFD_T; + +/** + @addtogroup CANFD_CONST CANFD Bit Field Definition + Constant Definitions for CANFD Controller +@{ */ + +#define CANFD_DBTP_DSJW_Pos (0) /*!< CANFD_T::DBTP: DSJW Position */ +#define CANFD_DBTP_DSJW_Msk (0xful << CANFD_DBTP_DSJW_Pos) /*!< CANFD_T::DBTP: DSJW Mask */ + +#define CANFD_DBTP_DTSEG2_Pos (4) /*!< CANFD_T::DBTP: DTSEG2 Position */ +#define CANFD_DBTP_DTSEG2_Msk (0xful << CANFD_DBTP_DTSEG2_Pos) /*!< CANFD_T::DBTP: DTSEG2 Mask */ + +#define CANFD_DBTP_DTSEG1_Pos (8) /*!< CANFD_T::DBTP: DTSEG1 Position */ +#define CANFD_DBTP_DTSEG1_Msk (0x1ful << CANFD_DBTP_DTSEG1_Pos) /*!< CANFD_T::DBTP: DTSEG1 Mask */ + +#define CANFD_DBTP_DBRP_Pos (16) /*!< CANFD_T::DBTP: DBRP Position */ +#define CANFD_DBTP_DBRP_Msk (0x1ful << CANFD_DBTP_DBRP_Pos) /*!< CANFD_T::DBTP: DBRP Mask */ + +#define CANFD_DBTP_TDC_Pos (23) /*!< CANFD_T::DBTP: TDC Position */ +#define CANFD_DBTP_TDC_Msk (0x1ul << CANFD_DBTP_TDC_Pos) /*!< CANFD_T::DBTP: TDC Mask */ + +#define CANFD_TEST_LBCK_Pos (4) /*!< CANFD_T::TEST: LBCK Position */ +#define CANFD_TEST_LBCK_Msk (0x1ul << CANFD_TEST_LBCK_Pos) /*!< CANFD_T::TEST: LBCK Mask */ + +#define CANFD_TEST_TX_Pos (5) /*!< CANFD_T::TEST: TX Position */ +#define CANFD_TEST_TX_Msk (0x3ul << CANFD_TEST_TX_Pos) /*!< CANFD_T::TEST: TX Mask */ + +#define CANFD_TEST_RX_Pos (7) /*!< CANFD_T::TEST: RX Position */ +#define CANFD_TEST_RX_Msk (0x1ul << CANFD_TEST_RX_Pos) /*!< CANFD_T::TEST: RX Mask */ + +#define CANFD_RWD_WDC_Pos (0) /*!< CANFD_T::RWD: WDC Position */ +#define CANFD_RWD_WDC_Msk (0xfful << CANFD_RWD_WDC_Pos) /*!< CANFD_T::RWD: WDC Mask */ + +#define CANFD_RWD_WDV_Pos (8) /*!< CANFD_T::RWD: WDV Position */ +#define CANFD_RWD_WDV_Msk (0xfful << CANFD_RWD_WDV_Pos) /*!< CANFD_T::RWD: WDV Mask */ + +#define CANFD_CCCR_INIT_Pos (0) /*!< CANFD_T::CCCR: INIT Position */ +#define CANFD_CCCR_INIT_Msk (0x1ul << CANFD_CCCR_INIT_Pos) /*!< CANFD_T::CCCR: INIT Mask */ + +#define CANFD_CCCR_CCE_Pos (1) /*!< CANFD_T::CCCR: CCE Position */ +#define CANFD_CCCR_CCE_Msk (0x1ul << CANFD_CCCR_CCE_Pos) /*!< CANFD_T::CCCR: CCE Mask */ + +#define CANFD_CCCR_ASM_Pos (2) /*!< CANFD_T::CCCR: ASM Position */ +#define CANFD_CCCR_ASM_Msk (0x1ul << CANFD_CCCR_ASM_Pos) /*!< CANFD_T::CCCR: ASM Mask */ + +#define CANFD_CCCR_CSA_Pos (3) /*!< CANFD_T::CCCR: CSA Position */ +#define CANFD_CCCR_CSA_Msk (0x1ul << CANFD_CCCR_CSA_Pos) /*!< CANFD_T::CCCR: CSA Mask */ + +#define CANFD_CCCR_CSR_Pos (4) /*!< CANFD_T::CCCR: CSR Position */ +#define CANFD_CCCR_CSR_Msk (0x1ul << CANFD_CCCR_CSR_Pos) /*!< CANFD_T::CCCR: CSR Mask */ + +#define CANFD_CCCR_MON_Pos (5) /*!< CANFD_T::CCCR: MON Position */ +#define CANFD_CCCR_MON_Msk (0x1ul << CANFD_CCCR_MON_Pos) /*!< CANFD_T::CCCR: MON Mask */ + +#define CANFD_CCCR_DAR_Pos (6) /*!< CANFD_T::CCCR: DAR Position */ +#define CANFD_CCCR_DAR_Msk (0x1ul << CANFD_CCCR_DAR_Pos) /*!< CANFD_T::CCCR: DAR Mask */ + +#define CANFD_CCCR_TEST_Pos (7) /*!< CANFD_T::CCCR: TEST Position */ +#define CANFD_CCCR_TEST_Msk (0x1ul << CANFD_CCCR_TEST_Pos) /*!< CANFD_T::CCCR: TEST Mask */ + +#define CANFD_CCCR_FDOE_Pos (8) /*!< CANFD_T::CCCR: FDOE Position */ +#define CANFD_CCCR_FDOE_Msk (0x1ul << CANFD_CCCR_FDOE_Pos) /*!< CANFD_T::CCCR: FDOE Mask */ + +#define CANFD_CCCR_BRSE_Pos (9) /*!< CANFD_T::CCCR: BRSE Position */ +#define CANFD_CCCR_BRSE_Msk (0x1ul << CANFD_CCCR_BRSE_Pos) /*!< CANFD_T::CCCR: BRSE Mask */ + +#define CANFD_CCCR_PXHD_Pos (12) /*!< CANFD_T::CCCR: PXHD Position */ +#define CANFD_CCCR_PXHD_Msk (0x1ul << CANFD_CCCR_PXHD_Pos) /*!< CANFD_T::CCCR: PXHD Mask */ + +#define CANFD_CCCR_EFBI_Pos (13) /*!< CANFD_T::CCCR: EFBI Position */ +#define CANFD_CCCR_EFBI_Msk (0x1ul << CANFD_CCCR_EFBI_Pos) /*!< CANFD_T::CCCR: EFBI Mask */ + +#define CANFD_CCCR_TXP_Pos (14) /*!< CANFD_T::CCCR: TXP Position */ +#define CANFD_CCCR_TXP_Msk (0x1ul << CANFD_CCCR_TXP_Pos) /*!< CANFD_T::CCCR: TXP Mask */ + +#define CANFD_CCCR_NISO_Pos (15) /*!< CANFD_T::CCCR: NISO Position */ +#define CANFD_CCCR_NISO_Msk (0x1ul << CANFD_CCCR_NISO_Pos) /*!< CANFD_T::CCCR: NISO Mask */ + +#define CANFD_NBTP_NTSEG2_Pos (0) /*!< CANFD_T::NBTP: NTSEG2 Position */ +#define CANFD_NBTP_NTSEG2_Msk (0x7ful << CANFD_NBTP_NTSEG2_Pos) /*!< CANFD_T::NBTP: NTSEG2 Mask */ + +#define CANFD_NBTP_NTSEG1_Pos (8) /*!< CANFD_T::NBTP: NTSEG1 Position */ +#define CANFD_NBTP_NTSEG1_Msk (0xfful << CANFD_NBTP_NTSEG1_Pos) /*!< CANFD_T::NBTP: NTSEG1 Mask */ + +#define CANFD_NBTP_NBRP_Pos (16) /*!< CANFD_T::NBTP: NBRP Position */ +#define CANFD_NBTP_NBRP_Msk (0x1fful << CANFD_NBTP_NBRP_Pos) /*!< CANFD_T::NBTP: NBRP Mask */ + +#define CANFD_NBTP_NSJW_Pos (25) /*!< CANFD_T::NBTP: NSJW Position */ +#define CANFD_NBTP_NSJW_Msk (0x7ful << CANFD_NBTP_NSJW_Pos) /*!< CANFD_T::NBTP: NSJW Mask */ + +#define CANFD_TSCC_TSS_Pos (0) /*!< CANFD_T::TSCC: TSS Position */ +#define CANFD_TSCC_TSS_Msk (0x3ul << CANFD_TSCC_TSS_Pos) /*!< CANFD_T::TSCC: TSS Mask */ + +#define CANFD_TSCC_TCP_Pos (16) /*!< CANFD_T::TSCC: TCP Position */ +#define CANFD_TSCC_TCP_Msk (0xful << CANFD_TSCC_TCP_Pos) /*!< CANFD_T::TSCC: TCP Mask */ + +#define CANFD_TSCV_TSC_Pos (0) /*!< CANFD_T::TSCV: TSC Position */ +#define CANFD_TSCV_TSC_Msk (0xfffful << CANFD_TSCV_TSC_Pos) /*!< CANFD_T::TSCV: TSC Mask */ + +#define CANFD_TOCC_ETOC_Pos (0) /*!< CANFD_T::TOCC: ETOC Position */ +#define CANFD_TOCC_ETOC_Msk (0x1ul << CANFD_TOCC_ETOC_Pos) /*!< CANFD_T::TOCC: ETOC Mask */ + +#define CANFD_TOCC_TOS_Pos (1) /*!< CANFD_T::TOCC: TOS Position */ +#define CANFD_TOCC_TOS_Msk (0x3ul << CANFD_TOCC_TOS_Pos) /*!< CANFD_T::TOCC: TOS Mask */ + +#define CANFD_TOCC_TOP_Pos (16) /*!< CANFD_T::TOCC: TOP Position */ +#define CANFD_TOCC_TOP_Msk (0xfffful << CANFD_TOCC_TOP_Pos) /*!< CANFD_T::TOCC: TOP Mask */ + +#define CANFD_TOCV_TOC_Pos (0) /*!< CANFD_T::TOCV: TOC Position */ +#define CANFD_TOCV_TOC_Msk (0xfffful << CANFD_TOCV_TOC_Pos) /*!< CANFD_T::TOCV: TOC Mask */ + +#define CANFD_ECR_TEC_Pos (0) /*!< CANFD_T::ECR: TEC Position */ +#define CANFD_ECR_TEC_Msk (0xfful << CANFD_ECR_TEC_Pos) /*!< CANFD_T::ECR: TEC Mask */ + +#define CANFD_ECR_REC_Pos (8) /*!< CANFD_T::ECR: REC Position */ +#define CANFD_ECR_REC_Msk (0x7ful << CANFD_ECR_REC_Pos) /*!< CANFD_T::ECR: REC Mask */ + +#define CANFD_ECR_RP_Pos (15) /*!< CANFD_T::ECR: RP Position */ +#define CANFD_ECR_RP_Msk (0x1ul << CANFD_ECR_RP_Pos) /*!< CANFD_T::ECR: RP Mask */ + +#define CANFD_ECR_CEL_Pos (16) /*!< CANFD_T::ECR: CEL Position */ +#define CANFD_ECR_CEL_Msk (0xfful << CANFD_ECR_CEL_Pos) /*!< CANFD_T::ECR: CEL Mask */ + +#define CANFD_PSR_LEC_Pos (0) /*!< CANFD_T::PSR: LEC Position */ +#define CANFD_PSR_LEC_Msk (0x7ul << CANFD_PSR_LEC_Pos) /*!< CANFD_T::PSR: LEC Mask */ + +#define CANFD_PSR_ACT_Pos (3) /*!< CANFD_T::PSR: ACT Position */ +#define CANFD_PSR_ACT_Msk (0x3ul << CANFD_PSR_ACT_Pos) /*!< CANFD_T::PSR: ACT Mask */ + +#define CANFD_PSR_EP_Pos (5) /*!< CANFD_T::PSR: EP Position */ +#define CANFD_PSR_EP_Msk (0x1ul << CANFD_PSR_EP_Pos) /*!< CANFD_T::PSR: EP Mask */ + +#define CANFD_PSR_EW_Pos (6) /*!< CANFD_T::PSR: EW Position */ +#define CANFD_PSR_EW_Msk (0x1ul << CANFD_PSR_EW_Pos) /*!< CANFD_T::PSR: EW Mask */ + +#define CANFD_PSR_BO_Pos (7) /*!< CANFD_T::PSR: BO Position */ +#define CANFD_PSR_BO_Msk (0x1ul << CANFD_PSR_BO_Pos) /*!< CANFD_T::PSR: BO Mask */ + +#define CANFD_PSR_DLEC_Pos (8) /*!< CANFD_T::PSR: DLEC Position */ +#define CANFD_PSR_DLEC_Msk (0x7ul << CANFD_PSR_DLEC_Pos) /*!< CANFD_T::PSR: DLEC Mask */ + +#define CANFD_PSR_RESI_Pos (11) /*!< CANFD_T::PSR: RESI Position */ +#define CANFD_PSR_RESI_Msk (0x1ul << CANFD_PSR_RESI_Pos) /*!< CANFD_T::PSR: RESI Mask */ + +#define CANFD_PSR_RBRS_Pos (12) /*!< CANFD_T::PSR: RBRS Position */ +#define CANFD_PSR_RBRS_Msk (0x1ul << CANFD_PSR_RBRS_Pos) /*!< CANFD_T::PSR: RBRS Mask */ + +#define CANFD_PSR_RFDF_Pos (13) /*!< CANFD_T::PSR: RFDF Position */ +#define CANFD_PSR_RFDF_Msk (0x1ul << CANFD_PSR_RFDF_Pos) /*!< CANFD_T::PSR: RFDF Mask */ + +#define CANFD_PSR_PXE_Pos (14) /*!< CANFD_T::PSR: PXE Position */ +#define CANFD_PSR_PXE_Msk (0x1ul << CANFD_PSR_PXE_Pos) /*!< CANFD_T::PSR: PXE Mask */ + +#define CANFD_PSR_TDCV_Pos (16) /*!< CANFD_T::PSR: TDCV Position */ +#define CANFD_PSR_TDCV_Msk (0x7ful << CANFD_PSR_TDCV_Pos) /*!< CANFD_T::PSR: TDCV Mask */ + +#define CANFD_TDCR_TDCF_Pos (0) /*!< CANFD_T::TDCR: TDCF Position */ +#define CANFD_TDCR_TDCF_Msk (0x7ful << CANFD_TDCR_TDCF_Pos) /*!< CANFD_T::TDCR: TDCF Mask */ + +#define CANFD_TDCR_TDCO_Pos (8) /*!< CANFD_T::TDCR: TDCO Position */ +#define CANFD_TDCR_TDCO_Msk (0x7ful << CANFD_TDCR_TDCO_Pos) /*!< CANFD_T::TDCR: TDCO Mask */ + +#define CANFD_IR_RF0N_Pos (0) /*!< CANFD_T::IR: RF0N Position */ +#define CANFD_IR_RF0N_Msk (0x1ul << CANFD_IR_RF0N_Pos) /*!< CANFD_T::IR: RF0N Mask */ + +#define CANFD_IR_RF0W_Pos (1) /*!< CANFD_T::IR: RF0W Position */ +#define CANFD_IR_RF0W_Msk (0x1ul << CANFD_IR_RF0W_Pos) /*!< CANFD_T::IR: RF0W Mask */ + +#define CANFD_IR_RF0F_Pos (2) /*!< CANFD_T::IR: RF0F Position */ +#define CANFD_IR_RF0F_Msk (0x1ul << CANFD_IR_RF0F_Pos) /*!< CANFD_T::IR: RF0F Mask */ + +#define CANFD_IR_RF0L_Pos (3) /*!< CANFD_T::IR: RF0L Position */ +#define CANFD_IR_RF0L_Msk (0x1ul << CANFD_IR_RF0L_Pos) /*!< CANFD_T::IR: RF0L Mask */ + +#define CANFD_IR_RF1N_Pos (4) /*!< CANFD_T::IR: RF1N Position */ +#define CANFD_IR_RF1N_Msk (0x1ul << CANFD_IR_RF1N_Pos) /*!< CANFD_T::IR: RF1N Mask */ + +#define CANFD_IR_RF1W_Pos (5) /*!< CANFD_T::IR: RF1W Position */ +#define CANFD_IR_RF1W_Msk (0x1ul << CANFD_IR_RF1W_Pos) /*!< CANFD_T::IR: RF1W Mask */ + +#define CANFD_IR_RF1F_Pos (6) /*!< CANFD_T::IR: RF1F Position */ +#define CANFD_IR_RF1F_Msk (0x1ul << CANFD_IR_RF1F_Pos) /*!< CANFD_T::IR: RF1F Mask */ + +#define CANFD_IR_RF1L_Pos (7) /*!< CANFD_T::IR: RF1L Position */ +#define CANFD_IR_RF1L_Msk (0x1ul << CANFD_IR_RF1L_Pos) /*!< CANFD_T::IR: RF1L Mask */ + +#define CANFD_IR_HPM_Pos (8) /*!< CANFD_T::IR: HPM Position */ +#define CANFD_IR_HPM_Msk (0x1ul << CANFD_IR_HPM_Pos) /*!< CANFD_T::IR: HPM Mask */ + +#define CANFD_IR_TC_Pos (9) /*!< CANFD_T::IR: TC Position */ +#define CANFD_IR_TC_Msk (0x1ul << CANFD_IR_TC_Pos) /*!< CANFD_T::IR: TC Mask */ + +#define CANFD_IR_TCF_Pos (10) /*!< CANFD_T::IR: TCF Position */ +#define CANFD_IR_TCF_Msk (0x1ul << CANFD_IR_TCF_Pos) /*!< CANFD_T::IR: TCF Mask */ + +#define CANFD_IR_TFE_Pos (11) /*!< CANFD_T::IR: TFE Position */ +#define CANFD_IR_TFE_Msk (0x1ul << CANFD_IR_TFE_Pos) /*!< CANFD_T::IR: TFE Mask */ + +#define CANFD_IR_TEFN_Pos (12) /*!< CANFD_T::IR: TEFN Position */ +#define CANFD_IR_TEFN_Msk (0x1ul << CANFD_IR_TEFN_Pos) /*!< CANFD_T::IR: TEFN Mask */ + +#define CANFD_IR_TEFW_Pos (13) /*!< CANFD_T::IR: TEFW Position */ +#define CANFD_IR_TEFW_Msk (0x1ul << CANFD_IR_TEFW_Pos) /*!< CANFD_T::IR: TEFW Mask */ + +#define CANFD_IR_TEFF_Pos (14) /*!< CANFD_T::IR: TEFF Position */ +#define CANFD_IR_TEFF_Msk (0x1ul << CANFD_IR_TEFF_Pos) /*!< CANFD_T::IR: TEFF Mask */ + +#define CANFD_IR_TEFL_Pos (15) /*!< CANFD_T::IR: TEFL Position */ +#define CANFD_IR_TEFL_Msk (0x1ul << CANFD_IR_TEFL_Pos) /*!< CANFD_T::IR: TEFL Mask */ + +#define CANFD_IR_TSW_Pos (16) /*!< CANFD_T::IR: TSW Position */ +#define CANFD_IR_TSW_Msk (0x1ul << CANFD_IR_TSW_Pos) /*!< CANFD_T::IR: TSW Mask */ + +#define CANFD_IR_MRAF_Pos (17) /*!< CANFD_T::IR: MRAF Position */ +#define CANFD_IR_MRAF_Msk (0x1ul << CANFD_IR_MRAF_Pos) /*!< CANFD_T::IR: MRAF Mask */ + +#define CANFD_IR_TOO_Pos (18) /*!< CANFD_T::IR: TOO Position */ +#define CANFD_IR_TOO_Msk (0x1ul << CANFD_IR_TOO_Pos) /*!< CANFD_T::IR: TOO Mask */ + +#define CANFD_IR_DRX_Pos (19) /*!< CANFD_T::IR: DRX Position */ +#define CANFD_IR_DRX_Msk (0x1ul << CANFD_IR_DRX_Pos) /*!< CANFD_T::IR: DRX Mask */ + +#define CANFD_IR_ELO_Pos (22) /*!< CANFD_T::IR: ELO Position */ +#define CANFD_IR_ELO_Msk (0x1ul << CANFD_IR_ELO_Pos) /*!< CANFD_T::IR: ELO Mask */ + +#define CANFD_IR_EP_Pos (23) /*!< CANFD_T::IR: EP Position */ +#define CANFD_IR_EP_Msk (0x1ul << CANFD_IR_EP_Pos) /*!< CANFD_T::IR: EP Mask */ + +#define CANFD_IR_EW_Pos (24) /*!< CANFD_T::IR: EW Position */ +#define CANFD_IR_EW_Msk (0x1ul << CANFD_IR_EW_Pos) /*!< CANFD_T::IR: EW Mask */ + +#define CANFD_IR_BO_Pos (25) /*!< CANFD_T::IR: BO Position */ +#define CANFD_IR_BO_Msk (0x1ul << CANFD_IR_BO_Pos) /*!< CANFD_T::IR: BO Mask */ + +#define CANFD_IR_WDI_Pos (26) /*!< CANFD_T::IR: WDI Position */ +#define CANFD_IR_WDI_Msk (0x1ul << CANFD_IR_WDI_Pos) /*!< CANFD_T::IR: WDI Mask */ + +#define CANFD_IR_PEA_Pos (27) /*!< CANFD_T::IR: PEA Position */ +#define CANFD_IR_PEA_Msk (0x1ul << CANFD_IR_PEA_Pos) /*!< CANFD_T::IR: PEA Mask */ + +#define CANFD_IR_PED_Pos (28) /*!< CANFD_T::IR: PED Position */ +#define CANFD_IR_PED_Msk (0x1ul << CANFD_IR_PED_Pos) /*!< CANFD_T::IR: PED Mask */ + +#define CANFD_IR_ARA_Pos (29) /*!< CANFD_T::IR: ARA Position */ +#define CANFD_IR_ARA_Msk (0x1ul << CANFD_IR_ARA_Pos) /*!< CANFD_T::IR: ARA Mask */ + +#define CANFD_IE_RF0NE_Pos (0) /*!< CANFD_T::IE: RF0NE Position */ +#define CANFD_IE_RF0NE_Msk (0x1ul << CANFD_IE_RF0NE_Pos) /*!< CANFD_T::IE: RF0NE Mask */ + +#define CANFD_IE_RF0WE_Pos (1) /*!< CANFD_T::IE: RF0WE Position */ +#define CANFD_IE_RF0WE_Msk (0x1ul << CANFD_IE_RF0WE_Pos) /*!< CANFD_T::IE: RF0WE Mask */ + +#define CANFD_IE_RF0FE_Pos (2) /*!< CANFD_T::IE: RF0FE Position */ +#define CANFD_IE_RF0FE_Msk (0x1ul << CANFD_IE_RF0FE_Pos) /*!< CANFD_T::IE: RF0FE Mask */ + +#define CANFD_IE_RF0LE_Pos (3) /*!< CANFD_T::IE: RF0LE Position */ +#define CANFD_IE_RF0LE_Msk (0x1ul << CANFD_IE_RF0LE_Pos) /*!< CANFD_T::IE: RF0LE Mask */ + +#define CANFD_IE_RF1NE_Pos (4) /*!< CANFD_T::IE: RF1NE Position */ +#define CANFD_IE_RF1NE_Msk (0x1ul << CANFD_IE_RF1NE_Pos) /*!< CANFD_T::IE: RF1NE Mask */ + +#define CANFD_IE_RF1WE_Pos (5) /*!< CANFD_T::IE: RF1WE Position */ +#define CANFD_IE_RF1WE_Msk (0x1ul << CANFD_IE_RF1WE_Pos) /*!< CANFD_T::IE: RF1WE Mask */ + +#define CANFD_IE_RF1FE_Pos (6) /*!< CANFD_T::IE: RF1FE Position */ +#define CANFD_IE_RF1FE_Msk (0x1ul << CANFD_IE_RF1FE_Pos) /*!< CANFD_T::IE: RF1FE Mask */ + +#define CANFD_IE_RF1LE_Pos (7) /*!< CANFD_T::IE: RF1LE Position */ +#define CANFD_IE_RF1LE_Msk (0x1ul << CANFD_IE_RF1LE_Pos) /*!< CANFD_T::IE: RF1LE Mask */ + +#define CANFD_IE_HPME_Pos (8) /*!< CANFD_T::IE: HPME Position */ +#define CANFD_IE_HPME_Msk (0x1ul << CANFD_IE_HPME_Pos) /*!< CANFD_T::IE: HPME Mask */ + +#define CANFD_IE_TCE_Pos (9) /*!< CANFD_T::IE: TCE Position */ +#define CANFD_IE_TCE_Msk (0x1ul << CANFD_IE_TCE_Pos) /*!< CANFD_T::IE: TCE Mask */ + +#define CANFD_IE_TCFE_Pos (10) /*!< CANFD_T::IE: TCFE Position */ +#define CANFD_IE_TCFE_Msk (0x1ul << CANFD_IE_TCFE_Pos) /*!< CANFD_T::IE: TCFE Mask */ + +#define CANFD_IE_TFEE_Pos (11) /*!< CANFD_T::IE: TFEE Position */ +#define CANFD_IE_TFEE_Msk (0x1ul << CANFD_IE_TFEE_Pos) /*!< CANFD_T::IE: TFEE Mask */ + +#define CANFD_IE_TEFNE_Pos (12) /*!< CANFD_T::IE: TEFNE Position */ +#define CANFD_IE_TEFNE_Msk (0x1ul << CANFD_IE_TEFNE_Pos) /*!< CANFD_T::IE: TEFNE Mask */ + +#define CANFD_IE_TEFWE_Pos (13) /*!< CANFD_T::IE: TEFWE Position */ +#define CANFD_IE_TEFWE_Msk (0x1ul << CANFD_IE_TEFWE_Pos) /*!< CANFD_T::IE: TEFWE Mask */ + +#define CANFD_IE_TEFFE_Pos (14) /*!< CANFD_T::IE: TEFFE Position */ +#define CANFD_IE_TEFFE_Msk (0x1ul << CANFD_IE_TEFFE_Pos) /*!< CANFD_T::IE: TEFFE Mask */ + +#define CANFD_IE_TEFLE_Pos (15) /*!< CANFD_T::IE: TEFLE Position */ +#define CANFD_IE_TEFLE_Msk (0x1ul << CANFD_IE_TEFLE_Pos) /*!< CANFD_T::IE: TEFLE Mask */ + +#define CANFD_IE_TSWE_Pos (16) /*!< CANFD_T::IE: TSWE Position */ +#define CANFD_IE_TSWE_Msk (0x1ul << CANFD_IE_TSWE_Pos) /*!< CANFD_T::IE: TSWE Mask */ + +#define CANFD_IE_MRAFE_Pos (17) /*!< CANFD_T::IE: MRAFE Position */ +#define CANFD_IE_MRAFE_Msk (0x1ul << CANFD_IE_MRAFE_Pos) /*!< CANFD_T::IE: MRAFE Mask */ + +#define CANFD_IE_TOOE_Pos (18) /*!< CANFD_T::IE: TOOE Position */ +#define CANFD_IE_TOOE_Msk (0x1ul << CANFD_IE_TOOE_Pos) /*!< CANFD_T::IE: TOOE Mask */ + +#define CANFD_IE_DRXE_Pos (19) /*!< CANFD_T::IE: DRXE Position */ +#define CANFD_IE_DRXE_Msk (0x1ul << CANFD_IE_DRXE_Pos) /*!< CANFD_T::IE: DRXE Mask */ + +#define CANFD_IE_BECE_Pos (20) /*!< CANFD_T::IE: BECE Position */ +#define CANFD_IE_BECE_Msk (0x1ul << CANFD_IE_BECE_Pos) /*!< CANFD_T::IE: BECE Mask */ + +#define CANFD_IE_BEUE_Pos (21) /*!< CANFD_T::IE: BEUE Position */ +#define CANFD_IE_BEUE_Msk (0x1ul << CANFD_IE_BEUE_Pos) /*!< CANFD_T::IE: BEUE Mask */ + +#define CANFD_IE_ELOE_Pos (22) /*!< CANFD_T::IE: ELOE Position */ +#define CANFD_IE_ELOE_Msk (0x1ul << CANFD_IE_ELOE_Pos) /*!< CANFD_T::IE: ELOE Mask */ + +#define CANFD_IE_EPE_Pos (23) /*!< CANFD_T::IE: EPE Position */ +#define CANFD_IE_EPE_Msk (0x1ul << CANFD_IE_EPE_Pos) /*!< CANFD_T::IE: EPE Mask */ + +#define CANFD_IE_EWE_Pos (24) /*!< CANFD_T::IE: EWE Position */ +#define CANFD_IE_EWE_Msk (0x1ul << CANFD_IE_EWE_Pos) /*!< CANFD_T::IE: EWE Mask */ + +#define CANFD_IE_BOE_Pos (25) /*!< CANFD_T::IE: BOE Position */ +#define CANFD_IE_BOE_Msk (0x1ul << CANFD_IE_BOE_Pos) /*!< CANFD_T::IE: BOE Mask */ + +#define CANFD_IE_WDIE_Pos (26) /*!< CANFD_T::IE: WDIE Position */ +#define CANFD_IE_WDIE_Msk (0x1ul << CANFD_IE_WDIE_Pos) /*!< CANFD_T::IE: WDIE Mask */ + +#define CANFD_IE_PEAE_Pos (27) /*!< CANFD_T::IE: PEAE Position */ +#define CANFD_IE_PEAE_Msk (0x1ul << CANFD_IE_PEAE_Pos) /*!< CANFD_T::IE: PEAE Mask */ + +#define CANFD_IE_PEDE_Pos (28) /*!< CANFD_T::IE: PEDE Position */ +#define CANFD_IE_PEDE_Msk (0x1ul << CANFD_IE_PEDE_Pos) /*!< CANFD_T::IE: PEDE Mask */ + +#define CANFD_IE_ARAE_Pos (29) /*!< CANFD_T::IE: ARAE Position */ +#define CANFD_IE_ARAE_Msk (0x1ul << CANFD_IE_ARAE_Pos) /*!< CANFD_T::IE: ARAE Mask */ + +#define CANFD_ILS_RF0NL_Pos (0) /*!< CANFD_T::ILS: RF0NL Position */ +#define CANFD_ILS_RF0NL_Msk (0x1ul << CANFD_ILS_RF0NL_Pos) /*!< CANFD_T::ILS: RF0NL Mask */ + +#define CANFD_ILS_RF0WL_Pos (1) /*!< CANFD_T::ILS: RF0WL Position */ +#define CANFD_ILS_RF0WL_Msk (0x1ul << CANFD_ILS_RF0WL_Pos) /*!< CANFD_T::ILS: RF0WL Mask */ + +#define CANFD_ILS_RF0FL_Pos (2) /*!< CANFD_T::ILS: RF0FL Position */ +#define CANFD_ILS_RF0FL_Msk (0x1ul << CANFD_ILS_RF0FL_Pos) /*!< CANFD_T::ILS: RF0FL Mask */ + +#define CANFD_ILS_RF0LL_Pos (3) /*!< CANFD_T::ILS: RF0LL Position */ +#define CANFD_ILS_RF0LL_Msk (0x1ul << CANFD_ILS_RF0LL_Pos) /*!< CANFD_T::ILS: RF0LL Mask */ + +#define CANFD_ILS_RF1NL_Pos (4) /*!< CANFD_T::ILS: RF1NL Position */ +#define CANFD_ILS_RF1NL_Msk (0x1ul << CANFD_ILS_RF1NL_Pos) /*!< CANFD_T::ILS: RF1NL Mask */ + +#define CANFD_ILS_RF1WL_Pos (5) /*!< CANFD_T::ILS: RF1WL Position */ +#define CANFD_ILS_RF1WL_Msk (0x1ul << CANFD_ILS_RF1WL_Pos) /*!< CANFD_T::ILS: RF1WL Mask */ + +#define CANFD_ILS_RF1FL_Pos (6) /*!< CANFD_T::ILS: RF1FL Position */ +#define CANFD_ILS_RF1FL_Msk (0x1ul << CANFD_ILS_RF1FL_Pos) /*!< CANFD_T::ILS: RF1FL Mask */ + +#define CANFD_ILS_RF1LL_Pos (7) /*!< CANFD_T::ILS: RF1LL Position */ +#define CANFD_ILS_RF1LL_Msk (0x1ul << CANFD_ILS_RF1LL_Pos) /*!< CANFD_T::ILS: RF1LL Mask */ + +#define CANFD_ILS_HPML_Pos (8) /*!< CANFD_T::ILS: HPML Position */ +#define CANFD_ILS_HPML_Msk (0x1ul << CANFD_ILS_HPML_Pos) /*!< CANFD_T::ILS: HPML Mask */ + +#define CANFD_ILS_TCL_Pos (9) /*!< CANFD_T::ILS: TCL Position */ +#define CANFD_ILS_TCL_Msk (0x1ul << CANFD_ILS_TCL_Pos) /*!< CANFD_T::ILS: TCL Mask */ + +#define CANFD_ILS_TCFL_Pos (10) /*!< CANFD_T::ILS: TCFL Position */ +#define CANFD_ILS_TCFL_Msk (0x1ul << CANFD_ILS_TCFL_Pos) /*!< CANFD_T::ILS: TCFL Mask */ + +#define CANFD_ILS_TFEL_Pos (11) /*!< CANFD_T::ILS: TFEL Position */ +#define CANFD_ILS_TFEL_Msk (0x1ul << CANFD_ILS_TFEL_Pos) /*!< CANFD_T::ILS: TFEL Mask */ + +#define CANFD_ILS_TEFNL_Pos (12) /*!< CANFD_T::ILS: TEFNL Position */ +#define CANFD_ILS_TEFNL_Msk (0x1ul << CANFD_ILS_TEFNL_Pos) /*!< CANFD_T::ILS: TEFNL Mask */ + +#define CANFD_ILS_TEFWL_Pos (13) /*!< CANFD_T::ILS: TEFWL Position */ +#define CANFD_ILS_TEFWL_Msk (0x1ul << CANFD_ILS_TEFWL_Pos) /*!< CANFD_T::ILS: TEFWL Mask */ + +#define CANFD_ILS_TEFFL_Pos (14) /*!< CANFD_T::ILS: TEFFL Position */ +#define CANFD_ILS_TEFFL_Msk (0x1ul << CANFD_ILS_TEFFL_Pos) /*!< CANFD_T::ILS: TEFFL Mask */ + +#define CANFD_ILS_TEFLL_Pos (15) /*!< CANFD_T::ILS: TEFLL Position */ +#define CANFD_ILS_TEFLL_Msk (0x1ul << CANFD_ILS_TEFLL_Pos) /*!< CANFD_T::ILS: TEFLL Mask */ + +#define CANFD_ILS_TSWL_Pos (16) /*!< CANFD_T::ILS: TSWL Position */ +#define CANFD_ILS_TSWL_Msk (0x1ul << CANFD_ILS_TSWL_Pos) /*!< CANFD_T::ILS: TSWL Mask */ + +#define CANFD_ILS_MRAFL_Pos (17) /*!< CANFD_T::ILS: MRAFL Position */ +#define CANFD_ILS_MRAFL_Msk (0x1ul << CANFD_ILS_MRAFL_Pos) /*!< CANFD_T::ILS: MRAFL Mask */ + +#define CANFD_ILS_TOOL_Pos (18) /*!< CANFD_T::ILS: TOOL Position */ +#define CANFD_ILS_TOOL_Msk (0x1ul << CANFD_ILS_TOOL_Pos) /*!< CANFD_T::ILS: TOOL Mask */ + +#define CANFD_ILS_DRXL_Pos (19) /*!< CANFD_T::ILS: DRXL Position */ +#define CANFD_ILS_DRXL_Msk (0x1ul << CANFD_ILS_DRXL_Pos) /*!< CANFD_T::ILS: DRXL Mask */ + +#define CANFD_ILS_ELOL_Pos (22) /*!< CANFD_T::ILS: ELOL Position */ +#define CANFD_ILS_ELOL_Msk (0x1ul << CANFD_ILS_ELOL_Pos) /*!< CANFD_T::ILS: ELOL Mask */ + +#define CANFD_ILS_EPL_Pos (23) /*!< CANFD_T::ILS: EPL Position */ +#define CANFD_ILS_EPL_Msk (0x1ul << CANFD_ILS_EPL_Pos) /*!< CANFD_T::ILS: EPL Mask */ + +#define CANFD_ILS_EWL_Pos (24) /*!< CANFD_T::ILS: EWL Position */ +#define CANFD_ILS_EWL_Msk (0x1ul << CANFD_ILS_EWL_Pos) /*!< CANFD_T::ILS: EWL Mask */ + +#define CANFD_ILS_BOL_Pos (25) /*!< CANFD_T::ILS: BOL Position */ +#define CANFD_ILS_BOL_Msk (0x1ul << CANFD_ILS_BOL_Pos) /*!< CANFD_T::ILS: BOL Mask */ + +#define CANFD_ILS_WDIL_Pos (26) /*!< CANFD_T::ILS: WDIL Position */ +#define CANFD_ILS_WDIL_Msk (0x1ul << CANFD_ILS_WDIL_Pos) /*!< CANFD_T::ILS: WDIL Mask */ + +#define CANFD_ILS_PEAL_Pos (27) /*!< CANFD_T::ILS: PEAL Position */ +#define CANFD_ILS_PEAL_Msk (0x1ul << CANFD_ILS_PEAL_Pos) /*!< CANFD_T::ILS: PEAL Mask */ + +#define CANFD_ILS_PEDL_Pos (28) /*!< CANFD_T::ILS: PEDL Position */ +#define CANFD_ILS_PEDL_Msk (0x1ul << CANFD_ILS_PEDL_Pos) /*!< CANFD_T::ILS: PEDL Mask */ + +#define CANFD_ILS_ARAL_Pos (29) /*!< CANFD_T::ILS: ARAL Position */ +#define CANFD_ILS_ARAL_Msk (0x1ul << CANFD_ILS_ARAL_Pos) /*!< CANFD_T::ILS: ARAL Mask */ + +#define CANFD_ILE_ENT0_Pos (0) /*!< CANFD_T::ILE: ENT0 Position */ +#define CANFD_ILE_ENT0_Msk (0x1ul << CANFD_ILE_ENT0_Pos) /*!< CANFD_T::ILE: ENT0 Mask */ + +#define CANFD_ILE_ENT1_Pos (1) /*!< CANFD_T::ILE: ENT1 Position */ +#define CANFD_ILE_ENT1_Msk (0x1ul << CANFD_ILE_ENT1_Pos) /*!< CANFD_T::ILE: ENT1 Mask */ + +#define CANFD_GFC_RRFE_Pos (0) /*!< CANFD_T::GFC: RRFE Position */ +#define CANFD_GFC_RRFE_Msk (0x1ul << CANFD_GFC_RRFE_Pos) /*!< CANFD_T::GFC: RRFE Mask */ + +#define CANFD_GFC_RRFS_Pos (1) /*!< CANFD_T::GFC: RRFS Position */ +#define CANFD_GFC_RRFS_Msk (0x1ul << CANFD_GFC_RRFS_Pos) /*!< CANFD_T::GFC: RRFS Mask */ + +#define CANFD_GFC_ANFE_Pos (2) /*!< CANFD_T::GFC: ANFE Position */ +#define CANFD_GFC_ANFE_Msk (0x3ul << CANFD_GFC_ANFE_Pos) /*!< CANFD_T::GFC: ANFE Mask */ + +#define CANFD_GFC_ANFS_Pos (4) /*!< CANFD_T::GFC: ANFS Position */ +#define CANFD_GFC_ANFS_Msk (0x3ul << CANFD_GFC_ANFS_Pos) /*!< CANFD_T::GFC: ANFS Mask */ + +#define CANFD_SIDFC_FLSSA_Pos (2) /*!< CANFD_T::SIDFC: FLSSA Position */ +#define CANFD_SIDFC_FLSSA_Msk (0x3ffful << CANFD_SIDFC_FLSSA_Pos) /*!< CANFD_T::SIDFC: FLSSA Mask */ + +#define CANFD_SIDFC_LSS_Pos (16) /*!< CANFD_T::SIDFC: LSS Position */ +#define CANFD_SIDFC_LSS_Msk (0xfful << CANFD_SIDFC_LSS_Pos) /*!< CANFD_T::SIDFC: LSS Mask */ + +#define CANFD_XIDFC_FLESA_Pos (2) /*!< CANFD_T::XIDFC: FLESA Position */ +#define CANFD_XIDFC_FLESA_Msk (0x3ffful << CANFD_XIDFC_FLESA_Pos) /*!< CANFD_T::XIDFC: FLESA Mask */ + +#define CANFD_XIDFC_LSE_Pos (16) /*!< CANFD_T::XIDFC: LSE Position */ +#define CANFD_XIDFC_LSE_Msk (0x7ful << CANFD_XIDFC_LSE_Pos) /*!< CANFD_T::XIDFC: LSE Mask */ + +#define CANFD_XIDAM_EIDM_Pos (0) /*!< CANFD_T::XIDAM: EIDM Position */ +#define CANFD_XIDAM_EIDM_Msk (0x1ffffffful << CANFD_XIDAM_EIDM_Pos) /*!< CANFD_T::XIDAM: EIDM Mask */ + +#define CANFD_HPMS_BIDX_Pos (0) /*!< CANFD_T::HPMS: BIDX Position */ +#define CANFD_HPMS_BIDX_Msk (0x3ful << CANFD_HPMS_BIDX_Pos) /*!< CANFD_T::HPMS: BIDX Mask */ + +#define CANFD_HPMS_MSI_Pos (6) /*!< CANFD_T::HPMS: MSI Position */ +#define CANFD_HPMS_MSI_Msk (0x3ul << CANFD_HPMS_MSI_Pos) /*!< CANFD_T::HPMS: MSI Mask */ + +#define CANFD_HPMS_FIDX_Pos (8) /*!< CANFD_T::HPMS: FIDX Position */ +#define CANFD_HPMS_FIDX_Msk (0x7ful << CANFD_HPMS_FIDX_Pos) /*!< CANFD_T::HPMS: FIDX Mask */ + +#define CANFD_HPMS_FLST_Pos (15) /*!< CANFD_T::HPMS: FLST Position */ +#define CANFD_HPMS_FLST_Msk (0x1ul << CANFD_HPMS_FLST_Pos) /*!< CANFD_T::HPMS: FLST Mask */ + +#define CANFD_NDAT1_NDn_Pos (0) /*!< CANFD_T::NDAT1: NDn Position */ +#define CANFD_NDAT1_NDn_Msk (0xfffffffful << CANFD_NDAT1_NDn_Pos) /*!< CANFD_T::NDAT1: NDn Mask */ + +#define CANFD_NDAT2_NDn_Pos (0) /*!< CANFD_T::NDAT2: NDn Position */ +#define CANFD_NDAT2_NDn_Msk (0xfffffffful << CANFD_NDAT2_NDn_Pos) /*!< CANFD_T::NDAT2: NDn Mask */ + +#define CANFD_RXF0C_F0SA_Pos (2) /*!< CANFD_T::RXF0C: F0SA Position */ +#define CANFD_RXF0C_F0SA_Msk (0x3ffful << CANFD_RXF0C_F0SA_Pos) /*!< CANFD_T::RXF0C: F0SA Mask */ + +#define CANFD_RXF0C_F0S_Pos (16) /*!< CANFD_T::RXF0C: F0S Position */ +#define CANFD_RXF0C_F0S_Msk (0x7ful << CANFD_RXF0C_F0S_Pos) /*!< CANFD_T::RXF0C: F0S Mask */ + +#define CANFD_RXF0C_F0WM_Pos (24) /*!< CANFD_T::RXF0C: F0WM Position */ +#define CANFD_RXF0C_F0WM_Msk (0x7ful << CANFD_RXF0C_F0WM_Pos) /*!< CANFD_T::RXF0C: F0WM Mask */ + +#define CANFD_RXF0C_F0OM_Pos (31) /*!< CANFD_T::RXF0C: F0OM Position */ +#define CANFD_RXF0C_F0OM_Msk (0x1ul << CANFD_RXF0C_F0OM_Pos) /*!< CANFD_T::RXF0C: F0OM Mask */ + +#define CANFD_RXF0S_F0FL_Pos (0) /*!< CANFD_T::RXF0S: F0FL Position */ +#define CANFD_RXF0S_F0FL_Msk (0x7ful << CANFD_RXF0S_F0FL_Pos) /*!< CANFD_T::RXF0S: F0FL Mask */ + +#define CANFD_RXF0S_F0GI_Pos (8) /*!< CANFD_T::RXF0S: F0GI Position */ +#define CANFD_RXF0S_F0GI_Msk (0x3ful << CANFD_RXF0S_F0GI_Pos) /*!< CANFD_T::RXF0S: F0GI Mask */ + +#define CANFD_RXF0S_F0PI_Pos (16) /*!< CANFD_T::RXF0S: F0PI Position */ +#define CANFD_RXF0S_F0PI_Msk (0x3ful << CANFD_RXF0S_F0PI_Pos) /*!< CANFD_T::RXF0S: F0PI Mask */ + +#define CANFD_RXF0S_F0F_Pos (24) /*!< CANFD_T::RXF0S: F0F Position */ +#define CANFD_RXF0S_F0F_Msk (0x1ul << CANFD_RXF0S_F0F_Pos) /*!< CANFD_T::RXF0S: F0F Mask */ + +#define CANFD_RXF0S_RF0L_Pos (25) /*!< CANFD_T::RXF0S: RF0L Position */ +#define CANFD_RXF0S_RF0L_Msk (0x1ul << CANFD_RXF0S_RF0L_Pos) /*!< CANFD_T::RXF0S: RF0L Mask */ + +#define CANFD_RXF0A_F0A_Pos (0) /*!< CANFD_T::RXF0A: F0A Position */ +#define CANFD_RXF0A_F0A_Msk (0x3ful << CANFD_RXF0A_F0A_Pos) /*!< CANFD_T::RXF0A: F0A Mask */ + +#define CANFD_RXBC_RBSA_Pos (2) /*!< CANFD_T::RXBC: RBSA Position */ +#define CANFD_RXBC_RBSA_Msk (0x3ffful << CANFD_RXBC_RBSA_Pos) /*!< CANFD_T::RXBC: RBSA Mask */ + +#define CANFD_RXF1C_F1SA_Pos (2) /*!< CANFD_T::RXF1C: F1SA Position */ +#define CANFD_RXF1C_F1SA_Msk (0x3ffful << CANFD_RXF1C_F1SA_Pos) /*!< CANFD_T::RXF1C: F1SA Mask */ + +#define CANFD_RXF1C_F1S_Pos (16) /*!< CANFD_T::RXF1C: F1S Position */ +#define CANFD_RXF1C_F1S_Msk (0x7ful << CANFD_RXF1C_F1S_Pos) /*!< CANFD_T::RXF1C: F1S Mask */ + +#define CANFD_RXF1C_F1WM_Pos (24) /*!< CANFD_T::RXF1C: F1WM Position */ +#define CANFD_RXF1C_F1WM_Msk (0x7ful << CANFD_RXF1C_F1WM_Pos) /*!< CANFD_T::RXF1C: F1WM Mask */ + +#define CANFD_RXF1C_F1OM_Pos (31) /*!< CANFD_T::RXF1C: F1OM Position */ +#define CANFD_RXF1C_F1OM_Msk (0x1ul << CANFD_RXF1C_F1OM_Pos) /*!< CANFD_T::RXF1C: F1OM Mask */ + +#define CANFD_RXF1S_F1FL_Pos (0) /*!< CANFD_T::RXF1S: F1FL Position */ +#define CANFD_RXF1S_F1FL_Msk (0x7ful << CANFD_RXF1S_F1FL_Pos) /*!< CANFD_T::RXF1S: F1FL Mask */ + +#define CANFD_RXF1S_F1G_Pos (8) /*!< CANFD_T::RXF1S: F1G Position */ +#define CANFD_RXF1S_F1G_Msk (0x3ful << CANFD_RXF1S_F1G_Pos) /*!< CANFD_T::RXF1S: F1G Mask */ + +#define CANFD_RXF1S_F1P_Pos (16) /*!< CANFD_T::RXF1S: F1P Position */ +#define CANFD_RXF1S_F1P_Msk (0x3ful << CANFD_RXF1S_F1P_Pos) /*!< CANFD_T::RXF1S: F1P Mask */ + +#define CANFD_RXF1S_F1F_Pos (24) /*!< CANFD_T::RXF1S: F1F Position */ +#define CANFD_RXF1S_F1F_Msk (0x1ul << CANFD_RXF1S_F1F_Pos) /*!< CANFD_T::RXF1S: F1F Mask */ + +#define CANFD_RXF1S_RF1L_Pos (25) /*!< CANFD_T::RXF1S: RF1L Position */ +#define CANFD_RXF1S_RF1L_Msk (0x1ul << CANFD_RXF1S_RF1L_Pos) /*!< CANFD_T::RXF1S: RF1L Mask */ + +#define CANFD_RXF1S_DMS_Pos (30) /*!< CANFD_T::RXF1S: DMS Position */ +#define CANFD_RXF1S_DMS_Msk (0x3ul << CANFD_RXF1S_DMS_Pos) /*!< CANFD_T::RXF1S: DMS Mask */ + +#define CANFD_RXF1A_F1A_Pos (0) /*!< CANFD_T::RXF1A: F1A Position */ +#define CANFD_RXF1A_F1A_Msk (0x3ful << CANFD_RXF1A_F1A_Pos) /*!< CANFD_T::RXF1A: F1A Mask */ + +#define CANFD_RXESC_F0DS_Pos (0) /*!< CANFD_T::RXESC: F0DS Position */ +#define CANFD_RXESC_F0DS_Msk (0x7ul << CANFD_RXESC_F0DS_Pos) /*!< CANFD_T::RXESC: F0DS Mask */ + +#define CANFD_RXESC_F1DS_Pos (4) /*!< CANFD_T::RXESC: F1DS Position */ +#define CANFD_RXESC_F1DS_Msk (0x7ul << CANFD_RXESC_F1DS_Pos) /*!< CANFD_T::RXESC: F1DS Mask */ + +#define CANFD_RXESC_RBDS_Pos (8) /*!< CANFD_T::RXESC: RBDS Position */ +#define CANFD_RXESC_RBDS_Msk (0x7ul << CANFD_RXESC_RBDS_Pos) /*!< CANFD_T::RXESC: RBDS Mask */ + +#define CANFD_TXBC_TBSA_Pos (2) /*!< CANFD_T::TXBC: TBSA Position */ +#define CANFD_TXBC_TBSA_Msk (0x3ffful << CANFD_TXBC_TBSA_Pos) /*!< CANFD_T::TXBC: TBSA Mask */ + +#define CANFD_TXBC_NDTB_Pos (16) /*!< CANFD_T::TXBC: NDTB Position */ +#define CANFD_TXBC_NDTB_Msk (0x3ful << CANFD_TXBC_NDTB_Pos) /*!< CANFD_T::TXBC: NDTB Mask */ + +#define CANFD_TXBC_TFQS_Pos (24) /*!< CANFD_T::TXBC: TFQS Position */ +#define CANFD_TXBC_TFQS_Msk (0x3ful << CANFD_TXBC_TFQS_Pos) /*!< CANFD_T::TXBC: TFQS Mask */ + +#define CANFD_TXBC_TFQM_Pos (30) /*!< CANFD_T::TXBC: TFQM Position */ +#define CANFD_TXBC_TFQM_Msk (0x1ul << CANFD_TXBC_TFQM_Pos) /*!< CANFD_T::TXBC: TFQM Mask */ + +#define CANFD_TXFQS_TFFL_Pos (0) /*!< CANFD_T::TXFQS: TFFL Position */ +#define CANFD_TXFQS_TFFL_Msk (0x3ful << CANFD_TXFQS_TFFL_Pos) /*!< CANFD_T::TXFQS: TFFL Mask */ + +#define CANFD_TXFQS_TFG_Pos (8) /*!< CANFD_T::TXFQS: TFG Position */ +#define CANFD_TXFQS_TFG_Msk (0x1ful << CANFD_TXFQS_TFG_Pos) /*!< CANFD_T::TXFQS: TFG Mask */ + +#define CANFD_TXFQS_TFQP_Pos (16) /*!< CANFD_T::TXFQS: TFQP Position */ +#define CANFD_TXFQS_TFQP_Msk (0x1ful << CANFD_TXFQS_TFQP_Pos) /*!< CANFD_T::TXFQS: TFQP Mask */ + +#define CANFD_TXFQS_TFQF_Pos (21) /*!< CANFD_T::TXFQS: TFQF Position */ +#define CANFD_TXFQS_TFQF_Msk (0x1ul << CANFD_TXFQS_TFQF_Pos) /*!< CANFD_T::TXFQS: TFQF Mask */ + +#define CANFD_TXESC_TBDS_Pos (0) /*!< CANFD_T::TXESC: TBDS Position */ +#define CANFD_TXESC_TBDS_Msk (0x7ul << CANFD_TXESC_TBDS_Pos) /*!< CANFD_T::TXESC: TBDS Mask */ + +#define CANFD_TXBRP_TRPn_Pos (0) /*!< CANFD_T::TXBRP: TRPn Position */ +#define CANFD_TXBRP_TRPn_Msk (0xfffffffful << CANFD_TXBRP_TRPn_Pos) /*!< CANFD_T::TXBRP: TRPn Mask */ + +#define CANFD_TXBAR_ARn_Pos (0) /*!< CANFD_T::TXBAR: ARn Position */ +#define CANFD_TXBAR_ARn_Msk (0xfffffffful << CANFD_TXBAR_ARn_Pos) /*!< CANFD_T::TXBAR: ARn Mask */ + +#define CANFD_TXBCR_CRn_Pos (0) /*!< CANFD_T::TXBCR: CRn Position */ +#define CANFD_TXBCR_CRn_Msk (0xfffffffful << CANFD_TXBCR_CRn_Pos) /*!< CANFD_T::TXBCR: CRn Mask */ + +#define CANFD_TXBTO_TOn_Pos (0) /*!< CANFD_T::TXBTO: TOn Position */ +#define CANFD_TXBTO_TOn_Msk (0xfffffffful << CANFD_TXBTO_TOn_Pos) /*!< CANFD_T::TXBTO: TOn Mask */ + +#define CANFD_TXBCF_CFn_Pos (0) /*!< CANFD_T::TXBCF: CFn Position */ +#define CANFD_TXBCF_CFn_Msk (0xfffffffful << CANFD_TXBCF_CFn_Pos) /*!< CANFD_T::TXBCF: CFn Mask */ + +#define CANFD_TXBTIE_TIEn_Pos (0) /*!< CANFD_T::TXBTIE: TIEn Position */ +#define CANFD_TXBTIE_TIEn_Msk (0xfffffffful << CANFD_TXBTIE_TIEn_Pos) /*!< CANFD_T::TXBTIE: TIEn Mask */ + +#define CANFD_TXBCIE_CFIEn_Pos (0) /*!< CANFD_T::TXBCIE: CFIEn Position */ +#define CANFD_TXBCIE_CFIEn_Msk (0xfffffffful << CANFD_TXBCIE_CFIEn_Pos) /*!< CANFD_T::TXBCIE: CFIEn Mask */ + +#define CANFD_TXEFC_EFSA_Pos (2) /*!< CANFD_T::TXEFC: EFSA Position */ +#define CANFD_TXEFC_EFSA_Msk (0x3ffful << CANFD_TXEFC_EFSA_Pos) /*!< CANFD_T::TXEFC: EFSA Mask */ + +#define CANFD_TXEFC_EFS_Pos (16) /*!< CANFD_T::TXEFC: EFS Position */ +#define CANFD_TXEFC_EFS_Msk (0x3ful << CANFD_TXEFC_EFS_Pos) /*!< CANFD_T::TXEFC: EFS Mask */ + +#define CANFD_TXEFC_EFWN_Pos (24) /*!< CANFD_T::TXEFC: EFWN Position */ +#define CANFD_TXEFC_EFWN_Msk (0x3ful << CANFD_TXEFC_EFWN_Pos) /*!< CANFD_T::TXEFC: EFWN Mask */ + +#define CANFD_TXEFS_EFFL_Pos (0) /*!< CANFD_T::TXEFS: EFFL Position */ +#define CANFD_TXEFS_EFFL_Msk (0x3ful << CANFD_TXEFS_EFFL_Pos) /*!< CANFD_T::TXEFS: EFFL Mask */ + +#define CANFD_TXEFS_EFG_Pos (8) /*!< CANFD_T::TXEFS: EFG Position */ +#define CANFD_TXEFS_EFG_Msk (0x1ful << CANFD_TXEFS_EFG_Pos) /*!< CANFD_T::TXEFS: EFG Mask */ + +#define CANFD_TXEFS_EFP_Pos (16) /*!< CANFD_T::TXEFS: EFP Position */ +#define CANFD_TXEFS_EFP_Msk (0x1ful << CANFD_TXEFS_EFP_Pos) /*!< CANFD_T::TXEFS: EFP Mask */ + +#define CANFD_TXEFS_EFF_Pos (24) /*!< CANFD_T::TXEFS: EFF Position */ +#define CANFD_TXEFS_EFF_Msk (0x1ul << CANFD_TXEFS_EFF_Pos) /*!< CANFD_T::TXEFS: EFF Mask */ + +#define CANFD_TXEFS_TEFL_Pos (25) /*!< CANFD_T::TXEFS: TEFL Position */ +#define CANFD_TXEFS_TEFL_Msk (0x1ul << CANFD_TXEFS_TEFL_Pos) /*!< CANFD_T::TXEFS: TEFL Mask */ + +#define CANFD_TXEFA_EFA_Pos (0) /*!< CANFD_T::TXEFA: EFA Position */ +#define CANFD_TXEFA_EFA_Msk (0x1ful << CANFD_TXEFA_EFA_Pos) /*!< CANFD_T::TXEFA: EFA Mask */ + +/**@}*/ /* CANFD_CONST */ +/**@}*/ /* end of CANFD register group */ +/**@}*/ /* end of REGISTER group */ + +#if defined ( __CC_ARM ) + #pragma no_anon_unions +#endif + +#endif /* __CANFD_REG_H__ */ diff --git a/bsp/nuvoton/libraries/ma35/Device/Nuvoton/MA35D1/Include/ccap_reg.h b/bsp/nuvoton/libraries/ma35/Device/Nuvoton/MA35D1/Include/ccap_reg.h new file mode 100644 index 0000000000..fc81bad940 --- /dev/null +++ b/bsp/nuvoton/libraries/ma35/Device/Nuvoton/MA35D1/Include/ccap_reg.h @@ -0,0 +1,453 @@ +/**************************************************************************//** + * @file ccap_reg.h + * @version V3.00 + * @brief CCAP register definition header file + * + * @copyright SPDX-License-Identifier: Apache-2.0 + * @copyright (C) 2021 Nuvoton Technology Corp. All rights reserved. + *****************************************************************************/ +#ifndef __CCAP_REG_H__ +#define __CCAP_REG_H__ + +#if defined ( __CC_ARM ) + #pragma anon_unions +#endif + +/** + @addtogroup REGISTER Control Register + @{ +*/ + +/** + @addtogroup CCAP Camera Capture Interface Controller (CCAP) + Memory Mapped Structure for CCAP Controller +@{ */ + + +typedef struct +{ + + + /** + * @var CCAP_T::CTL + * Offset: 0x00 Camera Capture Interface Control Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[0] |CCAPEN |Camera Capture Interface Enable Bit + * | | |0 = Camera Capture Interface Disabled. + * | | |1 = Camera Capture Interface Enabled. + * |[6] |PKTEN |Packet Output Enable Bit + * | | |0 = Packet output Disabled. + * | | |1 = Packet output Enabled. + * |[7] |MONO |Monochrome CMOS Sensor Select + * | | |0 = Color CMOS Sensor. + * | | |1 = Monochrome CMOS Sensor. The U/V components are ignored when the MONO is enabled. + * |[16] |SHUTTER |Camera Capture Interface Automatically Disable the Capture Interface After a Frame Had Been Captured + * | | |0 = Shutter Disabled. + * | | |1 = Shutter Enabled. + * |[17] |MY4_SWAP |Monochrome CMOS Sensor 4-bit Data Nibble Swap + * | | |0 = The 4-bit data input sequence: 1st Pixel is for 1st Nibble (1st pixel at MSB). + * | | |1 = The 4-bit data input sequence: 1st Pixel is for 2nd Nibble (1st pixel at LSB). + * |[18] |MY8_MY4 |Monochrome CMOS Sensor Data I/O Interface + * | | |0 = Monochrome CMOS sensor is by the 4-bit data I/O interface. + * | | |1 = Monochrome CMOS sensor is by the 8-bit data I/O interface. + * |[19] |Luma_Y_One|Color/Monochrome CMOS Sensor Luminance 8-bit Y to 1-bit Y Conversion + * | | |0 = Color/Monochrome CMOS sensor Luma-Y-One bit Disabled. + * | | |1 = Color/Monochrome CMOS sensor Luma-Y-One bit Enabled. + * | | |Note: Color CMOS sensor U/V components are ignored when the Luma_Y_One is enabled. + * |[20] |UPDATE |Update Register at New Frame + * | | |0 = Update register at new frame Disabled. + * | | |1 = Update register at new frame Enabled (Auto clear to 0 when register updated). + * |[24] |VPRST |Capture Interface Reset + * | | |0 = Capture interface reset Disabled. + * | | |1 = Capture interface reset Enabled. + * @var CCAP_T::PAR + * Offset: 0x04 Camera Capture Interface Parameter Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[0] |INFMT |Sensor Input Data Format + * | | |0 = YCbCr422. + * | | |1 = RGB565. + * |[1] |SENTYPE |Sensor Input Type + * | | |0 = CCIR601. + * | | |1 = CCIR656, VSync & Hsync embedded in the data signal. + * |[3:2] |INDATORD |Sensor Input Data Order + * | | |If INFMT (CCAP_PAR[0]) = 0 (YCbCr): + * | | |00 = Sensor input data (Byte 0 1 2 3) is Y0 U0 Y1 V0. + * | | |01 = Sensor input data (Byte 0 1 2 3) is Y0 V0 Y1 U0. + * | | |10 = Sensor input data (Byte 0 1 2 3) is U0 Y0 V0 Y1. + * | | |11 = Sensor input data (Byte 0 1 2 3) is V0 Y0 U0 Y1. + * | | |If INFMT (CCAP_PAR[0]) = 1 (RGB565): + * | | |00 = Sensor input data (Byte 0) is {R[4:0],G[5:3]}. Sensor input data (Byte 1) is {G[2:0], B[4:0]}. + * | | |01 = Sensor input data (Byte 0) is {B[4:0],G[5:3]}. Sensor input data (Byte 1) is {G[2:0], R[4:0]}. + * | | |10 = Sensor input data (Byte 0) is {G[2:0],B[4:0]}. Sensor input data (Byte 1) is {R[4:0], G[5:3]}. + * | | |11 = Sensor input data (Byte 0) is {G[2:0],R[4:0]}. Sensor input data (Byte 1) is {B[4:0], G[5:3]}. + * |[5:4] |OUTFMT |Image Data Format Output to System Memory + * | | |00 = YCbCr422. + * | | |01 = Only output Y. (Select this format when CCAP_CTL "Luma_Y_One" or "MONO" enabled). + * | | |10 = RGB555. + * | | |11 = RGB565. + * |[6] |RANGE |Scale Input YUV CCIR601 Color Range to Full Range + * | | |0 = Default. + * | | |1 = Scale to full range. + * |[8] |PCLKP |Sensor Pixel Clock Polarity + * | | |0 = Input video data and signals are latched by falling edge of Pixel Clock. + * | | |1 = Input video data and signals are latched by rising edge of Pixel Clock. + * |[9] |HSP |Sensor Hsync Polarity + * | | |0 = Sync Low. + * | | |1 = Sync High. + * |[10] |VSP |Sensor Vsync Polarity + * | | |0 = Sync Low. + * | | |1 = Sync High. + * |[18] |FBB |Field by Blank + * | | |Field by Blank (only in ccir-656 mode) means blanking pixel data(0x80108010) have to transfer to system memory or not. + * | | |0 = Field by blank Disabled. (blank pixel data will transfer to system memory). + * | | |1 = Field by blank Enabled. (only active data will transfer to system memory). + * @var CCAP_T::INT + * Offset: 0x08 Camera Capture Interface Interrupt Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[0] |VINTF |Video Frame End Interrupt + * | | |0 = Did not receive a frame completely. + * | | |1 = Received a frame completely. + * | | |Note: This bit is cleared by writing 1 to it. + * |[1] |MEINTF |Bus Master Transfer Error Interrupt + * | | |0 = Transfer Error did not occur. + * | | |1 = Transfer Error occurred. + * | | |Note: This bit is cleared by writing 1 to it. + * |[3] |ADDRMINTF |Memory Address Match Interrupt + * | | |0 = Memory Address Match Interrupt did not occur. + * | | |1 = Memory Address Match Interrupt occurred. + * | | |Note: This bit is cleared by writing 1 to it. + * |[16] |VIEN |Video Frame End Interrupt Enable Bit + * | | |0 = Video frame end interrupt Disabled. + * | | |1 = Video frame end interrupt Enabled. + * |[17] |MEIEN |Bus Master Transfer Error Interrupt Enable Bit + * | | |0 = Bus Master Transfer error interrupt Disabled. + * | | |1 = Bus Master Transfer error interrupt Enabled. + * |[19] |ADDRMIEN |Memory Address Match Interrupt Enable Bit + * | | |0 = Memory address match interrupt Disabled. + * | | |1 = Memory address match interrupt Enabled. + * @var CCAP_T::CWSP + * Offset: 0x20 Cropping Window Starting Address Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[11:0] |CWSADDRH |Cropping Window Horizontal Starting Address + * | | |Specify the value of the cropping window horizontal start address. + * |[26:16] |CWSADDRV |Cropping Window Vertical Starting Address + * | | |Specify the value of the cropping window vertical start address. + * @var CCAP_T::CWS + * Offset: 0x24 Cropping Window Size Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[11:0] |CWW |Cropping Window Width + * | | |Specify the size of the cropping window width. + * |[26:16] |CWH |Cropping Window Height + * | | |Specify the size of the cropping window height. + * @var CCAP_T::PKTSL + * Offset: 0x28 Packet Scaling Vertical/Horizontal Factor Register (LSB) + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[7:0] |PKTSHML |Packet Scaling Horizontal Factor M + * | | |Specifies the lower 8-bit of denominator part (M) of the horizontal scaling factor. + * | | |The lower 8-bit will be cascaded with higher 8-bit (PKDSHMH) to form a 16-bit denominator (M) of vertical factor. + * | | |The output image width will be equal to the image width * N/M. + * | | |Note: The value of N must be equal to or less than M. + * |[15:8] |PKTSHNL |Packet Scaling Horizontal Factor N + * | | |Specify the lower 8-bit of numerator part (N) of the horizontal scaling factor. + * | | |The lower 8-bit will be cascaded with higher 8-bit (PKDSHNH) to form a 16-bit numerator of horizontal factor. + * |[23:16] |PKTSVML |Packet Scaling Vertical Factor M + * | | |Specify the lower 8-bit of denominator part (M) of the vertical scaling factor. + * | | |The lower 8-bit will be cascaded with higher 8-bit (PKDSVMH) to form a 16-bit denominator (M) of vertical factor. + * | | |The output image width will be equal to the image height * N/M. + * | | |Note: The value of N must be equal to or less than M. + * |[31:24] |PKTSVNL |Packet Scaling Vertical Factor N + * | | |Specify the lower 8-bit of numerator part (N) of the vertical scaling factor. + * | | |The lower 8-bit will be cascaded with higher 8-bit (PKDSVNH) to form a 16-bit numerator of vertical factor. + * @var CCAP_T::FRCTL + * Offset: 0x30 Scaling Frame Rate Factor Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[5:0] |FRM |Scaling Frame Rate Factor M + * | | |Specify the denominator part (M) of the frame rate scaling factor. + * | | |The output image frame rate will be equal to input image frame rate * (N/M). + * | | |Note: The value of N must be equal to or less than M. + * |[13:8] |FRN |Scaling Frame Rate Factor N + * | | |Specify the numerator part (N) of the frame rate scaling factor. + * @var CCAP_T::STRIDE + * Offset: 0x34 Frame Output Pixel Stride Width Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[13:0] |PKTSTRIDE |Packet Frame Output Pixel Stride Width + * | | |The output pixel stride size of packet pipe. + * | | |It is a 32-pixel aligned stride width for the Luma-Y-One bit format or a 4-pixel aligned stride with for the Luma-Y-Eight bit format when color or monochrome CMOS sensors used. + * | | |This means that every new captured line is by word alignment address when color or monochrome CMOS sensors used. + * @var CCAP_T::FIFOTH + * Offset: 0x3C FIFO Threshold Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[28:24] |PKTFTH |Packet FIFO Threshold + * | | |Specify the 5-bit value of the packet FIFO threshold. + * |[31] |OVF |FIFO Overflow Flag + * | | |Indicate the FIFO overflow flag. + * @var CCAP_T::CMPADDR + * Offset: 0x40 Compare Memory Base Address Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[31:0] |CMPADDR |Compare Memory Base Address + * | | |It is a word alignment address, that is, the address is aligned by ignoring the 2 LSB bits [1:0]. + * @var CCAP_T::LUMA_Y1_THD + * Offset: 0x44 Luminance Y8 to Y1 Threshold Value Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :-----------: | :---- | + * |[7:0] |LUMA_Y1_THRESH |Luminance Y8 to Y1 Threshold Value + * | | |Specify the 8-bit threshold value for the luminance Y bit-8 to the luminance Y 1-bit conversion. + * @var CCAP_T::PKTSM + * Offset: 0x48 Packet Scaling Vertical/Horizontal Factor Register (MSB) + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[7:0] |PKTSHMH |Packet Scaling Horizontal Factor M + * | | |Specify the higher 8-bit of denominator part (M) of the horizontal scaling factor. + * | | |Please refer to the register CCAP_PKTSL for the detailed operation. + * |[15:8] |PKTSHNH |Packet Scaling Horizontal Factor N + * | | |Specify the higher 8-bit of numerator part (N) of the horizontal scaling factor. + * | | |Please refer to the register CCAP_PKTSL for the detailed operation. + * |[23:16] |PKTSVMH |Packet Scaling Vertical Factor M + * | | |Specify the higher 8-bit of denominator part (M) of the vertical scaling factor. + * | | |Please refer to the register CCAP_PKTSL to check the cooperation between these two registers. + * |[31:24] |PKTSVNH |Packet Scaling Vertical Factor N + * | | |Specify the higher 8-bit of numerator part (N) of the vertical scaling factor. + * | | |Please refer to the register CCAP_PKTSL to check the cooperation between these two registers. + * @var CCAP_T::CURADDRP + * Offset: 0x50 Current Packet System Memory Address Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[31:0] |CURADDR |Current Packet Output Memory Address + * | | |Specify the 32-bit value of the current packet output memory address. + * @var CCAP_T::PKTBA0 + * Offset: 0x60 System Memory Packet Base Address 0 Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[31:0] |BASEADDR |System Memory Packet Base Address 0 + * | | |It is a word alignment address, that is, the address is aligned by ignoring the 2 LSB bits [1:0]. + */ + __IO uint32_t CTL; /*!< [0x0000] Camera Capture Interface Control Register */ + __IO uint32_t PAR; /*!< [0x0004] Camera Capture Interface Parameter Register */ + __IO uint32_t INT; /*!< [0x0008] Camera Capture Interface Interrupt Register */ + __I uint32_t RESERVE0[5]; + __IO uint32_t CWSP; /*!< [0x0020] Cropping Window Starting Address Register */ + __IO uint32_t CWS; /*!< [0x0024] Cropping Window Size Register */ + __IO uint32_t PKTSL; /*!< [0x0028] Packet Scaling Vertical/Horizontal Factor Register (LSB) */ + __IO uint32_t PLNSL; /*!< [0x002C] Planar Scaling Vertical/Horizontal Factor Register (LSB) */ + __IO uint32_t FRCTL; /*!< [0x0030] Scaling Frame Rate Factor Register */ + __IO uint32_t STRIDE; /*!< [0x0034] Frame Output Pixel Stride Width Register */ + __I uint32_t RESERVE1[1]; + __IO uint32_t FIFOTH; /*!< [0x003C] FIFO Threshold Register */ + __IO uint32_t CMPADDR; /*!< [0x0040] Compare Memory Base Address Register */ + __IO uint32_t LUMA_Y1_THD; /*!< [0x0044] Luminance Y8 to Y1 Threshold Value Register */ + __IO uint32_t PKTSM; /*!< [0x0048] Packet Scaling Vertical/Horizontal Factor Register (MSB) */ + __IO uint32_t PLNSM; /*!< [0x004C] Planar Scaling Vertical/Horizontal Factor Register (MSB) */ + __I uint32_t CURADDRP; /*!< [0x0050] Current Packet System Memory Address Register */ + __I uint32_t CURADDRY; /*!< [0x0054] Current Planar Y System Memory Address Register */ + __I uint32_t CURADDRU; /*!< [0x0058] Current Planar U System Memory Address Register */ + __I uint32_t CURADDRV; /*!< [0x005C] Current Planar V System Memory Address Register */ + __IO uint32_t PKTBA0; /*!< [0x0060] System Memory Packet Base Address 0 Register */ + __I uint32_t RESERVE4[7]; + __IO uint32_t YBA; /*!< [0x0080] System Memory Planar Y Base Address Register */ + __IO uint32_t UBA; /*!< [0x0084] System Memory Planar U Base Address Register */ + __IO uint32_t VBA; /*!< [0x0088] System Memory Planar V Base Address Register */ +} CCAP_T; + +/** + @addtogroup CCAP_CONST CCAP Bit Field Definition + Constant Definitions for CCAP Controller +@{ */ + +#define CCAP_CTL_CCAPEN_Pos (0) /*!< CCAP_T::CTL: CCAPEN Position */ +#define CCAP_CTL_CCAPEN_Msk (0x1ul << CCAP_CTL_CCAPEN_Pos) /*!< CCAP_T::CTL: CCAPEN Mask */ + +#define CCAP_CTL_PLNEN_Pos (5) /*!< CCAP_T::CTL: PLNEN Position */ +#define CCAP_CTL_PLNEN_Msk (0x1ul << CCAP_CTL_PLNEN_Pos) /*!< CCAP_T::CTL: PLNEN Mask */ + +#define CCAP_CTL_PKTEN_Pos (6) /*!< CCAP_T::CTL: PKTEN Position */ +#define CCAP_CTL_PKTEN_Msk (0x1ul << CCAP_CTL_PKTEN_Pos) /*!< CCAP_T::CTL: PKTEN Mask */ + +#define CCAP_CTL_MONO_Pos (7) /*!< CCAP_T::CTL: MONO Position */ +#define CCAP_CTL_MONO_Msk (0x1ul << CCAP_CTL_MONO_Pos) /*!< CCAP_T::CTL: MONO Mask */ + +#define CCAP_CTL_SHUTTER_Pos (16) /*!< CCAP_T::CTL: SHUTTER Position */ +#define CCAP_CTL_SHUTTER_Msk (0x1ul << CCAP_CTL_SHUTTER_Pos) /*!< CCAP_T::CTL: SHUTTER Mask */ + +#define CCAP_CTL_MY4_SWAP_Pos (17) /*!< CCAP_T::CTL: MY4_SWAP Position */ +#define CCAP_CTL_MY4_SWAP_Msk (0x1ul << CCAP_CTL_MY4_SWAP_Pos) /*!< CCAP_T::CTL: MY4_SWAP Mask */ + +#define CCAP_CTL_MY8_MY4_Pos (18) /*!< CCAP_T::CTL: MY8_MY4 Position */ +#define CCAP_CTL_MY8_MY4_Msk (0x1ul << CCAP_CTL_MY8_MY4_Pos) /*!< CCAP_T::CTL: MY8_MY4 Mask */ + +#define CCAP_CTL_Luma_Y_One_Pos (19) /*!< CCAP_T::CTL: Luma_Y_One Position */ +#define CCAP_CTL_Luma_Y_One_Msk (0x1ul << CCAP_CTL_Luma_Y_One_Pos) /*!< CCAP_T::CTL: Luma_Y_One Mask */ + +#define CCAP_CTL_UPDATE_Pos (20) /*!< CCAP_T::CTL: UPDATE Position */ +#define CCAP_CTL_UPDATE_Msk (0x1ul << CCAP_CTL_UPDATE_Pos) /*!< CCAP_T::CTL: UPDATE Mask */ + +#define CCAP_CTL_VPRST_Pos (24) /*!< CCAP_T::CTL: VPRST Position */ +#define CCAP_CTL_VPRST_Msk (0x1ul << CCAP_CTL_VPRST_Pos) /*!< CCAP_T::CTL: VPRST Mask */ + +#define CCAP_PAR_INFMT_Pos (0) /*!< CCAP_T::PAR: INFMT Position */ +#define CCAP_PAR_INFMT_Msk (0x1ul << CCAP_PAR_INFMT_Pos) /*!< CCAP_T::PAR: INFMT Mask */ + +#define CCAP_PAR_SENTYPE_Pos (1) /*!< CCAP_T::PAR: SENTYPE Position */ +#define CCAP_PAR_SENTYPE_Msk (0x1ul << CCAP_PAR_SENTYPE_Pos) /*!< CCAP_T::PAR: SENTYPE Mask */ + +#define CCAP_PAR_INDATORD_Pos (2) /*!< CCAP_T::PAR: INDATORD Position */ +#define CCAP_PAR_INDATORD_Msk (0x3ul << CCAP_PAR_INDATORD_Pos) /*!< CCAP_T::PAR: INDATORD Mask */ + +#define CCAP_PAR_PLNFMT_Pos (7) /*!< CCAP_T::PAR: OUTFMT Position */ +#define CCAP_PAR_PLNFMT_Msk (0x1ul << CCAP_PAR_OUTFMT_Pos) /*!< CCAP_T::PAR: OUTFMT Mask */ + +#define CCAP_PAR_OUTFMT_Pos (4) /*!< CCAP_T::PAR: OUTFMT Position */ +#define CCAP_PAR_OUTFMT_Msk (0x3ul << CCAP_PAR_OUTFMT_Pos) /*!< CCAP_T::PAR: OUTFMT Mask */ + +#define CCAP_PAR_RANGE_Pos (6) /*!< CCAP_T::PAR: RANGE Position */ +#define CCAP_PAR_RANGE_Msk (0x1ul << CCAP_PAR_RANGE_Pos) /*!< CCAP_T::PAR: RANGE Mask */ + +#define CCAP_PAR_PCLKP_Pos (8) /*!< CCAP_T::PAR: PCLKP Position */ +#define CCAP_PAR_PCLKP_Msk (0x1ul << CCAP_PAR_PCLKP_Pos) /*!< CCAP_T::PAR: PCLKP Mask */ + +#define CCAP_PAR_HSP_Pos (9) /*!< CCAP_T::PAR: HSP Position */ +#define CCAP_PAR_HSP_Msk (0x1ul << CCAP_PAR_HSP_Pos) /*!< CCAP_T::PAR: HSP Mask */ + +#define CCAP_PAR_VSP_Pos (10) /*!< CCAP_T::PAR: VSP Position */ +#define CCAP_PAR_VSP_Msk (0x1ul << CCAP_PAR_VSP_Pos) /*!< CCAP_T::PAR: VSP Mask */ + +#define CCAP_PAR_FBB_Pos (18) /*!< CCAP_T::PAR: FBB Position */ +#define CCAP_PAR_FBB_Msk (0x1ul << CCAP_PAR_FBB_Pos) /*!< CCAP_T::PAR: FBB Mask */ + +#define CCAP_INT_VINTF_Pos (0) /*!< CCAP_T::INT: VINTF Position */ +#define CCAP_INT_VINTF_Msk (0x1ul << CCAP_INT_VINTF_Pos) /*!< CCAP_T::INT: VINTF Mask */ + +#define CCAP_INT_MEINTF_Pos (1) /*!< CCAP_T::INT: MEINTF Position */ +#define CCAP_INT_MEINTF_Msk (0x1ul << CCAP_INT_MEINTF_Pos) /*!< CCAP_T::INT: MEINTF Mask */ + +#define CCAP_INT_ADDRMINTF_Pos (3) /*!< CCAP_T::INT: ADDRMINTF Position */ +#define CCAP_INT_ADDRMINTF_Msk (0x1ul << CCAP_INT_ADDRMINTF_Pos) /*!< CCAP_T::INT: ADDRMINTF Mask */ + +#define CCAP_INT_VIEN_Pos (16) /*!< CCAP_T::INT: VIEN Position */ +#define CCAP_INT_VIEN_Msk (0x1ul << CCAP_INT_VIEN_Pos) /*!< CCAP_T::INT: VIEN Mask */ + +#define CCAP_INT_MEIEN_Pos (17) /*!< CCAP_T::INT: MEIEN Position */ +#define CCAP_INT_MEIEN_Msk (0x1ul << CCAP_INT_MEIEN_Pos) /*!< CCAP_T::INT: MEIEN Mask */ + +#define CCAP_INT_ADDRMIEN_Pos (19) /*!< CCAP_T::INT: ADDRMIEN Position */ +#define CCAP_INT_ADDRMIEN_Msk (0x1ul << CCAP_INT_ADDRMIEN_Pos) /*!< CCAP_T::INT: ADDRMIEN Mask */ + +#define CCAP_CWSP_CWSADDRH_Pos (0) /*!< CCAP_T::CWSP: CWSADDRH Position */ +#define CCAP_CWSP_CWSADDRH_Msk (0xffful << CCAP_CWSP_CWSADDRH_Pos) /*!< CCAP_T::CWSP: CWSADDRH Mask */ + +#define CCAP_CWSP_CWSADDRV_Pos (16) /*!< CCAP_T::CWSP: CWSADDRV Position */ +#define CCAP_CWSP_CWSADDRV_Msk (0x7fful << CCAP_CWSP_CWSADDRV_Pos) /*!< CCAP_T::CWSP: CWSADDRV Mask */ + +#define CCAP_CWS_CWW_Pos (0) /*!< CCAP_T::CWS: CWW Position */ +#define CCAP_CWS_CWW_Msk (0xffful << CCAP_CWS_CWW_Pos) /*!< CCAP_T::CWS: CWW Mask */ + +#define CCAP_CWS_CWH_Pos (16) /*!< CCAP_T::CWS: CIWH Position */ +#define CCAP_CWS_CWH_Msk (0x7fful << CCAP_CWS_CWH_Pos) /*!< CCAP_T::CWS: CIWH Mask */ + +#define CCAP_PKTSL_PKTSHML_Pos (0) /*!< CCAP_T::PKTSL: PKTSHML Position */ +#define CCAP_PKTSL_PKTSHML_Msk (0xfful << CCAP_PKTSL_PKTSHML_Pos) /*!< CCAP_T::PKTSL: PKTSHML Mask */ + +#define CCAP_PKTSL_PKTSHNL_Pos (8) /*!< CCAP_T::PKTSL: PKTSHNL Position */ +#define CCAP_PKTSL_PKTSHNL_Msk (0xfful << CCAP_PKTSL_PKTSHNL_Pos) /*!< CCAP_T::PKTSL: PKTSHNL Mask */ + +#define CCAP_PKTSL_PKTSVML_Pos (16) /*!< CCAP_T::PKTSL: PKTSVML Position */ +#define CCAP_PKTSL_PKTSVML_Msk (0xfful << CCAP_PKTSL_PKTSVML_Pos) /*!< CCAP_T::PKTSL: PKTSVML Mask */ + +#define CCAP_PKTSL_PKTSVNL_Pos (24) /*!< CCAP_T::PKTSL: PKTSVNL Position */ +#define CCAP_PKTSL_PKTSVNL_Msk (0xfful << CCAP_PKTSL_PKTSVNL_Pos) /*!< CCAP_T::PKTSL: PKTSVNL Mask */ + +#define CCAP_PLNSL_PLNSHML_Pos (0) /*!< CCAP_T::PLNSL: PLNSHML Position */ +#define CCAP_PLNSL_PLNSHML_Msk (0xfful << CCAP_PLNSL_PLNSHML_Pos) /*!< CCAP_T::PLNSL: PLNSHML Mask */ + +#define CCAP_PLNSL_PLNSHNL_Pos (8) /*!< CCAP_T::PLNSL: PLNSHNL Position */ +#define CCAP_PLNSL_PLNSHNL_Msk (0xfful << CCAP_PLNSL_PLNSHNL_Pos) /*!< CCAP_T::PLNSL: PLNSHNL Mask */ + +#define CCAP_PLNSL_PLNSVML_Pos (16) /*!< CCAP_T::PLNSL: PLNSVML Position */ +#define CCAP_PLNSL_PLNSVML_Msk (0xfful << CCAP_PLNSL_PLNSVML_Pos) /*!< CCAP_T::PLNSL: PLNSVML Mask */ + +#define CCAP_PLNSL_PLNSVNL_Pos (24) /*!< CCAP_T::PLNSL: PLNSVNL Position */ +#define CCAP_PLNSL_PLNSVNL_Msk (0xfful << CCAP_PLNSL_PLNSVNL_Pos) /*!< CCAP_T::PLNSL: PLNSVNL Mask */ + +#define CCAP_FRCTL_FRM_Pos (0) /*!< CCAP_T::FRCTL: FRM Position */ +#define CCAP_FRCTL_FRM_Msk (0x3ful << CCAP_FRCTL_FRM_Pos) /*!< CCAP_T::FRCTL: FRM Mask */ + +#define CCAP_FRCTL_FRN_Pos (8) /*!< CCAP_T::FRCTL: FRN Position */ +#define CCAP_FRCTL_FRN_Msk (0x3ful << CCAP_FRCTL_FRN_Pos) /*!< CCAP_T::FRCTL: FRN Mask */ + +#define CCAP_STRIDE_PKTSTRIDE_Pos (0) /*!< CCAP_T::STRIDE: PKTSTRIDE Position */ +#define CCAP_STRIDE_PKTSTRIDE_Msk (0x3ffful << CCAP_STRIDE_PKTSTRIDE_Pos) /*!< CCAP_T::STRIDE: PKTSTRIDE Mask */ + +#define CCAP_STRIDE_PLNSTRIDE_Pos (16) /*!< CCAP_T::STRIDE: PLNSTRIDE Position */ +#define CCAP_STRIDE_PLNSTRIDE_Msk (0x3ffful << CCAP_STRIDE_PLNSTRIDE_Pos) /*!< CCAP_T::STRIDE: PLNSTRIDE Mask */ + +#define CCAP_FIFOTH_PKTFTH_Pos (24) /*!< CCAP_T::FIFOTH: PKTFTH Position */ +#define CCAP_FIFOTH_PKTFTH_Msk (0x1ful << CCAP_FIFOTH_PKTFTH_Pos) /*!< CCAP_T::FIFOTH: PKTFTH Mask */ + +#define CCAP_FIFOTH_OVF_Pos (31) /*!< CCAP_T::FIFOTH: OVF Position */ +#define CCAP_FIFOTH_OVF_Msk (0x1ul << CCAP_FIFOTH_OVF_Pos) /*!< CCAP_T::FIFOTH: OVF Mask */ + +#define CCAP_CMPADDR_CMPADDR_Pos (0) /*!< CCAP_T::CMPADDR: CMPADDR Position */ +#define CCAP_CMPADDR_CMPADDR_Msk (0xfffffffful << CCAP_CMPADDR_CMPADDR_Pos) /*!< CCAP_T::CMPADDR: CMPADDR Mask */ + +#define CCAP_PKTSM_PKTSHMH_Pos (0) /*!< CCAP_T::PKTSM: PKTSHMH Position */ +#define CCAP_PKTSM_PKTSHMH_Msk (0xfful << CCAP_PKTSM_PKTSHMH_Pos) /*!< CCAP_T::PKTSM: PKTSHMH Mask */ + +#define CCAP_PKTSM_PKTSHNH_Pos (8) /*!< CCAP_T::PKTSM: PKTSHNH Position */ +#define CCAP_PKTSM_PKTSHNH_Msk (0xfful << CCAP_PKTSM_PKTSHNH_Pos) /*!< CCAP_T::PKTSM: PKTSHNH Mask */ + +#define CCAP_PKTSM_PKTSVMH_Pos (16) /*!< CCAP_T::PKTSM: PKTSVMH Position */ +#define CCAP_PKTSM_PKTSVMH_Msk (0xfful << CCAP_PKTSM_PKTSVMH_Pos) /*!< CCAP_T::PKTSM: PKTSVMH Mask */ + +#define CCAP_PKTSM_PKTSVNH_Pos (24) /*!< CCAP_T::PKTSM: PKTSVNH Position */ +#define CCAP_PKTSM_PKTSVNH_Msk (0xfful << CCAP_PKTSM_PKTSVNH_Pos) /*!< CCAP_T::PKTSM: PKTSVNH Mask */ + +#define CCAP_PLNSM_PLNSHMH_Pos (0) /*!< CCAP_T::PLNSM: PLNSHMH Position */ +#define CCAP_PLNSM_PLNSHMH_Msk (0xfful << CCAP_PLNSM_PLNSHMH_Pos) /*!< CCAP_T::PLNSM: PLNSHMH Mask */ + +#define CCAP_PLNSM_PLNSHNH_Pos (8) /*!< CCAP_T::PLNSM: PLNSHNH Position */ +#define CCAP_PLNSM_PLNSHNH_Msk (0xfful << CCAP_PLNSM_PLNSHNH_Pos) /*!< CCAP_T::PLNSM: PLNSHNH Mask */ + +#define CCAP_PLNSM_PLNSVMH_Pos (16) /*!< CCAP_T::PLNSM: PLNSVMH Position */ +#define CCAP_PLNSM_PLNSVMH_Msk (0xfful << CCAP_PLNSM_PLNSVMH_Pos) /*!< CCAP_T::PLNSM: PLNSVMH Mask */ + +#define CCAP_PLNSM_PLNSVNH_Pos (24) /*!< CCAP_T::PLNSM: PLNSVNH Position */ +#define CCAP_PLNSM_PLNSVNH_Msk (0xfful << CCAP_PLNSM_PLNSVNH_Pos) /*!< CCAP_T::PLNSM: PLNSVNH Mask */ + +#define CCAP_CURADDRP_CURADDR_Pos (0) /*!< CCAP_T::CURADDRP: CURADDR Position */ +#define CCAP_CURADDRP_CURADDR_Msk (0xfffffffful << CCAP_CURADDRP_CURADDR_Pos) /*!< CCAP_T::CURADDRP: CURADDR Mask */ + +#define CCAP_PKTBA0_BASEADDR_Pos (0) /*!< CCAP_T::PKTBA0: BASEADDR Position */ +#define CCAP_PKTBA0_BASEADDR_Msk (0xfffffffful << CCAP_PKTBA0_BASEADDR_Pos) /*!< CCAP_T::PKTBA0: BASEADDR Mask */ + +/**@}*/ /* CCAP_CONST */ +/**@}*/ /* end of CCAP register group */ +/**@}*/ /* end of REGISTER group */ + +#if defined ( __CC_ARM ) + #pragma no_anon_unions +#endif + +#endif /* __CCAP_REG_H__ */ diff --git a/bsp/nuvoton/libraries/ma35/Device/Nuvoton/MA35D1/Include/clk_reg.h b/bsp/nuvoton/libraries/ma35/Device/Nuvoton/MA35D1/Include/clk_reg.h new file mode 100644 index 0000000000..96a6945de9 --- /dev/null +++ b/bsp/nuvoton/libraries/ma35/Device/Nuvoton/MA35D1/Include/clk_reg.h @@ -0,0 +1,2596 @@ +/**************************************************************************//** + * @file clk_reg.h + * @brief CLK register definition header file + * + * SPDX-License-Identifier: Apache-2.0 + * @copyright (C) 2020 Nuvoton Technology Corp. All rights reserved. + *****************************************************************************/ +#ifndef __CLK_REG_H__ +#define __CLK_REG_H__ + +#if defined ( __CC_ARM ) + #pragma anon_unions +#endif + +/** + @addtogroup REGISTER Control Register + @{ +*/ + +typedef struct +{ + /** + * @var PLL_T::CTL0 + * Offset: 0x0 PLL Control Register 0(Write Protect) + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[10:0] |FBDIV |PLL Feedback Divider Control (Write Protect) + * | | |Set the feedback divider factor (N) from 16 to 2047. + * | | |The N = FBDIV[10:0]. + * | | |Note: This bit is write protected + * | | |Refer to the SYS_RLKTZS register + * | | |For PLL3, PLL4, and PLL5, user can also refer to the SYS_RLKTZNS register if SYSSIAEN is 1. + * |[17:12] |INDIV |PLL Reference Input Divider Control (Write Protect) + * | | |Set the reference divider factor (M) from 1 to 63. + * | | |The M = INDIV[5:0]. + * | | |Note: This bit is write protected + * | | |Refer to the SYS_RLKTZS register + * | | |For PLL3, PLL4, and PLL5, user can also refer to the SYS_RLKTZNS register if SYSSIAEN is 1. + * |[19:18] |MODE |Operation Mode Selection(Write Protect) + * | | |00 = Integer mode. + * | | |In this mode, the rising edges of the two clocks at the input of PFD are phase aligned + * | | |And the output clock frequency is at multiples of the input clock frequency contingent on the configuration of OUTDIV, INDIV and FBDIV. + * | | |01 = Fractional mode. + * | | |This mode is suitable for applications which need small output frequency steps, like 20 kHz + * | | |The jitter performance in this mode may be worse than in Integer Mode. + * | | |In this mode, the output clock frequency is at the fractional multiples of the input clock frequency + * | | |By setting the control pins FRAC [23:0], a small output frequency step is achieved.. + * | | |10 = Spread Spectrum Mode. + * | | |This mode is suitable for In this mode the output frequency of PLL will be modulated by triangle wave + * | | |It is for EMI consideration. + * | | |By setting SSRATE [10:0] and SLOPE [23:0], the modulation index and the modulation frequency can be programmed. + * | | |Note: This bit is write protected + * | | |Refer to the SYS_RLKTZS register + * | | |For PLL3, PLL4, and PLL5, user can also refer to the SYS_RLKTZNS register if SYSSIAEN is 1. + * |[30:20] |SSRATE |Spreading Frequency Control (Write Protect) + * | | |Set the spread step factor SSRATE from 0 to 2047, + * | | |SSRATE = SSRATE [10:0]. + * | | |Note: This bit is write protected + * | | |Refer to the SYS_RLKTZS register + * | | |For PLL3, PLL4, and PLL5, user can also refer to the SYS_RLKTZNS register if SYSSIAEN is 1. + * @var PLL_T::CTL1 + * Offset: 0x4 PLL Control Register 1(Write Protect) + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[0] |PD |Power-down Mode (Write Protect) + * | | |0 = PLL is enable (in normal mode). + * | | |1 = PLL is disable (in Power-down mode) (default). + * | | |Note: This bit is write protected + * | | |Refer to the SYS_RLKTZS register + * | | |For PLL3, PLL4, and PLL5, user can also refer to the SYS_RLKTZNS register if SYSSIAEN is 1. + * |[1] |BP |PLL Bypass Control (Write Protect) + * | | |0 = PLL is in normal mode (default). + * | | |1 = PLL clock output is same as PLL input clock Fref. + * | | |Note: This bit is write protected + * | | |Refer to the SYS_RLKTZS register + * | | |For PLL3, PLL4, and PLL5, user can also refer to the SYS_RLKTZNS register if SYSSIAEN is 1. + * |[6:4] |OUTDIV |PLL Output Divider Control (Write Protect) + * | | |Set the output divider factor (P) from 1 to 7. + * | | |P = OUTDIV[2:0]. + * | | |Note: This bit is write protected + * | | |Refer to the SYS_RLKTZS register + * | | |For PLL3, PLL4, and PLL5, user can also refer to the SYS_RLKTZNS register if SYSSIAEN is 1. + * |[31:8] |FRAC |PLL Fractional Portion of DN Value (Write Protect) + * | | |Set the fraction part (X) of Fractional Portion of DN Value factor. + * | | |The X = FRAC[23:0] / 224. + * | | |Note: This bit is write protected + * | | |Refer to the SYS_RLKTZS register + * | | |For PLL3, PLL4, and PLL5, user can also refer to the SYS_RLKTZNS register if SYSSIAEN is 1. + * @var PLL_T::CTL2 + * Offset: 0x8 PLL Control Register 2(Write Protect) + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[23:0] |SLOPE |PLL Stable Counter Selection (Write Protect) + * | | |Set the spread step factor SLOPE from 0 to 16777215, + * | | |SLOPE = SLOPE[23:0]. + * | | |Note 1: This bit is write protected + * | | |Refer to the SYS_RLKTZS register + * | | |For PLL3, PLL4, and PLL5, user can also refer to the SYS_RLKTZNS register if SYSSIAEN is 1. + * @var PLL_T::RESERVE + * Offset: 0xC + * --------------------------------------------------------------------------------------------------- + */ + __IO uint32_t CTL0; /*!< [0x0000] PLL Control Register 0 of PLL Channel n.(Write Protect) */ + __IO uint32_t CTL1; /*!< [0x0004] PLL Control Register 1 of PLL Channel n.(Write Protect) */ + __IO uint32_t CTL2; /*!< [0x0008] PLL Control Register 2 of PLL Channel n.(Write Protect) */ + __IO uint32_t RESERVE; /*!< [0x000c] Reserved */ + +} PLL_T; + +/** + @addtogroup CLK System Clock Controller(CLK) + Memory Mapped Structure for CLK Controller +@{ */ + +typedef struct +{ + + + /** + * @var CLK_T::PWRCTL + * Offset: 0x00 System Power-down Control Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[0] |HXTEN |HXT Enable Bit (Write Protect) + * | | |0 = 24 MHz external high speed crystal (HXT) Disabled. + * | | |1 = 24 MHz external high speed crystal (HXT) Enabled. + * | | |Note 1: This bit is write protected. Refer to the SYS_RLKTZS register. + * | | |Note 2: HXT cannot be disabled and HXTEN will always read as 1 if HCLK clock source is selected from HXT or PLL (clock source from HXT). + * |[1] |LXTEN |LXT Enable Bit (Write Protect) + * | | |0 = 32.768 kHz external low speed crystal (external LXT) Disabled. + * | | |1 = 32.768 kHz external low speed crystal (external LXT) Enabled. + * | | |Note 1: This bit is write protected. Refer to the SYS_RLKTZS register. + * | | |Note 2: LXT cannot be disabled and LXTEN will always read as 1 if HCLK clock source is selected from LXT when the LXT clock source is selected as external LXT by setting C32KS(RTC_LXTCTL[6]) to 1. + * |[2] |HIRCEN |HIRC Enable Bit (Write Protect) + * | | |The HCLK default clock source is from HIRC and this bit default value is 1. + * | | |0 = 12 MHz internal high speed RC oscillator (HIRC) Disabled. + * | | |1 = 12 MHz internal high speed RC oscillator (HIRC) Enabled. + * | | |Note 1: This bit is write protected. Refer to the SYS_RLKTZS register. + * | | |Note 2: HIRC cannot be disabled and HIRCEN will always read as 1 if HXTFQIEN or is set. + * |[3] |LIRCEN |LIRC Enable Bit (Write Protect) + * | | |0 = 32 kHz internal low speed RC oscillator (LIRC) Disabled. + * | | |1 = 32 kHz internal low speed RC oscillator (LIRC) Enabled. + * | | |Note 1: This bit is write protected. Refer to the SYS_RLKTZS register. + * |[10] |HXTDS |HXT Drive Current Strength (Write Protect) + * | | |0 = Lower power consumption requirement for 2.5V~3.3V I/O power application. + * | | |1 = higher noise immunity requirement for 2.5V~3.3V I/O power application.(default) + * | | |Note: This bit is write protected. Refer to the SYS_RLKTZS register. + * |[11] |SYSPLLAPD |SYSPLL Auto Power Down Option when CA35 & RTP-M4 are Power Down (Write Protect) + * | | |0 = When CA35 and RTP-M4 are both in WFI, the PD pin of SYS-PLL is the same as CLK_PLL2CTL1[0]. + * | | |1 = When CA35 and RTP-M4 are both in WFI, set the PD pin of SYS-PLL to high automatically. + * | | |Note 1: This bit is write protected. Refer to the SYS_RLKTZS register. + * | | |Note 2: This bit only works when the CA35 and RTP-M4 are not both in Power-down mode + * | | |If one of RTP-M4 and CA35 is not in Power-down mode, the PLL PD pin status is the controlled by CLK_PLL1CTL1[0]. + * |[12] |CAPLLAPD |CAPLL Auto Power Down Option when CA35 is Power Gating (Write Protect) + * | | |0 = When CA35 core power is not ready, the PD pin of CA-PLL is the same as CLK_PLL0CTL1[0]. + * | | |1 = When CA35 core power is not ready, set the PD pin of CA-PLL to high automatically. + * | | |Note 1: This bit is write protected. Refer to the SYS_RLKTZS register. + * | | |Note 2: This bit only works when the CA35 core power is not ready + * | | |If CA35 core power is ready, the PLL PD pin status is the controlled by CLK_PLL0CTL1[0]. + * |[13] |DDRPLLAPD |DDRPLL Auto Power Down Option when CA35 is Power Gating (Write Protect) + * | | |0 = When CA35 core power is not ready, the PD pin of DDR-PLL is the same as CLK_PLL2CTL1[0]. + * | | |1 = When CA35 core power is not ready, set the PD pin of DDR-PLL to high automatically. + * | | |Note 1: This bit is write protected. Refer to the SYS_RLKTZS register. + * | | |Note 2: This bit only works when the CA35 core power is not ready + * | | |If CA35 core power is ready, the PLL PD pin status is the controlled by CLK_PLL2CTL1[0]. + * |[14] |HXTAOFF |HXT Auto Off Option when CA35 is Power Gating (Write Protect) + * | | |0 = When CA35 core power is not ready, the HXT enable bit is the same as CLK_PWRCTL[0]. + * | | |1 = When CA35 core power is not ready, switch the HXT enable bit to low automatically. + * | | |Note 1: This bit is write protected. Refer to the SYS_RLKTZS register. + * | | |Note 2: This bit only works when the CA35 core power is not ready + * | | |If CA35 core power is ready, the HXT enable bit is the controlled by CLK_PWRCTL[0]. + * |[15] |HIRCAOFF |HIRC Auto Off Option when CA35 is Power Gating (Write Protect) + * | | |0 = When CA35 core power is not ready, the HIRC enable bit is the same as CLK_PWRCTL[2]. + * | | |1 = When CA35 core power is not ready, switch the HIRC enable bit to low automatically. + * | | |Note 1: This bit is write protected. Refer to the SYS_RLKTZS register. + * | | |Note 2: This bit only works when the CA35 core power is not ready + * | | |If CA35 core power is ready, the HIRC enable bit is the controlled by CLK_PWRCTL[2]. + * |[17:16] |LXTSTBS |LXT Stable Count Select (Write Protect) + * | | |00 = LXT stable count = 16384 clocks. + * | | |01 = LXT stable count = 65536 clocks. + * | | |10 = LXT stable count = 131072 clocks. + * | | |11 = LXT stable count = 327680 clocks. + * | | |Note: These bits are write protected. Refer to the SYS_RLKTZS register. + * |[21] |GICAOFF |GIC CLK Auto Off Option when CA35 is Power Gating (Write Protect) + * | | |0 = When CA35 core power is not ready, the GIC CLK will not be gated. + * | | |1 = When CA35 core power is not ready, the GIC CLK will be gated. + * | | |Note 1: This bit is write protected. Refer to the SYS_RLKTZS register. + * | | |Note 2: This bit only works when the CA35 core power is not ready + * | | |If CA35 core power is ready, the HIRC enable bit is the controlled by CLK_PWRCTL[2]. + * |[22] |HXTAPD |HXT Auto Off Option when CA35 is Power Down (Write Protect) + * | | |0 = When CA35 cores are in WFI, the HXT enable bit is the same as CLK_PWRCTL[0]. + * | | |1 = When CA35 cores are in WFI, switch the HXT enable bit to low automatically. + * | | |Note 1: This bit is write protected. Refer to the SYS_RLKTZS register. + * | | |Note 2: This bit only works when the CA35 cores are in the WFI + * | | |If CA35 cores are not in WFI, the HXT enable bit is the controlled by CLK_PWRCTL[0]. + * |[23] |HIRCAPD |HIRC Auto Off Option when CA35 is Power Down (Write Protect) + * | | |0 = When CA35 cores are in WFI, the HIRC enable bit is the same as CLK_PWRCTL[2]. + * | | |1 = When CA35 cores are in WFI, switch the HIRC enable bit to low automatically. + * | | |Note 1: This bit is write protected. Refer to the SYS_RLKTZS register. + * | | |Note 2: This bit only works when the CA35 cores are in the WFI + * | | |If CA35 cores are not in WFI, the HIRC enable bit is the controlled by CLK_PWRCTL[2]. + * @var CLK_T::SYSCLK0 + * Offset: 0x04 AXI and AHB Device Clock Enable Control Register 0 + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[1] |RTPEN |CPU RTP CortexM4 AHB Clock Enable Bit (Write Protect) + * | | |0 = Cortex M4 AHB clock Disabled. + * | | |1 = Cortex M4 AHB clock Enabled. + * | | |Note: This bit is write protected. Refer to the SYS_RLKTZS register. + * |[2] |TAHBCKEN |TSI AHB HCLK Clock Enable Bit (Write Protect) + * | | |0 = TSI AHB HCLK Disabled. + * | | |1 = TSI AHB HCLK Enabled. + * | | |Note: This bit is write protected. Refer to the SYS_RLKTZS register. + * |[3] |LVRDBEN |LVR Debounce Clock Enable Bit (Write Protect) + * | | |0 = LVR Debounce clock Disabled. + * | | |1 = LVR Debounce clock Enabled. + * | | |Note: This bit is write protected. Refer to the SYS_RLKTZS register. + * |[4] |DDR0CKEN |DDR Port0 Clock Enable Bit (Write Protect) + * | | |0 = DDR Port0 peripheral clock Disabled. + * | | |1 = DDR Port0 peripheral clock Enabled. + * | | |Note 1: This bit is write protected. Refer to the SYS_RLKTZS register. + * | | |Note 2: The peripheral clock of DDR Port 1, DDR Port 2, DDR Port 3, DDR Port 4, DDR Port5, DDR Port7 are enabled automatically by the peripheral clock enable bit of the IP on the corresponding bus. + * |[5] |DDR6CKEN |DDR Port6 Clock Enable Bit (Write Protect) + * | | |0 = DDR Port6 peripheral clock Disabled. + * | | |1 = DDR Port6 peripheral clock Enabled. + * | | |Note 1: This bit is write protected. Refer to the SYS_RLKTZS register. + * | | |Note 2: The peripheral clock of DDR Port 1, DDR Port 2, DDR Port 3, DDR Port 4, DDR Port5, DDR Port7 are enabled automatically by the peripheral clock enable bit of the IP on the corresponding bus. + * |[8] |CANFD0CKEN|CANFD0 Clock Enable Bit + * | | |0 = CANFD0 clock Disabled. + * | | |1 = CANFD0 clock Enabled. + * |[9] |CANFD1CKEN|CANFD1 Clock Enable Bit + * | | |0 = CANFD1 clock Disabled. + * | | |1 = CANFD1 clock Enabled. + * |[10] |CANFD2CKEN|CANFD2 Clock Enable Bit + * | | |0 = CANFD2 clock Disabled. + * | | |1 = CANFD2 clock Enabled. + * |[11] |CANFD3CKEN|CANFD3 Clock Enable Bit + * | | |0 = CANFD3 clock Disabled. + * | | |1 = CANFD3 clock Enabled. + * |[16] |SDH0EN |SD0 Host Controller AHB clock Enable Bit + * | | |0 = SDH0 controller AHB clock Disabled. + * | | |1 = SDH0 controller AHB clock Enabled. + * |[17] |SDH1EN |SD1 Host Controller AHB clock Enable Bit + * | | |0 = SDH1 controller AHB clock Disabled. + * | | |1 = SDH1 controller AHB clock Enabled. + * |[18] |NANDEN |NAND Controller Clock Enable Bit + * | | |0 = NAND controller clock Disabled. + * | | |1 = NAND controller clock Enabled. + * |[19] |USBDEN |USBD Clock Enable Bit + * | | |0 = USBD clock Disabled. + * | | |1 = USBD clock Enabled. + * |[20] |USBHEN |USBH Clock Enable Bit (TZNS) + * | | |0 = USBH clock Disabled. + * | | |1 = USBH clock Enabled. + * |[21] |HUSBH0EN |High Speed USBH Clock Enable Bit (TZNS) + * | | |0 = HUSBH0 clock Disabled. + * | | |1 = HUSBH0 clock Enabled. + * |[22] |HUSBH1EN |High Speed USBH Clock Enable Bit (TZNS) + * | | |0 = HUSBH1 clock Disabled. + * | | |1 = HUSBH1 clock Enabled. + * |[24] |GFXEN |GFX Clock Enable Bit (TZNS) + * | | |0 = GFX clock Disabled. + * | | |1 = GFX clock Enabled. + * |[25] |VDECEN |VC8000 Clock Enable Bit (TZNS) + * | | |0 = VC8000 clock Disabled. + * | | |1 = VC8000 clock Enabled. + * |[26] |DCUEN |DC Ultra Clock Enable Bit (TZNS) + * | | |0 = DC Ultra clock Disabled. + * | | |1 = DC Ultra clock Enabled. + * |[27] |GMAC0EN |Gigabit Ethernet MAC 0 AXI Clock Enable Bit (TZNS) + * | | |0 = Gigabit Ethernet MAC 0 AXI clock Disabled. + * | | |1 = Gigabit Ethernet MAC 0 AXI clock Enabled. + * |[28] |GMAC1EN |Gigabit Ethernet MAC 1 AXI Clock Enable Bit (TZNS) + * | | |0 = Gigabit Ethernet MAC 1 AXI clock Disabled. + * | | |1 = Gigabit Ethernet MAC 1 AXI clock Enabled. + * |[29] |CCAP0EN |CCAP0 Clock Enable Bit (TZNS) + * | | |0 = CCAP0 clock Disabled. + * | | |1 = CCAP0 clock Enabled. + * |[30] |CCAP1EN |CCAP1 Clock Enable Bit (TZNS) + * | | |0 = CCAP1 clock Disabled. + * | | |1 = CCAP1 clock Enabled. + * @var CLK_T::SYSCLK1 + * Offset: 0x08 AXI and AHB Device Clock Enable Control Register 1 + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[0] |PDMA0EN |PDMA0 Controller Clock Enable Bit + * | | |0 = PDMA0 peripheral clock Disabled. + * | | |1 = PDMA0 peripheral clock Enabled. + * |[1] |PDMA1EN |PDMA1 Controller Clock Enable Bit + * | | |0 = PDMA1 peripheral clock Disabled. + * | | |1 = PDMA1 peripheral clock Enabled. + * |[2] |PDMA2EN |PDMA2 Controller Clock Enable Bit + * | | |0 = PDMA2 peripheral clock Disabled. + * | | |1 = PDMA2 peripheral clock Enabled. + * |[3] |PDMA3EN |PDMA3 Controller Clock Enable Bit + * | | |0 = PDMA3 peripheral clock Disabled. + * | | |1 = PDMA3 peripheral clock Enabled. + * |[4] |WH0CKEN |Wormhole 0 Peripheral Clock Enable Bit (Write Protect, TZNS) + * | | |0 = Wormhole 0 clock Disabled. + * | | |1 = Wormhole 0 clock Enabled. + * | | |Note: This bit is write protected. Refer to the SYS_RLKTZNS register. + * |[5] |WH1CKEN |Wormhole 1 Peripheral Clock Enable Bit (Write Protect) + * | | |0 = Wormhole 1 clock Disabled. + * | | |1 = Wormhole 1 clock Enabled. + * | | |Note: This bit is write protected. Refer to the SYS_RLKTZS register. + * |[6] |HWSCKEN |Hardware Semaphore Clock Enable Bit (Write Protect, TZNS) + * | | |0 = Hardware Semaphore peripheral clock Disabled. + * | | |1 = Hardware Semaphore clock Enabled. + * | | |Note: This bit is write protected. Refer to the SYS_RLKTZNS register. + * |[7] |EBICKEN |EBI Controller Clock Enable Bit + * | | |0 = EBI peripheral clock Disabled. + * | | |1 = EBI peripheral clock Enabled. + * |[8] |SRAM0CKEN |SRAM Bank0 Controller Clock Enable Bit (Write Protect) + * | | |0 = SRAM bank0 clock Disabled. + * | | |1 = SRAM bank0 clock Enabled. + * | | |Note: This bit is write protected. Refer to the SYS_RLKTZS register. + * |[9] |SRAM1CKEN |SRAM Bank1 Controller Clock Enable Bit (Write Protect) + * | | |0 = SRAM bank1 clock Disabled. + * | | |1 = SRAM bank1 clock Enabled. + * | | |Note: This bit is write protected. Refer to the SYS_RLKTZS register. + * |[10] |ROMCKEN |ROM AHB Clock Enable Bit (Write Protect) + * | | |0 = ROM AHB clock Disabled. + * | | |1 = ROM AHB clock Enabled. + * | | |Note: This bit is write protected. Refer to the SYS_RLKTZS register. + * |[11] |TRACKEN |Coresight Trace Clock Enable Bit (Write Protect) + * | | |0 = Coresight trace clock Disabled. + * | | |1 = Coresight trace clock Enabled. + * | | |Note: This bit is write protected. Refer to the SYS_RLKTZS register. + * |[12] |DBGCKEN |Coresight Debug Clock Enable Bit (Write Protect) + * | | |0 = Coresight debug clock Disabled. + * | | |1 = Coresight debug clock Enabled. + * | | |Note: This bit is write protected. Refer to the SYS_RLKTZS register. + * |[13] |CLKOCKEN |CLKO Clock Enable Bit (Write Protect) + * | | |0 = CLKO clock Disabled. + * | | |1 = CLKO clock Enabled. + * | | |Note: This bit is write protected. Refer to the SYS_RLKTZS register. + * |[14] |GTMRCKEN |Cortex A35 Generic Timer Clock Enable Bit (Write Protect) + * | | |0 = Cortex A35 Generic timer clock Disabled. + * | | |1 = Cortex A35 Generic timer clock Enabled. + * | | |Note: This bit is write protected. Refer to the SYS_RLKTZS register. + * |[16] |GPACKEN |GPIOA AHB Clock Enable Bit + * | | |0 = GPIOA port clock Disabled. + * | | |1 = GPIOA port clock Enabled. + * |[17] |GPBCKEN |GPIOB AHB Clock Enable Bit + * | | |0 = GPIOB port clock Disabled. + * | | |1 = GPIOB port clock Enabled. + * |[18] |GPCCKEN |GPIOC AHB Clock Enable Bit + * | | |0 = GPIOC port clock Disabled. + * | | |1 = GPIOC port clock Enabled. + * |[19] |GPDCKEN |GPIOD AHB Clock Enable Bit + * | | |0 = GPIOD port clock Disabled. + * | | |1 = GPIOD port clock Enabled. + * |[20] |GPECKEN |GPIOE AHB Clock Enable Bit + * | | |0 = GPIOE port clock Disabled. + * | | |1 = GPIOE port clock Enabled. + * |[21] |GPFCKEN |GPIOF AHB Clock Enable Bit + * | | |0 = GPIOF port clock Disabled. + * | | |1 = GPIOF port clock Enabled. + * |[22] |GPGCKEN |GPIOG AHB Clock Enable Bit + * | | |0 = GPIOG port clock Disabled. + * | | |1 = GPIOG port clock Enabled. + * |[23] |GPHCKEN |GPIOH AHB Clock Enable Bit + * | | |0 = GPIOH port clock Disabled. + * | | |1 = GPIOH port clock Enabled. + * |[24] |GPICKEN |GPIOI AHB Clock Enable Bit + * | | |0 = GPIOI port clock Disabled. + * | | |1 = GPIOI port clock Enabled. + * |[25] |GPJCKEN |GPIOJ AHB Clock Enable Bit + * | | |0 = GPIOJ port clock Disabled. + * | | |1 = GPIOJ port clock Enabled. + * |[26] |GPKCKEN |GPIOK AHB Clock Enable Bit + * | | |0 = GPIOK port clock Disabled. + * | | |1 = GPIOK port clock Enabled. + * |[27] |GPLCKEN |GPIOL AHB Clock Enable Bit + * | | |0 = GPIOL port clock Disabled. + * | | |1 = GPIOL port clock Enabled. + * |[28] |GPMCKEN |GPIOM AHB Clock Enable Bit + * | | |0 = GPIOM port clock Disabled. + * | | |1 = GPIOM port clock Enabled. + * |[29] |GPNCKEN |GPION AHB Clock Enable Bit + * | | |0 = GPION port clock Disabled. + * | | |1 = GPION port clock Enabled. + * @var CLK_T::APBCLK0 + * Offset: 0x0C APB Devices Clock Enable Control Register 0 + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[0] |TMR0CKEN |Timer0 Clock Enable Bit + * | | |0 = Timer0 clock Disabled. + * | | |1 = Timer0 clock Enabled. + * |[1] |TMR1CKEN |Timer1 Clock Enable Bit + * | | |0 = Timer1 clock Disabled. + * | | |1 = Timer1 clock Enabled. + * |[2] |TMR2CKEN |Timer2 Clock Enable Bit + * | | |0 = Timer2 clock Disabled. + * | | |1 = Timer2 clock Enabled. + * |[3] |TMR3CKEN |Timer3 Clock Enable Bit + * | | |0 = Timer3 clock Disabled. + * | | |1 = Timer3 clock Enabled. + * |[4] |TMR4CKEN |Timer4 Clock Enable Bit + * | | |0 = Timer4 clock Disabled. + * | | |1 = Timer4 clock Enabled. + * |[5] |TMR5CKEN |Timer5 Clock Enable Bit + * | | |0 = Timer5 clock Disabled. + * | | |1 = Timer5 clock Enabled. + * |[6] |TMR6CKEN |Timer6 Clock Enable Bit + * | | |0 = Timer6 clock Disabled. + * | | |1 = Timer6 clock Enabled. + * |[7] |TMR7CKEN |Timer7 Clock Enable Bit + * | | |0 = Timer7 clock Disabled. + * | | |1 = Timer7 clock Enabled. + * |[8] |TMR8CKEN |Timer8 Clock Enable Bit + * | | |0 = Timer8 clock Disabled. + * | | |1 = Timer8 clock Enabled. + * |[9] |TMR9CKEN |Timer9 Clock Enable Bit + * | | |0 = Timer9 clock Disabled. + * | | |1 = Timer9 clock Enabled. + * |[10] |TMR10CKEN |Timer10 Clock Enable Bit + * | | |0 = Timer10 clock Disabled. + * | | |1 = Timer10 clock Enabled. + * |[11] |TMR11CKEN |Timer11 Clock Enable Bit + * | | |0 = Timer11 clock Disabled. + * | | |1 = Timer11 clock Enabled. + * |[12] |UART0CKEN |UART0 Clock Enable Bit + * | | |0 = UART0 clock Disabled. + * | | |1 = UART0 clock Enabled. + * |[13] |UART1CKEN |UART1 Clock Enable Bit + * | | |0 = UART1 clock Disabled. + * | | |1 = UART1 clock Enabled. + * |[14] |UART2CKEN |UART2 Clock Enable Bit + * | | |0 = UART2 clock Disabled. + * | | |1 = UART2 clock Enabled. + * |[15] |UART3CKEN |UART3 Clock Enable Bit + * | | |0 = UART3 clock Disabled. + * | | |1 = UART3 clock Enabled. + * |[16] |UART4CKEN |UART4 Clock Enable Bit + * | | |0 = UART4 clock Disabled. + * | | |1 = UART4 clock Enabled. + * |[17] |UART5CKEN |UART5 Clock Enable Bit + * | | |0 = UART5 clock Disabled. + * | | |1 = UART5 clock Enabled. + * |[18] |UART6CKEN |UART6 Clock Enable Bit + * | | |0 = UART6 clock Disabled. + * | | |1 = UART6 clock Enabled. + * |[19] |UART7CKEN |UART7 Clock Enable Bit + * | | |0 = UART7 clock Disabled. + * | | |1 = UART7 clock Enabled. + * |[20] |UART8CKEN |UART8 Clock Enable Bit + * | | |0 = UART8 clock Disabled. + * | | |1 = UART8 clock Enabled. + * |[21] |UART9CKEN |UART9 Clock Enable Bit + * | | |0 = UART9 clock Disabled. + * | | |1 = UART9 clock Enabled. + * |[22] |UART10CKEN|UART10 Clock Enable Bit + * | | |0 = UART10 clock Disabled. + * | | |1 = UART10 clock Enabled. + * |[23] |UART11CKEN|UART11 Clock Enable Bit + * | | |0 = UART11 clock Disabled. + * | | |1 = UART11 clock Enabled. + * |[24] |UART12CKEN|UART12 Clock Enable Bit + * | | |0 = UART12 clock Disabled. + * | | |1 = UART12 clock Enabled. + * |[25] |UART13CKEN|UART13 Clock Enable Bit + * | | |0 = UART13 clock Disabled. + * | | |1 = UART13 clock Enabled. + * |[26] |UART14CKEN|UART14 Clock Enable Bit + * | | |0 = UART14 clock Disabled. + * | | |1 = UART14 clock Enabled. + * |[27] |UART15CKEN|UART15 Clock Enable Bit + * | | |0 = UART15 clock Disabled. + * | | |1 = UART15 clock Enabled. + * |[28] |UART16CKEN|UART16 Clock Enable Bit + * | | |0 = UART16 clock Disabled. + * | | |1 = UART16 clock Enabled. + * |[29] |RTCCKEN |RTC Clock Enable Bit (Shared) + * | | |0 = RTC Clock Disabled. + * | | |1 = RTC Clock Enabled. + * | | |Note: This bit is write protected. Refer to the SYS_RLKTZS register. + * |[30] |DDRPCKEN |DDR PHY Utility Block Clock Enable Bit + * | | |0 = DDR PHY utility clock Disabled. + * | | |1 = DDR PHY utility clock Enabled. + * |[31] |KPICKEN |Keypad Interface Clock Enable Bit + * | | |0 = Keypad interface clock Disabled. + * | | |1 = Keypad interface clock Enabled. + * @var CLK_T::APBCLK1 + * Offset: 0x10 APB Devices Clock Enable Control Register 1 + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[0] |I2C0CKEN |I2C0 Clock Enable Bit + * | | |0 = I2C0 clock Disabled. + * | | |1 = I2C0 clock Enabled. + * |[1] |I2C1CKEN |I2C1 Clock Enable Bit + * | | |0 = I2C1 clock Disabled. + * | | |1 = I2C1 clock Enabled. + * |[2] |I2C2CKEN |I2C2 Clock Enable Bit + * | | |0 = I2C2 clock Disabled. + * | | |1 = I2C2 clock Enabled. + * |[3] |I2C3CKEN |I2C3 Clock Enable Bit + * | | |0 = I2C3 clock Disabled. + * | | |1 = I2C3 clock Enabled. + * |[4] |I2C4CKEN |I2C4 Clock Enable Bit + * | | |0 = I2C4 clock Disabled. + * | | |1 = I2C4 clock Enabled. + * |[5] |I2C5CKEN |I2C5 Clock Enable Bit + * | | |0 = I2C5 clock Disabled. + * | | |1 = I2C5 clock Enabled. + * |[6] |QSPI0CKEN |QSPI0 Clock Enable Bit + * | | |0 = QSPI0 clock Disabled. + * | | |1 = QSPI0 clock Enabled. + * |[7] |QSPI1CKEN |QSPI1 Clock Enable Bit + * | | |0 = QSPI1 clock Disabled. + * | | |1 = QSPI1 clock Enabled. + * |[12] |SC0CKEN |SC0 Clock Enable Bit + * | | |0 = SC0 clock Disabled. + * | | |1 = SC0 clock Enabled. + * |[13] |SC1CKEN |SC1 Clock Enable Bit + * | | |0 = SC1 clock Disabled. + * | | |1 = SC1 clock Enabled. + * |[16] |WDT0CKEN |Watchdog Timer 0 Clock Enable Bit (Write Protect) + * | | |0 = Watchdog timer 0 clock Disabled. + * | | |1 = Watchdog timer 0 clock Enabled. + * | | |Note: This bit is write protected. Refer to the SYS_RLKTZS register. + * |[17] |WDT1CKEN |Watchdog Timer 1 Clock Enable Bit (Write Protect) + * | | |0 = Watchdog timer 1 clock Disabled. + * | | |1 = Watchdog timer 1 clock Enabled. + * | | |Note: This bit is write protected. Refer to the SYS_RLKTZS register or SYS_RLKTZNS register. + * |[18] |WDT2CKEN |Watchdog Timer 2 Clock Enable Bit (Write Protect, SUBM) + * | | |0 = Watchdog timer 2 clock Disabled. + * | | |1 = Watchdog timer 2 clock Enabled. + * | | |Note: This bit is write protected. Refer to the SYS_RLKSUBM register. + * |[24] |EPWM0CKEN |EPWM0 Clock Enable Bit + * | | |0 = EPWM0 clock Disabled. + * | | |1 = EPWM0 clock Enabled. + * |[25] |EPWM1CKEN |EPWM1 Clock Enable Bit + * | | |0 = EPWM1 clock Disabled. + * | | |1 = EPWM1 clock Enabled. + * |[26] |EPWM2CKEN |EPWM2 Clock Enable Bit + * | | |0 = EPWM2 clock Disabled. + * | | |1 = EPWM2 clock Enabled. + * @var CLK_T::APBCLK2 + * Offset: 0x14 APB Devices Clock Enable Control Register 2 + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[0] |I2S0CKEN |I2S0 Clock Enable Bit + * | | |0 = I2S0 Clock Disabled. + * | | |1 = I2S0 Clock Enabled. + * |[1] |I2S1CKEN |I2S1 Clock Enable Bit + * | | |0 = I2S1 Clock Disabled. + * | | |1 = I2S1 Clock Enabled. + * |[2] |SSMCCEN |SSMCC Clock Enable Bit (Write Protect) + * | | |0 = SSMCC clock Disabled. + * | | |1 = SSMCC clock Enabled. + * | | |Note: This bit is write protected. Refer to the SYS_RLKTZS register. + * |[3] |SSPCCEN |SSPCC Clock Enable Bit (Write Protect) + * | | |0 = SSPCC clock Disabled. + * | | |1 = SSPCC clock Enabled. + * | | |Note: This bit is write protected. Refer to the SYS_RLKTZS register. + * |[4] |SPI0CKEN |SPI0 Clock Enable Bit + * | | |0 = SPI0 clock Disabled. + * | | |1 = SPI0 clock Enabled. + * |[5] |SPI1CKEN |SPI1 Clock Enable Bit + * | | |0 = SPI1 clock Disabled. + * | | |1 = SPI1 clock Enabled. + * |[6] |SPI2CKEN |SPI2 Clock Enable Bit + * | | |0 = SPI2 clock Disabled. + * | | |1 = SPI2 clock Enabled. + * |[7] |SPI3CKEN |SPI3 Clock Enable Bit + * | | |0 = SPI3 clock Disabled. + * | | |1 = SPI3 clock Enabled. + * |[8] |ECAP0CKEN |ECAP0 Clock Enable Bit + * | | |0 = ECAP0 clock Disabled. + * | | |1 = ECAP0 clock Enabled. + * |[9] |ECAP1CKEN |ECAP1 Clock Enable Bit + * | | |0 = ECAP1 clock Disabled. + * | | |1 = ECAP1 clock Enabled. + * |[10] |ECAP2CKEN |ECAP2 Clock Enable Bit + * | | |0 = ECAP2 clock Disabled. + * | | |1 = ECAP2 clock Enabled. + * |[12] |QEI0CKEN |QEI0 Clock Enable Bit + * | | |0 = QEI0 clock Disabled. + * | | |1 = QEI0 clock Enabled. + * |[13] |QEI1CKEN |QEI1 Clock Enable Bit + * | | |0 = QEI1 clock Disabled. + * | | |1 = QEI1 clock Enabled. + * |[14] |QEI2CKEN |QEI2 Clock Enable Bit + * | | |0 = QEI2 clock Disabled. + * | | |1 = QEI2 clock Enabled. + * |[24] |ADCCKEN |ADC Clock Enable Bit + * | | |0 = ADC clock Disabled. + * | | |1 = ADC clock Enabled. + * |[25] |EADCCKEN |EADC Clock Enable Bit + * | | |0 = EADC clock Disabled. + * | | |1 = EADC clock Enabled. + * @var CLK_T::CLKSEL0 + * Offset: 0x18 Clock Source Select Control Register 0 + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[1:0] |CA35CKSEL |Cortex A35 CPU Clock Source Selection (Write Protect) + * | | |Before clock switching, the related clock sources (both pre-select and new-select) must be turned on. + * | | |00 = Clock source from HXT. + * | | |01 = Clock source from CA-PLL. + * | | |10 = Clock source from EPLL. + * | | |11 = Clock source from APLL. + * | | |Note 2: These bits are write protected. Refer to the SYS_RLKTZS register. + * |[2] |SYSCK0SEL |System Clock Source Selection (Write Protect) + * | | |Before clock switching, the related clock sources (both pre-select and new-select) must be turned on. + * | | |0 = Clock source from EPLL/2. + * | | |1 = Clock source from SYS-PLL. + * | | |Note: These bits are write protected. Refer to the SYS_RLKTZS register. + * |[3] |LVRDBSEL |LVR Debounce Clock Selection (Write Protect) + * | | |Before clock switching, the related clock sources (both pre-select and new-select) must be turned on. + * | | |0 = Clock source from LIRC. + * | | |1 = Clock source from HIRC. + * | | |Note: These bits are write protected. Refer to the SYS_RLKTZS register. + * |[5:4] |SYSCK1SEL |System Clock Source Selection (Write Protect) + * | | |Before clock switching, the related clock sources (both pre-select and new-select) must be turned on. + * | | |00 = Clock source from HXT. + * | | |01 = Clock source from SYS-PLL. + * | | |10 = Clock source from APLL. + * | | |11 = Clock source from APLL. + * | | |Note: These bits are write protected. Refer to the SYS_RLKTZS register. + * |[10:8] |RTPSTSEL |RTP CortexM4 SysTick Clock Source Selection (Write Protect, SUBM) + * | | |If SYST_CTRL[2]=0, SysTick uses listed clock source below. + * | | |000 = Clock source from HXT. + * | | |001 = Clock source from LXT. + * | | |010 = Clock source from HXT/2. + * | | |011 = Clock source from SYSCLK1/2. + * | | |Others = Clock source from HIRC. + * | | |Note 1: if SysTick clock source is not from HCLK (i.e + * | | |SYST_CTRL[2] = 0), SysTick need clock frequency must less than or equal to HCLK/2. + * | | |Note 2: These bits are write protected. Refer to the SYS_RLKSUBM register. + * |[13:12] |CCAP0SEL |CCAP0 Sensor Clock Source Selection (TZNS) + * | | |Before clock switching, the related clock sources (both pre-select and new-select) must be turned on. + * | | |00 = Clock source from HXT. + * | | |01 = Clock source from VPLL. + * | | |10 = Clock source from APLL. + * | | |11 = Clock source from SYS-PLL. + * |[15:14] |CCAP1SEL |CCAP1 Sensor Clock Source Selection (TZNS) + * | | |Before clock switching, the related clock sources (both pre-select and new-select) must be turned on. + * | | |00 = Clock source from HXT. + * | | |01 = Clock source from VPLL. + * | | |10 = Clock source from APLL. + * | | |11 = Clock source from SYS-PLL. + * |[17:16] |SD0SEL |SD HOST0 Controller Core Logic Clock Source Selection + * | | |Before clock switching, the related clock sources (both pre-select and new-select) must be turned on. + * | | |00 = Clock source from APLL. + * | | |01 = Clock source from VPLL. + * | | |10 = Clock source from SYS-PLL. + * | | |11 = Clock source from SYS-PLL. + * |[19:18] |SD1SEL |SD HOST1 Controller Core Logic Clock Source Selection + * | | |Before clock switching, the related clock sources (both pre-select and new-select) must be turned on. + * | | |00 = Clock source from APLL. + * | | |01 = Clock source from VPLL. + * | | |10 = Clock source from SYS-PLL. + * | | |11 = Clock source from SYS-PLL. + * |[24] |DCUSEL |Display Controller Ultra Core Clock Source Selection (TZNS) + * | | |Before clock switching, the related clock sources (both pre-select and new-select) must be turned on. + * | | |0 = Clock source from EPLL/2. + * | | |1 = Clock source from SYS-PLL. + * |[25] |DCUPSEL |Display Controller Ultra Pixel Clock Source Selection (TZNS) + * | | |Before clock switching, the related clock sources (both pre-select and new-select) must be turned on. + * | | |0 = Clock source from VPLL. + * | | |1 = Clock source from APLL. + * |[26] |GFXSEL |GFX Core Clock Source Selection (TZNS) + * | | |Before clock switching, the related clock sources (both pre-select and new-select) must be turned on. + * | | |0 = Clock source from EPLL. + * | | |1 = Clock source from SYS-PLL. + * |[27] |DBGSEL |Coresight DBG Clock Source Selection (Write Protect) + * | | |Before clock switching, the related clock sources (both pre-select and new-select) must be turned on. + * | | |0 = Clock source from HIRC.1. + * | | |1 = Clock source from SYS-PLL. + * | | |Note: This bit is write protected. Refer to the SYS_RLKTZS register. + * @var CLK_T::CLKSEL1 + * Offset: 0x1C Clock Source Select Control Register 1 + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[2:0] |TMR0SEL |TIMER0 Clock Source Selection + * | | |000 = Clock source from 24 MHz external high speed crystal oscillator (HXT). + * | | |001 = Clock source from 32.768 kHz external low speed crystal oscillator (LXT). + * | | |010 = Clock source from PCLK0. + * | | |011 = Clock source from external clock TM0 pin. + * | | |101 = Clock source from 32 kHz internal low speed RC oscillator (LIRC). + * | | |111 = Clock source from 12 MHz internal high speed RC oscillator (HIRC). + * | | |Others = Reserved. + * |[6:4] |TMR1SEL |TIMER1 Clock Source Selection + * | | |000 = Clock source from 24 MHz external high speed crystal oscillator (HXT). + * | | |001 = Clock source from 32.768 kHz external low speed crystal oscillator (LXT). + * | | |010 = Clock source from PCLK0. + * | | |011 = Clock source from external clock TM1 pin. + * | | |101 = Clock source from 32 kHz internal low speed RC oscillator (LIRC). + * | | |111 = Clock source from 12 MHz internal high speed RC oscillator (HIRC). + * | | |Others = Reserved. + * |[10:8] |TMR2SEL |TIMER2 Clock Source Selection + * | | |000 = Clock source from 24 MHz external high speed crystal oscillator (HXT). + * | | |001 = Clock source from 32.768 kHz external low speed crystal oscillator (LXT). + * | | |010 = Clock source from PCLK1. + * | | |011 = Clock source from external clock TM2 pin. + * | | |101 = Clock source from 32 kHz internal low speed RC oscillator (LIRC). + * | | |111 = Clock source from 12 MHz internal high speed RC oscillator (HIRC). + * | | |Others = Reserved. + * |[14:12] |TMR3SEL |TIMER3 Clock Source Selection + * | | |000 = Clock source from 24 MHz external high speed crystal oscillator (HXT). + * | | |001 = Clock source from 32.768 kHz external low speed crystal oscillator (LXT). + * | | |010 = Clock source from PCLK1. + * | | |011 = Clock source from external clock TM3 pin. + * | | |101 = Clock source from 32 kHz internal low speed RC oscillator (LIRC). + * | | |111 = Clock source from 12 MHz internal high speed RC oscillator (HIRC). + * | | |Others = Reserved. + * |[18:16] |TMR4SEL |TIMER4 Clock Source Selection + * | | |000 = Clock source from 24 MHz external high speed crystal oscillator (HXT). + * | | |001 = Clock source from 32.768 kHz external low speed crystal oscillator (LXT). + * | | |010 = Clock source from PCLK2. + * | | |011 = Clock source from external clock TM4 pin. + * | | |101 = Clock source from 32 kHz internal low speed RC oscillator (LIRC). + * | | |111 = Clock source from 12 MHz internal high speed RC oscillator (HIRC). + * | | |Others = Reserved. + * |[22:20] |TMR5SEL |TIMER5 Clock Source Selection + * | | |000 = Clock source from 24 MHz external high speed crystal oscillator (HXT). + * | | |001 = Clock source from 32.768 kHz external low speed crystal oscillator (LXT). + * | | |010 = Clock source from PCLK2. + * | | |011 = Clock source from external clock TM5 pin. + * | | |101 = Clock source from 32 kHz internal low speed RC oscillator (LIRC). + * | | |111 = Clock source from 12 MHz internal high speed RC oscillator (HIRC). + * | | |Others = Reserved. + * |[26:24] |TMR6SEL |TIMER6 Clock Source Selection + * | | |000 = Clock source from 24 MHz external high speed crystal oscillator (HXT). + * | | |001 = Clock source from 32.768 kHz external low speed crystal oscillator (LXT). + * | | |010 = Clock source from PCLK0. + * | | |011 = Clock source from external clock TM6 pin. + * | | |101 = Clock source from 32 kHz internal low speed RC oscillator (LIRC). + * | | |111 = Clock source from 12 MHz internal high speed RC oscillator (HIRC). + * | | |Others = Reserved. + * |[30:28] |TMR7SEL |TIMER7 Clock Source Selection + * | | |000 = Clock source from 24 MHz external high speed crystal oscillator (HXT). + * | | |001 = Clock source from 32.768 kHz external low speed crystal oscillator (LXT). + * | | |010 = Clock source from PCLK0. + * | | |011 = Clock source from external clock TM7 pin. + * | | |101 = Clock source from 32 kHz internal low speed RC oscillator (LIRC). + * | | |111 = Clock source from 12 MHz internal high speed RC oscillator (HIRC). + * | | |Others = Reserved. + * @var CLK_T::CLKSEL2 + * Offset: 0x20 Clock Source Select Control Register 2 + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[2:0] |TMR8SEL |TIMER8 Clock Source Selection + * | | |000 = Clock source from 24 MHz external high speed crystal oscillator (HXT). + * | | |001 = Clock source from 32.768 kHz external low speed crystal oscillator (LXT). + * | | |010 = Clock source from PCLK1. + * | | |011 = Clock source from external clock TM8 pin. + * | | |101 = Clock source from 32 kHz internal low speed RC oscillator (LIRC). + * | | |111 = Clock source from 12 MHz internal high speed RC oscillator (HIRC). + * | | |Others = Reserved. + * |[6:4] |TMR9SEL |TIMER9 Clock Source Selection + * | | |000 = Clock source from 24 MHz external high speed crystal oscillator (HXT). + * | | |001 = Clock source from 32.768 kHz external low speed crystal oscillator (LXT). + * | | |010 = Clock source from PCLK1. + * | | |011 = Clock source from external clock TM9 pin. + * | | |101 = Clock source from 32 kHz internal low speed RC oscillator (LIRC). + * | | |111 = Clock source from 12 MHz internal high speed RC oscillator (HIRC). + * | | |Others = Reserved. + * |[10:8] |TMR10SEL |TIMER10 Clock Source Selection + * | | |000 = Clock source from 24 MHz external high speed crystal oscillator (HXT). + * | | |001 = Clock source from 32.768 kHz external low speed crystal oscillator (LXT). + * | | |010 = Clock source from PCLK2. + * | | |011 = Clock source from external clock TM10 pin. + * | | |101 = Clock source from 32 kHz internal low speed RC oscillator (LIRC). + * | | |111 = Clock source from 12 MHz internal high speed RC oscillator (HIRC). + * | | |Others = Reserved. + * |[14:12] |TMR11SEL |TIMER11 Clock Source Selection + * | | |000 = Clock source from 24 MHz external high speed crystal oscillator (HXT). + * | | |001 = Clock source from 32.768 kHz external low speed crystal oscillator (LXT). + * | | |010 = Clock source from PCLK2. + * | | |011 = Clock source from external clock TM11 pin. + * | | |101 = Clock source from 32 kHz internal low speed RC oscillator (LIRC). + * | | |111 = Clock source from 12 MHz internal high speed RC oscillator (HIRC). + * | | |Others = Reserved. + * |[17:16] |UART0SEL |UART0 Clock Source Selection + * | | |00 = Clock source from 24 MHz external high speed crystal oscillator (HXT). + * | | |01 = Clock source from SYSCLK1/2. + * | | |10 = Clock source from 32.768 kHz external low speed crystal oscillator (LXT). + * | | |11 = Clock source from 12 MHz internal high speed RC oscillator (HIRC). + * |[19:18] |UART1SEL |UART1 Clock Source Selection + * | | |00 = Clock source from 24 MHz external high speed crystal oscillator (HXT). + * | | |01 = Clock source from SYSCLK1/2. + * | | |10 = Clock source from 32.768 kHz external low speed crystal oscillator (LXT). + * | | |11 = Clock source from 12 MHz internal high speed RC oscillator (HIRC). + * |[21:20] |UART2SEL |UART2 Clock Source Selection + * | | |00 = Clock source from 24 MHz external high speed crystal oscillator (HXT). + * | | |01 = Clock source from SYSCLK1/2. + * | | |10 = Clock source from 32.768 kHz external low speed crystal oscillator (LXT). + * | | |11 = Clock source from 12 MHz internal high speed RC oscillator (HIRC). + * |[23:22] |UART3SEL |UART3 Clock Source Selection + * | | |00 = Clock source from 24 MHz external high speed crystal oscillator (HXT). + * | | |01 = Clock source from SYSCLK1/2. + * | | |10 = Clock source from 32.768 kHz external low speed crystal oscillator (LXT). + * | | |11 = Clock source from 12 MHz internal high speed RC oscillator (HIRC). + * |[25:24] |UART4SEL |UART4 Clock Source Selection + * | | |00 = Clock source from 24 MHz external high speed crystal oscillator (HXT). + * | | |01 = Clock source from SYSCLK1/2. + * | | |10 = Clock source from 32.768 kHz external low speed crystal oscillator (LXT). + * | | |11 = Clock source from 12 MHz internal high speed RC oscillator (HIRC). + * |[27:26] |UART5SEL |UART5 Clock Source Selection + * | | |00 = Clock source from 24 MHz external high speed crystal oscillator (HXT). + * | | |01 = Clock source from SYSCLK1/2. + * | | |10 = Clock source from 32.768 kHz external low speed crystal oscillator (LXT). + * | | |11 = Clock source from 12 MHz internal high speed RC oscillator (HIRC). + * |[29:28] |UART6SEL |UART6 Clock Source Selection + * | | |00 = Clock source from 24 MHz external high speed crystal oscillator (HXT). + * | | |01 = Clock source from SYSCLK1/2. + * | | |10 = Clock source from 32.768 kHz external low speed crystal oscillator (LXT). + * | | |11 = Clock source from 12 MHz internal high speed RC oscillator (HIRC). + * |[31:30] |UART7SEL |UART7 Clock Source Selection + * | | |00 = Clock source from 24 MHz external high speed crystal oscillator (HXT). + * | | |01 = Clock source from SYSCLK1/2. + * | | |10 = Clock source from 32.768 kHz external low speed crystal oscillator (LXT). + * | | |11 = Clock source from 12 MHz internal high speed RC oscillator (HIRC). + * @var CLK_T::CLKSEL3 + * Offset: 0x24 Clock Source Select Control Register 3 + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[1:0] |UART8SEL |UART8 Clock Source Selection + * | | |00 = Clock source from 24 MHz external high speed crystal oscillator (HXT). + * | | |01 = Clock source from SYSCLK1/2. + * | | |10 = Clock source from 32.768 kHz external low speed crystal oscillator (LXT). + * | | |11 = Clock source from 12 MHz internal high speed RC oscillator (HIRC). + * |[3:2] |UART9SEL |UART6 Clock Source Selection + * | | |00 = Clock source from 24 MHz external high speed crystal oscillator (HXT). + * | | |01 = Clock source from SYSCLK1/2. + * | | |10 = Clock source from 32.768 kHz external low speed crystal oscillator (LXT). + * | | |11 = Clock source from 12 MHz internal high speed RC oscillator (HIRC). + * |[5:4] |UART10SEL |UART10 Clock Source Selection + * | | |00 = Clock source from 24 MHz external high speed crystal oscillator (HXT). + * | | |01 = Clock source from SYSCLK1/2. + * | | |10 = Clock source from 32.768 kHz external low speed crystal oscillator (LXT). + * | | |11 = Clock source from 12 MHz internal high speed RC oscillator (HIRC). + * |[7:6] |UART11SEL |UART11 Clock Source Selection + * | | |00 = Clock source from 24 MHz external high speed crystal oscillator (HXT). + * | | |01 = Clock source from SYSCLK1/2. + * | | |10 = Clock source from 32.768 kHz external low speed crystal oscillator (LXT). + * | | |11 = Clock source from 12 MHz internal high speed RC oscillator (HIRC). + * |[9:8] |UART12SEL |UART12 Clock Source Selection + * | | |00 = Clock source from 24 MHz external high speed crystal oscillator (HXT). + * | | |01 = Clock source from SYSCLK1/2. + * | | |10 = Clock source from 32.768 kHz external low speed crystal oscillator (LXT). + * | | |11 = Clock source from 12 MHz internal high speed RC oscillator (HIRC). + * |[11:10] |UART13SEL |UART13 Clock Source Selection + * | | |00 = Clock source from 24 MHz external high speed crystal oscillator (HXT). + * | | |01 = Clock source from SYSCLK1/2. + * | | |10 = Clock source from 32.768 kHz external low speed crystal oscillator (LXT). + * | | |11 = Clock source from 12 MHz internal high speed RC oscillator (HIRC). + * |[13:12] |UART14SEL |UART14 Clock Source Selection + * | | |00 = Clock source from 24 MHz external high speed crystal oscillator (HXT). + * | | |01 = Clock source from SYSCLK1/2. + * | | |10 = Clock source from 32.768 kHz external low speed crystal oscillator (LXT). + * | | |11 = Clock source from 12 MHz internal high speed RC oscillator (HIRC). + * |[15:14] |UART15SEL |UART15 Clock Source Selection + * | | |00 = Clock source from 24 MHz external high speed crystal oscillator (HXT). + * | | |01 = Clock source from SYSCLK1/2. + * | | |10 = Clock source from 32.768 kHz external low speed crystal oscillator (LXT). + * | | |11 = Clock source from 12 MHz internal high speed RC oscillator (HIRC). + * |[17:16] |UART16SEL |UART16 Clock Source Selection + * | | |00 = Clock source from 24 MHz external high speed crystal oscillator (HXT). + * | | |01 = Clock source from SYSCLK1/2. + * | | |10 = Clock source from 32.768 kHz external low speed crystal oscillator (LXT). + * | | |11 = Clock source from 12 MHz internal high speed RC oscillator (HIRC). + * |[21:20] |WDT0SEL |Watchdog Timer Clock Source Selection (Write Protect) + * | | |01 = Clock source from 32.768 kHz external low speed crystal oscillator (LXT). + * | | |10 = Clock source from PCLK3/4096. + * | | |11 = Clock source from 32 kHz internal low speed RC oscillator (LIRC). + * | | |Others = Reserved. + * | | |Note: These bits are write protected. Refer to the SYS_RLKTZS register. + * |[23:22] |WWDT0SEL |Window Watchdog Timer Clock Source Selection (Write Protect) + * | | |10 = Clock source from PCLK3/4096. + * | | |11 = Clock source from 32 kHz internal low speed RC oscillator (LIRC). + * | | |Others = Reserved. + * | | |Note: These bits are write protected. Refer to the SYS_RLKTZS register. + * |[25:24] |WDT1SEL |Watchdog Timer Clock Source Selection (Write Protect) + * | | |01 = Clock source from 32.768 kHz external low speed crystal oscillator (LXT). + * | | |10 = Clock source from PCLK3/4096. + * | | |11 = Clock source from 32 kHz internal low speed RC oscillator (LIRC). + * | | |Others = Reserved. + * | | |Note: These bits are write protected. Refer to the SYS_RLKTZNS register or SYS_RLKTZS register. + * |[27:26] |WWDT1SEL |Window Watchdog Timer Clock Source Selection (Write Protect) + * | | |10 = Clock source from PCLK3/4096. + * | | |11 = Clock source from 32 kHz internal low speed RC oscillator (LIRC). + * | | |Others = Reserved. + * | | |Note: These bits are write protected. Refer to the SYS_RLKTZNS register or SYS_RLKTZS register. + * |[29:28] |WDT2SEL |Watchdog Timer Clock Source Selection (Write Protect, SUBM) + * | | |01 = Clock source from 32.768 kHz external low speed crystal oscillator (LXT). + * | | |10 = Clock source from PCLK4/4096. + * | | |11 = Clock source from 32 kHz internal low speed RC oscillator (LIRC). + * | | |Others = Reserved. + * | | |Note: These bits are write protected. Refer to the SYS_RLKTZNS register. + * |[31:30] |WWDT2SEL |Window Watchdog Timer Clock Source Selection (Write Protect, SUBM) + * | | |10 = Clock source from PCLK4/4096. + * | | |11 = Clock source from 32 kHz internal low speed RC oscillator (LIRC). + * | | |Others = Reserved. + * | | |Note: These bits are write protected. Refer to the SYS_RLKTZNS register. + * @var CLK_T::CLKSEL4 + * Offset: 0x28 Clock Source Select Control Register 4 + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[1:0] |SPI0SEL |SPI3 Clock Source Selection + * | | |00 = Clock source from 24 MHz external high speed crystal oscillator (HXT). + * | | |01 = Clock source from EPLL/4. + * | | |10 = Clock source from PCLK1. + * | | |11 = Clock source from 12 MHz internal high speed RC oscillator (HIRC). + * |[3:2] |SPI1SEL |SPI1 Clock Source Selection + * | | |00 = Clock source from 24 MHz external high speed crystal oscillator (HXT). + * | | |01 = Clock source from EPLL/4. + * | | |10 = Clock source from PCLK2. + * | | |11 = Clock source from 12 MHz internal high speed RC oscillator (HIRC). + * |[5:4] |SPI2SEL |SPI2 Clock Source Selection + * | | |00 = Clock source from 24 MHz external high speed crystal oscillator (HXT). + * | | |01 = Clock source from EPLL/4. + * | | |10 = Clock source from PCLK1. + * | | |11 = Clock source from 12 MHz internal high speed RC oscillator (HIRC). + * |[7:6] |SPI3SEL |SPI3 Clock Source Selection + * | | |00 = Clock source from 24 MHz external high speed crystal oscillator (HXT). + * | | |01 = Clock source from EPLL/4. + * | | |10 = Clock source from PCLK2. + * | | |11 = Clock source from 12 MHz internal high speed RC oscillator (HIRC). + * |[9:8] |QSPI0SEL |QSPI0 Clock Source Selection + * | | |00 = Clock source from 24 MHz external high speed crystal oscillator (HXT). + * | | |01 = Clock source from EPLL/4. + * | | |10 = Clock source from PCLK0. + * | | |11 = Clock source from 12 MHz internal high speed RC oscillator (HIRC). + * |[11:10] |QSPI1SEL |QSPI1 Clock Source Selection + * | | |00 = Clock source from 24 MHz external high speed crystal oscillator (HXT). + * | | |01 = Clock source from EPLL/4. + * | | |10 = Clock source from PCLK0. + * | | |11 = Clock source from 12 MHz internal high speed RC oscillator (HIRC). + * |[13:12] |I2S0SEL |I2S0 Clock Source Selection + * | | |00 = Clock source from HXT clock. + * | | |01 = Clock source from APLL clock. + * | | |10 = Clock source from PCLK0. + * | | |11 = Clock source from HIRC clock. + * |[15:14] |I2S1SEL |I2S1 Clock Source Selection + * | | |00 = Clock source from HXT clock. + * | | |01 = Clock source from APLL clock. + * | | |10 = Clock source from PCLK2. + * | | |11 = Clock source from HIRC clock. + * |[16] |CANFD0SEL |CANFD0 Clock Source Selection + * | | |0 = Clock source from APLL clock. + * | | |1 = Clock source from VPLL clock. + * |[17] |CANFD1SEL |CANFD1 Clock Source Selection + * | | |0 = Clock source from APLL clock. + * | | |1 = Clock source from VPLL clock. + * |[18] |CANFD2SEL |CANFD2 Clock Source Selection + * | | |0 = Clock source from APLL clock. + * | | |1 = Clock source from VPLL clock. + * |[19] |CANFD3SEL |CANFD3 Clock Source Selection + * | | |0 = Clock source from APLL clock. + * | | |1 = Clock source from VPLL clock. + * |[27:24] |CKOSEL |Reference Clock Our Source Selection + * | | |This field selects which clock is used to be the source of reference clock output + * | | |0000 = Clock source from HXT. + * | | |0001 = Clock source from LXT. + * | | |0010 = Clock source from HIRC. + * | | |0011 = Clock source from LIRC. + * | | |0100 = Reserved.. + * | | |0101 = Clock source from SYS-PLL. + * | | |0110 = Clock source from DDR core CLK. + * | | |0111 = Clock source from EPLL/4. + * | | |1000 = Clock source from APLL. + * | | |1001 = Clock source from VPLL. + * | | |1010 = Clock source from CA CLK. + * | | |1011 = Clock source from AXI0 ACLK. + * | | |1100 = Clock source from SYSCLK0. + * | | |1101 = Clock source from SYSCLK1. + * | | |1110 = Clock source from PCLK3. + * | | |1111 = Clock source from PCLK4. + * | | |Others = Reserved. + * |[28] |SC0SEL |Smart Card 0 Clock Source Selection + * | | |0 = Clock source from 4~24 MHz external high speed crystal oscillator (HXT). + * | | |1 = Clock source from PCLK4. + * |[29] |SC1SEL |Smart Card 1 Clock Source Selection + * | | |0 = Clock source from 4~24 MHz external high speed crystal oscillator (HXT). + * | | |1 = Clock source from PCLK4. + * |[30] |KPISEL |Key Pad Interface Clock Source Selection + * | | |0 = Clock source from 4~24 MHz external high speed crystal oscillator (HXT). + * | | |1 = Clock source from 32.768 kHz external low speed crystal oscillator (LXT). + * @var CLK_T::CLKDIV0 + * Offset: 0x2C Clock Divider Number Register 0 + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[1:0] |CANFD0DIV |CANFD0 Clock Divide Number From CANFD0 Clock Source + * | | |00 = Clock source from CANFD0 Clock Source /2. + * | | |01 = Clock source from CANFD0 Clock Source /4. + * | | |10 = Clock source from CANFD0 Clock Source /8. + * | | |11 = Clock source from CANFD0 Clock Source /16. + * |[3:2] |CANFD1DIV |CANFD1 Clock Divide Number From CANFD1 Clock Source + * | | |00 = Clock source from CANFD1 Clock Source /2. + * | | |01 = Clock source from CANFD1 Clock Source /4. + * | | |10 = Clock source from CANFD1 Clock Source /8. + * | | |11 = Clock source from CANFD1 Clock Source /16. + * |[5:4] |CANFD2DIV |CANFD2 Clock Divide Number From CANFD2 Clock Source + * | | |00 = Clock source from CANFD2 Clock Source /2. + * | | |01 = Clock source from CANFD2 Clock Source /4. + * | | |10 = Clock source from CANFD2 Clock Source /8. + * | | |11 = Clock source from CANFD2 Clock Source /16. + * |[7:6] |CANFD3DIV |CANFD3 Clock Divide Number From CANFD3 Clock Source + * | | |00 = Clock source from CANFD3 Clock Source /2. + * | | |01 = Clock source from CANFD3 Clock Source /4. + * | | |10 = Clock source from CANFD3 Clock Source /8. + * | | |11 = Clock source from CANFD3 Clock Source /16. + * |[25:24] |DCUPDIV |Display Controller Ultra Pixel Divided Clock Source (Read Only) + * | | |00 = Clock source from Display Controller Ultra Pixel Clock Source /2. + * | | |01 = Clock source from Display Controller Ultra Pixel Clock Source /4. + * | | |10 = Clock source from Display Controller Ultra Pixel Clock Source /8. + * | | |11 = Clock source from Display Controller Ultra Pixel Clock Source /16. + * |[26] |ACLK0DIV |AXI0 Bus Clock Divide Number From CA-PLL Clock Source (Write Protect) + * | | |0 = Clock source from CA-PLL /2. + * | | |1 = Clock source from CA-PLL /4. + * | | |Note: This bit is write protected. Refer to the SYS_RLKTZS register. + * |[29:28] |EMAC0DIV |EMAC0 TX Clock Divide Selection From EPLL Clock Source (Read Only) + * | | |00 = Clock source from EPLL /2.(RGMII). + * | | |01 = Clock source from EPLL /2.(RGMII). + * | | |10 = Clock source from EPLL /100 (RGMII). + * | | |11 = Clock source from EPLL /10 (RGMII). + * | | |X0 = Clock source from RMII reference clock /20 (RMII). + * | | |X1 = Clock source from RMII reference clock /2 (RMII). + * | | |Others = Reserved. + * | | |Note: This field definition depends on the Ethernet mac is RMII or not. + * |[31:30] |EMAC1DIV |EMAC1 TX Clock Divide Selection From EPLL Clock Source (Read Only) + * | | |00 = Clock source from EPLL /2.(RGMII). + * | | |01 = Clock source from EPLL /2.(RGMII). + * | | |10 = Clock source from EPLL /100 (RGMII). + * | | |11 = Clock source from EPLL /10 (RGMII). + * | | |X0 = Clock source from RMII reference clock /20 (RMII). + * | | |X1 = Clock source from RMII reference clock /2 (RMII). + * | | |Others = Reserved. + * | | |Note: This field definition depends on the Ethernet mac is RMII or not. + * @var CLK_T::CLKDIV1 + * Offset: 0x30 Clock Divider Number Register 1 + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[3:0] |SC0DIV |Smart Card 0 Clock Divide Number From SC0 Clock Source + * | | |SC0 clock frequency = (SC0 clock source frequency) / (SC0DIV + 1). + * |[7:4] |SC1DIV |Smart Card 1 Clock Divide Number From SC1 Clock Source + * | | |SC1 clock frequency = (SC1 clock source frequency) / (SC1DIV + 1). + * |[11:8] |CCAP0DIV |CCAP0 Clock Divide Number From CCAP0 Clock Source (TZNS) + * | | |CCAP0 clock frequency = (CCAP0 clock source frequency) / (CCAP0DIV + 1). + * |[15:12] |CCAP1DIV |CCAP1 Clock Divide Number From CCAP1 Clock Source (TZNS) + * | | |CCAP1 clock frequency = (CCAP1 clock source frequency) / (CCAP1DIV + 1). + * |[19:16] |UART0DIV |UART0 Clock Divide Number From UART0 Clock Source + * | | |UART0 clock frequency = (UART0 clock source frequency) / (UART0DIV + 1). + * |[23:20] |UART1DIV |UART1 Clock Divide Number From UART1 Clock Source + * | | |UART1 clock frequency = (UART1 clock source frequency) / (UART1DIV + 1). + * |[27:24] |UART2DIV |UART2 Clock Divide Number From UART2 Clock Source + * | | |UART2 clock frequency = (UART2 clock source frequency) / (UART2DIV + 1). + * |[31:28] |UART3DIV |UART3 Clock Divide Number From UART3 Clock Source + * | | |UART3 clock frequency = (UART3 clock source frequency) / (UART3DIV + 1). + * @var CLK_T::CLKDIV2 + * Offset: 0x34 Clock Divider Number Register 2 + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[3:0] |UART4DIV |UART4 Clock Divide Number From UART4 Clock Source + * | | |UART4 clock frequency = (UART4 clock source frequency) / (UART4DIV + 1). + * |[7:4] |UART5DIV |UART5 Clock Divide Number From UART5 Clock Source + * | | |UART5 clock frequency = (UART5 clock source frequency) / (UART5DIV + 1). + * |[11:8] |UART6DIV |UART6 Clock Divide Number From UART6 Clock Source + * | | |UART6 clock frequency = (UART6 clock source frequency) / (UART6DIV + 1). + * |[15:12] |UART7DIV |UART7 Clock Divide Number From UART7 Clock Source + * | | |UART7 clock frequency = (UART7 clock source frequency) / (UART7DIV + 1). + * |[19:16] |UART8DIV |UART8 Clock Divide Number From UART8 Clock Source + * | | |UART8 clock frequency = (UART8 clock source frequency) / (UART8DIV + 1). + * |[23:20] |UART9DIV |UART9 Clock Divide Number From UART9 Clock Source + * | | |UART9 clock frequency = (UART9 clock source frequency) / (UART9DIV + 1). + * |[27:24] |UART10DIV |UART10 Clock Divide Number From UART10 Clock Source + * | | |UART10 clock frequency = (UART10 clock source frequency) / (UART10DIV + 1). + * |[31:28] |UART11DIV |UART11 Clock Divide Number From UART11 Clock Source + * | | |UART11 clock frequency = (UART11 clock source frequency) / (UART11DIV + 1). + * @var CLK_T::CLKDIV3 + * Offset: 0x38 Clock Divider Number Register 3 + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[3:0] |UART12DIV |UART12 Clock Divide Number From UART12 Clock Source + * | | |UART12 clock frequency = (UART12 clock source frequency) / (UART12DIV + 1). + * |[7:4] |UART13DIV |UART13 Clock Divide Number From UART13 Clock Source + * | | |UART13 clock frequency = (UART13 clock source frequency) / (UART13DIV + 1). + * |[11:8] |UART14DIV |UART14 Clock Divide Number From UART14 Clock Source + * | | |UART14 clock frequency = (UART14 clock source frequency) / (UART14DIV + 1). + * |[15:12] |UART15DIV |UART15 Clock Divide Number From UART15 Clock Source + * | | |UART15 clock frequency = (UART15 clock source frequency) / (UART15DIV + 1). + * |[19:16] |UART16DIV |UART16 Clock Divide Number From UART16 Clock Source + * | | |UART16 clock frequency = (UART16 clock source frequency) / (UART16DIV + 1). + * @var CLK_T::CLKDIV4 + * Offset: 0x3C Clock Divider Number Register 4 + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[3:0] |EADCDIV |EADC Clock Divide Number From EADC Clock Source + * | | |EADC clock frequency = (EADC clock source frequency) / (EADCDIV + 1). + * |[20:4] |ADCDIV |ADC Clock Divide Number From ADC Clock Source + * | | |ADC clock frequency = (ADC clock source frequency) / (ADCDIV + 1). + * |[31:24] |KPIDIV |Keypad Interface Clock Divide Number From KPI Clock Source + * | | |KPI clock frequency = (KPI clock source frequency) / (KPIDIV + 1). + * @var CLK_T::CLKOCTL + * Offset: 0x40 Clock Output Control Register (Write Protect) + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[3:0] |FREQSEL |Clock Output Frequency Selection + * | | |The formula of output frequency is + * | | |Fout = Fin/2(N+1). + * | | |Fin is the input clock frequency. + * | | |Fout is the frequency of divider output clock. + * | | |N is the 4-bit value of FREQSEL [3:0]. + * |[4] |CLKOEN |Clock Output Enable Bit + * | | |0 = Clock Output function Disabled. + * | | |1 = Clock Output function Enabled. + * |[5] |DIV1EN |Clock Output Divide One Enable Bit + * | | |0 = Clock Output will output clock with source frequency divided by FREQSEL. + * | | |1 = Clock Output will output clock with source frequency. + * @var CLK_T::STATUS + * Offset: 0x50 Clock Status Monitor Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[0] |HXTSTB |HXT Clock Source Stable Flag (Read Only) + * | | |0 = 24 MHz external high speed crystal oscillator (HXT) clock is not stable or disabled. + * | | |1 = 24 MHz external high speed crystal oscillator (HXT) clock is stable and enabled. + * |[1] |LXTSTB |LXT Clock Source Stable Flag (Read Only) + * | | |LXT clock source can be selected as external LXT or LIRC32 by setting C32KS(RTC_LXTCTL[6]) + * | | |IfC32KS is set to 0 the LXT stable flag is set when external LXT clock source is stable + * | | |IfC32KS is set to 1 the LXT stable flag is set when LIRC32 clock source is stable. + * | | |0 = 32.768 kHz external low speed crystal oscillator (LXT) clock is not stable or disabled. + * | | |1 = 32.768 kHz external low speed crystal oscillator (LXT) clock is stabled and enabled. + * |[2] |SYSPLLSTB |SYS-PLL Clock Source Stable Flag (Read Only) + * | | |0 = SYS-PLL clock is not stable or disabled. + * | | |1 = SYS-PLL clock is stable and enabled. + * |[3] |LIRCSTB |LIRC Clock Source Stable Flag (Read Only) + * | | |0 = 32 kHz internal low speed RC oscillator (LIRC) clock is not stable or disabled. + * | | |1 = 32 kHz internal low speed RC oscillator (LIRC) clock is stable and enabled. + * |[4] |HIRCSTB |HIRC Clock Source Stable Flag (Read Only) + * | | |0 = 12 MHz internal high speed RC oscillator (HIRC) clock is not stable or disabled. + * | | |1 = 12 MHz internal high speed RC oscillator (HIRC) clock is stable and enabled. + * |[6] |CAPLLSTB |Cortex35 PLL Clock Source Stable Flag (Read Only) + * | | |0 = CA-PLL clock is not stable or disabled. + * | | |1 = CA-PLL clock is stable and enabled. + * |[8] |DDRPLLSTB |DDR-PLL Clock Source Stable Flag (Read Only) + * | | |0 = DDR-PLL clock is not stable or disabled. + * | | |1 = DDR-PLL clock is stable and enabled. + * |[9] |EPLLSTB |EPLL Clock Source Stable Flag (Read Only) + * | | |0 = EPLL clock is not stable or disabled. + * | | |1 = EPLL clock is stable and enabled. + * |[10] |APLLSTB |APLL Clock Source Stable Flag (Read Only) + * | | |0 = APLL clock is not stable or disabled. + * | | |1 = APLL clock is stable and enabled. + * |[11] |VPLLSTB |VPLL Clock Source Stable Flag (Read Only) + * | | |0 = VPLL clock is not stable or disabled. + * | | |1 = VPLL clock is stable and enabled. + * @var CLK_T::PLL0CTL0 + * Offset: 0x60 CA-PLL Control Register 0(Write Protect) + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[10:0] |FBDIV |PLL Feedback Divider Control (Write Protect) + * | | |Set the feedback divider factor (N) from 16 to 2047. + * | | |The N = FBDIV[10:0]. + * | | |Note: This bit is write protected + * | | |Refer to the SYS_RLKTZS register + * | | |For PLL3, PLL4, and PLL5, user can also refer to the SYS_RLKTZNS register if SYSSIAEN is 1. + * |[17:12] |INDIV |PLL Reference Input Divider Control (Write Protect) + * | | |Set the reference divider factor (M) from 1 to 63. + * | | |The M = INDIV[5:0]. + * | | |Note: This bit is write protected + * | | |Refer to the SYS_RLKTZS register + * | | |For PLL3, PLL4, and PLL5, user can also refer to the SYS_RLKTZNS register if SYSSIAEN is 1. + * |[19:18] |MODE |Operation Mode Selection(Write Protect) + * | | |00 = Integer mode. + * | | |In this mode, the rising edges of the two clocks at the input of PFD are phase aligned + * | | |And the output clock frequency is at multiples of the input clock frequency contingent on the configuration of OUTDIV, INDIV and FBDIV. + * | | |01 = Fractional mode. + * | | |This mode is suitable for applications which need small output frequency steps, like 20 kHz + * | | |The jitter performance in this mode may be worse than in Integer Mode. + * | | |In this mode, the output clock frequency is at the fractional multiples of the input clock frequency + * | | |By setting the control pins FRAC [23:0], a small output frequency step is achieved.. + * | | |10 = Spread Spectrum Mode. + * | | |This mode is suitable for In this mode the output frequency of PLL will be modulated by triangle wave + * | | |It is for EMI consideration. + * | | |By setting SSRATE [10:0] and SLOPE [23:0], the modulation index and the modulation frequency can be programmed. + * | | |Note: This bit is write protected + * | | |Refer to the SYS_RLKTZS register + * | | |For PLL3, PLL4, and PLL5, user can also refer to the SYS_RLKTZNS register if SYSSIAEN is 1. + * |[30:20] |SSRATE |Spreading Frequency Control (Write Protect) + * | | |Set the spread step factor SSRATE from 0 to 2047, + * | | |SSRATE = SSRATE [10:0]. + * | | |Note: This bit is write protected + * | | |Refer to the SYS_RLKTZS register + * | | |For PLL3, PLL4, and PLL5, user can also refer to the SYS_RLKTZNS register if SYSSIAEN is 1. + * @var CLK_T::PLL0CTL1 + * Offset: 0x64 CA-PLL Control Register 1(Write Protect) + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[0] |PD |Power-down Mode (Write Protect) + * | | |0 = PLL is enable (in normal mode). + * | | |1 = PLL is disable (in Power-down mode) (default). + * | | |Note: This bit is write protected + * | | |Refer to the SYS_RLKTZS register + * | | |For PLL3, PLL4, and PLL5, user can also refer to the SYS_RLKTZNS register if SYSSIAEN is 1. + * |[1] |BP |PLL Bypass Control (Write Protect) + * | | |0 = PLL is in normal mode (default). + * | | |1 = PLL clock output is same as PLL input clock Fref. + * | | |Note: This bit is write protected + * | | |Refer to the SYS_RLKTZS register + * | | |For PLL3, PLL4, and PLL5, user can also refer to the SYS_RLKTZNS register if SYSSIAEN is 1. + * |[6:4] |OUTDIV |PLL Output Divider Control (Write Protect) + * | | |Set the output divider factor (P) from 1 to 7. + * | | |P = OUTDIV[2:0]. + * | | |Note: This bit is write protected + * | | |Refer to the SYS_RLKTZS register + * | | |For PLL3, PLL4, and PLL5, user can also refer to the SYS_RLKTZNS register if SYSSIAEN is 1. + * |[31:8] |FRAC |PLL Fractional Portion of DN Value (Write Protect) + * | | |Set the fraction part (X) of Fractional Portion of DN Value factor. + * | | |The X = FRAC[23:0] / 224. + * | | |Note: This bit is write protected + * | | |Refer to the SYS_RLKTZS register + * | | |For PLL3, PLL4, and PLL5, user can also refer to the SYS_RLKTZNS register if SYSSIAEN is 1. + * @var CLK_T::PLL0CTL2 + * Offset: 0x68 CA-PLL Control Register 2(Write Protect) + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[23:0] |SLOPE |PLL Stable Counter Selection (Write Protect) + * | | |Set the spread step factor SLOPE from 0 to 16777215, + * | | |SLOPE = SLOPE[23:0]. + * | | |Note 1: This bit is write protected + * | | |Refer to the SYS_RLKTZS register + * | | |For PLL3, PLL4, and PLL5, user can also refer to the SYS_RLKTZNS register if SYSSIAEN is 1. + * @var CLK_T::PLL1CTL0 + * Offset: 0x70 SYS-PLL Control Register 0(Write Protect) + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[10:0] |FBDIV |PLL Feedback Divider Control (Write Protect) + * | | |Set the feedback divider factor (N) from 16 to 2047. + * | | |The N = FBDIV[10:0]. + * | | |Note: This bit is write protected + * | | |Refer to the SYS_RLKTZS register + * | | |For PLL3, PLL4, and PLL5, user can also refer to the SYS_RLKTZNS register if SYSSIAEN is 1. + * |[17:12] |INDIV |PLL Reference Input Divider Control (Write Protect) + * | | |Set the reference divider factor (M) from 1 to 63. + * | | |The M = INDIV[5:0]. + * | | |Note: This bit is write protected + * | | |Refer to the SYS_RLKTZS register + * | | |For PLL3, PLL4, and PLL5, user can also refer to the SYS_RLKTZNS register if SYSSIAEN is 1. + * |[19:18] |MODE |Operation Mode Selection(Write Protect) + * | | |00 = Integer mode. + * | | |In this mode, the rising edges of the two clocks at the input of PFD are phase aligned + * | | |And the output clock frequency is at multiples of the input clock frequency contingent on the configuration of OUTDIV, INDIV and FBDIV. + * | | |01 = Fractional mode. + * | | |This mode is suitable for applications which need small output frequency steps, like 20 kHz + * | | |The jitter performance in this mode may be worse than in Integer Mode. + * | | |In this mode, the output clock frequency is at the fractional multiples of the input clock frequency + * | | |By setting the control pins FRAC [23:0], a small output frequency step is achieved.. + * | | |10 = Spread Spectrum Mode. + * | | |This mode is suitable for In this mode the output frequency of PLL will be modulated by triangle wave + * | | |It is for EMI consideration. + * | | |By setting SSRATE [10:0] and SLOPE [23:0], the modulation index and the modulation frequency can be programmed. + * | | |Note: This bit is write protected + * | | |Refer to the SYS_RLKTZS register + * | | |For PLL3, PLL4, and PLL5, user can also refer to the SYS_RLKTZNS register if SYSSIAEN is 1. + * |[30:20] |SSRATE |Spreading Frequency Control (Write Protect) + * | | |Set the spread step factor SSRATE from 0 to 2047, + * | | |SSRATE = SSRATE [10:0]. + * | | |Note: This bit is write protected + * | | |Refer to the SYS_RLKTZS register + * | | |For PLL3, PLL4, and PLL5, user can also refer to the SYS_RLKTZNS register if SYSSIAEN is 1. + * @var CLK_T::PLL1CTL1 + * Offset: 0x74 SYS-PLL Control Register 1(Write Protect) + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[0] |PD |Power-down Mode (Write Protect) + * | | |0 = PLL is enable (in normal mode). + * | | |1 = PLL is disable (in Power-down mode) (default). + * | | |Note: This bit is write protected + * | | |Refer to the SYS_RLKTZS register + * | | |For PLL3, PLL4, and PLL5, user can also refer to the SYS_RLKTZNS register if SYSSIAEN is 1. + * |[1] |BP |PLL Bypass Control (Write Protect) + * | | |0 = PLL is in normal mode (default). + * | | |1 = PLL clock output is same as PLL input clock Fref. + * | | |Note: This bit is write protected + * | | |Refer to the SYS_RLKTZS register + * | | |For PLL3, PLL4, and PLL5, user can also refer to the SYS_RLKTZNS register if SYSSIAEN is 1. + * |[6:4] |OUTDIV |PLL Output Divider Control (Write Protect) + * | | |Set the output divider factor (P) from 1 to 7. + * | | |P = OUTDIV[2:0]. + * | | |Note: This bit is write protected + * | | |Refer to the SYS_RLKTZS register + * | | |For PLL3, PLL4, and PLL5, user can also refer to the SYS_RLKTZNS register if SYSSIAEN is 1. + * |[31:8] |FRAC |PLL Fractional Portion of DN Value (Write Protect) + * | | |Set the fraction part (X) of Fractional Portion of DN Value factor. + * | | |The X = FRAC[23:0] / 224. + * | | |Note: This bit is write protected + * | | |Refer to the SYS_RLKTZS register + * | | |For PLL3, PLL4, and PLL5, user can also refer to the SYS_RLKTZNS register if SYSSIAEN is 1. + * @var CLK_T::PLL1CTL2 + * Offset: 0x78 SYS-PLL Control Register 2(Write Protect) + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[23:0] |SLOPE |PLL Stable Counter Selection (Write Protect) + * | | |Set the spread step factor SLOPE from 0 to 16777215, + * | | |SLOPE = SLOPE[23:0]. + * | | |Note 1: This bit is write protected + * | | |Refer to the SYS_RLKTZS register + * | | |For PLL3, PLL4, and PLL5, user can also refer to the SYS_RLKTZNS register if SYSSIAEN is 1. + * @var CLK_T::PLL2CTL0 + * Offset: 0x80 DDR-PLL Control Register 0(Write Protect) + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[10:0] |FBDIV |PLL Feedback Divider Control (Write Protect) + * | | |Set the feedback divider factor (N) from 16 to 2047. + * | | |The N = FBDIV[10:0]. + * | | |Note: This bit is write protected + * | | |Refer to the SYS_RLKTZS register + * | | |For PLL3, PLL4, and PLL5, user can also refer to the SYS_RLKTZNS register if SYSSIAEN is 1. + * |[17:12] |INDIV |PLL Reference Input Divider Control (Write Protect) + * | | |Set the reference divider factor (M) from 1 to 63. + * | | |The M = INDIV[5:0]. + * | | |Note: This bit is write protected + * | | |Refer to the SYS_RLKTZS register + * | | |For PLL3, PLL4, and PLL5, user can also refer to the SYS_RLKTZNS register if SYSSIAEN is 1. + * |[19:18] |MODE |Operation Mode Selection(Write Protect) + * | | |00 = Integer mode. + * | | |In this mode, the rising edges of the two clocks at the input of PFD are phase aligned + * | | |And the output clock frequency is at multiples of the input clock frequency contingent on the configuration of OUTDIV, INDIV and FBDIV. + * | | |01 = Fractional mode. + * | | |This mode is suitable for applications which need small output frequency steps, like 20 kHz + * | | |The jitter performance in this mode may be worse than in Integer Mode. + * | | |In this mode, the output clock frequency is at the fractional multiples of the input clock frequency + * | | |By setting the control pins FRAC [23:0], a small output frequency step is achieved.. + * | | |10 = Spread Spectrum Mode. + * | | |This mode is suitable for In this mode the output frequency of PLL will be modulated by triangle wave + * | | |It is for EMI consideration. + * | | |By setting SSRATE [10:0] and SLOPE [23:0], the modulation index and the modulation frequency can be programmed. + * | | |Note: This bit is write protected + * | | |Refer to the SYS_RLKTZS register + * | | |For PLL3, PLL4, and PLL5, user can also refer to the SYS_RLKTZNS register if SYSSIAEN is 1. + * |[30:20] |SSRATE |Spreading Frequency Control (Write Protect) + * | | |Set the spread step factor SSRATE from 0 to 2047, + * | | |SSRATE = SSRATE [10:0]. + * | | |Note: This bit is write protected + * | | |Refer to the SYS_RLKTZS register + * | | |For PLL3, PLL4, and PLL5, user can also refer to the SYS_RLKTZNS register if SYSSIAEN is 1. + * @var CLK_T::PLL2CTL1 + * Offset: 0x84 DDR-PLL Control Register 1(Write Protect) + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[0] |PD |Power-down Mode (Write Protect) + * | | |0 = PLL is enable (in normal mode). + * | | |1 = PLL is disable (in Power-down mode) (default). + * | | |Note: This bit is write protected + * | | |Refer to the SYS_RLKTZS register + * | | |For PLL3, PLL4, and PLL5, user can also refer to the SYS_RLKTZNS register if SYSSIAEN is 1. + * |[1] |BP |PLL Bypass Control (Write Protect) + * | | |0 = PLL is in normal mode (default). + * | | |1 = PLL clock output is same as PLL input clock Fref. + * | | |Note: This bit is write protected + * | | |Refer to the SYS_RLKTZS register + * | | |For PLL3, PLL4, and PLL5, user can also refer to the SYS_RLKTZNS register if SYSSIAEN is 1. + * |[6:4] |OUTDIV |PLL Output Divider Control (Write Protect) + * | | |Set the output divider factor (P) from 1 to 7. + * | | |P = OUTDIV[2:0]. + * | | |Note: This bit is write protected + * | | |Refer to the SYS_RLKTZS register + * | | |For PLL3, PLL4, and PLL5, user can also refer to the SYS_RLKTZNS register if SYSSIAEN is 1. + * |[31:8] |FRAC |PLL Fractional Portion of DN Value (Write Protect) + * | | |Set the fraction part (X) of Fractional Portion of DN Value factor. + * | | |The X = FRAC[23:0] / 224. + * | | |Note: This bit is write protected + * | | |Refer to the SYS_RLKTZS register + * | | |For PLL3, PLL4, and PLL5, user can also refer to the SYS_RLKTZNS register if SYSSIAEN is 1. + * @var CLK_T::PLL2CTL2 + * Offset: 0x88 DDR-PLL Control Register 2(Write Protect) + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[23:0] |SLOPE |PLL Stable Counter Selection (Write Protect) + * | | |Set the spread step factor SLOPE from 0 to 16777215, + * | | |SLOPE = SLOPE[23:0]. + * | | |Note 1: This bit is write protected + * | | |Refer to the SYS_RLKTZS register + * | | |For PLL3, PLL4, and PLL5, user can also refer to the SYS_RLKTZNS register if SYSSIAEN is 1. + * @var CLK_T::PLL3CTL0 + * Offset: 0x90 APLL Control Register 0(Write Protect) + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[10:0] |FBDIV |PLL Feedback Divider Control (Write Protect) + * | | |Set the feedback divider factor (N) from 16 to 2047. + * | | |The N = FBDIV[10:0]. + * | | |Note: This bit is write protected + * | | |Refer to the SYS_RLKTZS register + * | | |For PLL3, PLL4, and PLL5, user can also refer to the SYS_RLKTZNS register if SYSSIAEN is 1. + * |[17:12] |INDIV |PLL Reference Input Divider Control (Write Protect) + * | | |Set the reference divider factor (M) from 1 to 63. + * | | |The M = INDIV[5:0]. + * | | |Note: This bit is write protected + * | | |Refer to the SYS_RLKTZS register + * | | |For PLL3, PLL4, and PLL5, user can also refer to the SYS_RLKTZNS register if SYSSIAEN is 1. + * |[19:18] |MODE |Operation Mode Selection(Write Protect) + * | | |00 = Integer mode. + * | | |In this mode, the rising edges of the two clocks at the input of PFD are phase aligned + * | | |And the output clock frequency is at multiples of the input clock frequency contingent on the configuration of OUTDIV, INDIV and FBDIV. + * | | |01 = Fractional mode. + * | | |This mode is suitable for applications which need small output frequency steps, like 20 kHz + * | | |The jitter performance in this mode may be worse than in Integer Mode. + * | | |In this mode, the output clock frequency is at the fractional multiples of the input clock frequency + * | | |By setting the control pins FRAC [23:0], a small output frequency step is achieved.. + * | | |10 = Spread Spectrum Mode. + * | | |This mode is suitable for In this mode the output frequency of PLL will be modulated by triangle wave + * | | |It is for EMI consideration. + * | | |By setting SSRATE [10:0] and SLOPE [23:0], the modulation index and the modulation frequency can be programmed. + * | | |Note: This bit is write protected + * | | |Refer to the SYS_RLKTZS register + * | | |For PLL3, PLL4, and PLL5, user can also refer to the SYS_RLKTZNS register if SYSSIAEN is 1. + * |[30:20] |SSRATE |Spreading Frequency Control (Write Protect) + * | | |Set the spread step factor SSRATE from 0 to 2047, + * | | |SSRATE = SSRATE [10:0]. + * | | |Note: This bit is write protected + * | | |Refer to the SYS_RLKTZS register + * | | |For PLL3, PLL4, and PLL5, user can also refer to the SYS_RLKTZNS register if SYSSIAEN is 1. + * @var CLK_T::PLL3CTL1 + * Offset: 0x94 APLL Control Register 1(Write Protect) + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[0] |PD |Power-down Mode (Write Protect) + * | | |0 = PLL is enable (in normal mode). + * | | |1 = PLL is disable (in Power-down mode) (default). + * | | |Note: This bit is write protected + * | | |Refer to the SYS_RLKTZS register + * | | |For PLL3, PLL4, and PLL5, user can also refer to the SYS_RLKTZNS register if SYSSIAEN is 1. + * |[1] |BP |PLL Bypass Control (Write Protect) + * | | |0 = PLL is in normal mode (default). + * | | |1 = PLL clock output is same as PLL input clock Fref. + * | | |Note: This bit is write protected + * | | |Refer to the SYS_RLKTZS register + * | | |For PLL3, PLL4, and PLL5, user can also refer to the SYS_RLKTZNS register if SYSSIAEN is 1. + * |[6:4] |OUTDIV |PLL Output Divider Control (Write Protect) + * | | |Set the output divider factor (P) from 1 to 7. + * | | |P = OUTDIV[2:0]. + * | | |Note: This bit is write protected + * | | |Refer to the SYS_RLKTZS register + * | | |For PLL3, PLL4, and PLL5, user can also refer to the SYS_RLKTZNS register if SYSSIAEN is 1. + * |[31:8] |FRAC |PLL Fractional Portion of DN Value (Write Protect) + * | | |Set the fraction part (X) of Fractional Portion of DN Value factor. + * | | |The X = FRAC[23:0] / 224. + * | | |Note: This bit is write protected + * | | |Refer to the SYS_RLKTZS register + * | | |For PLL3, PLL4, and PLL5, user can also refer to the SYS_RLKTZNS register if SYSSIAEN is 1. + * @var CLK_T::PLL3CTL2 + * Offset: 0x98 APLL Control Register 2(Write Protect) + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[23:0] |SLOPE |PLL Stable Counter Selection (Write Protect) + * | | |Set the spread step factor SLOPE from 0 to 16777215, + * | | |SLOPE = SLOPE[23:0]. + * | | |Note 1: This bit is write protected + * | | |Refer to the SYS_RLKTZS register + * | | |For PLL3, PLL4, and PLL5, user can also refer to the SYS_RLKTZNS register if SYSSIAEN is 1. + * @var CLK_T::PLL4CTL0 + * Offset: 0xA0 EPLL Control Register 0(Write Protect) + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[10:0] |FBDIV |PLL Feedback Divider Control (Write Protect) + * | | |Set the feedback divider factor (N) from 16 to 2047. + * | | |The N = FBDIV[10:0]. + * | | |Note: This bit is write protected + * | | |Refer to the SYS_RLKTZS register + * | | |For PLL3, PLL4, and PLL5, user can also refer to the SYS_RLKTZNS register if SYSSIAEN is 1. + * |[17:12] |INDIV |PLL Reference Input Divider Control (Write Protect) + * | | |Set the reference divider factor (M) from 1 to 63. + * | | |The M = INDIV[5:0]. + * | | |Note: This bit is write protected + * | | |Refer to the SYS_RLKTZS register + * | | |For PLL3, PLL4, and PLL5, user can also refer to the SYS_RLKTZNS register if SYSSIAEN is 1. + * |[19:18] |MODE |Operation Mode Selection(Write Protect) + * | | |00 = Integer mode. + * | | |In this mode, the rising edges of the two clocks at the input of PFD are phase aligned + * | | |And the output clock frequency is at multiples of the input clock frequency contingent on the configuration of OUTDIV, INDIV and FBDIV. + * | | |01 = Fractional mode. + * | | |This mode is suitable for applications which need small output frequency steps, like 20 kHz + * | | |The jitter performance in this mode may be worse than in Integer Mode. + * | | |In this mode, the output clock frequency is at the fractional multiples of the input clock frequency + * | | |By setting the control pins FRAC [23:0], a small output frequency step is achieved.. + * | | |10 = Spread Spectrum Mode. + * | | |This mode is suitable for In this mode the output frequency of PLL will be modulated by triangle wave + * | | |It is for EMI consideration. + * | | |By setting SSRATE [10:0] and SLOPE [23:0], the modulation index and the modulation frequency can be programmed. + * | | |Note: This bit is write protected + * | | |Refer to the SYS_RLKTZS register + * | | |For PLL3, PLL4, and PLL5, user can also refer to the SYS_RLKTZNS register if SYSSIAEN is 1. + * |[30:20] |SSRATE |Spreading Frequency Control (Write Protect) + * | | |Set the spread step factor SSRATE from 0 to 2047, + * | | |SSRATE = SSRATE [10:0]. + * | | |Note: This bit is write protected + * | | |Refer to the SYS_RLKTZS register + * | | |For PLL3, PLL4, and PLL5, user can also refer to the SYS_RLKTZNS register if SYSSIAEN is 1. + * @var CLK_T::PLL4CTL1 + * Offset: 0xA4 EPLL Control Register 1(Write Protect) + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[0] |PD |Power-down Mode (Write Protect) + * | | |0 = PLL is enable (in normal mode). + * | | |1 = PLL is disable (in Power-down mode) (default). + * | | |Note: This bit is write protected + * | | |Refer to the SYS_RLKTZS register + * | | |For PLL3, PLL4, and PLL5, user can also refer to the SYS_RLKTZNS register if SYSSIAEN is 1. + * |[1] |BP |PLL Bypass Control (Write Protect) + * | | |0 = PLL is in normal mode (default). + * | | |1 = PLL clock output is same as PLL input clock Fref. + * | | |Note: This bit is write protected + * | | |Refer to the SYS_RLKTZS register + * | | |For PLL3, PLL4, and PLL5, user can also refer to the SYS_RLKTZNS register if SYSSIAEN is 1. + * |[6:4] |OUTDIV |PLL Output Divider Control (Write Protect) + * | | |Set the output divider factor (P) from 1 to 7. + * | | |P = OUTDIV[2:0]. + * | | |Note: This bit is write protected + * | | |Refer to the SYS_RLKTZS register + * | | |For PLL3, PLL4, and PLL5, user can also refer to the SYS_RLKTZNS register if SYSSIAEN is 1. + * |[31:8] |FRAC |PLL Fractional Portion of DN Value (Write Protect) + * | | |Set the fraction part (X) of Fractional Portion of DN Value factor. + * | | |The X = FRAC[23:0] / 224. + * | | |Note: This bit is write protected + * | | |Refer to the SYS_RLKTZS register + * | | |For PLL3, PLL4, and PLL5, user can also refer to the SYS_RLKTZNS register if SYSSIAEN is 1. + * @var CLK_T::PLL4CTL2 + * Offset: 0xA8 EPLL Control Register 2(Write Protect) + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[23:0] |SLOPE |PLL Stable Counter Selection (Write Protect) + * | | |Set the spread step factor SLOPE from 0 to 16777215, + * | | |SLOPE = SLOPE[23:0]. + * | | |Note 1: This bit is write protected + * | | |Refer to the SYS_RLKTZS register + * | | |For PLL3, PLL4, and PLL5, user can also refer to the SYS_RLKTZNS register if SYSSIAEN is 1. + * @var CLK_T::PLL5CTL0 + * Offset: 0xB0 VPLL Control Register 0(Write Protect) + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[10:0] |FBDIV |PLL Feedback Divider Control (Write Protect) + * | | |Set the feedback divider factor (N) from 16 to 2047. + * | | |The N = FBDIV[10:0]. + * | | |Note: This bit is write protected + * | | |Refer to the SYS_RLKTZS register + * | | |For PLL3, PLL4, and PLL5, user can also refer to the SYS_RLKTZNS register if SYSSIAEN is 1. + * |[17:12] |INDIV |PLL Reference Input Divider Control (Write Protect) + * | | |Set the reference divider factor (M) from 1 to 63. + * | | |The M = INDIV[5:0]. + * | | |Note: This bit is write protected + * | | |Refer to the SYS_RLKTZS register + * | | |For PLL3, PLL4, and PLL5, user can also refer to the SYS_RLKTZNS register if SYSSIAEN is 1. + * |[19:18] |MODE |Operation Mode Selection(Write Protect) + * | | |00 = Integer mode. + * | | |In this mode, the rising edges of the two clocks at the input of PFD are phase aligned + * | | |And the output clock frequency is at multiples of the input clock frequency contingent on the configuration of OUTDIV, INDIV and FBDIV. + * | | |01 = Fractional mode. + * | | |This mode is suitable for applications which need small output frequency steps, like 20 kHz + * | | |The jitter performance in this mode may be worse than in Integer Mode. + * | | |In this mode, the output clock frequency is at the fractional multiples of the input clock frequency + * | | |By setting the control pins FRAC [23:0], a small output frequency step is achieved.. + * | | |10 = Spread Spectrum Mode. + * | | |This mode is suitable for In this mode the output frequency of PLL will be modulated by triangle wave + * | | |It is for EMI consideration. + * | | |By setting SSRATE [10:0] and SLOPE [23:0], the modulation index and the modulation frequency can be programmed. + * | | |Note: This bit is write protected + * | | |Refer to the SYS_RLKTZS register + * | | |For PLL3, PLL4, and PLL5, user can also refer to the SYS_RLKTZNS register if SYSSIAEN is 1. + * |[30:20] |SSRATE |Spreading Frequency Control (Write Protect) + * | | |Set the spread step factor SSRATE from 0 to 2047, + * | | |SSRATE = SSRATE [10:0]. + * | | |Note: This bit is write protected + * | | |Refer to the SYS_RLKTZS register + * | | |For PLL3, PLL4, and PLL5, user can also refer to the SYS_RLKTZNS register if SYSSIAEN is 1. + * @var CLK_T::PLL5CTL1 + * Offset: 0xB4 VPLL Control Register 1(Write Protect) + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[0] |PD |Power-down Mode (Write Protect) + * | | |0 = PLL is enable (in normal mode). + * | | |1 = PLL is disable (in Power-down mode) (default). + * | | |Note: This bit is write protected + * | | |Refer to the SYS_RLKTZS register + * | | |For PLL3, PLL4, and PLL5, user can also refer to the SYS_RLKTZNS register if SYSSIAEN is 1. + * |[1] |BP |PLL Bypass Control (Write Protect) + * | | |0 = PLL is in normal mode (default). + * | | |1 = PLL clock output is same as PLL input clock Fref. + * | | |Note: This bit is write protected + * | | |Refer to the SYS_RLKTZS register + * | | |For PLL3, PLL4, and PLL5, user can also refer to the SYS_RLKTZNS register if SYSSIAEN is 1. + * |[6:4] |OUTDIV |PLL Output Divider Control (Write Protect) + * | | |Set the output divider factor (P) from 1 to 7. + * | | |P = OUTDIV[2:0]. + * | | |Note: This bit is write protected + * | | |Refer to the SYS_RLKTZS register + * | | |For PLL3, PLL4, and PLL5, user can also refer to the SYS_RLKTZNS register if SYSSIAEN is 1. + * |[31:8] |FRAC |PLL Fractional Portion of DN Value (Write Protect) + * | | |Set the fraction part (X) of Fractional Portion of DN Value factor. + * | | |The X = FRAC[23:0] / 224. + * | | |Note: This bit is write protected + * | | |Refer to the SYS_RLKTZS register + * | | |For PLL3, PLL4, and PLL5, user can also refer to the SYS_RLKTZNS register if SYSSIAEN is 1. + * @var CLK_T::PLL5CTL2 + * Offset: 0xB8 VPLL Control Register 2(Write Protect) + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[23:0] |SLOPE |PLL Stable Counter Selection (Write Protect) + * | | |Set the spread step factor SLOPE from 0 to 16777215, + * | | |SLOPE = SLOPE[23:0]. + * | | |Note 1: This bit is write protected + * | | |Refer to the SYS_RLKTZS register + * | | |For PLL3, PLL4, and PLL5, user can also refer to the SYS_RLKTZNS register if SYSSIAEN is 1. + * @var CLK_T::CLKDCTL + * Offset: 0xC0 Clock Fail Detector Control Register(Write Protect) + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[4] |HXTFDEN |HXT Clock Fail Detector Enable Bit + * | | |0 = 24 MHz external high speed crystal oscillator (HXT) clock fail detector Disabled. + * | | |1 = 24 MHz external high speed crystal oscillator (HXT) clock fail detector Enabled. + * |[5] |HXTFIEN |HXT Clock Fail Interrupt Enable Bit + * | | |0 = 24 MHz external high speed crystal oscillator (HXT) clock fail interrupt Disabled. + * | | |1 = 24 MHz external high speed crystal oscillator (HXT) clock fail interrupt Enabled. + * |[12] |LXTFDEN |LXT Clock Fail Detector Enable Bit + * | | |0 = 32.768 kHz external low speed crystal oscillator (LXT) clock fail detector Disabled. + * | | |1 = 32.768 kHz external low speed crystal oscillator (LXT) clock fail detector Enabled. + * |[13] |LXTFIEN |LXT Clock Fail Interrupt Enable Bit + * | | |0 = 32.768 kHz external low speed crystal oscillator (LXT) clock fail interrupt Disabled. + * | | |1 = 32.768 kHz external low speed crystal oscillator (LXT) clock fail interrupt Enabled. + * |[16] |HXTFQDEN |HXT Clock Frequency Monitor Enable Bit + * | | |0 = 24 MHz external high speed crystal oscillator (HXT) clock frequency monitor Disabled. + * | | |1 = 24 MHz external high speed crystal oscillator (HXT) clock frequency monitor Enabled. + * |[17] |HXTFQIEN |HXT Clock Frequency Monitor Interrupt Enable Bit + * | | |0 = 24 MHz external high speed crystal oscillator (HXT) clock frequency monitor fail interrupt Disabled. + * | | |1 = 24 MHz external high speed crystal oscillator (HXT) clock frequency monitor fail interrupt Enabled. + * @var CLK_T::CLKDSTS + * Offset: 0xC4 Clock Fail Detector Status Register(Write Protect) + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[0] |HXTFIF |HXT Clock Fail Interrupt Flag (Write Protect, Write 1 to Clear) + * | | |0 = 24 MHz external high speed crystal oscillator (HXT) clock is normal. + * | | |1 = 24 MHz external high speed crystal oscillator (HXT) clock stops. + * | | |Note 1: Write 1 to clear the bit to 0. + * | | |Note 2: This bit is write protected. Refer to the SYS_RLKTZS register. + * |[1] |LXTFIF |LXT Clock Fail Interrupt Flag (Write Protect, Write 1 to Clear) + * | | |0 = 32.768 kHz external low speed crystal oscillator (LXT) clock is normal. + * | | |1 = 32.768 kHz external low speed crystal oscillator (LXT) stops. + * | | |Note 1: Write 1 to clear the bit to 0. + * | | |Note 2: This bit is write protected. Refer to the SYS_RLKTZS register. + * |[8] |HXTFQIF |HXT Clock Frequency Monitor Interrupt Flag (Write Protect, Write 1 to Clear) + * | | |0 = 24 MHz external high speed crystal oscillator (HXT) clock is normal. + * | | |1 = 24 MHz external high speed crystal oscillator (HXT) clock frequency is abnormal. + * | | |Note 1: Write 1 to clear the bit to 0. + * | | |Note 2: This bit is write protected. Refer to the SYS_RLKTZS register. + * @var CLK_T::CDUPB + * Offset: 0xC8 Clock Frequency Detector Upper Boundary Register(Write Protect) + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[9:0] |UPERBD |HXT Clock Frequency Detector Upper Boundary + * | | |The bits define the high value of frequency monitor window. + * | | |When HXT frequency monitor value higher than this register, the HXT frequency detect fail interrupt flag will set to 1. + * @var CLK_T::CDLOWB + * Offset: 0xCC Clock Frequency Detector Lower Boundary Register(Write Protect) + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[9:0] |LOWERBD |HXT Clock Frequency Detector Lower Boundary + * | | |The bits define the low value of frequency monitor window. + * | | |When HXT frequency monitor value lower than this register, the HXT frequency detect fail interrupt flag will set to 1. + * @var CLK_T::CKFLTRCTL + * Offset: 0xD0 Clock Filter Control Register (Write Protect) + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[0] |HXTFLTREN |HXT Clock Filter Enable Control Bit (Write Protect) + * | | |0 = HXT clock filter function Disabled. + * | | |1 = HXT clock filter function Enabled. + * | | |Note: This bit is write protected. Refer to the SYS_RLKTZS register. + * |[1] |HXTFLTRSEL|HXT Clock Filter Frequency Select + * | | |0 = HXT frequency is > 24 MHz. + * | | |1 = HXT frequency is <= 24 MHz. + * | | |Note: This bit is write protected. Refer to the SYS_RLKTZS register. + * |[4] |HXTGTEN |HXT Clock Gating Enable Control Bit (Write Protect) + * | | |0 = HXT clock filter function Disabled. + * | | |1 = HXT clock filter function Enabled. + * | | |Note: This bit is write protected. Refer to the SYS_RLKTZS register. + * |[5] |HXTBYPSEN |HXT Clock Bypass Enable Control Bit (Write Protect) + * | | |0 = HXT clock filter function Disabled. + * | | |1 = HXT clock filter function Enabled. + * | | |Note: This bit is write protected. Refer to the SYS_RLKTZS register. + * |[8] |HIRCFLTREN|HIRC Clock Filter Enable Control Bit (Write Protect) + * | | |0 = HIRC clock filter function Disabled. + * | | |1 = HIRC clock filter function Enabled. + * | | |Note: This bit is write protected. Refer to the SYS_RLKTZS register. + * |[9] |HIRCFLTRSEL|HIRC Clock Filter Frequency Select + * | | |0 = HIRC frequency is > 12 MHz. + * | | |1 = HIRC frequency is <= 12 MHz. + * | | |Note: This bit is write protected. Refer to the SYS_RLKTZS register. + * |[12] |HIRCGTEN |HIRC Clock Gating Enable Control Bit (Write Protect) + * | | |0 = HIRC clock filter function Disabled. + * | | |1 = HIRC clock filter function Enabled. + * | | |Note: This bit is write protected. Refer to the SYS_RLKTZS register. + */ + __IO uint32_t PWRCTL; /*!< [0x0000] System Power-down Control Register */ + __IO uint32_t SYSCLK0; /*!< [0x0004] AXI and AHB Device Clock Enable Control Register 0 */ + __IO uint32_t SYSCLK1; /*!< [0x0008] AXI and AHB Device Clock Enable Control Register 1 */ + __IO uint32_t APBCLK0; /*!< [0x000c] APB Devices Clock Enable Control Register 0 */ + __IO uint32_t APBCLK1; /*!< [0x0010] APB Devices Clock Enable Control Register 1 */ + __IO uint32_t APBCLK2; /*!< [0x0014] APB Devices Clock Enable Control Register 2 */ + __IO uint32_t CLKSEL0; /*!< [0x0018] Clock Source Select Control Register 0 */ + __IO uint32_t CLKSEL1; /*!< [0x001c] Clock Source Select Control Register 1 */ + __IO uint32_t CLKSEL2; /*!< [0x0020] Clock Source Select Control Register 2 */ + __IO uint32_t CLKSEL3; /*!< [0x0024] Clock Source Select Control Register 3 */ + __IO uint32_t CLKSEL4; /*!< [0x0028] Clock Source Select Control Register 4 */ + __IO uint32_t CLKDIV0; /*!< [0x002c] Clock Divider Number Register 0 */ + __IO uint32_t CLKDIV1; /*!< [0x0030] Clock Divider Number Register 1 */ + __IO uint32_t CLKDIV2; /*!< [0x0034] Clock Divider Number Register 2 */ + __IO uint32_t CLKDIV3; /*!< [0x0038] Clock Divider Number Register 3 */ + __IO uint32_t CLKDIV4; /*!< [0x003c] Clock Divider Number Register 4 */ + __IO uint32_t CLKOCTL; /*!< [0x0040] Clock Output Control Register (Write Protect) */ + __I uint32_t RESERVE0[3]; + __I uint32_t STATUS; /*!< [0x0050] Clock Status Monitor Register */ + __I uint32_t RESERVE1[3]; + union + { + /* data */ + __IO uint32_t PLL0CTL0; /*!< [0x0060] CA-PLL Control Register 0 */ + PLL_T PLL[6]; /*!< [0x0080] PLL Control Registers (Write Protect) */ + }; + __IO uint32_t CLKDCTL; /*!< [0x00c0] Clock Fail Detector Control Register(Write Protect) */ + __IO uint32_t CLKDSTS; /*!< [0x00c4] Clock Fail Detector Status Register(Write Protect) */ + __IO uint32_t CDUPB; /*!< [0x00c8] Clock Frequency Detector Upper Boundary Register(Write Protect) */ + __IO uint32_t CDLOWB; /*!< [0x00cc] Clock Frequency Detector Lower Boundary Register(Write Protect) */ + __IO uint32_t CKFLTRCTL; /*!< [0x00d0] Clock Filter Control Register (Write Protect) */ + +} CLK_T; + +/** + @addtogroup CLK_CONST CLK Bit Field Definition + Constant Definitions for CLK Controller +@{ */ + +#define CLK_PWRCTL_HXTEN_Pos (0) /*!< CLK_T::PWRCTL: HXTEN Position */ +#define CLK_PWRCTL_HXTEN_Msk (0x1ul << CLK_PWRCTL_HXTEN_Pos) /*!< CLK_T::PWRCTL: HXTEN Mask */ + +#define CLK_PWRCTL_LXTEN_Pos (1) /*!< CLK_T::PWRCTL: LXTEN Position */ +#define CLK_PWRCTL_LXTEN_Msk (0x1ul << CLK_PWRCTL_LXTEN_Pos) /*!< CLK_T::PWRCTL: LXTEN Mask */ + +#define CLK_PWRCTL_HIRCEN_Pos (2) /*!< CLK_T::PWRCTL: HIRCEN Position */ +#define CLK_PWRCTL_HIRCEN_Msk (0x1ul << CLK_PWRCTL_HIRCEN_Pos) /*!< CLK_T::PWRCTL: HIRCEN Mask */ + +#define CLK_PWRCTL_LIRCEN_Pos (3) /*!< CLK_T::PWRCTL: LIRCEN Position */ +#define CLK_PWRCTL_LIRCEN_Msk (0x1ul << CLK_PWRCTL_LIRCEN_Pos) /*!< CLK_T::PWRCTL: LIRCEN Mask */ + +#define CLK_PWRCTL_HXTDS_Pos (10) /*!< CLK_T::PWRCTL: HXTDS Position */ +#define CLK_PWRCTL_HXTDS_Msk (0x1ul << CLK_PWRCTL_HXTDS_Pos) /*!< CLK_T::PWRCTL: HXTDS Mask */ + +#define CLK_PWRCTL_SYSPLLAPD_Pos (11) /*!< CLK_T::PWRCTL: SYSPLLAPD Position */ +#define CLK_PWRCTL_SYSPLLAPD_Msk (0x1ul << CLK_PWRCTL_SYSPLLAPD_Pos) /*!< CLK_T::PWRCTL: SYSPLLAPD Mask */ + +#define CLK_PWRCTL_CAPLLAPD_Pos (12) /*!< CLK_T::PWRCTL: CAPLLAPD Position */ +#define CLK_PWRCTL_CAPLLAPD_Msk (0x1ul << CLK_PWRCTL_CAPLLAPD_Pos) /*!< CLK_T::PWRCTL: CAPLLAPD Mask */ + +#define CLK_PWRCTL_DDRPLLAPD_Pos (13) /*!< CLK_T::PWRCTL: DDRPLLAPD Position */ +#define CLK_PWRCTL_DDRPLLAPD_Msk (0x1ul << CLK_PWRCTL_DDRPLLAPD_Pos) /*!< CLK_T::PWRCTL: DDRPLLAPD Mask */ + +#define CLK_PWRCTL_HXTAOFF_Pos (14) /*!< CLK_T::PWRCTL: HXTAOFF Position */ +#define CLK_PWRCTL_HXTAOFF_Msk (0x1ul << CLK_PWRCTL_HXTAOFF_Pos) /*!< CLK_T::PWRCTL: HXTAOFF Mask */ + +#define CLK_PWRCTL_HIRCAOFF_Pos (15) /*!< CLK_T::PWRCTL: HIRCAOFF Position */ +#define CLK_PWRCTL_HIRCAOFF_Msk (0x1ul << CLK_PWRCTL_HIRCAOFF_Pos) /*!< CLK_T::PWRCTL: HIRCAOFF Mask */ + +#define CLK_PWRCTL_LXTSTBS_Pos (16) /*!< CLK_T::PWRCTL: LXTSTBS Position */ +#define CLK_PWRCTL_LXTSTBS_Msk (0x3ul << CLK_PWRCTL_LXTSTBS_Pos) /*!< CLK_T::PWRCTL: LXTSTBS Mask */ + +#define CLK_PWRCTL_GICAOFF_Pos (21) /*!< CLK_T::PWRCTL: GICAOFF Position */ +#define CLK_PWRCTL_GICAOFF_Msk (0x1ul << CLK_PWRCTL_GICAOFF_Pos) /*!< CLK_T::PWRCTL: GICAOFF Mask */ + +#define CLK_PWRCTL_HXTAPD_Pos (22) /*!< CLK_T::PWRCTL: HXTAPD Position */ +#define CLK_PWRCTL_HXTAPD_Msk (0x1ul << CLK_PWRCTL_HXTAPD_Pos) /*!< CLK_T::PWRCTL: HXTAPD Mask */ + +#define CLK_PWRCTL_HIRCAPD_Pos (23) /*!< CLK_T::PWRCTL: HIRCAPD Position */ +#define CLK_PWRCTL_HIRCAPD_Msk (0x1ul << CLK_PWRCTL_HIRCAPD_Pos) /*!< CLK_T::PWRCTL: HIRCAPD Mask */ + +#define CLK_SYSCLK0_RTPEN_Pos (1) /*!< CLK_T::SYSCLK0: RTPEN Position */ +#define CLK_SYSCLK0_RTPEN_Msk (0x1ul << CLK_SYSCLK0_RTPEN_Pos) /*!< CLK_T::SYSCLK0: RTPEN Mask */ + +#define CLK_SYSCLK0_TAHBCKEN_Pos (2) /*!< CLK_T::SYSCLK0: TAHBCKEN Position */ +#define CLK_SYSCLK0_TAHBCKEN_Msk (0x1ul << CLK_SYSCLK0_TAHBCKEN_Pos) /*!< CLK_T::SYSCLK0: TAHBCKEN Mask */ + +#define CLK_SYSCLK0_LVRDBEN_Pos (3) /*!< CLK_T::SYSCLK0: LVRDBEN Position */ +#define CLK_SYSCLK0_LVRDBEN_Msk (0x1ul << CLK_SYSCLK0_LVRDBEN_Pos) /*!< CLK_T::SYSCLK0: LVRDBEN Mask */ + +#define CLK_SYSCLK0_DDR0CKEN_Pos (4) /*!< CLK_T::SYSCLK0: DDR0CKEN Position */ +#define CLK_SYSCLK0_DDR0CKEN_Msk (0x1ul << CLK_SYSCLK0_DDR0CKEN_Pos) /*!< CLK_T::SYSCLK0: DDR0CKEN Mask */ + +#define CLK_SYSCLK0_DDR6CKEN_Pos (5) /*!< CLK_T::SYSCLK0: DDR6CKEN Position */ +#define CLK_SYSCLK0_DDR6CKEN_Msk (0x1ul << CLK_SYSCLK0_DDR6CKEN_Pos) /*!< CLK_T::SYSCLK0: DDR6CKEN Mask */ + +#define CLK_SYSCLK0_CANFD0CKEN_Pos (8) /*!< CLK_T::SYSCLK0: CANFD0CKEN Position */ +#define CLK_SYSCLK0_CANFD0CKEN_Msk (0x1ul << CLK_SYSCLK0_CANFD0CKEN_Pos) /*!< CLK_T::SYSCLK0: CANFD0CKEN Mask */ + +#define CLK_SYSCLK0_CANFD1CKEN_Pos (9) /*!< CLK_T::SYSCLK0: CANFD1CKEN Position */ +#define CLK_SYSCLK0_CANFD1CKEN_Msk (0x1ul << CLK_SYSCLK0_CANFD1CKEN_Pos) /*!< CLK_T::SYSCLK0: CANFD1CKEN Mask */ + +#define CLK_SYSCLK0_CANFD2CKEN_Pos (10) /*!< CLK_T::SYSCLK0: CANFD2CKEN Position */ +#define CLK_SYSCLK0_CANFD2CKEN_Msk (0x1ul << CLK_SYSCLK0_CANFD2CKEN_Pos) /*!< CLK_T::SYSCLK0: CANFD2CKEN Mask */ + +#define CLK_SYSCLK0_CANFD3CKEN_Pos (11) /*!< CLK_T::SYSCLK0: CANFD3CKEN Position */ +#define CLK_SYSCLK0_CANFD3CKEN_Msk (0x1ul << CLK_SYSCLK0_CANFD3CKEN_Pos) /*!< CLK_T::SYSCLK0: CANFD3CKEN Mask */ + +#define CLK_SYSCLK0_SDH0EN_Pos (16) /*!< CLK_T::SYSCLK0: SDH0EN Position */ +#define CLK_SYSCLK0_SDH0EN_Msk (0x1ul << CLK_SYSCLK0_SDH0EN_Pos) /*!< CLK_T::SYSCLK0: SDH0EN Mask */ + +#define CLK_SYSCLK0_SDH1EN_Pos (17) /*!< CLK_T::SYSCLK0: SDH1EN Position */ +#define CLK_SYSCLK0_SDH1EN_Msk (0x1ul << CLK_SYSCLK0_SDH1EN_Pos) /*!< CLK_T::SYSCLK0: SDH1EN Mask */ + +#define CLK_SYSCLK0_NANDEN_Pos (18) /*!< CLK_T::SYSCLK0: NANDEN Position */ +#define CLK_SYSCLK0_NANDEN_Msk (0x1ul << CLK_SYSCLK0_NANDEN_Pos) /*!< CLK_T::SYSCLK0: NANDEN Mask */ + +#define CLK_SYSCLK0_USBDEN_Pos (19) /*!< CLK_T::SYSCLK0: USBDEN Position */ +#define CLK_SYSCLK0_USBDEN_Msk (0x1ul << CLK_SYSCLK0_USBDEN_Pos) /*!< CLK_T::SYSCLK0: USBDEN Mask */ + +#define CLK_SYSCLK0_USBHEN_Pos (20) /*!< CLK_T::SYSCLK0: USBHEN Position */ +#define CLK_SYSCLK0_USBHEN_Msk (0x1ul << CLK_SYSCLK0_USBHEN_Pos) /*!< CLK_T::SYSCLK0: USBHEN Mask */ + +#define CLK_SYSCLK0_HUSBH0EN_Pos (21) /*!< CLK_T::SYSCLK0: HUSBH0EN Position */ +#define CLK_SYSCLK0_HUSBH0EN_Msk (0x1ul << CLK_SYSCLK0_HUSBH0EN_Pos) /*!< CLK_T::SYSCLK0: HUSBH0EN Mask */ + +#define CLK_SYSCLK0_HUSBH1EN_Pos (22) /*!< CLK_T::SYSCLK0: HUSBH1EN Position */ +#define CLK_SYSCLK0_HUSBH1EN_Msk (0x1ul << CLK_SYSCLK0_HUSBH1EN_Pos) /*!< CLK_T::SYSCLK0: HUSBH1EN Mask */ + +#define CLK_SYSCLK0_GFXEN_Pos (24) /*!< CLK_T::SYSCLK0: GFXEN Position */ +#define CLK_SYSCLK0_GFXEN_Msk (0x1ul << CLK_SYSCLK0_GFXEN_Pos) /*!< CLK_T::SYSCLK0: GFXEN Mask */ + +#define CLK_SYSCLK0_VDECEN_Pos (25) /*!< CLK_T::SYSCLK0: VDECEN Position */ +#define CLK_SYSCLK0_VDECEN_Msk (0x1ul << CLK_SYSCLK0_VDECEN_Pos) /*!< CLK_T::SYSCLK0: VDECEN Mask */ + +#define CLK_SYSCLK0_DCUEN_Pos (26) /*!< CLK_T::SYSCLK0: DCUEN Position */ +#define CLK_SYSCLK0_DCUEN_Msk (0x1ul << CLK_SYSCLK0_DCUEN_Pos) /*!< CLK_T::SYSCLK0: DCUEN Mask */ + +#define CLK_SYSCLK0_GMAC0EN_Pos (27) /*!< CLK_T::SYSCLK0: GMAC0EN Position */ +#define CLK_SYSCLK0_GMAC0EN_Msk (0x1ul << CLK_SYSCLK0_GMAC0EN_Pos) /*!< CLK_T::SYSCLK0: GMAC0EN Mask */ + +#define CLK_SYSCLK0_GMAC1EN_Pos (28) /*!< CLK_T::SYSCLK0: GMAC1EN Position */ +#define CLK_SYSCLK0_GMAC1EN_Msk (0x1ul << CLK_SYSCLK0_GMAC1EN_Pos) /*!< CLK_T::SYSCLK0: GMAC1EN Mask */ + +#define CLK_SYSCLK0_CCAP0EN_Pos (29) /*!< CLK_T::SYSCLK0: CCAP0EN Position */ +#define CLK_SYSCLK0_CCAP0EN_Msk (0x1ul << CLK_SYSCLK0_CCAP0EN_Pos) /*!< CLK_T::SYSCLK0: CCAP0EN Mask */ + +#define CLK_SYSCLK0_CCAP1EN_Pos (30) /*!< CLK_T::SYSCLK0: CCAP1EN Position */ +#define CLK_SYSCLK0_CCAP1EN_Msk (0x1ul << CLK_SYSCLK0_CCAP1EN_Pos) /*!< CLK_T::SYSCLK0: CCAP1EN Mask */ + +#define CLK_SYSCLK1_PDMA0EN_Pos (0) /*!< CLK_T::SYSCLK1: PDMA0EN Position */ +#define CLK_SYSCLK1_PDMA0EN_Msk (0x1ul << CLK_SYSCLK1_PDMA0EN_Pos) /*!< CLK_T::SYSCLK1: PDMA0EN Mask */ + +#define CLK_SYSCLK1_PDMA1EN_Pos (1) /*!< CLK_T::SYSCLK1: PDMA1EN Position */ +#define CLK_SYSCLK1_PDMA1EN_Msk (0x1ul << CLK_SYSCLK1_PDMA1EN_Pos) /*!< CLK_T::SYSCLK1: PDMA1EN Mask */ + +#define CLK_SYSCLK1_PDMA2EN_Pos (2) /*!< CLK_T::SYSCLK1: PDMA2EN Position */ +#define CLK_SYSCLK1_PDMA2EN_Msk (0x1ul << CLK_SYSCLK1_PDMA2EN_Pos) /*!< CLK_T::SYSCLK1: PDMA2EN Mask */ + +#define CLK_SYSCLK1_PDMA3EN_Pos (3) /*!< CLK_T::SYSCLK1: PDMA3EN Position */ +#define CLK_SYSCLK1_PDMA3EN_Msk (0x1ul << CLK_SYSCLK1_PDMA3EN_Pos) /*!< CLK_T::SYSCLK1: PDMA3EN Mask */ + +#define CLK_SYSCLK1_WH0CKEN_Pos (4) /*!< CLK_T::SYSCLK1: WH0CKEN Position */ +#define CLK_SYSCLK1_WH0CKEN_Msk (0x1ul << CLK_SYSCLK1_WH0CKEN_Pos) /*!< CLK_T::SYSCLK1: WH0CKEN Mask */ + +#define CLK_SYSCLK1_WH1CKEN_Pos (5) /*!< CLK_T::SYSCLK1: WH1CKEN Position */ +#define CLK_SYSCLK1_WH1CKEN_Msk (0x1ul << CLK_SYSCLK1_WH1CKEN_Pos) /*!< CLK_T::SYSCLK1: WH1CKEN Mask */ + +#define CLK_SYSCLK1_HWSCKEN_Pos (6) /*!< CLK_T::SYSCLK1: HWSCKEN Position */ +#define CLK_SYSCLK1_HWSCKEN_Msk (0x1ul << CLK_SYSCLK1_HWSCKEN_Pos) /*!< CLK_T::SYSCLK1: HWSCKEN Mask */ + +#define CLK_SYSCLK1_EBICKEN_Pos (7) /*!< CLK_T::SYSCLK1: EBICKEN Position */ +#define CLK_SYSCLK1_EBICKEN_Msk (0x1ul << CLK_SYSCLK1_EBICKEN_Pos) /*!< CLK_T::SYSCLK1: EBICKEN Mask */ + +#define CLK_SYSCLK1_SRAM0CKEN_Pos (8) /*!< CLK_T::SYSCLK1: SRAM0CKEN Position */ +#define CLK_SYSCLK1_SRAM0CKEN_Msk (0x1ul << CLK_SYSCLK1_SRAM0CKEN_Pos) /*!< CLK_T::SYSCLK1: SRAM0CKEN Mask */ + +#define CLK_SYSCLK1_SRAM1CKEN_Pos (9) /*!< CLK_T::SYSCLK1: SRAM1CKEN Position */ +#define CLK_SYSCLK1_SRAM1CKEN_Msk (0x1ul << CLK_SYSCLK1_SRAM1CKEN_Pos) /*!< CLK_T::SYSCLK1: SRAM1CKEN Mask */ + +#define CLK_SYSCLK1_ROMCKEN_Pos (10) /*!< CLK_T::SYSCLK1: ROMCKEN Position */ +#define CLK_SYSCLK1_ROMCKEN_Msk (0x1ul << CLK_SYSCLK1_ROMCKEN_Pos) /*!< CLK_T::SYSCLK1: ROMCKEN Mask */ + +#define CLK_SYSCLK1_TRACKEN_Pos (11) /*!< CLK_T::SYSCLK1: TRACKEN Position */ +#define CLK_SYSCLK1_TRACKEN_Msk (0x1ul << CLK_SYSCLK1_TRACKEN_Pos) /*!< CLK_T::SYSCLK1: TRACKEN Mask */ + +#define CLK_SYSCLK1_DBGCKEN_Pos (12) /*!< CLK_T::SYSCLK1: DBGCKEN Position */ +#define CLK_SYSCLK1_DBGCKEN_Msk (0x1ul << CLK_SYSCLK1_DBGCKEN_Pos) /*!< CLK_T::SYSCLK1: DBGCKEN Mask */ + +#define CLK_SYSCLK1_CLKOCKEN_Pos (13) /*!< CLK_T::SYSCLK1: CLKOCKEN Position */ +#define CLK_SYSCLK1_CLKOCKEN_Msk (0x1ul << CLK_SYSCLK1_CLKOCKEN_Pos) /*!< CLK_T::SYSCLK1: CLKOCKEN Mask */ + +#define CLK_SYSCLK1_GTMRCKEN_Pos (14) /*!< CLK_T::SYSCLK1: GTMRCKEN Position */ +#define CLK_SYSCLK1_GTMRCKEN_Msk (0x1ul << CLK_SYSCLK1_GTMRCKEN_Pos) /*!< CLK_T::SYSCLK1: GTMRCKEN Mask */ + +#define CLK_SYSCLK1_GPACKEN_Pos (16) /*!< CLK_T::SYSCLK1: GPACKEN Position */ +#define CLK_SYSCLK1_GPACKEN_Msk (0x1ul << CLK_SYSCLK1_GPACKEN_Pos) /*!< CLK_T::SYSCLK1: GPACKEN Mask */ + +#define CLK_SYSCLK1_GPBCKEN_Pos (17) /*!< CLK_T::SYSCLK1: GPBCKEN Position */ +#define CLK_SYSCLK1_GPBCKEN_Msk (0x1ul << CLK_SYSCLK1_GPBCKEN_Pos) /*!< CLK_T::SYSCLK1: GPBCKEN Mask */ + +#define CLK_SYSCLK1_GPCCKEN_Pos (18) /*!< CLK_T::SYSCLK1: GPCCKEN Position */ +#define CLK_SYSCLK1_GPCCKEN_Msk (0x1ul << CLK_SYSCLK1_GPCCKEN_Pos) /*!< CLK_T::SYSCLK1: GPCCKEN Mask */ + +#define CLK_SYSCLK1_GPDCKEN_Pos (19) /*!< CLK_T::SYSCLK1: GPDCKEN Position */ +#define CLK_SYSCLK1_GPDCKEN_Msk (0x1ul << CLK_SYSCLK1_GPDCKEN_Pos) /*!< CLK_T::SYSCLK1: GPDCKEN Mask */ + +#define CLK_SYSCLK1_GPECKEN_Pos (20) /*!< CLK_T::SYSCLK1: GPECKEN Position */ +#define CLK_SYSCLK1_GPECKEN_Msk (0x1ul << CLK_SYSCLK1_GPECKEN_Pos) /*!< CLK_T::SYSCLK1: GPECKEN Mask */ + +#define CLK_SYSCLK1_GPFCKEN_Pos (21) /*!< CLK_T::SYSCLK1: GPFCKEN Position */ +#define CLK_SYSCLK1_GPFCKEN_Msk (0x1ul << CLK_SYSCLK1_GPFCKEN_Pos) /*!< CLK_T::SYSCLK1: GPFCKEN Mask */ + +#define CLK_SYSCLK1_GPGCKEN_Pos (22) /*!< CLK_T::SYSCLK1: GPGCKEN Position */ +#define CLK_SYSCLK1_GPGCKEN_Msk (0x1ul << CLK_SYSCLK1_GPGCKEN_Pos) /*!< CLK_T::SYSCLK1: GPGCKEN Mask */ + +#define CLK_SYSCLK1_GPHCKEN_Pos (23) /*!< CLK_T::SYSCLK1: GPHCKEN Position */ +#define CLK_SYSCLK1_GPHCKEN_Msk (0x1ul << CLK_SYSCLK1_GPHCKEN_Pos) /*!< CLK_T::SYSCLK1: GPHCKEN Mask */ + +#define CLK_SYSCLK1_GPICKEN_Pos (24) /*!< CLK_T::SYSCLK1: GPICKEN Position */ +#define CLK_SYSCLK1_GPICKEN_Msk (0x1ul << CLK_SYSCLK1_GPICKEN_Pos) /*!< CLK_T::SYSCLK1: GPICKEN Mask */ + +#define CLK_SYSCLK1_GPJCKEN_Pos (25) /*!< CLK_T::SYSCLK1: GPJCKEN Position */ +#define CLK_SYSCLK1_GPJCKEN_Msk (0x1ul << CLK_SYSCLK1_GPJCKEN_Pos) /*!< CLK_T::SYSCLK1: GPJCKEN Mask */ + +#define CLK_SYSCLK1_GPKCKEN_Pos (26) /*!< CLK_T::SYSCLK1: GPKCKEN Position */ +#define CLK_SYSCLK1_GPKCKEN_Msk (0x1ul << CLK_SYSCLK1_GPKCKEN_Pos) /*!< CLK_T::SYSCLK1: GPKCKEN Mask */ + +#define CLK_SYSCLK1_GPLCKEN_Pos (27) /*!< CLK_T::SYSCLK1: GPLCKEN Position */ +#define CLK_SYSCLK1_GPLCKEN_Msk (0x1ul << CLK_SYSCLK1_GPLCKEN_Pos) /*!< CLK_T::SYSCLK1: GPLCKEN Mask */ + +#define CLK_SYSCLK1_GPMCKEN_Pos (28) /*!< CLK_T::SYSCLK1: GPMCKEN Position */ +#define CLK_SYSCLK1_GPMCKEN_Msk (0x1ul << CLK_SYSCLK1_GPMCKEN_Pos) /*!< CLK_T::SYSCLK1: GPMCKEN Mask */ + +#define CLK_SYSCLK1_GPNCKEN_Pos (29) /*!< CLK_T::SYSCLK1: GPNCKEN Position */ +#define CLK_SYSCLK1_GPNCKEN_Msk (0x1ul << CLK_SYSCLK1_GPNCKEN_Pos) /*!< CLK_T::SYSCLK1: GPNCKEN Mask */ + +#define CLK_APBCLK0_TMR0CKEN_Pos (0) /*!< CLK_T::APBCLK0: TMR0CKEN Position */ +#define CLK_APBCLK0_TMR0CKEN_Msk (0x1ul << CLK_APBCLK0_TMR0CKEN_Pos) /*!< CLK_T::APBCLK0: TMR0CKEN Mask */ + +#define CLK_APBCLK0_TMR1CKEN_Pos (1) /*!< CLK_T::APBCLK0: TMR1CKEN Position */ +#define CLK_APBCLK0_TMR1CKEN_Msk (0x1ul << CLK_APBCLK0_TMR1CKEN_Pos) /*!< CLK_T::APBCLK0: TMR1CKEN Mask */ + +#define CLK_APBCLK0_TMR2CKEN_Pos (2) /*!< CLK_T::APBCLK0: TMR2CKEN Position */ +#define CLK_APBCLK0_TMR2CKEN_Msk (0x1ul << CLK_APBCLK0_TMR2CKEN_Pos) /*!< CLK_T::APBCLK0: TMR2CKEN Mask */ + +#define CLK_APBCLK0_TMR3CKEN_Pos (3) /*!< CLK_T::APBCLK0: TMR3CKEN Position */ +#define CLK_APBCLK0_TMR3CKEN_Msk (0x1ul << CLK_APBCLK0_TMR3CKEN_Pos) /*!< CLK_T::APBCLK0: TMR3CKEN Mask */ + +#define CLK_APBCLK0_TMR4CKEN_Pos (4) /*!< CLK_T::APBCLK0: TMR4CKEN Position */ +#define CLK_APBCLK0_TMR4CKEN_Msk (0x1ul << CLK_APBCLK0_TMR4CKEN_Pos) /*!< CLK_T::APBCLK0: TMR4CKEN Mask */ + +#define CLK_APBCLK0_TMR5CKEN_Pos (5) /*!< CLK_T::APBCLK0: TMR5CKEN Position */ +#define CLK_APBCLK0_TMR5CKEN_Msk (0x1ul << CLK_APBCLK0_TMR5CKEN_Pos) /*!< CLK_T::APBCLK0: TMR5CKEN Mask */ + +#define CLK_APBCLK0_TMR6CKEN_Pos (6) /*!< CLK_T::APBCLK0: TMR6CKEN Position */ +#define CLK_APBCLK0_TMR6CKEN_Msk (0x1ul << CLK_APBCLK0_TMR6CKEN_Pos) /*!< CLK_T::APBCLK0: TMR6CKEN Mask */ + +#define CLK_APBCLK0_TMR7CKEN_Pos (7) /*!< CLK_T::APBCLK0: TMR7CKEN Position */ +#define CLK_APBCLK0_TMR7CKEN_Msk (0x1ul << CLK_APBCLK0_TMR7CKEN_Pos) /*!< CLK_T::APBCLK0: TMR7CKEN Mask */ + +#define CLK_APBCLK0_TMR8CKEN_Pos (8) /*!< CLK_T::APBCLK0: TMR8CKEN Position */ +#define CLK_APBCLK0_TMR8CKEN_Msk (0x1ul << CLK_APBCLK0_TMR8CKEN_Pos) /*!< CLK_T::APBCLK0: TMR8CKEN Mask */ + +#define CLK_APBCLK0_TMR9CKEN_Pos (9) /*!< CLK_T::APBCLK0: TMR9CKEN Position */ +#define CLK_APBCLK0_TMR9CKEN_Msk (0x1ul << CLK_APBCLK0_TMR9CKEN_Pos) /*!< CLK_T::APBCLK0: TMR9CKEN Mask */ + +#define CLK_APBCLK0_TMR10CKEN_Pos (10) /*!< CLK_T::APBCLK0: TMR10CKEN Position */ +#define CLK_APBCLK0_TMR10CKEN_Msk (0x1ul << CLK_APBCLK0_TMR10CKEN_Pos) /*!< CLK_T::APBCLK0: TMR10CKEN Mask */ + +#define CLK_APBCLK0_TMR11CKEN_Pos (11) /*!< CLK_T::APBCLK0: TMR11CKEN Position */ +#define CLK_APBCLK0_TMR11CKEN_Msk (0x1ul << CLK_APBCLK0_TMR11CKEN_Pos) /*!< CLK_T::APBCLK0: TMR11CKEN Mask */ + +#define CLK_APBCLK0_UART0CKEN_Pos (12) /*!< CLK_T::APBCLK0: UART0CKEN Position */ +#define CLK_APBCLK0_UART0CKEN_Msk (0x1ul << CLK_APBCLK0_UART0CKEN_Pos) /*!< CLK_T::APBCLK0: UART0CKEN Mask */ + +#define CLK_APBCLK0_UART1CKEN_Pos (13) /*!< CLK_T::APBCLK0: UART1CKEN Position */ +#define CLK_APBCLK0_UART1CKEN_Msk (0x1ul << CLK_APBCLK0_UART1CKEN_Pos) /*!< CLK_T::APBCLK0: UART1CKEN Mask */ + +#define CLK_APBCLK0_UART2CKEN_Pos (14) /*!< CLK_T::APBCLK0: UART2CKEN Position */ +#define CLK_APBCLK0_UART2CKEN_Msk (0x1ul << CLK_APBCLK0_UART2CKEN_Pos) /*!< CLK_T::APBCLK0: UART2CKEN Mask */ + +#define CLK_APBCLK0_UART3CKEN_Pos (15) /*!< CLK_T::APBCLK0: UART3CKEN Position */ +#define CLK_APBCLK0_UART3CKEN_Msk (0x1ul << CLK_APBCLK0_UART3CKEN_Pos) /*!< CLK_T::APBCLK0: UART3CKEN Mask */ + +#define CLK_APBCLK0_UART4CKEN_Pos (16) /*!< CLK_T::APBCLK0: UART4CKEN Position */ +#define CLK_APBCLK0_UART4CKEN_Msk (0x1ul << CLK_APBCLK0_UART4CKEN_Pos) /*!< CLK_T::APBCLK0: UART4CKEN Mask */ + +#define CLK_APBCLK0_UART5CKEN_Pos (17) /*!< CLK_T::APBCLK0: UART5CKEN Position */ +#define CLK_APBCLK0_UART5CKEN_Msk (0x1ul << CLK_APBCLK0_UART5CKEN_Pos) /*!< CLK_T::APBCLK0: UART5CKEN Mask */ + +#define CLK_APBCLK0_UART6CKEN_Pos (18) /*!< CLK_T::APBCLK0: UART6CKEN Position */ +#define CLK_APBCLK0_UART6CKEN_Msk (0x1ul << CLK_APBCLK0_UART6CKEN_Pos) /*!< CLK_T::APBCLK0: UART6CKEN Mask */ + +#define CLK_APBCLK0_UART7CKEN_Pos (19) /*!< CLK_T::APBCLK0: UART7CKEN Position */ +#define CLK_APBCLK0_UART7CKEN_Msk (0x1ul << CLK_APBCLK0_UART7CKEN_Pos) /*!< CLK_T::APBCLK0: UART7CKEN Mask */ + +#define CLK_APBCLK0_UART8CKEN_Pos (20) /*!< CLK_T::APBCLK0: UART8CKEN Position */ +#define CLK_APBCLK0_UART8CKEN_Msk (0x1ul << CLK_APBCLK0_UART8CKEN_Pos) /*!< CLK_T::APBCLK0: UART8CKEN Mask */ + +#define CLK_APBCLK0_UART9CKEN_Pos (21) /*!< CLK_T::APBCLK0: UART9CKEN Position */ +#define CLK_APBCLK0_UART9CKEN_Msk (0x1ul << CLK_APBCLK0_UART9CKEN_Pos) /*!< CLK_T::APBCLK0: UART9CKEN Mask */ + +#define CLK_APBCLK0_UART10CKEN_Pos (22) /*!< CLK_T::APBCLK0: UART10CKEN Position */ +#define CLK_APBCLK0_UART10CKEN_Msk (0x1ul << CLK_APBCLK0_UART10CKEN_Pos) /*!< CLK_T::APBCLK0: UART10CKEN Mask */ + +#define CLK_APBCLK0_UART11CKEN_Pos (23) /*!< CLK_T::APBCLK0: UART11CKEN Position */ +#define CLK_APBCLK0_UART11CKEN_Msk (0x1ul << CLK_APBCLK0_UART11CKEN_Pos) /*!< CLK_T::APBCLK0: UART11CKEN Mask */ + +#define CLK_APBCLK0_UART12CKEN_Pos (24) /*!< CLK_T::APBCLK0: UART12CKEN Position */ +#define CLK_APBCLK0_UART12CKEN_Msk (0x1ul << CLK_APBCLK0_UART12CKEN_Pos) /*!< CLK_T::APBCLK0: UART12CKEN Mask */ + +#define CLK_APBCLK0_UART13CKEN_Pos (25) /*!< CLK_T::APBCLK0: UART13CKEN Position */ +#define CLK_APBCLK0_UART13CKEN_Msk (0x1ul << CLK_APBCLK0_UART13CKEN_Pos) /*!< CLK_T::APBCLK0: UART13CKEN Mask */ + +#define CLK_APBCLK0_UART14CKEN_Pos (26) /*!< CLK_T::APBCLK0: UART14CKEN Position */ +#define CLK_APBCLK0_UART14CKEN_Msk (0x1ul << CLK_APBCLK0_UART14CKEN_Pos) /*!< CLK_T::APBCLK0: UART14CKEN Mask */ + +#define CLK_APBCLK0_UART15CKEN_Pos (27) /*!< CLK_T::APBCLK0: UART15CKEN Position */ +#define CLK_APBCLK0_UART15CKEN_Msk (0x1ul << CLK_APBCLK0_UART15CKEN_Pos) /*!< CLK_T::APBCLK0: UART15CKEN Mask */ + +#define CLK_APBCLK0_UART16CKEN_Pos (28) /*!< CLK_T::APBCLK0: UART16CKEN Position */ +#define CLK_APBCLK0_UART16CKEN_Msk (0x1ul << CLK_APBCLK0_UART16CKEN_Pos) /*!< CLK_T::APBCLK0: UART16CKEN Mask */ + +#define CLK_APBCLK0_RTCCKEN_Pos (29) /*!< CLK_T::APBCLK0: RTCCKEN Position */ +#define CLK_APBCLK0_RTCCKEN_Msk (0x1ul << CLK_APBCLK0_RTCCKEN_Pos) /*!< CLK_T::APBCLK0: RTCCKEN Mask */ + +#define CLK_APBCLK0_DDRPCKEN_Pos (30) /*!< CLK_T::APBCLK0: DDRPCKEN Position */ +#define CLK_APBCLK0_DDRPCKEN_Msk (0x1ul << CLK_APBCLK0_DDRPCKEN_Pos) /*!< CLK_T::APBCLK0: DDRPCKEN Mask */ + +#define CLK_APBCLK0_KPICKEN_Pos (31) /*!< CLK_T::APBCLK0: KPICKEN Position */ +#define CLK_APBCLK0_KPICKEN_Msk (0x1ul << CLK_APBCLK0_KPICKEN_Pos) /*!< CLK_T::APBCLK0: KPICKEN Mask */ + +#define CLK_APBCLK1_I2C0CKEN_Pos (0) /*!< CLK_T::APBCLK1: I2C0CKEN Position */ +#define CLK_APBCLK1_I2C0CKEN_Msk (0x1ul << CLK_APBCLK1_I2C0CKEN_Pos) /*!< CLK_T::APBCLK1: I2C0CKEN Mask */ + +#define CLK_APBCLK1_I2C1CKEN_Pos (1) /*!< CLK_T::APBCLK1: I2C1CKEN Position */ +#define CLK_APBCLK1_I2C1CKEN_Msk (0x1ul << CLK_APBCLK1_I2C1CKEN_Pos) /*!< CLK_T::APBCLK1: I2C1CKEN Mask */ + +#define CLK_APBCLK1_I2C2CKEN_Pos (2) /*!< CLK_T::APBCLK1: I2C2CKEN Position */ +#define CLK_APBCLK1_I2C2CKEN_Msk (0x1ul << CLK_APBCLK1_I2C2CKEN_Pos) /*!< CLK_T::APBCLK1: I2C2CKEN Mask */ + +#define CLK_APBCLK1_I2C3CKEN_Pos (3) /*!< CLK_T::APBCLK1: I2C3CKEN Position */ +#define CLK_APBCLK1_I2C3CKEN_Msk (0x1ul << CLK_APBCLK1_I2C3CKEN_Pos) /*!< CLK_T::APBCLK1: I2C3CKEN Mask */ + +#define CLK_APBCLK1_I2C4CKEN_Pos (4) /*!< CLK_T::APBCLK1: I2C4CKEN Position */ +#define CLK_APBCLK1_I2C4CKEN_Msk (0x1ul << CLK_APBCLK1_I2C4CKEN_Pos) /*!< CLK_T::APBCLK1: I2C4CKEN Mask */ + +#define CLK_APBCLK1_I2C5CKEN_Pos (5) /*!< CLK_T::APBCLK1: I2C5CKEN Position */ +#define CLK_APBCLK1_I2C5CKEN_Msk (0x1ul << CLK_APBCLK1_I2C5CKEN_Pos) /*!< CLK_T::APBCLK1: I2C5CKEN Mask */ + +#define CLK_APBCLK1_QSPI0CKEN_Pos (6) /*!< CLK_T::APBCLK1: QSPI0CKEN Position */ +#define CLK_APBCLK1_QSPI0CKEN_Msk (0x1ul << CLK_APBCLK1_QSPI0CKEN_Pos) /*!< CLK_T::APBCLK1: QSPI0CKEN Mask */ + +#define CLK_APBCLK1_QSPI1CKEN_Pos (7) /*!< CLK_T::APBCLK1: QSPI1CKEN Position */ +#define CLK_APBCLK1_QSPI1CKEN_Msk (0x1ul << CLK_APBCLK1_QSPI1CKEN_Pos) /*!< CLK_T::APBCLK1: QSPI1CKEN Mask */ + +#define CLK_APBCLK1_SC0CKEN_Pos (12) /*!< CLK_T::APBCLK1: SC0CKEN Position */ +#define CLK_APBCLK1_SC0CKEN_Msk (0x1ul << CLK_APBCLK1_SC0CKEN_Pos) /*!< CLK_T::APBCLK1: SC0CKEN Mask */ + +#define CLK_APBCLK1_SC1CKEN_Pos (13) /*!< CLK_T::APBCLK1: SC1CKEN Position */ +#define CLK_APBCLK1_SC1CKEN_Msk (0x1ul << CLK_APBCLK1_SC1CKEN_Pos) /*!< CLK_T::APBCLK1: SC1CKEN Mask */ + +#define CLK_APBCLK1_WDT0CKEN_Pos (16) /*!< CLK_T::APBCLK1: WDT0CKEN Position */ +#define CLK_APBCLK1_WDT0CKEN_Msk (0x1ul << CLK_APBCLK1_WDT0CKEN_Pos) /*!< CLK_T::APBCLK1: WDT0CKEN Mask */ + +#define CLK_APBCLK1_WDT1CKEN_Pos (17) /*!< CLK_T::APBCLK1: WDT1CKEN Position */ +#define CLK_APBCLK1_WDT1CKEN_Msk (0x1ul << CLK_APBCLK1_WDT1CKEN_Pos) /*!< CLK_T::APBCLK1: WDT1CKEN Mask */ + +#define CLK_APBCLK1_WDT2CKEN_Pos (18) /*!< CLK_T::APBCLK1: WDT2CKEN Position */ +#define CLK_APBCLK1_WDT2CKEN_Msk (0x1ul << CLK_APBCLK1_WDT2CKEN_Pos) /*!< CLK_T::APBCLK1: WDT2CKEN Mask */ + +#define CLK_APBCLK1_EPWM0CKEN_Pos (24) /*!< CLK_T::APBCLK1: EPWM0CKEN Position */ +#define CLK_APBCLK1_EPWM0CKEN_Msk (0x1ul << CLK_APBCLK1_EPWM0CKEN_Pos) /*!< CLK_T::APBCLK1: EPWM0CKEN Mask */ + +#define CLK_APBCLK1_EPWM1CKEN_Pos (25) /*!< CLK_T::APBCLK1: EPWM1CKEN Position */ +#define CLK_APBCLK1_EPWM1CKEN_Msk (0x1ul << CLK_APBCLK1_EPWM1CKEN_Pos) /*!< CLK_T::APBCLK1: EPWM1CKEN Mask */ + +#define CLK_APBCLK1_EPWM2CKEN_Pos (26) /*!< CLK_T::APBCLK1: EPWM2CKEN Position */ +#define CLK_APBCLK1_EPWM2CKEN_Msk (0x1ul << CLK_APBCLK1_EPWM2CKEN_Pos) /*!< CLK_T::APBCLK1: EPWM2CKEN Mask */ + +#define CLK_APBCLK2_I2S0CKEN_Pos (0) /*!< CLK_T::APBCLK2: I2S0CKEN Position */ +#define CLK_APBCLK2_I2S0CKEN_Msk (0x1ul << CLK_APBCLK2_I2S0CKEN_Pos) /*!< CLK_T::APBCLK2: I2S0CKEN Mask */ + +#define CLK_APBCLK2_I2S1CKEN_Pos (1) /*!< CLK_T::APBCLK2: I2S1CKEN Position */ +#define CLK_APBCLK2_I2S1CKEN_Msk (0x1ul << CLK_APBCLK2_I2S1CKEN_Pos) /*!< CLK_T::APBCLK2: I2S1CKEN Mask */ + +#define CLK_APBCLK2_SSMCCEN_Pos (2) /*!< CLK_T::APBCLK2: SSMCCEN Position */ +#define CLK_APBCLK2_SSMCCEN_Msk (0x1ul << CLK_APBCLK2_SSMCCEN_Pos) /*!< CLK_T::APBCLK2: SSMCCEN Mask */ + +#define CLK_APBCLK2_SSPCCEN_Pos (3) /*!< CLK_T::APBCLK2: SSPCCEN Position */ +#define CLK_APBCLK2_SSPCCEN_Msk (0x1ul << CLK_APBCLK2_SSPCCEN_Pos) /*!< CLK_T::APBCLK2: SSPCCEN Mask */ + +#define CLK_APBCLK2_SPI0CKEN_Pos (4) /*!< CLK_T::APBCLK2: SPI0CKEN Position */ +#define CLK_APBCLK2_SPI0CKEN_Msk (0x1ul << CLK_APBCLK2_SPI0CKEN_Pos) /*!< CLK_T::APBCLK2: SPI0CKEN Mask */ + +#define CLK_APBCLK2_SPI1CKEN_Pos (5) /*!< CLK_T::APBCLK2: SPI1CKEN Position */ +#define CLK_APBCLK2_SPI1CKEN_Msk (0x1ul << CLK_APBCLK2_SPI1CKEN_Pos) /*!< CLK_T::APBCLK2: SPI1CKEN Mask */ + +#define CLK_APBCLK2_SPI2CKEN_Pos (6) /*!< CLK_T::APBCLK2: SPI2CKEN Position */ +#define CLK_APBCLK2_SPI2CKEN_Msk (0x1ul << CLK_APBCLK2_SPI2CKEN_Pos) /*!< CLK_T::APBCLK2: SPI2CKEN Mask */ + +#define CLK_APBCLK2_SPI3CKEN_Pos (7) /*!< CLK_T::APBCLK2: SPI3CKEN Position */ +#define CLK_APBCLK2_SPI3CKEN_Msk (0x1ul << CLK_APBCLK2_SPI3CKEN_Pos) /*!< CLK_T::APBCLK2: SPI3CKEN Mask */ + +#define CLK_APBCLK2_ECAP0CKEN_Pos (8) /*!< CLK_T::APBCLK2: ECAP0CKEN Position */ +#define CLK_APBCLK2_ECAP0CKEN_Msk (0x1ul << CLK_APBCLK2_ECAP0CKEN_Pos) /*!< CLK_T::APBCLK2: ECAP0CKEN Mask */ + +#define CLK_APBCLK2_ECAP1CKEN_Pos (9) /*!< CLK_T::APBCLK2: ECAP1CKEN Position */ +#define CLK_APBCLK2_ECAP1CKEN_Msk (0x1ul << CLK_APBCLK2_ECAP1CKEN_Pos) /*!< CLK_T::APBCLK2: ECAP1CKEN Mask */ + +#define CLK_APBCLK2_ECAP2CKEN_Pos (10) /*!< CLK_T::APBCLK2: ECAP2CKEN Position */ +#define CLK_APBCLK2_ECAP2CKEN_Msk (0x1ul << CLK_APBCLK2_ECAP2CKEN_Pos) /*!< CLK_T::APBCLK2: ECAP2CKEN Mask */ + +#define CLK_APBCLK2_QEI0CKEN_Pos (12) /*!< CLK_T::APBCLK2: QEI0CKEN Position */ +#define CLK_APBCLK2_QEI0CKEN_Msk (0x1ul << CLK_APBCLK2_QEI0CKEN_Pos) /*!< CLK_T::APBCLK2: QEI0CKEN Mask */ + +#define CLK_APBCLK2_QEI1CKEN_Pos (13) /*!< CLK_T::APBCLK2: QEI1CKEN Position */ +#define CLK_APBCLK2_QEI1CKEN_Msk (0x1ul << CLK_APBCLK2_QEI1CKEN_Pos) /*!< CLK_T::APBCLK2: QEI1CKEN Mask */ + +#define CLK_APBCLK2_QEI2CKEN_Pos (14) /*!< CLK_T::APBCLK2: QEI2CKEN Position */ +#define CLK_APBCLK2_QEI2CKEN_Msk (0x1ul << CLK_APBCLK2_QEI2CKEN_Pos) /*!< CLK_T::APBCLK2: QEI2CKEN Mask */ + +#define CLK_APBCLK2_ADCCKEN_Pos (24) /*!< CLK_T::APBCLK2: ADCCKEN Position */ +#define CLK_APBCLK2_ADCCKEN_Msk (0x1ul << CLK_APBCLK2_ADCCKEN_Pos) /*!< CLK_T::APBCLK2: ADCCKEN Mask */ + +#define CLK_APBCLK2_EADCCKEN_Pos (25) /*!< CLK_T::APBCLK2: EADCCKEN Position */ +#define CLK_APBCLK2_EADCCKEN_Msk (0x1ul << CLK_APBCLK2_EADCCKEN_Pos) /*!< CLK_T::APBCLK2: EADCCKEN Mask */ + +#define CLK_CLKSEL0_CA35CKSEL_Pos (0) /*!< CLK_T::CLKSEL0: CA35CKSEL Position */ +#define CLK_CLKSEL0_CA35CKSEL_Msk (0x3ul << CLK_CLKSEL0_CA35CKSEL_Pos) /*!< CLK_T::CLKSEL0: CA35CKSEL Mask */ + +#define CLK_CLKSEL0_SYSCK0SEL_Pos (2) /*!< CLK_T::CLKSEL0: SYSCK0SEL Position */ +#define CLK_CLKSEL0_SYSCK0SEL_Msk (0x1ul << CLK_CLKSEL0_SYSCK0SEL_Pos) /*!< CLK_T::CLKSEL0: SYSCK0SEL Mask */ + +#define CLK_CLKSEL0_LVRDBSEL_Pos (3) /*!< CLK_T::CLKSEL0: LVRDBSEL Position */ +#define CLK_CLKSEL0_LVRDBSEL_Msk (0x1ul << CLK_CLKSEL0_LVRDBSEL_Pos) /*!< CLK_T::CLKSEL0: LVRDBSEL Mask */ + +#define CLK_CLKSEL0_SYSCK1SEL_Pos (4) /*!< CLK_T::CLKSEL0: SYSCK1SEL Position */ +#define CLK_CLKSEL0_SYSCK1SEL_Msk (0x1ul << CLK_CLKSEL0_SYSCK1SEL_Pos) /*!< CLK_T::CLKSEL0: SYSCK1SEL Mask */ + +#define CLK_CLKSEL0_RTPSTSEL_Pos (8) /*!< CLK_T::CLKSEL0: RTPSTSEL Position */ +#define CLK_CLKSEL0_RTPSTSEL_Msk (0x7ul << CLK_CLKSEL0_RTPSTSEL_Pos) /*!< CLK_T::CLKSEL0: RTPSTSEL Mask */ + +#define CLK_CLKSEL0_CCAP0SEL_Pos (12) /*!< CLK_T::CLKSEL0: CCAP0SEL Position */ +#define CLK_CLKSEL0_CCAP0SEL_Msk (0x3ul << CLK_CLKSEL0_CCAP0SEL_Pos) /*!< CLK_T::CLKSEL0: CCAP0SEL Mask */ + +#define CLK_CLKSEL0_CCAP1SEL_Pos (14) /*!< CLK_T::CLKSEL0: CCAP1SEL Position */ +#define CLK_CLKSEL0_CCAP1SEL_Msk (0x3ul << CLK_CLKSEL0_CCAP1SEL_Pos) /*!< CLK_T::CLKSEL0: CCAP1SEL Mask */ + +#define CLK_CLKSEL0_SD0SEL_Pos (16) /*!< CLK_T::CLKSEL0: SD0SEL Position */ +#define CLK_CLKSEL0_SD0SEL_Msk (0x3ul << CLK_CLKSEL0_SD0SEL_Pos) /*!< CLK_T::CLKSEL0: SD0SEL Mask */ + +#define CLK_CLKSEL0_SD1SEL_Pos (18) /*!< CLK_T::CLKSEL0: SD1SEL Position */ +#define CLK_CLKSEL0_SD1SEL_Msk (0x3ul << CLK_CLKSEL0_SD1SEL_Pos) /*!< CLK_T::CLKSEL0: SD1SEL Mask */ + +#define CLK_CLKSEL0_DCUSEL_Pos (24) /*!< CLK_T::CLKSEL0: DCUSEL Position */ +#define CLK_CLKSEL0_DCUSEL_Msk (0x1ul << CLK_CLKSEL0_DCUSEL_Pos) /*!< CLK_T::CLKSEL0: DCUSEL Mask */ + +#define CLK_CLKSEL0_GFXSEL_Pos (26) /*!< CLK_T::CLKSEL0: GFXSEL Position */ +#define CLK_CLKSEL0_GFXSEL_Msk (0x1ul << CLK_CLKSEL0_GFXSEL_Pos) /*!< CLK_T::CLKSEL0: GFXSEL Mask */ + +#define CLK_CLKSEL0_DBGSEL_Pos (27) /*!< CLK_T::CLKSEL0: DBGSEL Position */ +#define CLK_CLKSEL0_DBGSEL_Msk (0x1ul << CLK_CLKSEL0_DBGSEL_Pos) /*!< CLK_T::CLKSEL0: DBGSEL Mask */ + +#define CLK_CLKSEL1_TMR0SEL_Pos (0) /*!< CLK_T::CLKSEL1: TMR0SEL Position */ +#define CLK_CLKSEL1_TMR0SEL_Msk (0x7ul << CLK_CLKSEL1_TMR0SEL_Pos) /*!< CLK_T::CLKSEL1: TMR0SEL Mask */ + +#define CLK_CLKSEL1_TMR1SEL_Pos (4) /*!< CLK_T::CLKSEL1: TMR1SEL Position */ +#define CLK_CLKSEL1_TMR1SEL_Msk (0x7ul << CLK_CLKSEL1_TMR1SEL_Pos) /*!< CLK_T::CLKSEL1: TMR1SEL Mask */ + +#define CLK_CLKSEL1_TMR2SEL_Pos (8) /*!< CLK_T::CLKSEL1: TMR2SEL Position */ +#define CLK_CLKSEL1_TMR2SEL_Msk (0x7ul << CLK_CLKSEL1_TMR2SEL_Pos) /*!< CLK_T::CLKSEL1: TMR2SEL Mask */ + +#define CLK_CLKSEL1_TMR3SEL_Pos (12) /*!< CLK_T::CLKSEL1: TMR3SEL Position */ +#define CLK_CLKSEL1_TMR3SEL_Msk (0x7ul << CLK_CLKSEL1_TMR3SEL_Pos) /*!< CLK_T::CLKSEL1: TMR3SEL Mask */ + +#define CLK_CLKSEL1_TMR4SEL_Pos (16) /*!< CLK_T::CLKSEL1: TMR4SEL Position */ +#define CLK_CLKSEL1_TMR4SEL_Msk (0x7ul << CLK_CLKSEL1_TMR4SEL_Pos) /*!< CLK_T::CLKSEL1: TMR4SEL Mask */ + +#define CLK_CLKSEL1_TMR5SEL_Pos (20) /*!< CLK_T::CLKSEL1: TMR5SEL Position */ +#define CLK_CLKSEL1_TMR5SEL_Msk (0x7ul << CLK_CLKSEL1_TMR5SEL_Pos) /*!< CLK_T::CLKSEL1: TMR5SEL Mask */ + +#define CLK_CLKSEL1_TMR6SEL_Pos (24) /*!< CLK_T::CLKSEL1: TMR6SEL Position */ +#define CLK_CLKSEL1_TMR6SEL_Msk (0x7ul << CLK_CLKSEL1_TMR6SEL_Pos) /*!< CLK_T::CLKSEL1: TMR6SEL Mask */ + +#define CLK_CLKSEL1_TMR7SEL_Pos (28) /*!< CLK_T::CLKSEL1: TMR7SEL Position */ +#define CLK_CLKSEL1_TMR7SEL_Msk (0x7ul << CLK_CLKSEL1_TMR7SEL_Pos) /*!< CLK_T::CLKSEL1: TMR7SEL Mask */ + +#define CLK_CLKSEL2_TMR8SEL_Pos (0) /*!< CLK_T::CLKSEL2: TMR8SEL Position */ +#define CLK_CLKSEL2_TMR8SEL_Msk (0x7ul << CLK_CLKSEL2_TMR8SEL_Pos) /*!< CLK_T::CLKSEL2: TMR8SEL Mask */ + +#define CLK_CLKSEL2_TMR9SEL_Pos (4) /*!< CLK_T::CLKSEL2: TMR9SEL Position */ +#define CLK_CLKSEL2_TMR9SEL_Msk (0x7ul << CLK_CLKSEL2_TMR9SEL_Pos) /*!< CLK_T::CLKSEL2: TMR9SEL Mask */ + +#define CLK_CLKSEL2_TMR10SEL_Pos (8) /*!< CLK_T::CLKSEL2: TMR10SEL Position */ +#define CLK_CLKSEL2_TMR10SEL_Msk (0x7ul << CLK_CLKSEL2_TMR10SEL_Pos) /*!< CLK_T::CLKSEL2: TMR10SEL Mask */ + +#define CLK_CLKSEL2_TMR11SEL_Pos (12) /*!< CLK_T::CLKSEL2: TMR11SEL Position */ +#define CLK_CLKSEL2_TMR11SEL_Msk (0x7ul << CLK_CLKSEL2_TMR11SEL_Pos) /*!< CLK_T::CLKSEL2: TMR11SEL Mask */ + +#define CLK_CLKSEL2_UART0SEL_Pos (16) /*!< CLK_T::CLKSEL2: UART0SEL Position */ +#define CLK_CLKSEL2_UART0SEL_Msk (0x3ul << CLK_CLKSEL2_UART0SEL_Pos) /*!< CLK_T::CLKSEL2: UART0SEL Mask */ + +#define CLK_CLKSEL2_UART1SEL_Pos (18) /*!< CLK_T::CLKSEL2: UART1SEL Position */ +#define CLK_CLKSEL2_UART1SEL_Msk (0x3ul << CLK_CLKSEL2_UART1SEL_Pos) /*!< CLK_T::CLKSEL2: UART1SEL Mask */ + +#define CLK_CLKSEL2_UART2SEL_Pos (20) /*!< CLK_T::CLKSEL2: UART2SEL Position */ +#define CLK_CLKSEL2_UART2SEL_Msk (0x3ul << CLK_CLKSEL2_UART2SEL_Pos) /*!< CLK_T::CLKSEL2: UART2SEL Mask */ + +#define CLK_CLKSEL2_UART3SEL_Pos (22) /*!< CLK_T::CLKSEL2: UART3SEL Position */ +#define CLK_CLKSEL2_UART3SEL_Msk (0x3ul << CLK_CLKSEL2_UART3SEL_Pos) /*!< CLK_T::CLKSEL2: UART3SEL Mask */ + +#define CLK_CLKSEL2_UART4SEL_Pos (24) /*!< CLK_T::CLKSEL2: UART4SEL Position */ +#define CLK_CLKSEL2_UART4SEL_Msk (0x3ul << CLK_CLKSEL2_UART4SEL_Pos) /*!< CLK_T::CLKSEL2: UART4SEL Mask */ + +#define CLK_CLKSEL2_UART5SEL_Pos (26) /*!< CLK_T::CLKSEL2: UART5SEL Position */ +#define CLK_CLKSEL2_UART5SEL_Msk (0x3ul << CLK_CLKSEL2_UART5SEL_Pos) /*!< CLK_T::CLKSEL2: UART5SEL Mask */ + +#define CLK_CLKSEL2_UART6SEL_Pos (28) /*!< CLK_T::CLKSEL2: UART6SEL Position */ +#define CLK_CLKSEL2_UART6SEL_Msk (0x3ul << CLK_CLKSEL2_UART6SEL_Pos) /*!< CLK_T::CLKSEL2: UART6SEL Mask */ + +#define CLK_CLKSEL2_UART7SEL_Pos (30) /*!< CLK_T::CLKSEL2: UART7SEL Position */ +#define CLK_CLKSEL2_UART7SEL_Msk (0x3ul << CLK_CLKSEL2_UART7SEL_Pos) /*!< CLK_T::CLKSEL2: UART7SEL Mask */ + +#define CLK_CLKSEL3_UART8SEL_Pos (0) /*!< CLK_T::CLKSEL3: UART8SEL Position */ +#define CLK_CLKSEL3_UART8SEL_Msk (0x3ul << CLK_CLKSEL3_UART8SEL_Pos) /*!< CLK_T::CLKSEL3: UART8SEL Mask */ + +#define CLK_CLKSEL3_UART9SEL_Pos (2) /*!< CLK_T::CLKSEL3: UART9SEL Position */ +#define CLK_CLKSEL3_UART9SEL_Msk (0x3ul << CLK_CLKSEL3_UART9SEL_Pos) /*!< CLK_T::CLKSEL3: UART9SEL Mask */ + +#define CLK_CLKSEL3_UART10SEL_Pos (4) /*!< CLK_T::CLKSEL3: UART10SEL Position */ +#define CLK_CLKSEL3_UART10SEL_Msk (0x3ul << CLK_CLKSEL3_UART10SEL_Pos) /*!< CLK_T::CLKSEL3: UART10SEL Mask */ + +#define CLK_CLKSEL3_UART11SEL_Pos (6) /*!< CLK_T::CLKSEL3: UART11SEL Position */ +#define CLK_CLKSEL3_UART11SEL_Msk (0x3ul << CLK_CLKSEL3_UART11SEL_Pos) /*!< CLK_T::CLKSEL3: UART11SEL Mask */ + +#define CLK_CLKSEL3_UART12SEL_Pos (8) /*!< CLK_T::CLKSEL3: UART12SEL Position */ +#define CLK_CLKSEL3_UART12SEL_Msk (0x3ul << CLK_CLKSEL3_UART12SEL_Pos) /*!< CLK_T::CLKSEL3: UART12SEL Mask */ + +#define CLK_CLKSEL3_UART13SEL_Pos (10) /*!< CLK_T::CLKSEL3: UART13SEL Position */ +#define CLK_CLKSEL3_UART13SEL_Msk (0x3ul << CLK_CLKSEL3_UART13SEL_Pos) /*!< CLK_T::CLKSEL3: UART13SEL Mask */ + +#define CLK_CLKSEL3_UART14SEL_Pos (12) /*!< CLK_T::CLKSEL3: UART14SEL Position */ +#define CLK_CLKSEL3_UART14SEL_Msk (0x3ul << CLK_CLKSEL3_UART14SEL_Pos) /*!< CLK_T::CLKSEL3: UART14SEL Mask */ + +#define CLK_CLKSEL3_UART15SEL_Pos (14) /*!< CLK_T::CLKSEL3: UART15SEL Position */ +#define CLK_CLKSEL3_UART15SEL_Msk (0x3ul << CLK_CLKSEL3_UART15SEL_Pos) /*!< CLK_T::CLKSEL3: UART15SEL Mask */ + +#define CLK_CLKSEL3_UART16SEL_Pos (16) /*!< CLK_T::CLKSEL3: UART16SEL Position */ +#define CLK_CLKSEL3_UART16SEL_Msk (0x3ul << CLK_CLKSEL3_UART16SEL_Pos) /*!< CLK_T::CLKSEL3: UART16SEL Mask */ + +#define CLK_CLKSEL3_WDT0SEL_Pos (20) /*!< CLK_T::CLKSEL3: WDT0SEL Position */ +#define CLK_CLKSEL3_WDT0SEL_Msk (0x3ul << CLK_CLKSEL3_WDT0SEL_Pos) /*!< CLK_T::CLKSEL3: WDT0SEL Mask */ + +#define CLK_CLKSEL3_WWDT0SEL_Pos (22) /*!< CLK_T::CLKSEL3: WWDT0SEL Position */ +#define CLK_CLKSEL3_WWDT0SEL_Msk (0x3ul << CLK_CLKSEL3_WWDT0SEL_Pos) /*!< CLK_T::CLKSEL3: WWDT0SEL Mask */ + +#define CLK_CLKSEL3_WDT1SEL_Pos (24) /*!< CLK_T::CLKSEL3: WDT1SEL Position */ +#define CLK_CLKSEL3_WDT1SEL_Msk (0x3ul << CLK_CLKSEL3_WDT1SEL_Pos) /*!< CLK_T::CLKSEL3: WDT1SEL Mask */ + +#define CLK_CLKSEL3_WWDT1SEL_Pos (26) /*!< CLK_T::CLKSEL3: WWDT1SEL Position */ +#define CLK_CLKSEL3_WWDT1SEL_Msk (0x3ul << CLK_CLKSEL3_WWDT1SEL_Pos) /*!< CLK_T::CLKSEL3: WWDT1SEL Mask */ + +#define CLK_CLKSEL3_WDT2SEL_Pos (28) /*!< CLK_T::CLKSEL3: WDT2SEL Position */ +#define CLK_CLKSEL3_WDT2SEL_Msk (0x3ul << CLK_CLKSEL3_WDT2SEL_Pos) /*!< CLK_T::CLKSEL3: WDT2SEL Mask */ + +#define CLK_CLKSEL3_WWDT2SEL_Pos (30) /*!< CLK_T::CLKSEL3: WWDT2SEL Position */ +#define CLK_CLKSEL3_WWDT2SEL_Msk (0x3ul << CLK_CLKSEL3_WWDT2SEL_Pos) /*!< CLK_T::CLKSEL3: WWDT2SEL Mask */ + +#define CLK_CLKSEL4_SPI0SEL_Pos (0) /*!< CLK_T::CLKSEL4: SPI0SEL Position */ +#define CLK_CLKSEL4_SPI0SEL_Msk (0x3ul << CLK_CLKSEL4_SPI0SEL_Pos) /*!< CLK_T::CLKSEL4: SPI0SEL Mask */ + +#define CLK_CLKSEL4_SPI1SEL_Pos (2) /*!< CLK_T::CLKSEL4: SPI1SEL Position */ +#define CLK_CLKSEL4_SPI1SEL_Msk (0x3ul << CLK_CLKSEL4_SPI1SEL_Pos) /*!< CLK_T::CLKSEL4: SPI1SEL Mask */ + +#define CLK_CLKSEL4_SPI2SEL_Pos (4) /*!< CLK_T::CLKSEL4: SPI2SEL Position */ +#define CLK_CLKSEL4_SPI2SEL_Msk (0x3ul << CLK_CLKSEL4_SPI2SEL_Pos) /*!< CLK_T::CLKSEL4: SPI2SEL Mask */ + +#define CLK_CLKSEL4_SPI3SEL_Pos (6) /*!< CLK_T::CLKSEL4: SPI3SEL Position */ +#define CLK_CLKSEL4_SPI3SEL_Msk (0x3ul << CLK_CLKSEL4_SPI3SEL_Pos) /*!< CLK_T::CLKSEL4: SPI3SEL Mask */ + +#define CLK_CLKSEL4_QSPI0SEL_Pos (8) /*!< CLK_T::CLKSEL4: QSPI0SEL Position */ +#define CLK_CLKSEL4_QSPI0SEL_Msk (0x3ul << CLK_CLKSEL4_QSPI0SEL_Pos) /*!< CLK_T::CLKSEL4: QSPI0SEL Mask */ + +#define CLK_CLKSEL4_QSPI1SEL_Pos (10) /*!< CLK_T::CLKSEL4: QSPI1SEL Position */ +#define CLK_CLKSEL4_QSPI1SEL_Msk (0x3ul << CLK_CLKSEL4_QSPI1SEL_Pos) /*!< CLK_T::CLKSEL4: QSPI1SEL Mask */ + +#define CLK_CLKSEL4_I2S0SEL_Pos (12) /*!< CLK_T::CLKSEL4: I2S0SEL Position */ +#define CLK_CLKSEL4_I2S0SEL_Msk (0x3ul << CLK_CLKSEL4_I2S0SEL_Pos) /*!< CLK_T::CLKSEL4: I2S0SEL Mask */ + +#define CLK_CLKSEL4_I2S1SEL_Pos (14) /*!< CLK_T::CLKSEL4: I2S1SEL Position */ +#define CLK_CLKSEL4_I2S1SEL_Msk (0x3ul << CLK_CLKSEL4_I2S1SEL_Pos) /*!< CLK_T::CLKSEL4: I2S1SEL Mask */ + +#define CLK_CLKSEL4_CANFD0SEL_Pos (16) /*!< CLK_T::CLKSEL4: CANFD0SEL Position */ +#define CLK_CLKSEL4_CANFD0SEL_Msk (0x1ul << CLK_CLKSEL4_CANFD0SEL_Pos) /*!< CLK_T::CLKSEL4: CANFD0SEL Mask */ + +#define CLK_CLKSEL4_CANFD1SEL_Pos (17) /*!< CLK_T::CLKSEL4: CANFD1SEL Position */ +#define CLK_CLKSEL4_CANFD1SEL_Msk (0x1ul << CLK_CLKSEL4_CANFD1SEL_Pos) /*!< CLK_T::CLKSEL4: CANFD1SEL Mask */ + +#define CLK_CLKSEL4_CANFD2SEL_Pos (18) /*!< CLK_T::CLKSEL4: CANFD2SEL Position */ +#define CLK_CLKSEL4_CANFD2SEL_Msk (0x1ul << CLK_CLKSEL4_CANFD2SEL_Pos) /*!< CLK_T::CLKSEL4: CANFD2SEL Mask */ + +#define CLK_CLKSEL4_CANFD3SEL_Pos (19) /*!< CLK_T::CLKSEL4: CANFD3SEL Position */ +#define CLK_CLKSEL4_CANFD3SEL_Msk (0x1ul << CLK_CLKSEL4_CANFD3SEL_Pos) /*!< CLK_T::CLKSEL4: CANFD3SEL Mask */ + +#define CLK_CLKSEL4_CKOSEL_Pos (24) /*!< CLK_T::CLKSEL4: CKOSEL Position */ +#define CLK_CLKSEL4_CKOSEL_Msk (0xful << CLK_CLKSEL4_CKOSEL_Pos) /*!< CLK_T::CLKSEL4: CKOSEL Mask */ + +#define CLK_CLKSEL4_SC0SEL_Pos (28) /*!< CLK_T::CLKSEL4: SC0SEL Position */ +#define CLK_CLKSEL4_SC0SEL_Msk (0x1ul << CLK_CLKSEL4_SC0SEL_Pos) /*!< CLK_T::CLKSEL4: SC0SEL Mask */ + +#define CLK_CLKSEL4_SC1SEL_Pos (29) /*!< CLK_T::CLKSEL4: SC1SEL Position */ +#define CLK_CLKSEL4_SC1SEL_Msk (0x1ul << CLK_CLKSEL4_SC1SEL_Pos) /*!< CLK_T::CLKSEL4: SC1SEL Mask */ + +#define CLK_CLKSEL4_KPISEL_Pos (30) /*!< CLK_T::CLKSEL4: KPISEL Position */ +#define CLK_CLKSEL4_KPISEL_Msk (0x1ul << CLK_CLKSEL4_KPISEL_Pos) /*!< CLK_T::CLKSEL4: KPISEL Mask */ + +#define CLK_CLKDIV0_CANFD0DIV_Pos (0) /*!< CLK_T::CLKDIV0: CANFD0DIV Position */ +#define CLK_CLKDIV0_CANFD0DIV_Msk (0x7ul << CLK_CLKDIV0_CANFD0DIV_Pos) /*!< CLK_T::CLKDIV0: CANFD0DIV Mask */ + +#define CLK_CLKDIV0_CANFD1DIV_Pos (4) /*!< CLK_T::CLKDIV0: CANFD1DIV Position */ +#define CLK_CLKDIV0_CANFD1DIV_Msk (0x7ul << CLK_CLKDIV0_CANFD1DIV_Pos) /*!< CLK_T::CLKDIV0: CANFD1DIV Mask */ + +#define CLK_CLKDIV0_CANFD2DIV_Pos (8) /*!< CLK_T::CLKDIV0: CANFD2DIV Position */ +#define CLK_CLKDIV0_CANFD2DIV_Msk (0x7ul << CLK_CLKDIV0_CANFD2DIV_Pos) /*!< CLK_T::CLKDIV0: CANFD2DIV Mask */ + +#define CLK_CLKDIV0_CANFD3DIV_Pos (12) /*!< CLK_T::CLKDIV0: CANFD3DIV Position */ +#define CLK_CLKDIV0_CANFD3DIV_Msk (0x7ul << CLK_CLKDIV0_CANFD3DIV_Pos) /*!< CLK_T::CLKDIV0: CANFD3DIV Mask */ + +#define CLK_CLKDIV0_DCUPDIV_Pos (16) /*!< CLK_T::CLKDIV0: DCUPDIV Position */ +#define CLK_CLKDIV0_DCUPDIV_Msk (0x7ul << CLK_CLKDIV0_DCUPDIV_Pos) /*!< CLK_T::CLKDIV0: DCUPDIV Mask */ + +#define CLK_CLKDIV0_ACLK0DIV_Pos (26) /*!< CLK_T::CLKDIV0: ACLK0DIV Position */ +#define CLK_CLKDIV0_ACLK0DIV_Msk (0x1ul << CLK_CLKDIV0_ACLK0DIV_Pos) /*!< CLK_T::CLKDIV0: ACLK0DIV Mask */ + +#define CLK_CLKDIV0_EMAC0DIV_Pos (28) /*!< CLK_T::CLKDIV0: EMAC0DIV Position */ +#define CLK_CLKDIV0_EMAC0DIV_Msk (0x3ul << CLK_CLKDIV0_EMAC0DIV_Pos) /*!< CLK_T::CLKDIV0: EMAC0DIV Mask */ + +#define CLK_CLKDIV0_EMAC1DIV_Pos (30) /*!< CLK_T::CLKDIV0: EMAC1DIV Position */ +#define CLK_CLKDIV0_EMAC1DIV_Msk (0x3ul << CLK_CLKDIV0_EMAC1DIV_Pos) /*!< CLK_T::CLKDIV0: EMAC1DIV Mask */ + +#define CLK_CLKDIV1_SC0DIV_Pos (0) /*!< CLK_T::CLKDIV1: SC0DIV Position */ +#define CLK_CLKDIV1_SC0DIV_Msk (0xful << CLK_CLKDIV1_SC0DIV_Pos) /*!< CLK_T::CLKDIV1: SC0DIV Mask */ + +#define CLK_CLKDIV1_SC1DIV_Pos (4) /*!< CLK_T::CLKDIV1: SC1DIV Position */ +#define CLK_CLKDIV1_SC1DIV_Msk (0xful << CLK_CLKDIV1_SC1DIV_Pos) /*!< CLK_T::CLKDIV1: SC1DIV Mask */ + +#define CLK_CLKDIV1_CCAP0DIV_Pos (8) /*!< CLK_T::CLKDIV1: CCAP0DIV Position */ +#define CLK_CLKDIV1_CCAP0DIV_Msk (0xful << CLK_CLKDIV1_CCAP0DIV_Pos) /*!< CLK_T::CLKDIV1: CCAP0DIV Mask */ + +#define CLK_CLKDIV1_CCAP1DIV_Pos (12) /*!< CLK_T::CLKDIV1: CCAP1DIV Position */ +#define CLK_CLKDIV1_CCAP1DIV_Msk (0xful << CLK_CLKDIV1_CCAP1DIV_Pos) /*!< CLK_T::CLKDIV1: CCAP1DIV Mask */ + +#define CLK_CLKDIV1_UART0DIV_Pos (16) /*!< CLK_T::CLKDIV1: UART0DIV Position */ +#define CLK_CLKDIV1_UART0DIV_Msk (0xful << CLK_CLKDIV1_UART0DIV_Pos) /*!< CLK_T::CLKDIV1: UART0DIV Mask */ + +#define CLK_CLKDIV1_UART1DIV_Pos (20) /*!< CLK_T::CLKDIV1: UART1DIV Position */ +#define CLK_CLKDIV1_UART1DIV_Msk (0xful << CLK_CLKDIV1_UART1DIV_Pos) /*!< CLK_T::CLKDIV1: UART1DIV Mask */ + +#define CLK_CLKDIV1_UART2DIV_Pos (24) /*!< CLK_T::CLKDIV1: UART2DIV Position */ +#define CLK_CLKDIV1_UART2DIV_Msk (0xful << CLK_CLKDIV1_UART2DIV_Pos) /*!< CLK_T::CLKDIV1: UART2DIV Mask */ + +#define CLK_CLKDIV1_UART3DIV_Pos (28) /*!< CLK_T::CLKDIV1: UART3DIV Position */ +#define CLK_CLKDIV1_UART3DIV_Msk (0xful << CLK_CLKDIV1_UART3DIV_Pos) /*!< CLK_T::CLKDIV1: UART3DIV Mask */ + +#define CLK_CLKDIV2_UART4DIV_Pos (0) /*!< CLK_T::CLKDIV2: UART4DIV Position */ +#define CLK_CLKDIV2_UART4DIV_Msk (0xful << CLK_CLKDIV2_UART4DIV_Pos) /*!< CLK_T::CLKDIV2: UART4DIV Mask */ + +#define CLK_CLKDIV2_UART5DIV_Pos (4) /*!< CLK_T::CLKDIV2: UART5DIV Position */ +#define CLK_CLKDIV2_UART5DIV_Msk (0xful << CLK_CLKDIV2_UART5DIV_Pos) /*!< CLK_T::CLKDIV2: UART5DIV Mask */ + +#define CLK_CLKDIV2_UART6DIV_Pos (8) /*!< CLK_T::CLKDIV2: UART6DIV Position */ +#define CLK_CLKDIV2_UART6DIV_Msk (0xful << CLK_CLKDIV2_UART6DIV_Pos) /*!< CLK_T::CLKDIV2: UART6DIV Mask */ + +#define CLK_CLKDIV2_UART7DIV_Pos (12) /*!< CLK_T::CLKDIV2: UART7DIV Position */ +#define CLK_CLKDIV2_UART7DIV_Msk (0xful << CLK_CLKDIV2_UART7DIV_Pos) /*!< CLK_T::CLKDIV2: UART7DIV Mask */ + +#define CLK_CLKDIV2_UART8DIV_Pos (16) /*!< CLK_T::CLKDIV2: UART8DIV Position */ +#define CLK_CLKDIV2_UART8DIV_Msk (0xful << CLK_CLKDIV2_UART8DIV_Pos) /*!< CLK_T::CLKDIV2: UART8DIV Mask */ + +#define CLK_CLKDIV2_UART9DIV_Pos (20) /*!< CLK_T::CLKDIV2: UART9DIV Position */ +#define CLK_CLKDIV2_UART9DIV_Msk (0xful << CLK_CLKDIV2_UART9DIV_Pos) /*!< CLK_T::CLKDIV2: UART9DIV Mask */ + +#define CLK_CLKDIV2_UART10DIV_Pos (24) /*!< CLK_T::CLKDIV2: UART10DIV Position */ +#define CLK_CLKDIV2_UART10DIV_Msk (0xful << CLK_CLKDIV2_UART10DIV_Pos) /*!< CLK_T::CLKDIV2: UART10DIV Mask */ + +#define CLK_CLKDIV2_UART11DIV_Pos (28) /*!< CLK_T::CLKDIV2: UART11DIV Position */ +#define CLK_CLKDIV2_UART11DIV_Msk (0xful << CLK_CLKDIV2_UART11DIV_Pos) /*!< CLK_T::CLKDIV2: UART11DIV Mask */ + +#define CLK_CLKDIV3_UART12DIV_Pos (0) /*!< CLK_T::CLKDIV3: UART12DIV Position */ +#define CLK_CLKDIV3_UART12DIV_Msk (0xful << CLK_CLKDIV3_UART12DIV_Pos) /*!< CLK_T::CLKDIV3: UART12DIV Mask */ + +#define CLK_CLKDIV3_UART13DIV_Pos (4) /*!< CLK_T::CLKDIV3: UART13DIV Position */ +#define CLK_CLKDIV3_UART13DIV_Msk (0xful << CLK_CLKDIV3_UART13DIV_Pos) /*!< CLK_T::CLKDIV3: UART13DIV Mask */ + +#define CLK_CLKDIV3_UART14DIV_Pos (8) /*!< CLK_T::CLKDIV3: UART14DIV Position */ +#define CLK_CLKDIV3_UART14DIV_Msk (0xful << CLK_CLKDIV3_UART14DIV_Pos) /*!< CLK_T::CLKDIV3: UART14DIV Mask */ + +#define CLK_CLKDIV3_UART15DIV_Pos (12) /*!< CLK_T::CLKDIV3: UART15DIV Position */ +#define CLK_CLKDIV3_UART15DIV_Msk (0xful << CLK_CLKDIV3_UART15DIV_Pos) /*!< CLK_T::CLKDIV3: UART15DIV Mask */ + +#define CLK_CLKDIV3_UART16DIV_Pos (16) /*!< CLK_T::CLKDIV3: UART16DIV Position */ +#define CLK_CLKDIV3_UART16DIV_Msk (0xful << CLK_CLKDIV3_UART16DIV_Pos) /*!< CLK_T::CLKDIV3: UART16DIV Mask */ + +#define CLK_CLKDIV4_EADCDIV_Pos (0) /*!< CLK_T::CLKDIV4: EADCDIV Position */ +#define CLK_CLKDIV4_EADCDIV_Msk (0xful << CLK_CLKDIV4_EADCDIV_Pos) /*!< CLK_T::CLKDIV4: EADCDIV Mask */ + +#define CLK_CLKDIV4_ADCDIV_Pos (4) /*!< CLK_T::CLKDIV4: ADCDIV Position */ +#define CLK_CLKDIV4_ADCDIV_Msk (0x1fffful << CLK_CLKDIV4_ADCDIV_Pos) /*!< CLK_T::CLKDIV4: ADCDIV Mask */ + +#define CLK_CLKDIV4_KPIDIV_Pos (24) /*!< CLK_T::CLKDIV4: KPIDIV Position */ +#define CLK_CLKDIV4_KPIDIV_Msk (0xfful << CLK_CLKDIV4_KPIDIV_Pos) /*!< CLK_T::CLKDIV4: KPIDIV Mask */ + +#define CLK_CLKOCTL_FREQSEL_Pos (0) /*!< CLK_T::CLKOCTL: FREQSEL Position */ +#define CLK_CLKOCTL_FREQSEL_Msk (0xful << CLK_CLKOCTL_FREQSEL_Pos) /*!< CLK_T::CLKOCTL: FREQSEL Mask */ + +#define CLK_CLKOCTL_CLKOEN_Pos (4) /*!< CLK_T::CLKOCTL: CLKOEN Position */ +#define CLK_CLKOCTL_CLKOEN_Msk (0x1ul << CLK_CLKOCTL_CLKOEN_Pos) /*!< CLK_T::CLKOCTL: CLKOEN Mask */ + +#define CLK_CLKOCTL_DIV1EN_Pos (5) /*!< CLK_T::CLKOCTL: DIV1EN Position */ +#define CLK_CLKOCTL_DIV1EN_Msk (0x1ul << CLK_CLKOCTL_DIV1EN_Pos) /*!< CLK_T::CLKOCTL: DIV1EN Mask */ + +#define CLK_STATUS_HXTSTB_Pos (0) /*!< CLK_T::STATUS: HXTSTB Position */ +#define CLK_STATUS_HXTSTB_Msk (0x1ul << CLK_STATUS_HXTSTB_Pos) /*!< CLK_T::STATUS: HXTSTB Mask */ + +#define CLK_STATUS_LXTSTB_Pos (1) /*!< CLK_T::STATUS: LXTSTB Position */ +#define CLK_STATUS_LXTSTB_Msk (0x1ul << CLK_STATUS_LXTSTB_Pos) /*!< CLK_T::STATUS: LXTSTB Mask */ + +#define CLK_STATUS_SYSPLLSTB_Pos (2) /*!< CLK_T::STATUS: SYSPLLSTB Position */ +#define CLK_STATUS_SYSPLLSTB_Msk (0x1ul << CLK_STATUS_SYSPLLSTB_Pos) /*!< CLK_T::STATUS: SYSPLLSTB Mask */ + +#define CLK_STATUS_LIRCSTB_Pos (3) /*!< CLK_T::STATUS: LIRCSTB Position */ +#define CLK_STATUS_LIRCSTB_Msk (0x1ul << CLK_STATUS_LIRCSTB_Pos) /*!< CLK_T::STATUS: LIRCSTB Mask */ + +#define CLK_STATUS_HIRCSTB_Pos (4) /*!< CLK_T::STATUS: HIRCSTB Position */ +#define CLK_STATUS_HIRCSTB_Msk (0x1ul << CLK_STATUS_HIRCSTB_Pos) /*!< CLK_T::STATUS: HIRCSTB Mask */ + +#define CLK_STATUS_CAPLLSTB_Pos (6) /*!< CLK_T::STATUS: CAPLLSTB Position */ +#define CLK_STATUS_CAPLLSTB_Msk (0x1ul << CLK_STATUS_CAPLLSTB_Pos) /*!< CLK_T::STATUS: CAPLLSTB Mask */ + +#define CLK_STATUS_DDRPLLSTB_Pos (8) /*!< CLK_T::STATUS: DDRPLLSTB Position */ +#define CLK_STATUS_DDRPLLSTB_Msk (0x1ul << CLK_STATUS_DDRPLLSTB_Pos) /*!< CLK_T::STATUS: DDRPLLSTB Mask */ + +#define CLK_STATUS_EPLLSTB_Pos (9) /*!< CLK_T::STATUS: EPLLSTB Position */ +#define CLK_STATUS_EPLLSTB_Msk (0x1ul << CLK_STATUS_EPLLSTB_Pos) /*!< CLK_T::STATUS: EPLLSTB Mask */ + +#define CLK_STATUS_APLLSTB_Pos (10) /*!< CLK_T::STATUS: APLLSTB Position */ +#define CLK_STATUS_APLLSTB_Msk (0x1ul << CLK_STATUS_APLLSTB_Pos) /*!< CLK_T::STATUS: APLLSTB Mask */ + +#define CLK_STATUS_VPLLSTB_Pos (11) /*!< CLK_T::STATUS: VPLLSTB Position */ +#define CLK_STATUS_VPLLSTB_Msk (0x1ul << CLK_STATUS_VPLLSTB_Pos) /*!< CLK_T::STATUS: VPLLSTB Mask */ + +#define CLK_PLL0CTL0_FBDIV_Pos (0) /*!< CLK_T::PLL0CTL0: FBDIV Position */ +#define CLK_PLL0CTL0_FBDIV_Msk (0xfful << CLK_PLL0CTL0_FBDIV_Pos) /*!< CLK_T::PLL0CTL0: FBDIV Mask */ + +#define CLK_PLL0CTL0_INDIV_Pos (8) /*!< CLK_T::PLL0CTL0: INDIV Position */ +#define CLK_PLL0CTL0_INDIV_Msk (0xful << CLK_PLL0CTL0_INDIV_Pos) /*!< CLK_T::PLL0CTL0: INDIV Mask */ + +#define CLK_PLL0CTL0_OUTDIV_Pos (12) /*!< CLK_T::PLL0CTL0: MODE Position */ +#define CLK_PLL0CTL0_OUTDIV_Msk (0x3ul << CLK_PLL0CTL0_OUTDIV_Pos) /*!< CLK_T::PLL0CTL0: MODE Mask */ + +#define CLK_PLL0CTL0_PD_Pos (16) /*!< CLK_T::PLL0CTL0: PD Position */ +#define CLK_PLL0CTL0_PD_Msk (0x1ul << CLK_PLL0CTL0_PD_Pos) /*!< CLK_T::PLL0CTL0: PD Mask */ + +#define CLK_PLL0CTL0_BP_Pos (17) /*!< CLK_T::PLL0CTL0: BP Position */ +#define CLK_PLL0CTL0_BP_Msk (0x1ul << CLK_PLL0CTL0_BP_Pos) /*!< CLK_T::PLL0CTL0: BP Mask */ + +/* For PLL2 ~ PLL5 */ +#define CLK_PLLnCTL0_FBDIV_Pos (0) /*!< CLK_T::PLLnCTL0: FBDIV Position */ +#define CLK_PLLnCTL0_FBDIV_Msk (0x7fful << CLK_PLLnCTL0_FBDIV_Pos) /*!< CLK_T::PLLnCTL0: FBDIV Mask */ + +#define CLK_PLLnCTL0_INDIV_Pos (12) /*!< CLK_T::PLLnCTL0: INDIV Position */ +#define CLK_PLLnCTL0_INDIV_Msk (0x3ful << CLK_PLLnCTL0_INDIV_Pos) /*!< CLK_T::PLLnCTL0: INDIV Mask */ + +#define CLK_PLLnCTL0_MODE_Pos (18) /*!< CLK_T::PLLnCTL0: MODE Position */ +#define CLK_PLLnCTL0_MODE_Msk (0x3ul << CLK_PLLnCTL0_MODE_Pos) /*!< CLK_T::PLLnCTL0: MODE Mask */ + +#define CLK_PLLnCTL0_SSRATE_Pos (20) /*!< CLK_T::PLLnCTL0: SSRATE Position */ +#define CLK_PLLnCTL0_SSRATE_Msk (0x7fful << CLK_PLLnCTL0_SSRATE_Pos) /*!< CLK_T::PLLnCTL0: SSRATE Mask */ + +#define CLK_PLLnCTL1_PD_Pos (0) /*!< CLK_T::PLLnCTL1: PD Position */ +#define CLK_PLLnCTL1_PD_Msk (0x1ul << CLK_PLLnCTL1_PD_Pos) /*!< CLK_T::PLLnCTL1: PD Mask */ + +#define CLK_PLLnCTL1_BP_Pos (1) /*!< CLK_T::PLLnCTL1: BP Position */ +#define CLK_PLLnCTL1_BP_Msk (0x1ul << CLK_PLLnCTL1_BP_Pos) /*!< CLK_T::PLLnCTL1: BP Mask */ + +#define CLK_PLLnCTL1_OUTDIV_Pos (4) /*!< CLK_T::PLLnCTL1: OUTDIV Position */ +#define CLK_PLLnCTL1_OUTDIV_Msk (0x7ul << CLK_PLLnCTL1_OUTDIV_Pos) /*!< CLK_T::PLLnCTL1: OUTDIV Mask */ + +#define CLK_PLLnCTL1_FRAC_Pos (8) /*!< CLK_T::PLLnCTL1: FRAC Position */ +#define CLK_PLLnCTL1_FRAC_Msk (0xfffffful << CLK_PLLnCTL1_FRAC_Pos) /*!< CLK_T::PLLnCTL1: FRAC Mask */ + +#define CLK_PLLnCTL2_SLOPE_Pos (0) /*!< CLK_T::PLLnCTL2: SLOPE Position */ +#define CLK_PLLnCTL2_SLOPE_Msk (0xfffffful << CLK_PLLnCTL2_SLOPE_Pos) /*!< CLK_T::PLLnCTL2: SLOPE Mask */ + +#define CLK_CLKDCTL_HXTFDEN_Pos (4) /*!< CLK_T::CLKDCTL: HXTFDEN Position */ +#define CLK_CLKDCTL_HXTFDEN_Msk (0x1ul << CLK_CLKDCTL_HXTFDEN_Pos) /*!< CLK_T::CLKDCTL: HXTFDEN Mask */ + +#define CLK_CLKDCTL_HXTFIEN_Pos (5) /*!< CLK_T::CLKDCTL: HXTFIEN Position */ +#define CLK_CLKDCTL_HXTFIEN_Msk (0x1ul << CLK_CLKDCTL_HXTFIEN_Pos) /*!< CLK_T::CLKDCTL: HXTFIEN Mask */ + +#define CLK_CLKDCTL_LXTFDEN_Pos (12) /*!< CLK_T::CLKDCTL: LXTFDEN Position */ +#define CLK_CLKDCTL_LXTFDEN_Msk (0x1ul << CLK_CLKDCTL_LXTFDEN_Pos) /*!< CLK_T::CLKDCTL: LXTFDEN Mask */ + +#define CLK_CLKDCTL_LXTFIEN_Pos (13) /*!< CLK_T::CLKDCTL: LXTFIEN Position */ +#define CLK_CLKDCTL_LXTFIEN_Msk (0x1ul << CLK_CLKDCTL_LXTFIEN_Pos) /*!< CLK_T::CLKDCTL: LXTFIEN Mask */ + +#define CLK_CLKDCTL_HXTFQDEN_Pos (16) /*!< CLK_T::CLKDCTL: HXTFQDEN Position */ +#define CLK_CLKDCTL_HXTFQDEN_Msk (0x1ul << CLK_CLKDCTL_HXTFQDEN_Pos) /*!< CLK_T::CLKDCTL: HXTFQDEN Mask */ + +#define CLK_CLKDCTL_HXTFQIEN_Pos (17) /*!< CLK_T::CLKDCTL: HXTFQIEN Position */ +#define CLK_CLKDCTL_HXTFQIEN_Msk (0x1ul << CLK_CLKDCTL_HXTFQIEN_Pos) /*!< CLK_T::CLKDCTL: HXTFQIEN Mask */ + +#define CLK_CLKDSTS_HXTFIF_Pos (0) /*!< CLK_T::CLKDSTS: HXTFIF Position */ +#define CLK_CLKDSTS_HXTFIF_Msk (0x1ul << CLK_CLKDSTS_HXTFIF_Pos) /*!< CLK_T::CLKDSTS: HXTFIF Mask */ + +#define CLK_CLKDSTS_LXTFIF_Pos (1) /*!< CLK_T::CLKDSTS: LXTFIF Position */ +#define CLK_CLKDSTS_LXTFIF_Msk (0x1ul << CLK_CLKDSTS_LXTFIF_Pos) /*!< CLK_T::CLKDSTS: LXTFIF Mask */ + +#define CLK_CLKDSTS_HXTFQIF_Pos (8) /*!< CLK_T::CLKDSTS: HXTFQIF Position */ +#define CLK_CLKDSTS_HXTFQIF_Msk (0x1ul << CLK_CLKDSTS_HXTFQIF_Pos) /*!< CLK_T::CLKDSTS: HXTFQIF Mask */ + +#define CLK_CDUPB_UPERBD_Pos (0) /*!< CLK_T::CDUPB: UPERBD Position */ +#define CLK_CDUPB_UPERBD_Msk (0x3fful << CLK_CDUPB_UPERBD_Pos) /*!< CLK_T::CDUPB: UPERBD Mask */ + +#define CLK_CDLOWB_LOWERBD_Pos (0) /*!< CLK_T::CDLOWB: LOWERBD Position */ +#define CLK_CDLOWB_LOWERBD_Msk (0x3fful << CLK_CDLOWB_LOWERBD_Pos) /*!< CLK_T::CDLOWB: LOWERBD Mask */ + +#define CLK_CKFLTRCTL_HXTFLTREN_Pos (0) /*!< CLK_T::CKFLTRCTL: HXTFLTREN Position */ +#define CLK_CKFLTRCTL_HXTFLTREN_Msk (0x1ul << CLK_CKFLTRCTL_HXTFLTREN_Pos) /*!< CLK_T::CKFLTRCTL: HXTFLTREN Mask */ + +#define CLK_CKFLTRCTL_HXTFLTRSEL_Pos (1) /*!< CLK_T::CKFLTRCTL: HXTFLTRSEL Position */ +#define CLK_CKFLTRCTL_HXTFLTRSEL_Msk (0x1ul << CLK_CKFLTRCTL_HXTFLTRSEL_Pos) /*!< CLK_T::CKFLTRCTL: HXTFLTRSEL Mask */ + +#define CLK_CKFLTRCTL_HXTGTEN_Pos (4) /*!< CLK_T::CKFLTRCTL: HXTGTEN Position */ +#define CLK_CKFLTRCTL_HXTGTEN_Msk (0x1ul << CLK_CKFLTRCTL_HXTGTEN_Pos) /*!< CLK_T::CKFLTRCTL: HXTGTEN Mask */ + +#define CLK_CKFLTRCTL_HXTBYPSEN_Pos (5) /*!< CLK_T::CKFLTRCTL: HXTBYPSEN Position */ +#define CLK_CKFLTRCTL_HXTBYPSEN_Msk (0x1ul << CLK_CKFLTRCTL_HXTBYPSEN_Pos) /*!< CLK_T::CKFLTRCTL: HXTBYPSEN Mask */ + +#define CLK_CKFLTRCTL_HIRCFLTREN_Pos (8) /*!< CLK_T::CKFLTRCTL: HIRCFLTREN Position */ +#define CLK_CKFLTRCTL_HIRCFLTREN_Msk (0x1ul << CLK_CKFLTRCTL_HIRCFLTREN_Pos) /*!< CLK_T::CKFLTRCTL: HIRCFLTREN Mask */ + +#define CLK_CKFLTRCTL_HIRCFLTRSEL_Pos (9) /*!< CLK_T::CKFLTRCTL: HIRCFLTRSEL Position */ +#define CLK_CKFLTRCTL_HIRCFLTRSEL_Msk (0x1ul << CLK_CKFLTRCTL_HIRCFLTRSEL_Pos) /*!< CLK_T::CKFLTRCTL: HIRCFLTRSEL Mask */ + +#define CLK_CKFLTRCTL_HIRCGTEN_Pos (12) /*!< CLK_T::CKFLTRCTL: HIRCGTEN Position */ +#define CLK_CKFLTRCTL_HIRCGTEN_Msk (0x1ul << CLK_CKFLTRCTL_HIRCGTEN_Pos) /*!< CLK_T::CKFLTRCTL: HIRCGTEN Mask */ + +/**@}*/ /* CLK_CONST */ +/**@}*/ /* end of CLK register group */ +/**@}*/ /* end of REGISTER group */ + +#if defined ( __CC_ARM ) + #pragma no_anon_unions +#endif + +#endif /* __CLK_REG_H__ */ diff --git a/bsp/nuvoton/libraries/ma35/Device/Nuvoton/MA35D1/Include/crypto_reg.h b/bsp/nuvoton/libraries/ma35/Device/Nuvoton/MA35D1/Include/crypto_reg.h new file mode 100644 index 0000000000..dd621e1844 --- /dev/null +++ b/bsp/nuvoton/libraries/ma35/Device/Nuvoton/MA35D1/Include/crypto_reg.h @@ -0,0 +1,7135 @@ +/**************************************************************************//** + * @file crypto_reg.h + * @brief Cryptographic Accelerator definition header file + * + * SPDX-License-Identifier: Apache-2.0 + * @copyright (C) 2021 Nuvoton Technology Corp. All rights reserved. + *****************************************************************************/ +#ifndef __CRYPTO_REG_H__ +#define __CRYPTO_REG_H__ + +#if defined ( __CC_ARM ) + #pragma anon_unions +#endif + +/** + @addtogroup REGISTER Control Register + @{ +*/ + +/*---------------------- Cryptographic Accelerator -------------------------*/ +/** + @addtogroup CRYPTO Cryptographic Accelerator(CRYPTO) + Memory Mapped Structure for Cryptographic Accelerator +@{ */ + +typedef struct +{ + + /** + * @var CRYPTO_T::INTEN + * Offset: 0x00 Crypto Interrupt Enable Control Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[0] |AESIEN |AES Interrupt Enable Bit + * | | |0 = AES interrupt Disabled. + * | | |1 = AES interrupt Enabled. + * | | |Note: In DMA mode, an interrupt will be triggered when an amount of data set in AES_DMA_CNT is fed into the AES engine. + * | | |In Non-DMA mode, an interrupt will be triggered when the AES engine finishes the operation. + * |[1] |AESEIEN |AES Error Flag Enable Bit + * | | |0 = AES error interrupt flag Disabled. + * | | |1 = AES error interrupt flag Enabled. + * |[16] |PRNGIEN |PRNG Interrupt Enable Bit + * | | |0 = PRNG interrupt Disabled. + * | | |1 = PRNG interrupt Enabled. + * |[17] |PRNGEIEN |PRNG Error Flag Enable Bit + * | | |0 = PRNG error interrupt flag Disabled. + * | | |1 = PRNG error interrupt flag Enabled. + * |[22] |ECCIEN |ECC Interrupt Enable Bit + * | | |0 = ECC interrupt Disabled. + * | | |1 = ECC interrupt Enabled. + * | | |Note: In DMA mode, an interrupt will be triggered when an amount of data set in ECC_DMA_CNT is fed into the ECC engine + * | | |In Non-DMA mode, an interrupt will be triggered when the ECC engine finishes the operation. + * |[23] |ECCEIEN |ECC Error Interrupt Enable Bit + * | | |0 = ECC error interrupt flag Disabled. + * | | |1 = ECC error interrupt flag Enabled. + * |[24] |HMACIEN |SHA/HMAC Interrupt Enable Bit + * | | |0 = SHA/HMAC interrupt Disabled. + * | | |1 = SHA/HMAC interrupt Enabled. + * | | |Note: In DMA mode, an interrupt will be triggered when an amount of data set in HMAC_DMA_CNT is fed into the SHA/HMAC engine + * | | |In Non-DMA mode, an interrupt will be triggered when the SHA/HMAC engine finishes the operation. + * |[25] |HMACEIEN |SHA/HMAC Error Interrupt Enable Bit + * | | |0 = SHA/HMAC error interrupt flag Disabled. + * | | |1 = HMAC error interrupt flag Enabled. + * |[30] |RSAIEN |RSA Interrupt Enable Bit + * | | |0 = RSA interrupt Disabled. + * | | |1 = RSA interrupt Enabled. + * |[31] |RSAEIEN |RSA Error Interrupt Enable Bit + * | | |0 = RSA error interrupt flag Disabled. + * | | |1 = RSA error interrupt flag Enabled. + * @var CRYPTO_T::INTSTS + * Offset: 0x04 Crypto Interrupt Flag + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[0] |AESIF |AES Finish Interrupt Flag + * | | |0 = No AES interrupt. + * | | |1 = AES encryption/decryption done interrupt. + * | | |Note: This bit is cleared by writing 1, and it has no effect by writing 0. + * |[1] |AESEIF |AES Error Flag + * | | |0 = No AES error. + * | | |1 = AES encryption/decryption error interrupt. + * | | |Note: This bit is cleared by writing 1, and it has no effect by writing 0. + * |[16] |PRNGIF |PRNG Finish Interrupt Flag + * | | |0 = No PRNG interrupt. + * | | |1 = PRNG key generation done interrupt. + * | | |Note: This bit is cleared by writing 1, and it has no effect by writing 0. + * |[17] |PRNGEIF |PRNG Error Flag + * | | |0 = No PRNG error. + * | | |1 = PRNG key generation error interrupt. + * | | |Note: This bit is cleared by writing 1, and it has no effect by writing 0. + * |[22] |ECCIF |ECC Finish Interrupt Flag + * | | |0 = No ECC interrupt. + * | | |1 = ECC operation done interrupt. + * | | |Note: This bit is cleared by writing 1, and it has no effect by writing 0. + * |[23] |ECCEIF |ECC Error Flag + * | | |This register includes operating and setting error + * | | |The detail flag is shown in CRYPTO_ECC_STS register. + * | | |0 = No ECC error. + * | | |1 = ECC error interrupt. + * | | |Note: This bit is cleared by writing 1, and it has no effect by writing 0. + * |[24] |HMACIF |SHA/HMAC Finish Interrupt Flag + * | | |0 = No SHA/HMAC interrupt. + * | | |1 = SHA/HMAC operation done interrupt. + * | | |Note: This bit is cleared by writing 1, and it has no effect by writing 0. + * |[25] |HMACEIF |SHA/HMAC Error Flag + * | | |This register includes operating and setting error + * | | |The detail flag is shown in CRYPTO_HMAC_STS register. + * | | |0 = No SHA/HMAC error. + * | | |1 = SHA/HMAC error interrupt. + * | | |Note: This bit is cleared by writing 1, and it has no effect by writing 0. + * |[30] |RSAIF |RSA Finish Interrupt Flag + * | | |0 = No RSA interrupt. + * | | |1 = RSA operation done interrupt. + * | | |Note: This bit is cleared by writing 1, and it has no effect by writing 0. + * |[31] |RSAEIF |RSA Error Interrupt Flag + * | | |This register includes operating and setting error + * | | |The detail flag is shown in CRYPTO_RSA_STS register. + * | | |0 = No RSA error. + * | | |1 = RSA error interrupt. + * | | |Note: This bit is cleared by writing 1, and it has no effect by writing 0. + * @var CRYPTO_T::PRNG_CTL + * Offset: 0x08 PRNG Control Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[0] |START |Start PRNG Engine + * | | |0 = Stop PRNG engine. + * | | |1 = Generate new key and store the new key to register CRYPTO_PRNG_KEYx, which will be cleared when the new key is generated. + * |[1] |SEEDRLD |Reload New Seed for PRNG Engine + * | | |0 = Generating key based on the current seed. + * | | |1 = Reload new seed. + * |[5:2] |KEYSZ |PRNG Generate Key Size + * | | |0000 = 128 bits. + * | | |0001 = 163 bits. + * | | |0010 = 192 bits. + * | | |0011 = 224 bits. + * | | |0100 = 233 bits. + * | | |0101 = 255 bits. + * | | |0110 = 256 bits. + * | | |0111 = 283 bits (only for KS). + * | | |1000 = 384 bits (only for KS). + * | | |1001 = 409 bits (only for KS). + * | | |1010 = 512 bits (only for KS). + * | | |1011 = 521 bits (only for KS). + * | | |1100 = 571 bits (only for KS). + * | | |1101 = Reserved. + * | | |1110 = Reserved. + * | | |1111 = Reserved. + * | | |Note: 283~571 bits are only generated for key store. + * |[8] |BUSY |PRNG Busy (Read Only) + * | | |0 = PRNG engine is idle. + * | | |1 = PRNG engine is generating CRYPTO_PRNG_KEYx. + * |[16] |SEEDSRC |Seed Source + * | | |0 = Seed is from TRNG. + * | | |1 = Seed is from PRNG seed register. + * | | |Note: When SEEDRLD is set to 0, this bit (SEEDSRC) is meaningless. + * @var CRYPTO_T::PRNG_SEED + * Offset: 0x0C Seed for PRNG + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[31:0] |SEED |Seed for PRNG (Write Only) + * | | |The bits store the seed for PRNG engine. + * | | |Note: In TRNG+PRNG mode, the seed is from TRNG engine, and it will not be stored in this register. + * @var CRYPTO_T::PRNG_KEY0 + * Offset: 0x10 PRNG Generated Key0 + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[31:0] |KEY |Store PRNG Generated Key (Read Only) + * | | |The bits store the key that is generated by PRNG. + * @var CRYPTO_T::PRNG_KEY1 + * Offset: 0x14 PRNG Generated Key1 + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[31:0] |KEY |Store PRNG Generated Key (Read Only) + * | | |The bits store the key that is generated by PRNG. + * @var CRYPTO_T::PRNG_KEY2 + * Offset: 0x18 PRNG Generated Key2 + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[31:0] |KEY |Store PRNG Generated Key (Read Only) + * | | |The bits store the key that is generated by PRNG. + * @var CRYPTO_T::PRNG_KEY3 + * Offset: 0x1C PRNG Generated Key3 + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[31:0] |KEY |Store PRNG Generated Key (Read Only) + * | | |The bits store the key that is generated by PRNG. + * @var CRYPTO_T::PRNG_KEY4 + * Offset: 0x20 PRNG Generated Key4 + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[31:0] |KEY |Store PRNG Generated Key (Read Only) + * | | |The bits store the key that is generated by PRNG. + * @var CRYPTO_T::PRNG_KEY5 + * Offset: 0x24 PRNG Generated Key5 + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[31:0] |KEY |Store PRNG Generated Key (Read Only) + * | | |The bits store the key that is generated by PRNG. + * @var CRYPTO_T::PRNG_KEY6 + * Offset: 0x28 PRNG Generated Key6 + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[31:0] |KEY |Store PRNG Generated Key (Read Only) + * | | |The bits store the key that is generated by PRNG. + * @var CRYPTO_T::PRNG_KEY7 + * Offset: 0x2C PRNG Generated Key7 + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[31:0] |KEY |Store PRNG Generated Key (Read Only) + * | | |The bits store the key that is generated by PRNG. + * @var CRYPTO_T::PRNG_STS + * Offset: 0x30 PRNG Status Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[0] |BUSY |PRNG Busy Flag + * | | |0 = PRNG engine is idle. + * | | |1 = PRNG engine is generating CRYPTO_PRNG_KEYx. + * |[16] |KCTLERR |PRNG Key Control Register Error Flag + * | | |0 = No error. + * | | |1 = PRNG key control error + * | | |When PRNG execute ECDSA or ECDH, but PRNG seed not from TRNG or key is not written to the SRAM of key store (WSDST, CRYPTO_PRNG_KSCTL[23:22] is not equal to '00'). + * |[17] |KSERR |PRNG Access Key Store Error Flag + * | | |0 = No error. + * | | |1 = Access key store failed. + * |[18] |TRNGERR |True Random Number Generator Error Flag + * | | |0 = No error. + * | | |1 = Getting random number or seed failed. + * | | |Note: When TRNGERR becomes 1, TRNG may be BUSY, in TESTMODE or in wrong state. + * @var CRYPTO_T::AES_FDBCK0 + * Offset: 0x50 AES Engine Output Feedback Data After Cryptographic Operation + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[31:0] |FDBCK |AES Feedback Information + * | | |The feedback value is 128 bits in size. + * | | |The AES engine uses the data from CRYPTO_AES_FDBCKx as the data inputted to CRYPTO_AES_IVx for the next block in DMA cascade mode. + * | | |The AES engine outputs feedback information for IV in the next block's operation + * | | |Software can use this feedback information to implement more than four DMA channels + * | | |Software can store that feedback value temporarily + * | | |After switching back, fill the stored feedback value to CRYPTO_AES_IVx in the same channel operation, and then continue the operation with the original setting. + * @var CRYPTO_T::AES_FDBCK1 + * Offset: 0x54 AES Engine Output Feedback Data After Cryptographic Operation + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[31:0] |FDBCK |AES Feedback Information + * | | |The feedback value is 128 bits in size. + * | | |The AES engine uses the data from CRYPTO_AES_FDBCKx as the data inputted to CRYPTO_AES_IVx for the next block in DMA cascade mode. + * | | |The AES engine outputs feedback information for IV in the next block's operation + * | | |Software can use this feedback information to implement more than four DMA channels + * | | |Software can store that feedback value temporarily + * | | |After switching back, fill the stored feedback value to CRYPTO_AES_IVx in the same channel operation, and then continue the operation with the original setting. + * @var CRYPTO_T::AES_FDBCK2 + * Offset: 0x58 AES Engine Output Feedback Data After Cryptographic Operation + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[31:0] |FDBCK |AES Feedback Information + * | | |The feedback value is 128 bits in size. + * | | |The AES engine uses the data from CRYPTO_AES_FDBCKx as the data inputted to CRYPTO_AES_IVx for the next block in DMA cascade mode. + * | | |The AES engine outputs feedback information for IV in the next block's operation + * | | |Software can use this feedback information to implement more than four DMA channels + * | | |Software can store that feedback value temporarily + * | | |After switching back, fill the stored feedback value to CRYPTO_AES_IVx in the same channel operation, and then continue the operation with the original setting. + * @var CRYPTO_T::AES_FDBCK3 + * Offset: 0x5C AES Engine Output Feedback Data After Cryptographic Operation + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[31:0] |FDBCK |AES Feedback Information + * | | |The feedback value is 128 bits in size. + * | | |The AES engine uses the data from CRYPTO_AES_FDBCKx as the data inputted to CRYPTO_AES_IVx for the next block in DMA cascade mode. + * | | |The AES engine outputs feedback information for IV in the next block's operation + * | | |Software can use this feedback information to implement more than four DMA channels + * | | |Software can store that feedback value temporarily + * | | |After switching back, fill the stored feedback value to CRYPTO_AES_IVx in the same channel operation, and then continue the operation with the original setting. + * @var CRYPTO_T::AES_GCM_IVCNT0 + * Offset: 0x80 AES GCM IV Byte Count Register 0 + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[31:0] |CNT |AES GCM IV Byte Count + * | | |The bit length of IV is 64 bits for AES GCM mode + * | | |The CRYPTO_AES_GCM_IVCNT0 keeps the low weight byte count of initial vector (i.e., len(IV)[34:3]) of AES GCM mode and can be read and written. + * @var CRYPTO_T::AES_GCM_IVCNT1 + * Offset: 0x84 AES GCM IV Byte Count Register 1 + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[28:0] |CNT |AES GCM IV Byte Count + * | | |The bit length of IV is 64 bits for AES GCM mode + * | | |The CRYPTO_AES_GCM_IVCNT1 keeps the high weight byte count of initial vector (i.e., len(IV)[64:35]) of AES GCM mode and can be read and written. + * @var CRYPTO_T::AES_GCM_ACNT0 + * Offset: 0x88 AES GCM A Byte Count Register 0 + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[31:0] |CNT |AES GCM a Byte Count + * | | |The bit length of A is 64 bits for AES GCM mode + * | | |The CRYPTO_AES_GCM_ACNT0 keeps the low weight byte count of the additional authenticated data (i.e., len(A)[34:3]) of AES GCM mode and can be read and written. + * @var CRYPTO_T::AES_GCM_ACNT1 + * Offset: 0x8C AES GCM A Byte Count Register 1 + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[28:0] |CNT |AES GCM a Byte Count + * | | |The bit length of A is 64 bits for AES GCM mode + * | | |The CRYPTO_AES_GCM_ACNT0 keeps the high weight byte count of the additional authenticated data (i.e., len(A)[63:35]) of AES GCM mode and can be read and written. + * @var CRYPTO_T::AES_GCM_PCNT0 + * Offset: 0x90 AES GCM P Byte Count Register 0 + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[31:0] |CNT |AES GCM P Byte Count + * | | |The bit length of Por C is 39 bits for AES GCM mode + * | | |The CRYPTO_AES_GCM_PCNT0 keeps the low weight byte count of the plaintext or ciphertext (i.e., len(P)[34:3] or len(C)[34:3]) of AES GCM mode and can be read and written. + * @var CRYPTO_T::AES_GCM_PCNT1 + * Offset: 0x94 AES GCM P Byte Count Register 1 + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[28:0] |CNT |AES GCM P Byte Count + * | | |The bit length of Por C is 39 bits for AES GCM mode + * | | |The CRYPTO_AES_GCM_PCNT1 keeps the high weight byte count of the plaintext or ciphertext (i.e., len(P)[38:35] or len(C)[38:35]) of AES GCM mode and can be read and written. + * | | |The bit length of Por C is 64 bits for AES CCM mode + * | | |The CRYPTO_AES_GCM_PCNT1 keeps the high weight byte count of the plaintext or ciphertext (i.e., len(P)[63:35] or len(C)[63:35]) of AES CCM mode and can be read and written. + * @var CRYPTO_T::AES_FBADDR + * Offset: 0xA0 AES DMA Feedback Address Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[31:0] |FBADDR |AES DMA Feedback Address + * | | |In DMA cascade mode, software can update DMA feedback address register for automatically reading and writing feedback values via DMA + * | | |The FBADDR keeps the feedback address of the feedback data for the next cascade operation + * | | |Based on the feedback address, the AES accelerator can read the feedback data of the last cascade operation from SRAM memory space and write the feedback data of the current cascade operation to SRAM memory space + * | | |The start of feedback address should be located at word boundary + * | | |In other words, bit 1 and 0 of FBADDR are ignored. + * | | |FBADDR can be read and written. + * | | |In DMA mode, software can update the next CRYPTO_AES_FBADDR before triggering START. + * @var CRYPTO_T::AES_CTL + * Offset: 0x100 AES Control Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[0] |START |AES Engine Start + * | | |0 = No effect. + * | | |1 = Start AES engine. BUSY flag will be set. + * | | |Note: This bit is always 0 when it is read back. + * |[1] |STOP |AES Engine Stop + * | | |0 = No effect. + * | | |1 = Stop AES engine. + * | | |Note: This bit is always 0 when it is read back. + * |[3:2] |KEYSZ |AES Key Size + * | | |This bit defines three different key size for AES operation. + * | | |2'b00 = 128 bits key. + * | | |2'b01 = 192 bits key. + * | | |2'b10 = 256 bits key. + * | | |2'b11 = Reserved. + * | | |If the AES accelerator is operating and the corresponding flag BUSY is 1, updating this register has no effect. + * | | |Note: When SM4EN=1, the key size of AES must be 128. + * |[5] |DMALAST |AES Last Block + * | | |In DMA mode, this bit must be set as beginning the last DMA cascade round. + * | | |In Non-DMA mode, this bit must be set when feeding in the last block of data in ECB, CBC, CTR, OFB, and CFB mode, and feeding in the (last-1) block of data at CBC-CS1, CBC-CS2, and CBC-CS3 mode. + * | | |This bit is always 0 when it is read back, and must be written again once START is triggered. + * |[6] |DMACSCAD |AES Engine DMA with Cascade Mode + * | | |0 = DMA cascade function Disabled. + * | | |1 = In DMA cascade mode, software can update DMA source address register, destination address register, and byte count register during a cascade operation, without finishing the accelerator operation. + * |[7] |DMAEN |AES Engine DMA Enable Bit + * | | |0 = AES DMA engine Disabled. + * | | |The AES engine operates in Non-DMA mode. The data need to be written in CRYPTO_AES_DATIN. + * | | |1 = AES_DMA engine Enabled. + * | | |The AES engine operates in DMA mode, and data movement from/to the engine is done by DMA logic. + * |[15:8] |OPMODE |AES Engine Operation Modes + * | | |0x00 = ECB (Electronic Codebook Mode) 0x01 = CBC (Cipher Block Chaining Mode). + * | | |0x02 = CFB (Cipher Feedback Mode). + * | | |0x03 = OFB (Output Feedback Mode). + * | | |0x04 = CTR (Counter Mode). + * | | |0x10 = CBC-CS1 (CBC Ciphertext-Stealing 1 Mode). + * | | |0x11 = CBC-CS2 (CBC Ciphertext-Stealing 2 Mode). + * | | |0x12 = CBC-CS3 (CBC Ciphertext-Stealing 3 Mode). + * | | |0x20 = GCM (Galois/Counter Mode). + * | | |0x21 = GHASH (Galois Hash Function). + * | | |0x22 = CCM (Counter with CBC-MAC Mode). + * |[16] |ENCRYPTO |AES Encryption/Decryption + * | | |0 = AES engine executes decryption operation. + * | | |1 = AES engine executes encryption operation. + * |[17] |SM4EN |SM4 Engine Enable + * | | |0 = AES engine Enabled. + * | | |1 = SM4 engine Enabled. + * |[19] |DFAPEN |AES Differential Fault Attack Protection Enable + * | | |0 = AES Differential Fault Attack Protection Disabled. + * | | |1 = AES Differential Fault Attack Protection Enabled. + * |[20] |FBIN |Feedback Input to AES Via DMA Automatically + * | | |0 = DMA automatic feedback input function Disabled. + * | | |1 = DMA automatic feedback input function Enabled when DMAEN = 1. + * |[21] |FBOUT |Feedback Output From AES Via DMA Automatically + * | | |0 = DMA automatic feedback output function Disabled. + * | | |1 = DMA automatic feedback output function Enabled when DMAEN = 1. + * |[22] |OUTSWAP |AES Engine Output Data Swap + * | | |0 = Keep the original order. + * | | |1 = The order that CPU reads data from the accelerator will be changed from {byte3, byte2, byte1, byte0} to {byte0, byte1, byte2, byte3}. + * |[23] |INSWAP |AES Engine Input Data Swap + * | | |0 = Keep the original order. + * | | |1 = The order that CPU feeds data to the accelerator will be changed from {byte3, byte2, byte1, byte0} to {byte0, byte1, byte2, byte3}. + * |[24] |KOUTSWAP |AES Engine Output Key, Initial Vector and Feedback Swap + * | | |0 = Keep the original order. + * | | |1 = The order that CPU reads key, initial vector and feedback from the accelerator will be changed from {byte3, byte2, byte1, byte0} to {byte0, byte1, byte2, byte3}. + * |[25] |KINSWAP |AES Engine Input Key and Initial Vector Swap + * | | |0 = Keep the original order. + * | | |1 = The order that CPU feeds key and initial vector to the accelerator will be changed from {byte3, byte2, byte1, byte0} to {byte0, byte1, byte2, byte3}. + * |[30:26] |KEYUNPRT |Unprotect Key + * | | |Writing 0 to CRYPTO_AES_CTL[31] and "10110" to CRYPTO_AES_CTL[30:26] is to unprotect the AES key. + * | | |The KEYUNPRT can be read and written + * | | |When it is written as the AES engine is operating, BUSY flag is 1, there would be no effect on KEYUNPRT. + * |[31] |KEYPRT |Protect Key + * | | |Read as a flag to reflect KEYPRT. + * | | |0 = No effect. + * | | |1 = Protect the content of the AES key from reading + * | | |The return value for reading CRYPTO_AES_KEYx is not the content of the registers CRYPTO_AES_KEYx + * | | |Once it is set, it can be cleared by asserting KEYUNPRT + * | | |The key content would be cleared as well. + * @var CRYPTO_T::AES_STS + * Offset: 0x104 AES Engine Flag + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[0] |BUSY |AES Engine Busy + * | | |0 = The AES engine is idle or finished. + * | | |1 = The AES engine is under processing. + * |[8] |INBUFEMPTY|AES Input Buffer Empty + * | | |0 = There are some data in input buffer waiting for the AES engine to process. + * | | |1 = AES input buffer is empty + * | | |Software needs to feed data to the AES engine + * | | |Otherwise, the AES engine will be pending to wait for input data. + * |[9] |INBUFFULL |AES Input Buffer Full Flag + * | | |0 = AES input buffer is not full. Software can feed the data into the AES engine. + * | | |1 = AES input buffer is full + * | | |Software cannot feed data to the AES engine + * | | |Otherwise, the flag INBUFERR will be set to 1. + * |[10] |INBUFERR |AES Input Buffer Error Flag + * | | |0 = No error. + * | | |1 = Error happened during feeding data to the AES engine. + * |[12] |CNTERR |CRYPTO_AES_CNT Setting Error + * | | |0 = No error in CRYPTO_AES_CNT setting. + * | | |1 = CRYPTO_AES_CNT is 0 if DMAEN (CRYPTO_AES_CTL[7]) is enabled. + * |[16] |OUTBUFEMPTY|AES Out Buffer Empty + * | | |0 = AES output buffer is not empty. There are some valid data kept in output buffer. + * | | |1 = AES output buffer is empty + * | | |Software cannot get data from CRYPTO_AES_DATOUT + * | | |Otherwise, the flag OUTBUFERR will be set to 1 since the output buffer is empty. + * |[17] |OUTBUFFULL|AES Out Buffer Full Flag + * | | |0 = AES output buffer is not full. + * | | |1 = AES output buffer is full, and software needs to get data from CRYPTO_AES_DATOUT + * | | |Otherwise, the AES engine will be pending since the output buffer is full. + * |[18] |OUTBUFERR |AES Out Buffer Error Flag + * | | |0 = No error. + * | | |1 = Error happened during getting the result from AES engine. + * |[20] |BUSERR |AES DMA Access Bus Error Flag + * | | |0 = No error. + * | | |1 = Bus error will stop DMA operation and AES engine. + * |[21] |KSERR |AES Engine Access Key Store Error Flag + * | | |0 = No error. + * | | |1 = Key store access error will stop AES engine. + * |[22] |DFAERR |AES Engine Differential Fault Attack Error Flag + * | | |0 = No error. + * | | |1 = Differential Fault Attack happened in AES engine. The results from AES engine are wrong. + * @var CRYPTO_T::AES_DATIN + * Offset: 0x108 AES Engine Data Input Port Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[31:0] |DATIN |AES Engine Input Port + * | | |CPU feeds data to AES engine through this port by checking CRYPTO_AES_STS. Feed data as INBUFFULL is 0. + * @var CRYPTO_T::AES_DATOUT + * Offset: 0x10C AES Engine Data Output Port Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[31:0] |DATOUT |AES Engine Output Port + * | | |CPU gets results from the AES engine through this port by checking CRYPTO_AES_STS + * | | |Get data as OUTBUFEMPTY is 0. + * @var CRYPTO_T::AES_KEY0 + * Offset: 0x110 AES Key Word 0 Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[31:0] |KEY |CRYPTO_AES_KEYx + * | | |The KEY keeps the security key for AES operation. + * | | |x = 0, 1..7. + * | | |The security key for AES accelerator can be 128, 192, or 256 bits and four, six, or eight 32-bit registers are to store each security key. + * | | |{CRYPTO_AES_KEY3, CRYPTO_AES_KEY2, CRYPTO_AES_KEY1, CRYPTO_AES_KEY0} stores the 128-bit security key for AES operation. + * | | |{CRYPTO_AES_KEY5, CRYPTO_AES_KEY4, CRYPTO_AES_KEY3, CRYPTO_AES_KEY2, CRYPTO_AES_KEY1, CRYPTO_AES_KEY0} stores the 192-bit security key for AES operation. + * | | |{CRYPTO_AES_KEY7, CRYPTO_AES_KEY6, CRYPTO_AES_KEY5, CRYPTO_AES_KEY4, CRYPTO_AES_KEY3, CRYPTO_AES_KEY2, CRYPTO_AES_KEY1, CRYPTO_AES_KEY0} stores the 256-bit security key for AES operation. + * @var CRYPTO_T::AES_KEY1 + * Offset: 0x114 AES Key Word 1 Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[31:0] |KEY |CRYPTO_AES_KEYx + * | | |The KEY keeps the security key for AES operation. + * | | |x = 0, 1..7. + * | | |The security key for AES accelerator can be 128, 192, or 256 bits and four, six, or eight 32-bit registers are to store each security key. + * | | |{CRYPTO_AES_KEY3, CRYPTO_AES_KEY2, CRYPTO_AES_KEY1, CRYPTO_AES_KEY0} stores the 128-bit security key for AES operation. + * | | |{CRYPTO_AES_KEY5, CRYPTO_AES_KEY4, CRYPTO_AES_KEY3, CRYPTO_AES_KEY2, CRYPTO_AES_KEY1, CRYPTO_AES_KEY0} stores the 192-bit security key for AES operation. + * | | |{CRYPTO_AES_KEY7, CRYPTO_AES_KEY6, CRYPTO_AES_KEY5, CRYPTO_AES_KEY4, CRYPTO_AES_KEY3, CRYPTO_AES_KEY2, CRYPTO_AES_KEY1, CRYPTO_AES_KEY0} stores the 256-bit security key for AES operation. + * @var CRYPTO_T::AES_KEY2 + * Offset: 0x118 AES Key Word 2 Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[31:0] |KEY |CRYPTO_AES_KEYx + * | | |The KEY keeps the security key for AES operation. + * | | |x = 0, 1..7. + * | | |The security key for AES accelerator can be 128, 192, or 256 bits and four, six, or eight 32-bit registers are to store each security key. + * | | |{CRYPTO_AES_KEY3, CRYPTO_AES_KEY2, CRYPTO_AES_KEY1, CRYPTO_AES_KEY0} stores the 128-bit security key for AES operation. + * | | |{CRYPTO_AES_KEY5, CRYPTO_AES_KEY4, CRYPTO_AES_KEY3, CRYPTO_AES_KEY2, CRYPTO_AES_KEY1, CRYPTO_AES_KEY0} stores the 192-bit security key for AES operation. + * | | |{CRYPTO_AES_KEY7, CRYPTO_AES_KEY6, CRYPTO_AES_KEY5, CRYPTO_AES_KEY4, CRYPTO_AES_KEY3, CRYPTO_AES_KEY2, CRYPTO_AES_KEY1, CRYPTO_AES_KEY0} stores the 256-bit security key for AES operation. + * @var CRYPTO_T::AES_KEY3 + * Offset: 0x11C AES Key Word 3 Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[31:0] |KEY |CRYPTO_AES_KEYx + * | | |The KEY keeps the security key for AES operation. + * | | |x = 0, 1..7. + * | | |The security key for AES accelerator can be 128, 192, or 256 bits and four, six, or eight 32-bit registers are to store each security key. + * | | |{CRYPTO_AES_KEY3, CRYPTO_AES_KEY2, CRYPTO_AES_KEY1, CRYPTO_AES_KEY0} stores the 128-bit security key for AES operation. + * | | |{CRYPTO_AES_KEY5, CRYPTO_AES_KEY4, CRYPTO_AES_KEY3, CRYPTO_AES_KEY2, CRYPTO_AES_KEY1, CRYPTO_AES_KEY0} stores the 192-bit security key for AES operation. + * | | |{CRYPTO_AES_KEY7, CRYPTO_AES_KEY6, CRYPTO_AES_KEY5, CRYPTO_AES_KEY4, CRYPTO_AES_KEY3, CRYPTO_AES_KEY2, CRYPTO_AES_KEY1, CRYPTO_AES_KEY0} stores the 256-bit security key for AES operation. + * @var CRYPTO_T::AES_KEY4 + * Offset: 0x120 AES Key Word 4 Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[31:0] |KEY |CRYPTO_AES_KEYx + * | | |The KEY keeps the security key for AES operation. + * | | |x = 0, 1..7. + * | | |The security key for AES accelerator can be 128, 192, or 256 bits and four, six, or eight 32-bit registers are to store each security key. + * | | |{CRYPTO_AES_KEY3, CRYPTO_AES_KEY2, CRYPTO_AES_KEY1, CRYPTO_AES_KEY0} stores the 128-bit security key for AES operation. + * | | |{CRYPTO_AES_KEY5, CRYPTO_AES_KEY4, CRYPTO_AES_KEY3, CRYPTO_AES_KEY2, CRYPTO_AES_KEY1, CRYPTO_AES_KEY0} stores the 192-bit security key for AES operation. + * | | |{CRYPTO_AES_KEY7, CRYPTO_AES_KEY6, CRYPTO_AES_KEY5, CRYPTO_AES_KEY4, CRYPTO_AES_KEY3, CRYPTO_AES_KEY2, CRYPTO_AES_KEY1, CRYPTO_AES_KEY0} stores the 256-bit security key for AES operation. + * @var CRYPTO_T::AES_KEY5 + * Offset: 0x124 AES Key Word 5 Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[31:0] |KEY |CRYPTO_AES_KEYx + * | | |The KEY keeps the security key for AES operation. + * | | |x = 0, 1..7. + * | | |The security key for AES accelerator can be 128, 192, or 256 bits and four, six, or eight 32-bit registers are to store each security key. + * | | |{CRYPTO_AES_KEY3, CRYPTO_AES_KEY2, CRYPTO_AES_KEY1, CRYPTO_AES_KEY0} stores the 128-bit security key for AES operation. + * | | |{CRYPTO_AES_KEY5, CRYPTO_AES_KEY4, CRYPTO_AES_KEY3, CRYPTO_AES_KEY2, CRYPTO_AES_KEY1, CRYPTO_AES_KEY0} stores the 192-bit security key for AES operation. + * | | |{CRYPTO_AES_KEY7, CRYPTO_AES_KEY6, CRYPTO_AES_KEY5, CRYPTO_AES_KEY4, CRYPTO_AES_KEY3, CRYPTO_AES_KEY2, CRYPTO_AES_KEY1, CRYPTO_AES_KEY0} stores the 256-bit security key for AES operation. + * @var CRYPTO_T::AES_KEY6 + * Offset: 0x128 AES Key Word 6 Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[31:0] |KEY |CRYPTO_AES_KEYx + * | | |The KEY keeps the security key for AES operation. + * | | |x = 0, 1..7. + * | | |The security key for AES accelerator can be 128, 192, or 256 bits and four, six, or eight 32-bit registers are to store each security key. + * | | |{CRYPTO_AES_KEY3, CRYPTO_AES_KEY2, CRYPTO_AES_KEY1, CRYPTO_AES_KEY0} stores the 128-bit security key for AES operation. + * | | |{CRYPTO_AES_KEY5, CRYPTO_AES_KEY4, CRYPTO_AES_KEY3, CRYPTO_AES_KEY2, CRYPTO_AES_KEY1, CRYPTO_AES_KEY0} stores the 192-bit security key for AES operation. + * | | |{CRYPTO_AES_KEY7, CRYPTO_AES_KEY6, CRYPTO_AES_KEY5, CRYPTO_AES_KEY4, CRYPTO_AES_KEY3, CRYPTO_AES_KEY2, CRYPTO_AES_KEY1, CRYPTO_AES_KEY0} stores the 256-bit security key for AES operation. + * @var CRYPTO_T::AES_KEY7 + * Offset: 0x12C AES Key Word 7 Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[31:0] |KEY |CRYPTO_AES_KEYx + * | | |The KEY keeps the security key for AES operation. + * | | |x = 0, 1..7. + * | | |The security key for AES accelerator can be 128, 192, or 256 bits and four, six, or eight 32-bit registers are to store each security key. + * | | |{CRYPTO_AES_KEY3, CRYPTO_AES_KEY2, CRYPTO_AES_KEY1, CRYPTO_AES_KEY0} stores the 128-bit security key for AES operation. + * | | |{CRYPTO_AES_KEY5, CRYPTO_AES_KEY4, CRYPTO_AES_KEY3, CRYPTO_AES_KEY2, CRYPTO_AES_KEY1, CRYPTO_AES_KEY0} stores the 192-bit security key for AES operation. + * | | |{CRYPTO_AES_KEY7, CRYPTO_AES_KEY6, CRYPTO_AES_KEY5, CRYPTO_AES_KEY4, CRYPTO_AES_KEY3, CRYPTO_AES_KEY2, CRYPTO_AES_KEY1, CRYPTO_AES_KEY0} stores the 256-bit security key for AES operation. + * @var CRYPTO_T::AES_IV0 + * Offset: 0x130 AES Initial Vector Word 0 Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[31:0] |IV |AES Initial Vectors + * | | |x = 0, 1..3. + * | | |Four initial vectors (CRYPTO_AES_IV0, CRYPTO_AES_IV1, CRYPTO_AES_IV2, and CRYPTO_AES_IV3) are for AES operating in CBC, CFB, and OFB mode + * | | |Four registers (CRYPTO_AES_IV0, CRYPTO_AES_IV1, CRYPTO_AES_IV2, and CRYPTO_AES_IV3) act as Nonce counter when the AES engine is operating in CTR mode. + * @var CRYPTO_T::AES_IV1 + * Offset: 0x134 AES Initial Vector Word 1 Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[31:0] |IV |AES Initial Vectors + * | | |x = 0, 1..3. + * | | |Four initial vectors (CRYPTO_AES_IV0, CRYPTO_AES_IV1, CRYPTO_AES_IV2, and CRYPTO_AES_IV3) are for AES operating in CBC, CFB, and OFB mode + * | | |Four registers (CRYPTO_AES_IV0, CRYPTO_AES_IV1, CRYPTO_AES_IV2, and CRYPTO_AES_IV3) act as Nonce counter when the AES engine is operating in CTR mode. + * @var CRYPTO_T::AES_IV2 + * Offset: 0x138 AES Initial Vector Word 2 Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[31:0] |IV |AES Initial Vectors + * | | |x = 0, 1..3. + * | | |Four initial vectors (CRYPTO_AES_IV0, CRYPTO_AES_IV1, CRYPTO_AES_IV2, and CRYPTO_AES_IV3) are for AES operating in CBC, CFB, and OFB mode + * | | |Four registers (CRYPTO_AES_IV0, CRYPTO_AES_IV1, CRYPTO_AES_IV2, and CRYPTO_AES_IV3) act as Nonce counter when the AES engine is operating in CTR mode. + * @var CRYPTO_T::AES_IV3 + * Offset: 0x13C AES Initial Vector Word 3 Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[31:0] |IV |AES Initial Vectors + * | | |x = 0, 1..3. + * | | |Four initial vectors (CRYPTO_AES_IV0, CRYPTO_AES_IV1, CRYPTO_AES_IV2, and CRYPTO_AES_IV3) are for AES operating in CBC, CFB, and OFB mode + * | | |Four registers (CRYPTO_AES_IV0, CRYPTO_AES_IV1, CRYPTO_AES_IV2, and CRYPTO_AES_IV3) act as Nonce counter when the AES engine is operating in CTR mode. + * @var CRYPTO_T::AES_SADDR + * Offset: 0x140 AES DMA Source Address Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[31:0] |SADDR |AES DMA Source Address + * | | |The AES accelerator supports DMA function to transfer the plain text between SRAM memory space and embedded FIFO + * | | |The SADDR keeps the source address of the data buffer where the source text is stored + * | | |Based on the source address, the AES accelerator can read the plain text (encryption) / cipher text (decryption) from SRAM memory space and do AES operation + * | | |The start of source address should be located at word boundary + * | | |In other words, bit 1 and 0 of SADDR are ignored. + * | | |SADDR can be read and written + * | | |Writing to SADDR while the AES accelerator is operating doesn't affect the current AES operation + * | | |But the value of SADDR will be updated later on + * | | |Consequently, software can prepare the DMA source address for the next AES operation. + * | | |In DMA mode, software can update the next CRYPTO_AES_SADDR before triggering START. + * | | |The value of CRYPTO_AES_SADDR and CRYPTO_AES_DADDR can be the same. + * @var CRYPTO_T::AES_DADDR + * Offset: 0x144 AES DMA Destination Address Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[31:0] |DADDR |AES DMA Destination Address + * | | |The AES accelerator supports DMA function to transfer the cipher text between SRAM memory space and embedded FIFO + * | | |The DADDR keeps the destination address of the data buffer where the engine output's text will be stored + * | | |Based on the destination address, the AES accelerator can write the cipher text (encryption) / plain text (decryption) back to SRAM memory space after the AES operation is finished + * | | |The start of destination address should be located at word boundary + * | | |In other words, bit 1 and 0 of DADDR are ignored. + * | | |DADDR can be read and written + * | | |Writing to DADDR while the AES accelerator is operating doesn't affect the current AES operation + * | | |But the value of DADDR will be updated later on + * | | |Consequently, software can prepare the destination address for the next AES operation. + * | | |In DMA mode, software can update the next CRYPTO_AES_DADDR before triggering START. + * | | |The value of CRYPTO_AES_SADDR and CRYPTO_AES_DADDR can be the same. + * @var CRYPTO_T::AES_CNT + * Offset: 0x148 AES Byte Count Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[31:0] |CNT |AES Byte Count + * | | |The CRYPTO_AES_CNT keeps the byte count of source text that is for the AES engine operating in DMA mode + * | | |The CRYPTO_AES_CNT is 32-bit and the maximum of byte count is 4G bytes. + * | | |CRYPTO_AES_CNT can be read and written + * | | |Writing to CRYPTO_AES_CNT while the AES accelerator is operating doesn't affect the current AES operation + * | | |But the value of CRYPTO_AES_CNT will be updated later on + * | | |Consequently, software can prepare the byte count of data for the next AES operation. + * | | |According to CBC-CS1, CBC-CS2, and CBC-CS3 standard, the count of operation data must be more than 16 bytes + * | | |Operations that are qual or less than one block will output unexpected result. + * | | |In Non-DMA ECB, CBC, CFB, OFB, CTR, CCM and GCM mode, CRYPTO_AES_CNT must be set as byte count for the last block of data before feeding in the last block of data + * | | |In Non-DMA CBC-CS1, CBC-CS2, and CBC-CS3 mode, CRYPTO_AES_CNT must be set as byte count for the last two blocks of data before feeding in the last two blocks of data. + * | | |In AES GCM mode without DMA cascade function, the value of CRYPTO_AES_CNT is equal to the total value of {CRYPTO_AES_GCM_IVCNT1, CRYPTO_AES_GCM_IVCNT0}, {CRYPTO_AES_GCM_ACNT1, CRYPTO_AES_GCM_ACNT0} and {CRYPTO_AES_GCM_PCNT1, CRYPTO_AES_GCM_PCNT0}. + * | | |In AES GCM mode with DMA cascade function, the value of CRYPTO_AES_CNT represents the byte count of source text in this cascade function + * | | |Thus, the value of CRYPTO_AES_CNT is less than or equal to the total value of {CRYPTO_AES_GCM_IVCNT1, CRYPTO_AES_GCM_IVCNT0}, {CRYPTO_AES_GCM_ACNT1, CRYPTO_AES_GCM_ACNT0} and {CRYPTO_AES_GCM_PCNT1, CRYPTO_AES_GCM_PCNT0} and must be block alignment. + * | | |In AES CCM mode without DMA cascade function, the value of CRYPTO_AES_CNT is equal to the total value of {CRYPTO_AES_GCM_ACNT1, CRYPTO_AES_GCM_ACNT0} and {CRYPTO_AES_GCM_PCNT1, CRYPTO_AES_GCM_PCNT0}. + * | | |In AES CCM mode with DMA cascade function, the value of CRYPTO_AES_CNT represents the byte count of source text in this cascade function + * | | |Thus, the value of CRYPTO_AES_CNT is less than or equal to the total value of {CRYPTO_AES_GCM_ACNT1, CRYPTO_AES_GCM_ACNT0} and {CRYPTO_AES_GCM_PCNT1, CRYPTO_AES_GCM_PCNT0} and must be block alignment, except for the last block of plaintext or ciphertext. + * @var CRYPTO_T::HMAC_CTL + * Offset: 0x300 SHA/HMAC Control Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[0] |START |SHA/HMAC Engine Start + * | | |0 = No effect. + * | | |1 = Start SHA/HMAC engine. BUSY flag will be set. + * | | |Note: This bit is always 0 when it is read back. + * |[1] |STOP |SHA/HMAC Engine Stop + * | | |0 = No effect. + * | | |1 = Stop SHA/HMAC engine. + * | | |Note: This bit is always 0 when it is read back. + * |[4] |DMAFIRST |SHA/HMAC First Block in Cascade function + * | | |This bit must be set as feeding in first byte of data. + * |[5] |DMALAST |SHA/HMAC Last Block + * | | |This bit must be set as feeding in last byte of data. + * |[6] |DMACSCAD |SHA/HMAC Engine DMA with Cascade Mode + * | | |0 = DMA cascade function Disabled. + * | | |1 = In DMA cascade mode, software can update DMA source address register, destination address register, and byte count register during a cascade operation, without finishing the accelerator operation. + * |[7] |DMAEN |SHA/HMAC Engine DMA Enable Bit + * | | |0 = SHA/HMAC DMA engine Disabled. + * | | |SHA/HMAC engine operates in Non-DMA mode. The data need to be written in CRYPTO_HMAC_DATIN. + * | | |1 = SHA/HMAC DMA engine Enabled. + * | | |SHA/HMAC engine operates in DMA mode, and data movement from/to the engine is done by DMA logic. + * |[10:8] |OPMODE |SHA/HMAC Engine Operation Modes + * | | |When SHA3EN=0,. + * | | |0x0xx: SHA1-160 + * | | |0x100: SHA2-256 + * | | |0x101: SHA2-224 + * | | |0x110: SHA2-512 + * | | |0x111: SHA2-384 + * | | |When SHA3EN=1,. + * | | |0x100: SHA3-256 + * | | |0x101: SHA3-224 + * | | |0x110: SHA3-512 + * | | |0x111: SHA3-384 + * | | |0x000: SHAKE128 + * | | |0x001: SHAKE256 + * | | |Note: These bits can be read and written. But writing to them wouldn't take effect as BUSY is 1. + * | | |Note: When SM3EN=1, SHA/HMAC only execute SM3 and then generate 256 bits digest. + * | | |Note: When MD5EN=1, SHA/HMAC only execute MD5 and then generate 128 bits digest. + * |[11] |HMACEN |HMAC_SHA Engine Operating Mode + * | | |0 = Execute SHA function. + * | | |1 = Execute HMAC function. + * |[12] |SHA3EN |SHA3 Engine Enable Bit + * | | |0 = Execute other function. + * | | |1 = Execute SHA3 function if SM3EN=0 and MD5EN=0. + * |[13] |SM3EN |SM3 Engine Enable Bit + * | | |0 = Execute other function. + * | | |1 = Execute SM3 function if SHA3EN=0 and MD5EN=0. + * |[14] |MD5EN |MD5 Engine Enable Bit + * | | |0 = Execute other function. + * | | |1 = Execute MD5 function if SHA3EN=0 and SM3EN=0. + * |[20] |FBIN |Feedback Input to SHA/HMAC Via DMA Automatically + * | | |0 = DMA automatic feedback input function Disabled. + * | | |1 = DMA automatic feedback input function Enabled when DMAEN = 1. + * |[21] |FBOUT |Feedback Output From SHA/HMAC Via DMA Automatically + * | | |0 = DMA automatic feedback output function Disabled. + * | | |1 = DMA automatic feedback output function Enabled when DMAEN = 1. + * |[22] |OUTSWAP |SHA/HMAC Engine Output Data Swap + * | | |0 = Keep the original order. + * | | |1 = The order that CPU feeds data to the accelerator will be changed from {byte3, byte2, byte1, byte0} to {byte0, byte1, byte2, byte3}. + * |[23] |INSWAP |SHA/HMAC Engine Input Data Swap + * | | |0 = Keep the original order. + * | | |1 = The order that CPU feeds data to the accelerator will be changed from {byte3, byte2, byte1, byte0} to {byte0, byte1, byte2, byte3}. + * |[24] |NEXTDGST |SHAKE128/256 Next Digest Start + * | | |0 = No effect. + * | | |1 = Start SHAKE engine to generate the next digest only when SHAKEBUSY is 0 + * | | |BUSY and SHAKEBUSY flag will be set. + * |[25] |FINISHDGST|SHAKE128/256 Next Digest Finish + * | | |0 = No effect. + * | | |1 = finish generating the next digest. + * @var CRYPTO_T::HMAC_STS + * Offset: 0x304 SHA/HMAC Status Flag + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[0] |BUSY |SHA/HMAC Engine Busy + * | | |0 = SHA/HMAC engine is idle or finished. + * | | |1 = SHA/HMAC engine is busy. + * |[1] |DMABUSY |SHA/HMAC Engine DMA Busy Flag + * | | |0 = SHA/HMAC DMA engine is idle or finished. + * | | |1 = SHA/HMAC DMA engine is busy. + * |[2] |SHAKEBUSY |SHAKE Engine Busy Flag + * | | |0 = SHAKE engine is idle or finished. + * | | |1 = SHAKE engine is busy. + * |[8] |DMAERR |SHA/HMAC Engine DMA Error Flag + * | | |0 = Show the SHA/HMAC engine access normal. + * | | |1 = Show the SHA/HMAC engine access error. + * |[9] |KSERR |HMAC Engine Access Key Store Error Flag + * | | |0 = No error. + * | | |1 = Access error will stop HMAC engine. + * |[16] |DATINREQ |SHA/HMAC Non-DMA Mode Data Input Request + * | | |0 = No effect. + * | | |1 = Request SHA/HMAC Non-DMA mode data input. + * @var CRYPTO_T::HMAC_DGST0 + * Offset: 0x308 SHA/HMAC Output Feedback Data 0 + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[31:0] |DGST |SHA/HMAC Output Feedback Data Output Register + * | | |For SHA-160, the digest is stored in CRYPTO_HMAC_DGST0 ~ CRYPTO_HMAC_DGST4. + * | | |For SHA-224, the digest is stored in CRYPTO_HMAC_DGST0 ~ CRYPTO_HMAC_DGST6. + * | | |For SHA-256, the digest is stored in CRYPTO_HMAC_DGST0 ~ CRYPTO_HMAC_DGST7. + * | | |For SHA-384, the digest is stored in CRYPTO_HMAC_DGST0 ~ CRYPTO_HMAC_DGST11. + * | | |For SHA-512, the digest is stored in CRYPTO_HMAC_DGST0 ~ CRYPTO_HMAC_DGST15. + * @var CRYPTO_T::HMAC_DGST1 + * Offset: 0x30C SHA/HMAC Output Feedback Data 1 + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[31:0] |DGST |SHA/HMAC Output Feedback Data Output Register + * | | |For SHA-160, the digest is stored in CRYPTO_HMAC_DGST0 ~ CRYPTO_HMAC_DGST4. + * | | |For SHA-224, the digest is stored in CRYPTO_HMAC_DGST0 ~ CRYPTO_HMAC_DGST6. + * | | |For SHA-256, the digest is stored in CRYPTO_HMAC_DGST0 ~ CRYPTO_HMAC_DGST7. + * | | |For SHA-384, the digest is stored in CRYPTO_HMAC_DGST0 ~ CRYPTO_HMAC_DGST11. + * | | |For SHA-512, the digest is stored in CRYPTO_HMAC_DGST0 ~ CRYPTO_HMAC_DGST15. + * @var CRYPTO_T::HMAC_DGST2 + * Offset: 0x310 SHA/HMAC Output Feedback Data 2 + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[31:0] |DGST |SHA/HMAC Output Feedback Data Output Register + * | | |For SHA-160, the digest is stored in CRYPTO_HMAC_DGST0 ~ CRYPTO_HMAC_DGST4. + * | | |For SHA-224, the digest is stored in CRYPTO_HMAC_DGST0 ~ CRYPTO_HMAC_DGST6. + * | | |For SHA-256, the digest is stored in CRYPTO_HMAC_DGST0 ~ CRYPTO_HMAC_DGST7. + * | | |For SHA-384, the digest is stored in CRYPTO_HMAC_DGST0 ~ CRYPTO_HMAC_DGST11. + * | | |For SHA-512, the digest is stored in CRYPTO_HMAC_DGST0 ~ CRYPTO_HMAC_DGST15. + * @var CRYPTO_T::HMAC_DGST3 + * Offset: 0x314 SHA/HMAC Output Feedback Data 3 + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[31:0] |DGST |SHA/HMAC Output Feedback Data Output Register + * | | |For SHA-160, the digest is stored in CRYPTO_HMAC_DGST0 ~ CRYPTO_HMAC_DGST4. + * | | |For SHA-224, the digest is stored in CRYPTO_HMAC_DGST0 ~ CRYPTO_HMAC_DGST6. + * | | |For SHA-256, the digest is stored in CRYPTO_HMAC_DGST0 ~ CRYPTO_HMAC_DGST7. + * | | |For SHA-384, the digest is stored in CRYPTO_HMAC_DGST0 ~ CRYPTO_HMAC_DGST11. + * | | |For SHA-512, the digest is stored in CRYPTO_HMAC_DGST0 ~ CRYPTO_HMAC_DGST15. + * @var CRYPTO_T::HMAC_DGST4 + * Offset: 0x318 SHA/HMAC Output Feedback Data 4 + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[31:0] |DGST |SHA/HMAC Output Feedback Data Output Register + * | | |For SHA-160, the digest is stored in CRYPTO_HMAC_DGST0 ~ CRYPTO_HMAC_DGST4. + * | | |For SHA-224, the digest is stored in CRYPTO_HMAC_DGST0 ~ CRYPTO_HMAC_DGST6. + * | | |For SHA-256, the digest is stored in CRYPTO_HMAC_DGST0 ~ CRYPTO_HMAC_DGST7. + * | | |For SHA-384, the digest is stored in CRYPTO_HMAC_DGST0 ~ CRYPTO_HMAC_DGST11. + * | | |For SHA-512, the digest is stored in CRYPTO_HMAC_DGST0 ~ CRYPTO_HMAC_DGST15. + * @var CRYPTO_T::HMAC_DGST5 + * Offset: 0x31C SHA/HMAC Output Feedback Data 5 + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[31:0] |DGST |SHA/HMAC Output Feedback Data Output Register + * | | |For SHA-160, the digest is stored in CRYPTO_HMAC_DGST0 ~ CRYPTO_HMAC_DGST4. + * | | |For SHA-224, the digest is stored in CRYPTO_HMAC_DGST0 ~ CRYPTO_HMAC_DGST6. + * | | |For SHA-256, the digest is stored in CRYPTO_HMAC_DGST0 ~ CRYPTO_HMAC_DGST7. + * | | |For SHA-384, the digest is stored in CRYPTO_HMAC_DGST0 ~ CRYPTO_HMAC_DGST11. + * | | |For SHA-512, the digest is stored in CRYPTO_HMAC_DGST0 ~ CRYPTO_HMAC_DGST15. + * @var CRYPTO_T::HMAC_DGST6 + * Offset: 0x320 SHA/HMAC Output Feedback Data 6 + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[31:0] |DGST |SHA/HMAC Output Feedback Data Output Register + * | | |For SHA-160, the digest is stored in CRYPTO_HMAC_DGST0 ~ CRYPTO_HMAC_DGST4. + * | | |For SHA-224, the digest is stored in CRYPTO_HMAC_DGST0 ~ CRYPTO_HMAC_DGST6. + * | | |For SHA-256, the digest is stored in CRYPTO_HMAC_DGST0 ~ CRYPTO_HMAC_DGST7. + * | | |For SHA-384, the digest is stored in CRYPTO_HMAC_DGST0 ~ CRYPTO_HMAC_DGST11. + * | | |For SHA-512, the digest is stored in CRYPTO_HMAC_DGST0 ~ CRYPTO_HMAC_DGST15. + * @var CRYPTO_T::HMAC_DGST7 + * Offset: 0x324 SHA/HMAC Output Feedback Data 7 + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[31:0] |DGST |SHA/HMAC Output Feedback Data Output Register + * | | |For SHA-160, the digest is stored in CRYPTO_HMAC_DGST0 ~ CRYPTO_HMAC_DGST4. + * | | |For SHA-224, the digest is stored in CRYPTO_HMAC_DGST0 ~ CRYPTO_HMAC_DGST6. + * | | |For SHA-256, the digest is stored in CRYPTO_HMAC_DGST0 ~ CRYPTO_HMAC_DGST7. + * | | |For SHA-384, the digest is stored in CRYPTO_HMAC_DGST0 ~ CRYPTO_HMAC_DGST11. + * | | |For SHA-512, the digest is stored in CRYPTO_HMAC_DGST0 ~ CRYPTO_HMAC_DGST15. + * @var CRYPTO_T::HMAC_DGST8 + * Offset: 0x328 SHA/HMAC Output Feedback Data 8 + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[31:0] |DGST |SHA/HMAC Output Feedback Data Output Register + * | | |For SHA-160, the digest is stored in CRYPTO_HMAC_DGST0 ~ CRYPTO_HMAC_DGST4. + * | | |For SHA-224, the digest is stored in CRYPTO_HMAC_DGST0 ~ CRYPTO_HMAC_DGST6. + * | | |For SHA-256, the digest is stored in CRYPTO_HMAC_DGST0 ~ CRYPTO_HMAC_DGST7. + * | | |For SHA-384, the digest is stored in CRYPTO_HMAC_DGST0 ~ CRYPTO_HMAC_DGST11. + * | | |For SHA-512, the digest is stored in CRYPTO_HMAC_DGST0 ~ CRYPTO_HMAC_DGST15. + * @var CRYPTO_T::HMAC_DGST9 + * Offset: 0x32C SHA/HMAC Output Feedback Data 9 + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[31:0] |DGST |SHA/HMAC Output Feedback Data Output Register + * | | |For SHA-160, the digest is stored in CRYPTO_HMAC_DGST0 ~ CRYPTO_HMAC_DGST4. + * | | |For SHA-224, the digest is stored in CRYPTO_HMAC_DGST0 ~ CRYPTO_HMAC_DGST6. + * | | |For SHA-256, the digest is stored in CRYPTO_HMAC_DGST0 ~ CRYPTO_HMAC_DGST7. + * | | |For SHA-384, the digest is stored in CRYPTO_HMAC_DGST0 ~ CRYPTO_HMAC_DGST11. + * | | |For SHA-512, the digest is stored in CRYPTO_HMAC_DGST0 ~ CRYPTO_HMAC_DGST15. + * @var CRYPTO_T::HMAC_DGST10 + * Offset: 0x330 SHA/HMAC Output Feedback Data 10 + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[31:0] |DGST |SHA/HMAC Output Feedback Data Output Register + * | | |For SHA-160, the digest is stored in CRYPTO_HMAC_DGST0 ~ CRYPTO_HMAC_DGST4. + * | | |For SHA-224, the digest is stored in CRYPTO_HMAC_DGST0 ~ CRYPTO_HMAC_DGST6. + * | | |For SHA-256, the digest is stored in CRYPTO_HMAC_DGST0 ~ CRYPTO_HMAC_DGST7. + * | | |For SHA-384, the digest is stored in CRYPTO_HMAC_DGST0 ~ CRYPTO_HMAC_DGST11. + * | | |For SHA-512, the digest is stored in CRYPTO_HMAC_DGST0 ~ CRYPTO_HMAC_DGST15. + * @var CRYPTO_T::HMAC_DGST11 + * Offset: 0x334 SHA/HMAC Output Feedback Data 11 + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[31:0] |DGST |SHA/HMAC Output Feedback Data Output Register + * | | |For SHA-160, the digest is stored in CRYPTO_HMAC_DGST0 ~ CRYPTO_HMAC_DGST4. + * | | |For SHA-224, the digest is stored in CRYPTO_HMAC_DGST0 ~ CRYPTO_HMAC_DGST6. + * | | |For SHA-256, the digest is stored in CRYPTO_HMAC_DGST0 ~ CRYPTO_HMAC_DGST7. + * | | |For SHA-384, the digest is stored in CRYPTO_HMAC_DGST0 ~ CRYPTO_HMAC_DGST11. + * | | |For SHA-512, the digest is stored in CRYPTO_HMAC_DGST0 ~ CRYPTO_HMAC_DGST15. + * @var CRYPTO_T::HMAC_DGST12 + * Offset: 0x338 SHA/HMAC Output Feedback Data 12 + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[31:0] |DGST |SHA/HMAC Output Feedback Data Output Register + * | | |For SHA-160, the digest is stored in CRYPTO_HMAC_DGST0 ~ CRYPTO_HMAC_DGST4. + * | | |For SHA-224, the digest is stored in CRYPTO_HMAC_DGST0 ~ CRYPTO_HMAC_DGST6. + * | | |For SHA-256, the digest is stored in CRYPTO_HMAC_DGST0 ~ CRYPTO_HMAC_DGST7. + * | | |For SHA-384, the digest is stored in CRYPTO_HMAC_DGST0 ~ CRYPTO_HMAC_DGST11. + * | | |For SHA-512, the digest is stored in CRYPTO_HMAC_DGST0 ~ CRYPTO_HMAC_DGST15. + * @var CRYPTO_T::HMAC_DGST13 + * Offset: 0x33C SHA/HMAC Output Feedback Data 13 + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[31:0] |DGST |SHA/HMAC Output Feedback Data Output Register + * | | |For SHA-160, the digest is stored in CRYPTO_HMAC_DGST0 ~ CRYPTO_HMAC_DGST4. + * | | |For SHA-224, the digest is stored in CRYPTO_HMAC_DGST0 ~ CRYPTO_HMAC_DGST6. + * | | |For SHA-256, the digest is stored in CRYPTO_HMAC_DGST0 ~ CRYPTO_HMAC_DGST7. + * | | |For SHA-384, the digest is stored in CRYPTO_HMAC_DGST0 ~ CRYPTO_HMAC_DGST11. + * | | |For SHA-512, the digest is stored in CRYPTO_HMAC_DGST0 ~ CRYPTO_HMAC_DGST15. + * @var CRYPTO_T::HMAC_DGST14 + * Offset: 0x340 SHA/HMAC Output Feedback Data 14 + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[31:0] |DGST |SHA/HMAC Output Feedback Data Output Register + * | | |For SHA-160, the digest is stored in CRYPTO_HMAC_DGST0 ~ CRYPTO_HMAC_DGST4. + * | | |For SHA-224, the digest is stored in CRYPTO_HMAC_DGST0 ~ CRYPTO_HMAC_DGST6. + * | | |For SHA-256, the digest is stored in CRYPTO_HMAC_DGST0 ~ CRYPTO_HMAC_DGST7. + * | | |For SHA-384, the digest is stored in CRYPTO_HMAC_DGST0 ~ CRYPTO_HMAC_DGST11. + * | | |For SHA-512, the digest is stored in CRYPTO_HMAC_DGST0 ~ CRYPTO_HMAC_DGST15. + * @var CRYPTO_T::HMAC_DGST15 + * Offset: 0x344 SHA/HMAC Output Feedback Data 15 + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[31:0] |DGST |SHA/HMAC Output Feedback Data Output Register + * | | |For SHA-160, the digest is stored in CRYPTO_HMAC_DGST0 ~ CRYPTO_HMAC_DGST4. + * | | |For SHA-224, the digest is stored in CRYPTO_HMAC_DGST0 ~ CRYPTO_HMAC_DGST6. + * | | |For SHA-256, the digest is stored in CRYPTO_HMAC_DGST0 ~ CRYPTO_HMAC_DGST7. + * | | |For SHA-384, the digest is stored in CRYPTO_HMAC_DGST0 ~ CRYPTO_HMAC_DGST11. + * | | |For SHA-512, the digest is stored in CRYPTO_HMAC_DGST0 ~ CRYPTO_HMAC_DGST15. + * @var CRYPTO_T::HMAC_KEYCNT + * Offset: 0x348 SHA/HMAC Key Byte Count Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[31:0] |KEYCNT |SHA/HMAC Key Byte Count + * | | |The CRYPTO_HMAC_KEYCNT keeps the byte count of key that SHA/HMAC engine operates + * | | |The register is 32-bit and the maximum byte count is 4G bytes + * | | |It can be read and written. + * | | |Writing to the register CRYPTO_HMAC_KEYCNT as the SHA/HMAC accelerator operating doesn't affect the current SHA/HMAC operation + * | | |But the value of CRYPTO_HMAC_KEYCNT will be updated later on + * | | |Consequently, software can prepare the key count for the next SHA/HMAC operation. + * @var CRYPTO_T::HMAC_SADDR + * Offset: 0x34C SHA/HMAC DMA Source Address Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[31:0] |SADDR |SHA/HMAC DMA Source Address + * | | |The SHA/HMAC accelerator supports DMA function to transfer the plain text between SRAM memory space and embedded FIFO + * | | |The CRYPTO_HMAC_SADDR keeps the source address of the data buffer where the source text is stored + * | | |Based on the source address, the SHA/HMAC accelerator can read the plain text from SRAM memory space and do SHA/HMAC operation + * | | |The start of source address should be located at word boundary + * | | |In other words, bit 1 and 0 of CRYPTO_HMAC_SADDR are ignored. + * | | |CRYPTO_HMAC_SADDR can be read and written + * | | |Writing to CRYPTO_HMAC_SADDR while the SHA/HMAC accelerator is operating doesn't affect the current SHA/HMAC operation + * | | |But the value of CRYPTO_HMAC_SADDR will be updated later on + * | | |Consequently, software can prepare the DMA source address for the next SHA/HMAC operation. + * | | |In DMA mode, software can update the next CRYPTO_HMAC_SADDR before triggering START. + * | | |CRYPTO_HMAC_SADDR and CRYPTO_HMAC_DADDR can be the same in the value. + * @var CRYPTO_T::HMAC_DMACNT + * Offset: 0x350 SHA/HMAC Byte Count Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[31:0] |DMACNT |SHA/HMAC Operation Byte Count + * | | |The CRYPTO_HMAC_DMACNT keeps the byte count of source text that is for the SHA/HMAC engine operating in DMA mode + * | | |The CRYPTO_HMAC_DMACNT is 32-bit and the maximum of byte count is 4G bytes. + * | | |CRYPTO_HMAC_DMACNT can be read and written + * | | |Writing to CRYPTO_HMAC_DMACNT while the SHA/HMAC accelerator is operating doesn't affect the current SHA/HMAC operation + * | | |But the value of CRYPTO_HMAC_DMACNT will be updated later on + * | | |Consequently, software can prepare the byte count of data for the next SHA/HMAC operation. + * | | |In Non-DMA mode, CRYPTO_HMAC_DMACNT must be set as the byte count of the last block before feeding in the last block of data. + * @var CRYPTO_T::HMAC_DATIN + * Offset: 0x354 SHA/HMAC Engine Non-DMA Mode Data Input Port Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[31:0] |DATIN |SHA/HMAC Engine Input Port + * | | |CPU feeds data to SHA/HMAC engine through this port by checking CRYPTO_HMAC_STS + * | | |Feed data as DATINREQ is 1. + * @var CRYPTO_T::HMAC_FDBCK0 + * Offset: 0x358 SHA/HMAC Output Feedback Data 0 After SHA/HMAC Operation + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[31:0] |FDBCK |SHA/HMAC Feedback Information + * | | |The feedback value is 1728 bits in size for SHA1/2 and 2784 bits in size for SHA3. + * | | |The SHA/HMAC engine uses the data from CRYPTO_HMAC_FDBCKx as the data inputted to CRYPTO_HMAC_FDBCKx for the next block in DMA cascade mode. + * | | |The SHA/HMAC engine outputs feedback information for initial setting in the next block's operation + * | | |Software can store that feedback value temporarily + * | | |After switching back, fill the stored feedback value to CRYPTO_HMAC_FDBCKx in the same operation, and then continue the operation with the original setting. + * @var CRYPTO_T::HMAC_FDBCK1 + * Offset: 0x35C SHA/HMAC Output Feedback Data 1 After SHA/HMAC Operation + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[31:0] |FDBCK |SHA/HMAC Feedback Information + * | | |The feedback value is 1728 bits in size for SHA1/2 and 2784 bits in size for SHA3. + * | | |The SHA/HMAC engine uses the data from CRYPTO_HMAC_FDBCKx as the data inputted to CRYPTO_HMAC_FDBCKx for the next block in DMA cascade mode. + * | | |The SHA/HMAC engine outputs feedback information for initial setting in the next block's operation + * | | |Software can store that feedback value temporarily + * | | |After switching back, fill the stored feedback value to CRYPTO_HMAC_FDBCKx in the same operation, and then continue the operation with the original setting. + * @var CRYPTO_T::HMAC_FDBCK2 + * Offset: 0x360 SHA/HMAC Output Feedback Data 2 After SHA/HMAC Operation + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[31:0] |FDBCK |SHA/HMAC Feedback Information + * | | |The feedback value is 1728 bits in size for SHA1/2 and 2784 bits in size for SHA3. + * | | |The SHA/HMAC engine uses the data from CRYPTO_HMAC_FDBCKx as the data inputted to CRYPTO_HMAC_FDBCKx for the next block in DMA cascade mode. + * | | |The SHA/HMAC engine outputs feedback information for initial setting in the next block's operation + * | | |Software can store that feedback value temporarily + * | | |After switching back, fill the stored feedback value to CRYPTO_HMAC_FDBCKx in the same operation, and then continue the operation with the original setting. + * @var CRYPTO_T::HMAC_FDBCK3 + * Offset: 0x364 SHA/HMAC Output Feedback Data 3 After SHA/HMAC Operation + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[31:0] |FDBCK |SHA/HMAC Feedback Information + * | | |The feedback value is 1728 bits in size for SHA1/2 and 2784 bits in size for SHA3. + * | | |The SHA/HMAC engine uses the data from CRYPTO_HMAC_FDBCKx as the data inputted to CRYPTO_HMAC_FDBCKx for the next block in DMA cascade mode. + * | | |The SHA/HMAC engine outputs feedback information for initial setting in the next block's operation + * | | |Software can store that feedback value temporarily + * | | |After switching back, fill the stored feedback value to CRYPTO_HMAC_FDBCKx in the same operation, and then continue the operation with the original setting. + * @var CRYPTO_T::HMAC_FDBCK4 + * Offset: 0x368 SHA/HMAC Output Feedback Data 4 After SHA/HMAC Operation + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[31:0] |FDBCK |SHA/HMAC Feedback Information + * | | |The feedback value is 1728 bits in size for SHA1/2 and 2784 bits in size for SHA3. + * | | |The SHA/HMAC engine uses the data from CRYPTO_HMAC_FDBCKx as the data inputted to CRYPTO_HMAC_FDBCKx for the next block in DMA cascade mode. + * | | |The SHA/HMAC engine outputs feedback information for initial setting in the next block's operation + * | | |Software can store that feedback value temporarily + * | | |After switching back, fill the stored feedback value to CRYPTO_HMAC_FDBCKx in the same operation, and then continue the operation with the original setting. + * @var CRYPTO_T::HMAC_FDBCK5 + * Offset: 0x36C SHA/HMAC Output Feedback Data 5 After SHA/HMAC Operation + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[31:0] |FDBCK |SHA/HMAC Feedback Information + * | | |The feedback value is 1728 bits in size for SHA1/2 and 2784 bits in size for SHA3. + * | | |The SHA/HMAC engine uses the data from CRYPTO_HMAC_FDBCKx as the data inputted to CRYPTO_HMAC_FDBCKx for the next block in DMA cascade mode. + * | | |The SHA/HMAC engine outputs feedback information for initial setting in the next block's operation + * | | |Software can store that feedback value temporarily + * | | |After switching back, fill the stored feedback value to CRYPTO_HMAC_FDBCKx in the same operation, and then continue the operation with the original setting. + * @var CRYPTO_T::HMAC_FDBCK6 + * Offset: 0x370 SHA/HMAC Output Feedback Data 6 After SHA/HMAC Operation + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[31:0] |FDBCK |SHA/HMAC Feedback Information + * | | |The feedback value is 1728 bits in size for SHA1/2 and 2784 bits in size for SHA3. + * | | |The SHA/HMAC engine uses the data from CRYPTO_HMAC_FDBCKx as the data inputted to CRYPTO_HMAC_FDBCKx for the next block in DMA cascade mode. + * | | |The SHA/HMAC engine outputs feedback information for initial setting in the next block's operation + * | | |Software can store that feedback value temporarily + * | | |After switching back, fill the stored feedback value to CRYPTO_HMAC_FDBCKx in the same operation, and then continue the operation with the original setting. + * @var CRYPTO_T::HMAC_FDBCK7 + * Offset: 0x374 SHA/HMAC Output Feedback Data 7 After SHA/HMAC Operation + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[31:0] |FDBCK |SHA/HMAC Feedback Information + * | | |The feedback value is 1728 bits in size for SHA1/2 and 2784 bits in size for SHA3. + * | | |The SHA/HMAC engine uses the data from CRYPTO_HMAC_FDBCKx as the data inputted to CRYPTO_HMAC_FDBCKx for the next block in DMA cascade mode. + * | | |The SHA/HMAC engine outputs feedback information for initial setting in the next block's operation + * | | |Software can store that feedback value temporarily + * | | |After switching back, fill the stored feedback value to CRYPTO_HMAC_FDBCKx in the same operation, and then continue the operation with the original setting. + * @var CRYPTO_T::HMAC_FDBCK8 + * Offset: 0x378 SHA/HMAC Output Feedback Data 8 After SHA/HMAC Operation + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[31:0] |FDBCK |SHA/HMAC Feedback Information + * | | |The feedback value is 1728 bits in size for SHA1/2 and 2784 bits in size for SHA3. + * | | |The SHA/HMAC engine uses the data from CRYPTO_HMAC_FDBCKx as the data inputted to CRYPTO_HMAC_FDBCKx for the next block in DMA cascade mode. + * | | |The SHA/HMAC engine outputs feedback information for initial setting in the next block's operation + * | | |Software can store that feedback value temporarily + * | | |After switching back, fill the stored feedback value to CRYPTO_HMAC_FDBCKx in the same operation, and then continue the operation with the original setting. + * @var CRYPTO_T::HMAC_FDBCK9 + * Offset: 0x37C SHA/HMAC Output Feedback Data 9 After SHA/HMAC Operation + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[31:0] |FDBCK |SHA/HMAC Feedback Information + * | | |The feedback value is 1728 bits in size for SHA1/2 and 2784 bits in size for SHA3. + * | | |The SHA/HMAC engine uses the data from CRYPTO_HMAC_FDBCKx as the data inputted to CRYPTO_HMAC_FDBCKx for the next block in DMA cascade mode. + * | | |The SHA/HMAC engine outputs feedback information for initial setting in the next block's operation + * | | |Software can store that feedback value temporarily + * | | |After switching back, fill the stored feedback value to CRYPTO_HMAC_FDBCKx in the same operation, and then continue the operation with the original setting. + * @var CRYPTO_T::HMAC_FDBCK10 + * Offset: 0x380 SHA/HMAC Output Feedback Data 10 After SHA/HMAC Operation + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[31:0] |FDBCK |SHA/HMAC Feedback Information + * | | |The feedback value is 1728 bits in size for SHA1/2 and 2784 bits in size for SHA3. + * | | |The SHA/HMAC engine uses the data from CRYPTO_HMAC_FDBCKx as the data inputted to CRYPTO_HMAC_FDBCKx for the next block in DMA cascade mode. + * | | |The SHA/HMAC engine outputs feedback information for initial setting in the next block's operation + * | | |Software can store that feedback value temporarily + * | | |After switching back, fill the stored feedback value to CRYPTO_HMAC_FDBCKx in the same operation, and then continue the operation with the original setting. + * @var CRYPTO_T::HMAC_FDBCK11 + * Offset: 0x384 SHA/HMAC Output Feedback Data 11 After SHA/HMAC Operation + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[31:0] |FDBCK |SHA/HMAC Feedback Information + * | | |The feedback value is 1728 bits in size for SHA1/2 and 2784 bits in size for SHA3. + * | | |The SHA/HMAC engine uses the data from CRYPTO_HMAC_FDBCKx as the data inputted to CRYPTO_HMAC_FDBCKx for the next block in DMA cascade mode. + * | | |The SHA/HMAC engine outputs feedback information for initial setting in the next block's operation + * | | |Software can store that feedback value temporarily + * | | |After switching back, fill the stored feedback value to CRYPTO_HMAC_FDBCKx in the same operation, and then continue the operation with the original setting. + * @var CRYPTO_T::HMAC_FDBCK12 + * Offset: 0x388 SHA/HMAC Output Feedback Data 12 After SHA/HMAC Operation + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[31:0] |FDBCK |SHA/HMAC Feedback Information + * | | |The feedback value is 1728 bits in size for SHA1/2 and 2784 bits in size for SHA3. + * | | |The SHA/HMAC engine uses the data from CRYPTO_HMAC_FDBCKx as the data inputted to CRYPTO_HMAC_FDBCKx for the next block in DMA cascade mode. + * | | |The SHA/HMAC engine outputs feedback information for initial setting in the next block's operation + * | | |Software can store that feedback value temporarily + * | | |After switching back, fill the stored feedback value to CRYPTO_HMAC_FDBCKx in the same operation, and then continue the operation with the original setting. + * @var CRYPTO_T::HMAC_FDBCK13 + * Offset: 0x38C SHA/HMAC Output Feedback Data 13 After SHA/HMAC Operation + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[31:0] |FDBCK |SHA/HMAC Feedback Information + * | | |The feedback value is 1728 bits in size for SHA1/2 and 2784 bits in size for SHA3. + * | | |The SHA/HMAC engine uses the data from CRYPTO_HMAC_FDBCKx as the data inputted to CRYPTO_HMAC_FDBCKx for the next block in DMA cascade mode. + * | | |The SHA/HMAC engine outputs feedback information for initial setting in the next block's operation + * | | |Software can store that feedback value temporarily + * | | |After switching back, fill the stored feedback value to CRYPTO_HMAC_FDBCKx in the same operation, and then continue the operation with the original setting. + * @var CRYPTO_T::HMAC_FDBCK14 + * Offset: 0x390 SHA/HMAC Output Feedback Data 14 After SHA/HMAC Operation + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[31:0] |FDBCK |SHA/HMAC Feedback Information + * | | |The feedback value is 1728 bits in size for SHA1/2 and 2784 bits in size for SHA3. + * | | |The SHA/HMAC engine uses the data from CRYPTO_HMAC_FDBCKx as the data inputted to CRYPTO_HMAC_FDBCKx for the next block in DMA cascade mode. + * | | |The SHA/HMAC engine outputs feedback information for initial setting in the next block's operation + * | | |Software can store that feedback value temporarily + * | | |After switching back, fill the stored feedback value to CRYPTO_HMAC_FDBCKx in the same operation, and then continue the operation with the original setting. + * @var CRYPTO_T::HMAC_FDBCK15 + * Offset: 0x394 SHA/HMAC Output Feedback Data 15 After SHA/HMAC Operation + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[31:0] |FDBCK |SHA/HMAC Feedback Information + * | | |The feedback value is 1728 bits in size for SHA1/2 and 2784 bits in size for SHA3. + * | | |The SHA/HMAC engine uses the data from CRYPTO_HMAC_FDBCKx as the data inputted to CRYPTO_HMAC_FDBCKx for the next block in DMA cascade mode. + * | | |The SHA/HMAC engine outputs feedback information for initial setting in the next block's operation + * | | |Software can store that feedback value temporarily + * | | |After switching back, fill the stored feedback value to CRYPTO_HMAC_FDBCKx in the same operation, and then continue the operation with the original setting. + * @var CRYPTO_T::HMAC_FDBCK16 + * Offset: 0x398 SHA/HMAC Output Feedback Data 16 After SHA/HMAC Operation + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[31:0] |FDBCK |SHA/HMAC Feedback Information + * | | |The feedback value is 1728 bits in size for SHA1/2 and 2784 bits in size for SHA3. + * | | |The SHA/HMAC engine uses the data from CRYPTO_HMAC_FDBCKx as the data inputted to CRYPTO_HMAC_FDBCKx for the next block in DMA cascade mode. + * | | |The SHA/HMAC engine outputs feedback information for initial setting in the next block's operation + * | | |Software can store that feedback value temporarily + * | | |After switching back, fill the stored feedback value to CRYPTO_HMAC_FDBCKx in the same operation, and then continue the operation with the original setting. + * @var CRYPTO_T::HMAC_FDBCK17 + * Offset: 0x39C SHA/HMAC Output Feedback Data 17 After SHA/HMAC Operation + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[31:0] |FDBCK |SHA/HMAC Feedback Information + * | | |The feedback value is 1728 bits in size for SHA1/2 and 2784 bits in size for SHA3. + * | | |The SHA/HMAC engine uses the data from CRYPTO_HMAC_FDBCKx as the data inputted to CRYPTO_HMAC_FDBCKx for the next block in DMA cascade mode. + * | | |The SHA/HMAC engine outputs feedback information for initial setting in the next block's operation + * | | |Software can store that feedback value temporarily + * | | |After switching back, fill the stored feedback value to CRYPTO_HMAC_FDBCKx in the same operation, and then continue the operation with the original setting. + * @var CRYPTO_T::HMAC_FDBCK18 + * Offset: 0x3A0 SHA/HMAC Output Feedback Data 18 After SHA/HMAC Operation + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[31:0] |FDBCK |SHA/HMAC Feedback Information + * | | |The feedback value is 1728 bits in size for SHA1/2 and 2784 bits in size for SHA3. + * | | |The SHA/HMAC engine uses the data from CRYPTO_HMAC_FDBCKx as the data inputted to CRYPTO_HMAC_FDBCKx for the next block in DMA cascade mode. + * | | |The SHA/HMAC engine outputs feedback information for initial setting in the next block's operation + * | | |Software can store that feedback value temporarily + * | | |After switching back, fill the stored feedback value to CRYPTO_HMAC_FDBCKx in the same operation, and then continue the operation with the original setting. + * @var CRYPTO_T::HMAC_FDBCK19 + * Offset: 0x3A4 SHA/HMAC Output Feedback Data 19 After SHA/HMAC Operation + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[31:0] |FDBCK |SHA/HMAC Feedback Information + * | | |The feedback value is 1728 bits in size for SHA1/2 and 2784 bits in size for SHA3. + * | | |The SHA/HMAC engine uses the data from CRYPTO_HMAC_FDBCKx as the data inputted to CRYPTO_HMAC_FDBCKx for the next block in DMA cascade mode. + * | | |The SHA/HMAC engine outputs feedback information for initial setting in the next block's operation + * | | |Software can store that feedback value temporarily + * | | |After switching back, fill the stored feedback value to CRYPTO_HMAC_FDBCKx in the same operation, and then continue the operation with the original setting. + * @var CRYPTO_T::HMAC_FDBCK20 + * Offset: 0x3A8 SHA/HMAC Output Feedback Data 20 After SHA/HMAC Operation + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[31:0] |FDBCK |SHA/HMAC Feedback Information + * | | |The feedback value is 1728 bits in size for SHA1/2 and 2784 bits in size for SHA3. + * | | |The SHA/HMAC engine uses the data from CRYPTO_HMAC_FDBCKx as the data inputted to CRYPTO_HMAC_FDBCKx for the next block in DMA cascade mode. + * | | |The SHA/HMAC engine outputs feedback information for initial setting in the next block's operation + * | | |Software can store that feedback value temporarily + * | | |After switching back, fill the stored feedback value to CRYPTO_HMAC_FDBCKx in the same operation, and then continue the operation with the original setting. + * @var CRYPTO_T::HMAC_FDBCK21 + * Offset: 0x3AC SHA/HMAC Output Feedback Data 21 After SHA/HMAC Operation + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[31:0] |FDBCK |SHA/HMAC Feedback Information + * | | |The feedback value is 1728 bits in size for SHA1/2 and 2784 bits in size for SHA3. + * | | |The SHA/HMAC engine uses the data from CRYPTO_HMAC_FDBCKx as the data inputted to CRYPTO_HMAC_FDBCKx for the next block in DMA cascade mode. + * | | |The SHA/HMAC engine outputs feedback information for initial setting in the next block's operation + * | | |Software can store that feedback value temporarily + * | | |After switching back, fill the stored feedback value to CRYPTO_HMAC_FDBCKx in the same operation, and then continue the operation with the original setting. + * @var CRYPTO_T::HMAC_FDBCK22 + * Offset: 0x3B0 SHA/HMAC Output Feedback Data 22 After SHA/HMAC Operation + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[31:0] |FDBCK |SHA/HMAC Feedback Information + * | | |The feedback value is 1728 bits in size for SHA1/2 and 2784 bits in size for SHA3. + * | | |The SHA/HMAC engine uses the data from CRYPTO_HMAC_FDBCKx as the data inputted to CRYPTO_HMAC_FDBCKx for the next block in DMA cascade mode. + * | | |The SHA/HMAC engine outputs feedback information for initial setting in the next block's operation + * | | |Software can store that feedback value temporarily + * | | |After switching back, fill the stored feedback value to CRYPTO_HMAC_FDBCKx in the same operation, and then continue the operation with the original setting. + * @var CRYPTO_T::HMAC_FDBCK23 + * Offset: 0x3B4 SHA/HMAC Output Feedback Data 23 After SHA/HMAC Operation + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[31:0] |FDBCK |SHA/HMAC Feedback Information + * | | |The feedback value is 1728 bits in size for SHA1/2 and 2784 bits in size for SHA3. + * | | |The SHA/HMAC engine uses the data from CRYPTO_HMAC_FDBCKx as the data inputted to CRYPTO_HMAC_FDBCKx for the next block in DMA cascade mode. + * | | |The SHA/HMAC engine outputs feedback information for initial setting in the next block's operation + * | | |Software can store that feedback value temporarily + * | | |After switching back, fill the stored feedback value to CRYPTO_HMAC_FDBCKx in the same operation, and then continue the operation with the original setting. + * @var CRYPTO_T::HMAC_FDBCK24 + * Offset: 0x3B8 SHA/HMAC Output Feedback Data 24 After SHA/HMAC Operation + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[31:0] |FDBCK |SHA/HMAC Feedback Information + * | | |The feedback value is 1728 bits in size for SHA1/2 and 2784 bits in size for SHA3. + * | | |The SHA/HMAC engine uses the data from CRYPTO_HMAC_FDBCKx as the data inputted to CRYPTO_HMAC_FDBCKx for the next block in DMA cascade mode. + * | | |The SHA/HMAC engine outputs feedback information for initial setting in the next block's operation + * | | |Software can store that feedback value temporarily + * | | |After switching back, fill the stored feedback value to CRYPTO_HMAC_FDBCKx in the same operation, and then continue the operation with the original setting. + * @var CRYPTO_T::HMAC_FDBCK25 + * Offset: 0x3BC SHA/HMAC Output Feedback Data 25 After SHA/HMAC Operation + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[31:0] |FDBCK |SHA/HMAC Feedback Information + * | | |The feedback value is 1728 bits in size for SHA1/2 and 2784 bits in size for SHA3. + * | | |The SHA/HMAC engine uses the data from CRYPTO_HMAC_FDBCKx as the data inputted to CRYPTO_HMAC_FDBCKx for the next block in DMA cascade mode. + * | | |The SHA/HMAC engine outputs feedback information for initial setting in the next block's operation + * | | |Software can store that feedback value temporarily + * | | |After switching back, fill the stored feedback value to CRYPTO_HMAC_FDBCKx in the same operation, and then continue the operation with the original setting. + * @var CRYPTO_T::HMAC_FDBCK26 + * Offset: 0x3C0 SHA/HMAC Output Feedback Data 26 After SHA/HMAC Operation + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[31:0] |FDBCK |SHA/HMAC Feedback Information + * | | |The feedback value is 1728 bits in size for SHA1/2 and 2784 bits in size for SHA3. + * | | |The SHA/HMAC engine uses the data from CRYPTO_HMAC_FDBCKx as the data inputted to CRYPTO_HMAC_FDBCKx for the next block in DMA cascade mode. + * | | |The SHA/HMAC engine outputs feedback information for initial setting in the next block's operation + * | | |Software can store that feedback value temporarily + * | | |After switching back, fill the stored feedback value to CRYPTO_HMAC_FDBCKx in the same operation, and then continue the operation with the original setting. + * @var CRYPTO_T::HMAC_FDBCK27 + * Offset: 0x3C4 SHA/HMAC Output Feedback Data 27 After SHA/HMAC Operation + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[31:0] |FDBCK |SHA/HMAC Feedback Information + * | | |The feedback value is 1728 bits in size for SHA1/2 and 2784 bits in size for SHA3. + * | | |The SHA/HMAC engine uses the data from CRYPTO_HMAC_FDBCKx as the data inputted to CRYPTO_HMAC_FDBCKx for the next block in DMA cascade mode. + * | | |The SHA/HMAC engine outputs feedback information for initial setting in the next block's operation + * | | |Software can store that feedback value temporarily + * | | |After switching back, fill the stored feedback value to CRYPTO_HMAC_FDBCKx in the same operation, and then continue the operation with the original setting. + * @var CRYPTO_T::HMAC_FDBCK28 + * Offset: 0x3C8 SHA/HMAC Output Feedback Data 28 After SHA/HMAC Operation + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[31:0] |FDBCK |SHA/HMAC Feedback Information + * | | |The feedback value is 1728 bits in size for SHA1/2 and 2784 bits in size for SHA3. + * | | |The SHA/HMAC engine uses the data from CRYPTO_HMAC_FDBCKx as the data inputted to CRYPTO_HMAC_FDBCKx for the next block in DMA cascade mode. + * | | |The SHA/HMAC engine outputs feedback information for initial setting in the next block's operation + * | | |Software can store that feedback value temporarily + * | | |After switching back, fill the stored feedback value to CRYPTO_HMAC_FDBCKx in the same operation, and then continue the operation with the original setting. + * @var CRYPTO_T::HMAC_FDBCK29 + * Offset: 0x3CC SHA/HMAC Output Feedback Data 29 After SHA/HMAC Operation + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[31:0] |FDBCK |SHA/HMAC Feedback Information + * | | |The feedback value is 1728 bits in size for SHA1/2 and 2784 bits in size for SHA3. + * | | |The SHA/HMAC engine uses the data from CRYPTO_HMAC_FDBCKx as the data inputted to CRYPTO_HMAC_FDBCKx for the next block in DMA cascade mode. + * | | |The SHA/HMAC engine outputs feedback information for initial setting in the next block's operation + * | | |Software can store that feedback value temporarily + * | | |After switching back, fill the stored feedback value to CRYPTO_HMAC_FDBCKx in the same operation, and then continue the operation with the original setting. + * @var CRYPTO_T::HMAC_FDBCK30 + * Offset: 0x3D0 SHA/HMAC Output Feedback Data 30 After SHA/HMAC Operation + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[31:0] |FDBCK |SHA/HMAC Feedback Information + * | | |The feedback value is 1728 bits in size for SHA1/2 and 2784 bits in size for SHA3. + * | | |The SHA/HMAC engine uses the data from CRYPTO_HMAC_FDBCKx as the data inputted to CRYPTO_HMAC_FDBCKx for the next block in DMA cascade mode. + * | | |The SHA/HMAC engine outputs feedback information for initial setting in the next block's operation + * | | |Software can store that feedback value temporarily + * | | |After switching back, fill the stored feedback value to CRYPTO_HMAC_FDBCKx in the same operation, and then continue the operation with the original setting. + * @var CRYPTO_T::HMAC_FDBCK31 + * Offset: 0x3D4 SHA/HMAC Output Feedback Data 31 After SHA/HMAC Operation + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[31:0] |FDBCK |SHA/HMAC Feedback Information + * | | |The feedback value is 1728 bits in size for SHA1/2 and 2784 bits in size for SHA3. + * | | |The SHA/HMAC engine uses the data from CRYPTO_HMAC_FDBCKx as the data inputted to CRYPTO_HMAC_FDBCKx for the next block in DMA cascade mode. + * | | |The SHA/HMAC engine outputs feedback information for initial setting in the next block's operation + * | | |Software can store that feedback value temporarily + * | | |After switching back, fill the stored feedback value to CRYPTO_HMAC_FDBCKx in the same operation, and then continue the operation with the original setting. + * @var CRYPTO_T::HMAC_FDBCK32 + * Offset: 0x3D8 SHA/HMAC Output Feedback Data 32 After SHA/HMAC Operation + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[31:0] |FDBCK |SHA/HMAC Feedback Information + * | | |The feedback value is 1728 bits in size for SHA1/2 and 2784 bits in size for SHA3. + * | | |The SHA/HMAC engine uses the data from CRYPTO_HMAC_FDBCKx as the data inputted to CRYPTO_HMAC_FDBCKx for the next block in DMA cascade mode. + * | | |The SHA/HMAC engine outputs feedback information for initial setting in the next block's operation + * | | |Software can store that feedback value temporarily + * | | |After switching back, fill the stored feedback value to CRYPTO_HMAC_FDBCKx in the same operation, and then continue the operation with the original setting. + * @var CRYPTO_T::HMAC_FDBCK33 + * Offset: 0x3DC SHA/HMAC Output Feedback Data 33 After SHA/HMAC Operation + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[31:0] |FDBCK |SHA/HMAC Feedback Information + * | | |The feedback value is 1728 bits in size for SHA1/2 and 2784 bits in size for SHA3. + * | | |The SHA/HMAC engine uses the data from CRYPTO_HMAC_FDBCKx as the data inputted to CRYPTO_HMAC_FDBCKx for the next block in DMA cascade mode. + * | | |The SHA/HMAC engine outputs feedback information for initial setting in the next block's operation + * | | |Software can store that feedback value temporarily + * | | |After switching back, fill the stored feedback value to CRYPTO_HMAC_FDBCKx in the same operation, and then continue the operation with the original setting. + * @var CRYPTO_T::HMAC_FDBCK34 + * Offset: 0x3E0 SHA/HMAC Output Feedback Data 34 After SHA/HMAC Operation + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[31:0] |FDBCK |SHA/HMAC Feedback Information + * | | |The feedback value is 1728 bits in size for SHA1/2 and 2784 bits in size for SHA3. + * | | |The SHA/HMAC engine uses the data from CRYPTO_HMAC_FDBCKx as the data inputted to CRYPTO_HMAC_FDBCKx for the next block in DMA cascade mode. + * | | |The SHA/HMAC engine outputs feedback information for initial setting in the next block's operation + * | | |Software can store that feedback value temporarily + * | | |After switching back, fill the stored feedback value to CRYPTO_HMAC_FDBCKx in the same operation, and then continue the operation with the original setting. + * @var CRYPTO_T::HMAC_FDBCK35 + * Offset: 0x3E4 SHA/HMAC Output Feedback Data 35 After SHA/HMAC Operation + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[31:0] |FDBCK |SHA/HMAC Feedback Information + * | | |The feedback value is 1728 bits in size for SHA1/2 and 2784 bits in size for SHA3. + * | | |The SHA/HMAC engine uses the data from CRYPTO_HMAC_FDBCKx as the data inputted to CRYPTO_HMAC_FDBCKx for the next block in DMA cascade mode. + * | | |The SHA/HMAC engine outputs feedback information for initial setting in the next block's operation + * | | |Software can store that feedback value temporarily + * | | |After switching back, fill the stored feedback value to CRYPTO_HMAC_FDBCKx in the same operation, and then continue the operation with the original setting. + * @var CRYPTO_T::HMAC_FDBCK36 + * Offset: 0x3E8 SHA/HMAC Output Feedback Data 36 After SHA/HMAC Operation + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[31:0] |FDBCK |SHA/HMAC Feedback Information + * | | |The feedback value is 1728 bits in size for SHA1/2 and 2784 bits in size for SHA3. + * | | |The SHA/HMAC engine uses the data from CRYPTO_HMAC_FDBCKx as the data inputted to CRYPTO_HMAC_FDBCKx for the next block in DMA cascade mode. + * | | |The SHA/HMAC engine outputs feedback information for initial setting in the next block's operation + * | | |Software can store that feedback value temporarily + * | | |After switching back, fill the stored feedback value to CRYPTO_HMAC_FDBCKx in the same operation, and then continue the operation with the original setting. + * @var CRYPTO_T::HMAC_FDBCK37 + * Offset: 0x3EC SHA/HMAC Output Feedback Data 37 After SHA/HMAC Operation + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[31:0] |FDBCK |SHA/HMAC Feedback Information + * | | |The feedback value is 1728 bits in size for SHA1/2 and 2784 bits in size for SHA3. + * | | |The SHA/HMAC engine uses the data from CRYPTO_HMAC_FDBCKx as the data inputted to CRYPTO_HMAC_FDBCKx for the next block in DMA cascade mode. + * | | |The SHA/HMAC engine outputs feedback information for initial setting in the next block's operation + * | | |Software can store that feedback value temporarily + * | | |After switching back, fill the stored feedback value to CRYPTO_HMAC_FDBCKx in the same operation, and then continue the operation with the original setting. + * @var CRYPTO_T::HMAC_FDBCK38 + * Offset: 0x3F0 SHA/HMAC Output Feedback Data 38 After SHA/HMAC Operation + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[31:0] |FDBCK |SHA/HMAC Feedback Information + * | | |The feedback value is 1728 bits in size for SHA1/2 and 2784 bits in size for SHA3. + * | | |The SHA/HMAC engine uses the data from CRYPTO_HMAC_FDBCKx as the data inputted to CRYPTO_HMAC_FDBCKx for the next block in DMA cascade mode. + * | | |The SHA/HMAC engine outputs feedback information for initial setting in the next block's operation + * | | |Software can store that feedback value temporarily + * | | |After switching back, fill the stored feedback value to CRYPTO_HMAC_FDBCKx in the same operation, and then continue the operation with the original setting. + * @var CRYPTO_T::HMAC_FDBCK39 + * Offset: 0x3F4 SHA/HMAC Output Feedback Data 39 After SHA/HMAC Operation + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[31:0] |FDBCK |SHA/HMAC Feedback Information + * | | |The feedback value is 1728 bits in size for SHA1/2 and 2784 bits in size for SHA3. + * | | |The SHA/HMAC engine uses the data from CRYPTO_HMAC_FDBCKx as the data inputted to CRYPTO_HMAC_FDBCKx for the next block in DMA cascade mode. + * | | |The SHA/HMAC engine outputs feedback information for initial setting in the next block's operation + * | | |Software can store that feedback value temporarily + * | | |After switching back, fill the stored feedback value to CRYPTO_HMAC_FDBCKx in the same operation, and then continue the operation with the original setting. + * @var CRYPTO_T::HMAC_FDBCK40 + * Offset: 0x3F8 SHA/HMAC Output Feedback Data 40 After SHA/HMAC Operation + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[31:0] |FDBCK |SHA/HMAC Feedback Information + * | | |The feedback value is 1728 bits in size for SHA1/2 and 2784 bits in size for SHA3. + * | | |The SHA/HMAC engine uses the data from CRYPTO_HMAC_FDBCKx as the data inputted to CRYPTO_HMAC_FDBCKx for the next block in DMA cascade mode. + * | | |The SHA/HMAC engine outputs feedback information for initial setting in the next block's operation + * | | |Software can store that feedback value temporarily + * | | |After switching back, fill the stored feedback value to CRYPTO_HMAC_FDBCKx in the same operation, and then continue the operation with the original setting. + * @var CRYPTO_T::HMAC_FDBCK41 + * Offset: 0x3FC SHA/HMAC Output Feedback Data 41 After SHA/HMAC Operation + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[31:0] |FDBCK |SHA/HMAC Feedback Information + * | | |The feedback value is 1728 bits in size for SHA1/2 and 2784 bits in size for SHA3. + * | | |The SHA/HMAC engine uses the data from CRYPTO_HMAC_FDBCKx as the data inputted to CRYPTO_HMAC_FDBCKx for the next block in DMA cascade mode. + * | | |The SHA/HMAC engine outputs feedback information for initial setting in the next block's operation + * | | |Software can store that feedback value temporarily + * | | |After switching back, fill the stored feedback value to CRYPTO_HMAC_FDBCKx in the same operation, and then continue the operation with the original setting. + * @var CRYPTO_T::HMAC_FDBCK42 + * Offset: 0x400 SHA/HMAC Output Feedback Data 42 After SHA/HMAC Operation + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[31:0] |FDBCK |SHA/HMAC Feedback Information + * | | |The feedback value is 1728 bits in size for SHA1/2 and 2784 bits in size for SHA3. + * | | |The SHA/HMAC engine uses the data from CRYPTO_HMAC_FDBCKx as the data inputted to CRYPTO_HMAC_FDBCKx for the next block in DMA cascade mode. + * | | |The SHA/HMAC engine outputs feedback information for initial setting in the next block's operation + * | | |Software can store that feedback value temporarily + * | | |After switching back, fill the stored feedback value to CRYPTO_HMAC_FDBCKx in the same operation, and then continue the operation with the original setting. + * @var CRYPTO_T::HMAC_FDBCK43 + * Offset: 0x404 SHA/HMAC Output Feedback Data 43 After SHA/HMAC Operation + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[31:0] |FDBCK |SHA/HMAC Feedback Information + * | | |The feedback value is 1728 bits in size for SHA1/2 and 2784 bits in size for SHA3. + * | | |The SHA/HMAC engine uses the data from CRYPTO_HMAC_FDBCKx as the data inputted to CRYPTO_HMAC_FDBCKx for the next block in DMA cascade mode. + * | | |The SHA/HMAC engine outputs feedback information for initial setting in the next block's operation + * | | |Software can store that feedback value temporarily + * | | |After switching back, fill the stored feedback value to CRYPTO_HMAC_FDBCKx in the same operation, and then continue the operation with the original setting. + * @var CRYPTO_T::HMAC_FDBCK44 + * Offset: 0x408 SHA/HMAC Output Feedback Data 44 After SHA/HMAC Operation + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[31:0] |FDBCK |SHA/HMAC Feedback Information + * | | |The feedback value is 1728 bits in size for SHA1/2 and 2784 bits in size for SHA3. + * | | |The SHA/HMAC engine uses the data from CRYPTO_HMAC_FDBCKx as the data inputted to CRYPTO_HMAC_FDBCKx for the next block in DMA cascade mode. + * | | |The SHA/HMAC engine outputs feedback information for initial setting in the next block's operation + * | | |Software can store that feedback value temporarily + * | | |After switching back, fill the stored feedback value to CRYPTO_HMAC_FDBCKx in the same operation, and then continue the operation with the original setting. + * @var CRYPTO_T::HMAC_FDBCK45 + * Offset: 0x40C SHA/HMAC Output Feedback Data 45 After SHA/HMAC Operation + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[31:0] |FDBCK |SHA/HMAC Feedback Information + * | | |The feedback value is 1728 bits in size for SHA1/2 and 2784 bits in size for SHA3. + * | | |The SHA/HMAC engine uses the data from CRYPTO_HMAC_FDBCKx as the data inputted to CRYPTO_HMAC_FDBCKx for the next block in DMA cascade mode. + * | | |The SHA/HMAC engine outputs feedback information for initial setting in the next block's operation + * | | |Software can store that feedback value temporarily + * | | |After switching back, fill the stored feedback value to CRYPTO_HMAC_FDBCKx in the same operation, and then continue the operation with the original setting. + * @var CRYPTO_T::HMAC_FDBCK46 + * Offset: 0x410 SHA/HMAC Output Feedback Data 46 After SHA/HMAC Operation + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[31:0] |FDBCK |SHA/HMAC Feedback Information + * | | |The feedback value is 1728 bits in size for SHA1/2 and 2784 bits in size for SHA3. + * | | |The SHA/HMAC engine uses the data from CRYPTO_HMAC_FDBCKx as the data inputted to CRYPTO_HMAC_FDBCKx for the next block in DMA cascade mode. + * | | |The SHA/HMAC engine outputs feedback information for initial setting in the next block's operation + * | | |Software can store that feedback value temporarily + * | | |After switching back, fill the stored feedback value to CRYPTO_HMAC_FDBCKx in the same operation, and then continue the operation with the original setting. + * @var CRYPTO_T::HMAC_FDBCK47 + * Offset: 0x414 SHA/HMAC Output Feedback Data 47 After SHA/HMAC Operation + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[31:0] |FDBCK |SHA/HMAC Feedback Information + * | | |The feedback value is 1728 bits in size for SHA1/2 and 2784 bits in size for SHA3. + * | | |The SHA/HMAC engine uses the data from CRYPTO_HMAC_FDBCKx as the data inputted to CRYPTO_HMAC_FDBCKx for the next block in DMA cascade mode. + * | | |The SHA/HMAC engine outputs feedback information for initial setting in the next block's operation + * | | |Software can store that feedback value temporarily + * | | |After switching back, fill the stored feedback value to CRYPTO_HMAC_FDBCKx in the same operation, and then continue the operation with the original setting. + * @var CRYPTO_T::HMAC_FDBCK48 + * Offset: 0x418 SHA/HMAC Output Feedback Data 48 After SHA/HMAC Operation + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[31:0] |FDBCK |SHA/HMAC Feedback Information + * | | |The feedback value is 1728 bits in size for SHA1/2 and 2784 bits in size for SHA3. + * | | |The SHA/HMAC engine uses the data from CRYPTO_HMAC_FDBCKx as the data inputted to CRYPTO_HMAC_FDBCKx for the next block in DMA cascade mode. + * | | |The SHA/HMAC engine outputs feedback information for initial setting in the next block's operation + * | | |Software can store that feedback value temporarily + * | | |After switching back, fill the stored feedback value to CRYPTO_HMAC_FDBCKx in the same operation, and then continue the operation with the original setting. + * @var CRYPTO_T::HMAC_FDBCK49 + * Offset: 0x41C SHA/HMAC Output Feedback Data 49 After SHA/HMAC Operation + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[31:0] |FDBCK |SHA/HMAC Feedback Information + * | | |The feedback value is 1728 bits in size for SHA1/2 and 2784 bits in size for SHA3. + * | | |The SHA/HMAC engine uses the data from CRYPTO_HMAC_FDBCKx as the data inputted to CRYPTO_HMAC_FDBCKx for the next block in DMA cascade mode. + * | | |The SHA/HMAC engine outputs feedback information for initial setting in the next block's operation + * | | |Software can store that feedback value temporarily + * | | |After switching back, fill the stored feedback value to CRYPTO_HMAC_FDBCKx in the same operation, and then continue the operation with the original setting. + * @var CRYPTO_T::HMAC_FDBCK50 + * Offset: 0x420 SHA/HMAC Output Feedback Data 50 After SHA/HMAC Operation + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[31:0] |FDBCK |SHA/HMAC Feedback Information + * | | |The feedback value is 1728 bits in size for SHA1/2 and 2784 bits in size for SHA3. + * | | |The SHA/HMAC engine uses the data from CRYPTO_HMAC_FDBCKx as the data inputted to CRYPTO_HMAC_FDBCKx for the next block in DMA cascade mode. + * | | |The SHA/HMAC engine outputs feedback information for initial setting in the next block's operation + * | | |Software can store that feedback value temporarily + * | | |After switching back, fill the stored feedback value to CRYPTO_HMAC_FDBCKx in the same operation, and then continue the operation with the original setting. + * @var CRYPTO_T::HMAC_FDBCK51 + * Offset: 0x424 SHA/HMAC Output Feedback Data 51 After SHA/HMAC Operation + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[31:0] |FDBCK |SHA/HMAC Feedback Information + * | | |The feedback value is 1728 bits in size for SHA1/2 and 2784 bits in size for SHA3. + * | | |The SHA/HMAC engine uses the data from CRYPTO_HMAC_FDBCKx as the data inputted to CRYPTO_HMAC_FDBCKx for the next block in DMA cascade mode. + * | | |The SHA/HMAC engine outputs feedback information for initial setting in the next block's operation + * | | |Software can store that feedback value temporarily + * | | |After switching back, fill the stored feedback value to CRYPTO_HMAC_FDBCKx in the same operation, and then continue the operation with the original setting. + * @var CRYPTO_T::HMAC_FDBCK52 + * Offset: 0x428 SHA/HMAC Output Feedback Data 52 After SHA/HMAC Operation + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[31:0] |FDBCK |SHA/HMAC Feedback Information + * | | |The feedback value is 1728 bits in size for SHA1/2 and 2784 bits in size for SHA3. + * | | |The SHA/HMAC engine uses the data from CRYPTO_HMAC_FDBCKx as the data inputted to CRYPTO_HMAC_FDBCKx for the next block in DMA cascade mode. + * | | |The SHA/HMAC engine outputs feedback information for initial setting in the next block's operation + * | | |Software can store that feedback value temporarily + * | | |After switching back, fill the stored feedback value to CRYPTO_HMAC_FDBCKx in the same operation, and then continue the operation with the original setting. + * @var CRYPTO_T::HMAC_FDBCK53 + * Offset: 0x42C SHA/HMAC Output Feedback Data 53 After SHA/HMAC Operation + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[31:0] |FDBCK |SHA/HMAC Feedback Information + * | | |The feedback value is 1728 bits in size for SHA1/2 and 2784 bits in size for SHA3. + * | | |The SHA/HMAC engine uses the data from CRYPTO_HMAC_FDBCKx as the data inputted to CRYPTO_HMAC_FDBCKx for the next block in DMA cascade mode. + * | | |The SHA/HMAC engine outputs feedback information for initial setting in the next block's operation + * | | |Software can store that feedback value temporarily + * | | |After switching back, fill the stored feedback value to CRYPTO_HMAC_FDBCKx in the same operation, and then continue the operation with the original setting. + * @var CRYPTO_T::HMAC_FDBCK54 + * Offset: 0x430 SHA/HMAC Output Feedback Data 54 After SHA/HMAC Operation + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[31:0] |FDBCK |SHA/HMAC Feedback Information + * | | |The feedback value is 1728 bits in size for SHA1/2 and 2784 bits in size for SHA3. + * | | |The SHA/HMAC engine uses the data from CRYPTO_HMAC_FDBCKx as the data inputted to CRYPTO_HMAC_FDBCKx for the next block in DMA cascade mode. + * | | |The SHA/HMAC engine outputs feedback information for initial setting in the next block's operation + * | | |Software can store that feedback value temporarily + * | | |After switching back, fill the stored feedback value to CRYPTO_HMAC_FDBCKx in the same operation, and then continue the operation with the original setting. + * @var CRYPTO_T::HMAC_FDBCK55 + * Offset: 0x434 SHA/HMAC Output Feedback Data 55 After SHA/HMAC Operation + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[31:0] |FDBCK |SHA/HMAC Feedback Information + * | | |The feedback value is 1728 bits in size for SHA1/2 and 2784 bits in size for SHA3. + * | | |The SHA/HMAC engine uses the data from CRYPTO_HMAC_FDBCKx as the data inputted to CRYPTO_HMAC_FDBCKx for the next block in DMA cascade mode. + * | | |The SHA/HMAC engine outputs feedback information for initial setting in the next block's operation + * | | |Software can store that feedback value temporarily + * | | |After switching back, fill the stored feedback value to CRYPTO_HMAC_FDBCKx in the same operation, and then continue the operation with the original setting. + * @var CRYPTO_T::HMAC_FDBCK56 + * Offset: 0x438 SHA/HMAC Output Feedback Data 56 After SHA/HMAC Operation + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[31:0] |FDBCK |SHA/HMAC Feedback Information + * | | |The feedback value is 1728 bits in size for SHA1/2 and 2784 bits in size for SHA3. + * | | |The SHA/HMAC engine uses the data from CRYPTO_HMAC_FDBCKx as the data inputted to CRYPTO_HMAC_FDBCKx for the next block in DMA cascade mode. + * | | |The SHA/HMAC engine outputs feedback information for initial setting in the next block's operation + * | | |Software can store that feedback value temporarily + * | | |After switching back, fill the stored feedback value to CRYPTO_HMAC_FDBCKx in the same operation, and then continue the operation with the original setting. + * @var CRYPTO_T::HMAC_FDBCK57 + * Offset: 0x43C SHA/HMAC Output Feedback Data 57 After SHA/HMAC Operation + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[31:0] |FDBCK |SHA/HMAC Feedback Information + * | | |The feedback value is 1728 bits in size for SHA1/2 and 2784 bits in size for SHA3. + * | | |The SHA/HMAC engine uses the data from CRYPTO_HMAC_FDBCKx as the data inputted to CRYPTO_HMAC_FDBCKx for the next block in DMA cascade mode. + * | | |The SHA/HMAC engine outputs feedback information for initial setting in the next block's operation + * | | |Software can store that feedback value temporarily + * | | |After switching back, fill the stored feedback value to CRYPTO_HMAC_FDBCKx in the same operation, and then continue the operation with the original setting. + * @var CRYPTO_T::HMAC_FDBCK58 + * Offset: 0x440 SHA/HMAC Output Feedback Data 58 After SHA/HMAC Operation + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[31:0] |FDBCK |SHA/HMAC Feedback Information + * | | |The feedback value is 1728 bits in size for SHA1/2 and 2784 bits in size for SHA3. + * | | |The SHA/HMAC engine uses the data from CRYPTO_HMAC_FDBCKx as the data inputted to CRYPTO_HMAC_FDBCKx for the next block in DMA cascade mode. + * | | |The SHA/HMAC engine outputs feedback information for initial setting in the next block's operation + * | | |Software can store that feedback value temporarily + * | | |After switching back, fill the stored feedback value to CRYPTO_HMAC_FDBCKx in the same operation, and then continue the operation with the original setting. + * @var CRYPTO_T::HMAC_FDBCK59 + * Offset: 0x444 SHA/HMAC Output Feedback Data 59 After SHA/HMAC Operation + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[31:0] |FDBCK |SHA/HMAC Feedback Information + * | | |The feedback value is 1728 bits in size for SHA1/2 and 2784 bits in size for SHA3. + * | | |The SHA/HMAC engine uses the data from CRYPTO_HMAC_FDBCKx as the data inputted to CRYPTO_HMAC_FDBCKx for the next block in DMA cascade mode. + * | | |The SHA/HMAC engine outputs feedback information for initial setting in the next block's operation + * | | |Software can store that feedback value temporarily + * | | |After switching back, fill the stored feedback value to CRYPTO_HMAC_FDBCKx in the same operation, and then continue the operation with the original setting. + * @var CRYPTO_T::HMAC_FDBCK60 + * Offset: 0x448 SHA/HMAC Output Feedback Data 60 After SHA/HMAC Operation + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[31:0] |FDBCK |SHA/HMAC Feedback Information + * | | |The feedback value is 1728 bits in size for SHA1/2 and 2784 bits in size for SHA3. + * | | |The SHA/HMAC engine uses the data from CRYPTO_HMAC_FDBCKx as the data inputted to CRYPTO_HMAC_FDBCKx for the next block in DMA cascade mode. + * | | |The SHA/HMAC engine outputs feedback information for initial setting in the next block's operation + * | | |Software can store that feedback value temporarily + * | | |After switching back, fill the stored feedback value to CRYPTO_HMAC_FDBCKx in the same operation, and then continue the operation with the original setting. + * @var CRYPTO_T::HMAC_FDBCK61 + * Offset: 0x44C SHA/HMAC Output Feedback Data 61 After SHA/HMAC Operation + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[31:0] |FDBCK |SHA/HMAC Feedback Information + * | | |The feedback value is 1728 bits in size for SHA1/2 and 2784 bits in size for SHA3. + * | | |The SHA/HMAC engine uses the data from CRYPTO_HMAC_FDBCKx as the data inputted to CRYPTO_HMAC_FDBCKx for the next block in DMA cascade mode. + * | | |The SHA/HMAC engine outputs feedback information for initial setting in the next block's operation + * | | |Software can store that feedback value temporarily + * | | |After switching back, fill the stored feedback value to CRYPTO_HMAC_FDBCKx in the same operation, and then continue the operation with the original setting. + * @var CRYPTO_T::HMAC_FDBCK62 + * Offset: 0x450 SHA/HMAC Output Feedback Data 62 After SHA/HMAC Operation + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[31:0] |FDBCK |SHA/HMAC Feedback Information + * | | |The feedback value is 1728 bits in size for SHA1/2 and 2784 bits in size for SHA3. + * | | |The SHA/HMAC engine uses the data from CRYPTO_HMAC_FDBCKx as the data inputted to CRYPTO_HMAC_FDBCKx for the next block in DMA cascade mode. + * | | |The SHA/HMAC engine outputs feedback information for initial setting in the next block's operation + * | | |Software can store that feedback value temporarily + * | | |After switching back, fill the stored feedback value to CRYPTO_HMAC_FDBCKx in the same operation, and then continue the operation with the original setting. + * @var CRYPTO_T::HMAC_FDBCK63 + * Offset: 0x454 SHA/HMAC Output Feedback Data 63 After SHA/HMAC Operation + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[31:0] |FDBCK |SHA/HMAC Feedback Information + * | | |The feedback value is 1728 bits in size for SHA1/2 and 2784 bits in size for SHA3. + * | | |The SHA/HMAC engine uses the data from CRYPTO_HMAC_FDBCKx as the data inputted to CRYPTO_HMAC_FDBCKx for the next block in DMA cascade mode. + * | | |The SHA/HMAC engine outputs feedback information for initial setting in the next block's operation + * | | |Software can store that feedback value temporarily + * | | |After switching back, fill the stored feedback value to CRYPTO_HMAC_FDBCKx in the same operation, and then continue the operation with the original setting. + * @var CRYPTO_T::HMAC_FDBCK64 + * Offset: 0x458 SHA/HMAC Output Feedback Data 64 After SHA/HMAC Operation + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[31:0] |FDBCK |SHA/HMAC Feedback Information + * | | |The feedback value is 1728 bits in size for SHA1/2 and 2784 bits in size for SHA3. + * | | |The SHA/HMAC engine uses the data from CRYPTO_HMAC_FDBCKx as the data inputted to CRYPTO_HMAC_FDBCKx for the next block in DMA cascade mode. + * | | |The SHA/HMAC engine outputs feedback information for initial setting in the next block's operation + * | | |Software can store that feedback value temporarily + * | | |After switching back, fill the stored feedback value to CRYPTO_HMAC_FDBCKx in the same operation, and then continue the operation with the original setting. + * @var CRYPTO_T::HMAC_FDBCK65 + * Offset: 0x45C SHA/HMAC Output Feedback Data 65 After SHA/HMAC Operation + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[31:0] |FDBCK |SHA/HMAC Feedback Information + * | | |The feedback value is 1728 bits in size for SHA1/2 and 2784 bits in size for SHA3. + * | | |The SHA/HMAC engine uses the data from CRYPTO_HMAC_FDBCKx as the data inputted to CRYPTO_HMAC_FDBCKx for the next block in DMA cascade mode. + * | | |The SHA/HMAC engine outputs feedback information for initial setting in the next block's operation + * | | |Software can store that feedback value temporarily + * | | |After switching back, fill the stored feedback value to CRYPTO_HMAC_FDBCKx in the same operation, and then continue the operation with the original setting. + * @var CRYPTO_T::HMAC_FDBCK66 + * Offset: 0x460 SHA/HMAC Output Feedback Data 66 After SHA/HMAC Operation + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[31:0] |FDBCK |SHA/HMAC Feedback Information + * | | |The feedback value is 1728 bits in size for SHA1/2 and 2784 bits in size for SHA3. + * | | |The SHA/HMAC engine uses the data from CRYPTO_HMAC_FDBCKx as the data inputted to CRYPTO_HMAC_FDBCKx for the next block in DMA cascade mode. + * | | |The SHA/HMAC engine outputs feedback information for initial setting in the next block's operation + * | | |Software can store that feedback value temporarily + * | | |After switching back, fill the stored feedback value to CRYPTO_HMAC_FDBCKx in the same operation, and then continue the operation with the original setting. + * @var CRYPTO_T::HMAC_FDBCK67 + * Offset: 0x464 SHA/HMAC Output Feedback Data 67 After SHA/HMAC Operation + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[31:0] |FDBCK |SHA/HMAC Feedback Information + * | | |The feedback value is 1728 bits in size for SHA1/2 and 2784 bits in size for SHA3. + * | | |The SHA/HMAC engine uses the data from CRYPTO_HMAC_FDBCKx as the data inputted to CRYPTO_HMAC_FDBCKx for the next block in DMA cascade mode. + * | | |The SHA/HMAC engine outputs feedback information for initial setting in the next block's operation + * | | |Software can store that feedback value temporarily + * | | |After switching back, fill the stored feedback value to CRYPTO_HMAC_FDBCKx in the same operation, and then continue the operation with the original setting. + * @var CRYPTO_T::HMAC_FDBCK68 + * Offset: 0x468 SHA/HMAC Output Feedback Data 68 After SHA/HMAC Operation + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[31:0] |FDBCK |SHA/HMAC Feedback Information + * | | |The feedback value is 1728 bits in size for SHA1/2 and 2784 bits in size for SHA3. + * | | |The SHA/HMAC engine uses the data from CRYPTO_HMAC_FDBCKx as the data inputted to CRYPTO_HMAC_FDBCKx for the next block in DMA cascade mode. + * | | |The SHA/HMAC engine outputs feedback information for initial setting in the next block's operation + * | | |Software can store that feedback value temporarily + * | | |After switching back, fill the stored feedback value to CRYPTO_HMAC_FDBCKx in the same operation, and then continue the operation with the original setting. + * @var CRYPTO_T::HMAC_FDBCK69 + * Offset: 0x46C SHA/HMAC Output Feedback Data 69 After SHA/HMAC Operation + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[31:0] |FDBCK |SHA/HMAC Feedback Information + * | | |The feedback value is 1728 bits in size for SHA1/2 and 2784 bits in size for SHA3. + * | | |The SHA/HMAC engine uses the data from CRYPTO_HMAC_FDBCKx as the data inputted to CRYPTO_HMAC_FDBCKx for the next block in DMA cascade mode. + * | | |The SHA/HMAC engine outputs feedback information for initial setting in the next block's operation + * | | |Software can store that feedback value temporarily + * | | |After switching back, fill the stored feedback value to CRYPTO_HMAC_FDBCKx in the same operation, and then continue the operation with the original setting. + * @var CRYPTO_T::HMAC_FDBCK70 + * Offset: 0x470 SHA/HMAC Output Feedback Data 70 After SHA/HMAC Operation + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[31:0] |FDBCK |SHA/HMAC Feedback Information + * | | |The feedback value is 1728 bits in size for SHA1/2 and 2784 bits in size for SHA3. + * | | |The SHA/HMAC engine uses the data from CRYPTO_HMAC_FDBCKx as the data inputted to CRYPTO_HMAC_FDBCKx for the next block in DMA cascade mode. + * | | |The SHA/HMAC engine outputs feedback information for initial setting in the next block's operation + * | | |Software can store that feedback value temporarily + * | | |After switching back, fill the stored feedback value to CRYPTO_HMAC_FDBCKx in the same operation, and then continue the operation with the original setting. + * @var CRYPTO_T::HMAC_FDBCK71 + * Offset: 0x474 SHA/HMAC Output Feedback Data 71 After SHA/HMAC Operation + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[31:0] |FDBCK |SHA/HMAC Feedback Information + * | | |The feedback value is 1728 bits in size for SHA1/2 and 2784 bits in size for SHA3. + * | | |The SHA/HMAC engine uses the data from CRYPTO_HMAC_FDBCKx as the data inputted to CRYPTO_HMAC_FDBCKx for the next block in DMA cascade mode. + * | | |The SHA/HMAC engine outputs feedback information for initial setting in the next block's operation + * | | |Software can store that feedback value temporarily + * | | |After switching back, fill the stored feedback value to CRYPTO_HMAC_FDBCKx in the same operation, and then continue the operation with the original setting. + * @var CRYPTO_T::HMAC_FDBCK72 + * Offset: 0x478 SHA/HMAC Output Feedback Data 72 After SHA/HMAC Operation + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[31:0] |FDBCK |SHA/HMAC Feedback Information + * | | |The feedback value is 1728 bits in size for SHA1/2 and 2784 bits in size for SHA3. + * | | |The SHA/HMAC engine uses the data from CRYPTO_HMAC_FDBCKx as the data inputted to CRYPTO_HMAC_FDBCKx for the next block in DMA cascade mode. + * | | |The SHA/HMAC engine outputs feedback information for initial setting in the next block's operation + * | | |Software can store that feedback value temporarily + * | | |After switching back, fill the stored feedback value to CRYPTO_HMAC_FDBCKx in the same operation, and then continue the operation with the original setting. + * @var CRYPTO_T::HMAC_FDBCK73 + * Offset: 0x47C SHA/HMAC Output Feedback Data 73 After SHA/HMAC Operation + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[31:0] |FDBCK |SHA/HMAC Feedback Information + * | | |The feedback value is 1728 bits in size for SHA1/2 and 2784 bits in size for SHA3. + * | | |The SHA/HMAC engine uses the data from CRYPTO_HMAC_FDBCKx as the data inputted to CRYPTO_HMAC_FDBCKx for the next block in DMA cascade mode. + * | | |The SHA/HMAC engine outputs feedback information for initial setting in the next block's operation + * | | |Software can store that feedback value temporarily + * | | |After switching back, fill the stored feedback value to CRYPTO_HMAC_FDBCKx in the same operation, and then continue the operation with the original setting. + * @var CRYPTO_T::HMAC_FDBCK74 + * Offset: 0x480 SHA/HMAC Output Feedback Data 74 After SHA/HMAC Operation + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[31:0] |FDBCK |SHA/HMAC Feedback Information + * | | |The feedback value is 1728 bits in size for SHA1/2 and 2784 bits in size for SHA3. + * | | |The SHA/HMAC engine uses the data from CRYPTO_HMAC_FDBCKx as the data inputted to CRYPTO_HMAC_FDBCKx for the next block in DMA cascade mode. + * | | |The SHA/HMAC engine outputs feedback information for initial setting in the next block's operation + * | | |Software can store that feedback value temporarily + * | | |After switching back, fill the stored feedback value to CRYPTO_HMAC_FDBCKx in the same operation, and then continue the operation with the original setting. + * @var CRYPTO_T::HMAC_FDBCK75 + * Offset: 0x484 SHA/HMAC Output Feedback Data 75 After SHA/HMAC Operation + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[31:0] |FDBCK |SHA/HMAC Feedback Information + * | | |The feedback value is 1728 bits in size for SHA1/2 and 2784 bits in size for SHA3. + * | | |The SHA/HMAC engine uses the data from CRYPTO_HMAC_FDBCKx as the data inputted to CRYPTO_HMAC_FDBCKx for the next block in DMA cascade mode. + * | | |The SHA/HMAC engine outputs feedback information for initial setting in the next block's operation + * | | |Software can store that feedback value temporarily + * | | |After switching back, fill the stored feedback value to CRYPTO_HMAC_FDBCKx in the same operation, and then continue the operation with the original setting. + * @var CRYPTO_T::HMAC_FDBCK76 + * Offset: 0x488 SHA/HMAC Output Feedback Data 76 After SHA/HMAC Operation + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[31:0] |FDBCK |SHA/HMAC Feedback Information + * | | |The feedback value is 1728 bits in size for SHA1/2 and 2784 bits in size for SHA3. + * | | |The SHA/HMAC engine uses the data from CRYPTO_HMAC_FDBCKx as the data inputted to CRYPTO_HMAC_FDBCKx for the next block in DMA cascade mode. + * | | |The SHA/HMAC engine outputs feedback information for initial setting in the next block's operation + * | | |Software can store that feedback value temporarily + * | | |After switching back, fill the stored feedback value to CRYPTO_HMAC_FDBCKx in the same operation, and then continue the operation with the original setting. + * @var CRYPTO_T::HMAC_FDBCK77 + * Offset: 0x48C SHA/HMAC Output Feedback Data 77 After SHA/HMAC Operation + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[31:0] |FDBCK |SHA/HMAC Feedback Information + * | | |The feedback value is 1728 bits in size for SHA1/2 and 2784 bits in size for SHA3. + * | | |The SHA/HMAC engine uses the data from CRYPTO_HMAC_FDBCKx as the data inputted to CRYPTO_HMAC_FDBCKx for the next block in DMA cascade mode. + * | | |The SHA/HMAC engine outputs feedback information for initial setting in the next block's operation + * | | |Software can store that feedback value temporarily + * | | |After switching back, fill the stored feedback value to CRYPTO_HMAC_FDBCKx in the same operation, and then continue the operation with the original setting. + * @var CRYPTO_T::HMAC_FDBCK78 + * Offset: 0x490 SHA/HMAC Output Feedback Data 78 After SHA/HMAC Operation + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[31:0] |FDBCK |SHA/HMAC Feedback Information + * | | |The feedback value is 1728 bits in size for SHA1/2 and 2784 bits in size for SHA3. + * | | |The SHA/HMAC engine uses the data from CRYPTO_HMAC_FDBCKx as the data inputted to CRYPTO_HMAC_FDBCKx for the next block in DMA cascade mode. + * | | |The SHA/HMAC engine outputs feedback information for initial setting in the next block's operation + * | | |Software can store that feedback value temporarily + * | | |After switching back, fill the stored feedback value to CRYPTO_HMAC_FDBCKx in the same operation, and then continue the operation with the original setting. + * @var CRYPTO_T::HMAC_FDBCK79 + * Offset: 0x494 SHA/HMAC Output Feedback Data 79 After SHA/HMAC Operation + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[31:0] |FDBCK |SHA/HMAC Feedback Information + * | | |The feedback value is 1728 bits in size for SHA1/2 and 2784 bits in size for SHA3. + * | | |The SHA/HMAC engine uses the data from CRYPTO_HMAC_FDBCKx as the data inputted to CRYPTO_HMAC_FDBCKx for the next block in DMA cascade mode. + * | | |The SHA/HMAC engine outputs feedback information for initial setting in the next block's operation + * | | |Software can store that feedback value temporarily + * | | |After switching back, fill the stored feedback value to CRYPTO_HMAC_FDBCKx in the same operation, and then continue the operation with the original setting. + * @var CRYPTO_T::HMAC_FDBCK80 + * Offset: 0x498 SHA/HMAC Output Feedback Data 80 After SHA/HMAC Operation + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[31:0] |FDBCK |SHA/HMAC Feedback Information + * | | |The feedback value is 1728 bits in size for SHA1/2 and 2784 bits in size for SHA3. + * | | |The SHA/HMAC engine uses the data from CRYPTO_HMAC_FDBCKx as the data inputted to CRYPTO_HMAC_FDBCKx for the next block in DMA cascade mode. + * | | |The SHA/HMAC engine outputs feedback information for initial setting in the next block's operation + * | | |Software can store that feedback value temporarily + * | | |After switching back, fill the stored feedback value to CRYPTO_HMAC_FDBCKx in the same operation, and then continue the operation with the original setting. + * @var CRYPTO_T::HMAC_FDBCK81 + * Offset: 0x49C SHA/HMAC Output Feedback Data 81 After SHA/HMAC Operation + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[31:0] |FDBCK |SHA/HMAC Feedback Information + * | | |The feedback value is 1728 bits in size for SHA1/2 and 2784 bits in size for SHA3. + * | | |The SHA/HMAC engine uses the data from CRYPTO_HMAC_FDBCKx as the data inputted to CRYPTO_HMAC_FDBCKx for the next block in DMA cascade mode. + * | | |The SHA/HMAC engine outputs feedback information for initial setting in the next block's operation + * | | |Software can store that feedback value temporarily + * | | |After switching back, fill the stored feedback value to CRYPTO_HMAC_FDBCKx in the same operation, and then continue the operation with the original setting. + * @var CRYPTO_T::HMAC_FDBCK82 + * Offset: 0x4A0 SHA/HMAC Output Feedback Data 82 After SHA/HMAC Operation + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[31:0] |FDBCK |SHA/HMAC Feedback Information + * | | |The feedback value is 1728 bits in size for SHA1/2 and 2784 bits in size for SHA3. + * | | |The SHA/HMAC engine uses the data from CRYPTO_HMAC_FDBCKx as the data inputted to CRYPTO_HMAC_FDBCKx for the next block in DMA cascade mode. + * | | |The SHA/HMAC engine outputs feedback information for initial setting in the next block's operation + * | | |Software can store that feedback value temporarily + * | | |After switching back, fill the stored feedback value to CRYPTO_HMAC_FDBCKx in the same operation, and then continue the operation with the original setting. + * @var CRYPTO_T::HMAC_FDBCK83 + * Offset: 0x4A4 SHA/HMAC Output Feedback Data 83 After SHA/HMAC Operation + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[31:0] |FDBCK |SHA/HMAC Feedback Information + * | | |The feedback value is 1728 bits in size for SHA1/2 and 2784 bits in size for SHA3. + * | | |The SHA/HMAC engine uses the data from CRYPTO_HMAC_FDBCKx as the data inputted to CRYPTO_HMAC_FDBCKx for the next block in DMA cascade mode. + * | | |The SHA/HMAC engine outputs feedback information for initial setting in the next block's operation + * | | |Software can store that feedback value temporarily + * | | |After switching back, fill the stored feedback value to CRYPTO_HMAC_FDBCKx in the same operation, and then continue the operation with the original setting. + * @var CRYPTO_T::HMAC_FDBCK84 + * Offset: 0x4A8 SHA/HMAC Output Feedback Data 84 After SHA/HMAC Operation + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[31:0] |FDBCK |SHA/HMAC Feedback Information + * | | |The feedback value is 1728 bits in size for SHA1/2 and 2784 bits in size for SHA3. + * | | |The SHA/HMAC engine uses the data from CRYPTO_HMAC_FDBCKx as the data inputted to CRYPTO_HMAC_FDBCKx for the next block in DMA cascade mode. + * | | |The SHA/HMAC engine outputs feedback information for initial setting in the next block's operation + * | | |Software can store that feedback value temporarily + * | | |After switching back, fill the stored feedback value to CRYPTO_HMAC_FDBCKx in the same operation, and then continue the operation with the original setting. + * @var CRYPTO_T::HMAC_FDBCK85 + * Offset: 0x4AC SHA/HMAC Output Feedback Data 85 After SHA/HMAC Operation + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[31:0] |FDBCK |SHA/HMAC Feedback Information + * | | |The feedback value is 1728 bits in size for SHA1/2 and 2784 bits in size for SHA3. + * | | |The SHA/HMAC engine uses the data from CRYPTO_HMAC_FDBCKx as the data inputted to CRYPTO_HMAC_FDBCKx for the next block in DMA cascade mode. + * | | |The SHA/HMAC engine outputs feedback information for initial setting in the next block's operation + * | | |Software can store that feedback value temporarily + * | | |After switching back, fill the stored feedback value to CRYPTO_HMAC_FDBCKx in the same operation, and then continue the operation with the original setting. + * @var CRYPTO_T::HMAC_FDBCK86 + * Offset: 0x4B0 SHA/HMAC Output Feedback Data 86 After SHA/HMAC Operation + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[31:0] |FDBCK |SHA/HMAC Feedback Information + * | | |The feedback value is 1728 bits in size for SHA1/2 and 2784 bits in size for SHA3. + * | | |The SHA/HMAC engine uses the data from CRYPTO_HMAC_FDBCKx as the data inputted to CRYPTO_HMAC_FDBCKx for the next block in DMA cascade mode. + * | | |The SHA/HMAC engine outputs feedback information for initial setting in the next block's operation + * | | |Software can store that feedback value temporarily + * | | |After switching back, fill the stored feedback value to CRYPTO_HMAC_FDBCKx in the same operation, and then continue the operation with the original setting. + * @var CRYPTO_T::HMAC_FDBCK87 + * Offset: 0x4B4 SHA/HMAC Output Feedback Data 87 After SHA/HMAC Operation + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[31:0] |FDBCK |SHA/HMAC Feedback Information + * | | |The feedback value is 1728 bits in size for SHA1/2 and 2784 bits in size for SHA3. + * | | |The SHA/HMAC engine uses the data from CRYPTO_HMAC_FDBCKx as the data inputted to CRYPTO_HMAC_FDBCKx for the next block in DMA cascade mode. + * | | |The SHA/HMAC engine outputs feedback information for initial setting in the next block's operation + * | | |Software can store that feedback value temporarily + * | | |After switching back, fill the stored feedback value to CRYPTO_HMAC_FDBCKx in the same operation, and then continue the operation with the original setting. + * @var CRYPTO_T::HMAC_SHA512T + * Offset: 0x4F8 SHA/HMAC SHA512T Control Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[0] |SHA512TEN |SHA512T Engine Enable Bit + * | | |0 = Execute other function. + * | | |1 = Execute SHA512T function if SHA3EN=0, MD5EN=0 and SM3EN=0. + * | | |Note: When SHA512TEN=1, SHA/HMAC only execute SHA2-512. + * |[16:8] |TLEN |SHA512T output digest length + * | | |The TLEN is equal to value t of SHA512T. It also means the output digest length of SHA512T. + * | | |Note: TLEN < 512, and TLEN is not 384 + * @var CRYPTO_T::HMAC_FBADDR + * Offset: 0x4FC SHA/HMAC DMA Feedback Address Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[31:0] |FBADDR |SHA/HMAC DMA Feedback Address + * | | |In DMA cascade mode, software can update DMA feedback address register for automatically reading and writing feedback values via DMA + * | | |The FBADDR keeps the feedback address of the feedback data for the next cascade operation + * | | |Based on the feedback address, the SHA/HMAC accelerator can read the feedback data of the last cascade operation from SRAM memory space and write the feedback data of the current cascade operation to SRAM memory space + * | | |The start of feedback address should be located at word boundary + * | | |In other words, bit 1 and 0 of FBADDR are ignored. + * | | |FBADDR can be read and written. + * | | |In DMA mode, software can update the next CRYPTO_HMAC_FBADDR before triggering START. + * @var CRYPTO_T::HMAC_SHAKEDGST0 + * Offset: 0x500 SHA/HMAC SHAKE Digest Message 0 + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[31:0] |DGST |SHA/HMAC SHAKE Digest Message Register + * | | |For SHAKE-128, the digest is stored in CRYPTO_HMAC_SHAKEDGST0 0 ~ CRYPTO_HMAC_ SHAKEDGST0 41. + * | | |For SHAKE-256, the digest is stored in CRYPTO_HMAC_SHAKEDGST0 0 ~ CRYPTO_HMAC_ SHAKEDGST0 33. + * @var CRYPTO_T::HMAC_SHAKEDGST1 + * Offset: 0x504 SHA/HMAC SHAKE Digest Message 1 + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[31:0] |DGST |SHA/HMAC SHAKE Digest Message Register + * | | |For SHAKE-128, the digest is stored in CRYPTO_HMAC_SHAKEDGST0 0 ~ CRYPTO_HMAC_ SHAKEDGST0 41. + * | | |For SHAKE-256, the digest is stored in CRYPTO_HMAC_SHAKEDGST0 0 ~ CRYPTO_HMAC_ SHAKEDGST0 33. + * @var CRYPTO_T::HMAC_SHAKEDGST2 + * Offset: 0x508 SHA/HMAC SHAKE Digest Message 2 + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[31:0] |DGST |SHA/HMAC SHAKE Digest Message Register + * | | |For SHAKE-128, the digest is stored in CRYPTO_HMAC_SHAKEDGST0 0 ~ CRYPTO_HMAC_ SHAKEDGST0 41. + * | | |For SHAKE-256, the digest is stored in CRYPTO_HMAC_SHAKEDGST0 0 ~ CRYPTO_HMAC_ SHAKEDGST0 33. + * @var CRYPTO_T::HMAC_SHAKEDGST3 + * Offset: 0x50C SHA/HMAC SHAKE Digest Message 3 + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[31:0] |DGST |SHA/HMAC SHAKE Digest Message Register + * | | |For SHAKE-128, the digest is stored in CRYPTO_HMAC_SHAKEDGST0 0 ~ CRYPTO_HMAC_ SHAKEDGST0 41. + * | | |For SHAKE-256, the digest is stored in CRYPTO_HMAC_SHAKEDGST0 0 ~ CRYPTO_HMAC_ SHAKEDGST0 33. + * @var CRYPTO_T::HMAC_SHAKEDGST4 + * Offset: 0x510 SHA/HMAC SHAKE Digest Message 4 + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[31:0] |DGST |SHA/HMAC SHAKE Digest Message Register + * | | |For SHAKE-128, the digest is stored in CRYPTO_HMAC_SHAKEDGST0 0 ~ CRYPTO_HMAC_ SHAKEDGST0 41. + * | | |For SHAKE-256, the digest is stored in CRYPTO_HMAC_SHAKEDGST0 0 ~ CRYPTO_HMAC_ SHAKEDGST0 33. + * @var CRYPTO_T::HMAC_SHAKEDGST5 + * Offset: 0x514 SHA/HMAC SHAKE Digest Message 5 + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[31:0] |DGST |SHA/HMAC SHAKE Digest Message Register + * | | |For SHAKE-128, the digest is stored in CRYPTO_HMAC_SHAKEDGST0 0 ~ CRYPTO_HMAC_ SHAKEDGST0 41. + * | | |For SHAKE-256, the digest is stored in CRYPTO_HMAC_SHAKEDGST0 0 ~ CRYPTO_HMAC_ SHAKEDGST0 33. + * @var CRYPTO_T::HMAC_SHAKEDGST6 + * Offset: 0x518 SHA/HMAC SHAKE Digest Message 6 + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[31:0] |DGST |SHA/HMAC SHAKE Digest Message Register + * | | |For SHAKE-128, the digest is stored in CRYPTO_HMAC_SHAKEDGST0 0 ~ CRYPTO_HMAC_ SHAKEDGST0 41. + * | | |For SHAKE-256, the digest is stored in CRYPTO_HMAC_SHAKEDGST0 0 ~ CRYPTO_HMAC_ SHAKEDGST0 33. + * @var CRYPTO_T::HMAC_SHAKEDGST7 + * Offset: 0x51C SHA/HMAC SHAKE Digest Message 7 + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[31:0] |DGST |SHA/HMAC SHAKE Digest Message Register + * | | |For SHAKE-128, the digest is stored in CRYPTO_HMAC_SHAKEDGST0 0 ~ CRYPTO_HMAC_ SHAKEDGST0 41. + * | | |For SHAKE-256, the digest is stored in CRYPTO_HMAC_SHAKEDGST0 0 ~ CRYPTO_HMAC_ SHAKEDGST0 33. + * @var CRYPTO_T::HMAC_SHAKEDGST8 + * Offset: 0x520 SHA/HMAC SHAKE Digest Message 8 + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[31:0] |DGST |SHA/HMAC SHAKE Digest Message Register + * | | |For SHAKE-128, the digest is stored in CRYPTO_HMAC_SHAKEDGST0 0 ~ CRYPTO_HMAC_ SHAKEDGST0 41. + * | | |For SHAKE-256, the digest is stored in CRYPTO_HMAC_SHAKEDGST0 0 ~ CRYPTO_HMAC_ SHAKEDGST0 33. + * @var CRYPTO_T::HMAC_SHAKEDGST9 + * Offset: 0x524 SHA/HMAC SHAKE Digest Message 9 + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[31:0] |DGST |SHA/HMAC SHAKE Digest Message Register + * | | |For SHAKE-128, the digest is stored in CRYPTO_HMAC_SHAKEDGST0 0 ~ CRYPTO_HMAC_ SHAKEDGST0 41. + * | | |For SHAKE-256, the digest is stored in CRYPTO_HMAC_SHAKEDGST0 0 ~ CRYPTO_HMAC_ SHAKEDGST0 33. + * @var CRYPTO_T::HMAC_SHAKEDGST10 + * Offset: 0x528 SHA/HMAC SHAKE Digest Message 10 + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[31:0] |DGST |SHA/HMAC SHAKE Digest Message Register + * | | |For SHAKE-128, the digest is stored in CRYPTO_HMAC_SHAKEDGST0 0 ~ CRYPTO_HMAC_ SHAKEDGST0 41. + * | | |For SHAKE-256, the digest is stored in CRYPTO_HMAC_SHAKEDGST0 0 ~ CRYPTO_HMAC_ SHAKEDGST0 33. + * @var CRYPTO_T::HMAC_SHAKEDGST11 + * Offset: 0x52C SHA/HMAC SHAKE Digest Message 11 + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[31:0] |DGST |SHA/HMAC SHAKE Digest Message Register + * | | |For SHAKE-128, the digest is stored in CRYPTO_HMAC_SHAKEDGST0 0 ~ CRYPTO_HMAC_ SHAKEDGST0 41. + * | | |For SHAKE-256, the digest is stored in CRYPTO_HMAC_SHAKEDGST0 0 ~ CRYPTO_HMAC_ SHAKEDGST0 33. + * @var CRYPTO_T::HMAC_SHAKEDGST12 + * Offset: 0x530 SHA/HMAC SHAKE Digest Message 12 + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[31:0] |DGST |SHA/HMAC SHAKE Digest Message Register + * | | |For SHAKE-128, the digest is stored in CRYPTO_HMAC_SHAKEDGST0 0 ~ CRYPTO_HMAC_ SHAKEDGST0 41. + * | | |For SHAKE-256, the digest is stored in CRYPTO_HMAC_SHAKEDGST0 0 ~ CRYPTO_HMAC_ SHAKEDGST0 33. + * @var CRYPTO_T::HMAC_SHAKEDGST13 + * Offset: 0x534 SHA/HMAC SHAKE Digest Message 13 + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[31:0] |DGST |SHA/HMAC SHAKE Digest Message Register + * | | |For SHAKE-128, the digest is stored in CRYPTO_HMAC_SHAKEDGST0 0 ~ CRYPTO_HMAC_ SHAKEDGST0 41. + * | | |For SHAKE-256, the digest is stored in CRYPTO_HMAC_SHAKEDGST0 0 ~ CRYPTO_HMAC_ SHAKEDGST0 33. + * @var CRYPTO_T::HMAC_SHAKEDGST14 + * Offset: 0x538 SHA/HMAC SHAKE Digest Message 14 + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[31:0] |DGST |SHA/HMAC SHAKE Digest Message Register + * | | |For SHAKE-128, the digest is stored in CRYPTO_HMAC_SHAKEDGST0 0 ~ CRYPTO_HMAC_ SHAKEDGST0 41. + * | | |For SHAKE-256, the digest is stored in CRYPTO_HMAC_SHAKEDGST0 0 ~ CRYPTO_HMAC_ SHAKEDGST0 33. + * @var CRYPTO_T::HMAC_SHAKEDGST15 + * Offset: 0x53C SHA/HMAC SHAKE Digest Message 15 + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[31:0] |DGST |SHA/HMAC SHAKE Digest Message Register + * | | |For SHAKE-128, the digest is stored in CRYPTO_HMAC_SHAKEDGST0 0 ~ CRYPTO_HMAC_ SHAKEDGST0 41. + * | | |For SHAKE-256, the digest is stored in CRYPTO_HMAC_SHAKEDGST0 0 ~ CRYPTO_HMAC_ SHAKEDGST0 33. + * @var CRYPTO_T::HMAC_SHAKEDGST16 + * Offset: 0x540 SHA/HMAC SHAKE Digest Message 16 + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[31:0] |DGST |SHA/HMAC SHAKE Digest Message Register + * | | |For SHAKE-128, the digest is stored in CRYPTO_HMAC_SHAKEDGST0 0 ~ CRYPTO_HMAC_ SHAKEDGST0 41. + * | | |For SHAKE-256, the digest is stored in CRYPTO_HMAC_SHAKEDGST0 0 ~ CRYPTO_HMAC_ SHAKEDGST0 33. + * @var CRYPTO_T::HMAC_SHAKEDGST17 + * Offset: 0x544 SHA/HMAC SHAKE Digest Message 17 + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[31:0] |DGST |SHA/HMAC SHAKE Digest Message Register + * | | |For SHAKE-128, the digest is stored in CRYPTO_HMAC_SHAKEDGST0 0 ~ CRYPTO_HMAC_ SHAKEDGST0 41. + * | | |For SHAKE-256, the digest is stored in CRYPTO_HMAC_SHAKEDGST0 0 ~ CRYPTO_HMAC_ SHAKEDGST0 33. + * @var CRYPTO_T::HMAC_SHAKEDGST18 + * Offset: 0x548 SHA/HMAC SHAKE Digest Message 18 + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[31:0] |DGST |SHA/HMAC SHAKE Digest Message Register + * | | |For SHAKE-128, the digest is stored in CRYPTO_HMAC_SHAKEDGST0 0 ~ CRYPTO_HMAC_ SHAKEDGST0 41. + * | | |For SHAKE-256, the digest is stored in CRYPTO_HMAC_SHAKEDGST0 0 ~ CRYPTO_HMAC_ SHAKEDGST0 33. + * @var CRYPTO_T::HMAC_SHAKEDGST19 + * Offset: 0x54C SHA/HMAC SHAKE Digest Message 19 + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[31:0] |DGST |SHA/HMAC SHAKE Digest Message Register + * | | |For SHAKE-128, the digest is stored in CRYPTO_HMAC_SHAKEDGST0 0 ~ CRYPTO_HMAC_ SHAKEDGST0 41. + * | | |For SHAKE-256, the digest is stored in CRYPTO_HMAC_SHAKEDGST0 0 ~ CRYPTO_HMAC_ SHAKEDGST0 33. + * @var CRYPTO_T::HMAC_SHAKEDGST20 + * Offset: 0x550 SHA/HMAC SHAKE Digest Message 20 + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[31:0] |DGST |SHA/HMAC SHAKE Digest Message Register + * | | |For SHAKE-128, the digest is stored in CRYPTO_HMAC_SHAKEDGST0 0 ~ CRYPTO_HMAC_ SHAKEDGST0 41. + * | | |For SHAKE-256, the digest is stored in CRYPTO_HMAC_SHAKEDGST0 0 ~ CRYPTO_HMAC_ SHAKEDGST0 33. + * @var CRYPTO_T::HMAC_SHAKEDGST21 + * Offset: 0x554 SHA/HMAC SHAKE Digest Message 21 + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[31:0] |DGST |SHA/HMAC SHAKE Digest Message Register + * | | |For SHAKE-128, the digest is stored in CRYPTO_HMAC_SHAKEDGST0 0 ~ CRYPTO_HMAC_ SHAKEDGST0 41. + * | | |For SHAKE-256, the digest is stored in CRYPTO_HMAC_SHAKEDGST0 0 ~ CRYPTO_HMAC_ SHAKEDGST0 33. + * @var CRYPTO_T::HMAC_SHAKEDGST22 + * Offset: 0x558 SHA/HMAC SHAKE Digest Message 22 + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[31:0] |DGST |SHA/HMAC SHAKE Digest Message Register + * | | |For SHAKE-128, the digest is stored in CRYPTO_HMAC_SHAKEDGST0 0 ~ CRYPTO_HMAC_ SHAKEDGST0 41. + * | | |For SHAKE-256, the digest is stored in CRYPTO_HMAC_SHAKEDGST0 0 ~ CRYPTO_HMAC_ SHAKEDGST0 33. + * @var CRYPTO_T::HMAC_SHAKEDGST23 + * Offset: 0x55C SHA/HMAC SHAKE Digest Message 23 + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[31:0] |DGST |SHA/HMAC SHAKE Digest Message Register + * | | |For SHAKE-128, the digest is stored in CRYPTO_HMAC_SHAKEDGST0 0 ~ CRYPTO_HMAC_ SHAKEDGST0 41. + * | | |For SHAKE-256, the digest is stored in CRYPTO_HMAC_SHAKEDGST0 0 ~ CRYPTO_HMAC_ SHAKEDGST0 33. + * @var CRYPTO_T::HMAC_SHAKEDGST24 + * Offset: 0x560 SHA/HMAC SHAKE Digest Message 24 + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[31:0] |DGST |SHA/HMAC SHAKE Digest Message Register + * | | |For SHAKE-128, the digest is stored in CRYPTO_HMAC_SHAKEDGST0 0 ~ CRYPTO_HMAC_ SHAKEDGST0 41. + * | | |For SHAKE-256, the digest is stored in CRYPTO_HMAC_SHAKEDGST0 0 ~ CRYPTO_HMAC_ SHAKEDGST0 33. + * @var CRYPTO_T::HMAC_SHAKEDGST25 + * Offset: 0x564 SHA/HMAC SHAKE Digest Message 25 + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[31:0] |DGST |SHA/HMAC SHAKE Digest Message Register + * | | |For SHAKE-128, the digest is stored in CRYPTO_HMAC_SHAKEDGST0 0 ~ CRYPTO_HMAC_ SHAKEDGST0 41. + * | | |For SHAKE-256, the digest is stored in CRYPTO_HMAC_SHAKEDGST0 0 ~ CRYPTO_HMAC_ SHAKEDGST0 33. + * @var CRYPTO_T::HMAC_SHAKEDGST26 + * Offset: 0x568 SHA/HMAC SHAKE Digest Message 26 + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[31:0] |DGST |SHA/HMAC SHAKE Digest Message Register + * | | |For SHAKE-128, the digest is stored in CRYPTO_HMAC_SHAKEDGST0 0 ~ CRYPTO_HMAC_ SHAKEDGST0 41. + * | | |For SHAKE-256, the digest is stored in CRYPTO_HMAC_SHAKEDGST0 0 ~ CRYPTO_HMAC_ SHAKEDGST0 33. + * @var CRYPTO_T::HMAC_SHAKEDGST27 + * Offset: 0x56C SHA/HMAC SHAKE Digest Message 27 + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[31:0] |DGST |SHA/HMAC SHAKE Digest Message Register + * | | |For SHAKE-128, the digest is stored in CRYPTO_HMAC_SHAKEDGST0 0 ~ CRYPTO_HMAC_ SHAKEDGST0 41. + * | | |For SHAKE-256, the digest is stored in CRYPTO_HMAC_SHAKEDGST0 0 ~ CRYPTO_HMAC_ SHAKEDGST0 33. + * @var CRYPTO_T::HMAC_SHAKEDGST28 + * Offset: 0x570 SHA/HMAC SHAKE Digest Message 28 + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[31:0] |DGST |SHA/HMAC SHAKE Digest Message Register + * | | |For SHAKE-128, the digest is stored in CRYPTO_HMAC_SHAKEDGST0 0 ~ CRYPTO_HMAC_ SHAKEDGST0 41. + * | | |For SHAKE-256, the digest is stored in CRYPTO_HMAC_SHAKEDGST0 0 ~ CRYPTO_HMAC_ SHAKEDGST0 33. + * @var CRYPTO_T::HMAC_SHAKEDGST29 + * Offset: 0x574 SHA/HMAC SHAKE Digest Message 29 + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[31:0] |DGST |SHA/HMAC SHAKE Digest Message Register + * | | |For SHAKE-128, the digest is stored in CRYPTO_HMAC_SHAKEDGST0 0 ~ CRYPTO_HMAC_ SHAKEDGST0 41. + * | | |For SHAKE-256, the digest is stored in CRYPTO_HMAC_SHAKEDGST0 0 ~ CRYPTO_HMAC_ SHAKEDGST0 33. + * @var CRYPTO_T::HMAC_SHAKEDGST30 + * Offset: 0x578 SHA/HMAC SHAKE Digest Message 30 + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[31:0] |DGST |SHA/HMAC SHAKE Digest Message Register + * | | |For SHAKE-128, the digest is stored in CRYPTO_HMAC_SHAKEDGST0 0 ~ CRYPTO_HMAC_ SHAKEDGST0 41. + * | | |For SHAKE-256, the digest is stored in CRYPTO_HMAC_SHAKEDGST0 0 ~ CRYPTO_HMAC_ SHAKEDGST0 33. + * @var CRYPTO_T::HMAC_SHAKEDGST31 + * Offset: 0x57C SHA/HMAC SHAKE Digest Message 31 + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[31:0] |DGST |SHA/HMAC SHAKE Digest Message Register + * | | |For SHAKE-128, the digest is stored in CRYPTO_HMAC_SHAKEDGST0 0 ~ CRYPTO_HMAC_ SHAKEDGST0 41. + * | | |For SHAKE-256, the digest is stored in CRYPTO_HMAC_SHAKEDGST0 0 ~ CRYPTO_HMAC_ SHAKEDGST0 33. + * @var CRYPTO_T::HMAC_SHAKEDGST32 + * Offset: 0x580 SHA/HMAC SHAKE Digest Message 32 + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[31:0] |DGST |SHA/HMAC SHAKE Digest Message Register + * | | |For SHAKE-128, the digest is stored in CRYPTO_HMAC_SHAKEDGST0 0 ~ CRYPTO_HMAC_ SHAKEDGST0 41. + * | | |For SHAKE-256, the digest is stored in CRYPTO_HMAC_SHAKEDGST0 0 ~ CRYPTO_HMAC_ SHAKEDGST0 33. + * @var CRYPTO_T::HMAC_SHAKEDGST33 + * Offset: 0x584 SHA/HMAC SHAKE Digest Message 33 + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[31:0] |DGST |SHA/HMAC SHAKE Digest Message Register + * | | |For SHAKE-128, the digest is stored in CRYPTO_HMAC_SHAKEDGST0 0 ~ CRYPTO_HMAC_ SHAKEDGST0 41. + * | | |For SHAKE-256, the digest is stored in CRYPTO_HMAC_SHAKEDGST0 0 ~ CRYPTO_HMAC_ SHAKEDGST0 33. + * @var CRYPTO_T::HMAC_SHAKEDGST34 + * Offset: 0x588 SHA/HMAC SHAKE Digest Message 34 + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[31:0] |DGST |SHA/HMAC SHAKE Digest Message Register + * | | |For SHAKE-128, the digest is stored in CRYPTO_HMAC_SHAKEDGST0 0 ~ CRYPTO_HMAC_ SHAKEDGST0 41. + * | | |For SHAKE-256, the digest is stored in CRYPTO_HMAC_SHAKEDGST0 0 ~ CRYPTO_HMAC_ SHAKEDGST0 33. + * @var CRYPTO_T::HMAC_SHAKEDGST35 + * Offset: 0x58C SHA/HMAC SHAKE Digest Message 35 + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[31:0] |DGST |SHA/HMAC SHAKE Digest Message Register + * | | |For SHAKE-128, the digest is stored in CRYPTO_HMAC_SHAKEDGST0 0 ~ CRYPTO_HMAC_ SHAKEDGST0 41. + * | | |For SHAKE-256, the digest is stored in CRYPTO_HMAC_SHAKEDGST0 0 ~ CRYPTO_HMAC_ SHAKEDGST0 33. + * @var CRYPTO_T::HMAC_SHAKEDGST36 + * Offset: 0x590 SHA/HMAC SHAKE Digest Message 36 + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[31:0] |DGST |SHA/HMAC SHAKE Digest Message Register + * | | |For SHAKE-128, the digest is stored in CRYPTO_HMAC_SHAKEDGST0 0 ~ CRYPTO_HMAC_ SHAKEDGST0 41. + * | | |For SHAKE-256, the digest is stored in CRYPTO_HMAC_SHAKEDGST0 0 ~ CRYPTO_HMAC_ SHAKEDGST0 33. + * @var CRYPTO_T::HMAC_SHAKEDGST37 + * Offset: 0x594 SHA/HMAC SHAKE Digest Message 37 + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[31:0] |DGST |SHA/HMAC SHAKE Digest Message Register + * | | |For SHAKE-128, the digest is stored in CRYPTO_HMAC_SHAKEDGST0 0 ~ CRYPTO_HMAC_ SHAKEDGST0 41. + * | | |For SHAKE-256, the digest is stored in CRYPTO_HMAC_SHAKEDGST0 0 ~ CRYPTO_HMAC_ SHAKEDGST0 33. + * @var CRYPTO_T::HMAC_SHAKEDGST38 + * Offset: 0x598 SHA/HMAC SHAKE Digest Message 38 + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[31:0] |DGST |SHA/HMAC SHAKE Digest Message Register + * | | |For SHAKE-128, the digest is stored in CRYPTO_HMAC_SHAKEDGST0 0 ~ CRYPTO_HMAC_ SHAKEDGST0 41. + * | | |For SHAKE-256, the digest is stored in CRYPTO_HMAC_SHAKEDGST0 0 ~ CRYPTO_HMAC_ SHAKEDGST0 33. + * @var CRYPTO_T::HMAC_SHAKEDGST39 + * Offset: 0x59C SHA/HMAC SHAKE Digest Message 39 + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[31:0] |DGST |SHA/HMAC SHAKE Digest Message Register + * | | |For SHAKE-128, the digest is stored in CRYPTO_HMAC_SHAKEDGST0 0 ~ CRYPTO_HMAC_ SHAKEDGST0 41. + * | | |For SHAKE-256, the digest is stored in CRYPTO_HMAC_SHAKEDGST0 0 ~ CRYPTO_HMAC_ SHAKEDGST0 33. + * @var CRYPTO_T::HMAC_SHAKEDGST40 + * Offset: 0x5A0 SHA/HMAC SHAKE Digest Message 40 + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[31:0] |DGST |SHA/HMAC SHAKE Digest Message Register + * | | |For SHAKE-128, the digest is stored in CRYPTO_HMAC_SHAKEDGST0 0 ~ CRYPTO_HMAC_ SHAKEDGST0 41. + * | | |For SHAKE-256, the digest is stored in CRYPTO_HMAC_SHAKEDGST0 0 ~ CRYPTO_HMAC_ SHAKEDGST0 33. + * @var CRYPTO_T::HMAC_SHAKEDGST41 + * Offset: 0x5A4 SHA/HMAC SHAKE Digest Message 41 + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[31:0] |DGST |SHA/HMAC SHAKE Digest Message Register + * | | |For SHAKE-128, the digest is stored in CRYPTO_HMAC_SHAKEDGST0 0 ~ CRYPTO_HMAC_ SHAKEDGST0 41. + * | | |For SHAKE-256, the digest is stored in CRYPTO_HMAC_SHAKEDGST0 0 ~ CRYPTO_HMAC_ SHAKEDGST0 33. + * @var CRYPTO_T::ECC_CTL + * Offset: 0x800 ECC Control Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[0] |START |ECC Accelerator Start + * | | |0 = No effect. + * | | |1 = Start ECC accelerator. BUSY flag will be set. + * | | |This bit is always 0 when it is read back. + * | | |ECC accelerator will ignore this START signal when BUSY flag is 1. + * |[1] |STOP |ECC Accelerator Stop + * | | |0 = No effect. + * | | |1 = Abort ECC accelerator and make it into idle state. + * | | |This bit is always 0 when it is read back. + * | | |Remember to clear ECC interrupt flag after stopping ECC accelerator. + * |[4] |ECDSAS |Generate S in ECDSA Signature Generation + * | | |0 = No effect. + * | | |1 = Formula for generating S. + * | | |POINTX1 = ((POINTX2 * POINTY1 + POINTY2 ) / POINTX1) % CURVEN. + * |[5] |ECDSAR |Generate R in ECDSA Signature Generation + * | | |0 = No effect. + * | | |1 = Formula for generating R. + * | | |(POINTX1, POINTY1) = SCALARK * (POINTX1, POINTY1). + * |[7] |DMAEN |ECC Accelerator DMA Enable Bit + * | | |0 = ECC DMA engine Disabled. + * | | |1 = ECC DMA engine Enabled. + * | | |Only when START and DMAEN are 1, ECC DMA engine will be active. + * |[8] |FSEL |Field Selection + * | | |0 = Binary Field (GF(2m )). + * | | |1 = Prime Field (GF(p)). + * |[10:9] |ECCOP |Point Operation for BF and PF + * | | |00 = Point multiplication:. + * | | |(POINTX1, POINTY1) = SCALARK * (POINTX1, POINTY1). + * | | |01 = Modulus operation: choose by MODOP (CRYPTO_ECC_CTL[12:11]). + * | | |10 = Point addition:. + * | | |(POINTX1, POINTY1) = (POINTX1, POINTY1) +. + * | | |(POINTX2, POINTY2) + * | | |11 = Point doubling:. + * | | |(POINTX1, POINTY1) = 2 * (POINTX1, POINTY1). + * | | |Besides above three input data, point operations still need the parameters of elliptic curve (CURVEA, CURVEB, CURVEN and CURVEM) as shown in Figure 6.27-11 + * |[12:11] |MODOP |Modulus Operation for PF + * | | |00 = Division:. + * | | |POINTX1 = (POINTY1 / POINTX1) % CURVEN. + * | | |01 = Multiplication:. + * | | |POINTX1 = (POINTX1 * POINTY1) % CURVEN. + * | | |10 = Addition:. + * | | |POINTX1 = (POINTX1 + POINTY1) % CURVEN. + * | | |11 = Subtraction:. + * | | |POINTX1 = (POINTX1 - POINTY1) % CURVEN. + * | | |MODOP is active only when ECCOP = 01. + * |[13] |CSEL |Curve Selection + * | | |0 = NIST suggested curve. + * | | |1 = Montgomery curve. + * |[14] |SCAP |Side-channel Attack Protection + * | | |0 = Full speed without side-channel protection. + * | | |1 = Less speed with side-channel protection. + * |[15] |ASCAP |Advance Side-channel Attack Protection + * | | |0 = Advance side-channel protection Disabled. + * | | |1 = Advance side-channel protection Enabled. + * | | |ASCAP is active only when SCAP = 1. + * |[16] |LDP1 |The Control Signal of Register POINTX1 and POINTY1 for the x and Y Coordinate of the First Point + * | | |0 = The register for POINTX1 and POINTY1 is not modified by DMA or user. + * | | |1 = The register for POINTX1 and POINTY1 is modified by DMA or user. + * |[17] |LDP2 |The Control Signal of Register POINTX2 and POINTY2 for the x and Y Coordinate of the Second Point + * | | |0 = The register for POINTX2 and POINTY2 is not modified by DMA or user. + * | | |1 = The register for POINTX2 and POINTY2 is modified by DMA or user. + * |[18] |LDA |The Control Signal of Register for the Parameter CURVEA of Elliptic Curve + * | | |0 = The register for CURVEA is not modified by DMA or user. + * | | |1 = The register for CURVEA is modified by DMA or user. + * |[19] |LDB |The Control Signal of Register for the Parameter CURVEB of Elliptic Curve + * | | |0 = The register for CURVEB is not modified by DMA or user. + * | | |1 = The register for CURVEB is modified by DMA or user. + * |[20] |LDN |The Control Signal of Register for the Parameter CURVEN of Elliptic Curve + * | | |0 = The register for CURVEN is not modified by DMA or user. + * | | |1 = The register for CURVEN is modified by DMA or user. + * |[21] |LDK |The Control Signal of Register for SCALARK + * | | |0 = The register for SCALARK is not modified by DMA or user. + * | | |1 = The register for SCALARK is modified by DMA or user. + * |[31:22] |CURVEM |The key length of elliptic curve. + * @var CRYPTO_T::ECC_STS + * Offset: 0x804 ECC Status Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[0] |BUSY |ECC Accelerator Busy Flag + * | | |0 = The ECC accelerator is idle or finished. + * | | |1 = The ECC accelerator is under processing and protects all registers. + * | | |Note: Remember to clear ECC interrupt flag after ECC accelerator is finished + * |[1] |DMABUSY |ECC DMA Busy Flag + * | | |0 = ECC DMA is idle or finished. + * | | |1 = ECC DMA is busy. + * |[16] |BUSERR |ECC DMA Access Bus Error Flag + * | | |0 = No error. + * | | |1 = Bus error will stop DMA operation and ECC accelerator. + * |[17] |KSERR |ECC Engine Access Key Store Error Flag + * | | |0 = No error. + * | | |1 = Access error will stop ECC engine. + * |[18] |DFAERR |ECC Engine Differential Fault Attack Error Flag + * | | |0 = No error. + * | | |1 = Differential Fault Attack happened in ECC engine. The results from ECC engine are wrong. + * @var CRYPTO_T::ECC_X1_00 + * Offset: 0x808 ECC the X-coordinate Word0 of the First Point + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[31:0] |POINTX1 |ECC the X-coordinate Value of the First Point + * | | |For B-163 or K-163, POINTX1 is stored in CRYPTO_ECC_X1_00~CRYPTO_ECC_X1_05 + * | | |For B-233 or K-233, POINTX1 is stored in CRYPTO_ECC_X1_00~CRYPTO_ECC_X1_07 + * | | |For B-283 or K-283, POINTX1 is stored in CRYPTO_ECC_X1_00~CRYPTO_ECC_X1_08 + * | | |For B-409 or K-409, POINTX1 is stored in CRYPTO_ECC_X1_00~CRYPTO_ECC_X1_12 + * | | |For B-571 or K-571, POINTX1 is stored in CRYPTO_ECC_X1_00~CRYPTO_ECC_X1_17 + * | | |For P-192, POINTX1 is stored in CRYPTO_ECC_X1_00~CRYPTO_ECC_X1_05 + * | | |For P-224, POINTX1 is stored in CRYPTO_ECC_X1_00~CRYPTO_ECC_X1_06 + * | | |For P-256 or SM2, POINTX1 is stored in CRYPTO_ECC_X1_00~CRYPTO_ECC_X1_07 + * | | |For P-384, POINTX1 is stored in CRYPTO_ECC_X1_00~CRYPTO_ECC_X1_11 + * | | |For P-521, POINTX1 is stored in CRYPTO_ECC_X1_00~CRYPTO_ECC_X1_16 + * @var CRYPTO_T::ECC_X1_01 + * Offset: 0x80C ECC the X-coordinate Word1 of the First Point + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[31:0] |POINTX1 |ECC the X-coordinate Value of the First Point + * | | |For B-163 or K-163, POINTX1 is stored in CRYPTO_ECC_X1_00~CRYPTO_ECC_X1_05 + * | | |For B-233 or K-233, POINTX1 is stored in CRYPTO_ECC_X1_00~CRYPTO_ECC_X1_07 + * | | |For B-283 or K-283, POINTX1 is stored in CRYPTO_ECC_X1_00~CRYPTO_ECC_X1_08 + * | | |For B-409 or K-409, POINTX1 is stored in CRYPTO_ECC_X1_00~CRYPTO_ECC_X1_12 + * | | |For B-571 or K-571, POINTX1 is stored in CRYPTO_ECC_X1_00~CRYPTO_ECC_X1_17 + * | | |For P-192, POINTX1 is stored in CRYPTO_ECC_X1_00~CRYPTO_ECC_X1_05 + * | | |For P-224, POINTX1 is stored in CRYPTO_ECC_X1_00~CRYPTO_ECC_X1_06 + * | | |For P-256 or SM2, POINTX1 is stored in CRYPTO_ECC_X1_00~CRYPTO_ECC_X1_07 + * | | |For P-384, POINTX1 is stored in CRYPTO_ECC_X1_00~CRYPTO_ECC_X1_11 + * | | |For P-521, POINTX1 is stored in CRYPTO_ECC_X1_00~CRYPTO_ECC_X1_16 + * @var CRYPTO_T::ECC_X1_02 + * Offset: 0x810 ECC the X-coordinate Word2 of the First Point + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[31:0] |POINTX1 |ECC the X-coordinate Value of the First Point + * | | |For B-163 or K-163, POINTX1 is stored in CRYPTO_ECC_X1_00~CRYPTO_ECC_X1_05 + * | | |For B-233 or K-233, POINTX1 is stored in CRYPTO_ECC_X1_00~CRYPTO_ECC_X1_07 + * | | |For B-283 or K-283, POINTX1 is stored in CRYPTO_ECC_X1_00~CRYPTO_ECC_X1_08 + * | | |For B-409 or K-409, POINTX1 is stored in CRYPTO_ECC_X1_00~CRYPTO_ECC_X1_12 + * | | |For B-571 or K-571, POINTX1 is stored in CRYPTO_ECC_X1_00~CRYPTO_ECC_X1_17 + * | | |For P-192, POINTX1 is stored in CRYPTO_ECC_X1_00~CRYPTO_ECC_X1_05 + * | | |For P-224, POINTX1 is stored in CRYPTO_ECC_X1_00~CRYPTO_ECC_X1_06 + * | | |For P-256 or SM2, POINTX1 is stored in CRYPTO_ECC_X1_00~CRYPTO_ECC_X1_07 + * | | |For P-384, POINTX1 is stored in CRYPTO_ECC_X1_00~CRYPTO_ECC_X1_11 + * | | |For P-521, POINTX1 is stored in CRYPTO_ECC_X1_00~CRYPTO_ECC_X1_16 + * @var CRYPTO_T::ECC_X1_03 + * Offset: 0x814 ECC the X-coordinate Word3 of the First Point + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[31:0] |POINTX1 |ECC the X-coordinate Value of the First Point + * | | |For B-163 or K-163, POINTX1 is stored in CRYPTO_ECC_X1_00~CRYPTO_ECC_X1_05 + * | | |For B-233 or K-233, POINTX1 is stored in CRYPTO_ECC_X1_00~CRYPTO_ECC_X1_07 + * | | |For B-283 or K-283, POINTX1 is stored in CRYPTO_ECC_X1_00~CRYPTO_ECC_X1_08 + * | | |For B-409 or K-409, POINTX1 is stored in CRYPTO_ECC_X1_00~CRYPTO_ECC_X1_12 + * | | |For B-571 or K-571, POINTX1 is stored in CRYPTO_ECC_X1_00~CRYPTO_ECC_X1_17 + * | | |For P-192, POINTX1 is stored in CRYPTO_ECC_X1_00~CRYPTO_ECC_X1_05 + * | | |For P-224, POINTX1 is stored in CRYPTO_ECC_X1_00~CRYPTO_ECC_X1_06 + * | | |For P-256 or SM2, POINTX1 is stored in CRYPTO_ECC_X1_00~CRYPTO_ECC_X1_07 + * | | |For P-384, POINTX1 is stored in CRYPTO_ECC_X1_00~CRYPTO_ECC_X1_11 + * | | |For P-521, POINTX1 is stored in CRYPTO_ECC_X1_00~CRYPTO_ECC_X1_16 + * @var CRYPTO_T::ECC_X1_04 + * Offset: 0x818 ECC the X-coordinate Word4 of the First Point + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[31:0] |POINTX1 |ECC the X-coordinate Value of the First Point + * | | |For B-163 or K-163, POINTX1 is stored in CRYPTO_ECC_X1_00~CRYPTO_ECC_X1_05 + * | | |For B-233 or K-233, POINTX1 is stored in CRYPTO_ECC_X1_00~CRYPTO_ECC_X1_07 + * | | |For B-283 or K-283, POINTX1 is stored in CRYPTO_ECC_X1_00~CRYPTO_ECC_X1_08 + * | | |For B-409 or K-409, POINTX1 is stored in CRYPTO_ECC_X1_00~CRYPTO_ECC_X1_12 + * | | |For B-571 or K-571, POINTX1 is stored in CRYPTO_ECC_X1_00~CRYPTO_ECC_X1_17 + * | | |For P-192, POINTX1 is stored in CRYPTO_ECC_X1_00~CRYPTO_ECC_X1_05 + * | | |For P-224, POINTX1 is stored in CRYPTO_ECC_X1_00~CRYPTO_ECC_X1_06 + * | | |For P-256 or SM2, POINTX1 is stored in CRYPTO_ECC_X1_00~CRYPTO_ECC_X1_07 + * | | |For P-384, POINTX1 is stored in CRYPTO_ECC_X1_00~CRYPTO_ECC_X1_11 + * | | |For P-521, POINTX1 is stored in CRYPTO_ECC_X1_00~CRYPTO_ECC_X1_16 + * @var CRYPTO_T::ECC_X1_05 + * Offset: 0x81C ECC the X-coordinate Word5 of the First Point + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[31:0] |POINTX1 |ECC the X-coordinate Value of the First Point + * | | |For B-163 or K-163, POINTX1 is stored in CRYPTO_ECC_X1_00~CRYPTO_ECC_X1_05 + * | | |For B-233 or K-233, POINTX1 is stored in CRYPTO_ECC_X1_00~CRYPTO_ECC_X1_07 + * | | |For B-283 or K-283, POINTX1 is stored in CRYPTO_ECC_X1_00~CRYPTO_ECC_X1_08 + * | | |For B-409 or K-409, POINTX1 is stored in CRYPTO_ECC_X1_00~CRYPTO_ECC_X1_12 + * | | |For B-571 or K-571, POINTX1 is stored in CRYPTO_ECC_X1_00~CRYPTO_ECC_X1_17 + * | | |For P-192, POINTX1 is stored in CRYPTO_ECC_X1_00~CRYPTO_ECC_X1_05 + * | | |For P-224, POINTX1 is stored in CRYPTO_ECC_X1_00~CRYPTO_ECC_X1_06 + * | | |For P-256 or SM2, POINTX1 is stored in CRYPTO_ECC_X1_00~CRYPTO_ECC_X1_07 + * | | |For P-384, POINTX1 is stored in CRYPTO_ECC_X1_00~CRYPTO_ECC_X1_11 + * | | |For P-521, POINTX1 is stored in CRYPTO_ECC_X1_00~CRYPTO_ECC_X1_16 + * @var CRYPTO_T::ECC_X1_06 + * Offset: 0x820 ECC the X-coordinate Word6 of the First Point + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[31:0] |POINTX1 |ECC the X-coordinate Value of the First Point + * | | |For B-163 or K-163, POINTX1 is stored in CRYPTO_ECC_X1_00~CRYPTO_ECC_X1_05 + * | | |For B-233 or K-233, POINTX1 is stored in CRYPTO_ECC_X1_00~CRYPTO_ECC_X1_07 + * | | |For B-283 or K-283, POINTX1 is stored in CRYPTO_ECC_X1_00~CRYPTO_ECC_X1_08 + * | | |For B-409 or K-409, POINTX1 is stored in CRYPTO_ECC_X1_00~CRYPTO_ECC_X1_12 + * | | |For B-571 or K-571, POINTX1 is stored in CRYPTO_ECC_X1_00~CRYPTO_ECC_X1_17 + * | | |For P-192, POINTX1 is stored in CRYPTO_ECC_X1_00~CRYPTO_ECC_X1_05 + * | | |For P-224, POINTX1 is stored in CRYPTO_ECC_X1_00~CRYPTO_ECC_X1_06 + * | | |For P-256 or SM2, POINTX1 is stored in CRYPTO_ECC_X1_00~CRYPTO_ECC_X1_07 + * | | |For P-384, POINTX1 is stored in CRYPTO_ECC_X1_00~CRYPTO_ECC_X1_11 + * | | |For P-521, POINTX1 is stored in CRYPTO_ECC_X1_00~CRYPTO_ECC_X1_16 + * @var CRYPTO_T::ECC_X1_07 + * Offset: 0x824 ECC the X-coordinate Word7 of the First Point + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[31:0] |POINTX1 |ECC the X-coordinate Value of the First Point + * | | |For B-163 or K-163, POINTX1 is stored in CRYPTO_ECC_X1_00~CRYPTO_ECC_X1_05 + * | | |For B-233 or K-233, POINTX1 is stored in CRYPTO_ECC_X1_00~CRYPTO_ECC_X1_07 + * | | |For B-283 or K-283, POINTX1 is stored in CRYPTO_ECC_X1_00~CRYPTO_ECC_X1_08 + * | | |For B-409 or K-409, POINTX1 is stored in CRYPTO_ECC_X1_00~CRYPTO_ECC_X1_12 + * | | |For B-571 or K-571, POINTX1 is stored in CRYPTO_ECC_X1_00~CRYPTO_ECC_X1_17 + * | | |For P-192, POINTX1 is stored in CRYPTO_ECC_X1_00~CRYPTO_ECC_X1_05 + * | | |For P-224, POINTX1 is stored in CRYPTO_ECC_X1_00~CRYPTO_ECC_X1_06 + * | | |For P-256 or SM2, POINTX1 is stored in CRYPTO_ECC_X1_00~CRYPTO_ECC_X1_07 + * | | |For P-384, POINTX1 is stored in CRYPTO_ECC_X1_00~CRYPTO_ECC_X1_11 + * | | |For P-521, POINTX1 is stored in CRYPTO_ECC_X1_00~CRYPTO_ECC_X1_16 + * @var CRYPTO_T::ECC_X1_08 + * Offset: 0x828 ECC the X-coordinate Word8 of the First Point + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[31:0] |POINTX1 |ECC the X-coordinate Value of the First Point + * | | |For B-163 or K-163, POINTX1 is stored in CRYPTO_ECC_X1_00~CRYPTO_ECC_X1_05 + * | | |For B-233 or K-233, POINTX1 is stored in CRYPTO_ECC_X1_00~CRYPTO_ECC_X1_07 + * | | |For B-283 or K-283, POINTX1 is stored in CRYPTO_ECC_X1_00~CRYPTO_ECC_X1_08 + * | | |For B-409 or K-409, POINTX1 is stored in CRYPTO_ECC_X1_00~CRYPTO_ECC_X1_12 + * | | |For B-571 or K-571, POINTX1 is stored in CRYPTO_ECC_X1_00~CRYPTO_ECC_X1_17 + * | | |For P-192, POINTX1 is stored in CRYPTO_ECC_X1_00~CRYPTO_ECC_X1_05 + * | | |For P-224, POINTX1 is stored in CRYPTO_ECC_X1_00~CRYPTO_ECC_X1_06 + * | | |For P-256 or SM2, POINTX1 is stored in CRYPTO_ECC_X1_00~CRYPTO_ECC_X1_07 + * | | |For P-384, POINTX1 is stored in CRYPTO_ECC_X1_00~CRYPTO_ECC_X1_11 + * | | |For P-521, POINTX1 is stored in CRYPTO_ECC_X1_00~CRYPTO_ECC_X1_16 + * @var CRYPTO_T::ECC_X1_09 + * Offset: 0x82C ECC the X-coordinate Word9 of the First Point + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[31:0] |POINTX1 |ECC the X-coordinate Value of the First Point + * | | |For B-163 or K-163, POINTX1 is stored in CRYPTO_ECC_X1_00~CRYPTO_ECC_X1_05 + * | | |For B-233 or K-233, POINTX1 is stored in CRYPTO_ECC_X1_00~CRYPTO_ECC_X1_07 + * | | |For B-283 or K-283, POINTX1 is stored in CRYPTO_ECC_X1_00~CRYPTO_ECC_X1_08 + * | | |For B-409 or K-409, POINTX1 is stored in CRYPTO_ECC_X1_00~CRYPTO_ECC_X1_12 + * | | |For B-571 or K-571, POINTX1 is stored in CRYPTO_ECC_X1_00~CRYPTO_ECC_X1_17 + * | | |For P-192, POINTX1 is stored in CRYPTO_ECC_X1_00~CRYPTO_ECC_X1_05 + * | | |For P-224, POINTX1 is stored in CRYPTO_ECC_X1_00~CRYPTO_ECC_X1_06 + * | | |For P-256 or SM2, POINTX1 is stored in CRYPTO_ECC_X1_00~CRYPTO_ECC_X1_07 + * | | |For P-384, POINTX1 is stored in CRYPTO_ECC_X1_00~CRYPTO_ECC_X1_11 + * | | |For P-521, POINTX1 is stored in CRYPTO_ECC_X1_00~CRYPTO_ECC_X1_16 + * @var CRYPTO_T::ECC_X1_10 + * Offset: 0x830 ECC the X-coordinate Word10 of the First Point + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[31:0] |POINTX1 |ECC the X-coordinate Value of the First Point + * | | |For B-163 or K-163, POINTX1 is stored in CRYPTO_ECC_X1_00~CRYPTO_ECC_X1_05 + * | | |For B-233 or K-233, POINTX1 is stored in CRYPTO_ECC_X1_00~CRYPTO_ECC_X1_07 + * | | |For B-283 or K-283, POINTX1 is stored in CRYPTO_ECC_X1_00~CRYPTO_ECC_X1_08 + * | | |For B-409 or K-409, POINTX1 is stored in CRYPTO_ECC_X1_00~CRYPTO_ECC_X1_12 + * | | |For B-571 or K-571, POINTX1 is stored in CRYPTO_ECC_X1_00~CRYPTO_ECC_X1_17 + * | | |For P-192, POINTX1 is stored in CRYPTO_ECC_X1_00~CRYPTO_ECC_X1_05 + * | | |For P-224, POINTX1 is stored in CRYPTO_ECC_X1_00~CRYPTO_ECC_X1_06 + * | | |For P-256 or SM2, POINTX1 is stored in CRYPTO_ECC_X1_00~CRYPTO_ECC_X1_07 + * | | |For P-384, POINTX1 is stored in CRYPTO_ECC_X1_00~CRYPTO_ECC_X1_11 + * | | |For P-521, POINTX1 is stored in CRYPTO_ECC_X1_00~CRYPTO_ECC_X1_16 + * @var CRYPTO_T::ECC_X1_11 + * Offset: 0x834 ECC the X-coordinate Word11 of the First Point + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[31:0] |POINTX1 |ECC the X-coordinate Value of the First Point + * | | |For B-163 or K-163, POINTX1 is stored in CRYPTO_ECC_X1_00~CRYPTO_ECC_X1_05 + * | | |For B-233 or K-233, POINTX1 is stored in CRYPTO_ECC_X1_00~CRYPTO_ECC_X1_07 + * | | |For B-283 or K-283, POINTX1 is stored in CRYPTO_ECC_X1_00~CRYPTO_ECC_X1_08 + * | | |For B-409 or K-409, POINTX1 is stored in CRYPTO_ECC_X1_00~CRYPTO_ECC_X1_12 + * | | |For B-571 or K-571, POINTX1 is stored in CRYPTO_ECC_X1_00~CRYPTO_ECC_X1_17 + * | | |For P-192, POINTX1 is stored in CRYPTO_ECC_X1_00~CRYPTO_ECC_X1_05 + * | | |For P-224, POINTX1 is stored in CRYPTO_ECC_X1_00~CRYPTO_ECC_X1_06 + * | | |For P-256 or SM2, POINTX1 is stored in CRYPTO_ECC_X1_00~CRYPTO_ECC_X1_07 + * | | |For P-384, POINTX1 is stored in CRYPTO_ECC_X1_00~CRYPTO_ECC_X1_11 + * | | |For P-521, POINTX1 is stored in CRYPTO_ECC_X1_00~CRYPTO_ECC_X1_16 + * @var CRYPTO_T::ECC_X1_12 + * Offset: 0x838 ECC the X-coordinate Word12 of the First Point + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[31:0] |POINTX1 |ECC the X-coordinate Value of the First Point + * | | |For B-163 or K-163, POINTX1 is stored in CRYPTO_ECC_X1_00~CRYPTO_ECC_X1_05 + * | | |For B-233 or K-233, POINTX1 is stored in CRYPTO_ECC_X1_00~CRYPTO_ECC_X1_07 + * | | |For B-283 or K-283, POINTX1 is stored in CRYPTO_ECC_X1_00~CRYPTO_ECC_X1_08 + * | | |For B-409 or K-409, POINTX1 is stored in CRYPTO_ECC_X1_00~CRYPTO_ECC_X1_12 + * | | |For B-571 or K-571, POINTX1 is stored in CRYPTO_ECC_X1_00~CRYPTO_ECC_X1_17 + * | | |For P-192, POINTX1 is stored in CRYPTO_ECC_X1_00~CRYPTO_ECC_X1_05 + * | | |For P-224, POINTX1 is stored in CRYPTO_ECC_X1_00~CRYPTO_ECC_X1_06 + * | | |For P-256 or SM2, POINTX1 is stored in CRYPTO_ECC_X1_00~CRYPTO_ECC_X1_07 + * | | |For P-384, POINTX1 is stored in CRYPTO_ECC_X1_00~CRYPTO_ECC_X1_11 + * | | |For P-521, POINTX1 is stored in CRYPTO_ECC_X1_00~CRYPTO_ECC_X1_16 + * @var CRYPTO_T::ECC_X1_13 + * Offset: 0x83C ECC the X-coordinate Word13 of the First Point + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[31:0] |POINTX1 |ECC the X-coordinate Value of the First Point + * | | |For B-163 or K-163, POINTX1 is stored in CRYPTO_ECC_X1_00~CRYPTO_ECC_X1_05 + * | | |For B-233 or K-233, POINTX1 is stored in CRYPTO_ECC_X1_00~CRYPTO_ECC_X1_07 + * | | |For B-283 or K-283, POINTX1 is stored in CRYPTO_ECC_X1_00~CRYPTO_ECC_X1_08 + * | | |For B-409 or K-409, POINTX1 is stored in CRYPTO_ECC_X1_00~CRYPTO_ECC_X1_12 + * | | |For B-571 or K-571, POINTX1 is stored in CRYPTO_ECC_X1_00~CRYPTO_ECC_X1_17 + * | | |For P-192, POINTX1 is stored in CRYPTO_ECC_X1_00~CRYPTO_ECC_X1_05 + * | | |For P-224, POINTX1 is stored in CRYPTO_ECC_X1_00~CRYPTO_ECC_X1_06 + * | | |For P-256 or SM2, POINTX1 is stored in CRYPTO_ECC_X1_00~CRYPTO_ECC_X1_07 + * | | |For P-384, POINTX1 is stored in CRYPTO_ECC_X1_00~CRYPTO_ECC_X1_11 + * | | |For P-521, POINTX1 is stored in CRYPTO_ECC_X1_00~CRYPTO_ECC_X1_16 + * @var CRYPTO_T::ECC_X1_14 + * Offset: 0x840 ECC the X-coordinate Word14 of the First Point + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[31:0] |POINTX1 |ECC the X-coordinate Value of the First Point + * | | |For B-163 or K-163, POINTX1 is stored in CRYPTO_ECC_X1_00~CRYPTO_ECC_X1_05 + * | | |For B-233 or K-233, POINTX1 is stored in CRYPTO_ECC_X1_00~CRYPTO_ECC_X1_07 + * | | |For B-283 or K-283, POINTX1 is stored in CRYPTO_ECC_X1_00~CRYPTO_ECC_X1_08 + * | | |For B-409 or K-409, POINTX1 is stored in CRYPTO_ECC_X1_00~CRYPTO_ECC_X1_12 + * | | |For B-571 or K-571, POINTX1 is stored in CRYPTO_ECC_X1_00~CRYPTO_ECC_X1_17 + * | | |For P-192, POINTX1 is stored in CRYPTO_ECC_X1_00~CRYPTO_ECC_X1_05 + * | | |For P-224, POINTX1 is stored in CRYPTO_ECC_X1_00~CRYPTO_ECC_X1_06 + * | | |For P-256 or SM2, POINTX1 is stored in CRYPTO_ECC_X1_00~CRYPTO_ECC_X1_07 + * | | |For P-384, POINTX1 is stored in CRYPTO_ECC_X1_00~CRYPTO_ECC_X1_11 + * | | |For P-521, POINTX1 is stored in CRYPTO_ECC_X1_00~CRYPTO_ECC_X1_16 + * @var CRYPTO_T::ECC_X1_15 + * Offset: 0x844 ECC the X-coordinate Word15 of the First Point + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[31:0] |POINTX1 |ECC the X-coordinate Value of the First Point + * | | |For B-163 or K-163, POINTX1 is stored in CRYPTO_ECC_X1_00~CRYPTO_ECC_X1_05 + * | | |For B-233 or K-233, POINTX1 is stored in CRYPTO_ECC_X1_00~CRYPTO_ECC_X1_07 + * | | |For B-283 or K-283, POINTX1 is stored in CRYPTO_ECC_X1_00~CRYPTO_ECC_X1_08 + * | | |For B-409 or K-409, POINTX1 is stored in CRYPTO_ECC_X1_00~CRYPTO_ECC_X1_12 + * | | |For B-571 or K-571, POINTX1 is stored in CRYPTO_ECC_X1_00~CRYPTO_ECC_X1_17 + * | | |For P-192, POINTX1 is stored in CRYPTO_ECC_X1_00~CRYPTO_ECC_X1_05 + * | | |For P-224, POINTX1 is stored in CRYPTO_ECC_X1_00~CRYPTO_ECC_X1_06 + * | | |For P-256 or SM2, POINTX1 is stored in CRYPTO_ECC_X1_00~CRYPTO_ECC_X1_07 + * | | |For P-384, POINTX1 is stored in CRYPTO_ECC_X1_00~CRYPTO_ECC_X1_11 + * | | |For P-521, POINTX1 is stored in CRYPTO_ECC_X1_00~CRYPTO_ECC_X1_16 + * @var CRYPTO_T::ECC_X1_16 + * Offset: 0x848 ECC the X-coordinate Word16 of the First Point + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[31:0] |POINTX1 |ECC the X-coordinate Value of the First Point + * | | |For B-163 or K-163, POINTX1 is stored in CRYPTO_ECC_X1_00~CRYPTO_ECC_X1_05 + * | | |For B-233 or K-233, POINTX1 is stored in CRYPTO_ECC_X1_00~CRYPTO_ECC_X1_07 + * | | |For B-283 or K-283, POINTX1 is stored in CRYPTO_ECC_X1_00~CRYPTO_ECC_X1_08 + * | | |For B-409 or K-409, POINTX1 is stored in CRYPTO_ECC_X1_00~CRYPTO_ECC_X1_12 + * | | |For B-571 or K-571, POINTX1 is stored in CRYPTO_ECC_X1_00~CRYPTO_ECC_X1_17 + * | | |For P-192, POINTX1 is stored in CRYPTO_ECC_X1_00~CRYPTO_ECC_X1_05 + * | | |For P-224, POINTX1 is stored in CRYPTO_ECC_X1_00~CRYPTO_ECC_X1_06 + * | | |For P-256 or SM2, POINTX1 is stored in CRYPTO_ECC_X1_00~CRYPTO_ECC_X1_07 + * | | |For P-384, POINTX1 is stored in CRYPTO_ECC_X1_00~CRYPTO_ECC_X1_11 + * | | |For P-521, POINTX1 is stored in CRYPTO_ECC_X1_00~CRYPTO_ECC_X1_16 + * @var CRYPTO_T::ECC_X1_17 + * Offset: 0x84C ECC the X-coordinate Word17 of the First Point + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[31:0] |POINTX1 |ECC the X-coordinate Value of the First Point + * | | |For B-163 or K-163, POINTX1 is stored in CRYPTO_ECC_X1_00~CRYPTO_ECC_X1_05 + * | | |For B-233 or K-233, POINTX1 is stored in CRYPTO_ECC_X1_00~CRYPTO_ECC_X1_07 + * | | |For B-283 or K-283, POINTX1 is stored in CRYPTO_ECC_X1_00~CRYPTO_ECC_X1_08 + * | | |For B-409 or K-409, POINTX1 is stored in CRYPTO_ECC_X1_00~CRYPTO_ECC_X1_12 + * | | |For B-571 or K-571, POINTX1 is stored in CRYPTO_ECC_X1_00~CRYPTO_ECC_X1_17 + * | | |For P-192, POINTX1 is stored in CRYPTO_ECC_X1_00~CRYPTO_ECC_X1_05 + * | | |For P-224, POINTX1 is stored in CRYPTO_ECC_X1_00~CRYPTO_ECC_X1_06 + * | | |For P-256 or SM2, POINTX1 is stored in CRYPTO_ECC_X1_00~CRYPTO_ECC_X1_07 + * | | |For P-384, POINTX1 is stored in CRYPTO_ECC_X1_00~CRYPTO_ECC_X1_11 + * | | |For P-521, POINTX1 is stored in CRYPTO_ECC_X1_00~CRYPTO_ECC_X1_16 + * @var CRYPTO_T::ECC_Y1_00 + * Offset: 0x850 ECC the Y-coordinate Word0 of the First Point + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[31:0] |POINTY1 |ECC the Y-coordinate Value of the First Point + * | | |For B-163 or K-163, POINTY1 is stored in CRYPTO_ECC_Y1_00~CRYPTO_ECC_Y1_05 + * | | |For B-233 or K-233, POINTY1 is stored in CRYPTO_ECC_Y1_00~CRYPTO_ECC_Y1_07 + * | | |For B-283 or K-283, POINTY1 is stored in CRYPTO_ECC_Y1_00~CRYPTO_ECC_Y1_08 + * | | |For B-409 or K-409, POINTY1 is stored in CRYPTO_ECC_Y1_00~CRYPTO_ECC_Y1_12 + * | | |For B-571 or K-571, POINTY1 is stored in CRYPTO_ECC_Y1_00~CRYPTO_ECC_Y1_17 + * | | |For P-192, POINTY1 is stored in CRYPTO_ECC_Y1_00~CRYPTO_ECC_Y1_05 + * | | |For P-224, POINTY1 is stored in CRYPTO_ECC_Y1_00~CRYPTO_ECC_Y1_06 + * | | |For P-256 or SM2, POINTY1 is stored in CRYPTO_ECC_Y1_00~CRYPTO_ECC_Y1_07 + * | | |For P-384, POINTY1 is stored in CRYPTO_ECC_Y1_00~CRYPTO_ECC_Y1_11 + * | | |For P-521, POINTY1 is stored in CRYPTO_ECC_Y1_00~CRYPTO_ECC_Y1_16 + * @var CRYPTO_T::ECC_Y1_01 + * Offset: 0x854 ECC the Y-coordinate Word1 of the First Point + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[31:0] |POINTY1 |ECC the Y-coordinate Value of the First Point + * | | |For B-163 or K-163, POINTY1 is stored in CRYPTO_ECC_Y1_00~CRYPTO_ECC_Y1_05 + * | | |For B-233 or K-233, POINTY1 is stored in CRYPTO_ECC_Y1_00~CRYPTO_ECC_Y1_07 + * | | |For B-283 or K-283, POINTY1 is stored in CRYPTO_ECC_Y1_00~CRYPTO_ECC_Y1_08 + * | | |For B-409 or K-409, POINTY1 is stored in CRYPTO_ECC_Y1_00~CRYPTO_ECC_Y1_12 + * | | |For B-571 or K-571, POINTY1 is stored in CRYPTO_ECC_Y1_00~CRYPTO_ECC_Y1_17 + * | | |For P-192, POINTY1 is stored in CRYPTO_ECC_Y1_00~CRYPTO_ECC_Y1_05 + * | | |For P-224, POINTY1 is stored in CRYPTO_ECC_Y1_00~CRYPTO_ECC_Y1_06 + * | | |For P-256 or SM2, POINTY1 is stored in CRYPTO_ECC_Y1_00~CRYPTO_ECC_Y1_07 + * | | |For P-384, POINTY1 is stored in CRYPTO_ECC_Y1_00~CRYPTO_ECC_Y1_11 + * | | |For P-521, POINTY1 is stored in CRYPTO_ECC_Y1_00~CRYPTO_ECC_Y1_16 + * @var CRYPTO_T::ECC_Y1_02 + * Offset: 0x858 ECC the Y-coordinate Word2 of the First Point + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[31:0] |POINTY1 |ECC the Y-coordinate Value of the First Point + * | | |For B-163 or K-163, POINTY1 is stored in CRYPTO_ECC_Y1_00~CRYPTO_ECC_Y1_05 + * | | |For B-233 or K-233, POINTY1 is stored in CRYPTO_ECC_Y1_00~CRYPTO_ECC_Y1_07 + * | | |For B-283 or K-283, POINTY1 is stored in CRYPTO_ECC_Y1_00~CRYPTO_ECC_Y1_08 + * | | |For B-409 or K-409, POINTY1 is stored in CRYPTO_ECC_Y1_00~CRYPTO_ECC_Y1_12 + * | | |For B-571 or K-571, POINTY1 is stored in CRYPTO_ECC_Y1_00~CRYPTO_ECC_Y1_17 + * | | |For P-192, POINTY1 is stored in CRYPTO_ECC_Y1_00~CRYPTO_ECC_Y1_05 + * | | |For P-224, POINTY1 is stored in CRYPTO_ECC_Y1_00~CRYPTO_ECC_Y1_06 + * | | |For P-256 or SM2, POINTY1 is stored in CRYPTO_ECC_Y1_00~CRYPTO_ECC_Y1_07 + * | | |For P-384, POINTY1 is stored in CRYPTO_ECC_Y1_00~CRYPTO_ECC_Y1_11 + * | | |For P-521, POINTY1 is stored in CRYPTO_ECC_Y1_00~CRYPTO_ECC_Y1_16 + * @var CRYPTO_T::ECC_Y1_03 + * Offset: 0x85C ECC the Y-coordinate Word3 of the First Point + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[31:0] |POINTY1 |ECC the Y-coordinate Value of the First Point + * | | |For B-163 or K-163, POINTY1 is stored in CRYPTO_ECC_Y1_00~CRYPTO_ECC_Y1_05 + * | | |For B-233 or K-233, POINTY1 is stored in CRYPTO_ECC_Y1_00~CRYPTO_ECC_Y1_07 + * | | |For B-283 or K-283, POINTY1 is stored in CRYPTO_ECC_Y1_00~CRYPTO_ECC_Y1_08 + * | | |For B-409 or K-409, POINTY1 is stored in CRYPTO_ECC_Y1_00~CRYPTO_ECC_Y1_12 + * | | |For B-571 or K-571, POINTY1 is stored in CRYPTO_ECC_Y1_00~CRYPTO_ECC_Y1_17 + * | | |For P-192, POINTY1 is stored in CRYPTO_ECC_Y1_00~CRYPTO_ECC_Y1_05 + * | | |For P-224, POINTY1 is stored in CRYPTO_ECC_Y1_00~CRYPTO_ECC_Y1_06 + * | | |For P-256 or SM2, POINTY1 is stored in CRYPTO_ECC_Y1_00~CRYPTO_ECC_Y1_07 + * | | |For P-384, POINTY1 is stored in CRYPTO_ECC_Y1_00~CRYPTO_ECC_Y1_11 + * | | |For P-521, POINTY1 is stored in CRYPTO_ECC_Y1_00~CRYPTO_ECC_Y1_16 + * @var CRYPTO_T::ECC_Y1_04 + * Offset: 0x860 ECC the Y-coordinate Word4 of the First Point + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[31:0] |POINTY1 |ECC the Y-coordinate Value of the First Point + * | | |For B-163 or K-163, POINTY1 is stored in CRYPTO_ECC_Y1_00~CRYPTO_ECC_Y1_05 + * | | |For B-233 or K-233, POINTY1 is stored in CRYPTO_ECC_Y1_00~CRYPTO_ECC_Y1_07 + * | | |For B-283 or K-283, POINTY1 is stored in CRYPTO_ECC_Y1_00~CRYPTO_ECC_Y1_08 + * | | |For B-409 or K-409, POINTY1 is stored in CRYPTO_ECC_Y1_00~CRYPTO_ECC_Y1_12 + * | | |For B-571 or K-571, POINTY1 is stored in CRYPTO_ECC_Y1_00~CRYPTO_ECC_Y1_17 + * | | |For P-192, POINTY1 is stored in CRYPTO_ECC_Y1_00~CRYPTO_ECC_Y1_05 + * | | |For P-224, POINTY1 is stored in CRYPTO_ECC_Y1_00~CRYPTO_ECC_Y1_06 + * | | |For P-256 or SM2, POINTY1 is stored in CRYPTO_ECC_Y1_00~CRYPTO_ECC_Y1_07 + * | | |For P-384, POINTY1 is stored in CRYPTO_ECC_Y1_00~CRYPTO_ECC_Y1_11 + * | | |For P-521, POINTY1 is stored in CRYPTO_ECC_Y1_00~CRYPTO_ECC_Y1_16 + * @var CRYPTO_T::ECC_Y1_05 + * Offset: 0x864 ECC the Y-coordinate Word5 of the First Point + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[31:0] |POINTY1 |ECC the Y-coordinate Value of the First Point + * | | |For B-163 or K-163, POINTY1 is stored in CRYPTO_ECC_Y1_00~CRYPTO_ECC_Y1_05 + * | | |For B-233 or K-233, POINTY1 is stored in CRYPTO_ECC_Y1_00~CRYPTO_ECC_Y1_07 + * | | |For B-283 or K-283, POINTY1 is stored in CRYPTO_ECC_Y1_00~CRYPTO_ECC_Y1_08 + * | | |For B-409 or K-409, POINTY1 is stored in CRYPTO_ECC_Y1_00~CRYPTO_ECC_Y1_12 + * | | |For B-571 or K-571, POINTY1 is stored in CRYPTO_ECC_Y1_00~CRYPTO_ECC_Y1_17 + * | | |For P-192, POINTY1 is stored in CRYPTO_ECC_Y1_00~CRYPTO_ECC_Y1_05 + * | | |For P-224, POINTY1 is stored in CRYPTO_ECC_Y1_00~CRYPTO_ECC_Y1_06 + * | | |For P-256 or SM2, POINTY1 is stored in CRYPTO_ECC_Y1_00~CRYPTO_ECC_Y1_07 + * | | |For P-384, POINTY1 is stored in CRYPTO_ECC_Y1_00~CRYPTO_ECC_Y1_11 + * | | |For P-521, POINTY1 is stored in CRYPTO_ECC_Y1_00~CRYPTO_ECC_Y1_16 + * @var CRYPTO_T::ECC_Y1_06 + * Offset: 0x868 ECC the Y-coordinate Word6 of the First Point + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[31:0] |POINTY1 |ECC the Y-coordinate Value of the First Point + * | | |For B-163 or K-163, POINTY1 is stored in CRYPTO_ECC_Y1_00~CRYPTO_ECC_Y1_05 + * | | |For B-233 or K-233, POINTY1 is stored in CRYPTO_ECC_Y1_00~CRYPTO_ECC_Y1_07 + * | | |For B-283 or K-283, POINTY1 is stored in CRYPTO_ECC_Y1_00~CRYPTO_ECC_Y1_08 + * | | |For B-409 or K-409, POINTY1 is stored in CRYPTO_ECC_Y1_00~CRYPTO_ECC_Y1_12 + * | | |For B-571 or K-571, POINTY1 is stored in CRYPTO_ECC_Y1_00~CRYPTO_ECC_Y1_17 + * | | |For P-192, POINTY1 is stored in CRYPTO_ECC_Y1_00~CRYPTO_ECC_Y1_05 + * | | |For P-224, POINTY1 is stored in CRYPTO_ECC_Y1_00~CRYPTO_ECC_Y1_06 + * | | |For P-256 or SM2, POINTY1 is stored in CRYPTO_ECC_Y1_00~CRYPTO_ECC_Y1_07 + * | | |For P-384, POINTY1 is stored in CRYPTO_ECC_Y1_00~CRYPTO_ECC_Y1_11 + * | | |For P-521, POINTY1 is stored in CRYPTO_ECC_Y1_00~CRYPTO_ECC_Y1_16 + * @var CRYPTO_T::ECC_Y1_07 + * Offset: 0x86C ECC the Y-coordinate Word7 of the First Point + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[31:0] |POINTY1 |ECC the Y-coordinate Value of the First Point + * | | |For B-163 or K-163, POINTY1 is stored in CRYPTO_ECC_Y1_00~CRYPTO_ECC_Y1_05 + * | | |For B-233 or K-233, POINTY1 is stored in CRYPTO_ECC_Y1_00~CRYPTO_ECC_Y1_07 + * | | |For B-283 or K-283, POINTY1 is stored in CRYPTO_ECC_Y1_00~CRYPTO_ECC_Y1_08 + * | | |For B-409 or K-409, POINTY1 is stored in CRYPTO_ECC_Y1_00~CRYPTO_ECC_Y1_12 + * | | |For B-571 or K-571, POINTY1 is stored in CRYPTO_ECC_Y1_00~CRYPTO_ECC_Y1_17 + * | | |For P-192, POINTY1 is stored in CRYPTO_ECC_Y1_00~CRYPTO_ECC_Y1_05 + * | | |For P-224, POINTY1 is stored in CRYPTO_ECC_Y1_00~CRYPTO_ECC_Y1_06 + * | | |For P-256 or SM2, POINTY1 is stored in CRYPTO_ECC_Y1_00~CRYPTO_ECC_Y1_07 + * | | |For P-384, POINTY1 is stored in CRYPTO_ECC_Y1_00~CRYPTO_ECC_Y1_11 + * | | |For P-521, POINTY1 is stored in CRYPTO_ECC_Y1_00~CRYPTO_ECC_Y1_16 + * @var CRYPTO_T::ECC_Y1_08 + * Offset: 0x870 ECC the Y-coordinate Word8 of the First Point + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[31:0] |POINTY1 |ECC the Y-coordinate Value of the First Point + * | | |For B-163 or K-163, POINTY1 is stored in CRYPTO_ECC_Y1_00~CRYPTO_ECC_Y1_05 + * | | |For B-233 or K-233, POINTY1 is stored in CRYPTO_ECC_Y1_00~CRYPTO_ECC_Y1_07 + * | | |For B-283 or K-283, POINTY1 is stored in CRYPTO_ECC_Y1_00~CRYPTO_ECC_Y1_08 + * | | |For B-409 or K-409, POINTY1 is stored in CRYPTO_ECC_Y1_00~CRYPTO_ECC_Y1_12 + * | | |For B-571 or K-571, POINTY1 is stored in CRYPTO_ECC_Y1_00~CRYPTO_ECC_Y1_17 + * | | |For P-192, POINTY1 is stored in CRYPTO_ECC_Y1_00~CRYPTO_ECC_Y1_05 + * | | |For P-224, POINTY1 is stored in CRYPTO_ECC_Y1_00~CRYPTO_ECC_Y1_06 + * | | |For P-256 or SM2, POINTY1 is stored in CRYPTO_ECC_Y1_00~CRYPTO_ECC_Y1_07 + * | | |For P-384, POINTY1 is stored in CRYPTO_ECC_Y1_00~CRYPTO_ECC_Y1_11 + * | | |For P-521, POINTY1 is stored in CRYPTO_ECC_Y1_00~CRYPTO_ECC_Y1_16 + * @var CRYPTO_T::ECC_Y1_09 + * Offset: 0x874 ECC the Y-coordinate Word9 of the First Point + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[31:0] |POINTY1 |ECC the Y-coordinate Value of the First Point + * | | |For B-163 or K-163, POINTY1 is stored in CRYPTO_ECC_Y1_00~CRYPTO_ECC_Y1_05 + * | | |For B-233 or K-233, POINTY1 is stored in CRYPTO_ECC_Y1_00~CRYPTO_ECC_Y1_07 + * | | |For B-283 or K-283, POINTY1 is stored in CRYPTO_ECC_Y1_00~CRYPTO_ECC_Y1_08 + * | | |For B-409 or K-409, POINTY1 is stored in CRYPTO_ECC_Y1_00~CRYPTO_ECC_Y1_12 + * | | |For B-571 or K-571, POINTY1 is stored in CRYPTO_ECC_Y1_00~CRYPTO_ECC_Y1_17 + * | | |For P-192, POINTY1 is stored in CRYPTO_ECC_Y1_00~CRYPTO_ECC_Y1_05 + * | | |For P-224, POINTY1 is stored in CRYPTO_ECC_Y1_00~CRYPTO_ECC_Y1_06 + * | | |For P-256 or SM2, POINTY1 is stored in CRYPTO_ECC_Y1_00~CRYPTO_ECC_Y1_07 + * | | |For P-384, POINTY1 is stored in CRYPTO_ECC_Y1_00~CRYPTO_ECC_Y1_11 + * | | |For P-521, POINTY1 is stored in CRYPTO_ECC_Y1_00~CRYPTO_ECC_Y1_16 + * @var CRYPTO_T::ECC_Y1_10 + * Offset: 0x878 ECC the Y-coordinate Word10 of the First Point + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[31:0] |POINTY1 |ECC the Y-coordinate Value of the First Point + * | | |For B-163 or K-163, POINTY1 is stored in CRYPTO_ECC_Y1_00~CRYPTO_ECC_Y1_05 + * | | |For B-233 or K-233, POINTY1 is stored in CRYPTO_ECC_Y1_00~CRYPTO_ECC_Y1_07 + * | | |For B-283 or K-283, POINTY1 is stored in CRYPTO_ECC_Y1_00~CRYPTO_ECC_Y1_08 + * | | |For B-409 or K-409, POINTY1 is stored in CRYPTO_ECC_Y1_00~CRYPTO_ECC_Y1_12 + * | | |For B-571 or K-571, POINTY1 is stored in CRYPTO_ECC_Y1_00~CRYPTO_ECC_Y1_17 + * | | |For P-192, POINTY1 is stored in CRYPTO_ECC_Y1_00~CRYPTO_ECC_Y1_05 + * | | |For P-224, POINTY1 is stored in CRYPTO_ECC_Y1_00~CRYPTO_ECC_Y1_06 + * | | |For P-256 or SM2, POINTY1 is stored in CRYPTO_ECC_Y1_00~CRYPTO_ECC_Y1_07 + * | | |For P-384, POINTY1 is stored in CRYPTO_ECC_Y1_00~CRYPTO_ECC_Y1_11 + * | | |For P-521, POINTY1 is stored in CRYPTO_ECC_Y1_00~CRYPTO_ECC_Y1_16 + * @var CRYPTO_T::ECC_Y1_11 + * Offset: 0x87C ECC the Y-coordinate Word11 of the First Point + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[31:0] |POINTY1 |ECC the Y-coordinate Value of the First Point + * | | |For B-163 or K-163, POINTY1 is stored in CRYPTO_ECC_Y1_00~CRYPTO_ECC_Y1_05 + * | | |For B-233 or K-233, POINTY1 is stored in CRYPTO_ECC_Y1_00~CRYPTO_ECC_Y1_07 + * | | |For B-283 or K-283, POINTY1 is stored in CRYPTO_ECC_Y1_00~CRYPTO_ECC_Y1_08 + * | | |For B-409 or K-409, POINTY1 is stored in CRYPTO_ECC_Y1_00~CRYPTO_ECC_Y1_12 + * | | |For B-571 or K-571, POINTY1 is stored in CRYPTO_ECC_Y1_00~CRYPTO_ECC_Y1_17 + * | | |For P-192, POINTY1 is stored in CRYPTO_ECC_Y1_00~CRYPTO_ECC_Y1_05 + * | | |For P-224, POINTY1 is stored in CRYPTO_ECC_Y1_00~CRYPTO_ECC_Y1_06 + * | | |For P-256 or SM2, POINTY1 is stored in CRYPTO_ECC_Y1_00~CRYPTO_ECC_Y1_07 + * | | |For P-384, POINTY1 is stored in CRYPTO_ECC_Y1_00~CRYPTO_ECC_Y1_11 + * | | |For P-521, POINTY1 is stored in CRYPTO_ECC_Y1_00~CRYPTO_ECC_Y1_16 + * @var CRYPTO_T::ECC_Y1_12 + * Offset: 0x880 ECC the Y-coordinate Word12 of the First Point + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[31:0] |POINTY1 |ECC the Y-coordinate Value of the First Point + * | | |For B-163 or K-163, POINTY1 is stored in CRYPTO_ECC_Y1_00~CRYPTO_ECC_Y1_05 + * | | |For B-233 or K-233, POINTY1 is stored in CRYPTO_ECC_Y1_00~CRYPTO_ECC_Y1_07 + * | | |For B-283 or K-283, POINTY1 is stored in CRYPTO_ECC_Y1_00~CRYPTO_ECC_Y1_08 + * | | |For B-409 or K-409, POINTY1 is stored in CRYPTO_ECC_Y1_00~CRYPTO_ECC_Y1_12 + * | | |For B-571 or K-571, POINTY1 is stored in CRYPTO_ECC_Y1_00~CRYPTO_ECC_Y1_17 + * | | |For P-192, POINTY1 is stored in CRYPTO_ECC_Y1_00~CRYPTO_ECC_Y1_05 + * | | |For P-224, POINTY1 is stored in CRYPTO_ECC_Y1_00~CRYPTO_ECC_Y1_06 + * | | |For P-256 or SM2, POINTY1 is stored in CRYPTO_ECC_Y1_00~CRYPTO_ECC_Y1_07 + * | | |For P-384, POINTY1 is stored in CRYPTO_ECC_Y1_00~CRYPTO_ECC_Y1_11 + * | | |For P-521, POINTY1 is stored in CRYPTO_ECC_Y1_00~CRYPTO_ECC_Y1_16 + * @var CRYPTO_T::ECC_Y1_13 + * Offset: 0x884 ECC the Y-coordinate Word13 of the First Point + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[31:0] |POINTY1 |ECC the Y-coordinate Value of the First Point + * | | |For B-163 or K-163, POINTY1 is stored in CRYPTO_ECC_Y1_00~CRYPTO_ECC_Y1_05 + * | | |For B-233 or K-233, POINTY1 is stored in CRYPTO_ECC_Y1_00~CRYPTO_ECC_Y1_07 + * | | |For B-283 or K-283, POINTY1 is stored in CRYPTO_ECC_Y1_00~CRYPTO_ECC_Y1_08 + * | | |For B-409 or K-409, POINTY1 is stored in CRYPTO_ECC_Y1_00~CRYPTO_ECC_Y1_12 + * | | |For B-571 or K-571, POINTY1 is stored in CRYPTO_ECC_Y1_00~CRYPTO_ECC_Y1_17 + * | | |For P-192, POINTY1 is stored in CRYPTO_ECC_Y1_00~CRYPTO_ECC_Y1_05 + * | | |For P-224, POINTY1 is stored in CRYPTO_ECC_Y1_00~CRYPTO_ECC_Y1_06 + * | | |For P-256 or SM2, POINTY1 is stored in CRYPTO_ECC_Y1_00~CRYPTO_ECC_Y1_07 + * | | |For P-384, POINTY1 is stored in CRYPTO_ECC_Y1_00~CRYPTO_ECC_Y1_11 + * | | |For P-521, POINTY1 is stored in CRYPTO_ECC_Y1_00~CRYPTO_ECC_Y1_16 + * @var CRYPTO_T::ECC_Y1_14 + * Offset: 0x888 ECC the Y-coordinate Word14 of the First Point + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[31:0] |POINTY1 |ECC the Y-coordinate Value of the First Point + * | | |For B-163 or K-163, POINTY1 is stored in CRYPTO_ECC_Y1_00~CRYPTO_ECC_Y1_05 + * | | |For B-233 or K-233, POINTY1 is stored in CRYPTO_ECC_Y1_00~CRYPTO_ECC_Y1_07 + * | | |For B-283 or K-283, POINTY1 is stored in CRYPTO_ECC_Y1_00~CRYPTO_ECC_Y1_08 + * | | |For B-409 or K-409, POINTY1 is stored in CRYPTO_ECC_Y1_00~CRYPTO_ECC_Y1_12 + * | | |For B-571 or K-571, POINTY1 is stored in CRYPTO_ECC_Y1_00~CRYPTO_ECC_Y1_17 + * | | |For P-192, POINTY1 is stored in CRYPTO_ECC_Y1_00~CRYPTO_ECC_Y1_05 + * | | |For P-224, POINTY1 is stored in CRYPTO_ECC_Y1_00~CRYPTO_ECC_Y1_06 + * | | |For P-256 or SM2, POINTY1 is stored in CRYPTO_ECC_Y1_00~CRYPTO_ECC_Y1_07 + * | | |For P-384, POINTY1 is stored in CRYPTO_ECC_Y1_00~CRYPTO_ECC_Y1_11 + * | | |For P-521, POINTY1 is stored in CRYPTO_ECC_Y1_00~CRYPTO_ECC_Y1_16 + * @var CRYPTO_T::ECC_Y1_15 + * Offset: 0x88C ECC the Y-coordinate Word15 of the First Point + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[31:0] |POINTY1 |ECC the Y-coordinate Value of the First Point + * | | |For B-163 or K-163, POINTY1 is stored in CRYPTO_ECC_Y1_00~CRYPTO_ECC_Y1_05 + * | | |For B-233 or K-233, POINTY1 is stored in CRYPTO_ECC_Y1_00~CRYPTO_ECC_Y1_07 + * | | |For B-283 or K-283, POINTY1 is stored in CRYPTO_ECC_Y1_00~CRYPTO_ECC_Y1_08 + * | | |For B-409 or K-409, POINTY1 is stored in CRYPTO_ECC_Y1_00~CRYPTO_ECC_Y1_12 + * | | |For B-571 or K-571, POINTY1 is stored in CRYPTO_ECC_Y1_00~CRYPTO_ECC_Y1_17 + * | | |For P-192, POINTY1 is stored in CRYPTO_ECC_Y1_00~CRYPTO_ECC_Y1_05 + * | | |For P-224, POINTY1 is stored in CRYPTO_ECC_Y1_00~CRYPTO_ECC_Y1_06 + * | | |For P-256 or SM2, POINTY1 is stored in CRYPTO_ECC_Y1_00~CRYPTO_ECC_Y1_07 + * | | |For P-384, POINTY1 is stored in CRYPTO_ECC_Y1_00~CRYPTO_ECC_Y1_11 + * | | |For P-521, POINTY1 is stored in CRYPTO_ECC_Y1_00~CRYPTO_ECC_Y1_16 + * @var CRYPTO_T::ECC_Y1_16 + * Offset: 0x890 ECC the Y-coordinate Word16 of the First Point + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[31:0] |POINTY1 |ECC the Y-coordinate Value of the First Point + * | | |For B-163 or K-163, POINTY1 is stored in CRYPTO_ECC_Y1_00~CRYPTO_ECC_Y1_05 + * | | |For B-233 or K-233, POINTY1 is stored in CRYPTO_ECC_Y1_00~CRYPTO_ECC_Y1_07 + * | | |For B-283 or K-283, POINTY1 is stored in CRYPTO_ECC_Y1_00~CRYPTO_ECC_Y1_08 + * | | |For B-409 or K-409, POINTY1 is stored in CRYPTO_ECC_Y1_00~CRYPTO_ECC_Y1_12 + * | | |For B-571 or K-571, POINTY1 is stored in CRYPTO_ECC_Y1_00~CRYPTO_ECC_Y1_17 + * | | |For P-192, POINTY1 is stored in CRYPTO_ECC_Y1_00~CRYPTO_ECC_Y1_05 + * | | |For P-224, POINTY1 is stored in CRYPTO_ECC_Y1_00~CRYPTO_ECC_Y1_06 + * | | |For P-256 or SM2, POINTY1 is stored in CRYPTO_ECC_Y1_00~CRYPTO_ECC_Y1_07 + * | | |For P-384, POINTY1 is stored in CRYPTO_ECC_Y1_00~CRYPTO_ECC_Y1_11 + * | | |For P-521, POINTY1 is stored in CRYPTO_ECC_Y1_00~CRYPTO_ECC_Y1_16 + * @var CRYPTO_T::ECC_Y1_17 + * Offset: 0x894 ECC the Y-coordinate Word17 of the First Point + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[31:0] |POINTY1 |ECC the Y-coordinate Value of the First Point + * | | |For B-163 or K-163, POINTY1 is stored in CRYPTO_ECC_Y1_00~CRYPTO_ECC_Y1_05 + * | | |For B-233 or K-233, POINTY1 is stored in CRYPTO_ECC_Y1_00~CRYPTO_ECC_Y1_07 + * | | |For B-283 or K-283, POINTY1 is stored in CRYPTO_ECC_Y1_00~CRYPTO_ECC_Y1_08 + * | | |For B-409 or K-409, POINTY1 is stored in CRYPTO_ECC_Y1_00~CRYPTO_ECC_Y1_12 + * | | |For B-571 or K-571, POINTY1 is stored in CRYPTO_ECC_Y1_00~CRYPTO_ECC_Y1_17 + * | | |For P-192, POINTY1 is stored in CRYPTO_ECC_Y1_00~CRYPTO_ECC_Y1_05 + * | | |For P-224, POINTY1 is stored in CRYPTO_ECC_Y1_00~CRYPTO_ECC_Y1_06 + * | | |For P-256 or SM2, POINTY1 is stored in CRYPTO_ECC_Y1_00~CRYPTO_ECC_Y1_07 + * | | |For P-384, POINTY1 is stored in CRYPTO_ECC_Y1_00~CRYPTO_ECC_Y1_11 + * | | |For P-521, POINTY1 is stored in CRYPTO_ECC_Y1_00~CRYPTO_ECC_Y1_16 + * @var CRYPTO_T::ECC_X2_00 + * Offset: 0x898 ECC the X-coordinate Word0 of the Second Point + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[31:0] |POINTX2 |ECC the X-coordinate Value of the Second Point + * | | |For B-163 or K-163, POINTX2 is stored in CRYPTO_ECC_X2_00~CRYPTO_ECC_X2_05 + * | | |For B-233 or K-233, POINTX2 is stored in CRYPTO_ECC_X2_00~CRYPTO_ECC_X2_07 + * | | |For B-283 or K-283, POINTX2 is stored in CRYPTO_ECC_X2_00~CRYPTO_ECC_X2_08 + * | | |For B-409 or K-409, POINTX2 is stored in CRYPTO_ECC_X2_00~CRYPTO_ECC_X2_12 + * | | |For B-571 or K-571, POINTX2 is stored in CRYPTO_ECC_X2_00~CRYPTO_ECC_X2_17 + * | | |For P-192, POINTX2 is stored in CRYPTO_ECC_X2_00~CRYPTO_ECC_X2_05 + * | | |For P-224, POINTX2 is stored in CRYPTO_ECC_X2_00~CRYPTO_ECC_X2_06 + * | | |For P-256 or SM2, POINTX2 is stored in CRYPTO_ECC_X2_00~CRYPTO_ECC_X2_07 + * | | |For P-384, POINTX2 is stored in CRYPTO_ECC_X2_00~CRYPTO_ECC_X2_11 + * | | |For P-521, POINTX2 is stored in CRYPTO_ECC_X2_00~CRYPTO_ECC_X2_16 + * @var CRYPTO_T::ECC_X2_01 + * Offset: 0x89C ECC the X-coordinate Word1 of the Second Point + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[31:0] |POINTX2 |ECC the X-coordinate Value of the Second Point + * | | |For B-163 or K-163, POINTX2 is stored in CRYPTO_ECC_X2_00~CRYPTO_ECC_X2_05 + * | | |For B-233 or K-233, POINTX2 is stored in CRYPTO_ECC_X2_00~CRYPTO_ECC_X2_07 + * | | |For B-283 or K-283, POINTX2 is stored in CRYPTO_ECC_X2_00~CRYPTO_ECC_X2_08 + * | | |For B-409 or K-409, POINTX2 is stored in CRYPTO_ECC_X2_00~CRYPTO_ECC_X2_12 + * | | |For B-571 or K-571, POINTX2 is stored in CRYPTO_ECC_X2_00~CRYPTO_ECC_X2_17 + * | | |For P-192, POINTX2 is stored in CRYPTO_ECC_X2_00~CRYPTO_ECC_X2_05 + * | | |For P-224, POINTX2 is stored in CRYPTO_ECC_X2_00~CRYPTO_ECC_X2_06 + * | | |For P-256 or SM2, POINTX2 is stored in CRYPTO_ECC_X2_00~CRYPTO_ECC_X2_07 + * | | |For P-384, POINTX2 is stored in CRYPTO_ECC_X2_00~CRYPTO_ECC_X2_11 + * | | |For P-521, POINTX2 is stored in CRYPTO_ECC_X2_00~CRYPTO_ECC_X2_16 + * @var CRYPTO_T::ECC_X2_02 + * Offset: 0x8A0 ECC the X-coordinate Word2 of the Second Point + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[31:0] |POINTX2 |ECC the X-coordinate Value of the Second Point + * | | |For B-163 or K-163, POINTX2 is stored in CRYPTO_ECC_X2_00~CRYPTO_ECC_X2_05 + * | | |For B-233 or K-233, POINTX2 is stored in CRYPTO_ECC_X2_00~CRYPTO_ECC_X2_07 + * | | |For B-283 or K-283, POINTX2 is stored in CRYPTO_ECC_X2_00~CRYPTO_ECC_X2_08 + * | | |For B-409 or K-409, POINTX2 is stored in CRYPTO_ECC_X2_00~CRYPTO_ECC_X2_12 + * | | |For B-571 or K-571, POINTX2 is stored in CRYPTO_ECC_X2_00~CRYPTO_ECC_X2_17 + * | | |For P-192, POINTX2 is stored in CRYPTO_ECC_X2_00~CRYPTO_ECC_X2_05 + * | | |For P-224, POINTX2 is stored in CRYPTO_ECC_X2_00~CRYPTO_ECC_X2_06 + * | | |For P-256 or SM2, POINTX2 is stored in CRYPTO_ECC_X2_00~CRYPTO_ECC_X2_07 + * | | |For P-384, POINTX2 is stored in CRYPTO_ECC_X2_00~CRYPTO_ECC_X2_11 + * | | |For P-521, POINTX2 is stored in CRYPTO_ECC_X2_00~CRYPTO_ECC_X2_16 + * @var CRYPTO_T::ECC_X2_03 + * Offset: 0x8A4 ECC the X-coordinate Word3 of the Second Point + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[31:0] |POINTX2 |ECC the X-coordinate Value of the Second Point + * | | |For B-163 or K-163, POINTX2 is stored in CRYPTO_ECC_X2_00~CRYPTO_ECC_X2_05 + * | | |For B-233 or K-233, POINTX2 is stored in CRYPTO_ECC_X2_00~CRYPTO_ECC_X2_07 + * | | |For B-283 or K-283, POINTX2 is stored in CRYPTO_ECC_X2_00~CRYPTO_ECC_X2_08 + * | | |For B-409 or K-409, POINTX2 is stored in CRYPTO_ECC_X2_00~CRYPTO_ECC_X2_12 + * | | |For B-571 or K-571, POINTX2 is stored in CRYPTO_ECC_X2_00~CRYPTO_ECC_X2_17 + * | | |For P-192, POINTX2 is stored in CRYPTO_ECC_X2_00~CRYPTO_ECC_X2_05 + * | | |For P-224, POINTX2 is stored in CRYPTO_ECC_X2_00~CRYPTO_ECC_X2_06 + * | | |For P-256 or SM2, POINTX2 is stored in CRYPTO_ECC_X2_00~CRYPTO_ECC_X2_07 + * | | |For P-384, POINTX2 is stored in CRYPTO_ECC_X2_00~CRYPTO_ECC_X2_11 + * | | |For P-521, POINTX2 is stored in CRYPTO_ECC_X2_00~CRYPTO_ECC_X2_16 + * @var CRYPTO_T::ECC_X2_04 + * Offset: 0x8A8 ECC the X-coordinate Word4 of the Second Point + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[31:0] |POINTX2 |ECC the X-coordinate Value of the Second Point + * | | |For B-163 or K-163, POINTX2 is stored in CRYPTO_ECC_X2_00~CRYPTO_ECC_X2_05 + * | | |For B-233 or K-233, POINTX2 is stored in CRYPTO_ECC_X2_00~CRYPTO_ECC_X2_07 + * | | |For B-283 or K-283, POINTX2 is stored in CRYPTO_ECC_X2_00~CRYPTO_ECC_X2_08 + * | | |For B-409 or K-409, POINTX2 is stored in CRYPTO_ECC_X2_00~CRYPTO_ECC_X2_12 + * | | |For B-571 or K-571, POINTX2 is stored in CRYPTO_ECC_X2_00~CRYPTO_ECC_X2_17 + * | | |For P-192, POINTX2 is stored in CRYPTO_ECC_X2_00~CRYPTO_ECC_X2_05 + * | | |For P-224, POINTX2 is stored in CRYPTO_ECC_X2_00~CRYPTO_ECC_X2_06 + * | | |For P-256 or SM2, POINTX2 is stored in CRYPTO_ECC_X2_00~CRYPTO_ECC_X2_07 + * | | |For P-384, POINTX2 is stored in CRYPTO_ECC_X2_00~CRYPTO_ECC_X2_11 + * | | |For P-521, POINTX2 is stored in CRYPTO_ECC_X2_00~CRYPTO_ECC_X2_16 + * @var CRYPTO_T::ECC_X2_05 + * Offset: 0x8AC ECC the X-coordinate Word5 of the Second Point + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[31:0] |POINTX2 |ECC the X-coordinate Value of the Second Point + * | | |For B-163 or K-163, POINTX2 is stored in CRYPTO_ECC_X2_00~CRYPTO_ECC_X2_05 + * | | |For B-233 or K-233, POINTX2 is stored in CRYPTO_ECC_X2_00~CRYPTO_ECC_X2_07 + * | | |For B-283 or K-283, POINTX2 is stored in CRYPTO_ECC_X2_00~CRYPTO_ECC_X2_08 + * | | |For B-409 or K-409, POINTX2 is stored in CRYPTO_ECC_X2_00~CRYPTO_ECC_X2_12 + * | | |For B-571 or K-571, POINTX2 is stored in CRYPTO_ECC_X2_00~CRYPTO_ECC_X2_17 + * | | |For P-192, POINTX2 is stored in CRYPTO_ECC_X2_00~CRYPTO_ECC_X2_05 + * | | |For P-224, POINTX2 is stored in CRYPTO_ECC_X2_00~CRYPTO_ECC_X2_06 + * | | |For P-256 or SM2, POINTX2 is stored in CRYPTO_ECC_X2_00~CRYPTO_ECC_X2_07 + * | | |For P-384, POINTX2 is stored in CRYPTO_ECC_X2_00~CRYPTO_ECC_X2_11 + * | | |For P-521, POINTX2 is stored in CRYPTO_ECC_X2_00~CRYPTO_ECC_X2_16 + * @var CRYPTO_T::ECC_X2_06 + * Offset: 0x8B0 ECC the X-coordinate Word6 of the Second Point + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[31:0] |POINTX2 |ECC the X-coordinate Value of the Second Point + * | | |For B-163 or K-163, POINTX2 is stored in CRYPTO_ECC_X2_00~CRYPTO_ECC_X2_05 + * | | |For B-233 or K-233, POINTX2 is stored in CRYPTO_ECC_X2_00~CRYPTO_ECC_X2_07 + * | | |For B-283 or K-283, POINTX2 is stored in CRYPTO_ECC_X2_00~CRYPTO_ECC_X2_08 + * | | |For B-409 or K-409, POINTX2 is stored in CRYPTO_ECC_X2_00~CRYPTO_ECC_X2_12 + * | | |For B-571 or K-571, POINTX2 is stored in CRYPTO_ECC_X2_00~CRYPTO_ECC_X2_17 + * | | |For P-192, POINTX2 is stored in CRYPTO_ECC_X2_00~CRYPTO_ECC_X2_05 + * | | |For P-224, POINTX2 is stored in CRYPTO_ECC_X2_00~CRYPTO_ECC_X2_06 + * | | |For P-256 or SM2, POINTX2 is stored in CRYPTO_ECC_X2_00~CRYPTO_ECC_X2_07 + * | | |For P-384, POINTX2 is stored in CRYPTO_ECC_X2_00~CRYPTO_ECC_X2_11 + * | | |For P-521, POINTX2 is stored in CRYPTO_ECC_X2_00~CRYPTO_ECC_X2_16 + * @var CRYPTO_T::ECC_X2_07 + * Offset: 0x8B4 ECC the X-coordinate Word7 of the Second Point + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[31:0] |POINTX2 |ECC the X-coordinate Value of the Second Point + * | | |For B-163 or K-163, POINTX2 is stored in CRYPTO_ECC_X2_00~CRYPTO_ECC_X2_05 + * | | |For B-233 or K-233, POINTX2 is stored in CRYPTO_ECC_X2_00~CRYPTO_ECC_X2_07 + * | | |For B-283 or K-283, POINTX2 is stored in CRYPTO_ECC_X2_00~CRYPTO_ECC_X2_08 + * | | |For B-409 or K-409, POINTX2 is stored in CRYPTO_ECC_X2_00~CRYPTO_ECC_X2_12 + * | | |For B-571 or K-571, POINTX2 is stored in CRYPTO_ECC_X2_00~CRYPTO_ECC_X2_17 + * | | |For P-192, POINTX2 is stored in CRYPTO_ECC_X2_00~CRYPTO_ECC_X2_05 + * | | |For P-224, POINTX2 is stored in CRYPTO_ECC_X2_00~CRYPTO_ECC_X2_06 + * | | |For P-256 or SM2, POINTX2 is stored in CRYPTO_ECC_X2_00~CRYPTO_ECC_X2_07 + * | | |For P-384, POINTX2 is stored in CRYPTO_ECC_X2_00~CRYPTO_ECC_X2_11 + * | | |For P-521, POINTX2 is stored in CRYPTO_ECC_X2_00~CRYPTO_ECC_X2_16 + * @var CRYPTO_T::ECC_X2_08 + * Offset: 0x8B8 ECC the X-coordinate Word8 of the Second Point + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[31:0] |POINTX2 |ECC the X-coordinate Value of the Second Point + * | | |For B-163 or K-163, POINTX2 is stored in CRYPTO_ECC_X2_00~CRYPTO_ECC_X2_05 + * | | |For B-233 or K-233, POINTX2 is stored in CRYPTO_ECC_X2_00~CRYPTO_ECC_X2_07 + * | | |For B-283 or K-283, POINTX2 is stored in CRYPTO_ECC_X2_00~CRYPTO_ECC_X2_08 + * | | |For B-409 or K-409, POINTX2 is stored in CRYPTO_ECC_X2_00~CRYPTO_ECC_X2_12 + * | | |For B-571 or K-571, POINTX2 is stored in CRYPTO_ECC_X2_00~CRYPTO_ECC_X2_17 + * | | |For P-192, POINTX2 is stored in CRYPTO_ECC_X2_00~CRYPTO_ECC_X2_05 + * | | |For P-224, POINTX2 is stored in CRYPTO_ECC_X2_00~CRYPTO_ECC_X2_06 + * | | |For P-256 or SM2, POINTX2 is stored in CRYPTO_ECC_X2_00~CRYPTO_ECC_X2_07 + * | | |For P-384, POINTX2 is stored in CRYPTO_ECC_X2_00~CRYPTO_ECC_X2_11 + * | | |For P-521, POINTX2 is stored in CRYPTO_ECC_X2_00~CRYPTO_ECC_X2_16 + * @var CRYPTO_T::ECC_X2_09 + * Offset: 0x8BC ECC the X-coordinate Word9 of the Second Point + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[31:0] |POINTX2 |ECC the X-coordinate Value of the Second Point + * | | |For B-163 or K-163, POINTX2 is stored in CRYPTO_ECC_X2_00~CRYPTO_ECC_X2_05 + * | | |For B-233 or K-233, POINTX2 is stored in CRYPTO_ECC_X2_00~CRYPTO_ECC_X2_07 + * | | |For B-283 or K-283, POINTX2 is stored in CRYPTO_ECC_X2_00~CRYPTO_ECC_X2_08 + * | | |For B-409 or K-409, POINTX2 is stored in CRYPTO_ECC_X2_00~CRYPTO_ECC_X2_12 + * | | |For B-571 or K-571, POINTX2 is stored in CRYPTO_ECC_X2_00~CRYPTO_ECC_X2_17 + * | | |For P-192, POINTX2 is stored in CRYPTO_ECC_X2_00~CRYPTO_ECC_X2_05 + * | | |For P-224, POINTX2 is stored in CRYPTO_ECC_X2_00~CRYPTO_ECC_X2_06 + * | | |For P-256 or SM2, POINTX2 is stored in CRYPTO_ECC_X2_00~CRYPTO_ECC_X2_07 + * | | |For P-384, POINTX2 is stored in CRYPTO_ECC_X2_00~CRYPTO_ECC_X2_11 + * | | |For P-521, POINTX2 is stored in CRYPTO_ECC_X2_00~CRYPTO_ECC_X2_16 + * @var CRYPTO_T::ECC_X2_10 + * Offset: 0x8C0 ECC the X-coordinate Word10 of the Second Point + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[31:0] |POINTX2 |ECC the X-coordinate Value of the Second Point + * | | |For B-163 or K-163, POINTX2 is stored in CRYPTO_ECC_X2_00~CRYPTO_ECC_X2_05 + * | | |For B-233 or K-233, POINTX2 is stored in CRYPTO_ECC_X2_00~CRYPTO_ECC_X2_07 + * | | |For B-283 or K-283, POINTX2 is stored in CRYPTO_ECC_X2_00~CRYPTO_ECC_X2_08 + * | | |For B-409 or K-409, POINTX2 is stored in CRYPTO_ECC_X2_00~CRYPTO_ECC_X2_12 + * | | |For B-571 or K-571, POINTX2 is stored in CRYPTO_ECC_X2_00~CRYPTO_ECC_X2_17 + * | | |For P-192, POINTX2 is stored in CRYPTO_ECC_X2_00~CRYPTO_ECC_X2_05 + * | | |For P-224, POINTX2 is stored in CRYPTO_ECC_X2_00~CRYPTO_ECC_X2_06 + * | | |For P-256 or SM2, POINTX2 is stored in CRYPTO_ECC_X2_00~CRYPTO_ECC_X2_07 + * | | |For P-384, POINTX2 is stored in CRYPTO_ECC_X2_00~CRYPTO_ECC_X2_11 + * | | |For P-521, POINTX2 is stored in CRYPTO_ECC_X2_00~CRYPTO_ECC_X2_16 + * @var CRYPTO_T::ECC_X2_11 + * Offset: 0x8C4 ECC the X-coordinate Word11 of the Second Point + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[31:0] |POINTX2 |ECC the X-coordinate Value of the Second Point + * | | |For B-163 or K-163, POINTX2 is stored in CRYPTO_ECC_X2_00~CRYPTO_ECC_X2_05 + * | | |For B-233 or K-233, POINTX2 is stored in CRYPTO_ECC_X2_00~CRYPTO_ECC_X2_07 + * | | |For B-283 or K-283, POINTX2 is stored in CRYPTO_ECC_X2_00~CRYPTO_ECC_X2_08 + * | | |For B-409 or K-409, POINTX2 is stored in CRYPTO_ECC_X2_00~CRYPTO_ECC_X2_12 + * | | |For B-571 or K-571, POINTX2 is stored in CRYPTO_ECC_X2_00~CRYPTO_ECC_X2_17 + * | | |For P-192, POINTX2 is stored in CRYPTO_ECC_X2_00~CRYPTO_ECC_X2_05 + * | | |For P-224, POINTX2 is stored in CRYPTO_ECC_X2_00~CRYPTO_ECC_X2_06 + * | | |For P-256 or SM2, POINTX2 is stored in CRYPTO_ECC_X2_00~CRYPTO_ECC_X2_07 + * | | |For P-384, POINTX2 is stored in CRYPTO_ECC_X2_00~CRYPTO_ECC_X2_11 + * | | |For P-521, POINTX2 is stored in CRYPTO_ECC_X2_00~CRYPTO_ECC_X2_16 + * @var CRYPTO_T::ECC_X2_12 + * Offset: 0x8C8 ECC the X-coordinate Word12 of the Second Point + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[31:0] |POINTX2 |ECC the X-coordinate Value of the Second Point + * | | |For B-163 or K-163, POINTX2 is stored in CRYPTO_ECC_X2_00~CRYPTO_ECC_X2_05 + * | | |For B-233 or K-233, POINTX2 is stored in CRYPTO_ECC_X2_00~CRYPTO_ECC_X2_07 + * | | |For B-283 or K-283, POINTX2 is stored in CRYPTO_ECC_X2_00~CRYPTO_ECC_X2_08 + * | | |For B-409 or K-409, POINTX2 is stored in CRYPTO_ECC_X2_00~CRYPTO_ECC_X2_12 + * | | |For B-571 or K-571, POINTX2 is stored in CRYPTO_ECC_X2_00~CRYPTO_ECC_X2_17 + * | | |For P-192, POINTX2 is stored in CRYPTO_ECC_X2_00~CRYPTO_ECC_X2_05 + * | | |For P-224, POINTX2 is stored in CRYPTO_ECC_X2_00~CRYPTO_ECC_X2_06 + * | | |For P-256 or SM2, POINTX2 is stored in CRYPTO_ECC_X2_00~CRYPTO_ECC_X2_07 + * | | |For P-384, POINTX2 is stored in CRYPTO_ECC_X2_00~CRYPTO_ECC_X2_11 + * | | |For P-521, POINTX2 is stored in CRYPTO_ECC_X2_00~CRYPTO_ECC_X2_16 + * @var CRYPTO_T::ECC_X2_13 + * Offset: 0x8CC ECC the X-coordinate Word13 of the Second Point + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[31:0] |POINTX2 |ECC the X-coordinate Value of the Second Point + * | | |For B-163 or K-163, POINTX2 is stored in CRYPTO_ECC_X2_00~CRYPTO_ECC_X2_05 + * | | |For B-233 or K-233, POINTX2 is stored in CRYPTO_ECC_X2_00~CRYPTO_ECC_X2_07 + * | | |For B-283 or K-283, POINTX2 is stored in CRYPTO_ECC_X2_00~CRYPTO_ECC_X2_08 + * | | |For B-409 or K-409, POINTX2 is stored in CRYPTO_ECC_X2_00~CRYPTO_ECC_X2_12 + * | | |For B-571 or K-571, POINTX2 is stored in CRYPTO_ECC_X2_00~CRYPTO_ECC_X2_17 + * | | |For P-192, POINTX2 is stored in CRYPTO_ECC_X2_00~CRYPTO_ECC_X2_05 + * | | |For P-224, POINTX2 is stored in CRYPTO_ECC_X2_00~CRYPTO_ECC_X2_06 + * | | |For P-256 or SM2, POINTX2 is stored in CRYPTO_ECC_X2_00~CRYPTO_ECC_X2_07 + * | | |For P-384, POINTX2 is stored in CRYPTO_ECC_X2_00~CRYPTO_ECC_X2_11 + * | | |For P-521, POINTX2 is stored in CRYPTO_ECC_X2_00~CRYPTO_ECC_X2_16 + * @var CRYPTO_T::ECC_X2_14 + * Offset: 0x8D0 ECC the X-coordinate Word14 of the Second Point + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[31:0] |POINTX2 |ECC the X-coordinate Value of the Second Point + * | | |For B-163 or K-163, POINTX2 is stored in CRYPTO_ECC_X2_00~CRYPTO_ECC_X2_05 + * | | |For B-233 or K-233, POINTX2 is stored in CRYPTO_ECC_X2_00~CRYPTO_ECC_X2_07 + * | | |For B-283 or K-283, POINTX2 is stored in CRYPTO_ECC_X2_00~CRYPTO_ECC_X2_08 + * | | |For B-409 or K-409, POINTX2 is stored in CRYPTO_ECC_X2_00~CRYPTO_ECC_X2_12 + * | | |For B-571 or K-571, POINTX2 is stored in CRYPTO_ECC_X2_00~CRYPTO_ECC_X2_17 + * | | |For P-192, POINTX2 is stored in CRYPTO_ECC_X2_00~CRYPTO_ECC_X2_05 + * | | |For P-224, POINTX2 is stored in CRYPTO_ECC_X2_00~CRYPTO_ECC_X2_06 + * | | |For P-256 or SM2, POINTX2 is stored in CRYPTO_ECC_X2_00~CRYPTO_ECC_X2_07 + * | | |For P-384, POINTX2 is stored in CRYPTO_ECC_X2_00~CRYPTO_ECC_X2_11 + * | | |For P-521, POINTX2 is stored in CRYPTO_ECC_X2_00~CRYPTO_ECC_X2_16 + * @var CRYPTO_T::ECC_X2_15 + * Offset: 0x8D4 ECC the X-coordinate Word15 of the Second Point + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[31:0] |POINTX2 |ECC the X-coordinate Value of the Second Point + * | | |For B-163 or K-163, POINTX2 is stored in CRYPTO_ECC_X2_00~CRYPTO_ECC_X2_05 + * | | |For B-233 or K-233, POINTX2 is stored in CRYPTO_ECC_X2_00~CRYPTO_ECC_X2_07 + * | | |For B-283 or K-283, POINTX2 is stored in CRYPTO_ECC_X2_00~CRYPTO_ECC_X2_08 + * | | |For B-409 or K-409, POINTX2 is stored in CRYPTO_ECC_X2_00~CRYPTO_ECC_X2_12 + * | | |For B-571 or K-571, POINTX2 is stored in CRYPTO_ECC_X2_00~CRYPTO_ECC_X2_17 + * | | |For P-192, POINTX2 is stored in CRYPTO_ECC_X2_00~CRYPTO_ECC_X2_05 + * | | |For P-224, POINTX2 is stored in CRYPTO_ECC_X2_00~CRYPTO_ECC_X2_06 + * | | |For P-256 or SM2, POINTX2 is stored in CRYPTO_ECC_X2_00~CRYPTO_ECC_X2_07 + * | | |For P-384, POINTX2 is stored in CRYPTO_ECC_X2_00~CRYPTO_ECC_X2_11 + * | | |For P-521, POINTX2 is stored in CRYPTO_ECC_X2_00~CRYPTO_ECC_X2_16 + * @var CRYPTO_T::ECC_X2_16 + * Offset: 0x8D8 ECC the X-coordinate Word16 of the Second Point + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[31:0] |POINTX2 |ECC the X-coordinate Value of the Second Point + * | | |For B-163 or K-163, POINTX2 is stored in CRYPTO_ECC_X2_00~CRYPTO_ECC_X2_05 + * | | |For B-233 or K-233, POINTX2 is stored in CRYPTO_ECC_X2_00~CRYPTO_ECC_X2_07 + * | | |For B-283 or K-283, POINTX2 is stored in CRYPTO_ECC_X2_00~CRYPTO_ECC_X2_08 + * | | |For B-409 or K-409, POINTX2 is stored in CRYPTO_ECC_X2_00~CRYPTO_ECC_X2_12 + * | | |For B-571 or K-571, POINTX2 is stored in CRYPTO_ECC_X2_00~CRYPTO_ECC_X2_17 + * | | |For P-192, POINTX2 is stored in CRYPTO_ECC_X2_00~CRYPTO_ECC_X2_05 + * | | |For P-224, POINTX2 is stored in CRYPTO_ECC_X2_00~CRYPTO_ECC_X2_06 + * | | |For P-256 or SM2, POINTX2 is stored in CRYPTO_ECC_X2_00~CRYPTO_ECC_X2_07 + * | | |For P-384, POINTX2 is stored in CRYPTO_ECC_X2_00~CRYPTO_ECC_X2_11 + * | | |For P-521, POINTX2 is stored in CRYPTO_ECC_X2_00~CRYPTO_ECC_X2_16 + * @var CRYPTO_T::ECC_X2_17 + * Offset: 0x8DC ECC the X-coordinate Word17 of the Second Point + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[31:0] |POINTX2 |ECC the X-coordinate Value of the Second Point + * | | |For B-163 or K-163, POINTX2 is stored in CRYPTO_ECC_X2_00~CRYPTO_ECC_X2_05 + * | | |For B-233 or K-233, POINTX2 is stored in CRYPTO_ECC_X2_00~CRYPTO_ECC_X2_07 + * | | |For B-283 or K-283, POINTX2 is stored in CRYPTO_ECC_X2_00~CRYPTO_ECC_X2_08 + * | | |For B-409 or K-409, POINTX2 is stored in CRYPTO_ECC_X2_00~CRYPTO_ECC_X2_12 + * | | |For B-571 or K-571, POINTX2 is stored in CRYPTO_ECC_X2_00~CRYPTO_ECC_X2_17 + * | | |For P-192, POINTX2 is stored in CRYPTO_ECC_X2_00~CRYPTO_ECC_X2_05 + * | | |For P-224, POINTX2 is stored in CRYPTO_ECC_X2_00~CRYPTO_ECC_X2_06 + * | | |For P-256 or SM2, POINTX2 is stored in CRYPTO_ECC_X2_00~CRYPTO_ECC_X2_07 + * | | |For P-384, POINTX2 is stored in CRYPTO_ECC_X2_00~CRYPTO_ECC_X2_11 + * | | |For P-521, POINTX2 is stored in CRYPTO_ECC_X2_00~CRYPTO_ECC_X2_16 + * @var CRYPTO_T::ECC_Y2_00 + * Offset: 0x8E0 ECC the Y-coordinate Word0 of the Second Point + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[31:0] |POINTY2 |ECC the Y-coordinate Value of the Second Point + * | | |For B-163 or K-163, POINTY2 is stored in CRYPTO_ECC_Y2_00~CRYPTO_ECC_Y2_05 + * | | |For B-233 or K-233, POINTY2 is stored in CRYPTO_ECC_Y2_00~CRYPTO_ECC_Y2_07 + * | | |For B-283 or K-283, POINTY2 is stored in CRYPTO_ECC_Y2_00~CRYPTO_ECC_Y2_08 + * | | |For B-409 or K-409, POINTY2 is stored in CRYPTO_ECC_Y2_00~CRYPTO_ECC_Y2_12 + * | | |For B-571 or K-571, POINTY2 is stored in CRYPTO_ECC_Y2_00~CRYPTO_ECC_Y2_17 + * | | |For P-192, POINTY2 is stored in CRYPTO_ECC_Y2_00~CRYPTO_ECC_Y2_05 + * | | |For P-224, POINTY2 is stored in CRYPTO_ECC_Y2_00~CRYPTO_ECC_Y2_06 + * | | |For P-256 or SM2, POINTY2 is stored in CRYPTO_ECC_Y2_00~CRYPTO_ECC_Y2_07 + * | | |For P-384, POINTY2 is stored in CRYPTO_ECC_Y2_00~CRYPTO_ECC_Y2_11 + * | | |For P-521, POINTY2 is stored in CRYPTO_ECC_Y2_00~CRYPTO_ECC_Y2_16 + * @var CRYPTO_T::ECC_Y2_01 + * Offset: 0x8E4 ECC the Y-coordinate Word1 of the Second Point + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[31:0] |POINTY2 |ECC the Y-coordinate Value of the Second Point + * | | |For B-163 or K-163, POINTY2 is stored in CRYPTO_ECC_Y2_00~CRYPTO_ECC_Y2_05 + * | | |For B-233 or K-233, POINTY2 is stored in CRYPTO_ECC_Y2_00~CRYPTO_ECC_Y2_07 + * | | |For B-283 or K-283, POINTY2 is stored in CRYPTO_ECC_Y2_00~CRYPTO_ECC_Y2_08 + * | | |For B-409 or K-409, POINTY2 is stored in CRYPTO_ECC_Y2_00~CRYPTO_ECC_Y2_12 + * | | |For B-571 or K-571, POINTY2 is stored in CRYPTO_ECC_Y2_00~CRYPTO_ECC_Y2_17 + * | | |For P-192, POINTY2 is stored in CRYPTO_ECC_Y2_00~CRYPTO_ECC_Y2_05 + * | | |For P-224, POINTY2 is stored in CRYPTO_ECC_Y2_00~CRYPTO_ECC_Y2_06 + * | | |For P-256 or SM2, POINTY2 is stored in CRYPTO_ECC_Y2_00~CRYPTO_ECC_Y2_07 + * | | |For P-384, POINTY2 is stored in CRYPTO_ECC_Y2_00~CRYPTO_ECC_Y2_11 + * | | |For P-521, POINTY2 is stored in CRYPTO_ECC_Y2_00~CRYPTO_ECC_Y2_16 + * @var CRYPTO_T::ECC_Y2_02 + * Offset: 0x8E8 ECC the Y-coordinate Word2 of the Second Point + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[31:0] |POINTY2 |ECC the Y-coordinate Value of the Second Point + * | | |For B-163 or K-163, POINTY2 is stored in CRYPTO_ECC_Y2_00~CRYPTO_ECC_Y2_05 + * | | |For B-233 or K-233, POINTY2 is stored in CRYPTO_ECC_Y2_00~CRYPTO_ECC_Y2_07 + * | | |For B-283 or K-283, POINTY2 is stored in CRYPTO_ECC_Y2_00~CRYPTO_ECC_Y2_08 + * | | |For B-409 or K-409, POINTY2 is stored in CRYPTO_ECC_Y2_00~CRYPTO_ECC_Y2_12 + * | | |For B-571 or K-571, POINTY2 is stored in CRYPTO_ECC_Y2_00~CRYPTO_ECC_Y2_17 + * | | |For P-192, POINTY2 is stored in CRYPTO_ECC_Y2_00~CRYPTO_ECC_Y2_05 + * | | |For P-224, POINTY2 is stored in CRYPTO_ECC_Y2_00~CRYPTO_ECC_Y2_06 + * | | |For P-256 or SM2, POINTY2 is stored in CRYPTO_ECC_Y2_00~CRYPTO_ECC_Y2_07 + * | | |For P-384, POINTY2 is stored in CRYPTO_ECC_Y2_00~CRYPTO_ECC_Y2_11 + * | | |For P-521, POINTY2 is stored in CRYPTO_ECC_Y2_00~CRYPTO_ECC_Y2_16 + * @var CRYPTO_T::ECC_Y2_03 + * Offset: 0x8EC ECC the Y-coordinate Word3 of the Second Point + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[31:0] |POINTY2 |ECC the Y-coordinate Value of the Second Point + * | | |For B-163 or K-163, POINTY2 is stored in CRYPTO_ECC_Y2_00~CRYPTO_ECC_Y2_05 + * | | |For B-233 or K-233, POINTY2 is stored in CRYPTO_ECC_Y2_00~CRYPTO_ECC_Y2_07 + * | | |For B-283 or K-283, POINTY2 is stored in CRYPTO_ECC_Y2_00~CRYPTO_ECC_Y2_08 + * | | |For B-409 or K-409, POINTY2 is stored in CRYPTO_ECC_Y2_00~CRYPTO_ECC_Y2_12 + * | | |For B-571 or K-571, POINTY2 is stored in CRYPTO_ECC_Y2_00~CRYPTO_ECC_Y2_17 + * | | |For P-192, POINTY2 is stored in CRYPTO_ECC_Y2_00~CRYPTO_ECC_Y2_05 + * | | |For P-224, POINTY2 is stored in CRYPTO_ECC_Y2_00~CRYPTO_ECC_Y2_06 + * | | |For P-256 or SM2, POINTY2 is stored in CRYPTO_ECC_Y2_00~CRYPTO_ECC_Y2_07 + * | | |For P-384, POINTY2 is stored in CRYPTO_ECC_Y2_00~CRYPTO_ECC_Y2_11 + * | | |For P-521, POINTY2 is stored in CRYPTO_ECC_Y2_00~CRYPTO_ECC_Y2_16 + * @var CRYPTO_T::ECC_Y2_04 + * Offset: 0x8F0 ECC the Y-coordinate Word4 of the Second Point + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[31:0] |POINTY2 |ECC the Y-coordinate Value of the Second Point + * | | |For B-163 or K-163, POINTY2 is stored in CRYPTO_ECC_Y2_00~CRYPTO_ECC_Y2_05 + * | | |For B-233 or K-233, POINTY2 is stored in CRYPTO_ECC_Y2_00~CRYPTO_ECC_Y2_07 + * | | |For B-283 or K-283, POINTY2 is stored in CRYPTO_ECC_Y2_00~CRYPTO_ECC_Y2_08 + * | | |For B-409 or K-409, POINTY2 is stored in CRYPTO_ECC_Y2_00~CRYPTO_ECC_Y2_12 + * | | |For B-571 or K-571, POINTY2 is stored in CRYPTO_ECC_Y2_00~CRYPTO_ECC_Y2_17 + * | | |For P-192, POINTY2 is stored in CRYPTO_ECC_Y2_00~CRYPTO_ECC_Y2_05 + * | | |For P-224, POINTY2 is stored in CRYPTO_ECC_Y2_00~CRYPTO_ECC_Y2_06 + * | | |For P-256 or SM2, POINTY2 is stored in CRYPTO_ECC_Y2_00~CRYPTO_ECC_Y2_07 + * | | |For P-384, POINTY2 is stored in CRYPTO_ECC_Y2_00~CRYPTO_ECC_Y2_11 + * | | |For P-521, POINTY2 is stored in CRYPTO_ECC_Y2_00~CRYPTO_ECC_Y2_16 + * @var CRYPTO_T::ECC_Y2_05 + * Offset: 0x8F4 ECC the Y-coordinate Word5 of the Second Point + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[31:0] |POINTY2 |ECC the Y-coordinate Value of the Second Point + * | | |For B-163 or K-163, POINTY2 is stored in CRYPTO_ECC_Y2_00~CRYPTO_ECC_Y2_05 + * | | |For B-233 or K-233, POINTY2 is stored in CRYPTO_ECC_Y2_00~CRYPTO_ECC_Y2_07 + * | | |For B-283 or K-283, POINTY2 is stored in CRYPTO_ECC_Y2_00~CRYPTO_ECC_Y2_08 + * | | |For B-409 or K-409, POINTY2 is stored in CRYPTO_ECC_Y2_00~CRYPTO_ECC_Y2_12 + * | | |For B-571 or K-571, POINTY2 is stored in CRYPTO_ECC_Y2_00~CRYPTO_ECC_Y2_17 + * | | |For P-192, POINTY2 is stored in CRYPTO_ECC_Y2_00~CRYPTO_ECC_Y2_05 + * | | |For P-224, POINTY2 is stored in CRYPTO_ECC_Y2_00~CRYPTO_ECC_Y2_06 + * | | |For P-256 or SM2, POINTY2 is stored in CRYPTO_ECC_Y2_00~CRYPTO_ECC_Y2_07 + * | | |For P-384, POINTY2 is stored in CRYPTO_ECC_Y2_00~CRYPTO_ECC_Y2_11 + * | | |For P-521, POINTY2 is stored in CRYPTO_ECC_Y2_00~CRYPTO_ECC_Y2_16 + * @var CRYPTO_T::ECC_Y2_06 + * Offset: 0x8F8 ECC the Y-coordinate Word6 of the Second Point + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[31:0] |POINTY2 |ECC the Y-coordinate Value of the Second Point + * | | |For B-163 or K-163, POINTY2 is stored in CRYPTO_ECC_Y2_00~CRYPTO_ECC_Y2_05 + * | | |For B-233 or K-233, POINTY2 is stored in CRYPTO_ECC_Y2_00~CRYPTO_ECC_Y2_07 + * | | |For B-283 or K-283, POINTY2 is stored in CRYPTO_ECC_Y2_00~CRYPTO_ECC_Y2_08 + * | | |For B-409 or K-409, POINTY2 is stored in CRYPTO_ECC_Y2_00~CRYPTO_ECC_Y2_12 + * | | |For B-571 or K-571, POINTY2 is stored in CRYPTO_ECC_Y2_00~CRYPTO_ECC_Y2_17 + * | | |For P-192, POINTY2 is stored in CRYPTO_ECC_Y2_00~CRYPTO_ECC_Y2_05 + * | | |For P-224, POINTY2 is stored in CRYPTO_ECC_Y2_00~CRYPTO_ECC_Y2_06 + * | | |For P-256 or SM2, POINTY2 is stored in CRYPTO_ECC_Y2_00~CRYPTO_ECC_Y2_07 + * | | |For P-384, POINTY2 is stored in CRYPTO_ECC_Y2_00~CRYPTO_ECC_Y2_11 + * | | |For P-521, POINTY2 is stored in CRYPTO_ECC_Y2_00~CRYPTO_ECC_Y2_16 + * @var CRYPTO_T::ECC_Y2_07 + * Offset: 0x8FC ECC the Y-coordinate Word7 of the Second Point + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[31:0] |POINTY2 |ECC the Y-coordinate Value of the Second Point + * | | |For B-163 or K-163, POINTY2 is stored in CRYPTO_ECC_Y2_00~CRYPTO_ECC_Y2_05 + * | | |For B-233 or K-233, POINTY2 is stored in CRYPTO_ECC_Y2_00~CRYPTO_ECC_Y2_07 + * | | |For B-283 or K-283, POINTY2 is stored in CRYPTO_ECC_Y2_00~CRYPTO_ECC_Y2_08 + * | | |For B-409 or K-409, POINTY2 is stored in CRYPTO_ECC_Y2_00~CRYPTO_ECC_Y2_12 + * | | |For B-571 or K-571, POINTY2 is stored in CRYPTO_ECC_Y2_00~CRYPTO_ECC_Y2_17 + * | | |For P-192, POINTY2 is stored in CRYPTO_ECC_Y2_00~CRYPTO_ECC_Y2_05 + * | | |For P-224, POINTY2 is stored in CRYPTO_ECC_Y2_00~CRYPTO_ECC_Y2_06 + * | | |For P-256 or SM2, POINTY2 is stored in CRYPTO_ECC_Y2_00~CRYPTO_ECC_Y2_07 + * | | |For P-384, POINTY2 is stored in CRYPTO_ECC_Y2_00~CRYPTO_ECC_Y2_11 + * | | |For P-521, POINTY2 is stored in CRYPTO_ECC_Y2_00~CRYPTO_ECC_Y2_16 + * @var CRYPTO_T::ECC_Y2_08 + * Offset: 0x900 ECC the Y-coordinate Word8 of the Second Point + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[31:0] |POINTY2 |ECC the Y-coordinate Value of the Second Point + * | | |For B-163 or K-163, POINTY2 is stored in CRYPTO_ECC_Y2_00~CRYPTO_ECC_Y2_05 + * | | |For B-233 or K-233, POINTY2 is stored in CRYPTO_ECC_Y2_00~CRYPTO_ECC_Y2_07 + * | | |For B-283 or K-283, POINTY2 is stored in CRYPTO_ECC_Y2_00~CRYPTO_ECC_Y2_08 + * | | |For B-409 or K-409, POINTY2 is stored in CRYPTO_ECC_Y2_00~CRYPTO_ECC_Y2_12 + * | | |For B-571 or K-571, POINTY2 is stored in CRYPTO_ECC_Y2_00~CRYPTO_ECC_Y2_17 + * | | |For P-192, POINTY2 is stored in CRYPTO_ECC_Y2_00~CRYPTO_ECC_Y2_05 + * | | |For P-224, POINTY2 is stored in CRYPTO_ECC_Y2_00~CRYPTO_ECC_Y2_06 + * | | |For P-256 or SM2, POINTY2 is stored in CRYPTO_ECC_Y2_00~CRYPTO_ECC_Y2_07 + * | | |For P-384, POINTY2 is stored in CRYPTO_ECC_Y2_00~CRYPTO_ECC_Y2_11 + * | | |For P-521, POINTY2 is stored in CRYPTO_ECC_Y2_00~CRYPTO_ECC_Y2_16 + * @var CRYPTO_T::ECC_Y2_09 + * Offset: 0x904 ECC the Y-coordinate Word9 of the Second Point + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[31:0] |POINTY2 |ECC the Y-coordinate Value of the Second Point + * | | |For B-163 or K-163, POINTY2 is stored in CRYPTO_ECC_Y2_00~CRYPTO_ECC_Y2_05 + * | | |For B-233 or K-233, POINTY2 is stored in CRYPTO_ECC_Y2_00~CRYPTO_ECC_Y2_07 + * | | |For B-283 or K-283, POINTY2 is stored in CRYPTO_ECC_Y2_00~CRYPTO_ECC_Y2_08 + * | | |For B-409 or K-409, POINTY2 is stored in CRYPTO_ECC_Y2_00~CRYPTO_ECC_Y2_12 + * | | |For B-571 or K-571, POINTY2 is stored in CRYPTO_ECC_Y2_00~CRYPTO_ECC_Y2_17 + * | | |For P-192, POINTY2 is stored in CRYPTO_ECC_Y2_00~CRYPTO_ECC_Y2_05 + * | | |For P-224, POINTY2 is stored in CRYPTO_ECC_Y2_00~CRYPTO_ECC_Y2_06 + * | | |For P-256 or SM2, POINTY2 is stored in CRYPTO_ECC_Y2_00~CRYPTO_ECC_Y2_07 + * | | |For P-384, POINTY2 is stored in CRYPTO_ECC_Y2_00~CRYPTO_ECC_Y2_11 + * | | |For P-521, POINTY2 is stored in CRYPTO_ECC_Y2_00~CRYPTO_ECC_Y2_16 + * @var CRYPTO_T::ECC_Y2_10 + * Offset: 0x908 ECC the Y-coordinate Word10 of the Second Point + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[31:0] |POINTY2 |ECC the Y-coordinate Value of the Second Point + * | | |For B-163 or K-163, POINTY2 is stored in CRYPTO_ECC_Y2_00~CRYPTO_ECC_Y2_05 + * | | |For B-233 or K-233, POINTY2 is stored in CRYPTO_ECC_Y2_00~CRYPTO_ECC_Y2_07 + * | | |For B-283 or K-283, POINTY2 is stored in CRYPTO_ECC_Y2_00~CRYPTO_ECC_Y2_08 + * | | |For B-409 or K-409, POINTY2 is stored in CRYPTO_ECC_Y2_00~CRYPTO_ECC_Y2_12 + * | | |For B-571 or K-571, POINTY2 is stored in CRYPTO_ECC_Y2_00~CRYPTO_ECC_Y2_17 + * | | |For P-192, POINTY2 is stored in CRYPTO_ECC_Y2_00~CRYPTO_ECC_Y2_05 + * | | |For P-224, POINTY2 is stored in CRYPTO_ECC_Y2_00~CRYPTO_ECC_Y2_06 + * | | |For P-256 or SM2, POINTY2 is stored in CRYPTO_ECC_Y2_00~CRYPTO_ECC_Y2_07 + * | | |For P-384, POINTY2 is stored in CRYPTO_ECC_Y2_00~CRYPTO_ECC_Y2_11 + * | | |For P-521, POINTY2 is stored in CRYPTO_ECC_Y2_00~CRYPTO_ECC_Y2_16 + * @var CRYPTO_T::ECC_Y2_11 + * Offset: 0x90C ECC the Y-coordinate Word11 of the Second Point + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[31:0] |POINTY2 |ECC the Y-coordinate Value of the Second Point + * | | |For B-163 or K-163, POINTY2 is stored in CRYPTO_ECC_Y2_00~CRYPTO_ECC_Y2_05 + * | | |For B-233 or K-233, POINTY2 is stored in CRYPTO_ECC_Y2_00~CRYPTO_ECC_Y2_07 + * | | |For B-283 or K-283, POINTY2 is stored in CRYPTO_ECC_Y2_00~CRYPTO_ECC_Y2_08 + * | | |For B-409 or K-409, POINTY2 is stored in CRYPTO_ECC_Y2_00~CRYPTO_ECC_Y2_12 + * | | |For B-571 or K-571, POINTY2 is stored in CRYPTO_ECC_Y2_00~CRYPTO_ECC_Y2_17 + * | | |For P-192, POINTY2 is stored in CRYPTO_ECC_Y2_00~CRYPTO_ECC_Y2_05 + * | | |For P-224, POINTY2 is stored in CRYPTO_ECC_Y2_00~CRYPTO_ECC_Y2_06 + * | | |For P-256 or SM2, POINTY2 is stored in CRYPTO_ECC_Y2_00~CRYPTO_ECC_Y2_07 + * | | |For P-384, POINTY2 is stored in CRYPTO_ECC_Y2_00~CRYPTO_ECC_Y2_11 + * | | |For P-521, POINTY2 is stored in CRYPTO_ECC_Y2_00~CRYPTO_ECC_Y2_16 + * @var CRYPTO_T::ECC_Y2_12 + * Offset: 0x910 ECC the Y-coordinate Word12 of the Second Point + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[31:0] |POINTY2 |ECC the Y-coordinate Value of the Second Point + * | | |For B-163 or K-163, POINTY2 is stored in CRYPTO_ECC_Y2_00~CRYPTO_ECC_Y2_05 + * | | |For B-233 or K-233, POINTY2 is stored in CRYPTO_ECC_Y2_00~CRYPTO_ECC_Y2_07 + * | | |For B-283 or K-283, POINTY2 is stored in CRYPTO_ECC_Y2_00~CRYPTO_ECC_Y2_08 + * | | |For B-409 or K-409, POINTY2 is stored in CRYPTO_ECC_Y2_00~CRYPTO_ECC_Y2_12 + * | | |For B-571 or K-571, POINTY2 is stored in CRYPTO_ECC_Y2_00~CRYPTO_ECC_Y2_17 + * | | |For P-192, POINTY2 is stored in CRYPTO_ECC_Y2_00~CRYPTO_ECC_Y2_05 + * | | |For P-224, POINTY2 is stored in CRYPTO_ECC_Y2_00~CRYPTO_ECC_Y2_06 + * | | |For P-256 or SM2, POINTY2 is stored in CRYPTO_ECC_Y2_00~CRYPTO_ECC_Y2_07 + * | | |For P-384, POINTY2 is stored in CRYPTO_ECC_Y2_00~CRYPTO_ECC_Y2_11 + * | | |For P-521, POINTY2 is stored in CRYPTO_ECC_Y2_00~CRYPTO_ECC_Y2_16 + * @var CRYPTO_T::ECC_Y2_13 + * Offset: 0x914 ECC the Y-coordinate Word13 of the Second Point + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[31:0] |POINTY2 |ECC the Y-coordinate Value of the Second Point + * | | |For B-163 or K-163, POINTY2 is stored in CRYPTO_ECC_Y2_00~CRYPTO_ECC_Y2_05 + * | | |For B-233 or K-233, POINTY2 is stored in CRYPTO_ECC_Y2_00~CRYPTO_ECC_Y2_07 + * | | |For B-283 or K-283, POINTY2 is stored in CRYPTO_ECC_Y2_00~CRYPTO_ECC_Y2_08 + * | | |For B-409 or K-409, POINTY2 is stored in CRYPTO_ECC_Y2_00~CRYPTO_ECC_Y2_12 + * | | |For B-571 or K-571, POINTY2 is stored in CRYPTO_ECC_Y2_00~CRYPTO_ECC_Y2_17 + * | | |For P-192, POINTY2 is stored in CRYPTO_ECC_Y2_00~CRYPTO_ECC_Y2_05 + * | | |For P-224, POINTY2 is stored in CRYPTO_ECC_Y2_00~CRYPTO_ECC_Y2_06 + * | | |For P-256 or SM2, POINTY2 is stored in CRYPTO_ECC_Y2_00~CRYPTO_ECC_Y2_07 + * | | |For P-384, POINTY2 is stored in CRYPTO_ECC_Y2_00~CRYPTO_ECC_Y2_11 + * | | |For P-521, POINTY2 is stored in CRYPTO_ECC_Y2_00~CRYPTO_ECC_Y2_16 + * @var CRYPTO_T::ECC_Y2_14 + * Offset: 0x918 ECC the Y-coordinate Word14 of the Second Point + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[31:0] |POINTY2 |ECC the Y-coordinate Value of the Second Point + * | | |For B-163 or K-163, POINTY2 is stored in CRYPTO_ECC_Y2_00~CRYPTO_ECC_Y2_05 + * | | |For B-233 or K-233, POINTY2 is stored in CRYPTO_ECC_Y2_00~CRYPTO_ECC_Y2_07 + * | | |For B-283 or K-283, POINTY2 is stored in CRYPTO_ECC_Y2_00~CRYPTO_ECC_Y2_08 + * | | |For B-409 or K-409, POINTY2 is stored in CRYPTO_ECC_Y2_00~CRYPTO_ECC_Y2_12 + * | | |For B-571 or K-571, POINTY2 is stored in CRYPTO_ECC_Y2_00~CRYPTO_ECC_Y2_17 + * | | |For P-192, POINTY2 is stored in CRYPTO_ECC_Y2_00~CRYPTO_ECC_Y2_05 + * | | |For P-224, POINTY2 is stored in CRYPTO_ECC_Y2_00~CRYPTO_ECC_Y2_06 + * | | |For P-256 or SM2, POINTY2 is stored in CRYPTO_ECC_Y2_00~CRYPTO_ECC_Y2_07 + * | | |For P-384, POINTY2 is stored in CRYPTO_ECC_Y2_00~CRYPTO_ECC_Y2_11 + * | | |For P-521, POINTY2 is stored in CRYPTO_ECC_Y2_00~CRYPTO_ECC_Y2_16 + * @var CRYPTO_T::ECC_Y2_15 + * Offset: 0x91C ECC the Y-coordinate Word15 of the Second Point + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[31:0] |POINTY2 |ECC the Y-coordinate Value of the Second Point + * | | |For B-163 or K-163, POINTY2 is stored in CRYPTO_ECC_Y2_00~CRYPTO_ECC_Y2_05 + * | | |For B-233 or K-233, POINTY2 is stored in CRYPTO_ECC_Y2_00~CRYPTO_ECC_Y2_07 + * | | |For B-283 or K-283, POINTY2 is stored in CRYPTO_ECC_Y2_00~CRYPTO_ECC_Y2_08 + * | | |For B-409 or K-409, POINTY2 is stored in CRYPTO_ECC_Y2_00~CRYPTO_ECC_Y2_12 + * | | |For B-571 or K-571, POINTY2 is stored in CRYPTO_ECC_Y2_00~CRYPTO_ECC_Y2_17 + * | | |For P-192, POINTY2 is stored in CRYPTO_ECC_Y2_00~CRYPTO_ECC_Y2_05 + * | | |For P-224, POINTY2 is stored in CRYPTO_ECC_Y2_00~CRYPTO_ECC_Y2_06 + * | | |For P-256 or SM2, POINTY2 is stored in CRYPTO_ECC_Y2_00~CRYPTO_ECC_Y2_07 + * | | |For P-384, POINTY2 is stored in CRYPTO_ECC_Y2_00~CRYPTO_ECC_Y2_11 + * | | |For P-521, POINTY2 is stored in CRYPTO_ECC_Y2_00~CRYPTO_ECC_Y2_16 + * @var CRYPTO_T::ECC_Y2_16 + * Offset: 0x920 ECC the Y-coordinate Word16 of the Second Point + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[31:0] |POINTY2 |ECC the Y-coordinate Value of the Second Point + * | | |For B-163 or K-163, POINTY2 is stored in CRYPTO_ECC_Y2_00~CRYPTO_ECC_Y2_05 + * | | |For B-233 or K-233, POINTY2 is stored in CRYPTO_ECC_Y2_00~CRYPTO_ECC_Y2_07 + * | | |For B-283 or K-283, POINTY2 is stored in CRYPTO_ECC_Y2_00~CRYPTO_ECC_Y2_08 + * | | |For B-409 or K-409, POINTY2 is stored in CRYPTO_ECC_Y2_00~CRYPTO_ECC_Y2_12 + * | | |For B-571 or K-571, POINTY2 is stored in CRYPTO_ECC_Y2_00~CRYPTO_ECC_Y2_17 + * | | |For P-192, POINTY2 is stored in CRYPTO_ECC_Y2_00~CRYPTO_ECC_Y2_05 + * | | |For P-224, POINTY2 is stored in CRYPTO_ECC_Y2_00~CRYPTO_ECC_Y2_06 + * | | |For P-256 or SM2, POINTY2 is stored in CRYPTO_ECC_Y2_00~CRYPTO_ECC_Y2_07 + * | | |For P-384, POINTY2 is stored in CRYPTO_ECC_Y2_00~CRYPTO_ECC_Y2_11 + * | | |For P-521, POINTY2 is stored in CRYPTO_ECC_Y2_00~CRYPTO_ECC_Y2_16 + * @var CRYPTO_T::ECC_Y2_17 + * Offset: 0x924 ECC the Y-coordinate Word17 of the Second Point + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[31:0] |POINTY2 |ECC the Y-coordinate Value of the Second Point + * | | |For B-163 or K-163, POINTY2 is stored in CRYPTO_ECC_Y2_00~CRYPTO_ECC_Y2_05 + * | | |For B-233 or K-233, POINTY2 is stored in CRYPTO_ECC_Y2_00~CRYPTO_ECC_Y2_07 + * | | |For B-283 or K-283, POINTY2 is stored in CRYPTO_ECC_Y2_00~CRYPTO_ECC_Y2_08 + * | | |For B-409 or K-409, POINTY2 is stored in CRYPTO_ECC_Y2_00~CRYPTO_ECC_Y2_12 + * | | |For B-571 or K-571, POINTY2 is stored in CRYPTO_ECC_Y2_00~CRYPTO_ECC_Y2_17 + * | | |For P-192, POINTY2 is stored in CRYPTO_ECC_Y2_00~CRYPTO_ECC_Y2_05 + * | | |For P-224, POINTY2 is stored in CRYPTO_ECC_Y2_00~CRYPTO_ECC_Y2_06 + * | | |For P-256 or SM2, POINTY2 is stored in CRYPTO_ECC_Y2_00~CRYPTO_ECC_Y2_07 + * | | |For P-384, POINTY2 is stored in CRYPTO_ECC_Y2_00~CRYPTO_ECC_Y2_11 + * | | |For P-521, POINTY2 is stored in CRYPTO_ECC_Y2_00~CRYPTO_ECC_Y2_16 + * @var CRYPTO_T::ECC_A_00 + * Offset: 0x928 ECC the Parameter CURVEA Word0 of Elliptic Curve + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[31:0] |CURVEA |ECC the Parameter CURVEA Value of Elliptic Curve + * | | |The formula of elliptic curve is y2=x3+CURVEA*x+CURVEB in GF(p) and y2+x*y=x3+CURVEA*x2+CURVEB in GF(2m). + * | | |For B-163 or K-163, CURVEA is stored in CRYPTO_ECC_A_00~CRYPTO_ECC_A_05 + * | | |For B-233 or K-233, CURVEA is stored in CRYPTO_ECC_A_00~CRYPTO_ECC_A_07 + * | | |For B-283 or K-283, CURVEA is stored in CRYPTO_ECC_A_00~CRYPTO_ECC_A_08 + * | | |For B-409 or K-409, CURVEA is stored in CRYPTO_ECC_A_00~CRYPTO_ECC_A_12 + * | | |For B-571 or K-571, CURVEA is stored in CRYPTO_ECC_A_00~CRYPTO_ECC_A_17 + * | | |For P-192, CURVEA is stored in CRYPTO_ECC_A_00~CRYPTO_ECC_A_05 + * | | |For P-224, CURVEA is stored in CRYPTO_ECC_A_00~CRYPTO_ECC_A_06 + * | | |For P-256 or SM2, CURVEA is stored in CRYPTO_ECC_A_00~CRYPTO_ECC_A_07 + * | | |For P-384, CURVEA is stored in CRYPTO_ECC_A_00~CRYPTO_ECC_A_11 + * | | |For P-521, CURVEA is stored in CRYPTO_ECC_A_00~CRYPTO_ECC_A_16 + * @var CRYPTO_T::ECC_A_01 + * Offset: 0x92C ECC the Parameter CURVEA Word1 of Elliptic Curve + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[31:0] |CURVEA |ECC the Parameter CURVEA Value of Elliptic Curve + * | | |The formula of elliptic curve is y2=x3+CURVEA*x+CURVEB in GF(p) and y2+x*y=x3+CURVEA*x2+CURVEB in GF(2m). + * | | |For B-163 or K-163, CURVEA is stored in CRYPTO_ECC_A_00~CRYPTO_ECC_A_05 + * | | |For B-233 or K-233, CURVEA is stored in CRYPTO_ECC_A_00~CRYPTO_ECC_A_07 + * | | |For B-283 or K-283, CURVEA is stored in CRYPTO_ECC_A_00~CRYPTO_ECC_A_08 + * | | |For B-409 or K-409, CURVEA is stored in CRYPTO_ECC_A_00~CRYPTO_ECC_A_12 + * | | |For B-571 or K-571, CURVEA is stored in CRYPTO_ECC_A_00~CRYPTO_ECC_A_17 + * | | |For P-192, CURVEA is stored in CRYPTO_ECC_A_00~CRYPTO_ECC_A_05 + * | | |For P-224, CURVEA is stored in CRYPTO_ECC_A_00~CRYPTO_ECC_A_06 + * | | |For P-256 or SM2, CURVEA is stored in CRYPTO_ECC_A_00~CRYPTO_ECC_A_07 + * | | |For P-384, CURVEA is stored in CRYPTO_ECC_A_00~CRYPTO_ECC_A_11 + * | | |For P-521, CURVEA is stored in CRYPTO_ECC_A_00~CRYPTO_ECC_A_16 + * @var CRYPTO_T::ECC_A_02 + * Offset: 0x930 ECC the Parameter CURVEA Word2 of Elliptic Curve + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[31:0] |CURVEA |ECC the Parameter CURVEA Value of Elliptic Curve + * | | |The formula of elliptic curve is y2=x3+CURVEA*x+CURVEB in GF(p) and y2+x*y=x3+CURVEA*x2+CURVEB in GF(2m). + * | | |For B-163 or K-163, CURVEA is stored in CRYPTO_ECC_A_00~CRYPTO_ECC_A_05 + * | | |For B-233 or K-233, CURVEA is stored in CRYPTO_ECC_A_00~CRYPTO_ECC_A_07 + * | | |For B-283 or K-283, CURVEA is stored in CRYPTO_ECC_A_00~CRYPTO_ECC_A_08 + * | | |For B-409 or K-409, CURVEA is stored in CRYPTO_ECC_A_00~CRYPTO_ECC_A_12 + * | | |For B-571 or K-571, CURVEA is stored in CRYPTO_ECC_A_00~CRYPTO_ECC_A_17 + * | | |For P-192, CURVEA is stored in CRYPTO_ECC_A_00~CRYPTO_ECC_A_05 + * | | |For P-224, CURVEA is stored in CRYPTO_ECC_A_00~CRYPTO_ECC_A_06 + * | | |For P-256 or SM2, CURVEA is stored in CRYPTO_ECC_A_00~CRYPTO_ECC_A_07 + * | | |For P-384, CURVEA is stored in CRYPTO_ECC_A_00~CRYPTO_ECC_A_11 + * | | |For P-521, CURVEA is stored in CRYPTO_ECC_A_00~CRYPTO_ECC_A_16 + * @var CRYPTO_T::ECC_A_03 + * Offset: 0x934 ECC the Parameter CURVEA Word3 of Elliptic Curve + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[31:0] |CURVEA |ECC the Parameter CURVEA Value of Elliptic Curve + * | | |The formula of elliptic curve is y2=x3+CURVEA*x+CURVEB in GF(p) and y2+x*y=x3+CURVEA*x2+CURVEB in GF(2m). + * | | |For B-163 or K-163, CURVEA is stored in CRYPTO_ECC_A_00~CRYPTO_ECC_A_05 + * | | |For B-233 or K-233, CURVEA is stored in CRYPTO_ECC_A_00~CRYPTO_ECC_A_07 + * | | |For B-283 or K-283, CURVEA is stored in CRYPTO_ECC_A_00~CRYPTO_ECC_A_08 + * | | |For B-409 or K-409, CURVEA is stored in CRYPTO_ECC_A_00~CRYPTO_ECC_A_12 + * | | |For B-571 or K-571, CURVEA is stored in CRYPTO_ECC_A_00~CRYPTO_ECC_A_17 + * | | |For P-192, CURVEA is stored in CRYPTO_ECC_A_00~CRYPTO_ECC_A_05 + * | | |For P-224, CURVEA is stored in CRYPTO_ECC_A_00~CRYPTO_ECC_A_06 + * | | |For P-256 or SM2, CURVEA is stored in CRYPTO_ECC_A_00~CRYPTO_ECC_A_07 + * | | |For P-384, CURVEA is stored in CRYPTO_ECC_A_00~CRYPTO_ECC_A_11 + * | | |For P-521, CURVEA is stored in CRYPTO_ECC_A_00~CRYPTO_ECC_A_16 + * @var CRYPTO_T::ECC_A_04 + * Offset: 0x938 ECC the Parameter CURVEA Word4 of Elliptic Curve + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[31:0] |CURVEA |ECC the Parameter CURVEA Value of Elliptic Curve + * | | |The formula of elliptic curve is y2=x3+CURVEA*x+CURVEB in GF(p) and y2+x*y=x3+CURVEA*x2+CURVEB in GF(2m). + * | | |For B-163 or K-163, CURVEA is stored in CRYPTO_ECC_A_00~CRYPTO_ECC_A_05 + * | | |For B-233 or K-233, CURVEA is stored in CRYPTO_ECC_A_00~CRYPTO_ECC_A_07 + * | | |For B-283 or K-283, CURVEA is stored in CRYPTO_ECC_A_00~CRYPTO_ECC_A_08 + * | | |For B-409 or K-409, CURVEA is stored in CRYPTO_ECC_A_00~CRYPTO_ECC_A_12 + * | | |For B-571 or K-571, CURVEA is stored in CRYPTO_ECC_A_00~CRYPTO_ECC_A_17 + * | | |For P-192, CURVEA is stored in CRYPTO_ECC_A_00~CRYPTO_ECC_A_05 + * | | |For P-224, CURVEA is stored in CRYPTO_ECC_A_00~CRYPTO_ECC_A_06 + * | | |For P-256 or SM2, CURVEA is stored in CRYPTO_ECC_A_00~CRYPTO_ECC_A_07 + * | | |For P-384, CURVEA is stored in CRYPTO_ECC_A_00~CRYPTO_ECC_A_11 + * | | |For P-521, CURVEA is stored in CRYPTO_ECC_A_00~CRYPTO_ECC_A_16 + * @var CRYPTO_T::ECC_A_05 + * Offset: 0x93C ECC the Parameter CURVEA Word5 of Elliptic Curve + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[31:0] |CURVEA |ECC the Parameter CURVEA Value of Elliptic Curve + * | | |The formula of elliptic curve is y2=x3+CURVEA*x+CURVEB in GF(p) and y2+x*y=x3+CURVEA*x2+CURVEB in GF(2m). + * | | |For B-163 or K-163, CURVEA is stored in CRYPTO_ECC_A_00~CRYPTO_ECC_A_05 + * | | |For B-233 or K-233, CURVEA is stored in CRYPTO_ECC_A_00~CRYPTO_ECC_A_07 + * | | |For B-283 or K-283, CURVEA is stored in CRYPTO_ECC_A_00~CRYPTO_ECC_A_08 + * | | |For B-409 or K-409, CURVEA is stored in CRYPTO_ECC_A_00~CRYPTO_ECC_A_12 + * | | |For B-571 or K-571, CURVEA is stored in CRYPTO_ECC_A_00~CRYPTO_ECC_A_17 + * | | |For P-192, CURVEA is stored in CRYPTO_ECC_A_00~CRYPTO_ECC_A_05 + * | | |For P-224, CURVEA is stored in CRYPTO_ECC_A_00~CRYPTO_ECC_A_06 + * | | |For P-256 or SM2, CURVEA is stored in CRYPTO_ECC_A_00~CRYPTO_ECC_A_07 + * | | |For P-384, CURVEA is stored in CRYPTO_ECC_A_00~CRYPTO_ECC_A_11 + * | | |For P-521, CURVEA is stored in CRYPTO_ECC_A_00~CRYPTO_ECC_A_16 + * @var CRYPTO_T::ECC_A_06 + * Offset: 0x940 ECC the Parameter CURVEA Word6 of Elliptic Curve + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[31:0] |CURVEA |ECC the Parameter CURVEA Value of Elliptic Curve + * | | |The formula of elliptic curve is y2=x3+CURVEA*x+CURVEB in GF(p) and y2+x*y=x3+CURVEA*x2+CURVEB in GF(2m). + * | | |For B-163 or K-163, CURVEA is stored in CRYPTO_ECC_A_00~CRYPTO_ECC_A_05 + * | | |For B-233 or K-233, CURVEA is stored in CRYPTO_ECC_A_00~CRYPTO_ECC_A_07 + * | | |For B-283 or K-283, CURVEA is stored in CRYPTO_ECC_A_00~CRYPTO_ECC_A_08 + * | | |For B-409 or K-409, CURVEA is stored in CRYPTO_ECC_A_00~CRYPTO_ECC_A_12 + * | | |For B-571 or K-571, CURVEA is stored in CRYPTO_ECC_A_00~CRYPTO_ECC_A_17 + * | | |For P-192, CURVEA is stored in CRYPTO_ECC_A_00~CRYPTO_ECC_A_05 + * | | |For P-224, CURVEA is stored in CRYPTO_ECC_A_00~CRYPTO_ECC_A_06 + * | | |For P-256 or SM2, CURVEA is stored in CRYPTO_ECC_A_00~CRYPTO_ECC_A_07 + * | | |For P-384, CURVEA is stored in CRYPTO_ECC_A_00~CRYPTO_ECC_A_11 + * | | |For P-521, CURVEA is stored in CRYPTO_ECC_A_00~CRYPTO_ECC_A_16 + * @var CRYPTO_T::ECC_A_07 + * Offset: 0x944 ECC the Parameter CURVEA Word7 of Elliptic Curve + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[31:0] |CURVEA |ECC the Parameter CURVEA Value of Elliptic Curve + * | | |The formula of elliptic curve is y2=x3+CURVEA*x+CURVEB in GF(p) and y2+x*y=x3+CURVEA*x2+CURVEB in GF(2m). + * | | |For B-163 or K-163, CURVEA is stored in CRYPTO_ECC_A_00~CRYPTO_ECC_A_05 + * | | |For B-233 or K-233, CURVEA is stored in CRYPTO_ECC_A_00~CRYPTO_ECC_A_07 + * | | |For B-283 or K-283, CURVEA is stored in CRYPTO_ECC_A_00~CRYPTO_ECC_A_08 + * | | |For B-409 or K-409, CURVEA is stored in CRYPTO_ECC_A_00~CRYPTO_ECC_A_12 + * | | |For B-571 or K-571, CURVEA is stored in CRYPTO_ECC_A_00~CRYPTO_ECC_A_17 + * | | |For P-192, CURVEA is stored in CRYPTO_ECC_A_00~CRYPTO_ECC_A_05 + * | | |For P-224, CURVEA is stored in CRYPTO_ECC_A_00~CRYPTO_ECC_A_06 + * | | |For P-256 or SM2, CURVEA is stored in CRYPTO_ECC_A_00~CRYPTO_ECC_A_07 + * | | |For P-384, CURVEA is stored in CRYPTO_ECC_A_00~CRYPTO_ECC_A_11 + * | | |For P-521, CURVEA is stored in CRYPTO_ECC_A_00~CRYPTO_ECC_A_16 + * @var CRYPTO_T::ECC_A_08 + * Offset: 0x948 ECC the Parameter CURVEA Word8 of Elliptic Curve + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[31:0] |CURVEA |ECC the Parameter CURVEA Value of Elliptic Curve + * | | |The formula of elliptic curve is y2=x3+CURVEA*x+CURVEB in GF(p) and y2+x*y=x3+CURVEA*x2+CURVEB in GF(2m). + * | | |For B-163 or K-163, CURVEA is stored in CRYPTO_ECC_A_00~CRYPTO_ECC_A_05 + * | | |For B-233 or K-233, CURVEA is stored in CRYPTO_ECC_A_00~CRYPTO_ECC_A_07 + * | | |For B-283 or K-283, CURVEA is stored in CRYPTO_ECC_A_00~CRYPTO_ECC_A_08 + * | | |For B-409 or K-409, CURVEA is stored in CRYPTO_ECC_A_00~CRYPTO_ECC_A_12 + * | | |For B-571 or K-571, CURVEA is stored in CRYPTO_ECC_A_00~CRYPTO_ECC_A_17 + * | | |For P-192, CURVEA is stored in CRYPTO_ECC_A_00~CRYPTO_ECC_A_05 + * | | |For P-224, CURVEA is stored in CRYPTO_ECC_A_00~CRYPTO_ECC_A_06 + * | | |For P-256 or SM2, CURVEA is stored in CRYPTO_ECC_A_00~CRYPTO_ECC_A_07 + * | | |For P-384, CURVEA is stored in CRYPTO_ECC_A_00~CRYPTO_ECC_A_11 + * | | |For P-521, CURVEA is stored in CRYPTO_ECC_A_00~CRYPTO_ECC_A_16 + * @var CRYPTO_T::ECC_A_09 + * Offset: 0x94C ECC the Parameter CURVEA Word9 of Elliptic Curve + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[31:0] |CURVEA |ECC the Parameter CURVEA Value of Elliptic Curve + * | | |The formula of elliptic curve is y2=x3+CURVEA*x+CURVEB in GF(p) and y2+x*y=x3+CURVEA*x2+CURVEB in GF(2m). + * | | |For B-163 or K-163, CURVEA is stored in CRYPTO_ECC_A_00~CRYPTO_ECC_A_05 + * | | |For B-233 or K-233, CURVEA is stored in CRYPTO_ECC_A_00~CRYPTO_ECC_A_07 + * | | |For B-283 or K-283, CURVEA is stored in CRYPTO_ECC_A_00~CRYPTO_ECC_A_08 + * | | |For B-409 or K-409, CURVEA is stored in CRYPTO_ECC_A_00~CRYPTO_ECC_A_12 + * | | |For B-571 or K-571, CURVEA is stored in CRYPTO_ECC_A_00~CRYPTO_ECC_A_17 + * | | |For P-192, CURVEA is stored in CRYPTO_ECC_A_00~CRYPTO_ECC_A_05 + * | | |For P-224, CURVEA is stored in CRYPTO_ECC_A_00~CRYPTO_ECC_A_06 + * | | |For P-256 or SM2, CURVEA is stored in CRYPTO_ECC_A_00~CRYPTO_ECC_A_07 + * | | |For P-384, CURVEA is stored in CRYPTO_ECC_A_00~CRYPTO_ECC_A_11 + * | | |For P-521, CURVEA is stored in CRYPTO_ECC_A_00~CRYPTO_ECC_A_16 + * @var CRYPTO_T::ECC_A_10 + * Offset: 0x950 ECC the Parameter CURVEA Word10 of Elliptic Curve + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[31:0] |CURVEA |ECC the Parameter CURVEA Value of Elliptic Curve + * | | |The formula of elliptic curve is y2=x3+CURVEA*x+CURVEB in GF(p) and y2+x*y=x3+CURVEA*x2+CURVEB in GF(2m). + * | | |For B-163 or K-163, CURVEA is stored in CRYPTO_ECC_A_00~CRYPTO_ECC_A_05 + * | | |For B-233 or K-233, CURVEA is stored in CRYPTO_ECC_A_00~CRYPTO_ECC_A_07 + * | | |For B-283 or K-283, CURVEA is stored in CRYPTO_ECC_A_00~CRYPTO_ECC_A_08 + * | | |For B-409 or K-409, CURVEA is stored in CRYPTO_ECC_A_00~CRYPTO_ECC_A_12 + * | | |For B-571 or K-571, CURVEA is stored in CRYPTO_ECC_A_00~CRYPTO_ECC_A_17 + * | | |For P-192, CURVEA is stored in CRYPTO_ECC_A_00~CRYPTO_ECC_A_05 + * | | |For P-224, CURVEA is stored in CRYPTO_ECC_A_00~CRYPTO_ECC_A_06 + * | | |For P-256 or SM2, CURVEA is stored in CRYPTO_ECC_A_00~CRYPTO_ECC_A_07 + * | | |For P-384, CURVEA is stored in CRYPTO_ECC_A_00~CRYPTO_ECC_A_11 + * | | |For P-521, CURVEA is stored in CRYPTO_ECC_A_00~CRYPTO_ECC_A_16 + * @var CRYPTO_T::ECC_A_11 + * Offset: 0x954 ECC the Parameter CURVEA Word11 of Elliptic Curve + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[31:0] |CURVEA |ECC the Parameter CURVEA Value of Elliptic Curve + * | | |The formula of elliptic curve is y2=x3+CURVEA*x+CURVEB in GF(p) and y2+x*y=x3+CURVEA*x2+CURVEB in GF(2m). + * | | |For B-163 or K-163, CURVEA is stored in CRYPTO_ECC_A_00~CRYPTO_ECC_A_05 + * | | |For B-233 or K-233, CURVEA is stored in CRYPTO_ECC_A_00~CRYPTO_ECC_A_07 + * | | |For B-283 or K-283, CURVEA is stored in CRYPTO_ECC_A_00~CRYPTO_ECC_A_08 + * | | |For B-409 or K-409, CURVEA is stored in CRYPTO_ECC_A_00~CRYPTO_ECC_A_12 + * | | |For B-571 or K-571, CURVEA is stored in CRYPTO_ECC_A_00~CRYPTO_ECC_A_17 + * | | |For P-192, CURVEA is stored in CRYPTO_ECC_A_00~CRYPTO_ECC_A_05 + * | | |For P-224, CURVEA is stored in CRYPTO_ECC_A_00~CRYPTO_ECC_A_06 + * | | |For P-256 or SM2, CURVEA is stored in CRYPTO_ECC_A_00~CRYPTO_ECC_A_07 + * | | |For P-384, CURVEA is stored in CRYPTO_ECC_A_00~CRYPTO_ECC_A_11 + * | | |For P-521, CURVEA is stored in CRYPTO_ECC_A_00~CRYPTO_ECC_A_16 + * @var CRYPTO_T::ECC_A_12 + * Offset: 0x958 ECC the Parameter CURVEA Word12 of Elliptic Curve + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[31:0] |CURVEA |ECC the Parameter CURVEA Value of Elliptic Curve + * | | |The formula of elliptic curve is y2=x3+CURVEA*x+CURVEB in GF(p) and y2+x*y=x3+CURVEA*x2+CURVEB in GF(2m). + * | | |For B-163 or K-163, CURVEA is stored in CRYPTO_ECC_A_00~CRYPTO_ECC_A_05 + * | | |For B-233 or K-233, CURVEA is stored in CRYPTO_ECC_A_00~CRYPTO_ECC_A_07 + * | | |For B-283 or K-283, CURVEA is stored in CRYPTO_ECC_A_00~CRYPTO_ECC_A_08 + * | | |For B-409 or K-409, CURVEA is stored in CRYPTO_ECC_A_00~CRYPTO_ECC_A_12 + * | | |For B-571 or K-571, CURVEA is stored in CRYPTO_ECC_A_00~CRYPTO_ECC_A_17 + * | | |For P-192, CURVEA is stored in CRYPTO_ECC_A_00~CRYPTO_ECC_A_05 + * | | |For P-224, CURVEA is stored in CRYPTO_ECC_A_00~CRYPTO_ECC_A_06 + * | | |For P-256 or SM2, CURVEA is stored in CRYPTO_ECC_A_00~CRYPTO_ECC_A_07 + * | | |For P-384, CURVEA is stored in CRYPTO_ECC_A_00~CRYPTO_ECC_A_11 + * | | |For P-521, CURVEA is stored in CRYPTO_ECC_A_00~CRYPTO_ECC_A_16 + * @var CRYPTO_T::ECC_A_13 + * Offset: 0x95C ECC the Parameter CURVEA Word13 of Elliptic Curve + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[31:0] |CURVEA |ECC the Parameter CURVEA Value of Elliptic Curve + * | | |The formula of elliptic curve is y2=x3+CURVEA*x+CURVEB in GF(p) and y2+x*y=x3+CURVEA*x2+CURVEB in GF(2m). + * | | |For B-163 or K-163, CURVEA is stored in CRYPTO_ECC_A_00~CRYPTO_ECC_A_05 + * | | |For B-233 or K-233, CURVEA is stored in CRYPTO_ECC_A_00~CRYPTO_ECC_A_07 + * | | |For B-283 or K-283, CURVEA is stored in CRYPTO_ECC_A_00~CRYPTO_ECC_A_08 + * | | |For B-409 or K-409, CURVEA is stored in CRYPTO_ECC_A_00~CRYPTO_ECC_A_12 + * | | |For B-571 or K-571, CURVEA is stored in CRYPTO_ECC_A_00~CRYPTO_ECC_A_17 + * | | |For P-192, CURVEA is stored in CRYPTO_ECC_A_00~CRYPTO_ECC_A_05 + * | | |For P-224, CURVEA is stored in CRYPTO_ECC_A_00~CRYPTO_ECC_A_06 + * | | |For P-256 or SM2, CURVEA is stored in CRYPTO_ECC_A_00~CRYPTO_ECC_A_07 + * | | |For P-384, CURVEA is stored in CRYPTO_ECC_A_00~CRYPTO_ECC_A_11 + * | | |For P-521, CURVEA is stored in CRYPTO_ECC_A_00~CRYPTO_ECC_A_16 + * @var CRYPTO_T::ECC_A_14 + * Offset: 0x960 ECC the Parameter CURVEA Word14 of Elliptic Curve + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[31:0] |CURVEA |ECC the Parameter CURVEA Value of Elliptic Curve + * | | |The formula of elliptic curve is y2=x3+CURVEA*x+CURVEB in GF(p) and y2+x*y=x3+CURVEA*x2+CURVEB in GF(2m). + * | | |For B-163 or K-163, CURVEA is stored in CRYPTO_ECC_A_00~CRYPTO_ECC_A_05 + * | | |For B-233 or K-233, CURVEA is stored in CRYPTO_ECC_A_00~CRYPTO_ECC_A_07 + * | | |For B-283 or K-283, CURVEA is stored in CRYPTO_ECC_A_00~CRYPTO_ECC_A_08 + * | | |For B-409 or K-409, CURVEA is stored in CRYPTO_ECC_A_00~CRYPTO_ECC_A_12 + * | | |For B-571 or K-571, CURVEA is stored in CRYPTO_ECC_A_00~CRYPTO_ECC_A_17 + * | | |For P-192, CURVEA is stored in CRYPTO_ECC_A_00~CRYPTO_ECC_A_05 + * | | |For P-224, CURVEA is stored in CRYPTO_ECC_A_00~CRYPTO_ECC_A_06 + * | | |For P-256 or SM2, CURVEA is stored in CRYPTO_ECC_A_00~CRYPTO_ECC_A_07 + * | | |For P-384, CURVEA is stored in CRYPTO_ECC_A_00~CRYPTO_ECC_A_11 + * | | |For P-521, CURVEA is stored in CRYPTO_ECC_A_00~CRYPTO_ECC_A_16 + * @var CRYPTO_T::ECC_A_15 + * Offset: 0x964 ECC the Parameter CURVEA Word15 of Elliptic Curve + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[31:0] |CURVEA |ECC the Parameter CURVEA Value of Elliptic Curve + * | | |The formula of elliptic curve is y2=x3+CURVEA*x+CURVEB in GF(p) and y2+x*y=x3+CURVEA*x2+CURVEB in GF(2m). + * | | |For B-163 or K-163, CURVEA is stored in CRYPTO_ECC_A_00~CRYPTO_ECC_A_05 + * | | |For B-233 or K-233, CURVEA is stored in CRYPTO_ECC_A_00~CRYPTO_ECC_A_07 + * | | |For B-283 or K-283, CURVEA is stored in CRYPTO_ECC_A_00~CRYPTO_ECC_A_08 + * | | |For B-409 or K-409, CURVEA is stored in CRYPTO_ECC_A_00~CRYPTO_ECC_A_12 + * | | |For B-571 or K-571, CURVEA is stored in CRYPTO_ECC_A_00~CRYPTO_ECC_A_17 + * | | |For P-192, CURVEA is stored in CRYPTO_ECC_A_00~CRYPTO_ECC_A_05 + * | | |For P-224, CURVEA is stored in CRYPTO_ECC_A_00~CRYPTO_ECC_A_06 + * | | |For P-256 or SM2, CURVEA is stored in CRYPTO_ECC_A_00~CRYPTO_ECC_A_07 + * | | |For P-384, CURVEA is stored in CRYPTO_ECC_A_00~CRYPTO_ECC_A_11 + * | | |For P-521, CURVEA is stored in CRYPTO_ECC_A_00~CRYPTO_ECC_A_16 + * @var CRYPTO_T::ECC_A_16 + * Offset: 0x968 ECC the Parameter CURVEA Word16 of Elliptic Curve + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[31:0] |CURVEA |ECC the Parameter CURVEA Value of Elliptic Curve + * | | |The formula of elliptic curve is y2=x3+CURVEA*x+CURVEB in GF(p) and y2+x*y=x3+CURVEA*x2+CURVEB in GF(2m). + * | | |For B-163 or K-163, CURVEA is stored in CRYPTO_ECC_A_00~CRYPTO_ECC_A_05 + * | | |For B-233 or K-233, CURVEA is stored in CRYPTO_ECC_A_00~CRYPTO_ECC_A_07 + * | | |For B-283 or K-283, CURVEA is stored in CRYPTO_ECC_A_00~CRYPTO_ECC_A_08 + * | | |For B-409 or K-409, CURVEA is stored in CRYPTO_ECC_A_00~CRYPTO_ECC_A_12 + * | | |For B-571 or K-571, CURVEA is stored in CRYPTO_ECC_A_00~CRYPTO_ECC_A_17 + * | | |For P-192, CURVEA is stored in CRYPTO_ECC_A_00~CRYPTO_ECC_A_05 + * | | |For P-224, CURVEA is stored in CRYPTO_ECC_A_00~CRYPTO_ECC_A_06 + * | | |For P-256 or SM2, CURVEA is stored in CRYPTO_ECC_A_00~CRYPTO_ECC_A_07 + * | | |For P-384, CURVEA is stored in CRYPTO_ECC_A_00~CRYPTO_ECC_A_11 + * | | |For P-521, CURVEA is stored in CRYPTO_ECC_A_00~CRYPTO_ECC_A_16 + * @var CRYPTO_T::ECC_A_17 + * Offset: 0x96C ECC the Parameter CURVEA Word17 of Elliptic Curve + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[31:0] |CURVEA |ECC the Parameter CURVEA Value of Elliptic Curve + * | | |The formula of elliptic curve is y2=x3+CURVEA*x+CURVEB in GF(p) and y2+x*y=x3+CURVEA*x2+CURVEB in GF(2m). + * | | |For B-163 or K-163, CURVEA is stored in CRYPTO_ECC_A_00~CRYPTO_ECC_A_05 + * | | |For B-233 or K-233, CURVEA is stored in CRYPTO_ECC_A_00~CRYPTO_ECC_A_07 + * | | |For B-283 or K-283, CURVEA is stored in CRYPTO_ECC_A_00~CRYPTO_ECC_A_08 + * | | |For B-409 or K-409, CURVEA is stored in CRYPTO_ECC_A_00~CRYPTO_ECC_A_12 + * | | |For B-571 or K-571, CURVEA is stored in CRYPTO_ECC_A_00~CRYPTO_ECC_A_17 + * | | |For P-192, CURVEA is stored in CRYPTO_ECC_A_00~CRYPTO_ECC_A_05 + * | | |For P-224, CURVEA is stored in CRYPTO_ECC_A_00~CRYPTO_ECC_A_06 + * | | |For P-256 or SM2, CURVEA is stored in CRYPTO_ECC_A_00~CRYPTO_ECC_A_07 + * | | |For P-384, CURVEA is stored in CRYPTO_ECC_A_00~CRYPTO_ECC_A_11 + * | | |For P-521, CURVEA is stored in CRYPTO_ECC_A_00~CRYPTO_ECC_A_16 + * @var CRYPTO_T::ECC_B_00 + * Offset: 0x970 ECC the Parameter CURVEB Word0 of Elliptic Curve + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[31:0] |CURVEB |ECC the Parameter CURVEB Value of Elliptic Curve + * | | |The formula of elliptic curve is y2=x3+CURVEA*x+CURVEB in GF(p) and y2+x*y=x3+CURVEA*x2+CURVEB in GF(2m). + * | | |For B-163 or K-163, CURVEB is stored in CRYPTO_ECC_B_00~CRYPTO_ECC_B_05 + * | | |For B-233 or K-233, CURVEB is stored in CRYPTO_ECC_B_00~CRYPTO_ECC_B_07 + * | | |For B-283 or K-283, CURVEB is stored in CRYPTO_ECC_B_00~CRYPTO_ECC_B_08 + * | | |For B-409 or K-409, CURVEB is stored in CRYPTO_ECC_B_00~CRYPTO_ECC_B_12 + * | | |For B-521 or K-521, CURVEB is stored in CRYPTO_ECC_B_00~CRYPTO_ECC_B_17 + * | | |For P-192, CURVEB is stored in CRYPTO_ECC_B_00~CRYPTO_ECC_B_05 + * | | |For P-224, CURVEB is stored in CRYPTO_ECC_B_00~CRYPTO_ECC_B_06 + * | | |For P-256 or SM2, CURVEB is stored in CRYPTO_ECC_B_00~CRYPTO_ECC_B_07 + * | | |For P-384, CURVEB is stored in CRYPTO_ECC_B_00~CRYPTO_ECC_B_11 + * | | |For P-521, CURVEB is stored in CRYPTO_ECC_B_00~CRYPTO_ECC_B_16 + * @var CRYPTO_T::ECC_B_01 + * Offset: 0x974 ECC the Parameter CURVEB Word1 of Elliptic Curve + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[31:0] |CURVEB |ECC the Parameter CURVEB Value of Elliptic Curve + * | | |The formula of elliptic curve is y2=x3+CURVEA*x+CURVEB in GF(p) and y2+x*y=x3+CURVEA*x2+CURVEB in GF(2m). + * | | |For B-163 or K-163, CURVEB is stored in CRYPTO_ECC_B_00~CRYPTO_ECC_B_05 + * | | |For B-233 or K-233, CURVEB is stored in CRYPTO_ECC_B_00~CRYPTO_ECC_B_07 + * | | |For B-283 or K-283, CURVEB is stored in CRYPTO_ECC_B_00~CRYPTO_ECC_B_08 + * | | |For B-409 or K-409, CURVEB is stored in CRYPTO_ECC_B_00~CRYPTO_ECC_B_12 + * | | |For B-521 or K-521, CURVEB is stored in CRYPTO_ECC_B_00~CRYPTO_ECC_B_17 + * | | |For P-192, CURVEB is stored in CRYPTO_ECC_B_00~CRYPTO_ECC_B_05 + * | | |For P-224, CURVEB is stored in CRYPTO_ECC_B_00~CRYPTO_ECC_B_06 + * | | |For P-256 or SM2, CURVEB is stored in CRYPTO_ECC_B_00~CRYPTO_ECC_B_07 + * | | |For P-384, CURVEB is stored in CRYPTO_ECC_B_00~CRYPTO_ECC_B_11 + * | | |For P-521, CURVEB is stored in CRYPTO_ECC_B_00~CRYPTO_ECC_B_16 + * @var CRYPTO_T::ECC_B_02 + * Offset: 0x978 ECC the Parameter CURVEB Word2 of Elliptic Curve + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[31:0] |CURVEB |ECC the Parameter CURVEB Value of Elliptic Curve + * | | |The formula of elliptic curve is y2=x3+CURVEA*x+CURVEB in GF(p) and y2+x*y=x3+CURVEA*x2+CURVEB in GF(2m). + * | | |For B-163 or K-163, CURVEB is stored in CRYPTO_ECC_B_00~CRYPTO_ECC_B_05 + * | | |For B-233 or K-233, CURVEB is stored in CRYPTO_ECC_B_00~CRYPTO_ECC_B_07 + * | | |For B-283 or K-283, CURVEB is stored in CRYPTO_ECC_B_00~CRYPTO_ECC_B_08 + * | | |For B-409 or K-409, CURVEB is stored in CRYPTO_ECC_B_00~CRYPTO_ECC_B_12 + * | | |For B-521 or K-521, CURVEB is stored in CRYPTO_ECC_B_00~CRYPTO_ECC_B_17 + * | | |For P-192, CURVEB is stored in CRYPTO_ECC_B_00~CRYPTO_ECC_B_05 + * | | |For P-224, CURVEB is stored in CRYPTO_ECC_B_00~CRYPTO_ECC_B_06 + * | | |For P-256 or SM2, CURVEB is stored in CRYPTO_ECC_B_00~CRYPTO_ECC_B_07 + * | | |For P-384, CURVEB is stored in CRYPTO_ECC_B_00~CRYPTO_ECC_B_11 + * | | |For P-521, CURVEB is stored in CRYPTO_ECC_B_00~CRYPTO_ECC_B_16 + * @var CRYPTO_T::ECC_B_03 + * Offset: 0x97C ECC the Parameter CURVEB Word3 of Elliptic Curve + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[31:0] |CURVEB |ECC the Parameter CURVEB Value of Elliptic Curve + * | | |The formula of elliptic curve is y2=x3+CURVEA*x+CURVEB in GF(p) and y2+x*y=x3+CURVEA*x2+CURVEB in GF(2m). + * | | |For B-163 or K-163, CURVEB is stored in CRYPTO_ECC_B_00~CRYPTO_ECC_B_05 + * | | |For B-233 or K-233, CURVEB is stored in CRYPTO_ECC_B_00~CRYPTO_ECC_B_07 + * | | |For B-283 or K-283, CURVEB is stored in CRYPTO_ECC_B_00~CRYPTO_ECC_B_08 + * | | |For B-409 or K-409, CURVEB is stored in CRYPTO_ECC_B_00~CRYPTO_ECC_B_12 + * | | |For B-521 or K-521, CURVEB is stored in CRYPTO_ECC_B_00~CRYPTO_ECC_B_17 + * | | |For P-192, CURVEB is stored in CRYPTO_ECC_B_00~CRYPTO_ECC_B_05 + * | | |For P-224, CURVEB is stored in CRYPTO_ECC_B_00~CRYPTO_ECC_B_06 + * | | |For P-256 or SM2, CURVEB is stored in CRYPTO_ECC_B_00~CRYPTO_ECC_B_07 + * | | |For P-384, CURVEB is stored in CRYPTO_ECC_B_00~CRYPTO_ECC_B_11 + * | | |For P-521, CURVEB is stored in CRYPTO_ECC_B_00~CRYPTO_ECC_B_16 + * @var CRYPTO_T::ECC_B_04 + * Offset: 0x980 ECC the Parameter CURVEB Word4 of Elliptic Curve + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[31:0] |CURVEB |ECC the Parameter CURVEB Value of Elliptic Curve + * | | |The formula of elliptic curve is y2=x3+CURVEA*x+CURVEB in GF(p) and y2+x*y=x3+CURVEA*x2+CURVEB in GF(2m). + * | | |For B-163 or K-163, CURVEB is stored in CRYPTO_ECC_B_00~CRYPTO_ECC_B_05 + * | | |For B-233 or K-233, CURVEB is stored in CRYPTO_ECC_B_00~CRYPTO_ECC_B_07 + * | | |For B-283 or K-283, CURVEB is stored in CRYPTO_ECC_B_00~CRYPTO_ECC_B_08 + * | | |For B-409 or K-409, CURVEB is stored in CRYPTO_ECC_B_00~CRYPTO_ECC_B_12 + * | | |For B-521 or K-521, CURVEB is stored in CRYPTO_ECC_B_00~CRYPTO_ECC_B_17 + * | | |For P-192, CURVEB is stored in CRYPTO_ECC_B_00~CRYPTO_ECC_B_05 + * | | |For P-224, CURVEB is stored in CRYPTO_ECC_B_00~CRYPTO_ECC_B_06 + * | | |For P-256 or SM2, CURVEB is stored in CRYPTO_ECC_B_00~CRYPTO_ECC_B_07 + * | | |For P-384, CURVEB is stored in CRYPTO_ECC_B_00~CRYPTO_ECC_B_11 + * | | |For P-521, CURVEB is stored in CRYPTO_ECC_B_00~CRYPTO_ECC_B_16 + * @var CRYPTO_T::ECC_B_05 + * Offset: 0x984 ECC the Parameter CURVEB Word5 of Elliptic Curve + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[31:0] |CURVEB |ECC the Parameter CURVEB Value of Elliptic Curve + * | | |The formula of elliptic curve is y2=x3+CURVEA*x+CURVEB in GF(p) and y2+x*y=x3+CURVEA*x2+CURVEB in GF(2m). + * | | |For B-163 or K-163, CURVEB is stored in CRYPTO_ECC_B_00~CRYPTO_ECC_B_05 + * | | |For B-233 or K-233, CURVEB is stored in CRYPTO_ECC_B_00~CRYPTO_ECC_B_07 + * | | |For B-283 or K-283, CURVEB is stored in CRYPTO_ECC_B_00~CRYPTO_ECC_B_08 + * | | |For B-409 or K-409, CURVEB is stored in CRYPTO_ECC_B_00~CRYPTO_ECC_B_12 + * | | |For B-521 or K-521, CURVEB is stored in CRYPTO_ECC_B_00~CRYPTO_ECC_B_17 + * | | |For P-192, CURVEB is stored in CRYPTO_ECC_B_00~CRYPTO_ECC_B_05 + * | | |For P-224, CURVEB is stored in CRYPTO_ECC_B_00~CRYPTO_ECC_B_06 + * | | |For P-256 or SM2, CURVEB is stored in CRYPTO_ECC_B_00~CRYPTO_ECC_B_07 + * | | |For P-384, CURVEB is stored in CRYPTO_ECC_B_00~CRYPTO_ECC_B_11 + * | | |For P-521, CURVEB is stored in CRYPTO_ECC_B_00~CRYPTO_ECC_B_16 + * @var CRYPTO_T::ECC_B_06 + * Offset: 0x988 ECC the Parameter CURVEB Word6 of Elliptic Curve + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[31:0] |CURVEB |ECC the Parameter CURVEB Value of Elliptic Curve + * | | |The formula of elliptic curve is y2=x3+CURVEA*x+CURVEB in GF(p) and y2+x*y=x3+CURVEA*x2+CURVEB in GF(2m). + * | | |For B-163 or K-163, CURVEB is stored in CRYPTO_ECC_B_00~CRYPTO_ECC_B_05 + * | | |For B-233 or K-233, CURVEB is stored in CRYPTO_ECC_B_00~CRYPTO_ECC_B_07 + * | | |For B-283 or K-283, CURVEB is stored in CRYPTO_ECC_B_00~CRYPTO_ECC_B_08 + * | | |For B-409 or K-409, CURVEB is stored in CRYPTO_ECC_B_00~CRYPTO_ECC_B_12 + * | | |For B-521 or K-521, CURVEB is stored in CRYPTO_ECC_B_00~CRYPTO_ECC_B_17 + * | | |For P-192, CURVEB is stored in CRYPTO_ECC_B_00~CRYPTO_ECC_B_05 + * | | |For P-224, CURVEB is stored in CRYPTO_ECC_B_00~CRYPTO_ECC_B_06 + * | | |For P-256 or SM2, CURVEB is stored in CRYPTO_ECC_B_00~CRYPTO_ECC_B_07 + * | | |For P-384, CURVEB is stored in CRYPTO_ECC_B_00~CRYPTO_ECC_B_11 + * | | |For P-521, CURVEB is stored in CRYPTO_ECC_B_00~CRYPTO_ECC_B_16 + * @var CRYPTO_T::ECC_B_07 + * Offset: 0x98C ECC the Parameter CURVEB Word7 of Elliptic Curve + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[31:0] |CURVEB |ECC the Parameter CURVEB Value of Elliptic Curve + * | | |The formula of elliptic curve is y2=x3+CURVEA*x+CURVEB in GF(p) and y2+x*y=x3+CURVEA*x2+CURVEB in GF(2m). + * | | |For B-163 or K-163, CURVEB is stored in CRYPTO_ECC_B_00~CRYPTO_ECC_B_05 + * | | |For B-233 or K-233, CURVEB is stored in CRYPTO_ECC_B_00~CRYPTO_ECC_B_07 + * | | |For B-283 or K-283, CURVEB is stored in CRYPTO_ECC_B_00~CRYPTO_ECC_B_08 + * | | |For B-409 or K-409, CURVEB is stored in CRYPTO_ECC_B_00~CRYPTO_ECC_B_12 + * | | |For B-521 or K-521, CURVEB is stored in CRYPTO_ECC_B_00~CRYPTO_ECC_B_17 + * | | |For P-192, CURVEB is stored in CRYPTO_ECC_B_00~CRYPTO_ECC_B_05 + * | | |For P-224, CURVEB is stored in CRYPTO_ECC_B_00~CRYPTO_ECC_B_06 + * | | |For P-256 or SM2, CURVEB is stored in CRYPTO_ECC_B_00~CRYPTO_ECC_B_07 + * | | |For P-384, CURVEB is stored in CRYPTO_ECC_B_00~CRYPTO_ECC_B_11 + * | | |For P-521, CURVEB is stored in CRYPTO_ECC_B_00~CRYPTO_ECC_B_16 + * @var CRYPTO_T::ECC_B_08 + * Offset: 0x990 ECC the Parameter CURVEB Word8 of Elliptic Curve + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[31:0] |CURVEB |ECC the Parameter CURVEB Value of Elliptic Curve + * | | |The formula of elliptic curve is y2=x3+CURVEA*x+CURVEB in GF(p) and y2+x*y=x3+CURVEA*x2+CURVEB in GF(2m). + * | | |For B-163 or K-163, CURVEB is stored in CRYPTO_ECC_B_00~CRYPTO_ECC_B_05 + * | | |For B-233 or K-233, CURVEB is stored in CRYPTO_ECC_B_00~CRYPTO_ECC_B_07 + * | | |For B-283 or K-283, CURVEB is stored in CRYPTO_ECC_B_00~CRYPTO_ECC_B_08 + * | | |For B-409 or K-409, CURVEB is stored in CRYPTO_ECC_B_00~CRYPTO_ECC_B_12 + * | | |For B-521 or K-521, CURVEB is stored in CRYPTO_ECC_B_00~CRYPTO_ECC_B_17 + * | | |For P-192, CURVEB is stored in CRYPTO_ECC_B_00~CRYPTO_ECC_B_05 + * | | |For P-224, CURVEB is stored in CRYPTO_ECC_B_00~CRYPTO_ECC_B_06 + * | | |For P-256 or SM2, CURVEB is stored in CRYPTO_ECC_B_00~CRYPTO_ECC_B_07 + * | | |For P-384, CURVEB is stored in CRYPTO_ECC_B_00~CRYPTO_ECC_B_11 + * | | |For P-521, CURVEB is stored in CRYPTO_ECC_B_00~CRYPTO_ECC_B_16 + * @var CRYPTO_T::ECC_B_09 + * Offset: 0x994 ECC the Parameter CURVEB Word9 of Elliptic Curve + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[31:0] |CURVEB |ECC the Parameter CURVEB Value of Elliptic Curve + * | | |The formula of elliptic curve is y2=x3+CURVEA*x+CURVEB in GF(p) and y2+x*y=x3+CURVEA*x2+CURVEB in GF(2m). + * | | |For B-163 or K-163, CURVEB is stored in CRYPTO_ECC_B_00~CRYPTO_ECC_B_05 + * | | |For B-233 or K-233, CURVEB is stored in CRYPTO_ECC_B_00~CRYPTO_ECC_B_07 + * | | |For B-283 or K-283, CURVEB is stored in CRYPTO_ECC_B_00~CRYPTO_ECC_B_08 + * | | |For B-409 or K-409, CURVEB is stored in CRYPTO_ECC_B_00~CRYPTO_ECC_B_12 + * | | |For B-521 or K-521, CURVEB is stored in CRYPTO_ECC_B_00~CRYPTO_ECC_B_17 + * | | |For P-192, CURVEB is stored in CRYPTO_ECC_B_00~CRYPTO_ECC_B_05 + * | | |For P-224, CURVEB is stored in CRYPTO_ECC_B_00~CRYPTO_ECC_B_06 + * | | |For P-256 or SM2, CURVEB is stored in CRYPTO_ECC_B_00~CRYPTO_ECC_B_07 + * | | |For P-384, CURVEB is stored in CRYPTO_ECC_B_00~CRYPTO_ECC_B_11 + * | | |For P-521, CURVEB is stored in CRYPTO_ECC_B_00~CRYPTO_ECC_B_16 + * @var CRYPTO_T::ECC_B_10 + * Offset: 0x998 ECC the Parameter CURVEB Word10 of Elliptic Curve + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[31:0] |CURVEB |ECC the Parameter CURVEB Value of Elliptic Curve + * | | |The formula of elliptic curve is y2=x3+CURVEA*x+CURVEB in GF(p) and y2+x*y=x3+CURVEA*x2+CURVEB in GF(2m). + * | | |For B-163 or K-163, CURVEB is stored in CRYPTO_ECC_B_00~CRYPTO_ECC_B_05 + * | | |For B-233 or K-233, CURVEB is stored in CRYPTO_ECC_B_00~CRYPTO_ECC_B_07 + * | | |For B-283 or K-283, CURVEB is stored in CRYPTO_ECC_B_00~CRYPTO_ECC_B_08 + * | | |For B-409 or K-409, CURVEB is stored in CRYPTO_ECC_B_00~CRYPTO_ECC_B_12 + * | | |For B-521 or K-521, CURVEB is stored in CRYPTO_ECC_B_00~CRYPTO_ECC_B_17 + * | | |For P-192, CURVEB is stored in CRYPTO_ECC_B_00~CRYPTO_ECC_B_05 + * | | |For P-224, CURVEB is stored in CRYPTO_ECC_B_00~CRYPTO_ECC_B_06 + * | | |For P-256 or SM2, CURVEB is stored in CRYPTO_ECC_B_00~CRYPTO_ECC_B_07 + * | | |For P-384, CURVEB is stored in CRYPTO_ECC_B_00~CRYPTO_ECC_B_11 + * | | |For P-521, CURVEB is stored in CRYPTO_ECC_B_00~CRYPTO_ECC_B_16 + * @var CRYPTO_T::ECC_B_11 + * Offset: 0x99C ECC the Parameter CURVEB Word11 of Elliptic Curve + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[31:0] |CURVEB |ECC the Parameter CURVEB Value of Elliptic Curve + * | | |The formula of elliptic curve is y2=x3+CURVEA*x+CURVEB in GF(p) and y2+x*y=x3+CURVEA*x2+CURVEB in GF(2m). + * | | |For B-163 or K-163, CURVEB is stored in CRYPTO_ECC_B_00~CRYPTO_ECC_B_05 + * | | |For B-233 or K-233, CURVEB is stored in CRYPTO_ECC_B_00~CRYPTO_ECC_B_07 + * | | |For B-283 or K-283, CURVEB is stored in CRYPTO_ECC_B_00~CRYPTO_ECC_B_08 + * | | |For B-409 or K-409, CURVEB is stored in CRYPTO_ECC_B_00~CRYPTO_ECC_B_12 + * | | |For B-521 or K-521, CURVEB is stored in CRYPTO_ECC_B_00~CRYPTO_ECC_B_17 + * | | |For P-192, CURVEB is stored in CRYPTO_ECC_B_00~CRYPTO_ECC_B_05 + * | | |For P-224, CURVEB is stored in CRYPTO_ECC_B_00~CRYPTO_ECC_B_06 + * | | |For P-256 or SM2, CURVEB is stored in CRYPTO_ECC_B_00~CRYPTO_ECC_B_07 + * | | |For P-384, CURVEB is stored in CRYPTO_ECC_B_00~CRYPTO_ECC_B_11 + * | | |For P-521, CURVEB is stored in CRYPTO_ECC_B_00~CRYPTO_ECC_B_16 + * @var CRYPTO_T::ECC_B_12 + * Offset: 0x9A0 ECC the Parameter CURVEB Word12 of Elliptic Curve + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[31:0] |CURVEB |ECC the Parameter CURVEB Value of Elliptic Curve + * | | |The formula of elliptic curve is y2=x3+CURVEA*x+CURVEB in GF(p) and y2+x*y=x3+CURVEA*x2+CURVEB in GF(2m). + * | | |For B-163 or K-163, CURVEB is stored in CRYPTO_ECC_B_00~CRYPTO_ECC_B_05 + * | | |For B-233 or K-233, CURVEB is stored in CRYPTO_ECC_B_00~CRYPTO_ECC_B_07 + * | | |For B-283 or K-283, CURVEB is stored in CRYPTO_ECC_B_00~CRYPTO_ECC_B_08 + * | | |For B-409 or K-409, CURVEB is stored in CRYPTO_ECC_B_00~CRYPTO_ECC_B_12 + * | | |For B-521 or K-521, CURVEB is stored in CRYPTO_ECC_B_00~CRYPTO_ECC_B_17 + * | | |For P-192, CURVEB is stored in CRYPTO_ECC_B_00~CRYPTO_ECC_B_05 + * | | |For P-224, CURVEB is stored in CRYPTO_ECC_B_00~CRYPTO_ECC_B_06 + * | | |For P-256 or SM2, CURVEB is stored in CRYPTO_ECC_B_00~CRYPTO_ECC_B_07 + * | | |For P-384, CURVEB is stored in CRYPTO_ECC_B_00~CRYPTO_ECC_B_11 + * | | |For P-521, CURVEB is stored in CRYPTO_ECC_B_00~CRYPTO_ECC_B_16 + * @var CRYPTO_T::ECC_B_13 + * Offset: 0x9A4 ECC the Parameter CURVEB Word13 of Elliptic Curve + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[31:0] |CURVEB |ECC the Parameter CURVEB Value of Elliptic Curve + * | | |The formula of elliptic curve is y2=x3+CURVEA*x+CURVEB in GF(p) and y2+x*y=x3+CURVEA*x2+CURVEB in GF(2m). + * | | |For B-163 or K-163, CURVEB is stored in CRYPTO_ECC_B_00~CRYPTO_ECC_B_05 + * | | |For B-233 or K-233, CURVEB is stored in CRYPTO_ECC_B_00~CRYPTO_ECC_B_07 + * | | |For B-283 or K-283, CURVEB is stored in CRYPTO_ECC_B_00~CRYPTO_ECC_B_08 + * | | |For B-409 or K-409, CURVEB is stored in CRYPTO_ECC_B_00~CRYPTO_ECC_B_12 + * | | |For B-521 or K-521, CURVEB is stored in CRYPTO_ECC_B_00~CRYPTO_ECC_B_17 + * | | |For P-192, CURVEB is stored in CRYPTO_ECC_B_00~CRYPTO_ECC_B_05 + * | | |For P-224, CURVEB is stored in CRYPTO_ECC_B_00~CRYPTO_ECC_B_06 + * | | |For P-256 or SM2, CURVEB is stored in CRYPTO_ECC_B_00~CRYPTO_ECC_B_07 + * | | |For P-384, CURVEB is stored in CRYPTO_ECC_B_00~CRYPTO_ECC_B_11 + * | | |For P-521, CURVEB is stored in CRYPTO_ECC_B_00~CRYPTO_ECC_B_16 + * @var CRYPTO_T::ECC_B_14 + * Offset: 0x9A8 ECC the Parameter CURVEB Word14 of Elliptic Curve + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[31:0] |CURVEB |ECC the Parameter CURVEB Value of Elliptic Curve + * | | |The formula of elliptic curve is y2=x3+CURVEA*x+CURVEB in GF(p) and y2+x*y=x3+CURVEA*x2+CURVEB in GF(2m). + * | | |For B-163 or K-163, CURVEB is stored in CRYPTO_ECC_B_00~CRYPTO_ECC_B_05 + * | | |For B-233 or K-233, CURVEB is stored in CRYPTO_ECC_B_00~CRYPTO_ECC_B_07 + * | | |For B-283 or K-283, CURVEB is stored in CRYPTO_ECC_B_00~CRYPTO_ECC_B_08 + * | | |For B-409 or K-409, CURVEB is stored in CRYPTO_ECC_B_00~CRYPTO_ECC_B_12 + * | | |For B-521 or K-521, CURVEB is stored in CRYPTO_ECC_B_00~CRYPTO_ECC_B_17 + * | | |For P-192, CURVEB is stored in CRYPTO_ECC_B_00~CRYPTO_ECC_B_05 + * | | |For P-224, CURVEB is stored in CRYPTO_ECC_B_00~CRYPTO_ECC_B_06 + * | | |For P-256 or SM2, CURVEB is stored in CRYPTO_ECC_B_00~CRYPTO_ECC_B_07 + * | | |For P-384, CURVEB is stored in CRYPTO_ECC_B_00~CRYPTO_ECC_B_11 + * | | |For P-521, CURVEB is stored in CRYPTO_ECC_B_00~CRYPTO_ECC_B_16 + * @var CRYPTO_T::ECC_B_15 + * Offset: 0x9AC ECC the Parameter CURVEB Word15 of Elliptic Curve + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[31:0] |CURVEB |ECC the Parameter CURVEB Value of Elliptic Curve + * | | |The formula of elliptic curve is y2=x3+CURVEA*x+CURVEB in GF(p) and y2+x*y=x3+CURVEA*x2+CURVEB in GF(2m). + * | | |For B-163 or K-163, CURVEB is stored in CRYPTO_ECC_B_00~CRYPTO_ECC_B_05 + * | | |For B-233 or K-233, CURVEB is stored in CRYPTO_ECC_B_00~CRYPTO_ECC_B_07 + * | | |For B-283 or K-283, CURVEB is stored in CRYPTO_ECC_B_00~CRYPTO_ECC_B_08 + * | | |For B-409 or K-409, CURVEB is stored in CRYPTO_ECC_B_00~CRYPTO_ECC_B_12 + * | | |For B-521 or K-521, CURVEB is stored in CRYPTO_ECC_B_00~CRYPTO_ECC_B_17 + * | | |For P-192, CURVEB is stored in CRYPTO_ECC_B_00~CRYPTO_ECC_B_05 + * | | |For P-224, CURVEB is stored in CRYPTO_ECC_B_00~CRYPTO_ECC_B_06 + * | | |For P-256 or SM2, CURVEB is stored in CRYPTO_ECC_B_00~CRYPTO_ECC_B_07 + * | | |For P-384, CURVEB is stored in CRYPTO_ECC_B_00~CRYPTO_ECC_B_11 + * | | |For P-521, CURVEB is stored in CRYPTO_ECC_B_00~CRYPTO_ECC_B_16 + * @var CRYPTO_T::ECC_B_16 + * Offset: 0x9B0 ECC the Parameter CURVEB Word16 of Elliptic Curve + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[31:0] |CURVEB |ECC the Parameter CURVEB Value of Elliptic Curve + * | | |The formula of elliptic curve is y2=x3+CURVEA*x+CURVEB in GF(p) and y2+x*y=x3+CURVEA*x2+CURVEB in GF(2m). + * | | |For B-163 or K-163, CURVEB is stored in CRYPTO_ECC_B_00~CRYPTO_ECC_B_05 + * | | |For B-233 or K-233, CURVEB is stored in CRYPTO_ECC_B_00~CRYPTO_ECC_B_07 + * | | |For B-283 or K-283, CURVEB is stored in CRYPTO_ECC_B_00~CRYPTO_ECC_B_08 + * | | |For B-409 or K-409, CURVEB is stored in CRYPTO_ECC_B_00~CRYPTO_ECC_B_12 + * | | |For B-521 or K-521, CURVEB is stored in CRYPTO_ECC_B_00~CRYPTO_ECC_B_17 + * | | |For P-192, CURVEB is stored in CRYPTO_ECC_B_00~CRYPTO_ECC_B_05 + * | | |For P-224, CURVEB is stored in CRYPTO_ECC_B_00~CRYPTO_ECC_B_06 + * | | |For P-256 or SM2, CURVEB is stored in CRYPTO_ECC_B_00~CRYPTO_ECC_B_07 + * | | |For P-384, CURVEB is stored in CRYPTO_ECC_B_00~CRYPTO_ECC_B_11 + * | | |For P-521, CURVEB is stored in CRYPTO_ECC_B_00~CRYPTO_ECC_B_16 + * @var CRYPTO_T::ECC_B_17 + * Offset: 0x9B4 ECC the Parameter CURVEB Word17 of Elliptic Curve + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[31:0] |CURVEB |ECC the Parameter CURVEB Value of Elliptic Curve + * | | |The formula of elliptic curve is y2=x3+CURVEA*x+CURVEB in GF(p) and y2+x*y=x3+CURVEA*x2+CURVEB in GF(2m). + * | | |For B-163 or K-163, CURVEB is stored in CRYPTO_ECC_B_00~CRYPTO_ECC_B_05 + * | | |For B-233 or K-233, CURVEB is stored in CRYPTO_ECC_B_00~CRYPTO_ECC_B_07 + * | | |For B-283 or K-283, CURVEB is stored in CRYPTO_ECC_B_00~CRYPTO_ECC_B_08 + * | | |For B-409 or K-409, CURVEB is stored in CRYPTO_ECC_B_00~CRYPTO_ECC_B_12 + * | | |For B-521 or K-521, CURVEB is stored in CRYPTO_ECC_B_00~CRYPTO_ECC_B_17 + * | | |For P-192, CURVEB is stored in CRYPTO_ECC_B_00~CRYPTO_ECC_B_05 + * | | |For P-224, CURVEB is stored in CRYPTO_ECC_B_00~CRYPTO_ECC_B_06 + * | | |For P-256 or SM2, CURVEB is stored in CRYPTO_ECC_B_00~CRYPTO_ECC_B_07 + * | | |For P-384, CURVEB is stored in CRYPTO_ECC_B_00~CRYPTO_ECC_B_11 + * | | |For P-521, CURVEB is stored in CRYPTO_ECC_B_00~CRYPTO_ECC_B_16 + * @var CRYPTO_T::ECC_N_00 + * Offset: 0x9B8 ECC the Parameter CURVEN Word0 of Elliptic Curve + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[31:0] |CURVEN |ECC the Parameter CURVEN Value of Elliptic Curve + * | | |In GF(p), CURVEN is the prime p. + * | | |In GF(2m), CURVEN is the irreducible polynomial. + * | | |For B-163 or K-163, CURVEN is stored in CRYPTO_ECC_N_00~CRYPTO_ECC_N_05 + * | | |For B-233 or K-233, CURVEN is stored in CRYPTO_ECC_N_00~CRYPTO_ECC_N_07 + * | | |For B-283 or K-283, CURVEN is stored in CRYPTO_ECC_N_00~CRYPTO_ECC_N_08 + * | | |For B-409 or K-409, CURVEN is stored in CRYPTO_ECC_N_00~CRYPTO_ECC_N_12 + * | | |For B-571 or K-571, CURVEN is stored in CRYPTO_ECC_N_00~CRYPTO_ECC_N_17 + * | | |For P-192, CURVEN is stored in CRYPTO_ECC_N_00~CRYPTO_ECC_N_05 + * | | |For P-224, CURVEN is stored in CRYPTO_ECC_N_00~CRYPTO_ECC_N_06 + * | | |For P-256 or SM2, CURVEN is stored in CRYPTO_ECC_N_00~CRYPTO_ECC_N_07 + * | | |For P-384, CURVEN is stored in CRYPTO_ECC_N_00~CRYPTO_ECC_N_11 + * | | |For P-521, CURVEN is stored in CRYPTO_ECC_N_00~CRYPTO_ECC_N_16 + * @var CRYPTO_T::ECC_N_01 + * Offset: 0x9BC ECC the Parameter CURVEN Word1 of Elliptic Curve + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[31:0] |CURVEN |ECC the Parameter CURVEN Value of Elliptic Curve + * | | |In GF(p), CURVEN is the prime p. + * | | |In GF(2m), CURVEN is the irreducible polynomial. + * | | |For B-163 or K-163, CURVEN is stored in CRYPTO_ECC_N_00~CRYPTO_ECC_N_05 + * | | |For B-233 or K-233, CURVEN is stored in CRYPTO_ECC_N_00~CRYPTO_ECC_N_07 + * | | |For B-283 or K-283, CURVEN is stored in CRYPTO_ECC_N_00~CRYPTO_ECC_N_08 + * | | |For B-409 or K-409, CURVEN is stored in CRYPTO_ECC_N_00~CRYPTO_ECC_N_12 + * | | |For B-571 or K-571, CURVEN is stored in CRYPTO_ECC_N_00~CRYPTO_ECC_N_17 + * | | |For P-192, CURVEN is stored in CRYPTO_ECC_N_00~CRYPTO_ECC_N_05 + * | | |For P-224, CURVEN is stored in CRYPTO_ECC_N_00~CRYPTO_ECC_N_06 + * | | |For P-256 or SM2, CURVEN is stored in CRYPTO_ECC_N_00~CRYPTO_ECC_N_07 + * | | |For P-384, CURVEN is stored in CRYPTO_ECC_N_00~CRYPTO_ECC_N_11 + * | | |For P-521, CURVEN is stored in CRYPTO_ECC_N_00~CRYPTO_ECC_N_16 + * @var CRYPTO_T::ECC_N_02 + * Offset: 0x9C0 ECC the Parameter CURVEN Word2 of Elliptic Curve + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[31:0] |CURVEN |ECC the Parameter CURVEN Value of Elliptic Curve + * | | |In GF(p), CURVEN is the prime p. + * | | |In GF(2m), CURVEN is the irreducible polynomial. + * | | |For B-163 or K-163, CURVEN is stored in CRYPTO_ECC_N_00~CRYPTO_ECC_N_05 + * | | |For B-233 or K-233, CURVEN is stored in CRYPTO_ECC_N_00~CRYPTO_ECC_N_07 + * | | |For B-283 or K-283, CURVEN is stored in CRYPTO_ECC_N_00~CRYPTO_ECC_N_08 + * | | |For B-409 or K-409, CURVEN is stored in CRYPTO_ECC_N_00~CRYPTO_ECC_N_12 + * | | |For B-571 or K-571, CURVEN is stored in CRYPTO_ECC_N_00~CRYPTO_ECC_N_17 + * | | |For P-192, CURVEN is stored in CRYPTO_ECC_N_00~CRYPTO_ECC_N_05 + * | | |For P-224, CURVEN is stored in CRYPTO_ECC_N_00~CRYPTO_ECC_N_06 + * | | |For P-256 or SM2, CURVEN is stored in CRYPTO_ECC_N_00~CRYPTO_ECC_N_07 + * | | |For P-384, CURVEN is stored in CRYPTO_ECC_N_00~CRYPTO_ECC_N_11 + * | | |For P-521, CURVEN is stored in CRYPTO_ECC_N_00~CRYPTO_ECC_N_16 + * @var CRYPTO_T::ECC_N_03 + * Offset: 0x9C4 ECC the Parameter CURVEN Word3 of Elliptic Curve + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[31:0] |CURVEN |ECC the Parameter CURVEN Value of Elliptic Curve + * | | |In GF(p), CURVEN is the prime p. + * | | |In GF(2m), CURVEN is the irreducible polynomial. + * | | |For B-163 or K-163, CURVEN is stored in CRYPTO_ECC_N_00~CRYPTO_ECC_N_05 + * | | |For B-233 or K-233, CURVEN is stored in CRYPTO_ECC_N_00~CRYPTO_ECC_N_07 + * | | |For B-283 or K-283, CURVEN is stored in CRYPTO_ECC_N_00~CRYPTO_ECC_N_08 + * | | |For B-409 or K-409, CURVEN is stored in CRYPTO_ECC_N_00~CRYPTO_ECC_N_12 + * | | |For B-571 or K-571, CURVEN is stored in CRYPTO_ECC_N_00~CRYPTO_ECC_N_17 + * | | |For P-192, CURVEN is stored in CRYPTO_ECC_N_00~CRYPTO_ECC_N_05 + * | | |For P-224, CURVEN is stored in CRYPTO_ECC_N_00~CRYPTO_ECC_N_06 + * | | |For P-256 or SM2, CURVEN is stored in CRYPTO_ECC_N_00~CRYPTO_ECC_N_07 + * | | |For P-384, CURVEN is stored in CRYPTO_ECC_N_00~CRYPTO_ECC_N_11 + * | | |For P-521, CURVEN is stored in CRYPTO_ECC_N_00~CRYPTO_ECC_N_16 + * @var CRYPTO_T::ECC_N_04 + * Offset: 0x9C8 ECC the Parameter CURVEN Word4 of Elliptic Curve + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[31:0] |CURVEN |ECC the Parameter CURVEN Value of Elliptic Curve + * | | |In GF(p), CURVEN is the prime p. + * | | |In GF(2m), CURVEN is the irreducible polynomial. + * | | |For B-163 or K-163, CURVEN is stored in CRYPTO_ECC_N_00~CRYPTO_ECC_N_05 + * | | |For B-233 or K-233, CURVEN is stored in CRYPTO_ECC_N_00~CRYPTO_ECC_N_07 + * | | |For B-283 or K-283, CURVEN is stored in CRYPTO_ECC_N_00~CRYPTO_ECC_N_08 + * | | |For B-409 or K-409, CURVEN is stored in CRYPTO_ECC_N_00~CRYPTO_ECC_N_12 + * | | |For B-571 or K-571, CURVEN is stored in CRYPTO_ECC_N_00~CRYPTO_ECC_N_17 + * | | |For P-192, CURVEN is stored in CRYPTO_ECC_N_00~CRYPTO_ECC_N_05 + * | | |For P-224, CURVEN is stored in CRYPTO_ECC_N_00~CRYPTO_ECC_N_06 + * | | |For P-256 or SM2, CURVEN is stored in CRYPTO_ECC_N_00~CRYPTO_ECC_N_07 + * | | |For P-384, CURVEN is stored in CRYPTO_ECC_N_00~CRYPTO_ECC_N_11 + * | | |For P-521, CURVEN is stored in CRYPTO_ECC_N_00~CRYPTO_ECC_N_16 + * @var CRYPTO_T::ECC_N_05 + * Offset: 0x9CC ECC the Parameter CURVEN Word5 of Elliptic Curve + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[31:0] |CURVEN |ECC the Parameter CURVEN Value of Elliptic Curve + * | | |In GF(p), CURVEN is the prime p. + * | | |In GF(2m), CURVEN is the irreducible polynomial. + * | | |For B-163 or K-163, CURVEN is stored in CRYPTO_ECC_N_00~CRYPTO_ECC_N_05 + * | | |For B-233 or K-233, CURVEN is stored in CRYPTO_ECC_N_00~CRYPTO_ECC_N_07 + * | | |For B-283 or K-283, CURVEN is stored in CRYPTO_ECC_N_00~CRYPTO_ECC_N_08 + * | | |For B-409 or K-409, CURVEN is stored in CRYPTO_ECC_N_00~CRYPTO_ECC_N_12 + * | | |For B-571 or K-571, CURVEN is stored in CRYPTO_ECC_N_00~CRYPTO_ECC_N_17 + * | | |For P-192, CURVEN is stored in CRYPTO_ECC_N_00~CRYPTO_ECC_N_05 + * | | |For P-224, CURVEN is stored in CRYPTO_ECC_N_00~CRYPTO_ECC_N_06 + * | | |For P-256 or SM2, CURVEN is stored in CRYPTO_ECC_N_00~CRYPTO_ECC_N_07 + * | | |For P-384, CURVEN is stored in CRYPTO_ECC_N_00~CRYPTO_ECC_N_11 + * | | |For P-521, CURVEN is stored in CRYPTO_ECC_N_00~CRYPTO_ECC_N_16 + * @var CRYPTO_T::ECC_N_06 + * Offset: 0x9D0 ECC the Parameter CURVEN Word6 of Elliptic Curve + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[31:0] |CURVEN |ECC the Parameter CURVEN Value of Elliptic Curve + * | | |In GF(p), CURVEN is the prime p. + * | | |In GF(2m), CURVEN is the irreducible polynomial. + * | | |For B-163 or K-163, CURVEN is stored in CRYPTO_ECC_N_00~CRYPTO_ECC_N_05 + * | | |For B-233 or K-233, CURVEN is stored in CRYPTO_ECC_N_00~CRYPTO_ECC_N_07 + * | | |For B-283 or K-283, CURVEN is stored in CRYPTO_ECC_N_00~CRYPTO_ECC_N_08 + * | | |For B-409 or K-409, CURVEN is stored in CRYPTO_ECC_N_00~CRYPTO_ECC_N_12 + * | | |For B-571 or K-571, CURVEN is stored in CRYPTO_ECC_N_00~CRYPTO_ECC_N_17 + * | | |For P-192, CURVEN is stored in CRYPTO_ECC_N_00~CRYPTO_ECC_N_05 + * | | |For P-224, CURVEN is stored in CRYPTO_ECC_N_00~CRYPTO_ECC_N_06 + * | | |For P-256 or SM2, CURVEN is stored in CRYPTO_ECC_N_00~CRYPTO_ECC_N_07 + * | | |For P-384, CURVEN is stored in CRYPTO_ECC_N_00~CRYPTO_ECC_N_11 + * | | |For P-521, CURVEN is stored in CRYPTO_ECC_N_00~CRYPTO_ECC_N_16 + * @var CRYPTO_T::ECC_N_07 + * Offset: 0x9D4 ECC the Parameter CURVEN Word7 of Elliptic Curve + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[31:0] |CURVEN |ECC the Parameter CURVEN Value of Elliptic Curve + * | | |In GF(p), CURVEN is the prime p. + * | | |In GF(2m), CURVEN is the irreducible polynomial. + * | | |For B-163 or K-163, CURVEN is stored in CRYPTO_ECC_N_00~CRYPTO_ECC_N_05 + * | | |For B-233 or K-233, CURVEN is stored in CRYPTO_ECC_N_00~CRYPTO_ECC_N_07 + * | | |For B-283 or K-283, CURVEN is stored in CRYPTO_ECC_N_00~CRYPTO_ECC_N_08 + * | | |For B-409 or K-409, CURVEN is stored in CRYPTO_ECC_N_00~CRYPTO_ECC_N_12 + * | | |For B-571 or K-571, CURVEN is stored in CRYPTO_ECC_N_00~CRYPTO_ECC_N_17 + * | | |For P-192, CURVEN is stored in CRYPTO_ECC_N_00~CRYPTO_ECC_N_05 + * | | |For P-224, CURVEN is stored in CRYPTO_ECC_N_00~CRYPTO_ECC_N_06 + * | | |For P-256 or SM2, CURVEN is stored in CRYPTO_ECC_N_00~CRYPTO_ECC_N_07 + * | | |For P-384, CURVEN is stored in CRYPTO_ECC_N_00~CRYPTO_ECC_N_11 + * | | |For P-521, CURVEN is stored in CRYPTO_ECC_N_00~CRYPTO_ECC_N_16 + * @var CRYPTO_T::ECC_N_08 + * Offset: 0x9D8 ECC the Parameter CURVEN Word8 of Elliptic Curve + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[31:0] |CURVEN |ECC the Parameter CURVEN Value of Elliptic Curve + * | | |In GF(p), CURVEN is the prime p. + * | | |In GF(2m), CURVEN is the irreducible polynomial. + * | | |For B-163 or K-163, CURVEN is stored in CRYPTO_ECC_N_00~CRYPTO_ECC_N_05 + * | | |For B-233 or K-233, CURVEN is stored in CRYPTO_ECC_N_00~CRYPTO_ECC_N_07 + * | | |For B-283 or K-283, CURVEN is stored in CRYPTO_ECC_N_00~CRYPTO_ECC_N_08 + * | | |For B-409 or K-409, CURVEN is stored in CRYPTO_ECC_N_00~CRYPTO_ECC_N_12 + * | | |For B-571 or K-571, CURVEN is stored in CRYPTO_ECC_N_00~CRYPTO_ECC_N_17 + * | | |For P-192, CURVEN is stored in CRYPTO_ECC_N_00~CRYPTO_ECC_N_05 + * | | |For P-224, CURVEN is stored in CRYPTO_ECC_N_00~CRYPTO_ECC_N_06 + * | | |For P-256 or SM2, CURVEN is stored in CRYPTO_ECC_N_00~CRYPTO_ECC_N_07 + * | | |For P-384, CURVEN is stored in CRYPTO_ECC_N_00~CRYPTO_ECC_N_11 + * | | |For P-521, CURVEN is stored in CRYPTO_ECC_N_00~CRYPTO_ECC_N_16 + * @var CRYPTO_T::ECC_N_09 + * Offset: 0x9DC ECC the Parameter CURVEN Word9 of Elliptic Curve + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[31:0] |CURVEN |ECC the Parameter CURVEN Value of Elliptic Curve + * | | |In GF(p), CURVEN is the prime p. + * | | |In GF(2m), CURVEN is the irreducible polynomial. + * | | |For B-163 or K-163, CURVEN is stored in CRYPTO_ECC_N_00~CRYPTO_ECC_N_05 + * | | |For B-233 or K-233, CURVEN is stored in CRYPTO_ECC_N_00~CRYPTO_ECC_N_07 + * | | |For B-283 or K-283, CURVEN is stored in CRYPTO_ECC_N_00~CRYPTO_ECC_N_08 + * | | |For B-409 or K-409, CURVEN is stored in CRYPTO_ECC_N_00~CRYPTO_ECC_N_12 + * | | |For B-571 or K-571, CURVEN is stored in CRYPTO_ECC_N_00~CRYPTO_ECC_N_17 + * | | |For P-192, CURVEN is stored in CRYPTO_ECC_N_00~CRYPTO_ECC_N_05 + * | | |For P-224, CURVEN is stored in CRYPTO_ECC_N_00~CRYPTO_ECC_N_06 + * | | |For P-256 or SM2, CURVEN is stored in CRYPTO_ECC_N_00~CRYPTO_ECC_N_07 + * | | |For P-384, CURVEN is stored in CRYPTO_ECC_N_00~CRYPTO_ECC_N_11 + * | | |For P-521, CURVEN is stored in CRYPTO_ECC_N_00~CRYPTO_ECC_N_16 + * @var CRYPTO_T::ECC_N_10 + * Offset: 0x9E0 ECC the Parameter CURVEN Word10 of Elliptic Curve + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[31:0] |CURVEN |ECC the Parameter CURVEN Value of Elliptic Curve + * | | |In GF(p), CURVEN is the prime p. + * | | |In GF(2m), CURVEN is the irreducible polynomial. + * | | |For B-163 or K-163, CURVEN is stored in CRYPTO_ECC_N_00~CRYPTO_ECC_N_05 + * | | |For B-233 or K-233, CURVEN is stored in CRYPTO_ECC_N_00~CRYPTO_ECC_N_07 + * | | |For B-283 or K-283, CURVEN is stored in CRYPTO_ECC_N_00~CRYPTO_ECC_N_08 + * | | |For B-409 or K-409, CURVEN is stored in CRYPTO_ECC_N_00~CRYPTO_ECC_N_12 + * | | |For B-571 or K-571, CURVEN is stored in CRYPTO_ECC_N_00~CRYPTO_ECC_N_17 + * | | |For P-192, CURVEN is stored in CRYPTO_ECC_N_00~CRYPTO_ECC_N_05 + * | | |For P-224, CURVEN is stored in CRYPTO_ECC_N_00~CRYPTO_ECC_N_06 + * | | |For P-256 or SM2, CURVEN is stored in CRYPTO_ECC_N_00~CRYPTO_ECC_N_07 + * | | |For P-384, CURVEN is stored in CRYPTO_ECC_N_00~CRYPTO_ECC_N_11 + * | | |For P-521, CURVEN is stored in CRYPTO_ECC_N_00~CRYPTO_ECC_N_16 + * @var CRYPTO_T::ECC_N_11 + * Offset: 0x9E4 ECC the Parameter CURVEN Word11 of Elliptic Curve + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[31:0] |CURVEN |ECC the Parameter CURVEN Value of Elliptic Curve + * | | |In GF(p), CURVEN is the prime p. + * | | |In GF(2m), CURVEN is the irreducible polynomial. + * | | |For B-163 or K-163, CURVEN is stored in CRYPTO_ECC_N_00~CRYPTO_ECC_N_05 + * | | |For B-233 or K-233, CURVEN is stored in CRYPTO_ECC_N_00~CRYPTO_ECC_N_07 + * | | |For B-283 or K-283, CURVEN is stored in CRYPTO_ECC_N_00~CRYPTO_ECC_N_08 + * | | |For B-409 or K-409, CURVEN is stored in CRYPTO_ECC_N_00~CRYPTO_ECC_N_12 + * | | |For B-571 or K-571, CURVEN is stored in CRYPTO_ECC_N_00~CRYPTO_ECC_N_17 + * | | |For P-192, CURVEN is stored in CRYPTO_ECC_N_00~CRYPTO_ECC_N_05 + * | | |For P-224, CURVEN is stored in CRYPTO_ECC_N_00~CRYPTO_ECC_N_06 + * | | |For P-256 or SM2, CURVEN is stored in CRYPTO_ECC_N_00~CRYPTO_ECC_N_07 + * | | |For P-384, CURVEN is stored in CRYPTO_ECC_N_00~CRYPTO_ECC_N_11 + * | | |For P-521, CURVEN is stored in CRYPTO_ECC_N_00~CRYPTO_ECC_N_16 + * @var CRYPTO_T::ECC_N_12 + * Offset: 0x9E8 ECC the Parameter CURVEN Word12 of Elliptic Curve + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[31:0] |CURVEN |ECC the Parameter CURVEN Value of Elliptic Curve + * | | |In GF(p), CURVEN is the prime p. + * | | |In GF(2m), CURVEN is the irreducible polynomial. + * | | |For B-163 or K-163, CURVEN is stored in CRYPTO_ECC_N_00~CRYPTO_ECC_N_05 + * | | |For B-233 or K-233, CURVEN is stored in CRYPTO_ECC_N_00~CRYPTO_ECC_N_07 + * | | |For B-283 or K-283, CURVEN is stored in CRYPTO_ECC_N_00~CRYPTO_ECC_N_08 + * | | |For B-409 or K-409, CURVEN is stored in CRYPTO_ECC_N_00~CRYPTO_ECC_N_12 + * | | |For B-571 or K-571, CURVEN is stored in CRYPTO_ECC_N_00~CRYPTO_ECC_N_17 + * | | |For P-192, CURVEN is stored in CRYPTO_ECC_N_00~CRYPTO_ECC_N_05 + * | | |For P-224, CURVEN is stored in CRYPTO_ECC_N_00~CRYPTO_ECC_N_06 + * | | |For P-256 or SM2, CURVEN is stored in CRYPTO_ECC_N_00~CRYPTO_ECC_N_07 + * | | |For P-384, CURVEN is stored in CRYPTO_ECC_N_00~CRYPTO_ECC_N_11 + * | | |For P-521, CURVEN is stored in CRYPTO_ECC_N_00~CRYPTO_ECC_N_16 + * @var CRYPTO_T::ECC_N_13 + * Offset: 0x9EC ECC the Parameter CURVEN Word13 of Elliptic Curve + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[31:0] |CURVEN |ECC the Parameter CURVEN Value of Elliptic Curve + * | | |In GF(p), CURVEN is the prime p. + * | | |In GF(2m), CURVEN is the irreducible polynomial. + * | | |For B-163 or K-163, CURVEN is stored in CRYPTO_ECC_N_00~CRYPTO_ECC_N_05 + * | | |For B-233 or K-233, CURVEN is stored in CRYPTO_ECC_N_00~CRYPTO_ECC_N_07 + * | | |For B-283 or K-283, CURVEN is stored in CRYPTO_ECC_N_00~CRYPTO_ECC_N_08 + * | | |For B-409 or K-409, CURVEN is stored in CRYPTO_ECC_N_00~CRYPTO_ECC_N_12 + * | | |For B-571 or K-571, CURVEN is stored in CRYPTO_ECC_N_00~CRYPTO_ECC_N_17 + * | | |For P-192, CURVEN is stored in CRYPTO_ECC_N_00~CRYPTO_ECC_N_05 + * | | |For P-224, CURVEN is stored in CRYPTO_ECC_N_00~CRYPTO_ECC_N_06 + * | | |For P-256 or SM2, CURVEN is stored in CRYPTO_ECC_N_00~CRYPTO_ECC_N_07 + * | | |For P-384, CURVEN is stored in CRYPTO_ECC_N_00~CRYPTO_ECC_N_11 + * | | |For P-521, CURVEN is stored in CRYPTO_ECC_N_00~CRYPTO_ECC_N_16 + * @var CRYPTO_T::ECC_N_14 + * Offset: 0x9F0 ECC the Parameter CURVEN Word14 of Elliptic Curve + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[31:0] |CURVEN |ECC the Parameter CURVEN Value of Elliptic Curve + * | | |In GF(p), CURVEN is the prime p. + * | | |In GF(2m), CURVEN is the irreducible polynomial. + * | | |For B-163 or K-163, CURVEN is stored in CRYPTO_ECC_N_00~CRYPTO_ECC_N_05 + * | | |For B-233 or K-233, CURVEN is stored in CRYPTO_ECC_N_00~CRYPTO_ECC_N_07 + * | | |For B-283 or K-283, CURVEN is stored in CRYPTO_ECC_N_00~CRYPTO_ECC_N_08 + * | | |For B-409 or K-409, CURVEN is stored in CRYPTO_ECC_N_00~CRYPTO_ECC_N_12 + * | | |For B-571 or K-571, CURVEN is stored in CRYPTO_ECC_N_00~CRYPTO_ECC_N_17 + * | | |For P-192, CURVEN is stored in CRYPTO_ECC_N_00~CRYPTO_ECC_N_05 + * | | |For P-224, CURVEN is stored in CRYPTO_ECC_N_00~CRYPTO_ECC_N_06 + * | | |For P-256 or SM2, CURVEN is stored in CRYPTO_ECC_N_00~CRYPTO_ECC_N_07 + * | | |For P-384, CURVEN is stored in CRYPTO_ECC_N_00~CRYPTO_ECC_N_11 + * | | |For P-521, CURVEN is stored in CRYPTO_ECC_N_00~CRYPTO_ECC_N_16 + * @var CRYPTO_T::ECC_N_15 + * Offset: 0x9F4 ECC the Parameter CURVEN Word15 of Elliptic Curve + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[31:0] |CURVEN |ECC the Parameter CURVEN Value of Elliptic Curve + * | | |In GF(p), CURVEN is the prime p. + * | | |In GF(2m), CURVEN is the irreducible polynomial. + * | | |For B-163 or K-163, CURVEN is stored in CRYPTO_ECC_N_00~CRYPTO_ECC_N_05 + * | | |For B-233 or K-233, CURVEN is stored in CRYPTO_ECC_N_00~CRYPTO_ECC_N_07 + * | | |For B-283 or K-283, CURVEN is stored in CRYPTO_ECC_N_00~CRYPTO_ECC_N_08 + * | | |For B-409 or K-409, CURVEN is stored in CRYPTO_ECC_N_00~CRYPTO_ECC_N_12 + * | | |For B-571 or K-571, CURVEN is stored in CRYPTO_ECC_N_00~CRYPTO_ECC_N_17 + * | | |For P-192, CURVEN is stored in CRYPTO_ECC_N_00~CRYPTO_ECC_N_05 + * | | |For P-224, CURVEN is stored in CRYPTO_ECC_N_00~CRYPTO_ECC_N_06 + * | | |For P-256 or SM2, CURVEN is stored in CRYPTO_ECC_N_00~CRYPTO_ECC_N_07 + * | | |For P-384, CURVEN is stored in CRYPTO_ECC_N_00~CRYPTO_ECC_N_11 + * | | |For P-521, CURVEN is stored in CRYPTO_ECC_N_00~CRYPTO_ECC_N_16 + * @var CRYPTO_T::ECC_N_16 + * Offset: 0x9F8 ECC the Parameter CURVEN Word16 of Elliptic Curve + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[31:0] |CURVEN |ECC the Parameter CURVEN Value of Elliptic Curve + * | | |In GF(p), CURVEN is the prime p. + * | | |In GF(2m), CURVEN is the irreducible polynomial. + * | | |For B-163 or K-163, CURVEN is stored in CRYPTO_ECC_N_00~CRYPTO_ECC_N_05 + * | | |For B-233 or K-233, CURVEN is stored in CRYPTO_ECC_N_00~CRYPTO_ECC_N_07 + * | | |For B-283 or K-283, CURVEN is stored in CRYPTO_ECC_N_00~CRYPTO_ECC_N_08 + * | | |For B-409 or K-409, CURVEN is stored in CRYPTO_ECC_N_00~CRYPTO_ECC_N_12 + * | | |For B-571 or K-571, CURVEN is stored in CRYPTO_ECC_N_00~CRYPTO_ECC_N_17 + * | | |For P-192, CURVEN is stored in CRYPTO_ECC_N_00~CRYPTO_ECC_N_05 + * | | |For P-224, CURVEN is stored in CRYPTO_ECC_N_00~CRYPTO_ECC_N_06 + * | | |For P-256 or SM2, CURVEN is stored in CRYPTO_ECC_N_00~CRYPTO_ECC_N_07 + * | | |For P-384, CURVEN is stored in CRYPTO_ECC_N_00~CRYPTO_ECC_N_11 + * | | |For P-521, CURVEN is stored in CRYPTO_ECC_N_00~CRYPTO_ECC_N_16 + * @var CRYPTO_T::ECC_N_17 + * Offset: 0x9FC ECC the Parameter CURVEN Word17 of Elliptic Curve + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[31:0] |CURVEN |ECC the Parameter CURVEN Value of Elliptic Curve + * | | |In GF(p), CURVEN is the prime p. + * | | |In GF(2m), CURVEN is the irreducible polynomial. + * | | |For B-163 or K-163, CURVEN is stored in CRYPTO_ECC_N_00~CRYPTO_ECC_N_05 + * | | |For B-233 or K-233, CURVEN is stored in CRYPTO_ECC_N_00~CRYPTO_ECC_N_07 + * | | |For B-283 or K-283, CURVEN is stored in CRYPTO_ECC_N_00~CRYPTO_ECC_N_08 + * | | |For B-409 or K-409, CURVEN is stored in CRYPTO_ECC_N_00~CRYPTO_ECC_N_12 + * | | |For B-571 or K-571, CURVEN is stored in CRYPTO_ECC_N_00~CRYPTO_ECC_N_17 + * | | |For P-192, CURVEN is stored in CRYPTO_ECC_N_00~CRYPTO_ECC_N_05 + * | | |For P-224, CURVEN is stored in CRYPTO_ECC_N_00~CRYPTO_ECC_N_06 + * | | |For P-256 or SM2, CURVEN is stored in CRYPTO_ECC_N_00~CRYPTO_ECC_N_07 + * | | |For P-384, CURVEN is stored in CRYPTO_ECC_N_00~CRYPTO_ECC_N_11 + * | | |For P-521, CURVEN is stored in CRYPTO_ECC_N_00~CRYPTO_ECC_N_16 + * @var CRYPTO_T::ECC_K_00 + * Offset: 0xA00 ECC the Scalar SCALARK Word0 of Point Multiplication + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[31:0] |SCALARK |ECC the Scalar SCALARK Value of Point Multiplication + * | | |Because the SCALARK usually stores the private key, ECC accelerator do not allow to read the register SCALARK. + * | | |For B-163 or K-163, SCALARK is stored in CRYPTO_ECC_K_00~CRYPTO_ECC_K_05 + * | | |For B-233 or K-233, SCALARK is stored in CRYPTO_ECC_K_00~CRYPTO_ECC_K_07 + * | | |For B-283 or K-283, SCALARK is stored in CRYPTO_ECC_K_00~CRYPTO_ECC_K_08 + * | | |For B-409 or K-409, SCALARK is stored in CRYPTO_ECC_K_00~CRYPTO_ECC_K_12 + * | | |For B-571 or K-571, SCALARK is stored in CRYPTO_ECC_K_00~CRYPTO_ECC_K_17 + * | | |For P-192, SCALARK is stored in CRYPTO_ECC_K_00~CRYPTO_ECC_K_05 + * | | |For P-224, SCALARK is stored in CRYPTO_ECC_K_00~CRYPTO_ECC_K_06 + * | | |For P-256 or SM2, SCALARK is stored in CRYPTO_ECC_K_00~CRYPTO_ECC_K_07 + * | | |For P-384, SCALARK is stored in CRYPTO_ECC_K_00~CRYPTO_ECC_K_11 + * | | |For P-521, SCALARK is stored in CRYPTO_ECC_K_00~CRYPTO_ECC_K_16 + * @var CRYPTO_T::ECC_K_01 + * Offset: 0xA04 ECC the Scalar SCALARK Word1 of Point Multiplication + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[31:0] |SCALARK |ECC the Scalar SCALARK Value of Point Multiplication + * | | |Because the SCALARK usually stores the private key, ECC accelerator do not allow to read the register SCALARK. + * | | |For B-163 or K-163, SCALARK is stored in CRYPTO_ECC_K_00~CRYPTO_ECC_K_05 + * | | |For B-233 or K-233, SCALARK is stored in CRYPTO_ECC_K_00~CRYPTO_ECC_K_07 + * | | |For B-283 or K-283, SCALARK is stored in CRYPTO_ECC_K_00~CRYPTO_ECC_K_08 + * | | |For B-409 or K-409, SCALARK is stored in CRYPTO_ECC_K_00~CRYPTO_ECC_K_12 + * | | |For B-571 or K-571, SCALARK is stored in CRYPTO_ECC_K_00~CRYPTO_ECC_K_17 + * | | |For P-192, SCALARK is stored in CRYPTO_ECC_K_00~CRYPTO_ECC_K_05 + * | | |For P-224, SCALARK is stored in CRYPTO_ECC_K_00~CRYPTO_ECC_K_06 + * | | |For P-256 or SM2, SCALARK is stored in CRYPTO_ECC_K_00~CRYPTO_ECC_K_07 + * | | |For P-384, SCALARK is stored in CRYPTO_ECC_K_00~CRYPTO_ECC_K_11 + * | | |For P-521, SCALARK is stored in CRYPTO_ECC_K_00~CRYPTO_ECC_K_16 + * @var CRYPTO_T::ECC_K_02 + * Offset: 0xA08 ECC the Scalar SCALARK Word2 of Point Multiplication + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[31:0] |SCALARK |ECC the Scalar SCALARK Value of Point Multiplication + * | | |Because the SCALARK usually stores the private key, ECC accelerator do not allow to read the register SCALARK. + * | | |For B-163 or K-163, SCALARK is stored in CRYPTO_ECC_K_00~CRYPTO_ECC_K_05 + * | | |For B-233 or K-233, SCALARK is stored in CRYPTO_ECC_K_00~CRYPTO_ECC_K_07 + * | | |For B-283 or K-283, SCALARK is stored in CRYPTO_ECC_K_00~CRYPTO_ECC_K_08 + * | | |For B-409 or K-409, SCALARK is stored in CRYPTO_ECC_K_00~CRYPTO_ECC_K_12 + * | | |For B-571 or K-571, SCALARK is stored in CRYPTO_ECC_K_00~CRYPTO_ECC_K_17 + * | | |For P-192, SCALARK is stored in CRYPTO_ECC_K_00~CRYPTO_ECC_K_05 + * | | |For P-224, SCALARK is stored in CRYPTO_ECC_K_00~CRYPTO_ECC_K_06 + * | | |For P-256 or SM2, SCALARK is stored in CRYPTO_ECC_K_00~CRYPTO_ECC_K_07 + * | | |For P-384, SCALARK is stored in CRYPTO_ECC_K_00~CRYPTO_ECC_K_11 + * | | |For P-521, SCALARK is stored in CRYPTO_ECC_K_00~CRYPTO_ECC_K_16 + * @var CRYPTO_T::ECC_K_03 + * Offset: 0xA0C ECC the Scalar SCALARK Word3 of Point Multiplication + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[31:0] |SCALARK |ECC the Scalar SCALARK Value of Point Multiplication + * | | |Because the SCALARK usually stores the private key, ECC accelerator do not allow to read the register SCALARK. + * | | |For B-163 or K-163, SCALARK is stored in CRYPTO_ECC_K_00~CRYPTO_ECC_K_05 + * | | |For B-233 or K-233, SCALARK is stored in CRYPTO_ECC_K_00~CRYPTO_ECC_K_07 + * | | |For B-283 or K-283, SCALARK is stored in CRYPTO_ECC_K_00~CRYPTO_ECC_K_08 + * | | |For B-409 or K-409, SCALARK is stored in CRYPTO_ECC_K_00~CRYPTO_ECC_K_12 + * | | |For B-571 or K-571, SCALARK is stored in CRYPTO_ECC_K_00~CRYPTO_ECC_K_17 + * | | |For P-192, SCALARK is stored in CRYPTO_ECC_K_00~CRYPTO_ECC_K_05 + * | | |For P-224, SCALARK is stored in CRYPTO_ECC_K_00~CRYPTO_ECC_K_06 + * | | |For P-256 or SM2, SCALARK is stored in CRYPTO_ECC_K_00~CRYPTO_ECC_K_07 + * | | |For P-384, SCALARK is stored in CRYPTO_ECC_K_00~CRYPTO_ECC_K_11 + * | | |For P-521, SCALARK is stored in CRYPTO_ECC_K_00~CRYPTO_ECC_K_16 + * @var CRYPTO_T::ECC_K_04 + * Offset: 0xA10 ECC the Scalar SCALARK Word4 of Point Multiplication + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[31:0] |SCALARK |ECC the Scalar SCALARK Value of Point Multiplication + * | | |Because the SCALARK usually stores the private key, ECC accelerator do not allow to read the register SCALARK. + * | | |For B-163 or K-163, SCALARK is stored in CRYPTO_ECC_K_00~CRYPTO_ECC_K_05 + * | | |For B-233 or K-233, SCALARK is stored in CRYPTO_ECC_K_00~CRYPTO_ECC_K_07 + * | | |For B-283 or K-283, SCALARK is stored in CRYPTO_ECC_K_00~CRYPTO_ECC_K_08 + * | | |For B-409 or K-409, SCALARK is stored in CRYPTO_ECC_K_00~CRYPTO_ECC_K_12 + * | | |For B-571 or K-571, SCALARK is stored in CRYPTO_ECC_K_00~CRYPTO_ECC_K_17 + * | | |For P-192, SCALARK is stored in CRYPTO_ECC_K_00~CRYPTO_ECC_K_05 + * | | |For P-224, SCALARK is stored in CRYPTO_ECC_K_00~CRYPTO_ECC_K_06 + * | | |For P-256 or SM2, SCALARK is stored in CRYPTO_ECC_K_00~CRYPTO_ECC_K_07 + * | | |For P-384, SCALARK is stored in CRYPTO_ECC_K_00~CRYPTO_ECC_K_11 + * | | |For P-521, SCALARK is stored in CRYPTO_ECC_K_00~CRYPTO_ECC_K_16 + * @var CRYPTO_T::ECC_K_05 + * Offset: 0xA14 ECC the Scalar SCALARK Word5 of Point Multiplication + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[31:0] |SCALARK |ECC the Scalar SCALARK Value of Point Multiplication + * | | |Because the SCALARK usually stores the private key, ECC accelerator do not allow to read the register SCALARK. + * | | |For B-163 or K-163, SCALARK is stored in CRYPTO_ECC_K_00~CRYPTO_ECC_K_05 + * | | |For B-233 or K-233, SCALARK is stored in CRYPTO_ECC_K_00~CRYPTO_ECC_K_07 + * | | |For B-283 or K-283, SCALARK is stored in CRYPTO_ECC_K_00~CRYPTO_ECC_K_08 + * | | |For B-409 or K-409, SCALARK is stored in CRYPTO_ECC_K_00~CRYPTO_ECC_K_12 + * | | |For B-571 or K-571, SCALARK is stored in CRYPTO_ECC_K_00~CRYPTO_ECC_K_17 + * | | |For P-192, SCALARK is stored in CRYPTO_ECC_K_00~CRYPTO_ECC_K_05 + * | | |For P-224, SCALARK is stored in CRYPTO_ECC_K_00~CRYPTO_ECC_K_06 + * | | |For P-256 or SM2, SCALARK is stored in CRYPTO_ECC_K_00~CRYPTO_ECC_K_07 + * | | |For P-384, SCALARK is stored in CRYPTO_ECC_K_00~CRYPTO_ECC_K_11 + * | | |For P-521, SCALARK is stored in CRYPTO_ECC_K_00~CRYPTO_ECC_K_16 + * @var CRYPTO_T::ECC_K_06 + * Offset: 0xA18 ECC the Scalar SCALARK Word6 of Point Multiplication + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[31:0] |SCALARK |ECC the Scalar SCALARK Value of Point Multiplication + * | | |Because the SCALARK usually stores the private key, ECC accelerator do not allow to read the register SCALARK. + * | | |For B-163 or K-163, SCALARK is stored in CRYPTO_ECC_K_00~CRYPTO_ECC_K_05 + * | | |For B-233 or K-233, SCALARK is stored in CRYPTO_ECC_K_00~CRYPTO_ECC_K_07 + * | | |For B-283 or K-283, SCALARK is stored in CRYPTO_ECC_K_00~CRYPTO_ECC_K_08 + * | | |For B-409 or K-409, SCALARK is stored in CRYPTO_ECC_K_00~CRYPTO_ECC_K_12 + * | | |For B-571 or K-571, SCALARK is stored in CRYPTO_ECC_K_00~CRYPTO_ECC_K_17 + * | | |For P-192, SCALARK is stored in CRYPTO_ECC_K_00~CRYPTO_ECC_K_05 + * | | |For P-224, SCALARK is stored in CRYPTO_ECC_K_00~CRYPTO_ECC_K_06 + * | | |For P-256 or SM2, SCALARK is stored in CRYPTO_ECC_K_00~CRYPTO_ECC_K_07 + * | | |For P-384, SCALARK is stored in CRYPTO_ECC_K_00~CRYPTO_ECC_K_11 + * | | |For P-521, SCALARK is stored in CRYPTO_ECC_K_00~CRYPTO_ECC_K_16 + * @var CRYPTO_T::ECC_K_07 + * Offset: 0xA1C ECC the Scalar SCALARK Word7 of Point Multiplication + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[31:0] |SCALARK |ECC the Scalar SCALARK Value of Point Multiplication + * | | |Because the SCALARK usually stores the private key, ECC accelerator do not allow to read the register SCALARK. + * | | |For B-163 or K-163, SCALARK is stored in CRYPTO_ECC_K_00~CRYPTO_ECC_K_05 + * | | |For B-233 or K-233, SCALARK is stored in CRYPTO_ECC_K_00~CRYPTO_ECC_K_07 + * | | |For B-283 or K-283, SCALARK is stored in CRYPTO_ECC_K_00~CRYPTO_ECC_K_08 + * | | |For B-409 or K-409, SCALARK is stored in CRYPTO_ECC_K_00~CRYPTO_ECC_K_12 + * | | |For B-571 or K-571, SCALARK is stored in CRYPTO_ECC_K_00~CRYPTO_ECC_K_17 + * | | |For P-192, SCALARK is stored in CRYPTO_ECC_K_00~CRYPTO_ECC_K_05 + * | | |For P-224, SCALARK is stored in CRYPTO_ECC_K_00~CRYPTO_ECC_K_06 + * | | |For P-256 or SM2, SCALARK is stored in CRYPTO_ECC_K_00~CRYPTO_ECC_K_07 + * | | |For P-384, SCALARK is stored in CRYPTO_ECC_K_00~CRYPTO_ECC_K_11 + * | | |For P-521, SCALARK is stored in CRYPTO_ECC_K_00~CRYPTO_ECC_K_16 + * @var CRYPTO_T::ECC_K_08 + * Offset: 0xA20 ECC the Scalar SCALARK Word8 of Point Multiplication + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[31:0] |SCALARK |ECC the Scalar SCALARK Value of Point Multiplication + * | | |Because the SCALARK usually stores the private key, ECC accelerator do not allow to read the register SCALARK. + * | | |For B-163 or K-163, SCALARK is stored in CRYPTO_ECC_K_00~CRYPTO_ECC_K_05 + * | | |For B-233 or K-233, SCALARK is stored in CRYPTO_ECC_K_00~CRYPTO_ECC_K_07 + * | | |For B-283 or K-283, SCALARK is stored in CRYPTO_ECC_K_00~CRYPTO_ECC_K_08 + * | | |For B-409 or K-409, SCALARK is stored in CRYPTO_ECC_K_00~CRYPTO_ECC_K_12 + * | | |For B-571 or K-571, SCALARK is stored in CRYPTO_ECC_K_00~CRYPTO_ECC_K_17 + * | | |For P-192, SCALARK is stored in CRYPTO_ECC_K_00~CRYPTO_ECC_K_05 + * | | |For P-224, SCALARK is stored in CRYPTO_ECC_K_00~CRYPTO_ECC_K_06 + * | | |For P-256 or SM2, SCALARK is stored in CRYPTO_ECC_K_00~CRYPTO_ECC_K_07 + * | | |For P-384, SCALARK is stored in CRYPTO_ECC_K_00~CRYPTO_ECC_K_11 + * | | |For P-521, SCALARK is stored in CRYPTO_ECC_K_00~CRYPTO_ECC_K_16 + * @var CRYPTO_T::ECC_K_09 + * Offset: 0xA24 ECC the Scalar SCALARK Word9 of Point Multiplication + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[31:0] |SCALARK |ECC the Scalar SCALARK Value of Point Multiplication + * | | |Because the SCALARK usually stores the private key, ECC accelerator do not allow to read the register SCALARK. + * | | |For B-163 or K-163, SCALARK is stored in CRYPTO_ECC_K_00~CRYPTO_ECC_K_05 + * | | |For B-233 or K-233, SCALARK is stored in CRYPTO_ECC_K_00~CRYPTO_ECC_K_07 + * | | |For B-283 or K-283, SCALARK is stored in CRYPTO_ECC_K_00~CRYPTO_ECC_K_08 + * | | |For B-409 or K-409, SCALARK is stored in CRYPTO_ECC_K_00~CRYPTO_ECC_K_12 + * | | |For B-571 or K-571, SCALARK is stored in CRYPTO_ECC_K_00~CRYPTO_ECC_K_17 + * | | |For P-192, SCALARK is stored in CRYPTO_ECC_K_00~CRYPTO_ECC_K_05 + * | | |For P-224, SCALARK is stored in CRYPTO_ECC_K_00~CRYPTO_ECC_K_06 + * | | |For P-256 or SM2, SCALARK is stored in CRYPTO_ECC_K_00~CRYPTO_ECC_K_07 + * | | |For P-384, SCALARK is stored in CRYPTO_ECC_K_00~CRYPTO_ECC_K_11 + * | | |For P-521, SCALARK is stored in CRYPTO_ECC_K_00~CRYPTO_ECC_K_16 + * @var CRYPTO_T::ECC_K_10 + * Offset: 0xA28 ECC the Scalar SCALARK Word10 of Point Multiplication + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[31:0] |SCALARK |ECC the Scalar SCALARK Value of Point Multiplication + * | | |Because the SCALARK usually stores the private key, ECC accelerator do not allow to read the register SCALARK. + * | | |For B-163 or K-163, SCALARK is stored in CRYPTO_ECC_K_00~CRYPTO_ECC_K_05 + * | | |For B-233 or K-233, SCALARK is stored in CRYPTO_ECC_K_00~CRYPTO_ECC_K_07 + * | | |For B-283 or K-283, SCALARK is stored in CRYPTO_ECC_K_00~CRYPTO_ECC_K_08 + * | | |For B-409 or K-409, SCALARK is stored in CRYPTO_ECC_K_00~CRYPTO_ECC_K_12 + * | | |For B-571 or K-571, SCALARK is stored in CRYPTO_ECC_K_00~CRYPTO_ECC_K_17 + * | | |For P-192, SCALARK is stored in CRYPTO_ECC_K_00~CRYPTO_ECC_K_05 + * | | |For P-224, SCALARK is stored in CRYPTO_ECC_K_00~CRYPTO_ECC_K_06 + * | | |For P-256 or SM2, SCALARK is stored in CRYPTO_ECC_K_00~CRYPTO_ECC_K_07 + * | | |For P-384, SCALARK is stored in CRYPTO_ECC_K_00~CRYPTO_ECC_K_11 + * | | |For P-521, SCALARK is stored in CRYPTO_ECC_K_00~CRYPTO_ECC_K_16 + * @var CRYPTO_T::ECC_K_11 + * Offset: 0xA2C ECC the Scalar SCALARK Word11 of Point Multiplication + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[31:0] |SCALARK |ECC the Scalar SCALARK Value of Point Multiplication + * | | |Because the SCALARK usually stores the private key, ECC accelerator do not allow to read the register SCALARK. + * | | |For B-163 or K-163, SCALARK is stored in CRYPTO_ECC_K_00~CRYPTO_ECC_K_05 + * | | |For B-233 or K-233, SCALARK is stored in CRYPTO_ECC_K_00~CRYPTO_ECC_K_07 + * | | |For B-283 or K-283, SCALARK is stored in CRYPTO_ECC_K_00~CRYPTO_ECC_K_08 + * | | |For B-409 or K-409, SCALARK is stored in CRYPTO_ECC_K_00~CRYPTO_ECC_K_12 + * | | |For B-571 or K-571, SCALARK is stored in CRYPTO_ECC_K_00~CRYPTO_ECC_K_17 + * | | |For P-192, SCALARK is stored in CRYPTO_ECC_K_00~CRYPTO_ECC_K_05 + * | | |For P-224, SCALARK is stored in CRYPTO_ECC_K_00~CRYPTO_ECC_K_06 + * | | |For P-256 or SM2, SCALARK is stored in CRYPTO_ECC_K_00~CRYPTO_ECC_K_07 + * | | |For P-384, SCALARK is stored in CRYPTO_ECC_K_00~CRYPTO_ECC_K_11 + * | | |For P-521, SCALARK is stored in CRYPTO_ECC_K_00~CRYPTO_ECC_K_16 + * @var CRYPTO_T::ECC_K_12 + * Offset: 0xA30 ECC the Scalar SCALARK Word12 of Point Multiplication + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[31:0] |SCALARK |ECC the Scalar SCALARK Value of Point Multiplication + * | | |Because the SCALARK usually stores the private key, ECC accelerator do not allow to read the register SCALARK. + * | | |For B-163 or K-163, SCALARK is stored in CRYPTO_ECC_K_00~CRYPTO_ECC_K_05 + * | | |For B-233 or K-233, SCALARK is stored in CRYPTO_ECC_K_00~CRYPTO_ECC_K_07 + * | | |For B-283 or K-283, SCALARK is stored in CRYPTO_ECC_K_00~CRYPTO_ECC_K_08 + * | | |For B-409 or K-409, SCALARK is stored in CRYPTO_ECC_K_00~CRYPTO_ECC_K_12 + * | | |For B-571 or K-571, SCALARK is stored in CRYPTO_ECC_K_00~CRYPTO_ECC_K_17 + * | | |For P-192, SCALARK is stored in CRYPTO_ECC_K_00~CRYPTO_ECC_K_05 + * | | |For P-224, SCALARK is stored in CRYPTO_ECC_K_00~CRYPTO_ECC_K_06 + * | | |For P-256 or SM2, SCALARK is stored in CRYPTO_ECC_K_00~CRYPTO_ECC_K_07 + * | | |For P-384, SCALARK is stored in CRYPTO_ECC_K_00~CRYPTO_ECC_K_11 + * | | |For P-521, SCALARK is stored in CRYPTO_ECC_K_00~CRYPTO_ECC_K_16 + * @var CRYPTO_T::ECC_K_13 + * Offset: 0xA34 ECC the Scalar SCALARK Word13 of Point Multiplication + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[31:0] |SCALARK |ECC the Scalar SCALARK Value of Point Multiplication + * | | |Because the SCALARK usually stores the private key, ECC accelerator do not allow to read the register SCALARK. + * | | |For B-163 or K-163, SCALARK is stored in CRYPTO_ECC_K_00~CRYPTO_ECC_K_05 + * | | |For B-233 or K-233, SCALARK is stored in CRYPTO_ECC_K_00~CRYPTO_ECC_K_07 + * | | |For B-283 or K-283, SCALARK is stored in CRYPTO_ECC_K_00~CRYPTO_ECC_K_08 + * | | |For B-409 or K-409, SCALARK is stored in CRYPTO_ECC_K_00~CRYPTO_ECC_K_12 + * | | |For B-571 or K-571, SCALARK is stored in CRYPTO_ECC_K_00~CRYPTO_ECC_K_17 + * | | |For P-192, SCALARK is stored in CRYPTO_ECC_K_00~CRYPTO_ECC_K_05 + * | | |For P-224, SCALARK is stored in CRYPTO_ECC_K_00~CRYPTO_ECC_K_06 + * | | |For P-256 or SM2, SCALARK is stored in CRYPTO_ECC_K_00~CRYPTO_ECC_K_07 + * | | |For P-384, SCALARK is stored in CRYPTO_ECC_K_00~CRYPTO_ECC_K_11 + * | | |For P-521, SCALARK is stored in CRYPTO_ECC_K_00~CRYPTO_ECC_K_16 + * @var CRYPTO_T::ECC_K_14 + * Offset: 0xA38 ECC the Scalar SCALARK Word14 of Point Multiplication + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[31:0] |SCALARK |ECC the Scalar SCALARK Value of Point Multiplication + * | | |Because the SCALARK usually stores the private key, ECC accelerator do not allow to read the register SCALARK. + * | | |For B-163 or K-163, SCALARK is stored in CRYPTO_ECC_K_00~CRYPTO_ECC_K_05 + * | | |For B-233 or K-233, SCALARK is stored in CRYPTO_ECC_K_00~CRYPTO_ECC_K_07 + * | | |For B-283 or K-283, SCALARK is stored in CRYPTO_ECC_K_00~CRYPTO_ECC_K_08 + * | | |For B-409 or K-409, SCALARK is stored in CRYPTO_ECC_K_00~CRYPTO_ECC_K_12 + * | | |For B-571 or K-571, SCALARK is stored in CRYPTO_ECC_K_00~CRYPTO_ECC_K_17 + * | | |For P-192, SCALARK is stored in CRYPTO_ECC_K_00~CRYPTO_ECC_K_05 + * | | |For P-224, SCALARK is stored in CRYPTO_ECC_K_00~CRYPTO_ECC_K_06 + * | | |For P-256 or SM2, SCALARK is stored in CRYPTO_ECC_K_00~CRYPTO_ECC_K_07 + * | | |For P-384, SCALARK is stored in CRYPTO_ECC_K_00~CRYPTO_ECC_K_11 + * | | |For P-521, SCALARK is stored in CRYPTO_ECC_K_00~CRYPTO_ECC_K_16 + * @var CRYPTO_T::ECC_K_15 + * Offset: 0xA3C ECC the Scalar SCALARK Word15 of Point Multiplication + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[31:0] |SCALARK |ECC the Scalar SCALARK Value of Point Multiplication + * | | |Because the SCALARK usually stores the private key, ECC accelerator do not allow to read the register SCALARK. + * | | |For B-163 or K-163, SCALARK is stored in CRYPTO_ECC_K_00~CRYPTO_ECC_K_05 + * | | |For B-233 or K-233, SCALARK is stored in CRYPTO_ECC_K_00~CRYPTO_ECC_K_07 + * | | |For B-283 or K-283, SCALARK is stored in CRYPTO_ECC_K_00~CRYPTO_ECC_K_08 + * | | |For B-409 or K-409, SCALARK is stored in CRYPTO_ECC_K_00~CRYPTO_ECC_K_12 + * | | |For B-571 or K-571, SCALARK is stored in CRYPTO_ECC_K_00~CRYPTO_ECC_K_17 + * | | |For P-192, SCALARK is stored in CRYPTO_ECC_K_00~CRYPTO_ECC_K_05 + * | | |For P-224, SCALARK is stored in CRYPTO_ECC_K_00~CRYPTO_ECC_K_06 + * | | |For P-256 or SM2, SCALARK is stored in CRYPTO_ECC_K_00~CRYPTO_ECC_K_07 + * | | |For P-384, SCALARK is stored in CRYPTO_ECC_K_00~CRYPTO_ECC_K_11 + * | | |For P-521, SCALARK is stored in CRYPTO_ECC_K_00~CRYPTO_ECC_K_16 + * @var CRYPTO_T::ECC_K_16 + * Offset: 0xA40 ECC the Scalar SCALARK Word16 of Point Multiplication + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[31:0] |SCALARK |ECC the Scalar SCALARK Value of Point Multiplication + * | | |Because the SCALARK usually stores the private key, ECC accelerator do not allow to read the register SCALARK. + * | | |For B-163 or K-163, SCALARK is stored in CRYPTO_ECC_K_00~CRYPTO_ECC_K_05 + * | | |For B-233 or K-233, SCALARK is stored in CRYPTO_ECC_K_00~CRYPTO_ECC_K_07 + * | | |For B-283 or K-283, SCALARK is stored in CRYPTO_ECC_K_00~CRYPTO_ECC_K_08 + * | | |For B-409 or K-409, SCALARK is stored in CRYPTO_ECC_K_00~CRYPTO_ECC_K_12 + * | | |For B-571 or K-571, SCALARK is stored in CRYPTO_ECC_K_00~CRYPTO_ECC_K_17 + * | | |For P-192, SCALARK is stored in CRYPTO_ECC_K_00~CRYPTO_ECC_K_05 + * | | |For P-224, SCALARK is stored in CRYPTO_ECC_K_00~CRYPTO_ECC_K_06 + * | | |For P-256 or SM2, SCALARK is stored in CRYPTO_ECC_K_00~CRYPTO_ECC_K_07 + * | | |For P-384, SCALARK is stored in CRYPTO_ECC_K_00~CRYPTO_ECC_K_11 + * | | |For P-521, SCALARK is stored in CRYPTO_ECC_K_00~CRYPTO_ECC_K_16 + * @var CRYPTO_T::ECC_K_17 + * Offset: 0xA44 ECC the Scalar SCALARK Word17 of Point Multiplication + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[31:0] |SCALARK |ECC the Scalar SCALARK Value of Point Multiplication + * | | |Because the SCALARK usually stores the private key, ECC accelerator do not allow to read the register SCALARK. + * | | |For B-163 or K-163, SCALARK is stored in CRYPTO_ECC_K_00~CRYPTO_ECC_K_05 + * | | |For B-233 or K-233, SCALARK is stored in CRYPTO_ECC_K_00~CRYPTO_ECC_K_07 + * | | |For B-283 or K-283, SCALARK is stored in CRYPTO_ECC_K_00~CRYPTO_ECC_K_08 + * | | |For B-409 or K-409, SCALARK is stored in CRYPTO_ECC_K_00~CRYPTO_ECC_K_12 + * | | |For B-571 or K-571, SCALARK is stored in CRYPTO_ECC_K_00~CRYPTO_ECC_K_17 + * | | |For P-192, SCALARK is stored in CRYPTO_ECC_K_00~CRYPTO_ECC_K_05 + * | | |For P-224, SCALARK is stored in CRYPTO_ECC_K_00~CRYPTO_ECC_K_06 + * | | |For P-256 or SM2, SCALARK is stored in CRYPTO_ECC_K_00~CRYPTO_ECC_K_07 + * | | |For P-384, SCALARK is stored in CRYPTO_ECC_K_00~CRYPTO_ECC_K_11 + * | | |For P-521, SCALARK is stored in CRYPTO_ECC_K_00~CRYPTO_ECC_K_16 + * @var CRYPTO_T::ECC_SADDR + * Offset: 0xA48 ECC DMA Source Address Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * @var CRYPTO_T::ECC_DADDR + * Offset: 0xA4C ECC DMA Destination Address Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[31:0] |DADDR |ECC DMA Destination Address + * | | |The ECC accelerator supports DMA function to transfer the DATA and PARAMETER between SRAM memory and ECC accelerator + * | | |The DADDR keeps the destination address of the data buffer where output data of ECC engine will be stored + * | | |Based on the destination address, the ECC accelerator can write the result data back to SRAM memory space after the ECC operation is finished + * | | |The start of destination address should be located at word boundary + * | | |That is, bit 1 and 0 of DADDR are ignored + * | | |DADDR can be read and written + * | | |In DMA mode, software must update the CRYPTO_ECC_DADDR before triggering START + * @var CRYPTO_T::ECC_STARTREG + * Offset: 0xA50 ECC Starting Address of Updated Registers + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[31:0] |STARTREG |ECC Starting Address of Updated Registers + * | | |The address of the updated registers that DMA feeds the first data or parameter to ECC engine + * | | |When ECC engine is active, ECC accelerator does not allow users to modify STARTRE.G + * | | |For example, to update input data from register CRYPTO_ECC POINTX1 + * | | |Thus, the value of STARTREG is 0x808. + * @var CRYPTO_T::ECC_WORDCNT + * Offset: 0xA54 ECC DMA Word Count + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[31:0] |WORDCNT |ECC DMA Word Count + * | | |The CRYPTO_ECC_WORDCNT keeps the word count of source data that is for the required input data of ECC accelerator with various operations in DMA mode + * | | |Although CRYPTO_ECC_WORDCNT is 32-bit, the maximum of word count in ECC accelerator is 144 words + * | | |CRYPTO_ECC_WORDCNT can be read and written + * @var CRYPTO_T::RSA_CTL + * Offset: 0xB00 RSA Control Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[0] |START |RSA Accelerator Start + * | | |0 = No effect. + * | | |1 = Start RSA accelerator. BUSY flag will be set. + * | | |This bit is always 0 when it is read back. + * | | |RSA accelerator will ignore this START signal when BUSY flag is 1. + * |[1] |STOP |RSA Accelerator Stop + * | | |0 = No effect. + * | | |1 = Abort RSA accelerator and make it into initial state. + * | | |This bit is always 0 when it is read back. + * | | |Remember to clear RSA interrupt flag after stopping RSA accelerator. + * |[2] |CRT |CRT Enable Control + * | | |0 = CRT Disabled. + * | | |1 = CRT Enabled. + * | | |CRT is only used in decryption with key length 2048, 3072,4096 bits. + * |[3] |CRTBYP |CRT Bypass Enable Control + * | | |0 = CRT Bypass Disabled. + * | | |1 = CRT Bypass Enabled. + * | | |CRT bypass is only used in CRT decryption with the same key. + * | | |Note: If users want to decrypt repeatedly with the same key, they can execute CRT bypass mode after the first time CRT decryption (means the second time to the latest time), but they cannot set CRTBYP to 1 in non-CRT mode. + * |[5:4] |KEYLENG |The Key Length of RSA Operation + * | | |00 = 1024-bits. + * | | |01 = 2048-bits. + * | | |10 = 3072-bits. + * | | |11 = 4096-bits. + * |[8] |SCAP |Side Channel Attack Protection Enable Control + * | | |0 = Side Channel Attack Protection Disabled. + * | | |1 = Side Channel Attack Protection Enabled. + * @var CRYPTO_T::RSA_STS + * Offset: 0xB04 RSA Status Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[0] |BUSY |RSA Accelerator Busy Flag + * | | |0 = The RSA accelerator is idle or finished. + * | | |1 = The RSA accelerator is under processing and protects all registers. + * | | |Remember to clear RSA interrupt flag after RSA accelerator finished. + * |[1] |DMABUSY |RSA DMA Busy Flag + * | | |0 = RSA DMA is idle or finished. + * | | |1 = RSA DMA is busy. + * |[16] |BUSERR |RSA DMA Access Bus Error Flag + * | | |0 = No error. + * | | |1 = Bus error will stop DMA operation and RSA accelerator. + * |[17] |CTLERR |RSA Control Register Error Flag + * | | |0 = No error. + * | | |1 = RSA control error. RSA will not start in the unsupported situation. + * | | |Note: If users use the error combination of control, even though they don't set START(CRYPTO_RSA_CTL[0]) to 1, CTLERR still be set to 1. + * |[18] |KSERR |RSA Engine Access Key Store Error Flag + * | | |0 = No error. + * | | |1 = Access error will stop RSA engine. + * @var CRYPTO_T::RSA_SADDR0 + * Offset: 0xB08 RSA DMA Source Address Register0 + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[31:0] |SADDR0 |RSA DMA Source Address Register0 + * | | |The RSA accelerator supports DMA function to transfer the DATA and PARAMETER between SRAM memory space and RSA accelerator. + * | | |This register is stored the address of RSA the Base of Exponentiation (M). + * @var CRYPTO_T::RSA_SADDR1 + * Offset: 0xB0C RSA DMA Source Address Register1 + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[31:0] |SADDR1 |RSA DMA Source Address Register1 + * | | |The RSA accelerator supports DMA function to transfer the DATA and PARAMETER between SRAM memory space and RSA accelerator. + * | | |This register is stored the address of RSA the Base of Modulus Operation (N). + * @var CRYPTO_T::RSA_SADDR2 + * Offset: 0xB10 RSA DMA Source Address Register2 + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[31:0] |SADDR2 |RSA DMA Source Address Register2 + * | | |The RSA accelerator supports DMA function to transfer the DATA and PARAMETER between SRAM memory space and RSA accelerator. + * | | |This register is stored the address of RSA the Exponent of Exponentiation (E). + * @var CRYPTO_T::RSA_SADDR3 + * Offset: 0xB14 RSA DMA Source Address Register3 + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[31:0] |SADDR3 |RSA DMA Source Address Register3 + * | | |The RSA accelerator supports DMA function to transfer the DATA and PARAMETER between SRAM memory space and RSA accelerator. + * | | |This register is stored the address of RSA the Factor of Modulus Operation (p). + * @var CRYPTO_T::RSA_SADDR4 + * Offset: 0xB18 RSA DMA Source Address Register4 + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[31:0] |SADDR4 |RSA DMA Source Address Register4 + * | | |The RSA accelerator supports DMA function to transfer the DATA and PARAMETER between SRAM memory space and RSA accelerator. + * | | |This register is stored the address of RSA the Factor of Modulus Operation (q). + * @var CRYPTO_T::RSA_DADDR + * Offset: 0xB1C RSA DMA Destination Address Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[31:0] |DADDR |RSA DMA Destination Address Register + * | | |The RSA accelerator supports DMA function to transfer the DATA and PARAMETER between SRAM memory space and RSA accelerator. + * | | |This register is stored the address of RSA DMA Destination Address Register (Ans). + * @var CRYPTO_T::RSA_MADDR0 + * Offset: 0xB20 RSA DMA Middle Address Register0 + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[31:0] |MADDR0 |RSA DMA Middle Address Register0 + * | | |The RSA accelerator supports DMA function to transfer the DATA and PARAMETER between SRAM memory space and RSA accelerator. + * @var CRYPTO_T::RSA_MADDR1 + * Offset: 0xB24 RSA DMA Middle Address Register1 + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[31:0] |MADDR1 |RSA DMA Middle Address Register1 + * | | |The RSA accelerator supports DMA function to transfer the DATA and PARAMETER between SRAM memory space and RSA accelerator. + * @var CRYPTO_T::RSA_MADDR2 + * Offset: 0xB28 RSA DMA Middle Address Register2 + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[31:0] |MADDR2 |RSA DMA Middle Address Register2 + * | | |The RSA accelerator supports DMA function to transfer the DATA and PARAMETER between SRAM memory space and RSA accelerator. + * @var CRYPTO_T::RSA_MADDR3 + * Offset: 0xB2C RSA DMA Middle Address Register3 + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[31:0] |MADDR3 |RSA DMA Middle Address Register3 + * | | |The RSA accelerator supports DMA function to transfer the DATA and PARAMETER between SRAM memory space and RSA accelerator. + * @var CRYPTO_T::RSA_MADDR4 + * Offset: 0xB30 RSA DMA Middle Address Register4 + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[31:0] |MADDR4 |RSA DMA Middle Address Register4 + * | | |The RSA accelerator supports DMA function to transfer the DATA and PARAMETER between SRAM memory space and RSA accelerator. + * @var CRYPTO_T::RSA_MADDR5 + * Offset: 0xB34 RSA DMA Middle Address Register5 + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[31:0] |MADDR5 |RSA DMA Middle Address Register5 + * | | |The RSA accelerator supports DMA function to transfer the DATA and PARAMETER between SRAM memory space and RSA accelerator. + * @var CRYPTO_T::RSA_MADDR6 + * Offset: 0xB38 RSA DMA Middle Address Register6 + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[31:0] |MADDR6 |RSA DMA Middle Address Register6 + * | | |The RSA accelerator supports DMA function to transfer the DATA and PARAMETER between SRAM memory space and RSA accelerator. + * @var CRYPTO_T::PRNG_KSCTL + * Offset: 0xF00 PRNG Key Control Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[4:0] |NUM |Write Key Number + * | | |The key number is sent to key store + * | | |Note: Only for destination Is OTP of key store. + * |[8] |KEYSRC |Key Source + * | | |0 = Key (random number) is from PRNG engine. + * | | |1 = Key (random number) is from TRNG engine (skip PRNG operation). + * | | |Note: When KEYSRC is set to 1, PRNG operation will be skipped, it indicates that the bit (SEEDRLD) is meaningless. + * |[16] |TRUST |Write Key Trust Selection Bit + * | | |0 = Set written key as the non-secure key. + * | | |1 = Set written key as the secure key. + * |[19] |ECDH |ECDH Control Bit + * | | |0 = reserved. + * | | |1 = key is written to key store and used in ECDH. + * | | |Note: When ECDH was set to '1', 1 + * | | |PRNG seed must from TRNG and key is must written to the SRAM of key store (WSDST, CRYPTO_PRNG_KSCTL[23:22] must set to '00') + * | | |Otherwise, KCTLERR will become '1'(CRYPTO_PRNG_KSSTS[16]) + * | | |2 + * | | |Key must in the interval [1, n-1] (the parameter n is from ECC) + * | | |The value of n cannot be 0 or 1, otherwise, PRNG will always keep busy. + * |[20] |ECDSA |ECDSA Control Bit + * | | |0 = reserved. + * | | |1 = key is written to key store and used in ECDSA. + * | | |Note: When ECDSA was set to '1', 1 + * | | |PRNG seed must from TRNG and key is must written to the SRAM of key store (WSDST, CRYPTO_PRNG_KSCTL[23:22] must set to '00') + * | | |Otherwise, KCTLERR will become '1'(CRYPTO_PRNG_KSSTS[16]) + * | | |2 + * | | |Key must in the interval [1, n-1] (the parameter n is from ECC) + * | | |The value of n cannot be 0 or 1, otherwise, PRNG will always keep busy. + * |[21] |WDST |Write Key Destination + * | | |0 = key is written to registers CRYPTO_PRNG_KEYx. + * | | |1 = key is written to key store. + * |[23:22] |WSDST |Write Key Store Destination + * | | |00 = key is written to the SRAM of key store. + * | | |10 = key is written to the OTP of key store. + * | | |Others = reserved. + * |[26:24] |OWNER |Write Key Owner Selection Bits + * | | |000 = Only for AES used. + * | | |001 = Only for HMAC engine used. + * | | |100 = Only for ECC engine used. + * | | |101 = Only for CPU engine use. + * | | |Others = reserved. + * @var CRYPTO_T::PRNG_KSSTS + * Offset: 0xF04 PRNG Key Status Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[4:0] |NUM |Key Number + * | | |The key number is generated by key store + * @var CRYPTO_T::AES_KSCTL + * Offset: 0xF10 AES Key Control Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[4:0] |NUM |Read Key Number + * | | |The key number is sent to key store + * |[5] |RSRC |Read Key Source + * | | |0 = key is read from registers CRYPTO_AESx_KEYx. + * | | |1 = key is read from key store. + * |[7:6] |RSSRC |Read Key Store Source + * | | |00 = key is read from the SRAM of key store. + * | | |10 = key is read from the OTP of key store. + * | | |Others = reserved. + * @var CRYPTO_T::HMAC_KSCTL + * Offset: 0xF30 HMAC Key Control Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[4:0] |NUM |Read Key Number + * | | |The key number is sent to key store + * |[5] |RSRC |Read Key Source + * | | |0 = key is read from HMAC registers. + * | | |1 = key is read from key store. + * |[7:6] |RSSRC |Read Key Store Source + * | | |00 = key is read from the SRAM of key store. + * | | |10 = key is read from the OTP of key store. + * | | |Others = reserved. + * @var CRYPTO_T::ECC_KSCTL + * Offset: 0xF40 ECC Key Control Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[4:0] |NUMK |Read Key Number K + * | | |The key number of CRYPTO_ECC_K is sent to key store when RSRCK =1. + * |[5] |RSRCK |Read Key Source for Key Number K + * | | |0 = key is read from ECC registers. + * | | |1 = key is read from key store. + * |[7:6] |RSSRCK |Read Key Store Source for Key Number K + * | | |00 = key is read from the SRAM of key store. + * | | |10 = key is read from the OTP of key store. + * | | |Others = reserved. + * |[14] |ECDH |ECDH Control Bit + * | | |0 = reserved. + * | | |1 = Set ECC operation is in ECDH + * | | |When this bit and RSRCK are equal to 0x1, ECC will read ECDH private key to CRYPTO_ECC_K from key store. + * |[16] |TRUST |Write Key Trust Selection Bit + * | | |0 = Set ECDH written key as the non-secure key. + * | | |1 = Set ECDH written key as the secure key. + * |[20] |XY |ECDH Output Select Bit + * | | |0 = The ECDH written key is from X-coordinate Value. + * | | |1 = The ECDH written key is from Y-coordinate Value. + * |[21] |WDST |Write Key Destination + * | | |0 = The ECDH written key is in registers CRYPTO_ECC_X1 and CRYPTO_ECC_Y. + * | | |1 = The ECDH written key is written to key store. + * |[23:22] |WSDST |Write Key Store Destination + * | | |00 = The ECDH written key is written to the SRAM of key store. + * | | |10 = The ECDH written key is written to the OTP of key store. + * | | |Others = reserved. + * |[26:24] |OWNER |Write Key Owner Selection Bits + * | | |000 = The ECDH written key is only for AES used. + * | | |001 = The ECDH written key is only for HMAC engine used. + * | | |100 = The ECDH written key is only for ECC engine used. + * | | |101 = The ECDH written key is only for CPU engine use. + * | | |Others = reserved. + * @var CRYPTO_T::ECC_KSSTS + * Offset: 0xF44 ECC Key Status Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[4:0] |NUM |Key Number + * | | |The key number is generated by key store after ECDH. + * @var CRYPTO_T::ECC_KSXY + * Offset: 0xF48 ECC XY Number Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[4:0] |NUMX |Read Key Number X + * | | |The key number of CRYPTO_ECC_X1 is sent to key store when RSRCXY =1. + * |[5] |RSRCXY |Read Key Source for Key Number x and Y + * | | |0 = Key is read from ECC registers. + * | | |1 = Key is read from key store. + * |[7:6] |RSSRCX |Read Key Store Source for Key Number X + * | | |00 = Key is read from the SRAM of key store. + * | | |10 = Key is read from the OTP of key store. + * | | |Others = reserved. + * |[12:8] |NUMY |Read Key Number Y + * | | |The key number of CRYPTO_ECC_Y1 is sent to key store when RSRCXY =1. + * |[15:14] |RSSRCY |Read Key Store Source for Key Number Y + * | | |00 = Key is read from the SRAM of key store. + * | | |10 = Key is read from the OTP of key store. + * | | |Others = reserved. + * @var CRYPTO_T::RSA_KSCTL + * Offset: 0xF50 RSA Key Control Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[4:0] |NUM |Read Key Number + * | | |The key number is sent to key store + * |[5] |RSRC |Read Key Source + * | | |0 = Key is read from RSA engine. + * | | |1 = Key is read from key store. + * |[7:6] |RSSRC |Read Key Store Source + * | | |00 = Key is read from the SRAM of key store. + * | | |Others = Reserved. + * |[12:8] |BKNUM |Read Exponent Blind Key Number + * | | |The key number is sent to key store, and its destination always be the SRAM of key store + * | | |CPU cannot read the exponent blind key. + * | | |Note: Use this key number, only when executing SCA protection but no-CRT mode + * | | |When allocate space of key store, key owner selection bits(KS_METADATA[18:16]) should be '010'. + * @var CRYPTO_T::RSA_KSSTS0 + * Offset: 0xF54 RSA Key Status Register 0 + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[4:0] |NUM0 |Key Number0 + * | | |The key number is generated by key store, RSA can get complete p by key number in key store while operating. + * | | |Note: The size of this key as half key length. + * |[12:8] |NUM1 |Key Number1 + * | | |The key number is generated by key store, RSA can get complete q by key number in Key Store while operating. + * | | |Note: The size of this key as half key length. + * |[20:16] |NUM2 |Key Number2 + * | | |The key number is generated by key store, RSA can get or store the intermediate temporary value by key number in the key store while operating. + * | | |Note: The size of this key as key length. + * |[28:24] |NUM3 |Key Number3 + * | | |The key number is generated by key store, RSA can get or store the intermediate temporary value by key number in the key store while operating. + * | | |Note: The size of this key as key length. + * @var CRYPTO_T::RSA_KSSTS1 + * Offset: 0xF58 RSA Key Status Register 1 + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[4:0] |NUM4 |Key Number4 + * | | |The key number is generated by key store, RSA can get or store the intermediate temporary value by key number in key store while operating. + * | | |Note: The size of this key as half key length. + * |[12:8] |NUM5 |Key Number5 + * | | |The key number is generated by key store, RSA can get or store the intermediate temporary value by key number in key store while operating. + * | | |Note: The size of this key as half key length. + * |[20:16] |NUM6 |Key Number6 + * | | |The key number is generated by key store, RSA can get or store the intermediate temporary value by key number in key store while operating. + * | | |Note: The size of this key as key length. + * |[28:24] |NUM7 |Key Number7 + * | | |The key number is generated by key store, RSA can get or store the intermediate temporary value by key number in key store while operating. + * | | |Note: The size of this key as key length. + */ + __IO uint32_t INTEN; /*!< [0x0000] Crypto Interrupt Enable Control Register */ + __IO uint32_t INTSTS; /*!< [0x0004] Crypto Interrupt Flag */ + __IO uint32_t PRNG_CTL; /*!< [0x0008] PRNG Control Register */ + __O uint32_t PRNG_SEED; /*!< [0x000c] Seed for PRNG */ + __I uint32_t PRNG_KEY0; /*!< [0x0010] PRNG Generated Key0 */ + __I uint32_t PRNG_KEY1; /*!< [0x0014] PRNG Generated Key1 */ + __I uint32_t PRNG_KEY2; /*!< [0x0018] PRNG Generated Key2 */ + __I uint32_t PRNG_KEY3; /*!< [0x001c] PRNG Generated Key3 */ + __I uint32_t PRNG_KEY4; /*!< [0x0020] PRNG Generated Key4 */ + __I uint32_t PRNG_KEY5; /*!< [0x0024] PRNG Generated Key5 */ + __I uint32_t PRNG_KEY6; /*!< [0x0028] PRNG Generated Key6 */ + __I uint32_t PRNG_KEY7; /*!< [0x002c] PRNG Generated Key7 */ + __I uint32_t PRNG_STS; /*!< [0x0030] PRNG Status Register */ + __I uint32_t RESERVE0[7]; + __I uint32_t AES_FDBCK0; /*!< [0x0050] AES Engine Output Feedback Data After Cryptographic Operation */ + __I uint32_t AES_FDBCK1; /*!< [0x0054] AES Engine Output Feedback Data After Cryptographic Operation */ + __I uint32_t AES_FDBCK2; /*!< [0x0058] AES Engine Output Feedback Data After Cryptographic Operation */ + __I uint32_t AES_FDBCK3; /*!< [0x005c] AES Engine Output Feedback Data After Cryptographic Operation */ + __I uint32_t RESERVE1[8]; + __IO uint32_t AES_GCM_IVCNT0; /*!< [0x0080] AES GCM IV Byte Count Register 0 */ + __IO uint32_t AES_GCM_IVCNT1; /*!< [0x0084] AES GCM IV Byte Count Register 1 */ + __IO uint32_t AES_GCM_ACNT0; /*!< [0x0088] AES GCM A Byte Count Register 0 */ + __IO uint32_t AES_GCM_ACNT1; /*!< [0x008c] AES GCM A Byte Count Register 1 */ + __IO uint32_t AES_GCM_PCNT0; /*!< [0x0090] AES GCM P Byte Count Register 0 */ + __IO uint32_t AES_GCM_PCNT1; /*!< [0x0094] AES GCM P Byte Count Register 1 */ + __I uint32_t RESERVE2[2]; + __IO uint32_t AES_FBADDR; /*!< [0x00a0] AES DMA Feedback Address Register */ + __I uint32_t RESERVE3[23]; + __IO uint32_t AES_CTL; /*!< [0x0100] AES Control Register */ + __I uint32_t AES_STS; /*!< [0x0104] AES Engine Flag */ + __IO uint32_t AES_DATIN; /*!< [0x0108] AES Engine Data Input Port Register */ + __I uint32_t AES_DATOUT; /*!< [0x010c] AES Engine Data Output Port Register */ + __IO uint32_t AES_KEY0; /*!< [0x0110] AES Key Word 0 Register */ + __IO uint32_t AES_KEY1; /*!< [0x0114] AES Key Word 1 Register */ + __IO uint32_t AES_KEY2; /*!< [0x0118] AES Key Word 2 Register */ + __IO uint32_t AES_KEY3; /*!< [0x011c] AES Key Word 3 Register */ + __IO uint32_t AES_KEY4; /*!< [0x0120] AES Key Word 4 Register */ + __IO uint32_t AES_KEY5; /*!< [0x0124] AES Key Word 5 Register */ + __IO uint32_t AES_KEY6; /*!< [0x0128] AES Key Word 6 Register */ + __IO uint32_t AES_KEY7; /*!< [0x012c] AES Key Word 7 Register */ + __IO uint32_t AES_IV0; /*!< [0x0130] AES Initial Vector Word 0 Register */ + __IO uint32_t AES_IV1; /*!< [0x0134] AES Initial Vector Word 1 Register */ + __IO uint32_t AES_IV2; /*!< [0x0138] AES Initial Vector Word 2 Register */ + __IO uint32_t AES_IV3; /*!< [0x013c] AES Initial Vector Word 3 Register */ + __IO uint32_t AES_SADDR; /*!< [0x0140] AES DMA Source Address Register */ + __IO uint32_t AES_DADDR; /*!< [0x0144] AES DMA Destination Address Register */ + __IO uint32_t AES_CNT; /*!< [0x0148] AES Byte Count Register */ + __I uint32_t RESERVE4[109]; + __IO uint32_t HMAC_CTL; /*!< [0x0300] SHA/HMAC Control Register */ + __I uint32_t HMAC_STS; /*!< [0x0304] SHA/HMAC Status Flag */ + __I uint32_t HMAC_DGST0; /*!< [0x0308] SHA/HMAC Output Feedback Data 0 */ + __I uint32_t HMAC_DGST1; /*!< [0x030c] SHA/HMAC Output Feedback Data 1 */ + __I uint32_t HMAC_DGST2; /*!< [0x0310] SHA/HMAC Output Feedback Data 2 */ + __I uint32_t HMAC_DGST3; /*!< [0x0314] SHA/HMAC Output Feedback Data 3 */ + __I uint32_t HMAC_DGST4; /*!< [0x0318] SHA/HMAC Output Feedback Data 4 */ + __I uint32_t HMAC_DGST5; /*!< [0x031c] SHA/HMAC Output Feedback Data 5 */ + __I uint32_t HMAC_DGST6; /*!< [0x0320] SHA/HMAC Output Feedback Data 6 */ + __I uint32_t HMAC_DGST7; /*!< [0x0324] SHA/HMAC Output Feedback Data 7 */ + __I uint32_t HMAC_DGST8; /*!< [0x0328] SHA/HMAC Output Feedback Data 8 */ + __I uint32_t HMAC_DGST9; /*!< [0x032c] SHA/HMAC Output Feedback Data 9 */ + __I uint32_t HMAC_DGST10; /*!< [0x0330] SHA/HMAC Output Feedback Data 10 */ + __I uint32_t HMAC_DGST11; /*!< [0x0334] SHA/HMAC Output Feedback Data 11 */ + __I uint32_t HMAC_DGST12; /*!< [0x0338] SHA/HMAC Output Feedback Data 12 */ + __I uint32_t HMAC_DGST13; /*!< [0x033c] SHA/HMAC Output Feedback Data 13 */ + __I uint32_t HMAC_DGST14; /*!< [0x0340] SHA/HMAC Output Feedback Data 14 */ + __I uint32_t HMAC_DGST15; /*!< [0x0344] SHA/HMAC Output Feedback Data 15 */ + __IO uint32_t HMAC_KEYCNT; /*!< [0x0348] SHA/HMAC Key Byte Count Register */ + __IO uint32_t HMAC_SADDR; /*!< [0x034c] SHA/HMAC DMA Source Address Register */ + __IO uint32_t HMAC_DMACNT; /*!< [0x0350] SHA/HMAC Byte Count Register */ + __IO uint32_t HMAC_DATIN; /*!< [0x0354] SHA/HMAC Engine Non-DMA Mode Data Input Port Register */ + __IO uint32_t HMAC_FDBCK0; /*!< [0x0358] SHA/HMAC Output Feedback Data 0 After SHA/HMAC Operation */ + __IO uint32_t HMAC_FDBCK1; /*!< [0x035c] SHA/HMAC Output Feedback Data 1 After SHA/HMAC Operation */ + __IO uint32_t HMAC_FDBCK2; /*!< [0x0360] SHA/HMAC Output Feedback Data 2 After SHA/HMAC Operation */ + __IO uint32_t HMAC_FDBCK3; /*!< [0x0364] SHA/HMAC Output Feedback Data 3 After SHA/HMAC Operation */ + __IO uint32_t HMAC_FDBCK4; /*!< [0x0368] SHA/HMAC Output Feedback Data 4 After SHA/HMAC Operation */ + __IO uint32_t HMAC_FDBCK5; /*!< [0x036c] SHA/HMAC Output Feedback Data 5 After SHA/HMAC Operation */ + __IO uint32_t HMAC_FDBCK6; /*!< [0x0370] SHA/HMAC Output Feedback Data 6 After SHA/HMAC Operation */ + __IO uint32_t HMAC_FDBCK7; /*!< [0x0374] SHA/HMAC Output Feedback Data 7 After SHA/HMAC Operation */ + __IO uint32_t HMAC_FDBCK8; /*!< [0x0378] SHA/HMAC Output Feedback Data 8 After SHA/HMAC Operation */ + __IO uint32_t HMAC_FDBCK9; /*!< [0x037c] SHA/HMAC Output Feedback Data 9 After SHA/HMAC Operation */ + __IO uint32_t HMAC_FDBCK10; /*!< [0x0380] SHA/HMAC Output Feedback Data 10 After SHA/HMAC Operation */ + __IO uint32_t HMAC_FDBCK11; /*!< [0x0384] SHA/HMAC Output Feedback Data 11 After SHA/HMAC Operation */ + __IO uint32_t HMAC_FDBCK12; /*!< [0x0388] SHA/HMAC Output Feedback Data 12 After SHA/HMAC Operation */ + __IO uint32_t HMAC_FDBCK13; /*!< [0x038c] SHA/HMAC Output Feedback Data 13 After SHA/HMAC Operation */ + __IO uint32_t HMAC_FDBCK14; /*!< [0x0390] SHA/HMAC Output Feedback Data 14 After SHA/HMAC Operation */ + __IO uint32_t HMAC_FDBCK15; /*!< [0x0394] SHA/HMAC Output Feedback Data 15 After SHA/HMAC Operation */ + __IO uint32_t HMAC_FDBCK16; /*!< [0x0398] SHA/HMAC Output Feedback Data 16 After SHA/HMAC Operation */ + __IO uint32_t HMAC_FDBCK17; /*!< [0x039c] SHA/HMAC Output Feedback Data 17 After SHA/HMAC Operation */ + __IO uint32_t HMAC_FDBCK18; /*!< [0x03a0] SHA/HMAC Output Feedback Data 18 After SHA/HMAC Operation */ + __IO uint32_t HMAC_FDBCK19; /*!< [0x03a4] SHA/HMAC Output Feedback Data 19 After SHA/HMAC Operation */ + __IO uint32_t HMAC_FDBCK20; /*!< [0x03a8] SHA/HMAC Output Feedback Data 20 After SHA/HMAC Operation */ + __IO uint32_t HMAC_FDBCK21; /*!< [0x03ac] SHA/HMAC Output Feedback Data 21 After SHA/HMAC Operation */ + __IO uint32_t HMAC_FDBCK22; /*!< [0x03b0] SHA/HMAC Output Feedback Data 22 After SHA/HMAC Operation */ + __IO uint32_t HMAC_FDBCK23; /*!< [0x03b4] SHA/HMAC Output Feedback Data 23 After SHA/HMAC Operation */ + __IO uint32_t HMAC_FDBCK24; /*!< [0x03b8] SHA/HMAC Output Feedback Data 24 After SHA/HMAC Operation */ + __IO uint32_t HMAC_FDBCK25; /*!< [0x03bc] SHA/HMAC Output Feedback Data 25 After SHA/HMAC Operation */ + __IO uint32_t HMAC_FDBCK26; /*!< [0x03c0] SHA/HMAC Output Feedback Data 26 After SHA/HMAC Operation */ + __IO uint32_t HMAC_FDBCK27; /*!< [0x03c4] SHA/HMAC Output Feedback Data 27 After SHA/HMAC Operation */ + __IO uint32_t HMAC_FDBCK28; /*!< [0x03c8] SHA/HMAC Output Feedback Data 28 After SHA/HMAC Operation */ + __IO uint32_t HMAC_FDBCK29; /*!< [0x03cc] SHA/HMAC Output Feedback Data 29 After SHA/HMAC Operation */ + __IO uint32_t HMAC_FDBCK30; /*!< [0x03d0] SHA/HMAC Output Feedback Data 30 After SHA/HMAC Operation */ + __IO uint32_t HMAC_FDBCK31; /*!< [0x03d4] SHA/HMAC Output Feedback Data 31 After SHA/HMAC Operation */ + __IO uint32_t HMAC_FDBCK32; /*!< [0x03d8] SHA/HMAC Output Feedback Data 32 After SHA/HMAC Operation */ + __IO uint32_t HMAC_FDBCK33; /*!< [0x03dc] SHA/HMAC Output Feedback Data 33 After SHA/HMAC Operation */ + __IO uint32_t HMAC_FDBCK34; /*!< [0x03e0] SHA/HMAC Output Feedback Data 34 After SHA/HMAC Operation */ + __IO uint32_t HMAC_FDBCK35; /*!< [0x03e4] SHA/HMAC Output Feedback Data 35 After SHA/HMAC Operation */ + __IO uint32_t HMAC_FDBCK36; /*!< [0x03e8] SHA/HMAC Output Feedback Data 36 After SHA/HMAC Operation */ + __IO uint32_t HMAC_FDBCK37; /*!< [0x03ec] SHA/HMAC Output Feedback Data 37 After SHA/HMAC Operation */ + __IO uint32_t HMAC_FDBCK38; /*!< [0x03f0] SHA/HMAC Output Feedback Data 38 After SHA/HMAC Operation */ + __IO uint32_t HMAC_FDBCK39; /*!< [0x03f4] SHA/HMAC Output Feedback Data 39 After SHA/HMAC Operation */ + __IO uint32_t HMAC_FDBCK40; /*!< [0x03f8] SHA/HMAC Output Feedback Data 40 After SHA/HMAC Operation */ + __IO uint32_t HMAC_FDBCK41; /*!< [0x03fc] SHA/HMAC Output Feedback Data 41 After SHA/HMAC Operation */ + __IO uint32_t HMAC_FDBCK42; /*!< [0x0400] SHA/HMAC Output Feedback Data 42 After SHA/HMAC Operation */ + __IO uint32_t HMAC_FDBCK43; /*!< [0x0404] SHA/HMAC Output Feedback Data 43 After SHA/HMAC Operation */ + __IO uint32_t HMAC_FDBCK44; /*!< [0x0408] SHA/HMAC Output Feedback Data 44 After SHA/HMAC Operation */ + __IO uint32_t HMAC_FDBCK45; /*!< [0x040c] SHA/HMAC Output Feedback Data 45 After SHA/HMAC Operation */ + __IO uint32_t HMAC_FDBCK46; /*!< [0x0410] SHA/HMAC Output Feedback Data 46 After SHA/HMAC Operation */ + __IO uint32_t HMAC_FDBCK47; /*!< [0x0414] SHA/HMAC Output Feedback Data 47 After SHA/HMAC Operation */ + __IO uint32_t HMAC_FDBCK48; /*!< [0x0418] SHA/HMAC Output Feedback Data 48 After SHA/HMAC Operation */ + __IO uint32_t HMAC_FDBCK49; /*!< [0x041c] SHA/HMAC Output Feedback Data 49 After SHA/HMAC Operation */ + __IO uint32_t HMAC_FDBCK50; /*!< [0x0420] SHA/HMAC Output Feedback Data 50 After SHA/HMAC Operation */ + __IO uint32_t HMAC_FDBCK51; /*!< [0x0424] SHA/HMAC Output Feedback Data 51 After SHA/HMAC Operation */ + __IO uint32_t HMAC_FDBCK52; /*!< [0x0428] SHA/HMAC Output Feedback Data 52 After SHA/HMAC Operation */ + __IO uint32_t HMAC_FDBCK53; /*!< [0x042c] SHA/HMAC Output Feedback Data 53 After SHA/HMAC Operation */ + __IO uint32_t HMAC_FDBCK54; /*!< [0x0430] SHA/HMAC Output Feedback Data 54 After SHA/HMAC Operation */ + __IO uint32_t HMAC_FDBCK55; /*!< [0x0434] SHA/HMAC Output Feedback Data 55 After SHA/HMAC Operation */ + __IO uint32_t HMAC_FDBCK56; /*!< [0x0438] SHA/HMAC Output Feedback Data 56 After SHA/HMAC Operation */ + __IO uint32_t HMAC_FDBCK57; /*!< [0x043c] SHA/HMAC Output Feedback Data 57 After SHA/HMAC Operation */ + __IO uint32_t HMAC_FDBCK58; /*!< [0x0440] SHA/HMAC Output Feedback Data 58 After SHA/HMAC Operation */ + __IO uint32_t HMAC_FDBCK59; /*!< [0x0444] SHA/HMAC Output Feedback Data 59 After SHA/HMAC Operation */ + __IO uint32_t HMAC_FDBCK60; /*!< [0x0448] SHA/HMAC Output Feedback Data 60 After SHA/HMAC Operation */ + __IO uint32_t HMAC_FDBCK61; /*!< [0x044c] SHA/HMAC Output Feedback Data 61 After SHA/HMAC Operation */ + __IO uint32_t HMAC_FDBCK62; /*!< [0x0450] SHA/HMAC Output Feedback Data 62 After SHA/HMAC Operation */ + __IO uint32_t HMAC_FDBCK63; /*!< [0x0454] SHA/HMAC Output Feedback Data 63 After SHA/HMAC Operation */ + __IO uint32_t HMAC_FDBCK64; /*!< [0x0458] SHA/HMAC Output Feedback Data 64 After SHA/HMAC Operation */ + __IO uint32_t HMAC_FDBCK65; /*!< [0x045c] SHA/HMAC Output Feedback Data 65 After SHA/HMAC Operation */ + __IO uint32_t HMAC_FDBCK66; /*!< [0x0460] SHA/HMAC Output Feedback Data 66 After SHA/HMAC Operation */ + __IO uint32_t HMAC_FDBCK67; /*!< [0x0464] SHA/HMAC Output Feedback Data 67 After SHA/HMAC Operation */ + __IO uint32_t HMAC_FDBCK68; /*!< [0x0468] SHA/HMAC Output Feedback Data 68 After SHA/HMAC Operation */ + __IO uint32_t HMAC_FDBCK69; /*!< [0x046c] SHA/HMAC Output Feedback Data 69 After SHA/HMAC Operation */ + __IO uint32_t HMAC_FDBCK70; /*!< [0x0470] SHA/HMAC Output Feedback Data 70 After SHA/HMAC Operation */ + __IO uint32_t HMAC_FDBCK71; /*!< [0x0474] SHA/HMAC Output Feedback Data 71 After SHA/HMAC Operation */ + __IO uint32_t HMAC_FDBCK72; /*!< [0x0478] SHA/HMAC Output Feedback Data 72 After SHA/HMAC Operation */ + __IO uint32_t HMAC_FDBCK73; /*!< [0x047c] SHA/HMAC Output Feedback Data 73 After SHA/HMAC Operation */ + __IO uint32_t HMAC_FDBCK74; /*!< [0x0480] SHA/HMAC Output Feedback Data 74 After SHA/HMAC Operation */ + __IO uint32_t HMAC_FDBCK75; /*!< [0x0484] SHA/HMAC Output Feedback Data 75 After SHA/HMAC Operation */ + __IO uint32_t HMAC_FDBCK76; /*!< [0x0488] SHA/HMAC Output Feedback Data 76 After SHA/HMAC Operation */ + __IO uint32_t HMAC_FDBCK77; /*!< [0x048c] SHA/HMAC Output Feedback Data 77 After SHA/HMAC Operation */ + __IO uint32_t HMAC_FDBCK78; /*!< [0x0490] SHA/HMAC Output Feedback Data 78 After SHA/HMAC Operation */ + __IO uint32_t HMAC_FDBCK79; /*!< [0x0494] SHA/HMAC Output Feedback Data 79 After SHA/HMAC Operation */ + __IO uint32_t HMAC_FDBCK80; /*!< [0x0498] SHA/HMAC Output Feedback Data 80 After SHA/HMAC Operation */ + __IO uint32_t HMAC_FDBCK81; /*!< [0x049c] SHA/HMAC Output Feedback Data 81 After SHA/HMAC Operation */ + __IO uint32_t HMAC_FDBCK82; /*!< [0x04a0] SHA/HMAC Output Feedback Data 82 After SHA/HMAC Operation */ + __IO uint32_t HMAC_FDBCK83; /*!< [0x04a4] SHA/HMAC Output Feedback Data 83 After SHA/HMAC Operation */ + __IO uint32_t HMAC_FDBCK84; /*!< [0x04a8] SHA/HMAC Output Feedback Data 84 After SHA/HMAC Operation */ + __IO uint32_t HMAC_FDBCK85; /*!< [0x04ac] SHA/HMAC Output Feedback Data 85 After SHA/HMAC Operation */ + __IO uint32_t HMAC_FDBCK86; /*!< [0x04b0] SHA/HMAC Output Feedback Data 86 After SHA/HMAC Operation */ + __IO uint32_t HMAC_FDBCK87; /*!< [0x04b4] SHA/HMAC Output Feedback Data 87 After SHA/HMAC Operation */ + __I uint32_t RESERVE5[16]; + __IO uint32_t HMAC_SHA512T; /*!< [0x04f8] SHA/HMAC SHA512T Control Register */ + __IO uint32_t HMAC_FBADDR; /*!< [0x04fc] SHA/HMAC DMA Feedback Address Register */ + __I uint32_t HMAC_SHAKEDGST0; /*!< [0x0500] SHA/HMAC SHAKE Digest Message 0 */ + __I uint32_t HMAC_SHAKEDGST1; /*!< [0x0504] SHA/HMAC SHAKE Digest Message 1 */ + __I uint32_t HMAC_SHAKEDGST2; /*!< [0x0508] SHA/HMAC SHAKE Digest Message 2 */ + __I uint32_t HMAC_SHAKEDGST3; /*!< [0x050c] SHA/HMAC SHAKE Digest Message 3 */ + __I uint32_t HMAC_SHAKEDGST4; /*!< [0x0510] SHA/HMAC SHAKE Digest Message 4 */ + __I uint32_t HMAC_SHAKEDGST5; /*!< [0x0514] SHA/HMAC SHAKE Digest Message 5 */ + __I uint32_t HMAC_SHAKEDGST6; /*!< [0x0518] SHA/HMAC SHAKE Digest Message 6 */ + __I uint32_t HMAC_SHAKEDGST7; /*!< [0x051c] SHA/HMAC SHAKE Digest Message 7 */ + __I uint32_t HMAC_SHAKEDGST8; /*!< [0x0520] SHA/HMAC SHAKE Digest Message 8 */ + __I uint32_t HMAC_SHAKEDGST9; /*!< [0x0524] SHA/HMAC SHAKE Digest Message 9 */ + __I uint32_t HMAC_SHAKEDGST10; /*!< [0x0528] SHA/HMAC SHAKE Digest Message 10 */ + __I uint32_t HMAC_SHAKEDGST11; /*!< [0x052c] SHA/HMAC SHAKE Digest Message 11 */ + __I uint32_t HMAC_SHAKEDGST12; /*!< [0x0530] SHA/HMAC SHAKE Digest Message 12 */ + __I uint32_t HMAC_SHAKEDGST13; /*!< [0x0534] SHA/HMAC SHAKE Digest Message 13 */ + __I uint32_t HMAC_SHAKEDGST14; /*!< [0x0538] SHA/HMAC SHAKE Digest Message 14 */ + __I uint32_t HMAC_SHAKEDGST15; /*!< [0x053c] SHA/HMAC SHAKE Digest Message 15 */ + __I uint32_t HMAC_SHAKEDGST16; /*!< [0x0540] SHA/HMAC SHAKE Digest Message 16 */ + __I uint32_t HMAC_SHAKEDGST17; /*!< [0x0544] SHA/HMAC SHAKE Digest Message 17 */ + __I uint32_t HMAC_SHAKEDGST18; /*!< [0x0548] SHA/HMAC SHAKE Digest Message 18 */ + __I uint32_t HMAC_SHAKEDGST19; /*!< [0x054c] SHA/HMAC SHAKE Digest Message 19 */ + __I uint32_t HMAC_SHAKEDGST20; /*!< [0x0550] SHA/HMAC SHAKE Digest Message 20 */ + __I uint32_t HMAC_SHAKEDGST21; /*!< [0x0554] SHA/HMAC SHAKE Digest Message 21 */ + __I uint32_t HMAC_SHAKEDGST22; /*!< [0x0558] SHA/HMAC SHAKE Digest Message 22 */ + __I uint32_t HMAC_SHAKEDGST23; /*!< [0x055c] SHA/HMAC SHAKE Digest Message 23 */ + __I uint32_t HMAC_SHAKEDGST24; /*!< [0x0560] SHA/HMAC SHAKE Digest Message 24 */ + __I uint32_t HMAC_SHAKEDGST25; /*!< [0x0564] SHA/HMAC SHAKE Digest Message 25 */ + __I uint32_t HMAC_SHAKEDGST26; /*!< [0x0568] SHA/HMAC SHAKE Digest Message 26 */ + __I uint32_t HMAC_SHAKEDGST27; /*!< [0x056c] SHA/HMAC SHAKE Digest Message 27 */ + __I uint32_t HMAC_SHAKEDGST28; /*!< [0x0570] SHA/HMAC SHAKE Digest Message 28 */ + __I uint32_t HMAC_SHAKEDGST29; /*!< [0x0574] SHA/HMAC SHAKE Digest Message 29 */ + __I uint32_t HMAC_SHAKEDGST30; /*!< [0x0578] SHA/HMAC SHAKE Digest Message 30 */ + __I uint32_t HMAC_SHAKEDGST31; /*!< [0x057c] SHA/HMAC SHAKE Digest Message 31 */ + __I uint32_t HMAC_SHAKEDGST32; /*!< [0x0580] SHA/HMAC SHAKE Digest Message 32 */ + __I uint32_t HMAC_SHAKEDGST33; /*!< [0x0584] SHA/HMAC SHAKE Digest Message 33 */ + __I uint32_t HMAC_SHAKEDGST34; /*!< [0x0588] SHA/HMAC SHAKE Digest Message 34 */ + __I uint32_t HMAC_SHAKEDGST35; /*!< [0x058c] SHA/HMAC SHAKE Digest Message 35 */ + __I uint32_t HMAC_SHAKEDGST36; /*!< [0x0590] SHA/HMAC SHAKE Digest Message 36 */ + __I uint32_t HMAC_SHAKEDGST37; /*!< [0x0594] SHA/HMAC SHAKE Digest Message 37 */ + __I uint32_t HMAC_SHAKEDGST38; /*!< [0x0598] SHA/HMAC SHAKE Digest Message 38 */ + __I uint32_t HMAC_SHAKEDGST39; /*!< [0x059c] SHA/HMAC SHAKE Digest Message 39 */ + __I uint32_t HMAC_SHAKEDGST40; /*!< [0x05a0] SHA/HMAC SHAKE Digest Message 40 */ + __I uint32_t HMAC_SHAKEDGST41; /*!< [0x05a4] SHA/HMAC SHAKE Digest Message 41 */ + __I uint32_t RESERVE6[150]; + __IO uint32_t ECC_CTL; /*!< [0x0800] ECC Control Register */ + __I uint32_t ECC_STS; /*!< [0x0804] ECC Status Register */ + __IO uint32_t ECC_X1_00; /*!< [0x0808] ECC the X-coordinate Word0 of the First Point */ + __IO uint32_t ECC_X1_01; /*!< [0x080c] ECC the X-coordinate Word1 of the First Point */ + __IO uint32_t ECC_X1_02; /*!< [0x0810] ECC the X-coordinate Word2 of the First Point */ + __IO uint32_t ECC_X1_03; /*!< [0x0814] ECC the X-coordinate Word3 of the First Point */ + __IO uint32_t ECC_X1_04; /*!< [0x0818] ECC the X-coordinate Word4 of the First Point */ + __IO uint32_t ECC_X1_05; /*!< [0x081c] ECC the X-coordinate Word5 of the First Point */ + __IO uint32_t ECC_X1_06; /*!< [0x0820] ECC the X-coordinate Word6 of the First Point */ + __IO uint32_t ECC_X1_07; /*!< [0x0824] ECC the X-coordinate Word7 of the First Point */ + __IO uint32_t ECC_X1_08; /*!< [0x0828] ECC the X-coordinate Word8 of the First Point */ + __IO uint32_t ECC_X1_09; /*!< [0x082c] ECC the X-coordinate Word9 of the First Point */ + __IO uint32_t ECC_X1_10; /*!< [0x0830] ECC the X-coordinate Word10 of the First Point */ + __IO uint32_t ECC_X1_11; /*!< [0x0834] ECC the X-coordinate Word11 of the First Point */ + __IO uint32_t ECC_X1_12; /*!< [0x0838] ECC the X-coordinate Word12 of the First Point */ + __IO uint32_t ECC_X1_13; /*!< [0x083c] ECC the X-coordinate Word13 of the First Point */ + __IO uint32_t ECC_X1_14; /*!< [0x0840] ECC the X-coordinate Word14 of the First Point */ + __IO uint32_t ECC_X1_15; /*!< [0x0844] ECC the X-coordinate Word15 of the First Point */ + __IO uint32_t ECC_X1_16; /*!< [0x0848] ECC the X-coordinate Word16 of the First Point */ + __IO uint32_t ECC_X1_17; /*!< [0x084c] ECC the X-coordinate Word17 of the First Point */ + __IO uint32_t ECC_Y1_00; /*!< [0x0850] ECC the Y-coordinate Word0 of the First Point */ + __IO uint32_t ECC_Y1_01; /*!< [0x0854] ECC the Y-coordinate Word1 of the First Point */ + __IO uint32_t ECC_Y1_02; /*!< [0x0858] ECC the Y-coordinate Word2 of the First Point */ + __IO uint32_t ECC_Y1_03; /*!< [0x085c] ECC the Y-coordinate Word3 of the First Point */ + __IO uint32_t ECC_Y1_04; /*!< [0x0860] ECC the Y-coordinate Word4 of the First Point */ + __IO uint32_t ECC_Y1_05; /*!< [0x0864] ECC the Y-coordinate Word5 of the First Point */ + __IO uint32_t ECC_Y1_06; /*!< [0x0868] ECC the Y-coordinate Word6 of the First Point */ + __IO uint32_t ECC_Y1_07; /*!< [0x086c] ECC the Y-coordinate Word7 of the First Point */ + __IO uint32_t ECC_Y1_08; /*!< [0x0870] ECC the Y-coordinate Word8 of the First Point */ + __IO uint32_t ECC_Y1_09; /*!< [0x0874] ECC the Y-coordinate Word9 of the First Point */ + __IO uint32_t ECC_Y1_10; /*!< [0x0878] ECC the Y-coordinate Word10 of the First Point */ + __IO uint32_t ECC_Y1_11; /*!< [0x087c] ECC the Y-coordinate Word11 of the First Point */ + __IO uint32_t ECC_Y1_12; /*!< [0x0880] ECC the Y-coordinate Word12 of the First Point */ + __IO uint32_t ECC_Y1_13; /*!< [0x0884] ECC the Y-coordinate Word13 of the First Point */ + __IO uint32_t ECC_Y1_14; /*!< [0x0888] ECC the Y-coordinate Word14 of the First Point */ + __IO uint32_t ECC_Y1_15; /*!< [0x088c] ECC the Y-coordinate Word15 of the First Point */ + __IO uint32_t ECC_Y1_16; /*!< [0x0890] ECC the Y-coordinate Word16 of the First Point */ + __IO uint32_t ECC_Y1_17; /*!< [0x0894] ECC the Y-coordinate Word17 of the First Point */ + __IO uint32_t ECC_X2_00; /*!< [0x0898] ECC the X-coordinate Word0 of the Second Point */ + __IO uint32_t ECC_X2_01; /*!< [0x089c] ECC the X-coordinate Word1 of the Second Point */ + __IO uint32_t ECC_X2_02; /*!< [0x08a0] ECC the X-coordinate Word2 of the Second Point */ + __IO uint32_t ECC_X2_03; /*!< [0x08a4] ECC the X-coordinate Word3 of the Second Point */ + __IO uint32_t ECC_X2_04; /*!< [0x08a8] ECC the X-coordinate Word4 of the Second Point */ + __IO uint32_t ECC_X2_05; /*!< [0x08ac] ECC the X-coordinate Word5 of the Second Point */ + __IO uint32_t ECC_X2_06; /*!< [0x08b0] ECC the X-coordinate Word6 of the Second Point */ + __IO uint32_t ECC_X2_07; /*!< [0x08b4] ECC the X-coordinate Word7 of the Second Point */ + __IO uint32_t ECC_X2_08; /*!< [0x08b8] ECC the X-coordinate Word8 of the Second Point */ + __IO uint32_t ECC_X2_09; /*!< [0x08bc] ECC the X-coordinate Word9 of the Second Point */ + __IO uint32_t ECC_X2_10; /*!< [0x08c0] ECC the X-coordinate Word10 of the Second Point */ + __IO uint32_t ECC_X2_11; /*!< [0x08c4] ECC the X-coordinate Word11 of the Second Point */ + __IO uint32_t ECC_X2_12; /*!< [0x08c8] ECC the X-coordinate Word12 of the Second Point */ + __IO uint32_t ECC_X2_13; /*!< [0x08cc] ECC the X-coordinate Word13 of the Second Point */ + __IO uint32_t ECC_X2_14; /*!< [0x08d0] ECC the X-coordinate Word14 of the Second Point */ + __IO uint32_t ECC_X2_15; /*!< [0x08d4] ECC the X-coordinate Word15 of the Second Point */ + __IO uint32_t ECC_X2_16; /*!< [0x08d8] ECC the X-coordinate Word16 of the Second Point */ + __IO uint32_t ECC_X2_17; /*!< [0x08dc] ECC the X-coordinate Word17 of the Second Point */ + __IO uint32_t ECC_Y2_00; /*!< [0x08e0] ECC the Y-coordinate Word0 of the Second Point */ + __IO uint32_t ECC_Y2_01; /*!< [0x08e4] ECC the Y-coordinate Word1 of the Second Point */ + __IO uint32_t ECC_Y2_02; /*!< [0x08e8] ECC the Y-coordinate Word2 of the Second Point */ + __IO uint32_t ECC_Y2_03; /*!< [0x08ec] ECC the Y-coordinate Word3 of the Second Point */ + __IO uint32_t ECC_Y2_04; /*!< [0x08f0] ECC the Y-coordinate Word4 of the Second Point */ + __IO uint32_t ECC_Y2_05; /*!< [0x08f4] ECC the Y-coordinate Word5 of the Second Point */ + __IO uint32_t ECC_Y2_06; /*!< [0x08f8] ECC the Y-coordinate Word6 of the Second Point */ + __IO uint32_t ECC_Y2_07; /*!< [0x08fc] ECC the Y-coordinate Word7 of the Second Point */ + __IO uint32_t ECC_Y2_08; /*!< [0x0900] ECC the Y-coordinate Word8 of the Second Point */ + __IO uint32_t ECC_Y2_09; /*!< [0x0904] ECC the Y-coordinate Word9 of the Second Point */ + __IO uint32_t ECC_Y2_10; /*!< [0x0908] ECC the Y-coordinate Word10 of the Second Point */ + __IO uint32_t ECC_Y2_11; /*!< [0x090c] ECC the Y-coordinate Word11 of the Second Point */ + __IO uint32_t ECC_Y2_12; /*!< [0x0910] ECC the Y-coordinate Word12 of the Second Point */ + __IO uint32_t ECC_Y2_13; /*!< [0x0914] ECC the Y-coordinate Word13 of the Second Point */ + __IO uint32_t ECC_Y2_14; /*!< [0x0918] ECC the Y-coordinate Word14 of the Second Point */ + __IO uint32_t ECC_Y2_15; /*!< [0x091c] ECC the Y-coordinate Word15 of the Second Point */ + __IO uint32_t ECC_Y2_16; /*!< [0x0920] ECC the Y-coordinate Word16 of the Second Point */ + __IO uint32_t ECC_Y2_17; /*!< [0x0924] ECC the Y-coordinate Word17 of the Second Point */ + __IO uint32_t ECC_A_00; /*!< [0x0928] ECC the Parameter CURVEA Word0 of Elliptic Curve */ + __IO uint32_t ECC_A_01; /*!< [0x092c] ECC the Parameter CURVEA Word1 of Elliptic Curve */ + __IO uint32_t ECC_A_02; /*!< [0x0930] ECC the Parameter CURVEA Word2 of Elliptic Curve */ + __IO uint32_t ECC_A_03; /*!< [0x0934] ECC the Parameter CURVEA Word3 of Elliptic Curve */ + __IO uint32_t ECC_A_04; /*!< [0x0938] ECC the Parameter CURVEA Word4 of Elliptic Curve */ + __IO uint32_t ECC_A_05; /*!< [0x093c] ECC the Parameter CURVEA Word5 of Elliptic Curve */ + __IO uint32_t ECC_A_06; /*!< [0x0940] ECC the Parameter CURVEA Word6 of Elliptic Curve */ + __IO uint32_t ECC_A_07; /*!< [0x0944] ECC the Parameter CURVEA Word7 of Elliptic Curve */ + __IO uint32_t ECC_A_08; /*!< [0x0948] ECC the Parameter CURVEA Word8 of Elliptic Curve */ + __IO uint32_t ECC_A_09; /*!< [0x094c] ECC the Parameter CURVEA Word9 of Elliptic Curve */ + __IO uint32_t ECC_A_10; /*!< [0x0950] ECC the Parameter CURVEA Word10 of Elliptic Curve */ + __IO uint32_t ECC_A_11; /*!< [0x0954] ECC the Parameter CURVEA Word11 of Elliptic Curve */ + __IO uint32_t ECC_A_12; /*!< [0x0958] ECC the Parameter CURVEA Word12 of Elliptic Curve */ + __IO uint32_t ECC_A_13; /*!< [0x095c] ECC the Parameter CURVEA Word13 of Elliptic Curve */ + __IO uint32_t ECC_A_14; /*!< [0x0960] ECC the Parameter CURVEA Word14 of Elliptic Curve */ + __IO uint32_t ECC_A_15; /*!< [0x0964] ECC the Parameter CURVEA Word15 of Elliptic Curve */ + __IO uint32_t ECC_A_16; /*!< [0x0968] ECC the Parameter CURVEA Word16 of Elliptic Curve */ + __IO uint32_t ECC_A_17; /*!< [0x096c] ECC the Parameter CURVEA Word17 of Elliptic Curve */ + __IO uint32_t ECC_B_00; /*!< [0x0970] ECC the Parameter CURVEB Word0 of Elliptic Curve */ + __IO uint32_t ECC_B_01; /*!< [0x0974] ECC the Parameter CURVEB Word1 of Elliptic Curve */ + __IO uint32_t ECC_B_02; /*!< [0x0978] ECC the Parameter CURVEB Word2 of Elliptic Curve */ + __IO uint32_t ECC_B_03; /*!< [0x097c] ECC the Parameter CURVEB Word3 of Elliptic Curve */ + __IO uint32_t ECC_B_04; /*!< [0x0980] ECC the Parameter CURVEB Word4 of Elliptic Curve */ + __IO uint32_t ECC_B_05; /*!< [0x0984] ECC the Parameter CURVEB Word5 of Elliptic Curve */ + __IO uint32_t ECC_B_06; /*!< [0x0988] ECC the Parameter CURVEB Word6 of Elliptic Curve */ + __IO uint32_t ECC_B_07; /*!< [0x098c] ECC the Parameter CURVEB Word7 of Elliptic Curve */ + __IO uint32_t ECC_B_08; /*!< [0x0990] ECC the Parameter CURVEB Word8 of Elliptic Curve */ + __IO uint32_t ECC_B_09; /*!< [0x0994] ECC the Parameter CURVEB Word9 of Elliptic Curve */ + __IO uint32_t ECC_B_10; /*!< [0x0998] ECC the Parameter CURVEB Word10 of Elliptic Curve */ + __IO uint32_t ECC_B_11; /*!< [0x099c] ECC the Parameter CURVEB Word11 of Elliptic Curve */ + __IO uint32_t ECC_B_12; /*!< [0x09a0] ECC the Parameter CURVEB Word12 of Elliptic Curve */ + __IO uint32_t ECC_B_13; /*!< [0x09a4] ECC the Parameter CURVEB Word13 of Elliptic Curve */ + __IO uint32_t ECC_B_14; /*!< [0x09a8] ECC the Parameter CURVEB Word14 of Elliptic Curve */ + __IO uint32_t ECC_B_15; /*!< [0x09ac] ECC the Parameter CURVEB Word15 of Elliptic Curve */ + __IO uint32_t ECC_B_16; /*!< [0x09b0] ECC the Parameter CURVEB Word16 of Elliptic Curve */ + __IO uint32_t ECC_B_17; /*!< [0x09b4] ECC the Parameter CURVEB Word17 of Elliptic Curve */ + __IO uint32_t ECC_N_00; /*!< [0x09b8] ECC the Parameter CURVEN Word0 of Elliptic Curve */ + __IO uint32_t ECC_N_01; /*!< [0x09bc] ECC the Parameter CURVEN Word1 of Elliptic Curve */ + __IO uint32_t ECC_N_02; /*!< [0x09c0] ECC the Parameter CURVEN Word2 of Elliptic Curve */ + __IO uint32_t ECC_N_03; /*!< [0x09c4] ECC the Parameter CURVEN Word3 of Elliptic Curve */ + __IO uint32_t ECC_N_04; /*!< [0x09c8] ECC the Parameter CURVEN Word4 of Elliptic Curve */ + __IO uint32_t ECC_N_05; /*!< [0x09cc] ECC the Parameter CURVEN Word5 of Elliptic Curve */ + __IO uint32_t ECC_N_06; /*!< [0x09d0] ECC the Parameter CURVEN Word6 of Elliptic Curve */ + __IO uint32_t ECC_N_07; /*!< [0x09d4] ECC the Parameter CURVEN Word7 of Elliptic Curve */ + __IO uint32_t ECC_N_08; /*!< [0x09d8] ECC the Parameter CURVEN Word8 of Elliptic Curve */ + __IO uint32_t ECC_N_09; /*!< [0x09dc] ECC the Parameter CURVEN Word9 of Elliptic Curve */ + __IO uint32_t ECC_N_10; /*!< [0x09e0] ECC the Parameter CURVEN Word10 of Elliptic Curve */ + __IO uint32_t ECC_N_11; /*!< [0x09e4] ECC the Parameter CURVEN Word11 of Elliptic Curve */ + __IO uint32_t ECC_N_12; /*!< [0x09e8] ECC the Parameter CURVEN Word12 of Elliptic Curve */ + __IO uint32_t ECC_N_13; /*!< [0x09ec] ECC the Parameter CURVEN Word13 of Elliptic Curve */ + __IO uint32_t ECC_N_14; /*!< [0x09f0] ECC the Parameter CURVEN Word14 of Elliptic Curve */ + __IO uint32_t ECC_N_15; /*!< [0x09f4] ECC the Parameter CURVEN Word15 of Elliptic Curve */ + __IO uint32_t ECC_N_16; /*!< [0x09f8] ECC the Parameter CURVEN Word16 of Elliptic Curve */ + __IO uint32_t ECC_N_17; /*!< [0x09fc] ECC the Parameter CURVEN Word17 of Elliptic Curve */ + __O uint32_t ECC_K_00; /*!< [0x0a00] ECC the Scalar SCALARK Word0 of Point Multiplication */ + __O uint32_t ECC_K_01; /*!< [0x0a04] ECC the Scalar SCALARK Word1 of Point Multiplication */ + __O uint32_t ECC_K_02; /*!< [0x0a08] ECC the Scalar SCALARK Word2 of Point Multiplication */ + __O uint32_t ECC_K_03; /*!< [0x0a0c] ECC the Scalar SCALARK Word3 of Point Multiplication */ + __O uint32_t ECC_K_04; /*!< [0x0a10] ECC the Scalar SCALARK Word4 of Point Multiplication */ + __O uint32_t ECC_K_05; /*!< [0x0a14] ECC the Scalar SCALARK Word5 of Point Multiplication */ + __O uint32_t ECC_K_06; /*!< [0x0a18] ECC the Scalar SCALARK Word6 of Point Multiplication */ + __O uint32_t ECC_K_07; /*!< [0x0a1c] ECC the Scalar SCALARK Word7 of Point Multiplication */ + __O uint32_t ECC_K_08; /*!< [0x0a20] ECC the Scalar SCALARK Word8 of Point Multiplication */ + __O uint32_t ECC_K_09; /*!< [0x0a24] ECC the Scalar SCALARK Word9 of Point Multiplication */ + __O uint32_t ECC_K_10; /*!< [0x0a28] ECC the Scalar SCALARK Word10 of Point Multiplication */ + __O uint32_t ECC_K_11; /*!< [0x0a2c] ECC the Scalar SCALARK Word11 of Point Multiplication */ + __O uint32_t ECC_K_12; /*!< [0x0a30] ECC the Scalar SCALARK Word12 of Point Multiplication */ + __O uint32_t ECC_K_13; /*!< [0x0a34] ECC the Scalar SCALARK Word13 of Point Multiplication */ + __O uint32_t ECC_K_14; /*!< [0x0a38] ECC the Scalar SCALARK Word14 of Point Multiplication */ + __O uint32_t ECC_K_15; /*!< [0x0a3c] ECC the Scalar SCALARK Word15 of Point Multiplication */ + __O uint32_t ECC_K_16; /*!< [0x0a40] ECC the Scalar SCALARK Word16 of Point Multiplication */ + __O uint32_t ECC_K_17; /*!< [0x0a44] ECC the Scalar SCALARK Word17 of Point Multiplication */ + __IO uint32_t ECC_SADDR; /*!< [0x0a48] ECC DMA Source Address Register */ + __IO uint32_t ECC_DADDR; /*!< [0x0a4c] ECC DMA Destination Address Register */ + __IO uint32_t ECC_STARTREG; /*!< [0x0a50] ECC Starting Address of Updated Registers */ + __IO uint32_t ECC_WORDCNT; /*!< [0x0a54] ECC DMA Word Count */ + __I uint32_t RESERVE7[42]; + __IO uint32_t RSA_CTL; /*!< [0x0b00] RSA Control Register */ + __I uint32_t RSA_STS; /*!< [0x0b04] RSA Status Register */ + __IO uint32_t RSA_SADDR0; /*!< [0x0b08] RSA DMA Source Address Register0 */ + __IO uint32_t RSA_SADDR1; /*!< [0x0b0c] RSA DMA Source Address Register1 */ + __IO uint32_t RSA_SADDR2; /*!< [0x0b10] RSA DMA Source Address Register2 */ + __IO uint32_t RSA_SADDR3; /*!< [0x0b14] RSA DMA Source Address Register3 */ + __IO uint32_t RSA_SADDR4; /*!< [0x0b18] RSA DMA Source Address Register4 */ + __IO uint32_t RSA_DADDR; /*!< [0x0b1c] RSA DMA Destination Address Register */ + __IO uint32_t RSA_MADDR0; /*!< [0x0b20] RSA DMA Middle Address Register0 */ + __IO uint32_t RSA_MADDR1; /*!< [0x0b24] RSA DMA Middle Address Register1 */ + __IO uint32_t RSA_MADDR2; /*!< [0x0b28] RSA DMA Middle Address Register2 */ + __IO uint32_t RSA_MADDR3; /*!< [0x0b2c] RSA DMA Middle Address Register3 */ + __IO uint32_t RSA_MADDR4; /*!< [0x0b30] RSA DMA Middle Address Register4 */ + __IO uint32_t RSA_MADDR5; /*!< [0x0b34] RSA DMA Middle Address Register5 */ + __IO uint32_t RSA_MADDR6; /*!< [0x0b38] RSA DMA Middle Address Register6 */ + __I uint32_t RESERVE8[241]; + __O uint32_t PRNG_KSCTL; /*!< [0x0f00] PRNG Key Control Register */ + __I uint32_t PRNG_KSSTS; /*!< [0x0f04] PRNG Key Status Register */ + __I uint32_t RESERVE9[2]; + __O uint32_t AES_KSCTL; /*!< [0x0f10] AES Key Control Register */ + __I uint32_t RESERVE10[7]; + __O uint32_t HMAC_KSCTL; /*!< [0x0f30] HMAC Key Control Register */ + __I uint32_t RESERVE11[3]; + __O uint32_t ECC_KSCTL; /*!< [0x0f40] ECC Key Control Register */ + __I uint32_t ECC_KSSTS; /*!< [0x0f44] ECC Key Status Register */ + __O uint32_t ECC_KSXY; /*!< [0x0f48] ECC XY Number Register */ + __I uint32_t RESERVE12[1]; + __O uint32_t RSA_KSCTL; /*!< [0x0f50] RSA Key Control Register */ + __IO uint32_t RSA_KSSTS0; /*!< [0x0f54] RSA Key Status Register 0 */ + __IO uint32_t RSA_KSSTS1; /*!< [0x0f58] RSA Key Status Register 1 */ + +} CRYPTO_T; + +/** + @addtogroup CRYPTO_CONST CRYPTO Bit Field Definition + Constant Definitions for CRYPTO Controller +@{ */ + +#define CRYPTO_INTEN_AESIEN_Pos (0) /*!< CRYPTO_T::INTEN: AESIEN Position */ +#define CRYPTO_INTEN_AESIEN_Msk (0x1ul << CRYPTO_INTEN_AESIEN_Pos) /*!< CRYPTO_T::INTEN: AESIEN Mask */ + +#define CRYPTO_INTEN_AESEIEN_Pos (1) /*!< CRYPTO_T::INTEN: AESEIEN Position */ +#define CRYPTO_INTEN_AESEIEN_Msk (0x1ul << CRYPTO_INTEN_AESEIEN_Pos) /*!< CRYPTO_T::INTEN: AESEIEN Mask */ + +#define CRYPTO_INTEN_PRNGIEN_Pos (16) /*!< CRYPTO_T::INTEN: PRNGIEN Position */ +#define CRYPTO_INTEN_PRNGIEN_Msk (0x1ul << CRYPTO_INTEN_PRNGIEN_Pos) /*!< CRYPTO_T::INTEN: PRNGIEN Mask */ + +#define CRYPTO_INTEN_PRNGEIEN_Pos (17) /*!< CRYPTO_T::INTEN: PRNGEIEN Position */ +#define CRYPTO_INTEN_PRNGEIEN_Msk (0x1ul << CRYPTO_INTEN_PRNGEIEN_Pos) /*!< CRYPTO_T::INTEN: PRNGEIEN Mask */ + +#define CRYPTO_INTEN_ECCIEN_Pos (22) /*!< CRYPTO_T::INTEN: ECCIEN Position */ +#define CRYPTO_INTEN_ECCIEN_Msk (0x1ul << CRYPTO_INTEN_ECCIEN_Pos) /*!< CRYPTO_T::INTEN: ECCIEN Mask */ + +#define CRYPTO_INTEN_ECCEIEN_Pos (23) /*!< CRYPTO_T::INTEN: ECCEIEN Position */ +#define CRYPTO_INTEN_ECCEIEN_Msk (0x1ul << CRYPTO_INTEN_ECCEIEN_Pos) /*!< CRYPTO_T::INTEN: ECCEIEN Mask */ + +#define CRYPTO_INTEN_HMACIEN_Pos (24) /*!< CRYPTO_T::INTEN: HMACIEN Position */ +#define CRYPTO_INTEN_HMACIEN_Msk (0x1ul << CRYPTO_INTEN_HMACIEN_Pos) /*!< CRYPTO_T::INTEN: HMACIEN Mask */ + +#define CRYPTO_INTEN_HMACEIEN_Pos (25) /*!< CRYPTO_T::INTEN: HMACEIEN Position */ +#define CRYPTO_INTEN_HMACEIEN_Msk (0x1ul << CRYPTO_INTEN_HMACEIEN_Pos) /*!< CRYPTO_T::INTEN: HMACEIEN Mask */ + +#define CRYPTO_INTEN_RSAIEN_Pos (30) /*!< CRYPTO_T::INTEN: RSAIEN Position */ +#define CRYPTO_INTEN_RSAIEN_Msk (0x1ul << CRYPTO_INTEN_RSAIEN_Pos) /*!< CRYPTO_T::INTEN: RSAIEN Mask */ + +#define CRYPTO_INTEN_RSAEIEN_Pos (31) /*!< CRYPTO_T::INTEN: RSAEIEN Position */ +#define CRYPTO_INTEN_RSAEIEN_Msk (0x1ul << CRYPTO_INTEN_RSAEIEN_Pos) /*!< CRYPTO_T::INTEN: RSAEIEN Mask */ + +#define CRYPTO_INTSTS_AESIF_Pos (0) /*!< CRYPTO_T::INTSTS: AESIF Position */ +#define CRYPTO_INTSTS_AESIF_Msk (0x1ul << CRYPTO_INTSTS_AESIF_Pos) /*!< CRYPTO_T::INTSTS: AESIF Mask */ + +#define CRYPTO_INTSTS_AESEIF_Pos (1) /*!< CRYPTO_T::INTSTS: AESEIF Position */ +#define CRYPTO_INTSTS_AESEIF_Msk (0x1ul << CRYPTO_INTSTS_AESEIF_Pos) /*!< CRYPTO_T::INTSTS: AESEIF Mask */ + +#define CRYPTO_INTSTS_PRNGIF_Pos (16) /*!< CRYPTO_T::INTSTS: PRNGIF Position */ +#define CRYPTO_INTSTS_PRNGIF_Msk (0x1ul << CRYPTO_INTSTS_PRNGIF_Pos) /*!< CRYPTO_T::INTSTS: PRNGIF Mask */ + +#define CRYPTO_INTSTS_PRNGEIF_Pos (17) /*!< CRYPTO_T::INTSTS: PRNGEIF Position */ +#define CRYPTO_INTSTS_PRNGEIF_Msk (0x1ul << CRYPTO_INTSTS_PRNGEIF_Pos) /*!< CRYPTO_T::INTSTS: PRNGEIF Mask */ + +#define CRYPTO_INTSTS_ECCIF_Pos (22) /*!< CRYPTO_T::INTSTS: ECCIF Position */ +#define CRYPTO_INTSTS_ECCIF_Msk (0x1ul << CRYPTO_INTSTS_ECCIF_Pos) /*!< CRYPTO_T::INTSTS: ECCIF Mask */ + +#define CRYPTO_INTSTS_ECCEIF_Pos (23) /*!< CRYPTO_T::INTSTS: ECCEIF Position */ +#define CRYPTO_INTSTS_ECCEIF_Msk (0x1ul << CRYPTO_INTSTS_ECCEIF_Pos) /*!< CRYPTO_T::INTSTS: ECCEIF Mask */ + +#define CRYPTO_INTSTS_HMACIF_Pos (24) /*!< CRYPTO_T::INTSTS: HMACIF Position */ +#define CRYPTO_INTSTS_HMACIF_Msk (0x1ul << CRYPTO_INTSTS_HMACIF_Pos) /*!< CRYPTO_T::INTSTS: HMACIF Mask */ + +#define CRYPTO_INTSTS_HMACEIF_Pos (25) /*!< CRYPTO_T::INTSTS: HMACEIF Position */ +#define CRYPTO_INTSTS_HMACEIF_Msk (0x1ul << CRYPTO_INTSTS_HMACEIF_Pos) /*!< CRYPTO_T::INTSTS: HMACEIF Mask */ + +#define CRYPTO_INTSTS_RSAIF_Pos (30) /*!< CRYPTO_T::INTSTS: RSAIF Position */ +#define CRYPTO_INTSTS_RSAIF_Msk (0x1ul << CRYPTO_INTSTS_RSAIF_Pos) /*!< CRYPTO_T::INTSTS: RSAIF Mask */ + +#define CRYPTO_INTSTS_RSAEIF_Pos (31) /*!< CRYPTO_T::INTSTS: RSAEIF Position */ +#define CRYPTO_INTSTS_RSAEIF_Msk (0x1ul << CRYPTO_INTSTS_RSAEIF_Pos) /*!< CRYPTO_T::INTSTS: RSAEIF Mask */ + +#define CRYPTO_PRNG_CTL_START_Pos (0) /*!< CRYPTO_T::PRNG_CTL: START Position */ +#define CRYPTO_PRNG_CTL_START_Msk (0x1ul << CRYPTO_PRNG_CTL_START_Pos) /*!< CRYPTO_T::PRNG_CTL: START Mask */ + +#define CRYPTO_PRNG_CTL_SEEDRLD_Pos (1) /*!< CRYPTO_T::PRNG_CTL: SEEDRLD Position */ +#define CRYPTO_PRNG_CTL_SEEDRLD_Msk (0x1ul << CRYPTO_PRNG_CTL_SEEDRLD_Pos) /*!< CRYPTO_T::PRNG_CTL: SEEDRLD Mask */ + +#define CRYPTO_PRNG_CTL_KEYSZ_Pos (2) /*!< CRYPTO_T::PRNG_CTL: KEYSZ Position */ +#define CRYPTO_PRNG_CTL_KEYSZ_Msk (0xful << CRYPTO_PRNG_CTL_KEYSZ_Pos) /*!< CRYPTO_T::PRNG_CTL: KEYSZ Mask */ + +#define CRYPTO_PRNG_CTL_BUSY_Pos (8) /*!< CRYPTO_T::PRNG_CTL: BUSY Position */ +#define CRYPTO_PRNG_CTL_BUSY_Msk (0x1ul << CRYPTO_PRNG_CTL_BUSY_Pos) /*!< CRYPTO_T::PRNG_CTL: BUSY Mask */ + +#define CRYPTO_PRNG_CTL_SEEDSRC_Pos (16) /*!< CRYPTO_T::PRNG_CTL: SEEDSRC Position */ +#define CRYPTO_PRNG_CTL_SEEDSRC_Msk (0x1ul << CRYPTO_PRNG_CTL_SEEDSRC_Pos) /*!< CRYPTO_T::PRNG_CTL: SEEDSRC Mask */ + +#define CRYPTO_PRNG_SEED_SEED_Pos (0) /*!< CRYPTO_T::PRNG_SEED: SEED Position */ +#define CRYPTO_PRNG_SEED_SEED_Msk (0xfffffffful << CRYPTO_PRNG_SEED_SEED_Pos) /*!< CRYPTO_T::PRNG_SEED: SEED Mask */ + +#define CRYPTO_PRNG_KEY0_KEY_Pos (0) /*!< CRYPTO_T::PRNG_KEY0: KEY Position */ +#define CRYPTO_PRNG_KEY0_KEY_Msk (0xfffffffful << CRYPTO_PRNG_KEY0_KEY_Pos) /*!< CRYPTO_T::PRNG_KEY0: KEY Mask */ + +#define CRYPTO_PRNG_KEY1_KEY_Pos (0) /*!< CRYPTO_T::PRNG_KEY1: KEY Position */ +#define CRYPTO_PRNG_KEY1_KEY_Msk (0xfffffffful << CRYPTO_PRNG_KEY1_KEY_Pos) /*!< CRYPTO_T::PRNG_KEY1: KEY Mask */ + +#define CRYPTO_PRNG_KEY2_KEY_Pos (0) /*!< CRYPTO_T::PRNG_KEY2: KEY Position */ +#define CRYPTO_PRNG_KEY2_KEY_Msk (0xfffffffful << CRYPTO_PRNG_KEY2_KEY_Pos) /*!< CRYPTO_T::PRNG_KEY2: KEY Mask */ + +#define CRYPTO_PRNG_KEY3_KEY_Pos (0) /*!< CRYPTO_T::PRNG_KEY3: KEY Position */ +#define CRYPTO_PRNG_KEY3_KEY_Msk (0xfffffffful << CRYPTO_PRNG_KEY3_KEY_Pos) /*!< CRYPTO_T::PRNG_KEY3: KEY Mask */ + +#define CRYPTO_PRNG_KEY4_KEY_Pos (0) /*!< CRYPTO_T::PRNG_KEY4: KEY Position */ +#define CRYPTO_PRNG_KEY4_KEY_Msk (0xfffffffful << CRYPTO_PRNG_KEY4_KEY_Pos) /*!< CRYPTO_T::PRNG_KEY4: KEY Mask */ + +#define CRYPTO_PRNG_KEY5_KEY_Pos (0) /*!< CRYPTO_T::PRNG_KEY5: KEY Position */ +#define CRYPTO_PRNG_KEY5_KEY_Msk (0xfffffffful << CRYPTO_PRNG_KEY5_KEY_Pos) /*!< CRYPTO_T::PRNG_KEY5: KEY Mask */ + +#define CRYPTO_PRNG_KEY6_KEY_Pos (0) /*!< CRYPTO_T::PRNG_KEY6: KEY Position */ +#define CRYPTO_PRNG_KEY6_KEY_Msk (0xfffffffful << CRYPTO_PRNG_KEY6_KEY_Pos) /*!< CRYPTO_T::PRNG_KEY6: KEY Mask */ + +#define CRYPTO_PRNG_KEY7_KEY_Pos (0) /*!< CRYPTO_T::PRNG_KEY7: KEY Position */ +#define CRYPTO_PRNG_KEY7_KEY_Msk (0xfffffffful << CRYPTO_PRNG_KEY7_KEY_Pos) /*!< CRYPTO_T::PRNG_KEY7: KEY Mask */ + +#define CRYPTO_PRNG_STS_BUSY_Pos (0) /*!< CRYPTO_T::PRNG_STS: BUSY Position */ +#define CRYPTO_PRNG_STS_BUSY_Msk (0x1ul << CRYPTO_PRNG_STS_BUSY_Pos) /*!< CRYPTO_T::PRNG_STS: BUSY Mask */ + +#define CRYPTO_PRNG_STS_KCTLERR_Pos (16) /*!< CRYPTO_T::PRNG_STS: KCTLERR Position */ +#define CRYPTO_PRNG_STS_KCTLERR_Msk (0x1ul << CRYPTO_PRNG_STS_KCTLERR_Pos) /*!< CRYPTO_T::PRNG_STS: KCTLERR Mask */ + +#define CRYPTO_PRNG_STS_KSERR_Pos (17) /*!< CRYPTO_T::PRNG_STS: KSERR Position */ +#define CRYPTO_PRNG_STS_KSERR_Msk (0x1ul << CRYPTO_PRNG_STS_KSERR_Pos) /*!< CRYPTO_T::PRNG_STS: KSERR Mask */ + +#define CRYPTO_PRNG_STS_TRNGERR_Pos (18) /*!< CRYPTO_T::PRNG_STS: TRNGERR Position */ +#define CRYPTO_PRNG_STS_TRNGERR_Msk (0x1ul << CRYPTO_PRNG_STS_TRNGERR_Pos) /*!< CRYPTO_T::PRNG_STS: TRNGERR Mask */ + +#define CRYPTO_AES_FDBCK0_FDBCK_Pos (0) /*!< CRYPTO_T::AES_FDBCK0: FDBCK Position */ +#define CRYPTO_AES_FDBCK0_FDBCK_Msk (0xfffffffful << CRYPTO_AES_FDBCK0_FDBCK_Pos) /*!< CRYPTO_T::AES_FDBCK0: FDBCK Mask */ + +#define CRYPTO_AES_FDBCK1_FDBCK_Pos (0) /*!< CRYPTO_T::AES_FDBCK1: FDBCK Position */ +#define CRYPTO_AES_FDBCK1_FDBCK_Msk (0xfffffffful << CRYPTO_AES_FDBCK1_FDBCK_Pos) /*!< CRYPTO_T::AES_FDBCK1: FDBCK Mask */ + +#define CRYPTO_AES_FDBCK2_FDBCK_Pos (0) /*!< CRYPTO_T::AES_FDBCK2: FDBCK Position */ +#define CRYPTO_AES_FDBCK2_FDBCK_Msk (0xfffffffful << CRYPTO_AES_FDBCK2_FDBCK_Pos) /*!< CRYPTO_T::AES_FDBCK2: FDBCK Mask */ + +#define CRYPTO_AES_FDBCK3_FDBCK_Pos (0) /*!< CRYPTO_T::AES_FDBCK3: FDBCK Position */ +#define CRYPTO_AES_FDBCK3_FDBCK_Msk (0xfffffffful << CRYPTO_AES_FDBCK3_FDBCK_Pos) /*!< CRYPTO_T::AES_FDBCK3: FDBCK Mask */ + +#define CRYPTO_AES_GCM_IVCNT0_CNT_Pos (0) /*!< CRYPTO_T::AES_GCM_IVCNT0: CNT Position */ +#define CRYPTO_AES_GCM_IVCNT0_CNT_Msk (0xfffffffful << CRYPTO_AES_GCM_IVCNT0_CNT_Pos) /*!< CRYPTO_T::AES_GCM_IVCNT0: CNT Mask */ + +#define CRYPTO_AES_GCM_IVCNT1_CNT_Pos (0) /*!< CRYPTO_T::AES_GCM_IVCNT1: CNT Position */ +#define CRYPTO_AES_GCM_IVCNT1_CNT_Msk (0x1ffffffful << CRYPTO_AES_GCM_IVCNT1_CNT_Pos) /*!< CRYPTO_T::AES_GCM_IVCNT1: CNT Mask */ + +#define CRYPTO_AES_GCM_ACNT0_CNT_Pos (0) /*!< CRYPTO_T::AES_GCM_ACNT0: CNT Position */ +#define CRYPTO_AES_GCM_ACNT0_CNT_Msk (0xfffffffful << CRYPTO_AES_GCM_ACNT0_CNT_Pos) /*!< CRYPTO_T::AES_GCM_ACNT0: CNT Mask */ + +#define CRYPTO_AES_GCM_ACNT1_CNT_Pos (0) /*!< CRYPTO_T::AES_GCM_ACNT1: CNT Position */ +#define CRYPTO_AES_GCM_ACNT1_CNT_Msk (0x1ffffffful << CRYPTO_AES_GCM_ACNT1_CNT_Pos) /*!< CRYPTO_T::AES_GCM_ACNT1: CNT Mask */ + +#define CRYPTO_AES_GCM_PCNT0_CNT_Pos (0) /*!< CRYPTO_T::AES_GCM_PCNT0: CNT Position */ +#define CRYPTO_AES_GCM_PCNT0_CNT_Msk (0xfffffffful << CRYPTO_AES_GCM_PCNT0_CNT_Pos) /*!< CRYPTO_T::AES_GCM_PCNT0: CNT Mask */ + +#define CRYPTO_AES_GCM_PCNT1_CNT_Pos (0) /*!< CRYPTO_T::AES_GCM_PCNT1: CNT Position */ +#define CRYPTO_AES_GCM_PCNT1_CNT_Msk (0x1ffffffful << CRYPTO_AES_GCM_PCNT1_CNT_Pos) /*!< CRYPTO_T::AES_GCM_PCNT1: CNT Mask */ + +#define CRYPTO_AES_FBADDR_FBADDR_Pos (0) /*!< CRYPTO_T::AES_FBADDR: FBADDR Position */ +#define CRYPTO_AES_FBADDR_FBADDR_Msk (0xfffffffful << CRYPTO_AES_FBADDR_FBADDR_Pos) /*!< CRYPTO_T::AES_FBADDR: FBADDR Mask */ + +#define CRYPTO_AES_CTL_START_Pos (0) /*!< CRYPTO_T::AES_CTL: START Position */ +#define CRYPTO_AES_CTL_START_Msk (0x1ul << CRYPTO_AES_CTL_START_Pos) /*!< CRYPTO_T::AES_CTL: START Mask */ + +#define CRYPTO_AES_CTL_STOP_Pos (1) /*!< CRYPTO_T::AES_CTL: STOP Position */ +#define CRYPTO_AES_CTL_STOP_Msk (0x1ul << CRYPTO_AES_CTL_STOP_Pos) /*!< CRYPTO_T::AES_CTL: STOP Mask */ + +#define CRYPTO_AES_CTL_KEYSZ_Pos (2) /*!< CRYPTO_T::AES_CTL: KEYSZ Position */ +#define CRYPTO_AES_CTL_KEYSZ_Msk (0x3ul << CRYPTO_AES_CTL_KEYSZ_Pos) /*!< CRYPTO_T::AES_CTL: KEYSZ Mask */ + +#define CRYPTO_AES_CTL_DMALAST_Pos (5) /*!< CRYPTO_T::AES_CTL: DMALAST Position */ +#define CRYPTO_AES_CTL_DMALAST_Msk (0x1ul << CRYPTO_AES_CTL_DMALAST_Pos) /*!< CRYPTO_T::AES_CTL: DMALAST Mask */ + +#define CRYPTO_AES_CTL_DMACSCAD_Pos (6) /*!< CRYPTO_T::AES_CTL: DMACSCAD Position */ +#define CRYPTO_AES_CTL_DMACSCAD_Msk (0x1ul << CRYPTO_AES_CTL_DMACSCAD_Pos) /*!< CRYPTO_T::AES_CTL: DMACSCAD Mask */ + +#define CRYPTO_AES_CTL_DMAEN_Pos (7) /*!< CRYPTO_T::AES_CTL: DMAEN Position */ +#define CRYPTO_AES_CTL_DMAEN_Msk (0x1ul << CRYPTO_AES_CTL_DMAEN_Pos) /*!< CRYPTO_T::AES_CTL: DMAEN Mask */ + +#define CRYPTO_AES_CTL_OPMODE_Pos (8) /*!< CRYPTO_T::AES_CTL: OPMODE Position */ +#define CRYPTO_AES_CTL_OPMODE_Msk (0xfful << CRYPTO_AES_CTL_OPMODE_Pos) /*!< CRYPTO_T::AES_CTL: OPMODE Mask */ + +#define CRYPTO_AES_CTL_ENCRYPTO_Pos (16) /*!< CRYPTO_T::AES_CTL: ENCRYPTO Position */ +#define CRYPTO_AES_CTL_ENCRYPTO_Msk (0x1ul << CRYPTO_AES_CTL_ENCRYPTO_Pos) /*!< CRYPTO_T::AES_CTL: ENCRYPTO Mask */ + +#define CRYPTO_AES_CTL_SM4EN_Pos (17) /*!< CRYPTO_T::AES_CTL: SM4EN Position */ +#define CRYPTO_AES_CTL_SM4EN_Msk (0x1ul << CRYPTO_AES_CTL_SM4EN_Pos) /*!< CRYPTO_T::AES_CTL: SM4EN Mask */ + +#define CRYPTO_AES_CTL_DFAPEN_Pos (19) /*!< CRYPTO_T::AES_CTL: DFAPEN Position */ +#define CRYPTO_AES_CTL_DFAPEN_Msk (0x1ul << CRYPTO_AES_CTL_DFAPEN_Pos) /*!< CRYPTO_T::AES_CTL: DFAPEN Mask */ + +#define CRYPTO_AES_CTL_FBIN_Pos (20) /*!< CRYPTO_T::AES_CTL: FBIN Position */ +#define CRYPTO_AES_CTL_FBIN_Msk (0x1ul << CRYPTO_AES_CTL_FBIN_Pos) /*!< CRYPTO_T::AES_CTL: FBIN Mask */ + +#define CRYPTO_AES_CTL_FBOUT_Pos (21) /*!< CRYPTO_T::AES_CTL: FBOUT Position */ +#define CRYPTO_AES_CTL_FBOUT_Msk (0x1ul << CRYPTO_AES_CTL_FBOUT_Pos) /*!< CRYPTO_T::AES_CTL: FBOUT Mask */ + +#define CRYPTO_AES_CTL_OUTSWAP_Pos (22) /*!< CRYPTO_T::AES_CTL: OUTSWAP Position */ +#define CRYPTO_AES_CTL_OUTSWAP_Msk (0x1ul << CRYPTO_AES_CTL_OUTSWAP_Pos) /*!< CRYPTO_T::AES_CTL: OUTSWAP Mask */ + +#define CRYPTO_AES_CTL_INSWAP_Pos (23) /*!< CRYPTO_T::AES_CTL: INSWAP Position */ +#define CRYPTO_AES_CTL_INSWAP_Msk (0x1ul << CRYPTO_AES_CTL_INSWAP_Pos) /*!< CRYPTO_T::AES_CTL: INSWAP Mask */ + +#define CRYPTO_AES_CTL_KOUTSWAP_Pos (24) /*!< CRYPTO_T::AES_CTL: KOUTSWAP Position */ +#define CRYPTO_AES_CTL_KOUTSWAP_Msk (0x1ul << CRYPTO_AES_CTL_KOUTSWAP_Pos) /*!< CRYPTO_T::AES_CTL: KOUTSWAP Mask */ + +#define CRYPTO_AES_CTL_KINSWAP_Pos (25) /*!< CRYPTO_T::AES_CTL: KINSWAP Position */ +#define CRYPTO_AES_CTL_KINSWAP_Msk (0x1ul << CRYPTO_AES_CTL_KINSWAP_Pos) /*!< CRYPTO_T::AES_CTL: KINSWAP Mask */ + +#define CRYPTO_AES_CTL_KEYUNPRT_Pos (26) /*!< CRYPTO_T::AES_CTL: KEYUNPRT Position */ +#define CRYPTO_AES_CTL_KEYUNPRT_Msk (0x1ful << CRYPTO_AES_CTL_KEYUNPRT_Pos) /*!< CRYPTO_T::AES_CTL: KEYUNPRT Mask */ + +#define CRYPTO_AES_CTL_KEYPRT_Pos (31) /*!< CRYPTO_T::AES_CTL: KEYPRT Position */ +#define CRYPTO_AES_CTL_KEYPRT_Msk (0x1ul << CRYPTO_AES_CTL_KEYPRT_Pos) /*!< CRYPTO_T::AES_CTL: KEYPRT Mask */ + +#define CRYPTO_AES_STS_BUSY_Pos (0) /*!< CRYPTO_T::AES_STS: BUSY Position */ +#define CRYPTO_AES_STS_BUSY_Msk (0x1ul << CRYPTO_AES_STS_BUSY_Pos) /*!< CRYPTO_T::AES_STS: BUSY Mask */ + +#define CRYPTO_AES_STS_INBUFEMPTY_Pos (8) /*!< CRYPTO_T::AES_STS: INBUFEMPTY Position */ +#define CRYPTO_AES_STS_INBUFEMPTY_Msk (0x1ul << CRYPTO_AES_STS_INBUFEMPTY_Pos) /*!< CRYPTO_T::AES_STS: INBUFEMPTY Mask */ + +#define CRYPTO_AES_STS_INBUFFULL_Pos (9) /*!< CRYPTO_T::AES_STS: INBUFFULL Position */ +#define CRYPTO_AES_STS_INBUFFULL_Msk (0x1ul << CRYPTO_AES_STS_INBUFFULL_Pos) /*!< CRYPTO_T::AES_STS: INBUFFULL Mask */ + +#define CRYPTO_AES_STS_INBUFERR_Pos (10) /*!< CRYPTO_T::AES_STS: INBUFERR Position */ +#define CRYPTO_AES_STS_INBUFERR_Msk (0x1ul << CRYPTO_AES_STS_INBUFERR_Pos) /*!< CRYPTO_T::AES_STS: INBUFERR Mask */ + +#define CRYPTO_AES_STS_CNTERR_Pos (12) /*!< CRYPTO_T::AES_STS: CNTERR Position */ +#define CRYPTO_AES_STS_CNTERR_Msk (0x1ul << CRYPTO_AES_STS_CNTERR_Pos) /*!< CRYPTO_T::AES_STS: CNTERR Mask */ + +#define CRYPTO_AES_STS_OUTBUFEMPTY_Pos (16) /*!< CRYPTO_T::AES_STS: OUTBUFEMPTY Position*/ +#define CRYPTO_AES_STS_OUTBUFEMPTY_Msk (0x1ul << CRYPTO_AES_STS_OUTBUFEMPTY_Pos) /*!< CRYPTO_T::AES_STS: OUTBUFEMPTY Mask */ + +#define CRYPTO_AES_STS_OUTBUFFULL_Pos (17) /*!< CRYPTO_T::AES_STS: OUTBUFFULL Position */ +#define CRYPTO_AES_STS_OUTBUFFULL_Msk (0x1ul << CRYPTO_AES_STS_OUTBUFFULL_Pos) /*!< CRYPTO_T::AES_STS: OUTBUFFULL Mask */ + +#define CRYPTO_AES_STS_OUTBUFERR_Pos (18) /*!< CRYPTO_T::AES_STS: OUTBUFERR Position */ +#define CRYPTO_AES_STS_OUTBUFERR_Msk (0x1ul << CRYPTO_AES_STS_OUTBUFERR_Pos) /*!< CRYPTO_T::AES_STS: OUTBUFERR Mask */ + +#define CRYPTO_AES_STS_BUSERR_Pos (20) /*!< CRYPTO_T::AES_STS: BUSERR Position */ +#define CRYPTO_AES_STS_BUSERR_Msk (0x1ul << CRYPTO_AES_STS_BUSERR_Pos) /*!< CRYPTO_T::AES_STS: BUSERR Mask */ + +#define CRYPTO_AES_STS_KSERR_Pos (21) /*!< CRYPTO_T::AES_STS: KSERR Position */ +#define CRYPTO_AES_STS_KSERR_Msk (0x1ul << CRYPTO_AES_STS_KSERR_Pos) /*!< CRYPTO_T::AES_STS: KSERR Mask */ + +#define CRYPTO_AES_STS_DFAERR_Pos (22) /*!< CRYPTO_T::AES_STS: DFAERR Position */ +#define CRYPTO_AES_STS_DFAERR_Msk (0x1ul << CRYPTO_AES_STS_DFAERR_Pos) /*!< CRYPTO_T::AES_STS: DFAERR Mask */ + +#define CRYPTO_AES_DATIN_DATIN_Pos (0) /*!< CRYPTO_T::AES_DATIN: DATIN Position */ +#define CRYPTO_AES_DATIN_DATIN_Msk (0xfffffffful << CRYPTO_AES_DATIN_DATIN_Pos) /*!< CRYPTO_T::AES_DATIN: DATIN Mask */ + +#define CRYPTO_AES_DATOUT_DATOUT_Pos (0) /*!< CRYPTO_T::AES_DATOUT: DATOUT Position */ +#define CRYPTO_AES_DATOUT_DATOUT_Msk (0xfffffffful << CRYPTO_AES_DATOUT_DATOUT_Pos) /*!< CRYPTO_T::AES_DATOUT: DATOUT Mask */ + +#define CRYPTO_AES_KEY0_KEY_Pos (0) /*!< CRYPTO_T::AES_KEY0: KEY Position */ +#define CRYPTO_AES_KEY0_KEY_Msk (0xfffffffful << CRYPTO_AES_KEY0_KEY_Pos) /*!< CRYPTO_T::AES_KEY0: KEY Mask */ + +#define CRYPTO_AES_KEY1_KEY_Pos (0) /*!< CRYPTO_T::AES_KEY1: KEY Position */ +#define CRYPTO_AES_KEY1_KEY_Msk (0xfffffffful << CRYPTO_AES_KEY1_KEY_Pos) /*!< CRYPTO_T::AES_KEY1: KEY Mask */ + +#define CRYPTO_AES_KEY2_KEY_Pos (0) /*!< CRYPTO_T::AES_KEY2: KEY Position */ +#define CRYPTO_AES_KEY2_KEY_Msk (0xfffffffful << CRYPTO_AES_KEY2_KEY_Pos) /*!< CRYPTO_T::AES_KEY2: KEY Mask */ + +#define CRYPTO_AES_KEY3_KEY_Pos (0) /*!< CRYPTO_T::AES_KEY3: KEY Position */ +#define CRYPTO_AES_KEY3_KEY_Msk (0xfffffffful << CRYPTO_AES_KEY3_KEY_Pos) /*!< CRYPTO_T::AES_KEY3: KEY Mask */ + +#define CRYPTO_AES_KEY4_KEY_Pos (0) /*!< CRYPTO_T::AES_KEY4: KEY Position */ +#define CRYPTO_AES_KEY4_KEY_Msk (0xfffffffful << CRYPTO_AES_KEY4_KEY_Pos) /*!< CRYPTO_T::AES_KEY4: KEY Mask */ + +#define CRYPTO_AES_KEY5_KEY_Pos (0) /*!< CRYPTO_T::AES_KEY5: KEY Position */ +#define CRYPTO_AES_KEY5_KEY_Msk (0xfffffffful << CRYPTO_AES_KEY5_KEY_Pos) /*!< CRYPTO_T::AES_KEY5: KEY Mask */ + +#define CRYPTO_AES_KEY6_KEY_Pos (0) /*!< CRYPTO_T::AES_KEY6: KEY Position */ +#define CRYPTO_AES_KEY6_KEY_Msk (0xfffffffful << CRYPTO_AES_KEY6_KEY_Pos) /*!< CRYPTO_T::AES_KEY6: KEY Mask */ + +#define CRYPTO_AES_KEY7_KEY_Pos (0) /*!< CRYPTO_T::AES_KEY7: KEY Position */ +#define CRYPTO_AES_KEY7_KEY_Msk (0xfffffffful << CRYPTO_AES_KEY7_KEY_Pos) /*!< CRYPTO_T::AES_KEY7: KEY Mask */ + +#define CRYPTO_AES_IV0_IV_Pos (0) /*!< CRYPTO_T::AES_IV0: IV Position */ +#define CRYPTO_AES_IV0_IV_Msk (0xfffffffful << CRYPTO_AES_IV0_IV_Pos) /*!< CRYPTO_T::AES_IV0: IV Mask */ + +#define CRYPTO_AES_IV1_IV_Pos (0) /*!< CRYPTO_T::AES_IV1: IV Position */ +#define CRYPTO_AES_IV1_IV_Msk (0xfffffffful << CRYPTO_AES_IV1_IV_Pos) /*!< CRYPTO_T::AES_IV1: IV Mask */ + +#define CRYPTO_AES_IV2_IV_Pos (0) /*!< CRYPTO_T::AES_IV2: IV Position */ +#define CRYPTO_AES_IV2_IV_Msk (0xfffffffful << CRYPTO_AES_IV2_IV_Pos) /*!< CRYPTO_T::AES_IV2: IV Mask */ + +#define CRYPTO_AES_IV3_IV_Pos (0) /*!< CRYPTO_T::AES_IV3: IV Position */ +#define CRYPTO_AES_IV3_IV_Msk (0xfffffffful << CRYPTO_AES_IV3_IV_Pos) /*!< CRYPTO_T::AES_IV3: IV Mask */ + +#define CRYPTO_AES_SADDR_SADDR_Pos (0) /*!< CRYPTO_T::AES_SADDR: SADDR Position */ +#define CRYPTO_AES_SADDR_SADDR_Msk (0xfffffffful << CRYPTO_AES_SADDR_SADDR_Pos) /*!< CRYPTO_T::AES_SADDR: SADDR Mask */ + +#define CRYPTO_AES_DADDR_DADDR_Pos (0) /*!< CRYPTO_T::AES_DADDR: DADDR Position */ +#define CRYPTO_AES_DADDR_DADDR_Msk (0xfffffffful << CRYPTO_AES_DADDR_DADDR_Pos) /*!< CRYPTO_T::AES_DADDR: DADDR Mask */ + +#define CRYPTO_AES_CNT_CNT_Pos (0) /*!< CRYPTO_T::AES_CNT: CNT Position */ +#define CRYPTO_AES_CNT_CNT_Msk (0xfffffffful << CRYPTO_AES_CNT_CNT_Pos) /*!< CRYPTO_T::AES_CNT: CNT Mask */ + +#define CRYPTO_HMAC_CTL_START_Pos (0) /*!< CRYPTO_T::HMAC_CTL: START Position */ +#define CRYPTO_HMAC_CTL_START_Msk (0x1ul << CRYPTO_HMAC_CTL_START_Pos) /*!< CRYPTO_T::HMAC_CTL: START Mask */ + +#define CRYPTO_HMAC_CTL_STOP_Pos (1) /*!< CRYPTO_T::HMAC_CTL: STOP Position */ +#define CRYPTO_HMAC_CTL_STOP_Msk (0x1ul << CRYPTO_HMAC_CTL_STOP_Pos) /*!< CRYPTO_T::HMAC_CTL: STOP Mask */ + +#define CRYPTO_HMAC_CTL_DMAFIRST_Pos (4) /*!< CRYPTO_T::HMAC_CTL: DMAFIRST Position */ +#define CRYPTO_HMAC_CTL_DMAFIRST_Msk (0x1ul << CRYPTO_HMAC_CTL_DMAFIRST_Pos) /*!< CRYPTO_T::HMAC_CTL: DMAFIRST Mask */ + +#define CRYPTO_HMAC_CTL_DMALAST_Pos (5) /*!< CRYPTO_T::HMAC_CTL: DMALAST Position */ +#define CRYPTO_HMAC_CTL_DMALAST_Msk (0x1ul << CRYPTO_HMAC_CTL_DMALAST_Pos) /*!< CRYPTO_T::HMAC_CTL: DMALAST Mask */ + +#define CRYPTO_HMAC_CTL_DMACSCAD_Pos (6) /*!< CRYPTO_T::HMAC_CTL: DMACSCAD Position */ +#define CRYPTO_HMAC_CTL_DMACSCAD_Msk (0x1ul << CRYPTO_HMAC_CTL_DMACSCAD_Pos) /*!< CRYPTO_T::HMAC_CTL: DMACSCAD Mask */ + +#define CRYPTO_HMAC_CTL_DMAEN_Pos (7) /*!< CRYPTO_T::HMAC_CTL: DMAEN Position */ +#define CRYPTO_HMAC_CTL_DMAEN_Msk (0x1ul << CRYPTO_HMAC_CTL_DMAEN_Pos) /*!< CRYPTO_T::HMAC_CTL: DMAEN Mask */ + +#define CRYPTO_HMAC_CTL_OPMODE_Pos (8) /*!< CRYPTO_T::HMAC_CTL: OPMODE Position */ +#define CRYPTO_HMAC_CTL_OPMODE_Msk (0x7ul << CRYPTO_HMAC_CTL_OPMODE_Pos) /*!< CRYPTO_T::HMAC_CTL: OPMODE Mask */ + +#define CRYPTO_HMAC_CTL_HMACEN_Pos (11) /*!< CRYPTO_T::HMAC_CTL: HMACEN Position */ +#define CRYPTO_HMAC_CTL_HMACEN_Msk (0x1ul << CRYPTO_HMAC_CTL_HMACEN_Pos) /*!< CRYPTO_T::HMAC_CTL: HMACEN Mask */ + +#define CRYPTO_HMAC_CTL_SHA3EN_Pos (12) /*!< CRYPTO_T::HMAC_CTL: SHA3EN Position */ +#define CRYPTO_HMAC_CTL_SHA3EN_Msk (0x1ul << CRYPTO_HMAC_CTL_SHA3EN_Pos) /*!< CRYPTO_T::HMAC_CTL: SHA3EN Mask */ + +#define CRYPTO_HMAC_CTL_SM3EN_Pos (13) /*!< CRYPTO_T::HMAC_CTL: SM3EN Position */ +#define CRYPTO_HMAC_CTL_SM3EN_Msk (0x1ul << CRYPTO_HMAC_CTL_SM3EN_Pos) /*!< CRYPTO_T::HMAC_CTL: SM3EN Mask */ + +#define CRYPTO_HMAC_CTL_MD5EN_Pos (14) /*!< CRYPTO_T::HMAC_CTL: MD5EN Position */ +#define CRYPTO_HMAC_CTL_MD5EN_Msk (0x1ul << CRYPTO_HMAC_CTL_MD5EN_Pos) /*!< CRYPTO_T::HMAC_CTL: MD5EN Mask */ + +#define CRYPTO_HMAC_CTL_FBIN_Pos (20) /*!< CRYPTO_T::HMAC_CTL: FBIN Position */ +#define CRYPTO_HMAC_CTL_FBIN_Msk (0x1ul << CRYPTO_HMAC_CTL_FBIN_Pos) /*!< CRYPTO_T::HMAC_CTL: FBIN Mask */ + +#define CRYPTO_HMAC_CTL_FBOUT_Pos (21) /*!< CRYPTO_T::HMAC_CTL: FBOUT Position */ +#define CRYPTO_HMAC_CTL_FBOUT_Msk (0x1ul << CRYPTO_HMAC_CTL_FBOUT_Pos) /*!< CRYPTO_T::HMAC_CTL: FBOUT Mask */ + +#define CRYPTO_HMAC_CTL_OUTSWAP_Pos (22) /*!< CRYPTO_T::HMAC_CTL: OUTSWAP Position */ +#define CRYPTO_HMAC_CTL_OUTSWAP_Msk (0x1ul << CRYPTO_HMAC_CTL_OUTSWAP_Pos) /*!< CRYPTO_T::HMAC_CTL: OUTSWAP Mask */ + +#define CRYPTO_HMAC_CTL_INSWAP_Pos (23) /*!< CRYPTO_T::HMAC_CTL: INSWAP Position */ +#define CRYPTO_HMAC_CTL_INSWAP_Msk (0x1ul << CRYPTO_HMAC_CTL_INSWAP_Pos) /*!< CRYPTO_T::HMAC_CTL: INSWAP Mask */ + +#define CRYPTO_HMAC_CTL_NEXTDGST_Pos (24) /*!< CRYPTO_T::HMAC_CTL: NEXTDGST Position */ +#define CRYPTO_HMAC_CTL_NEXTDGST_Msk (0x1ul << CRYPTO_HMAC_CTL_NEXTDGST_Pos) /*!< CRYPTO_T::HMAC_CTL: NEXTDGST Mask */ + +#define CRYPTO_HMAC_CTL_FINISHDGST_Pos (25) /*!< CRYPTO_T::HMAC_CTL: FINISHDGST Position*/ +#define CRYPTO_HMAC_CTL_FINISHDGST_Msk (0x1ul << CRYPTO_HMAC_CTL_FINISHDGST_Pos) /*!< CRYPTO_T::HMAC_CTL: FINISHDGST Mask */ + +#define CRYPTO_HMAC_STS_BUSY_Pos (0) /*!< CRYPTO_T::HMAC_STS: BUSY Position */ +#define CRYPTO_HMAC_STS_BUSY_Msk (0x1ul << CRYPTO_HMAC_STS_BUSY_Pos) /*!< CRYPTO_T::HMAC_STS: BUSY Mask */ + +#define CRYPTO_HMAC_STS_DMABUSY_Pos (1) /*!< CRYPTO_T::HMAC_STS: DMABUSY Position */ +#define CRYPTO_HMAC_STS_DMABUSY_Msk (0x1ul << CRYPTO_HMAC_STS_DMABUSY_Pos) /*!< CRYPTO_T::HMAC_STS: DMABUSY Mask */ + +#define CRYPTO_HMAC_STS_SHAKEBUSY_Pos (2) /*!< CRYPTO_T::HMAC_STS: SHAKEBUSY Position */ +#define CRYPTO_HMAC_STS_SHAKEBUSY_Msk (0x1ul << CRYPTO_HMAC_STS_SHAKEBUSY_Pos) /*!< CRYPTO_T::HMAC_STS: SHAKEBUSY Mask */ + +#define CRYPTO_HMAC_STS_DMAERR_Pos (8) /*!< CRYPTO_T::HMAC_STS: DMAERR Position */ +#define CRYPTO_HMAC_STS_DMAERR_Msk (0x1ul << CRYPTO_HMAC_STS_DMAERR_Pos) /*!< CRYPTO_T::HMAC_STS: DMAERR Mask */ + +#define CRYPTO_HMAC_STS_KSERR_Pos (9) /*!< CRYPTO_T::HMAC_STS: KSERR Position */ +#define CRYPTO_HMAC_STS_KSERR_Msk (0x1ul << CRYPTO_HMAC_STS_KSERR_Pos) /*!< CRYPTO_T::HMAC_STS: KSERR Mask */ + +#define CRYPTO_HMAC_STS_DATINREQ_Pos (16) /*!< CRYPTO_T::HMAC_STS: DATINREQ Position */ +#define CRYPTO_HMAC_STS_DATINREQ_Msk (0x1ul << CRYPTO_HMAC_STS_DATINREQ_Pos) /*!< CRYPTO_T::HMAC_STS: DATINREQ Mask */ + +#define CRYPTO_HMAC_DGST0_DGST_Pos (0) /*!< CRYPTO_T::HMAC_DGST0: DGST Position */ +#define CRYPTO_HMAC_DGST0_DGST_Msk (0xfffffffful << CRYPTO_HMAC_DGST0_DGST_Pos) /*!< CRYPTO_T::HMAC_DGST0: DGST Mask */ + +#define CRYPTO_HMAC_DGST1_DGST_Pos (0) /*!< CRYPTO_T::HMAC_DGST1: DGST Position */ +#define CRYPTO_HMAC_DGST1_DGST_Msk (0xfffffffful << CRYPTO_HMAC_DGST1_DGST_Pos) /*!< CRYPTO_T::HMAC_DGST1: DGST Mask */ + +#define CRYPTO_HMAC_DGST2_DGST_Pos (0) /*!< CRYPTO_T::HMAC_DGST2: DGST Position */ +#define CRYPTO_HMAC_DGST2_DGST_Msk (0xfffffffful << CRYPTO_HMAC_DGST2_DGST_Pos) /*!< CRYPTO_T::HMAC_DGST2: DGST Mask */ + +#define CRYPTO_HMAC_DGST3_DGST_Pos (0) /*!< CRYPTO_T::HMAC_DGST3: DGST Position */ +#define CRYPTO_HMAC_DGST3_DGST_Msk (0xfffffffful << CRYPTO_HMAC_DGST3_DGST_Pos) /*!< CRYPTO_T::HMAC_DGST3: DGST Mask */ + +#define CRYPTO_HMAC_DGST4_DGST_Pos (0) /*!< CRYPTO_T::HMAC_DGST4: DGST Position */ +#define CRYPTO_HMAC_DGST4_DGST_Msk (0xfffffffful << CRYPTO_HMAC_DGST4_DGST_Pos) /*!< CRYPTO_T::HMAC_DGST4: DGST Mask */ + +#define CRYPTO_HMAC_DGST5_DGST_Pos (0) /*!< CRYPTO_T::HMAC_DGST5: DGST Position */ +#define CRYPTO_HMAC_DGST5_DGST_Msk (0xfffffffful << CRYPTO_HMAC_DGST5_DGST_Pos) /*!< CRYPTO_T::HMAC_DGST5: DGST Mask */ + +#define CRYPTO_HMAC_DGST6_DGST_Pos (0) /*!< CRYPTO_T::HMAC_DGST6: DGST Position */ +#define CRYPTO_HMAC_DGST6_DGST_Msk (0xfffffffful << CRYPTO_HMAC_DGST6_DGST_Pos) /*!< CRYPTO_T::HMAC_DGST6: DGST Mask */ + +#define CRYPTO_HMAC_DGST7_DGST_Pos (0) /*!< CRYPTO_T::HMAC_DGST7: DGST Position */ +#define CRYPTO_HMAC_DGST7_DGST_Msk (0xfffffffful << CRYPTO_HMAC_DGST7_DGST_Pos) /*!< CRYPTO_T::HMAC_DGST7: DGST Mask */ + +#define CRYPTO_HMAC_DGST8_DGST_Pos (0) /*!< CRYPTO_T::HMAC_DGST8: DGST Position */ +#define CRYPTO_HMAC_DGST8_DGST_Msk (0xfffffffful << CRYPTO_HMAC_DGST8_DGST_Pos) /*!< CRYPTO_T::HMAC_DGST8: DGST Mask */ + +#define CRYPTO_HMAC_DGST9_DGST_Pos (0) /*!< CRYPTO_T::HMAC_DGST9: DGST Position */ +#define CRYPTO_HMAC_DGST9_DGST_Msk (0xfffffffful << CRYPTO_HMAC_DGST9_DGST_Pos) /*!< CRYPTO_T::HMAC_DGST9: DGST Mask */ + +#define CRYPTO_HMAC_DGST10_DGST_Pos (0) /*!< CRYPTO_T::HMAC_DGST10: DGST Position */ +#define CRYPTO_HMAC_DGST10_DGST_Msk (0xfffffffful << CRYPTO_HMAC_DGST10_DGST_Pos) /*!< CRYPTO_T::HMAC_DGST10: DGST Mask */ + +#define CRYPTO_HMAC_DGST11_DGST_Pos (0) /*!< CRYPTO_T::HMAC_DGST11: DGST Position */ +#define CRYPTO_HMAC_DGST11_DGST_Msk (0xfffffffful << CRYPTO_HMAC_DGST11_DGST_Pos) /*!< CRYPTO_T::HMAC_DGST11: DGST Mask */ + +#define CRYPTO_HMAC_DGST12_DGST_Pos (0) /*!< CRYPTO_T::HMAC_DGST12: DGST Position */ +#define CRYPTO_HMAC_DGST12_DGST_Msk (0xfffffffful << CRYPTO_HMAC_DGST12_DGST_Pos) /*!< CRYPTO_T::HMAC_DGST12: DGST Mask */ + +#define CRYPTO_HMAC_DGST13_DGST_Pos (0) /*!< CRYPTO_T::HMAC_DGST13: DGST Position */ +#define CRYPTO_HMAC_DGST13_DGST_Msk (0xfffffffful << CRYPTO_HMAC_DGST13_DGST_Pos) /*!< CRYPTO_T::HMAC_DGST13: DGST Mask */ + +#define CRYPTO_HMAC_DGST14_DGST_Pos (0) /*!< CRYPTO_T::HMAC_DGST14: DGST Position */ +#define CRYPTO_HMAC_DGST14_DGST_Msk (0xfffffffful << CRYPTO_HMAC_DGST14_DGST_Pos) /*!< CRYPTO_T::HMAC_DGST14: DGST Mask */ + +#define CRYPTO_HMAC_DGST15_DGST_Pos (0) /*!< CRYPTO_T::HMAC_DGST15: DGST Position */ +#define CRYPTO_HMAC_DGST15_DGST_Msk (0xfffffffful << CRYPTO_HMAC_DGST15_DGST_Pos) /*!< CRYPTO_T::HMAC_DGST15: DGST Mask */ + +#define CRYPTO_HMAC_KEYCNT_KEYCNT_Pos (0) /*!< CRYPTO_T::HMAC_KEYCNT: KEYCNT Position */ +#define CRYPTO_HMAC_KEYCNT_KEYCNT_Msk (0xfffffffful << CRYPTO_HMAC_KEYCNT_KEYCNT_Pos) /*!< CRYPTO_T::HMAC_KEYCNT: KEYCNT Mask */ + +#define CRYPTO_HMAC_SADDR_SADDR_Pos (0) /*!< CRYPTO_T::HMAC_SADDR: SADDR Position */ +#define CRYPTO_HMAC_SADDR_SADDR_Msk (0xfffffffful << CRYPTO_HMAC_SADDR_SADDR_Pos) /*!< CRYPTO_T::HMAC_SADDR: SADDR Mask */ + +#define CRYPTO_HMAC_DMACNT_DMACNT_Pos (0) /*!< CRYPTO_T::HMAC_DMACNT: DMACNT Position */ +#define CRYPTO_HMAC_DMACNT_DMACNT_Msk (0xfffffffful << CRYPTO_HMAC_DMACNT_DMACNT_Pos) /*!< CRYPTO_T::HMAC_DMACNT: DMACNT Mask */ + +#define CRYPTO_HMAC_DATIN_DATIN_Pos (0) /*!< CRYPTO_T::HMAC_DATIN: DATIN Position */ +#define CRYPTO_HMAC_DATIN_DATIN_Msk (0xfffffffful << CRYPTO_HMAC_DATIN_DATIN_Pos) /*!< CRYPTO_T::HMAC_DATIN: DATIN Mask */ + +#define CRYPTO_HMAC_FDBCK0_FDBCK_Pos (0) /*!< CRYPTO_T::HMAC_FDBCK0: FDBCK Position */ +#define CRYPTO_HMAC_FDBCK0_FDBCK_Msk (0xfffffffful << CRYPTO_HMAC_FDBCK0_FDBCK_Pos) /*!< CRYPTO_T::HMAC_FDBCK0: FDBCK Mask */ + +#define CRYPTO_HMAC_FDBCK1_FDBCK_Pos (0) /*!< CRYPTO_T::HMAC_FDBCK1: FDBCK Position */ +#define CRYPTO_HMAC_FDBCK1_FDBCK_Msk (0xfffffffful << CRYPTO_HMAC_FDBCK1_FDBCK_Pos) /*!< CRYPTO_T::HMAC_FDBCK1: FDBCK Mask */ + +#define CRYPTO_HMAC_FDBCK2_FDBCK_Pos (0) /*!< CRYPTO_T::HMAC_FDBCK2: FDBCK Position */ +#define CRYPTO_HMAC_FDBCK2_FDBCK_Msk (0xfffffffful << CRYPTO_HMAC_FDBCK2_FDBCK_Pos) /*!< CRYPTO_T::HMAC_FDBCK2: FDBCK Mask */ + +#define CRYPTO_HMAC_FDBCK3_FDBCK_Pos (0) /*!< CRYPTO_T::HMAC_FDBCK3: FDBCK Position */ +#define CRYPTO_HMAC_FDBCK3_FDBCK_Msk (0xfffffffful << CRYPTO_HMAC_FDBCK3_FDBCK_Pos) /*!< CRYPTO_T::HMAC_FDBCK3: FDBCK Mask */ + +#define CRYPTO_HMAC_FDBCK4_FDBCK_Pos (0) /*!< CRYPTO_T::HMAC_FDBCK4: FDBCK Position */ +#define CRYPTO_HMAC_FDBCK4_FDBCK_Msk (0xfffffffful << CRYPTO_HMAC_FDBCK4_FDBCK_Pos) /*!< CRYPTO_T::HMAC_FDBCK4: FDBCK Mask */ + +#define CRYPTO_HMAC_FDBCK5_FDBCK_Pos (0) /*!< CRYPTO_T::HMAC_FDBCK5: FDBCK Position */ +#define CRYPTO_HMAC_FDBCK5_FDBCK_Msk (0xfffffffful << CRYPTO_HMAC_FDBCK5_FDBCK_Pos) /*!< CRYPTO_T::HMAC_FDBCK5: FDBCK Mask */ + +#define CRYPTO_HMAC_FDBCK6_FDBCK_Pos (0) /*!< CRYPTO_T::HMAC_FDBCK6: FDBCK Position */ +#define CRYPTO_HMAC_FDBCK6_FDBCK_Msk (0xfffffffful << CRYPTO_HMAC_FDBCK6_FDBCK_Pos) /*!< CRYPTO_T::HMAC_FDBCK6: FDBCK Mask */ + +#define CRYPTO_HMAC_FDBCK7_FDBCK_Pos (0) /*!< CRYPTO_T::HMAC_FDBCK7: FDBCK Position */ +#define CRYPTO_HMAC_FDBCK7_FDBCK_Msk (0xfffffffful << CRYPTO_HMAC_FDBCK7_FDBCK_Pos) /*!< CRYPTO_T::HMAC_FDBCK7: FDBCK Mask */ + +#define CRYPTO_HMAC_FDBCK8_FDBCK_Pos (0) /*!< CRYPTO_T::HMAC_FDBCK8: FDBCK Position */ +#define CRYPTO_HMAC_FDBCK8_FDBCK_Msk (0xfffffffful << CRYPTO_HMAC_FDBCK8_FDBCK_Pos) /*!< CRYPTO_T::HMAC_FDBCK8: FDBCK Mask */ + +#define CRYPTO_HMAC_FDBCK9_FDBCK_Pos (0) /*!< CRYPTO_T::HMAC_FDBCK9: FDBCK Position */ +#define CRYPTO_HMAC_FDBCK9_FDBCK_Msk (0xfffffffful << CRYPTO_HMAC_FDBCK9_FDBCK_Pos) /*!< CRYPTO_T::HMAC_FDBCK9: FDBCK Mask */ + +#define CRYPTO_HMAC_FDBCK10_FDBCK_Pos (0) /*!< CRYPTO_T::HMAC_FDBCK10: FDBCK Position */ +#define CRYPTO_HMAC_FDBCK10_FDBCK_Msk (0xfffffffful << CRYPTO_HMAC_FDBCK10_FDBCK_Pos) /*!< CRYPTO_T::HMAC_FDBCK10: FDBCK Mask */ + +#define CRYPTO_HMAC_FDBCK11_FDBCK_Pos (0) /*!< CRYPTO_T::HMAC_FDBCK11: FDBCK Position */ +#define CRYPTO_HMAC_FDBCK11_FDBCK_Msk (0xfffffffful << CRYPTO_HMAC_FDBCK11_FDBCK_Pos) /*!< CRYPTO_T::HMAC_FDBCK11: FDBCK Mask */ + +#define CRYPTO_HMAC_FDBCK12_FDBCK_Pos (0) /*!< CRYPTO_T::HMAC_FDBCK12: FDBCK Position */ +#define CRYPTO_HMAC_FDBCK12_FDBCK_Msk (0xfffffffful << CRYPTO_HMAC_FDBCK12_FDBCK_Pos) /*!< CRYPTO_T::HMAC_FDBCK12: FDBCK Mask */ + +#define CRYPTO_HMAC_FDBCK13_FDBCK_Pos (0) /*!< CRYPTO_T::HMAC_FDBCK13: FDBCK Position */ +#define CRYPTO_HMAC_FDBCK13_FDBCK_Msk (0xfffffffful << CRYPTO_HMAC_FDBCK13_FDBCK_Pos) /*!< CRYPTO_T::HMAC_FDBCK13: FDBCK Mask */ + +#define CRYPTO_HMAC_FDBCK14_FDBCK_Pos (0) /*!< CRYPTO_T::HMAC_FDBCK14: FDBCK Position */ +#define CRYPTO_HMAC_FDBCK14_FDBCK_Msk (0xfffffffful << CRYPTO_HMAC_FDBCK14_FDBCK_Pos) /*!< CRYPTO_T::HMAC_FDBCK14: FDBCK Mask */ + +#define CRYPTO_HMAC_FDBCK15_FDBCK_Pos (0) /*!< CRYPTO_T::HMAC_FDBCK15: FDBCK Position */ +#define CRYPTO_HMAC_FDBCK15_FDBCK_Msk (0xfffffffful << CRYPTO_HMAC_FDBCK15_FDBCK_Pos) /*!< CRYPTO_T::HMAC_FDBCK15: FDBCK Mask */ + +#define CRYPTO_HMAC_FDBCK16_FDBCK_Pos (0) /*!< CRYPTO_T::HMAC_FDBCK16: FDBCK Position */ +#define CRYPTO_HMAC_FDBCK16_FDBCK_Msk (0xfffffffful << CRYPTO_HMAC_FDBCK16_FDBCK_Pos) /*!< CRYPTO_T::HMAC_FDBCK16: FDBCK Mask */ + +#define CRYPTO_HMAC_FDBCK17_FDBCK_Pos (0) /*!< CRYPTO_T::HMAC_FDBCK17: FDBCK Position */ +#define CRYPTO_HMAC_FDBCK17_FDBCK_Msk (0xfffffffful << CRYPTO_HMAC_FDBCK17_FDBCK_Pos) /*!< CRYPTO_T::HMAC_FDBCK17: FDBCK Mask */ + +#define CRYPTO_HMAC_FDBCK18_FDBCK_Pos (0) /*!< CRYPTO_T::HMAC_FDBCK18: FDBCK Position */ +#define CRYPTO_HMAC_FDBCK18_FDBCK_Msk (0xfffffffful << CRYPTO_HMAC_FDBCK18_FDBCK_Pos) /*!< CRYPTO_T::HMAC_FDBCK18: FDBCK Mask */ + +#define CRYPTO_HMAC_FDBCK19_FDBCK_Pos (0) /*!< CRYPTO_T::HMAC_FDBCK19: FDBCK Position */ +#define CRYPTO_HMAC_FDBCK19_FDBCK_Msk (0xfffffffful << CRYPTO_HMAC_FDBCK19_FDBCK_Pos) /*!< CRYPTO_T::HMAC_FDBCK19: FDBCK Mask */ + +#define CRYPTO_HMAC_FDBCK20_FDBCK_Pos (0) /*!< CRYPTO_T::HMAC_FDBCK20: FDBCK Position */ +#define CRYPTO_HMAC_FDBCK20_FDBCK_Msk (0xfffffffful << CRYPTO_HMAC_FDBCK20_FDBCK_Pos) /*!< CRYPTO_T::HMAC_FDBCK20: FDBCK Mask */ + +#define CRYPTO_HMAC_FDBCK21_FDBCK_Pos (0) /*!< CRYPTO_T::HMAC_FDBCK21: FDBCK Position */ +#define CRYPTO_HMAC_FDBCK21_FDBCK_Msk (0xfffffffful << CRYPTO_HMAC_FDBCK21_FDBCK_Pos) /*!< CRYPTO_T::HMAC_FDBCK21: FDBCK Mask */ + +#define CRYPTO_HMAC_FDBCK22_FDBCK_Pos (0) /*!< CRYPTO_T::HMAC_FDBCK22: FDBCK Position */ +#define CRYPTO_HMAC_FDBCK22_FDBCK_Msk (0xfffffffful << CRYPTO_HMAC_FDBCK22_FDBCK_Pos) /*!< CRYPTO_T::HMAC_FDBCK22: FDBCK Mask */ + +#define CRYPTO_HMAC_FDBCK23_FDBCK_Pos (0) /*!< CRYPTO_T::HMAC_FDBCK23: FDBCK Position */ +#define CRYPTO_HMAC_FDBCK23_FDBCK_Msk (0xfffffffful << CRYPTO_HMAC_FDBCK23_FDBCK_Pos) /*!< CRYPTO_T::HMAC_FDBCK23: FDBCK Mask */ + +#define CRYPTO_HMAC_FDBCK24_FDBCK_Pos (0) /*!< CRYPTO_T::HMAC_FDBCK24: FDBCK Position */ +#define CRYPTO_HMAC_FDBCK24_FDBCK_Msk (0xfffffffful << CRYPTO_HMAC_FDBCK24_FDBCK_Pos) /*!< CRYPTO_T::HMAC_FDBCK24: FDBCK Mask */ + +#define CRYPTO_HMAC_FDBCK25_FDBCK_Pos (0) /*!< CRYPTO_T::HMAC_FDBCK25: FDBCK Position */ +#define CRYPTO_HMAC_FDBCK25_FDBCK_Msk (0xfffffffful << CRYPTO_HMAC_FDBCK25_FDBCK_Pos) /*!< CRYPTO_T::HMAC_FDBCK25: FDBCK Mask */ + +#define CRYPTO_HMAC_FDBCK26_FDBCK_Pos (0) /*!< CRYPTO_T::HMAC_FDBCK26: FDBCK Position */ +#define CRYPTO_HMAC_FDBCK26_FDBCK_Msk (0xfffffffful << CRYPTO_HMAC_FDBCK26_FDBCK_Pos) /*!< CRYPTO_T::HMAC_FDBCK26: FDBCK Mask */ + +#define CRYPTO_HMAC_FDBCK27_FDBCK_Pos (0) /*!< CRYPTO_T::HMAC_FDBCK27: FDBCK Position */ +#define CRYPTO_HMAC_FDBCK27_FDBCK_Msk (0xfffffffful << CRYPTO_HMAC_FDBCK27_FDBCK_Pos) /*!< CRYPTO_T::HMAC_FDBCK27: FDBCK Mask */ + +#define CRYPTO_HMAC_FDBCK28_FDBCK_Pos (0) /*!< CRYPTO_T::HMAC_FDBCK28: FDBCK Position */ +#define CRYPTO_HMAC_FDBCK28_FDBCK_Msk (0xfffffffful << CRYPTO_HMAC_FDBCK28_FDBCK_Pos) /*!< CRYPTO_T::HMAC_FDBCK28: FDBCK Mask */ + +#define CRYPTO_HMAC_FDBCK29_FDBCK_Pos (0) /*!< CRYPTO_T::HMAC_FDBCK29: FDBCK Position */ +#define CRYPTO_HMAC_FDBCK29_FDBCK_Msk (0xfffffffful << CRYPTO_HMAC_FDBCK29_FDBCK_Pos) /*!< CRYPTO_T::HMAC_FDBCK29: FDBCK Mask */ + +#define CRYPTO_HMAC_FDBCK30_FDBCK_Pos (0) /*!< CRYPTO_T::HMAC_FDBCK30: FDBCK Position */ +#define CRYPTO_HMAC_FDBCK30_FDBCK_Msk (0xfffffffful << CRYPTO_HMAC_FDBCK30_FDBCK_Pos) /*!< CRYPTO_T::HMAC_FDBCK30: FDBCK Mask */ + +#define CRYPTO_HMAC_FDBCK31_FDBCK_Pos (0) /*!< CRYPTO_T::HMAC_FDBCK31: FDBCK Position */ +#define CRYPTO_HMAC_FDBCK31_FDBCK_Msk (0xfffffffful << CRYPTO_HMAC_FDBCK31_FDBCK_Pos) /*!< CRYPTO_T::HMAC_FDBCK31: FDBCK Mask */ + +#define CRYPTO_HMAC_FDBCK32_FDBCK_Pos (0) /*!< CRYPTO_T::HMAC_FDBCK32: FDBCK Position */ +#define CRYPTO_HMAC_FDBCK32_FDBCK_Msk (0xfffffffful << CRYPTO_HMAC_FDBCK32_FDBCK_Pos) /*!< CRYPTO_T::HMAC_FDBCK32: FDBCK Mask */ + +#define CRYPTO_HMAC_FDBCK33_FDBCK_Pos (0) /*!< CRYPTO_T::HMAC_FDBCK33: FDBCK Position */ +#define CRYPTO_HMAC_FDBCK33_FDBCK_Msk (0xfffffffful << CRYPTO_HMAC_FDBCK33_FDBCK_Pos) /*!< CRYPTO_T::HMAC_FDBCK33: FDBCK Mask */ + +#define CRYPTO_HMAC_FDBCK34_FDBCK_Pos (0) /*!< CRYPTO_T::HMAC_FDBCK34: FDBCK Position */ +#define CRYPTO_HMAC_FDBCK34_FDBCK_Msk (0xfffffffful << CRYPTO_HMAC_FDBCK34_FDBCK_Pos) /*!< CRYPTO_T::HMAC_FDBCK34: FDBCK Mask */ + +#define CRYPTO_HMAC_FDBCK35_FDBCK_Pos (0) /*!< CRYPTO_T::HMAC_FDBCK35: FDBCK Position */ +#define CRYPTO_HMAC_FDBCK35_FDBCK_Msk (0xfffffffful << CRYPTO_HMAC_FDBCK35_FDBCK_Pos) /*!< CRYPTO_T::HMAC_FDBCK35: FDBCK Mask */ + +#define CRYPTO_HMAC_FDBCK36_FDBCK_Pos (0) /*!< CRYPTO_T::HMAC_FDBCK36: FDBCK Position */ +#define CRYPTO_HMAC_FDBCK36_FDBCK_Msk (0xfffffffful << CRYPTO_HMAC_FDBCK36_FDBCK_Pos) /*!< CRYPTO_T::HMAC_FDBCK36: FDBCK Mask */ + +#define CRYPTO_HMAC_FDBCK37_FDBCK_Pos (0) /*!< CRYPTO_T::HMAC_FDBCK37: FDBCK Position */ +#define CRYPTO_HMAC_FDBCK37_FDBCK_Msk (0xfffffffful << CRYPTO_HMAC_FDBCK37_FDBCK_Pos) /*!< CRYPTO_T::HMAC_FDBCK37: FDBCK Mask */ + +#define CRYPTO_HMAC_FDBCK38_FDBCK_Pos (0) /*!< CRYPTO_T::HMAC_FDBCK38: FDBCK Position */ +#define CRYPTO_HMAC_FDBCK38_FDBCK_Msk (0xfffffffful << CRYPTO_HMAC_FDBCK38_FDBCK_Pos) /*!< CRYPTO_T::HMAC_FDBCK38: FDBCK Mask */ + +#define CRYPTO_HMAC_FDBCK39_FDBCK_Pos (0) /*!< CRYPTO_T::HMAC_FDBCK39: FDBCK Position */ +#define CRYPTO_HMAC_FDBCK39_FDBCK_Msk (0xfffffffful << CRYPTO_HMAC_FDBCK39_FDBCK_Pos) /*!< CRYPTO_T::HMAC_FDBCK39: FDBCK Mask */ + +#define CRYPTO_HMAC_FDBCK40_FDBCK_Pos (0) /*!< CRYPTO_T::HMAC_FDBCK40: FDBCK Position */ +#define CRYPTO_HMAC_FDBCK40_FDBCK_Msk (0xfffffffful << CRYPTO_HMAC_FDBCK40_FDBCK_Pos) /*!< CRYPTO_T::HMAC_FDBCK40: FDBCK Mask */ + +#define CRYPTO_HMAC_FDBCK41_FDBCK_Pos (0) /*!< CRYPTO_T::HMAC_FDBCK41: FDBCK Position */ +#define CRYPTO_HMAC_FDBCK41_FDBCK_Msk (0xfffffffful << CRYPTO_HMAC_FDBCK41_FDBCK_Pos) /*!< CRYPTO_T::HMAC_FDBCK41: FDBCK Mask */ + +#define CRYPTO_HMAC_FDBCK42_FDBCK_Pos (0) /*!< CRYPTO_T::HMAC_FDBCK42: FDBCK Position */ +#define CRYPTO_HMAC_FDBCK42_FDBCK_Msk (0xfffffffful << CRYPTO_HMAC_FDBCK42_FDBCK_Pos) /*!< CRYPTO_T::HMAC_FDBCK42: FDBCK Mask */ + +#define CRYPTO_HMAC_FDBCK43_FDBCK_Pos (0) /*!< CRYPTO_T::HMAC_FDBCK43: FDBCK Position */ +#define CRYPTO_HMAC_FDBCK43_FDBCK_Msk (0xfffffffful << CRYPTO_HMAC_FDBCK43_FDBCK_Pos) /*!< CRYPTO_T::HMAC_FDBCK43: FDBCK Mask */ + +#define CRYPTO_HMAC_FDBCK44_FDBCK_Pos (0) /*!< CRYPTO_T::HMAC_FDBCK44: FDBCK Position */ +#define CRYPTO_HMAC_FDBCK44_FDBCK_Msk (0xfffffffful << CRYPTO_HMAC_FDBCK44_FDBCK_Pos) /*!< CRYPTO_T::HMAC_FDBCK44: FDBCK Mask */ + +#define CRYPTO_HMAC_FDBCK45_FDBCK_Pos (0) /*!< CRYPTO_T::HMAC_FDBCK45: FDBCK Position */ +#define CRYPTO_HMAC_FDBCK45_FDBCK_Msk (0xfffffffful << CRYPTO_HMAC_FDBCK45_FDBCK_Pos) /*!< CRYPTO_T::HMAC_FDBCK45: FDBCK Mask */ + +#define CRYPTO_HMAC_FDBCK46_FDBCK_Pos (0) /*!< CRYPTO_T::HMAC_FDBCK46: FDBCK Position */ +#define CRYPTO_HMAC_FDBCK46_FDBCK_Msk (0xfffffffful << CRYPTO_HMAC_FDBCK46_FDBCK_Pos) /*!< CRYPTO_T::HMAC_FDBCK46: FDBCK Mask */ + +#define CRYPTO_HMAC_FDBCK47_FDBCK_Pos (0) /*!< CRYPTO_T::HMAC_FDBCK47: FDBCK Position */ +#define CRYPTO_HMAC_FDBCK47_FDBCK_Msk (0xfffffffful << CRYPTO_HMAC_FDBCK47_FDBCK_Pos) /*!< CRYPTO_T::HMAC_FDBCK47: FDBCK Mask */ + +#define CRYPTO_HMAC_FDBCK48_FDBCK_Pos (0) /*!< CRYPTO_T::HMAC_FDBCK48: FDBCK Position */ +#define CRYPTO_HMAC_FDBCK48_FDBCK_Msk (0xfffffffful << CRYPTO_HMAC_FDBCK48_FDBCK_Pos) /*!< CRYPTO_T::HMAC_FDBCK48: FDBCK Mask */ + +#define CRYPTO_HMAC_FDBCK49_FDBCK_Pos (0) /*!< CRYPTO_T::HMAC_FDBCK49: FDBCK Position */ +#define CRYPTO_HMAC_FDBCK49_FDBCK_Msk (0xfffffffful << CRYPTO_HMAC_FDBCK49_FDBCK_Pos) /*!< CRYPTO_T::HMAC_FDBCK49: FDBCK Mask */ + +#define CRYPTO_HMAC_FDBCK50_FDBCK_Pos (0) /*!< CRYPTO_T::HMAC_FDBCK50: FDBCK Position */ +#define CRYPTO_HMAC_FDBCK50_FDBCK_Msk (0xfffffffful << CRYPTO_HMAC_FDBCK50_FDBCK_Pos) /*!< CRYPTO_T::HMAC_FDBCK50: FDBCK Mask */ + +#define CRYPTO_HMAC_FDBCK51_FDBCK_Pos (0) /*!< CRYPTO_T::HMAC_FDBCK51: FDBCK Position */ +#define CRYPTO_HMAC_FDBCK51_FDBCK_Msk (0xfffffffful << CRYPTO_HMAC_FDBCK51_FDBCK_Pos) /*!< CRYPTO_T::HMAC_FDBCK51: FDBCK Mask */ + +#define CRYPTO_HMAC_FDBCK52_FDBCK_Pos (0) /*!< CRYPTO_T::HMAC_FDBCK52: FDBCK Position */ +#define CRYPTO_HMAC_FDBCK52_FDBCK_Msk (0xfffffffful << CRYPTO_HMAC_FDBCK52_FDBCK_Pos) /*!< CRYPTO_T::HMAC_FDBCK52: FDBCK Mask */ + +#define CRYPTO_HMAC_FDBCK53_FDBCK_Pos (0) /*!< CRYPTO_T::HMAC_FDBCK53: FDBCK Position */ +#define CRYPTO_HMAC_FDBCK53_FDBCK_Msk (0xfffffffful << CRYPTO_HMAC_FDBCK53_FDBCK_Pos) /*!< CRYPTO_T::HMAC_FDBCK53: FDBCK Mask */ + +#define CRYPTO_HMAC_FDBCK54_FDBCK_Pos (0) /*!< CRYPTO_T::HMAC_FDBCK54: FDBCK Position */ +#define CRYPTO_HMAC_FDBCK54_FDBCK_Msk (0xfffffffful << CRYPTO_HMAC_FDBCK54_FDBCK_Pos) /*!< CRYPTO_T::HMAC_FDBCK54: FDBCK Mask */ + +#define CRYPTO_HMAC_FDBCK55_FDBCK_Pos (0) /*!< CRYPTO_T::HMAC_FDBCK55: FDBCK Position */ +#define CRYPTO_HMAC_FDBCK55_FDBCK_Msk (0xfffffffful << CRYPTO_HMAC_FDBCK55_FDBCK_Pos) /*!< CRYPTO_T::HMAC_FDBCK55: FDBCK Mask */ + +#define CRYPTO_HMAC_FDBCK56_FDBCK_Pos (0) /*!< CRYPTO_T::HMAC_FDBCK56: FDBCK Position */ +#define CRYPTO_HMAC_FDBCK56_FDBCK_Msk (0xfffffffful << CRYPTO_HMAC_FDBCK56_FDBCK_Pos) /*!< CRYPTO_T::HMAC_FDBCK56: FDBCK Mask */ + +#define CRYPTO_HMAC_FDBCK57_FDBCK_Pos (0) /*!< CRYPTO_T::HMAC_FDBCK57: FDBCK Position */ +#define CRYPTO_HMAC_FDBCK57_FDBCK_Msk (0xfffffffful << CRYPTO_HMAC_FDBCK57_FDBCK_Pos) /*!< CRYPTO_T::HMAC_FDBCK57: FDBCK Mask */ + +#define CRYPTO_HMAC_FDBCK58_FDBCK_Pos (0) /*!< CRYPTO_T::HMAC_FDBCK58: FDBCK Position */ +#define CRYPTO_HMAC_FDBCK58_FDBCK_Msk (0xfffffffful << CRYPTO_HMAC_FDBCK58_FDBCK_Pos) /*!< CRYPTO_T::HMAC_FDBCK58: FDBCK Mask */ + +#define CRYPTO_HMAC_FDBCK59_FDBCK_Pos (0) /*!< CRYPTO_T::HMAC_FDBCK59: FDBCK Position */ +#define CRYPTO_HMAC_FDBCK59_FDBCK_Msk (0xfffffffful << CRYPTO_HMAC_FDBCK59_FDBCK_Pos) /*!< CRYPTO_T::HMAC_FDBCK59: FDBCK Mask */ + +#define CRYPTO_HMAC_FDBCK60_FDBCK_Pos (0) /*!< CRYPTO_T::HMAC_FDBCK60: FDBCK Position */ +#define CRYPTO_HMAC_FDBCK60_FDBCK_Msk (0xfffffffful << CRYPTO_HMAC_FDBCK60_FDBCK_Pos) /*!< CRYPTO_T::HMAC_FDBCK60: FDBCK Mask */ + +#define CRYPTO_HMAC_FDBCK61_FDBCK_Pos (0) /*!< CRYPTO_T::HMAC_FDBCK61: FDBCK Position */ +#define CRYPTO_HMAC_FDBCK61_FDBCK_Msk (0xfffffffful << CRYPTO_HMAC_FDBCK61_FDBCK_Pos) /*!< CRYPTO_T::HMAC_FDBCK61: FDBCK Mask */ + +#define CRYPTO_HMAC_FDBCK62_FDBCK_Pos (0) /*!< CRYPTO_T::HMAC_FDBCK62: FDBCK Position */ +#define CRYPTO_HMAC_FDBCK62_FDBCK_Msk (0xfffffffful << CRYPTO_HMAC_FDBCK62_FDBCK_Pos) /*!< CRYPTO_T::HMAC_FDBCK62: FDBCK Mask */ + +#define CRYPTO_HMAC_FDBCK63_FDBCK_Pos (0) /*!< CRYPTO_T::HMAC_FDBCK63: FDBCK Position */ +#define CRYPTO_HMAC_FDBCK63_FDBCK_Msk (0xfffffffful << CRYPTO_HMAC_FDBCK63_FDBCK_Pos) /*!< CRYPTO_T::HMAC_FDBCK63: FDBCK Mask */ + +#define CRYPTO_HMAC_FDBCK64_FDBCK_Pos (0) /*!< CRYPTO_T::HMAC_FDBCK64: FDBCK Position */ +#define CRYPTO_HMAC_FDBCK64_FDBCK_Msk (0xfffffffful << CRYPTO_HMAC_FDBCK64_FDBCK_Pos) /*!< CRYPTO_T::HMAC_FDBCK64: FDBCK Mask */ + +#define CRYPTO_HMAC_FDBCK65_FDBCK_Pos (0) /*!< CRYPTO_T::HMAC_FDBCK65: FDBCK Position */ +#define CRYPTO_HMAC_FDBCK65_FDBCK_Msk (0xfffffffful << CRYPTO_HMAC_FDBCK65_FDBCK_Pos) /*!< CRYPTO_T::HMAC_FDBCK65: FDBCK Mask */ + +#define CRYPTO_HMAC_FDBCK66_FDBCK_Pos (0) /*!< CRYPTO_T::HMAC_FDBCK66: FDBCK Position */ +#define CRYPTO_HMAC_FDBCK66_FDBCK_Msk (0xfffffffful << CRYPTO_HMAC_FDBCK66_FDBCK_Pos) /*!< CRYPTO_T::HMAC_FDBCK66: FDBCK Mask */ + +#define CRYPTO_HMAC_FDBCK67_FDBCK_Pos (0) /*!< CRYPTO_T::HMAC_FDBCK67: FDBCK Position */ +#define CRYPTO_HMAC_FDBCK67_FDBCK_Msk (0xfffffffful << CRYPTO_HMAC_FDBCK67_FDBCK_Pos) /*!< CRYPTO_T::HMAC_FDBCK67: FDBCK Mask */ + +#define CRYPTO_HMAC_FDBCK68_FDBCK_Pos (0) /*!< CRYPTO_T::HMAC_FDBCK68: FDBCK Position */ +#define CRYPTO_HMAC_FDBCK68_FDBCK_Msk (0xfffffffful << CRYPTO_HMAC_FDBCK68_FDBCK_Pos) /*!< CRYPTO_T::HMAC_FDBCK68: FDBCK Mask */ + +#define CRYPTO_HMAC_FDBCK69_FDBCK_Pos (0) /*!< CRYPTO_T::HMAC_FDBCK69: FDBCK Position */ +#define CRYPTO_HMAC_FDBCK69_FDBCK_Msk (0xfffffffful << CRYPTO_HMAC_FDBCK69_FDBCK_Pos) /*!< CRYPTO_T::HMAC_FDBCK69: FDBCK Mask */ + +#define CRYPTO_HMAC_FDBCK70_FDBCK_Pos (0) /*!< CRYPTO_T::HMAC_FDBCK70: FDBCK Position */ +#define CRYPTO_HMAC_FDBCK70_FDBCK_Msk (0xfffffffful << CRYPTO_HMAC_FDBCK70_FDBCK_Pos) /*!< CRYPTO_T::HMAC_FDBCK70: FDBCK Mask */ + +#define CRYPTO_HMAC_FDBCK71_FDBCK_Pos (0) /*!< CRYPTO_T::HMAC_FDBCK71: FDBCK Position */ +#define CRYPTO_HMAC_FDBCK71_FDBCK_Msk (0xfffffffful << CRYPTO_HMAC_FDBCK71_FDBCK_Pos) /*!< CRYPTO_T::HMAC_FDBCK71: FDBCK Mask */ + +#define CRYPTO_HMAC_FDBCK72_FDBCK_Pos (0) /*!< CRYPTO_T::HMAC_FDBCK72: FDBCK Position */ +#define CRYPTO_HMAC_FDBCK72_FDBCK_Msk (0xfffffffful << CRYPTO_HMAC_FDBCK72_FDBCK_Pos) /*!< CRYPTO_T::HMAC_FDBCK72: FDBCK Mask */ + +#define CRYPTO_HMAC_FDBCK73_FDBCK_Pos (0) /*!< CRYPTO_T::HMAC_FDBCK73: FDBCK Position */ +#define CRYPTO_HMAC_FDBCK73_FDBCK_Msk (0xfffffffful << CRYPTO_HMAC_FDBCK73_FDBCK_Pos) /*!< CRYPTO_T::HMAC_FDBCK73: FDBCK Mask */ + +#define CRYPTO_HMAC_FDBCK74_FDBCK_Pos (0) /*!< CRYPTO_T::HMAC_FDBCK74: FDBCK Position */ +#define CRYPTO_HMAC_FDBCK74_FDBCK_Msk (0xfffffffful << CRYPTO_HMAC_FDBCK74_FDBCK_Pos) /*!< CRYPTO_T::HMAC_FDBCK74: FDBCK Mask */ + +#define CRYPTO_HMAC_FDBCK75_FDBCK_Pos (0) /*!< CRYPTO_T::HMAC_FDBCK75: FDBCK Position */ +#define CRYPTO_HMAC_FDBCK75_FDBCK_Msk (0xfffffffful << CRYPTO_HMAC_FDBCK75_FDBCK_Pos) /*!< CRYPTO_T::HMAC_FDBCK75: FDBCK Mask */ + +#define CRYPTO_HMAC_FDBCK76_FDBCK_Pos (0) /*!< CRYPTO_T::HMAC_FDBCK76: FDBCK Position */ +#define CRYPTO_HMAC_FDBCK76_FDBCK_Msk (0xfffffffful << CRYPTO_HMAC_FDBCK76_FDBCK_Pos) /*!< CRYPTO_T::HMAC_FDBCK76: FDBCK Mask */ + +#define CRYPTO_HMAC_FDBCK77_FDBCK_Pos (0) /*!< CRYPTO_T::HMAC_FDBCK77: FDBCK Position */ +#define CRYPTO_HMAC_FDBCK77_FDBCK_Msk (0xfffffffful << CRYPTO_HMAC_FDBCK77_FDBCK_Pos) /*!< CRYPTO_T::HMAC_FDBCK77: FDBCK Mask */ + +#define CRYPTO_HMAC_FDBCK78_FDBCK_Pos (0) /*!< CRYPTO_T::HMAC_FDBCK78: FDBCK Position */ +#define CRYPTO_HMAC_FDBCK78_FDBCK_Msk (0xfffffffful << CRYPTO_HMAC_FDBCK78_FDBCK_Pos) /*!< CRYPTO_T::HMAC_FDBCK78: FDBCK Mask */ + +#define CRYPTO_HMAC_FDBCK79_FDBCK_Pos (0) /*!< CRYPTO_T::HMAC_FDBCK79: FDBCK Position */ +#define CRYPTO_HMAC_FDBCK79_FDBCK_Msk (0xfffffffful << CRYPTO_HMAC_FDBCK79_FDBCK_Pos) /*!< CRYPTO_T::HMAC_FDBCK79: FDBCK Mask */ + +#define CRYPTO_HMAC_FDBCK80_FDBCK_Pos (0) /*!< CRYPTO_T::HMAC_FDBCK80: FDBCK Position */ +#define CRYPTO_HMAC_FDBCK80_FDBCK_Msk (0xfffffffful << CRYPTO_HMAC_FDBCK80_FDBCK_Pos) /*!< CRYPTO_T::HMAC_FDBCK80: FDBCK Mask */ + +#define CRYPTO_HMAC_FDBCK81_FDBCK_Pos (0) /*!< CRYPTO_T::HMAC_FDBCK81: FDBCK Position */ +#define CRYPTO_HMAC_FDBCK81_FDBCK_Msk (0xfffffffful << CRYPTO_HMAC_FDBCK81_FDBCK_Pos) /*!< CRYPTO_T::HMAC_FDBCK81: FDBCK Mask */ + +#define CRYPTO_HMAC_FDBCK82_FDBCK_Pos (0) /*!< CRYPTO_T::HMAC_FDBCK82: FDBCK Position */ +#define CRYPTO_HMAC_FDBCK82_FDBCK_Msk (0xfffffffful << CRYPTO_HMAC_FDBCK82_FDBCK_Pos) /*!< CRYPTO_T::HMAC_FDBCK82: FDBCK Mask */ + +#define CRYPTO_HMAC_FDBCK83_FDBCK_Pos (0) /*!< CRYPTO_T::HMAC_FDBCK83: FDBCK Position */ +#define CRYPTO_HMAC_FDBCK83_FDBCK_Msk (0xfffffffful << CRYPTO_HMAC_FDBCK83_FDBCK_Pos) /*!< CRYPTO_T::HMAC_FDBCK83: FDBCK Mask */ + +#define CRYPTO_HMAC_FDBCK84_FDBCK_Pos (0) /*!< CRYPTO_T::HMAC_FDBCK84: FDBCK Position */ +#define CRYPTO_HMAC_FDBCK84_FDBCK_Msk (0xfffffffful << CRYPTO_HMAC_FDBCK84_FDBCK_Pos) /*!< CRYPTO_T::HMAC_FDBCK84: FDBCK Mask */ + +#define CRYPTO_HMAC_FDBCK85_FDBCK_Pos (0) /*!< CRYPTO_T::HMAC_FDBCK85: FDBCK Position */ +#define CRYPTO_HMAC_FDBCK85_FDBCK_Msk (0xfffffffful << CRYPTO_HMAC_FDBCK85_FDBCK_Pos) /*!< CRYPTO_T::HMAC_FDBCK85: FDBCK Mask */ + +#define CRYPTO_HMAC_FDBCK86_FDBCK_Pos (0) /*!< CRYPTO_T::HMAC_FDBCK86: FDBCK Position */ +#define CRYPTO_HMAC_FDBCK86_FDBCK_Msk (0xfffffffful << CRYPTO_HMAC_FDBCK86_FDBCK_Pos) /*!< CRYPTO_T::HMAC_FDBCK86: FDBCK Mask */ + +#define CRYPTO_HMAC_FDBCK87_FDBCK_Pos (0) /*!< CRYPTO_T::HMAC_FDBCK87: FDBCK Position */ +#define CRYPTO_HMAC_FDBCK87_FDBCK_Msk (0xfffffffful << CRYPTO_HMAC_FDBCK87_FDBCK_Pos) /*!< CRYPTO_T::HMAC_FDBCK87: FDBCK Mask */ + +#define CRYPTO_HMAC_SHA512T_SHA512TEN_Pos (0) /*!< CRYPTO_T::HMAC_SHA512T: SHA512TEN Position*/ +#define CRYPTO_HMAC_SHA512T_SHA512TEN_Msk (0x1ul << CRYPTO_HMAC_SHA512T_SHA512TEN_Pos) /*!< CRYPTO_T::HMAC_SHA512T: SHA512TEN Mask */ + +#define CRYPTO_HMAC_SHA512T_TLEN_Pos (8) /*!< CRYPTO_T::HMAC_SHA512T: TLEN Position */ +#define CRYPTO_HMAC_SHA512T_TLEN_Msk (0x1fful << CRYPTO_HMAC_SHA512T_TLEN_Pos) /*!< CRYPTO_T::HMAC_SHA512T: TLEN Mask */ + +#define CRYPTO_HMAC_FBADDR_FBADDR_Pos (0) /*!< CRYPTO_T::HMAC_FBADDR: FBADDR Position */ +#define CRYPTO_HMAC_FBADDR_FBADDR_Msk (0xfffffffful << CRYPTO_HMAC_FBADDR_FBADDR_Pos) /*!< CRYPTO_T::HMAC_FBADDR: FBADDR Mask */ + +#define CRYPTO_HMAC_SHAKEDGST0_DGST_Pos (0) /*!< CRYPTO_T::HMAC_SHAKEDGST0: DGST Position*/ +#define CRYPTO_HMAC_SHAKEDGST0_DGST_Msk (0xfffffffful << CRYPTO_HMAC_SHAKEDGST0_DGST_Pos) /*!< CRYPTO_T::HMAC_SHAKEDGST0: DGST Mask */ + +#define CRYPTO_HMAC_SHAKEDGST1_DGST_Pos (0) /*!< CRYPTO_T::HMAC_SHAKEDGST1: DGST Position*/ +#define CRYPTO_HMAC_SHAKEDGST1_DGST_Msk (0xfffffffful << CRYPTO_HMAC_SHAKEDGST1_DGST_Pos) /*!< CRYPTO_T::HMAC_SHAKEDGST1: DGST Mask */ + +#define CRYPTO_HMAC_SHAKEDGST2_DGST_Pos (0) /*!< CRYPTO_T::HMAC_SHAKEDGST2: DGST Position*/ +#define CRYPTO_HMAC_SHAKEDGST2_DGST_Msk (0xfffffffful << CRYPTO_HMAC_SHAKEDGST2_DGST_Pos) /*!< CRYPTO_T::HMAC_SHAKEDGST2: DGST Mask */ + +#define CRYPTO_HMAC_SHAKEDGST3_DGST_Pos (0) /*!< CRYPTO_T::HMAC_SHAKEDGST3: DGST Position*/ +#define CRYPTO_HMAC_SHAKEDGST3_DGST_Msk (0xfffffffful << CRYPTO_HMAC_SHAKEDGST3_DGST_Pos) /*!< CRYPTO_T::HMAC_SHAKEDGST3: DGST Mask */ + +#define CRYPTO_HMAC_SHAKEDGST4_DGST_Pos (0) /*!< CRYPTO_T::HMAC_SHAKEDGST4: DGST Position*/ +#define CRYPTO_HMAC_SHAKEDGST4_DGST_Msk (0xfffffffful << CRYPTO_HMAC_SHAKEDGST4_DGST_Pos) /*!< CRYPTO_T::HMAC_SHAKEDGST4: DGST Mask */ + +#define CRYPTO_HMAC_SHAKEDGST5_DGST_Pos (0) /*!< CRYPTO_T::HMAC_SHAKEDGST5: DGST Position*/ +#define CRYPTO_HMAC_SHAKEDGST5_DGST_Msk (0xfffffffful << CRYPTO_HMAC_SHAKEDGST5_DGST_Pos) /*!< CRYPTO_T::HMAC_SHAKEDGST5: DGST Mask */ + +#define CRYPTO_HMAC_SHAKEDGST6_DGST_Pos (0) /*!< CRYPTO_T::HMAC_SHAKEDGST6: DGST Position*/ +#define CRYPTO_HMAC_SHAKEDGST6_DGST_Msk (0xfffffffful << CRYPTO_HMAC_SHAKEDGST6_DGST_Pos) /*!< CRYPTO_T::HMAC_SHAKEDGST6: DGST Mask */ + +#define CRYPTO_HMAC_SHAKEDGST7_DGST_Pos (0) /*!< CRYPTO_T::HMAC_SHAKEDGST7: DGST Position*/ +#define CRYPTO_HMAC_SHAKEDGST7_DGST_Msk (0xfffffffful << CRYPTO_HMAC_SHAKEDGST7_DGST_Pos) /*!< CRYPTO_T::HMAC_SHAKEDGST7: DGST Mask */ + +#define CRYPTO_HMAC_SHAKEDGST8_DGST_Pos (0) /*!< CRYPTO_T::HMAC_SHAKEDGST8: DGST Position*/ +#define CRYPTO_HMAC_SHAKEDGST8_DGST_Msk (0xfffffffful << CRYPTO_HMAC_SHAKEDGST8_DGST_Pos) /*!< CRYPTO_T::HMAC_SHAKEDGST8: DGST Mask */ + +#define CRYPTO_HMAC_SHAKEDGST9_DGST_Pos (0) /*!< CRYPTO_T::HMAC_SHAKEDGST9: DGST Position*/ +#define CRYPTO_HMAC_SHAKEDGST9_DGST_Msk (0xfffffffful << CRYPTO_HMAC_SHAKEDGST9_DGST_Pos) /*!< CRYPTO_T::HMAC_SHAKEDGST9: DGST Mask */ + +#define CRYPTO_HMAC_SHAKEDGST10_DGST_Pos (0) /*!< CRYPTO_T::HMAC_SHAKEDGST10: DGST Position*/ +#define CRYPTO_HMAC_SHAKEDGST10_DGST_Msk (0xfffffffful << CRYPTO_HMAC_SHAKEDGST10_DGST_Pos) /*!< CRYPTO_T::HMAC_SHAKEDGST10: DGST Mask */ + +#define CRYPTO_HMAC_SHAKEDGST11_DGST_Pos (0) /*!< CRYPTO_T::HMAC_SHAKEDGST11: DGST Position*/ +#define CRYPTO_HMAC_SHAKEDGST11_DGST_Msk (0xfffffffful << CRYPTO_HMAC_SHAKEDGST11_DGST_Pos) /*!< CRYPTO_T::HMAC_SHAKEDGST11: DGST Mask */ + +#define CRYPTO_HMAC_SHAKEDGST12_DGST_Pos (0) /*!< CRYPTO_T::HMAC_SHAKEDGST12: DGST Position*/ +#define CRYPTO_HMAC_SHAKEDGST12_DGST_Msk (0xfffffffful << CRYPTO_HMAC_SHAKEDGST12_DGST_Pos) /*!< CRYPTO_T::HMAC_SHAKEDGST12: DGST Mask */ + +#define CRYPTO_HMAC_SHAKEDGST13_DGST_Pos (0) /*!< CRYPTO_T::HMAC_SHAKEDGST13: DGST Position*/ +#define CRYPTO_HMAC_SHAKEDGST13_DGST_Msk (0xfffffffful << CRYPTO_HMAC_SHAKEDGST13_DGST_Pos) /*!< CRYPTO_T::HMAC_SHAKEDGST13: DGST Mask */ + +#define CRYPTO_HMAC_SHAKEDGST14_DGST_Pos (0) /*!< CRYPTO_T::HMAC_SHAKEDGST14: DGST Position*/ +#define CRYPTO_HMAC_SHAKEDGST14_DGST_Msk (0xfffffffful << CRYPTO_HMAC_SHAKEDGST14_DGST_Pos) /*!< CRYPTO_T::HMAC_SHAKEDGST14: DGST Mask */ + +#define CRYPTO_HMAC_SHAKEDGST15_DGST_Pos (0) /*!< CRYPTO_T::HMAC_SHAKEDGST15: DGST Position*/ +#define CRYPTO_HMAC_SHAKEDGST15_DGST_Msk (0xfffffffful << CRYPTO_HMAC_SHAKEDGST15_DGST_Pos) /*!< CRYPTO_T::HMAC_SHAKEDGST15: DGST Mask */ + +#define CRYPTO_HMAC_SHAKEDGST16_DGST_Pos (0) /*!< CRYPTO_T::HMAC_SHAKEDGST16: DGST Position*/ +#define CRYPTO_HMAC_SHAKEDGST16_DGST_Msk (0xfffffffful << CRYPTO_HMAC_SHAKEDGST16_DGST_Pos) /*!< CRYPTO_T::HMAC_SHAKEDGST16: DGST Mask */ + +#define CRYPTO_HMAC_SHAKEDGST17_DGST_Pos (0) /*!< CRYPTO_T::HMAC_SHAKEDGST17: DGST Position*/ +#define CRYPTO_HMAC_SHAKEDGST17_DGST_Msk (0xfffffffful << CRYPTO_HMAC_SHAKEDGST17_DGST_Pos) /*!< CRYPTO_T::HMAC_SHAKEDGST17: DGST Mask */ + +#define CRYPTO_HMAC_SHAKEDGST18_DGST_Pos (0) /*!< CRYPTO_T::HMAC_SHAKEDGST18: DGST Position*/ +#define CRYPTO_HMAC_SHAKEDGST18_DGST_Msk (0xfffffffful << CRYPTO_HMAC_SHAKEDGST18_DGST_Pos) /*!< CRYPTO_T::HMAC_SHAKEDGST18: DGST Mask */ + +#define CRYPTO_HMAC_SHAKEDGST19_DGST_Pos (0) /*!< CRYPTO_T::HMAC_SHAKEDGST19: DGST Position*/ +#define CRYPTO_HMAC_SHAKEDGST19_DGST_Msk (0xfffffffful << CRYPTO_HMAC_SHAKEDGST19_DGST_Pos) /*!< CRYPTO_T::HMAC_SHAKEDGST19: DGST Mask */ + +#define CRYPTO_HMAC_SHAKEDGST20_DGST_Pos (0) /*!< CRYPTO_T::HMAC_SHAKEDGST20: DGST Position*/ +#define CRYPTO_HMAC_SHAKEDGST20_DGST_Msk (0xfffffffful << CRYPTO_HMAC_SHAKEDGST20_DGST_Pos) /*!< CRYPTO_T::HMAC_SHAKEDGST20: DGST Mask */ + +#define CRYPTO_HMAC_SHAKEDGST21_DGST_Pos (0) /*!< CRYPTO_T::HMAC_SHAKEDGST21: DGST Position*/ +#define CRYPTO_HMAC_SHAKEDGST21_DGST_Msk (0xfffffffful << CRYPTO_HMAC_SHAKEDGST21_DGST_Pos) /*!< CRYPTO_T::HMAC_SHAKEDGST21: DGST Mask */ + +#define CRYPTO_HMAC_SHAKEDGST22_DGST_Pos (0) /*!< CRYPTO_T::HMAC_SHAKEDGST22: DGST Position*/ +#define CRYPTO_HMAC_SHAKEDGST22_DGST_Msk (0xfffffffful << CRYPTO_HMAC_SHAKEDGST22_DGST_Pos) /*!< CRYPTO_T::HMAC_SHAKEDGST22: DGST Mask */ + +#define CRYPTO_HMAC_SHAKEDGST23_DGST_Pos (0) /*!< CRYPTO_T::HMAC_SHAKEDGST23: DGST Position*/ +#define CRYPTO_HMAC_SHAKEDGST23_DGST_Msk (0xfffffffful << CRYPTO_HMAC_SHAKEDGST23_DGST_Pos) /*!< CRYPTO_T::HMAC_SHAKEDGST23: DGST Mask */ + +#define CRYPTO_HMAC_SHAKEDGST24_DGST_Pos (0) /*!< CRYPTO_T::HMAC_SHAKEDGST24: DGST Position*/ +#define CRYPTO_HMAC_SHAKEDGST24_DGST_Msk (0xfffffffful << CRYPTO_HMAC_SHAKEDGST24_DGST_Pos) /*!< CRYPTO_T::HMAC_SHAKEDGST24: DGST Mask */ + +#define CRYPTO_HMAC_SHAKEDGST25_DGST_Pos (0) /*!< CRYPTO_T::HMAC_SHAKEDGST25: DGST Position*/ +#define CRYPTO_HMAC_SHAKEDGST25_DGST_Msk (0xfffffffful << CRYPTO_HMAC_SHAKEDGST25_DGST_Pos) /*!< CRYPTO_T::HMAC_SHAKEDGST25: DGST Mask */ + +#define CRYPTO_HMAC_SHAKEDGST26_DGST_Pos (0) /*!< CRYPTO_T::HMAC_SHAKEDGST26: DGST Position*/ +#define CRYPTO_HMAC_SHAKEDGST26_DGST_Msk (0xfffffffful << CRYPTO_HMAC_SHAKEDGST26_DGST_Pos) /*!< CRYPTO_T::HMAC_SHAKEDGST26: DGST Mask */ + +#define CRYPTO_HMAC_SHAKEDGST27_DGST_Pos (0) /*!< CRYPTO_T::HMAC_SHAKEDGST27: DGST Position*/ +#define CRYPTO_HMAC_SHAKEDGST27_DGST_Msk (0xfffffffful << CRYPTO_HMAC_SHAKEDGST27_DGST_Pos) /*!< CRYPTO_T::HMAC_SHAKEDGST27: DGST Mask */ + +#define CRYPTO_HMAC_SHAKEDGST28_DGST_Pos (0) /*!< CRYPTO_T::HMAC_SHAKEDGST28: DGST Position*/ +#define CRYPTO_HMAC_SHAKEDGST28_DGST_Msk (0xfffffffful << CRYPTO_HMAC_SHAKEDGST28_DGST_Pos) /*!< CRYPTO_T::HMAC_SHAKEDGST28: DGST Mask */ + +#define CRYPTO_HMAC_SHAKEDGST29_DGST_Pos (0) /*!< CRYPTO_T::HMAC_SHAKEDGST29: DGST Position*/ +#define CRYPTO_HMAC_SHAKEDGST29_DGST_Msk (0xfffffffful << CRYPTO_HMAC_SHAKEDGST29_DGST_Pos) /*!< CRYPTO_T::HMAC_SHAKEDGST29: DGST Mask */ + +#define CRYPTO_HMAC_SHAKEDGST30_DGST_Pos (0) /*!< CRYPTO_T::HMAC_SHAKEDGST30: DGST Position*/ +#define CRYPTO_HMAC_SHAKEDGST30_DGST_Msk (0xfffffffful << CRYPTO_HMAC_SHAKEDGST30_DGST_Pos) /*!< CRYPTO_T::HMAC_SHAKEDGST30: DGST Mask */ + +#define CRYPTO_HMAC_SHAKEDGST31_DGST_Pos (0) /*!< CRYPTO_T::HMAC_SHAKEDGST31: DGST Position*/ +#define CRYPTO_HMAC_SHAKEDGST31_DGST_Msk (0xfffffffful << CRYPTO_HMAC_SHAKEDGST31_DGST_Pos) /*!< CRYPTO_T::HMAC_SHAKEDGST31: DGST Mask */ + +#define CRYPTO_HMAC_SHAKEDGST32_DGST_Pos (0) /*!< CRYPTO_T::HMAC_SHAKEDGST32: DGST Position*/ +#define CRYPTO_HMAC_SHAKEDGST32_DGST_Msk (0xfffffffful << CRYPTO_HMAC_SHAKEDGST32_DGST_Pos) /*!< CRYPTO_T::HMAC_SHAKEDGST32: DGST Mask */ + +#define CRYPTO_HMAC_SHAKEDGST33_DGST_Pos (0) /*!< CRYPTO_T::HMAC_SHAKEDGST33: DGST Position*/ +#define CRYPTO_HMAC_SHAKEDGST33_DGST_Msk (0xfffffffful << CRYPTO_HMAC_SHAKEDGST33_DGST_Pos) /*!< CRYPTO_T::HMAC_SHAKEDGST33: DGST Mask */ + +#define CRYPTO_HMAC_SHAKEDGST34_DGST_Pos (0) /*!< CRYPTO_T::HMAC_SHAKEDGST34: DGST Position*/ +#define CRYPTO_HMAC_SHAKEDGST34_DGST_Msk (0xfffffffful << CRYPTO_HMAC_SHAKEDGST34_DGST_Pos) /*!< CRYPTO_T::HMAC_SHAKEDGST34: DGST Mask */ + +#define CRYPTO_HMAC_SHAKEDGST35_DGST_Pos (0) /*!< CRYPTO_T::HMAC_SHAKEDGST35: DGST Position*/ +#define CRYPTO_HMAC_SHAKEDGST35_DGST_Msk (0xfffffffful << CRYPTO_HMAC_SHAKEDGST35_DGST_Pos) /*!< CRYPTO_T::HMAC_SHAKEDGST35: DGST Mask */ + +#define CRYPTO_HMAC_SHAKEDGST36_DGST_Pos (0) /*!< CRYPTO_T::HMAC_SHAKEDGST36: DGST Position*/ +#define CRYPTO_HMAC_SHAKEDGST36_DGST_Msk (0xfffffffful << CRYPTO_HMAC_SHAKEDGST36_DGST_Pos) /*!< CRYPTO_T::HMAC_SHAKEDGST36: DGST Mask */ + +#define CRYPTO_HMAC_SHAKEDGST37_DGST_Pos (0) /*!< CRYPTO_T::HMAC_SHAKEDGST37: DGST Position*/ +#define CRYPTO_HMAC_SHAKEDGST37_DGST_Msk (0xfffffffful << CRYPTO_HMAC_SHAKEDGST37_DGST_Pos) /*!< CRYPTO_T::HMAC_SHAKEDGST37: DGST Mask */ + +#define CRYPTO_HMAC_SHAKEDGST38_DGST_Pos (0) /*!< CRYPTO_T::HMAC_SHAKEDGST38: DGST Position*/ +#define CRYPTO_HMAC_SHAKEDGST38_DGST_Msk (0xfffffffful << CRYPTO_HMAC_SHAKEDGST38_DGST_Pos) /*!< CRYPTO_T::HMAC_SHAKEDGST38: DGST Mask */ + +#define CRYPTO_HMAC_SHAKEDGST39_DGST_Pos (0) /*!< CRYPTO_T::HMAC_SHAKEDGST39: DGST Position*/ +#define CRYPTO_HMAC_SHAKEDGST39_DGST_Msk (0xfffffffful << CRYPTO_HMAC_SHAKEDGST39_DGST_Pos) /*!< CRYPTO_T::HMAC_SHAKEDGST39: DGST Mask */ + +#define CRYPTO_HMAC_SHAKEDGST40_DGST_Pos (0) /*!< CRYPTO_T::HMAC_SHAKEDGST40: DGST Position*/ +#define CRYPTO_HMAC_SHAKEDGST40_DGST_Msk (0xfffffffful << CRYPTO_HMAC_SHAKEDGST40_DGST_Pos) /*!< CRYPTO_T::HMAC_SHAKEDGST40: DGST Mask */ + +#define CRYPTO_HMAC_SHAKEDGST41_DGST_Pos (0) /*!< CRYPTO_T::HMAC_SHAKEDGST41: DGST Position*/ +#define CRYPTO_HMAC_SHAKEDGST41_DGST_Msk (0xfffffffful << CRYPTO_HMAC_SHAKEDGST41_DGST_Pos) /*!< CRYPTO_T::HMAC_SHAKEDGST41: DGST Mask */ + +#define CRYPTO_ECC_CTL_START_Pos (0) /*!< CRYPTO_T::ECC_CTL: START Position */ +#define CRYPTO_ECC_CTL_START_Msk (0x1ul << CRYPTO_ECC_CTL_START_Pos) /*!< CRYPTO_T::ECC_CTL: START Mask */ + +#define CRYPTO_ECC_CTL_STOP_Pos (1) /*!< CRYPTO_T::ECC_CTL: STOP Position */ +#define CRYPTO_ECC_CTL_STOP_Msk (0x1ul << CRYPTO_ECC_CTL_STOP_Pos) /*!< CRYPTO_T::ECC_CTL: STOP Mask */ + +#define CRYPTO_ECC_CTL_ECDSAS_Pos (4) /*!< CRYPTO_T::ECC_CTL: ECDSAS Position */ +#define CRYPTO_ECC_CTL_ECDSAS_Msk (0x1ul << CRYPTO_ECC_CTL_ECDSAS_Pos) /*!< CRYPTO_T::ECC_CTL: ECDSAS Mask */ + +#define CRYPTO_ECC_CTL_ECDSAR_Pos (5) /*!< CRYPTO_T::ECC_CTL: ECDSAR Position */ +#define CRYPTO_ECC_CTL_ECDSAR_Msk (0x1ul << CRYPTO_ECC_CTL_ECDSAR_Pos) /*!< CRYPTO_T::ECC_CTL: ECDSAR Mask */ + +#define CRYPTO_ECC_CTL_DMAEN_Pos (7) /*!< CRYPTO_T::ECC_CTL: DMAEN Position */ +#define CRYPTO_ECC_CTL_DMAEN_Msk (0x1ul << CRYPTO_ECC_CTL_DMAEN_Pos) /*!< CRYPTO_T::ECC_CTL: DMAEN Mask */ + +#define CRYPTO_ECC_CTL_FSEL_Pos (8) /*!< CRYPTO_T::ECC_CTL: FSEL Position */ +#define CRYPTO_ECC_CTL_FSEL_Msk (0x1ul << CRYPTO_ECC_CTL_FSEL_Pos) /*!< CRYPTO_T::ECC_CTL: FSEL Mask */ + +#define CRYPTO_ECC_CTL_ECCOP_Pos (9) /*!< CRYPTO_T::ECC_CTL: ECCOP Position */ +#define CRYPTO_ECC_CTL_ECCOP_Msk (0x3ul << CRYPTO_ECC_CTL_ECCOP_Pos) /*!< CRYPTO_T::ECC_CTL: ECCOP Mask */ + +#define CRYPTO_ECC_CTL_MODOP_Pos (11) /*!< CRYPTO_T::ECC_CTL: MODOP Position */ +#define CRYPTO_ECC_CTL_MODOP_Msk (0x3ul << CRYPTO_ECC_CTL_MODOP_Pos) /*!< CRYPTO_T::ECC_CTL: MODOP Mask */ + +#define CRYPTO_ECC_CTL_CSEL_Pos (13) /*!< CRYPTO_T::ECC_CTL: CSEL Position */ +#define CRYPTO_ECC_CTL_CSEL_Msk (0x1ul << CRYPTO_ECC_CTL_CSEL_Pos) /*!< CRYPTO_T::ECC_CTL: CSEL Mask */ + +#define CRYPTO_ECC_CTL_SCAP_Pos (14) /*!< CRYPTO_T::ECC_CTL: SCAP Position */ +#define CRYPTO_ECC_CTL_SCAP_Msk (0x1ul << CRYPTO_ECC_CTL_SCAP_Pos) /*!< CRYPTO_T::ECC_CTL: SCAP Mask */ + +#define CRYPTO_ECC_CTL_ASCAP_Pos (15) /*!< CRYPTO_T::ECC_CTL: ASCAP Position */ +#define CRYPTO_ECC_CTL_ASCAP_Msk (0x1ul << CRYPTO_ECC_CTL_ASCAP_Pos) /*!< CRYPTO_T::ECC_CTL: ASCAP Mask */ + +#define CRYPTO_ECC_CTL_LDP1_Pos (16) /*!< CRYPTO_T::ECC_CTL: LDP1 Position */ +#define CRYPTO_ECC_CTL_LDP1_Msk (0x1ul << CRYPTO_ECC_CTL_LDP1_Pos) /*!< CRYPTO_T::ECC_CTL: LDP1 Mask */ + +#define CRYPTO_ECC_CTL_LDP2_Pos (17) /*!< CRYPTO_T::ECC_CTL: LDP2 Position */ +#define CRYPTO_ECC_CTL_LDP2_Msk (0x1ul << CRYPTO_ECC_CTL_LDP2_Pos) /*!< CRYPTO_T::ECC_CTL: LDP2 Mask */ + +#define CRYPTO_ECC_CTL_LDA_Pos (18) /*!< CRYPTO_T::ECC_CTL: LDA Position */ +#define CRYPTO_ECC_CTL_LDA_Msk (0x1ul << CRYPTO_ECC_CTL_LDA_Pos) /*!< CRYPTO_T::ECC_CTL: LDA Mask */ + +#define CRYPTO_ECC_CTL_LDB_Pos (19) /*!< CRYPTO_T::ECC_CTL: LDB Position */ +#define CRYPTO_ECC_CTL_LDB_Msk (0x1ul << CRYPTO_ECC_CTL_LDB_Pos) /*!< CRYPTO_T::ECC_CTL: LDB Mask */ + +#define CRYPTO_ECC_CTL_LDN_Pos (20) /*!< CRYPTO_T::ECC_CTL: LDN Position */ +#define CRYPTO_ECC_CTL_LDN_Msk (0x1ul << CRYPTO_ECC_CTL_LDN_Pos) /*!< CRYPTO_T::ECC_CTL: LDN Mask */ + +#define CRYPTO_ECC_CTL_LDK_Pos (21) /*!< CRYPTO_T::ECC_CTL: LDK Position */ +#define CRYPTO_ECC_CTL_LDK_Msk (0x1ul << CRYPTO_ECC_CTL_LDK_Pos) /*!< CRYPTO_T::ECC_CTL: LDK Mask */ + +#define CRYPTO_ECC_CTL_CURVEM_Pos (22) /*!< CRYPTO_T::ECC_CTL: CURVEM Position */ +#define CRYPTO_ECC_CTL_CURVEM_Msk (0x3fful << CRYPTO_ECC_CTL_CURVEM_Pos) /*!< CRYPTO_T::ECC_CTL: CURVEM Mask */ + +#define CRYPTO_ECC_STS_BUSY_Pos (0) /*!< CRYPTO_T::ECC_STS: BUSY Position */ +#define CRYPTO_ECC_STS_BUSY_Msk (0x1ul << CRYPTO_ECC_STS_BUSY_Pos) /*!< CRYPTO_T::ECC_STS: BUSY Mask */ + +#define CRYPTO_ECC_STS_DMABUSY_Pos (1) /*!< CRYPTO_T::ECC_STS: DMABUSY Position */ +#define CRYPTO_ECC_STS_DMABUSY_Msk (0x1ul << CRYPTO_ECC_STS_DMABUSY_Pos) /*!< CRYPTO_T::ECC_STS: DMABUSY Mask */ + +#define CRYPTO_ECC_STS_BUSERR_Pos (16) /*!< CRYPTO_T::ECC_STS: BUSERR Position */ +#define CRYPTO_ECC_STS_BUSERR_Msk (0x1ul << CRYPTO_ECC_STS_BUSERR_Pos) /*!< CRYPTO_T::ECC_STS: BUSERR Mask */ + +#define CRYPTO_ECC_STS_KSERR_Pos (17) /*!< CRYPTO_T::ECC_STS: KSERR Position */ +#define CRYPTO_ECC_STS_KSERR_Msk (0x1ul << CRYPTO_ECC_STS_KSERR_Pos) /*!< CRYPTO_T::ECC_STS: KSERR Mask */ + +#define CRYPTO_ECC_STS_DFAERR_Pos (18) /*!< CRYPTO_T::ECC_STS: DFAERR Position */ +#define CRYPTO_ECC_STS_DFAERR_Msk (0x1ul << CRYPTO_ECC_STS_DFAERR_Pos) /*!< CRYPTO_T::ECC_STS: DFAERR Mask */ + +#define CRYPTO_ECC_X1_00_POINTX1_Pos (0) /*!< CRYPTO_T::ECC_X1_00: POINTX1 Position */ +#define CRYPTO_ECC_X1_00_POINTX1_Msk (0xfffffffful << CRYPTO_ECC_X1_00_POINTX1_Pos) /*!< CRYPTO_T::ECC_X1_00: POINTX1 Mask */ + +#define CRYPTO_ECC_X1_01_POINTX1_Pos (0) /*!< CRYPTO_T::ECC_X1_01: POINTX1 Position */ +#define CRYPTO_ECC_X1_01_POINTX1_Msk (0xfffffffful << CRYPTO_ECC_X1_01_POINTX1_Pos) /*!< CRYPTO_T::ECC_X1_01: POINTX1 Mask */ + +#define CRYPTO_ECC_X1_02_POINTX1_Pos (0) /*!< CRYPTO_T::ECC_X1_02: POINTX1 Position */ +#define CRYPTO_ECC_X1_02_POINTX1_Msk (0xfffffffful << CRYPTO_ECC_X1_02_POINTX1_Pos) /*!< CRYPTO_T::ECC_X1_02: POINTX1 Mask */ + +#define CRYPTO_ECC_X1_03_POINTX1_Pos (0) /*!< CRYPTO_T::ECC_X1_03: POINTX1 Position */ +#define CRYPTO_ECC_X1_03_POINTX1_Msk (0xfffffffful << CRYPTO_ECC_X1_03_POINTX1_Pos) /*!< CRYPTO_T::ECC_X1_03: POINTX1 Mask */ + +#define CRYPTO_ECC_X1_04_POINTX1_Pos (0) /*!< CRYPTO_T::ECC_X1_04: POINTX1 Position */ +#define CRYPTO_ECC_X1_04_POINTX1_Msk (0xfffffffful << CRYPTO_ECC_X1_04_POINTX1_Pos) /*!< CRYPTO_T::ECC_X1_04: POINTX1 Mask */ + +#define CRYPTO_ECC_X1_05_POINTX1_Pos (0) /*!< CRYPTO_T::ECC_X1_05: POINTX1 Position */ +#define CRYPTO_ECC_X1_05_POINTX1_Msk (0xfffffffful << CRYPTO_ECC_X1_05_POINTX1_Pos) /*!< CRYPTO_T::ECC_X1_05: POINTX1 Mask */ + +#define CRYPTO_ECC_X1_06_POINTX1_Pos (0) /*!< CRYPTO_T::ECC_X1_06: POINTX1 Position */ +#define CRYPTO_ECC_X1_06_POINTX1_Msk (0xfffffffful << CRYPTO_ECC_X1_06_POINTX1_Pos) /*!< CRYPTO_T::ECC_X1_06: POINTX1 Mask */ + +#define CRYPTO_ECC_X1_07_POINTX1_Pos (0) /*!< CRYPTO_T::ECC_X1_07: POINTX1 Position */ +#define CRYPTO_ECC_X1_07_POINTX1_Msk (0xfffffffful << CRYPTO_ECC_X1_07_POINTX1_Pos) /*!< CRYPTO_T::ECC_X1_07: POINTX1 Mask */ + +#define CRYPTO_ECC_X1_08_POINTX1_Pos (0) /*!< CRYPTO_T::ECC_X1_08: POINTX1 Position */ +#define CRYPTO_ECC_X1_08_POINTX1_Msk (0xfffffffful << CRYPTO_ECC_X1_08_POINTX1_Pos) /*!< CRYPTO_T::ECC_X1_08: POINTX1 Mask */ + +#define CRYPTO_ECC_X1_09_POINTX1_Pos (0) /*!< CRYPTO_T::ECC_X1_09: POINTX1 Position */ +#define CRYPTO_ECC_X1_09_POINTX1_Msk (0xfffffffful << CRYPTO_ECC_X1_09_POINTX1_Pos) /*!< CRYPTO_T::ECC_X1_09: POINTX1 Mask */ + +#define CRYPTO_ECC_X1_10_POINTX1_Pos (0) /*!< CRYPTO_T::ECC_X1_10: POINTX1 Position */ +#define CRYPTO_ECC_X1_10_POINTX1_Msk (0xfffffffful << CRYPTO_ECC_X1_10_POINTX1_Pos) /*!< CRYPTO_T::ECC_X1_10: POINTX1 Mask */ + +#define CRYPTO_ECC_X1_11_POINTX1_Pos (0) /*!< CRYPTO_T::ECC_X1_11: POINTX1 Position */ +#define CRYPTO_ECC_X1_11_POINTX1_Msk (0xfffffffful << CRYPTO_ECC_X1_11_POINTX1_Pos) /*!< CRYPTO_T::ECC_X1_11: POINTX1 Mask */ + +#define CRYPTO_ECC_X1_12_POINTX1_Pos (0) /*!< CRYPTO_T::ECC_X1_12: POINTX1 Position */ +#define CRYPTO_ECC_X1_12_POINTX1_Msk (0xfffffffful << CRYPTO_ECC_X1_12_POINTX1_Pos) /*!< CRYPTO_T::ECC_X1_12: POINTX1 Mask */ + +#define CRYPTO_ECC_X1_13_POINTX1_Pos (0) /*!< CRYPTO_T::ECC_X1_13: POINTX1 Position */ +#define CRYPTO_ECC_X1_13_POINTX1_Msk (0xfffffffful << CRYPTO_ECC_X1_13_POINTX1_Pos) /*!< CRYPTO_T::ECC_X1_13: POINTX1 Mask */ + +#define CRYPTO_ECC_X1_14_POINTX1_Pos (0) /*!< CRYPTO_T::ECC_X1_14: POINTX1 Position */ +#define CRYPTO_ECC_X1_14_POINTX1_Msk (0xfffffffful << CRYPTO_ECC_X1_14_POINTX1_Pos) /*!< CRYPTO_T::ECC_X1_14: POINTX1 Mask */ + +#define CRYPTO_ECC_X1_15_POINTX1_Pos (0) /*!< CRYPTO_T::ECC_X1_15: POINTX1 Position */ +#define CRYPTO_ECC_X1_15_POINTX1_Msk (0xfffffffful << CRYPTO_ECC_X1_15_POINTX1_Pos) /*!< CRYPTO_T::ECC_X1_15: POINTX1 Mask */ + +#define CRYPTO_ECC_X1_16_POINTX1_Pos (0) /*!< CRYPTO_T::ECC_X1_16: POINTX1 Position */ +#define CRYPTO_ECC_X1_16_POINTX1_Msk (0xfffffffful << CRYPTO_ECC_X1_16_POINTX1_Pos) /*!< CRYPTO_T::ECC_X1_16: POINTX1 Mask */ + +#define CRYPTO_ECC_X1_17_POINTX1_Pos (0) /*!< CRYPTO_T::ECC_X1_17: POINTX1 Position */ +#define CRYPTO_ECC_X1_17_POINTX1_Msk (0xfffffffful << CRYPTO_ECC_X1_17_POINTX1_Pos) /*!< CRYPTO_T::ECC_X1_17: POINTX1 Mask */ + +#define CRYPTO_ECC_Y1_00_POINTY1_Pos (0) /*!< CRYPTO_T::ECC_Y1_00: POINTY1 Position */ +#define CRYPTO_ECC_Y1_00_POINTY1_Msk (0xfffffffful << CRYPTO_ECC_Y1_00_POINTY1_Pos) /*!< CRYPTO_T::ECC_Y1_00: POINTY1 Mask */ + +#define CRYPTO_ECC_Y1_01_POINTY1_Pos (0) /*!< CRYPTO_T::ECC_Y1_01: POINTY1 Position */ +#define CRYPTO_ECC_Y1_01_POINTY1_Msk (0xfffffffful << CRYPTO_ECC_Y1_01_POINTY1_Pos) /*!< CRYPTO_T::ECC_Y1_01: POINTY1 Mask */ + +#define CRYPTO_ECC_Y1_02_POINTY1_Pos (0) /*!< CRYPTO_T::ECC_Y1_02: POINTY1 Position */ +#define CRYPTO_ECC_Y1_02_POINTY1_Msk (0xfffffffful << CRYPTO_ECC_Y1_02_POINTY1_Pos) /*!< CRYPTO_T::ECC_Y1_02: POINTY1 Mask */ + +#define CRYPTO_ECC_Y1_03_POINTY1_Pos (0) /*!< CRYPTO_T::ECC_Y1_03: POINTY1 Position */ +#define CRYPTO_ECC_Y1_03_POINTY1_Msk (0xfffffffful << CRYPTO_ECC_Y1_03_POINTY1_Pos) /*!< CRYPTO_T::ECC_Y1_03: POINTY1 Mask */ + +#define CRYPTO_ECC_Y1_04_POINTY1_Pos (0) /*!< CRYPTO_T::ECC_Y1_04: POINTY1 Position */ +#define CRYPTO_ECC_Y1_04_POINTY1_Msk (0xfffffffful << CRYPTO_ECC_Y1_04_POINTY1_Pos) /*!< CRYPTO_T::ECC_Y1_04: POINTY1 Mask */ + +#define CRYPTO_ECC_Y1_05_POINTY1_Pos (0) /*!< CRYPTO_T::ECC_Y1_05: POINTY1 Position */ +#define CRYPTO_ECC_Y1_05_POINTY1_Msk (0xfffffffful << CRYPTO_ECC_Y1_05_POINTY1_Pos) /*!< CRYPTO_T::ECC_Y1_05: POINTY1 Mask */ + +#define CRYPTO_ECC_Y1_06_POINTY1_Pos (0) /*!< CRYPTO_T::ECC_Y1_06: POINTY1 Position */ +#define CRYPTO_ECC_Y1_06_POINTY1_Msk (0xfffffffful << CRYPTO_ECC_Y1_06_POINTY1_Pos) /*!< CRYPTO_T::ECC_Y1_06: POINTY1 Mask */ + +#define CRYPTO_ECC_Y1_07_POINTY1_Pos (0) /*!< CRYPTO_T::ECC_Y1_07: POINTY1 Position */ +#define CRYPTO_ECC_Y1_07_POINTY1_Msk (0xfffffffful << CRYPTO_ECC_Y1_07_POINTY1_Pos) /*!< CRYPTO_T::ECC_Y1_07: POINTY1 Mask */ + +#define CRYPTO_ECC_Y1_08_POINTY1_Pos (0) /*!< CRYPTO_T::ECC_Y1_08: POINTY1 Position */ +#define CRYPTO_ECC_Y1_08_POINTY1_Msk (0xfffffffful << CRYPTO_ECC_Y1_08_POINTY1_Pos) /*!< CRYPTO_T::ECC_Y1_08: POINTY1 Mask */ + +#define CRYPTO_ECC_Y1_09_POINTY1_Pos (0) /*!< CRYPTO_T::ECC_Y1_09: POINTY1 Position */ +#define CRYPTO_ECC_Y1_09_POINTY1_Msk (0xfffffffful << CRYPTO_ECC_Y1_09_POINTY1_Pos) /*!< CRYPTO_T::ECC_Y1_09: POINTY1 Mask */ + +#define CRYPTO_ECC_Y1_10_POINTY1_Pos (0) /*!< CRYPTO_T::ECC_Y1_10: POINTY1 Position */ +#define CRYPTO_ECC_Y1_10_POINTY1_Msk (0xfffffffful << CRYPTO_ECC_Y1_10_POINTY1_Pos) /*!< CRYPTO_T::ECC_Y1_10: POINTY1 Mask */ + +#define CRYPTO_ECC_Y1_11_POINTY1_Pos (0) /*!< CRYPTO_T::ECC_Y1_11: POINTY1 Position */ +#define CRYPTO_ECC_Y1_11_POINTY1_Msk (0xfffffffful << CRYPTO_ECC_Y1_11_POINTY1_Pos) /*!< CRYPTO_T::ECC_Y1_11: POINTY1 Mask */ + +#define CRYPTO_ECC_Y1_12_POINTY1_Pos (0) /*!< CRYPTO_T::ECC_Y1_12: POINTY1 Position */ +#define CRYPTO_ECC_Y1_12_POINTY1_Msk (0xfffffffful << CRYPTO_ECC_Y1_12_POINTY1_Pos) /*!< CRYPTO_T::ECC_Y1_12: POINTY1 Mask */ + +#define CRYPTO_ECC_Y1_13_POINTY1_Pos (0) /*!< CRYPTO_T::ECC_Y1_13: POINTY1 Position */ +#define CRYPTO_ECC_Y1_13_POINTY1_Msk (0xfffffffful << CRYPTO_ECC_Y1_13_POINTY1_Pos) /*!< CRYPTO_T::ECC_Y1_13: POINTY1 Mask */ + +#define CRYPTO_ECC_Y1_14_POINTY1_Pos (0) /*!< CRYPTO_T::ECC_Y1_14: POINTY1 Position */ +#define CRYPTO_ECC_Y1_14_POINTY1_Msk (0xfffffffful << CRYPTO_ECC_Y1_14_POINTY1_Pos) /*!< CRYPTO_T::ECC_Y1_14: POINTY1 Mask */ + +#define CRYPTO_ECC_Y1_15_POINTY1_Pos (0) /*!< CRYPTO_T::ECC_Y1_15: POINTY1 Position */ +#define CRYPTO_ECC_Y1_15_POINTY1_Msk (0xfffffffful << CRYPTO_ECC_Y1_15_POINTY1_Pos) /*!< CRYPTO_T::ECC_Y1_15: POINTY1 Mask */ + +#define CRYPTO_ECC_Y1_16_POINTY1_Pos (0) /*!< CRYPTO_T::ECC_Y1_16: POINTY1 Position */ +#define CRYPTO_ECC_Y1_16_POINTY1_Msk (0xfffffffful << CRYPTO_ECC_Y1_16_POINTY1_Pos) /*!< CRYPTO_T::ECC_Y1_16: POINTY1 Mask */ + +#define CRYPTO_ECC_Y1_17_POINTY1_Pos (0) /*!< CRYPTO_T::ECC_Y1_17: POINTY1 Position */ +#define CRYPTO_ECC_Y1_17_POINTY1_Msk (0xfffffffful << CRYPTO_ECC_Y1_17_POINTY1_Pos) /*!< CRYPTO_T::ECC_Y1_17: POINTY1 Mask */ + +#define CRYPTO_ECC_X2_00_POINTX2_Pos (0) /*!< CRYPTO_T::ECC_X2_00: POINTX2 Position */ +#define CRYPTO_ECC_X2_00_POINTX2_Msk (0xfffffffful << CRYPTO_ECC_X2_00_POINTX2_Pos) /*!< CRYPTO_T::ECC_X2_00: POINTX2 Mask */ + +#define CRYPTO_ECC_X2_01_POINTX2_Pos (0) /*!< CRYPTO_T::ECC_X2_01: POINTX2 Position */ +#define CRYPTO_ECC_X2_01_POINTX2_Msk (0xfffffffful << CRYPTO_ECC_X2_01_POINTX2_Pos) /*!< CRYPTO_T::ECC_X2_01: POINTX2 Mask */ + +#define CRYPTO_ECC_X2_02_POINTX2_Pos (0) /*!< CRYPTO_T::ECC_X2_02: POINTX2 Position */ +#define CRYPTO_ECC_X2_02_POINTX2_Msk (0xfffffffful << CRYPTO_ECC_X2_02_POINTX2_Pos) /*!< CRYPTO_T::ECC_X2_02: POINTX2 Mask */ + +#define CRYPTO_ECC_X2_03_POINTX2_Pos (0) /*!< CRYPTO_T::ECC_X2_03: POINTX2 Position */ +#define CRYPTO_ECC_X2_03_POINTX2_Msk (0xfffffffful << CRYPTO_ECC_X2_03_POINTX2_Pos) /*!< CRYPTO_T::ECC_X2_03: POINTX2 Mask */ + +#define CRYPTO_ECC_X2_04_POINTX2_Pos (0) /*!< CRYPTO_T::ECC_X2_04: POINTX2 Position */ +#define CRYPTO_ECC_X2_04_POINTX2_Msk (0xfffffffful << CRYPTO_ECC_X2_04_POINTX2_Pos) /*!< CRYPTO_T::ECC_X2_04: POINTX2 Mask */ + +#define CRYPTO_ECC_X2_05_POINTX2_Pos (0) /*!< CRYPTO_T::ECC_X2_05: POINTX2 Position */ +#define CRYPTO_ECC_X2_05_POINTX2_Msk (0xfffffffful << CRYPTO_ECC_X2_05_POINTX2_Pos) /*!< CRYPTO_T::ECC_X2_05: POINTX2 Mask */ + +#define CRYPTO_ECC_X2_06_POINTX2_Pos (0) /*!< CRYPTO_T::ECC_X2_06: POINTX2 Position */ +#define CRYPTO_ECC_X2_06_POINTX2_Msk (0xfffffffful << CRYPTO_ECC_X2_06_POINTX2_Pos) /*!< CRYPTO_T::ECC_X2_06: POINTX2 Mask */ + +#define CRYPTO_ECC_X2_07_POINTX2_Pos (0) /*!< CRYPTO_T::ECC_X2_07: POINTX2 Position */ +#define CRYPTO_ECC_X2_07_POINTX2_Msk (0xfffffffful << CRYPTO_ECC_X2_07_POINTX2_Pos) /*!< CRYPTO_T::ECC_X2_07: POINTX2 Mask */ + +#define CRYPTO_ECC_X2_08_POINTX2_Pos (0) /*!< CRYPTO_T::ECC_X2_08: POINTX2 Position */ +#define CRYPTO_ECC_X2_08_POINTX2_Msk (0xfffffffful << CRYPTO_ECC_X2_08_POINTX2_Pos) /*!< CRYPTO_T::ECC_X2_08: POINTX2 Mask */ + +#define CRYPTO_ECC_X2_09_POINTX2_Pos (0) /*!< CRYPTO_T::ECC_X2_09: POINTX2 Position */ +#define CRYPTO_ECC_X2_09_POINTX2_Msk (0xfffffffful << CRYPTO_ECC_X2_09_POINTX2_Pos) /*!< CRYPTO_T::ECC_X2_09: POINTX2 Mask */ + +#define CRYPTO_ECC_X2_10_POINTX2_Pos (0) /*!< CRYPTO_T::ECC_X2_10: POINTX2 Position */ +#define CRYPTO_ECC_X2_10_POINTX2_Msk (0xfffffffful << CRYPTO_ECC_X2_10_POINTX2_Pos) /*!< CRYPTO_T::ECC_X2_10: POINTX2 Mask */ + +#define CRYPTO_ECC_X2_11_POINTX2_Pos (0) /*!< CRYPTO_T::ECC_X2_11: POINTX2 Position */ +#define CRYPTO_ECC_X2_11_POINTX2_Msk (0xfffffffful << CRYPTO_ECC_X2_11_POINTX2_Pos) /*!< CRYPTO_T::ECC_X2_11: POINTX2 Mask */ + +#define CRYPTO_ECC_X2_12_POINTX2_Pos (0) /*!< CRYPTO_T::ECC_X2_12: POINTX2 Position */ +#define CRYPTO_ECC_X2_12_POINTX2_Msk (0xfffffffful << CRYPTO_ECC_X2_12_POINTX2_Pos) /*!< CRYPTO_T::ECC_X2_12: POINTX2 Mask */ + +#define CRYPTO_ECC_X2_13_POINTX2_Pos (0) /*!< CRYPTO_T::ECC_X2_13: POINTX2 Position */ +#define CRYPTO_ECC_X2_13_POINTX2_Msk (0xfffffffful << CRYPTO_ECC_X2_13_POINTX2_Pos) /*!< CRYPTO_T::ECC_X2_13: POINTX2 Mask */ + +#define CRYPTO_ECC_X2_14_POINTX2_Pos (0) /*!< CRYPTO_T::ECC_X2_14: POINTX2 Position */ +#define CRYPTO_ECC_X2_14_POINTX2_Msk (0xfffffffful << CRYPTO_ECC_X2_14_POINTX2_Pos) /*!< CRYPTO_T::ECC_X2_14: POINTX2 Mask */ + +#define CRYPTO_ECC_X2_15_POINTX2_Pos (0) /*!< CRYPTO_T::ECC_X2_15: POINTX2 Position */ +#define CRYPTO_ECC_X2_15_POINTX2_Msk (0xfffffffful << CRYPTO_ECC_X2_15_POINTX2_Pos) /*!< CRYPTO_T::ECC_X2_15: POINTX2 Mask */ + +#define CRYPTO_ECC_X2_16_POINTX2_Pos (0) /*!< CRYPTO_T::ECC_X2_16: POINTX2 Position */ +#define CRYPTO_ECC_X2_16_POINTX2_Msk (0xfffffffful << CRYPTO_ECC_X2_16_POINTX2_Pos) /*!< CRYPTO_T::ECC_X2_16: POINTX2 Mask */ + +#define CRYPTO_ECC_X2_17_POINTX2_Pos (0) /*!< CRYPTO_T::ECC_X2_17: POINTX2 Position */ +#define CRYPTO_ECC_X2_17_POINTX2_Msk (0xfffffffful << CRYPTO_ECC_X2_17_POINTX2_Pos) /*!< CRYPTO_T::ECC_X2_17: POINTX2 Mask */ + +#define CRYPTO_ECC_Y2_00_POINTY2_Pos (0) /*!< CRYPTO_T::ECC_Y2_00: POINTY2 Position */ +#define CRYPTO_ECC_Y2_00_POINTY2_Msk (0xfffffffful << CRYPTO_ECC_Y2_00_POINTY2_Pos) /*!< CRYPTO_T::ECC_Y2_00: POINTY2 Mask */ + +#define CRYPTO_ECC_Y2_01_POINTY2_Pos (0) /*!< CRYPTO_T::ECC_Y2_01: POINTY2 Position */ +#define CRYPTO_ECC_Y2_01_POINTY2_Msk (0xfffffffful << CRYPTO_ECC_Y2_01_POINTY2_Pos) /*!< CRYPTO_T::ECC_Y2_01: POINTY2 Mask */ + +#define CRYPTO_ECC_Y2_02_POINTY2_Pos (0) /*!< CRYPTO_T::ECC_Y2_02: POINTY2 Position */ +#define CRYPTO_ECC_Y2_02_POINTY2_Msk (0xfffffffful << CRYPTO_ECC_Y2_02_POINTY2_Pos) /*!< CRYPTO_T::ECC_Y2_02: POINTY2 Mask */ + +#define CRYPTO_ECC_Y2_03_POINTY2_Pos (0) /*!< CRYPTO_T::ECC_Y2_03: POINTY2 Position */ +#define CRYPTO_ECC_Y2_03_POINTY2_Msk (0xfffffffful << CRYPTO_ECC_Y2_03_POINTY2_Pos) /*!< CRYPTO_T::ECC_Y2_03: POINTY2 Mask */ + +#define CRYPTO_ECC_Y2_04_POINTY2_Pos (0) /*!< CRYPTO_T::ECC_Y2_04: POINTY2 Position */ +#define CRYPTO_ECC_Y2_04_POINTY2_Msk (0xfffffffful << CRYPTO_ECC_Y2_04_POINTY2_Pos) /*!< CRYPTO_T::ECC_Y2_04: POINTY2 Mask */ + +#define CRYPTO_ECC_Y2_05_POINTY2_Pos (0) /*!< CRYPTO_T::ECC_Y2_05: POINTY2 Position */ +#define CRYPTO_ECC_Y2_05_POINTY2_Msk (0xfffffffful << CRYPTO_ECC_Y2_05_POINTY2_Pos) /*!< CRYPTO_T::ECC_Y2_05: POINTY2 Mask */ + +#define CRYPTO_ECC_Y2_06_POINTY2_Pos (0) /*!< CRYPTO_T::ECC_Y2_06: POINTY2 Position */ +#define CRYPTO_ECC_Y2_06_POINTY2_Msk (0xfffffffful << CRYPTO_ECC_Y2_06_POINTY2_Pos) /*!< CRYPTO_T::ECC_Y2_06: POINTY2 Mask */ + +#define CRYPTO_ECC_Y2_07_POINTY2_Pos (0) /*!< CRYPTO_T::ECC_Y2_07: POINTY2 Position */ +#define CRYPTO_ECC_Y2_07_POINTY2_Msk (0xfffffffful << CRYPTO_ECC_Y2_07_POINTY2_Pos) /*!< CRYPTO_T::ECC_Y2_07: POINTY2 Mask */ + +#define CRYPTO_ECC_Y2_08_POINTY2_Pos (0) /*!< CRYPTO_T::ECC_Y2_08: POINTY2 Position */ +#define CRYPTO_ECC_Y2_08_POINTY2_Msk (0xfffffffful << CRYPTO_ECC_Y2_08_POINTY2_Pos) /*!< CRYPTO_T::ECC_Y2_08: POINTY2 Mask */ + +#define CRYPTO_ECC_Y2_09_POINTY2_Pos (0) /*!< CRYPTO_T::ECC_Y2_09: POINTY2 Position */ +#define CRYPTO_ECC_Y2_09_POINTY2_Msk (0xfffffffful << CRYPTO_ECC_Y2_09_POINTY2_Pos) /*!< CRYPTO_T::ECC_Y2_09: POINTY2 Mask */ + +#define CRYPTO_ECC_Y2_10_POINTY2_Pos (0) /*!< CRYPTO_T::ECC_Y2_10: POINTY2 Position */ +#define CRYPTO_ECC_Y2_10_POINTY2_Msk (0xfffffffful << CRYPTO_ECC_Y2_10_POINTY2_Pos) /*!< CRYPTO_T::ECC_Y2_10: POINTY2 Mask */ + +#define CRYPTO_ECC_Y2_11_POINTY2_Pos (0) /*!< CRYPTO_T::ECC_Y2_11: POINTY2 Position */ +#define CRYPTO_ECC_Y2_11_POINTY2_Msk (0xfffffffful << CRYPTO_ECC_Y2_11_POINTY2_Pos) /*!< CRYPTO_T::ECC_Y2_11: POINTY2 Mask */ + +#define CRYPTO_ECC_Y2_12_POINTY2_Pos (0) /*!< CRYPTO_T::ECC_Y2_12: POINTY2 Position */ +#define CRYPTO_ECC_Y2_12_POINTY2_Msk (0xfffffffful << CRYPTO_ECC_Y2_12_POINTY2_Pos) /*!< CRYPTO_T::ECC_Y2_12: POINTY2 Mask */ + +#define CRYPTO_ECC_Y2_13_POINTY2_Pos (0) /*!< CRYPTO_T::ECC_Y2_13: POINTY2 Position */ +#define CRYPTO_ECC_Y2_13_POINTY2_Msk (0xfffffffful << CRYPTO_ECC_Y2_13_POINTY2_Pos) /*!< CRYPTO_T::ECC_Y2_13: POINTY2 Mask */ + +#define CRYPTO_ECC_Y2_14_POINTY2_Pos (0) /*!< CRYPTO_T::ECC_Y2_14: POINTY2 Position */ +#define CRYPTO_ECC_Y2_14_POINTY2_Msk (0xfffffffful << CRYPTO_ECC_Y2_14_POINTY2_Pos) /*!< CRYPTO_T::ECC_Y2_14: POINTY2 Mask */ + +#define CRYPTO_ECC_Y2_15_POINTY2_Pos (0) /*!< CRYPTO_T::ECC_Y2_15: POINTY2 Position */ +#define CRYPTO_ECC_Y2_15_POINTY2_Msk (0xfffffffful << CRYPTO_ECC_Y2_15_POINTY2_Pos) /*!< CRYPTO_T::ECC_Y2_15: POINTY2 Mask */ + +#define CRYPTO_ECC_Y2_16_POINTY2_Pos (0) /*!< CRYPTO_T::ECC_Y2_16: POINTY2 Position */ +#define CRYPTO_ECC_Y2_16_POINTY2_Msk (0xfffffffful << CRYPTO_ECC_Y2_16_POINTY2_Pos) /*!< CRYPTO_T::ECC_Y2_16: POINTY2 Mask */ + +#define CRYPTO_ECC_Y2_17_POINTY2_Pos (0) /*!< CRYPTO_T::ECC_Y2_17: POINTY2 Position */ +#define CRYPTO_ECC_Y2_17_POINTY2_Msk (0xfffffffful << CRYPTO_ECC_Y2_17_POINTY2_Pos) /*!< CRYPTO_T::ECC_Y2_17: POINTY2 Mask */ + +#define CRYPTO_ECC_A_00_CURVEA_Pos (0) /*!< CRYPTO_T::ECC_A_00: CURVEA Position */ +#define CRYPTO_ECC_A_00_CURVEA_Msk (0xfffffffful << CRYPTO_ECC_A_00_CURVEA_Pos) /*!< CRYPTO_T::ECC_A_00: CURVEA Mask */ + +#define CRYPTO_ECC_A_01_CURVEA_Pos (0) /*!< CRYPTO_T::ECC_A_01: CURVEA Position */ +#define CRYPTO_ECC_A_01_CURVEA_Msk (0xfffffffful << CRYPTO_ECC_A_01_CURVEA_Pos) /*!< CRYPTO_T::ECC_A_01: CURVEA Mask */ + +#define CRYPTO_ECC_A_02_CURVEA_Pos (0) /*!< CRYPTO_T::ECC_A_02: CURVEA Position */ +#define CRYPTO_ECC_A_02_CURVEA_Msk (0xfffffffful << CRYPTO_ECC_A_02_CURVEA_Pos) /*!< CRYPTO_T::ECC_A_02: CURVEA Mask */ + +#define CRYPTO_ECC_A_03_CURVEA_Pos (0) /*!< CRYPTO_T::ECC_A_03: CURVEA Position */ +#define CRYPTO_ECC_A_03_CURVEA_Msk (0xfffffffful << CRYPTO_ECC_A_03_CURVEA_Pos) /*!< CRYPTO_T::ECC_A_03: CURVEA Mask */ + +#define CRYPTO_ECC_A_04_CURVEA_Pos (0) /*!< CRYPTO_T::ECC_A_04: CURVEA Position */ +#define CRYPTO_ECC_A_04_CURVEA_Msk (0xfffffffful << CRYPTO_ECC_A_04_CURVEA_Pos) /*!< CRYPTO_T::ECC_A_04: CURVEA Mask */ + +#define CRYPTO_ECC_A_05_CURVEA_Pos (0) /*!< CRYPTO_T::ECC_A_05: CURVEA Position */ +#define CRYPTO_ECC_A_05_CURVEA_Msk (0xfffffffful << CRYPTO_ECC_A_05_CURVEA_Pos) /*!< CRYPTO_T::ECC_A_05: CURVEA Mask */ + +#define CRYPTO_ECC_A_06_CURVEA_Pos (0) /*!< CRYPTO_T::ECC_A_06: CURVEA Position */ +#define CRYPTO_ECC_A_06_CURVEA_Msk (0xfffffffful << CRYPTO_ECC_A_06_CURVEA_Pos) /*!< CRYPTO_T::ECC_A_06: CURVEA Mask */ + +#define CRYPTO_ECC_A_07_CURVEA_Pos (0) /*!< CRYPTO_T::ECC_A_07: CURVEA Position */ +#define CRYPTO_ECC_A_07_CURVEA_Msk (0xfffffffful << CRYPTO_ECC_A_07_CURVEA_Pos) /*!< CRYPTO_T::ECC_A_07: CURVEA Mask */ + +#define CRYPTO_ECC_A_08_CURVEA_Pos (0) /*!< CRYPTO_T::ECC_A_08: CURVEA Position */ +#define CRYPTO_ECC_A_08_CURVEA_Msk (0xfffffffful << CRYPTO_ECC_A_08_CURVEA_Pos) /*!< CRYPTO_T::ECC_A_08: CURVEA Mask */ + +#define CRYPTO_ECC_A_09_CURVEA_Pos (0) /*!< CRYPTO_T::ECC_A_09: CURVEA Position */ +#define CRYPTO_ECC_A_09_CURVEA_Msk (0xfffffffful << CRYPTO_ECC_A_09_CURVEA_Pos) /*!< CRYPTO_T::ECC_A_09: CURVEA Mask */ + +#define CRYPTO_ECC_A_10_CURVEA_Pos (0) /*!< CRYPTO_T::ECC_A_10: CURVEA Position */ +#define CRYPTO_ECC_A_10_CURVEA_Msk (0xfffffffful << CRYPTO_ECC_A_10_CURVEA_Pos) /*!< CRYPTO_T::ECC_A_10: CURVEA Mask */ + +#define CRYPTO_ECC_A_11_CURVEA_Pos (0) /*!< CRYPTO_T::ECC_A_11: CURVEA Position */ +#define CRYPTO_ECC_A_11_CURVEA_Msk (0xfffffffful << CRYPTO_ECC_A_11_CURVEA_Pos) /*!< CRYPTO_T::ECC_A_11: CURVEA Mask */ + +#define CRYPTO_ECC_A_12_CURVEA_Pos (0) /*!< CRYPTO_T::ECC_A_12: CURVEA Position */ +#define CRYPTO_ECC_A_12_CURVEA_Msk (0xfffffffful << CRYPTO_ECC_A_12_CURVEA_Pos) /*!< CRYPTO_T::ECC_A_12: CURVEA Mask */ + +#define CRYPTO_ECC_A_13_CURVEA_Pos (0) /*!< CRYPTO_T::ECC_A_13: CURVEA Position */ +#define CRYPTO_ECC_A_13_CURVEA_Msk (0xfffffffful << CRYPTO_ECC_A_13_CURVEA_Pos) /*!< CRYPTO_T::ECC_A_13: CURVEA Mask */ + +#define CRYPTO_ECC_A_14_CURVEA_Pos (0) /*!< CRYPTO_T::ECC_A_14: CURVEA Position */ +#define CRYPTO_ECC_A_14_CURVEA_Msk (0xfffffffful << CRYPTO_ECC_A_14_CURVEA_Pos) /*!< CRYPTO_T::ECC_A_14: CURVEA Mask */ + +#define CRYPTO_ECC_A_15_CURVEA_Pos (0) /*!< CRYPTO_T::ECC_A_15: CURVEA Position */ +#define CRYPTO_ECC_A_15_CURVEA_Msk (0xfffffffful << CRYPTO_ECC_A_15_CURVEA_Pos) /*!< CRYPTO_T::ECC_A_15: CURVEA Mask */ + +#define CRYPTO_ECC_A_16_CURVEA_Pos (0) /*!< CRYPTO_T::ECC_A_16: CURVEA Position */ +#define CRYPTO_ECC_A_16_CURVEA_Msk (0xfffffffful << CRYPTO_ECC_A_16_CURVEA_Pos) /*!< CRYPTO_T::ECC_A_16: CURVEA Mask */ + +#define CRYPTO_ECC_A_17_CURVEA_Pos (0) /*!< CRYPTO_T::ECC_A_17: CURVEA Position */ +#define CRYPTO_ECC_A_17_CURVEA_Msk (0xfffffffful << CRYPTO_ECC_A_17_CURVEA_Pos) /*!< CRYPTO_T::ECC_A_17: CURVEA Mask */ + +#define CRYPTO_ECC_B_00_CURVEB_Pos (0) /*!< CRYPTO_T::ECC_B_00: CURVEB Position */ +#define CRYPTO_ECC_B_00_CURVEB_Msk (0xfffffffful << CRYPTO_ECC_B_00_CURVEB_Pos) /*!< CRYPTO_T::ECC_B_00: CURVEB Mask */ + +#define CRYPTO_ECC_B_01_CURVEB_Pos (0) /*!< CRYPTO_T::ECC_B_01: CURVEB Position */ +#define CRYPTO_ECC_B_01_CURVEB_Msk (0xfffffffful << CRYPTO_ECC_B_01_CURVEB_Pos) /*!< CRYPTO_T::ECC_B_01: CURVEB Mask */ + +#define CRYPTO_ECC_B_02_CURVEB_Pos (0) /*!< CRYPTO_T::ECC_B_02: CURVEB Position */ +#define CRYPTO_ECC_B_02_CURVEB_Msk (0xfffffffful << CRYPTO_ECC_B_02_CURVEB_Pos) /*!< CRYPTO_T::ECC_B_02: CURVEB Mask */ + +#define CRYPTO_ECC_B_03_CURVEB_Pos (0) /*!< CRYPTO_T::ECC_B_03: CURVEB Position */ +#define CRYPTO_ECC_B_03_CURVEB_Msk (0xfffffffful << CRYPTO_ECC_B_03_CURVEB_Pos) /*!< CRYPTO_T::ECC_B_03: CURVEB Mask */ + +#define CRYPTO_ECC_B_04_CURVEB_Pos (0) /*!< CRYPTO_T::ECC_B_04: CURVEB Position */ +#define CRYPTO_ECC_B_04_CURVEB_Msk (0xfffffffful << CRYPTO_ECC_B_04_CURVEB_Pos) /*!< CRYPTO_T::ECC_B_04: CURVEB Mask */ + +#define CRYPTO_ECC_B_05_CURVEB_Pos (0) /*!< CRYPTO_T::ECC_B_05: CURVEB Position */ +#define CRYPTO_ECC_B_05_CURVEB_Msk (0xfffffffful << CRYPTO_ECC_B_05_CURVEB_Pos) /*!< CRYPTO_T::ECC_B_05: CURVEB Mask */ + +#define CRYPTO_ECC_B_06_CURVEB_Pos (0) /*!< CRYPTO_T::ECC_B_06: CURVEB Position */ +#define CRYPTO_ECC_B_06_CURVEB_Msk (0xfffffffful << CRYPTO_ECC_B_06_CURVEB_Pos) /*!< CRYPTO_T::ECC_B_06: CURVEB Mask */ + +#define CRYPTO_ECC_B_07_CURVEB_Pos (0) /*!< CRYPTO_T::ECC_B_07: CURVEB Position */ +#define CRYPTO_ECC_B_07_CURVEB_Msk (0xfffffffful << CRYPTO_ECC_B_07_CURVEB_Pos) /*!< CRYPTO_T::ECC_B_07: CURVEB Mask */ + +#define CRYPTO_ECC_B_08_CURVEB_Pos (0) /*!< CRYPTO_T::ECC_B_08: CURVEB Position */ +#define CRYPTO_ECC_B_08_CURVEB_Msk (0xfffffffful << CRYPTO_ECC_B_08_CURVEB_Pos) /*!< CRYPTO_T::ECC_B_08: CURVEB Mask */ + +#define CRYPTO_ECC_B_09_CURVEB_Pos (0) /*!< CRYPTO_T::ECC_B_09: CURVEB Position */ +#define CRYPTO_ECC_B_09_CURVEB_Msk (0xfffffffful << CRYPTO_ECC_B_09_CURVEB_Pos) /*!< CRYPTO_T::ECC_B_09: CURVEB Mask */ + +#define CRYPTO_ECC_B_10_CURVEB_Pos (0) /*!< CRYPTO_T::ECC_B_10: CURVEB Position */ +#define CRYPTO_ECC_B_10_CURVEB_Msk (0xfffffffful << CRYPTO_ECC_B_10_CURVEB_Pos) /*!< CRYPTO_T::ECC_B_10: CURVEB Mask */ + +#define CRYPTO_ECC_B_11_CURVEB_Pos (0) /*!< CRYPTO_T::ECC_B_11: CURVEB Position */ +#define CRYPTO_ECC_B_11_CURVEB_Msk (0xfffffffful << CRYPTO_ECC_B_11_CURVEB_Pos) /*!< CRYPTO_T::ECC_B_11: CURVEB Mask */ + +#define CRYPTO_ECC_B_12_CURVEB_Pos (0) /*!< CRYPTO_T::ECC_B_12: CURVEB Position */ +#define CRYPTO_ECC_B_12_CURVEB_Msk (0xfffffffful << CRYPTO_ECC_B_12_CURVEB_Pos) /*!< CRYPTO_T::ECC_B_12: CURVEB Mask */ + +#define CRYPTO_ECC_B_13_CURVEB_Pos (0) /*!< CRYPTO_T::ECC_B_13: CURVEB Position */ +#define CRYPTO_ECC_B_13_CURVEB_Msk (0xfffffffful << CRYPTO_ECC_B_13_CURVEB_Pos) /*!< CRYPTO_T::ECC_B_13: CURVEB Mask */ + +#define CRYPTO_ECC_B_14_CURVEB_Pos (0) /*!< CRYPTO_T::ECC_B_14: CURVEB Position */ +#define CRYPTO_ECC_B_14_CURVEB_Msk (0xfffffffful << CRYPTO_ECC_B_14_CURVEB_Pos) /*!< CRYPTO_T::ECC_B_14: CURVEB Mask */ + +#define CRYPTO_ECC_B_15_CURVEB_Pos (0) /*!< CRYPTO_T::ECC_B_15: CURVEB Position */ +#define CRYPTO_ECC_B_15_CURVEB_Msk (0xfffffffful << CRYPTO_ECC_B_15_CURVEB_Pos) /*!< CRYPTO_T::ECC_B_15: CURVEB Mask */ + +#define CRYPTO_ECC_B_16_CURVEB_Pos (0) /*!< CRYPTO_T::ECC_B_16: CURVEB Position */ +#define CRYPTO_ECC_B_16_CURVEB_Msk (0xfffffffful << CRYPTO_ECC_B_16_CURVEB_Pos) /*!< CRYPTO_T::ECC_B_16: CURVEB Mask */ + +#define CRYPTO_ECC_B_17_CURVEB_Pos (0) /*!< CRYPTO_T::ECC_B_17: CURVEB Position */ +#define CRYPTO_ECC_B_17_CURVEB_Msk (0xfffffffful << CRYPTO_ECC_B_17_CURVEB_Pos) /*!< CRYPTO_T::ECC_B_17: CURVEB Mask */ + +#define CRYPTO_ECC_N_00_CURVEN_Pos (0) /*!< CRYPTO_T::ECC_N_00: CURVEN Position */ +#define CRYPTO_ECC_N_00_CURVEN_Msk (0xfffffffful << CRYPTO_ECC_N_00_CURVEN_Pos) /*!< CRYPTO_T::ECC_N_00: CURVEN Mask */ + +#define CRYPTO_ECC_N_01_CURVEN_Pos (0) /*!< CRYPTO_T::ECC_N_01: CURVEN Position */ +#define CRYPTO_ECC_N_01_CURVEN_Msk (0xfffffffful << CRYPTO_ECC_N_01_CURVEN_Pos) /*!< CRYPTO_T::ECC_N_01: CURVEN Mask */ + +#define CRYPTO_ECC_N_02_CURVEN_Pos (0) /*!< CRYPTO_T::ECC_N_02: CURVEN Position */ +#define CRYPTO_ECC_N_02_CURVEN_Msk (0xfffffffful << CRYPTO_ECC_N_02_CURVEN_Pos) /*!< CRYPTO_T::ECC_N_02: CURVEN Mask */ + +#define CRYPTO_ECC_N_03_CURVEN_Pos (0) /*!< CRYPTO_T::ECC_N_03: CURVEN Position */ +#define CRYPTO_ECC_N_03_CURVEN_Msk (0xfffffffful << CRYPTO_ECC_N_03_CURVEN_Pos) /*!< CRYPTO_T::ECC_N_03: CURVEN Mask */ + +#define CRYPTO_ECC_N_04_CURVEN_Pos (0) /*!< CRYPTO_T::ECC_N_04: CURVEN Position */ +#define CRYPTO_ECC_N_04_CURVEN_Msk (0xfffffffful << CRYPTO_ECC_N_04_CURVEN_Pos) /*!< CRYPTO_T::ECC_N_04: CURVEN Mask */ + +#define CRYPTO_ECC_N_05_CURVEN_Pos (0) /*!< CRYPTO_T::ECC_N_05: CURVEN Position */ +#define CRYPTO_ECC_N_05_CURVEN_Msk (0xfffffffful << CRYPTO_ECC_N_05_CURVEN_Pos) /*!< CRYPTO_T::ECC_N_05: CURVEN Mask */ + +#define CRYPTO_ECC_N_06_CURVEN_Pos (0) /*!< CRYPTO_T::ECC_N_06: CURVEN Position */ +#define CRYPTO_ECC_N_06_CURVEN_Msk (0xfffffffful << CRYPTO_ECC_N_06_CURVEN_Pos) /*!< CRYPTO_T::ECC_N_06: CURVEN Mask */ + +#define CRYPTO_ECC_N_07_CURVEN_Pos (0) /*!< CRYPTO_T::ECC_N_07: CURVEN Position */ +#define CRYPTO_ECC_N_07_CURVEN_Msk (0xfffffffful << CRYPTO_ECC_N_07_CURVEN_Pos) /*!< CRYPTO_T::ECC_N_07: CURVEN Mask */ + +#define CRYPTO_ECC_N_08_CURVEN_Pos (0) /*!< CRYPTO_T::ECC_N_08: CURVEN Position */ +#define CRYPTO_ECC_N_08_CURVEN_Msk (0xfffffffful << CRYPTO_ECC_N_08_CURVEN_Pos) /*!< CRYPTO_T::ECC_N_08: CURVEN Mask */ + +#define CRYPTO_ECC_N_09_CURVEN_Pos (0) /*!< CRYPTO_T::ECC_N_09: CURVEN Position */ +#define CRYPTO_ECC_N_09_CURVEN_Msk (0xfffffffful << CRYPTO_ECC_N_09_CURVEN_Pos) /*!< CRYPTO_T::ECC_N_09: CURVEN Mask */ + +#define CRYPTO_ECC_N_10_CURVEN_Pos (0) /*!< CRYPTO_T::ECC_N_10: CURVEN Position */ +#define CRYPTO_ECC_N_10_CURVEN_Msk (0xfffffffful << CRYPTO_ECC_N_10_CURVEN_Pos) /*!< CRYPTO_T::ECC_N_10: CURVEN Mask */ + +#define CRYPTO_ECC_N_11_CURVEN_Pos (0) /*!< CRYPTO_T::ECC_N_11: CURVEN Position */ +#define CRYPTO_ECC_N_11_CURVEN_Msk (0xfffffffful << CRYPTO_ECC_N_11_CURVEN_Pos) /*!< CRYPTO_T::ECC_N_11: CURVEN Mask */ + +#define CRYPTO_ECC_N_12_CURVEN_Pos (0) /*!< CRYPTO_T::ECC_N_12: CURVEN Position */ +#define CRYPTO_ECC_N_12_CURVEN_Msk (0xfffffffful << CRYPTO_ECC_N_12_CURVEN_Pos) /*!< CRYPTO_T::ECC_N_12: CURVEN Mask */ + +#define CRYPTO_ECC_N_13_CURVEN_Pos (0) /*!< CRYPTO_T::ECC_N_13: CURVEN Position */ +#define CRYPTO_ECC_N_13_CURVEN_Msk (0xfffffffful << CRYPTO_ECC_N_13_CURVEN_Pos) /*!< CRYPTO_T::ECC_N_13: CURVEN Mask */ + +#define CRYPTO_ECC_N_14_CURVEN_Pos (0) /*!< CRYPTO_T::ECC_N_14: CURVEN Position */ +#define CRYPTO_ECC_N_14_CURVEN_Msk (0xfffffffful << CRYPTO_ECC_N_14_CURVEN_Pos) /*!< CRYPTO_T::ECC_N_14: CURVEN Mask */ + +#define CRYPTO_ECC_N_15_CURVEN_Pos (0) /*!< CRYPTO_T::ECC_N_15: CURVEN Position */ +#define CRYPTO_ECC_N_15_CURVEN_Msk (0xfffffffful << CRYPTO_ECC_N_15_CURVEN_Pos) /*!< CRYPTO_T::ECC_N_15: CURVEN Mask */ + +#define CRYPTO_ECC_N_16_CURVEN_Pos (0) /*!< CRYPTO_T::ECC_N_16: CURVEN Position */ +#define CRYPTO_ECC_N_16_CURVEN_Msk (0xfffffffful << CRYPTO_ECC_N_16_CURVEN_Pos) /*!< CRYPTO_T::ECC_N_16: CURVEN Mask */ + +#define CRYPTO_ECC_N_17_CURVEN_Pos (0) /*!< CRYPTO_T::ECC_N_17: CURVEN Position */ +#define CRYPTO_ECC_N_17_CURVEN_Msk (0xfffffffful << CRYPTO_ECC_N_17_CURVEN_Pos) /*!< CRYPTO_T::ECC_N_17: CURVEN Mask */ + +#define CRYPTO_ECC_K_00_SCALARK_Pos (0) /*!< CRYPTO_T::ECC_K_00: SCALARK Position */ +#define CRYPTO_ECC_K_00_SCALARK_Msk (0xfffffffful << CRYPTO_ECC_K_00_SCALARK_Pos) /*!< CRYPTO_T::ECC_K_00: SCALARK Mask */ + +#define CRYPTO_ECC_K_01_SCALARK_Pos (0) /*!< CRYPTO_T::ECC_K_01: SCALARK Position */ +#define CRYPTO_ECC_K_01_SCALARK_Msk (0xfffffffful << CRYPTO_ECC_K_01_SCALARK_Pos) /*!< CRYPTO_T::ECC_K_01: SCALARK Mask */ + +#define CRYPTO_ECC_K_02_SCALARK_Pos (0) /*!< CRYPTO_T::ECC_K_02: SCALARK Position */ +#define CRYPTO_ECC_K_02_SCALARK_Msk (0xfffffffful << CRYPTO_ECC_K_02_SCALARK_Pos) /*!< CRYPTO_T::ECC_K_02: SCALARK Mask */ + +#define CRYPTO_ECC_K_03_SCALARK_Pos (0) /*!< CRYPTO_T::ECC_K_03: SCALARK Position */ +#define CRYPTO_ECC_K_03_SCALARK_Msk (0xfffffffful << CRYPTO_ECC_K_03_SCALARK_Pos) /*!< CRYPTO_T::ECC_K_03: SCALARK Mask */ + +#define CRYPTO_ECC_K_04_SCALARK_Pos (0) /*!< CRYPTO_T::ECC_K_04: SCALARK Position */ +#define CRYPTO_ECC_K_04_SCALARK_Msk (0xfffffffful << CRYPTO_ECC_K_04_SCALARK_Pos) /*!< CRYPTO_T::ECC_K_04: SCALARK Mask */ + +#define CRYPTO_ECC_K_05_SCALARK_Pos (0) /*!< CRYPTO_T::ECC_K_05: SCALARK Position */ +#define CRYPTO_ECC_K_05_SCALARK_Msk (0xfffffffful << CRYPTO_ECC_K_05_SCALARK_Pos) /*!< CRYPTO_T::ECC_K_05: SCALARK Mask */ + +#define CRYPTO_ECC_K_06_SCALARK_Pos (0) /*!< CRYPTO_T::ECC_K_06: SCALARK Position */ +#define CRYPTO_ECC_K_06_SCALARK_Msk (0xfffffffful << CRYPTO_ECC_K_06_SCALARK_Pos) /*!< CRYPTO_T::ECC_K_06: SCALARK Mask */ + +#define CRYPTO_ECC_K_07_SCALARK_Pos (0) /*!< CRYPTO_T::ECC_K_07: SCALARK Position */ +#define CRYPTO_ECC_K_07_SCALARK_Msk (0xfffffffful << CRYPTO_ECC_K_07_SCALARK_Pos) /*!< CRYPTO_T::ECC_K_07: SCALARK Mask */ + +#define CRYPTO_ECC_K_08_SCALARK_Pos (0) /*!< CRYPTO_T::ECC_K_08: SCALARK Position */ +#define CRYPTO_ECC_K_08_SCALARK_Msk (0xfffffffful << CRYPTO_ECC_K_08_SCALARK_Pos) /*!< CRYPTO_T::ECC_K_08: SCALARK Mask */ + +#define CRYPTO_ECC_K_09_SCALARK_Pos (0) /*!< CRYPTO_T::ECC_K_09: SCALARK Position */ +#define CRYPTO_ECC_K_09_SCALARK_Msk (0xfffffffful << CRYPTO_ECC_K_09_SCALARK_Pos) /*!< CRYPTO_T::ECC_K_09: SCALARK Mask */ + +#define CRYPTO_ECC_K_10_SCALARK_Pos (0) /*!< CRYPTO_T::ECC_K_10: SCALARK Position */ +#define CRYPTO_ECC_K_10_SCALARK_Msk (0xfffffffful << CRYPTO_ECC_K_10_SCALARK_Pos) /*!< CRYPTO_T::ECC_K_10: SCALARK Mask */ + +#define CRYPTO_ECC_K_11_SCALARK_Pos (0) /*!< CRYPTO_T::ECC_K_11: SCALARK Position */ +#define CRYPTO_ECC_K_11_SCALARK_Msk (0xfffffffful << CRYPTO_ECC_K_11_SCALARK_Pos) /*!< CRYPTO_T::ECC_K_11: SCALARK Mask */ + +#define CRYPTO_ECC_K_12_SCALARK_Pos (0) /*!< CRYPTO_T::ECC_K_12: SCALARK Position */ +#define CRYPTO_ECC_K_12_SCALARK_Msk (0xfffffffful << CRYPTO_ECC_K_12_SCALARK_Pos) /*!< CRYPTO_T::ECC_K_12: SCALARK Mask */ + +#define CRYPTO_ECC_K_13_SCALARK_Pos (0) /*!< CRYPTO_T::ECC_K_13: SCALARK Position */ +#define CRYPTO_ECC_K_13_SCALARK_Msk (0xfffffffful << CRYPTO_ECC_K_13_SCALARK_Pos) /*!< CRYPTO_T::ECC_K_13: SCALARK Mask */ + +#define CRYPTO_ECC_K_14_SCALARK_Pos (0) /*!< CRYPTO_T::ECC_K_14: SCALARK Position */ +#define CRYPTO_ECC_K_14_SCALARK_Msk (0xfffffffful << CRYPTO_ECC_K_14_SCALARK_Pos) /*!< CRYPTO_T::ECC_K_14: SCALARK Mask */ + +#define CRYPTO_ECC_K_15_SCALARK_Pos (0) /*!< CRYPTO_T::ECC_K_15: SCALARK Position */ +#define CRYPTO_ECC_K_15_SCALARK_Msk (0xfffffffful << CRYPTO_ECC_K_15_SCALARK_Pos) /*!< CRYPTO_T::ECC_K_15: SCALARK Mask */ + +#define CRYPTO_ECC_K_16_SCALARK_Pos (0) /*!< CRYPTO_T::ECC_K_16: SCALARK Position */ +#define CRYPTO_ECC_K_16_SCALARK_Msk (0xfffffffful << CRYPTO_ECC_K_16_SCALARK_Pos) /*!< CRYPTO_T::ECC_K_16: SCALARK Mask */ + +#define CRYPTO_ECC_K_17_SCALARK_Pos (0) /*!< CRYPTO_T::ECC_K_17: SCALARK Position */ +#define CRYPTO_ECC_K_17_SCALARK_Msk (0xfffffffful << CRYPTO_ECC_K_17_SCALARK_Pos) /*!< CRYPTO_T::ECC_K_17: SCALARK Mask */ + +#define CRYPTO_ECC_DADDR_DADDR_Pos (0) /*!< CRYPTO_T::ECC_DADDR: DADDR Position */ +#define CRYPTO_ECC_DADDR_DADDR_Msk (0xfffffffful << CRYPTO_ECC_DADDR_DADDR_Pos) /*!< CRYPTO_T::ECC_DADDR: DADDR Mask */ + +#define CRYPTO_ECC_STARTREG_STARTREG_Pos (0) /*!< CRYPTO_T::ECC_STARTREG: STARTREG Position*/ +#define CRYPTO_ECC_STARTREG_STARTREG_Msk (0xfffffffful << CRYPTO_ECC_STARTREG_STARTREG_Pos) /*!< CRYPTO_T::ECC_STARTREG: STARTREG Mask */ + +#define CRYPTO_ECC_WORDCNT_WORDCNT_Pos (0) /*!< CRYPTO_T::ECC_WORDCNT: WORDCNT Position*/ +#define CRYPTO_ECC_WORDCNT_WORDCNT_Msk (0xfffffffful << CRYPTO_ECC_WORDCNT_WORDCNT_Pos) /*!< CRYPTO_T::ECC_WORDCNT: WORDCNT Mask */ + +#define CRYPTO_RSA_CTL_START_Pos (0) /*!< CRYPTO_T::RSA_CTL: START Position */ +#define CRYPTO_RSA_CTL_START_Msk (0x1ul << CRYPTO_RSA_CTL_START_Pos) /*!< CRYPTO_T::RSA_CTL: START Mask */ + +#define CRYPTO_RSA_CTL_STOP_Pos (1) /*!< CRYPTO_T::RSA_CTL: STOP Position */ +#define CRYPTO_RSA_CTL_STOP_Msk (0x1ul << CRYPTO_RSA_CTL_STOP_Pos) /*!< CRYPTO_T::RSA_CTL: STOP Mask */ + +#define CRYPTO_RSA_CTL_CRT_Pos (2) /*!< CRYPTO_T::RSA_CTL: CRT Position */ +#define CRYPTO_RSA_CTL_CRT_Msk (0x1ul << CRYPTO_RSA_CTL_CRT_Pos) /*!< CRYPTO_T::RSA_CTL: CRT Mask */ + +#define CRYPTO_RSA_CTL_CRTBYP_Pos (3) /*!< CRYPTO_T::RSA_CTL: CRTBYP Position */ +#define CRYPTO_RSA_CTL_CRTBYP_Msk (0x1ul << CRYPTO_RSA_CTL_CRTBYP_Pos) /*!< CRYPTO_T::RSA_CTL: CRTBYP Mask */ + +#define CRYPTO_RSA_CTL_KEYLENG_Pos (4) /*!< CRYPTO_T::RSA_CTL: KEYLENG Position */ +#define CRYPTO_RSA_CTL_KEYLENG_Msk (0x3ul << CRYPTO_RSA_CTL_KEYLENG_Pos) /*!< CRYPTO_T::RSA_CTL: KEYLENG Mask */ + +#define CRYPTO_RSA_CTL_SCAP_Pos (8) /*!< CRYPTO_T::RSA_CTL: SCAP Position */ +#define CRYPTO_RSA_CTL_SCAP_Msk (0x1ul << CRYPTO_RSA_CTL_SCAP_Pos) /*!< CRYPTO_T::RSA_CTL: SCAP Mask */ + +#define CRYPTO_RSA_STS_BUSY_Pos (0) /*!< CRYPTO_T::RSA_STS: BUSY Position */ +#define CRYPTO_RSA_STS_BUSY_Msk (0x1ul << CRYPTO_RSA_STS_BUSY_Pos) /*!< CRYPTO_T::RSA_STS: BUSY Mask */ + +#define CRYPTO_RSA_STS_DMABUSY_Pos (1) /*!< CRYPTO_T::RSA_STS: DMABUSY Position */ +#define CRYPTO_RSA_STS_DMABUSY_Msk (0x1ul << CRYPTO_RSA_STS_DMABUSY_Pos) /*!< CRYPTO_T::RSA_STS: DMABUSY Mask */ + +#define CRYPTO_RSA_STS_BUSERR_Pos (16) /*!< CRYPTO_T::RSA_STS: BUSERR Position */ +#define CRYPTO_RSA_STS_BUSERR_Msk (0x1ul << CRYPTO_RSA_STS_BUSERR_Pos) /*!< CRYPTO_T::RSA_STS: BUSERR Mask */ + +#define CRYPTO_RSA_STS_CTLERR_Pos (17) /*!< CRYPTO_T::RSA_STS: CTLERR Position */ +#define CRYPTO_RSA_STS_CTLERR_Msk (0x1ul << CRYPTO_RSA_STS_CTLERR_Pos) /*!< CRYPTO_T::RSA_STS: CTLERR Mask */ + +#define CRYPTO_RSA_STS_KSERR_Pos (18) /*!< CRYPTO_T::RSA_STS: KSERR Position */ +#define CRYPTO_RSA_STS_KSERR_Msk (0x1ul << CRYPTO_RSA_STS_KSERR_Pos) /*!< CRYPTO_T::RSA_STS: KSERR Mask */ + +#define CRYPTO_RSA_SADDR0_SADDR0_Pos (0) /*!< CRYPTO_T::RSA_SADDR0: SADDR0 Position */ +#define CRYPTO_RSA_SADDR0_SADDR0_Msk (0xfffffffful << CRYPTO_RSA_SADDR0_SADDR0_Pos) /*!< CRYPTO_T::RSA_SADDR0: SADDR0 Mask */ + +#define CRYPTO_RSA_SADDR1_SADDR1_Pos (0) /*!< CRYPTO_T::RSA_SADDR1: SADDR1 Position */ +#define CRYPTO_RSA_SADDR1_SADDR1_Msk (0xfffffffful << CRYPTO_RSA_SADDR1_SADDR1_Pos) /*!< CRYPTO_T::RSA_SADDR1: SADDR1 Mask */ + +#define CRYPTO_RSA_SADDR2_SADDR2_Pos (0) /*!< CRYPTO_T::RSA_SADDR2: SADDR2 Position */ +#define CRYPTO_RSA_SADDR2_SADDR2_Msk (0xfffffffful << CRYPTO_RSA_SADDR2_SADDR2_Pos) /*!< CRYPTO_T::RSA_SADDR2: SADDR2 Mask */ + +#define CRYPTO_RSA_SADDR3_SADDR3_Pos (0) /*!< CRYPTO_T::RSA_SADDR3: SADDR3 Position */ +#define CRYPTO_RSA_SADDR3_SADDR3_Msk (0xfffffffful << CRYPTO_RSA_SADDR3_SADDR3_Pos) /*!< CRYPTO_T::RSA_SADDR3: SADDR3 Mask */ + +#define CRYPTO_RSA_SADDR4_SADDR4_Pos (0) /*!< CRYPTO_T::RSA_SADDR4: SADDR4 Position */ +#define CRYPTO_RSA_SADDR4_SADDR4_Msk (0xfffffffful << CRYPTO_RSA_SADDR4_SADDR4_Pos) /*!< CRYPTO_T::RSA_SADDR4: SADDR4 Mask */ + +#define CRYPTO_RSA_DADDR_DADDR_Pos (0) /*!< CRYPTO_T::RSA_DADDR: DADDR Position */ +#define CRYPTO_RSA_DADDR_DADDR_Msk (0xfffffffful << CRYPTO_RSA_DADDR_DADDR_Pos) /*!< CRYPTO_T::RSA_DADDR: DADDR Mask */ + +#define CRYPTO_RSA_MADDR0_MADDR0_Pos (0) /*!< CRYPTO_T::RSA_MADDR0: MADDR0 Position */ +#define CRYPTO_RSA_MADDR0_MADDR0_Msk (0xfffffffful << CRYPTO_RSA_MADDR0_MADDR0_Pos) /*!< CRYPTO_T::RSA_MADDR0: MADDR0 Mask */ + +#define CRYPTO_RSA_MADDR1_MADDR1_Pos (0) /*!< CRYPTO_T::RSA_MADDR1: MADDR1 Position */ +#define CRYPTO_RSA_MADDR1_MADDR1_Msk (0xfffffffful << CRYPTO_RSA_MADDR1_MADDR1_Pos) /*!< CRYPTO_T::RSA_MADDR1: MADDR1 Mask */ + +#define CRYPTO_RSA_MADDR2_MADDR2_Pos (0) /*!< CRYPTO_T::RSA_MADDR2: MADDR2 Position */ +#define CRYPTO_RSA_MADDR2_MADDR2_Msk (0xfffffffful << CRYPTO_RSA_MADDR2_MADDR2_Pos) /*!< CRYPTO_T::RSA_MADDR2: MADDR2 Mask */ + +#define CRYPTO_RSA_MADDR3_MADDR3_Pos (0) /*!< CRYPTO_T::RSA_MADDR3: MADDR3 Position */ +#define CRYPTO_RSA_MADDR3_MADDR3_Msk (0xfffffffful << CRYPTO_RSA_MADDR3_MADDR3_Pos) /*!< CRYPTO_T::RSA_MADDR3: MADDR3 Mask */ + +#define CRYPTO_RSA_MADDR4_MADDR4_Pos (0) /*!< CRYPTO_T::RSA_MADDR4: MADDR4 Position */ +#define CRYPTO_RSA_MADDR4_MADDR4_Msk (0xfffffffful << CRYPTO_RSA_MADDR4_MADDR4_Pos) /*!< CRYPTO_T::RSA_MADDR4: MADDR4 Mask */ + +#define CRYPTO_RSA_MADDR5_MADDR5_Pos (0) /*!< CRYPTO_T::RSA_MADDR5: MADDR5 Position */ +#define CRYPTO_RSA_MADDR5_MADDR5_Msk (0xfffffffful << CRYPTO_RSA_MADDR5_MADDR5_Pos) /*!< CRYPTO_T::RSA_MADDR5: MADDR5 Mask */ + +#define CRYPTO_RSA_MADDR6_MADDR6_Pos (0) /*!< CRYPTO_T::RSA_MADDR6: MADDR6 Position */ +#define CRYPTO_RSA_MADDR6_MADDR6_Msk (0xfffffffful << CRYPTO_RSA_MADDR6_MADDR6_Pos) /*!< CRYPTO_T::RSA_MADDR6: MADDR6 Mask */ + +#define CRYPTO_PRNG_KSCTL_NUM_Pos (0) /*!< CRYPTO_T::PRNG_KSCTL: NUM Position */ +#define CRYPTO_PRNG_KSCTL_NUM_Msk (0x1ful << CRYPTO_PRNG_KSCTL_NUM_Pos) /*!< CRYPTO_T::PRNG_KSCTL: NUM Mask */ + +#define CRYPTO_PRNG_KSCTL_KEYSRC_Pos (8) /*!< CRYPTO_T::PRNG_KSCTL: KEYSRC Position */ +#define CRYPTO_PRNG_KSCTL_KEYSRC_Msk (0x1ul << CRYPTO_PRNG_KSCTL_KEYSRC_Pos) /*!< CRYPTO_T::PRNG_KSCTL: KEYSRC Mask */ + +#define CRYPTO_PRNG_KSCTL_TRUST_Pos (16) /*!< CRYPTO_T::PRNG_KSCTL: TRUST Position */ +#define CRYPTO_PRNG_KSCTL_TRUST_Msk (0x1ul << CRYPTO_PRNG_KSCTL_TRUST_Pos) /*!< CRYPTO_T::PRNG_KSCTL: TRUST Mask */ + +#define CRYPTO_PRNG_KSCTL_ECDH_Pos (19) /*!< CRYPTO_T::PRNG_KSCTL: ECDH Position */ +#define CRYPTO_PRNG_KSCTL_ECDH_Msk (0x1ul << CRYPTO_PRNG_KSCTL_ECDH_Pos) /*!< CRYPTO_T::PRNG_KSCTL: ECDH Mask */ + +#define CRYPTO_PRNG_KSCTL_ECDSA_Pos (20) /*!< CRYPTO_T::PRNG_KSCTL: ECDSA Position */ +#define CRYPTO_PRNG_KSCTL_ECDSA_Msk (0x1ul << CRYPTO_PRNG_KSCTL_ECDSA_Pos) /*!< CRYPTO_T::PRNG_KSCTL: ECDSA Mask */ + +#define CRYPTO_PRNG_KSCTL_WDST_Pos (21) /*!< CRYPTO_T::PRNG_KSCTL: WDST Position */ +#define CRYPTO_PRNG_KSCTL_WDST_Msk (0x1ul << CRYPTO_PRNG_KSCTL_WDST_Pos) /*!< CRYPTO_T::PRNG_KSCTL: WDST Mask */ + +#define CRYPTO_PRNG_KSCTL_WSDST_Pos (22) /*!< CRYPTO_T::PRNG_KSCTL: WSDST Position */ +#define CRYPTO_PRNG_KSCTL_WSDST_Msk (0x3ul << CRYPTO_PRNG_KSCTL_WSDST_Pos) /*!< CRYPTO_T::PRNG_KSCTL: WSDST Mask */ + +#define CRYPTO_PRNG_KSCTL_OWNER_Pos (24) /*!< CRYPTO_T::PRNG_KSCTL: OWNER Position */ +#define CRYPTO_PRNG_KSCTL_OWNER_Msk (0x7ul << CRYPTO_PRNG_KSCTL_OWNER_Pos) /*!< CRYPTO_T::PRNG_KSCTL: OWNER Mask */ + +#define CRYPTO_PRNG_KSSTS_NUM_Pos (0) /*!< CRYPTO_T::PRNG_KSSTS: NUM Position */ +#define CRYPTO_PRNG_KSSTS_NUM_Msk (0x1ful << CRYPTO_PRNG_KSSTS_NUM_Pos) /*!< CRYPTO_T::PRNG_KSSTS: NUM Mask */ + +#define CRYPTO_AES_KSCTL_NUM_Pos (0) /*!< CRYPTO_T::AES_KSCTL: NUM Position */ +#define CRYPTO_AES_KSCTL_NUM_Msk (0x1ful << CRYPTO_AES_KSCTL_NUM_Pos) /*!< CRYPTO_T::AES_KSCTL: NUM Mask */ + +#define CRYPTO_AES_KSCTL_RSRC_Pos (5) /*!< CRYPTO_T::AES_KSCTL: RSRC Position */ +#define CRYPTO_AES_KSCTL_RSRC_Msk (0x1ul << CRYPTO_AES_KSCTL_RSRC_Pos) /*!< CRYPTO_T::AES_KSCTL: RSRC Mask */ + +#define CRYPTO_AES_KSCTL_RSSRC_Pos (6) /*!< CRYPTO_T::AES_KSCTL: RSSRC Position */ +#define CRYPTO_AES_KSCTL_RSSRC_Msk (0x3ul << CRYPTO_AES_KSCTL_RSSRC_Pos) /*!< CRYPTO_T::AES_KSCTL: RSSRC Mask */ + +#define CRYPTO_HMAC_KSCTL_NUM_Pos (0) /*!< CRYPTO_T::HMAC_KSCTL: NUM Position */ +#define CRYPTO_HMAC_KSCTL_NUM_Msk (0x1ful << CRYPTO_HMAC_KSCTL_NUM_Pos) /*!< CRYPTO_T::HMAC_KSCTL: NUM Mask */ + +#define CRYPTO_HMAC_KSCTL_RSRC_Pos (5) /*!< CRYPTO_T::HMAC_KSCTL: RSRC Position */ +#define CRYPTO_HMAC_KSCTL_RSRC_Msk (0x1ul << CRYPTO_HMAC_KSCTL_RSRC_Pos) /*!< CRYPTO_T::HMAC_KSCTL: RSRC Mask */ + +#define CRYPTO_HMAC_KSCTL_RSSRC_Pos (6) /*!< CRYPTO_T::HMAC_KSCTL: RSSRC Position */ +#define CRYPTO_HMAC_KSCTL_RSSRC_Msk (0x3ul << CRYPTO_HMAC_KSCTL_RSSRC_Pos) /*!< CRYPTO_T::HMAC_KSCTL: RSSRC Mask */ + +#define CRYPTO_ECC_KSCTL_NUMK_Pos (0) /*!< CRYPTO_T::ECC_KSCTL: NUMK Position */ +#define CRYPTO_ECC_KSCTL_NUMK_Msk (0x1ful << CRYPTO_ECC_KSCTL_NUMK_Pos) /*!< CRYPTO_T::ECC_KSCTL: NUMK Mask */ + +#define CRYPTO_ECC_KSCTL_RSRCK_Pos (5) /*!< CRYPTO_T::ECC_KSCTL: RSRCK Position */ +#define CRYPTO_ECC_KSCTL_RSRCK_Msk (0x1ul << CRYPTO_ECC_KSCTL_RSRCK_Pos) /*!< CRYPTO_T::ECC_KSCTL: RSRCK Mask */ + +#define CRYPTO_ECC_KSCTL_RSSRCK_Pos (6) /*!< CRYPTO_T::ECC_KSCTL: RSSRCK Position */ +#define CRYPTO_ECC_KSCTL_RSSRCK_Msk (0x3ul << CRYPTO_ECC_KSCTL_RSSRCK_Pos) /*!< CRYPTO_T::ECC_KSCTL: RSSRCK Mask */ + +#define CRYPTO_ECC_KSCTL_ECDH_Pos (14) /*!< CRYPTO_T::ECC_KSCTL: ECDH Position */ +#define CRYPTO_ECC_KSCTL_ECDH_Msk (0x1ul << CRYPTO_ECC_KSCTL_ECDH_Pos) /*!< CRYPTO_T::ECC_KSCTL: ECDH Mask */ + +#define CRYPTO_ECC_KSCTL_TRUST_Pos (16) /*!< CRYPTO_T::ECC_KSCTL: TRUST Position */ +#define CRYPTO_ECC_KSCTL_TRUST_Msk (0x1ul << CRYPTO_ECC_KSCTL_TRUST_Pos) /*!< CRYPTO_T::ECC_KSCTL: TRUST Mask */ + +#define CRYPTO_ECC_KSCTL_XY_Pos (20) /*!< CRYPTO_T::ECC_KSCTL: XY Position */ +#define CRYPTO_ECC_KSCTL_XY_Msk (0x1ul << CRYPTO_ECC_KSCTL_XY_Pos) /*!< CRYPTO_T::ECC_KSCTL: XY Mask */ + +#define CRYPTO_ECC_KSCTL_WDST_Pos (21) /*!< CRYPTO_T::ECC_KSCTL: WDST Position */ +#define CRYPTO_ECC_KSCTL_WDST_Msk (0x1ul << CRYPTO_ECC_KSCTL_WDST_Pos) /*!< CRYPTO_T::ECC_KSCTL: WDST Mask */ + +#define CRYPTO_ECC_KSCTL_WSDST_Pos (22) /*!< CRYPTO_T::ECC_KSCTL: WSDST Position */ +#define CRYPTO_ECC_KSCTL_WSDST_Msk (0x3ul << CRYPTO_ECC_KSCTL_WSDST_Pos) /*!< CRYPTO_T::ECC_KSCTL: WSDST Mask */ + +#define CRYPTO_ECC_KSCTL_OWNER_Pos (24) /*!< CRYPTO_T::ECC_KSCTL: OWNER Position */ +#define CRYPTO_ECC_KSCTL_OWNER_Msk (0x7ul << CRYPTO_ECC_KSCTL_OWNER_Pos) /*!< CRYPTO_T::ECC_KSCTL: OWNER Mask */ + +#define CRYPTO_ECC_KSSTS_NUM_Pos (0) /*!< CRYPTO_T::ECC_KSSTS: NUM Position */ +#define CRYPTO_ECC_KSSTS_NUM_Msk (0x1ful << CRYPTO_ECC_KSSTS_NUM_Pos) /*!< CRYPTO_T::ECC_KSSTS: NUM Mask */ + +#define CRYPTO_ECC_KSXY_NUMX_Pos (0) /*!< CRYPTO_T::ECC_KSXY: NUMX Position */ +#define CRYPTO_ECC_KSXY_NUMX_Msk (0x1ful << CRYPTO_ECC_KSXY_NUMX_Pos) /*!< CRYPTO_T::ECC_KSXY: NUMX Mask */ + +#define CRYPTO_ECC_KSXY_RSRCXY_Pos (5) /*!< CRYPTO_T::ECC_KSXY: RSRCXY Position */ +#define CRYPTO_ECC_KSXY_RSRCXY_Msk (0x1ul << CRYPTO_ECC_KSXY_RSRCXY_Pos) /*!< CRYPTO_T::ECC_KSXY: RSRCXY Mask */ + +#define CRYPTO_ECC_KSXY_RSSRCX_Pos (6) /*!< CRYPTO_T::ECC_KSXY: RSSRCX Position */ +#define CRYPTO_ECC_KSXY_RSSRCX_Msk (0x3ul << CRYPTO_ECC_KSXY_RSSRCX_Pos) /*!< CRYPTO_T::ECC_KSXY: RSSRCX Mask */ + +#define CRYPTO_ECC_KSXY_NUMY_Pos (8) /*!< CRYPTO_T::ECC_KSXY: NUMY Position */ +#define CRYPTO_ECC_KSXY_NUMY_Msk (0x1ful << CRYPTO_ECC_KSXY_NUMY_Pos) /*!< CRYPTO_T::ECC_KSXY: NUMY Mask */ + +#define CRYPTO_ECC_KSXY_RSSRCY_Pos (14) /*!< CRYPTO_T::ECC_KSXY: RSSRCY Position */ +#define CRYPTO_ECC_KSXY_RSSRCY_Msk (0x3ul << CRYPTO_ECC_KSXY_RSSRCY_Pos) /*!< CRYPTO_T::ECC_KSXY: RSSRCY Mask */ + +#define CRYPTO_RSA_KSCTL_NUM_Pos (0) /*!< CRYPTO_T::RSA_KSCTL: NUM Position */ +#define CRYPTO_RSA_KSCTL_NUM_Msk (0x1ful << CRYPTO_RSA_KSCTL_NUM_Pos) /*!< CRYPTO_T::RSA_KSCTL: NUM Mask */ + +#define CRYPTO_RSA_KSCTL_RSRC_Pos (5) /*!< CRYPTO_T::RSA_KSCTL: RSRC Position */ +#define CRYPTO_RSA_KSCTL_RSRC_Msk (0x1ul << CRYPTO_RSA_KSCTL_RSRC_Pos) /*!< CRYPTO_T::RSA_KSCTL: RSRC Mask */ + +#define CRYPTO_RSA_KSCTL_RSSRC_Pos (6) /*!< CRYPTO_T::RSA_KSCTL: RSSRC Position */ +#define CRYPTO_RSA_KSCTL_RSSRC_Msk (0x3ul << CRYPTO_RSA_KSCTL_RSSRC_Pos) /*!< CRYPTO_T::RSA_KSCTL: RSSRC Mask */ + +#define CRYPTO_RSA_KSCTL_BKNUM_Pos (8) /*!< CRYPTO_T::RSA_KSCTL: BKNUM Position */ +#define CRYPTO_RSA_KSCTL_BKNUM_Msk (0x1ful << CRYPTO_RSA_KSCTL_BKNUM_Pos) /*!< CRYPTO_T::RSA_KSCTL: BKNUM Mask */ + +#define CRYPTO_RSA_KSSTS0_NUM0_Pos (0) /*!< CRYPTO_T::RSA_KSSTS0: NUM0 Position */ +#define CRYPTO_RSA_KSSTS0_NUM0_Msk (0x1ful << CRYPTO_RSA_KSSTS0_NUM0_Pos) /*!< CRYPTO_T::RSA_KSSTS0: NUM0 Mask */ + +#define CRYPTO_RSA_KSSTS0_NUM1_Pos (8) /*!< CRYPTO_T::RSA_KSSTS0: NUM1 Position */ +#define CRYPTO_RSA_KSSTS0_NUM1_Msk (0x1ful << CRYPTO_RSA_KSSTS0_NUM1_Pos) /*!< CRYPTO_T::RSA_KSSTS0: NUM1 Mask */ + +#define CRYPTO_RSA_KSSTS0_NUM2_Pos (16) /*!< CRYPTO_T::RSA_KSSTS0: NUM2 Position */ +#define CRYPTO_RSA_KSSTS0_NUM2_Msk (0x1ful << CRYPTO_RSA_KSSTS0_NUM2_Pos) /*!< CRYPTO_T::RSA_KSSTS0: NUM2 Mask */ + +#define CRYPTO_RSA_KSSTS0_NUM3_Pos (24) /*!< CRYPTO_T::RSA_KSSTS0: NUM3 Position */ +#define CRYPTO_RSA_KSSTS0_NUM3_Msk (0x1ful << CRYPTO_RSA_KSSTS0_NUM3_Pos) /*!< CRYPTO_T::RSA_KSSTS0: NUM3 Mask */ + +#define CRYPTO_RSA_KSSTS1_NUM4_Pos (0) /*!< CRYPTO_T::RSA_KSSTS1: NUM4 Position */ +#define CRYPTO_RSA_KSSTS1_NUM4_Msk (0x1ful << CRYPTO_RSA_KSSTS1_NUM4_Pos) /*!< CRYPTO_T::RSA_KSSTS1: NUM4 Mask */ + +#define CRYPTO_RSA_KSSTS1_NUM5_Pos (8) /*!< CRYPTO_T::RSA_KSSTS1: NUM5 Position */ +#define CRYPTO_RSA_KSSTS1_NUM5_Msk (0x1ful << CRYPTO_RSA_KSSTS1_NUM5_Pos) /*!< CRYPTO_T::RSA_KSSTS1: NUM5 Mask */ + +#define CRYPTO_RSA_KSSTS1_NUM6_Pos (16) /*!< CRYPTO_T::RSA_KSSTS1: NUM6 Position */ +#define CRYPTO_RSA_KSSTS1_NUM6_Msk (0x1ful << CRYPTO_RSA_KSSTS1_NUM6_Pos) /*!< CRYPTO_T::RSA_KSSTS1: NUM6 Mask */ + +#define CRYPTO_RSA_KSSTS1_NUM7_Pos (24) /*!< CRYPTO_T::RSA_KSSTS1: NUM7 Position */ +#define CRYPTO_RSA_KSSTS1_NUM7_Msk (0x1ful << CRYPTO_RSA_KSSTS1_NUM7_Pos) /*!< CRYPTO_T::RSA_KSSTS1: NUM7 Mask */ + +/**@}*/ /* CRYPTO_CONST */ +/**@}*/ /* end of CRYPTO register group */ +/**@}*/ /* end of REGISTER group */ + +#if defined ( __CC_ARM ) + #pragma no_anon_unions +#endif + +#endif /* __CRYPTO_REG_H__ */ diff --git a/bsp/nuvoton/libraries/ma35/Device/Nuvoton/MA35D1/Include/ddr32phy_reg.h b/bsp/nuvoton/libraries/ma35/Device/Nuvoton/MA35D1/Include/ddr32phy_reg.h new file mode 100644 index 0000000000..d1408a3ba5 --- /dev/null +++ b/bsp/nuvoton/libraries/ma35/Device/Nuvoton/MA35D1/Include/ddr32phy_reg.h @@ -0,0 +1,9569 @@ +/**************************************************************************//** + * @file ddr32phy_reg.h + * @brief DDR32PHY register definition header file + * + * SPDX-License-Identifier: Apache-2.0 + * @copyright (C) 2020 Nuvoton Technology Corp. All rights reserved. + *****************************************************************************/ +#ifndef __DDR32PHY_REG_H__ +#define __DDR32PHY_REG_H__ + +#if defined ( __CC_ARM ) + #pragma anon_unions +#endif +/** @addtogroup REGISTER Control Register + + @{ + +*/ + + +/*---------------------- DDR 3/2 PHY Controller -------------------------*/ +/** + @addtogroup DDR32PHY DDR 3/2 PHY Controller(DDR32PHY) + Memory Mapped Structure for DDRPHY Controller +@{ */ + +typedef struct +{ + + + /** + * @var DDRPHY_T::RIDR + * Offset: 0x00 Revision Identification Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[3:0] |PUBMNR |PUB Minor Revision + * | | |Indicates minor update of the PUB such as bug fixes. Normally no new features are included. + * |[7:4] |PUBMDR |PUB Moderate Revision + * | | |Indicates moderate revision of the PUB such as addition of new features + * | | |Normally the new version is still compatible with previous versions. + * |[11:8] |PUBMJR |PUB Major Revision + * | | |Indicates major revision of the PUB such addition of the features that make the new version not compatible with previous versions. + * |[15:12] |PHYMNR |PHY Minor Revision + * | | |Indicates minor update of the PHY such as bug fixes. Normally no new features are included. + * |[19:16] |PHYMDR |PHY Moderate Revision + * | | |Indicates moderate revision of the PHY such as addition of new features + * | | |Normally the new version is still compatible with previous versions. + * |[23:20] |PHYMJR |PHY Major Revision + * | | |Indicates major revision of the PHY such addition of the features that make the new version not compatible with previous versions. + * |[31:24] |UDRID |User-Defined Revision ID + * | | |General purpose revision identification set by the user. + * @var DDRPHY_T::PIR + * Offset: 0x04 PHY Initialization Register (PIR) + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[0] |INIT |Initialization Trigger + * | | |A write of '1' to this bit triggers the DDR system initialization, including PHY initialization, DRAM initialization, and PHY training + * | | |The exact initialization steps to be executed are specified in bits 1 to 15 of this register + * | | |A bit setting of 1 means the step will be executed as part of the initialization sequence, while a setting of '0' means the step will be bypassed + * | | |The initialization trigger bit is self-clearing. + * |[1] |ZCAL |Impedance Calibration + * | | |Performs PHY impedance calibration + * | | |When set the impedance calibration will be performed in parallel with PHY initialization (PLL initialization + DDL calibration + PHY reset). + * |[4] |PLLINIT |PLL Initialization + * | | |Executes the PLL initialization sequence which includes correct driving of PLL power-down, reset and gear shift pins, and then waiting for the PHY PLLs to lock. + * |[5] |DCAL |Digital Delay Line Calibration + * | | |Performs PHY delay line calibration. + * |[6] |PHYRST |PHY Reset + * | | |Resets the AC and DATX8 modules by asserting the AC/DATX8 reset pin. + * |[7] |DRAMRST |DRAM Reset + * | | |Issues a reset to the DRAM (by driving the DRAM reset pin low) and wait 200us + * | | |This can be triggered in isolation or with the full DRAM initialization (DRAMINIT) + * | | |For the latter case, the reset is issued and 200us is waited before starting the full initialization sequence. + * |[8] |DRAMINIT |DRAM Initialization + * | | |Executes the DRAM initialization sequence. + * |[9] |WL |Write Leveling + * | | |Executes a PUB write leveling routine. + * |[10] |QSGATE |Read DQS Gate Training + * | | |Executes a PUB training routine to determine the optimum position of the read data DQS strobe for maximum system timing margins. + * |[11] |WLADJ |Write Leveling Adjust + * | | |Executes a PUB training routine that re- adjusts the write latency used during write in case the write leveling routine changed the expected latency. + * | | |Note: Ensure that the DCU command cache is cleared prior to running WLADJ. + * |[12] |RDDSKW |Read Data Bit Deskew + * | | |Executes a PUB training routine to deskew the DQ bits during read. + * |[13] |WRDSKW |Write Data Bit Deskew + * | | |Executes a PUB training routine to deskew the DQ bits during write. + * |[14] |RDEYE |Read Data Eye Training + * | | |Executes a PUB training routine to maximize the read data eye. + * |[15] |WREYE |Write Data Eye Training + * | | |Executes a PUB training routine to maximize the write data eye. + * |[16] |ICPC |Initialization Complete Pin Configuration + * | | |Specifies how the DFI initialization complete output pin (dfi_init_complete) should be used to indicate the status of initialization + * | | |Valid values are: + * | | |0 = Asserted after PHY initialization (DLL locking and impedance calibration) is complete. + * | | |1 = Asserted after PHY initialization is complete and the triggered the PUB initialization (DRAM initialization, data training, or initialization trigger with no selected initialization) is complete. + * |[17] |PLLBYP |PLL Bypass + * | | |A setting of 1 on this bit will put all PHY PLLs in bypass mode. + * |[18] |CTLDINIT |Controller DRAM Initialization + * | | |Indicates, if set, that DRAM initialization will be performed by the controller + * | | |Otherwise if not set it indicates that DRAM initialization will be performed using the built-in initialization sequence or using software through the configuration port. + * |[19] |RDIMMINIT |RDIMM Initialization + * | | |Executes the RDIMM buffer chip initialization before executing DRAM initialization + * | | |The RDIMM buffer chip initialization is run after the DRAM is reset and CKE have been driven high by the DRAM initialization sequence. + * |[27] |CLRSR |Clear Status Registers + * | | |Writing 1 to this bit clears (reset to 0) select status bits in register PGSR0. + * | | |This bit is primarily for debug purposes and is typically not needed during normal functional operation + * | | |It can be used when PGSR.IDONE=1, to manually clear a selection of the PGSR status bits, although starting a new initialization process (PIR[0].INIT = 1'b1) automatically clears the PGSR status bits associated with the initialization steps enabled. + * | | |The following list describes which bits within the PGSR0 register are cleared when CLRSR is set to 1'b1 and which bits are not cleared: + * | | |The following bits are not cleared by PIR[27] (CLRSR): + * | | |- PGSR0[31] (APLOCK) + * | | |- PGSR0[29:28] (PLDONE_CHN) + * | | |- PGSR0[23] (WLAERR) + * | | |- PGSR0[21] (WLERR) + * | | |- PGSR0[4] (DIDONE) + * | | |- PGSR0[2] (DCDONE) + * | | |- PGSR0[1] (PLDONE) + * | | |- PGSR0[0] (IDONE) + * | | |The following bits are always zero: + * | | |- PGSR0[30] (reserved) + * | | |- PGSR0[19:12] (reserved) + * | | |The following bits are cleared unconditionally by PIR[27] (CLRSR): + * | | |- PGSR0[27] (WEERR) + * | | |- PGSR0[26] (REERR) + * | | |- PGSR0[25] (WDERR) + * | | |- PGSR0[24] (RDERR) + * | | |- PGSR0[22] (QSGERR) + * | | |- PGSR0[20] (ZCERR) + * | | |- PGSR0[11] (WEDONE) + * | | |- PGSR0[10] (REDONE) + * | | |- PGSR0[9] (WDDONE) + * | | |- PGSR0[8] (RDDONE) + * | | |- PGSR0[7] (WLADONE) + * | | |- PGSR0[6] (QSGDONE) + * | | |- PGSR0[5] (WLDONE) + * | | |- PGSR0[3] (ZCDONE) + * |[28] |LOCKBYP |PLL Lock Bypass + * | | |Bypasses or stops, if set, the waiting of PLLs to lock + * | | |PLL lock wait is automatically triggered after reset + * | | |PLL lock wait may be triggered manually using INIT and PLLINIT bits of the PIR register + * | | |This bit is self-clearing. + * |[29] |DCALBYP |Digital Delay Line Calibration Bypass + * | | |Bypasses or stops, if set, DDL calibration that automatically triggers after reset + * | | |DDL calibration may be triggered manually using INIT and DCAL bits of the PIR register + * | | |This bit is self- clearing. + * |[30] |ZCALBYP |Impedance Calibration Bypass + * | | |Bypasses or stops, if set, impedance calibration of all ZQ control blocks that automatically triggers after reset + * | | |Impedance calibration may be triggered manually using INIT and ZCAL bits of the PIR register + * | | |This bit is self-clearing. + * |[31] |INITBYP |Initialization Bypass + * | | |Bypasses or stops, if set, all initialization routines currently running, including PHY initialization, DRAM initialization, and PHY training + * | | |Initialization may be triggered manually using INIT and the other relevant bits of the PIR register + * | | |This bit is self-clearing. + * @var DDRPHY_T::PGCR0 + * Offset: 0x08 PHY General Configuration Registers 0 (PGCR0) + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[0] |WLLVT |Write Leveling LCDL Delay VT Compensation + * | | |Enables, if set, the VT drift compensation of the write leveling LCDL. + * |[1] |WDLVT |Write DQ LCDL Delay VT Compensation + * | | |Enables, if set, the VT drift compensation of the write DQ LCDL. + * |[2] |RDLVT |Read DQS LCDL Delay VT Compensation + * | | |Enables, if set, the VT drift compensation of the read DQS LCDL. + * |[3] |RGLVT |Read DQS Gating LCDL Delay VT Compensation + * | | |Enables, if set, the VT drift compensation of the read DQS gating LCDL. + * |[4] |WDBVT |Write Data BDL VT Compensation + * | | |Enables, if set, the VT drift compensation of the write data bit delay lines. + * |[5] |RDBVT |Read Data BDL VT Compensation + * | | |Enables, if set, the VT drift compensation of the read data bit delay lines. + * |[6] |DLTMODE |Delay Line Test Mode + * | | |Selects, if set, the delay line oscillator test mode + * | | |Setting this bit also clears all delay line register values + * | | |For DL oscillator testing, first set this bit, then apply desired non-zero LCDL and BDL register programmings. + * |[7] |DLTST |Delay Line Test Start + * | | |A write of '1' to this bit will trigger delay line oscillator mode period measurement + * | | |This bit is not self clearing and needs to be reset to '0' before the measurement can be re-triggered. + * |[8] |OSCEN |Oscillator Enable: Enables, if set, the delay line oscillation. + * |[11:9] |OSCDIV |Oscillator Mode Division + * | | |Specifies the factor by which the delay line oscillator mode output is divided down before it is output on the delay line digital test output pin dl_dto + * | | |Valid values are: + * | | |000 = Divide by 1 + * | | |001 = Divide by 256 + * | | |010 = Divide by 512 + * | | |011 = Divide by 1024 + * | | |100 = Divide by 2048 + * | | |101 = Divide by 4096 + * | | |110 = Divide by 8192 + * | | |111 = Divide by 65536 + * |[13:12] |OSCWDL |Oscillator Mode Write-Leveling Delay Line Select + * | | |Selects which of the two write leveling LCDLs is active + * | | |The delay select value of the inactive LCDL is set to zero while the delay select value of the active LCDL can be varied by the input write leveling delay select pin + * | | |Valid values are: + * | | |00 = No WL LCDL is active + * | | |01 = DDR WL LCDL is active + * | | |10 = SDR WL LCDL is active + * | | |11 = Both LCDLs are active + * |[18:14] |DTOSEL |Digital Test Output Select + * | | |Selects the PHY digital test output that is driven onto PHY digital test output (phy_dto) pin: Valid values are: + * | | |00000 = DATX8 0 PLL digital test output + * | | |00001 = DATX8 1 PLL digital test output + * | | |00010 = DATX8 2 PLL digital test output + * | | |00011 = DATX8 3 PLL digital test output + * | | |00100 = DATX8 4 PLL digital test output + * | | |00101 = DATX8 5 PLL digital test output + * | | |00110 = DATX8 6 PLL digital test output + * | | |00111 = DATX8 7 PLL digital test output + * | | |01000 = DATX8 8 PLL digital test output + * | | |01001 = AC PLL digital test output + * | | |01010 - 01111 = Reserved + * | | |10000 = DATX8 0 delay line digital test output + * | | |10001 = DATX8 1 delay line digital test output + * | | |10010 = DATX8 2 delay line digital test output + * | | |10011 = DATX8 3 delay line digital test output + * | | |10100 = DATX8 4 delay line digital test output + * | | |10101 = DATX8 5 delay line digital test output + * | | |10110 = DATX8 6 delay line digital test output + * | | |10111 = DATX8 7 delay line digital test output + * | | |11000 = DATX8 8 delay line digital test output + * | | |11001 = AC delay line digital test output + * | | |11010 - 11111 = Reserved + * |[25] |PUBMODE |PUB Mode Enable + * | | |Enables, if set, the PUB to control the interface to the PHY and SDRAM + * | | |In this mode the DFI commands from the controller are ignored + * | | |The bit must be set to 0 after the system determines it is convenient to pass control of the DFI bus to the controller + * | | |When set to 0 the DFI interface has control of the PHY and SDRAM interface except when triggering pub operations such as BIST, DCU or data training. + * |[31:26] |CKEN |CK Enable + * | | |Controls whether the CK going to the SDRAM is enabled (toggling) or disabled (static value) and whether the CK is inverted + * | | |Two bits for each of the up to three CK pairs + * | | |Valid values for the two bits are: + * | | |00 = CK disabled (Driven to constant 0) + * | | |01 = CK toggling with inverted polarity + * | | |10 = CK toggling with normal polarity (This should be the default setting) + * | | |11 = CK disabled (Driven to constant 1) + * @var DDRPHY_T::PGCR1 + * Offset: 0x0C PHY General Configuration Registers 1 (PGCR1) + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[0] |PDDISDX |Power Down Disabled Byte + * | | |Indicates, if set, that the PLL and I/Os of a disabled byte should be powered down. + * |[1] |WLMODE |Write Leveling Mode + * | | |Indicates, if set, that the PUB is in software write leveling mode in which software executes single steps of DQS pulsing by writing '1' to PIR.WL + * | | |The write leveling DQ status from the DRAM is captured in DXnGSR0.WLDQ. + * |[2] |WLSTEP |Write Leveling Step + * | | |Specifies the number of delay step-size increments during each step of write leveling + * | | |Valid values are: + * | | |0 = computed to be 1/2 of the associated lane's DXnGSR0.WLPRD value + * | | |1 = 1 step size + * |[4] |WSLOPT |Write System Latency Optimization + * | | |Controls the insertion of a pipeline stage on the AC signals from the DFI interface to the PHY to cater for a negative write system latency (WSL) value (only -1 possible). + * | | |0x0 = A pipeline stage is inserted only if WL2 training results in a WSL of -1 for any rank + * | | |0x1 = Inserts a pipeline stage + * |[5] |ACHRST |AC PHY High-Speed Reset + * | | |A Write of '0' to this bit resets the AC macro without resetting the PUB RTL logic + * | | |This bit is not self-clearing and a '1' must be written to de-assert the reset. + * |[6] |WLSELT |Write Leveling Select Type + * | | |Selects the encoding type for the write leveling select signal depending on the desired setup/hold margins for the internal pipelines + * | | |Refer to the DDR PHY Databook for details of how the select type is used + * | | |Valid values are: + * | | |0 = Type 1: Setup margin of 90 degrees and hold margin of 90 degrees + * | | |1 = Type 2: Setup margin of 135 degrees and hold margin of 45 degrees + * |[8:7] |IODDRM |I/O DDR Mode + * | | |Selects the DDR mode for the I/Os + * | | |These bits connect to bits [2:1] of the IOM pin of the SSTL I/O + * | | |For more information, refer to the SSTL I/O chapter in the DWC DDR PHY Databook. + * |[9] |MDLEN |Master Delay Line Enable + * | | |Enables, if set, the AC master delay line calibration to perform subsequent period measurements following the initial period measurements that are performed after reset or on when calibration is manually triggered + * | | |These additional measurements are accumulated and filtered as long as this bit remains high. + * |[10] |LPFEN |Low-Pass Filter Enable + * | | |Enables, if set, the low pass filtering of MDL period measurements. + * |[12:11] |LPFDEPTH |Low-Pass Filter Depth + * | | |Specifies the number of measurements over which MDL period measurements are filtered + * | | |This determines the time constant of the low pass filter + * | | |Valid values are: + * | | |00 = 2 + * | | |01 = 4 + * | | |10 = 8 + * | | |11 = 16 + * |[14:13] |FDEPTH |Filter Depth + * | | |Specifies the number of measurements over which all AC and DATX8 initial period measurements, that happen after reset or when calibration is manually triggered, are averaged + * | | |Valid values are: + * | | |00 = 2 + * | | |01 = 4 + * | | |10 = 8 + * | | |11 = 16 + * |[22:15] |DLDLMT |Delay Line VT Drift Limit + * | | |Specifies the minimum change in the delay line VT drift in one direction which should result in the assertion of the delay line VT drift status signal (vt_drift) + * | | |The limit is specified in terms of delay select values + * | | |A value of 0 disables the assertion of delay line VT drift status signal. + * |[24:23] |ZCKSEL |Impedance Clock Divider Select + * | | |Selects the divide ratio for the clock used by the impedance control logic relative to the clock used by the memory controller and SDRAM. + * | | |Valid values are: + * | | |00 = Divide by 2 + * | | |01 = Divide by 8 + * | | |10 = Divide by 32 + * | | |11 = Divide by 64 + * |[25] |DXHRST |DX PHY High-Speed Reset + * | | |a Write of '0' to this bit resets the DX macro without resetting the PUB RTL logic + * | | |This bit is not self-clearing and a '1' must be written to de-assert the reset. + * |[26] |INHVT |VT Calculation Inhibit + * | | |Inhibits calculation of the next VT compensated delay line values + * | | |A value of 1 will inhibit the VT calculation + * | | |This bit should be set to 1 during writes to the delay line registers. + * |[27] |IOLB |I/O Loop-Back Select + * | | |Selects where inside the I/O the loop-back of signals happens. Valid values are: + * | | |1'b0 = Loopback is after output buffer; output enable must be asserted + * | | |1'b1 = Loopback is before output buffer; output enable is don't care + * |[28] |LBDQSS |Loopback DQS Shift + * | | |Selects how the read DQS is shifted during loopback to ensure that the read DQS is centered into the read data eye + * | | |Valid values are: + * | | |1'b0 = PUB sets the read DQS LCDL to 0 (internally) + * | | |DQS is already shifted 90 degrees by write path + * | | |1'b1 = The read DQS shift is set manually through software + * |[30:29] |LBGDQS |Loopback DQS Gating + * | | |Selects the DQS gating mode that should be used when the PHY is in loopback mode, including BIST loopback mode + * | | |Valid values are: + * | | |2'b00 = DQS gate is always on + * | | |2'b01 = DQS gate training will be triggered on the PUB + * | | |2'b10 = DQS gate is set manually using software + * | | |2'b11 = Reserved + * |[31] |LBMODE |Loopback Mode + * | | |Indicates, if set, that the PHY/PUB is in loopback mode. + * @var DDRPHY_T::PGSR0 + * Offset: 0x10 PHY General Status Registers 0 (PGSR0) + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[0] |IDONE |Initialization Done + * | | |Indicates, if set, that the DDR system initialization has completed + * | | |This bit is set after all the selected initialization routines in PIR register have completed. + * |[1] |PLDONE |PLL Lock Done + * | | |Indicates, if set, that PLL locking has completed. + * |[2] |DCDONE |Digital Delay Line Calibration Done + * | | |Indicates, if set, that DDL calibration has completed. + * |[3] |ZCDONE |Impedance Calibration Done: Indicates, if set, that impedance calibration has completed. + * |[4] |DIDONE |DRAM Initialization Done + * | | |Indicates, if set, that DRAM initialization has completed. + * |[5] |WLDONE |Write Leveling Done + * | | |Indicates, if set, that write leveling has completed. + * |[6] |QSGDONE |Read DQS Gate Training Done + * | | |Indicates, if set, that DQS gate training has completed. + * |[7] |WLADONE |Write Leveling Adjustment Done + * | | |Indicates, if set, that write leveling adjustment has completed. + * |[8] |RDDONE |Read Data Bit Deskew Done + * | | |Indicates, if set, that read bit deskew has completed. + * |[9] |WDDONE |Write Data Bit Deskew Done + * | | |Indicates, if set, that write bit deskew has completed. + * |[10] |REDONE |Read Data Eye Training Done + * | | |Indicates, if set, that read eye training has completed. + * |[11] |WEDONE |Write Data Eye Training Done + * | | |Indicates, if set, that write eye training has completed. + * |[20] |ZCERR |Impedance Calibration Error + * | | |Indicates, if set, that there is an error in impedance calibration. + * |[21] |WLERR |Write Leveling Error + * | | |Indicates, if set, that there is an error in write leveling. + * |[22] |QSGERR |Read DQS Gate Training Error + * | | |Indicates, if set, that there is an error in DQS gate training. + * |[23] |WLAERR |Write Data Leveling Adjustment Error + * | | |Indicates, if set, that there is an error in write leveling adjustment. + * |[24] |RDERR |Read Data Bit Deskew Error + * | | |Indicates, if set, that there is an error in read bit deskew. + * |[25] |WDERR |Write Data Bit Deskew Error + * | | |Indicates, if set, that there is an error in write bit deskew. + * |[26] |REERR |Read Data Eye Training Error + * | | |Indicates, if set, that there is an error in read eye training. + * |[27] |WEERR |Write Eye Training Error + * | | |Indicates, if set, that there is an error in write eye training. + * |[29:28] |PLDONE_CHN|PLL Lock Done per Channel + * | | |Indicates PLL locking has completed for each underlying channel + * | | |Bit 28 represents channel 0 while bit 29 represents channel 1. + * |[31] |APLOCK |AC PLL Lock + * | | |Indicates, if set, that AC PLL has locked. This is a direct status of the AC PLL lock pin. + * @var DDRPHY_T::PGSR1 + * Offset: 0x14 PHY General Status Registers 1 (PGSR1) + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[0] |DLTDONE |Delay Line Test Done + * | | |Indicates, if set, that the PHY control block has finished doing period measurement of the AC delay line digital test output. + * |[24:1] |DLTCODE |Delay Line Test Code + * | | |Returns the code measured by the PHY control block that corresponds to the period of the AC delay line digital test output. + * |[30] |VTSTOP |VT Stop + * | | |Indicates, if set, that the VT calculation logic has stopped computing the next values for the VT compensated delay line values + * | | |After assertion of the PGCR.INHVT, the VTSTOP bit should be read to ensure all VT compensation logic has stopped computations before writing to the delay line registers. + * |[31] |PARERR |RDIMM Parity Error + * | | |Indicates, if set, that there was a parity error (i.e + * | | |err_out_n was sampled low) during one of the transactions to the RDIMM buffer chip + * | | |This bit remains asserted until cleared by the PIR.CLRSR. + * @var DDRPHY_T::PLLCR + * Offset: 0x18 PLL Control Register (PLLCR) + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[1:0] |DTC |Digital Test Control + * | | |Selects various PLL digital test signals and other test mode signals to be brought out via bit [1] of the PLL digital test output (pll_dto[1]) + * | | |Valid values are: + * | | |00 = '0' (Test output is disabled) + * | | |01 = PLL x1 clock (X1) + * | | |10 = PLL reference (input) clock (REF_CLK) + * | | |11 = PLL feedback clock (FB_X1) + * |[5:2] |ATC |Analog Test Control + * | | |Selects various PLL analog test signals to be brought out via PLL analog test output pin (pll_ato) + * | | |Valid values are: + * | | |0000 = Reserved + * | | |0001 = vdd_ckin + * | | |0010 = vrfbf + * | | |0011 = vdd_cko + * | | |0100 = vp_cp + * | | |0101 = vpfil(vp) + * | | |0110 = Reserved + * | | |0111 = gd + * | | |1000 = vcntrl_atb + * | | |1001 = vref_atb + * | | |1010 = vpsf_atb + * | | |1011 - 1111 = Reserved + * |[9:6] |ATOEN |Analog Test Enable + * | | |Selects the analog test signal that is driven on the analog test output pin + * | | |Otherwise the analog test output is tri-stated + * | | |This allows analog test output pins from multiple PLLs to be connected together + * | | |Valid values are: + * | | |0000 = All PLL analog test signals are tri-stated + * | | |0001 = AC PLL analog test signal is driven out + * | | |0010 = DATX8 0 PLL analog test signal is driven out + * | | |0011 = DATX8 1 PLL analog test signal is driven out + * | | |0100 = DATX8 2 PLL analog test signal is driven out + * | | |0101 = DATX8 3 PLL analog test signal is driven out + * | | |0110 = DATX8 4 PLL analog test signal is driven out + * | | |0111 = DATX8 5 PLL analog test signal is driven out + * | | |1000 = DATX8 6 PLL analog test signal is driven out + * | | |1001 = DATX8 7 PLL analog test signal is driven out + * | | |1010 = DATX8 8 PLL analog test signal is driven out + * | | |1011 - 1111 = Reserved + * |[10] |GSHIFT |Gear Shift + * | | |Enables, if set, rapid locking mode. + * |[12:11] |CPIC |Charge Pump Integrating Current Control + * |[16:13] |CPPC |Charge Pump Proportional Current Control + * |[17] |QPMODE |PLL Quadrature Phase Mode + * | | |Enables, if set, the quadrature phase clock outputs. This mode is not used in this version of the PHY. + * |[19:18] |FRQSEL |PLL Frequency Select + * | | |00 = PLL reference clock (ctl_clk/REF_CLK) ranges from 250 MHz to 400 MHz + * | | |01 = PLL reference clock (ctl_clk/REF_CLK) ranges from 166 MHz to 300 MHz + * | | |10 = Reserved + * | | |11 = Reserved + * |[29] |PLLPD |PLL Power Down + * | | |Puts the PLLs in Power-down mode by driving the PLL power down pin + * | | |This bit is not self-clearing and a '0' must be written to de-assert the power-down. + * |[30] |PLLRST |PLL Rest + * | | |Resets the PLLs by driving the PLL reset pin + * | | |This bit is not self-clearing and a '0' must be written to de-assert the reset. + * |[31] |BYP |PLL Bypass + * | | |Bypasses the PLL, if set, to 1. + * @var DDRPHY_T::PTR0 + * Offset: 0x1C PHY Timing Registers 0 (PTR0) + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[5:0] |tPHYRST |PHY Reset Time + * | | |Number of configuration or APB clock cycles that the PHY reset must remain asserted after PHY calibration is done before the reset to the PHY is de-asserted + * | | |This is used to extend the reset to the PHY so that the reset is asserted for some clock cycles after the clocks are stable + * | | |Valid values are from 1 to 63 (the value must be non-zero). + * |[20:6] |tPLLGS |PLL Gear Shift Time + * | | |Number of configuration or APB clock cycles from when the PLL reset pin is de-asserted to when the PLL gear shift pin is de-asserted + * | | |This must correspond to a value that is equal to or more than 4us + * | | |Default value corresponds to 4us. + * |[31:21] |tPLLPD |PLL Power-Down Time + * | | |Number of configuration or APB clock cycles that the PLL must remain in power-down mode, i.e + * | | |number of clock cycles from when PLL power-down pin is asserted to when PLL power-down pin is de-asserted + * | | |This must correspond to a value that is equal to or more than 1us + * | | |Default value corresponds to 1us. + * @var DDRPHY_T::PTR1 + * Offset: 0x20 PHY Timing Registers 1 (PTR1) + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[12:0] |tPLLRST |PLL Reset Time + * | | |Number of configuration or APB clock cycles that the PLL must remain in reset mode, i.e + * | | |number of clock cycles from when PLL power-down pin is de-asserted and PLL reset pin is asserted to when PLL reset pin is de-asserted + * | | |The setting must correspond to a value that is equal to, or greater than 3us. + * |[31:16] |tPLLLOCK |PLL Lock Time + * | | |Number of configuration or APB clock cycles for the PLL to stabilize and lock, i.e + * | | |number of clock cycles from when the PLL reset pin is de-asserted to when the PLL has lock and is ready for use + * | | |This must correspond to a value that is equal to or more than 100us + * | | |Default value corresponds to 100us. + * @var DDRPHY_T::PTR2 + * Offset: 0x24 PHY Timing Registers 2 (PTR2) + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[4:0] |tCALON |Calibration On Time + * | | |Number of clock cycles that the calibration clock is enabled (cal_clk_en asserted). + * |[9:5] |tCALS |Calibration Setup Time + * | | |Number of controller clock cycles from when calibration is enabled (cal_en asserted) to when the calibration clock is asserted again (cal_clk_en asserted). + * |[14:10] |tCALH |Calibration Hold Time + * | | |Number of controller clock cycles from when the clock was disabled (cal_clk_en deasserted) to when calibration is enable (cal_en asserted). + * |[19:15] |tWLDLYS |Write Leveling Delay Settling Time + * | | |Number of controller clock cycles from when a new value of the write leveling delay is applied to the LCDL to when to DQS high is driven high + * | | |This allows the delay to settle. + * @var DDRPHY_T::PTR3 + * Offset: 0x28 PHY Timing Registers 3 (PTR3) + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[19:0] |tDINIT0 |DRAM Initialization Time 0 + * | | |DRAM initialization time in DRAM clock cycles corresponding to the following: + * | | |DDR3 = CKE low time with power and clock stable (500 us) DDR2 = CKE low time with power and clock stable (200 us) Default value corresponds to DDR3 500 us at 1066 MHz. + * | | |During Verilog simulations, it is recommended that this value is changed to a much smaller value in order to avoid long simulation times + * | | |However, this may cause a memory model error, due to a violation of the CKE setup sequence + * | | |This violation is expected if this value is not programmed to the required SDRAM CKE low time, but memory models should be able to tolerate this violation without malfunction of the model. + * |[28:20] |tDINIT1 |DRAM Initialization Time 1 + * | | |DRAM initialization time in DRAM clock cycles corresponding to the following: + * | | |DDR3 = CKE high time to first command (tRFC + 10 ns or 5 tCK, whichever is bigger) DDR2 = CKE high time to first command (400 ns) + * | | |Default value corresponds to DDR3 tRFC of 360ns at 1066 MHz. + * @var DDRPHY_T::PTR4 + * Offset: 0x2C PHY Timing Registers 4 (PTR4) + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[17:0] |tDINIT2 |DRAM Initialization Time 2 + * | | |DRAM initialization time in DRAM clock cycles corresponding to the following: + * | | |DDR3 = Reset low time (200 us on power-up or 100 ns after power-up) Default value corresponds to DDR3 200 us at 1066 MHz. + * |[27:18] |tDINIT3 |DRAM Initialization Time 3 + * | | |DRAM initialization time in DRAM clock cycles corresponding to the following: + * | | |DDR3 = Time from ZQ initialization command to first command (1 us) Default value corresponds to the DDR3 640ns at 1066 MHz. + * @var DDRPHY_T::ACMDLR + * Offset: 0x30 AC Master Delay Line Register (ACMDLR) + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[7:0] |IPRD |Initial Period + * | | |Initial period measured by the master delay line calibration for VT drift compensation + * | | |This value is used as the denominator when calculating the ratios of updates during VT compensation. + * |[15:8] |TPRD |Target Period + * | | |Target period measured by the master delay line calibration for VT drift compensation + * | | |This is the current measured value of the period and is continuously updated if the MDL is enabled to do so. + * |[23:16] |MDLD |MDL Delay + * | | |Delay select for the LCDL for the Master Delay Line. + * @var DDRPHY_T::ACBDLR + * Offset: 0x34 AC Bit Delay Line Register (ACBDLR) + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[5:0] |CK0BD |CK0 Bit Delay + * | | |Delay select for the BDL on CK0. + * |[11:6] |CK1BD |CK1 Bit Delay + * | | |Delay select for the BDL on CK1. + * |[17:12] |CK2BD |CK2 Bit Delay + * | | |Delay select for the BDL on CK2. + * |[23:18] |ACBD |Address/Command Bit Delay + * | | |Delay select for the BDLs on address and command signals. + * @var DDRPHY_T::ACIOCR + * Offset: 0x38 AC I/O Configuration Register (ACIOCR) + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[0] |ACIOM |Address/Command I/O Mode + * | | |Selects SSTL mode (when set to 0) or CMOS mode (when set to 1) of the I/O for all address and command pins + * | | |This bit connects to bit [0] of the IOM pin on the D3F I/Os, and for other I/O libraries, it connects to the IOM pin of the I/O. + * |[1] |ACOE |Address/Command Output Enable + * | | |Enables, when set, the output driver on the I/O for all address and command pins. + * |[2] |ACODT |Address/Command On-Die Termination + * | | |Enables, when set, the on-die termination on the I/O for RAS#, CAS#, WE#, BA[2:0], and A[15:0] pins. + * |[3] |ACPDD |AC Power Down Driver + * | | |Powers down, when set, the output driver on the I/O for RAS#, CAS#, WE#, BA[2:0], and A[15:0] pins. + * | | |Note: Asserting PDD puts the IO driver cell into a lower power, lower speed mode of operation + * | | |However, it will still drive if its OE is asserted + * | | |ODT will be disabled (if used) + * | | |Asserting PDD does not prevent the IO from driving. + * |[4] |ACPDR |AC Power Down Receiver + * | | |Powers down, when set, the input receiver on the I/O for RAS#, CAS#, WE#, BA[2:0], and A[15:0] pins. + * |[7:5] |CKODT |CK On-Die Termination + * | | |Enables, when set, the on-die termination on the I/O for CK[0], CK[1], and CK[2] pins, respectively. + * |[10:8] |CKPDD |CK Power Down Driver + * | | |Powers down, when set, the output driver on the I/O for CK[0], CK[1], and CK[2] pins, respectively. + * | | |Note: Asserting PDD puts the IO driver cell into a lower power, lower speed mode of operation + * | | |However, it will still drive if its OE is asserted + * | | |ODT will be disabled (if used) + * | | |Asserting PDD does not prevent the IO from driving. + * |[13:11] |CKPDR |CK Power Down Receiver + * | | |Powers down, when set, the input receiver on the I/O for CK[0], CK[1], and CK[2] pins, respectively. + * |[17:14] |RANKODT |Rank On-Die Termination + * | | |Enables, when set, the on-die termination on the I/O for CKE[3:0], ODT[3:0], and CS#[3:0] pins + * | | |RANKODT[0] controls the on-die termination for CKE[0], ODT[0], and CS#[0], RANKODT[1] controls the on-die termination for CKE[1], ODT[1], and CS#[1], and so on. + * |[21:18] |CSPDD |CS# Power Down Driver + * | | |Powers down, when set, the output driver on the I/O for CS#[3:0] pins + * | | |CSPDD[0] controls the power down for CS#[0], CSPDD[1] controls the power down for CS#[1], and so on + * | | |CKE and ODT driver power down is controlled by DSGCR register. + * | | |Note: Asserting PDD puts the IO driver cell into a lower power, lower speed mode of operation + * | | |However, it will still drive if its OE is asserted + * | | |ODT will be disabled (if used) + * | | |Asserting PDD does not prevent the IO from driving. + * |[25:22] |RANKPDR |Rank Power Down Receiver + * | | |Powers down, when set, the input receiver on the I/O CKE[3:0], ODT[3:0], and CS#[3:0] pins + * | | |RANKPDR[0] controls the power down for CKE[0], ODT[0], and CS#[0], RANKPDR[1] controls the power down for CKE[1], ODT[1], and CS#[1], and so on. + * |[26] |RSTODT |SDRAM Reset On-Die Termination + * | | |Enables, when set, the on-die termination on the I/O for SDRAM RST# pin. + * |[27] |RSTPDD |SDRAM Reset Power Down Driver + * | | |Powers down, when set, the output driver on the I/O for SDRAM RST# pin. + * | | |Note: Asserting PDD puts the IO driver cell into a lower power, lower speed mode of operation + * | | |However, it will still drive if its OE is asserted + * | | |ODT will be disabled (if used) + * | | |Asserting PDD does not prevent the IO from driving. + * |[28] |RSTPDR |SDRAM Reset Power Down Receiver + * | | |Powers down, when set, the input receiver on the I/O for SDRAM RST# pin. + * |[29] |RSTIOM |SDRAM Reset I/O Mode + * | | |Selects SSTL mode (when set to 0) or CMOS mode (when set to 1) of the I/O for SDRAM Reset. + * |[31:30] |ACSR |Address/Command Slew Rate + * | | |Selects slew rate of the I/O for all address and command pins. + * @var DDRPHY_T::DXCCR + * Offset: 0x3C DATX8 Common Configuration Register (DXCCR) + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[0] |DXODT |Data On-Die Termination + * | | |Enables, when set, the on-die termination on the I/O for DQ, DM, and DQS/DQS# pins of all DATX8 macros + * | | |This bit is ORed with the ODT configuration bit of the individual DATX8 ("DATX8 General Configuration Register (DXnGCR)") + * |[1] |DXIOM |Data I/O Mode + * | | |Selects SSTL mode (when set to 0) or CMOS mode (when set to 1) of the I/O for DQ, DM, and DQS/DQS# pins of all DATX8 macros + * | | |This bit is ORed with the IOM configuration bit of the individual DATX8. + * |[2] |MDLEN |Master Delay Line Enable + * | | |Enables, if set, all DATX8 master delay line calibration to perform subsequent period measurements following the initial period measurements that are performed after reset or on when calibration is manually triggered + * | | |These additional measurements are accumulated and filtered as long as this bit remains high + * | | |This bit is ANDed with the MDLEN bit in the individual DATX8. + * |[3] |DXPDD |Data Power Down Driver + * | | |Powers down, when set, the output driver on I/O for DQ, DM, and DQS/DQS# pins of all DATX8 macros + * | | |This bit is ORed with the PDD configuration bit of the individual DATX8. + * | | |Note: Asserting PDD puts the IO driver cell into a lower power, lower speed mode of operation + * | | |However, it will still drive if its OE is asserted + * | | |ODT will be disabled (if used) + * | | |Asserting PDD does not prevent the IO from driving. + * |[4] |DXPDR |Data Power Down Receiver + * | | |Powers down, when set, the input receiver on I/O for DQ, DM, and DQS/DQS# pins of all DATX8 macros + * | | |This bit is ORed with the PDR configuration bit of the individual DATX8. + * |[8:5] |DQSRES |DQS Resistor + * | | |Selects the on-die pull-down/pull-up resistor for DQS pins + * | | |DQSRES[3] selects pull-down (when set to 0) or pull-up (when set to 1) + * | | |DQSRES[2:0] selects the resistor value. + * | | |Refer PHY databook for pull-down/pull-up resistor values (RA_SEL/RB_SEL) for + * | | |DQS/DQS_b. + * |[12:9] |DQSNRES |DQS# Resistor + * | | |Selects the on-die pull-up/pull-down resistor for DQS# pins. Same encoding as DQSRES. + * | | |Refer PHY databook for pull-down/pull-up resistor values (RA_SEL/RB_SEL) for + * | | |DQS/DQS_b. + * |[14:13] |DXSR |Data Slew Rate + * | | |Selects slew rate of the I/O for DQ, DM, and DQS/DQS# pins of all DATX8 macros. + * |[17:15] |MSBUDQ |Most Significant Byte Unused DQs + * | | |Specifies the number of DQ bits that are not used in the most significant byte + * | | |The used (valid) bits for this byte are [8-MSBDQ-1:0] + * | | |To disable the whole byte, use the DXnGCR.DXEN register. + * |[18] |UDQODT |Unused DQ On-Die Termination + * | | |Enables, when set, the on-die termination on the I/O for unused DQ pins. + * |[19] |UDQPDD |Unused DQ Power Down Driver + * | | |Powers down, when set, the output driver on the I/O for unused DQ pins. + * | | |Note: Asserting PDD puts the IO driver cell into a lower power, lower speed mode of operation + * | | |However, it will still drive if its OE is asserted + * | | |ODT will be disabled (if used) + * | | |Asserting PDD does not prevent the IO from driving. + * |[20] |UDQPDR |Unused DQ Power Down Receiver + * | | |Powers down, when set, the input receiver on the I/O for unused DQ pins. + * |[21] |UDQIOM |Unused DQ I/O Mode + * | | |Selects SSTL mode (when set to 0) or CMOS mode (when set to 1) of the I/O for unused DQ pins. + * |[22] |DYNDXPDD |Dynamic Data Power Down Driver + * | | |Dynamically powers down, when set, the output driver on I/O for the DQ pins of the active DATX8 macros + * | | |Applies only when DXPDD and DXnGCR.DXPDD are not set to 1 + * | | |Driver is powered-up on a DFI WRITE command and powered-down (twrlat + WL/2 + n) HDR cycles after the last DFI WRITE command + * | | |Note that n is defined by the register bit field DXCCR[27:24] (DDPDDCDO). + * | | |Note: Asserting PDD puts the IO driver cell into a lower power, lower speed mode of operation + * | | |However, it will still drive if its OE is asserted + * | | |ODT will be disabled (if used) + * | | |Asserting PDD does not prevent the IO from driving. + * |[23] |DYNDXPDR |Data Power Down Receiver + * | | |Dynamically powers down, when set, the input receiver on I/O for the DQ pins of the active DATX8 macros + * | | |Applies only when DXPDR and DXnGCR.DXPDR are not set to 1 + * | | |Receiver is powered-up on a DFI READ command and powered-down (trddata_en + fixed_read_latency + n) HDR cycles after the last DFI READ command + * | | |Note that n is defined by the register bit field DXCCR[31:28] (DDPDRCDO). + * |[27:24] |DDPDDCDO |Dynamic Data Power Down Driver Count Down Offset + * | | |Offset applied in calculating window of time where driver is powered up + * |[31:28] |DDPDRCDO |Dynamic Data Power Down Receiver Count Down Offset + * | | |Offset applied in calculating window of time where receiver is powered up + * @var DDRPHY_T::DSGCR + * Offset: 0x40 DDR System General Configuration Register (DSGCR) + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[0] |PUREN |PHY Update Request Enable + * | | |Specifies if set, that the PHY should issue PHY- initiated update request when there is DDL VT drift. + * |[1] |BDISEN |Byte Disable Enable + * | | |Specifies, if set, that the PHY should respond to DFI byte disable request + * | | |Otherwise the byte disable from the DFI is ignored in which case bytes can only be disabled using the DXnGCR register. + * |[2] |ZUEN |Impedance Update Enable + * | | |Specifies, if set, that in addition to DDL VT update, the PHY could also perform impedance calibration (update). + * | | |Refer to the "Impedance Control Register 0-1 (ZQnCR0-1)" bit fields DFICU0, DFICU1 and DFICCU bits to control if an impedance calibration is performed (update) with a DFI controller update request. + * | | |Refer to the "Impedance Control Register 0-1 (ZQnCR0-1)"D bit fields DFIPU0 and DFIPU1 bits to control if an impedance calibration is performed (update) with a DFI PHY update request. + * |[3] |LPIOPD |Low Power I/O Power Down + * | | |Specifies, if set, that the PHY should respond to the DFI low power opportunity request and power down the I/Os of the byte. + * |[4] |LPPLLPD |Low Power PLL Power Down + * | | |Specifies, if set, that the PHY should respond to the DFI low power opportunity request and power down the PLL of the byte if the wakeup time request satisfies the PLL lock time. + * |[5] |CUAEN |Controller Update Acknowledge Enable + * | | |Specifies, if set, that the PHY should issue controller update acknowledge when the DFI controller update request is asserted + * | | |By default, the PHY does not acknowledge controller initiated update requests but simply does an update whenever there is a controller update request + * | | |This speeds up the update. + * |[6] |DQSGX |DQS Gate Extension + * | | |Specifies, if set, that the DQS gating must be extended by two DRAM clock cycles and then re-centered, i.e + * | | |one clock cycle extension on either side. + * |[7] |BRRMODE |Bypass Rise-to-Rise Mode + * | | |Indicates, if set, that the PHY bypass mode is configured to run in rise-to-rise mode + * | | |Otherwise if not set the PHY bypass mode is running in rise-to-fall mode. + * |[11:8] |PUAD |PHY Update Acknowledge Delay + * | | |Specifies the number of clock cycles that the indication for the completion of PHY update from the PHY to the controller should be delayed + * | | |This essentially delays, by this many clock cycles, the de-assertion of dfi_ctrlup_ack and dfi_phyupd_req signals relative to the time when the delay lines or I/Os are updated. + * |[12] |DTOODT |DTO On-Die Termination + * | | |Enables, when set, the on-die termination on the I/O for DTO pins. + * |[13] |DTOPDD |DTO Power Down Driver + * | | |Powers down, when set, the output driver on the I/O for DTO pins. + * | | |Note: Asserting PDD puts the IO driver cell into a lower power, lower speed mode of operation + * | | |However, it will still drive if its OE is asserted + * | | |ODT will be disabled (if used) + * | | |Asserting PDD does not prevent the IO from driving. + * |[14] |DTOPDR |DTO Power Down Receiver + * | | |Powers down, when set, the input receiver on the I/O for DTO pins. + * |[15] |DTOIOM |DTO I/O Mode + * | | |Selects SSTL mode (when set to 0) or CMOS mode (when set to 1) of the I/O for DTO pins. + * |[16] |DTOOE |DTO Output Enable + * | | |Enables, when set, the output driver on the I/O for DTO pins. + * |[17] |ATOAE |ATO Analog Test Enable + * | | |Enables, if set, the analog test output (ATO) I/O. + * |[18] |RRMODE |Rise-to-Rise Mode + * | | |Indicates, if set, that the PHY mission mode is configured to run in rise-to-rise mode + * | | |Otherwise if not set the PHY mission mode is running in rise-to- fall mode. + * |[19] |SDRMODE |Single Data Rate Mode + * | | |Indicates, if set, that the external controller is configured to run in single data rate (SDR) mode + * | | |Otherwise if not set the controller is running in half data rate (HDR) mode + * | | |This bit not supported in the current version of the PUB. + * |[23:20] |CKEPDD |CKE Power Down Driver + * | | |Powers down, when set, the output driver on the I/O for CKE[3:0] pins + * | | |CKEPDD[0] controls the power down for CKE[0], CKEPDD[1] controls the power down for CKE[1], and so on. + * | | |Note: Asserting PDD puts the IO driver cell into a lower power, lower speed mode of operation + * | | |However, it will still drive if its OE is asserted + * | | |ODT will be disabled (if used) + * | | |Asserting PDD does not prevent the IO from driving. + * |[27:24] |ODTPDD |ODT Power Down Driver + * | | |Powers down, when set, the output driver on the I/O for ODT[3:0] pins + * | | |ODTPDD[0] controls the power down for ODT[0], ODTPDD[1] controls the power down for ODT[1], and so on. + * | | |Note: Asserting PDD puts the IO driver cell into a lower power, lower speed mode of operation + * | | |However, it will still drive if its OE is asserted + * | | |ODT will be disabled (if used) + * | | |Asserting PDD does not prevent the IO from driving. + * |[28] |CKOE |SDRAM CK Output Enable + * | | |Enables, when set, the output driver on the I/O for SDRAM CK/CK# pins. + * |[29] |ODTOE |SDRAM ODT Output Enable + * | | |Enables, when set, the output driver on the I/O for SDRAM ODT pins. + * |[30] |RSTOE |SDRAM Reset Output Enable + * | | |Enables, when set, the output driver on the I/O for SDRAM RST# pin. + * |[31] |CKEOE |SDRAM CKE Output Enable + * | | |Enables, when set, the output driver on the I/O for SDRAM CKE pins. + * @var DDRPHY_T::DCR + * Offset: 0x44 DRAM Configuration Register (DCR) + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[2:0] |DDRMD |DDR Mode + * | | |SDRAM DDR mode. Valid values are: + * | | |000 = Reserved + * | | |001 = Reserved + * | | |010 = DDR2 + * | | |011 = DDR3 + * | | |100 - 111 = Reserved + * |[3] |DDR8BNK |DDR 8-Bank + * | | |Indicates, if set, that the SDRAM used has 8 banks + * | | |tRPA = tRP+1 and tFAW are used for 8-bank DRAMs, otherwise tRPA = tRP and no tFAW is used. + * | | |Note that a setting of 1 for DRAMs that have fewer than 8 banks results in correct functionality, but less tight DRAM command spacing for the parameters. + * |[6:4] |PDQ |Primary DQ + * | | |Specifies the DQ pin in a byte that is designated as a primary pin for Multi-Purpose Register (MPR) reads + * | | |Valid values are 0 to 7 for DQ[0] to DQ[7], respectively. + * |[7] |MPRDQ |Multi-Purpose Register DQ + * | | |Specifies the value that is driven on non-primary DQ pins during MPR reads. Valid values are: + * | | |0 = Primary DQ drives out the data from MPR (0-1-0-1); non-primary DQs drive '0' + * | | |1 = Primary DQ and non-primary DQs all drive the same data from MPR (0-1-0-1) + * |[17:10] |BYTEMASK |Byte Mask + * | | |Mask applied to all beats of read data on all byte lanes during read DQS gate training + * | | |This allows training to be conducted based on selected bit(s) from the byte lanes. + * | | |Valid values for each bit are: + * | | |0 = Disable compare for that bit + * | | |1 = Enable compare for that bit + * | | |Note that this mask applies in DDR3 MPR operation mode as well and must be in keeping with the PDQ field setting. + * |[27] |NOSRA |No Simultaneous Rank Access + * | | |Specifies, if set, that simultaneous rank access on the same clock cycle is not allowed + * | | |This means that multiple chip select signals should not be asserted at the same time + * | | |This may be required on some DIMM systems. + * |[28] |DDR2T |DDR 2T Timing + * | | |Indicates, if set, that 2T timing should be used by PUB internally generated SDRAM transactions. + * |[29] |UDIMM |Un-buffered DIMM Address Mirroring + * | | |Indicates, if set, that there is address mirroring on the second rank of an un-buffered DIMM (the rank connected to CS#[1]) + * | | |In this case, the PUB re-scrambles the bank and address when sending mode register commands to the second rank + * | | |This only applies to PUB internal SDRAM transactions + * | | |Transactions generated by the controller must make its own adjustments when using an un-buffered DIMM + * | | |DCR[NOSRA] must be set if address mirroring is enabled. + * @var DDRPHY_T::DTPR0 + * Offset: 0x48 DRAM Timing Parameters Register 0 (DTPR0) 105 + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[3:0] |tRTP |Internal read to precharge command delay + * | | |Valid values are 2 to 15. + * |[7:4] |tWTR |Internal write to read command delay + * | | |Valid values are 1 to 15. + * |[11:8] |tRP |Precharge command period + * | | |The minimum time between a precharge command and any other command + * | | |Note that the Controller automatically derives tRPA for 8- bank DDR2 devices by adding 1 to tRP + * | | |Valid values are 2 to 15. + * |[15:12] |tRCD |Activate to read or write delay + * | | |Minimum time from when an activate command is issued to when a read or write to the activated row can be issued + * | | |Valid values are 2 to 15. + * |[21:16] |tRAS |Activate to precharge command delay + * | | |Valid values are 2 to 63. + * |[25:22] |tRRD |Activate to activate command delay + * | | |Valid values are 1 to 15. + * |[31:26] |tRC |Activate to activate command delay + * | | |Valid values are 2 to 63. + * @var DDRPHY_T::DTPR1 + * Offset: 0x4C DRAM Timing Parameters Register 1 (DTPR1) + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[1:0] |tMRD |Load mode cycle time + * | | |The minimum time between a load mode register command and any other command + * | | |For DDR3 this is the minimum time between two load mode register commands + * | | |Valid values for DDR2 are 2 to 3 + * | | |For DDR3, the value used for tMRD is 4 plus the value programmed in these bits, i.e + * | | |tMRD value for DDR3 ranges from 4 to 7. + * |[4:2] |tMOD |Load mode update delay + * | | |The minimum time between a load mode register command and a non-load mode register command + * | | |Valid values are: + * | | |000 = 12 + * | | |001 = 13 + * | | |010 = 14 + * | | |011 = 15 + * | | |100 = 16 + * | | |101 = 17 + * | | |110 - 111 = Reserved + * |[10:5] |tFAW |4-bank activate period + * | | |No more than 4-bank activate commands may be issued in a given tFAW period + * | | |Only applies to 8-bank devices + * | | |Valid values are 2 to 63. + * |[19:11] |tRFC |Refresh-to-Refresh + * | | |Indicates the minimum time between two refresh commands or between a refresh and an active command + * | | |This is derived from the minimum refresh interval from the Datasheet, tRFC(min), divided by the clock cycle time + * | | |The default number of clock cycles is for the largest JEDEC tRFC(min parameter value supported. + * |[25:20] |tWLMRD |Minimum delay from when write leveling mode is programmed to the first + * | | |DQS/DQS# rising edge. + * |[29:26] |tWLO |Write leveling output delay + * | | |Number of clock cycles from when write leveling DQS is driven high by the control block to when the results from the SDRAM on DQ is sampled by the control block + * | | |This must include the SDRAM tWLO timing parameter plus the round trip delay from control block to SDRAM back to control block. + * |[31:30] |tAONDtAOFD|ODT turn-on/turn-off delays. + * | | |Valid values are: + * | | |00 = 2/2.5 + * | | |01 = 3/3.5 + * | | |10 = 4/4.5 + * | | |11 = 5/5.5 + * | | |Most DDR2 devices utilize a fixed value of 2/2.5 + * | | |For non-standard SDRAMs, the user must ensure that the operational Write Latency is always greater than or equal to the ODT turn-on delay + * | | |For example, a DDR2 SDRAM with CAS latency set to 3 and CAS additive latency set to 0 has a Write Latency of 2 + * | | |Thus 2/2.5 can be used, but not 3/3.5 or higher. + * @var DDRPHY_T::DTPR2 + * Offset: 0x50 DRAM Timing Parameters Register 2 (DTPR2) + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[9:0] |tXS |Self refresh exit delay + * | | |The minimum time between a self refresh exit command and any other command + * | | |This parameter must be set to the maximum of the various minimum self refresh exit delay parameters specified in the SDRAM Datasheet, i.e + * | | |max(tXSNR, tXSRD) for DDR2 and max(tXS, tXSDLL) for DDR3 + * | | |Valid values are 2 to + * | | |1023. + * |[14:10] |tXP |Power down exit delay + * | | |The minimum time between a power down exit command and any other command + * | | |This parameter must be set to the maximum of the various minimum power down exit delay parameters specified in the SDRAM Datasheet, i.e + * | | |max(tXP, tXARD, tXARDS) for DDR2 and max(tXP, tXPDLL) for DDR3 + * | | |Valid values are 2 to 31. + * |[18:15] |tCKE |CKE minimum pulse width + * | | |Also specifies the minimum time that the SDRAM must remain in power down or self refresh mode + * | | |For DDR3 this parameter must be set to the value of tCKESR which is usually bigger than the value of tCKE + * | | |Valid values are 2 to 15. + * |[28:19] |tDLLK |DLL locking time + * | | |Valid values are 2 to 1023. + * |[29] |tRTODT |Read to ODT delay + * | | |Specifies whether ODT can be enabled immediately after the read post-amble or one clock delay has to be added + * | | |Valid values are: + * | | |0 = ODT may be turned on immediately after read post-amble + * | | |1 = ODT may not be turned on until one clock after the read post-amble + * | | |If tRTODT is set to 1, then the read-to-write latency is increased by 1 if ODT is enabled. + * |[30] |tRTW |Read to Write command delay + * | | |Valid values are: + * | | |0 = standard bus turn around delay + * | | |1 = add 1 clock to standard bus turn around delay + * | | |This parameter allows the user to increase the delay between issuing Write commands to the SDRAM when preceded by Read commands + * | | |This provides an option to increase bus turn-around margin for high frequency systems. + * |[31] |tCCD |Read to read and write to write command delay + * | | |Valid values are: + * | | |0 = BL/2 for DDR2 and 4 for DDR3 + * | | |1 = BL/2 + 1 for DDR2 and 5 for DDR3 + * @var DDRPHY_T::MR0 + * Offset: 0x54 Mode Register 0 (MR0) + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[1:0] |BL |Burst Length + * | | |Determines the maximum number of column locations that can be accessed during a given read or write command + * | | |Valid values are: + * | | |Valid values for DDR3 are: + * | | |00 = 8 (Fixed) + * | | |01 = 4 or 8 (On the fly) + * | | |10 = 4 (Fixed) + * | | |11 = Reserved + * |[2] |CL0 |CAS Latency + * | | |The delay between when the SDRAM registers a read command to when data is available. Valid values are: + * | | |0010 = 5 + * | | |0100 = 6 + * | | |0110 = 7 + * | | |1000 = 8 + * | | |1010 = 9 + * | | |1100 = 10 + * | | |1110 = 11 + * | | |0001 = 12 + * | | |0011 = 13 + * | | |0101 = 14 + * | | |All other settings are reserved and should not be used. + * |[3] |BT |Burst Type + * | | |Indicates whether a burst is sequential (0) or interleaved (1). + * |[6:4] |CL1 |CAS Latency + * | | |The delay between when the SDRAM registers a read command to when data is available. Valid values are: + * | | |0010 = 5 + * | | |0100 = 6 + * | | |0110 = 7 + * | | |1000 = 8 + * | | |1010 = 9 + * | | |1100 = 10 + * | | |1110 = 11 + * | | |0001 = 12 + * | | |0011 = 13 + * | | |0101 = 14 + * | | |All other settings are reserved and should not be used. + * |[7] |TM |Operating Mode + * | | |Selects either normal operating mode (0) or test mode (1) + * | | |Test mode is reserved for the manufacturer and should not be used. + * |[8] |DR |DLL Reset + * | | |Writing a '1' to this bit will reset the SDRAM DLL + * | | |This bit is self- clearing, i.e + * | | |it returns back to '0' after the DLL reset has been issued. + * |[11:9] |WR |Write Recovery + * | | |This is the value of the write recovery + * | | |It is calculated by dividing the Datasheet write recovery time, tWR (ns) by the Datasheet clock cycle time, tCK (ns) and rounding up a non-integer value to the next integer + * | | |Valid values are: + * | | |000 = 16 + * | | |001 = 5 + * | | |010 = 6 + * | | |011 = 7 + * | | |100 = 8 + * | | |101 = 10 + * | | |110 = 12 + * | | |111 = 14 + * | | |All other settings are reserved and should not be used. + * | | |Note: tWR (ns) is the time from the first SDRAM positive clock edge after the last data-in pair of a write command, to when a precharge of the same bank can be issued. + * |[12] |PD |Power-Down Control + * | | |Controls the exit time for power-down modes + * | | |Refer to the SDRAM Datasheet for details on power-down modes + * | | |Valid values are: + * | | |0 = Slow exit (DLL off) + * | | |1 = Fast exit (DLL on) + * @var DDRPHY_T::MR1 + * Offset: 0x58 Mode Register 1 (MR1) + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[0] |DE |DLL Enable/Disable + * | | |Enable (0) or disable (1) the DLL. DLL must be enabled for normal operation. + * | | |Note: SDRAM DLL off mode is not supported + * |[1] |DIC0 |Output Driver Impedance Control + * | | |Controls the output drive strength. Valid values are: + * | | |00 = RZQ/6 + * | | |01 = RZQ7 + * | | |10 = Reserved + * | | |11 = Reserved + * |[2] |RTT0 |On Die Termination + * | | |Selects the effective resistance for SDRAM on die termination. Valid values are: + * | | |000 = ODT disabled + * | | |001 = RZQ/4 + * | | |010 = RZQ/2 + * | | |011 = RZQ/6 + * | | |100 = RZQ/12 + * | | |101 = RZQ/8 + * | | |All other settings are reserved and should not be used. + * |[4:3] |AL |Posted CAS Additive Latency + * | | |Setting additive latency that allows read and write commands to be issued to the SDRAM earlier than normal (refer to the SDRAM Datasheet for details) + * | | |Valid values are: + * | | |00 = 0 (AL disabled) + * | | |01 = CL - 1 + * | | |10 = CL - 2 + * | | |11 = Reserved + * |[5] |DIC1 |Output Driver Impedance Control + * | | |Controls the output drive strength. Valid values are: + * | | |00 = RZQ/6 + * | | |01 = RZQ7 + * | | |10 = Reserved + * | | |11 = Reserved + * |[6] |RTT1 |On Die Termination + * | | |Selects the effective resistance for SDRAM on die termination. Valid values are: + * | | |000 = ODT disabled + * | | |001 = RZQ/4 + * | | |010 = RZQ/2 + * | | |011 = RZQ/6 + * | | |100 = RZQ/12 + * | | |101 = RZQ/8 + * | | |All other settings are reserved and should not be used. + * |[7] |LEVEL |Write Leveling Enable + * | | |Enables write-leveling when set. + * |[9] |RTT2 |On Die Termination + * | | |Selects the effective resistance for SDRAM on die termination. Valid values are: + * | | |000 = ODT disabled + * | | |001 = RZQ/4 + * | | |010 = RZQ/2 + * | | |011 = RZQ/6 + * | | |100 = RZQ/12 + * | | |101 = RZQ/8 + * | | |All other settings are reserved and should not be used. + * |[11] |TDQS |Termination Data Strobe + * | | |When enabled ('1') TDQS provides additional termination resistance outputs that may be useful in some system configurations + * | | |Refer to the SDRAM Datasheet for details. + * |[12] |QOFF |Output Enable/Disable + * | | |When '0', all outputs function normal; when '1' all SDRAM outputs are disabled removing output buffer current + * | | |This feature is intended to be used for IDD characterization of read current and should not be used in normal operation. + * @var DDRPHY_T::MR2 + * Offset: 0x5C Mode Register 2/Extended Mode Register 2 (MR2/EMR2) + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[2:0] |PASR |Partial Array Self Refresh + * | | |Specifies that data located in areas of the array beyond the specified location will be lost if self refresh is entered. + * | | |Valid settings for 4 banks are: + * | | |000 = Full Array + * | | |001 = Half Array (BA[1:0] = 00 & 01) + * | | |010 = Quarter Array (BA[1:0] = 00) + * | | |011 = Not defined + * | | |100 = 3/4 Array (BA[1:0] = 01, 10, & 11) + * | | |101 = Half Array (BA[1:0] = 10 & 11) + * | | |110 = Quarter Array (BA[1:0] = 11) + * | | |111 = Not defined + * | | |Valid settings for 8 banks are: + * | | |000 = Full Array + * | | |001 = Half Array (BA[2:0] = 000, 001, 010 & 011) + * | | |010 = Quarter Array (BA[2:0] = 000, 001) + * | | |011 = 1/8 Array (BA[2:0] = 000) + * | | |100 = 3/4 Array (BA[2:0] = 010, 011, 100, 101, 110 & 111) + * | | |101 = Half Array (BA[2:0] = 100, 101, 110 & 111) + * | | |110 = Quarter Array (BA[2:0] = 110 & 111) + * | | |111 = 1/8 Array (BA[2:0] 111) + * |[5:3] |CWL |CAS Write Latency + * | | |The delay between when the SDRAM registers a write command to when write data is available + * | | |Valid values are: + * | | |000 = 5 (tCK > 2.5ns) + * | | |001 = 6 (2.5ns > tCK > 1.875ns) + * | | |010 = 7 (1.875ns > tCK> 1.5ns) + * | | |011 = 8 (1.5ns > tCK > 1.25ns) + * | | |100 = 9 (1.25ns > tCK > 1.07ns) + * | | |101 = 10 (1.07ns > tCK > 0.935ns) + * | | |110 = 11 (0.935ns > tCK > 0.833ns) + * | | |111 = 12 (0.833ns > tCK > 0.75ns) + * | | |All other settings are reserved and should not be used. + * |[6] |ASR |Auto Self-Refresh + * | | |When enabled ('1'), SDRAM automatically provides self-refresh power management functions for all supported operating temperature values + * | | |Otherwise the SRT bit must be programmed to indicate the temperature range. + * |[7] |SRT |Self-Refresh Temperature Range + * | | |Selects either normal ('0') or extended ('1') operating temperature range during self-refresh. + * |[10:9] |RTTWR |Dynamic ODT + * | | |Selects RTT for dynamic ODT. Valid values are: + * | | |00 = Dynamic ODT off + * | | |01 = RZQ/4 + * | | |10 = RZQ/2 + * | | |11 = Reserved + * @var DDRPHY_T::MR3 + * Offset: 0x60 Mode Register 3 (MR3) + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[1:0] |MPRLOC |Multi-Purpose Register Location + * | | |Selects MPR data location: Valid value are: + * | | |00 = Predefined pattern for system calibration + * | | |All other settings are reserved and should not be used. + * |[2] |MPR |Multi-Purpose Register Enable + * | | |Enables, if set, that read data should come from the Multi-Purpose Register + * | | |Otherwise read data come from the DRAM array. + * @var DDRPHY_T::ODTCR + * Offset: 0x64 ODT Configuration Register (ODTCR) + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[3:0] |RDODT0 |Write ODT + * | | |Specifies whether ODT should be enabled ('1') or disabled ('0') on each of the up to four ranks when a write command is sent to rank n + * | | |WRODT0, WRODT1, WRODT2, and WRODT3 specify ODT settings when a write is to rank 0, rank 1, rank 2, and rank 3, respectively + * | | |The four bits of each field each represent a rank, the LSB being rank 0 and the MSB being rank 3 + * | | |Default is to enable ODT only on rank being written to. + * |[7:4] |RDODT1 |Write ODT + * | | |Specifies whether ODT should be enabled ('1') or disabled ('0') on each of the up to four ranks when a write command is sent to rank n + * | | |WRODT0, WRODT1, WRODT2, and WRODT3 specify ODT settings when a write is to rank 0, rank 1, rank 2, and rank 3, respectively + * | | |The four bits of each field each represent a rank, the LSB being rank 0 and the MSB being rank 3 + * | | |Default is to enable ODT only on rank being written to. + * |[11:8] |RDODT2 |Write ODT + * | | |Specifies whether ODT should be enabled ('1') or disabled ('0') on each of the up to four ranks when a write command is sent to rank n + * | | |WRODT0, WRODT1, WRODT2, and WRODT3 specify ODT settings when a write is to rank 0, rank 1, rank 2, and rank 3, respectively + * | | |The four bits of each field each represent a rank, the LSB being rank 0 and the MSB being rank 3 + * | | |Default is to enable ODT only on rank being written to. + * |[15:12] |RDODT3 |Write ODT + * | | |Specifies whether ODT should be enabled ('1') or disabled ('0') on each of the up to four ranks when a write command is sent to rank n + * | | |WRODT0, WRODT1, WRODT2, and WRODT3 specify ODT settings when a write is to rank 0, rank 1, rank 2, and rank 3, respectively + * | | |The four bits of each field each represent a rank, the LSB being rank 0 and the MSB being rank 3 + * | | |Default is to enable ODT only on rank being written to. + * |[19:16] |WRODT0 |Read ODT + * | | |Specifies whether ODT should be enabled ('1') or disabled ('0') on each of the up to four ranks when a read command is sent to rank n + * | | |RDODT0, RDODT1, RDODT2, and RDODT3 specify ODT settings when a read is to rank 0, rank 1, rank 2, and rank 3, respectively + * | | |The four bits of each field each represent a rank, the LSB being rank 0 and the MSB being rank 3 + * | | |Default is to disable ODT during reads + * |[23:20] |WRODT1 |Read ODT + * | | |Specifies whether ODT should be enabled ('1') or disabled ('0') on each of the up to four ranks when a read command is sent to rank n + * | | |RDODT0, RDODT1, RDODT2, and RDODT3 specify ODT settings when a read is to rank 0, rank 1, rank 2, and rank 3, respectively + * | | |The four bits of each field each represent a rank, the LSB being rank 0 and the MSB being rank 3 + * | | |Default is to disable ODT during reads + * |[27:24] |WRODT2 |Read ODT + * | | |Specifies whether ODT should be enabled ('1') or disabled ('0') on each of the up to four ranks when a read command is sent to rank n + * | | |RDODT0, RDODT1, RDODT2, and RDODT3 specify ODT settings when a read is to rank 0, rank 1, rank 2, and rank 3, respectively + * | | |The four bits of each field each represent a rank, the LSB being rank 0 and the MSB being rank 3 + * | | |Default is to disable ODT during reads + * |[31:28] |WRODT3 |Read ODT + * | | |Specifies whether ODT should be enabled ('1') or disabled ('0') on each of the up to four ranks when a read command is sent to rank n + * | | |RDODT0, RDODT1, RDODT2, and RDODT3 specify ODT settings when a read is to rank 0, rank 1, rank 2, and rank 3, respectively + * | | |The four bits of each field each represent a rank, the LSB being rank 0 and the MSB being rank 3 + * | | |Default is to disable ODT during reads + * @var DDRPHY_T::DTCR + * Offset: 0x68 Data Training Configuration Register (DTCR) + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[11:0] |DTCOL |Data Training Column Address + * | | |Selects the SDRAM column address to be used during data training + * | | |The lower four bits of this address must always be "000". + * |[27:12] |DTROW |Data Training Row Address + * | | |Selects the SDRAM row address to be used during data training. + * |[30:28] |DTBANK |Data Training Bank Address + * | | |Selects the SDRAM bank address to be used during data training. + * @var DDRPHY_T::DTAR0 + * Offset: 0x6C Data Training Address Register 0 (DTAR0) + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * @var DDRPHY_T::DTAR1 + * Offset: 0x70 Data Training Address Register 1 (DTAR1) + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[11:0] |DTCOL |Data Training Column Address + * | | |Selects the SDRAM column address to be used during data training + * | | |The lower four bits of this address must always be "000". + * |[27:12] |DTROW |Data Training Row Address + * | | |Selects the SDRAM row address to be used during data training. + * |[30:28] |DTBANK |Data Training Bank Address + * | | |Selects the SDRAM bank address to be used during data training. + * @var DDRPHY_T::DTAR2 + * Offset: 0x74 Data Training Address Register 2 (DTAR2) + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[11:0] |DTCOL |Data Training Column Address + * | | |Selects the SDRAM column address to be used during data training + * | | |The lower four bits of this address must always be "000". + * |[27:12] |DTROW |Data Training Row Address + * | | |Selects the SDRAM row address to be used during data training. + * |[30:28] |DTBANK |Data Training Bank Address + * | | |Selects the SDRAM bank address to be used during data training. + * @var DDRPHY_T::DTAR3 + * Offset: 0x78 Data Training Address Register 3 (DTAR3) + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[11:0] |DTCOL |Data Training Column Address + * | | |Selects the SDRAM column address to be used during data training + * | | |The lower four bits of this address must always be "000". + * |[27:12] |DTROW |Data Training Row Address + * | | |Selects the SDRAM row address to be used during data training. + * |[30:28] |DTBANK |Data Training Bank Address + * | | |Selects the SDRAM bank address to be used during data training. + * @var DDRPHY_T::DTDR0 + * Offset: 0x7C Data Training Data Register 0 (DTDR0) + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[7:0] |DTBYTE1 |Data Training Data + * | | |The first 4 bytes of data used during data training + * | | |This same data byte is used for each Byte Lane + * | | |Default sequence is a walking 1 while toggling data every data cycle. + * |[15:8] |DTBYTE0 |Data Training Data + * | | |The first 4 bytes of data used during data training + * | | |This same data byte is used for each Byte Lane + * | | |Default sequence is a walking 1 while toggling data every data cycle. + * |[23:16] |DTBYTE2 |Data Training Data + * | | |The first 4 bytes of data used during data training + * | | |This same data byte is used for each Byte Lane + * | | |Default sequence is a walking 1 while toggling data every data cycle. + * |[31:24] |DTBYTE3 |Data Training Data + * | | |The first 4 bytes of data used during data training + * | | |This same data byte is used for each Byte Lane + * | | |Default sequence is a walking 1 while toggling data every data cycle. + * @var DDRPHY_T::DTDR1 + * Offset: 0x80 Data Training Data Register 1 (DTDR1) + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[7:0] |DTBYTE4 |Data Training Data + * | | |The second 4 bytes of data used during data training + * | | |This same data byte is used for each Byte Lane + * | | |Default sequence is a walking 1 while toggling data every data cycle. + * |[15:8] |DTBYTE5 |Data Training Data + * | | |The second 4 bytes of data used during data training + * | | |This same data byte is used for each Byte Lane + * | | |Default sequence is a walking 1 while toggling data every data cycle. + * |[23:16] |DTBYTE6 |Data Training Data + * | | |The second 4 bytes of data used during data training + * | | |This same data byte is used for each Byte Lane + * | | |Default sequence is a walking 1 while toggling data every data cycle. + * |[31:24] |DTBYTE7 |Data Training Data + * | | |The second 4 bytes of data used during data training + * | | |This same data byte is used for each Byte Lane + * | | |Default sequence is a walking 1 while toggling data every data cycle. + * @var DDRPHY_T::DTEDR0 + * Offset: 0x84 Data Training Eye Data Register 0 (DTEDR0) + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[7:0] |DTWLMN |Data Training WDQ LCDL Minimum. + * |[15:8] |DTWLMX |Data Training WDQ LCDL Maximum. + * |[23:16] |DTWBMN |Data Training Write BDL Shift Minimum. + * |[31:24] |DTWBMX |Data Training Write BDL Shift Maximum. + * @var DDRPHY_T::DTEDR1 + * Offset: 0x88 Data Training Eye Data Register 1 (DTEDR1) + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[7:0] |DTRLMN |Data Training RDQS LCDL Minimum. + * |[15:8] |DTRLMX |Data Training RDQS LCDL Maximum. + * |[23:16] |DTRBMN |Data Training Read BDL Shift Minimum. + * |[31:24] |DTRBMX |Data Training Read BDL Shift Maximum. + * @var DDRPHY_T::PGCR2 + * Offset: 0x8C PHY General Configuration Register 2 (PGCR2) + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[17:0] |tREFPRD |Refresh Period + * | | |Indicates the period, after which the PUB has to issue a refresh command to the SDRAM + * | | |This is derived from the maximum refresh interval from the Datasheet, tRFC(max) or REFI, divided by the clock cycle time + * | | |A further 400 clocks must be subtracted from the derived number to account for command flow and missed slots of refreshes in the internal PUB blocks + * | | |The default corresponds to DDR3 9*7.8us at 1066 MHz when a burst of 9 refreshes are issued at every refresh interval. + * |[18] |NOBUB |No Bubbles + * | | |Specified whether reads should be returned to the controller with no bubbles + * | | |Enabling no-bubble reads increases the read latency + * | | |Valid values are: + * | | |0 = Bubbles are allowed during reads + * | | |1 = Bubbles are not allowed during reads + * |[19] |FXDLAT |Fixed Latency + * | | |Specified whether all reads should be returned to the controller with a fixed read latency + * | | |Enabling fixed read latency increases the read latency + * | | |Valid values are: + * | | |0 = Disable fixed read latency + * | | |1 = Enable fixed read latency + * | | |Fixed read latency is calculated as (12 + (maximum DXnGTR.RxDGSL)/2) HDR + * | | |clock cycles + * |[27:20] |DTPMXTMR |Data Training PUB Mode Timer Exit + * | | |Specifies the number of controller clocks to wait when entering and exiting pub mode data training + * | | |The default value ensures controller refreshes do not cause memory model errors when entering and exiting data training + * | | |The value should be increased if controller initiated SDRAM ZQ short or long operation may occur just before or just after the execution of data training. + * |[28] |SHRAC |Shared-AC mode + * | | |Set to 1 to enable shared address/command mode with two independent data channels - available only if shared address/command mode support is compiled in. + * |[29] |ACPDDC |AC Power-Down with Dual Channels + * | | |Set to 1 to power-down address/command lane when both data channels are powered-down + * | | |Only valid in shared-AC mode. + * |[30] |LPMSTRC0 |Low-Power Master Channel 0 + * | | |Set to 1 to have channel 0 act as master to drive channel 1 low-power functions simultaneously + * | | |Only valid in shared-AC mode. + * |[31] |DYNACPDD |Dynamic AC Power Down Driver + * | | |Powers down, when set, the output driver on I/O for ADDR and BA + * | | |This bit is ORed with bit ACIOCR[3] (ACPDD). + * | | |Note: Asserting PDD puts the IO driver cell into a lower power, lower speed mode of operation + * | | |However, it will still drive if its OE is asserted + * | | |ODT will be disabled (if used) + * | | |Asserting PDD does not prevent the IO from driving. + * @var DDRPHY_T::RDIMMGCR0 + * Offset: 0xB0 RDIMM General Configuration Register 0 (RDIMMGCR0) 123 + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[0] |RDIMM |Registered DIMM + * | | |Indicates, if set, that a registered DIMM is used + * | | |In this case, the PUB increases the SDRAM write and read latencies (WL/RL) by 1 and also enforces that accesses adhere to RDIMM buffer chip + * | | |This only applies to PUB internal SDRAM transactions + * | | |Transactions generated by the controller must make its own adjustments to WL/RL when using a registered DIMM + * | | |The DCR.NOSRA register bit must be set to '1' if using the standard RDIMM buffer chip so that normal DRAM accesses do not assert multiple chip select bits at the same time. + * |[1] |ERRNOREG |Parity Error No Registering + * | | |Indicates, if set, that parity error signal from the RDIMM should be passed to the DFI controller without any synchronization or registering + * |[2] |SOPERR |Stop On Parity Error + * | | |Indicates, if set, that the PUB is to stop driving commands to the DRAM upon encountering a parity error + * | | |Transactions can resume only after status is cleared via PIR.CLRSR. + * |[14] |PARINODT |PAR_IN On-Die Termination + * | | |Enables, when set, the on-die termination on the I/O for PAR_IN pin. + * |[15] |PARINPDD |PAR_IN Power Down Driver + * | | |Powers down, when set, the output driver on the I/O for PAR_IN pin. + * |[16] |PARINPDR |PAR_IN Power Down Receiver + * | | |Powers down, when set, the input receiver on the I/O for PAR_IN pin. + * |[17] |PARINIOM |PAR_IN I/O Mode + * | | |Selects SSTL mode (when set to 0) or CMOS mode (when set to 1) of the I/O for PAR_IN pin. + * |[18] |PARINOE |PAR_IN Output Enable + * | | |Enables, when set, the output driver on the I/O for PAR_IN pin. + * |[19] |ERROUTODT |ERROUT# On-Die Termination + * | | |Enables, when set, the on-die termination on the I/O for ERROUT# pin. + * |[20] |ERROUTPDD |ERROUT# Power Down Driver + * | | |Powers down, when set, the output driver on the I/O for ERROUT# pin. + * |[21] |ERROUTPDR |ERROUT# Power Down Receiver + * | | |Powers down, when set, the input receiver on the I/O for ERROUT# pin. + * |[22] |ERROUTIOM |ERROUT# I/O Mode + * | | |Selects SSTL mode (when set to 0) or CMOS mode (when set to 1) of the I/O for ERROUT# pin. + * |[23] |ERROUTOE |ERROUT# Output Enable + * | | |Enables, when set, the output driver on the I/O for ERROUT# pin. + * |[24] |RDIMMODT |RDIMM Outputs On-Die Termination + * | | |Enables, when set, the on-die termination on the I/O for QCSEN# and MIRROR pins. + * |[25] |RDIMMPDD |RDIMM Outputs Power Down Driver + * | | |Powers down, when set, the output driver on the I/O for QCSEN# and MIRROR pins. + * |[26] |RDIMMPDR |RDIMM Outputs Power Down Receiver + * | | |Powers down, when set, the input receiver on the I/O for QCSEN# and MIRROR pins. + * |[27] |RDIMMIOM |RDIMM Outputs I/O Mode + * | | |Selects SSTL mode (when set to 0) or CMOS mode (when set to 1) of the I/O for QCSEN# and MIRROR pins. + * |[28] |QCSENOE |QCSEN# Output Enable + * | | |Enables, when set, the output driver on the I/O for QCSEN# pin. + * |[29] |MIRROROE |MIRROR Output Enable + * | | |Enables, when set, the output driver on the I/O for MIRROR pin. + * |[30] |QCSEN |RDMIMM Quad CS Enable + * | | |Enables, if set, the Quad CS mode for the RDIMM registering buffer chip + * | | |This register bit controls the buffer chip QCSEN# signal. + * |[31] |MIRROR |RDIMM Mirror + * | | |Selects between two different ballouts of the RDIMM buffer chip for front or back operation + * | | |This register bit controls the buffer chip MIRROR signal. + * @var DDRPHY_T::RDIMMGCR1 + * Offset: 0xB4 RDIMM General Configuration Register 1 (RDIMMGCR1) + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[11:0] |tBCSTAB |Stabilization time + * | | |Number of DRAM clock cycles for the RDIMM buffer chip to stabilize + * | | |This parameter corresponds to the buffer chip tSTAB parameter + * | | |Default value is in decimal format and corresponds to 6us at 533 MHz. + * |[14:12] |tBCMRD |Command word to command word programming delay + * | | |Number of DRAM clock cycles between two RDIMM buffer chip command programming accesses + * | | |The value used for tBCMRD is 8 plus the value programmed in these bits, i.e + * | | |tBCMRD value ranges from 8 to 15 + * | | |This parameter corresponds to the buffer chip tMRD parameter. + * |[31:16] |CRINIT |Control Registers Initialization Enable + * | | |Indicates which RDIMM buffer chip control registers (RC0 to RC15) should be initialized (written) when the PUB is triggered to initialize the buffer chip + * | | |A setting of '1' on CRINIT[n] bit means that CRn should be written during initialization. + * @var DDRPHY_T::RDIMMCR0 + * Offset: 0xB8 RDIMM Control Register 0 (RDIMMCR0) + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[3:0] |RC0 |Control Word 0 + * | | |Bit definitions are: + * | | |RC0[0]: 0 = Output inversion enabled, 1 = Output inversion disabled. + * | | |RC0[1]: 0 = Floating outputs disabled, 1 = Floating outputs enabled. + * | | |RC0[2]: 0 = A outputs enabled, 1 = A outputs disabled. + * | | |RC0[3]: 0 = B outputs enabled, 1 = B outputs disabled. + * |[7:4] |RC1 |Control Word 1 + * | | |Bit definitions are: + * | | |RC1[0]: 0 = Y0/Y0# clock enabled, 1 = Y0/Y0# clock disabled. + * | | |RC1[1]: 0 = Y1/Y1# clock enabled, 1 = Y1/Y1# clock disabled. + * | | |RC1[2]: 0 = Y2/Y2# clock enabled, 1 = Y2/Y2# clock disabled. + * | | |RC1[3]: 0 = Y3/Y3# clock enabled, 1 = Y3/Y3# clock disabled. + * |[11:8] |RC2 |Control Word 2 + * | | |Bit definitions are: + * | | |RC2[0]: 0 = Standard (1/2 clock) pre-launch, 1 = Prelaunch controlled by RC1. + * | | |RC2[1]: 0 = Reserved. + * | | |RC2[2]: 0 = 100 Ohm input bus termination, 1 = 150 Ohm input bus termination. + * | | |RC2[3]: 0 = Operation frequency band 1, 1 = Test mode frequency band 2. + * |[15:12] |RC3 |Control Word 3 + * | | |RC3[1:0] is driver settings for command/address A outputs, and RC3[3:2] is driver settings for command/address B outputs + * | | |Bit definitions are: + * | | |00 = Light drive (4 or 5 DRAM loads) + * | | |01 = Moderate drive (8 or 10 DRAM loads) + * | | |10 = Strong drive (16 or 20 DRAM loads) + * | | |11 = Reserved + * |[19:16] |RC4 |Control Word 4 + * | | |RC4[1:0] is driver settings for control A outputs, and RC4[3:2] is driver settings for control B outputs + * | | |Bit definitions are: + * | | |00 = Light drive (4 or 5 DRAM loads) + * | | |01 = Moderate drive (8 or 10 DRAM loads) + * | | |10 = Reserved + * | | |11 = Reserved + * |[23:20] |RC5 |Control Word 5 + * | | |RC5[1:0] is driver settings for clock Y1, Y1#, Y3, and Y3# outputs, and RC5[3:2] is driver settings for clock Y0, Y0#, Y2, and Y2# outputs + * | | |Bit definitions are: + * | | |00 = Light drive (4 or 5 DRAM loads) + * | | |01 = Moderate drive (8 or 10 DRAM loads) + * | | |10 = Strong drive (16 or 20 DRAM loads) + * | | |11 = Reserved + * |[27:24] |RC6 |Control Word 6 + * | | |Reserved, free to use by vendor. + * |[31:28] |RC7 |Control Word 7 + * | | |Reserved, free to use by vendor. + * @var DDRPHY_T::RDIMMCR1 + * Offset: 0xBC RDIMM Control Register 1 (RDIMMCR1) + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[3:0] |RC8 |Control Word 8 + * | | |RC8[2:0] is Input Bus Termination (IBT) setting as follows: + * | | |000 = IBT as defined in RC2. + * | | |001 = Reserved + * | | |010 = 200 Ohm + * | | |011 = Reserved + * | | |100 = 300 Ohm + * | | |101 = Reserved + * | | |110 = Reserved + * | | |111 = Off + * | | |RC8[3]: 0 = IBT off when MIRROR is HIGH, 1 = IBT on when MIRROR is high + * |[7:4] |RC9 |Control Word 9 + * | | |Bit definitions are: + * | | |RC9[0]: 0 = Floating outputs as defined in RC0, 1 = Weak drive enabled. + * | | |RC9[1]: 0 = Reserved. + * | | |RC9[2]: 0 = CKE power down with IBT ON, QxODT is a function of DxODT, 1 = CKE power down with IBT off, QxODT held LOW + * | | |RC9[2] is valid only when RC9[3] is 1. + * | | |RC9[3]: 0 = CKE Power-down mode disabled, 1 = CKE Power-down mode enabled. + * |[11:8] |RC10 |Control Word 10 + * | | |RC10[2:0] is RDIMM operating speed setting as follows: + * | | |000 = DDR3/DDR3L-800 + * | | |001 = DDR3/DDR3L-1066 + * | | |010 = DDR3/DDR3L-1333 + * | | |011 = DDR3/DDR3L-1600 + * | | |100 = Reserved + * | | |101 = Reserved + * | | |110 = Reserved + * | | |111 = Reserved + * | | |RC10[3]: Don't care. + * |[15:12] |RC11 |Control Word 11 + * | | |RC10[1:0] is VDD operating voltage setting as follows: + * | | |00 = DDR3 1.5V mode + * | | |01 = DDR3L 1.35V mode + * | | |10 = Reserved + * | | |11 = Reserved + * | | |RC10[3:2]: Reserved. + * |[19:16] |RC12 |Control Word 12 + * | | |Reserved for future use. + * |[23:20] |RC13 |Control Word 13 + * | | |Reserved for future use. + * |[27:24] |RC14 |Control Word 14 + * | | |Reserved for future use + * |[31:28] |RC15 |Control Word 15 + * | | |Reserved for future use + * @var DDRPHY_T::DCUAR + * Offset: 0xC0 DCU Address Register (DCUAR) + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[3:0] |CWADDR |Cache Word Address + * | | |Address of the cache word to be accessed. + * |[7:4] |CSADDR |Cache Slice Address + * | | |Address of the cache slice to be accessed. + * |[9:8] |CSEL |Cache Select + * | | |Selects the cache to be accessed. Valid values are: + * | | |00 = Command cache + * | | |01 = Expected data cache + * | | |10 = Read data cache + * | | |11 = Reserved + * |[10] |INCA |Increment Address + * | | |Specifies, if set, that the cache address specified in WADDR and SADDR should be automatically incremented after each access of the cache + * | | |The increment happens in such a way that all the slices of a selected word are first accessed before going to the next word. + * |[11] |ATYPE |Access Type + * | | |Specifies the type of access to be performed using this address. Valid values are: + * | | |0 = Write access + * | | |1 = Read access + * @var DDRPHY_T::DCUDR + * Offset: 0xC4 DCU Data Register (DCUDR) + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[31:0] |CDATA |Cache Data + * | | |Data to be written to or read from a cache + * | | |This data corresponds to the cache word slice specified by the DCU Address Register. + * @var DDRPHY_T::DCURR + * Offset: 0xC8 DCU Run Register (DCURR) + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[3:0] |DINST |DCU Instruction + * | | |Selects the DCU command to be executed: Valid values are: + * | | |0000 = NOP: No operation + * | | |0001 = Run: Triggers the execution of commands in the command cache. + * | | |0010 = Stop: Stops the execution of commands in the command cache. + * | | |0011 = Stop Loop: Stops the execution of an infinite loop in the command cache. + * | | |0100 = Reset: Resets all DCU run time registers. See "DCU Status" for details. + * | | |0101 - 1111 Reserved + * |[7:4] |SADDR |Start Address + * | | |Cache word address where the execution of commands should begin. + * |[11:8] |EADDR |End Address + * | | |Cache word address where the execution of command should end. + * |[19:12] |NFAIL |Number of Failures + * | | |Specifies the number of failures after which the execution of commands and the capture of read data should stop if SONF bit of this register is set + * | | |Execution of commands and the capture of read data will stop after (NFAIL+1) failures if SONF is set. + * | | |Valid values are from 0 to 254. + * |[20] |SONF |Stop On Nth Fail + * | | |Specifies, if set, that the execution of commands and the capture of read data should stop when there are N read data failures + * | | |The number of failures is specified by NFAIL + * | | |Otherwise commands execute until the end of the program or until manually stopped using a STOP command. + * |[21] |SCOF |Stop Capture On Full + * | | |Specifies, if set, that the capture of read data should stop when the capture cache is full. + * |[22] |RCEN |Read Capture Enable + * | | |Indicates, if set, that read data coming back from the SDRAM should be captured into the read data cache. + * |[23] |XCEN |Expected Compare Enable + * | | |Indicates, if set, that read data coming back from the SDRAM should be should be compared with the expected data. + * @var DDRPHY_T::DCULR + * Offset: 0xCC DCU Loop Register (DCULR) + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[3:0] |LSADDR |Loop Start Address + * | | |Command cache word address where the loop should start. + * |[7:4] |LEADDR |Loop End Address + * | | |Command cache word address where the loop should end. + * |[15:8] |LCNT |Loop Count + * | | |The number of times that the loop should be executed if LINF is not set. + * |[16] |LINF |Loop Infinite + * | | |Indicates, if set, that the loop should be executed indefinitely until stopped by the STOP command + * | | |Otherwise the loop is execute LCNT times. + * |[17] |IDA |Increment DRAM Address + * | | |Indicates, if set, that DRAM addresses should be incremented every time a DRAM read/write command inside the loop is executed. + * |[31:28] |XLEADDR |Expected Data Loop End Address + * | | |The last expected data cache word address that contains valid expected data + * | | |Expected data should be looped between 0 and this address. + * | | |XLEADDR field uses only the following bits based on the cache depth: + * | | |DCU expected data cache = 4, XLEADDR[1:0] + * | | |DCU expected data cache = 8, XLEADDR[2:0] + * | | |DCU expected data cache = 16, XLEADDR[3:0] + * @var DDRPHY_T::DCUGCR + * Offset: 0xD0 DCU General Configuration Register (DCUGCR) + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[15:0] |RCSW |Read Capture Start Word + * | | |The capture and compare of read data should start after Nth word + * | | |For example setting this value to 12 will skip the first 12 read data. + * @var DDRPHY_T::DCUTPR + * Offset: 0xD4 DCU Timing Parameter Register (DCUTPR) + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[7:0] |tDCUT0 |DCU Generic Timing Parameter 0 + * |[15:8] |tDCUT1 |DCU Generic Timing Parameter 1 + * |[23:16] |tDCUT2 |DCU Generic Timing Parameter 2 + * |[31:24] |tDCUT3 |DCU Generic Timing Parameter 3 + * @var DDRPHY_T::DCUSR0 + * Offset: 0xD8 DCU Status Register 0 (DCUSR0) + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[0] |RDONE |Run Done + * | | |Indicates, if set, that the DCU has finished executing the commands in the command cache + * | | |This bit is also set to indicate that a STOP command has successfully been executed and command execution has stopped. + * |[1] |CFAIL |Capture Fail + * | | |Indicates, if set, that at least one read data word has failed. + * |[2] |CFULL |Capture Full + * | | |Indicates, if set, that the capture cache is full. + * @var DDRPHY_T::DCUSR1 + * Offset: 0xDC DCU Status Register 1 (DCUSR1) + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[15:0] |RDCNT |Read Count + * | | |Number of read words returned from the SDRAM. + * |[23:16] |FLCNT |Fail Count + * | | |Number of read words that have failed. + * |[31:24] |LPCNT |Loop Count + * | | |Indicates the value of the loop count + * | | |This is useful when the program has stopped because of failures to assess how many reads were executed before first fail. + * @var DDRPHY_T::BISTRR + * Offset: 0x100 BIST Run Register (BISTRR) + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[2:0] |BINST |BIST Instruction + * | | |Selects the BIST instruction to be executed: Valid values are: + * | | |000 = NOP: No operation + * | | |001 = Run: Triggers the running of the BIST. + * | | |010 = Stop: Stops the running of the BIST. + * | | |011 = Reset: Resets all BIST run-time registers, such as error counters. + * | | |100 - 111 Reserved + * |[3] |BMODE |BIST Mode + * | | |Selects the mode in which BIST is run. Valid values are: + * | | |0 = Loopback mode: Address, commands and data loop back at the PHY I/Os. + * | | |1 = DRAM mode: Address, commands and data go to DRAM for normal memory accesses. + * |[4] |BINF |BIST Infinite Run + * | | |Specifies, if set, that the BIST should be run indefinitely until when it is either stopped or a failure has been encountered + * | | |Otherwise BIST is run until number of BIST words specified in the BISTWCR register has been generated. + * |[12:5] |NFAIL |Number of Failures + * | | |Specifies the number of failures after which the execution of commands and the capture of read data should stop if BSONF bit of this register is set + * | | |Execution of commands and the capture of read data will stop after (NFAIL+1) failures if BSONF is set. + * |[13] |BSONF |BIST Stop On Nth Fail + * | | |Specifies, if set, that the BIST should stop when an nth data word or address/command comparison error has been encountered. + * |[14] |BDXEN |BIST DATX8 Enable + * | | |Enables the running of BIST on the data byte lane PHYs + * | | |This bit is exclusive with BACEN, i.e + * | | |both cannot be set to '1' at the same time. + * |[15] |BACEN |BIST AC Enable + * | | |Enables the running of BIST on the address/command lane PHY + * | | |This bit is exclusive with BDXEN, i.e + * | | |both cannot be set to '1' at the same time. + * |[16] |BDMEN |BIST Data Mask Enable + * | | |Enables, if set, that the data mask BIST should be included in the BIST run, i.e + * | | |data pattern generated and loopback data compared + * | | |This is valid only for loopback mode. + * |[18:17] |BDPAT |BIST Data Pattern + * | | |Selects the data pattern used during BIST. Valid values are: + * | | |00 = Walking 0 + * | | |01 = Walking 1 + * | | |10 = LFSR-based pseudo-random + * | | |11 = User programmable (Not valid for AC loopback). + * |[22:19] |BDXSEL |BIST DATX8 Select + * | | |Select the byte lane for comparison of loopback/read data. Valid values are 0 to 8. + * |[24:23] |BCKSEL |BIST CK Select + * | | |Selects the CK that should be used to register the AC loopback signals from the I/Os. Valid values are: + * | | |00 = CK[0] + * | | |01 = CK[1] + * | | |10 = CK[2] + * | | |11 = Reserved + * |[26:25] |BCCSEL |BIST Clock Cycle Select + * | | |Selects the clock numbers on which the AC loopback data is written into the FIFO + * | | |Data is written into the loopback FIFO once every four clock cycles + * | | |Valid values are: + * | | |00 = Clock cycle 0, 4, 8, 12, etc. + * | | |01 = Clock cycle 1, 5, 9, 13, etc. + * | | |10 = Clock cycle 2, 6, 10, 14, etc. + * | | |11 = Clock cycle 3, 7, 11, 15, etc. + * @var DDRPHY_T::BISTWCR + * Offset: 0x104 BIST Word Count Register (BISTWCR) + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[15:0] |BWCNT |BIST Word Count + * | | |Indicates the number of words to generate during BIST + * | | |This must be a multiple of DRAM burst length (BL) divided by 2, e.g + * | | |for BL=8, valid values are 4, 8, 12, 16, and so on. + * @var DDRPHY_T::BISTMSKR0 + * Offset: 0x108 BIST Mask Register 0 (BISTMSKR0) + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[15:0] |AMSK |Address Mask + * | | |Mask bit for each of the up to 16 address bits. + * |[18:16] |BAMSK |Bank Address Mask + * | | |Mask bit for each of the up to 3 bank address bits. + * |[19] |WEMSK |WE Mask + * | | |Mask bit for the WE#. + * |[23:20] |CKEMSK |CKE Mask + * | | |Mask bit for each of the up to 4 CKE bits. + * |[27:24] |CSMSK |CS Mask + * | | |Mask bit for each of the up to 4 CS# bits. + * |[31:28] |ODTMSK |ODT Mask + * | | |Mask bit for each of the up to 4 ODT bits. + * @var DDRPHY_T::BISTMSKR1 + * Offset: 0x10C BIST Mask Register 1 (BISTMSKR1) + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[0] |RASMSK |RAS Mask + * | | |Mask bit for the RAS. + * |[1] |CASMSK |CAS Mask + * | | |Mask bit for the CAS. + * |[27] |PARMSK |Mask bit for the PAR_IN + * | | |Only for DIMM parity support and only if the design is compiled for less than 3 ranks. + * |[31:28] |DMMSK |DM Mask + * | | |Mask bit for the data mask (DM) bit. + * @var DDRPHY_T::BISTMSKR2 + * Offset: 0x110 BIST Mask Register 2 (BISTMSKR2) + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[31:0] |DQMSK |DQ Mask + * | | |Mask bit for each of the 8 data (DQ) bits. + * @var DDRPHY_T::BISTLSR + * Offset: 0x114 BIST LFSR Seed Register (BISTLSR) + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[31:0] |SEED |LFSR seed + * | | |LFSR seed for pseudo-random BIST patterns. + * @var DDRPHY_T::BISTAR0 + * Offset: 0x118 BIST Address Register 0 (BISTAR0) + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[11:0] |BCOL |BIST Column Address + * | | |Selects the SDRAM column address to be used during BIST + * | | |The lower bits of this address must be "0000" for BL16, "000" for BL8, "00" for BL4 and "0" for BL2. + * |[27:12] |BROW |BIST Row Address + * | | |Selects the SDRAM row address to be used during BIST. + * |[30:28] |BBANK |BIST Bank Address + * | | |Selects the SDRAM bank address to be used during BIST. + * @var DDRPHY_T::BISTAR1 + * Offset: 0x11C BIST Address Register 1 (BISTAR1) + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[1:0] |BRANK |BIST Rank + * | | |Selects the SDRAM rank to be used during BIST. Valid values range from 0 to maximum ranks minus 1. + * |[3:2] |BMRANK |BIST Maximum Rank + * | | |Specifies the maximum SDRAM rank to be used during BIST + * | | |The default value is set to maximum ranks minus 1 + * | | |Example default shown here is for a 4-rank system + * |[15:4] |BAINC |BIST Address Increment + * | | |Selects the value by which the SDRAM address is incremented for each write/read access + * | | |This value must be at the beginning of a burst boundary, i.e + * | | |the lower bits must be "0000" for BL16, "000" for BL8, "00" for BL4 and "0" for BL2. + * @var DDRPHY_T::BISTAR2 + * Offset: 0x120 BIST Address Register 2 (BISTAR2) + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[11:0] |BMCOL |BIST Maximum Column Address + * | | |Specifies the maximum SDRAM column address to be used during BIST before the address increments to the next row. + * |[27:12] |BMROW |BIST Maximum Row Address + * | | |Specifies the maximum SDRAM row address to be used during BIST before the address increments to the next bank. + * |[30:28] |BMBANK |BIST Maximum Bank Address + * | | |Specifies the maximum SDRAM bank address to be used during BIST before the address increments to the next rank. + * @var DDRPHY_T::BISTUDPR + * Offset: 0x124 BIST User Data Pattern Register (BISTUDPR) + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[15:0] |BUDP0 |BIST User Data Pattern 0 + * | | |Data to be applied on even DQ pins during BIST. + * |[31:16] |BUDP1 |BIST User Data Pattern 1 + * | | |Data to be applied on odd DQ pins during BIST. + * @var DDRPHY_T::BISTGSR + * Offset: 0x128 BIST General Status Register (BISTGSR) + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[0] |BDONE |BIST Done + * | | |Indicates, if set, that the BIST has finished executing + * | | |This bit is reset to zero when BIST is triggered. + * |[1] |BACERR |BIST Address/Command Error + * | | |indicates, if set, that there is a data comparison error in the address/command lane. + * |[2] |BDXERR |BIST Data Error + * | | |indicates, if set, that there is a data comparison error in the byte lane. + * |[17:16] |PARBER |PAR_IN Bit Error + * | | |Indicates the number of bit errors on PAR_IN + * |[27:20] |DMBER |DM Bit Error + * | | |Indicates the number of bit errors on data mask (DM) bit + * | | |DMBER[1:0] are for even DQS cycles first DM beat, and DMBER[3:2] are for even DQS cycles second DM beat + * | | |Similarly, DMBER[5:4] are for odd DQS cycles first DM beat, and DMBER[7:6] are for odd DQS cycles second DM beat. + * |[29:28] |RASBER |RAS Bit Error + * | | |Indicates the number of bit errors on RAS. + * |[31:30] |CASBER |CAS Bit Error + * | | |Indicates the number of bit errors on CAS. + * @var DDRPHY_T::BISTWER + * Offset: 0x12C BIST Word Error Register (BISTWER) + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[15:0] |ACWER |Address/Command Word Error + * | | |Indicates the number of word errors on the address/command lane + * | | |An error on any bit of the address/command bus increments the error count. + * |[31:16] |DXWER |Byte Word Error + * | | |Indicates the number of word errors on the byte lane + * | | |An error on any bit of the data bus including the data mask bit increments the error count. + * @var DDRPHY_T::BISTBER0 + * Offset: 0x130 BIST Bit Error Register 0 (BISTBER0) + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[31:0] |ABER |Address Bit Error + * | | |Each group of two bits indicate the bit error count on each of the up to 16 address bits + * | | |[1:0] is the error count for A[0], [3:2] for A[1], and so on. + * @var DDRPHY_T::BISTBER1 + * Offset: 0x134 BIST Bit Error Register 1 (BISTBER1) + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[5:0] |BABER |Bank Address Bit Error + * | | |Each group of two bits indicate the bit error count on each of the up to 3 bank address bits + * | | |[1:0] is the error count for BA[0], [3:2] for BA[1], and so on. + * |[7:6] |WEBER |WE# Bit Error + * | | |Indicates the number of bit errors on WE#. + * |[15:8] |CKEBER |CKE Bit Error + * | | |Each group of two bits indicate the bit error count on each of the up to 4 CKE bits + * | | |[1:0] is the error count for CKE[0], [3:2] for CKE[1], and so on. + * |[23:16] |CSBER |CS# Bit Error + * | | |Each group of two bits indicate the bit error count on each of the up to 4 CS# bits + * | | |[1:0] is the error count for CS#[0], [3:2] for CS#[1], and so on. + * |[31:24] |ODTBER |ODT Bit Error + * | | |Each group of two bits indicates the bit error count on each of the up to 4 ODT bits + * | | |[1:0] is the error count for ODT[0], [3:2] for ODT[1], and so on. + * @var DDRPHY_T::BISTBER2 + * Offset: 0x138 BIST Bit Error Register 2 (BISTBER2) + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[31:0] |DQBER0 |Data Bit Error + * | | |The error count for even DQS cycles + * | | |The first 16 bits indicate the error count for the first data beat (i.e + * | | |the data driven out on DQ[7:0] on the rising edge of DQS) + * | | |The second 16 bits indicate the error on the second data beat (i.e + * | | |the error count of the data driven out on DQ[7:0] on the falling edge of DQS) + * | | |For each of the 16-bit group, the first 2 bits are for DQ[0], the second for DQ[1], and so on. + * @var DDRPHY_T::BISTBER3 + * Offset: 0x13C BIST Bit Error Register 3 (BISTBER3) + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[31:0] |DQBER1 |Data Bit Error + * | | |The error count for odd DQS cycles + * | | |The first 16 bits indicate the error count for the first data beat (i.e + * | | |the data driven out on DQ[7:0] on the rising edge of DQS) + * | | |The second 16 bits indicate the error on the second data beat (i.e + * | | |the error count of the data driven out on DQ[7:0] on the falling edge of DQS) + * | | |For each of the 16-bit group, the first 2 bits are for DQ[0], the second for DQ[1], and so on. + * @var DDRPHY_T::BISTWCSR + * Offset: 0x140 BIST Word Count Status Register (BISTWCSR) + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[15:0] |ACWCNT |Address/Command Word Count + * | | |Indicates the number of words received from the address/command lane. + * |[31:16] |DXWCNT |Byte Word Count + * | | |Indicates the number of words received from the byte lane. + * @var DDRPHY_T::BISTFWR0 + * Offset: 0x144 BIST Fail Word Register 0 (BISTFWR0) + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[15:0] |AWEBS |Address Word Error Bit Status + * | | |Bit status during a word error for each of the up to 16 address bits. + * |[18:16] |BAWEBS |Bank Address Word Error Bit Status + * | | |Bit status during a word error for each of the up to 3 bank address bits. + * |[19] |WEWEBS |WE Word Error Bit Status + * | | |Bit status during a word error for the WE#. + * |[23:20] |CKEWEBS |CKE Word Error Bit Status + * | | |Bit status during a word error for each of the up to 4 CKE bits. + * |[27:24] |CSWEBS |CS Word Error Bit Status + * | | |Bit status during a word error for each of the up to 4 CS# bits. + * |[31:28] |ODTWEBS |ODT Word Error Bit Status + * | | |Bit status during a word error for each of the up to 4 ODT bits. + * @var DDRPHY_T::BISTFWR1 + * Offset: 0x148 BIST Fail Word Register 1 (BISTFWR1) + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[0] |RASWEBS |RAS Word Error Bit Status + * | | |Bit status during a word error for the RAS. + * |[1] |CASWEBS |CAS Word Error Bit Status + * | | |Bit status during a word error for the CAS. + * |[26] |PARWEBS |PAR_IN Word Error Bit Status + * | | |Bit status during a word error for the PAR_IN. Only for DIMM parity support + * |[31:28] |DMWEBS |DM Word Error Bit Status + * | | |Bit status during a word error for the data mask (DM) bit + * | | |DMWEBS [0] is for the first DM beat, DMWEBS [1] is for the second DM beat, and so on. + * @var DDRPHY_T::BISTFWR2 + * Offset: 0x14C BIST Fail Word Register 2 (BISTFWR2) + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[31:0] |DQWEBS |DQ Word Error Bit Status + * | | |Bit status during a word error for each of the 8 data (DQ) bits + * | | |The first 8 bits indicate the status of the first data beat (i.e + * | | |the status of the data driven out on DQ[7:0] on the rising edge of DQS) + * | | |The second 8 bits indicate the status of the second data beat (i.e + * | | |the status of the data driven out on DQ[7:0] on the falling edge of DQS), and so on + * | | |For each of the 8-bit group, the first bit is for DQ[0], the second bit is for DQ[1], and so on. + * @var DDRPHY_T::AACR + * Offset: 0x174 Anti-Aging Control Register (AACR) + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[29:0] |AATR |Anti-Aging Toggle Rate + * | | |Defines the number of controller clock (ctl_clk) cycles after which the PUB will toggle the data going to DATX8 if the data channel between the controller/PUB and DATX8 has been idle for this long. + * | | |The default value corresponds to a toggling count of 4096 ctl_clk cycles + * | | |For a ctl_clk running at 533 MHz the toggle rate will be approximately 7.68us. + * | | |The default value may also be overridden by the macro + * | | |DWC_AACR_AATR_DFLT. + * |[30] |AAENC |Anti-Aging Enable Control + * | | |Enables, if set, the automatic toggling of the data going to the DATX8 when the data channel from the controller/PUB to DATX8 is idle for programmable number of clock cycles. + * |[31] |AAOENC |Anti-Aging PAD Output Enable Control + * | | |Enables, if set, anti-aging toggling on the pad output enable signal "ctl_oe_n" going into the DATX8s + * | | |This will increase power consumption for the anti-aging feature. + * @var DDRPHY_T::GPR0 + * Offset: 0x178 General Purpose Register 0 (GPR0) + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[31:0] |GPR0 |General Purpose Register 0 + * | | |General purpose register bits. + * @var DDRPHY_T::GPR1 + * Offset: 0x17C General Purpose Register 1 (GPR1) + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[31:0] |GPR1 |General Purpose Register 1 + * | | |General purpose register bits. + * @var DDRPHY_T::ZQ0CR0 + * Offset: 0x180 Impedance Control Register 0 (ZQnCR0) + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[27:0] |ZDATA |Impedance Over-Ride Data + * | | |Data used to directly drive the impedance control. + * | | |ZDATA field mapping for D3R I/O is as follows: + * | | |ZDATA[27:20] is reserved and returns zeros on reads. + * | | |ZDATA[19:15] is used to select the pull-up on-die termination impedance. + * | | |ZDATA[14:10] is used to select the pull-down on-die termination impedance. + * | | |ZDATA[9:5] is used to select the pull-up output impedance + * | | |ZDATA[4:0] is used to select the pull-down output impedance. + * | | |Note: The default value is 0x000014A for I/O type D3R. + * |[28] |ZDEN |Impedance Over-Ride Enable + * | | |When this bit is set, it allows users to directly drive the impedance control using the data programmed in the ZDATA field + * | | |Otherwise, the control is generated automatically by the impedance control logic. + * |[29] |ZCALBYP |Impedance Calibration Bypass + * | | |Bypasses, if set, impedance calibration of this ZQ control block when impedance calibration is already in progress + * | | |Impedance calibration can be disabled prior to trigger by using the ZCALEN bit. + * |[30] |ZCALEN |Impedance Calibration Enable + * | | |Enables, if set, the impedance calibration of this ZQ control block when impedance calibration is triggered using either the ZCAL bit of PIR register or the DFI update interface. + * |[31] |ZQPD |ZQ Power Down + * | | |Powers down, if set, the PZQ cell. + * @var DDRPHY_T::ZQ0CR1 + * Offset: 0x184 Impedance Control Register 1 (ZQnCR1) + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[7:0] |ZPROG |Impedance Divide Ratio + * | | |Selects the external resistor divide ratio to be used to set the output impedance and the on-die termination as follows: + * | | |ZPROG[7:4] = On-die termination divide select + * | | |ZPROG[3:0] = Output impedance divide select + * |[12] |DFICU0 |DFI Controller Update Interface 0 + * | | |Sets this impedance controller to be enabled for calibration when the DFI controller update interface 0 (channel 0) requests an update. + * |[13] |DFICU1 |DFI Controller Update Interface 1 + * | | |Sets this impedance controller to be enabled for calibration when the DFI controller update interface 1 (channel 1) requests an update + * | | |Only valid in shared-AC mode. + * |[14] |DFICCU |DFI Concurrent Controller Update Interface + * | | |Sets this impedance controller to be enabled for calibration when both of the DFI controller update interfaces request an update on the same clock + * | | |This provides the ability to enable impedance calibration updates for the Address/Command lane + * | | |Only valid in shared-AC mode. + * |[16] |DFIPU0 |DFI Update Interface 0 + * | | |Sets this impedance controller to be enabled for calibration when the DFI PHY update interface 0 (channel 0) requests an update. + * |[17] |DFIPU1 |DFI Update Interface 1 + * | | |Sets this impedance controller to be enabled for calibration when the DFI PHY update interface 1 (channel 1) requests an update + * | | |Only valid in shared-AC mode. + * @var DDRPHY_T::ZQ0SR0 + * Offset: 0x188 Impedance Status Register 0 (ZQnSR0) + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[27:0] |ZCTRL |Impedance Control + * | | |Current value of impedance control. + * | | |ZCTRL field mapping for D3R I/O is as follows: + * | | |ZCTRL[27:20] is reserved and returns zeros on reads. + * | | |ZCTRL[19:15] is used to select the pull-up on-die termination impedance. + * | | |ZCTRL[14:10] is used to select the pull-down on-die termination impedance. + * | | |ZCTRL[9:5] is used to select the pull-up output impedance. + * | | |ZCTRL[4:0] is used to select the pull-down output impedance. + * | | |Note: The default value is 0x000014A for I/O type D3R. + * |[30] |ZERR |Impedance Calibration Error + * | | |If set, indicates that there was an error during impedance calibration. + * |[31] |ZDONE |Impedance Calibration Done + * | | |Indicates that impedance calibration has completed. + * @var DDRPHY_T::ZQ0SR1 + * Offset: 0x18C Impedance Status Register 1 (ZQnSR1) + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[1:0] |ZPD |Output impedance pull-down calibration status + * | | |Valid status encodings are: + * | | |00 = Completed with no errors + * | | |01 = Overflow error + * | | |10 = Underflow error + * | | |11 = Calibration in progress + * |[3:2] |ZPU |Output impedance pull-up calibration status + * | | |Similar status encodings as ZPD. + * |[5:4] |OPD |On-die termination pull-down calibration status + * | | |Similar status encodings as ZPD. + * |[7:6] |OPU |On-die termination pull-up calibration status + * | | |Similar status encodings as ZPD. + * @var DDRPHY_T::ZQ1CR0 + * Offset: 0x190 Impedance Control Register 0 (ZQnCR0) + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[27:0] |ZDATA |Impedance Over-Ride Data + * | | |Data used to directly drive the impedance control. + * | | |ZDATA field mapping for D3R I/O is as follows: + * | | |ZDATA[27:20] is reserved and returns zeros on reads. + * | | |ZDATA[19:15] is used to select the pull-up on-die termination impedance. + * | | |ZDATA[14:10] is used to select the pull-down on-die termination impedance. + * | | |ZDATA[9:5] is used to select the pull-up output impedance + * | | |ZDATA[4:0] is used to select the pull-down output impedance. + * | | |Note: The default value is 0x000014A for I/O type D3R. + * |[28] |ZDEN |Impedance Over-Ride Enable + * | | |When this bit is set, it allows users to directly drive the impedance control using the data programmed in the ZDATA field + * | | |Otherwise, the control is generated automatically by the impedance control logic. + * |[29] |ZCALBYP |Impedance Calibration Bypass + * | | |Bypasses, if set, impedance calibration of this ZQ control block when impedance calibration is already in progress + * | | |Impedance calibration can be disabled prior to trigger by using the ZCALEN bit. + * |[30] |ZCALEN |Impedance Calibration Enable + * | | |Enables, if set, the impedance calibration of this ZQ control block when impedance calibration is triggered using either the ZCAL bit of PIR register or the DFI update interface. + * |[31] |ZQPD |ZQ Power Down + * | | |Powers down, if set, the PZQ cell. + * @var DDRPHY_T::ZQ1CR1 + * Offset: 0x194 Impedance Control Register 1 (ZQnCR1) + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[7:0] |ZPROG |Impedance Divide Ratio + * | | |Selects the external resistor divide ratio to be used to set the output impedance and the on-die termination as follows: + * | | |ZPROG[7:4] = On-die termination divide select + * | | |ZPROG[3:0] = Output impedance divide select + * |[12] |DFICU0 |DFI Controller Update Interface 0 + * | | |Sets this impedance controller to be enabled for calibration when the DFI controller update interface 0 (channel 0) requests an update. + * |[13] |DFICU1 |DFI Controller Update Interface 1 + * | | |Sets this impedance controller to be enabled for calibration when the DFI controller update interface 1 (channel 1) requests an update + * | | |Only valid in shared-AC mode. + * |[14] |DFICCU |DFI Concurrent Controller Update Interface + * | | |Sets this impedance controller to be enabled for calibration when both of the DFI controller update interfaces request an update on the same clock + * | | |This provides the ability to enable impedance calibration updates for the Address/Command lane + * | | |Only valid in shared-AC mode. + * |[16] |DFIPU0 |DFI Update Interface 0 + * | | |Sets this impedance controller to be enabled for calibration when the DFI PHY update interface 0 (channel 0) requests an update. + * |[17] |DFIPU1 |DFI Update Interface 1 + * | | |Sets this impedance controller to be enabled for calibration when the DFI PHY update interface 1 (channel 1) requests an update + * | | |Only valid in shared-AC mode. + * @var DDRPHY_T::ZQ1SR0 + * Offset: 0x198 Impedance Status Register 0 (ZQnSR0) + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[27:0] |ZCTRL |Impedance Control + * | | |Current value of impedance control. + * | | |ZCTRL field mapping for D3R I/O is as follows: + * | | |ZCTRL[27:20] is reserved and returns zeros on reads. + * | | |ZCTRL[19:15] is used to select the pull-up on-die termination impedance. + * | | |ZCTRL[14:10] is used to select the pull-down on-die termination impedance. + * | | |ZCTRL[9:5] is used to select the pull-up output impedance. + * | | |ZCTRL[4:0] is used to select the pull-down output impedance. + * | | |Note: The default value is 0x000014A for I/O type D3R. + * |[30] |ZERR |Impedance Calibration Error + * | | |If set, indicates that there was an error during impedance calibration. + * |[31] |ZDONE |Impedance Calibration Done + * | | |Indicates that impedance calibration has completed. + * @var DDRPHY_T::ZQ1SR1 + * Offset: 0x19C Impedance Status Register 1 (ZQnSR1) + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[1:0] |ZPD |Output impedance pull-down calibration status + * | | |Valid status encodings are: + * | | |00 = Completed with no errors + * | | |01 = Overflow error + * | | |10 = Underflow error + * | | |11 = Calibration in progress + * |[3:2] |ZPU |Output impedance pull-up calibration status + * | | |Similar status encodings as ZPD. + * |[5:4] |OPD |On-die termination pull-down calibration status + * | | |Similar status encodings as ZPD. + * |[7:6] |OPU |On-die termination pull-up calibration status + * | | |Similar status encodings as ZPD. + * @var DDRPHY_T::ZQ2CR0 + * Offset: 0x1A0 Impedance Control Register 0 (ZQnCR0) + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[27:0] |ZDATA |Impedance Over-Ride Data + * | | |Data used to directly drive the impedance control. + * | | |ZDATA field mapping for D3R I/O is as follows: + * | | |ZDATA[27:20] is reserved and returns zeros on reads. + * | | |ZDATA[19:15] is used to select the pull-up on-die termination impedance. + * | | |ZDATA[14:10] is used to select the pull-down on-die termination impedance. + * | | |ZDATA[9:5] is used to select the pull-up output impedance + * | | |ZDATA[4:0] is used to select the pull-down output impedance. + * | | |Note: The default value is 0x000014A for I/O type D3R. + * |[28] |ZDEN |Impedance Over-Ride Enable + * | | |When this bit is set, it allows users to directly drive the impedance control using the data programmed in the ZDATA field + * | | |Otherwise, the control is generated automatically by the impedance control logic. + * |[29] |ZCALBYP |Impedance Calibration Bypass + * | | |Bypasses, if set, impedance calibration of this ZQ control block when impedance calibration is already in progress + * | | |Impedance calibration can be disabled prior to trigger by using the ZCALEN bit. + * |[30] |ZCALEN |Impedance Calibration Enable + * | | |Enables, if set, the impedance calibration of this ZQ control block when impedance calibration is triggered using either the ZCAL bit of PIR register or the DFI update interface. + * |[31] |ZQPD |ZQ Power Down + * | | |Powers down, if set, the PZQ cell. + * @var DDRPHY_T::ZQ2CR1 + * Offset: 0x1A4 Impedance Control Register 1 (ZQnCR1) + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[7:0] |ZPROG |Impedance Divide Ratio + * | | |Selects the external resistor divide ratio to be used to set the output impedance and the on-die termination as follows: + * | | |ZPROG[7:4] = On-die termination divide select + * | | |ZPROG[3:0] = Output impedance divide select + * |[12] |DFICU0 |DFI Controller Update Interface 0 + * | | |Sets this impedance controller to be enabled for calibration when the DFI controller update interface 0 (channel 0) requests an update. + * |[13] |DFICU1 |DFI Controller Update Interface 1 + * | | |Sets this impedance controller to be enabled for calibration when the DFI controller update interface 1 (channel 1) requests an update + * | | |Only valid in shared-AC mode. + * |[14] |DFICCU |DFI Concurrent Controller Update Interface + * | | |Sets this impedance controller to be enabled for calibration when both of the DFI controller update interfaces request an update on the same clock + * | | |This provides the ability to enable impedance calibration updates for the Address/Command lane + * | | |Only valid in shared-AC mode. + * |[16] |DFIPU0 |DFI Update Interface 0 + * | | |Sets this impedance controller to be enabled for calibration when the DFI PHY update interface 0 (channel 0) requests an update. + * |[17] |DFIPU1 |DFI Update Interface 1 + * | | |Sets this impedance controller to be enabled for calibration when the DFI PHY update interface 1 (channel 1) requests an update + * | | |Only valid in shared-AC mode. + * @var DDRPHY_T::ZQ2SR0 + * Offset: 0x1A8 Impedance Status Register 0 (ZQnSR0) + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[27:0] |ZCTRL |Impedance Control + * | | |Current value of impedance control. + * | | |ZCTRL field mapping for D3R I/O is as follows: + * | | |ZCTRL[27:20] is reserved and returns zeros on reads. + * | | |ZCTRL[19:15] is used to select the pull-up on-die termination impedance. + * | | |ZCTRL[14:10] is used to select the pull-down on-die termination impedance. + * | | |ZCTRL[9:5] is used to select the pull-up output impedance. + * | | |ZCTRL[4:0] is used to select the pull-down output impedance. + * | | |Note: The default value is 0x000014A for I/O type D3R. + * |[30] |ZERR |Impedance Calibration Error + * | | |If set, indicates that there was an error during impedance calibration. + * |[31] |ZDONE |Impedance Calibration Done + * | | |Indicates that impedance calibration has completed. + * @var DDRPHY_T::ZQ2SR1 + * Offset: 0x1AC Impedance Status Register 1 (ZQnSR1) + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[1:0] |ZPD |Output impedance pull-down calibration status + * | | |Valid status encodings are: + * | | |00 = Completed with no errors + * | | |01 = Overflow error + * | | |10 = Underflow error + * | | |11 = Calibration in progress + * |[3:2] |ZPU |Output impedance pull-up calibration status + * | | |Similar status encodings as ZPD. + * |[5:4] |OPD |On-die termination pull-down calibration status + * | | |Similar status encodings as ZPD. + * |[7:6] |OPU |On-die termination pull-up calibration status + * | | |Similar status encodings as ZPD. + * @var DDRPHY_T::ZQ3CR0 + * Offset: 0x1B0 Impedance Control Register 0 (ZQnCR0) + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[27:0] |ZDATA |Impedance Over-Ride Data + * | | |Data used to directly drive the impedance control. + * | | |ZDATA field mapping for D3R I/O is as follows: + * | | |ZDATA[27:20] is reserved and returns zeros on reads. + * | | |ZDATA[19:15] is used to select the pull-up on-die termination impedance. + * | | |ZDATA[14:10] is used to select the pull-down on-die termination impedance. + * | | |ZDATA[9:5] is used to select the pull-up output impedance + * | | |ZDATA[4:0] is used to select the pull-down output impedance. + * | | |Note: The default value is 0x000014A for I/O type D3R. + * |[28] |ZDEN |Impedance Over-Ride Enable + * | | |When this bit is set, it allows users to directly drive the impedance control using the data programmed in the ZDATA field + * | | |Otherwise, the control is generated automatically by the impedance control logic. + * |[29] |ZCALBYP |Impedance Calibration Bypass + * | | |Bypasses, if set, impedance calibration of this ZQ control block when impedance calibration is already in progress + * | | |Impedance calibration can be disabled prior to trigger by using the ZCALEN bit. + * |[30] |ZCALEN |Impedance Calibration Enable + * | | |Enables, if set, the impedance calibration of this ZQ control block when impedance calibration is triggered using either the ZCAL bit of PIR register or the DFI update interface. + * |[31] |ZQPD |ZQ Power Down + * | | |Powers down, if set, the PZQ cell. + * @var DDRPHY_T::ZQ3CR1 + * Offset: 0x1B4 Impedance Control Register 1 (ZQnCR1) + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[7:0] |ZPROG |Impedance Divide Ratio + * | | |Selects the external resistor divide ratio to be used to set the output impedance and the on-die termination as follows: + * | | |ZPROG[7:4] = On-die termination divide select + * | | |ZPROG[3:0] = Output impedance divide select + * |[12] |DFICU0 |DFI Controller Update Interface 0 + * | | |Sets this impedance controller to be enabled for calibration when the DFI controller update interface 0 (channel 0) requests an update. + * |[13] |DFICU1 |DFI Controller Update Interface 1 + * | | |Sets this impedance controller to be enabled for calibration when the DFI controller update interface 1 (channel 1) requests an update + * | | |Only valid in shared-AC mode. + * |[14] |DFICCU |DFI Concurrent Controller Update Interface + * | | |Sets this impedance controller to be enabled for calibration when both of the DFI controller update interfaces request an update on the same clock + * | | |This provides the ability to enable impedance calibration updates for the Address/Command lane + * | | |Only valid in shared-AC mode. + * |[16] |DFIPU0 |DFI Update Interface 0 + * | | |Sets this impedance controller to be enabled for calibration when the DFI PHY update interface 0 (channel 0) requests an update. + * |[17] |DFIPU1 |DFI Update Interface 1 + * | | |Sets this impedance controller to be enabled for calibration when the DFI PHY update interface 1 (channel 1) requests an update + * | | |Only valid in shared-AC mode. + * @var DDRPHY_T::ZQ3SR0 + * Offset: 0x1B8 Impedance Status Register 0 (ZQnSR0) + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[27:0] |ZCTRL |Impedance Control + * | | |Current value of impedance control. + * | | |ZCTRL field mapping for D3R I/O is as follows: + * | | |ZCTRL[27:20] is reserved and returns zeros on reads. + * | | |ZCTRL[19:15] is used to select the pull-up on-die termination impedance. + * | | |ZCTRL[14:10] is used to select the pull-down on-die termination impedance. + * | | |ZCTRL[9:5] is used to select the pull-up output impedance. + * | | |ZCTRL[4:0] is used to select the pull-down output impedance. + * | | |Note: The default value is 0x000014A for I/O type D3R. + * |[30] |ZERR |Impedance Calibration Error + * | | |If set, indicates that there was an error during impedance calibration. + * |[31] |ZDONE |Impedance Calibration Done + * | | |Indicates that impedance calibration has completed. + * @var DDRPHY_T::ZQ3SR1 + * Offset: 0x1BC Impedance Status Register 1 (ZQnSR1) + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[1:0] |ZPD |Output impedance pull-down calibration status + * | | |Valid status encodings are: + * | | |00 = Completed with no errors + * | | |01 = Overflow error + * | | |10 = Underflow error + * | | |11 = Calibration in progress + * |[3:2] |ZPU |Output impedance pull-up calibration status + * | | |Similar status encodings as ZPD. + * |[5:4] |OPD |On-die termination pull-down calibration status + * | | |Similar status encodings as ZPD. + * |[7:6] |OPU |On-die termination pull-up calibration status + * | | |Similar status encodings as ZPD. + * @var DDRPHY_T::DX0GCR + * Offset: 0x1C0 DATX8 General Configuration Register (DXnGCR) + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[0] |DXEN |Data Byte Enable + * | | |Enables, if set, the data byte + * | | |Setting this bit to '0' disables the byte, i.e + * | | |the byte is not used in PHY initialization or training and is ignored during SDRAM read/write operations. + * |[1] |DQSODT |DQS On-Die Termination + * | | |Enables, when set, the on-die termination on the I/O for DQS/DQS# pin of the byte + * | | |This bit is ORed with the common DATX8 ODT configuration bit (see "DATX8 Common Configuration Register (DXCCR)"). + * | | |Note: This bit is only valid when DXnGCR0[9] is '0'. + * |[2] |DQODT |Data On-Die Termination + * | | |Enables, when set, the on-die termination on the I/O for DQ and DM pins of the byte + * | | |This bit is ORed with the common DATX8 ODT configuration bit (see "DATX8 Common Configuration Register (DXCCR)"). + * | | |Note: This bit is only valid when DXnGCR0[10] is '0'. + * |[3] |DXIOM |Data I/O Mode + * | | |Selects SSTL mode (when set to 0) or CMOS mode (when set to 1) of the I/O for DQ, DM, and DQS/DQS# pins of the byte + * | | |This bit is ORed with the IOM configuration bit of the individual DATX8(see "DATX8 Common Configuration Register (DXCCR)"). + * |[4] |DXPDD |Data Power Down Driver + * | | |Powers down, when set, the output driver on I/O for DQ, DM, and DQS/DQS# pins of the byte + * | | |This bit is ORed with the common PDD configuration bit (see "DATX8 Common Configuration Register (DXCCR)"). + * | | |Note: Asserting PDD puts the IO driver cell into a lower power, lower speed mode of operation + * | | |However, it will still drive if its OE is asserted + * | | |ODT will be disabled (if used) + * | | |Asserting PDD does not prevent the IO from driving. + * |[5] |DXPDR |Data Power Down Receiver + * | | |Powers down, when set, the input receiver on I/O for DQ, DM, and DQS/DQS# pins of the byte + * | | |This bit is ORed with the common PDR configuration bit (see "DATX8 Common Configuration Register (DXCCR)"). + * |[6] |DQSRPD |DQSR Power Down + * | | |Powers down, if set, the PDQSR cell + * | | |This bit is ORed with the common PDR configuration bit (see "DATX8 Common Configuration Register (DXCCR)") + * |[8:7] |DSEN |Write DQS Enable + * | | |Controls whether the write DQS going to the SDRAM is enabled (toggling) or disabled (static value) and whether the DQS is inverted + * | | |DQS# is always the inversion of DQS + * | | |These values are valid only when DQS/DQS# output enable is on, otherwise the DQS/DQS# is tristated + * | | |Valid settings are: + * | | |00 = Reserved + * | | |01 = DQS toggling with normal polarity (This should be the default setting) + * | | |10 = Reserved + * | | |11 = Reserved + * |[9] |DQSRTT |DQS Dynamic RTT Control + * | | |If set, the on die termination (ODT) control of the DQS/DQS# SSTL I/O is dynamically generated to enable the ODT during read operation and disabled otherwise + * | | |By setting this bit to '0' the dynamic ODT feature is disabled + * | | |To control ODT statically this bit must be set to '0' and DXnGCR0[1] (DQSODT) is used to enable ODT (when set to '1') or disable ODT(when set to '0'). + * |[10] |DQRTT |DQ Dynamic RTT Control + * | | |If set, the on die termination (ODT) control of the DQ/DM SSTL I/O is dynamically generated to enable the ODT during read operation and disabled otherwise + * | | |By setting this bit to '0' the dynamic ODT feature is disabled + * | | |To control ODT statically this bit must be set to '0' and DXnGCR0[2] (DQODT) is used to enable ODT (when set to '1') or disable ODT(when set to '0'). + * |[12:11] |RTTOH |RTT Output Hold + * | | |Indicates the number of clock cycles (from 0 to 3) after the read data postamble for which ODT control should remain set to DQSODT for DQS or DQODT for DQ/DM before disabling it (setting it to "0") when using dynamic ODT control + * | | |ODT is disabled almost RTTOH clock cycles after the read postamble. + * |[13] |RTTOAL |RTT On Additive Latency + * | | |Indicates when the ODT control of DQ/DQS SSTL I/Os is set to the value in DQODT/DQSODT during read cycles + * | | |Valid values are: + * | | |0 = ODT control is set to DQSODT/DQODT almost two cycles before read data preamble + * | | |1 = ODT control is set to DQSODT/DQODT almost one cycle before read data preamble + * |[15:14] |DXOEO |Data Byte Output Enable Override + * | | |Specifies whether the output I/O output enable for the byte lane should be set to a fixed value + * | | |Valid values are: + * | | |00 = No override. Output enable is controlled by DFI transactions + * | | |01 = Output enable is asserted (I/O is forced to output mode). + * | | |10 = Output enable is de-asserted (I/O is forced to input mode) + * | | |11 = Reserved + * |[16] |PLLRST |PLL Rest + * | | |Resets the byte PLL by driving the PLL reset pin + * | | |This bit is not self- clearing and a '0' must be written to de-assert the reset + * | | |This bit is ORed with the global PLLRST configuration bit. + * |[17] |PLLPD |PLL Power Down + * | | |Puts the byte PLL in Power-down mode by driving the PLL power down pin + * | | |This bit is not self-clearing and a '0' must be written to de-assert the power-down + * | | |This bit is ORed with the global PLLPD configuration bit. + * |[18] |GSHIFT |Gear Shift + * | | |Enables, if set, rapid locking mode on the byte PLL + * | | |This bit is ORed with the global GSHIFT configuration bit. + * |[19] |PLLBYP |PLL Bypass + * | | |Puts the byte PLL in bypass mode by driving the PLL bypass pin + * | | |This bit is not self-clearing and a '0' must be written to de-assert the bypass + * | | |This bit is ORed with the global BYP configuration bit. + * |[29:26] |WLRKEN |Write Level Rank Enable + * | | |Specifies the ranks that should be write leveled for this byte + * | | |Write leveling responses from ranks that are not enabled for write leveling for a particular byte are ignored and write leveling is flagged as done for these ranks + * | | |WLRKEN[0] enables rank 0, [1] enables rank 1, [2] enables rank 2, and [3] enables rank 3. + * |[30] |MDLEN |Master Delay Line Enable + * | | |Enables, if set, the DATX8 master delay line calibration to perform subsequent period measurements following the initial period measurements that are performed after reset or when calibration is manually triggered + * | | |These additional measurements are accumulated and filtered as long as this bit remains high + * | | |This bit is ANDed with the common DATX8 MDL enable bit. + * |[31] |CALBYP |Calibration Bypass + * | | |Prevents, if set, period measurement calibration from automatically triggering after PHY initialization. + * @var DDRPHY_T::DX0GSR0 + * Offset: 0x1C4 DATX8 General Status Registers 0 (DXnGSR0) + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[0] |WDQCAL |Write DQ Calibration + * | | |Indicates, if set, that the DATX8 has finished doing period measurement calibration for the write DQ LCDL. + * |[1] |RDQSCAL |Read DQS Calibration + * | | |Indicates, if set, that the DATX8 has finished doing period measurement calibration for the read DQS LCDL. + * |[2] |RDQSNCAL |Read DQS# Calibration + * | | |Indicates, if set, that the DATX8 has finished doing period measurement calibration for the read DQS# LCDL. + * |[3] |GDQSCAL |Read DQS gating Calibration + * | | |Indicates, if set, that the DATX8 has finished doing period measurement calibration for the read DQS gating LCDL. + * |[4] |WLCAL |Write Leveling Calibration + * | | |Indicates, if set, that the DATX8 has finished doing period measurement calibration for the write leveling slave delay line. + * |[5] |WLDONE |Write Leveling Done + * | | |Indicates, if set, that the DATX8 has completed write leveling. + * |[6] |WLERR |Write Leveling Error + * | | |Indicates, if set, that there is a write leveling error in the DATX8. + * |[14:7] |WLPRD |Write Leveling Period + * | | |Returns the DDR clock period measured by the write leveling LCDL during calibration + * | | |The measured period is used to generate the control of the write leveling pipeline which is a function of the write-leveling delay and the clock period + * | | |This value is PVT compensated. + * |[15] |DPLOCK |DATX8 PLL Lock + * | | |Indicates, if set, that the DATX8 PLL has locked. This is a direct status of the DATX8 PLL lock pin. + * |[23:16] |GDQSPRD |Read DQS gating Period + * | | |Returns the DDR clock period measured by the read DQS gating LCDL during calibration + * | | |This value is PVT compensated. + * |[27:24] |QSGERR |DQS Gate Training Error + * | | |Indicates, if set, that there is an error in DQS gate training. One bit for each of the up to 4 ranks. + * |[28] |WLDQ |Write Leveling DQ Status + * | | |Captures the write leveling DQ status from the DRAM during software write leveling. + * @var DDRPHY_T::DX0GSR1 + * Offset: 0x1C8 DATX8 General Status Registers 1 (DXnGSR1) + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[0] |DLTDONE |Delay Line Test Done + * | | |Indicates, if set, that the PHY control block has finished doing period measurement of the DATX8 delay line digital test output. + * |[24:1] |DLTCODE |Delay Line Test Code + * | | |Returns the code measured by the PHY control block that corresponds to the period of the DATX8 delay line digital test output. + * @var DDRPHY_T::DX0BDLR0 + * Offset: 0x1CC DATX8 Bit Delay Line Register 0 (DXnBDLR0) + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[5:0] |DQ0WBD |DQ0 Write Bit Delay + * | | |Delay select for the BDL on DQ0 write path. + * |[11:6] |DQ1WBD |DQ1 Write Bit Delay + * | | |Delay select for the BDL on DQ1 write path. + * |[17:12] |DQ2WBD |DQ2 Write Bit Delay + * | | |Delay select for the BDL on DQ2 write path. + * |[23:18] |DQ3WBD |DQ3 Write Bit Delay + * | | |Delay select for the BDL on DQ3 write path + * |[29:24] |DQ4WBD |DQ4 Write Bit Delay + * | | |Delay select for the BDL on DQ4 write path. + * @var DDRPHY_T::DX0BDLR1 + * Offset: 0x1D0 DATX8 Bit Delay Line Register 1 (DXnBDLR1) + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[5:0] |DQ5WBD |DQ5 Write Bit Delay + * | | |Delay select for the BDL on DQ5 write path. + * |[11:6] |DQ6WBD |DQ6 Write Bit Delay + * | | |Delay select for the BDL on DQ6 write path. + * |[17:12] |DQ7WBD |DQ7 Write Bit Delay + * | | |Delay select for the BDL on DQ7 write path. + * |[23:18] |DMWBD |DM Write Bit Delay + * | | |Delay select for the BDL on DM write path. + * |[29:24] |DSWBD |DQS Write Bit Delay + * | | |Delay select for the BDL on DQS write path + * @var DDRPHY_T::DX0BDLR2 + * Offset: 0x1D4 DATX8 Bit Delay Line Register 2 (DXnBDLR2) + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[5:0] |DSOEBD |DQS Output Enable Bit Delay + * | | |Delay select for the BDL on DQS output enable path + * |[11:6] |DQOEBD |DQ Output Enable Bit Delay + * | | |Delay select for the BDL on DQ/DM output enable path. + * |[17:12] |DSRBD |DQS Read Bit Delay + * | | |Delay select for the BDL on DQS read path + * |[23:18] |DSNRBD |DQSN Read Bit Delay + * | | |Delay select for the BDL on DQSN read path + * @var DDRPHY_T::DX0BDLR3 + * Offset: 0x1D8 DATX8 Bit Delay Line Register 3 (DXnBDLR3) + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[5:0] |DQ0RBD |DQ0 Read Bit Delay + * | | |Delay select for the BDL on DQ0 read path. + * |[11:6] |DQ1RBD |DQ1 Read Bit Delay + * | | |Delay select for the BDL on DQ1 read path. + * |[17:12] |DQ2RBD |DQ2 Read Bit Delay + * | | |Delay select for the BDL on DQ2 read path. + * |[23:18] |DQ3RBD |DQ3 Read Bit Delay + * | | |Delay select for the BDL on DQ3 read path + * |[29:24] |DQ4RBD |DQ4 Read Bit Delay + * | | |Delay select for the BDL on DQ4 read path. + * @var DDRPHY_T::DX0BDLR4 + * Offset: 0x1DC DATX8 Bit Delay Line Register 4 (DXnBDLR4) + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[5:0] |DQ5RBD |DQ5 Read Bit Delay + * | | |Delay select for the BDL on DQ5 read path. + * |[11:6] |DQ6RBD |DQ6 Read Bit Delay + * | | |Delay select for the BDL on DQ6 read path. + * |[17:12] |DQ7RBD |DQ7 Read Bit Delay + * | | |Delay select for the BDL on DQ7 read path. + * |[23:18] |DMRBD |DM Read Bit Delay + * | | |Delay select for the BDL on DM read path. + * @var DDRPHY_T::DX0LCDLR0 + * Offset: 0x1E0 DATX8 Bit Delay Line Register 0 (DXnBDLR0) + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[7:0] |R0WLD |Rank 0 Write Leveling Delay + * | | |Rank 0 delay select for the write leveling (WL) LCDL + * |[15:8] |R1WLD |Rank 1 Write Leveling Delay + * | | |Rank 1 delay select for the write leveling (WL) LCDL + * |[23:16] |R2WLD |Rank 2 Write Leveling Delay + * | | |Rank 2 delay select for the write leveling (WL) LCDL + * |[31:24] |R3WLD |Rank 3 Write Leveling Delay + * | | |Rank 3 delay select for the write leveling (WL) LCDL + * @var DDRPHY_T::DX0LCDLR1 + * Offset: 0x1E4 DATX8 Bit Delay Line Register 1 (DXnBDLR1) + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[7:0] |WDQD |Write Data Delay + * | | |Delay select for the write data (WDQ) LCDL + * |[15:8] |RDQSD |Read DQS Delay + * | | |Delay select for the read DQS (RDQS) LCDL + * |[23:16] |RDQSND |Read DQSN Delay + * | | |Delay select for the read DQSN (RDQS) LCDL + * @var DDRPHY_T::DX0LCDLR2 + * Offset: 0x1E8 DATX8 Bit Delay Line Register 2 (DXnBDLR2) + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[7:0] |R0DQSGD |Rank 0 Read DQS Gating Delay + * | | |Rank 0 delay select for the read DQS gating (DQSG) LCDL + * |[15:8] |R1DQSGD |Rank 1 Read DQS Gating Delay + * | | |Rank 1 delay select for the read DQS gating (DQSG) LCDL + * |[23:16] |R2DQSGD |Rank 2 Read DQS Gating Delay + * | | |Rank 2 delay select for the read DQS gating (DQSG) LCDL + * |[31:24] |R3DQSGD |Rank 3 Read DQS Gating Delay + * | | |Rank 3 delay select for the read DQS gating (DQSG) LCDL + * @var DDRPHY_T::DX0MDLR + * Offset: 0x1EC DATX8 Master Delay Line Register (DXnMDLR) + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[7:0] |IPRD |Initial Period + * | | |Initial period measured by the master delay line calibration for VT drift compensation + * | | |This value is used as the denominator when calculating the ratios of updates during VT compensation. + * |[15:8] |TPRD |Target Period + * | | |Target period measured by the master delay line calibration for VT drift compensation + * | | |This is the current measured value of the period and is continuously updated if the MDL is enabled to do so. + * |[23:16] |MDLD |MDL Delay + * | | |Delay select for the LCDL for the Master Delay Line. + * @var DDRPHY_T::DX0GTR + * Offset: 0x1F0 DATX8 General Timing Register (DXnGTR) + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[2:0] |R0DGSL |Rank n DQS Gating System Latency + * | | |This is used to increase the number of clock cycles needed to expect valid DDR read data by up to seven extra clock cycles + * | | |This is used to compensate for board delays and other system delays + * | | |Power-up default is 000 (i.e + * | | |no extra clock cycles required) + * | | |The SL fields are initially set by the PUB during automatic DQS data training but these values can be overwritten by a direct write to this register + * | | |Every three bits of this register control the latency of each of the (up to) four ranks + * | | |R0DGSL controls the latency of rank 0, R1DGSL controls rank 1, and so on + * | | |Valid values are 0 to 7. + * |[5:3] |R1DGSL |Rank n DQS Gating System Latency + * | | |This is used to increase the number of clock cycles needed to expect valid DDR read data by up to seven extra clock cycles + * | | |This is used to compensate for board delays and other system delays + * | | |Power-up default is 000 (i.e + * | | |no extra clock cycles required) + * | | |The SL fields are initially set by the PUB during automatic DQS data training but these values can be overwritten by a direct write to this register + * | | |Every three bits of this register control the latency of each of the (up to) four ranks + * | | |R0DGSL controls the latency of rank 0, R1DGSL controls rank 1, and so on + * | | |Valid values are 0 to 7. + * |[8:6] |R2DGSL |Rank n DQS Gating System Latency + * | | |This is used to increase the number of clock cycles needed to expect valid DDR read data by up to seven extra clock cycles + * | | |This is used to compensate for board delays and other system delays + * | | |Power-up default is 000 (i.e + * | | |no extra clock cycles required) + * | | |The SL fields are initially set by the PUB during automatic DQS data training but these values can be overwritten by a direct write to this register + * | | |Every three bits of this register control the latency of each of the (up to) four ranks + * | | |R0DGSL controls the latency of rank 0, R1DGSL controls rank 1, and so on + * | | |Valid values are 0 to 7. + * |[11:9] |R3DGSL |Rank n DQS Gating System Latency + * | | |This is used to increase the number of clock cycles needed to expect valid DDR read data by up to seven extra clock cycles + * | | |This is used to compensate for board delays and other system delays + * | | |Power-up default is 000 (i.e + * | | |no extra clock cycles required) + * | | |The SL fields are initially set by the PUB during automatic DQS data training but these values can be overwritten by a direct write to this register + * | | |Every three bits of this register control the latency of each of the (up to) four ranks + * | | |R0DGSL controls the latency of rank 0, R1DGSL controls rank 1, and so on + * | | |Valid values are 0 to 7. + * |[13:12] |R0WLSL |Rank n Write Leveling System Latency + * | | |This is used to adjust the write latency after write leveling + * | | |Power-up default is 01 (i.e + * | | |no extra clock cycles required) + * | | |The SL fields are initially set by the PUB during automatic write leveling but these values can be overwritten by a direct write to this register + * | | |Every two bits of this register control the latency of each of the (up to) four ranks + * | | |R0WLSL controls the latency of rank 0, R1WLSL controls rank 1, and so on + * | | |Valid values: + * | | |00 = Write latency = WL - 1 + * | | |01 = Write latency = WL + * | | |10 = Write latency = WL + 1 + * | | |11 = Reserved + * |[15:14] |R1WLSL |Rank n Write Leveling System Latency + * | | |This is used to adjust the write latency after write leveling + * | | |Power-up default is 01 (i.e + * | | |no extra clock cycles required) + * | | |The SL fields are initially set by the PUB during automatic write leveling but these values can be overwritten by a direct write to this register + * | | |Every two bits of this register control the latency of each of the (up to) four ranks + * | | |R0WLSL controls the latency of rank 0, R1WLSL controls rank 1, and so on + * | | |Valid values: + * | | |00 = Write latency = WL - 1 + * | | |01 = Write latency = WL + * | | |10 = Write latency = WL + 1 + * | | |11 = Reserved + * |[17:16] |R2WLSL |Rank n Write Leveling System Latency + * | | |This is used to adjust the write latency after write leveling + * | | |Power-up default is 01 (i.e + * | | |no extra clock cycles required) + * | | |The SL fields are initially set by the PUB during automatic write leveling but these values can be overwritten by a direct write to this register + * | | |Every two bits of this register control the latency of each of the (up to) four ranks + * | | |R0WLSL controls the latency of rank 0, R1WLSL controls rank 1, and so on + * | | |Valid values: + * | | |00 = Write latency = WL - 1 + * | | |01 = Write latency = WL + * | | |10 = Write latency = WL + 1 + * | | |11 = Reserved + * |[19:18] |R3WLSL |Rank n Write Leveling System Latency + * | | |This is used to adjust the write latency after write leveling + * | | |Power-up default is 01 (i.e + * | | |no extra clock cycles required) + * | | |The SL fields are initially set by the PUB during automatic write leveling but these values can be overwritten by a direct write to this register + * | | |Every two bits of this register control the latency of each of the (up to) four ranks + * | | |R0WLSL controls the latency of rank 0, R1WLSL controls rank 1, and so on + * | | |Valid values: + * | | |00 = Write latency = WL - 1 + * | | |01 = Write latency = WL + * | | |10 = Write latency = WL + 1 + * | | |11 = Reserved + * @var DDRPHY_T::DX0GSR2 + * Offset: 0x1F4 DATX8 General Status Register 2 (DXnGSR2) + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[0] |RDERR |Read Bit Deskew Error + * | | |Indicates, if set, that the DATX8 has encountered an error during execution of the read bit deskew training. + * |[1] |RDWN |Read Bit Deskew Warning + * | | |Indicates, if set, that the DATX8 has encountered a warning during execution of the read bit deskew training. + * |[2] |WDERR |Write Bit Deskew Error + * | | |Indicates, if set, that the DATX8 has encountered an error during execution of the write bit deskew training. + * |[3] |WDWN |Write Bit Deskew Warning + * | | |Indicates, if set, that the DATX8 has encountered a warning during execution of the write bit deskew training. + * |[4] |REERR |Read Data Eye Training Error + * | | |Indicates, if set, that the DATX8 has encountered an error during execution of the read data eye training. + * |[5] |REWN |Read Data Eye Training Warning + * | | |Indicates, if set, that the DATX8 has encountered a warning during execution of the read data eye training. + * |[6] |WEERR |Write Data Eye Training Error + * | | |Indicates, if set, that the DATX8 has encountered an error during execution of the write data eye training. + * |[7] |WEWN |Write Data Eye Training Warning + * | | |Indicates, if set, that the DATX8 has encountered a warning during execution of the write data eye training. + * |[11:8] |ESTAT |Error Status + * | | |If an error occurred for this lane as indicated by RDERR, WDERR, REERR or WEERR the error status code can provide additional information regard when the error occurred during the algorithm execution. + * @var DDRPHY_T::DX1GCR + * Offset: 0x200 DATX8 General Configuration Register (DXnGCR) + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[0] |DXEN |Data Byte Enable + * | | |Enables, if set, the data byte + * | | |Setting this bit to '0' disables the byte, i.e + * | | |the byte is not used in PHY initialization or training and is ignored during SDRAM read/write operations. + * |[1] |DQSODT |DQS On-Die Termination + * | | |Enables, when set, the on-die termination on the I/O for DQS/DQS# pin of the byte + * | | |This bit is ORed with the common DATX8 ODT configuration bit (see "DATX8 Common Configuration Register (DXCCR)"). + * | | |Note: This bit is only valid when DXnGCR0[9] is '0'. + * |[2] |DQODT |Data On-Die Termination + * | | |Enables, when set, the on-die termination on the I/O for DQ and DM pins of the byte + * | | |This bit is ORed with the common DATX8 ODT configuration bit (see "DATX8 Common Configuration Register (DXCCR)"). + * | | |Note: This bit is only valid when DXnGCR0[10] is '0'. + * |[3] |DXIOM |Data I/O Mode + * | | |Selects SSTL mode (when set to 0) or CMOS mode (when set to 1) of the I/O for DQ, DM, and DQS/DQS# pins of the byte + * | | |This bit is ORed with the IOM configuration bit of the individual DATX8(see "DATX8 Common Configuration Register (DXCCR)"). + * |[4] |DXPDD |Data Power Down Driver + * | | |Powers down, when set, the output driver on I/O for DQ, DM, and DQS/DQS# pins of the byte + * | | |This bit is ORed with the common PDD configuration bit (see "DATX8 Common Configuration Register (DXCCR)"). + * | | |Note: Asserting PDD puts the IO driver cell into a lower power, lower speed mode of operation + * | | |However, it will still drive if its OE is asserted + * | | |ODT will be disabled (if used) + * | | |Asserting PDD does not prevent the IO from driving. + * |[5] |DXPDR |Data Power Down Receiver + * | | |Powers down, when set, the input receiver on I/O for DQ, DM, and DQS/DQS# pins of the byte + * | | |This bit is ORed with the common PDR configuration bit (see "DATX8 Common Configuration Register (DXCCR)"). + * |[6] |DQSRPD |DQSR Power Down + * | | |Powers down, if set, the PDQSR cell + * | | |This bit is ORed with the common PDR configuration bit (see "DATX8 Common Configuration Register (DXCCR)") + * |[8:7] |DSEN |Write DQS Enable + * | | |Controls whether the write DQS going to the SDRAM is enabled (toggling) or disabled (static value) and whether the DQS is inverted + * | | |DQS# is always the inversion of DQS + * | | |These values are valid only when DQS/DQS# output enable is on, otherwise the DQS/DQS# is tristated + * | | |Valid settings are: + * | | |00 = Reserved + * | | |01 = DQS toggling with normal polarity (This should be the default setting) + * | | |10 = Reserved + * | | |11 = Reserved + * |[9] |DQSRTT |DQS Dynamic RTT Control + * | | |If set, the on die termination (ODT) control of the DQS/DQS# SSTL I/O is dynamically generated to enable the ODT during read operation and disabled otherwise + * | | |By setting this bit to '0' the dynamic ODT feature is disabled + * | | |To control ODT statically this bit must be set to '0' and DXnGCR0[1] (DQSODT) is used to enable ODT (when set to '1') or disable ODT(when set to '0'). + * |[10] |DQRTT |DQ Dynamic RTT Control + * | | |If set, the on die termination (ODT) control of the DQ/DM SSTL I/O is dynamically generated to enable the ODT during read operation and disabled otherwise + * | | |By setting this bit to '0' the dynamic ODT feature is disabled + * | | |To control ODT statically this bit must be set to '0' and DXnGCR0[2] (DQODT) is used to enable ODT (when set to '1') or disable ODT(when set to '0'). + * |[12:11] |RTTOH |RTT Output Hold + * | | |Indicates the number of clock cycles (from 0 to 3) after the read data postamble for which ODT control should remain set to DQSODT for DQS or DQODT for DQ/DM before disabling it (setting it to '0') when using dynamic ODT control + * | | |ODT is disabled almost RTTOH clock cycles after the read postamble. + * |[13] |RTTOAL |RTT On Additive Latency + * | | |Indicates when the ODT control of DQ/DQS SSTL I/Os is set to the value in DQODT/DQSODT during read cycles + * | | |Valid values are: + * | | |0 = ODT control is set to DQSODT/DQODT almost two cycles before read data preamble + * | | |1 = ODT control is set to DQSODT/DQODT almost one cycle before read data preamble + * |[15:14] |DXOEO |Data Byte Output Enable Override + * | | |Specifies whether the output I/O output enable for the byte lane should be set to a fixed value + * | | |Valid values are: + * | | |00 = No override. Output enable is controlled by DFI transactions + * | | |01 = Output enable is asserted (I/O is forced to output mode). + * | | |10 = Output enable is de-asserted (I/O is forced to input mode) + * | | |11 = Reserved + * |[16] |PLLRST |PLL Rest + * | | |Resets the byte PLL by driving the PLL reset pin + * | | |This bit is not self- clearing and a '0' must be written to de-assert the reset + * | | |This bit is ORed with the global PLLRST configuration bit. + * |[17] |PLLPD |PLL Power Down + * | | |Puts the byte PLL in Power-down mode by driving the PLL power down pin + * | | |This bit is not self-clearing and a '0' must be written to de-assert the power-down + * | | |This bit is ORed with the global PLLPD configuration bit. + * |[18] |GSHIFT |Gear Shift + * | | |Enables, if set, rapid locking mode on the byte PLL + * | | |This bit is ORed with the global GSHIFT configuration bit. + * |[19] |PLLBYP |PLL Bypass + * | | |Puts the byte PLL in bypass mode by driving the PLL bypass pin + * | | |This bit is not self-clearing and a '0' must be written to de-assert the bypass + * | | |This bit is ORed with the global BYP configuration bit. + * |[29:26] |WLRKEN |Write Level Rank Enable + * | | |Specifies the ranks that should be write leveled for this byte + * | | |Write leveling responses from ranks that are not enabled for write leveling for a particular byte are ignored and write leveling is flagged as done for these ranks + * | | |WLRKEN[0] enables rank 0, [1] enables rank 1, [2] enables rank 2, and [3] enables rank 3. + * |[30] |MDLEN |Master Delay Line Enable + * | | |Enables, if set, the DATX8 master delay line calibration to perform subsequent period measurements following the initial period measurements that are performed after reset or when calibration is manually triggered + * | | |These additional measurements are accumulated and filtered as long as this bit remains high + * | | |This bit is ANDed with the common DATX8 MDL enable bit. + * |[31] |CALBYP |Calibration Bypass + * | | |Prevents, if set, period measurement calibration from automatically triggering after PHY initialization. + * @var DDRPHY_T::DX1GSR0 + * Offset: 0x204 DATX8 General Status Registers 0 (DXnGSR0) + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[0] |WDQCAL |Write DQ Calibration + * | | |Indicates, if set, that the DATX8 has finished doing period measurement calibration for the write DQ LCDL. + * |[1] |RDQSCAL |Read DQS Calibration + * | | |Indicates, if set, that the DATX8 has finished doing period measurement calibration for the read DQS LCDL. + * |[2] |RDQSNCAL |Read DQS# Calibration + * | | |Indicates, if set, that the DATX8 has finished doing period measurement calibration for the read DQS# LCDL. + * |[3] |GDQSCAL |Read DQS gating Calibration + * | | |Indicates, if set, that the DATX8 has finished doing period measurement calibration for the read DQS gating LCDL. + * |[4] |WLCAL |Write Leveling Calibration + * | | |Indicates, if set, that the DATX8 has finished doing period measurement calibration for the write leveling slave delay line. + * |[5] |WLDONE |Write Leveling Done + * | | |Indicates, if set, that the DATX8 has completed write leveling. + * |[6] |WLERR |Write Leveling Error + * | | |Indicates, if set, that there is a write leveling error in the DATX8. + * |[14:7] |WLPRD |Write Leveling Period + * | | |Returns the DDR clock period measured by the write leveling LCDL during calibration + * | | |The measured period is used to generate the control of the write leveling pipeline which is a function of the write-leveling delay and the clock period + * | | |This value is PVT compensated. + * |[15] |DPLOCK |DATX8 PLL Lock + * | | |Indicates, if set, that the DATX8 PLL has locked. This is a direct status of the DATX8 PLL lock pin. + * |[23:16] |GDQSPRD |Read DQS gating Period + * | | |Returns the DDR clock period measured by the read DQS gating LCDL during calibration + * | | |This value is PVT compensated. + * |[27:24] |QSGERR |DQS Gate Training Error + * | | |Indicates, if set, that there is an error in DQS gate training. One bit for each of the up to 4 ranks. + * |[28] |WLDQ |Write Leveling DQ Status + * | | |Captures the write leveling DQ status from the DRAM during software write leveling. + * @var DDRPHY_T::DX1GSR1 + * Offset: 0x208 DATX8 General Status Registers 1 (DXnGSR1) + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[0] |DLTDONE |Delay Line Test Done + * | | |Indicates, if set, that the PHY control block has finished doing period measurement of the DATX8 delay line digital test output. + * |[24:1] |DLTCODE |Delay Line Test Code + * | | |Returns the code measured by the PHY control block that corresponds to the period of the DATX8 delay line digital test output. + * @var DDRPHY_T::DX1BDLR0 + * Offset: 0x20C DATX8 Bit Delay Line Register 0 (DXnBDLR0) + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[5:0] |DQ0WBD |DQ0 Write Bit Delay + * | | |Delay select for the BDL on DQ0 write path. + * |[11:6] |DQ1WBD |DQ1 Write Bit Delay + * | | |Delay select for the BDL on DQ1 write path. + * |[17:12] |DQ2WBD |DQ2 Write Bit Delay + * | | |Delay select for the BDL on DQ2 write path. + * |[23:18] |DQ3WBD |DQ3 Write Bit Delay + * | | |Delay select for the BDL on DQ3 write path + * |[29:24] |DQ4WBD |DQ4 Write Bit Delay + * | | |Delay select for the BDL on DQ4 write path. + * @var DDRPHY_T::DX1BDLR1 + * Offset: 0x210 DATX8 Bit Delay Line Register 1 (DXnBDLR1) + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[5:0] |DQ5WBD |DQ5 Write Bit Delay + * | | |Delay select for the BDL on DQ5 write path. + * |[11:6] |DQ6WBD |DQ6 Write Bit Delay + * | | |Delay select for the BDL on DQ6 write path. + * |[17:12] |DQ7WBD |DQ7 Write Bit Delay + * | | |Delay select for the BDL on DQ7 write path. + * |[23:18] |DMWBD |DM Write Bit Delay + * | | |Delay select for the BDL on DM write path. + * |[29:24] |DSWBD |DQS Write Bit Delay + * | | |Delay select for the BDL on DQS write path + * @var DDRPHY_T::DX1BDLR2 + * Offset: 0x214 DATX8 Bit Delay Line Register 2 (DXnBDLR2) + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[5:0] |DSOEBD |DQS Output Enable Bit Delay + * | | |Delay select for the BDL on DQS output enable path + * |[11:6] |DQOEBD |DQ Output Enable Bit Delay + * | | |Delay select for the BDL on DQ/DM output enable path. + * |[17:12] |DSRBD |DQS Read Bit Delay + * | | |Delay select for the BDL on DQS read path + * |[23:18] |DSNRBD |DQSN Read Bit Delay + * | | |Delay select for the BDL on DQSN read path + * @var DDRPHY_T::DX1BDLR3 + * Offset: 0x218 DATX8 Bit Delay Line Register 3 (DXnBDLR3) + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[5:0] |DQ0RBD |DQ0 Read Bit Delay + * | | |Delay select for the BDL on DQ0 read path. + * |[11:6] |DQ1RBD |DQ1 Read Bit Delay + * | | |Delay select for the BDL on DQ1 read path. + * |[17:12] |DQ2RBD |DQ2 Read Bit Delay + * | | |Delay select for the BDL on DQ2 read path. + * |[23:18] |DQ3RBD |DQ3 Read Bit Delay + * | | |Delay select for the BDL on DQ3 read path + * |[29:24] |DQ4RBD |DQ4 Read Bit Delay + * | | |Delay select for the BDL on DQ4 read path. + * @var DDRPHY_T::DX1BDLR4 + * Offset: 0x21C DATX8 Bit Delay Line Register 4 (DXnBDLR4) + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[5:0] |DQ5RBD |DQ5 Read Bit Delay + * | | |Delay select for the BDL on DQ5 read path. + * |[11:6] |DQ6RBD |DQ6 Read Bit Delay + * | | |Delay select for the BDL on DQ6 read path. + * |[17:12] |DQ7RBD |DQ7 Read Bit Delay + * | | |Delay select for the BDL on DQ7 read path. + * |[23:18] |DMRBD |DM Read Bit Delay + * | | |Delay select for the BDL on DM read path. + * @var DDRPHY_T::DX1LCDLR0 + * Offset: 0x220 DATX8 Bit Delay Line Register 0 (DXnBDLR0) + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[7:0] |R0WLD |Rank 0 Write Leveling Delay + * | | |Rank 0 delay select for the write leveling (WL) LCDL + * |[15:8] |R1WLD |Rank 1 Write Leveling Delay + * | | |Rank 1 delay select for the write leveling (WL) LCDL + * |[23:16] |R2WLD |Rank 2 Write Leveling Delay + * | | |Rank 2 delay select for the write leveling (WL) LCDL + * |[31:24] |R3WLD |Rank 3 Write Leveling Delay + * | | |Rank 3 delay select for the write leveling (WL) LCDL + * @var DDRPHY_T::DX1LCDLR1 + * Offset: 0x224 DATX8 Bit Delay Line Register 1 (DXnBDLR1) + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[7:0] |WDQD |Write Data Delay + * | | |Delay select for the write data (WDQ) LCDL + * |[15:8] |RDQSD |Read DQS Delay + * | | |Delay select for the read DQS (RDQS) LCDL + * |[23:16] |RDQSND |Read DQSN Delay + * | | |Delay select for the read DQSN (RDQS) LCDL + * @var DDRPHY_T::DX1LCDLR2 + * Offset: 0x228 DATX8 Bit Delay Line Register 2 (DXnBDLR2) + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[7:0] |R0DQSGD |Rank 0 Read DQS Gating Delay + * | | |Rank 0 delay select for the read DQS gating (DQSG) LCDL + * |[15:8] |R1DQSGD |Rank 1 Read DQS Gating Delay + * | | |Rank 1 delay select for the read DQS gating (DQSG) LCDL + * |[23:16] |R2DQSGD |Rank 2 Read DQS Gating Delay + * | | |Rank 2 delay select for the read DQS gating (DQSG) LCDL + * |[31:24] |R3DQSGD |Rank 3 Read DQS Gating Delay + * | | |Rank 3 delay select for the read DQS gating (DQSG) LCDL + * @var DDRPHY_T::DX1MDLR + * Offset: 0x22C DATX8 Master Delay Line Register (DXnMDLR) + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[7:0] |IPRD |Initial Period + * | | |Initial period measured by the master delay line calibration for VT drift compensation + * | | |This value is used as the denominator when calculating the ratios of updates during VT compensation. + * |[15:8] |TPRD |Target Period + * | | |Target period measured by the master delay line calibration for VT drift compensation + * | | |This is the current measured value of the period and is continuously updated if the MDL is enabled to do so. + * |[23:16] |MDLD |MDL Delay + * | | |Delay select for the LCDL for the Master Delay Line. + * @var DDRPHY_T::DX1GTR + * Offset: 0x230 DATX8 General Timing Register (DXnGTR) + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[2:0] |R0DGSL |Rank n DQS Gating System Latency + * | | |This is used to increase the number of clock cycles needed to expect valid DDR read data by up to seven extra clock cycles + * | | |This is used to compensate for board delays and other system delays + * | | |Power-up default is 000 (i.e + * | | |no extra clock cycles required) + * | | |The SL fields are initially set by the PUB during automatic DQS data training but these values can be overwritten by a direct write to this register + * | | |Every three bits of this register control the latency of each of the (up to) four ranks + * | | |R0DGSL controls the latency of rank 0, R1DGSL controls rank 1, and so on + * | | |Valid values are 0 to 7. + * |[5:3] |R1DGSL |Rank n DQS Gating System Latency + * | | |This is used to increase the number of clock cycles needed to expect valid DDR read data by up to seven extra clock cycles + * | | |This is used to compensate for board delays and other system delays + * | | |Power-up default is 000 (i.e + * | | |no extra clock cycles required) + * | | |The SL fields are initially set by the PUB during automatic DQS data training but these values can be overwritten by a direct write to this register + * | | |Every three bits of this register control the latency of each of the (up to) four ranks + * | | |R0DGSL controls the latency of rank 0, R1DGSL controls rank 1, and so on + * | | |Valid values are 0 to 7. + * |[8:6] |R2DGSL |Rank n DQS Gating System Latency + * | | |This is used to increase the number of clock cycles needed to expect valid DDR read data by up to seven extra clock cycles + * | | |This is used to compensate for board delays and other system delays + * | | |Power-up default is 000 (i.e + * | | |no extra clock cycles required) + * | | |The SL fields are initially set by the PUB during automatic DQS data training but these values can be overwritten by a direct write to this register + * | | |Every three bits of this register control the latency of each of the (up to) four ranks + * | | |R0DGSL controls the latency of rank 0, R1DGSL controls rank 1, and so on + * | | |Valid values are 0 to 7. + * |[11:9] |R3DGSL |Rank n DQS Gating System Latency + * | | |This is used to increase the number of clock cycles needed to expect valid DDR read data by up to seven extra clock cycles + * | | |This is used to compensate for board delays and other system delays + * | | |Power-up default is 000 (i.e + * | | |no extra clock cycles required) + * | | |The SL fields are initially set by the PUB during automatic DQS data training but these values can be overwritten by a direct write to this register + * | | |Every three bits of this register control the latency of each of the (up to) four ranks + * | | |R0DGSL controls the latency of rank 0, R1DGSL controls rank 1, and so on + * | | |Valid values are 0 to 7. + * |[13:12] |R0WLSL |Rank n Write Leveling System Latency + * | | |This is used to adjust the write latency after write leveling + * | | |Power-up default is 01 (i.e + * | | |no extra clock cycles required) + * | | |The SL fields are initially set by the PUB during automatic write leveling but these values can be overwritten by a direct write to this register + * | | |Every two bits of this register control the latency of each of the (up to) four ranks + * | | |R0WLSL controls the latency of rank 0, R1WLSL controls rank 1, and so on + * | | |Valid values: + * | | |00 = Write latency = WL - 1 + * | | |01 = Write latency = WL + * | | |10 = Write latency = WL + 1 + * | | |11 = Reserved + * |[15:14] |R1WLSL |Rank n Write Leveling System Latency + * | | |This is used to adjust the write latency after write leveling + * | | |Power-up default is 01 (i.e + * | | |no extra clock cycles required) + * | | |The SL fields are initially set by the PUB during automatic write leveling but these values can be overwritten by a direct write to this register + * | | |Every two bits of this register control the latency of each of the (up to) four ranks + * | | |R0WLSL controls the latency of rank 0, R1WLSL controls rank 1, and so on + * | | |Valid values: + * | | |00 = Write latency = WL - 1 + * | | |01 = Write latency = WL + * | | |10 = Write latency = WL + 1 + * | | |11 = Reserved + * |[17:16] |R2WLSL |Rank n Write Leveling System Latency + * | | |This is used to adjust the write latency after write leveling + * | | |Power-up default is 01 (i.e + * | | |no extra clock cycles required) + * | | |The SL fields are initially set by the PUB during automatic write leveling but these values can be overwritten by a direct write to this register + * | | |Every two bits of this register control the latency of each of the (up to) four ranks + * | | |R0WLSL controls the latency of rank 0, R1WLSL controls rank 1, and so on + * | | |Valid values: + * | | |00 = Write latency = WL - 1 + * | | |01 = Write latency = WL + * | | |10 = Write latency = WL + 1 + * | | |11 = Reserved + * |[19:18] |R3WLSL |Rank n Write Leveling System Latency + * | | |This is used to adjust the write latency after write leveling + * | | |Power-up default is 01 (i.e + * | | |no extra clock cycles required) + * | | |The SL fields are initially set by the PUB during automatic write leveling but these values can be overwritten by a direct write to this register + * | | |Every two bits of this register control the latency of each of the (up to) four ranks + * | | |R0WLSL controls the latency of rank 0, R1WLSL controls rank 1, and so on + * | | |Valid values: + * | | |00 = Write latency = WL - 1 + * | | |01 = Write latency = WL + * | | |10 = Write latency = WL + 1 + * | | |11 = Reserved + * @var DDRPHY_T::DX1GSR2 + * Offset: 0x234 DATX8 General Status Register 2 (DXnGSR2) + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[0] |RDERR |Read Bit Deskew Error + * | | |Indicates, if set, that the DATX8 has encountered an error during execution of the read bit deskew training. + * |[1] |RDWN |Read Bit Deskew Warning + * | | |Indicates, if set, that the DATX8 has encountered a warning during execution of the read bit deskew training. + * |[2] |WDERR |Write Bit Deskew Error + * | | |Indicates, if set, that the DATX8 has encountered an error during execution of the write bit deskew training. + * |[3] |WDWN |Write Bit Deskew Warning + * | | |Indicates, if set, that the DATX8 has encountered a warning during execution of the write bit deskew training. + * |[4] |REERR |Read Data Eye Training Error + * | | |Indicates, if set, that the DATX8 has encountered an error during execution of the read data eye training. + * |[5] |REWN |Read Data Eye Training Warning + * | | |Indicates, if set, that the DATX8 has encountered a warning during execution of the read data eye training. + * |[6] |WEERR |Write Data Eye Training Error + * | | |Indicates, if set, that the DATX8 has encountered an error during execution of the write data eye training. + * |[7] |WEWN |Write Data Eye Training Warning + * | | |Indicates, if set, that the DATX8 has encountered a warning during execution of the write data eye training. + * |[11:8] |ESTAT |Error Status + * | | |If an error occurred for this lane as indicated by RDERR, WDERR, REERR or WEERR the error status code can provide additional information regard when the error occurred during the algorithm execution. + * @var DDRPHY_T::DX2GCR + * Offset: 0x240 DATX8 General Configuration Register (DXnGCR) + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[0] |DXEN |Data Byte Enable + * | | |Enables, if set, the data byte + * | | |Setting this bit to '0' disables the byte, i.e + * | | |the byte is not used in PHY initialization or training and is ignored during SDRAM read/write operations. + * |[1] |DQSODT |DQS On-Die Termination + * | | |Enables, when set, the on-die termination on the I/O for DQS/DQS# pin of the byte + * | | |This bit is ORed with the common DATX8 ODT configuration bit (see "DATX8 Common Configuration Register (DXCCR)"). + * | | |Note: This bit is only valid when DXnGCR0[9] is '0'. + * |[2] |DQODT |Data On-Die Termination + * | | |Enables, when set, the on-die termination on the I/O for DQ and DM pins of the byte + * | | |This bit is ORed with the common DATX8 ODT configuration bit (see "DATX8 Common Configuration Register (DXCCR)"). + * | | |Note: This bit is only valid when DXnGCR0[10] is '0'. + * |[3] |DXIOM |Data I/O Mode + * | | |Selects SSTL mode (when set to 0) or CMOS mode (when set to 1) of the I/O for DQ, DM, and DQS/DQS# pins of the byte + * | | |This bit is ORed with the IOM configuration bit of the individual DATX8(see "DATX8 Common Configuration Register (DXCCR)"). + * |[4] |DXPDD |Data Power Down Driver + * | | |Powers down, when set, the output driver on I/O for DQ, DM, and DQS/DQS# pins of the byte + * | | |This bit is ORed with the common PDD configuration bit (see "DATX8 Common Configuration Register (DXCCR)"). + * | | |Note: Asserting PDD puts the IO driver cell into a lower power, lower speed mode of operation + * | | |However, it will still drive if its OE is asserted + * | | |ODT will be disabled (if used) + * | | |Asserting PDD does not prevent the IO from driving. + * |[5] |DXPDR |Data Power Down Receiver + * | | |Powers down, when set, the input receiver on I/O for DQ, DM, and DQS/DQS# pins of the byte + * | | |This bit is ORed with the common PDR configuration bit (see "DATX8 Common Configuration Register (DXCCR)"). + * |[6] |DQSRPD |DQSR Power Down + * | | |Powers down, if set, the PDQSR cell + * | | |This bit is ORed with the common PDR configuration bit (see "DATX8 Common Configuration Register (DXCCR)") + * |[8:7] |DSEN |Write DQS Enable + * | | |Controls whether the write DQS going to the SDRAM is enabled (toggling) or disabled (static value) and whether the DQS is inverted + * | | |DQS# is always the inversion of DQS + * | | |These values are valid only when DQS/DQS# output enable is on, otherwise the DQS/DQS# is tristated + * | | |Valid settings are: + * | | |00 = Reserved + * | | |01 = DQS toggling with normal polarity (This should be the default setting) + * | | |10 = Reserved + * | | |11 = Reserved + * |[9] |DQSRTT |DQS Dynamic RTT Control + * | | |If set, the on die termination (ODT) control of the DQS/DQS# SSTL I/O is dynamically generated to enable the ODT during read operation and disabled otherwise + * | | |By setting this bit to '0' the dynamic ODT feature is disabled + * | | |To control ODT statically this bit must be set to '0' and DXnGCR0[1] (DQSODT) is used to enable ODT (when set to '1') or disable ODT(when set to '0'). + * |[10] |DQRTT |DQ Dynamic RTT Control + * | | |If set, the on die termination (ODT) control of the DQ/DM SSTL I/O is dynamically generated to enable the ODT during read operation and disabled otherwise + * | | |By setting this bit to '0' the dynamic ODT feature is disabled + * | | |To control ODT statically this bit must be set to '0' and DXnGCR0[2] (DQODT) is used to enable ODT (when set to '1') or disable ODT(when set to '0'). + * |[12:11] |RTTOH |RTT Output Hold + * | | |Indicates the number of clock cycles (from 0 to 3) after the read data postamble for which ODT control should remain set to DQSODT for DQS or DQODT for DQ/DM before disabling it (setting it to '0') when using dynamic ODT control + * | | |ODT is disabled almost RTTOH clock cycles after the read postamble. + * |[13] |RTTOAL |RTT On Additive Latency + * | | |Indicates when the ODT control of DQ/DQS SSTL I/Os is set to the value in DQODT/DQSODT during read cycles + * | | |Valid values are: + * | | |0 = ODT control is set to DQSODT/DQODT almost two cycles before read data preamble + * | | |1 = ODT control is set to DQSODT/DQODT almost one cycle before read data preamble + * |[15:14] |DXOEO |Data Byte Output Enable Override + * | | |Specifies whether the output I/O output enable for the byte lane should be set to a fixed value + * | | |Valid values are: + * | | |00 = No override. Output enable is controlled by DFI transactions + * | | |01 = Output enable is asserted (I/O is forced to output mode). + * | | |10 = Output enable is de-asserted (I/O is forced to input mode) + * | | |11 = Reserved + * |[16] |PLLRST |PLL Rest + * | | |Resets the byte PLL by driving the PLL reset pin + * | | |This bit is not self- clearing and a '0' must be written to de-assert the reset + * | | |This bit is ORed with the global PLLRST configuration bit. + * |[17] |PLLPD |PLL Power Down + * | | |Puts the byte PLL in Power-down mode by driving the PLL power down pin + * | | |This bit is not self-clearing and a '0' must be written to de-assert the power-down + * | | |This bit is ORed with the global PLLPD configuration bit. + * |[18] |GSHIFT |Gear Shift + * | | |Enables, if set, rapid locking mode on the byte PLL + * | | |This bit is ORed with the global GSHIFT configuration bit. + * |[19] |PLLBYP |PLL Bypass + * | | |Puts the byte PLL in bypass mode by driving the PLL bypass pin + * | | |This bit is not self-clearing and a '0' must be written to de-assert the bypass + * | | |This bit is ORed with the global BYP configuration bit. + * |[29:26] |WLRKEN |Write Level Rank Enable + * | | |Specifies the ranks that should be write leveled for this byte + * | | |Write leveling responses from ranks that are not enabled for write leveling for a particular byte are ignored and write leveling is flagged as done for these ranks + * | | |WLRKEN[0] enables rank 0, [1] enables rank 1, [2] enables rank 2, and [3] enables rank 3. + * |[30] |MDLEN |Master Delay Line Enable + * | | |Enables, if set, the DATX8 master delay line calibration to perform subsequent period measurements following the initial period measurements that are performed after reset or when calibration is manually triggered + * | | |These additional measurements are accumulated and filtered as long as this bit remains high + * | | |This bit is ANDed with the common DATX8 MDL enable bit. + * |[31] |CALBYP |Calibration Bypass + * | | |Prevents, if set, period measurement calibration from automatically triggering after PHY initialization. + * @var DDRPHY_T::DX2GSR0 + * Offset: 0x244 DATX8 General Status Registers 0 (DXnGSR0) + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[0] |WDQCAL |Write DQ Calibration + * | | |Indicates, if set, that the DATX8 has finished doing period measurement calibration for the write DQ LCDL. + * |[1] |RDQSCAL |Read DQS Calibration + * | | |Indicates, if set, that the DATX8 has finished doing period measurement calibration for the read DQS LCDL. + * |[2] |RDQSNCAL |Read DQS# Calibration + * | | |Indicates, if set, that the DATX8 has finished doing period measurement calibration for the read DQS# LCDL. + * |[3] |GDQSCAL |Read DQS gating Calibration + * | | |Indicates, if set, that the DATX8 has finished doing period measurement calibration for the read DQS gating LCDL. + * |[4] |WLCAL |Write Leveling Calibration + * | | |Indicates, if set, that the DATX8 has finished doing period measurement calibration for the write leveling slave delay line. + * |[5] |WLDONE |Write Leveling Done + * | | |Indicates, if set, that the DATX8 has completed write leveling. + * |[6] |WLERR |Write Leveling Error + * | | |Indicates, if set, that there is a write leveling error in the DATX8. + * |[14:7] |WLPRD |Write Leveling Period + * | | |Returns the DDR clock period measured by the write leveling LCDL during calibration + * | | |The measured period is used to generate the control of the write leveling pipeline which is a function of the write-leveling delay and the clock period + * | | |This value is PVT compensated. + * |[15] |DPLOCK |DATX8 PLL Lock + * | | |Indicates, if set, that the DATX8 PLL has locked. This is a direct status of the DATX8 PLL lock pin. + * |[23:16] |GDQSPRD |Read DQS gating Period + * | | |Returns the DDR clock period measured by the read DQS gating LCDL during calibration + * | | |This value is PVT compensated. + * |[27:24] |QSGERR |DQS Gate Training Error + * | | |Indicates, if set, that there is an error in DQS gate training. One bit for each of the up to 4 ranks. + * |[28] |WLDQ |Write Leveling DQ Status + * | | |Captures the write leveling DQ status from the DRAM during software write leveling. + * @var DDRPHY_T::DX2GSR1 + * Offset: 0x248 DATX8 General Status Registers 1 (DXnGSR1) + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[0] |DLTDONE |Delay Line Test Done + * | | |Indicates, if set, that the PHY control block has finished doing period measurement of the DATX8 delay line digital test output. + * |[24:1] |DLTCODE |Delay Line Test Code + * | | |Returns the code measured by the PHY control block that corresponds to the period of the DATX8 delay line digital test output. + * @var DDRPHY_T::DX2BDLR0 + * Offset: 0x24C DATX8 Bit Delay Line Register 0 (DXnBDLR0) + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[5:0] |DQ0WBD |DQ0 Write Bit Delay + * | | |Delay select for the BDL on DQ0 write path. + * |[11:6] |DQ1WBD |DQ1 Write Bit Delay + * | | |Delay select for the BDL on DQ1 write path. + * |[17:12] |DQ2WBD |DQ2 Write Bit Delay + * | | |Delay select for the BDL on DQ2 write path. + * |[23:18] |DQ3WBD |DQ3 Write Bit Delay + * | | |Delay select for the BDL on DQ3 write path + * |[29:24] |DQ4WBD |DQ4 Write Bit Delay + * | | |Delay select for the BDL on DQ4 write path. + * @var DDRPHY_T::DX2BDLR1 + * Offset: 0x250 DATX8 Bit Delay Line Register 1 (DXnBDLR1) + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[5:0] |DQ5WBD |DQ5 Write Bit Delay + * | | |Delay select for the BDL on DQ5 write path. + * |[11:6] |DQ6WBD |DQ6 Write Bit Delay + * | | |Delay select for the BDL on DQ6 write path. + * |[17:12] |DQ7WBD |DQ7 Write Bit Delay + * | | |Delay select for the BDL on DQ7 write path. + * |[23:18] |DMWBD |DM Write Bit Delay + * | | |Delay select for the BDL on DM write path. + * |[29:24] |DSWBD |DQS Write Bit Delay + * | | |Delay select for the BDL on DQS write path + * @var DDRPHY_T::DX2BDLR2 + * Offset: 0x254 DATX8 Bit Delay Line Register 2 (DXnBDLR2) + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[5:0] |DSOEBD |DQS Output Enable Bit Delay + * | | |Delay select for the BDL on DQS output enable path + * |[11:6] |DQOEBD |DQ Output Enable Bit Delay + * | | |Delay select for the BDL on DQ/DM output enable path. + * |[17:12] |DSRBD |DQS Read Bit Delay + * | | |Delay select for the BDL on DQS read path + * |[23:18] |DSNRBD |DQSN Read Bit Delay + * | | |Delay select for the BDL on DQSN read path + * @var DDRPHY_T::DX2BDLR3 + * Offset: 0x258 DATX8 Bit Delay Line Register 3 (DXnBDLR3) + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[5:0] |DQ0RBD |DQ0 Read Bit Delay + * | | |Delay select for the BDL on DQ0 read path. + * |[11:6] |DQ1RBD |DQ1 Read Bit Delay + * | | |Delay select for the BDL on DQ1 read path. + * |[17:12] |DQ2RBD |DQ2 Read Bit Delay + * | | |Delay select for the BDL on DQ2 read path. + * |[23:18] |DQ3RBD |DQ3 Read Bit Delay + * | | |Delay select for the BDL on DQ3 read path + * |[29:24] |DQ4RBD |DQ4 Read Bit Delay + * | | |Delay select for the BDL on DQ4 read path. + * @var DDRPHY_T::DX2BDLR4 + * Offset: 0x25C DATX8 Bit Delay Line Register 4 (DXnBDLR4) + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[5:0] |DQ5RBD |DQ5 Read Bit Delay + * | | |Delay select for the BDL on DQ5 read path. + * |[11:6] |DQ6RBD |DQ6 Read Bit Delay + * | | |Delay select for the BDL on DQ6 read path. + * |[17:12] |DQ7RBD |DQ7 Read Bit Delay + * | | |Delay select for the BDL on DQ7 read path. + * |[23:18] |DMRBD |DM Read Bit Delay + * | | |Delay select for the BDL on DM read path. + * @var DDRPHY_T::DX2LCDLR0 + * Offset: 0x260 DATX8 Bit Delay Line Register 0 (DXnBDLR0) + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[7:0] |R0WLD |Rank 0 Write Leveling Delay + * | | |Rank 0 delay select for the write leveling (WL) LCDL + * |[15:8] |R1WLD |Rank 1 Write Leveling Delay + * | | |Rank 1 delay select for the write leveling (WL) LCDL + * |[23:16] |R2WLD |Rank 2 Write Leveling Delay + * | | |Rank 2 delay select for the write leveling (WL) LCDL + * |[31:24] |R3WLD |Rank 3 Write Leveling Delay + * | | |Rank 3 delay select for the write leveling (WL) LCDL + * @var DDRPHY_T::DX2LCDLR1 + * Offset: 0x264 DATX8 Bit Delay Line Register 1 (DXnBDLR1) + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[7:0] |WDQD |Write Data Delay + * | | |Delay select for the write data (WDQ) LCDL + * |[15:8] |RDQSD |Read DQS Delay + * | | |Delay select for the read DQS (RDQS) LCDL + * |[23:16] |RDQSND |Read DQSN Delay + * | | |Delay select for the read DQSN (RDQS) LCDL + * @var DDRPHY_T::DX2LCDLR2 + * Offset: 0x268 DATX8 Bit Delay Line Register 2 (DXnBDLR2) + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[7:0] |R0DQSGD |Rank 0 Read DQS Gating Delay + * | | |Rank 0 delay select for the read DQS gating (DQSG) LCDL + * |[15:8] |R1DQSGD |Rank 1 Read DQS Gating Delay + * | | |Rank 1 delay select for the read DQS gating (DQSG) LCDL + * |[23:16] |R2DQSGD |Rank 2 Read DQS Gating Delay + * | | |Rank 2 delay select for the read DQS gating (DQSG) LCDL + * |[31:24] |R3DQSGD |Rank 3 Read DQS Gating Delay + * | | |Rank 3 delay select for the read DQS gating (DQSG) LCDL + * @var DDRPHY_T::DX2MDLR + * Offset: 0x26C DATX8 Master Delay Line Register (DXnMDLR) + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[7:0] |IPRD |Initial Period + * | | |Initial period measured by the master delay line calibration for VT drift compensation + * | | |This value is used as the denominator when calculating the ratios of updates during VT compensation. + * |[15:8] |TPRD |Target Period + * | | |Target period measured by the master delay line calibration for VT drift compensation + * | | |This is the current measured value of the period and is continuously updated if the MDL is enabled to do so. + * |[23:16] |MDLD |MDL Delay + * | | |Delay select for the LCDL for the Master Delay Line. + * @var DDRPHY_T::DX2GTR + * Offset: 0x270 DATX8 General Timing Register (DXnGTR) + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[2:0] |R0DGSL |Rank n DQS Gating System Latency + * | | |This is used to increase the number of clock cycles needed to expect valid DDR read data by up to seven extra clock cycles + * | | |This is used to compensate for board delays and other system delays + * | | |Power-up default is 000 (i.e + * | | |no extra clock cycles required) + * | | |The SL fields are initially set by the PUB during automatic DQS data training but these values can be overwritten by a direct write to this register + * | | |Every three bits of this register control the latency of each of the (up to) four ranks + * | | |R0DGSL controls the latency of rank 0, R1DGSL controls rank 1, and so on + * | | |Valid values are 0 to 7. + * |[5:3] |R1DGSL |Rank n DQS Gating System Latency + * | | |This is used to increase the number of clock cycles needed to expect valid DDR read data by up to seven extra clock cycles + * | | |This is used to compensate for board delays and other system delays + * | | |Power-up default is 000 (i.e + * | | |no extra clock cycles required) + * | | |The SL fields are initially set by the PUB during automatic DQS data training but these values can be overwritten by a direct write to this register + * | | |Every three bits of this register control the latency of each of the (up to) four ranks + * | | |R0DGSL controls the latency of rank 0, R1DGSL controls rank 1, and so on + * | | |Valid values are 0 to 7. + * |[8:6] |R2DGSL |Rank n DQS Gating System Latency + * | | |This is used to increase the number of clock cycles needed to expect valid DDR read data by up to seven extra clock cycles + * | | |This is used to compensate for board delays and other system delays + * | | |Power-up default is 000 (i.e + * | | |no extra clock cycles required) + * | | |The SL fields are initially set by the PUB during automatic DQS data training but these values can be overwritten by a direct write to this register + * | | |Every three bits of this register control the latency of each of the (up to) four ranks + * | | |R0DGSL controls the latency of rank 0, R1DGSL controls rank 1, and so on + * | | |Valid values are 0 to 7. + * |[11:9] |R3DGSL |Rank n DQS Gating System Latency + * | | |This is used to increase the number of clock cycles needed to expect valid DDR read data by up to seven extra clock cycles + * | | |This is used to compensate for board delays and other system delays + * | | |Power-up default is 000 (i.e + * | | |no extra clock cycles required) + * | | |The SL fields are initially set by the PUB during automatic DQS data training but these values can be overwritten by a direct write to this register + * | | |Every three bits of this register control the latency of each of the (up to) four ranks + * | | |R0DGSL controls the latency of rank 0, R1DGSL controls rank 1, and so on + * | | |Valid values are 0 to 7. + * |[13:12] |R0WLSL |Rank n Write Leveling System Latency + * | | |This is used to adjust the write latency after write leveling + * | | |Power-up default is 01 (i.e + * | | |no extra clock cycles required) + * | | |The SL fields are initially set by the PUB during automatic write leveling but these values can be overwritten by a direct write to this register + * | | |Every two bits of this register control the latency of each of the (up to) four ranks + * | | |R0WLSL controls the latency of rank 0, R1WLSL controls rank 1, and so on + * | | |Valid values: + * | | |00 = Write latency = WL - 1 + * | | |01 = Write latency = WL + * | | |10 = Write latency = WL + 1 + * | | |11 = Reserved + * |[15:14] |R1WLSL |Rank n Write Leveling System Latency + * | | |This is used to adjust the write latency after write leveling + * | | |Power-up default is 01 (i.e + * | | |no extra clock cycles required) + * | | |The SL fields are initially set by the PUB during automatic write leveling but these values can be overwritten by a direct write to this register + * | | |Every two bits of this register control the latency of each of the (up to) four ranks + * | | |R0WLSL controls the latency of rank 0, R1WLSL controls rank 1, and so on + * | | |Valid values: + * | | |00 = Write latency = WL - 1 + * | | |01 = Write latency = WL + * | | |10 = Write latency = WL + 1 + * | | |11 = Reserved + * |[17:16] |R2WLSL |Rank n Write Leveling System Latency + * | | |This is used to adjust the write latency after write leveling + * | | |Power-up default is 01 (i.e + * | | |no extra clock cycles required) + * | | |The SL fields are initially set by the PUB during automatic write leveling but these values can be overwritten by a direct write to this register + * | | |Every two bits of this register control the latency of each of the (up to) four ranks + * | | |R0WLSL controls the latency of rank 0, R1WLSL controls rank 1, and so on + * | | |Valid values: + * | | |00 = Write latency = WL - 1 + * | | |01 = Write latency = WL + * | | |10 = Write latency = WL + 1 + * | | |11 = Reserved + * |[19:18] |R3WLSL |Rank n Write Leveling System Latency + * | | |This is used to adjust the write latency after write leveling + * | | |Power-up default is 01 (i.e + * | | |no extra clock cycles required) + * | | |The SL fields are initially set by the PUB during automatic write leveling but these values can be overwritten by a direct write to this register + * | | |Every two bits of this register control the latency of each of the (up to) four ranks + * | | |R0WLSL controls the latency of rank 0, R1WLSL controls rank 1, and so on + * | | |Valid values: + * | | |00 = Write latency = WL - 1 + * | | |01 = Write latency = WL + * | | |10 = Write latency = WL + 1 + * | | |11 = Reserved + * @var DDRPHY_T::DX2GSR2 + * Offset: 0x274 DATX8 General Status Register 2 (DXnGSR2) + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[0] |RDERR |Read Bit Deskew Error + * | | |Indicates, if set, that the DATX8 has encountered an error during execution of the read bit deskew training. + * |[1] |RDWN |Read Bit Deskew Warning + * | | |Indicates, if set, that the DATX8 has encountered a warning during execution of the read bit deskew training. + * |[2] |WDERR |Write Bit Deskew Error + * | | |Indicates, if set, that the DATX8 has encountered an error during execution of the write bit deskew training. + * |[3] |WDWN |Write Bit Deskew Warning + * | | |Indicates, if set, that the DATX8 has encountered a warning during execution of the write bit deskew training. + * |[4] |REERR |Read Data Eye Training Error + * | | |Indicates, if set, that the DATX8 has encountered an error during execution of the read data eye training. + * |[5] |REWN |Read Data Eye Training Warning + * | | |Indicates, if set, that the DATX8 has encountered a warning during execution of the read data eye training. + * |[6] |WEERR |Write Data Eye Training Error + * | | |Indicates, if set, that the DATX8 has encountered an error during execution of the write data eye training. + * |[7] |WEWN |Write Data Eye Training Warning + * | | |Indicates, if set, that the DATX8 has encountered a warning during execution of the write data eye training. + * |[11:8] |ESTAT |Error Status + * | | |If an error occurred for this lane as indicated by RDERR, WDERR, REERR or WEERR the error status code can provide additional information regard when the error occurred during the algorithm execution. + * @var DDRPHY_T::DX3GCR + * Offset: 0x280 DATX8 General Configuration Register (DXnGCR) + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[0] |DXEN |Data Byte Enable + * | | |Enables, if set, the data byte + * | | |Setting this bit to '0' disables the byte, i.e + * | | |the byte is not used in PHY initialization or training and is ignored during SDRAM read/write operations. + * |[1] |DQSODT |DQS On-Die Termination + * | | |Enables, when set, the on-die termination on the I/O for DQS/DQS# pin of the byte + * | | |This bit is ORed with the common DATX8 ODT configuration bit (see "DATX8 Common Configuration Register (DXCCR)"). + * | | |Note: This bit is only valid when DXnGCR0[9] is '0'. + * |[2] |DQODT |Data On-Die Termination + * | | |Enables, when set, the on-die termination on the I/O for DQ and DM pins of the byte + * | | |This bit is ORed with the common DATX8 ODT configuration bit (see "DATX8 Common Configuration Register (DXCCR)"). + * | | |Note: This bit is only valid when DXnGCR0[10] is '0'. + * |[3] |DXIOM |Data I/O Mode + * | | |Selects SSTL mode (when set to 0) or CMOS mode (when set to 1) of the I/O for DQ, DM, and DQS/DQS# pins of the byte + * | | |This bit is ORed with the IOM configuration bit of the individual DATX8(see "DATX8 Common Configuration Register (DXCCR)"). + * |[4] |DXPDD |Data Power Down Driver + * | | |Powers down, when set, the output driver on I/O for DQ, DM, and DQS/DQS# pins of the byte + * | | |This bit is ORed with the common PDD configuration bit (see "DATX8 Common Configuration Register (DXCCR)"). + * | | |Note: Asserting PDD puts the IO driver cell into a lower power, lower speed mode of operation + * | | |However, it will still drive if its OE is asserted + * | | |ODT will be disabled (if used) + * | | |Asserting PDD does not prevent the IO from driving. + * |[5] |DXPDR |Data Power Down Receiver + * | | |Powers down, when set, the input receiver on I/O for DQ, DM, and DQS/DQS# pins of the byte + * | | |This bit is ORed with the common PDR configuration bit (see "DATX8 Common Configuration Register (DXCCR)"). + * |[6] |DQSRPD |DQSR Power Down + * | | |Powers down, if set, the PDQSR cell + * | | |This bit is ORed with the common PDR configuration bit (see "DATX8 Common Configuration Register (DXCCR)") + * |[8:7] |DSEN |Write DQS Enable + * | | |Controls whether the write DQS going to the SDRAM is enabled (toggling) or disabled (static value) and whether the DQS is inverted + * | | |DQS# is always the inversion of DQS + * | | |These values are valid only when DQS/DQS# output enable is on, otherwise the DQS/DQS# is tristated + * | | |Valid settings are: + * | | |00 = Reserved + * | | |01 = DQS toggling with normal polarity (This should be the default setting) + * | | |10 = Reserved + * | | |11 = Reserved + * |[9] |DQSRTT |DQS Dynamic RTT Control + * | | |If set, the on die termination (ODT) control of the DQS/DQS# SSTL I/O is dynamically generated to enable the ODT during read operation and disabled otherwise + * | | |By setting this bit to '0' the dynamic ODT feature is disabled + * | | |To control ODT statically this bit must be set to '0' and DXnGCR0[1] (DQSODT) is used to enable ODT (when set to '1') or disable ODT(when set to '0'). + * |[10] |DQRTT |DQ Dynamic RTT Control + * | | |If set, the on die termination (ODT) control of the DQ/DM SSTL I/O is dynamically generated to enable the ODT during read operation and disabled otherwise + * | | |By setting this bit to '0' the dynamic ODT feature is disabled + * | | |To control ODT statically this bit must be set to '0' and DXnGCR0[2] (DQODT) is used to enable ODT (when set to '1') or disable ODT(when set to '0'). + * |[12:11] |RTTOH |RTT Output Hold + * | | |Indicates the number of clock cycles (from 0 to 3) after the read data postamble for which ODT control should remain set to DQSODT for DQS or DQODT for DQ/DM before disabling it (setting it to '0') when using dynamic ODT control + * | | |ODT is disabled almost RTTOH clock cycles after the read postamble. + * |[13] |RTTOAL |RTT On Additive Latency + * | | |Indicates when the ODT control of DQ/DQS SSTL I/Os is set to the value in DQODT/DQSODT during read cycles + * | | |Valid values are: + * | | |0 = ODT control is set to DQSODT/DQODT almost two cycles before read data preamble + * | | |1 = ODT control is set to DQSODT/DQODT almost one cycle before read data preamble + * |[15:14] |DXOEO |Data Byte Output Enable Override + * | | |Specifies whether the output I/O output enable for the byte lane should be set to a fixed value + * | | |Valid values are: + * | | |00 = No override. Output enable is controlled by DFI transactions + * | | |01 = Output enable is asserted (I/O is forced to output mode). + * | | |10 = Output enable is de-asserted (I/O is forced to input mode) + * | | |11 = Reserved + * |[16] |PLLRST |PLL Rest + * | | |Resets the byte PLL by driving the PLL reset pin + * | | |This bit is not self- clearing and a '0' must be written to de-assert the reset + * | | |This bit is ORed with the global PLLRST configuration bit. + * |[17] |PLLPD |PLL Power Down + * | | |Puts the byte PLL in Power-down mode by driving the PLL power down pin + * | | |This bit is not self-clearing and a '0' must be written to de-assert the power-down + * | | |This bit is ORed with the global PLLPD configuration bit. + * |[18] |GSHIFT |Gear Shift + * | | |Enables, if set, rapid locking mode on the byte PLL + * | | |This bit is ORed with the global GSHIFT configuration bit. + * |[19] |PLLBYP |PLL Bypass + * | | |Puts the byte PLL in bypass mode by driving the PLL bypass pin + * | | |This bit is not self-clearing and a '0' must be written to de-assert the bypass + * | | |This bit is ORed with the global BYP configuration bit. + * |[29:26] |WLRKEN |Write Level Rank Enable + * | | |Specifies the ranks that should be write leveled for this byte + * | | |Write leveling responses from ranks that are not enabled for write leveling for a particular byte are ignored and write leveling is flagged as done for these ranks + * | | |WLRKEN[0] enables rank 0, [1] enables rank 1, [2] enables rank 2, and [3] enables rank 3. + * |[30] |MDLEN |Master Delay Line Enable + * | | |Enables, if set, the DATX8 master delay line calibration to perform subsequent period measurements following the initial period measurements that are performed after reset or when calibration is manually triggered + * | | |These additional measurements are accumulated and filtered as long as this bit remains high + * | | |This bit is ANDed with the common DATX8 MDL enable bit. + * |[31] |CALBYP |Calibration Bypass + * | | |Prevents, if set, period measurement calibration from automatically triggering after PHY initialization. + * @var DDRPHY_T::DX3GSR0 + * Offset: 0x284 DATX8 General Status Registers 0 (DXnGSR0) + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[0] |WDQCAL |Write DQ Calibration + * | | |Indicates, if set, that the DATX8 has finished doing period measurement calibration for the write DQ LCDL. + * |[1] |RDQSCAL |Read DQS Calibration + * | | |Indicates, if set, that the DATX8 has finished doing period measurement calibration for the read DQS LCDL. + * |[2] |RDQSNCAL |Read DQS# Calibration + * | | |Indicates, if set, that the DATX8 has finished doing period measurement calibration for the read DQS# LCDL. + * |[3] |GDQSCAL |Read DQS gating Calibration + * | | |Indicates, if set, that the DATX8 has finished doing period measurement calibration for the read DQS gating LCDL. + * |[4] |WLCAL |Write Leveling Calibration + * | | |Indicates, if set, that the DATX8 has finished doing period measurement calibration for the write leveling slave delay line. + * |[5] |WLDONE |Write Leveling Done + * | | |Indicates, if set, that the DATX8 has completed write leveling. + * |[6] |WLERR |Write Leveling Error + * | | |Indicates, if set, that there is a write leveling error in the DATX8. + * |[14:7] |WLPRD |Write Leveling Period + * | | |Returns the DDR clock period measured by the write leveling LCDL during calibration + * | | |The measured period is used to generate the control of the write leveling pipeline which is a function of the write-leveling delay and the clock period + * | | |This value is PVT compensated. + * |[15] |DPLOCK |DATX8 PLL Lock + * | | |Indicates, if set, that the DATX8 PLL has locked. This is a direct status of the DATX8 PLL lock pin. + * |[23:16] |GDQSPRD |Read DQS gating Period + * | | |Returns the DDR clock period measured by the read DQS gating LCDL during calibration + * | | |This value is PVT compensated. + * |[27:24] |QSGERR |DQS Gate Training Error + * | | |Indicates, if set, that there is an error in DQS gate training. One bit for each of the up to 4 ranks. + * |[28] |WLDQ |Write Leveling DQ Status + * | | |Captures the write leveling DQ status from the DRAM during software write leveling. + * @var DDRPHY_T::DX3GSR1 + * Offset: 0x288 DATX8 General Status Registers 1 (DXnGSR1) + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[0] |DLTDONE |Delay Line Test Done + * | | |Indicates, if set, that the PHY control block has finished doing period measurement of the DATX8 delay line digital test output. + * |[24:1] |DLTCODE |Delay Line Test Code + * | | |Returns the code measured by the PHY control block that corresponds to the period of the DATX8 delay line digital test output. + * @var DDRPHY_T::DX3BDLR0 + * Offset: 0x28C DATX8 Bit Delay Line Register 0 (DXnBDLR0) + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[5:0] |DQ0WBD |DQ0 Write Bit Delay + * | | |Delay select for the BDL on DQ0 write path. + * |[11:6] |DQ1WBD |DQ1 Write Bit Delay + * | | |Delay select for the BDL on DQ1 write path. + * |[17:12] |DQ2WBD |DQ2 Write Bit Delay + * | | |Delay select for the BDL on DQ2 write path. + * |[23:18] |DQ3WBD |DQ3 Write Bit Delay + * | | |Delay select for the BDL on DQ3 write path + * |[29:24] |DQ4WBD |DQ4 Write Bit Delay + * | | |Delay select for the BDL on DQ4 write path. + * @var DDRPHY_T::DX3BDLR1 + * Offset: 0x290 DATX8 Bit Delay Line Register 1 (DXnBDLR1) + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[5:0] |DQ5WBD |DQ5 Write Bit Delay + * | | |Delay select for the BDL on DQ5 write path. + * |[11:6] |DQ6WBD |DQ6 Write Bit Delay + * | | |Delay select for the BDL on DQ6 write path. + * |[17:12] |DQ7WBD |DQ7 Write Bit Delay + * | | |Delay select for the BDL on DQ7 write path. + * |[23:18] |DMWBD |DM Write Bit Delay + * | | |Delay select for the BDL on DM write path. + * |[29:24] |DSWBD |DQS Write Bit Delay + * | | |Delay select for the BDL on DQS write path + * @var DDRPHY_T::DX3BDLR2 + * Offset: 0x294 DATX8 Bit Delay Line Register 2 (DXnBDLR2) + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[5:0] |DSOEBD |DQS Output Enable Bit Delay + * | | |Delay select for the BDL on DQS output enable path + * |[11:6] |DQOEBD |DQ Output Enable Bit Delay + * | | |Delay select for the BDL on DQ/DM output enable path. + * |[17:12] |DSRBD |DQS Read Bit Delay + * | | |Delay select for the BDL on DQS read path + * |[23:18] |DSNRBD |DQSN Read Bit Delay + * | | |Delay select for the BDL on DQSN read path + * @var DDRPHY_T::DX3BDLR3 + * Offset: 0x298 DATX8 Bit Delay Line Register 3 (DXnBDLR3) + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[5:0] |DQ0RBD |DQ0 Read Bit Delay + * | | |Delay select for the BDL on DQ0 read path. + * |[11:6] |DQ1RBD |DQ1 Read Bit Delay + * | | |Delay select for the BDL on DQ1 read path. + * |[17:12] |DQ2RBD |DQ2 Read Bit Delay + * | | |Delay select for the BDL on DQ2 read path. + * |[23:18] |DQ3RBD |DQ3 Read Bit Delay + * | | |Delay select for the BDL on DQ3 read path + * |[29:24] |DQ4RBD |DQ4 Read Bit Delay + * | | |Delay select for the BDL on DQ4 read path. + * @var DDRPHY_T::DX3BDLR4 + * Offset: 0x29C DATX8 Bit Delay Line Register 4 (DXnBDLR4) + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[5:0] |DQ5RBD |DQ5 Read Bit Delay + * | | |Delay select for the BDL on DQ5 read path. + * |[11:6] |DQ6RBD |DQ6 Read Bit Delay + * | | |Delay select for the BDL on DQ6 read path. + * |[17:12] |DQ7RBD |DQ7 Read Bit Delay + * | | |Delay select for the BDL on DQ7 read path. + * |[23:18] |DMRBD |DM Read Bit Delay + * | | |Delay select for the BDL on DM read path. + * @var DDRPHY_T::DX3LCDLR0 + * Offset: 0x2A0 DATX8 Bit Delay Line Register 0 (DXnBDLR0) + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[7:0] |R0WLD |Rank 0 Write Leveling Delay + * | | |Rank 0 delay select for the write leveling (WL) LCDL + * |[15:8] |R1WLD |Rank 1 Write Leveling Delay + * | | |Rank 1 delay select for the write leveling (WL) LCDL + * |[23:16] |R2WLD |Rank 2 Write Leveling Delay + * | | |Rank 2 delay select for the write leveling (WL) LCDL + * |[31:24] |R3WLD |Rank 3 Write Leveling Delay + * | | |Rank 3 delay select for the write leveling (WL) LCDL + * @var DDRPHY_T::DX3LCDLR1 + * Offset: 0x2A4 DATX8 Bit Delay Line Register 1 (DXnBDLR1) + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[7:0] |WDQD |Write Data Delay + * | | |Delay select for the write data (WDQ) LCDL + * |[15:8] |RDQSD |Read DQS Delay + * | | |Delay select for the read DQS (RDQS) LCDL + * |[23:16] |RDQSND |Read DQSN Delay + * | | |Delay select for the read DQSN (RDQS) LCDL + * @var DDRPHY_T::DX3LCDLR2 + * Offset: 0x2A8 DATX8 Bit Delay Line Register 2 (DXnBDLR2) + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[7:0] |R0DQSGD |Rank 0 Read DQS Gating Delay + * | | |Rank 0 delay select for the read DQS gating (DQSG) LCDL + * |[15:8] |R1DQSGD |Rank 1 Read DQS Gating Delay + * | | |Rank 1 delay select for the read DQS gating (DQSG) LCDL + * |[23:16] |R2DQSGD |Rank 2 Read DQS Gating Delay + * | | |Rank 2 delay select for the read DQS gating (DQSG) LCDL + * |[31:24] |R3DQSGD |Rank 3 Read DQS Gating Delay + * | | |Rank 3 delay select for the read DQS gating (DQSG) LCDL + * @var DDRPHY_T::DX3MDLR + * Offset: 0x2AC DATX8 Master Delay Line Register (DXnMDLR) + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[7:0] |IPRD |Initial Period + * | | |Initial period measured by the master delay line calibration for VT drift compensation + * | | |This value is used as the denominator when calculating the ratios of updates during VT compensation. + * |[15:8] |TPRD |Target Period + * | | |Target period measured by the master delay line calibration for VT drift compensation + * | | |This is the current measured value of the period and is continuously updated if the MDL is enabled to do so. + * |[23:16] |MDLD |MDL Delay + * | | |Delay select for the LCDL for the Master Delay Line. + * @var DDRPHY_T::DX3GTR + * Offset: 0x2B0 DATX8 General Timing Register (DXnGTR) + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[2:0] |R0DGSL |Rank n DQS Gating System Latency + * | | |This is used to increase the number of clock cycles needed to expect valid DDR read data by up to seven extra clock cycles + * | | |This is used to compensate for board delays and other system delays + * | | |Power-up default is 000 (i.e + * | | |no extra clock cycles required) + * | | |The SL fields are initially set by the PUB during automatic DQS data training but these values can be overwritten by a direct write to this register + * | | |Every three bits of this register control the latency of each of the (up to) four ranks + * | | |R0DGSL controls the latency of rank 0, R1DGSL controls rank 1, and so on + * | | |Valid values are 0 to 7. + * |[5:3] |R1DGSL |Rank n DQS Gating System Latency + * | | |This is used to increase the number of clock cycles needed to expect valid DDR read data by up to seven extra clock cycles + * | | |This is used to compensate for board delays and other system delays + * | | |Power-up default is 000 (i.e + * | | |no extra clock cycles required) + * | | |The SL fields are initially set by the PUB during automatic DQS data training but these values can be overwritten by a direct write to this register + * | | |Every three bits of this register control the latency of each of the (up to) four ranks + * | | |R0DGSL controls the latency of rank 0, R1DGSL controls rank 1, and so on + * | | |Valid values are 0 to 7. + * |[8:6] |R2DGSL |Rank n DQS Gating System Latency + * | | |This is used to increase the number of clock cycles needed to expect valid DDR read data by up to seven extra clock cycles + * | | |This is used to compensate for board delays and other system delays + * | | |Power-up default is 000 (i.e + * | | |no extra clock cycles required) + * | | |The SL fields are initially set by the PUB during automatic DQS data training but these values can be overwritten by a direct write to this register + * | | |Every three bits of this register control the latency of each of the (up to) four ranks + * | | |R0DGSL controls the latency of rank 0, R1DGSL controls rank 1, and so on + * | | |Valid values are 0 to 7. + * |[11:9] |R3DGSL |Rank n DQS Gating System Latency + * | | |This is used to increase the number of clock cycles needed to expect valid DDR read data by up to seven extra clock cycles + * | | |This is used to compensate for board delays and other system delays + * | | |Power-up default is 000 (i.e + * | | |no extra clock cycles required) + * | | |The SL fields are initially set by the PUB during automatic DQS data training but these values can be overwritten by a direct write to this register + * | | |Every three bits of this register control the latency of each of the (up to) four ranks + * | | |R0DGSL controls the latency of rank 0, R1DGSL controls rank 1, and so on + * | | |Valid values are 0 to 7. + * |[13:12] |R0WLSL |Rank n Write Leveling System Latency + * | | |This is used to adjust the write latency after write leveling + * | | |Power-up default is 01 (i.e + * | | |no extra clock cycles required) + * | | |The SL fields are initially set by the PUB during automatic write leveling but these values can be overwritten by a direct write to this register + * | | |Every two bits of this register control the latency of each of the (up to) four ranks + * | | |R0WLSL controls the latency of rank 0, R1WLSL controls rank 1, and so on + * | | |Valid values: + * | | |00 = Write latency = WL - 1 + * | | |01 = Write latency = WL + * | | |10 = Write latency = WL + 1 + * | | |11 = Reserved + * |[15:14] |R1WLSL |Rank n Write Leveling System Latency + * | | |This is used to adjust the write latency after write leveling + * | | |Power-up default is 01 (i.e + * | | |no extra clock cycles required) + * | | |The SL fields are initially set by the PUB during automatic write leveling but these values can be overwritten by a direct write to this register + * | | |Every two bits of this register control the latency of each of the (up to) four ranks + * | | |R0WLSL controls the latency of rank 0, R1WLSL controls rank 1, and so on + * | | |Valid values: + * | | |00 = Write latency = WL - 1 + * | | |01 = Write latency = WL + * | | |10 = Write latency = WL + 1 + * | | |11 = Reserved + * |[17:16] |R2WLSL |Rank n Write Leveling System Latency + * | | |This is used to adjust the write latency after write leveling + * | | |Power-up default is 01 (i.e + * | | |no extra clock cycles required) + * | | |The SL fields are initially set by the PUB during automatic write leveling but these values can be overwritten by a direct write to this register + * | | |Every two bits of this register control the latency of each of the (up to) four ranks + * | | |R0WLSL controls the latency of rank 0, R1WLSL controls rank 1, and so on + * | | |Valid values: + * | | |00 = Write latency = WL - 1 + * | | |01 = Write latency = WL + * | | |10 = Write latency = WL + 1 + * | | |11 = Reserved + * |[19:18] |R3WLSL |Rank n Write Leveling System Latency + * | | |This is used to adjust the write latency after write leveling + * | | |Power-up default is 01 (i.e + * | | |no extra clock cycles required) + * | | |The SL fields are initially set by the PUB during automatic write leveling but these values can be overwritten by a direct write to this register + * | | |Every two bits of this register control the latency of each of the (up to) four ranks + * | | |R0WLSL controls the latency of rank 0, R1WLSL controls rank 1, and so on + * | | |Valid values: + * | | |00 = Write latency = WL - 1 + * | | |01 = Write latency = WL + * | | |10 = Write latency = WL + 1 + * | | |11 = Reserved + * @var DDRPHY_T::DX3GSR2 + * Offset: 0x2B4 DATX8 General Status Register 2 (DXnGSR2) + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[0] |RDERR |Read Bit Deskew Error + * | | |Indicates, if set, that the DATX8 has encountered an error during execution of the read bit deskew training. + * |[1] |RDWN |Read Bit Deskew Warning + * | | |Indicates, if set, that the DATX8 has encountered a warning during execution of the read bit deskew training. + * |[2] |WDERR |Write Bit Deskew Error + * | | |Indicates, if set, that the DATX8 has encountered an error during execution of the write bit deskew training. + * |[3] |WDWN |Write Bit Deskew Warning + * | | |Indicates, if set, that the DATX8 has encountered a warning during execution of the write bit deskew training. + * |[4] |REERR |Read Data Eye Training Error + * | | |Indicates, if set, that the DATX8 has encountered an error during execution of the read data eye training. + * |[5] |REWN |Read Data Eye Training Warning + * | | |Indicates, if set, that the DATX8 has encountered a warning during execution of the read data eye training. + * |[6] |WEERR |Write Data Eye Training Error + * | | |Indicates, if set, that the DATX8 has encountered an error during execution of the write data eye training. + * |[7] |WEWN |Write Data Eye Training Warning + * | | |Indicates, if set, that the DATX8 has encountered a warning during execution of the write data eye training. + * |[11:8] |ESTAT |Error Status + * | | |If an error occurred for this lane as indicated by RDERR, WDERR, REERR or WEERR the error status code can provide additional information regard when the error occurred during the algorithm execution. + * @var DDRPHY_T::DX4GCR + * Offset: 0x2C0 DATX8 General Configuration Register (DXnGCR) + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[0] |DXEN |Data Byte Enable + * | | |Enables, if set, the data byte + * | | |Setting this bit to '0' disables the byte, i.e + * | | |the byte is not used in PHY initialization or training and is ignored during SDRAM read/write operations. + * |[1] |DQSODT |DQS On-Die Termination + * | | |Enables, when set, the on-die termination on the I/O for DQS/DQS# pin of the byte + * | | |This bit is ORed with the common DATX8 ODT configuration bit (see "DATX8 Common Configuration Register (DXCCR)"). + * | | |Note: This bit is only valid when DXnGCR0[9] is '0'. + * |[2] |DQODT |Data On-Die Termination + * | | |Enables, when set, the on-die termination on the I/O for DQ and DM pins of the byte + * | | |This bit is ORed with the common DATX8 ODT configuration bit (see "DATX8 Common Configuration Register (DXCCR)"). + * | | |Note: This bit is only valid when DXnGCR0[10] is '0'. + * |[3] |DXIOM |Data I/O Mode + * | | |Selects SSTL mode (when set to 0) or CMOS mode (when set to 1) of the I/O for DQ, DM, and DQS/DQS# pins of the byte + * | | |This bit is ORed with the IOM configuration bit of the individual DATX8(see "DATX8 Common Configuration Register (DXCCR)"). + * |[4] |DXPDD |Data Power Down Driver + * | | |Powers down, when set, the output driver on I/O for DQ, DM, and DQS/DQS# pins of the byte + * | | |This bit is ORed with the common PDD configuration bit (see "DATX8 Common Configuration Register (DXCCR)"). + * | | |Note: Asserting PDD puts the IO driver cell into a lower power, lower speed mode of operation + * | | |However, it will still drive if its OE is asserted + * | | |ODT will be disabled (if used) + * | | |Asserting PDD does not prevent the IO from driving. + * |[5] |DXPDR |Data Power Down Receiver + * | | |Powers down, when set, the input receiver on I/O for DQ, DM, and DQS/DQS# pins of the byte + * | | |This bit is ORed with the common PDR configuration bit (see "DATX8 Common Configuration Register (DXCCR)"). + * |[6] |DQSRPD |DQSR Power Down + * | | |Powers down, if set, the PDQSR cell + * | | |This bit is ORed with the common PDR configuration bit (see "DATX8 Common Configuration Register (DXCCR)") + * |[8:7] |DSEN |Write DQS Enable + * | | |Controls whether the write DQS going to the SDRAM is enabled (toggling) or disabled (static value) and whether the DQS is inverted + * | | |DQS# is always the inversion of DQS + * | | |These values are valid only when DQS/DQS# output enable is on, otherwise the DQS/DQS# is tristated + * | | |Valid settings are: + * | | |00 = Reserved + * | | |01 = DQS toggling with normal polarity (This should be the default setting) + * | | |10 = Reserved + * | | |11 = Reserved + * |[9] |DQSRTT |DQS Dynamic RTT Control + * | | |If set, the on die termination (ODT) control of the DQS/DQS# SSTL I/O is dynamically generated to enable the ODT during read operation and disabled otherwise + * | | |By setting this bit to '0' the dynamic ODT feature is disabled + * | | |To control ODT statically this bit must be set to '0' and DXnGCR0[1] (DQSODT) is used to enable ODT (when set to '1') or disable ODT(when set to '0'). + * |[10] |DQRTT |DQ Dynamic RTT Control + * | | |If set, the on die termination (ODT) control of the DQ/DM SSTL I/O is dynamically generated to enable the ODT during read operation and disabled otherwise + * | | |By setting this bit to '0' the dynamic ODT feature is disabled + * | | |To control ODT statically this bit must be set to '0' and DXnGCR0[2] (DQODT) is used to enable ODT (when set to '1') or disable ODT(when set to '0'). + * |[12:11] |RTTOH |RTT Output Hold + * | | |Indicates the number of clock cycles (from 0 to 3) after the read data postamble for which ODT control should remain set to DQSODT for DQS or DQODT for DQ/DM before disabling it (setting it to '0') when using dynamic ODT control + * | | |ODT is disabled almost RTTOH clock cycles after the read postamble. + * |[13] |RTTOAL |RTT On Additive Latency + * | | |Indicates when the ODT control of DQ/DQS SSTL I/Os is set to the value in DQODT/DQSODT during read cycles + * | | |Valid values are: + * | | |0 = ODT control is set to DQSODT/DQODT almost two cycles before read data preamble + * | | |1 = ODT control is set to DQSODT/DQODT almost one cycle before read data preamble + * |[15:14] |DXOEO |Data Byte Output Enable Override + * | | |Specifies whether the output I/O output enable for the byte lane should be set to a fixed value + * | | |Valid values are: + * | | |00 = No override. Output enable is controlled by DFI transactions + * | | |01 = Output enable is asserted (I/O is forced to output mode). + * | | |10 = Output enable is de-asserted (I/O is forced to input mode) + * | | |11 = Reserved + * |[16] |PLLRST |PLL Rest + * | | |Resets the byte PLL by driving the PLL reset pin + * | | |This bit is not self- clearing and a '0' must be written to de-assert the reset + * | | |This bit is ORed with the global PLLRST configuration bit. + * |[17] |PLLPD |PLL Power Down + * | | |Puts the byte PLL in Power-down mode by driving the PLL power down pin + * | | |This bit is not self-clearing and a '0' must be written to de-assert the power-down + * | | |This bit is ORed with the global PLLPD configuration bit. + * |[18] |GSHIFT |Gear Shift + * | | |Enables, if set, rapid locking mode on the byte PLL + * | | |This bit is ORed with the global GSHIFT configuration bit. + * |[19] |PLLBYP |PLL Bypass + * | | |Puts the byte PLL in bypass mode by driving the PLL bypass pin + * | | |This bit is not self-clearing and a '0' must be written to de-assert the bypass + * | | |This bit is ORed with the global BYP configuration bit. + * |[29:26] |WLRKEN |Write Level Rank Enable + * | | |Specifies the ranks that should be write leveled for this byte + * | | |Write leveling responses from ranks that are not enabled for write leveling for a particular byte are ignored and write leveling is flagged as done for these ranks + * | | |WLRKEN[0] enables rank 0, [1] enables rank 1, [2] enables rank 2, and [3] enables rank 3. + * |[30] |MDLEN |Master Delay Line Enable + * | | |Enables, if set, the DATX8 master delay line calibration to perform subsequent period measurements following the initial period measurements that are performed after reset or when calibration is manually triggered + * | | |These additional measurements are accumulated and filtered as long as this bit remains high + * | | |This bit is ANDed with the common DATX8 MDL enable bit. + * |[31] |CALBYP |Calibration Bypass + * | | |Prevents, if set, period measurement calibration from automatically triggering after PHY initialization. + * @var DDRPHY_T::DX4GSR0 + * Offset: 0x2C4 DATX8 General Status Registers 0 (DXnGSR0) + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[0] |WDQCAL |Write DQ Calibration + * | | |Indicates, if set, that the DATX8 has finished doing period measurement calibration for the write DQ LCDL. + * |[1] |RDQSCAL |Read DQS Calibration + * | | |Indicates, if set, that the DATX8 has finished doing period measurement calibration for the read DQS LCDL. + * |[2] |RDQSNCAL |Read DQS# Calibration + * | | |Indicates, if set, that the DATX8 has finished doing period measurement calibration for the read DQS# LCDL. + * |[3] |GDQSCAL |Read DQS gating Calibration + * | | |Indicates, if set, that the DATX8 has finished doing period measurement calibration for the read DQS gating LCDL. + * |[4] |WLCAL |Write Leveling Calibration + * | | |Indicates, if set, that the DATX8 has finished doing period measurement calibration for the write leveling slave delay line. + * |[5] |WLDONE |Write Leveling Done + * | | |Indicates, if set, that the DATX8 has completed write leveling. + * |[6] |WLERR |Write Leveling Error + * | | |Indicates, if set, that there is a write leveling error in the DATX8. + * |[14:7] |WLPRD |Write Leveling Period + * | | |Returns the DDR clock period measured by the write leveling LCDL during calibration + * | | |The measured period is used to generate the control of the write leveling pipeline which is a function of the write-leveling delay and the clock period + * | | |This value is PVT compensated. + * |[15] |DPLOCK |DATX8 PLL Lock + * | | |Indicates, if set, that the DATX8 PLL has locked. This is a direct status of the DATX8 PLL lock pin. + * |[23:16] |GDQSPRD |Read DQS gating Period + * | | |Returns the DDR clock period measured by the read DQS gating LCDL during calibration + * | | |This value is PVT compensated. + * |[27:24] |QSGERR |DQS Gate Training Error + * | | |Indicates, if set, that there is an error in DQS gate training. One bit for each of the up to 4 ranks. + * |[28] |WLDQ |Write Leveling DQ Status + * | | |Captures the write leveling DQ status from the DRAM during software write leveling. + * @var DDRPHY_T::DX4GSR1 + * Offset: 0x2C8 DATX8 General Status Registers 1 (DXnGSR1) + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[0] |DLTDONE |Delay Line Test Done + * | | |Indicates, if set, that the PHY control block has finished doing period measurement of the DATX8 delay line digital test output. + * |[24:1] |DLTCODE |Delay Line Test Code + * | | |Returns the code measured by the PHY control block that corresponds to the period of the DATX8 delay line digital test output. + * @var DDRPHY_T::DX4BDLR0 + * Offset: 0x2CC DATX8 Bit Delay Line Register 0 (DXnBDLR0) + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[5:0] |DQ0WBD |DQ0 Write Bit Delay + * | | |Delay select for the BDL on DQ0 write path. + * |[11:6] |DQ1WBD |DQ1 Write Bit Delay + * | | |Delay select for the BDL on DQ1 write path. + * |[17:12] |DQ2WBD |DQ2 Write Bit Delay + * | | |Delay select for the BDL on DQ2 write path. + * |[23:18] |DQ3WBD |DQ3 Write Bit Delay + * | | |Delay select for the BDL on DQ3 write path + * |[29:24] |DQ4WBD |DQ4 Write Bit Delay + * | | |Delay select for the BDL on DQ4 write path. + * @var DDRPHY_T::DX4BDLR1 + * Offset: 0x2D0 DATX8 Bit Delay Line Register 1 (DXnBDLR1) + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[5:0] |DQ5WBD |DQ5 Write Bit Delay + * | | |Delay select for the BDL on DQ5 write path. + * |[11:6] |DQ6WBD |DQ6 Write Bit Delay + * | | |Delay select for the BDL on DQ6 write path. + * |[17:12] |DQ7WBD |DQ7 Write Bit Delay + * | | |Delay select for the BDL on DQ7 write path. + * |[23:18] |DMWBD |DM Write Bit Delay + * | | |Delay select for the BDL on DM write path. + * |[29:24] |DSWBD |DQS Write Bit Delay + * | | |Delay select for the BDL on DQS write path + * @var DDRPHY_T::DX4BDLR2 + * Offset: 0x2D4 DATX8 Bit Delay Line Register 2 (DXnBDLR2) + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[5:0] |DSOEBD |DQS Output Enable Bit Delay + * | | |Delay select for the BDL on DQS output enable path + * |[11:6] |DQOEBD |DQ Output Enable Bit Delay + * | | |Delay select for the BDL on DQ/DM output enable path. + * |[17:12] |DSRBD |DQS Read Bit Delay + * | | |Delay select for the BDL on DQS read path + * |[23:18] |DSNRBD |DQSN Read Bit Delay + * | | |Delay select for the BDL on DQSN read path + * @var DDRPHY_T::DX4BDLR3 + * Offset: 0x2D8 DATX8 Bit Delay Line Register 3 (DXnBDLR3) + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[5:0] |DQ0RBD |DQ0 Read Bit Delay + * | | |Delay select for the BDL on DQ0 read path. + * |[11:6] |DQ1RBD |DQ1 Read Bit Delay + * | | |Delay select for the BDL on DQ1 read path. + * |[17:12] |DQ2RBD |DQ2 Read Bit Delay + * | | |Delay select for the BDL on DQ2 read path. + * |[23:18] |DQ3RBD |DQ3 Read Bit Delay + * | | |Delay select for the BDL on DQ3 read path + * |[29:24] |DQ4RBD |DQ4 Read Bit Delay + * | | |Delay select for the BDL on DQ4 read path. + * @var DDRPHY_T::DX4BDLR4 + * Offset: 0x2DC DATX8 Bit Delay Line Register 4 (DXnBDLR4) + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[5:0] |DQ5RBD |DQ5 Read Bit Delay + * | | |Delay select for the BDL on DQ5 read path. + * |[11:6] |DQ6RBD |DQ6 Read Bit Delay + * | | |Delay select for the BDL on DQ6 read path. + * |[17:12] |DQ7RBD |DQ7 Read Bit Delay + * | | |Delay select for the BDL on DQ7 read path. + * |[23:18] |DMRBD |DM Read Bit Delay + * | | |Delay select for the BDL on DM read path. + * @var DDRPHY_T::DX4LCDLR0 + * Offset: 0x2E0 DATX8 Bit Delay Line Register 0 (DXnBDLR0) + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[7:0] |R0WLD |Rank 0 Write Leveling Delay + * | | |Rank 0 delay select for the write leveling (WL) LCDL + * |[15:8] |R1WLD |Rank 1 Write Leveling Delay + * | | |Rank 1 delay select for the write leveling (WL) LCDL + * |[23:16] |R2WLD |Rank 2 Write Leveling Delay + * | | |Rank 2 delay select for the write leveling (WL) LCDL + * |[31:24] |R3WLD |Rank 3 Write Leveling Delay + * | | |Rank 3 delay select for the write leveling (WL) LCDL + * @var DDRPHY_T::DX4LCDLR1 + * Offset: 0x2E4 DATX8 Bit Delay Line Register 1 (DXnBDLR1) + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * @var DDRPHY_T::DX4LCDLR2 + * Offset: 0x2E8 DATX8 Bit Delay Line Register 2 (DXnBDLR2) + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[7:0] |R0DQSGD |Rank 0 Read DQS Gating Delay + * | | |Rank 0 delay select for the read DQS gating (DQSG) LCDL + * |[15:8] |R1DQSGD |Rank 1 Read DQS Gating Delay + * | | |Rank 1 delay select for the read DQS gating (DQSG) LCDL + * |[23:16] |R2DQSGD |Rank 2 Read DQS Gating Delay + * | | |Rank 2 delay select for the read DQS gating (DQSG) LCDL + * |[31:24] |R3DQSGD |Rank 3 Read DQS Gating Delay + * | | |Rank 3 delay select for the read DQS gating (DQSG) LCDL + * @var DDRPHY_T::DX4MDLR + * Offset: 0x2EC DATX8 Master Delay Line Register (DXnMDLR) + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[7:0] |IPRD |Initial Period + * | | |Initial period measured by the master delay line calibration for VT drift compensation + * | | |This value is used as the denominator when calculating the ratios of updates during VT compensation. + * |[15:8] |TPRD |Target Period + * | | |Target period measured by the master delay line calibration for VT drift compensation + * | | |This is the current measured value of the period and is continuously updated if the MDL is enabled to do so. + * |[23:16] |MDLD |MDL Delay + * | | |Delay select for the LCDL for the Master Delay Line. + * @var DDRPHY_T::DX4GTR + * Offset: 0x2F0 DATX8 General Timing Register (DXnGTR) + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[2:0] |R0DGSL |Rank n DQS Gating System Latency + * | | |This is used to increase the number of clock cycles needed to expect valid DDR read data by up to seven extra clock cycles + * | | |This is used to compensate for board delays and other system delays + * | | |Power-up default is 000 (i.e + * | | |no extra clock cycles required) + * | | |The SL fields are initially set by the PUB during automatic DQS data training but these values can be overwritten by a direct write to this register + * | | |Every three bits of this register control the latency of each of the (up to) four ranks + * | | |R0DGSL controls the latency of rank 0, R1DGSL controls rank 1, and so on + * | | |Valid values are 0 to 7. + * |[5:3] |R1DGSL |Rank n DQS Gating System Latency + * | | |This is used to increase the number of clock cycles needed to expect valid DDR read data by up to seven extra clock cycles + * | | |This is used to compensate for board delays and other system delays + * | | |Power-up default is 000 (i.e + * | | |no extra clock cycles required) + * | | |The SL fields are initially set by the PUB during automatic DQS data training but these values can be overwritten by a direct write to this register + * | | |Every three bits of this register control the latency of each of the (up to) four ranks + * | | |R0DGSL controls the latency of rank 0, R1DGSL controls rank 1, and so on + * | | |Valid values are 0 to 7. + * |[8:6] |R2DGSL |Rank n DQS Gating System Latency + * | | |This is used to increase the number of clock cycles needed to expect valid DDR read data by up to seven extra clock cycles + * | | |This is used to compensate for board delays and other system delays + * | | |Power-up default is 000 (i.e + * | | |no extra clock cycles required) + * | | |The SL fields are initially set by the PUB during automatic DQS data training but these values can be overwritten by a direct write to this register + * | | |Every three bits of this register control the latency of each of the (up to) four ranks + * | | |R0DGSL controls the latency of rank 0, R1DGSL controls rank 1, and so on + * | | |Valid values are 0 to 7. + * |[11:9] |R3DGSL |Rank n DQS Gating System Latency + * | | |This is used to increase the number of clock cycles needed to expect valid DDR read data by up to seven extra clock cycles + * | | |This is used to compensate for board delays and other system delays + * | | |Power-up default is 000 (i.e + * | | |no extra clock cycles required) + * | | |The SL fields are initially set by the PUB during automatic DQS data training but these values can be overwritten by a direct write to this register + * | | |Every three bits of this register control the latency of each of the (up to) four ranks + * | | |R0DGSL controls the latency of rank 0, R1DGSL controls rank 1, and so on + * | | |Valid values are 0 to 7. + * |[13:12] |R0WLSL |Rank n Write Leveling System Latency + * | | |This is used to adjust the write latency after write leveling + * | | |Power-up default is 01 (i.e + * | | |no extra clock cycles required) + * | | |The SL fields are initially set by the PUB during automatic write leveling but these values can be overwritten by a direct write to this register + * | | |Every two bits of this register control the latency of each of the (up to) four ranks + * | | |R0WLSL controls the latency of rank 0, R1WLSL controls rank 1, and so on + * | | |Valid values: + * | | |00 = Write latency = WL - 1 + * | | |01 = Write latency = WL + * | | |10 = Write latency = WL + 1 + * | | |11 = Reserved + * |[15:14] |R1WLSL |Rank n Write Leveling System Latency + * | | |This is used to adjust the write latency after write leveling + * | | |Power-up default is 01 (i.e + * | | |no extra clock cycles required) + * | | |The SL fields are initially set by the PUB during automatic write leveling but these values can be overwritten by a direct write to this register + * | | |Every two bits of this register control the latency of each of the (up to) four ranks + * | | |R0WLSL controls the latency of rank 0, R1WLSL controls rank 1, and so on + * | | |Valid values: + * | | |00 = Write latency = WL - 1 + * | | |01 = Write latency = WL + * | | |10 = Write latency = WL + 1 + * | | |11 = Reserved + * |[17:16] |R2WLSL |Rank n Write Leveling System Latency + * | | |This is used to adjust the write latency after write leveling + * | | |Power-up default is 01 (i.e + * | | |no extra clock cycles required) + * | | |The SL fields are initially set by the PUB during automatic write leveling but these values can be overwritten by a direct write to this register + * | | |Every two bits of this register control the latency of each of the (up to) four ranks + * | | |R0WLSL controls the latency of rank 0, R1WLSL controls rank 1, and so on + * | | |Valid values: + * | | |00 = Write latency = WL - 1 + * | | |01 = Write latency = WL + * | | |10 = Write latency = WL + 1 + * | | |11 = Reserved + * |[19:18] |R3WLSL |Rank n Write Leveling System Latency + * | | |This is used to adjust the write latency after write leveling + * | | |Power-up default is 01 (i.e + * | | |no extra clock cycles required) + * | | |The SL fields are initially set by the PUB during automatic write leveling but these values can be overwritten by a direct write to this register + * | | |Every two bits of this register control the latency of each of the (up to) four ranks + * | | |R0WLSL controls the latency of rank 0, R1WLSL controls rank 1, and so on + * | | |Valid values: + * | | |00 = Write latency = WL - 1 + * | | |01 = Write latency = WL + * | | |10 = Write latency = WL + 1 + * | | |11 = Reserved + * @var DDRPHY_T::DX4GSR2 + * Offset: 0x2F4 DATX8 General Status Register 2 (DXnGSR2) + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[0] |RDERR |Read Bit Deskew Error + * | | |Indicates, if set, that the DATX8 has encountered an error during execution of the read bit deskew training. + * |[1] |RDWN |Read Bit Deskew Warning + * | | |Indicates, if set, that the DATX8 has encountered a warning during execution of the read bit deskew training. + * |[2] |WDERR |Write Bit Deskew Error + * | | |Indicates, if set, that the DATX8 has encountered an error during execution of the write bit deskew training. + * |[3] |WDWN |Write Bit Deskew Warning + * | | |Indicates, if set, that the DATX8 has encountered a warning during execution of the write bit deskew training. + * |[4] |REERR |Read Data Eye Training Error + * | | |Indicates, if set, that the DATX8 has encountered an error during execution of the read data eye training. + * |[5] |REWN |Read Data Eye Training Warning + * | | |Indicates, if set, that the DATX8 has encountered a warning during execution of the read data eye training. + * |[6] |WEERR |Write Data Eye Training Error + * | | |Indicates, if set, that the DATX8 has encountered an error during execution of the write data eye training. + * |[7] |WEWN |Write Data Eye Training Warning + * | | |Indicates, if set, that the DATX8 has encountered a warning during execution of the write data eye training. + * |[11:8] |ESTAT |Error Status + * | | |If an error occurred for this lane as indicated by RDERR, WDERR, REERR or WEERR the error status code can provide additional information regard when the error occurred during the algorithm execution. + * @var DDRPHY_T::DX5GCR + * Offset: 0x300 DATX8 General Configuration Register (DXnGCR) + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[0] |DXEN |Data Byte Enable + * | | |Enables, if set, the data byte + * | | |Setting this bit to '0' disables the byte, i.e + * | | |the byte is not used in PHY initialization or training and is ignored during SDRAM read/write operations. + * |[1] |DQSODT |DQS On-Die Termination + * | | |Enables, when set, the on-die termination on the I/O for DQS/DQS# pin of the byte + * | | |This bit is ORed with the common DATX8 ODT configuration bit (see "DATX8 Common Configuration Register (DXCCR)"). + * | | |Note: This bit is only valid when DXnGCR0[9] is '0'. + * |[2] |DQODT |Data On-Die Termination + * | | |Enables, when set, the on-die termination on the I/O for DQ and DM pins of the byte + * | | |This bit is ORed with the common DATX8 ODT configuration bit (see "DATX8 Common Configuration Register (DXCCR)"). + * | | |Note: This bit is only valid when DXnGCR0[10] is '0'. + * |[3] |DXIOM |Data I/O Mode + * | | |Selects SSTL mode (when set to 0) or CMOS mode (when set to 1) of the I/O for DQ, DM, and DQS/DQS# pins of the byte + * | | |This bit is ORed with the IOM configuration bit of the individual DATX8(see "DATX8 Common Configuration Register (DXCCR)"). + * |[4] |DXPDD |Data Power Down Driver + * | | |Powers down, when set, the output driver on I/O for DQ, DM, and DQS/DQS# pins of the byte + * | | |This bit is ORed with the common PDD configuration bit (see "DATX8 Common Configuration Register (DXCCR)"). + * | | |Note: Asserting PDD puts the IO driver cell into a lower power, lower speed mode of operation + * | | |However, it will still drive if its OE is asserted + * | | |ODT will be disabled (if used) + * | | |Asserting PDD does not prevent the IO from driving. + * |[5] |DXPDR |Data Power Down Receiver + * | | |Powers down, when set, the input receiver on I/O for DQ, DM, and DQS/DQS# pins of the byte + * | | |This bit is ORed with the common PDR configuration bit (see "DATX8 Common Configuration Register (DXCCR)"). + * |[6] |DQSRPD |DQSR Power Down + * | | |Powers down, if set, the PDQSR cell + * | | |This bit is ORed with the common PDR configuration bit (see "DATX8 Common Configuration Register (DXCCR)") + * |[8:7] |DSEN |Write DQS Enable + * | | |Controls whether the write DQS going to the SDRAM is enabled (toggling) or disabled (static value) and whether the DQS is inverted + * | | |DQS# is always the inversion of DQS + * | | |These values are valid only when DQS/DQS# output enable is on, otherwise the DQS/DQS# is tristated + * | | |Valid settings are: + * | | |00 = Reserved + * | | |01 = DQS toggling with normal polarity (This should be the default setting) + * | | |10 = Reserved + * | | |11 = Reserved + * |[9] |DQSRTT |DQS Dynamic RTT Control + * | | |If set, the on die termination (ODT) control of the DQS/DQS# SSTL I/O is dynamically generated to enable the ODT during read operation and disabled otherwise + * | | |By setting this bit to '0' the dynamic ODT feature is disabled + * | | |To control ODT statically this bit must be set to '0' and DXnGCR0[1] (DQSODT) is used to enable ODT (when set to '1') or disable ODT(when set to '0'). + * |[10] |DQRTT |DQ Dynamic RTT Control + * | | |If set, the on die termination (ODT) control of the DQ/DM SSTL I/O is dynamically generated to enable the ODT during read operation and disabled otherwise + * | | |By setting this bit to '0' the dynamic ODT feature is disabled + * | | |To control ODT statically this bit must be set to '0' and DXnGCR0[2] (DQODT) is used to enable ODT (when set to '1') or disable ODT(when set to '0'). + * |[12:11] |RTTOH |RTT Output Hold + * | | |Indicates the number of clock cycles (from 0 to 3) after the read data postamble for which ODT control should remain set to DQSODT for DQS or DQODT for DQ/DM before disabling it (setting it to '0') when using dynamic ODT control + * | | |ODT is disabled almost RTTOH clock cycles after the read postamble. + * |[13] |RTTOAL |RTT On Additive Latency + * | | |Indicates when the ODT control of DQ/DQS SSTL I/Os is set to the value in DQODT/DQSODT during read cycles + * | | |Valid values are: + * | | |0 = ODT control is set to DQSODT/DQODT almost two cycles before read data preamble + * | | |1 = ODT control is set to DQSODT/DQODT almost one cycle before read data preamble + * |[15:14] |DXOEO |Data Byte Output Enable Override + * | | |Specifies whether the output I/O output enable for the byte lane should be set to a fixed value + * | | |Valid values are: + * | | |00 = No override. Output enable is controlled by DFI transactions + * | | |01 = Output enable is asserted (I/O is forced to output mode). + * | | |10 = Output enable is de-asserted (I/O is forced to input mode) + * | | |11 = Reserved + * |[16] |PLLRST |PLL Rest + * | | |Resets the byte PLL by driving the PLL reset pin + * | | |This bit is not self- clearing and a '0' must be written to de-assert the reset + * | | |This bit is ORed with the global PLLRST configuration bit. + * |[17] |PLLPD |PLL Power Down + * | | |Puts the byte PLL in Power-down mode by driving the PLL power down pin + * | | |This bit is not self-clearing and a '0' must be written to de-assert the power-down + * | | |This bit is ORed with the global PLLPD configuration bit. + * |[18] |GSHIFT |Gear Shift + * | | |Enables, if set, rapid locking mode on the byte PLL + * | | |This bit is ORed with the global GSHIFT configuration bit. + * |[19] |PLLBYP |PLL Bypass + * | | |Puts the byte PLL in bypass mode by driving the PLL bypass pin + * | | |This bit is not self-clearing and a '0' must be written to de-assert the bypass + * | | |This bit is ORed with the global BYP configuration bit. + * |[29:26] |WLRKEN |Write Level Rank Enable + * | | |Specifies the ranks that should be write leveled for this byte + * | | |Write leveling responses from ranks that are not enabled for write leveling for a particular byte are ignored and write leveling is flagged as done for these ranks + * | | |WLRKEN[0] enables rank 0, [1] enables rank 1, [2] enables rank 2, and [3] enables rank 3. + * |[30] |MDLEN |Master Delay Line Enable + * | | |Enables, if set, the DATX8 master delay line calibration to perform subsequent period measurements following the initial period measurements that are performed after reset or when calibration is manually triggered + * | | |These additional measurements are accumulated and filtered as long as this bit remains high + * | | |This bit is ANDed with the common DATX8 MDL enable bit. + * |[31] |CALBYP |Calibration Bypass + * | | |Prevents, if set, period measurement calibration from automatically triggering after PHY initialization. + * @var DDRPHY_T::DX5GSR0 + * Offset: 0x304 DATX8 General Status Registers 0 (DXnGSR0) + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[0] |WDQCAL |Write DQ Calibration + * | | |Indicates, if set, that the DATX8 has finished doing period measurement calibration for the write DQ LCDL. + * |[1] |RDQSCAL |Read DQS Calibration + * | | |Indicates, if set, that the DATX8 has finished doing period measurement calibration for the read DQS LCDL. + * |[2] |RDQSNCAL |Read DQS# Calibration + * | | |Indicates, if set, that the DATX8 has finished doing period measurement calibration for the read DQS# LCDL. + * |[3] |GDQSCAL |Read DQS gating Calibration + * | | |Indicates, if set, that the DATX8 has finished doing period measurement calibration for the read DQS gating LCDL. + * |[4] |WLCAL |Write Leveling Calibration + * | | |Indicates, if set, that the DATX8 has finished doing period measurement calibration for the write leveling slave delay line. + * |[5] |WLDONE |Write Leveling Done + * | | |Indicates, if set, that the DATX8 has completed write leveling. + * |[6] |WLERR |Write Leveling Error + * | | |Indicates, if set, that there is a write leveling error in the DATX8. + * |[14:7] |WLPRD |Write Leveling Period + * | | |Returns the DDR clock period measured by the write leveling LCDL during calibration + * | | |The measured period is used to generate the control of the write leveling pipeline which is a function of the write-leveling delay and the clock period + * | | |This value is PVT compensated. + * |[15] |DPLOCK |DATX8 PLL Lock + * | | |Indicates, if set, that the DATX8 PLL has locked. This is a direct status of the DATX8 PLL lock pin. + * |[23:16] |GDQSPRD |Read DQS gating Period + * | | |Returns the DDR clock period measured by the read DQS gating LCDL during calibration + * | | |This value is PVT compensated. + * |[27:24] |QSGERR |DQS Gate Training Error + * | | |Indicates, if set, that there is an error in DQS gate training. One bit for each of the up to 4 ranks. + * |[28] |WLDQ |Write Leveling DQ Status + * | | |Captures the write leveling DQ status from the DRAM during software write leveling. + * @var DDRPHY_T::DX5GSR1 + * Offset: 0x308 DATX8 General Status Registers 1 (DXnGSR1) + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[0] |DLTDONE |Delay Line Test Done + * | | |Indicates, if set, that the PHY control block has finished doing period measurement of the DATX8 delay line digital test output. + * |[24:1] |DLTCODE |Delay Line Test Code + * | | |Returns the code measured by the PHY control block that corresponds to the period of the DATX8 delay line digital test output. + * @var DDRPHY_T::DX5BDLR0 + * Offset: 0x30C DATX8 Bit Delay Line Register 0 (DXnBDLR0) + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[5:0] |DQ0WBD |DQ0 Write Bit Delay + * | | |Delay select for the BDL on DQ0 write path. + * |[11:6] |DQ1WBD |DQ1 Write Bit Delay + * | | |Delay select for the BDL on DQ1 write path. + * |[17:12] |DQ2WBD |DQ2 Write Bit Delay + * | | |Delay select for the BDL on DQ2 write path. + * |[23:18] |DQ3WBD |DQ3 Write Bit Delay + * | | |Delay select for the BDL on DQ3 write path + * |[29:24] |DQ4WBD |DQ4 Write Bit Delay + * | | |Delay select for the BDL on DQ4 write path. + * @var DDRPHY_T::DX5BDLR1 + * Offset: 0x310 DATX8 Bit Delay Line Register 1 (DXnBDLR1) + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[5:0] |DQ5WBD |DQ5 Write Bit Delay + * | | |Delay select for the BDL on DQ5 write path. + * |[11:6] |DQ6WBD |DQ6 Write Bit Delay + * | | |Delay select for the BDL on DQ6 write path. + * |[17:12] |DQ7WBD |DQ7 Write Bit Delay + * | | |Delay select for the BDL on DQ7 write path. + * |[23:18] |DMWBD |DM Write Bit Delay + * | | |Delay select for the BDL on DM write path. + * |[29:24] |DSWBD |DQS Write Bit Delay + * | | |Delay select for the BDL on DQS write path + * @var DDRPHY_T::DX5BDLR2 + * Offset: 0x314 DATX8 Bit Delay Line Register 2 (DXnBDLR2) + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[5:0] |DSOEBD |DQS Output Enable Bit Delay + * | | |Delay select for the BDL on DQS output enable path + * |[11:6] |DQOEBD |DQ Output Enable Bit Delay + * | | |Delay select for the BDL on DQ/DM output enable path. + * |[17:12] |DSRBD |DQS Read Bit Delay + * | | |Delay select for the BDL on DQS read path + * |[23:18] |DSNRBD |DQSN Read Bit Delay + * | | |Delay select for the BDL on DQSN read path + * @var DDRPHY_T::DX5BDLR3 + * Offset: 0x318 DATX8 Bit Delay Line Register 3 (DXnBDLR3) + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[5:0] |DQ0RBD |DQ0 Read Bit Delay + * | | |Delay select for the BDL on DQ0 read path. + * |[11:6] |DQ1RBD |DQ1 Read Bit Delay + * | | |Delay select for the BDL on DQ1 read path. + * |[17:12] |DQ2RBD |DQ2 Read Bit Delay + * | | |Delay select for the BDL on DQ2 read path. + * |[23:18] |DQ3RBD |DQ3 Read Bit Delay + * | | |Delay select for the BDL on DQ3 read path + * |[29:24] |DQ4RBD |DQ4 Read Bit Delay + * | | |Delay select for the BDL on DQ4 read path. + * @var DDRPHY_T::DX5BDLR4 + * Offset: 0x31C DATX8 Bit Delay Line Register 4 (DXnBDLR4) + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[5:0] |DQ5RBD |DQ5 Read Bit Delay + * | | |Delay select for the BDL on DQ5 read path. + * |[11:6] |DQ6RBD |DQ6 Read Bit Delay + * | | |Delay select for the BDL on DQ6 read path. + * |[17:12] |DQ7RBD |DQ7 Read Bit Delay + * | | |Delay select for the BDL on DQ7 read path. + * |[23:18] |DMRBD |DM Read Bit Delay + * | | |Delay select for the BDL on DM read path. + * @var DDRPHY_T::DX5LCDLR0 + * Offset: 0x320 DATX8 Bit Delay Line Register 0 (DXnBDLR0) + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[7:0] |R0WLD |Rank 0 Write Leveling Delay + * | | |Rank 0 delay select for the write leveling (WL) LCDL + * |[15:8] |R1WLD |Rank 1 Write Leveling Delay + * | | |Rank 1 delay select for the write leveling (WL) LCDL + * |[23:16] |R2WLD |Rank 2 Write Leveling Delay + * | | |Rank 2 delay select for the write leveling (WL) LCDL + * |[31:24] |R3WLD |Rank 3 Write Leveling Delay + * | | |Rank 3 delay select for the write leveling (WL) LCDL + * @var DDRPHY_T::DX5LCDLR1 + * Offset: 0x324 DATX8 Bit Delay Line Register 1 (DXnBDLR1) + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[7:0] |WDQD |Write Data Delay + * | | |Delay select for the write data (WDQ) LCDL + * |[15:8] |RDQSD |Read DQS Delay + * | | |Delay select for the read DQS (RDQS) LCDL + * |[23:16] |RDQSND |Read DQSN Delay + * | | |Delay select for the read DQSN (RDQS) LCDL + * @var DDRPHY_T::DX5LCDLR2 + * Offset: 0x328 DATX8 Bit Delay Line Register 2 (DXnBDLR2) + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[7:0] |R0DQSGD |Rank 0 Read DQS Gating Delay + * | | |Rank 0 delay select for the read DQS gating (DQSG) LCDL + * |[15:8] |R1DQSGD |Rank 1 Read DQS Gating Delay + * | | |Rank 1 delay select for the read DQS gating (DQSG) LCDL + * |[23:16] |R2DQSGD |Rank 2 Read DQS Gating Delay + * | | |Rank 2 delay select for the read DQS gating (DQSG) LCDL + * |[31:24] |R3DQSGD |Rank 3 Read DQS Gating Delay + * | | |Rank 3 delay select for the read DQS gating (DQSG) LCDL + * @var DDRPHY_T::DX5MDLR + * Offset: 0x32C DATX8 Master Delay Line Register (DXnMDLR) + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[7:0] |IPRD |Initial Period + * | | |Initial period measured by the master delay line calibration for VT drift compensation + * | | |This value is used as the denominator when calculating the ratios of updates during VT compensation. + * |[15:8] |TPRD |Target Period + * | | |Target period measured by the master delay line calibration for VT drift compensation + * | | |This is the current measured value of the period and is continuously updated if the MDL is enabled to do so. + * |[23:16] |MDLD |MDL Delay + * | | |Delay select for the LCDL for the Master Delay Line. + * @var DDRPHY_T::DX5GTR + * Offset: 0x330 DATX8 General Timing Register (DXnGTR) + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[2:0] |R0DGSL |Rank n DQS Gating System Latency + * | | |This is used to increase the number of clock cycles needed to expect valid DDR read data by up to seven extra clock cycles + * | | |This is used to compensate for board delays and other system delays + * | | |Power-up default is 000 (i.e + * | | |no extra clock cycles required) + * | | |The SL fields are initially set by the PUB during automatic DQS data training but these values can be overwritten by a direct write to this register + * | | |Every three bits of this register control the latency of each of the (up to) four ranks + * | | |R0DGSL controls the latency of rank 0, R1DGSL controls rank 1, and so on + * | | |Valid values are 0 to 7. + * |[5:3] |R1DGSL |Rank n DQS Gating System Latency + * | | |This is used to increase the number of clock cycles needed to expect valid DDR read data by up to seven extra clock cycles + * | | |This is used to compensate for board delays and other system delays + * | | |Power-up default is 000 (i.e + * | | |no extra clock cycles required) + * | | |The SL fields are initially set by the PUB during automatic DQS data training but these values can be overwritten by a direct write to this register + * | | |Every three bits of this register control the latency of each of the (up to) four ranks + * | | |R0DGSL controls the latency of rank 0, R1DGSL controls rank 1, and so on + * | | |Valid values are 0 to 7. + * |[8:6] |R2DGSL |Rank n DQS Gating System Latency + * | | |This is used to increase the number of clock cycles needed to expect valid DDR read data by up to seven extra clock cycles + * | | |This is used to compensate for board delays and other system delays + * | | |Power-up default is 000 (i.e + * | | |no extra clock cycles required) + * | | |The SL fields are initially set by the PUB during automatic DQS data training but these values can be overwritten by a direct write to this register + * | | |Every three bits of this register control the latency of each of the (up to) four ranks + * | | |R0DGSL controls the latency of rank 0, R1DGSL controls rank 1, and so on + * | | |Valid values are 0 to 7. + * |[11:9] |R3DGSL |Rank n DQS Gating System Latency + * | | |This is used to increase the number of clock cycles needed to expect valid DDR read data by up to seven extra clock cycles + * | | |This is used to compensate for board delays and other system delays + * | | |Power-up default is 000 (i.e + * | | |no extra clock cycles required) + * | | |The SL fields are initially set by the PUB during automatic DQS data training but these values can be overwritten by a direct write to this register + * | | |Every three bits of this register control the latency of each of the (up to) four ranks + * | | |R0DGSL controls the latency of rank 0, R1DGSL controls rank 1, and so on + * | | |Valid values are 0 to 7. + * |[13:12] |R0WLSL |Rank n Write Leveling System Latency + * | | |This is used to adjust the write latency after write leveling + * | | |Power-up default is 01 (i.e + * | | |no extra clock cycles required) + * | | |The SL fields are initially set by the PUB during automatic write leveling but these values can be overwritten by a direct write to this register + * | | |Every two bits of this register control the latency of each of the (up to) four ranks + * | | |R0WLSL controls the latency of rank 0, R1WLSL controls rank 1, and so on + * | | |Valid values: + * | | |00 = Write latency = WL - 1 + * | | |01 = Write latency = WL + * | | |10 = Write latency = WL + 1 + * | | |11 = Reserved + * |[15:14] |R1WLSL |Rank n Write Leveling System Latency + * | | |This is used to adjust the write latency after write leveling + * | | |Power-up default is 01 (i.e + * | | |no extra clock cycles required) + * | | |The SL fields are initially set by the PUB during automatic write leveling but these values can be overwritten by a direct write to this register + * | | |Every two bits of this register control the latency of each of the (up to) four ranks + * | | |R0WLSL controls the latency of rank 0, R1WLSL controls rank 1, and so on + * | | |Valid values: + * | | |00 = Write latency = WL - 1 + * | | |01 = Write latency = WL + * | | |10 = Write latency = WL + 1 + * | | |11 = Reserved + * |[17:16] |R2WLSL |Rank n Write Leveling System Latency + * | | |This is used to adjust the write latency after write leveling + * | | |Power-up default is 01 (i.e + * | | |no extra clock cycles required) + * | | |The SL fields are initially set by the PUB during automatic write leveling but these values can be overwritten by a direct write to this register + * | | |Every two bits of this register control the latency of each of the (up to) four ranks + * | | |R0WLSL controls the latency of rank 0, R1WLSL controls rank 1, and so on + * | | |Valid values: + * | | |00 = Write latency = WL - 1 + * | | |01 = Write latency = WL + * | | |10 = Write latency = WL + 1 + * | | |11 = Reserved + * |[19:18] |R3WLSL |Rank n Write Leveling System Latency + * | | |This is used to adjust the write latency after write leveling + * | | |Power-up default is 01 (i.e + * | | |no extra clock cycles required) + * | | |The SL fields are initially set by the PUB during automatic write leveling but these values can be overwritten by a direct write to this register + * | | |Every two bits of this register control the latency of each of the (up to) four ranks + * | | |R0WLSL controls the latency of rank 0, R1WLSL controls rank 1, and so on + * | | |Valid values: + * | | |00 = Write latency = WL - 1 + * | | |01 = Write latency = WL + * | | |10 = Write latency = WL + 1 + * | | |11 = Reserved + * @var DDRPHY_T::DX5GSR2 + * Offset: 0x334 DATX8 General Status Register 2 (DXnGSR2) + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[0] |RDERR |Read Bit Deskew Error + * | | |Indicates, if set, that the DATX8 has encountered an error during execution of the read bit deskew training. + * |[1] |RDWN |Read Bit Deskew Warning + * | | |Indicates, if set, that the DATX8 has encountered a warning during execution of the read bit deskew training. + * |[2] |WDERR |Write Bit Deskew Error + * | | |Indicates, if set, that the DATX8 has encountered an error during execution of the write bit deskew training. + * |[3] |WDWN |Write Bit Deskew Warning + * | | |Indicates, if set, that the DATX8 has encountered a warning during execution of the write bit deskew training. + * |[4] |REERR |Read Data Eye Training Error + * | | |Indicates, if set, that the DATX8 has encountered an error during execution of the read data eye training. + * |[5] |REWN |Read Data Eye Training Warning + * | | |Indicates, if set, that the DATX8 has encountered a warning during execution of the read data eye training. + * |[6] |WEERR |Write Data Eye Training Error + * | | |Indicates, if set, that the DATX8 has encountered an error during execution of the write data eye training. + * |[7] |WEWN |Write Data Eye Training Warning + * | | |Indicates, if set, that the DATX8 has encountered a warning during execution of the write data eye training. + * |[11:8] |ESTAT |Error Status + * | | |If an error occurred for this lane as indicated by RDERR, WDERR, REERR or WEERR the error status code can provide additional information regard when the error occurred during the algorithm execution. + * @var DDRPHY_T::DX6GCR + * Offset: 0x340 DATX8 General Configuration Register (DXnGCR) + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[0] |DXEN |Data Byte Enable + * | | |Enables, if set, the data byte + * | | |Setting this bit to '0' disables the byte, i.e + * | | |the byte is not used in PHY initialization or training and is ignored during SDRAM read/write operations. + * |[1] |DQSODT |DQS On-Die Termination + * | | |Enables, when set, the on-die termination on the I/O for DQS/DQS# pin of the byte + * | | |This bit is ORed with the common DATX8 ODT configuration bit (see "DATX8 Common Configuration Register (DXCCR)"). + * | | |Note: This bit is only valid when DXnGCR0[9] is '0'. + * |[2] |DQODT |Data On-Die Termination + * | | |Enables, when set, the on-die termination on the I/O for DQ and DM pins of the byte + * | | |This bit is ORed with the common DATX8 ODT configuration bit (see "DATX8 Common Configuration Register (DXCCR)"). + * | | |Note: This bit is only valid when DXnGCR0[10] is '0'. + * |[3] |DXIOM |Data I/O Mode + * | | |Selects SSTL mode (when set to 0) or CMOS mode (when set to 1) of the I/O for DQ, DM, and DQS/DQS# pins of the byte + * | | |This bit is ORed with the IOM configuration bit of the individual DATX8(see "DATX8 Common Configuration Register (DXCCR)"). + * |[4] |DXPDD |Data Power Down Driver + * | | |Powers down, when set, the output driver on I/O for DQ, DM, and DQS/DQS# pins of the byte + * | | |This bit is ORed with the common PDD configuration bit (see "DATX8 Common Configuration Register (DXCCR)"). + * | | |Note: Asserting PDD puts the IO driver cell into a lower power, lower speed mode of operation + * | | |However, it will still drive if its OE is asserted + * | | |ODT will be disabled (if used) + * | | |Asserting PDD does not prevent the IO from driving. + * |[5] |DXPDR |Data Power Down Receiver + * | | |Powers down, when set, the input receiver on I/O for DQ, DM, and DQS/DQS# pins of the byte + * | | |This bit is ORed with the common PDR configuration bit (see "DATX8 Common Configuration Register (DXCCR)"). + * |[6] |DQSRPD |DQSR Power Down + * | | |Powers down, if set, the PDQSR cell + * | | |This bit is ORed with the common PDR configuration bit (see "DATX8 Common Configuration Register (DXCCR)") + * |[8:7] |DSEN |Write DQS Enable + * | | |Controls whether the write DQS going to the SDRAM is enabled (toggling) or disabled (static value) and whether the DQS is inverted + * | | |DQS# is always the inversion of DQS + * | | |These values are valid only when DQS/DQS# output enable is on, otherwise the DQS/DQS# is tristated + * | | |Valid settings are: + * | | |00 = Reserved + * | | |01 = DQS toggling with normal polarity (This should be the default setting) + * | | |10 = Reserved + * | | |11 = Reserved + * |[9] |DQSRTT |DQS Dynamic RTT Control + * | | |If set, the on die termination (ODT) control of the DQS/DQS# SSTL I/O is dynamically generated to enable the ODT during read operation and disabled otherwise + * | | |By setting this bit to '0' the dynamic ODT feature is disabled + * | | |To control ODT statically this bit must be set to '0' and DXnGCR0[1] (DQSODT) is used to enable ODT (when set to '1') or disable ODT(when set to '0'). + * |[10] |DQRTT |DQ Dynamic RTT Control + * | | |If set, the on die termination (ODT) control of the DQ/DM SSTL I/O is dynamically generated to enable the ODT during read operation and disabled otherwise + * | | |By setting this bit to '0' the dynamic ODT feature is disabled + * | | |To control ODT statically this bit must be set to '0' and DXnGCR0[2] (DQODT) is used to enable ODT (when set to '1') or disable ODT(when set to '0'). + * |[12:11] |RTTOH |RTT Output Hold + * | | |Indicates the number of clock cycles (from 0 to 3) after the read data postamble for which ODT control should remain set to DQSODT for DQS or DQODT for DQ/DM before disabling it (setting it to '0') when using dynamic ODT control + * | | |ODT is disabled almost RTTOH clock cycles after the read postamble. + * |[13] |RTTOAL |RTT On Additive Latency + * | | |Indicates when the ODT control of DQ/DQS SSTL I/Os is set to the value in DQODT/DQSODT during read cycles + * | | |Valid values are: + * | | |0 = ODT control is set to DQSODT/DQODT almost two cycles before read data preamble + * | | |1 = ODT control is set to DQSODT/DQODT almost one cycle before read data preamble + * |[15:14] |DXOEO |Data Byte Output Enable Override + * | | |Specifies whether the output I/O output enable for the byte lane should be set to a fixed value + * | | |Valid values are: + * | | |00 = No override. Output enable is controlled by DFI transactions + * | | |01 = Output enable is asserted (I/O is forced to output mode). + * | | |10 = Output enable is de-asserted (I/O is forced to input mode) + * | | |11 = Reserved + * |[16] |PLLRST |PLL Rest + * | | |Resets the byte PLL by driving the PLL reset pin + * | | |This bit is not self- clearing and a '0' must be written to de-assert the reset + * | | |This bit is ORed with the global PLLRST configuration bit. + * |[17] |PLLPD |PLL Power Down + * | | |Puts the byte PLL in Power-down mode by driving the PLL power down pin + * | | |This bit is not self-clearing and a '0' must be written to de-assert the power-down + * | | |This bit is ORed with the global PLLPD configuration bit. + * |[18] |GSHIFT |Gear Shift + * | | |Enables, if set, rapid locking mode on the byte PLL + * | | |This bit is ORed with the global GSHIFT configuration bit. + * |[19] |PLLBYP |PLL Bypass + * | | |Puts the byte PLL in bypass mode by driving the PLL bypass pin + * | | |This bit is not self-clearing and a '0' must be written to de-assert the bypass + * | | |This bit is ORed with the global BYP configuration bit. + * |[29:26] |WLRKEN |Write Level Rank Enable + * | | |Specifies the ranks that should be write leveled for this byte + * | | |Write leveling responses from ranks that are not enabled for write leveling for a particular byte are ignored and write leveling is flagged as done for these ranks + * | | |WLRKEN[0] enables rank 0, [1] enables rank 1, [2] enables rank 2, and [3] enables rank 3. + * |[30] |MDLEN |Master Delay Line Enable + * | | |Enables, if set, the DATX8 master delay line calibration to perform subsequent period measurements following the initial period measurements that are performed after reset or when calibration is manually triggered + * | | |These additional measurements are accumulated and filtered as long as this bit remains high + * | | |This bit is ANDed with the common DATX8 MDL enable bit. + * |[31] |CALBYP |Calibration Bypass + * | | |Prevents, if set, period measurement calibration from automatically triggering after PHY initialization. + * @var DDRPHY_T::DX6GSR0 + * Offset: 0x344 DATX8 General Status Registers 0 (DXnGSR0) + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[0] |WDQCAL |Write DQ Calibration + * | | |Indicates, if set, that the DATX8 has finished doing period measurement calibration for the write DQ LCDL. + * |[1] |RDQSCAL |Read DQS Calibration + * | | |Indicates, if set, that the DATX8 has finished doing period measurement calibration for the read DQS LCDL. + * |[2] |RDQSNCAL |Read DQS# Calibration + * | | |Indicates, if set, that the DATX8 has finished doing period measurement calibration for the read DQS# LCDL. + * |[3] |GDQSCAL |Read DQS gating Calibration + * | | |Indicates, if set, that the DATX8 has finished doing period measurement calibration for the read DQS gating LCDL. + * |[4] |WLCAL |Write Leveling Calibration + * | | |Indicates, if set, that the DATX8 has finished doing period measurement calibration for the write leveling slave delay line. + * |[5] |WLDONE |Write Leveling Done + * | | |Indicates, if set, that the DATX8 has completed write leveling. + * |[6] |WLERR |Write Leveling Error + * | | |Indicates, if set, that there is a write leveling error in the DATX8. + * |[14:7] |WLPRD |Write Leveling Period + * | | |Returns the DDR clock period measured by the write leveling LCDL during calibration + * | | |The measured period is used to generate the control of the write leveling pipeline which is a function of the write-leveling delay and the clock period + * | | |This value is PVT compensated. + * |[15] |DPLOCK |DATX8 PLL Lock + * | | |Indicates, if set, that the DATX8 PLL has locked. This is a direct status of the DATX8 PLL lock pin. + * |[23:16] |GDQSPRD |Read DQS gating Period + * | | |Returns the DDR clock period measured by the read DQS gating LCDL during calibration + * | | |This value is PVT compensated. + * |[27:24] |QSGERR |DQS Gate Training Error + * | | |Indicates, if set, that there is an error in DQS gate training. One bit for each of the up to 4 ranks. + * |[28] |WLDQ |Write Leveling DQ Status + * | | |Captures the write leveling DQ status from the DRAM during software write leveling. + * @var DDRPHY_T::DX6GSR1 + * Offset: 0x348 DATX8 General Status Registers 1 (DXnGSR1) + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[0] |DLTDONE |Delay Line Test Done + * | | |Indicates, if set, that the PHY control block has finished doing period measurement of the DATX8 delay line digital test output. + * |[24:1] |DLTCODE |Delay Line Test Code + * | | |Returns the code measured by the PHY control block that corresponds to the period of the DATX8 delay line digital test output. + * @var DDRPHY_T::DX6BDLR0 + * Offset: 0x34C DATX8 Bit Delay Line Register 0 (DXnBDLR0) + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[5:0] |DQ0WBD |DQ0 Write Bit Delay + * | | |Delay select for the BDL on DQ0 write path. + * |[11:6] |DQ1WBD |DQ1 Write Bit Delay + * | | |Delay select for the BDL on DQ1 write path. + * |[17:12] |DQ2WBD |DQ2 Write Bit Delay + * | | |Delay select for the BDL on DQ2 write path. + * |[23:18] |DQ3WBD |DQ3 Write Bit Delay + * | | |Delay select for the BDL on DQ3 write path + * |[29:24] |DQ4WBD |DQ4 Write Bit Delay + * | | |Delay select for the BDL on DQ4 write path. + * @var DDRPHY_T::DX6BDLR1 + * Offset: 0x350 DATX8 Bit Delay Line Register 1 (DXnBDLR1) + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[5:0] |DQ5WBD |DQ5 Write Bit Delay + * | | |Delay select for the BDL on DQ5 write path. + * |[11:6] |DQ6WBD |DQ6 Write Bit Delay + * | | |Delay select for the BDL on DQ6 write path. + * |[17:12] |DQ7WBD |DQ7 Write Bit Delay + * | | |Delay select for the BDL on DQ7 write path. + * |[23:18] |DMWBD |DM Write Bit Delay + * | | |Delay select for the BDL on DM write path. + * |[29:24] |DSWBD |DQS Write Bit Delay + * | | |Delay select for the BDL on DQS write path + * @var DDRPHY_T::DX6BDLR2 + * Offset: 0x354 DATX8 Bit Delay Line Register 2 (DXnBDLR2) + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[5:0] |DSOEBD |DQS Output Enable Bit Delay + * | | |Delay select for the BDL on DQS output enable path + * |[11:6] |DQOEBD |DQ Output Enable Bit Delay + * | | |Delay select for the BDL on DQ/DM output enable path. + * |[17:12] |DSRBD |DQS Read Bit Delay + * | | |Delay select for the BDL on DQS read path + * |[23:18] |DSNRBD |DQSN Read Bit Delay + * | | |Delay select for the BDL on DQSN read path + * @var DDRPHY_T::DX6BDLR3 + * Offset: 0x358 DATX8 Bit Delay Line Register 3 (DXnBDLR3) + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[5:0] |DQ0RBD |DQ0 Read Bit Delay + * | | |Delay select for the BDL on DQ0 read path. + * |[11:6] |DQ1RBD |DQ1 Read Bit Delay + * | | |Delay select for the BDL on DQ1 read path. + * |[17:12] |DQ2RBD |DQ2 Read Bit Delay + * | | |Delay select for the BDL on DQ2 read path. + * |[23:18] |DQ3RBD |DQ3 Read Bit Delay + * | | |Delay select for the BDL on DQ3 read path + * |[29:24] |DQ4RBD |DQ4 Read Bit Delay + * | | |Delay select for the BDL on DQ4 read path. + * @var DDRPHY_T::DX6BDLR4 + * Offset: 0x35C DATX8 Bit Delay Line Register 4 (DXnBDLR4) + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[5:0] |DQ5RBD |DQ5 Read Bit Delay + * | | |Delay select for the BDL on DQ5 read path. + * |[11:6] |DQ6RBD |DQ6 Read Bit Delay + * | | |Delay select for the BDL on DQ6 read path. + * |[17:12] |DQ7RBD |DQ7 Read Bit Delay + * | | |Delay select for the BDL on DQ7 read path. + * |[23:18] |DMRBD |DM Read Bit Delay + * | | |Delay select for the BDL on DM read path. + * @var DDRPHY_T::DX6LCDLR0 + * Offset: 0x360 DATX8 Bit Delay Line Register 0 (DXnBDLR0) + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[7:0] |R0WLD |Rank 0 Write Leveling Delay + * | | |Rank 0 delay select for the write leveling (WL) LCDL + * |[15:8] |R1WLD |Rank 1 Write Leveling Delay + * | | |Rank 1 delay select for the write leveling (WL) LCDL + * |[23:16] |R2WLD |Rank 2 Write Leveling Delay + * | | |Rank 2 delay select for the write leveling (WL) LCDL + * |[31:24] |R3WLD |Rank 3 Write Leveling Delay + * | | |Rank 3 delay select for the write leveling (WL) LCDL + * @var DDRPHY_T::DX6LCDLR1 + * Offset: 0x364 DATX8 Bit Delay Line Register 1 (DXnBDLR1) + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * @var DDRPHY_T::DX6LCDLR2 + * Offset: 0x368 DATX8 Bit Delay Line Register 2 (DXnBDLR2) + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[7:0] |R0DQSGD |Rank 0 Read DQS Gating Delay + * | | |Rank 0 delay select for the read DQS gating (DQSG) LCDL + * |[15:8] |R1DQSGD |Rank 1 Read DQS Gating Delay + * | | |Rank 1 delay select for the read DQS gating (DQSG) LCDL + * |[23:16] |R2DQSGD |Rank 2 Read DQS Gating Delay + * | | |Rank 2 delay select for the read DQS gating (DQSG) LCDL + * |[31:24] |R3DQSGD |Rank 3 Read DQS Gating Delay + * | | |Rank 3 delay select for the read DQS gating (DQSG) LCDL + * @var DDRPHY_T::DX6MDLR + * Offset: 0x36C DATX8 Master Delay Line Register (DXnMDLR) + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[7:0] |IPRD |Initial Period + * | | |Initial period measured by the master delay line calibration for VT drift compensation + * | | |This value is used as the denominator when calculating the ratios of updates during VT compensation. + * |[15:8] |TPRD |Target Period + * | | |Target period measured by the master delay line calibration for VT drift compensation + * | | |This is the current measured value of the period and is continuously updated if the MDL is enabled to do so. + * |[23:16] |MDLD |MDL Delay + * | | |Delay select for the LCDL for the Master Delay Line. + * @var DDRPHY_T::DX6GTR + * Offset: 0x370 DATX8 General Timing Register (DXnGTR) + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[2:0] |R0DGSL |Rank n DQS Gating System Latency + * | | |This is used to increase the number of clock cycles needed to expect valid DDR read data by up to seven extra clock cycles + * | | |This is used to compensate for board delays and other system delays + * | | |Power-up default is 000 (i.e + * | | |no extra clock cycles required) + * | | |The SL fields are initially set by the PUB during automatic DQS data training but these values can be overwritten by a direct write to this register + * | | |Every three bits of this register control the latency of each of the (up to) four ranks + * | | |R0DGSL controls the latency of rank 0, R1DGSL controls rank 1, and so on + * | | |Valid values are 0 to 7. + * |[5:3] |R1DGSL |Rank n DQS Gating System Latency + * | | |This is used to increase the number of clock cycles needed to expect valid DDR read data by up to seven extra clock cycles + * | | |This is used to compensate for board delays and other system delays + * | | |Power-up default is 000 (i.e + * | | |no extra clock cycles required) + * | | |The SL fields are initially set by the PUB during automatic DQS data training but these values can be overwritten by a direct write to this register + * | | |Every three bits of this register control the latency of each of the (up to) four ranks + * | | |R0DGSL controls the latency of rank 0, R1DGSL controls rank 1, and so on + * | | |Valid values are 0 to 7. + * |[8:6] |R2DGSL |Rank n DQS Gating System Latency + * | | |This is used to increase the number of clock cycles needed to expect valid DDR read data by up to seven extra clock cycles + * | | |This is used to compensate for board delays and other system delays + * | | |Power-up default is 000 (i.e + * | | |no extra clock cycles required) + * | | |The SL fields are initially set by the PUB during automatic DQS data training but these values can be overwritten by a direct write to this register + * | | |Every three bits of this register control the latency of each of the (up to) four ranks + * | | |R0DGSL controls the latency of rank 0, R1DGSL controls rank 1, and so on + * | | |Valid values are 0 to 7. + * |[11:9] |R3DGSL |Rank n DQS Gating System Latency + * | | |This is used to increase the number of clock cycles needed to expect valid DDR read data by up to seven extra clock cycles + * | | |This is used to compensate for board delays and other system delays + * | | |Power-up default is 000 (i.e + * | | |no extra clock cycles required) + * | | |The SL fields are initially set by the PUB during automatic DQS data training but these values can be overwritten by a direct write to this register + * | | |Every three bits of this register control the latency of each of the (up to) four ranks + * | | |R0DGSL controls the latency of rank 0, R1DGSL controls rank 1, and so on + * | | |Valid values are 0 to 7. + * |[13:12] |R0WLSL |Rank n Write Leveling System Latency + * | | |This is used to adjust the write latency after write leveling + * | | |Power-up default is 01 (i.e + * | | |no extra clock cycles required) + * | | |The SL fields are initially set by the PUB during automatic write leveling but these values can be overwritten by a direct write to this register + * | | |Every two bits of this register control the latency of each of the (up to) four ranks + * | | |R0WLSL controls the latency of rank 0, R1WLSL controls rank 1, and so on + * | | |Valid values: + * | | |00 = Write latency = WL - 1 + * | | |01 = Write latency = WL + * | | |10 = Write latency = WL + 1 + * | | |11 = Reserved + * |[15:14] |R1WLSL |Rank n Write Leveling System Latency + * | | |This is used to adjust the write latency after write leveling + * | | |Power-up default is 01 (i.e + * | | |no extra clock cycles required) + * | | |The SL fields are initially set by the PUB during automatic write leveling but these values can be overwritten by a direct write to this register + * | | |Every two bits of this register control the latency of each of the (up to) four ranks + * | | |R0WLSL controls the latency of rank 0, R1WLSL controls rank 1, and so on + * | | |Valid values: + * | | |00 = Write latency = WL - 1 + * | | |01 = Write latency = WL + * | | |10 = Write latency = WL + 1 + * | | |11 = Reserved + * |[17:16] |R2WLSL |Rank n Write Leveling System Latency + * | | |This is used to adjust the write latency after write leveling + * | | |Power-up default is 01 (i.e + * | | |no extra clock cycles required) + * | | |The SL fields are initially set by the PUB during automatic write leveling but these values can be overwritten by a direct write to this register + * | | |Every two bits of this register control the latency of each of the (up to) four ranks + * | | |R0WLSL controls the latency of rank 0, R1WLSL controls rank 1, and so on + * | | |Valid values: + * | | |00 = Write latency = WL - 1 + * | | |01 = Write latency = WL + * | | |10 = Write latency = WL + 1 + * | | |11 = Reserved + * |[19:18] |R3WLSL |Rank n Write Leveling System Latency + * | | |This is used to adjust the write latency after write leveling + * | | |Power-up default is 01 (i.e + * | | |no extra clock cycles required) + * | | |The SL fields are initially set by the PUB during automatic write leveling but these values can be overwritten by a direct write to this register + * | | |Every two bits of this register control the latency of each of the (up to) four ranks + * | | |R0WLSL controls the latency of rank 0, R1WLSL controls rank 1, and so on + * | | |Valid values: + * | | |00 = Write latency = WL - 1 + * | | |01 = Write latency = WL + * | | |10 = Write latency = WL + 1 + * | | |11 = Reserved + * @var DDRPHY_T::DX6GSR2 + * Offset: 0x374 DATX8 General Status Register 2 (DXnGSR2) + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[0] |RDERR |Read Bit Deskew Error + * | | |Indicates, if set, that the DATX8 has encountered an error during execution of the read bit deskew training. + * |[1] |RDWN |Read Bit Deskew Warning + * | | |Indicates, if set, that the DATX8 has encountered a warning during execution of the read bit deskew training. + * |[2] |WDERR |Write Bit Deskew Error + * | | |Indicates, if set, that the DATX8 has encountered an error during execution of the write bit deskew training. + * |[3] |WDWN |Write Bit Deskew Warning + * | | |Indicates, if set, that the DATX8 has encountered a warning during execution of the write bit deskew training. + * |[4] |REERR |Read Data Eye Training Error + * | | |Indicates, if set, that the DATX8 has encountered an error during execution of the read data eye training. + * |[5] |REWN |Read Data Eye Training Warning + * | | |Indicates, if set, that the DATX8 has encountered a warning during execution of the read data eye training. + * |[6] |WEERR |Write Data Eye Training Error + * | | |Indicates, if set, that the DATX8 has encountered an error during execution of the write data eye training. + * |[7] |WEWN |Write Data Eye Training Warning + * | | |Indicates, if set, that the DATX8 has encountered a warning during execution of the write data eye training. + * |[11:8] |ESTAT |Error Status + * | | |If an error occurred for this lane as indicated by RDERR, WDERR, REERR or WEERR the error status code can provide additional information regard when the error occurred during the algorithm execution. + * @var DDRPHY_T::DX7GCR + * Offset: 0x380 DATX8 General Configuration Register (DXnGCR) + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[0] |DXEN |Data Byte Enable + * | | |Enables, if set, the data byte + * | | |Setting this bit to '0' disables the byte, i.e + * | | |the byte is not used in PHY initialization or training and is ignored during SDRAM read/write operations. + * |[1] |DQSODT |DQS On-Die Termination + * | | |Enables, when set, the on-die termination on the I/O for DQS/DQS# pin of the byte + * | | |This bit is ORed with the common DATX8 ODT configuration bit (see "DATX8 Common Configuration Register (DXCCR)"). + * | | |Note: This bit is only valid when DXnGCR0[9] is '0'. + * |[2] |DQODT |Data On-Die Termination + * | | |Enables, when set, the on-die termination on the I/O for DQ and DM pins of the byte + * | | |This bit is ORed with the common DATX8 ODT configuration bit (see "DATX8 Common Configuration Register (DXCCR)"). + * | | |Note: This bit is only valid when DXnGCR0[10] is '0'. + * |[3] |DXIOM |Data I/O Mode + * | | |Selects SSTL mode (when set to 0) or CMOS mode (when set to 1) of the I/O for DQ, DM, and DQS/DQS# pins of the byte + * | | |This bit is ORed with the IOM configuration bit of the individual DATX8(see "DATX8 Common Configuration Register (DXCCR)"). + * |[4] |DXPDD |Data Power Down Driver + * | | |Powers down, when set, the output driver on I/O for DQ, DM, and DQS/DQS# pins of the byte + * | | |This bit is ORed with the common PDD configuration bit (see "DATX8 Common Configuration Register (DXCCR)"). + * | | |Note: Asserting PDD puts the IO driver cell into a lower power, lower speed mode of operation + * | | |However, it will still drive if its OE is asserted + * | | |ODT will be disabled (if used) + * | | |Asserting PDD does not prevent the IO from driving. + * |[5] |DXPDR |Data Power Down Receiver + * | | |Powers down, when set, the input receiver on I/O for DQ, DM, and DQS/DQS# pins of the byte + * | | |This bit is ORed with the common PDR configuration bit (see "DATX8 Common Configuration Register (DXCCR)"). + * |[6] |DQSRPD |DQSR Power Down + * | | |Powers down, if set, the PDQSR cell + * | | |This bit is ORed with the common PDR configuration bit (see "DATX8 Common Configuration Register (DXCCR)") + * |[8:7] |DSEN |Write DQS Enable + * | | |Controls whether the write DQS going to the SDRAM is enabled (toggling) or disabled (static value) and whether the DQS is inverted + * | | |DQS# is always the inversion of DQS + * | | |These values are valid only when DQS/DQS# output enable is on, otherwise the DQS/DQS# is tristated + * | | |Valid settings are: + * | | |00 = Reserved + * | | |01 = DQS toggling with normal polarity (This should be the default setting) + * | | |10 = Reserved + * | | |11 = Reserved + * |[9] |DQSRTT |DQS Dynamic RTT Control + * | | |If set, the on die termination (ODT) control of the DQS/DQS# SSTL I/O is dynamically generated to enable the ODT during read operation and disabled otherwise + * | | |By setting this bit to '0' the dynamic ODT feature is disabled + * | | |To control ODT statically this bit must be set to '0' and DXnGCR0[1] (DQSODT) is used to enable ODT (when set to '1') or disable ODT(when set to '0'). + * |[10] |DQRTT |DQ Dynamic RTT Control + * | | |If set, the on die termination (ODT) control of the DQ/DM SSTL I/O is dynamically generated to enable the ODT during read operation and disabled otherwise + * | | |By setting this bit to '0' the dynamic ODT feature is disabled + * | | |To control ODT statically this bit must be set to '0' and DXnGCR0[2] (DQODT) is used to enable ODT (when set to '1') or disable ODT(when set to '0'). + * |[12:11] |RTTOH |RTT Output Hold + * | | |Indicates the number of clock cycles (from 0 to 3) after the read data postamble for which ODT control should remain set to DQSODT for DQS or DQODT for DQ/DM before disabling it (setting it to '0') when using dynamic ODT control + * | | |ODT is disabled almost RTTOH clock cycles after the read postamble. + * |[13] |RTTOAL |RTT On Additive Latency + * | | |Indicates when the ODT control of DQ/DQS SSTL I/Os is set to the value in DQODT/DQSODT during read cycles + * | | |Valid values are: + * | | |0 = ODT control is set to DQSODT/DQODT almost two cycles before read data preamble + * | | |1 = ODT control is set to DQSODT/DQODT almost one cycle before read data preamble + * |[15:14] |DXOEO |Data Byte Output Enable Override + * | | |Specifies whether the output I/O output enable for the byte lane should be set to a fixed value + * | | |Valid values are: + * | | |00 = No override. Output enable is controlled by DFI transactions + * | | |01 = Output enable is asserted (I/O is forced to output mode). + * | | |10 = Output enable is de-asserted (I/O is forced to input mode) + * | | |11 = Reserved + * |[16] |PLLRST |PLL Rest + * | | |Resets the byte PLL by driving the PLL reset pin + * | | |This bit is not self- clearing and a '0' must be written to de-assert the reset + * | | |This bit is ORed with the global PLLRST configuration bit. + * |[17] |PLLPD |PLL Power Down + * | | |Puts the byte PLL in Power-down mode by driving the PLL power down pin + * | | |This bit is not self-clearing and a '0' must be written to de-assert the power-down + * | | |This bit is ORed with the global PLLPD configuration bit. + * |[18] |GSHIFT |Gear Shift + * | | |Enables, if set, rapid locking mode on the byte PLL + * | | |This bit is ORed with the global GSHIFT configuration bit. + * |[19] |PLLBYP |PLL Bypass + * | | |Puts the byte PLL in bypass mode by driving the PLL bypass pin + * | | |This bit is not self-clearing and a '0' must be written to de-assert the bypass + * | | |This bit is ORed with the global BYP configuration bit. + * |[29:26] |WLRKEN |Write Level Rank Enable + * | | |Specifies the ranks that should be write leveled for this byte + * | | |Write leveling responses from ranks that are not enabled for write leveling for a particular byte are ignored and write leveling is flagged as done for these ranks + * | | |WLRKEN[0] enables rank 0, [1] enables rank 1, [2] enables rank 2, and [3] enables rank 3. + * |[30] |MDLEN |Master Delay Line Enable + * | | |Enables, if set, the DATX8 master delay line calibration to perform subsequent period measurements following the initial period measurements that are performed after reset or when calibration is manually triggered + * | | |These additional measurements are accumulated and filtered as long as this bit remains high + * | | |This bit is ANDed with the common DATX8 MDL enable bit. + * |[31] |CALBYP |Calibration Bypass + * | | |Prevents, if set, period measurement calibration from automatically triggering after PHY initialization. + * @var DDRPHY_T::DX7GSR0 + * Offset: 0x384 DATX8 General Status Registers 0 (DXnGSR0) + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[0] |WDQCAL |Write DQ Calibration + * | | |Indicates, if set, that the DATX8 has finished doing period measurement calibration for the write DQ LCDL. + * |[1] |RDQSCAL |Read DQS Calibration + * | | |Indicates, if set, that the DATX8 has finished doing period measurement calibration for the read DQS LCDL. + * |[2] |RDQSNCAL |Read DQS# Calibration + * | | |Indicates, if set, that the DATX8 has finished doing period measurement calibration for the read DQS# LCDL. + * |[3] |GDQSCAL |Read DQS gating Calibration + * | | |Indicates, if set, that the DATX8 has finished doing period measurement calibration for the read DQS gating LCDL. + * |[4] |WLCAL |Write Leveling Calibration + * | | |Indicates, if set, that the DATX8 has finished doing period measurement calibration for the write leveling slave delay line. + * |[5] |WLDONE |Write Leveling Done + * | | |Indicates, if set, that the DATX8 has completed write leveling. + * |[6] |WLERR |Write Leveling Error + * | | |Indicates, if set, that there is a write leveling error in the DATX8. + * |[14:7] |WLPRD |Write Leveling Period + * | | |Returns the DDR clock period measured by the write leveling LCDL during calibration + * | | |The measured period is used to generate the control of the write leveling pipeline which is a function of the write-leveling delay and the clock period + * | | |This value is PVT compensated. + * |[15] |DPLOCK |DATX8 PLL Lock + * | | |Indicates, if set, that the DATX8 PLL has locked. This is a direct status of the DATX8 PLL lock pin. + * |[23:16] |GDQSPRD |Read DQS gating Period + * | | |Returns the DDR clock period measured by the read DQS gating LCDL during calibration + * | | |This value is PVT compensated. + * |[27:24] |QSGERR |DQS Gate Training Error + * | | |Indicates, if set, that there is an error in DQS gate training. One bit for each of the up to 4 ranks. + * |[28] |WLDQ |Write Leveling DQ Status + * | | |Captures the write leveling DQ status from the DRAM during software write leveling. + * @var DDRPHY_T::DX7GSR1 + * Offset: 0x388 DATX8 General Status Registers 1 (DXnGSR1) + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[0] |DLTDONE |Delay Line Test Done + * | | |Indicates, if set, that the PHY control block has finished doing period measurement of the DATX8 delay line digital test output. + * |[24:1] |DLTCODE |Delay Line Test Code + * | | |Returns the code measured by the PHY control block that corresponds to the period of the DATX8 delay line digital test output. + * @var DDRPHY_T::DX7BDLR0 + * Offset: 0x38C DATX8 Bit Delay Line Register 0 (DXnBDLR0) + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[5:0] |DQ0WBD |DQ0 Write Bit Delay + * | | |Delay select for the BDL on DQ0 write path. + * |[11:6] |DQ1WBD |DQ1 Write Bit Delay + * | | |Delay select for the BDL on DQ1 write path. + * |[17:12] |DQ2WBD |DQ2 Write Bit Delay + * | | |Delay select for the BDL on DQ2 write path. + * |[23:18] |DQ3WBD |DQ3 Write Bit Delay + * | | |Delay select for the BDL on DQ3 write path + * |[29:24] |DQ4WBD |DQ4 Write Bit Delay + * | | |Delay select for the BDL on DQ4 write path. + * @var DDRPHY_T::DX7BDLR1 + * Offset: 0x390 DATX8 Bit Delay Line Register 1 (DXnBDLR1) + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[5:0] |DQ5WBD |DQ5 Write Bit Delay + * | | |Delay select for the BDL on DQ5 write path. + * |[11:6] |DQ6WBD |DQ6 Write Bit Delay + * | | |Delay select for the BDL on DQ6 write path. + * |[17:12] |DQ7WBD |DQ7 Write Bit Delay + * | | |Delay select for the BDL on DQ7 write path. + * |[23:18] |DMWBD |DM Write Bit Delay + * | | |Delay select for the BDL on DM write path. + * |[29:24] |DSWBD |DQS Write Bit Delay + * | | |Delay select for the BDL on DQS write path + * @var DDRPHY_T::DX7BDLR2 + * Offset: 0x394 DATX8 Bit Delay Line Register 2 (DXnBDLR2) + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[5:0] |DSOEBD |DQS Output Enable Bit Delay + * | | |Delay select for the BDL on DQS output enable path + * |[11:6] |DQOEBD |DQ Output Enable Bit Delay + * | | |Delay select for the BDL on DQ/DM output enable path. + * |[17:12] |DSRBD |DQS Read Bit Delay + * | | |Delay select for the BDL on DQS read path + * |[23:18] |DSNRBD |DQSN Read Bit Delay + * | | |Delay select for the BDL on DQSN read path + * @var DDRPHY_T::DX7BDLR3 + * Offset: 0x398 DATX8 Bit Delay Line Register 3 (DXnBDLR3) + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[5:0] |DQ0RBD |DQ0 Read Bit Delay + * | | |Delay select for the BDL on DQ0 read path. + * |[11:6] |DQ1RBD |DQ1 Read Bit Delay + * | | |Delay select for the BDL on DQ1 read path. + * |[17:12] |DQ2RBD |DQ2 Read Bit Delay + * | | |Delay select for the BDL on DQ2 read path. + * |[23:18] |DQ3RBD |DQ3 Read Bit Delay + * | | |Delay select for the BDL on DQ3 read path + * |[29:24] |DQ4RBD |DQ4 Read Bit Delay + * | | |Delay select for the BDL on DQ4 read path. + * @var DDRPHY_T::DX7BDLR4 + * Offset: 0x39C DATX8 Bit Delay Line Register 4 (DXnBDLR4) + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[5:0] |DQ5RBD |DQ5 Read Bit Delay + * | | |Delay select for the BDL on DQ5 read path. + * |[11:6] |DQ6RBD |DQ6 Read Bit Delay + * | | |Delay select for the BDL on DQ6 read path. + * |[17:12] |DQ7RBD |DQ7 Read Bit Delay + * | | |Delay select for the BDL on DQ7 read path. + * |[23:18] |DMRBD |DM Read Bit Delay + * | | |Delay select for the BDL on DM read path. + * @var DDRPHY_T::DX7LCDLR0 + * Offset: 0x3A0 DATX8 Bit Delay Line Register 0 (DXnBDLR0) + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[7:0] |R0WLD |Rank 0 Write Leveling Delay + * | | |Rank 0 delay select for the write leveling (WL) LCDL + * |[15:8] |R1WLD |Rank 1 Write Leveling Delay + * | | |Rank 1 delay select for the write leveling (WL) LCDL + * |[23:16] |R2WLD |Rank 2 Write Leveling Delay + * | | |Rank 2 delay select for the write leveling (WL) LCDL + * |[31:24] |R3WLD |Rank 3 Write Leveling Delay + * | | |Rank 3 delay select for the write leveling (WL) LCDL + * @var DDRPHY_T::DX7LCDLR1 + * Offset: 0x3A4 DATX8 Bit Delay Line Register 1 (DXnBDLR1) + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[7:0] |WDQD |Write Data Delay + * | | |Delay select for the write data (WDQ) LCDL + * |[15:8] |RDQSD |Read DQS Delay + * | | |Delay select for the read DQS (RDQS) LCDL + * |[23:16] |RDQSND |Read DQSN Delay + * | | |Delay select for the read DQSN (RDQS) LCDL + * @var DDRPHY_T::DX7LCDLR2 + * Offset: 0x3A8 DATX8 Bit Delay Line Register 2 (DXnBDLR2) + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[7:0] |R0DQSGD |Rank 0 Read DQS Gating Delay + * | | |Rank 0 delay select for the read DQS gating (DQSG) LCDL + * |[15:8] |R1DQSGD |Rank 1 Read DQS Gating Delay + * | | |Rank 1 delay select for the read DQS gating (DQSG) LCDL + * |[23:16] |R2DQSGD |Rank 2 Read DQS Gating Delay + * | | |Rank 2 delay select for the read DQS gating (DQSG) LCDL + * |[31:24] |R3DQSGD |Rank 3 Read DQS Gating Delay + * | | |Rank 3 delay select for the read DQS gating (DQSG) LCDL + * @var DDRPHY_T::DX7MDLR + * Offset: 0x3AC DATX8 Master Delay Line Register (DXnMDLR) + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[7:0] |IPRD |Initial Period + * | | |Initial period measured by the master delay line calibration for VT drift compensation + * | | |This value is used as the denominator when calculating the ratios of updates during VT compensation. + * |[15:8] |TPRD |Target Period + * | | |Target period measured by the master delay line calibration for VT drift compensation + * | | |This is the current measured value of the period and is continuously updated if the MDL is enabled to do so. + * |[23:16] |MDLD |MDL Delay + * | | |Delay select for the LCDL for the Master Delay Line. + * @var DDRPHY_T::DX7GTR + * Offset: 0x3B0 DATX8 General Timing Register (DXnGTR) + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[2:0] |R0DGSL |Rank n DQS Gating System Latency + * | | |This is used to increase the number of clock cycles needed to expect valid DDR read data by up to seven extra clock cycles + * | | |This is used to compensate for board delays and other system delays + * | | |Power-up default is 000 (i.e + * | | |no extra clock cycles required) + * | | |The SL fields are initially set by the PUB during automatic DQS data training but these values can be overwritten by a direct write to this register + * | | |Every three bits of this register control the latency of each of the (up to) four ranks + * | | |R0DGSL controls the latency of rank 0, R1DGSL controls rank 1, and so on + * | | |Valid values are 0 to 7. + * |[5:3] |R1DGSL |Rank n DQS Gating System Latency + * | | |This is used to increase the number of clock cycles needed to expect valid DDR read data by up to seven extra clock cycles + * | | |This is used to compensate for board delays and other system delays + * | | |Power-up default is 000 (i.e + * | | |no extra clock cycles required) + * | | |The SL fields are initially set by the PUB during automatic DQS data training but these values can be overwritten by a direct write to this register + * | | |Every three bits of this register control the latency of each of the (up to) four ranks + * | | |R0DGSL controls the latency of rank 0, R1DGSL controls rank 1, and so on + * | | |Valid values are 0 to 7. + * |[8:6] |R2DGSL |Rank n DQS Gating System Latency + * | | |This is used to increase the number of clock cycles needed to expect valid DDR read data by up to seven extra clock cycles + * | | |This is used to compensate for board delays and other system delays + * | | |Power-up default is 000 (i.e + * | | |no extra clock cycles required) + * | | |The SL fields are initially set by the PUB during automatic DQS data training but these values can be overwritten by a direct write to this register + * | | |Every three bits of this register control the latency of each of the (up to) four ranks + * | | |R0DGSL controls the latency of rank 0, R1DGSL controls rank 1, and so on + * | | |Valid values are 0 to 7. + * |[11:9] |R3DGSL |Rank n DQS Gating System Latency + * | | |This is used to increase the number of clock cycles needed to expect valid DDR read data by up to seven extra clock cycles + * | | |This is used to compensate for board delays and other system delays + * | | |Power-up default is 000 (i.e + * | | |no extra clock cycles required) + * | | |The SL fields are initially set by the PUB during automatic DQS data training but these values can be overwritten by a direct write to this register + * | | |Every three bits of this register control the latency of each of the (up to) four ranks + * | | |R0DGSL controls the latency of rank 0, R1DGSL controls rank 1, and so on + * | | |Valid values are 0 to 7. + * |[13:12] |R0WLSL |Rank n Write Leveling System Latency + * | | |This is used to adjust the write latency after write leveling + * | | |Power-up default is 01 (i.e + * | | |no extra clock cycles required) + * | | |The SL fields are initially set by the PUB during automatic write leveling but these values can be overwritten by a direct write to this register + * | | |Every two bits of this register control the latency of each of the (up to) four ranks + * | | |R0WLSL controls the latency of rank 0, R1WLSL controls rank 1, and so on + * | | |Valid values: + * | | |00 = Write latency = WL - 1 + * | | |01 = Write latency = WL + * | | |10 = Write latency = WL + 1 + * | | |11 = Reserved + * |[15:14] |R1WLSL |Rank n Write Leveling System Latency + * | | |This is used to adjust the write latency after write leveling + * | | |Power-up default is 01 (i.e + * | | |no extra clock cycles required) + * | | |The SL fields are initially set by the PUB during automatic write leveling but these values can be overwritten by a direct write to this register + * | | |Every two bits of this register control the latency of each of the (up to) four ranks + * | | |R0WLSL controls the latency of rank 0, R1WLSL controls rank 1, and so on + * | | |Valid values: + * | | |00 = Write latency = WL - 1 + * | | |01 = Write latency = WL + * | | |10 = Write latency = WL + 1 + * | | |11 = Reserved + * |[17:16] |R2WLSL |Rank n Write Leveling System Latency + * | | |This is used to adjust the write latency after write leveling + * | | |Power-up default is 01 (i.e + * | | |no extra clock cycles required) + * | | |The SL fields are initially set by the PUB during automatic write leveling but these values can be overwritten by a direct write to this register + * | | |Every two bits of this register control the latency of each of the (up to) four ranks + * | | |R0WLSL controls the latency of rank 0, R1WLSL controls rank 1, and so on + * | | |Valid values: + * | | |00 = Write latency = WL - 1 + * | | |01 = Write latency = WL + * | | |10 = Write latency = WL + 1 + * | | |11 = Reserved + * |[19:18] |R3WLSL |Rank n Write Leveling System Latency + * | | |This is used to adjust the write latency after write leveling + * | | |Power-up default is 01 (i.e + * | | |no extra clock cycles required) + * | | |The SL fields are initially set by the PUB during automatic write leveling but these values can be overwritten by a direct write to this register + * | | |Every two bits of this register control the latency of each of the (up to) four ranks + * | | |R0WLSL controls the latency of rank 0, R1WLSL controls rank 1, and so on + * | | |Valid values: + * | | |00 = Write latency = WL - 1 + * | | |01 = Write latency = WL + * | | |10 = Write latency = WL + 1 + * | | |11 = Reserved + * @var DDRPHY_T::DX7GSR2 + * Offset: 0x3B4 DATX8 General Status Register 2 (DXnGSR2) + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[0] |RDERR |Read Bit Deskew Error + * | | |Indicates, if set, that the DATX8 has encountered an error during execution of the read bit deskew training. + * |[1] |RDWN |Read Bit Deskew Warning + * | | |Indicates, if set, that the DATX8 has encountered a warning during execution of the read bit deskew training. + * |[2] |WDERR |Write Bit Deskew Error + * | | |Indicates, if set, that the DATX8 has encountered an error during execution of the write bit deskew training. + * |[3] |WDWN |Write Bit Deskew Warning + * | | |Indicates, if set, that the DATX8 has encountered a warning during execution of the write bit deskew training. + * |[4] |REERR |Read Data Eye Training Error + * | | |Indicates, if set, that the DATX8 has encountered an error during execution of the read data eye training. + * |[5] |REWN |Read Data Eye Training Warning + * | | |Indicates, if set, that the DATX8 has encountered a warning during execution of the read data eye training. + * |[6] |WEERR |Write Data Eye Training Error + * | | |Indicates, if set, that the DATX8 has encountered an error during execution of the write data eye training. + * |[7] |WEWN |Write Data Eye Training Warning + * | | |Indicates, if set, that the DATX8 has encountered a warning during execution of the write data eye training. + * |[11:8] |ESTAT |Error Status + * | | |If an error occurred for this lane as indicated by RDERR, WDERR, REERR or WEERR the error status code can provide additional information regard when the error occurred during the algorithm execution. + * @var DDRPHY_T::DX8GCR + * Offset: 0x3C0 DATX8 General Configuration Register (DXnGCR) + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[0] |DXEN |Data Byte Enable + * | | |Enables, if set, the data byte + * | | |Setting this bit to '0' disables the byte, i.e + * | | |the byte is not used in PHY initialization or training and is ignored during SDRAM read/write operations. + * |[1] |DQSODT |DQS On-Die Termination + * | | |Enables, when set, the on-die termination on the I/O for DQS/DQS# pin of the byte + * | | |This bit is ORed with the common DATX8 ODT configuration bit (see "DATX8 Common Configuration Register (DXCCR)"). + * | | |Note: This bit is only valid when DXnGCR0[9] is '0'. + * |[2] |DQODT |Data On-Die Termination + * | | |Enables, when set, the on-die termination on the I/O for DQ and DM pins of the byte + * | | |This bit is ORed with the common DATX8 ODT configuration bit (see "DATX8 Common Configuration Register (DXCCR)"). + * | | |Note: This bit is only valid when DXnGCR0[10] is '0'. + * |[3] |DXIOM |Data I/O Mode + * | | |Selects SSTL mode (when set to 0) or CMOS mode (when set to 1) of the I/O for DQ, DM, and DQS/DQS# pins of the byte + * | | |This bit is ORed with the IOM configuration bit of the individual DATX8(see "DATX8 Common Configuration Register (DXCCR)"). + * |[4] |DXPDD |Data Power Down Driver + * | | |Powers down, when set, the output driver on I/O for DQ, DM, and DQS/DQS# pins of the byte + * | | |This bit is ORed with the common PDD configuration bit (see "DATX8 Common Configuration Register (DXCCR)"). + * | | |Note: Asserting PDD puts the IO driver cell into a lower power, lower speed mode of operation + * | | |However, it will still drive if its OE is asserted + * | | |ODT will be disabled (if used) + * | | |Asserting PDD does not prevent the IO from driving. + * |[5] |DXPDR |Data Power Down Receiver + * | | |Powers down, when set, the input receiver on I/O for DQ, DM, and DQS/DQS# pins of the byte + * | | |This bit is ORed with the common PDR configuration bit (see "DATX8 Common Configuration Register (DXCCR)"). + * |[6] |DQSRPD |DQSR Power Down + * | | |Powers down, if set, the PDQSR cell + * | | |This bit is ORed with the common PDR configuration bit (see "DATX8 Common Configuration Register (DXCCR)") + * |[8:7] |DSEN |Write DQS Enable + * | | |Controls whether the write DQS going to the SDRAM is enabled (toggling) or disabled (static value) and whether the DQS is inverted + * | | |DQS# is always the inversion of DQS + * | | |These values are valid only when DQS/DQS# output enable is on, otherwise the DQS/DQS# is tristated + * | | |Valid settings are: + * | | |00 = Reserved + * | | |01 = DQS toggling with normal polarity (This should be the default setting) + * | | |10 = Reserved + * | | |11 = Reserved + * |[9] |DQSRTT |DQS Dynamic RTT Control + * | | |If set, the on die termination (ODT) control of the DQS/DQS# SSTL I/O is dynamically generated to enable the ODT during read operation and disabled otherwise + * | | |By setting this bit to '0' the dynamic ODT feature is disabled + * | | |To control ODT statically this bit must be set to '0' and DXnGCR0[1] (DQSODT) is used to enable ODT (when set to '1') or disable ODT(when set to '0'). + * |[10] |DQRTT |DQ Dynamic RTT Control + * | | |If set, the on die termination (ODT) control of the DQ/DM SSTL I/O is dynamically generated to enable the ODT during read operation and disabled otherwise + * | | |By setting this bit to '0' the dynamic ODT feature is disabled + * | | |To control ODT statically this bit must be set to '0' and DXnGCR0[2] (DQODT) is used to enable ODT (when set to '1') or disable ODT(when set to '0'). + * |[12:11] |RTTOH |RTT Output Hold + * | | |Indicates the number of clock cycles (from 0 to 3) after the read data postamble for which ODT control should remain set to DQSODT for DQS or DQODT for DQ/DM before disabling it (setting it to '0') when using dynamic ODT control + * | | |ODT is disabled almost RTTOH clock cycles after the read postamble. + * |[13] |RTTOAL |RTT On Additive Latency + * | | |Indicates when the ODT control of DQ/DQS SSTL I/Os is set to the value in DQODT/DQSODT during read cycles + * | | |Valid values are: + * | | |0 = ODT control is set to DQSODT/DQODT almost two cycles before read data preamble + * | | |1 = ODT control is set to DQSODT/DQODT almost one cycle before read data preamble + * |[15:14] |DXOEO |Data Byte Output Enable Override + * | | |Specifies whether the output I/O output enable for the byte lane should be set to a fixed value + * | | |Valid values are: + * | | |00 = No override. Output enable is controlled by DFI transactions + * | | |01 = Output enable is asserted (I/O is forced to output mode). + * | | |10 = Output enable is de-asserted (I/O is forced to input mode) + * | | |11 = Reserved + * |[16] |PLLRST |PLL Rest + * | | |Resets the byte PLL by driving the PLL reset pin + * | | |This bit is not self- clearing and a '0' must be written to de-assert the reset + * | | |This bit is ORed with the global PLLRST configuration bit. + * |[17] |PLLPD |PLL Power Down + * | | |Puts the byte PLL in Power-down mode by driving the PLL power down pin + * | | |This bit is not self-clearing and a '0' must be written to de-assert the power-down + * | | |This bit is ORed with the global PLLPD configuration bit. + * |[18] |GSHIFT |Gear Shift + * | | |Enables, if set, rapid locking mode on the byte PLL + * | | |This bit is ORed with the global GSHIFT configuration bit. + * |[19] |PLLBYP |PLL Bypass + * | | |Puts the byte PLL in bypass mode by driving the PLL bypass pin + * | | |This bit is not self-clearing and a '0' must be written to de-assert the bypass + * | | |This bit is ORed with the global BYP configuration bit. + * |[29:26] |WLRKEN |Write Level Rank Enable + * | | |Specifies the ranks that should be write leveled for this byte + * | | |Write leveling responses from ranks that are not enabled for write leveling for a particular byte are ignored and write leveling is flagged as done for these ranks + * | | |WLRKEN[0] enables rank 0, [1] enables rank 1, [2] enables rank 2, and [3] enables rank 3. + * |[30] |MDLEN |Master Delay Line Enable + * | | |Enables, if set, the DATX8 master delay line calibration to perform subsequent period measurements following the initial period measurements that are performed after reset or when calibration is manually triggered + * | | |These additional measurements are accumulated and filtered as long as this bit remains high + * | | |This bit is ANDed with the common DATX8 MDL enable bit. + * |[31] |CALBYP |Calibration Bypass + * | | |Prevents, if set, period measurement calibration from automatically triggering after PHY initialization. + * @var DDRPHY_T::DX8GSR0 + * Offset: 0x3C4 DATX8 General Status Registers 0 (DXnGSR0) + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[0] |WDQCAL |Write DQ Calibration + * | | |Indicates, if set, that the DATX8 has finished doing period measurement calibration for the write DQ LCDL. + * |[1] |RDQSCAL |Read DQS Calibration + * | | |Indicates, if set, that the DATX8 has finished doing period measurement calibration for the read DQS LCDL. + * |[2] |RDQSNCAL |Read DQS# Calibration + * | | |Indicates, if set, that the DATX8 has finished doing period measurement calibration for the read DQS# LCDL. + * |[3] |GDQSCAL |Read DQS gating Calibration + * | | |Indicates, if set, that the DATX8 has finished doing period measurement calibration for the read DQS gating LCDL. + * |[4] |WLCAL |Write Leveling Calibration + * | | |Indicates, if set, that the DATX8 has finished doing period measurement calibration for the write leveling slave delay line. + * |[5] |WLDONE |Write Leveling Done + * | | |Indicates, if set, that the DATX8 has completed write leveling. + * |[6] |WLERR |Write Leveling Error + * | | |Indicates, if set, that there is a write leveling error in the DATX8. + * |[14:7] |WLPRD |Write Leveling Period + * | | |Returns the DDR clock period measured by the write leveling LCDL during calibration + * | | |The measured period is used to generate the control of the write leveling pipeline which is a function of the write-leveling delay and the clock period + * | | |This value is PVT compensated. + * |[15] |DPLOCK |DATX8 PLL Lock + * | | |Indicates, if set, that the DATX8 PLL has locked. This is a direct status of the DATX8 PLL lock pin. + * |[23:16] |GDQSPRD |Read DQS gating Period + * | | |Returns the DDR clock period measured by the read DQS gating LCDL during calibration + * | | |This value is PVT compensated. + * |[27:24] |QSGERR |DQS Gate Training Error + * | | |Indicates, if set, that there is an error in DQS gate training. One bit for each of the up to 4 ranks. + * |[28] |WLDQ |Write Leveling DQ Status + * | | |Captures the write leveling DQ status from the DRAM during software write leveling. + * @var DDRPHY_T::DX8GSR1 + * Offset: 0x3C8 DATX8 General Status Registers 1 (DXnGSR1) + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[0] |DLTDONE |Delay Line Test Done + * | | |Indicates, if set, that the PHY control block has finished doing period measurement of the DATX8 delay line digital test output. + * |[24:1] |DLTCODE |Delay Line Test Code + * | | |Returns the code measured by the PHY control block that corresponds to the period of the DATX8 delay line digital test output. + * @var DDRPHY_T::DX8BDLR0 + * Offset: 0x3CC DATX8 Bit Delay Line Register 0 (DXnBDLR0) + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[5:0] |DQ0WBD |DQ0 Write Bit Delay + * | | |Delay select for the BDL on DQ0 write path. + * |[11:6] |DQ1WBD |DQ1 Write Bit Delay + * | | |Delay select for the BDL on DQ1 write path. + * |[17:12] |DQ2WBD |DQ2 Write Bit Delay + * | | |Delay select for the BDL on DQ2 write path. + * |[23:18] |DQ3WBD |DQ3 Write Bit Delay + * | | |Delay select for the BDL on DQ3 write path + * |[29:24] |DQ4WBD |DQ4 Write Bit Delay + * | | |Delay select for the BDL on DQ4 write path. + * @var DDRPHY_T::DX8BDLR1 + * Offset: 0x3D0 DATX8 Bit Delay Line Register 1 (DXnBDLR1) + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[5:0] |DQ5WBD |DQ5 Write Bit Delay + * | | |Delay select for the BDL on DQ5 write path. + * |[11:6] |DQ6WBD |DQ6 Write Bit Delay + * | | |Delay select for the BDL on DQ6 write path. + * |[17:12] |DQ7WBD |DQ7 Write Bit Delay + * | | |Delay select for the BDL on DQ7 write path. + * |[23:18] |DMWBD |DM Write Bit Delay + * | | |Delay select for the BDL on DM write path. + * |[29:24] |DSWBD |DQS Write Bit Delay + * | | |Delay select for the BDL on DQS write path + * @var DDRPHY_T::DX8BDLR2 + * Offset: 0x3D4 DATX8 Bit Delay Line Register 2 (DXnBDLR2) + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[5:0] |DSOEBD |DQS Output Enable Bit Delay + * | | |Delay select for the BDL on DQS output enable path + * |[11:6] |DQOEBD |DQ Output Enable Bit Delay + * | | |Delay select for the BDL on DQ/DM output enable path. + * |[17:12] |DSRBD |DQS Read Bit Delay + * | | |Delay select for the BDL on DQS read path + * |[23:18] |DSNRBD |DQSN Read Bit Delay + * | | |Delay select for the BDL on DQSN read path + * @var DDRPHY_T::DX8BDLR3 + * Offset: 0x3D8 DATX8 Bit Delay Line Register 3 (DXnBDLR3) + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[5:0] |DQ0RBD |DQ0 Read Bit Delay + * | | |Delay select for the BDL on DQ0 read path. + * |[11:6] |DQ1RBD |DQ1 Read Bit Delay + * | | |Delay select for the BDL on DQ1 read path. + * |[17:12] |DQ2RBD |DQ2 Read Bit Delay + * | | |Delay select for the BDL on DQ2 read path. + * |[23:18] |DQ3RBD |DQ3 Read Bit Delay + * | | |Delay select for the BDL on DQ3 read path + * |[29:24] |DQ4RBD |DQ4 Read Bit Delay + * | | |Delay select for the BDL on DQ4 read path. + * @var DDRPHY_T::DX8BDLR4 + * Offset: 0x3DC DATX8 Bit Delay Line Register 4 (DXnBDLR4) + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[5:0] |DQ5RBD |DQ5 Read Bit Delay + * | | |Delay select for the BDL on DQ5 read path. + * |[11:6] |DQ6RBD |DQ6 Read Bit Delay + * | | |Delay select for the BDL on DQ6 read path. + * |[17:12] |DQ7RBD |DQ7 Read Bit Delay + * | | |Delay select for the BDL on DQ7 read path. + * |[23:18] |DMRBD |DM Read Bit Delay + * | | |Delay select for the BDL on DM read path. + * @var DDRPHY_T::DX8LCDLR0 + * Offset: 0x3E0 DATX8 Bit Delay Line Register 0 (DXnBDLR0) + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[7:0] |R0WLD |Rank 0 Write Leveling Delay + * | | |Rank 0 delay select for the write leveling (WL) LCDL + * |[15:8] |R1WLD |Rank 1 Write Leveling Delay + * | | |Rank 1 delay select for the write leveling (WL) LCDL + * |[23:16] |R2WLD |Rank 2 Write Leveling Delay + * | | |Rank 2 delay select for the write leveling (WL) LCDL + * |[31:24] |R3WLD |Rank 3 Write Leveling Delay + * | | |Rank 3 delay select for the write leveling (WL) LCDL + * @var DDRPHY_T::DX8LCDLR1 + * Offset: 0x3E4 DATX8 Bit Delay Line Register 1 (DXnBDLR1) + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[7:0] |WDQD |Write Data Delay + * | | |Delay select for the write data (WDQ) LCDL + * |[15:8] |RDQSD |Read DQS Delay + * | | |Delay select for the read DQS (RDQS) LCDL + * |[23:16] |RDQSND |Read DQSN Delay + * | | |Delay select for the read DQSN (RDQS) LCDL + * @var DDRPHY_T::DX8LCDLR2 + * Offset: 0x3E8 DATX8 Bit Delay Line Register 2 (DXnBDLR2) + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[7:0] |R0DQSGD |Rank 0 Read DQS Gating Delay + * | | |Rank 0 delay select for the read DQS gating (DQSG) LCDL + * |[15:8] |R1DQSGD |Rank 1 Read DQS Gating Delay + * | | |Rank 1 delay select for the read DQS gating (DQSG) LCDL + * |[23:16] |R2DQSGD |Rank 2 Read DQS Gating Delay + * | | |Rank 2 delay select for the read DQS gating (DQSG) LCDL + * |[31:24] |R3DQSGD |Rank 3 Read DQS Gating Delay + * | | |Rank 3 delay select for the read DQS gating (DQSG) LCDL + * @var DDRPHY_T::DX8MDLR + * Offset: 0x3EC DATX8 Master Delay Line Register (DXnMDLR) + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[7:0] |IPRD |Initial Period + * | | |Initial period measured by the master delay line calibration for VT drift compensation + * | | |This value is used as the denominator when calculating the ratios of updates during VT compensation. + * |[15:8] |TPRD |Target Period + * | | |Target period measured by the master delay line calibration for VT drift compensation + * | | |This is the current measured value of the period and is continuously updated if the MDL is enabled to do so. + * |[23:16] |MDLD |MDL Delay + * | | |Delay select for the LCDL for the Master Delay Line. + * @var DDRPHY_T::DX8GTR + * Offset: 0x3F0 DATX8 General Timing Register (DXnGTR) + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[2:0] |R0DGSL |Rank n DQS Gating System Latency + * | | |This is used to increase the number of clock cycles needed to expect valid DDR read data by up to seven extra clock cycles + * | | |This is used to compensate for board delays and other system delays + * | | |Power-up default is 000 (i.e + * | | |no extra clock cycles required) + * | | |The SL fields are initially set by the PUB during automatic DQS data training but these values can be overwritten by a direct write to this register + * | | |Every three bits of this register control the latency of each of the (up to) four ranks + * | | |R0DGSL controls the latency of rank 0, R1DGSL controls rank 1, and so on + * | | |Valid values are 0 to 7. + * |[5:3] |R1DGSL |Rank n DQS Gating System Latency + * | | |This is used to increase the number of clock cycles needed to expect valid DDR read data by up to seven extra clock cycles + * | | |This is used to compensate for board delays and other system delays + * | | |Power-up default is 000 (i.e + * | | |no extra clock cycles required) + * | | |The SL fields are initially set by the PUB during automatic DQS data training but these values can be overwritten by a direct write to this register + * | | |Every three bits of this register control the latency of each of the (up to) four ranks + * | | |R0DGSL controls the latency of rank 0, R1DGSL controls rank 1, and so on + * | | |Valid values are 0 to 7. + * |[8:6] |R2DGSL |Rank n DQS Gating System Latency + * | | |This is used to increase the number of clock cycles needed to expect valid DDR read data by up to seven extra clock cycles + * | | |This is used to compensate for board delays and other system delays + * | | |Power-up default is 000 (i.e + * | | |no extra clock cycles required) + * | | |The SL fields are initially set by the PUB during automatic DQS data training but these values can be overwritten by a direct write to this register + * | | |Every three bits of this register control the latency of each of the (up to) four ranks + * | | |R0DGSL controls the latency of rank 0, R1DGSL controls rank 1, and so on + * | | |Valid values are 0 to 7. + * |[11:9] |R3DGSL |Rank n DQS Gating System Latency + * | | |This is used to increase the number of clock cycles needed to expect valid DDR read data by up to seven extra clock cycles + * | | |This is used to compensate for board delays and other system delays + * | | |Power-up default is 000 (i.e + * | | |no extra clock cycles required) + * | | |The SL fields are initially set by the PUB during automatic DQS data training but these values can be overwritten by a direct write to this register + * | | |Every three bits of this register control the latency of each of the (up to) four ranks + * | | |R0DGSL controls the latency of rank 0, R1DGSL controls rank 1, and so on + * | | |Valid values are 0 to 7. + * |[13:12] |R0WLSL |Rank n Write Leveling System Latency + * | | |This is used to adjust the write latency after write leveling + * | | |Power-up default is 01 (i.e + * | | |no extra clock cycles required) + * | | |The SL fields are initially set by the PUB during automatic write leveling but these values can be overwritten by a direct write to this register + * | | |Every two bits of this register control the latency of each of the (up to) four ranks + * | | |R0WLSL controls the latency of rank 0, R1WLSL controls rank 1, and so on + * | | |Valid values: + * | | |00 = Write latency = WL - 1 + * | | |01 = Write latency = WL + * | | |10 = Write latency = WL + 1 + * | | |11 = Reserved + * |[15:14] |R1WLSL |Rank n Write Leveling System Latency + * | | |This is used to adjust the write latency after write leveling + * | | |Power-up default is 01 (i.e + * | | |no extra clock cycles required) + * | | |The SL fields are initially set by the PUB during automatic write leveling but these values can be overwritten by a direct write to this register + * | | |Every two bits of this register control the latency of each of the (up to) four ranks + * | | |R0WLSL controls the latency of rank 0, R1WLSL controls rank 1, and so on + * | | |Valid values: + * | | |00 = Write latency = WL - 1 + * | | |01 = Write latency = WL + * | | |10 = Write latency = WL + 1 + * | | |11 = Reserved + * |[17:16] |R2WLSL |Rank n Write Leveling System Latency + * | | |This is used to adjust the write latency after write leveling + * | | |Power-up default is 01 (i.e + * | | |no extra clock cycles required) + * | | |The SL fields are initially set by the PUB during automatic write leveling but these values can be overwritten by a direct write to this register + * | | |Every two bits of this register control the latency of each of the (up to) four ranks + * | | |R0WLSL controls the latency of rank 0, R1WLSL controls rank 1, and so on + * | | |Valid values: + * | | |00 = Write latency = WL - 1 + * | | |01 = Write latency = WL + * | | |10 = Write latency = WL + 1 + * | | |11 = Reserved + * |[19:18] |R3WLSL |Rank n Write Leveling System Latency + * | | |This is used to adjust the write latency after write leveling + * | | |Power-up default is 01 (i.e + * | | |no extra clock cycles required) + * | | |The SL fields are initially set by the PUB during automatic write leveling but these values can be overwritten by a direct write to this register + * | | |Every two bits of this register control the latency of each of the (up to) four ranks + * | | |R0WLSL controls the latency of rank 0, R1WLSL controls rank 1, and so on + * | | |Valid values: + * | | |00 = Write latency = WL - 1 + * | | |01 = Write latency = WL + * | | |10 = Write latency = WL + 1 + * | | |11 = Reserved + * @var DDRPHY_T::DX8GSR2 + * Offset: 0x3F4 DATX8 General Status Register 2 (DXnGSR2) + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[0] |RDERR |Read Bit Deskew Error + * | | |Indicates, if set, that the DATX8 has encountered an error during execution of the read bit deskew training. + * |[1] |RDWN |Read Bit Deskew Warning + * | | |Indicates, if set, that the DATX8 has encountered a warning during execution of the read bit deskew training. + * |[2] |WDERR |Write Bit Deskew Error + * | | |Indicates, if set, that the DATX8 has encountered an error during execution of the write bit deskew training. + * |[3] |WDWN |Write Bit Deskew Warning + * | | |Indicates, if set, that the DATX8 has encountered a warning during execution of the write bit deskew training. + * |[4] |REERR |Read Data Eye Training Error + * | | |Indicates, if set, that the DATX8 has encountered an error during execution of the read data eye training. + * |[5] |REWN |Read Data Eye Training Warning + * | | |Indicates, if set, that the DATX8 has encountered a warning during execution of the read data eye training. + * |[6] |WEERR |Write Data Eye Training Error + * | | |Indicates, if set, that the DATX8 has encountered an error during execution of the write data eye training. + * |[7] |WEWN |Write Data Eye Training Warning + * | | |Indicates, if set, that the DATX8 has encountered a warning during execution of the write data eye training. + * |[11:8] |ESTAT |Error Status + * | | |If an error occurred for this lane as indicated by RDERR, WDERR, REERR or WEERR the error status code can provide additional information regard when the error occurred during the algorithm execution. + */ + __I uint32_t RIDR; /*!< [0x0000] Revision Identification Register */ + __IO uint32_t PIR; /*!< [0x0004] PHY Initialization Register (PIR) */ + __IO uint32_t PGCR0; /*!< [0x0008] PHY General Configuration Registers 0 (PGCR0) */ + __IO uint32_t PGCR1; /*!< [0x000c] PHY General Configuration Registers 1 (PGCR1) */ + __I uint32_t PGSR0; /*!< [0x0010] PHY General Status Registers 0 (PGSR0) */ + __I uint32_t PGSR1; /*!< [0x0014] PHY General Status Registers 1 (PGSR1) */ + __IO uint32_t PLLCR; /*!< [0x0018] PLL Control Register (PLLCR) */ + __IO uint32_t PTR0; /*!< [0x001c] PHY Timing Registers 0 (PTR0) */ + __IO uint32_t PTR1; /*!< [0x0020] PHY Timing Registers 1 (PTR1) */ + __IO uint32_t PTR2; /*!< [0x0024] PHY Timing Registers 2 (PTR2) */ + __IO uint32_t PTR3; /*!< [0x0028] PHY Timing Registers 3 (PTR3) */ + __IO uint32_t PTR4; /*!< [0x002c] PHY Timing Registers 4 (PTR4) */ + __IO uint32_t ACMDLR; /*!< [0x0030] AC Master Delay Line Register (ACMDLR) */ + __IO uint32_t ACBDLR; /*!< [0x0034] AC Bit Delay Line Register (ACBDLR) */ + __IO uint32_t ACIOCR; /*!< [0x0038] AC I/O Configuration Register (ACIOCR) */ + __IO uint32_t DXCCR; /*!< [0x003c] DATX8 Common Configuration Register (DXCCR) */ + __IO uint32_t DSGCR; /*!< [0x0040] DDR System General Configuration Register (DSGCR) */ + __IO uint32_t DCR; /*!< [0x0044] DRAM Configuration Register (DCR) */ + __IO uint32_t DTPR0; /*!< [0x0048] DRAM Timing Parameters Register 0 (DTPR0) 105 */ + __IO uint32_t DTPR1; /*!< [0x004c] DRAM Timing Parameters Register 1 (DTPR1) */ + __IO uint32_t DTPR2; /*!< [0x0050] DRAM Timing Parameters Register 2 (DTPR2) */ + __IO uint32_t MR0; /*!< [0x0054] Mode Register 0 (MR0) */ + __IO uint32_t MR1; /*!< [0x0058] Mode Register 1 (MR1) */ + __IO uint32_t MR2; /*!< [0x005c] Mode Register 2/Extended Mode Register 2 (MR2/EMR2) */ + __IO uint32_t MR3; /*!< [0x0060] Mode Register 3 (MR3) */ + __IO uint32_t ODTCR; /*!< [0x0064] ODT Configuration Register (ODTCR) */ + __IO uint32_t DTCR; /*!< [0x0068] Data Training Configuration Register (DTCR) */ + __IO uint32_t DTAR0; /*!< [0x006c] Data Training Address Register 0 (DTAR0) */ + __IO uint32_t DTAR1; /*!< [0x0070] Data Training Address Register 1 (DTAR1) */ + __IO uint32_t DTAR2; /*!< [0x0074] Data Training Address Register 2 (DTAR2) */ + __IO uint32_t DTAR3; /*!< [0x0078] Data Training Address Register 3 (DTAR3) */ + __IO uint32_t DTDR0; /*!< [0x007c] Data Training Data Register 0 (DTDR0) */ + __IO uint32_t DTDR1; /*!< [0x0080] Data Training Data Register 1 (DTDR1) */ + __I uint32_t DTEDR0; /*!< [0x0084] Data Training Eye Data Register 0 (DTEDR0) */ + __I uint32_t DTEDR1; /*!< [0x0088] Data Training Eye Data Register 1 (DTEDR1) */ + __IO uint32_t PGCR2; /*!< [0x008c] PHY General Configuration Register 2 (PGCR2) */ + __I uint32_t RESERVE0[8]; + __I uint32_t RDIMMGCR0; /*!< [0x00b0] RDIMM General Configuration Register 0 (RDIMMGCR0) 123 */ + __I uint32_t RDIMMGCR1; /*!< [0x00b4] RDIMM General Configuration Register 1 (RDIMMGCR1) */ + __I uint32_t RDIMMCR0; /*!< [0x00b8] RDIMM Control Register 0 (RDIMMCR0) */ + __I uint32_t RDIMMCR1; /*!< [0x00bc] RDIMM Control Register 1 (RDIMMCR1) */ + __IO uint32_t DCUAR; /*!< [0x00c0] DCU Address Register (DCUAR) */ + __IO uint32_t DCUDR; /*!< [0x00c4] DCU Data Register (DCUDR) */ + __IO uint32_t DCURR; /*!< [0x00c8] DCU Run Register (DCURR) */ + __IO uint32_t DCULR; /*!< [0x00cc] DCU Loop Register (DCULR) */ + __IO uint32_t DCUGCR; /*!< [0x00d0] DCU General Configuration Register (DCUGCR) */ + __IO uint32_t DCUTPR; /*!< [0x00d4] DCU Timing Parameter Register (DCUTPR) */ + __I uint32_t DCUSR0; /*!< [0x00d8] DCU Status Register 0 (DCUSR0) */ + __I uint32_t DCUSR1; /*!< [0x00dc] DCU Status Register 1 (DCUSR1) */ + __I uint32_t RESERVE1[8]; + __IO uint32_t BISTRR; /*!< [0x0100] BIST Run Register (BISTRR) */ + __IO uint32_t BISTWCR; /*!< [0x0104] BIST Word Count Register (BISTWCR) */ + __IO uint32_t BISTMSKR0; /*!< [0x0108] BIST Mask Register 0 (BISTMSKR0) */ + __IO uint32_t BISTMSKR1; /*!< [0x010c] BIST Mask Register 1 (BISTMSKR1) */ + __IO uint32_t BISTMSKR2; /*!< [0x0110] BIST Mask Register 2 (BISTMSKR2) */ + __IO uint32_t BISTLSR; /*!< [0x0114] BIST LFSR Seed Register (BISTLSR) */ + __IO uint32_t BISTAR0; /*!< [0x0118] BIST Address Register 0 (BISTAR0) */ + __IO uint32_t BISTAR1; /*!< [0x011c] BIST Address Register 1 (BISTAR1) */ + __IO uint32_t BISTAR2; /*!< [0x0120] BIST Address Register 2 (BISTAR2) */ + __IO uint32_t BISTUDPR; /*!< [0x0124] BIST User Data Pattern Register (BISTUDPR) */ + __I uint32_t BISTGSR; /*!< [0x0128] BIST General Status Register (BISTGSR) */ + __I uint32_t BISTWER; /*!< [0x012c] BIST Word Error Register (BISTWER) */ + __I uint32_t BISTBER0; /*!< [0x0130] BIST Bit Error Register 0 (BISTBER0) */ + __I uint32_t BISTBER1; /*!< [0x0134] BIST Bit Error Register 1 (BISTBER1) */ + __I uint32_t BISTBER2; /*!< [0x0138] BIST Bit Error Register 2 (BISTBER2) */ + __I uint32_t BISTBER3; /*!< [0x013c] BIST Bit Error Register 3 (BISTBER3) */ + __I uint32_t BISTWCSR; /*!< [0x0140] BIST Word Count Status Register (BISTWCSR) */ + __I uint32_t BISTFWR0; /*!< [0x0144] BIST Fail Word Register 0 (BISTFWR0) */ + __I uint32_t BISTFWR1; /*!< [0x0148] BIST Fail Word Register 1 (BISTFWR1) */ + __I uint32_t BISTFWR2; /*!< [0x014c] BIST Fail Word Register 2 (BISTFWR2) */ + __I uint32_t RESERVE2[9]; + __IO uint32_t AACR; /*!< [0x0174] Anti-Aging Control Register (AACR) */ + __IO uint32_t GPR0; /*!< [0x0178] General Purpose Register 0 (GPR0) */ + __IO uint32_t GPR1; /*!< [0x017c] General Purpose Register 1 (GPR1) */ + __IO uint32_t ZQ0CR0; /*!< [0x0180] Impedance Control Register 0 (ZQnCR0) */ + __IO uint32_t ZQ0CR1; /*!< [0x0184] Impedance Control Register 1 (ZQnCR1) */ + __I uint32_t ZQ0SR0; /*!< [0x0188] Impedance Status Register 0 (ZQnSR0) */ + __I uint32_t ZQ0SR1; /*!< [0x018c] Impedance Status Register 1 (ZQnSR1) */ + __IO uint32_t ZQ1CR0; /*!< [0x0190] Impedance Control Register 0 (ZQnCR0) */ + __IO uint32_t ZQ1CR1; /*!< [0x0194] Impedance Control Register 1 (ZQnCR1) */ + __I uint32_t ZQ1SR0; /*!< [0x0198] Impedance Status Register 0 (ZQnSR0) */ + __I uint32_t ZQ1SR1; /*!< [0x019c] Impedance Status Register 1 (ZQnSR1) */ + __IO uint32_t ZQ2CR0; /*!< [0x01a0] Impedance Control Register 0 (ZQnCR0) */ + __IO uint32_t ZQ2CR1; /*!< [0x01a4] Impedance Control Register 1 (ZQnCR1) */ + __I uint32_t ZQ2SR0; /*!< [0x01a8] Impedance Status Register 0 (ZQnSR0) */ + __I uint32_t ZQ2SR1; /*!< [0x01ac] Impedance Status Register 1 (ZQnSR1) */ + __IO uint32_t ZQ3CR0; /*!< [0x01b0] Impedance Control Register 0 (ZQnCR0) */ + __IO uint32_t ZQ3CR1; /*!< [0x01b4] Impedance Control Register 1 (ZQnCR1) */ + __I uint32_t ZQ3SR0; /*!< [0x01b8] Impedance Status Register 0 (ZQnSR0) */ + __I uint32_t ZQ3SR1; /*!< [0x01bc] Impedance Status Register 1 (ZQnSR1) */ + __IO uint32_t DX0GCR; /*!< [0x01c0] DATX8 General Configuration Register (DXnGCR) */ + __I uint32_t DX0GSR0; /*!< [0x01c4] DATX8 General Status Registers 0 (DXnGSR0) */ + __I uint32_t DX0GSR1; /*!< [0x01c8] DATX8 General Status Registers 1 (DXnGSR1) */ + __IO uint32_t DX0BDLR0; /*!< [0x01cc] DATX8 Bit Delay Line Register 0 (DXnBDLR0) */ + __IO uint32_t DX0BDLR1; /*!< [0x01d0] DATX8 Bit Delay Line Register 1 (DXnBDLR1) */ + __IO uint32_t DX0BDLR2; /*!< [0x01d4] DATX8 Bit Delay Line Register 2 (DXnBDLR2) */ + __IO uint32_t DX0BDLR3; /*!< [0x01d8] DATX8 Bit Delay Line Register 3 (DXnBDLR3) */ + __IO uint32_t DX0BDLR4; /*!< [0x01dc] DATX8 Bit Delay Line Register 4 (DXnBDLR4) */ + __IO uint32_t DX0LCDLR0; /*!< [0x01e0] DATX8 Bit Delay Line Register 0 (DXnBDLR0) */ + __IO uint32_t DX0LCDLR1; /*!< [0x01e4] DATX8 Bit Delay Line Register 1 (DXnBDLR1) */ + __IO uint32_t DX0LCDLR2; /*!< [0x01e8] DATX8 Bit Delay Line Register 2 (DXnBDLR2) */ + __IO uint32_t DX0MDLR; /*!< [0x01ec] DATX8 Master Delay Line Register (DXnMDLR) */ + __IO uint32_t DX0GTR; /*!< [0x01f0] DATX8 General Timing Register (DXnGTR) */ + __IO uint32_t DX0GSR2; /*!< [0x01f4] DATX8 General Status Register 2 (DXnGSR2) */ + __I uint32_t RESERVE3[2]; + __IO uint32_t DX1GCR; /*!< [0x0200] DATX8 General Configuration Register (DXnGCR) */ + __I uint32_t DX1GSR0; /*!< [0x0204] DATX8 General Status Registers 0 (DXnGSR0) */ + __I uint32_t DX1GSR1; /*!< [0x0208] DATX8 General Status Registers 1 (DXnGSR1) */ + __IO uint32_t DX1BDLR0; /*!< [0x020c] DATX8 Bit Delay Line Register 0 (DXnBDLR0) */ + __IO uint32_t DX1BDLR1; /*!< [0x0210] DATX8 Bit Delay Line Register 1 (DXnBDLR1) */ + __IO uint32_t DX1BDLR2; /*!< [0x0214] DATX8 Bit Delay Line Register 2 (DXnBDLR2) */ + __IO uint32_t DX1BDLR3; /*!< [0x0218] DATX8 Bit Delay Line Register 3 (DXnBDLR3) */ + __IO uint32_t DX1BDLR4; /*!< [0x021c] DATX8 Bit Delay Line Register 4 (DXnBDLR4) */ + __IO uint32_t DX1LCDLR0; /*!< [0x0220] DATX8 Bit Delay Line Register 0 (DXnBDLR0) */ + __IO uint32_t DX1LCDLR1; /*!< [0x0224] DATX8 Bit Delay Line Register 1 (DXnBDLR1) */ + __IO uint32_t DX1LCDLR2; /*!< [0x0228] DATX8 Bit Delay Line Register 2 (DXnBDLR2) */ + __IO uint32_t DX1MDLR; /*!< [0x022c] DATX8 Master Delay Line Register (DXnMDLR) */ + __IO uint32_t DX1GTR; /*!< [0x0230] DATX8 General Timing Register (DXnGTR) */ + __IO uint32_t DX1GSR2; /*!< [0x0234] DATX8 General Status Register 2 (DXnGSR2) */ + __I uint32_t RESERVE4[2]; + __IO uint32_t DX2GCR; /*!< [0x0240] DATX8 General Configuration Register (DXnGCR) */ + __I uint32_t DX2GSR0; /*!< [0x0244] DATX8 General Status Registers 0 (DXnGSR0) */ + __I uint32_t DX2GSR1; /*!< [0x0248] DATX8 General Status Registers 1 (DXnGSR1) */ + __IO uint32_t DX2BDLR0; /*!< [0x024c] DATX8 Bit Delay Line Register 0 (DXnBDLR0) */ + __IO uint32_t DX2BDLR1; /*!< [0x0250] DATX8 Bit Delay Line Register 1 (DXnBDLR1) */ + __IO uint32_t DX2BDLR2; /*!< [0x0254] DATX8 Bit Delay Line Register 2 (DXnBDLR2) */ + __IO uint32_t DX2BDLR3; /*!< [0x0258] DATX8 Bit Delay Line Register 3 (DXnBDLR3) */ + __IO uint32_t DX2BDLR4; /*!< [0x025c] DATX8 Bit Delay Line Register 4 (DXnBDLR4) */ + __IO uint32_t DX2LCDLR0; /*!< [0x0260] DATX8 Bit Delay Line Register 0 (DXnBDLR0) */ + __IO uint32_t DX2LCDLR1; /*!< [0x0264] DATX8 Bit Delay Line Register 1 (DXnBDLR1) */ + __IO uint32_t DX2LCDLR2; /*!< [0x0268] DATX8 Bit Delay Line Register 2 (DXnBDLR2) */ + __IO uint32_t DX2MDLR; /*!< [0x026c] DATX8 Master Delay Line Register (DXnMDLR) */ + __IO uint32_t DX2GTR; /*!< [0x0270] DATX8 General Timing Register (DXnGTR) */ + __IO uint32_t DX2GSR2; /*!< [0x0274] DATX8 General Status Register 2 (DXnGSR2) */ + __I uint32_t RESERVE5[2]; + __IO uint32_t DX3GCR; /*!< [0x0280] DATX8 General Configuration Register (DXnGCR) */ + __I uint32_t DX3GSR0; /*!< [0x0284] DATX8 General Status Registers 0 (DXnGSR0) */ + __I uint32_t DX3GSR1; /*!< [0x0288] DATX8 General Status Registers 1 (DXnGSR1) */ + __IO uint32_t DX3BDLR0; /*!< [0x028c] DATX8 Bit Delay Line Register 0 (DXnBDLR0) */ + __IO uint32_t DX3BDLR1; /*!< [0x0290] DATX8 Bit Delay Line Register 1 (DXnBDLR1) */ + __IO uint32_t DX3BDLR2; /*!< [0x0294] DATX8 Bit Delay Line Register 2 (DXnBDLR2) */ + __IO uint32_t DX3BDLR3; /*!< [0x0298] DATX8 Bit Delay Line Register 3 (DXnBDLR3) */ + __IO uint32_t DX3BDLR4; /*!< [0x029c] DATX8 Bit Delay Line Register 4 (DXnBDLR4) */ + __IO uint32_t DX3LCDLR0; /*!< [0x02a0] DATX8 Bit Delay Line Register 0 (DXnBDLR0) */ + __IO uint32_t DX3LCDLR1; /*!< [0x02a4] DATX8 Bit Delay Line Register 1 (DXnBDLR1) */ + __IO uint32_t DX3LCDLR2; /*!< [0x02a8] DATX8 Bit Delay Line Register 2 (DXnBDLR2) */ + __IO uint32_t DX3MDLR; /*!< [0x02ac] DATX8 Master Delay Line Register (DXnMDLR) */ + __IO uint32_t DX3GTR; /*!< [0x02b0] DATX8 General Timing Register (DXnGTR) */ + __IO uint32_t DX3GSR2; /*!< [0x02b4] DATX8 General Status Register 2 (DXnGSR2) */ + __I uint32_t RESERVE6[2]; + __IO uint32_t DX4GCR; /*!< [0x02c0] DATX8 General Configuration Register (DXnGCR) */ + __I uint32_t DX4GSR0; /*!< [0x02c4] DATX8 General Status Registers 0 (DXnGSR0) */ + __I uint32_t DX4GSR1; /*!< [0x02c8] DATX8 General Status Registers 1 (DXnGSR1) */ + __IO uint32_t DX4BDLR0; /*!< [0x02cc] DATX8 Bit Delay Line Register 0 (DXnBDLR0) */ + __IO uint32_t DX4BDLR1; /*!< [0x02d0] DATX8 Bit Delay Line Register 1 (DXnBDLR1) */ + __IO uint32_t DX4BDLR2; /*!< [0x02d4] DATX8 Bit Delay Line Register 2 (DXnBDLR2) */ + __IO uint32_t DX4BDLR3; /*!< [0x02d8] DATX8 Bit Delay Line Register 3 (DXnBDLR3) */ + __IO uint32_t DX4BDLR4; /*!< [0x02dc] DATX8 Bit Delay Line Register 4 (DXnBDLR4) */ + __IO uint32_t DX4LCDLR0; /*!< [0x02e0] DATX8 Bit Delay Line Register 0 (DXnBDLR0) */ + __IO uint32_t DX4LCDLR1; /*!< [0x02e4] DATX8 Bit Delay Line Register 1 (DXnBDLR1) */ + __IO uint32_t DX4LCDLR2; /*!< [0x02e8] DATX8 Bit Delay Line Register 2 (DXnBDLR2) */ + __IO uint32_t DX4MDLR; /*!< [0x02ec] DATX8 Master Delay Line Register (DXnMDLR) */ + __IO uint32_t DX4GTR; /*!< [0x02f0] DATX8 General Timing Register (DXnGTR) */ + __IO uint32_t DX4GSR2; /*!< [0x02f4] DATX8 General Status Register 2 (DXnGSR2) */ + __I uint32_t RESERVE7[2]; + __IO uint32_t DX5GCR; /*!< [0x0300] DATX8 General Configuration Register (DXnGCR) */ + __I uint32_t DX5GSR0; /*!< [0x0304] DATX8 General Status Registers 0 (DXnGSR0) */ + __I uint32_t DX5GSR1; /*!< [0x0308] DATX8 General Status Registers 1 (DXnGSR1) */ + __IO uint32_t DX5BDLR0; /*!< [0x030c] DATX8 Bit Delay Line Register 0 (DXnBDLR0) */ + __IO uint32_t DX5BDLR1; /*!< [0x0310] DATX8 Bit Delay Line Register 1 (DXnBDLR1) */ + __IO uint32_t DX5BDLR2; /*!< [0x0314] DATX8 Bit Delay Line Register 2 (DXnBDLR2) */ + __IO uint32_t DX5BDLR3; /*!< [0x0318] DATX8 Bit Delay Line Register 3 (DXnBDLR3) */ + __IO uint32_t DX5BDLR4; /*!< [0x031c] DATX8 Bit Delay Line Register 4 (DXnBDLR4) */ + __IO uint32_t DX5LCDLR0; /*!< [0x0320] DATX8 Bit Delay Line Register 0 (DXnBDLR0) */ + __IO uint32_t DX5LCDLR1; /*!< [0x0324] DATX8 Bit Delay Line Register 1 (DXnBDLR1) */ + __IO uint32_t DX5LCDLR2; /*!< [0x0328] DATX8 Bit Delay Line Register 2 (DXnBDLR2) */ + __IO uint32_t DX5MDLR; /*!< [0x032c] DATX8 Master Delay Line Register (DXnMDLR) */ + __IO uint32_t DX5GTR; /*!< [0x0330] DATX8 General Timing Register (DXnGTR) */ + __IO uint32_t DX5GSR2; /*!< [0x0334] DATX8 General Status Register 2 (DXnGSR2) */ + __I uint32_t RESERVE8[2]; + __IO uint32_t DX6GCR; /*!< [0x0340] DATX8 General Configuration Register (DXnGCR) */ + __I uint32_t DX6GSR0; /*!< [0x0344] DATX8 General Status Registers 0 (DXnGSR0) */ + __I uint32_t DX6GSR1; /*!< [0x0348] DATX8 General Status Registers 1 (DXnGSR1) */ + __IO uint32_t DX6BDLR0; /*!< [0x034c] DATX8 Bit Delay Line Register 0 (DXnBDLR0) */ + __IO uint32_t DX6BDLR1; /*!< [0x0350] DATX8 Bit Delay Line Register 1 (DXnBDLR1) */ + __IO uint32_t DX6BDLR2; /*!< [0x0354] DATX8 Bit Delay Line Register 2 (DXnBDLR2) */ + __IO uint32_t DX6BDLR3; /*!< [0x0358] DATX8 Bit Delay Line Register 3 (DXnBDLR3) */ + __IO uint32_t DX6BDLR4; /*!< [0x035c] DATX8 Bit Delay Line Register 4 (DXnBDLR4) */ + __IO uint32_t DX6LCDLR0; /*!< [0x0360] DATX8 Bit Delay Line Register 0 (DXnBDLR0) */ + __IO uint32_t DX6LCDLR1; /*!< [0x0364] DATX8 Bit Delay Line Register 1 (DXnBDLR1) */ + __IO uint32_t DX6LCDLR2; /*!< [0x0368] DATX8 Bit Delay Line Register 2 (DXnBDLR2) */ + __IO uint32_t DX6MDLR; /*!< [0x036c] DATX8 Master Delay Line Register (DXnMDLR) */ + __IO uint32_t DX6GTR; /*!< [0x0370] DATX8 General Timing Register (DXnGTR) */ + __IO uint32_t DX6GSR2; /*!< [0x0374] DATX8 General Status Register 2 (DXnGSR2) */ + __I uint32_t RESERVE9[2]; + __IO uint32_t DX7GCR; /*!< [0x0380] DATX8 General Configuration Register (DXnGCR) */ + __I uint32_t DX7GSR0; /*!< [0x0384] DATX8 General Status Registers 0 (DXnGSR0) */ + __I uint32_t DX7GSR1; /*!< [0x0388] DATX8 General Status Registers 1 (DXnGSR1) */ + __IO uint32_t DX7BDLR0; /*!< [0x038c] DATX8 Bit Delay Line Register 0 (DXnBDLR0) */ + __IO uint32_t DX7BDLR1; /*!< [0x0390] DATX8 Bit Delay Line Register 1 (DXnBDLR1) */ + __IO uint32_t DX7BDLR2; /*!< [0x0394] DATX8 Bit Delay Line Register 2 (DXnBDLR2) */ + __IO uint32_t DX7BDLR3; /*!< [0x0398] DATX8 Bit Delay Line Register 3 (DXnBDLR3) */ + __IO uint32_t DX7BDLR4; /*!< [0x039c] DATX8 Bit Delay Line Register 4 (DXnBDLR4) */ + __IO uint32_t DX7LCDLR0; /*!< [0x03a0] DATX8 Bit Delay Line Register 0 (DXnBDLR0) */ + __IO uint32_t DX7LCDLR1; /*!< [0x03a4] DATX8 Bit Delay Line Register 1 (DXnBDLR1) */ + __IO uint32_t DX7LCDLR2; /*!< [0x03a8] DATX8 Bit Delay Line Register 2 (DXnBDLR2) */ + __IO uint32_t DX7MDLR; /*!< [0x03ac] DATX8 Master Delay Line Register (DXnMDLR) */ + __IO uint32_t DX7GTR; /*!< [0x03b0] DATX8 General Timing Register (DXnGTR) */ + __IO uint32_t DX7GSR2; /*!< [0x03b4] DATX8 General Status Register 2 (DXnGSR2) */ + __I uint32_t RESERVE10[2]; + __IO uint32_t DX8GCR; /*!< [0x03c0] DATX8 General Configuration Register (DXnGCR) */ + __I uint32_t DX8GSR0; /*!< [0x03c4] DATX8 General Status Registers 0 (DXnGSR0) */ + __I uint32_t DX8GSR1; /*!< [0x03c8] DATX8 General Status Registers 1 (DXnGSR1) */ + __IO uint32_t DX8BDLR0; /*!< [0x03cc] DATX8 Bit Delay Line Register 0 (DXnBDLR0) */ + __IO uint32_t DX8BDLR1; /*!< [0x03d0] DATX8 Bit Delay Line Register 1 (DXnBDLR1) */ + __IO uint32_t DX8BDLR2; /*!< [0x03d4] DATX8 Bit Delay Line Register 2 (DXnBDLR2) */ + __IO uint32_t DX8BDLR3; /*!< [0x03d8] DATX8 Bit Delay Line Register 3 (DXnBDLR3) */ + __IO uint32_t DX8BDLR4; /*!< [0x03dc] DATX8 Bit Delay Line Register 4 (DXnBDLR4) */ + __IO uint32_t DX8LCDLR0; /*!< [0x03e0] DATX8 Bit Delay Line Register 0 (DXnBDLR0) */ + __IO uint32_t DX8LCDLR1; /*!< [0x03e4] DATX8 Bit Delay Line Register 1 (DXnBDLR1) */ + __IO uint32_t DX8LCDLR2; /*!< [0x03e8] DATX8 Bit Delay Line Register 2 (DXnBDLR2) */ + __IO uint32_t DX8MDLR; /*!< [0x03ec] DATX8 Master Delay Line Register (DXnMDLR) */ + __IO uint32_t DX8GTR; /*!< [0x03f0] DATX8 General Timing Register (DXnGTR) */ + __IO uint32_t DX8GSR2; /*!< [0x03f4] DATX8 General Status Register 2 (DXnGSR2) */ + +} DDRPHY_T; + +/** + @addtogroup DDRPHY_CONST DDRPHY Bit Field Definition + Constant Definitions for DDRPHY Controller +@{ */ + +#define DDRPHY_RIDR_PUBMNR_Pos (0) /*!< DDRPHY_T::RIDR: PUBMNR Position */ +#define DDRPHY_RIDR_PUBMNR_Msk (0xful << DDRPHY_RIDR_PUBMNR_Pos) /*!< DDRPHY_T::RIDR: PUBMNR Mask */ + +#define DDRPHY_RIDR_PUBMDR_Pos (4) /*!< DDRPHY_T::RIDR: PUBMDR Position */ +#define DDRPHY_RIDR_PUBMDR_Msk (0xful << DDRPHY_RIDR_PUBMDR_Pos) /*!< DDRPHY_T::RIDR: PUBMDR Mask */ + +#define DDRPHY_RIDR_PUBMJR_Pos (8) /*!< DDRPHY_T::RIDR: PUBMJR Position */ +#define DDRPHY_RIDR_PUBMJR_Msk (0xful << DDRPHY_RIDR_PUBMJR_Pos) /*!< DDRPHY_T::RIDR: PUBMJR Mask */ + +#define DDRPHY_RIDR_PHYMNR_Pos (12) /*!< DDRPHY_T::RIDR: PHYMNR Position */ +#define DDRPHY_RIDR_PHYMNR_Msk (0xful << DDRPHY_RIDR_PHYMNR_Pos) /*!< DDRPHY_T::RIDR: PHYMNR Mask */ + +#define DDRPHY_RIDR_PHYMDR_Pos (16) /*!< DDRPHY_T::RIDR: PHYMDR Position */ +#define DDRPHY_RIDR_PHYMDR_Msk (0xful << DDRPHY_RIDR_PHYMDR_Pos) /*!< DDRPHY_T::RIDR: PHYMDR Mask */ + +#define DDRPHY_RIDR_PHYMJR_Pos (20) /*!< DDRPHY_T::RIDR: PHYMJR Position */ +#define DDRPHY_RIDR_PHYMJR_Msk (0xful << DDRPHY_RIDR_PHYMJR_Pos) /*!< DDRPHY_T::RIDR: PHYMJR Mask */ + +#define DDRPHY_RIDR_UDRID_Pos (24) /*!< DDRPHY_T::RIDR: UDRID Position */ +#define DDRPHY_RIDR_UDRID_Msk (0xfful << DDRPHY_RIDR_UDRID_Pos) /*!< DDRPHY_T::RIDR: UDRID Mask */ + +#define DDRPHY_PIR_INIT_Pos (0) /*!< DDRPHY_T::PIR: INIT Position */ +#define DDRPHY_PIR_INIT_Msk (0x1ul << DDRPHY_PIR_INIT_Pos) /*!< DDRPHY_T::PIR: INIT Mask */ + +#define DDRPHY_PIR_ZCAL_Pos (1) /*!< DDRPHY_T::PIR: ZCAL Position */ +#define DDRPHY_PIR_ZCAL_Msk (0x1ul << DDRPHY_PIR_ZCAL_Pos) /*!< DDRPHY_T::PIR: ZCAL Mask */ + +#define DDRPHY_PIR_PLLINIT_Pos (4) /*!< DDRPHY_T::PIR: PLLINIT Position */ +#define DDRPHY_PIR_PLLINIT_Msk (0x1ul << DDRPHY_PIR_PLLINIT_Pos) /*!< DDRPHY_T::PIR: PLLINIT Mask */ + +#define DDRPHY_PIR_DCAL_Pos (5) /*!< DDRPHY_T::PIR: DCAL Position */ +#define DDRPHY_PIR_DCAL_Msk (0x1ul << DDRPHY_PIR_DCAL_Pos) /*!< DDRPHY_T::PIR: DCAL Mask */ + +#define DDRPHY_PIR_PHYRST_Pos (6) /*!< DDRPHY_T::PIR: PHYRST Position */ +#define DDRPHY_PIR_PHYRST_Msk (0x1ul << DDRPHY_PIR_PHYRST_Pos) /*!< DDRPHY_T::PIR: PHYRST Mask */ + +#define DDRPHY_PIR_DRAMRST_Pos (7) /*!< DDRPHY_T::PIR: DRAMRST Position */ +#define DDRPHY_PIR_DRAMRST_Msk (0x1ul << DDRPHY_PIR_DRAMRST_Pos) /*!< DDRPHY_T::PIR: DRAMRST Mask */ + +#define DDRPHY_PIR_DRAMINIT_Pos (8) /*!< DDRPHY_T::PIR: DRAMINIT Position */ +#define DDRPHY_PIR_DRAMINIT_Msk (0x1ul << DDRPHY_PIR_DRAMINIT_Pos) /*!< DDRPHY_T::PIR: DRAMINIT Mask */ + +#define DDRPHY_PIR_WL_Pos (9) /*!< DDRPHY_T::PIR: WL Position */ +#define DDRPHY_PIR_WL_Msk (0x1ul << DDRPHY_PIR_WL_Pos) /*!< DDRPHY_T::PIR: WL Mask */ + +#define DDRPHY_PIR_QSGATE_Pos (10) /*!< DDRPHY_T::PIR: QSGATE Position */ +#define DDRPHY_PIR_QSGATE_Msk (0x1ul << DDRPHY_PIR_QSGATE_Pos) /*!< DDRPHY_T::PIR: QSGATE Mask */ + +#define DDRPHY_PIR_WLADJ_Pos (11) /*!< DDRPHY_T::PIR: WLADJ Position */ +#define DDRPHY_PIR_WLADJ_Msk (0x1ul << DDRPHY_PIR_WLADJ_Pos) /*!< DDRPHY_T::PIR: WLADJ Mask */ + +#define DDRPHY_PIR_RDDSKW_Pos (12) /*!< DDRPHY_T::PIR: RDDSKW Position */ +#define DDRPHY_PIR_RDDSKW_Msk (0x1ul << DDRPHY_PIR_RDDSKW_Pos) /*!< DDRPHY_T::PIR: RDDSKW Mask */ + +#define DDRPHY_PIR_WRDSKW_Pos (13) /*!< DDRPHY_T::PIR: WRDSKW Position */ +#define DDRPHY_PIR_WRDSKW_Msk (0x1ul << DDRPHY_PIR_WRDSKW_Pos) /*!< DDRPHY_T::PIR: WRDSKW Mask */ + +#define DDRPHY_PIR_RDEYE_Pos (14) /*!< DDRPHY_T::PIR: RDEYE Position */ +#define DDRPHY_PIR_RDEYE_Msk (0x1ul << DDRPHY_PIR_RDEYE_Pos) /*!< DDRPHY_T::PIR: RDEYE Mask */ + +#define DDRPHY_PIR_WREYE_Pos (15) /*!< DDRPHY_T::PIR: WREYE Position */ +#define DDRPHY_PIR_WREYE_Msk (0x1ul << DDRPHY_PIR_WREYE_Pos) /*!< DDRPHY_T::PIR: WREYE Mask */ + +#define DDRPHY_PIR_ICPC_Pos (16) /*!< DDRPHY_T::PIR: ICPC Position */ +#define DDRPHY_PIR_ICPC_Msk (0x1ul << DDRPHY_PIR_ICPC_Pos) /*!< DDRPHY_T::PIR: ICPC Mask */ + +#define DDRPHY_PIR_PLLBYP_Pos (17) /*!< DDRPHY_T::PIR: PLLBYP Position */ +#define DDRPHY_PIR_PLLBYP_Msk (0x1ul << DDRPHY_PIR_PLLBYP_Pos) /*!< DDRPHY_T::PIR: PLLBYP Mask */ + +#define DDRPHY_PIR_CTLDINIT_Pos (18) /*!< DDRPHY_T::PIR: CTLDINIT Position */ +#define DDRPHY_PIR_CTLDINIT_Msk (0x1ul << DDRPHY_PIR_CTLDINIT_Pos) /*!< DDRPHY_T::PIR: CTLDINIT Mask */ + +#define DDRPHY_PIR_RDIMMINIT_Pos (19) /*!< DDRPHY_T::PIR: RDIMMINIT Position */ +#define DDRPHY_PIR_RDIMMINIT_Msk (0x1ul << DDRPHY_PIR_RDIMMINIT_Pos) /*!< DDRPHY_T::PIR: RDIMMINIT Mask */ + +#define DDRPHY_PIR_CLRSR_Pos (27) /*!< DDRPHY_T::PIR: CLRSR Position */ +#define DDRPHY_PIR_CLRSR_Msk (0x1ul << DDRPHY_PIR_CLRSR_Pos) /*!< DDRPHY_T::PIR: CLRSR Mask */ + +#define DDRPHY_PIR_LOCKBYP_Pos (28) /*!< DDRPHY_T::PIR: LOCKBYP Position */ +#define DDRPHY_PIR_LOCKBYP_Msk (0x1ul << DDRPHY_PIR_LOCKBYP_Pos) /*!< DDRPHY_T::PIR: LOCKBYP Mask */ + +#define DDRPHY_PIR_DCALBYP_Pos (29) /*!< DDRPHY_T::PIR: DCALBYP Position */ +#define DDRPHY_PIR_DCALBYP_Msk (0x1ul << DDRPHY_PIR_DCALBYP_Pos) /*!< DDRPHY_T::PIR: DCALBYP Mask */ + +#define DDRPHY_PIR_ZCALBYP_Pos (30) /*!< DDRPHY_T::PIR: ZCALBYP Position */ +#define DDRPHY_PIR_ZCALBYP_Msk (0x1ul << DDRPHY_PIR_ZCALBYP_Pos) /*!< DDRPHY_T::PIR: ZCALBYP Mask */ + +#define DDRPHY_PIR_INITBYP_Pos (31) /*!< DDRPHY_T::PIR: INITBYP Position */ +#define DDRPHY_PIR_INITBYP_Msk (0x1ul << DDRPHY_PIR_INITBYP_Pos) /*!< DDRPHY_T::PIR: INITBYP Mask */ + +#define DDRPHY_PGCR0_WLLVT_Pos (0) /*!< DDRPHY_T::PGCR0: WLLVT Position */ +#define DDRPHY_PGCR0_WLLVT_Msk (0x1ul << DDRPHY_PGCR0_WLLVT_Pos) /*!< DDRPHY_T::PGCR0: WLLVT Mask */ + +#define DDRPHY_PGCR0_WDLVT_Pos (1) /*!< DDRPHY_T::PGCR0: WDLVT Position */ +#define DDRPHY_PGCR0_WDLVT_Msk (0x1ul << DDRPHY_PGCR0_WDLVT_Pos) /*!< DDRPHY_T::PGCR0: WDLVT Mask */ + +#define DDRPHY_PGCR0_RDLVT_Pos (2) /*!< DDRPHY_T::PGCR0: RDLVT Position */ +#define DDRPHY_PGCR0_RDLVT_Msk (0x1ul << DDRPHY_PGCR0_RDLVT_Pos) /*!< DDRPHY_T::PGCR0: RDLVT Mask */ + +#define DDRPHY_PGCR0_RGLVT_Pos (3) /*!< DDRPHY_T::PGCR0: RGLVT Position */ +#define DDRPHY_PGCR0_RGLVT_Msk (0x1ul << DDRPHY_PGCR0_RGLVT_Pos) /*!< DDRPHY_T::PGCR0: RGLVT Mask */ + +#define DDRPHY_PGCR0_WDBVT_Pos (4) /*!< DDRPHY_T::PGCR0: WDBVT Position */ +#define DDRPHY_PGCR0_WDBVT_Msk (0x1ul << DDRPHY_PGCR0_WDBVT_Pos) /*!< DDRPHY_T::PGCR0: WDBVT Mask */ + +#define DDRPHY_PGCR0_RDBVT_Pos (5) /*!< DDRPHY_T::PGCR0: RDBVT Position */ +#define DDRPHY_PGCR0_RDBVT_Msk (0x1ul << DDRPHY_PGCR0_RDBVT_Pos) /*!< DDRPHY_T::PGCR0: RDBVT Mask */ + +#define DDRPHY_PGCR0_DLTMODE_Pos (6) /*!< DDRPHY_T::PGCR0: DLTMODE Position */ +#define DDRPHY_PGCR0_DLTMODE_Msk (0x1ul << DDRPHY_PGCR0_DLTMODE_Pos) /*!< DDRPHY_T::PGCR0: DLTMODE Mask */ + +#define DDRPHY_PGCR0_DLTST_Pos (7) /*!< DDRPHY_T::PGCR0: DLTST Position */ +#define DDRPHY_PGCR0_DLTST_Msk (0x1ul << DDRPHY_PGCR0_DLTST_Pos) /*!< DDRPHY_T::PGCR0: DLTST Mask */ + +#define DDRPHY_PGCR0_OSCEN_Pos (8) /*!< DDRPHY_T::PGCR0: OSCEN Position */ +#define DDRPHY_PGCR0_OSCEN_Msk (0x1ul << DDRPHY_PGCR0_OSCEN_Pos) /*!< DDRPHY_T::PGCR0: OSCEN Mask */ + +#define DDRPHY_PGCR0_OSCDIV_Pos (9) /*!< DDRPHY_T::PGCR0: OSCDIV Position */ +#define DDRPHY_PGCR0_OSCDIV_Msk (0x7ul << DDRPHY_PGCR0_OSCDIV_Pos) /*!< DDRPHY_T::PGCR0: OSCDIV Mask */ + +#define DDRPHY_PGCR0_OSCWDL_Pos (12) /*!< DDRPHY_T::PGCR0: OSCWDL Position */ +#define DDRPHY_PGCR0_OSCWDL_Msk (0x3ul << DDRPHY_PGCR0_OSCWDL_Pos) /*!< DDRPHY_T::PGCR0: OSCWDL Mask */ + +#define DDRPHY_PGCR0_DTOSEL_Pos (14) /*!< DDRPHY_T::PGCR0: DTOSEL Position */ +#define DDRPHY_PGCR0_DTOSEL_Msk (0x1ful << DDRPHY_PGCR0_DTOSEL_Pos) /*!< DDRPHY_T::PGCR0: DTOSEL Mask */ + +#define DDRPHY_PGCR0_PUBMODE_Pos (25) /*!< DDRPHY_T::PGCR0: PUBMODE Position */ +#define DDRPHY_PGCR0_PUBMODE_Msk (0x1ul << DDRPHY_PGCR0_PUBMODE_Pos) /*!< DDRPHY_T::PGCR0: PUBMODE Mask */ + +#define DDRPHY_PGCR0_CKEN_Pos (26) /*!< DDRPHY_T::PGCR0: CKEN Position */ +#define DDRPHY_PGCR0_CKEN_Msk (0x3ful << DDRPHY_PGCR0_CKEN_Pos) /*!< DDRPHY_T::PGCR0: CKEN Mask */ + +#define DDRPHY_PGCR1_PDDISDX_Pos (0) /*!< DDRPHY_T::PGCR1: PDDISDX Position */ +#define DDRPHY_PGCR1_PDDISDX_Msk (0x1ul << DDRPHY_PGCR1_PDDISDX_Pos) /*!< DDRPHY_T::PGCR1: PDDISDX Mask */ + +#define DDRPHY_PGCR1_WLMODE_Pos (1) /*!< DDRPHY_T::PGCR1: WLMODE Position */ +#define DDRPHY_PGCR1_WLMODE_Msk (0x1ul << DDRPHY_PGCR1_WLMODE_Pos) /*!< DDRPHY_T::PGCR1: WLMODE Mask */ + +#define DDRPHY_PGCR1_WLSTEP_Pos (2) /*!< DDRPHY_T::PGCR1: WLSTEP Position */ +#define DDRPHY_PGCR1_WLSTEP_Msk (0x1ul << DDRPHY_PGCR1_WLSTEP_Pos) /*!< DDRPHY_T::PGCR1: WLSTEP Mask */ + +#define DDRPHY_PGCR1_WSLOPT_Pos (4) /*!< DDRPHY_T::PGCR1: WSLOPT Position */ +#define DDRPHY_PGCR1_WSLOPT_Msk (0x1ul << DDRPHY_PGCR1_WSLOPT_Pos) /*!< DDRPHY_T::PGCR1: WSLOPT Mask */ + +#define DDRPHY_PGCR1_ACHRST_Pos (5) /*!< DDRPHY_T::PGCR1: ACHRST Position */ +#define DDRPHY_PGCR1_ACHRST_Msk (0x1ul << DDRPHY_PGCR1_ACHRST_Pos) /*!< DDRPHY_T::PGCR1: ACHRST Mask */ + +#define DDRPHY_PGCR1_WLSELT_Pos (6) /*!< DDRPHY_T::PGCR1: WLSELT Position */ +#define DDRPHY_PGCR1_WLSELT_Msk (0x1ul << DDRPHY_PGCR1_WLSELT_Pos) /*!< DDRPHY_T::PGCR1: WLSELT Mask */ + +#define DDRPHY_PGCR1_IODDRM_Pos (7) /*!< DDRPHY_T::PGCR1: IODDRM Position */ +#define DDRPHY_PGCR1_IODDRM_Msk (0x3ul << DDRPHY_PGCR1_IODDRM_Pos) /*!< DDRPHY_T::PGCR1: IODDRM Mask */ + +#define DDRPHY_PGCR1_MDLEN_Pos (9) /*!< DDRPHY_T::PGCR1: MDLEN Position */ +#define DDRPHY_PGCR1_MDLEN_Msk (0x1ul << DDRPHY_PGCR1_MDLEN_Pos) /*!< DDRPHY_T::PGCR1: MDLEN Mask */ + +#define DDRPHY_PGCR1_LPFEN_Pos (10) /*!< DDRPHY_T::PGCR1: LPFEN Position */ +#define DDRPHY_PGCR1_LPFEN_Msk (0x1ul << DDRPHY_PGCR1_LPFEN_Pos) /*!< DDRPHY_T::PGCR1: LPFEN Mask */ + +#define DDRPHY_PGCR1_LPFDEPTH_Pos (11) /*!< DDRPHY_T::PGCR1: LPFDEPTH Position */ +#define DDRPHY_PGCR1_LPFDEPTH_Msk (0x3ul << DDRPHY_PGCR1_LPFDEPTH_Pos) /*!< DDRPHY_T::PGCR1: LPFDEPTH Mask */ + +#define DDRPHY_PGCR1_FDEPTH_Pos (13) /*!< DDRPHY_T::PGCR1: FDEPTH Position */ +#define DDRPHY_PGCR1_FDEPTH_Msk (0x3ul << DDRPHY_PGCR1_FDEPTH_Pos) /*!< DDRPHY_T::PGCR1: FDEPTH Mask */ + +#define DDRPHY_PGCR1_DLDLMT_Pos (15) /*!< DDRPHY_T::PGCR1: DLDLMT Position */ +#define DDRPHY_PGCR1_DLDLMT_Msk (0xfful << DDRPHY_PGCR1_DLDLMT_Pos) /*!< DDRPHY_T::PGCR1: DLDLMT Mask */ + +#define DDRPHY_PGCR1_ZCKSEL_Pos (23) /*!< DDRPHY_T::PGCR1: ZCKSEL Position */ +#define DDRPHY_PGCR1_ZCKSEL_Msk (0x3ul << DDRPHY_PGCR1_ZCKSEL_Pos) /*!< DDRPHY_T::PGCR1: ZCKSEL Mask */ + +#define DDRPHY_PGCR1_DXHRST_Pos (25) /*!< DDRPHY_T::PGCR1: DXHRST Position */ +#define DDRPHY_PGCR1_DXHRST_Msk (0x1ul << DDRPHY_PGCR1_DXHRST_Pos) /*!< DDRPHY_T::PGCR1: DXHRST Mask */ + +#define DDRPHY_PGCR1_INHVT_Pos (26) /*!< DDRPHY_T::PGCR1: INHVT Position */ +#define DDRPHY_PGCR1_INHVT_Msk (0x1ul << DDRPHY_PGCR1_INHVT_Pos) /*!< DDRPHY_T::PGCR1: INHVT Mask */ + +#define DDRPHY_PGCR1_IOLB_Pos (27) /*!< DDRPHY_T::PGCR1: IOLB Position */ +#define DDRPHY_PGCR1_IOLB_Msk (0x1ul << DDRPHY_PGCR1_IOLB_Pos) /*!< DDRPHY_T::PGCR1: IOLB Mask */ + +#define DDRPHY_PGCR1_LBDQSS_Pos (28) /*!< DDRPHY_T::PGCR1: LBDQSS Position */ +#define DDRPHY_PGCR1_LBDQSS_Msk (0x1ul << DDRPHY_PGCR1_LBDQSS_Pos) /*!< DDRPHY_T::PGCR1: LBDQSS Mask */ + +#define DDRPHY_PGCR1_LBGDQS_Pos (29) /*!< DDRPHY_T::PGCR1: LBGDQS Position */ +#define DDRPHY_PGCR1_LBGDQS_Msk (0x3ul << DDRPHY_PGCR1_LBGDQS_Pos) /*!< DDRPHY_T::PGCR1: LBGDQS Mask */ + +#define DDRPHY_PGCR1_LBMODE_Pos (31) /*!< DDRPHY_T::PGCR1: LBMODE Position */ +#define DDRPHY_PGCR1_LBMODE_Msk (0x1ul << DDRPHY_PGCR1_LBMODE_Pos) /*!< DDRPHY_T::PGCR1: LBMODE Mask */ + +#define DDRPHY_PGSR0_IDONE_Pos (0) /*!< DDRPHY_T::PGSR0: IDONE Position */ +#define DDRPHY_PGSR0_IDONE_Msk (0x1ul << DDRPHY_PGSR0_IDONE_Pos) /*!< DDRPHY_T::PGSR0: IDONE Mask */ + +#define DDRPHY_PGSR0_PLDONE_Pos (1) /*!< DDRPHY_T::PGSR0: PLDONE Position */ +#define DDRPHY_PGSR0_PLDONE_Msk (0x1ul << DDRPHY_PGSR0_PLDONE_Pos) /*!< DDRPHY_T::PGSR0: PLDONE Mask */ + +#define DDRPHY_PGSR0_DCDONE_Pos (2) /*!< DDRPHY_T::PGSR0: DCDONE Position */ +#define DDRPHY_PGSR0_DCDONE_Msk (0x1ul << DDRPHY_PGSR0_DCDONE_Pos) /*!< DDRPHY_T::PGSR0: DCDONE Mask */ + +#define DDRPHY_PGSR0_ZCDONE_Pos (3) /*!< DDRPHY_T::PGSR0: ZCDONE Position */ +#define DDRPHY_PGSR0_ZCDONE_Msk (0x1ul << DDRPHY_PGSR0_ZCDONE_Pos) /*!< DDRPHY_T::PGSR0: ZCDONE Mask */ + +#define DDRPHY_PGSR0_DIDONE_Pos (4) /*!< DDRPHY_T::PGSR0: DIDONE Position */ +#define DDRPHY_PGSR0_DIDONE_Msk (0x1ul << DDRPHY_PGSR0_DIDONE_Pos) /*!< DDRPHY_T::PGSR0: DIDONE Mask */ + +#define DDRPHY_PGSR0_WLDONE_Pos (5) /*!< DDRPHY_T::PGSR0: WLDONE Position */ +#define DDRPHY_PGSR0_WLDONE_Msk (0x1ul << DDRPHY_PGSR0_WLDONE_Pos) /*!< DDRPHY_T::PGSR0: WLDONE Mask */ + +#define DDRPHY_PGSR0_QSGDONE_Pos (6) /*!< DDRPHY_T::PGSR0: QSGDONE Position */ +#define DDRPHY_PGSR0_QSGDONE_Msk (0x1ul << DDRPHY_PGSR0_QSGDONE_Pos) /*!< DDRPHY_T::PGSR0: QSGDONE Mask */ + +#define DDRPHY_PGSR0_WLADONE_Pos (7) /*!< DDRPHY_T::PGSR0: WLADONE Position */ +#define DDRPHY_PGSR0_WLADONE_Msk (0x1ul << DDRPHY_PGSR0_WLADONE_Pos) /*!< DDRPHY_T::PGSR0: WLADONE Mask */ + +#define DDRPHY_PGSR0_RDDONE_Pos (8) /*!< DDRPHY_T::PGSR0: RDDONE Position */ +#define DDRPHY_PGSR0_RDDONE_Msk (0x1ul << DDRPHY_PGSR0_RDDONE_Pos) /*!< DDRPHY_T::PGSR0: RDDONE Mask */ + +#define DDRPHY_PGSR0_WDDONE_Pos (9) /*!< DDRPHY_T::PGSR0: WDDONE Position */ +#define DDRPHY_PGSR0_WDDONE_Msk (0x1ul << DDRPHY_PGSR0_WDDONE_Pos) /*!< DDRPHY_T::PGSR0: WDDONE Mask */ + +#define DDRPHY_PGSR0_REDONE_Pos (10) /*!< DDRPHY_T::PGSR0: REDONE Position */ +#define DDRPHY_PGSR0_REDONE_Msk (0x1ul << DDRPHY_PGSR0_REDONE_Pos) /*!< DDRPHY_T::PGSR0: REDONE Mask */ + +#define DDRPHY_PGSR0_WEDONE_Pos (11) /*!< DDRPHY_T::PGSR0: WEDONE Position */ +#define DDRPHY_PGSR0_WEDONE_Msk (0x1ul << DDRPHY_PGSR0_WEDONE_Pos) /*!< DDRPHY_T::PGSR0: WEDONE Mask */ + +#define DDRPHY_PGSR0_ZCERR_Pos (20) /*!< DDRPHY_T::PGSR0: ZCERR Position */ +#define DDRPHY_PGSR0_ZCERR_Msk (0x1ul << DDRPHY_PGSR0_ZCERR_Pos) /*!< DDRPHY_T::PGSR0: ZCERR Mask */ + +#define DDRPHY_PGSR0_WLERR_Pos (21) /*!< DDRPHY_T::PGSR0: WLERR Position */ +#define DDRPHY_PGSR0_WLERR_Msk (0x1ul << DDRPHY_PGSR0_WLERR_Pos) /*!< DDRPHY_T::PGSR0: WLERR Mask */ + +#define DDRPHY_PGSR0_QSGERR_Pos (22) /*!< DDRPHY_T::PGSR0: QSGERR Position */ +#define DDRPHY_PGSR0_QSGERR_Msk (0x1ul << DDRPHY_PGSR0_QSGERR_Pos) /*!< DDRPHY_T::PGSR0: QSGERR Mask */ + +#define DDRPHY_PGSR0_WLAERR_Pos (23) /*!< DDRPHY_T::PGSR0: WLAERR Position */ +#define DDRPHY_PGSR0_WLAERR_Msk (0x1ul << DDRPHY_PGSR0_WLAERR_Pos) /*!< DDRPHY_T::PGSR0: WLAERR Mask */ + +#define DDRPHY_PGSR0_RDERR_Pos (24) /*!< DDRPHY_T::PGSR0: RDERR Position */ +#define DDRPHY_PGSR0_RDERR_Msk (0x1ul << DDRPHY_PGSR0_RDERR_Pos) /*!< DDRPHY_T::PGSR0: RDERR Mask */ + +#define DDRPHY_PGSR0_WDERR_Pos (25) /*!< DDRPHY_T::PGSR0: WDERR Position */ +#define DDRPHY_PGSR0_WDERR_Msk (0x1ul << DDRPHY_PGSR0_WDERR_Pos) /*!< DDRPHY_T::PGSR0: WDERR Mask */ + +#define DDRPHY_PGSR0_REERR_Pos (26) /*!< DDRPHY_T::PGSR0: REERR Position */ +#define DDRPHY_PGSR0_REERR_Msk (0x1ul << DDRPHY_PGSR0_REERR_Pos) /*!< DDRPHY_T::PGSR0: REERR Mask */ + +#define DDRPHY_PGSR0_WEERR_Pos (27) /*!< DDRPHY_T::PGSR0: WEERR Position */ +#define DDRPHY_PGSR0_WEERR_Msk (0x1ul << DDRPHY_PGSR0_WEERR_Pos) /*!< DDRPHY_T::PGSR0: WEERR Mask */ + +#define DDRPHY_PGSR0_PLDONE_CHN_Pos (28) /*!< DDRPHY_T::PGSR0: PLDONE_CHN Position */ +#define DDRPHY_PGSR0_PLDONE_CHN_Msk (0x3ul << DDRPHY_PGSR0_PLDONE_CHN_Pos) /*!< DDRPHY_T::PGSR0: PLDONE_CHN Mask */ + +#define DDRPHY_PGSR0_APLOCK_Pos (31) /*!< DDRPHY_T::PGSR0: APLOCK Position */ +#define DDRPHY_PGSR0_APLOCK_Msk (0x1ul << DDRPHY_PGSR0_APLOCK_Pos) /*!< DDRPHY_T::PGSR0: APLOCK Mask */ + +#define DDRPHY_PGSR1_DLTDONE_Pos (0) /*!< DDRPHY_T::PGSR1: DLTDONE Position */ +#define DDRPHY_PGSR1_DLTDONE_Msk (0x1ul << DDRPHY_PGSR1_DLTDONE_Pos) /*!< DDRPHY_T::PGSR1: DLTDONE Mask */ + +#define DDRPHY_PGSR1_DLTCODE_Pos (1) /*!< DDRPHY_T::PGSR1: DLTCODE Position */ +#define DDRPHY_PGSR1_DLTCODE_Msk (0xfffffful << DDRPHY_PGSR1_DLTCODE_Pos) /*!< DDRPHY_T::PGSR1: DLTCODE Mask */ + +#define DDRPHY_PGSR1_VTSTOP_Pos (30) /*!< DDRPHY_T::PGSR1: VTSTOP Position */ +#define DDRPHY_PGSR1_VTSTOP_Msk (0x1ul << DDRPHY_PGSR1_VTSTOP_Pos) /*!< DDRPHY_T::PGSR1: VTSTOP Mask */ + +#define DDRPHY_PGSR1_PARERR_Pos (31) /*!< DDRPHY_T::PGSR1: PARERR Position */ +#define DDRPHY_PGSR1_PARERR_Msk (0x1ul << DDRPHY_PGSR1_PARERR_Pos) /*!< DDRPHY_T::PGSR1: PARERR Mask */ + +#define DDRPHY_PLLCR_DTC_Pos (0) /*!< DDRPHY_T::PLLCR: DTC Position */ +#define DDRPHY_PLLCR_DTC_Msk (0x3ul << DDRPHY_PLLCR_DTC_Pos) /*!< DDRPHY_T::PLLCR: DTC Mask */ + +#define DDRPHY_PLLCR_ATC_Pos (2) /*!< DDRPHY_T::PLLCR: ATC Position */ +#define DDRPHY_PLLCR_ATC_Msk (0xful << DDRPHY_PLLCR_ATC_Pos) /*!< DDRPHY_T::PLLCR: ATC Mask */ + +#define DDRPHY_PLLCR_ATOEN_Pos (6) /*!< DDRPHY_T::PLLCR: ATOEN Position */ +#define DDRPHY_PLLCR_ATOEN_Msk (0xful << DDRPHY_PLLCR_ATOEN_Pos) /*!< DDRPHY_T::PLLCR: ATOEN Mask */ + +#define DDRPHY_PLLCR_GSHIFT_Pos (10) /*!< DDRPHY_T::PLLCR: GSHIFT Position */ +#define DDRPHY_PLLCR_GSHIFT_Msk (0x1ul << DDRPHY_PLLCR_GSHIFT_Pos) /*!< DDRPHY_T::PLLCR: GSHIFT Mask */ + +#define DDRPHY_PLLCR_CPIC_Pos (11) /*!< DDRPHY_T::PLLCR: CPIC Position */ +#define DDRPHY_PLLCR_CPIC_Msk (0x3ul << DDRPHY_PLLCR_CPIC_Pos) /*!< DDRPHY_T::PLLCR: CPIC Mask */ + +#define DDRPHY_PLLCR_CPPC_Pos (13) /*!< DDRPHY_T::PLLCR: CPPC Position */ +#define DDRPHY_PLLCR_CPPC_Msk (0xful << DDRPHY_PLLCR_CPPC_Pos) /*!< DDRPHY_T::PLLCR: CPPC Mask */ + +#define DDRPHY_PLLCR_QPMODE_Pos (17) /*!< DDRPHY_T::PLLCR: QPMODE Position */ +#define DDRPHY_PLLCR_QPMODE_Msk (0x1ul << DDRPHY_PLLCR_QPMODE_Pos) /*!< DDRPHY_T::PLLCR: QPMODE Mask */ + +#define DDRPHY_PLLCR_FRQSEL_Pos (18) /*!< DDRPHY_T::PLLCR: FRQSEL Position */ +#define DDRPHY_PLLCR_FRQSEL_Msk (0x3ul << DDRPHY_PLLCR_FRQSEL_Pos) /*!< DDRPHY_T::PLLCR: FRQSEL Mask */ + +#define DDRPHY_PLLCR_PLLPD_Pos (29) /*!< DDRPHY_T::PLLCR: PLLPD Position */ +#define DDRPHY_PLLCR_PLLPD_Msk (0x1ul << DDRPHY_PLLCR_PLLPD_Pos) /*!< DDRPHY_T::PLLCR: PLLPD Mask */ + +#define DDRPHY_PLLCR_PLLRST_Pos (30) /*!< DDRPHY_T::PLLCR: PLLRST Position */ +#define DDRPHY_PLLCR_PLLRST_Msk (0x1ul << DDRPHY_PLLCR_PLLRST_Pos) /*!< DDRPHY_T::PLLCR: PLLRST Mask */ + +#define DDRPHY_PLLCR_BYP_Pos (31) /*!< DDRPHY_T::PLLCR: BYP Position */ +#define DDRPHY_PLLCR_BYP_Msk (0x1ul << DDRPHY_PLLCR_BYP_Pos) /*!< DDRPHY_T::PLLCR: BYP Mask */ + +#define DDRPHY_PTR0_tPHYRST_Pos (0) /*!< DDRPHY_T::PTR0: tPHYRST Position */ +#define DDRPHY_PTR0_tPHYRST_Msk (0x3ful << DDRPHY_PTR0_tPHYRST_Pos) /*!< DDRPHY_T::PTR0: tPHYRST Mask */ + +#define DDRPHY_PTR0_tPLLGS_Pos (6) /*!< DDRPHY_T::PTR0: tPLLGS Position */ +#define DDRPHY_PTR0_tPLLGS_Msk (0x7ffful << DDRPHY_PTR0_tPLLGS_Pos) /*!< DDRPHY_T::PTR0: tPLLGS Mask */ + +#define DDRPHY_PTR0_tPLLPD_Pos (21) /*!< DDRPHY_T::PTR0: tPLLPD Position */ +#define DDRPHY_PTR0_tPLLPD_Msk (0x7fful << DDRPHY_PTR0_tPLLPD_Pos) /*!< DDRPHY_T::PTR0: tPLLPD Mask */ + +#define DDRPHY_PTR1_tPLLRST_Pos (0) /*!< DDRPHY_T::PTR1: tPLLRST Position */ +#define DDRPHY_PTR1_tPLLRST_Msk (0x1ffful << DDRPHY_PTR1_tPLLRST_Pos) /*!< DDRPHY_T::PTR1: tPLLRST Mask */ + +#define DDRPHY_PTR1_tPLLLOCK_Pos (16) /*!< DDRPHY_T::PTR1: tPLLLOCK Position */ +#define DDRPHY_PTR1_tPLLLOCK_Msk (0xfffful << DDRPHY_PTR1_tPLLLOCK_Pos) /*!< DDRPHY_T::PTR1: tPLLLOCK Mask */ + +#define DDRPHY_PTR2_tCALON_Pos (0) /*!< DDRPHY_T::PTR2: tCALON Position */ +#define DDRPHY_PTR2_tCALON_Msk (0x1ful << DDRPHY_PTR2_tCALON_Pos) /*!< DDRPHY_T::PTR2: tCALON Mask */ + +#define DDRPHY_PTR2_tCALS_Pos (5) /*!< DDRPHY_T::PTR2: tCALS Position */ +#define DDRPHY_PTR2_tCALS_Msk (0x1ful << DDRPHY_PTR2_tCALS_Pos) /*!< DDRPHY_T::PTR2: tCALS Mask */ + +#define DDRPHY_PTR2_tCALH_Pos (10) /*!< DDRPHY_T::PTR2: tCALH Position */ +#define DDRPHY_PTR2_tCALH_Msk (0x1ful << DDRPHY_PTR2_tCALH_Pos) /*!< DDRPHY_T::PTR2: tCALH Mask */ + +#define DDRPHY_PTR2_tWLDLYS_Pos (15) /*!< DDRPHY_T::PTR2: tWLDLYS Position */ +#define DDRPHY_PTR2_tWLDLYS_Msk (0x1ful << DDRPHY_PTR2_tWLDLYS_Pos) /*!< DDRPHY_T::PTR2: tWLDLYS Mask */ + +#define DDRPHY_PTR3_tDINIT0_Pos (0) /*!< DDRPHY_T::PTR3: tDINIT0 Position */ +#define DDRPHY_PTR3_tDINIT0_Msk (0xffffful << DDRPHY_PTR3_tDINIT0_Pos) /*!< DDRPHY_T::PTR3: tDINIT0 Mask */ + +#define DDRPHY_PTR3_tDINIT1_Pos (20) /*!< DDRPHY_T::PTR3: tDINIT1 Position */ +#define DDRPHY_PTR3_tDINIT1_Msk (0x1fful << DDRPHY_PTR3_tDINIT1_Pos) /*!< DDRPHY_T::PTR3: tDINIT1 Mask */ + +#define DDRPHY_PTR4_tDINIT2_Pos (0) /*!< DDRPHY_T::PTR4: tDINIT2 Position */ +#define DDRPHY_PTR4_tDINIT2_Msk (0x3fffful << DDRPHY_PTR4_tDINIT2_Pos) /*!< DDRPHY_T::PTR4: tDINIT2 Mask */ + +#define DDRPHY_PTR4_tDINIT3_Pos (18) /*!< DDRPHY_T::PTR4: tDINIT3 Position */ +#define DDRPHY_PTR4_tDINIT3_Msk (0x3fful << DDRPHY_PTR4_tDINIT3_Pos) /*!< DDRPHY_T::PTR4: tDINIT3 Mask */ + +#define DDRPHY_ACMDLR_IPRD_Pos (0) /*!< DDRPHY_T::ACMDLR: IPRD Position */ +#define DDRPHY_ACMDLR_IPRD_Msk (0xfful << DDRPHY_ACMDLR_IPRD_Pos) /*!< DDRPHY_T::ACMDLR: IPRD Mask */ + +#define DDRPHY_ACMDLR_TPRD_Pos (8) /*!< DDRPHY_T::ACMDLR: TPRD Position */ +#define DDRPHY_ACMDLR_TPRD_Msk (0xfful << DDRPHY_ACMDLR_TPRD_Pos) /*!< DDRPHY_T::ACMDLR: TPRD Mask */ + +#define DDRPHY_ACMDLR_MDLD_Pos (16) /*!< DDRPHY_T::ACMDLR: MDLD Position */ +#define DDRPHY_ACMDLR_MDLD_Msk (0xfful << DDRPHY_ACMDLR_MDLD_Pos) /*!< DDRPHY_T::ACMDLR: MDLD Mask */ + +#define DDRPHY_ACBDLR_CK0BD_Pos (0) /*!< DDRPHY_T::ACBDLR: CK0BD Position */ +#define DDRPHY_ACBDLR_CK0BD_Msk (0x3ful << DDRPHY_ACBDLR_CK0BD_Pos) /*!< DDRPHY_T::ACBDLR: CK0BD Mask */ + +#define DDRPHY_ACBDLR_CK1BD_Pos (6) /*!< DDRPHY_T::ACBDLR: CK1BD Position */ +#define DDRPHY_ACBDLR_CK1BD_Msk (0x3ful << DDRPHY_ACBDLR_CK1BD_Pos) /*!< DDRPHY_T::ACBDLR: CK1BD Mask */ + +#define DDRPHY_ACBDLR_CK2BD_Pos (12) /*!< DDRPHY_T::ACBDLR: CK2BD Position */ +#define DDRPHY_ACBDLR_CK2BD_Msk (0x3ful << DDRPHY_ACBDLR_CK2BD_Pos) /*!< DDRPHY_T::ACBDLR: CK2BD Mask */ + +#define DDRPHY_ACBDLR_ACBD_Pos (18) /*!< DDRPHY_T::ACBDLR: ACBD Position */ +#define DDRPHY_ACBDLR_ACBD_Msk (0x3ful << DDRPHY_ACBDLR_ACBD_Pos) /*!< DDRPHY_T::ACBDLR: ACBD Mask */ + +#define DDRPHY_ACIOCR_ACIOM_Pos (0) /*!< DDRPHY_T::ACIOCR: ACIOM Position */ +#define DDRPHY_ACIOCR_ACIOM_Msk (0x1ul << DDRPHY_ACIOCR_ACIOM_Pos) /*!< DDRPHY_T::ACIOCR: ACIOM Mask */ + +#define DDRPHY_ACIOCR_ACOE_Pos (1) /*!< DDRPHY_T::ACIOCR: ACOE Position */ +#define DDRPHY_ACIOCR_ACOE_Msk (0x1ul << DDRPHY_ACIOCR_ACOE_Pos) /*!< DDRPHY_T::ACIOCR: ACOE Mask */ + +#define DDRPHY_ACIOCR_ACODT_Pos (2) /*!< DDRPHY_T::ACIOCR: ACODT Position */ +#define DDRPHY_ACIOCR_ACODT_Msk (0x1ul << DDRPHY_ACIOCR_ACODT_Pos) /*!< DDRPHY_T::ACIOCR: ACODT Mask */ + +#define DDRPHY_ACIOCR_ACPDD_Pos (3) /*!< DDRPHY_T::ACIOCR: ACPDD Position */ +#define DDRPHY_ACIOCR_ACPDD_Msk (0x1ul << DDRPHY_ACIOCR_ACPDD_Pos) /*!< DDRPHY_T::ACIOCR: ACPDD Mask */ + +#define DDRPHY_ACIOCR_ACPDR_Pos (4) /*!< DDRPHY_T::ACIOCR: ACPDR Position */ +#define DDRPHY_ACIOCR_ACPDR_Msk (0x1ul << DDRPHY_ACIOCR_ACPDR_Pos) /*!< DDRPHY_T::ACIOCR: ACPDR Mask */ + +#define DDRPHY_ACIOCR_CKODT_Pos (5) /*!< DDRPHY_T::ACIOCR: CKODT Position */ +#define DDRPHY_ACIOCR_CKODT_Msk (0x7ul << DDRPHY_ACIOCR_CKODT_Pos) /*!< DDRPHY_T::ACIOCR: CKODT Mask */ + +#define DDRPHY_ACIOCR_CKPDD_Pos (8) /*!< DDRPHY_T::ACIOCR: CKPDD Position */ +#define DDRPHY_ACIOCR_CKPDD_Msk (0x7ul << DDRPHY_ACIOCR_CKPDD_Pos) /*!< DDRPHY_T::ACIOCR: CKPDD Mask */ + +#define DDRPHY_ACIOCR_CKPDR_Pos (11) /*!< DDRPHY_T::ACIOCR: CKPDR Position */ +#define DDRPHY_ACIOCR_CKPDR_Msk (0x7ul << DDRPHY_ACIOCR_CKPDR_Pos) /*!< DDRPHY_T::ACIOCR: CKPDR Mask */ + +#define DDRPHY_ACIOCR_RANKODT_Pos (14) /*!< DDRPHY_T::ACIOCR: RANKODT Position */ +#define DDRPHY_ACIOCR_RANKODT_Msk (0xful << DDRPHY_ACIOCR_RANKODT_Pos) /*!< DDRPHY_T::ACIOCR: RANKODT Mask */ + +#define DDRPHY_ACIOCR_CSPDD_Pos (18) /*!< DDRPHY_T::ACIOCR: CSPDD Position */ +#define DDRPHY_ACIOCR_CSPDD_Msk (0xful << DDRPHY_ACIOCR_CSPDD_Pos) /*!< DDRPHY_T::ACIOCR: CSPDD Mask */ + +#define DDRPHY_ACIOCR_RANKPDR_Pos (22) /*!< DDRPHY_T::ACIOCR: RANKPDR Position */ +#define DDRPHY_ACIOCR_RANKPDR_Msk (0xful << DDRPHY_ACIOCR_RANKPDR_Pos) /*!< DDRPHY_T::ACIOCR: RANKPDR Mask */ + +#define DDRPHY_ACIOCR_RSTODT_Pos (26) /*!< DDRPHY_T::ACIOCR: RSTODT Position */ +#define DDRPHY_ACIOCR_RSTODT_Msk (0x1ul << DDRPHY_ACIOCR_RSTODT_Pos) /*!< DDRPHY_T::ACIOCR: RSTODT Mask */ + +#define DDRPHY_ACIOCR_RSTPDD_Pos (27) /*!< DDRPHY_T::ACIOCR: RSTPDD Position */ +#define DDRPHY_ACIOCR_RSTPDD_Msk (0x1ul << DDRPHY_ACIOCR_RSTPDD_Pos) /*!< DDRPHY_T::ACIOCR: RSTPDD Mask */ + +#define DDRPHY_ACIOCR_RSTPDR_Pos (28) /*!< DDRPHY_T::ACIOCR: RSTPDR Position */ +#define DDRPHY_ACIOCR_RSTPDR_Msk (0x1ul << DDRPHY_ACIOCR_RSTPDR_Pos) /*!< DDRPHY_T::ACIOCR: RSTPDR Mask */ + +#define DDRPHY_ACIOCR_RSTIOM_Pos (29) /*!< DDRPHY_T::ACIOCR: RSTIOM Position */ +#define DDRPHY_ACIOCR_RSTIOM_Msk (0x1ul << DDRPHY_ACIOCR_RSTIOM_Pos) /*!< DDRPHY_T::ACIOCR: RSTIOM Mask */ + +#define DDRPHY_ACIOCR_ACSR_Pos (30) /*!< DDRPHY_T::ACIOCR: ACSR Position */ +#define DDRPHY_ACIOCR_ACSR_Msk (0x3ul << DDRPHY_ACIOCR_ACSR_Pos) /*!< DDRPHY_T::ACIOCR: ACSR Mask */ + +#define DDRPHY_DXCCR_DXODT_Pos (0) /*!< DDRPHY_T::DXCCR: DXODT Position */ +#define DDRPHY_DXCCR_DXODT_Msk (0x1ul << DDRPHY_DXCCR_DXODT_Pos) /*!< DDRPHY_T::DXCCR: DXODT Mask */ + +#define DDRPHY_DXCCR_DXIOM_Pos (1) /*!< DDRPHY_T::DXCCR: DXIOM Position */ +#define DDRPHY_DXCCR_DXIOM_Msk (0x1ul << DDRPHY_DXCCR_DXIOM_Pos) /*!< DDRPHY_T::DXCCR: DXIOM Mask */ + +#define DDRPHY_DXCCR_MDLEN_Pos (2) /*!< DDRPHY_T::DXCCR: MDLEN Position */ +#define DDRPHY_DXCCR_MDLEN_Msk (0x1ul << DDRPHY_DXCCR_MDLEN_Pos) /*!< DDRPHY_T::DXCCR: MDLEN Mask */ + +#define DDRPHY_DXCCR_DXPDD_Pos (3) /*!< DDRPHY_T::DXCCR: DXPDD Position */ +#define DDRPHY_DXCCR_DXPDD_Msk (0x1ul << DDRPHY_DXCCR_DXPDD_Pos) /*!< DDRPHY_T::DXCCR: DXPDD Mask */ + +#define DDRPHY_DXCCR_DXPDR_Pos (4) /*!< DDRPHY_T::DXCCR: DXPDR Position */ +#define DDRPHY_DXCCR_DXPDR_Msk (0x1ul << DDRPHY_DXCCR_DXPDR_Pos) /*!< DDRPHY_T::DXCCR: DXPDR Mask */ + +#define DDRPHY_DXCCR_DQSRES_Pos (5) /*!< DDRPHY_T::DXCCR: DQSRES Position */ +#define DDRPHY_DXCCR_DQSRES_Msk (0xful << DDRPHY_DXCCR_DQSRES_Pos) /*!< DDRPHY_T::DXCCR: DQSRES Mask */ + +#define DDRPHY_DXCCR_DQSNRES_Pos (9) /*!< DDRPHY_T::DXCCR: DQSNRES Position */ +#define DDRPHY_DXCCR_DQSNRES_Msk (0xful << DDRPHY_DXCCR_DQSNRES_Pos) /*!< DDRPHY_T::DXCCR: DQSNRES Mask */ + +#define DDRPHY_DXCCR_DXSR_Pos (13) /*!< DDRPHY_T::DXCCR: DXSR Position */ +#define DDRPHY_DXCCR_DXSR_Msk (0x3ul << DDRPHY_DXCCR_DXSR_Pos) /*!< DDRPHY_T::DXCCR: DXSR Mask */ + +#define DDRPHY_DXCCR_MSBUDQ_Pos (15) /*!< DDRPHY_T::DXCCR: MSBUDQ Position */ +#define DDRPHY_DXCCR_MSBUDQ_Msk (0x7ul << DDRPHY_DXCCR_MSBUDQ_Pos) /*!< DDRPHY_T::DXCCR: MSBUDQ Mask */ + +#define DDRPHY_DXCCR_UDQODT_Pos (18) /*!< DDRPHY_T::DXCCR: UDQODT Position */ +#define DDRPHY_DXCCR_UDQODT_Msk (0x1ul << DDRPHY_DXCCR_UDQODT_Pos) /*!< DDRPHY_T::DXCCR: UDQODT Mask */ + +#define DDRPHY_DXCCR_UDQPDD_Pos (19) /*!< DDRPHY_T::DXCCR: UDQPDD Position */ +#define DDRPHY_DXCCR_UDQPDD_Msk (0x1ul << DDRPHY_DXCCR_UDQPDD_Pos) /*!< DDRPHY_T::DXCCR: UDQPDD Mask */ + +#define DDRPHY_DXCCR_UDQPDR_Pos (20) /*!< DDRPHY_T::DXCCR: UDQPDR Position */ +#define DDRPHY_DXCCR_UDQPDR_Msk (0x1ul << DDRPHY_DXCCR_UDQPDR_Pos) /*!< DDRPHY_T::DXCCR: UDQPDR Mask */ + +#define DDRPHY_DXCCR_UDQIOM_Pos (21) /*!< DDRPHY_T::DXCCR: UDQIOM Position */ +#define DDRPHY_DXCCR_UDQIOM_Msk (0x1ul << DDRPHY_DXCCR_UDQIOM_Pos) /*!< DDRPHY_T::DXCCR: UDQIOM Mask */ + +#define DDRPHY_DXCCR_DYNDXPDD_Pos (22) /*!< DDRPHY_T::DXCCR: DYNDXPDD Position */ +#define DDRPHY_DXCCR_DYNDXPDD_Msk (0x1ul << DDRPHY_DXCCR_DYNDXPDD_Pos) /*!< DDRPHY_T::DXCCR: DYNDXPDD Mask */ + +#define DDRPHY_DXCCR_DYNDXPDR_Pos (23) /*!< DDRPHY_T::DXCCR: DYNDXPDR Position */ +#define DDRPHY_DXCCR_DYNDXPDR_Msk (0x1ul << DDRPHY_DXCCR_DYNDXPDR_Pos) /*!< DDRPHY_T::DXCCR: DYNDXPDR Mask */ + +#define DDRPHY_DXCCR_DDPDDCDO_Pos (24) /*!< DDRPHY_T::DXCCR: DDPDDCDO Position */ +#define DDRPHY_DXCCR_DDPDDCDO_Msk (0xful << DDRPHY_DXCCR_DDPDDCDO_Pos) /*!< DDRPHY_T::DXCCR: DDPDDCDO Mask */ + +#define DDRPHY_DXCCR_DDPDRCDO_Pos (28) /*!< DDRPHY_T::DXCCR: DDPDRCDO Position */ +#define DDRPHY_DXCCR_DDPDRCDO_Msk (0xful << DDRPHY_DXCCR_DDPDRCDO_Pos) /*!< DDRPHY_T::DXCCR: DDPDRCDO Mask */ + +#define DDRPHY_DSGCR_PUREN_Pos (0) /*!< DDRPHY_T::DSGCR: PUREN Position */ +#define DDRPHY_DSGCR_PUREN_Msk (0x1ul << DDRPHY_DSGCR_PUREN_Pos) /*!< DDRPHY_T::DSGCR: PUREN Mask */ + +#define DDRPHY_DSGCR_BDISEN_Pos (1) /*!< DDRPHY_T::DSGCR: BDISEN Position */ +#define DDRPHY_DSGCR_BDISEN_Msk (0x1ul << DDRPHY_DSGCR_BDISEN_Pos) /*!< DDRPHY_T::DSGCR: BDISEN Mask */ + +#define DDRPHY_DSGCR_ZUEN_Pos (2) /*!< DDRPHY_T::DSGCR: ZUEN Position */ +#define DDRPHY_DSGCR_ZUEN_Msk (0x1ul << DDRPHY_DSGCR_ZUEN_Pos) /*!< DDRPHY_T::DSGCR: ZUEN Mask */ + +#define DDRPHY_DSGCR_LPIOPD_Pos (3) /*!< DDRPHY_T::DSGCR: LPIOPD Position */ +#define DDRPHY_DSGCR_LPIOPD_Msk (0x1ul << DDRPHY_DSGCR_LPIOPD_Pos) /*!< DDRPHY_T::DSGCR: LPIOPD Mask */ + +#define DDRPHY_DSGCR_LPPLLPD_Pos (4) /*!< DDRPHY_T::DSGCR: LPPLLPD Position */ +#define DDRPHY_DSGCR_LPPLLPD_Msk (0x1ul << DDRPHY_DSGCR_LPPLLPD_Pos) /*!< DDRPHY_T::DSGCR: LPPLLPD Mask */ + +#define DDRPHY_DSGCR_CUAEN_Pos (5) /*!< DDRPHY_T::DSGCR: CUAEN Position */ +#define DDRPHY_DSGCR_CUAEN_Msk (0x1ul << DDRPHY_DSGCR_CUAEN_Pos) /*!< DDRPHY_T::DSGCR: CUAEN Mask */ + +#define DDRPHY_DSGCR_DQSGX_Pos (6) /*!< DDRPHY_T::DSGCR: DQSGX Position */ +#define DDRPHY_DSGCR_DQSGX_Msk (0x1ul << DDRPHY_DSGCR_DQSGX_Pos) /*!< DDRPHY_T::DSGCR: DQSGX Mask */ + +#define DDRPHY_DSGCR_BRRMODE_Pos (7) /*!< DDRPHY_T::DSGCR: BRRMODE Position */ +#define DDRPHY_DSGCR_BRRMODE_Msk (0x1ul << DDRPHY_DSGCR_BRRMODE_Pos) /*!< DDRPHY_T::DSGCR: BRRMODE Mask */ + +#define DDRPHY_DSGCR_PUAD_Pos (8) /*!< DDRPHY_T::DSGCR: PUAD Position */ +#define DDRPHY_DSGCR_PUAD_Msk (0xful << DDRPHY_DSGCR_PUAD_Pos) /*!< DDRPHY_T::DSGCR: PUAD Mask */ + +#define DDRPHY_DSGCR_DTOODT_Pos (12) /*!< DDRPHY_T::DSGCR: DTOODT Position */ +#define DDRPHY_DSGCR_DTOODT_Msk (0x1ul << DDRPHY_DSGCR_DTOODT_Pos) /*!< DDRPHY_T::DSGCR: DTOODT Mask */ + +#define DDRPHY_DSGCR_DTOPDD_Pos (13) /*!< DDRPHY_T::DSGCR: DTOPDD Position */ +#define DDRPHY_DSGCR_DTOPDD_Msk (0x1ul << DDRPHY_DSGCR_DTOPDD_Pos) /*!< DDRPHY_T::DSGCR: DTOPDD Mask */ + +#define DDRPHY_DSGCR_DTOPDR_Pos (14) /*!< DDRPHY_T::DSGCR: DTOPDR Position */ +#define DDRPHY_DSGCR_DTOPDR_Msk (0x1ul << DDRPHY_DSGCR_DTOPDR_Pos) /*!< DDRPHY_T::DSGCR: DTOPDR Mask */ + +#define DDRPHY_DSGCR_DTOIOM_Pos (15) /*!< DDRPHY_T::DSGCR: DTOIOM Position */ +#define DDRPHY_DSGCR_DTOIOM_Msk (0x1ul << DDRPHY_DSGCR_DTOIOM_Pos) /*!< DDRPHY_T::DSGCR: DTOIOM Mask */ + +#define DDRPHY_DSGCR_DTOOE_Pos (16) /*!< DDRPHY_T::DSGCR: DTOOE Position */ +#define DDRPHY_DSGCR_DTOOE_Msk (0x1ul << DDRPHY_DSGCR_DTOOE_Pos) /*!< DDRPHY_T::DSGCR: DTOOE Mask */ + +#define DDRPHY_DSGCR_ATOAE_Pos (17) /*!< DDRPHY_T::DSGCR: ATOAE Position */ +#define DDRPHY_DSGCR_ATOAE_Msk (0x1ul << DDRPHY_DSGCR_ATOAE_Pos) /*!< DDRPHY_T::DSGCR: ATOAE Mask */ + +#define DDRPHY_DSGCR_RRMODE_Pos (18) /*!< DDRPHY_T::DSGCR: RRMODE Position */ +#define DDRPHY_DSGCR_RRMODE_Msk (0x1ul << DDRPHY_DSGCR_RRMODE_Pos) /*!< DDRPHY_T::DSGCR: RRMODE Mask */ + +#define DDRPHY_DSGCR_SDRMODE_Pos (19) /*!< DDRPHY_T::DSGCR: SDRMODE Position */ +#define DDRPHY_DSGCR_SDRMODE_Msk (0x1ul << DDRPHY_DSGCR_SDRMODE_Pos) /*!< DDRPHY_T::DSGCR: SDRMODE Mask */ + +#define DDRPHY_DSGCR_CKEPDD_Pos (20) /*!< DDRPHY_T::DSGCR: CKEPDD Position */ +#define DDRPHY_DSGCR_CKEPDD_Msk (0xful << DDRPHY_DSGCR_CKEPDD_Pos) /*!< DDRPHY_T::DSGCR: CKEPDD Mask */ + +#define DDRPHY_DSGCR_ODTPDD_Pos (24) /*!< DDRPHY_T::DSGCR: ODTPDD Position */ +#define DDRPHY_DSGCR_ODTPDD_Msk (0xful << DDRPHY_DSGCR_ODTPDD_Pos) /*!< DDRPHY_T::DSGCR: ODTPDD Mask */ + +#define DDRPHY_DSGCR_CKOE_Pos (28) /*!< DDRPHY_T::DSGCR: CKOE Position */ +#define DDRPHY_DSGCR_CKOE_Msk (0x1ul << DDRPHY_DSGCR_CKOE_Pos) /*!< DDRPHY_T::DSGCR: CKOE Mask */ + +#define DDRPHY_DSGCR_ODTOE_Pos (29) /*!< DDRPHY_T::DSGCR: ODTOE Position */ +#define DDRPHY_DSGCR_ODTOE_Msk (0x1ul << DDRPHY_DSGCR_ODTOE_Pos) /*!< DDRPHY_T::DSGCR: ODTOE Mask */ + +#define DDRPHY_DSGCR_RSTOE_Pos (30) /*!< DDRPHY_T::DSGCR: RSTOE Position */ +#define DDRPHY_DSGCR_RSTOE_Msk (0x1ul << DDRPHY_DSGCR_RSTOE_Pos) /*!< DDRPHY_T::DSGCR: RSTOE Mask */ + +#define DDRPHY_DSGCR_CKEOE_Pos (31) /*!< DDRPHY_T::DSGCR: CKEOE Position */ +#define DDRPHY_DSGCR_CKEOE_Msk (0x1ul << DDRPHY_DSGCR_CKEOE_Pos) /*!< DDRPHY_T::DSGCR: CKEOE Mask */ + +#define DDRPHY_DCR_DDRMD_Pos (0) /*!< DDRPHY_T::DCR: DDRMD Position */ +#define DDRPHY_DCR_DDRMD_Msk (0x7ul << DDRPHY_DCR_DDRMD_Pos) /*!< DDRPHY_T::DCR: DDRMD Mask */ + +#define DDRPHY_DCR_DDR8BNK_Pos (3) /*!< DDRPHY_T::DCR: DDR8BNK Position */ +#define DDRPHY_DCR_DDR8BNK_Msk (0x1ul << DDRPHY_DCR_DDR8BNK_Pos) /*!< DDRPHY_T::DCR: DDR8BNK Mask */ + +#define DDRPHY_DCR_PDQ_Pos (4) /*!< DDRPHY_T::DCR: PDQ Position */ +#define DDRPHY_DCR_PDQ_Msk (0x7ul << DDRPHY_DCR_PDQ_Pos) /*!< DDRPHY_T::DCR: PDQ Mask */ + +#define DDRPHY_DCR_MPRDQ_Pos (7) /*!< DDRPHY_T::DCR: MPRDQ Position */ +#define DDRPHY_DCR_MPRDQ_Msk (0x1ul << DDRPHY_DCR_MPRDQ_Pos) /*!< DDRPHY_T::DCR: MPRDQ Mask */ + +#define DDRPHY_DCR_BYTEMASK_Pos (10) /*!< DDRPHY_T::DCR: BYTEMASK Position */ +#define DDRPHY_DCR_BYTEMASK_Msk (0xfful << DDRPHY_DCR_BYTEMASK_Pos) /*!< DDRPHY_T::DCR: BYTEMASK Mask */ + +#define DDRPHY_DCR_NOSRA_Pos (27) /*!< DDRPHY_T::DCR: NOSRA Position */ +#define DDRPHY_DCR_NOSRA_Msk (0x1ul << DDRPHY_DCR_NOSRA_Pos) /*!< DDRPHY_T::DCR: NOSRA Mask */ + +#define DDRPHY_DCR_DDR2T_Pos (28) /*!< DDRPHY_T::DCR: DDR2T Position */ +#define DDRPHY_DCR_DDR2T_Msk (0x1ul << DDRPHY_DCR_DDR2T_Pos) /*!< DDRPHY_T::DCR: DDR2T Mask */ + +#define DDRPHY_DCR_UDIMM_Pos (29) /*!< DDRPHY_T::DCR: UDIMM Position */ +#define DDRPHY_DCR_UDIMM_Msk (0x1ul << DDRPHY_DCR_UDIMM_Pos) /*!< DDRPHY_T::DCR: UDIMM Mask */ + +#define DDRPHY_DTPR0_tRTP_Pos (0) /*!< DDRPHY_T::DTPR0: tRTP Position */ +#define DDRPHY_DTPR0_tRTP_Msk (0xful << DDRPHY_DTPR0_tRTP_Pos) /*!< DDRPHY_T::DTPR0: tRTP Mask */ + +#define DDRPHY_DTPR0_tWTR_Pos (4) /*!< DDRPHY_T::DTPR0: tWTR Position */ +#define DDRPHY_DTPR0_tWTR_Msk (0xful << DDRPHY_DTPR0_tWTR_Pos) /*!< DDRPHY_T::DTPR0: tWTR Mask */ + +#define DDRPHY_DTPR0_tRP_Pos (8) /*!< DDRPHY_T::DTPR0: tRP Position */ +#define DDRPHY_DTPR0_tRP_Msk (0xful << DDRPHY_DTPR0_tRP_Pos) /*!< DDRPHY_T::DTPR0: tRP Mask */ + +#define DDRPHY_DTPR0_tRCD_Pos (12) /*!< DDRPHY_T::DTPR0: tRCD Position */ +#define DDRPHY_DTPR0_tRCD_Msk (0xful << DDRPHY_DTPR0_tRCD_Pos) /*!< DDRPHY_T::DTPR0: tRCD Mask */ + +#define DDRPHY_DTPR0_tRAS_Pos (16) /*!< DDRPHY_T::DTPR0: tRAS Position */ +#define DDRPHY_DTPR0_tRAS_Msk (0x3ful << DDRPHY_DTPR0_tRAS_Pos) /*!< DDRPHY_T::DTPR0: tRAS Mask */ + +#define DDRPHY_DTPR0_tRRD_Pos (22) /*!< DDRPHY_T::DTPR0: tRRD Position */ +#define DDRPHY_DTPR0_tRRD_Msk (0xful << DDRPHY_DTPR0_tRRD_Pos) /*!< DDRPHY_T::DTPR0: tRRD Mask */ + +#define DDRPHY_DTPR0_tRC_Pos (26) /*!< DDRPHY_T::DTPR0: tRC Position */ +#define DDRPHY_DTPR0_tRC_Msk (0x3ful << DDRPHY_DTPR0_tRC_Pos) /*!< DDRPHY_T::DTPR0: tRC Mask */ + +#define DDRPHY_DTPR1_tMRD_Pos (0) /*!< DDRPHY_T::DTPR1: tMRD Position */ +#define DDRPHY_DTPR1_tMRD_Msk (0x3ul << DDRPHY_DTPR1_tMRD_Pos) /*!< DDRPHY_T::DTPR1: tMRD Mask */ + +#define DDRPHY_DTPR1_tMOD_Pos (2) /*!< DDRPHY_T::DTPR1: tMOD Position */ +#define DDRPHY_DTPR1_tMOD_Msk (0x7ul << DDRPHY_DTPR1_tMOD_Pos) /*!< DDRPHY_T::DTPR1: tMOD Mask */ + +#define DDRPHY_DTPR1_tFAW_Pos (5) /*!< DDRPHY_T::DTPR1: tFAW Position */ +#define DDRPHY_DTPR1_tFAW_Msk (0x3ful << DDRPHY_DTPR1_tFAW_Pos) /*!< DDRPHY_T::DTPR1: tFAW Mask */ + +#define DDRPHY_DTPR1_tRFC_Pos (11) /*!< DDRPHY_T::DTPR1: tRFC Position */ +#define DDRPHY_DTPR1_tRFC_Msk (0x1fful << DDRPHY_DTPR1_tRFC_Pos) /*!< DDRPHY_T::DTPR1: tRFC Mask */ + +#define DDRPHY_DTPR1_tWLMRD_Pos (20) /*!< DDRPHY_T::DTPR1: tWLMRD Position */ +#define DDRPHY_DTPR1_tWLMRD_Msk (0x3ful << DDRPHY_DTPR1_tWLMRD_Pos) /*!< DDRPHY_T::DTPR1: tWLMRD Mask */ + +#define DDRPHY_DTPR1_tWLO_Pos (26) /*!< DDRPHY_T::DTPR1: tWLO Position */ +#define DDRPHY_DTPR1_tWLO_Msk (0xful << DDRPHY_DTPR1_tWLO_Pos) /*!< DDRPHY_T::DTPR1: tWLO Mask */ + +#define DDRPHY_DTPR1_tAONDtAOFD_Pos (30) /*!< DDRPHY_T::DTPR1: tAONDtAOFD Position */ +#define DDRPHY_DTPR1_tAONDtAOFD_Msk (0x3ul << DDRPHY_DTPR1_tAONDtAOFD_Pos) /*!< DDRPHY_T::DTPR1: tAONDtAOFD Mask */ + +#define DDRPHY_DTPR2_tXS_Pos (0) /*!< DDRPHY_T::DTPR2: tXS Position */ +#define DDRPHY_DTPR2_tXS_Msk (0x3fful << DDRPHY_DTPR2_tXS_Pos) /*!< DDRPHY_T::DTPR2: tXS Mask */ + +#define DDRPHY_DTPR2_tXP_Pos (10) /*!< DDRPHY_T::DTPR2: tXP Position */ +#define DDRPHY_DTPR2_tXP_Msk (0x1ful << DDRPHY_DTPR2_tXP_Pos) /*!< DDRPHY_T::DTPR2: tXP Mask */ + +#define DDRPHY_DTPR2_tCKE_Pos (15) /*!< DDRPHY_T::DTPR2: tCKE Position */ +#define DDRPHY_DTPR2_tCKE_Msk (0xful << DDRPHY_DTPR2_tCKE_Pos) /*!< DDRPHY_T::DTPR2: tCKE Mask */ + +#define DDRPHY_DTPR2_tDLLK_Pos (19) /*!< DDRPHY_T::DTPR2: tDLLK Position */ +#define DDRPHY_DTPR2_tDLLK_Msk (0x3fful << DDRPHY_DTPR2_tDLLK_Pos) /*!< DDRPHY_T::DTPR2: tDLLK Mask */ + +#define DDRPHY_DTPR2_tRTODT_Pos (29) /*!< DDRPHY_T::DTPR2: tRTODT Position */ +#define DDRPHY_DTPR2_tRTODT_Msk (0x1ul << DDRPHY_DTPR2_tRTODT_Pos) /*!< DDRPHY_T::DTPR2: tRTODT Mask */ + +#define DDRPHY_DTPR2_tRTW_Pos (30) /*!< DDRPHY_T::DTPR2: tRTW Position */ +#define DDRPHY_DTPR2_tRTW_Msk (0x1ul << DDRPHY_DTPR2_tRTW_Pos) /*!< DDRPHY_T::DTPR2: tRTW Mask */ + +#define DDRPHY_DTPR2_tCCD_Pos (31) /*!< DDRPHY_T::DTPR2: tCCD Position */ +#define DDRPHY_DTPR2_tCCD_Msk (0x1ul << DDRPHY_DTPR2_tCCD_Pos) /*!< DDRPHY_T::DTPR2: tCCD Mask */ + +#define DDRPHY_MR0_BL_Pos (0) /*!< DDRPHY_T::MR0: BL Position */ +#define DDRPHY_MR0_BL_Msk (0x3ul << DDRPHY_MR0_BL_Pos) /*!< DDRPHY_T::MR0: BL Mask */ + +#define DDRPHY_MR0_CL0_Pos (2) /*!< DDRPHY_T::MR0: CL0 Position */ +#define DDRPHY_MR0_CL0_Msk (0x1ul << DDRPHY_MR0_CL0_Pos) /*!< DDRPHY_T::MR0: CL0 Mask */ + +#define DDRPHY_MR0_BT_Pos (3) /*!< DDRPHY_T::MR0: BT Position */ +#define DDRPHY_MR0_BT_Msk (0x1ul << DDRPHY_MR0_BT_Pos) /*!< DDRPHY_T::MR0: BT Mask */ + +#define DDRPHY_MR0_CL1_Pos (4) /*!< DDRPHY_T::MR0: CL1 Position */ +#define DDRPHY_MR0_CL1_Msk (0x7ul << DDRPHY_MR0_CL1_Pos) /*!< DDRPHY_T::MR0: CL1 Mask */ + +#define DDRPHY_MR0_TM_Pos (7) /*!< DDRPHY_T::MR0: TM Position */ +#define DDRPHY_MR0_TM_Msk (0x1ul << DDRPHY_MR0_TM_Pos) /*!< DDRPHY_T::MR0: TM Mask */ + +#define DDRPHY_MR0_DR_Pos (8) /*!< DDRPHY_T::MR0: DR Position */ +#define DDRPHY_MR0_DR_Msk (0x1ul << DDRPHY_MR0_DR_Pos) /*!< DDRPHY_T::MR0: DR Mask */ + +#define DDRPHY_MR0_WR_Pos (9) /*!< DDRPHY_T::MR0: WR Position */ +#define DDRPHY_MR0_WR_Msk (0x7ul << DDRPHY_MR0_WR_Pos) /*!< DDRPHY_T::MR0: WR Mask */ + +#define DDRPHY_MR0_PD_Pos (12) /*!< DDRPHY_T::MR0: PD Position */ +#define DDRPHY_MR0_PD_Msk (0x1ul << DDRPHY_MR0_PD_Pos) /*!< DDRPHY_T::MR0: PD Mask */ + +#define DDRPHY_MR1_DE_Pos (0) /*!< DDRPHY_T::MR1: DE Position */ +#define DDRPHY_MR1_DE_Msk (0x1ul << DDRPHY_MR1_DE_Pos) /*!< DDRPHY_T::MR1: DE Mask */ + +#define DDRPHY_MR1_DIC0_Pos (1) /*!< DDRPHY_T::MR1: DIC0 Position */ +#define DDRPHY_MR1_DIC0_Msk (0x1ul << DDRPHY_MR1_DIC0_Pos) /*!< DDRPHY_T::MR1: DIC0 Mask */ + +#define DDRPHY_MR1_RTT0_Pos (2) /*!< DDRPHY_T::MR1: RTT0 Position */ +#define DDRPHY_MR1_RTT0_Msk (0x1ul << DDRPHY_MR1_RTT0_Pos) /*!< DDRPHY_T::MR1: RTT0 Mask */ + +#define DDRPHY_MR1_AL_Pos (3) /*!< DDRPHY_T::MR1: AL Position */ +#define DDRPHY_MR1_AL_Msk (0x3ul << DDRPHY_MR1_AL_Pos) /*!< DDRPHY_T::MR1: AL Mask */ + +#define DDRPHY_MR1_DIC1_Pos (5) /*!< DDRPHY_T::MR1: DIC1 Position */ +#define DDRPHY_MR1_DIC1_Msk (0x1ul << DDRPHY_MR1_DIC1_Pos) /*!< DDRPHY_T::MR1: DIC1 Mask */ + +#define DDRPHY_MR1_RTT1_Pos (6) /*!< DDRPHY_T::MR1: RTT1 Position */ +#define DDRPHY_MR1_RTT1_Msk (0x1ul << DDRPHY_MR1_RTT1_Pos) /*!< DDRPHY_T::MR1: RTT1 Mask */ + +#define DDRPHY_MR1_LEVEL_Pos (7) /*!< DDRPHY_T::MR1: LEVEL Position */ +#define DDRPHY_MR1_LEVEL_Msk (0x1ul << DDRPHY_MR1_LEVEL_Pos) /*!< DDRPHY_T::MR1: LEVEL Mask */ + +#define DDRPHY_MR1_RTT2_Pos (9) /*!< DDRPHY_T::MR1: RTT2 Position */ +#define DDRPHY_MR1_RTT2_Msk (0x1ul << DDRPHY_MR1_RTT2_Pos) /*!< DDRPHY_T::MR1: RTT2 Mask */ + +#define DDRPHY_MR1_TDQS_Pos (11) /*!< DDRPHY_T::MR1: TDQS Position */ +#define DDRPHY_MR1_TDQS_Msk (0x1ul << DDRPHY_MR1_TDQS_Pos) /*!< DDRPHY_T::MR1: TDQS Mask */ + +#define DDRPHY_MR1_QOFF_Pos (12) /*!< DDRPHY_T::MR1: QOFF Position */ +#define DDRPHY_MR1_QOFF_Msk (0x1ul << DDRPHY_MR1_QOFF_Pos) /*!< DDRPHY_T::MR1: QOFF Mask */ + +#define DDRPHY_MR2_PASR_Pos (0) /*!< DDRPHY_T::MR2: PASR Position */ +#define DDRPHY_MR2_PASR_Msk (0x7ul << DDRPHY_MR2_PASR_Pos) /*!< DDRPHY_T::MR2: PASR Mask */ + +#define DDRPHY_MR2_CWL_Pos (3) /*!< DDRPHY_T::MR2: CWL Position */ +#define DDRPHY_MR2_CWL_Msk (0x7ul << DDRPHY_MR2_CWL_Pos) /*!< DDRPHY_T::MR2: CWL Mask */ + +#define DDRPHY_MR2_ASR_Pos (6) /*!< DDRPHY_T::MR2: ASR Position */ +#define DDRPHY_MR2_ASR_Msk (0x1ul << DDRPHY_MR2_ASR_Pos) /*!< DDRPHY_T::MR2: ASR Mask */ + +#define DDRPHY_MR2_SRT_Pos (7) /*!< DDRPHY_T::MR2: SRT Position */ +#define DDRPHY_MR2_SRT_Msk (0x1ul << DDRPHY_MR2_SRT_Pos) /*!< DDRPHY_T::MR2: SRT Mask */ + +#define DDRPHY_MR2_RTTWR_Pos (9) /*!< DDRPHY_T::MR2: RTTWR Position */ +#define DDRPHY_MR2_RTTWR_Msk (0x3ul << DDRPHY_MR2_RTTWR_Pos) /*!< DDRPHY_T::MR2: RTTWR Mask */ + +#define DDRPHY_MR3_MPRLOC_Pos (0) /*!< DDRPHY_T::MR3: MPRLOC Position */ +#define DDRPHY_MR3_MPRLOC_Msk (0x3ul << DDRPHY_MR3_MPRLOC_Pos) /*!< DDRPHY_T::MR3: MPRLOC Mask */ + +#define DDRPHY_MR3_MPR_Pos (2) /*!< DDRPHY_T::MR3: MPR Position */ +#define DDRPHY_MR3_MPR_Msk (0x1ul << DDRPHY_MR3_MPR_Pos) /*!< DDRPHY_T::MR3: MPR Mask */ + +#define DDRPHY_ODTCR_RDODT0_Pos (0) /*!< DDRPHY_T::ODTCR: RDODT0 Position */ +#define DDRPHY_ODTCR_RDODT0_Msk (0xful << DDRPHY_ODTCR_RDODT0_Pos) /*!< DDRPHY_T::ODTCR: RDODT0 Mask */ + +#define DDRPHY_ODTCR_RDODT1_Pos (4) /*!< DDRPHY_T::ODTCR: RDODT1 Position */ +#define DDRPHY_ODTCR_RDODT1_Msk (0xful << DDRPHY_ODTCR_RDODT1_Pos) /*!< DDRPHY_T::ODTCR: RDODT1 Mask */ + +#define DDRPHY_ODTCR_RDODT2_Pos (8) /*!< DDRPHY_T::ODTCR: RDODT2 Position */ +#define DDRPHY_ODTCR_RDODT2_Msk (0xful << DDRPHY_ODTCR_RDODT2_Pos) /*!< DDRPHY_T::ODTCR: RDODT2 Mask */ + +#define DDRPHY_ODTCR_RDODT3_Pos (12) /*!< DDRPHY_T::ODTCR: RDODT3 Position */ +#define DDRPHY_ODTCR_RDODT3_Msk (0xful << DDRPHY_ODTCR_RDODT3_Pos) /*!< DDRPHY_T::ODTCR: RDODT3 Mask */ + +#define DDRPHY_ODTCR_WRODT0_Pos (16) /*!< DDRPHY_T::ODTCR: WRODT0 Position */ +#define DDRPHY_ODTCR_WRODT0_Msk (0xful << DDRPHY_ODTCR_WRODT0_Pos) /*!< DDRPHY_T::ODTCR: WRODT0 Mask */ + +#define DDRPHY_ODTCR_WRODT1_Pos (20) /*!< DDRPHY_T::ODTCR: WRODT1 Position */ +#define DDRPHY_ODTCR_WRODT1_Msk (0xful << DDRPHY_ODTCR_WRODT1_Pos) /*!< DDRPHY_T::ODTCR: WRODT1 Mask */ + +#define DDRPHY_ODTCR_WRODT2_Pos (24) /*!< DDRPHY_T::ODTCR: WRODT2 Position */ +#define DDRPHY_ODTCR_WRODT2_Msk (0xful << DDRPHY_ODTCR_WRODT2_Pos) /*!< DDRPHY_T::ODTCR: WRODT2 Mask */ + +#define DDRPHY_ODTCR_WRODT3_Pos (28) /*!< DDRPHY_T::ODTCR: WRODT3 Position */ +#define DDRPHY_ODTCR_WRODT3_Msk (0xful << DDRPHY_ODTCR_WRODT3_Pos) /*!< DDRPHY_T::ODTCR: WRODT3 Mask */ + +#define DDRPHY_DTCR_DTCOL_Pos (0) /*!< DDRPHY_T::DTCR: DTCOL Position */ +#define DDRPHY_DTCR_DTCOL_Msk (0xffful << DDRPHY_DTCR_DTCOL_Pos) /*!< DDRPHY_T::DTCR: DTCOL Mask */ + +#define DDRPHY_DTCR_DTROW_Pos (12) /*!< DDRPHY_T::DTCR: DTROW Position */ +#define DDRPHY_DTCR_DTROW_Msk (0xfffful << DDRPHY_DTCR_DTROW_Pos) /*!< DDRPHY_T::DTCR: DTROW Mask */ + +#define DDRPHY_DTCR_DTBANK_Pos (28) /*!< DDRPHY_T::DTCR: DTBANK Position */ +#define DDRPHY_DTCR_DTBANK_Msk (0x7ul << DDRPHY_DTCR_DTBANK_Pos) /*!< DDRPHY_T::DTCR: DTBANK Mask */ + +#define DDRPHY_DTAR1_DTCOL_Pos (0) /*!< DDRPHY_T::DTAR1: DTCOL Position */ +#define DDRPHY_DTAR1_DTCOL_Msk (0xffful << DDRPHY_DTAR1_DTCOL_Pos) /*!< DDRPHY_T::DTAR1: DTCOL Mask */ + +#define DDRPHY_DTAR1_DTROW_Pos (12) /*!< DDRPHY_T::DTAR1: DTROW Position */ +#define DDRPHY_DTAR1_DTROW_Msk (0xfffful << DDRPHY_DTAR1_DTROW_Pos) /*!< DDRPHY_T::DTAR1: DTROW Mask */ + +#define DDRPHY_DTAR1_DTBANK_Pos (28) /*!< DDRPHY_T::DTAR1: DTBANK Position */ +#define DDRPHY_DTAR1_DTBANK_Msk (0x7ul << DDRPHY_DTAR1_DTBANK_Pos) /*!< DDRPHY_T::DTAR1: DTBANK Mask */ + +#define DDRPHY_DTAR2_DTCOL_Pos (0) /*!< DDRPHY_T::DTAR2: DTCOL Position */ +#define DDRPHY_DTAR2_DTCOL_Msk (0xffful << DDRPHY_DTAR2_DTCOL_Pos) /*!< DDRPHY_T::DTAR2: DTCOL Mask */ + +#define DDRPHY_DTAR2_DTROW_Pos (12) /*!< DDRPHY_T::DTAR2: DTROW Position */ +#define DDRPHY_DTAR2_DTROW_Msk (0xfffful << DDRPHY_DTAR2_DTROW_Pos) /*!< DDRPHY_T::DTAR2: DTROW Mask */ + +#define DDRPHY_DTAR2_DTBANK_Pos (28) /*!< DDRPHY_T::DTAR2: DTBANK Position */ +#define DDRPHY_DTAR2_DTBANK_Msk (0x7ul << DDRPHY_DTAR2_DTBANK_Pos) /*!< DDRPHY_T::DTAR2: DTBANK Mask */ + +#define DDRPHY_DTAR3_DTCOL_Pos (0) /*!< DDRPHY_T::DTAR3: DTCOL Position */ +#define DDRPHY_DTAR3_DTCOL_Msk (0xffful << DDRPHY_DTAR3_DTCOL_Pos) /*!< DDRPHY_T::DTAR3: DTCOL Mask */ + +#define DDRPHY_DTAR3_DTROW_Pos (12) /*!< DDRPHY_T::DTAR3: DTROW Position */ +#define DDRPHY_DTAR3_DTROW_Msk (0xfffful << DDRPHY_DTAR3_DTROW_Pos) /*!< DDRPHY_T::DTAR3: DTROW Mask */ + +#define DDRPHY_DTAR3_DTBANK_Pos (28) /*!< DDRPHY_T::DTAR3: DTBANK Position */ +#define DDRPHY_DTAR3_DTBANK_Msk (0x7ul << DDRPHY_DTAR3_DTBANK_Pos) /*!< DDRPHY_T::DTAR3: DTBANK Mask */ + +#define DDRPHY_DTDR0_DTBYTE1_Pos (0) /*!< DDRPHY_T::DTDR0: DTBYTE1 Position */ +#define DDRPHY_DTDR0_DTBYTE1_Msk (0xfful << DDRPHY_DTDR0_DTBYTE1_Pos) /*!< DDRPHY_T::DTDR0: DTBYTE1 Mask */ + +#define DDRPHY_DTDR0_DTBYTE0_Pos (8) /*!< DDRPHY_T::DTDR0: DTBYTE0 Position */ +#define DDRPHY_DTDR0_DTBYTE0_Msk (0xfful << DDRPHY_DTDR0_DTBYTE0_Pos) /*!< DDRPHY_T::DTDR0: DTBYTE0 Mask */ + +#define DDRPHY_DTDR0_DTBYTE2_Pos (16) /*!< DDRPHY_T::DTDR0: DTBYTE2 Position */ +#define DDRPHY_DTDR0_DTBYTE2_Msk (0xfful << DDRPHY_DTDR0_DTBYTE2_Pos) /*!< DDRPHY_T::DTDR0: DTBYTE2 Mask */ + +#define DDRPHY_DTDR0_DTBYTE3_Pos (24) /*!< DDRPHY_T::DTDR0: DTBYTE3 Position */ +#define DDRPHY_DTDR0_DTBYTE3_Msk (0xfful << DDRPHY_DTDR0_DTBYTE3_Pos) /*!< DDRPHY_T::DTDR0: DTBYTE3 Mask */ + +#define DDRPHY_DTDR1_DTBYTE4_Pos (0) /*!< DDRPHY_T::DTDR1: DTBYTE4 Position */ +#define DDRPHY_DTDR1_DTBYTE4_Msk (0xfful << DDRPHY_DTDR1_DTBYTE4_Pos) /*!< DDRPHY_T::DTDR1: DTBYTE4 Mask */ + +#define DDRPHY_DTDR1_DTBYTE5_Pos (8) /*!< DDRPHY_T::DTDR1: DTBYTE5 Position */ +#define DDRPHY_DTDR1_DTBYTE5_Msk (0xfful << DDRPHY_DTDR1_DTBYTE5_Pos) /*!< DDRPHY_T::DTDR1: DTBYTE5 Mask */ + +#define DDRPHY_DTDR1_DTBYTE6_Pos (16) /*!< DDRPHY_T::DTDR1: DTBYTE6 Position */ +#define DDRPHY_DTDR1_DTBYTE6_Msk (0xfful << DDRPHY_DTDR1_DTBYTE6_Pos) /*!< DDRPHY_T::DTDR1: DTBYTE6 Mask */ + +#define DDRPHY_DTDR1_DTBYTE7_Pos (24) /*!< DDRPHY_T::DTDR1: DTBYTE7 Position */ +#define DDRPHY_DTDR1_DTBYTE7_Msk (0xfful << DDRPHY_DTDR1_DTBYTE7_Pos) /*!< DDRPHY_T::DTDR1: DTBYTE7 Mask */ + +#define DDRPHY_DTEDR0_DTWLMN_Pos (0) /*!< DDRPHY_T::DTEDR0: DTWLMN Position */ +#define DDRPHY_DTEDR0_DTWLMN_Msk (0xfful << DDRPHY_DTEDR0_DTWLMN_Pos) /*!< DDRPHY_T::DTEDR0: DTWLMN Mask */ + +#define DDRPHY_DTEDR0_DTWLMX_Pos (8) /*!< DDRPHY_T::DTEDR0: DTWLMX Position */ +#define DDRPHY_DTEDR0_DTWLMX_Msk (0xfful << DDRPHY_DTEDR0_DTWLMX_Pos) /*!< DDRPHY_T::DTEDR0: DTWLMX Mask */ + +#define DDRPHY_DTEDR0_DTWBMN_Pos (16) /*!< DDRPHY_T::DTEDR0: DTWBMN Position */ +#define DDRPHY_DTEDR0_DTWBMN_Msk (0xfful << DDRPHY_DTEDR0_DTWBMN_Pos) /*!< DDRPHY_T::DTEDR0: DTWBMN Mask */ + +#define DDRPHY_DTEDR0_DTWBMX_Pos (24) /*!< DDRPHY_T::DTEDR0: DTWBMX Position */ +#define DDRPHY_DTEDR0_DTWBMX_Msk (0xfful << DDRPHY_DTEDR0_DTWBMX_Pos) /*!< DDRPHY_T::DTEDR0: DTWBMX Mask */ + +#define DDRPHY_DTEDR1_DTRLMN_Pos (0) /*!< DDRPHY_T::DTEDR1: DTRLMN Position */ +#define DDRPHY_DTEDR1_DTRLMN_Msk (0xfful << DDRPHY_DTEDR1_DTRLMN_Pos) /*!< DDRPHY_T::DTEDR1: DTRLMN Mask */ + +#define DDRPHY_DTEDR1_DTRLMX_Pos (8) /*!< DDRPHY_T::DTEDR1: DTRLMX Position */ +#define DDRPHY_DTEDR1_DTRLMX_Msk (0xfful << DDRPHY_DTEDR1_DTRLMX_Pos) /*!< DDRPHY_T::DTEDR1: DTRLMX Mask */ + +#define DDRPHY_DTEDR1_DTRBMN_Pos (16) /*!< DDRPHY_T::DTEDR1: DTRBMN Position */ +#define DDRPHY_DTEDR1_DTRBMN_Msk (0xfful << DDRPHY_DTEDR1_DTRBMN_Pos) /*!< DDRPHY_T::DTEDR1: DTRBMN Mask */ + +#define DDRPHY_DTEDR1_DTRBMX_Pos (24) /*!< DDRPHY_T::DTEDR1: DTRBMX Position */ +#define DDRPHY_DTEDR1_DTRBMX_Msk (0xfful << DDRPHY_DTEDR1_DTRBMX_Pos) /*!< DDRPHY_T::DTEDR1: DTRBMX Mask */ + +#define DDRPHY_PGCR2_tREFPRD_Pos (0) /*!< DDRPHY_T::PGCR2: tREFPRD Position */ +#define DDRPHY_PGCR2_tREFPRD_Msk (0x3fffful << DDRPHY_PGCR2_tREFPRD_Pos) /*!< DDRPHY_T::PGCR2: tREFPRD Mask */ + +#define DDRPHY_PGCR2_NOBUB_Pos (18) /*!< DDRPHY_T::PGCR2: NOBUB Position */ +#define DDRPHY_PGCR2_NOBUB_Msk (0x1ul << DDRPHY_PGCR2_NOBUB_Pos) /*!< DDRPHY_T::PGCR2: NOBUB Mask */ + +#define DDRPHY_PGCR2_FXDLAT_Pos (19) /*!< DDRPHY_T::PGCR2: FXDLAT Position */ +#define DDRPHY_PGCR2_FXDLAT_Msk (0x1ul << DDRPHY_PGCR2_FXDLAT_Pos) /*!< DDRPHY_T::PGCR2: FXDLAT Mask */ + +#define DDRPHY_PGCR2_DTPMXTMR_Pos (20) /*!< DDRPHY_T::PGCR2: DTPMXTMR Position */ +#define DDRPHY_PGCR2_DTPMXTMR_Msk (0xfful << DDRPHY_PGCR2_DTPMXTMR_Pos) /*!< DDRPHY_T::PGCR2: DTPMXTMR Mask */ + +#define DDRPHY_PGCR2_SHRAC_Pos (28) /*!< DDRPHY_T::PGCR2: SHRAC Position */ +#define DDRPHY_PGCR2_SHRAC_Msk (0x1ul << DDRPHY_PGCR2_SHRAC_Pos) /*!< DDRPHY_T::PGCR2: SHRAC Mask */ + +#define DDRPHY_PGCR2_ACPDDC_Pos (29) /*!< DDRPHY_T::PGCR2: ACPDDC Position */ +#define DDRPHY_PGCR2_ACPDDC_Msk (0x1ul << DDRPHY_PGCR2_ACPDDC_Pos) /*!< DDRPHY_T::PGCR2: ACPDDC Mask */ + +#define DDRPHY_PGCR2_LPMSTRC0_Pos (30) /*!< DDRPHY_T::PGCR2: LPMSTRC0 Position */ +#define DDRPHY_PGCR2_LPMSTRC0_Msk (0x1ul << DDRPHY_PGCR2_LPMSTRC0_Pos) /*!< DDRPHY_T::PGCR2: LPMSTRC0 Mask */ + +#define DDRPHY_PGCR2_DYNACPDD_Pos (31) /*!< DDRPHY_T::PGCR2: DYNACPDD Position */ +#define DDRPHY_PGCR2_DYNACPDD_Msk (0x1ul << DDRPHY_PGCR2_DYNACPDD_Pos) /*!< DDRPHY_T::PGCR2: DYNACPDD Mask */ + +#define DDRPHY_RDIMMGCR0_RDIMM_Pos (0) /*!< DDRPHY_T::RDIMMGCR0: RDIMM Position */ +#define DDRPHY_RDIMMGCR0_RDIMM_Msk (0x1ul << DDRPHY_RDIMMGCR0_RDIMM_Pos) /*!< DDRPHY_T::RDIMMGCR0: RDIMM Mask */ + +#define DDRPHY_RDIMMGCR0_ERRNOREG_Pos (1) /*!< DDRPHY_T::RDIMMGCR0: ERRNOREG Position */ +#define DDRPHY_RDIMMGCR0_ERRNOREG_Msk (0x1ul << DDRPHY_RDIMMGCR0_ERRNOREG_Pos) /*!< DDRPHY_T::RDIMMGCR0: ERRNOREG Mask */ + +#define DDRPHY_RDIMMGCR0_SOPERR_Pos (2) /*!< DDRPHY_T::RDIMMGCR0: SOPERR Position */ +#define DDRPHY_RDIMMGCR0_SOPERR_Msk (0x1ul << DDRPHY_RDIMMGCR0_SOPERR_Pos) /*!< DDRPHY_T::RDIMMGCR0: SOPERR Mask */ + +#define DDRPHY_RDIMMGCR0_PARINODT_Pos (14) /*!< DDRPHY_T::RDIMMGCR0: PARINODT Position */ +#define DDRPHY_RDIMMGCR0_PARINODT_Msk (0x1ul << DDRPHY_RDIMMGCR0_PARINODT_Pos) /*!< DDRPHY_T::RDIMMGCR0: PARINODT Mask */ + +#define DDRPHY_RDIMMGCR0_PARINPDD_Pos (15) /*!< DDRPHY_T::RDIMMGCR0: PARINPDD Position */ +#define DDRPHY_RDIMMGCR0_PARINPDD_Msk (0x1ul << DDRPHY_RDIMMGCR0_PARINPDD_Pos) /*!< DDRPHY_T::RDIMMGCR0: PARINPDD Mask */ + +#define DDRPHY_RDIMMGCR0_PARINPDR_Pos (16) /*!< DDRPHY_T::RDIMMGCR0: PARINPDR Position */ +#define DDRPHY_RDIMMGCR0_PARINPDR_Msk (0x1ul << DDRPHY_RDIMMGCR0_PARINPDR_Pos) /*!< DDRPHY_T::RDIMMGCR0: PARINPDR Mask */ + +#define DDRPHY_RDIMMGCR0_PARINIOM_Pos (17) /*!< DDRPHY_T::RDIMMGCR0: PARINIOM Position */ +#define DDRPHY_RDIMMGCR0_PARINIOM_Msk (0x1ul << DDRPHY_RDIMMGCR0_PARINIOM_Pos) /*!< DDRPHY_T::RDIMMGCR0: PARINIOM Mask */ + +#define DDRPHY_RDIMMGCR0_PARINOE_Pos (18) /*!< DDRPHY_T::RDIMMGCR0: PARINOE Position */ +#define DDRPHY_RDIMMGCR0_PARINOE_Msk (0x1ul << DDRPHY_RDIMMGCR0_PARINOE_Pos) /*!< DDRPHY_T::RDIMMGCR0: PARINOE Mask */ + +#define DDRPHY_RDIMMGCR0_ERROUTODT_Pos (19) /*!< DDRPHY_T::RDIMMGCR0: ERROUTODT Position*/ +#define DDRPHY_RDIMMGCR0_ERROUTODT_Msk (0x1ul << DDRPHY_RDIMMGCR0_ERROUTODT_Pos) /*!< DDRPHY_T::RDIMMGCR0: ERROUTODT Mask */ + +#define DDRPHY_RDIMMGCR0_ERROUTPDD_Pos (20) /*!< DDRPHY_T::RDIMMGCR0: ERROUTPDD Position*/ +#define DDRPHY_RDIMMGCR0_ERROUTPDD_Msk (0x1ul << DDRPHY_RDIMMGCR0_ERROUTPDD_Pos) /*!< DDRPHY_T::RDIMMGCR0: ERROUTPDD Mask */ + +#define DDRPHY_RDIMMGCR0_ERROUTPDR_Pos (21) /*!< DDRPHY_T::RDIMMGCR0: ERROUTPDR Position*/ +#define DDRPHY_RDIMMGCR0_ERROUTPDR_Msk (0x1ul << DDRPHY_RDIMMGCR0_ERROUTPDR_Pos) /*!< DDRPHY_T::RDIMMGCR0: ERROUTPDR Mask */ + +#define DDRPHY_RDIMMGCR0_ERROUTIOM_Pos (22) /*!< DDRPHY_T::RDIMMGCR0: ERROUTIOM Position*/ +#define DDRPHY_RDIMMGCR0_ERROUTIOM_Msk (0x1ul << DDRPHY_RDIMMGCR0_ERROUTIOM_Pos) /*!< DDRPHY_T::RDIMMGCR0: ERROUTIOM Mask */ + +#define DDRPHY_RDIMMGCR0_ERROUTOE_Pos (23) /*!< DDRPHY_T::RDIMMGCR0: ERROUTOE Position */ +#define DDRPHY_RDIMMGCR0_ERROUTOE_Msk (0x1ul << DDRPHY_RDIMMGCR0_ERROUTOE_Pos) /*!< DDRPHY_T::RDIMMGCR0: ERROUTOE Mask */ + +#define DDRPHY_RDIMMGCR0_RDIMMODT_Pos (24) /*!< DDRPHY_T::RDIMMGCR0: RDIMMODT Position */ +#define DDRPHY_RDIMMGCR0_RDIMMODT_Msk (0x1ul << DDRPHY_RDIMMGCR0_RDIMMODT_Pos) /*!< DDRPHY_T::RDIMMGCR0: RDIMMODT Mask */ + +#define DDRPHY_RDIMMGCR0_RDIMMPDD_Pos (25) /*!< DDRPHY_T::RDIMMGCR0: RDIMMPDD Position */ +#define DDRPHY_RDIMMGCR0_RDIMMPDD_Msk (0x1ul << DDRPHY_RDIMMGCR0_RDIMMPDD_Pos) /*!< DDRPHY_T::RDIMMGCR0: RDIMMPDD Mask */ + +#define DDRPHY_RDIMMGCR0_RDIMMPDR_Pos (26) /*!< DDRPHY_T::RDIMMGCR0: RDIMMPDR Position */ +#define DDRPHY_RDIMMGCR0_RDIMMPDR_Msk (0x1ul << DDRPHY_RDIMMGCR0_RDIMMPDR_Pos) /*!< DDRPHY_T::RDIMMGCR0: RDIMMPDR Mask */ + +#define DDRPHY_RDIMMGCR0_RDIMMIOM_Pos (27) /*!< DDRPHY_T::RDIMMGCR0: RDIMMIOM Position */ +#define DDRPHY_RDIMMGCR0_RDIMMIOM_Msk (0x1ul << DDRPHY_RDIMMGCR0_RDIMMIOM_Pos) /*!< DDRPHY_T::RDIMMGCR0: RDIMMIOM Mask */ + +#define DDRPHY_RDIMMGCR0_QCSENOE_Pos (28) /*!< DDRPHY_T::RDIMMGCR0: QCSENOE Position */ +#define DDRPHY_RDIMMGCR0_QCSENOE_Msk (0x1ul << DDRPHY_RDIMMGCR0_QCSENOE_Pos) /*!< DDRPHY_T::RDIMMGCR0: QCSENOE Mask */ + +#define DDRPHY_RDIMMGCR0_MIRROROE_Pos (29) /*!< DDRPHY_T::RDIMMGCR0: MIRROROE Position */ +#define DDRPHY_RDIMMGCR0_MIRROROE_Msk (0x1ul << DDRPHY_RDIMMGCR0_MIRROROE_Pos) /*!< DDRPHY_T::RDIMMGCR0: MIRROROE Mask */ + +#define DDRPHY_RDIMMGCR0_QCSEN_Pos (30) /*!< DDRPHY_T::RDIMMGCR0: QCSEN Position */ +#define DDRPHY_RDIMMGCR0_QCSEN_Msk (0x1ul << DDRPHY_RDIMMGCR0_QCSEN_Pos) /*!< DDRPHY_T::RDIMMGCR0: QCSEN Mask */ + +#define DDRPHY_RDIMMGCR0_MIRROR_Pos (31) /*!< DDRPHY_T::RDIMMGCR0: MIRROR Position */ +#define DDRPHY_RDIMMGCR0_MIRROR_Msk (0x1ul << DDRPHY_RDIMMGCR0_MIRROR_Pos) /*!< DDRPHY_T::RDIMMGCR0: MIRROR Mask */ + +#define DDRPHY_RDIMMGCR1_tBCSTAB_Pos (0) /*!< DDRPHY_T::RDIMMGCR1: tBCSTAB Position */ +#define DDRPHY_RDIMMGCR1_tBCSTAB_Msk (0xffful << DDRPHY_RDIMMGCR1_tBCSTAB_Pos) /*!< DDRPHY_T::RDIMMGCR1: tBCSTAB Mask */ + +#define DDRPHY_RDIMMGCR1_tBCMRD_Pos (12) /*!< DDRPHY_T::RDIMMGCR1: tBCMRD Position */ +#define DDRPHY_RDIMMGCR1_tBCMRD_Msk (0x7ul << DDRPHY_RDIMMGCR1_tBCMRD_Pos) /*!< DDRPHY_T::RDIMMGCR1: tBCMRD Mask */ + +#define DDRPHY_RDIMMGCR1_CRINIT_Pos (16) /*!< DDRPHY_T::RDIMMGCR1: CRINIT Position */ +#define DDRPHY_RDIMMGCR1_CRINIT_Msk (0xfffful << DDRPHY_RDIMMGCR1_CRINIT_Pos) /*!< DDRPHY_T::RDIMMGCR1: CRINIT Mask */ + +#define DDRPHY_RDIMMCR0_RC0_Pos (0) /*!< DDRPHY_T::RDIMMCR0: RC0 Position */ +#define DDRPHY_RDIMMCR0_RC0_Msk (0xful << DDRPHY_RDIMMCR0_RC0_Pos) /*!< DDRPHY_T::RDIMMCR0: RC0 Mask */ + +#define DDRPHY_RDIMMCR0_RC1_Pos (4) /*!< DDRPHY_T::RDIMMCR0: RC1 Position */ +#define DDRPHY_RDIMMCR0_RC1_Msk (0xful << DDRPHY_RDIMMCR0_RC1_Pos) /*!< DDRPHY_T::RDIMMCR0: RC1 Mask */ + +#define DDRPHY_RDIMMCR0_RC2_Pos (8) /*!< DDRPHY_T::RDIMMCR0: RC2 Position */ +#define DDRPHY_RDIMMCR0_RC2_Msk (0xful << DDRPHY_RDIMMCR0_RC2_Pos) /*!< DDRPHY_T::RDIMMCR0: RC2 Mask */ + +#define DDRPHY_RDIMMCR0_RC3_Pos (12) /*!< DDRPHY_T::RDIMMCR0: RC3 Position */ +#define DDRPHY_RDIMMCR0_RC3_Msk (0xful << DDRPHY_RDIMMCR0_RC3_Pos) /*!< DDRPHY_T::RDIMMCR0: RC3 Mask */ + +#define DDRPHY_RDIMMCR0_RC4_Pos (16) /*!< DDRPHY_T::RDIMMCR0: RC4 Position */ +#define DDRPHY_RDIMMCR0_RC4_Msk (0xful << DDRPHY_RDIMMCR0_RC4_Pos) /*!< DDRPHY_T::RDIMMCR0: RC4 Mask */ + +#define DDRPHY_RDIMMCR0_RC5_Pos (20) /*!< DDRPHY_T::RDIMMCR0: RC5 Position */ +#define DDRPHY_RDIMMCR0_RC5_Msk (0xful << DDRPHY_RDIMMCR0_RC5_Pos) /*!< DDRPHY_T::RDIMMCR0: RC5 Mask */ + +#define DDRPHY_RDIMMCR0_RC6_Pos (24) /*!< DDRPHY_T::RDIMMCR0: RC6 Position */ +#define DDRPHY_RDIMMCR0_RC6_Msk (0xful << DDRPHY_RDIMMCR0_RC6_Pos) /*!< DDRPHY_T::RDIMMCR0: RC6 Mask */ + +#define DDRPHY_RDIMMCR0_RC7_Pos (28) /*!< DDRPHY_T::RDIMMCR0: RC7 Position */ +#define DDRPHY_RDIMMCR0_RC7_Msk (0xful << DDRPHY_RDIMMCR0_RC7_Pos) /*!< DDRPHY_T::RDIMMCR0: RC7 Mask */ + +#define DDRPHY_RDIMMCR1_RC8_Pos (0) /*!< DDRPHY_T::RDIMMCR1: RC8 Position */ +#define DDRPHY_RDIMMCR1_RC8_Msk (0xful << DDRPHY_RDIMMCR1_RC8_Pos) /*!< DDRPHY_T::RDIMMCR1: RC8 Mask */ + +#define DDRPHY_RDIMMCR1_RC9_Pos (4) /*!< DDRPHY_T::RDIMMCR1: RC9 Position */ +#define DDRPHY_RDIMMCR1_RC9_Msk (0xful << DDRPHY_RDIMMCR1_RC9_Pos) /*!< DDRPHY_T::RDIMMCR1: RC9 Mask */ + +#define DDRPHY_RDIMMCR1_RC10_Pos (8) /*!< DDRPHY_T::RDIMMCR1: RC10 Position */ +#define DDRPHY_RDIMMCR1_RC10_Msk (0xful << DDRPHY_RDIMMCR1_RC10_Pos) /*!< DDRPHY_T::RDIMMCR1: RC10 Mask */ + +#define DDRPHY_RDIMMCR1_RC11_Pos (12) /*!< DDRPHY_T::RDIMMCR1: RC11 Position */ +#define DDRPHY_RDIMMCR1_RC11_Msk (0xful << DDRPHY_RDIMMCR1_RC11_Pos) /*!< DDRPHY_T::RDIMMCR1: RC11 Mask */ + +#define DDRPHY_RDIMMCR1_RC12_Pos (16) /*!< DDRPHY_T::RDIMMCR1: RC12 Position */ +#define DDRPHY_RDIMMCR1_RC12_Msk (0xful << DDRPHY_RDIMMCR1_RC12_Pos) /*!< DDRPHY_T::RDIMMCR1: RC12 Mask */ + +#define DDRPHY_RDIMMCR1_RC13_Pos (20) /*!< DDRPHY_T::RDIMMCR1: RC13 Position */ +#define DDRPHY_RDIMMCR1_RC13_Msk (0xful << DDRPHY_RDIMMCR1_RC13_Pos) /*!< DDRPHY_T::RDIMMCR1: RC13 Mask */ + +#define DDRPHY_RDIMMCR1_RC14_Pos (24) /*!< DDRPHY_T::RDIMMCR1: RC14 Position */ +#define DDRPHY_RDIMMCR1_RC14_Msk (0xful << DDRPHY_RDIMMCR1_RC14_Pos) /*!< DDRPHY_T::RDIMMCR1: RC14 Mask */ + +#define DDRPHY_RDIMMCR1_RC15_Pos (28) /*!< DDRPHY_T::RDIMMCR1: RC15 Position */ +#define DDRPHY_RDIMMCR1_RC15_Msk (0xful << DDRPHY_RDIMMCR1_RC15_Pos) /*!< DDRPHY_T::RDIMMCR1: RC15 Mask */ + +#define DDRPHY_DCUAR_CWADDR_Pos (0) /*!< DDRPHY_T::DCUAR: CWADDR Position */ +#define DDRPHY_DCUAR_CWADDR_Msk (0xful << DDRPHY_DCUAR_CWADDR_Pos) /*!< DDRPHY_T::DCUAR: CWADDR Mask */ + +#define DDRPHY_DCUAR_CSADDR_Pos (4) /*!< DDRPHY_T::DCUAR: CSADDR Position */ +#define DDRPHY_DCUAR_CSADDR_Msk (0xful << DDRPHY_DCUAR_CSADDR_Pos) /*!< DDRPHY_T::DCUAR: CSADDR Mask */ + +#define DDRPHY_DCUAR_CSEL_Pos (8) /*!< DDRPHY_T::DCUAR: CSEL Position */ +#define DDRPHY_DCUAR_CSEL_Msk (0x3ul << DDRPHY_DCUAR_CSEL_Pos) /*!< DDRPHY_T::DCUAR: CSEL Mask */ + +#define DDRPHY_DCUAR_INCA_Pos (10) /*!< DDRPHY_T::DCUAR: INCA Position */ +#define DDRPHY_DCUAR_INCA_Msk (0x1ul << DDRPHY_DCUAR_INCA_Pos) /*!< DDRPHY_T::DCUAR: INCA Mask */ + +#define DDRPHY_DCUAR_ATYPE_Pos (11) /*!< DDRPHY_T::DCUAR: ATYPE Position */ +#define DDRPHY_DCUAR_ATYPE_Msk (0x1ul << DDRPHY_DCUAR_ATYPE_Pos) /*!< DDRPHY_T::DCUAR: ATYPE Mask */ + +#define DDRPHY_DCUDR_CDATA_Pos (0) /*!< DDRPHY_T::DCUDR: CDATA Position */ +#define DDRPHY_DCUDR_CDATA_Msk (0xfffffffful << DDRPHY_DCUDR_CDATA_Pos) /*!< DDRPHY_T::DCUDR: CDATA Mask */ + +#define DDRPHY_DCURR_DINST_Pos (0) /*!< DDRPHY_T::DCURR: DINST Position */ +#define DDRPHY_DCURR_DINST_Msk (0xful << DDRPHY_DCURR_DINST_Pos) /*!< DDRPHY_T::DCURR: DINST Mask */ + +#define DDRPHY_DCURR_SADDR_Pos (4) /*!< DDRPHY_T::DCURR: SADDR Position */ +#define DDRPHY_DCURR_SADDR_Msk (0xful << DDRPHY_DCURR_SADDR_Pos) /*!< DDRPHY_T::DCURR: SADDR Mask */ + +#define DDRPHY_DCURR_EADDR_Pos (8) /*!< DDRPHY_T::DCURR: EADDR Position */ +#define DDRPHY_DCURR_EADDR_Msk (0xful << DDRPHY_DCURR_EADDR_Pos) /*!< DDRPHY_T::DCURR: EADDR Mask */ + +#define DDRPHY_DCURR_NFAIL_Pos (12) /*!< DDRPHY_T::DCURR: NFAIL Position */ +#define DDRPHY_DCURR_NFAIL_Msk (0xfful << DDRPHY_DCURR_NFAIL_Pos) /*!< DDRPHY_T::DCURR: NFAIL Mask */ + +#define DDRPHY_DCURR_SONF_Pos (20) /*!< DDRPHY_T::DCURR: SONF Position */ +#define DDRPHY_DCURR_SONF_Msk (0x1ul << DDRPHY_DCURR_SONF_Pos) /*!< DDRPHY_T::DCURR: SONF Mask */ + +#define DDRPHY_DCURR_SCOF_Pos (21) /*!< DDRPHY_T::DCURR: SCOF Position */ +#define DDRPHY_DCURR_SCOF_Msk (0x1ul << DDRPHY_DCURR_SCOF_Pos) /*!< DDRPHY_T::DCURR: SCOF Mask */ + +#define DDRPHY_DCURR_RCEN_Pos (22) /*!< DDRPHY_T::DCURR: RCEN Position */ +#define DDRPHY_DCURR_RCEN_Msk (0x1ul << DDRPHY_DCURR_RCEN_Pos) /*!< DDRPHY_T::DCURR: RCEN Mask */ + +#define DDRPHY_DCURR_XCEN_Pos (23) /*!< DDRPHY_T::DCURR: XCEN Position */ +#define DDRPHY_DCURR_XCEN_Msk (0x1ul << DDRPHY_DCURR_XCEN_Pos) /*!< DDRPHY_T::DCURR: XCEN Mask */ + +#define DDRPHY_DCULR_LSADDR_Pos (0) /*!< DDRPHY_T::DCULR: LSADDR Position */ +#define DDRPHY_DCULR_LSADDR_Msk (0xful << DDRPHY_DCULR_LSADDR_Pos) /*!< DDRPHY_T::DCULR: LSADDR Mask */ + +#define DDRPHY_DCULR_LEADDR_Pos (4) /*!< DDRPHY_T::DCULR: LEADDR Position */ +#define DDRPHY_DCULR_LEADDR_Msk (0xful << DDRPHY_DCULR_LEADDR_Pos) /*!< DDRPHY_T::DCULR: LEADDR Mask */ + +#define DDRPHY_DCULR_LCNT_Pos (8) /*!< DDRPHY_T::DCULR: LCNT Position */ +#define DDRPHY_DCULR_LCNT_Msk (0xfful << DDRPHY_DCULR_LCNT_Pos) /*!< DDRPHY_T::DCULR: LCNT Mask */ + +#define DDRPHY_DCULR_LINF_Pos (16) /*!< DDRPHY_T::DCULR: LINF Position */ +#define DDRPHY_DCULR_LINF_Msk (0x1ul << DDRPHY_DCULR_LINF_Pos) /*!< DDRPHY_T::DCULR: LINF Mask */ + +#define DDRPHY_DCULR_IDA_Pos (17) /*!< DDRPHY_T::DCULR: IDA Position */ +#define DDRPHY_DCULR_IDA_Msk (0x1ul << DDRPHY_DCULR_IDA_Pos) /*!< DDRPHY_T::DCULR: IDA Mask */ + +#define DDRPHY_DCULR_XLEADDR_Pos (28) /*!< DDRPHY_T::DCULR: XLEADDR Position */ +#define DDRPHY_DCULR_XLEADDR_Msk (0xful << DDRPHY_DCULR_XLEADDR_Pos) /*!< DDRPHY_T::DCULR: XLEADDR Mask */ + +#define DDRPHY_DCUGCR_RCSW_Pos (0) /*!< DDRPHY_T::DCUGCR: RCSW Position */ +#define DDRPHY_DCUGCR_RCSW_Msk (0xfffful << DDRPHY_DCUGCR_RCSW_Pos) /*!< DDRPHY_T::DCUGCR: RCSW Mask */ + +#define DDRPHY_DCUTPR_tDCUT0_Pos (0) /*!< DDRPHY_T::DCUTPR: tDCUT0 Position */ +#define DDRPHY_DCUTPR_tDCUT0_Msk (0xfful << DDRPHY_DCUTPR_tDCUT0_Pos) /*!< DDRPHY_T::DCUTPR: tDCUT0 Mask */ + +#define DDRPHY_DCUTPR_tDCUT1_Pos (8) /*!< DDRPHY_T::DCUTPR: tDCUT1 Position */ +#define DDRPHY_DCUTPR_tDCUT1_Msk (0xfful << DDRPHY_DCUTPR_tDCUT1_Pos) /*!< DDRPHY_T::DCUTPR: tDCUT1 Mask */ + +#define DDRPHY_DCUTPR_tDCUT2_Pos (16) /*!< DDRPHY_T::DCUTPR: tDCUT2 Position */ +#define DDRPHY_DCUTPR_tDCUT2_Msk (0xfful << DDRPHY_DCUTPR_tDCUT2_Pos) /*!< DDRPHY_T::DCUTPR: tDCUT2 Mask */ + +#define DDRPHY_DCUTPR_tDCUT3_Pos (24) /*!< DDRPHY_T::DCUTPR: tDCUT3 Position */ +#define DDRPHY_DCUTPR_tDCUT3_Msk (0xfful << DDRPHY_DCUTPR_tDCUT3_Pos) /*!< DDRPHY_T::DCUTPR: tDCUT3 Mask */ + +#define DDRPHY_DCUSR0_RDONE_Pos (0) /*!< DDRPHY_T::DCUSR0: RDONE Position */ +#define DDRPHY_DCUSR0_RDONE_Msk (0x1ul << DDRPHY_DCUSR0_RDONE_Pos) /*!< DDRPHY_T::DCUSR0: RDONE Mask */ + +#define DDRPHY_DCUSR0_CFAIL_Pos (1) /*!< DDRPHY_T::DCUSR0: CFAIL Position */ +#define DDRPHY_DCUSR0_CFAIL_Msk (0x1ul << DDRPHY_DCUSR0_CFAIL_Pos) /*!< DDRPHY_T::DCUSR0: CFAIL Mask */ + +#define DDRPHY_DCUSR0_CFULL_Pos (2) /*!< DDRPHY_T::DCUSR0: CFULL Position */ +#define DDRPHY_DCUSR0_CFULL_Msk (0x1ul << DDRPHY_DCUSR0_CFULL_Pos) /*!< DDRPHY_T::DCUSR0: CFULL Mask */ + +#define DDRPHY_DCUSR1_RDCNT_Pos (0) /*!< DDRPHY_T::DCUSR1: RDCNT Position */ +#define DDRPHY_DCUSR1_RDCNT_Msk (0xfffful << DDRPHY_DCUSR1_RDCNT_Pos) /*!< DDRPHY_T::DCUSR1: RDCNT Mask */ + +#define DDRPHY_DCUSR1_FLCNT_Pos (16) /*!< DDRPHY_T::DCUSR1: FLCNT Position */ +#define DDRPHY_DCUSR1_FLCNT_Msk (0xfful << DDRPHY_DCUSR1_FLCNT_Pos) /*!< DDRPHY_T::DCUSR1: FLCNT Mask */ + +#define DDRPHY_DCUSR1_LPCNT_Pos (24) /*!< DDRPHY_T::DCUSR1: LPCNT Position */ +#define DDRPHY_DCUSR1_LPCNT_Msk (0xfful << DDRPHY_DCUSR1_LPCNT_Pos) /*!< DDRPHY_T::DCUSR1: LPCNT Mask */ + +#define DDRPHY_BISTRR_BINST_Pos (0) /*!< DDRPHY_T::BISTRR: BINST Position */ +#define DDRPHY_BISTRR_BINST_Msk (0x7ul << DDRPHY_BISTRR_BINST_Pos) /*!< DDRPHY_T::BISTRR: BINST Mask */ + +#define DDRPHY_BISTRR_BMODE_Pos (3) /*!< DDRPHY_T::BISTRR: BMODE Position */ +#define DDRPHY_BISTRR_BMODE_Msk (0x1ul << DDRPHY_BISTRR_BMODE_Pos) /*!< DDRPHY_T::BISTRR: BMODE Mask */ + +#define DDRPHY_BISTRR_BINF_Pos (4) /*!< DDRPHY_T::BISTRR: BINF Position */ +#define DDRPHY_BISTRR_BINF_Msk (0x1ul << DDRPHY_BISTRR_BINF_Pos) /*!< DDRPHY_T::BISTRR: BINF Mask */ + +#define DDRPHY_BISTRR_NFAIL_Pos (5) /*!< DDRPHY_T::BISTRR: NFAIL Position */ +#define DDRPHY_BISTRR_NFAIL_Msk (0xfful << DDRPHY_BISTRR_NFAIL_Pos) /*!< DDRPHY_T::BISTRR: NFAIL Mask */ + +#define DDRPHY_BISTRR_BSONF_Pos (13) /*!< DDRPHY_T::BISTRR: BSONF Position */ +#define DDRPHY_BISTRR_BSONF_Msk (0x1ul << DDRPHY_BISTRR_BSONF_Pos) /*!< DDRPHY_T::BISTRR: BSONF Mask */ + +#define DDRPHY_BISTRR_BDXEN_Pos (14) /*!< DDRPHY_T::BISTRR: BDXEN Position */ +#define DDRPHY_BISTRR_BDXEN_Msk (0x1ul << DDRPHY_BISTRR_BDXEN_Pos) /*!< DDRPHY_T::BISTRR: BDXEN Mask */ + +#define DDRPHY_BISTRR_BACEN_Pos (15) /*!< DDRPHY_T::BISTRR: BACEN Position */ +#define DDRPHY_BISTRR_BACEN_Msk (0x1ul << DDRPHY_BISTRR_BACEN_Pos) /*!< DDRPHY_T::BISTRR: BACEN Mask */ + +#define DDRPHY_BISTRR_BDMEN_Pos (16) /*!< DDRPHY_T::BISTRR: BDMEN Position */ +#define DDRPHY_BISTRR_BDMEN_Msk (0x1ul << DDRPHY_BISTRR_BDMEN_Pos) /*!< DDRPHY_T::BISTRR: BDMEN Mask */ + +#define DDRPHY_BISTRR_BDPAT_Pos (17) /*!< DDRPHY_T::BISTRR: BDPAT Position */ +#define DDRPHY_BISTRR_BDPAT_Msk (0x3ul << DDRPHY_BISTRR_BDPAT_Pos) /*!< DDRPHY_T::BISTRR: BDPAT Mask */ + +#define DDRPHY_BISTRR_BDXSEL_Pos (19) /*!< DDRPHY_T::BISTRR: BDXSEL Position */ +#define DDRPHY_BISTRR_BDXSEL_Msk (0xful << DDRPHY_BISTRR_BDXSEL_Pos) /*!< DDRPHY_T::BISTRR: BDXSEL Mask */ + +#define DDRPHY_BISTRR_BCKSEL_Pos (23) /*!< DDRPHY_T::BISTRR: BCKSEL Position */ +#define DDRPHY_BISTRR_BCKSEL_Msk (0x3ul << DDRPHY_BISTRR_BCKSEL_Pos) /*!< DDRPHY_T::BISTRR: BCKSEL Mask */ + +#define DDRPHY_BISTRR_BCCSEL_Pos (25) /*!< DDRPHY_T::BISTRR: BCCSEL Position */ +#define DDRPHY_BISTRR_BCCSEL_Msk (0x3ul << DDRPHY_BISTRR_BCCSEL_Pos) /*!< DDRPHY_T::BISTRR: BCCSEL Mask */ + +#define DDRPHY_BISTWCR_BWCNT_Pos (0) /*!< DDRPHY_T::BISTWCR: BWCNT Position */ +#define DDRPHY_BISTWCR_BWCNT_Msk (0xfffful << DDRPHY_BISTWCR_BWCNT_Pos) /*!< DDRPHY_T::BISTWCR: BWCNT Mask */ + +#define DDRPHY_BISTMSKR0_AMSK_Pos (0) /*!< DDRPHY_T::BISTMSKR0: AMSK Position */ +#define DDRPHY_BISTMSKR0_AMSK_Msk (0xfffful << DDRPHY_BISTMSKR0_AMSK_Pos) /*!< DDRPHY_T::BISTMSKR0: AMSK Mask */ + +#define DDRPHY_BISTMSKR0_BAMSK_Pos (16) /*!< DDRPHY_T::BISTMSKR0: BAMSK Position */ +#define DDRPHY_BISTMSKR0_BAMSK_Msk (0x7ul << DDRPHY_BISTMSKR0_BAMSK_Pos) /*!< DDRPHY_T::BISTMSKR0: BAMSK Mask */ + +#define DDRPHY_BISTMSKR0_WEMSK_Pos (19) /*!< DDRPHY_T::BISTMSKR0: WEMSK Position */ +#define DDRPHY_BISTMSKR0_WEMSK_Msk (0x1ul << DDRPHY_BISTMSKR0_WEMSK_Pos) /*!< DDRPHY_T::BISTMSKR0: WEMSK Mask */ + +#define DDRPHY_BISTMSKR0_CKEMSK_Pos (20) /*!< DDRPHY_T::BISTMSKR0: CKEMSK Position */ +#define DDRPHY_BISTMSKR0_CKEMSK_Msk (0xful << DDRPHY_BISTMSKR0_CKEMSK_Pos) /*!< DDRPHY_T::BISTMSKR0: CKEMSK Mask */ + +#define DDRPHY_BISTMSKR0_CSMSK_Pos (24) /*!< DDRPHY_T::BISTMSKR0: CSMSK Position */ +#define DDRPHY_BISTMSKR0_CSMSK_Msk (0xful << DDRPHY_BISTMSKR0_CSMSK_Pos) /*!< DDRPHY_T::BISTMSKR0: CSMSK Mask */ + +#define DDRPHY_BISTMSKR0_ODTMSK_Pos (28) /*!< DDRPHY_T::BISTMSKR0: ODTMSK Position */ +#define DDRPHY_BISTMSKR0_ODTMSK_Msk (0xful << DDRPHY_BISTMSKR0_ODTMSK_Pos) /*!< DDRPHY_T::BISTMSKR0: ODTMSK Mask */ + +#define DDRPHY_BISTMSKR1_RASMSK_Pos (0) /*!< DDRPHY_T::BISTMSKR1: RASMSK Position */ +#define DDRPHY_BISTMSKR1_RASMSK_Msk (0x1ul << DDRPHY_BISTMSKR1_RASMSK_Pos) /*!< DDRPHY_T::BISTMSKR1: RASMSK Mask */ + +#define DDRPHY_BISTMSKR1_CASMSK_Pos (1) /*!< DDRPHY_T::BISTMSKR1: CASMSK Position */ +#define DDRPHY_BISTMSKR1_CASMSK_Msk (0x1ul << DDRPHY_BISTMSKR1_CASMSK_Pos) /*!< DDRPHY_T::BISTMSKR1: CASMSK Mask */ + +#define DDRPHY_BISTMSKR1_PARMSK_Pos (27) /*!< DDRPHY_T::BISTMSKR1: PARMSK Position */ +#define DDRPHY_BISTMSKR1_PARMSK_Msk (0x1ul << DDRPHY_BISTMSKR1_PARMSK_Pos) /*!< DDRPHY_T::BISTMSKR1: PARMSK Mask */ + +#define DDRPHY_BISTMSKR1_DMMSK_Pos (28) /*!< DDRPHY_T::BISTMSKR1: DMMSK Position */ +#define DDRPHY_BISTMSKR1_DMMSK_Msk (0xful << DDRPHY_BISTMSKR1_DMMSK_Pos) /*!< DDRPHY_T::BISTMSKR1: DMMSK Mask */ + +#define DDRPHY_BISTMSKR2_DQMSK_Pos (0) /*!< DDRPHY_T::BISTMSKR2: DQMSK Position */ +#define DDRPHY_BISTMSKR2_DQMSK_Msk (0xfffffffful << DDRPHY_BISTMSKR2_DQMSK_Pos) /*!< DDRPHY_T::BISTMSKR2: DQMSK Mask */ + +#define DDRPHY_BISTLSR_SEED_Pos (0) /*!< DDRPHY_T::BISTLSR: SEED Position */ +#define DDRPHY_BISTLSR_SEED_Msk (0xfffffffful << DDRPHY_BISTLSR_SEED_Pos) /*!< DDRPHY_T::BISTLSR: SEED Mask */ + +#define DDRPHY_BISTAR0_BCOL_Pos (0) /*!< DDRPHY_T::BISTAR0: BCOL Position */ +#define DDRPHY_BISTAR0_BCOL_Msk (0xffful << DDRPHY_BISTAR0_BCOL_Pos) /*!< DDRPHY_T::BISTAR0: BCOL Mask */ + +#define DDRPHY_BISTAR0_BROW_Pos (12) /*!< DDRPHY_T::BISTAR0: BROW Position */ +#define DDRPHY_BISTAR0_BROW_Msk (0xfffful << DDRPHY_BISTAR0_BROW_Pos) /*!< DDRPHY_T::BISTAR0: BROW Mask */ + +#define DDRPHY_BISTAR0_BBANK_Pos (28) /*!< DDRPHY_T::BISTAR0: BBANK Position */ +#define DDRPHY_BISTAR0_BBANK_Msk (0x7ul << DDRPHY_BISTAR0_BBANK_Pos) /*!< DDRPHY_T::BISTAR0: BBANK Mask */ + +#define DDRPHY_BISTAR1_BRANK_Pos (0) /*!< DDRPHY_T::BISTAR1: BRANK Position */ +#define DDRPHY_BISTAR1_BRANK_Msk (0x3ul << DDRPHY_BISTAR1_BRANK_Pos) /*!< DDRPHY_T::BISTAR1: BRANK Mask */ + +#define DDRPHY_BISTAR1_BMRANK_Pos (2) /*!< DDRPHY_T::BISTAR1: BMRANK Position */ +#define DDRPHY_BISTAR1_BMRANK_Msk (0x3ul << DDRPHY_BISTAR1_BMRANK_Pos) /*!< DDRPHY_T::BISTAR1: BMRANK Mask */ + +#define DDRPHY_BISTAR1_BAINC_Pos (4) /*!< DDRPHY_T::BISTAR1: BAINC Position */ +#define DDRPHY_BISTAR1_BAINC_Msk (0xffful << DDRPHY_BISTAR1_BAINC_Pos) /*!< DDRPHY_T::BISTAR1: BAINC Mask */ + +#define DDRPHY_BISTAR2_BMCOL_Pos (0) /*!< DDRPHY_T::BISTAR2: BMCOL Position */ +#define DDRPHY_BISTAR2_BMCOL_Msk (0xffful << DDRPHY_BISTAR2_BMCOL_Pos) /*!< DDRPHY_T::BISTAR2: BMCOL Mask */ + +#define DDRPHY_BISTAR2_BMROW_Pos (12) /*!< DDRPHY_T::BISTAR2: BMROW Position */ +#define DDRPHY_BISTAR2_BMROW_Msk (0xfffful << DDRPHY_BISTAR2_BMROW_Pos) /*!< DDRPHY_T::BISTAR2: BMROW Mask */ + +#define DDRPHY_BISTAR2_BMBANK_Pos (28) /*!< DDRPHY_T::BISTAR2: BMBANK Position */ +#define DDRPHY_BISTAR2_BMBANK_Msk (0x7ul << DDRPHY_BISTAR2_BMBANK_Pos) /*!< DDRPHY_T::BISTAR2: BMBANK Mask */ + +#define DDRPHY_BISTUDPR_BUDP0_Pos (0) /*!< DDRPHY_T::BISTUDPR: BUDP0 Position */ +#define DDRPHY_BISTUDPR_BUDP0_Msk (0xfffful << DDRPHY_BISTUDPR_BUDP0_Pos) /*!< DDRPHY_T::BISTUDPR: BUDP0 Mask */ + +#define DDRPHY_BISTUDPR_BUDP1_Pos (16) /*!< DDRPHY_T::BISTUDPR: BUDP1 Position */ +#define DDRPHY_BISTUDPR_BUDP1_Msk (0xfffful << DDRPHY_BISTUDPR_BUDP1_Pos) /*!< DDRPHY_T::BISTUDPR: BUDP1 Mask */ + +#define DDRPHY_BISTGSR_BDONE_Pos (0) /*!< DDRPHY_T::BISTGSR: BDONE Position */ +#define DDRPHY_BISTGSR_BDONE_Msk (0x1ul << DDRPHY_BISTGSR_BDONE_Pos) /*!< DDRPHY_T::BISTGSR: BDONE Mask */ + +#define DDRPHY_BISTGSR_BACERR_Pos (1) /*!< DDRPHY_T::BISTGSR: BACERR Position */ +#define DDRPHY_BISTGSR_BACERR_Msk (0x1ul << DDRPHY_BISTGSR_BACERR_Pos) /*!< DDRPHY_T::BISTGSR: BACERR Mask */ + +#define DDRPHY_BISTGSR_BDXERR_Pos (2) /*!< DDRPHY_T::BISTGSR: BDXERR Position */ +#define DDRPHY_BISTGSR_BDXERR_Msk (0x1ul << DDRPHY_BISTGSR_BDXERR_Pos) /*!< DDRPHY_T::BISTGSR: BDXERR Mask */ + +#define DDRPHY_BISTGSR_PARBER_Pos (16) /*!< DDRPHY_T::BISTGSR: PARBER Position */ +#define DDRPHY_BISTGSR_PARBER_Msk (0x3ul << DDRPHY_BISTGSR_PARBER_Pos) /*!< DDRPHY_T::BISTGSR: PARBER Mask */ + +#define DDRPHY_BISTGSR_DMBER_Pos (20) /*!< DDRPHY_T::BISTGSR: DMBER Position */ +#define DDRPHY_BISTGSR_DMBER_Msk (0xfful << DDRPHY_BISTGSR_DMBER_Pos) /*!< DDRPHY_T::BISTGSR: DMBER Mask */ + +#define DDRPHY_BISTGSR_RASBER_Pos (28) /*!< DDRPHY_T::BISTGSR: RASBER Position */ +#define DDRPHY_BISTGSR_RASBER_Msk (0x3ul << DDRPHY_BISTGSR_RASBER_Pos) /*!< DDRPHY_T::BISTGSR: RASBER Mask */ + +#define DDRPHY_BISTGSR_CASBER_Pos (30) /*!< DDRPHY_T::BISTGSR: CASBER Position */ +#define DDRPHY_BISTGSR_CASBER_Msk (0x3ul << DDRPHY_BISTGSR_CASBER_Pos) /*!< DDRPHY_T::BISTGSR: CASBER Mask */ + +#define DDRPHY_BISTWER_ACWER_Pos (0) /*!< DDRPHY_T::BISTWER: ACWER Position */ +#define DDRPHY_BISTWER_ACWER_Msk (0xfffful << DDRPHY_BISTWER_ACWER_Pos) /*!< DDRPHY_T::BISTWER: ACWER Mask */ + +#define DDRPHY_BISTWER_DXWER_Pos (16) /*!< DDRPHY_T::BISTWER: DXWER Position */ +#define DDRPHY_BISTWER_DXWER_Msk (0xfffful << DDRPHY_BISTWER_DXWER_Pos) /*!< DDRPHY_T::BISTWER: DXWER Mask */ + +#define DDRPHY_BISTBER0_ABER_Pos (0) /*!< DDRPHY_T::BISTBER0: ABER Position */ +#define DDRPHY_BISTBER0_ABER_Msk (0xfffffffful << DDRPHY_BISTBER0_ABER_Pos) /*!< DDRPHY_T::BISTBER0: ABER Mask */ + +#define DDRPHY_BISTBER1_BABER_Pos (0) /*!< DDRPHY_T::BISTBER1: BABER Position */ +#define DDRPHY_BISTBER1_BABER_Msk (0x3ful << DDRPHY_BISTBER1_BABER_Pos) /*!< DDRPHY_T::BISTBER1: BABER Mask */ + +#define DDRPHY_BISTBER1_WEBER_Pos (6) /*!< DDRPHY_T::BISTBER1: WEBER Position */ +#define DDRPHY_BISTBER1_WEBER_Msk (0x3ul << DDRPHY_BISTBER1_WEBER_Pos) /*!< DDRPHY_T::BISTBER1: WEBER Mask */ + +#define DDRPHY_BISTBER1_CKEBER_Pos (8) /*!< DDRPHY_T::BISTBER1: CKEBER Position */ +#define DDRPHY_BISTBER1_CKEBER_Msk (0xfful << DDRPHY_BISTBER1_CKEBER_Pos) /*!< DDRPHY_T::BISTBER1: CKEBER Mask */ + +#define DDRPHY_BISTBER1_CSBER_Pos (16) /*!< DDRPHY_T::BISTBER1: CSBER Position */ +#define DDRPHY_BISTBER1_CSBER_Msk (0xfful << DDRPHY_BISTBER1_CSBER_Pos) /*!< DDRPHY_T::BISTBER1: CSBER Mask */ + +#define DDRPHY_BISTBER1_ODTBER_Pos (24) /*!< DDRPHY_T::BISTBER1: ODTBER Position */ +#define DDRPHY_BISTBER1_ODTBER_Msk (0xfful << DDRPHY_BISTBER1_ODTBER_Pos) /*!< DDRPHY_T::BISTBER1: ODTBER Mask */ + +#define DDRPHY_BISTBER2_DQBER0_Pos (0) /*!< DDRPHY_T::BISTBER2: DQBER0 Position */ +#define DDRPHY_BISTBER2_DQBER0_Msk (0xfffffffful << DDRPHY_BISTBER2_DQBER0_Pos) /*!< DDRPHY_T::BISTBER2: DQBER0 Mask */ + +#define DDRPHY_BISTBER3_DQBER1_Pos (0) /*!< DDRPHY_T::BISTBER3: DQBER1 Position */ +#define DDRPHY_BISTBER3_DQBER1_Msk (0xfffffffful << DDRPHY_BISTBER3_DQBER1_Pos) /*!< DDRPHY_T::BISTBER3: DQBER1 Mask */ + +#define DDRPHY_BISTWCSR_ACWCNT_Pos (0) /*!< DDRPHY_T::BISTWCSR: ACWCNT Position */ +#define DDRPHY_BISTWCSR_ACWCNT_Msk (0xfffful << DDRPHY_BISTWCSR_ACWCNT_Pos) /*!< DDRPHY_T::BISTWCSR: ACWCNT Mask */ + +#define DDRPHY_BISTWCSR_DXWCNT_Pos (16) /*!< DDRPHY_T::BISTWCSR: DXWCNT Position */ +#define DDRPHY_BISTWCSR_DXWCNT_Msk (0xfffful << DDRPHY_BISTWCSR_DXWCNT_Pos) /*!< DDRPHY_T::BISTWCSR: DXWCNT Mask */ + +#define DDRPHY_BISTFWR0_AWEBS_Pos (0) /*!< DDRPHY_T::BISTFWR0: AWEBS Position */ +#define DDRPHY_BISTFWR0_AWEBS_Msk (0xfffful << DDRPHY_BISTFWR0_AWEBS_Pos) /*!< DDRPHY_T::BISTFWR0: AWEBS Mask */ + +#define DDRPHY_BISTFWR0_BAWEBS_Pos (16) /*!< DDRPHY_T::BISTFWR0: BAWEBS Position */ +#define DDRPHY_BISTFWR0_BAWEBS_Msk (0x7ul << DDRPHY_BISTFWR0_BAWEBS_Pos) /*!< DDRPHY_T::BISTFWR0: BAWEBS Mask */ + +#define DDRPHY_BISTFWR0_WEWEBS_Pos (19) /*!< DDRPHY_T::BISTFWR0: WEWEBS Position */ +#define DDRPHY_BISTFWR0_WEWEBS_Msk (0x1ul << DDRPHY_BISTFWR0_WEWEBS_Pos) /*!< DDRPHY_T::BISTFWR0: WEWEBS Mask */ + +#define DDRPHY_BISTFWR0_CKEWEBS_Pos (20) /*!< DDRPHY_T::BISTFWR0: CKEWEBS Position */ +#define DDRPHY_BISTFWR0_CKEWEBS_Msk (0xful << DDRPHY_BISTFWR0_CKEWEBS_Pos) /*!< DDRPHY_T::BISTFWR0: CKEWEBS Mask */ + +#define DDRPHY_BISTFWR0_CSWEBS_Pos (24) /*!< DDRPHY_T::BISTFWR0: CSWEBS Position */ +#define DDRPHY_BISTFWR0_CSWEBS_Msk (0xful << DDRPHY_BISTFWR0_CSWEBS_Pos) /*!< DDRPHY_T::BISTFWR0: CSWEBS Mask */ + +#define DDRPHY_BISTFWR0_ODTWEBS_Pos (28) /*!< DDRPHY_T::BISTFWR0: ODTWEBS Position */ +#define DDRPHY_BISTFWR0_ODTWEBS_Msk (0xful << DDRPHY_BISTFWR0_ODTWEBS_Pos) /*!< DDRPHY_T::BISTFWR0: ODTWEBS Mask */ + +#define DDRPHY_BISTFWR1_RASWEBS_Pos (0) /*!< DDRPHY_T::BISTFWR1: RASWEBS Position */ +#define DDRPHY_BISTFWR1_RASWEBS_Msk (0x1ul << DDRPHY_BISTFWR1_RASWEBS_Pos) /*!< DDRPHY_T::BISTFWR1: RASWEBS Mask */ + +#define DDRPHY_BISTFWR1_CASWEBS_Pos (1) /*!< DDRPHY_T::BISTFWR1: CASWEBS Position */ +#define DDRPHY_BISTFWR1_CASWEBS_Msk (0x1ul << DDRPHY_BISTFWR1_CASWEBS_Pos) /*!< DDRPHY_T::BISTFWR1: CASWEBS Mask */ + +#define DDRPHY_BISTFWR1_PARWEBS_Pos (26) /*!< DDRPHY_T::BISTFWR1: PARWEBS Position */ +#define DDRPHY_BISTFWR1_PARWEBS_Msk (0x1ul << DDRPHY_BISTFWR1_PARWEBS_Pos) /*!< DDRPHY_T::BISTFWR1: PARWEBS Mask */ + +#define DDRPHY_BISTFWR1_DMWEBS_Pos (28) /*!< DDRPHY_T::BISTFWR1: DMWEBS Position */ +#define DDRPHY_BISTFWR1_DMWEBS_Msk (0xful << DDRPHY_BISTFWR1_DMWEBS_Pos) /*!< DDRPHY_T::BISTFWR1: DMWEBS Mask */ + +#define DDRPHY_BISTFWR2_DQWEBS_Pos (0) /*!< DDRPHY_T::BISTFWR2: DQWEBS Position */ +#define DDRPHY_BISTFWR2_DQWEBS_Msk (0xfffffffful << DDRPHY_BISTFWR2_DQWEBS_Pos) /*!< DDRPHY_T::BISTFWR2: DQWEBS Mask */ + +#define DDRPHY_AACR_AATR_Pos (0) /*!< DDRPHY_T::AACR: AATR Position */ +#define DDRPHY_AACR_AATR_Msk (0x3ffffffful << DDRPHY_AACR_AATR_Pos) /*!< DDRPHY_T::AACR: AATR Mask */ + +#define DDRPHY_AACR_AAENC_Pos (30) /*!< DDRPHY_T::AACR: AAENC Position */ +#define DDRPHY_AACR_AAENC_Msk (0x1ul << DDRPHY_AACR_AAENC_Pos) /*!< DDRPHY_T::AACR: AAENC Mask */ + +#define DDRPHY_AACR_AAOENC_Pos (31) /*!< DDRPHY_T::AACR: AAOENC Position */ +#define DDRPHY_AACR_AAOENC_Msk (0x1ul << DDRPHY_AACR_AAOENC_Pos) /*!< DDRPHY_T::AACR: AAOENC Mask */ + +#define DDRPHY_GPR0_GPR0_Pos (0) /*!< DDRPHY_T::GPR0: GPR0 Position */ +#define DDRPHY_GPR0_GPR0_Msk (0xfffffffful << DDRPHY_GPR0_GPR0_Pos) /*!< DDRPHY_T::GPR0: GPR0 Mask */ + +#define DDRPHY_GPR1_GPR1_Pos (0) /*!< DDRPHY_T::GPR1: GPR1 Position */ +#define DDRPHY_GPR1_GPR1_Msk (0xfffffffful << DDRPHY_GPR1_GPR1_Pos) /*!< DDRPHY_T::GPR1: GPR1 Mask */ + +#define DDRPHY_ZQ0CR0_ZDATA_Pos (0) /*!< DDRPHY_T::ZQ0CR0: ZDATA Position */ +#define DDRPHY_ZQ0CR0_ZDATA_Msk (0xffffffful << DDRPHY_ZQ0CR0_ZDATA_Pos) /*!< DDRPHY_T::ZQ0CR0: ZDATA Mask */ + +#define DDRPHY_ZQ0CR0_ZDEN_Pos (28) /*!< DDRPHY_T::ZQ0CR0: ZDEN Position */ +#define DDRPHY_ZQ0CR0_ZDEN_Msk (0x1ul << DDRPHY_ZQ0CR0_ZDEN_Pos) /*!< DDRPHY_T::ZQ0CR0: ZDEN Mask */ + +#define DDRPHY_ZQ0CR0_ZCALBYP_Pos (29) /*!< DDRPHY_T::ZQ0CR0: ZCALBYP Position */ +#define DDRPHY_ZQ0CR0_ZCALBYP_Msk (0x1ul << DDRPHY_ZQ0CR0_ZCALBYP_Pos) /*!< DDRPHY_T::ZQ0CR0: ZCALBYP Mask */ + +#define DDRPHY_ZQ0CR0_ZCALEN_Pos (30) /*!< DDRPHY_T::ZQ0CR0: ZCALEN Position */ +#define DDRPHY_ZQ0CR0_ZCALEN_Msk (0x1ul << DDRPHY_ZQ0CR0_ZCALEN_Pos) /*!< DDRPHY_T::ZQ0CR0: ZCALEN Mask */ + +#define DDRPHY_ZQ0CR0_ZQPD_Pos (31) /*!< DDRPHY_T::ZQ0CR0: ZQPD Position */ +#define DDRPHY_ZQ0CR0_ZQPD_Msk (0x1ul << DDRPHY_ZQ0CR0_ZQPD_Pos) /*!< DDRPHY_T::ZQ0CR0: ZQPD Mask */ + +#define DDRPHY_ZQ0CR1_ZPROG_Pos (0) /*!< DDRPHY_T::ZQ0CR1: ZPROG Position */ +#define DDRPHY_ZQ0CR1_ZPROG_Msk (0xfful << DDRPHY_ZQ0CR1_ZPROG_Pos) /*!< DDRPHY_T::ZQ0CR1: ZPROG Mask */ + +#define DDRPHY_ZQ0CR1_DFICU0_Pos (12) /*!< DDRPHY_T::ZQ0CR1: DFICU0 Position */ +#define DDRPHY_ZQ0CR1_DFICU0_Msk (0x1ul << DDRPHY_ZQ0CR1_DFICU0_Pos) /*!< DDRPHY_T::ZQ0CR1: DFICU0 Mask */ + +#define DDRPHY_ZQ0CR1_DFICU1_Pos (13) /*!< DDRPHY_T::ZQ0CR1: DFICU1 Position */ +#define DDRPHY_ZQ0CR1_DFICU1_Msk (0x1ul << DDRPHY_ZQ0CR1_DFICU1_Pos) /*!< DDRPHY_T::ZQ0CR1: DFICU1 Mask */ + +#define DDRPHY_ZQ0CR1_DFICCU_Pos (14) /*!< DDRPHY_T::ZQ0CR1: DFICCU Position */ +#define DDRPHY_ZQ0CR1_DFICCU_Msk (0x1ul << DDRPHY_ZQ0CR1_DFICCU_Pos) /*!< DDRPHY_T::ZQ0CR1: DFICCU Mask */ + +#define DDRPHY_ZQ0CR1_DFIPU0_Pos (16) /*!< DDRPHY_T::ZQ0CR1: DFIPU0 Position */ +#define DDRPHY_ZQ0CR1_DFIPU0_Msk (0x1ul << DDRPHY_ZQ0CR1_DFIPU0_Pos) /*!< DDRPHY_T::ZQ0CR1: DFIPU0 Mask */ + +#define DDRPHY_ZQ0CR1_DFIPU1_Pos (17) /*!< DDRPHY_T::ZQ0CR1: DFIPU1 Position */ +#define DDRPHY_ZQ0CR1_DFIPU1_Msk (0x1ul << DDRPHY_ZQ0CR1_DFIPU1_Pos) /*!< DDRPHY_T::ZQ0CR1: DFIPU1 Mask */ + +#define DDRPHY_ZQ0SR0_ZCTRL_Pos (0) /*!< DDRPHY_T::ZQ0SR0: ZCTRL Position */ +#define DDRPHY_ZQ0SR0_ZCTRL_Msk (0xffffffful << DDRPHY_ZQ0SR0_ZCTRL_Pos) /*!< DDRPHY_T::ZQ0SR0: ZCTRL Mask */ + +#define DDRPHY_ZQ0SR0_ZERR_Pos (30) /*!< DDRPHY_T::ZQ0SR0: ZERR Position */ +#define DDRPHY_ZQ0SR0_ZERR_Msk (0x1ul << DDRPHY_ZQ0SR0_ZERR_Pos) /*!< DDRPHY_T::ZQ0SR0: ZERR Mask */ + +#define DDRPHY_ZQ0SR0_ZDONE_Pos (31) /*!< DDRPHY_T::ZQ0SR0: ZDONE Position */ +#define DDRPHY_ZQ0SR0_ZDONE_Msk (0x1ul << DDRPHY_ZQ0SR0_ZDONE_Pos) /*!< DDRPHY_T::ZQ0SR0: ZDONE Mask */ + +#define DDRPHY_ZQ0SR1_ZPD_Pos (0) /*!< DDRPHY_T::ZQ0SR1: ZPD Position */ +#define DDRPHY_ZQ0SR1_ZPD_Msk (0x3ul << DDRPHY_ZQ0SR1_ZPD_Pos) /*!< DDRPHY_T::ZQ0SR1: ZPD Mask */ + +#define DDRPHY_ZQ0SR1_ZPU_Pos (2) /*!< DDRPHY_T::ZQ0SR1: ZPU Position */ +#define DDRPHY_ZQ0SR1_ZPU_Msk (0x3ul << DDRPHY_ZQ0SR1_ZPU_Pos) /*!< DDRPHY_T::ZQ0SR1: ZPU Mask */ + +#define DDRPHY_ZQ0SR1_OPD_Pos (4) /*!< DDRPHY_T::ZQ0SR1: OPD Position */ +#define DDRPHY_ZQ0SR1_OPD_Msk (0x3ul << DDRPHY_ZQ0SR1_OPD_Pos) /*!< DDRPHY_T::ZQ0SR1: OPD Mask */ + +#define DDRPHY_ZQ0SR1_OPU_Pos (6) /*!< DDRPHY_T::ZQ0SR1: OPU Position */ +#define DDRPHY_ZQ0SR1_OPU_Msk (0x3ul << DDRPHY_ZQ0SR1_OPU_Pos) /*!< DDRPHY_T::ZQ0SR1: OPU Mask */ + +#define DDRPHY_ZQ1CR0_ZDATA_Pos (0) /*!< DDRPHY_T::ZQ1CR0: ZDATA Position */ +#define DDRPHY_ZQ1CR0_ZDATA_Msk (0xffffffful << DDRPHY_ZQ1CR0_ZDATA_Pos) /*!< DDRPHY_T::ZQ1CR0: ZDATA Mask */ + +#define DDRPHY_ZQ1CR0_ZDEN_Pos (28) /*!< DDRPHY_T::ZQ1CR0: ZDEN Position */ +#define DDRPHY_ZQ1CR0_ZDEN_Msk (0x1ul << DDRPHY_ZQ1CR0_ZDEN_Pos) /*!< DDRPHY_T::ZQ1CR0: ZDEN Mask */ + +#define DDRPHY_ZQ1CR0_ZCALBYP_Pos (29) /*!< DDRPHY_T::ZQ1CR0: ZCALBYP Position */ +#define DDRPHY_ZQ1CR0_ZCALBYP_Msk (0x1ul << DDRPHY_ZQ1CR0_ZCALBYP_Pos) /*!< DDRPHY_T::ZQ1CR0: ZCALBYP Mask */ + +#define DDRPHY_ZQ1CR0_ZCALEN_Pos (30) /*!< DDRPHY_T::ZQ1CR0: ZCALEN Position */ +#define DDRPHY_ZQ1CR0_ZCALEN_Msk (0x1ul << DDRPHY_ZQ1CR0_ZCALEN_Pos) /*!< DDRPHY_T::ZQ1CR0: ZCALEN Mask */ + +#define DDRPHY_ZQ1CR0_ZQPD_Pos (31) /*!< DDRPHY_T::ZQ1CR0: ZQPD Position */ +#define DDRPHY_ZQ1CR0_ZQPD_Msk (0x1ul << DDRPHY_ZQ1CR0_ZQPD_Pos) /*!< DDRPHY_T::ZQ1CR0: ZQPD Mask */ + +#define DDRPHY_ZQ1CR1_ZPROG_Pos (0) /*!< DDRPHY_T::ZQ1CR1: ZPROG Position */ +#define DDRPHY_ZQ1CR1_ZPROG_Msk (0xfful << DDRPHY_ZQ1CR1_ZPROG_Pos) /*!< DDRPHY_T::ZQ1CR1: ZPROG Mask */ + +#define DDRPHY_ZQ1CR1_DFICU0_Pos (12) /*!< DDRPHY_T::ZQ1CR1: DFICU0 Position */ +#define DDRPHY_ZQ1CR1_DFICU0_Msk (0x1ul << DDRPHY_ZQ1CR1_DFICU0_Pos) /*!< DDRPHY_T::ZQ1CR1: DFICU0 Mask */ + +#define DDRPHY_ZQ1CR1_DFICU1_Pos (13) /*!< DDRPHY_T::ZQ1CR1: DFICU1 Position */ +#define DDRPHY_ZQ1CR1_DFICU1_Msk (0x1ul << DDRPHY_ZQ1CR1_DFICU1_Pos) /*!< DDRPHY_T::ZQ1CR1: DFICU1 Mask */ + +#define DDRPHY_ZQ1CR1_DFICCU_Pos (14) /*!< DDRPHY_T::ZQ1CR1: DFICCU Position */ +#define DDRPHY_ZQ1CR1_DFICCU_Msk (0x1ul << DDRPHY_ZQ1CR1_DFICCU_Pos) /*!< DDRPHY_T::ZQ1CR1: DFICCU Mask */ + +#define DDRPHY_ZQ1CR1_DFIPU0_Pos (16) /*!< DDRPHY_T::ZQ1CR1: DFIPU0 Position */ +#define DDRPHY_ZQ1CR1_DFIPU0_Msk (0x1ul << DDRPHY_ZQ1CR1_DFIPU0_Pos) /*!< DDRPHY_T::ZQ1CR1: DFIPU0 Mask */ + +#define DDRPHY_ZQ1CR1_DFIPU1_Pos (17) /*!< DDRPHY_T::ZQ1CR1: DFIPU1 Position */ +#define DDRPHY_ZQ1CR1_DFIPU1_Msk (0x1ul << DDRPHY_ZQ1CR1_DFIPU1_Pos) /*!< DDRPHY_T::ZQ1CR1: DFIPU1 Mask */ + +#define DDRPHY_ZQ1SR0_ZCTRL_Pos (0) /*!< DDRPHY_T::ZQ1SR0: ZCTRL Position */ +#define DDRPHY_ZQ1SR0_ZCTRL_Msk (0xffffffful << DDRPHY_ZQ1SR0_ZCTRL_Pos) /*!< DDRPHY_T::ZQ1SR0: ZCTRL Mask */ + +#define DDRPHY_ZQ1SR0_ZERR_Pos (30) /*!< DDRPHY_T::ZQ1SR0: ZERR Position */ +#define DDRPHY_ZQ1SR0_ZERR_Msk (0x1ul << DDRPHY_ZQ1SR0_ZERR_Pos) /*!< DDRPHY_T::ZQ1SR0: ZERR Mask */ + +#define DDRPHY_ZQ1SR0_ZDONE_Pos (31) /*!< DDRPHY_T::ZQ1SR0: ZDONE Position */ +#define DDRPHY_ZQ1SR0_ZDONE_Msk (0x1ul << DDRPHY_ZQ1SR0_ZDONE_Pos) /*!< DDRPHY_T::ZQ1SR0: ZDONE Mask */ + +#define DDRPHY_ZQ1SR1_ZPD_Pos (0) /*!< DDRPHY_T::ZQ1SR1: ZPD Position */ +#define DDRPHY_ZQ1SR1_ZPD_Msk (0x3ul << DDRPHY_ZQ1SR1_ZPD_Pos) /*!< DDRPHY_T::ZQ1SR1: ZPD Mask */ + +#define DDRPHY_ZQ1SR1_ZPU_Pos (2) /*!< DDRPHY_T::ZQ1SR1: ZPU Position */ +#define DDRPHY_ZQ1SR1_ZPU_Msk (0x3ul << DDRPHY_ZQ1SR1_ZPU_Pos) /*!< DDRPHY_T::ZQ1SR1: ZPU Mask */ + +#define DDRPHY_ZQ1SR1_OPD_Pos (4) /*!< DDRPHY_T::ZQ1SR1: OPD Position */ +#define DDRPHY_ZQ1SR1_OPD_Msk (0x3ul << DDRPHY_ZQ1SR1_OPD_Pos) /*!< DDRPHY_T::ZQ1SR1: OPD Mask */ + +#define DDRPHY_ZQ1SR1_OPU_Pos (6) /*!< DDRPHY_T::ZQ1SR1: OPU Position */ +#define DDRPHY_ZQ1SR1_OPU_Msk (0x3ul << DDRPHY_ZQ1SR1_OPU_Pos) /*!< DDRPHY_T::ZQ1SR1: OPU Mask */ + +#define DDRPHY_ZQ2CR0_ZDATA_Pos (0) /*!< DDRPHY_T::ZQ2CR0: ZDATA Position */ +#define DDRPHY_ZQ2CR0_ZDATA_Msk (0xffffffful << DDRPHY_ZQ2CR0_ZDATA_Pos) /*!< DDRPHY_T::ZQ2CR0: ZDATA Mask */ + +#define DDRPHY_ZQ2CR0_ZDEN_Pos (28) /*!< DDRPHY_T::ZQ2CR0: ZDEN Position */ +#define DDRPHY_ZQ2CR0_ZDEN_Msk (0x1ul << DDRPHY_ZQ2CR0_ZDEN_Pos) /*!< DDRPHY_T::ZQ2CR0: ZDEN Mask */ + +#define DDRPHY_ZQ2CR0_ZCALBYP_Pos (29) /*!< DDRPHY_T::ZQ2CR0: ZCALBYP Position */ +#define DDRPHY_ZQ2CR0_ZCALBYP_Msk (0x1ul << DDRPHY_ZQ2CR0_ZCALBYP_Pos) /*!< DDRPHY_T::ZQ2CR0: ZCALBYP Mask */ + +#define DDRPHY_ZQ2CR0_ZCALEN_Pos (30) /*!< DDRPHY_T::ZQ2CR0: ZCALEN Position */ +#define DDRPHY_ZQ2CR0_ZCALEN_Msk (0x1ul << DDRPHY_ZQ2CR0_ZCALEN_Pos) /*!< DDRPHY_T::ZQ2CR0: ZCALEN Mask */ + +#define DDRPHY_ZQ2CR0_ZQPD_Pos (31) /*!< DDRPHY_T::ZQ2CR0: ZQPD Position */ +#define DDRPHY_ZQ2CR0_ZQPD_Msk (0x1ul << DDRPHY_ZQ2CR0_ZQPD_Pos) /*!< DDRPHY_T::ZQ2CR0: ZQPD Mask */ + +#define DDRPHY_ZQ2CR1_ZPROG_Pos (0) /*!< DDRPHY_T::ZQ2CR1: ZPROG Position */ +#define DDRPHY_ZQ2CR1_ZPROG_Msk (0xfful << DDRPHY_ZQ2CR1_ZPROG_Pos) /*!< DDRPHY_T::ZQ2CR1: ZPROG Mask */ + +#define DDRPHY_ZQ2CR1_DFICU0_Pos (12) /*!< DDRPHY_T::ZQ2CR1: DFICU0 Position */ +#define DDRPHY_ZQ2CR1_DFICU0_Msk (0x1ul << DDRPHY_ZQ2CR1_DFICU0_Pos) /*!< DDRPHY_T::ZQ2CR1: DFICU0 Mask */ + +#define DDRPHY_ZQ2CR1_DFICU1_Pos (13) /*!< DDRPHY_T::ZQ2CR1: DFICU1 Position */ +#define DDRPHY_ZQ2CR1_DFICU1_Msk (0x1ul << DDRPHY_ZQ2CR1_DFICU1_Pos) /*!< DDRPHY_T::ZQ2CR1: DFICU1 Mask */ + +#define DDRPHY_ZQ2CR1_DFICCU_Pos (14) /*!< DDRPHY_T::ZQ2CR1: DFICCU Position */ +#define DDRPHY_ZQ2CR1_DFICCU_Msk (0x1ul << DDRPHY_ZQ2CR1_DFICCU_Pos) /*!< DDRPHY_T::ZQ2CR1: DFICCU Mask */ + +#define DDRPHY_ZQ2CR1_DFIPU0_Pos (16) /*!< DDRPHY_T::ZQ2CR1: DFIPU0 Position */ +#define DDRPHY_ZQ2CR1_DFIPU0_Msk (0x1ul << DDRPHY_ZQ2CR1_DFIPU0_Pos) /*!< DDRPHY_T::ZQ2CR1: DFIPU0 Mask */ + +#define DDRPHY_ZQ2CR1_DFIPU1_Pos (17) /*!< DDRPHY_T::ZQ2CR1: DFIPU1 Position */ +#define DDRPHY_ZQ2CR1_DFIPU1_Msk (0x1ul << DDRPHY_ZQ2CR1_DFIPU1_Pos) /*!< DDRPHY_T::ZQ2CR1: DFIPU1 Mask */ + +#define DDRPHY_ZQ2SR0_ZCTRL_Pos (0) /*!< DDRPHY_T::ZQ2SR0: ZCTRL Position */ +#define DDRPHY_ZQ2SR0_ZCTRL_Msk (0xffffffful << DDRPHY_ZQ2SR0_ZCTRL_Pos) /*!< DDRPHY_T::ZQ2SR0: ZCTRL Mask */ + +#define DDRPHY_ZQ2SR0_ZERR_Pos (30) /*!< DDRPHY_T::ZQ2SR0: ZERR Position */ +#define DDRPHY_ZQ2SR0_ZERR_Msk (0x1ul << DDRPHY_ZQ2SR0_ZERR_Pos) /*!< DDRPHY_T::ZQ2SR0: ZERR Mask */ + +#define DDRPHY_ZQ2SR0_ZDONE_Pos (31) /*!< DDRPHY_T::ZQ2SR0: ZDONE Position */ +#define DDRPHY_ZQ2SR0_ZDONE_Msk (0x1ul << DDRPHY_ZQ2SR0_ZDONE_Pos) /*!< DDRPHY_T::ZQ2SR0: ZDONE Mask */ + +#define DDRPHY_ZQ2SR1_ZPD_Pos (0) /*!< DDRPHY_T::ZQ2SR1: ZPD Position */ +#define DDRPHY_ZQ2SR1_ZPD_Msk (0x3ul << DDRPHY_ZQ2SR1_ZPD_Pos) /*!< DDRPHY_T::ZQ2SR1: ZPD Mask */ + +#define DDRPHY_ZQ2SR1_ZPU_Pos (2) /*!< DDRPHY_T::ZQ2SR1: ZPU Position */ +#define DDRPHY_ZQ2SR1_ZPU_Msk (0x3ul << DDRPHY_ZQ2SR1_ZPU_Pos) /*!< DDRPHY_T::ZQ2SR1: ZPU Mask */ + +#define DDRPHY_ZQ2SR1_OPD_Pos (4) /*!< DDRPHY_T::ZQ2SR1: OPD Position */ +#define DDRPHY_ZQ2SR1_OPD_Msk (0x3ul << DDRPHY_ZQ2SR1_OPD_Pos) /*!< DDRPHY_T::ZQ2SR1: OPD Mask */ + +#define DDRPHY_ZQ2SR1_OPU_Pos (6) /*!< DDRPHY_T::ZQ2SR1: OPU Position */ +#define DDRPHY_ZQ2SR1_OPU_Msk (0x3ul << DDRPHY_ZQ2SR1_OPU_Pos) /*!< DDRPHY_T::ZQ2SR1: OPU Mask */ + +#define DDRPHY_ZQ3CR0_ZDATA_Pos (0) /*!< DDRPHY_T::ZQ3CR0: ZDATA Position */ +#define DDRPHY_ZQ3CR0_ZDATA_Msk (0xffffffful << DDRPHY_ZQ3CR0_ZDATA_Pos) /*!< DDRPHY_T::ZQ3CR0: ZDATA Mask */ + +#define DDRPHY_ZQ3CR0_ZDEN_Pos (28) /*!< DDRPHY_T::ZQ3CR0: ZDEN Position */ +#define DDRPHY_ZQ3CR0_ZDEN_Msk (0x1ul << DDRPHY_ZQ3CR0_ZDEN_Pos) /*!< DDRPHY_T::ZQ3CR0: ZDEN Mask */ + +#define DDRPHY_ZQ3CR0_ZCALBYP_Pos (29) /*!< DDRPHY_T::ZQ3CR0: ZCALBYP Position */ +#define DDRPHY_ZQ3CR0_ZCALBYP_Msk (0x1ul << DDRPHY_ZQ3CR0_ZCALBYP_Pos) /*!< DDRPHY_T::ZQ3CR0: ZCALBYP Mask */ + +#define DDRPHY_ZQ3CR0_ZCALEN_Pos (30) /*!< DDRPHY_T::ZQ3CR0: ZCALEN Position */ +#define DDRPHY_ZQ3CR0_ZCALEN_Msk (0x1ul << DDRPHY_ZQ3CR0_ZCALEN_Pos) /*!< DDRPHY_T::ZQ3CR0: ZCALEN Mask */ + +#define DDRPHY_ZQ3CR0_ZQPD_Pos (31) /*!< DDRPHY_T::ZQ3CR0: ZQPD Position */ +#define DDRPHY_ZQ3CR0_ZQPD_Msk (0x1ul << DDRPHY_ZQ3CR0_ZQPD_Pos) /*!< DDRPHY_T::ZQ3CR0: ZQPD Mask */ + +#define DDRPHY_ZQ3CR1_ZPROG_Pos (0) /*!< DDRPHY_T::ZQ3CR1: ZPROG Position */ +#define DDRPHY_ZQ3CR1_ZPROG_Msk (0xfful << DDRPHY_ZQ3CR1_ZPROG_Pos) /*!< DDRPHY_T::ZQ3CR1: ZPROG Mask */ + +#define DDRPHY_ZQ3CR1_DFICU0_Pos (12) /*!< DDRPHY_T::ZQ3CR1: DFICU0 Position */ +#define DDRPHY_ZQ3CR1_DFICU0_Msk (0x1ul << DDRPHY_ZQ3CR1_DFICU0_Pos) /*!< DDRPHY_T::ZQ3CR1: DFICU0 Mask */ + +#define DDRPHY_ZQ3CR1_DFICU1_Pos (13) /*!< DDRPHY_T::ZQ3CR1: DFICU1 Position */ +#define DDRPHY_ZQ3CR1_DFICU1_Msk (0x1ul << DDRPHY_ZQ3CR1_DFICU1_Pos) /*!< DDRPHY_T::ZQ3CR1: DFICU1 Mask */ + +#define DDRPHY_ZQ3CR1_DFICCU_Pos (14) /*!< DDRPHY_T::ZQ3CR1: DFICCU Position */ +#define DDRPHY_ZQ3CR1_DFICCU_Msk (0x1ul << DDRPHY_ZQ3CR1_DFICCU_Pos) /*!< DDRPHY_T::ZQ3CR1: DFICCU Mask */ + +#define DDRPHY_ZQ3CR1_DFIPU0_Pos (16) /*!< DDRPHY_T::ZQ3CR1: DFIPU0 Position */ +#define DDRPHY_ZQ3CR1_DFIPU0_Msk (0x1ul << DDRPHY_ZQ3CR1_DFIPU0_Pos) /*!< DDRPHY_T::ZQ3CR1: DFIPU0 Mask */ + +#define DDRPHY_ZQ3CR1_DFIPU1_Pos (17) /*!< DDRPHY_T::ZQ3CR1: DFIPU1 Position */ +#define DDRPHY_ZQ3CR1_DFIPU1_Msk (0x1ul << DDRPHY_ZQ3CR1_DFIPU1_Pos) /*!< DDRPHY_T::ZQ3CR1: DFIPU1 Mask */ + +#define DDRPHY_ZQ3SR0_ZCTRL_Pos (0) /*!< DDRPHY_T::ZQ3SR0: ZCTRL Position */ +#define DDRPHY_ZQ3SR0_ZCTRL_Msk (0xffffffful << DDRPHY_ZQ3SR0_ZCTRL_Pos) /*!< DDRPHY_T::ZQ3SR0: ZCTRL Mask */ + +#define DDRPHY_ZQ3SR0_ZERR_Pos (30) /*!< DDRPHY_T::ZQ3SR0: ZERR Position */ +#define DDRPHY_ZQ3SR0_ZERR_Msk (0x1ul << DDRPHY_ZQ3SR0_ZERR_Pos) /*!< DDRPHY_T::ZQ3SR0: ZERR Mask */ + +#define DDRPHY_ZQ3SR0_ZDONE_Pos (31) /*!< DDRPHY_T::ZQ3SR0: ZDONE Position */ +#define DDRPHY_ZQ3SR0_ZDONE_Msk (0x1ul << DDRPHY_ZQ3SR0_ZDONE_Pos) /*!< DDRPHY_T::ZQ3SR0: ZDONE Mask */ + +#define DDRPHY_ZQ3SR1_ZPD_Pos (0) /*!< DDRPHY_T::ZQ3SR1: ZPD Position */ +#define DDRPHY_ZQ3SR1_ZPD_Msk (0x3ul << DDRPHY_ZQ3SR1_ZPD_Pos) /*!< DDRPHY_T::ZQ3SR1: ZPD Mask */ + +#define DDRPHY_ZQ3SR1_ZPU_Pos (2) /*!< DDRPHY_T::ZQ3SR1: ZPU Position */ +#define DDRPHY_ZQ3SR1_ZPU_Msk (0x3ul << DDRPHY_ZQ3SR1_ZPU_Pos) /*!< DDRPHY_T::ZQ3SR1: ZPU Mask */ + +#define DDRPHY_ZQ3SR1_OPD_Pos (4) /*!< DDRPHY_T::ZQ3SR1: OPD Position */ +#define DDRPHY_ZQ3SR1_OPD_Msk (0x3ul << DDRPHY_ZQ3SR1_OPD_Pos) /*!< DDRPHY_T::ZQ3SR1: OPD Mask */ + +#define DDRPHY_ZQ3SR1_OPU_Pos (6) /*!< DDRPHY_T::ZQ3SR1: OPU Position */ +#define DDRPHY_ZQ3SR1_OPU_Msk (0x3ul << DDRPHY_ZQ3SR1_OPU_Pos) /*!< DDRPHY_T::ZQ3SR1: OPU Mask */ + +#define DDRPHY_DX0GCR_DXEN_Pos (0) /*!< DDRPHY_T::DX0GCR: DXEN Position */ +#define DDRPHY_DX0GCR_DXEN_Msk (0x1ul << DDRPHY_DX0GCR_DXEN_Pos) /*!< DDRPHY_T::DX0GCR: DXEN Mask */ + +#define DDRPHY_DX0GCR_DQSODT_Pos (1) /*!< DDRPHY_T::DX0GCR: DQSODT Position */ +#define DDRPHY_DX0GCR_DQSODT_Msk (0x1ul << DDRPHY_DX0GCR_DQSODT_Pos) /*!< DDRPHY_T::DX0GCR: DQSODT Mask */ + +#define DDRPHY_DX0GCR_DQODT_Pos (2) /*!< DDRPHY_T::DX0GCR: DQODT Position */ +#define DDRPHY_DX0GCR_DQODT_Msk (0x1ul << DDRPHY_DX0GCR_DQODT_Pos) /*!< DDRPHY_T::DX0GCR: DQODT Mask */ + +#define DDRPHY_DX0GCR_DXIOM_Pos (3) /*!< DDRPHY_T::DX0GCR: DXIOM Position */ +#define DDRPHY_DX0GCR_DXIOM_Msk (0x1ul << DDRPHY_DX0GCR_DXIOM_Pos) /*!< DDRPHY_T::DX0GCR: DXIOM Mask */ + +#define DDRPHY_DX0GCR_DXPDD_Pos (4) /*!< DDRPHY_T::DX0GCR: DXPDD Position */ +#define DDRPHY_DX0GCR_DXPDD_Msk (0x1ul << DDRPHY_DX0GCR_DXPDD_Pos) /*!< DDRPHY_T::DX0GCR: DXPDD Mask */ + +#define DDRPHY_DX0GCR_DXPDR_Pos (5) /*!< DDRPHY_T::DX0GCR: DXPDR Position */ +#define DDRPHY_DX0GCR_DXPDR_Msk (0x1ul << DDRPHY_DX0GCR_DXPDR_Pos) /*!< DDRPHY_T::DX0GCR: DXPDR Mask */ + +#define DDRPHY_DX0GCR_DQSRPD_Pos (6) /*!< DDRPHY_T::DX0GCR: DQSRPD Position */ +#define DDRPHY_DX0GCR_DQSRPD_Msk (0x1ul << DDRPHY_DX0GCR_DQSRPD_Pos) /*!< DDRPHY_T::DX0GCR: DQSRPD Mask */ + +#define DDRPHY_DX0GCR_DSEN_Pos (7) /*!< DDRPHY_T::DX0GCR: DSEN Position */ +#define DDRPHY_DX0GCR_DSEN_Msk (0x3ul << DDRPHY_DX0GCR_DSEN_Pos) /*!< DDRPHY_T::DX0GCR: DSEN Mask */ + +#define DDRPHY_DX0GCR_DQSRTT_Pos (9) /*!< DDRPHY_T::DX0GCR: DQSRTT Position */ +#define DDRPHY_DX0GCR_DQSRTT_Msk (0x1ul << DDRPHY_DX0GCR_DQSRTT_Pos) /*!< DDRPHY_T::DX0GCR: DQSRTT Mask */ + +#define DDRPHY_DX0GCR_DQRTT_Pos (10) /*!< DDRPHY_T::DX0GCR: DQRTT Position */ +#define DDRPHY_DX0GCR_DQRTT_Msk (0x1ul << DDRPHY_DX0GCR_DQRTT_Pos) /*!< DDRPHY_T::DX0GCR: DQRTT Mask */ + +#define DDRPHY_DX0GCR_RTTOH_Pos (11) /*!< DDRPHY_T::DX0GCR: RTTOH Position */ +#define DDRPHY_DX0GCR_RTTOH_Msk (0x3ul << DDRPHY_DX0GCR_RTTOH_Pos) /*!< DDRPHY_T::DX0GCR: RTTOH Mask */ + +#define DDRPHY_DX0GCR_RTTOAL_Pos (13) /*!< DDRPHY_T::DX0GCR: RTTOAL Position */ +#define DDRPHY_DX0GCR_RTTOAL_Msk (0x1ul << DDRPHY_DX0GCR_RTTOAL_Pos) /*!< DDRPHY_T::DX0GCR: RTTOAL Mask */ + +#define DDRPHY_DX0GCR_DXOEO_Pos (14) /*!< DDRPHY_T::DX0GCR: DXOEO Position */ +#define DDRPHY_DX0GCR_DXOEO_Msk (0x3ul << DDRPHY_DX0GCR_DXOEO_Pos) /*!< DDRPHY_T::DX0GCR: DXOEO Mask */ + +#define DDRPHY_DX0GCR_PLLRST_Pos (16) /*!< DDRPHY_T::DX0GCR: PLLRST Position */ +#define DDRPHY_DX0GCR_PLLRST_Msk (0x1ul << DDRPHY_DX0GCR_PLLRST_Pos) /*!< DDRPHY_T::DX0GCR: PLLRST Mask */ + +#define DDRPHY_DX0GCR_PLLPD_Pos (17) /*!< DDRPHY_T::DX0GCR: PLLPD Position */ +#define DDRPHY_DX0GCR_PLLPD_Msk (0x1ul << DDRPHY_DX0GCR_PLLPD_Pos) /*!< DDRPHY_T::DX0GCR: PLLPD Mask */ + +#define DDRPHY_DX0GCR_GSHIFT_Pos (18) /*!< DDRPHY_T::DX0GCR: GSHIFT Position */ +#define DDRPHY_DX0GCR_GSHIFT_Msk (0x1ul << DDRPHY_DX0GCR_GSHIFT_Pos) /*!< DDRPHY_T::DX0GCR: GSHIFT Mask */ + +#define DDRPHY_DX0GCR_PLLBYP_Pos (19) /*!< DDRPHY_T::DX0GCR: PLLBYP Position */ +#define DDRPHY_DX0GCR_PLLBYP_Msk (0x1ul << DDRPHY_DX0GCR_PLLBYP_Pos) /*!< DDRPHY_T::DX0GCR: PLLBYP Mask */ + +#define DDRPHY_DX0GCR_WLRKEN_Pos (26) /*!< DDRPHY_T::DX0GCR: WLRKEN Position */ +#define DDRPHY_DX0GCR_WLRKEN_Msk (0xful << DDRPHY_DX0GCR_WLRKEN_Pos) /*!< DDRPHY_T::DX0GCR: WLRKEN Mask */ + +#define DDRPHY_DX0GCR_MDLEN_Pos (30) /*!< DDRPHY_T::DX0GCR: MDLEN Position */ +#define DDRPHY_DX0GCR_MDLEN_Msk (0x1ul << DDRPHY_DX0GCR_MDLEN_Pos) /*!< DDRPHY_T::DX0GCR: MDLEN Mask */ + +#define DDRPHY_DX0GCR_CALBYP_Pos (31) /*!< DDRPHY_T::DX0GCR: CALBYP Position */ +#define DDRPHY_DX0GCR_CALBYP_Msk (0x1ul << DDRPHY_DX0GCR_CALBYP_Pos) /*!< DDRPHY_T::DX0GCR: CALBYP Mask */ + +#define DDRPHY_DX0GSR0_WDQCAL_Pos (0) /*!< DDRPHY_T::DX0GSR0: WDQCAL Position */ +#define DDRPHY_DX0GSR0_WDQCAL_Msk (0x1ul << DDRPHY_DX0GSR0_WDQCAL_Pos) /*!< DDRPHY_T::DX0GSR0: WDQCAL Mask */ + +#define DDRPHY_DX0GSR0_RDQSCAL_Pos (1) /*!< DDRPHY_T::DX0GSR0: RDQSCAL Position */ +#define DDRPHY_DX0GSR0_RDQSCAL_Msk (0x1ul << DDRPHY_DX0GSR0_RDQSCAL_Pos) /*!< DDRPHY_T::DX0GSR0: RDQSCAL Mask */ + +#define DDRPHY_DX0GSR0_RDQSNCAL_Pos (2) /*!< DDRPHY_T::DX0GSR0: RDQSNCAL Position */ +#define DDRPHY_DX0GSR0_RDQSNCAL_Msk (0x1ul << DDRPHY_DX0GSR0_RDQSNCAL_Pos) /*!< DDRPHY_T::DX0GSR0: RDQSNCAL Mask */ + +#define DDRPHY_DX0GSR0_GDQSCAL_Pos (3) /*!< DDRPHY_T::DX0GSR0: GDQSCAL Position */ +#define DDRPHY_DX0GSR0_GDQSCAL_Msk (0x1ul << DDRPHY_DX0GSR0_GDQSCAL_Pos) /*!< DDRPHY_T::DX0GSR0: GDQSCAL Mask */ + +#define DDRPHY_DX0GSR0_WLCAL_Pos (4) /*!< DDRPHY_T::DX0GSR0: WLCAL Position */ +#define DDRPHY_DX0GSR0_WLCAL_Msk (0x1ul << DDRPHY_DX0GSR0_WLCAL_Pos) /*!< DDRPHY_T::DX0GSR0: WLCAL Mask */ + +#define DDRPHY_DX0GSR0_WLDONE_Pos (5) /*!< DDRPHY_T::DX0GSR0: WLDONE Position */ +#define DDRPHY_DX0GSR0_WLDONE_Msk (0x1ul << DDRPHY_DX0GSR0_WLDONE_Pos) /*!< DDRPHY_T::DX0GSR0: WLDONE Mask */ + +#define DDRPHY_DX0GSR0_WLERR_Pos (6) /*!< DDRPHY_T::DX0GSR0: WLERR Position */ +#define DDRPHY_DX0GSR0_WLERR_Msk (0x1ul << DDRPHY_DX0GSR0_WLERR_Pos) /*!< DDRPHY_T::DX0GSR0: WLERR Mask */ + +#define DDRPHY_DX0GSR0_WLPRD_Pos (7) /*!< DDRPHY_T::DX0GSR0: WLPRD Position */ +#define DDRPHY_DX0GSR0_WLPRD_Msk (0xfful << DDRPHY_DX0GSR0_WLPRD_Pos) /*!< DDRPHY_T::DX0GSR0: WLPRD Mask */ + +#define DDRPHY_DX0GSR0_DPLOCK_Pos (15) /*!< DDRPHY_T::DX0GSR0: DPLOCK Position */ +#define DDRPHY_DX0GSR0_DPLOCK_Msk (0x1ul << DDRPHY_DX0GSR0_DPLOCK_Pos) /*!< DDRPHY_T::DX0GSR0: DPLOCK Mask */ + +#define DDRPHY_DX0GSR0_GDQSPRD_Pos (16) /*!< DDRPHY_T::DX0GSR0: GDQSPRD Position */ +#define DDRPHY_DX0GSR0_GDQSPRD_Msk (0xfful << DDRPHY_DX0GSR0_GDQSPRD_Pos) /*!< DDRPHY_T::DX0GSR0: GDQSPRD Mask */ + +#define DDRPHY_DX0GSR0_QSGERR_Pos (24) /*!< DDRPHY_T::DX0GSR0: QSGERR Position */ +#define DDRPHY_DX0GSR0_QSGERR_Msk (0xful << DDRPHY_DX0GSR0_QSGERR_Pos) /*!< DDRPHY_T::DX0GSR0: QSGERR Mask */ + +#define DDRPHY_DX0GSR0_WLDQ_Pos (28) /*!< DDRPHY_T::DX0GSR0: WLDQ Position */ +#define DDRPHY_DX0GSR0_WLDQ_Msk (0x1ul << DDRPHY_DX0GSR0_WLDQ_Pos) /*!< DDRPHY_T::DX0GSR0: WLDQ Mask */ + +#define DDRPHY_DX0GSR1_DLTDONE_Pos (0) /*!< DDRPHY_T::DX0GSR1: DLTDONE Position */ +#define DDRPHY_DX0GSR1_DLTDONE_Msk (0x1ul << DDRPHY_DX0GSR1_DLTDONE_Pos) /*!< DDRPHY_T::DX0GSR1: DLTDONE Mask */ + +#define DDRPHY_DX0GSR1_DLTCODE_Pos (1) /*!< DDRPHY_T::DX0GSR1: DLTCODE Position */ +#define DDRPHY_DX0GSR1_DLTCODE_Msk (0xfffffful << DDRPHY_DX0GSR1_DLTCODE_Pos) /*!< DDRPHY_T::DX0GSR1: DLTCODE Mask */ + +#define DDRPHY_DX0BDLR0_DQ0WBD_Pos (0) /*!< DDRPHY_T::DX0BDLR0: DQ0WBD Position */ +#define DDRPHY_DX0BDLR0_DQ0WBD_Msk (0x3ful << DDRPHY_DX0BDLR0_DQ0WBD_Pos) /*!< DDRPHY_T::DX0BDLR0: DQ0WBD Mask */ + +#define DDRPHY_DX0BDLR0_DQ1WBD_Pos (6) /*!< DDRPHY_T::DX0BDLR0: DQ1WBD Position */ +#define DDRPHY_DX0BDLR0_DQ1WBD_Msk (0x3ful << DDRPHY_DX0BDLR0_DQ1WBD_Pos) /*!< DDRPHY_T::DX0BDLR0: DQ1WBD Mask */ + +#define DDRPHY_DX0BDLR0_DQ2WBD_Pos (12) /*!< DDRPHY_T::DX0BDLR0: DQ2WBD Position */ +#define DDRPHY_DX0BDLR0_DQ2WBD_Msk (0x3ful << DDRPHY_DX0BDLR0_DQ2WBD_Pos) /*!< DDRPHY_T::DX0BDLR0: DQ2WBD Mask */ + +#define DDRPHY_DX0BDLR0_DQ3WBD_Pos (18) /*!< DDRPHY_T::DX0BDLR0: DQ3WBD Position */ +#define DDRPHY_DX0BDLR0_DQ3WBD_Msk (0x3ful << DDRPHY_DX0BDLR0_DQ3WBD_Pos) /*!< DDRPHY_T::DX0BDLR0: DQ3WBD Mask */ + +#define DDRPHY_DX0BDLR0_DQ4WBD_Pos (24) /*!< DDRPHY_T::DX0BDLR0: DQ4WBD Position */ +#define DDRPHY_DX0BDLR0_DQ4WBD_Msk (0x3ful << DDRPHY_DX0BDLR0_DQ4WBD_Pos) /*!< DDRPHY_T::DX0BDLR0: DQ4WBD Mask */ + +#define DDRPHY_DX0BDLR1_DQ5WBD_Pos (0) /*!< DDRPHY_T::DX0BDLR1: DQ5WBD Position */ +#define DDRPHY_DX0BDLR1_DQ5WBD_Msk (0x3ful << DDRPHY_DX0BDLR1_DQ5WBD_Pos) /*!< DDRPHY_T::DX0BDLR1: DQ5WBD Mask */ + +#define DDRPHY_DX0BDLR1_DQ6WBD_Pos (6) /*!< DDRPHY_T::DX0BDLR1: DQ6WBD Position */ +#define DDRPHY_DX0BDLR1_DQ6WBD_Msk (0x3ful << DDRPHY_DX0BDLR1_DQ6WBD_Pos) /*!< DDRPHY_T::DX0BDLR1: DQ6WBD Mask */ + +#define DDRPHY_DX0BDLR1_DQ7WBD_Pos (12) /*!< DDRPHY_T::DX0BDLR1: DQ7WBD Position */ +#define DDRPHY_DX0BDLR1_DQ7WBD_Msk (0x3ful << DDRPHY_DX0BDLR1_DQ7WBD_Pos) /*!< DDRPHY_T::DX0BDLR1: DQ7WBD Mask */ + +#define DDRPHY_DX0BDLR1_DMWBD_Pos (18) /*!< DDRPHY_T::DX0BDLR1: DMWBD Position */ +#define DDRPHY_DX0BDLR1_DMWBD_Msk (0x3ful << DDRPHY_DX0BDLR1_DMWBD_Pos) /*!< DDRPHY_T::DX0BDLR1: DMWBD Mask */ + +#define DDRPHY_DX0BDLR1_DSWBD_Pos (24) /*!< DDRPHY_T::DX0BDLR1: DSWBD Position */ +#define DDRPHY_DX0BDLR1_DSWBD_Msk (0x3ful << DDRPHY_DX0BDLR1_DSWBD_Pos) /*!< DDRPHY_T::DX0BDLR1: DSWBD Mask */ + +#define DDRPHY_DX0BDLR2_DSOEBD_Pos (0) /*!< DDRPHY_T::DX0BDLR2: DSOEBD Position */ +#define DDRPHY_DX0BDLR2_DSOEBD_Msk (0x3ful << DDRPHY_DX0BDLR2_DSOEBD_Pos) /*!< DDRPHY_T::DX0BDLR2: DSOEBD Mask */ + +#define DDRPHY_DX0BDLR2_DQOEBD_Pos (6) /*!< DDRPHY_T::DX0BDLR2: DQOEBD Position */ +#define DDRPHY_DX0BDLR2_DQOEBD_Msk (0x3ful << DDRPHY_DX0BDLR2_DQOEBD_Pos) /*!< DDRPHY_T::DX0BDLR2: DQOEBD Mask */ + +#define DDRPHY_DX0BDLR2_DSRBD_Pos (12) /*!< DDRPHY_T::DX0BDLR2: DSRBD Position */ +#define DDRPHY_DX0BDLR2_DSRBD_Msk (0x3ful << DDRPHY_DX0BDLR2_DSRBD_Pos) /*!< DDRPHY_T::DX0BDLR2: DSRBD Mask */ + +#define DDRPHY_DX0BDLR2_DSNRBD_Pos (18) /*!< DDRPHY_T::DX0BDLR2: DSNRBD Position */ +#define DDRPHY_DX0BDLR2_DSNRBD_Msk (0x3ful << DDRPHY_DX0BDLR2_DSNRBD_Pos) /*!< DDRPHY_T::DX0BDLR2: DSNRBD Mask */ + +#define DDRPHY_DX0BDLR3_DQ0RBD_Pos (0) /*!< DDRPHY_T::DX0BDLR3: DQ0RBD Position */ +#define DDRPHY_DX0BDLR3_DQ0RBD_Msk (0x3ful << DDRPHY_DX0BDLR3_DQ0RBD_Pos) /*!< DDRPHY_T::DX0BDLR3: DQ0RBD Mask */ + +#define DDRPHY_DX0BDLR3_DQ1RBD_Pos (6) /*!< DDRPHY_T::DX0BDLR3: DQ1RBD Position */ +#define DDRPHY_DX0BDLR3_DQ1RBD_Msk (0x3ful << DDRPHY_DX0BDLR3_DQ1RBD_Pos) /*!< DDRPHY_T::DX0BDLR3: DQ1RBD Mask */ + +#define DDRPHY_DX0BDLR3_DQ2RBD_Pos (12) /*!< DDRPHY_T::DX0BDLR3: DQ2RBD Position */ +#define DDRPHY_DX0BDLR3_DQ2RBD_Msk (0x3ful << DDRPHY_DX0BDLR3_DQ2RBD_Pos) /*!< DDRPHY_T::DX0BDLR3: DQ2RBD Mask */ + +#define DDRPHY_DX0BDLR3_DQ3RBD_Pos (18) /*!< DDRPHY_T::DX0BDLR3: DQ3RBD Position */ +#define DDRPHY_DX0BDLR3_DQ3RBD_Msk (0x3ful << DDRPHY_DX0BDLR3_DQ3RBD_Pos) /*!< DDRPHY_T::DX0BDLR3: DQ3RBD Mask */ + +#define DDRPHY_DX0BDLR3_DQ4RBD_Pos (24) /*!< DDRPHY_T::DX0BDLR3: DQ4RBD Position */ +#define DDRPHY_DX0BDLR3_DQ4RBD_Msk (0x3ful << DDRPHY_DX0BDLR3_DQ4RBD_Pos) /*!< DDRPHY_T::DX0BDLR3: DQ4RBD Mask */ + +#define DDRPHY_DX0BDLR4_DQ5RBD_Pos (0) /*!< DDRPHY_T::DX0BDLR4: DQ5RBD Position */ +#define DDRPHY_DX0BDLR4_DQ5RBD_Msk (0x3ful << DDRPHY_DX0BDLR4_DQ5RBD_Pos) /*!< DDRPHY_T::DX0BDLR4: DQ5RBD Mask */ + +#define DDRPHY_DX0BDLR4_DQ6RBD_Pos (6) /*!< DDRPHY_T::DX0BDLR4: DQ6RBD Position */ +#define DDRPHY_DX0BDLR4_DQ6RBD_Msk (0x3ful << DDRPHY_DX0BDLR4_DQ6RBD_Pos) /*!< DDRPHY_T::DX0BDLR4: DQ6RBD Mask */ + +#define DDRPHY_DX0BDLR4_DQ7RBD_Pos (12) /*!< DDRPHY_T::DX0BDLR4: DQ7RBD Position */ +#define DDRPHY_DX0BDLR4_DQ7RBD_Msk (0x3ful << DDRPHY_DX0BDLR4_DQ7RBD_Pos) /*!< DDRPHY_T::DX0BDLR4: DQ7RBD Mask */ + +#define DDRPHY_DX0BDLR4_DMRBD_Pos (18) /*!< DDRPHY_T::DX0BDLR4: DMRBD Position */ +#define DDRPHY_DX0BDLR4_DMRBD_Msk (0x3ful << DDRPHY_DX0BDLR4_DMRBD_Pos) /*!< DDRPHY_T::DX0BDLR4: DMRBD Mask */ + +#define DDRPHY_DX0LCDLR0_R0WLD_Pos (0) /*!< DDRPHY_T::DX0LCDLR0: R0WLD Position */ +#define DDRPHY_DX0LCDLR0_R0WLD_Msk (0xfful << DDRPHY_DX0LCDLR0_R0WLD_Pos) /*!< DDRPHY_T::DX0LCDLR0: R0WLD Mask */ + +#define DDRPHY_DX0LCDLR0_R1WLD_Pos (8) /*!< DDRPHY_T::DX0LCDLR0: R1WLD Position */ +#define DDRPHY_DX0LCDLR0_R1WLD_Msk (0xfful << DDRPHY_DX0LCDLR0_R1WLD_Pos) /*!< DDRPHY_T::DX0LCDLR0: R1WLD Mask */ + +#define DDRPHY_DX0LCDLR0_R2WLD_Pos (16) /*!< DDRPHY_T::DX0LCDLR0: R2WLD Position */ +#define DDRPHY_DX0LCDLR0_R2WLD_Msk (0xfful << DDRPHY_DX0LCDLR0_R2WLD_Pos) /*!< DDRPHY_T::DX0LCDLR0: R2WLD Mask */ + +#define DDRPHY_DX0LCDLR0_R3WLD_Pos (24) /*!< DDRPHY_T::DX0LCDLR0: R3WLD Position */ +#define DDRPHY_DX0LCDLR0_R3WLD_Msk (0xfful << DDRPHY_DX0LCDLR0_R3WLD_Pos) /*!< DDRPHY_T::DX0LCDLR0: R3WLD Mask */ + +#define DDRPHY_DX0LCDLR1_WDQD_Pos (0) /*!< DDRPHY_T::DX0LCDLR1: WDQD Position */ +#define DDRPHY_DX0LCDLR1_WDQD_Msk (0xfful << DDRPHY_DX0LCDLR1_WDQD_Pos) /*!< DDRPHY_T::DX0LCDLR1: WDQD Mask */ + +#define DDRPHY_DX0LCDLR1_RDQSD_Pos (8) /*!< DDRPHY_T::DX0LCDLR1: RDQSD Position */ +#define DDRPHY_DX0LCDLR1_RDQSD_Msk (0xfful << DDRPHY_DX0LCDLR1_RDQSD_Pos) /*!< DDRPHY_T::DX0LCDLR1: RDQSD Mask */ + +#define DDRPHY_DX0LCDLR1_RDQSND_Pos (16) /*!< DDRPHY_T::DX0LCDLR1: RDQSND Position */ +#define DDRPHY_DX0LCDLR1_RDQSND_Msk (0xfful << DDRPHY_DX0LCDLR1_RDQSND_Pos) /*!< DDRPHY_T::DX0LCDLR1: RDQSND Mask */ + +#define DDRPHY_DX0LCDLR2_R0DQSGD_Pos (0) /*!< DDRPHY_T::DX0LCDLR2: R0DQSGD Position */ +#define DDRPHY_DX0LCDLR2_R0DQSGD_Msk (0xfful << DDRPHY_DX0LCDLR2_R0DQSGD_Pos) /*!< DDRPHY_T::DX0LCDLR2: R0DQSGD Mask */ + +#define DDRPHY_DX0LCDLR2_R1DQSGD_Pos (8) /*!< DDRPHY_T::DX0LCDLR2: R1DQSGD Position */ +#define DDRPHY_DX0LCDLR2_R1DQSGD_Msk (0xfful << DDRPHY_DX0LCDLR2_R1DQSGD_Pos) /*!< DDRPHY_T::DX0LCDLR2: R1DQSGD Mask */ + +#define DDRPHY_DX0LCDLR2_R2DQSGD_Pos (16) /*!< DDRPHY_T::DX0LCDLR2: R2DQSGD Position */ +#define DDRPHY_DX0LCDLR2_R2DQSGD_Msk (0xfful << DDRPHY_DX0LCDLR2_R2DQSGD_Pos) /*!< DDRPHY_T::DX0LCDLR2: R2DQSGD Mask */ + +#define DDRPHY_DX0LCDLR2_R3DQSGD_Pos (24) /*!< DDRPHY_T::DX0LCDLR2: R3DQSGD Position */ +#define DDRPHY_DX0LCDLR2_R3DQSGD_Msk (0xfful << DDRPHY_DX0LCDLR2_R3DQSGD_Pos) /*!< DDRPHY_T::DX0LCDLR2: R3DQSGD Mask */ + +#define DDRPHY_DX0MDLR_IPRD_Pos (0) /*!< DDRPHY_T::DX0MDLR: IPRD Position */ +#define DDRPHY_DX0MDLR_IPRD_Msk (0xfful << DDRPHY_DX0MDLR_IPRD_Pos) /*!< DDRPHY_T::DX0MDLR: IPRD Mask */ + +#define DDRPHY_DX0MDLR_TPRD_Pos (8) /*!< DDRPHY_T::DX0MDLR: TPRD Position */ +#define DDRPHY_DX0MDLR_TPRD_Msk (0xfful << DDRPHY_DX0MDLR_TPRD_Pos) /*!< DDRPHY_T::DX0MDLR: TPRD Mask */ + +#define DDRPHY_DX0MDLR_MDLD_Pos (16) /*!< DDRPHY_T::DX0MDLR: MDLD Position */ +#define DDRPHY_DX0MDLR_MDLD_Msk (0xfful << DDRPHY_DX0MDLR_MDLD_Pos) /*!< DDRPHY_T::DX0MDLR: MDLD Mask */ + +#define DDRPHY_DX0GTR_R0DGSL_Pos (0) /*!< DDRPHY_T::DX0GTR: R0DGSL Position */ +#define DDRPHY_DX0GTR_R0DGSL_Msk (0x7ul << DDRPHY_DX0GTR_R0DGSL_Pos) /*!< DDRPHY_T::DX0GTR: R0DGSL Mask */ + +#define DDRPHY_DX0GTR_R1DGSL_Pos (3) /*!< DDRPHY_T::DX0GTR: R1DGSL Position */ +#define DDRPHY_DX0GTR_R1DGSL_Msk (0x7ul << DDRPHY_DX0GTR_R1DGSL_Pos) /*!< DDRPHY_T::DX0GTR: R1DGSL Mask */ + +#define DDRPHY_DX0GTR_R2DGSL_Pos (6) /*!< DDRPHY_T::DX0GTR: R2DGSL Position */ +#define DDRPHY_DX0GTR_R2DGSL_Msk (0x7ul << DDRPHY_DX0GTR_R2DGSL_Pos) /*!< DDRPHY_T::DX0GTR: R2DGSL Mask */ + +#define DDRPHY_DX0GTR_R3DGSL_Pos (9) /*!< DDRPHY_T::DX0GTR: R3DGSL Position */ +#define DDRPHY_DX0GTR_R3DGSL_Msk (0x7ul << DDRPHY_DX0GTR_R3DGSL_Pos) /*!< DDRPHY_T::DX0GTR: R3DGSL Mask */ + +#define DDRPHY_DX0GTR_R0WLSL_Pos (12) /*!< DDRPHY_T::DX0GTR: R0WLSL Position */ +#define DDRPHY_DX0GTR_R0WLSL_Msk (0x3ul << DDRPHY_DX0GTR_R0WLSL_Pos) /*!< DDRPHY_T::DX0GTR: R0WLSL Mask */ + +#define DDRPHY_DX0GTR_R1WLSL_Pos (14) /*!< DDRPHY_T::DX0GTR: R1WLSL Position */ +#define DDRPHY_DX0GTR_R1WLSL_Msk (0x3ul << DDRPHY_DX0GTR_R1WLSL_Pos) /*!< DDRPHY_T::DX0GTR: R1WLSL Mask */ + +#define DDRPHY_DX0GTR_R2WLSL_Pos (16) /*!< DDRPHY_T::DX0GTR: R2WLSL Position */ +#define DDRPHY_DX0GTR_R2WLSL_Msk (0x3ul << DDRPHY_DX0GTR_R2WLSL_Pos) /*!< DDRPHY_T::DX0GTR: R2WLSL Mask */ + +#define DDRPHY_DX0GTR_R3WLSL_Pos (18) /*!< DDRPHY_T::DX0GTR: R3WLSL Position */ +#define DDRPHY_DX0GTR_R3WLSL_Msk (0x3ul << DDRPHY_DX0GTR_R3WLSL_Pos) /*!< DDRPHY_T::DX0GTR: R3WLSL Mask */ + +#define DDRPHY_DX0GSR2_RDERR_Pos (0) /*!< DDRPHY_T::DX0GSR2: RDERR Position */ +#define DDRPHY_DX0GSR2_RDERR_Msk (0x1ul << DDRPHY_DX0GSR2_RDERR_Pos) /*!< DDRPHY_T::DX0GSR2: RDERR Mask */ + +#define DDRPHY_DX0GSR2_RDWN_Pos (1) /*!< DDRPHY_T::DX0GSR2: RDWN Position */ +#define DDRPHY_DX0GSR2_RDWN_Msk (0x1ul << DDRPHY_DX0GSR2_RDWN_Pos) /*!< DDRPHY_T::DX0GSR2: RDWN Mask */ + +#define DDRPHY_DX0GSR2_WDERR_Pos (2) /*!< DDRPHY_T::DX0GSR2: WDERR Position */ +#define DDRPHY_DX0GSR2_WDERR_Msk (0x1ul << DDRPHY_DX0GSR2_WDERR_Pos) /*!< DDRPHY_T::DX0GSR2: WDERR Mask */ + +#define DDRPHY_DX0GSR2_WDWN_Pos (3) /*!< DDRPHY_T::DX0GSR2: WDWN Position */ +#define DDRPHY_DX0GSR2_WDWN_Msk (0x1ul << DDRPHY_DX0GSR2_WDWN_Pos) /*!< DDRPHY_T::DX0GSR2: WDWN Mask */ + +#define DDRPHY_DX0GSR2_REERR_Pos (4) /*!< DDRPHY_T::DX0GSR2: REERR Position */ +#define DDRPHY_DX0GSR2_REERR_Msk (0x1ul << DDRPHY_DX0GSR2_REERR_Pos) /*!< DDRPHY_T::DX0GSR2: REERR Mask */ + +#define DDRPHY_DX0GSR2_REWN_Pos (5) /*!< DDRPHY_T::DX0GSR2: REWN Position */ +#define DDRPHY_DX0GSR2_REWN_Msk (0x1ul << DDRPHY_DX0GSR2_REWN_Pos) /*!< DDRPHY_T::DX0GSR2: REWN Mask */ + +#define DDRPHY_DX0GSR2_WEERR_Pos (6) /*!< DDRPHY_T::DX0GSR2: WEERR Position */ +#define DDRPHY_DX0GSR2_WEERR_Msk (0x1ul << DDRPHY_DX0GSR2_WEERR_Pos) /*!< DDRPHY_T::DX0GSR2: WEERR Mask */ + +#define DDRPHY_DX0GSR2_WEWN_Pos (7) /*!< DDRPHY_T::DX0GSR2: WEWN Position */ +#define DDRPHY_DX0GSR2_WEWN_Msk (0x1ul << DDRPHY_DX0GSR2_WEWN_Pos) /*!< DDRPHY_T::DX0GSR2: WEWN Mask */ + +#define DDRPHY_DX0GSR2_ESTAT_Pos (8) /*!< DDRPHY_T::DX0GSR2: ESTAT Position */ +#define DDRPHY_DX0GSR2_ESTAT_Msk (0xful << DDRPHY_DX0GSR2_ESTAT_Pos) /*!< DDRPHY_T::DX0GSR2: ESTAT Mask */ + +#define DDRPHY_DX1GCR_DXEN_Pos (0) /*!< DDRPHY_T::DX1GCR: DXEN Position */ +#define DDRPHY_DX1GCR_DXEN_Msk (0x1ul << DDRPHY_DX1GCR_DXEN_Pos) /*!< DDRPHY_T::DX1GCR: DXEN Mask */ + +#define DDRPHY_DX1GCR_DQSODT_Pos (1) /*!< DDRPHY_T::DX1GCR: DQSODT Position */ +#define DDRPHY_DX1GCR_DQSODT_Msk (0x1ul << DDRPHY_DX1GCR_DQSODT_Pos) /*!< DDRPHY_T::DX1GCR: DQSODT Mask */ + +#define DDRPHY_DX1GCR_DQODT_Pos (2) /*!< DDRPHY_T::DX1GCR: DQODT Position */ +#define DDRPHY_DX1GCR_DQODT_Msk (0x1ul << DDRPHY_DX1GCR_DQODT_Pos) /*!< DDRPHY_T::DX1GCR: DQODT Mask */ + +#define DDRPHY_DX1GCR_DXIOM_Pos (3) /*!< DDRPHY_T::DX1GCR: DXIOM Position */ +#define DDRPHY_DX1GCR_DXIOM_Msk (0x1ul << DDRPHY_DX1GCR_DXIOM_Pos) /*!< DDRPHY_T::DX1GCR: DXIOM Mask */ + +#define DDRPHY_DX1GCR_DXPDD_Pos (4) /*!< DDRPHY_T::DX1GCR: DXPDD Position */ +#define DDRPHY_DX1GCR_DXPDD_Msk (0x1ul << DDRPHY_DX1GCR_DXPDD_Pos) /*!< DDRPHY_T::DX1GCR: DXPDD Mask */ + +#define DDRPHY_DX1GCR_DXPDR_Pos (5) /*!< DDRPHY_T::DX1GCR: DXPDR Position */ +#define DDRPHY_DX1GCR_DXPDR_Msk (0x1ul << DDRPHY_DX1GCR_DXPDR_Pos) /*!< DDRPHY_T::DX1GCR: DXPDR Mask */ + +#define DDRPHY_DX1GCR_DQSRPD_Pos (6) /*!< DDRPHY_T::DX1GCR: DQSRPD Position */ +#define DDRPHY_DX1GCR_DQSRPD_Msk (0x1ul << DDRPHY_DX1GCR_DQSRPD_Pos) /*!< DDRPHY_T::DX1GCR: DQSRPD Mask */ + +#define DDRPHY_DX1GCR_DSEN_Pos (7) /*!< DDRPHY_T::DX1GCR: DSEN Position */ +#define DDRPHY_DX1GCR_DSEN_Msk (0x3ul << DDRPHY_DX1GCR_DSEN_Pos) /*!< DDRPHY_T::DX1GCR: DSEN Mask */ + +#define DDRPHY_DX1GCR_DQSRTT_Pos (9) /*!< DDRPHY_T::DX1GCR: DQSRTT Position */ +#define DDRPHY_DX1GCR_DQSRTT_Msk (0x1ul << DDRPHY_DX1GCR_DQSRTT_Pos) /*!< DDRPHY_T::DX1GCR: DQSRTT Mask */ + +#define DDRPHY_DX1GCR_DQRTT_Pos (10) /*!< DDRPHY_T::DX1GCR: DQRTT Position */ +#define DDRPHY_DX1GCR_DQRTT_Msk (0x1ul << DDRPHY_DX1GCR_DQRTT_Pos) /*!< DDRPHY_T::DX1GCR: DQRTT Mask */ + +#define DDRPHY_DX1GCR_RTTOH_Pos (11) /*!< DDRPHY_T::DX1GCR: RTTOH Position */ +#define DDRPHY_DX1GCR_RTTOH_Msk (0x3ul << DDRPHY_DX1GCR_RTTOH_Pos) /*!< DDRPHY_T::DX1GCR: RTTOH Mask */ + +#define DDRPHY_DX1GCR_RTTOAL_Pos (13) /*!< DDRPHY_T::DX1GCR: RTTOAL Position */ +#define DDRPHY_DX1GCR_RTTOAL_Msk (0x1ul << DDRPHY_DX1GCR_RTTOAL_Pos) /*!< DDRPHY_T::DX1GCR: RTTOAL Mask */ + +#define DDRPHY_DX1GCR_DXOEO_Pos (14) /*!< DDRPHY_T::DX1GCR: DXOEO Position */ +#define DDRPHY_DX1GCR_DXOEO_Msk (0x3ul << DDRPHY_DX1GCR_DXOEO_Pos) /*!< DDRPHY_T::DX1GCR: DXOEO Mask */ + +#define DDRPHY_DX1GCR_PLLRST_Pos (16) /*!< DDRPHY_T::DX1GCR: PLLRST Position */ +#define DDRPHY_DX1GCR_PLLRST_Msk (0x1ul << DDRPHY_DX1GCR_PLLRST_Pos) /*!< DDRPHY_T::DX1GCR: PLLRST Mask */ + +#define DDRPHY_DX1GCR_PLLPD_Pos (17) /*!< DDRPHY_T::DX1GCR: PLLPD Position */ +#define DDRPHY_DX1GCR_PLLPD_Msk (0x1ul << DDRPHY_DX1GCR_PLLPD_Pos) /*!< DDRPHY_T::DX1GCR: PLLPD Mask */ + +#define DDRPHY_DX1GCR_GSHIFT_Pos (18) /*!< DDRPHY_T::DX1GCR: GSHIFT Position */ +#define DDRPHY_DX1GCR_GSHIFT_Msk (0x1ul << DDRPHY_DX1GCR_GSHIFT_Pos) /*!< DDRPHY_T::DX1GCR: GSHIFT Mask */ + +#define DDRPHY_DX1GCR_PLLBYP_Pos (19) /*!< DDRPHY_T::DX1GCR: PLLBYP Position */ +#define DDRPHY_DX1GCR_PLLBYP_Msk (0x1ul << DDRPHY_DX1GCR_PLLBYP_Pos) /*!< DDRPHY_T::DX1GCR: PLLBYP Mask */ + +#define DDRPHY_DX1GCR_WLRKEN_Pos (26) /*!< DDRPHY_T::DX1GCR: WLRKEN Position */ +#define DDRPHY_DX1GCR_WLRKEN_Msk (0xful << DDRPHY_DX1GCR_WLRKEN_Pos) /*!< DDRPHY_T::DX1GCR: WLRKEN Mask */ + +#define DDRPHY_DX1GCR_MDLEN_Pos (30) /*!< DDRPHY_T::DX1GCR: MDLEN Position */ +#define DDRPHY_DX1GCR_MDLEN_Msk (0x1ul << DDRPHY_DX1GCR_MDLEN_Pos) /*!< DDRPHY_T::DX1GCR: MDLEN Mask */ + +#define DDRPHY_DX1GCR_CALBYP_Pos (31) /*!< DDRPHY_T::DX1GCR: CALBYP Position */ +#define DDRPHY_DX1GCR_CALBYP_Msk (0x1ul << DDRPHY_DX1GCR_CALBYP_Pos) /*!< DDRPHY_T::DX1GCR: CALBYP Mask */ + +#define DDRPHY_DX1GSR0_WDQCAL_Pos (0) /*!< DDRPHY_T::DX1GSR0: WDQCAL Position */ +#define DDRPHY_DX1GSR0_WDQCAL_Msk (0x1ul << DDRPHY_DX1GSR0_WDQCAL_Pos) /*!< DDRPHY_T::DX1GSR0: WDQCAL Mask */ + +#define DDRPHY_DX1GSR0_RDQSCAL_Pos (1) /*!< DDRPHY_T::DX1GSR0: RDQSCAL Position */ +#define DDRPHY_DX1GSR0_RDQSCAL_Msk (0x1ul << DDRPHY_DX1GSR0_RDQSCAL_Pos) /*!< DDRPHY_T::DX1GSR0: RDQSCAL Mask */ + +#define DDRPHY_DX1GSR0_RDQSNCAL_Pos (2) /*!< DDRPHY_T::DX1GSR0: RDQSNCAL Position */ +#define DDRPHY_DX1GSR0_RDQSNCAL_Msk (0x1ul << DDRPHY_DX1GSR0_RDQSNCAL_Pos) /*!< DDRPHY_T::DX1GSR0: RDQSNCAL Mask */ + +#define DDRPHY_DX1GSR0_GDQSCAL_Pos (3) /*!< DDRPHY_T::DX1GSR0: GDQSCAL Position */ +#define DDRPHY_DX1GSR0_GDQSCAL_Msk (0x1ul << DDRPHY_DX1GSR0_GDQSCAL_Pos) /*!< DDRPHY_T::DX1GSR0: GDQSCAL Mask */ + +#define DDRPHY_DX1GSR0_WLCAL_Pos (4) /*!< DDRPHY_T::DX1GSR0: WLCAL Position */ +#define DDRPHY_DX1GSR0_WLCAL_Msk (0x1ul << DDRPHY_DX1GSR0_WLCAL_Pos) /*!< DDRPHY_T::DX1GSR0: WLCAL Mask */ + +#define DDRPHY_DX1GSR0_WLDONE_Pos (5) /*!< DDRPHY_T::DX1GSR0: WLDONE Position */ +#define DDRPHY_DX1GSR0_WLDONE_Msk (0x1ul << DDRPHY_DX1GSR0_WLDONE_Pos) /*!< DDRPHY_T::DX1GSR0: WLDONE Mask */ + +#define DDRPHY_DX1GSR0_WLERR_Pos (6) /*!< DDRPHY_T::DX1GSR0: WLERR Position */ +#define DDRPHY_DX1GSR0_WLERR_Msk (0x1ul << DDRPHY_DX1GSR0_WLERR_Pos) /*!< DDRPHY_T::DX1GSR0: WLERR Mask */ + +#define DDRPHY_DX1GSR0_WLPRD_Pos (7) /*!< DDRPHY_T::DX1GSR0: WLPRD Position */ +#define DDRPHY_DX1GSR0_WLPRD_Msk (0xfful << DDRPHY_DX1GSR0_WLPRD_Pos) /*!< DDRPHY_T::DX1GSR0: WLPRD Mask */ + +#define DDRPHY_DX1GSR0_DPLOCK_Pos (15) /*!< DDRPHY_T::DX1GSR0: DPLOCK Position */ +#define DDRPHY_DX1GSR0_DPLOCK_Msk (0x1ul << DDRPHY_DX1GSR0_DPLOCK_Pos) /*!< DDRPHY_T::DX1GSR0: DPLOCK Mask */ + +#define DDRPHY_DX1GSR0_GDQSPRD_Pos (16) /*!< DDRPHY_T::DX1GSR0: GDQSPRD Position */ +#define DDRPHY_DX1GSR0_GDQSPRD_Msk (0xfful << DDRPHY_DX1GSR0_GDQSPRD_Pos) /*!< DDRPHY_T::DX1GSR0: GDQSPRD Mask */ + +#define DDRPHY_DX1GSR0_QSGERR_Pos (24) /*!< DDRPHY_T::DX1GSR0: QSGERR Position */ +#define DDRPHY_DX1GSR0_QSGERR_Msk (0xful << DDRPHY_DX1GSR0_QSGERR_Pos) /*!< DDRPHY_T::DX1GSR0: QSGERR Mask */ + +#define DDRPHY_DX1GSR0_WLDQ_Pos (28) /*!< DDRPHY_T::DX1GSR0: WLDQ Position */ +#define DDRPHY_DX1GSR0_WLDQ_Msk (0x1ul << DDRPHY_DX1GSR0_WLDQ_Pos) /*!< DDRPHY_T::DX1GSR0: WLDQ Mask */ + +#define DDRPHY_DX1GSR1_DLTDONE_Pos (0) /*!< DDRPHY_T::DX1GSR1: DLTDONE Position */ +#define DDRPHY_DX1GSR1_DLTDONE_Msk (0x1ul << DDRPHY_DX1GSR1_DLTDONE_Pos) /*!< DDRPHY_T::DX1GSR1: DLTDONE Mask */ + +#define DDRPHY_DX1GSR1_DLTCODE_Pos (1) /*!< DDRPHY_T::DX1GSR1: DLTCODE Position */ +#define DDRPHY_DX1GSR1_DLTCODE_Msk (0xfffffful << DDRPHY_DX1GSR1_DLTCODE_Pos) /*!< DDRPHY_T::DX1GSR1: DLTCODE Mask */ + +#define DDRPHY_DX1BDLR0_DQ0WBD_Pos (0) /*!< DDRPHY_T::DX1BDLR0: DQ0WBD Position */ +#define DDRPHY_DX1BDLR0_DQ0WBD_Msk (0x3ful << DDRPHY_DX1BDLR0_DQ0WBD_Pos) /*!< DDRPHY_T::DX1BDLR0: DQ0WBD Mask */ + +#define DDRPHY_DX1BDLR0_DQ1WBD_Pos (6) /*!< DDRPHY_T::DX1BDLR0: DQ1WBD Position */ +#define DDRPHY_DX1BDLR0_DQ1WBD_Msk (0x3ful << DDRPHY_DX1BDLR0_DQ1WBD_Pos) /*!< DDRPHY_T::DX1BDLR0: DQ1WBD Mask */ + +#define DDRPHY_DX1BDLR0_DQ2WBD_Pos (12) /*!< DDRPHY_T::DX1BDLR0: DQ2WBD Position */ +#define DDRPHY_DX1BDLR0_DQ2WBD_Msk (0x3ful << DDRPHY_DX1BDLR0_DQ2WBD_Pos) /*!< DDRPHY_T::DX1BDLR0: DQ2WBD Mask */ + +#define DDRPHY_DX1BDLR0_DQ3WBD_Pos (18) /*!< DDRPHY_T::DX1BDLR0: DQ3WBD Position */ +#define DDRPHY_DX1BDLR0_DQ3WBD_Msk (0x3ful << DDRPHY_DX1BDLR0_DQ3WBD_Pos) /*!< DDRPHY_T::DX1BDLR0: DQ3WBD Mask */ + +#define DDRPHY_DX1BDLR0_DQ4WBD_Pos (24) /*!< DDRPHY_T::DX1BDLR0: DQ4WBD Position */ +#define DDRPHY_DX1BDLR0_DQ4WBD_Msk (0x3ful << DDRPHY_DX1BDLR0_DQ4WBD_Pos) /*!< DDRPHY_T::DX1BDLR0: DQ4WBD Mask */ + +#define DDRPHY_DX1BDLR1_DQ5WBD_Pos (0) /*!< DDRPHY_T::DX1BDLR1: DQ5WBD Position */ +#define DDRPHY_DX1BDLR1_DQ5WBD_Msk (0x3ful << DDRPHY_DX1BDLR1_DQ5WBD_Pos) /*!< DDRPHY_T::DX1BDLR1: DQ5WBD Mask */ + +#define DDRPHY_DX1BDLR1_DQ6WBD_Pos (6) /*!< DDRPHY_T::DX1BDLR1: DQ6WBD Position */ +#define DDRPHY_DX1BDLR1_DQ6WBD_Msk (0x3ful << DDRPHY_DX1BDLR1_DQ6WBD_Pos) /*!< DDRPHY_T::DX1BDLR1: DQ6WBD Mask */ + +#define DDRPHY_DX1BDLR1_DQ7WBD_Pos (12) /*!< DDRPHY_T::DX1BDLR1: DQ7WBD Position */ +#define DDRPHY_DX1BDLR1_DQ7WBD_Msk (0x3ful << DDRPHY_DX1BDLR1_DQ7WBD_Pos) /*!< DDRPHY_T::DX1BDLR1: DQ7WBD Mask */ + +#define DDRPHY_DX1BDLR1_DMWBD_Pos (18) /*!< DDRPHY_T::DX1BDLR1: DMWBD Position */ +#define DDRPHY_DX1BDLR1_DMWBD_Msk (0x3ful << DDRPHY_DX1BDLR1_DMWBD_Pos) /*!< DDRPHY_T::DX1BDLR1: DMWBD Mask */ + +#define DDRPHY_DX1BDLR1_DSWBD_Pos (24) /*!< DDRPHY_T::DX1BDLR1: DSWBD Position */ +#define DDRPHY_DX1BDLR1_DSWBD_Msk (0x3ful << DDRPHY_DX1BDLR1_DSWBD_Pos) /*!< DDRPHY_T::DX1BDLR1: DSWBD Mask */ + +#define DDRPHY_DX1BDLR2_DSOEBD_Pos (0) /*!< DDRPHY_T::DX1BDLR2: DSOEBD Position */ +#define DDRPHY_DX1BDLR2_DSOEBD_Msk (0x3ful << DDRPHY_DX1BDLR2_DSOEBD_Pos) /*!< DDRPHY_T::DX1BDLR2: DSOEBD Mask */ + +#define DDRPHY_DX1BDLR2_DQOEBD_Pos (6) /*!< DDRPHY_T::DX1BDLR2: DQOEBD Position */ +#define DDRPHY_DX1BDLR2_DQOEBD_Msk (0x3ful << DDRPHY_DX1BDLR2_DQOEBD_Pos) /*!< DDRPHY_T::DX1BDLR2: DQOEBD Mask */ + +#define DDRPHY_DX1BDLR2_DSRBD_Pos (12) /*!< DDRPHY_T::DX1BDLR2: DSRBD Position */ +#define DDRPHY_DX1BDLR2_DSRBD_Msk (0x3ful << DDRPHY_DX1BDLR2_DSRBD_Pos) /*!< DDRPHY_T::DX1BDLR2: DSRBD Mask */ + +#define DDRPHY_DX1BDLR2_DSNRBD_Pos (18) /*!< DDRPHY_T::DX1BDLR2: DSNRBD Position */ +#define DDRPHY_DX1BDLR2_DSNRBD_Msk (0x3ful << DDRPHY_DX1BDLR2_DSNRBD_Pos) /*!< DDRPHY_T::DX1BDLR2: DSNRBD Mask */ + +#define DDRPHY_DX1BDLR3_DQ0RBD_Pos (0) /*!< DDRPHY_T::DX1BDLR3: DQ0RBD Position */ +#define DDRPHY_DX1BDLR3_DQ0RBD_Msk (0x3ful << DDRPHY_DX1BDLR3_DQ0RBD_Pos) /*!< DDRPHY_T::DX1BDLR3: DQ0RBD Mask */ + +#define DDRPHY_DX1BDLR3_DQ1RBD_Pos (6) /*!< DDRPHY_T::DX1BDLR3: DQ1RBD Position */ +#define DDRPHY_DX1BDLR3_DQ1RBD_Msk (0x3ful << DDRPHY_DX1BDLR3_DQ1RBD_Pos) /*!< DDRPHY_T::DX1BDLR3: DQ1RBD Mask */ + +#define DDRPHY_DX1BDLR3_DQ2RBD_Pos (12) /*!< DDRPHY_T::DX1BDLR3: DQ2RBD Position */ +#define DDRPHY_DX1BDLR3_DQ2RBD_Msk (0x3ful << DDRPHY_DX1BDLR3_DQ2RBD_Pos) /*!< DDRPHY_T::DX1BDLR3: DQ2RBD Mask */ + +#define DDRPHY_DX1BDLR3_DQ3RBD_Pos (18) /*!< DDRPHY_T::DX1BDLR3: DQ3RBD Position */ +#define DDRPHY_DX1BDLR3_DQ3RBD_Msk (0x3ful << DDRPHY_DX1BDLR3_DQ3RBD_Pos) /*!< DDRPHY_T::DX1BDLR3: DQ3RBD Mask */ + +#define DDRPHY_DX1BDLR3_DQ4RBD_Pos (24) /*!< DDRPHY_T::DX1BDLR3: DQ4RBD Position */ +#define DDRPHY_DX1BDLR3_DQ4RBD_Msk (0x3ful << DDRPHY_DX1BDLR3_DQ4RBD_Pos) /*!< DDRPHY_T::DX1BDLR3: DQ4RBD Mask */ + +#define DDRPHY_DX1BDLR4_DQ5RBD_Pos (0) /*!< DDRPHY_T::DX1BDLR4: DQ5RBD Position */ +#define DDRPHY_DX1BDLR4_DQ5RBD_Msk (0x3ful << DDRPHY_DX1BDLR4_DQ5RBD_Pos) /*!< DDRPHY_T::DX1BDLR4: DQ5RBD Mask */ + +#define DDRPHY_DX1BDLR4_DQ6RBD_Pos (6) /*!< DDRPHY_T::DX1BDLR4: DQ6RBD Position */ +#define DDRPHY_DX1BDLR4_DQ6RBD_Msk (0x3ful << DDRPHY_DX1BDLR4_DQ6RBD_Pos) /*!< DDRPHY_T::DX1BDLR4: DQ6RBD Mask */ + +#define DDRPHY_DX1BDLR4_DQ7RBD_Pos (12) /*!< DDRPHY_T::DX1BDLR4: DQ7RBD Position */ +#define DDRPHY_DX1BDLR4_DQ7RBD_Msk (0x3ful << DDRPHY_DX1BDLR4_DQ7RBD_Pos) /*!< DDRPHY_T::DX1BDLR4: DQ7RBD Mask */ + +#define DDRPHY_DX1BDLR4_DMRBD_Pos (18) /*!< DDRPHY_T::DX1BDLR4: DMRBD Position */ +#define DDRPHY_DX1BDLR4_DMRBD_Msk (0x3ful << DDRPHY_DX1BDLR4_DMRBD_Pos) /*!< DDRPHY_T::DX1BDLR4: DMRBD Mask */ + +#define DDRPHY_DX1LCDLR0_R0WLD_Pos (0) /*!< DDRPHY_T::DX1LCDLR0: R0WLD Position */ +#define DDRPHY_DX1LCDLR0_R0WLD_Msk (0xfful << DDRPHY_DX1LCDLR0_R0WLD_Pos) /*!< DDRPHY_T::DX1LCDLR0: R0WLD Mask */ + +#define DDRPHY_DX1LCDLR0_R1WLD_Pos (8) /*!< DDRPHY_T::DX1LCDLR0: R1WLD Position */ +#define DDRPHY_DX1LCDLR0_R1WLD_Msk (0xfful << DDRPHY_DX1LCDLR0_R1WLD_Pos) /*!< DDRPHY_T::DX1LCDLR0: R1WLD Mask */ + +#define DDRPHY_DX1LCDLR0_R2WLD_Pos (16) /*!< DDRPHY_T::DX1LCDLR0: R2WLD Position */ +#define DDRPHY_DX1LCDLR0_R2WLD_Msk (0xfful << DDRPHY_DX1LCDLR0_R2WLD_Pos) /*!< DDRPHY_T::DX1LCDLR0: R2WLD Mask */ + +#define DDRPHY_DX1LCDLR0_R3WLD_Pos (24) /*!< DDRPHY_T::DX1LCDLR0: R3WLD Position */ +#define DDRPHY_DX1LCDLR0_R3WLD_Msk (0xfful << DDRPHY_DX1LCDLR0_R3WLD_Pos) /*!< DDRPHY_T::DX1LCDLR0: R3WLD Mask */ + +#define DDRPHY_DX1LCDLR1_WDQD_Pos (0) /*!< DDRPHY_T::DX1LCDLR1: WDQD Position */ +#define DDRPHY_DX1LCDLR1_WDQD_Msk (0xfful << DDRPHY_DX1LCDLR1_WDQD_Pos) /*!< DDRPHY_T::DX1LCDLR1: WDQD Mask */ + +#define DDRPHY_DX1LCDLR1_RDQSD_Pos (8) /*!< DDRPHY_T::DX1LCDLR1: RDQSD Position */ +#define DDRPHY_DX1LCDLR1_RDQSD_Msk (0xfful << DDRPHY_DX1LCDLR1_RDQSD_Pos) /*!< DDRPHY_T::DX1LCDLR1: RDQSD Mask */ + +#define DDRPHY_DX1LCDLR1_RDQSND_Pos (16) /*!< DDRPHY_T::DX1LCDLR1: RDQSND Position */ +#define DDRPHY_DX1LCDLR1_RDQSND_Msk (0xfful << DDRPHY_DX1LCDLR1_RDQSND_Pos) /*!< DDRPHY_T::DX1LCDLR1: RDQSND Mask */ + +#define DDRPHY_DX1LCDLR2_R0DQSGD_Pos (0) /*!< DDRPHY_T::DX1LCDLR2: R0DQSGD Position */ +#define DDRPHY_DX1LCDLR2_R0DQSGD_Msk (0xfful << DDRPHY_DX1LCDLR2_R0DQSGD_Pos) /*!< DDRPHY_T::DX1LCDLR2: R0DQSGD Mask */ + +#define DDRPHY_DX1LCDLR2_R1DQSGD_Pos (8) /*!< DDRPHY_T::DX1LCDLR2: R1DQSGD Position */ +#define DDRPHY_DX1LCDLR2_R1DQSGD_Msk (0xfful << DDRPHY_DX1LCDLR2_R1DQSGD_Pos) /*!< DDRPHY_T::DX1LCDLR2: R1DQSGD Mask */ + +#define DDRPHY_DX1LCDLR2_R2DQSGD_Pos (16) /*!< DDRPHY_T::DX1LCDLR2: R2DQSGD Position */ +#define DDRPHY_DX1LCDLR2_R2DQSGD_Msk (0xfful << DDRPHY_DX1LCDLR2_R2DQSGD_Pos) /*!< DDRPHY_T::DX1LCDLR2: R2DQSGD Mask */ + +#define DDRPHY_DX1LCDLR2_R3DQSGD_Pos (24) /*!< DDRPHY_T::DX1LCDLR2: R3DQSGD Position */ +#define DDRPHY_DX1LCDLR2_R3DQSGD_Msk (0xfful << DDRPHY_DX1LCDLR2_R3DQSGD_Pos) /*!< DDRPHY_T::DX1LCDLR2: R3DQSGD Mask */ + +#define DDRPHY_DX1MDLR_IPRD_Pos (0) /*!< DDRPHY_T::DX1MDLR: IPRD Position */ +#define DDRPHY_DX1MDLR_IPRD_Msk (0xfful << DDRPHY_DX1MDLR_IPRD_Pos) /*!< DDRPHY_T::DX1MDLR: IPRD Mask */ + +#define DDRPHY_DX1MDLR_TPRD_Pos (8) /*!< DDRPHY_T::DX1MDLR: TPRD Position */ +#define DDRPHY_DX1MDLR_TPRD_Msk (0xfful << DDRPHY_DX1MDLR_TPRD_Pos) /*!< DDRPHY_T::DX1MDLR: TPRD Mask */ + +#define DDRPHY_DX1MDLR_MDLD_Pos (16) /*!< DDRPHY_T::DX1MDLR: MDLD Position */ +#define DDRPHY_DX1MDLR_MDLD_Msk (0xfful << DDRPHY_DX1MDLR_MDLD_Pos) /*!< DDRPHY_T::DX1MDLR: MDLD Mask */ + +#define DDRPHY_DX1GTR_R0DGSL_Pos (0) /*!< DDRPHY_T::DX1GTR: R0DGSL Position */ +#define DDRPHY_DX1GTR_R0DGSL_Msk (0x7ul << DDRPHY_DX1GTR_R0DGSL_Pos) /*!< DDRPHY_T::DX1GTR: R0DGSL Mask */ + +#define DDRPHY_DX1GTR_R1DGSL_Pos (3) /*!< DDRPHY_T::DX1GTR: R1DGSL Position */ +#define DDRPHY_DX1GTR_R1DGSL_Msk (0x7ul << DDRPHY_DX1GTR_R1DGSL_Pos) /*!< DDRPHY_T::DX1GTR: R1DGSL Mask */ + +#define DDRPHY_DX1GTR_R2DGSL_Pos (6) /*!< DDRPHY_T::DX1GTR: R2DGSL Position */ +#define DDRPHY_DX1GTR_R2DGSL_Msk (0x7ul << DDRPHY_DX1GTR_R2DGSL_Pos) /*!< DDRPHY_T::DX1GTR: R2DGSL Mask */ + +#define DDRPHY_DX1GTR_R3DGSL_Pos (9) /*!< DDRPHY_T::DX1GTR: R3DGSL Position */ +#define DDRPHY_DX1GTR_R3DGSL_Msk (0x7ul << DDRPHY_DX1GTR_R3DGSL_Pos) /*!< DDRPHY_T::DX1GTR: R3DGSL Mask */ + +#define DDRPHY_DX1GTR_R0WLSL_Pos (12) /*!< DDRPHY_T::DX1GTR: R0WLSL Position */ +#define DDRPHY_DX1GTR_R0WLSL_Msk (0x3ul << DDRPHY_DX1GTR_R0WLSL_Pos) /*!< DDRPHY_T::DX1GTR: R0WLSL Mask */ + +#define DDRPHY_DX1GTR_R1WLSL_Pos (14) /*!< DDRPHY_T::DX1GTR: R1WLSL Position */ +#define DDRPHY_DX1GTR_R1WLSL_Msk (0x3ul << DDRPHY_DX1GTR_R1WLSL_Pos) /*!< DDRPHY_T::DX1GTR: R1WLSL Mask */ + +#define DDRPHY_DX1GTR_R2WLSL_Pos (16) /*!< DDRPHY_T::DX1GTR: R2WLSL Position */ +#define DDRPHY_DX1GTR_R2WLSL_Msk (0x3ul << DDRPHY_DX1GTR_R2WLSL_Pos) /*!< DDRPHY_T::DX1GTR: R2WLSL Mask */ + +#define DDRPHY_DX1GTR_R3WLSL_Pos (18) /*!< DDRPHY_T::DX1GTR: R3WLSL Position */ +#define DDRPHY_DX1GTR_R3WLSL_Msk (0x3ul << DDRPHY_DX1GTR_R3WLSL_Pos) /*!< DDRPHY_T::DX1GTR: R3WLSL Mask */ + +#define DDRPHY_DX1GSR2_RDERR_Pos (0) /*!< DDRPHY_T::DX1GSR2: RDERR Position */ +#define DDRPHY_DX1GSR2_RDERR_Msk (0x1ul << DDRPHY_DX1GSR2_RDERR_Pos) /*!< DDRPHY_T::DX1GSR2: RDERR Mask */ + +#define DDRPHY_DX1GSR2_RDWN_Pos (1) /*!< DDRPHY_T::DX1GSR2: RDWN Position */ +#define DDRPHY_DX1GSR2_RDWN_Msk (0x1ul << DDRPHY_DX1GSR2_RDWN_Pos) /*!< DDRPHY_T::DX1GSR2: RDWN Mask */ + +#define DDRPHY_DX1GSR2_WDERR_Pos (2) /*!< DDRPHY_T::DX1GSR2: WDERR Position */ +#define DDRPHY_DX1GSR2_WDERR_Msk (0x1ul << DDRPHY_DX1GSR2_WDERR_Pos) /*!< DDRPHY_T::DX1GSR2: WDERR Mask */ + +#define DDRPHY_DX1GSR2_WDWN_Pos (3) /*!< DDRPHY_T::DX1GSR2: WDWN Position */ +#define DDRPHY_DX1GSR2_WDWN_Msk (0x1ul << DDRPHY_DX1GSR2_WDWN_Pos) /*!< DDRPHY_T::DX1GSR2: WDWN Mask */ + +#define DDRPHY_DX1GSR2_REERR_Pos (4) /*!< DDRPHY_T::DX1GSR2: REERR Position */ +#define DDRPHY_DX1GSR2_REERR_Msk (0x1ul << DDRPHY_DX1GSR2_REERR_Pos) /*!< DDRPHY_T::DX1GSR2: REERR Mask */ + +#define DDRPHY_DX1GSR2_REWN_Pos (5) /*!< DDRPHY_T::DX1GSR2: REWN Position */ +#define DDRPHY_DX1GSR2_REWN_Msk (0x1ul << DDRPHY_DX1GSR2_REWN_Pos) /*!< DDRPHY_T::DX1GSR2: REWN Mask */ + +#define DDRPHY_DX1GSR2_WEERR_Pos (6) /*!< DDRPHY_T::DX1GSR2: WEERR Position */ +#define DDRPHY_DX1GSR2_WEERR_Msk (0x1ul << DDRPHY_DX1GSR2_WEERR_Pos) /*!< DDRPHY_T::DX1GSR2: WEERR Mask */ + +#define DDRPHY_DX1GSR2_WEWN_Pos (7) /*!< DDRPHY_T::DX1GSR2: WEWN Position */ +#define DDRPHY_DX1GSR2_WEWN_Msk (0x1ul << DDRPHY_DX1GSR2_WEWN_Pos) /*!< DDRPHY_T::DX1GSR2: WEWN Mask */ + +#define DDRPHY_DX1GSR2_ESTAT_Pos (8) /*!< DDRPHY_T::DX1GSR2: ESTAT Position */ +#define DDRPHY_DX1GSR2_ESTAT_Msk (0xful << DDRPHY_DX1GSR2_ESTAT_Pos) /*!< DDRPHY_T::DX1GSR2: ESTAT Mask */ + +#define DDRPHY_DX2GCR_DXEN_Pos (0) /*!< DDRPHY_T::DX2GCR: DXEN Position */ +#define DDRPHY_DX2GCR_DXEN_Msk (0x1ul << DDRPHY_DX2GCR_DXEN_Pos) /*!< DDRPHY_T::DX2GCR: DXEN Mask */ + +#define DDRPHY_DX2GCR_DQSODT_Pos (1) /*!< DDRPHY_T::DX2GCR: DQSODT Position */ +#define DDRPHY_DX2GCR_DQSODT_Msk (0x1ul << DDRPHY_DX2GCR_DQSODT_Pos) /*!< DDRPHY_T::DX2GCR: DQSODT Mask */ + +#define DDRPHY_DX2GCR_DQODT_Pos (2) /*!< DDRPHY_T::DX2GCR: DQODT Position */ +#define DDRPHY_DX2GCR_DQODT_Msk (0x1ul << DDRPHY_DX2GCR_DQODT_Pos) /*!< DDRPHY_T::DX2GCR: DQODT Mask */ + +#define DDRPHY_DX2GCR_DXIOM_Pos (3) /*!< DDRPHY_T::DX2GCR: DXIOM Position */ +#define DDRPHY_DX2GCR_DXIOM_Msk (0x1ul << DDRPHY_DX2GCR_DXIOM_Pos) /*!< DDRPHY_T::DX2GCR: DXIOM Mask */ + +#define DDRPHY_DX2GCR_DXPDD_Pos (4) /*!< DDRPHY_T::DX2GCR: DXPDD Position */ +#define DDRPHY_DX2GCR_DXPDD_Msk (0x1ul << DDRPHY_DX2GCR_DXPDD_Pos) /*!< DDRPHY_T::DX2GCR: DXPDD Mask */ + +#define DDRPHY_DX2GCR_DXPDR_Pos (5) /*!< DDRPHY_T::DX2GCR: DXPDR Position */ +#define DDRPHY_DX2GCR_DXPDR_Msk (0x1ul << DDRPHY_DX2GCR_DXPDR_Pos) /*!< DDRPHY_T::DX2GCR: DXPDR Mask */ + +#define DDRPHY_DX2GCR_DQSRPD_Pos (6) /*!< DDRPHY_T::DX2GCR: DQSRPD Position */ +#define DDRPHY_DX2GCR_DQSRPD_Msk (0x1ul << DDRPHY_DX2GCR_DQSRPD_Pos) /*!< DDRPHY_T::DX2GCR: DQSRPD Mask */ + +#define DDRPHY_DX2GCR_DSEN_Pos (7) /*!< DDRPHY_T::DX2GCR: DSEN Position */ +#define DDRPHY_DX2GCR_DSEN_Msk (0x3ul << DDRPHY_DX2GCR_DSEN_Pos) /*!< DDRPHY_T::DX2GCR: DSEN Mask */ + +#define DDRPHY_DX2GCR_DQSRTT_Pos (9) /*!< DDRPHY_T::DX2GCR: DQSRTT Position */ +#define DDRPHY_DX2GCR_DQSRTT_Msk (0x1ul << DDRPHY_DX2GCR_DQSRTT_Pos) /*!< DDRPHY_T::DX2GCR: DQSRTT Mask */ + +#define DDRPHY_DX2GCR_DQRTT_Pos (10) /*!< DDRPHY_T::DX2GCR: DQRTT Position */ +#define DDRPHY_DX2GCR_DQRTT_Msk (0x1ul << DDRPHY_DX2GCR_DQRTT_Pos) /*!< DDRPHY_T::DX2GCR: DQRTT Mask */ + +#define DDRPHY_DX2GCR_RTTOH_Pos (11) /*!< DDRPHY_T::DX2GCR: RTTOH Position */ +#define DDRPHY_DX2GCR_RTTOH_Msk (0x3ul << DDRPHY_DX2GCR_RTTOH_Pos) /*!< DDRPHY_T::DX2GCR: RTTOH Mask */ + +#define DDRPHY_DX2GCR_RTTOAL_Pos (13) /*!< DDRPHY_T::DX2GCR: RTTOAL Position */ +#define DDRPHY_DX2GCR_RTTOAL_Msk (0x1ul << DDRPHY_DX2GCR_RTTOAL_Pos) /*!< DDRPHY_T::DX2GCR: RTTOAL Mask */ + +#define DDRPHY_DX2GCR_DXOEO_Pos (14) /*!< DDRPHY_T::DX2GCR: DXOEO Position */ +#define DDRPHY_DX2GCR_DXOEO_Msk (0x3ul << DDRPHY_DX2GCR_DXOEO_Pos) /*!< DDRPHY_T::DX2GCR: DXOEO Mask */ + +#define DDRPHY_DX2GCR_PLLRST_Pos (16) /*!< DDRPHY_T::DX2GCR: PLLRST Position */ +#define DDRPHY_DX2GCR_PLLRST_Msk (0x1ul << DDRPHY_DX2GCR_PLLRST_Pos) /*!< DDRPHY_T::DX2GCR: PLLRST Mask */ + +#define DDRPHY_DX2GCR_PLLPD_Pos (17) /*!< DDRPHY_T::DX2GCR: PLLPD Position */ +#define DDRPHY_DX2GCR_PLLPD_Msk (0x1ul << DDRPHY_DX2GCR_PLLPD_Pos) /*!< DDRPHY_T::DX2GCR: PLLPD Mask */ + +#define DDRPHY_DX2GCR_GSHIFT_Pos (18) /*!< DDRPHY_T::DX2GCR: GSHIFT Position */ +#define DDRPHY_DX2GCR_GSHIFT_Msk (0x1ul << DDRPHY_DX2GCR_GSHIFT_Pos) /*!< DDRPHY_T::DX2GCR: GSHIFT Mask */ + +#define DDRPHY_DX2GCR_PLLBYP_Pos (19) /*!< DDRPHY_T::DX2GCR: PLLBYP Position */ +#define DDRPHY_DX2GCR_PLLBYP_Msk (0x1ul << DDRPHY_DX2GCR_PLLBYP_Pos) /*!< DDRPHY_T::DX2GCR: PLLBYP Mask */ + +#define DDRPHY_DX2GCR_WLRKEN_Pos (26) /*!< DDRPHY_T::DX2GCR: WLRKEN Position */ +#define DDRPHY_DX2GCR_WLRKEN_Msk (0xful << DDRPHY_DX2GCR_WLRKEN_Pos) /*!< DDRPHY_T::DX2GCR: WLRKEN Mask */ + +#define DDRPHY_DX2GCR_MDLEN_Pos (30) /*!< DDRPHY_T::DX2GCR: MDLEN Position */ +#define DDRPHY_DX2GCR_MDLEN_Msk (0x1ul << DDRPHY_DX2GCR_MDLEN_Pos) /*!< DDRPHY_T::DX2GCR: MDLEN Mask */ + +#define DDRPHY_DX2GCR_CALBYP_Pos (31) /*!< DDRPHY_T::DX2GCR: CALBYP Position */ +#define DDRPHY_DX2GCR_CALBYP_Msk (0x1ul << DDRPHY_DX2GCR_CALBYP_Pos) /*!< DDRPHY_T::DX2GCR: CALBYP Mask */ + +#define DDRPHY_DX2GSR0_WDQCAL_Pos (0) /*!< DDRPHY_T::DX2GSR0: WDQCAL Position */ +#define DDRPHY_DX2GSR0_WDQCAL_Msk (0x1ul << DDRPHY_DX2GSR0_WDQCAL_Pos) /*!< DDRPHY_T::DX2GSR0: WDQCAL Mask */ + +#define DDRPHY_DX2GSR0_RDQSCAL_Pos (1) /*!< DDRPHY_T::DX2GSR0: RDQSCAL Position */ +#define DDRPHY_DX2GSR0_RDQSCAL_Msk (0x1ul << DDRPHY_DX2GSR0_RDQSCAL_Pos) /*!< DDRPHY_T::DX2GSR0: RDQSCAL Mask */ + +#define DDRPHY_DX2GSR0_RDQSNCAL_Pos (2) /*!< DDRPHY_T::DX2GSR0: RDQSNCAL Position */ +#define DDRPHY_DX2GSR0_RDQSNCAL_Msk (0x1ul << DDRPHY_DX2GSR0_RDQSNCAL_Pos) /*!< DDRPHY_T::DX2GSR0: RDQSNCAL Mask */ + +#define DDRPHY_DX2GSR0_GDQSCAL_Pos (3) /*!< DDRPHY_T::DX2GSR0: GDQSCAL Position */ +#define DDRPHY_DX2GSR0_GDQSCAL_Msk (0x1ul << DDRPHY_DX2GSR0_GDQSCAL_Pos) /*!< DDRPHY_T::DX2GSR0: GDQSCAL Mask */ + +#define DDRPHY_DX2GSR0_WLCAL_Pos (4) /*!< DDRPHY_T::DX2GSR0: WLCAL Position */ +#define DDRPHY_DX2GSR0_WLCAL_Msk (0x1ul << DDRPHY_DX2GSR0_WLCAL_Pos) /*!< DDRPHY_T::DX2GSR0: WLCAL Mask */ + +#define DDRPHY_DX2GSR0_WLDONE_Pos (5) /*!< DDRPHY_T::DX2GSR0: WLDONE Position */ +#define DDRPHY_DX2GSR0_WLDONE_Msk (0x1ul << DDRPHY_DX2GSR0_WLDONE_Pos) /*!< DDRPHY_T::DX2GSR0: WLDONE Mask */ + +#define DDRPHY_DX2GSR0_WLERR_Pos (6) /*!< DDRPHY_T::DX2GSR0: WLERR Position */ +#define DDRPHY_DX2GSR0_WLERR_Msk (0x1ul << DDRPHY_DX2GSR0_WLERR_Pos) /*!< DDRPHY_T::DX2GSR0: WLERR Mask */ + +#define DDRPHY_DX2GSR0_WLPRD_Pos (7) /*!< DDRPHY_T::DX2GSR0: WLPRD Position */ +#define DDRPHY_DX2GSR0_WLPRD_Msk (0xfful << DDRPHY_DX2GSR0_WLPRD_Pos) /*!< DDRPHY_T::DX2GSR0: WLPRD Mask */ + +#define DDRPHY_DX2GSR0_DPLOCK_Pos (15) /*!< DDRPHY_T::DX2GSR0: DPLOCK Position */ +#define DDRPHY_DX2GSR0_DPLOCK_Msk (0x1ul << DDRPHY_DX2GSR0_DPLOCK_Pos) /*!< DDRPHY_T::DX2GSR0: DPLOCK Mask */ + +#define DDRPHY_DX2GSR0_GDQSPRD_Pos (16) /*!< DDRPHY_T::DX2GSR0: GDQSPRD Position */ +#define DDRPHY_DX2GSR0_GDQSPRD_Msk (0xfful << DDRPHY_DX2GSR0_GDQSPRD_Pos) /*!< DDRPHY_T::DX2GSR0: GDQSPRD Mask */ + +#define DDRPHY_DX2GSR0_QSGERR_Pos (24) /*!< DDRPHY_T::DX2GSR0: QSGERR Position */ +#define DDRPHY_DX2GSR0_QSGERR_Msk (0xful << DDRPHY_DX2GSR0_QSGERR_Pos) /*!< DDRPHY_T::DX2GSR0: QSGERR Mask */ + +#define DDRPHY_DX2GSR0_WLDQ_Pos (28) /*!< DDRPHY_T::DX2GSR0: WLDQ Position */ +#define DDRPHY_DX2GSR0_WLDQ_Msk (0x1ul << DDRPHY_DX2GSR0_WLDQ_Pos) /*!< DDRPHY_T::DX2GSR0: WLDQ Mask */ + +#define DDRPHY_DX2GSR1_DLTDONE_Pos (0) /*!< DDRPHY_T::DX2GSR1: DLTDONE Position */ +#define DDRPHY_DX2GSR1_DLTDONE_Msk (0x1ul << DDRPHY_DX2GSR1_DLTDONE_Pos) /*!< DDRPHY_T::DX2GSR1: DLTDONE Mask */ + +#define DDRPHY_DX2GSR1_DLTCODE_Pos (1) /*!< DDRPHY_T::DX2GSR1: DLTCODE Position */ +#define DDRPHY_DX2GSR1_DLTCODE_Msk (0xfffffful << DDRPHY_DX2GSR1_DLTCODE_Pos) /*!< DDRPHY_T::DX2GSR1: DLTCODE Mask */ + +#define DDRPHY_DX2BDLR0_DQ0WBD_Pos (0) /*!< DDRPHY_T::DX2BDLR0: DQ0WBD Position */ +#define DDRPHY_DX2BDLR0_DQ0WBD_Msk (0x3ful << DDRPHY_DX2BDLR0_DQ0WBD_Pos) /*!< DDRPHY_T::DX2BDLR0: DQ0WBD Mask */ + +#define DDRPHY_DX2BDLR0_DQ1WBD_Pos (6) /*!< DDRPHY_T::DX2BDLR0: DQ1WBD Position */ +#define DDRPHY_DX2BDLR0_DQ1WBD_Msk (0x3ful << DDRPHY_DX2BDLR0_DQ1WBD_Pos) /*!< DDRPHY_T::DX2BDLR0: DQ1WBD Mask */ + +#define DDRPHY_DX2BDLR0_DQ2WBD_Pos (12) /*!< DDRPHY_T::DX2BDLR0: DQ2WBD Position */ +#define DDRPHY_DX2BDLR0_DQ2WBD_Msk (0x3ful << DDRPHY_DX2BDLR0_DQ2WBD_Pos) /*!< DDRPHY_T::DX2BDLR0: DQ2WBD Mask */ + +#define DDRPHY_DX2BDLR0_DQ3WBD_Pos (18) /*!< DDRPHY_T::DX2BDLR0: DQ3WBD Position */ +#define DDRPHY_DX2BDLR0_DQ3WBD_Msk (0x3ful << DDRPHY_DX2BDLR0_DQ3WBD_Pos) /*!< DDRPHY_T::DX2BDLR0: DQ3WBD Mask */ + +#define DDRPHY_DX2BDLR0_DQ4WBD_Pos (24) /*!< DDRPHY_T::DX2BDLR0: DQ4WBD Position */ +#define DDRPHY_DX2BDLR0_DQ4WBD_Msk (0x3ful << DDRPHY_DX2BDLR0_DQ4WBD_Pos) /*!< DDRPHY_T::DX2BDLR0: DQ4WBD Mask */ + +#define DDRPHY_DX2BDLR1_DQ5WBD_Pos (0) /*!< DDRPHY_T::DX2BDLR1: DQ5WBD Position */ +#define DDRPHY_DX2BDLR1_DQ5WBD_Msk (0x3ful << DDRPHY_DX2BDLR1_DQ5WBD_Pos) /*!< DDRPHY_T::DX2BDLR1: DQ5WBD Mask */ + +#define DDRPHY_DX2BDLR1_DQ6WBD_Pos (6) /*!< DDRPHY_T::DX2BDLR1: DQ6WBD Position */ +#define DDRPHY_DX2BDLR1_DQ6WBD_Msk (0x3ful << DDRPHY_DX2BDLR1_DQ6WBD_Pos) /*!< DDRPHY_T::DX2BDLR1: DQ6WBD Mask */ + +#define DDRPHY_DX2BDLR1_DQ7WBD_Pos (12) /*!< DDRPHY_T::DX2BDLR1: DQ7WBD Position */ +#define DDRPHY_DX2BDLR1_DQ7WBD_Msk (0x3ful << DDRPHY_DX2BDLR1_DQ7WBD_Pos) /*!< DDRPHY_T::DX2BDLR1: DQ7WBD Mask */ + +#define DDRPHY_DX2BDLR1_DMWBD_Pos (18) /*!< DDRPHY_T::DX2BDLR1: DMWBD Position */ +#define DDRPHY_DX2BDLR1_DMWBD_Msk (0x3ful << DDRPHY_DX2BDLR1_DMWBD_Pos) /*!< DDRPHY_T::DX2BDLR1: DMWBD Mask */ + +#define DDRPHY_DX2BDLR1_DSWBD_Pos (24) /*!< DDRPHY_T::DX2BDLR1: DSWBD Position */ +#define DDRPHY_DX2BDLR1_DSWBD_Msk (0x3ful << DDRPHY_DX2BDLR1_DSWBD_Pos) /*!< DDRPHY_T::DX2BDLR1: DSWBD Mask */ + +#define DDRPHY_DX2BDLR2_DSOEBD_Pos (0) /*!< DDRPHY_T::DX2BDLR2: DSOEBD Position */ +#define DDRPHY_DX2BDLR2_DSOEBD_Msk (0x3ful << DDRPHY_DX2BDLR2_DSOEBD_Pos) /*!< DDRPHY_T::DX2BDLR2: DSOEBD Mask */ + +#define DDRPHY_DX2BDLR2_DQOEBD_Pos (6) /*!< DDRPHY_T::DX2BDLR2: DQOEBD Position */ +#define DDRPHY_DX2BDLR2_DQOEBD_Msk (0x3ful << DDRPHY_DX2BDLR2_DQOEBD_Pos) /*!< DDRPHY_T::DX2BDLR2: DQOEBD Mask */ + +#define DDRPHY_DX2BDLR2_DSRBD_Pos (12) /*!< DDRPHY_T::DX2BDLR2: DSRBD Position */ +#define DDRPHY_DX2BDLR2_DSRBD_Msk (0x3ful << DDRPHY_DX2BDLR2_DSRBD_Pos) /*!< DDRPHY_T::DX2BDLR2: DSRBD Mask */ + +#define DDRPHY_DX2BDLR2_DSNRBD_Pos (18) /*!< DDRPHY_T::DX2BDLR2: DSNRBD Position */ +#define DDRPHY_DX2BDLR2_DSNRBD_Msk (0x3ful << DDRPHY_DX2BDLR2_DSNRBD_Pos) /*!< DDRPHY_T::DX2BDLR2: DSNRBD Mask */ + +#define DDRPHY_DX2BDLR3_DQ0RBD_Pos (0) /*!< DDRPHY_T::DX2BDLR3: DQ0RBD Position */ +#define DDRPHY_DX2BDLR3_DQ0RBD_Msk (0x3ful << DDRPHY_DX2BDLR3_DQ0RBD_Pos) /*!< DDRPHY_T::DX2BDLR3: DQ0RBD Mask */ + +#define DDRPHY_DX2BDLR3_DQ1RBD_Pos (6) /*!< DDRPHY_T::DX2BDLR3: DQ1RBD Position */ +#define DDRPHY_DX2BDLR3_DQ1RBD_Msk (0x3ful << DDRPHY_DX2BDLR3_DQ1RBD_Pos) /*!< DDRPHY_T::DX2BDLR3: DQ1RBD Mask */ + +#define DDRPHY_DX2BDLR3_DQ2RBD_Pos (12) /*!< DDRPHY_T::DX2BDLR3: DQ2RBD Position */ +#define DDRPHY_DX2BDLR3_DQ2RBD_Msk (0x3ful << DDRPHY_DX2BDLR3_DQ2RBD_Pos) /*!< DDRPHY_T::DX2BDLR3: DQ2RBD Mask */ + +#define DDRPHY_DX2BDLR3_DQ3RBD_Pos (18) /*!< DDRPHY_T::DX2BDLR3: DQ3RBD Position */ +#define DDRPHY_DX2BDLR3_DQ3RBD_Msk (0x3ful << DDRPHY_DX2BDLR3_DQ3RBD_Pos) /*!< DDRPHY_T::DX2BDLR3: DQ3RBD Mask */ + +#define DDRPHY_DX2BDLR3_DQ4RBD_Pos (24) /*!< DDRPHY_T::DX2BDLR3: DQ4RBD Position */ +#define DDRPHY_DX2BDLR3_DQ4RBD_Msk (0x3ful << DDRPHY_DX2BDLR3_DQ4RBD_Pos) /*!< DDRPHY_T::DX2BDLR3: DQ4RBD Mask */ + +#define DDRPHY_DX2BDLR4_DQ5RBD_Pos (0) /*!< DDRPHY_T::DX2BDLR4: DQ5RBD Position */ +#define DDRPHY_DX2BDLR4_DQ5RBD_Msk (0x3ful << DDRPHY_DX2BDLR4_DQ5RBD_Pos) /*!< DDRPHY_T::DX2BDLR4: DQ5RBD Mask */ + +#define DDRPHY_DX2BDLR4_DQ6RBD_Pos (6) /*!< DDRPHY_T::DX2BDLR4: DQ6RBD Position */ +#define DDRPHY_DX2BDLR4_DQ6RBD_Msk (0x3ful << DDRPHY_DX2BDLR4_DQ6RBD_Pos) /*!< DDRPHY_T::DX2BDLR4: DQ6RBD Mask */ + +#define DDRPHY_DX2BDLR4_DQ7RBD_Pos (12) /*!< DDRPHY_T::DX2BDLR4: DQ7RBD Position */ +#define DDRPHY_DX2BDLR4_DQ7RBD_Msk (0x3ful << DDRPHY_DX2BDLR4_DQ7RBD_Pos) /*!< DDRPHY_T::DX2BDLR4: DQ7RBD Mask */ + +#define DDRPHY_DX2BDLR4_DMRBD_Pos (18) /*!< DDRPHY_T::DX2BDLR4: DMRBD Position */ +#define DDRPHY_DX2BDLR4_DMRBD_Msk (0x3ful << DDRPHY_DX2BDLR4_DMRBD_Pos) /*!< DDRPHY_T::DX2BDLR4: DMRBD Mask */ + +#define DDRPHY_DX2LCDLR0_R0WLD_Pos (0) /*!< DDRPHY_T::DX2LCDLR0: R0WLD Position */ +#define DDRPHY_DX2LCDLR0_R0WLD_Msk (0xfful << DDRPHY_DX2LCDLR0_R0WLD_Pos) /*!< DDRPHY_T::DX2LCDLR0: R0WLD Mask */ + +#define DDRPHY_DX2LCDLR0_R1WLD_Pos (8) /*!< DDRPHY_T::DX2LCDLR0: R1WLD Position */ +#define DDRPHY_DX2LCDLR0_R1WLD_Msk (0xfful << DDRPHY_DX2LCDLR0_R1WLD_Pos) /*!< DDRPHY_T::DX2LCDLR0: R1WLD Mask */ + +#define DDRPHY_DX2LCDLR0_R2WLD_Pos (16) /*!< DDRPHY_T::DX2LCDLR0: R2WLD Position */ +#define DDRPHY_DX2LCDLR0_R2WLD_Msk (0xfful << DDRPHY_DX2LCDLR0_R2WLD_Pos) /*!< DDRPHY_T::DX2LCDLR0: R2WLD Mask */ + +#define DDRPHY_DX2LCDLR0_R3WLD_Pos (24) /*!< DDRPHY_T::DX2LCDLR0: R3WLD Position */ +#define DDRPHY_DX2LCDLR0_R3WLD_Msk (0xfful << DDRPHY_DX2LCDLR0_R3WLD_Pos) /*!< DDRPHY_T::DX2LCDLR0: R3WLD Mask */ + +#define DDRPHY_DX2LCDLR1_WDQD_Pos (0) /*!< DDRPHY_T::DX2LCDLR1: WDQD Position */ +#define DDRPHY_DX2LCDLR1_WDQD_Msk (0xfful << DDRPHY_DX2LCDLR1_WDQD_Pos) /*!< DDRPHY_T::DX2LCDLR1: WDQD Mask */ + +#define DDRPHY_DX2LCDLR1_RDQSD_Pos (8) /*!< DDRPHY_T::DX2LCDLR1: RDQSD Position */ +#define DDRPHY_DX2LCDLR1_RDQSD_Msk (0xfful << DDRPHY_DX2LCDLR1_RDQSD_Pos) /*!< DDRPHY_T::DX2LCDLR1: RDQSD Mask */ + +#define DDRPHY_DX2LCDLR1_RDQSND_Pos (16) /*!< DDRPHY_T::DX2LCDLR1: RDQSND Position */ +#define DDRPHY_DX2LCDLR1_RDQSND_Msk (0xfful << DDRPHY_DX2LCDLR1_RDQSND_Pos) /*!< DDRPHY_T::DX2LCDLR1: RDQSND Mask */ + +#define DDRPHY_DX2LCDLR2_R0DQSGD_Pos (0) /*!< DDRPHY_T::DX2LCDLR2: R0DQSGD Position */ +#define DDRPHY_DX2LCDLR2_R0DQSGD_Msk (0xfful << DDRPHY_DX2LCDLR2_R0DQSGD_Pos) /*!< DDRPHY_T::DX2LCDLR2: R0DQSGD Mask */ + +#define DDRPHY_DX2LCDLR2_R1DQSGD_Pos (8) /*!< DDRPHY_T::DX2LCDLR2: R1DQSGD Position */ +#define DDRPHY_DX2LCDLR2_R1DQSGD_Msk (0xfful << DDRPHY_DX2LCDLR2_R1DQSGD_Pos) /*!< DDRPHY_T::DX2LCDLR2: R1DQSGD Mask */ + +#define DDRPHY_DX2LCDLR2_R2DQSGD_Pos (16) /*!< DDRPHY_T::DX2LCDLR2: R2DQSGD Position */ +#define DDRPHY_DX2LCDLR2_R2DQSGD_Msk (0xfful << DDRPHY_DX2LCDLR2_R2DQSGD_Pos) /*!< DDRPHY_T::DX2LCDLR2: R2DQSGD Mask */ + +#define DDRPHY_DX2LCDLR2_R3DQSGD_Pos (24) /*!< DDRPHY_T::DX2LCDLR2: R3DQSGD Position */ +#define DDRPHY_DX2LCDLR2_R3DQSGD_Msk (0xfful << DDRPHY_DX2LCDLR2_R3DQSGD_Pos) /*!< DDRPHY_T::DX2LCDLR2: R3DQSGD Mask */ + +#define DDRPHY_DX2MDLR_IPRD_Pos (0) /*!< DDRPHY_T::DX2MDLR: IPRD Position */ +#define DDRPHY_DX2MDLR_IPRD_Msk (0xfful << DDRPHY_DX2MDLR_IPRD_Pos) /*!< DDRPHY_T::DX2MDLR: IPRD Mask */ + +#define DDRPHY_DX2MDLR_TPRD_Pos (8) /*!< DDRPHY_T::DX2MDLR: TPRD Position */ +#define DDRPHY_DX2MDLR_TPRD_Msk (0xfful << DDRPHY_DX2MDLR_TPRD_Pos) /*!< DDRPHY_T::DX2MDLR: TPRD Mask */ + +#define DDRPHY_DX2MDLR_MDLD_Pos (16) /*!< DDRPHY_T::DX2MDLR: MDLD Position */ +#define DDRPHY_DX2MDLR_MDLD_Msk (0xfful << DDRPHY_DX2MDLR_MDLD_Pos) /*!< DDRPHY_T::DX2MDLR: MDLD Mask */ + +#define DDRPHY_DX2GTR_R0DGSL_Pos (0) /*!< DDRPHY_T::DX2GTR: R0DGSL Position */ +#define DDRPHY_DX2GTR_R0DGSL_Msk (0x7ul << DDRPHY_DX2GTR_R0DGSL_Pos) /*!< DDRPHY_T::DX2GTR: R0DGSL Mask */ + +#define DDRPHY_DX2GTR_R1DGSL_Pos (3) /*!< DDRPHY_T::DX2GTR: R1DGSL Position */ +#define DDRPHY_DX2GTR_R1DGSL_Msk (0x7ul << DDRPHY_DX2GTR_R1DGSL_Pos) /*!< DDRPHY_T::DX2GTR: R1DGSL Mask */ + +#define DDRPHY_DX2GTR_R2DGSL_Pos (6) /*!< DDRPHY_T::DX2GTR: R2DGSL Position */ +#define DDRPHY_DX2GTR_R2DGSL_Msk (0x7ul << DDRPHY_DX2GTR_R2DGSL_Pos) /*!< DDRPHY_T::DX2GTR: R2DGSL Mask */ + +#define DDRPHY_DX2GTR_R3DGSL_Pos (9) /*!< DDRPHY_T::DX2GTR: R3DGSL Position */ +#define DDRPHY_DX2GTR_R3DGSL_Msk (0x7ul << DDRPHY_DX2GTR_R3DGSL_Pos) /*!< DDRPHY_T::DX2GTR: R3DGSL Mask */ + +#define DDRPHY_DX2GTR_R0WLSL_Pos (12) /*!< DDRPHY_T::DX2GTR: R0WLSL Position */ +#define DDRPHY_DX2GTR_R0WLSL_Msk (0x3ul << DDRPHY_DX2GTR_R0WLSL_Pos) /*!< DDRPHY_T::DX2GTR: R0WLSL Mask */ + +#define DDRPHY_DX2GTR_R1WLSL_Pos (14) /*!< DDRPHY_T::DX2GTR: R1WLSL Position */ +#define DDRPHY_DX2GTR_R1WLSL_Msk (0x3ul << DDRPHY_DX2GTR_R1WLSL_Pos) /*!< DDRPHY_T::DX2GTR: R1WLSL Mask */ + +#define DDRPHY_DX2GTR_R2WLSL_Pos (16) /*!< DDRPHY_T::DX2GTR: R2WLSL Position */ +#define DDRPHY_DX2GTR_R2WLSL_Msk (0x3ul << DDRPHY_DX2GTR_R2WLSL_Pos) /*!< DDRPHY_T::DX2GTR: R2WLSL Mask */ + +#define DDRPHY_DX2GTR_R3WLSL_Pos (18) /*!< DDRPHY_T::DX2GTR: R3WLSL Position */ +#define DDRPHY_DX2GTR_R3WLSL_Msk (0x3ul << DDRPHY_DX2GTR_R3WLSL_Pos) /*!< DDRPHY_T::DX2GTR: R3WLSL Mask */ + +#define DDRPHY_DX2GSR2_RDERR_Pos (0) /*!< DDRPHY_T::DX2GSR2: RDERR Position */ +#define DDRPHY_DX2GSR2_RDERR_Msk (0x1ul << DDRPHY_DX2GSR2_RDERR_Pos) /*!< DDRPHY_T::DX2GSR2: RDERR Mask */ + +#define DDRPHY_DX2GSR2_RDWN_Pos (1) /*!< DDRPHY_T::DX2GSR2: RDWN Position */ +#define DDRPHY_DX2GSR2_RDWN_Msk (0x1ul << DDRPHY_DX2GSR2_RDWN_Pos) /*!< DDRPHY_T::DX2GSR2: RDWN Mask */ + +#define DDRPHY_DX2GSR2_WDERR_Pos (2) /*!< DDRPHY_T::DX2GSR2: WDERR Position */ +#define DDRPHY_DX2GSR2_WDERR_Msk (0x1ul << DDRPHY_DX2GSR2_WDERR_Pos) /*!< DDRPHY_T::DX2GSR2: WDERR Mask */ + +#define DDRPHY_DX2GSR2_WDWN_Pos (3) /*!< DDRPHY_T::DX2GSR2: WDWN Position */ +#define DDRPHY_DX2GSR2_WDWN_Msk (0x1ul << DDRPHY_DX2GSR2_WDWN_Pos) /*!< DDRPHY_T::DX2GSR2: WDWN Mask */ + +#define DDRPHY_DX2GSR2_REERR_Pos (4) /*!< DDRPHY_T::DX2GSR2: REERR Position */ +#define DDRPHY_DX2GSR2_REERR_Msk (0x1ul << DDRPHY_DX2GSR2_REERR_Pos) /*!< DDRPHY_T::DX2GSR2: REERR Mask */ + +#define DDRPHY_DX2GSR2_REWN_Pos (5) /*!< DDRPHY_T::DX2GSR2: REWN Position */ +#define DDRPHY_DX2GSR2_REWN_Msk (0x1ul << DDRPHY_DX2GSR2_REWN_Pos) /*!< DDRPHY_T::DX2GSR2: REWN Mask */ + +#define DDRPHY_DX2GSR2_WEERR_Pos (6) /*!< DDRPHY_T::DX2GSR2: WEERR Position */ +#define DDRPHY_DX2GSR2_WEERR_Msk (0x1ul << DDRPHY_DX2GSR2_WEERR_Pos) /*!< DDRPHY_T::DX2GSR2: WEERR Mask */ + +#define DDRPHY_DX2GSR2_WEWN_Pos (7) /*!< DDRPHY_T::DX2GSR2: WEWN Position */ +#define DDRPHY_DX2GSR2_WEWN_Msk (0x1ul << DDRPHY_DX2GSR2_WEWN_Pos) /*!< DDRPHY_T::DX2GSR2: WEWN Mask */ + +#define DDRPHY_DX2GSR2_ESTAT_Pos (8) /*!< DDRPHY_T::DX2GSR2: ESTAT Position */ +#define DDRPHY_DX2GSR2_ESTAT_Msk (0xful << DDRPHY_DX2GSR2_ESTAT_Pos) /*!< DDRPHY_T::DX2GSR2: ESTAT Mask */ + +#define DDRPHY_DX3GCR_DXEN_Pos (0) /*!< DDRPHY_T::DX3GCR: DXEN Position */ +#define DDRPHY_DX3GCR_DXEN_Msk (0x1ul << DDRPHY_DX3GCR_DXEN_Pos) /*!< DDRPHY_T::DX3GCR: DXEN Mask */ + +#define DDRPHY_DX3GCR_DQSODT_Pos (1) /*!< DDRPHY_T::DX3GCR: DQSODT Position */ +#define DDRPHY_DX3GCR_DQSODT_Msk (0x1ul << DDRPHY_DX3GCR_DQSODT_Pos) /*!< DDRPHY_T::DX3GCR: DQSODT Mask */ + +#define DDRPHY_DX3GCR_DQODT_Pos (2) /*!< DDRPHY_T::DX3GCR: DQODT Position */ +#define DDRPHY_DX3GCR_DQODT_Msk (0x1ul << DDRPHY_DX3GCR_DQODT_Pos) /*!< DDRPHY_T::DX3GCR: DQODT Mask */ + +#define DDRPHY_DX3GCR_DXIOM_Pos (3) /*!< DDRPHY_T::DX3GCR: DXIOM Position */ +#define DDRPHY_DX3GCR_DXIOM_Msk (0x1ul << DDRPHY_DX3GCR_DXIOM_Pos) /*!< DDRPHY_T::DX3GCR: DXIOM Mask */ + +#define DDRPHY_DX3GCR_DXPDD_Pos (4) /*!< DDRPHY_T::DX3GCR: DXPDD Position */ +#define DDRPHY_DX3GCR_DXPDD_Msk (0x1ul << DDRPHY_DX3GCR_DXPDD_Pos) /*!< DDRPHY_T::DX3GCR: DXPDD Mask */ + +#define DDRPHY_DX3GCR_DXPDR_Pos (5) /*!< DDRPHY_T::DX3GCR: DXPDR Position */ +#define DDRPHY_DX3GCR_DXPDR_Msk (0x1ul << DDRPHY_DX3GCR_DXPDR_Pos) /*!< DDRPHY_T::DX3GCR: DXPDR Mask */ + +#define DDRPHY_DX3GCR_DQSRPD_Pos (6) /*!< DDRPHY_T::DX3GCR: DQSRPD Position */ +#define DDRPHY_DX3GCR_DQSRPD_Msk (0x1ul << DDRPHY_DX3GCR_DQSRPD_Pos) /*!< DDRPHY_T::DX3GCR: DQSRPD Mask */ + +#define DDRPHY_DX3GCR_DSEN_Pos (7) /*!< DDRPHY_T::DX3GCR: DSEN Position */ +#define DDRPHY_DX3GCR_DSEN_Msk (0x3ul << DDRPHY_DX3GCR_DSEN_Pos) /*!< DDRPHY_T::DX3GCR: DSEN Mask */ + +#define DDRPHY_DX3GCR_DQSRTT_Pos (9) /*!< DDRPHY_T::DX3GCR: DQSRTT Position */ +#define DDRPHY_DX3GCR_DQSRTT_Msk (0x1ul << DDRPHY_DX3GCR_DQSRTT_Pos) /*!< DDRPHY_T::DX3GCR: DQSRTT Mask */ + +#define DDRPHY_DX3GCR_DQRTT_Pos (10) /*!< DDRPHY_T::DX3GCR: DQRTT Position */ +#define DDRPHY_DX3GCR_DQRTT_Msk (0x1ul << DDRPHY_DX3GCR_DQRTT_Pos) /*!< DDRPHY_T::DX3GCR: DQRTT Mask */ + +#define DDRPHY_DX3GCR_RTTOH_Pos (11) /*!< DDRPHY_T::DX3GCR: RTTOH Position */ +#define DDRPHY_DX3GCR_RTTOH_Msk (0x3ul << DDRPHY_DX3GCR_RTTOH_Pos) /*!< DDRPHY_T::DX3GCR: RTTOH Mask */ + +#define DDRPHY_DX3GCR_RTTOAL_Pos (13) /*!< DDRPHY_T::DX3GCR: RTTOAL Position */ +#define DDRPHY_DX3GCR_RTTOAL_Msk (0x1ul << DDRPHY_DX3GCR_RTTOAL_Pos) /*!< DDRPHY_T::DX3GCR: RTTOAL Mask */ + +#define DDRPHY_DX3GCR_DXOEO_Pos (14) /*!< DDRPHY_T::DX3GCR: DXOEO Position */ +#define DDRPHY_DX3GCR_DXOEO_Msk (0x3ul << DDRPHY_DX3GCR_DXOEO_Pos) /*!< DDRPHY_T::DX3GCR: DXOEO Mask */ + +#define DDRPHY_DX3GCR_PLLRST_Pos (16) /*!< DDRPHY_T::DX3GCR: PLLRST Position */ +#define DDRPHY_DX3GCR_PLLRST_Msk (0x1ul << DDRPHY_DX3GCR_PLLRST_Pos) /*!< DDRPHY_T::DX3GCR: PLLRST Mask */ + +#define DDRPHY_DX3GCR_PLLPD_Pos (17) /*!< DDRPHY_T::DX3GCR: PLLPD Position */ +#define DDRPHY_DX3GCR_PLLPD_Msk (0x1ul << DDRPHY_DX3GCR_PLLPD_Pos) /*!< DDRPHY_T::DX3GCR: PLLPD Mask */ + +#define DDRPHY_DX3GCR_GSHIFT_Pos (18) /*!< DDRPHY_T::DX3GCR: GSHIFT Position */ +#define DDRPHY_DX3GCR_GSHIFT_Msk (0x1ul << DDRPHY_DX3GCR_GSHIFT_Pos) /*!< DDRPHY_T::DX3GCR: GSHIFT Mask */ + +#define DDRPHY_DX3GCR_PLLBYP_Pos (19) /*!< DDRPHY_T::DX3GCR: PLLBYP Position */ +#define DDRPHY_DX3GCR_PLLBYP_Msk (0x1ul << DDRPHY_DX3GCR_PLLBYP_Pos) /*!< DDRPHY_T::DX3GCR: PLLBYP Mask */ + +#define DDRPHY_DX3GCR_WLRKEN_Pos (26) /*!< DDRPHY_T::DX3GCR: WLRKEN Position */ +#define DDRPHY_DX3GCR_WLRKEN_Msk (0xful << DDRPHY_DX3GCR_WLRKEN_Pos) /*!< DDRPHY_T::DX3GCR: WLRKEN Mask */ + +#define DDRPHY_DX3GCR_MDLEN_Pos (30) /*!< DDRPHY_T::DX3GCR: MDLEN Position */ +#define DDRPHY_DX3GCR_MDLEN_Msk (0x1ul << DDRPHY_DX3GCR_MDLEN_Pos) /*!< DDRPHY_T::DX3GCR: MDLEN Mask */ + +#define DDRPHY_DX3GCR_CALBYP_Pos (31) /*!< DDRPHY_T::DX3GCR: CALBYP Position */ +#define DDRPHY_DX3GCR_CALBYP_Msk (0x1ul << DDRPHY_DX3GCR_CALBYP_Pos) /*!< DDRPHY_T::DX3GCR: CALBYP Mask */ + +#define DDRPHY_DX3GSR0_WDQCAL_Pos (0) /*!< DDRPHY_T::DX3GSR0: WDQCAL Position */ +#define DDRPHY_DX3GSR0_WDQCAL_Msk (0x1ul << DDRPHY_DX3GSR0_WDQCAL_Pos) /*!< DDRPHY_T::DX3GSR0: WDQCAL Mask */ + +#define DDRPHY_DX3GSR0_RDQSCAL_Pos (1) /*!< DDRPHY_T::DX3GSR0: RDQSCAL Position */ +#define DDRPHY_DX3GSR0_RDQSCAL_Msk (0x1ul << DDRPHY_DX3GSR0_RDQSCAL_Pos) /*!< DDRPHY_T::DX3GSR0: RDQSCAL Mask */ + +#define DDRPHY_DX3GSR0_RDQSNCAL_Pos (2) /*!< DDRPHY_T::DX3GSR0: RDQSNCAL Position */ +#define DDRPHY_DX3GSR0_RDQSNCAL_Msk (0x1ul << DDRPHY_DX3GSR0_RDQSNCAL_Pos) /*!< DDRPHY_T::DX3GSR0: RDQSNCAL Mask */ + +#define DDRPHY_DX3GSR0_GDQSCAL_Pos (3) /*!< DDRPHY_T::DX3GSR0: GDQSCAL Position */ +#define DDRPHY_DX3GSR0_GDQSCAL_Msk (0x1ul << DDRPHY_DX3GSR0_GDQSCAL_Pos) /*!< DDRPHY_T::DX3GSR0: GDQSCAL Mask */ + +#define DDRPHY_DX3GSR0_WLCAL_Pos (4) /*!< DDRPHY_T::DX3GSR0: WLCAL Position */ +#define DDRPHY_DX3GSR0_WLCAL_Msk (0x1ul << DDRPHY_DX3GSR0_WLCAL_Pos) /*!< DDRPHY_T::DX3GSR0: WLCAL Mask */ + +#define DDRPHY_DX3GSR0_WLDONE_Pos (5) /*!< DDRPHY_T::DX3GSR0: WLDONE Position */ +#define DDRPHY_DX3GSR0_WLDONE_Msk (0x1ul << DDRPHY_DX3GSR0_WLDONE_Pos) /*!< DDRPHY_T::DX3GSR0: WLDONE Mask */ + +#define DDRPHY_DX3GSR0_WLERR_Pos (6) /*!< DDRPHY_T::DX3GSR0: WLERR Position */ +#define DDRPHY_DX3GSR0_WLERR_Msk (0x1ul << DDRPHY_DX3GSR0_WLERR_Pos) /*!< DDRPHY_T::DX3GSR0: WLERR Mask */ + +#define DDRPHY_DX3GSR0_WLPRD_Pos (7) /*!< DDRPHY_T::DX3GSR0: WLPRD Position */ +#define DDRPHY_DX3GSR0_WLPRD_Msk (0xfful << DDRPHY_DX3GSR0_WLPRD_Pos) /*!< DDRPHY_T::DX3GSR0: WLPRD Mask */ + +#define DDRPHY_DX3GSR0_DPLOCK_Pos (15) /*!< DDRPHY_T::DX3GSR0: DPLOCK Position */ +#define DDRPHY_DX3GSR0_DPLOCK_Msk (0x1ul << DDRPHY_DX3GSR0_DPLOCK_Pos) /*!< DDRPHY_T::DX3GSR0: DPLOCK Mask */ + +#define DDRPHY_DX3GSR0_GDQSPRD_Pos (16) /*!< DDRPHY_T::DX3GSR0: GDQSPRD Position */ +#define DDRPHY_DX3GSR0_GDQSPRD_Msk (0xfful << DDRPHY_DX3GSR0_GDQSPRD_Pos) /*!< DDRPHY_T::DX3GSR0: GDQSPRD Mask */ + +#define DDRPHY_DX3GSR0_QSGERR_Pos (24) /*!< DDRPHY_T::DX3GSR0: QSGERR Position */ +#define DDRPHY_DX3GSR0_QSGERR_Msk (0xful << DDRPHY_DX3GSR0_QSGERR_Pos) /*!< DDRPHY_T::DX3GSR0: QSGERR Mask */ + +#define DDRPHY_DX3GSR0_WLDQ_Pos (28) /*!< DDRPHY_T::DX3GSR0: WLDQ Position */ +#define DDRPHY_DX3GSR0_WLDQ_Msk (0x1ul << DDRPHY_DX3GSR0_WLDQ_Pos) /*!< DDRPHY_T::DX3GSR0: WLDQ Mask */ + +#define DDRPHY_DX3GSR1_DLTDONE_Pos (0) /*!< DDRPHY_T::DX3GSR1: DLTDONE Position */ +#define DDRPHY_DX3GSR1_DLTDONE_Msk (0x1ul << DDRPHY_DX3GSR1_DLTDONE_Pos) /*!< DDRPHY_T::DX3GSR1: DLTDONE Mask */ + +#define DDRPHY_DX3GSR1_DLTCODE_Pos (1) /*!< DDRPHY_T::DX3GSR1: DLTCODE Position */ +#define DDRPHY_DX3GSR1_DLTCODE_Msk (0xfffffful << DDRPHY_DX3GSR1_DLTCODE_Pos) /*!< DDRPHY_T::DX3GSR1: DLTCODE Mask */ + +#define DDRPHY_DX3BDLR0_DQ0WBD_Pos (0) /*!< DDRPHY_T::DX3BDLR0: DQ0WBD Position */ +#define DDRPHY_DX3BDLR0_DQ0WBD_Msk (0x3ful << DDRPHY_DX3BDLR0_DQ0WBD_Pos) /*!< DDRPHY_T::DX3BDLR0: DQ0WBD Mask */ + +#define DDRPHY_DX3BDLR0_DQ1WBD_Pos (6) /*!< DDRPHY_T::DX3BDLR0: DQ1WBD Position */ +#define DDRPHY_DX3BDLR0_DQ1WBD_Msk (0x3ful << DDRPHY_DX3BDLR0_DQ1WBD_Pos) /*!< DDRPHY_T::DX3BDLR0: DQ1WBD Mask */ + +#define DDRPHY_DX3BDLR0_DQ2WBD_Pos (12) /*!< DDRPHY_T::DX3BDLR0: DQ2WBD Position */ +#define DDRPHY_DX3BDLR0_DQ2WBD_Msk (0x3ful << DDRPHY_DX3BDLR0_DQ2WBD_Pos) /*!< DDRPHY_T::DX3BDLR0: DQ2WBD Mask */ + +#define DDRPHY_DX3BDLR0_DQ3WBD_Pos (18) /*!< DDRPHY_T::DX3BDLR0: DQ3WBD Position */ +#define DDRPHY_DX3BDLR0_DQ3WBD_Msk (0x3ful << DDRPHY_DX3BDLR0_DQ3WBD_Pos) /*!< DDRPHY_T::DX3BDLR0: DQ3WBD Mask */ + +#define DDRPHY_DX3BDLR0_DQ4WBD_Pos (24) /*!< DDRPHY_T::DX3BDLR0: DQ4WBD Position */ +#define DDRPHY_DX3BDLR0_DQ4WBD_Msk (0x3ful << DDRPHY_DX3BDLR0_DQ4WBD_Pos) /*!< DDRPHY_T::DX3BDLR0: DQ4WBD Mask */ + +#define DDRPHY_DX3BDLR1_DQ5WBD_Pos (0) /*!< DDRPHY_T::DX3BDLR1: DQ5WBD Position */ +#define DDRPHY_DX3BDLR1_DQ5WBD_Msk (0x3ful << DDRPHY_DX3BDLR1_DQ5WBD_Pos) /*!< DDRPHY_T::DX3BDLR1: DQ5WBD Mask */ + +#define DDRPHY_DX3BDLR1_DQ6WBD_Pos (6) /*!< DDRPHY_T::DX3BDLR1: DQ6WBD Position */ +#define DDRPHY_DX3BDLR1_DQ6WBD_Msk (0x3ful << DDRPHY_DX3BDLR1_DQ6WBD_Pos) /*!< DDRPHY_T::DX3BDLR1: DQ6WBD Mask */ + +#define DDRPHY_DX3BDLR1_DQ7WBD_Pos (12) /*!< DDRPHY_T::DX3BDLR1: DQ7WBD Position */ +#define DDRPHY_DX3BDLR1_DQ7WBD_Msk (0x3ful << DDRPHY_DX3BDLR1_DQ7WBD_Pos) /*!< DDRPHY_T::DX3BDLR1: DQ7WBD Mask */ + +#define DDRPHY_DX3BDLR1_DMWBD_Pos (18) /*!< DDRPHY_T::DX3BDLR1: DMWBD Position */ +#define DDRPHY_DX3BDLR1_DMWBD_Msk (0x3ful << DDRPHY_DX3BDLR1_DMWBD_Pos) /*!< DDRPHY_T::DX3BDLR1: DMWBD Mask */ + +#define DDRPHY_DX3BDLR1_DSWBD_Pos (24) /*!< DDRPHY_T::DX3BDLR1: DSWBD Position */ +#define DDRPHY_DX3BDLR1_DSWBD_Msk (0x3ful << DDRPHY_DX3BDLR1_DSWBD_Pos) /*!< DDRPHY_T::DX3BDLR1: DSWBD Mask */ + +#define DDRPHY_DX3BDLR2_DSOEBD_Pos (0) /*!< DDRPHY_T::DX3BDLR2: DSOEBD Position */ +#define DDRPHY_DX3BDLR2_DSOEBD_Msk (0x3ful << DDRPHY_DX3BDLR2_DSOEBD_Pos) /*!< DDRPHY_T::DX3BDLR2: DSOEBD Mask */ + +#define DDRPHY_DX3BDLR2_DQOEBD_Pos (6) /*!< DDRPHY_T::DX3BDLR2: DQOEBD Position */ +#define DDRPHY_DX3BDLR2_DQOEBD_Msk (0x3ful << DDRPHY_DX3BDLR2_DQOEBD_Pos) /*!< DDRPHY_T::DX3BDLR2: DQOEBD Mask */ + +#define DDRPHY_DX3BDLR2_DSRBD_Pos (12) /*!< DDRPHY_T::DX3BDLR2: DSRBD Position */ +#define DDRPHY_DX3BDLR2_DSRBD_Msk (0x3ful << DDRPHY_DX3BDLR2_DSRBD_Pos) /*!< DDRPHY_T::DX3BDLR2: DSRBD Mask */ + +#define DDRPHY_DX3BDLR2_DSNRBD_Pos (18) /*!< DDRPHY_T::DX3BDLR2: DSNRBD Position */ +#define DDRPHY_DX3BDLR2_DSNRBD_Msk (0x3ful << DDRPHY_DX3BDLR2_DSNRBD_Pos) /*!< DDRPHY_T::DX3BDLR2: DSNRBD Mask */ + +#define DDRPHY_DX3BDLR3_DQ0RBD_Pos (0) /*!< DDRPHY_T::DX3BDLR3: DQ0RBD Position */ +#define DDRPHY_DX3BDLR3_DQ0RBD_Msk (0x3ful << DDRPHY_DX3BDLR3_DQ0RBD_Pos) /*!< DDRPHY_T::DX3BDLR3: DQ0RBD Mask */ + +#define DDRPHY_DX3BDLR3_DQ1RBD_Pos (6) /*!< DDRPHY_T::DX3BDLR3: DQ1RBD Position */ +#define DDRPHY_DX3BDLR3_DQ1RBD_Msk (0x3ful << DDRPHY_DX3BDLR3_DQ1RBD_Pos) /*!< DDRPHY_T::DX3BDLR3: DQ1RBD Mask */ + +#define DDRPHY_DX3BDLR3_DQ2RBD_Pos (12) /*!< DDRPHY_T::DX3BDLR3: DQ2RBD Position */ +#define DDRPHY_DX3BDLR3_DQ2RBD_Msk (0x3ful << DDRPHY_DX3BDLR3_DQ2RBD_Pos) /*!< DDRPHY_T::DX3BDLR3: DQ2RBD Mask */ + +#define DDRPHY_DX3BDLR3_DQ3RBD_Pos (18) /*!< DDRPHY_T::DX3BDLR3: DQ3RBD Position */ +#define DDRPHY_DX3BDLR3_DQ3RBD_Msk (0x3ful << DDRPHY_DX3BDLR3_DQ3RBD_Pos) /*!< DDRPHY_T::DX3BDLR3: DQ3RBD Mask */ + +#define DDRPHY_DX3BDLR3_DQ4RBD_Pos (24) /*!< DDRPHY_T::DX3BDLR3: DQ4RBD Position */ +#define DDRPHY_DX3BDLR3_DQ4RBD_Msk (0x3ful << DDRPHY_DX3BDLR3_DQ4RBD_Pos) /*!< DDRPHY_T::DX3BDLR3: DQ4RBD Mask */ + +#define DDRPHY_DX3BDLR4_DQ5RBD_Pos (0) /*!< DDRPHY_T::DX3BDLR4: DQ5RBD Position */ +#define DDRPHY_DX3BDLR4_DQ5RBD_Msk (0x3ful << DDRPHY_DX3BDLR4_DQ5RBD_Pos) /*!< DDRPHY_T::DX3BDLR4: DQ5RBD Mask */ + +#define DDRPHY_DX3BDLR4_DQ6RBD_Pos (6) /*!< DDRPHY_T::DX3BDLR4: DQ6RBD Position */ +#define DDRPHY_DX3BDLR4_DQ6RBD_Msk (0x3ful << DDRPHY_DX3BDLR4_DQ6RBD_Pos) /*!< DDRPHY_T::DX3BDLR4: DQ6RBD Mask */ + +#define DDRPHY_DX3BDLR4_DQ7RBD_Pos (12) /*!< DDRPHY_T::DX3BDLR4: DQ7RBD Position */ +#define DDRPHY_DX3BDLR4_DQ7RBD_Msk (0x3ful << DDRPHY_DX3BDLR4_DQ7RBD_Pos) /*!< DDRPHY_T::DX3BDLR4: DQ7RBD Mask */ + +#define DDRPHY_DX3BDLR4_DMRBD_Pos (18) /*!< DDRPHY_T::DX3BDLR4: DMRBD Position */ +#define DDRPHY_DX3BDLR4_DMRBD_Msk (0x3ful << DDRPHY_DX3BDLR4_DMRBD_Pos) /*!< DDRPHY_T::DX3BDLR4: DMRBD Mask */ + +#define DDRPHY_DX3LCDLR0_R0WLD_Pos (0) /*!< DDRPHY_T::DX3LCDLR0: R0WLD Position */ +#define DDRPHY_DX3LCDLR0_R0WLD_Msk (0xfful << DDRPHY_DX3LCDLR0_R0WLD_Pos) /*!< DDRPHY_T::DX3LCDLR0: R0WLD Mask */ + +#define DDRPHY_DX3LCDLR0_R1WLD_Pos (8) /*!< DDRPHY_T::DX3LCDLR0: R1WLD Position */ +#define DDRPHY_DX3LCDLR0_R1WLD_Msk (0xfful << DDRPHY_DX3LCDLR0_R1WLD_Pos) /*!< DDRPHY_T::DX3LCDLR0: R1WLD Mask */ + +#define DDRPHY_DX3LCDLR0_R2WLD_Pos (16) /*!< DDRPHY_T::DX3LCDLR0: R2WLD Position */ +#define DDRPHY_DX3LCDLR0_R2WLD_Msk (0xfful << DDRPHY_DX3LCDLR0_R2WLD_Pos) /*!< DDRPHY_T::DX3LCDLR0: R2WLD Mask */ + +#define DDRPHY_DX3LCDLR0_R3WLD_Pos (24) /*!< DDRPHY_T::DX3LCDLR0: R3WLD Position */ +#define DDRPHY_DX3LCDLR0_R3WLD_Msk (0xfful << DDRPHY_DX3LCDLR0_R3WLD_Pos) /*!< DDRPHY_T::DX3LCDLR0: R3WLD Mask */ + +#define DDRPHY_DX3LCDLR1_WDQD_Pos (0) /*!< DDRPHY_T::DX3LCDLR1: WDQD Position */ +#define DDRPHY_DX3LCDLR1_WDQD_Msk (0xfful << DDRPHY_DX3LCDLR1_WDQD_Pos) /*!< DDRPHY_T::DX3LCDLR1: WDQD Mask */ + +#define DDRPHY_DX3LCDLR1_RDQSD_Pos (8) /*!< DDRPHY_T::DX3LCDLR1: RDQSD Position */ +#define DDRPHY_DX3LCDLR1_RDQSD_Msk (0xfful << DDRPHY_DX3LCDLR1_RDQSD_Pos) /*!< DDRPHY_T::DX3LCDLR1: RDQSD Mask */ + +#define DDRPHY_DX3LCDLR1_RDQSND_Pos (16) /*!< DDRPHY_T::DX3LCDLR1: RDQSND Position */ +#define DDRPHY_DX3LCDLR1_RDQSND_Msk (0xfful << DDRPHY_DX3LCDLR1_RDQSND_Pos) /*!< DDRPHY_T::DX3LCDLR1: RDQSND Mask */ + +#define DDRPHY_DX3LCDLR2_R0DQSGD_Pos (0) /*!< DDRPHY_T::DX3LCDLR2: R0DQSGD Position */ +#define DDRPHY_DX3LCDLR2_R0DQSGD_Msk (0xfful << DDRPHY_DX3LCDLR2_R0DQSGD_Pos) /*!< DDRPHY_T::DX3LCDLR2: R0DQSGD Mask */ + +#define DDRPHY_DX3LCDLR2_R1DQSGD_Pos (8) /*!< DDRPHY_T::DX3LCDLR2: R1DQSGD Position */ +#define DDRPHY_DX3LCDLR2_R1DQSGD_Msk (0xfful << DDRPHY_DX3LCDLR2_R1DQSGD_Pos) /*!< DDRPHY_T::DX3LCDLR2: R1DQSGD Mask */ + +#define DDRPHY_DX3LCDLR2_R2DQSGD_Pos (16) /*!< DDRPHY_T::DX3LCDLR2: R2DQSGD Position */ +#define DDRPHY_DX3LCDLR2_R2DQSGD_Msk (0xfful << DDRPHY_DX3LCDLR2_R2DQSGD_Pos) /*!< DDRPHY_T::DX3LCDLR2: R2DQSGD Mask */ + +#define DDRPHY_DX3LCDLR2_R3DQSGD_Pos (24) /*!< DDRPHY_T::DX3LCDLR2: R3DQSGD Position */ +#define DDRPHY_DX3LCDLR2_R3DQSGD_Msk (0xfful << DDRPHY_DX3LCDLR2_R3DQSGD_Pos) /*!< DDRPHY_T::DX3LCDLR2: R3DQSGD Mask */ + +#define DDRPHY_DX3MDLR_IPRD_Pos (0) /*!< DDRPHY_T::DX3MDLR: IPRD Position */ +#define DDRPHY_DX3MDLR_IPRD_Msk (0xfful << DDRPHY_DX3MDLR_IPRD_Pos) /*!< DDRPHY_T::DX3MDLR: IPRD Mask */ + +#define DDRPHY_DX3MDLR_TPRD_Pos (8) /*!< DDRPHY_T::DX3MDLR: TPRD Position */ +#define DDRPHY_DX3MDLR_TPRD_Msk (0xfful << DDRPHY_DX3MDLR_TPRD_Pos) /*!< DDRPHY_T::DX3MDLR: TPRD Mask */ + +#define DDRPHY_DX3MDLR_MDLD_Pos (16) /*!< DDRPHY_T::DX3MDLR: MDLD Position */ +#define DDRPHY_DX3MDLR_MDLD_Msk (0xfful << DDRPHY_DX3MDLR_MDLD_Pos) /*!< DDRPHY_T::DX3MDLR: MDLD Mask */ + +#define DDRPHY_DX3GTR_R0DGSL_Pos (0) /*!< DDRPHY_T::DX3GTR: R0DGSL Position */ +#define DDRPHY_DX3GTR_R0DGSL_Msk (0x7ul << DDRPHY_DX3GTR_R0DGSL_Pos) /*!< DDRPHY_T::DX3GTR: R0DGSL Mask */ + +#define DDRPHY_DX3GTR_R1DGSL_Pos (3) /*!< DDRPHY_T::DX3GTR: R1DGSL Position */ +#define DDRPHY_DX3GTR_R1DGSL_Msk (0x7ul << DDRPHY_DX3GTR_R1DGSL_Pos) /*!< DDRPHY_T::DX3GTR: R1DGSL Mask */ + +#define DDRPHY_DX3GTR_R2DGSL_Pos (6) /*!< DDRPHY_T::DX3GTR: R2DGSL Position */ +#define DDRPHY_DX3GTR_R2DGSL_Msk (0x7ul << DDRPHY_DX3GTR_R2DGSL_Pos) /*!< DDRPHY_T::DX3GTR: R2DGSL Mask */ + +#define DDRPHY_DX3GTR_R3DGSL_Pos (9) /*!< DDRPHY_T::DX3GTR: R3DGSL Position */ +#define DDRPHY_DX3GTR_R3DGSL_Msk (0x7ul << DDRPHY_DX3GTR_R3DGSL_Pos) /*!< DDRPHY_T::DX3GTR: R3DGSL Mask */ + +#define DDRPHY_DX3GTR_R0WLSL_Pos (12) /*!< DDRPHY_T::DX3GTR: R0WLSL Position */ +#define DDRPHY_DX3GTR_R0WLSL_Msk (0x3ul << DDRPHY_DX3GTR_R0WLSL_Pos) /*!< DDRPHY_T::DX3GTR: R0WLSL Mask */ + +#define DDRPHY_DX3GTR_R1WLSL_Pos (14) /*!< DDRPHY_T::DX3GTR: R1WLSL Position */ +#define DDRPHY_DX3GTR_R1WLSL_Msk (0x3ul << DDRPHY_DX3GTR_R1WLSL_Pos) /*!< DDRPHY_T::DX3GTR: R1WLSL Mask */ + +#define DDRPHY_DX3GTR_R2WLSL_Pos (16) /*!< DDRPHY_T::DX3GTR: R2WLSL Position */ +#define DDRPHY_DX3GTR_R2WLSL_Msk (0x3ul << DDRPHY_DX3GTR_R2WLSL_Pos) /*!< DDRPHY_T::DX3GTR: R2WLSL Mask */ + +#define DDRPHY_DX3GTR_R3WLSL_Pos (18) /*!< DDRPHY_T::DX3GTR: R3WLSL Position */ +#define DDRPHY_DX3GTR_R3WLSL_Msk (0x3ul << DDRPHY_DX3GTR_R3WLSL_Pos) /*!< DDRPHY_T::DX3GTR: R3WLSL Mask */ + +#define DDRPHY_DX3GSR2_RDERR_Pos (0) /*!< DDRPHY_T::DX3GSR2: RDERR Position */ +#define DDRPHY_DX3GSR2_RDERR_Msk (0x1ul << DDRPHY_DX3GSR2_RDERR_Pos) /*!< DDRPHY_T::DX3GSR2: RDERR Mask */ + +#define DDRPHY_DX3GSR2_RDWN_Pos (1) /*!< DDRPHY_T::DX3GSR2: RDWN Position */ +#define DDRPHY_DX3GSR2_RDWN_Msk (0x1ul << DDRPHY_DX3GSR2_RDWN_Pos) /*!< DDRPHY_T::DX3GSR2: RDWN Mask */ + +#define DDRPHY_DX3GSR2_WDERR_Pos (2) /*!< DDRPHY_T::DX3GSR2: WDERR Position */ +#define DDRPHY_DX3GSR2_WDERR_Msk (0x1ul << DDRPHY_DX3GSR2_WDERR_Pos) /*!< DDRPHY_T::DX3GSR2: WDERR Mask */ + +#define DDRPHY_DX3GSR2_WDWN_Pos (3) /*!< DDRPHY_T::DX3GSR2: WDWN Position */ +#define DDRPHY_DX3GSR2_WDWN_Msk (0x1ul << DDRPHY_DX3GSR2_WDWN_Pos) /*!< DDRPHY_T::DX3GSR2: WDWN Mask */ + +#define DDRPHY_DX3GSR2_REERR_Pos (4) /*!< DDRPHY_T::DX3GSR2: REERR Position */ +#define DDRPHY_DX3GSR2_REERR_Msk (0x1ul << DDRPHY_DX3GSR2_REERR_Pos) /*!< DDRPHY_T::DX3GSR2: REERR Mask */ + +#define DDRPHY_DX3GSR2_REWN_Pos (5) /*!< DDRPHY_T::DX3GSR2: REWN Position */ +#define DDRPHY_DX3GSR2_REWN_Msk (0x1ul << DDRPHY_DX3GSR2_REWN_Pos) /*!< DDRPHY_T::DX3GSR2: REWN Mask */ + +#define DDRPHY_DX3GSR2_WEERR_Pos (6) /*!< DDRPHY_T::DX3GSR2: WEERR Position */ +#define DDRPHY_DX3GSR2_WEERR_Msk (0x1ul << DDRPHY_DX3GSR2_WEERR_Pos) /*!< DDRPHY_T::DX3GSR2: WEERR Mask */ + +#define DDRPHY_DX3GSR2_WEWN_Pos (7) /*!< DDRPHY_T::DX3GSR2: WEWN Position */ +#define DDRPHY_DX3GSR2_WEWN_Msk (0x1ul << DDRPHY_DX3GSR2_WEWN_Pos) /*!< DDRPHY_T::DX3GSR2: WEWN Mask */ + +#define DDRPHY_DX3GSR2_ESTAT_Pos (8) /*!< DDRPHY_T::DX3GSR2: ESTAT Position */ +#define DDRPHY_DX3GSR2_ESTAT_Msk (0xful << DDRPHY_DX3GSR2_ESTAT_Pos) /*!< DDRPHY_T::DX3GSR2: ESTAT Mask */ + +#define DDRPHY_DX4GCR_DXEN_Pos (0) /*!< DDRPHY_T::DX4GCR: DXEN Position */ +#define DDRPHY_DX4GCR_DXEN_Msk (0x1ul << DDRPHY_DX4GCR_DXEN_Pos) /*!< DDRPHY_T::DX4GCR: DXEN Mask */ + +#define DDRPHY_DX4GCR_DQSODT_Pos (1) /*!< DDRPHY_T::DX4GCR: DQSODT Position */ +#define DDRPHY_DX4GCR_DQSODT_Msk (0x1ul << DDRPHY_DX4GCR_DQSODT_Pos) /*!< DDRPHY_T::DX4GCR: DQSODT Mask */ + +#define DDRPHY_DX4GCR_DQODT_Pos (2) /*!< DDRPHY_T::DX4GCR: DQODT Position */ +#define DDRPHY_DX4GCR_DQODT_Msk (0x1ul << DDRPHY_DX4GCR_DQODT_Pos) /*!< DDRPHY_T::DX4GCR: DQODT Mask */ + +#define DDRPHY_DX4GCR_DXIOM_Pos (3) /*!< DDRPHY_T::DX4GCR: DXIOM Position */ +#define DDRPHY_DX4GCR_DXIOM_Msk (0x1ul << DDRPHY_DX4GCR_DXIOM_Pos) /*!< DDRPHY_T::DX4GCR: DXIOM Mask */ + +#define DDRPHY_DX4GCR_DXPDD_Pos (4) /*!< DDRPHY_T::DX4GCR: DXPDD Position */ +#define DDRPHY_DX4GCR_DXPDD_Msk (0x1ul << DDRPHY_DX4GCR_DXPDD_Pos) /*!< DDRPHY_T::DX4GCR: DXPDD Mask */ + +#define DDRPHY_DX4GCR_DXPDR_Pos (5) /*!< DDRPHY_T::DX4GCR: DXPDR Position */ +#define DDRPHY_DX4GCR_DXPDR_Msk (0x1ul << DDRPHY_DX4GCR_DXPDR_Pos) /*!< DDRPHY_T::DX4GCR: DXPDR Mask */ + +#define DDRPHY_DX4GCR_DQSRPD_Pos (6) /*!< DDRPHY_T::DX4GCR: DQSRPD Position */ +#define DDRPHY_DX4GCR_DQSRPD_Msk (0x1ul << DDRPHY_DX4GCR_DQSRPD_Pos) /*!< DDRPHY_T::DX4GCR: DQSRPD Mask */ + +#define DDRPHY_DX4GCR_DSEN_Pos (7) /*!< DDRPHY_T::DX4GCR: DSEN Position */ +#define DDRPHY_DX4GCR_DSEN_Msk (0x3ul << DDRPHY_DX4GCR_DSEN_Pos) /*!< DDRPHY_T::DX4GCR: DSEN Mask */ + +#define DDRPHY_DX4GCR_DQSRTT_Pos (9) /*!< DDRPHY_T::DX4GCR: DQSRTT Position */ +#define DDRPHY_DX4GCR_DQSRTT_Msk (0x1ul << DDRPHY_DX4GCR_DQSRTT_Pos) /*!< DDRPHY_T::DX4GCR: DQSRTT Mask */ + +#define DDRPHY_DX4GCR_DQRTT_Pos (10) /*!< DDRPHY_T::DX4GCR: DQRTT Position */ +#define DDRPHY_DX4GCR_DQRTT_Msk (0x1ul << DDRPHY_DX4GCR_DQRTT_Pos) /*!< DDRPHY_T::DX4GCR: DQRTT Mask */ + +#define DDRPHY_DX4GCR_RTTOH_Pos (11) /*!< DDRPHY_T::DX4GCR: RTTOH Position */ +#define DDRPHY_DX4GCR_RTTOH_Msk (0x3ul << DDRPHY_DX4GCR_RTTOH_Pos) /*!< DDRPHY_T::DX4GCR: RTTOH Mask */ + +#define DDRPHY_DX4GCR_RTTOAL_Pos (13) /*!< DDRPHY_T::DX4GCR: RTTOAL Position */ +#define DDRPHY_DX4GCR_RTTOAL_Msk (0x1ul << DDRPHY_DX4GCR_RTTOAL_Pos) /*!< DDRPHY_T::DX4GCR: RTTOAL Mask */ + +#define DDRPHY_DX4GCR_DXOEO_Pos (14) /*!< DDRPHY_T::DX4GCR: DXOEO Position */ +#define DDRPHY_DX4GCR_DXOEO_Msk (0x3ul << DDRPHY_DX4GCR_DXOEO_Pos) /*!< DDRPHY_T::DX4GCR: DXOEO Mask */ + +#define DDRPHY_DX4GCR_PLLRST_Pos (16) /*!< DDRPHY_T::DX4GCR: PLLRST Position */ +#define DDRPHY_DX4GCR_PLLRST_Msk (0x1ul << DDRPHY_DX4GCR_PLLRST_Pos) /*!< DDRPHY_T::DX4GCR: PLLRST Mask */ + +#define DDRPHY_DX4GCR_PLLPD_Pos (17) /*!< DDRPHY_T::DX4GCR: PLLPD Position */ +#define DDRPHY_DX4GCR_PLLPD_Msk (0x1ul << DDRPHY_DX4GCR_PLLPD_Pos) /*!< DDRPHY_T::DX4GCR: PLLPD Mask */ + +#define DDRPHY_DX4GCR_GSHIFT_Pos (18) /*!< DDRPHY_T::DX4GCR: GSHIFT Position */ +#define DDRPHY_DX4GCR_GSHIFT_Msk (0x1ul << DDRPHY_DX4GCR_GSHIFT_Pos) /*!< DDRPHY_T::DX4GCR: GSHIFT Mask */ + +#define DDRPHY_DX4GCR_PLLBYP_Pos (19) /*!< DDRPHY_T::DX4GCR: PLLBYP Position */ +#define DDRPHY_DX4GCR_PLLBYP_Msk (0x1ul << DDRPHY_DX4GCR_PLLBYP_Pos) /*!< DDRPHY_T::DX4GCR: PLLBYP Mask */ + +#define DDRPHY_DX4GCR_WLRKEN_Pos (26) /*!< DDRPHY_T::DX4GCR: WLRKEN Position */ +#define DDRPHY_DX4GCR_WLRKEN_Msk (0xful << DDRPHY_DX4GCR_WLRKEN_Pos) /*!< DDRPHY_T::DX4GCR: WLRKEN Mask */ + +#define DDRPHY_DX4GCR_MDLEN_Pos (30) /*!< DDRPHY_T::DX4GCR: MDLEN Position */ +#define DDRPHY_DX4GCR_MDLEN_Msk (0x1ul << DDRPHY_DX4GCR_MDLEN_Pos) /*!< DDRPHY_T::DX4GCR: MDLEN Mask */ + +#define DDRPHY_DX4GCR_CALBYP_Pos (31) /*!< DDRPHY_T::DX4GCR: CALBYP Position */ +#define DDRPHY_DX4GCR_CALBYP_Msk (0x1ul << DDRPHY_DX4GCR_CALBYP_Pos) /*!< DDRPHY_T::DX4GCR: CALBYP Mask */ + +#define DDRPHY_DX4GSR0_WDQCAL_Pos (0) /*!< DDRPHY_T::DX4GSR0: WDQCAL Position */ +#define DDRPHY_DX4GSR0_WDQCAL_Msk (0x1ul << DDRPHY_DX4GSR0_WDQCAL_Pos) /*!< DDRPHY_T::DX4GSR0: WDQCAL Mask */ + +#define DDRPHY_DX4GSR0_RDQSCAL_Pos (1) /*!< DDRPHY_T::DX4GSR0: RDQSCAL Position */ +#define DDRPHY_DX4GSR0_RDQSCAL_Msk (0x1ul << DDRPHY_DX4GSR0_RDQSCAL_Pos) /*!< DDRPHY_T::DX4GSR0: RDQSCAL Mask */ + +#define DDRPHY_DX4GSR0_RDQSNCAL_Pos (2) /*!< DDRPHY_T::DX4GSR0: RDQSNCAL Position */ +#define DDRPHY_DX4GSR0_RDQSNCAL_Msk (0x1ul << DDRPHY_DX4GSR0_RDQSNCAL_Pos) /*!< DDRPHY_T::DX4GSR0: RDQSNCAL Mask */ + +#define DDRPHY_DX4GSR0_GDQSCAL_Pos (3) /*!< DDRPHY_T::DX4GSR0: GDQSCAL Position */ +#define DDRPHY_DX4GSR0_GDQSCAL_Msk (0x1ul << DDRPHY_DX4GSR0_GDQSCAL_Pos) /*!< DDRPHY_T::DX4GSR0: GDQSCAL Mask */ + +#define DDRPHY_DX4GSR0_WLCAL_Pos (4) /*!< DDRPHY_T::DX4GSR0: WLCAL Position */ +#define DDRPHY_DX4GSR0_WLCAL_Msk (0x1ul << DDRPHY_DX4GSR0_WLCAL_Pos) /*!< DDRPHY_T::DX4GSR0: WLCAL Mask */ + +#define DDRPHY_DX4GSR0_WLDONE_Pos (5) /*!< DDRPHY_T::DX4GSR0: WLDONE Position */ +#define DDRPHY_DX4GSR0_WLDONE_Msk (0x1ul << DDRPHY_DX4GSR0_WLDONE_Pos) /*!< DDRPHY_T::DX4GSR0: WLDONE Mask */ + +#define DDRPHY_DX4GSR0_WLERR_Pos (6) /*!< DDRPHY_T::DX4GSR0: WLERR Position */ +#define DDRPHY_DX4GSR0_WLERR_Msk (0x1ul << DDRPHY_DX4GSR0_WLERR_Pos) /*!< DDRPHY_T::DX4GSR0: WLERR Mask */ + +#define DDRPHY_DX4GSR0_WLPRD_Pos (7) /*!< DDRPHY_T::DX4GSR0: WLPRD Position */ +#define DDRPHY_DX4GSR0_WLPRD_Msk (0xfful << DDRPHY_DX4GSR0_WLPRD_Pos) /*!< DDRPHY_T::DX4GSR0: WLPRD Mask */ + +#define DDRPHY_DX4GSR0_DPLOCK_Pos (15) /*!< DDRPHY_T::DX4GSR0: DPLOCK Position */ +#define DDRPHY_DX4GSR0_DPLOCK_Msk (0x1ul << DDRPHY_DX4GSR0_DPLOCK_Pos) /*!< DDRPHY_T::DX4GSR0: DPLOCK Mask */ + +#define DDRPHY_DX4GSR0_GDQSPRD_Pos (16) /*!< DDRPHY_T::DX4GSR0: GDQSPRD Position */ +#define DDRPHY_DX4GSR0_GDQSPRD_Msk (0xfful << DDRPHY_DX4GSR0_GDQSPRD_Pos) /*!< DDRPHY_T::DX4GSR0: GDQSPRD Mask */ + +#define DDRPHY_DX4GSR0_QSGERR_Pos (24) /*!< DDRPHY_T::DX4GSR0: QSGERR Position */ +#define DDRPHY_DX4GSR0_QSGERR_Msk (0xful << DDRPHY_DX4GSR0_QSGERR_Pos) /*!< DDRPHY_T::DX4GSR0: QSGERR Mask */ + +#define DDRPHY_DX4GSR0_WLDQ_Pos (28) /*!< DDRPHY_T::DX4GSR0: WLDQ Position */ +#define DDRPHY_DX4GSR0_WLDQ_Msk (0x1ul << DDRPHY_DX4GSR0_WLDQ_Pos) /*!< DDRPHY_T::DX4GSR0: WLDQ Mask */ + +#define DDRPHY_DX4GSR1_DLTDONE_Pos (0) /*!< DDRPHY_T::DX4GSR1: DLTDONE Position */ +#define DDRPHY_DX4GSR1_DLTDONE_Msk (0x1ul << DDRPHY_DX4GSR1_DLTDONE_Pos) /*!< DDRPHY_T::DX4GSR1: DLTDONE Mask */ + +#define DDRPHY_DX4GSR1_DLTCODE_Pos (1) /*!< DDRPHY_T::DX4GSR1: DLTCODE Position */ +#define DDRPHY_DX4GSR1_DLTCODE_Msk (0xfffffful << DDRPHY_DX4GSR1_DLTCODE_Pos) /*!< DDRPHY_T::DX4GSR1: DLTCODE Mask */ + +#define DDRPHY_DX4BDLR0_DQ0WBD_Pos (0) /*!< DDRPHY_T::DX4BDLR0: DQ0WBD Position */ +#define DDRPHY_DX4BDLR0_DQ0WBD_Msk (0x3ful << DDRPHY_DX4BDLR0_DQ0WBD_Pos) /*!< DDRPHY_T::DX4BDLR0: DQ0WBD Mask */ + +#define DDRPHY_DX4BDLR0_DQ1WBD_Pos (6) /*!< DDRPHY_T::DX4BDLR0: DQ1WBD Position */ +#define DDRPHY_DX4BDLR0_DQ1WBD_Msk (0x3ful << DDRPHY_DX4BDLR0_DQ1WBD_Pos) /*!< DDRPHY_T::DX4BDLR0: DQ1WBD Mask */ + +#define DDRPHY_DX4BDLR0_DQ2WBD_Pos (12) /*!< DDRPHY_T::DX4BDLR0: DQ2WBD Position */ +#define DDRPHY_DX4BDLR0_DQ2WBD_Msk (0x3ful << DDRPHY_DX4BDLR0_DQ2WBD_Pos) /*!< DDRPHY_T::DX4BDLR0: DQ2WBD Mask */ + +#define DDRPHY_DX4BDLR0_DQ3WBD_Pos (18) /*!< DDRPHY_T::DX4BDLR0: DQ3WBD Position */ +#define DDRPHY_DX4BDLR0_DQ3WBD_Msk (0x3ful << DDRPHY_DX4BDLR0_DQ3WBD_Pos) /*!< DDRPHY_T::DX4BDLR0: DQ3WBD Mask */ + +#define DDRPHY_DX4BDLR0_DQ4WBD_Pos (24) /*!< DDRPHY_T::DX4BDLR0: DQ4WBD Position */ +#define DDRPHY_DX4BDLR0_DQ4WBD_Msk (0x3ful << DDRPHY_DX4BDLR0_DQ4WBD_Pos) /*!< DDRPHY_T::DX4BDLR0: DQ4WBD Mask */ + +#define DDRPHY_DX4BDLR1_DQ5WBD_Pos (0) /*!< DDRPHY_T::DX4BDLR1: DQ5WBD Position */ +#define DDRPHY_DX4BDLR1_DQ5WBD_Msk (0x3ful << DDRPHY_DX4BDLR1_DQ5WBD_Pos) /*!< DDRPHY_T::DX4BDLR1: DQ5WBD Mask */ + +#define DDRPHY_DX4BDLR1_DQ6WBD_Pos (6) /*!< DDRPHY_T::DX4BDLR1: DQ6WBD Position */ +#define DDRPHY_DX4BDLR1_DQ6WBD_Msk (0x3ful << DDRPHY_DX4BDLR1_DQ6WBD_Pos) /*!< DDRPHY_T::DX4BDLR1: DQ6WBD Mask */ + +#define DDRPHY_DX4BDLR1_DQ7WBD_Pos (12) /*!< DDRPHY_T::DX4BDLR1: DQ7WBD Position */ +#define DDRPHY_DX4BDLR1_DQ7WBD_Msk (0x3ful << DDRPHY_DX4BDLR1_DQ7WBD_Pos) /*!< DDRPHY_T::DX4BDLR1: DQ7WBD Mask */ + +#define DDRPHY_DX4BDLR1_DMWBD_Pos (18) /*!< DDRPHY_T::DX4BDLR1: DMWBD Position */ +#define DDRPHY_DX4BDLR1_DMWBD_Msk (0x3ful << DDRPHY_DX4BDLR1_DMWBD_Pos) /*!< DDRPHY_T::DX4BDLR1: DMWBD Mask */ + +#define DDRPHY_DX4BDLR1_DSWBD_Pos (24) /*!< DDRPHY_T::DX4BDLR1: DSWBD Position */ +#define DDRPHY_DX4BDLR1_DSWBD_Msk (0x3ful << DDRPHY_DX4BDLR1_DSWBD_Pos) /*!< DDRPHY_T::DX4BDLR1: DSWBD Mask */ + +#define DDRPHY_DX4BDLR2_DSOEBD_Pos (0) /*!< DDRPHY_T::DX4BDLR2: DSOEBD Position */ +#define DDRPHY_DX4BDLR2_DSOEBD_Msk (0x3ful << DDRPHY_DX4BDLR2_DSOEBD_Pos) /*!< DDRPHY_T::DX4BDLR2: DSOEBD Mask */ + +#define DDRPHY_DX4BDLR2_DQOEBD_Pos (6) /*!< DDRPHY_T::DX4BDLR2: DQOEBD Position */ +#define DDRPHY_DX4BDLR2_DQOEBD_Msk (0x3ful << DDRPHY_DX4BDLR2_DQOEBD_Pos) /*!< DDRPHY_T::DX4BDLR2: DQOEBD Mask */ + +#define DDRPHY_DX4BDLR2_DSRBD_Pos (12) /*!< DDRPHY_T::DX4BDLR2: DSRBD Position */ +#define DDRPHY_DX4BDLR2_DSRBD_Msk (0x3ful << DDRPHY_DX4BDLR2_DSRBD_Pos) /*!< DDRPHY_T::DX4BDLR2: DSRBD Mask */ + +#define DDRPHY_DX4BDLR2_DSNRBD_Pos (18) /*!< DDRPHY_T::DX4BDLR2: DSNRBD Position */ +#define DDRPHY_DX4BDLR2_DSNRBD_Msk (0x3ful << DDRPHY_DX4BDLR2_DSNRBD_Pos) /*!< DDRPHY_T::DX4BDLR2: DSNRBD Mask */ + +#define DDRPHY_DX4BDLR3_DQ0RBD_Pos (0) /*!< DDRPHY_T::DX4BDLR3: DQ0RBD Position */ +#define DDRPHY_DX4BDLR3_DQ0RBD_Msk (0x3ful << DDRPHY_DX4BDLR3_DQ0RBD_Pos) /*!< DDRPHY_T::DX4BDLR3: DQ0RBD Mask */ + +#define DDRPHY_DX4BDLR3_DQ1RBD_Pos (6) /*!< DDRPHY_T::DX4BDLR3: DQ1RBD Position */ +#define DDRPHY_DX4BDLR3_DQ1RBD_Msk (0x3ful << DDRPHY_DX4BDLR3_DQ1RBD_Pos) /*!< DDRPHY_T::DX4BDLR3: DQ1RBD Mask */ + +#define DDRPHY_DX4BDLR3_DQ2RBD_Pos (12) /*!< DDRPHY_T::DX4BDLR3: DQ2RBD Position */ +#define DDRPHY_DX4BDLR3_DQ2RBD_Msk (0x3ful << DDRPHY_DX4BDLR3_DQ2RBD_Pos) /*!< DDRPHY_T::DX4BDLR3: DQ2RBD Mask */ + +#define DDRPHY_DX4BDLR3_DQ3RBD_Pos (18) /*!< DDRPHY_T::DX4BDLR3: DQ3RBD Position */ +#define DDRPHY_DX4BDLR3_DQ3RBD_Msk (0x3ful << DDRPHY_DX4BDLR3_DQ3RBD_Pos) /*!< DDRPHY_T::DX4BDLR3: DQ3RBD Mask */ + +#define DDRPHY_DX4BDLR3_DQ4RBD_Pos (24) /*!< DDRPHY_T::DX4BDLR3: DQ4RBD Position */ +#define DDRPHY_DX4BDLR3_DQ4RBD_Msk (0x3ful << DDRPHY_DX4BDLR3_DQ4RBD_Pos) /*!< DDRPHY_T::DX4BDLR3: DQ4RBD Mask */ + +#define DDRPHY_DX4BDLR4_DQ5RBD_Pos (0) /*!< DDRPHY_T::DX4BDLR4: DQ5RBD Position */ +#define DDRPHY_DX4BDLR4_DQ5RBD_Msk (0x3ful << DDRPHY_DX4BDLR4_DQ5RBD_Pos) /*!< DDRPHY_T::DX4BDLR4: DQ5RBD Mask */ + +#define DDRPHY_DX4BDLR4_DQ6RBD_Pos (6) /*!< DDRPHY_T::DX4BDLR4: DQ6RBD Position */ +#define DDRPHY_DX4BDLR4_DQ6RBD_Msk (0x3ful << DDRPHY_DX4BDLR4_DQ6RBD_Pos) /*!< DDRPHY_T::DX4BDLR4: DQ6RBD Mask */ + +#define DDRPHY_DX4BDLR4_DQ7RBD_Pos (12) /*!< DDRPHY_T::DX4BDLR4: DQ7RBD Position */ +#define DDRPHY_DX4BDLR4_DQ7RBD_Msk (0x3ful << DDRPHY_DX4BDLR4_DQ7RBD_Pos) /*!< DDRPHY_T::DX4BDLR4: DQ7RBD Mask */ + +#define DDRPHY_DX4BDLR4_DMRBD_Pos (18) /*!< DDRPHY_T::DX4BDLR4: DMRBD Position */ +#define DDRPHY_DX4BDLR4_DMRBD_Msk (0x3ful << DDRPHY_DX4BDLR4_DMRBD_Pos) /*!< DDRPHY_T::DX4BDLR4: DMRBD Mask */ + +#define DDRPHY_DX4LCDLR0_R0WLD_Pos (0) /*!< DDRPHY_T::DX4LCDLR0: R0WLD Position */ +#define DDRPHY_DX4LCDLR0_R0WLD_Msk (0xfful << DDRPHY_DX4LCDLR0_R0WLD_Pos) /*!< DDRPHY_T::DX4LCDLR0: R0WLD Mask */ + +#define DDRPHY_DX4LCDLR0_R1WLD_Pos (8) /*!< DDRPHY_T::DX4LCDLR0: R1WLD Position */ +#define DDRPHY_DX4LCDLR0_R1WLD_Msk (0xfful << DDRPHY_DX4LCDLR0_R1WLD_Pos) /*!< DDRPHY_T::DX4LCDLR0: R1WLD Mask */ + +#define DDRPHY_DX4LCDLR0_R2WLD_Pos (16) /*!< DDRPHY_T::DX4LCDLR0: R2WLD Position */ +#define DDRPHY_DX4LCDLR0_R2WLD_Msk (0xfful << DDRPHY_DX4LCDLR0_R2WLD_Pos) /*!< DDRPHY_T::DX4LCDLR0: R2WLD Mask */ + +#define DDRPHY_DX4LCDLR0_R3WLD_Pos (24) /*!< DDRPHY_T::DX4LCDLR0: R3WLD Position */ +#define DDRPHY_DX4LCDLR0_R3WLD_Msk (0xfful << DDRPHY_DX4LCDLR0_R3WLD_Pos) /*!< DDRPHY_T::DX4LCDLR0: R3WLD Mask */ + +#define DDRPHY_DX4LCDLR2_R0DQSGD_Pos (0) /*!< DDRPHY_T::DX4LCDLR2: R0DQSGD Position */ +#define DDRPHY_DX4LCDLR2_R0DQSGD_Msk (0xfful << DDRPHY_DX4LCDLR2_R0DQSGD_Pos) /*!< DDRPHY_T::DX4LCDLR2: R0DQSGD Mask */ + +#define DDRPHY_DX4LCDLR2_R1DQSGD_Pos (8) /*!< DDRPHY_T::DX4LCDLR2: R1DQSGD Position */ +#define DDRPHY_DX4LCDLR2_R1DQSGD_Msk (0xfful << DDRPHY_DX4LCDLR2_R1DQSGD_Pos) /*!< DDRPHY_T::DX4LCDLR2: R1DQSGD Mask */ + +#define DDRPHY_DX4LCDLR2_R2DQSGD_Pos (16) /*!< DDRPHY_T::DX4LCDLR2: R2DQSGD Position */ +#define DDRPHY_DX4LCDLR2_R2DQSGD_Msk (0xfful << DDRPHY_DX4LCDLR2_R2DQSGD_Pos) /*!< DDRPHY_T::DX4LCDLR2: R2DQSGD Mask */ + +#define DDRPHY_DX4LCDLR2_R3DQSGD_Pos (24) /*!< DDRPHY_T::DX4LCDLR2: R3DQSGD Position */ +#define DDRPHY_DX4LCDLR2_R3DQSGD_Msk (0xfful << DDRPHY_DX4LCDLR2_R3DQSGD_Pos) /*!< DDRPHY_T::DX4LCDLR2: R3DQSGD Mask */ + +#define DDRPHY_DX4MDLR_IPRD_Pos (0) /*!< DDRPHY_T::DX4MDLR: IPRD Position */ +#define DDRPHY_DX4MDLR_IPRD_Msk (0xfful << DDRPHY_DX4MDLR_IPRD_Pos) /*!< DDRPHY_T::DX4MDLR: IPRD Mask */ + +#define DDRPHY_DX4MDLR_TPRD_Pos (8) /*!< DDRPHY_T::DX4MDLR: TPRD Position */ +#define DDRPHY_DX4MDLR_TPRD_Msk (0xfful << DDRPHY_DX4MDLR_TPRD_Pos) /*!< DDRPHY_T::DX4MDLR: TPRD Mask */ + +#define DDRPHY_DX4MDLR_MDLD_Pos (16) /*!< DDRPHY_T::DX4MDLR: MDLD Position */ +#define DDRPHY_DX4MDLR_MDLD_Msk (0xfful << DDRPHY_DX4MDLR_MDLD_Pos) /*!< DDRPHY_T::DX4MDLR: MDLD Mask */ + +#define DDRPHY_DX4GTR_R0DGSL_Pos (0) /*!< DDRPHY_T::DX4GTR: R0DGSL Position */ +#define DDRPHY_DX4GTR_R0DGSL_Msk (0x7ul << DDRPHY_DX4GTR_R0DGSL_Pos) /*!< DDRPHY_T::DX4GTR: R0DGSL Mask */ + +#define DDRPHY_DX4GTR_R1DGSL_Pos (3) /*!< DDRPHY_T::DX4GTR: R1DGSL Position */ +#define DDRPHY_DX4GTR_R1DGSL_Msk (0x7ul << DDRPHY_DX4GTR_R1DGSL_Pos) /*!< DDRPHY_T::DX4GTR: R1DGSL Mask */ + +#define DDRPHY_DX4GTR_R2DGSL_Pos (6) /*!< DDRPHY_T::DX4GTR: R2DGSL Position */ +#define DDRPHY_DX4GTR_R2DGSL_Msk (0x7ul << DDRPHY_DX4GTR_R2DGSL_Pos) /*!< DDRPHY_T::DX4GTR: R2DGSL Mask */ + +#define DDRPHY_DX4GTR_R3DGSL_Pos (9) /*!< DDRPHY_T::DX4GTR: R3DGSL Position */ +#define DDRPHY_DX4GTR_R3DGSL_Msk (0x7ul << DDRPHY_DX4GTR_R3DGSL_Pos) /*!< DDRPHY_T::DX4GTR: R3DGSL Mask */ + +#define DDRPHY_DX4GTR_R0WLSL_Pos (12) /*!< DDRPHY_T::DX4GTR: R0WLSL Position */ +#define DDRPHY_DX4GTR_R0WLSL_Msk (0x3ul << DDRPHY_DX4GTR_R0WLSL_Pos) /*!< DDRPHY_T::DX4GTR: R0WLSL Mask */ + +#define DDRPHY_DX4GTR_R1WLSL_Pos (14) /*!< DDRPHY_T::DX4GTR: R1WLSL Position */ +#define DDRPHY_DX4GTR_R1WLSL_Msk (0x3ul << DDRPHY_DX4GTR_R1WLSL_Pos) /*!< DDRPHY_T::DX4GTR: R1WLSL Mask */ + +#define DDRPHY_DX4GTR_R2WLSL_Pos (16) /*!< DDRPHY_T::DX4GTR: R2WLSL Position */ +#define DDRPHY_DX4GTR_R2WLSL_Msk (0x3ul << DDRPHY_DX4GTR_R2WLSL_Pos) /*!< DDRPHY_T::DX4GTR: R2WLSL Mask */ + +#define DDRPHY_DX4GTR_R3WLSL_Pos (18) /*!< DDRPHY_T::DX4GTR: R3WLSL Position */ +#define DDRPHY_DX4GTR_R3WLSL_Msk (0x3ul << DDRPHY_DX4GTR_R3WLSL_Pos) /*!< DDRPHY_T::DX4GTR: R3WLSL Mask */ + +#define DDRPHY_DX4GSR2_RDERR_Pos (0) /*!< DDRPHY_T::DX4GSR2: RDERR Position */ +#define DDRPHY_DX4GSR2_RDERR_Msk (0x1ul << DDRPHY_DX4GSR2_RDERR_Pos) /*!< DDRPHY_T::DX4GSR2: RDERR Mask */ + +#define DDRPHY_DX4GSR2_RDWN_Pos (1) /*!< DDRPHY_T::DX4GSR2: RDWN Position */ +#define DDRPHY_DX4GSR2_RDWN_Msk (0x1ul << DDRPHY_DX4GSR2_RDWN_Pos) /*!< DDRPHY_T::DX4GSR2: RDWN Mask */ + +#define DDRPHY_DX4GSR2_WDERR_Pos (2) /*!< DDRPHY_T::DX4GSR2: WDERR Position */ +#define DDRPHY_DX4GSR2_WDERR_Msk (0x1ul << DDRPHY_DX4GSR2_WDERR_Pos) /*!< DDRPHY_T::DX4GSR2: WDERR Mask */ + +#define DDRPHY_DX4GSR2_WDWN_Pos (3) /*!< DDRPHY_T::DX4GSR2: WDWN Position */ +#define DDRPHY_DX4GSR2_WDWN_Msk (0x1ul << DDRPHY_DX4GSR2_WDWN_Pos) /*!< DDRPHY_T::DX4GSR2: WDWN Mask */ + +#define DDRPHY_DX4GSR2_REERR_Pos (4) /*!< DDRPHY_T::DX4GSR2: REERR Position */ +#define DDRPHY_DX4GSR2_REERR_Msk (0x1ul << DDRPHY_DX4GSR2_REERR_Pos) /*!< DDRPHY_T::DX4GSR2: REERR Mask */ + +#define DDRPHY_DX4GSR2_REWN_Pos (5) /*!< DDRPHY_T::DX4GSR2: REWN Position */ +#define DDRPHY_DX4GSR2_REWN_Msk (0x1ul << DDRPHY_DX4GSR2_REWN_Pos) /*!< DDRPHY_T::DX4GSR2: REWN Mask */ + +#define DDRPHY_DX4GSR2_WEERR_Pos (6) /*!< DDRPHY_T::DX4GSR2: WEERR Position */ +#define DDRPHY_DX4GSR2_WEERR_Msk (0x1ul << DDRPHY_DX4GSR2_WEERR_Pos) /*!< DDRPHY_T::DX4GSR2: WEERR Mask */ + +#define DDRPHY_DX4GSR2_WEWN_Pos (7) /*!< DDRPHY_T::DX4GSR2: WEWN Position */ +#define DDRPHY_DX4GSR2_WEWN_Msk (0x1ul << DDRPHY_DX4GSR2_WEWN_Pos) /*!< DDRPHY_T::DX4GSR2: WEWN Mask */ + +#define DDRPHY_DX4GSR2_ESTAT_Pos (8) /*!< DDRPHY_T::DX4GSR2: ESTAT Position */ +#define DDRPHY_DX4GSR2_ESTAT_Msk (0xful << DDRPHY_DX4GSR2_ESTAT_Pos) /*!< DDRPHY_T::DX4GSR2: ESTAT Mask */ + +#define DDRPHY_DX5GCR_DXEN_Pos (0) /*!< DDRPHY_T::DX5GCR: DXEN Position */ +#define DDRPHY_DX5GCR_DXEN_Msk (0x1ul << DDRPHY_DX5GCR_DXEN_Pos) /*!< DDRPHY_T::DX5GCR: DXEN Mask */ + +#define DDRPHY_DX5GCR_DQSODT_Pos (1) /*!< DDRPHY_T::DX5GCR: DQSODT Position */ +#define DDRPHY_DX5GCR_DQSODT_Msk (0x1ul << DDRPHY_DX5GCR_DQSODT_Pos) /*!< DDRPHY_T::DX5GCR: DQSODT Mask */ + +#define DDRPHY_DX5GCR_DQODT_Pos (2) /*!< DDRPHY_T::DX5GCR: DQODT Position */ +#define DDRPHY_DX5GCR_DQODT_Msk (0x1ul << DDRPHY_DX5GCR_DQODT_Pos) /*!< DDRPHY_T::DX5GCR: DQODT Mask */ + +#define DDRPHY_DX5GCR_DXIOM_Pos (3) /*!< DDRPHY_T::DX5GCR: DXIOM Position */ +#define DDRPHY_DX5GCR_DXIOM_Msk (0x1ul << DDRPHY_DX5GCR_DXIOM_Pos) /*!< DDRPHY_T::DX5GCR: DXIOM Mask */ + +#define DDRPHY_DX5GCR_DXPDD_Pos (4) /*!< DDRPHY_T::DX5GCR: DXPDD Position */ +#define DDRPHY_DX5GCR_DXPDD_Msk (0x1ul << DDRPHY_DX5GCR_DXPDD_Pos) /*!< DDRPHY_T::DX5GCR: DXPDD Mask */ + +#define DDRPHY_DX5GCR_DXPDR_Pos (5) /*!< DDRPHY_T::DX5GCR: DXPDR Position */ +#define DDRPHY_DX5GCR_DXPDR_Msk (0x1ul << DDRPHY_DX5GCR_DXPDR_Pos) /*!< DDRPHY_T::DX5GCR: DXPDR Mask */ + +#define DDRPHY_DX5GCR_DQSRPD_Pos (6) /*!< DDRPHY_T::DX5GCR: DQSRPD Position */ +#define DDRPHY_DX5GCR_DQSRPD_Msk (0x1ul << DDRPHY_DX5GCR_DQSRPD_Pos) /*!< DDRPHY_T::DX5GCR: DQSRPD Mask */ + +#define DDRPHY_DX5GCR_DSEN_Pos (7) /*!< DDRPHY_T::DX5GCR: DSEN Position */ +#define DDRPHY_DX5GCR_DSEN_Msk (0x3ul << DDRPHY_DX5GCR_DSEN_Pos) /*!< DDRPHY_T::DX5GCR: DSEN Mask */ + +#define DDRPHY_DX5GCR_DQSRTT_Pos (9) /*!< DDRPHY_T::DX5GCR: DQSRTT Position */ +#define DDRPHY_DX5GCR_DQSRTT_Msk (0x1ul << DDRPHY_DX5GCR_DQSRTT_Pos) /*!< DDRPHY_T::DX5GCR: DQSRTT Mask */ + +#define DDRPHY_DX5GCR_DQRTT_Pos (10) /*!< DDRPHY_T::DX5GCR: DQRTT Position */ +#define DDRPHY_DX5GCR_DQRTT_Msk (0x1ul << DDRPHY_DX5GCR_DQRTT_Pos) /*!< DDRPHY_T::DX5GCR: DQRTT Mask */ + +#define DDRPHY_DX5GCR_RTTOH_Pos (11) /*!< DDRPHY_T::DX5GCR: RTTOH Position */ +#define DDRPHY_DX5GCR_RTTOH_Msk (0x3ul << DDRPHY_DX5GCR_RTTOH_Pos) /*!< DDRPHY_T::DX5GCR: RTTOH Mask */ + +#define DDRPHY_DX5GCR_RTTOAL_Pos (13) /*!< DDRPHY_T::DX5GCR: RTTOAL Position */ +#define DDRPHY_DX5GCR_RTTOAL_Msk (0x1ul << DDRPHY_DX5GCR_RTTOAL_Pos) /*!< DDRPHY_T::DX5GCR: RTTOAL Mask */ + +#define DDRPHY_DX5GCR_DXOEO_Pos (14) /*!< DDRPHY_T::DX5GCR: DXOEO Position */ +#define DDRPHY_DX5GCR_DXOEO_Msk (0x3ul << DDRPHY_DX5GCR_DXOEO_Pos) /*!< DDRPHY_T::DX5GCR: DXOEO Mask */ + +#define DDRPHY_DX5GCR_PLLRST_Pos (16) /*!< DDRPHY_T::DX5GCR: PLLRST Position */ +#define DDRPHY_DX5GCR_PLLRST_Msk (0x1ul << DDRPHY_DX5GCR_PLLRST_Pos) /*!< DDRPHY_T::DX5GCR: PLLRST Mask */ + +#define DDRPHY_DX5GCR_PLLPD_Pos (17) /*!< DDRPHY_T::DX5GCR: PLLPD Position */ +#define DDRPHY_DX5GCR_PLLPD_Msk (0x1ul << DDRPHY_DX5GCR_PLLPD_Pos) /*!< DDRPHY_T::DX5GCR: PLLPD Mask */ + +#define DDRPHY_DX5GCR_GSHIFT_Pos (18) /*!< DDRPHY_T::DX5GCR: GSHIFT Position */ +#define DDRPHY_DX5GCR_GSHIFT_Msk (0x1ul << DDRPHY_DX5GCR_GSHIFT_Pos) /*!< DDRPHY_T::DX5GCR: GSHIFT Mask */ + +#define DDRPHY_DX5GCR_PLLBYP_Pos (19) /*!< DDRPHY_T::DX5GCR: PLLBYP Position */ +#define DDRPHY_DX5GCR_PLLBYP_Msk (0x1ul << DDRPHY_DX5GCR_PLLBYP_Pos) /*!< DDRPHY_T::DX5GCR: PLLBYP Mask */ + +#define DDRPHY_DX5GCR_WLRKEN_Pos (26) /*!< DDRPHY_T::DX5GCR: WLRKEN Position */ +#define DDRPHY_DX5GCR_WLRKEN_Msk (0xful << DDRPHY_DX5GCR_WLRKEN_Pos) /*!< DDRPHY_T::DX5GCR: WLRKEN Mask */ + +#define DDRPHY_DX5GCR_MDLEN_Pos (30) /*!< DDRPHY_T::DX5GCR: MDLEN Position */ +#define DDRPHY_DX5GCR_MDLEN_Msk (0x1ul << DDRPHY_DX5GCR_MDLEN_Pos) /*!< DDRPHY_T::DX5GCR: MDLEN Mask */ + +#define DDRPHY_DX5GCR_CALBYP_Pos (31) /*!< DDRPHY_T::DX5GCR: CALBYP Position */ +#define DDRPHY_DX5GCR_CALBYP_Msk (0x1ul << DDRPHY_DX5GCR_CALBYP_Pos) /*!< DDRPHY_T::DX5GCR: CALBYP Mask */ + +#define DDRPHY_DX5GSR0_WDQCAL_Pos (0) /*!< DDRPHY_T::DX5GSR0: WDQCAL Position */ +#define DDRPHY_DX5GSR0_WDQCAL_Msk (0x1ul << DDRPHY_DX5GSR0_WDQCAL_Pos) /*!< DDRPHY_T::DX5GSR0: WDQCAL Mask */ + +#define DDRPHY_DX5GSR0_RDQSCAL_Pos (1) /*!< DDRPHY_T::DX5GSR0: RDQSCAL Position */ +#define DDRPHY_DX5GSR0_RDQSCAL_Msk (0x1ul << DDRPHY_DX5GSR0_RDQSCAL_Pos) /*!< DDRPHY_T::DX5GSR0: RDQSCAL Mask */ + +#define DDRPHY_DX5GSR0_RDQSNCAL_Pos (2) /*!< DDRPHY_T::DX5GSR0: RDQSNCAL Position */ +#define DDRPHY_DX5GSR0_RDQSNCAL_Msk (0x1ul << DDRPHY_DX5GSR0_RDQSNCAL_Pos) /*!< DDRPHY_T::DX5GSR0: RDQSNCAL Mask */ + +#define DDRPHY_DX5GSR0_GDQSCAL_Pos (3) /*!< DDRPHY_T::DX5GSR0: GDQSCAL Position */ +#define DDRPHY_DX5GSR0_GDQSCAL_Msk (0x1ul << DDRPHY_DX5GSR0_GDQSCAL_Pos) /*!< DDRPHY_T::DX5GSR0: GDQSCAL Mask */ + +#define DDRPHY_DX5GSR0_WLCAL_Pos (4) /*!< DDRPHY_T::DX5GSR0: WLCAL Position */ +#define DDRPHY_DX5GSR0_WLCAL_Msk (0x1ul << DDRPHY_DX5GSR0_WLCAL_Pos) /*!< DDRPHY_T::DX5GSR0: WLCAL Mask */ + +#define DDRPHY_DX5GSR0_WLDONE_Pos (5) /*!< DDRPHY_T::DX5GSR0: WLDONE Position */ +#define DDRPHY_DX5GSR0_WLDONE_Msk (0x1ul << DDRPHY_DX5GSR0_WLDONE_Pos) /*!< DDRPHY_T::DX5GSR0: WLDONE Mask */ + +#define DDRPHY_DX5GSR0_WLERR_Pos (6) /*!< DDRPHY_T::DX5GSR0: WLERR Position */ +#define DDRPHY_DX5GSR0_WLERR_Msk (0x1ul << DDRPHY_DX5GSR0_WLERR_Pos) /*!< DDRPHY_T::DX5GSR0: WLERR Mask */ + +#define DDRPHY_DX5GSR0_WLPRD_Pos (7) /*!< DDRPHY_T::DX5GSR0: WLPRD Position */ +#define DDRPHY_DX5GSR0_WLPRD_Msk (0xfful << DDRPHY_DX5GSR0_WLPRD_Pos) /*!< DDRPHY_T::DX5GSR0: WLPRD Mask */ + +#define DDRPHY_DX5GSR0_DPLOCK_Pos (15) /*!< DDRPHY_T::DX5GSR0: DPLOCK Position */ +#define DDRPHY_DX5GSR0_DPLOCK_Msk (0x1ul << DDRPHY_DX5GSR0_DPLOCK_Pos) /*!< DDRPHY_T::DX5GSR0: DPLOCK Mask */ + +#define DDRPHY_DX5GSR0_GDQSPRD_Pos (16) /*!< DDRPHY_T::DX5GSR0: GDQSPRD Position */ +#define DDRPHY_DX5GSR0_GDQSPRD_Msk (0xfful << DDRPHY_DX5GSR0_GDQSPRD_Pos) /*!< DDRPHY_T::DX5GSR0: GDQSPRD Mask */ + +#define DDRPHY_DX5GSR0_QSGERR_Pos (24) /*!< DDRPHY_T::DX5GSR0: QSGERR Position */ +#define DDRPHY_DX5GSR0_QSGERR_Msk (0xful << DDRPHY_DX5GSR0_QSGERR_Pos) /*!< DDRPHY_T::DX5GSR0: QSGERR Mask */ + +#define DDRPHY_DX5GSR0_WLDQ_Pos (28) /*!< DDRPHY_T::DX5GSR0: WLDQ Position */ +#define DDRPHY_DX5GSR0_WLDQ_Msk (0x1ul << DDRPHY_DX5GSR0_WLDQ_Pos) /*!< DDRPHY_T::DX5GSR0: WLDQ Mask */ + +#define DDRPHY_DX5GSR1_DLTDONE_Pos (0) /*!< DDRPHY_T::DX5GSR1: DLTDONE Position */ +#define DDRPHY_DX5GSR1_DLTDONE_Msk (0x1ul << DDRPHY_DX5GSR1_DLTDONE_Pos) /*!< DDRPHY_T::DX5GSR1: DLTDONE Mask */ + +#define DDRPHY_DX5GSR1_DLTCODE_Pos (1) /*!< DDRPHY_T::DX5GSR1: DLTCODE Position */ +#define DDRPHY_DX5GSR1_DLTCODE_Msk (0xfffffful << DDRPHY_DX5GSR1_DLTCODE_Pos) /*!< DDRPHY_T::DX5GSR1: DLTCODE Mask */ + +#define DDRPHY_DX5BDLR0_DQ0WBD_Pos (0) /*!< DDRPHY_T::DX5BDLR0: DQ0WBD Position */ +#define DDRPHY_DX5BDLR0_DQ0WBD_Msk (0x3ful << DDRPHY_DX5BDLR0_DQ0WBD_Pos) /*!< DDRPHY_T::DX5BDLR0: DQ0WBD Mask */ + +#define DDRPHY_DX5BDLR0_DQ1WBD_Pos (6) /*!< DDRPHY_T::DX5BDLR0: DQ1WBD Position */ +#define DDRPHY_DX5BDLR0_DQ1WBD_Msk (0x3ful << DDRPHY_DX5BDLR0_DQ1WBD_Pos) /*!< DDRPHY_T::DX5BDLR0: DQ1WBD Mask */ + +#define DDRPHY_DX5BDLR0_DQ2WBD_Pos (12) /*!< DDRPHY_T::DX5BDLR0: DQ2WBD Position */ +#define DDRPHY_DX5BDLR0_DQ2WBD_Msk (0x3ful << DDRPHY_DX5BDLR0_DQ2WBD_Pos) /*!< DDRPHY_T::DX5BDLR0: DQ2WBD Mask */ + +#define DDRPHY_DX5BDLR0_DQ3WBD_Pos (18) /*!< DDRPHY_T::DX5BDLR0: DQ3WBD Position */ +#define DDRPHY_DX5BDLR0_DQ3WBD_Msk (0x3ful << DDRPHY_DX5BDLR0_DQ3WBD_Pos) /*!< DDRPHY_T::DX5BDLR0: DQ3WBD Mask */ + +#define DDRPHY_DX5BDLR0_DQ4WBD_Pos (24) /*!< DDRPHY_T::DX5BDLR0: DQ4WBD Position */ +#define DDRPHY_DX5BDLR0_DQ4WBD_Msk (0x3ful << DDRPHY_DX5BDLR0_DQ4WBD_Pos) /*!< DDRPHY_T::DX5BDLR0: DQ4WBD Mask */ + +#define DDRPHY_DX5BDLR1_DQ5WBD_Pos (0) /*!< DDRPHY_T::DX5BDLR1: DQ5WBD Position */ +#define DDRPHY_DX5BDLR1_DQ5WBD_Msk (0x3ful << DDRPHY_DX5BDLR1_DQ5WBD_Pos) /*!< DDRPHY_T::DX5BDLR1: DQ5WBD Mask */ + +#define DDRPHY_DX5BDLR1_DQ6WBD_Pos (6) /*!< DDRPHY_T::DX5BDLR1: DQ6WBD Position */ +#define DDRPHY_DX5BDLR1_DQ6WBD_Msk (0x3ful << DDRPHY_DX5BDLR1_DQ6WBD_Pos) /*!< DDRPHY_T::DX5BDLR1: DQ6WBD Mask */ + +#define DDRPHY_DX5BDLR1_DQ7WBD_Pos (12) /*!< DDRPHY_T::DX5BDLR1: DQ7WBD Position */ +#define DDRPHY_DX5BDLR1_DQ7WBD_Msk (0x3ful << DDRPHY_DX5BDLR1_DQ7WBD_Pos) /*!< DDRPHY_T::DX5BDLR1: DQ7WBD Mask */ + +#define DDRPHY_DX5BDLR1_DMWBD_Pos (18) /*!< DDRPHY_T::DX5BDLR1: DMWBD Position */ +#define DDRPHY_DX5BDLR1_DMWBD_Msk (0x3ful << DDRPHY_DX5BDLR1_DMWBD_Pos) /*!< DDRPHY_T::DX5BDLR1: DMWBD Mask */ + +#define DDRPHY_DX5BDLR1_DSWBD_Pos (24) /*!< DDRPHY_T::DX5BDLR1: DSWBD Position */ +#define DDRPHY_DX5BDLR1_DSWBD_Msk (0x3ful << DDRPHY_DX5BDLR1_DSWBD_Pos) /*!< DDRPHY_T::DX5BDLR1: DSWBD Mask */ + +#define DDRPHY_DX5BDLR2_DSOEBD_Pos (0) /*!< DDRPHY_T::DX5BDLR2: DSOEBD Position */ +#define DDRPHY_DX5BDLR2_DSOEBD_Msk (0x3ful << DDRPHY_DX5BDLR2_DSOEBD_Pos) /*!< DDRPHY_T::DX5BDLR2: DSOEBD Mask */ + +#define DDRPHY_DX5BDLR2_DQOEBD_Pos (6) /*!< DDRPHY_T::DX5BDLR2: DQOEBD Position */ +#define DDRPHY_DX5BDLR2_DQOEBD_Msk (0x3ful << DDRPHY_DX5BDLR2_DQOEBD_Pos) /*!< DDRPHY_T::DX5BDLR2: DQOEBD Mask */ + +#define DDRPHY_DX5BDLR2_DSRBD_Pos (12) /*!< DDRPHY_T::DX5BDLR2: DSRBD Position */ +#define DDRPHY_DX5BDLR2_DSRBD_Msk (0x3ful << DDRPHY_DX5BDLR2_DSRBD_Pos) /*!< DDRPHY_T::DX5BDLR2: DSRBD Mask */ + +#define DDRPHY_DX5BDLR2_DSNRBD_Pos (18) /*!< DDRPHY_T::DX5BDLR2: DSNRBD Position */ +#define DDRPHY_DX5BDLR2_DSNRBD_Msk (0x3ful << DDRPHY_DX5BDLR2_DSNRBD_Pos) /*!< DDRPHY_T::DX5BDLR2: DSNRBD Mask */ + +#define DDRPHY_DX5BDLR3_DQ0RBD_Pos (0) /*!< DDRPHY_T::DX5BDLR3: DQ0RBD Position */ +#define DDRPHY_DX5BDLR3_DQ0RBD_Msk (0x3ful << DDRPHY_DX5BDLR3_DQ0RBD_Pos) /*!< DDRPHY_T::DX5BDLR3: DQ0RBD Mask */ + +#define DDRPHY_DX5BDLR3_DQ1RBD_Pos (6) /*!< DDRPHY_T::DX5BDLR3: DQ1RBD Position */ +#define DDRPHY_DX5BDLR3_DQ1RBD_Msk (0x3ful << DDRPHY_DX5BDLR3_DQ1RBD_Pos) /*!< DDRPHY_T::DX5BDLR3: DQ1RBD Mask */ + +#define DDRPHY_DX5BDLR3_DQ2RBD_Pos (12) /*!< DDRPHY_T::DX5BDLR3: DQ2RBD Position */ +#define DDRPHY_DX5BDLR3_DQ2RBD_Msk (0x3ful << DDRPHY_DX5BDLR3_DQ2RBD_Pos) /*!< DDRPHY_T::DX5BDLR3: DQ2RBD Mask */ + +#define DDRPHY_DX5BDLR3_DQ3RBD_Pos (18) /*!< DDRPHY_T::DX5BDLR3: DQ3RBD Position */ +#define DDRPHY_DX5BDLR3_DQ3RBD_Msk (0x3ful << DDRPHY_DX5BDLR3_DQ3RBD_Pos) /*!< DDRPHY_T::DX5BDLR3: DQ3RBD Mask */ + +#define DDRPHY_DX5BDLR3_DQ4RBD_Pos (24) /*!< DDRPHY_T::DX5BDLR3: DQ4RBD Position */ +#define DDRPHY_DX5BDLR3_DQ4RBD_Msk (0x3ful << DDRPHY_DX5BDLR3_DQ4RBD_Pos) /*!< DDRPHY_T::DX5BDLR3: DQ4RBD Mask */ + +#define DDRPHY_DX5BDLR4_DQ5RBD_Pos (0) /*!< DDRPHY_T::DX5BDLR4: DQ5RBD Position */ +#define DDRPHY_DX5BDLR4_DQ5RBD_Msk (0x3ful << DDRPHY_DX5BDLR4_DQ5RBD_Pos) /*!< DDRPHY_T::DX5BDLR4: DQ5RBD Mask */ + +#define DDRPHY_DX5BDLR4_DQ6RBD_Pos (6) /*!< DDRPHY_T::DX5BDLR4: DQ6RBD Position */ +#define DDRPHY_DX5BDLR4_DQ6RBD_Msk (0x3ful << DDRPHY_DX5BDLR4_DQ6RBD_Pos) /*!< DDRPHY_T::DX5BDLR4: DQ6RBD Mask */ + +#define DDRPHY_DX5BDLR4_DQ7RBD_Pos (12) /*!< DDRPHY_T::DX5BDLR4: DQ7RBD Position */ +#define DDRPHY_DX5BDLR4_DQ7RBD_Msk (0x3ful << DDRPHY_DX5BDLR4_DQ7RBD_Pos) /*!< DDRPHY_T::DX5BDLR4: DQ7RBD Mask */ + +#define DDRPHY_DX5BDLR4_DMRBD_Pos (18) /*!< DDRPHY_T::DX5BDLR4: DMRBD Position */ +#define DDRPHY_DX5BDLR4_DMRBD_Msk (0x3ful << DDRPHY_DX5BDLR4_DMRBD_Pos) /*!< DDRPHY_T::DX5BDLR4: DMRBD Mask */ + +#define DDRPHY_DX5LCDLR0_R0WLD_Pos (0) /*!< DDRPHY_T::DX5LCDLR0: R0WLD Position */ +#define DDRPHY_DX5LCDLR0_R0WLD_Msk (0xfful << DDRPHY_DX5LCDLR0_R0WLD_Pos) /*!< DDRPHY_T::DX5LCDLR0: R0WLD Mask */ + +#define DDRPHY_DX5LCDLR0_R1WLD_Pos (8) /*!< DDRPHY_T::DX5LCDLR0: R1WLD Position */ +#define DDRPHY_DX5LCDLR0_R1WLD_Msk (0xfful << DDRPHY_DX5LCDLR0_R1WLD_Pos) /*!< DDRPHY_T::DX5LCDLR0: R1WLD Mask */ + +#define DDRPHY_DX5LCDLR0_R2WLD_Pos (16) /*!< DDRPHY_T::DX5LCDLR0: R2WLD Position */ +#define DDRPHY_DX5LCDLR0_R2WLD_Msk (0xfful << DDRPHY_DX5LCDLR0_R2WLD_Pos) /*!< DDRPHY_T::DX5LCDLR0: R2WLD Mask */ + +#define DDRPHY_DX5LCDLR0_R3WLD_Pos (24) /*!< DDRPHY_T::DX5LCDLR0: R3WLD Position */ +#define DDRPHY_DX5LCDLR0_R3WLD_Msk (0xfful << DDRPHY_DX5LCDLR0_R3WLD_Pos) /*!< DDRPHY_T::DX5LCDLR0: R3WLD Mask */ + +#define DDRPHY_DX5LCDLR1_WDQD_Pos (0) /*!< DDRPHY_T::DX5LCDLR1: WDQD Position */ +#define DDRPHY_DX5LCDLR1_WDQD_Msk (0xfful << DDRPHY_DX5LCDLR1_WDQD_Pos) /*!< DDRPHY_T::DX5LCDLR1: WDQD Mask */ + +#define DDRPHY_DX5LCDLR1_RDQSD_Pos (8) /*!< DDRPHY_T::DX5LCDLR1: RDQSD Position */ +#define DDRPHY_DX5LCDLR1_RDQSD_Msk (0xfful << DDRPHY_DX5LCDLR1_RDQSD_Pos) /*!< DDRPHY_T::DX5LCDLR1: RDQSD Mask */ + +#define DDRPHY_DX5LCDLR1_RDQSND_Pos (16) /*!< DDRPHY_T::DX5LCDLR1: RDQSND Position */ +#define DDRPHY_DX5LCDLR1_RDQSND_Msk (0xfful << DDRPHY_DX5LCDLR1_RDQSND_Pos) /*!< DDRPHY_T::DX5LCDLR1: RDQSND Mask */ + +#define DDRPHY_DX5LCDLR2_R0DQSGD_Pos (0) /*!< DDRPHY_T::DX5LCDLR2: R0DQSGD Position */ +#define DDRPHY_DX5LCDLR2_R0DQSGD_Msk (0xfful << DDRPHY_DX5LCDLR2_R0DQSGD_Pos) /*!< DDRPHY_T::DX5LCDLR2: R0DQSGD Mask */ + +#define DDRPHY_DX5LCDLR2_R1DQSGD_Pos (8) /*!< DDRPHY_T::DX5LCDLR2: R1DQSGD Position */ +#define DDRPHY_DX5LCDLR2_R1DQSGD_Msk (0xfful << DDRPHY_DX5LCDLR2_R1DQSGD_Pos) /*!< DDRPHY_T::DX5LCDLR2: R1DQSGD Mask */ + +#define DDRPHY_DX5LCDLR2_R2DQSGD_Pos (16) /*!< DDRPHY_T::DX5LCDLR2: R2DQSGD Position */ +#define DDRPHY_DX5LCDLR2_R2DQSGD_Msk (0xfful << DDRPHY_DX5LCDLR2_R2DQSGD_Pos) /*!< DDRPHY_T::DX5LCDLR2: R2DQSGD Mask */ + +#define DDRPHY_DX5LCDLR2_R3DQSGD_Pos (24) /*!< DDRPHY_T::DX5LCDLR2: R3DQSGD Position */ +#define DDRPHY_DX5LCDLR2_R3DQSGD_Msk (0xfful << DDRPHY_DX5LCDLR2_R3DQSGD_Pos) /*!< DDRPHY_T::DX5LCDLR2: R3DQSGD Mask */ + +#define DDRPHY_DX5MDLR_IPRD_Pos (0) /*!< DDRPHY_T::DX5MDLR: IPRD Position */ +#define DDRPHY_DX5MDLR_IPRD_Msk (0xfful << DDRPHY_DX5MDLR_IPRD_Pos) /*!< DDRPHY_T::DX5MDLR: IPRD Mask */ + +#define DDRPHY_DX5MDLR_TPRD_Pos (8) /*!< DDRPHY_T::DX5MDLR: TPRD Position */ +#define DDRPHY_DX5MDLR_TPRD_Msk (0xfful << DDRPHY_DX5MDLR_TPRD_Pos) /*!< DDRPHY_T::DX5MDLR: TPRD Mask */ + +#define DDRPHY_DX5MDLR_MDLD_Pos (16) /*!< DDRPHY_T::DX5MDLR: MDLD Position */ +#define DDRPHY_DX5MDLR_MDLD_Msk (0xfful << DDRPHY_DX5MDLR_MDLD_Pos) /*!< DDRPHY_T::DX5MDLR: MDLD Mask */ + +#define DDRPHY_DX5GTR_R0DGSL_Pos (0) /*!< DDRPHY_T::DX5GTR: R0DGSL Position */ +#define DDRPHY_DX5GTR_R0DGSL_Msk (0x7ul << DDRPHY_DX5GTR_R0DGSL_Pos) /*!< DDRPHY_T::DX5GTR: R0DGSL Mask */ + +#define DDRPHY_DX5GTR_R1DGSL_Pos (3) /*!< DDRPHY_T::DX5GTR: R1DGSL Position */ +#define DDRPHY_DX5GTR_R1DGSL_Msk (0x7ul << DDRPHY_DX5GTR_R1DGSL_Pos) /*!< DDRPHY_T::DX5GTR: R1DGSL Mask */ + +#define DDRPHY_DX5GTR_R2DGSL_Pos (6) /*!< DDRPHY_T::DX5GTR: R2DGSL Position */ +#define DDRPHY_DX5GTR_R2DGSL_Msk (0x7ul << DDRPHY_DX5GTR_R2DGSL_Pos) /*!< DDRPHY_T::DX5GTR: R2DGSL Mask */ + +#define DDRPHY_DX5GTR_R3DGSL_Pos (9) /*!< DDRPHY_T::DX5GTR: R3DGSL Position */ +#define DDRPHY_DX5GTR_R3DGSL_Msk (0x7ul << DDRPHY_DX5GTR_R3DGSL_Pos) /*!< DDRPHY_T::DX5GTR: R3DGSL Mask */ + +#define DDRPHY_DX5GTR_R0WLSL_Pos (12) /*!< DDRPHY_T::DX5GTR: R0WLSL Position */ +#define DDRPHY_DX5GTR_R0WLSL_Msk (0x3ul << DDRPHY_DX5GTR_R0WLSL_Pos) /*!< DDRPHY_T::DX5GTR: R0WLSL Mask */ + +#define DDRPHY_DX5GTR_R1WLSL_Pos (14) /*!< DDRPHY_T::DX5GTR: R1WLSL Position */ +#define DDRPHY_DX5GTR_R1WLSL_Msk (0x3ul << DDRPHY_DX5GTR_R1WLSL_Pos) /*!< DDRPHY_T::DX5GTR: R1WLSL Mask */ + +#define DDRPHY_DX5GTR_R2WLSL_Pos (16) /*!< DDRPHY_T::DX5GTR: R2WLSL Position */ +#define DDRPHY_DX5GTR_R2WLSL_Msk (0x3ul << DDRPHY_DX5GTR_R2WLSL_Pos) /*!< DDRPHY_T::DX5GTR: R2WLSL Mask */ + +#define DDRPHY_DX5GTR_R3WLSL_Pos (18) /*!< DDRPHY_T::DX5GTR: R3WLSL Position */ +#define DDRPHY_DX5GTR_R3WLSL_Msk (0x3ul << DDRPHY_DX5GTR_R3WLSL_Pos) /*!< DDRPHY_T::DX5GTR: R3WLSL Mask */ + +#define DDRPHY_DX5GSR2_RDERR_Pos (0) /*!< DDRPHY_T::DX5GSR2: RDERR Position */ +#define DDRPHY_DX5GSR2_RDERR_Msk (0x1ul << DDRPHY_DX5GSR2_RDERR_Pos) /*!< DDRPHY_T::DX5GSR2: RDERR Mask */ + +#define DDRPHY_DX5GSR2_RDWN_Pos (1) /*!< DDRPHY_T::DX5GSR2: RDWN Position */ +#define DDRPHY_DX5GSR2_RDWN_Msk (0x1ul << DDRPHY_DX5GSR2_RDWN_Pos) /*!< DDRPHY_T::DX5GSR2: RDWN Mask */ + +#define DDRPHY_DX5GSR2_WDERR_Pos (2) /*!< DDRPHY_T::DX5GSR2: WDERR Position */ +#define DDRPHY_DX5GSR2_WDERR_Msk (0x1ul << DDRPHY_DX5GSR2_WDERR_Pos) /*!< DDRPHY_T::DX5GSR2: WDERR Mask */ + +#define DDRPHY_DX5GSR2_WDWN_Pos (3) /*!< DDRPHY_T::DX5GSR2: WDWN Position */ +#define DDRPHY_DX5GSR2_WDWN_Msk (0x1ul << DDRPHY_DX5GSR2_WDWN_Pos) /*!< DDRPHY_T::DX5GSR2: WDWN Mask */ + +#define DDRPHY_DX5GSR2_REERR_Pos (4) /*!< DDRPHY_T::DX5GSR2: REERR Position */ +#define DDRPHY_DX5GSR2_REERR_Msk (0x1ul << DDRPHY_DX5GSR2_REERR_Pos) /*!< DDRPHY_T::DX5GSR2: REERR Mask */ + +#define DDRPHY_DX5GSR2_REWN_Pos (5) /*!< DDRPHY_T::DX5GSR2: REWN Position */ +#define DDRPHY_DX5GSR2_REWN_Msk (0x1ul << DDRPHY_DX5GSR2_REWN_Pos) /*!< DDRPHY_T::DX5GSR2: REWN Mask */ + +#define DDRPHY_DX5GSR2_WEERR_Pos (6) /*!< DDRPHY_T::DX5GSR2: WEERR Position */ +#define DDRPHY_DX5GSR2_WEERR_Msk (0x1ul << DDRPHY_DX5GSR2_WEERR_Pos) /*!< DDRPHY_T::DX5GSR2: WEERR Mask */ + +#define DDRPHY_DX5GSR2_WEWN_Pos (7) /*!< DDRPHY_T::DX5GSR2: WEWN Position */ +#define DDRPHY_DX5GSR2_WEWN_Msk (0x1ul << DDRPHY_DX5GSR2_WEWN_Pos) /*!< DDRPHY_T::DX5GSR2: WEWN Mask */ + +#define DDRPHY_DX5GSR2_ESTAT_Pos (8) /*!< DDRPHY_T::DX5GSR2: ESTAT Position */ +#define DDRPHY_DX5GSR2_ESTAT_Msk (0xful << DDRPHY_DX5GSR2_ESTAT_Pos) /*!< DDRPHY_T::DX5GSR2: ESTAT Mask */ + +#define DDRPHY_DX6GCR_DXEN_Pos (0) /*!< DDRPHY_T::DX6GCR: DXEN Position */ +#define DDRPHY_DX6GCR_DXEN_Msk (0x1ul << DDRPHY_DX6GCR_DXEN_Pos) /*!< DDRPHY_T::DX6GCR: DXEN Mask */ + +#define DDRPHY_DX6GCR_DQSODT_Pos (1) /*!< DDRPHY_T::DX6GCR: DQSODT Position */ +#define DDRPHY_DX6GCR_DQSODT_Msk (0x1ul << DDRPHY_DX6GCR_DQSODT_Pos) /*!< DDRPHY_T::DX6GCR: DQSODT Mask */ + +#define DDRPHY_DX6GCR_DQODT_Pos (2) /*!< DDRPHY_T::DX6GCR: DQODT Position */ +#define DDRPHY_DX6GCR_DQODT_Msk (0x1ul << DDRPHY_DX6GCR_DQODT_Pos) /*!< DDRPHY_T::DX6GCR: DQODT Mask */ + +#define DDRPHY_DX6GCR_DXIOM_Pos (3) /*!< DDRPHY_T::DX6GCR: DXIOM Position */ +#define DDRPHY_DX6GCR_DXIOM_Msk (0x1ul << DDRPHY_DX6GCR_DXIOM_Pos) /*!< DDRPHY_T::DX6GCR: DXIOM Mask */ + +#define DDRPHY_DX6GCR_DXPDD_Pos (4) /*!< DDRPHY_T::DX6GCR: DXPDD Position */ +#define DDRPHY_DX6GCR_DXPDD_Msk (0x1ul << DDRPHY_DX6GCR_DXPDD_Pos) /*!< DDRPHY_T::DX6GCR: DXPDD Mask */ + +#define DDRPHY_DX6GCR_DXPDR_Pos (5) /*!< DDRPHY_T::DX6GCR: DXPDR Position */ +#define DDRPHY_DX6GCR_DXPDR_Msk (0x1ul << DDRPHY_DX6GCR_DXPDR_Pos) /*!< DDRPHY_T::DX6GCR: DXPDR Mask */ + +#define DDRPHY_DX6GCR_DQSRPD_Pos (6) /*!< DDRPHY_T::DX6GCR: DQSRPD Position */ +#define DDRPHY_DX6GCR_DQSRPD_Msk (0x1ul << DDRPHY_DX6GCR_DQSRPD_Pos) /*!< DDRPHY_T::DX6GCR: DQSRPD Mask */ + +#define DDRPHY_DX6GCR_DSEN_Pos (7) /*!< DDRPHY_T::DX6GCR: DSEN Position */ +#define DDRPHY_DX6GCR_DSEN_Msk (0x3ul << DDRPHY_DX6GCR_DSEN_Pos) /*!< DDRPHY_T::DX6GCR: DSEN Mask */ + +#define DDRPHY_DX6GCR_DQSRTT_Pos (9) /*!< DDRPHY_T::DX6GCR: DQSRTT Position */ +#define DDRPHY_DX6GCR_DQSRTT_Msk (0x1ul << DDRPHY_DX6GCR_DQSRTT_Pos) /*!< DDRPHY_T::DX6GCR: DQSRTT Mask */ + +#define DDRPHY_DX6GCR_DQRTT_Pos (10) /*!< DDRPHY_T::DX6GCR: DQRTT Position */ +#define DDRPHY_DX6GCR_DQRTT_Msk (0x1ul << DDRPHY_DX6GCR_DQRTT_Pos) /*!< DDRPHY_T::DX6GCR: DQRTT Mask */ + +#define DDRPHY_DX6GCR_RTTOH_Pos (11) /*!< DDRPHY_T::DX6GCR: RTTOH Position */ +#define DDRPHY_DX6GCR_RTTOH_Msk (0x3ul << DDRPHY_DX6GCR_RTTOH_Pos) /*!< DDRPHY_T::DX6GCR: RTTOH Mask */ + +#define DDRPHY_DX6GCR_RTTOAL_Pos (13) /*!< DDRPHY_T::DX6GCR: RTTOAL Position */ +#define DDRPHY_DX6GCR_RTTOAL_Msk (0x1ul << DDRPHY_DX6GCR_RTTOAL_Pos) /*!< DDRPHY_T::DX6GCR: RTTOAL Mask */ + +#define DDRPHY_DX6GCR_DXOEO_Pos (14) /*!< DDRPHY_T::DX6GCR: DXOEO Position */ +#define DDRPHY_DX6GCR_DXOEO_Msk (0x3ul << DDRPHY_DX6GCR_DXOEO_Pos) /*!< DDRPHY_T::DX6GCR: DXOEO Mask */ + +#define DDRPHY_DX6GCR_PLLRST_Pos (16) /*!< DDRPHY_T::DX6GCR: PLLRST Position */ +#define DDRPHY_DX6GCR_PLLRST_Msk (0x1ul << DDRPHY_DX6GCR_PLLRST_Pos) /*!< DDRPHY_T::DX6GCR: PLLRST Mask */ + +#define DDRPHY_DX6GCR_PLLPD_Pos (17) /*!< DDRPHY_T::DX6GCR: PLLPD Position */ +#define DDRPHY_DX6GCR_PLLPD_Msk (0x1ul << DDRPHY_DX6GCR_PLLPD_Pos) /*!< DDRPHY_T::DX6GCR: PLLPD Mask */ + +#define DDRPHY_DX6GCR_GSHIFT_Pos (18) /*!< DDRPHY_T::DX6GCR: GSHIFT Position */ +#define DDRPHY_DX6GCR_GSHIFT_Msk (0x1ul << DDRPHY_DX6GCR_GSHIFT_Pos) /*!< DDRPHY_T::DX6GCR: GSHIFT Mask */ + +#define DDRPHY_DX6GCR_PLLBYP_Pos (19) /*!< DDRPHY_T::DX6GCR: PLLBYP Position */ +#define DDRPHY_DX6GCR_PLLBYP_Msk (0x1ul << DDRPHY_DX6GCR_PLLBYP_Pos) /*!< DDRPHY_T::DX6GCR: PLLBYP Mask */ + +#define DDRPHY_DX6GCR_WLRKEN_Pos (26) /*!< DDRPHY_T::DX6GCR: WLRKEN Position */ +#define DDRPHY_DX6GCR_WLRKEN_Msk (0xful << DDRPHY_DX6GCR_WLRKEN_Pos) /*!< DDRPHY_T::DX6GCR: WLRKEN Mask */ + +#define DDRPHY_DX6GCR_MDLEN_Pos (30) /*!< DDRPHY_T::DX6GCR: MDLEN Position */ +#define DDRPHY_DX6GCR_MDLEN_Msk (0x1ul << DDRPHY_DX6GCR_MDLEN_Pos) /*!< DDRPHY_T::DX6GCR: MDLEN Mask */ + +#define DDRPHY_DX6GCR_CALBYP_Pos (31) /*!< DDRPHY_T::DX6GCR: CALBYP Position */ +#define DDRPHY_DX6GCR_CALBYP_Msk (0x1ul << DDRPHY_DX6GCR_CALBYP_Pos) /*!< DDRPHY_T::DX6GCR: CALBYP Mask */ + +#define DDRPHY_DX6GSR0_WDQCAL_Pos (0) /*!< DDRPHY_T::DX6GSR0: WDQCAL Position */ +#define DDRPHY_DX6GSR0_WDQCAL_Msk (0x1ul << DDRPHY_DX6GSR0_WDQCAL_Pos) /*!< DDRPHY_T::DX6GSR0: WDQCAL Mask */ + +#define DDRPHY_DX6GSR0_RDQSCAL_Pos (1) /*!< DDRPHY_T::DX6GSR0: RDQSCAL Position */ +#define DDRPHY_DX6GSR0_RDQSCAL_Msk (0x1ul << DDRPHY_DX6GSR0_RDQSCAL_Pos) /*!< DDRPHY_T::DX6GSR0: RDQSCAL Mask */ + +#define DDRPHY_DX6GSR0_RDQSNCAL_Pos (2) /*!< DDRPHY_T::DX6GSR0: RDQSNCAL Position */ +#define DDRPHY_DX6GSR0_RDQSNCAL_Msk (0x1ul << DDRPHY_DX6GSR0_RDQSNCAL_Pos) /*!< DDRPHY_T::DX6GSR0: RDQSNCAL Mask */ + +#define DDRPHY_DX6GSR0_GDQSCAL_Pos (3) /*!< DDRPHY_T::DX6GSR0: GDQSCAL Position */ +#define DDRPHY_DX6GSR0_GDQSCAL_Msk (0x1ul << DDRPHY_DX6GSR0_GDQSCAL_Pos) /*!< DDRPHY_T::DX6GSR0: GDQSCAL Mask */ + +#define DDRPHY_DX6GSR0_WLCAL_Pos (4) /*!< DDRPHY_T::DX6GSR0: WLCAL Position */ +#define DDRPHY_DX6GSR0_WLCAL_Msk (0x1ul << DDRPHY_DX6GSR0_WLCAL_Pos) /*!< DDRPHY_T::DX6GSR0: WLCAL Mask */ + +#define DDRPHY_DX6GSR0_WLDONE_Pos (5) /*!< DDRPHY_T::DX6GSR0: WLDONE Position */ +#define DDRPHY_DX6GSR0_WLDONE_Msk (0x1ul << DDRPHY_DX6GSR0_WLDONE_Pos) /*!< DDRPHY_T::DX6GSR0: WLDONE Mask */ + +#define DDRPHY_DX6GSR0_WLERR_Pos (6) /*!< DDRPHY_T::DX6GSR0: WLERR Position */ +#define DDRPHY_DX6GSR0_WLERR_Msk (0x1ul << DDRPHY_DX6GSR0_WLERR_Pos) /*!< DDRPHY_T::DX6GSR0: WLERR Mask */ + +#define DDRPHY_DX6GSR0_WLPRD_Pos (7) /*!< DDRPHY_T::DX6GSR0: WLPRD Position */ +#define DDRPHY_DX6GSR0_WLPRD_Msk (0xfful << DDRPHY_DX6GSR0_WLPRD_Pos) /*!< DDRPHY_T::DX6GSR0: WLPRD Mask */ + +#define DDRPHY_DX6GSR0_DPLOCK_Pos (15) /*!< DDRPHY_T::DX6GSR0: DPLOCK Position */ +#define DDRPHY_DX6GSR0_DPLOCK_Msk (0x1ul << DDRPHY_DX6GSR0_DPLOCK_Pos) /*!< DDRPHY_T::DX6GSR0: DPLOCK Mask */ + +#define DDRPHY_DX6GSR0_GDQSPRD_Pos (16) /*!< DDRPHY_T::DX6GSR0: GDQSPRD Position */ +#define DDRPHY_DX6GSR0_GDQSPRD_Msk (0xfful << DDRPHY_DX6GSR0_GDQSPRD_Pos) /*!< DDRPHY_T::DX6GSR0: GDQSPRD Mask */ + +#define DDRPHY_DX6GSR0_QSGERR_Pos (24) /*!< DDRPHY_T::DX6GSR0: QSGERR Position */ +#define DDRPHY_DX6GSR0_QSGERR_Msk (0xful << DDRPHY_DX6GSR0_QSGERR_Pos) /*!< DDRPHY_T::DX6GSR0: QSGERR Mask */ + +#define DDRPHY_DX6GSR0_WLDQ_Pos (28) /*!< DDRPHY_T::DX6GSR0: WLDQ Position */ +#define DDRPHY_DX6GSR0_WLDQ_Msk (0x1ul << DDRPHY_DX6GSR0_WLDQ_Pos) /*!< DDRPHY_T::DX6GSR0: WLDQ Mask */ + +#define DDRPHY_DX6GSR1_DLTDONE_Pos (0) /*!< DDRPHY_T::DX6GSR1: DLTDONE Position */ +#define DDRPHY_DX6GSR1_DLTDONE_Msk (0x1ul << DDRPHY_DX6GSR1_DLTDONE_Pos) /*!< DDRPHY_T::DX6GSR1: DLTDONE Mask */ + +#define DDRPHY_DX6GSR1_DLTCODE_Pos (1) /*!< DDRPHY_T::DX6GSR1: DLTCODE Position */ +#define DDRPHY_DX6GSR1_DLTCODE_Msk (0xfffffful << DDRPHY_DX6GSR1_DLTCODE_Pos) /*!< DDRPHY_T::DX6GSR1: DLTCODE Mask */ + +#define DDRPHY_DX6BDLR0_DQ0WBD_Pos (0) /*!< DDRPHY_T::DX6BDLR0: DQ0WBD Position */ +#define DDRPHY_DX6BDLR0_DQ0WBD_Msk (0x3ful << DDRPHY_DX6BDLR0_DQ0WBD_Pos) /*!< DDRPHY_T::DX6BDLR0: DQ0WBD Mask */ + +#define DDRPHY_DX6BDLR0_DQ1WBD_Pos (6) /*!< DDRPHY_T::DX6BDLR0: DQ1WBD Position */ +#define DDRPHY_DX6BDLR0_DQ1WBD_Msk (0x3ful << DDRPHY_DX6BDLR0_DQ1WBD_Pos) /*!< DDRPHY_T::DX6BDLR0: DQ1WBD Mask */ + +#define DDRPHY_DX6BDLR0_DQ2WBD_Pos (12) /*!< DDRPHY_T::DX6BDLR0: DQ2WBD Position */ +#define DDRPHY_DX6BDLR0_DQ2WBD_Msk (0x3ful << DDRPHY_DX6BDLR0_DQ2WBD_Pos) /*!< DDRPHY_T::DX6BDLR0: DQ2WBD Mask */ + +#define DDRPHY_DX6BDLR0_DQ3WBD_Pos (18) /*!< DDRPHY_T::DX6BDLR0: DQ3WBD Position */ +#define DDRPHY_DX6BDLR0_DQ3WBD_Msk (0x3ful << DDRPHY_DX6BDLR0_DQ3WBD_Pos) /*!< DDRPHY_T::DX6BDLR0: DQ3WBD Mask */ + +#define DDRPHY_DX6BDLR0_DQ4WBD_Pos (24) /*!< DDRPHY_T::DX6BDLR0: DQ4WBD Position */ +#define DDRPHY_DX6BDLR0_DQ4WBD_Msk (0x3ful << DDRPHY_DX6BDLR0_DQ4WBD_Pos) /*!< DDRPHY_T::DX6BDLR0: DQ4WBD Mask */ + +#define DDRPHY_DX6BDLR1_DQ5WBD_Pos (0) /*!< DDRPHY_T::DX6BDLR1: DQ5WBD Position */ +#define DDRPHY_DX6BDLR1_DQ5WBD_Msk (0x3ful << DDRPHY_DX6BDLR1_DQ5WBD_Pos) /*!< DDRPHY_T::DX6BDLR1: DQ5WBD Mask */ + +#define DDRPHY_DX6BDLR1_DQ6WBD_Pos (6) /*!< DDRPHY_T::DX6BDLR1: DQ6WBD Position */ +#define DDRPHY_DX6BDLR1_DQ6WBD_Msk (0x3ful << DDRPHY_DX6BDLR1_DQ6WBD_Pos) /*!< DDRPHY_T::DX6BDLR1: DQ6WBD Mask */ + +#define DDRPHY_DX6BDLR1_DQ7WBD_Pos (12) /*!< DDRPHY_T::DX6BDLR1: DQ7WBD Position */ +#define DDRPHY_DX6BDLR1_DQ7WBD_Msk (0x3ful << DDRPHY_DX6BDLR1_DQ7WBD_Pos) /*!< DDRPHY_T::DX6BDLR1: DQ7WBD Mask */ + +#define DDRPHY_DX6BDLR1_DMWBD_Pos (18) /*!< DDRPHY_T::DX6BDLR1: DMWBD Position */ +#define DDRPHY_DX6BDLR1_DMWBD_Msk (0x3ful << DDRPHY_DX6BDLR1_DMWBD_Pos) /*!< DDRPHY_T::DX6BDLR1: DMWBD Mask */ + +#define DDRPHY_DX6BDLR1_DSWBD_Pos (24) /*!< DDRPHY_T::DX6BDLR1: DSWBD Position */ +#define DDRPHY_DX6BDLR1_DSWBD_Msk (0x3ful << DDRPHY_DX6BDLR1_DSWBD_Pos) /*!< DDRPHY_T::DX6BDLR1: DSWBD Mask */ + +#define DDRPHY_DX6BDLR2_DSOEBD_Pos (0) /*!< DDRPHY_T::DX6BDLR2: DSOEBD Position */ +#define DDRPHY_DX6BDLR2_DSOEBD_Msk (0x3ful << DDRPHY_DX6BDLR2_DSOEBD_Pos) /*!< DDRPHY_T::DX6BDLR2: DSOEBD Mask */ + +#define DDRPHY_DX6BDLR2_DQOEBD_Pos (6) /*!< DDRPHY_T::DX6BDLR2: DQOEBD Position */ +#define DDRPHY_DX6BDLR2_DQOEBD_Msk (0x3ful << DDRPHY_DX6BDLR2_DQOEBD_Pos) /*!< DDRPHY_T::DX6BDLR2: DQOEBD Mask */ + +#define DDRPHY_DX6BDLR2_DSRBD_Pos (12) /*!< DDRPHY_T::DX6BDLR2: DSRBD Position */ +#define DDRPHY_DX6BDLR2_DSRBD_Msk (0x3ful << DDRPHY_DX6BDLR2_DSRBD_Pos) /*!< DDRPHY_T::DX6BDLR2: DSRBD Mask */ + +#define DDRPHY_DX6BDLR2_DSNRBD_Pos (18) /*!< DDRPHY_T::DX6BDLR2: DSNRBD Position */ +#define DDRPHY_DX6BDLR2_DSNRBD_Msk (0x3ful << DDRPHY_DX6BDLR2_DSNRBD_Pos) /*!< DDRPHY_T::DX6BDLR2: DSNRBD Mask */ + +#define DDRPHY_DX6BDLR3_DQ0RBD_Pos (0) /*!< DDRPHY_T::DX6BDLR3: DQ0RBD Position */ +#define DDRPHY_DX6BDLR3_DQ0RBD_Msk (0x3ful << DDRPHY_DX6BDLR3_DQ0RBD_Pos) /*!< DDRPHY_T::DX6BDLR3: DQ0RBD Mask */ + +#define DDRPHY_DX6BDLR3_DQ1RBD_Pos (6) /*!< DDRPHY_T::DX6BDLR3: DQ1RBD Position */ +#define DDRPHY_DX6BDLR3_DQ1RBD_Msk (0x3ful << DDRPHY_DX6BDLR3_DQ1RBD_Pos) /*!< DDRPHY_T::DX6BDLR3: DQ1RBD Mask */ + +#define DDRPHY_DX6BDLR3_DQ2RBD_Pos (12) /*!< DDRPHY_T::DX6BDLR3: DQ2RBD Position */ +#define DDRPHY_DX6BDLR3_DQ2RBD_Msk (0x3ful << DDRPHY_DX6BDLR3_DQ2RBD_Pos) /*!< DDRPHY_T::DX6BDLR3: DQ2RBD Mask */ + +#define DDRPHY_DX6BDLR3_DQ3RBD_Pos (18) /*!< DDRPHY_T::DX6BDLR3: DQ3RBD Position */ +#define DDRPHY_DX6BDLR3_DQ3RBD_Msk (0x3ful << DDRPHY_DX6BDLR3_DQ3RBD_Pos) /*!< DDRPHY_T::DX6BDLR3: DQ3RBD Mask */ + +#define DDRPHY_DX6BDLR3_DQ4RBD_Pos (24) /*!< DDRPHY_T::DX6BDLR3: DQ4RBD Position */ +#define DDRPHY_DX6BDLR3_DQ4RBD_Msk (0x3ful << DDRPHY_DX6BDLR3_DQ4RBD_Pos) /*!< DDRPHY_T::DX6BDLR3: DQ4RBD Mask */ + +#define DDRPHY_DX6BDLR4_DQ5RBD_Pos (0) /*!< DDRPHY_T::DX6BDLR4: DQ5RBD Position */ +#define DDRPHY_DX6BDLR4_DQ5RBD_Msk (0x3ful << DDRPHY_DX6BDLR4_DQ5RBD_Pos) /*!< DDRPHY_T::DX6BDLR4: DQ5RBD Mask */ + +#define DDRPHY_DX6BDLR4_DQ6RBD_Pos (6) /*!< DDRPHY_T::DX6BDLR4: DQ6RBD Position */ +#define DDRPHY_DX6BDLR4_DQ6RBD_Msk (0x3ful << DDRPHY_DX6BDLR4_DQ6RBD_Pos) /*!< DDRPHY_T::DX6BDLR4: DQ6RBD Mask */ + +#define DDRPHY_DX6BDLR4_DQ7RBD_Pos (12) /*!< DDRPHY_T::DX6BDLR4: DQ7RBD Position */ +#define DDRPHY_DX6BDLR4_DQ7RBD_Msk (0x3ful << DDRPHY_DX6BDLR4_DQ7RBD_Pos) /*!< DDRPHY_T::DX6BDLR4: DQ7RBD Mask */ + +#define DDRPHY_DX6BDLR4_DMRBD_Pos (18) /*!< DDRPHY_T::DX6BDLR4: DMRBD Position */ +#define DDRPHY_DX6BDLR4_DMRBD_Msk (0x3ful << DDRPHY_DX6BDLR4_DMRBD_Pos) /*!< DDRPHY_T::DX6BDLR4: DMRBD Mask */ + +#define DDRPHY_DX6LCDLR0_R0WLD_Pos (0) /*!< DDRPHY_T::DX6LCDLR0: R0WLD Position */ +#define DDRPHY_DX6LCDLR0_R0WLD_Msk (0xfful << DDRPHY_DX6LCDLR0_R0WLD_Pos) /*!< DDRPHY_T::DX6LCDLR0: R0WLD Mask */ + +#define DDRPHY_DX6LCDLR0_R1WLD_Pos (8) /*!< DDRPHY_T::DX6LCDLR0: R1WLD Position */ +#define DDRPHY_DX6LCDLR0_R1WLD_Msk (0xfful << DDRPHY_DX6LCDLR0_R1WLD_Pos) /*!< DDRPHY_T::DX6LCDLR0: R1WLD Mask */ + +#define DDRPHY_DX6LCDLR0_R2WLD_Pos (16) /*!< DDRPHY_T::DX6LCDLR0: R2WLD Position */ +#define DDRPHY_DX6LCDLR0_R2WLD_Msk (0xfful << DDRPHY_DX6LCDLR0_R2WLD_Pos) /*!< DDRPHY_T::DX6LCDLR0: R2WLD Mask */ + +#define DDRPHY_DX6LCDLR0_R3WLD_Pos (24) /*!< DDRPHY_T::DX6LCDLR0: R3WLD Position */ +#define DDRPHY_DX6LCDLR0_R3WLD_Msk (0xfful << DDRPHY_DX6LCDLR0_R3WLD_Pos) /*!< DDRPHY_T::DX6LCDLR0: R3WLD Mask */ + +#define DDRPHY_DX6LCDLR2_R0DQSGD_Pos (0) /*!< DDRPHY_T::DX6LCDLR2: R0DQSGD Position */ +#define DDRPHY_DX6LCDLR2_R0DQSGD_Msk (0xfful << DDRPHY_DX6LCDLR2_R0DQSGD_Pos) /*!< DDRPHY_T::DX6LCDLR2: R0DQSGD Mask */ + +#define DDRPHY_DX6LCDLR2_R1DQSGD_Pos (8) /*!< DDRPHY_T::DX6LCDLR2: R1DQSGD Position */ +#define DDRPHY_DX6LCDLR2_R1DQSGD_Msk (0xfful << DDRPHY_DX6LCDLR2_R1DQSGD_Pos) /*!< DDRPHY_T::DX6LCDLR2: R1DQSGD Mask */ + +#define DDRPHY_DX6LCDLR2_R2DQSGD_Pos (16) /*!< DDRPHY_T::DX6LCDLR2: R2DQSGD Position */ +#define DDRPHY_DX6LCDLR2_R2DQSGD_Msk (0xfful << DDRPHY_DX6LCDLR2_R2DQSGD_Pos) /*!< DDRPHY_T::DX6LCDLR2: R2DQSGD Mask */ + +#define DDRPHY_DX6LCDLR2_R3DQSGD_Pos (24) /*!< DDRPHY_T::DX6LCDLR2: R3DQSGD Position */ +#define DDRPHY_DX6LCDLR2_R3DQSGD_Msk (0xfful << DDRPHY_DX6LCDLR2_R3DQSGD_Pos) /*!< DDRPHY_T::DX6LCDLR2: R3DQSGD Mask */ + +#define DDRPHY_DX6MDLR_IPRD_Pos (0) /*!< DDRPHY_T::DX6MDLR: IPRD Position */ +#define DDRPHY_DX6MDLR_IPRD_Msk (0xfful << DDRPHY_DX6MDLR_IPRD_Pos) /*!< DDRPHY_T::DX6MDLR: IPRD Mask */ + +#define DDRPHY_DX6MDLR_TPRD_Pos (8) /*!< DDRPHY_T::DX6MDLR: TPRD Position */ +#define DDRPHY_DX6MDLR_TPRD_Msk (0xfful << DDRPHY_DX6MDLR_TPRD_Pos) /*!< DDRPHY_T::DX6MDLR: TPRD Mask */ + +#define DDRPHY_DX6MDLR_MDLD_Pos (16) /*!< DDRPHY_T::DX6MDLR: MDLD Position */ +#define DDRPHY_DX6MDLR_MDLD_Msk (0xfful << DDRPHY_DX6MDLR_MDLD_Pos) /*!< DDRPHY_T::DX6MDLR: MDLD Mask */ + +#define DDRPHY_DX6GTR_R0DGSL_Pos (0) /*!< DDRPHY_T::DX6GTR: R0DGSL Position */ +#define DDRPHY_DX6GTR_R0DGSL_Msk (0x7ul << DDRPHY_DX6GTR_R0DGSL_Pos) /*!< DDRPHY_T::DX6GTR: R0DGSL Mask */ + +#define DDRPHY_DX6GTR_R1DGSL_Pos (3) /*!< DDRPHY_T::DX6GTR: R1DGSL Position */ +#define DDRPHY_DX6GTR_R1DGSL_Msk (0x7ul << DDRPHY_DX6GTR_R1DGSL_Pos) /*!< DDRPHY_T::DX6GTR: R1DGSL Mask */ + +#define DDRPHY_DX6GTR_R2DGSL_Pos (6) /*!< DDRPHY_T::DX6GTR: R2DGSL Position */ +#define DDRPHY_DX6GTR_R2DGSL_Msk (0x7ul << DDRPHY_DX6GTR_R2DGSL_Pos) /*!< DDRPHY_T::DX6GTR: R2DGSL Mask */ + +#define DDRPHY_DX6GTR_R3DGSL_Pos (9) /*!< DDRPHY_T::DX6GTR: R3DGSL Position */ +#define DDRPHY_DX6GTR_R3DGSL_Msk (0x7ul << DDRPHY_DX6GTR_R3DGSL_Pos) /*!< DDRPHY_T::DX6GTR: R3DGSL Mask */ + +#define DDRPHY_DX6GTR_R0WLSL_Pos (12) /*!< DDRPHY_T::DX6GTR: R0WLSL Position */ +#define DDRPHY_DX6GTR_R0WLSL_Msk (0x3ul << DDRPHY_DX6GTR_R0WLSL_Pos) /*!< DDRPHY_T::DX6GTR: R0WLSL Mask */ + +#define DDRPHY_DX6GTR_R1WLSL_Pos (14) /*!< DDRPHY_T::DX6GTR: R1WLSL Position */ +#define DDRPHY_DX6GTR_R1WLSL_Msk (0x3ul << DDRPHY_DX6GTR_R1WLSL_Pos) /*!< DDRPHY_T::DX6GTR: R1WLSL Mask */ + +#define DDRPHY_DX6GTR_R2WLSL_Pos (16) /*!< DDRPHY_T::DX6GTR: R2WLSL Position */ +#define DDRPHY_DX6GTR_R2WLSL_Msk (0x3ul << DDRPHY_DX6GTR_R2WLSL_Pos) /*!< DDRPHY_T::DX6GTR: R2WLSL Mask */ + +#define DDRPHY_DX6GTR_R3WLSL_Pos (18) /*!< DDRPHY_T::DX6GTR: R3WLSL Position */ +#define DDRPHY_DX6GTR_R3WLSL_Msk (0x3ul << DDRPHY_DX6GTR_R3WLSL_Pos) /*!< DDRPHY_T::DX6GTR: R3WLSL Mask */ + +#define DDRPHY_DX6GSR2_RDERR_Pos (0) /*!< DDRPHY_T::DX6GSR2: RDERR Position */ +#define DDRPHY_DX6GSR2_RDERR_Msk (0x1ul << DDRPHY_DX6GSR2_RDERR_Pos) /*!< DDRPHY_T::DX6GSR2: RDERR Mask */ + +#define DDRPHY_DX6GSR2_RDWN_Pos (1) /*!< DDRPHY_T::DX6GSR2: RDWN Position */ +#define DDRPHY_DX6GSR2_RDWN_Msk (0x1ul << DDRPHY_DX6GSR2_RDWN_Pos) /*!< DDRPHY_T::DX6GSR2: RDWN Mask */ + +#define DDRPHY_DX6GSR2_WDERR_Pos (2) /*!< DDRPHY_T::DX6GSR2: WDERR Position */ +#define DDRPHY_DX6GSR2_WDERR_Msk (0x1ul << DDRPHY_DX6GSR2_WDERR_Pos) /*!< DDRPHY_T::DX6GSR2: WDERR Mask */ + +#define DDRPHY_DX6GSR2_WDWN_Pos (3) /*!< DDRPHY_T::DX6GSR2: WDWN Position */ +#define DDRPHY_DX6GSR2_WDWN_Msk (0x1ul << DDRPHY_DX6GSR2_WDWN_Pos) /*!< DDRPHY_T::DX6GSR2: WDWN Mask */ + +#define DDRPHY_DX6GSR2_REERR_Pos (4) /*!< DDRPHY_T::DX6GSR2: REERR Position */ +#define DDRPHY_DX6GSR2_REERR_Msk (0x1ul << DDRPHY_DX6GSR2_REERR_Pos) /*!< DDRPHY_T::DX6GSR2: REERR Mask */ + +#define DDRPHY_DX6GSR2_REWN_Pos (5) /*!< DDRPHY_T::DX6GSR2: REWN Position */ +#define DDRPHY_DX6GSR2_REWN_Msk (0x1ul << DDRPHY_DX6GSR2_REWN_Pos) /*!< DDRPHY_T::DX6GSR2: REWN Mask */ + +#define DDRPHY_DX6GSR2_WEERR_Pos (6) /*!< DDRPHY_T::DX6GSR2: WEERR Position */ +#define DDRPHY_DX6GSR2_WEERR_Msk (0x1ul << DDRPHY_DX6GSR2_WEERR_Pos) /*!< DDRPHY_T::DX6GSR2: WEERR Mask */ + +#define DDRPHY_DX6GSR2_WEWN_Pos (7) /*!< DDRPHY_T::DX6GSR2: WEWN Position */ +#define DDRPHY_DX6GSR2_WEWN_Msk (0x1ul << DDRPHY_DX6GSR2_WEWN_Pos) /*!< DDRPHY_T::DX6GSR2: WEWN Mask */ + +#define DDRPHY_DX6GSR2_ESTAT_Pos (8) /*!< DDRPHY_T::DX6GSR2: ESTAT Position */ +#define DDRPHY_DX6GSR2_ESTAT_Msk (0xful << DDRPHY_DX6GSR2_ESTAT_Pos) /*!< DDRPHY_T::DX6GSR2: ESTAT Mask */ + +#define DDRPHY_DX7GCR_DXEN_Pos (0) /*!< DDRPHY_T::DX7GCR: DXEN Position */ +#define DDRPHY_DX7GCR_DXEN_Msk (0x1ul << DDRPHY_DX7GCR_DXEN_Pos) /*!< DDRPHY_T::DX7GCR: DXEN Mask */ + +#define DDRPHY_DX7GCR_DQSODT_Pos (1) /*!< DDRPHY_T::DX7GCR: DQSODT Position */ +#define DDRPHY_DX7GCR_DQSODT_Msk (0x1ul << DDRPHY_DX7GCR_DQSODT_Pos) /*!< DDRPHY_T::DX7GCR: DQSODT Mask */ + +#define DDRPHY_DX7GCR_DQODT_Pos (2) /*!< DDRPHY_T::DX7GCR: DQODT Position */ +#define DDRPHY_DX7GCR_DQODT_Msk (0x1ul << DDRPHY_DX7GCR_DQODT_Pos) /*!< DDRPHY_T::DX7GCR: DQODT Mask */ + +#define DDRPHY_DX7GCR_DXIOM_Pos (3) /*!< DDRPHY_T::DX7GCR: DXIOM Position */ +#define DDRPHY_DX7GCR_DXIOM_Msk (0x1ul << DDRPHY_DX7GCR_DXIOM_Pos) /*!< DDRPHY_T::DX7GCR: DXIOM Mask */ + +#define DDRPHY_DX7GCR_DXPDD_Pos (4) /*!< DDRPHY_T::DX7GCR: DXPDD Position */ +#define DDRPHY_DX7GCR_DXPDD_Msk (0x1ul << DDRPHY_DX7GCR_DXPDD_Pos) /*!< DDRPHY_T::DX7GCR: DXPDD Mask */ + +#define DDRPHY_DX7GCR_DXPDR_Pos (5) /*!< DDRPHY_T::DX7GCR: DXPDR Position */ +#define DDRPHY_DX7GCR_DXPDR_Msk (0x1ul << DDRPHY_DX7GCR_DXPDR_Pos) /*!< DDRPHY_T::DX7GCR: DXPDR Mask */ + +#define DDRPHY_DX7GCR_DQSRPD_Pos (6) /*!< DDRPHY_T::DX7GCR: DQSRPD Position */ +#define DDRPHY_DX7GCR_DQSRPD_Msk (0x1ul << DDRPHY_DX7GCR_DQSRPD_Pos) /*!< DDRPHY_T::DX7GCR: DQSRPD Mask */ + +#define DDRPHY_DX7GCR_DSEN_Pos (7) /*!< DDRPHY_T::DX7GCR: DSEN Position */ +#define DDRPHY_DX7GCR_DSEN_Msk (0x3ul << DDRPHY_DX7GCR_DSEN_Pos) /*!< DDRPHY_T::DX7GCR: DSEN Mask */ + +#define DDRPHY_DX7GCR_DQSRTT_Pos (9) /*!< DDRPHY_T::DX7GCR: DQSRTT Position */ +#define DDRPHY_DX7GCR_DQSRTT_Msk (0x1ul << DDRPHY_DX7GCR_DQSRTT_Pos) /*!< DDRPHY_T::DX7GCR: DQSRTT Mask */ + +#define DDRPHY_DX7GCR_DQRTT_Pos (10) /*!< DDRPHY_T::DX7GCR: DQRTT Position */ +#define DDRPHY_DX7GCR_DQRTT_Msk (0x1ul << DDRPHY_DX7GCR_DQRTT_Pos) /*!< DDRPHY_T::DX7GCR: DQRTT Mask */ + +#define DDRPHY_DX7GCR_RTTOH_Pos (11) /*!< DDRPHY_T::DX7GCR: RTTOH Position */ +#define DDRPHY_DX7GCR_RTTOH_Msk (0x3ul << DDRPHY_DX7GCR_RTTOH_Pos) /*!< DDRPHY_T::DX7GCR: RTTOH Mask */ + +#define DDRPHY_DX7GCR_RTTOAL_Pos (13) /*!< DDRPHY_T::DX7GCR: RTTOAL Position */ +#define DDRPHY_DX7GCR_RTTOAL_Msk (0x1ul << DDRPHY_DX7GCR_RTTOAL_Pos) /*!< DDRPHY_T::DX7GCR: RTTOAL Mask */ + +#define DDRPHY_DX7GCR_DXOEO_Pos (14) /*!< DDRPHY_T::DX7GCR: DXOEO Position */ +#define DDRPHY_DX7GCR_DXOEO_Msk (0x3ul << DDRPHY_DX7GCR_DXOEO_Pos) /*!< DDRPHY_T::DX7GCR: DXOEO Mask */ + +#define DDRPHY_DX7GCR_PLLRST_Pos (16) /*!< DDRPHY_T::DX7GCR: PLLRST Position */ +#define DDRPHY_DX7GCR_PLLRST_Msk (0x1ul << DDRPHY_DX7GCR_PLLRST_Pos) /*!< DDRPHY_T::DX7GCR: PLLRST Mask */ + +#define DDRPHY_DX7GCR_PLLPD_Pos (17) /*!< DDRPHY_T::DX7GCR: PLLPD Position */ +#define DDRPHY_DX7GCR_PLLPD_Msk (0x1ul << DDRPHY_DX7GCR_PLLPD_Pos) /*!< DDRPHY_T::DX7GCR: PLLPD Mask */ + +#define DDRPHY_DX7GCR_GSHIFT_Pos (18) /*!< DDRPHY_T::DX7GCR: GSHIFT Position */ +#define DDRPHY_DX7GCR_GSHIFT_Msk (0x1ul << DDRPHY_DX7GCR_GSHIFT_Pos) /*!< DDRPHY_T::DX7GCR: GSHIFT Mask */ + +#define DDRPHY_DX7GCR_PLLBYP_Pos (19) /*!< DDRPHY_T::DX7GCR: PLLBYP Position */ +#define DDRPHY_DX7GCR_PLLBYP_Msk (0x1ul << DDRPHY_DX7GCR_PLLBYP_Pos) /*!< DDRPHY_T::DX7GCR: PLLBYP Mask */ + +#define DDRPHY_DX7GCR_WLRKEN_Pos (26) /*!< DDRPHY_T::DX7GCR: WLRKEN Position */ +#define DDRPHY_DX7GCR_WLRKEN_Msk (0xful << DDRPHY_DX7GCR_WLRKEN_Pos) /*!< DDRPHY_T::DX7GCR: WLRKEN Mask */ + +#define DDRPHY_DX7GCR_MDLEN_Pos (30) /*!< DDRPHY_T::DX7GCR: MDLEN Position */ +#define DDRPHY_DX7GCR_MDLEN_Msk (0x1ul << DDRPHY_DX7GCR_MDLEN_Pos) /*!< DDRPHY_T::DX7GCR: MDLEN Mask */ + +#define DDRPHY_DX7GCR_CALBYP_Pos (31) /*!< DDRPHY_T::DX7GCR: CALBYP Position */ +#define DDRPHY_DX7GCR_CALBYP_Msk (0x1ul << DDRPHY_DX7GCR_CALBYP_Pos) /*!< DDRPHY_T::DX7GCR: CALBYP Mask */ + +#define DDRPHY_DX7GSR0_WDQCAL_Pos (0) /*!< DDRPHY_T::DX7GSR0: WDQCAL Position */ +#define DDRPHY_DX7GSR0_WDQCAL_Msk (0x1ul << DDRPHY_DX7GSR0_WDQCAL_Pos) /*!< DDRPHY_T::DX7GSR0: WDQCAL Mask */ + +#define DDRPHY_DX7GSR0_RDQSCAL_Pos (1) /*!< DDRPHY_T::DX7GSR0: RDQSCAL Position */ +#define DDRPHY_DX7GSR0_RDQSCAL_Msk (0x1ul << DDRPHY_DX7GSR0_RDQSCAL_Pos) /*!< DDRPHY_T::DX7GSR0: RDQSCAL Mask */ + +#define DDRPHY_DX7GSR0_RDQSNCAL_Pos (2) /*!< DDRPHY_T::DX7GSR0: RDQSNCAL Position */ +#define DDRPHY_DX7GSR0_RDQSNCAL_Msk (0x1ul << DDRPHY_DX7GSR0_RDQSNCAL_Pos) /*!< DDRPHY_T::DX7GSR0: RDQSNCAL Mask */ + +#define DDRPHY_DX7GSR0_GDQSCAL_Pos (3) /*!< DDRPHY_T::DX7GSR0: GDQSCAL Position */ +#define DDRPHY_DX7GSR0_GDQSCAL_Msk (0x1ul << DDRPHY_DX7GSR0_GDQSCAL_Pos) /*!< DDRPHY_T::DX7GSR0: GDQSCAL Mask */ + +#define DDRPHY_DX7GSR0_WLCAL_Pos (4) /*!< DDRPHY_T::DX7GSR0: WLCAL Position */ +#define DDRPHY_DX7GSR0_WLCAL_Msk (0x1ul << DDRPHY_DX7GSR0_WLCAL_Pos) /*!< DDRPHY_T::DX7GSR0: WLCAL Mask */ + +#define DDRPHY_DX7GSR0_WLDONE_Pos (5) /*!< DDRPHY_T::DX7GSR0: WLDONE Position */ +#define DDRPHY_DX7GSR0_WLDONE_Msk (0x1ul << DDRPHY_DX7GSR0_WLDONE_Pos) /*!< DDRPHY_T::DX7GSR0: WLDONE Mask */ + +#define DDRPHY_DX7GSR0_WLERR_Pos (6) /*!< DDRPHY_T::DX7GSR0: WLERR Position */ +#define DDRPHY_DX7GSR0_WLERR_Msk (0x1ul << DDRPHY_DX7GSR0_WLERR_Pos) /*!< DDRPHY_T::DX7GSR0: WLERR Mask */ + +#define DDRPHY_DX7GSR0_WLPRD_Pos (7) /*!< DDRPHY_T::DX7GSR0: WLPRD Position */ +#define DDRPHY_DX7GSR0_WLPRD_Msk (0xfful << DDRPHY_DX7GSR0_WLPRD_Pos) /*!< DDRPHY_T::DX7GSR0: WLPRD Mask */ + +#define DDRPHY_DX7GSR0_DPLOCK_Pos (15) /*!< DDRPHY_T::DX7GSR0: DPLOCK Position */ +#define DDRPHY_DX7GSR0_DPLOCK_Msk (0x1ul << DDRPHY_DX7GSR0_DPLOCK_Pos) /*!< DDRPHY_T::DX7GSR0: DPLOCK Mask */ + +#define DDRPHY_DX7GSR0_GDQSPRD_Pos (16) /*!< DDRPHY_T::DX7GSR0: GDQSPRD Position */ +#define DDRPHY_DX7GSR0_GDQSPRD_Msk (0xfful << DDRPHY_DX7GSR0_GDQSPRD_Pos) /*!< DDRPHY_T::DX7GSR0: GDQSPRD Mask */ + +#define DDRPHY_DX7GSR0_QSGERR_Pos (24) /*!< DDRPHY_T::DX7GSR0: QSGERR Position */ +#define DDRPHY_DX7GSR0_QSGERR_Msk (0xful << DDRPHY_DX7GSR0_QSGERR_Pos) /*!< DDRPHY_T::DX7GSR0: QSGERR Mask */ + +#define DDRPHY_DX7GSR0_WLDQ_Pos (28) /*!< DDRPHY_T::DX7GSR0: WLDQ Position */ +#define DDRPHY_DX7GSR0_WLDQ_Msk (0x1ul << DDRPHY_DX7GSR0_WLDQ_Pos) /*!< DDRPHY_T::DX7GSR0: WLDQ Mask */ + +#define DDRPHY_DX7GSR1_DLTDONE_Pos (0) /*!< DDRPHY_T::DX7GSR1: DLTDONE Position */ +#define DDRPHY_DX7GSR1_DLTDONE_Msk (0x1ul << DDRPHY_DX7GSR1_DLTDONE_Pos) /*!< DDRPHY_T::DX7GSR1: DLTDONE Mask */ + +#define DDRPHY_DX7GSR1_DLTCODE_Pos (1) /*!< DDRPHY_T::DX7GSR1: DLTCODE Position */ +#define DDRPHY_DX7GSR1_DLTCODE_Msk (0xfffffful << DDRPHY_DX7GSR1_DLTCODE_Pos) /*!< DDRPHY_T::DX7GSR1: DLTCODE Mask */ + +#define DDRPHY_DX7BDLR0_DQ0WBD_Pos (0) /*!< DDRPHY_T::DX7BDLR0: DQ0WBD Position */ +#define DDRPHY_DX7BDLR0_DQ0WBD_Msk (0x3ful << DDRPHY_DX7BDLR0_DQ0WBD_Pos) /*!< DDRPHY_T::DX7BDLR0: DQ0WBD Mask */ + +#define DDRPHY_DX7BDLR0_DQ1WBD_Pos (6) /*!< DDRPHY_T::DX7BDLR0: DQ1WBD Position */ +#define DDRPHY_DX7BDLR0_DQ1WBD_Msk (0x3ful << DDRPHY_DX7BDLR0_DQ1WBD_Pos) /*!< DDRPHY_T::DX7BDLR0: DQ1WBD Mask */ + +#define DDRPHY_DX7BDLR0_DQ2WBD_Pos (12) /*!< DDRPHY_T::DX7BDLR0: DQ2WBD Position */ +#define DDRPHY_DX7BDLR0_DQ2WBD_Msk (0x3ful << DDRPHY_DX7BDLR0_DQ2WBD_Pos) /*!< DDRPHY_T::DX7BDLR0: DQ2WBD Mask */ + +#define DDRPHY_DX7BDLR0_DQ3WBD_Pos (18) /*!< DDRPHY_T::DX7BDLR0: DQ3WBD Position */ +#define DDRPHY_DX7BDLR0_DQ3WBD_Msk (0x3ful << DDRPHY_DX7BDLR0_DQ3WBD_Pos) /*!< DDRPHY_T::DX7BDLR0: DQ3WBD Mask */ + +#define DDRPHY_DX7BDLR0_DQ4WBD_Pos (24) /*!< DDRPHY_T::DX7BDLR0: DQ4WBD Position */ +#define DDRPHY_DX7BDLR0_DQ4WBD_Msk (0x3ful << DDRPHY_DX7BDLR0_DQ4WBD_Pos) /*!< DDRPHY_T::DX7BDLR0: DQ4WBD Mask */ + +#define DDRPHY_DX7BDLR1_DQ5WBD_Pos (0) /*!< DDRPHY_T::DX7BDLR1: DQ5WBD Position */ +#define DDRPHY_DX7BDLR1_DQ5WBD_Msk (0x3ful << DDRPHY_DX7BDLR1_DQ5WBD_Pos) /*!< DDRPHY_T::DX7BDLR1: DQ5WBD Mask */ + +#define DDRPHY_DX7BDLR1_DQ6WBD_Pos (6) /*!< DDRPHY_T::DX7BDLR1: DQ6WBD Position */ +#define DDRPHY_DX7BDLR1_DQ6WBD_Msk (0x3ful << DDRPHY_DX7BDLR1_DQ6WBD_Pos) /*!< DDRPHY_T::DX7BDLR1: DQ6WBD Mask */ + +#define DDRPHY_DX7BDLR1_DQ7WBD_Pos (12) /*!< DDRPHY_T::DX7BDLR1: DQ7WBD Position */ +#define DDRPHY_DX7BDLR1_DQ7WBD_Msk (0x3ful << DDRPHY_DX7BDLR1_DQ7WBD_Pos) /*!< DDRPHY_T::DX7BDLR1: DQ7WBD Mask */ + +#define DDRPHY_DX7BDLR1_DMWBD_Pos (18) /*!< DDRPHY_T::DX7BDLR1: DMWBD Position */ +#define DDRPHY_DX7BDLR1_DMWBD_Msk (0x3ful << DDRPHY_DX7BDLR1_DMWBD_Pos) /*!< DDRPHY_T::DX7BDLR1: DMWBD Mask */ + +#define DDRPHY_DX7BDLR1_DSWBD_Pos (24) /*!< DDRPHY_T::DX7BDLR1: DSWBD Position */ +#define DDRPHY_DX7BDLR1_DSWBD_Msk (0x3ful << DDRPHY_DX7BDLR1_DSWBD_Pos) /*!< DDRPHY_T::DX7BDLR1: DSWBD Mask */ + +#define DDRPHY_DX7BDLR2_DSOEBD_Pos (0) /*!< DDRPHY_T::DX7BDLR2: DSOEBD Position */ +#define DDRPHY_DX7BDLR2_DSOEBD_Msk (0x3ful << DDRPHY_DX7BDLR2_DSOEBD_Pos) /*!< DDRPHY_T::DX7BDLR2: DSOEBD Mask */ + +#define DDRPHY_DX7BDLR2_DQOEBD_Pos (6) /*!< DDRPHY_T::DX7BDLR2: DQOEBD Position */ +#define DDRPHY_DX7BDLR2_DQOEBD_Msk (0x3ful << DDRPHY_DX7BDLR2_DQOEBD_Pos) /*!< DDRPHY_T::DX7BDLR2: DQOEBD Mask */ + +#define DDRPHY_DX7BDLR2_DSRBD_Pos (12) /*!< DDRPHY_T::DX7BDLR2: DSRBD Position */ +#define DDRPHY_DX7BDLR2_DSRBD_Msk (0x3ful << DDRPHY_DX7BDLR2_DSRBD_Pos) /*!< DDRPHY_T::DX7BDLR2: DSRBD Mask */ + +#define DDRPHY_DX7BDLR2_DSNRBD_Pos (18) /*!< DDRPHY_T::DX7BDLR2: DSNRBD Position */ +#define DDRPHY_DX7BDLR2_DSNRBD_Msk (0x3ful << DDRPHY_DX7BDLR2_DSNRBD_Pos) /*!< DDRPHY_T::DX7BDLR2: DSNRBD Mask */ + +#define DDRPHY_DX7BDLR3_DQ0RBD_Pos (0) /*!< DDRPHY_T::DX7BDLR3: DQ0RBD Position */ +#define DDRPHY_DX7BDLR3_DQ0RBD_Msk (0x3ful << DDRPHY_DX7BDLR3_DQ0RBD_Pos) /*!< DDRPHY_T::DX7BDLR3: DQ0RBD Mask */ + +#define DDRPHY_DX7BDLR3_DQ1RBD_Pos (6) /*!< DDRPHY_T::DX7BDLR3: DQ1RBD Position */ +#define DDRPHY_DX7BDLR3_DQ1RBD_Msk (0x3ful << DDRPHY_DX7BDLR3_DQ1RBD_Pos) /*!< DDRPHY_T::DX7BDLR3: DQ1RBD Mask */ + +#define DDRPHY_DX7BDLR3_DQ2RBD_Pos (12) /*!< DDRPHY_T::DX7BDLR3: DQ2RBD Position */ +#define DDRPHY_DX7BDLR3_DQ2RBD_Msk (0x3ful << DDRPHY_DX7BDLR3_DQ2RBD_Pos) /*!< DDRPHY_T::DX7BDLR3: DQ2RBD Mask */ + +#define DDRPHY_DX7BDLR3_DQ3RBD_Pos (18) /*!< DDRPHY_T::DX7BDLR3: DQ3RBD Position */ +#define DDRPHY_DX7BDLR3_DQ3RBD_Msk (0x3ful << DDRPHY_DX7BDLR3_DQ3RBD_Pos) /*!< DDRPHY_T::DX7BDLR3: DQ3RBD Mask */ + +#define DDRPHY_DX7BDLR3_DQ4RBD_Pos (24) /*!< DDRPHY_T::DX7BDLR3: DQ4RBD Position */ +#define DDRPHY_DX7BDLR3_DQ4RBD_Msk (0x3ful << DDRPHY_DX7BDLR3_DQ4RBD_Pos) /*!< DDRPHY_T::DX7BDLR3: DQ4RBD Mask */ + +#define DDRPHY_DX7BDLR4_DQ5RBD_Pos (0) /*!< DDRPHY_T::DX7BDLR4: DQ5RBD Position */ +#define DDRPHY_DX7BDLR4_DQ5RBD_Msk (0x3ful << DDRPHY_DX7BDLR4_DQ5RBD_Pos) /*!< DDRPHY_T::DX7BDLR4: DQ5RBD Mask */ + +#define DDRPHY_DX7BDLR4_DQ6RBD_Pos (6) /*!< DDRPHY_T::DX7BDLR4: DQ6RBD Position */ +#define DDRPHY_DX7BDLR4_DQ6RBD_Msk (0x3ful << DDRPHY_DX7BDLR4_DQ6RBD_Pos) /*!< DDRPHY_T::DX7BDLR4: DQ6RBD Mask */ + +#define DDRPHY_DX7BDLR4_DQ7RBD_Pos (12) /*!< DDRPHY_T::DX7BDLR4: DQ7RBD Position */ +#define DDRPHY_DX7BDLR4_DQ7RBD_Msk (0x3ful << DDRPHY_DX7BDLR4_DQ7RBD_Pos) /*!< DDRPHY_T::DX7BDLR4: DQ7RBD Mask */ + +#define DDRPHY_DX7BDLR4_DMRBD_Pos (18) /*!< DDRPHY_T::DX7BDLR4: DMRBD Position */ +#define DDRPHY_DX7BDLR4_DMRBD_Msk (0x3ful << DDRPHY_DX7BDLR4_DMRBD_Pos) /*!< DDRPHY_T::DX7BDLR4: DMRBD Mask */ + +#define DDRPHY_DX7LCDLR0_R0WLD_Pos (0) /*!< DDRPHY_T::DX7LCDLR0: R0WLD Position */ +#define DDRPHY_DX7LCDLR0_R0WLD_Msk (0xfful << DDRPHY_DX7LCDLR0_R0WLD_Pos) /*!< DDRPHY_T::DX7LCDLR0: R0WLD Mask */ + +#define DDRPHY_DX7LCDLR0_R1WLD_Pos (8) /*!< DDRPHY_T::DX7LCDLR0: R1WLD Position */ +#define DDRPHY_DX7LCDLR0_R1WLD_Msk (0xfful << DDRPHY_DX7LCDLR0_R1WLD_Pos) /*!< DDRPHY_T::DX7LCDLR0: R1WLD Mask */ + +#define DDRPHY_DX7LCDLR0_R2WLD_Pos (16) /*!< DDRPHY_T::DX7LCDLR0: R2WLD Position */ +#define DDRPHY_DX7LCDLR0_R2WLD_Msk (0xfful << DDRPHY_DX7LCDLR0_R2WLD_Pos) /*!< DDRPHY_T::DX7LCDLR0: R2WLD Mask */ + +#define DDRPHY_DX7LCDLR0_R3WLD_Pos (24) /*!< DDRPHY_T::DX7LCDLR0: R3WLD Position */ +#define DDRPHY_DX7LCDLR0_R3WLD_Msk (0xfful << DDRPHY_DX7LCDLR0_R3WLD_Pos) /*!< DDRPHY_T::DX7LCDLR0: R3WLD Mask */ + +#define DDRPHY_DX7LCDLR1_WDQD_Pos (0) /*!< DDRPHY_T::DX7LCDLR1: WDQD Position */ +#define DDRPHY_DX7LCDLR1_WDQD_Msk (0xfful << DDRPHY_DX7LCDLR1_WDQD_Pos) /*!< DDRPHY_T::DX7LCDLR1: WDQD Mask */ + +#define DDRPHY_DX7LCDLR1_RDQSD_Pos (8) /*!< DDRPHY_T::DX7LCDLR1: RDQSD Position */ +#define DDRPHY_DX7LCDLR1_RDQSD_Msk (0xfful << DDRPHY_DX7LCDLR1_RDQSD_Pos) /*!< DDRPHY_T::DX7LCDLR1: RDQSD Mask */ + +#define DDRPHY_DX7LCDLR1_RDQSND_Pos (16) /*!< DDRPHY_T::DX7LCDLR1: RDQSND Position */ +#define DDRPHY_DX7LCDLR1_RDQSND_Msk (0xfful << DDRPHY_DX7LCDLR1_RDQSND_Pos) /*!< DDRPHY_T::DX7LCDLR1: RDQSND Mask */ + +#define DDRPHY_DX7LCDLR2_R0DQSGD_Pos (0) /*!< DDRPHY_T::DX7LCDLR2: R0DQSGD Position */ +#define DDRPHY_DX7LCDLR2_R0DQSGD_Msk (0xfful << DDRPHY_DX7LCDLR2_R0DQSGD_Pos) /*!< DDRPHY_T::DX7LCDLR2: R0DQSGD Mask */ + +#define DDRPHY_DX7LCDLR2_R1DQSGD_Pos (8) /*!< DDRPHY_T::DX7LCDLR2: R1DQSGD Position */ +#define DDRPHY_DX7LCDLR2_R1DQSGD_Msk (0xfful << DDRPHY_DX7LCDLR2_R1DQSGD_Pos) /*!< DDRPHY_T::DX7LCDLR2: R1DQSGD Mask */ + +#define DDRPHY_DX7LCDLR2_R2DQSGD_Pos (16) /*!< DDRPHY_T::DX7LCDLR2: R2DQSGD Position */ +#define DDRPHY_DX7LCDLR2_R2DQSGD_Msk (0xfful << DDRPHY_DX7LCDLR2_R2DQSGD_Pos) /*!< DDRPHY_T::DX7LCDLR2: R2DQSGD Mask */ + +#define DDRPHY_DX7LCDLR2_R3DQSGD_Pos (24) /*!< DDRPHY_T::DX7LCDLR2: R3DQSGD Position */ +#define DDRPHY_DX7LCDLR2_R3DQSGD_Msk (0xfful << DDRPHY_DX7LCDLR2_R3DQSGD_Pos) /*!< DDRPHY_T::DX7LCDLR2: R3DQSGD Mask */ + +#define DDRPHY_DX7MDLR_IPRD_Pos (0) /*!< DDRPHY_T::DX7MDLR: IPRD Position */ +#define DDRPHY_DX7MDLR_IPRD_Msk (0xfful << DDRPHY_DX7MDLR_IPRD_Pos) /*!< DDRPHY_T::DX7MDLR: IPRD Mask */ + +#define DDRPHY_DX7MDLR_TPRD_Pos (8) /*!< DDRPHY_T::DX7MDLR: TPRD Position */ +#define DDRPHY_DX7MDLR_TPRD_Msk (0xfful << DDRPHY_DX7MDLR_TPRD_Pos) /*!< DDRPHY_T::DX7MDLR: TPRD Mask */ + +#define DDRPHY_DX7MDLR_MDLD_Pos (16) /*!< DDRPHY_T::DX7MDLR: MDLD Position */ +#define DDRPHY_DX7MDLR_MDLD_Msk (0xfful << DDRPHY_DX7MDLR_MDLD_Pos) /*!< DDRPHY_T::DX7MDLR: MDLD Mask */ + +#define DDRPHY_DX7GTR_R0DGSL_Pos (0) /*!< DDRPHY_T::DX7GTR: R0DGSL Position */ +#define DDRPHY_DX7GTR_R0DGSL_Msk (0x7ul << DDRPHY_DX7GTR_R0DGSL_Pos) /*!< DDRPHY_T::DX7GTR: R0DGSL Mask */ + +#define DDRPHY_DX7GTR_R1DGSL_Pos (3) /*!< DDRPHY_T::DX7GTR: R1DGSL Position */ +#define DDRPHY_DX7GTR_R1DGSL_Msk (0x7ul << DDRPHY_DX7GTR_R1DGSL_Pos) /*!< DDRPHY_T::DX7GTR: R1DGSL Mask */ + +#define DDRPHY_DX7GTR_R2DGSL_Pos (6) /*!< DDRPHY_T::DX7GTR: R2DGSL Position */ +#define DDRPHY_DX7GTR_R2DGSL_Msk (0x7ul << DDRPHY_DX7GTR_R2DGSL_Pos) /*!< DDRPHY_T::DX7GTR: R2DGSL Mask */ + +#define DDRPHY_DX7GTR_R3DGSL_Pos (9) /*!< DDRPHY_T::DX7GTR: R3DGSL Position */ +#define DDRPHY_DX7GTR_R3DGSL_Msk (0x7ul << DDRPHY_DX7GTR_R3DGSL_Pos) /*!< DDRPHY_T::DX7GTR: R3DGSL Mask */ + +#define DDRPHY_DX7GTR_R0WLSL_Pos (12) /*!< DDRPHY_T::DX7GTR: R0WLSL Position */ +#define DDRPHY_DX7GTR_R0WLSL_Msk (0x3ul << DDRPHY_DX7GTR_R0WLSL_Pos) /*!< DDRPHY_T::DX7GTR: R0WLSL Mask */ + +#define DDRPHY_DX7GTR_R1WLSL_Pos (14) /*!< DDRPHY_T::DX7GTR: R1WLSL Position */ +#define DDRPHY_DX7GTR_R1WLSL_Msk (0x3ul << DDRPHY_DX7GTR_R1WLSL_Pos) /*!< DDRPHY_T::DX7GTR: R1WLSL Mask */ + +#define DDRPHY_DX7GTR_R2WLSL_Pos (16) /*!< DDRPHY_T::DX7GTR: R2WLSL Position */ +#define DDRPHY_DX7GTR_R2WLSL_Msk (0x3ul << DDRPHY_DX7GTR_R2WLSL_Pos) /*!< DDRPHY_T::DX7GTR: R2WLSL Mask */ + +#define DDRPHY_DX7GTR_R3WLSL_Pos (18) /*!< DDRPHY_T::DX7GTR: R3WLSL Position */ +#define DDRPHY_DX7GTR_R3WLSL_Msk (0x3ul << DDRPHY_DX7GTR_R3WLSL_Pos) /*!< DDRPHY_T::DX7GTR: R3WLSL Mask */ + +#define DDRPHY_DX7GSR2_RDERR_Pos (0) /*!< DDRPHY_T::DX7GSR2: RDERR Position */ +#define DDRPHY_DX7GSR2_RDERR_Msk (0x1ul << DDRPHY_DX7GSR2_RDERR_Pos) /*!< DDRPHY_T::DX7GSR2: RDERR Mask */ + +#define DDRPHY_DX7GSR2_RDWN_Pos (1) /*!< DDRPHY_T::DX7GSR2: RDWN Position */ +#define DDRPHY_DX7GSR2_RDWN_Msk (0x1ul << DDRPHY_DX7GSR2_RDWN_Pos) /*!< DDRPHY_T::DX7GSR2: RDWN Mask */ + +#define DDRPHY_DX7GSR2_WDERR_Pos (2) /*!< DDRPHY_T::DX7GSR2: WDERR Position */ +#define DDRPHY_DX7GSR2_WDERR_Msk (0x1ul << DDRPHY_DX7GSR2_WDERR_Pos) /*!< DDRPHY_T::DX7GSR2: WDERR Mask */ + +#define DDRPHY_DX7GSR2_WDWN_Pos (3) /*!< DDRPHY_T::DX7GSR2: WDWN Position */ +#define DDRPHY_DX7GSR2_WDWN_Msk (0x1ul << DDRPHY_DX7GSR2_WDWN_Pos) /*!< DDRPHY_T::DX7GSR2: WDWN Mask */ + +#define DDRPHY_DX7GSR2_REERR_Pos (4) /*!< DDRPHY_T::DX7GSR2: REERR Position */ +#define DDRPHY_DX7GSR2_REERR_Msk (0x1ul << DDRPHY_DX7GSR2_REERR_Pos) /*!< DDRPHY_T::DX7GSR2: REERR Mask */ + +#define DDRPHY_DX7GSR2_REWN_Pos (5) /*!< DDRPHY_T::DX7GSR2: REWN Position */ +#define DDRPHY_DX7GSR2_REWN_Msk (0x1ul << DDRPHY_DX7GSR2_REWN_Pos) /*!< DDRPHY_T::DX7GSR2: REWN Mask */ + +#define DDRPHY_DX7GSR2_WEERR_Pos (6) /*!< DDRPHY_T::DX7GSR2: WEERR Position */ +#define DDRPHY_DX7GSR2_WEERR_Msk (0x1ul << DDRPHY_DX7GSR2_WEERR_Pos) /*!< DDRPHY_T::DX7GSR2: WEERR Mask */ + +#define DDRPHY_DX7GSR2_WEWN_Pos (7) /*!< DDRPHY_T::DX7GSR2: WEWN Position */ +#define DDRPHY_DX7GSR2_WEWN_Msk (0x1ul << DDRPHY_DX7GSR2_WEWN_Pos) /*!< DDRPHY_T::DX7GSR2: WEWN Mask */ + +#define DDRPHY_DX7GSR2_ESTAT_Pos (8) /*!< DDRPHY_T::DX7GSR2: ESTAT Position */ +#define DDRPHY_DX7GSR2_ESTAT_Msk (0xful << DDRPHY_DX7GSR2_ESTAT_Pos) /*!< DDRPHY_T::DX7GSR2: ESTAT Mask */ + +#define DDRPHY_DX8GCR_DXEN_Pos (0) /*!< DDRPHY_T::DX8GCR: DXEN Position */ +#define DDRPHY_DX8GCR_DXEN_Msk (0x1ul << DDRPHY_DX8GCR_DXEN_Pos) /*!< DDRPHY_T::DX8GCR: DXEN Mask */ + +#define DDRPHY_DX8GCR_DQSODT_Pos (1) /*!< DDRPHY_T::DX8GCR: DQSODT Position */ +#define DDRPHY_DX8GCR_DQSODT_Msk (0x1ul << DDRPHY_DX8GCR_DQSODT_Pos) /*!< DDRPHY_T::DX8GCR: DQSODT Mask */ + +#define DDRPHY_DX8GCR_DQODT_Pos (2) /*!< DDRPHY_T::DX8GCR: DQODT Position */ +#define DDRPHY_DX8GCR_DQODT_Msk (0x1ul << DDRPHY_DX8GCR_DQODT_Pos) /*!< DDRPHY_T::DX8GCR: DQODT Mask */ + +#define DDRPHY_DX8GCR_DXIOM_Pos (3) /*!< DDRPHY_T::DX8GCR: DXIOM Position */ +#define DDRPHY_DX8GCR_DXIOM_Msk (0x1ul << DDRPHY_DX8GCR_DXIOM_Pos) /*!< DDRPHY_T::DX8GCR: DXIOM Mask */ + +#define DDRPHY_DX8GCR_DXPDD_Pos (4) /*!< DDRPHY_T::DX8GCR: DXPDD Position */ +#define DDRPHY_DX8GCR_DXPDD_Msk (0x1ul << DDRPHY_DX8GCR_DXPDD_Pos) /*!< DDRPHY_T::DX8GCR: DXPDD Mask */ + +#define DDRPHY_DX8GCR_DXPDR_Pos (5) /*!< DDRPHY_T::DX8GCR: DXPDR Position */ +#define DDRPHY_DX8GCR_DXPDR_Msk (0x1ul << DDRPHY_DX8GCR_DXPDR_Pos) /*!< DDRPHY_T::DX8GCR: DXPDR Mask */ + +#define DDRPHY_DX8GCR_DQSRPD_Pos (6) /*!< DDRPHY_T::DX8GCR: DQSRPD Position */ +#define DDRPHY_DX8GCR_DQSRPD_Msk (0x1ul << DDRPHY_DX8GCR_DQSRPD_Pos) /*!< DDRPHY_T::DX8GCR: DQSRPD Mask */ + +#define DDRPHY_DX8GCR_DSEN_Pos (7) /*!< DDRPHY_T::DX8GCR: DSEN Position */ +#define DDRPHY_DX8GCR_DSEN_Msk (0x3ul << DDRPHY_DX8GCR_DSEN_Pos) /*!< DDRPHY_T::DX8GCR: DSEN Mask */ + +#define DDRPHY_DX8GCR_DQSRTT_Pos (9) /*!< DDRPHY_T::DX8GCR: DQSRTT Position */ +#define DDRPHY_DX8GCR_DQSRTT_Msk (0x1ul << DDRPHY_DX8GCR_DQSRTT_Pos) /*!< DDRPHY_T::DX8GCR: DQSRTT Mask */ + +#define DDRPHY_DX8GCR_DQRTT_Pos (10) /*!< DDRPHY_T::DX8GCR: DQRTT Position */ +#define DDRPHY_DX8GCR_DQRTT_Msk (0x1ul << DDRPHY_DX8GCR_DQRTT_Pos) /*!< DDRPHY_T::DX8GCR: DQRTT Mask */ + +#define DDRPHY_DX8GCR_RTTOH_Pos (11) /*!< DDRPHY_T::DX8GCR: RTTOH Position */ +#define DDRPHY_DX8GCR_RTTOH_Msk (0x3ul << DDRPHY_DX8GCR_RTTOH_Pos) /*!< DDRPHY_T::DX8GCR: RTTOH Mask */ + +#define DDRPHY_DX8GCR_RTTOAL_Pos (13) /*!< DDRPHY_T::DX8GCR: RTTOAL Position */ +#define DDRPHY_DX8GCR_RTTOAL_Msk (0x1ul << DDRPHY_DX8GCR_RTTOAL_Pos) /*!< DDRPHY_T::DX8GCR: RTTOAL Mask */ + +#define DDRPHY_DX8GCR_DXOEO_Pos (14) /*!< DDRPHY_T::DX8GCR: DXOEO Position */ +#define DDRPHY_DX8GCR_DXOEO_Msk (0x3ul << DDRPHY_DX8GCR_DXOEO_Pos) /*!< DDRPHY_T::DX8GCR: DXOEO Mask */ + +#define DDRPHY_DX8GCR_PLLRST_Pos (16) /*!< DDRPHY_T::DX8GCR: PLLRST Position */ +#define DDRPHY_DX8GCR_PLLRST_Msk (0x1ul << DDRPHY_DX8GCR_PLLRST_Pos) /*!< DDRPHY_T::DX8GCR: PLLRST Mask */ + +#define DDRPHY_DX8GCR_PLLPD_Pos (17) /*!< DDRPHY_T::DX8GCR: PLLPD Position */ +#define DDRPHY_DX8GCR_PLLPD_Msk (0x1ul << DDRPHY_DX8GCR_PLLPD_Pos) /*!< DDRPHY_T::DX8GCR: PLLPD Mask */ + +#define DDRPHY_DX8GCR_GSHIFT_Pos (18) /*!< DDRPHY_T::DX8GCR: GSHIFT Position */ +#define DDRPHY_DX8GCR_GSHIFT_Msk (0x1ul << DDRPHY_DX8GCR_GSHIFT_Pos) /*!< DDRPHY_T::DX8GCR: GSHIFT Mask */ + +#define DDRPHY_DX8GCR_PLLBYP_Pos (19) /*!< DDRPHY_T::DX8GCR: PLLBYP Position */ +#define DDRPHY_DX8GCR_PLLBYP_Msk (0x1ul << DDRPHY_DX8GCR_PLLBYP_Pos) /*!< DDRPHY_T::DX8GCR: PLLBYP Mask */ + +#define DDRPHY_DX8GCR_WLRKEN_Pos (26) /*!< DDRPHY_T::DX8GCR: WLRKEN Position */ +#define DDRPHY_DX8GCR_WLRKEN_Msk (0xful << DDRPHY_DX8GCR_WLRKEN_Pos) /*!< DDRPHY_T::DX8GCR: WLRKEN Mask */ + +#define DDRPHY_DX8GCR_MDLEN_Pos (30) /*!< DDRPHY_T::DX8GCR: MDLEN Position */ +#define DDRPHY_DX8GCR_MDLEN_Msk (0x1ul << DDRPHY_DX8GCR_MDLEN_Pos) /*!< DDRPHY_T::DX8GCR: MDLEN Mask */ + +#define DDRPHY_DX8GCR_CALBYP_Pos (31) /*!< DDRPHY_T::DX8GCR: CALBYP Position */ +#define DDRPHY_DX8GCR_CALBYP_Msk (0x1ul << DDRPHY_DX8GCR_CALBYP_Pos) /*!< DDRPHY_T::DX8GCR: CALBYP Mask */ + +#define DDRPHY_DX8GSR0_WDQCAL_Pos (0) /*!< DDRPHY_T::DX8GSR0: WDQCAL Position */ +#define DDRPHY_DX8GSR0_WDQCAL_Msk (0x1ul << DDRPHY_DX8GSR0_WDQCAL_Pos) /*!< DDRPHY_T::DX8GSR0: WDQCAL Mask */ + +#define DDRPHY_DX8GSR0_RDQSCAL_Pos (1) /*!< DDRPHY_T::DX8GSR0: RDQSCAL Position */ +#define DDRPHY_DX8GSR0_RDQSCAL_Msk (0x1ul << DDRPHY_DX8GSR0_RDQSCAL_Pos) /*!< DDRPHY_T::DX8GSR0: RDQSCAL Mask */ + +#define DDRPHY_DX8GSR0_RDQSNCAL_Pos (2) /*!< DDRPHY_T::DX8GSR0: RDQSNCAL Position */ +#define DDRPHY_DX8GSR0_RDQSNCAL_Msk (0x1ul << DDRPHY_DX8GSR0_RDQSNCAL_Pos) /*!< DDRPHY_T::DX8GSR0: RDQSNCAL Mask */ + +#define DDRPHY_DX8GSR0_GDQSCAL_Pos (3) /*!< DDRPHY_T::DX8GSR0: GDQSCAL Position */ +#define DDRPHY_DX8GSR0_GDQSCAL_Msk (0x1ul << DDRPHY_DX8GSR0_GDQSCAL_Pos) /*!< DDRPHY_T::DX8GSR0: GDQSCAL Mask */ + +#define DDRPHY_DX8GSR0_WLCAL_Pos (4) /*!< DDRPHY_T::DX8GSR0: WLCAL Position */ +#define DDRPHY_DX8GSR0_WLCAL_Msk (0x1ul << DDRPHY_DX8GSR0_WLCAL_Pos) /*!< DDRPHY_T::DX8GSR0: WLCAL Mask */ + +#define DDRPHY_DX8GSR0_WLDONE_Pos (5) /*!< DDRPHY_T::DX8GSR0: WLDONE Position */ +#define DDRPHY_DX8GSR0_WLDONE_Msk (0x1ul << DDRPHY_DX8GSR0_WLDONE_Pos) /*!< DDRPHY_T::DX8GSR0: WLDONE Mask */ + +#define DDRPHY_DX8GSR0_WLERR_Pos (6) /*!< DDRPHY_T::DX8GSR0: WLERR Position */ +#define DDRPHY_DX8GSR0_WLERR_Msk (0x1ul << DDRPHY_DX8GSR0_WLERR_Pos) /*!< DDRPHY_T::DX8GSR0: WLERR Mask */ + +#define DDRPHY_DX8GSR0_WLPRD_Pos (7) /*!< DDRPHY_T::DX8GSR0: WLPRD Position */ +#define DDRPHY_DX8GSR0_WLPRD_Msk (0xfful << DDRPHY_DX8GSR0_WLPRD_Pos) /*!< DDRPHY_T::DX8GSR0: WLPRD Mask */ + +#define DDRPHY_DX8GSR0_DPLOCK_Pos (15) /*!< DDRPHY_T::DX8GSR0: DPLOCK Position */ +#define DDRPHY_DX8GSR0_DPLOCK_Msk (0x1ul << DDRPHY_DX8GSR0_DPLOCK_Pos) /*!< DDRPHY_T::DX8GSR0: DPLOCK Mask */ + +#define DDRPHY_DX8GSR0_GDQSPRD_Pos (16) /*!< DDRPHY_T::DX8GSR0: GDQSPRD Position */ +#define DDRPHY_DX8GSR0_GDQSPRD_Msk (0xfful << DDRPHY_DX8GSR0_GDQSPRD_Pos) /*!< DDRPHY_T::DX8GSR0: GDQSPRD Mask */ + +#define DDRPHY_DX8GSR0_QSGERR_Pos (24) /*!< DDRPHY_T::DX8GSR0: QSGERR Position */ +#define DDRPHY_DX8GSR0_QSGERR_Msk (0xful << DDRPHY_DX8GSR0_QSGERR_Pos) /*!< DDRPHY_T::DX8GSR0: QSGERR Mask */ + +#define DDRPHY_DX8GSR0_WLDQ_Pos (28) /*!< DDRPHY_T::DX8GSR0: WLDQ Position */ +#define DDRPHY_DX8GSR0_WLDQ_Msk (0x1ul << DDRPHY_DX8GSR0_WLDQ_Pos) /*!< DDRPHY_T::DX8GSR0: WLDQ Mask */ + +#define DDRPHY_DX8GSR1_DLTDONE_Pos (0) /*!< DDRPHY_T::DX8GSR1: DLTDONE Position */ +#define DDRPHY_DX8GSR1_DLTDONE_Msk (0x1ul << DDRPHY_DX8GSR1_DLTDONE_Pos) /*!< DDRPHY_T::DX8GSR1: DLTDONE Mask */ + +#define DDRPHY_DX8GSR1_DLTCODE_Pos (1) /*!< DDRPHY_T::DX8GSR1: DLTCODE Position */ +#define DDRPHY_DX8GSR1_DLTCODE_Msk (0xfffffful << DDRPHY_DX8GSR1_DLTCODE_Pos) /*!< DDRPHY_T::DX8GSR1: DLTCODE Mask */ + +#define DDRPHY_DX8BDLR0_DQ0WBD_Pos (0) /*!< DDRPHY_T::DX8BDLR0: DQ0WBD Position */ +#define DDRPHY_DX8BDLR0_DQ0WBD_Msk (0x3ful << DDRPHY_DX8BDLR0_DQ0WBD_Pos) /*!< DDRPHY_T::DX8BDLR0: DQ0WBD Mask */ + +#define DDRPHY_DX8BDLR0_DQ1WBD_Pos (6) /*!< DDRPHY_T::DX8BDLR0: DQ1WBD Position */ +#define DDRPHY_DX8BDLR0_DQ1WBD_Msk (0x3ful << DDRPHY_DX8BDLR0_DQ1WBD_Pos) /*!< DDRPHY_T::DX8BDLR0: DQ1WBD Mask */ + +#define DDRPHY_DX8BDLR0_DQ2WBD_Pos (12) /*!< DDRPHY_T::DX8BDLR0: DQ2WBD Position */ +#define DDRPHY_DX8BDLR0_DQ2WBD_Msk (0x3ful << DDRPHY_DX8BDLR0_DQ2WBD_Pos) /*!< DDRPHY_T::DX8BDLR0: DQ2WBD Mask */ + +#define DDRPHY_DX8BDLR0_DQ3WBD_Pos (18) /*!< DDRPHY_T::DX8BDLR0: DQ3WBD Position */ +#define DDRPHY_DX8BDLR0_DQ3WBD_Msk (0x3ful << DDRPHY_DX8BDLR0_DQ3WBD_Pos) /*!< DDRPHY_T::DX8BDLR0: DQ3WBD Mask */ + +#define DDRPHY_DX8BDLR0_DQ4WBD_Pos (24) /*!< DDRPHY_T::DX8BDLR0: DQ4WBD Position */ +#define DDRPHY_DX8BDLR0_DQ4WBD_Msk (0x3ful << DDRPHY_DX8BDLR0_DQ4WBD_Pos) /*!< DDRPHY_T::DX8BDLR0: DQ4WBD Mask */ + +#define DDRPHY_DX8BDLR1_DQ5WBD_Pos (0) /*!< DDRPHY_T::DX8BDLR1: DQ5WBD Position */ +#define DDRPHY_DX8BDLR1_DQ5WBD_Msk (0x3ful << DDRPHY_DX8BDLR1_DQ5WBD_Pos) /*!< DDRPHY_T::DX8BDLR1: DQ5WBD Mask */ + +#define DDRPHY_DX8BDLR1_DQ6WBD_Pos (6) /*!< DDRPHY_T::DX8BDLR1: DQ6WBD Position */ +#define DDRPHY_DX8BDLR1_DQ6WBD_Msk (0x3ful << DDRPHY_DX8BDLR1_DQ6WBD_Pos) /*!< DDRPHY_T::DX8BDLR1: DQ6WBD Mask */ + +#define DDRPHY_DX8BDLR1_DQ7WBD_Pos (12) /*!< DDRPHY_T::DX8BDLR1: DQ7WBD Position */ +#define DDRPHY_DX8BDLR1_DQ7WBD_Msk (0x3ful << DDRPHY_DX8BDLR1_DQ7WBD_Pos) /*!< DDRPHY_T::DX8BDLR1: DQ7WBD Mask */ + +#define DDRPHY_DX8BDLR1_DMWBD_Pos (18) /*!< DDRPHY_T::DX8BDLR1: DMWBD Position */ +#define DDRPHY_DX8BDLR1_DMWBD_Msk (0x3ful << DDRPHY_DX8BDLR1_DMWBD_Pos) /*!< DDRPHY_T::DX8BDLR1: DMWBD Mask */ + +#define DDRPHY_DX8BDLR1_DSWBD_Pos (24) /*!< DDRPHY_T::DX8BDLR1: DSWBD Position */ +#define DDRPHY_DX8BDLR1_DSWBD_Msk (0x3ful << DDRPHY_DX8BDLR1_DSWBD_Pos) /*!< DDRPHY_T::DX8BDLR1: DSWBD Mask */ + +#define DDRPHY_DX8BDLR2_DSOEBD_Pos (0) /*!< DDRPHY_T::DX8BDLR2: DSOEBD Position */ +#define DDRPHY_DX8BDLR2_DSOEBD_Msk (0x3ful << DDRPHY_DX8BDLR2_DSOEBD_Pos) /*!< DDRPHY_T::DX8BDLR2: DSOEBD Mask */ + +#define DDRPHY_DX8BDLR2_DQOEBD_Pos (6) /*!< DDRPHY_T::DX8BDLR2: DQOEBD Position */ +#define DDRPHY_DX8BDLR2_DQOEBD_Msk (0x3ful << DDRPHY_DX8BDLR2_DQOEBD_Pos) /*!< DDRPHY_T::DX8BDLR2: DQOEBD Mask */ + +#define DDRPHY_DX8BDLR2_DSRBD_Pos (12) /*!< DDRPHY_T::DX8BDLR2: DSRBD Position */ +#define DDRPHY_DX8BDLR2_DSRBD_Msk (0x3ful << DDRPHY_DX8BDLR2_DSRBD_Pos) /*!< DDRPHY_T::DX8BDLR2: DSRBD Mask */ + +#define DDRPHY_DX8BDLR2_DSNRBD_Pos (18) /*!< DDRPHY_T::DX8BDLR2: DSNRBD Position */ +#define DDRPHY_DX8BDLR2_DSNRBD_Msk (0x3ful << DDRPHY_DX8BDLR2_DSNRBD_Pos) /*!< DDRPHY_T::DX8BDLR2: DSNRBD Mask */ + +#define DDRPHY_DX8BDLR3_DQ0RBD_Pos (0) /*!< DDRPHY_T::DX8BDLR3: DQ0RBD Position */ +#define DDRPHY_DX8BDLR3_DQ0RBD_Msk (0x3ful << DDRPHY_DX8BDLR3_DQ0RBD_Pos) /*!< DDRPHY_T::DX8BDLR3: DQ0RBD Mask */ + +#define DDRPHY_DX8BDLR3_DQ1RBD_Pos (6) /*!< DDRPHY_T::DX8BDLR3: DQ1RBD Position */ +#define DDRPHY_DX8BDLR3_DQ1RBD_Msk (0x3ful << DDRPHY_DX8BDLR3_DQ1RBD_Pos) /*!< DDRPHY_T::DX8BDLR3: DQ1RBD Mask */ + +#define DDRPHY_DX8BDLR3_DQ2RBD_Pos (12) /*!< DDRPHY_T::DX8BDLR3: DQ2RBD Position */ +#define DDRPHY_DX8BDLR3_DQ2RBD_Msk (0x3ful << DDRPHY_DX8BDLR3_DQ2RBD_Pos) /*!< DDRPHY_T::DX8BDLR3: DQ2RBD Mask */ + +#define DDRPHY_DX8BDLR3_DQ3RBD_Pos (18) /*!< DDRPHY_T::DX8BDLR3: DQ3RBD Position */ +#define DDRPHY_DX8BDLR3_DQ3RBD_Msk (0x3ful << DDRPHY_DX8BDLR3_DQ3RBD_Pos) /*!< DDRPHY_T::DX8BDLR3: DQ3RBD Mask */ + +#define DDRPHY_DX8BDLR3_DQ4RBD_Pos (24) /*!< DDRPHY_T::DX8BDLR3: DQ4RBD Position */ +#define DDRPHY_DX8BDLR3_DQ4RBD_Msk (0x3ful << DDRPHY_DX8BDLR3_DQ4RBD_Pos) /*!< DDRPHY_T::DX8BDLR3: DQ4RBD Mask */ + +#define DDRPHY_DX8BDLR4_DQ5RBD_Pos (0) /*!< DDRPHY_T::DX8BDLR4: DQ5RBD Position */ +#define DDRPHY_DX8BDLR4_DQ5RBD_Msk (0x3ful << DDRPHY_DX8BDLR4_DQ5RBD_Pos) /*!< DDRPHY_T::DX8BDLR4: DQ5RBD Mask */ + +#define DDRPHY_DX8BDLR4_DQ6RBD_Pos (6) /*!< DDRPHY_T::DX8BDLR4: DQ6RBD Position */ +#define DDRPHY_DX8BDLR4_DQ6RBD_Msk (0x3ful << DDRPHY_DX8BDLR4_DQ6RBD_Pos) /*!< DDRPHY_T::DX8BDLR4: DQ6RBD Mask */ + +#define DDRPHY_DX8BDLR4_DQ7RBD_Pos (12) /*!< DDRPHY_T::DX8BDLR4: DQ7RBD Position */ +#define DDRPHY_DX8BDLR4_DQ7RBD_Msk (0x3ful << DDRPHY_DX8BDLR4_DQ7RBD_Pos) /*!< DDRPHY_T::DX8BDLR4: DQ7RBD Mask */ + +#define DDRPHY_DX8BDLR4_DMRBD_Pos (18) /*!< DDRPHY_T::DX8BDLR4: DMRBD Position */ +#define DDRPHY_DX8BDLR4_DMRBD_Msk (0x3ful << DDRPHY_DX8BDLR4_DMRBD_Pos) /*!< DDRPHY_T::DX8BDLR4: DMRBD Mask */ + +#define DDRPHY_DX8LCDLR0_R0WLD_Pos (0) /*!< DDRPHY_T::DX8LCDLR0: R0WLD Position */ +#define DDRPHY_DX8LCDLR0_R0WLD_Msk (0xfful << DDRPHY_DX8LCDLR0_R0WLD_Pos) /*!< DDRPHY_T::DX8LCDLR0: R0WLD Mask */ + +#define DDRPHY_DX8LCDLR0_R1WLD_Pos (8) /*!< DDRPHY_T::DX8LCDLR0: R1WLD Position */ +#define DDRPHY_DX8LCDLR0_R1WLD_Msk (0xfful << DDRPHY_DX8LCDLR0_R1WLD_Pos) /*!< DDRPHY_T::DX8LCDLR0: R1WLD Mask */ + +#define DDRPHY_DX8LCDLR0_R2WLD_Pos (16) /*!< DDRPHY_T::DX8LCDLR0: R2WLD Position */ +#define DDRPHY_DX8LCDLR0_R2WLD_Msk (0xfful << DDRPHY_DX8LCDLR0_R2WLD_Pos) /*!< DDRPHY_T::DX8LCDLR0: R2WLD Mask */ + +#define DDRPHY_DX8LCDLR0_R3WLD_Pos (24) /*!< DDRPHY_T::DX8LCDLR0: R3WLD Position */ +#define DDRPHY_DX8LCDLR0_R3WLD_Msk (0xfful << DDRPHY_DX8LCDLR0_R3WLD_Pos) /*!< DDRPHY_T::DX8LCDLR0: R3WLD Mask */ + +#define DDRPHY_DX8LCDLR1_WDQD_Pos (0) /*!< DDRPHY_T::DX8LCDLR1: WDQD Position */ +#define DDRPHY_DX8LCDLR1_WDQD_Msk (0xfful << DDRPHY_DX8LCDLR1_WDQD_Pos) /*!< DDRPHY_T::DX8LCDLR1: WDQD Mask */ + +#define DDRPHY_DX8LCDLR1_RDQSD_Pos (8) /*!< DDRPHY_T::DX8LCDLR1: RDQSD Position */ +#define DDRPHY_DX8LCDLR1_RDQSD_Msk (0xfful << DDRPHY_DX8LCDLR1_RDQSD_Pos) /*!< DDRPHY_T::DX8LCDLR1: RDQSD Mask */ + +#define DDRPHY_DX8LCDLR1_RDQSND_Pos (16) /*!< DDRPHY_T::DX8LCDLR1: RDQSND Position */ +#define DDRPHY_DX8LCDLR1_RDQSND_Msk (0xfful << DDRPHY_DX8LCDLR1_RDQSND_Pos) /*!< DDRPHY_T::DX8LCDLR1: RDQSND Mask */ + +#define DDRPHY_DX8LCDLR2_R0DQSGD_Pos (0) /*!< DDRPHY_T::DX8LCDLR2: R0DQSGD Position */ +#define DDRPHY_DX8LCDLR2_R0DQSGD_Msk (0xfful << DDRPHY_DX8LCDLR2_R0DQSGD_Pos) /*!< DDRPHY_T::DX8LCDLR2: R0DQSGD Mask */ + +#define DDRPHY_DX8LCDLR2_R1DQSGD_Pos (8) /*!< DDRPHY_T::DX8LCDLR2: R1DQSGD Position */ +#define DDRPHY_DX8LCDLR2_R1DQSGD_Msk (0xfful << DDRPHY_DX8LCDLR2_R1DQSGD_Pos) /*!< DDRPHY_T::DX8LCDLR2: R1DQSGD Mask */ + +#define DDRPHY_DX8LCDLR2_R2DQSGD_Pos (16) /*!< DDRPHY_T::DX8LCDLR2: R2DQSGD Position */ +#define DDRPHY_DX8LCDLR2_R2DQSGD_Msk (0xfful << DDRPHY_DX8LCDLR2_R2DQSGD_Pos) /*!< DDRPHY_T::DX8LCDLR2: R2DQSGD Mask */ + +#define DDRPHY_DX8LCDLR2_R3DQSGD_Pos (24) /*!< DDRPHY_T::DX8LCDLR2: R3DQSGD Position */ +#define DDRPHY_DX8LCDLR2_R3DQSGD_Msk (0xfful << DDRPHY_DX8LCDLR2_R3DQSGD_Pos) /*!< DDRPHY_T::DX8LCDLR2: R3DQSGD Mask */ + +#define DDRPHY_DX8MDLR_IPRD_Pos (0) /*!< DDRPHY_T::DX8MDLR: IPRD Position */ +#define DDRPHY_DX8MDLR_IPRD_Msk (0xfful << DDRPHY_DX8MDLR_IPRD_Pos) /*!< DDRPHY_T::DX8MDLR: IPRD Mask */ + +#define DDRPHY_DX8MDLR_TPRD_Pos (8) /*!< DDRPHY_T::DX8MDLR: TPRD Position */ +#define DDRPHY_DX8MDLR_TPRD_Msk (0xfful << DDRPHY_DX8MDLR_TPRD_Pos) /*!< DDRPHY_T::DX8MDLR: TPRD Mask */ + +#define DDRPHY_DX8MDLR_MDLD_Pos (16) /*!< DDRPHY_T::DX8MDLR: MDLD Position */ +#define DDRPHY_DX8MDLR_MDLD_Msk (0xfful << DDRPHY_DX8MDLR_MDLD_Pos) /*!< DDRPHY_T::DX8MDLR: MDLD Mask */ + +#define DDRPHY_DX8GTR_R0DGSL_Pos (0) /*!< DDRPHY_T::DX8GTR: R0DGSL Position */ +#define DDRPHY_DX8GTR_R0DGSL_Msk (0x7ul << DDRPHY_DX8GTR_R0DGSL_Pos) /*!< DDRPHY_T::DX8GTR: R0DGSL Mask */ + +#define DDRPHY_DX8GTR_R1DGSL_Pos (3) /*!< DDRPHY_T::DX8GTR: R1DGSL Position */ +#define DDRPHY_DX8GTR_R1DGSL_Msk (0x7ul << DDRPHY_DX8GTR_R1DGSL_Pos) /*!< DDRPHY_T::DX8GTR: R1DGSL Mask */ + +#define DDRPHY_DX8GTR_R2DGSL_Pos (6) /*!< DDRPHY_T::DX8GTR: R2DGSL Position */ +#define DDRPHY_DX8GTR_R2DGSL_Msk (0x7ul << DDRPHY_DX8GTR_R2DGSL_Pos) /*!< DDRPHY_T::DX8GTR: R2DGSL Mask */ + +#define DDRPHY_DX8GTR_R3DGSL_Pos (9) /*!< DDRPHY_T::DX8GTR: R3DGSL Position */ +#define DDRPHY_DX8GTR_R3DGSL_Msk (0x7ul << DDRPHY_DX8GTR_R3DGSL_Pos) /*!< DDRPHY_T::DX8GTR: R3DGSL Mask */ + +#define DDRPHY_DX8GTR_R0WLSL_Pos (12) /*!< DDRPHY_T::DX8GTR: R0WLSL Position */ +#define DDRPHY_DX8GTR_R0WLSL_Msk (0x3ul << DDRPHY_DX8GTR_R0WLSL_Pos) /*!< DDRPHY_T::DX8GTR: R0WLSL Mask */ + +#define DDRPHY_DX8GTR_R1WLSL_Pos (14) /*!< DDRPHY_T::DX8GTR: R1WLSL Position */ +#define DDRPHY_DX8GTR_R1WLSL_Msk (0x3ul << DDRPHY_DX8GTR_R1WLSL_Pos) /*!< DDRPHY_T::DX8GTR: R1WLSL Mask */ + +#define DDRPHY_DX8GTR_R2WLSL_Pos (16) /*!< DDRPHY_T::DX8GTR: R2WLSL Position */ +#define DDRPHY_DX8GTR_R2WLSL_Msk (0x3ul << DDRPHY_DX8GTR_R2WLSL_Pos) /*!< DDRPHY_T::DX8GTR: R2WLSL Mask */ + +#define DDRPHY_DX8GTR_R3WLSL_Pos (18) /*!< DDRPHY_T::DX8GTR: R3WLSL Position */ +#define DDRPHY_DX8GTR_R3WLSL_Msk (0x3ul << DDRPHY_DX8GTR_R3WLSL_Pos) /*!< DDRPHY_T::DX8GTR: R3WLSL Mask */ + +#define DDRPHY_DX8GSR2_RDERR_Pos (0) /*!< DDRPHY_T::DX8GSR2: RDERR Position */ +#define DDRPHY_DX8GSR2_RDERR_Msk (0x1ul << DDRPHY_DX8GSR2_RDERR_Pos) /*!< DDRPHY_T::DX8GSR2: RDERR Mask */ + +#define DDRPHY_DX8GSR2_RDWN_Pos (1) /*!< DDRPHY_T::DX8GSR2: RDWN Position */ +#define DDRPHY_DX8GSR2_RDWN_Msk (0x1ul << DDRPHY_DX8GSR2_RDWN_Pos) /*!< DDRPHY_T::DX8GSR2: RDWN Mask */ + +#define DDRPHY_DX8GSR2_WDERR_Pos (2) /*!< DDRPHY_T::DX8GSR2: WDERR Position */ +#define DDRPHY_DX8GSR2_WDERR_Msk (0x1ul << DDRPHY_DX8GSR2_WDERR_Pos) /*!< DDRPHY_T::DX8GSR2: WDERR Mask */ + +#define DDRPHY_DX8GSR2_WDWN_Pos (3) /*!< DDRPHY_T::DX8GSR2: WDWN Position */ +#define DDRPHY_DX8GSR2_WDWN_Msk (0x1ul << DDRPHY_DX8GSR2_WDWN_Pos) /*!< DDRPHY_T::DX8GSR2: WDWN Mask */ + +#define DDRPHY_DX8GSR2_REERR_Pos (4) /*!< DDRPHY_T::DX8GSR2: REERR Position */ +#define DDRPHY_DX8GSR2_REERR_Msk (0x1ul << DDRPHY_DX8GSR2_REERR_Pos) /*!< DDRPHY_T::DX8GSR2: REERR Mask */ + +#define DDRPHY_DX8GSR2_REWN_Pos (5) /*!< DDRPHY_T::DX8GSR2: REWN Position */ +#define DDRPHY_DX8GSR2_REWN_Msk (0x1ul << DDRPHY_DX8GSR2_REWN_Pos) /*!< DDRPHY_T::DX8GSR2: REWN Mask */ + +#define DDRPHY_DX8GSR2_WEERR_Pos (6) /*!< DDRPHY_T::DX8GSR2: WEERR Position */ +#define DDRPHY_DX8GSR2_WEERR_Msk (0x1ul << DDRPHY_DX8GSR2_WEERR_Pos) /*!< DDRPHY_T::DX8GSR2: WEERR Mask */ + +#define DDRPHY_DX8GSR2_WEWN_Pos (7) /*!< DDRPHY_T::DX8GSR2: WEWN Position */ +#define DDRPHY_DX8GSR2_WEWN_Msk (0x1ul << DDRPHY_DX8GSR2_WEWN_Pos) /*!< DDRPHY_T::DX8GSR2: WEWN Mask */ + +#define DDRPHY_DX8GSR2_ESTAT_Pos (8) /*!< DDRPHY_T::DX8GSR2: ESTAT Position */ +#define DDRPHY_DX8GSR2_ESTAT_Msk (0xful << DDRPHY_DX8GSR2_ESTAT_Pos) /*!< DDRPHY_T::DX8GSR2: ESTAT Mask */ + +/**@}*/ /* DDRPHY_CONST */ +/**@}*/ /* end of DDRPHY register group */ + + +/**@}*/ /* end of REGISTER group */ + +#if defined ( __CC_ARM ) + #pragma no_anon_unions +#endif + +#endif /* __DDR32PHY_REG_H__ */ + diff --git a/bsp/nuvoton/libraries/ma35/Device/Nuvoton/MA35D1/Include/disp_reg.h b/bsp/nuvoton/libraries/ma35/Device/Nuvoton/MA35D1/Include/disp_reg.h new file mode 100644 index 0000000000..ece14b5249 --- /dev/null +++ b/bsp/nuvoton/libraries/ma35/Device/Nuvoton/MA35D1/Include/disp_reg.h @@ -0,0 +1,1432 @@ +/**************************************************************************//** +* @file disp_reg.h +* @brief LCD Display Controller driver header file +* +* SPDX-License-Identifier: Apache-2.0 +* @copyright (C) 2021 Nuvoton Technology Corp. All rights reserved. +*****************************************************************************/ + +#ifndef __DISP_REG_H__ +#define __DISP_REG_H__ + +#if defined ( __CC_ARM ) + #pragma anon_unions +#endif + +/** + @addtogroup REGISTER Control Register + @{ +*/ + +/** + @addtogroup DISP LCD Display Controller(DISP) + Memory Mapped Structure for DISP Controller +@{ */ + +typedef struct +{ + /** + * @var DISP_T::AQHiClockControl + * Offset: 0x00 Clock Control Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[1] |CLKDC_DIS |Disable DC clock. + * |[8:2] |FSCALE_VAL|Core clock frequency scale value. + * |[9] |FSCALE_CMD_LOAD|Core clock frequency scale value enable When writing a 1 to this bit, it updates the frequency scale factor with the value FSCALE_VAL[6:0] The bit must be set back to 0 after that If this bit is set and FSCALE_VAL=0 (an invalid combination), the HREADYOUT output signal will get stuck to 0. + * |[10] |DISABLE_RAM_CLOCK_GATING|Disables clock gating for rams. + * |[11] |DISABLE_DEBUG_REGISTERS|Disable debug registers If this bit is 1, debug registers are clock gated(reset=1). + * |[12] |SOFT_RESET|Soft resets the IP. + * |[13] |DISABLE_RAM_POWER_OPTIMIZATION|Disables ram power optimization. + * @var DISP_T::FrameBufferAddress0 + * Offset: 0x1400 Framebuffer Start Address Register. Starting address of the framebuffer. Note: This register is double buffered. + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[30:0] |ADDRESS |Framebuffer Start Address + * |[31] |TYPE |0 => SYSTEM 1 => VIRTUAL_SYSTEM + * @var DISP_T::FrameBufferStride0 + * Offset: 0x1408 Framebuffer Stride Register. Stride of the framebuffer in bytes. Note: This register is double buffered. + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[16:0] |STRIDE |Number of bytes from start of one line to next line. + * @var DISP_T::DisplayDitherConfig0 + * Offset: 0x1410 Display Dither Configuration Register. Configuration register for dithering. Note: This register is double buffered. + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[31] |ENABLE |Enabling dithering allows R8G8B8 modes to show better on panels with less bits- per-pixel Note: This field is double buffered. + * @var DISP_T::PanelConfig0 + * Offset: 0x1418 Panel Configuration Register. Note: This register is double buffered. + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[0] |DE |Data Enable enabled/disabled 0 => DISABLED 1 => ENABLED + * |[1] |DE_POLARITY|Data Enable polarity 0 => POSITIVE 1 => NEGATIVE + * |[4] |DATA_ENABLE|Data enabled/disabled 0 => DISABLED 1 => ENABLED + * |[5] |DATA_POLARITY|Data polarity 0 => POSITIVE 1 => NEGATIVE + * |[8] |CLOCK |Clock enabled/disabled 0 => DISABLED 1 => ENABLED + * |[9] |CLOCK_POLARITY|Clock polarity 0 => POSITIVE 1 => NEGATIVE + * @var DISP_T::DisplayDitherTableLow0 + * Offset: 0x1420 Display Dither Table Register. Note: This register is double buffered. + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[3:0] |Y0_X0 |Dither threshold value for x,y=0,0. + * |[7:4] |Y0_X1 |Dither threshold value for x,y=1,0. + * |[11:8] |Y0_X2 |Dither threshold value for x,y=2,0. + * |[15:12] |Y0_X3 |Dither threshold value for x,y=3,0. + * |[19:16] |Y1_X0 |Dither threshold value for x,y=0,1. + * |[23:20] |Y1_X1 |Dither threshold value for x,y=1,1. + * |[27:24] |Y1_X2 |Dither threshold value for x,y=2,1. + * |[31:28] |Y1_X3 |Dither threshold value for x,y=3,1. + * @var DISP_T::DisplayDitherTableHigh0 + * Offset: 0x1428 Display Dither Table Register. Note: This register is double buffered. + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[3:0] |Y2_X0 |Dither threshold value for x,y=0,2. + * |[7:4] |Y2_X1 |Dither threshold value for x,y=1,2. + * |[11:8] |Y2_X2 |Dither threshold value for x,y=2,2. + * |[15:12] |Y2_X3 |Dither threshold value for x,y=3,2. + * |[19:16] |Y3_X0 |Dither threshold value for x,y=0,3. + * |[23:20] |Y3_X1 |Dither threshold value for x,y=1,3. + * |[27:24] |Y3_X2 |Dither threshold value for x,y=2,3. + * |[31:28] |Y3_X3 |Dither threshold value for x,y=3,3. + * @var DISP_T::HDisplay0 + * Offset: 0x1430 Horizontal Total and Display End Counter Register. Note: This register is double buffered + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[14:0] |DISPLAY_END|Visible number of horizontal pixels. + * |[30:16] |TOTAL |Total number of horizontal pixels. + * @var DISP_T::HSync0 + * Offset: 0x1438 Horizontal Sync Counter Register. Note: This register is double buffered. + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[14:0] |START |Start of horizontal sync pulse. + * |[29:15] |END |End of horizontal sync pulse. + * |[30] |PULSE |Horizontal sync pulse control 0 => DISABLED 1 => ENABLED + * |[31] |POLARITY |Polarity of the horizontal sync pulse 0 => POSITIVE 1 => NEGATIVE + * @var DISP_T::VDisplay0 + * Offset: 0x1440 Vertical Total and Display End Counter Register. Note: This register is double buffered. + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[14:0] |DISPLAY_END|Visible number of vertical lines + * |[30:16] |TOTAL |Total number of vertical lines. + * @var DISP_T::VSync0 + * Offset: 0x1448 Vertical Sync Counter Register. Note: This register is double buffered. + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[14:0] |START |Start of the vertical sync pulse + * |[29:15] |END |End of the vertical sync pulse. + * |[30] |PULSE |Vertical sync pulse control 0 => DISABLED 1 => ENABLED + * |[31] |POLARITY |Polarity of the vertical sync pulse 0 => POSITIVE 1 => NEGATIVE + * @var DISP_T::DisplayCurrentLocation0 + * Offset: 0x1450 Display Current Location Register. Current x,y location of display controller. + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[15:0] |X |Current X location. + * |[31:16] |Y |Current Y location. + * @var DISP_T::GammaIndex0 + * Offset: 0x1458 Gamma Table Index Register. Index into gamma table. See GammaData for more information. + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[7:0] |INDEX |Index into gamma table. + * @var DISP_T::GammaData0 + * Offset: 0x1460 Gamma Data Translation Register. Translation values for the gamma table. When this register gets written, the data gets stored in the gamma table at the index specified by the GammaIndex register. After the register is written, the index gets incremented. + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[9:0] |BLUE |Blue translation value. + * |[19:10] |GREEN |Green translation value. + * |[29:20] |READ |Red translation value. + * @var DISP_T::CursorConfig + * Offset: 0x1468 Cursor Configuration Register. + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[1:0] |FORMAT |Format of the cursor Note: This field is double buffered. + * |[4] |DISPLAY |Display Controller owning the cursor. + * |[12:8] |HOT_SPOT_Y|Vertical offset to cursor hotspot Note: This field is double buffered. + * |[20:16] |HOT_SPOT_X|Horizontal offset to cursor hotspot Note: This field is double buffered. + * @var DISP_T::CursorAddress + * Offset: 0x146C Cursor Address Register. Address of the cursor shape. Note: This register is double buffered. + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[30:0] |ADDRESS |Cursor Address + * |[31] |TYPE |0 => SYSTEM 1 => VIRTUAL_SYSTEM + * @var DISP_T::CursorLocation + * Offset: 0x1470 Cursor Location Register. Location of the cursor on the owning display. Note: This register is double buffered. + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[14:0] |X |X location of cursor's hotspot. + * |[30:16] |Y |Y location of cursor's hotspot. + * @var DISP_T::CursorBackground + * Offset: 0x1474 Masked Cursor Background Color Register. The background color for Masked cursors. Note: This register is double buffered. + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[7:0] |BLUE |Blue value. + * |[15:8] |GREEN |Green value. + * |[23:16] |RED |Red value. + * @var DISP_T::CursorForeground + * Offset: 0x1478 Masked Cursor Foreground Color Register. The foreground color for Masked cursors. Note: This register is double buffered. + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[7:0] |BLUE |Blue value. + * |[15:8] |GREEN |Green value. + * |[23:16] |RED |Red value. + * @var DISP_T::DisplayIntr + * Offset: 0x147C Display Interrupt Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[0] |DISP0 |Display0 interrupt(read only) + * @var DISP_T::DisplayIntrEnable + * Offset: 0x1480 Display Interrupt Enable Register. The interrupt enable register for display_0. Note: Interrupt enable for register DisplayIntr. + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[0] |DISP0 |Display0 interrupt enable (read only) + * @var DISP_T::CursorModuleClockGatingControl + * Offset: 0x1484 Clock Gating Control for Cursor Register. Module level clock gating control for cursor. + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[0] |DISABLE_MODULE_CLOCK_GATING_CURSOR|Disable module clock gating cursor 0 => ENABLED 1 => DISABLED + * @var DISP_T::GeneralConfig0 + * Offset: 0x14B0 General Miscellaneous Configuration Register. Misc option configuration. Note: This register is double buffered. + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[1:0] |ENDIAN_CONTROL|Control endian swapping 0 => NO_SWAP 1 => SWAP_WORD 2 => SWAP_DWORD 3 => SWAP_DDWORD + * |[2] |STALL_OUTPUT_WHEN_UNDERFLOW|If enabled, when FIFO underflow happens, output is stalled 0 => DISABLED 1 => ENABLED + * |[3] |DISABLE_IDLE|Disable idle signal 0 => DISABLED 1 => ENABLED + * @var DISP_T::DpiConfig0 + * Offset: 0x14B8 DPI Configuration Register. The configuration register for DPI output. Note: This register is double buffered. + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[2:0] |DPI_DATA_FORMAT|DPI interface data format Refer to DPI spec 'Interface color coding' for details 0 => D16CFG1 1 => D16CFG2 2 => D16CFG3 3 => D18CFG1 4 => D18CFG2 5 => D24 + * @var DISP_T::DebugCounterSelect0 + * Offset: 0x14D0 Debug Counter Selection Register. + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[7:0] |SELECT |Write a value to this field to pick up from 0~255 counters Then the counter will be on DebugCounterValue 00 => TOTAL_AXI_VIDEO_RD_REQ_CNT * video read request number * 01 => TOTAL_AXI_VIDEO_RD_LAST_CNT * video read return data last number * 02 => TOTAL_AXI_VIDEO_REQ_BURST_CNT * video number of 16 byte burst requests bytes * 03 => TOTAL_AXI_VIDEO_RD_BURST_CUNT * video number of 16 byte burst read return data * 04 => TOTAL_PIXEL_CNT * total pixels sent * 05 => TOTAL_FRAME_CNT * total frames sent * 06 => TOTAL_INPUT_DBI_CMD_CNT * total DBI input command * 07 => TOTAL_OUTPUT_DBI_CMD_CNT * total DBI output command * 08 => DEBUG_SIGNALS0 * debug signals * 09 => TOTAL_AXI_OVERLAY0_RD_REQ_CNT * overlay read request number * 0A => TOTAL_AXI_OVERLAY0_RD_LAST_CNT * overlay read return data last number * 0B => TOTAL_AXI_OVERLAY0_REQ_BURST_CNT * overlay number of 16 byte bursts of request bytes * 0C => TOTAL_AXI_OVERLAY0_RD_BURST_CUNT * overlay number of 16 bytes bursts of read return data * 0D => DEBUG_SIGNALS_FREE_POOL 0E => DEBUG_SIGNALS_INFOBUF_RD 0F => DEBUG_SIGNALS_INFOBUF_WR0 10 => DEBUG_SIGNALS_INFOBUF_WR1 11 => DEBUG_SIGNALS_INFOBUF_WR2 12 => DEBUG_SIGNALS_INFOBUF_WR3 13 => DEBUG_SIGNALS_OVERLAY0_FREE_POOL 14 => DEBUG_SIGNALS_OVERLAY0_INFOBUF_RD 15 => DEBUG_SIGNALS_OVERLAY0_INFOBUF_WR0 16 => DEBUG_SIGNALS_OVERLAY0_INFOBUF_WR1 17 => DEBUG_SIGNALS_OVERLAY0_INFOBUF_WR2 18 => DEBUG_SIGNALS_OVERLAY0_INFOBUF_WR3 19 => OVERLAY_BLEND_DEBUGSIGNALS 1A => CURSOR_BLEND_DEBUGSIGNALS 1C => VIDEO_WALKER_DEBUGSIGNALS_1 1D => VIDEO_WALKER_DEBUGSIGNALS_2 1E => VIDEO_WALKER_DEBUGSIGNALS_3 1F => OVERLAY_WALKER_DEBUGSIGNALS_1 20 => OVERLAY_WALKER_DEBUGSIGNALS_2 21 => OVERLAY_WALKER_DEBUGSIGNALS_3 FF => RESET_ALL_DEBUG_COUNTERS * Reset all debug counters *. + * @var DISP_T::DebugCounterValue0 + * Offset: 0x14D8 Debug Counter Value Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[31:0] |VALUE |Selected debug counter value + * @var DISP_T::FrameBufferColorKey0 + * Offset: 0x1508 Framebuffer Color Key Start Address Register. Start of color key range of framebuffer. Note: This register is double buffered. + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[7:0] |BLUE |BLUE value + * |[15:8] |GREEN |GREEN value + * |[23:16] |RED |RED value + * |[31:24] |ALPHA |ALPHA value + * @var DISP_T::FrameBufferColorKeyHigh0 + * Offset: 0x1510 Framebuffer Color Key End Address Register. End of color key range of framebuffer. Note: This register is double buffered. + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[7:0] |BLUE |BLUE value + * |[15:8] |GREEN |GREEN value + * |[23:16] |RED |RED value + * |[31:24] |ALPHA |ALPHA value + * @var DISP_T::FrameBufferConfig0 + * Offset: 0x1518 Framebuffer Configuration Register. Framebuffer attribute configuration. Note: This register is double buffered. Some fields are double buffered. + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[0] |OUTPUT |When Output is enabled, pixels will be displayed When Output is disabled, all pixels will be black This allows a panel to have the correct timing but without any pixels Note: This field is double buffered 0 => DISABLED 1 => ENABLED. + * |[2] |GAMMA |When Gamma is enabled, the R, G, and B channels will be routed through the Gamma LUT to perform gamma correction Note: This field is double buffered 0 => DISABLED 1 => ENABLED. + * |[3] |VALID |The valid field defines whether we can copy a new set of registers at the next VBLANK or not This ensures a frame will always start with a valid working set if this register is programmed last, which reduces the need for SW to wait for the start of a VBLANK signal in order to ensure all states are loaded before the next VBLANK 0 => WORKING 1 => PENDING. + * |[4] |RESET |Enable reset for the display controller + * | | |0: See below for DPI + * | | |For DBI,this field should be 0 + * | | |1: RESET + * | | |Enable DPI timing, start a DPI transfer + * | | |Write 0 to this bit to reset the display controller, then configure the other registers and lastly write a 1 to this bit to let the display controller start + * | | |When the display controller starts, it begins at VBLANK_START, and all registers get flopped to the working set at VSYNC_END + * | | |Counters will be reset to the end of HSYNC and VSYNC + * | | |(Refer the Timing Diagram provided in the Hardware Feature document) + * | | |For DBI, do not write 1 to this field + * | | |Use DbiReset DBI_IF_LEVEL_RESET instead + * | | |This bit is WRITE ONLY. + * | | |1 => RESET. + * |[5] |UNDERFLOW |0: NO 1: YES When the display FIFO underflows, this bit gets set to one Reading this register will reset it back to zero This field is READ ONLY 0 => NO 1 => YES. + * |[6] |FLIP_IN_PROGRESS|0: NO 1: YES When the framebuffer address gets written to, this bit gets set to one It will be reset to zero at the start of the next VBLANK when the registers gets copied into the working set This field is (READ ONLY) 0 => NO 1 => YES. + * |[8] |CLEAR |When enabled, the pixel value of the framebuffer comes from FrameBufferClearValue; otherwise, the pixel value comes from memory 0 => DISABLED 1 => ENABLED + * |[10:9] |TRANSPARENCY|Transparency of framebuffer 0 => OPAQUE 1 => MASK 2 => KEY + * |[16:14] |YUV |YUV standard 1 => SELECT_709 * BT709 * 3 => SELECT_2020 * BT2020 * + * |[24:23] |SWIZZLE |0 => ARGB 1 => RGBA 2 => ABGR 3 => BGRA + * |[25] |UV_SWIZZLE|UV swizzle type + * |[31:26] |FORMAT |The format of the framebuffer 00 => X4R4G4B4 01 => A4R4G4B4 02 => X1R5G5B5 03 => A1R5G5B5 04 => R5G6B5 05 => X8R8G8B8 06 => A8R8G8B8 07 => YUY2 08 => UYVY 09 => INDEX8 0A => MONOCHROME 0F => YV12 10 => A8 11 => NV12 12 => NV16 13 => RG16 14 => R8 15 => NV12_10BIT 16 => A2R10G10B10 17 => NV16_10BIT 18 => INDEX1 19 => INDEX2 1A => INDEX4 1B => P010 1C => NV12_10BIT_L1 1D => NV16_10BIT_L1 + * @var DISP_T::FrameBufferBGColor0 + * Offset: 0x1528 Framebuffer Background Color Register. Background color used when a pixel from the framebuffer falls outside of the range of color key. + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[7:0] |BLUE |BLUE value + * |[15:8] |GREEN |GREEN value + * |[23:16] |RED |RED value + * |[31:24] |ALPHA |ALPHA value + * @var DISP_T::FrameBufferUPlanarAddress0 + * Offset: 0x1530 Framebuffer Second Plane U Start Address Register. Starting address of the second planar (often the U plane) of the framebuffer if one exists. + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[30:0] |ADDRESS |Framebuffer Second Plane U Start Address + * |[31] |TYPE |0 => SYSTEM 1 => VIRTUAL_SYSTEM + * @var DISP_T::FrameBufferVPlanarAddress0 + * Offset: 0x1538 Framebuffer Third Plane V Start Address Register. Starting address of the third planar (often the V plane) of the framebuffer if one exists. Note: This register is double buffered. + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[30:0] |ADDRESS |Framebuffer Third Plane V Start Address + * |[31] |TYPE |0 => SYSTEM 1 => VIRTUAL_SYSTEM + * @var DISP_T::OverlayConfig0 + * Offset: 0x1540 Overlay Configuration Register. Overlay attributes control. Note: This register is double buffered. + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[1:0] |TRANSPARENCY|Transparency of the overlay 0 => OPAQUE 1 => MASK 2 => KEY + * |[7:5] |YUV |YUV standard + * | | |1 => SELECT_709 * BT709 * 3 => SELECT_2020 * BT2020 *. + * |[14:13] |SWIZZLE |0 => ARGB 1 => RGBA 2 => ABGR 3 => BGRA + * |[15] |UV_SWIZZLE|UV swizzle type. + * |[21:16] |FORMAT |The format of the overlay + * | | |00 => X4R4G4B4 01 => A4R4G4B4 02 => X1R5G5B5 03 => A1R5G5B5 04 => R5G6B5 05 => X8R8G8B8 06 => A8R8G8B8 07 => YUY2 08 => UYVY 09 => INDEX8 0A => MONOCHROME 0F => YV12 10 => A8 11 => NV12 12 => NV16 13 => RG16 14 => R8 15 => NV12_10BIT 16 => A2R10G10B10 17 => NV16_10BIT 18 => INDEX1 19 => INDEX2 1A => INDEX4 1B => P010 1C => NV12_10BIT_L1 1D => NV16_10BIT_L1. + * |[23] |UNDERFLOW |When the overlay FIFO underflows, this bit gets set to one Reading this register will reset it back to zero 0 => NO 1 => YES. + * |[24] |ENABLE |Enable this overlay layer 0 => DISABLE 1 => ENABLE + * |[25] |CLEAR |When enabled, the pixel value of the overlay comes from OverlayClearValue; otherwise the pixel value comes from memory 0 => DISABLED 1 => ENABLED + * @var DISP_T::OverlayAlphaBlendConfig0 + * Offset: 0x1580 Overlay Alpha Blending Configuration Register. Note: This register is double buffered. + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[0] |SRC_ALPHA_MODE|0 => NORMAL 1 => INVERSED + * |[1] |DISABLE_ALPHA_BLEND|0 => DISABLED 1 => ENABLED + * |[4:3] |SRC_GLOBAL_ALPHA_MODE|0 => NORMAL 1 => GLOBAL 2 => SCALED + * |[7:5] |SRC_BLENDING_MODE|0 => ZERO 1 => ONE 2 => NORMAL 3 => INVERSED 4 => COLOR 5 => COLOR_INVERSED 6 => SATURATED_ALPHA 7 => SATURATED_DEST_ALPHA + * |[8] |SRC_ALPHA_FACTOR|Src Blending factor is calculated from Src alpha 0 => DISABLED 1 => ENABLED + * |[9] |DST_ALPHA_MODE|0 => NORMAL 1 => INVERSED + * |[11:10] |DST_GLOBAL_ALPHA_MODE|0 => NORMAL 1 => GLOBAL 2 => SCALED + * |[14:12] |DST_BLENDING_MODE|0 => ZERO 1 => ONE 2 => NORMAL 3 => INVERSED 4 => COLOR 5 => COLOR_INVERSED 6 => SATURATED_ALPHA 7 => SATURATED_DEST_ALPHA + * |[15] |DST_ALPHA_FACTOR|Dst Blending factor is calculated from Dst alpha 0 => DISABLED 1 => ENABLED + * @var DISP_T::OverlayAddress0 + * Offset: 0x15C0 Overlay Start Address Register. Starting address of the overlay. Note: This register is double buffered. + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[30:0] |ADDRESS |Overlay Start Address + * |[31] |TYPE |0 => SYSTEM 1 => VIRTUAL_SYSTEM + * @var DISP_T::OverlayStride0 + * Offset: 0x1600 Overlay Stride Register. Stride of the overlay in bytes. Note: This register is double buffered. + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[16:0] |STRIDE |Number of bytes from the start of one line to next line. + * @var DISP_T::OverlayTL0 + * Offset: 0x1640 Overlay Origin Register. Top left coordinate of the panel pixel where the overlay should start. Be aware there is no panning inside the overlay. Note: This register is double buffered + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[14:0] |X |Left boundary of overlay window. + * |[29:15] |Y |Top boundary of overlay window. + * @var DISP_T::OverlayBR0 + * Offset: 0x1680 Overlay End Register. Bottom right coordinate of the panel pixel where the overlay should end. The border is inclusive. Note: This register is double buffered. + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[14:0] |X |Right boundary of overlay. + * |[29:15] |Y |Bottom boundary of overlay. + * @var DISP_T::OverlaySrcGlobalColor0 + * Offset: 0x16C0 Overlay Source Global Color Register. Color value used when alpha blending process is configured to use global color for source. Note: This register is double buffered. + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[7:0] |BLUE |BLUE value + * |[15:8] |GREEN |GREEN value + * |[23:16] |RED |RED value + * |[31:24] |ALPHA |ALPHA value + * @var DISP_T::OverlayDstGlobalColor0 + * Offset: 0x1700 Overlay Destination Global Color Register. Color value used when alpha blending process is configured to use global color for destination. Note: This register is double buffered. + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[7:0] |BLUE |BLUE value + * |[15:8] |GREEN |GREEN value + * |[23:16] |RED |RED value + * |[31:24] |ALPHA |ALPHA value + * @var DISP_T::OverlayColorKey0 + * Offset: 0x1740 Overlay Color Key Start Address Register. Start of color key range for overlay. Note: This register is double buffered. + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[7:0] |BLUE |BLUE value + * |[15:8] |GREEN |GREEN value + * |[23:16] |RED |RED value + * |[31:24] |ALPHA |ALPHA value + * @var DISP_T::OverlayColorKeyHigh0 + * Offset: 0x1780 Overlay Color Key End Address Register. End of color key range for overlay. Note: This register is double buffered. + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[7:0] |BLUE |BLUE value + * |[15:8] |GREEN |GREEN value + * |[23:16] |RED |RED value + * |[31:24] |ALPHA |ALPHA value + * @var DISP_T::OverlaySize0 + * Offset: 0x17C0 Overlay Window Size Register. Window size of the overlay buffer in memory - in pixels. Note: This register is double buffered. + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[14:0] |WIDTH |Overlay width + * |[29:15] |HEIGHT |Overlay height + * @var DISP_T::FrameBufferUStride0 + * Offset: 0x1800 Framebuffer Second Plane U Stride Register. Stride of the second planar (often the U plane) of the framebuffer if one exists. Note: This register is double buffered. + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[16:0] |STRIDE |Number of bytes from the start of one line to next line. + * @var DISP_T::FrameBufferVStride0 + * Offset: 0x1808 Framebuffer Third Plane V Stride Register. Stride of the third planar (often the V plane) of the framebuffer if one exists. Note: This register is double buffered. + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[16:0] |STRIDE |Number of bytes from the start of one line to next line. + * @var DISP_T::FrameBufferSize0 + * Offset: 0x1810 Framebuffer Size Register. Window size of the framebuffer in memory - in pixels. Note: This register is double buffered. + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[14:0] |WIDTH |Frame width + * |[29:15] |HEIGHT |Frame height + * @var DISP_T::IndexColorTableIndex0 + * Offset: 0x1818 Index Color Table Index Register. Index into index color table. See IndexColorTableData for more information. + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[7:0] |INDEX |index into index color table. + * @var DISP_T::IndexColorTableData0 + * Offset: 0x1820 Index Color Table Data Translation Register. Translation values for the index color table. When this register gets written, the data gets stored in the index color table at the index specified by the IndexColorTableIndex register. After the register is written, the index gets incremented. Note: This register is double buffered. + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[7:0] |BLUE |BLUE value + * |[15:8] |GREEN |GREEN value + * |[23:16] |RED |RED value + * |[31:24] |ALPHA |ALPHA value + * @var DISP_T::OverlayUPlanarAddress0 + * Offset: 0x1840 Overlay Second Plane U Start Address Register. Address of the second planar (often U plane) of the overlay if one exists. Note: This register is double buffered. + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[30:0] |ADDRESS |Overlay Third Plane V Start Address + * |[31] |TYPE |0 => SYSTEM 1 => VIRTUAL_SYSTEM + * @var DISP_T::OverlayVPlanarAddress0 + * Offset: 0x1880 Overlay Third Plane V Start Address Register. Address of the third planar (often V plane) of the overlay if one exists. Note: This register is double buffered. + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[30:0] |ADDRESS |Overlay Second Plane U Stride + * |[31] |TYPE |0 => SYSTEM 1 => VIRTUAL_SYSTEM + * @var DISP_T::OverlayUStride0 + * Offset: 0x18C0 Overlay Second Plane U Stride Register. Stride of the second planar of the overlay if one exists. Note: This register is double buffered. + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[16:0] |STRIDE |Number of bytes from the start of one line to next line. + * @var DISP_T::OverlayVStride0 + * Offset: 0x1900 Overlay Third Plane V Stride Register. Stride of the third planar of the overlay if one exists. Note: This register is double buffered. + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[16:0] |STRIDE |Number of bytes from start of one line to next line. + * @var DISP_T::OverlayClearValue0 + * Offset: 0x1940 Overlay Clear Value Register. Clear value used when OverlayConfig.Clear is enabled. Format is A8R8G8B8. Note: This register is double buffered. + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[7:0] |BLUE |BLUE value + * |[15:8] |GREEN |GREEN value + * |[23:16] |RED |RED value + * |[31:24] |ALPHA |ALPHA value + * @var DISP_T::OverlayIndexColorTableIndex0 + * Offset: 0x1980 Overlay Index Color Table Index Register. Index into overlay index color table. See OverlayIndexColorTableData for more information. + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[7:0] |INDEX |Index into index color table. + * @var DISP_T::OverlayIndexColorTableData0 + * Offset: 0x19C0 Index Color Table Data Translation Register. Translation values for the index color table of the overlay. When this register gets written, the data gets stored in the index color table at the index specified by the OverlayIndexColorTableIndex register. After the register is written, the index gets incremented. Note: This register is double buffered. + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[7:0] |BLUE |BLUE value + * |[15:8] |GREEN |GREEN value + * |[23:16] |RED |RED value + * |[31:24] |ALPHA |ALPHA value + * @var DISP_T::FrameBufferClearValue0 + * Offset: 0x1A18 Framebuffer Clear Value Register. Clear value used when FrameBufferConfig. Clear is enabled, format is A8R8G8B8. Note: This register is double buffered. + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[7:0] |BLUE |BLUE value + * |[15:8] |GREEN |GREEN value + * |[23:16] |RED |RED value + * |[31:24] |ALPHA |ALPHA value + * @var DISP_T::ModuleClockGatingControl0 + * Offset: 0x1A28 Clock Gating Module Control Register. Module level clock gating control for video and overlay. + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[0] |DISABLE_MODULE_CLOCK_GATING_VIDEO|Disable module clock gating video 0 => ENABLE 1 => DISABLE. + * |[1] |DISABLE_MODULE_CLOCK_GATING_OVERLAY0|Disable module clock gating overlay0 0 => ENABLE 1 => DISABLE. + * |[9] |DISABLE_MODULE_CLOCK_GATING_WB_FIFO|Disable module clock gating WBFifo 0 => ENABLE 1 => DISABLE. + * @var DISP_T::LatencyCounter0 + * Offset: 0x1A30 Latency Counter Register. + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[31:0] |COUNTER |Latency counter value which is used to judge whether latency is low or high. + * @var DISP_T::Qos0 + * Offset: 0x1A38 Quality of Service Latency Value Register. + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[3:0] |LOW |If latency low, will send low value. + * |[7:4] |HIGH |If latency high, will send high value. + * @var DISP_T::MpuIntfCmd0 + * Offset: 0x1C40 MPU Command Configuration Register. + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[15:0] |REG_DATA |Register address or register configured parameter. + * |[26:24] |READ_COUNT|0 is invalid value, one read operation returns 1 data at least, Max value is 5 It is designed to prepare 5 registers to save returned data. + * |[29] |START |HW generates a pulse while writing 1 to this field, then HW starts to send display data to the LCD. + * |[31:30] |CMD |0: Not a valid command, HW ignores the CMD/REGDATA/READCOUNT field Usage: only want to trigger HW, don't configure other fields 1: Write register by MPU interface 2: Write register parameter by MPU interface 3: Read register by MPU interface. + * @var DISP_T::MpuIntfReadPara00 + * Offset: 0x1C48 MPU Read Parameter0 Register. + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[17:0] |DATA |Read register returned parameter0. + * @var DISP_T::MpuIntfReadPara10 + * Offset: 0x1C50 MPU Read Parameter1 Register. + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[17:0] |DATA |Read register returned parameter1. + * @var DISP_T::MpuIntfReadPara20 + * Offset: 0x1C58 MPU Read Parameter2 Register. + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[17:0] |DATA |Read register returned parameter2. + * @var DISP_T::MpuIntfReadPara30 + * Offset: 0x1C60 MPU Read Parameter3 Register. + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[17:0] |DATA |Read register returned parameter3. + * @var DISP_T::MpuIntfReadPara40 + * Offset: 0x1C68 MPU Read Parameter4 Register. + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[17:0] |DATA |Read register returned parameter4. + * @var DISP_T::MpuIntfReadStatus0 + * Offset: 0x1C70 MPU Read Parameter Status Register. + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[0] |DATA |Returned parameter readiness + * | | |0 = UNREADY + * | | |The returned parameters of all read registers are not ready + * | | |1 = READY + * | | |The returned parameters of all read registers are ready. + * @var DISP_T::MpuIntfConfig0 + * Offset: 0x1C78 MPU Interface Configuration Register. + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[0] |REGISTER_MODE|0: 8 bit register mode, only MpuIntfCmd[7:0] are valid Only send 8 bits valid data each time to LCD by MPU Interface 1: 16 bit register mode, only MpuIntfCmd[15:0] are valid, Only send 16 bits valid data each time to the LCD by MPU Interface 0 = MODE_8_BIT 1 = MODE_16_BIT + * |[2:1] |DATA_BUS_WIDTH|MPU interface bus width 0 = WIDTH_8_BIT 1 = WIDTH_9_BIT 2 = WIDTH_16_BIT 3 = WIDTH_18_BIT + * |[3] |DATA_BUS_MODE|0 = MODE0. Mode0: 8-bit:DB[7:0]; 9-bit:DB[8:0]; 16-bit:DB[15:0]; 18-bit:DB[17:0], 1 = MODE1. Mode1: 8-bit:DB[17:10]; 9-bit:DB[17:9]; 16-bit:{DB[17:10],DB[8:1]}; 18-bit:DB[17:0]. + * |[4] |INTERFACE_MODE|System Interface. + * |[5] |ENABLE_VSYNC|0: Disable; 1: Enable VSYNC interface 0 = DISABLE 1 = ENABLE + * |[6] |VSYNC_POLARITY|VSYNC signal is negative or positive value 0 = NEGATIVE 1 = POSITIVE + * |[7] |ENABLE_TE |0: Disable; 1: Enable TE interface 0 = DISABLE 1 = ENABLE + * |[8] |TE_POLARITY|TE signal is positive or negative value 0 = POSITIVE 1 = NEGATIVE + * |[9] |DCX_POLARITY|DCX polarity for command and data 0 = MODE0. 0-command, 1-data 1 = MODE1. 1-command, 0-data. + * |[10] |DATA_MODE24_BIT|16 bit data bus, 24 bit data output 0 = MODE0. 0: 2 pixels per 3 transfers 1 = MODE1. 1: 1 pixel per 2 transfers. + * |[11] |INTERFACE_RESET|Write 1 to this field, HW will reset the MPU interface. + * |[12] |ENABLE_MPU_INTF|O:Disable; 1: Enable MPU interface 0 = DISABLE 1 = ENABLE + * @var DISP_T::MpuIntfFrame0 + * Offset: 0x1C80 MPU Frame Configuration Register. Note: This register is double buffered. + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[0] |FRAME_UPDATE|0: When using VSync interface/TE mode, if this bit is 0, this frame data won't be updated 1: When using VSync interface/TE mode, if this bit is 1, this frame data will be updated 0 => NO 1 => YES. + * |[2:1] |DATA_FORMAT|0: 16 bit format R5G6B5 1: 18 bit format R6G6B6 2: 24 bit format R8G8B8. 3: Reserved 0 => R5G6B5 1 => R6G6B6 2 => R8G8B8 + * |[3] |MPU_WRITE_BACK|0: Disable MPU data write back 1: Enable MPU interface data write back 0 => DISABLE 1 => ENABLE. + * @var DISP_T::MpuIntfACWrI800 + * Offset: 0x1C88 MPU Write AC Characteristics I80 Register. + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[9:0] |WR_PERIOD_I80|I80 system write period cycle number Minimum number is 3 Default number is 0, 0 means 1024 cycle number Cycle unit is pixel clock. + * |[19:10] |WRX_ASSERT|I80 system WRX assert cycle number Minimum number is 1 Default number is 0, 0 means 1024 cycle number Cycle unit is pixel clock. + * |[29:20] |WRX_DE_ASSERT|I80 system WRX de-assert cycle number Minimum number is 1 Default number is 0, 0 means 1024 cycle number Cycle unit is pixel clock + * @var DISP_T::MpuIntfACRdI800 + * Offset: 0x1C90 MPU Read AC Characteristics I80 Register. + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[9:0] |RD_PERIOD_I80|I80 system read period cycle number Minimum number is 3 Default number is 0, 0 means 1024 cycle number Cycle unit is pixel clock. + * |[19:10] |RDX_ASSERT|I80 system RDX assert cycle number Minimum number is 1 Default number is 0, 0 means 1024 cycle number Cycle unit is pixel clock. + * |[29:20] |RDX_DE_ASSERT|I80 system RDX de-assert cycle number Minimum number is 1 Default number is 0, 0 means 1024 cycle number Cycle unit is pixel clock. + * @var DISP_T::MpuIntfACWrM680 + * Offset: 0x1C98 MPU Write AC Characteristics M68 Register. + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[9:0] |WR_PERIOD_M68|M68 system write period cycle number Minimum number is 3 Default number is 0, 0 means 1024 cycle number Cycle unit is pixel clock. + * |[19:10] |WR_EASSERT|M68 system write E assert cycle number Minimum number is 1 Default number is 0, 0 means 1024 cycle number Cycle unit is pixel clock. + * |[29:20] |WR_EDE_ASSERT|M68 system write E de-assert cycle number Minimum number is 1 Default number is 0, 0 means 1024 cycle number Cycle unit is pixel clock. + * @var DISP_T::MpuIntfACRdM680 + * Offset: 0x1CA0 MPU Read AC Characteristics M68 Register. + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[9:0] |RD_PERIOD_I80|M68 system read period cycle number Minimum number is 3 Default number is 0, 0 means 1024 cycle number Cycle unit is pixel clock. + * |[19:10] |RDX_ASSERT|M68 system RDX assert cycle number Minimum number is 1 Default number is 0, 0 means 1024 cycle number Cycle unit is pixel clock. + * |[29:20] |RDX_DE_ASSERT|M68 system RDX de-assert cycle number Minimum number is 1 Default number is 0, 0 means 1024 cycle number Cycle unit is pixel clock. + * @var DISP_T::MpuIntfACVsyncCSX0 + * Offset: 0x1CA8 MPU CSX Assert Register. + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[9:0] |CSX_ASSERT|Add delay between VSYNC-high and CSX- low This field specifies how many transfer-one-pixel period. + */ + __IO uint32_t AQHiClockControl; /*!< [0x0000] Clock Control Register */ + __I uint32_t RESERVE0[1279]; + __IO uint32_t FrameBufferAddress0; /*!< [0x1400] Framebuffer Start Address Register. Starting address of the framebuffer. Note: This register is double buffered. */ + __I uint32_t RESERVE1[1]; + __IO uint32_t FrameBufferStride0; /*!< [0x1408] Framebuffer Stride Register. Stride of the framebuffer in bytes. Note: This register is double buffered. */ + __I uint32_t RESERVE2[1]; + __IO uint32_t DisplayDitherConfig0; /*!< [0x1410] Display Dither Configuration Register. Configuration register for dithering. Note: This register is double buffered. */ + __I uint32_t RESERVE3[1]; + __IO uint32_t PanelConfig0; /*!< [0x1418] Panel Configuration Register. Note: This register is double buffered. */ + __I uint32_t RESERVE4[1]; + __IO uint32_t DisplayDitherTableLow0; /*!< [0x1420] Display Dither Table Register. Note: This register is double buffered. */ + __I uint32_t RESERVE5[1]; + __IO uint32_t DisplayDitherTableHigh0; /*!< [0x1428] Display Dither Table Register. Note: This register is double buffered. */ + __I uint32_t RESERVE6[1]; + __IO uint32_t HDisplay0; /*!< [0x1430] Horizontal Total and Display End Counter Register. Note: This register is double buffered */ + __I uint32_t RESERVE7[1]; + __IO uint32_t HSync0; /*!< [0x1438] Horizontal Sync Counter Register. Note: This register is double buffered. */ + __I uint32_t RESERVE8[1]; + __IO uint32_t VDisplay0; /*!< [0x1440] Vertical Total and Display End Counter Register. Note: This register is double buffered. */ + __I uint32_t RESERVE9[1]; + __IO uint32_t VSync0; /*!< [0x1448] Vertical Sync Counter Register. Note: This register is double buffered. */ + __I uint32_t RESERVE10[1]; + __I uint32_t DisplayCurrentLocation0; /*!< [0x1450] Display Current Location Register. Current x,y location of display controller. */ + __I uint32_t RESERVE11[1]; + __O uint32_t GammaIndex0; /*!< [0x1458] Gamma Table Index Register. Index into gamma table. See GammaData for more information. */ + __I uint32_t RESERVE12[1]; + __O uint32_t GammaData0; /*!< [0x1460] Gamma Data Translation Register. Translation values for the gamma table. When this register gets written, the data gets stored in the gamma table at the index specified by the GammaIndex register. After the register is written, the index gets incremented. */ + __I uint32_t RESERVE13[1]; + __IO uint32_t CursorConfig; /*!< [0x1468] Cursor Configuration Register. */ + __IO uint32_t CursorAddress; /*!< [0x146c] Cursor Address Register. Address of the cursor shape. Note: This register is double buffered. */ + __IO uint32_t CursorLocation; /*!< [0x1470] Cursor Location Register. Location of the cursor on the owning display. Note: This register is double buffered. */ + __IO uint32_t CursorBackground; /*!< [0x1474] Masked Cursor Background Color Register. The background color for Masked cursors. Note: This register is double buffered. */ + __IO uint32_t CursorForeground; /*!< [0x1478] Masked Cursor Foreground Color Register. The foreground color for Masked cursors. Note: This register is double buffered. */ + __I uint32_t DisplayIntr; /*!< [0x147c] Display Interrupt Register */ + __IO uint32_t DisplayIntrEnable; /*!< [0x1480] Display Interrupt Enable Register. The interrupt enable register for display_0. Note: Interrupt enable for register DisplayIntr. */ + __IO uint32_t CursorModuleClockGatingControl; /*!< [0x1484] Clock Gating Control for Cursor Register. Module level clock gating control for cursor. */ + __IO uint32_t DbiConfig0; /*!< [0x1488] Wayne Undertable register */ + __I uint32_t RESERVE14[9]; + __IO uint32_t GeneralConfig0; /*!< [0x14b0] General Miscellaneous Configuration Register. Misc option configuration. Note: This register is double buffered. */ + __I uint32_t RESERVE15[1]; + __IO uint32_t DpiConfig0; /*!< [0x14b8] DPI Configuration Register. The configuration register for DPI output. Note: This register is double buffered. */ + __I uint32_t RESERVE16[5]; + __IO uint32_t DebugCounterSelect0; /*!< [0x14d0] Debug Counter Selection Register. */ + __I uint32_t RESERVE17[1]; + __I uint32_t DebugCounterValue0; /*!< [0x14d8] Debug Counter Value Register */ + __I uint32_t RESERVE18[11]; + __IO uint32_t FrameBufferColorKey0; /*!< [0x1508] Framebuffer Color Key Start Address Register. Start of color key range of framebuffer. Note: This register is double buffered. */ + __I uint32_t RESERVE19[1]; + __IO uint32_t FrameBufferColorKeyHigh0; /*!< [0x1510] Framebuffer Color Key End Address Register. End of color key range of framebuffer. Note: This register is double buffered. */ + __I uint32_t RESERVE20[1]; + __IO uint32_t FrameBufferConfig0; /*!< [0x1518] Framebuffer Configuration Register. Framebuffer attribute configuration. Note: This register is double buffered. Some fields are double buffered. */ + __I uint32_t RESERVE21[3]; + __IO uint32_t FrameBufferBGColor0; /*!< [0x1528] Framebuffer Background Color Register. Background color used when a pixel from the framebuffer falls outside of the range of color key. */ + __I uint32_t RESERVE22[1]; + __IO uint32_t FrameBufferUPlanarAddress0; /*!< [0x1530] Framebuffer Second Plane U Start Address Register. Starting address of the second planar (often the U plane) of the framebuffer if one exists. */ + __I uint32_t RESERVE23[1]; + __IO uint32_t FrameBufferVPlanarAddress0; /*!< [0x1538] Framebuffer Third Plane V Start Address Register. Starting address of the third planar (often the V plane) of the framebuffer if one exists. Note: This register is double buffered. */ + __I uint32_t RESERVE24[1]; + __IO uint32_t OverlayConfig0; /*!< [0x1540] Overlay Configuration Register. Overlay attributes control. Note: This register is double buffered. */ + __I uint32_t RESERVE25[15]; + __IO uint32_t OverlayAlphaBlendConfig0; /*!< [0x1580] Overlay Alpha Blending Configuration Register. Note: This register is double buffered. */ + __I uint32_t RESERVE26[15]; + __IO uint32_t OverlayAddress0; /*!< [0x15c0] Overlay Start Address Register. Starting address of the overlay. Note: This register is double buffered. */ + __I uint32_t RESERVE27[15]; + __IO uint32_t OverlayStride0; /*!< [0x1600] Overlay Stride Register. Stride of the overlay in bytes. Note: This register is double buffered. */ + __I uint32_t RESERVE28[15]; + __IO uint32_t OverlayTL0; /*!< [0x1640] Overlay Origin Register. Top left coordinate of the panel pixel where the overlay should start. Be aware there is no panning inside the overlay. Note: This register is double buffered */ + __I uint32_t RESERVE29[15]; + __IO uint32_t OverlayBR0; /*!< [0x1680] Overlay End Register. Bottom right coordinate of the panel pixel where the overlay should end. The border is inclusive. Note: This register is double buffered. */ + __I uint32_t RESERVE30[15]; + __IO uint32_t OverlaySrcGlobalColor0; /*!< [0x16c0] Overlay Source Global Color Register. Color value used when alpha blending process is configured to use global color for source. Note: This register is double buffered. */ + __I uint32_t RESERVE31[15]; + __IO uint32_t OverlayDstGlobalColor0; /*!< [0x1700] Overlay Destination Global Color Register. Color value used when alpha blending process is configured to use global color for destination. Note: This register is double buffered. */ + __I uint32_t RESERVE32[15]; + __IO uint32_t OverlayColorKey0; /*!< [0x1740] Overlay Color Key Start Address Register. Start of color key range for overlay. Note: This register is double buffered. */ + __I uint32_t RESERVE33[15]; + __IO uint32_t OverlayColorKeyHigh0; /*!< [0x1780] Overlay Color Key End Address Register. End of color key range for overlay. Note: This register is double buffered. */ + __I uint32_t RESERVE34[15]; + __IO uint32_t OverlaySize0; /*!< [0x17c0] Overlay Window Size Register. Window size of the overlay buffer in memory - in pixels. Note: This register is double buffered. */ + __I uint32_t RESERVE35[15]; + __IO uint32_t FrameBufferUStride0; /*!< [0x1800] Framebuffer Second Plane U Stride Register. Stride of the second planar (often the U plane) of the framebuffer if one exists. Note: This register is double buffered. */ + __I uint32_t RESERVE36[1]; + __IO uint32_t FrameBufferVStride0; /*!< [0x1808] Framebuffer Third Plane V Stride Register. Stride of the third planar (often the V plane) of the framebuffer if one exists. Note: This register is double buffered. */ + __I uint32_t RESERVE37[1]; + __IO uint32_t FrameBufferSize0; /*!< [0x1810] Framebuffer Size Register. Window size of the framebuffer in memory - in pixels. Note: This register is double buffered. */ + __I uint32_t RESERVE38[1]; + __O uint32_t IndexColorTableIndex0; /*!< [0x1818] Index Color Table Index Register. Index into index color table. See IndexColorTableData for more information. */ + __I uint32_t RESERVE39[1]; + __O uint32_t IndexColorTableData0; /*!< [0x1820] Index Color Table Data Translation Register. Translation values for the index color table. When this register gets written, the data gets stored in the index color table at the index specified by the IndexColorTableIndex register. After the register is written, the index gets incremented. Note: This register is double buffered. */ + __I uint32_t RESERVE40[7]; + __IO uint32_t OverlayUPlanarAddress0; /*!< [0x1840] Overlay Second Plane U Start Address Register. Address of the second planar (often U plane) of the overlay if one exists. Note: This register is double buffered. */ + __I uint32_t RESERVE41[15]; + __IO uint32_t OverlayVPlanarAddress0; /*!< [0x1880] Overlay Third Plane V Start Address Register. Address of the third planar (often V plane) of the overlay if one exists. Note: This register is double buffered. */ + __I uint32_t RESERVE42[15]; + __IO uint32_t OverlayUStride0; /*!< [0x18c0] Overlay Second Plane U Stride Register. Stride of the second planar of the overlay if one exists. Note: This register is double buffered. */ + __I uint32_t RESERVE43[15]; + __IO uint32_t OverlayVStride0; /*!< [0x1900] Overlay Third Plane V Stride Register. Stride of the third planar of the overlay if one exists. Note: This register is double buffered. */ + __I uint32_t RESERVE44[15]; + __IO uint32_t OverlayClearValue0; /*!< [0x1940] Overlay Clear Value Register. Clear value used when OverlayConfig.Clear is enabled. Format is A8R8G8B8. Note: This register is double buffered. */ + __I uint32_t RESERVE45[15]; + __O uint32_t OverlayIndexColorTableIndex0; /*!< [0x1980] Overlay Index Color Table Index Register. Index into overlay index color table. See OverlayIndexColorTableData for more information. */ + __I uint32_t RESERVE46[15]; + __O uint32_t OverlayIndexColorTableData0; /*!< [0x19c0] Index Color Table Data Translation Register. Translation values for the index color table of the overlay. When this register gets written, the data gets stored in the index color table at the index specified by the OverlayIndexColorTableIndex register. After the register is written, the index gets incremented. Note: This register is double buffered. */ + __I uint32_t RESERVE47[21]; + __IO uint32_t FrameBufferClearValue0; /*!< [0x1a18] Framebuffer Clear Value Register. Clear value used when FrameBufferConfig. Clear is enabled, format is A8R8G8B8. Note: This register is double buffered. */ + __I uint32_t RESERVE48[3]; + __IO uint32_t ModuleClockGatingControl0; /*!< [0x1a28] Clock Gating Module Control Register. Module level clock gating control for video and overlay. */ + __I uint32_t RESERVE49[1]; + __IO uint32_t LatencyCounter0; /*!< [0x1a30] Latency Counter Register. */ + __I uint32_t RESERVE50[1]; + __IO uint32_t Qos0; /*!< [0x1a38] Quality of Service Latency Value Register. */ + __I uint32_t RESERVE51[129]; + __IO uint32_t MpuIntfCmd0; /*!< [0x1c40] MPU Command Configuration Register. */ + __I uint32_t RESERVE52[1]; + __I uint32_t MpuIntfReadPara00; /*!< [0x1c48] MPU Read Parameter0 Register. */ + __I uint32_t RESERVE53[1]; + __I uint32_t MpuIntfReadPara10; /*!< [0x1c50] MPU Read Parameter1 Register. */ + __I uint32_t RESERVE54[1]; + __I uint32_t MpuIntfReadPara20; /*!< [0x1c58] MPU Read Parameter2 Register. */ + __I uint32_t RESERVE55[1]; + __I uint32_t MpuIntfReadPara30; /*!< [0x1c60] MPU Read Parameter3 Register. */ + __I uint32_t RESERVE56[1]; + __I uint32_t MpuIntfReadPara40; /*!< [0x1c68] MPU Read Parameter4 Register. */ + __I uint32_t RESERVE57[1]; + __I uint32_t MpuIntfReadStatus0; /*!< [0x1c70] MPU Read Parameter Status Register. */ + __I uint32_t RESERVE58[1]; + __IO uint32_t MpuIntfConfig0; /*!< [0x1c78] MPU Interface Configuration Register. */ + __I uint32_t RESERVE59[1]; + __IO uint32_t MpuIntfFrame0; /*!< [0x1c80] MPU Frame Configuration Register. Note: This register is double buffered. */ + __I uint32_t RESERVE60[1]; + __IO uint32_t MpuIntfACWrI800; /*!< [0x1c88] MPU Write AC Characteristics I80 Register. */ + __I uint32_t RESERVE61[1]; + __IO uint32_t MpuIntfACRdI800; /*!< [0x1c90] MPU Read AC Characteristics I80 Register. */ + __I uint32_t RESERVE62[1]; + __IO uint32_t MpuIntfACWrM680; /*!< [0x1c98] MPU Write AC Characteristics M68 Register. */ + __I uint32_t RESERVE63[1]; + __IO uint32_t MpuIntfACRdM680; /*!< [0x1ca0] MPU Read AC Characteristics M68 Register. */ + __I uint32_t RESERVE64[1]; + __IO uint32_t MpuIntfACVsyncCSX0; /*!< [0x1ca8] MPU CSX Assert Register. */ + +} DISP_T; + +/** + @addtogroup DISP_CONST DISP Bit Field Definition + Constant Definitions for DISP Controller +@{ */ + +#define DISP_AQHiClockControl_CLKDC_DIS_Pos (1) /*!< DISP_T::AQHiClockControl: CLKDC_DIS Position*/ +#define DISP_AQHiClockControl_CLKDC_DIS_Msk (0x1ul << DISP_AQHiClockControl_CLKDC_DIS_Pos) /*!< DISP_T::AQHiClockControl: CLKDC_DIS Mask*/ + +#define DISP_AQHiClockControl_FSCALE_VAL_Pos (2) /*!< DISP_T::AQHiClockControl: FSCALE_VAL Position*/ +#define DISP_AQHiClockControl_FSCALE_VAL_Msk (0x7ful << DISP_AQHiClockControl_FSCALE_VAL_Pos) /*!< DISP_T::AQHiClockControl: FSCALE_VAL Mask*/ + +#define DISP_AQHiClockControl_FSCALE_CMD_LOAD_Pos (9) /*!< DISP_T::AQHiClockControl: FSCALE_CMD_LOAD Position*/ +#define DISP_AQHiClockControl_FSCALE_CMD_LOAD_Msk (0x1ul << DISP_AQHiClockControl_FSCALE_CMD_LOAD_Pos) /*!< DISP_T::AQHiClockControl: FSCALE_CMD_LOAD Mask*/ + +#define DISP_AQHiClockControl_DISABLE_RAM_CLOCK_GATING_Pos (10) /*!< DISP_T::AQHiClockControl: DISABLE_RAM_CLOCK_GATING Position*/ +#define DISP_AQHiClockControl_DISABLE_RAM_CLOCK_GATING_Msk (0x1ul << DISP_AQHiClockControl_DISABLE_RAM_CLOCK_GATING_Pos) /*!< DISP_T::AQHiClockControl: DISABLE_RAM_CLOCK_GATING Mask*/ + +#define DISP_AQHiClockControl_DISABLE_DEBUG_REGISTERS_Pos (11) /*!< DISP_T::AQHiClockControl: DISABLE_DEBUG_REGISTERS Position*/ +#define DISP_AQHiClockControl_DISABLE_DEBUG_REGISTERS_Msk (0x1ul << DISP_AQHiClockControl_DISABLE_DEBUG_REGISTERS_Pos) /*!< DISP_T::AQHiClockControl: DISABLE_DEBUG_REGISTERS Mask*/ + +#define DISP_AQHiClockControl_SOFT_RESET_Pos (12) /*!< DISP_T::AQHiClockControl: SOFT_RESET Position*/ +#define DISP_AQHiClockControl_SOFT_RESET_Msk (0x1ul << DISP_AQHiClockControl_SOFT_RESET_Pos) /*!< DISP_T::AQHiClockControl: SOFT_RESET Mask*/ + +#define DISP_AQHiClockControl_DISABLE_RAM_POWER_OPTIMIZATION_Pos (13) /*!< DISP_T::AQHiClockControl: DISABLE_RAM_POWER_OPTIMIZATION Position*/ +#define DISP_AQHiClockControl_DISABLE_RAM_POWER_OPTIMIZATION_Msk (0x1ul << DISP_AQHiClockControl_DISABLE_RAM_POWER_OPTIMIZATION_Pos) /*!< DISP_T::AQHiClockControl: DISABLE_RAM_POWER_OPTIMIZATION Mask*/ + +#define DISP_FrameBufferAddress0_ADDRESS_Pos (0) /*!< DISP_T::FrameBufferAddress0: ADDRESS Position*/ +#define DISP_FrameBufferAddress0_ADDRESS_Msk (0x7ffffffful << DISP_FrameBufferAddress0_ADDRESS_Pos) /*!< DISP_T::FrameBufferAddress0: ADDRESS Mask*/ + +#define DISP_FrameBufferAddress0_TYPE_Pos (31) /*!< DISP_T::FrameBufferAddress0: TYPE Position*/ +#define DISP_FrameBufferAddress0_TYPE_Msk (0x1ul << DISP_FrameBufferAddress0_TYPE_Pos) /*!< DISP_T::FrameBufferAddress0: TYPE Mask*/ + +#define DISP_FrameBufferStride0_STRIDE_Pos (0) /*!< DISP_T::FrameBufferStride0: STRIDE Position*/ +#define DISP_FrameBufferStride0_STRIDE_Msk (0x1fffful << DISP_FrameBufferStride0_STRIDE_Pos) /*!< DISP_T::FrameBufferStride0: STRIDE Mask*/ + +#define DISP_DisplayDitherConfig0_ENABLE_Pos (31) /*!< DISP_T::DisplayDitherConfig0: ENABLE Position*/ +#define DISP_DisplayDitherConfig0_ENABLE_Msk (0x1ul << DISP_DisplayDitherConfig0_ENABLE_Pos) /*!< DISP_T::DisplayDitherConfig0: ENABLE Mask*/ + +#define DISP_PanelConfig0_DE_Pos (0) /*!< DISP_T::PanelConfig0: DE Position */ +#define DISP_PanelConfig0_DE_Msk (0x1ul << DISP_PanelConfig0_DE_Pos) /*!< DISP_T::PanelConfig0: DE Mask */ + +#define DISP_PanelConfig0_DE_POLARITY_Pos (1) /*!< DISP_T::PanelConfig0: DE_POLARITY Position*/ +#define DISP_PanelConfig0_DE_POLARITY_Msk (0x1ul << DISP_PanelConfig0_DE_POLARITY_Pos) /*!< DISP_T::PanelConfig0: DE_POLARITY Mask*/ + +#define DISP_PanelConfig0_DATA_ENABLE_Pos (4) /*!< DISP_T::PanelConfig0: DATA_ENABLE Position*/ +#define DISP_PanelConfig0_DATA_ENABLE_Msk (0x1ul << DISP_PanelConfig0_DATA_ENABLE_Pos) /*!< DISP_T::PanelConfig0: DATA_ENABLE Mask*/ + +#define DISP_PanelConfig0_DATA_POLARITY_Pos (5) /*!< DISP_T::PanelConfig0: DATA_POLARITY Position*/ +#define DISP_PanelConfig0_DATA_POLARITY_Msk (0x1ul << DISP_PanelConfig0_DATA_POLARITY_Pos) /*!< DISP_T::PanelConfig0: DATA_POLARITY Mask*/ + +#define DISP_PanelConfig0_CLOCK_Pos (8) /*!< DISP_T::PanelConfig0: CLOCK Position*/ +#define DISP_PanelConfig0_CLOCK_Msk (0x1ul << DISP_PanelConfig0_CLOCK_Pos) /*!< DISP_T::PanelConfig0: CLOCK Mask */ + +#define DISP_PanelConfig0_CLOCK_POLARITY_Pos (9) /*!< DISP_T::PanelConfig0: CLOCK_POLARITY Position*/ +#define DISP_PanelConfig0_CLOCK_POLARITY_Msk (0x1ul << DISP_PanelConfig0_CLOCK_POLARITY_Pos) /*!< DISP_T::PanelConfig0: CLOCK_POLARITY Mask*/ + +#define DISP_DisplayDitherTableLow0_Y0_X0_Pos (0) /*!< DISP_T::DisplayDitherTableLow0: Y0_X0 Position*/ +#define DISP_DisplayDitherTableLow0_Y0_X0_Msk (0xful << DISP_DisplayDitherTableLow0_Y0_X0_Pos) /*!< DISP_T::DisplayDitherTableLow0: Y0_X0 Mask*/ + +#define DISP_DisplayDitherTableLow0_Y0_X1_Pos (4) /*!< DISP_T::DisplayDitherTableLow0: Y0_X1 Position*/ +#define DISP_DisplayDitherTableLow0_Y0_X1_Msk (0xful << DISP_DisplayDitherTableLow0_Y0_X1_Pos) /*!< DISP_T::DisplayDitherTableLow0: Y0_X1 Mask*/ + +#define DISP_DisplayDitherTableLow0_Y0_X2_Pos (8) /*!< DISP_T::DisplayDitherTableLow0: Y0_X2 Position*/ +#define DISP_DisplayDitherTableLow0_Y0_X2_Msk (0xful << DISP_DisplayDitherTableLow0_Y0_X2_Pos) /*!< DISP_T::DisplayDitherTableLow0: Y0_X2 Mask*/ + +#define DISP_DisplayDitherTableLow0_Y0_X3_Pos (12) /*!< DISP_T::DisplayDitherTableLow0: Y0_X3 Position*/ +#define DISP_DisplayDitherTableLow0_Y0_X3_Msk (0xful << DISP_DisplayDitherTableLow0_Y0_X3_Pos) /*!< DISP_T::DisplayDitherTableLow0: Y0_X3 Mask*/ + +#define DISP_DisplayDitherTableLow0_Y1_X0_Pos (16) /*!< DISP_T::DisplayDitherTableLow0: Y1_X0 Position*/ +#define DISP_DisplayDitherTableLow0_Y1_X0_Msk (0xful << DISP_DisplayDitherTableLow0_Y1_X0_Pos) /*!< DISP_T::DisplayDitherTableLow0: Y1_X0 Mask*/ + +#define DISP_DisplayDitherTableLow0_Y1_X1_Pos (20) /*!< DISP_T::DisplayDitherTableLow0: Y1_X1 Position*/ +#define DISP_DisplayDitherTableLow0_Y1_X1_Msk (0xful << DISP_DisplayDitherTableLow0_Y1_X1_Pos) /*!< DISP_T::DisplayDitherTableLow0: Y1_X1 Mask*/ + +#define DISP_DisplayDitherTableLow0_Y1_X2_Pos (24) /*!< DISP_T::DisplayDitherTableLow0: Y1_X2 Position*/ +#define DISP_DisplayDitherTableLow0_Y1_X2_Msk (0xful << DISP_DisplayDitherTableLow0_Y1_X2_Pos) /*!< DISP_T::DisplayDitherTableLow0: Y1_X2 Mask*/ + +#define DISP_DisplayDitherTableLow0_Y1_X3_Pos (28) /*!< DISP_T::DisplayDitherTableLow0: Y1_X3 Position*/ +#define DISP_DisplayDitherTableLow0_Y1_X3_Msk (0xful << DISP_DisplayDitherTableLow0_Y1_X3_Pos) /*!< DISP_T::DisplayDitherTableLow0: Y1_X3 Mask*/ + +#define DISP_DisplayDitherTableHigh0_Y2_X0_Pos (0) /*!< DISP_T::DisplayDitherTableHigh0: Y2_X0 Position*/ +#define DISP_DisplayDitherTableHigh0_Y2_X0_Msk (0xful << DISP_DisplayDitherTableHigh0_Y2_X0_Pos) /*!< DISP_T::DisplayDitherTableHigh0: Y2_X0 Mask*/ + +#define DISP_DisplayDitherTableHigh0_Y2_X1_Pos (4) /*!< DISP_T::DisplayDitherTableHigh0: Y2_X1 Position*/ +#define DISP_DisplayDitherTableHigh0_Y2_X1_Msk (0xful << DISP_DisplayDitherTableHigh0_Y2_X1_Pos) /*!< DISP_T::DisplayDitherTableHigh0: Y2_X1 Mask*/ + +#define DISP_DisplayDitherTableHigh0_Y2_X2_Pos (8) /*!< DISP_T::DisplayDitherTableHigh0: Y2_X2 Position*/ +#define DISP_DisplayDitherTableHigh0_Y2_X2_Msk (0xful << DISP_DisplayDitherTableHigh0_Y2_X2_Pos) /*!< DISP_T::DisplayDitherTableHigh0: Y2_X2 Mask*/ + +#define DISP_DisplayDitherTableHigh0_Y2_X3_Pos (12) /*!< DISP_T::DisplayDitherTableHigh0: Y2_X3 Position*/ +#define DISP_DisplayDitherTableHigh0_Y2_X3_Msk (0xful << DISP_DisplayDitherTableHigh0_Y2_X3_Pos) /*!< DISP_T::DisplayDitherTableHigh0: Y2_X3 Mask*/ + +#define DISP_DisplayDitherTableHigh0_Y3_X0_Pos (16) /*!< DISP_T::DisplayDitherTableHigh0: Y3_X0 Position*/ +#define DISP_DisplayDitherTableHigh0_Y3_X0_Msk (0xful << DISP_DisplayDitherTableHigh0_Y3_X0_Pos) /*!< DISP_T::DisplayDitherTableHigh0: Y3_X0 Mask*/ + +#define DISP_DisplayDitherTableHigh0_Y3_X1_Pos (20) /*!< DISP_T::DisplayDitherTableHigh0: Y3_X1 Position*/ +#define DISP_DisplayDitherTableHigh0_Y3_X1_Msk (0xful << DISP_DisplayDitherTableHigh0_Y3_X1_Pos) /*!< DISP_T::DisplayDitherTableHigh0: Y3_X1 Mask*/ + +#define DISP_DisplayDitherTableHigh0_Y3_X2_Pos (24) /*!< DISP_T::DisplayDitherTableHigh0: Y3_X2 Position*/ +#define DISP_DisplayDitherTableHigh0_Y3_X2_Msk (0xful << DISP_DisplayDitherTableHigh0_Y3_X2_Pos) /*!< DISP_T::DisplayDitherTableHigh0: Y3_X2 Mask*/ + +#define DISP_DisplayDitherTableHigh0_Y3_X3_Pos (28) /*!< DISP_T::DisplayDitherTableHigh0: Y3_X3 Position*/ +#define DISP_DisplayDitherTableHigh0_Y3_X3_Msk (0xful << DISP_DisplayDitherTableHigh0_Y3_X3_Pos) /*!< DISP_T::DisplayDitherTableHigh0: Y3_X3 Mask*/ + +#define DISP_HDisplay0_DISPLAY_END_Pos (0) /*!< DISP_T::HDisplay0: DISPLAY_END Position*/ +#define DISP_HDisplay0_DISPLAY_END_Msk (0x7ffful << DISP_HDisplay0_DISPLAY_END_Pos) /*!< DISP_T::HDisplay0: DISPLAY_END Mask*/ + +#define DISP_HDisplay0_TOTAL_Pos (16) /*!< DISP_T::HDisplay0: TOTAL Position */ +#define DISP_HDisplay0_TOTAL_Msk (0x7ffful << DISP_HDisplay0_TOTAL_Pos) /*!< DISP_T::HDisplay0: TOTAL Mask */ + +#define DISP_HSync0_START_Pos (0) /*!< DISP_T::HSync0: START Position */ +#define DISP_HSync0_START_Msk (0x7ffful << DISP_HSync0_START_Pos) /*!< DISP_T::HSync0: START Mask */ + +#define DISP_HSync0_END_Pos (15) /*!< DISP_T::HSync0: END Position */ +#define DISP_HSync0_END_Msk (0x7ffful << DISP_HSync0_END_Pos) /*!< DISP_T::HSync0: END Mask */ + +#define DISP_HSync0_PULSE_Pos (30) /*!< DISP_T::HSync0: PULSE Position */ +#define DISP_HSync0_PULSE_Msk (0x1ul << DISP_HSync0_PULSE_Pos) /*!< DISP_T::HSync0: PULSE Mask */ + +#define DISP_HSync0_POLARITY_Pos (31) /*!< DISP_T::HSync0: POLARITY Position */ +#define DISP_HSync0_POLARITY_Msk (0x1ul << DISP_HSync0_POLARITY_Pos) /*!< DISP_T::HSync0: POLARITY Mask */ + +#define DISP_VDisplay0_DISPLAY_END_Pos (0) /*!< DISP_T::VDisplay0: DISPLAY_END Position*/ +#define DISP_VDisplay0_DISPLAY_END_Msk (0x7ffful << DISP_VDisplay0_DISPLAY_END_Pos) /*!< DISP_T::VDisplay0: DISPLAY_END Mask*/ + +#define DISP_VDisplay0_TOTAL_Pos (16) /*!< DISP_T::VDisplay0: TOTAL Position */ +#define DISP_VDisplay0_TOTAL_Msk (0x7ffful << DISP_VDisplay0_TOTAL_Pos) /*!< DISP_T::VDisplay0: TOTAL Mask */ + +#define DISP_VSync0_START_Pos (0) /*!< DISP_T::VSync0: START Position */ +#define DISP_VSync0_START_Msk (0x7ffful << DISP_VSync0_START_Pos) /*!< DISP_T::VSync0: START Mask */ + +#define DISP_VSync0_END_Pos (15) /*!< DISP_T::VSync0: END Position */ +#define DISP_VSync0_END_Msk (0x7ffful << DISP_VSync0_END_Pos) /*!< DISP_T::VSync0: END Mask */ + +#define DISP_VSync0_PULSE_Pos (30) /*!< DISP_T::VSync0: PULSE Position */ +#define DISP_VSync0_PULSE_Msk (0x1ul << DISP_VSync0_PULSE_Pos) /*!< DISP_T::VSync0: PULSE Mask */ + +#define DISP_VSync0_POLARITY_Pos (31) /*!< DISP_T::VSync0: POLARITY Position */ +#define DISP_VSync0_POLARITY_Msk (0x1ul << DISP_VSync0_POLARITY_Pos) /*!< DISP_T::VSync0: POLARITY Mask */ + +#define DISP_DisplayCurrentLocation0_X_Pos (0) /*!< DISP_T::DisplayCurrentLocation0: X Position*/ +#define DISP_DisplayCurrentLocation0_X_Msk (0xfffful << DISP_DisplayCurrentLocation0_X_Pos) /*!< DISP_T::DisplayCurrentLocation0: X Mask*/ + +#define DISP_DisplayCurrentLocation0_Y_Pos (16) /*!< DISP_T::DisplayCurrentLocation0: Y Position*/ +#define DISP_DisplayCurrentLocation0_Y_Msk (0xfffful << DISP_DisplayCurrentLocation0_Y_Pos) /*!< DISP_T::DisplayCurrentLocation0: Y Mask*/ + +#define DISP_GammaIndex0_INDEX_Pos (0) /*!< DISP_T::GammaIndex0: INDEX Position*/ +#define DISP_GammaIndex0_INDEX_Msk (0xfful << DISP_GammaIndex0_INDEX_Pos) /*!< DISP_T::GammaIndex0: INDEX Mask */ + +#define DISP_GammaData0_BLUE_Pos (0) /*!< DISP_T::GammaData0: BLUE Position */ +#define DISP_GammaData0_BLUE_Msk (0x3fful << DISP_GammaData0_BLUE_Pos) /*!< DISP_T::GammaData0: BLUE Mask */ + +#define DISP_GammaData0_GREEN_Pos (10) /*!< DISP_T::GammaData0: GREEN Position*/ +#define DISP_GammaData0_GREEN_Msk (0x3fful << DISP_GammaData0_GREEN_Pos) /*!< DISP_T::GammaData0: GREEN Mask */ + +#define DISP_GammaData0_READ_Pos (20) /*!< DISP_T::GammaData0: READ Position */ +#define DISP_GammaData0_READ_Msk (0x3fful << DISP_GammaData0_READ_Pos) /*!< DISP_T::GammaData0: READ Mask */ + +#define DISP_CursorConfig_FORMAT_Pos (0) /*!< DISP_T::CursorConfig: FORMAT Position*/ +#define DISP_CursorConfig_FORMAT_Msk (0x3ul << DISP_CursorConfig_FORMAT_Pos) /*!< DISP_T::CursorConfig: FORMAT Mask */ + +#define DISP_CursorConfig_DISPLAY_Pos (4) /*!< DISP_T::CursorConfig: DISPLAY Position*/ +#define DISP_CursorConfig_DISPLAY_Msk (0x1ul << DISP_CursorConfig_DISPLAY_Pos) /*!< DISP_T::CursorConfig: DISPLAY Mask*/ + +#define DISP_CursorConfig_HOT_SPOT_Y_Pos (8) /*!< DISP_T::CursorConfig: HOT_SPOT_Y Position*/ +#define DISP_CursorConfig_HOT_SPOT_Y_Msk (0x1ful << DISP_CursorConfig_HOT_SPOT_Y_Pos) /*!< DISP_T::CursorConfig: HOT_SPOT_Y Mask*/ + +#define DISP_CursorConfig_HOT_SPOT_X_Pos (16) /*!< DISP_T::CursorConfig: HOT_SPOT_X Position*/ +#define DISP_CursorConfig_HOT_SPOT_X_Msk (0x1ful << DISP_CursorConfig_HOT_SPOT_X_Pos) /*!< DISP_T::CursorConfig: HOT_SPOT_X Mask*/ + +#define DISP_CursorAddress_ADDRESS_Pos (0) /*!< DISP_T::CursorAddress: ADDRESS Position*/ +#define DISP_CursorAddress_ADDRESS_Msk (0x7ffffffful << DISP_CursorAddress_ADDRESS_Pos) /*!< DISP_T::CursorAddress: ADDRESS Mask*/ + +#define DISP_CursorAddress_TYPE_Pos (31) /*!< DISP_T::CursorAddress: TYPE Position*/ +#define DISP_CursorAddress_TYPE_Msk (0x1ul << DISP_CursorAddress_TYPE_Pos) /*!< DISP_T::CursorAddress: TYPE Mask */ + +#define DISP_CursorLocation_X_Pos (0) /*!< DISP_T::CursorLocation: X Position*/ +#define DISP_CursorLocation_X_Msk (0x7ffful << DISP_CursorLocation_X_Pos) /*!< DISP_T::CursorLocation: X Mask */ + +#define DISP_CursorLocation_Y_Pos (16) /*!< DISP_T::CursorLocation: Y Position*/ +#define DISP_CursorLocation_Y_Msk (0x7ffful << DISP_CursorLocation_Y_Pos) /*!< DISP_T::CursorLocation: Y Mask */ + +#define DISP_CursorBackground_BLUE_Pos (0) /*!< DISP_T::CursorBackground: BLUE Position*/ +#define DISP_CursorBackground_BLUE_Msk (0xfful << DISP_CursorBackground_BLUE_Pos) /*!< DISP_T::CursorBackground: BLUE Mask*/ + +#define DISP_CursorBackground_GREEN_Pos (8) /*!< DISP_T::CursorBackground: GREEN Position*/ +#define DISP_CursorBackground_GREEN_Msk (0xfful << DISP_CursorBackground_GREEN_Pos) /*!< DISP_T::CursorBackground: GREEN Mask*/ + +#define DISP_CursorBackground_RED_Pos (16) /*!< DISP_T::CursorBackground: RED Position*/ +#define DISP_CursorBackground_RED_Msk (0xfful << DISP_CursorBackground_RED_Pos) /*!< DISP_T::CursorBackground: RED Mask*/ + +#define DISP_CursorForeground_BLUE_Pos (0) /*!< DISP_T::CursorForeground: BLUE Position*/ +#define DISP_CursorForeground_BLUE_Msk (0xfful << DISP_CursorForeground_BLUE_Pos) /*!< DISP_T::CursorForeground: BLUE Mask*/ + +#define DISP_CursorForeground_GREEN_Pos (8) /*!< DISP_T::CursorForeground: GREEN Position*/ +#define DISP_CursorForeground_GREEN_Msk (0xfful << DISP_CursorForeground_GREEN_Pos) /*!< DISP_T::CursorForeground: GREEN Mask*/ + +#define DISP_CursorForeground_RED_Pos (16) /*!< DISP_T::CursorForeground: RED Position*/ +#define DISP_CursorForeground_RED_Msk (0xfful << DISP_CursorForeground_RED_Pos) /*!< DISP_T::CursorForeground: RED Mask*/ + +#define DISP_DisplayIntr_DISP0_Pos (0) /*!< DISP_T::DisplayIntr: DISP0 Position*/ +#define DISP_DisplayIntr_DISP0_Msk (0x1ul << DISP_DisplayIntr_DISP0_Pos) /*!< DISP_T::DisplayIntr: DISP0 Mask */ + +#define DISP_DisplayIntrEnable_DISP0_Pos (0) /*!< DISP_T::DisplayIntrEnable: DISP0 Position*/ +#define DISP_DisplayIntrEnable_DISP0_Msk (0x1ul << DISP_DisplayIntrEnable_DISP0_Pos) /*!< DISP_T::DisplayIntrEnable: DISP0 Mask*/ + +#define DISP_CursorModuleClockGatingControl_DISABLE_MODULE_CLOCK_GATING_CURSOR_Pos (0) /*!< DISP_T::CursorModuleClockGatingControl: DISABLE_MODULE_CLOCK_GATING_CURSOR Position*/ +#define DISP_CursorModuleClockGatingControl_DISABLE_MODULE_CLOCK_GATING_CURSOR_Msk (0x1ul << DISP_CursorModuleClockGatingControl_DISABLE_MODULE_CLOCK_GATING_CURSOR_Pos) /*!< DISP_T::CursorModuleClockGatingControl: DISABLE_MODULE_CLOCK_GATING_CURSOR Mask*/ + +#define DISP_GeneralConfig0_ENDIAN_CONTROL_Pos (0) /*!< DISP_T::GeneralConfig0: ENDIAN_CONTROL Position*/ +#define DISP_GeneralConfig0_ENDIAN_CONTROL_Msk (0x3ul << DISP_GeneralConfig0_ENDIAN_CONTROL_Pos) /*!< DISP_T::GeneralConfig0: ENDIAN_CONTROL Mask*/ + +#define DISP_GeneralConfig0_STALL_OUTPUT_WHEN_UNDERFLOW_Pos (2) /*!< DISP_T::GeneralConfig0: STALL_OUTPUT_WHEN_UNDERFLOW Position*/ +#define DISP_GeneralConfig0_STALL_OUTPUT_WHEN_UNDERFLOW_Msk (0x1ul << DISP_GeneralConfig0_STALL_OUTPUT_WHEN_UNDERFLOW_Pos) /*!< DISP_T::GeneralConfig0: STALL_OUTPUT_WHEN_UNDERFLOW Mask*/ + +#define DISP_GeneralConfig0_DISABLE_IDLE_Pos (3) /*!< DISP_T::GeneralConfig0: DISABLE_IDLE Position*/ +#define DISP_GeneralConfig0_DISABLE_IDLE_Msk (0x1ul << DISP_GeneralConfig0_DISABLE_IDLE_Pos) /*!< DISP_T::GeneralConfig0: DISABLE_IDLE Mask*/ + +#define DISP_DpiConfig0_DPI_DATA_FORMAT_Pos (0) /*!< DISP_T::DpiConfig0: DPI_DATA_FORMAT Position*/ +#define DISP_DpiConfig0_DPI_DATA_FORMAT_Msk (0x7ul << DISP_DpiConfig0_DPI_DATA_FORMAT_Pos) /*!< DISP_T::DpiConfig0: DPI_DATA_FORMAT Mask*/ + +#define DISP_DebugCounterSelect0_SELECT_Pos (0) /*!< DISP_T::DebugCounterSelect0: SELECT Position*/ +#define DISP_DebugCounterSelect0_SELECT_Msk (0xfful << DISP_DebugCounterSelect0_SELECT_Pos) /*!< DISP_T::DebugCounterSelect0: SELECT Mask*/ + +#define DISP_DebugCounterValue0_VALUE_Pos (0) /*!< DISP_T::DebugCounterValue0: VALUE Position*/ +#define DISP_DebugCounterValue0_VALUE_Msk (0xfffffffful << DISP_DebugCounterValue0_VALUE_Pos) /*!< DISP_T::DebugCounterValue0: VALUE Mask*/ + +#define DISP_FrameBufferColorKey0_BLUE_Pos (0) /*!< DISP_T::FrameBufferColorKey0: BLUE Position*/ +#define DISP_FrameBufferColorKey0_BLUE_Msk (0xfful << DISP_FrameBufferColorKey0_BLUE_Pos) /*!< DISP_T::FrameBufferColorKey0: BLUE Mask*/ + +#define DISP_FrameBufferColorKey0_GREEN_Pos (8) /*!< DISP_T::FrameBufferColorKey0: GREEN Position*/ +#define DISP_FrameBufferColorKey0_GREEN_Msk (0xfful << DISP_FrameBufferColorKey0_GREEN_Pos) /*!< DISP_T::FrameBufferColorKey0: GREEN Mask*/ + +#define DISP_FrameBufferColorKey0_RED_Pos (16) /*!< DISP_T::FrameBufferColorKey0: RED Position*/ +#define DISP_FrameBufferColorKey0_RED_Msk (0xfful << DISP_FrameBufferColorKey0_RED_Pos) /*!< DISP_T::FrameBufferColorKey0: RED Mask*/ + +#define DISP_FrameBufferColorKey0_ALPHA_Pos (24) /*!< DISP_T::FrameBufferColorKey0: ALPHA Position*/ +#define DISP_FrameBufferColorKey0_ALPHA_Msk (0xfful << DISP_FrameBufferColorKey0_ALPHA_Pos) /*!< DISP_T::FrameBufferColorKey0: ALPHA Mask*/ + +#define DISP_FrameBufferColorKeyHigh0_BLUE_Pos (0) /*!< DISP_T::FrameBufferColorKeyHigh0: BLUE Position*/ +#define DISP_FrameBufferColorKeyHigh0_BLUE_Msk (0xfful << DISP_FrameBufferColorKeyHigh0_BLUE_Pos) /*!< DISP_T::FrameBufferColorKeyHigh0: BLUE Mask*/ + +#define DISP_FrameBufferColorKeyHigh0_GREEN_Pos (8) /*!< DISP_T::FrameBufferColorKeyHigh0: GREEN Position*/ +#define DISP_FrameBufferColorKeyHigh0_GREEN_Msk (0xfful << DISP_FrameBufferColorKeyHigh0_GREEN_Pos) /*!< DISP_T::FrameBufferColorKeyHigh0: GREEN Mask*/ + +#define DISP_FrameBufferColorKeyHigh0_RED_Pos (16) /*!< DISP_T::FrameBufferColorKeyHigh0: RED Position*/ +#define DISP_FrameBufferColorKeyHigh0_RED_Msk (0xfful << DISP_FrameBufferColorKeyHigh0_RED_Pos) /*!< DISP_T::FrameBufferColorKeyHigh0: RED Mask*/ + +#define DISP_FrameBufferColorKeyHigh0_ALPHA_Pos (24) /*!< DISP_T::FrameBufferColorKeyHigh0: ALPHA Position*/ +#define DISP_FrameBufferColorKeyHigh0_ALPHA_Msk (0xfful << DISP_FrameBufferColorKeyHigh0_ALPHA_Pos) /*!< DISP_T::FrameBufferColorKeyHigh0: ALPHA Mask*/ + +#define DISP_FrameBufferConfig0_OUTPUT_Pos (0) /*!< DISP_T::FrameBufferConfig0: OUTPUT Position*/ +#define DISP_FrameBufferConfig0_OUTPUT_Msk (0x1ul << DISP_FrameBufferConfig0_OUTPUT_Pos) /*!< DISP_T::FrameBufferConfig0: OUTPUT Mask*/ + +#define DISP_FrameBufferConfig0_GAMMA_Pos (2) /*!< DISP_T::FrameBufferConfig0: GAMMA Position*/ +#define DISP_FrameBufferConfig0_GAMMA_Msk (0x1ul << DISP_FrameBufferConfig0_GAMMA_Pos) /*!< DISP_T::FrameBufferConfig0: GAMMA Mask*/ + +#define DISP_FrameBufferConfig0_VALID_Pos (3) /*!< DISP_T::FrameBufferConfig0: VALID Position*/ +#define DISP_FrameBufferConfig0_VALID_Msk (0x1ul << DISP_FrameBufferConfig0_VALID_Pos) /*!< DISP_T::FrameBufferConfig0: VALID Mask*/ + +#define DISP_FrameBufferConfig0_RESET_Pos (4) /*!< DISP_T::FrameBufferConfig0: RESET Position*/ +#define DISP_FrameBufferConfig0_RESET_Msk (0x1ul << DISP_FrameBufferConfig0_RESET_Pos) /*!< DISP_T::FrameBufferConfig0: RESET Mask*/ + +#define DISP_FrameBufferConfig0_UNDERFLOW_Pos (5) /*!< DISP_T::FrameBufferConfig0: UNDERFLOW Position*/ +#define DISP_FrameBufferConfig0_UNDERFLOW_Msk (0x1ul << DISP_FrameBufferConfig0_UNDERFLOW_Pos) /*!< DISP_T::FrameBufferConfig0: UNDERFLOW Mask*/ + +#define DISP_FrameBufferConfig0_FLIP_IN_PROGRESS_Pos (6) /*!< DISP_T::FrameBufferConfig0: FLIP_IN_PROGRESS Position*/ +#define DISP_FrameBufferConfig0_FLIP_IN_PROGRESS_Msk (0x1ul << DISP_FrameBufferConfig0_FLIP_IN_PROGRESS_Pos) /*!< DISP_T::FrameBufferConfig0: FLIP_IN_PROGRESS Mask*/ + +#define DISP_FrameBufferConfig0_CLEAR_Pos (8) /*!< DISP_T::FrameBufferConfig0: CLEAR Position*/ +#define DISP_FrameBufferConfig0_CLEAR_Msk (0x1ul << DISP_FrameBufferConfig0_CLEAR_Pos) /*!< DISP_T::FrameBufferConfig0: CLEAR Mask*/ + +#define DISP_FrameBufferConfig0_TRANSPARENCY_Pos (9) /*!< DISP_T::FrameBufferConfig0: TRANSPARENCY Position*/ +#define DISP_FrameBufferConfig0_TRANSPARENCY_Msk (0x3ul << DISP_FrameBufferConfig0_TRANSPARENCY_Pos) /*!< DISP_T::FrameBufferConfig0: TRANSPARENCY Mask*/ + +#define DISP_FrameBufferConfig0_YUV_Pos (14) /*!< DISP_T::FrameBufferConfig0: YUV Position*/ +#define DISP_FrameBufferConfig0_YUV_Msk (0x7ul << DISP_FrameBufferConfig0_YUV_Pos) /*!< DISP_T::FrameBufferConfig0: YUV Mask*/ + +#define DISP_FrameBufferConfig0_SWIZZLE_Pos (23) /*!< DISP_T::FrameBufferConfig0: SWIZZLE Position*/ +#define DISP_FrameBufferConfig0_SWIZZLE_Msk (0x3ul << DISP_FrameBufferConfig0_SWIZZLE_Pos) /*!< DISP_T::FrameBufferConfig0: SWIZZLE Mask*/ + +#define DISP_FrameBufferConfig0_UV_SWIZZLE_Pos (25) /*!< DISP_T::FrameBufferConfig0: UV_SWIZZLE Position*/ +#define DISP_FrameBufferConfig0_UV_SWIZZLE_Msk (0x1ul << DISP_FrameBufferConfig0_UV_SWIZZLE_Pos) /*!< DISP_T::FrameBufferConfig0: UV_SWIZZLE Mask*/ + +#define DISP_FrameBufferConfig0_FORMAT_Pos (26) /*!< DISP_T::FrameBufferConfig0: FORMAT Position*/ +#define DISP_FrameBufferConfig0_FORMAT_Msk (0x3ful << DISP_FrameBufferConfig0_FORMAT_Pos) /*!< DISP_T::FrameBufferConfig0: FORMAT Mask*/ + +#define DISP_FrameBufferBGColor0_BLUE_Pos (0) /*!< DISP_T::FrameBufferBGColor0: BLUE Position*/ +#define DISP_FrameBufferBGColor0_BLUE_Msk (0xfful << DISP_FrameBufferBGColor0_BLUE_Pos) /*!< DISP_T::FrameBufferBGColor0: BLUE Mask*/ + +#define DISP_FrameBufferBGColor0_GREEN_Pos (8) /*!< DISP_T::FrameBufferBGColor0: GREEN Position*/ +#define DISP_FrameBufferBGColor0_GREEN_Msk (0xfful << DISP_FrameBufferBGColor0_GREEN_Pos) /*!< DISP_T::FrameBufferBGColor0: GREEN Mask*/ + +#define DISP_FrameBufferBGColor0_RED_Pos (16) /*!< DISP_T::FrameBufferBGColor0: RED Position*/ +#define DISP_FrameBufferBGColor0_RED_Msk (0xfful << DISP_FrameBufferBGColor0_RED_Pos) /*!< DISP_T::FrameBufferBGColor0: RED Mask*/ + +#define DISP_FrameBufferBGColor0_ALPHA_Pos (24) /*!< DISP_T::FrameBufferBGColor0: ALPHA Position*/ +#define DISP_FrameBufferBGColor0_ALPHA_Msk (0xfful << DISP_FrameBufferBGColor0_ALPHA_Pos) /*!< DISP_T::FrameBufferBGColor0: ALPHA Mask*/ + +#define DISP_FrameBufferUPlanarAddress0_ADDRESS_Pos (0) /*!< DISP_T::FrameBufferUPlanarAddress0: ADDRESS Position*/ +#define DISP_FrameBufferUPlanarAddress0_ADDRESS_Msk (0x7ffffffful << DISP_FrameBufferUPlanarAddress0_ADDRESS_Pos) /*!< DISP_T::FrameBufferUPlanarAddress0: ADDRESS Mask*/ + +#define DISP_FrameBufferUPlanarAddress0_TYPE_Pos (31) /*!< DISP_T::FrameBufferUPlanarAddress0: TYPE Position*/ +#define DISP_FrameBufferUPlanarAddress0_TYPE_Msk (0x1ul << DISP_FrameBufferUPlanarAddress0_TYPE_Pos) /*!< DISP_T::FrameBufferUPlanarAddress0: TYPE Mask*/ + +#define DISP_FrameBufferVPlanarAddress0_ADDRESS_Pos (0) /*!< DISP_T::FrameBufferVPlanarAddress0: ADDRESS Position*/ +#define DISP_FrameBufferVPlanarAddress0_ADDRESS_Msk (0x7ffffffful << DISP_FrameBufferVPlanarAddress0_ADDRESS_Pos) /*!< DISP_T::FrameBufferVPlanarAddress0: ADDRESS Mask*/ + +#define DISP_FrameBufferVPlanarAddress0_TYPE_Pos (31) /*!< DISP_T::FrameBufferVPlanarAddress0: TYPE Position*/ +#define DISP_FrameBufferVPlanarAddress0_TYPE_Msk (0x1ul << DISP_FrameBufferVPlanarAddress0_TYPE_Pos) /*!< DISP_T::FrameBufferVPlanarAddress0: TYPE Mask*/ + +#define DISP_OverlayConfig0_TRANSPARENCY_Pos (0) /*!< DISP_T::OverlayConfig0: TRANSPARENCY Position*/ +#define DISP_OverlayConfig0_TRANSPARENCY_Msk (0x3ul << DISP_OverlayConfig0_TRANSPARENCY_Pos) /*!< DISP_T::OverlayConfig0: TRANSPARENCY Mask*/ + +#define DISP_OverlayConfig0_YUV_Pos (5) /*!< DISP_T::OverlayConfig0: YUV Position*/ +#define DISP_OverlayConfig0_YUV_Msk (0x7ul << DISP_OverlayConfig0_YUV_Pos) /*!< DISP_T::OverlayConfig0: YUV Mask */ + +#define DISP_OverlayConfig0_SWIZZLE_Pos (13) /*!< DISP_T::OverlayConfig0: SWIZZLE Position*/ +#define DISP_OverlayConfig0_SWIZZLE_Msk (0x3ul << DISP_OverlayConfig0_SWIZZLE_Pos) /*!< DISP_T::OverlayConfig0: SWIZZLE Mask*/ + +#define DISP_OverlayConfig0_UV_SWIZZLE_Pos (15) /*!< DISP_T::OverlayConfig0: UV_SWIZZLE Position*/ +#define DISP_OverlayConfig0_UV_SWIZZLE_Msk (0x1ul << DISP_OverlayConfig0_UV_SWIZZLE_Pos) /*!< DISP_T::OverlayConfig0: UV_SWIZZLE Mask*/ + +#define DISP_OverlayConfig0_FORMAT_Pos (16) /*!< DISP_T::OverlayConfig0: FORMAT Position*/ +#define DISP_OverlayConfig0_FORMAT_Msk (0x3ful << DISP_OverlayConfig0_FORMAT_Pos) /*!< DISP_T::OverlayConfig0: FORMAT Mask*/ + +#define DISP_OverlayConfig0_UNDERFLOW_Pos (23) /*!< DISP_T::OverlayConfig0: UNDERFLOW Position*/ +#define DISP_OverlayConfig0_UNDERFLOW_Msk (0x1ul << DISP_OverlayConfig0_UNDERFLOW_Pos) /*!< DISP_T::OverlayConfig0: UNDERFLOW Mask*/ + +#define DISP_OverlayConfig0_ENABLE_Pos (24) /*!< DISP_T::OverlayConfig0: ENABLE Position*/ +#define DISP_OverlayConfig0_ENABLE_Msk (0x1ul << DISP_OverlayConfig0_ENABLE_Pos) /*!< DISP_T::OverlayConfig0: ENABLE Mask*/ + +#define DISP_OverlayConfig0_CLEAR_Pos (25) /*!< DISP_T::OverlayConfig0: CLEAR Position*/ +#define DISP_OverlayConfig0_CLEAR_Msk (0x1ul << DISP_OverlayConfig0_CLEAR_Pos) /*!< DISP_T::OverlayConfig0: CLEAR Mask*/ + +#define DISP_OverlayAlphaBlendConfig0_SRC_ALPHA_MODE_Pos (0) /*!< DISP_T::OverlayAlphaBlendConfig0: SRC_ALPHA_MODE Position*/ +#define DISP_OverlayAlphaBlendConfig0_SRC_ALPHA_MODE_Msk (0x1ul << DISP_OverlayAlphaBlendConfig0_SRC_ALPHA_MODE_Pos) /*!< DISP_T::OverlayAlphaBlendConfig0: SRC_ALPHA_MODE Mask*/ + +#define DISP_OverlayAlphaBlendConfig0_DISABLE_ALPHA_BLEND_Pos (1) /*!< DISP_T::OverlayAlphaBlendConfig0: DISABLE_ALPHA_BLEND Position*/ +#define DISP_OverlayAlphaBlendConfig0_DISABLE_ALPHA_BLEND_Msk (0x1ul << DISP_OverlayAlphaBlendConfig0_DISABLE_ALPHA_BLEND_Pos) /*!< DISP_T::OverlayAlphaBlendConfig0: DISABLE_ALPHA_BLEND Mask*/ + +#define DISP_OverlayAlphaBlendConfig0_SRC_GLOBAL_ALPHA_MODE_Pos (3) /*!< DISP_T::OverlayAlphaBlendConfig0: SRC_GLOBAL_ALPHA_MODE Position*/ +#define DISP_OverlayAlphaBlendConfig0_SRC_GLOBAL_ALPHA_MODE_Msk (0x3ul << DISP_OverlayAlphaBlendConfig0_SRC_GLOBAL_ALPHA_MODE_Pos) /*!< DISP_T::OverlayAlphaBlendConfig0: SRC_GLOBAL_ALPHA_MODE Mask*/ + +#define DISP_OverlayAlphaBlendConfig0_SRC_BLENDING_MODE_Pos (5) /*!< DISP_T::OverlayAlphaBlendConfig0: SRC_BLENDING_MODE Position*/ +#define DISP_OverlayAlphaBlendConfig0_SRC_BLENDING_MODE_Msk (0x7ul << DISP_OverlayAlphaBlendConfig0_SRC_BLENDING_MODE_Pos) /*!< DISP_T::OverlayAlphaBlendConfig0: SRC_BLENDING_MODE Mask*/ + +#define DISP_OverlayAlphaBlendConfig0_SRC_ALPHA_FACTOR_Pos (8) /*!< DISP_T::OverlayAlphaBlendConfig0: SRC_ALPHA_FACTOR Position*/ +#define DISP_OverlayAlphaBlendConfig0_SRC_ALPHA_FACTOR_Msk (0x1ul << DISP_OverlayAlphaBlendConfig0_SRC_ALPHA_FACTOR_Pos) /*!< DISP_T::OverlayAlphaBlendConfig0: SRC_ALPHA_FACTOR Mask*/ + +#define DISP_OverlayAlphaBlendConfig0_DST_ALPHA_MODE_Pos (9) /*!< DISP_T::OverlayAlphaBlendConfig0: DST_ALPHA_MODE Position*/ +#define DISP_OverlayAlphaBlendConfig0_DST_ALPHA_MODE_Msk (0x1ul << DISP_OverlayAlphaBlendConfig0_DST_ALPHA_MODE_Pos) /*!< DISP_T::OverlayAlphaBlendConfig0: DST_ALPHA_MODE Mask*/ + +#define DISP_OverlayAlphaBlendConfig0_DST_GLOBAL_ALPHA_MODE_Pos (10) /*!< DISP_T::OverlayAlphaBlendConfig0: DST_GLOBAL_ALPHA_MODE Position*/ +#define DISP_OverlayAlphaBlendConfig0_DST_GLOBAL_ALPHA_MODE_Msk (0x3ul << DISP_OverlayAlphaBlendConfig0_DST_GLOBAL_ALPHA_MODE_Pos) /*!< DISP_T::OverlayAlphaBlendConfig0: DST_GLOBAL_ALPHA_MODE Mask*/ + +#define DISP_OverlayAlphaBlendConfig0_DST_BLENDING_MODE_Pos (12) /*!< DISP_T::OverlayAlphaBlendConfig0: DST_BLENDING_MODE Position*/ +#define DISP_OverlayAlphaBlendConfig0_DST_BLENDING_MODE_Msk (0x7ul << DISP_OverlayAlphaBlendConfig0_DST_BLENDING_MODE_Pos) /*!< DISP_T::OverlayAlphaBlendConfig0: DST_BLENDING_MODE Mask*/ + +#define DISP_OverlayAlphaBlendConfig0_DST_ALPHA_FACTOR_Pos (15) /*!< DISP_T::OverlayAlphaBlendConfig0: DST_ALPHA_FACTOR Position*/ +#define DISP_OverlayAlphaBlendConfig0_DST_ALPHA_FACTOR_Msk (0x1ul << DISP_OverlayAlphaBlendConfig0_DST_ALPHA_FACTOR_Pos) /*!< DISP_T::OverlayAlphaBlendConfig0: DST_ALPHA_FACTOR Mask*/ + +#define DISP_OverlayAddress0_ADDRESS_Pos (0) /*!< DISP_T::OverlayAddress0: ADDRESS Position*/ +#define DISP_OverlayAddress0_ADDRESS_Msk (0x7ffffffful << DISP_OverlayAddress0_ADDRESS_Pos) /*!< DISP_T::OverlayAddress0: ADDRESS Mask*/ + +#define DISP_OverlayAddress0_TYPE_Pos (31) /*!< DISP_T::OverlayAddress0: TYPE Position*/ +#define DISP_OverlayAddress0_TYPE_Msk (0x1ul << DISP_OverlayAddress0_TYPE_Pos) /*!< DISP_T::OverlayAddress0: TYPE Mask*/ + +#define DISP_OverlayStride0_STRIDE_Pos (0) /*!< DISP_T::OverlayStride0: STRIDE Position*/ +#define DISP_OverlayStride0_STRIDE_Msk (0x1fffful << DISP_OverlayStride0_STRIDE_Pos) /*!< DISP_T::OverlayStride0: STRIDE Mask*/ + +#define DISP_OverlayTL0_X_Pos (0) /*!< DISP_T::OverlayTL0: X Position */ +#define DISP_OverlayTL0_X_Msk (0x7ffful << DISP_OverlayTL0_X_Pos) /*!< DISP_T::OverlayTL0: X Mask */ + +#define DISP_OverlayTL0_Y_Pos (15) /*!< DISP_T::OverlayTL0: Y Position */ +#define DISP_OverlayTL0_Y_Msk (0x7ffful << DISP_OverlayTL0_Y_Pos) /*!< DISP_T::OverlayTL0: Y Mask */ + +#define DISP_OverlayBR0_X_Pos (0) /*!< DISP_T::OverlayBR0: X Position */ +#define DISP_OverlayBR0_X_Msk (0x7ffful << DISP_OverlayBR0_X_Pos) /*!< DISP_T::OverlayBR0: X Mask */ + +#define DISP_OverlayBR0_Y_Pos (15) /*!< DISP_T::OverlayBR0: Y Position */ +#define DISP_OverlayBR0_Y_Msk (0x7ffful << DISP_OverlayBR0_Y_Pos) /*!< DISP_T::OverlayBR0: Y Mask */ + +#define DISP_OverlaySrcGlobalColor0_BLUE_Pos (0) /*!< DISP_T::OverlaySrcGlobalColor0: BLUE Position*/ +#define DISP_OverlaySrcGlobalColor0_BLUE_Msk (0xfful << DISP_OverlaySrcGlobalColor0_BLUE_Pos) /*!< DISP_T::OverlaySrcGlobalColor0: BLUE Mask*/ + +#define DISP_OverlaySrcGlobalColor0_GREEN_Pos (8) /*!< DISP_T::OverlaySrcGlobalColor0: GREEN Position*/ +#define DISP_OverlaySrcGlobalColor0_GREEN_Msk (0xfful << DISP_OverlaySrcGlobalColor0_GREEN_Pos) /*!< DISP_T::OverlaySrcGlobalColor0: GREEN Mask*/ + +#define DISP_OverlaySrcGlobalColor0_RED_Pos (16) /*!< DISP_T::OverlaySrcGlobalColor0: RED Position*/ +#define DISP_OverlaySrcGlobalColor0_RED_Msk (0xfful << DISP_OverlaySrcGlobalColor0_RED_Pos) /*!< DISP_T::OverlaySrcGlobalColor0: RED Mask*/ + +#define DISP_OverlaySrcGlobalColor0_ALPHA_Pos (24) /*!< DISP_T::OverlaySrcGlobalColor0: ALPHA Position*/ +#define DISP_OverlaySrcGlobalColor0_ALPHA_Msk (0xfful << DISP_OverlaySrcGlobalColor0_ALPHA_Pos) /*!< DISP_T::OverlaySrcGlobalColor0: ALPHA Mask*/ + +#define DISP_OverlayDstGlobalColor0_BLUE_Pos (0) /*!< DISP_T::OverlayDstGlobalColor0: BLUE Position*/ +#define DISP_OverlayDstGlobalColor0_BLUE_Msk (0xfful << DISP_OverlayDstGlobalColor0_BLUE_Pos) /*!< DISP_T::OverlayDstGlobalColor0: BLUE Mask*/ + +#define DISP_OverlayDstGlobalColor0_GREEN_Pos (8) /*!< DISP_T::OverlayDstGlobalColor0: GREEN Position*/ +#define DISP_OverlayDstGlobalColor0_GREEN_Msk (0xfful << DISP_OverlayDstGlobalColor0_GREEN_Pos) /*!< DISP_T::OverlayDstGlobalColor0: GREEN Mask*/ + +#define DISP_OverlayDstGlobalColor0_RED_Pos (16) /*!< DISP_T::OverlayDstGlobalColor0: RED Position*/ +#define DISP_OverlayDstGlobalColor0_RED_Msk (0xfful << DISP_OverlayDstGlobalColor0_RED_Pos) /*!< DISP_T::OverlayDstGlobalColor0: RED Mask*/ + +#define DISP_OverlayDstGlobalColor0_ALPHA_Pos (24) /*!< DISP_T::OverlayDstGlobalColor0: ALPHA Position*/ +#define DISP_OverlayDstGlobalColor0_ALPHA_Msk (0xfful << DISP_OverlayDstGlobalColor0_ALPHA_Pos) /*!< DISP_T::OverlayDstGlobalColor0: ALPHA Mask*/ + +#define DISP_OverlayColorKey0_BLUE_Pos (0) /*!< DISP_T::OverlayColorKey0: BLUE Position*/ +#define DISP_OverlayColorKey0_BLUE_Msk (0xfful << DISP_OverlayColorKey0_BLUE_Pos) /*!< DISP_T::OverlayColorKey0: BLUE Mask*/ + +#define DISP_OverlayColorKey0_GREEN_Pos (8) /*!< DISP_T::OverlayColorKey0: GREEN Position*/ +#define DISP_OverlayColorKey0_GREEN_Msk (0xfful << DISP_OverlayColorKey0_GREEN_Pos) /*!< DISP_T::OverlayColorKey0: GREEN Mask*/ + +#define DISP_OverlayColorKey0_RED_Pos (16) /*!< DISP_T::OverlayColorKey0: RED Position*/ +#define DISP_OverlayColorKey0_RED_Msk (0xfful << DISP_OverlayColorKey0_RED_Pos) /*!< DISP_T::OverlayColorKey0: RED Mask*/ + +#define DISP_OverlayColorKey0_ALPHA_Pos (24) /*!< DISP_T::OverlayColorKey0: ALPHA Position*/ +#define DISP_OverlayColorKey0_ALPHA_Msk (0xfful << DISP_OverlayColorKey0_ALPHA_Pos) /*!< DISP_T::OverlayColorKey0: ALPHA Mask*/ + +#define DISP_OverlayColorKeyHigh0_BLUE_Pos (0) /*!< DISP_T::OverlayColorKeyHigh0: BLUE Position*/ +#define DISP_OverlayColorKeyHigh0_BLUE_Msk (0xfful << DISP_OverlayColorKeyHigh0_BLUE_Pos) /*!< DISP_T::OverlayColorKeyHigh0: BLUE Mask*/ + +#define DISP_OverlayColorKeyHigh0_GREEN_Pos (8) /*!< DISP_T::OverlayColorKeyHigh0: GREEN Position*/ +#define DISP_OverlayColorKeyHigh0_GREEN_Msk (0xfful << DISP_OverlayColorKeyHigh0_GREEN_Pos) /*!< DISP_T::OverlayColorKeyHigh0: GREEN Mask*/ + +#define DISP_OverlayColorKeyHigh0_RED_Pos (16) /*!< DISP_T::OverlayColorKeyHigh0: RED Position*/ +#define DISP_OverlayColorKeyHigh0_RED_Msk (0xfful << DISP_OverlayColorKeyHigh0_RED_Pos) /*!< DISP_T::OverlayColorKeyHigh0: RED Mask*/ + +#define DISP_OverlayColorKeyHigh0_ALPHA_Pos (24) /*!< DISP_T::OverlayColorKeyHigh0: ALPHA Position*/ +#define DISP_OverlayColorKeyHigh0_ALPHA_Msk (0xfful << DISP_OverlayColorKeyHigh0_ALPHA_Pos) /*!< DISP_T::OverlayColorKeyHigh0: ALPHA Mask*/ + +#define DISP_OverlaySize0_WIDTH_Pos (0) /*!< DISP_T::OverlaySize0: WIDTH Position*/ +#define DISP_OverlaySize0_WIDTH_Msk (0x7ffful << DISP_OverlaySize0_WIDTH_Pos) /*!< DISP_T::OverlaySize0: WIDTH Mask */ + +#define DISP_OverlaySize0_HEIGHT_Pos (15) /*!< DISP_T::OverlaySize0: HEIGHT Position*/ +#define DISP_OverlaySize0_HEIGHT_Msk (0x7ffful << DISP_OverlaySize0_HEIGHT_Pos) /*!< DISP_T::OverlaySize0: HEIGHT Mask */ + +#define DISP_FrameBufferUStride0_STRIDE_Pos (0) /*!< DISP_T::FrameBufferUStride0: STRIDE Position*/ +#define DISP_FrameBufferUStride0_STRIDE_Msk (0x1fffful << DISP_FrameBufferUStride0_STRIDE_Pos) /*!< DISP_T::FrameBufferUStride0: STRIDE Mask*/ + +#define DISP_FrameBufferVStride0_STRIDE_Pos (0) /*!< DISP_T::FrameBufferVStride0: STRIDE Position*/ +#define DISP_FrameBufferVStride0_STRIDE_Msk (0x1fffful << DISP_FrameBufferVStride0_STRIDE_Pos) /*!< DISP_T::FrameBufferVStride0: STRIDE Mask*/ + +#define DISP_FrameBufferSize0_WIDTH_Pos (0) /*!< DISP_T::FrameBufferSize0: WIDTH Position*/ +#define DISP_FrameBufferSize0_WIDTH_Msk (0x7ffful << DISP_FrameBufferSize0_WIDTH_Pos) /*!< DISP_T::FrameBufferSize0: WIDTH Mask*/ + +#define DISP_FrameBufferSize0_HEIGHT_Pos (15) /*!< DISP_T::FrameBufferSize0: HEIGHT Position*/ +#define DISP_FrameBufferSize0_HEIGHT_Msk (0x7ffful << DISP_FrameBufferSize0_HEIGHT_Pos) /*!< DISP_T::FrameBufferSize0: HEIGHT Mask*/ + +#define DISP_IndexColorTableIndex0_INDEX_Pos (0) /*!< DISP_T::IndexColorTableIndex0: INDEX Position*/ +#define DISP_IndexColorTableIndex0_INDEX_Msk (0xfful << DISP_IndexColorTableIndex0_INDEX_Pos) /*!< DISP_T::IndexColorTableIndex0: INDEX Mask*/ + +#define DISP_IndexColorTableData0_BLUE_Pos (0) /*!< DISP_T::IndexColorTableData0: BLUE Position*/ +#define DISP_IndexColorTableData0_BLUE_Msk (0xfful << DISP_IndexColorTableData0_BLUE_Pos) /*!< DISP_T::IndexColorTableData0: BLUE Mask*/ + +#define DISP_IndexColorTableData0_GREEN_Pos (8) /*!< DISP_T::IndexColorTableData0: GREEN Position*/ +#define DISP_IndexColorTableData0_GREEN_Msk (0xfful << DISP_IndexColorTableData0_GREEN_Pos) /*!< DISP_T::IndexColorTableData0: GREEN Mask*/ + +#define DISP_IndexColorTableData0_RED_Pos (16) /*!< DISP_T::IndexColorTableData0: RED Position*/ +#define DISP_IndexColorTableData0_RED_Msk (0xfful << DISP_IndexColorTableData0_RED_Pos) /*!< DISP_T::IndexColorTableData0: RED Mask*/ + +#define DISP_IndexColorTableData0_ALPHA_Pos (24) /*!< DISP_T::IndexColorTableData0: ALPHA Position*/ +#define DISP_IndexColorTableData0_ALPHA_Msk (0xfful << DISP_IndexColorTableData0_ALPHA_Pos) /*!< DISP_T::IndexColorTableData0: ALPHA Mask*/ + +#define DISP_OverlayUPlanarAddress0_ADDRESS_Pos (0) /*!< DISP_T::OverlayUPlanarAddress0: ADDRESS Position*/ +#define DISP_OverlayUPlanarAddress0_ADDRESS_Msk (0x7ffffffful << DISP_OverlayUPlanarAddress0_ADDRESS_Pos) /*!< DISP_T::OverlayUPlanarAddress0: ADDRESS Mask*/ + +#define DISP_OverlayUPlanarAddress0_TYPE_Pos (31) /*!< DISP_T::OverlayUPlanarAddress0: TYPE Position*/ +#define DISP_OverlayUPlanarAddress0_TYPE_Msk (0x1ul << DISP_OverlayUPlanarAddress0_TYPE_Pos) /*!< DISP_T::OverlayUPlanarAddress0: TYPE Mask*/ + +#define DISP_OverlayVPlanarAddress0_ADDRESS_Pos (0) /*!< DISP_T::OverlayVPlanarAddress0: ADDRESS Position*/ +#define DISP_OverlayVPlanarAddress0_ADDRESS_Msk (0x7ffffffful << DISP_OverlayVPlanarAddress0_ADDRESS_Pos) /*!< DISP_T::OverlayVPlanarAddress0: ADDRESS Mask*/ + +#define DISP_OverlayVPlanarAddress0_TYPE_Pos (31) /*!< DISP_T::OverlayVPlanarAddress0: TYPE Position*/ +#define DISP_OverlayVPlanarAddress0_TYPE_Msk (0x1ul << DISP_OverlayVPlanarAddress0_TYPE_Pos) /*!< DISP_T::OverlayVPlanarAddress0: TYPE Mask*/ + +#define DISP_OverlayUStride0_STRIDE_Pos (0) /*!< DISP_T::OverlayUStride0: STRIDE Position*/ +#define DISP_OverlayUStride0_STRIDE_Msk (0x1fffful << DISP_OverlayUStride0_STRIDE_Pos) /*!< DISP_T::OverlayUStride0: STRIDE Mask*/ + +#define DISP_OverlayVStride0_STRIDE_Pos (0) /*!< DISP_T::OverlayVStride0: STRIDE Position*/ +#define DISP_OverlayVStride0_STRIDE_Msk (0x1fffful << DISP_OverlayVStride0_STRIDE_Pos) /*!< DISP_T::OverlayVStride0: STRIDE Mask*/ + +#define DISP_OverlayClearValue0_BLUE_Pos (0) /*!< DISP_T::OverlayClearValue0: BLUE Position*/ +#define DISP_OverlayClearValue0_BLUE_Msk (0xfful << DISP_OverlayClearValue0_BLUE_Pos) /*!< DISP_T::OverlayClearValue0: BLUE Mask*/ + +#define DISP_OverlayClearValue0_GREEN_Pos (8) /*!< DISP_T::OverlayClearValue0: GREEN Position*/ +#define DISP_OverlayClearValue0_GREEN_Msk (0xfful << DISP_OverlayClearValue0_GREEN_Pos) /*!< DISP_T::OverlayClearValue0: GREEN Mask*/ + +#define DISP_OverlayClearValue0_RED_Pos (16) /*!< DISP_T::OverlayClearValue0: RED Position*/ +#define DISP_OverlayClearValue0_RED_Msk (0xfful << DISP_OverlayClearValue0_RED_Pos) /*!< DISP_T::OverlayClearValue0: RED Mask*/ + +#define DISP_OverlayClearValue0_ALPHA_Pos (24) /*!< DISP_T::OverlayClearValue0: ALPHA Position*/ +#define DISP_OverlayClearValue0_ALPHA_Msk (0xfful << DISP_OverlayClearValue0_ALPHA_Pos) /*!< DISP_T::OverlayClearValue0: ALPHA Mask*/ + +#define DISP_OverlayIndexColorTableIndex0_INDEX_Pos (0) /*!< DISP_T::OverlayIndexColorTableIndex0: INDEX Position*/ +#define DISP_OverlayIndexColorTableIndex0_INDEX_Msk (0xfful << DISP_OverlayIndexColorTableIndex0_INDEX_Pos) /*!< DISP_T::OverlayIndexColorTableIndex0: INDEX Mask*/ + +#define DISP_OverlayIndexColorTableData0_BLUE_Pos (0) /*!< DISP_T::OverlayIndexColorTableData0: BLUE Position*/ +#define DISP_OverlayIndexColorTableData0_BLUE_Msk (0xfful << DISP_OverlayIndexColorTableData0_BLUE_Pos) /*!< DISP_T::OverlayIndexColorTableData0: BLUE Mask*/ + +#define DISP_OverlayIndexColorTableData0_GREEN_Pos (8) /*!< DISP_T::OverlayIndexColorTableData0: GREEN Position*/ +#define DISP_OverlayIndexColorTableData0_GREEN_Msk (0xfful << DISP_OverlayIndexColorTableData0_GREEN_Pos) /*!< DISP_T::OverlayIndexColorTableData0: GREEN Mask*/ + +#define DISP_OverlayIndexColorTableData0_RED_Pos (16) /*!< DISP_T::OverlayIndexColorTableData0: RED Position*/ +#define DISP_OverlayIndexColorTableData0_RED_Msk (0xfful << DISP_OverlayIndexColorTableData0_RED_Pos) /*!< DISP_T::OverlayIndexColorTableData0: RED Mask*/ + +#define DISP_OverlayIndexColorTableData0_ALPHA_Pos (24) /*!< DISP_T::OverlayIndexColorTableData0: ALPHA Position*/ +#define DISP_OverlayIndexColorTableData0_ALPHA_Msk (0xfful << DISP_OverlayIndexColorTableData0_ALPHA_Pos) /*!< DISP_T::OverlayIndexColorTableData0: ALPHA Mask*/ + +#define DISP_FrameBufferClearValue0_BLUE_Pos (0) /*!< DISP_T::FrameBufferClearValue0: BLUE Position*/ +#define DISP_FrameBufferClearValue0_BLUE_Msk (0xfful << DISP_FrameBufferClearValue0_BLUE_Pos) /*!< DISP_T::FrameBufferClearValue0: BLUE Mask*/ + +#define DISP_FrameBufferClearValue0_GREEN_Pos (8) /*!< DISP_T::FrameBufferClearValue0: GREEN Position*/ +#define DISP_FrameBufferClearValue0_GREEN_Msk (0xfful << DISP_FrameBufferClearValue0_GREEN_Pos) /*!< DISP_T::FrameBufferClearValue0: GREEN Mask*/ + +#define DISP_FrameBufferClearValue0_RED_Pos (16) /*!< DISP_T::FrameBufferClearValue0: RED Position*/ +#define DISP_FrameBufferClearValue0_RED_Msk (0xfful << DISP_FrameBufferClearValue0_RED_Pos) /*!< DISP_T::FrameBufferClearValue0: RED Mask*/ + +#define DISP_FrameBufferClearValue0_ALPHA_Pos (24) /*!< DISP_T::FrameBufferClearValue0: ALPHA Position*/ +#define DISP_FrameBufferClearValue0_ALPHA_Msk (0xfful << DISP_FrameBufferClearValue0_ALPHA_Pos) /*!< DISP_T::FrameBufferClearValue0: ALPHA Mask*/ + +#define DISP_ModuleClockGatingControl0_DISABLE_MODULE_CLOCK_GATING_VIDEO_Pos (0) /*!< DISP_T::ModuleClockGatingControl0: DISABLE_MODULE_CLOCK_GATING_VIDEO Position*/ +#define DISP_ModuleClockGatingControl0_DISABLE_MODULE_CLOCK_GATING_VIDEO_Msk (0x1ul << DISP_ModuleClockGatingControl0_DISABLE_MODULE_CLOCK_GATING_VIDEO_Pos) /*!< DISP_T::ModuleClockGatingControl0: DISABLE_MODULE_CLOCK_GATING_VIDEO Mask*/ + +#define DISP_ModuleClockGatingControl0_DISABLE_MODULE_CLOCK_GATING_OVERLAY0_Pos (1) /*!< DISP_T::ModuleClockGatingControl0: DISABLE_MODULE_CLOCK_GATING_OVERLAY0 Position*/ +#define DISP_ModuleClockGatingControl0_DISABLE_MODULE_CLOCK_GATING_OVERLAY0_Msk (0x1ul << DISP_ModuleClockGatingControl0_DISABLE_MODULE_CLOCK_GATING_OVERLAY0_Pos) /*!< DISP_T::ModuleClockGatingControl0: DISABLE_MODULE_CLOCK_GATING_OVERLAY0 Mask*/ + +#define DISP_ModuleClockGatingControl0_DISABLE_MODULE_CLOCK_GATING_WB_FIFO_Pos (9) /*!< DISP_T::ModuleClockGatingControl0: DISABLE_MODULE_CLOCK_GATING_WB_FIFO Position*/ +#define DISP_ModuleClockGatingControl0_DISABLE_MODULE_CLOCK_GATING_WB_FIFO_Msk (0x1ul << DISP_ModuleClockGatingControl0_DISABLE_MODULE_CLOCK_GATING_WB_FIFO_Pos) /*!< DISP_T::ModuleClockGatingControl0: DISABLE_MODULE_CLOCK_GATING_WB_FIFO Mask*/ + +#define DISP_LatencyCounter0_COUNTER_Pos (0) /*!< DISP_T::LatencyCounter0: COUNTER Position*/ +#define DISP_LatencyCounter0_COUNTER_Msk (0xfffffffful << DISP_LatencyCounter0_COUNTER_Pos) /*!< DISP_T::LatencyCounter0: COUNTER Mask*/ + +#define DISP_Qos0_LOW_Pos (0) /*!< DISP_T::Qos0: LOW Position */ +#define DISP_Qos0_LOW_Msk (0xful << DISP_Qos0_LOW_Pos) /*!< DISP_T::Qos0: LOW Mask */ + +#define DISP_Qos0_HIGH_Pos (4) /*!< DISP_T::Qos0: HIGH Position */ +#define DISP_Qos0_HIGH_Msk (0xful << DISP_Qos0_HIGH_Pos) /*!< DISP_T::Qos0: HIGH Mask */ + +#define DISP_MpuIntfCmd0_REG_DATA_Pos (0) /*!< DISP_T::MpuIntfCmd0: REG_DATA Position*/ +#define DISP_MpuIntfCmd0_REG_DATA_Msk (0xfffful << DISP_MpuIntfCmd0_REG_DATA_Pos) /*!< DISP_T::MpuIntfCmd0: REG_DATA Mask*/ + +#define DISP_MpuIntfCmd0_READ_COUNT_Pos (24) /*!< DISP_T::MpuIntfCmd0: READ_COUNT Position*/ +#define DISP_MpuIntfCmd0_READ_COUNT_Msk (0x7ul << DISP_MpuIntfCmd0_READ_COUNT_Pos) /*!< DISP_T::MpuIntfCmd0: READ_COUNT Mask*/ + +#define DISP_MpuIntfCmd0_START_Pos (29) /*!< DISP_T::MpuIntfCmd0: START Position*/ +#define DISP_MpuIntfCmd0_START_Msk (0x1ul << DISP_MpuIntfCmd0_START_Pos) /*!< DISP_T::MpuIntfCmd0: START Mask */ + +#define DISP_MpuIntfCmd0_CMD_Pos (30) /*!< DISP_T::MpuIntfCmd0: CMD Position */ +#define DISP_MpuIntfCmd0_CMD_Msk (0x3ul << DISP_MpuIntfCmd0_CMD_Pos) /*!< DISP_T::MpuIntfCmd0: CMD Mask */ + +#define DISP_MpuIntfReadPara00_DATA_Pos (0) /*!< DISP_T::MpuIntfReadPara00: DATA Position*/ +#define DISP_MpuIntfReadPara00_DATA_Msk (0x3fffful << DISP_MpuIntfReadPara00_DATA_Pos) /*!< DISP_T::MpuIntfReadPara00: DATA Mask*/ + +#define DISP_MpuIntfReadPara10_DATA_Pos (0) /*!< DISP_T::MpuIntfReadPara10: DATA Position*/ +#define DISP_MpuIntfReadPara10_DATA_Msk (0x3fffful << DISP_MpuIntfReadPara10_DATA_Pos) /*!< DISP_T::MpuIntfReadPara10: DATA Mask*/ + +#define DISP_MpuIntfReadPara20_DATA_Pos (0) /*!< DISP_T::MpuIntfReadPara20: DATA Position*/ +#define DISP_MpuIntfReadPara20_DATA_Msk (0x3fffful << DISP_MpuIntfReadPara20_DATA_Pos) /*!< DISP_T::MpuIntfReadPara20: DATA Mask*/ + +#define DISP_MpuIntfReadPara30_DATA_Pos (0) /*!< DISP_T::MpuIntfReadPara30: DATA Position*/ +#define DISP_MpuIntfReadPara30_DATA_Msk (0x3fffful << DISP_MpuIntfReadPara30_DATA_Pos) /*!< DISP_T::MpuIntfReadPara30: DATA Mask*/ + +#define DISP_MpuIntfReadPara40_DATA_Pos (0) /*!< DISP_T::MpuIntfReadPara40: DATA Position*/ +#define DISP_MpuIntfReadPara40_DATA_Msk (0x3fffful << DISP_MpuIntfReadPara40_DATA_Pos) /*!< DISP_T::MpuIntfReadPara40: DATA Mask*/ + +#define DISP_MpuIntfReadStatus0_DATA_Pos (0) /*!< DISP_T::MpuIntfReadStatus0: DATA Position*/ +#define DISP_MpuIntfReadStatus0_DATA_Msk (0x1ul << DISP_MpuIntfReadStatus0_DATA_Pos) /*!< DISP_T::MpuIntfReadStatus0: DATA Mask*/ + +#define DISP_MpuIntfConfig0_REGISTER_MODE_Pos (0) /*!< DISP_T::MpuIntfConfig0: REGISTER_MODE Position*/ +#define DISP_MpuIntfConfig0_REGISTER_MODE_Msk (0x1ul << DISP_MpuIntfConfig0_REGISTER_MODE_Pos) /*!< DISP_T::MpuIntfConfig0: REGISTER_MODE Mask*/ + +#define DISP_MpuIntfConfig0_DATA_BUS_WIDTH_Pos (1) /*!< DISP_T::MpuIntfConfig0: DATA_BUS_WIDTH Position*/ +#define DISP_MpuIntfConfig0_DATA_BUS_WIDTH_Msk (0x3ul << DISP_MpuIntfConfig0_DATA_BUS_WIDTH_Pos) /*!< DISP_T::MpuIntfConfig0: DATA_BUS_WIDTH Mask*/ + +#define DISP_MpuIntfConfig0_DATA_BUS_MODE_Pos (3) /*!< DISP_T::MpuIntfConfig0: DATA_BUS_MODE Position*/ +#define DISP_MpuIntfConfig0_DATA_BUS_MODE_Msk (0x1ul << DISP_MpuIntfConfig0_DATA_BUS_MODE_Pos) /*!< DISP_T::MpuIntfConfig0: DATA_BUS_MODE Mask*/ + +#define DISP_MpuIntfConfig0_INTERFACE_MODE_Pos (4) /*!< DISP_T::MpuIntfConfig0: INTERFACE_MODE Position*/ +#define DISP_MpuIntfConfig0_INTERFACE_MODE_Msk (0x1ul << DISP_MpuIntfConfig0_INTERFACE_MODE_Pos) /*!< DISP_T::MpuIntfConfig0: INTERFACE_MODE Mask*/ + +#define DISP_MpuIntfConfig0_ENABLE_VSYNC_Pos (5) /*!< DISP_T::MpuIntfConfig0: ENABLE_VSYNC Position*/ +#define DISP_MpuIntfConfig0_ENABLE_VSYNC_Msk (0x1ul << DISP_MpuIntfConfig0_ENABLE_VSYNC_Pos) /*!< DISP_T::MpuIntfConfig0: ENABLE_VSYNC Mask*/ + +#define DISP_MpuIntfConfig0_VSYNC_POLARITY_Pos (6) /*!< DISP_T::MpuIntfConfig0: VSYNC_POLARITY Position*/ +#define DISP_MpuIntfConfig0_VSYNC_POLARITY_Msk (0x1ul << DISP_MpuIntfConfig0_VSYNC_POLARITY_Pos) /*!< DISP_T::MpuIntfConfig0: VSYNC_POLARITY Mask*/ + +#define DISP_MpuIntfConfig0_ENABLE_TE_Pos (7) /*!< DISP_T::MpuIntfConfig0: ENABLE_TE Position*/ +#define DISP_MpuIntfConfig0_ENABLE_TE_Msk (0x1ul << DISP_MpuIntfConfig0_ENABLE_TE_Pos) /*!< DISP_T::MpuIntfConfig0: ENABLE_TE Mask*/ + +#define DISP_MpuIntfConfig0_TE_POLARITY_Pos (8) /*!< DISP_T::MpuIntfConfig0: TE_POLARITY Position*/ +#define DISP_MpuIntfConfig0_TE_POLARITY_Msk (0x1ul << DISP_MpuIntfConfig0_TE_POLARITY_Pos) /*!< DISP_T::MpuIntfConfig0: TE_POLARITY Mask*/ + +#define DISP_MpuIntfConfig0_DCX_POLARITY_Pos (9) /*!< DISP_T::MpuIntfConfig0: DCX_POLARITY Position*/ +#define DISP_MpuIntfConfig0_DCX_POLARITY_Msk (0x1ul << DISP_MpuIntfConfig0_DCX_POLARITY_Pos) /*!< DISP_T::MpuIntfConfig0: DCX_POLARITY Mask*/ + +#define DISP_MpuIntfConfig0_DATA_MODE24_BIT_Pos (10) /*!< DISP_T::MpuIntfConfig0: DATA_MODE24_BIT Position*/ +#define DISP_MpuIntfConfig0_DATA_MODE24_BIT_Msk (0x1ul << DISP_MpuIntfConfig0_DATA_MODE24_BIT_Pos) /*!< DISP_T::MpuIntfConfig0: DATA_MODE24_BIT Mask*/ + +#define DISP_MpuIntfConfig0_INTERFACE_RESET_Pos (11) /*!< DISP_T::MpuIntfConfig0: INTERFACE_RESET Position*/ +#define DISP_MpuIntfConfig0_INTERFACE_RESET_Msk (0x1ul << DISP_MpuIntfConfig0_INTERFACE_RESET_Pos) /*!< DISP_T::MpuIntfConfig0: INTERFACE_RESET Mask*/ + +#define DISP_MpuIntfConfig0_ENABLE_MPU_INTF_Pos (12) /*!< DISP_T::MpuIntfConfig0: ENABLE_MPU_INTF Position*/ +#define DISP_MpuIntfConfig0_ENABLE_MPU_INTF_Msk (0x1ul << DISP_MpuIntfConfig0_ENABLE_MPU_INTF_Pos) /*!< DISP_T::MpuIntfConfig0: ENABLE_MPU_INTF Mask*/ + +#define DISP_MpuIntfFrame0_FRAME_UPDATE_Pos (0) /*!< DISP_T::MpuIntfFrame0: FRAME_UPDATE Position*/ +#define DISP_MpuIntfFrame0_FRAME_UPDATE_Msk (0x1ul << DISP_MpuIntfFrame0_FRAME_UPDATE_Pos) /*!< DISP_T::MpuIntfFrame0: FRAME_UPDATE Mask*/ + +#define DISP_MpuIntfFrame0_DATA_FORMAT_Pos (1) /*!< DISP_T::MpuIntfFrame0: DATA_FORMAT Position*/ +#define DISP_MpuIntfFrame0_DATA_FORMAT_Msk (0x3ul << DISP_MpuIntfFrame0_DATA_FORMAT_Pos) /*!< DISP_T::MpuIntfFrame0: DATA_FORMAT Mask*/ + +#define DISP_MpuIntfFrame0_MPU_WRITE_BACK_Pos (3) /*!< DISP_T::MpuIntfFrame0: MPU_WRITE_BACK Position*/ +#define DISP_MpuIntfFrame0_MPU_WRITE_BACK_Msk (0x1ul << DISP_MpuIntfFrame0_MPU_WRITE_BACK_Pos) /*!< DISP_T::MpuIntfFrame0: MPU_WRITE_BACK Mask*/ + +#define DISP_MpuIntfACWrI800_WR_PERIOD_I80_Pos (0) /*!< DISP_T::MpuIntfACWrI800: WR_PERIOD_I80 Position*/ +#define DISP_MpuIntfACWrI800_WR_PERIOD_I80_Msk (0x3fful << DISP_MpuIntfACWrI800_WR_PERIOD_I80_Pos) /*!< DISP_T::MpuIntfACWrI800: WR_PERIOD_I80 Mask*/ + +#define DISP_MpuIntfACWrI800_WRX_ASSERT_Pos (10) /*!< DISP_T::MpuIntfACWrI800: WRX_ASSERT Position*/ +#define DISP_MpuIntfACWrI800_WRX_ASSERT_Msk (0x3fful << DISP_MpuIntfACWrI800_WRX_ASSERT_Pos) /*!< DISP_T::MpuIntfACWrI800: WRX_ASSERT Mask*/ + +#define DISP_MpuIntfACWrI800_WRX_DE_ASSERT_Pos (20) /*!< DISP_T::MpuIntfACWrI800: WRX_DE_ASSERT Position*/ +#define DISP_MpuIntfACWrI800_WRX_DE_ASSERT_Msk (0x3fful << DISP_MpuIntfACWrI800_WRX_DE_ASSERT_Pos) /*!< DISP_T::MpuIntfACWrI800: WRX_DE_ASSERT Mask*/ + +#define DISP_MpuIntfACRdI800_RD_PERIOD_I80_Pos (0) /*!< DISP_T::MpuIntfACRdI800: RD_PERIOD_I80 Position*/ +#define DISP_MpuIntfACRdI800_RD_PERIOD_I80_Msk (0x3fful << DISP_MpuIntfACRdI800_RD_PERIOD_I80_Pos) /*!< DISP_T::MpuIntfACRdI800: RD_PERIOD_I80 Mask*/ + +#define DISP_MpuIntfACRdI800_RDX_ASSERT_Pos (10) /*!< DISP_T::MpuIntfACRdI800: RDX_ASSERT Position*/ +#define DISP_MpuIntfACRdI800_RDX_ASSERT_Msk (0x3fful << DISP_MpuIntfACRdI800_RDX_ASSERT_Pos) /*!< DISP_T::MpuIntfACRdI800: RDX_ASSERT Mask*/ + +#define DISP_MpuIntfACRdI800_RDX_DE_ASSERT_Pos (20) /*!< DISP_T::MpuIntfACRdI800: RDX_DE_ASSERT Position*/ +#define DISP_MpuIntfACRdI800_RDX_DE_ASSERT_Msk (0x3fful << DISP_MpuIntfACRdI800_RDX_DE_ASSERT_Pos) /*!< DISP_T::MpuIntfACRdI800: RDX_DE_ASSERT Mask*/ + +#define DISP_MpuIntfACWrM680_WR_PERIOD_M68_Pos (0) /*!< DISP_T::MpuIntfACWrM680: WR_PERIOD_M68 Position*/ +#define DISP_MpuIntfACWrM680_WR_PERIOD_M68_Msk (0x3fful << DISP_MpuIntfACWrM680_WR_PERIOD_M68_Pos) /*!< DISP_T::MpuIntfACWrM680: WR_PERIOD_M68 Mask*/ + +#define DISP_MpuIntfACWrM680_WR_EASSERT_Pos (10) /*!< DISP_T::MpuIntfACWrM680: WR_EASSERT Position*/ +#define DISP_MpuIntfACWrM680_WR_EASSERT_Msk (0x3fful << DISP_MpuIntfACWrM680_WR_EASSERT_Pos) /*!< DISP_T::MpuIntfACWrM680: WR_EASSERT Mask*/ + +#define DISP_MpuIntfACWrM680_WR_EDE_ASSERT_Pos (20) /*!< DISP_T::MpuIntfACWrM680: WR_EDE_ASSERT Position*/ +#define DISP_MpuIntfACWrM680_WR_EDE_ASSERT_Msk (0x3fful << DISP_MpuIntfACWrM680_WR_EDE_ASSERT_Pos) /*!< DISP_T::MpuIntfACWrM680: WR_EDE_ASSERT Mask*/ + +#define DISP_MpuIntfACRdM680_RD_PERIOD_I80_Pos (0) /*!< DISP_T::MpuIntfACRdM680: RD_PERIOD_I80 Position*/ +#define DISP_MpuIntfACRdM680_RD_PERIOD_I80_Msk (0x3fful << DISP_MpuIntfACRdM680_RD_PERIOD_I80_Pos) /*!< DISP_T::MpuIntfACRdM680: RD_PERIOD_I80 Mask*/ + +#define DISP_MpuIntfACRdM680_RDX_ASSERT_Pos (10) /*!< DISP_T::MpuIntfACRdM680: RDX_ASSERT Position*/ +#define DISP_MpuIntfACRdM680_RDX_ASSERT_Msk (0x3fful << DISP_MpuIntfACRdM680_RDX_ASSERT_Pos) /*!< DISP_T::MpuIntfACRdM680: RDX_ASSERT Mask*/ + +#define DISP_MpuIntfACRdM680_RDX_DE_ASSERT_Pos (20) /*!< DISP_T::MpuIntfACRdM680: RDX_DE_ASSERT Position*/ +#define DISP_MpuIntfACRdM680_RDX_DE_ASSERT_Msk (0x3fful << DISP_MpuIntfACRdM680_RDX_DE_ASSERT_Pos) /*!< DISP_T::MpuIntfACRdM680: RDX_DE_ASSERT Mask*/ + +#define DISP_MpuIntfACVsyncCSX0_CSX_ASSERT_Pos (0) /*!< DISP_T::MpuIntfACVsyncCSX0: CSX_ASSERT Position*/ +#define DISP_MpuIntfACVsyncCSX0_CSX_ASSERT_Msk (0x3fful << DISP_MpuIntfACVsyncCSX0_CSX_ASSERT_Pos) /*!< DISP_T::MpuIntfACVsyncCSX0: CSX_ASSERT Mask*/ + +/**@}*/ /* DISP_CONST */ +/**@}*/ /* end of DISP register group */ +/**@}*/ /* end of REGISTER group */ + +#if defined ( __CC_ARM ) + #pragma no_anon_unions +#endif + +#endif //__DISP_REG_H__ diff --git a/bsp/nuvoton/libraries/ma35/Device/Nuvoton/MA35D1/Include/dpm_reg.h b/bsp/nuvoton/libraries/ma35/Device/Nuvoton/MA35D1/Include/dpm_reg.h new file mode 100644 index 0000000000..3f056d4596 --- /dev/null +++ b/bsp/nuvoton/libraries/ma35/Device/Nuvoton/MA35D1/Include/dpm_reg.h @@ -0,0 +1,315 @@ +/**************************************************************************//** + * @file dpm_reg.h + * @brief DPM register definition header file + * + * SPDX-License-Identifier: Apache-2.0 + * @copyright (C) 2020 Nuvoton Technology Corp. All rights reserved. + *****************************************************************************/ +#ifndef __DPM_REG_H__ +#define __DPM_REG_H__ + +#if defined ( __CC_ARM ) + #pragma anon_unions +#endif + +/** + @addtogroup REGISTER Control Register + @{ +*/ + +/*---------------------- Debug Protection Mechanism -------------------------*/ +/** + @addtogroup DPM Debug Protection Mechanism(DPM) + Memory Mapped Structure for DPM Controller +@{ */ + +typedef struct +{ + + + /** + * @var DPM_T::A35SDS + * Offset: 0x10 DPM A35 Secure Debug State Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[0] |REGDEN |Debug State Register Enable Bit + * | | |0 = Set the debug state to CLOSE state when current state is OPEN state. + * | | |1 = Set the debug state to OPEN state when current state is CLOSE state. + * | | |Note: if SINFAEN.SSPCC is set to high. This bit becomes read-only by Non-Secure software + * |[1] |ODIS |Debug State OTP Disable Bit (Read Only) + * | | |Indicate the Disable bit stored in OTP. + * |[2] |OLOCK |Debug State OTP Lock Bit (Read Only) + * | | |Indicate the Lock bit stored in OTP. + * |[31:24] |VCODE |Write Verify Code and Read Verify Code + * | | |Read operation: + * | | |0xA5 = The read access for DPM_CTL is correct. + * | | |Others = The read access for DPM_CTL is incorrect. + * | | |Write operation: + * | | |0x5A = The write verify code, which is needed to do a valid write to DPM_CA35SDS. + * | | |Others = Invalid write verify code. + * @var DPM_T::A35SNDS + * Offset: 0x14 DPM A35 Secure Non-invasive Debug State Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[0] |REGDEN |Debug State Register Enable Bit + * | | |0 = Set the debug state to CLOSE state when current state is OPEN state. + * | | |1 = Set the debug state to OPEN state when current state is CLOSE state. + * | | |Note: if SINFAEN.SSPCC is set to high. This bit becomes read-only by Non-Secure software + * |[1] |ODIS |Debug State OTP Disable Bit (Read Only) + * | | |Indicate the Disable bit stored in OTP. + * |[2] |OLOCK |Debug State OTP Lock Bit (Read Only) + * | | |Indicate the Lock bit stored in OTP. + * |[31:24] |VCODE |Write Verify Code and Read Verify Code + * | | |Read operation: + * | | |0xA5 = The read access for DPM_CTL is correct. + * | | |Others = The read access for DPM_CTL is incorrect. + * | | |Write operation: + * | | |0x5A = The write verify code, which is needed to do a valid write to DPM_CA35SDS. + * | | |Others = Invalid write verify code. + * @var DPM_T::A35NSDS + * Offset: 0x18 DPM A35 Non-secure Debug State Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[0] |REGDEN |Debug State Register Enable Bit + * | | |0 = Set the debug state to CLOSE state when current state is OPEN state. + * | | |1 = Set the debug state to OPEN state when current state is CLOSE state. + * | | |Note: if SINFAEN.SSPCC is set to high. This bit becomes read-only by Non-Secure software + * |[1] |ODIS |Debug State OTP Disable Bit (Read Only) + * | | |Indicate the Disable bit stored in OTP. + * |[2] |OLOCK |Debug State OTP Lock Bit (Read Only) + * | | |Indicate the Lock bit stored in OTP. + * |[31:24] |VCODE |Write Verify Code and Read Verify Code + * | | |Read operation: + * | | |0xA5 = The read access for DPM_CTL is correct. + * | | |Others = The read access for DPM_CTL is incorrect. + * | | |Write operation: + * | | |0x5A = The write verify code, which is needed to do a valid write to DPM_CA35SDS. + * | | |Others = Invalid write verify code. + * @var DPM_T::A35NSNDS + * Offset: 0x1C DPM A35 Non-secure Non-invasive Debug State Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[0] |REGDEN |Debug State Register Enable Bit + * | | |0 = Set the debug state to CLOSE state when current state is OPEN state. + * | | |1 = Set the debug state to OPEN state when current state is CLOSE state. + * | | |Note: if SINFAEN.SSPCC is set to high. This bit becomes read-only by Non-Secure software + * |[1] |ODIS |Debug State OTP Disable Bit (Read Only) + * | | |Indicate the Disable bit stored in OTP. + * |[2] |OLOCK |Debug State OTP Lock Bit (Read Only) + * | | |Indicate the Lock bit stored in OTP. + * |[31:24] |VCODE |Write Verify Code and Read Verify Code + * | | |Read operation: + * | | |0xA5 = The read access for DPM_CTL is correct. + * | | |Others = The read access for DPM_CTL is incorrect. + * | | |Write operation: + * | | |0x5A = The write verify code, which is needed to do a valid write to DPM_CA35SDS. + * | | |Others = Invalid write verify code. + * @var DPM_T::M4DS + * Offset: 0x20 DPM M4 Debug State Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[0] |REGDEN |Debug State Register Enable Bit + * | | |0 = Set the debug state to CLOSE state when current state is OPEN state. + * | | |1 = Set the debug state to OPEN state when current state is CLOSE state. + * | | |Note: if SINFAEN.SSPCC is set to high. This bit becomes read-only by Non-Secure software + * |[1] |ODIS |Debug State OTP Disable Bit (Read Only) + * | | |Indicate the Disable bit stored in OTP. + * |[2] |OLOCK |Debug State OTP Lock Bit (Read Only) + * | | |Indicate the Lock bit stored in OTP. + * |[31:24] |VCODE |Write Verify Code and Read Verify Code + * | | |Read operation: + * | | |0xA5 = The read access for DPM_CTL is correct. + * | | |Others = The read access for DPM_CTL is incorrect. + * | | |Write operation: + * | | |0x5A = The write verify code, which is needed to do a valid write to DPM_CA35SDS. + * | | |Others = Invalid write verify code. + * @var DPM_T::M4NDS + * Offset: 0x24 DPM M4 Non-invasive Debug State Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[0] |REGDEN |Debug State Register Enable Bit + * | | |0 = Set the debug state to CLOSE state when current state is OPEN state. + * | | |1 = Set the debug state to OPEN state when current state is CLOSE state. + * | | |Note: if SINFAEN.SSPCC is set to high. This bit becomes read-only by Non-Secure software + * |[1] |ODIS |Debug State OTP Disable Bit (Read Only) + * | | |Indicate the Disable bit stored in OTP. + * |[2] |OLOCK |Debug State OTP Lock Bit (Read Only) + * | | |Indicate the Lock bit stored in OTP. + * |[31:24] |VCODE |Write Verify Code and Read Verify Code + * | | |Read operation: + * | | |0xA5 = The read access for DPM_CTL is correct. + * | | |Others = The read access for DPM_CTL is incorrect. + * | | |Write operation: + * | | |0x5A = The write verify code, which is needed to do a valid write to DPM_CA35SDS. + * | | |Others = Invalid write verify code. + * @var DPM_T::EXTDS + * Offset: 0x30 DPM External Debug State Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[0] |REGDEN |Debug State Register Enable Bit + * | | |0 = Set the debug state to CLOSE state when current state is OPEN state. + * | | |1 = Set the debug state to OPEN state when current state is CLOSE state. + * | | |Note: if SINFAEN.SSPCC is set to high. This bit becomes read-only by Non-Secure software + * |[1] |ODIS |Debug State OTP Disable Bit (Read Only) + * | | |Indicate the Disable bit stored in OTP. + * |[2] |OLOCK |Debug State OTP Lock Bit (Read Only) + * | | |Indicate the Lock bit stored in OTP. + * |[31:24] |VCODE |Write Verify Code and Read Verify Code + * | | |Read operation: + * | | |0xA5 = The read access for DPM_CTL is correct. + * | | |Others = The read access for DPM_CTL is incorrect. + * | | |Write operation: + * | | |0x5A = The write verify code, which is needed to do a valid write to DPM_CA35SDS. + * | | |Others = Invalid write verify code. + * @var DPM_T::EXTTDS + * Offset: 0x34 DPM External Tracing Debug State Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[0] |REGDEN |Debug State Register Enable Bit + * | | |0 = Set the debug state to CLOSE state when current state is OPEN state. + * | | |1 = Set the debug state to OPEN state when current state is CLOSE state. + * | | |Note: if SINFAEN.SSPCC is set to high. This bit becomes read-only by Non-Secure software + * |[1] |ODIS |Debug State OTP Disable Bit (Read Only) + * | | |Indicate the Disable bit stored in OTP. + * |[2] |OLOCK |Debug State OTP Lock Bit (Read Only) + * | | |Indicate the Lock bit stored in OTP. + * |[31:24] |VCODE |Write Verify Code and Read Verify Code + * | | |Read operation: + * | | |0xA5 = The read access for DPM_CTL is correct. + * | | |Others = The read access for DPM_CTL is incorrect. + * | | |Write operation: + * | | |0x5A = The write verify code, which is needed to do a valid write to DPM_CA35SDS. + * | | |Others = Invalid write verify code. + */ + __I uint32_t RESERVE0[4]; + __IO uint32_t A35SDS; /*!< [0x0010] DPM A35 Secure Debug State Register */ + __IO uint32_t A35SNDS; /*!< [0x0014] DPM A35 Secure Non-invasive Debug State Register */ + __IO uint32_t A35NSDS; /*!< [0x0018] DPM A35 Non-secure Debug State Register */ + __IO uint32_t A35NSNDS; /*!< [0x001c] DPM A35 Non-secure Non-invasive Debug State Register */ + __IO uint32_t M4DS; /*!< [0x0020] DPM M4 Debug State Register */ + __IO uint32_t M4NDS; /*!< [0x0024] DPM M4 Non-invasive Debug State Register */ + __I uint32_t RESERVE1[2]; + __IO uint32_t EXTDS; /*!< [0x0030] DPM External Debug State Register */ + __IO uint32_t EXTTDS; /*!< [0x0034] DPM External Tracing Debug State Register */ + +} DPM_T; + +/** + @addtogroup DPM_CONST DPM Bit Field Definition + Constant Definitions for DPM Controller +@{ */ + +#define DPM_A35SDS_REGDEN_Pos (0) /*!< DPM_T::A35SDS: REGDEN Position */ +#define DPM_A35SDS_REGDEN_Msk (0x1ul << DPM_A35SDS_REGDEN_Pos) /*!< DPM_T::A35SDS: REGDEN Mask */ + +#define DPM_A35SDS_ODIS_Pos (1) /*!< DPM_T::A35SDS: ODIS Position */ +#define DPM_A35SDS_ODIS_Msk (0x1ul << DPM_A35SDS_ODIS_Pos) /*!< DPM_T::A35SDS: ODIS Mask */ + +#define DPM_A35SDS_OLOCK_Pos (2) /*!< DPM_T::A35SDS: OLOCK Position */ +#define DPM_A35SDS_OLOCK_Msk (0x1ul << DPM_A35SDS_OLOCK_Pos) /*!< DPM_T::A35SDS: OLOCK Mask */ + +#define DPM_A35SDS_VCODE_Pos (24) /*!< DPM_T::A35SDS: VCODE Position */ +#define DPM_A35SDS_VCODE_Msk (0xfful << DPM_A35SDS_VCODE_Pos) /*!< DPM_T::A35SDS: VCODE Mask */ + +#define DPM_A35SNDS_REGDEN_Pos (0) /*!< DPM_T::A35SNDS: REGDEN Position */ +#define DPM_A35SNDS_REGDEN_Msk (0x1ul << DPM_A35SNDS_REGDEN_Pos) /*!< DPM_T::A35SNDS: REGDEN Mask */ + +#define DPM_A35SNDS_ODIS_Pos (1) /*!< DPM_T::A35SNDS: ODIS Position */ +#define DPM_A35SNDS_ODIS_Msk (0x1ul << DPM_A35SNDS_ODIS_Pos) /*!< DPM_T::A35SNDS: ODIS Mask */ + +#define DPM_A35SNDS_OLOCK_Pos (2) /*!< DPM_T::A35SNDS: OLOCK Position */ +#define DPM_A35SNDS_OLOCK_Msk (0x1ul << DPM_A35SNDS_OLOCK_Pos) /*!< DPM_T::A35SNDS: OLOCK Mask */ + +#define DPM_A35SNDS_VCODE_Pos (24) /*!< DPM_T::A35SNDS: VCODE Position */ +#define DPM_A35SNDS_VCODE_Msk (0xfful << DPM_A35SNDS_VCODE_Pos) /*!< DPM_T::A35SNDS: VCODE Mask */ + +#define DPM_A35NSDS_REGDEN_Pos (0) /*!< DPM_T::A35NSDS: REGDEN Position */ +#define DPM_A35NSDS_REGDEN_Msk (0x1ul << DPM_A35NSDS_REGDEN_Pos) /*!< DPM_T::A35NSDS: REGDEN Mask */ + +#define DPM_A35NSDS_ODIS_Pos (1) /*!< DPM_T::A35NSDS: ODIS Position */ +#define DPM_A35NSDS_ODIS_Msk (0x1ul << DPM_A35NSDS_ODIS_Pos) /*!< DPM_T::A35NSDS: ODIS Mask */ + +#define DPM_A35NSDS_OLOCK_Pos (2) /*!< DPM_T::A35NSDS: OLOCK Position */ +#define DPM_A35NSDS_OLOCK_Msk (0x1ul << DPM_A35NSDS_OLOCK_Pos) /*!< DPM_T::A35NSDS: OLOCK Mask */ + +#define DPM_A35NSDS_VCODE_Pos (24) /*!< DPM_T::A35NSDS: VCODE Position */ +#define DPM_A35NSDS_VCODE_Msk (0xfful << DPM_A35NSDS_VCODE_Pos) /*!< DPM_T::A35NSDS: VCODE Mask */ + +#define DPM_A35NSNDS_REGDEN_Pos (0) /*!< DPM_T::A35NSNDS: REGDEN Position */ +#define DPM_A35NSNDS_REGDEN_Msk (0x1ul << DPM_A35NSNDS_REGDEN_Pos) /*!< DPM_T::A35NSNDS: REGDEN Mask */ + +#define DPM_A35NSNDS_ODIS_Pos (1) /*!< DPM_T::A35NSNDS: ODIS Position */ +#define DPM_A35NSNDS_ODIS_Msk (0x1ul << DPM_A35NSNDS_ODIS_Pos) /*!< DPM_T::A35NSNDS: ODIS Mask */ + +#define DPM_A35NSNDS_OLOCK_Pos (2) /*!< DPM_T::A35NSNDS: OLOCK Position */ +#define DPM_A35NSNDS_OLOCK_Msk (0x1ul << DPM_A35NSNDS_OLOCK_Pos) /*!< DPM_T::A35NSNDS: OLOCK Mask */ + +#define DPM_A35NSNDS_VCODE_Pos (24) /*!< DPM_T::A35NSNDS: VCODE Position */ +#define DPM_A35NSNDS_VCODE_Msk (0xfful << DPM_A35NSNDS_VCODE_Pos) /*!< DPM_T::A35NSNDS: VCODE Mask */ + +#define DPM_M4DS_REGDEN_Pos (0) /*!< DPM_T::M4DS: REGDEN Position */ +#define DPM_M4DS_REGDEN_Msk (0x1ul << DPM_M4DS_REGDEN_Pos) /*!< DPM_T::M4DS: REGDEN Mask */ + +#define DPM_M4DS_ODIS_Pos (1) /*!< DPM_T::M4DS: ODIS Position */ +#define DPM_M4DS_ODIS_Msk (0x1ul << DPM_M4DS_ODIS_Pos) /*!< DPM_T::M4DS: ODIS Mask */ + +#define DPM_M4DS_OLOCK_Pos (2) /*!< DPM_T::M4DS: OLOCK Position */ +#define DPM_M4DS_OLOCK_Msk (0x1ul << DPM_M4DS_OLOCK_Pos) /*!< DPM_T::M4DS: OLOCK Mask */ + +#define DPM_M4DS_VCODE_Pos (24) /*!< DPM_T::M4DS: VCODE Position */ +#define DPM_M4DS_VCODE_Msk (0xfful << DPM_M4DS_VCODE_Pos) /*!< DPM_T::M4DS: VCODE Mask */ + +#define DPM_M4NDS_REGDEN_Pos (0) /*!< DPM_T::M4NDS: REGDEN Position */ +#define DPM_M4NDS_REGDEN_Msk (0x1ul << DPM_M4NDS_REGDEN_Pos) /*!< DPM_T::M4NDS: REGDEN Mask */ + +#define DPM_M4NDS_ODIS_Pos (1) /*!< DPM_T::M4NDS: ODIS Position */ +#define DPM_M4NDS_ODIS_Msk (0x1ul << DPM_M4NDS_ODIS_Pos) /*!< DPM_T::M4NDS: ODIS Mask */ + +#define DPM_M4NDS_OLOCK_Pos (2) /*!< DPM_T::M4NDS: OLOCK Position */ +#define DPM_M4NDS_OLOCK_Msk (0x1ul << DPM_M4NDS_OLOCK_Pos) /*!< DPM_T::M4NDS: OLOCK Mask */ + +#define DPM_M4NDS_VCODE_Pos (24) /*!< DPM_T::M4NDS: VCODE Position */ +#define DPM_M4NDS_VCODE_Msk (0xfful << DPM_M4NDS_VCODE_Pos) /*!< DPM_T::M4NDS: VCODE Mask */ + +#define DPM_EXTDS_REGDEN_Pos (0) /*!< DPM_T::EXTDS: REGDEN Position */ +#define DPM_EXTDS_REGDEN_Msk (0x1ul << DPM_EXTDS_REGDEN_Pos) /*!< DPM_T::EXTDS: REGDEN Mask */ + +#define DPM_EXTDS_ODIS_Pos (1) /*!< DPM_T::EXTDS: ODIS Position */ +#define DPM_EXTDS_ODIS_Msk (0x1ul << DPM_EXTDS_ODIS_Pos) /*!< DPM_T::EXTDS: ODIS Mask */ + +#define DPM_EXTDS_OLOCK_Pos (2) /*!< DPM_T::EXTDS: OLOCK Position */ +#define DPM_EXTDS_OLOCK_Msk (0x1ul << DPM_EXTDS_OLOCK_Pos) /*!< DPM_T::EXTDS: OLOCK Mask */ + +#define DPM_EXTDS_VCODE_Pos (24) /*!< DPM_T::EXTDS: VCODE Position */ +#define DPM_EXTDS_VCODE_Msk (0xfful << DPM_EXTDS_VCODE_Pos) /*!< DPM_T::EXTDS: VCODE Mask */ + +#define DPM_EXTTDS_REGDEN_Pos (0) /*!< DPM_T::EXTTDS: REGDEN Position */ +#define DPM_EXTTDS_REGDEN_Msk (0x1ul << DPM_EXTTDS_REGDEN_Pos) /*!< DPM_T::EXTTDS: REGDEN Mask */ + +#define DPM_EXTTDS_ODIS_Pos (1) /*!< DPM_T::EXTTDS: ODIS Position */ +#define DPM_EXTTDS_ODIS_Msk (0x1ul << DPM_EXTTDS_ODIS_Pos) /*!< DPM_T::EXTTDS: ODIS Mask */ + +#define DPM_EXTTDS_OLOCK_Pos (2) /*!< DPM_T::EXTTDS: OLOCK Position */ +#define DPM_EXTTDS_OLOCK_Msk (0x1ul << DPM_EXTTDS_OLOCK_Pos) /*!< DPM_T::EXTTDS: OLOCK Mask */ + +#define DPM_EXTTDS_VCODE_Pos (24) /*!< DPM_T::EXTTDS: VCODE Position */ +#define DPM_EXTTDS_VCODE_Msk (0xfful << DPM_EXTTDS_VCODE_Pos) /*!< DPM_T::EXTTDS: VCODE Mask */ + +/**@}*/ /* DPM_CONST */ +/**@}*/ /* end of DPM register group */ +/**@}*/ /* end of REGISTER group */ + +#if defined ( __CC_ARM ) + #pragma no_anon_unions +#endif + +#endif /* __DPM_REG_H__ */ + diff --git a/bsp/nuvoton/libraries/ma35/Device/Nuvoton/MA35D1/Include/eadc_reg.h b/bsp/nuvoton/libraries/ma35/Device/Nuvoton/MA35D1/Include/eadc_reg.h new file mode 100644 index 0000000000..aae9b39239 --- /dev/null +++ b/bsp/nuvoton/libraries/ma35/Device/Nuvoton/MA35D1/Include/eadc_reg.h @@ -0,0 +1,2278 @@ +/**************************************************************************//** + * @file eadc_reg.h + * @brief EADC register definition header file + * + * SPDX-License-Identifier: Apache-2.0 + * @copyright (C) 2020 Nuvoton Technology Corp. All rights reserved. + *****************************************************************************/ +#ifndef __EADC_REG_H__ +#define __EADC_REG_H__ + +#if defined ( __CC_ARM ) + #pragma anon_unions +#endif + +/** + @addtogroup REGISTER Control Register + @{ +*/ + +/** + @addtogroup EADC Enhanced Analog to Digital Converter(EADC) + Memory Mapped Structure for EADC Controller +@{ */ + +typedef struct +{ + + + /** + * @var EADC_T::DAT0 + * Offset: 0x00 ADC Data Register 0 for Sample Module 0 + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[15:0] |RESULT |ADC Conversion Result + * | | |This field contains 12 bits conversion result. + * | | |When DMOF (EADC_CTL[9]) is set to 0, 12-bit ADC conversion result with unsigned format will be filled in RESULT[11:0] and zero will be filled in RESULT[15:12]. + * | | |When DMOF (EADC_CTL[9]) set to 1, 12-bit ADC conversion result with 2's complement format will be filled in RESULT[11:0] and signed bits to will be filled in RESULT[15:12]. + * |[16] |OV |Overrun Flag + * | | |If converted data in RESULT[11:0] has not been read before new conversion result is loaded to this register, OV is set to 1. + * | | |0 = Data in RESULT[11:0] is recent conversion result. + * | | |1 = Data in RESULT[11:0] is overwrite. + * | | |Note: It is cleared by hardware after EADC_DAT register is read. + * |[17] |VALID |Valid Flag + * | | |This bit is set to 1 when corresponding sample module channel analog input conversion is completed and cleared by hardware after EADC_DAT register is read. + * | | |0 = Data in RESULT[11:0] bits is not valid. + * | | |1 = Data in RESULT[11:0] bits is valid. + * @var EADC_T::DAT1 + * Offset: 0x04 ADC Data Register 1 for Sample Module 1 + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[15:0] |RESULT |ADC Conversion Result + * | | |This field contains 12 bits conversion result. + * | | |When DMOF (EADC_CTL[9]) is set to 0, 12-bit ADC conversion result with unsigned format will be filled in RESULT[11:0] and zero will be filled in RESULT[15:12]. + * | | |When DMOF (EADC_CTL[9]) set to 1, 12-bit ADC conversion result with 2's complement format will be filled in RESULT[11:0] and signed bits to will be filled in RESULT[15:12]. + * |[16] |OV |Overrun Flag + * | | |If converted data in RESULT[11:0] has not been read before new conversion result is loaded to this register, OV is set to 1. + * | | |0 = Data in RESULT[11:0] is recent conversion result. + * | | |1 = Data in RESULT[11:0] is overwrite. + * | | |Note: It is cleared by hardware after EADC_DAT register is read. + * |[17] |VALID |Valid Flag + * | | |This bit is set to 1 when corresponding sample module channel analog input conversion is completed and cleared by hardware after EADC_DAT register is read. + * | | |0 = Data in RESULT[11:0] bits is not valid. + * | | |1 = Data in RESULT[11:0] bits is valid. + * @var EADC_T::DAT2 + * Offset: 0x08 ADC Data Register 2 for Sample Module 2 + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[15:0] |RESULT |ADC Conversion Result + * | | |This field contains 12 bits conversion result. + * | | |When DMOF (EADC_CTL[9]) is set to 0, 12-bit ADC conversion result with unsigned format will be filled in RESULT[11:0] and zero will be filled in RESULT[15:12]. + * | | |When DMOF (EADC_CTL[9]) set to 1, 12-bit ADC conversion result with 2's complement format will be filled in RESULT[11:0] and signed bits to will be filled in RESULT[15:12]. + * |[16] |OV |Overrun Flag + * | | |If converted data in RESULT[11:0] has not been read before new conversion result is loaded to this register, OV is set to 1. + * | | |0 = Data in RESULT[11:0] is recent conversion result. + * | | |1 = Data in RESULT[11:0] is overwrite. + * | | |Note: It is cleared by hardware after EADC_DAT register is read. + * |[17] |VALID |Valid Flag + * | | |This bit is set to 1 when corresponding sample module channel analog input conversion is completed and cleared by hardware after EADC_DAT register is read. + * | | |0 = Data in RESULT[11:0] bits is not valid. + * | | |1 = Data in RESULT[11:0] bits is valid. + * @var EADC_T::DAT3 + * Offset: 0x0C ADC Data Register 3 for Sample Module 3 + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[15:0] |RESULT |ADC Conversion Result + * | | |This field contains 12 bits conversion result. + * | | |When DMOF (EADC_CTL[9]) is set to 0, 12-bit ADC conversion result with unsigned format will be filled in RESULT[11:0] and zero will be filled in RESULT[15:12]. + * | | |When DMOF (EADC_CTL[9]) set to 1, 12-bit ADC conversion result with 2's complement format will be filled in RESULT[11:0] and signed bits to will be filled in RESULT[15:12]. + * |[16] |OV |Overrun Flag + * | | |If converted data in RESULT[11:0] has not been read before new conversion result is loaded to this register, OV is set to 1. + * | | |0 = Data in RESULT[11:0] is recent conversion result. + * | | |1 = Data in RESULT[11:0] is overwrite. + * | | |Note: It is cleared by hardware after EADC_DAT register is read. + * |[17] |VALID |Valid Flag + * | | |This bit is set to 1 when corresponding sample module channel analog input conversion is completed and cleared by hardware after EADC_DAT register is read. + * | | |0 = Data in RESULT[11:0] bits is not valid. + * | | |1 = Data in RESULT[11:0] bits is valid. + * @var EADC_T::DAT4 + * Offset: 0x10 ADC Data Register 4 for Sample Module 4 + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[15:0] |RESULT |ADC Conversion Result + * | | |This field contains 12 bits conversion result. + * | | |When DMOF (EADC_CTL[9]) is set to 0, 12-bit ADC conversion result with unsigned format will be filled in RESULT[11:0] and zero will be filled in RESULT[15:12]. + * | | |When DMOF (EADC_CTL[9]) set to 1, 12-bit ADC conversion result with 2's complement format will be filled in RESULT[11:0] and signed bits to will be filled in RESULT[15:12]. + * |[16] |OV |Overrun Flag + * | | |If converted data in RESULT[11:0] has not been read before new conversion result is loaded to this register, OV is set to 1. + * | | |0 = Data in RESULT[11:0] is recent conversion result. + * | | |1 = Data in RESULT[11:0] is overwrite. + * | | |Note: It is cleared by hardware after EADC_DAT register is read. + * |[17] |VALID |Valid Flag + * | | |This bit is set to 1 when corresponding sample module channel analog input conversion is completed and cleared by hardware after EADC_DAT register is read. + * | | |0 = Data in RESULT[11:0] bits is not valid. + * | | |1 = Data in RESULT[11:0] bits is valid. + * @var EADC_T::DAT5 + * Offset: 0x14 ADC Data Register 5 for Sample Module 5 + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[15:0] |RESULT |ADC Conversion Result + * | | |This field contains 12 bits conversion result. + * | | |When DMOF (EADC_CTL[9]) is set to 0, 12-bit ADC conversion result with unsigned format will be filled in RESULT[11:0] and zero will be filled in RESULT[15:12]. + * | | |When DMOF (EADC_CTL[9]) set to 1, 12-bit ADC conversion result with 2's complement format will be filled in RESULT[11:0] and signed bits to will be filled in RESULT[15:12]. + * |[16] |OV |Overrun Flag + * | | |If converted data in RESULT[11:0] has not been read before new conversion result is loaded to this register, OV is set to 1. + * | | |0 = Data in RESULT[11:0] is recent conversion result. + * | | |1 = Data in RESULT[11:0] is overwrite. + * | | |Note: It is cleared by hardware after EADC_DAT register is read. + * |[17] |VALID |Valid Flag + * | | |This bit is set to 1 when corresponding sample module channel analog input conversion is completed and cleared by hardware after EADC_DAT register is read. + * | | |0 = Data in RESULT[11:0] bits is not valid. + * | | |1 = Data in RESULT[11:0] bits is valid. + * @var EADC_T::DAT6 + * Offset: 0x18 ADC Data Register 6 for Sample Module 6 + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[15:0] |RESULT |ADC Conversion Result + * | | |This field contains 12 bits conversion result. + * | | |When DMOF (EADC_CTL[9]) is set to 0, 12-bit ADC conversion result with unsigned format will be filled in RESULT[11:0] and zero will be filled in RESULT[15:12]. + * | | |When DMOF (EADC_CTL[9]) set to 1, 12-bit ADC conversion result with 2's complement format will be filled in RESULT[11:0] and signed bits to will be filled in RESULT[15:12]. + * |[16] |OV |Overrun Flag + * | | |If converted data in RESULT[11:0] has not been read before new conversion result is loaded to this register, OV is set to 1. + * | | |0 = Data in RESULT[11:0] is recent conversion result. + * | | |1 = Data in RESULT[11:0] is overwrite. + * | | |Note: It is cleared by hardware after EADC_DAT register is read. + * |[17] |VALID |Valid Flag + * | | |This bit is set to 1 when corresponding sample module channel analog input conversion is completed and cleared by hardware after EADC_DAT register is read. + * | | |0 = Data in RESULT[11:0] bits is not valid. + * | | |1 = Data in RESULT[11:0] bits is valid. + * @var EADC_T::DAT7 + * Offset: 0x1C ADC Data Register 7 for Sample Module 7 + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[15:0] |RESULT |ADC Conversion Result + * | | |This field contains 12 bits conversion result. + * | | |When DMOF (EADC_CTL[9]) is set to 0, 12-bit ADC conversion result with unsigned format will be filled in RESULT[11:0] and zero will be filled in RESULT[15:12]. + * | | |When DMOF (EADC_CTL[9]) set to 1, 12-bit ADC conversion result with 2's complement format will be filled in RESULT[11:0] and signed bits to will be filled in RESULT[15:12]. + * |[16] |OV |Overrun Flag + * | | |If converted data in RESULT[11:0] has not been read before new conversion result is loaded to this register, OV is set to 1. + * | | |0 = Data in RESULT[11:0] is recent conversion result. + * | | |1 = Data in RESULT[11:0] is overwrite. + * | | |Note: It is cleared by hardware after EADC_DAT register is read. + * |[17] |VALID |Valid Flag + * | | |This bit is set to 1 when corresponding sample module channel analog input conversion is completed and cleared by hardware after EADC_DAT register is read. + * | | |0 = Data in RESULT[11:0] bits is not valid. + * | | |1 = Data in RESULT[11:0] bits is valid. + * @var EADC_T::DAT8 + * Offset: 0x20 ADC Data Register 8 for Sample Module 8 + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[15:0] |RESULT |ADC Conversion Result + * | | |This field contains 12 bits conversion result. + * | | |When DMOF (EADC_CTL[9]) is set to 0, 12-bit ADC conversion result with unsigned format will be filled in RESULT[11:0] and zero will be filled in RESULT[15:12]. + * | | |When DMOF (EADC_CTL[9]) set to 1, 12-bit ADC conversion result with 2's complement format will be filled in RESULT[11:0] and signed bits to will be filled in RESULT[15:12]. + * |[16] |OV |Overrun Flag + * | | |If converted data in RESULT[11:0] has not been read before new conversion result is loaded to this register, OV is set to 1. + * | | |0 = Data in RESULT[11:0] is recent conversion result. + * | | |1 = Data in RESULT[11:0] is overwrite. + * | | |Note: It is cleared by hardware after EADC_DAT register is read. + * |[17] |VALID |Valid Flag + * | | |This bit is set to 1 when corresponding sample module channel analog input conversion is completed and cleared by hardware after EADC_DAT register is read. + * | | |0 = Data in RESULT[11:0] bits is not valid. + * | | |1 = Data in RESULT[11:0] bits is valid. + * @var EADC_T::CURDAT + * Offset: 0x4C ADC PDMA Current Transfer Data Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[17:0] |CURDAT |ADC PDMA Current Transfer Data (Read Only) + * | | |This register is a shadow register of EADC_DATn (n=0~8) for PDMA support. + * @var EADC_T::CTL + * Offset: 0x50 ADC Control Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[0] |ADCEN |ADC Converter Enable Bit + * | | |0 = EADC Disabled. + * | | |1 = EADC Enabled. + * | | |Note: Before starting ADC conversion function, this bit should be set to 1 + * | | |Clear it to 0 to disable ADC converter analog circuit power consumption. + * |[1] |ADCRST |ADC Converter Control Circuits Reset + * | | |0 = No effect. + * | | |1 = Cause ADC control circuits reset to initial state, but not change the ADC registers value. + * | | |Note: ADCRST bit remains 1 during ADC reset, when ADC reset end, the ADCRST bit is automatically cleared to 0. + * |[2] |ADCIEN0 |Specific Sample Module ADC ADINT0 Interrupt Enable Bit + * | | |The ADC converter generates a conversion end ADIF0 (EADC_STATUS2[0]) upon the end of specific sample module ADC conversion + * | | |If ADCIEN0 bit is set then conversion end interrupt request ADINT0 is generated. + * | | |0 = Specific sample module ADC ADINT0 interrupt function Disabled. + * | | |1 = Specific sample module ADC ADINT0 interrupt function Enabled. + * |[3] |ADCIEN1 |Specific Sample Module ADC ADINT1 Interrupt Enable Bit + * | | |The ADC converter generates a conversion end ADIF1 (EADC_STATUS2[1]) upon the end of specific sample module ADC conversion + * | | |If ADCIEN1 bit is set then conversion end interrupt request ADINT1 is generated. + * | | |0 = Specific sample module ADC ADINT1 interrupt function Disabled. + * | | |1 = Specific sample module ADC ADINT1 interrupt function Enabled. + * |[4] |ADCIEN2 |Specific Sample Module ADC ADINT2 Interrupt Enable Bit + * | | |The ADC converter generates a conversion end ADIF2 (EADC_STATUS2[2]) upon the end of specific sample module ADC conversion + * | | |If ADCIEN2 bit is set then conversion end interrupt request ADINT2 is generated. + * | | |0 = Specific sample module ADC ADINT2 interrupt function Disabled. + * | | |1 = Specific sample module ADC ADINT2 interrupt function Enabled. + * |[5] |ADCIEN3 |Specific Sample Module ADC ADINT3 Interrupt Enable Bit + * | | |The ADC converter generates a conversion end ADIF3 (EADC_STATUS2[3]) upon the end of specific sample module ADC conversion + * | | |If ADCIEN3 bit is set then conversion end interrupt request ADINT3 is generated. + * | | |0 = Specific sample module ADC ADINT3 interrupt function Disabled. + * | | |1 = Specific sample module ADC ADINT3 interrupt function Enabled. + * |[7:6] |RES |Resolution (Read Only) + * | | |11 = 12-bit ADC result will be put at RESULT (EADC_DATn[11:0]). + * |[8] |DIFFEN |Differential Analog Input Mode Enable Bit + * | | |0 = Single-end analog input mode. + * | | |1 = Differential analog input mode. + * |[9] |DMOF |ADC Differential Input Mode Output Format + * | | |0 = ADC conversion result will be filled in RESULT (EADC_DATn[15:0], where n= 0 ~ 8) with unsigned format. + * | | |1 = ADC conversion result will be filled in RESULT (EADC_DATn[15:0], where n= 0 ~ 8) with 2'complement format. + * |[11:10] |VREFSEL |Internal Voltage Reference Select Bit + * | | |ADC have internal voltage reference, user can control this bit to select reference voltage for ADC + * | | |00 = 1.6V. + * | | |01 = 2.0V. + * | | |10 = 2.5V (AVDD33 >= 2.8V). + * | | |11 = 3.0V (AVDD33 >= 3.3V). + * |[12] |SPEED |Speed Mode Select Bit + * | | |Control signal for ADC conversion speed + * | | |0 = Low speed mode. + * | | |1 = High speed mode. + * @var EADC_T::SWTRG + * Offset: 0x54 ADC Sample Module Software Start Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[8:0] |SWTRG |ADC Sample Module 0~8 Software Force to Start ADC Conversion + * | | |0 = No effect. + * | | |1 = Cause an ADC conversion when the priority is given to sample module. + * | | |Note: After writing this register to start ADC conversion, the EADC_PENDSTS register will show which sample module will conversion + * | | |If user want to disable the conversion of the sample module, user can write EADC_PENDSTS register to clear it. + * @var EADC_T::PENDSTS + * Offset: 0x58 ADC Start of Conversion Pending Flag Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[8:0] |STPF |ADC Sample Module 0~8 Start of Conversion Pending Flag + * | | |Read Operation: + * | | |0 = There is no pending conversion for sample module. + * | | |1 = Sample module ADC start of conversion is pending. + * | | |Write Operation: + * | | |1 = Clear pending flag & cancel the conversion for sample module. + * | | |Note: This bit remains 1 during pending state + * | | |When the respective ADC conversion is ended, the STPFn (n=0~8) bit is automatically cleared to 0 + * @var EADC_T::OVSTS + * Offset: 0x5C ADC Sample Module Start of Conversion Overrun Flag Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[8:0] |SPOVF |ADC SAMPLE0~8 Overrun Flag + * | | |0 = No sample module event overrun. + * | | |1 = Indicates a new sample module event is generated while an old one event is pending. + * | | |Note: This bit is cleared by writing 1 to it. + * @var EADC_T::SCTL0 + * Offset: 0x80 ADC Sample Module 0 Control Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[3:0] |CHSEL |ADC Sample Module Channel Selection + * | | |00H = EADC_CH0. + * | | |01H = EADC_CH1. + * | | |02H = EADC_CH2. + * | | |03H = EADC_CH3. + * | | |04H = EADC_CH4. + * | | |05H = EADC_CH5. + * | | |06H = EADC_CH6. + * | | |07H = EADC_CH7. + * | | |08H = VBAT/4. + * |[4] |EXTREN |ADC External Trigger Rising Edge Enable Bit + * | | |0 = Rising edge Disabled when ADC selects EADC0_ST as trigger source. + * | | |1 = Rising edge Enabled when ADC selects EADC0_ST as trigger source. + * |[5] |EXTFEN |ADC External Trigger Falling Edge Enable Bit + * | | |0 = Falling edge Disabled when ADC selects EADC0_ST as trigger source. + * | | |1 = Falling edge Enabled when ADC selects EADC0_ST as trigger source. + * |[7:6] |TRGDLYDIV |ADC Sample Module Start of Conversion Trigger Delay Clock Divider Selection + * | | |Trigger delay clock frequency: + * | | |00 = ADC_CLK/1. + * | | |01 = ADC_CLK/2. + * | | |10 = ADC_CLK/4. + * | | |11 = ADC_CLK/16. + * |[15:8] |TRGDLYCNT |ADC Sample Module Start of Conversion Trigger Delay Time + * | | |Trigger delay time = TRGDLYCNT x ADC_CLK period x n (n=1,2,4,16 from TRGDLYDIV setting). + * | | |Note: If TRGDLYCNT is set to 1, trigger delay time is actually the same as TRGDLYCNT is set to 2 for hardware operation. + * |[21:16] |TRGSEL |ADC Sample Module Start of Conversion Trigger Source Selection + * | | |0H = Disable trigger. + * | | |1H = External trigger from EADC0_ST pin input. + * | | |2H = ADC ADINT0 interrupt EOC (End of conversion) pulse trigger. + * | | |3H = ADC ADINT1 interrupt EOC (End of conversion) pulse trigger. + * | | |4H = Timer0 overflow pulse trigger. + * | | |5H = Timer1 overflow pulse trigger. + * | | |6H = Timer2 overflow pulse trigger. + * | | |7H = Timer3 overflow pulse trigger. + * | | |8H = Timer4 overflow pulse trigger. + * | | |9H = Timer5 overflow pulse trigger. + * | | |AH = Timer6 overflow pulse trigger. + * | | |BH = Timer7 overflow pulse trigger. + * | | |CH = Timer8 overflow pulse trigger. + * | | |DH = Timer9 overflow pulse trigger. + * | | |EH = Timer10 overflow pulse trigger. + * | | |FH = Timer11 overflow pulse trigger. + * | | |10H = EPWM0TG0. + * | | |11H = EPWM0TG1. + * | | |12H = EPWM0TG2. + * | | |13H = EPWM0TG3. + * | | |14H = EPWM0TG4. + * | | |15H = EPWM0TG5. + * | | |16H = EPWM1TG0. + * | | |17H = EPWM1TG1. + * | | |18H = EPWM1TG2. + * | | |19H = EPWM1TG3. + * | | |1AH = EPWM1TG4. + * | | |1BH = EPWM1TG5. + * | | |1CH = EPWM2TG0. + * | | |1DH = EPWM2TG1. + * | | |1EH = EPWM2TG2. + * | | |1FH = EPWM2TG3. + * | | |20H = EPWM2TG4. + * | | |21H = EPWM2TG5. + * | | |other = Reserved. + * |[22] |INTPOS |Interrupt Flag Position Select + * | | |0 = Set ADIFn (EADC_STATUS2[n], n=0~3) at ADC end of conversion. + * | | |1 = Set ADIFn (EADC_STATUS2[n], n=0~3) at ADC start of conversion. + * |[23] |DBMEN |Double Buffer Mode Enable Bit + * | | |0 = Sample has one sample result register (default). + * | | |1 = Sample has two sample result registers. + * @var EADC_T::SCTL1 + * Offset: 0x84 ADC Sample Module 1 Control Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[3:0] |CHSEL |ADC Sample Module Channel Selection + * | | |00H = EADC_CH0. + * | | |01H = EADC_CH1. + * | | |02H = EADC_CH2. + * | | |03H = EADC_CH3. + * | | |04H = EADC_CH4. + * | | |05H = EADC_CH5. + * | | |06H = EADC_CH6. + * | | |07H = EADC_CH7. + * | | |08H = VBAT/4. + * |[4] |EXTREN |ADC External Trigger Rising Edge Enable Bit + * | | |0 = Rising edge Disabled when ADC selects EADC0_ST as trigger source. + * | | |1 = Rising edge Enabled when ADC selects EADC0_ST as trigger source. + * |[5] |EXTFEN |ADC External Trigger Falling Edge Enable Bit + * | | |0 = Falling edge Disabled when ADC selects EADC0_ST as trigger source. + * | | |1 = Falling edge Enabled when ADC selects EADC0_ST as trigger source. + * |[7:6] |TRGDLYDIV |ADC Sample Module Start of Conversion Trigger Delay Clock Divider Selection + * | | |Trigger delay clock frequency: + * | | |00 = ADC_CLK/1. + * | | |01 = ADC_CLK/2. + * | | |10 = ADC_CLK/4. + * | | |11 = ADC_CLK/16. + * |[15:8] |TRGDLYCNT |ADC Sample Module Start of Conversion Trigger Delay Time + * | | |Trigger delay time = TRGDLYCNT x ADC_CLK period x n (n=1,2,4,16 from TRGDLYDIV setting). + * | | |Note: If TRGDLYCNT is set to 1, trigger delay time is actually the same as TRGDLYCNT is set to 2 for hardware operation. + * |[21:16] |TRGSEL |ADC Sample Module Start of Conversion Trigger Source Selection + * | | |0H = Disable trigger. + * | | |1H = External trigger from EADC0_ST pin input. + * | | |2H = ADC ADINT0 interrupt EOC (End of conversion) pulse trigger. + * | | |3H = ADC ADINT1 interrupt EOC (End of conversion) pulse trigger. + * | | |4H = Timer0 overflow pulse trigger. + * | | |5H = Timer1 overflow pulse trigger. + * | | |6H = Timer2 overflow pulse trigger. + * | | |7H = Timer3 overflow pulse trigger. + * | | |8H = Timer4 overflow pulse trigger. + * | | |9H = Timer5 overflow pulse trigger. + * | | |AH = Timer6 overflow pulse trigger. + * | | |BH = Timer7 overflow pulse trigger. + * | | |CH = Timer8 overflow pulse trigger. + * | | |DH = Timer9 overflow pulse trigger. + * | | |EH = Timer10 overflow pulse trigger. + * | | |FH = Timer11 overflow pulse trigger. + * | | |10H = EPWM0TG0. + * | | |11H = EPWM0TG1. + * | | |12H = EPWM0TG2. + * | | |13H = EPWM0TG3. + * | | |14H = EPWM0TG4. + * | | |15H = EPWM0TG5. + * | | |16H = EPWM1TG0. + * | | |17H = EPWM1TG1. + * | | |18H = EPWM1TG2. + * | | |19H = EPWM1TG3. + * | | |1AH = EPWM1TG4. + * | | |1BH = EPWM1TG5. + * | | |1CH = EPWM2TG0. + * | | |1DH = EPWM2TG1. + * | | |1EH = EPWM2TG2. + * | | |1FH = EPWM2TG3. + * | | |20H = EPWM2TG4. + * | | |21H = EPWM2TG5. + * | | |other = Reserved. + * |[22] |INTPOS |Interrupt Flag Position Select + * | | |0 = Set ADIFn (EADC_STATUS2[n], n=0~3) at ADC end of conversion. + * | | |1 = Set ADIFn (EADC_STATUS2[n], n=0~3) at ADC start of conversion. + * |[23] |DBMEN |Double Buffer Mode Enable Bit + * | | |0 = Sample has one sample result register (default). + * | | |1 = Sample has two sample result registers. + * @var EADC_T::SCTL2 + * Offset: 0x88 ADC Sample Module 2 Control Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[3:0] |CHSEL |ADC Sample Module Channel Selection + * | | |00H = EADC_CH0. + * | | |01H = EADC_CH1. + * | | |02H = EADC_CH2. + * | | |03H = EADC_CH3. + * | | |04H = EADC_CH4. + * | | |05H = EADC_CH5. + * | | |06H = EADC_CH6. + * | | |07H = EADC_CH7. + * | | |08H = VBAT/4. + * |[4] |EXTREN |ADC External Trigger Rising Edge Enable Bit + * | | |0 = Rising edge Disabled when ADC selects EADC0_ST as trigger source. + * | | |1 = Rising edge Enabled when ADC selects EADC0_ST as trigger source. + * |[5] |EXTFEN |ADC External Trigger Falling Edge Enable Bit + * | | |0 = Falling edge Disabled when ADC selects EADC0_ST as trigger source. + * | | |1 = Falling edge Enabled when ADC selects EADC0_ST as trigger source. + * |[7:6] |TRGDLYDIV |ADC Sample Module Start of Conversion Trigger Delay Clock Divider Selection + * | | |Trigger delay clock frequency: + * | | |00 = ADC_CLK/1. + * | | |01 = ADC_CLK/2. + * | | |10 = ADC_CLK/4. + * | | |11 = ADC_CLK/16. + * |[15:8] |TRGDLYCNT |ADC Sample Module Start of Conversion Trigger Delay Time + * | | |Trigger delay time = TRGDLYCNT x ADC_CLK period x n (n=1,2,4,16 from TRGDLYDIV setting). + * | | |Note: If TRGDLYCNT is set to 1, trigger delay time is actually the same as TRGDLYCNT is set to 2 for hardware operation. + * |[21:16] |TRGSEL |ADC Sample Module Start of Conversion Trigger Source Selection + * | | |0H = Disable trigger. + * | | |1H = External trigger from EADC0_ST pin input. + * | | |2H = ADC ADINT0 interrupt EOC (End of conversion) pulse trigger. + * | | |3H = ADC ADINT1 interrupt EOC (End of conversion) pulse trigger. + * | | |4H = Timer0 overflow pulse trigger. + * | | |5H = Timer1 overflow pulse trigger. + * | | |6H = Timer2 overflow pulse trigger. + * | | |7H = Timer3 overflow pulse trigger. + * | | |8H = Timer4 overflow pulse trigger. + * | | |9H = Timer5 overflow pulse trigger. + * | | |AH = Timer6 overflow pulse trigger. + * | | |BH = Timer7 overflow pulse trigger. + * | | |CH = Timer8 overflow pulse trigger. + * | | |DH = Timer9 overflow pulse trigger. + * | | |EH = Timer10 overflow pulse trigger. + * | | |FH = Timer11 overflow pulse trigger. + * | | |10H = EPWM0TG0. + * | | |11H = EPWM0TG1. + * | | |12H = EPWM0TG2. + * | | |13H = EPWM0TG3. + * | | |14H = EPWM0TG4. + * | | |15H = EPWM0TG5. + * | | |16H = EPWM1TG0. + * | | |17H = EPWM1TG1. + * | | |18H = EPWM1TG2. + * | | |19H = EPWM1TG3. + * | | |1AH = EPWM1TG4. + * | | |1BH = EPWM1TG5. + * | | |1CH = EPWM2TG0. + * | | |1DH = EPWM2TG1. + * | | |1EH = EPWM2TG2. + * | | |1FH = EPWM2TG3. + * | | |20H = EPWM2TG4. + * | | |21H = EPWM2TG5. + * | | |other = Reserved. + * |[22] |INTPOS |Interrupt Flag Position Select + * | | |0 = Set ADIFn (EADC_STATUS2[n], n=0~3) at ADC end of conversion. + * | | |1 = Set ADIFn (EADC_STATUS2[n], n=0~3) at ADC start of conversion. + * |[23] |DBMEN |Double Buffer Mode Enable Bit + * | | |0 = Sample has one sample result register (default). + * | | |1 = Sample has two sample result registers. + * @var EADC_T::SCTL3 + * Offset: 0x8C ADC Sample Module 3 Control Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[3:0] |CHSEL |ADC Sample Module Channel Selection + * | | |00H = EADC_CH0. + * | | |01H = EADC_CH1. + * | | |02H = EADC_CH2. + * | | |03H = EADC_CH3. + * | | |04H = EADC_CH4. + * | | |05H = EADC_CH5. + * | | |06H = EADC_CH6. + * | | |07H = EADC_CH7. + * | | |08H = VBAT/4. + * |[4] |EXTREN |ADC External Trigger Rising Edge Enable Bit + * | | |0 = Rising edge Disabled when ADC selects EADC0_ST as trigger source. + * | | |1 = Rising edge Enabled when ADC selects EADC0_ST as trigger source. + * |[5] |EXTFEN |ADC External Trigger Falling Edge Enable Bit + * | | |0 = Falling edge Disabled when ADC selects EADC0_ST as trigger source. + * | | |1 = Falling edge Enabled when ADC selects EADC0_ST as trigger source. + * |[7:6] |TRGDLYDIV |ADC Sample Module Start of Conversion Trigger Delay Clock Divider Selection + * | | |Trigger delay clock frequency: + * | | |00 = ADC_CLK/1. + * | | |01 = ADC_CLK/2. + * | | |10 = ADC_CLK/4. + * | | |11 = ADC_CLK/16. + * |[15:8] |TRGDLYCNT |ADC Sample Module Start of Conversion Trigger Delay Time + * | | |Trigger delay time = TRGDLYCNT x ADC_CLK period x n (n=1,2,4,16 from TRGDLYDIV setting). + * | | |Note: If TRGDLYCNT is set to 1, trigger delay time is actually the same as TRGDLYCNT is set to 2 for hardware operation. + * |[21:16] |TRGSEL |ADC Sample Module Start of Conversion Trigger Source Selection + * | | |0H = Disable trigger. + * | | |1H = External trigger from EADC0_ST pin input. + * | | |2H = ADC ADINT0 interrupt EOC (End of conversion) pulse trigger. + * | | |3H = ADC ADINT1 interrupt EOC (End of conversion) pulse trigger. + * | | |4H = Timer0 overflow pulse trigger. + * | | |5H = Timer1 overflow pulse trigger. + * | | |6H = Timer2 overflow pulse trigger. + * | | |7H = Timer3 overflow pulse trigger. + * | | |8H = Timer4 overflow pulse trigger. + * | | |9H = Timer5 overflow pulse trigger. + * | | |AH = Timer6 overflow pulse trigger. + * | | |BH = Timer7 overflow pulse trigger. + * | | |CH = Timer8 overflow pulse trigger. + * | | |DH = Timer9 overflow pulse trigger. + * | | |EH = Timer10 overflow pulse trigger. + * | | |FH = Timer11 overflow pulse trigger. + * | | |10H = EPWM0TG0. + * | | |11H = EPWM0TG1. + * | | |12H = EPWM0TG2. + * | | |13H = EPWM0TG3. + * | | |14H = EPWM0TG4. + * | | |15H = EPWM0TG5. + * | | |16H = EPWM1TG0. + * | | |17H = EPWM1TG1. + * | | |18H = EPWM1TG2. + * | | |19H = EPWM1TG3. + * | | |1AH = EPWM1TG4. + * | | |1BH = EPWM1TG5. + * | | |1CH = EPWM2TG0. + * | | |1DH = EPWM2TG1. + * | | |1EH = EPWM2TG2. + * | | |1FH = EPWM2TG3. + * | | |20H = EPWM2TG4. + * | | |21H = EPWM2TG5. + * | | |other = Reserved. + * |[22] |INTPOS |Interrupt Flag Position Select + * | | |0 = Set ADIFn (EADC_STATUS2[n], n=0~3) at ADC end of conversion. + * | | |1 = Set ADIFn (EADC_STATUS2[n], n=0~3) at ADC start of conversion. + * |[23] |DBMEN |Double Buffer Mode Enable Bit + * | | |0 = Sample has one sample result register (default). + * | | |1 = Sample has two sample result registers. + * @var EADC_T::SCTL4 + * Offset: 0x90 ADC Sample Module 4 Control Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[3:0] |CHSEL |ADC Sample Module Channel Selection + * | | |00H = EADC_CH0. + * | | |01H = EADC_CH1. + * | | |02H = EADC_CH2. + * | | |03H = EADC_CH3. + * | | |04H = EADC_CH4. + * | | |05H = EADC_CH5. + * | | |06H = EADC_CH6. + * | | |07H = EADC_CH7. + * | | |08H = VBAT/4. + * |[4] |EXTREN |ADC External Trigger Rising Edge Enable Bit + * | | |0 = Rising edge Disabled when ADC selects EADC0_ST as trigger source. + * | | |1 = Rising edge Enabled when ADC selects EADC0_ST as trigger source. + * |[5] |EXTFEN |ADC External Trigger Falling Edge Enable Bit + * | | |0 = Falling edge Disabled when ADC selects EADC0_ST as trigger source. + * | | |1 = Falling edge Enabled when ADC selects EADC0_ST as trigger source. + * |[7:6] |TRGDLYDIV |ADC Sample Module Start of Conversion Trigger Delay Clock Divider Selection + * | | |Trigger delay clock frequency: + * | | |00 = ADC_CLK/1. + * | | |01 = ADC_CLK/2. + * | | |10 = ADC_CLK/4. + * | | |11 = ADC_CLK/16. + * |[15:8] |TRGDLYCNT |ADC Sample Module Start of Conversion Trigger Delay Time + * | | |Trigger delay time = TRGDLYCNT x ADC_CLK period x n (n=1,2,4,16 from TRGDLYDIV setting). + * | | |Note: If TRGDLYCNT is set to 1, trigger delay time is actually the same as TRGDLYCNT is set to 2 for hardware operation. + * |[21:16] |TRGSEL |ADC Sample Module Start of Conversion Trigger Source Selection + * | | |0H = Disable trigger. + * | | |1H = External trigger from EADC0_ST pin input. + * | | |2H = ADC ADINT0 interrupt EOC (End of conversion) pulse trigger. + * | | |3H = ADC ADINT1 interrupt EOC (End of conversion) pulse trigger. + * | | |4H = Timer0 overflow pulse trigger. + * | | |5H = Timer1 overflow pulse trigger. + * | | |6H = Timer2 overflow pulse trigger. + * | | |7H = Timer3 overflow pulse trigger. + * | | |8H = Timer4 overflow pulse trigger. + * | | |9H = Timer5 overflow pulse trigger. + * | | |AH = Timer6 overflow pulse trigger. + * | | |BH = Timer7 overflow pulse trigger. + * | | |CH = Timer8 overflow pulse trigger. + * | | |DH = Timer9 overflow pulse trigger. + * | | |EH = Timer10 overflow pulse trigger. + * | | |FH = Timer11 overflow pulse trigger. + * | | |10H = EPWM0TG0. + * | | |11H = EPWM0TG1. + * | | |12H = EPWM0TG2. + * | | |13H = EPWM0TG3. + * | | |14H = EPWM0TG4. + * | | |15H = EPWM0TG5. + * | | |16H = EPWM1TG0. + * | | |17H = EPWM1TG1. + * | | |18H = EPWM1TG2. + * | | |19H = EPWM1TG3. + * | | |1AH = EPWM1TG4. + * | | |1BH = EPWM1TG5. + * | | |1CH = EPWM2TG0. + * | | |1DH = EPWM2TG1. + * | | |1EH = EPWM2TG2. + * | | |1FH = EPWM2TG3. + * | | |20H = EPWM2TG4. + * | | |21H = EPWM2TG5. + * | | |other = Reserved. + * |[22] |INTPOS |Interrupt Flag Position Select + * | | |0 = Set ADIFn (EADC_STATUS2[n], n=0~3) at ADC end of conversion. + * | | |1 = Set ADIFn (EADC_STATUS2[n], n=0~3) at ADC start of conversion. + * @var EADC_T::SCTL5 + * Offset: 0x94 ADC Sample Module 5 Control Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[3:0] |CHSEL |ADC Sample Module Channel Selection + * | | |00H = EADC_CH0. + * | | |01H = EADC_CH1. + * | | |02H = EADC_CH2. + * | | |03H = EADC_CH3. + * | | |04H = EADC_CH4. + * | | |05H = EADC_CH5. + * | | |06H = EADC_CH6. + * | | |07H = EADC_CH7. + * | | |08H = VBAT/4. + * |[4] |EXTREN |ADC External Trigger Rising Edge Enable Bit + * | | |0 = Rising edge Disabled when ADC selects EADC0_ST as trigger source. + * | | |1 = Rising edge Enabled when ADC selects EADC0_ST as trigger source. + * |[5] |EXTFEN |ADC External Trigger Falling Edge Enable Bit + * | | |0 = Falling edge Disabled when ADC selects EADC0_ST as trigger source. + * | | |1 = Falling edge Enabled when ADC selects EADC0_ST as trigger source. + * |[7:6] |TRGDLYDIV |ADC Sample Module Start of Conversion Trigger Delay Clock Divider Selection + * | | |Trigger delay clock frequency: + * | | |00 = ADC_CLK/1. + * | | |01 = ADC_CLK/2. + * | | |10 = ADC_CLK/4. + * | | |11 = ADC_CLK/16. + * |[15:8] |TRGDLYCNT |ADC Sample Module Start of Conversion Trigger Delay Time + * | | |Trigger delay time = TRGDLYCNT x ADC_CLK period x n (n=1,2,4,16 from TRGDLYDIV setting). + * | | |Note: If TRGDLYCNT is set to 1, trigger delay time is actually the same as TRGDLYCNT is set to 2 for hardware operation. + * |[21:16] |TRGSEL |ADC Sample Module Start of Conversion Trigger Source Selection + * | | |0H = Disable trigger. + * | | |1H = External trigger from EADC0_ST pin input. + * | | |2H = ADC ADINT0 interrupt EOC (End of conversion) pulse trigger. + * | | |3H = ADC ADINT1 interrupt EOC (End of conversion) pulse trigger. + * | | |4H = Timer0 overflow pulse trigger. + * | | |5H = Timer1 overflow pulse trigger. + * | | |6H = Timer2 overflow pulse trigger. + * | | |7H = Timer3 overflow pulse trigger. + * | | |8H = Timer4 overflow pulse trigger. + * | | |9H = Timer5 overflow pulse trigger. + * | | |AH = Timer6 overflow pulse trigger. + * | | |BH = Timer7 overflow pulse trigger. + * | | |CH = Timer8 overflow pulse trigger. + * | | |DH = Timer9 overflow pulse trigger. + * | | |EH = Timer10 overflow pulse trigger. + * | | |FH = Timer11 overflow pulse trigger. + * | | |10H = EPWM0TG0. + * | | |11H = EPWM0TG1. + * | | |12H = EPWM0TG2. + * | | |13H = EPWM0TG3. + * | | |14H = EPWM0TG4. + * | | |15H = EPWM0TG5. + * | | |16H = EPWM1TG0. + * | | |17H = EPWM1TG1. + * | | |18H = EPWM1TG2. + * | | |19H = EPWM1TG3. + * | | |1AH = EPWM1TG4. + * | | |1BH = EPWM1TG5. + * | | |1CH = EPWM2TG0. + * | | |1DH = EPWM2TG1. + * | | |1EH = EPWM2TG2. + * | | |1FH = EPWM2TG3. + * | | |20H = EPWM2TG4. + * | | |21H = EPWM2TG5. + * | | |other = Reserved. + * |[22] |INTPOS |Interrupt Flag Position Select + * | | |0 = Set ADIFn (EADC_STATUS2[n], n=0~3) at ADC end of conversion. + * | | |1 = Set ADIFn (EADC_STATUS2[n], n=0~3) at ADC start of conversion. + * @var EADC_T::SCTL6 + * Offset: 0x98 ADC Sample Module 6 Control Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[3:0] |CHSEL |ADC Sample Module Channel Selection + * | | |00H = EADC_CH0. + * | | |01H = EADC_CH1. + * | | |02H = EADC_CH2. + * | | |03H = EADC_CH3. + * | | |04H = EADC_CH4. + * | | |05H = EADC_CH5. + * | | |06H = EADC_CH6. + * | | |07H = EADC_CH7. + * | | |08H = VBAT/4. + * |[4] |EXTREN |ADC External Trigger Rising Edge Enable Bit + * | | |0 = Rising edge Disabled when ADC selects EADC0_ST as trigger source. + * | | |1 = Rising edge Enabled when ADC selects EADC0_ST as trigger source. + * |[5] |EXTFEN |ADC External Trigger Falling Edge Enable Bit + * | | |0 = Falling edge Disabled when ADC selects EADC0_ST as trigger source. + * | | |1 = Falling edge Enabled when ADC selects EADC0_ST as trigger source. + * |[7:6] |TRGDLYDIV |ADC Sample Module Start of Conversion Trigger Delay Clock Divider Selection + * | | |Trigger delay clock frequency: + * | | |00 = ADC_CLK/1. + * | | |01 = ADC_CLK/2. + * | | |10 = ADC_CLK/4. + * | | |11 = ADC_CLK/16. + * |[15:8] |TRGDLYCNT |ADC Sample Module Start of Conversion Trigger Delay Time + * | | |Trigger delay time = TRGDLYCNT x ADC_CLK period x n (n=1,2,4,16 from TRGDLYDIV setting). + * | | |Note: If TRGDLYCNT is set to 1, trigger delay time is actually the same as TRGDLYCNT is set to 2 for hardware operation. + * |[21:16] |TRGSEL |ADC Sample Module Start of Conversion Trigger Source Selection + * | | |0H = Disable trigger. + * | | |1H = External trigger from EADC0_ST pin input. + * | | |2H = ADC ADINT0 interrupt EOC (End of conversion) pulse trigger. + * | | |3H = ADC ADINT1 interrupt EOC (End of conversion) pulse trigger. + * | | |4H = Timer0 overflow pulse trigger. + * | | |5H = Timer1 overflow pulse trigger. + * | | |6H = Timer2 overflow pulse trigger. + * | | |7H = Timer3 overflow pulse trigger. + * | | |8H = Timer4 overflow pulse trigger. + * | | |9H = Timer5 overflow pulse trigger. + * | | |AH = Timer6 overflow pulse trigger. + * | | |BH = Timer7 overflow pulse trigger. + * | | |CH = Timer8 overflow pulse trigger. + * | | |DH = Timer9 overflow pulse trigger. + * | | |EH = Timer10 overflow pulse trigger. + * | | |FH = Timer11 overflow pulse trigger. + * | | |10H = EPWM0TG0. + * | | |11H = EPWM0TG1. + * | | |12H = EPWM0TG2. + * | | |13H = EPWM0TG3. + * | | |14H = EPWM0TG4. + * | | |15H = EPWM0TG5. + * | | |16H = EPWM1TG0. + * | | |17H = EPWM1TG1. + * | | |18H = EPWM1TG2. + * | | |19H = EPWM1TG3. + * | | |1AH = EPWM1TG4. + * | | |1BH = EPWM1TG5. + * | | |1CH = EPWM2TG0. + * | | |1DH = EPWM2TG1. + * | | |1EH = EPWM2TG2. + * | | |1FH = EPWM2TG3. + * | | |20H = EPWM2TG4. + * | | |21H = EPWM2TG5. + * | | |other = Reserved. + * |[22] |INTPOS |Interrupt Flag Position Select + * | | |0 = Set ADIFn (EADC_STATUS2[n], n=0~3) at ADC end of conversion. + * | | |1 = Set ADIFn (EADC_STATUS2[n], n=0~3) at ADC start of conversion. + * @var EADC_T::SCTL7 + * Offset: 0x9C ADC Sample Module 7 Control Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[3:0] |CHSEL |ADC Sample Module Channel Selection + * | | |00H = EADC_CH0. + * | | |01H = EADC_CH1. + * | | |02H = EADC_CH2. + * | | |03H = EADC_CH3. + * | | |04H = EADC_CH4. + * | | |05H = EADC_CH5. + * | | |06H = EADC_CH6. + * | | |07H = EADC_CH7. + * | | |08H = VBAT/4. + * |[4] |EXTREN |ADC External Trigger Rising Edge Enable Bit + * | | |0 = Rising edge Disabled when ADC selects EADC0_ST as trigger source. + * | | |1 = Rising edge Enabled when ADC selects EADC0_ST as trigger source. + * |[5] |EXTFEN |ADC External Trigger Falling Edge Enable Bit + * | | |0 = Falling edge Disabled when ADC selects EADC0_ST as trigger source. + * | | |1 = Falling edge Enabled when ADC selects EADC0_ST as trigger source. + * |[7:6] |TRGDLYDIV |ADC Sample Module Start of Conversion Trigger Delay Clock Divider Selection + * | | |Trigger delay clock frequency: + * | | |00 = ADC_CLK/1. + * | | |01 = ADC_CLK/2. + * | | |10 = ADC_CLK/4. + * | | |11 = ADC_CLK/16. + * |[15:8] |TRGDLYCNT |ADC Sample Module Start of Conversion Trigger Delay Time + * | | |Trigger delay time = TRGDLYCNT x ADC_CLK period x n (n=1,2,4,16 from TRGDLYDIV setting). + * | | |Note: If TRGDLYCNT is set to 1, trigger delay time is actually the same as TRGDLYCNT is set to 2 for hardware operation. + * |[21:16] |TRGSEL |ADC Sample Module Start of Conversion Trigger Source Selection + * | | |0H = Disable trigger. + * | | |1H = External trigger from EADC0_ST pin input. + * | | |2H = ADC ADINT0 interrupt EOC (End of conversion) pulse trigger. + * | | |3H = ADC ADINT1 interrupt EOC (End of conversion) pulse trigger. + * | | |4H = Timer0 overflow pulse trigger. + * | | |5H = Timer1 overflow pulse trigger. + * | | |6H = Timer2 overflow pulse trigger. + * | | |7H = Timer3 overflow pulse trigger. + * | | |8H = Timer4 overflow pulse trigger. + * | | |9H = Timer5 overflow pulse trigger. + * | | |AH = Timer6 overflow pulse trigger. + * | | |BH = Timer7 overflow pulse trigger. + * | | |CH = Timer8 overflow pulse trigger. + * | | |DH = Timer9 overflow pulse trigger. + * | | |EH = Timer10 overflow pulse trigger. + * | | |FH = Timer11 overflow pulse trigger. + * | | |10H = EPWM0TG0. + * | | |11H = EPWM0TG1. + * | | |12H = EPWM0TG2. + * | | |13H = EPWM0TG3. + * | | |14H = EPWM0TG4. + * | | |15H = EPWM0TG5. + * | | |16H = EPWM1TG0. + * | | |17H = EPWM1TG1. + * | | |18H = EPWM1TG2. + * | | |19H = EPWM1TG3. + * | | |1AH = EPWM1TG4. + * | | |1BH = EPWM1TG5. + * | | |1CH = EPWM2TG0. + * | | |1DH = EPWM2TG1. + * | | |1EH = EPWM2TG2. + * | | |1FH = EPWM2TG3. + * | | |20H = EPWM2TG4. + * | | |21H = EPWM2TG5. + * | | |other = Reserved. + * |[22] |INTPOS |Interrupt Flag Position Select + * | | |0 = Set ADIFn (EADC_STATUS2[n], n=0~3) at ADC end of conversion. + * | | |1 = Set ADIFn (EADC_STATUS2[n], n=0~3) at ADC start of conversion. + * @var EADC_T::INTSRC0 + * Offset: 0xD0 ADC Interrupt 0 Source Enable Control Register. + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[0] |SPLIE0 |Sample Module 0 Interrupt Enable Bit + * | | |0 = Sample Module 0 interrupt Disabled. + * | | |1 = Sample Module 0 interrupt Enabled. + * |[1] |SPLIE1 |Sample Module 1 Interrupt Enable Bit + * | | |0 = Sample Module 1 interrupt Disabled. + * | | |1 = Sample Module 1 interrupt Enabled. + * |[2] |SPLIE2 |Sample Module 2 Interrupt Enable Bit + * | | |0 = Sample Module 2 interrupt Disabled. + * | | |1 = Sample Module 2 interrupt Enabled. + * |[3] |SPLIE3 |Sample Module 3 Interrupt Enable Bit + * | | |0 = Sample Module 3 interrupt Disabled. + * | | |1 = Sample Module 3 interrupt Enabled. + * |[4] |SPLIE4 |Sample Module 4 Interrupt Enable Bit + * | | |0 = Sample Module 4 interrupt Disabled. + * | | |1 = Sample Module 4 interrupt Enabled. + * |[5] |SPLIE5 |Sample Module 5 Interrupt Enable Bit + * | | |0 = Sample Module 5 interrupt Disabled. + * | | |1 = Sample Module 5 interrupt Enabled. + * |[6] |SPLIE6 |Sample Module 6 Interrupt Enable Bit + * | | |0 = Sample Module 6 interrupt Disabled. + * | | |1 = Sample Module 6 interrupt Enabled. + * |[7] |SPLIE7 |Sample Module 7 Interrupt Enable Bit + * | | |0 = Sample Module 7 interrupt Disabled. + * | | |1 = Sample Module 7 interrupt Enabled. + * |[8] |SPLIE8 |Sample Module 8 Interrupt Enable Bit + * | | |0 = Sample Module 8 interrupt Disabled. + * | | |1 = Sample Module 8 interrupt Enabled. + * @var EADC_T::INTSRC1 + * Offset: 0xD4 ADC Interrupt 1 Source Enable Control Register. + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[0] |SPLIE0 |Sample Module 0 Interrupt Enable Bit + * | | |0 = Sample Module 0 interrupt Disabled. + * | | |1 = Sample Module 0 interrupt Enabled. + * |[1] |SPLIE1 |Sample Module 1 Interrupt Enable Bit + * | | |0 = Sample Module 1 interrupt Disabled. + * | | |1 = Sample Module 1 interrupt Enabled. + * |[2] |SPLIE2 |Sample Module 2 Interrupt Enable Bit + * | | |0 = Sample Module 2 interrupt Disabled. + * | | |1 = Sample Module 2 interrupt Enabled. + * |[3] |SPLIE3 |Sample Module 3 Interrupt Enable Bit + * | | |0 = Sample Module 3 interrupt Disabled. + * | | |1 = Sample Module 3 interrupt Enabled. + * |[4] |SPLIE4 |Sample Module 4 Interrupt Enable Bit + * | | |0 = Sample Module 4 interrupt Disabled. + * | | |1 = Sample Module 4 interrupt Enabled. + * |[5] |SPLIE5 |Sample Module 5 Interrupt Enable Bit + * | | |0 = Sample Module 5 interrupt Disabled. + * | | |1 = Sample Module 5 interrupt Enabled. + * |[6] |SPLIE6 |Sample Module 6 Interrupt Enable Bit + * | | |0 = Sample Module 6 interrupt Disabled. + * | | |1 = Sample Module 6 interrupt Enabled. + * |[7] |SPLIE7 |Sample Module 7 Interrupt Enable Bit + * | | |0 = Sample Module 7 interrupt Disabled. + * | | |1 = Sample Module 7 interrupt Enabled. + * |[8] |SPLIE8 |Sample Module 8 Interrupt Enable Bit + * | | |0 = Sample Module 8 interrupt Disabled. + * | | |1 = Sample Module 8 interrupt Enabled. + * @var EADC_T::INTSRC2 + * Offset: 0xD8 ADC Interrupt 2 Source Enable Control Register. + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[0] |SPLIE0 |Sample Module 0 Interrupt Enable Bit + * | | |0 = Sample Module 0 interrupt Disabled. + * | | |1 = Sample Module 0 interrupt Enabled. + * |[1] |SPLIE1 |Sample Module 1 Interrupt Enable Bit + * | | |0 = Sample Module 1 interrupt Disabled. + * | | |1 = Sample Module 1 interrupt Enabled. + * |[2] |SPLIE2 |Sample Module 2 Interrupt Enable Bit + * | | |0 = Sample Module 2 interrupt Disabled. + * | | |1 = Sample Module 2 interrupt Enabled. + * |[3] |SPLIE3 |Sample Module 3 Interrupt Enable Bit + * | | |0 = Sample Module 3 interrupt Disabled. + * | | |1 = Sample Module 3 interrupt Enabled. + * |[4] |SPLIE4 |Sample Module 4 Interrupt Enable Bit + * | | |0 = Sample Module 4 interrupt Disabled. + * | | |1 = Sample Module 4 interrupt Enabled. + * |[5] |SPLIE5 |Sample Module 5 Interrupt Enable Bit + * | | |0 = Sample Module 5 interrupt Disabled. + * | | |1 = Sample Module 5 interrupt Enabled. + * |[6] |SPLIE6 |Sample Module 6 Interrupt Enable Bit + * | | |0 = Sample Module 6 interrupt Disabled. + * | | |1 = Sample Module 6 interrupt Enabled. + * |[7] |SPLIE7 |Sample Module 7 Interrupt Enable Bit + * | | |0 = Sample Module 7 interrupt Disabled. + * | | |1 = Sample Module 7 interrupt Enabled. + * |[8] |SPLIE8 |Sample Module 8 Interrupt Enable Bit + * | | |0 = Sample Module 8 interrupt Disabled. + * | | |1 = Sample Module 8 interrupt Enabled. + * @var EADC_T::INTSRC3 + * Offset: 0xDC ADC Interrupt 3 Source Enable Control Register. + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[0] |SPLIE0 |Sample Module 0 Interrupt Enable Bit + * | | |0 = Sample Module 0 interrupt Disabled. + * | | |1 = Sample Module 0 interrupt Enabled. + * |[1] |SPLIE1 |Sample Module 1 Interrupt Enable Bit + * | | |0 = Sample Module 1 interrupt Disabled. + * | | |1 = Sample Module 1 interrupt Enabled. + * |[2] |SPLIE2 |Sample Module 2 Interrupt Enable Bit + * | | |0 = Sample Module 2 interrupt Disabled. + * | | |1 = Sample Module 2 interrupt Enabled. + * |[3] |SPLIE3 |Sample Module 3 Interrupt Enable Bit + * | | |0 = Sample Module 3 interrupt Disabled. + * | | |1 = Sample Module 3 interrupt Enabled. + * |[4] |SPLIE4 |Sample Module 4 Interrupt Enable Bit + * | | |0 = Sample Module 4 interrupt Disabled. + * | | |1 = Sample Module 4 interrupt Enabled. + * |[5] |SPLIE5 |Sample Module 5 Interrupt Enable Bit + * | | |0 = Sample Module 5 interrupt Disabled. + * | | |1 = Sample Module 5 interrupt Enabled. + * |[6] |SPLIE6 |Sample Module 6 Interrupt Enable Bit + * | | |0 = Sample Module 6 interrupt Disabled. + * | | |1 = Sample Module 6 interrupt Enabled. + * |[7] |SPLIE7 |Sample Module 7 Interrupt Enable Bit + * | | |0 = Sample Module 7 interrupt Disabled. + * | | |1 = Sample Module 7 interrupt Enabled. + * |[8] |SPLIE8 |Sample Module 8 Interrupt Enable Bit + * | | |0 = Sample Module 8 interrupt Disabled. + * | | |1 = Sample Module 8 interrupt Enabled. + * @var EADC_T::CMP0 + * Offset: 0xE0 ADC Result Compare Register 0 + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[0] |ADCMPEN |ADC Result Compare Enable Bit + * | | |0 = Compare Disabled. + * | | |1 = Compare Enabled. + * | | |Set this bit to 1 to enable compare CMPDAT (EADC_CMPn[27:16], n=0~3) with specified sample module conversion result when converted data is loaded into EADC_DAT register. + * |[1] |ADCMPIE |ADC Result Compare Interrupt Enable Bit + * | | |0 = Compare function interrupt Disabled. + * | | |1 = Compare function interrupt Enabled. + * | | |If the compare function is enabled and the compare condition matches the setting of CMPCOND (EADC_CMPn[2], n=0~3) and CMPMCNT (EADC_CMPn[11:8], n=0~3), ADCMPFn (EADC_STATUS2[7:4], n=0~3) will be asserted, in the meanwhile, if ADCMPIE is set to 1, a compare interrupt request is generated. + * |[2] |CMPCOND |Compare Condition + * | | |0= Set the compare condition as that when a 12-bit ADC conversion result is less than the 12-bit CMPDAT (EADC_CMPn [27:16]), the internal match counter will increase one. + * | | |1= Set the compare condition as that when a 12-bit ADC conversion result is greater or equal to the 12-bit CMPDAT (EADC_CMPn [27:16]), the internal match counter will increase one. + * | | |Note: When the internal counter reaches the value to (CMPMCNT (EADC_CMPn[11:8], n=0~3) +1), the CMPF bit will be set. + * |[6:3] |CMPSPL |Compare Sample Module Selection + * | | |00000 = Sample Module 0 conversion result EADC_DAT0 is selected to be compared. + * | | |00001 = Sample Module 1 conversion result EADC_DAT1 is selected to be compared. + * | | |00010 = Sample Module 2 conversion result EADC_DAT2 is selected to be compared. + * | | |00011 = Sample Module 3 conversion result EADC_DAT3 is selected to be compared. + * | | |00100 = Sample Module 4 conversion result EADC_DAT4 is selected to be compared. + * | | |00101 = Sample Module 5 conversion result EADC_DAT5 is selected to be compared. + * | | |00110 = Sample Module 6 conversion result EADC_DAT6 is selected to be compared. + * | | |00111 = Sample Module 7 conversion result EADC_DAT7 is selected to be compared. + * | | |01000 = Sample Module 8 conversion result EADC_DAT8 is selected to be compared. + * |[11:8] |CMPMCNT |Compare Match Count + * | | |When the specified ADC sample module analog conversion result matches the compare condition defined by CMPCOND (EADC_CMPn[2], n=0~3), the internal match counter will increase 1 + * | | |If the compare result does not meet the compare condition, the internal compare match counter will reset to 0 + * | | |When the internal counter reaches the value to (CMPMCNT +1), the ADCMPFn (EADC_STATUS2[7:4], n=0~3) will be set. + * |[15] |CMPWEN |Compare Window Mode Enable Bit + * | | |0 = ADCMPF0 (EADC_STATUS2[4]) will be set when EADC_CMP0 compared condition matched + * | | |ADCMPF2 (EADC_STATUS2[6]) will be set when EADC_CMP2 compared condition matched + * | | |1 = ADCMPF0 (EADC_STATUS2[4]) will be set when both EADC_CMP0 and EADC_CMP1 compared condition matched + * | | |ADCMPF2 (EADC_STATUS2[6]) will be set when both EADC_CMP2 and EADC_CMP3 compared condition matched. + * | | |Note: This bit is only present in EADC_CMP0 and EADC_CMP2 register. + * |[27:16] |CMPDAT |Comparison Data + * | | |The 12 bits data is used to compare with conversion result of specified sample module + * | | |User can use it to monitor the external analog input pin voltage transition without imposing a load on software. + * @var EADC_T::CMP1 + * Offset: 0xE4 ADC Result Compare Register 1 + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[0] |ADCMPEN |ADC Result Compare Enable Bit + * | | |0 = Compare Disabled. + * | | |1 = Compare Enabled. + * | | |Set this bit to 1 to enable compare CMPDAT (EADC_CMPn[27:16], n=0~3) with specified sample module conversion result when converted data is loaded into EADC_DAT register. + * |[1] |ADCMPIE |ADC Result Compare Interrupt Enable Bit + * | | |0 = Compare function interrupt Disabled. + * | | |1 = Compare function interrupt Enabled. + * | | |If the compare function is enabled and the compare condition matches the setting of CMPCOND (EADC_CMPn[2], n=0~3) and CMPMCNT (EADC_CMPn[11:8], n=0~3), ADCMPFn (EADC_STATUS2[7:4], n=0~3) will be asserted, in the meanwhile, if ADCMPIE is set to 1, a compare interrupt request is generated. + * |[2] |CMPCOND |Compare Condition + * | | |0= Set the compare condition as that when a 12-bit ADC conversion result is less than the 12-bit CMPDAT (EADC_CMPn [27:16]), the internal match counter will increase one. + * | | |1= Set the compare condition as that when a 12-bit ADC conversion result is greater or equal to the 12-bit CMPDAT (EADC_CMPn [27:16]), the internal match counter will increase one. + * | | |Note: When the internal counter reaches the value to (CMPMCNT (EADC_CMPn[11:8], n=0~3) +1), the CMPF bit will be set. + * |[6:3] |CMPSPL |Compare Sample Module Selection + * | | |00000 = Sample Module 0 conversion result EADC_DAT0 is selected to be compared. + * | | |00001 = Sample Module 1 conversion result EADC_DAT1 is selected to be compared. + * | | |00010 = Sample Module 2 conversion result EADC_DAT2 is selected to be compared. + * | | |00011 = Sample Module 3 conversion result EADC_DAT3 is selected to be compared. + * | | |00100 = Sample Module 4 conversion result EADC_DAT4 is selected to be compared. + * | | |00101 = Sample Module 5 conversion result EADC_DAT5 is selected to be compared. + * | | |00110 = Sample Module 6 conversion result EADC_DAT6 is selected to be compared. + * | | |00111 = Sample Module 7 conversion result EADC_DAT7 is selected to be compared. + * | | |01000 = Sample Module 8 conversion result EADC_DAT8 is selected to be compared. + * |[11:8] |CMPMCNT |Compare Match Count + * | | |When the specified ADC sample module analog conversion result matches the compare condition defined by CMPCOND (EADC_CMPn[2], n=0~3), the internal match counter will increase 1 + * | | |If the compare result does not meet the compare condition, the internal compare match counter will reset to 0 + * | | |When the internal counter reaches the value to (CMPMCNT +1), the ADCMPFn (EADC_STATUS2[7:4], n=0~3) will be set. + * |[15] |CMPWEN |Compare Window Mode Enable Bit + * | | |0 = ADCMPF0 (EADC_STATUS2[4]) will be set when EADC_CMP0 compared condition matched + * | | |ADCMPF2 (EADC_STATUS2[6]) will be set when EADC_CMP2 compared condition matched + * | | |1 = ADCMPF0 (EADC_STATUS2[4]) will be set when both EADC_CMP0 and EADC_CMP1 compared condition matched + * | | |ADCMPF2 (EADC_STATUS2[6]) will be set when both EADC_CMP2 and EADC_CMP3 compared condition matched. + * | | |Note: This bit is only present in EADC_CMP0 and EADC_CMP2 register. + * |[27:16] |CMPDAT |Comparison Data + * | | |The 12 bits data is used to compare with conversion result of specified sample module + * | | |User can use it to monitor the external analog input pin voltage transition without imposing a load on software. + * @var EADC_T::CMP2 + * Offset: 0xE8 ADC Result Compare Register 2 + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[0] |ADCMPEN |ADC Result Compare Enable Bit + * | | |0 = Compare Disabled. + * | | |1 = Compare Enabled. + * | | |Set this bit to 1 to enable compare CMPDAT (EADC_CMPn[27:16], n=0~3) with specified sample module conversion result when converted data is loaded into EADC_DAT register. + * |[1] |ADCMPIE |ADC Result Compare Interrupt Enable Bit + * | | |0 = Compare function interrupt Disabled. + * | | |1 = Compare function interrupt Enabled. + * | | |If the compare function is enabled and the compare condition matches the setting of CMPCOND (EADC_CMPn[2], n=0~3) and CMPMCNT (EADC_CMPn[11:8], n=0~3), ADCMPFn (EADC_STATUS2[7:4], n=0~3) will be asserted, in the meanwhile, if ADCMPIE is set to 1, a compare interrupt request is generated. + * |[2] |CMPCOND |Compare Condition + * | | |0= Set the compare condition as that when a 12-bit ADC conversion result is less than the 12-bit CMPDAT (EADC_CMPn [27:16]), the internal match counter will increase one. + * | | |1= Set the compare condition as that when a 12-bit ADC conversion result is greater or equal to the 12-bit CMPDAT (EADC_CMPn [27:16]), the internal match counter will increase one. + * | | |Note: When the internal counter reaches the value to (CMPMCNT (EADC_CMPn[11:8], n=0~3) +1), the CMPF bit will be set. + * |[6:3] |CMPSPL |Compare Sample Module Selection + * | | |00000 = Sample Module 0 conversion result EADC_DAT0 is selected to be compared. + * | | |00001 = Sample Module 1 conversion result EADC_DAT1 is selected to be compared. + * | | |00010 = Sample Module 2 conversion result EADC_DAT2 is selected to be compared. + * | | |00011 = Sample Module 3 conversion result EADC_DAT3 is selected to be compared. + * | | |00100 = Sample Module 4 conversion result EADC_DAT4 is selected to be compared. + * | | |00101 = Sample Module 5 conversion result EADC_DAT5 is selected to be compared. + * | | |00110 = Sample Module 6 conversion result EADC_DAT6 is selected to be compared. + * | | |00111 = Sample Module 7 conversion result EADC_DAT7 is selected to be compared. + * | | |01000 = Sample Module 8 conversion result EADC_DAT8 is selected to be compared. + * |[11:8] |CMPMCNT |Compare Match Count + * | | |When the specified ADC sample module analog conversion result matches the compare condition defined by CMPCOND (EADC_CMPn[2], n=0~3), the internal match counter will increase 1 + * | | |If the compare result does not meet the compare condition, the internal compare match counter will reset to 0 + * | | |When the internal counter reaches the value to (CMPMCNT +1), the ADCMPFn (EADC_STATUS2[7:4], n=0~3) will be set. + * |[15] |CMPWEN |Compare Window Mode Enable Bit + * | | |0 = ADCMPF0 (EADC_STATUS2[4]) will be set when EADC_CMP0 compared condition matched + * | | |ADCMPF2 (EADC_STATUS2[6]) will be set when EADC_CMP2 compared condition matched + * | | |1 = ADCMPF0 (EADC_STATUS2[4]) will be set when both EADC_CMP0 and EADC_CMP1 compared condition matched + * | | |ADCMPF2 (EADC_STATUS2[6]) will be set when both EADC_CMP2 and EADC_CMP3 compared condition matched. + * | | |Note: This bit is only present in EADC_CMP0 and EADC_CMP2 register. + * |[27:16] |CMPDAT |Comparison Data + * | | |The 12 bits data is used to compare with conversion result of specified sample module + * | | |User can use it to monitor the external analog input pin voltage transition without imposing a load on software. + * @var EADC_T::CMP3 + * Offset: 0xEC ADC Result Compare Register 3 + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[0] |ADCMPEN |ADC Result Compare Enable Bit + * | | |0 = Compare Disabled. + * | | |1 = Compare Enabled. + * | | |Set this bit to 1 to enable compare CMPDAT (EADC_CMPn[27:16], n=0~3) with specified sample module conversion result when converted data is loaded into EADC_DAT register. + * |[1] |ADCMPIE |ADC Result Compare Interrupt Enable Bit + * | | |0 = Compare function interrupt Disabled. + * | | |1 = Compare function interrupt Enabled. + * | | |If the compare function is enabled and the compare condition matches the setting of CMPCOND (EADC_CMPn[2], n=0~3) and CMPMCNT (EADC_CMPn[11:8], n=0~3), ADCMPFn (EADC_STATUS2[7:4], n=0~3) will be asserted, in the meanwhile, if ADCMPIE is set to 1, a compare interrupt request is generated. + * |[2] |CMPCOND |Compare Condition + * | | |0= Set the compare condition as that when a 12-bit ADC conversion result is less than the 12-bit CMPDAT (EADC_CMPn [27:16]), the internal match counter will increase one. + * | | |1= Set the compare condition as that when a 12-bit ADC conversion result is greater or equal to the 12-bit CMPDAT (EADC_CMPn [27:16]), the internal match counter will increase one. + * | | |Note: When the internal counter reaches the value to (CMPMCNT (EADC_CMPn[11:8], n=0~3) +1), the CMPF bit will be set. + * |[6:3] |CMPSPL |Compare Sample Module Selection + * | | |00000 = Sample Module 0 conversion result EADC_DAT0 is selected to be compared. + * | | |00001 = Sample Module 1 conversion result EADC_DAT1 is selected to be compared. + * | | |00010 = Sample Module 2 conversion result EADC_DAT2 is selected to be compared. + * | | |00011 = Sample Module 3 conversion result EADC_DAT3 is selected to be compared. + * | | |00100 = Sample Module 4 conversion result EADC_DAT4 is selected to be compared. + * | | |00101 = Sample Module 5 conversion result EADC_DAT5 is selected to be compared. + * | | |00110 = Sample Module 6 conversion result EADC_DAT6 is selected to be compared. + * | | |00111 = Sample Module 7 conversion result EADC_DAT7 is selected to be compared. + * | | |01000 = Sample Module 8 conversion result EADC_DAT8 is selected to be compared. + * |[11:8] |CMPMCNT |Compare Match Count + * | | |When the specified ADC sample module analog conversion result matches the compare condition defined by CMPCOND (EADC_CMPn[2], n=0~3), the internal match counter will increase 1 + * | | |If the compare result does not meet the compare condition, the internal compare match counter will reset to 0 + * | | |When the internal counter reaches the value to (CMPMCNT +1), the ADCMPFn (EADC_STATUS2[7:4], n=0~3) will be set. + * |[15] |CMPWEN |Compare Window Mode Enable Bit + * | | |0 = ADCMPF0 (EADC_STATUS2[4]) will be set when EADC_CMP0 compared condition matched + * | | |ADCMPF2 (EADC_STATUS2[6]) will be set when EADC_CMP2 compared condition matched + * | | |1 = ADCMPF0 (EADC_STATUS2[4]) will be set when both EADC_CMP0 and EADC_CMP1 compared condition matched + * | | |ADCMPF2 (EADC_STATUS2[6]) will be set when both EADC_CMP2 and EADC_CMP3 compared condition matched. + * | | |Note: This bit is only present in EADC_CMP0 and EADC_CMP2 register. + * |[27:16] |CMPDAT |Comparison Data + * | | |The 12 bits data is used to compare with conversion result of specified sample module + * | | |User can use it to monitor the external analog input pin voltage transition without imposing a load on software. + * @var EADC_T::STATUS0 + * Offset: 0xF0 ADC Status Register 0 + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[8:0] |VALID |EADC_DAT0~8 Data Valid Flag + * | | |It is a mirror of VALID bit in sample module ADC result data register EADC_DATn. (n=0~8). + * |[24:16] |OV |EADC_DAT0~8 Overrun Flag + * | | |It is a mirror to OV bit in sample module ADC result data register EADC_DATn. (n=0~8). + * @var EADC_T::STATUS2 + * Offset: 0xF8 ADC Status Register 2 + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[0] |ADIF0 |ADC ADINT0 Interrupt Flag + * | | |0 = No ADINT0 interrupt pulse received. + * | | |1 = ADINT0 interrupt pulse has been received. + * | | |Note 1: This bit is cleared by writing 1 to it. + * | | |Note 2:This bit indicates whether an ADC conversion of specific sample module has been completed + * |[1] |ADIF1 |ADC ADINT1 Interrupt Flag + * | | |0 = No ADINT1 interrupt pulse received. + * | | |1 = ADINT1 interrupt pulse has been received. + * | | |Note 1: This bit is cleared by writing 1 to it. + * | | |Note 2:This bit indicates whether an ADC conversion of specific sample module has been completed + * |[2] |ADIF2 |ADC ADINT2 Interrupt Flag + * | | |0 = No ADINT2 interrupt pulse received. + * | | |1 = ADINT2 interrupt pulse has been received. + * | | |Note 1: This bit is cleared by writing 1 to it. + * | | |Note 2:This bit indicates whether an ADC conversion of specific sample module has been completed + * |[3] |ADIF3 |ADC ADINT3 Interrupt Flag + * | | |0 = No ADINT3 interrupt pulse received. + * | | |1 = ADINT3 interrupt pulse has been received. + * | | |Note 1: This bit is cleared by writing 1 to it. + * | | |Note 2:This bit indicates whether an ADC conversion of specific sample module has been completed + * |[4] |ADCMPF0 |ADC Compare 0 Flag + * | | |When the specific sample module ADC conversion result meets setting condition in EADC_CMP0 then this bit is set to 1. + * | | |0 = Conversion result in EADC_DAT does not meet EADC_CMP0 register setting. + * | | |1 = Conversion result in EADC_DAT meets EADC_CMP0 register setting. + * | | |Note: This bit is cleared by writing 1 to it. + * |[5] |ADCMPF1 |ADC Compare 1 Flag + * | | |When the specific sample module ADC conversion result meets setting condition in EADC_CMP1 then this bit is set to 1. + * | | |0 = Conversion result in EADC_DAT does not meet EADC_CMP1 register setting. + * | | |1 = Conversion result in EADC_DAT meets EADC_CMP1 register setting. + * | | |Note: This bit is cleared by writing 1 to it. + * |[6] |ADCMPF2 |ADC Compare 2 Flag + * | | |When the specific sample module ADC conversion result meets setting condition in EADC_CMP2 then this bit is set to 1. + * | | |0 = Conversion result in EADC_DAT does not meet EADC_CMP2 register setting. + * | | |1 = Conversion result in EADC_DAT meets EADC_CMP2 register setting. + * | | |Note: This bit is cleared by writing 1 to it. + * |[7] |ADCMPF3 |ADC Compare 3 Flag + * | | |When the specific sample module ADC conversion result meets setting condition in EADC_CMP3 then this bit is set to 1. + * | | |0 = Conversion result in EADC_DAT does not meet EADC_CMP3 register setting. + * | | |1 = Conversion result in EADC_DAT meets EADC_CMP3 register setting. + * | | |Note: This bit is cleared by writing 1 to it. + * |[8] |ADOVIF0 |ADC ADINT0 Interrupt Flag Overrun + * | | |0 = ADINT0 interrupt flag is not overwritten to 1. + * | | |1 = ADINT0 interrupt flag is overwritten to 1. + * | | |Note: This bit is cleared by writing 1 to it. + * |[9] |ADOVIF1 |ADC ADINT1 Interrupt Flag Overrun + * | | |0 = ADINT1 interrupt flag is not overwritten to 1. + * | | |1 = ADINT1 interrupt flag is overwritten to 1. + * | | |Note: This bit is cleared by writing 1 to it. + * |[10] |ADOVIF2 |ADC ADINT2 Interrupt Flag Overrun + * | | |0 = ADINT2 interrupt flag is not overwritten to 1. + * | | |1 = ADINT2 interrupt flag is overwritten to 1. + * | | |Note: This bit is cleared by writing 1 to it. + * |[11] |ADOVIF3 |ADC ADINT3 Interrupt Flag Overrun + * | | |0 = ADINT3 interrupt flag is not overwritten to 1. + * | | |1 = ADINT3 interrupt flag is overwritten to 1. + * | | |Note: This bit is cleared by writing 1 to it. + * |[12] |ADCMPO0 |ADC Compare 0 Output Status (Read Only) + * | | |The 12 bits compare0 data CMPDAT0 (EADC_CMP0[27:16]) is used to compare with conversion result of specified sample module + * | | |User can use it to monitor the external analog input pin voltage status. + * | | |0 = Conversion result in EADC_DAT is less than CMPDAT0 setting. + * | | |1 = Conversion result in EADC_DAT is greater than or equal to CMPDAT0 setting. + * |[13] |ADCMPO1 |ADC Compare 1 Output Status (Read Only) + * | | |The 12 bits compare1 data CMPDAT1 (EADC_CMP1[27:16]) is used to compare with conversion result of specified sample module + * | | |User can use it to monitor the external analog input pin voltage status. + * | | |0 = Conversion result in EADC_DAT is less than CMPDAT1 setting. + * | | |1 = Conversion result in EADC_DAT is greater than or equal to CMPDAT1 setting. + * |[14] |ADCMPO2 |ADC Compare 2 Output Status (Read Only) + * | | |The 12 bits compare2 data CMPDAT2 (EADC_CMP2[27:16]) is used to compare with conversion result of specified sample module + * | | |User can use it to monitor the external analog input pin voltage status. + * | | |0 = Conversion result in EADC_DAT is less than CMPDAT2 setting. + * | | |1 = Conversion result in EADC_DAT is greater than or equal to CMPDAT2 setting. + * |[15] |ADCMPO3 |ADC Compare 3 Output Status (Read Only) + * | | |The 12 bits compare3 data CMPDAT3 (EADC_CMP3[27:16]) is used to compare with conversion result of specified sample module + * | | |User can use it to monitor the external analog input pin voltage status. + * | | |0 = Conversion result in EADC_DAT is less than CMPDAT3 setting. + * | | |1 = Conversion result in EADC_DAT is greater than or equal to CMPDAT3 setting. + * |[20:16] |CHANNEL |Current Conversion Channel (Read Only) + * | | |This filed reflects ADC current conversion channel when BUSY=1. + * | | |00H = EADC_CH0. + * | | |01H = EADC_CH1. + * | | |02H = EADC_CH2. + * | | |03H = EADC_CH3. + * | | |04H = EADC_CH4. + * | | |05H = EADC_CH5. + * | | |06H = EADC_CH6. + * | | |07H = EADC_CH7. + * | | |08H = VBAT/4. + * |[23] |BUSY |Busy/Idle (Read Only) + * | | |0 = EADC is in idle state. + * | | |1 = EADC is busy at conversion. + * |[24] |ADOVIF |All ADC Interrupt Flag Overrun Bits Check (Read Only) + * | | |n=0~3. + * | | |0 = None of ADINT interrupt flag ADOVIFn (EADC_STATUS2[11:8]) is overwritten to 1. + * | | |1 = Any one of ADINT interrupt flag ADOVIFn (EADC_STATUS2[11:8]) is overwritten to 1. + * | | |Note: This bit will keep 1 when any ADOVIFn Flag is equal to 1. + * |[25] |STOVF |All ADC Sample Module Start of Conversion Overrun Flags Check (Read Only) + * | | |n=0~8. + * | | |0 = None of sample module event overrun flag SPOVF (EADC_OVSTS[n]) is set to 1. + * | | |1 = Any one of sample module event overrun flag SPOVF (EADC_OVSTS[n]) is set to 1. + * | | |Note: This bit will keep 1 when any SPOVF Flag is equal to 1. + * |[26] |AVALID |All Sample Module ADC Result Data Register EADC_DAT Data Valid Flag Check (Read Only) + * | | |n=0~8. + * | | |0 = None of sample module data register valid flag VALID (EADC_DATn[17]) is set to 1. + * | | |1 = Any one of sample module data register valid flag VALID (EADC_DATn[17]) is set to 1. + * | | |Note: This bit will keep 1 when any VALID Flag is equal to 1. + * |[27] |AOV |All Sample Module ADC Result Data Register Overrun Flags Check (Read Only) + * | | |n=0~8. + * | | |0 = None of sample module data register overrun flag OV (EADC_DATn[16]) is set to 1. + * | | |1 = Any one of sample module data register overrun flag OV (EADC_DATn[16]) is set to 1. + * | | |Note: This bit will keep 1 when any OV Flag is equal to 1. + * @var EADC_T::STATUS3 + * Offset: 0xFC ADC Status Register 3 + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[4:0] |CURSPL |ADC Current Sample Module (Read Only) + * | | |This register shows the current ADC is controlled by which sample module control logic modules. + * | | |If the ADC is Idle, the bit filed will be set to 0x1F. + * @var EADC_T::DDAT0 + * Offset: 0x100 ADC Double Data Register 0 for Sample Module 0 + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[15:0] |RESULT |ADC Conversion Results + * | | |This field contains 12 bits conversion results. + * | | |When the DMOF (EADC_CTL[9]) is set to 0, 12-bit ADC conversion result with unsigned format will be filled in RESULT [11:0] and zero will be filled in RESULT [15:12]. + * | | |When DMOF (EADC_CTL[9]) is set to 1, 12-bit ADC conversion result with 2's complement format will be filled in RESULT [11:0] and signed bits to will be filled in RESULT [15:12]. + * |[16] |OV |Overrun Flag + * | | |0 = Data in RESULT (EADC_DATn[15:0], n=0~3) is recent conversion result. + * | | |1 = Data in RESULT (EADC_DATn[15:0], n=0~3) is overwrite. + * | | |Note: If converted data in RESULT[15:0] has not been read before new conversion result is loaded to this register, OV is set to 1 + * | | |It is cleared by hardware after EADC_DDAT register is read. + * |[17] |VALID |Valid Flag + * | | |0 = Double data in RESULT (EADC_DDATn[15:0]) is not valid. + * | | |1 = Double data in RESULT (EADC_DDATn[15:0]) is valid. + * | | |Note: This bit is set to 1 when corresponding sample module channel analog input conversion is completed and cleared by hardware after EADC_DDATn register is read (n=0~3). + * @var EADC_T::DDAT1 + * Offset: 0x104 ADC Double Data Register 1 for Sample Module 1 + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[15:0] |RESULT |ADC Conversion Results + * | | |This field contains 12 bits conversion results. + * | | |When the DMOF (EADC_CTL[9]) is set to 0, 12-bit ADC conversion result with unsigned format will be filled in RESULT [11:0] and zero will be filled in RESULT [15:12]. + * | | |When DMOF (EADC_CTL[9]) is set to 1, 12-bit ADC conversion result with 2's complement format will be filled in RESULT [11:0] and signed bits to will be filled in RESULT [15:12]. + * |[16] |OV |Overrun Flag + * | | |0 = Data in RESULT (EADC_DATn[15:0], n=0~3) is recent conversion result. + * | | |1 = Data in RESULT (EADC_DATn[15:0], n=0~3) is overwrite. + * | | |Note: If converted data in RESULT[15:0] has not been read before new conversion result is loaded to this register, OV is set to 1 + * | | |It is cleared by hardware after EADC_DDAT register is read. + * |[17] |VALID |Valid Flag + * | | |0 = Double data in RESULT (EADC_DDATn[15:0]) is not valid. + * | | |1 = Double data in RESULT (EADC_DDATn[15:0]) is valid. + * | | |Note: This bit is set to 1 when corresponding sample module channel analog input conversion is completed and cleared by hardware after EADC_DDATn register is read (n=0~3). + * @var EADC_T::DDAT2 + * Offset: 0x108 ADC Double Data Register 2 for Sample Module 2 + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[15:0] |RESULT |ADC Conversion Results + * | | |This field contains 12 bits conversion results. + * | | |When the DMOF (EADC_CTL[9]) is set to 0, 12-bit ADC conversion result with unsigned format will be filled in RESULT [11:0] and zero will be filled in RESULT [15:12]. + * | | |When DMOF (EADC_CTL[9]) is set to 1, 12-bit ADC conversion result with 2's complement format will be filled in RESULT [11:0] and signed bits to will be filled in RESULT [15:12]. + * |[16] |OV |Overrun Flag + * | | |0 = Data in RESULT (EADC_DATn[15:0], n=0~3) is recent conversion result. + * | | |1 = Data in RESULT (EADC_DATn[15:0], n=0~3) is overwrite. + * | | |Note: If converted data in RESULT[15:0] has not been read before new conversion result is loaded to this register, OV is set to 1 + * | | |It is cleared by hardware after EADC_DDAT register is read. + * |[17] |VALID |Valid Flag + * | | |0 = Double data in RESULT (EADC_DDATn[15:0]) is not valid. + * | | |1 = Double data in RESULT (EADC_DDATn[15:0]) is valid. + * | | |Note: This bit is set to 1 when corresponding sample module channel analog input conversion is completed and cleared by hardware after EADC_DDATn register is read (n=0~3). + * @var EADC_T::DDAT3 + * Offset: 0x10C ADC Double Data Register 3 for Sample Module 3 + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[15:0] |RESULT |ADC Conversion Results + * | | |This field contains 12 bits conversion results. + * | | |When the DMOF (EADC_CTL[9]) is set to 0, 12-bit ADC conversion result with unsigned format will be filled in RESULT [11:0] and zero will be filled in RESULT [15:12]. + * | | |When DMOF (EADC_CTL[9]) is set to 1, 12-bit ADC conversion result with 2's complement format will be filled in RESULT [11:0] and signed bits to will be filled in RESULT [15:12]. + * |[16] |OV |Overrun Flag + * | | |0 = Data in RESULT (EADC_DATn[15:0], n=0~3) is recent conversion result. + * | | |1 = Data in RESULT (EADC_DATn[15:0], n=0~3) is overwrite. + * | | |Note: If converted data in RESULT[15:0] has not been read before new conversion result is loaded to this register, OV is set to 1 + * | | |It is cleared by hardware after EADC_DDAT register is read. + * |[17] |VALID |Valid Flag + * | | |0 = Double data in RESULT (EADC_DDATn[15:0]) is not valid. + * | | |1 = Double data in RESULT (EADC_DDATn[15:0]) is valid. + * | | |Note: This bit is set to 1 when corresponding sample module channel analog input conversion is completed and cleared by hardware after EADC_DDATn register is read (n=0~3). + * @var EADC_T::PWRM + * Offset: 0x110 ADC Power Management Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[0] |PWUPRDY |ADC Power-up Sequence Completed and Ready for Conversion (Read Only) + * | | |0 = ADC is not ready for conversion may be in power down state or in the progress of start-up. + * | | |1 = ADC is ready for conversion. + * |[1] |PWUCALEN |Power Up Calibration Function Enable Bit + * | | |0 = Calibration function Disabled at power up. + * | | |1 = Calibration function Enabled at power up. + * | | |Note: This bit works together with CALSEL (EADC_CALCTL [3]), see the following + * | | |{PWUCALEN, CALSEL } Description: + * | | |PWUCALEN is 0 and CALSEL is 0: No need to calibrate. + * | | |PWUCALEN is 0 and CALSEL is 1: No need to calibrate. + * | | |PWUCALEN is 1 and CALSEL is 1: Calibrate when power up. + * |[3:2] |PWDMOD |ADC Power-down Mode + * | | |Set this bit field to select ADC Power-down mode when system power-down. + * | | |00 = ADC Deep Power-down mode. + * | | |01 = ADC Power down. + * | | |10 = ADC Standby mode. + * | | |11 = ADC Deep Power-down mode. + * | | |Note: Different PWDMOD has different power down/up sequence; in order to avoid ADC powering up with wrong sequence, user must keep PWMOD consistent each time in power down and start-up + * |[27:8] |IREFSUT |ADC Internal REF Start-up Time + * | | |Set this bit field to control internal reference start-up time + * | | |The typical required internal reference start-up time is 1ms when ADC fully power down + * | | |Internal reference start-up time = (1/ADC_CLK) x IREFSUT. + * | | |Note 1: ADC fully Power-down mode means both ADC macro and internal reference enter Power-down mode. + * | | |Note 2: ADC macro enters Power-down mode when ADCEN(EADC_CTL[0] = 0. + * | | |Note 3: ADC internal reference enters Power-down mode when PDREF(EADC_REFADJCT[0] = 1. + * @var EADC_T::CALCTL + * Offset: 0x114 ADC Calibration Control Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[1] |CALSTART |Calibration Functional Block Start + * | | |0 = Stop calibration functional block. + * | | |1 = Start calibration functional block. + * | | |Note: This bit is set by software and cleared by hardware after re-calibration is finished. + * |[2] |CALDONE |Calibration Functional Block Complete (Read Only) + * | | |0 = During a calibration. + * | | |1 = Calibration is completed. + * |[3] |CALSEL |Select Calibration Functional Block Enable Bit + * | | |0 = Calibration functional block Disabled. + * | | |1 = Calibration functional block Enabled. + * @var EADC_T::PDMACTL + * Offset: 0x130 ADC PDMA Control Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[8:0] |PDMATEN |PDMA Transfer Enable Bit + * | | |When EADC conversion is completed, the converted data is loaded into EADC_DATn (n: 0 ~ 8) register, user can enable this bit to generate a PDMA data transfer request. + * | | |0 = PDMA data transfer Disabled. + * | | |1 = PDMA data transfer Enabled. + * | | |Note:When this bit field is set to 1, user must set EADCIENn (EADC_CTL[5:2], n=0~3) = 0 to disable interrupt. + * |[31] |PDMABUSY |PDMA Busy Bit + * | | |When EADC conversion is completed, the converted data is loaded into EADC_DATn (n: 0 ~ 8) register + * | | |User can trigger PDMA to read converted data + * | | |When PDMA is too busy to read converted data, this bit field to 1. + * | | |Note: This bit is cleared by writing 1 to it. + * @var EADC_T::SELSMP0 + * Offset: 0x140 ADC Select Sampling Time Register 0 + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[1:0] |SELSMP0 |Channel n Select Sampling Time Option + * | | |ADC sampling time selection bit, in case more sampling time is needed when the input signal resistance is higher. + * | | |00 = 3+0 ADC_CLK. + * | | |01 = 3+2 ADC_CLK. + * | | |10 = 3+4 ADC_CLK. + * | | |11 = 3+6 ADC_CLK. + * | | |Note: Please set the same value in all of SELSMPn (n = 0,1..8). + * |[5:4] |SELSMP1 |Channel n Select Sampling Time Option + * | | |ADC sampling time selection bit, in case more sampling time is needed when the input signal resistance is higher. + * | | |00 = 3+0 ADC_CLK. + * | | |01 = 3+2 ADC_CLK. + * | | |10 = 3+4 ADC_CLK. + * | | |11 = 3+6 ADC_CLK. + * | | |Note: Please set the same value in all of SELSMPn (n = 0,1..8). + * |[9:8] |SELSMP2 |Channel n Select Sampling Time Option + * | | |ADC sampling time selection bit, in case more sampling time is needed when the input signal resistance is higher. + * | | |00 = 3+0 ADC_CLK. + * | | |01 = 3+2 ADC_CLK. + * | | |10 = 3+4 ADC_CLK. + * | | |11 = 3+6 ADC_CLK. + * | | |Note: Please set the same value in all of SELSMPn (n = 0,1..8). + * |[13:12] |SELSMP3 |Channel n Select Sampling Time Option + * | | |ADC sampling time selection bit, in case more sampling time is needed when the input signal resistance is higher. + * | | |00 = 3+0 ADC_CLK. + * | | |01 = 3+2 ADC_CLK. + * | | |10 = 3+4 ADC_CLK. + * | | |11 = 3+6 ADC_CLK. + * | | |Note: Please set the same value in all of SELSMPn (n = 0,1..8). + * |[17:16] |SELSMP4 |Channel n Select Sampling Time Option + * | | |ADC sampling time selection bit, in case more sampling time is needed when the input signal resistance is higher. + * | | |00 = 3+0 ADC_CLK. + * | | |01 = 3+2 ADC_CLK. + * | | |10 = 3+4 ADC_CLK. + * | | |11 = 3+6 ADC_CLK. + * | | |Note: Please set the same value in all of SELSMPn (n = 0,1..8). + * |[21:20] |SELSMP5 |Channel n Select Sampling Time Option + * | | |ADC sampling time selection bit, in case more sampling time is needed when the input signal resistance is higher. + * | | |00 = 3+0 ADC_CLK. + * | | |01 = 3+2 ADC_CLK. + * | | |10 = 3+4 ADC_CLK. + * | | |11 = 3+6 ADC_CLK. + * | | |Note: Please set the same value in all of SELSMPn (n = 0,1..8). + * |[25:24] |SELSMP6 |Channel n Select Sampling Time Option + * | | |ADC sampling time selection bit, in case more sampling time is needed when the input signal resistance is higher. + * | | |00 = 3+0 ADC_CLK. + * | | |01 = 3+2 ADC_CLK. + * | | |10 = 3+4 ADC_CLK. + * | | |11 = 3+6 ADC_CLK. + * | | |Note: Please set the same value in all of SELSMPn (n = 0,1..8). + * |[29:28] |SELSMP7 |Channel n Select Sampling Time Option + * | | |ADC sampling time selection bit, in case more sampling time is needed when the input signal resistance is higher. + * | | |00 = 3+0 ADC_CLK. + * | | |01 = 3+2 ADC_CLK. + * | | |10 = 3+4 ADC_CLK. + * | | |11 = 3+6 ADC_CLK. + * | | |Note: Please set the same value in all of SELSMPn (n = 0,1..8). + * @var EADC_T::SELSMP1 + * Offset: 0x144 ADC Select Sampling Time Register 1 + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[1:0] |SELSMP8 |Channel 8 Select Sampling Time Option + * | | |ADC sampling time selection bit, in case more sampling time is needed when the input signal resistance is higher. + * | | |00 = 3+0 ADC_CLK. + * | | |01 = 3+2 ADC_CLK. + * | | |10 = 3+4 ADC_CLK. + * | | |11 = 3+6 ADC_CLK. + * | | |Note: Please set the same value in all of SELSMPn (n = 0,1..8). + * @var EADC_T::REFADJCTL + * Offset: 0x150 ADC Reference Voltage Adjust Control Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[0] |PDREF |ADC Power Down Internal Reference Control Bit + * | | |0 = Normal operating mode. + * | | |1 = Power-down mode. + * | | |Note: If power down internal reference, ADC's reference voltage must come from external VREF. + * |[4:1] |REFADJ |ADC Internal Band-gap Voltage Option + * | | |By setting REFADJ according to the following formula and configuration table, one can adjust reference voltage VREF in a small range: + * | | |VREF = GAIN x VBG. + * | | |GAIN = 1.6, 2.0, 2.5, 3.0(by setting VREFSEL(EADC_CTL[11:10]) = 00, 01, 10, 11 respectively). + * | | |VBG is internal band-gap voltage, typical 1.0V, VBG can be configured by the following: + * | | |0000 = VBG_type. + * | | |0001 = VBG_type + 20 mV. + * | | |0010 = VBG_type + 40 mV. + * | | |0011 = VBG_type + 60 mV. + * | | |0100 = VBG_type + 80 mV. + * | | |0101 = VBG_type + 100 mV. + * | | |0110 = VBG_type + 120 mV. + * | | |0111 = VBG_type + 160 mV. + * | | |1000 = VBG_type - 20 mV. + * | | |1001 = VBG_type - 40 mV. + * | | |1010 = VBG_type - 60 mV. + * | | |1011 = VBG_type - 80 mV. + * | | |1100 = VBG_type - 100 mV. + * | | |1101 = VBG_type - 120 mV. + * | | |1110 = VBG_type - 140 mV. + * | | |1111 = VBG_type - 160 mV. + * | | |Note: VBG_type = 1.0 V. + */ + __I uint32_t DAT[19]; /*!< [0x0000] ADC Data Register 0~18 for Sample Module 0~18 */ + __I uint32_t CURDAT; /*!< [0x004c] ADC PDMA Current Transfer Data Register */ + __IO uint32_t CTL; /*!< [0x0050] ADC Control Register */ + __O uint32_t SWTRG; /*!< [0x0054] ADC Sample Module Software Start Register */ + __IO uint32_t PENDSTS; /*!< [0x0058] ADC Start of Conversion Pending Flag Register */ + __IO uint32_t OVSTS; /*!< [0x005c] ADC Sample Module Start of Conversion Overrun Flag Register */ + /// @cond HIDDEN_SYMBOLS + __I uint32_t RESERVE0[8]; + /// @endcond //HIDDEN_SYMBOLS + __IO uint32_t SCTL[19]; /*!< [0x0080] ADC Sample Module 0~18 Control Register */ + /// @cond HIDDEN_SYMBOLS + __I uint32_t RESERVE1[1]; + /// @endcond //HIDDEN_SYMBOLS + __IO uint32_t INTSRC[4]; /*!< [0x00d0] ADC interrupt 0~3 Source Enable Control Register. */ + __IO uint32_t CMP[4]; /*!< [0x00e0] ADC Result Compare Register 0~3 */ + __I uint32_t STATUS0; /*!< [0x00f0] ADC Status Register 0 */ + __I uint32_t STATUS1; /*!< [0x00f4] ADC Status Register 1 */ + __IO uint32_t STATUS2; /*!< [0x00f8] ADC Status Register 2 */ + __I uint32_t STATUS3; /*!< [0x00fc] ADC Status Register 3 */ + __I uint32_t DDAT[4]; /*!< [0x0100] ADC Double Data Register 0~3 for Sample Module 0~3 */ + __IO uint32_t PWRM; /*!< [0x0110] ADC Power Management Register */ + __IO uint32_t CALCTL; /*!< [0x0114] ADC Calibration Control Register */ + __IO uint32_t CALDWRD; /*!< [0x0118] ADC Calibration Load Word Register */ + /// @cond HIDDEN_SYMBOLS + __I uint32_t RESERVE2[5]; + /// @endcond //HIDDEN_SYMBOLS + __IO uint32_t PDMACTL; /*!< [0x0130] ADC PDMA Control Register */ + __I uint32_t RESERVE5[3]; + __IO uint32_t SELSMP0; /*!< [0x0140] ADC Select Sampling Time Register 0 */ + __IO uint32_t SELSMP1; /*!< [0x0144] ADC Select Sampling Time Register 1 */ + __I uint32_t RESERVE6[2]; + __IO uint32_t REFADJCTL; /*!< [0x0150] ADC Reference Voltage Adjust Control Register */ + +} EADC_T; + +/** + @addtogroup EADC_CONST EADC Bit Field Definition + Constant Definitions for EADC Controller +@{ */ + +#define EADC_DAT_RESULT_Pos (0) /*!< EADC_T::DAT: RESULT Position */ +#define EADC_DAT_RESULT_Msk (0xfffful << EADC_DAT_RESULT_Pos) /*!< EADC_T::DAT: RESULT Mask */ + +#define EADC_DAT_OV_Pos (16) /*!< EADC_T::DAT: OV Position */ +#define EADC_DAT_OV_Msk (0x1ul << EADC_DAT_OV_Pos) /*!< EADC_T::DAT: OV Mask */ + +#define EADC_DAT_VALID_Pos (17) /*!< EADC_T::DAT: VALID Position */ +#define EADC_DAT_VALID_Msk (0x1ul << EADC_DAT_VALID_Pos) /*!< EADC_T::DAT: VALID Mask */ + +#define EADC_DAT0_RESULT_Pos (0) /*!< EADC_T::DAT0: RESULT Position */ +#define EADC_DAT0_RESULT_Msk (0xfffful << EADC_DAT0_RESULT_Pos) /*!< EADC_T::DAT0: RESULT Mask */ + +#define EADC_DAT0_OV_Pos (16) /*!< EADC_T::DAT0: OV Position */ +#define EADC_DAT0_OV_Msk (0x1ul << EADC_DAT0_OV_Pos) /*!< EADC_T::DAT0: OV Mask */ + +#define EADC_DAT0_VALID_Pos (17) /*!< EADC_T::DAT0: VALID Position */ +#define EADC_DAT0_VALID_Msk (0x1ul << EADC_DAT0_VALID_Pos) /*!< EADC_T::DAT0: VALID Mask */ + +#define EADC_DAT1_RESULT_Pos (0) /*!< EADC_T::DAT1: RESULT Position */ +#define EADC_DAT1_RESULT_Msk (0xfffful << EADC_DAT1_RESULT_Pos) /*!< EADC_T::DAT1: RESULT Mask */ + +#define EADC_DAT1_OV_Pos (16) /*!< EADC_T::DAT1: OV Position */ +#define EADC_DAT1_OV_Msk (0x1ul << EADC_DAT1_OV_Pos) /*!< EADC_T::DAT1: OV Mask */ + +#define EADC_DAT1_VALID_Pos (17) /*!< EADC_T::DAT1: VALID Position */ +#define EADC_DAT1_VALID_Msk (0x1ul << EADC_DAT1_VALID_Pos) /*!< EADC_T::DAT1: VALID Mask */ + +#define EADC_DAT2_RESULT_Pos (0) /*!< EADC_T::DAT2: RESULT Position */ +#define EADC_DAT2_RESULT_Msk (0xfffful << EADC_DAT2_RESULT_Pos) /*!< EADC_T::DAT2: RESULT Mask */ + +#define EADC_DAT2_OV_Pos (16) /*!< EADC_T::DAT2: OV Position */ +#define EADC_DAT2_OV_Msk (0x1ul << EADC_DAT2_OV_Pos) /*!< EADC_T::DAT2: OV Mask */ + +#define EADC_DAT2_VALID_Pos (17) /*!< EADC_T::DAT2: VALID Position */ +#define EADC_DAT2_VALID_Msk (0x1ul << EADC_DAT2_VALID_Pos) /*!< EADC_T::DAT2: VALID Mask */ + +#define EADC_DAT3_RESULT_Pos (0) /*!< EADC_T::DAT3: RESULT Position */ +#define EADC_DAT3_RESULT_Msk (0xfffful << EADC_DAT3_RESULT_Pos) /*!< EADC_T::DAT3: RESULT Mask */ + +#define EADC_DAT3_OV_Pos (16) /*!< EADC_T::DAT3: OV Position */ +#define EADC_DAT3_OV_Msk (0x1ul << EADC_DAT3_OV_Pos) /*!< EADC_T::DAT3: OV Mask */ + +#define EADC_DAT3_VALID_Pos (17) /*!< EADC_T::DAT3: VALID Position */ +#define EADC_DAT3_VALID_Msk (0x1ul << EADC_DAT3_VALID_Pos) /*!< EADC_T::DAT3: VALID Mask */ + +#define EADC_DAT4_RESULT_Pos (0) /*!< EADC_T::DAT4: RESULT Position */ +#define EADC_DAT4_RESULT_Msk (0xfffful << EADC_DAT4_RESULT_Pos) /*!< EADC_T::DAT4: RESULT Mask */ + +#define EADC_DAT4_OV_Pos (16) /*!< EADC_T::DAT4: OV Position */ +#define EADC_DAT4_OV_Msk (0x1ul << EADC_DAT4_OV_Pos) /*!< EADC_T::DAT4: OV Mask */ + +#define EADC_DAT4_VALID_Pos (17) /*!< EADC_T::DAT4: VALID Position */ +#define EADC_DAT4_VALID_Msk (0x1ul << EADC_DAT4_VALID_Pos) /*!< EADC_T::DAT4: VALID Mask */ + +#define EADC_DAT5_RESULT_Pos (0) /*!< EADC_T::DAT5: RESULT Position */ +#define EADC_DAT5_RESULT_Msk (0xfffful << EADC_DAT5_RESULT_Pos) /*!< EADC_T::DAT5: RESULT Mask */ + +#define EADC_DAT5_OV_Pos (16) /*!< EADC_T::DAT5: OV Position */ +#define EADC_DAT5_OV_Msk (0x1ul << EADC_DAT5_OV_Pos) /*!< EADC_T::DAT5: OV Mask */ + +#define EADC_DAT5_VALID_Pos (17) /*!< EADC_T::DAT5: VALID Position */ +#define EADC_DAT5_VALID_Msk (0x1ul << EADC_DAT5_VALID_Pos) /*!< EADC_T::DAT5: VALID Mask */ + +#define EADC_DAT6_RESULT_Pos (0) /*!< EADC_T::DAT6: RESULT Position */ +#define EADC_DAT6_RESULT_Msk (0xfffful << EADC_DAT6_RESULT_Pos) /*!< EADC_T::DAT6: RESULT Mask */ + +#define EADC_DAT6_OV_Pos (16) /*!< EADC_T::DAT6: OV Position */ +#define EADC_DAT6_OV_Msk (0x1ul << EADC_DAT6_OV_Pos) /*!< EADC_T::DAT6: OV Mask */ + +#define EADC_DAT6_VALID_Pos (17) /*!< EADC_T::DAT6: VALID Position */ +#define EADC_DAT6_VALID_Msk (0x1ul << EADC_DAT6_VALID_Pos) /*!< EADC_T::DAT6: VALID Mask */ + +#define EADC_DAT7_RESULT_Pos (0) /*!< EADC_T::DAT7: RESULT Position */ +#define EADC_DAT7_RESULT_Msk (0xfffful << EADC_DAT7_RESULT_Pos) /*!< EADC_T::DAT7: RESULT Mask */ + +#define EADC_DAT7_OV_Pos (16) /*!< EADC_T::DAT7: OV Position */ +#define EADC_DAT7_OV_Msk (0x1ul << EADC_DAT7_OV_Pos) /*!< EADC_T::DAT7: OV Mask */ + +#define EADC_DAT7_VALID_Pos (17) /*!< EADC_T::DAT7: VALID Position */ +#define EADC_DAT7_VALID_Msk (0x1ul << EADC_DAT7_VALID_Pos) /*!< EADC_T::DAT7: VALID Mask */ + +#define EADC_DAT8_RESULT_Pos (0) /*!< EADC_T::DAT8: RESULT Position */ +#define EADC_DAT8_RESULT_Msk (0xfffful << EADC_DAT8_RESULT_Pos) /*!< EADC_T::DAT8: RESULT Mask */ + +#define EADC_DAT8_OV_Pos (16) /*!< EADC_T::DAT8: OV Position */ +#define EADC_DAT8_OV_Msk (0x1ul << EADC_DAT8_OV_Pos) /*!< EADC_T::DAT8: OV Mask */ + +#define EADC_DAT8_VALID_Pos (17) /*!< EADC_T::DAT8: VALID Position */ +#define EADC_DAT8_VALID_Msk (0x1ul << EADC_DAT8_VALID_Pos) /*!< EADC_T::DAT8: VALID Mask */ + +#define EADC_CURDAT_CURDAT_Pos (0) /*!< EADC_T::CURDAT: CURDAT Position */ +#define EADC_CURDAT_CURDAT_Msk (0x3fffful << EADC_CURDAT_CURDAT_Pos) /*!< EADC_T::CURDAT: CURDAT Mask */ + +#define EADC_CTL_ADCEN_Pos (0) /*!< EADC_T::CTL: ADCEN Position */ +#define EADC_CTL_ADCEN_Msk (0x1ul << EADC_CTL_ADCEN_Pos) /*!< EADC_T::CTL: ADCEN Mask */ + +#define EADC_CTL_ADCRST_Pos (1) /*!< EADC_T::CTL: ADCRST Position */ +#define EADC_CTL_ADCRST_Msk (0x1ul << EADC_CTL_ADCRST_Pos) /*!< EADC_T::CTL: ADCRST Mask */ + +#define EADC_CTL_ADCIEN0_Pos (2) /*!< EADC_T::CTL: ADCIEN0 Position */ +#define EADC_CTL_ADCIEN0_Msk (0x1ul << EADC_CTL_ADCIEN0_Pos) /*!< EADC_T::CTL: ADCIEN0 Mask */ + +#define EADC_CTL_ADCIEN1_Pos (3) /*!< EADC_T::CTL: ADCIEN1 Position */ +#define EADC_CTL_ADCIEN1_Msk (0x1ul << EADC_CTL_ADCIEN1_Pos) /*!< EADC_T::CTL: ADCIEN1 Mask */ + +#define EADC_CTL_ADCIEN2_Pos (4) /*!< EADC_T::CTL: ADCIEN2 Position */ +#define EADC_CTL_ADCIEN2_Msk (0x1ul << EADC_CTL_ADCIEN2_Pos) /*!< EADC_T::CTL: ADCIEN2 Mask */ + +#define EADC_CTL_ADCIEN3_Pos (5) /*!< EADC_T::CTL: ADCIEN3 Position */ +#define EADC_CTL_ADCIEN3_Msk (0x1ul << EADC_CTL_ADCIEN3_Pos) /*!< EADC_T::CTL: ADCIEN3 Mask */ + +#define EADC_CTL_RES_Pos (6) /*!< EADC_T::CTL: RES Position */ +#define EADC_CTL_RES_Msk (0x3ul << EADC_CTL_RES_Pos) /*!< EADC_T::CTL: RES Mask */ + +#define EADC_CTL_DIFFEN_Pos (8) /*!< EADC_T::CTL: DIFFEN Position */ +#define EADC_CTL_DIFFEN_Msk (0x1ul << EADC_CTL_DIFFEN_Pos) /*!< EADC_T::CTL: DIFFEN Mask */ + +#define EADC_CTL_DMOF_Pos (9) /*!< EADC_T::CTL: DMOF Position */ +#define EADC_CTL_DMOF_Msk (0x1ul << EADC_CTL_DMOF_Pos) /*!< EADC_T::CTL: DMOF Mask */ + +#define EADC_CTL_VREFSEL_Pos (10) /*!< EADC_T::CTL: VREFSEL Position */ +#define EADC_CTL_VREFSEL_Msk (0x3ul << EADC_CTL_VREFSEL_Pos) /*!< EADC_T::CTL: VREFSEL Mask */ + +#define EADC_CTL_SPEED_Pos (12) /*!< EADC_T::CTL: SPEED Position */ +#define EADC_CTL_SPEED_Msk (0x1ul << EADC_CTL_SPEED_Pos) /*!< EADC_T::CTL: SPEED Mask */ + +#define EADC_SWTRG_SWTRG_Pos (0) /*!< EADC_T::SWTRG: SWTRG Position */ +#define EADC_SWTRG_SWTRG_Msk (0x1fful << EADC_SWTRG_SWTRG_Pos) /*!< EADC_T::SWTRG: SWTRG Mask */ + +#define EADC_PENDSTS_STPF_Pos (0) /*!< EADC_T::PENDSTS: STPF Position */ +#define EADC_PENDSTS_STPF_Msk (0x1fful << EADC_PENDSTS_STPF_Pos) /*!< EADC_T::PENDSTS: STPF Mask */ + +#define EADC_OVSTS_SPOVF_Pos (0) /*!< EADC_T::OVSTS: SPOVF Position */ +#define EADC_OVSTS_SPOVF_Msk (0x1fful << EADC_OVSTS_SPOVF_Pos) /*!< EADC_T::OVSTS: SPOVF Mask */ + +#define EADC_SCTL_CHSEL_Pos (0) /*!< EADC_T::SCTL: CHSEL Position */ +#define EADC_SCTL_CHSEL_Msk (0xful << EADC_SCTL_CHSEL_Pos) /*!< EADC_T::SCTL: CHSEL Mask */ + +#define EADC_SCTL_EXTREN_Pos (4) /*!< EADC_T::SCTL: EXTREN Position */ +#define EADC_SCTL_EXTREN_Msk (0x1ul << EADC_SCTL_EXTREN_Pos) /*!< EADC_T::SCTL: EXTREN Mask */ + +#define EADC_SCTL_EXTFEN_Pos (5) /*!< EADC_T::SCTL: EXTFEN Position */ +#define EADC_SCTL_EXTFEN_Msk (0x1ul << EADC_SCTL_EXTFEN_Pos) /*!< EADC_T::SCTL: EXTFEN Mask */ + +#define EADC_SCTL_TRGDLYDIV_Pos (6) /*!< EADC_T::SCTL: TRGDLYDIV Position */ +#define EADC_SCTL_TRGDLYDIV_Msk (0x3ul << EADC_SCTL_TRGDLYDIV_Pos) /*!< EADC_T::SCTL: TRGDLYDIV Mask */ + +#define EADC_SCTL_TRGDLYCNT_Pos (8) /*!< EADC_T::SCTL: TRGDLYCNT Position */ +#define EADC_SCTL_TRGDLYCNT_Msk (0xfful << EADC_SCTL_TRGDLYCNT_Pos) /*!< EADC_T::SCTL: TRGDLYCNT Mask */ + +#define EADC_SCTL_TRGSEL_Pos (16) /*!< EADC_T::SCTL: TRGSEL Position */ +#define EADC_SCTL_TRGSEL_Msk (0x1ful << EADC_SCTL_TRGSEL_Pos) /*!< EADC_T::SCTL: TRGSEL Mask */ + +#define EADC_SCTL_INTPOS_Pos (22) /*!< EADC_T::SCTL: INTPOS Position */ +#define EADC_SCTL_INTPOS_Msk (0x1ul << EADC_SCTL_INTPOS_Pos) /*!< EADC_T::SCTL: INTPOS Mask */ + +#define EADC_SCTL_DBMEN_Pos (23) /*!< EADC_T::SCTL: DBMEN Position */ +#define EADC_SCTL_DBMEN_Msk (0x1ul << EADC_SCTL_DBMEN_Pos) /*!< EADC_T::SCTL: DBMEN Mask */ + +#define EADC_SCTL_EXTSMPT_Pos (24) /*!< EADC_T::SCTL: EXTSMPT Position */ +#define EADC_SCTL_EXTSMPT_Msk (0xfful << EADC_SCTL_EXTSMPT_Pos) /*!< EADC_T::SCTL: EXTSMPT Mask */ + +#define EADC_SCTL0_CHSEL_Pos (0) /*!< EADC_T::SCTL0: CHSEL Position */ +#define EADC_SCTL0_CHSEL_Msk (0xful << EADC_SCTL0_CHSEL_Pos) /*!< EADC_T::SCTL0: CHSEL Mask */ + +#define EADC_SCTL0_EXTREN_Pos (4) /*!< EADC_T::SCTL0: EXTREN Position */ +#define EADC_SCTL0_EXTREN_Msk (0x1ul << EADC_SCTL0_EXTREN_Pos) /*!< EADC_T::SCTL0: EXTREN Mask */ + +#define EADC_SCTL0_EXTFEN_Pos (5) /*!< EADC_T::SCTL0: EXTFEN Position */ +#define EADC_SCTL0_EXTFEN_Msk (0x1ul << EADC_SCTL0_EXTFEN_Pos) /*!< EADC_T::SCTL0: EXTFEN Mask */ + +#define EADC_SCTL0_TRGDLYDIV_Pos (6) /*!< EADC_T::SCTL0: TRGDLYDIV Position */ +#define EADC_SCTL0_TRGDLYDIV_Msk (0x3ul << EADC_SCTL0_TRGDLYDIV_Pos) /*!< EADC_T::SCTL0: TRGDLYDIV Mask */ + +#define EADC_SCTL0_TRGDLYCNT_Pos (8) /*!< EADC_T::SCTL0: TRGDLYCNT Position */ +#define EADC_SCTL0_TRGDLYCNT_Msk (0xfful << EADC_SCTL0_TRGDLYCNT_Pos) /*!< EADC_T::SCTL0: TRGDLYCNT Mask */ + +#define EADC_SCTL0_TRGSEL_Pos (16) /*!< EADC_T::SCTL0: TRGSEL Position */ +#define EADC_SCTL0_TRGSEL_Msk (0x3ful << EADC_SCTL0_TRGSEL_Pos) /*!< EADC_T::SCTL0: TRGSEL Mask */ + +#define EADC_SCTL0_INTPOS_Pos (22) /*!< EADC_T::SCTL0: INTPOS Position */ +#define EADC_SCTL0_INTPOS_Msk (0x1ul << EADC_SCTL0_INTPOS_Pos) /*!< EADC_T::SCTL0: INTPOS Mask */ + +#define EADC_SCTL0_DBMEN_Pos (23) /*!< EADC_T::SCTL0: DBMEN Position */ +#define EADC_SCTL0_DBMEN_Msk (0x1ul << EADC_SCTL0_DBMEN_Pos) /*!< EADC_T::SCTL0: DBMEN Mask */ + +#define EADC_SCTL1_CHSEL_Pos (0) /*!< EADC_T::SCTL1: CHSEL Position */ +#define EADC_SCTL1_CHSEL_Msk (0xful << EADC_SCTL1_CHSEL_Pos) /*!< EADC_T::SCTL1: CHSEL Mask */ + +#define EADC_SCTL1_EXTREN_Pos (4) /*!< EADC_T::SCTL1: EXTREN Position */ +#define EADC_SCTL1_EXTREN_Msk (0x1ul << EADC_SCTL1_EXTREN_Pos) /*!< EADC_T::SCTL1: EXTREN Mask */ + +#define EADC_SCTL1_EXTFEN_Pos (5) /*!< EADC_T::SCTL1: EXTFEN Position */ +#define EADC_SCTL1_EXTFEN_Msk (0x1ul << EADC_SCTL1_EXTFEN_Pos) /*!< EADC_T::SCTL1: EXTFEN Mask */ + +#define EADC_SCTL1_TRGDLYDIV_Pos (6) /*!< EADC_T::SCTL1: TRGDLYDIV Position */ +#define EADC_SCTL1_TRGDLYDIV_Msk (0x3ul << EADC_SCTL1_TRGDLYDIV_Pos) /*!< EADC_T::SCTL1: TRGDLYDIV Mask */ + +#define EADC_SCTL1_TRGDLYCNT_Pos (8) /*!< EADC_T::SCTL1: TRGDLYCNT Position */ +#define EADC_SCTL1_TRGDLYCNT_Msk (0xfful << EADC_SCTL1_TRGDLYCNT_Pos) /*!< EADC_T::SCTL1: TRGDLYCNT Mask */ + +#define EADC_SCTL1_TRGSEL_Pos (16) /*!< EADC_T::SCTL1: TRGSEL Position */ +#define EADC_SCTL1_TRGSEL_Msk (0x3ful << EADC_SCTL1_TRGSEL_Pos) /*!< EADC_T::SCTL1: TRGSEL Mask */ + +#define EADC_SCTL1_INTPOS_Pos (22) /*!< EADC_T::SCTL1: INTPOS Position */ +#define EADC_SCTL1_INTPOS_Msk (0x1ul << EADC_SCTL1_INTPOS_Pos) /*!< EADC_T::SCTL1: INTPOS Mask */ + +#define EADC_SCTL1_DBMEN_Pos (23) /*!< EADC_T::SCTL1: DBMEN Position */ +#define EADC_SCTL1_DBMEN_Msk (0x1ul << EADC_SCTL1_DBMEN_Pos) /*!< EADC_T::SCTL1: DBMEN Mask */ + +#define EADC_SCTL2_CHSEL_Pos (0) /*!< EADC_T::SCTL2: CHSEL Position */ +#define EADC_SCTL2_CHSEL_Msk (0xful << EADC_SCTL2_CHSEL_Pos) /*!< EADC_T::SCTL2: CHSEL Mask */ + +#define EADC_SCTL2_EXTREN_Pos (4) /*!< EADC_T::SCTL2: EXTREN Position */ +#define EADC_SCTL2_EXTREN_Msk (0x1ul << EADC_SCTL2_EXTREN_Pos) /*!< EADC_T::SCTL2: EXTREN Mask */ + +#define EADC_SCTL2_EXTFEN_Pos (5) /*!< EADC_T::SCTL2: EXTFEN Position */ +#define EADC_SCTL2_EXTFEN_Msk (0x1ul << EADC_SCTL2_EXTFEN_Pos) /*!< EADC_T::SCTL2: EXTFEN Mask */ + +#define EADC_SCTL2_TRGDLYDIV_Pos (6) /*!< EADC_T::SCTL2: TRGDLYDIV Position */ +#define EADC_SCTL2_TRGDLYDIV_Msk (0x3ul << EADC_SCTL2_TRGDLYDIV_Pos) /*!< EADC_T::SCTL2: TRGDLYDIV Mask */ + +#define EADC_SCTL2_TRGDLYCNT_Pos (8) /*!< EADC_T::SCTL2: TRGDLYCNT Position */ +#define EADC_SCTL2_TRGDLYCNT_Msk (0xfful << EADC_SCTL2_TRGDLYCNT_Pos) /*!< EADC_T::SCTL2: TRGDLYCNT Mask */ + +#define EADC_SCTL2_TRGSEL_Pos (16) /*!< EADC_T::SCTL2: TRGSEL Position */ +#define EADC_SCTL2_TRGSEL_Msk (0x3ful << EADC_SCTL2_TRGSEL_Pos) /*!< EADC_T::SCTL2: TRGSEL Mask */ + +#define EADC_SCTL2_INTPOS_Pos (22) /*!< EADC_T::SCTL2: INTPOS Position */ +#define EADC_SCTL2_INTPOS_Msk (0x1ul << EADC_SCTL2_INTPOS_Pos) /*!< EADC_T::SCTL2: INTPOS Mask */ + +#define EADC_SCTL2_DBMEN_Pos (23) /*!< EADC_T::SCTL2: DBMEN Position */ +#define EADC_SCTL2_DBMEN_Msk (0x1ul << EADC_SCTL2_DBMEN_Pos) /*!< EADC_T::SCTL2: DBMEN Mask */ + +#define EADC_SCTL3_CHSEL_Pos (0) /*!< EADC_T::SCTL3: CHSEL Position */ +#define EADC_SCTL3_CHSEL_Msk (0xful << EADC_SCTL3_CHSEL_Pos) /*!< EADC_T::SCTL3: CHSEL Mask */ + +#define EADC_SCTL3_EXTREN_Pos (4) /*!< EADC_T::SCTL3: EXTREN Position */ +#define EADC_SCTL3_EXTREN_Msk (0x1ul << EADC_SCTL3_EXTREN_Pos) /*!< EADC_T::SCTL3: EXTREN Mask */ + +#define EADC_SCTL3_EXTFEN_Pos (5) /*!< EADC_T::SCTL3: EXTFEN Position */ +#define EADC_SCTL3_EXTFEN_Msk (0x1ul << EADC_SCTL3_EXTFEN_Pos) /*!< EADC_T::SCTL3: EXTFEN Mask */ + +#define EADC_SCTL3_TRGDLYDIV_Pos (6) /*!< EADC_T::SCTL3: TRGDLYDIV Position */ +#define EADC_SCTL3_TRGDLYDIV_Msk (0x3ul << EADC_SCTL3_TRGDLYDIV_Pos) /*!< EADC_T::SCTL3: TRGDLYDIV Mask */ + +#define EADC_SCTL3_TRGDLYCNT_Pos (8) /*!< EADC_T::SCTL3: TRGDLYCNT Position */ +#define EADC_SCTL3_TRGDLYCNT_Msk (0xfful << EADC_SCTL3_TRGDLYCNT_Pos) /*!< EADC_T::SCTL3: TRGDLYCNT Mask */ + +#define EADC_SCTL3_TRGSEL_Pos (16) /*!< EADC_T::SCTL3: TRGSEL Position */ +#define EADC_SCTL3_TRGSEL_Msk (0x3ful << EADC_SCTL3_TRGSEL_Pos) /*!< EADC_T::SCTL3: TRGSEL Mask */ + +#define EADC_SCTL3_INTPOS_Pos (22) /*!< EADC_T::SCTL3: INTPOS Position */ +#define EADC_SCTL3_INTPOS_Msk (0x1ul << EADC_SCTL3_INTPOS_Pos) /*!< EADC_T::SCTL3: INTPOS Mask */ + +#define EADC_SCTL3_DBMEN_Pos (23) /*!< EADC_T::SCTL3: DBMEN Position */ +#define EADC_SCTL3_DBMEN_Msk (0x1ul << EADC_SCTL3_DBMEN_Pos) /*!< EADC_T::SCTL3: DBMEN Mask */ + +#define EADC_SCTL4_CHSEL_Pos (0) /*!< EADC_T::SCTL4: CHSEL Position */ +#define EADC_SCTL4_CHSEL_Msk (0xful << EADC_SCTL4_CHSEL_Pos) /*!< EADC_T::SCTL4: CHSEL Mask */ + +#define EADC_SCTL4_EXTREN_Pos (4) /*!< EADC_T::SCTL4: EXTREN Position */ +#define EADC_SCTL4_EXTREN_Msk (0x1ul << EADC_SCTL4_EXTREN_Pos) /*!< EADC_T::SCTL4: EXTREN Mask */ + +#define EADC_SCTL4_EXTFEN_Pos (5) /*!< EADC_T::SCTL4: EXTFEN Position */ +#define EADC_SCTL4_EXTFEN_Msk (0x1ul << EADC_SCTL4_EXTFEN_Pos) /*!< EADC_T::SCTL4: EXTFEN Mask */ + +#define EADC_SCTL4_TRGDLYDIV_Pos (6) /*!< EADC_T::SCTL4: TRGDLYDIV Position */ +#define EADC_SCTL4_TRGDLYDIV_Msk (0x3ul << EADC_SCTL4_TRGDLYDIV_Pos) /*!< EADC_T::SCTL4: TRGDLYDIV Mask */ + +#define EADC_SCTL4_TRGDLYCNT_Pos (8) /*!< EADC_T::SCTL4: TRGDLYCNT Position */ +#define EADC_SCTL4_TRGDLYCNT_Msk (0xfful << EADC_SCTL4_TRGDLYCNT_Pos) /*!< EADC_T::SCTL4: TRGDLYCNT Mask */ + +#define EADC_SCTL4_TRGSEL_Pos (16) /*!< EADC_T::SCTL4: TRGSEL Position */ +#define EADC_SCTL4_TRGSEL_Msk (0x3ful << EADC_SCTL4_TRGSEL_Pos) /*!< EADC_T::SCTL4: TRGSEL Mask */ + +#define EADC_SCTL4_INTPOS_Pos (22) /*!< EADC_T::SCTL4: INTPOS Position */ +#define EADC_SCTL4_INTPOS_Msk (0x1ul << EADC_SCTL4_INTPOS_Pos) /*!< EADC_T::SCTL4: INTPOS Mask */ + +#define EADC_SCTL5_CHSEL_Pos (0) /*!< EADC_T::SCTL5: CHSEL Position */ +#define EADC_SCTL5_CHSEL_Msk (0xful << EADC_SCTL5_CHSEL_Pos) /*!< EADC_T::SCTL5: CHSEL Mask */ + +#define EADC_SCTL5_EXTREN_Pos (4) /*!< EADC_T::SCTL5: EXTREN Position */ +#define EADC_SCTL5_EXTREN_Msk (0x1ul << EADC_SCTL5_EXTREN_Pos) /*!< EADC_T::SCTL5: EXTREN Mask */ + +#define EADC_SCTL5_EXTFEN_Pos (5) /*!< EADC_T::SCTL5: EXTFEN Position */ +#define EADC_SCTL5_EXTFEN_Msk (0x1ul << EADC_SCTL5_EXTFEN_Pos) /*!< EADC_T::SCTL5: EXTFEN Mask */ + +#define EADC_SCTL5_TRGDLYDIV_Pos (6) /*!< EADC_T::SCTL5: TRGDLYDIV Position */ +#define EADC_SCTL5_TRGDLYDIV_Msk (0x3ul << EADC_SCTL5_TRGDLYDIV_Pos) /*!< EADC_T::SCTL5: TRGDLYDIV Mask */ + +#define EADC_SCTL5_TRGDLYCNT_Pos (8) /*!< EADC_T::SCTL5: TRGDLYCNT Position */ +#define EADC_SCTL5_TRGDLYCNT_Msk (0xfful << EADC_SCTL5_TRGDLYCNT_Pos) /*!< EADC_T::SCTL5: TRGDLYCNT Mask */ + +#define EADC_SCTL5_TRGSEL_Pos (16) /*!< EADC_T::SCTL5: TRGSEL Position */ +#define EADC_SCTL5_TRGSEL_Msk (0x3ful << EADC_SCTL5_TRGSEL_Pos) /*!< EADC_T::SCTL5: TRGSEL Mask */ + +#define EADC_SCTL5_INTPOS_Pos (22) /*!< EADC_T::SCTL5: INTPOS Position */ +#define EADC_SCTL5_INTPOS_Msk (0x1ul << EADC_SCTL5_INTPOS_Pos) /*!< EADC_T::SCTL5: INTPOS Mask */ + +#define EADC_SCTL6_CHSEL_Pos (0) /*!< EADC_T::SCTL6: CHSEL Position */ +#define EADC_SCTL6_CHSEL_Msk (0xful << EADC_SCTL6_CHSEL_Pos) /*!< EADC_T::SCTL6: CHSEL Mask */ + +#define EADC_SCTL6_EXTREN_Pos (4) /*!< EADC_T::SCTL6: EXTREN Position */ +#define EADC_SCTL6_EXTREN_Msk (0x1ul << EADC_SCTL6_EXTREN_Pos) /*!< EADC_T::SCTL6: EXTREN Mask */ + +#define EADC_SCTL6_EXTFEN_Pos (5) /*!< EADC_T::SCTL6: EXTFEN Position */ +#define EADC_SCTL6_EXTFEN_Msk (0x1ul << EADC_SCTL6_EXTFEN_Pos) /*!< EADC_T::SCTL6: EXTFEN Mask */ + +#define EADC_SCTL6_TRGDLYDIV_Pos (6) /*!< EADC_T::SCTL6: TRGDLYDIV Position */ +#define EADC_SCTL6_TRGDLYDIV_Msk (0x3ul << EADC_SCTL6_TRGDLYDIV_Pos) /*!< EADC_T::SCTL6: TRGDLYDIV Mask */ + +#define EADC_SCTL6_TRGDLYCNT_Pos (8) /*!< EADC_T::SCTL6: TRGDLYCNT Position */ +#define EADC_SCTL6_TRGDLYCNT_Msk (0xfful << EADC_SCTL6_TRGDLYCNT_Pos) /*!< EADC_T::SCTL6: TRGDLYCNT Mask */ + +#define EADC_SCTL6_TRGSEL_Pos (16) /*!< EADC_T::SCTL6: TRGSEL Position */ +#define EADC_SCTL6_TRGSEL_Msk (0x3ful << EADC_SCTL6_TRGSEL_Pos) /*!< EADC_T::SCTL6: TRGSEL Mask */ + +#define EADC_SCTL6_INTPOS_Pos (22) /*!< EADC_T::SCTL6: INTPOS Position */ +#define EADC_SCTL6_INTPOS_Msk (0x1ul << EADC_SCTL6_INTPOS_Pos) /*!< EADC_T::SCTL6: INTPOS Mask */ + +#define EADC_SCTL7_CHSEL_Pos (0) /*!< EADC_T::SCTL7: CHSEL Position */ +#define EADC_SCTL7_CHSEL_Msk (0xful << EADC_SCTL7_CHSEL_Pos) /*!< EADC_T::SCTL7: CHSEL Mask */ + +#define EADC_SCTL7_EXTREN_Pos (4) /*!< EADC_T::SCTL7: EXTREN Position */ +#define EADC_SCTL7_EXTREN_Msk (0x1ul << EADC_SCTL7_EXTREN_Pos) /*!< EADC_T::SCTL7: EXTREN Mask */ + +#define EADC_SCTL7_EXTFEN_Pos (5) /*!< EADC_T::SCTL7: EXTFEN Position */ +#define EADC_SCTL7_EXTFEN_Msk (0x1ul << EADC_SCTL7_EXTFEN_Pos) /*!< EADC_T::SCTL7: EXTFEN Mask */ + +#define EADC_SCTL7_TRGDLYDIV_Pos (6) /*!< EADC_T::SCTL7: TRGDLYDIV Position */ +#define EADC_SCTL7_TRGDLYDIV_Msk (0x3ul << EADC_SCTL7_TRGDLYDIV_Pos) /*!< EADC_T::SCTL7: TRGDLYDIV Mask */ + +#define EADC_SCTL7_TRGDLYCNT_Pos (8) /*!< EADC_T::SCTL7: TRGDLYCNT Position */ +#define EADC_SCTL7_TRGDLYCNT_Msk (0xfful << EADC_SCTL7_TRGDLYCNT_Pos) /*!< EADC_T::SCTL7: TRGDLYCNT Mask */ + +#define EADC_SCTL7_TRGSEL_Pos (16) /*!< EADC_T::SCTL7: TRGSEL Position */ +#define EADC_SCTL7_TRGSEL_Msk (0x3ful << EADC_SCTL7_TRGSEL_Pos) /*!< EADC_T::SCTL7: TRGSEL Mask */ + +#define EADC_SCTL7_INTPOS_Pos (22) /*!< EADC_T::SCTL7: INTPOS Position */ +#define EADC_SCTL7_INTPOS_Msk (0x1ul << EADC_SCTL7_INTPOS_Pos) /*!< EADC_T::SCTL7: INTPOS Mask */ + +#define EADC_INTSRC0_SPLIE0_Pos (0) /*!< EADC_T::INTSRC0: SPLIE0 Position */ +#define EADC_INTSRC0_SPLIE0_Msk (0x1ul << EADC_INTSRC0_SPLIE0_Pos) /*!< EADC_T::INTSRC0: SPLIE0 Mask */ + +#define EADC_INTSRC0_SPLIE1_Pos (1) /*!< EADC_T::INTSRC0: SPLIE1 Position */ +#define EADC_INTSRC0_SPLIE1_Msk (0x1ul << EADC_INTSRC0_SPLIE1_Pos) /*!< EADC_T::INTSRC0: SPLIE1 Mask */ + +#define EADC_INTSRC0_SPLIE2_Pos (2) /*!< EADC_T::INTSRC0: SPLIE2 Position */ +#define EADC_INTSRC0_SPLIE2_Msk (0x1ul << EADC_INTSRC0_SPLIE2_Pos) /*!< EADC_T::INTSRC0: SPLIE2 Mask */ + +#define EADC_INTSRC0_SPLIE3_Pos (3) /*!< EADC_T::INTSRC0: SPLIE3 Position */ +#define EADC_INTSRC0_SPLIE3_Msk (0x1ul << EADC_INTSRC0_SPLIE3_Pos) /*!< EADC_T::INTSRC0: SPLIE3 Mask */ + +#define EADC_INTSRC0_SPLIE4_Pos (4) /*!< EADC_T::INTSRC0: SPLIE4 Position */ +#define EADC_INTSRC0_SPLIE4_Msk (0x1ul << EADC_INTSRC0_SPLIE4_Pos) /*!< EADC_T::INTSRC0: SPLIE4 Mask */ + +#define EADC_INTSRC0_SPLIE5_Pos (5) /*!< EADC_T::INTSRC0: SPLIE5 Position */ +#define EADC_INTSRC0_SPLIE5_Msk (0x1ul << EADC_INTSRC0_SPLIE5_Pos) /*!< EADC_T::INTSRC0: SPLIE5 Mask */ + +#define EADC_INTSRC0_SPLIE6_Pos (6) /*!< EADC_T::INTSRC0: SPLIE6 Position */ +#define EADC_INTSRC0_SPLIE6_Msk (0x1ul << EADC_INTSRC0_SPLIE6_Pos) /*!< EADC_T::INTSRC0: SPLIE6 Mask */ + +#define EADC_INTSRC0_SPLIE7_Pos (7) /*!< EADC_T::INTSRC0: SPLIE7 Position */ +#define EADC_INTSRC0_SPLIE7_Msk (0x1ul << EADC_INTSRC0_SPLIE7_Pos) /*!< EADC_T::INTSRC0: SPLIE7 Mask */ + +#define EADC_INTSRC0_SPLIE8_Pos (8) /*!< EADC_T::INTSRC0: SPLIE8 Position */ +#define EADC_INTSRC0_SPLIE8_Msk (0x1ul << EADC_INTSRC0_SPLIE8_Pos) /*!< EADC_T::INTSRC0: SPLIE8 Mask */ + +#define EADC_INTSRC1_SPLIE0_Pos (0) /*!< EADC_T::INTSRC1: SPLIE0 Position */ +#define EADC_INTSRC1_SPLIE0_Msk (0x1ul << EADC_INTSRC1_SPLIE0_Pos) /*!< EADC_T::INTSRC1: SPLIE0 Mask */ + +#define EADC_INTSRC1_SPLIE1_Pos (1) /*!< EADC_T::INTSRC1: SPLIE1 Position */ +#define EADC_INTSRC1_SPLIE1_Msk (0x1ul << EADC_INTSRC1_SPLIE1_Pos) /*!< EADC_T::INTSRC1: SPLIE1 Mask */ + +#define EADC_INTSRC1_SPLIE2_Pos (2) /*!< EADC_T::INTSRC1: SPLIE2 Position */ +#define EADC_INTSRC1_SPLIE2_Msk (0x1ul << EADC_INTSRC1_SPLIE2_Pos) /*!< EADC_T::INTSRC1: SPLIE2 Mask */ + +#define EADC_INTSRC1_SPLIE3_Pos (3) /*!< EADC_T::INTSRC1: SPLIE3 Position */ +#define EADC_INTSRC1_SPLIE3_Msk (0x1ul << EADC_INTSRC1_SPLIE3_Pos) /*!< EADC_T::INTSRC1: SPLIE3 Mask */ + +#define EADC_INTSRC1_SPLIE4_Pos (4) /*!< EADC_T::INTSRC1: SPLIE4 Position */ +#define EADC_INTSRC1_SPLIE4_Msk (0x1ul << EADC_INTSRC1_SPLIE4_Pos) /*!< EADC_T::INTSRC1: SPLIE4 Mask */ + +#define EADC_INTSRC1_SPLIE5_Pos (5) /*!< EADC_T::INTSRC1: SPLIE5 Position */ +#define EADC_INTSRC1_SPLIE5_Msk (0x1ul << EADC_INTSRC1_SPLIE5_Pos) /*!< EADC_T::INTSRC1: SPLIE5 Mask */ + +#define EADC_INTSRC1_SPLIE6_Pos (6) /*!< EADC_T::INTSRC1: SPLIE6 Position */ +#define EADC_INTSRC1_SPLIE6_Msk (0x1ul << EADC_INTSRC1_SPLIE6_Pos) /*!< EADC_T::INTSRC1: SPLIE6 Mask */ + +#define EADC_INTSRC1_SPLIE7_Pos (7) /*!< EADC_T::INTSRC1: SPLIE7 Position */ +#define EADC_INTSRC1_SPLIE7_Msk (0x1ul << EADC_INTSRC1_SPLIE7_Pos) /*!< EADC_T::INTSRC1: SPLIE7 Mask */ + +#define EADC_INTSRC1_SPLIE8_Pos (8) /*!< EADC_T::INTSRC1: SPLIE8 Position */ +#define EADC_INTSRC1_SPLIE8_Msk (0x1ul << EADC_INTSRC1_SPLIE8_Pos) /*!< EADC_T::INTSRC1: SPLIE8 Mask */ + +#define EADC_INTSRC2_SPLIE0_Pos (0) /*!< EADC_T::INTSRC2: SPLIE0 Position */ +#define EADC_INTSRC2_SPLIE0_Msk (0x1ul << EADC_INTSRC2_SPLIE0_Pos) /*!< EADC_T::INTSRC2: SPLIE0 Mask */ + +#define EADC_INTSRC2_SPLIE1_Pos (1) /*!< EADC_T::INTSRC2: SPLIE1 Position */ +#define EADC_INTSRC2_SPLIE1_Msk (0x1ul << EADC_INTSRC2_SPLIE1_Pos) /*!< EADC_T::INTSRC2: SPLIE1 Mask */ + +#define EADC_INTSRC2_SPLIE2_Pos (2) /*!< EADC_T::INTSRC2: SPLIE2 Position */ +#define EADC_INTSRC2_SPLIE2_Msk (0x1ul << EADC_INTSRC2_SPLIE2_Pos) /*!< EADC_T::INTSRC2: SPLIE2 Mask */ + +#define EADC_INTSRC2_SPLIE3_Pos (3) /*!< EADC_T::INTSRC2: SPLIE3 Position */ +#define EADC_INTSRC2_SPLIE3_Msk (0x1ul << EADC_INTSRC2_SPLIE3_Pos) /*!< EADC_T::INTSRC2: SPLIE3 Mask */ + +#define EADC_INTSRC2_SPLIE4_Pos (4) /*!< EADC_T::INTSRC2: SPLIE4 Position */ +#define EADC_INTSRC2_SPLIE4_Msk (0x1ul << EADC_INTSRC2_SPLIE4_Pos) /*!< EADC_T::INTSRC2: SPLIE4 Mask */ + +#define EADC_INTSRC2_SPLIE5_Pos (5) /*!< EADC_T::INTSRC2: SPLIE5 Position */ +#define EADC_INTSRC2_SPLIE5_Msk (0x1ul << EADC_INTSRC2_SPLIE5_Pos) /*!< EADC_T::INTSRC2: SPLIE5 Mask */ + +#define EADC_INTSRC2_SPLIE6_Pos (6) /*!< EADC_T::INTSRC2: SPLIE6 Position */ +#define EADC_INTSRC2_SPLIE6_Msk (0x1ul << EADC_INTSRC2_SPLIE6_Pos) /*!< EADC_T::INTSRC2: SPLIE6 Mask */ + +#define EADC_INTSRC2_SPLIE7_Pos (7) /*!< EADC_T::INTSRC2: SPLIE7 Position */ +#define EADC_INTSRC2_SPLIE7_Msk (0x1ul << EADC_INTSRC2_SPLIE7_Pos) /*!< EADC_T::INTSRC2: SPLIE7 Mask */ + +#define EADC_INTSRC2_SPLIE8_Pos (8) /*!< EADC_T::INTSRC2: SPLIE8 Position */ +#define EADC_INTSRC2_SPLIE8_Msk (0x1ul << EADC_INTSRC2_SPLIE8_Pos) /*!< EADC_T::INTSRC2: SPLIE8 Mask */ + +#define EADC_INTSRC3_SPLIE0_Pos (0) /*!< EADC_T::INTSRC3: SPLIE0 Position */ +#define EADC_INTSRC3_SPLIE0_Msk (0x1ul << EADC_INTSRC3_SPLIE0_Pos) /*!< EADC_T::INTSRC3: SPLIE0 Mask */ + +#define EADC_INTSRC3_SPLIE1_Pos (1) /*!< EADC_T::INTSRC3: SPLIE1 Position */ +#define EADC_INTSRC3_SPLIE1_Msk (0x1ul << EADC_INTSRC3_SPLIE1_Pos) /*!< EADC_T::INTSRC3: SPLIE1 Mask */ + +#define EADC_INTSRC3_SPLIE2_Pos (2) /*!< EADC_T::INTSRC3: SPLIE2 Position */ +#define EADC_INTSRC3_SPLIE2_Msk (0x1ul << EADC_INTSRC3_SPLIE2_Pos) /*!< EADC_T::INTSRC3: SPLIE2 Mask */ + +#define EADC_INTSRC3_SPLIE3_Pos (3) /*!< EADC_T::INTSRC3: SPLIE3 Position */ +#define EADC_INTSRC3_SPLIE3_Msk (0x1ul << EADC_INTSRC3_SPLIE3_Pos) /*!< EADC_T::INTSRC3: SPLIE3 Mask */ + +#define EADC_INTSRC3_SPLIE4_Pos (4) /*!< EADC_T::INTSRC3: SPLIE4 Position */ +#define EADC_INTSRC3_SPLIE4_Msk (0x1ul << EADC_INTSRC3_SPLIE4_Pos) /*!< EADC_T::INTSRC3: SPLIE4 Mask */ + +#define EADC_INTSRC3_SPLIE5_Pos (5) /*!< EADC_T::INTSRC3: SPLIE5 Position */ +#define EADC_INTSRC3_SPLIE5_Msk (0x1ul << EADC_INTSRC3_SPLIE5_Pos) /*!< EADC_T::INTSRC3: SPLIE5 Mask */ + +#define EADC_INTSRC3_SPLIE6_Pos (6) /*!< EADC_T::INTSRC3: SPLIE6 Position */ +#define EADC_INTSRC3_SPLIE6_Msk (0x1ul << EADC_INTSRC3_SPLIE6_Pos) /*!< EADC_T::INTSRC3: SPLIE6 Mask */ + +#define EADC_INTSRC3_SPLIE7_Pos (7) /*!< EADC_T::INTSRC3: SPLIE7 Position */ +#define EADC_INTSRC3_SPLIE7_Msk (0x1ul << EADC_INTSRC3_SPLIE7_Pos) /*!< EADC_T::INTSRC3: SPLIE7 Mask */ + +#define EADC_INTSRC3_SPLIE8_Pos (8) /*!< EADC_T::INTSRC3: SPLIE8 Position */ +#define EADC_INTSRC3_SPLIE8_Msk (0x1ul << EADC_INTSRC3_SPLIE8_Pos) /*!< EADC_T::INTSRC3: SPLIE8 Mask */ + +#define EADC_CMP_ADCMPEN_Pos (0) /*!< EADC_T::CMP: ADCMPEN Position */ +#define EADC_CMP_ADCMPEN_Msk (0x1ul << EADC_CMP_ADCMPEN_Pos) /*!< EADC_T::CMP: ADCMPEN Mask */ + +#define EADC_CMP_ADCMPIE_Pos (1) /*!< EADC_T::CMP: ADCMPIE Position */ +#define EADC_CMP_ADCMPIE_Msk (0x1ul << EADC_CMP_ADCMPIE_Pos) /*!< EADC_T::CMP: ADCMPIE Mask */ + +#define EADC_CMP_CMPCOND_Pos (2) /*!< EADC_T::CMP: CMPCOND Position */ +#define EADC_CMP_CMPCOND_Msk (0x1ul << EADC_CMP_CMPCOND_Pos) /*!< EADC_T::CMP: CMPCOND Mask */ + +#define EADC_CMP_CMPSPL_Pos (3) /*!< EADC_T::CMP: CMPSPL Position */ +#define EADC_CMP_CMPSPL_Msk (0x1ful << EADC_CMP_CMPSPL_Pos) /*!< EADC_T::CMP: CMPSPL Mask */ + +#define EADC_CMP_CMPMCNT_Pos (8) /*!< EADC_T::CMP: CMPMCNT Position */ +#define EADC_CMP_CMPMCNT_Msk (0xful << EADC_CMP_CMPMCNT_Pos) /*!< EADC_T::CMP: CMPMCNT Mask */ + +#define EADC_CMP_CMPWEN_Pos (15) /*!< EADC_T::CMP: CMPWEN Position */ +#define EADC_CMP_CMPWEN_Msk (0x1ul << EADC_CMP_CMPWEN_Pos) /*!< EADC_T::CMP: CMPWEN Mask */ + +#define EADC_CMP_CMPDAT_Pos (16) /*!< EADC_T::CMP: CMPDAT Position */ +#define EADC_CMP_CMPDAT_Msk (0xffful << EADC_CMP_CMPDAT_Pos) /*!< EADC_T::CMP: CMPDAT Mask */ + +#define EADC_CMP0_ADCMPEN_Pos (0) /*!< EADC_T::CMP0: ADCMPEN Position */ +#define EADC_CMP0_ADCMPEN_Msk (0x1ul << EADC_CMP0_ADCMPEN_Pos) /*!< EADC_T::CMP0: ADCMPEN Mask */ + +#define EADC_CMP0_ADCMPIE_Pos (1) /*!< EADC_T::CMP0: ADCMPIE Position */ +#define EADC_CMP0_ADCMPIE_Msk (0x1ul << EADC_CMP0_ADCMPIE_Pos) /*!< EADC_T::CMP0: ADCMPIE Mask */ + +#define EADC_CMP0_CMPCOND_Pos (2) /*!< EADC_T::CMP0: CMPCOND Position */ +#define EADC_CMP0_CMPCOND_Msk (0x1ul << EADC_CMP0_CMPCOND_Pos) /*!< EADC_T::CMP0: CMPCOND Mask */ + +#define EADC_CMP0_CMPSPL_Pos (3) /*!< EADC_T::CMP0: CMPSPL Position */ +#define EADC_CMP0_CMPSPL_Msk (0xful << EADC_CMP0_CMPSPL_Pos) /*!< EADC_T::CMP0: CMPSPL Mask */ + +#define EADC_CMP0_CMPMCNT_Pos (8) /*!< EADC_T::CMP0: CMPMCNT Position */ +#define EADC_CMP0_CMPMCNT_Msk (0xful << EADC_CMP0_CMPMCNT_Pos) /*!< EADC_T::CMP0: CMPMCNT Mask */ + +#define EADC_CMP0_CMPWEN_Pos (15) /*!< EADC_T::CMP0: CMPWEN Position */ +#define EADC_CMP0_CMPWEN_Msk (0x1ul << EADC_CMP0_CMPWEN_Pos) /*!< EADC_T::CMP0: CMPWEN Mask */ + +#define EADC_CMP0_CMPDAT_Pos (16) /*!< EADC_T::CMP0: CMPDAT Position */ +#define EADC_CMP0_CMPDAT_Msk (0xffful << EADC_CMP0_CMPDAT_Pos) /*!< EADC_T::CMP0: CMPDAT Mask */ + +#define EADC_CMP1_ADCMPEN_Pos (0) /*!< EADC_T::CMP1: ADCMPEN Position */ +#define EADC_CMP1_ADCMPEN_Msk (0x1ul << EADC_CMP1_ADCMPEN_Pos) /*!< EADC_T::CMP1: ADCMPEN Mask */ + +#define EADC_CMP1_ADCMPIE_Pos (1) /*!< EADC_T::CMP1: ADCMPIE Position */ +#define EADC_CMP1_ADCMPIE_Msk (0x1ul << EADC_CMP1_ADCMPIE_Pos) /*!< EADC_T::CMP1: ADCMPIE Mask */ + +#define EADC_CMP1_CMPCOND_Pos (2) /*!< EADC_T::CMP1: CMPCOND Position */ +#define EADC_CMP1_CMPCOND_Msk (0x1ul << EADC_CMP1_CMPCOND_Pos) /*!< EADC_T::CMP1: CMPCOND Mask */ + +#define EADC_CMP1_CMPSPL_Pos (3) /*!< EADC_T::CMP1: CMPSPL Position */ +#define EADC_CMP1_CMPSPL_Msk (0xful << EADC_CMP1_CMPSPL_Pos) /*!< EADC_T::CMP1: CMPSPL Mask */ + +#define EADC_CMP1_CMPMCNT_Pos (8) /*!< EADC_T::CMP1: CMPMCNT Position */ +#define EADC_CMP1_CMPMCNT_Msk (0xful << EADC_CMP1_CMPMCNT_Pos) /*!< EADC_T::CMP1: CMPMCNT Mask */ + +#define EADC_CMP1_CMPWEN_Pos (15) /*!< EADC_T::CMP1: CMPWEN Position */ +#define EADC_CMP1_CMPWEN_Msk (0x1ul << EADC_CMP1_CMPWEN_Pos) /*!< EADC_T::CMP1: CMPWEN Mask */ + +#define EADC_CMP1_CMPDAT_Pos (16) /*!< EADC_T::CMP1: CMPDAT Position */ +#define EADC_CMP1_CMPDAT_Msk (0xffful << EADC_CMP1_CMPDAT_Pos) /*!< EADC_T::CMP1: CMPDAT Mask */ + +#define EADC_CMP2_ADCMPEN_Pos (0) /*!< EADC_T::CMP2: ADCMPEN Position */ +#define EADC_CMP2_ADCMPEN_Msk (0x1ul << EADC_CMP2_ADCMPEN_Pos) /*!< EADC_T::CMP2: ADCMPEN Mask */ + +#define EADC_CMP2_ADCMPIE_Pos (1) /*!< EADC_T::CMP2: ADCMPIE Position */ +#define EADC_CMP2_ADCMPIE_Msk (0x1ul << EADC_CMP2_ADCMPIE_Pos) /*!< EADC_T::CMP2: ADCMPIE Mask */ + +#define EADC_CMP2_CMPCOND_Pos (2) /*!< EADC_T::CMP2: CMPCOND Position */ +#define EADC_CMP2_CMPCOND_Msk (0x1ul << EADC_CMP2_CMPCOND_Pos) /*!< EADC_T::CMP2: CMPCOND Mask */ + +#define EADC_CMP2_CMPSPL_Pos (3) /*!< EADC_T::CMP2: CMPSPL Position */ +#define EADC_CMP2_CMPSPL_Msk (0xful << EADC_CMP2_CMPSPL_Pos) /*!< EADC_T::CMP2: CMPSPL Mask */ + +#define EADC_CMP2_CMPMCNT_Pos (8) /*!< EADC_T::CMP2: CMPMCNT Position */ +#define EADC_CMP2_CMPMCNT_Msk (0xful << EADC_CMP2_CMPMCNT_Pos) /*!< EADC_T::CMP2: CMPMCNT Mask */ + +#define EADC_CMP2_CMPWEN_Pos (15) /*!< EADC_T::CMP2: CMPWEN Position */ +#define EADC_CMP2_CMPWEN_Msk (0x1ul << EADC_CMP2_CMPWEN_Pos) /*!< EADC_T::CMP2: CMPWEN Mask */ + +#define EADC_CMP2_CMPDAT_Pos (16) /*!< EADC_T::CMP2: CMPDAT Position */ +#define EADC_CMP2_CMPDAT_Msk (0xffful << EADC_CMP2_CMPDAT_Pos) /*!< EADC_T::CMP2: CMPDAT Mask */ + +#define EADC_CMP3_ADCMPEN_Pos (0) /*!< EADC_T::CMP3: ADCMPEN Position */ +#define EADC_CMP3_ADCMPEN_Msk (0x1ul << EADC_CMP3_ADCMPEN_Pos) /*!< EADC_T::CMP3: ADCMPEN Mask */ + +#define EADC_CMP3_ADCMPIE_Pos (1) /*!< EADC_T::CMP3: ADCMPIE Position */ +#define EADC_CMP3_ADCMPIE_Msk (0x1ul << EADC_CMP3_ADCMPIE_Pos) /*!< EADC_T::CMP3: ADCMPIE Mask */ + +#define EADC_CMP3_CMPCOND_Pos (2) /*!< EADC_T::CMP3: CMPCOND Position */ +#define EADC_CMP3_CMPCOND_Msk (0x1ul << EADC_CMP3_CMPCOND_Pos) /*!< EADC_T::CMP3: CMPCOND Mask */ + +#define EADC_CMP3_CMPSPL_Pos (3) /*!< EADC_T::CMP3: CMPSPL Position */ +#define EADC_CMP3_CMPSPL_Msk (0xful << EADC_CMP3_CMPSPL_Pos) /*!< EADC_T::CMP3: CMPSPL Mask */ + +#define EADC_CMP3_CMPMCNT_Pos (8) /*!< EADC_T::CMP3: CMPMCNT Position */ +#define EADC_CMP3_CMPMCNT_Msk (0xful << EADC_CMP3_CMPMCNT_Pos) /*!< EADC_T::CMP3: CMPMCNT Mask */ + +#define EADC_CMP3_CMPWEN_Pos (15) /*!< EADC_T::CMP3: CMPWEN Position */ +#define EADC_CMP3_CMPWEN_Msk (0x1ul << EADC_CMP3_CMPWEN_Pos) /*!< EADC_T::CMP3: CMPWEN Mask */ + +#define EADC_CMP3_CMPDAT_Pos (16) /*!< EADC_T::CMP3: CMPDAT Position */ +#define EADC_CMP3_CMPDAT_Msk (0xffful << EADC_CMP3_CMPDAT_Pos) /*!< EADC_T::CMP3: CMPDAT Mask */ + +#define EADC_STATUS0_VALID_Pos (0) /*!< EADC_T::STATUS0: VALID Position */ +#define EADC_STATUS0_VALID_Msk (0x1fful << EADC_STATUS0_VALID_Pos) /*!< EADC_T::STATUS0: VALID Mask */ + +#define EADC_STATUS0_OV_Pos (16) /*!< EADC_T::STATUS0: OV Position */ +#define EADC_STATUS0_OV_Msk (0x1fful << EADC_STATUS0_OV_Pos) /*!< EADC_T::STATUS0: OV Mask */ + +#define EADC_STATUS2_ADIF0_Pos (0) /*!< EADC_T::STATUS2: ADIF0 Position */ +#define EADC_STATUS2_ADIF0_Msk (0x1ul << EADC_STATUS2_ADIF0_Pos) /*!< EADC_T::STATUS2: ADIF0 Mask */ + +#define EADC_STATUS2_ADIF1_Pos (1) /*!< EADC_T::STATUS2: ADIF1 Position */ +#define EADC_STATUS2_ADIF1_Msk (0x1ul << EADC_STATUS2_ADIF1_Pos) /*!< EADC_T::STATUS2: ADIF1 Mask */ + +#define EADC_STATUS2_ADIF2_Pos (2) /*!< EADC_T::STATUS2: ADIF2 Position */ +#define EADC_STATUS2_ADIF2_Msk (0x1ul << EADC_STATUS2_ADIF2_Pos) /*!< EADC_T::STATUS2: ADIF2 Mask */ + +#define EADC_STATUS2_ADIF3_Pos (3) /*!< EADC_T::STATUS2: ADIF3 Position */ +#define EADC_STATUS2_ADIF3_Msk (0x1ul << EADC_STATUS2_ADIF3_Pos) /*!< EADC_T::STATUS2: ADIF3 Mask */ + +#define EADC_STATUS2_ADCMPF0_Pos (4) /*!< EADC_T::STATUS2: ADCMPF0 Position */ +#define EADC_STATUS2_ADCMPF0_Msk (0x1ul << EADC_STATUS2_ADCMPF0_Pos) /*!< EADC_T::STATUS2: ADCMPF0 Mask */ + +#define EADC_STATUS2_ADCMPF1_Pos (5) /*!< EADC_T::STATUS2: ADCMPF1 Position */ +#define EADC_STATUS2_ADCMPF1_Msk (0x1ul << EADC_STATUS2_ADCMPF1_Pos) /*!< EADC_T::STATUS2: ADCMPF1 Mask */ + +#define EADC_STATUS2_ADCMPF2_Pos (6) /*!< EADC_T::STATUS2: ADCMPF2 Position */ +#define EADC_STATUS2_ADCMPF2_Msk (0x1ul << EADC_STATUS2_ADCMPF2_Pos) /*!< EADC_T::STATUS2: ADCMPF2 Mask */ + +#define EADC_STATUS2_ADCMPF3_Pos (7) /*!< EADC_T::STATUS2: ADCMPF3 Position */ +#define EADC_STATUS2_ADCMPF3_Msk (0x1ul << EADC_STATUS2_ADCMPF3_Pos) /*!< EADC_T::STATUS2: ADCMPF3 Mask */ + +#define EADC_STATUS2_ADOVIF0_Pos (8) /*!< EADC_T::STATUS2: ADOVIF0 Position */ +#define EADC_STATUS2_ADOVIF0_Msk (0x1ul << EADC_STATUS2_ADOVIF0_Pos) /*!< EADC_T::STATUS2: ADOVIF0 Mask */ + +#define EADC_STATUS2_ADOVIF1_Pos (9) /*!< EADC_T::STATUS2: ADOVIF1 Position */ +#define EADC_STATUS2_ADOVIF1_Msk (0x1ul << EADC_STATUS2_ADOVIF1_Pos) /*!< EADC_T::STATUS2: ADOVIF1 Mask */ + +#define EADC_STATUS2_ADOVIF2_Pos (10) /*!< EADC_T::STATUS2: ADOVIF2 Position */ +#define EADC_STATUS2_ADOVIF2_Msk (0x1ul << EADC_STATUS2_ADOVIF2_Pos) /*!< EADC_T::STATUS2: ADOVIF2 Mask */ + +#define EADC_STATUS2_ADOVIF3_Pos (11) /*!< EADC_T::STATUS2: ADOVIF3 Position */ +#define EADC_STATUS2_ADOVIF3_Msk (0x1ul << EADC_STATUS2_ADOVIF3_Pos) /*!< EADC_T::STATUS2: ADOVIF3 Mask */ + +#define EADC_STATUS2_ADCMPO0_Pos (12) /*!< EADC_T::STATUS2: ADCMPO0 Position */ +#define EADC_STATUS2_ADCMPO0_Msk (0x1ul << EADC_STATUS2_ADCMPO0_Pos) /*!< EADC_T::STATUS2: ADCMPO0 Mask */ + +#define EADC_STATUS2_ADCMPO1_Pos (13) /*!< EADC_T::STATUS2: ADCMPO1 Position */ +#define EADC_STATUS2_ADCMPO1_Msk (0x1ul << EADC_STATUS2_ADCMPO1_Pos) /*!< EADC_T::STATUS2: ADCMPO1 Mask */ + +#define EADC_STATUS2_ADCMPO2_Pos (14) /*!< EADC_T::STATUS2: ADCMPO2 Position */ +#define EADC_STATUS2_ADCMPO2_Msk (0x1ul << EADC_STATUS2_ADCMPO2_Pos) /*!< EADC_T::STATUS2: ADCMPO2 Mask */ + +#define EADC_STATUS2_ADCMPO3_Pos (15) /*!< EADC_T::STATUS2: ADCMPO3 Position */ +#define EADC_STATUS2_ADCMPO3_Msk (0x1ul << EADC_STATUS2_ADCMPO3_Pos) /*!< EADC_T::STATUS2: ADCMPO3 Mask */ + +#define EADC_STATUS2_CHANNEL_Pos (16) /*!< EADC_T::STATUS2: CHANNEL Position */ +#define EADC_STATUS2_CHANNEL_Msk (0x1ful << EADC_STATUS2_CHANNEL_Pos) /*!< EADC_T::STATUS2: CHANNEL Mask */ + +#define EADC_STATUS2_BUSY_Pos (23) /*!< EADC_T::STATUS2: BUSY Position */ +#define EADC_STATUS2_BUSY_Msk (0x1ul << EADC_STATUS2_BUSY_Pos) /*!< EADC_T::STATUS2: BUSY Mask */ + +#define EADC_STATUS2_ADOVIF_Pos (24) /*!< EADC_T::STATUS2: ADOVIF Position */ +#define EADC_STATUS2_ADOVIF_Msk (0x1ul << EADC_STATUS2_ADOVIF_Pos) /*!< EADC_T::STATUS2: ADOVIF Mask */ + +#define EADC_STATUS2_STOVF_Pos (25) /*!< EADC_T::STATUS2: STOVF Position */ +#define EADC_STATUS2_STOVF_Msk (0x1ul << EADC_STATUS2_STOVF_Pos) /*!< EADC_T::STATUS2: STOVF Mask */ + +#define EADC_STATUS2_AVALID_Pos (26) /*!< EADC_T::STATUS2: AVALID Position */ +#define EADC_STATUS2_AVALID_Msk (0x1ul << EADC_STATUS2_AVALID_Pos) /*!< EADC_T::STATUS2: AVALID Mask */ + +#define EADC_STATUS2_AOV_Pos (27) /*!< EADC_T::STATUS2: AOV Position */ +#define EADC_STATUS2_AOV_Msk (0x1ul << EADC_STATUS2_AOV_Pos) /*!< EADC_T::STATUS2: AOV Mask */ + +#define EADC_STATUS3_CURSPL_Pos (0) /*!< EADC_T::STATUS3: CURSPL Position */ +#define EADC_STATUS3_CURSPL_Msk (0x1ful << EADC_STATUS3_CURSPL_Pos) /*!< EADC_T::STATUS3: CURSPL Mask */ + +#define EADC_DDAT0_RESULT_Pos (0) /*!< EADC_T::DDAT0: RESULT Position */ +#define EADC_DDAT0_RESULT_Msk (0xfffful << EADC_DDAT0_RESULT_Pos) /*!< EADC_T::DDAT0: RESULT Mask */ + +#define EADC_DDAT0_OV_Pos (16) /*!< EADC_T::DDAT0: OV Position */ +#define EADC_DDAT0_OV_Msk (0x1ul << EADC_DDAT0_OV_Pos) /*!< EADC_T::DDAT0: OV Mask */ + +#define EADC_DDAT0_VALID_Pos (17) /*!< EADC_T::DDAT0: VALID Position */ +#define EADC_DDAT0_VALID_Msk (0x1ul << EADC_DDAT0_VALID_Pos) /*!< EADC_T::DDAT0: VALID Mask */ + +#define EADC_DDAT1_RESULT_Pos (0) /*!< EADC_T::DDAT1: RESULT Position */ +#define EADC_DDAT1_RESULT_Msk (0xfffful << EADC_DDAT1_RESULT_Pos) /*!< EADC_T::DDAT1: RESULT Mask */ + +#define EADC_DDAT1_OV_Pos (16) /*!< EADC_T::DDAT1: OV Position */ +#define EADC_DDAT1_OV_Msk (0x1ul << EADC_DDAT1_OV_Pos) /*!< EADC_T::DDAT1: OV Mask */ + +#define EADC_DDAT1_VALID_Pos (17) /*!< EADC_T::DDAT1: VALID Position */ +#define EADC_DDAT1_VALID_Msk (0x1ul << EADC_DDAT1_VALID_Pos) /*!< EADC_T::DDAT1: VALID Mask */ + +#define EADC_DDAT2_RESULT_Pos (0) /*!< EADC_T::DDAT2: RESULT Position */ +#define EADC_DDAT2_RESULT_Msk (0xfffful << EADC_DDAT2_RESULT_Pos) /*!< EADC_T::DDAT2: RESULT Mask */ + +#define EADC_DDAT2_OV_Pos (16) /*!< EADC_T::DDAT2: OV Position */ +#define EADC_DDAT2_OV_Msk (0x1ul << EADC_DDAT2_OV_Pos) /*!< EADC_T::DDAT2: OV Mask */ + +#define EADC_DDAT2_VALID_Pos (17) /*!< EADC_T::DDAT2: VALID Position */ +#define EADC_DDAT2_VALID_Msk (0x1ul << EADC_DDAT2_VALID_Pos) /*!< EADC_T::DDAT2: VALID Mask */ + +#define EADC_DDAT3_RESULT_Pos (0) /*!< EADC_T::DDAT3: RESULT Position */ +#define EADC_DDAT3_RESULT_Msk (0xfffful << EADC_DDAT3_RESULT_Pos) /*!< EADC_T::DDAT3: RESULT Mask */ + +#define EADC_DDAT3_OV_Pos (16) /*!< EADC_T::DDAT3: OV Position */ +#define EADC_DDAT3_OV_Msk (0x1ul << EADC_DDAT3_OV_Pos) /*!< EADC_T::DDAT3: OV Mask */ + +#define EADC_DDAT3_VALID_Pos (17) /*!< EADC_T::DDAT3: VALID Position */ +#define EADC_DDAT3_VALID_Msk (0x1ul << EADC_DDAT3_VALID_Pos) /*!< EADC_T::DDAT3: VALID Mask */ + +#define EADC_PWRM_PWUPRDY_Pos (0) /*!< EADC_T::PWRM: PWUPRDY Position */ +#define EADC_PWRM_PWUPRDY_Msk (0x1ul << EADC_PWRM_PWUPRDY_Pos) /*!< EADC_T::PWRM: PWUPRDY Mask */ + +#define EADC_PWRM_PWUCALEN_Pos (1) /*!< EADC_T::PWRM: PWUCALEN Position */ +#define EADC_PWRM_PWUCALEN_Msk (0x1ul << EADC_PWRM_PWUCALEN_Pos) /*!< EADC_T::PWRM: PWUCALEN Mask */ + +#define EADC_PWRM_PWDMOD_Pos (2) /*!< EADC_T::PWRM: PWDMOD Position */ +#define EADC_PWRM_PWDMOD_Msk (0x3ul << EADC_PWRM_PWDMOD_Pos) /*!< EADC_T::PWRM: PWDMOD Mask */ + +#define EADC_PWRM_IREFSUT_Pos (8) /*!< EADC_T::PWRM: IREFSUT Position */ +#define EADC_PWRM_IREFSUT_Msk (0xffffful << EADC_PWRM_IREFSUT_Pos) /*!< EADC_T::PWRM: IREFSUT Mask */ + +#define EADC_CALCTL_CALSTART_Pos (1) /*!< EADC_T::CALCTL: CALSTART Position */ +#define EADC_CALCTL_CALSTART_Msk (0x1ul << EADC_CALCTL_CALSTART_Pos) /*!< EADC_T::CALCTL: CALSTART Mask */ + +#define EADC_CALCTL_CALDONE_Pos (2) /*!< EADC_T::CALCTL: CALDONE Position */ +#define EADC_CALCTL_CALDONE_Msk (0x1ul << EADC_CALCTL_CALDONE_Pos) /*!< EADC_T::CALCTL: CALDONE Mask */ + +#define EADC_CALCTL_CALSEL_Pos (3) /*!< EADC_T::CALCTL: CALSEL Position */ +#define EADC_CALCTL_CALSEL_Msk (0x1ul << EADC_CALCTL_CALSEL_Pos) /*!< EADC_T::CALCTL: CALSEL Mask */ + +#define EADC_PDMACTL_PDMATEN_Pos (0) /*!< EADC_T::PDMACTL: PDMATEN Position */ +#define EADC_PDMACTL_PDMATEN_Msk (0x1fful << EADC_PDMACTL_PDMATEN_Pos) /*!< EADC_T::PDMACTL: PDMATEN Mask */ + +#define EADC_PDMACTL_PDMABUSY_Pos (31) /*!< EADC_T::PDMACTL: PDMABUSY Position */ +#define EADC_PDMACTL_PDMABUSY_Msk (0x1ul << EADC_PDMACTL_PDMABUSY_Pos) /*!< EADC_T::PDMACTL: PDMABUSY Mask */ + +#define EADC_SELSMP0_SELSMP0_Pos (0) /*!< EADC_T::SELSMP0: SELSMP0 Position */ +#define EADC_SELSMP0_SELSMP0_Msk (0x3ul << EADC_SELSMP0_SELSMP0_Pos) /*!< EADC_T::SELSMP0: SELSMP0 Mask */ + +#define EADC_SELSMP0_SELSMP1_Pos (4) /*!< EADC_T::SELSMP0: SELSMP1 Position */ +#define EADC_SELSMP0_SELSMP1_Msk (0x3ul << EADC_SELSMP0_SELSMP1_Pos) /*!< EADC_T::SELSMP0: SELSMP1 Mask */ + +#define EADC_SELSMP0_SELSMP2_Pos (8) /*!< EADC_T::SELSMP0: SELSMP2 Position */ +#define EADC_SELSMP0_SELSMP2_Msk (0x3ul << EADC_SELSMP0_SELSMP2_Pos) /*!< EADC_T::SELSMP0: SELSMP2 Mask */ + +#define EADC_SELSMP0_SELSMP3_Pos (12) /*!< EADC_T::SELSMP0: SELSMP3 Position */ +#define EADC_SELSMP0_SELSMP3_Msk (0x3ul << EADC_SELSMP0_SELSMP3_Pos) /*!< EADC_T::SELSMP0: SELSMP3 Mask */ + +#define EADC_SELSMP0_SELSMP4_Pos (16) /*!< EADC_T::SELSMP0: SELSMP4 Position */ +#define EADC_SELSMP0_SELSMP4_Msk (0x3ul << EADC_SELSMP0_SELSMP4_Pos) /*!< EADC_T::SELSMP0: SELSMP4 Mask */ + +#define EADC_SELSMP0_SELSMP5_Pos (20) /*!< EADC_T::SELSMP0: SELSMP5 Position */ +#define EADC_SELSMP0_SELSMP5_Msk (0x3ul << EADC_SELSMP0_SELSMP5_Pos) /*!< EADC_T::SELSMP0: SELSMP5 Mask */ + +#define EADC_SELSMP0_SELSMP6_Pos (24) /*!< EADC_T::SELSMP0: SELSMP6 Position */ +#define EADC_SELSMP0_SELSMP6_Msk (0x3ul << EADC_SELSMP0_SELSMP6_Pos) /*!< EADC_T::SELSMP0: SELSMP6 Mask */ + +#define EADC_SELSMP0_SELSMP7_Pos (28) /*!< EADC_T::SELSMP0: SELSMP7 Position */ +#define EADC_SELSMP0_SELSMP7_Msk (0x3ul << EADC_SELSMP0_SELSMP7_Pos) /*!< EADC_T::SELSMP0: SELSMP7 Mask */ + +#define EADC_SELSMP1_SELSMP8_Pos (0) /*!< EADC_T::SELSMP1: SELSMP8 Position */ +#define EADC_SELSMP1_SELSMP8_Msk (0x3ul << EADC_SELSMP1_SELSMP8_Pos) /*!< EADC_T::SELSMP1: SELSMP8 Mask */ + +#define EADC_REFADJCTL_PDREF_Pos (0) /*!< EADC_T::REFADJCTL: PDREF Position */ +#define EADC_REFADJCTL_PDREF_Msk (0x1ul << EADC_REFADJCTL_PDREF_Pos) /*!< EADC_T::REFADJCTL: PDREF Mask */ + +#define EADC_REFADJCTL_REFADJ_Pos (1) /*!< EADC_T::REFADJCTL: REFADJ Position */ +#define EADC_REFADJCTL_REFADJ_Msk (0xful << EADC_REFADJCTL_REFADJ_Pos) /*!< EADC_T::REFADJCTL: REFADJ Mask */ + +/**@}*/ /* EADC_CONST */ +/**@}*/ /* end of EADC register group */ +/**@}*/ /* end of REGISTER group */ + +#if defined ( __CC_ARM ) + #pragma no_anon_unions +#endif + +#endif /* __EADC_REG_H__ */ diff --git a/bsp/nuvoton/libraries/ma35/Device/Nuvoton/MA35D1/Include/ebi_reg.h b/bsp/nuvoton/libraries/ma35/Device/Nuvoton/MA35D1/Include/ebi_reg.h new file mode 100644 index 0000000000..f56049f135 --- /dev/null +++ b/bsp/nuvoton/libraries/ma35/Device/Nuvoton/MA35D1/Include/ebi_reg.h @@ -0,0 +1,428 @@ +/**************************************************************************//** + * @file ebi_reg.h + * @brief EBI register definition header file + * + * SPDX-License-Identifier: Apache-2.0 + * @copyright (C) 2020 Nuvoton Technology Corp. All rights reserved. + *****************************************************************************/ +#ifndef __EBI_REG_H__ +#define __EBI_REG_H__ + +#if defined ( __CC_ARM ) + #pragma anon_unions +#endif + +/** + @addtogroup REGISTER Control Register + @{ +*/ + +/** + @addtogroup EBI External Bus Interface Controller(EBI) + Memory Mapped Structure for EBI Controller +@{ */ + +typedef struct +{ + + + /** + * @var EBI_T::CTL0 + * Offset: 0x00 External Bus Interface Bank0 Control Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[0] |EN |EBI Enable Bit + * | | |This bit is the functional enable bit for EBI. + * | | |0 = EBI function Disabled. + * | | |1 = EBI function Enabled. + * |[1] |DW16 |EBI Data Width 16-bit Select + * | | |This bit defines if the EBI data width is 8-bit or 16-bit. + * | | |0 = EBI data width is 8-bit. + * | | |1 = EBI data width is 16-bit. + * |[2] |CSPOLINV |Chip Select Pin Polar Inverse + * | | |This bit defines the active level of EBI chip select pin (EBI_nCS). + * | | |0 = Chip select pin (EBI_nCS) is active low. + * | | |1 = Chip select pin (EBI_nCS) is active high. + * |[3] |ADSEPEN |EBI Address/Data Bus Separate Mode Enable Bit + * | | |0 = Address/Data Bus Separate Mode Disabled. + * | | |1 = Address/Data Bus Separate Mode Enabled. + * |[4] |CACCESS |Continuous Data Access Mode + * | | |When continuous access mode enabled, the tASU, tALE and tLHD cycles are bypass for continuous data transfer request. + * | | |0 = Continuous data access mode Disabled. + * | | |1 = Continuous data access mode Enabled. + * |[10:8] |MCLKDIV |External Output Clock Divider + * | | |The frequency of EBI output clock (MCLK) is controlled by MCLKDIV as follow: + * | | |000 = HCLK/1. + * | | |001 = HCLK/2. + * | | |010 = HCLK/4. + * | | |011 = HCLK/8. + * | | |100 = HCLK/16. + * | | |101 = HCLK/32. + * | | |110 = HCLK/64. + * | | |111 = HCLK/128. + * |[18:16] |TALE |Extend Time of ALE + * | | |The EBI_ALE high pulse period (tALE) to latch the address can be controlled by TALE. + * | | |tALE = (TALE+1)*EBI_MCLK. + * | | |Note: This field only available in EBI_CTL0 register. + * |[24] |WBUFEN |EBI Write Buffer Enable Bit + * | | |0 = EBI write buffer Disabled. + * | | |1 = EBI write buffer Enabled. + * | | |Note: This bit only available in EBI_CTL0 register. + * @var EBI_T::TCTL0 + * Offset: 0x04 External Bus Interface Bank0 Timing Control Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[7:3] |TACC |EBI Data Access Time + * | | |TACC defines data access time (tACC). + * | | |tACC = (TACC +1) * EBI_MCLK. + * |[10:8] |TAHD |EBI Data Access Hold Time + * | | |TAHD defines data access hold time (tAHD). + * | | |tAHD = (TAHD +1) * EBI_MCLK. + * |[15:12] |W2X |Idle Cycle After Write + * | | |This field defines the number of W2X idle cycle. + * | | |W2X idle cycle = (W2X * EBI_MCLK). + * | | |When write action is finished, W2X idle cycle is inserted and EBI_nCS return to idle state. + * |[22] |RAHDOFF |Access Hold Time Disable Control When Read + * | | |0 = Data Access Hold Time (tAHD) during EBI reading Enabled. + * | | |1 = Data Access Hold Time (tAHD) during EBI reading Disabled. + * |[23] |WAHDOFF |Access Hold Time Disable Control When Write + * | | |0 = Data Access Hold Time (tAHD) during EBI writing Enabled. + * | | |1 = Data Access Hold Time (tAHD) during EBI writing Disabled. + * |[27:24] |R2R |Idle Cycle Between Read-to-read + * | | |This field defines the number of R2R idle cycle. + * | | |R2R idle cycle = (R2R * EBI_MCLK). + * | | |When read action is finished and the next action is going to read, R2R idle cycle is inserted and EBI_nCS return to idle state. + * @var EBI_T::CTL1 + * Offset: 0x10 External Bus Interface Bank1 Control Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[0] |EN |EBI Enable Bit + * | | |This bit is the functional enable bit for EBI. + * | | |0 = EBI function Disabled. + * | | |1 = EBI function Enabled. + * |[1] |DW16 |EBI Data Width 16-bit Select + * | | |This bit defines if the EBI data width is 8-bit or 16-bit. + * | | |0 = EBI data width is 8-bit. + * | | |1 = EBI data width is 16-bit. + * |[2] |CSPOLINV |Chip Select Pin Polar Inverse + * | | |This bit defines the active level of EBI chip select pin (EBI_nCS). + * | | |0 = Chip select pin (EBI_nCS) is active low. + * | | |1 = Chip select pin (EBI_nCS) is active high. + * |[3] |ADSEPEN |EBI Address/Data Bus Separate Mode Enable Bit + * | | |0 = Address/Data Bus Separate Mode Disabled. + * | | |1 = Address/Data Bus Separate Mode Enabled. + * |[4] |CACCESS |Continuous Data Access Mode + * | | |When continuous access mode enabled, the tASU, tALE and tLHD cycles are bypass for continuous data transfer request. + * | | |0 = Continuous data access mode Disabled. + * | | |1 = Continuous data access mode Enabled. + * |[10:8] |MCLKDIV |External Output Clock Divider + * | | |The frequency of EBI output clock (MCLK) is controlled by MCLKDIV as follow: + * | | |000 = HCLK/1. + * | | |001 = HCLK/2. + * | | |010 = HCLK/4. + * | | |011 = HCLK/8. + * | | |100 = HCLK/16. + * | | |101 = HCLK/32. + * | | |110 = HCLK/64. + * | | |111 = HCLK/128. + * |[18:16] |TALE |Extend Time of ALE + * | | |The EBI_ALE high pulse period (tALE) to latch the address can be controlled by TALE. + * | | |tALE = (TALE+1)*EBI_MCLK. + * | | |Note: This field only available in EBI_CTL0 register. + * |[24] |WBUFEN |EBI Write Buffer Enable Bit + * | | |0 = EBI write buffer Disabled. + * | | |1 = EBI write buffer Enabled. + * | | |Note: This bit only available in EBI_CTL0 register. + * @var EBI_T::TCTL1 + * Offset: 0x14 External Bus Interface Bank1 Timing Control Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[7:3] |TACC |EBI Data Access Time + * | | |TACC defines data access time (tACC). + * | | |tACC = (TACC +1) * EBI_MCLK. + * |[10:8] |TAHD |EBI Data Access Hold Time + * | | |TAHD defines data access hold time (tAHD). + * | | |tAHD = (TAHD +1) * EBI_MCLK. + * |[15:12] |W2X |Idle Cycle After Write + * | | |This field defines the number of W2X idle cycle. + * | | |W2X idle cycle = (W2X * EBI_MCLK). + * | | |When write action is finished, W2X idle cycle is inserted and EBI_nCS return to idle state. + * |[22] |RAHDOFF |Access Hold Time Disable Control When Read + * | | |0 = Data Access Hold Time (tAHD) during EBI reading Enabled. + * | | |1 = Data Access Hold Time (tAHD) during EBI reading Disabled. + * |[23] |WAHDOFF |Access Hold Time Disable Control When Write + * | | |0 = Data Access Hold Time (tAHD) during EBI writing Enabled. + * | | |1 = Data Access Hold Time (tAHD) during EBI writing Disabled. + * |[27:24] |R2R |Idle Cycle Between Read-to-read + * | | |This field defines the number of R2R idle cycle. + * | | |R2R idle cycle = (R2R * EBI_MCLK). + * | | |When read action is finished and the next action is going to read, R2R idle cycle is inserted and EBI_nCS return to idle state. + * @var EBI_T::CTL2 + * Offset: 0x20 External Bus Interface Bank2 Control Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[0] |EN |EBI Enable Bit + * | | |This bit is the functional enable bit for EBI. + * | | |0 = EBI function Disabled. + * | | |1 = EBI function Enabled. + * |[1] |DW16 |EBI Data Width 16-bit Select + * | | |This bit defines if the EBI data width is 8-bit or 16-bit. + * | | |0 = EBI data width is 8-bit. + * | | |1 = EBI data width is 16-bit. + * |[2] |CSPOLINV |Chip Select Pin Polar Inverse + * | | |This bit defines the active level of EBI chip select pin (EBI_nCS). + * | | |0 = Chip select pin (EBI_nCS) is active low. + * | | |1 = Chip select pin (EBI_nCS) is active high. + * |[3] |ADSEPEN |EBI Address/Data Bus Separate Mode Enable Bit + * | | |0 = Address/Data Bus Separate Mode Disabled. + * | | |1 = Address/Data Bus Separate Mode Enabled. + * |[4] |CACCESS |Continuous Data Access Mode + * | | |When continuous access mode enabled, the tASU, tALE and tLHD cycles are bypass for continuous data transfer request. + * | | |0 = Continuous data access mode Disabled. + * | | |1 = Continuous data access mode Enabled. + * |[10:8] |MCLKDIV |External Output Clock Divider + * | | |The frequency of EBI output clock (MCLK) is controlled by MCLKDIV as follow: + * | | |000 = HCLK/1. + * | | |001 = HCLK/2. + * | | |010 = HCLK/4. + * | | |011 = HCLK/8. + * | | |100 = HCLK/16. + * | | |101 = HCLK/32. + * | | |110 = HCLK/64. + * | | |111 = HCLK/128. + * |[18:16] |TALE |Extend Time of ALE + * | | |The EBI_ALE high pulse period (tALE) to latch the address can be controlled by TALE. + * | | |tALE = (TALE+1)*EBI_MCLK. + * | | |Note: This field only available in EBI_CTL0 register. + * |[24] |WBUFEN |EBI Write Buffer Enable Bit + * | | |0 = EBI write buffer Disabled. + * | | |1 = EBI write buffer Enabled. + * | | |Note: This bit only available in EBI_CTL0 register. + * @var EBI_T::TCTL2 + * Offset: 0x24 External Bus Interface Bank2 Timing Control Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[7:3] |TACC |EBI Data Access Time + * | | |TACC defines data access time (tACC). + * | | |tACC = (TACC +1) * EBI_MCLK. + * |[10:8] |TAHD |EBI Data Access Hold Time + * | | |TAHD defines data access hold time (tAHD). + * | | |tAHD = (TAHD +1) * EBI_MCLK. + * |[15:12] |W2X |Idle Cycle After Write + * | | |This field defines the number of W2X idle cycle. + * | | |W2X idle cycle = (W2X * EBI_MCLK). + * | | |When write action is finished, W2X idle cycle is inserted and EBI_nCS return to idle state. + * |[22] |RAHDOFF |Access Hold Time Disable Control When Read + * | | |0 = Data Access Hold Time (tAHD) during EBI reading Enabled. + * | | |1 = Data Access Hold Time (tAHD) during EBI reading Disabled. + * |[23] |WAHDOFF |Access Hold Time Disable Control When Write + * | | |0 = Data Access Hold Time (tAHD) during EBI writing Enabled. + * | | |1 = Data Access Hold Time (tAHD) during EBI writing Disabled. + * |[27:24] |R2R |Idle Cycle Between Read-to-read + * | | |This field defines the number of R2R idle cycle. + * | | |R2R idle cycle = (R2R * EBI_MCLK). + * | | |When read action is finished and the next action is going to read, R2R idle cycle is inserted and EBI_nCS return to idle state. + */ + __IO uint32_t CTL0; /*!< [0x0000] External Bus Interface Bank0 Control Register */ + __IO uint32_t TCTL0; /*!< [0x0004] External Bus Interface Bank0 Timing Control Register */ + /// @cond HIDDEN_SYMBOLS + __I uint32_t RESERVE0[2]; + /// @endcond //HIDDEN_SYMBOLS + __IO uint32_t CTL1; /*!< [0x0010] External Bus Interface Bank1 Control Register */ + __IO uint32_t TCTL1; /*!< [0x0014] External Bus Interface Bank1 Timing Control Register */ + /// @cond HIDDEN_SYMBOLS + __I uint32_t RESERVE1[2]; + /// @endcond //HIDDEN_SYMBOLS + __IO uint32_t CTL2; /*!< [0x0020] External Bus Interface Bank2 Control Register */ + __IO uint32_t TCTL2; /*!< [0x0024] External Bus Interface Bank2 Timing Control Register */ + +} EBI_T; + +/** + @addtogroup EBI_CONST EBI Bit Field Definition + Constant Definitions for EBI Controller +@{ */ + +#define EBI_CTL_EN_Pos (0) /*!< EBI_T::CTL: EN Position */ +#define EBI_CTL_EN_Msk (0x1ul << EBI_CTL_EN_Pos) /*!< EBI_T::CTL: EN Mask */ + +#define EBI_CTL_DW16_Pos (1) /*!< EBI_T::CTL: DW16 Position */ +#define EBI_CTL_DW16_Msk (0x1ul << EBI_CTL_DW16_Pos) /*!< EBI_T::CTL: DW16 Mask */ + +#define EBI_CTL_CSPOLINV_Pos (2) /*!< EBI_T::CTL: CSPOLINV Position */ +#define EBI_CTL_CSPOLINV_Msk (0x1ul << EBI_CTL_CSPOLINV_Pos) /*!< EBI_T::CTL: CSPOLINV Mask */ + +#define EBI_CTL_ADSEPEN_Pos (3) /*!< EBI_T::CTL: ADSEPEN Position */ +#define EBI_CTL_ADSEPEN_Msk (0x1ul << EBI_CTL_ADSEPEN_Pos) /*!< EBI_T::CTL: ADSEPEN Mask */ + +#define EBI_CTL_CACCESS_Pos (4) /*!< EBI_T::CTL: CACCESS Position */ +#define EBI_CTL_CACCESS_Msk (0x1ul << EBI_CTL_CACCESS_Pos) /*!< EBI_T::CTL: CACCESS Mask */ + +#define EBI_CTL_MCLKDIV_Pos (8) /*!< EBI_T::CTL: MCLKDIV Position */ +#define EBI_CTL_MCLKDIV_Msk (0x7ul << EBI_CTL_MCLKDIV_Pos) /*!< EBI_T::CTL: MCLKDIV Mask */ + +#define EBI_CTL_TALE_Pos (16) /*!< EBI_T::CTL: TALE Position */ +#define EBI_CTL_TALE_Msk (0x7ul << EBI_CTL_TALE_Pos) /*!< EBI_T::CTL: TALE Mask */ + +#define EBI_CTL_WBUFEN_Pos (24) /*!< EBI_T::CTL: WBUFEN Position */ +#define EBI_CTL_WBUFEN_Msk (0x1ul << EBI_CTL_WBUFEN_Pos) /*!< EBI_T::CTL: WBUFEN Mask */ + +#define EBI_TCTL_TACC_Pos (3) /*!< EBI_T::TCTL: TACC Position */ +#define EBI_TCTL_TACC_Msk (0x1ful << EBI_TCTL_TACC_Pos) /*!< EBI_T::TCTL: TACC Mask */ + +#define EBI_TCTL_TAHD_Pos (8) /*!< EBI_T::TCTL: TAHD Position */ +#define EBI_TCTL_TAHD_Msk (0x7ul << EBI_TCTL_TAHD_Pos) /*!< EBI_T::TCTL: TAHD Mask */ + +#define EBI_TCTL_W2X_Pos (12) /*!< EBI_T::TCTL: W2X Position */ +#define EBI_TCTL_W2X_Msk (0xful << EBI_TCTL_W2X_Pos) /*!< EBI_T::TCTL: W2X Mask */ + +#define EBI_TCTL_RAHDOFF_Pos (22) /*!< EBI_T::TCTL: RAHDOFF Position */ +#define EBI_TCTL_RAHDOFF_Msk (0x1ul << EBI_TCTL_RAHDOFF_Pos) /*!< EBI_T::TCTL: RAHDOFF Mask */ + +#define EBI_TCTL_WAHDOFF_Pos (23) /*!< EBI_T::TCTL: WAHDOFF Position */ +#define EBI_TCTL_WAHDOFF_Msk (0x1ul << EBI_TCTL_WAHDOFF_Pos) /*!< EBI_T::TCTL: WAHDOFF Mask */ + +#define EBI_TCTL_R2R_Pos (24) /*!< EBI_T::TCTL: R2R Position */ +#define EBI_TCTL_R2R_Msk (0xful << EBI_TCTL_R2R_Pos) /*!< EBI_T::TCTL: R2R Mask */ + +#define EBI_CTL0_EN_Pos (0) /*!< EBI_T::CTL0: EN Position */ +#define EBI_CTL0_EN_Msk (0x1ul << EBI_CTL0_EN_Pos) /*!< EBI_T::CTL0: EN Mask */ + +#define EBI_CTL0_DW16_Pos (1) /*!< EBI_T::CTL0: DW16 Position */ +#define EBI_CTL0_DW16_Msk (0x1ul << EBI_CTL0_DW16_Pos) /*!< EBI_T::CTL0: DW16 Mask */ + +#define EBI_CTL0_CSPOLINV_Pos (2) /*!< EBI_T::CTL0: CSPOLINV Position */ +#define EBI_CTL0_CSPOLINV_Msk (0x1ul << EBI_CTL0_CSPOLINV_Pos) /*!< EBI_T::CTL0: CSPOLINV Mask */ + +#define EBI_CTL0_ADSEPEN_Pos (3) /*!< EBI_T::CTL0: ADSEPEN Position */ +#define EBI_CTL0_ADSEPEN_Msk (0x1ul << EBI_CTL0_ADSEPEN_Pos) /*!< EBI_T::CTL0: ADSEPEN Mask */ + +#define EBI_CTL0_CACCESS_Pos (4) /*!< EBI_T::CTL0: CACCESS Position */ +#define EBI_CTL0_CACCESS_Msk (0x1ul << EBI_CTL0_CACCESS_Pos) /*!< EBI_T::CTL0: CACCESS Mask */ + +#define EBI_CTL0_MCLKDIV_Pos (8) /*!< EBI_T::CTL0: MCLKDIV Position */ +#define EBI_CTL0_MCLKDIV_Msk (0x7ul << EBI_CTL0_MCLKDIV_Pos) /*!< EBI_T::CTL0: MCLKDIV Mask */ + +#define EBI_CTL0_TALE_Pos (16) /*!< EBI_T::CTL0: TALE Position */ +#define EBI_CTL0_TALE_Msk (0x7ul << EBI_CTL0_TALE_Pos) /*!< EBI_T::CTL0: TALE Mask */ + +#define EBI_CTL0_WBUFEN_Pos (24) /*!< EBI_T::CTL0: WBUFEN Position */ +#define EBI_CTL0_WBUFEN_Msk (0x1ul << EBI_CTL0_WBUFEN_Pos) /*!< EBI_T::CTL0: WBUFEN Mask */ + +#define EBI_TCTL0_TACC_Pos (3) /*!< EBI_T::TCTL0: TACC Position */ +#define EBI_TCTL0_TACC_Msk (0x1ful << EBI_TCTL0_TACC_Pos) /*!< EBI_T::TCTL0: TACC Mask */ + +#define EBI_TCTL0_TAHD_Pos (8) /*!< EBI_T::TCTL0: TAHD Position */ +#define EBI_TCTL0_TAHD_Msk (0x7ul << EBI_TCTL0_TAHD_Pos) /*!< EBI_T::TCTL0: TAHD Mask */ + +#define EBI_TCTL0_W2X_Pos (12) /*!< EBI_T::TCTL0: W2X Position */ +#define EBI_TCTL0_W2X_Msk (0xful << EBI_TCTL0_W2X_Pos) /*!< EBI_T::TCTL0: W2X Mask */ + +#define EBI_TCTL0_RAHDOFF_Pos (22) /*!< EBI_T::TCTL0: RAHDOFF Position */ +#define EBI_TCTL0_RAHDOFF_Msk (0x1ul << EBI_TCTL0_RAHDOFF_Pos) /*!< EBI_T::TCTL0: RAHDOFF Mask */ + +#define EBI_TCTL0_WAHDOFF_Pos (23) /*!< EBI_T::TCTL0: WAHDOFF Position */ +#define EBI_TCTL0_WAHDOFF_Msk (0x1ul << EBI_TCTL0_WAHDOFF_Pos) /*!< EBI_T::TCTL0: WAHDOFF Mask */ + +#define EBI_TCTL0_R2R_Pos (24) /*!< EBI_T::TCTL0: R2R Position */ +#define EBI_TCTL0_R2R_Msk (0xful << EBI_TCTL0_R2R_Pos) /*!< EBI_T::TCTL0: R2R Mask */ + +#define EBI_CTL1_EN_Pos (0) /*!< EBI_T::CTL1: EN Position */ +#define EBI_CTL1_EN_Msk (0x1ul << EBI_CTL1_EN_Pos) /*!< EBI_T::CTL1: EN Mask */ + +#define EBI_CTL1_DW16_Pos (1) /*!< EBI_T::CTL1: DW16 Position */ +#define EBI_CTL1_DW16_Msk (0x1ul << EBI_CTL1_DW16_Pos) /*!< EBI_T::CTL1: DW16 Mask */ + +#define EBI_CTL1_CSPOLINV_Pos (2) /*!< EBI_T::CTL1: CSPOLINV Position */ +#define EBI_CTL1_CSPOLINV_Msk (0x1ul << EBI_CTL1_CSPOLINV_Pos) /*!< EBI_T::CTL1: CSPOLINV Mask */ + +#define EBI_CTL1_ADSEPEN_Pos (3) /*!< EBI_T::CTL1: ADSEPEN Position */ +#define EBI_CTL1_ADSEPEN_Msk (0x1ul << EBI_CTL1_ADSEPEN_Pos) /*!< EBI_T::CTL1: ADSEPEN Mask */ + +#define EBI_CTL1_CACCESS_Pos (4) /*!< EBI_T::CTL1: CACCESS Position */ +#define EBI_CTL1_CACCESS_Msk (0x1ul << EBI_CTL1_CACCESS_Pos) /*!< EBI_T::CTL1: CACCESS Mask */ + +#define EBI_CTL1_MCLKDIV_Pos (8) /*!< EBI_T::CTL1: MCLKDIV Position */ +#define EBI_CTL1_MCLKDIV_Msk (0x7ul << EBI_CTL1_MCLKDIV_Pos) /*!< EBI_T::CTL1: MCLKDIV Mask */ + +#define EBI_CTL1_TALE_Pos (16) /*!< EBI_T::CTL1: TALE Position */ +#define EBI_CTL1_TALE_Msk (0x7ul << EBI_CTL1_TALE_Pos) /*!< EBI_T::CTL1: TALE Mask */ + +#define EBI_CTL1_WBUFEN_Pos (24) /*!< EBI_T::CTL1: WBUFEN Position */ +#define EBI_CTL1_WBUFEN_Msk (0x1ul << EBI_CTL1_WBUFEN_Pos) /*!< EBI_T::CTL1: WBUFEN Mask */ + +#define EBI_TCTL1_TACC_Pos (3) /*!< EBI_T::TCTL1: TACC Position */ +#define EBI_TCTL1_TACC_Msk (0x1ful << EBI_TCTL1_TACC_Pos) /*!< EBI_T::TCTL1: TACC Mask */ + +#define EBI_TCTL1_TAHD_Pos (8) /*!< EBI_T::TCTL1: TAHD Position */ +#define EBI_TCTL1_TAHD_Msk (0x7ul << EBI_TCTL1_TAHD_Pos) /*!< EBI_T::TCTL1: TAHD Mask */ + +#define EBI_TCTL1_W2X_Pos (12) /*!< EBI_T::TCTL1: W2X Position */ +#define EBI_TCTL1_W2X_Msk (0xful << EBI_TCTL1_W2X_Pos) /*!< EBI_T::TCTL1: W2X Mask */ + +#define EBI_TCTL1_RAHDOFF_Pos (22) /*!< EBI_T::TCTL1: RAHDOFF Position */ +#define EBI_TCTL1_RAHDOFF_Msk (0x1ul << EBI_TCTL1_RAHDOFF_Pos) /*!< EBI_T::TCTL1: RAHDOFF Mask */ + +#define EBI_TCTL1_WAHDOFF_Pos (23) /*!< EBI_T::TCTL1: WAHDOFF Position */ +#define EBI_TCTL1_WAHDOFF_Msk (0x1ul << EBI_TCTL1_WAHDOFF_Pos) /*!< EBI_T::TCTL1: WAHDOFF Mask */ + +#define EBI_TCTL1_R2R_Pos (24) /*!< EBI_T::TCTL1: R2R Position */ +#define EBI_TCTL1_R2R_Msk (0xful << EBI_TCTL1_R2R_Pos) /*!< EBI_T::TCTL1: R2R Mask */ + +#define EBI_CTL2_EN_Pos (0) /*!< EBI_T::CTL2: EN Position */ +#define EBI_CTL2_EN_Msk (0x1ul << EBI_CTL2_EN_Pos) /*!< EBI_T::CTL2: EN Mask */ + +#define EBI_CTL2_DW16_Pos (1) /*!< EBI_T::CTL2: DW16 Position */ +#define EBI_CTL2_DW16_Msk (0x1ul << EBI_CTL2_DW16_Pos) /*!< EBI_T::CTL2: DW16 Mask */ + +#define EBI_CTL2_CSPOLINV_Pos (2) /*!< EBI_T::CTL2: CSPOLINV Position */ +#define EBI_CTL2_CSPOLINV_Msk (0x1ul << EBI_CTL2_CSPOLINV_Pos) /*!< EBI_T::CTL2: CSPOLINV Mask */ + +#define EBI_CTL2_ADSEPEN_Pos (3) /*!< EBI_T::CTL2: ADSEPEN Position */ +#define EBI_CTL2_ADSEPEN_Msk (0x1ul << EBI_CTL2_ADSEPEN_Pos) /*!< EBI_T::CTL2: ADSEPEN Mask */ + +#define EBI_CTL2_CACCESS_Pos (4) /*!< EBI_T::CTL2: CACCESS Position */ +#define EBI_CTL2_CACCESS_Msk (0x1ul << EBI_CTL2_CACCESS_Pos) /*!< EBI_T::CTL2: CACCESS Mask */ + +#define EBI_CTL2_MCLKDIV_Pos (8) /*!< EBI_T::CTL2: MCLKDIV Position */ +#define EBI_CTL2_MCLKDIV_Msk (0x7ul << EBI_CTL2_MCLKDIV_Pos) /*!< EBI_T::CTL2: MCLKDIV Mask */ + +#define EBI_CTL2_TALE_Pos (16) /*!< EBI_T::CTL2: TALE Position */ +#define EBI_CTL2_TALE_Msk (0x7ul << EBI_CTL2_TALE_Pos) /*!< EBI_T::CTL2: TALE Mask */ + +#define EBI_CTL2_WBUFEN_Pos (24) /*!< EBI_T::CTL2: WBUFEN Position */ +#define EBI_CTL2_WBUFEN_Msk (0x1ul << EBI_CTL2_WBUFEN_Pos) /*!< EBI_T::CTL2: WBUFEN Mask */ + +#define EBI_TCTL2_TACC_Pos (3) /*!< EBI_T::TCTL2: TACC Position */ +#define EBI_TCTL2_TACC_Msk (0x1ful << EBI_TCTL2_TACC_Pos) /*!< EBI_T::TCTL2: TACC Mask */ + +#define EBI_TCTL2_TAHD_Pos (8) /*!< EBI_T::TCTL2: TAHD Position */ +#define EBI_TCTL2_TAHD_Msk (0x7ul << EBI_TCTL2_TAHD_Pos) /*!< EBI_T::TCTL2: TAHD Mask */ + +#define EBI_TCTL2_W2X_Pos (12) /*!< EBI_T::TCTL2: W2X Position */ +#define EBI_TCTL2_W2X_Msk (0xful << EBI_TCTL2_W2X_Pos) /*!< EBI_T::TCTL2: W2X Mask */ + +#define EBI_TCTL2_RAHDOFF_Pos (22) /*!< EBI_T::TCTL2: RAHDOFF Position */ +#define EBI_TCTL2_RAHDOFF_Msk (0x1ul << EBI_TCTL2_RAHDOFF_Pos) /*!< EBI_T::TCTL2: RAHDOFF Mask */ + +#define EBI_TCTL2_WAHDOFF_Pos (23) /*!< EBI_T::TCTL2: WAHDOFF Position */ +#define EBI_TCTL2_WAHDOFF_Msk (0x1ul << EBI_TCTL2_WAHDOFF_Pos) /*!< EBI_T::TCTL2: WAHDOFF Mask */ + +#define EBI_TCTL2_R2R_Pos (24) /*!< EBI_T::TCTL2: R2R Position */ +#define EBI_TCTL2_R2R_Msk (0xful << EBI_TCTL2_R2R_Pos) /*!< EBI_T::TCTL2: R2R Mask */ + +/**@}*/ /* EBI_CONST */ +/**@}*/ /* end of EBI register group */ +/**@}*/ /* end of REGISTER group */ + +#if defined ( __CC_ARM ) + #pragma no_anon_unions +#endif + +#endif /* __EBI_REG_H__ */ diff --git a/bsp/nuvoton/libraries/ma35/Device/Nuvoton/MA35D1/Include/ecap_reg.h b/bsp/nuvoton/libraries/ma35/Device/Nuvoton/MA35D1/Include/ecap_reg.h new file mode 100644 index 0000000000..6584e6f556 --- /dev/null +++ b/bsp/nuvoton/libraries/ma35/Device/Nuvoton/MA35D1/Include/ecap_reg.h @@ -0,0 +1,389 @@ +/**************************************************************************//** + * @file ecap_reg.h + * @brief ECAP register definition header file + * + * SPDX-License-Identifier: Apache-2.0 + * @copyright (C) 2020 Nuvoton Technology Corp. All rights reserved. + *****************************************************************************/ +#ifndef __ECAP_REG_H__ +#define __ECAP_REG_H__ + +#if defined ( __CC_ARM ) + #pragma anon_unions +#endif + +/** + @addtogroup REGISTER Control Register + @{ +*/ + +/** + @addtogroup ECAP Enhanced Input Capture Timer(ECAP) + Memory Mapped Structure for ECAP Controller +@{ */ + +typedef struct +{ + + /** + * @var ECAP_T::CNT + * Offset: 0x00 Input Capture Counter (24-bit up counter) + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[23:0] |CNT |Input Capture Timer/Counter + * | | |The input Capture Timer/Counter is a 24-bit up-counting counter + * | | |The clock source for the counter is from the clock divider + * @var ECAP_T::HLD0 + * Offset: 0x04 Input Capture Hold Register 0 + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[23:0] |HOLD |Input Capture Counter Hold Register + * | | |When an active input capture channel detects a valid edge signal change, the ECAPCNT value is latched into the corresponding holding register + * | | |Each input channel has its own holding register named by ECAP_HLDx where x is from 0 to 2 to indicate inputs from IC0 to IC2, respectively. + * @var ECAP_T::HLD1 + * Offset: 0x08 Input Capture Hold Register 1 + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[23:0] |HOLD |Input Capture Counter Hold Register + * | | |When an active input capture channel detects a valid edge signal change, the ECAPCNT value is latched into the corresponding holding register + * | | |Each input channel has its own holding register named by ECAP_HLDx where x is from 0 to 2 to indicate inputs from IC0 to IC2, respectively. + * @var ECAP_T::HLD2 + * Offset: 0x0C Input Capture Hold Register 2 + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[23:0] |HOLD |Input Capture Counter Hold Register + * | | |When an active input capture channel detects a valid edge signal change, the ECAPCNT value is latched into the corresponding holding register + * | | |Each input channel has its own holding register named by ECAP_HLDx where x is from 0 to 2 to indicate inputs from IC0 to IC2, respectively. + * @var ECAP_T::CNTCMP + * Offset: 0x10 Input Capture Compare Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[23:0] |CNTCMP |Input Capture Counter Compare Register + * | | |If the compare function is enabled (CMPEN = 1), this register (ECAP_CNTCMP) is used to compare with the capture counter (ECAP_CNT). + * | | |If the reload control is enabled (RLDEN[n] = 1, n=0~3), an overflow event or capture events will trigger the hardware to load the value of this register (ECAP_CNTCMP) into ECAP_CNT. + * @var ECAP_T::CTL0 + * Offset: 0x14 Input Capture Control Register 0 + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[2:0] |NFCLKSEL |Noise Filter Clock Pre-divide Selection + * | | |To determine the sampling frequency of the Noise Filter clock + * | | |000 = CAP_CLK. + * | | |001 = CAP_CLK/2. + * | | |010 = CAP_CLK/4. + * | | |011 = CAP_CLK/16. + * | | |100 = CAP_CLK/32. + * | | |101 = CAP_CLK/64. + * |[3] |CAPNFDIS |Input Capture Noise Filter Disable Control + * | | |0 = Noise filter of Input Capture Enabled. + * | | |1 = Noise filter of Input Capture Disabled (Bypass). + * |[4] |IC0EN |Port Pin IC0 Input to Input Capture Unit Enable Control + * | | |0 = IC0 input to Input Capture Unit Disabled. + * | | |1 = IC0 input to Input Capture Unit Enabled. + * |[5] |IC1EN |Port Pin IC1 Input to Input Capture Unit Enable Control + * | | |0 = IC1 input to Input Capture Unit Disabled. + * | | |1 = IC1 input to Input Capture Unit Enabled. + * |[6] |IC2EN |Port Pin IC2 Input to Input Capture Unit Enable Control + * | | |0 = IC2 input to Input Capture Unit Disabled. + * | | |1 = IC2 input to Input Capture Unit Enabled. + * |[9:8] |CAPSEL0 |CAP0 Input Source Selection + * | | |00 = CAP0 input is from port pin ICAP0. + * | | |01 = Reserved. + * | | |10 = CAP0 input is from signal CHA of QEI controller unit n. + * | | |11 = Reserved. + * | | |Note: Input capture unit n matches QEIn, where n = 0~1. + * |[11:10] |CAPSEL1 |CAP1 Input Source Selection + * | | |00 = CAP1 input is from port pin ICAP1. + * | | |01 = Reserved. + * | | |10 = CAP1 input is from signal CHB of QEI controller unit n. + * | | |11 = Reserved. + * | | |Note: Input capture unit n matches QEIn, where n = 0~1. + * |[13:12] |CAPSEL2 |CAP2 Input Source Selection + * | | |00 = CAP2 input is from port pin ICAP2. + * | | |01 = Reserved. + * | | |10 = CAP2 input is from signal CHX of QEI controller unit n. + * | | |11 = Reserved. + * | | |Note: Input capture unit n matches QEIn, where n = 0~1. + * |[16] |CAPIEN0 |Input Capture Channel 0 Interrupt Enable Control + * | | |0 = The flag CAPTF0 can trigger Input Capture interrupt Disabled. + * | | |1 = The flag CAPTF0 can trigger Input Capture interrupt Enabled. + * |[17] |CAPIEN1 |Input Capture Channel 1 Interrupt Enable Control + * | | |0 = The flag CAPTF1 can trigger Input Capture interrupt Disabled. + * | | |1 = The flag CAPTF1 can trigger Input Capture interrupt Enabled. + * |[18] |CAPIEN2 |Input Capture Channel 2 Interrupt Enable Control + * | | |0 = The flag CAPTF2 can trigger Input Capture interrupt Disabled. + * | | |1 = The flag CAPTF2 can trigger Input Capture interrupt Enabled. + * |[20] |OVIEN |CAPOVF Trigger Input Capture Interrupt Enable Control + * | | |0 = The flag CAPOVF can trigger Input Capture interrupt Disabled. + * | | |1 = The flag CAPOVF can trigger Input Capture interrupt Enabled. + * |[21] |CMPIEN |CAPCMPF Trigger Input Capture Interrupt Enable Control + * | | |0 = The flag CAPCMPF can trigger Input Capture interrupt Disabled. + * | | |1 = The flag CAPCMPF can trigger Input Capture interrupt Enabled. + * |[24] |CNTEN |Input Capture Counter Start Counting Control + * | | |Setting this bit to 1, the capture counter (ECAP_CNT) starts up-counting synchronously with the clock from the . + * | | |0 = ECAP_CNT stop counting. + * | | |1 = ECAP_CNT starts up-counting. + * |[25] |CMPCLREN |Input Capture Counter Cleared by Compare-match Control + * | | |If this bit is set to 1, the capture counter (ECAP_CNT) will be cleared to 0 when the compare-match event (CAPCMPF = 1) occurs. + * | | |0 = Compare-match event (CAPCMPF) can clear capture counter (ECAP_CNT) Disabled. + * | | |1 = Compare-match event (CAPCMPF) can clear capture counter (ECAP_CNT) Enabled. + * |[28] |CMPEN |Compare Function Enable Control + * | | |The compare function in input capture timer/counter is to compare the dynamic counting ECAP_CNT with the compare register ECAP_CNTCMP, if ECAP_CNT value reaches ECAP_CNTCMP, the flag CAPCMPF will be set. + * | | |0 = The compare function Disabled. + * | | |1 = The compare function Enabled. + * |[29] |CAPEN |Input Capture Timer/Counter Enable Control + * | | |0 = Input Capture function Disabled. + * | | |1 = Input Capture function Enabled. + * @var ECAP_T::CTL1 + * Offset: 0x18 Input Capture Control Register 1 + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[1:0] |EDGESEL0 |Channel 0 Captured Edge Selection + * | | |Input capture0 can detect falling edge change only, rising edge change only or both edge change + * | | |00 = Detect rising edge only. + * | | |01 = Detect falling edge only. + * | | |1x = Detect both rising and falling edge. + * |[3:2] |EDGESEL1 |Channel 1 Captured Edge Selection + * | | |Input capture1 can detect falling edge change only, rising edge change only or both edge change + * | | |00 = Detect rising edge only. + * | | |01 = Detect falling edge only. + * | | |1x = Detect both rising and falling edge. + * |[5:4] |EDGESEL2 |Channel 2 Captured Edge Selection + * | | |Input capture2 can detect falling edge change only, rising edge change only or both edge changes + * | | |00 = Detect rising edge only. + * | | |01 = Detect falling edge only. + * | | |1x = Detect both rising and falling edge. + * |[8] |CAP0RLDEN |Capture Counter Reload Function Triggered by Event CAPTE0 Enable Bit + * | | |0 = The reload triggered by Event CAPTE0 Disabled. + * | | |1 = The reload triggered by Event CAPTE0 Enabled. + * |[9] |CAP1RLDEN |Capture Counter Reload Function Triggered by Event CAPTE1 Enable Bit + * | | |0 = The reload triggered by Event CAPTE1 Disabled. + * | | |1 = The reload triggered by Event CAPTE1 Enabled. + * |[10] |CAP2RLDEN |Capture Counter Reload Function Triggered by Event CAPTE2 Enable Bit + * | | |0 = The reload triggered by Event CAPTE2 Disabled. + * | | |1 = The reload triggered by Event CAPTE2 Enabled. + * |[11] |OVRLDEN |Capture Counter Reload Function Triggered by Overflow Enable Bit + * | | |0 = The reload triggered by CAPOV Disabled. + * | | |1 = The reload triggered by CAPOV Enabled. + * |[14:12] |CLKSEL |Capture Timer Clock Divide Selection + * | | |The capture timer clock has a pre-divider with eight divided options controlled by CLKSEL[2:0]. + * | | |000 = CAP_CLK/1. + * | | |001 = CAP_CLK/4. + * | | |010 = CAP_CLK/16. + * | | |011 = CAP_CLK/32. + * | | |100 = CAP_CLK/64. + * | | |101 = CAP_CLK/96. + * | | |110 = CAP_CLK/112. + * | | |111 = CAP_CLK/128. + * |[17:16] |CNTSRCSEL |Capture Timer/Counter Clock Source Selection + * | | |Select the capture timer/counter clock source. + * | | |00 = CAP_CLK (default). + * | | |01 = CAP0. + * | | |10 = CAP1. + * | | |11 = CAP2. + * |[20] |CAP0CLREN |Capture Counter Cleared by Capture Event0 Control + * | | |0 = Event CAPTE0 can clear capture counter (ECAP_CNT) Disabled. + * | | |1 = Event CAPTE0 can clear capture counter (ECAP_CNT) Enabled. + * |[21] |CAP1CLREN |Capture Counter Cleared by Capture Event1 Control + * | | |0 = Event CAPTE1 can clear capture counter (ECAP_CNT) Disabled. + * | | |1 = Event CAPTE1 can clear capture counter (ECAP_CNT) Enabled. + * |[22] |CAP2CLREN |Capture Counter Cleared by Capture Event2 Control + * | | |0 = Event CAPTE2 can clear capture counter (ECAP_CNT) Disabled. + * | | |1 = Event CAPTE2 can clear capture counter (ECAP_CNT) Enabled. + * @var ECAP_T::STATUS + * Offset: 0x1C Input Capture Status Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[0] |CAPTF0 |Input Capture Channel 0 Triggered Flag + * | | |When the input capture channel 0 detects a valid edge change at CAP0 input, it will set flag CAPTF0 to high. + * | | |0 = No valid edge change has been detected at CAP0 input since last clear. + * | | |1 = At least a valid edge change has been detected at CAP0 input since last clear. + * | | |Note: This bit is only cleared by writing 1 to it. + * |[1] |CAPTF1 |Input Capture Channel 1 Triggered Flag + * | | |When the input capture channel 1 detects a valid edge change at CAP1 input, it will set flag CAPTF1 to high. + * | | |0 = No valid edge change has been detected at CAP1 input since last clear. + * | | |1 = At least a valid edge change has been detected at CAP1 input since last clear. + * | | |Note: This bit is only cleared by writing 1 to it. + * |[2] |CAPTF2 |Input Capture Channel 2 Triggered Flag + * | | |When the input capture channel 2 detects a valid edge change at CAP2 input, it will set flag CAPTF2 to high. + * | | |0 = No valid edge change has been detected at CAP2 input since last clear. + * | | |1 = At least a valid edge change has been detected at CAP2 input since last clear. + * | | |Note: This bit is only cleared by writing 1 to it. + * |[4] |CAPCMPF |Input Capture Compare-match Flag + * | | |If the input capture compare function is enabled, the flag is set by hardware when capture counter (ECAP_CNT) up counts and reaches the ECAP_CNTCMP value. + * | | |0 = ECAP_CNT has not matched ECAP_CNTCMP value since last clear. + * | | |1 = ECAP_CNT has matched ECAP_CNTCMP value at least once since last clear. + * | | |Note: This bit is only cleared by writing 1 to it. + * |[5] |CAPOVF |Input Capture Counter Overflow Flag + * | | |Flag is set by hardware when counter (ECAP_CNT) overflows from 0x00FF_FFFF to zero. + * | | |0 = No overflow event has occurred since last clear. + * | | |1 = Overflow event(s) has/have occurred since last clear. + * | | |Note: This bit is only cleared by writing 1 to it. + * |[6] |CAP0 |Value of Input Channel 0, CAP0 (Read Only) + * | | |Reflecting the value of input channel 0, CAP0 + * | | |(The bit is read only and write is ignored) + * |[7] |CAP1 |Value of Input Channel 1, CAP1 (Read Only) + * | | |Reflecting the value of input channel 1, CAP1 + * | | |(The bit is read only and write is ignored) + * |[8] |CAP2 |Value of Input Channel 2, CAP2 (Read Only) + * | | |Reflecting the value of input channel 2, CAP2. + * | | |(The bit is read only and write is ignored) + */ + __IO uint32_t CNT; /*!< [0x0000] Input Capture Counter */ + __IO uint32_t HLD0; /*!< [0x0004] Input Capture Hold Register 0 */ + __IO uint32_t HLD1; /*!< [0x0008] Input Capture Hold Register 1 */ + __IO uint32_t HLD2; /*!< [0x000c] Input Capture Hold Register 2 */ + __IO uint32_t CNTCMP; /*!< [0x0010] Input Capture Compare Register */ + __IO uint32_t CTL0; /*!< [0x0014] Input Capture Control Register 0 */ + __IO uint32_t CTL1; /*!< [0x0018] Input Capture Control Register 1 */ + __IO uint32_t STATUS; /*!< [0x001c] Input Capture Status Register */ + +} ECAP_T; + +/** + @addtogroup ECAP_CONST ECAP Bit Field Definition + Constant Definitions for ECAP Controller +@{ */ + +#define ECAP_CNT_CNT_Pos (0) /*!< ECAP_T::CNT: CNT Position */ +#define ECAP_CNT_CNT_Msk (0xfffffful << ECAP_CNT_CNT_Pos) /*!< ECAP_T::CNT: CNT Mask */ + +#define ECAP_HLD0_HOLD_Pos (0) /*!< ECAP_T::HLD0: HOLD Position */ +#define ECAP_HLD0_HOLD_Msk (0xfffffful << ECAP_HLD0_HOLD_Pos) /*!< ECAP_T::HLD0: HOLD Mask */ + +#define ECAP_HLD1_HOLD_Pos (0) /*!< ECAP_T::HLD1: HOLD Position */ +#define ECAP_HLD1_HOLD_Msk (0xfffffful << ECAP_HLD1_HOLD_Pos) /*!< ECAP_T::HLD1: HOLD Mask */ + +#define ECAP_HLD2_HOLD_Pos (0) /*!< ECAP_T::HLD2: HOLD Position */ +#define ECAP_HLD2_HOLD_Msk (0xfffffful << ECAP_HLD2_HOLD_Pos) /*!< ECAP_T::HLD2: HOLD Mask */ + +#define ECAP_CNTCMP_CNTCMP_Pos (0) /*!< ECAP_T::CNTCMP: CNTCMP Position */ +#define ECAP_CNTCMP_CNTCMP_Msk (0xfffffful << ECAP_CNTCMP_CNTCMP_Pos) /*!< ECAP_T::CNTCMP: CNTCMP Mask */ + +#define ECAP_CTL0_NFCLKSEL_Pos (0) /*!< ECAP_T::CTL0: NFCLKSEL Position */ +#define ECAP_CTL0_NFCLKSEL_Msk (0x7ul << ECAP_CTL0_NFCLKSEL_Pos) /*!< ECAP_T::CTL0: NFCLKSEL Mask */ + +#define ECAP_CTL0_CAPNFDIS_Pos (3) /*!< ECAP_T::CTL0: CAPNFDIS Position */ +#define ECAP_CTL0_CAPNFDIS_Msk (0x1ul << ECAP_CTL0_CAPNFDIS_Pos) /*!< ECAP_T::CTL0: CAPNFDIS Mask */ + +#define ECAP_CTL0_IC0EN_Pos (4) /*!< ECAP_T::CTL0: IC0EN Position */ +#define ECAP_CTL0_IC0EN_Msk (0x1ul << ECAP_CTL0_IC0EN_Pos) /*!< ECAP_T::CTL0: IC0EN Mask */ + +#define ECAP_CTL0_IC1EN_Pos (5) /*!< ECAP_T::CTL0: IC1EN Position */ +#define ECAP_CTL0_IC1EN_Msk (0x1ul << ECAP_CTL0_IC1EN_Pos) /*!< ECAP_T::CTL0: IC1EN Mask */ + +#define ECAP_CTL0_IC2EN_Pos (6) /*!< ECAP_T::CTL0: IC2EN Position */ +#define ECAP_CTL0_IC2EN_Msk (0x1ul << ECAP_CTL0_IC2EN_Pos) /*!< ECAP_T::CTL0: IC2EN Mask */ + +#define ECAP_CTL0_CAPSEL0_Pos (8) /*!< ECAP_T::CTL0: CAPSEL0 Position */ +#define ECAP_CTL0_CAPSEL0_Msk (0x3ul << ECAP_CTL0_CAPSEL0_Pos) /*!< ECAP_T::CTL0: CAPSEL0 Mask */ + +#define ECAP_CTL0_CAPSEL1_Pos (10) /*!< ECAP_T::CTL0: CAPSEL1 Position */ +#define ECAP_CTL0_CAPSEL1_Msk (0x3ul << ECAP_CTL0_CAPSEL1_Pos) /*!< ECAP_T::CTL0: CAPSEL1 Mask */ + +#define ECAP_CTL0_CAPSEL2_Pos (12) /*!< ECAP_T::CTL0: CAPSEL2 Position */ +#define ECAP_CTL0_CAPSEL2_Msk (0x3ul << ECAP_CTL0_CAPSEL2_Pos) /*!< ECAP_T::CTL0: CAPSEL2 Mask */ + +#define ECAP_CTL0_CAPIEN0_Pos (16) /*!< ECAP_T::CTL0: CAPIEN0 Position */ +#define ECAP_CTL0_CAPIEN0_Msk (0x1ul << ECAP_CTL0_CAPIEN0_Pos) /*!< ECAP_T::CTL0: CAPIEN0 Mask */ + +#define ECAP_CTL0_CAPIEN1_Pos (17) /*!< ECAP_T::CTL0: CAPIEN1 Position */ +#define ECAP_CTL0_CAPIEN1_Msk (0x1ul << ECAP_CTL0_CAPIEN1_Pos) /*!< ECAP_T::CTL0: CAPIEN1 Mask */ + +#define ECAP_CTL0_CAPIEN2_Pos (18) /*!< ECAP_T::CTL0: CAPIEN2 Position */ +#define ECAP_CTL0_CAPIEN2_Msk (0x1ul << ECAP_CTL0_CAPIEN2_Pos) /*!< ECAP_T::CTL0: CAPIEN2 Mask */ + +#define ECAP_CTL0_OVIEN_Pos (20) /*!< ECAP_T::CTL0: OVIEN Position */ +#define ECAP_CTL0_OVIEN_Msk (0x1ul << ECAP_CTL0_OVIEN_Pos) /*!< ECAP_T::CTL0: OVIEN Mask */ + +#define ECAP_CTL0_CMPIEN_Pos (21) /*!< ECAP_T::CTL0: CMPIEN Position */ +#define ECAP_CTL0_CMPIEN_Msk (0x1ul << ECAP_CTL0_CMPIEN_Pos) /*!< ECAP_T::CTL0: CMPIEN Mask */ + +#define ECAP_CTL0_CNTEN_Pos (24) /*!< ECAP_T::CTL0: CNTEN Position */ +#define ECAP_CTL0_CNTEN_Msk (0x1ul << ECAP_CTL0_CNTEN_Pos) /*!< ECAP_T::CTL0: CNTEN Mask */ + +#define ECAP_CTL0_CMPCLREN_Pos (25) /*!< ECAP_T::CTL0: CMPCLREN Position */ +#define ECAP_CTL0_CMPCLREN_Msk (0x1ul << ECAP_CTL0_CMPCLREN_Pos) /*!< ECAP_T::CTL0: CMPCLREN Mask */ + +#define ECAP_CTL0_CMPEN_Pos (28) /*!< ECAP_T::CTL0: CMPEN Position */ +#define ECAP_CTL0_CMPEN_Msk (0x1ul << ECAP_CTL0_CMPEN_Pos) /*!< ECAP_T::CTL0: CMPEN Mask */ + +#define ECAP_CTL0_CAPEN_Pos (29) /*!< ECAP_T::CTL0: CAPEN Position */ +#define ECAP_CTL0_CAPEN_Msk (0x1ul << ECAP_CTL0_CAPEN_Pos) /*!< ECAP_T::CTL0: CAPEN Mask */ + +#define ECAP_CTL1_EDGESEL0_Pos (0) /*!< ECAP_T::CTL1: EDGESEL0 Position */ +#define ECAP_CTL1_EDGESEL0_Msk (0x3ul << ECAP_CTL1_EDGESEL0_Pos) /*!< ECAP_T::CTL1: EDGESEL0 Mask */ + +#define ECAP_CTL1_EDGESEL1_Pos (2) /*!< ECAP_T::CTL1: EDGESEL1 Position */ +#define ECAP_CTL1_EDGESEL1_Msk (0x3ul << ECAP_CTL1_EDGESEL1_Pos) /*!< ECAP_T::CTL1: EDGESEL1 Mask */ + +#define ECAP_CTL1_EDGESEL2_Pos (4) /*!< ECAP_T::CTL1: EDGESEL2 Position */ +#define ECAP_CTL1_EDGESEL2_Msk (0x3ul << ECAP_CTL1_EDGESEL2_Pos) /*!< ECAP_T::CTL1: EDGESEL2 Mask */ + +#define ECAP_CTL1_CAP0RLDEN_Pos (8) /*!< ECAP_T::CTL1: CAP0RLDEN Position */ +#define ECAP_CTL1_CAP0RLDEN_Msk (0x1ul << ECAP_CTL1_CAP0RLDEN_Pos) /*!< ECAP_T::CTL1: CAP0RLDEN Mask */ + +#define ECAP_CTL1_CAP1RLDEN_Pos (9) /*!< ECAP_T::CTL1: CAP1RLDEN Position */ +#define ECAP_CTL1_CAP1RLDEN_Msk (0x1ul << ECAP_CTL1_CAP1RLDEN_Pos) /*!< ECAP_T::CTL1: CAP1RLDEN Mask */ + +#define ECAP_CTL1_CAP2RLDEN_Pos (10) /*!< ECAP_T::CTL1: CAP2RLDEN Position */ +#define ECAP_CTL1_CAP2RLDEN_Msk (0x1ul << ECAP_CTL1_CAP2RLDEN_Pos) /*!< ECAP_T::CTL1: CAP2RLDEN Mask */ + +#define ECAP_CTL1_OVRLDEN_Pos (11) /*!< ECAP_T::CTL1: OVRLDEN Position */ +#define ECAP_CTL1_OVRLDEN_Msk (0x1ul << ECAP_CTL1_OVRLDEN_Pos) /*!< ECAP_T::CTL1: OVRLDEN Mask */ + +#define ECAP_CTL1_CLKSEL_Pos (12) /*!< ECAP_T::CTL1: CLKSEL Position */ +#define ECAP_CTL1_CLKSEL_Msk (0x7ul << ECAP_CTL1_CLKSEL_Pos) /*!< ECAP_T::CTL1: CLKSEL Mask */ + +#define ECAP_CTL1_CNTSRCSEL_Pos (16) /*!< ECAP_T::CTL1: CNTSRCSEL Position */ +#define ECAP_CTL1_CNTSRCSEL_Msk (0x3ul << ECAP_CTL1_CNTSRCSEL_Pos) /*!< ECAP_T::CTL1: CNTSRCSEL Mask */ + +#define ECAP_CTL1_CAP0CLREN_Pos (20) /*!< ECAP_T::CTL1: CAP0CLREN Position */ +#define ECAP_CTL1_CAP0CLREN_Msk (0x1ul << ECAP_CTL1_CAP0CLREN_Pos) /*!< ECAP_T::CTL1: CAP0CLREN Mask */ + +#define ECAP_CTL1_CAP1CLREN_Pos (21) /*!< ECAP_T::CTL1: CAP1CLREN Position */ +#define ECAP_CTL1_CAP1CLREN_Msk (0x1ul << ECAP_CTL1_CAP1CLREN_Pos) /*!< ECAP_T::CTL1: CAP1CLREN Mask */ + +#define ECAP_CTL1_CAP2CLREN_Pos (22) /*!< ECAP_T::CTL1: CAP2CLREN Position */ +#define ECAP_CTL1_CAP2CLREN_Msk (0x1ul << ECAP_CTL1_CAP2CLREN_Pos) /*!< ECAP_T::CTL1: CAP2CLREN Mask */ + +#define ECAP_STATUS_CAPTF0_Pos (0) /*!< ECAP_T::STATUS: CAPTF0 Position */ +#define ECAP_STATUS_CAPTF0_Msk (0x1ul << ECAP_STATUS_CAPTF0_Pos) /*!< ECAP_T::STATUS: CAPTF0 Mask */ + +#define ECAP_STATUS_CAPTF1_Pos (1) /*!< ECAP_T::STATUS: CAPTF1 Position */ +#define ECAP_STATUS_CAPTF1_Msk (0x1ul << ECAP_STATUS_CAPTF1_Pos) /*!< ECAP_T::STATUS: CAPTF1 Mask */ + +#define ECAP_STATUS_CAPTF2_Pos (2) /*!< ECAP_T::STATUS: CAPTF2 Position */ +#define ECAP_STATUS_CAPTF2_Msk (0x1ul << ECAP_STATUS_CAPTF2_Pos) /*!< ECAP_T::STATUS: CAPTF2 Mask */ + +#define ECAP_STATUS_CAPCMPF_Pos (4) /*!< ECAP_T::STATUS: CAPCMPF Position */ +#define ECAP_STATUS_CAPCMPF_Msk (0x1ul << ECAP_STATUS_CAPCMPF_Pos) /*!< ECAP_T::STATUS: CAPCMPF Mask */ + +#define ECAP_STATUS_CAPOVF_Pos (5) /*!< ECAP_T::STATUS: CAPOVF Position */ +#define ECAP_STATUS_CAPOVF_Msk (0x1ul << ECAP_STATUS_CAPOVF_Pos) /*!< ECAP_T::STATUS: CAPOVF Mask */ + +#define ECAP_STATUS_CAP0_Pos (8) /*!< ECAP_T::STATUS: CAP0 Position */ +#define ECAP_STATUS_CAP0_Msk (0x1ul << ECAP_STATUS_CAP0_Pos) /*!< ECAP_T::STATUS: CAP0 Mask */ + +#define ECAP_STATUS_CAP1_Pos (9) /*!< ECAP_T::STATUS: CAP1 Position */ +#define ECAP_STATUS_CAP1_Msk (0x1ul << ECAP_STATUS_CAP1_Pos) /*!< ECAP_T::STATUS: CAP1 Mask */ + +#define ECAP_STATUS_CAP2_Pos (10) /*!< ECAP_T::STATUS: CAP2 Position */ +#define ECAP_STATUS_CAP2_Msk (0x1ul << ECAP_STATUS_CAP2_Pos) /*!< ECAP_T::STATUS: CAP2 Mask */ + +/**@}*/ /* ECAP_CONST */ +/**@}*/ /* end of ECAP register group */ +/**@}*/ /* end of REGISTER group */ + +#if defined ( __CC_ARM ) + #pragma no_anon_unions +#endif + +#endif /* __ECAP_REG_H__ */ diff --git a/bsp/nuvoton/libraries/ma35/Device/Nuvoton/MA35D1/Include/epwm_reg.h b/bsp/nuvoton/libraries/ma35/Device/Nuvoton/MA35D1/Include/epwm_reg.h new file mode 100644 index 0000000000..7f6d087900 --- /dev/null +++ b/bsp/nuvoton/libraries/ma35/Device/Nuvoton/MA35D1/Include/epwm_reg.h @@ -0,0 +1,4978 @@ +/**************************************************************************//** + * @file epwm_reg.h + * @brief EPWM register definition header file + * + * SPDX-License-Identifier: Apache-2.0 + * @copyright (C) 2020 Nuvoton Technology Corp. All rights reserved. + *****************************************************************************/ +#ifndef __EPWM_REG_H__ +#define __EPWM_REG_H__ + +#if defined ( __CC_ARM ) + #pragma anon_unions +#endif + +/** + @addtogroup REGISTER Control Register + @{ +*/ + +/*---------------------- Enhanced PWM Generator -------------------------*/ +/** + @addtogroup EPWM Enhanced PWM Generator(EPWM) + Memory Mapped Structure for EPWM Controller +@{ */ + +typedef struct +{ + /** + * @var ECAPDAT_T::RCAPDAT + * Offset: 0x20C EPWM Rising Capture Data Register 0~5 + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[15:0] |RCAPDAT |EPWM Rising Capture Data (Read Only) + * | | |When rising capture condition happened, the EPWM counter value will be saved in this register. + * @var ECAPDAT_T::FCAPDAT + * Offset: 0x210 EPWM Falling Capture Data Register 0~5 + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[15:0] |FCAPDAT |EPWM Falling Capture Data (Read Only) + * | | |When falling capture condition happened, the EPWM counter value will be saved in this register. + */ + __IO uint32_t RCAPDAT; /*!< [0x20C/0x214/0x21C/0x224/0x22C/0x234] EPWM Rising Capture Data Register 0~5 */ + __IO uint32_t FCAPDAT; /*!< [0x210/0x218/0x220/0x228/0x230/0x238] EPWM Falling Capture Data Register 0~5 */ +} ECAPDAT_T; + +typedef struct +{ + + + /** + * @var EPWM_T::CTL0 + * Offset: 0x00 EPWM Control Register 0 + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[0] |CTRLD0 |Center Re-load + * | | |In up-down counter type, PERIOD will load to PBUF at the end point of each period + * | | |CMPDAT will load to CMPBUF at the center point of a period + * |[1] |CTRLD1 |Center Re-load + * | | |In up-down counter type, PERIOD will load to PBUF at the end point of each period + * | | |CMPDAT will load to CMPBUF at the center point of a period + * |[2] |CTRLD2 |Center Re-load + * | | |In up-down counter type, PERIOD will load to PBUF at the end point of each period + * | | |CMPDAT will load to CMPBUF at the center point of a period + * |[3] |CTRLD3 |Center Re-load + * | | |In up-down counter type, PERIOD will load to PBUF at the end point of each period + * | | |CMPDAT will load to CMPBUF at the center point of a period + * |[4] |CTRLD4 |Center Re-load + * | | |In up-down counter type, PERIOD will load to PBUF at the end point of each period + * | | |CMPDAT will load to CMPBUF at the center point of a period + * |[5] |CTRLD5 |Center Re-load + * | | |In up-down counter type, PERIOD will load to PBUF at the end point of each period + * | | |CMPDAT will load to CMPBUF at the center point of a period + * |[8] |WINLDEN0 |Window Load Enable Bits + * | | |0 = PERIOD will load to PBUF at the end point of each period + * | | |CMPDAT will load to CMPBUF at the end point or center point of each period by setting CTRLD bit. + * | | |1 = PERIOD will load to PBUF at the end point of each period + * | | |CMPDAT will load to CMPBUF at the end point of each period when valid reload window is set + * | | |The valid reload window is set by software write 1 to EPWM_LOAD register and cleared by hardware after load success. + * |[9] |WINLDEN1 |Window Load Enable Bits + * | | |0 = PERIOD will load to PBUF at the end point of each period + * | | |CMPDAT will load to CMPBUF at the end point or center point of each period by setting CTRLD bit. + * | | |1 = PERIOD will load to PBUF at the end point of each period + * | | |CMPDAT will load to CMPBUF at the end point of each period when valid reload window is set + * | | |The valid reload window is set by software write 1 to EPWM_LOAD register and cleared by hardware after load success. + * |[10] |WINLDEN2 |Window Load Enable Bits + * | | |0 = PERIOD will load to PBUF at the end point of each period + * | | |CMPDAT will load to CMPBUF at the end point or center point of each period by setting CTRLD bit. + * | | |1 = PERIOD will load to PBUF at the end point of each period + * | | |CMPDAT will load to CMPBUF at the end point of each period when valid reload window is set + * | | |The valid reload window is set by software write 1 to EPWM_LOAD register and cleared by hardware after load success. + * |[11] |WINLDEN3 |Window Load Enable Bits + * | | |0 = PERIOD will load to PBUF at the end point of each period + * | | |CMPDAT will load to CMPBUF at the end point or center point of each period by setting CTRLD bit. + * | | |1 = PERIOD will load to PBUF at the end point of each period + * | | |CMPDAT will load to CMPBUF at the end point of each period when valid reload window is set + * | | |The valid reload window is set by software write 1 to EPWM_LOAD register and cleared by hardware after load success. + * |[12] |WINLDEN4 |Window Load Enable Bits + * | | |0 = PERIOD will load to PBUF at the end point of each period + * | | |CMPDAT will load to CMPBUF at the end point or center point of each period by setting CTRLD bit. + * | | |1 = PERIOD will load to PBUF at the end point of each period + * | | |CMPDAT will load to CMPBUF at the end point of each period when valid reload window is set + * | | |The valid reload window is set by software write 1 to EPWM_LOAD register and cleared by hardware after load success. + * |[13] |WINLDEN5 |Window Load Enable Bits + * | | |0 = PERIOD will load to PBUF at the end point of each period + * | | |CMPDAT will load to CMPBUF at the end point or center point of each period by setting CTRLD bit. + * | | |1 = PERIOD will load to PBUF at the end point of each period + * | | |CMPDAT will load to CMPBUF at the end point of each period when valid reload window is set + * | | |The valid reload window is set by software write 1 to EPWM_LOAD register and cleared by hardware after load success. + * |[16] |IMMLDEN0 |Immediately Load Enable Bits + * | | |0 = PERIOD will load to PBUF at the end point of each period + * | | |CMPDAT will load to CMPBUF at the end point or center point of each period by setting CTRLD bit. + * | | |1 = PERIOD/CMPDAT will load to PBUF and CMPBUF immediately when software update PERIOD/CMPDAT. + * | | |Note: If IMMLDENn is enabled, WINLDENn and CTRLDn will be invalid. + * |[17] |IMMLDEN1 |Immediately Load Enable Bits + * | | |0 = PERIOD will load to PBUF at the end point of each period + * | | |CMPDAT will load to CMPBUF at the end point or center point of each period by setting CTRLD bit. + * | | |1 = PERIOD/CMPDAT will load to PBUF and CMPBUF immediately when software update PERIOD/CMPDAT. + * | | |Note: If IMMLDENn is enabled, WINLDENn and CTRLDn will be invalid. + * |[18] |IMMLDEN2 |Immediately Load Enable Bits + * | | |0 = PERIOD will load to PBUF at the end point of each period + * | | |CMPDAT will load to CMPBUF at the end point or center point of each period by setting CTRLD bit. + * | | |1 = PERIOD/CMPDAT will load to PBUF and CMPBUF immediately when software update PERIOD/CMPDAT. + * | | |Note: If IMMLDENn is enabled, WINLDENn and CTRLDn will be invalid. + * |[19] |IMMLDEN3 |Immediately Load Enable Bits + * | | |0 = PERIOD will load to PBUF at the end point of each period + * | | |CMPDAT will load to CMPBUF at the end point or center point of each period by setting CTRLD bit. + * | | |1 = PERIOD/CMPDAT will load to PBUF and CMPBUF immediately when software update PERIOD/CMPDAT. + * | | |Note: If IMMLDENn is enabled, WINLDENn and CTRLDn will be invalid. + * |[20] |IMMLDEN4 |Immediately Load Enable Bits + * | | |0 = PERIOD will load to PBUF at the end point of each period + * | | |CMPDAT will load to CMPBUF at the end point or center point of each period by setting CTRLD bit. + * | | |1 = PERIOD/CMPDAT will load to PBUF and CMPBUF immediately when software update PERIOD/CMPDAT. + * | | |Note: If IMMLDENn is enabled, WINLDENn and CTRLDn will be invalid. + * |[21] |IMMLDEN5 |Immediately Load Enable Bits + * | | |0 = PERIOD will load to PBUF at the end point of each period + * | | |CMPDAT will load to CMPBUF at the end point or center point of each period by setting CTRLD bit. + * | | |1 = PERIOD/CMPDAT will load to PBUF and CMPBUF immediately when software update PERIOD/CMPDAT. + * | | |Note: If IMMLDENn is enabled, WINLDENn and CTRLDn will be invalid. + * |[24] |GROUPEN |Group Function Enable Bit + * | | |0 = The output waveform of each EPWM channel are independent. + * | | |1 = Unify the EPWM_CH2 and EPWM_CH4 to output the same waveform as EPWM_CH0 and unify the EPWM_CH3 and EPWM_CH5 to output the same waveform as EPWM_CH1. + * |[30] |DBGHALT |ICE Debug Mode Counter Halt (Write Protect) + * | | |If counter halt is enabled, all EPWM counters will keep current value until exit ICE debug mode. + * | | |0 = ICE debug mode counter halt Disabled. + * | | |1 = ICE debug mode counter halt Enabled. + * | | |Note: This bit is write protected + * | | |Refer to the SYS_RLKTZS register or SYS_RLKTZNS register or SYS_RLKSUBM register + * |[31] |DBGTRIOFF |ICE Debug Mode Acknowledge Disable Bit (Write Protect) + * | | |0 = ICE debug mode acknowledgement effects EPWM output. + * | | |EPWM pin will be forced as tri-state while ICE debug mode acknowledged. + * | | |1 = ICE debug mode acknowledgement disabled. + * | | |EPWM pin will keep output no matter ICE debug mode acknowledged or not. + * | | |Note: This bit is write protected + * | | |Refer to the SYS_RLKTZS register or SYS_RLKTZNS register or SYS_RLKSUBM register + * @var EPWM_T::CTL1 + * Offset: 0x04 EPWM Control Register 1 + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[1:0] |CNTTYPE0 |EPWM Counter Behavior Type + * | | |00 = Up counter type (supported in capture mode). + * | | |01 = Down count type (supported in capture mode). + * | | |10 = Up-down counter type. + * | | |11 = Reserved. + * |[3:2] |CNTTYPE1 |EPWM Counter Behavior Type + * | | |00 = Up counter type (supported in capture mode). + * | | |01 = Down count type (supported in capture mode). + * | | |10 = Up-down counter type. + * | | |11 = Reserved. + * |[5:4] |CNTTYPE2 |EPWM Counter Behavior Type + * | | |00 = Up counter type (supported in capture mode). + * | | |01 = Down count type (supported in capture mode). + * | | |10 = Up-down counter type. + * | | |11 = Reserved. + * |[7:6] |CNTTYPE3 |EPWM Counter Behavior Type + * | | |00 = Up counter type (supported in capture mode). + * | | |01 = Down count type (supported in capture mode). + * | | |10 = Up-down counter type. + * | | |11 = Reserved. + * |[9:8] |CNTTYPE4 |EPWM Counter Behavior Type + * | | |00 = Up counter type (supported in capture mode). + * | | |01 = Down count type (supported in capture mode). + * | | |10 = Up-down counter type. + * | | |11 = Reserved. + * |[11:10] |CNTTYPE5 |EPWM Counter Behavior Type + * | | |00 = Up counter type (supported in capture mode). + * | | |01 = Down count type (supported in capture mode). + * | | |10 = Up-down counter type. + * | | |11 = Reserved. + * |[16] |CNTMODE0 |EPWM Counter Mode + * | | |0 = Auto-reload mode. + * | | |1 = One-shot mode. + * |[17] |CNTMODE1 |EPWM Counter Mode + * | | |0 = Auto-reload mode. + * | | |1 = One-shot mode. + * |[18] |CNTMODE2 |EPWM Counter Mode + * | | |0 = Auto-reload mode. + * | | |1 = One-shot mode. + * |[19] |CNTMODE3 |EPWM Counter Mode + * | | |0 = Auto-reload mode. + * | | |1 = One-shot mode. + * |[20] |CNTMODE4 |EPWM Counter Mode + * | | |0 = Auto-reload mode. + * | | |1 = One-shot mode. + * |[21] |CNTMODE5 |EPWM Counter Mode + * | | |0 = Auto-reload mode. + * | | |1 = One-shot mode. + * |[24] |OUTMODE0 |EPWM Output Mode + * | | |Each bit n controls the output mode of corresponding EPWM channel n. + * | | |0 = EPWM independent mode. + * | | |1 = EPWM complementary mode. + * | | |Note: When operating in group function, these bits must all set to the same mode. + * |[25] |OUTMODE2 |EPWM Output Mode + * | | |Each bit n controls the output mode of corresponding EPWM channel n. + * | | |0 = EPWM independent mode. + * | | |1 = EPWM complementary mode. + * | | |Note: When operating in group function, these bits must all set to the same mode. + * |[26] |OUTMODE4 |EPWM Output Mode + * | | |Each bit n controls the output mode of corresponding EPWM channel n. + * | | |0 = EPWM independent mode. + * | | |1 = EPWM complementary mode. + * | | |Note: When operating in group function, these bits must all set to the same mode. + * @var EPWM_T::SYNC + * Offset: 0x08 EPWM Synchronization Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[0] |PHSEN0 |SYNC Phase Enable Bits + * | | |0 = EPWM counter disabled to load PHS value. + * | | |1 = EPWM counter enabled to load PHS value. + * |[1] |PHSEN2 |SYNC Phase Enable Bits + * | | |0 = EPWM counter disabled to load PHS value. + * | | |1 = EPWM counter enabled to load PHS value. + * |[2] |PHSEN4 |SYNC Phase Enable Bits + * | | |0 = EPWM counter disabled to load PHS value. + * | | |1 = EPWM counter enabled to load PHS value. + * |[9:8] |SINSRC0 |EPWM0_SYNC_IN Source Selection + * | | |00 = Synchronize source from SYNC_IN or SWSYNC. + * | | |01 = Counter equal to 0. + * | | |10 = Counter equal to EPWM_CMPDATm, m denotes 1, 3, 5. + * | | |11 = SYNC_OUT will not be generated. + * |[11:10] |SINSRC2 |EPWM0_SYNC_IN Source Selection + * | | |00 = Synchronize source from SYNC_IN or SWSYNC. + * | | |01 = Counter equal to 0. + * | | |10 = Counter equal to EPWM_CMPDATm, m denotes 1, 3, 5. + * | | |11 = SYNC_OUT will not be generated. + * |[13:12] |SINSRC4 |EPWM0_SYNC_IN Source Selection + * | | |00 = Synchronize source from SYNC_IN or SWSYNC. + * | | |01 = Counter equal to 0. + * | | |10 = Counter equal to EPWM_CMPDATm, m denotes 1, 3, 5. + * | | |11 = SYNC_OUT will not be generated. + * |[16] |SNFLTEN |EPWM0_SYNC_IN Noise Filter Enable Bits + * | | |0 = Noise filter of input pin EPWM0_SYNC_IN Disabled. + * | | |1 = Noise filter of input pin EPWM0_SYNC_IN Enabled. + * |[19:17] |SFLTCSEL |SYNC Edge Detector Filter Clock Selection + * | | |000 = Filter clock = HCLK. + * | | |001 = Filter clock = HCLK/2. + * | | |010 = Filter clock = HCLK/4. + * | | |011 = Filter clock = HCLK/8. + * | | |100 = Filter clock = HCLK/16. + * | | |101 = Filter clock = HCLK/32. + * | | |110 = Filter clock = HCLK/64. + * | | |111 = Filter clock = HCLK/128. + * |[22:20] |SFLTCNT |SYNC Edge Detector Filter Count + * | | |The register bits control the counter number of edge detector. + * |[23] |SINPINV |SYNC Input Pin Inverse + * | | |0 = The state of pin SYNC is passed to the negative edge detector. + * | | |1 = The inversed state of pin SYNC is passed to the negative edge detector. + * |[24] |PHSDIR0 |EPWM Phase Direction Control + * | | |0 = Control EPWM counter count decrement after synchronizing. + * | | |1 = Control EPWM counter count increment after synchronizing. + * |[25] |PHSDIR2 |EPWM Phase Direction Control + * | | |0 = Control EPWM counter count decrement after synchronizing. + * | | |1 = Control EPWM counter count increment after synchronizing. + * |[26] |PHSDIR4 |EPWM Phase Direction Control + * | | |0 = Control EPWM counter count decrement after synchronizing. + * | | |1 = Control EPWM counter count increment after synchronizing. + * @var EPWM_T::SWSYNC + * Offset: 0x0C EPWM Software Control Synchronization Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[0] |SWSYNC0 |Software SYNC Function + * | | |When SINSRCn (EPWM_SYNC[13:8]) is selected to 0, SYNC_OUT source comes from SYNC_IN or this bit. + * |[1] |SWSYNC2 |Software SYNC Function + * | | |When SINSRCn (EPWM_SYNC[13:8]) is selected to 0, SYNC_OUT source comes from SYNC_IN or this bit. + * |[2] |SWSYNC4 |Software SYNC Function + * | | |When SINSRCn (EPWM_SYNC[13:8]) is selected to 0, SYNC_OUT source comes from SYNC_IN or this bit. + * @var EPWM_T::CLKSRC + * Offset: 0x10 EPWM Clock Source Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[3:0] |ECLKSRC0 |EPWM_CH01 External Clock Source Select + * | | |0000 = EPWMx_CLK, x denotes 0, 1 or 2. + * | | |0001 = TIMER0 overflow. + * | | |0010 = TIMER1 overflow. + * | | |0011 = TIMER2 overflow. + * | | |0100 = TIMER3 overflow. + * | | |0101 = TIMER4 overflow. + * | | |0110 = TIMER5 overflow. + * | | |0111 = TIMER6 overflow. + * | | |1000 = TIMER7 overflow. + * | | |1001 = TIMER8 overflow. + * | | |1010 = TIMER9 overflow. + * | | |1011 = TIMER10 overflow. + * | | |1100 = TIMER11 overflow. + * | | |Others = Reserved. + * |[11:8] |ECLKSRC2 |EPWM_CH23 External Clock Source Select + * | | |0000 = EPWMx_CLK, x denotes 0, 1 or 2. + * | | |0001 = TIMER0 overflow. + * | | |0010 = TIMER1 overflow. + * | | |0011 = TIMER2 overflow. + * | | |0100 = TIMER3 overflow. + * | | |0101 = TIMER4 overflow. + * | | |0110 = TIMER5 overflow. + * | | |0111 = TIMER6 overflow. + * | | |1000 = TIMER7 overflow. + * | | |1001 = TIMER8 overflow. + * | | |1010 = TIMER9 overflow. + * | | |1011 = TIMER10 overflow. + * | | |1100 = TIMER11 overflow. + * | | |Others = Reserved. + * |[19:16] |ECLKSRC4 |EPWM_CH45 External Clock Source Select + * | | |0000 = EPWMx_CLK, x denotes 0, 1 or 2. + * | | |0001 = TIMER0 overflow. + * | | |0010 = TIMER1 overflow. + * | | |0011 = TIMER2 overflow. + * | | |0100 = TIMER3 overflow. + * | | |0101 = TIMER4 overflow. + * | | |0110 = TIMER5 overflow. + * | | |0111 = TIMER6 overflow. + * | | |1000 = TIMER7 overflow. + * | | |1001 = TIMER8 overflow. + * | | |1010 = TIMER9 overflow. + * | | |1011 = TIMER10 overflow. + * | | |1100 = TIMER11 overflow. + * | | |Others = Reserved. + * @var EPWM_T::CLKPSC0_1 + * Offset: 0x14 EPWM Clock Prescale Register 0/1 + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[11:0] |CLKPSC |EPWM Counter Clock Prescale + * | | |The clock of EPWM counter is decided by clock prescaler + * | | |Each EPWM pair share one EPWM counter clock prescaler + * | | |The clock of EPWM counter is divided by (CLKPSC+ 1) + * @var EPWM_T::CLKPSC2_3 + * Offset: 0x18 EPWM Clock Prescale Register 2/3 + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[11:0] |CLKPSC |EPWM Counter Clock Prescale + * | | |The clock of EPWM counter is decided by clock prescaler + * | | |Each EPWM pair share one EPWM counter clock prescaler + * | | |The clock of EPWM counter is divided by (CLKPSC+ 1) + * @var EPWM_T::CLKPSC4_5 + * Offset: 0x1C EPWM Clock Prescale Register 4/5 + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[11:0] |CLKPSC |EPWM Counter Clock Prescale + * | | |The clock of EPWM counter is decided by clock prescaler + * | | |Each EPWM pair share one EPWM counter clock prescaler + * | | |The clock of EPWM counter is divided by (CLKPSC+ 1) + * @var EPWM_T::CNTEN + * Offset: 0x20 EPWM Counter Enable Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[0] |CNTEN0 |EPWM Counter Enable Bits + * | | |0 = EPWM Counter and clock prescaler stop running. + * | | |1 = EPWM Counter and clock prescaler start running. + * |[1] |CNTEN1 |EPWM Counter Enable Bits + * | | |0 = EPWM Counter and clock prescaler stop running. + * | | |1 = EPWM Counter and clock prescaler start running. + * |[2] |CNTEN2 |EPWM Counter Enable Bits + * | | |0 = EPWM Counter and clock prescaler stop running. + * | | |1 = EPWM Counter and clock prescaler start running. + * |[3] |CNTEN3 |EPWM Counter Enable Bits + * | | |0 = EPWM Counter and clock prescaler stop running. + * | | |1 = EPWM Counter and clock prescaler start running. + * |[4] |CNTEN4 |EPWM Counter Enable Bits + * | | |0 = EPWM Counter and clock prescaler stop running. + * | | |1 = EPWM Counter and clock prescaler start running. + * |[5] |CNTEN5 |EPWM Counter Enable Bits + * | | |0 = EPWM Counter and clock prescaler stop running. + * | | |1 = EPWM Counter and clock prescaler start running. + * @var EPWM_T::CNTCLR + * Offset: 0x24 EPWM Clear Counter Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[0] |CNTCLR0 |Clear EPWM Counter Control Bit + * | | |It is automatically cleared by hardware. Each bit n controls the corresponding EPWM channel n. + * | | |0 = No effect. + * | | |1 = Clear 16-bit EPWM counter to 0000H. + * |[1] |CNTCLR1 |Clear EPWM Counter Control Bit + * | | |It is automatically cleared by hardware. Each bit n controls the corresponding EPWM channel n. + * | | |0 = No effect. + * | | |1 = Clear 16-bit EPWM counter to 0000H. + * |[2] |CNTCLR2 |Clear EPWM Counter Control Bit + * | | |It is automatically cleared by hardware. Each bit n controls the corresponding EPWM channel n. + * | | |0 = No effect. + * | | |1 = Clear 16-bit EPWM counter to 0000H. + * |[3] |CNTCLR3 |Clear EPWM Counter Control Bit + * | | |It is automatically cleared by hardware. Each bit n controls the corresponding EPWM channel n. + * | | |0 = No effect. + * | | |1 = Clear 16-bit EPWM counter to 0000H. + * |[4] |CNTCLR4 |Clear EPWM Counter Control Bit + * | | |It is automatically cleared by hardware. Each bit n controls the corresponding EPWM channel n. + * | | |0 = No effect. + * | | |1 = Clear 16-bit EPWM counter to 0000H. + * |[5] |CNTCLR5 |Clear EPWM Counter Control Bit + * | | |It is automatically cleared by hardware. Each bit n controls the corresponding EPWM channel n. + * | | |0 = No effect. + * | | |1 = Clear 16-bit EPWM counter to 0000H. + * @var EPWM_T::LOAD + * Offset: 0x28 EPWM Load Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[0] |LOAD0 |Re-load EPWM Comparator Register Control Bit + * | | |This bit is software write, hardware clear when current EPWM period ended. + * | | |Write Operation: + * | | |0 = No effect. + * | | |1 = Set load window of window loading mode. + * | | |Read Operation: + * | | |0 = No load window is set. + * | | |1 = Load window is set. + * | | |Note: This bit is only used in window loading mode, WINLDENn(EPWM_CTL0[13:8]) = 1. + * |[1] |LOAD1 |Re-load EPWM Comparator Register Control Bit + * | | |This bit is software write, hardware clear when current EPWM period ended. + * | | |Write Operation: + * | | |0 = No effect. + * | | |1 = Set load window of window loading mode. + * | | |Read Operation: + * | | |0 = No load window is set. + * | | |1 = Load window is set. + * | | |Note: This bit is only used in window loading mode, WINLDENn(EPWM_CTL0[13:8]) = 1. + * |[2] |LOAD2 |Re-load EPWM Comparator Register Control Bit + * | | |This bit is software write, hardware clear when current EPWM period ended. + * | | |Write Operation: + * | | |0 = No effect. + * | | |1 = Set load window of window loading mode. + * | | |Read Operation: + * | | |0 = No load window is set. + * | | |1 = Load window is set. + * | | |Note: This bit is only used in window loading mode, WINLDENn(EPWM_CTL0[13:8]) = 1. + * |[3] |LOAD3 |Re-load EPWM Comparator Register Control Bit + * | | |This bit is software write, hardware clear when current EPWM period ended. + * | | |Write Operation: + * | | |0 = No effect. + * | | |1 = Set load window of window loading mode. + * | | |Read Operation: + * | | |0 = No load window is set. + * | | |1 = Load window is set. + * | | |Note: This bit is only used in window loading mode, WINLDENn(EPWM_CTL0[13:8]) = 1. + * |[4] |LOAD4 |Re-load EPWM Comparator Register Control Bit + * | | |This bit is software write, hardware clear when current EPWM period ended. + * | | |Write Operation: + * | | |0 = No effect. + * | | |1 = Set load window of window loading mode. + * | | |Read Operation: + * | | |0 = No load window is set. + * | | |1 = Load window is set. + * | | |Note: This bit is only used in window loading mode, WINLDENn(EPWM_CTL0[13:8]) = 1. + * |[5] |LOAD5 |Re-load EPWM Comparator Register Control Bit + * | | |This bit is software write, hardware clear when current EPWM period ended. + * | | |Write Operation: + * | | |0 = No effect. + * | | |1 = Set load window of window loading mode. + * | | |Read Operation: + * | | |0 = No load window is set. + * | | |1 = Load window is set. + * | | |Note: This bit is only used in window loading mode, WINLDENn(EPWM_CTL0[13:8]) = 1. + * @var EPWM_T::PERIOD0 + * Offset: 0x30 EPWM Period Register 0 + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[15:0] |PERIOD |EPWM Period Register + * | | |Up-Count mode: + * | | |In this mode, EPWM counter counts from 0 to PERIOD, and restarts from 0. + * | | |EPWM period time = (PERIOD+1) * (CLKPSC+1) * EPWM_CLK . + * | | |Down-Count mode: + * | | |In this mode, EPWM counter counts from PERIOD to 0, and restarts from PERIOD. + * | | |EPWM period time = (PERIOD+1) * (CLKPSC+1) * EPWM_CLK . + * | | |Up-Down-Count mode: + * | | |In this mode, EPWM counter counts from 0 to PERIOD, then decrements to 0 and repeats again. + * | | |EPWM period time = 2 * PERIOD * (CLKPSC+1) * EPWM_CLK. + * @var EPWM_T::PERIOD1 + * Offset: 0x34 EPWM Period Register 1 + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[15:0] |PERIOD |EPWM Period Register + * | | |Up-Count mode: + * | | |In this mode, EPWM counter counts from 0 to PERIOD, and restarts from 0. + * | | |EPWM period time = (PERIOD+1) * (CLKPSC+1) * EPWM_CLK . + * | | |Down-Count mode: + * | | |In this mode, EPWM counter counts from PERIOD to 0, and restarts from PERIOD. + * | | |EPWM period time = (PERIOD+1) * (CLKPSC+1) * EPWM_CLK . + * | | |Up-Down-Count mode: + * | | |In this mode, EPWM counter counts from 0 to PERIOD, then decrements to 0 and repeats again. + * | | |EPWM period time = 2 * PERIOD * (CLKPSC+1) * EPWM_CLK. + * @var EPWM_T::PERIOD2 + * Offset: 0x38 EPWM Period Register 2 + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[15:0] |PERIOD |EPWM Period Register + * | | |Up-Count mode: + * | | |In this mode, EPWM counter counts from 0 to PERIOD, and restarts from 0. + * | | |EPWM period time = (PERIOD+1) * (CLKPSC+1) * EPWM_CLK . + * | | |Down-Count mode: + * | | |In this mode, EPWM counter counts from PERIOD to 0, and restarts from PERIOD. + * | | |EPWM period time = (PERIOD+1) * (CLKPSC+1) * EPWM_CLK . + * | | |Up-Down-Count mode: + * | | |In this mode, EPWM counter counts from 0 to PERIOD, then decrements to 0 and repeats again. + * | | |EPWM period time = 2 * PERIOD * (CLKPSC+1) * EPWM_CLK. + * @var EPWM_T::PERIOD3 + * Offset: 0x3C EPWM Period Register 3 + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[15:0] |PERIOD |EPWM Period Register + * | | |Up-Count mode: + * | | |In this mode, EPWM counter counts from 0 to PERIOD, and restarts from 0. + * | | |EPWM period time = (PERIOD+1) * (CLKPSC+1) * EPWM_CLK . + * | | |Down-Count mode: + * | | |In this mode, EPWM counter counts from PERIOD to 0, and restarts from PERIOD. + * | | |EPWM period time = (PERIOD+1) * (CLKPSC+1) * EPWM_CLK . + * | | |Up-Down-Count mode: + * | | |In this mode, EPWM counter counts from 0 to PERIOD, then decrements to 0 and repeats again. + * | | |EPWM period time = 2 * PERIOD * (CLKPSC+1) * EPWM_CLK. + * @var EPWM_T::PERIOD4 + * Offset: 0x40 EPWM Period Register 4 + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[15:0] |PERIOD |EPWM Period Register + * | | |Up-Count mode: + * | | |In this mode, EPWM counter counts from 0 to PERIOD, and restarts from 0. + * | | |EPWM period time = (PERIOD+1) * (CLKPSC+1) * EPWM_CLK . + * | | |Down-Count mode: + * | | |In this mode, EPWM counter counts from PERIOD to 0, and restarts from PERIOD. + * | | |EPWM period time = (PERIOD+1) * (CLKPSC+1) * EPWM_CLK . + * | | |Up-Down-Count mode: + * | | |In this mode, EPWM counter counts from 0 to PERIOD, then decrements to 0 and repeats again. + * | | |EPWM period time = 2 * PERIOD * (CLKPSC+1) * EPWM_CLK. + * @var EPWM_T::PERIOD5 + * Offset: 0x44 EPWM Period Register 5 + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[15:0] |PERIOD |EPWM Period Register + * | | |Up-Count mode: + * | | |In this mode, EPWM counter counts from 0 to PERIOD, and restarts from 0. + * | | |EPWM period time = (PERIOD+1) * (CLKPSC+1) * EPWM_CLK . + * | | |Down-Count mode: + * | | |In this mode, EPWM counter counts from PERIOD to 0, and restarts from PERIOD. + * | | |EPWM period time = (PERIOD+1) * (CLKPSC+1) * EPWM_CLK . + * | | |Up-Down-Count mode: + * | | |In this mode, EPWM counter counts from 0 to PERIOD, then decrements to 0 and repeats again. + * | | |EPWM period time = 2 * PERIOD * (CLKPSC+1) * EPWM_CLK. + * @var EPWM_T::CMPDAT0 + * Offset: 0x50 EPWM Comparator Register 0 + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[15:0] |CMP |EPWM Comparator Register + * | | |CMP is used to compare with CNT (EPWM_CNTn[15:0]) bits to generate EPWM waveform, interrupt and trigger EADC. + * | | |In independent mode, CMPDAT0~5 is denoted as 6 independent EPWM_CH0~5 compared point. + * | | |In complementary mode, CMPDAT0, 2, 4 is denoted as the first compared point, and CMPDAT1, 3, 5 is denoted as the second compared point for the corresponding 3 complementary pairs EPWM_CH0 and EPWM_CH1, EPWM_CH2 and EPWM_CH3, EPWM_CH4 and EPWM_CH5. + * @var EPWM_T::CMPDAT1 + * Offset: 0x54 EPWM Comparator Register 1 + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[15:0] |CMP |EPWM Comparator Register + * | | |CMP is used to compare with CNT (EPWM_CNTn[15:0]) bits to generate EPWM waveform, interrupt and trigger EADC. + * | | |In independent mode, CMPDAT0~5 is denoted as 6 independent EPWM_CH0~5 compared point. + * | | |In complementary mode, CMPDAT0, 2, 4 is denoted as the first compared point, and CMPDAT1, 3, 5 is denoted as the second compared point for the corresponding 3 complementary pairs EPWM_CH0 and EPWM_CH1, EPWM_CH2 and EPWM_CH3, EPWM_CH4 and EPWM_CH5. + * @var EPWM_T::CMPDAT2 + * Offset: 0x58 EPWM Comparator Register 2 + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[15:0] |CMP |EPWM Comparator Register + * | | |CMP is used to compare with CNT (EPWM_CNTn[15:0]) bits to generate EPWM waveform, interrupt and trigger EADC. + * | | |In independent mode, CMPDAT0~5 is denoted as 6 independent EPWM_CH0~5 compared point. + * | | |In complementary mode, CMPDAT0, 2, 4 is denoted as the first compared point, and CMPDAT1, 3, 5 is denoted as the second compared point for the corresponding 3 complementary pairs EPWM_CH0 and EPWM_CH1, EPWM_CH2 and EPWM_CH3, EPWM_CH4 and EPWM_CH5. + * @var EPWM_T::CMPDAT3 + * Offset: 0x5C EPWM Comparator Register 3 + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[15:0] |CMP |EPWM Comparator Register + * | | |CMP is used to compare with CNT (EPWM_CNTn[15:0]) bits to generate EPWM waveform, interrupt and trigger EADC. + * | | |In independent mode, CMPDAT0~5 is denoted as 6 independent EPWM_CH0~5 compared point. + * | | |In complementary mode, CMPDAT0, 2, 4 is denoted as the first compared point, and CMPDAT1, 3, 5 is denoted as the second compared point for the corresponding 3 complementary pairs EPWM_CH0 and EPWM_CH1, EPWM_CH2 and EPWM_CH3, EPWM_CH4 and EPWM_CH5. + * @var EPWM_T::CMPDAT4 + * Offset: 0x60 EPWM Comparator Register 4 + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[15:0] |CMP |EPWM Comparator Register + * | | |CMP is used to compare with CNT (EPWM_CNTn[15:0]) bits to generate EPWM waveform, interrupt and trigger EADC. + * | | |In independent mode, CMPDAT0~5 is denoted as 6 independent EPWM_CH0~5 compared point. + * | | |In complementary mode, CMPDAT0, 2, 4 is denoted as the first compared point, and CMPDAT1, 3, 5 is denoted as the second compared point for the corresponding 3 complementary pairs EPWM_CH0 and EPWM_CH1, EPWM_CH2 and EPWM_CH3, EPWM_CH4 and EPWM_CH5. + * @var EPWM_T::CMPDAT5 + * Offset: 0x64 EPWM Comparator Register 5 + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[15:0] |CMP |EPWM Comparator Register + * | | |CMP is used to compare with CNT (EPWM_CNTn[15:0]) bits to generate EPWM waveform, interrupt and trigger EADC. + * | | |In independent mode, CMPDAT0~5 is denoted as 6 independent EPWM_CH0~5 compared point. + * | | |In complementary mode, CMPDAT0, 2, 4 is denoted as the first compared point, and CMPDAT1, 3, 5 is denoted as the second compared point for the corresponding 3 complementary pairs EPWM_CH0 and EPWM_CH1, EPWM_CH2 and EPWM_CH3, EPWM_CH4 and EPWM_CH5. + * @var EPWM_T::DTCTL0_1 + * Offset: 0x70 EPWM Dead-time Control Register 0/1 + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[11:0] |DTCNT |Dead-time Counter (Write Protect) + * | | |The dead-time can be calculated from the following formula: + * | | |DTCKSEL=0: Dead-time = (DTCNT[11:0]+1) * EPWM_CLK period. + * | | |DTCKSEL=1: Dead-time = (DTCNT[11:0]+1) * EPWM_CLK period * (CLKPSC+1). + * | | |Note: This bit is write protected + * | | |Refer to the SYS_RLKTZS register or SYS_RLKTZNS register or SYS_RLKSUBM register + * |[16] |DTEN |Enable Dead-time Insertion for EPWM Pair (Write Protect) + * | | |Dead-time insertion is only active when this pair of complementary EPWM is enabled + * | | |If dead- time insertion is inactive, the outputs of pin pair are complementary without any delay. + * | | |0 = Dead-time insertion disabled on the pin pair. + * | | |1 = Dead-time insertion enabled on the pin pair. + * | | |Note: This bit is write protected + * | | |Refer to the SYS_RLKTZS register or SYS_RLKTZNS register or SYS_RLKSUBM register + * |[24] |DTCKSEL |Dead-time Clock Select (Write Protect) + * | | |0 = Dead-time clock source from EPWM_CLK. + * | | |1 = Dead-time clock source from prescaler output. + * | | |Note: This bit is write protected. Refer to REGWRPROT register. + * @var EPWM_T::DTCTL2_3 + * Offset: 0x74 EPWM Dead-time Control Register 2/3 + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[11:0] |DTCNT |Dead-time Counter (Write Protect) + * | | |The dead-time can be calculated from the following formula: + * | | |DTCKSEL=0: Dead-time = (DTCNT[11:0]+1) * EPWM_CLK period. + * | | |DTCKSEL=1: Dead-time = (DTCNT[11:0]+1) * EPWM_CLK period * (CLKPSC+1). + * | | |Note: This bit is write protected + * | | |Refer to the SYS_RLKTZS register or SYS_RLKTZNS register or SYS_RLKSUBM register + * |[16] |DTEN |Enable Dead-time Insertion for EPWM Pair (Write Protect) + * | | |Dead-time insertion is only active when this pair of complementary EPWM is enabled + * | | |If dead- time insertion is inactive, the outputs of pin pair are complementary without any delay. + * | | |0 = Dead-time insertion disabled on the pin pair. + * | | |1 = Dead-time insertion enabled on the pin pair. + * | | |Note: This bit is write protected + * | | |Refer to the SYS_RLKTZS register or SYS_RLKTZNS register or SYS_RLKSUBM register + * |[24] |DTCKSEL |Dead-time Clock Select (Write Protect) + * | | |0 = Dead-time clock source from EPWM_CLK. + * | | |1 = Dead-time clock source from prescaler output. + * | | |Note: This bit is write protected. Refer to REGWRPROT register. + * @var EPWM_T::DTCTL4_5 + * Offset: 0x78 EPWM Dead-time Control Register 4/5 + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[11:0] |DTCNT |Dead-time Counter (Write Protect) + * | | |The dead-time can be calculated from the following formula: + * | | |DTCKSEL=0: Dead-time = (DTCNT[11:0]+1) * EPWM_CLK period. + * | | |DTCKSEL=1: Dead-time = (DTCNT[11:0]+1) * EPWM_CLK period * (CLKPSC+1). + * | | |Note: This bit is write protected + * | | |Refer to the SYS_RLKTZS register or SYS_RLKTZNS register or SYS_RLKSUBM register + * |[16] |DTEN |Enable Dead-time Insertion for EPWM Pair (Write Protect) + * | | |Dead-time insertion is only active when this pair of complementary EPWM is enabled + * | | |If dead- time insertion is inactive, the outputs of pin pair are complementary without any delay. + * | | |0 = Dead-time insertion disabled on the pin pair. + * | | |1 = Dead-time insertion enabled on the pin pair. + * | | |Note: This bit is write protected + * | | |Refer to the SYS_RLKTZS register or SYS_RLKTZNS register or SYS_RLKSUBM register + * |[24] |DTCKSEL |Dead-time Clock Select (Write Protect) + * | | |0 = Dead-time clock source from EPWM_CLK. + * | | |1 = Dead-time clock source from prescaler output. + * | | |Note: This bit is write protected. Refer to REGWRPROT register. + * @var EPWM_T::PHS0_1 + * Offset: 0x80 EPWM Counter Phase Register 0/1 + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[15:0] |PHS |EPWM Synchronous Start Phase Bits + * | | |PHS determines the EPWM synchronous start phase value + * | | |These bits are only used for synchronous function. + * @var EPWM_T::PHS2_3 + * Offset: 0x84 EPWM Counter Phase Register 2/3 + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[15:0] |PHS |EPWM Synchronous Start Phase Bits + * | | |PHS determines the EPWM synchronous start phase value + * | | |These bits are only used for synchronous function. + * @var EPWM_T::PHS4_5 + * Offset: 0x88 EPWM Counter Phase Register 4/5 + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[15:0] |PHS |EPWM Synchronous Start Phase Bits + * | | |PHS determines the EPWM synchronous start phase value + * | | |These bits are only used for synchronous function. + * @var EPWM_T::CNT0 + * Offset: 0x90 EPWM Counter Register 0 + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[15:0] |CNT |EPWM Data Register (Read Only) + * | | |User can monitor CNT to know the current value in 16-bit period counter. + * |[16] |DIRF |EPWM Direction Indicator Flag (Read Only) + * | | |0 = Counter is counting down. + * | | |1 = Counter is counting up. + * @var EPWM_T::CNT1 + * Offset: 0x94 EPWM Counter Register 1 + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[15:0] |CNT |EPWM Data Register (Read Only) + * | | |User can monitor CNT to know the current value in 16-bit period counter. + * |[16] |DIRF |EPWM Direction Indicator Flag (Read Only) + * | | |0 = Counter is counting down. + * | | |1 = Counter is counting up. + * @var EPWM_T::CNT2 + * Offset: 0x98 EPWM Counter Register 2 + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[15:0] |CNT |EPWM Data Register (Read Only) + * | | |User can monitor CNT to know the current value in 16-bit period counter. + * |[16] |DIRF |EPWM Direction Indicator Flag (Read Only) + * | | |0 = Counter is counting down. + * | | |1 = Counter is counting up. + * @var EPWM_T::CNT3 + * Offset: 0x9C EPWM Counter Register 3 + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[15:0] |CNT |EPWM Data Register (Read Only) + * | | |User can monitor CNT to know the current value in 16-bit period counter. + * |[16] |DIRF |EPWM Direction Indicator Flag (Read Only) + * | | |0 = Counter is counting down. + * | | |1 = Counter is counting up. + * @var EPWM_T::CNT4 + * Offset: 0xA0 EPWM Counter Register 4 + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[15:0] |CNT |EPWM Data Register (Read Only) + * | | |User can monitor CNT to know the current value in 16-bit period counter. + * |[16] |DIRF |EPWM Direction Indicator Flag (Read Only) + * | | |0 = Counter is counting down. + * | | |1 = Counter is counting up. + * @var EPWM_T::CNT5 + * Offset: 0xA4 EPWM Counter Register 5 + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[15:0] |CNT |EPWM Data Register (Read Only) + * | | |User can monitor CNT to know the current value in 16-bit period counter. + * |[16] |DIRF |EPWM Direction Indicator Flag (Read Only) + * | | |0 = Counter is counting down. + * | | |1 = Counter is counting up. + * @var EPWM_T::WGCTL0 + * Offset: 0xB0 EPWM Generation Register 0 + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[1:0] |ZPCTL0 |EPWM Zero Point Control + * | | |EPWM can control output level when EPWM counter counts to 0. + * | | |00 = Do nothing. + * | | |01 = EPWM zero point output Low. + * | | |10 = EPWM zero point output High. + * | | |11 = EPWM zero point output Toggle. + * |[3:2] |ZPCTL1 |EPWM Zero Point Control + * | | |EPWM can control output level when EPWM counter counts to 0. + * | | |00 = Do nothing. + * | | |01 = EPWM zero point output Low. + * | | |10 = EPWM zero point output High. + * | | |11 = EPWM zero point output Toggle. + * |[5:4] |ZPCTL2 |EPWM Zero Point Control + * | | |EPWM can control output level when EPWM counter counts to 0. + * | | |00 = Do nothing. + * | | |01 = EPWM zero point output Low. + * | | |10 = EPWM zero point output High. + * | | |11 = EPWM zero point output Toggle. + * |[7:6] |ZPCTL3 |EPWM Zero Point Control + * | | |EPWM can control output level when EPWM counter counts to 0. + * | | |00 = Do nothing. + * | | |01 = EPWM zero point output Low. + * | | |10 = EPWM zero point output High. + * | | |11 = EPWM zero point output Toggle. + * |[9:8] |ZPCTL4 |EPWM Zero Point Control + * | | |EPWM can control output level when EPWM counter counts to 0. + * | | |00 = Do nothing. + * | | |01 = EPWM zero point output Low. + * | | |10 = EPWM zero point output High. + * | | |11 = EPWM zero point output Toggle. + * |[11:10] |ZPCTL5 |EPWM Zero Point Control + * | | |EPWM can control output level when EPWM counter counts to 0. + * | | |00 = Do nothing. + * | | |01 = EPWM zero point output Low. + * | | |10 = EPWM zero point output High. + * | | |11 = EPWM zero point output Toggle. + * |[17:16] |PRDPCTL0 |EPWM Period Point Control + * | | |EPWM can control output level when EPWM counter counts to (PERIODn+1). + * | | |00 = Do nothing. + * | | |01 = EPWM period (center) point output Low. + * | | |10 = EPWM period (center) point output High. + * | | |11 = EPWM period (center) point output Toggle. + * | | |Note: This bit is center point control when EPWM counter operating in up-down counter type. + * |[19:18] |PRDPCTL1 |EPWM Period Point Control + * | | |EPWM can control output level when EPWM counter counts to (PERIODn+1). + * | | |00 = Do nothing. + * | | |01 = EPWM period (center) point output Low. + * | | |10 = EPWM period (center) point output High. + * | | |11 = EPWM period (center) point output Toggle. + * | | |Note: This bit is center point control when EPWM counter operating in up-down counter type. + * |[21:20] |PRDPCTL2 |EPWM Period Point Control + * | | |EPWM can control output level when EPWM counter counts to (PERIODn+1). + * | | |00 = Do nothing. + * | | |01 = EPWM period (center) point output Low. + * | | |10 = EPWM period (center) point output High. + * | | |11 = EPWM period (center) point output Toggle. + * | | |Note: This bit is center point control when EPWM counter operating in up-down counter type. + * |[23:22] |PRDPCTL3 |EPWM Period Point Control + * | | |EPWM can control output level when EPWM counter counts to (PERIODn+1). + * | | |00 = Do nothing. + * | | |01 = EPWM period (center) point output Low. + * | | |10 = EPWM period (center) point output High. + * | | |11 = EPWM period (center) point output Toggle. + * | | |Note: This bit is center point control when EPWM counter operating in up-down counter type. + * |[25:24] |PRDPCTL4 |EPWM Period Point Control + * | | |EPWM can control output level when EPWM counter counts to (PERIODn+1). + * | | |00 = Do nothing. + * | | |01 = EPWM period (center) point output Low. + * | | |10 = EPWM period (center) point output High. + * | | |11 = EPWM period (center) point output Toggle. + * | | |Note: This bit is center point control when EPWM counter operating in up-down counter type. + * |[27:26] |PRDPCTL5 |EPWM Period Point Control + * | | |EPWM can control output level when EPWM counter counts to (PERIODn+1). + * | | |00 = Do nothing. + * | | |01 = EPWM period (center) point output Low. + * | | |10 = EPWM period (center) point output High. + * | | |11 = EPWM period (center) point output Toggle. + * | | |Note: This bit is center point control when EPWM counter operating in up-down counter type. + * @var EPWM_T::WGCTL1 + * Offset: 0xB4 EPWM Generation Register 1 + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[1:0] |CMPUCTL0 |EPWM Compare Up Point Control + * | | |EPWM can control output level when EPWM counter counts up to CMPDAT. + * | | |00 = Do nothing. + * | | |01 = EPWM compare up point output Low. + * | | |10 = EPWM compare up point output High. + * | | |11 = EPWM compare up point output Toggle. + * | | |Note: In complementary mode, CMPUCTL1, 3, 5 is used as another CMPUCTL for channel 0, 2, 4. + * |[3:2] |CMPUCTL1 |EPWM Compare Up Point Control + * | | |EPWM can control output level when EPWM counter counts up to CMPDAT. + * | | |00 = Do nothing. + * | | |01 = EPWM compare up point output Low. + * | | |10 = EPWM compare up point output High. + * | | |11 = EPWM compare up point output Toggle. + * | | |Note: In complementary mode, CMPUCTL1, 3, 5 is used as another CMPUCTL for channel 0, 2, 4. + * |[5:4] |CMPUCTL2 |EPWM Compare Up Point Control + * | | |EPWM can control output level when EPWM counter counts up to CMPDAT. + * | | |00 = Do nothing. + * | | |01 = EPWM compare up point output Low. + * | | |10 = EPWM compare up point output High. + * | | |11 = EPWM compare up point output Toggle. + * | | |Note: In complementary mode, CMPUCTL1, 3, 5 is used as another CMPUCTL for channel 0, 2, 4. + * |[7:6] |CMPUCTL3 |EPWM Compare Up Point Control + * | | |EPWM can control output level when EPWM counter counts up to CMPDAT. + * | | |00 = Do nothing. + * | | |01 = EPWM compare up point output Low. + * | | |10 = EPWM compare up point output High. + * | | |11 = EPWM compare up point output Toggle. + * | | |Note: In complementary mode, CMPUCTL1, 3, 5 is used as another CMPUCTL for channel 0, 2, 4. + * |[9:8] |CMPUCTL4 |EPWM Compare Up Point Control + * | | |EPWM can control output level when EPWM counter counts up to CMPDAT. + * | | |00 = Do nothing. + * | | |01 = EPWM compare up point output Low. + * | | |10 = EPWM compare up point output High. + * | | |11 = EPWM compare up point output Toggle. + * | | |Note: In complementary mode, CMPUCTL1, 3, 5 is used as another CMPUCTL for channel 0, 2, 4. + * |[11:10] |CMPUCTL5 |EPWM Compare Up Point Control + * | | |EPWM can control output level when EPWM counter counts up to CMPDAT. + * | | |00 = Do nothing. + * | | |01 = EPWM compare up point output Low. + * | | |10 = EPWM compare up point output High. + * | | |11 = EPWM compare up point output Toggle. + * | | |Note: In complementary mode, CMPUCTL1, 3, 5 is used as another CMPUCTL for channel 0, 2, 4. + * |[17:16] |CMPDCTL0 |EPWM Compare Down Point Control + * | | |EPWM can control output level when EPWM counter counts down to CMPDAT. + * | | |00 = Do nothing. + * | | |01 = EPWM compare down point output Low. + * | | |10 = EPWM compare down point output High. + * | | |11 = EPWM compare down point output Toggle. + * | | |Note: In complementary mode, CMPDCTL1, 3, 5 is used as another CMPDCTL for channel 0, 2, 4. + * |[19:18] |CMPDCTL1 |EPWM Compare Down Point Control + * | | |EPWM can control output level when EPWM counter counts down to CMPDAT. + * | | |00 = Do nothing. + * | | |01 = EPWM compare down point output Low. + * | | |10 = EPWM compare down point output High. + * | | |11 = EPWM compare down point output Toggle. + * | | |Note: In complementary mode, CMPDCTL1, 3, 5 is used as another CMPDCTL for channel 0, 2, 4. + * |[21:20] |CMPDCTL2 |EPWM Compare Down Point Control + * | | |EPWM can control output level when EPWM counter counts down to CMPDAT. + * | | |00 = Do nothing. + * | | |01 = EPWM compare down point output Low. + * | | |10 = EPWM compare down point output High. + * | | |11 = EPWM compare down point output Toggle. + * | | |Note: In complementary mode, CMPDCTL1, 3, 5 is used as another CMPDCTL for channel 0, 2, 4. + * |[23:22] |CMPDCTL3 |EPWM Compare Down Point Control + * | | |EPWM can control output level when EPWM counter counts down to CMPDAT. + * | | |00 = Do nothing. + * | | |01 = EPWM compare down point output Low. + * | | |10 = EPWM compare down point output High. + * | | |11 = EPWM compare down point output Toggle. + * | | |Note: In complementary mode, CMPDCTL1, 3, 5 is used as another CMPDCTL for channel 0, 2, 4. + * |[25:24] |CMPDCTL4 |EPWM Compare Down Point Control + * | | |EPWM can control output level when EPWM counter counts down to CMPDAT. + * | | |00 = Do nothing. + * | | |01 = EPWM compare down point output Low. + * | | |10 = EPWM compare down point output High. + * | | |11 = EPWM compare down point output Toggle. + * | | |Note: In complementary mode, CMPDCTL1, 3, 5 is used as another CMPDCTL for channel 0, 2, 4. + * |[27:26] |CMPDCTL5 |EPWM Compare Down Point Control + * | | |EPWM can control output level when EPWM counter counts down to CMPDAT. + * | | |00 = Do nothing. + * | | |01 = EPWM compare down point output Low. + * | | |10 = EPWM compare down point output High. + * | | |11 = EPWM compare down point output Toggle. + * | | |Note: In complementary mode, CMPDCTL1, 3, 5 is used as another CMPDCTL for channel 0, 2, 4. + * @var EPWM_T::MSKEN + * Offset: 0xB8 EPWM Mask Enable Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[0] |MSKEN0 |EPWM Mask Enable Bits + * | | |The EPWM output signal will be masked when this bit is enabled + * | | |The corresponding EPWM channel n will output MSKDATn (EPWM_MSK[5:0]) data. + * | | |0 = EPWM output signal is non-masked. + * | | |1 = EPWM output signal is masked and output MSKDATn data. + * |[1] |MSKEN1 |EPWM Mask Enable Bits + * | | |The EPWM output signal will be masked when this bit is enabled + * | | |The corresponding EPWM channel n will output MSKDATn (EPWM_MSK[5:0]) data. + * | | |0 = EPWM output signal is non-masked. + * | | |1 = EPWM output signal is masked and output MSKDATn data. + * |[2] |MSKEN2 |EPWM Mask Enable Bits + * | | |The EPWM output signal will be masked when this bit is enabled + * | | |The corresponding EPWM channel n will output MSKDATn (EPWM_MSK[5:0]) data. + * | | |0 = EPWM output signal is non-masked. + * | | |1 = EPWM output signal is masked and output MSKDATn data. + * |[3] |MSKEN3 |EPWM Mask Enable Bits + * | | |The EPWM output signal will be masked when this bit is enabled + * | | |The corresponding EPWM channel n will output MSKDATn (EPWM_MSK[5:0]) data. + * | | |0 = EPWM output signal is non-masked. + * | | |1 = EPWM output signal is masked and output MSKDATn data. + * |[4] |MSKEN4 |EPWM Mask Enable Bits + * | | |The EPWM output signal will be masked when this bit is enabled + * | | |The corresponding EPWM channel n will output MSKDATn (EPWM_MSK[5:0]) data. + * | | |0 = EPWM output signal is non-masked. + * | | |1 = EPWM output signal is masked and output MSKDATn data. + * |[5] |MSKEN5 |EPWM Mask Enable Bits + * | | |The EPWM output signal will be masked when this bit is enabled + * | | |The corresponding EPWM channel n will output MSKDATn (EPWM_MSK[5:0]) data. + * | | |0 = EPWM output signal is non-masked. + * | | |1 = EPWM output signal is masked and output MSKDATn data. + * @var EPWM_T::MSK + * Offset: 0xBC EPWM Mask Data Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[0] |MSKDAT0 |EPWM Mask Data Bit + * | | |This data bit control the state of EPWMn output pin, if corresponding mask function is enabled. + * | | |0 = Output logic low to EPWM channel n. + * | | |1 = Output logic high to EPWM channel n. + * |[1] |MSKDAT1 |EPWM Mask Data Bit + * | | |This data bit control the state of EPWMn output pin, if corresponding mask function is enabled. + * | | |0 = Output logic low to EPWM channel n. + * | | |1 = Output logic high to EPWM channel n. + * |[2] |MSKDAT2 |EPWM Mask Data Bit + * | | |This data bit control the state of EPWMn output pin, if corresponding mask function is enabled. + * | | |0 = Output logic low to EPWM channel n. + * | | |1 = Output logic high to EPWM channel n. + * |[3] |MSKDAT3 |EPWM Mask Data Bit + * | | |This data bit control the state of EPWMn output pin, if corresponding mask function is enabled. + * | | |0 = Output logic low to EPWM channel n. + * | | |1 = Output logic high to EPWM channel n. + * |[4] |MSKDAT4 |EPWM Mask Data Bit + * | | |This data bit control the state of EPWMn output pin, if corresponding mask function is enabled. + * | | |0 = Output logic low to EPWM channel n. + * | | |1 = Output logic high to EPWM channel n. + * |[5] |MSKDAT5 |EPWM Mask Data Bit + * | | |This data bit control the state of EPWMn output pin, if corresponding mask function is enabled. + * | | |0 = Output logic low to EPWM channel n. + * | | |1 = Output logic high to EPWM channel n. + * @var EPWM_T::BNF + * Offset: 0xC0 EPWM Brake Noise Filter Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[0] |BRK0NFEN |EPWM Brake 0 Noise Filter Enable Bit + * | | |0 = Noise filter of EPWM Brake 0 Disabled. + * | | |1 = Noise filter of EPWM Brake 0 Enabled. + * |[3:1] |BRK0NFSEL |Brake 0 Edge Detector Filter Clock Selection + * | | |000 = Filter clock = HCLK. + * | | |001 = Filter clock = HCLK/2. + * | | |010 = Filter clock = HCLK/4. + * | | |011 = Filter clock = HCLK/8. + * | | |100 = Filter clock = HCLK/16. + * | | |101 = Filter clock = HCLK/32. + * | | |110 = Filter clock = HCLK/64. + * | | |111 = Filter clock = HCLK/128. + * |[6:4] |BRK0FCNT |Brake 0 Edge Detector Filter Count + * | | |The register bits control the Brake0 filter counter to count from 0 to BRK0FCNT. + * |[7] |BRK0PINV |Brake 0 Pin Inverse + * | | |0 = brake pin event will be detected if EPWMx BRAKE0 pin status transfer from low to high in edge-detect, or pin status is high in level-detect. + * | | |1 = brake pin event will be detected if EPWMx BRAKE0 pin status transfer from high to low in edge-detect, or pin status is low in level-detect. + * |[8] |BRK1NFEN |EPWM Brake 1 Noise Filter Enable Bit + * | | |0 = Noise filter of EPWM Brake 1 Disabled. + * | | |1 = Noise filter of EPWM Brake 1 Enabled. + * |[11:9] |BRK1NFSEL |Brake 1 Edge Detector Filter Clock Selection + * | | |000 = Filter clock = HCLK. + * | | |001 = Filter clock = HCLK/2. + * | | |010 = Filter clock = HCLK/4. + * | | |011 = Filter clock = HCLK/8. + * | | |100 = Filter clock = HCLK/16. + * | | |101 = Filter clock = HCLK/32. + * | | |110 = Filter clock = HCLK/64. + * | | |111 = Filter clock = HCLK/128. + * |[14:12] |BRK1FCNT |Brake 1 Edge Detector Filter Count + * | | |The register bits control the Brake1 filter counter to count from 0 to BRK1FCNT. + * |[15] |BRK1PINV |Brake 1 Pin Inverse + * | | |0 = brake pin event will be detected if EPWMx BRAKE1 pin status transfer from low to high in edge-detect, or pin status is high in level-detect. + * | | |1 = brake pin event will be detected if EPWMx BRAKE1 pin status transfer from high to low in edge-detect, or pin status is low in level-detect. + * |[17:16] |BK0SRC |Brake 0 Pin Source Select + * | | |For EPWM0 setting: + * | | |0 = Brake 0 pin source come from EPWM0_BRAKE0. + * | | |1 = Brake 0 pin source come from EPWM1_BRAKE0. + * | | |2 = Brake 0 pin source come from EPWM2_BRAKE0. + * | | |For EPWM1 setting: + * | | |0 = Brake 0 pin source come from EPWM1_BRAKE0. + * | | |1 = Brake 0 pin source come from EPWM0_BRAKE0. + * | | |2 = Brake 1 pin source come from EPWM2_BRAKE0. + * | | |For EPWM2 setting: + * | | |0 = Brake 0 pin source come from EPWM2_BRAKE0. + * | | |1 = Brake 0 pin source come from EPWM0_BRAKE0. + * | | |2 = Brake 1 pin source come from EPWM1_BRAKE0. + * |[25:24] |BK1SRC |Brake 1 Pin Source Select + * | | |For EPWM0 setting: + * | | |0 = Brake 1 pin source come from EPWM0_BRAKE1. + * | | |1 = Brake 1 pin source come from EPWM1_BRAKE1. + * | | |2 = Brake 1 pin source come from EPWM2_BRAKE1. + * | | |For EPWM1 setting: + * | | |0 = Brake 1 pin source come from EPWM1_BRAKE1. + * | | |1 = Brake 1 pin source come from EPWM0_BRAKE1. + * | | |2 = Brake 1 pin source come from EPWM2_BRAKE1. + * | | |For EPWM2 setting: + * | | |0 = Brake 1 pin source come from EPWM2_BRAKE1. + * | | |1 = Brake 1 pin source come from EPWM0_BRAKE1. + * | | |2 = Brake 1 pin source come from EPWM1_BRAKE1. + * @var EPWM_T::FAILBRK + * Offset: 0xC4 EPWM System Fail Brake Control Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[0] |CSSBRKEN |Clock Security System Detection Trigger EPWM Brake Function 0 Enable Bit + * | | |0 = Brake Function triggered by CSS detection Disabled. + * | | |1 = Brake Function triggered by CSS detection Enabled. + * |[1] |LVDBRKEN |Low Voltage Interrupt Flag Detection Trigger EPWM Brake Function 0 Enable Bit + * | | |0 = Brake Function triggered by LVD Disabled. + * | | |1 = Brake Function triggered by LVD Enabled. + * |[3] |CORBRKEN |Core Lockup Detection Trigger EPWM Brake Function 0 Enable Bit + * | | |0 = Brake Function triggered by Core lockup detection Disabled. + * | | |1 = Brake Function triggered by Core lockup detection Enabled. + * @var EPWM_T::BRKCTL0_1 + * Offset: 0xC8 EPWM Brake Edge Detect Control Register 0/1 + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[4] |BRKP0EEN |Enable EPWMx_BRAKE0 Pin As Edge-detect Brake Source (Write Protect) + * | | |0 = EPWMx_BRAKE0 pin as edge-detect brake source Disabled. + * | | |1 = EPWMx_BRAKE0 pin as edge-detect brake source Enabled. + * | | |Note: This bit is write protected + * | | |Refer to the SYS_RLKTZS register or SYS_RLKTZNS register or SYS_RLKSUBM register. + * |[5] |BRKP1EEN |Enable EPWMx_BRAKE1 Pin As Edge-detect Brake Source (Write Protect) + * | | |0 = EPWMx_BRAKE1 pin as edge-detect brake source Disabled. + * | | |1 = EPWMx_BRAKE1 pin as edge-detect brake source Enabled. + * | | |Note: This bit is write protected + * | | |Refer to the SYS_RLKTZS register or SYS_RLKTZNS register or SYS_RLKSUBM register. + * |[7] |SYSEBEN |Enable System Fail As Edge-detect Brake Source (Write Protect) + * | | |0 = System Fail condition as edge-detect brake source Disabled. + * | | |1 = System Fail condition as edge-detect brake source Enabled. + * | | |Note: This bit is write protected + * | | |Refer to the SYS_RLKTZS register or SYS_RLKTZNS register or SYS_RLKSUBM register. + * |[12] |BRKP0LEN |Enable BKP0 Pin As Level-detect Brake Source (Write Protect) + * | | |0 = EPWMx_BRAKE0 pin as level-detect brake source Disabled. + * | | |1 = EPWMx_BRAKE0 pin as level-detect brake source Enabled. + * | | |Note: This bit is write protected + * | | |Refer to the SYS_RLKTZS register or SYS_RLKTZNS register or SYS_RLKSUBM register. + * |[13] |BRKP1LEN |Enable BKP1 Pin As Level-detect Brake Source (Write Protect) + * | | |0 = EPWMx_BRAKE1 pin as level-detect brake source Disabled. + * | | |1 = EPWMx_BRAKE1 pin as level-detect brake source Enabled. + * | | |Note: This bit is write protected + * | | |Refer to the SYS_RLKTZS register or SYS_RLKTZNS register or SYS_RLKSUBM register. + * |[15] |SYSLBEN |Enable System Fail As Level-detect Brake Source (Write Protect) + * | | |0 = System Fail condition as level-detect brake source Disabled. + * | | |1 = System Fail condition as level-detect brake source Enabled. + * | | |Note: This bit is write protected + * | | |Refer to the SYS_RLKTZS register or SYS_RLKTZNS register or SYS_RLKSUBM register. + * |[17:16] |BRKAEVEN |EPWM Brake Action Select for Even Channel (Write Protect) + * | | |00 = EPWMx brake event will not affect even channels output. + * | | |01 = EPWM even channel output tri-state when EPWMx brake event happened. + * | | |10 = EPWM even channel output low level when EPWMx brake event happened. + * | | |11 = EPWM even channel output high level when EPWMx brake event happened. + * | | |Note: This bit is write protected + * | | |Refer to the SYS_RLKTZS register or SYS_RLKTZNS register or SYS_RLKSUBM register. + * |[19:18] |BRKAODD |EPWM Brake Action Select for Odd Channel (Write Protect) + * | | |00 = EPWMx brake event will not affect odd channels output. + * | | |01 = EPWM odd channel output tri-state when EPWMx brake event happened. + * | | |10 = EPWM odd channel output low level when EPWMx brake event happened. + * | | |11 = EPWM odd channel output high level when EPWMx brake event happened. + * | | |Note: This bit is write protected + * | | |Refer to the SYS_RLKTZS register or SYS_RLKTZNS register or SYS_RLKSUBM register + * |[20] |EADCEBEN |Enable EADC Result Monitor As Edge-detect Brake Source (Write Protect) + * | | |0 = EADCRM as edge-detect brake source Disabled. + * | | |1 = EADCRM as edge-detect brake source Enabled. + * | | |Note: This bit is write protected + * | | |Refer to the SYS_RLKTZS register or SYS_RLKTZNS register or SYS_RLKSUBM register + * |[28] |EADCLBEN |Enable EADC Result Monitor As Level-detect Brake Source (Write Protect) + * | | |0 = EADCRM as level-detect brake source Disabled. + * | | |1 = EADCRM as level-detect brake source Enabled. + * | | |Note: This bit is write protected + * | | |Refer to the SYS_RLKTZS register or SYS_RLKTZNS register or SYS_RLKSUBM register + * @var EPWM_T::BRKCTL2_3 + * Offset: 0xCC EPWM Brake Edge Detect Control Register 2/3 + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[4] |BRKP0EEN |Enable EPWMx_BRAKE0 Pin As Edge-detect Brake Source (Write Protect) + * | | |0 = EPWMx_BRAKE0 pin as edge-detect brake source Disabled. + * | | |1 = EPWMx_BRAKE0 pin as edge-detect brake source Enabled. + * | | |Note: This bit is write protected + * | | |Refer to the SYS_RLKTZS register or SYS_RLKTZNS register or SYS_RLKSUBM register. + * |[5] |BRKP1EEN |Enable EPWMx_BRAKE1 Pin As Edge-detect Brake Source (Write Protect) + * | | |0 = EPWMx_BRAKE1 pin as edge-detect brake source Disabled. + * | | |1 = EPWMx_BRAKE1 pin as edge-detect brake source Enabled. + * | | |Note: This bit is write protected + * | | |Refer to the SYS_RLKTZS register or SYS_RLKTZNS register or SYS_RLKSUBM register. + * |[7] |SYSEBEN |Enable System Fail As Edge-detect Brake Source (Write Protect) + * | | |0 = System Fail condition as edge-detect brake source Disabled. + * | | |1 = System Fail condition as edge-detect brake source Enabled. + * | | |Note: This bit is write protected + * | | |Refer to the SYS_RLKTZS register or SYS_RLKTZNS register or SYS_RLKSUBM register. + * |[12] |BRKP0LEN |Enable BKP0 Pin As Level-detect Brake Source (Write Protect) + * | | |0 = EPWMx_BRAKE0 pin as level-detect brake source Disabled. + * | | |1 = EPWMx_BRAKE0 pin as level-detect brake source Enabled. + * | | |Note: This bit is write protected + * | | |Refer to the SYS_RLKTZS register or SYS_RLKTZNS register or SYS_RLKSUBM register. + * |[13] |BRKP1LEN |Enable BKP1 Pin As Level-detect Brake Source (Write Protect) + * | | |0 = EPWMx_BRAKE1 pin as level-detect brake source Disabled. + * | | |1 = EPWMx_BRAKE1 pin as level-detect brake source Enabled. + * | | |Note: This bit is write protected + * | | |Refer to the SYS_RLKTZS register or SYS_RLKTZNS register or SYS_RLKSUBM register. + * |[15] |SYSLBEN |Enable System Fail As Level-detect Brake Source (Write Protect) + * | | |0 = System Fail condition as level-detect brake source Disabled. + * | | |1 = System Fail condition as level-detect brake source Enabled. + * | | |Note: This bit is write protected + * | | |Refer to the SYS_RLKTZS register or SYS_RLKTZNS register or SYS_RLKSUBM register. + * |[17:16] |BRKAEVEN |EPWM Brake Action Select for Even Channel (Write Protect) + * | | |00 = EPWMx brake event will not affect even channels output. + * | | |01 = EPWM even channel output tri-state when EPWMx brake event happened. + * | | |10 = EPWM even channel output low level when EPWMx brake event happened. + * | | |11 = EPWM even channel output high level when EPWMx brake event happened. + * | | |Note: This bit is write protected + * | | |Refer to the SYS_RLKTZS register or SYS_RLKTZNS register or SYS_RLKSUBM register. + * |[19:18] |BRKAODD |EPWM Brake Action Select for Odd Channel (Write Protect) + * | | |00 = EPWMx brake event will not affect odd channels output. + * | | |01 = EPWM odd channel output tri-state when EPWMx brake event happened. + * | | |10 = EPWM odd channel output low level when EPWMx brake event happened. + * | | |11 = EPWM odd channel output high level when EPWMx brake event happened. + * | | |Note: This bit is write protected + * | | |Refer to the SYS_RLKTZS register or SYS_RLKTZNS register or SYS_RLKSUBM register + * |[20] |EADCEBEN |Enable EADC Result Monitor As Edge-detect Brake Source (Write Protect) + * | | |0 = EADCRM as edge-detect brake source Disabled. + * | | |1 = EADCRM as edge-detect brake source Enabled. + * | | |Note: This bit is write protected + * | | |Refer to the SYS_RLKTZS register or SYS_RLKTZNS register or SYS_RLKSUBM register + * |[28] |EADCLBEN |Enable EADC Result Monitor As Level-detect Brake Source (Write Protect) + * | | |0 = EADCRM as level-detect brake source Disabled. + * | | |1 = EADCRM as level-detect brake source Enabled. + * | | |Note: This bit is write protected + * | | |Refer to the SYS_RLKTZS register or SYS_RLKTZNS register or SYS_RLKSUBM register + * @var EPWM_T::BRKCTL4_5 + * Offset: 0xD0 EPWM Brake Edge Detect Control Register 4/5 + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[4] |BRKP0EEN |Enable EPWMx_BRAKE0 Pin As Edge-detect Brake Source (Write Protect) + * | | |0 = EPWMx_BRAKE0 pin as edge-detect brake source Disabled. + * | | |1 = EPWMx_BRAKE0 pin as edge-detect brake source Enabled. + * | | |Note: This bit is write protected + * | | |Refer to the SYS_RLKTZS register or SYS_RLKTZNS register or SYS_RLKSUBM register. + * |[5] |BRKP1EEN |Enable EPWMx_BRAKE1 Pin As Edge-detect Brake Source (Write Protect) + * | | |0 = EPWMx_BRAKE1 pin as edge-detect brake source Disabled. + * | | |1 = EPWMx_BRAKE1 pin as edge-detect brake source Enabled. + * | | |Note: This bit is write protected + * | | |Refer to the SYS_RLKTZS register or SYS_RLKTZNS register or SYS_RLKSUBM register. + * |[7] |SYSEBEN |Enable System Fail As Edge-detect Brake Source (Write Protect) + * | | |0 = System Fail condition as edge-detect brake source Disabled. + * | | |1 = System Fail condition as edge-detect brake source Enabled. + * | | |Note: This bit is write protected + * | | |Refer to the SYS_RLKTZS register or SYS_RLKTZNS register or SYS_RLKSUBM register. + * |[12] |BRKP0LEN |Enable BKP0 Pin As Level-detect Brake Source (Write Protect) + * | | |0 = EPWMx_BRAKE0 pin as level-detect brake source Disabled. + * | | |1 = EPWMx_BRAKE0 pin as level-detect brake source Enabled. + * | | |Note: This bit is write protected + * | | |Refer to the SYS_RLKTZS register or SYS_RLKTZNS register or SYS_RLKSUBM register. + * |[13] |BRKP1LEN |Enable BKP1 Pin As Level-detect Brake Source (Write Protect) + * | | |0 = EPWMx_BRAKE1 pin as level-detect brake source Disabled. + * | | |1 = EPWMx_BRAKE1 pin as level-detect brake source Enabled. + * | | |Note: This bit is write protected + * | | |Refer to the SYS_RLKTZS register or SYS_RLKTZNS register or SYS_RLKSUBM register. + * |[15] |SYSLBEN |Enable System Fail As Level-detect Brake Source (Write Protect) + * | | |0 = System Fail condition as level-detect brake source Disabled. + * | | |1 = System Fail condition as level-detect brake source Enabled. + * | | |Note: This bit is write protected + * | | |Refer to the SYS_RLKTZS register or SYS_RLKTZNS register or SYS_RLKSUBM register. + * |[17:16] |BRKAEVEN |EPWM Brake Action Select for Even Channel (Write Protect) + * | | |00 = EPWMx brake event will not affect even channels output. + * | | |01 = EPWM even channel output tri-state when EPWMx brake event happened. + * | | |10 = EPWM even channel output low level when EPWMx brake event happened. + * | | |11 = EPWM even channel output high level when EPWMx brake event happened. + * | | |Note: This bit is write protected + * | | |Refer to the SYS_RLKTZS register or SYS_RLKTZNS register or SYS_RLKSUBM register. + * |[19:18] |BRKAODD |EPWM Brake Action Select for Odd Channel (Write Protect) + * | | |00 = EPWMx brake event will not affect odd channels output. + * | | |01 = EPWM odd channel output tri-state when EPWMx brake event happened. + * | | |10 = EPWM odd channel output low level when EPWMx brake event happened. + * | | |11 = EPWM odd channel output high level when EPWMx brake event happened. + * | | |Note: This bit is write protected + * | | |Refer to the SYS_RLKTZS register or SYS_RLKTZNS register or SYS_RLKSUBM register + * |[20] |EADCEBEN |Enable EADC Result Monitor As Edge-detect Brake Source (Write Protect) + * | | |0 = EADCRM as edge-detect brake source Disabled. + * | | |1 = EADCRM as edge-detect brake source Enabled. + * | | |Note: This bit is write protected + * | | |Refer to the SYS_RLKTZS register or SYS_RLKTZNS register or SYS_RLKSUBM register + * |[28] |EADCLBEN |Enable EADC Result Monitor As Level-detect Brake Source (Write Protect) + * | | |0 = EADCRM as level-detect brake source Disabled. + * | | |1 = EADCRM as level-detect brake source Enabled. + * | | |Note: This bit is write protected + * | | |Refer to the SYS_RLKTZS register or SYS_RLKTZNS register or SYS_RLKSUBM register + * @var EPWM_T::POLCTL + * Offset: 0xD4 EPWM Pin Polar Inverse Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[0] |PINV0 |EPWM PIN Polar Inverse Control + * | | |The register controls polarity state of EPWMx_CHn output pin. + * | | |0 = EPWMx_CHn output pin polar inverse Disabled. + * | | |1 = EPWMx_CHn output pin polar inverse Enabled. + * |[1] |PINV1 |EPWM PIN Polar Inverse Control + * | | |The register controls polarity state of EPWMx_CHn output pin. + * | | |0 = EPWMx_CHn output pin polar inverse Disabled. + * | | |1 = EPWMx_CHn output pin polar inverse Enabled. + * |[2] |PINV2 |EPWM PIN Polar Inverse Control + * | | |The register controls polarity state of EPWMx_CHn output pin. + * | | |0 = EPWMx_CHn output pin polar inverse Disabled. + * | | |1 = EPWMx_CHn output pin polar inverse Enabled. + * |[3] |PINV3 |EPWM PIN Polar Inverse Control + * | | |The register controls polarity state of EPWMx_CHn output pin. + * | | |0 = EPWMx_CHn output pin polar inverse Disabled. + * | | |1 = EPWMx_CHn output pin polar inverse Enabled. + * |[4] |PINV4 |EPWM PIN Polar Inverse Control + * | | |The register controls polarity state of EPWMx_CHn output pin. + * | | |0 = EPWMx_CHn output pin polar inverse Disabled. + * | | |1 = EPWMx_CHn output pin polar inverse Enabled. + * |[5] |PINV5 |EPWM PIN Polar Inverse Control + * | | |The register controls polarity state of EPWMx_CHn output pin. + * | | |0 = EPWMx_CHn output pin polar inverse Disabled. + * | | |1 = EPWMx_CHn output pin polar inverse Enabled. + * @var EPWM_T::POEN + * Offset: 0xD8 EPWM Output Enable Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[0] |POEN0 |EPWM Pin Output Enable Bits + * | | |0 = EPWMx_CHn pin at tri-state. + * | | |1 = EPWMx_CHn pin in output mode. + * |[1] |POEN1 |EPWM Pin Output Enable Bits + * | | |0 = EPWMx_CHn pin at tri-state. + * | | |1 = EPWMx_CHn pin in output mode. + * |[2] |POEN2 |EPWM Pin Output Enable Bits + * | | |0 = EPWMx_CHn pin at tri-state. + * | | |1 = EPWMx_CHn pin in output mode. + * |[3] |POEN3 |EPWM Pin Output Enable Bits + * | | |0 = EPWMx_CHn pin at tri-state. + * | | |1 = EPWMx_CHn pin in output mode. + * |[4] |POEN4 |EPWM Pin Output Enable Bits + * | | |0 = EPWMx_CHn pin at tri-state. + * | | |1 = EPWMx_CHn pin in output mode. + * |[5] |POEN5 |EPWM Pin Output Enable Bits + * | | |0 = EPWMx_CHn pin at tri-state. + * | | |1 = EPWMx_CHn pin in output mode. + * @var EPWM_T::SWBRK + * Offset: 0xDC EPWM Software Brake Control Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[0] |BRKETRG0 |EPWM Edge Brake Software Trigger (Write Only) (Write Protect) + * | | |Write 1 to this bit will trigger edge brake, and set BRKEIFn to 1 in EPWM_INTSTS1 register. + * | | |Note: This bit is write protected + * | | |Refer to the SYS_RLKTZS register or SYS_RLKTZNS register or SYS_RLKSUBM register. + * |[1] |BRKETRG2 |EPWM Edge Brake Software Trigger (Write Only) (Write Protect) + * | | |Write 1 to this bit will trigger edge brake, and set BRKEIFn to 1 in EPWM_INTSTS1 register. + * | | |Note: This bit is write protected + * | | |Refer to the SYS_RLKTZS register or SYS_RLKTZNS register or SYS_RLKSUBM register. + * |[2] |BRKETRG4 |EPWM Edge Brake Software Trigger (Write Only) (Write Protect) + * | | |Write 1 to this bit will trigger edge brake, and set BRKEIFn to 1 in EPWM_INTSTS1 register. + * | | |Note: This bit is write protected + * | | |Refer to the SYS_RLKTZS register or SYS_RLKTZNS register or SYS_RLKSUBM register. + * |[8] |BRKLTRG0 |EPWM Level Brake Software Trigger (Write Only) (Write Protect) + * | | |Write 1 to this bit will trigger level brake, and set BRKLIFn to 1 in EPWM_INTSTS1 register. + * | | |Note: This bit is write protected + * | | |Refer to the SYS_RLKTZS register or SYS_RLKTZNS register or SYS_RLKSUBM register. + * |[9] |BRKLTRG2 |EPWM Level Brake Software Trigger (Write Only) (Write Protect) + * | | |Write 1 to this bit will trigger level brake, and set BRKLIFn to 1 in EPWM_INTSTS1 register. + * | | |Note: This bit is write protected + * | | |Refer to the SYS_RLKTZS register or SYS_RLKTZNS register or SYS_RLKSUBM register. + * |[10] |BRKLTRG4 |EPWM Level Brake Software Trigger (Write Only) (Write Protect) + * | | |Write 1 to this bit will trigger level brake, and set BRKLIFn to 1 in EPWM_INTSTS1 register. + * | | |Note: This bit is write protected + * | | |Refer to the SYS_RLKTZS register or SYS_RLKTZNS register or SYS_RLKSUBM register. + * @var EPWM_T::INTEN0 + * Offset: 0xE0 EPWM Interrupt Enable Register 0 + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[0] |ZIEN0 |EPWM Zero Point Interrupt Enable Bits + * | | |0 = Zero point interrupt Disabled. + * | | |1 = Zero point interrupt Enabled. + * | | |Note: Odd channels will read always 0 at complementary mode. + * |[1] |ZIEN1 |EPWM Zero Point Interrupt Enable Bits + * | | |0 = Zero point interrupt Disabled. + * | | |1 = Zero point interrupt Enabled. + * | | |Note: Odd channels will read always 0 at complementary mode. + * |[2] |ZIEN2 |EPWM Zero Point Interrupt Enable Bits + * | | |0 = Zero point interrupt Disabled. + * | | |1 = Zero point interrupt Enabled. + * | | |Note: Odd channels will read always 0 at complementary mode. + * |[3] |ZIEN3 |EPWM Zero Point Interrupt Enable Bits + * | | |0 = Zero point interrupt Disabled. + * | | |1 = Zero point interrupt Enabled. + * | | |Note: Odd channels will read always 0 at complementary mode. + * |[4] |ZIEN4 |EPWM Zero Point Interrupt Enable Bits + * | | |0 = Zero point interrupt Disabled. + * | | |1 = Zero point interrupt Enabled. + * | | |Note: Odd channels will read always 0 at complementary mode. + * |[5] |ZIEN5 |EPWM Zero Point Interrupt Enable Bits + * | | |0 = Zero point interrupt Disabled. + * | | |1 = Zero point interrupt Enabled. + * | | |Note: Odd channels will read always 0 at complementary mode. + * |[8] |PIEN0 |EPWM Period Point Interrupt Enable Bits + * | | |0 = Period point interrupt Disabled. + * | | |1 = Period point interrupt Enabled. + * | | |Note 1: When up-down counter type period point means center point. + * | | |Note 2: Odd channels will read always 0 at complementary mode. + * |[9] |PIEN1 |EPWM Period Point Interrupt Enable Bits + * | | |0 = Period point interrupt Disabled. + * | | |1 = Period point interrupt Enabled. + * | | |Note 1: When up-down counter type period point means center point. + * | | |Note 2: Odd channels will read always 0 at complementary mode. + * |[10] |PIEN2 |EPWM Period Point Interrupt Enable Bits + * | | |0 = Period point interrupt Disabled. + * | | |1 = Period point interrupt Enabled. + * | | |Note 1: When up-down counter type period point means center point. + * | | |Note 2: Odd channels will read always 0 at complementary mode. + * |[11] |PIEN3 |EPWM Period Point Interrupt Enable Bits + * | | |0 = Period point interrupt Disabled. + * | | |1 = Period point interrupt Enabled. + * | | |Note 1: When up-down counter type period point means center point. + * | | |Note 2: Odd channels will read always 0 at complementary mode. + * |[12] |PIEN4 |EPWM Period Point Interrupt Enable Bits + * | | |0 = Period point interrupt Disabled. + * | | |1 = Period point interrupt Enabled. + * | | |Note 1: When up-down counter type period point means center point. + * | | |Note 2: Odd channels will read always 0 at complementary mode. + * |[13] |PIEN5 |EPWM Period Point Interrupt Enable Bits + * | | |0 = Period point interrupt Disabled. + * | | |1 = Period point interrupt Enabled. + * | | |Note 1: When up-down counter type period point means center point. + * | | |Note 2: Odd channels will read always 0 at complementary mode. + * |[16] |CMPUIEN0 |EPWM Compare Up Count Interrupt Enable Bits + * | | |0 = Compare up count interrupt Disabled. + * | | |1 = Compare up count interrupt Enabled. + * | | |Note: In complementary mode, CMPUIEN1, 3, 5 is used as another CMPUIEN for channel 0, 2, 4. + * |[17] |CMPUIEN1 |EPWM Compare Up Count Interrupt Enable Bits + * | | |0 = Compare up count interrupt Disabled. + * | | |1 = Compare up count interrupt Enabled. + * | | |Note: In complementary mode, CMPUIEN1, 3, 5 is used as another CMPUIEN for channel 0, 2, 4. + * |[18] |CMPUIEN2 |EPWM Compare Up Count Interrupt Enable Bits + * | | |0 = Compare up count interrupt Disabled. + * | | |1 = Compare up count interrupt Enabled. + * | | |Note: In complementary mode, CMPUIEN1, 3, 5 is used as another CMPUIEN for channel 0, 2, 4. + * |[19] |CMPUIEN3 |EPWM Compare Up Count Interrupt Enable Bits + * | | |0 = Compare up count interrupt Disabled. + * | | |1 = Compare up count interrupt Enabled. + * | | |Note: In complementary mode, CMPUIEN1, 3, 5 is used as another CMPUIEN for channel 0, 2, 4. + * |[20] |CMPUIEN4 |EPWM Compare Up Count Interrupt Enable Bits + * | | |0 = Compare up count interrupt Disabled. + * | | |1 = Compare up count interrupt Enabled. + * | | |Note: In complementary mode, CMPUIEN1, 3, 5 is used as another CMPUIEN for channel 0, 2, 4. + * |[21] |CMPUIEN5 |EPWM Compare Up Count Interrupt Enable Bits + * | | |0 = Compare up count interrupt Disabled. + * | | |1 = Compare up count interrupt Enabled. + * | | |Note: In complementary mode, CMPUIEN1, 3, 5 is used as another CMPUIEN for channel 0, 2, 4. + * |[24] |CMPDIEN0 |EPWM Compare Down Count Interrupt Enable Bits + * | | |0 = Compare down count interrupt Disabled. + * | | |1 = Compare down count interrupt Enabled. + * | | |Note: In complementary mode, CMPDIEN1, 3, 5 is used as another CMPDIEN for channel 0, 2, 4. + * |[25] |CMPDIEN1 |EPWM Compare Down Count Interrupt Enable Bits + * | | |0 = Compare down count interrupt Disabled. + * | | |1 = Compare down count interrupt Enabled. + * | | |Note: In complementary mode, CMPDIEN1, 3, 5 is used as another CMPDIEN for channel 0, 2, 4. + * |[26] |CMPDIEN2 |EPWM Compare Down Count Interrupt Enable Bits + * | | |0 = Compare down count interrupt Disabled. + * | | |1 = Compare down count interrupt Enabled. + * | | |Note: In complementary mode, CMPDIEN1, 3, 5 is used as another CMPDIEN for channel 0, 2, 4. + * |[27] |CMPDIEN3 |EPWM Compare Down Count Interrupt Enable Bits + * | | |0 = Compare down count interrupt Disabled. + * | | |1 = Compare down count interrupt Enabled. + * | | |Note: In complementary mode, CMPDIEN1, 3, 5 is used as another CMPDIEN for channel 0, 2, 4. + * |[28] |CMPDIEN4 |EPWM Compare Down Count Interrupt Enable Bits + * | | |0 = Compare down count interrupt Disabled. + * | | |1 = Compare down count interrupt Enabled. + * | | |Note: In complementary mode, CMPDIEN1, 3, 5 is used as another CMPDIEN for channel 0, 2, 4. + * |[29] |CMPDIEN5 |EPWM Compare Down Count Interrupt Enable Bits + * | | |0 = Compare down count interrupt Disabled. + * | | |1 = Compare down count interrupt Enabled. + * | | |Note: In complementary mode, CMPDIEN1, 3, 5 is used as another CMPDIEN for channel 0, 2, 4. + * @var EPWM_T::INTEN1 + * Offset: 0xE4 EPWM Interrupt Enable Register 1 + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[0] |BRKEIEN0_1|EPWM Edge-detect Brake Interrupt Enable for Channel0/1 (Write Protect) + * | | |0 = Edge-detect Brake interrupt for channel0/1 Disabled. + * | | |1 = Edge-detect Brake interrupt for channel0/1 Enabled. + * | | |Note: This bit is write protected + * | | |Refer to the SYS_RLKTZS register or SYS_RLKTZNS register or SYS_RLKSUBM register. + * |[1] |BRKEIEN2_3|EPWM Edge-detect Brake Interrupt Enable for Channel2/3 (Write Protect) + * | | |0 = Edge-detect Brake interrupt for channel2/3 Disabled. + * | | |1 = Edge-detect Brake interrupt for channel2/3 Enabled. + * | | |Note: This bit is write protected + * | | |Refer to the SYS_RLKTZS register or SYS_RLKTZNS register or SYS_RLKSUBM register. + * |[2] |BRKEIEN4_5|EPWM Edge-detect Brake Interrupt Enable for Channel4/5 (Write Protect) + * | | |0 = Edge-detect Brake interrupt for channel4/5 Disabled. + * | | |1 = Edge-detect Brake interrupt for channel4/5 Enabled. + * | | |Note: This bit is write protected + * | | |Refer to the SYS_RLKTZS register or SYS_RLKTZNS register or SYS_RLKSUBM register. + * |[8] |BRKLIEN0_1|EPWM Level-detect Brake Interrupt Enable for Channel0/1 (Write Protect) + * | | |0 = Level-detect Brake interrupt for channel0/1 Disabled. + * | | |1 = Level-detect Brake interrupt for channel0/1 Enabled. + * | | |Note: This bit is write protected + * | | |Refer to the SYS_RLKTZS register or SYS_RLKTZNS register or SYS_RLKSUBM register. + * |[9] |BRKLIEN2_3|EPWM Level-detect Brake Interrupt Enable for Channel2/3 (Write Protect) + * | | |0 = Level-detect Brake interrupt for channel2/3 Disabled. + * | | |1 = Level-detect Brake interrupt for channel2/3 Enabled. + * | | |Note: This bit is write protected + * | | |Refer to the SYS_RLKTZS register or SYS_RLKTZNS register or SYS_RLKSUBM register. + * |[10] |BRKLIEN4_5|EPWM Level-detect Brake Interrupt Enable for Channel4/5 (Write Protect) + * | | |0 = Level-detect Brake interrupt for channel4/5 Disabled. + * | | |1 = Level-detect Brake interrupt for channel4/5 Enabled. + * | | |Note: This bit is write protected + * | | |Refer to the SYS_RLKTZS register or SYS_RLKTZNS register or SYS_RLKSUBM register. + * @var EPWM_T::INTSTS0 + * Offset: 0xE8 EPWM Interrupt Flag Register 0 + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[0] |ZIF0 |EPWM Zero Point Interrupt Flag + * | | |This bit is set by hardware when EPWM counter reaches 0. + * | | |Note: This bit can be cleared to 0 by software writing 1 + * |[1] |ZIF1 |EPWM Zero Point Interrupt Flag + * | | |This bit is set by hardware when EPWM counter reaches 0. + * | | |Note: This bit can be cleared to 0 by software writing 1 + * |[2] |ZIF2 |EPWM Zero Point Interrupt Flag + * | | |This bit is set by hardware when EPWM counter reaches 0. + * | | |Note: This bit can be cleared to 0 by software writing 1 + * |[3] |ZIF3 |EPWM Zero Point Interrupt Flag + * | | |This bit is set by hardware when EPWM counter reaches 0. + * | | |Note: This bit can be cleared to 0 by software writing 1 + * |[4] |ZIF4 |EPWM Zero Point Interrupt Flag + * | | |This bit is set by hardware when EPWM counter reaches 0. + * | | |Note: This bit can be cleared to 0 by software writing 1 + * |[5] |ZIF5 |EPWM Zero Point Interrupt Flag + * | | |This bit is set by hardware when EPWM counter reaches 0. + * | | |Note: This bit can be cleared to 0 by software writing 1 + * |[8] |PIF0 |EPWM Period Point Interrupt Flag + * | | |This bit is set by hardware when EPWM counter reaches EPWM_PERIODn. + * | | |Note: This bit can be cleared to 0 by software writing 1. + * |[9] |PIF1 |EPWM Period Point Interrupt Flag + * | | |This bit is set by hardware when EPWM counter reaches EPWM_PERIODn. + * | | |Note: This bit can be cleared to 0 by software writing 1. + * |[10] |PIF2 |EPWM Period Point Interrupt Flag + * | | |This bit is set by hardware when EPWM counter reaches EPWM_PERIODn. + * | | |Note: This bit can be cleared to 0 by software writing 1. + * |[11] |PIF3 |EPWM Period Point Interrupt Flag + * | | |This bit is set by hardware when EPWM counter reaches EPWM_PERIODn. + * | | |Note: This bit can be cleared to 0 by software writing 1. + * |[12] |PIF4 |EPWM Period Point Interrupt Flag + * | | |This bit is set by hardware when EPWM counter reaches EPWM_PERIODn. + * | | |Note: This bit can be cleared to 0 by software writing 1. + * |[13] |PIF5 |EPWM Period Point Interrupt Flag + * | | |This bit is set by hardware when EPWM counter reaches EPWM_PERIODn. + * | | |Note: This bit can be cleared to 0 by software writing 1. + * |[16] |CMPUIF0 |EPWM Compare Up Count Interrupt Flag + * | | |Flag is set by hardware when EPWM counter up count and reaches EPWM_CMPDATn, software can clear this bit by writing 1 to it. + * | | |Note: In complementary mode, CMPUIF1, 3, 5 is used as another CMPUIF for channel 0, 2, 4. + * |[17] |CMPUIF1 |EPWM Compare Up Count Interrupt Flag + * | | |Flag is set by hardware when EPWM counter up count and reaches EPWM_CMPDATn, software can clear this bit by writing 1 to it. + * | | |Note: In complementary mode, CMPUIF1, 3, 5 is used as another CMPUIF for channel 0, 2, 4. + * |[18] |CMPUIF2 |EPWM Compare Up Count Interrupt Flag + * | | |Flag is set by hardware when EPWM counter up count and reaches EPWM_CMPDATn, software can clear this bit by writing 1 to it. + * | | |Note: In complementary mode, CMPUIF1, 3, 5 is used as another CMPUIF for channel 0, 2, 4. + * |[19] |CMPUIF3 |EPWM Compare Up Count Interrupt Flag + * | | |Flag is set by hardware when EPWM counter up count and reaches EPWM_CMPDATn, software can clear this bit by writing 1 to it. + * | | |Note: In complementary mode, CMPUIF1, 3, 5 is used as another CMPUIF for channel 0, 2, 4. + * |[20] |CMPUIF4 |EPWM Compare Up Count Interrupt Flag + * | | |Flag is set by hardware when EPWM counter up count and reaches EPWM_CMPDATn, software can clear this bit by writing 1 to it. + * | | |Note: In complementary mode, CMPUIF1, 3, 5 is used as another CMPUIF for channel 0, 2, 4. + * |[21] |CMPUIF5 |EPWM Compare Up Count Interrupt Flag + * | | |Flag is set by hardware when EPWM counter up count and reaches EPWM_CMPDATn, software can clear this bit by writing 1 to it. + * | | |Note: In complementary mode, CMPUIF1, 3, 5 is used as another CMPUIF for channel 0, 2, 4. + * |[24] |CMPDIF0 |EPWM Compare Down Count Interrupt Flag + * | | |Flag is set by hardware when EPWM counter down count and reaches EPWM_CMPDATn, software can clear this bit by writing 1 to it. + * | | |Note: In complementary mode, CMPDIF1, 3, 5 is used as another CMPDIF for channel 0, 2, 4. + * |[25] |CMPDIF1 |EPWM Compare Down Count Interrupt Flag + * | | |Flag is set by hardware when EPWM counter down count and reaches EPWM_CMPDATn, software can clear this bit by writing 1 to it. + * | | |Note: In complementary mode, CMPDIF1, 3, 5 is used as another CMPDIF for channel 0, 2, 4. + * |[26] |CMPDIF2 |EPWM Compare Down Count Interrupt Flag + * | | |Flag is set by hardware when EPWM counter down count and reaches EPWM_CMPDATn, software can clear this bit by writing 1 to it. + * | | |Note: In complementary mode, CMPDIF1, 3, 5 is used as another CMPDIF for channel 0, 2, 4. + * |[27] |CMPDIF3 |EPWM Compare Down Count Interrupt Flag + * | | |Flag is set by hardware when EPWM counter down count and reaches EPWM_CMPDATn, software can clear this bit by writing 1 to it. + * | | |Note: In complementary mode, CMPDIF1, 3, 5 is used as another CMPDIF for channel 0, 2, 4. + * |[28] |CMPDIF4 |EPWM Compare Down Count Interrupt Flag + * | | |Flag is set by hardware when EPWM counter down count and reaches EPWM_CMPDATn, software can clear this bit by writing 1 to it. + * | | |Note: In complementary mode, CMPDIF1, 3, 5 is used as another CMPDIF for channel 0, 2, 4. + * |[29] |CMPDIF5 |EPWM Compare Down Count Interrupt Flag + * | | |Flag is set by hardware when EPWM counter down count and reaches EPWM_CMPDATn, software can clear this bit by writing 1 to it. + * | | |Note: In complementary mode, CMPDIF1, 3, 5 is used as another CMPDIF for channel 0, 2, 4. + * @var EPWM_T::INTSTS1 + * Offset: 0xEC EPWM Interrupt Flag Register 1 + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[0] |BRKEIF0 |EPWM Channel n Edge-detect Brake Interrupt Flag (Write Protect) + * | | |0 = EPWM channel n edge-detect brake event do not happened. + * | | |1 = When EPWM channel n edge-detect brake event happened, this bit is set to 1, writing 1 to clear. + * | | |Note: This bit is write protected + * | | |Refer to the SYS_RLKTZS register or SYS_RLKTZNS register or SYS_RLKSUBM register. + * |[1] |BRKEIF1 |EPWM Channel n Edge-detect Brake Interrupt Flag (Write Protect) + * | | |0 = EPWM channel n edge-detect brake event do not happened. + * | | |1 = When EPWM channel n edge-detect brake event happened, this bit is set to 1, writing 1 to clear. + * | | |Note: This bit is write protected + * | | |Refer to the SYS_RLKTZS register or SYS_RLKTZNS register or SYS_RLKSUBM register. + * |[2] |BRKEIF2 |EPWM Channel n Edge-detect Brake Interrupt Flag (Write Protect) + * | | |0 = EPWM channel n edge-detect brake event do not happened. + * | | |1 = When EPWM channel n edge-detect brake event happened, this bit is set to 1, writing 1 to clear. + * | | |Note: This bit is write protected + * | | |Refer to the SYS_RLKTZS register or SYS_RLKTZNS register or SYS_RLKSUBM register. + * |[3] |BRKEIF3 |EPWM Channel n Edge-detect Brake Interrupt Flag (Write Protect) + * | | |0 = EPWM channel n edge-detect brake event do not happened. + * | | |1 = When EPWM channel n edge-detect brake event happened, this bit is set to 1, writing 1 to clear. + * | | |Note: This bit is write protected + * | | |Refer to the SYS_RLKTZS register or SYS_RLKTZNS register or SYS_RLKSUBM register. + * |[4] |BRKEIF4 |EPWM Channel n Edge-detect Brake Interrupt Flag (Write Protect) + * | | |0 = EPWM channel n edge-detect brake event do not happened. + * | | |1 = When EPWM channel n edge-detect brake event happened, this bit is set to 1, writing 1 to clear. + * | | |Note: This bit is write protected + * | | |Refer to the SYS_RLKTZS register or SYS_RLKTZNS register or SYS_RLKSUBM register. + * |[5] |BRKEIF5 |EPWM Channel n Edge-detect Brake Interrupt Flag (Write Protect) + * | | |0 = EPWM channel n edge-detect brake event do not happened. + * | | |1 = When EPWM channel n edge-detect brake event happened, this bit is set to 1, writing 1 to clear. + * | | |Note: This bit is write protected + * | | |Refer to the SYS_RLKTZS register or SYS_RLKTZNS register or SYS_RLKSUBM register. + * |[8] |BRKLIF0 |EPWM Channel n Level-detect Brake Interrupt Flag (Write Protect) + * | | |0 = EPWM channel n level-detect brake event do not happened. + * | | |1 = When EPWM channel n level-detect brake event happened, this bit is set to 1, writing 1 to clear. + * | | |Note: This bit is write protected + * | | |Refer to the SYS_RLKTZS register or SYS_RLKTZNS register or SYS_RLKSUBM register. + * |[9] |BRKLIF1 |EPWM Channel n Level-detect Brake Interrupt Flag (Write Protect) + * | | |0 = EPWM channel n level-detect brake event do not happened. + * | | |1 = When EPWM channel n level-detect brake event happened, this bit is set to 1, writing 1 to clear. + * | | |Note: This bit is write protected + * | | |Refer to the SYS_RLKTZS register or SYS_RLKTZNS register or SYS_RLKSUBM register. + * |[10] |BRKLIF2 |EPWM Channel n Level-detect Brake Interrupt Flag (Write Protect) + * | | |0 = EPWM channel n level-detect brake event do not happened. + * | | |1 = When EPWM channel n level-detect brake event happened, this bit is set to 1, writing 1 to clear. + * | | |Note: This bit is write protected + * | | |Refer to the SYS_RLKTZS register or SYS_RLKTZNS register or SYS_RLKSUBM register. + * |[11] |BRKLIF3 |EPWM Channel n Level-detect Brake Interrupt Flag (Write Protect) + * | | |0 = EPWM channel n level-detect brake event do not happened. + * | | |1 = When EPWM channel n level-detect brake event happened, this bit is set to 1, writing 1 to clear. + * | | |Note: This bit is write protected + * | | |Refer to the SYS_RLKTZS register or SYS_RLKTZNS register or SYS_RLKSUBM register. + * |[12] |BRKLIF4 |EPWM Channel n Level-detect Brake Interrupt Flag (Write Protect) + * | | |0 = EPWM channel n level-detect brake event do not happened. + * | | |1 = When EPWM channel n level-detect brake event happened, this bit is set to 1, writing 1 to clear. + * | | |Note: This bit is write protected + * | | |Refer to the SYS_RLKTZS register or SYS_RLKTZNS register or SYS_RLKSUBM register. + * |[13] |BRKLIF5 |EPWM Channel n Level-detect Brake Interrupt Flag (Write Protect) + * | | |0 = EPWM channel n level-detect brake event do not happened. + * | | |1 = When EPWM channel n level-detect brake event happened, this bit is set to 1, writing 1 to clear. + * | | |Note: This bit is write protected + * | | |Refer to the SYS_RLKTZS register or SYS_RLKTZNS register or SYS_RLKSUBM register. + * |[16] |BRKESTS0 |EPWM Channel n Edge-detect Brake Status (Read Only) + * | | |0 = EPWM channel n edge-detect brake state is released. + * | | |1 = When EPWM channel n edge-detect brake detects a falling edge of any enabled brake source; this flag will be set to indicate the EPWM channel n at brake state. + * | | |Note: This bit is read only and auto cleared by hardware + * | | |When edge-detect brake interrupt flag is cleared, EPWM will release brake state until current EPWM period finished + * | | |The EPWM waveform will start output from next full EPWM period. + * |[17] |BRKESTS1 |EPWM Channel n Edge-detect Brake Status (Read Only) + * | | |0 = EPWM channel n edge-detect brake state is released. + * | | |1 = When EPWM channel n edge-detect brake detects a falling edge of any enabled brake source; this flag will be set to indicate the EPWM channel n at brake state. + * | | |Note: This bit is read only and auto cleared by hardware + * | | |When edge-detect brake interrupt flag is cleared, EPWM will release brake state until current EPWM period finished + * | | |The EPWM waveform will start output from next full EPWM period. + * |[18] |BRKESTS2 |EPWM Channel n Edge-detect Brake Status (Read Only) + * | | |0 = EPWM channel n edge-detect brake state is released. + * | | |1 = When EPWM channel n edge-detect brake detects a falling edge of any enabled brake source; this flag will be set to indicate the EPWM channel n at brake state. + * | | |Note: This bit is read only and auto cleared by hardware + * | | |When edge-detect brake interrupt flag is cleared, EPWM will release brake state until current EPWM period finished + * | | |The EPWM waveform will start output from next full EPWM period. + * |[19] |BRKESTS3 |EPWM Channel n Edge-detect Brake Status (Read Only) + * | | |0 = EPWM channel n edge-detect brake state is released. + * | | |1 = When EPWM channel n edge-detect brake detects a falling edge of any enabled brake source; this flag will be set to indicate the EPWM channel n at brake state. + * | | |Note: This bit is read only and auto cleared by hardware + * | | |When edge-detect brake interrupt flag is cleared, EPWM will release brake state until current EPWM period finished + * | | |The EPWM waveform will start output from next full EPWM period. + * |[20] |BRKESTS4 |EPWM Channel n Edge-detect Brake Status (Read Only) + * | | |0 = EPWM channel n edge-detect brake state is released. + * | | |1 = When EPWM channel n edge-detect brake detects a falling edge of any enabled brake source; this flag will be set to indicate the EPWM channel n at brake state. + * | | |Note: This bit is read only and auto cleared by hardware + * | | |When edge-detect brake interrupt flag is cleared, EPWM will release brake state until current EPWM period finished + * | | |The EPWM waveform will start output from next full EPWM period. + * |[21] |BRKESTS5 |EPWM Channel n Edge-detect Brake Status (Read Only) + * | | |0 = EPWM channel n edge-detect brake state is released. + * | | |1 = When EPWM channel n edge-detect brake detects a falling edge of any enabled brake source; this flag will be set to indicate the EPWM channel n at brake state. + * | | |Note: This bit is read only and auto cleared by hardware + * | | |When edge-detect brake interrupt flag is cleared, EPWM will release brake state until current EPWM period finished + * | | |The EPWM waveform will start output from next full EPWM period. + * |[24] |BRKLSTS0 |EPWM Channel n Level-detect Brake Status (Read Only) + * | | |0 = EPWM channel n level-detect brake state is released. + * | | |1 = When EPWM channel n level-detect brake detects a falling edge of any enabled brake source; this flag will be set to indicate the EPWM channel n at brake state. + * | | |Note: This bit is read only and auto cleared by hardware + * | | |When enabled brake source return to high level, EPWM will release brake state until current EPWM period finished + * | | |The EPWM waveform will start output from next full EPWM period. + * |[25] |BRKLSTS1 |EPWM Channel n Level-detect Brake Status (Read Only) + * | | |0 = EPWM channel n level-detect brake state is released. + * | | |1 = When EPWM channel n level-detect brake detects a falling edge of any enabled brake source; this flag will be set to indicate the EPWM channel n at brake state. + * | | |Note: This bit is read only and auto cleared by hardware + * | | |When enabled brake source return to high level, EPWM will release brake state until current EPWM period finished + * | | |The EPWM waveform will start output from next full EPWM period. + * |[26] |BRKLSTS2 |EPWM Channel n Level-detect Brake Status (Read Only) + * | | |0 = EPWM channel n level-detect brake state is released. + * | | |1 = When EPWM channel n level-detect brake detects a falling edge of any enabled brake source; this flag will be set to indicate the EPWM channel n at brake state. + * | | |Note: This bit is read only and auto cleared by hardware + * | | |When enabled brake source return to high level, EPWM will release brake state until current EPWM period finished + * | | |The EPWM waveform will start output from next full EPWM period. + * |[27] |BRKLSTS3 |EPWM Channel n Level-detect Brake Status (Read Only) + * | | |0 = EPWM channel n level-detect brake state is released. + * | | |1 = When EPWM channel n level-detect brake detects a falling edge of any enabled brake source; this flag will be set to indicate the EPWM channel n at brake state. + * | | |Note: This bit is read only and auto cleared by hardware + * | | |When enabled brake source return to high level, EPWM will release brake state until current EPWM period finished + * | | |The EPWM waveform will start output from next full EPWM period. + * |[28] |BRKLSTS4 |EPWM Channel n Level-detect Brake Status (Read Only) + * | | |0 = EPWM channel n level-detect brake state is released. + * | | |1 = When EPWM channel n level-detect brake detects a falling edge of any enabled brake source; this flag will be set to indicate the EPWM channel n at brake state. + * | | |Note: This bit is read only and auto cleared by hardware + * | | |When enabled brake source return to high level, EPWM will release brake state until current EPWM period finished + * | | |The EPWM waveform will start output from next full EPWM period. + * |[29] |BRKLSTS5 |EPWM Channel n Level-detect Brake Status (Read Only) + * | | |0 = EPWM channel n level-detect brake state is released. + * | | |1 = When EPWM channel n level-detect brake detects a falling edge of any enabled brake source; this flag will be set to indicate the EPWM channel n at brake state. + * | | |Note: This bit is read only and auto cleared by hardware + * | | |When enabled brake source return to high level, EPWM will release brake state until current EPWM period finished + * | | |The EPWM waveform will start output from next full EPWM period. + * @var EPWM_T::EADCTS0 + * Offset: 0xF8 EPWM Trigger EADC Source Select Register 0 + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[3:0] |TRGSEL0 |EPWM_CH0 Trigger EADC Source Select + * | | |0000 = EPWM_CH0 zero point. + * | | |0001 = EPWM_CH0 period point. + * | | |0010 = EPWM_CH0 zero or period point. + * | | |0011 = EPWM_CH0 up-count compared point. + * | | |0100 = EPWM_CH0 down-count compared point. + * | | |0101 = EPWM_CH1 zero point. + * | | |0110 = EPWM_CH1 period point. + * | | |0111 = EPWM_CH1 zero or period point. + * | | |1000 = EPWM_CH1 up-count compared point. + * | | |1001 = EPWM_CH1 down-count compared point. + * | | |1010 = EPWM_CH0 up-count free trigger compared point. + * | | |1011 = EPWM_CH0 down-count free trigger compared point. + * | | |1100 = EPWM_CH2 up-count free trigger compared point. + * | | |1101 = EPWM_CH2 down-count free trigger compared point. + * | | |1110 = EPWM_CH4 up-count free trigger compared point. + * | | |1111 = EPWM_CH4 down-count free trigger compared point. + * |[7] |TRGEN0 |EPWM_CH0 Trigger EADC Enable Bit + * | | |0 = EPWM_CH0 Trigger EADC function Disabled. + * | | |1 = EPWM_CH0 Trigger EADC function Enabled. + * |[11:8] |TRGSEL1 |EPWM_CH1 Trigger EADC Source Select + * | | |0000 = EPWM_CH0 zero point. + * | | |0001 = EPWM_CH0 period point. + * | | |0010 = EPWM_CH0 zero or period point. + * | | |0011 = EPWM_CH0 up-count compared point. + * | | |0100 = EPWM_CH0 down-count compared point. + * | | |0101 = EPWM_CH1 zero point. + * | | |0110 = EPWM_CH1 period point. + * | | |0111 = EPWM_CH1 zero or period point. + * | | |1000 = EPWM_CH1 up-count compared point. + * | | |1001 = EPWM_CH1 down-count compared point. + * | | |1010 = EPWM_CH0 up-count free trigger compared point. + * | | |1011 = EPWM_CH0 down-count free trigger compared point. + * | | |1100 = EPWM_CH2 up-count free trigger compared point. + * | | |1101 = EPWM_CH2 down-count free trigger compared point. + * | | |1110 = EPWM_CH4 up-count free trigger compared point. + * | | |1111 = EPWM_CH4 down-count free trigger compared point. + * |[15] |TRGEN1 |EPWM_CH1 Trigger EADC Enable Bit + * | | |0 = EPWM_CH1 Trigger EADC function Disabled. + * | | |1 = EPWM_CH1 Trigger EADC function Enabled. + * |[19:16] |TRGSEL2 |EPWM_CH2 Trigger EADC Source Select + * | | |0000 = EPWM_CH2 zero point. + * | | |0001 = EPWM_CH2 period point. + * | | |0010 = EPWM_CH2 zero or period point. + * | | |0011 = EPWM_CH2 up-count compared point. + * | | |0100 = EPWM_CH2 down-count compared point. + * | | |0101 = EPWM_CH3 zero point. + * | | |0110 = EPWM_CH3 period point. + * | | |0111 = EPWM_CH3 zero or period point. + * | | |1000 = EPWM_CH3 up-count compared point. + * | | |1001 = EPWM_CH3 down-count compared point. + * | | |1010 = EPWM_CH0 up-count free trigger compared point. + * | | |1011 = EPWM_CH0 down-count free trigger compared point. + * | | |1100 = EPWM_CH2 up-count free trigger compared point. + * | | |1101 = EPWM_CH2 down-count free trigger compared point. + * | | |1110 = EPWM_CH4 up-count free trigger compared point. + * | | |1111 = EPWM_CH4 down-count free trigger compared point. + * |[23] |TRGEN2 |EPWM_CH2 Trigger EADC Enable Bit + * | | |0 = EPWM_CH2 Trigger EADC function Disabled. + * | | |1 = EPWM_CH2 Trigger EADC function Enabled. + * |[27:24] |TRGSEL3 |EPWM_CH3 Trigger EADC Source Select + * | | |0000 = EPWM_CH2 zero point. + * | | |0001 = EPWM_CH2 period point. + * | | |0010 = EPWM_CH2 zero or period point. + * | | |0011 = EPWM_CH2 up-count compared point. + * | | |0100 = EPWM_CH2 down-count compared point. + * | | |0101 = EPWM_CH3 zero point. + * | | |0110 = EPWM_CH3 period point. + * | | |0111 = EPWM_CH3 zero or period point. + * | | |1000 = EPWM_CH3 up-count compared point. + * | | |1001 = EPWM_CH3 down-count compared point. + * | | |1010 = EPWM_CH0 up-count free trigger compared point. + * | | |1011 = EPWM_CH0 down-count free trigger compared point. + * | | |1100 = EPWM_CH2 up-count free trigger compared point. + * | | |1101 = EPWM_CH2 down-count free trigger compared point. + * | | |1110 = EPWM_CH4 up-count free trigger compared point. + * | | |1111 = EPWM_CH4 down-count free trigger compared point. + * |[31] |TRGEN3 |EPWM_CH3 Trigger EADC Enable Bit + * | | |0 = EPWM_CH3 Trigger EADC function Disabled. + * | | |1 = EPWM_CH3 Trigger EADC function Enabled. + * @var EPWM_T::EADCTS1 + * Offset: 0xFC EPWM Trigger EADC Source Select Register 1 + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[3:0] |TRGSEL4 |EPWM_CH4 Trigger EADC Source Select + * | | |0000 = EPWM_CH4 zero point. + * | | |0001 = EPWM_CH4 period point. + * | | |0010 = EPWM_CH4 zero or period point. + * | | |0011 = EPWM_CH4 up-count compared point. + * | | |0100 = EPWM_CH4 down-count compared point. + * | | |0101 = EPWM_CH5 zero point. + * | | |0110 = EPWM_CH5 period point. + * | | |0111 = EPWM_CH5 zero or period point. + * | | |1000 = EPWM_CH5 up-count compared point. + * | | |1001 = EPWM_CH5 down-count compared point. + * | | |1010 = EPWM_CH0 up-count free trigger compared point. + * | | |1011 = EPWM_CH0 down-count free trigger compared point. + * | | |1100 = EPWM_CH2 up-count free trigger compared point. + * | | |1101 = EPWM_CH2 down-count free trigger compared point. + * | | |1110 = EPWM_CH4 up-count free trigger compared point. + * | | |1111 = EPWM_CH4 down-count free trigger compared point. + * |[7] |TRGEN4 |EPWM_CH4 Trigger EADC Enable Bit + * | | |0 = EPWM_CH4 Trigger EADC function Disabled. + * | | |1 = EPWM_CH4 Trigger EADC function Enabled. + * |[11:8] |TRGSEL5 |EPWM_CH5 Trigger EADC Source Select + * | | |0000 = EPWM_CH4 zero point. + * | | |0001 = EPWM_CH4 period point. + * | | |0010 = EPWM_CH4 zero or period point. + * | | |0011 = EPWM_CH4 up-count compared point. + * | | |0100 = EPWM_CH4 down-count compared point. + * | | |0101 = EPWM_CH5 zero point. + * | | |0110 = EPWM_CH5 period point. + * | | |0111 = EPWM_CH5 zero or period point. + * | | |1000 = EPWM_CH5 up-count compared point. + * | | |1001 = EPWM_CH5 down-count compared point. + * | | |1010 = EPWM_CH0 up-count free trigger compared point. + * | | |1011 = EPWM_CH0 down-count free trigger compared point. + * | | |1100 = EPWM_CH2 up-count free trigger compared point. + * | | |1101 = EPWM_CH2 down-count free trigger compared point. + * | | |1110 = EPWM_CH4 up-count free trigger compared point. + * | | |1111 = EPWM_CH4 down-count free trigger compared point. + * |[15] |TRGEN5 |EPWM_CH5 Trigger EADC Enable Bit + * | | |0 = EPWM_CH5 Trigger EADC function Disabled. + * | | |1 = EPWM_CH5 Trigger EADC function Enabled. + * @var EPWM_T::FTCMPDAT0_1 + * Offset: 0x100 EPWM Free Trigger Compare Register 0/1 + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[15:0] |FTCMP |EPWM Free Trigger Compare Register + * | | |FTCMP uses to compare with even CNT (EPWM_CNTm[15:0], m=0,2,4) to trigger EADC + * | | |FTCMPDAT0, 2, 4 corresponding complementary pairs EPWM_CH0and EPWM_CH1, EPWM_CH2 and EPWM_CH3, EPWM_CH4 and EPWM_CH5. + * @var EPWM_T::FTCMPDAT2_3 + * Offset: 0x104 EPWM Free Trigger Compare Register 2/3 + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[15:0] |FTCMP |EPWM Free Trigger Compare Register + * | | |FTCMP uses to compare with even CNT (EPWM_CNTm[15:0], m=0,2,4) to trigger EADC + * | | |FTCMPDAT0, 2, 4 corresponding complementary pairs EPWM_CH0and EPWM_CH1, EPWM_CH2 and EPWM_CH3, EPWM_CH4 and EPWM_CH5. + * @var EPWM_T::FTCMPDAT4_5 + * Offset: 0x108 EPWM Free Trigger Compare Register 4/5 + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[15:0] |FTCMP |EPWM Free Trigger Compare Register + * | | |FTCMP uses to compare with even CNT (EPWM_CNTm[15:0], m=0,2,4) to trigger EADC + * | | |FTCMPDAT0, 2, 4 corresponding complementary pairs EPWM_CH0and EPWM_CH1, EPWM_CH2 and EPWM_CH3, EPWM_CH4 and EPWM_CH5. + * @var EPWM_T::SSCTL + * Offset: 0x110 EPWM Synchronous Start Control Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[0] |SSEN0 |EPWM Synchronous Start Function Enable Bits + * | | |When synchronous start function is enabled, the EPWM counter enable register (EPWM_CNTEN) can be enabled by writing EPWM synchronous start trigger bit (CNTSEN). + * | | |0 = EPWM synchronous start function Disabled. + * | | |1 = EPWM synchronous start function Enabled. + * |[1] |SSEN1 |EPWM Synchronous Start Function Enable Bits + * | | |When synchronous start function is enabled, the EPWM counter enable register (EPWM_CNTEN) can be enabled by writing EPWM synchronous start trigger bit (CNTSEN). + * | | |0 = EPWM synchronous start function Disabled. + * | | |1 = EPWM synchronous start function Enabled. + * |[2] |SSEN2 |EPWM Synchronous Start Function Enable Bits + * | | |When synchronous start function is enabled, the EPWM counter enable register (EPWM_CNTEN) can be enabled by writing EPWM synchronous start trigger bit (CNTSEN). + * | | |0 = EPWM synchronous start function Disabled. + * | | |1 = EPWM synchronous start function Enabled. + * |[3] |SSEN3 |EPWM Synchronous Start Function Enable Bits + * | | |When synchronous start function is enabled, the EPWM counter enable register (EPWM_CNTEN) can be enabled by writing EPWM synchronous start trigger bit (CNTSEN). + * | | |0 = EPWM synchronous start function Disabled. + * | | |1 = EPWM synchronous start function Enabled. + * |[4] |SSEN4 |EPWM Synchronous Start Function Enable Bits + * | | |When synchronous start function is enabled, the EPWM counter enable register (EPWM_CNTEN) can be enabled by writing EPWM synchronous start trigger bit (CNTSEN). + * | | |0 = EPWM synchronous start function Disabled. + * | | |1 = EPWM synchronous start function Enabled. + * |[5] |SSEN5 |EPWM Synchronous Start Function Enable Bits + * | | |When synchronous start function is enabled, the EPWM counter enable register (EPWM_CNTEN) can be enabled by writing EPWM synchronous start trigger bit (CNTSEN). + * | | |0 = EPWM synchronous start function Disabled. + * | | |1 = EPWM synchronous start function Enabled. + * |[9:8] |SSRC |EPWM Synchronous Start Source Select Bits + * | | |00 = Synchronous start source come from EPWM0. + * | | |01 = Synchronous start source come from EPWM1. + * | | |10 = Synchronous start source come from EPWM2. + * | | |11 = Reserved. + * @var EPWM_T::SSTRG + * Offset: 0x114 EPWM Synchronous Start Trigger Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[0] |CNTSEN |EPWM Counter Synchronous Start Enable (Write Only) + * | | |PMW counter synchronous enable function is used to make selected EPWM channels (include EPWM0_CHx and EPWM1_CHx) start counting at the same time. + * | | |Writing this bit to 1 will also set the counter enable bit (CNTENn, n denotes channel 0 to 5) if correlated EPWM channel counter synchronous start function is enabled. + * @var EPWM_T::LEBCTL + * Offset: 0x118 EPWM Leading Edge Blanking Control Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[0] |LEBEN |EPWM Leading Edge Blanking Enable Bit + * | | |0 = EPWM Leading Edge Blanking Disabled. + * | | |1 = EPWM Leading Edge Blanking Enabled. + * |[8] |SRCEN0 |EPWM Leading Edge Blanking Source From EPWM_CH0 Enable Bit + * | | |0 = EPWM Leading Edge Blanking Source from EPWM_CH0 Disabled. + * | | |1 = EPWM Leading Edge Blanking Source from EPWM_CH0 Enabled. + * |[9] |SRCEN2 |EPWM Leading Edge Blanking Source From EPWM_CH2 Enable Bit + * | | |0 = EPWM Leading Edge Blanking Source from EPWM_CH2 Disabled. + * | | |1 = EPWM Leading Edge Blanking Source from EPWM_CH2 Enabled. + * |[10] |SRCEN4 |EPWM Leading Edge Blanking Source From EPWM_CH4 Enable Bit + * | | |0 = EPWM Leading Edge Blanking Source from EPWM_CH4 Disabled. + * | | |1 = EPWM Leading Edge Blanking Source from EPWM_CH4 Enabled. + * |[17:16] |TRGTYPE |EPWM Leading Edge Blanking Trigger Type + * | | |0 = When detect leading edge blanking source rising edge, blanking counter start counting. + * | | |1 = When detect leading edge blanking source falling edge, blanking counter start counting. + * | | |2 = When detect leading edge blanking source rising or falling edge, blanking counter start counting. + * | | |3 = Reserved. + * @var EPWM_T::LEBCNT + * Offset: 0x11C EPWM Leading Edge Blanking Counter Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[8:0] |LEBCNT |EPWM Leading Edge Blanking Counter + * | | |This counter value decides leading edge blanking window size + * | | |Blanking window size = LEBCNT+1, and LEB counter clock base is ECLK. + * @var EPWM_T::STATUS + * Offset: 0x120 EPWM Status Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[0] |CNTMAXF0 |Time-base Counter Equal to 0xFFFF Latched Flag + * | | |0 = The time-base counter never reached its maximum value 0xFFFF. + * | | |1 = The time-base counter reached its maximum value. + * | | |Note: This bit can be cleared by software writing 1. + * |[1] |CNTMAXF1 |Time-base Counter Equal to 0xFFFF Latched Flag + * | | |0 = The time-base counter never reached its maximum value 0xFFFF. + * | | |1 = The time-base counter reached its maximum value. + * | | |Note: This bit can be cleared by software writing 1. + * |[2] |CNTMAXF2 |Time-base Counter Equal to 0xFFFF Latched Flag + * | | |0 = The time-base counter never reached its maximum value 0xFFFF. + * | | |1 = The time-base counter reached its maximum value. + * | | |Note: This bit can be cleared by software writing 1. + * |[3] |CNTMAXF3 |Time-base Counter Equal to 0xFFFF Latched Flag + * | | |0 = The time-base counter never reached its maximum value 0xFFFF. + * | | |1 = The time-base counter reached its maximum value. + * | | |Note: This bit can be cleared by software writing 1. + * |[4] |CNTMAXF4 |Time-base Counter Equal to 0xFFFF Latched Flag + * | | |0 = The time-base counter never reached its maximum value 0xFFFF. + * | | |1 = The time-base counter reached its maximum value. + * | | |Note: This bit can be cleared by software writing 1. + * |[5] |CNTMAXF5 |Time-base Counter Equal to 0xFFFF Latched Flag + * | | |0 = The time-base counter never reached its maximum value 0xFFFF. + * | | |1 = The time-base counter reached its maximum value. + * | | |Note: This bit can be cleared by software writing 1. + * |[8] |SYNCINF0 |Input Synchronization Latched Flag + * | | |0 = No SYNC_IN event occurred. + * | | |1 = A SYNC_IN event occurred. + * | | |Note: This bit can be cleared by software writing 1. + * |[9] |SYNCINF2 |Input Synchronization Latched Flag + * | | |0 = No SYNC_IN event occurred. + * | | |1 = A SYNC_IN event occurred. + * | | |Note: This bit can be cleared by software writing 1. + * |[10] |SYNCINF4 |Input Synchronization Latched Flag + * | | |0 = No SYNC_IN event occurred. + * | | |1 = A SYNC_IN event occurred. + * | | |Note: This bit can be cleared by software writing 1. + * |[16] |EADCTRGF0 |EADC Start of Conversion Flag + * | | |0 = No EADC start of conversion trigger event occurred. + * | | |1 = An EADC start of conversion trigger event occurred. + * | | |Note: This bit can be cleared by software writing 1. + * |[17] |EADCTRGF1 |EADC Start of Conversion Flag + * | | |0 = No EADC start of conversion trigger event occurred. + * | | |1 = An EADC start of conversion trigger event occurred. + * | | |Note: This bit can be cleared by software writing 1. + * |[18] |EADCTRGF2 |EADC Start of Conversion Flag + * | | |0 = No EADC start of conversion trigger event occurred. + * | | |1 = An EADC start of conversion trigger event occurred. + * | | |Note: This bit can be cleared by software writing 1. + * |[19] |EADCTRGF3 |EADC Start of Conversion Flag + * | | |0 = No EADC start of conversion trigger event occurred. + * | | |1 = An EADC start of conversion trigger event occurred. + * | | |Note: This bit can be cleared by software writing 1. + * |[20] |EADCTRGF4 |EADC Start of Conversion Flag + * | | |0 = No EADC start of conversion trigger event occurred. + * | | |1 = An EADC start of conversion trigger event occurred. + * | | |Note: This bit can be cleared by software writing 1. + * |[21] |EADCTRGF5 |EADC Start of Conversion Flag + * | | |0 = No EADC start of conversion trigger event occurred. + * | | |1 = An EADC start of conversion trigger event occurred. + * | | |Note: This bit can be cleared by software writing 1. + * @var EPWM_T::IFA0 + * Offset: 0x130 EPWM Interrupt Flag Accumulator Register 0 + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[15:0] |IFACNT |EPWM_CHn Interrupt Flag Counter + * | | |The register sets the count number which defines how many times of EPWM_CHn period occurs to set bit IFAIFn to request the EPWM period interrupt. + * | | |EPWM flag will be set in every IFACNT[15:0] times of EPWM period. + * |[24] |STPMOD |EPWM_CHn Accumulator Stop Mode Enable Bits + * | | |0 = EPWM_CHn Stop Mode Disable. + * | | |1 = EPWM_CHn Stop Mode Enable. + * |[29:28] |IFASEL |EPWM_CHn Interrupt Flag Accumulator Source Select + * | | |00 = EPWM_CHn zero point. + * | | |01 = EPWM_CHn period in channel n. + * | | |10 = EPWM_CHn up-count compared point. + * | | |11 = EPWM_CHn down-count compared point. + * |[31] |IFAEN |EPWM_CHn Interrupt Flag Accumulator Enable Bits + * | | |0 = EPWM_CHn interrupt flag accumulator Disabled. + * | | |1 = EPWM_CHn interrupt flag accumulator Enabled. + * @var EPWM_T::IFA1 + * Offset: 0x134 EPWM Interrupt Flag Accumulator Register 1 + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[15:0] |IFACNT |EPWM_CHn Interrupt Flag Counter + * | | |The register sets the count number which defines how many times of EPWM_CHn period occurs to set bit IFAIFn to request the EPWM period interrupt. + * | | |EPWM flag will be set in every IFACNT[15:0] times of EPWM period. + * |[24] |STPMOD |EPWM_CHn Accumulator Stop Mode Enable Bits + * | | |0 = EPWM_CHn Stop Mode Disable. + * | | |1 = EPWM_CHn Stop Mode Enable. + * |[29:28] |IFASEL |EPWM_CHn Interrupt Flag Accumulator Source Select + * | | |00 = EPWM_CHn zero point. + * | | |01 = EPWM_CHn period in channel n. + * | | |10 = EPWM_CHn up-count compared point. + * | | |11 = EPWM_CHn down-count compared point. + * |[31] |IFAEN |EPWM_CHn Interrupt Flag Accumulator Enable Bits + * | | |0 = EPWM_CHn interrupt flag accumulator Disabled. + * | | |1 = EPWM_CHn interrupt flag accumulator Enabled. + * @var EPWM_T::IFA2 + * Offset: 0x138 EPWM Interrupt Flag Accumulator Register 2 + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[15:0] |IFACNT |EPWM_CHn Interrupt Flag Counter + * | | |The register sets the count number which defines how many times of EPWM_CHn period occurs to set bit IFAIFn to request the EPWM period interrupt. + * | | |EPWM flag will be set in every IFACNT[15:0] times of EPWM period. + * |[24] |STPMOD |EPWM_CHn Accumulator Stop Mode Enable Bits + * | | |0 = EPWM_CHn Stop Mode Disable. + * | | |1 = EPWM_CHn Stop Mode Enable. + * |[29:28] |IFASEL |EPWM_CHn Interrupt Flag Accumulator Source Select + * | | |00 = EPWM_CHn zero point. + * | | |01 = EPWM_CHn period in channel n. + * | | |10 = EPWM_CHn up-count compared point. + * | | |11 = EPWM_CHn down-count compared point. + * |[31] |IFAEN |EPWM_CHn Interrupt Flag Accumulator Enable Bits + * | | |0 = EPWM_CHn interrupt flag accumulator Disabled. + * | | |1 = EPWM_CHn interrupt flag accumulator Enabled. + * @var EPWM_T::IFA3 + * Offset: 0x13C EPWM Interrupt Flag Accumulator Register 3 + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[15:0] |IFACNT |EPWM_CHn Interrupt Flag Counter + * | | |The register sets the count number which defines how many times of EPWM_CHn period occurs to set bit IFAIFn to request the EPWM period interrupt. + * | | |EPWM flag will be set in every IFACNT[15:0] times of EPWM period. + * |[24] |STPMOD |EPWM_CHn Accumulator Stop Mode Enable Bits + * | | |0 = EPWM_CHn Stop Mode Disable. + * | | |1 = EPWM_CHn Stop Mode Enable. + * |[29:28] |IFASEL |EPWM_CHn Interrupt Flag Accumulator Source Select + * | | |00 = EPWM_CHn zero point. + * | | |01 = EPWM_CHn period in channel n. + * | | |10 = EPWM_CHn up-count compared point. + * | | |11 = EPWM_CHn down-count compared point. + * |[31] |IFAEN |EPWM_CHn Interrupt Flag Accumulator Enable Bits + * | | |0 = EPWM_CHn interrupt flag accumulator Disabled. + * | | |1 = EPWM_CHn interrupt flag accumulator Enabled. + * @var EPWM_T::IFA4 + * Offset: 0x140 EPWM Interrupt Flag Accumulator Register 4 + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[15:0] |IFACNT |EPWM_CHn Interrupt Flag Counter + * | | |The register sets the count number which defines how many times of EPWM_CHn period occurs to set bit IFAIFn to request the EPWM period interrupt. + * | | |EPWM flag will be set in every IFACNT[15:0] times of EPWM period. + * |[24] |STPMOD |EPWM_CHn Accumulator Stop Mode Enable Bits + * | | |0 = EPWM_CHn Stop Mode Disable. + * | | |1 = EPWM_CHn Stop Mode Enable. + * |[29:28] |IFASEL |EPWM_CHn Interrupt Flag Accumulator Source Select + * | | |00 = EPWM_CHn zero point. + * | | |01 = EPWM_CHn period in channel n. + * | | |10 = EPWM_CHn up-count compared point. + * | | |11 = EPWM_CHn down-count compared point. + * |[31] |IFAEN |EPWM_CHn Interrupt Flag Accumulator Enable Bits + * | | |0 = EPWM_CHn interrupt flag accumulator Disabled. + * | | |1 = EPWM_CHn interrupt flag accumulator Enabled. + * @var EPWM_T::IFA5 + * Offset: 0x144 EPWM Interrupt Flag Accumulator Register 5 + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[15:0] |IFACNT |EPWM_CHn Interrupt Flag Counter + * | | |The register sets the count number which defines how many times of EPWM_CHn period occurs to set bit IFAIFn to request the EPWM period interrupt. + * | | |EPWM flag will be set in every IFACNT[15:0] times of EPWM period. + * |[24] |STPMOD |EPWM_CHn Accumulator Stop Mode Enable Bits + * | | |0 = EPWM_CHn Stop Mode Disable. + * | | |1 = EPWM_CHn Stop Mode Enable. + * |[29:28] |IFASEL |EPWM_CHn Interrupt Flag Accumulator Source Select + * | | |00 = EPWM_CHn zero point. + * | | |01 = EPWM_CHn period in channel n. + * | | |10 = EPWM_CHn up-count compared point. + * | | |11 = EPWM_CHn down-count compared point. + * |[31] |IFAEN |EPWM_CHn Interrupt Flag Accumulator Enable Bits + * | | |0 = EPWM_CHn interrupt flag accumulator Disabled. + * | | |1 = EPWM_CHn interrupt flag accumulator Enabled. + * @var EPWM_T::AINTSTS + * Offset: 0x150 EPWM Accumulator Interrupt Flag Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[0] |IFAIF0 |EPWM_CHn Interrupt Flag Accumulator Interrupt Flag + * | | |Flag is set by hardware when condition matches IFASEL in EPWM_IFAn register, software can clear this bit by writing 1 to it. + * |[1] |IFAIF1 |EPWM_CHn Interrupt Flag Accumulator Interrupt Flag + * | | |Flag is set by hardware when condition matches IFASEL in EPWM_IFAn register, software can clear this bit by writing 1 to it. + * |[2] |IFAIF2 |EPWM_CHn Interrupt Flag Accumulator Interrupt Flag + * | | |Flag is set by hardware when condition matches IFASEL in EPWM_IFAn register, software can clear this bit by writing 1 to it. + * |[3] |IFAIF3 |EPWM_CHn Interrupt Flag Accumulator Interrupt Flag + * | | |Flag is set by hardware when condition matches IFASEL in EPWM_IFAn register, software can clear this bit by writing 1 to it. + * |[4] |IFAIF4 |EPWM_CHn Interrupt Flag Accumulator Interrupt Flag + * | | |Flag is set by hardware when condition matches IFASEL in EPWM_IFAn register, software can clear this bit by writing 1 to it. + * |[5] |IFAIF5 |EPWM_CHn Interrupt Flag Accumulator Interrupt Flag + * | | |Flag is set by hardware when condition matches IFASEL in EPWM_IFAn register, software can clear this bit by writing 1 to it. + * @var EPWM_T::AINTEN + * Offset: 0x154 EPWM Accumulator Interrupt Enable Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[0] |IFAIEN0 |EPWM_CHn Interrupt Flag Accumulator Interrupt Enable Bits + * | | |0 = Interrupt Flag accumulator interrupt Disabled. + * | | |1 = Interrupt Flag accumulator interrupt Enabled. + * |[1] |IFAIEN1 |EPWM_CHn Interrupt Flag Accumulator Interrupt Enable Bits + * | | |0 = Interrupt Flag accumulator interrupt Disabled. + * | | |1 = Interrupt Flag accumulator interrupt Enabled. + * |[2] |IFAIEN2 |EPWM_CHn Interrupt Flag Accumulator Interrupt Enable Bits + * | | |0 = Interrupt Flag accumulator interrupt Disabled. + * | | |1 = Interrupt Flag accumulator interrupt Enabled. + * |[3] |IFAIEN3 |EPWM_CHn Interrupt Flag Accumulator Interrupt Enable Bits + * | | |0 = Interrupt Flag accumulator interrupt Disabled. + * | | |1 = Interrupt Flag accumulator interrupt Enabled. + * |[4] |IFAIEN4 |EPWM_CHn Interrupt Flag Accumulator Interrupt Enable Bits + * | | |0 = Interrupt Flag accumulator interrupt Disabled. + * | | |1 = Interrupt Flag accumulator interrupt Enabled. + * |[5] |IFAIEN5 |EPWM_CHn Interrupt Flag Accumulator Interrupt Enable Bits + * | | |0 = Interrupt Flag accumulator interrupt Disabled. + * | | |1 = Interrupt Flag accumulator interrupt Enabled. + * @var EPWM_T::APDMACTL + * Offset: 0x158 EPWM Accumulator PDMA Control Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[0] |APDMAEN0 |Channel n Accumulator PDMA Enable Bits + * | | |0 = Channel n PDMA function Disabled. + * | | |1 = Channel n PDMA function Enabled for the channel n to trigger PDMA to transfer memory data to register. + * |[1] |APDMAEN1 |Channel n Accumulator PDMA Enable Bits + * | | |0 = Channel n PDMA function Disabled. + * | | |1 = Channel n PDMA function Enabled for the channel n to trigger PDMA to transfer memory data to register. + * |[2] |APDMAEN2 |Channel n Accumulator PDMA Enable Bits + * | | |0 = Channel n PDMA function Disabled. + * | | |1 = Channel n PDMA function Enabled for the channel n to trigger PDMA to transfer memory data to register. + * |[3] |APDMAEN3 |Channel n Accumulator PDMA Enable Bits + * | | |0 = Channel n PDMA function Disabled. + * | | |1 = Channel n PDMA function Enabled for the channel n to trigger PDMA to transfer memory data to register. + * |[4] |APDMAEN4 |Channel n Accumulator PDMA Enable Bits + * | | |0 = Channel n PDMA function Disabled. + * | | |1 = Channel n PDMA function Enabled for the channel n to trigger PDMA to transfer memory data to register. + * |[5] |APDMAEN5 |Channel n Accumulator PDMA Enable Bits + * | | |0 = Channel n PDMA function Disabled. + * | | |1 = Channel n PDMA function Enabled for the channel n to trigger PDMA to transfer memory data to register. + * @var EPWM_T::FDEN + * Offset: 0x160 EPWM Fault Detect Enable Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[0] |FDEN0 |EPWM Fault Detect Function Enable Bit + * | | |0 = Fault detect function Disable. + * | | |1 = Fault detect function Enable. + * |[1] |FDEN1 |EPWM Fault Detect Function Enable Bit + * | | |0 = Fault detect function Disable. + * | | |1 = Fault detect function Enable. + * |[2] |FDEN2 |EPWM Fault Detect Function Enable Bit + * | | |0 = Fault detect function Disable. + * | | |1 = Fault detect function Enable. + * |[3] |FDEN3 |EPWM Fault Detect Function Enable Bit + * | | |0 = Fault detect function Disable. + * | | |1 = Fault detect function Enable. + * |[4] |FDEN4 |EPWM Fault Detect Function Enable Bit + * | | |0 = Fault detect function Disable. + * | | |1 = Fault detect function Enable. + * |[5] |FDEN5 |EPWM Fault Detect Function Enable Bit + * | | |0 = Fault detect function Disable. + * | | |1 = Fault detect function Enable. + * |[8] |FDODIS0 |EPWM Channel n Output Fault Detect Disable Bit + * | | |0 = EPWM detect fault and output Enable. + * | | |1 = EPWM detect fault and output Disable. + * |[9] |FDODIS1 |EPWM Channel n Output Fault Detect Disable Bit + * | | |0 = EPWM detect fault and output Enable. + * | | |1 = EPWM detect fault and output Disable. + * |[10] |FDODIS2 |EPWM Channel n Output Fault Detect Disable Bit + * | | |0 = EPWM detect fault and output Enable. + * | | |1 = EPWM detect fault and output Disable. + * |[11] |FDODIS3 |EPWM Channel n Output Fault Detect Disable Bit + * | | |0 = EPWM detect fault and output Enable. + * | | |1 = EPWM detect fault and output Disable. + * |[12] |FDODIS4 |EPWM Channel n Output Fault Detect Disable Bit + * | | |0 = EPWM detect fault and output Enable. + * | | |1 = EPWM detect fault and output Disable. + * |[13] |FDODIS5 |EPWM Channel n Output Fault Detect Disable Bit + * | | |0 = EPWM detect fault and output Enable. + * | | |1 = EPWM detect fault and output Disable. + * |[16] |FDCKS0 |EPWM Channel n Fault Detect Clock Source Select Bit + * | | |0 = EPWMx_CLK, x denotes 0, 1or 2. + * | | |1 = EPWMx_CLK divide by prescaler, x denotes 0, 1 or 2. + * |[17] |FDCKS1 |EPWM Channel n Fault Detect Clock Source Select Bit + * | | |0 = EPWMx_CLK, x denotes 0, 1or 2. + * | | |1 = EPWMx_CLK divide by prescaler, x denotes 0, 1 or 2. + * |[18] |FDCKS2 |EPWM Channel n Fault Detect Clock Source Select Bit + * | | |0 = EPWMx_CLK, x denotes 0, 1or 2. + * | | |1 = EPWMx_CLK divide by prescaler, x denotes 0, 1 or 2. + * |[19] |FDCKS3 |EPWM Channel n Fault Detect Clock Source Select Bit + * | | |0 = EPWMx_CLK, x denotes 0, 1or 2. + * | | |1 = EPWMx_CLK divide by prescaler, x denotes 0, 1 or 2. + * |[20] |FDCKS4 |EPWM Channel n Fault Detect Clock Source Select Bit + * | | |0 = EPWMx_CLK, x denotes 0, 1or 2. + * | | |1 = EPWMx_CLK divide by prescaler, x denotes 0, 1 or 2. + * |[21] |FDCKS5 |EPWM Channel n Fault Detect Clock Source Select Bit + * | | |0 = EPWMx_CLK, x denotes 0, 1or 2. + * | | |1 = EPWMx_CLK divide by prescaler, x denotes 0, 1 or 2. + * @var EPWM_T::FDCTL0 + * Offset: 0x164 EPWM Fault Detect Control Register 0 + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[6:0] |TRMSKCNT |Transition Mask Counter + * | | |The fault detect result will be masked before counter count from 0 to TRMSKCNT. + * | | |FDCKS is set to 0: + * | | |Mask time is EPWMx_CLK * (2^FDCKSEL) * (TRMSKCNT +2) + * | | |FDCKS is set to 1: + * | | |Mask time EPWMx_CLK * CLKPSC * (2^FDCKSEL) * (TRMSKCNT +2) + * | | |Note: + * | | |CLKPSC (EPWM_CLKPSC) is 0: + * | | |TRMSKCNT >= DGSMPCYC + 2. + * | | |FDCKS is 1 and CLKPSC (EPWM_CLKPSC) is 1: + * | | |TRMSKCNT >= DGSMPCYC + 1. + * | | |FDCKS is 1 and CLKPSC (EPWM_CLKPSC) is 2: + * | | |TRMSKCNT >= DGSMPCYC. + * |[15] |FDMSKEN |Fault Detect Mask Enable Bit + * | | |0 = Fault detect mask function Disabled. + * | | |1 = Fault detect mask function Enabled. + * |[18:16] |DGSMPCYC |Deglitch Sampling Cycle + * | | |FDCKS is set to 0: + * | | |Sampling detect signal each EPWMx_CLK * (2^FDCKSEL) period and detect DGSMPCYC+1 times + * | | |FDCKS is set to 1: + * | | |Sampling detect signal each EPWMx_CLK * CLKPSC * (2^FDCKSEL) period and detect DGSMPCYC+1 times + * | | |Note: + * | | |CLKPSC (EPWM_CLKPSC) is 0: + * | | |TRMSKCNT >= DGSMPCYC + 2. + * | | |FDCKS is 1 and CLKPSC (EPWM_CLKPSC) is 1: + * | | |TRMSKCNT >= DGSMPCYC + 1. + * | | |FDCKS is 1 and CLKPSC (EPWM_CLKPSC) is 2: + * | | |TRMSKCNT >= DGSMPCYC. + * |[29:28] |FDCKSEL |EPWM Channel Fault Detect Clock Select + * | | |00 = FLT_CLK/1. + * | | |01 = FLT_CLK/2. + * | | |10 = FLT_CLK/4. + * | | |11 = FLT_CLK/8. + * | | |Note: FLT_CLK is FDCKSn (EPWM_FDENn[16+n], n=0,1..5) selected clock. + * |[31] |FDDGEN |Fault Detect Deglitch Enable Bit + * | | |0 = Fault detect deglitch function Disable. + * | | |1 = Fault detect deglitch function Enable. + * @var EPWM_T::FDCTL1 + * Offset: 0x168 EPWM Fault Detect Control Register 1 + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[6:0] |TRMSKCNT |Transition Mask Counter + * | | |The fault detect result will be masked before counter count from 0 to TRMSKCNT. + * | | |FDCKS is set to 0: + * | | |Mask time is EPWMx_CLK * (2^FDCKSEL) * (TRMSKCNT +2) + * | | |FDCKS is set to 1: + * | | |Mask time EPWMx_CLK * CLKPSC * (2^FDCKSEL) * (TRMSKCNT +2) + * | | |Note: + * | | |CLKPSC (EPWM_CLKPSC) is 0: + * | | |TRMSKCNT >= DGSMPCYC + 2. + * | | |FDCKS is 1 and CLKPSC (EPWM_CLKPSC) is 1: + * | | |TRMSKCNT >= DGSMPCYC + 1. + * | | |FDCKS is 1 and CLKPSC (EPWM_CLKPSC) is 2: + * | | |TRMSKCNT >= DGSMPCYC. + * |[15] |FDMSKEN |Fault Detect Mask Enable Bit + * | | |0 = Fault detect mask function Disabled. + * | | |1 = Fault detect mask function Enabled. + * |[18:16] |DGSMPCYC |Deglitch Sampling Cycle + * | | |FDCKS is set to 0: + * | | |Sampling detect signal each EPWMx_CLK * (2^FDCKSEL) period and detect DGSMPCYC+1 times + * | | |FDCKS is set to 1: + * | | |Sampling detect signal each EPWMx_CLK * CLKPSC * (2^FDCKSEL) period and detect DGSMPCYC+1 times + * | | |Note: + * | | |CLKPSC (EPWM_CLKPSC) is 0: + * | | |TRMSKCNT >= DGSMPCYC + 2. + * | | |FDCKS is 1 and CLKPSC (EPWM_CLKPSC) is 1: + * | | |TRMSKCNT >= DGSMPCYC + 1. + * | | |FDCKS is 1 and CLKPSC (EPWM_CLKPSC) is 2: + * | | |TRMSKCNT >= DGSMPCYC. + * |[29:28] |FDCKSEL |EPWM Channel Fault Detect Clock Select + * | | |00 = FLT_CLK/1. + * | | |01 = FLT_CLK/2. + * | | |10 = FLT_CLK/4. + * | | |11 = FLT_CLK/8. + * | | |Note: FLT_CLK is FDCKSn (EPWM_FDENn[16+n], n=0,1..5) selected clock. + * |[31] |FDDGEN |Fault Detect Deglitch Enable Bit + * | | |0 = Fault detect deglitch function Disable. + * | | |1 = Fault detect deglitch function Enable. + * @var EPWM_T::FDCTL2 + * Offset: 0x16C EPWM Fault Detect Control Register 2 + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[6:0] |TRMSKCNT |Transition Mask Counter + * | | |The fault detect result will be masked before counter count from 0 to TRMSKCNT. + * | | |FDCKS is set to 0: + * | | |Mask time is EPWMx_CLK * (2^FDCKSEL) * (TRMSKCNT +2) + * | | |FDCKS is set to 1: + * | | |Mask time EPWMx_CLK * CLKPSC * (2^FDCKSEL) * (TRMSKCNT +2) + * | | |Note: + * | | |CLKPSC (EPWM_CLKPSC) is 0: + * | | |TRMSKCNT >= DGSMPCYC + 2. + * | | |FDCKS is 1 and CLKPSC (EPWM_CLKPSC) is 1: + * | | |TRMSKCNT >= DGSMPCYC + 1. + * | | |FDCKS is 1 and CLKPSC (EPWM_CLKPSC) is 2: + * | | |TRMSKCNT >= DGSMPCYC. + * |[15] |FDMSKEN |Fault Detect Mask Enable Bit + * | | |0 = Fault detect mask function Disabled. + * | | |1 = Fault detect mask function Enabled. + * |[18:16] |DGSMPCYC |Deglitch Sampling Cycle + * | | |FDCKS is set to 0: + * | | |Sampling detect signal each EPWMx_CLK * (2^FDCKSEL) period and detect DGSMPCYC+1 times + * | | |FDCKS is set to 1: + * | | |Sampling detect signal each EPWMx_CLK * CLKPSC * (2^FDCKSEL) period and detect DGSMPCYC+1 times + * | | |Note: + * | | |CLKPSC (EPWM_CLKPSC) is 0: + * | | |TRMSKCNT >= DGSMPCYC + 2. + * | | |FDCKS is 1 and CLKPSC (EPWM_CLKPSC) is 1: + * | | |TRMSKCNT >= DGSMPCYC + 1. + * | | |FDCKS is 1 and CLKPSC (EPWM_CLKPSC) is 2: + * | | |TRMSKCNT >= DGSMPCYC. + * |[29:28] |FDCKSEL |EPWM Channel Fault Detect Clock Select + * | | |00 = FLT_CLK/1. + * | | |01 = FLT_CLK/2. + * | | |10 = FLT_CLK/4. + * | | |11 = FLT_CLK/8. + * | | |Note: FLT_CLK is FDCKSn (EPWM_FDENn[16+n], n=0,1..5) selected clock. + * |[31] |FDDGEN |Fault Detect Deglitch Enable Bit + * | | |0 = Fault detect deglitch function Disable. + * | | |1 = Fault detect deglitch function Enable. + * @var EPWM_T::FDCTL3 + * Offset: 0x170 EPWM Fault Detect Control Register 3 + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[6:0] |TRMSKCNT |Transition Mask Counter + * | | |The fault detect result will be masked before counter count from 0 to TRMSKCNT. + * | | |FDCKS is set to 0: + * | | |Mask time is EPWMx_CLK * (2^FDCKSEL) * (TRMSKCNT +2) + * | | |FDCKS is set to 1: + * | | |Mask time EPWMx_CLK * CLKPSC * (2^FDCKSEL) * (TRMSKCNT +2) + * | | |Note: + * | | |CLKPSC (EPWM_CLKPSC) is 0: + * | | |TRMSKCNT >= DGSMPCYC + 2. + * | | |FDCKS is 1 and CLKPSC (EPWM_CLKPSC) is 1: + * | | |TRMSKCNT >= DGSMPCYC + 1. + * | | |FDCKS is 1 and CLKPSC (EPWM_CLKPSC) is 2: + * | | |TRMSKCNT >= DGSMPCYC. + * |[15] |FDMSKEN |Fault Detect Mask Enable Bit + * | | |0 = Fault detect mask function Disabled. + * | | |1 = Fault detect mask function Enabled. + * |[18:16] |DGSMPCYC |Deglitch Sampling Cycle + * | | |FDCKS is set to 0: + * | | |Sampling detect signal each EPWMx_CLK * (2^FDCKSEL) period and detect DGSMPCYC+1 times + * | | |FDCKS is set to 1: + * | | |Sampling detect signal each EPWMx_CLK * CLKPSC * (2^FDCKSEL) period and detect DGSMPCYC+1 times + * | | |Note: + * | | |CLKPSC (EPWM_CLKPSC) is 0: + * | | |TRMSKCNT >= DGSMPCYC + 2. + * | | |FDCKS is 1 and CLKPSC (EPWM_CLKPSC) is 1: + * | | |TRMSKCNT >= DGSMPCYC + 1. + * | | |FDCKS is 1 and CLKPSC (EPWM_CLKPSC) is 2: + * | | |TRMSKCNT >= DGSMPCYC. + * |[29:28] |FDCKSEL |EPWM Channel Fault Detect Clock Select + * | | |00 = FLT_CLK/1. + * | | |01 = FLT_CLK/2. + * | | |10 = FLT_CLK/4. + * | | |11 = FLT_CLK/8. + * | | |Note: FLT_CLK is FDCKSn (EPWM_FDENn[16+n], n=0,1..5) selected clock. + * |[31] |FDDGEN |Fault Detect Deglitch Enable Bit + * | | |0 = Fault detect deglitch function Disable. + * | | |1 = Fault detect deglitch function Enable. + * @var EPWM_T::FDCTL4 + * Offset: 0x174 EPWM Fault Detect Control Register 4 + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[6:0] |TRMSKCNT |Transition Mask Counter + * | | |The fault detect result will be masked before counter count from 0 to TRMSKCNT. + * | | |FDCKS is set to 0: + * | | |Mask time is EPWMx_CLK * (2^FDCKSEL) * (TRMSKCNT +2) + * | | |FDCKS is set to 1: + * | | |Mask time EPWMx_CLK * CLKPSC * (2^FDCKSEL) * (TRMSKCNT +2) + * | | |Note: + * | | |CLKPSC (EPWM_CLKPSC) is 0: + * | | |TRMSKCNT >= DGSMPCYC + 2. + * | | |FDCKS is 1 and CLKPSC (EPWM_CLKPSC) is 1: + * | | |TRMSKCNT >= DGSMPCYC + 1. + * | | |FDCKS is 1 and CLKPSC (EPWM_CLKPSC) is 2: + * | | |TRMSKCNT >= DGSMPCYC. + * |[15] |FDMSKEN |Fault Detect Mask Enable Bit + * | | |0 = Fault detect mask function Disabled. + * | | |1 = Fault detect mask function Enabled. + * |[18:16] |DGSMPCYC |Deglitch Sampling Cycle + * | | |FDCKS is set to 0: + * | | |Sampling detect signal each EPWMx_CLK * (2^FDCKSEL) period and detect DGSMPCYC+1 times + * | | |FDCKS is set to 1: + * | | |Sampling detect signal each EPWMx_CLK * CLKPSC * (2^FDCKSEL) period and detect DGSMPCYC+1 times + * | | |Note: + * | | |CLKPSC (EPWM_CLKPSC) is 0: + * | | |TRMSKCNT >= DGSMPCYC + 2. + * | | |FDCKS is 1 and CLKPSC (EPWM_CLKPSC) is 1: + * | | |TRMSKCNT >= DGSMPCYC + 1. + * | | |FDCKS is 1 and CLKPSC (EPWM_CLKPSC) is 2: + * | | |TRMSKCNT >= DGSMPCYC. + * |[29:28] |FDCKSEL |EPWM Channel Fault Detect Clock Select + * | | |00 = FLT_CLK/1. + * | | |01 = FLT_CLK/2. + * | | |10 = FLT_CLK/4. + * | | |11 = FLT_CLK/8. + * | | |Note: FLT_CLK is FDCKSn (EPWM_FDENn[16+n], n=0,1..5) selected clock. + * |[31] |FDDGEN |Fault Detect Deglitch Enable Bit + * | | |0 = Fault detect deglitch function Disable. + * | | |1 = Fault detect deglitch function Enable. + * @var EPWM_T::FDCTL5 + * Offset: 0x178 EPWM Fault Detect Control Register 5 + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[6:0] |TRMSKCNT |Transition Mask Counter + * | | |The fault detect result will be masked before counter count from 0 to TRMSKCNT. + * | | |FDCKS is set to 0: + * | | |Mask time is EPWMx_CLK * (2^FDCKSEL) * (TRMSKCNT +2) + * | | |FDCKS is set to 1: + * | | |Mask time EPWMx_CLK * CLKPSC * (2^FDCKSEL) * (TRMSKCNT +2) + * | | |Note: + * | | |CLKPSC (EPWM_CLKPSC) is 0: + * | | |TRMSKCNT >= DGSMPCYC + 2. + * | | |FDCKS is 1 and CLKPSC (EPWM_CLKPSC) is 1: + * | | |TRMSKCNT >= DGSMPCYC + 1. + * | | |FDCKS is 1 and CLKPSC (EPWM_CLKPSC) is 2: + * | | |TRMSKCNT >= DGSMPCYC. + * |[15] |FDMSKEN |Fault Detect Mask Enable Bit + * | | |0 = Fault detect mask function Disabled. + * | | |1 = Fault detect mask function Enabled. + * |[18:16] |DGSMPCYC |Deglitch Sampling Cycle + * | | |FDCKS is set to 0: + * | | |Sampling detect signal each EPWMx_CLK * (2^FDCKSEL) period and detect DGSMPCYC+1 times + * | | |FDCKS is set to 1: + * | | |Sampling detect signal each EPWMx_CLK * CLKPSC * (2^FDCKSEL) period and detect DGSMPCYC+1 times + * | | |Note: + * | | |CLKPSC (EPWM_CLKPSC) is 0: + * | | |TRMSKCNT >= DGSMPCYC + 2. + * | | |FDCKS is 1 and CLKPSC (EPWM_CLKPSC) is 1: + * | | |TRMSKCNT >= DGSMPCYC + 1. + * | | |FDCKS is 1 and CLKPSC (EPWM_CLKPSC) is 2: + * | | |TRMSKCNT >= DGSMPCYC. + * |[29:28] |FDCKSEL |EPWM Channel Fault Detect Clock Select + * | | |00 = FLT_CLK/1. + * | | |01 = FLT_CLK/2. + * | | |10 = FLT_CLK/4. + * | | |11 = FLT_CLK/8. + * | | |Note: FLT_CLK is FDCKSn (EPWM_FDENn[16+n], n=0,1..5) selected clock. + * |[31] |FDDGEN |Fault Detect Deglitch Enable Bit + * | | |0 = Fault detect deglitch function Disable. + * | | |1 = Fault detect deglitch function Enable. + * @var EPWM_T::FDIEN + * Offset: 0x17C EPWM Fault Detect Interrupt Enable Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[0] |FDIENn |EPWM Channel n Fault Detect Interrupt Enable Bit + * | | |0 = EPWM Channel n Fault Detect Interrupt Disabled. + * | | |1 = EPWM Channel n Fault Detect Interrupt Enabled. + * @var EPWM_T::FDSTS + * Offset: 0x180 EPWM Fault Detect Interrupt Flag Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[5:0] |FDIFn |EPWM Channel n Fault Detect Interrupt Flag Bit + * | | |Fault Detect Interrupt Flag will be set when EPWM output short + * | | |Software can clear this bit by writing 1 to it. + * @var EPWM_T::EADCPSCCTL + * Offset: 0x184 EPWM Trigger EADC Prescale Control Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[0] |PSCEN0 |EPWM Trigger EADC Pre-scale Function Enable Bits + * | | |0 = EPWM Trigger EADC Pre-scale Function Disabled. + * | | |1 = EPWM Trigger EADC Pre-scale Function Enabled. + * |[1] |PSCEN1 |EPWM Trigger EADC Pre-scale Function Enable Bits + * | | |0 = EPWM Trigger EADC Pre-scale Function Disabled. + * | | |1 = EPWM Trigger EADC Pre-scale Function Enabled. + * |[2] |PSCEN2 |EPWM Trigger EADC Pre-scale Function Enable Bits + * | | |0 = EPWM Trigger EADC Pre-scale Function Disabled. + * | | |1 = EPWM Trigger EADC Pre-scale Function Enabled. + * |[3] |PSCEN3 |EPWM Trigger EADC Pre-scale Function Enable Bits + * | | |0 = EPWM Trigger EADC Pre-scale Function Disabled. + * | | |1 = EPWM Trigger EADC Pre-scale Function Enabled. + * |[4] |PSCEN4 |EPWM Trigger EADC Pre-scale Function Enable Bits + * | | |0 = EPWM Trigger EADC Pre-scale Function Disabled. + * | | |1 = EPWM Trigger EADC Pre-scale Function Enabled. + * |[5] |PSCEN5 |EPWM Trigger EADC Pre-scale Function Enable Bits + * | | |0 = EPWM Trigger EADC Pre-scale Function Disabled. + * | | |1 = EPWM Trigger EADC Pre-scale Function Enabled. + * @var EPWM_T::EADCPSC0 + * Offset: 0x188 EPWM Trigger EADC Prescale Register 0 + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[3:0] |EADCPSC0 |EPWM Channel 0 Trigger EADC Prescale + * | | |The register sets the count number which defines (EADCPSC0+1) times of EPWM_CH0 trigger EADC event occurs to trigger EADC and set trigger EADC flag bit EADCTRGF0. + * |[11:8] |EADCPSC1 |EPWM Channel 1 Trigger EADC Prescale + * | | |The register sets the count number which defines (EADCPSC1+1) times of EPWM_CH1 trigger EADC event occurs to trigger EADC and set trigger EADC flag bit EADCTRGF1. + * |[19:16] |EADCPSC2 |EPWM Channel 2 Trigger EADC Prescale + * | | |The register sets the count number which defines (EADCPSC2+1) times of EPWM_CH2 trigger EADC event occurs to trigger EADC and set trigger EADC flag bit EADCTRGF3. + * |[27:24] |EADCPSC3 |EPWM Channel 3 Trigger EADC Prescale + * | | |The register sets the count number which defines (EADCPSC3+1) times of EPWM_CH3 trigger EADC event occurs to trigger EADC and set trigger EADC flag bit EADCTRGF3. + * @var EPWM_T::EADCPSC1 + * Offset: 0x18C EPWM Trigger EADC Prescale Register 1 + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[3:0] |EADCPSC4 |EPWM Channel 4 Trigger EADC Prescale + * | | |The register sets the count number which defines (EADCPSC4+1) times of EPWM_CH3 trigger EADC event occurs to trigger EADC and set trigger EADC flag bit EADCTRGF4. + * |[11:8] |EADCPSC5 |EPWM Channel 5 Trigger EADC Prescale + * | | |The register sets the count number which defines (EADCPSC5+1) times of EPWM_CH3 trigger EADC event occurs to trigger EADC and set trigger EADC flag bit EADCTRGF5. + * @var EPWM_T::EADCPSCNT0 + * Offset: 0x190 EPWM Trigger EADC Prescale Counter Register 0 + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[3:0] |PSCNT0 |EPWM Trigger EADC Prescale Counter 0 + * | | |User can monitor PSCNT0 to know the current value in 4-bit trigger EADC prescale counter. + * | | |Note 1: user can write only when PSCEN0 is 0. + * | | |Note 2: Write data limitation: PSCNT0 < EADCPSC0. + * |[11:8] |PSCNT1 |EPWM Trigger EADC Prescale Counter 1 + * | | |User can monitor PSCNT1 to know the current value in 4-bit trigger EADC prescale counter. + * | | |Note 1: user can write only when PSCEN1 is 0. + * | | |Note 2: Write data limitation: PSCNT1 < EADCPSC1. + * |[19:16] |PSCNT2 |EPWM Trigger EADC Prescale Counter 2 + * | | |User can monitor PSCNT2 to know the current value in 4-bit trigger EADC prescale counter. + * | | |Note 1: user can write only when PSCEN2 is 0. + * | | |Note 2: Write data limitation: PSCNT2 < EADCPSC2. + * |[27:24] |PSCNT3 |EPWM Trigger EADC Prescale Counter 3 + * | | |User can monitor PSCNT3 to know the current value in 4-bit trigger EADC prescale counter. + * | | |Note 1: user can write only when PSCEN3 is 0. + * | | |Note 2: Write data limitation: PSCNT3 < EADCPSC3. + * @var EPWM_T::EADCPSCNT1 + * Offset: 0x194 EPWM Trigger EADC Prescale Counter Register 1 + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[3:0] |PSCNT4 |EPWM Trigger EADC Prescale Counter 4 + * | | |User can monitor PSCNT4 to know the current value in 4-bit trigger EADC prescale counter. + * | | |Note 1: user can write only when PSCEN4 is 0. + * | | |Note 2: Write data limitation: PSCNT4 < EADCPSC4. + * |[11:8] |PSCNT5 |EPWM Trigger EADC Prescale Counter 5 + * | | |User can monitor PSCNT5 to know the current value in 4-bit trigger EADC prescale counter. + * | | |Note 1: user can write only when PSCEN5 is 0. + * | | |Note 2: Write data limitation: PSCNT5 < EADCPSC5. + * @var EPWM_T::CAPINEN + * Offset: 0x200 EPWM Capture Input Enable Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[0] |CAPINEN0 |Capture Input Enable Bits + * | | |0 = EPWM Channel capture input path Disabled + * | | |The input of EPWM channel capture function is always regarded as 0. + * | | |1 = EPWM Channel capture input path Enabled + * | | |The input of EPWM channel capture function comes from correlative multifunction pin. + * |[1] |CAPINEN1 |Capture Input Enable Bits + * | | |0 = EPWM Channel capture input path Disabled + * | | |The input of EPWM channel capture function is always regarded as 0. + * | | |1 = EPWM Channel capture input path Enabled + * | | |The input of EPWM channel capture function comes from correlative multifunction pin. + * |[2] |CAPINEN2 |Capture Input Enable Bits + * | | |0 = EPWM Channel capture input path Disabled + * | | |The input of EPWM channel capture function is always regarded as 0. + * | | |1 = EPWM Channel capture input path Enabled + * | | |The input of EPWM channel capture function comes from correlative multifunction pin. + * |[3] |CAPINEN3 |Capture Input Enable Bits + * | | |0 = EPWM Channel capture input path Disabled + * | | |The input of EPWM channel capture function is always regarded as 0. + * | | |1 = EPWM Channel capture input path Enabled + * | | |The input of EPWM channel capture function comes from correlative multifunction pin. + * |[4] |CAPINEN4 |Capture Input Enable Bits + * | | |0 = EPWM Channel capture input path Disabled + * | | |The input of EPWM channel capture function is always regarded as 0. + * | | |1 = EPWM Channel capture input path Enabled + * | | |The input of EPWM channel capture function comes from correlative multifunction pin. + * |[5] |CAPINEN5 |Capture Input Enable Bits + * | | |0 = EPWM Channel capture input path Disabled + * | | |The input of EPWM channel capture function is always regarded as 0. + * | | |1 = EPWM Channel capture input path Enabled + * | | |The input of EPWM channel capture function comes from correlative multifunction pin. + * @var EPWM_T::CAPCTL + * Offset: 0x204 EPWM Capture Control Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[0] |CAPEN0 |Capture Function Enable Bits + * | | |0 = Capture function Disabled. RCAPDAT/FCAPDAT register will not be updated. + * | | |1 = Capture function Enabled + * | | |Capture latched the EPWM counter value when detected rising or falling edge of input signal and saved to RCAPDAT (Rising latch) and FCAPDAT (Falling latch). + * |[1] |CAPEN1 |Capture Function Enable Bits + * | | |0 = Capture function Disabled. RCAPDAT/FCAPDAT register will not be updated. + * | | |1 = Capture function Enabled + * | | |Capture latched the EPWM counter value when detected rising or falling edge of input signal and saved to RCAPDAT (Rising latch) and FCAPDAT (Falling latch). + * |[2] |CAPEN2 |Capture Function Enable Bits + * | | |0 = Capture function Disabled. RCAPDAT/FCAPDAT register will not be updated. + * | | |1 = Capture function Enabled + * | | |Capture latched the EPWM counter value when detected rising or falling edge of input signal and saved to RCAPDAT (Rising latch) and FCAPDAT (Falling latch). + * |[3] |CAPEN3 |Capture Function Enable Bits + * | | |0 = Capture function Disabled. RCAPDAT/FCAPDAT register will not be updated. + * | | |1 = Capture function Enabled + * | | |Capture latched the EPWM counter value when detected rising or falling edge of input signal and saved to RCAPDAT (Rising latch) and FCAPDAT (Falling latch). + * |[4] |CAPEN4 |Capture Function Enable Bits + * | | |0 = Capture function Disabled. RCAPDAT/FCAPDAT register will not be updated. + * | | |1 = Capture function Enabled + * | | |Capture latched the EPWM counter value when detected rising or falling edge of input signal and saved to RCAPDAT (Rising latch) and FCAPDAT (Falling latch). + * |[5] |CAPEN5 |Capture Function Enable Bits + * | | |0 = Capture function Disabled. RCAPDAT/FCAPDAT register will not be updated. + * | | |1 = Capture function Enabled + * | | |Capture latched the EPWM counter value when detected rising or falling edge of input signal and saved to RCAPDAT (Rising latch) and FCAPDAT (Falling latch). + * |[8] |CAPINV0 |Capture Inverter Enable Bits + * | | |0 = Capture source inverter Disabled. + * | | |1 = Capture source inverter Enabled. Reverse the input signal from GPIO. + * |[9] |CAPINV1 |Capture Inverter Enable Bits + * | | |0 = Capture source inverter Disabled. + * | | |1 = Capture source inverter Enabled. Reverse the input signal from GPIO. + * |[10] |CAPINV2 |Capture Inverter Enable Bits + * | | |0 = Capture source inverter Disabled. + * | | |1 = Capture source inverter Enabled. Reverse the input signal from GPIO. + * |[11] |CAPINV3 |Capture Inverter Enable Bits + * | | |0 = Capture source inverter Disabled. + * | | |1 = Capture source inverter Enabled. Reverse the input signal from GPIO. + * |[12] |CAPINV4 |Capture Inverter Enable Bits + * | | |0 = Capture source inverter Disabled. + * | | |1 = Capture source inverter Enabled. Reverse the input signal from GPIO. + * |[13] |CAPINV5 |Capture Inverter Enable Bits + * | | |0 = Capture source inverter Disabled. + * | | |1 = Capture source inverter Enabled. Reverse the input signal from GPIO. + * |[16] |RCRLDEN0 |Rising Capture Reload Enable Bits + * | | |0 = Rising capture reload counter Disabled. + * | | |1 = Rising capture reload counter Enabled. + * |[17] |RCRLDEN1 |Rising Capture Reload Enable Bits + * | | |0 = Rising capture reload counter Disabled. + * | | |1 = Rising capture reload counter Enabled. + * |[18] |RCRLDEN2 |Rising Capture Reload Enable Bits + * | | |0 = Rising capture reload counter Disabled. + * | | |1 = Rising capture reload counter Enabled. + * |[19] |RCRLDEN3 |Rising Capture Reload Enable Bits + * | | |0 = Rising capture reload counter Disabled. + * | | |1 = Rising capture reload counter Enabled. + * |[20] |RCRLDEN4 |Rising Capture Reload Enable Bits + * | | |0 = Rising capture reload counter Disabled. + * | | |1 = Rising capture reload counter Enabled. + * |[21] |RCRLDEN5 |Rising Capture Reload Enable Bits + * | | |0 = Rising capture reload counter Disabled. + * | | |1 = Rising capture reload counter Enabled. + * |[24] |FCRLDEN0 |Falling Capture Reload Enable Bits + * | | |0 = Falling capture reload counter Disabled. + * | | |1 = Falling capture reload counter Enabled. + * |[25] |FCRLDEN1 |Falling Capture Reload Enable Bits + * | | |0 = Falling capture reload counter Disabled. + * | | |1 = Falling capture reload counter Enabled. + * |[26] |FCRLDEN2 |Falling Capture Reload Enable Bits + * | | |0 = Falling capture reload counter Disabled. + * | | |1 = Falling capture reload counter Enabled. + * |[27] |FCRLDEN3 |Falling Capture Reload Enable Bits + * | | |0 = Falling capture reload counter Disabled. + * | | |1 = Falling capture reload counter Enabled. + * |[28] |FCRLDEN4 |Falling Capture Reload Enable Bits + * | | |0 = Falling capture reload counter Disabled. + * | | |1 = Falling capture reload counter Enabled. + * |[29] |FCRLDEN5 |Falling Capture Reload Enable Bits + * | | |0 = Falling capture reload counter Disabled. + * | | |1 = Falling capture reload counter Enabled. + * @var EPWM_T::CAPSTS + * Offset: 0x208 EPWM Capture Status Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[0] |CRLIFOV0 |Capture Rising Latch Interrupt Flag Overrun Status (Read Only) + * | | |This flag indicates if rising latch happened when the corresponding CRLIF is 1. + * | | |Note: This bit will be cleared automatically when user clear corresponding CRLIF. + * |[1] |CRLIFOV1 |Capture Rising Latch Interrupt Flag Overrun Status (Read Only) + * | | |This flag indicates if rising latch happened when the corresponding CRLIF is 1. + * | | |Note: This bit will be cleared automatically when user clear corresponding CRLIF. + * |[2] |CRLIFOV2 |Capture Rising Latch Interrupt Flag Overrun Status (Read Only) + * | | |This flag indicates if rising latch happened when the corresponding CRLIF is 1. + * | | |Note: This bit will be cleared automatically when user clear corresponding CRLIF. + * |[3] |CRLIFOV3 |Capture Rising Latch Interrupt Flag Overrun Status (Read Only) + * | | |This flag indicates if rising latch happened when the corresponding CRLIF is 1. + * | | |Note: This bit will be cleared automatically when user clear corresponding CRLIF. + * |[4] |CRLIFOV4 |Capture Rising Latch Interrupt Flag Overrun Status (Read Only) + * | | |This flag indicates if rising latch happened when the corresponding CRLIF is 1. + * | | |Note: This bit will be cleared automatically when user clear corresponding CRLIF. + * |[5] |CRLIFOV5 |Capture Rising Latch Interrupt Flag Overrun Status (Read Only) + * | | |This flag indicates if rising latch happened when the corresponding CRLIF is 1. + * | | |Note: This bit will be cleared automatically when user clear corresponding CRLIF. + * |[8] |CFLIFOV0 |Capture Falling Latch Interrupt Flag Overrun Status (Read Only) + * | | |This flag indicates if falling latch happened when the corresponding CFLIF is 1. + * | | |Note: This bit will be cleared automatically when user clear corresponding CFLIF. + * |[9] |CFLIFOV1 |Capture Falling Latch Interrupt Flag Overrun Status (Read Only) + * | | |This flag indicates if falling latch happened when the corresponding CFLIF is 1. + * | | |Note: This bit will be cleared automatically when user clear corresponding CFLIF. + * |[10] |CFLIFOV2 |Capture Falling Latch Interrupt Flag Overrun Status (Read Only) + * | | |This flag indicates if falling latch happened when the corresponding CFLIF is 1. + * | | |Note: This bit will be cleared automatically when user clear corresponding CFLIF. + * |[11] |CFLIFOV3 |Capture Falling Latch Interrupt Flag Overrun Status (Read Only) + * | | |This flag indicates if falling latch happened when the corresponding CFLIF is 1. + * | | |Note: This bit will be cleared automatically when user clear corresponding CFLIF. + * |[12] |CFLIFOV4 |Capture Falling Latch Interrupt Flag Overrun Status (Read Only) + * | | |This flag indicates if falling latch happened when the corresponding CFLIF is 1. + * | | |Note: This bit will be cleared automatically when user clear corresponding CFLIF. + * |[13] |CFLIFOV5 |Capture Falling Latch Interrupt Flag Overrun Status (Read Only) + * | | |This flag indicates if falling latch happened when the corresponding CFLIF is 1. + * | | |Note: This bit will be cleared automatically when user clear corresponding CFLIF. + * @var EPWM_T::RCAPDAT0 + * Offset: 0x20C EPWM Rising Capture Data Register 0 + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[15:0] |RCAPDAT |EPWM Rising Capture Data Register (Read Only) + * | | |When rising capture condition happened, the EPWM counter value will be saved in this register. + * @var EPWM_T::FCAPDAT0 + * Offset: 0x210 EPWM Falling Capture Data Register 0 + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[15:0] |FCAPDAT |EPWM Falling Capture Data Register (Read Only) + * | | |When falling capture condition happened, the EPWM counter value will be saved in this register. + * @var EPWM_T::RCAPDAT1 + * Offset: 0x214 EPWM Rising Capture Data Register 1 + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[15:0] |RCAPDAT |EPWM Rising Capture Data Register (Read Only) + * | | |When rising capture condition happened, the EPWM counter value will be saved in this register. + * @var EPWM_T::FCAPDAT1 + * Offset: 0x218 EPWM Falling Capture Data Register 1 + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[15:0] |FCAPDAT |EPWM Falling Capture Data Register (Read Only) + * | | |When falling capture condition happened, the EPWM counter value will be saved in this register. + * @var EPWM_T::RCAPDAT2 + * Offset: 0x21C EPWM Rising Capture Data Register 2 + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[15:0] |RCAPDAT |EPWM Rising Capture Data Register (Read Only) + * | | |When rising capture condition happened, the EPWM counter value will be saved in this register. + * @var EPWM_T::FCAPDAT2 + * Offset: 0x220 EPWM Falling Capture Data Register 2 + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[15:0] |FCAPDAT |EPWM Falling Capture Data Register (Read Only) + * | | |When falling capture condition happened, the EPWM counter value will be saved in this register. + * @var EPWM_T::RCAPDAT3 + * Offset: 0x224 EPWM Rising Capture Data Register 3 + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[15:0] |RCAPDAT |EPWM Rising Capture Data Register (Read Only) + * | | |When rising capture condition happened, the EPWM counter value will be saved in this register. + * @var EPWM_T::FCAPDAT3 + * Offset: 0x228 EPWM Falling Capture Data Register 3 + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[15:0] |FCAPDAT |EPWM Falling Capture Data Register (Read Only) + * | | |When falling capture condition happened, the EPWM counter value will be saved in this register. + * @var EPWM_T::RCAPDAT4 + * Offset: 0x22C EPWM Rising Capture Data Register 4 + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[15:0] |RCAPDAT |EPWM Rising Capture Data Register (Read Only) + * | | |When rising capture condition happened, the EPWM counter value will be saved in this register. + * @var EPWM_T::FCAPDAT4 + * Offset: 0x230 EPWM Falling Capture Data Register 4 + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[15:0] |FCAPDAT |EPWM Falling Capture Data Register (Read Only) + * | | |When falling capture condition happened, the EPWM counter value will be saved in this register. + * @var EPWM_T::RCAPDAT5 + * Offset: 0x234 EPWM Rising Capture Data Register 5 + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[15:0] |RCAPDAT |EPWM Rising Capture Data Register (Read Only) + * | | |When rising capture condition happened, the EPWM counter value will be saved in this register. + * @var EPWM_T::FCAPDAT5 + * Offset: 0x238 EPWM Falling Capture Data Register 5 + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[15:0] |FCAPDAT |EPWM Falling Capture Data Register (Read Only) + * | | |When falling capture condition happened, the EPWM counter value will be saved in this register. + * @var EPWM_T::PDMACTL + * Offset: 0x23C EPWM PDMA Control Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[0] |CHEN0_1 |Channel 0/1 PDMA Enable Bit + * | | |0 = Channel 0/1 PDMA function Disabled. + * | | |1 = Channel 0/1 PDMA function Enabled for the channel 0/1 captured data and transfer to memory. + * |[2:1] |CAPMOD0_1 |Select EPWM_RCAPDAT0/1 or EPWM_FCAPDAT0/1 to Do PDMA Transfer + * | | |00 = Reserved. + * | | |01 = EPWM_RCAPDAT0/1. + * | | |10 = EPWM_FCAPDAT0/1. + * | | |11 = Both EPWM_RCAPDAT0/1 and EPWM_FCAPDAT0/1. + * |[3] |CAPORD0_1 |Capture Channel 0/1 Rising/Falling Order + * | | |Set this bit to determine whether the EPWM_RCAPDAT0/1 or EPWM_FCAPDAT0/1 is the first captured data transferred to memory through PDMA when CAPMOD0_1 =11. + * | | |0 = EPWM_FCAPDAT0/1 is the first captured data to memory. + * | | |1 = EPWM_RCAPDAT0/1 is the first captured data to memory. + * |[4] |CHSEL0_1 |Select Channel 0/1 to Do PDMA Transfer + * | | |0 = Channel0. + * | | |1 = Channel1. + * |[8] |CHEN2_3 |Channel 2/3 PDMA Enable Bit + * | | |0 = Channel 2/3 PDMA function Disabled. + * | | |1 = Channel 2/3 PDMA function Enabled for the channel 2/3 captured data and transfer to memory. + * |[10:9] |CAPMOD2_3 |Select EPWM_RCAPDAT2/3 or EPWM_FCAODAT2/3 to Do PDMA Transfer + * | | |00 = Reserved. + * | | |01 = EPWM_RCAPDAT2/3. + * | | |10 = EPWM_FCAPDAT2/3. + * | | |11 = Both EPWM_RCAPDAT2/3 and EPWM_FCAPDAT2/3. + * |[11] |CAPORD2_3 |Capture Channel 2/3 Rising/Falling Order + * | | |Set this bit to determine whether the EPWM_RCAPDAT2/3 or EPWM_FCAPDAT2/3 is the first captured data transferred to memory through PDMA when CAPMOD2_3 =11. + * | | |0 = EPWM_FCAPDAT2/3 is the first captured data to memory. + * | | |1 = EPWM_RCAPDAT2/3 is the first captured data to memory. + * |[12] |CHSEL2_3 |Select Channel 2/3 to Do PDMA Transfer + * | | |0 = Channel2. + * | | |1 = Channel3. + * |[16] |CHEN4_5 |Channel 4/5 PDMA Enable Bit + * | | |0 = Channel 4/5 PDMA function Disabled. + * | | |1 = Channel 4/5 PDMA function Enabled for the channel 4/5 captured data and transfer to memory. + * |[18:17] |CAPMOD4_5 |Select EPWM_RCAPDAT4/5 or EPWM_FCAPDAT4/5 to Do PDMA Transfer + * | | |00 = Reserved. + * | | |01 = EPWM_RCAPDAT4/5. + * | | |10 = EPWM_FCAPDAT4/5. + * | | |11 = Both EPWM_RCAPDAT4/5 and EPWM_FCAPDAT4/5. + * |[19] |CAPORD4_5 |Capture Channel 4/5 Rising/Falling Order + * | | |Set this bit to determine whether the EPWM_RCAPDAT4/5 or EPWM_FCAPDAT4/5 is the first captured data transferred to memory through PDMA when CAPMOD4_5 =11. + * | | |0 = EPWM_FCAPDAT4/5 is the first captured data to memory. + * | | |1 = EPWM_RCAPDAT4/5 is the first captured data to memory. + * |[20] |CHSEL4_5 |Select Channel 4/5 to Do PDMA Transfer + * | | |0 = Channel4. + * | | |1 = Channel5. + * @var EPWM_T::PDMACAP0_1 + * Offset: 0x240 EPWM Capture Channel 01 PDMA Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[15:0] |CAPBUF |EPWM Capture PDMA Register (Read Only) + * | | |This register is used as a buffer to transfer EPWM capture rising or falling data to memory by PDMA. + * @var EPWM_T::PDMACAP2_3 + * Offset: 0x244 EPWM Capture Channel 23 PDMA Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[15:0] |CAPBUF |EPWM Capture PDMA Register (Read Only) + * | | |This register is used as a buffer to transfer EPWM capture rising or falling data to memory by PDMA. + * @var EPWM_T::PDMACAP4_5 + * Offset: 0x248 EPWM Capture Channel 45 PDMA Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[15:0] |CAPBUF |EPWM Capture PDMA Register (Read Only) + * | | |This register is used as a buffer to transfer EPWM capture rising or falling data to memory by PDMA. + * @var EPWM_T::CAPIEN + * Offset: 0x250 EPWM Capture Interrupt Enable Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[0] |CAPRIEN0 |EPWM Capture Rising Latch Interrupt Enable Bits + * | | |0 = Capture rising edge latch interrupt Disabled. + * | | |1 = Capture rising edge latch interrupt Enabled. + * |[1] |CAPRIEN1 |EPWM Capture Rising Latch Interrupt Enable Bits + * | | |0 = Capture rising edge latch interrupt Disabled. + * | | |1 = Capture rising edge latch interrupt Enabled. + * |[2] |CAPRIEN2 |EPWM Capture Rising Latch Interrupt Enable Bits + * | | |0 = Capture rising edge latch interrupt Disabled. + * | | |1 = Capture rising edge latch interrupt Enabled. + * |[3] |CAPRIEN3 |EPWM Capture Rising Latch Interrupt Enable Bits + * | | |0 = Capture rising edge latch interrupt Disabled. + * | | |1 = Capture rising edge latch interrupt Enabled. + * |[4] |CAPRIEN4 |EPWM Capture Rising Latch Interrupt Enable Bits + * | | |0 = Capture rising edge latch interrupt Disabled. + * | | |1 = Capture rising edge latch interrupt Enabled. + * |[5] |CAPRIEN5 |EPWM Capture Rising Latch Interrupt Enable Bits + * | | |0 = Capture rising edge latch interrupt Disabled. + * | | |1 = Capture rising edge latch interrupt Enabled. + * |[8] |CAPFIEN0 |EPWM Capture Falling Latch Interrupt Enable Bits + * | | |0 = Capture falling edge latch interrupt Disabled. + * | | |1 = Capture falling edge latch interrupt Enabled. + * |[9] |CAPFIEN1 |EPWM Capture Falling Latch Interrupt Enable Bits + * | | |0 = Capture falling edge latch interrupt Disabled. + * | | |1 = Capture falling edge latch interrupt Enabled. + * |[10] |CAPFIEN2 |EPWM Capture Falling Latch Interrupt Enable Bits + * | | |0 = Capture falling edge latch interrupt Disabled. + * | | |1 = Capture falling edge latch interrupt Enabled. + * |[11] |CAPFIEN3 |EPWM Capture Falling Latch Interrupt Enable Bits + * | | |0 = Capture falling edge latch interrupt Disabled. + * | | |1 = Capture falling edge latch interrupt Enabled. + * |[12] |CAPFIEN4 |EPWM Capture Falling Latch Interrupt Enable Bits + * | | |0 = Capture falling edge latch interrupt Disabled. + * | | |1 = Capture falling edge latch interrupt Enabled. + * |[13] |CAPFIEN5 |EPWM Capture Falling Latch Interrupt Enable Bits + * | | |0 = Capture falling edge latch interrupt Disabled. + * | | |1 = Capture falling edge latch interrupt Enabled. + * @var EPWM_T::CAPIF + * Offset: 0x254 EPWM Capture Interrupt Flag Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[0] |CRLIF0 |EPWM Capture Rising Latch Interrupt Flag + * | | |0 = No capture rising latch condition happened. + * | | |1 = Capture rising latch condition happened, this flag will be set to high. + * | | |Note 1: When Capture with PDMA operating, CAPIF corresponding channel CRLIF will be cleared by hardware after PDMA transfer data. + * | | |Note 2: This bit is cleared by writing 1 to it. + * |[1] |CRLIF1 |EPWM Capture Rising Latch Interrupt Flag + * | | |0 = No capture rising latch condition happened. + * | | |1 = Capture rising latch condition happened, this flag will be set to high. + * | | |Note 1: When Capture with PDMA operating, CAPIF corresponding channel CRLIF will be cleared by hardware after PDMA transfer data. + * | | |Note 2: This bit is cleared by writing 1 to it. + * |[2] |CRLIF2 |EPWM Capture Rising Latch Interrupt Flag + * | | |0 = No capture rising latch condition happened. + * | | |1 = Capture rising latch condition happened, this flag will be set to high. + * | | |Note 1: When Capture with PDMA operating, CAPIF corresponding channel CRLIF will be cleared by hardware after PDMA transfer data. + * | | |Note 2: This bit is cleared by writing 1 to it. + * |[3] |CRLIF3 |EPWM Capture Rising Latch Interrupt Flag + * | | |0 = No capture rising latch condition happened. + * | | |1 = Capture rising latch condition happened, this flag will be set to high. + * | | |Note 1: When Capture with PDMA operating, CAPIF corresponding channel CRLIF will be cleared by hardware after PDMA transfer data. + * | | |Note 2: This bit is cleared by writing 1 to it. + * |[4] |CRLIF4 |EPWM Capture Rising Latch Interrupt Flag + * | | |0 = No capture rising latch condition happened. + * | | |1 = Capture rising latch condition happened, this flag will be set to high. + * | | |Note 1: When Capture with PDMA operating, CAPIF corresponding channel CRLIF will be cleared by hardware after PDMA transfer data. + * | | |Note 2: This bit is cleared by writing 1 to it. + * |[5] |CRLIF5 |EPWM Capture Rising Latch Interrupt Flag + * | | |0 = No capture rising latch condition happened. + * | | |1 = Capture rising latch condition happened, this flag will be set to high. + * | | |Note 1: When Capture with PDMA operating, CAPIF corresponding channel CRLIF will be cleared by hardware after PDMA transfer data. + * | | |Note 2: This bit is cleared by writing 1 to it. + * |[8] |CFLIF0 |EPWM Capture Falling Latch Interrupt Flag + * | | |0 = No capture falling latch condition happened. + * | | |1 = Capture falling latch condition happened, this flag will be set to high. + * | | |Note 1: When Capture with PDMA operating, CAPIF corresponding channel CFLIF will be cleared by hardware after PDMA transfer data. + * | | |Note 2: This bit is cleared by writing 1 to it. + * |[9] |CFLIF1 |EPWM Capture Falling Latch Interrupt Flag + * | | |0 = No capture falling latch condition happened. + * | | |1 = Capture falling latch condition happened, this flag will be set to high. + * | | |Note 1: When Capture with PDMA operating, CAPIF corresponding channel CFLIF will be cleared by hardware after PDMA transfer data. + * | | |Note 2: This bit is cleared by writing 1 to it. + * |[10] |CFLIF2 |EPWM Capture Falling Latch Interrupt Flag + * | | |0 = No capture falling latch condition happened. + * | | |1 = Capture falling latch condition happened, this flag will be set to high. + * | | |Note 1: When Capture with PDMA operating, CAPIF corresponding channel CFLIF will be cleared by hardware after PDMA transfer data. + * | | |Note 2: This bit is cleared by writing 1 to it. + * |[11] |CFLIF3 |EPWM Capture Falling Latch Interrupt Flag + * | | |0 = No capture falling latch condition happened. + * | | |1 = Capture falling latch condition happened, this flag will be set to high. + * | | |Note 1: When Capture with PDMA operating, CAPIF corresponding channel CFLIF will be cleared by hardware after PDMA transfer data. + * | | |Note 2: This bit is cleared by writing 1 to it. + * |[12] |CFLIF4 |EPWM Capture Falling Latch Interrupt Flag + * | | |0 = No capture falling latch condition happened. + * | | |1 = Capture falling latch condition happened, this flag will be set to high. + * | | |Note 1: When Capture with PDMA operating, CAPIF corresponding channel CFLIF will be cleared by hardware after PDMA transfer data. + * | | |Note 2: This bit is cleared by writing 1 to it. + * |[13] |CFLIF5 |EPWM Capture Falling Latch Interrupt Flag + * | | |0 = No capture falling latch condition happened. + * | | |1 = Capture falling latch condition happened, this flag will be set to high. + * | | |Note 1: When Capture with PDMA operating, CAPIF corresponding channel CFLIF will be cleared by hardware after PDMA transfer data. + * | | |Note 2: This bit is cleared by writing 1 to it. + * @var EPWM_T::PBUF0 + * Offset: 0x304 EPWM PERIOD0 Buffer + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[15:0] |PBUF |EPWM Period Register Buffer (Read Only) + * | | |Used as PERIOD active register. + * @var EPWM_T::PBUF1 + * Offset: 0x308 EPWM PERIOD1 Buffer + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[15:0] |PBUF |EPWM Period Register Buffer (Read Only) + * | | |Used as PERIOD active register. + * @var EPWM_T::PBUF2 + * Offset: 0x30C EPWM PERIOD2 Buffer + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[15:0] |PBUF |EPWM Period Register Buffer (Read Only) + * | | |Used as PERIOD active register. + * @var EPWM_T::PBUF3 + * Offset: 0x310 EPWM PERIOD3 Buffer + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[15:0] |PBUF |EPWM Period Register Buffer (Read Only) + * | | |Used as PERIOD active register. + * @var EPWM_T::PBUF4 + * Offset: 0x314 EPWM PERIOD4 Buffer + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[15:0] |PBUF |EPWM Period Register Buffer (Read Only) + * | | |Used as PERIOD active register. + * @var EPWM_T::PBUF5 + * Offset: 0x318 EPWM PERIOD5 Buffer + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[15:0] |PBUF |EPWM Period Register Buffer (Read Only) + * | | |Used as PERIOD active register. + * @var EPWM_T::CMPBUF0 + * Offset: 0x31C EPWM CMPDAT0 Buffer + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[15:0] |CMPBUF |EPWM Comparator Register Buffer (Read Only) + * | | |Used as CMP active register. + * @var EPWM_T::CMPBUF1 + * Offset: 0x320 EPWM CMPDAT1 Buffer + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[15:0] |CMPBUF |EPWM Comparator Register Buffer (Read Only) + * | | |Used as CMP active register. + * @var EPWM_T::CMPBUF2 + * Offset: 0x324 EPWM CMPDAT2 Buffer + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[15:0] |CMPBUF |EPWM Comparator Register Buffer (Read Only) + * | | |Used as CMP active register. + * @var EPWM_T::CMPBUF3 + * Offset: 0x328 EPWM CMPDAT3 Buffer + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[15:0] |CMPBUF |EPWM Comparator Register Buffer (Read Only) + * | | |Used as CMP active register. + * @var EPWM_T::CMPBUF4 + * Offset: 0x32C EPWM CMPDAT4 Buffer + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[15:0] |CMPBUF |EPWM Comparator Register Buffer (Read Only) + * | | |Used as CMP active register. + * @var EPWM_T::CMPBUF5 + * Offset: 0x330 EPWM CMPDAT5 Buffer + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[15:0] |CMPBUF |EPWM Comparator Register Buffer (Read Only) + * | | |Used as CMP active register. + * @var EPWM_T::CPSCBUF0_1 + * Offset: 0x334 EPWM CLKPSC0_1 Buffer + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[11:0] |CPSCBUF |EPWM Counter Clock Prescale Buffer + * | | |Used as EPWM counter clock pre-scare active register. + * @var EPWM_T::CPSCBUF2_3 + * Offset: 0x338 EPWM CLKPSC2_3 Buffer + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[11:0] |CPSCBUF |EPWM Counter Clock Prescale Buffer + * | | |Used as EPWM counter clock pre-scare active register. + * @var EPWM_T::CPSCBUF4_5 + * Offset: 0x33C EPWM CLKPSC4_5 Buffer + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[11:0] |CPSCBUF |EPWM Counter Clock Prescale Buffer + * | | |Used as EPWM counter clock pre-scare active register. + * @var EPWM_T::FTCBUF0_1 + * Offset: 0x340 EPWM FTCMPDAT0_1 Buffer + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[15:0] |FTCMPBUF |EPWM FTCMPDAT Buffer (Read Only) + * | | |Used as FTCMPDAT active register. + * @var EPWM_T::FTCBUF2_3 + * Offset: 0x344 EPWM FTCMPDAT2_3 Buffer + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[15:0] |FTCMPBUF |EPWM FTCMPDAT Buffer (Read Only) + * | | |Used as FTCMPDAT active register. + * @var EPWM_T::FTCBUF4_5 + * Offset: 0x348 EPWM FTCMPDAT4_5 Buffer + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[15:0] |FTCMPBUF |EPWM FTCMPDAT Buffer (Read Only) + * | | |Used as FTCMPDAT active register. + * @var EPWM_T::FTCI + * Offset: 0x34C EPWM FTCMPDAT Indicator Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[0] |FTCMU0 |EPWM FTCMPDAT Up Indicator + * | | |Indicator is set by hardware when EPWM counter up count and reaches EPWM_FTCMPDATn, software can clear this bit by writing 1 to it. + * |[1] |FTCMU2 |EPWM FTCMPDAT Up Indicator + * | | |Indicator is set by hardware when EPWM counter up count and reaches EPWM_FTCMPDATn, software can clear this bit by writing 1 to it. + * |[2] |FTCMU4 |EPWM FTCMPDAT Up Indicator + * | | |Indicator is set by hardware when EPWM counter up count and reaches EPWM_FTCMPDATn, software can clear this bit by writing 1 to it. + * |[8] |FTCMD0 |EPWM FTCMPDAT Down Indicator + * | | |Indicator is set by hardware when EPWM counter down count and reaches EPWM_FTCMPDATn, software can clear this bit by writing 1 to it. + * |[9] |FTCMD2 |EPWM FTCMPDAT Down Indicator + * | | |Indicator is set by hardware when EPWM counter down count and reaches EPWM_FTCMPDATn, software can clear this bit by writing 1 to it. + * |[10] |FTCMD4 |EPWM FTCMPDAT Down Indicator + * | | |Indicator is set by hardware when EPWM counter down count and reaches EPWM_FTCMPDATn, software can clear this bit by writing 1 to it. + */ + __IO uint32_t CTL0; /*!< [0x0000] EPWM Control Register 0 */ + __IO uint32_t CTL1; /*!< [0x0004] EPWM Control Register 1 */ + __IO uint32_t SYNC; /*!< [0x0008] EPWM Synchronization Register */ + __IO uint32_t SWSYNC; /*!< [0x000c] EPWM Software Control Synchronization Register */ + __IO uint32_t CLKSRC; /*!< [0x0010] EPWM Clock Source Register */ + __IO uint32_t CLKPSC[3]; /*!< [0x0014] EPWM Clock Prescale Register 0/1,2/3,4/5 */ + __IO uint32_t CNTEN; /*!< [0x0020] EPWM Counter Enable Register */ + __IO uint32_t CNTCLR; /*!< [0x0024] EPWM Clear Counter Register */ + __IO uint32_t LOAD; /*!< [0x0028] EPWM Load Register */ + /// @cond HIDDEN_SYMBOLS + __I uint32_t RESERVE0[1]; + /// @endcond //HIDDEN_SYMBOLS + __IO uint32_t PERIOD[6]; /*!< [0x0030] EPWM Period Register 0~5 */ + /// @cond HIDDEN_SYMBOLS + __I uint32_t RESERVE1[2]; + /// @endcond //HIDDEN_SYMBOLS + __IO uint32_t CMPDAT[6]; /*!< [0x0050] EPWM Comparator Register 0~5 */ + /// @cond HIDDEN_SYMBOLS + __I uint32_t RESERVE2[2]; + /// @endcond //HIDDEN_SYMBOLS + __IO uint32_t DTCTL[3]; /*!< [0x0070] EPWM Dead-Time Control Register 0/1,2/3,4/5 */ + /// @cond HIDDEN_SYMBOLS + __I uint32_t RESERVE3[1]; + /// @endcond //HIDDEN_SYMBOLS + __IO uint32_t PHS[3]; /*!< [0x0080] EPWM Counter Phase Register 0/1,2/3,4/5 */ + /// @cond HIDDEN_SYMBOLS + __I uint32_t RESERVE4[1]; + /// @endcond //HIDDEN_SYMBOLS + __I uint32_t CNT[6]; /*!< [0x0090] EPWM Counter Register 0~5 */ + /// @cond HIDDEN_SYMBOLS + __I uint32_t RESERVE5[2]; + /// @endcond //HIDDEN_SYMBOLS + __IO uint32_t WGCTL0; /*!< [0x00b0] EPWM Generation Register 0 */ + __IO uint32_t WGCTL1; /*!< [0x00b4] EPWM Generation Register 1 */ + __IO uint32_t MSKEN; /*!< [0x00b8] EPWM Mask Enable Register */ + __IO uint32_t MSK; /*!< [0x00bc] EPWM Mask Data Register */ + __IO uint32_t BNF; /*!< [0x00c0] EPWM Brake Noise Filter Register */ + __IO uint32_t FAILBRK; /*!< [0x00c4] EPWM System Fail Brake Control Register */ + __IO uint32_t BRKCTL[3]; /*!< [0x00c8] EPWM Brake Edge Detect Control Register 0/1,2/3,4/5 */ + __IO uint32_t POLCTL; /*!< [0x00d4] EPWM Pin Polar Inverse Register */ + __IO uint32_t POEN; /*!< [0x00d8] EPWM Output Enable Register */ + __O uint32_t SWBRK; /*!< [0x00dc] EPWM Software Brake Control Register */ + __IO uint32_t INTEN0; /*!< [0x00e0] EPWM Interrupt Enable Register 0 */ + __IO uint32_t INTEN1; /*!< [0x00e4] EPWM Interrupt Enable Register 1 */ + __IO uint32_t INTSTS0; /*!< [0x00e8] EPWM Interrupt Flag Register 0 */ + __IO uint32_t INTSTS1; /*!< [0x00ec] EPWM Interrupt Flag Register 1 */ + /// @cond HIDDEN_SYMBOLS + __I uint32_t RESERVE6[1]; + /// @endcond //HIDDEN_SYMBOLS + __IO uint32_t DACTRGEN; /*!< [0x00f4] EPWM Trigger DAC Enable Register */ + __IO uint32_t EADCTS0; /*!< [0x00f8] EPWM Trigger EADC Source Select Register 0 */ + __IO uint32_t EADCTS1; /*!< [0x00fc] EPWM Trigger EADC Source Select Register 1 */ + __IO uint32_t FTCMPDAT[3]; /*!< [0x0100] EPWM Free Trigger Compare Register 0/1,2/3,4/5 */ + /// @cond HIDDEN_SYMBOLS + __I uint32_t RESERVE7[1]; + /// @endcond //HIDDEN_SYMBOLS + __IO uint32_t SSCTL; /*!< [0x0110] EPWM Synchronous Start Control Register */ + __O uint32_t SSTRG; /*!< [0x0114] EPWM Synchronous Start Trigger Register */ + __IO uint32_t LEBCTL; /*!< [0x0118] EPWM Leading Edge Blanking Control Register */ + __IO uint32_t LEBCNT; /*!< [0x011c] EPWM Leading Edge Blanking Counter Register */ + __IO uint32_t STATUS; /*!< [0x0120] EPWM Status Register */ + /// @cond HIDDEN_SYMBOLS + __I uint32_t RESERVE8[3]; + /// @endcond //HIDDEN_SYMBOLS + __IO uint32_t IFA[6]; /*!< [0x0130] EPWM Interrupt Flag Accumulator Register 0~5 */ + /// @cond HIDDEN_SYMBOLS + __I uint32_t RESERVE9[2]; + /// @endcond //HIDDEN_SYMBOLS + __IO uint32_t AINTSTS; /*!< [0x0150] EPWM Accumulator Interrupt Flag Register */ + __IO uint32_t AINTEN; /*!< [0x0154] EPWM Accumulator Interrupt Enable Register */ + __IO uint32_t APDMACTL; /*!< [0x0158] EPWM Accumulator PDMA Control Register */ + /// @cond HIDDEN_SYMBOLS + __I uint32_t RESERVE10[1]; + /// @endcond //HIDDEN_SYMBOLS + __IO uint32_t FDEN; /*!< [0x0160] EPWM Fault Detect Enable Register */ + __IO uint32_t FDCTL[6]; /*!< [0x0164~0x178] EPWM Fault Detect Control Register 0~5 */ + __IO uint32_t FDIEN; /*!< [0x017C] EPWM Fault Detect Interrupt Enable Register */ + __IO uint32_t FDSTS; /*!< [0x0180] EPWM Fault Detect Interrupt Flag Register */ + __IO uint32_t EADCPSCCTL; /*!< [0x0184] EPWM Trigger EADC Prescale Control Register */ + __IO uint32_t EADCPSC0; /*!< [0x0188] EPWM Trigger EADC Prescale Register 0 */ + __IO uint32_t EADCPSC1; /*!< [0x018C] EPWM Trigger EADC Prescale Register 1 */ + __IO uint32_t EADCPSCNT0; /*!< [0x0190] EPWM Trigger EADC Prescale Counter Register 0 */ + __IO uint32_t EADCPSCNT1; /*!< [0x0194] EPWM Trigger EADC Prescale Counter Register 1 */ + /// @cond HIDDEN_SYMBOLS + __I uint32_t RESERVE11[26]; + /// @endcond //HIDDEN_SYMBOLS + __IO uint32_t CAPINEN; /*!< [0x0200] EPWM Capture Input Enable Register */ + __IO uint32_t CAPCTL; /*!< [0x0204] EPWM Capture Control Register */ + __I uint32_t CAPSTS; /*!< [0x0208] EPWM Capture Status Register */ + ECAPDAT_T CAPDAT[6]; /*!< [0x020C] EPWM Rising and Falling Capture Data Register 0~5 */ + __IO uint32_t PDMACTL; /*!< [0x023c] EPWM PDMA Control Register */ + __I uint32_t PDMACAP[3]; /*!< [0x0240] EPWM Capture Channel 01,23,45 PDMA Register */ + /// @cond HIDDEN_SYMBOLS + __I uint32_t RESERVE12[1]; + /// @endcond //HIDDEN_SYMBOLS + __IO uint32_t CAPIEN; /*!< [0x0250] EPWM Capture Interrupt Enable Register */ + __IO uint32_t CAPIF; /*!< [0x0254] EPWM Capture Interrupt Flag Register */ + /// @cond HIDDEN_SYMBOLS + __I uint32_t RESERVE13[43]; + /// @endcond //HIDDEN_SYMBOLS + __I uint32_t PBUF[6]; /*!< [0x0304] EPWM PERIOD0~5 Buffer */ + __I uint32_t CMPBUF[6]; /*!< [0x031c] EPWM CMPDAT0~5 Buffer */ + __I uint32_t CPSCBUF[3]; /*!< [0x0334] EPWM CLKPSC0_1/2_3/4_5 Buffer */ + __I uint32_t FTCBUF[3]; /*!< [0x0340] EPWM FTCMPDAT0_1/2_3/4_5 Buffer */ + __IO uint32_t FTCI; /*!< [0x034c] EPWM FTCMPDAT Indicator Register */ + +} EPWM_T; + +/** + @addtogroup EPWM_CONST EPWM Bit Field Definition + Constant Definitions for EPWM Controller +@{ */ + +#define EPWM_CTL0_CTRLD0_Pos (0) /*!< EPWM_T::CTL0: CTRLD0 Position */ +#define EPWM_CTL0_CTRLD0_Msk (0x1ul << EPWM_CTL0_CTRLD0_Pos) /*!< EPWM_T::CTL0: CTRLD0 Mask */ + +#define EPWM_CTL0_CTRLD1_Pos (1) /*!< EPWM_T::CTL0: CTRLD1 Position */ +#define EPWM_CTL0_CTRLD1_Msk (0x1ul << EPWM_CTL0_CTRLD1_Pos) /*!< EPWM_T::CTL0: CTRLD1 Mask */ + +#define EPWM_CTL0_CTRLD2_Pos (2) /*!< EPWM_T::CTL0: CTRLD2 Position */ +#define EPWM_CTL0_CTRLD2_Msk (0x1ul << EPWM_CTL0_CTRLD2_Pos) /*!< EPWM_T::CTL0: CTRLD2 Mask */ + +#define EPWM_CTL0_CTRLD3_Pos (3) /*!< EPWM_T::CTL0: CTRLD3 Position */ +#define EPWM_CTL0_CTRLD3_Msk (0x1ul << EPWM_CTL0_CTRLD3_Pos) /*!< EPWM_T::CTL0: CTRLD3 Mask */ + +#define EPWM_CTL0_CTRLD4_Pos (4) /*!< EPWM_T::CTL0: CTRLD4 Position */ +#define EPWM_CTL0_CTRLD4_Msk (0x1ul << EPWM_CTL0_CTRLD4_Pos) /*!< EPWM_T::CTL0: CTRLD4 Mask */ + +#define EPWM_CTL0_CTRLD5_Pos (5) /*!< EPWM_T::CTL0: CTRLD5 Position */ +#define EPWM_CTL0_CTRLD5_Msk (0x1ul << EPWM_CTL0_CTRLD5_Pos) /*!< EPWM_T::CTL0: CTRLD5 Mask */ + +#define EPWM_CTL0_WINLDEN0_Pos (8) /*!< EPWM_T::CTL0: WINLDEN0 Position */ +#define EPWM_CTL0_WINLDEN0_Msk (0x1ul << EPWM_CTL0_WINLDEN0_Pos) /*!< EPWM_T::CTL0: WINLDEN0 Mask */ + +#define EPWM_CTL0_WINLDEN1_Pos (9) /*!< EPWM_T::CTL0: WINLDEN1 Position */ +#define EPWM_CTL0_WINLDEN1_Msk (0x1ul << EPWM_CTL0_WINLDEN1_Pos) /*!< EPWM_T::CTL0: WINLDEN1 Mask */ + +#define EPWM_CTL0_WINLDEN2_Pos (10) /*!< EPWM_T::CTL0: WINLDEN2 Position */ +#define EPWM_CTL0_WINLDEN2_Msk (0x1ul << EPWM_CTL0_WINLDEN2_Pos) /*!< EPWM_T::CTL0: WINLDEN2 Mask */ + +#define EPWM_CTL0_WINLDEN3_Pos (11) /*!< EPWM_T::CTL0: WINLDEN3 Position */ +#define EPWM_CTL0_WINLDEN3_Msk (0x1ul << EPWM_CTL0_WINLDEN3_Pos) /*!< EPWM_T::CTL0: WINLDEN3 Mask */ + +#define EPWM_CTL0_WINLDEN4_Pos (12) /*!< EPWM_T::CTL0: WINLDEN4 Position */ +#define EPWM_CTL0_WINLDEN4_Msk (0x1ul << EPWM_CTL0_WINLDEN4_Pos) /*!< EPWM_T::CTL0: WINLDEN4 Mask */ + +#define EPWM_CTL0_WINLDEN5_Pos (13) /*!< EPWM_T::CTL0: WINLDEN5 Position */ +#define EPWM_CTL0_WINLDEN5_Msk (0x1ul << EPWM_CTL0_WINLDEN5_Pos) /*!< EPWM_T::CTL0: WINLDEN5 Mask */ + +#define EPWM_CTL0_IMMLDEN0_Pos (16) /*!< EPWM_T::CTL0: IMMLDEN0 Position */ +#define EPWM_CTL0_IMMLDEN0_Msk (0x1ul << EPWM_CTL0_IMMLDEN0_Pos) /*!< EPWM_T::CTL0: IMMLDEN0 Mask */ + +#define EPWM_CTL0_IMMLDEN1_Pos (17) /*!< EPWM_T::CTL0: IMMLDEN1 Position */ +#define EPWM_CTL0_IMMLDEN1_Msk (0x1ul << EPWM_CTL0_IMMLDEN1_Pos) /*!< EPWM_T::CTL0: IMMLDEN1 Mask */ + +#define EPWM_CTL0_IMMLDEN2_Pos (18) /*!< EPWM_T::CTL0: IMMLDEN2 Position */ +#define EPWM_CTL0_IMMLDEN2_Msk (0x1ul << EPWM_CTL0_IMMLDEN2_Pos) /*!< EPWM_T::CTL0: IMMLDEN2 Mask */ + +#define EPWM_CTL0_IMMLDEN3_Pos (19) /*!< EPWM_T::CTL0: IMMLDEN3 Position */ +#define EPWM_CTL0_IMMLDEN3_Msk (0x1ul << EPWM_CTL0_IMMLDEN3_Pos) /*!< EPWM_T::CTL0: IMMLDEN3 Mask */ + +#define EPWM_CTL0_IMMLDEN4_Pos (20) /*!< EPWM_T::CTL0: IMMLDEN4 Position */ +#define EPWM_CTL0_IMMLDEN4_Msk (0x1ul << EPWM_CTL0_IMMLDEN4_Pos) /*!< EPWM_T::CTL0: IMMLDEN4 Mask */ + +#define EPWM_CTL0_IMMLDEN5_Pos (21) /*!< EPWM_T::CTL0: IMMLDEN5 Position */ +#define EPWM_CTL0_IMMLDEN5_Msk (0x1ul << EPWM_CTL0_IMMLDEN5_Pos) /*!< EPWM_T::CTL0: IMMLDEN5 Mask */ + +#define EPWM_CTL0_GROUPEN_Pos (24) /*!< EPWM_T::CTL0: GROUPEN Position */ +#define EPWM_CTL0_GROUPEN_Msk (0x1ul << EPWM_CTL0_GROUPEN_Pos) /*!< EPWM_T::CTL0: GROUPEN Mask */ + +#define EPWM_CTL0_DBGHALT_Pos (30) /*!< EPWM_T::CTL0: DBGHALT Position */ +#define EPWM_CTL0_DBGHALT_Msk (0x1ul << EPWM_CTL0_DBGHALT_Pos) /*!< EPWM_T::CTL0: DBGHALT Mask */ + +#define EPWM_CTL0_DBGTRIOFF_Pos (31) /*!< EPWM_T::CTL0: DBGTRIOFF Position */ +#define EPWM_CTL0_DBGTRIOFF_Msk (0x1ul << EPWM_CTL0_DBGTRIOFF_Pos) /*!< EPWM_T::CTL0: DBGTRIOFF Mask */ + +#define EPWM_CTL1_CNTTYPE0_Pos (0) /*!< EPWM_T::CTL1: CNTTYPE0 Position */ +#define EPWM_CTL1_CNTTYPE0_Msk (0x3ul << EPWM_CTL1_CNTTYPE0_Pos) /*!< EPWM_T::CTL1: CNTTYPE0 Mask */ + +#define EPWM_CTL1_CNTTYPE1_Pos (2) /*!< EPWM_T::CTL1: CNTTYPE1 Position */ +#define EPWM_CTL1_CNTTYPE1_Msk (0x3ul << EPWM_CTL1_CNTTYPE1_Pos) /*!< EPWM_T::CTL1: CNTTYPE1 Mask */ + +#define EPWM_CTL1_CNTTYPE2_Pos (4) /*!< EPWM_T::CTL1: CNTTYPE2 Position */ +#define EPWM_CTL1_CNTTYPE2_Msk (0x3ul << EPWM_CTL1_CNTTYPE2_Pos) /*!< EPWM_T::CTL1: CNTTYPE2 Mask */ + +#define EPWM_CTL1_CNTTYPE3_Pos (6) /*!< EPWM_T::CTL1: CNTTYPE3 Position */ +#define EPWM_CTL1_CNTTYPE3_Msk (0x3ul << EPWM_CTL1_CNTTYPE3_Pos) /*!< EPWM_T::CTL1: CNTTYPE3 Mask */ + +#define EPWM_CTL1_CNTTYPE4_Pos (8) /*!< EPWM_T::CTL1: CNTTYPE4 Position */ +#define EPWM_CTL1_CNTTYPE4_Msk (0x3ul << EPWM_CTL1_CNTTYPE4_Pos) /*!< EPWM_T::CTL1: CNTTYPE4 Mask */ + +#define EPWM_CTL1_CNTTYPE5_Pos (10) /*!< EPWM_T::CTL1: CNTTYPE5 Position */ +#define EPWM_CTL1_CNTTYPE5_Msk (0x3ul << EPWM_CTL1_CNTTYPE5_Pos) /*!< EPWM_T::CTL1: CNTTYPE5 Mask */ + +#define EPWM_CTL1_CNTMODE0_Pos (16) /*!< EPWM_T::CTL1: CNTMODE0 Position */ +#define EPWM_CTL1_CNTMODE0_Msk (0x1ul << EPWM_CTL1_CNTMODE0_Pos) /*!< EPWM_T::CTL1: CNTMODE0 Mask */ + +#define EPWM_CTL1_CNTMODE1_Pos (17) /*!< EPWM_T::CTL1: CNTMODE1 Position */ +#define EPWM_CTL1_CNTMODE1_Msk (0x1ul << EPWM_CTL1_CNTMODE1_Pos) /*!< EPWM_T::CTL1: CNTMODE1 Mask */ + +#define EPWM_CTL1_CNTMODE2_Pos (18) /*!< EPWM_T::CTL1: CNTMODE2 Position */ +#define EPWM_CTL1_CNTMODE2_Msk (0x1ul << EPWM_CTL1_CNTMODE2_Pos) /*!< EPWM_T::CTL1: CNTMODE2 Mask */ + +#define EPWM_CTL1_CNTMODE3_Pos (19) /*!< EPWM_T::CTL1: CNTMODE3 Position */ +#define EPWM_CTL1_CNTMODE3_Msk (0x1ul << EPWM_CTL1_CNTMODE3_Pos) /*!< EPWM_T::CTL1: CNTMODE3 Mask */ + +#define EPWM_CTL1_CNTMODE4_Pos (20) /*!< EPWM_T::CTL1: CNTMODE4 Position */ +#define EPWM_CTL1_CNTMODE4_Msk (0x1ul << EPWM_CTL1_CNTMODE4_Pos) /*!< EPWM_T::CTL1: CNTMODE4 Mask */ + +#define EPWM_CTL1_CNTMODE5_Pos (21) /*!< EPWM_T::CTL1: CNTMODE5 Position */ +#define EPWM_CTL1_CNTMODE5_Msk (0x1ul << EPWM_CTL1_CNTMODE5_Pos) /*!< EPWM_T::CTL1: CNTMODE5 Mask */ + +#define EPWM_CTL1_OUTMODE0_Pos (24) /*!< EPWM_T::CTL1: OUTMODE0 Position */ +#define EPWM_CTL1_OUTMODE0_Msk (0x1ul << EPWM_CTL1_OUTMODE0_Pos) /*!< EPWM_T::CTL1: OUTMODE0 Mask */ + +#define EPWM_CTL1_OUTMODE2_Pos (25) /*!< EPWM_T::CTL1: OUTMODE2 Position */ +#define EPWM_CTL1_OUTMODE2_Msk (0x1ul << EPWM_CTL1_OUTMODE2_Pos) /*!< EPWM_T::CTL1: OUTMODE2 Mask */ + +#define EPWM_CTL1_OUTMODE4_Pos (26) /*!< EPWM_T::CTL1: OUTMODE4 Position */ +#define EPWM_CTL1_OUTMODE4_Msk (0x1ul << EPWM_CTL1_OUTMODE4_Pos) /*!< EPWM_T::CTL1: OUTMODE4 Mask */ + +#define EPWM_SYNC_PHSEN0_Pos (0) /*!< EPWM_T::SYNC: PHSEN0 Position */ +#define EPWM_SYNC_PHSEN0_Msk (0x1ul << EPWM_SYNC_PHSEN0_Pos) /*!< EPWM_T::SYNC: PHSEN0 Mask */ + +#define EPWM_SYNC_PHSEN2_Pos (1) /*!< EPWM_T::SYNC: PHSEN2 Position */ +#define EPWM_SYNC_PHSEN2_Msk (0x1ul << EPWM_SYNC_PHSEN2_Pos) /*!< EPWM_T::SYNC: PHSEN2 Mask */ + +#define EPWM_SYNC_PHSEN4_Pos (2) /*!< EPWM_T::SYNC: PHSEN4 Position */ +#define EPWM_SYNC_PHSEN4_Msk (0x1ul << EPWM_SYNC_PHSEN4_Pos) /*!< EPWM_T::SYNC: PHSEN4 Mask */ + +#define EPWM_SYNC_SINSRC0_Pos (8) /*!< EPWM_T::SYNC: SINSRC0 Position */ +#define EPWM_SYNC_SINSRC0_Msk (0x3ul << EPWM_SYNC_SINSRC0_Pos) /*!< EPWM_T::SYNC: SINSRC0 Mask */ + +#define EPWM_SYNC_SINSRC2_Pos (10) /*!< EPWM_T::SYNC: SINSRC2 Position */ +#define EPWM_SYNC_SINSRC2_Msk (0x3ul << EPWM_SYNC_SINSRC2_Pos) /*!< EPWM_T::SYNC: SINSRC2 Mask */ + +#define EPWM_SYNC_SINSRC4_Pos (12) /*!< EPWM_T::SYNC: SINSRC4 Position */ +#define EPWM_SYNC_SINSRC4_Msk (0x3ul << EPWM_SYNC_SINSRC4_Pos) /*!< EPWM_T::SYNC: SINSRC4 Mask */ + +#define EPWM_SYNC_SNFLTEN_Pos (16) /*!< EPWM_T::SYNC: SNFLTEN Position */ +#define EPWM_SYNC_SNFLTEN_Msk (0x1ul << EPWM_SYNC_SNFLTEN_Pos) /*!< EPWM_T::SYNC: SNFLTEN Mask */ + +#define EPWM_SYNC_SFLTCSEL_Pos (17) /*!< EPWM_T::SYNC: SFLTCSEL Position */ +#define EPWM_SYNC_SFLTCSEL_Msk (0x7ul << EPWM_SYNC_SFLTCSEL_Pos) /*!< EPWM_T::SYNC: SFLTCSEL Mask */ + +#define EPWM_SYNC_SFLTCNT_Pos (20) /*!< EPWM_T::SYNC: SFLTCNT Position */ +#define EPWM_SYNC_SFLTCNT_Msk (0x7ul << EPWM_SYNC_SFLTCNT_Pos) /*!< EPWM_T::SYNC: SFLTCNT Mask */ + +#define EPWM_SYNC_SINPINV_Pos (23) /*!< EPWM_T::SYNC: SINPINV Position */ +#define EPWM_SYNC_SINPINV_Msk (0x1ul << EPWM_SYNC_SINPINV_Pos) /*!< EPWM_T::SYNC: SINPINV Mask */ + +#define EPWM_SYNC_PHSDIR0_Pos (24) /*!< EPWM_T::SYNC: PHSDIR0 Position */ +#define EPWM_SYNC_PHSDIR0_Msk (0x1ul << EPWM_SYNC_PHSDIR0_Pos) /*!< EPWM_T::SYNC: PHSDIR0 Mask */ + +#define EPWM_SYNC_PHSDIR2_Pos (25) /*!< EPWM_T::SYNC: PHSDIR2 Position */ +#define EPWM_SYNC_PHSDIR2_Msk (0x1ul << EPWM_SYNC_PHSDIR2_Pos) /*!< EPWM_T::SYNC: PHSDIR2 Mask */ + +#define EPWM_SYNC_PHSDIR4_Pos (26) /*!< EPWM_T::SYNC: PHSDIR4 Position */ +#define EPWM_SYNC_PHSDIR4_Msk (0x1ul << EPWM_SYNC_PHSDIR4_Pos) /*!< EPWM_T::SYNC: PHSDIR4 Mask */ + +#define EPWM_SWSYNC_SWSYNC0_Pos (0) /*!< EPWM_T::SWSYNC: SWSYNC0 Position */ +#define EPWM_SWSYNC_SWSYNC0_Msk (0x1ul << EPWM_SWSYNC_SWSYNC0_Pos) /*!< EPWM_T::SWSYNC: SWSYNC0 Mask */ + +#define EPWM_SWSYNC_SWSYNC2_Pos (1) /*!< EPWM_T::SWSYNC: SWSYNC2 Position */ +#define EPWM_SWSYNC_SWSYNC2_Msk (0x1ul << EPWM_SWSYNC_SWSYNC2_Pos) /*!< EPWM_T::SWSYNC: SWSYNC2 Mask */ + +#define EPWM_SWSYNC_SWSYNC4_Pos (2) /*!< EPWM_T::SWSYNC: SWSYNC4 Position */ +#define EPWM_SWSYNC_SWSYNC4_Msk (0x1ul << EPWM_SWSYNC_SWSYNC4_Pos) /*!< EPWM_T::SWSYNC: SWSYNC4 Mask */ + +#define EPWM_CLKSRC_ECLKSRC0_Pos (0) /*!< EPWM_T::CLKSRC: ECLKSRC0 Position */ +#define EPWM_CLKSRC_ECLKSRC0_Msk (0xful << EPWM_CLKSRC_ECLKSRC0_Pos) /*!< EPWM_T::CLKSRC: ECLKSRC0 Mask */ + +#define EPWM_CLKSRC_ECLKSRC2_Pos (8) /*!< EPWM_T::CLKSRC: ECLKSRC2 Position */ +#define EPWM_CLKSRC_ECLKSRC2_Msk (0xful << EPWM_CLKSRC_ECLKSRC2_Pos) /*!< EPWM_T::CLKSRC: ECLKSRC2 Mask */ + +#define EPWM_CLKSRC_ECLKSRC4_Pos (16) /*!< EPWM_T::CLKSRC: ECLKSRC4 Position */ +#define EPWM_CLKSRC_ECLKSRC4_Msk (0xful << EPWM_CLKSRC_ECLKSRC4_Pos) /*!< EPWM_T::CLKSRC: ECLKSRC4 Mask */ + +#define EPWM_CLKPSC0_1_CLKPSC_Pos (0) /*!< EPWM_T::CLKPSC0_1: CLKPSC Position */ +#define EPWM_CLKPSC0_1_CLKPSC_Msk (0xffful << EPWM_CLKPSC0_1_CLKPSC_Pos) /*!< EPWM_T::CLKPSC0_1: CLKPSC Mask */ + +#define EPWM_CLKPSC2_3_CLKPSC_Pos (0) /*!< EPWM_T::CLKPSC2_3: CLKPSC Position */ +#define EPWM_CLKPSC2_3_CLKPSC_Msk (0xffful << EPWM_CLKPSC2_3_CLKPSC_Pos) /*!< EPWM_T::CLKPSC2_3: CLKPSC Mask */ + +#define EPWM_CLKPSC4_5_CLKPSC_Pos (0) /*!< EPWM_T::CLKPSC4_5: CLKPSC Position */ +#define EPWM_CLKPSC4_5_CLKPSC_Msk (0xffful << EPWM_CLKPSC4_5_CLKPSC_Pos) /*!< EPWM_T::CLKPSC4_5: CLKPSC Mask */ + +#define EPWM_CNTEN_CNTEN0_Pos (0) /*!< EPWM_T::CNTEN: CNTEN0 Position */ +#define EPWM_CNTEN_CNTEN0_Msk (0x1ul << EPWM_CNTEN_CNTEN0_Pos) /*!< EPWM_T::CNTEN: CNTEN0 Mask */ + +#define EPWM_CNTEN_CNTEN1_Pos (1) /*!< EPWM_T::CNTEN: CNTEN1 Position */ +#define EPWM_CNTEN_CNTEN1_Msk (0x1ul << EPWM_CNTEN_CNTEN1_Pos) /*!< EPWM_T::CNTEN: CNTEN1 Mask */ + +#define EPWM_CNTEN_CNTEN2_Pos (2) /*!< EPWM_T::CNTEN: CNTEN2 Position */ +#define EPWM_CNTEN_CNTEN2_Msk (0x1ul << EPWM_CNTEN_CNTEN2_Pos) /*!< EPWM_T::CNTEN: CNTEN2 Mask */ + +#define EPWM_CNTEN_CNTEN3_Pos (3) /*!< EPWM_T::CNTEN: CNTEN3 Position */ +#define EPWM_CNTEN_CNTEN3_Msk (0x1ul << EPWM_CNTEN_CNTEN3_Pos) /*!< EPWM_T::CNTEN: CNTEN3 Mask */ + +#define EPWM_CNTEN_CNTEN4_Pos (4) /*!< EPWM_T::CNTEN: CNTEN4 Position */ +#define EPWM_CNTEN_CNTEN4_Msk (0x1ul << EPWM_CNTEN_CNTEN4_Pos) /*!< EPWM_T::CNTEN: CNTEN4 Mask */ + +#define EPWM_CNTEN_CNTEN5_Pos (5) /*!< EPWM_T::CNTEN: CNTEN5 Position */ +#define EPWM_CNTEN_CNTEN5_Msk (0x1ul << EPWM_CNTEN_CNTEN5_Pos) /*!< EPWM_T::CNTEN: CNTEN5 Mask */ + +#define EPWM_CNTCLR_CNTCLR0_Pos (0) /*!< EPWM_T::CNTCLR: CNTCLR0 Position */ +#define EPWM_CNTCLR_CNTCLR0_Msk (0x1ul << EPWM_CNTCLR_CNTCLR0_Pos) /*!< EPWM_T::CNTCLR: CNTCLR0 Mask */ + +#define EPWM_CNTCLR_CNTCLR1_Pos (1) /*!< EPWM_T::CNTCLR: CNTCLR1 Position */ +#define EPWM_CNTCLR_CNTCLR1_Msk (0x1ul << EPWM_CNTCLR_CNTCLR1_Pos) /*!< EPWM_T::CNTCLR: CNTCLR1 Mask */ + +#define EPWM_CNTCLR_CNTCLR2_Pos (2) /*!< EPWM_T::CNTCLR: CNTCLR2 Position */ +#define EPWM_CNTCLR_CNTCLR2_Msk (0x1ul << EPWM_CNTCLR_CNTCLR2_Pos) /*!< EPWM_T::CNTCLR: CNTCLR2 Mask */ + +#define EPWM_CNTCLR_CNTCLR3_Pos (3) /*!< EPWM_T::CNTCLR: CNTCLR3 Position */ +#define EPWM_CNTCLR_CNTCLR3_Msk (0x1ul << EPWM_CNTCLR_CNTCLR3_Pos) /*!< EPWM_T::CNTCLR: CNTCLR3 Mask */ + +#define EPWM_CNTCLR_CNTCLR4_Pos (4) /*!< EPWM_T::CNTCLR: CNTCLR4 Position */ +#define EPWM_CNTCLR_CNTCLR4_Msk (0x1ul << EPWM_CNTCLR_CNTCLR4_Pos) /*!< EPWM_T::CNTCLR: CNTCLR4 Mask */ + +#define EPWM_CNTCLR_CNTCLR5_Pos (5) /*!< EPWM_T::CNTCLR: CNTCLR5 Position */ +#define EPWM_CNTCLR_CNTCLR5_Msk (0x1ul << EPWM_CNTCLR_CNTCLR5_Pos) /*!< EPWM_T::CNTCLR: CNTCLR5 Mask */ + +#define EPWM_LOAD_LOAD0_Pos (0) /*!< EPWM_T::LOAD: LOAD0 Position */ +#define EPWM_LOAD_LOAD0_Msk (0x1ul << EPWM_LOAD_LOAD0_Pos) /*!< EPWM_T::LOAD: LOAD0 Mask */ + +#define EPWM_LOAD_LOAD1_Pos (1) /*!< EPWM_T::LOAD: LOAD1 Position */ +#define EPWM_LOAD_LOAD1_Msk (0x1ul << EPWM_LOAD_LOAD1_Pos) /*!< EPWM_T::LOAD: LOAD1 Mask */ + +#define EPWM_LOAD_LOAD2_Pos (2) /*!< EPWM_T::LOAD: LOAD2 Position */ +#define EPWM_LOAD_LOAD2_Msk (0x1ul << EPWM_LOAD_LOAD2_Pos) /*!< EPWM_T::LOAD: LOAD2 Mask */ + +#define EPWM_LOAD_LOAD3_Pos (3) /*!< EPWM_T::LOAD: LOAD3 Position */ +#define EPWM_LOAD_LOAD3_Msk (0x1ul << EPWM_LOAD_LOAD3_Pos) /*!< EPWM_T::LOAD: LOAD3 Mask */ + +#define EPWM_LOAD_LOAD4_Pos (4) /*!< EPWM_T::LOAD: LOAD4 Position */ +#define EPWM_LOAD_LOAD4_Msk (0x1ul << EPWM_LOAD_LOAD4_Pos) /*!< EPWM_T::LOAD: LOAD4 Mask */ + +#define EPWM_LOAD_LOAD5_Pos (5) /*!< EPWM_T::LOAD: LOAD5 Position */ +#define EPWM_LOAD_LOAD5_Msk (0x1ul << EPWM_LOAD_LOAD5_Pos) /*!< EPWM_T::LOAD: LOAD5 Mask */ + +#define EPWM_PERIOD0_PERIOD_Pos (0) /*!< EPWM_T::PERIOD0: PERIOD Position */ +#define EPWM_PERIOD0_PERIOD_Msk (0xfffful << EPWM_PERIOD0_PERIOD_Pos) /*!< EPWM_T::PERIOD0: PERIOD Mask */ + +#define EPWM_PERIOD1_PERIOD_Pos (0) /*!< EPWM_T::PERIOD1: PERIOD Position */ +#define EPWM_PERIOD1_PERIOD_Msk (0xfffful << EPWM_PERIOD1_PERIOD_Pos) /*!< EPWM_T::PERIOD1: PERIOD Mask */ + +#define EPWM_PERIOD2_PERIOD_Pos (0) /*!< EPWM_T::PERIOD2: PERIOD Position */ +#define EPWM_PERIOD2_PERIOD_Msk (0xfffful << EPWM_PERIOD2_PERIOD_Pos) /*!< EPWM_T::PERIOD2: PERIOD Mask */ + +#define EPWM_PERIOD3_PERIOD_Pos (0) /*!< EPWM_T::PERIOD3: PERIOD Position */ +#define EPWM_PERIOD3_PERIOD_Msk (0xfffful << EPWM_PERIOD3_PERIOD_Pos) /*!< EPWM_T::PERIOD3: PERIOD Mask */ + +#define EPWM_PERIOD4_PERIOD_Pos (0) /*!< EPWM_T::PERIOD4: PERIOD Position */ +#define EPWM_PERIOD4_PERIOD_Msk (0xfffful << EPWM_PERIOD4_PERIOD_Pos) /*!< EPWM_T::PERIOD4: PERIOD Mask */ + +#define EPWM_PERIOD5_PERIOD_Pos (0) /*!< EPWM_T::PERIOD5: PERIOD Position */ +#define EPWM_PERIOD5_PERIOD_Msk (0xfffful << EPWM_PERIOD5_PERIOD_Pos) /*!< EPWM_T::PERIOD5: PERIOD Mask */ + +#define EPWM_CMPDAT0_CMP_Pos (0) /*!< EPWM_T::CMPDAT0: CMP Position */ +#define EPWM_CMPDAT0_CMP_Msk (0xfffful << EPWM_CMPDAT0_CMP_Pos) /*!< EPWM_T::CMPDAT0: CMP Mask */ + +#define EPWM_CMPDAT1_CMP_Pos (0) /*!< EPWM_T::CMPDAT1: CMP Position */ +#define EPWM_CMPDAT1_CMP_Msk (0xfffful << EPWM_CMPDAT1_CMP_Pos) /*!< EPWM_T::CMPDAT1: CMP Mask */ + +#define EPWM_CMPDAT2_CMP_Pos (0) /*!< EPWM_T::CMPDAT2: CMP Position */ +#define EPWM_CMPDAT2_CMP_Msk (0xfffful << EPWM_CMPDAT2_CMP_Pos) /*!< EPWM_T::CMPDAT2: CMP Mask */ + +#define EPWM_CMPDAT3_CMP_Pos (0) /*!< EPWM_T::CMPDAT3: CMP Position */ +#define EPWM_CMPDAT3_CMP_Msk (0xfffful << EPWM_CMPDAT3_CMP_Pos) /*!< EPWM_T::CMPDAT3: CMP Mask */ + +#define EPWM_CMPDAT4_CMP_Pos (0) /*!< EPWM_T::CMPDAT4: CMP Position */ +#define EPWM_CMPDAT4_CMP_Msk (0xfffful << EPWM_CMPDAT4_CMP_Pos) /*!< EPWM_T::CMPDAT4: CMP Mask */ + +#define EPWM_CMPDAT5_CMP_Pos (0) /*!< EPWM_T::CMPDAT5: CMP Position */ +#define EPWM_CMPDAT5_CMP_Msk (0xfffful << EPWM_CMPDAT5_CMP_Pos) /*!< EPWM_T::CMPDAT5: CMP Mask */ + +#define EPWM_DTCTL0_1_DTCNT_Pos (0) /*!< EPWM_T::DTCTL0_1: DTCNT Position */ +#define EPWM_DTCTL0_1_DTCNT_Msk (0xffful << EPWM_DTCTL0_1_DTCNT_Pos) /*!< EPWM_T::DTCTL0_1: DTCNT Mask */ + +#define EPWM_DTCTL0_1_DTEN_Pos (16) /*!< EPWM_T::DTCTL0_1: DTEN Position */ +#define EPWM_DTCTL0_1_DTEN_Msk (0x1ul << EPWM_DTCTL0_1_DTEN_Pos) /*!< EPWM_T::DTCTL0_1: DTEN Mask */ + +#define EPWM_DTCTL0_1_DTCKSEL_Pos (24) /*!< EPWM_T::DTCTL0_1: DTCKSEL Position */ +#define EPWM_DTCTL0_1_DTCKSEL_Msk (0x1ul << EPWM_DTCTL0_1_DTCKSEL_Pos) /*!< EPWM_T::DTCTL0_1: DTCKSEL Mask */ + +#define EPWM_DTCTL2_3_DTCNT_Pos (0) /*!< EPWM_T::DTCTL2_3: DTCNT Position */ +#define EPWM_DTCTL2_3_DTCNT_Msk (0xffful << EPWM_DTCTL2_3_DTCNT_Pos) /*!< EPWM_T::DTCTL2_3: DTCNT Mask */ + +#define EPWM_DTCTL2_3_DTEN_Pos (16) /*!< EPWM_T::DTCTL2_3: DTEN Position */ +#define EPWM_DTCTL2_3_DTEN_Msk (0x1ul << EPWM_DTCTL2_3_DTEN_Pos) /*!< EPWM_T::DTCTL2_3: DTEN Mask */ + +#define EPWM_DTCTL2_3_DTCKSEL_Pos (24) /*!< EPWM_T::DTCTL2_3: DTCKSEL Position */ +#define EPWM_DTCTL2_3_DTCKSEL_Msk (0x1ul << EPWM_DTCTL2_3_DTCKSEL_Pos) /*!< EPWM_T::DTCTL2_3: DTCKSEL Mask */ + +#define EPWM_DTCTL4_5_DTCNT_Pos (0) /*!< EPWM_T::DTCTL4_5: DTCNT Position */ +#define EPWM_DTCTL4_5_DTCNT_Msk (0xffful << EPWM_DTCTL4_5_DTCNT_Pos) /*!< EPWM_T::DTCTL4_5: DTCNT Mask */ + +#define EPWM_DTCTL4_5_DTEN_Pos (16) /*!< EPWM_T::DTCTL4_5: DTEN Position */ +#define EPWM_DTCTL4_5_DTEN_Msk (0x1ul << EPWM_DTCTL4_5_DTEN_Pos) /*!< EPWM_T::DTCTL4_5: DTEN Mask */ + +#define EPWM_DTCTL4_5_DTCKSEL_Pos (24) /*!< EPWM_T::DTCTL4_5: DTCKSEL Position */ +#define EPWM_DTCTL4_5_DTCKSEL_Msk (0x1ul << EPWM_DTCTL4_5_DTCKSEL_Pos) /*!< EPWM_T::DTCTL4_5: DTCKSEL Mask */ + +#define EPWM_PHS0_1_PHS_Pos (0) /*!< EPWM_T::PHS0_1: PHS Position */ +#define EPWM_PHS0_1_PHS_Msk (0xfffful << EPWM_PHS0_1_PHS_Pos) /*!< EPWM_T::PHS0_1: PHS Mask */ + +#define EPWM_PHS2_3_PHS_Pos (0) /*!< EPWM_T::PHS2_3: PHS Position */ +#define EPWM_PHS2_3_PHS_Msk (0xfffful << EPWM_PHS2_3_PHS_Pos) /*!< EPWM_T::PHS2_3: PHS Mask */ + +#define EPWM_PHS4_5_PHS_Pos (0) /*!< EPWM_T::PHS4_5: PHS Position */ +#define EPWM_PHS4_5_PHS_Msk (0xfffful << EPWM_PHS4_5_PHS_Pos) /*!< EPWM_T::PHS4_5: PHS Mask */ + +#define EPWM_CNT0_CNT_Pos (0) /*!< EPWM_T::CNT0: CNT Position */ +#define EPWM_CNT0_CNT_Msk (0xfffful << EPWM_CNT0_CNT_Pos) /*!< EPWM_T::CNT0: CNT Mask */ + +#define EPWM_CNT0_DIRF_Pos (16) /*!< EPWM_T::CNT0: DIRF Position */ +#define EPWM_CNT0_DIRF_Msk (0x1ul << EPWM_CNT0_DIRF_Pos) /*!< EPWM_T::CNT0: DIRF Mask */ + +#define EPWM_CNT1_CNT_Pos (0) /*!< EPWM_T::CNT1: CNT Position */ +#define EPWM_CNT1_CNT_Msk (0xfffful << EPWM_CNT1_CNT_Pos) /*!< EPWM_T::CNT1: CNT Mask */ + +#define EPWM_CNT1_DIRF_Pos (16) /*!< EPWM_T::CNT1: DIRF Position */ +#define EPWM_CNT1_DIRF_Msk (0x1ul << EPWM_CNT1_DIRF_Pos) /*!< EPWM_T::CNT1: DIRF Mask */ + +#define EPWM_CNT2_CNT_Pos (0) /*!< EPWM_T::CNT2: CNT Position */ +#define EPWM_CNT2_CNT_Msk (0xfffful << EPWM_CNT2_CNT_Pos) /*!< EPWM_T::CNT2: CNT Mask */ + +#define EPWM_CNT2_DIRF_Pos (16) /*!< EPWM_T::CNT2: DIRF Position */ +#define EPWM_CNT2_DIRF_Msk (0x1ul << EPWM_CNT2_DIRF_Pos) /*!< EPWM_T::CNT2: DIRF Mask */ + +#define EPWM_CNT3_CNT_Pos (0) /*!< EPWM_T::CNT3: CNT Position */ +#define EPWM_CNT3_CNT_Msk (0xfffful << EPWM_CNT3_CNT_Pos) /*!< EPWM_T::CNT3: CNT Mask */ + +#define EPWM_CNT3_DIRF_Pos (16) /*!< EPWM_T::CNT3: DIRF Position */ +#define EPWM_CNT3_DIRF_Msk (0x1ul << EPWM_CNT3_DIRF_Pos) /*!< EPWM_T::CNT3: DIRF Mask */ + +#define EPWM_CNT4_CNT_Pos (0) /*!< EPWM_T::CNT4: CNT Position */ +#define EPWM_CNT4_CNT_Msk (0xfffful << EPWM_CNT4_CNT_Pos) /*!< EPWM_T::CNT4: CNT Mask */ + +#define EPWM_CNT4_DIRF_Pos (16) /*!< EPWM_T::CNT4: DIRF Position */ +#define EPWM_CNT4_DIRF_Msk (0x1ul << EPWM_CNT4_DIRF_Pos) /*!< EPWM_T::CNT4: DIRF Mask */ + +#define EPWM_CNT5_CNT_Pos (0) /*!< EPWM_T::CNT5: CNT Position */ +#define EPWM_CNT5_CNT_Msk (0xfffful << EPWM_CNT5_CNT_Pos) /*!< EPWM_T::CNT5: CNT Mask */ + +#define EPWM_CNT5_DIRF_Pos (16) /*!< EPWM_T::CNT5: DIRF Position */ +#define EPWM_CNT5_DIRF_Msk (0x1ul << EPWM_CNT5_DIRF_Pos) /*!< EPWM_T::CNT5: DIRF Mask */ + +#define EPWM_WGCTL0_ZPCTL0_Pos (0) /*!< EPWM_T::WGCTL0: ZPCTL0 Position */ +#define EPWM_WGCTL0_ZPCTL0_Msk (0x3ul << EPWM_WGCTL0_ZPCTL0_Pos) /*!< EPWM_T::WGCTL0: ZPCTL0 Mask */ + +#define EPWM_WGCTL0_ZPCTL1_Pos (2) /*!< EPWM_T::WGCTL0: ZPCTL1 Position */ +#define EPWM_WGCTL0_ZPCTL1_Msk (0x3ul << EPWM_WGCTL0_ZPCTL1_Pos) /*!< EPWM_T::WGCTL0: ZPCTL1 Mask */ + +#define EPWM_WGCTL0_ZPCTL2_Pos (4) /*!< EPWM_T::WGCTL0: ZPCTL2 Position */ +#define EPWM_WGCTL0_ZPCTL2_Msk (0x3ul << EPWM_WGCTL0_ZPCTL2_Pos) /*!< EPWM_T::WGCTL0: ZPCTL2 Mask */ + +#define EPWM_WGCTL0_ZPCTL3_Pos (6) /*!< EPWM_T::WGCTL0: ZPCTL3 Position */ +#define EPWM_WGCTL0_ZPCTL3_Msk (0x3ul << EPWM_WGCTL0_ZPCTL3_Pos) /*!< EPWM_T::WGCTL0: ZPCTL3 Mask */ + +#define EPWM_WGCTL0_ZPCTL4_Pos (8) /*!< EPWM_T::WGCTL0: ZPCTL4 Position */ +#define EPWM_WGCTL0_ZPCTL4_Msk (0x3ul << EPWM_WGCTL0_ZPCTL4_Pos) /*!< EPWM_T::WGCTL0: ZPCTL4 Mask */ + +#define EPWM_WGCTL0_ZPCTL5_Pos (10) /*!< EPWM_T::WGCTL0: ZPCTL5 Position */ +#define EPWM_WGCTL0_ZPCTL5_Msk (0x3ul << EPWM_WGCTL0_ZPCTL5_Pos) /*!< EPWM_T::WGCTL0: ZPCTL5 Mask */ + +#define EPWM_WGCTL0_PRDPCTL0_Pos (16) /*!< EPWM_T::WGCTL0: PRDPCTL0 Position */ +#define EPWM_WGCTL0_PRDPCTL0_Msk (0x3ul << EPWM_WGCTL0_PRDPCTL0_Pos) /*!< EPWM_T::WGCTL0: PRDPCTL0 Mask */ + +#define EPWM_WGCTL0_PRDPCTL1_Pos (18) /*!< EPWM_T::WGCTL0: PRDPCTL1 Position */ +#define EPWM_WGCTL0_PRDPCTL1_Msk (0x3ul << EPWM_WGCTL0_PRDPCTL1_Pos) /*!< EPWM_T::WGCTL0: PRDPCTL1 Mask */ + +#define EPWM_WGCTL0_PRDPCTL2_Pos (20) /*!< EPWM_T::WGCTL0: PRDPCTL2 Position */ +#define EPWM_WGCTL0_PRDPCTL2_Msk (0x3ul << EPWM_WGCTL0_PRDPCTL2_Pos) /*!< EPWM_T::WGCTL0: PRDPCTL2 Mask */ + +#define EPWM_WGCTL0_PRDPCTL3_Pos (22) /*!< EPWM_T::WGCTL0: PRDPCTL3 Position */ +#define EPWM_WGCTL0_PRDPCTL3_Msk (0x3ul << EPWM_WGCTL0_PRDPCTL3_Pos) /*!< EPWM_T::WGCTL0: PRDPCTL3 Mask */ + +#define EPWM_WGCTL0_PRDPCTL4_Pos (24) /*!< EPWM_T::WGCTL0: PRDPCTL4 Position */ +#define EPWM_WGCTL0_PRDPCTL4_Msk (0x3ul << EPWM_WGCTL0_PRDPCTL4_Pos) /*!< EPWM_T::WGCTL0: PRDPCTL4 Mask */ + +#define EPWM_WGCTL0_PRDPCTL5_Pos (26) /*!< EPWM_T::WGCTL0: PRDPCTL5 Position */ +#define EPWM_WGCTL0_PRDPCTL5_Msk (0x3ul << EPWM_WGCTL0_PRDPCTL5_Pos) /*!< EPWM_T::WGCTL0: PRDPCTL5 Mask */ + +#define EPWM_WGCTL1_CMPUCTL0_Pos (0) /*!< EPWM_T::WGCTL1: CMPUCTL0 Position */ +#define EPWM_WGCTL1_CMPUCTL0_Msk (0x3ul << EPWM_WGCTL1_CMPUCTL0_Pos) /*!< EPWM_T::WGCTL1: CMPUCTL0 Mask */ + +#define EPWM_WGCTL1_CMPUCTL1_Pos (2) /*!< EPWM_T::WGCTL1: CMPUCTL1 Position */ +#define EPWM_WGCTL1_CMPUCTL1_Msk (0x3ul << EPWM_WGCTL1_CMPUCTL1_Pos) /*!< EPWM_T::WGCTL1: CMPUCTL1 Mask */ + +#define EPWM_WGCTL1_CMPUCTL2_Pos (4) /*!< EPWM_T::WGCTL1: CMPUCTL2 Position */ +#define EPWM_WGCTL1_CMPUCTL2_Msk (0x3ul << EPWM_WGCTL1_CMPUCTL2_Pos) /*!< EPWM_T::WGCTL1: CMPUCTL2 Mask */ + +#define EPWM_WGCTL1_CMPUCTL3_Pos (6) /*!< EPWM_T::WGCTL1: CMPUCTL3 Position */ +#define EPWM_WGCTL1_CMPUCTL3_Msk (0x3ul << EPWM_WGCTL1_CMPUCTL3_Pos) /*!< EPWM_T::WGCTL1: CMPUCTL3 Mask */ + +#define EPWM_WGCTL1_CMPUCTL4_Pos (8) /*!< EPWM_T::WGCTL1: CMPUCTL4 Position */ +#define EPWM_WGCTL1_CMPUCTL4_Msk (0x3ul << EPWM_WGCTL1_CMPUCTL4_Pos) /*!< EPWM_T::WGCTL1: CMPUCTL4 Mask */ + +#define EPWM_WGCTL1_CMPUCTL5_Pos (10) /*!< EPWM_T::WGCTL1: CMPUCTL5 Position */ +#define EPWM_WGCTL1_CMPUCTL5_Msk (0x3ul << EPWM_WGCTL1_CMPUCTL5_Pos) /*!< EPWM_T::WGCTL1: CMPUCTL5 Mask */ + +#define EPWM_WGCTL1_CMPDCTL0_Pos (16) /*!< EPWM_T::WGCTL1: CMPDCTL0 Position */ +#define EPWM_WGCTL1_CMPDCTL0_Msk (0x3ul << EPWM_WGCTL1_CMPDCTL0_Pos) /*!< EPWM_T::WGCTL1: CMPDCTL0 Mask */ + +#define EPWM_WGCTL1_CMPDCTL1_Pos (18) /*!< EPWM_T::WGCTL1: CMPDCTL1 Position */ +#define EPWM_WGCTL1_CMPDCTL1_Msk (0x3ul << EPWM_WGCTL1_CMPDCTL1_Pos) /*!< EPWM_T::WGCTL1: CMPDCTL1 Mask */ + +#define EPWM_WGCTL1_CMPDCTL2_Pos (20) /*!< EPWM_T::WGCTL1: CMPDCTL2 Position */ +#define EPWM_WGCTL1_CMPDCTL2_Msk (0x3ul << EPWM_WGCTL1_CMPDCTL2_Pos) /*!< EPWM_T::WGCTL1: CMPDCTL2 Mask */ + +#define EPWM_WGCTL1_CMPDCTL3_Pos (22) /*!< EPWM_T::WGCTL1: CMPDCTL3 Position */ +#define EPWM_WGCTL1_CMPDCTL3_Msk (0x3ul << EPWM_WGCTL1_CMPDCTL3_Pos) /*!< EPWM_T::WGCTL1: CMPDCTL3 Mask */ + +#define EPWM_WGCTL1_CMPDCTL4_Pos (24) /*!< EPWM_T::WGCTL1: CMPDCTL4 Position */ +#define EPWM_WGCTL1_CMPDCTL4_Msk (0x3ul << EPWM_WGCTL1_CMPDCTL4_Pos) /*!< EPWM_T::WGCTL1: CMPDCTL4 Mask */ + +#define EPWM_WGCTL1_CMPDCTL5_Pos (26) /*!< EPWM_T::WGCTL1: CMPDCTL5 Position */ +#define EPWM_WGCTL1_CMPDCTL5_Msk (0x3ul << EPWM_WGCTL1_CMPDCTL5_Pos) /*!< EPWM_T::WGCTL1: CMPDCTL5 Mask */ + +#define EPWM_MSKEN_MSKEN0_Pos (0) /*!< EPWM_T::MSKEN: MSKEN0 Position */ +#define EPWM_MSKEN_MSKEN0_Msk (0x1ul << EPWM_MSKEN_MSKEN0_Pos) /*!< EPWM_T::MSKEN: MSKEN0 Mask */ + +#define EPWM_MSKEN_MSKEN1_Pos (1) /*!< EPWM_T::MSKEN: MSKEN1 Position */ +#define EPWM_MSKEN_MSKEN1_Msk (0x1ul << EPWM_MSKEN_MSKEN1_Pos) /*!< EPWM_T::MSKEN: MSKEN1 Mask */ + +#define EPWM_MSKEN_MSKEN2_Pos (2) /*!< EPWM_T::MSKEN: MSKEN2 Position */ +#define EPWM_MSKEN_MSKEN2_Msk (0x1ul << EPWM_MSKEN_MSKEN2_Pos) /*!< EPWM_T::MSKEN: MSKEN2 Mask */ + +#define EPWM_MSKEN_MSKEN3_Pos (3) /*!< EPWM_T::MSKEN: MSKEN3 Position */ +#define EPWM_MSKEN_MSKEN3_Msk (0x1ul << EPWM_MSKEN_MSKEN3_Pos) /*!< EPWM_T::MSKEN: MSKEN3 Mask */ + +#define EPWM_MSKEN_MSKEN4_Pos (4) /*!< EPWM_T::MSKEN: MSKEN4 Position */ +#define EPWM_MSKEN_MSKEN4_Msk (0x1ul << EPWM_MSKEN_MSKEN4_Pos) /*!< EPWM_T::MSKEN: MSKEN4 Mask */ + +#define EPWM_MSKEN_MSKEN5_Pos (5) /*!< EPWM_T::MSKEN: MSKEN5 Position */ +#define EPWM_MSKEN_MSKEN5_Msk (0x1ul << EPWM_MSKEN_MSKEN5_Pos) /*!< EPWM_T::MSKEN: MSKEN5 Mask */ + +#define EPWM_MSK_MSKDAT0_Pos (0) /*!< EPWM_T::MSK: MSKDAT0 Position */ +#define EPWM_MSK_MSKDAT0_Msk (0x1ul << EPWM_MSK_MSKDAT0_Pos) /*!< EPWM_T::MSK: MSKDAT0 Mask */ + +#define EPWM_MSK_MSKDAT1_Pos (1) /*!< EPWM_T::MSK: MSKDAT1 Position */ +#define EPWM_MSK_MSKDAT1_Msk (0x1ul << EPWM_MSK_MSKDAT1_Pos) /*!< EPWM_T::MSK: MSKDAT1 Mask */ + +#define EPWM_MSK_MSKDAT2_Pos (2) /*!< EPWM_T::MSK: MSKDAT2 Position */ +#define EPWM_MSK_MSKDAT2_Msk (0x1ul << EPWM_MSK_MSKDAT2_Pos) /*!< EPWM_T::MSK: MSKDAT2 Mask */ + +#define EPWM_MSK_MSKDAT3_Pos (3) /*!< EPWM_T::MSK: MSKDAT3 Position */ +#define EPWM_MSK_MSKDAT3_Msk (0x1ul << EPWM_MSK_MSKDAT3_Pos) /*!< EPWM_T::MSK: MSKDAT3 Mask */ + +#define EPWM_MSK_MSKDAT4_Pos (4) /*!< EPWM_T::MSK: MSKDAT4 Position */ +#define EPWM_MSK_MSKDAT4_Msk (0x1ul << EPWM_MSK_MSKDAT4_Pos) /*!< EPWM_T::MSK: MSKDAT4 Mask */ + +#define EPWM_MSK_MSKDAT5_Pos (5) /*!< EPWM_T::MSK: MSKDAT5 Position */ +#define EPWM_MSK_MSKDAT5_Msk (0x1ul << EPWM_MSK_MSKDAT5_Pos) /*!< EPWM_T::MSK: MSKDAT5 Mask */ + +#define EPWM_BNF_BRK0NFEN_Pos (0) /*!< EPWM_T::BNF: BRK0NFEN Position */ +#define EPWM_BNF_BRK0NFEN_Msk (0x1ul << EPWM_BNF_BRK0NFEN_Pos) /*!< EPWM_T::BNF: BRK0NFEN Mask */ + +#define EPWM_BNF_BRK0NFSEL_Pos (1) /*!< EPWM_T::BNF: BRK0NFSEL Position */ +#define EPWM_BNF_BRK0NFSEL_Msk (0x7ul << EPWM_BNF_BRK0NFSEL_Pos) /*!< EPWM_T::BNF: BRK0NFSEL Mask */ + +#define EPWM_BNF_BRK0FCNT_Pos (4) /*!< EPWM_T::BNF: BRK0FCNT Position */ +#define EPWM_BNF_BRK0FCNT_Msk (0x7ul << EPWM_BNF_BRK0FCNT_Pos) /*!< EPWM_T::BNF: BRK0FCNT Mask */ + +#define EPWM_BNF_BRK0PINV_Pos (7) /*!< EPWM_T::BNF: BRK0PINV Position */ +#define EPWM_BNF_BRK0PINV_Msk (0x1ul << EPWM_BNF_BRK0PINV_Pos) /*!< EPWM_T::BNF: BRK0PINV Mask */ + +#define EPWM_BNF_BRK1NFEN_Pos (8) /*!< EPWM_T::BNF: BRK1NFEN Position */ +#define EPWM_BNF_BRK1NFEN_Msk (0x1ul << EPWM_BNF_BRK1NFEN_Pos) /*!< EPWM_T::BNF: BRK1NFEN Mask */ + +#define EPWM_BNF_BRK1NFSEL_Pos (9) /*!< EPWM_T::BNF: BRK1NFSEL Position */ +#define EPWM_BNF_BRK1NFSEL_Msk (0x7ul << EPWM_BNF_BRK1NFSEL_Pos) /*!< EPWM_T::BNF: BRK1NFSEL Mask */ + +#define EPWM_BNF_BRK1FCNT_Pos (12) /*!< EPWM_T::BNF: BRK1FCNT Position */ +#define EPWM_BNF_BRK1FCNT_Msk (0x7ul << EPWM_BNF_BRK1FCNT_Pos) /*!< EPWM_T::BNF: BRK1FCNT Mask */ + +#define EPWM_BNF_BRK1PINV_Pos (15) /*!< EPWM_T::BNF: BRK1PINV Position */ +#define EPWM_BNF_BRK1PINV_Msk (0x1ul << EPWM_BNF_BRK1PINV_Pos) /*!< EPWM_T::BNF: BRK1PINV Mask */ + +#define EPWM_BNF_BK0SRC_Pos (16) /*!< EPWM_T::BNF: BK0SRC Position */ +#define EPWM_BNF_BK0SRC_Msk (0x3ul << EPWM_BNF_BK0SRC_Pos) /*!< EPWM_T::BNF: BK0SRC Mask */ + +#define EPWM_BNF_BK1SRC_Pos (24) /*!< EPWM_T::BNF: BK1SRC Position */ +#define EPWM_BNF_BK1SRC_Msk (0x3ul << EPWM_BNF_BK1SRC_Pos) /*!< EPWM_T::BNF: BK1SRC Mask */ + +#define EPWM_FAILBRK_CSSBRKEN_Pos (0) /*!< EPWM_T::FAILBRK: CSSBRKEN Position */ +#define EPWM_FAILBRK_CSSBRKEN_Msk (0x1ul << EPWM_FAILBRK_CSSBRKEN_Pos) /*!< EPWM_T::FAILBRK: CSSBRKEN Mask */ + +#define EPWM_FAILBRK_LVDBRKEN_Pos (1) /*!< EPWM_T::FAILBRK: LVDBRKEN Position */ +#define EPWM_FAILBRK_LVDBRKEN_Msk (0x1ul << EPWM_FAILBRK_LVDBRKEN_Pos) /*!< EPWM_T::FAILBRK: LVDBRKEN Mask */ + +#define EPWM_FAILBRK_BODBRKEN_Pos (1) /*!< EPWM_T::FAILBRK: BODBRKEN Position */ +#define EPWM_FAILBRK_BODBRKEN_Msk (0x1ul << EPWM_FAILBRK_BODBRKEN_Pos) /*!< EPWM_T::FAILBRK: BODBRKEN Mask */ + +#define EPWM_FAILBRK_RAMBRKEN_Pos (2) /*!< EPWM_T::FAILBRK: RAMBRKEN Position */ +#define EPWM_FAILBRK_RAMBRKEN_Msk (0x1ul << EPWM_FAILBRK_RAMBRKEN_Pos) /*!< EPWM_T::FAILBRK: RAMBRKEN Mask */ + +#define EPWM_FAILBRK_CORBRKEN_Pos (3) /*!< EPWM_T::FAILBRK: CORBRKEN Position */ +#define EPWM_FAILBRK_CORBRKEN_Msk (0x1ul << EPWM_FAILBRK_CORBRKEN_Pos) /*!< EPWM_T::FAILBRK: CORBRKEN Mask */ + +#define EPWM_BRKCTL0_1_BRKP0EEN_Pos (4) /*!< EPWM_T::BRKCTL0_1: BRKP0EEN Position */ +#define EPWM_BRKCTL0_1_BRKP0EEN_Msk (0x1ul << EPWM_BRKCTL0_1_BRKP0EEN_Pos) /*!< EPWM_T::BRKCTL0_1: BRKP0EEN Mask */ + +#define EPWM_BRKCTL0_1_BRKP1EEN_Pos (5) /*!< EPWM_T::BRKCTL0_1: BRKP1EEN Position */ +#define EPWM_BRKCTL0_1_BRKP1EEN_Msk (0x1ul << EPWM_BRKCTL0_1_BRKP1EEN_Pos) /*!< EPWM_T::BRKCTL0_1: BRKP1EEN Mask */ + +#define EPWM_BRKCTL0_1_SYSEBEN_Pos (7) /*!< EPWM_T::BRKCTL0_1: SYSEBEN Position */ +#define EPWM_BRKCTL0_1_SYSEBEN_Msk (0x1ul << EPWM_BRKCTL0_1_SYSEBEN_Pos) /*!< EPWM_T::BRKCTL0_1: SYSEBEN Mask */ + +#define EPWM_BRKCTL0_1_BRKP0LEN_Pos (12) /*!< EPWM_T::BRKCTL0_1: BRKP0LEN Position */ +#define EPWM_BRKCTL0_1_BRKP0LEN_Msk (0x1ul << EPWM_BRKCTL0_1_BRKP0LEN_Pos) /*!< EPWM_T::BRKCTL0_1: BRKP0LEN Mask */ + +#define EPWM_BRKCTL0_1_BRKP1LEN_Pos (13) /*!< EPWM_T::BRKCTL0_1: BRKP1LEN Position */ +#define EPWM_BRKCTL0_1_BRKP1LEN_Msk (0x1ul << EPWM_BRKCTL0_1_BRKP1LEN_Pos) /*!< EPWM_T::BRKCTL0_1: BRKP1LEN Mask */ + +#define EPWM_BRKCTL0_1_SYSLBEN_Pos (15) /*!< EPWM_T::BRKCTL0_1: SYSLBEN Position */ +#define EPWM_BRKCTL0_1_SYSLBEN_Msk (0x1ul << EPWM_BRKCTL0_1_SYSLBEN_Pos) /*!< EPWM_T::BRKCTL0_1: SYSLBEN Mask */ + +#define EPWM_BRKCTL0_1_BRKAEVEN_Pos (16) /*!< EPWM_T::BRKCTL0_1: BRKAEVEN Position */ +#define EPWM_BRKCTL0_1_BRKAEVEN_Msk (0x3ul << EPWM_BRKCTL0_1_BRKAEVEN_Pos) /*!< EPWM_T::BRKCTL0_1: BRKAEVEN Mask */ + +#define EPWM_BRKCTL0_1_BRKAODD_Pos (18) /*!< EPWM_T::BRKCTL0_1: BRKAODD Position */ +#define EPWM_BRKCTL0_1_BRKAODD_Msk (0x3ul << EPWM_BRKCTL0_1_BRKAODD_Pos) /*!< EPWM_T::BRKCTL0_1: BRKAODD Mask */ + +#define EPWM_BRKCTL0_1_EADCEBEN_Pos (20) /*!< EPWM_T::BRKCTL0_1: EADCEBEN Position */ +#define EPWM_BRKCTL0_1_EADCEBEN_Msk (0x1ul << EPWM_BRKCTL0_1_EADCEBEN_Pos) /*!< EPWM_T::BRKCTL0_1: EADCEBEN Mask */ + +#define EPWM_BRKCTL0_1_EADCLBEN_Pos (28) /*!< EPWM_T::BRKCTL0_1: EADCLBEN Position */ +#define EPWM_BRKCTL0_1_EADCLBEN_Msk (0x1ul << EPWM_BRKCTL0_1_EADCLBEN_Pos) /*!< EPWM_T::BRKCTL0_1: EADCLBEN Mask */ + +#define EPWM_BRKCTL2_3_BRKP0EEN_Pos (4) /*!< EPWM_T::BRKCTL2_3: BRKP0EEN Position */ +#define EPWM_BRKCTL2_3_BRKP0EEN_Msk (0x1ul << EPWM_BRKCTL2_3_BRKP0EEN_Pos) /*!< EPWM_T::BRKCTL2_3: BRKP0EEN Mask */ + +#define EPWM_BRKCTL2_3_BRKP1EEN_Pos (5) /*!< EPWM_T::BRKCTL2_3: BRKP1EEN Position */ +#define EPWM_BRKCTL2_3_BRKP1EEN_Msk (0x1ul << EPWM_BRKCTL2_3_BRKP1EEN_Pos) /*!< EPWM_T::BRKCTL2_3: BRKP1EEN Mask */ + +#define EPWM_BRKCTL2_3_SYSEBEN_Pos (7) /*!< EPWM_T::BRKCTL2_3: SYSEBEN Position */ +#define EPWM_BRKCTL2_3_SYSEBEN_Msk (0x1ul << EPWM_BRKCTL2_3_SYSEBEN_Pos) /*!< EPWM_T::BRKCTL2_3: SYSEBEN Mask */ + +#define EPWM_BRKCTL2_3_BRKP0LEN_Pos (12) /*!< EPWM_T::BRKCTL2_3: BRKP0LEN Position */ +#define EPWM_BRKCTL2_3_BRKP0LEN_Msk (0x1ul << EPWM_BRKCTL2_3_BRKP0LEN_Pos) /*!< EPWM_T::BRKCTL2_3: BRKP0LEN Mask */ + +#define EPWM_BRKCTL2_3_BRKP1LEN_Pos (13) /*!< EPWM_T::BRKCTL2_3: BRKP1LEN Position */ +#define EPWM_BRKCTL2_3_BRKP1LEN_Msk (0x1ul << EPWM_BRKCTL2_3_BRKP1LEN_Pos) /*!< EPWM_T::BRKCTL2_3: BRKP1LEN Mask */ + +#define EPWM_BRKCTL2_3_SYSLBEN_Pos (15) /*!< EPWM_T::BRKCTL2_3: SYSLBEN Position */ +#define EPWM_BRKCTL2_3_SYSLBEN_Msk (0x1ul << EPWM_BRKCTL2_3_SYSLBEN_Pos) /*!< EPWM_T::BRKCTL2_3: SYSLBEN Mask */ + +#define EPWM_BRKCTL2_3_BRKAEVEN_Pos (16) /*!< EPWM_T::BRKCTL2_3: BRKAEVEN Position */ +#define EPWM_BRKCTL2_3_BRKAEVEN_Msk (0x3ul << EPWM_BRKCTL2_3_BRKAEVEN_Pos) /*!< EPWM_T::BRKCTL2_3: BRKAEVEN Mask */ + +#define EPWM_BRKCTL2_3_BRKAODD_Pos (18) /*!< EPWM_T::BRKCTL2_3: BRKAODD Position */ +#define EPWM_BRKCTL2_3_BRKAODD_Msk (0x3ul << EPWM_BRKCTL2_3_BRKAODD_Pos) /*!< EPWM_T::BRKCTL2_3: BRKAODD Mask */ + +#define EPWM_BRKCTL2_3_EADCEBEN_Pos (20) /*!< EPWM_T::BRKCTL2_3: EADCEBEN Position */ +#define EPWM_BRKCTL2_3_EADCEBEN_Msk (0x1ul << EPWM_BRKCTL2_3_EADCEBEN_Pos) /*!< EPWM_T::BRKCTL2_3: EADCEBEN Mask */ + +#define EPWM_BRKCTL2_3_EADCLBEN_Pos (28) /*!< EPWM_T::BRKCTL2_3: EADCLBEN Position */ +#define EPWM_BRKCTL2_3_EADCLBEN_Msk (0x1ul << EPWM_BRKCTL2_3_EADCLBEN_Pos) /*!< EPWM_T::BRKCTL2_3: EADCLBEN Mask */ + +#define EPWM_BRKCTL4_5_BRKP0EEN_Pos (4) /*!< EPWM_T::BRKCTL4_5: BRKP0EEN Position */ +#define EPWM_BRKCTL4_5_BRKP0EEN_Msk (0x1ul << EPWM_BRKCTL4_5_BRKP0EEN_Pos) /*!< EPWM_T::BRKCTL4_5: BRKP0EEN Mask */ + +#define EPWM_BRKCTL4_5_BRKP1EEN_Pos (5) /*!< EPWM_T::BRKCTL4_5: BRKP1EEN Position */ +#define EPWM_BRKCTL4_5_BRKP1EEN_Msk (0x1ul << EPWM_BRKCTL4_5_BRKP1EEN_Pos) /*!< EPWM_T::BRKCTL4_5: BRKP1EEN Mask */ + +#define EPWM_BRKCTL4_5_SYSEBEN_Pos (7) /*!< EPWM_T::BRKCTL4_5: SYSEBEN Position */ +#define EPWM_BRKCTL4_5_SYSEBEN_Msk (0x1ul << EPWM_BRKCTL4_5_SYSEBEN_Pos) /*!< EPWM_T::BRKCTL4_5: SYSEBEN Mask */ + +#define EPWM_BRKCTL4_5_BRKP0LEN_Pos (12) /*!< EPWM_T::BRKCTL4_5: BRKP0LEN Position */ +#define EPWM_BRKCTL4_5_BRKP0LEN_Msk (0x1ul << EPWM_BRKCTL4_5_BRKP0LEN_Pos) /*!< EPWM_T::BRKCTL4_5: BRKP0LEN Mask */ + +#define EPWM_BRKCTL4_5_BRKP1LEN_Pos (13) /*!< EPWM_T::BRKCTL4_5: BRKP1LEN Position */ +#define EPWM_BRKCTL4_5_BRKP1LEN_Msk (0x1ul << EPWM_BRKCTL4_5_BRKP1LEN_Pos) /*!< EPWM_T::BRKCTL4_5: BRKP1LEN Mask */ + +#define EPWM_BRKCTL4_5_SYSLBEN_Pos (15) /*!< EPWM_T::BRKCTL4_5: SYSLBEN Position */ +#define EPWM_BRKCTL4_5_SYSLBEN_Msk (0x1ul << EPWM_BRKCTL4_5_SYSLBEN_Pos) /*!< EPWM_T::BRKCTL4_5: SYSLBEN Mask */ + +#define EPWM_BRKCTL4_5_BRKAEVEN_Pos (16) /*!< EPWM_T::BRKCTL4_5: BRKAEVEN Position */ +#define EPWM_BRKCTL4_5_BRKAEVEN_Msk (0x3ul << EPWM_BRKCTL4_5_BRKAEVEN_Pos) /*!< EPWM_T::BRKCTL4_5: BRKAEVEN Mask */ + +#define EPWM_BRKCTL4_5_BRKAODD_Pos (18) /*!< EPWM_T::BRKCTL4_5: BRKAODD Position */ +#define EPWM_BRKCTL4_5_BRKAODD_Msk (0x3ul << EPWM_BRKCTL4_5_BRKAODD_Pos) /*!< EPWM_T::BRKCTL4_5: BRKAODD Mask */ + +#define EPWM_BRKCTL4_5_EADCEBEN_Pos (20) /*!< EPWM_T::BRKCTL4_5: EADCEBEN Position */ +#define EPWM_BRKCTL4_5_EADCEBEN_Msk (0x1ul << EPWM_BRKCTL4_5_EADCEBEN_Pos) /*!< EPWM_T::BRKCTL4_5: EADCEBEN Mask */ + +#define EPWM_BRKCTL4_5_EADCLBEN_Pos (28) /*!< EPWM_T::BRKCTL4_5: EADCLBEN Position */ +#define EPWM_BRKCTL4_5_EADCLBEN_Msk (0x1ul << EPWM_BRKCTL4_5_EADCLBEN_Pos) /*!< EPWM_T::BRKCTL4_5: EADCLBEN Mask */ + +#define EPWM_POLCTL_PINV0_Pos (0) /*!< EPWM_T::POLCTL: PINV0 Position */ +#define EPWM_POLCTL_PINV0_Msk (0x1ul << EPWM_POLCTL_PINV0_Pos) /*!< EPWM_T::POLCTL: PINV0 Mask */ + +#define EPWM_POLCTL_PINV1_Pos (1) /*!< EPWM_T::POLCTL: PINV1 Position */ +#define EPWM_POLCTL_PINV1_Msk (0x1ul << EPWM_POLCTL_PINV1_Pos) /*!< EPWM_T::POLCTL: PINV1 Mask */ + +#define EPWM_POLCTL_PINV2_Pos (2) /*!< EPWM_T::POLCTL: PINV2 Position */ +#define EPWM_POLCTL_PINV2_Msk (0x1ul << EPWM_POLCTL_PINV2_Pos) /*!< EPWM_T::POLCTL: PINV2 Mask */ + +#define EPWM_POLCTL_PINV3_Pos (3) /*!< EPWM_T::POLCTL: PINV3 Position */ +#define EPWM_POLCTL_PINV3_Msk (0x1ul << EPWM_POLCTL_PINV3_Pos) /*!< EPWM_T::POLCTL: PINV3 Mask */ + +#define EPWM_POLCTL_PINV4_Pos (4) /*!< EPWM_T::POLCTL: PINV4 Position */ +#define EPWM_POLCTL_PINV4_Msk (0x1ul << EPWM_POLCTL_PINV4_Pos) /*!< EPWM_T::POLCTL: PINV4 Mask */ + +#define EPWM_POLCTL_PINV5_Pos (5) /*!< EPWM_T::POLCTL: PINV5 Position */ +#define EPWM_POLCTL_PINV5_Msk (0x1ul << EPWM_POLCTL_PINV5_Pos) /*!< EPWM_T::POLCTL: PINV5 Mask */ + +#define EPWM_POEN_POEN0_Pos (0) /*!< EPWM_T::POEN: POEN0 Position */ +#define EPWM_POEN_POEN0_Msk (0x1ul << EPWM_POEN_POEN0_Pos) /*!< EPWM_T::POEN: POEN0 Mask */ + +#define EPWM_POEN_POEN1_Pos (1) /*!< EPWM_T::POEN: POEN1 Position */ +#define EPWM_POEN_POEN1_Msk (0x1ul << EPWM_POEN_POEN1_Pos) /*!< EPWM_T::POEN: POEN1 Mask */ + +#define EPWM_POEN_POEN2_Pos (2) /*!< EPWM_T::POEN: POEN2 Position */ +#define EPWM_POEN_POEN2_Msk (0x1ul << EPWM_POEN_POEN2_Pos) /*!< EPWM_T::POEN: POEN2 Mask */ + +#define EPWM_POEN_POEN3_Pos (3) /*!< EPWM_T::POEN: POEN3 Position */ +#define EPWM_POEN_POEN3_Msk (0x1ul << EPWM_POEN_POEN3_Pos) /*!< EPWM_T::POEN: POEN3 Mask */ + +#define EPWM_POEN_POEN4_Pos (4) /*!< EPWM_T::POEN: POEN4 Position */ +#define EPWM_POEN_POEN4_Msk (0x1ul << EPWM_POEN_POEN4_Pos) /*!< EPWM_T::POEN: POEN4 Mask */ + +#define EPWM_POEN_POEN5_Pos (5) /*!< EPWM_T::POEN: POEN5 Position */ +#define EPWM_POEN_POEN5_Msk (0x1ul << EPWM_POEN_POEN5_Pos) /*!< EPWM_T::POEN: POEN5 Mask */ + +#define EPWM_SWBRK_BRKETRG0_Pos (0) /*!< EPWM_T::SWBRK: BRKETRG0 Position */ +#define EPWM_SWBRK_BRKETRG0_Msk (0x1ul << EPWM_SWBRK_BRKETRG0_Pos) /*!< EPWM_T::SWBRK: BRKETRG0 Mask */ + +#define EPWM_SWBRK_BRKETRG2_Pos (1) /*!< EPWM_T::SWBRK: BRKETRG2 Position */ +#define EPWM_SWBRK_BRKETRG2_Msk (0x1ul << EPWM_SWBRK_BRKETRG2_Pos) /*!< EPWM_T::SWBRK: BRKETRG2 Mask */ + +#define EPWM_SWBRK_BRKETRG4_Pos (2) /*!< EPWM_T::SWBRK: BRKETRG4 Position */ +#define EPWM_SWBRK_BRKETRG4_Msk (0x1ul << EPWM_SWBRK_BRKETRG4_Pos) /*!< EPWM_T::SWBRK: BRKETRG4 Mask */ + +#define EPWM_SWBRK_BRKLTRG0_Pos (8) /*!< EPWM_T::SWBRK: BRKLTRG0 Position */ +#define EPWM_SWBRK_BRKLTRG0_Msk (0x1ul << EPWM_SWBRK_BRKLTRG0_Pos) /*!< EPWM_T::SWBRK: BRKLTRG0 Mask */ + +#define EPWM_SWBRK_BRKLTRG2_Pos (9) /*!< EPWM_T::SWBRK: BRKLTRG2 Position */ +#define EPWM_SWBRK_BRKLTRG2_Msk (0x1ul << EPWM_SWBRK_BRKLTRG2_Pos) /*!< EPWM_T::SWBRK: BRKLTRG2 Mask */ + +#define EPWM_SWBRK_BRKLTRG4_Pos (10) /*!< EPWM_T::SWBRK: BRKLTRG4 Position */ +#define EPWM_SWBRK_BRKLTRG4_Msk (0x1ul << EPWM_SWBRK_BRKLTRG4_Pos) /*!< EPWM_T::SWBRK: BRKLTRG4 Mask */ + +#define EPWM_INTEN0_ZIEN0_Pos (0) /*!< EPWM_T::INTEN0: ZIEN0 Position */ +#define EPWM_INTEN0_ZIEN0_Msk (0x1ul << EPWM_INTEN0_ZIEN0_Pos) /*!< EPWM_T::INTEN0: ZIEN0 Mask */ + +#define EPWM_INTEN0_ZIEN1_Pos (1) /*!< EPWM_T::INTEN0: ZIEN1 Position */ +#define EPWM_INTEN0_ZIEN1_Msk (0x1ul << EPWM_INTEN0_ZIEN1_Pos) /*!< EPWM_T::INTEN0: ZIEN1 Mask */ + +#define EPWM_INTEN0_ZIEN2_Pos (2) /*!< EPWM_T::INTEN0: ZIEN2 Position */ +#define EPWM_INTEN0_ZIEN2_Msk (0x1ul << EPWM_INTEN0_ZIEN2_Pos) /*!< EPWM_T::INTEN0: ZIEN2 Mask */ + +#define EPWM_INTEN0_ZIEN3_Pos (3) /*!< EPWM_T::INTEN0: ZIEN3 Position */ +#define EPWM_INTEN0_ZIEN3_Msk (0x1ul << EPWM_INTEN0_ZIEN3_Pos) /*!< EPWM_T::INTEN0: ZIEN3 Mask */ + +#define EPWM_INTEN0_ZIEN4_Pos (4) /*!< EPWM_T::INTEN0: ZIEN4 Position */ +#define EPWM_INTEN0_ZIEN4_Msk (0x1ul << EPWM_INTEN0_ZIEN4_Pos) /*!< EPWM_T::INTEN0: ZIEN4 Mask */ + +#define EPWM_INTEN0_ZIEN5_Pos (5) /*!< EPWM_T::INTEN0: ZIEN5 Position */ +#define EPWM_INTEN0_ZIEN5_Msk (0x1ul << EPWM_INTEN0_ZIEN5_Pos) /*!< EPWM_T::INTEN0: ZIEN5 Mask */ + +#define EPWM_INTEN0_PIEN0_Pos (8) /*!< EPWM_T::INTEN0: PIEN0 Position */ +#define EPWM_INTEN0_PIEN0_Msk (0x1ul << EPWM_INTEN0_PIEN0_Pos) /*!< EPWM_T::INTEN0: PIEN0 Mask */ + +#define EPWM_INTEN0_PIEN1_Pos (9) /*!< EPWM_T::INTEN0: PIEN1 Position */ +#define EPWM_INTEN0_PIEN1_Msk (0x1ul << EPWM_INTEN0_PIEN1_Pos) /*!< EPWM_T::INTEN0: PIEN1 Mask */ + +#define EPWM_INTEN0_PIEN2_Pos (10) /*!< EPWM_T::INTEN0: PIEN2 Position */ +#define EPWM_INTEN0_PIEN2_Msk (0x1ul << EPWM_INTEN0_PIEN2_Pos) /*!< EPWM_T::INTEN0: PIEN2 Mask */ + +#define EPWM_INTEN0_PIEN3_Pos (11) /*!< EPWM_T::INTEN0: PIEN3 Position */ +#define EPWM_INTEN0_PIEN3_Msk (0x1ul << EPWM_INTEN0_PIEN3_Pos) /*!< EPWM_T::INTEN0: PIEN3 Mask */ + +#define EPWM_INTEN0_PIEN4_Pos (12) /*!< EPWM_T::INTEN0: PIEN4 Position */ +#define EPWM_INTEN0_PIEN4_Msk (0x1ul << EPWM_INTEN0_PIEN4_Pos) /*!< EPWM_T::INTEN0: PIEN4 Mask */ + +#define EPWM_INTEN0_PIEN5_Pos (13) /*!< EPWM_T::INTEN0: PIEN5 Position */ +#define EPWM_INTEN0_PIEN5_Msk (0x1ul << EPWM_INTEN0_PIEN5_Pos) /*!< EPWM_T::INTEN0: PIEN5 Mask */ + +#define EPWM_INTEN0_CMPUIEN0_Pos (16) /*!< EPWM_T::INTEN0: CMPUIEN0 Position */ +#define EPWM_INTEN0_CMPUIEN0_Msk (0x1ul << EPWM_INTEN0_CMPUIEN0_Pos) /*!< EPWM_T::INTEN0: CMPUIEN0 Mask */ + +#define EPWM_INTEN0_CMPUIEN1_Pos (17) /*!< EPWM_T::INTEN0: CMPUIEN1 Position */ +#define EPWM_INTEN0_CMPUIEN1_Msk (0x1ul << EPWM_INTEN0_CMPUIEN1_Pos) /*!< EPWM_T::INTEN0: CMPUIEN1 Mask */ + +#define EPWM_INTEN0_CMPUIEN2_Pos (18) /*!< EPWM_T::INTEN0: CMPUIEN2 Position */ +#define EPWM_INTEN0_CMPUIEN2_Msk (0x1ul << EPWM_INTEN0_CMPUIEN2_Pos) /*!< EPWM_T::INTEN0: CMPUIEN2 Mask */ + +#define EPWM_INTEN0_CMPUIEN3_Pos (19) /*!< EPWM_T::INTEN0: CMPUIEN3 Position */ +#define EPWM_INTEN0_CMPUIEN3_Msk (0x1ul << EPWM_INTEN0_CMPUIEN3_Pos) /*!< EPWM_T::INTEN0: CMPUIEN3 Mask */ + +#define EPWM_INTEN0_CMPUIEN4_Pos (20) /*!< EPWM_T::INTEN0: CMPUIEN4 Position */ +#define EPWM_INTEN0_CMPUIEN4_Msk (0x1ul << EPWM_INTEN0_CMPUIEN4_Pos) /*!< EPWM_T::INTEN0: CMPUIEN4 Mask */ + +#define EPWM_INTEN0_CMPUIEN5_Pos (21) /*!< EPWM_T::INTEN0: CMPUIEN5 Position */ +#define EPWM_INTEN0_CMPUIEN5_Msk (0x1ul << EPWM_INTEN0_CMPUIEN5_Pos) /*!< EPWM_T::INTEN0: CMPUIEN5 Mask */ + +#define EPWM_INTEN0_CMPDIEN0_Pos (24) /*!< EPWM_T::INTEN0: CMPDIEN0 Position */ +#define EPWM_INTEN0_CMPDIEN0_Msk (0x1ul << EPWM_INTEN0_CMPDIEN0_Pos) /*!< EPWM_T::INTEN0: CMPDIEN0 Mask */ + +#define EPWM_INTEN0_CMPDIEN1_Pos (25) /*!< EPWM_T::INTEN0: CMPDIEN1 Position */ +#define EPWM_INTEN0_CMPDIEN1_Msk (0x1ul << EPWM_INTEN0_CMPDIEN1_Pos) /*!< EPWM_T::INTEN0: CMPDIEN1 Mask */ + +#define EPWM_INTEN0_CMPDIEN2_Pos (26) /*!< EPWM_T::INTEN0: CMPDIEN2 Position */ +#define EPWM_INTEN0_CMPDIEN2_Msk (0x1ul << EPWM_INTEN0_CMPDIEN2_Pos) /*!< EPWM_T::INTEN0: CMPDIEN2 Mask */ + +#define EPWM_INTEN0_CMPDIEN3_Pos (27) /*!< EPWM_T::INTEN0: CMPDIEN3 Position */ +#define EPWM_INTEN0_CMPDIEN3_Msk (0x1ul << EPWM_INTEN0_CMPDIEN3_Pos) /*!< EPWM_T::INTEN0: CMPDIEN3 Mask */ + +#define EPWM_INTEN0_CMPDIEN4_Pos (28) /*!< EPWM_T::INTEN0: CMPDIEN4 Position */ +#define EPWM_INTEN0_CMPDIEN4_Msk (0x1ul << EPWM_INTEN0_CMPDIEN4_Pos) /*!< EPWM_T::INTEN0: CMPDIEN4 Mask */ + +#define EPWM_INTEN0_CMPDIEN5_Pos (29) /*!< EPWM_T::INTEN0: CMPDIEN5 Position */ +#define EPWM_INTEN0_CMPDIEN5_Msk (0x1ul << EPWM_INTEN0_CMPDIEN5_Pos) /*!< EPWM_T::INTEN0: CMPDIEN5 Mask */ + +#define EPWM_INTEN1_BRKEIEN0_1_Pos (0) /*!< EPWM_T::INTEN1: BRKEIEN0_1 Position */ +#define EPWM_INTEN1_BRKEIEN0_1_Msk (0x1ul << EPWM_INTEN1_BRKEIEN0_1_Pos) /*!< EPWM_T::INTEN1: BRKEIEN0_1 Mask */ + +#define EPWM_INTEN1_BRKEIEN2_3_Pos (1) /*!< EPWM_T::INTEN1: BRKEIEN2_3 Position */ +#define EPWM_INTEN1_BRKEIEN2_3_Msk (0x1ul << EPWM_INTEN1_BRKEIEN2_3_Pos) /*!< EPWM_T::INTEN1: BRKEIEN2_3 Mask */ + +#define EPWM_INTEN1_BRKEIEN4_5_Pos (2) /*!< EPWM_T::INTEN1: BRKEIEN4_5 Position */ +#define EPWM_INTEN1_BRKEIEN4_5_Msk (0x1ul << EPWM_INTEN1_BRKEIEN4_5_Pos) /*!< EPWM_T::INTEN1: BRKEIEN4_5 Mask */ + +#define EPWM_INTEN1_BRKLIEN0_1_Pos (8) /*!< EPWM_T::INTEN1: BRKLIEN0_1 Position */ +#define EPWM_INTEN1_BRKLIEN0_1_Msk (0x1ul << EPWM_INTEN1_BRKLIEN0_1_Pos) /*!< EPWM_T::INTEN1: BRKLIEN0_1 Mask */ + +#define EPWM_INTEN1_BRKLIEN2_3_Pos (9) /*!< EPWM_T::INTEN1: BRKLIEN2_3 Position */ +#define EPWM_INTEN1_BRKLIEN2_3_Msk (0x1ul << EPWM_INTEN1_BRKLIEN2_3_Pos) /*!< EPWM_T::INTEN1: BRKLIEN2_3 Mask */ + +#define EPWM_INTEN1_BRKLIEN4_5_Pos (10) /*!< EPWM_T::INTEN1: BRKLIEN4_5 Position */ +#define EPWM_INTEN1_BRKLIEN4_5_Msk (0x1ul << EPWM_INTEN1_BRKLIEN4_5_Pos) /*!< EPWM_T::INTEN1: BRKLIEN4_5 Mask */ + +#define EPWM_INTSTS0_ZIF0_Pos (0) /*!< EPWM_T::INTSTS0: ZIF0 Position */ +#define EPWM_INTSTS0_ZIF0_Msk (0x1ul << EPWM_INTSTS0_ZIF0_Pos) /*!< EPWM_T::INTSTS0: ZIF0 Mask */ + +#define EPWM_INTSTS0_ZIF1_Pos (1) /*!< EPWM_T::INTSTS0: ZIF1 Position */ +#define EPWM_INTSTS0_ZIF1_Msk (0x1ul << EPWM_INTSTS0_ZIF1_Pos) /*!< EPWM_T::INTSTS0: ZIF1 Mask */ + +#define EPWM_INTSTS0_ZIF2_Pos (2) /*!< EPWM_T::INTSTS0: ZIF2 Position */ +#define EPWM_INTSTS0_ZIF2_Msk (0x1ul << EPWM_INTSTS0_ZIF2_Pos) /*!< EPWM_T::INTSTS0: ZIF2 Mask */ + +#define EPWM_INTSTS0_ZIF3_Pos (3) /*!< EPWM_T::INTSTS0: ZIF3 Position */ +#define EPWM_INTSTS0_ZIF3_Msk (0x1ul << EPWM_INTSTS0_ZIF3_Pos) /*!< EPWM_T::INTSTS0: ZIF3 Mask */ + +#define EPWM_INTSTS0_ZIF4_Pos (4) /*!< EPWM_T::INTSTS0: ZIF4 Position */ +#define EPWM_INTSTS0_ZIF4_Msk (0x1ul << EPWM_INTSTS0_ZIF4_Pos) /*!< EPWM_T::INTSTS0: ZIF4 Mask */ + +#define EPWM_INTSTS0_ZIF5_Pos (5) /*!< EPWM_T::INTSTS0: ZIF5 Position */ +#define EPWM_INTSTS0_ZIF5_Msk (0x1ul << EPWM_INTSTS0_ZIF5_Pos) /*!< EPWM_T::INTSTS0: ZIF5 Mask */ + +#define EPWM_INTSTS0_PIF0_Pos (8) /*!< EPWM_T::INTSTS0: PIF0 Position */ +#define EPWM_INTSTS0_PIF0_Msk (0x1ul << EPWM_INTSTS0_PIF0_Pos) /*!< EPWM_T::INTSTS0: PIF0 Mask */ + +#define EPWM_INTSTS0_PIF1_Pos (9) /*!< EPWM_T::INTSTS0: PIF1 Position */ +#define EPWM_INTSTS0_PIF1_Msk (0x1ul << EPWM_INTSTS0_PIF1_Pos) /*!< EPWM_T::INTSTS0: PIF1 Mask */ + +#define EPWM_INTSTS0_PIF2_Pos (10) /*!< EPWM_T::INTSTS0: PIF2 Position */ +#define EPWM_INTSTS0_PIF2_Msk (0x1ul << EPWM_INTSTS0_PIF2_Pos) /*!< EPWM_T::INTSTS0: PIF2 Mask */ + +#define EPWM_INTSTS0_PIF3_Pos (11) /*!< EPWM_T::INTSTS0: PIF3 Position */ +#define EPWM_INTSTS0_PIF3_Msk (0x1ul << EPWM_INTSTS0_PIF3_Pos) /*!< EPWM_T::INTSTS0: PIF3 Mask */ + +#define EPWM_INTSTS0_PIF4_Pos (12) /*!< EPWM_T::INTSTS0: PIF4 Position */ +#define EPWM_INTSTS0_PIF4_Msk (0x1ul << EPWM_INTSTS0_PIF4_Pos) /*!< EPWM_T::INTSTS0: PIF4 Mask */ + +#define EPWM_INTSTS0_PIF5_Pos (13) /*!< EPWM_T::INTSTS0: PIF5 Position */ +#define EPWM_INTSTS0_PIF5_Msk (0x1ul << EPWM_INTSTS0_PIF5_Pos) /*!< EPWM_T::INTSTS0: PIF5 Mask */ + +#define EPWM_INTSTS0_CMPUIF0_Pos (16) /*!< EPWM_T::INTSTS0: CMPUIF0 Position */ +#define EPWM_INTSTS0_CMPUIF0_Msk (0x1ul << EPWM_INTSTS0_CMPUIF0_Pos) /*!< EPWM_T::INTSTS0: CMPUIF0 Mask */ + +#define EPWM_INTSTS0_CMPUIF1_Pos (17) /*!< EPWM_T::INTSTS0: CMPUIF1 Position */ +#define EPWM_INTSTS0_CMPUIF1_Msk (0x1ul << EPWM_INTSTS0_CMPUIF1_Pos) /*!< EPWM_T::INTSTS0: CMPUIF1 Mask */ + +#define EPWM_INTSTS0_CMPUIF2_Pos (18) /*!< EPWM_T::INTSTS0: CMPUIF2 Position */ +#define EPWM_INTSTS0_CMPUIF2_Msk (0x1ul << EPWM_INTSTS0_CMPUIF2_Pos) /*!< EPWM_T::INTSTS0: CMPUIF2 Mask */ + +#define EPWM_INTSTS0_CMPUIF3_Pos (19) /*!< EPWM_T::INTSTS0: CMPUIF3 Position */ +#define EPWM_INTSTS0_CMPUIF3_Msk (0x1ul << EPWM_INTSTS0_CMPUIF3_Pos) /*!< EPWM_T::INTSTS0: CMPUIF3 Mask */ + +#define EPWM_INTSTS0_CMPUIF4_Pos (20) /*!< EPWM_T::INTSTS0: CMPUIF4 Position */ +#define EPWM_INTSTS0_CMPUIF4_Msk (0x1ul << EPWM_INTSTS0_CMPUIF4_Pos) /*!< EPWM_T::INTSTS0: CMPUIF4 Mask */ + +#define EPWM_INTSTS0_CMPUIF5_Pos (21) /*!< EPWM_T::INTSTS0: CMPUIF5 Position */ +#define EPWM_INTSTS0_CMPUIF5_Msk (0x1ul << EPWM_INTSTS0_CMPUIF5_Pos) /*!< EPWM_T::INTSTS0: CMPUIF5 Mask */ + +#define EPWM_INTSTS0_CMPDIF0_Pos (24) /*!< EPWM_T::INTSTS0: CMPDIF0 Position */ +#define EPWM_INTSTS0_CMPDIF0_Msk (0x1ul << EPWM_INTSTS0_CMPDIF0_Pos) /*!< EPWM_T::INTSTS0: CMPDIF0 Mask */ + +#define EPWM_INTSTS0_CMPDIF1_Pos (25) /*!< EPWM_T::INTSTS0: CMPDIF1 Position */ +#define EPWM_INTSTS0_CMPDIF1_Msk (0x1ul << EPWM_INTSTS0_CMPDIF1_Pos) /*!< EPWM_T::INTSTS0: CMPDIF1 Mask */ + +#define EPWM_INTSTS0_CMPDIF2_Pos (26) /*!< EPWM_T::INTSTS0: CMPDIF2 Position */ +#define EPWM_INTSTS0_CMPDIF2_Msk (0x1ul << EPWM_INTSTS0_CMPDIF2_Pos) /*!< EPWM_T::INTSTS0: CMPDIF2 Mask */ + +#define EPWM_INTSTS0_CMPDIF3_Pos (27) /*!< EPWM_T::INTSTS0: CMPDIF3 Position */ +#define EPWM_INTSTS0_CMPDIF3_Msk (0x1ul << EPWM_INTSTS0_CMPDIF3_Pos) /*!< EPWM_T::INTSTS0: CMPDIF3 Mask */ + +#define EPWM_INTSTS0_CMPDIF4_Pos (28) /*!< EPWM_T::INTSTS0: CMPDIF4 Position */ +#define EPWM_INTSTS0_CMPDIF4_Msk (0x1ul << EPWM_INTSTS0_CMPDIF4_Pos) /*!< EPWM_T::INTSTS0: CMPDIF4 Mask */ + +#define EPWM_INTSTS0_CMPDIF5_Pos (29) /*!< EPWM_T::INTSTS0: CMPDIF5 Position */ +#define EPWM_INTSTS0_CMPDIF5_Msk (0x1ul << EPWM_INTSTS0_CMPDIF5_Pos) /*!< EPWM_T::INTSTS0: CMPDIF5 Mask */ + +#define EPWM_INTSTS1_BRKEIF0_Pos (0) /*!< EPWM_T::INTSTS1: BRKEIF0 Position */ +#define EPWM_INTSTS1_BRKEIF0_Msk (0x1ul << EPWM_INTSTS1_BRKEIF0_Pos) /*!< EPWM_T::INTSTS1: BRKEIF0 Mask */ + +#define EPWM_INTSTS1_BRKEIF1_Pos (1) /*!< EPWM_T::INTSTS1: BRKEIF1 Position */ +#define EPWM_INTSTS1_BRKEIF1_Msk (0x1ul << EPWM_INTSTS1_BRKEIF1_Pos) /*!< EPWM_T::INTSTS1: BRKEIF1 Mask */ + +#define EPWM_INTSTS1_BRKEIF2_Pos (2) /*!< EPWM_T::INTSTS1: BRKEIF2 Position */ +#define EPWM_INTSTS1_BRKEIF2_Msk (0x1ul << EPWM_INTSTS1_BRKEIF2_Pos) /*!< EPWM_T::INTSTS1: BRKEIF2 Mask */ + +#define EPWM_INTSTS1_BRKEIF3_Pos (3) /*!< EPWM_T::INTSTS1: BRKEIF3 Position */ +#define EPWM_INTSTS1_BRKEIF3_Msk (0x1ul << EPWM_INTSTS1_BRKEIF3_Pos) /*!< EPWM_T::INTSTS1: BRKEIF3 Mask */ + +#define EPWM_INTSTS1_BRKEIF4_Pos (4) /*!< EPWM_T::INTSTS1: BRKEIF4 Position */ +#define EPWM_INTSTS1_BRKEIF4_Msk (0x1ul << EPWM_INTSTS1_BRKEIF4_Pos) /*!< EPWM_T::INTSTS1: BRKEIF4 Mask */ + +#define EPWM_INTSTS1_BRKEIF5_Pos (5) /*!< EPWM_T::INTSTS1: BRKEIF5 Position */ +#define EPWM_INTSTS1_BRKEIF5_Msk (0x1ul << EPWM_INTSTS1_BRKEIF5_Pos) /*!< EPWM_T::INTSTS1: BRKEIF5 Mask */ + +#define EPWM_INTSTS1_BRKLIF0_Pos (8) /*!< EPWM_T::INTSTS1: BRKLIF0 Position */ +#define EPWM_INTSTS1_BRKLIF0_Msk (0x1ul << EPWM_INTSTS1_BRKLIF0_Pos) /*!< EPWM_T::INTSTS1: BRKLIF0 Mask */ + +#define EPWM_INTSTS1_BRKLIF1_Pos (9) /*!< EPWM_T::INTSTS1: BRKLIF1 Position */ +#define EPWM_INTSTS1_BRKLIF1_Msk (0x1ul << EPWM_INTSTS1_BRKLIF1_Pos) /*!< EPWM_T::INTSTS1: BRKLIF1 Mask */ + +#define EPWM_INTSTS1_BRKLIF2_Pos (10) /*!< EPWM_T::INTSTS1: BRKLIF2 Position */ +#define EPWM_INTSTS1_BRKLIF2_Msk (0x1ul << EPWM_INTSTS1_BRKLIF2_Pos) /*!< EPWM_T::INTSTS1: BRKLIF2 Mask */ + +#define EPWM_INTSTS1_BRKLIF3_Pos (11) /*!< EPWM_T::INTSTS1: BRKLIF3 Position */ +#define EPWM_INTSTS1_BRKLIF3_Msk (0x1ul << EPWM_INTSTS1_BRKLIF3_Pos) /*!< EPWM_T::INTSTS1: BRKLIF3 Mask */ + +#define EPWM_INTSTS1_BRKLIF4_Pos (12) /*!< EPWM_T::INTSTS1: BRKLIF4 Position */ +#define EPWM_INTSTS1_BRKLIF4_Msk (0x1ul << EPWM_INTSTS1_BRKLIF4_Pos) /*!< EPWM_T::INTSTS1: BRKLIF4 Mask */ + +#define EPWM_INTSTS1_BRKLIF5_Pos (13) /*!< EPWM_T::INTSTS1: BRKLIF5 Position */ +#define EPWM_INTSTS1_BRKLIF5_Msk (0x1ul << EPWM_INTSTS1_BRKLIF5_Pos) /*!< EPWM_T::INTSTS1: BRKLIF5 Mask */ + +#define EPWM_INTSTS1_BRKESTS0_Pos (16) /*!< EPWM_T::INTSTS1: BRKESTS0 Position */ +#define EPWM_INTSTS1_BRKESTS0_Msk (0x1ul << EPWM_INTSTS1_BRKESTS0_Pos) /*!< EPWM_T::INTSTS1: BRKESTS0 Mask */ + +#define EPWM_INTSTS1_BRKESTS1_Pos (17) /*!< EPWM_T::INTSTS1: BRKESTS1 Position */ +#define EPWM_INTSTS1_BRKESTS1_Msk (0x1ul << EPWM_INTSTS1_BRKESTS1_Pos) /*!< EPWM_T::INTSTS1: BRKESTS1 Mask */ + +#define EPWM_INTSTS1_BRKESTS2_Pos (18) /*!< EPWM_T::INTSTS1: BRKESTS2 Position */ +#define EPWM_INTSTS1_BRKESTS2_Msk (0x1ul << EPWM_INTSTS1_BRKESTS2_Pos) /*!< EPWM_T::INTSTS1: BRKESTS2 Mask */ + +#define EPWM_INTSTS1_BRKESTS3_Pos (19) /*!< EPWM_T::INTSTS1: BRKESTS3 Position */ +#define EPWM_INTSTS1_BRKESTS3_Msk (0x1ul << EPWM_INTSTS1_BRKESTS3_Pos) /*!< EPWM_T::INTSTS1: BRKESTS3 Mask */ + +#define EPWM_INTSTS1_BRKESTS4_Pos (20) /*!< EPWM_T::INTSTS1: BRKESTS4 Position */ +#define EPWM_INTSTS1_BRKESTS4_Msk (0x1ul << EPWM_INTSTS1_BRKESTS4_Pos) /*!< EPWM_T::INTSTS1: BRKESTS4 Mask */ + +#define EPWM_INTSTS1_BRKESTS5_Pos (21) /*!< EPWM_T::INTSTS1: BRKESTS5 Position */ +#define EPWM_INTSTS1_BRKESTS5_Msk (0x1ul << EPWM_INTSTS1_BRKESTS5_Pos) /*!< EPWM_T::INTSTS1: BRKESTS5 Mask */ + +#define EPWM_INTSTS1_BRKLSTS0_Pos (24) /*!< EPWM_T::INTSTS1: BRKLSTS0 Position */ +#define EPWM_INTSTS1_BRKLSTS0_Msk (0x1ul << EPWM_INTSTS1_BRKLSTS0_Pos) /*!< EPWM_T::INTSTS1: BRKLSTS0 Mask */ + +#define EPWM_INTSTS1_BRKLSTS1_Pos (25) /*!< EPWM_T::INTSTS1: BRKLSTS1 Position */ +#define EPWM_INTSTS1_BRKLSTS1_Msk (0x1ul << EPWM_INTSTS1_BRKLSTS1_Pos) /*!< EPWM_T::INTSTS1: BRKLSTS1 Mask */ + +#define EPWM_INTSTS1_BRKLSTS2_Pos (26) /*!< EPWM_T::INTSTS1: BRKLSTS2 Position */ +#define EPWM_INTSTS1_BRKLSTS2_Msk (0x1ul << EPWM_INTSTS1_BRKLSTS2_Pos) /*!< EPWM_T::INTSTS1: BRKLSTS2 Mask */ + +#define EPWM_INTSTS1_BRKLSTS3_Pos (27) /*!< EPWM_T::INTSTS1: BRKLSTS3 Position */ +#define EPWM_INTSTS1_BRKLSTS3_Msk (0x1ul << EPWM_INTSTS1_BRKLSTS3_Pos) /*!< EPWM_T::INTSTS1: BRKLSTS3 Mask */ + +#define EPWM_INTSTS1_BRKLSTS4_Pos (28) /*!< EPWM_T::INTSTS1: BRKLSTS4 Position */ +#define EPWM_INTSTS1_BRKLSTS4_Msk (0x1ul << EPWM_INTSTS1_BRKLSTS4_Pos) /*!< EPWM_T::INTSTS1: BRKLSTS4 Mask */ + +#define EPWM_INTSTS1_BRKLSTS5_Pos (29) /*!< EPWM_T::INTSTS1: BRKLSTS5 Position */ +#define EPWM_INTSTS1_BRKLSTS5_Msk (0x1ul << EPWM_INTSTS1_BRKLSTS5_Pos) /*!< EPWM_T::INTSTS1: BRKLSTS5 Mask */ + +#define EPWM_EADCTS0_TRGSEL0_Pos (0) /*!< EPWM_T::EADCTS0: TRGSEL0 Position */ +#define EPWM_EADCTS0_TRGSEL0_Msk (0xful << EPWM_EADCTS0_TRGSEL0_Pos) /*!< EPWM_T::EADCTS0: TRGSEL0 Mask */ + +#define EPWM_EADCTS0_TRGEN0_Pos (7) /*!< EPWM_T::EADCTS0: TRGEN0 Position */ +#define EPWM_EADCTS0_TRGEN0_Msk (0x1ul << EPWM_EADCTS0_TRGEN0_Pos) /*!< EPWM_T::EADCTS0: TRGEN0 Mask */ + +#define EPWM_EADCTS0_TRGSEL1_Pos (8) /*!< EPWM_T::EADCTS0: TRGSEL1 Position */ +#define EPWM_EADCTS0_TRGSEL1_Msk (0xful << EPWM_EADCTS0_TRGSEL1_Pos) /*!< EPWM_T::EADCTS0: TRGSEL1 Mask */ + +#define EPWM_EADCTS0_TRGEN1_Pos (15) /*!< EPWM_T::EADCTS0: TRGEN1 Position */ +#define EPWM_EADCTS0_TRGEN1_Msk (0x1ul << EPWM_EADCTS0_TRGEN1_Pos) /*!< EPWM_T::EADCTS0: TRGEN1 Mask */ + +#define EPWM_EADCTS0_TRGSEL2_Pos (16) /*!< EPWM_T::EADCTS0: TRGSEL2 Position */ +#define EPWM_EADCTS0_TRGSEL2_Msk (0xful << EPWM_EADCTS0_TRGSEL2_Pos) /*!< EPWM_T::EADCTS0: TRGSEL2 Mask */ + +#define EPWM_EADCTS0_TRGEN2_Pos (23) /*!< EPWM_T::EADCTS0: TRGEN2 Position */ +#define EPWM_EADCTS0_TRGEN2_Msk (0x1ul << EPWM_EADCTS0_TRGEN2_Pos) /*!< EPWM_T::EADCTS0: TRGEN2 Mask */ + +#define EPWM_EADCTS0_TRGSEL3_Pos (24) /*!< EPWM_T::EADCTS0: TRGSEL3 Position */ +#define EPWM_EADCTS0_TRGSEL3_Msk (0xful << EPWM_EADCTS0_TRGSEL3_Pos) /*!< EPWM_T::EADCTS0: TRGSEL3 Mask */ + +#define EPWM_EADCTS0_TRGEN3_Pos (31) /*!< EPWM_T::EADCTS0: TRGEN3 Position */ +#define EPWM_EADCTS0_TRGEN3_Msk (0x1ul << EPWM_EADCTS0_TRGEN3_Pos) /*!< EPWM_T::EADCTS0: TRGEN3 Mask */ + +#define EPWM_EADCTS1_TRGSEL4_Pos (0) /*!< EPWM_T::EADCTS1: TRGSEL4 Position */ +#define EPWM_EADCTS1_TRGSEL4_Msk (0xful << EPWM_EADCTS1_TRGSEL4_Pos) /*!< EPWM_T::EADCTS1: TRGSEL4 Mask */ + +#define EPWM_EADCTS1_TRGEN4_Pos (7) /*!< EPWM_T::EADCTS1: TRGEN4 Position */ +#define EPWM_EADCTS1_TRGEN4_Msk (0x1ul << EPWM_EADCTS1_TRGEN4_Pos) /*!< EPWM_T::EADCTS1: TRGEN4 Mask */ + +#define EPWM_EADCTS1_TRGSEL5_Pos (8) /*!< EPWM_T::EADCTS1: TRGSEL5 Position */ +#define EPWM_EADCTS1_TRGSEL5_Msk (0xful << EPWM_EADCTS1_TRGSEL5_Pos) /*!< EPWM_T::EADCTS1: TRGSEL5 Mask */ + +#define EPWM_EADCTS1_TRGEN5_Pos (15) /*!< EPWM_T::EADCTS1: TRGEN5 Position */ +#define EPWM_EADCTS1_TRGEN5_Msk (0x1ul << EPWM_EADCTS1_TRGEN5_Pos) /*!< EPWM_T::EADCTS1: TRGEN5 Mask */ + +#define EPWM_FTCMPDAT0_1_FTCMP_Pos (0) /*!< EPWM_T::FTCMPDAT0_1: FTCMP Position */ +#define EPWM_FTCMPDAT0_1_FTCMP_Msk (0xfffful << EPWM_FTCMPDAT0_1_FTCMP_Pos) /*!< EPWM_T::FTCMPDAT0_1: FTCMP Mask */ + +#define EPWM_FTCMPDAT2_3_FTCMP_Pos (0) /*!< EPWM_T::FTCMPDAT2_3: FTCMP Position */ +#define EPWM_FTCMPDAT2_3_FTCMP_Msk (0xfffful << EPWM_FTCMPDAT2_3_FTCMP_Pos) /*!< EPWM_T::FTCMPDAT2_3: FTCMP Mask */ + +#define EPWM_FTCMPDAT4_5_FTCMP_Pos (0) /*!< EPWM_T::FTCMPDAT4_5: FTCMP Position */ +#define EPWM_FTCMPDAT4_5_FTCMP_Msk (0xfffful << EPWM_FTCMPDAT4_5_FTCMP_Pos) /*!< EPWM_T::FTCMPDAT4_5: FTCMP Mask */ + +#define EPWM_SSCTL_SSEN0_Pos (0) /*!< EPWM_T::SSCTL: SSEN0 Position */ +#define EPWM_SSCTL_SSEN0_Msk (0x1ul << EPWM_SSCTL_SSEN0_Pos) /*!< EPWM_T::SSCTL: SSEN0 Mask */ + +#define EPWM_SSCTL_SSEN1_Pos (1) /*!< EPWM_T::SSCTL: SSEN1 Position */ +#define EPWM_SSCTL_SSEN1_Msk (0x1ul << EPWM_SSCTL_SSEN1_Pos) /*!< EPWM_T::SSCTL: SSEN1 Mask */ + +#define EPWM_SSCTL_SSEN2_Pos (2) /*!< EPWM_T::SSCTL: SSEN2 Position */ +#define EPWM_SSCTL_SSEN2_Msk (0x1ul << EPWM_SSCTL_SSEN2_Pos) /*!< EPWM_T::SSCTL: SSEN2 Mask */ + +#define EPWM_SSCTL_SSEN3_Pos (3) /*!< EPWM_T::SSCTL: SSEN3 Position */ +#define EPWM_SSCTL_SSEN3_Msk (0x1ul << EPWM_SSCTL_SSEN3_Pos) /*!< EPWM_T::SSCTL: SSEN3 Mask */ + +#define EPWM_SSCTL_SSEN4_Pos (4) /*!< EPWM_T::SSCTL: SSEN4 Position */ +#define EPWM_SSCTL_SSEN4_Msk (0x1ul << EPWM_SSCTL_SSEN4_Pos) /*!< EPWM_T::SSCTL: SSEN4 Mask */ + +#define EPWM_SSCTL_SSEN5_Pos (5) /*!< EPWM_T::SSCTL: SSEN5 Position */ +#define EPWM_SSCTL_SSEN5_Msk (0x1ul << EPWM_SSCTL_SSEN5_Pos) /*!< EPWM_T::SSCTL: SSEN5 Mask */ + +#define EPWM_SSCTL_SSRC_Pos (8) /*!< EPWM_T::SSCTL: SSRC Position */ +#define EPWM_SSCTL_SSRC_Msk (0x3ul << EPWM_SSCTL_SSRC_Pos) /*!< EPWM_T::SSCTL: SSRC Mask */ + +#define EPWM_SSTRG_CNTSEN_Pos (0) /*!< EPWM_T::SSTRG: CNTSEN Position */ +#define EPWM_SSTRG_CNTSEN_Msk (0x1ul << EPWM_SSTRG_CNTSEN_Pos) /*!< EPWM_T::SSTRG: CNTSEN Mask */ + +#define EPWM_LEBCTL_LEBEN_Pos (0) /*!< EPWM_T::LEBCTL: LEBEN Position */ +#define EPWM_LEBCTL_LEBEN_Msk (0x1ul << EPWM_LEBCTL_LEBEN_Pos) /*!< EPWM_T::LEBCTL: LEBEN Mask */ + +#define EPWM_LEBCTL_SRCEN0_Pos (8) /*!< EPWM_T::LEBCTL: SRCEN0 Position */ +#define EPWM_LEBCTL_SRCEN0_Msk (0x1ul << EPWM_LEBCTL_SRCEN0_Pos) /*!< EPWM_T::LEBCTL: SRCEN0 Mask */ + +#define EPWM_LEBCTL_SRCEN2_Pos (9) /*!< EPWM_T::LEBCTL: SRCEN2 Position */ +#define EPWM_LEBCTL_SRCEN2_Msk (0x1ul << EPWM_LEBCTL_SRCEN2_Pos) /*!< EPWM_T::LEBCTL: SRCEN2 Mask */ + +#define EPWM_LEBCTL_SRCEN4_Pos (10) /*!< EPWM_T::LEBCTL: SRCEN4 Position */ +#define EPWM_LEBCTL_SRCEN4_Msk (0x1ul << EPWM_LEBCTL_SRCEN4_Pos) /*!< EPWM_T::LEBCTL: SRCEN4 Mask */ + +#define EPWM_LEBCTL_TRGTYPE_Pos (16) /*!< EPWM_T::LEBCTL: TRGTYPE Position */ +#define EPWM_LEBCTL_TRGTYPE_Msk (0x3ul << EPWM_LEBCTL_TRGTYPE_Pos) /*!< EPWM_T::LEBCTL: TRGTYPE Mask */ + +#define EPWM_LEBCNT_LEBCNT_Pos (0) /*!< EPWM_T::LEBCNT: LEBCNT Position */ +#define EPWM_LEBCNT_LEBCNT_Msk (0x1fful << EPWM_LEBCNT_LEBCNT_Pos) /*!< EPWM_T::LEBCNT: LEBCNT Mask */ + +#define EPWM_STATUS_CNTMAXF0_Pos (0) /*!< EPWM_T::STATUS: CNTMAXF0 Position */ +#define EPWM_STATUS_CNTMAXF0_Msk (0x1ul << EPWM_STATUS_CNTMAXF0_Pos) /*!< EPWM_T::STATUS: CNTMAXF0 Mask */ + +#define EPWM_STATUS_CNTMAXF1_Pos (1) /*!< EPWM_T::STATUS: CNTMAXF1 Position */ +#define EPWM_STATUS_CNTMAXF1_Msk (0x1ul << EPWM_STATUS_CNTMAXF1_Pos) /*!< EPWM_T::STATUS: CNTMAXF1 Mask */ + +#define EPWM_STATUS_CNTMAXF2_Pos (2) /*!< EPWM_T::STATUS: CNTMAXF2 Position */ +#define EPWM_STATUS_CNTMAXF2_Msk (0x1ul << EPWM_STATUS_CNTMAXF2_Pos) /*!< EPWM_T::STATUS: CNTMAXF2 Mask */ + +#define EPWM_STATUS_CNTMAXF3_Pos (3) /*!< EPWM_T::STATUS: CNTMAXF3 Position */ +#define EPWM_STATUS_CNTMAXF3_Msk (0x1ul << EPWM_STATUS_CNTMAXF3_Pos) /*!< EPWM_T::STATUS: CNTMAXF3 Mask */ + +#define EPWM_STATUS_CNTMAXF4_Pos (4) /*!< EPWM_T::STATUS: CNTMAXF4 Position */ +#define EPWM_STATUS_CNTMAXF4_Msk (0x1ul << EPWM_STATUS_CNTMAXF4_Pos) /*!< EPWM_T::STATUS: CNTMAXF4 Mask */ + +#define EPWM_STATUS_CNTMAXF5_Pos (5) /*!< EPWM_T::STATUS: CNTMAXF5 Position */ +#define EPWM_STATUS_CNTMAXF5_Msk (0x1ul << EPWM_STATUS_CNTMAXF5_Pos) /*!< EPWM_T::STATUS: CNTMAXF5 Mask */ + +#define EPWM_STATUS_SYNCINF0_Pos (8) /*!< EPWM_T::STATUS: SYNCINF0 Position */ +#define EPWM_STATUS_SYNCINF0_Msk (0x1ul << EPWM_STATUS_SYNCINF0_Pos) /*!< EPWM_T::STATUS: SYNCINF0 Mask */ + +#define EPWM_STATUS_SYNCINF2_Pos (9) /*!< EPWM_T::STATUS: SYNCINF2 Position */ +#define EPWM_STATUS_SYNCINF2_Msk (0x1ul << EPWM_STATUS_SYNCINF2_Pos) /*!< EPWM_T::STATUS: SYNCINF2 Mask */ + +#define EPWM_STATUS_SYNCINF4_Pos (10) /*!< EPWM_T::STATUS: SYNCINF4 Position */ +#define EPWM_STATUS_SYNCINF4_Msk (0x1ul << EPWM_STATUS_SYNCINF4_Pos) /*!< EPWM_T::STATUS: SYNCINF4 Mask */ + +#define EPWM_STATUS_EADCTRGF0_Pos (16) /*!< EPWM_T::STATUS: EADCTRGF0 Position */ +#define EPWM_STATUS_EADCTRGF0_Msk (0x1ul << EPWM_STATUS_EADCTRGF0_Pos) /*!< EPWM_T::STATUS: EADCTRGF0 Mask */ + +#define EPWM_STATUS_EADCTRGF1_Pos (17) /*!< EPWM_T::STATUS: EADCTRGF1 Position */ +#define EPWM_STATUS_EADCTRGF1_Msk (0x1ul << EPWM_STATUS_EADCTRGF1_Pos) /*!< EPWM_T::STATUS: EADCTRGF1 Mask */ + +#define EPWM_STATUS_EADCTRGF2_Pos (18) /*!< EPWM_T::STATUS: EADCTRGF2 Position */ +#define EPWM_STATUS_EADCTRGF2_Msk (0x1ul << EPWM_STATUS_EADCTRGF2_Pos) /*!< EPWM_T::STATUS: EADCTRGF2 Mask */ + +#define EPWM_STATUS_EADCTRGF3_Pos (19) /*!< EPWM_T::STATUS: EADCTRGF3 Position */ +#define EPWM_STATUS_EADCTRGF3_Msk (0x1ul << EPWM_STATUS_EADCTRGF3_Pos) /*!< EPWM_T::STATUS: EADCTRGF3 Mask */ + +#define EPWM_STATUS_EADCTRGF4_Pos (20) /*!< EPWM_T::STATUS: EADCTRGF4 Position */ +#define EPWM_STATUS_EADCTRGF4_Msk (0x1ul << EPWM_STATUS_EADCTRGF4_Pos) /*!< EPWM_T::STATUS: EADCTRGF4 Mask */ + +#define EPWM_STATUS_EADCTRGF5_Pos (21) /*!< EPWM_T::STATUS: EADCTRGF5 Position */ +#define EPWM_STATUS_EADCTRGF5_Msk (0x1ul << EPWM_STATUS_EADCTRGF5_Pos) /*!< EPWM_T::STATUS: EADCTRGF5 Mask */ + +#define EPWM_IFA0_IFACNT_Pos (0) /*!< EPWM_T::IFA0: IFACNT Position */ +#define EPWM_IFA0_IFACNT_Msk (0xfffful << EPWM_IFA0_IFACNT_Pos) /*!< EPWM_T::IFA0: IFACNT Mask */ + +#define EPWM_IFA0_STPMOD_Pos (24) /*!< EPWM_T::IFA0: STPMOD Position */ +#define EPWM_IFA0_STPMOD_Msk (0x1ul << EPWM_IFA0_STPMOD_Pos) /*!< EPWM_T::IFA0: STPMOD Mask */ + +#define EPWM_IFA0_IFASEL_Pos (28) /*!< EPWM_T::IFA0: IFASEL Position */ +#define EPWM_IFA0_IFASEL_Msk (0x3ul << EPWM_IFA0_IFASEL_Pos) /*!< EPWM_T::IFA0: IFASEL Mask */ + +#define EPWM_IFA0_IFAEN_Pos (31) /*!< EPWM_T::IFA0: IFAEN Position */ +#define EPWM_IFA0_IFAEN_Msk (0x1ul << EPWM_IFA0_IFAEN_Pos) /*!< EPWM_T::IFA0: IFAEN Mask */ + +#define EPWM_IFA1_IFACNT_Pos (0) /*!< EPWM_T::IFA1: IFACNT Position */ +#define EPWM_IFA1_IFACNT_Msk (0xfffful << EPWM_IFA1_IFACNT_Pos) /*!< EPWM_T::IFA1: IFACNT Mask */ + +#define EPWM_IFA1_STPMOD_Pos (24) /*!< EPWM_T::IFA1: STPMOD Position */ +#define EPWM_IFA1_STPMOD_Msk (0x1ul << EPWM_IFA1_STPMOD_Pos) /*!< EPWM_T::IFA1: STPMOD Mask */ + +#define EPWM_IFA1_IFASEL_Pos (28) /*!< EPWM_T::IFA1: IFASEL Position */ +#define EPWM_IFA1_IFASEL_Msk (0x3ul << EPWM_IFA1_IFASEL_Pos) /*!< EPWM_T::IFA1: IFASEL Mask */ + +#define EPWM_IFA1_IFAEN_Pos (31) /*!< EPWM_T::IFA1: IFAEN Position */ +#define EPWM_IFA1_IFAEN_Msk (0x1ul << EPWM_IFA1_IFAEN_Pos) /*!< EPWM_T::IFA1: IFAEN Mask */ + +#define EPWM_IFA2_IFACNT_Pos (0) /*!< EPWM_T::IFA2: IFACNT Position */ +#define EPWM_IFA2_IFACNT_Msk (0xfffful << EPWM_IFA2_IFACNT_Pos) /*!< EPWM_T::IFA2: IFACNT Mask */ + +#define EPWM_IFA2_STPMOD_Pos (24) /*!< EPWM_T::IFA2: STPMOD Position */ +#define EPWM_IFA2_STPMOD_Msk (0x1ul << EPWM_IFA2_STPMOD_Pos) /*!< EPWM_T::IFA2: STPMOD Mask */ + +#define EPWM_IFA2_IFASEL_Pos (28) /*!< EPWM_T::IFA2: IFASEL Position */ +#define EPWM_IFA2_IFASEL_Msk (0x3ul << EPWM_IFA2_IFASEL_Pos) /*!< EPWM_T::IFA2: IFASEL Mask */ + +#define EPWM_IFA2_IFAEN_Pos (31) /*!< EPWM_T::IFA2: IFAEN Position */ +#define EPWM_IFA2_IFAEN_Msk (0x1ul << EPWM_IFA2_IFAEN_Pos) /*!< EPWM_T::IFA2: IFAEN Mask */ + +#define EPWM_IFA3_IFACNT_Pos (0) /*!< EPWM_T::IFA3: IFACNT Position */ +#define EPWM_IFA3_IFACNT_Msk (0xfffful << EPWM_IFA3_IFACNT_Pos) /*!< EPWM_T::IFA3: IFACNT Mask */ + +#define EPWM_IFA3_STPMOD_Pos (24) /*!< EPWM_T::IFA3: STPMOD Position */ +#define EPWM_IFA3_STPMOD_Msk (0x1ul << EPWM_IFA3_STPMOD_Pos) /*!< EPWM_T::IFA3: STPMOD Mask */ + +#define EPWM_IFA3_IFASEL_Pos (28) /*!< EPWM_T::IFA3: IFASEL Position */ +#define EPWM_IFA3_IFASEL_Msk (0x3ul << EPWM_IFA3_IFASEL_Pos) /*!< EPWM_T::IFA3: IFASEL Mask */ + +#define EPWM_IFA3_IFAEN_Pos (31) /*!< EPWM_T::IFA3: IFAEN Position */ +#define EPWM_IFA3_IFAEN_Msk (0x1ul << EPWM_IFA3_IFAEN_Pos) /*!< EPWM_T::IFA3: IFAEN Mask */ + +#define EPWM_IFA4_IFACNT_Pos (0) /*!< EPWM_T::IFA4: IFACNT Position */ +#define EPWM_IFA4_IFACNT_Msk (0xfffful << EPWM_IFA4_IFACNT_Pos) /*!< EPWM_T::IFA4: IFACNT Mask */ + +#define EPWM_IFA4_STPMOD_Pos (24) /*!< EPWM_T::IFA4: STPMOD Position */ +#define EPWM_IFA4_STPMOD_Msk (0x1ul << EPWM_IFA4_STPMOD_Pos) /*!< EPWM_T::IFA4: STPMOD Mask */ + +#define EPWM_IFA4_IFASEL_Pos (28) /*!< EPWM_T::IFA4: IFASEL Position */ +#define EPWM_IFA4_IFASEL_Msk (0x3ul << EPWM_IFA4_IFASEL_Pos) /*!< EPWM_T::IFA4: IFASEL Mask */ + +#define EPWM_IFA4_IFAEN_Pos (31) /*!< EPWM_T::IFA4: IFAEN Position */ +#define EPWM_IFA4_IFAEN_Msk (0x1ul << EPWM_IFA4_IFAEN_Pos) /*!< EPWM_T::IFA4: IFAEN Mask */ + +#define EPWM_IFA5_IFACNT_Pos (0) /*!< EPWM_T::IFA5: IFACNT Position */ +#define EPWM_IFA5_IFACNT_Msk (0xfffful << EPWM_IFA5_IFACNT_Pos) /*!< EPWM_T::IFA5: IFACNT Mask */ + +#define EPWM_IFA5_STPMOD_Pos (24) /*!< EPWM_T::IFA5: STPMOD Position */ +#define EPWM_IFA5_STPMOD_Msk (0x1ul << EPWM_IFA5_STPMOD_Pos) /*!< EPWM_T::IFA5: STPMOD Mask */ + +#define EPWM_IFA5_IFASEL_Pos (28) /*!< EPWM_T::IFA5: IFASEL Position */ +#define EPWM_IFA5_IFASEL_Msk (0x3ul << EPWM_IFA5_IFASEL_Pos) /*!< EPWM_T::IFA5: IFASEL Mask */ + +#define EPWM_IFA5_IFAEN_Pos (31) /*!< EPWM_T::IFA5: IFAEN Position */ +#define EPWM_IFA5_IFAEN_Msk (0x1ul << EPWM_IFA5_IFAEN_Pos) /*!< EPWM_T::IFA5: IFAEN Mask */ + +#define EPWM_AINTSTS_IFAIF0_Pos (0) /*!< EPWM_T::AINTSTS: IFAIF0 Position */ +#define EPWM_AINTSTS_IFAIF0_Msk (0x1ul << EPWM_AINTSTS_IFAIF0_Pos) /*!< EPWM_T::AINTSTS: IFAIF0 Mask */ + +#define EPWM_AINTSTS_IFAIF1_Pos (1) /*!< EPWM_T::AINTSTS: IFAIF1 Position */ +#define EPWM_AINTSTS_IFAIF1_Msk (0x1ul << EPWM_AINTSTS_IFAIF1_Pos) /*!< EPWM_T::AINTSTS: IFAIF1 Mask */ + +#define EPWM_AINTSTS_IFAIF2_Pos (2) /*!< EPWM_T::AINTSTS: IFAIF2 Position */ +#define EPWM_AINTSTS_IFAIF2_Msk (0x1ul << EPWM_AINTSTS_IFAIF2_Pos) /*!< EPWM_T::AINTSTS: IFAIF2 Mask */ + +#define EPWM_AINTSTS_IFAIF3_Pos (3) /*!< EPWM_T::AINTSTS: IFAIF3 Position */ +#define EPWM_AINTSTS_IFAIF3_Msk (0x1ul << EPWM_AINTSTS_IFAIF3_Pos) /*!< EPWM_T::AINTSTS: IFAIF3 Mask */ + +#define EPWM_AINTSTS_IFAIF4_Pos (4) /*!< EPWM_T::AINTSTS: IFAIF4 Position */ +#define EPWM_AINTSTS_IFAIF4_Msk (0x1ul << EPWM_AINTSTS_IFAIF4_Pos) /*!< EPWM_T::AINTSTS: IFAIF4 Mask */ + +#define EPWM_AINTSTS_IFAIF5_Pos (5) /*!< EPWM_T::AINTSTS: IFAIF5 Position */ +#define EPWM_AINTSTS_IFAIF5_Msk (0x1ul << EPWM_AINTSTS_IFAIF5_Pos) /*!< EPWM_T::AINTSTS: IFAIF5 Mask */ + +#define EPWM_AINTEN_IFAIEN0_Pos (0) /*!< EPWM_T::AINTEN: IFAIEN0 Position */ +#define EPWM_AINTEN_IFAIEN0_Msk (0x1ul << EPWM_AINTEN_IFAIEN0_Pos) /*!< EPWM_T::AINTEN: IFAIEN0 Mask */ + +#define EPWM_AINTEN_IFAIEN1_Pos (1) /*!< EPWM_T::AINTEN: IFAIEN1 Position */ +#define EPWM_AINTEN_IFAIEN1_Msk (0x1ul << EPWM_AINTEN_IFAIEN1_Pos) /*!< EPWM_T::AINTEN: IFAIEN1 Mask */ + +#define EPWM_AINTEN_IFAIEN2_Pos (2) /*!< EPWM_T::AINTEN: IFAIEN2 Position */ +#define EPWM_AINTEN_IFAIEN2_Msk (0x1ul << EPWM_AINTEN_IFAIEN2_Pos) /*!< EPWM_T::AINTEN: IFAIEN2 Mask */ + +#define EPWM_AINTEN_IFAIEN3_Pos (3) /*!< EPWM_T::AINTEN: IFAIEN3 Position */ +#define EPWM_AINTEN_IFAIEN3_Msk (0x1ul << EPWM_AINTEN_IFAIEN3_Pos) /*!< EPWM_T::AINTEN: IFAIEN3 Mask */ + +#define EPWM_AINTEN_IFAIEN4_Pos (4) /*!< EPWM_T::AINTEN: IFAIEN4 Position */ +#define EPWM_AINTEN_IFAIEN4_Msk (0x1ul << EPWM_AINTEN_IFAIEN4_Pos) /*!< EPWM_T::AINTEN: IFAIEN4 Mask */ + +#define EPWM_AINTEN_IFAIEN5_Pos (5) /*!< EPWM_T::AINTEN: IFAIEN5 Position */ +#define EPWM_AINTEN_IFAIEN5_Msk (0x1ul << EPWM_AINTEN_IFAIEN5_Pos) /*!< EPWM_T::AINTEN: IFAIEN5 Mask */ + +#define EPWM_APDMACTL_APDMAEN0_Pos (0) /*!< EPWM_T::APDMACTL: APDMAEN0 Position */ +#define EPWM_APDMACTL_APDMAEN0_Msk (0x1ul << EPWM_APDMACTL_APDMAEN0_Pos) /*!< EPWM_T::APDMACTL: APDMAEN0 Mask */ + +#define EPWM_APDMACTL_APDMAEN1_Pos (1) /*!< EPWM_T::APDMACTL: APDMAEN1 Position */ +#define EPWM_APDMACTL_APDMAEN1_Msk (0x1ul << EPWM_APDMACTL_APDMAEN1_Pos) /*!< EPWM_T::APDMACTL: APDMAEN1 Mask */ + +#define EPWM_APDMACTL_APDMAEN2_Pos (2) /*!< EPWM_T::APDMACTL: APDMAEN2 Position */ +#define EPWM_APDMACTL_APDMAEN2_Msk (0x1ul << EPWM_APDMACTL_APDMAEN2_Pos) /*!< EPWM_T::APDMACTL: APDMAEN2 Mask */ + +#define EPWM_APDMACTL_APDMAEN3_Pos (3) /*!< EPWM_T::APDMACTL: APDMAEN3 Position */ +#define EPWM_APDMACTL_APDMAEN3_Msk (0x1ul << EPWM_APDMACTL_APDMAEN3_Pos) /*!< EPWM_T::APDMACTL: APDMAEN3 Mask */ + +#define EPWM_APDMACTL_APDMAEN4_Pos (4) /*!< EPWM_T::APDMACTL: APDMAEN4 Position */ +#define EPWM_APDMACTL_APDMAEN4_Msk (0x1ul << EPWM_APDMACTL_APDMAEN4_Pos) /*!< EPWM_T::APDMACTL: APDMAEN4 Mask */ + +#define EPWM_APDMACTL_APDMAEN5_Pos (5) /*!< EPWM_T::APDMACTL: APDMAEN5 Position */ +#define EPWM_APDMACTL_APDMAEN5_Msk (0x1ul << EPWM_APDMACTL_APDMAEN5_Pos) /*!< EPWM_T::APDMACTL: APDMAEN5 Mask */ + +#define EPWM_FDEN_FDEN0_Pos (0) /*!< EPWM_T::FDEN: FDEN0 Position */ +#define EPWM_FDEN_FDEN0_Msk (0x1ul << EPWM_FDEN_FDEN0_Pos) /*!< EPWM_T::FDEN: FDEN0 Mask */ + +#define EPWM_FDEN_FDEN1_Pos (1) /*!< EPWM_T::FDEN: FDEN1 Position */ +#define EPWM_FDEN_FDEN1_Msk (0x1ul << EPWM_FDEN_FDEN1_Pos) /*!< EPWM_T::FDEN: FDEN1 Mask */ + +#define EPWM_FDEN_FDEN2_Pos (2) /*!< EPWM_T::FDEN: FDEN2 Position */ +#define EPWM_FDEN_FDEN2_Msk (0x1ul << EPWM_FDEN_FDEN2_Pos) /*!< EPWM_T::FDEN: FDEN2 Mask */ + +#define EPWM_FDEN_FDEN3_Pos (3) /*!< EPWM_T::FDEN: FDEN3 Position */ +#define EPWM_FDEN_FDEN3_Msk (0x1ul << EPWM_FDEN_FDEN3_Pos) /*!< EPWM_T::FDEN: FDEN3 Mask */ + +#define EPWM_FDEN_FDEN4_Pos (4) /*!< EPWM_T::FDEN: FDEN4 Position */ +#define EPWM_FDEN_FDEN4_Msk (0x1ul << EPWM_FDEN_FDEN4_Pos) /*!< EPWM_T::FDEN: FDEN4 Mask */ + +#define EPWM_FDEN_FDEN5_Pos (5) /*!< EPWM_T::FDEN: FDEN5 Position */ +#define EPWM_FDEN_FDEN5_Msk (0x1ul << EPWM_FDEN_FDEN5_Pos) /*!< EPWM_T::FDEN: FDEN5 Mask */ + +#define EPWM_FDEN_FDODIS0_Pos (8) /*!< EPWM_T::FDEN: FDODIS0 Position */ +#define EPWM_FDEN_FDODIS0_Msk (0x1ul << EPWM_FDEN_FDODIS0_Pos) /*!< EPWM_T::FDEN: FDODIS0 Mask */ + +#define EPWM_FDEN_FDODIS1_Pos (9) /*!< EPWM_T::FDEN: FDODIS1 Position */ +#define EPWM_FDEN_FDODIS1_Msk (0x1ul << EPWM_FDEN_FDODIS1_Pos) /*!< EPWM_T::FDEN: FDODIS1 Mask */ + +#define EPWM_FDEN_FDODIS2_Pos (10) /*!< EPWM_T::FDEN: FDODIS2 Position */ +#define EPWM_FDEN_FDODIS2_Msk (0x1ul << EPWM_FDEN_FDODIS2_Pos) /*!< EPWM_T::FDEN: FDODIS2 Mask */ + +#define EPWM_FDEN_FDODIS3_Pos (11) /*!< EPWM_T::FDEN: FDODIS3 Position */ +#define EPWM_FDEN_FDODIS3_Msk (0x1ul << EPWM_FDEN_FDODIS3_Pos) /*!< EPWM_T::FDEN: FDODIS3 Mask */ + +#define EPWM_FDEN_FDODIS4_Pos (12) /*!< EPWM_T::FDEN: FDODIS4 Position */ +#define EPWM_FDEN_FDODIS4_Msk (0x1ul << EPWM_FDEN_FDODIS4_Pos) /*!< EPWM_T::FDEN: FDODIS4 Mask */ + +#define EPWM_FDEN_FDODIS5_Pos (13) /*!< EPWM_T::FDEN: FDODIS5 Position */ +#define EPWM_FDEN_FDODIS5_Msk (0x1ul << EPWM_FDEN_FDODIS5_Pos) /*!< EPWM_T::FDEN: FDODIS5 Mask */ + +#define EPWM_FDEN_FDCKS0_Pos (16) /*!< EPWM_T::FDEN: FDCKS0 Position */ +#define EPWM_FDEN_FDCKS0_Msk (0x1ul << EPWM_FDEN_FDCKS0_Pos) /*!< EPWM_T::FDEN: FDCKS0 Mask */ + +#define EPWM_FDEN_FDCKS1_Pos (17) /*!< EPWM_T::FDEN: FDCKS1 Position */ +#define EPWM_FDEN_FDCKS1_Msk (0x1ul << EPWM_FDEN_FDCKS1_Pos) /*!< EPWM_T::FDEN: FDCKS1 Mask */ + +#define EPWM_FDEN_FDCKS2_Pos (18) /*!< EPWM_T::FDEN: FDCKS2 Position */ +#define EPWM_FDEN_FDCKS2_Msk (0x1ul << EPWM_FDEN_FDCKS2_Pos) /*!< EPWM_T::FDEN: FDCKS2 Mask */ + +#define EPWM_FDEN_FDCKS3_Pos (19) /*!< EPWM_T::FDEN: FDCKS3 Position */ +#define EPWM_FDEN_FDCKS3_Msk (0x1ul << EPWM_FDEN_FDCKS3_Pos) /*!< EPWM_T::FDEN: FDCKS3 Mask */ + +#define EPWM_FDEN_FDCKS4_Pos (20) /*!< EPWM_T::FDEN: FDCKS4 Position */ +#define EPWM_FDEN_FDCKS4_Msk (0x1ul << EPWM_FDEN_FDCKS4_Pos) /*!< EPWM_T::FDEN: FDCKS4 Mask */ + +#define EPWM_FDEN_FDCKS5_Pos (21) /*!< EPWM_T::FDEN: FDCKS5 Position */ +#define EPWM_FDEN_FDCKS5_Msk (0x1ul << EPWM_FDEN_FDCKS5_Pos) /*!< EPWM_T::FDEN: FDCKS5 Mask */ + +#define EPWM_FDCTL0_TRMSKCNT_Pos (0) /*!< EPWM_T::FDCTL0: TRMSKCNT Position */ +#define EPWM_FDCTL0_TRMSKCNT_Msk (0x7ful << EPWM_FDCTL0_TRMSKCNT_Pos) /*!< EPWM_T::FDCTL0: TRMSKCNT Mask */ + +#define EPWM_FDCTL0_FDMSKEN_Pos (15) /*!< EPWM_T::FDCTL0: FDMSKEN Position */ +#define EPWM_FDCTL0_FDMSKEN_Msk (0x1ul << EPWM_FDCTL0_FDMSKEN_Pos) /*!< EPWM_T::FDCTL0: FDMSKEN Mask */ + +#define EPWM_FDCTL0_DGSMPCYC_Pos (16) /*!< EPWM_T::FDCTL0: DGSMPCYC Position */ +#define EPWM_FDCTL0_DGSMPCYC_Msk (0x7ul << EPWM_FDCTL0_DGSMPCYC_Pos) /*!< EPWM_T::FDCTL0: DGSMPCYC Mask */ + +#define EPWM_FDCTL0_FDCKSEL_Pos (28) /*!< EPWM_T::FDCTL0: FDCKSEL Position */ +#define EPWM_FDCTL0_FDCKSEL_Msk (0x3ul << EPWM_FDCTL0_FDCKSEL_Pos) /*!< EPWM_T::FDCTL0: FDCKSEL Mask */ + +#define EPWM_FDCTL0_FDDGEN_Pos (31) /*!< EPWM_T::FDCTL0: FDDGEN Position */ +#define EPWM_FDCTL0_FDDGEN_Msk (0x1ul << EPWM_FDCTL0_FDDGEN_Pos) /*!< EPWM_T::FDCTL0: FDDGEN Mask */ + +#define EPWM_FDCTL1_TRMSKCNT_Pos (0) /*!< EPWM_T::FDCTL1: TRMSKCNT Position */ +#define EPWM_FDCTL1_TRMSKCNT_Msk (0x7ful << EPWM_FDCTL1_TRMSKCNT_Pos) /*!< EPWM_T::FDCTL1: TRMSKCNT Mask */ + +#define EPWM_FDCTL1_FDMSKEN_Pos (15) /*!< EPWM_T::FDCTL1: FDMSKEN Position */ +#define EPWM_FDCTL1_FDMSKEN_Msk (0x1ul << EPWM_FDCTL1_FDMSKEN_Pos) /*!< EPWM_T::FDCTL1: FDMSKEN Mask */ + +#define EPWM_FDCTL1_DGSMPCYC_Pos (16) /*!< EPWM_T::FDCTL1: DGSMPCYC Position */ +#define EPWM_FDCTL1_DGSMPCYC_Msk (0x7ul << EPWM_FDCTL1_DGSMPCYC_Pos) /*!< EPWM_T::FDCTL1: DGSMPCYC Mask */ + +#define EPWM_FDCTL1_FDCKSEL_Pos (28) /*!< EPWM_T::FDCTL1: FDCKSEL Position */ +#define EPWM_FDCTL1_FDCKSEL_Msk (0x3ul << EPWM_FDCTL1_FDCKSEL_Pos) /*!< EPWM_T::FDCTL1: FDCKSEL Mask */ + +#define EPWM_FDCTL1_FDDGEN_Pos (31) /*!< EPWM_T::FDCTL1: FDDGEN Position */ +#define EPWM_FDCTL1_FDDGEN_Msk (0x1ul << EPWM_FDCTL1_FDDGEN_Pos) /*!< EPWM_T::FDCTL1: FDDGEN Mask */ + +#define EPWM_FDCTL2_TRMSKCNT_Pos (0) /*!< EPWM_T::FDCTL2: TRMSKCNT Position */ +#define EPWM_FDCTL2_TRMSKCNT_Msk (0x7ful << EPWM_FDCTL2_TRMSKCNT_Pos) /*!< EPWM_T::FDCTL2: TRMSKCNT Mask */ + +#define EPWM_FDCTL2_FDMSKEN_Pos (15) /*!< EPWM_T::FDCTL2: FDMSKEN Position */ +#define EPWM_FDCTL2_FDMSKEN_Msk (0x1ul << EPWM_FDCTL2_FDMSKEN_Pos) /*!< EPWM_T::FDCTL2: FDMSKEN Mask */ + +#define EPWM_FDCTL2_DGSMPCYC_Pos (16) /*!< EPWM_T::FDCTL2: DGSMPCYC Position */ +#define EPWM_FDCTL2_DGSMPCYC_Msk (0x7ul << EPWM_FDCTL2_DGSMPCYC_Pos) /*!< EPWM_T::FDCTL2: DGSMPCYC Mask */ + +#define EPWM_FDCTL2_FDCKSEL_Pos (28) /*!< EPWM_T::FDCTL2: FDCKSEL Position */ +#define EPWM_FDCTL2_FDCKSEL_Msk (0x3ul << EPWM_FDCTL2_FDCKSEL_Pos) /*!< EPWM_T::FDCTL2: FDCKSEL Mask */ + +#define EPWM_FDCTL2_FDDGEN_Pos (31) /*!< EPWM_T::FDCTL2: FDDGEN Position */ +#define EPWM_FDCTL2_FDDGEN_Msk (0x1ul << EPWM_FDCTL2_FDDGEN_Pos) /*!< EPWM_T::FDCTL2: FDDGEN Mask */ + +#define EPWM_FDCTL3_TRMSKCNT_Pos (0) /*!< EPWM_T::FDCTL3: TRMSKCNT Position */ +#define EPWM_FDCTL3_TRMSKCNT_Msk (0x7ful << EPWM_FDCTL3_TRMSKCNT_Pos) /*!< EPWM_T::FDCTL3: TRMSKCNT Mask */ + +#define EPWM_FDCTL3_FDMSKEN_Pos (15) /*!< EPWM_T::FDCTL3: FDMSKEN Position */ +#define EPWM_FDCTL3_FDMSKEN_Msk (0x1ul << EPWM_FDCTL3_FDMSKEN_Pos) /*!< EPWM_T::FDCTL3: FDMSKEN Mask */ + +#define EPWM_FDCTL3_DGSMPCYC_Pos (16) /*!< EPWM_T::FDCTL3: DGSMPCYC Position */ +#define EPWM_FDCTL3_DGSMPCYC_Msk (0x7ul << EPWM_FDCTL3_DGSMPCYC_Pos) /*!< EPWM_T::FDCTL3: DGSMPCYC Mask */ + +#define EPWM_FDCTL3_FDCKSEL_Pos (28) /*!< EPWM_T::FDCTL3: FDCKSEL Position */ +#define EPWM_FDCTL3_FDCKSEL_Msk (0x3ul << EPWM_FDCTL3_FDCKSEL_Pos) /*!< EPWM_T::FDCTL3: FDCKSEL Mask */ + +#define EPWM_FDCTL3_FDDGEN_Pos (31) /*!< EPWM_T::FDCTL3: FDDGEN Position */ +#define EPWM_FDCTL3_FDDGEN_Msk (0x1ul << EPWM_FDCTL3_FDDGEN_Pos) /*!< EPWM_T::FDCTL3: FDDGEN Mask */ + +#define EPWM_FDCTL4_TRMSKCNT_Pos (0) /*!< EPWM_T::FDCTL4: TRMSKCNT Position */ +#define EPWM_FDCTL4_TRMSKCNT_Msk (0x7ful << EPWM_FDCTL4_TRMSKCNT_Pos) /*!< EPWM_T::FDCTL4: TRMSKCNT Mask */ + +#define EPWM_FDCTL4_FDMSKEN_Pos (15) /*!< EPWM_T::FDCTL4: FDMSKEN Position */ +#define EPWM_FDCTL4_FDMSKEN_Msk (0x1ul << EPWM_FDCTL4_FDMSKEN_Pos) /*!< EPWM_T::FDCTL4: FDMSKEN Mask */ + +#define EPWM_FDCTL4_DGSMPCYC_Pos (16) /*!< EPWM_T::FDCTL4: DGSMPCYC Position */ +#define EPWM_FDCTL4_DGSMPCYC_Msk (0x7ul << EPWM_FDCTL4_DGSMPCYC_Pos) /*!< EPWM_T::FDCTL4: DGSMPCYC Mask */ + +#define EPWM_FDCTL4_FDCKSEL_Pos (28) /*!< EPWM_T::FDCTL4: FDCKSEL Position */ +#define EPWM_FDCTL4_FDCKSEL_Msk (0x3ul << EPWM_FDCTL4_FDCKSEL_Pos) /*!< EPWM_T::FDCTL4: FDCKSEL Mask */ + +#define EPWM_FDCTL4_FDDGEN_Pos (31) /*!< EPWM_T::FDCTL4: FDDGEN Position */ +#define EPWM_FDCTL4_FDDGEN_Msk (0x1ul << EPWM_FDCTL4_FDDGEN_Pos) /*!< EPWM_T::FDCTL4: FDDGEN Mask */ + +#define EPWM_FDCTL5_TRMSKCNT_Pos (0) /*!< EPWM_T::FDCTL5: TRMSKCNT Position */ +#define EPWM_FDCTL5_TRMSKCNT_Msk (0x7ful << EPWM_FDCTL5_TRMSKCNT_Pos) /*!< EPWM_T::FDCTL5: TRMSKCNT Mask */ + +#define EPWM_FDCTL5_FDMSKEN_Pos (15) /*!< EPWM_T::FDCTL5: FDMSKEN Position */ +#define EPWM_FDCTL5_FDMSKEN_Msk (0x1ul << EPWM_FDCTL5_FDMSKEN_Pos) /*!< EPWM_T::FDCTL5: FDMSKEN Mask */ + +#define EPWM_FDCTL5_DGSMPCYC_Pos (16) /*!< EPWM_T::FDCTL5: DGSMPCYC Position */ +#define EPWM_FDCTL5_DGSMPCYC_Msk (0x7ul << EPWM_FDCTL5_DGSMPCYC_Pos) /*!< EPWM_T::FDCTL5: DGSMPCYC Mask */ + +#define EPWM_FDCTL5_FDCKSEL_Pos (28) /*!< EPWM_T::FDCTL5: FDCKSEL Position */ +#define EPWM_FDCTL5_FDCKSEL_Msk (0x3ul << EPWM_FDCTL5_FDCKSEL_Pos) /*!< EPWM_T::FDCTL5: FDCKSEL Mask */ + +#define EPWM_FDCTL5_FDDGEN_Pos (31) /*!< EPWM_T::FDCTL5: FDDGEN Position */ +#define EPWM_FDCTL5_FDDGEN_Msk (0x1ul << EPWM_FDCTL5_FDDGEN_Pos) /*!< EPWM_T::FDCTL5: FDDGEN Mask */ + +#define EPWM_FDIEN_FDIENn_Pos (0) /*!< EPWM_T::FDIEN: FDIENn Position */ +#define EPWM_FDIEN_FDIENn_Msk (0x1ul << EPWM_FDIEN_FDIENn_Pos) /*!< EPWM_T::FDIEN: FDIENn Mask */ + +#define EPWM_FDSTS_FDIFn_Pos (0) /*!< EPWM_T::FDSTS: FDIFn Position */ +#define EPWM_FDSTS_FDIFn_Msk (0x3ful << EPWM_FDSTS_FDIFn_Pos) /*!< EPWM_T::FDSTS: FDIFn Mask */ + +#define EPWM_FDIEN_FDIEN0_Pos (0) /*!< EPWM_T::FDIEN: FDIEN0 Position */ +#define EPWM_FDIEN_FDIEN0_Msk (0x1ul << EPWM_FDIEN_FDIEN0_Pos) /*!< EPWM_T::FDIEN: FDIEN0 Mask */ + +#define EPWM_FDIEN_FDIEN1_Pos (1) /*!< EPWM_T::FDIEN: FDIEN1 Position */ +#define EPWM_FDIEN_FDIEN1_Msk (0x1ul << EPWM_FDIEN_FDIEN1_Pos) /*!< EPWM_T::FDIEN: FDIEN1 Mask */ + +#define EPWM_FDIEN_FDIEN2_Pos (2) /*!< EPWM_T::FDIEN: FDIEN2 Position */ +#define EPWM_FDIEN_FDIEN2_Msk (0x1ul << EPWM_FDIEN_FDIEN2_Pos) /*!< EPWM_T::FDIEN: FDIEN2 Mask */ + +#define EPWM_FDIEN_FDIEN3_Pos (3) /*!< EPWM_T::FDIEN: FDIEN3 Position */ +#define EPWM_FDIEN_FDIEN3_Msk (0x1ul << EPWM_FDIEN_FDIEN3_Pos) /*!< EPWM_T::FDIEN: FDIEN3 Mask */ + +#define EPWM_FDIEN_FDIEN4_Pos (4) /*!< EPWM_T::FDIEN: FDIEN4 Position */ +#define EPWM_FDIEN_FDIEN4_Msk (0x1ul << EPWM_FDIEN_FDIEN4_Pos) /*!< EPWM_T::FDIEN: FDIEN4 Mask */ + +#define EPWM_FDIEN_FDIEN5_Pos (5) /*!< EPWM_T::FDIEN: FDIEN5 Position */ +#define EPWM_FDIEN_FDIEN5_Msk (0x1ul << EPWM_FDIEN_FDIEN5_Pos) /*!< EPWM_T::FDIEN: FDIEN5 Mask */ + +#define EPWM_FDSTS_FDIF0_Pos (0) /*!< EPWM_T::FDSTS: FDIF0 Position */ +#define EPWM_FDSTS_FDIF0_Msk (0x1ul << EPWM_FDSTS_FDIF0_Pos) /*!< EPWM_T::FDSTS: FDIF0 Mask */ + +#define EPWM_FDSTS_FDIF1_Pos (1) /*!< EPWM_T::FDSTS: FDIF1 Position */ +#define EPWM_FDSTS_FDIF1_Msk (0x1ul << EPWM_FDSTS_FDIF1_Pos) /*!< EPWM_T::FDSTS: FDIF1 Mask */ + +#define EPWM_FDSTS_FDIF2_Pos (2) /*!< EPWM_T::FDSTS: FDIF2 Position */ +#define EPWM_FDSTS_FDIF2_Msk (0x1ul << EPWM_FDSTS_FDIF2_Pos) /*!< EPWM_T::FDSTS: FDIF2 Mask */ + +#define EPWM_FDSTS_FDIF3_Pos (3) /*!< EPWM_T::FDSTS: FDIF3 Position */ +#define EPWM_FDSTS_FDIF3_Msk (0x1ul << EPWM_FDSTS_FDIF3_Pos) /*!< EPWM_T::FDSTS: FDIF3 Mask */ + +#define EPWM_FDSTS_FDIF4_Pos (4) /*!< EPWM_T::FDSTS: FDIF4 Position */ +#define EPWM_FDSTS_FDIF4_Msk (0x1ul << EPWM_FDSTS_FDIF4_Pos) /*!< EPWM_T::FDSTS: FDIF4 Mask */ + +#define EPWM_FDSTS_FDIF5_Pos (5) /*!< EPWM_T::FDSTS: FDIF5 Position */ +#define EPWM_FDSTS_FDIF5_Msk (0x1ul << EPWM_FDSTS_FDIF5_Pos) /*!< EPWM_T::FDSTS: FDIF5 Mask */ + +#define EPWM_EADCPSCCTL_PSCEN0_Pos (0) /*!< EPWM_T::EADCPSCCTL: PSCEN0 Position */ +#define EPWM_EADCPSCCTL_PSCEN0_Msk (0x1ul << EPWM_EADCPSCCTL_PSCEN0_Pos) /*!< EPWM_T::EADCPSCCTL: PSCEN0 Mask */ + +#define EPWM_EADCPSCCTL_PSCEN1_Pos (1) /*!< EPWM_T::EADCPSCCTL: PSCEN1 Position */ +#define EPWM_EADCPSCCTL_PSCEN1_Msk (0x1ul << EPWM_EADCPSCCTL_PSCEN1_Pos) /*!< EPWM_T::EADCPSCCTL: PSCEN1 Mask */ + +#define EPWM_EADCPSCCTL_PSCEN2_Pos (2) /*!< EPWM_T::EADCPSCCTL: PSCEN2 Position */ +#define EPWM_EADCPSCCTL_PSCEN2_Msk (0x1ul << EPWM_EADCPSCCTL_PSCEN2_Pos) /*!< EPWM_T::EADCPSCCTL: PSCEN2 Mask */ + +#define EPWM_EADCPSCCTL_PSCEN3_Pos (3) /*!< EPWM_T::EADCPSCCTL: PSCEN3 Position */ +#define EPWM_EADCPSCCTL_PSCEN3_Msk (0x1ul << EPWM_EADCPSCCTL_PSCEN3_Pos) /*!< EPWM_T::EADCPSCCTL: PSCEN3 Mask */ + +#define EPWM_EADCPSCCTL_PSCEN4_Pos (4) /*!< EPWM_T::EADCPSCCTL: PSCEN4 Position */ +#define EPWM_EADCPSCCTL_PSCEN4_Msk (0x1ul << EPWM_EADCPSCCTL_PSCEN4_Pos) /*!< EPWM_T::EADCPSCCTL: PSCEN4 Mask */ + +#define EPWM_EADCPSCCTL_PSCEN5_Pos (5) /*!< EPWM_T::EADCPSCCTL: PSCEN5 Position */ +#define EPWM_EADCPSCCTL_PSCEN5_Msk (0x1ul << EPWM_EADCPSCCTL_PSCEN5_Pos) /*!< EPWM_T::EADCPSCCTL: PSCEN5 Mask */ + +#define EPWM_EADCPSC0_EADCPSC0_Pos (0) /*!< EPWM_T::EADCPSC0: EADCPSC0 Position */ +#define EPWM_EADCPSC0_EADCPSC0_Msk (0xful << EPWM_EADCPSC0_EADCPSC0_Pos) /*!< EPWM_T::EADCPSC0: EADCPSC0 Mask */ + +#define EPWM_EADCPSC0_EADCPSC1_Pos (8) /*!< EPWM_T::EADCPSC0: EADCPSC1 Position */ +#define EPWM_EADCPSC0_EADCPSC1_Msk (0xful << EPWM_EADCPSC0_EADCPSC1_Pos) /*!< EPWM_T::EADCPSC0: EADCPSC1 Mask */ + +#define EPWM_EADCPSC0_EADCPSC2_Pos (16) /*!< EPWM_T::EADCPSC0: EADCPSC2 Position */ +#define EPWM_EADCPSC0_EADCPSC2_Msk (0xful << EPWM_EADCPSC0_EADCPSC2_Pos) /*!< EPWM_T::EADCPSC0: EADCPSC2 Mask */ + +#define EPWM_EADCPSC0_EADCPSC3_Pos (24) /*!< EPWM_T::EADCPSC0: EADCPSC3 Position */ +#define EPWM_EADCPSC0_EADCPSC3_Msk (0xful << EPWM_EADCPSC0_EADCPSC3_Pos) /*!< EPWM_T::EADCPSC0: EADCPSC3 Mask */ + +#define EPWM_EADCPSC1_EADCPSC4_Pos (0) /*!< EPWM_T::EADCPSC1: EADCPSC4 Position */ +#define EPWM_EADCPSC1_EADCPSC4_Msk (0xful << EPWM_EADCPSC1_EADCPSC4_Pos) /*!< EPWM_T::EADCPSC1: EADCPSC4 Mask */ + +#define EPWM_EADCPSC1_EADCPSC5_Pos (8) /*!< EPWM_T::EADCPSC1: EADCPSC5 Position */ +#define EPWM_EADCPSC1_EADCPSC5_Msk (0xful << EPWM_EADCPSC1_EADCPSC5_Pos) /*!< EPWM_T::EADCPSC1: EADCPSC5 Mask */ + +#define EPWM_EADCPSCNT0_PSCNT0_Pos (0) /*!< EPWM_T::EADCPSCNT0: PSCNT0 Position */ +#define EPWM_EADCPSCNT0_PSCNT0_Msk (0xful << EPWM_EADCPSCNT0_PSCNT0_Pos) /*!< EPWM_T::EADCPSCNT0: PSCNT0 Mask */ + +#define EPWM_EADCPSCNT0_PSCNT1_Pos (8) /*!< EPWM_T::EADCPSCNT0: PSCNT1 Position */ +#define EPWM_EADCPSCNT0_PSCNT1_Msk (0xful << EPWM_EADCPSCNT0_PSCNT1_Pos) /*!< EPWM_T::EADCPSCNT0: PSCNT1 Mask */ + +#define EPWM_EADCPSCNT0_PSCNT2_Pos (16) /*!< EPWM_T::EADCPSCNT0: PSCNT2 Position */ +#define EPWM_EADCPSCNT0_PSCNT2_Msk (0xful << EPWM_EADCPSCNT0_PSCNT2_Pos) /*!< EPWM_T::EADCPSCNT0: PSCNT2 Mask */ + +#define EPWM_EADCPSCNT0_PSCNT3_Pos (24) /*!< EPWM_T::EADCPSCNT0: PSCNT3 Position */ +#define EPWM_EADCPSCNT0_PSCNT3_Msk (0xful << EPWM_EADCPSCNT0_PSCNT3_Pos) /*!< EPWM_T::EADCPSCNT0: PSCNT3 Mask */ + +#define EPWM_EADCPSCNT1_PSCNT4_Pos (0) /*!< EPWM_T::EADCPSCNT1: PSCNT4 Position */ +#define EPWM_EADCPSCNT1_PSCNT4_Msk (0xful << EPWM_EADCPSCNT1_PSCNT4_Pos) /*!< EPWM_T::EADCPSCNT1: PSCNT4 Mask */ + +#define EPWM_EADCPSCNT1_PSCNT5_Pos (8) /*!< EPWM_T::EADCPSCNT1: PSCNT5 Position */ +#define EPWM_EADCPSCNT1_PSCNT5_Msk (0xful << EPWM_EADCPSCNT1_PSCNT5_Pos) /*!< EPWM_T::EADCPSCNT1: PSCNT5 Mask */ + +#define EPWM_CAPINEN_CAPINEN0_Pos (0) /*!< EPWM_T::CAPINEN: CAPINEN0 Position */ +#define EPWM_CAPINEN_CAPINEN0_Msk (0x1ul << EPWM_CAPINEN_CAPINEN0_Pos) /*!< EPWM_T::CAPINEN: CAPINEN0 Mask */ + +#define EPWM_CAPINEN_CAPINEN1_Pos (1) /*!< EPWM_T::CAPINEN: CAPINEN1 Position */ +#define EPWM_CAPINEN_CAPINEN1_Msk (0x1ul << EPWM_CAPINEN_CAPINEN1_Pos) /*!< EPWM_T::CAPINEN: CAPINEN1 Mask */ + +#define EPWM_CAPINEN_CAPINEN2_Pos (2) /*!< EPWM_T::CAPINEN: CAPINEN2 Position */ +#define EPWM_CAPINEN_CAPINEN2_Msk (0x1ul << EPWM_CAPINEN_CAPINEN2_Pos) /*!< EPWM_T::CAPINEN: CAPINEN2 Mask */ + +#define EPWM_CAPINEN_CAPINEN3_Pos (3) /*!< EPWM_T::CAPINEN: CAPINEN3 Position */ +#define EPWM_CAPINEN_CAPINEN3_Msk (0x1ul << EPWM_CAPINEN_CAPINEN3_Pos) /*!< EPWM_T::CAPINEN: CAPINEN3 Mask */ + +#define EPWM_CAPINEN_CAPINEN4_Pos (4) /*!< EPWM_T::CAPINEN: CAPINEN4 Position */ +#define EPWM_CAPINEN_CAPINEN4_Msk (0x1ul << EPWM_CAPINEN_CAPINEN4_Pos) /*!< EPWM_T::CAPINEN: CAPINEN4 Mask */ + +#define EPWM_CAPINEN_CAPINEN5_Pos (5) /*!< EPWM_T::CAPINEN: CAPINEN5 Position */ +#define EPWM_CAPINEN_CAPINEN5_Msk (0x1ul << EPWM_CAPINEN_CAPINEN5_Pos) /*!< EPWM_T::CAPINEN: CAPINEN5 Mask */ + +#define EPWM_CAPCTL_CAPEN0_Pos (0) /*!< EPWM_T::CAPCTL: CAPEN0 Position */ +#define EPWM_CAPCTL_CAPEN0_Msk (0x1ul << EPWM_CAPCTL_CAPEN0_Pos) /*!< EPWM_T::CAPCTL: CAPEN0 Mask */ + +#define EPWM_CAPCTL_CAPEN1_Pos (1) /*!< EPWM_T::CAPCTL: CAPEN1 Position */ +#define EPWM_CAPCTL_CAPEN1_Msk (0x1ul << EPWM_CAPCTL_CAPEN1_Pos) /*!< EPWM_T::CAPCTL: CAPEN1 Mask */ + +#define EPWM_CAPCTL_CAPEN2_Pos (2) /*!< EPWM_T::CAPCTL: CAPEN2 Position */ +#define EPWM_CAPCTL_CAPEN2_Msk (0x1ul << EPWM_CAPCTL_CAPEN2_Pos) /*!< EPWM_T::CAPCTL: CAPEN2 Mask */ + +#define EPWM_CAPCTL_CAPEN3_Pos (3) /*!< EPWM_T::CAPCTL: CAPEN3 Position */ +#define EPWM_CAPCTL_CAPEN3_Msk (0x1ul << EPWM_CAPCTL_CAPEN3_Pos) /*!< EPWM_T::CAPCTL: CAPEN3 Mask */ + +#define EPWM_CAPCTL_CAPEN4_Pos (4) /*!< EPWM_T::CAPCTL: CAPEN4 Position */ +#define EPWM_CAPCTL_CAPEN4_Msk (0x1ul << EPWM_CAPCTL_CAPEN4_Pos) /*!< EPWM_T::CAPCTL: CAPEN4 Mask */ + +#define EPWM_CAPCTL_CAPEN5_Pos (5) /*!< EPWM_T::CAPCTL: CAPEN5 Position */ +#define EPWM_CAPCTL_CAPEN5_Msk (0x1ul << EPWM_CAPCTL_CAPEN5_Pos) /*!< EPWM_T::CAPCTL: CAPEN5 Mask */ + +#define EPWM_CAPCTL_CAPINV0_Pos (8) /*!< EPWM_T::CAPCTL: CAPINV0 Position */ +#define EPWM_CAPCTL_CAPINV0_Msk (0x1ul << EPWM_CAPCTL_CAPINV0_Pos) /*!< EPWM_T::CAPCTL: CAPINV0 Mask */ + +#define EPWM_CAPCTL_CAPINV1_Pos (9) /*!< EPWM_T::CAPCTL: CAPINV1 Position */ +#define EPWM_CAPCTL_CAPINV1_Msk (0x1ul << EPWM_CAPCTL_CAPINV1_Pos) /*!< EPWM_T::CAPCTL: CAPINV1 Mask */ + +#define EPWM_CAPCTL_CAPINV2_Pos (10) /*!< EPWM_T::CAPCTL: CAPINV2 Position */ +#define EPWM_CAPCTL_CAPINV2_Msk (0x1ul << EPWM_CAPCTL_CAPINV2_Pos) /*!< EPWM_T::CAPCTL: CAPINV2 Mask */ + +#define EPWM_CAPCTL_CAPINV3_Pos (11) /*!< EPWM_T::CAPCTL: CAPINV3 Position */ +#define EPWM_CAPCTL_CAPINV3_Msk (0x1ul << EPWM_CAPCTL_CAPINV3_Pos) /*!< EPWM_T::CAPCTL: CAPINV3 Mask */ + +#define EPWM_CAPCTL_CAPINV4_Pos (12) /*!< EPWM_T::CAPCTL: CAPINV4 Position */ +#define EPWM_CAPCTL_CAPINV4_Msk (0x1ul << EPWM_CAPCTL_CAPINV4_Pos) /*!< EPWM_T::CAPCTL: CAPINV4 Mask */ + +#define EPWM_CAPCTL_CAPINV5_Pos (13) /*!< EPWM_T::CAPCTL: CAPINV5 Position */ +#define EPWM_CAPCTL_CAPINV5_Msk (0x1ul << EPWM_CAPCTL_CAPINV5_Pos) /*!< EPWM_T::CAPCTL: CAPINV5 Mask */ + +#define EPWM_CAPCTL_RCRLDEN0_Pos (16) /*!< EPWM_T::CAPCTL: RCRLDEN0 Position */ +#define EPWM_CAPCTL_RCRLDEN0_Msk (0x1ul << EPWM_CAPCTL_RCRLDEN0_Pos) /*!< EPWM_T::CAPCTL: RCRLDEN0 Mask */ + +#define EPWM_CAPCTL_RCRLDEN1_Pos (17) /*!< EPWM_T::CAPCTL: RCRLDEN1 Position */ +#define EPWM_CAPCTL_RCRLDEN1_Msk (0x1ul << EPWM_CAPCTL_RCRLDEN1_Pos) /*!< EPWM_T::CAPCTL: RCRLDEN1 Mask */ + +#define EPWM_CAPCTL_RCRLDEN2_Pos (18) /*!< EPWM_T::CAPCTL: RCRLDEN2 Position */ +#define EPWM_CAPCTL_RCRLDEN2_Msk (0x1ul << EPWM_CAPCTL_RCRLDEN2_Pos) /*!< EPWM_T::CAPCTL: RCRLDEN2 Mask */ + +#define EPWM_CAPCTL_RCRLDEN3_Pos (19) /*!< EPWM_T::CAPCTL: RCRLDEN3 Position */ +#define EPWM_CAPCTL_RCRLDEN3_Msk (0x1ul << EPWM_CAPCTL_RCRLDEN3_Pos) /*!< EPWM_T::CAPCTL: RCRLDEN3 Mask */ + +#define EPWM_CAPCTL_RCRLDEN4_Pos (20) /*!< EPWM_T::CAPCTL: RCRLDEN4 Position */ +#define EPWM_CAPCTL_RCRLDEN4_Msk (0x1ul << EPWM_CAPCTL_RCRLDEN4_Pos) /*!< EPWM_T::CAPCTL: RCRLDEN4 Mask */ + +#define EPWM_CAPCTL_RCRLDEN5_Pos (21) /*!< EPWM_T::CAPCTL: RCRLDEN5 Position */ +#define EPWM_CAPCTL_RCRLDEN5_Msk (0x1ul << EPWM_CAPCTL_RCRLDEN5_Pos) /*!< EPWM_T::CAPCTL: RCRLDEN5 Mask */ + +#define EPWM_CAPCTL_FCRLDEN0_Pos (24) /*!< EPWM_T::CAPCTL: FCRLDEN0 Position */ +#define EPWM_CAPCTL_FCRLDEN0_Msk (0x1ul << EPWM_CAPCTL_FCRLDEN0_Pos) /*!< EPWM_T::CAPCTL: FCRLDEN0 Mask */ + +#define EPWM_CAPCTL_FCRLDEN1_Pos (25) /*!< EPWM_T::CAPCTL: FCRLDEN1 Position */ +#define EPWM_CAPCTL_FCRLDEN1_Msk (0x1ul << EPWM_CAPCTL_FCRLDEN1_Pos) /*!< EPWM_T::CAPCTL: FCRLDEN1 Mask */ + +#define EPWM_CAPCTL_FCRLDEN2_Pos (26) /*!< EPWM_T::CAPCTL: FCRLDEN2 Position */ +#define EPWM_CAPCTL_FCRLDEN2_Msk (0x1ul << EPWM_CAPCTL_FCRLDEN2_Pos) /*!< EPWM_T::CAPCTL: FCRLDEN2 Mask */ + +#define EPWM_CAPCTL_FCRLDEN3_Pos (27) /*!< EPWM_T::CAPCTL: FCRLDEN3 Position */ +#define EPWM_CAPCTL_FCRLDEN3_Msk (0x1ul << EPWM_CAPCTL_FCRLDEN3_Pos) /*!< EPWM_T::CAPCTL: FCRLDEN3 Mask */ + +#define EPWM_CAPCTL_FCRLDEN4_Pos (28) /*!< EPWM_T::CAPCTL: FCRLDEN4 Position */ +#define EPWM_CAPCTL_FCRLDEN4_Msk (0x1ul << EPWM_CAPCTL_FCRLDEN4_Pos) /*!< EPWM_T::CAPCTL: FCRLDEN4 Mask */ + +#define EPWM_CAPCTL_FCRLDEN5_Pos (29) /*!< EPWM_T::CAPCTL: FCRLDEN5 Position */ +#define EPWM_CAPCTL_FCRLDEN5_Msk (0x1ul << EPWM_CAPCTL_FCRLDEN5_Pos) /*!< EPWM_T::CAPCTL: FCRLDEN5 Mask */ + +#define EPWM_CAPSTS_CRLIFOV0_Pos (0) /*!< EPWM_T::CAPSTS: CRLIFOV0 Position */ +#define EPWM_CAPSTS_CRLIFOV0_Msk (0x1ul << EPWM_CAPSTS_CRLIFOV0_Pos) /*!< EPWM_T::CAPSTS: CRLIFOV0 Mask */ + +#define EPWM_CAPSTS_CRLIFOV1_Pos (1) /*!< EPWM_T::CAPSTS: CRLIFOV1 Position */ +#define EPWM_CAPSTS_CRLIFOV1_Msk (0x1ul << EPWM_CAPSTS_CRLIFOV1_Pos) /*!< EPWM_T::CAPSTS: CRLIFOV1 Mask */ + +#define EPWM_CAPSTS_CRLIFOV2_Pos (2) /*!< EPWM_T::CAPSTS: CRLIFOV2 Position */ +#define EPWM_CAPSTS_CRLIFOV2_Msk (0x1ul << EPWM_CAPSTS_CRLIFOV2_Pos) /*!< EPWM_T::CAPSTS: CRLIFOV2 Mask */ + +#define EPWM_CAPSTS_CRLIFOV3_Pos (3) /*!< EPWM_T::CAPSTS: CRLIFOV3 Position */ +#define EPWM_CAPSTS_CRLIFOV3_Msk (0x1ul << EPWM_CAPSTS_CRLIFOV3_Pos) /*!< EPWM_T::CAPSTS: CRLIFOV3 Mask */ + +#define EPWM_CAPSTS_CRLIFOV4_Pos (4) /*!< EPWM_T::CAPSTS: CRLIFOV4 Position */ +#define EPWM_CAPSTS_CRLIFOV4_Msk (0x1ul << EPWM_CAPSTS_CRLIFOV4_Pos) /*!< EPWM_T::CAPSTS: CRLIFOV4 Mask */ + +#define EPWM_CAPSTS_CRLIFOV5_Pos (5) /*!< EPWM_T::CAPSTS: CRLIFOV5 Position */ +#define EPWM_CAPSTS_CRLIFOV5_Msk (0x1ul << EPWM_CAPSTS_CRLIFOV5_Pos) /*!< EPWM_T::CAPSTS: CRLIFOV5 Mask */ + +#define EPWM_CAPSTS_CFLIFOV0_Pos (8) /*!< EPWM_T::CAPSTS: CFLIFOV0 Position */ +#define EPWM_CAPSTS_CFLIFOV0_Msk (0x1ul << EPWM_CAPSTS_CFLIFOV0_Pos) /*!< EPWM_T::CAPSTS: CFLIFOV0 Mask */ + +#define EPWM_CAPSTS_CFLIFOV1_Pos (9) /*!< EPWM_T::CAPSTS: CFLIFOV1 Position */ +#define EPWM_CAPSTS_CFLIFOV1_Msk (0x1ul << EPWM_CAPSTS_CFLIFOV1_Pos) /*!< EPWM_T::CAPSTS: CFLIFOV1 Mask */ + +#define EPWM_CAPSTS_CFLIFOV2_Pos (10) /*!< EPWM_T::CAPSTS: CFLIFOV2 Position */ +#define EPWM_CAPSTS_CFLIFOV2_Msk (0x1ul << EPWM_CAPSTS_CFLIFOV2_Pos) /*!< EPWM_T::CAPSTS: CFLIFOV2 Mask */ + +#define EPWM_CAPSTS_CFLIFOV3_Pos (11) /*!< EPWM_T::CAPSTS: CFLIFOV3 Position */ +#define EPWM_CAPSTS_CFLIFOV3_Msk (0x1ul << EPWM_CAPSTS_CFLIFOV3_Pos) /*!< EPWM_T::CAPSTS: CFLIFOV3 Mask */ + +#define EPWM_CAPSTS_CFLIFOV4_Pos (12) /*!< EPWM_T::CAPSTS: CFLIFOV4 Position */ +#define EPWM_CAPSTS_CFLIFOV4_Msk (0x1ul << EPWM_CAPSTS_CFLIFOV4_Pos) /*!< EPWM_T::CAPSTS: CFLIFOV4 Mask */ + +#define EPWM_CAPSTS_CFLIFOV5_Pos (13) /*!< EPWM_T::CAPSTS: CFLIFOV5 Position */ +#define EPWM_CAPSTS_CFLIFOV5_Msk (0x1ul << EPWM_CAPSTS_CFLIFOV5_Pos) /*!< EPWM_T::CAPSTS: CFLIFOV5 Mask */ + +#define EPWM_RCAPDAT0_RCAPDAT_Pos (0) /*!< EPWM_T::RCAPDAT0: RCAPDAT Position */ +#define EPWM_RCAPDAT0_RCAPDAT_Msk (0xfffful << EPWM_RCAPDAT0_RCAPDAT_Pos) /*!< EPWM_T::RCAPDAT0: RCAPDAT Mask */ + +#define EPWM_FCAPDAT0_FCAPDAT_Pos (0) /*!< EPWM_T::FCAPDAT0: FCAPDAT Position */ +#define EPWM_FCAPDAT0_FCAPDAT_Msk (0xfffful << EPWM_FCAPDAT0_FCAPDAT_Pos) /*!< EPWM_T::FCAPDAT0: FCAPDAT Mask */ + +#define EPWM_RCAPDAT1_RCAPDAT_Pos (0) /*!< EPWM_T::RCAPDAT1: RCAPDAT Position */ +#define EPWM_RCAPDAT1_RCAPDAT_Msk (0xfffful << EPWM_RCAPDAT1_RCAPDAT_Pos) /*!< EPWM_T::RCAPDAT1: RCAPDAT Mask */ + +#define EPWM_FCAPDAT1_FCAPDAT_Pos (0) /*!< EPWM_T::FCAPDAT1: FCAPDAT Position */ +#define EPWM_FCAPDAT1_FCAPDAT_Msk (0xfffful << EPWM_FCAPDAT1_FCAPDAT_Pos) /*!< EPWM_T::FCAPDAT1: FCAPDAT Mask */ + +#define EPWM_RCAPDAT2_RCAPDAT_Pos (0) /*!< EPWM_T::RCAPDAT2: RCAPDAT Position */ +#define EPWM_RCAPDAT2_RCAPDAT_Msk (0xfffful << EPWM_RCAPDAT2_RCAPDAT_Pos) /*!< EPWM_T::RCAPDAT2: RCAPDAT Mask */ + +#define EPWM_FCAPDAT2_FCAPDAT_Pos (0) /*!< EPWM_T::FCAPDAT2: FCAPDAT Position */ +#define EPWM_FCAPDAT2_FCAPDAT_Msk (0xfffful << EPWM_FCAPDAT2_FCAPDAT_Pos) /*!< EPWM_T::FCAPDAT2: FCAPDAT Mask */ + +#define EPWM_RCAPDAT3_RCAPDAT_Pos (0) /*!< EPWM_T::RCAPDAT3: RCAPDAT Position */ +#define EPWM_RCAPDAT3_RCAPDAT_Msk (0xfffful << EPWM_RCAPDAT3_RCAPDAT_Pos) /*!< EPWM_T::RCAPDAT3: RCAPDAT Mask */ + +#define EPWM_FCAPDAT3_FCAPDAT_Pos (0) /*!< EPWM_T::FCAPDAT3: FCAPDAT Position */ +#define EPWM_FCAPDAT3_FCAPDAT_Msk (0xfffful << EPWM_FCAPDAT3_FCAPDAT_Pos) /*!< EPWM_T::FCAPDAT3: FCAPDAT Mask */ + +#define EPWM_RCAPDAT4_RCAPDAT_Pos (0) /*!< EPWM_T::RCAPDAT4: RCAPDAT Position */ +#define EPWM_RCAPDAT4_RCAPDAT_Msk (0xfffful << EPWM_RCAPDAT4_RCAPDAT_Pos) /*!< EPWM_T::RCAPDAT4: RCAPDAT Mask */ + +#define EPWM_FCAPDAT4_FCAPDAT_Pos (0) /*!< EPWM_T::FCAPDAT4: FCAPDAT Position */ +#define EPWM_FCAPDAT4_FCAPDAT_Msk (0xfffful << EPWM_FCAPDAT4_FCAPDAT_Pos) /*!< EPWM_T::FCAPDAT4: FCAPDAT Mask */ + +#define EPWM_RCAPDAT5_RCAPDAT_Pos (0) /*!< EPWM_T::RCAPDAT5: RCAPDAT Position */ +#define EPWM_RCAPDAT5_RCAPDAT_Msk (0xfffful << EPWM_RCAPDAT5_RCAPDAT_Pos) /*!< EPWM_T::RCAPDAT5: RCAPDAT Mask */ + +#define EPWM_FCAPDAT5_FCAPDAT_Pos (0) /*!< EPWM_T::FCAPDAT5: FCAPDAT Position */ +#define EPWM_FCAPDAT5_FCAPDAT_Msk (0xfffful << EPWM_FCAPDAT5_FCAPDAT_Pos) /*!< EPWM_T::FCAPDAT5: FCAPDAT Mask */ + +#define EPWM_PDMACTL_CHEN0_1_Pos (0) /*!< EPWM_T::PDMACTL: CHEN0_1 Position */ +#define EPWM_PDMACTL_CHEN0_1_Msk (0x1ul << EPWM_PDMACTL_CHEN0_1_Pos) /*!< EPWM_T::PDMACTL: CHEN0_1 Mask */ + +#define EPWM_PDMACTL_CAPMOD0_1_Pos (1) /*!< EPWM_T::PDMACTL: CAPMOD0_1 Position */ +#define EPWM_PDMACTL_CAPMOD0_1_Msk (0x3ul << EPWM_PDMACTL_CAPMOD0_1_Pos) /*!< EPWM_T::PDMACTL: CAPMOD0_1 Mask */ + +#define EPWM_PDMACTL_CAPORD0_1_Pos (3) /*!< EPWM_T::PDMACTL: CAPORD0_1 Position */ +#define EPWM_PDMACTL_CAPORD0_1_Msk (0x1ul << EPWM_PDMACTL_CAPORD0_1_Pos) /*!< EPWM_T::PDMACTL: CAPORD0_1 Mask */ + +#define EPWM_PDMACTL_CHSEL0_1_Pos (4) /*!< EPWM_T::PDMACTL: CHSEL0_1 Position */ +#define EPWM_PDMACTL_CHSEL0_1_Msk (0x1ul << EPWM_PDMACTL_CHSEL0_1_Pos) /*!< EPWM_T::PDMACTL: CHSEL0_1 Mask */ + +#define EPWM_PDMACTL_CHEN2_3_Pos (8) /*!< EPWM_T::PDMACTL: CHEN2_3 Position */ +#define EPWM_PDMACTL_CHEN2_3_Msk (0x1ul << EPWM_PDMACTL_CHEN2_3_Pos) /*!< EPWM_T::PDMACTL: CHEN2_3 Mask */ + +#define EPWM_PDMACTL_CAPMOD2_3_Pos (9) /*!< EPWM_T::PDMACTL: CAPMOD2_3 Position */ +#define EPWM_PDMACTL_CAPMOD2_3_Msk (0x3ul << EPWM_PDMACTL_CAPMOD2_3_Pos) /*!< EPWM_T::PDMACTL: CAPMOD2_3 Mask */ + +#define EPWM_PDMACTL_CAPORD2_3_Pos (11) /*!< EPWM_T::PDMACTL: CAPORD2_3 Position */ +#define EPWM_PDMACTL_CAPORD2_3_Msk (0x1ul << EPWM_PDMACTL_CAPORD2_3_Pos) /*!< EPWM_T::PDMACTL: CAPORD2_3 Mask */ + +#define EPWM_PDMACTL_CHSEL2_3_Pos (12) /*!< EPWM_T::PDMACTL: CHSEL2_3 Position */ +#define EPWM_PDMACTL_CHSEL2_3_Msk (0x1ul << EPWM_PDMACTL_CHSEL2_3_Pos) /*!< EPWM_T::PDMACTL: CHSEL2_3 Mask */ + +#define EPWM_PDMACTL_CHEN4_5_Pos (16) /*!< EPWM_T::PDMACTL: CHEN4_5 Position */ +#define EPWM_PDMACTL_CHEN4_5_Msk (0x1ul << EPWM_PDMACTL_CHEN4_5_Pos) /*!< EPWM_T::PDMACTL: CHEN4_5 Mask */ + +#define EPWM_PDMACTL_CAPMOD4_5_Pos (17) /*!< EPWM_T::PDMACTL: CAPMOD4_5 Position */ +#define EPWM_PDMACTL_CAPMOD4_5_Msk (0x3ul << EPWM_PDMACTL_CAPMOD4_5_Pos) /*!< EPWM_T::PDMACTL: CAPMOD4_5 Mask */ + +#define EPWM_PDMACTL_CAPORD4_5_Pos (19) /*!< EPWM_T::PDMACTL: CAPORD4_5 Position */ +#define EPWM_PDMACTL_CAPORD4_5_Msk (0x1ul << EPWM_PDMACTL_CAPORD4_5_Pos) /*!< EPWM_T::PDMACTL: CAPORD4_5 Mask */ + +#define EPWM_PDMACTL_CHSEL4_5_Pos (20) /*!< EPWM_T::PDMACTL: CHSEL4_5 Position */ +#define EPWM_PDMACTL_CHSEL4_5_Msk (0x1ul << EPWM_PDMACTL_CHSEL4_5_Pos) /*!< EPWM_T::PDMACTL: CHSEL4_5 Mask */ + +#define EPWM_PDMACAP0_1_CAPBUF_Pos (0) /*!< EPWM_T::PDMACAP0_1: CAPBUF Position */ +#define EPWM_PDMACAP0_1_CAPBUF_Msk (0xfffful << EPWM_PDMACAP0_1_CAPBUF_Pos) /*!< EPWM_T::PDMACAP0_1: CAPBUF Mask */ + +#define EPWM_PDMACAP2_3_CAPBUF_Pos (0) /*!< EPWM_T::PDMACAP2_3: CAPBUF Position */ +#define EPWM_PDMACAP2_3_CAPBUF_Msk (0xfffful << EPWM_PDMACAP2_3_CAPBUF_Pos) /*!< EPWM_T::PDMACAP2_3: CAPBUF Mask */ + +#define EPWM_PDMACAP4_5_CAPBUF_Pos (0) /*!< EPWM_T::PDMACAP4_5: CAPBUF Position */ +#define EPWM_PDMACAP4_5_CAPBUF_Msk (0xfffful << EPWM_PDMACAP4_5_CAPBUF_Pos) /*!< EPWM_T::PDMACAP4_5: CAPBUF Mask */ + +#define EPWM_CAPIEN_CAPRIEN0_Pos (0) /*!< EPWM_T::CAPIEN: CAPRIEN0 Position */ +#define EPWM_CAPIEN_CAPRIEN0_Msk (0x1ul << EPWM_CAPIEN_CAPRIEN0_Pos) /*!< EPWM_T::CAPIEN: CAPRIEN0 Mask */ + +#define EPWM_CAPIEN_CAPRIEN1_Pos (1) /*!< EPWM_T::CAPIEN: CAPRIEN1 Position */ +#define EPWM_CAPIEN_CAPRIEN1_Msk (0x1ul << EPWM_CAPIEN_CAPRIEN1_Pos) /*!< EPWM_T::CAPIEN: CAPRIEN1 Mask */ + +#define EPWM_CAPIEN_CAPRIEN2_Pos (2) /*!< EPWM_T::CAPIEN: CAPRIEN2 Position */ +#define EPWM_CAPIEN_CAPRIEN2_Msk (0x1ul << EPWM_CAPIEN_CAPRIEN2_Pos) /*!< EPWM_T::CAPIEN: CAPRIEN2 Mask */ + +#define EPWM_CAPIEN_CAPRIEN3_Pos (3) /*!< EPWM_T::CAPIEN: CAPRIEN3 Position */ +#define EPWM_CAPIEN_CAPRIEN3_Msk (0x1ul << EPWM_CAPIEN_CAPRIEN3_Pos) /*!< EPWM_T::CAPIEN: CAPRIEN3 Mask */ + +#define EPWM_CAPIEN_CAPRIEN4_Pos (4) /*!< EPWM_T::CAPIEN: CAPRIEN4 Position */ +#define EPWM_CAPIEN_CAPRIEN4_Msk (0x1ul << EPWM_CAPIEN_CAPRIEN4_Pos) /*!< EPWM_T::CAPIEN: CAPRIEN4 Mask */ + +#define EPWM_CAPIEN_CAPRIEN5_Pos (5) /*!< EPWM_T::CAPIEN: CAPRIEN5 Position */ +#define EPWM_CAPIEN_CAPRIEN5_Msk (0x1ul << EPWM_CAPIEN_CAPRIEN5_Pos) /*!< EPWM_T::CAPIEN: CAPRIEN5 Mask */ + +#define EPWM_CAPIEN_CAPFIEN0_Pos (8) /*!< EPWM_T::CAPIEN: CAPFIEN0 Position */ +#define EPWM_CAPIEN_CAPFIEN0_Msk (0x1ul << EPWM_CAPIEN_CAPFIEN0_Pos) /*!< EPWM_T::CAPIEN: CAPFIEN0 Mask */ + +#define EPWM_CAPIEN_CAPFIEN1_Pos (9) /*!< EPWM_T::CAPIEN: CAPFIEN1 Position */ +#define EPWM_CAPIEN_CAPFIEN1_Msk (0x1ul << EPWM_CAPIEN_CAPFIEN1_Pos) /*!< EPWM_T::CAPIEN: CAPFIEN1 Mask */ + +#define EPWM_CAPIEN_CAPFIEN2_Pos (10) /*!< EPWM_T::CAPIEN: CAPFIEN2 Position */ +#define EPWM_CAPIEN_CAPFIEN2_Msk (0x1ul << EPWM_CAPIEN_CAPFIEN2_Pos) /*!< EPWM_T::CAPIEN: CAPFIEN2 Mask */ + +#define EPWM_CAPIEN_CAPFIEN3_Pos (11) /*!< EPWM_T::CAPIEN: CAPFIEN3 Position */ +#define EPWM_CAPIEN_CAPFIEN3_Msk (0x1ul << EPWM_CAPIEN_CAPFIEN3_Pos) /*!< EPWM_T::CAPIEN: CAPFIEN3 Mask */ + +#define EPWM_CAPIEN_CAPFIEN4_Pos (12) /*!< EPWM_T::CAPIEN: CAPFIEN4 Position */ +#define EPWM_CAPIEN_CAPFIEN4_Msk (0x1ul << EPWM_CAPIEN_CAPFIEN4_Pos) /*!< EPWM_T::CAPIEN: CAPFIEN4 Mask */ + +#define EPWM_CAPIEN_CAPFIEN5_Pos (13) /*!< EPWM_T::CAPIEN: CAPFIEN5 Position */ +#define EPWM_CAPIEN_CAPFIEN5_Msk (0x1ul << EPWM_CAPIEN_CAPFIEN5_Pos) /*!< EPWM_T::CAPIEN: CAPFIEN5 Mask */ + +#define EPWM_CAPIF_CRLIF0_Pos (0) /*!< EPWM_T::CAPIF: CRLIF0 Position */ +#define EPWM_CAPIF_CRLIF0_Msk (0x1ul << EPWM_CAPIF_CRLIF0_Pos) /*!< EPWM_T::CAPIF: CRLIF0 Mask */ + +#define EPWM_CAPIF_CRLIF1_Pos (1) /*!< EPWM_T::CAPIF: CRLIF1 Position */ +#define EPWM_CAPIF_CRLIF1_Msk (0x1ul << EPWM_CAPIF_CRLIF1_Pos) /*!< EPWM_T::CAPIF: CRLIF1 Mask */ + +#define EPWM_CAPIF_CRLIF2_Pos (2) /*!< EPWM_T::CAPIF: CRLIF2 Position */ +#define EPWM_CAPIF_CRLIF2_Msk (0x1ul << EPWM_CAPIF_CRLIF2_Pos) /*!< EPWM_T::CAPIF: CRLIF2 Mask */ + +#define EPWM_CAPIF_CRLIF3_Pos (3) /*!< EPWM_T::CAPIF: CRLIF3 Position */ +#define EPWM_CAPIF_CRLIF3_Msk (0x1ul << EPWM_CAPIF_CRLIF3_Pos) /*!< EPWM_T::CAPIF: CRLIF3 Mask */ + +#define EPWM_CAPIF_CRLIF4_Pos (4) /*!< EPWM_T::CAPIF: CRLIF4 Position */ +#define EPWM_CAPIF_CRLIF4_Msk (0x1ul << EPWM_CAPIF_CRLIF4_Pos) /*!< EPWM_T::CAPIF: CRLIF4 Mask */ + +#define EPWM_CAPIF_CRLIF5_Pos (5) /*!< EPWM_T::CAPIF: CRLIF5 Position */ +#define EPWM_CAPIF_CRLIF5_Msk (0x1ul << EPWM_CAPIF_CRLIF5_Pos) /*!< EPWM_T::CAPIF: CRLIF5 Mask */ + +#define EPWM_CAPIF_CFLIF0_Pos (8) /*!< EPWM_T::CAPIF: CFLIF0 Position */ +#define EPWM_CAPIF_CFLIF0_Msk (0x1ul << EPWM_CAPIF_CFLIF0_Pos) /*!< EPWM_T::CAPIF: CFLIF0 Mask */ + +#define EPWM_CAPIF_CFLIF1_Pos (9) /*!< EPWM_T::CAPIF: CFLIF1 Position */ +#define EPWM_CAPIF_CFLIF1_Msk (0x1ul << EPWM_CAPIF_CFLIF1_Pos) /*!< EPWM_T::CAPIF: CFLIF1 Mask */ + +#define EPWM_CAPIF_CFLIF2_Pos (10) /*!< EPWM_T::CAPIF: CFLIF2 Position */ +#define EPWM_CAPIF_CFLIF2_Msk (0x1ul << EPWM_CAPIF_CFLIF2_Pos) /*!< EPWM_T::CAPIF: CFLIF2 Mask */ + +#define EPWM_CAPIF_CFLIF3_Pos (11) /*!< EPWM_T::CAPIF: CFLIF3 Position */ +#define EPWM_CAPIF_CFLIF3_Msk (0x1ul << EPWM_CAPIF_CFLIF3_Pos) /*!< EPWM_T::CAPIF: CFLIF3 Mask */ + +#define EPWM_CAPIF_CFLIF4_Pos (12) /*!< EPWM_T::CAPIF: CFLIF4 Position */ +#define EPWM_CAPIF_CFLIF4_Msk (0x1ul << EPWM_CAPIF_CFLIF4_Pos) /*!< EPWM_T::CAPIF: CFLIF4 Mask */ + +#define EPWM_CAPIF_CFLIF5_Pos (13) /*!< EPWM_T::CAPIF: CFLIF5 Position */ +#define EPWM_CAPIF_CFLIF5_Msk (0x1ul << EPWM_CAPIF_CFLIF5_Pos) /*!< EPWM_T::CAPIF: CFLIF5 Mask */ + +#define EPWM_PBUF0_PBUF_Pos (0) /*!< EPWM_T::PBUF0: PBUF Position */ +#define EPWM_PBUF0_PBUF_Msk (0xfffful << EPWM_PBUF0_PBUF_Pos) /*!< EPWM_T::PBUF0: PBUF Mask */ + +#define EPWM_PBUF1_PBUF_Pos (0) /*!< EPWM_T::PBUF1: PBUF Position */ +#define EPWM_PBUF1_PBUF_Msk (0xfffful << EPWM_PBUF1_PBUF_Pos) /*!< EPWM_T::PBUF1: PBUF Mask */ + +#define EPWM_PBUF2_PBUF_Pos (0) /*!< EPWM_T::PBUF2: PBUF Position */ +#define EPWM_PBUF2_PBUF_Msk (0xfffful << EPWM_PBUF2_PBUF_Pos) /*!< EPWM_T::PBUF2: PBUF Mask */ + +#define EPWM_PBUF3_PBUF_Pos (0) /*!< EPWM_T::PBUF3: PBUF Position */ +#define EPWM_PBUF3_PBUF_Msk (0xfffful << EPWM_PBUF3_PBUF_Pos) /*!< EPWM_T::PBUF3: PBUF Mask */ + +#define EPWM_PBUF4_PBUF_Pos (0) /*!< EPWM_T::PBUF4: PBUF Position */ +#define EPWM_PBUF4_PBUF_Msk (0xfffful << EPWM_PBUF4_PBUF_Pos) /*!< EPWM_T::PBUF4: PBUF Mask */ + +#define EPWM_PBUF5_PBUF_Pos (0) /*!< EPWM_T::PBUF5: PBUF Position */ +#define EPWM_PBUF5_PBUF_Msk (0xfffful << EPWM_PBUF5_PBUF_Pos) /*!< EPWM_T::PBUF5: PBUF Mask */ + +#define EPWM_CMPBUF0_CMPBUF_Pos (0) /*!< EPWM_T::CMPBUF0: CMPBUF Position */ +#define EPWM_CMPBUF0_CMPBUF_Msk (0xfffful << EPWM_CMPBUF0_CMPBUF_Pos) /*!< EPWM_T::CMPBUF0: CMPBUF Mask */ + +#define EPWM_CMPBUF1_CMPBUF_Pos (0) /*!< EPWM_T::CMPBUF1: CMPBUF Position */ +#define EPWM_CMPBUF1_CMPBUF_Msk (0xfffful << EPWM_CMPBUF1_CMPBUF_Pos) /*!< EPWM_T::CMPBUF1: CMPBUF Mask */ + +#define EPWM_CMPBUF2_CMPBUF_Pos (0) /*!< EPWM_T::CMPBUF2: CMPBUF Position */ +#define EPWM_CMPBUF2_CMPBUF_Msk (0xfffful << EPWM_CMPBUF2_CMPBUF_Pos) /*!< EPWM_T::CMPBUF2: CMPBUF Mask */ + +#define EPWM_CMPBUF3_CMPBUF_Pos (0) /*!< EPWM_T::CMPBUF3: CMPBUF Position */ +#define EPWM_CMPBUF3_CMPBUF_Msk (0xfffful << EPWM_CMPBUF3_CMPBUF_Pos) /*!< EPWM_T::CMPBUF3: CMPBUF Mask */ + +#define EPWM_CMPBUF4_CMPBUF_Pos (0) /*!< EPWM_T::CMPBUF4: CMPBUF Position */ +#define EPWM_CMPBUF4_CMPBUF_Msk (0xfffful << EPWM_CMPBUF4_CMPBUF_Pos) /*!< EPWM_T::CMPBUF4: CMPBUF Mask */ + +#define EPWM_CMPBUF5_CMPBUF_Pos (0) /*!< EPWM_T::CMPBUF5: CMPBUF Position */ +#define EPWM_CMPBUF5_CMPBUF_Msk (0xfffful << EPWM_CMPBUF5_CMPBUF_Pos) /*!< EPWM_T::CMPBUF5: CMPBUF Mask */ + +#define EPWM_CPSCBUF0_1_CPSCBUF_Pos (0) /*!< EPWM_T::CPSCBUF0_1: CPSCBUF Position */ +#define EPWM_CPSCBUF0_1_CPSCBUF_Msk (0xffful << EPWM_CPSCBUF0_1_CPSCBUF_Pos) /*!< EPWM_T::CPSCBUF0_1: CPSCBUF Mask */ + +#define EPWM_CPSCBUF2_3_CPSCBUF_Pos (0) /*!< EPWM_T::CPSCBUF2_3: CPSCBUF Position */ +#define EPWM_CPSCBUF2_3_CPSCBUF_Msk (0xffful << EPWM_CPSCBUF2_3_CPSCBUF_Pos) /*!< EPWM_T::CPSCBUF2_3: CPSCBUF Mask */ + +#define EPWM_CPSCBUF4_5_CPSCBUF_Pos (0) /*!< EPWM_T::CPSCBUF4_5: CPSCBUF Position */ +#define EPWM_CPSCBUF4_5_CPSCBUF_Msk (0xffful << EPWM_CPSCBUF4_5_CPSCBUF_Pos) /*!< EPWM_T::CPSCBUF4_5: CPSCBUF Mask */ + +#define EPWM_FTCBUF0_1_FTCMPBUF_Pos (0) /*!< EPWM_T::FTCBUF0_1: FTCMPBUF Position */ +#define EPWM_FTCBUF0_1_FTCMPBUF_Msk (0xfffful << EPWM_FTCBUF0_1_FTCMPBUF_Pos) /*!< EPWM_T::FTCBUF0_1: FTCMPBUF Mask */ + +#define EPWM_FTCBUF2_3_FTCMPBUF_Pos (0) /*!< EPWM_T::FTCBUF2_3: FTCMPBUF Position */ +#define EPWM_FTCBUF2_3_FTCMPBUF_Msk (0xfffful << EPWM_FTCBUF2_3_FTCMPBUF_Pos) /*!< EPWM_T::FTCBUF2_3: FTCMPBUF Mask */ + +#define EPWM_FTCBUF4_5_FTCMPBUF_Pos (0) /*!< EPWM_T::FTCBUF4_5: FTCMPBUF Position */ +#define EPWM_FTCBUF4_5_FTCMPBUF_Msk (0xfffful << EPWM_FTCBUF4_5_FTCMPBUF_Pos) /*!< EPWM_T::FTCBUF4_5: FTCMPBUF Mask */ + +#define EPWM_FTCI_FTCMU0_Pos (0) /*!< EPWM_T::FTCI: FTCMU0 Position */ +#define EPWM_FTCI_FTCMU0_Msk (0x1ul << EPWM_FTCI_FTCMU0_Pos) /*!< EPWM_T::FTCI: FTCMU0 Mask */ + +#define EPWM_FTCI_FTCMU2_Pos (1) /*!< EPWM_T::FTCI: FTCMU2 Position */ +#define EPWM_FTCI_FTCMU2_Msk (0x1ul << EPWM_FTCI_FTCMU2_Pos) /*!< EPWM_T::FTCI: FTCMU2 Mask */ + +#define EPWM_FTCI_FTCMU4_Pos (2) /*!< EPWM_T::FTCI: FTCMU4 Position */ +#define EPWM_FTCI_FTCMU4_Msk (0x1ul << EPWM_FTCI_FTCMU4_Pos) /*!< EPWM_T::FTCI: FTCMU4 Mask */ + +#define EPWM_FTCI_FTCMD0_Pos (8) /*!< EPWM_T::FTCI: FTCMD0 Position */ +#define EPWM_FTCI_FTCMD0_Msk (0x1ul << EPWM_FTCI_FTCMD0_Pos) /*!< EPWM_T::FTCI: FTCMD0 Mask */ + +#define EPWM_FTCI_FTCMD2_Pos (9) /*!< EPWM_T::FTCI: FTCMD2 Position */ +#define EPWM_FTCI_FTCMD2_Msk (0x1ul << EPWM_FTCI_FTCMD2_Pos) /*!< EPWM_T::FTCI: FTCMD2 Mask */ + +#define EPWM_FTCI_FTCMD4_Pos (10) /*!< EPWM_T::FTCI: FTCMD4 Position */ +#define EPWM_FTCI_FTCMD4_Msk (0x1ul << EPWM_FTCI_FTCMD4_Pos) /*!< EPWM_T::FTCI: FTCMD4 Mask */ + +/**@}*/ /* EPWM_CONST */ +/**@}*/ /* end of EPWM register group */ +/**@}*/ /* end of REGISTER group */ + +#if defined ( __CC_ARM ) + #pragma no_anon_unions +#endif + +#endif /* __EPWM_REG_H__ */ diff --git a/bsp/nuvoton/libraries/ma35/Device/Nuvoton/MA35D1/Include/gfx_reg.h b/bsp/nuvoton/libraries/ma35/Device/Nuvoton/MA35D1/Include/gfx_reg.h new file mode 100644 index 0000000000..f042e3524b --- /dev/null +++ b/bsp/nuvoton/libraries/ma35/Device/Nuvoton/MA35D1/Include/gfx_reg.h @@ -0,0 +1,382 @@ +/**************************************************************************//** + * @file gfx_reg.h + * @brief GFX register definition header file + * + * SPDX-License-Identifier: Apache-2.0 + * @copyright (C) 2021 Nuvoton Technology Corp. All rights reserved. + *****************************************************************************/ +#ifndef __GFX_REG_H__ +#define __GFX_REG_H__ + +#if defined ( __CC_ARM ) + #pragma anon_unions +#endif + +/** + @addtogroup REGISTER Control Register + @{ +*/ + +/** + @addtogroup GFX 2D Graphic Engine (GFX) + Memory Mapped Structure for GFX Controller +@{ */ + +typedef struct +{ + + + /** + * @var GFX_T::AQHiClockControl + * Offset: 0x00 Clock control register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[0] |CLK3D_DIS |Disable 3D clock + * | | |Software core clock disable signal for core (clk1x) clock. + * | | |When set to 1, the clock is frozen. + * |[1] |CLK2D_DIS |Disable 2D clock + * | | |Software clock disable signal. + * | | |For this core both bits CLK3D_DIS and CLK2D_DIS should be controlled by software. + * | | |The AXI interface clock is the only block not stalled at that point. + * |[8:2] |FSCALE_VAL|Core clock frequency scale value + * | | |If this value is set to 1, the core clock will be 1/64 of clk1x, otherwise clock is fully frequency + * |[9] |FSCALE_CMD_LOAD|Core clock frequency scale value + * | | |When writing a 1 to this bit, it updates the frequency scale factor with the value FSCALE_VAL. + * | | |The bit must be set back to 0 after that. + * | | |If this bit is set and FSCALE_VAL=0 (an invalid combination), the HREADYOUT output signal will get stuck to 0. + * |[10] |DISABLE_RAM_CLOCK_GATING|Disables clock gating for rams. + * |[12] |SOFT_RESET|Soft resets the GFX. + * |[17] |IDLE2_D |2D pipe is idle. + * |[19] |ISOLATE_GPU|Isolate GPU bit + * | | |Used for power on/off sequence. + * @var GFX_T::AQHiIdle + * Offset: 0x04 Idle status register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[0] |IDLE_FE |FE is idle. + * |[1] |IDLE_DE |DE is idle. + * |[2] |IDLE_PE |PE is idle. + * |[31] |AXI_LP |AXI is in low power mode. + * @var GFX_T::AQAxiConfig + * Offset: 0x08 AXI configuration register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[11:8] |AWCACHE |Set AWCACHE[3:0] value + * |[15:12] |ARCACHE |Set ARCACHE[3:0] value + * |[17:16] |AXDOMAIN_SHARED|Configure AxDOMAIN value for shareable request. + * |[19:18] |AXDOMAIN_NON_SHARED|Configure AxDOMAIN value for non-shareable request. + * |[23:20] |AXCACHE_OVERRIDE_SHARED|Configure AxCACHE value for shareable request. + * @var GFX_T::AQAxiStatus + * Offset: 0x0C AXI status register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[3:0] |WR_ERR_ID |Write error ID + * |[7:4] |RD_ERR_ID |Read error ID + * |[8] |DET_WR_ERR|1 = Detect write error + * |[9] |DET_RD_ERR|1 = Detect read error + * @var GFX_T::AQIntrAcknowledge + * Offset: 0x10 Interrupt acknowledge register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[31:0] |INTR_VEC |Interrupt Vector + * | | |Each bit represents a corresponding event being triggered. + * | | |Reading from this register clears the outstanding interrupt. + * | | |For each interrupt event, 0=Clear, 1=Interrupt Active. + * | | |INTR_VEC[31] is AXI_BUS_ERROR, 0 = No Error. + * @var GFX_T::AQIntrEnbl + * Offset: 0x14 Interrupt enable register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[31:0] |INTR_ENBL_VEC|Interrupt enable + * | | |Each bit enables a corresponding event. + * @var GFX_T::GCChipRev + * Offset: 0x24 Revision register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[31:0] |REV |Revision + * @var GFX_T::GCChipDate + * Offset: 0x28 Release date register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[31:0] |DATE |Date (YYYY/MM/DD) + * @var GFX_T::gcTotalCycles + * Offset: 0x78 Total cycles register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[31:0] |CYCLES |Total cycles + * | | |This register is a free running counter. + * | | |It can be reset by writing 0 to it. + * @var GFX_T::gcregHIChipPatchRev + * Offset: 0x98 Patch revision level register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[7:0] |PATCH_REV |Patch revision level for the chip. + * @var GFX_T::gcProductId + * Offset: 0xA8 Product ID register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[3:0] |GRADE_LEVEL|Grade Level + * | | |0 = None-no extra letter on the product name;. + * | | |2 = L-Lite. + * | | |3 = UL-Ultra Lite. + * |[23:4] |NUM |Product Number + * | | |520 for this core. + * |[27:24] |TYPE |Core Type + * | | |0 = GC (2D or 3D Graphics Cores). + * @var GFX_T::gcModulePowerControls + * Offset: 0x100 Control register for module level power + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[0] |ENABLE_MODULE_CLOCK_GATING|Enables module level clock gating. + * |[1] |DISABLE_STALL_MODULE_CLOCK_GATING|Disables module level clock gating for stall condition. + * |[2] |DISABLE_STARVE_MODULE_CLOCK_GATING|Disables module level clock gating for starve/idle condition. + * @var GFX_T::gcregMMUControl + * Offset: 0x18C MMU Control register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[0] |ENABLE |Enable the MMU + * | | |For security reasons, once the MMU is enabled it cannot be disabled anymore. + * | | |1 = enable. + * @var GFX_T::AQMemoryDebug + * Offset: 0x414 Memory debug register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[7:0] |MAX_OUTSTANDING_READS|Limits the total number of outstanding read requests. + * @var GFX_T::AQRegisterTImingControl + * Offset: 0x42C SRAM timing control register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[7:0] |FOR_RF1P |For 1 port RAM + * |[15:8] |FOR_RF2P |For 2 port RAM + * |[17:16] |FAST_RTC |RTC for fast RAMs + * |[19:18] |FAST_WTC |WTC for fast RAMs + * |[20] |POWER_DOW |Power down + * |[21] |DEEP_SLEEP|Deep sleep + * |[22] |LIGHT_SLEEP|Light sleep + * @var GFX_T::AQCmdBufferAddr + * Offset: 0x654 Command buffer base address register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[31:0] |ADDRESS |Base address for the command buffer + * | | |The address must be 64-bit alignment and it is always physical. + * | | |To check the value of the current fetch address use AQFEDebugCurCmdAdr register. + * | | |Since this is a write only register is has no reset value. + * @var GFX_T::AQCmdBufferCtrl + * Offset: 0x658 Command buffer control register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[15:0] |PREFETCH |Prefetch (write only) + * | | |Number of 64-bit words to fetch from the command buffer. + * |[16] |ENABLE |Enable + * | | |Enable the command parser. + * @var GFX_T::AQFEDebugCurCmdAdr + * Offset: 0x664 Command decoder address register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[31:4] |CUR_CMD_ADR|This is the command decoder address + * | | |The address is always physical so the MSB should always be 0. + * | | |Note that with the current MMU all 32 bits are valid. + * | | |It has no reset value. + */ + __IO uint32_t AQHiClockControl; /*!< [0x0000] Clock control register */ + __I uint32_t AQHiIdle; /*!< [0x0004] Idle status register */ + __IO uint32_t AQAxiConfig; /*!< [0x0008] AXI configuration register */ + __I uint32_t AQAxiStatus; /*!< [0x000c] AXI status register */ + __I uint32_t AQIntrAcknowledge; /*!< [0x0010] Interrupt acknowledge register */ + __IO uint32_t AQIntrEnbl; /*!< [0x0014] Interrupt enable register */ + __I uint32_t RESERVE0[3]; + __I uint32_t GCChipRev; /*!< [0x0024] Revision register */ + __I uint32_t GCChipDate; /*!< [0x0028] Release date register */ + __I uint32_t RESERVE1[19]; + __IO uint32_t gcTotalCycles; /*!< [0x0078] Total cycles register */ + __I uint32_t RESERVE2[7]; + __I uint32_t gcregHIChipPatchRev; /*!< [0x0098] Patch revision level register */ + __I uint32_t RESERVE3[3]; + __I uint32_t gcProductId; /*!< [0x00a8] Product ID register */ + __I uint32_t RESERVE4[21]; + __IO uint32_t gcModulePowerControls; /*!< [0x0100] Control register for module level power */ + __I uint32_t RESERVE5[34]; + __O uint32_t gcregMMUControl; /*!< [0x018c] MMU Control register */ + __I uint32_t RESERVE6[161]; + __IO uint32_t AQMemoryDebug; /*!< [0x0414] Memory debug register */ + __I uint32_t RESERVE7[5]; + __IO uint32_t AQRegisterTImingControl; /*!< [0x042c] SRAM timing control register */ + __I uint32_t RESERVE8[137]; + __O uint32_t AQCmdBufferAddr; /*!< [0x0654] Command buffer base address register */ + __IO uint32_t AQCmdBufferCtrl; /*!< [0x0658] Command buffer control register */ + __I uint32_t RESERVE9[2]; + __I uint32_t AQFEDebugCurCmdAdr; /*!< [0x0664] Command decoder address register */ + +} GFX_T; + +/** + @addtogroup GFX_CONST GFX Bit Field Definition + Constant Definitions for GFX Controller +@{ */ + +#define GFX_AQHiClockControl_CLK3D_DIS_Pos (0) /*!< GFX_T::AQHiClockControl: CLK3D_DIS Position*/ +#define GFX_AQHiClockControl_CLK3D_DIS_Msk (0x1ul << GFX_AQHiClockControl_CLK3D_DIS_Pos) /*!< GFX_T::AQHiClockControl: CLK3D_DIS Mask*/ + +#define GFX_AQHiClockControl_CLK2D_DIS_Pos (1) /*!< GFX_T::AQHiClockControl: CLK2D_DIS Position*/ +#define GFX_AQHiClockControl_CLK2D_DIS_Msk (0x1ul << GFX_AQHiClockControl_CLK2D_DIS_Pos) /*!< GFX_T::AQHiClockControl: CLK2D_DIS Mask*/ + +#define GFX_AQHiClockControl_FSCALE_VAL_Pos (2) /*!< GFX_T::AQHiClockControl: FSCALE_VAL Position*/ +#define GFX_AQHiClockControl_FSCALE_VAL_Msk (0x7ful << GFX_AQHiClockControl_FSCALE_VAL_Pos) /*!< GFX_T::AQHiClockControl: FSCALE_VAL Mask*/ + +#define GFX_AQHiClockControl_FSCALE_CMD_LOAD_Pos (9) /*!< GFX_T::AQHiClockControl: FSCALE_CMD_LOAD Position*/ +#define GFX_AQHiClockControl_FSCALE_CMD_LOAD_Msk (0x1ul << GFX_AQHiClockControl_FSCALE_CMD_LOAD_Pos) /*!< GFX_T::AQHiClockControl: FSCALE_CMD_LOAD Mask*/ + +#define GFX_AQHiClockControl_DISABLE_RAM_CLOCK_GATING_Pos (10) /*!< GFX_T::AQHiClockControl: DISABLE_RAM_CLOCK_GATING Position*/ +#define GFX_AQHiClockControl_DISABLE_RAM_CLOCK_GATING_Msk (0x1ul << GFX_AQHiClockControl_DISABLE_RAM_CLOCK_GATING_Pos) /*!< GFX_T::AQHiClockControl: DISABLE_RAM_CLOCK_GATING Mask*/ + +#define GFX_AQHiClockControl_SOFT_RESET_Pos (12) /*!< GFX_T::AQHiClockControl: SOFT_RESET Position*/ +#define GFX_AQHiClockControl_SOFT_RESET_Msk (0x1ul << GFX_AQHiClockControl_SOFT_RESET_Pos) /*!< GFX_T::AQHiClockControl: SOFT_RESET Mask*/ + +#define GFX_AQHiClockControl_IDLE2_D_Pos (17) /*!< GFX_T::AQHiClockControl: IDLE2_D Position*/ +#define GFX_AQHiClockControl_IDLE2_D_Msk (0x1ul << GFX_AQHiClockControl_IDLE2_D_Pos) /*!< GFX_T::AQHiClockControl: IDLE2_D Mask */ + +#define GFX_AQHiClockControl_ISOLATE_GPU_Pos (19) /*!< GFX_T::AQHiClockControl: ISOLATE_GPU Position*/ +#define GFX_AQHiClockControl_ISOLATE_GPU_Msk (0x1ul << GFX_AQHiClockControl_ISOLATE_GPU_Pos) /*!< GFX_T::AQHiClockControl: ISOLATE_GPU Mask*/ + +#define GFX_AQHiIdle_IDLE_FE_Pos (0) /*!< GFX_T::AQHiIdle: IDLE_FE Position */ +#define GFX_AQHiIdle_IDLE_FE_Msk (0x1ul << GFX_AQHiIdle_IDLE_FE_Pos) /*!< GFX_T::AQHiIdle: IDLE_FE Mask */ + +#define GFX_AQHiIdle_IDLE_DE_Pos (1) /*!< GFX_T::AQHiIdle: IDLE_DE Position */ +#define GFX_AQHiIdle_IDLE_DE_Msk (0x1ul << GFX_AQHiIdle_IDLE_DE_Pos) /*!< GFX_T::AQHiIdle: IDLE_DE Mask */ + +#define GFX_AQHiIdle_IDLE_PE_Pos (2) /*!< GFX_T::AQHiIdle: IDLE_PE Position */ +#define GFX_AQHiIdle_IDLE_PE_Msk (0x1ul << GFX_AQHiIdle_IDLE_PE_Pos) /*!< GFX_T::AQHiIdle: IDLE_PE Mask */ + +#define GFX_AQHiIdle_AXI_LP_Pos (31) /*!< GFX_T::AQHiIdle: AXI_LP Position */ +#define GFX_AQHiIdle_AXI_LP_Msk (0x1ul << GFX_AQHiIdle_AXI_LP_Pos) /*!< GFX_T::AQHiIdle: AXI_LP Mask */ + +#define GFX_AQAxiConfig_AWCACHE_Pos (8) /*!< GFX_T::AQAxiConfig: AWCACHE Position */ +#define GFX_AQAxiConfig_AWCACHE_Msk (0xful << GFX_AQAxiConfig_AWCACHE_Pos) /*!< GFX_T::AQAxiConfig: AWCACHE Mask */ + +#define GFX_AQAxiConfig_ARCACHE_Pos (12) /*!< GFX_T::AQAxiConfig: ARCACHE Position */ +#define GFX_AQAxiConfig_ARCACHE_Msk (0xful << GFX_AQAxiConfig_ARCACHE_Pos) /*!< GFX_T::AQAxiConfig: ARCACHE Mask */ + +#define GFX_AQAxiConfig_AXDOMAIN_SHARED_Pos (16) /*!< GFX_T::AQAxiConfig: AXDOMAIN_SHARED Position*/ +#define GFX_AQAxiConfig_AXDOMAIN_SHARED_Msk (0x3ul << GFX_AQAxiConfig_AXDOMAIN_SHARED_Pos) /*!< GFX_T::AQAxiConfig: AXDOMAIN_SHARED Mask*/ + +#define GFX_AQAxiConfig_AXDOMAIN_NON_SHARED_Pos (18) /*!< GFX_T::AQAxiConfig: AXDOMAIN_NON_SHARED Position*/ +#define GFX_AQAxiConfig_AXDOMAIN_NON_SHARED_Msk (0x3ul << GFX_AQAxiConfig_AXDOMAIN_NON_SHARED_Pos) /*!< GFX_T::AQAxiConfig: AXDOMAIN_NON_SHARED Mask*/ + +#define GFX_AQAxiConfig_AXCACHE_OVERRIDE_SHARED_Pos (20) /*!< GFX_T::AQAxiConfig: AXCACHE_OVERRIDE_SHARED Position*/ +#define GFX_AQAxiConfig_AXCACHE_OVERRIDE_SHARED_Msk (0xful << GFX_AQAxiConfig_AXCACHE_OVERRIDE_SHARED_Pos) /*!< GFX_T::AQAxiConfig: AXCACHE_OVERRIDE_SHARED Mask*/ + +#define GFX_AQAxiStatus_WR_ERR_ID_Pos (0) /*!< GFX_T::AQAxiStatus: WR_ERR_ID Position */ +#define GFX_AQAxiStatus_WR_ERR_ID_Msk (0xful << GFX_AQAxiStatus_WR_ERR_ID_Pos) /*!< GFX_T::AQAxiStatus: WR_ERR_ID Mask */ + +#define GFX_AQAxiStatus_RD_ERR_ID_Pos (4) /*!< GFX_T::AQAxiStatus: RD_ERR_ID Position */ +#define GFX_AQAxiStatus_RD_ERR_ID_Msk (0xful << GFX_AQAxiStatus_RD_ERR_ID_Pos) /*!< GFX_T::AQAxiStatus: RD_ERR_ID Mask */ + +#define GFX_AQAxiStatus_DET_WR_ERR_Pos (8) /*!< GFX_T::AQAxiStatus: DET_WR_ERR Position*/ +#define GFX_AQAxiStatus_DET_WR_ERR_Msk (0x1ul << GFX_AQAxiStatus_DET_WR_ERR_Pos) /*!< GFX_T::AQAxiStatus: DET_WR_ERR Mask */ + +#define GFX_AQAxiStatus_DET_RD_ERR_Pos (9) /*!< GFX_T::AQAxiStatus: DET_RD_ERR Position*/ +#define GFX_AQAxiStatus_DET_RD_ERR_Msk (0x1ul << GFX_AQAxiStatus_DET_RD_ERR_Pos) /*!< GFX_T::AQAxiStatus: DET_RD_ERR Mask */ + +#define GFX_AQIntrAcknowledge_INTR_VEC_Pos (0) /*!< GFX_T::AQIntrAcknowledge: INTR_VEC Position*/ +#define GFX_AQIntrAcknowledge_INTR_VEC_Msk (0xfffffffful << GFX_AQIntrAcknowledge_INTR_VEC_Pos) /*!< GFX_T::AQIntrAcknowledge: INTR_VEC Mask*/ + +#define GFX_AQIntrEnbl_INTR_ENBL_VEC_Pos (0) /*!< GFX_T::AQIntrEnbl: INTR_ENBL_VEC Position*/ +#define GFX_AQIntrEnbl_INTR_ENBL_VEC_Msk (0xfffffffful << GFX_AQIntrEnbl_INTR_ENBL_VEC_Pos) /*!< GFX_T::AQIntrEnbl: INTR_ENBL_VEC Mask */ + +#define GFX_GCChipRev_REV_Pos (0) /*!< GFX_T::GCChipRev: REV Position */ +#define GFX_GCChipRev_REV_Msk (0xfffffffful << GFX_GCChipRev_REV_Pos) /*!< GFX_T::GCChipRev: REV Mask */ + +#define GFX_GCChipDate_DATE_Pos (0) /*!< GFX_T::GCChipDate: DATE Position */ +#define GFX_GCChipDate_DATE_Msk (0xfffffffful << GFX_GCChipDate_DATE_Pos) /*!< GFX_T::GCChipDate: DATE Mask */ + +#define GFX_gcTotalCycles_CYCLES_Pos (0) /*!< GFX_T::gcTotalCycles: CYCLES Position */ +#define GFX_gcTotalCycles_CYCLES_Msk (0xfffffffful << GFX_gcTotalCycles_CYCLES_Pos) /*!< GFX_T::gcTotalCycles: CYCLES Mask */ + +#define GFX_gcregHIChipPatchRev_PATCH_REV_Pos (0) /*!< GFX_T::gcregHIChipPatchRev: PATCH_REV Position*/ +#define GFX_gcregHIChipPatchRev_PATCH_REV_Msk (0xfful << GFX_gcregHIChipPatchRev_PATCH_REV_Pos) /*!< GFX_T::gcregHIChipPatchRev: PATCH_REV Mask*/ + +#define GFX_gcProductId_GRADE_LEVEL_Pos (0) /*!< GFX_T::gcProductId: GRADE_LEVEL Position*/ +#define GFX_gcProductId_GRADE_LEVEL_Msk (0xful << GFX_gcProductId_GRADE_LEVEL_Pos) /*!< GFX_T::gcProductId: GRADE_LEVEL Mask */ + +#define GFX_gcProductId_NUM_Pos (4) /*!< GFX_T::gcProductId: NUM Position */ +#define GFX_gcProductId_NUM_Msk (0xffffful << GFX_gcProductId_NUM_Pos) /*!< GFX_T::gcProductId: NUM Mask */ + +#define GFX_gcProductId_TYPE_Pos (24) /*!< GFX_T::gcProductId: TYPE Position */ +#define GFX_gcProductId_TYPE_Msk (0xful << GFX_gcProductId_TYPE_Pos) /*!< GFX_T::gcProductId: TYPE Mask */ + +#define GFX_gcModulePowerControls_ENABLE_MODULE_CLOCK_GATING_Pos (0) /*!< GFX_T::gcModulePowerControls: ENABLE_MODULE_CLOCK_GATING Position*/ +#define GFX_gcModulePowerControls_ENABLE_MODULE_CLOCK_GATING_Msk (0x1ul << GFX_gcModulePowerControls_ENABLE_MODULE_CLOCK_GATING_Pos) /*!< GFX_T::gcModulePowerControls: ENABLE_MODULE_CLOCK_GATING Mask*/ + +#define GFX_gcModulePowerControls_DISABLE_STALL_MODULE_CLOCK_GATING_Pos (1) /*!< GFX_T::gcModulePowerControls: DISABLE_STALL_MODULE_CLOCK_GATING Position*/ +#define GFX_gcModulePowerControls_DISABLE_STALL_MODULE_CLOCK_GATING_Msk (0x1ul << GFX_gcModulePowerControls_DISABLE_STALL_MODULE_CLOCK_GATING_Pos) /*!< GFX_T::gcModulePowerControls: DISABLE_STALL_MODULE_CLOCK_GATING Mask*/ + +#define GFX_gcModulePowerControls_DISABLE_STARVE_MODULE_CLOCK_GATING_Pos (2) /*!< GFX_T::gcModulePowerControls: DISABLE_STARVE_MODULE_CLOCK_GATING Position*/ +#define GFX_gcModulePowerControls_DISABLE_STARVE_MODULE_CLOCK_GATING_Msk (0x1ul << GFX_gcModulePowerControls_DISABLE_STARVE_MODULE_CLOCK_GATING_Pos) /*!< GFX_T::gcModulePowerControls: DISABLE_STARVE_MODULE_CLOCK_GATING Mask*/ + +#define GFX_gcregMMUControl_ENABLE_Pos (0) /*!< GFX_T::gcregMMUControl: ENABLE Position*/ +#define GFX_gcregMMUControl_ENABLE_Msk (0x1ul << GFX_gcregMMUControl_ENABLE_Pos) /*!< GFX_T::gcregMMUControl: ENABLE Mask */ + +#define GFX_AQMemoryDebug_MAX_OUTSTANDING_READS_Pos (0) /*!< GFX_T::AQMemoryDebug: MAX_OUTSTANDING_READS Position*/ +#define GFX_AQMemoryDebug_MAX_OUTSTANDING_READS_Msk (0xfful << GFX_AQMemoryDebug_MAX_OUTSTANDING_READS_Pos) /*!< GFX_T::AQMemoryDebug: MAX_OUTSTANDING_READS Mask*/ + +#define GFX_AQRegisterTImingControl_FOR_RF1P_Pos (0) /*!< GFX_T::AQRegisterTImingControl: FOR_RF1P Position*/ +#define GFX_AQRegisterTImingControl_FOR_RF1P_Msk (0xfful << GFX_AQRegisterTImingControl_FOR_RF1P_Pos) /*!< GFX_T::AQRegisterTImingControl: FOR_RF1P Mask*/ + +#define GFX_AQRegisterTImingControl_FOR_RF2P_Pos (8) /*!< GFX_T::AQRegisterTImingControl: FOR_RF2P Position*/ +#define GFX_AQRegisterTImingControl_FOR_RF2P_Msk (0xfful << GFX_AQRegisterTImingControl_FOR_RF2P_Pos) /*!< GFX_T::AQRegisterTImingControl: FOR_RF2P Mask*/ + +#define GFX_AQRegisterTImingControl_FAST_RTC_Pos (16) /*!< GFX_T::AQRegisterTImingControl: FAST_RTC Position*/ +#define GFX_AQRegisterTImingControl_FAST_RTC_Msk (0x3ul << GFX_AQRegisterTImingControl_FAST_RTC_Pos) /*!< GFX_T::AQRegisterTImingControl: FAST_RTC Mask*/ + +#define GFX_AQRegisterTImingControl_FAST_WTC_Pos (18) /*!< GFX_T::AQRegisterTImingControl: FAST_WTC Position*/ +#define GFX_AQRegisterTImingControl_FAST_WTC_Msk (0x3ul << GFX_AQRegisterTImingControl_FAST_WTC_Pos) /*!< GFX_T::AQRegisterTImingControl: FAST_WTC Mask*/ + +#define GFX_AQRegisterTImingControl_POWER_DOW_Pos (20) /*!< GFX_T::AQRegisterTImingControl: POWER_DOW Position*/ +#define GFX_AQRegisterTImingControl_POWER_DOW_Msk (0x1ul << GFX_AQRegisterTImingControl_POWER_DOW_Pos) /*!< GFX_T::AQRegisterTImingControl: POWER_DOW Mask*/ + +#define GFX_AQRegisterTImingControl_DEEP_SLEEP_Pos (21) /*!< GFX_T::AQRegisterTImingControl: DEEP_SLEEP Position*/ +#define GFX_AQRegisterTImingControl_DEEP_SLEEP_Msk (0x1ul << GFX_AQRegisterTImingControl_DEEP_SLEEP_Pos) /*!< GFX_T::AQRegisterTImingControl: DEEP_SLEEP Mask*/ + +#define GFX_AQRegisterTImingControl_LIGHT_SLEEP_Pos (22) /*!< GFX_T::AQRegisterTImingControl: LIGHT_SLEEP Position*/ +#define GFX_AQRegisterTImingControl_LIGHT_SLEEP_Msk (0x1ul << GFX_AQRegisterTImingControl_LIGHT_SLEEP_Pos) /*!< GFX_T::AQRegisterTImingControl: LIGHT_SLEEP Mask*/ + +#define GFX_AQCmdBufferAddr_ADDRESS_Pos (0) /*!< GFX_T::AQCmdBufferAddr: ADDRESS Position*/ +#define GFX_AQCmdBufferAddr_ADDRESS_Msk (0xfffffffful << GFX_AQCmdBufferAddr_ADDRESS_Pos) /*!< GFX_T::AQCmdBufferAddr: ADDRESS Mask */ + +#define GFX_AQCmdBufferCtrl_PREFETCH_Pos (0) /*!< GFX_T::AQCmdBufferCtrl: PREFETCH Position*/ +#define GFX_AQCmdBufferCtrl_PREFETCH_Msk (0xfffful << GFX_AQCmdBufferCtrl_PREFETCH_Pos) /*!< GFX_T::AQCmdBufferCtrl: PREFETCH Mask */ + +#define GFX_AQCmdBufferCtrl_ENABLE_Pos (16) /*!< GFX_T::AQCmdBufferCtrl: ENABLE Position*/ +#define GFX_AQCmdBufferCtrl_ENABLE_Msk (0x1ul << GFX_AQCmdBufferCtrl_ENABLE_Pos) /*!< GFX_T::AQCmdBufferCtrl: ENABLE Mask */ + +#define GFX_AQFEDebugCurCmdAdr_CUR_CMD_ADR_Pos (4) /*!< GFX_T::AQFEDebugCurCmdAdr: CUR_CMD_ADR Position*/ +#define GFX_AQFEDebugCurCmdAdr_CUR_CMD_ADR_Msk (0xffffffful << GFX_AQFEDebugCurCmdAdr_CUR_CMD_ADR_Pos) /*!< GFX_T::AQFEDebugCurCmdAdr: CUR_CMD_ADR Mask*/ + +/**@}*/ /* GFX_CONST */ +/**@}*/ /* end of GFX register group */ + +/**@}*/ /* end of REGISTER group */ + +#if defined ( __CC_ARM ) + #pragma no_anon_unions +#endif + +#endif /* __GFX_REG_H__ */ diff --git a/bsp/nuvoton/libraries/ma35/Device/Nuvoton/MA35D1/Include/gmac_reg.h b/bsp/nuvoton/libraries/ma35/Device/Nuvoton/MA35D1/Include/gmac_reg.h new file mode 100644 index 0000000000..c307da4635 --- /dev/null +++ b/bsp/nuvoton/libraries/ma35/Device/Nuvoton/MA35D1/Include/gmac_reg.h @@ -0,0 +1,2606 @@ +/**************************************************************************//** + * @file gmac_reg.h + * @brief GMAC register definition header file + * + * SPDX-License-Identifier: Apache-2.0 + * @copyright (C) 2021 Nuvoton Technology Corp. All rights reserved. + *****************************************************************************/ +#ifndef __GAMAC_REG_H__ +#define __GMAC_REG_H__ + +#if defined ( __CC_ARM ) + #pragma anon_unions +#endif + +/** + @addtogroup REGISTER Control Register + @{ +*/ +/** + @addtogroup GMAC Gigabit Ethernet MAC (GMAC) + Memory Mapped Structure for GMAC Controller +@{ */ + +typedef struct +{ + + /** + * @var GMAC_T::MACCFG + * Offset: 0x00 Register 0 (MAC Configuration Register) + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[1:0] |PRELEN |Preamble Length for Transmit Frames + * | | |These bits control the number of preamble bytes that are added to the beginning of every Transmit frame + * | | |The preamble reduction occurs only when the MAC is operating in the full-duplex mode. + * | | |2'b00: 7 bytes of preamble + * | | |2'b01: 5 byte of preamble + * | | |2'b10: 3 bytes of preamble + * | | |2'b11: reserved + * |[2] |RE |Receiver Enable + * | | |When this bit is set, the receiver state machine of the MAC is enabled for receiving frames from the GMII or MII + * | | |When this bit is reset, the MAC receive state machine is disabled after the completion of the reception of the current frame, and does not receive any further frames from the GMII or MII. + * |[3] |TE |Transmitter Enable + * | | |When this bit is set, the transmit state machine of the MAC is enabled for transmission on the GMII or MII + * | | |When this bit is reset, the MAC transmit state machine is disabled after the completion of the transmission of the current frame, and does not transmit any further frames. + * |[4] |DC |Deferral Check + * | | |When this bit is set, the deferral check function is enabled in the MAC + * | | |The MAC issues a Frame Abort status, along with the excessive deferral error bit set in the transmit frame status, when the transmit state machine is deferred for more than 24,288 bit times in the 10 or 100 Mbps mode. + * | | |If the MAC is configured for 1000 Mbps operation or if the Jumbo frame mode is enabled in the 10 or 100 Mbps mode, the threshold for deferral is 155,680 bits times + * | | |Deferral begins when the transmitter is ready to transmit, but it is prevented because of an active carrier sense signal (CRS) on GMII or MII. + * | | |The defer time is not cumulative + * | | |For example, if the transmitter defers for 10,000 bit times because the CRS signal is active and then the CRS signal becomes inactive, the transmitter transmits and collision happens + * | | |Because of collision, the transmitter needs to back off and then defer again after back off completion + * | | |In such a scenario, the deferral timer is reset to 0 and it is restarted + * | | |When this bit is reset, the deferral check function is disabled and the MAC defers until the CRS signal goes inactive + * | | |This bit is applicable only in the half-duplex mode. + * |[6:5] |BL |Back-Off Limit + * | | |The Back-Off limit determines the random integer number (r) of slot time delays (4,096 bit times for 1000 Mbps and 512 bit times for 10/100 Mbps) for which the MAC waits before rescheduling a transmission attempt during retries after a collision + * | | |This bit is applicable only in the half-duplex mode. + * | | |00: k = min (n, 10) + * | | |01: k = min (n, 8) + * | | |10: k = min (n, 4) + * | | |11: k = min (n, 1) + * | | |where n = retransmission attempt + * | | |The random integer r takes the value in the range 0 <= r < kth power of 2 + * |[7] |ACS |Automatic Pad or CRC Stripping + * | | |When this bit is set, the MAC strips the Pad or FCS field on the incoming frames only if the value of the length field is less than 1,536 bytes + * | | |All received frames with length field greater than or equal to 1,536 bytes are passed to the application without stripping the Pad or FCS field. + * | | |When this bit is reset, the MAC passes all incoming frames, without modifying them, to the Host. + * |[8] |LUD |Link Up or Down + * | | |This bit indicates whether the link is up or down during the transmission of configuration in the RGMII interface: + * | | |0: Link Down + * | | |1: Link Up + * |[9] |DR |Disable Retry + * | | |When this bit is set, the MAC attempts only one transmission + * | | |When a collision occurs on the GMII or MII interface, the MAC ignores the current frame transmission and reports a Frame Abort with excessive collision error in the transmit frame status. + * | | |When this bit is reset, the MAC attempts retries based on the settings of the BL field (Bits [6:5]) + * | | |This bit is applicable only in the half-duplex mode. + * |[10] |IPC |Checksum Offload + * | | |When this bit is set, the MAC calculates the 16-bit one's complement of the one's complement sum of all received Ethernet frame payloads + * | | |It also checks whether the IPv4 Header checksum (assumed to be bytes 2526 or 2930 (VLAN-tagged) of the received Ethernet frame) is correct for the received frame and gives the status in the receive status word + * | | |The MAC also appends the 16-bit checksum calculated for the IP header datagram payload (bytes after the IPv4 header) and appends it to the Ethernet frame transferred to the application (when Type 2 COE is deselected). + * | | |When this bit is reset, this function is disabled. + * | | |When Type 2 COE is selected, this bit, when set, enables the IPv4 header checksum checking and IPv4 or IPv6 TCP, UDP, or ICMP payload checksum checking + * | | |When this bit is reset, the COE function in the receiver is disabled and the corresponding PCE and IP HCE status bits are always cleared. + * |[11] |DM |Duplex Mode + * | | |When this bit is set, the MAC operates in the full-duplex mode where it can transmit and receive simultaneously + * |[12] |LM |Loopback Mode + * | | |When this bit is set, the MAC operates in the loopback mode at GMII or MII + * | | |The (G)MII Receive clock input (clk_rx_i) is required for the loopback to work properly, because the Transmit clock is not looped-back internally. + * |[13] |DO |Disable Receive Own + * | | |When this bit is set, the MAC disables the reception of frames when the phy_txen_o is asserted in the half-duplex mode + * | | |When this bit is reset, the MAC receives all packets that are given by the PHY while transmitting + * | | |This bit is not applicable if the MAC is operating in the full-duplex mode + * |[14] |FES |Speed + * | | |This bit selects the speed in the RMII or RGMII interface + * | | |0: 10 Mbps + * | | |1: 100 Mbps + * |[15] |PS |Port Select + * | | |This bit selects the Ethernet line speed: + * | | |0: For 1000 Mbps operations + * | | |1: For 10 or 100 Mbps operations + * | | |In 10 or 100 Mbps operations, this bit, along with FES bit, selects the exact line speed + * | | |The mac_portselect_o signal reflects the value of this bit. + * |[16] |DCRS |Disable Carrier Sense During Transmission + * | | |When set high, this bit makes the MAC transmitter ignore the (G)MII CRS signal during frame transmission in the half-duplex mode + * | | |This request results in no errors generated because of Loss of Carrier or No Carrier during such transmission + * | | |When this bit is low, the MAC transmitter generates such errors because of Carrier Sense and can even abort the transmissions + * |[19:17] |IFG |Inter-Frame Gap + * | | |These bits control the minimum IFG between frames during transmission. + * | | |000: 96 bit times + * | | |001: 88 bit times + * | | |010: 80 bit times + * | | |... + * | | |111: 40 bit times + * | | |In the half-duplex mode, the minimum IFG can be configured only for 64 bit times (IFG = 100) + * | | |Lower values are not considered + * | | |In the 1000-Mbps mode, the minimum IFG supported is 80 bit times (and above). + * |[20] |JE |Jumbo Frame Enable + * | | |When this bit is set, the MAC allows Jumbo frames of 9,018 bytes (9,022 bytes for VLAN tagged frames) without reporting a giant frame error in the receive frame status. + * |[21] |BE |Frame Burst Enable + * | | |When this bit is set, the MAC allows frame bursting during transmission in the GMII half-duplex mode. + * |[22] |JD |Jabber Disable + * | | |When this bit is set, the MAC disables the jabber timer on the transmitter + * | | |The MAC can transfer frames of up to 16,384 bytes + * | | |When this bit is reset, the MAC cuts off the transmitter if the application sends out more than 2,048 bytes of data (10,240 if JE is set high) during transmission. + * |[23] |WD |Watchdog Disable + * | | |When this bit is set, the MAC disables the watchdog timer on the receiver + * | | |The MAC can receive frames of up to 16,384 bytes + * | | |When this bit is reset, the MAC does not allow a receive frame which more than 2,048 bytes (10,240 if JE is set high) or the value programmed in Register 55 (Watchdog Timeout Register). + * | | |The MAC cuts off any bytes received after the watchdog limit number of bytes. + * |[24] |TC |Transmit Configuration in RGMII + * | | |When set, this bit enables the transmission of duplex mode, link speed, and link up or down information to the PHY in the RGMII port + * | | |When this bit is reset, no such information is driven to the PHY + * |[25] |CST |CRC Stripping for Type Frames + * | | |When this bit is set, the last 4 bytes (FCS) of all frames of Ether type (Length/Type field greater than or equal to 1,536) are stripped and dropped before forwarding the frame to the application + * | | |This function is not valid when the IP Checksum Engine (Type 1) is enabled in the MAC receiver + * | | |This function is valid when Type 2 Checksum Offload Engine is enabled. + * |[27] |TWOKPE |IEEE 802.3as Support for 2K Packets + * | | |When set, the MAC considers all frames, with up to 2,000 bytes length, as normal packets + * | | |When Bit 20 (JE) is not set, the MAC considers all received frames of size more than 2 Kbytes as Giant frames + * | | |When this bit is reset and Bit 20 (JE) is not set, the MAC considers all received frames of size more than 1,518 bytes (1,522 bytes for tagged) as Giant frames + * | | |When Bit 20 is set, setting this bit has no effect on Giant Frame status. + * |[30:28] |SARC |Source Address Insertion or Replacement Control + * | | |This field controls the source address insertion or replacement for all transmitted frames + * | | |Bit 30 specifies which MAC Address register (0 or 1) is used for source address insertion or replacement based on the values of Bits [29:28]: + * | | |* 2'b0x: The input signals mti_sa_ctrl_i and ati_sa_ctrl_i control the SA field generation. * 2'b10: + * | | |If Bit 30 is set to 0, the MAC inserts the content of the MAC Address 0 registers (registers 16 and 17) in the SA field of all transmitted frames. + * | | |If Bit 30 is set to 1, the MAC inserts the content of the MAC Address 1 registers (registers 18 and 19) in the SA field of all transmitted frames. + * | | |* 2'b11: + * | | |If Bit 30 is set to 0, the MAC replaces the content of the MAC Address 0 registers (registers 16 and 17) in the SA field of all transmitted frames. + * | | |If Bit 30 is set to 1, the MAC replaces the content of the MAC Address 1 registers (registers 18 and 19) in the SA field of all transmitted frames. + * | | |Note: + * | | |Changes to this field take effect only on the start of a frame + * | | |If you write this register field when a frame is being transmitted, only the subsequent frame can use the updated value, that is, the current frame does not use the updated value + * @var GMAC_T::MACFRMFLTR + * Offset: 0x04 Register 1 (MAC Frame Filter) + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[0] |PR |Promiscuous Mode + * | | |When this bit is set, the Address Filter module passes all incoming frames regardless of its destination or source address + * | | |The SA or DA Filter Fails status bits of the Receive Status Word are always cleared when PR is set. + * |[3] |DAIF |DA Inverse Filtering + * | | |When this bit is set, the Address Check block operates in inverse filtering mode for the DA address comparison for both unicast and multicast frames. + * | | |When reset, normal filtering of frames is performed. + * |[4] |PM |Pass All Multicast + * | | |When set, this bit indicates that all received frames with a multicast destination address (first bit in the destination address field is '1') are passed. + * | | |When reset, filtering of multicast frame depends on HMC bit. + * |[5] |DBF |Disable Broadcast Frames + * | | |When this bit is set, the AFM module filters all incoming broadcast frames + * | | |In addition, it overrides all other filter settings. + * | | |When this bit is reset, the AFM module passes all received broadcast frames. + * |[7:6] |PCF |Pass Control Frames + * | | |These bits control the forwarding of all control frames (including unicast and multicast PAUSE frames). + * | | |00: MAC filters all control frames from reaching the application. + * | | |01: MAC forwards all control frames except PAUSE control frames to application even if they fail the Address filter. + * | | |10: MAC forwards all control frames to application even if they fail the Address Filter. + * | | |11: MAC forwards control frames that pass the Address Filter. + * | | |The following conditions should be true for the PAUSE control frames processing: + * | | |Condition 1: The MAC is in the full-duplex mode and flow control is enabled by setting Bit 2 (RFE) of Register 6 (Flow Control Register) to 1. + * | | |Condition 2: The destination address (DA) of the received frame matches the special multicast address or the MAC Address 0 when Bit 3 (UP) of the Register 6 (Flow Control Register) is set. + * | | |Condition 3: The Type field of the received frame is 0x8808 and the OPCODE field is 0x0001. + * | | |Note: + * | | |This field should be set to 01 only when the Condition 1 is true, that is, the MAC is programmed to operate in the full-duplex mode and the RFE bit is enabled + * | | |Otherwise, the PAUSE frame filtering may be inconsistent + * | | |When Condition 1 is false, the PAUSE frames are considered as generic control frames + * | | |Therefore, to pass all control frames (including PAUSE control frames) when the full-duplex mode and flow control is not enabled, you should set the PCF field to 10 or 11 (as required by the application). + * |[8] |SAIF |SA Inverse Filtering + * | | |When this bit is set, the Address Check block operates in inverse filtering mode for the SA address comparison + * | | |The frames whose SA matches the SA registers are marked as failing the SA Address filter. + * | | |When this bit is reset, frames whose SA does not match the SA registers are marked as failing the SA Address filter. + * |[9] |SAF |Source Address Filter Enable + * | | |When this bit is set, the MAC compares the SA field of the received frames with the values programmed in the enabled SA registers + * | | |If the comparison fails, the MAC drops the frame + * | | |When this bit is reset, the MAC forwards the received frame to the application with updated SAF bit of the Rx Status depending on the SA address comparison. + * | | |Note: According to the IEEE specification, Bit 47 of the SA is reserved and set to 0 + * | | |However, in GMAC, the MAC compares all 48 bits + * | | |The software driver should take this into consideration while programming the MAC address registers for SA. + * |[16] |VTFE |VLAN Tag Filter Enable + * | | |When set, this bit enables the MAC to drop VLAN tagged frames that do not match the VLAN Tag comparison. + * | | |When reset, the MAC forwards all frames irrespective of the match status of the VLAN Tag. + * |[31] |RA |Receive All + * | | |When this bit is set, the MAC Receiver module passes all received frames, irrespective of whether they pass the address filter or not, to the Application + * | | |The result of the SA or DA filtering is updated (pass or fail) in the corresponding bits in the Receive Status Word. + * | | |When this bit is reset, the Receiver module passes only those frames to the Application that pass the SA or DA address filter. + * @var GMAC_T::GMIIADDR + * Offset: 0x10 Register 4 (GMII Address Register) + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[0] |GB |GMII Busy + * | | |This bit should read logic 0 before writing to Register 4 and Register 5 + * | | |During a PHY register access, the software sets this bit to 1'b1 to indicate that a Read or Write access is in progress. + * | | |Register 5 is invalid until this bit is cleared by the MAC + * | | |Therefore, Register 5 (GMII Data) should be kept valid until the MAC clears this bit during a PHY Write operation + * | | |Similarly for a read operation, the contents of Register 5 are not valid until this bit is cleared. + * | | |The subsequent read or write operation should happen only after the previous operation is complete + * | | |Because there is no acknowledgment from the PHY to MAC after a read or write operation is completed, there is no change in the functionality of this bit even when the PHY is not present. + * |[1] |GW |GMII Write + * | | |When set, this bit indicates to the PHY that this is a Write operation using the GMII Data register + * | | |If this bit is not set, it indicates that this is a Read operation, that is, placing the data in the GMII Data register. + * |[5:2] |CR |CSR Clock Range + * | | |The CSR Clock Range selection determines the frequency of the MDC clock according to the CSR clock frequency used in your design + * | | |The suggested range of CSR clock frequency applicable for each value (when Bit[5] = 0) ensures that the MDC clock is approximately between the frequency range 1.0 MHz - 2.5 MHz. + * | | |0000: The frequency of the CSR clock is 60-100 MHz and the MDC clock is CSR clock/42. + * | | |0001: The frequency of the CSR clock is 100-150 MHz and the MDC clock is CSR clock/62. + * | | |0010: The frequency of the CSR clock is 20-35 MHz and the MDC clock is CSR clock/16. + * | | |0011: The frequency of the CSR clock is 35-60 MHz and the MDC clock is CSR clock/26. + * | | |0100: The frequency of the CSR clock is 150-250 MHz and the MDC clock is CSR clock/102. + * | | |0100: The frequency of the CSR clock is 250-300 MHz and the MDC clock is CSR clock/124. + * | | |0110 and 0111: Reserved + * | | |When Bit 5 is set, you can achieve MDC clock of frequency higher than the IEEE 802.3 specified frequency limit of 2.5 MHz and program a clock divider of lower value + * | | |For example, when CSR clock is of 100 MHz frequency and you program these bits as 1010, then the resultant MDC clock is of 12.5 MHz which is outside the limit of IEEE 802.3 specified range. + * | | |Program the following values only if the interfacing chips support faster MDC clocks: + * | | |1000: CSR clock/4 + * | | |1001: CSR clock/6 + * | | |1010: CSR clock/8 + * | | |1011: CSR clock/10 + * | | |1100: CSR clock/12 + * | | |1101: CSR clock/14 + * | | |1110: CSR clock/16 + * | | |1111: CSR clock/18 + * |[10:6] |GR |GMII Register + * | | |These bits select the desired GMII register in the selected PHY device. + * |[15:11] |PA |Physical Layer Address + * | | |This field indicates which of the 32 possible PHY devices are being accessed. + * @var GMAC_T::GMIIDATA + * Offset: 0x14 Register 5 (GMII Data Register) + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[15:0] |GD |GMII Data + * | | |This field contains the 16-bit data value read from the PHY after a Management Read operation or the 16-bit data value to be written to the PHY before a Management Write operation. + * @var GMAC_T::FLOWCTL + * Offset: 0x18 Register 6 (Flow Control Register) + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[0] |FCA_BPA |Flow Control Busy or Backpressure Activate + * | | |This bit initiates a Pause Control frame in the full-duplex mode and activates the backpressure function in the half-duplex mode if the TFE bit is set. + * | | |In the full-duplex mode, this bit should be read as 1'b0 before writing to the Flow Control register + * | | |To initiate a Pause control frame, the Application must set this bit to 1'b1 + * | | |During a transfer of the Control Frame, this bit continues to be set to signify that a frame transmission is in progress + * | | |After the completion of Pause control frame transmission, the MAC resets this bit to 1'b0 + * | | |The Flow Control register should not be written to until this bit is cleared. + * | | |In the half-duplex mode, when this bit is set (and TFE is set), then backpressure is asserted by the MAC + * | | |During backpressure, when the MAC receives a new frame, the transmitter starts sending a JAM pattern resulting in a collision + * | | |This control register bit is logically ORed with the mti_flowctrl_i input signal for the backpressure function + * | | |When the MAC is configured for the full-duplex mode, the BPA is automatically disabled. + * |[1] |TFE |Transmit Flow Control Enable + * | | |In the full-duplex mode, when this bit is set, the MAC enables the flow control operation to transmit Pause frames + * | | |When this bit is reset, the flow control operation in the MAC is disabled, and the MAC does not transmit any Pause frames. + * | | |In half-duplex mode, when this bit is set, the MAC enables the back-pressure operation + * | | |When this bit is reset, the back-pressure feature is disabled. + * |[2] |RFE |Receive Flow Control Enable + * | | |When this bit is set, the MAC decodes the received Pause frame and disables its transmitter for a specified (Pause) time + * | | |When this bit is reset, the decode function of the Pause frame is disabled. + * |[3] |UP |Unicast Pause Frame Detect + * | | |A pause frame is processed when it has the unique multicast address specified in the IEEE Std 802.3 + * | | |When this bit is set, the MAC can also detect Pause frames with unicast address of the station + * | | |This unicast address should be as specified in the MAC Address0 High Register and MAC Address0 Low Register. + * | | |When this bit is reset, the MAC only detects Pause frames with unique multicast address. + * | | |Note: The MAC does not process a Pause frame if the multicast address of received frame is different from the unique multicast address. + * |[5:4] |PLT |Pause Low Threshold + * | | |This field configures the threshold of the PAUSE timer at which the input flow control signal mti_flowctrl_i (or sbd_flowctrl_i) is checked for automatic retransmission of PAUSE Frame. + * | | |The threshold values should be always less than the Pause Time configured in Bits[31:16] + * | | |For example, if PT = 100H (256 slot-times), and PLT = 01, then a second PAUSE frame is automatically transmitted if the mti_flowctrl_i signal is asserted at 228 (256 - 28) slot times after the first PAUSE frame is transmitted. + * | | |The following list provides the threshold values for different values: + * | | |00: The threshold is Pause time minus 4 slot times (PT - 4 slot times). + * | | |01: The threshold is Pause time minus 28 slot times (PT - 28 slot times). + * | | |10: The threshold is Pause time minus 144 slot times (PT - 144 slot times). + * | | |11: The threshold is Pause time minus 256 slot times (PT - 256 slot times). + * | | |The slot time is defined as the time taken to transmit 512 bits (64 bytes) on the GMII or MII interface. + * |[7] |DZPQ |Disable Zero-Quanta Pause + * | | |When this bit is set, it disables the automatic generation of the Zero-Quanta Pause Control frames on the de-assertion of the flow-control signal from the FIFO layer (MTL or external sideband flow control signal sbd_flowctrl_i/mti_flowctrl_i) + * | | |When this bit is reset, normal operation with automatic Zero-Quanta Pause Control frame generation is enabled. + * |[31:16] |PT |Pause Time + * | | |This field holds the value to be used in the Pause Time field in the transmit control frame + * | | |Consecutive writes to this register should be performed only after at least four clock cycles in the destination clock domain. + * @var GMAC_T::VLANTAG + * Offset: 0x1C Register 7 (VLAN Tag Register) + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[15:0] |VL |VLAN Tag Identifier for Receive Frames + * | | |This field contains the 802.1Q VLAN tag to identify the VLAN frames and is compared to the 15th and 16th bytes of the frames being received for VLAN frames + * | | |The following list describes the bits of this field: + * | | |Bits [15:13]: User Priority + * | | |Bit 12: Canonical Format Indicator (CFI) or Drop Eligible Indicator (DEI) + * | | |Bits[11:0]: VLAN tag's VLAN Identifier (VID) field + * | | |When the ETV bit is set, only the VID (Bits[11:0]) is used for comparison + * | | |If VL (VL[11:0] if ETV is set) is all zeros, the MAC does not check the fifteenth and 16th bytes for VLAN tag comparison, and declares all frames with a Type field value of 0x8100 or 0x88a8 as VLAN frames. + * |[16] |ETV |Enable 12-Bit VLAN Tag Comparison + * | | |When this bit is set, a 12-bit VLAN identifier is used for comparing and filtering instead of the complete 16-bit VLAN tag + * | | |Bits [11:0] of VLAN tag are compared with the corresponding field in the received VLAN-tagged frame + * | | |Similarly, when enabled, only 12 bits of the VLAN tag in the received frame are used for hash-based VLAN filtering. + * | | |When this bit is reset, all 16 bits of the 15th and 16th bytes of the received VLAN frame are used for comparison and VLAN hash filtering. + * |[17] |VTIM |VLAN Tag Inverse Match Enable + * | | |When set, this bit enables the VLAN Tag inverse matching + * | | |The frames that do not have matching VLAN Tag are marked as matched. + * | | |When reset, this bit enables the VLAN Tag perfect matching + * | | |The frames with matched VLAN Tag are marked as matched. + * |[18] |ESVL |Enable S-VLAN + * | | |When this bit is set, the MAC transmitter and receiver also consider the S-VLAN (Type = 0x88A8) frames as valid VLAN tagged frames. + * @var GMAC_T::VERSION + * Offset: 0x20 Register 8 (Version Register) + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * @var GMAC_T::REGDEBUG + * Offset: 0x24 Register 9 (Debug Register) + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[0] |RPESTS |MAC GMII or MII Receive Protocol Engine Status + * | | |When high, this bit indicates that the MAC GMII or MII receive protocol engine is actively receiving data and not in IDLE state. + * |[2:1] |RFCFCSTS |MAC Receive Frame Controller FIFO Status + * | | |When high, this field indicates the active state of the small FIFO Read and Write controllers of the MAC Receive Frame Controller Module. + * |[4] |RWCSTS |MTL Rx FIFO Write Controller Active Status + * | | |When high, this bit indicates that the MTL Rx FIFO Write Controller is active and is transferring a received frame to the FIFO. + * |[6:5] |RRCSTS |MTL Rx FIFO Read Controller State + * | | |This field gives the state of the Rx FIFO read Controller: + * | | |00: IDLE state + * | | |01: Reading frame data + * | | |10: Reading frame status (or timestamp) + * | | |11: Flushing the frame data and status + * |[9:8] |RXFSTS |MTL Rx FIFO Fill-level Status + * | | |This field gives the status of the fill-level of the Rx FIFO: + * | | |00: Rx FIFO Empty + * | | |01: Rx FIFO fill level is below the flow-control deactivate threshold + * | | |10: Rx FIFO fill level is above the flow-control activate threshold + * | | |11: Rx FIFO Full + * |[16] |TPESTS |MAC GMII or MII Transmit Protocol Engine Status + * | | |When high, this bit indicates that the MAC GMII or MII transmit protocol engine is actively transmitting data and is not in the IDLE state. + * |[18:17] |TFCSTS |MAC Transmit Frame Controller Status + * | | |This field indicates the state of the MAC Transmit Frame Controller module: + * | | |00: IDLE state + * | | |01: Waiting for Status of previous frame or IFG or back off period to be over + * | | |10: Generating and transmitting a PAUSE control frame (in the full-duplex mode) + * | | |11: Transferring input frame for transmission + * |[19] |TXPAUSED |MAC transmitter in PAUSE + * | | |When high, this bit indicates that the MAC transmitter is in the PAUSE condition (in the full-duplex only mode) and hence does not schedule any frame for transmission. + * |[21:20] |TRCSTS |MTL Tx FIFO Read Controller Status + * | | |This field indicates the state of the Tx FIFO Read Controller: + * | | |00: IDLE state + * | | |01: READ state (transferring data to MAC transmitter) + * | | |10: Waiting for TxStatus from MAC transmitter + * | | |11: Writing the received TxStatus or flushing the Tx FIFO + * |[22] |TWCSTS |MTL Tx FIFO Write Controller Active Status + * | | |When high, this bit indicates that the MTL Tx FIFO Write Controller is active and transferring data to the Tx FIFO. + * |[24] |TXFSTS |MTL Tx FIFO Not Empty Status + * | | |When high, this bit indicates that the MTL Tx FIFO is not empty and some data is left for transmission. + * |[25] |TXSTSFSTS |MTL TxStatus FIFO Full Status + * | | |When high, this bit indicates that the MTL TxStatus FIFO is full + * | | |Therefore, the MTL cannot accept any more frames for transmission. + * @var GMAC_T::PMTCTLSTS + * Offset: 0x2C Register 11 (PMT Control and Status Register) + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[0] |PWRDWN |Power Down + * | | |When set, the MAC receiver drops all received frames until it receives the expected magic packet or wake-up frame + * | | |This bit is then self-cleared and the power-down mode is disabled + * | | |The Software can also clear this bit before the expected magic packet or wake-up frame is received + * | | |The frames, received by the MAC after this bit is cleared, are forwarded to the application + * | | |This bit must only be set when the Magic Packet Enable, Global Unicast, or Wake-Up Frame Enable bit is set high. + * | | |Note: You can gate-off the CSR clock during the power-down mode + * | | |However, when the CSR clock is gated-off, you cannot perform any read or write operations on this register + * | | |Therefore, the Software cannot clear this bit. + * |[1] |MGKPKTEN |Magic Packet Enable + * | | |When set, enables generation of a power management event because of magic packet reception. + * |[5] |MGKPRCVD |Magic Packet Received (read only) + * | | |When set, this bit indicates that the power management event is generated because of the reception of a magic packet + * | | |This bit is cleared by a Read into this register. + * @var GMAC_T::LPICTLSTS + * Offset: 0x30 Register 12 (LPI Control and Status Register) + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[0] |TLPIEN |Transmit LPI Entry (read only) + * | | |When set, this bit indicates that the MAC Transmitter has entered the LPI state because of the setting of the LPIEN bit + * | | |This bit is cleared by a read into this register. + * |[1] |TLPIEX |Transmit LPI Exit (read only) + * | | |When set, this bit indicates that the MAC transmitter has exited the LPI state after the user has cleared the LPIEN bit and the LPI TW Timer has expired + * | | |This bit is cleared by a read into this register. + * |[2] |RLPIEN |Receive LPI Entry (read only) + * | | |When set, this bit indicates that the MAC Receiver has received an LPI pattern and entered the LPI state + * | | |This bit is cleared by a read into this register. + * | | |Note: This bit may not get set if the MAC stops receiving the LPI pattern for a very short duration, such as, less than 3 clock cycles of CSR clock. + * |[3] |RLPIEX |Receive LPI Exit (read only) + * | | |When set, this bit indicates that the MAC Receiver has stopped receiving the LPI pattern on the GMII or MII interface, exited the LPI state, and resumed the normal reception + * | | |This bit is cleared by a read into this register. + * | | |Note: This bit may not get set if the MAC stops receiving the LPI pattern for a very short duration, such as, less than 3 clock cycles of CSR clock. + * |[8] |TLPIST |Transmit LPI State (read only) + * | | |When set, this bit indicates that the MAC is transmitting the LPI pattern on the GMII or MII interface. + * |[9] |RLPIST |Receive LPI State (read only) + * | | |When set, this bit indicates that the MAC is receiving the LPI pattern on the GMII or MII interface. + * |[16] |LPIEN |LPI Enable + * | | |When set, this bit instructs the MAC Transmitter to enter the LPI state + * | | |When reset, this bit instructs the MAC to exit the LPI state and resume normal transmission. + * | | |This bit is cleared when the LPITXA bit is set and the MAC exits the LPI state because of the arrival of a new packet for transmission. + * |[17] |PLS |PHY Link Status + * | | |This bit indicates the link status of the PHY + * | | |The MAC Transmitter asserts the LPI pattern only when the link status is up (okay) at least for the time indicated by the LPI LS TIMER + * | | |When set, the link is considered to be okay (up) and when reset, the link is considered to be down. + * |[18] |PLSEN |PHY Link Status Enable + * | | |This bit enables the link status received on the RGMII receive paths to be used for activating the LPI LS TIMER. + * | | |When set, the MAC uses the link-status bits of Register 54 (RGMII Status Register) and Bit 17 (PLS) for the LPI LS Timer trigger + * | | |When cleared, the MAC ignores the link-status bits of Register 54 and takes only the PLS bit. + * | | |This bit is RO and reserved if you have not selected the RGMII PHY interface. + * |[19] |LPITXA |LPI TX Automate + * | | |This bit controls the behavior of the MAC when it is entering or coming out of the LPI mode on the transmit side + * | | |If the LPITXA and LPIEN bits are set to 1, the MAC enters the LPI mode only after all outstanding frames (in the core) and pending frames (in the application interface) have been transmitted + * | | |The MAC comes out of the LPI mode when the application sends any frame for transmission or the application issues a TX FIFO Flush command + * | | |In addition, the MAC automatically clears the LPIEN bit when it exits the LPI state + * | | |If TX FIFO Flush is set, in Bit 20 of Register 1006 (Operation Mode Register), when the MAC is in the LPI mode, the MAC exits the LPI mode. + * | | |When this bit is 0, the LPIEN bit directly controls behavior of the MAC when it is entering or coming out of the LPI mode. + * @var GMAC_T::LPITMRCTL + * Offset: 0x34 Register 13 (LPI Timers Control Register) + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[15:0] |TWT |LPI TW Timer + * | | |This field specifies the minimum time (in microseconds) for which the MAC waits after it stops transmitting the LPI pattern to the PHY and before it resumes the normal transmission + * | | |The TLPIEX status bit is set after the expiry of this timer. + * |[25:16] |LST |LPI LS Timer + * | | |This field specifies the minimum time (in milliseconds) for which the link status from the PHY should be up (OKAY) before the LPI pattern can be transmitted to the PHY + * | | |The MAC does not transmit the LPI pattern even when the LPIEN bit is set unless the LPI LS Timer reaches the programmed terminal count + * | | |The default value of the LPI LS Timer is 1000 (1 sec) as defined in the IEEE standard. + * @var GMAC_T::INTSTS + * Offset: 0x38 Register 14 (Interrupt Register) + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[0] |RGSMIIIS |RGMII Interrupt Status + * | | |This bit is set because of any change in value of the Link Status of RGMII interface (Bit 3 in Register 54 (RGMII Status Register)) + * | | |This bit is cleared when you perform a read operation on the RGMII Status Register. + * |[3] |PMTIS |PMT Interrupt Status + * | | |This bit is set when a Magic packet or Wake-on-LAN frame is received in the power-down mode (see Bits 5 and 6 in the PMT Control and Status Register) + * | | |This bit is cleared when both Bits[6:5] are cleared because of a read operation to the PMT Control and Status register. + * |[9] |TSIS |Timestamp Interrupt Status + * | | |When the Advanced Timestamp feature is enabled, this bit is set when any of the following conditions is true: + * | | |The system time value equals or exceeds the value specified in the Target Time High and Low registers. + * | | |There is an overflow in the seconds register. + * | | |The Auxiliary snapshot trigger is asserted. + * | | |This bit is cleared on reading Bit 0 of the Register 458 (Timestamp Status Register). + * | | |If default Timestamping is enabled, when set, this bit indicates that the system time value is equal to or exceeds the value specified in the Target Time registers + * | | |In this mode, this bit is cleared after the completion of the read of this bit + * | | |In all other modes, this bit is reserved. + * |[10] |LPIIS |LPI Interrupt Status + * | | |When the Energy Efficient Ethernet feature is enabled, this bit is set for any LPI state entry or exit in the MAC Transmitter or Receiver + * | | |This bit is cleared on reading Bit 0 of Register 12 (LPI Control and Status Register) + * | | |In all other modes, this bit is reserved. + * @var GMAC_T::INTMSK + * Offset: 0x3C Register 15 (Interrupt Mask Register) + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[0] |RGSMIIIM |RGMII or SMII Interrupt Mask + * | | |When set, this bit disables the assertion of the interrupt signal because of the setting of the RGMII or SMII Interrupt Status bit in Register 14 (Interrupt Status Register). + * |[1] |PCSLCHGIM |PCS Link Status Interrupt Mask (read only) + * | | |When set, this bit disables the assertion of the interrupt signal because of the setting of the PCS Link-status changed bit in Register 14 (Interrupt Status Register). + * |[2] |PCSANCIM |PCS AN Completion Interrupt Mask (read only) + * | | |When set, this bit disables the assertion of the interrupt signal because of the setting of PCS Auto-negotiation complete bit in Register 14 (Interrupt Status Register) + * |[3] |PMTIM |PMT Interrupt Mask + * | | |When set, this bit disables the assertion of the interrupt signal because of the setting of PMT Interrupt Status bit in Register 14 (Interrupt Status Register). + * |[9] |TSIM |Timestamp Interrupt Mask + * | | |When set, this bit disables the assertion of the interrupt signal because of the setting of Timestamp Interrupt Status bit in Register 14 (Interrupt Status Register) + * | | |This bit is valid only when IEEE1588 timestamping is enabled + * | | |In all other modes, this bit is reserved. + * |[10] |LPIIM |LPI Interrupt Mask + * | | |When set, this bit disables the assertion of the interrupt signal because of the setting of the LPI Interrupt Status bit in Register 14 (Interrupt Status Register) + * @var GMAC_T::MACADDR0H + * Offset: 0x40 Register 16 (MAC Address0 High Register) + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[15:0] |ADDRHI |MAC Address0 [47:32] + * | | |This field contains the upper 16 bits (47:32) of the first 6-byte MAC address + * | | |The MAC uses this field for filtering the received frames and inserting the MAC address in the Transmit Flow Control (PAUSE) Frames. + * |[31] |AE |Address Enable (read only) + * | | |This bit is always set to 1. + * @var GMAC_T::MACADDR0L + * Offset: 0x44 Register 17 (MAC Address0 Low Register) + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[31:0] |ADDRLO |MAC Address0 [31:0] + * | | |This field contains the lower 32 bits of the first 6-byte MAC address + * | | |This is used by the MAC for filtering the received frames and inserting the MAC address in the Transmit Flow Control (PAUSE) Frames. + * @var GMAC_T::MACADDR1H + * Offset: 0x48 Register 18 (MAC Address1 High Register) + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[15:0] |ADDRHI |MAC Address1 [47:32] + * | | |This field contains the upper 16 bits (47:32) of the second 6-byte MAC address. + * |[29:24] |MBC |Mask Byte Control + * | | |These bits are mask control bits for comparison of each of the MAC Address bytes + * | | |When set high, the MAC does not compare the corresponding byte of received DA or SA with the contents of MAC Address1 registers + * | | |Each bit controls the masking of the bytes as follows: + * | | |Bit 29: Register 18[15:8] + * | | |Bit 28: Register 18[7:0] + * | | |Bit 27: Register 19[31:24] + * | | |... + * | | |Bit 24: Register 19[7:0] + * | | |You can filter a group of addresses (known as group address filtering) by masking one or more bytes of the address. + * |[30] |SA |Source Address + * | | |When this bit is set, the MAC Address1[47:0] is used to compare with the SA fields of the received frame. + * | | |When this bit is reset, the MAC Address1[47:0] is used to compare with the DA fields of the received frame. + * |[31] |AE |Address Enable + * | | |When this bit is set, the address filter module uses the second MAC address for perfect filtering + * | | |When this bit is reset, the address filter module ignores the address for filtering. + * @var GMAC_T::MACADDR1L + * Offset: 0x4C Register 19 (MAC Address1 Low Register) + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[31:0] |ADDRLO |MAC Address1 [31:0] + * | | |This field contains the lower 32 bits of the second 6-byte MAC address + * | | |The content of this field is undefined until loaded by the Application after the initialization process. + * @var GMAC_T::MACADDR2H + * Offset: 0x50 Register 20 (MAC Address2 High Register) + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[15:0] |ADDRHI |MAC Address2 [47:32] + * | | |This field contains the upper 16 bits (47:32) of the third 6-byte MAC address. + * |[29:24] |MBC |Mask Byte Control + * | | |These bits are mask control bits for comparison of each of the MAC Address bytes + * | | |When set high, the MAC does not compare the corresponding byte of received DA or SA with the contents of MAC Address2 registers + * | | |Each bit controls the masking of the bytes as follows: + * | | |Bit 29: Register 18[15:8] + * | | |Bit 28: Register 18[7:0] + * | | |Bit 27: Register 19[31:24] + * | | |... + * | | |Bit 24: Register 19[7:0] + * |[30] |SA |Source Address + * | | |When this bit is set, the MAC Address2[47:0] is used to compare with the SA fields of the received frame. + * | | |When this bit is reset, the MAC Address2[47:0] is used to compare with the DA fields of the received frame. + * |[31] |AE |Address Enable + * | | |When this bit is set, the address filter module uses the third MAC address for perfect filtering + * | | |When this bit is reset, the address filter module ignores the address for filtering. + * @var GMAC_T::MACADDR2L + * Offset: 0x54 Register 21 (MAC Address2 Low Register) + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[31:0] |ADDRLO |MAC Address2 [31:0] + * | | |This field contains the lower 32 bits of the third 6-byte MAC address + * | | |The content of this field is undefined until loaded by the Application after the initialization process. + * @var GMAC_T::MACADDR3H + * Offset: 0x58 Register 22 (MAC Address3 High Register) + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[15:0] |ADDRHI |MAC Address3 [47:32] + * | | |This field contains the upper 16 bits (47:32) of the fourth 6-byte MAC address. + * |[29:24] |MBC |Mask Byte Control + * | | |These bits are mask control bits for comparison of each of the MAC Address bytes + * | | |When set high, the MAC does not compare the corresponding byte of received DA or SA with the contents of MAC Address3 registers + * | | |Each bit controls the masking of the bytes as follows: + * | | |Bit 29: Register 18[15:8] + * | | |Bit 28: Register 18[7:0] + * | | |Bit 27: Register 19[31:24] + * | | |... + * | | |Bit 24: Register 19[7:0] + * |[30] |SA |Source Address + * | | |When this bit is set, the MAC Address3[47:0] is used to compare with the SA fields of the received frame. + * | | |When this bit is reset, the MAC Address3[47:0] is used to compare with the DA fields of the received frame. + * |[31] |AE |Address Enable + * | | |When this bit is set, the address filter module uses the fourth MAC address for perfect filtering + * | | |When this bit is reset, the address filter module ignores the address for filtering. + * @var GMAC_T::MACADDR3L + * Offset: 0x5C Register 23 (MAC Address3 Low Register) + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[31:0] |ADDRLO |MAC Address3 [31:0] + * | | |This field contains the lower 32 bits of the fourth 6-byte MAC address + * | | |The content of this field is undefined until loaded by the Application after the initialization process. + * @var GMAC_T::MACADDR4H + * Offset: 0x60 Register 24 (MAC Address4 High Register) + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[15:0] |ADDRHI |MAC Address4 [47:32] + * | | |This field contains the upper 16 bits (47:32) of the fifth 6-byte MAC address. + * |[29:24] |MBC |Mask Byte Control + * | | |These bits are mask control bits for comparison of each of the MAC Address bytes + * | | |When set high, the MAC does not compare the corresponding byte of received DA or SA with the contents of MAC Address4 registers + * | | |Each bit controls the masking of the bytes as follows: + * | | |Bit 29: Register 18[15:8] + * | | |Bit 28: Register 18[7:0] + * | | |Bit 27: Register 19[31:24] + * | | |... + * | | |Bit 24: Register 19[7:0] + * |[30] |SA |Source Address + * | | |When this bit is set, the MAC Address4[47:0] is used to compare with the SA fields of the received frame. + * | | |When this bit is reset, the MAC Address4[47:0] is used to compare with the DA fields of the received frame. + * |[31] |AE |Address Enable + * | | |When this bit is set, the address filter module uses the fifth MAC address for perfect filtering + * | | |When this bit is reset, the address filter module ignores the address for filtering. + * @var GMAC_T::MACADDR4L + * Offset: 0x64 Register 25 (MAC Address4 Low Register) + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[31:0] |ADDRLO |MAC Address4 [31:0] + * | | |This field contains the lower 32 bits of the fifth 6-byte MAC address + * | | |The content of this field is undefined until loaded by the Application after the initialization process. + * @var GMAC_T::MACADDR5H + * Offset: 0x68 Register 26 (MAC Address5 High Register) + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[15:0] |ADDRHI |MAC Address5 [47:32] + * | | |This field contains the upper 16 bits (47:32) of the sixth 6-byte MAC address. + * |[29:24] |MBC |Mask Byte Control + * | | |These bits are mask control bits for comparison of each of the MAC Address bytes + * | | |When set high, the MAC does not compare the corresponding byte of received DA or SA with the contents of MAC Address5 registers + * | | |Each bit controls the masking of the bytes as follows: + * | | |Bit 29: Register 18[15:8] + * | | |Bit 28: Register 18[7:0] + * | | |Bit 27: Register 19[31:24] + * | | |... + * | | |Bit 24: Register 19[7:0] + * |[30] |SA |Source Address + * | | |When this bit is set, the MAC Address5[47:0] is used to compare with the SA fields of the received frame + * | | |When this bit is reset, the MAC Address5[47:0] is used to compare with the DA fields of the received frame. + * |[31] |AE |Address Enable + * | | |When this bit is set, the address filter module uses the sixth MAC address for perfect filtering + * | | |When this bit is reset, the address filter module ignores the address for filtering. + * @var GMAC_T::MACADDR5L + * Offset: 0x6C Register 27 (MAC Address5 Low Register) + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[31:0] |ADDRLO |MAC Address5 [31:0] + * | | |This field contains the lower 32 bits of the sixth 6-byte MAC address + * | | |The content of this field is undefined until loaded by the Application after the initialization process. + * @var GMAC_T::MACADDR6H + * Offset: 0x70 Register 28 (MAC Address6 High Register) + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[15:0] |ADDRHI |MAC Address6 [47:32] + * | | |This field contains the upper 16 bits (47:32) of the seventh 6-byte MAC address. + * |[29:24] |MBC |Mask Byte Control + * | | |These bits are mask control bits for comparison of each of the MAC Address bytes + * | | |When set high, the MAC does not compare the corresponding byte of received DA or SA with the contents of MAC Address6 registers + * | | |Each bit controls the masking of the bytes as follows: + * | | |Bit 29: Register 18[15:8] + * | | |Bit 28: Register 18[7:0] + * | | |Bit 27: Register 19[31:24] + * | | |... + * | | |Bit 24: Register 19[7:0] + * |[30] |SA |Source Address + * | | |When this bit is set, the MAC Address6[47:0] is used to compare with the SA fields of the received frame + * | | |When this bit is reset, the MAC Address6[47:0] is used to compare with the DA fields of the received frame. + * |[31] |AE |Address Enable + * | | |When this bit is set, the address filter module uses the seventh MAC address for perfect filtering + * | | |When this bit is reset, the address filter module ignores the address for filtering. + * @var GMAC_T::MACADDR6L + * Offset: 0x74 Register 29 (MAC Address6 Low Register) + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[31:0] |ADDRLO |MAC Address6 [31:0] + * | | |This field contains the lower 32 bits of the seventh 6-byte MAC address + * | | |The content of this field is undefined until loaded by the Application after the initialization process. + * @var GMAC_T::MACADDR7H + * Offset: 0x78 Register 30 (MAC Address7 High Register) + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[15:0] |ADDRHI |MAC Address7 [47:32] + * | | |This field contains the upper 16 bits (47:32) of the eighth 6-byte MAC address. + * |[29:24] |MBC |Mask Byte Control + * | | |These bits are mask control bits for comparison of each of the MAC Address bytes + * | | |When set high, the MAC does not compare the corresponding byte of received DA or SA with the contents of MAC Address6 registers + * | | |Each bit controls the masking of the bytes as follows: + * | | |Bit 29: Register 18[15:8] + * | | |Bit 28: Register 18[7:0] + * | | |Bit 27: Register 19[31:24] + * | | |... + * | | |Bit 24: Register 19[7:0] + * |[30] |SA |Source Address + * | | |When this bit is set, the MAC Address7[47:0] is used to compare with the SA fields of the received frame + * | | |When this bit is reset, the MAC Address7[47:0] is used to compare with the DA fields of the received frame. + * |[31] |AE |Address Enable + * | | |When this bit is set, the address filter module uses the eighth MAC address for perfect filtering + * | | |When this bit is reset, the address filter module ignores the address for filtering. + * @var GMAC_T::MACADDR7L + * Offset: 0x7C Register 31 (MAC Address7 Low Register) + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[31:0] |ADDRLO |MAC Address7 [31:0] + * | | |This field contains the lower 32 bits of the eighth 6-byte MAC address + * | | |The content of this field is undefined until loaded by the Application after the initialization process. + * @var GMAC_T::MACADDR8H + * Offset: 0x80 Register 32 (MAC Address8 High Register) + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[15:0] |ADDRHI |MAC Address8 [47:32] + * | | |This field contains the upper 16 bits (47:32) of the ninth 6-byte MAC address. + * |[29:24] |MBC |Mask Byte Control + * | | |These bits are mask control bits for comparison of each of the MAC Address bytes + * | | |When set high, the MAC does not compare the corresponding byte of received DA or SA with the contents of MAC Address8 registers + * | | |Each bit controls the masking of the bytes as follows: + * | | |Bit 29: Register 18[15:8] + * | | |Bit 28: Register 18[7:0] + * | | |Bit 27: Register 19[31:24] + * | | |... + * | | |Bit 24: Register 19[7:0] + * |[30] |SA |Source Address + * | | |When this bit is set, the MAC Address8[47:0] is used to compare with the SA fields of the received frame + * | | |When this bit is reset, the MAC Address8[47:0] is used to compare with the DA fields of the received frame. + * |[31] |AE |Address Enable + * | | |When this bit is set, the address filter module uses the ninth MAC address for perfect filtering + * | | |When this bit is reset, the address filter module ignores the address for filtering. + * @var GMAC_T::MACADDR8L + * Offset: 0x84 Register 33 (MAC Address8 Low Register) + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[31:0] |ADDRLO |MAC Address8 [31:0] + * | | |This field contains the lower 32 bits of the ninth 6-byte MAC address + * | | |The content of this field is undefined until loaded by the Application after the initialization process. + * @var GMAC_T::RGMIICTLSTS + * Offset: 0xD8 Register 54 (RGMII Status Register) + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[0] |LNKMOD |Link Mode + * | | |This bit indicates the current mode of operation of the link: + * | | |1'b0: Half-duplex mode + * | | |1'b1: Full-duplex mode + * |[2:1] |LNKSPEED |Link Speed + * | | |This bit indicates the current speed of the link: + * | | |00: 2.5 MHz + * | | |01: 25 MHz + * | | |10: 125 MHz + * |[3] |LNKSTS |Link Status + * | | |When set, this bit indicates that the link is up between the local PHY and the remote PHY + * | | |When cleared, this bit indicates that the link is down between the local PHY and the remote PHY. + * @var GMAC_T::WDTOUT + * Offset: 0xDC Register 55 (Watchdog Timeout Register) This register controls the watchdog timeout for received frames + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[13:0] |WTO |Watchdog Timeout + * | | |When Bit 16 (PWE) is set and Bit 23 (WD) of Register 0 (MAC Configuration Register) is reset, this field is used as watchdog timeout for a received frame + * | | |If the length of a received frame exceeds the value of this field, such frame is terminated and declared as an error frame. + * | | |Note: When Bit 16 (PWE) is set, the value in this field should be more than 1,522 (0x05F2) + * | | |Otherwise, the IEEE Std 802.3-specified valid tagged frames are declared as error frames and are dropped. + * |[16] |PWE |Programmable Watchdog Enable + * | | |When this bit is set and Bit 23 (WD) of Register 0 (MAC Configuration Register) is reset, the WTO field (Bits[13:0]) is used as watchdog timeout for a received frame + * | | |When this bit is cleared, the watchdog timeout for a received frame is controlled by the setting of Bit 23 (WD) and Bit 20 (JE) in Register 0 (MAC Configuration Register). + * @var GMAC_T::VLANINCL + * Offset: 0x584 Register 353 (VLAN Tag Inclusion or Replacement Register) + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[15:0] |VLT |VLAN Tag for Transmit Frames + * | | |This field contains the value of the VLAN tag to be inserted or replaced + * | | |The value must only be changed when the transmit lines are inactive or during the initialization phase + * | | |Bits[15:13] are the User Priority, Bit 12 is the CFI/DEI, and Bits[11:0] are the VLAN tag's VID field. + * |[17:16] |VLC |VLAN Tag Control in Transmit Frames + * | | |2'b00: No VLAN tag deletion, insertion, or replacement + * | | |2'b01: VLAN tag deletion + * | | |The MAC removes the VLAN type (bytes 13 and 14) and VLAN tag (bytes 15 and 16) of all transmitted frames with VLAN tags. + * | | |2'b10: VLAN tag insertion + * | | |The MAC inserts VLT in bytes 15 and 16 of the frame after inserting the Type value (0x8100/0x88a8) in bytes 13 and 14 + * | | |This operation is performed on all transmitted frames, irrespective of whether they already have a VLAN tag. + * | | |2'b11: VLAN tag replacement + * | | |The MAC replaces VLT in bytes 15 and 16 of all VLAN-type transmitted frames (Bytes 13 and 14 are 0x8100/0x88a8). + * | | |Note: Changes to this field take effect only on the start of a frame + * | | |If you write this register field when a frame is being transmitted, only the subsequent frame can use the updated value, that is, the current frame does not use the updated value + * |[18] |VLP |VLAN Priority Control + * | | |When this bit is set, the control Bits [17:16] are used for VLAN deletion, insertion, or replacement + * | | |When this bit is reset, the mti_vlan_ctrl_i control input is used, and Bits [17:16] are ignored. + * |[19] |CSVL |C-VLAN or S-VLAN + * | | |When this bit is set, S-VLAN type (0x88A8) is inserted or replaced in the 13th and 14th bytes of transmitted frames + * | | |When this bit is reset, C-VLAN type (0x8100) is inserted or replaced in the transmitted frames. + * @var GMAC_T::TSCTL + * Offset: 0x700 Register 448 (Timestamp Control Register) + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[0] |TSENA |Timestamp Enable + * | | |When set, the timestamp is added for the transmit and receive frames + * | | |When disabled, timestamp is not added for the transmit and receive frames and the Timestamp Generator is also suspended + * | | |You need to initialize the Timestamp (system time) after enabling this mode + * | | |On the receive side, the MAC processes the 1588 frames only if this bit is set. + * |[1] |TSCFUPDT |Timestamp Fine or Coarse Update + * | | |When set, this bit indicates that the system times update should be done using the fine update method + * | | |When reset, it indicates the system timestamp update should be done using the Coarse method. + * |[2] |TSINIT |Timestamp Initialize + * | | |When set, the system time is initialized (overwritten) with the value specified in the Register 452 (System Time - Seconds Update Register) and Register 453 (System Time - Nanoseconds Update Register). + * | | |This bit should be read zero before updating it + * | | |This bit is reset when the initialization is complete + * | | |The Timestamp Higher Word register can only be initialized. + * |[3] |TSUPDT |Timestamp Update + * | | |When set, the system time is updated (added or subtracted) with the value specified in Register 452 (System Time - Seconds Update Register) and Register 453 (System Time - Nanoseconds Update Register). + * | | |This bit should be read zero before updating it + * | | |This bit is reset when the update is completed in hardware + * | | |The Timestamp Higher Word register is not updated. + * |[4] |TSTRIG |Timestamp Interrupt Trigger Enable + * | | |When set, the timestamp interrupt is generated when the System Time becomes greater than the value written in the Target Time register + * | | |This bit is reset after the generation of the Timestamp Trigger Interrupt. + * |[5] |TSADDREG |Addend Reg Update + * | | |When set, the content of the Timestamp Addend register is updated in the PTP block for fine correction + * | | |This is cleared when the update is completed + * | | |This register bit should be zero before setting it. + * |[8] |TSENALL |Enable Timestamp for All Frames + * | | |When set, the timestamp snapshot is enabled for all frames received by the MAC. + * |[9] |TSCTRLSSR |Timestamp Digital or Binary Rollover Control + * | | |When set, the Timestamp Low register rolls over after 0x3B9A_C9FF value (that is, 1 nanosecond accuracy) and increments the timestamp (High) seconds + * | | |When reset, the rollover value of sub-second register is 0x7FFF_FFFF + * | | |The sub-second increment has to be programmed correctly depending on the PTP reference clock frequency and the value of this bit. + * |[10] |TSVER2ENA |Enable PTP packet Processing for Version 2 Format + * | | |When set, the PTP packets are processed using the 1588 version 2 format + * | | |Otherwise, the PTP packets are processed using the version 1 format. + * |[11] |TSIPENA |Enable Processing of PTP over Ethernet Frames + * | | |When set, the MAC receiver processes the PTP packets encapsulated directly in the Ethernet frames + * | | |When this bit is clear, the MAC ignores the PTP over Ethernet packets. + * |[12] |TSIPV6ENA |Enable Processing of PTP Frames Sent Over IPv6-UDP + * | | |When set, the MAC receiver processes PTP packets encapsulated in UDP over IPv6 packets + * | | |When this bit is clear, the MAC ignores the PTP transported over UDP-IPv6 packets. + * |[13] |TSIPV4ENA |Enable Processing of PTP Frames Sent over IPv4-UDP + * | | |When set, the MAC receiver processes the PTP packets encapsulated in UDP over IPv4 packets + * | | |When this bit is clear, the MAC ignores the PTP transported over UDP-IPv4 packets + * | | |This bit is set by default. + * |[14] |TSEVNTENA |Enable Timestamp Snapshot for Event Messages + * | | |When set, the timestamp snapshot is taken only for event messages (SYNC, Delay_Req, Pdelay_Req, or Pdelay_Resp) + * | | |When reset, the snapshot is taken for all messages except Announce, Management, and Signaling. + * |[15] |TSMSTRENA |Enable Snapshot for Messages Relevant to Master + * | | |When set, the snapshot is taken only for the messages relevant to the master node + * | | |Otherwise, the snapshot is taken for the messages relevant to the slave node. + * |[17:16] |SNAPTYPSEL|Select PTP packets for Taking Snapshots + * | | |These bits along with Bits 15 and 14 decide the set of PTP packet types for which snapshot needs to be taken. + * |[18] |TSENMACADDR|Enable MAC address for PTP Frame Filtering + * | | |When set, the DA MAC address (that matches any MAC Address register) is used to filter the PTP frames when PTP is directly sent over Ethernet. + * @var GMAC_T::SSECINC + * Offset: 0x704 Register 449 (Sub-Second Increment Register) + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[7:0] |SSINC |Sub-second Increment Value + * | | |The value programmed in this field is accumulated every clock cycle (of clk_ptp_i) with the contents of the sub-second register + * | | |For example, when PTP clock is 50 MHz (period is 20 ns), you should program 20 (0x14) when the System Time-Nanoseconds register has an accuracy of 1 ns (TSCTRLSSR bit is set) + * | | |When TSCTRLSSR is clear, the Nanoseconds register has a resolution of ~0.465ns + * | | |In this case, you should program a value of 43 (0x2B) that is derived by 20ns/0.465. + * @var GMAC_T::STSEC + * Offset: 0x708 Register 450 (System Time - Seconds Register) + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[31:0] |TSS |Timestamp Second + * | | |The value in this field indicates the current value in seconds of the System Time maintained by the MAC. + * @var GMAC_T::STNSEC + * Offset: 0x70C Register 451 (System Time - Nanoseconds Register) + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[30:0] |TSSS |Timestamp Sub Seconds + * | | |The value in this field has the sub second representation of time, with an accuracy of 0.46 ns + * | | |When bit 9 (TSCTRLSSR) is set in Register 448 (Timestamp Control Register), each bit represents 1 ns and the maximum value is 0x3B9A_C9FF, after which it rolls-over to zero. + * @var GMAC_T::STSECU + * Offset: 0x710 Register 452 (System Time - Seconds Update Register) + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[31:0] |TSS |Timestamp Second + * | | |The value in this field indicates the time in seconds to be initialized or added to the system time. + * @var GMAC_T::STNSECU + * Offset: 0x714 Register 453 (System Time - Nanoseconds Update Register) + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[30:0] |TSSS |Timestamp Sub Second + * | | |The value in this field has the sub second representation of time, with an accuracy of 0.46 ns + * | | |When bit 9 (TSCTRLSSR) is set in Register 448 (Timestamp Control Register), each bit represents 1 ns and the programmed value should not exceed 0x3B9A_C9FF. + * |[31] |ADDSUB |Add or subtract time + * | | |When this bit is set, the time value is subtracted with the contents of the update register + * | | |When this bit is reset, the time value is added with the contents of the update register. + * @var GMAC_T::TSADDEND + * Offset: 0x718 Register 454 (Timestamp Addend Register) + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[31:0] |TSAR |Timestamp Addend Register + * | | |This field indicates the 32-bit time value to be added to the Accumulator register to achieve time synchronization. + * @var GMAC_T::TGTSEC + * Offset: 0x71C Register 455 (Target Time Seconds Register) + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[31:0] |TSTR |Target Time Seconds Register + * | | |This register stores the time in seconds + * | | |When the timestamp value matches or exceeds both Target Timestamp registers, then based on Bits [6:5] of Register 459 (PPS Control Register), the MAC starts or stops the PPS signal output and generates an interrupt (if enabled). + * @var GMAC_T::TGTNSEC + * Offset: 0x720 Register 456 (Target Time Nanoseconds Register) + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[30:0] |TTSLO |Target Timestamp Low Register + * | | |This register stores the time in (signed) nanoseconds + * | | |When the value of the timestamp matches the both Target Timestamp registers, then based on the TRGTMODSEL0 field (Bits [6:5]) in Register 459 (PPS Control Register), the MAC starts or stops the PPS signal output and generates an interrupt (if enabled). + * | | |This value should not exceed 0x3B9A_C9FF when TSCTRLSSR is set in the Timestamp control register + * | | |The actual start or stop time of the PPS signal output may have an error margin up to one unit of sub-second increment value. + * |[31] |TRGTBUSY |Target Time Register Busy (read only) + * | | |The MAC sets this bit when the PPSCMD field (Bits[3:0]) in Register 459 (PPS Control Register) is programmed to 010 or 011 + * | | |Programming the PPSCMD field to 010 or 011, instructs the MAC to synchronize the Target Time Registers to the PTP clock domain. + * | | |The MAC clears this bit after synchronizing the Target Time Registers to the PTP clock domain The application must not update the Target Time Registers when this bit is read as 1 + * | | |Otherwise, the synchronization of the previous programmed time gets corrupted + * | | |This bit is reserved when the Enable Flexible Pulse-Per-Second Output feature is not selected. + * @var GMAC_T::STHSEC + * Offset: 0x724 Register 457 (System Time - Higher Word Seconds Register) + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[15:0] |TSHWR |Timestamp Higher Word Register + * | | |This field contains the most significant 16-bits of the timestamp seconds value + * | | |The register is directly written to initialize the value + * | | |This register is incremented when there is an overflow from the 32-bits of the System Time - Seconds register. + * @var GMAC_T::TSSTS + * Offset: 0x728 Register 458 (Timestamp Status Register) + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[0] |TSSOVF |Timestamp Seconds Overflow + * | | |When set, this bit indicates that the seconds value of the timestamp (when supporting version 2 format) has overflowed beyond 32'hFFFF_FFFF. + * |[1] |TSTARGT |Timestamp Target Time Reached + * | | |When set, this bit indicates that the value of system time is greater or equal to the value specified in the Register 455 (Target Time Seconds Register) and Register 456 (Target Time Nanoseconds Register). + * |[2] |AUXTSTRIG |Auxiliary Timestamp Trigger Snapshot + * | | |This bit is set high when the auxiliary snapshot is written to the FIFO + * | | |This bit is valid only if the Enable IEEE 1588 Auxiliary Snapshot feature is selected. + * |[3] |TSTRGTERR |Timestamp Target Time Error + * | | |This bit is set when the target time, being programmed in Target Time Registers, is already elapsed + * | | |This bit is cleared when read by the application. + * |[19:16] |ATSSTN |Auxiliary Timestamp Snapshot Trigger Identifier + * | | |These bits identify the Auxiliary trigger inputs for which the timestamp available in the Auxiliary Snapshot Register is applicable + * | | |When more than one bit is set at the same time, it means that corresponding auxiliary triggers were sampled at the same clock + * | | |These bits are applicable only if the number of Auxiliary snapshots is more than one + * | | |One bit is assigned for each trigger as shown in the following list: + * | | |Bit 16: Auxiliary trigger 0 + * | | |Bit 17: Auxiliary trigger 1 + * | | |Bit 18: Auxiliary trigger 2 + * | | |Bit 19: Auxiliary trigger 3 + * | | |The software can read this register to find the triggers that are set when the timestamp is taken. + * @var GMAC_T::PPSCTL + * Offset: 0x72C Register 459 (PPS Control Register) + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[3:0] |PPSCTL_PPSCMD|PPSCTL0 or PPSCMD0 + * | | |PPSCTL0: PPS0 Output Frequency Control + * | | |This field controls the frequency of the PPS0 output (ptp_pps_o[0]) signal + * | | |The default value of PPSCTL is 0000, and the PPS output is 1 pulse (of width clk_ptp_i) every second + * | | |For other values of PPSCTL, the PPS output becomes a generated clock of following frequencies: + * | | |-0001: The binary rollover is 2 Hz, and the digital rollover is 1 Hz + * | | |-0010: The binary rollover is 4 Hz, and the digital rollover is 2 Hz + * | | |-0011: The binary rollover is 8 Hz, and the digital rollover is 4 Hz + * | | |-0100: The binary rollover is 16 Hz, and the digital rollover is 8 Hz + * | | |-.. + * | | |-1111: The binary rollover is 32.768 kHz, and the digital rollover is 16.384 kHz + * | | |Note: + * | | |In the binary rollover mode, the PPS output (ptp_pps_o) has a duty cycle of 50 percent with these frequencies. + * | | |In the digital rollover mode, the PPS output frequency is an average number + * | | |The actual clock is of different frequency that gets synchronized every second + * | | |For example: + * | | |* When PPSCTL = 0001, the PPS (1 Hz) has a low period of 537 ms and a high period of 463 ms * When PPSCTL = 0010, the PPS (2 Hz) is a sequence of: + * | | |One clock of 50 percent duty cycle and 537 ms period + * | | |Second clock of 463 ms period (268 ms low and 195 ms high) + * | | |* When PPSCTL = 0011, the PPS (4 Hz) is a sequence of: + * | | |Three clocks of 50 percent duty cycle and 268 ms period + * | | |Fourth clock of 195 ms period (134 ms low and 61 ms high) + * | | |This behavior is because of the non-linear toggling of bits in the digital rollover mode in Register 451 (System Time - Nanoseconds Register). + * | | |Flexible PPS0 Output (ptp_pps_o[0]) Control Programming these bits with a non-zero value instructs the MAC to initiate an event + * | | |Once the command is transferred or synchronized to the PTP clock domain, these bits get cleared automatically + * | | |The Software should ensure that these bits are programmed only when they are all-zero + * | | |The following list describes the values of PPSCMD0: + * | | |* 0000: No Command * 0001: START Single Pulse This command generates single pulse rising at the start point defined in Target Time Registers (register 455 and 456) and of a duration defined in the PPS0 PPSWDTH Register + * | | |* 0010: START Pulse Train This command generates the train of pulses rising at the start point defined in the Target Time Registers and of a duration defined in the PPSWDTH Register and repeated at interval defined in the PPS Interval Register + * | | |By default, the PPS pulse train is free-running unless stopped by 'STOP Pulse train at time' or 'STOP Pulse Train immediately' commands + * | | |* 0011: Cancel START + * | | |This command cancels the START Single Pulse and START Pulse Train commands if the system time has not crossed the programmed start time + * | | |* 0100: STOP Pulse train at time This command stops the train of pulses initiated by the START Pulse Train command (PPSCMD = 0010) after the time programmed in the Target Time registers elapses + * | | |* 0101: STOP Pulse Train immediately This command immediately stops the train of pulses initiated by the START Pulse Train command (PPSCMD = 0010) + * | | |* 0110: Cancel STOP Pulse train This command cancels the STOP pulse train at time command if the programmed stop time has not elapsed + * | | |The PPS pulse train becomes free-running on the successful execution of this command + * | | |* 0111-1111: Reserved + * |[4] |PPSEN0 |Flexible PPS Output Mode Enable + * | | |When set low, Bits[3:0] function as PPSCTL (backward compatible) + * | | |When set high, Bits[3:0] function as PPSCMD. + * |[6:5] |TRGTMODSEL0|Target Time Register Mode for PPS0 Output + * | | |This field indicates the Target Time registers (register 455 and 456) mode for PPS0 output signal: + * | | |00: Indicates that the Target Time registers are programmed only for generating the interrupt event. + * | | |01: Reserved + * | | |10: Indicates that the Target Time registers are programmed for generating the interrupt event and starting or stopping the generation of the PPS0 output signal. + * | | |11: Indicates that the Target Time registers are programmed only for starting or stopping the generation of the PPS0 output signal + * | | |No interrupt is asserted. + * @var GMAC_T::PPSINTVL + * Offset: 0x760 Register 472 (PPS0 Interval Register) + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[31:0] |PPSINT |PPS0 Output Signal Interval + * | | |These bits store the interval between the rising edges of PPS0 signal output in terms of units of sub-second increment value + * | | |You need to program one value less than the required interval + * | | |For example, if the PTP reference clock is 50 MHz (period of 20ns), and desired interval between rising edges of PPS0 signal output is 100ns (that is, five units of sub-second increment value), then you should program value 4 (5 -1) in this register. + * @var GMAC_T::PPSWDTH + * Offset: 0x764 Register 473 (PPS0 PPSWDTH Register) + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[31:0] |PPSWIDTH |PPS0 Output Signal PPSWDTH + * | | |These bits store the width between the rising edge and corresponding falling edge of the PPS0 signal output in terms of units of sub-second increment value. + * | | |You need to program one value less than the required interval + * | | |For example, if PTP reference clock is 50 MHz (period of 20ns), and desired width between the rising and corresponding falling edges of PPS0 signal output is 80ns (that is, four units of sub-second increment value), then you should program value 3 (4-1) in this register. + * | | |Note: The value programmed in this register must be lesser than the value programmed in Register 472 (PPS0 Interval Register). + */ + + __IO uint32_t MACCFG; /*!< [0x0000] Register 0 (MAC Configuration Register) */ + __IO uint32_t MACFRMFLTR; /*!< [0x0004] Register 1 (MAC Frame Filter) */ + __I uint32_t RESERVE0[2]; + __IO uint32_t GMIIADDR; /*!< [0x0010] Register 4 (GMII Address Register) */ + __IO uint32_t GMIIDATA; /*!< [0x0014] Register 5 (GMII Data Register) */ + __IO uint32_t FLOWCTL; /*!< [0x0018] Register 6 (Flow Control Register) */ + __IO uint32_t VLANTAG; /*!< [0x001c] Register 7 (VLAN Tag Register) */ + __IO uint32_t VERSION; /*!< [0x0020] Register 8 (Version Register) */ + __I uint32_t REGREGDEBUG; /*!< [0x0024] Register 9 (Debug Register) */ + __I uint32_t RESERVE1[1]; + __IO uint32_t PMTCTLSTS; /*!< [0x002c] Register 11 (PMT Control and Status Register) */ + __IO uint32_t LPICTLSTS; /*!< [0x0030] Register 12 (LPI Control and Status Register) */ + __IO uint32_t LPITMRCTL; /*!< [0x0034] Register 13 (LPI Timers Control Register) */ + __I uint32_t INTSTS; /*!< [0x0038] Register 14 (Interrupt Status Register) */ + __IO uint32_t INTMSK; /*!< [0x003c] Register 15 (Interrupt Mask Register) */ + __IO uint32_t MACADDR0H; /*!< [0x0040] Register 16 (MAC Address0 High Register) */ + __IO uint32_t MACADDR0L; /*!< [0x0044] Register 17 (MAC Address0 Low Register) */ + __IO uint32_t MACADDR1H; /*!< [0x0048] Register 18 (MAC Address1 High Register) */ + __IO uint32_t MACADDR1L; /*!< [0x004c] Register 19 (MAC Address1 Low Register) */ + __IO uint32_t MACADDR2H; /*!< [0x0050] Register 20 (MAC Address2 High Register) */ + __IO uint32_t MACADDR2L; /*!< [0x0054] Register 21 (MAC Address2 Low Register) */ + __IO uint32_t MACADDR3H; /*!< [0x0058] Register 22 (MAC Address3 High Register) */ + __IO uint32_t MACADDR3L; /*!< [0x005c] Register 23 (MAC Address3 Low Register) */ + __IO uint32_t MACADDR4H; /*!< [0x0060] Register 24 (MAC Address4 High Register) */ + __IO uint32_t MACADDR4L; /*!< [0x0064] Register 25 (MAC Address4 Low Register) */ + __IO uint32_t MACADDR5H; /*!< [0x0068] Register 26 (MAC Address5 High Register) */ + __IO uint32_t MACADDR5L; /*!< [0x006c] Register 27 (MAC Address5 Low Register) */ + __IO uint32_t MACADDR6H; /*!< [0x0070] Register 28 (MAC Address6 High Register) */ + __IO uint32_t MACADDR6L; /*!< [0x0074] Register 29 (MAC Address6 Low Register) */ + __IO uint32_t MACADDR7H; /*!< [0x0078] Register 30 (MAC Address7 High Register) */ + __IO uint32_t MACADDR7L; /*!< [0x007c] Register 31 (MAC Address7 Low Register) */ + __IO uint32_t MACADDR8H; /*!< [0x0080] Register 32 (MAC Address8 High Register) */ + __IO uint32_t MACADDR8L; /*!< [0x0084] Register 33 (MAC Address8 Low Register) */ + __I uint32_t RESERVE2[20]; + __I uint32_t RGMIICTLSTS; /*!< [0x00d8] Register 54 (RGMII Status Register) */ + __IO uint32_t WDTOUT; /*!< [0x00dc] Register 55 (Watchdog Timeout Register) */ + __I uint32_t RESERVE3[297]; + __IO uint32_t VLANINCL; /*!< [0x0584] Register 353 (VLAN Tag Inclusion or Replacement Register) */ + __I uint32_t RESERVE4[94]; + __IO uint32_t TSCTL; /*!< [0x0700] Register 448 (Timestamp Control Register) */ + __IO uint32_t SSECINC; /*!< [0x0704] Register 449 (Sub-Second Increment Register) */ + __I uint32_t STSEC; /*!< [0x0708] Register 450 (System Time - Seconds Register) */ + __I uint32_t STNSEC; /*!< [0x070c] Register 451 (System Time - Nanoseconds Register) */ + __IO uint32_t STSECU; /*!< [0x0710] Register 452 (System Time - Seconds Update Register) */ + __IO uint32_t STNSECU; /*!< [0x0714] Register 453 (System Time - Nanoseconds Update Register) */ + __IO uint32_t TSADDEND; /*!< [0x0718] Register 454 (Timestamp Addend Register) */ + __IO uint32_t TGTSEC; /*!< [0x071c] Register 455 (Target Time Seconds Register) */ + __IO uint32_t TGTNSEC; /*!< [0x0720] Register 456 (Target Time Nanoseconds Register) */ + __IO uint32_t STHSEC; /*!< [0x0724] Register 457 (System Time - Higher Word Seconds Register) */ + __I uint32_t TSSTS; /*!< [0x0728] Register 458 (Timestamp Status Register) */ + __IO uint32_t PPSCTL; /*!< [0x072c] Register 459 (PPS Control Register) */ + __I uint32_t RESERVE5[12]; + __IO uint32_t PPSINTVL; /*!< [0x0760] Register 472 (PPS0 Interval Register) */ + __IO uint32_t PPSWDTH; /*!< [0x0764] Register 473 (PPS0 Width Register) */ + +} GMAC_T; + + +/** + @addtogroup GMAC_CONST GMAC Bit Field Definition + Constant Definitions for GMAC Controller +@{ */ + +#define GMAC_MACCFG_PRELEN_Pos (0) /*!< GMAC_T::MACCFG: PRELEN Position */ +#define GMAC_MACCFG_PRELEN_Msk (0x3ul << GMAC_MACCFG_PRELEN_Pos) /*!< GMAC_T::MACCFG: PRELEN Mask */ + +#define GMAC_MACCFG_RE_Pos (2) /*!< GMAC_T::MACCFG: RE Position */ +#define GMAC_MACCFG_RE_Msk (0x1ul << GMAC_MACCFG_RE_Pos) /*!< GMAC_T::MACCFG: RE Mask */ + +#define GMAC_MACCFG_TE_Pos (3) /*!< GMAC_T::MACCFG: TE Position */ +#define GMAC_MACCFG_TE_Msk (0x1ul << GMAC_MACCFG_TE_Pos) /*!< GMAC_T::MACCFG: TE Mask */ + +#define GMAC_MACCFG_DC_Pos (4) /*!< GMAC_T::MACCFG: DC Position */ +#define GMAC_MACCFG_DC_Msk (0x1ul << GMAC_MACCFG_DC_Pos) /*!< GMAC_T::MACCFG: DC Mask */ + +#define GMAC_MACCFG_BL_Pos (5) /*!< GMAC_T::MACCFG: BL Position */ +#define GMAC_MACCFG_BL_Msk (0x3ul << GMAC_MACCFG_BL_Pos) /*!< GMAC_T::MACCFG: BL Mask */ + +#define GMAC_MACCFG_ACS_Pos (7) /*!< GMAC_T::MACCFG: ACS Position */ +#define GMAC_MACCFG_ACS_Msk (0x1ul << GMAC_MACCFG_ACS_Pos) /*!< GMAC_T::MACCFG: ACS Mask */ + +#define GMAC_MACCFG_LUD_Pos (8) /*!< GMAC_T::MACCFG: LUD Position */ +#define GMAC_MACCFG_LUD_Msk (0x1ul << GMAC_MACCFG_LUD_Pos) /*!< GMAC_T::MACCFG: LUD Mask */ + +#define GMAC_MACCFG_DR_Pos (9) /*!< GMAC_T::MACCFG: DR Position */ +#define GMAC_MACCFG_DR_Msk (0x1ul << GMAC_MACCFG_DR_Pos) /*!< GMAC_T::MACCFG: DR Mask */ + +#define GMAC_MACCFG_IPC_Pos (10) /*!< GMAC_T::MACCFG: IPC Position */ +#define GMAC_MACCFG_IPC_Msk (0x1ul << GMAC_MACCFG_IPC_Pos) /*!< GMAC_T::MACCFG: IPC Mask */ + +#define GMAC_MACCFG_DM_Pos (11) /*!< GMAC_T::MACCFG: DM Position */ +#define GMAC_MACCFG_DM_Msk (0x1ul << GMAC_MACCFG_DM_Pos) /*!< GMAC_T::MACCFG: DM Mask */ + +#define GMAC_MACCFG_LM_Pos (12) /*!< GMAC_T::MACCFG: LM Position */ +#define GMAC_MACCFG_LM_Msk (0x1ul << GMAC_MACCFG_LM_Pos) /*!< GMAC_T::MACCFG: LM Mask */ + +#define GMAC_MACCFG_DO_Pos (13) /*!< GMAC_T::MACCFG: DO Position */ +#define GMAC_MACCFG_DO_Msk (0x1ul << GMAC_MACCFG_DO_Pos) /*!< GMAC_T::MACCFG: DO Mask */ + +#define GMAC_MACCFG_FES_Pos (14) /*!< GMAC_T::MACCFG: FES Position */ +#define GMAC_MACCFG_FES_Msk (0x1ul << GMAC_MACCFG_FES_Pos) /*!< GMAC_T::MACCFG: FES Mask */ + +#define GMAC_MACCFG_PS_Pos (15) /*!< GMAC_T::MACCFG: PS Position */ +#define GMAC_MACCFG_PS_Msk (0x1ul << GMAC_MACCFG_PS_Pos) /*!< GMAC_T::MACCFG: PS Mask */ + +#define GMAC_MACCFG_DCRS_Pos (16) /*!< GMAC_T::MACCFG: DCRS Position */ +#define GMAC_MACCFG_DCRS_Msk (0x1ul << GMAC_MACCFG_DCRS_Pos) /*!< GMAC_T::MACCFG: DCRS Mask */ + +#define GMAC_MACCFG_IFG_Pos (17) /*!< GMAC_T::MACCFG: IFG Position */ +#define GMAC_MACCFG_IFG_Msk (0x7ul << GMAC_MACCFG_IFG_Pos) /*!< GMAC_T::MACCFG: IFG Mask */ + +#define GMAC_MACCFG_JE_Pos (20) /*!< GMAC_T::MACCFG: JE Position */ +#define GMAC_MACCFG_JE_Msk (0x1ul << GMAC_MACCFG_JE_Pos) /*!< GMAC_T::MACCFG: JE Mask */ + +#define GMAC_MACCFG_BE_Pos (21) /*!< GMAC_T::MACCFG: BE Position */ +#define GMAC_MACCFG_BE_Msk (0x1ul << GMAC_MACCFG_BE_Pos) /*!< GMAC_T::MACCFG: BE Mask */ + +#define GMAC_MACCFG_JD_Pos (22) /*!< GMAC_T::MACCFG: JD Position */ +#define GMAC_MACCFG_JD_Msk (0x1ul << GMAC_MACCFG_JD_Pos) /*!< GMAC_T::MACCFG: JD Mask */ + +#define GMAC_MACCFG_WD_Pos (23) /*!< GMAC_T::MACCFG: WD Position */ +#define GMAC_MACCFG_WD_Msk (0x1ul << GMAC_MACCFG_WD_Pos) /*!< GMAC_T::MACCFG: WD Mask */ + +#define GMAC_MACCFG_TC_Pos (24) /*!< GMAC_T::MACCFG: TC Position */ +#define GMAC_MACCFG_TC_Msk (0x1ul << GMAC_MACCFG_TC_Pos) /*!< GMAC_T::MACCFG: TC Mask */ + +#define GMAC_MACCFG_CST_Pos (25) /*!< GMAC_T::MACCFG: CST Position */ +#define GMAC_MACCFG_CST_Msk (0x1ul << GMAC_MACCFG_CST_Pos) /*!< GMAC_T::MACCFG: CST Mask */ + +#define GMAC_MACCFG_TWOKPE_Pos (27) /*!< GMAC_T::MACCFG: TWOKPE Position */ +#define GMAC_MACCFG_TWOKPE_Msk (0x1ul << GMAC_MACCFG_TWOKPE_Pos) /*!< GMAC_T::MACCFG: TWOKPE Mask */ + +#define GMAC_MACCFG_SARC_Pos (28) /*!< GMAC_T::MACCFG: SARC Position */ +#define GMAC_MACCFG_SARC_Msk (0x7ul << GMAC_MACCFG_SARC_Pos) /*!< GMAC_T::MACCFG: SARC Mask */ + +#define GMAC_MACFRMFLTR_PR_Pos (0) /*!< GMAC_T::MACFRMFLTR: PR Position */ +#define GMAC_MACFRMFLTR_PR_Msk (0x1ul << GMAC_MACFRMFLTR_PR_Pos) /*!< GMAC_T::MACFRMFLTR: PR Mask */ + +#define GMAC_MACFRMFLTR_DAIF_Pos (3) /*!< GMAC_T::MACFRMFLTR: DAIF Position */ +#define GMAC_MACFRMFLTR_DAIF_Msk (0x1ul << GMAC_MACFRMFLTR_DAIF_Pos) /*!< GMAC_T::MACFRMFLTR: DAIF Mask */ + +#define GMAC_MACFRMFLTR_PM_Pos (4) /*!< GMAC_T::MACFRMFLTR: PM Position */ +#define GMAC_MACFRMFLTR_PM_Msk (0x1ul << GMAC_MACFRMFLTR_PM_Pos) /*!< GMAC_T::MACFRMFLTR: PM Mask */ + +#define GMAC_MACFRMFLTR_DBF_Pos (5) /*!< GMAC_T::MACFRMFLTR: DBF Position */ +#define GMAC_MACFRMFLTR_DBF_Msk (0x1ul << GMAC_MACFRMFLTR_DBF_Pos) /*!< GMAC_T::MACFRMFLTR: DBF Mask */ + +#define GMAC_MACFRMFLTR_PCF_Pos (6) /*!< GMAC_T::MACFRMFLTR: PCF Position */ +#define GMAC_MACFRMFLTR_PCF_Msk (0x3ul << GMAC_MACFRMFLTR_PCF_Pos) /*!< GMAC_T::MACFRMFLTR: PCF Mask */ + +#define GMAC_MACFRMFLTR_SAIF_Pos (8) /*!< GMAC_T::MACFRMFLTR: SAIF Position */ +#define GMAC_MACFRMFLTR_SAIF_Msk (0x1ul << GMAC_MACFRMFLTR_SAIF_Pos) /*!< GMAC_T::MACFRMFLTR: SAIF Mask */ + +#define GMAC_MACFRMFLTR_SAF_Pos (9) /*!< GMAC_T::MACFRMFLTR: SAF Position */ +#define GMAC_MACFRMFLTR_SAF_Msk (0x1ul << GMAC_MACFRMFLTR_SAF_Pos) /*!< GMAC_T::MACFRMFLTR: SAF Mask */ + +#define GMAC_MACFRMFLTR_VTFE_Pos (16) /*!< GMAC_T::MACFRMFLTR: VTFE Position */ +#define GMAC_MACFRMFLTR_VTFE_Msk (0x1ul << GMAC_MACFRMFLTR_VTFE_Pos) /*!< GMAC_T::MACFRMFLTR: VTFE Mask */ + +#define GMAC_MACFRMFLTR_RA_Pos (31) /*!< GMAC_T::MACFRMFLTR: RA Position */ +#define GMAC_MACFRMFLTR_RA_Msk (0x1ul << GMAC_MACFRMFLTR_RA_Pos) /*!< GMAC_T::MACFRMFLTR: RA Mask */ + +#define GMAC_GMIIADDR_GB_Pos (0) /*!< GMAC_T::GMIIADDR: GB Position */ +#define GMAC_GMIIADDR_GB_Msk (0x1ul << GMAC_GMIIADDR_GB_Pos) /*!< GMAC_T::GMIIADDR: GB Mask */ + +#define GMAC_GMIIADDR_GW_Pos (1) /*!< GMAC_T::GMIIADDR: GW Position */ +#define GMAC_GMIIADDR_GW_Msk (0x1ul << GMAC_GMIIADDR_GW_Pos) /*!< GMAC_T::GMIIADDR: GW Mask */ + +#define GMAC_GMIIADDR_CR_Pos (2) /*!< GMAC_T::GMIIADDR: CR Position */ +#define GMAC_GMIIADDR_CR_Msk (0xful << GMAC_GMIIADDR_CR_Pos) /*!< GMAC_T::GMIIADDR: CR Mask */ + +#define GMAC_GMIIADDR_GR_Pos (6) /*!< GMAC_T::GMIIADDR: GR Position */ +#define GMAC_GMIIADDR_GR_Msk (0x1ful << GMAC_GMIIADDR_GR_Pos) /*!< GMAC_T::GMIIADDR: GR Mask */ + +#define GMAC_GMIIADDR_PA_Pos (11) /*!< GMAC_T::GMIIADDR: PA Position */ +#define GMAC_GMIIADDR_PA_Msk (0x1ful << GMAC_GMIIADDR_PA_Pos) /*!< GMAC_T::GMIIADDR: PA Mask */ + +#define GMAC_GMII_Date_GD_Pos (0) /*!< GMAC_T::GMII_Date: GD Position */ +#define GMAC_GMII_Date_GD_Msk (0xfffful << GMAC_GMII_Date_GD_Pos) /*!< GMAC_T::GMII_Date: GD Mask */ + +#define GMAC_FLOWCTL_FCA_BPA_Pos (0) /*!< GMAC_T::FLOWCTL: FCA_BPA Position */ +#define GMAC_FLOWCTL_FCA_BPA_Msk (0x1ul << GMAC_FLOWCTL_FCA_BPA_Pos) /*!< GMAC_T::FLOWCTL: FCA_BPA Mask */ + +#define GMAC_FLOWCTL_TFE_Pos (1) /*!< GMAC_T::FLOWCTL: TFE Position */ +#define GMAC_FLOWCTL_TFE_Msk (0x1ul << GMAC_FLOWCTL_TFE_Pos) /*!< GMAC_T::FLOWCTL: TFE Mask */ + +#define GMAC_FLOWCTL_RFE_Pos (2) /*!< GMAC_T::FLOWCTL: RFE Position */ +#define GMAC_FLOWCTL_RFE_Msk (0x1ul << GMAC_FLOWCTL_RFE_Pos) /*!< GMAC_T::FLOWCTL: RFE Mask */ + +#define GMAC_FLOWCTL_UP_Pos (3) /*!< GMAC_T::FLOWCTL: UP Position */ +#define GMAC_FLOWCTL_UP_Msk (0x1ul << GMAC_FLOWCTL_UP_Pos) /*!< GMAC_T::FLOWCTL: UP Mask */ + +#define GMAC_FLOWCTL_PLT_Pos (4) /*!< GMAC_T::FLOWCTL: PLT Position */ +#define GMAC_FLOWCTL_PLT_Msk (0x3ul << GMAC_FLOWCTL_PLT_Pos) /*!< GMAC_T::FLOWCTL: PLT Mask */ + +#define GMAC_FLOWCTL_DZPQ_Pos (7) /*!< GMAC_T::FLOWCTL: DZPQ Position */ +#define GMAC_FLOWCTL_DZPQ_Msk (0x1ul << GMAC_FLOWCTL_DZPQ_Pos) /*!< GMAC_T::FLOWCTL: DZPQ Mask */ + +#define GMAC_FLOWCTL_PT_Pos (16) /*!< GMAC_T::FLOWCTL: PT Position */ +#define GMAC_FLOWCTL_PT_Msk (0xfffful << GMAC_FLOWCTL_PT_Pos) /*!< GMAC_T::FLOWCTL: PT Mask */ + +#define GMAC_VLANTAG_VL_Pos (0) /*!< GMAC_T::VLANTAG: VL Position */ +#define GMAC_VLANTAG_VL_Msk (0xfffful << GMAC_VLANTAG_VL_Pos) /*!< GMAC_T::VLANTAG: VL Mask */ + +#define GMAC_VLANTAG_ETV_Pos (16) /*!< GMAC_T::VLANTAG: ETV Position */ +#define GMAC_VLANTAG_ETV_Msk (0x1ul << GMAC_VLANTAG_ETV_Pos) /*!< GMAC_T::VLANTAG: ETV Mask */ + +#define GMAC_VLANTAG_VTIM_Pos (17) /*!< GMAC_T::VLANTAG: VTIM Position */ +#define GMAC_VLANTAG_VTIM_Msk (0x1ul << GMAC_VLANTAG_VTIM_Pos) /*!< GMAC_T::VLANTAG: VTIM Mask */ + +#define GMAC_VLANTAG_ESVL_Pos (18) /*!< GMAC_T::VLANTAG: ESVL Position */ +#define GMAC_VLANTAG_ESVL_Msk (0x1ul << GMAC_VLANTAG_ESVL_Pos) /*!< GMAC_T::VLANTAG: ESVL Mask */ + +#define GMAC_REGREGDEBUG_RPESTS_Pos (0) /*!< GMAC_T::REGDEBUG: RPESTS Position */ +#define GMAC_REGDEBUG_RPESTS_Msk (0x1ul << GMAC_REGDEBUG_RPESTS_Pos) /*!< GMAC_T::REGDEBUG: RPESTS Mask */ + +#define GMAC_REGDEBUG_RFCFCSTS_Pos (1) /*!< GMAC_T::REGDEBUG: RFCFCSTS Position */ +#define GMAC_REGDEBUG_RFCFCSTS_Msk (0x3ul << GMAC_REGDEBUG_RFCFCSTS_Pos) /*!< GMAC_T::REGDEBUG: RFCFCSTS Mask */ + +#define GMAC_REGDEBUG_RWCSTS_Pos (4) /*!< GMAC_T::REGDEBUG: RWCSTS Position */ +#define GMAC_REGDEBUG_RWCSTS_Msk (0x1ul << GMAC_REGDEBUG_RWCSTS_Pos) /*!< GMAC_T::REGDEBUG: RWCSTS Mask */ + +#define GMAC_REGDEBUG_RRCSTS_Pos (5) /*!< GMAC_T::REGDEBUG: RRCSTS Position */ +#define GMAC_REGDEBUG_RRCSTS_Msk (0x3ul << GMAC_REGDEBUG_RRCSTS_Pos) /*!< GMAC_T::REGDEBUG: RRCSTS Mask */ + +#define GMAC_REGDEBUG_RXFSTS_Pos (8) /*!< GMAC_T::REGDEBUG: RXFSTS Position */ +#define GMAC_REGDEBUG_RXFSTS_Msk (0x3ul << GMAC_REGDEBUG_RXFSTS_Pos) /*!< GMAC_T::REGDEBUG: RXFSTS Mask */ + +#define GMAC_REGDEBUG_TPESTS_Pos (16) /*!< GMAC_T::REGDEBUG: TPESTS Position */ +#define GMAC_REGDEBUG_TPESTS_Msk (0x1ul << GMAC_REGDEBUG_TPESTS_Pos) /*!< GMAC_T::REGDEBUG: TPESTS Mask */ + +#define GMAC_REGDEBUG_TFCSTS_Pos (17) /*!< GMAC_T::REGDEBUG: TFCSTS Position */ +#define GMAC_REGDEBUG_TFCSTS_Msk (0x3ul << GMAC_REGDEBUG_TFCSTS_Pos) /*!< GMAC_T::REGDEBUG: TFCSTS Mask */ + +#define GMAC_REGDEBUG_TXPAUSED_Pos (19) /*!< GMAC_T::REGDEBUG: TXPAUSED Position */ +#define GMAC_REGDEBUG_TXPAUSED_Msk (0x1ul << GMAC_REGDEBUG_TXPAUSED_Pos) /*!< GMAC_T::REGDEBUG: TXPAUSED Mask */ + +#define GMAC_REGDEBUG_TRCSTS_Pos (20) /*!< GMAC_T::REGDEBUG: TRCSTS Position */ +#define GMAC_REGDEBUG_TRCSTS_Msk (0x3ul << GMAC_REGDEBUG_TRCSTS_Pos) /*!< GMAC_T::REGDEBUG: TRCSTS Mask */ + +#define GMAC_REGDEBUG_TWCSTS_Pos (22) /*!< GMAC_T::REGDEBUG: TWCSTS Position */ +#define GMAC_REGDEBUG_TWCSTS_Msk (0x1ul << GMAC_REGDEBUG_TWCSTS_Pos) /*!< GMAC_T::REGDEBUG: TWCSTS Mask */ + +#define GMAC_REGDEBUG_TXFSTS_Pos (24) /*!< GMAC_T::REGDEBUG: TXFSTS Position */ +#define GMAC_REGDEBUG_TXFSTS_Msk (0x1ul << GMAC_REGDEBUG_TXFSTS_Pos) /*!< GMAC_T::REGDEBUG: TXFSTS Mask */ + +#define GMAC_REGDEBUG_TXSTSFSTS_Pos (25) /*!< GMAC_T::REGDEBUG: TXSTSFSTS Position */ +#define GMAC_REGDEBUG_TXSTSFSTS_Msk (0x1ul << GMAC_REGDEBUG_TXSTSFSTS_Pos) /*!< GMAC_T::REGDEBUG: TXSTSFSTS Mask */ + +#define GMAC_PMTCTLSTS_PWRDWN_Pos (0) /*!< GMAC_T::PMTCTLSTS: PWRDWN Position*/ +#define GMAC_PMTCTLSTS_PWRDWN_Msk (0x1ul << GMAC_PMTCTLSTS_PWRDWN_Pos) /*!< GMAC_T::PMTCTLSTS: PWRDWN Mask */ + +#define GMAC_PMTCTLSTS_MGKPKTEN_Pos (1) /*!< GMAC_T::PMTCTLSTS: MGKPKTEN Position*/ +#define GMAC_PMTCTLSTS_MGKPKTEN_Msk (0x1ul << GMAC_PMTCTLSTS_MGKPKTEN_Pos) /*!< GMAC_T::PMTCTLSTS: MGKPKTEN Mask */ + +#define GMAC_PMTCTLSTS_MGKPRCVD_Pos (5) /*!< GMAC_T::PMTCTLSTS: MGKPRCVD Position*/ +#define GMAC_PMTCTLSTS_MGKPRCVD_Msk (0x1ul << GMAC_PMTCTLSTS_MGKPRCVD_Pos) /*!< GMAC_T::PMTCTLSTS: MGKPRCVD Mask */ + +#define GMAC_LPICTLSTS_TLPIEN_Pos (0) /*!< GMAC_T::LPICTLSTS: TLPIEN Position*/ +#define GMAC_LPICTLSTS_TLPIEN_Msk (0x1ul << GMAC_LPICTLSTS_TLPIEN_Pos) /*!< GMAC_T::LPICTLSTS: TLPIEN Mask */ + +#define GMAC_LPICTLSTS_TLPIEX_Pos (1) /*!< GMAC_T::LPICTLSTS: TLPIEX Position*/ +#define GMAC_LPICTLSTS_TLPIEX_Msk (0x1ul << GMAC_LPICTLSTS_TLPIEX_Pos) /*!< GMAC_T::LPICTLSTS: TLPIEX Mask */ + +#define GMAC_LPICTLSTS_RLPIEN_Pos (2) /*!< GMAC_T::LPICTLSTS: RLPIEN Position*/ +#define GMAC_LPICTLSTS_RLPIEN_Msk (0x1ul << GMAC_LPICTLSTS_RLPIEN_Pos) /*!< GMAC_T::LPICTLSTS: RLPIEN Mask */ + +#define GMAC_LPICTLSTS_RLPIEX_Pos (3) /*!< GMAC_T::LPICTLSTS: RLPIEX Position*/ +#define GMAC_LPICTLSTS_RLPIEX_Msk (0x1ul << GMAC_LPICTLSTS_RLPIEX_Pos) /*!< GMAC_T::LPICTLSTS: RLPIEX Mask */ + +#define GMAC_LPICTLSTS_TLPIST_Pos (8) /*!< GMAC_T::LPICTLSTS: TLPIST Position*/ +#define GMAC_LPICTLSTS_TLPIST_Msk (0x1ul << GMAC_LPICTLSTS_TLPIST_Pos) /*!< GMAC_T::LPICTLSTS: TLPIST Mask */ + +#define GMAC_LPICTLSTS_RLPIST_Pos (9) /*!< GMAC_T::LPICTLSTS: RLPIST Position*/ +#define GMAC_LPICTLSTS_RLPIST_Msk (0x1ul << GMAC_LPICTLSTS_RLPIST_Pos) /*!< GMAC_T::LPICTLSTS: RLPIST Mask */ + +#define GMAC_LPICTLSTS_LPIEN_Pos (16) /*!< GMAC_T::LPICTLSTS: LPIEN Position */ +#define GMAC_LPICTLSTS_LPIEN_Msk (0x1ul << GMAC_LPICTLSTS_LPIEN_Pos) /*!< GMAC_T::LPICTLSTS: LPIEN Mask */ + +#define GMAC_LPICTLSTS_PLS_Pos (17) /*!< GMAC_T::LPICTLSTS: PLS Position */ +#define GMAC_LPICTLSTS_PLS_Msk (0x1ul << GMAC_LPICTLSTS_PLS_Pos) /*!< GMAC_T::LPICTLSTS: PLS Mask */ + +#define GMAC_LPICTLSTS_PLSEN_Pos (18) /*!< GMAC_T::LPICTLSTS: PLSEN Position */ +#define GMAC_LPICTLSTS_PLSEN_Msk (0x1ul << GMAC_LPICTLSTS_PLSEN_Pos) /*!< GMAC_T::LPICTLSTS: PLSEN Mask */ + +#define GMAC_LPICTLSTS_LPITXA_Pos (19) /*!< GMAC_T::LPICTLSTS: LPITXA Position*/ +#define GMAC_LPICTLSTS_LPITXA_Msk (0x1ul << GMAC_LPICTLSTS_LPITXA_Pos) /*!< GMAC_T::LPICTLSTS: LPITXA Mask */ + +#define GMAC_LPITMRCTL_TWT_Pos (0) /*!< GMAC_T::LPITMRCTL: TWT Position */ +#define GMAC_LPITMRCTL_TWT_Msk (0xfffful << GMAC_LPITMRCTL_TWT_Pos) /*!< GMAC_T::LPITMRCTL: TWT Mask */ + +#define GMAC_LPITMRCTL_LST_Pos (16) /*!< GMAC_T::LPITMRCTL: LST Position */ +#define GMAC_LPITMRCTL_LST_Msk (0x3fful << GMAC_LPITMRCTL_LST_Pos) /*!< GMAC_T::LPITMRCTL: LST Mask */ + +#define GMAC_INTSTS_RGSMIIIS_Pos (0) /*!< GMAC_T::INTSTS: RGSMIIIS Position */ +#define GMAC_INTSTS_RGSMIIIS_Msk (0x1ul << GMAC_INTSTS_RGSMIIIS_Pos) /*!< GMAC_T::INTSTS: RGSMIIIS Mask */ + +#define GMAC_INTSTS_PMTIS_Pos (3) /*!< GMAC_T::INTSTS: PMTIS Position */ +#define GMAC_INTSTS_PMTIS_Msk (0x1ul << GMAC_INTSTS_PMTIS_Pos) /*!< GMAC_T::INTSTS: PMTIS Mask */ + +#define GMAC_INTSTS_TSIS_Pos (9) /*!< GMAC_T::INTSTS: TSIS Position */ +#define GMAC_INTSTS_TSIS_Msk (0x1ul << GMAC_INTSTS_TSIS_Pos) /*!< GMAC_T::INTSTS: TSIS Mask */ + +#define GMAC_INTSTS_LPIIS_Pos (10) /*!< GMAC_T::INTSTS: LPIIS Position */ +#define GMAC_INTSTS_LPIIS_Msk (0x1ul << GMAC_INTSTS_LPIIS_Pos) /*!< GMAC_T::INTSTS: LPIIS Mask */ + +#define GMAC_INTMSK_RGSMIIIM_Pos (0) /*!< GMAC_T::INTMSK: RGSMIIIM Position */ +#define GMAC_INTMSK_RGSMIIIM_Msk (0x1ul << GMAC_INTMSK_RGSMIIIM_Pos) /*!< GMAC_T::INTMSK: RGSMIIIM INTMSK */ + +#define GMAC_INTMSK_PCSLCHGIM_Pos (1) /*!< GMAC_T::INTMSK: PCSLCHGIM Position */ +#define GMAC_INTMSK_PCSLCHGIM_Msk (0x1ul << GMAC_INTMSK_PCSLCHGIM_Pos) /*!< GMAC_T::INTMSK: PCSLCHGIM INTMSK */ + +#define GMAC_INTMSK_PCSANCIM_Pos (2) /*!< GMAC_T::INTMSK: PCSANCIM Position */ +#define GMAC_INTMSK_PCSANCIM_Msk (0x1ul << GMAC_INTMSK_PCSANCIM_Pos) /*!< GMAC_T::INTMSK: PCSANCIM INTMSK */ + +#define GMAC_INTMSK_PMTIM_Pos (3) /*!< GMAC_T::INTMSK: PMTIM Position */ +#define GMAC_INTMSK_PMTIM_Msk (0x1ul << GMAC_INTMSK_PMTIM_Pos) /*!< GMAC_T::INTMSK: PMTIM INTMSK */ + +#define GMAC_INTMSK_TSIM_Pos (9) /*!< GMAC_T::INTMSK: TSIM Position */ +#define GMAC_INTMSK_TSIM_Msk (0x1ul << GMAC_INTMSK_TSIM_Pos) /*!< GMAC_T::INTMSK: TSIM INTMSK */ + +#define GMAC_INTMSK_LPIIM_Pos (10) /*!< GMAC_T::INTMSK: LPIIM Position */ +#define GMAC_INTMSK_LPIIM_Msk (0x1ul << GMAC_INTMSK_LPIIM_Pos) /*!< GMAC_T::INTMSK: LPIIM INTMSK */ + +#define GMAC_MACADDR0H_ADDRHI_Pos (0) /*!< GMAC_T::MACADDR0H: ADDRHI Position */ +#define GMAC_MACADDR0H_ADDRHI_Msk (0xfffful << GMAC_MACADDR0H_ADDRHI_Pos) /*!< GMAC_T::MACADDR0H: ADDRHI Mask */ + +#define GMAC_MACADDR0H_AE_Pos (31) /*!< GMAC_T::MACADDR0H: AE Position */ +#define GMAC_MACADDR0H_AE_Msk (0x1ul << GMAC_MACADDR0H_AE_Pos) /*!< GMAC_T::MACADDR0H: AE Mask */ + +#define GMAC_MACADDR0L_ADDRLO_Pos (0) /*!< GMAC_T::MACADDR0L: ADDRLO Position */ +#define GMAC_MACADDR0L_ADDRLO_Msk (0xfffffffful << GMAC_MACADDR0L_ADDRLO_Pos) /*!< GMAC_T::MACADDR0L: ADDRLO Mask */ + +#define GMAC_MACADDR1H_ADDRHI_Pos (0) /*!< GMAC_T::MACADDR1H: ADDRHI Position */ +#define GMAC_MACADDR1H_ADDRHI_Msk (0xfffful << GMAC_MACADDR1H_ADDRHI_Pos) /*!< GMAC_T::MACADDR1H: ADDRHI Mask */ + +#define GMAC_MACADDR1H_MBC_Pos (24) /*!< GMAC_T::MACADDR1H: MBC Position */ +#define GMAC_MACADDR1H_MBC_Msk (0x3ful << GMAC_MACADDR1H_MBC_Pos) /*!< GMAC_T::MACADDR1H: MBC Mask */ + +#define GMAC_MACADDR1H_SA_Pos (30) /*!< GMAC_T::MACADDR1H: SA Position */ +#define GMAC_MACADDR1H_SA_Msk (0x1ul << GMAC_MACADDR1H_SA_Pos) /*!< GMAC_T::MACADDR1H: SA Mask */ + +#define GMAC_MACADDR1H_AE_Pos (31) /*!< GMAC_T::MACADDR1H: AE Position */ +#define GMAC_MACADDR1H_AE_Msk (0x1ul << GMAC_MACADDR1H_AE_Pos) /*!< GMAC_T::MACADDR1H: AE Mask */ + +#define GMAC_MACADDR1L_ADDRLO_Pos (0) /*!< GMAC_T::MACADDR1L: ADDRLO Position */ +#define GMAC_MACADDR1L_ADDRLO_Msk (0xfffffffful << GMAC_MACADDR1L_ADDRLO_Pos) /*!< GMAC_T::MACADDR1L: ADDRLO Mask */ + +#define GMAC_MACADDR2H_ADDRHI_Pos (0) /*!< GMAC_T::MACADDR2H: ADDRHI Position */ +#define GMAC_MACADDR2H_ADDRHI_Msk (0xfffful << GMAC_MACADDR2H_ADDRHI_Pos) /*!< GMAC_T::MACADDR2H: ADDRHI Mask */ + +#define GMAC_MACADDR2H_MBC_Pos (24) /*!< GMAC_T::MACADDR2H: MBC Position */ +#define GMAC_MACADDR2H_MBC_Msk (0x3ful << GMAC_MACADDR2H_MBC_Pos) /*!< GMAC_T::MACADDR2H: MBC Mask */ + +#define GMAC_MACADDR2H_SA_Pos (30) /*!< GMAC_T::MACADDR2H: SA Position */ +#define GMAC_MACADDR2H_SA_Msk (0x1ul << GMAC_MACADDR2H_SA_Pos) /*!< GMAC_T::MACADDR2H: SA Mask */ + +#define GMAC_MACADDR2H_AE_Pos (31) /*!< GMAC_T::MACADDR2H: AE Position */ +#define GMAC_MACADDR2H_AE_Msk (0x1ul << GMAC_MACADDR2H_AE_Pos) /*!< GMAC_T::MACADDR2H: AE Mask */ + +#define GMAC_MACADDR2L_ADDRLO_Pos (0) /*!< GMAC_T::MACADDR2L: ADDRLO Position */ +#define GMAC_MACADDR2L_ADDRLO_Msk (0xfffffffful << GMAC_MACADDR2L_ADDRLO_Pos) /*!< GMAC_T::MACADDR2L: ADDRLO Mask */ + +#define GMAC_MACADDR3H_ADDRHI_Pos (0) /*!< GMAC_T::MACADDR3H: ADDRHI Position */ +#define GMAC_MACADDR3H_ADDRHI_Msk (0xfffful << GMAC_MACADDR3H_ADDRHI_Pos) /*!< GMAC_T::MACADDR3H: ADDRHI Mask */ + +#define GMAC_MACADDR3H_MBC_Pos (24) /*!< GMAC_T::MACADDR3H: MBC Position */ +#define GMAC_MACADDR3H_MBC_Msk (0x3ful << GMAC_MACADDR3H_MBC_Pos) /*!< GMAC_T::MACADDR3H: MBC Mask */ + +#define GMAC_MACADDR3H_SA_Pos (30) /*!< GMAC_T::MACADDR3H: SA Position */ +#define GMAC_MACADDR3H_SA_Msk (0x1ul << GMAC_MACADDR3H_SA_Pos) /*!< GMAC_T::MACADDR3H: SA Mask */ + +#define GMAC_MACADDR3H_AE_Pos (31) /*!< GMAC_T::MACADDR3H: AE Position */ +#define GMAC_MACADDR3H_AE_Msk (0x1ul << GMAC_MACADDR3H_AE_Pos) /*!< GMAC_T::MACADDR3H: AE Mask */ + +#define GMAC_MACADDR3L_ADDRLO_Pos (0) /*!< GMAC_T::MACADDR3L: ADDRLO Position */ +#define GMAC_MACADDR3L_ADDRLO_Msk (0xfffffffful << GMAC_MACADDR3L_ADDRLO_Pos) /*!< GMAC_T::MACADDR3L: ADDRLO Mask */ + +#define GMAC_MACADDR4H_ADDRHI_Pos (0) /*!< GMAC_T::MACADDR4H: ADDRHI Position */ +#define GMAC_MACADDR4H_ADDRHI_Msk (0xfffful << GMAC_MACADDR4H_ADDRHI_Pos) /*!< GMAC_T::MACADDR4H: ADDRHI Mask */ + +#define GMAC_MACADDR4H_MBC_Pos (24) /*!< GMAC_T::MACADDR4H: MBC Position */ +#define GMAC_MACADDR4H_MBC_Msk (0x3ful << GMAC_MACADDR4H_MBC_Pos) /*!< GMAC_T::MACADDR4H: MBC Mask */ + +#define GMAC_MACADDR4H_SA_Pos (30) /*!< GMAC_T::MACADDR4H: SA Position */ +#define GMAC_MACADDR4H_SA_Msk (0x1ul << GMAC_MACADDR4H_SA_Pos) /*!< GMAC_T::MACADDR4H: SA Mask */ + +#define GMAC_MACADDR4H_AE_Pos (31) /*!< GMAC_T::MACADDR4H: AE Position */ +#define GMAC_MACADDR4H_AE_Msk (0x1ul << GMAC_MACADDR4H_AE_Pos) /*!< GMAC_T::MACADDR4H: AE Mask */ + +#define GMAC_MACADDR4L_ADDRLO_Pos (0) /*!< GMAC_T::MACADDR4L: ADDRLO Position */ +#define GMAC_MACADDR4L_ADDRLO_Msk (0xfffffffful << GMAC_MACADDR4L_ADDRLO_Pos) /*!< GMAC_T::MACADDR4L: ADDRLO Mask */ + +#define GMAC_MACADDR5H_ADDRHI_Pos (0) /*!< GMAC_T::MACADDR5H: ADDRHI Position */ +#define GMAC_MACADDR5H_ADDRHI_Msk (0xfffful << GMAC_MACADDR5H_ADDRHI_Pos) /*!< GMAC_T::MACADDR5H: ADDRHI Mask */ + +#define GMAC_MACADDR5H_MBC_Pos (24) /*!< GMAC_T::MACADDR5H: MBC Position */ +#define GMAC_MACADDR5H_MBC_Msk (0x3ful << GMAC_MACADDR5H_MBC_Pos) /*!< GMAC_T::MACADDR5H: MBC Mask */ + +#define GMAC_MACADDR5H_SA_Pos (30) /*!< GMAC_T::MACADDR5H: SA Position */ +#define GMAC_MACADDR5H_SA_Msk (0x1ul << GMAC_MACADDR5H_SA_Pos) /*!< GMAC_T::MACADDR5H: SA Mask */ + +#define GMAC_MACADDR5H_AE_Pos (31) /*!< GMAC_T::MACADDR5H: AE Position */ +#define GMAC_MACADDR5H_AE_Msk (0x1ul << GMAC_MACADDR5H_AE_Pos) /*!< GMAC_T::MACADDR5H: AE Mask */ + +#define GMAC_MACADDR5L_ADDRLO_Pos (0) /*!< GMAC_T::MACADDR5L: ADDRLO Position */ +#define GMAC_MACADDR5L_ADDRLO_Msk (0xfffffffful << GMAC_MACADDR5L_ADDRLO_Pos) /*!< GMAC_T::MACADDR5L: ADDRLO Mask */ + +#define GMAC_MACADDR6H_ADDRHI_Pos (0) /*!< GMAC_T::MACADDR6H: ADDRHI Position */ +#define GMAC_MACADDR6H_ADDRHI_Msk (0xfffful << GMAC_MACADDR6H_ADDRHI_Pos) /*!< GMAC_T::MACADDR6H: ADDRHI Mask */ + +#define GMAC_MACADDR6H_MBC_Pos (24) /*!< GMAC_T::MACADDR6H: MBC Position */ +#define GMAC_MACADDR6H_MBC_Msk (0x3ful << GMAC_MACADDR6H_MBC_Pos) /*!< GMAC_T::MACADDR6H: MBC Mask */ + +#define GMAC_MACADDR6H_SA_Pos (30) /*!< GMAC_T::MACADDR6H: SA Position */ +#define GMAC_MACADDR6H_SA_Msk (0x1ul << GMAC_MACADDR6H_SA_Pos) /*!< GMAC_T::MACADDR6H: SA Mask */ + +#define GMAC_MACADDR6H_AE_Pos (31) /*!< GMAC_T::MACADDR6H: AE Position */ +#define GMAC_MACADDR6H_AE_Msk (0x1ul << GMAC_MACADDR6H_AE_Pos) /*!< GMAC_T::MACADDR6H: AE Mask */ + +#define GMAC_MACADDR6L_ADDRLO_Pos (0) /*!< GMAC_T::MACADDR6L: ADDRLO Position */ +#define GMAC_MACADDR6L_ADDRLO_Msk (0xfffffffful << GMAC_MACADDR6L_ADDRLO_Pos) /*!< GMAC_T::MACADDR6L: ADDRLO Mask */ + +#define GMAC_MACADDR7H_ADDRHI_Pos (0) /*!< GMAC_T::MACADDR7H: ADDRHI Position */ +#define GMAC_MACADDR7H_ADDRHI_Msk (0xfffful << GMAC_MACADDR7H_ADDRHI_Pos) /*!< GMAC_T::MACADDR7H: ADDRHI Mask */ + +#define GMAC_MACADDR7H_MBC_Pos (24) /*!< GMAC_T::MACADDR7H: MBC Position */ +#define GMAC_MACADDR7H_MBC_Msk (0x3ful << GMAC_MACADDR7H_MBC_Pos) /*!< GMAC_T::MACADDR7H: MBC Mask */ + +#define GMAC_MACADDR7H_SA_Pos (30) /*!< GMAC_T::MACADDR7H: SA Position */ +#define GMAC_MACADDR7H_SA_Msk (0x1ul << GMAC_MACADDR7H_SA_Pos) /*!< GMAC_T::MACADDR7H: SA Mask */ + +#define GMAC_MACADDR7H_AE_Pos (31) /*!< GMAC_T::MACADDR7H: AE Position */ +#define GMAC_MACADDR7H_AE_Msk (0x1ul << GMAC_MACADDR7H_AE_Pos) /*!< GMAC_T::MACADDR7H: AE Mask */ + +#define GMAC_MACADDR7L_ADDRLO_Pos (0) /*!< GMAC_T::MACADDR7L: ADDRLO Position */ +#define GMAC_MACADDR7L_ADDRLO_Msk (0xfffffffful << GMAC_MACADDR7L_ADDRLO_Pos) /*!< GMAC_T::MACADDR7L: ADDRLO Mask */ + +#define GMAC_MACADDR8H_ADDRHI_Pos (0) /*!< GMAC_T::MACADDR8H: ADDRHI Position */ +#define GMAC_MACADDR8H_ADDRHI_Msk (0xfffful << GMAC_MACADDR8H_ADDRHI_Pos) /*!< GMAC_T::MACADDR8H: ADDRHI Mask */ + +#define GMAC_MACADDR8H_MBC_Pos (24) /*!< GMAC_T::MACADDR8H: MBC Position */ +#define GMAC_MACADDR8H_MBC_Msk (0x3ful << GMAC_MACADDR8H_MBC_Pos) /*!< GMAC_T::MACADDR8H: MBC Mask */ + +#define GMAC_MACADDR8H_SA_Pos (30) /*!< GMAC_T::MACADDR8H: SA Position */ +#define GMAC_MACADDR8H_SA_Msk (0x1ul << GMAC_MACADDR8H_SA_Pos) /*!< GMAC_T::MACADDR8H: SA Mask */ + +#define GMAC_MACADDR8H_AE_Pos (31) /*!< GMAC_T::MACADDR8H: AE Position */ +#define GMAC_MACADDR8H_AE_Msk (0x1ul << GMAC_MACADDR8H_AE_Pos) /*!< GMAC_T::MACADDR8H: AE Mask */ + +#define GMAC_MACADDR8L_ADDRLO_Pos (0) /*!< GMAC_T::MACADDR8L: ADDRLO Position */ +#define GMAC_MACADDR8L_ADDRLO_Msk (0xfffffffful << GMAC_MACADDR8L_ADDRLO_Pos) /*!< GMAC_T::MACADDR8L: ADDRLO Mask */ + +#define GMAC_RGMIICTLSTS_LNKMOD_Pos (0) /*!< GMAC_T::RGMIICTLSTS: LNKMOD Position*/ +#define GMAC_RGMIICTLSTS_LNKMOD_Msk (0x1ul << GMAC_RGMIICTLSTS_LNKMOD_Pos) /*!< GMAC_T::RGMIICTLSTS: LNKMOD Mask */ + +#define GMAC_RGMIICTLSTS_LNKSPEED_Pos (1) /*!< GMAC_T::RGMIICTLSTS: LNKSPEED Position*/ +#define GMAC_RGMIICTLSTS_LNKSPEED_Msk (0x3ul << GMAC_RGMIICTLSTS_LNKSPEED_Pos) /*!< GMAC_T::RGMIICTLSTS: LNKSPEED Mask */ + +#define GMAC_RGMIICTLSTS_LNKSTS_Pos (3) /*!< GMAC_T::RGMIICTLSTS: LNKSTS Position*/ +#define GMAC_RGMIICTLSTS_LNKSTS_Msk (0x1ul << GMAC_RGMIICTLSTS_LNKSTS_Pos) /*!< GMAC_T::RGMIICTLSTS: LNKSTS Mask */ + +#define GMAC_WDTOUT_WTO_Pos (0) /*!< GMAC_T::WDTOUT: WTO Position */ +#define GMAC_WDTOUT_WTO_Msk (0x3ffful << GMAC_WDTOUT_WTO_Pos) /*!< GMAC_T::WDTOUT: WTO Mask */ + +#define GMAC_WDTOUT_PWE_Pos (16) /*!< GMAC_T::WDTOUT: PWE Position */ +#define GMAC_WDTOUT_PWE_Msk (0x1ul << GMAC_WDTOUT_PWE_Pos) /*!< GMAC_T::WDTOUT: PWE Mask */ + +#define GMAC_VLANINCL_VLT_Pos (0) /*!< GMAC_T::VLANINCL: VLT Position */ +#define GMAC_VLANINCL_VLT_Msk (0xfffful << GMAC_VLANINCL_VLT_Pos) /*!< GMAC_T::VLANINCL: VLT Mask */ + +#define GMAC_VLANINCL_VLC_Pos (16) /*!< GMAC_T::VLANINCL: VLC Position */ +#define GMAC_VLANINCL_VLC_Msk (0x3ul << GMAC_VLANINCL_VLC_Pos) /*!< GMAC_T::VLANINCL: VLC Mask */ + +#define GMAC_VLANINCL_VLP_Pos (18) /*!< GMAC_T::VLANINCL: VLP Position */ +#define GMAC_VLANINCL_VLP_Msk (0x1ul << GMAC_VLANINCL_VLP_Pos) /*!< GMAC_T::VLANINCL: VLP Mask */ + +#define GMAC_VLANINCL_CSVL_Pos (19) /*!< GMAC_T::VLANINCL: CSVL Position */ +#define GMAC_VLANINCL_CSVL_Msk (0x1ul << GMAC_VLANINCL_CSVL_Pos) /*!< GMAC_T::VLANINCL: CSVL Mask */ + +#define GMAC_TSCTL_TSENA_Pos (0) /*!< GMAC_T::TSCTL: TSENA Position */ +#define GMAC_TSCTL_TSENA_Msk (0x1ul << GMAC_TSCTL_TSENA_Pos) /*!< GMAC_T::TSCTL: TSENA Mask */ + +#define GMAC_TSCTL_TSCFUPDT_Pos (1) /*!< GMAC_T::TSCTL: TSCFUPDT Position */ +#define GMAC_TSCTL_TSCFUPDT_Msk (0x1ul << GMAC_TSCTL_TSCFUPDT_Pos) /*!< GMAC_T::TSCTL: TSCFUPDT Mask */ + +#define GMAC_TSCTL_TSINIT_Pos (2) /*!< GMAC_T::TSCTL: TSINIT Position */ +#define GMAC_TSCTL_TSINIT_Msk (0x1ul << GMAC_TSCTL_TSINIT_Pos) /*!< GMAC_T::TSCTL: TSINIT Mask */ + +#define GMAC_TSCTL_TSUPDT_Pos (3) /*!< GMAC_T::TSCTL: TSUPDT Position */ +#define GMAC_TSCTL_TSUPDT_Msk (0x1ul << GMAC_TSCTL_TSUPDT_Pos) /*!< GMAC_T::TSCTL: TSUPDT Mask */ + +#define GMAC_TSCTL_TSTRIG_Pos (4) /*!< GMAC_T::TSCTL: TSTRIG Position */ +#define GMAC_TSCTL_TSTRIG_Msk (0x1ul << GMAC_TSCTL_TSTRIG_Pos) /*!< GMAC_T::TSCTL: TSTRIG Mask */ + +#define GMAC_TSCTL_TSADDREG_Pos (5) /*!< GMAC_T::TSCTL: TSADDREG Position */ +#define GMAC_TSCTL_TSADDREG_Msk (0x1ul << GMAC_TSCTL_TSADDREG_Pos) /*!< GMAC_T::TSCTL: TSADDREG Mask */ + +#define GMAC_TSCTL_TSENALL_Pos (8) /*!< GMAC_T::TSCTL: TSENALL Position */ +#define GMAC_TSCTL_TSENALL_Msk (0x1ul << GMAC_TSCTL_TSENALL_Pos) /*!< GMAC_T::TSCTL: TSENALL Mask */ + +#define GMAC_TSCTL_TSCTRLSSR_Pos (9) /*!< GMAC_T::TSCTL: TSCTRLSSR Position */ +#define GMAC_TSCTL_TSCTRLSSR_Msk (0x1ul << GMAC_TSCTL_TSCTRLSSR_Pos) /*!< GMAC_T::TSCTL: TSCTRLSSR Mask */ + +#define GMAC_TSCTL_TSVER2ENA_Pos (10) /*!< GMAC_T::TSCTL: TSVER2ENA Position */ +#define GMAC_TSCTL_TSVER2ENA_Msk (0x1ul << GMAC_TSCTL_TSVER2ENA_Pos) /*!< GMAC_T::TSCTL: TSVER2ENA Mask */ + +#define GMAC_TSCTL_TSIPENA_Pos (11) /*!< GMAC_T::TSCTL: TSIPENA Position */ +#define GMAC_TSCTL_TSIPENA_Msk (0x1ul << GMAC_TSCTL_TSIPENA_Pos) /*!< GMAC_T::TSCTL: TSIPENA Mask */ + +#define GMAC_TSCTL_TSIPV6ENA_Pos (12) /*!< GMAC_T::TSCTL: TSIPV6ENA Position */ +#define GMAC_TSCTL_TSIPV6ENA_Msk (0x1ul << GMAC_TSCTL_TSIPV6ENA_Pos) /*!< GMAC_T::TSCTL: TSIPV6ENA Mask */ + +#define GMAC_TSCTL_TSIPV4ENA_Pos (13) /*!< GMAC_T::TSCTL: TSIPV4ENA Position */ +#define GMAC_TSCTL_TSIPV4ENA_Msk (0x1ul << GMAC_TSCTL_TSIPV4ENA_Pos) /*!< GMAC_T::TSCTL: TSIPV4ENA Mask */ + +#define GMAC_TSCTL_TSEVNTENA_Pos (14) /*!< GMAC_T::TSCTL: TSEVNTENA Position */ +#define GMAC_TSCTL_TSEVNTENA_Msk (0x1ul << GMAC_TSCTL_TSEVNTENA_Pos) /*!< GMAC_T::TSCTL: TSEVNTENA Mask */ + +#define GMAC_TSCTL_TSMSTRENA_Pos (15) /*!< GMAC_T::TSCTL: TSMSTRENA Position */ +#define GMAC_TSCTL_TSMSTRENA_Msk (0x1ul << GMAC_TSCTL_TSMSTRENA_Pos) /*!< GMAC_T::TSCTL: TSMSTRENA Mask */ + +#define GMAC_TSCTL_SNAPTYPSEL_Pos (16) /*!< GMAC_T::TSCTL: SNAPTYPSEL Position */ +#define GMAC_TSCTL_SNAPTYPSEL_Msk (0x3ul << GMAC_TSCTL_SNAPTYPSEL_Pos) /*!< GMAC_T::TSCTL: SNAPTYPSEL Mask */ + +#define GMAC_TSCTL_TSENMACADDR_Pos (18) /*!< GMAC_T::TSCTL: TSENMACADDR Position */ +#define GMAC_TSCTL_TSENMACADDR_Msk (0x1ul << GMAC_TSCTL_TSENMACADDR_Pos) /*!< GMAC_T::TSCTL: TSENMACADDR Mask */ + +#define GMAC_SSECINC_SSINC_Pos (0) /*!< GMAC_T::SSECINC: SSINC Position */ +#define GMAC_SSECINC_SSINC_Msk (0xfful << GMAC_SSECINC_SSINC_Pos) /*!< GMAC_T::SSECINC: SSINC Mask */ + +#define GMAC_STSEC_TSS_Pos (0) /*!< GMAC_T::STSEC: TSS Position */ +#define GMAC_STSEC_TSS_Msk (0xfffffffful << GMAC_STSEC_TSS_Pos) /*!< GMAC_T::STSEC: TSS Mask */ + +#define GMAC_STNSEC_TSSS_Pos (0) /*!< GMAC_T::STNSEC: TSSS Position */ +#define GMAC_STNSEC_TSSS_Msk (0x7ffffffful << GMAC_STNSEC_TSSS_Pos) /*!< GMAC_T::STNSEC: TSSS Mask */ + +#define GMAC_STSECU_TSS_Pos (0) /*!< GMAC_T::STSECU: TSS Position */ +#define GMAC_STSECU_TSS_Msk (0xfffffffful << GMAC_STSECU_TSS_Pos) /*!< GMAC_T::STSECU: TSS Mask */ + +#define GMAC_STNSECU_TSSS_Pos (0) /*!< GMAC_T::STNSECU: TSSS Position */ +#define GMAC_STNSECU_TSSS_Msk (0x7ffffffful << GMAC_STNSECU_TSSS_Pos) /*!< GMAC_T::STNSECU: TSSS Mask */ + +#define GMAC_STNSECU_ADDSUB_Pos (31) /*!< GMAC_T::STNSECU: ADDSUB Position */ +#define GMAC_STNSECU_ADDSUB_Msk (0x1ul << GMAC_STNSECU_ADDSUB_Pos) /*!< GMAC_T::STNSECU: ADDSUB Mask */ + +#define GMAC_TSADDEND_TSAR_Pos (0) /*!< GMAC_T::TSADDEND: TSAR Position */ +#define GMAC_TSADDEND_TSAR_Msk (0xfffffffful << GMAC_TSADDEND_TSAR_Pos) /*!< GMAC_T::TSADDEND: TSAR Mask */ + +#define GMAC_TGTSEC_TSTR_Pos (0) /*!< GMAC_T::TGTSEC: TSTR Position */ +#define GMAC_TGTSEC_TSTR_Msk (0xfffffffful << GMAC_TGTSEC_TSTR_Pos) /*!< GMAC_T::TGTSEC: TSTR Mask */ + +#define GMAC_TGTNSEC_TTSLO_Pos (0) /*!< GMAC_T::TGTNSEC: TTSLO Position */ +#define GMAC_TGTNSEC_TTSLO_Msk (0x7ffffffful << GMAC_TGTNSEC_TTSLO_Pos) /*!< GMAC_T::TGTNSEC: TTSLO Mask */ + +#define GMAC_TGTNSEC_TRGTBUSY_Pos (31) /*!< GMAC_T::TGTNSEC: TRGTBUSY Position */ +#define GMAC_TGTNSEC_TRGTBUSY_Msk (0x1ul << GMAC_TGTNSEC_TRGTBUSY_Pos) /*!< GMAC_T::TGTNSEC: TRGTBUSY Mask */ + +#define GMAC_STHSEC_TSHWR_Pos (0) /*!< GMAC_T::STHSEC: TSHWR Position */ +#define GMAC_STHSEC_TSHWR_Msk (0xfffful << GMAC_STHSEC_TSHWR_Pos) /*!< GMAC_T::STHSEC: TSHWR Mask */ + +#define GMAC_TSSTS_TSSOVF_Pos (0) /*!< GMAC_T::TSSTS: TSSOVF Position */ +#define GMAC_TSSTS_TSSOVF_Msk (0x1ul << GMAC_TSSTS_TSSOVF_Pos) /*!< GMAC_T::TSSTS: TSSOVF Mask */ + +#define GMAC_TSSTS_TSTARGT_Pos (1) /*!< GMAC_T::TSSTS: TSTARGT Position */ +#define GMAC_TSSTS_TSTARGT_Msk (0x1ul << GMAC_TSSTS_TSTARGT_Pos) /*!< GMAC_T::TSSTS: TSTARGT Mask */ + +#define GMAC_TSSTS_AUXTSTRIG_Pos (2) /*!< GMAC_T::TSSTS: AUXTSTRIG Position */ +#define GMAC_TSSTS_AUXTSTRIG_Msk (0x1ul << GMAC_TSSTS_AUXTSTRIG_Pos) /*!< GMAC_T::TSSTS: AUXTSTRIG Mask */ + +#define GMAC_TSSTS_TSTRGTERR_Pos (3) /*!< GMAC_T::TSSTS: TSTRGTERR Position */ +#define GMAC_TSSTS_TSTRGTERR_Msk (0x1ul << GMAC_TSSTS_TSTRGTERR_Pos) /*!< GMAC_T::TSSTS: TSTRGTERR Mask */ + +#define GMAC_TSSTS_ATSSTN_Pos (16) /*!< GMAC_T::TSSTS: ATSSTN Position */ +#define GMAC_TSSTS_ATSSTN_Msk (0xful << GMAC_TSSTS_ATSSTN_Pos) /*!< GMAC_T::TSSTS: ATSSTN Mask */ + +#define GMAC_PPSCTL_PPSCTL_PPSCMD_Pos (0) /*!< GMAC_T::PPSCTL: PPSCTL_PPSCMD Position*/ +#define GMAC_PPSCTL_PPSCTL_PPSCMD_Msk (0xful << GMAC_PPSCTL_PPSCTL_PPSCMD_Pos) /*!< GMAC_T::PPSCTL: PPSCTL_PPSCMD Mask */ + +#define GMAC_PPSCTL_PPSEN0_Pos (4) /*!< GMAC_T::PPSCTL: PPSEN0 Position */ +#define GMAC_PPSCTL_PPSEN0_Msk (0x1ul << GMAC_PPSCTL_PPSEN0_Pos) /*!< GMAC_T::PPSCTL: PPSEN0 Mask */ + +#define GMAC_PPSCTL_TRGTMODSEL0_Pos (5) /*!< GMAC_T::PPSCTL: TRGTMODSEL0 Position */ +#define GMAC_PPSCTL_TRGTMODSEL0_Msk (0x3ul << GMAC_PPSCTL_TRGTMODSEL0_Pos) /*!< GMAC_T::PPSCTL: TRGTMODSEL0 Mask */ + +#define GMAC_PPSINTVL_PPSINT_Pos (0) /*!< GMAC_T::PPSINTVL: PPSINT Position */ +#define GMAC_PPSINTVL_PPSINT_Msk (0xfffffffful << GMAC_PPSINTVL_PPSINT_Pos) /*!< GMAC_T::PPSINTVL: PPSINT Mask */ + +#define GMAC_PPSWDTH_PPSWIDTH_Pos (0) /*!< GMAC_T::PPSWDTH: PPSWIDTH Position */ +#define GMAC_PPSWDTH_PPSWIDTH_Msk (0xfffffffful << GMAC_PPSWDTH_PPSWIDTH_Pos) /*!< GMAC_T::PPSWDTH: PPSWIDTH Mask */ + +/**@}*/ /* GMAC_CONST */ +/**@}*/ /* end of GMAC register group */ + +/** + @addtogroup GMAC Gigabit Ethernet MAC DMA(GMACDMA) + Memory Mapped Structure for GMAC DMA +@{ */ + +typedef struct +{ + + /** + * @var GMACDMA_T::BUSMODE + * Offset: 0x0000 Register 1000 (Bus Mode Register) + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[0] |SWR |Software Reset + * | | |When this bit is set, the MAC DMA Controller resets the logic and all internal registers of the MAC + * | | |It is cleared automatically after the reset operation has completed in all of the GMAC clock domains + * | | |Before reprogramming any register of the GMAC, you should read a zero (0) value in this bit . + * | | |Note: + * | | |The Software reset function is driven only by this bit. + * | | |The reset operation is completed only when all resets in all active clock domains are de-asserted + * | | |Therefore, it is essential that all the PHY inputs clocks (applicable for the selected PHY interface) are present for the software reset completion. + * |[6:2] |DSL |Descriptor Skip Length + * | | |This bit specifies the number of Word, Dword, or Lword (depending on the 32-bit, 64-bit, or 128-bit bus) to skip between two unchained descriptors + * | | |The address skipping starts from the end of current descriptor to the start of next descriptor + * | | |When the DSL value is equal to zero, the descriptor table is taken as contiguous by the DMA in Ring mode. + * |[7] |ATDS |Alternate Descriptor Size + * | | |When set, the size of the alternate descriptor increases to 32 bytes (8 DWORDS) + * | | |This is required when the Advanced Timestamp feature or the IPC Full Offload Engine (Type 2) is enabled in the receiver + * | | |The enhanced descriptor is not required if the Advanced Timestamp and IPC Full Checksum Offload (Type 2) features are not enabled + * | | |In such cases, you can use the 16 bytes descriptor to save 4 bytes of memory. + * | | |When reset, the descriptor size reverts back to 4 DWORDs (16 bytes) + * | | |This bit preserves the backward compatibility for the descriptor size + * | | |In versions prior to 3.50a, the descriptor size is 16 bytes for both normal and enhanced descriptor + * | | |In version 3.50a, descriptor size is increased to 32 bytes because of the Advanced Timestamp and IPC Full Checksum Offload Engine (Type 2) features. + * |[13:8] |PBL |Programmable Burst Length + * | | |These bits indicate the maximum number of beats to be transferred in one DMA transaction + * | | |This is the maximum value that is used in a single block Read or Write + * | | |The DMA always attempts to burst as specified in PBL each time it starts a Burst transfer on the host bus + * | | |PBL can be programmed with permissible values of 1, 2, 4, 8, 16, and 32 + * | | |Any other value results in undefined behavior + * | | |When USP is set high, this PBL value is applicable only for Tx DMA transactions + * | | |If the number of beats to be transferred is more than 32, then perform the following steps: + * | | |1. Set the PBLx8 mode. + * | | |2. Set the PBL. + * | | |For example, if the maximum number of beats to be transferred is 64, then first set PBLx8 to 1 and then set PBL to 8 + * | | |The PBL values have the following limitation: The maximum number of possible beats (PBL) is limited by the size of the Tx FIFO and Rx FIFO in the MTL layer and the data bus width on the DMA + * | | |The FIFO has a constraint that the maximum beat supported is half the depth of the FIFO, except when specified. + * | | |For different data bus widths and FIFO sizes, the valid PBL range (including x8 mode) is provided in the following list + * | | |If the PBL is common for both transmit and receive DMA, the minimum Rx FIFO and Tx FIFO depths must be considered. + * | | |Note: In the half-duplex mode, the valid PBL range specified in the following list is applicable only for Tx FIFO. + * | | |* 32-Bit Data Bus PPSWDTH + * | | |128 Bytes FIFO Depth: In the full-duplex mode, the valid PBL range is 16 or less + * | | |In the half-duplex mode, the valid PBL range is 8 or less for the 10 or 100 Mbps mode. + * | | |256 Bytes FIFO Depth: In the full-duplex mode and the half-duplex (10 or 100 Mbps) modes, the valid PBL range is 32 or less. + * | | |512 Bytes FIFO Depth: In the full-duplex mode and the half-duplex (10 or 100 Mbps) modes, the valid PBL range is 64 or less. + * | | |1 KB FIFO Depth: In the full-duplex mode, the valid PBL range is 128 or less + * | | |In the half-duplex mode, the valid PBL range is 128 or less in the 10 or 100 Mbps mode and 64 or less in the 1000 Mbps mode. + * | | |2 KB and Higher FIFO Depth: All PBL values are supported in the full-duplex mode and half-duplex modes. + * | | |* 64-Bit Data Bus PPSWDTH + * | | |128 Bytes FIFO Depth: In the full-duplex mode, the valid PBL range is 8 or less + * | | |In the half-duplex mode, the valid PBL range is 4 or less for the 10 or 100 Mbps mode. + * | | |256 Bytes FIFO Depth: In the full-duplex mode and the half-duplex (10 or 100 Mbps) modes, the valid PBL range is 16 or less. + * | | |512 Bytes FIFO Depth: In the full-duplex mode and the half-duplex (10 or 100 Mbps) modes, the valid PBL range is 32 or less. + * | | |1 KB FIFO Depth: In the full-duplex mode, the valid PBL range is 64 or less + * | | |In the half-duplex mode, the valid PBL range is 64 or less in the 10 or 100 Mbps mode and 32 or less in the 1000-Mbps mode. + * | | |2 KB FIFO Depth: In the full-duplex mode and the half-duplex (10 or 100 Mbps) modes, the valid PBL range is 128 or less. + * | | |4 KB and Higher FIFO Depth: All PBL values are supported in the full-duplex and half-duplex modes. + * | | |* 128-Bit Data Bus PPSWDTH + * | | |128 Bytes FIFO Depth: In the full-duplex mode, the valid PBL range is 4 or less + * | | |In the half-duplex mode, the valid PBL range is 2 or less for the 10 or 100 Mbps mode. + * | | |256 Bytes FIFO Depth: In the full-duplex mode and the half-duplex (10 or 100 Mbps) modes, the valid PBL range is 8 or less. + * | | |512 Bytes FIFO Depth: In the full-duplex mode and the half-duplex (10 or 100 Mbps) modes, the valid PBL range is 16 or less. + * | | |1 KB FIFO Depth: In the full-duplex mode, the valid PBL range is 32 or less + * | | |In the half-duplex mode, the valid PBL range is 32 or less in the 10 or 100 Mbps mode and 16 or less in the 1000-Mbps mode. + * | | |2 KB FIFO Depth: In the full-duplex mode and the half-duplex (10 or 100 Mbps) modes, the valid PBL range is 64 or less. + * | | |4 KB FIFO Depth: In the full-duplex mode and the half-duplex (10 or 100 Mbps) modes, the valid PBL range is 128 or less. + * | | |8 KB and Higher FIFO Depth: All PBL values are supported in the full-duplex and half-duplex modes. + * |[16] |FB |Fixed Burst + * | | |This bit controls whether the AHB or AXI Master interface performs fixed burst transfers or not + * | | |When set, the AHB interface uses only SINGLE, INCR4, INCR8, or INCR16 during start of the normal burst transfers + * | | |When reset, the AHB or AXI interface uses SINGLE and INCR burst transfer operations. + * | | |For more information, see Bit 0 (UNDEF) of the AXI Bus Mode register. + * |[22:17] |RPBL |Rx DMA PBL + * | | |This field indicates the maximum number of beats to be transferred in one Rx DMA transaction + * | | |This is the maximum value that is used in a single block Read or Write. + * | | |The Rx DMA always attempts to burst as specified in the RPBL bit each time it starts a Burst transfer on the host bus + * | | |You can program RPBL with values of 1, 2, 4, 8, 16, and 32 + * | | |Any other value results in undefined behavior + * | | |This field is valid and applicable only when USP is set high. + * |[23] |USP |Use Separate PBL + * | | |When set high, this bit configures the Rx DMA to use the value configured in Bits[22:17] as PBL + * | | |The PBL value in Bits[13:8] is applicable only to the Tx DMA operations. + * | | |When reset to low, the PBL value in Bits[13:8] is applicable for both DMA engines. + * |[24] |PBLx8 |PBLx8 Mode + * | | |When set high, this bit multiplies the programmed PBL value (Bits[22:17] and Bits[13:8]) eight times + * | | |Therefore, the DMA transfers the data in 8, 16, 32, 64, 128, and 256 beats depending on the PBL value + * |[25] |AAL |Address Aligned Beats + * | | |When this bit is set high and the FB bit is equal to 1, the AHB or AXI interface generates all bursts aligned to the start address LS bits + * | | |If the FB bit is equal to 0, the first burst (accessing the data buffer's start address) is not aligned, but subsequent bursts are aligned to the address. + * @var GMACDMA_T::TXDEM + * Offset: 0x0004 Register 1001 (Transmit Poll Demand Register) + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[31:0] |TPD |Transmit Poll Demand + * | | |When these bits are written with any value, the DMA reads the current descriptor pointed to by Register 1018 (Current Host Transmit Descriptor Register) + * | | |If that descriptor is not available (owned by the Host), the transmission returns to the Suspend state and the Bit 2 (TU) of Register 1005 (Status Register) is asserted + * | | |If the descriptor is available, the transmission resumes. + * @var GMACDMA_T::RXDEM + * Offset: 0x0008 Register 1002 (Receive Poll Demand Register) + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[31:0] |RPD |Receive Poll Demand + * | | |When these bits are written with any value, the DMA reads the current descriptor pointed to by Register 1019 (Current Host Receive Descriptor Register) + * | | |If that descriptor is not available (owned by the Host), the reception returns to the Suspended state and the Bit 7 (RU) of Register 1005 (Status Register) is not asserted + * | | |If the descriptor is available, the Rx DMA returns to the active state. + * @var GMACDMA_T::RXDADDR + * Offset: 0x000C Register 1003 (Receive Descriptor List Address Register) + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[31:3] |RDESLA_64_bit|Start of Receive List + * | | |This field contains the base address of the first descriptor in the Receive Descriptor list + * | | |The LSB bits (2:0) for 64-bit bus width are ignored and are internally taken as all-zero by the DMA + * | | |Therefore, these LSB bits are read-only (RO). + * @var GMACDMA_T::TXDADDR + * Offset: 0x0010 Register 1004 (Transmit Descriptor List Address Register) + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[31:3] |TDESLA_64_bit|Start of Transmit List + * | | |This field contains the base address of the first descriptor in the Transmit Descriptor list + * | | |The LSB bits (2:0) for 64-bit bus width are ignored and are internally taken as all-zero by the DMA + * | | |Therefore, these LSB bits are read-only (RO). + * @var GMACDMA_T::Status + * Offset: 0x0014 Register 1005 (Status Register) + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[0] |TI |Transmit Interrupt + * | | |This bit indicates that the frame transmission is complete + * | | |When transmission is complete, Bit 31 (OWN) of TDES0 is reset, and the specific frame status information is updated in the descriptor. + * |[1] |TPS |Transmit Process Stopped + * | | |This bit is set when the transmission is stopped. + * |[2] |TU |Transmit Buffer Unavailable + * | | |This bit indicates that the host owns the Next Descriptor in the Transmit List and the DMA cannot acquire it + * | | |Transmission is suspended + * | | |Bits[22:20] explain the Transmit Process state transitions. + * | | |To resume processing Transmit descriptors, the host should change the ownership of the descriptor by setting TDES0[31] and then issue a Transmit Poll Demand command. + * |[3] |TJT |Transmit Jabber Timeout + * | | |This bit indicates that the Transmit Jabber Timer expired, which happens when the frame size exceeds 2,048 (10,240 bytes when the Jumbo frame is enabled) + * | | |When the Jabber Timeout occurs, the transmission process is aborted and placed in the Stopped state + * | | |This causes the Transmit Jabber Timeout TDES0[14] flag to assert. + * |[4] |OVF |Receive Overflow + * | | |This bit indicates that the Receive Buffer had an Overflow during frame reception + * | | |If the partial frame is transferred to the application, the overflow status is set in RDES0[11]. + * |[5] |UNF |Transmit Underflow + * | | |This bit indicates that the Transmit Buffer had an Underflow during frame transmission + * | | |Transmission is suspended and an Underflow Error TDES0[1] is set. + * |[6] |RI |Receive Interrupt + * | | |This bit indicates that the frame reception is complete + * | | |When reception is complete, the Bit 31 of RDES1 (Disable Interrupt on Completion) is reset in the last Descriptor, and the specific frame status information is updated in the descriptor + * | | |The reception remains in the Running state. + * |[7] |RU |Receive Buffer Unavailable + * | | |This bit indicates that the host owns the Next Descriptor in the Receive List and the DMA cannot acquire it + * | | |The Receive Process is suspended + * | | |To resume processing Receive descriptors, the host should change the ownership of the descriptor and issue a Receive Poll Demand command + * | | |If no Receive Poll Demand is issued, the Receive Process resumes when the next recognized incoming frame is received + * | | |This bit is set only when the previous Receive Descriptor is owned by the DMA. + * |[8] |RPS |Receive Process Stopped + * | | |This bit is asserted when the Receive Process enters the Stopped state. + * |[9] |RWT |Receive Watchdog Timeout + * | | |When set, this bit indicates that the Receive Watchdog Timer expired while receiving the current frame and the current frame is truncated after the watchdog timeout. + * |[10] |ETI |Early Transmit Interrupt + * | | |This bit indicates that the frame to be transmitted is fully transferred to the MTL Transmit FIFO. + * |[13] |FBI |Fatal Bus Error Interrupt + * | | |This bit indicates that a bus error occurred, as described in Bits[25:23] + * | | |When this bit is set, the corresponding DMA engine disables all of its bus accesses. + * |[14] |ERI |Early Receive Interrupt + * | | |This bit indicates that the DMA filled the first data buffer of the packet + * | | |This bit is cleared when the software writes 1 to this bit or Bit 6 (RI) of this register is set (whichever occurs earlier). + * |[15] |AIS |Abnormal Interrupt Summary + * | | |Abnormal Interrupt Summary bit value is the logical OR of the following when the corresponding interrupt bits are enabled in Register 1007 (Interrupt Enable Register): + * | | |Register 1005[1]: Transmit Process Stopped + * | | |Register 1005[3]: Transmit Jabber Timeout + * | | |Register 1005[4]: Receive FIFO Overflow + * | | |Register 1005[5]: Transmit Underflow + * | | |Register 1005[7]: Receive Buffer Unavailable + * | | |Register 1005[8]: Receive Process Stopped + * | | |Register 1005[9]: Receive Watchdog Timeout + * | | |Register 1005[10]: Early Transmit Interrupt + * | | |Register 1005[13]: Fatal Bus Error + * | | |Only unmasked bits affect the Abnormal Interrupt Summary bit. + * | | |This is a sticky bit and must be cleared each time a corresponding bit, which causes AIS to be set, is cleared. + * |[16] |NIS |Normal Interrupt Summary + * | | |Normal Interrupt Summary bit value is the logical OR of the following when the corresponding interrupt bits are enabled in Register 1007 (Interrupt Enable Register): + * | | |Register 1005[0]: Transmit Interrupt + * | | |Register 1005[2]: Transmit Buffer Unavailable + * | | |Register 1005[6]: Receive Interrupt + * | | |Register 1005[14]: Early Receive Interrupt + * | | |Only unmasked bits (interrupts for which interrupt enable is set in Register 1007) affect the Normal Interrupt Summary bit. + * | | |This is a sticky bit and must be cleared (by writing 1 to this bit) each time a corresponding bit, which causes NIS to be set, is cleared. + * |[19:17] |RS |Received Process State (read only) + * | | |This field indicates the Receive DMA FSM state. This field does not generate an interrupt. + * | | |3'b000: Stopped: Reset or Stop Receive Command issued + * | | |3'b001: Running: Fetching Receive Transfer Descriptor + * | | |3'b010: Reserved for future use + * | | |3'b011: Running: Waiting for receive packet + * | | |3'b100: Suspended: Receive Descriptor Unavailable + * | | |3'b101: Running: Closing Receive Descriptor + * | | |3'b110: TIME_STAMP write state + * | | |3'b111: Running: Transferring the receive packet data from receive buffer to host memory + * |[22:20] |TS |Transmit Process State (read only) + * | | |This field indicates the Transmit DMA FSM state. This field does not generate an interrupt. + * | | |3'b000: Stopped; Reset or Stop Transmit Command issued + * | | |3'b001: Running; Fetching Transmit Transfer Descriptor + * | | |3'b010: Running; Waiting for status + * | | |3'b011: Running; Reading Data from host memory buffer and queuing it to transmit buffer (Tx FIFO) + * | | |3'b100: TIME_STAMP write state + * | | |3'b101: Reserved for future use + * | | |3'b110: Suspended; Transmit Descriptor Unavailable or Transmit Buffer Underflow + * | | |3'b111: Running; Closing Transmit Descriptor + * |[25:23] |EB |Error Bits (read only) + * | | |This field indicates the type of error that caused a Bus Error, for example, error response on the AHB or AXI interface + * | | |This field is valid only when Bit 13 (FBI) is set + * | | |This field does not generate an interrupt. + * | | |0 0 0: Error during Rx DMA Write Data Transfer + * | | |0 1 1: Error during Tx DMA Read Data Transfer + * | | |1 0 0: Error during Rx DMA Descriptor Write Access + * | | |1 0 1: Error during Tx DMA Descriptor Write Access + * | | |1 1 0: Error during Rx DMA Descriptor Read Access + * | | |1 1 1: Error during Tx DMA Descriptor Read Access + * | | |Note: 001 and 010 are reserved. + * |[26] |GLI |GMAC Line interface Interrupt (read only) + * | | |When set, this bit reflects any of the following interrupt events in the GMAC interfaces: + * | | |RGMII: Link change event + * | | |To identify the exact cause of the interrupt, the software must first read Bit 11 and Bits[2:0] of Register 14 (Interrupt Status Register) and then to clear the source of interrupt (which also clears the GLI interrupt), read any of the following corresponding registers: + * | | |RGMII: Register 54 (RGMII Status Register) + * | | |The interrupt signal from the GMAC subsystem (sbd_intr_o) is high when this bit is high. + * |[28] |GPI |GMAC PMT Interrupt (read only) + * | | |This bit indicates an interrupt event in the PMT module of the GMAC + * | | |The software must read the PMT Control and Status Register in the MAC to get the exact cause of interrupt and clear its source to reset this bit to 1'b0 + * | | |The interrupt signal from the GMAC subsystem (sbd_intr_o) is high when this bit is high. + * | | |This bit is applicable only when the Power Management feature is enabled + * | | |Otherwise, this bit is reserved. + * | | |Note: The GPI and pmt_intr_o interrupts are generated in different clock domains. + * |[29] |TTI |Timestamp Trigger Interrupt (read only) + * | | |This bit indicates an interrupt event in the Timestamp Generator block of GMAC + * | | |The software must read the corresponding registers in the GMAC to get the exact cause of interrupt and clear its source to reset this bit to 1'b0 + * | | |When this bit is high, the interrupt signal from the GMAC subsystem (sbd_intr_o) is high. + * | | |This bit is applicable only when the IEEE 1588 Timestamp feature is enabled + * | | |Otherwise, this bit is reserved. + * |[30] |GLPII |GMAC LPI Interrupt (for Channel 0) (read only) + * | | |This bit indicates an interrupt event in the LPI logic of the GMAC + * | | |To reset this bit to 1'b0, the software must read the corresponding registers in the GMAC to get the exact cause of the interrupt and clear its source. + * | | |Note: GLPII status is given only in Channel 0 DMA register and is applicable only when the Energy Efficient Ethernet feature is enabled + * | | |Otherwise, this bit is reserved + * | | |When this bit is high, the interrupt signal from the MAC (sbd_intr_o) is high. + * @var GMACDMA_T::OPMODE + * Offset: 0x0018 Register 1006 (Operation Mode Register) + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[1] |SR |Start or Stop Receive + * | | |When this bit is set, the Receive process is placed in the Running state + * | | |The DMA attempts to acquire the descriptor from the Receive list and processes the incoming frames + * | | |The descriptor acquisition is attempted from the current position in the list, which is the address set by Register 1003 (Receive Descriptor List Address Register) or the position retained when the Receive process was previously stopped + * | | |If the DMA does not own the descriptor, reception is suspended and Bit 7 (Receive Buffer Unavailable) of Register 1005 (Status Register) is set + * | | |The Start Receive command is effective only when the reception has stopped + * | | |If the command is issued before setting Register 1003 (Receive Descriptor List Address Register), the DMA behavior is unpredictable. + * | | |When this bit is cleared, the Rx DMA operation is stopped after the transfer of the current frame + * | | |The next descriptor position in the Receive list is saved and becomes the current position after the Receive process is restarted + * | | |The Stop Receive command is effective only when the Receive process is in either the Running (waiting for receive packet) or in the Suspended state. + * |[2] |OSF |Operate on Second Frame + * | | |When this bit is set, it instructs the DMA to process the second frame of the Transmit data even before the status for the first frame is obtained. + * |[4:3] |RTC |Receive Threshold Control + * | | |These two bits control the threshold level of the MTL Receive FIFO + * | | |Transfer (request) to DMA starts when the frame size within the MTL Receive FIFO is larger than the threshold + * | | |In addition, full frames with length less than the threshold are transferred automatically. + * | | |These bits are valid only when the RSF bit is zero, and are ignored when the RSF bit is set to 1. + * | | |00: 64 + * | | |01: 32 + * | | |10: 96 + * | | |11: 128 + * |[5] |DGF |Drop Giant Frames + * | | |When set, the MAC drops the received giant frames in the Rx FIFO, that is, frames that are larger than the computed giant frame limit + * | | |When reset, the MAC does not drop the giant frames in the Rx FIFO. + * |[6] |FUF |Forward Undersized Good Frames + * | | |When set, the Rx FIFO forwards Undersized frames (frames with no Error and length less than 64 bytes) including pad-bytes and CRC. + * | | |When reset, the Rx FIFO drops all frames of less than 64 bytes, unless a frame is already transferred because of the lower value of Receive Threshold, for example, RTC = 01. + * |[7] |FEF |Forward Error Frames + * | | |When this bit is reset, the Rx FIFO drops frames with error status (CRC error, collision error, GMII_ER, giant frame, watchdog timeout, or overflow) + * | | |However, if the start byte (write) pointer of a frame is already transferred to the read controller side (in Threshold mode), then the frame is not dropped + * | | |When the FEF bit is set, all frames except runt error frames are forwarded to the DMA + * | | |If the Bit 25 (RSF) is set and the Rx FIFO overflows when a partial frame is written, then the frame is dropped irrespective of the FEF bit setting + * | | |However, if the Bit 25 (RSF) is reset and the Rx FIFO overflows when a partial frame is written, then a partial frame may be forwarded to the DMA. + * |[8] |EFC |Enable HW Flow Control + * | | |When this bit is set, the flow control signal operation based on the fill-level of Rx FIFO is enabled + * | | |When reset, the flow control operation is disabled + * | | |This bit is not used (reserved and always reset) when the Rx FIFO is less than 4 KB. + * |[10:9] |RFA |Threshold for Activating Flow Control (in half-duplex and full-duplex) + * | | |These bits control the threshold (Fill level of Rx FIFO) at which the flow control is activated. + * | | |00: Full minus 1 KB, that is, FULL - 1KB + * | | |01: Full minus 2 KB, that is, FULL - 2KB + * | | |10: Full minus 3 KB, that is, FULL - 3KB + * | | |11: Full minus 4 KB, that is, FULL - 4KB + * | | |These values are applicable only to Rx FIFOs of 4 KB or more and when Bit 8 (EFC) is set high + * | | |If the Rx FIFO is 8 KB or more, an additional Bit (RFA_2) is used for more threshold levels as described in Bit 23 + * | | |These bits are reserved and read-only when the depth of Rx FIFO is less than 4 KB. + * | | |Note: When FIFO size is exactly 4 KB, although the GMAC allows you to program the value of these bits to 11, the software should not program these bits to 2'b11 + * | | |The value 2'b11 means flow control on FIFO empty condition. + * |[12:11] |RFD |Threshold for Deactivating Flow Control (in half-duplex and full-duplex) + * | | |These bits control the threshold (Fill-level of Rx FIFO) at which the flow control is de-asserted after activation. + * | | |00: Full minus 1 KB, that is, FULL - 1KB + * | | |01: Full minus 2 KB, that is, FULL - 2KB + * | | |10: Full minus 3 KB, that is, FULL - 3KB + * | | |11: Full minus 4 KB, that is, FULL - 4KB + * | | |The de-assertion is effective only after flow control is asserted + * | | |If the Rx FIFO is 8 KB or more, an additional bit (RFD_2) is used for more threshold levels as described in Bit 22 + * | | |These bits are reserved and read-only when the Rx FIFO depth is less than 4 KB + * | | |Note: For proper flow control, the value programmed in the "RFD_2, RFD" fields should be equal to or more than the value programmed in the "RFA_2, RFA" fields. + * |[13] |ST |Start or Stop Transmission Command + * | | |When this bit is set, transmission is placed in the Running state, and the DMA checks the Transmit List at the current position for a frame to be transmitted + * | | |Descriptor acquisition is attempted either from the current position in the list, which is the Transmit List Base Address set by Register 1004 (Transmit Descriptor List Address Register), or from the position retained when transmission was stopped previously + * | | |If the DMA does not own the current descriptor, transmission enters the Suspended state and Bit 2 (Transmit Buffer Unavailable) of Register 1005 (Status Register) is set + * | | |The Start Transmission command is effective only when transmission is stopped + * | | |If the command is issued before setting Register 1004 (Transmit Descriptor List Address Register), then the DMA behavior is unpredictable. + * | | |When this bit is reset, the transmission process is placed in the Stopped state after completing the transmission of the current frame + * | | |The Next Descriptor position in the Transmit List is saved, and it becomes the current position when transmission is restarted + * | | |To change the list address, you need to program Register 1004 (Transmit Descriptor List Address Register) with a new value when this bit is reset + * | | |The new value is considered when this bit is set again + * | | |The stop transmission command is effective only when the transmission of the current frame is complete or the transmission is in the Suspended state. + * |[16:14] |TTC |Transmit Threshold Control + * | | |These bits control the threshold level of the MTL Transmit FIFO + * | | |Transmission starts when the frame size within the MTL Transmit FIFO is larger than the threshold + * | | |In addition, full frames with a length less than the threshold are also transmitted + * | | |These bits are used only when Bit 21 (TSF) is reset. + * | | |000: 64 + * | | |001: 128 + * | | |010: 192 + * | | |011: 256 + * | | |100: 40 + * | | |101: 32 + * | | |110: 24 + * | | |111: 16 + * |[20] |FTF |Flush Transmit FIFO + * | | |When this bit is set, the transmit FIFO controller logic is reset to its default values and thus all data in the Tx FIFO is lost or flushed + * | | |This bit is cleared internally when the flushing operation is completed + * | | |The Operation Mode register should not be written to until this bit is cleared + * | | |The data which is already accepted by the MAC transmitter is not flushed + * | | |It is scheduled for transmission and results in underflow and runt frame transmission. + * | | |Note: The flush operation is complete only when the Tx FIFO is emptied of its contents and all the pending Transmit Status of the transmitted frames are accepted by the host + * | | |To complete this flush operation, the PHY transmit clock (clk_tx_i) is required to be active. + * |[21] |TSF |Transmit Store and Forward + * | | |When this bit is set, transmission starts when a full frame resides in the MTL Transmit FIFO + * | | |When this bit is set, the TTC values specified in Bits[16:14] are ignored + * | | |This bit should be changed only when the transmission is stopped. + * |[24] |DFF |Disable Flushing of Received Frames + * | | |When this bit is set, the Rx DMA does not flush any frames because of the unavailability of receive descriptors or buffers as it does normally when this bit is reset + * |[25] |RSF |Receive Store and Forward + * | | |When this bit is set, the MTL reads a frame from the Rx FIFO only after the complete frame has been written to it, ignoring the RTC bits + * | | |When this bit is reset, the Rx FIFO operates in the cut-through mode, subject to the threshold specified by the RTC bits + * |[26] |DT |Disable Dropping of TCP/IP Checksum Error Frames + * | | |When this bit is set, the MAC does not drop the frames which only have errors detected by the Receive Checksum Offload engine + * | | |Such frames do not have any errors (including FCS error) in the Ethernet frame received by the MAC but have errors only in the encapsulated payload + * | | |When this bit is reset, all error frames are dropped if the FEF bit is reset. + * | | |If the IPC Full Checksum Offload Engine (Type 2) is disabled, this bit is reserved (RO with value 1'b0). + * @var GMACDMA_T::INTEN + * Offset: 0x001C Register 1007 (Interrupt Enable Register) + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[0] |TIE |Transmit Interrupt Enable + * | | |When this bit is set with Normal Interrupt Summary Enable (Bit 16), the Transmit Interrupt is enabled + * | | |When this bit is reset, the Transmit Interrupt is disabled. + * |[1] |TSE |Transmit Stopped Enable + * | | |When this bit is set with Abnormal Interrupt Summary Enable (Bit 15), the Transmission Stopped Interrupt is enabled + * | | |When this bit is reset, the Transmission Stopped Interrupt is disabled. + * |[2] |TUE |Transmit Buffer Unavailable Enable + * | | |When this bit is set with Normal Interrupt Summary Enable (Bit 16), the Transmit Buffer Unavailable Interrupt is enabled + * | | |When this bit is reset, the Transmit Buffer Unavailable Interrupt is disabled. + * |[3] |TJE |Transmit Jabber Timeout Enable + * | | |When this bit is set with Abnormal Interrupt Summary Enable (Bit 15), the Transmit Jabber Timeout Interrupt is enabled + * | | |When this bit is reset, the Transmit Jabber Timeout Interrupt is disabled. + * |[4] |OVE |Overflow Interrupt Enable + * | | |When this bit is set with Abnormal Interrupt Summary Enable (Bit 15), the Receive Overflow Interrupt is enabled + * | | |When this bit is reset, the Overflow Interrupt is disabled. + * |[5] |UNE |Underflow Interrupt Enable + * | | |When this bit is set with Abnormal Interrupt Summary Enable (Bit 15), the Transmit Underflow Interrupt is enabled + * | | |When this bit is reset, the Underflow Interrupt is disabled. + * |[6] |RIE |Receive Interrupt Enable + * | | |When this bit is set with Normal Interrupt Summary Enable (Bit 16), the Receive Interrupt is enabled + * | | |When this bit is reset, the Receive Interrupt is disabled. + * |[7] |RUE |Receive Buffer Unavailable Enable + * | | |When this bit is set with Abnormal Interrupt Summary Enable (Bit 15), the Receive Buffer Unavailable Interrupt is enabled + * | | |When this bit is reset, the Receive Buffer Unavailable Interrupt is disabled. + * |[8] |RSE |Receive Stopped Enable + * | | |When this bit is set with Abnormal Interrupt Summary Enable (Bit 15), the Receive Stopped Interrupt is enabled + * | | |When this bit is reset, the Receive Stopped Interrupt is disabled. + * |[9] |RWE |Receive Watchdog Timeout Enable + * | | |When this bit is set with Abnormal Interrupt Summary Enable (Bit 15), the Receive Watchdog Timeout Interrupt is enabled + * | | |When this bit is reset, the Receive Watchdog Timeout Interrupt is disabled. + * |[10] |ETE |Early Transmit Interrupt Enable + * | | |When this bit is set with an Abnormal Interrupt Summary Enable (Bit 15), the Early Transmit Interrupt is enabled + * | | |When this bit is reset, the Early Transmit Interrupt is disabled. + * |[13] |FBE |Fatal Bus Error Enable + * | | |When this bit is set with Abnormal Interrupt Summary Enable (Bit 15), the Fatal Bus Error Interrupt is enabled + * | | |When this bit is reset, the Fatal Bus Error Enable Interrupt is disabled. + * |[14] |ERE |Early Receive Interrupt Enable + * | | |When this bit is set with Normal Interrupt Summary Enable (Bit 16), the Early Receive Interrupt is enabled + * | | |When this bit is reset, the Early Receive Interrupt is disabled. + * |[15] |AIE |Abnormal Interrupt Summary Enable + * | | |When this bit is set, abnormal interrupt summary is enabled + * | | |When this bit is reset, the abnormal interrupt summary is disabled + * | | |This bit enables the following interrupts in Register 1005 (Status Register): + * | | |Register 1005[1]: Transmit Process Stopped + * | | |Register 1005[3]: Transmit Jabber Timeout + * | | |Register 1005[4]: Receive Overflow + * | | |Register 1005[5]: Transmit Underflow + * | | |Register 1005[7]: Receive Buffer Unavailable + * | | |Register 1005[8]: Receive Process Stopped + * | | |Register 1005[9]: Receive Watchdog Timeout + * | | |Register 1005[10]: Early Transmit Interrupt + * | | |Register 1005[13]: Fatal Bus Error + * |[16] |NIE |Normal Interrupt Summary Enable + * | | |When this bit is set, normal interrupt summary is enabled + * | | |When this bit is reset, normal interrupt summary is disabled + * | | |This bit enables the following interrupts in Register 1005 (Status Register): + * | | |Register 1005[0]: Transmit Interrupt + * | | |Register 1005[2]: Transmit Buffer Unavailable + * | | |Register 1005[6]: Receive Interrupt + * | | |Register 1005[14]: Early Receive Interrupt + * @var GMACDMA_T::MFOVCNTR + * Offset: 0x0020 Register 1008 (Missed Frame and Buffer Overflow Counter Register) + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[15:0] |MISFRMCNT |Missed Frame Counter + * | | |This field indicates the number of frames missed by the controller because of the Host Receive Buffer being unavailable + * | | |This counter is incremented each time the DMA discards an incoming frame + * | | |The counter is cleared when this register is read with mci_be_i[0] at 1'b1. + * |[16] |MISCNTOVF |Overflow Bit for Missed Frame Counter + * | | |This bit is set every time Missed Frame Counter (Bits[15:0]) overflows, that is, the DMA discards an incoming frame because of the Host Receive Buffer being unavailable with the missed frame counter at maximum value + * | | |In such a scenario, the Missed frame counter is reset to all-zeros and this bit indicates that the rollover happened. + * |[27:17] |OVFFRMCNT |Overflow Frame Counter + * | | |This field indicates the number of frames missed by the application + * | | |This counter is incremented each time the MTL FIFO overflows + * | | |The counter is cleared when this register is read with mci_be_i[2] at 1'b1. + * |[28] |OVFCNTOVF |Overflow Bit for FIFO Overflow Counter + * | | |This bit is set every time the Overflow Frame Counter (Bits[27:17]) overflows, that is, the Rx FIFO overflows with the overflow frame counter at maximum value + * | | |In such a scenario, the overflow frame counter is reset to all-zeros and this bit indicates that the rollover happened. + * @var GMACDMA_T::RXINTWDT + * Offset: 0x0024 Register 1009 (Receive Interrupt Watchdog Timer Register) + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[7:0] |RIWT |RI Watchdog Timer Count + * | | |This bit indicates the number of system clock cycles multiplied by 256 for which the watchdog timer is set + * | | |The watchdog timer gets triggered with the programmed value after the Rx DMA completes the transfer of a frame for which the RI status bit is not set because of the setting in the corresponding descriptor RDES1[31] + * | | |When the watchdog timer runs out, the RI bit is set and the timer is stopped + * | | |The watchdog timer is reset when the RI bit is set high because of automatic setting of RI as per RDES1[31] of any received frame. + * @var GMACDMA_T::AXIMODE + * Offset: 0x0028 Register 1010 (AXI Bus Mode Register) + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[0] |UNDEF |AXI Undefined Burst Length (read only) + * | | |This bit is read-only bit and indicates the complement (invert) value of Bit 16 (FB) in Register 1000 (Bus Mode Register[16]). + * | | |When this bit is set to 1, the GMAC-AXI is allowed to perform any burst length equal to or below the maximum allowed burst length programmed in Bits[7:1]. + * | | |When this bit is set to 0, the GMAC-AXI is allowed to perform only fixed burst lengths as indicated by BLEN256, BLEN128, BLEN64, BLEN32, BLEN16, BLEN8, or BLEN4, or a burst length of 1 + * |[1] |BLEN4 |AXI Burst Length 4 + * | | |When this bit is set to 1, the GMAC-AXI is allowed to select a burst length of 4 on the AXI Master interface. + * | | |Setting this bit has no effect when UNDEF is set to 1. + * |[2] |BLEN8 |AXI Burst Length 8 + * | | |When this bit is set to 1, the GMAC-AXI is allowed to select a burst length of 8 on the AXI Master interface. + * | | |Setting this bit has no effect when UNDEF is set to 1. + * |[3] |BLEN16 |AXI Burst Length 16 + * | | |When this bit is set to 1 or UNDEF is set to 1, the GMAC-AXI is allowed to select a burst length of 16 on the AXI Master interface. + * |[12] |AXI_AAL |Address-Aligned Beats (read only) + * | | |This bit is read-only bit and reflects the Bit 25 (AAL) of Register 1000 (Bus Mode Register). + * | | |When this bit is set to 1, the GMAC-AXI performs address-aligned burst transfers on both read and write channels. + * |[13] |ONEKBBE |1 KB Boundary Crossing Enable for the GMAC-AXI Master When set, the GMAC-AXI Master performs burst transfers that do not cross 1 KB boundary. When reset, the GMAC-AXI Master performs burst transfers that do not cross 4 KB boundary. + * |[17:16] |RD_OSR_LMT|AXI Maximum Read OutStanding Request Limit + * | | |This value limits the maximum outstanding request on the AXI read interface + * | | |Maximum outstanding requests = RD_OSR_LMT+1 + * | | |Note: The Bit 18 is reserved if AXI_GM_MAX_RD_REQUESTS = 4 + * | | |The Bit 19 is reserved if AXI_GM_MAX_RD_REQUESTS != 16. + * |[18] |RD_OSR_LMT_GT4|Reserved. + * |[19] |RD_OSR_LMT_GT8|Reserved. + * |[21:20] |WR_OSR_LMT|AXI Maximum Write OutStanding Request Limit + * |[22] |WR_OSR_LMT_GT4|Reserved. + * |[23] |WR_OSR_LMT_GT8|Reserved. + * |[30] |LPI_XIT_FRM|Unlock on Magic Packet or Remote Wake Up + * | | |When set to 1, this bit enables the GMAC-AXI to come out of the LPI mode only when the Magic Packet or Remote Wake Up Packet is received + * | | |When set to 0, this bit enables the GMAC-AXI to come out of LPI mode when any frame is received. + * |[31] |EN_LPI |Enable Low Power Interface (LPI) + * | | |When set to 1, this bit enables the LPI mode and accepts the LPI request from the AXI System Clock controller. + * | | |When set to 0, this bit disables the LPI mode and always denies the LPI request from the AXI System Clock controller. + * @var GMACDMA_T::BUSSTS + * Offset: 0x002C Register 1011 (AHB or AXI Status Register) + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[0] |AXWHSTS |AXI Master Write Channel or AHB Master Status + * | | |When high, it indicates that AXI Master's write channel is active and transferring data. + * |[1] |AXIRDSTS |AXI Master Read Channel Status + * | | |When high, it indicates that AXI Master's read channel is active and transferring data. + * @var GMACDMA_T::CTXDESC + * Offset: 0x0048 Register 1018 (Current Host Transmit Descriptor Register) + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[31:0] |CURTDESAPTR|Host Transmit Descriptor Address Pointer + * | | |Cleared on Reset. Pointer updated by the DMA during operation. + * @var GMACDMA_T::CRXDESC + * Offset: 0x004C Register 1019 (Current Host Receive Descriptor Register) + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[31:0] |CURRDESAPTR|Host Receive Descriptor Address Pointer + * | | |Cleared on Reset. Pointer updated by the DMA during operation. + * @var GMACDMA_T::CTXBUF + * Offset: 0x0050 Register 1020 (Current Host Transmit Buffer Address Register) + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[31:0] |CURTBUFAPTR|Host Transmit Buffer Address Pointer + * | | |Cleared on Reset. Pointer updated by the DMA during operation. + * @var GMACDMA_T::CRXBUF + * Offset: 0x0054 Register 1021 (Current Host Receive Buffer Address Register) + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[31:0] |CURRBUFAPTR|Host Receive Buffer Address Pointer + * | | |Cleared on Reset. Pointer updated by the DMA during operation. + * @var GMACDMA_T::HWFEAT + * Offset: 0x0058 Register 1022 (HW Feature Register) + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[0] |MIISEL |10 or 100 Mbps support + * |[1] |GMIISEL |1000 Mbps support + * |[2] |HDSEL |Half-Duplex support + * |[3] |EXTHASHEN |Expanded DA Hash Filter + * |[4] |HASHSEL |HASH Filter + * |[5] |ADDMACADRSEL|Multiple MAC Address Registers + * |[6] |PCSSEL |PCS registers (TBI, SGMII, or RTBI PHY interface) + * |[7] |L3L4FLTREN|Layer 3 and Layer 4 Filter Feature + * |[8] |SMASEL |SMA (MDIO) Interface + * |[9] |RWKSEL |PMT Remote Wakeup + * |[10] |MGKSEL |PMT Magic Packet + * |[11] |MMCSEL |RMON Module + * |[12] |TSVER1SEL |Only IEEE 1588-2002 Timestamp + * |[13] |TSVER2SEL |IEEE 1588-2008 Advanced Timestamp + * |[14] |EEESEL |Energy Efficient Ethernet + * |[15] |AVSEL |AV Feature + * |[16] |TXCOESEL |Checksum Offload in Tx + * |[17] |RXTYP1COE |Type 1 IP Checksum Offload (Type 1) in Rx + * | | |Note: If IPCHKSUM_EN = Enabled and IPC_FULL_OFFLOAD = Enabled, then RXTYP1COE = 0 and RXTYP2COE =1. + * |[18] |RXTYP2COE |Type 2 IP Checksum Offload (Type 2) in Rx + * |[19] |RXFIFOSIZE|Rx FIFO > 2,048 Bytes + * |[21:20] |RXCHCNT |Number of additional Rx channels + * |[23:22] |TXCHCNT |Number of additional Tx channels + * |[24] |ENHDESSEL |Alternate (Enhanced Descriptor) + * |[25] |INTTSEN |Timestamping with Internal System Time + * |[26] |FLEXIPPSEN|Flexible Pulse-Per-Second Output + * |[27] |SAVLANINS |Source Address or VLAN Insertion + * |[30:28] |ACTPHYIF |Active or Selected PHY interface + * | | |When you have multiple PHY interfaces in your configuration, this field indicates the sampled value of phy_intf_sel_i during reset de-assertion + * | | |0001: RGMII + * | | |0100: RMII + * | | |All Others: Reserved + */ + __IO uint32_t BUSMODE; /*!< [0x0000] Register 1000 (Bus Mode Register) */ + __IO uint32_t TXDEM; /*!< [0x0004] Register 1001 (Transmit Poll Demand Register) */ + __IO uint32_t RXDEM; /*!< [0x0008] Register 1002 (Receive Poll Demand Register) */ + __IO uint32_t RXDADDR; /*!< [0x000c] Register 1003 (Receive Descriptor List Address Register) */ + __IO uint32_t TXDADDR; /*!< [0x0010] Register 1004 (Transmit Descriptor List Address Register) */ + __IO uint32_t STS; /*!< [0x0014] Register 1005 (Status Register) */ + __IO uint32_t OPMODE; /*!< [0x0018] Register 1006 (Operation Mode Register) */ + __IO uint32_t INTEN; /*!< [0x001c] Register 1007 (Interrupt Enable Register) */ + __I uint32_t MFOVCNTR; /*!< [0x0020] Register 1008 (Missed Frame and Buffer Overflow Counter Register)*/ + __IO uint32_t RXINTWDT; /*!< [0x0024] Register 1009 (Receive Interrupt Watchdog Timer Register) */ + __IO uint32_t AXIMODE; /*!< [0x0028] Register 1010 (AXI Bus Mode Register) */ + __I uint32_t BUSSTS; /*!< [0x002c] Register 1011 (AHB or AXI Status Register) */ + __I uint32_t RESERVE0[6]; + __I uint32_t CTXDESC; /*!< [0x0048] Register 1018 (Current Host Transmit Descriptor Register) */ + __I uint32_t CRXDESC; /*!< [0x004c] Register 1019 (Current Host Receive Descriptor Register) */ + __I uint32_t CTXBUF; /*!< [0x0050] Register 1020 (Current Host Transmit Buffer Address Register) */ + __I uint32_t CRXBUF; /*!< [0x0054] Register 1021 (Current Host Receive Buffer Address Register) */ + __I uint32_t HWFEAT; /*!< [0x0058] Register 1022 (HW Feature Register) */ + +} GMACDMA_T; + + +/** + @addtogroup GMACDMA_CONST GMACDMA Bit Field Definition + Constant Definitions for GMACDMA +@{ */ +#define GMACDMA_BUSMODE_SWR_Pos (0) /*!< GMACDMA_T::BUSMODE: SWR Position */ +#define GMACDMA_BUSMODE_SWR_Msk (0x1ul << GMACDMA_BUSMODE_SWR_Pos) /*!< GMACDMA_T::BUSMODE: SWR Mask */ + +#define GMACDMA_BUSMODE_DSL_Pos (2) /*!< GMACDMA_T::BUSMODE: DSL Position */ +#define GMACDMA_BUSMODE_DSL_Msk (0x1ful << GMACDMA_BUSMODE_DSL_Pos) /*!< GMACDMA_T::BUSMODE: DSL Mask */ + +#define GMACDMA_BUSMODE_ATDS_Pos (7) /*!< GMACDMA_T::BUSMODE: ATDS Position */ +#define GMACDMA_BUSMODE_ATDS_Msk (0x1ul << GMACDMA_BUSMODE_ATDS_Pos) /*!< GMACDMA_T::BUSMODE: ATDS Mask */ + +#define GMACDMA_BUSMODE_PBL_Pos (8) /*!< GMACDMA_T::BUSMODE: PBL Position */ +#define GMACDMA_BUSMODE_PBL_Msk (0x3ful << GMACDMA_BUSMODE_PBL_Pos) /*!< GMACDMA_T::BUSMODE: PBL Mask */ + +#define GMACDMA_BUSMODE_FB_Pos (16) /*!< GMACDMA_T::BUSMODE: FB Position */ +#define GMACDMA_BUSMODE_FB_Msk (0x1ul << GMACDMA_BUSMODE_FB_Pos) /*!< GMACDMA_T::BUSMODE: FB Mask */ + +#define GMACDMA_BUSMODE_RPBL_Pos (17) /*!< GMACDMA_T::BUSMODE: RPBL Position */ +#define GMACDMA_BUSMODE_RPBL_Msk (0x3ful << GMACDMA_BUSMODE_RPBL_Pos) /*!< GMACDMA_T::BUSMODE: RPBL Mask */ + +#define GMACDMA_BUSMODE_USP_Pos (23) /*!< GMACDMA_T::BUSMODE: USP Position */ +#define GMACDMA_BUSMODE_USP_Msk (0x1ul << GMACDMA_BUSMODE_USP_Pos) /*!< GMACDMA_T::BUSMODE: USP Mask */ + +#define GMACDMA_BUSMODE_PBLx8_Pos (24) /*!< GMACDMA_T::BUSMODE: PBLx8 Position */ +#define GMACDMA_BUSMODE_PBLx8_Msk (0x1ul << GMACDMA_BUSMODE_PBLx8_Pos) /*!< GMACDMA_T::BUSMODE: PBLx8 Mask */ + +#define GMACDMA_BUSMODE_AAL_Pos (25) /*!< GMACDMA_T::BUSMODE: AAL Position */ +#define GMACDMA_BUSMODE_AAL_Msk (0x1ul << GMACDMA_BUSMODE_AAL_Pos) /*!< GMACDMA_T::BUSMODE: AAL Mask */ + +#define GMACDMA_TXDEM_TPD_Pos (0) /*!< GMACDMA_T::TXDEM: TPD Position */ +#define GMACDMA_TXDEM_TPD_Msk (0xfffffffful << GMACDMA_TXDEM_TPD_Pos) /*!< GMACDMA_T::TXDEM: TPD Mask */ + +#define GMACDMA_RXDEM_RPD_Pos (0) /*!< GMACDMA_T::RXDEM: RPD Position */ +#define GMACDMA_RXDEM_RPD_Msk (0xfffffffful << GMACDMA_RXDEM_RPD_Pos) /*!< GMACDMA_T::RXDEM: RPD Mask */ + +#define GMACDMA_RXDADDR_RDESLA_64_bit_Pos (3) /*!< GMACDMA_T::RXDADDR: RDESLA_64_bit Position */ +#define GMACDMA_RXDADDR_RDESLA_64_bit_Msk (0x1ffffffful << GMACDMA_RXDADDR_RDESLA_64_bit_Pos) /*!< GMACDMA_T::RXDADDR: RDESLA_64_bit Mask */ + +#define GMACDMA_TXDADDR_TDESLA_64_bit_Pos (3) /*!< GMACDMA_T::TXDADDR: TDESLA_64_bit Position */ +#define GMACDMA_TXDADDR_TDESLA_64_bit_Msk (0x1ffffffful << GMACDMA_TXDADDR_TDESLA_64_bit_Pos) /*!< GMACDMA_T::TXDADDR: TDESLA_64_bit Mask */ + +#define GMACDMA_STS_TI_Pos (0) /*!< GMACDMA_T::STS: TI Position */ +#define GMACDMA_STS_TI_Msk (0x1ul << GMACDMA_STS_TI_Pos) /*!< GMACDMA_T::STS: TI Mask */ + +#define GMACDMA_STS_TPS_Pos (1) /*!< GMACDMA_T::STS: TPS Position */ +#define GMACDMA_STS_TPS_Msk (0x1ul << GMACDMA_STS_TPS_Pos) /*!< GMACDMA_T::STS: TPS Mask */ + +#define GMACDMA_STS_TU_Pos (2) /*!< GMACDMA_T::STS: TU Position */ +#define GMACDMA_STS_TU_Msk (0x1ul << GMACDMA_STS_TU_Pos) /*!< GMACDMA_T::STS: TU Mask */ + +#define GMACDMA_STS_TJT_Pos (3) /*!< GMACDMA_T::STS: TJT Position */ +#define GMACDMA_STS_TJT_Msk (0x1ul << GMACDMA_STS_TJT_Pos) /*!< GMACDMA_T::STS: TJT Mask */ + +#define GMACDMA_STS_OVF_Pos (4) /*!< GMACDMA_T::STS: OVF Position */ +#define GMACDMA_STS_OVF_Msk (0x1ul << GMACDMA_STS_OVF_Pos) /*!< GMACDMA_T::STS: OVF Mask */ + +#define GMACDMA_STS_UNF_Pos (5) /*!< GMACDMA_T::STS: UNF Position */ +#define GMACDMA_STS_UNF_Msk (0x1ul << GMACDMA_STS_UNF_Pos) /*!< GMACDMA_T::STS: UNF Mask */ + +#define GMACDMA_STS_RI_Pos (6) /*!< GMACDMA_T::STS: RI Position */ +#define GMACDMA_STS_RI_Msk (0x1ul << GMACDMA_STS_RI_Pos) /*!< GMACDMA_T::STS: RI Mask */ + +#define GMACDMA_STS_RU_Pos (7) /*!< GMACDMA_T::STS: RU Position */ +#define GMACDMA_STS_RU_Msk (0x1ul << GMACDMA_STS_RU_Pos) /*!< GMACDMA_T::STS: RU Mask */ + +#define GMACDMA_STS_RPS_Pos (8) /*!< GMACDMA_T::STS: RPS Position */ +#define GMACDMA_STS_RPS_Msk (0x1ul << GMACDMA_STS_RPS_Pos) /*!< GMACDMA_T::STS: RPS Mask */ + +#define GMACDMA_STS_RWT_Pos (9) /*!< GMACDMA_T::STS: RWT Position */ +#define GMACDMA_STS_RWT_Msk (0x1ul << GMACDMA_STS_RWT_Pos) /*!< GMACDMA_T::STS: RWT Mask */ + +#define GMACDMA_STS_ETI_Pos (10) /*!< GMACDMA_T::STS: ETI Position */ +#define GMACDMA_STS_ETI_Msk (0x1ul << GMACDMA_STS_ETI_Pos) /*!< GMACDMA_T::STS: ETI Mask */ + +#define GMACDMA_STS_FBI_Pos (13) /*!< GMACDMA_T::STS: FBI Position */ +#define GMACDMA_STS_FBI_Msk (0x1ul << GMACDMA_STS_FBI_Pos) /*!< GMACDMA_T::STS: FBI Mask */ + +#define GMACDMA_STS_ERI_Pos (14) /*!< GMACDMA_T::STS: ERI Position */ +#define GMACDMA_STS_ERI_Msk (0x1ul << GMACDMA_STS_ERI_Pos) /*!< GMACDMA_T::STS: ERI Mask */ + +#define GMACDMA_STS_AIS_Pos (15) /*!< GMACDMA_T::STS: AIS Position */ +#define GMACDMA_STS_AIS_Msk (0x1ul << GMACDMA_STS_AIS_Pos) /*!< GMACDMA_T::STS: AIS Mask */ + +#define GMACDMA_STS_NIS_Pos (16) /*!< GMACDMA_T::STS: NIS Position */ +#define GMACDMA_STS_NIS_Msk (0x1ul << GMACDMA_STS_NIS_Pos) /*!< GMACDMA_T::STS: NIS Mask */ + +#define GMACDMA_STS_RS_Pos (17) /*!< GMACDMA_T::STS: RS Position */ +#define GMACDMA_STS_RS_Msk (0x7ul << GMACDMA_STS_RS_Pos) /*!< GMACDMA_T::STS: RS Mask */ + +#define GMACDMA_STS_TS_Pos (20) /*!< GMACDMA_T::STS: TS Position */ +#define GMACDMA_STS_TS_Msk (0x7ul << GMACDMA_STS_TS_Pos) /*!< GMACDMA_T::STS: TS Mask */ + +#define GMACDMA_STS_EB_Pos (23) /*!< GMACDMA_T::STS: EB Position */ +#define GMACDMA_STS_EB_Msk (0x7ul << GMACDMA_STS_EB_Pos) /*!< GMACDMA_T::STS: EB Mask */ + +#define GMACDMA_STS_GLI_Pos (26) /*!< GMACDMA_T::STS: GLI Position */ +#define GMACDMA_STS_GLI_Msk (0x1ul << GMACDMA_STS_GLI_Pos) /*!< GMACDMA_T::STS: GLI Mask */ + +#define GMACDMA_STS_GPI_Pos (28) /*!< GMACDMA_T::STS: GPI Position */ +#define GMACDMA_STS_GPI_Msk (0x1ul << GMACDMA_STS_GPI_Pos) /*!< GMACDMA_T::STS: GPI Mask */ + +#define GMACDMA_STS_TTI_Pos (29) /*!< GMACDMA_T::STS: TTI Position */ +#define GMACDMA_STS_TTI_Msk (0x1ul << GMACDMA_STS_TTI_Pos) /*!< GMACDMA_T::STS: TTI Mask */ + +#define GMACDMA_STS_GLPII_Pos (30) /*!< GMACDMA_T::STS: GLPII Position */ +#define GMACDMA_STS_GLPII_Msk (0x1ul << GMACDMA_STS_GLPII_Pos) /*!< GMACDMA_T::STS: GLPII Mask */ + +#define GMACDMA_OPMODE_SR_Pos (1) /*!< GMACDMA_T::OPMODE: SR Position */ +#define GMACDMA_OPMODE_SR_Msk (0x1ul << GMACDMA_OPMODE_SR_Pos) /*!< GMACDMA_T::OPMODE: SR Mask */ + +#define GMACDMA_OPMODE_OSF_Pos (2) /*!< GMACDMA_T::OPMODE: OSF Position */ +#define GMACDMA_OPMODE_OSF_Msk (0x1ul << GMACDMA_OPMODE_OSF_Pos) /*!< GMACDMA_T::OPMODE: OSF Mask */ + +#define GMACDMA_OPMODE_RTC_Pos (3) /*!< GMACDMA_T::OPMODE: RTC Position */ +#define GMACDMA_OPMODE_RTC_Msk (0x3ul << GMACDMA_OPMODE_RTC_Pos) /*!< GMACDMA_T::OPMODE: RTC Mask */ + +#define GMACDMA_OPMODE_DGF_Pos (5) /*!< GMACDMA_T::OPMODE: DGF Position */ +#define GMACDMA_OPMODE_DGF_Msk (0x1ul << GMACDMA_OPMODE_DGF_Pos) /*!< GMACDMA_T::OPMODE: DGF Mask */ + +#define GMACDMA_OPMODE_FUF_Pos (6) /*!< GMACDMA_T::OPMODE: FUF Position */ +#define GMACDMA_OPMODE_FUF_Msk (0x1ul << GMACDMA_OPMODE_FUF_Pos) /*!< GMACDMA_T::OPMODE: FUF Mask */ + +#define GMACDMA_OPMODE_FEF_Pos (7) /*!< GMACDMA_T::OPMODE: FEF Position */ +#define GMACDMA_OPMODE_FEF_Msk (0x1ul << GMACDMA_OPMODE_FEF_Pos) /*!< GMACDMA_T::OPMODE: FEF Mask */ + +#define GMACDMA_OPMODE_EFC_Pos (8) /*!< GMACDMA_T::OPMODE: EFC Position */ +#define GMACDMA_OPMODE_EFC_Msk (0x1ul << GMACDMA_OPMODE_EFC_Pos) /*!< GMACDMA_T::OPMODE: EFC Mask */ + +#define GMACDMA_OPMODE_RFA_Pos (9) /*!< GMACDMA_T::OPMODE: RFA Position */ +#define GMACDMA_OPMODE_RFA_Msk (0x3ul << GMACDMA_OPMODE_RFA_Pos) /*!< GMACDMA_T::OPMODE: RFA Mask */ + +#define GMACDMA_OPMODE_RFD_Pos (11) /*!< GMACDMA_T::OPMODE: RFD Position */ +#define GMACDMA_OPMODE_RFD_Msk (0x3ul << GMACDMA_OPMODE_RFD_Pos) /*!< GMACDMA_T::OPMODE: RFD Mask */ + +#define GMACDMA_OPMODE_ST_Pos (13) /*!< GMACDMA_T::OPMODE: ST Position */ +#define GMACDMA_OPMODE_ST_Msk (0x1ul << GMACDMA_OPMODE_ST_Pos) /*!< GMACDMA_T::OPMODE: ST Mask */ + +#define GMACDMA_OPMODE_TTC_Pos (14) /*!< GMACDMA_T::OPMODE: TTC Position */ +#define GMACDMA_OPMODE_TTC_Msk (0x7ul << GMACDMA_OPMODE_TTC_Pos) /*!< GMACDMA_T::OPMODE: TTC Mask */ + +#define GMACDMA_OPMODE_FTF_Pos (20) /*!< GMACDMA_T::OPMODE: FTF Position */ +#define GMACDMA_OPMODE_FTF_Msk (0x1ul << GMACDMA_OPMODE_FTF_Pos) /*!< GMACDMA_T::OPMODE: FTF Mask */ + +#define GMACDMA_OPMODE_TSF_Pos (21) /*!< GMACDMA_T::OPMODE: TSF Position */ +#define GMACDMA_OPMODE_TSF_Msk (0x1ul << GMACDMA_OPMODE_TSF_Pos) /*!< GMACDMA_T::OPMODE: TSF Mask */ + +#define GMACDMA_OPMODE_DFF_Pos (24) /*!< GMACDMA_T::OPMODE: DFF Position */ +#define GMACDMA_OPMODE_DFF_Msk (0x1ul << GMACDMA_OPMODE_DFF_Pos) /*!< GMACDMA_T::OPMODE: DFF Mask */ + +#define GMACDMA_OPMODE_RSF_Pos (25) /*!< GMACDMA_T::OPMODE: RSF Position */ +#define GMACDMA_OPMODE_RSF_Msk (0x1ul << GMACDMA_OPMODE_RSF_Pos) /*!< GMACDMA_T::OPMODE: RSF Mask */ + +#define GMACDMA_OPMODE_DT_Pos (26) /*!< GMACDMA_T::OPMODE: DT Position */ +#define GMACDMA_OPMODE_DT_Msk (0x1ul << GMACDMA_OPMODE_DT_Pos) /*!< GMACDMA_T::OPMODE: DT Mask */ + +#define GMACDMA_INTEN_TIE_Pos (0) /*!< GMACDMA_T::INTEN: TIE Position */ +#define GMACDMA_INTEN_TIE_Msk (0x1ul << GMACDMA_INTEN_TIE_Pos) /*!< GMACDMA_T::INTEN: TIE Mask */ + +#define GMACDMA_INTEN_TSE_Pos (1) /*!< GMACDMA_T::INTEN: TSE Position */ +#define GMACDMA_INTEN_TSE_Msk (0x1ul << GMACDMA_INTEN_TSE_Pos) /*!< GMACDMA_T::INTEN: TSE Mask */ + +#define GMACDMA_INTEN_TUE_Pos (2) /*!< GMACDMA_T::INTEN: TUE Position */ +#define GMACDMA_INTEN_TUE_Msk (0x1ul << GMACDMA_INTEN_TUE_Pos) /*!< GMACDMA_T::INTEN: TUE Mask */ + +#define GMACDMA_INTEN_TJE_Pos (3) /*!< GMACDMA_T::INTEN: TJE Position */ +#define GMACDMA_INTEN_TJE_Msk (0x1ul << GMACDMA_INTEN_TJE_Pos) /*!< GMACDMA_T::INTEN: TJE Mask */ + +#define GMACDMA_INTEN_OVE_Pos (4) /*!< GMACDMA_T::INTEN: OVE Position */ +#define GMACDMA_INTEN_OVE_Msk (0x1ul << GMACDMA_INTEN_OVE_Pos) /*!< GMACDMA_T::INTEN: OVE Mask */ + +#define GMACDMA_INTEN_UNE_Pos (5) /*!< GMACDMA_T::INTEN: UNE Position */ +#define GMACDMA_INTEN_UNE_Msk (0x1ul << GMACDMA_INTEN_UNE_Pos) /*!< GMACDMA_T::INTEN: UNE Mask */ + +#define GMACDMA_INTEN_RIE_Pos (6) /*!< GMACDMA_T::INTEN: RIE Position */ +#define GMACDMA_INTEN_RIE_Msk (0x1ul << GMACDMA_INTEN_RIE_Pos) /*!< GMACDMA_T::INTEN: RIE Mask */ + +#define GMACDMA_INTEN_RUE_Pos (7) /*!< GMACDMA_T::INTEN: RUE Position */ +#define GMACDMA_INTEN_RUE_Msk (0x1ul << GMACDMA_INTEN_RUE_Pos) /*!< GMACDMA_T::INTEN: RUE Mask */ + +#define GMACDMA_INTEN_RSE_Pos (8) /*!< GMACDMA_T::INTEN: RSE Position */ +#define GMACDMA_INTEN_RSE_Msk (0x1ul << GMACDMA_INTEN_RSE_Pos) /*!< GMACDMA_T::INTEN: RSE Mask */ + +#define GMACDMA_INTEN_RWE_Pos (9) /*!< GMACDMA_T::INTEN: RWE Position */ +#define GMACDMA_INTEN_RWE_Msk (0x1ul << GMACDMA_INTEN_RWE_Pos) /*!< GMACDMA_T::INTEN: RWE Mask */ + +#define GMACDMA_INTEN_ETE_Pos (10) /*!< GMACDMA_T::INTEN: ETE Position */ +#define GMACDMA_INTEN_ETE_Msk (0x1ul << GMACDMA_INTEN_ETE_Pos) /*!< GMACDMA_T::INTEN: ETE Mask */ + +#define GMACDMA_INTEN_FBE_Pos (13) /*!< GMACDMA_T::INTEN: FBE Position */ +#define GMACDMA_INTEN_FBE_Msk (0x1ul << GMACDMA_INTEN_FBE_Pos) /*!< GMACDMA_T::INTEN: FBE Mask */ + +#define GMACDMA_INTEN_ERE_Pos (14) /*!< GMACDMA_T::INTEN: ERE Position */ +#define GMACDMA_INTEN_ERE_Msk (0x1ul << GMACDMA_INTEN_ERE_Pos) /*!< GMACDMA_T::INTEN: ERE Mask */ + +#define GMACDMA_INTEN_AIE_Pos (15) /*!< GMACDMA_T::INTEN: AIE Position */ +#define GMACDMA_INTEN_AIE_Msk (0x1ul << GMACDMA_INTEN_AIE_Pos) /*!< GMACDMA_T::INTEN: AIE Mask */ + +#define GMACDMA_INTEN_NIE_Pos (16) /*!< GMACDMA_T::INTEN: NIE Position */ +#define GMACDMA_INTEN_NIE_Msk (0x1ul << GMACDMA_INTEN_NIE_Pos) /*!< GMACDMA_T::INTEN: NIE Mask */ + +#define GMACDMA_MFOVCNTR_MISFRMCNT_Pos (0) /*!< GMACDMA_T::MFOVCNTR: MISFRMCNT Position*/ +#define GMACDMA_MFOVCNTR_MISFRMCNT_Msk (0xfffful << GMACDMA_MFOVCNTR_MISFRMCNT_Pos) /*!< GMACDMA_T::MFOVCNTR: MISFRMCNT Mask*/ + +#define GMACDMA_MFOVCNTR_MISCNTOVF_Pos (16) /*!< GMACDMA_T::MFOVCNTR: MISCNTOVF Position*/ +#define GMACDMA_MFOVCNTR_MISCNTOVF_Msk (0x1ul << GMACDMA_MFOVCNTR_MISCNTOVF_Pos) /*!< GMACDMA_T::MFOVCNTR: MISCNTOVF Mask*/ + +#define GMACDMA_MFOVCNTR_OVFFRMCNT_Pos (17) /*!< GMACDMA_T::MFOVCNTR: OVFFRMCNT Position*/ +#define GMACDMA_MFOVCNTR_OVFFRMCNT_Msk (0x7fful << GMACDMA_MFOVCNTR_OVFFRMCNT_Pos) /*!< GMACDMA_T::MFOVCNTR: OVFFRMCNT Mask*/ + +#define GMACDMA_MFOVCNTR_OVFCNTOVF_Pos (28) /*!< GMACDMA_T::MFOVCNTR: OVFCNTOVF Position*/ +#define GMACDMA_MFOVCNTR_OVFCNTOVF_Msk (0x1ul << GMACDMA_MFOVCNTR_OVFCNTOVF_Pos) /*!< GMACDMA_T::MFOVCNTR: OVFCNTOVF Mask*/ + +#define GMACDMA_RXINTWDT_RIWT_Pos (0) /*!< GMACDMA_T::RXINTWDT: RIWT Position*/ +#define GMACDMA_RXINTWDT_RIWT_Msk (0xfful << GMACDMA_RXINTWDT_RIWT_Pos) /*!< GMACDMA_T::RXINTWDT: RIWT Mask*/ + +#define GMACDMA_AXIMODE_UNDEF_Pos (0) /*!< GMACDMA_T::AXIMODE: UNDEF Position */ +#define GMACDMA_AXIMODE_UNDEF_Msk (0x1ul << GMACDMA_AXIMODE_UNDEF_Pos) /*!< GMACDMA_T::AXIMODE: UNDEF Mask */ + +#define GMACDMA_AXIMODE_BLEN4_Pos (1) /*!< GMACDMA_T::AXIMODE: BLEN4 Position */ +#define GMACDMA_AXIMODE_BLEN4_Msk (0x1ul << GMACDMA_AXIMODE_BLEN4_Pos) /*!< GMACDMA_T::AXIMODE: BLEN4 Mask */ + +#define GMACDMA_AXIMODE_BLEN8_Pos (2) /*!< GMACDMA_T::AXIMODE: BLEN8 Position */ +#define GMACDMA_AXIMODE_BLEN8_Msk (0x1ul << GMACDMA_AXIMODE_BLEN8_Pos) /*!< GMACDMA_T::AXIMODE: BLEN8 Mask */ + +#define GMACDMA_AXIMODE_BLEN16_Pos (3) /*!< GMACDMA_T::AXIMODE: BLEN16 Position */ +#define GMACDMA_AXIMODE_BLEN16_Msk (0x1ul << GMACDMA_AXIMODE_BLEN16_Pos) /*!< GMACDMA_T::AXIMODE: BLEN16 Mask */ + +#define GMACDMA_AXIMODE_AXI_AAL_Pos (12) /*!< GMACDMA_T::AXIMODE: AXI_AAL Position */ +#define GMACDMA_AXIMODE_AXI_AAL_Msk (0x1ul << GMACDMA_AXIMODE_AXI_AAL_Pos) /*!< GMACDMA_T::AXIMODE: AXI_AAL Mask */ + +#define GMACDMA_AXIMODE_ONEKBBE_Pos (13) /*!< GMACDMA_T::AXIMODE: ONEKBBE Position */ +#define GMACDMA_AXIMODE_ONEKBBE_Msk (0x1ul << GMACDMA_AXIMODE_ONEKBBE_Pos) /*!< GMACDMA_T::AXIMODE: ONEKBBE Mask */ + +#define GMACDMA_AXIMODE_RD_OSR_LMT_Pos (16) /*!< GMACDMA_T::AXIMODE: RD_OSR_LMT Position */ +#define GMACDMA_AXIMODE_RD_OSR_LMT_Msk (0x3ul << GMACDMA_AXIMODE_RD_OSR_LMT_Pos) /*!< GMACDMA_T::AXIMODE: RD_OSR_LMT Mask */ + +#define GMACDMA_AXIMODE_RD_OSR_LMT_GT4_Pos (18) /*!< GMACDMA_T::AXIMODE: RD_OSR_LMT_GT4 Position*/ +#define GMACDMA_AXIMODE_RD_OSR_LMT_GT4_Msk (0x1ul << GMACDMA_AXIMODE_RD_OSR_LMT_GT4_Pos) /*!< GMACDMA_T::AXIMODE: RD_OSR_LMT_GT4 Mask */ + +#define GMACDMA_AXIMODE_RD_OSR_LMT_GT8_Pos (19) /*!< GMACDMA_T::AXIMODE: RD_OSR_LMT_GT8 Position*/ +#define GMACDMA_AXIMODE_RD_OSR_LMT_GT8_Msk (0x1ul << GMACDMA_AXIMODE_RD_OSR_LMT_GT8_Pos) /*!< GMACDMA_T::AXIMODE: RD_OSR_LMT_GT8 Mask */ + +#define GMACDMA_AXIMODE_WR_OSR_LMT_Pos (20) /*!< GMACDMA_T::AXIMODE: WR_OSR_LMT Position */ +#define GMACDMA_AXIMODE_WR_OSR_LMT_Msk (0x3ul << GMACDMA_AXIMODE_WR_OSR_LMT_Pos) /*!< GMACDMA_T::AXIMODE: WR_OSR_LMT Mask */ + +#define GMACDMA_AXIMODE_WR_OSR_LMT_GT4_Pos (22) /*!< GMACDMA_T::AXIMODE: WR_OSR_LMT_GT4 Position*/ +#define GMACDMA_AXIMODE_WR_OSR_LMT_GT4_Msk (0x1ul << GMACDMA_AXIMODE_WR_OSR_LMT_GT4_Pos) /*!< GMACDMA_T::AXIMODE: WR_OSR_LMT_GT4 Mask */ + +#define GMACDMA_AXIMODE_WR_OSR_LMT_GT8_Pos (23) /*!< GMACDMA_T::AXIMODE: WR_OSR_LMT_GT8 Position*/ +#define GMACDMA_AXIMODE_WR_OSR_LMT_GT8_Msk (0x1ul << GMACDMA_AXIMODE_WR_OSR_LMT_GT8_Pos) /*!< GMACDMA_T::AXIMODE: WR_OSR_LMT_GT8 Mask */ + +#define GMACDMA_AXIMODE_LPI_XIT_FRM_Pos (30) /*!< GMACDMA_T::AXIMODE: LPI_XIT_FRM Position */ +#define GMACDMA_AXIMODE_LPI_XIT_FRM_Msk (0x1ul << GMACDMA_AXIMODE_LPI_XIT_FRM_Pos) /*!< GMACDMA_T::AXIMODE: LPI_XIT_FRM Mask */ + +#define GMACDMA_AXIMODE_EN_LPI_Pos (31) /*!< GMACDMA_T::AXIMODE: EN_LPI Position */ +#define GMACDMA_AXIMODE_EN_LPI_Msk (0x1ul << GMACDMA_AXIMODE_EN_LPI_Pos) /*!< GMACDMA_T::AXIMODE: EN_LPI Mask */ + +#define GMACDMA_BUSSTS_AXWHSTS_Pos (0) /*!< GMACDMA_T::BUSSTS: AXWHSTS Position*/ +#define GMACDMA_BUSSTS_AXWHSTS_Msk (0x1ul << GMACDMA_BUSSTS_AXWHSTS_Pos) /*!< GMACDMA_T::BUSSTS: AXWHSTS Mask */ + +#define GMACDMA_BUSSTS_AXIRDSTS_Pos (1) /*!< GMACDMA_T::BUSSTS: AXIRDSTS Position*/ +#define GMACDMA_BUSSTS_AXIRDSTS_Msk (0x1ul << GMACDMA_BUSSTS_AXIRDSTS_Pos) /*!< GMACDMA_T::BUSSTS: AXIRDSTS Mask */ + +#define GMACDMA_CTXDESC_CURTDESAPTR_Pos (0) /*!< GMACDMA_T::CTXDESC: CURTDESAPTR Position*/ +#define GMACDMA_CTXDESC_CURTDESAPTR_Msk (0xfffffffful << GMACDMA_CTXDESC_CURTDESAPTR_Pos) /*!< GMACDMA_T::CTXDESC: CURTDESAPTR Mask*/ + +#define GMACDMA_CRXDESC_CURRDESAPTR_Pos (0) /*!< GMACDMA_T::CRXDESC: CURRDESAPTR Position*/ +#define GMACDMA_CRXDESC_CURRDESAPTR_Msk (0xfffffffful << GMACDMA_CRXDESC_CURRDESAPTR_Pos) /*!< GMACDMA_T::CRXDESC: CURRDESAPTR Mask*/ + +#define GMACDMA_CTXBUF_CURTBUFAPTR_Pos (0) /*!< GMACDMA_T::CTXBUF: CURTBUFAPTR Position*/ +#define GMACDMA_CTXBUF_CURTBUFAPTR_Msk (0xfffffffful << GMACDMA_CTXBUF_CURTBUFAPTR_Pos) /*!< GMACDMA_T::CTXBUF: CURTBUFAPTR Mask*/ + +#define GMACDMA_CRXBUF_CURRBUFAPTR_Pos (0) /*!< GMACDMA_T::CRXBUF: CURRBUFAPTR Position*/ +#define GMACDMA_CRXBUF_CURRBUFAPTR_Msk (0xfffffffful << GMACDMA_CRXBUF_CURRBUFAPTR_Pos) /*!< GMACDMA_T::CRXBUF: CURRBUFAPTR Mask*/ + +#define GMACDMA_HWFEAT_MIISEL_Pos (0) /*!< GMACDMA_T::HWFEAT: MIISEL Position */ +#define GMACDMA_HWFEAT_MIISEL_Msk (0x1ul << GMACDMA_HWFEAT_MIISEL_Pos) /*!< GMACDMA_T::HWFEAT: MIISEL Mask */ + +#define GMACDMA_HWFEAT_GMIISEL_Pos (1) /*!< GMACDMA_T::HWFEAT: GMIISEL Position */ +#define GMACDMA_HWFEAT_GMIISEL_Msk (0x1ul << GMACDMA_HWFEAT_GMIISEL_Pos) /*!< GMACDMA_T::HWFEAT: GMIISEL Mask */ + +#define GMACDMA_HWFEAT_HDSEL_Pos (2) /*!< GMACDMA_T::HWFEAT: HDSEL Position */ +#define GMACDMA_HWFEAT_HDSEL_Msk (0x1ul << GMACDMA_HWFEAT_HDSEL_Pos) /*!< GMACDMA_T::HWFEAT: HDSEL Mask */ + +#define GMACDMA_HWFEAT_EXTHASHEN_Pos (3) /*!< GMACDMA_T::HWFEAT: EXTHASHEN Position */ +#define GMACDMA_HWFEAT_EXTHASHEN_Msk (0x1ul << GMACDMA_HWFEAT_EXTHASHEN_Pos) /*!< GMACDMA_T::HWFEAT: EXTHASHEN Mask */ + +#define GMACDMA_HWFEAT_HASHSEL_Pos (4) /*!< GMACDMA_T::HWFEAT: HASHSEL Position */ +#define GMACDMA_HWFEAT_HASHSEL_Msk (0x1ul << GMACDMA_HWFEAT_HASHSEL_Pos) /*!< GMACDMA_T::HWFEAT: HASHSEL Mask */ + +#define GMACDMA_HWFEAT_ADDMACADRSEL_Pos (5) /*!< GMACDMA_T::HWFEAT: ADDMACADRSEL Position */ +#define GMACDMA_HWFEAT_ADDMACADRSEL_Msk (0x1ul << GMACDMA_HWFEAT_ADDMACADRSEL_Pos) /*!< GMACDMA_T::HWFEAT: ADDMACADRSEL Mask */ + +#define GMACDMA_HWFEAT_PCSSEL_Pos (6) /*!< GMACDMA_T::HWFEAT: PCSSEL Position */ +#define GMACDMA_HWFEAT_PCSSEL_Msk (0x1ul << GMACDMA_HWFEAT_PCSSEL_Pos) /*!< GMACDMA_T::HWFEAT: PCSSEL Mask */ + +#define GMACDMA_HWFEAT_L3L4FLTREN_Pos (7) /*!< GMACDMA_T::HWFEAT: L3L4FLTREN Position */ +#define GMACDMA_HWFEAT_L3L4FLTREN_Msk (0x1ul << GMACDMA_HWFEAT_L3L4FLTREN_Pos) /*!< GMACDMA_T::HWFEAT: L3L4FLTREN Mask */ + +#define GMACDMA_HWFEAT_SMASEL_Pos (8) /*!< GMACDMA_T::HWFEAT: SMASEL Position */ +#define GMACDMA_HWFEAT_SMASEL_Msk (0x1ul << GMACDMA_HWFEAT_SMASEL_Pos) /*!< GMACDMA_T::HWFEAT: SMASEL Mask */ + +#define GMACDMA_HWFEAT_RWKSEL_Pos (9) /*!< GMACDMA_T::HWFEAT: RWKSEL Position */ +#define GMACDMA_HWFEAT_RWKSEL_Msk (0x1ul << GMACDMA_HWFEAT_RWKSEL_Pos) /*!< GMACDMA_T::HWFEAT: RWKSEL Mask */ + +#define GMACDMA_HWFEAT_MGKSEL_Pos (10) /*!< GMACDMA_T::HWFEAT: MGKSEL Position */ +#define GMACDMA_HWFEAT_MGKSEL_Msk (0x1ul << GMACDMA_HWFEAT_MGKSEL_Pos) /*!< GMACDMA_T::HWFEAT: MGKSEL Mask */ + +#define GMACDMA_HWFEAT_MMCSEL_Pos (11) /*!< GMACDMA_T::HWFEAT: MMCSEL Position */ +#define GMACDMA_HWFEAT_MMCSEL_Msk (0x1ul << GMACDMA_HWFEAT_MMCSEL_Pos) /*!< GMACDMA_T::HWFEAT: MMCSEL Mask */ + +#define GMACDMA_HWFEAT_TSVER1SEL_Pos (12) /*!< GMACDMA_T::HWFEAT: TSVER1SEL Position */ +#define GMACDMA_HWFEAT_TSVER1SEL_Msk (0x1ul << GMACDMA_HWFEAT_TSVER1SEL_Pos) /*!< GMACDMA_T::HWFEAT: TSVER1SEL Mask */ + +#define GMACDMA_HWFEAT_TSVER2SEL_Pos (13) /*!< GMACDMA_T::HWFEAT: TSVER2SEL Position */ +#define GMACDMA_HWFEAT_TSVER2SEL_Msk (0x1ul << GMACDMA_HWFEAT_TSVER2SEL_Pos) /*!< GMACDMA_T::HWFEAT: TSVER2SEL Mask */ + +#define GMACDMA_HWFEAT_EEESEL_Pos (14) /*!< GMACDMA_T::HWFEAT: EEESEL Position */ +#define GMACDMA_HWFEAT_EEESEL_Msk (0x1ul << GMACDMA_HWFEAT_EEESEL_Pos) /*!< GMACDMA_T::HWFEAT: EEESEL Mask */ + +#define GMACDMA_HWFEAT_AVSEL_Pos (15) /*!< GMACDMA_T::HWFEAT: AVSEL Position */ +#define GMACDMA_HWFEAT_AVSEL_Msk (0x1ul << GMACDMA_HWFEAT_AVSEL_Pos) /*!< GMACDMA_T::HWFEAT: AVSEL Mask */ + +#define GMACDMA_HWFEAT_TXCOESEL_Pos (16) /*!< GMACDMA_T::HWFEAT: TXCOESEL Position */ +#define GMACDMA_HWFEAT_TXCOESEL_Msk (0x1ul << GMACDMA_HWFEAT_TXCOESEL_Pos) /*!< GMACDMA_T::HWFEAT: TXCOESEL Mask */ + +#define GMACDMA_HWFEAT_RXTYP1COE_Pos (17) /*!< GMACDMA_T::HWFEAT: RXTYP1COE Position */ +#define GMACDMA_HWFEAT_RXTYP1COE_Msk (0x1ul << GMACDMA_HWFEAT_RXTYP1COE_Pos) /*!< GMACDMA_T::HWFEAT: RXTYP1COE Mask */ + +#define GMACDMA_HWFEAT_RXTYP2COE_Pos (18) /*!< GMACDMA_T::HWFEAT: RXTYP2COE Position */ +#define GMACDMA_HWFEAT_RXTYP2COE_Msk (0x1ul << GMACDMA_HWFEAT_RXTYP2COE_Pos) /*!< GMACDMA_T::HWFEAT: RXTYP2COE Mask */ + +#define GMACDMA_HWFEAT_RXFIFOSIZE_Pos (19) /*!< GMACDMA_T::HWFEAT: RXFIFOSIZE Position */ +#define GMACDMA_HWFEAT_RXFIFOSIZE_Msk (0x1ul << GMACDMA_HWFEAT_RXFIFOSIZE_Pos) /*!< GMACDMA_T::HWFEAT: RXFIFOSIZE Mask */ + +#define GMACDMA_HWFEAT_RXCHCNT_Pos (20) /*!< GMACDMA_T::HWFEAT: RXCHCNT Position */ +#define GMACDMA_HWFEAT_RXCHCNT_Msk (0x3ul << GMACDMA_HWFEAT_RXCHCNT_Pos) /*!< GMACDMA_T::HWFEAT: RXCHCNT Mask */ + +#define GMACDMA_HWFEAT_TXCHCNT_Pos (22) /*!< GMACDMA_T::HWFEAT: TXCHCNT Position */ +#define GMACDMA_HWFEAT_TXCHCNT_Msk (0x3ul << GMACDMA_HWFEAT_TXCHCNT_Pos) /*!< GMACDMA_T::HWFEAT: TXCHCNT Mask */ + +#define GMACDMA_HWFEAT_ENHDESSEL_Pos (24) /*!< GMACDMA_T::HWFEAT: ENHDESSEL Position */ +#define GMACDMA_HWFEAT_ENHDESSEL_Msk (0x1ul << GMACDMA_HWFEAT_ENHDESSEL_Pos) /*!< GMACDMA_T::HWFEAT: ENHDESSEL Mask */ + +#define GMACDMA_HWFEAT_INTTSEN_Pos (25) /*!< GMACDMA_T::HWFEAT: INTTSEN Position */ +#define GMACDMA_HWFEAT_INTTSEN_Msk (0x1ul << GMACDMA_HWFEAT_INTTSEN_Pos) /*!< GMACDMA_T::HWFEAT: INTTSEN Mask */ + +#define GMACDMA_HWFEAT_FLEXIPPSEN_Pos (26) /*!< GMACDMA_T::HWFEAT: FLEXIPPSEN Position */ +#define GMACDMA_HWFEAT_FLEXIPPSEN_Msk (0x1ul << GMACDMA_HWFEAT_FLEXIPPSEN_Pos) /*!< GMACDMA_T::HWFEAT: FLEXIPPSEN Mask */ + +#define GMACDMA_HWFEAT_SAVLANINS_Pos (27) /*!< GMACDMA_T::HWFEAT: SAVLANINS Position */ +#define GMACDMA_HWFEAT_SAVLANINS_Msk (0x1ul << GMACDMA_HWFEAT_SAVLANINS_Pos) /*!< GMACDMA_T::HWFEAT: SAVLANINS Mask */ + +#define GMACDMA_HWFEAT_ACTPHYIF_Pos (28) /*!< GMACDMA_T::HWFEAT: ACTPHYIF Position */ +#define GMACDMA_HWFEAT_ACTPHYIF_Msk (0x7ul << GMACDMA_HWFEAT_ACTPHYIF_Pos) /*!< GMACDMA_T::HWFEAT: ACTPHYIF Mask */ + +/**@}*/ /* GMACDMA_CONST */ +/**@}*/ /* end of GMACDMA register group */ +/**@}*/ /* end of REGISTER group */ + +#if defined ( __CC_ARM ) + #pragma no_anon_unions +#endif + +#endif /* __GMAC_REG_H__ */ diff --git a/bsp/nuvoton/libraries/ma35/Device/Nuvoton/MA35D1/Include/gpio_reg.h b/bsp/nuvoton/libraries/ma35/Device/Nuvoton/MA35D1/Include/gpio_reg.h new file mode 100644 index 0000000000..c969d76b76 --- /dev/null +++ b/bsp/nuvoton/libraries/ma35/Device/Nuvoton/MA35D1/Include/gpio_reg.h @@ -0,0 +1,1221 @@ +/**************************************************************************//** + * @file gpio_reg.h + * @brief GPIO register definition header file + * + * SPDX-License-Identifier: Apache-2.0 + * @copyright (C) 2020 Nuvoton Technology Corp. All rights reserved. + *****************************************************************************/ +#ifndef __GPIO_REG_H__ +#define __GPIO_REG_H__ + +#if defined ( __CC_ARM ) + #pragma anon_unions +#endif + +/** + @addtogroup REGISTER Control Register + @{ +*/ + +/** + @addtogroup GPIO General Purpose Input/Output Controller(GPIO) + Memory Mapped Structure for GPIO Controller +@{ */ + + +typedef struct +{ + + /** + * @var GPIO_T::MODE + * Offset: 0x00/0x40/0x80/0xC0/0x100/0x140/0x180/0x1C0/0x200/0x240/0x280/0x2C0/0x300/0x340 Port A-N I/O Mode Control + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[2n+1:2n]|MODEn |Port A-N I/O Pin[n] Mode Control + * | | |Determine each I/O mode of Px.n pins. + * | | |00 = Px.n is in Input mode. + * | | |01 = Px.n is in Push-pull Output mode. + * | | |10 = Px.n is in Open-drain Output mode. + * | | |11 = Reserved. + * | | |Note 1: The default value is 0x0000_0000 and all pins will be input mode after chip powered on. + * | | |Note 2: If MFOS is enabled then GPIO mode setting is ignored. + * @var GPIO_T::DINOFF + * Offset: 0x04/0x44/0x84/0xC4/0x104/0x144/0x184/0x1C4/0x204/0x244/0x284/0x2C4/0x304/0x344 Port A-N Digital Input Path Disable Control + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[n+16] |DINOFFn |Port A-N Pin[n] Digital Input Path Disable Bit + * | | |Each of these bits is used to control if the digital input path of corresponding Px.n pin is disabled. + * | | |If input is analog signal, users can disable Px.n digital input path to avoid input current leakage. + * | | |0 = Px.n digital input path Enabled. + * | | |1 = Px.n digital input path Disabled (digital input tied to low). + * @var GPIO_T::DOUT + * Offset: 0x08/0x48/0x88/0xC8/0x108/0x148/0x188/0x1C8/0x208/0x248/0x288/0x2C8/0x308/0x348 Port A-N Data Output Value + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[n] |DOUTn |Port A-N Pin[n] Output Value + * | | |Each of these bits controls the status of a Px.n pin when the Px.n is configured as Push-pull output, Open-drain output or Quasi-bidirectional mode. + * | | |0 = Px.n will drive Low if the Px.n pin is configured as Push-pull output, Open-drain output or Quasi-bidirectional mode. + * | | |1 = Px.n will drive High if the Px.n pin is configured as Push-pull output or Quasi-bidirectional mode. + * @var GPIO_T::DATMSK + * Offset: 0x0C/0x4C/0x8C/0xCC/0x10C/0x14C/0x18C/0x1CC/0x20C/0x24C/0x28C/0x2CC/0x30C/0x34C Port A-N Data Output Write Mask + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[n] |DATMSKn |Port A-N Pin[n] Data Output Write Mask + * | | |These bits are used to protect the corresponding DOUT (Px_DOUT[n]) bit + * | | |When the DATMSK (Px_DATMSK[n]) bit is set to 1, the corresponding DOUT (Px_DOUT[n]) bit is protected. + * | | |If the write signal is masked, writing data to the protect bit is ignored. + * | | |0 = Corresponding DOUT (Px_DOUT[n]) bit can be updated. + * | | |1 = Corresponding DOUT (Px_DOUT[n]) bit protected. + * | | |Note: This function only protects the corresponding DOUT (Px_DOUT[n]) bit, and will not protect the corresponding PDIO (Pxn_PDIO[0]) bit. + * @var GPIO_T::PIN + * Offset: 0x10/0x50/0x90/0xD0/0x110/0x150/0x190/0x1D0/0x210/0x250/0x290/0x2D0/0x310/0x350 Port A-N Pin Value + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[n] |PINn |Port A-N Pin[n] Pin Value + * | | |Each bit of the register reflects the actual status of the respective Px.n pin. + * | | |If the bit is 1, it indicates the corresponding pin status is high; else the pin status is low. + * @var GPIO_T::DBEN + * Offset: 0x14/0x54/0x94/0xD4/0x114/0x154/0x194/0x1D4/0x214/0x254/0x294/0x2D4/0x314/0x354 Port A-N De-Bounce Enable Control Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[n] |DBENn |Port A-N Pin[n] Input Signal De-Bounce Enable Bit + * | | |The DBEN[n] bit is used to enable the de-bounce function for each corresponding bit. + * | | |If the input signal pulse width cannot be sampled by continuous two de-bounce sample cycle, the input signal transition is seen as the signal bounce and will not trigger the interrupt. + * | | |The de-bounce clock source is controlled by DBCLKSRC (GPIO_DBCTL [4]), one de-bounce sample cycle period is controlled by DBCLKSEL (GPIO_DBCTL [3:0]). + * | | |0 = Px.n de-bounce function Disabled. + * | | |1 = Px.n de-bounce function Enabled. + * | | |The de-bounce function is valid only for edge triggered interrupt. + * | | |If the interrupt mode is level triggered, the de-bounce enable bit is ignored. + * @var GPIO_T::INTTYPE + * Offset: 0x18/0x58/0x98/0xD8/0x118/0x158/0x198/0x1D8/0x218/0x258/0x298/0x2D8/0x318/0x358 Port A-N Interrupt Trigger Type Control + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[n] |TYPEn |Port A-N Pin[n] Edge or Level Detection Interrupt Trigger Type Control + * | | |TYPE (Px_INTTYPE[n]) bit is used to control the triggered interrupt is by level trigger or by edge trigger. + * | | |If the interrupt is by edge trigger, the trigger source can be controlled by de-bounce. + * | | |If the interrupt is by level trigger, the input source is sampled by one HCLK clock and generates the interrupt. + * | | |0 = Edge trigger interrupt. + * | | |1 = Level trigger interrupt. + * | | |If the pin is set as the level trigger interrupt, only one level can be set on the registers RHIEN (Px_INTEN[n+16])/FLIEN (Px_INTEN[n]). + * | | |If both levels to trigger interrupt are set, the setting is ignored and no interrupt will occur. + * | | |The de-bounce function is valid only for edge triggered interrupt. + * | | |If the interrupt mode is level triggered, the de-bounce enable bit is ignored. + * @var GPIO_T::INTEN + * Offset: 0x1C/0x5C/0x9C/0xDC/0x11C/0x15C/0x19C/0x1DC/0x21C/0x25C/0x29C/0x2DC/0x31C/0x35C Port A-N Interrupt Enable Control Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[n] |FLIENn |Port A-N Pin[n] Falling Edge or Low Level Interrupt Trigger Type Enable Bit + * | | |The FLIEN (Px_INTEN[n]) bit is used to enable the interrupt for each of the corresponding input Px.n pin. + * | | |Set bit to 1 also enable the pin wake-up function. + * | | |When setting the FLIEN (Px_INTEN[n]) bit to 1 : + * | | |If the interrupt is level trigger (TYPE (Px_INTTYPE[n]) bit is set to 1), the input Px.n pin will generate the interrupt while this pin state is at low level. + * | | |If the interrupt is edge trigger(TYPE (Px_INTTYPE[n]) bit is set to 0), the input Px.n pin will generate the interrupt while this pin state changed from high to low. + * | | |0 = Px.n level low or high to low interrupt Disabled. + * | | |1 = Px.n level low or high to low interrupt Enabled. + * |[n+16] |RHIENn |Port A-N Pin[n] Rising Edge or High Level Interrupt Trigger Type Enable Bit + * | | |The RHIEN (Px_INTEN[n+16]) bit is used to enable the interrupt for each of the corresponding input Px.n pin + * | | |Set bit to 1 also enable the pin wake-up function. + * | | |When setting the RHIEN (Px_INTEN[n+16]) bit to 1 : + * | | |If the interrupt is level trigger (TYPE (Px_INTTYPE[n]) bit is set to 1), the input Px.n pin will generate the interrupt while this pin state is at high level. + * | | |If the interrupt is edge trigger (TYPE (Px_INTTYPE[n]) bit is set to 0), the input Px.n pin will generate the interrupt while this pin state changed from low to high. + * | | |0 = Px.n level high or low to high interrupt Disabled. + * | | |1 = Px.n level high or low to high interrupt Enabled. + * @var GPIO_T::INTSRC + * Offset: 0x20/0x60/0xA0/0xE0/0x120/0x160/0x1A0/0x1E0/0x220/0x260/0x2A0/0x2E0/0x320/0x360 Port A-N Interrupt Source Flag + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[n] |INTSRCn |Port A-N Pin[n] Interrupt Source Flag + * | | |Write Operation : + * | | |0 = No action. + * | | |1 = Clear the corresponding pending interrupt. + * | | |Read Operation : + * | | |0 = No interrupt at Px.n. + * | | |1 = Px.n generates an interrupt. + * @var GPIO_T::SMTEN + * Offset: 0x24/0x64/0xA4/0xE4/0x124/0x164/0x1A4/0x1E4/0x224/0x264/0x2A4/0x2E4/0x324/0x364 Port A-N Input Schmitt Trigger Enable Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[n] |SMTENn |Port A-N Pin[n] Input Schmitt Trigger Enable Bit + * | | |0 = Px.n input Schmitt trigger function Disabled. + * | | |1 = Px.n input Schmitt trigger function Enabled. + * @var GPIO_T::SLEWCTL + * Offset: 0x28/0x68/0xA8/0xE8/0x128/0x168/0x1A8/0x1E8/0x228/0x268/0x2A8/0x2E8/0x328/0x368 Port A-N High Slew Rate Control Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[2n+1:2n]|HSRENn |Port A-N Pin[n] High Slew Rate Control + * | | |00 = Px.n output with normal slew rate mode. + * | | |01 = Px.n output with high slew rate mode . + * | | |10 = Reserved. + * | | |11 = Reserved. + * @var GPIO_T::PUSEL + * Offset: 0x30/0x70/0xB0/0xF0/0x130/0x170/0x1B0/0x1F0/0x230/0x270/0x2B0/0x2F0/0x330/0x370 Port A-N Pull-up and Pull-down Selection Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[2n+1:2n]|PUSELn |Port A-N Pin[n] Pull-up and Pull-down Enable Register + * | | |Determine each I/O Pull-up/pull-down of Px.n pins. + * | | |00 = Px.n pull-up and pull-down disable. + * | | |01 = Px.n pull-up enable. + * | | |10 = Px.n pull-down enable. + * | | |11 = Px.n pull-up and pull-down disable. + * | | |Note: Basically, the pull-up control and pull-down control has following behavior limitation. + * | | |The independent pull-up control register only valid when MODEn is set as input and open-drain mode even if I/O function is switched to multi-function pin, e.g + * | | |UARTx_RXD. + * | | |The independent pull-down control register is only valid when MODEn set as tri-state mode. + * | | |When both pull-up pull-down is set as 1 at "tri-state" mode, keep I/O in tri-state mode. + * @var GPIO_T::DBCTL + * Offset: 0x34/0x74/0xB4/0xF4/0x134/0x174/0x1B4/0x1F4/0x234/0x274/0x2B4/0x2F4/0x334/0x374 Port A-N Interrupt De-bounce Control Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[3:0] |DBCLKSEL |De-bounce Sampling Cycle Selection + * | | |0000 = Sample interrupt input once per 1 clocks. + * | | |0001 = Sample interrupt input once per 2 clocks. + * | | |0010 = Sample interrupt input once per 4 clocks. + * | | |0011 = Sample interrupt input once per 8 clocks. + * | | |0100 = Sample interrupt input once per 16 clocks. + * | | |0101 = Sample interrupt input once per 32 clocks. + * | | |0110 = Sample interrupt input once per 64 clocks. + * | | |0111 = Sample interrupt input once per 128 clocks. + * | | |1000 = Sample interrupt input once per 256 clocks. + * | | |1001 = Sample interrupt input once per 2*256 clocks. + * | | |1010 = Sample interrupt input once per 4*256 clocks. + * | | |1011 = Sample interrupt input once per 8*256 clocks. + * | | |1100 = Sample interrupt input once per 16*256 clocks. + * | | |1101 = Sample interrupt input once per 32*256 clocks. + * | | |1110 = Sample interrupt input once per 64*256 clocks. + * | | |1111 = Sample interrupt input once per 128*256 clocks. + * |[4] |DBCLKSRC |De-bounce Counter Clock Source Selection + * | | |0 = De-bounce counter clock source is the HXT. + * | | |1 = De-bounce counter clock source is the LIRC. + * | | |Note: This bit is reserved if the chip package without LIRC + * | | |The de-bounce counter clock source is only from HXT + * | | |And setting this bit does not guarantee what will occur. + * |[5] |ICLKON |Interrupt Clock on Mode + * | | |0 = Edge detection circuit is active only if I/O pin corresponding RHIEN (Px_INTEN[n+16])/FLIEN (Px_INTEN[n]) bit is set to 1. + * | | |1 = All I/O pins edge detection circuit is always active after reset. + * | | |Note: It is recommended to disable this bit to save system power if no special application concern. + * @var GPIO_T::DS + * Offset: 0x38 0x38/0x78/0xB8/0xF8/0x138/0x178/0x1B8/0x1F8/0x238/0x278/0x2B8/0x2F8/0x338/0x378 Port A-N Driver Strength Control Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[0] |DS10_DS00 |Port A-N Pin[n] Driver Strength Control Register + * | | |Determine each driver strength of Px.n pins. + * | | |00 = [ DS1n, DS0n] is minimum diver strength. + * | | |11 = [ DS1n, DS0n] is maximum diver strength. + * | | |Note: PH_DS bit20~bit23 are reserved. + * | | |The UDS and DS bits are Px.n driver strength control bits. + * | | |When [ UDS, DS1, DS0 ] are "111", the driver strength is maximum. + * | | |When [ UDS, DS1, DS0 ] are "000", the driver strength is minimum. + * |[1] |DS11_DS01 |Port A-N Pin[n] Driver Strength Control Register + * | | |Determine each driver strength of Px.n pins. + * | | |00 = [ DS1n, DS0n] is minimum diver strength. + * | | |11 = [ DS1n, DS0n] is maximum diver strength. + * | | |Note: PH_DS bit20~bit23 are reserved. + * | | |The UDS and DS bits are Px.n driver strength control bits. + * | | |When [ UDS, DS1, DS0 ] are "111", the driver strength is maximum. + * | | |When [ UDS, DS1, DS0 ] are "000", the driver strength is minimum. + * |[2] |DS12_DS02 |Port A-N Pin[n] Driver Strength Control Register + * | | |Determine each driver strength of Px.n pins. + * | | |00 = [ DS1n, DS0n] is minimum diver strength. + * | | |11 = [ DS1n, DS0n] is maximum diver strength. + * | | |Note: PH_DS bit20~bit23 are reserved. + * | | |The UDS and DS bits are Px.n driver strength control bits. + * | | |When [ UDS, DS1, DS0 ] are "111", the driver strength is maximum. + * | | |When [ UDS, DS1, DS0 ] are "000", the driver strength is minimum. + * |[3] |DS13_DS03 |Port A-N Pin[n] Driver Strength Control Register + * | | |Determine each driver strength of Px.n pins. + * | | |00 = [ DS1n, DS0n] is minimum diver strength. + * | | |11 = [ DS1n, DS0n] is maximum diver strength. + * | | |Note: PH_DS bit20~bit23 are reserved. + * | | |The UDS and DS bits are Px.n driver strength control bits. + * | | |When [ UDS, DS1, DS0 ] are "111", the driver strength is maximum. + * | | |When [ UDS, DS1, DS0 ] are "000", the driver strength is minimum. + * |[4] |DS14_DS04 |Port A-N Pin[n] Driver Strength Control Register + * | | |Determine each driver strength of Px.n pins. + * | | |00 = [ DS1n, DS0n] is minimum diver strength. + * | | |11 = [ DS1n, DS0n] is maximum diver strength. + * | | |Note: PH_DS bit20~bit23 are reserved. + * | | |The UDS and DS bits are Px.n driver strength control bits. + * | | |When [ UDS, DS1, DS0 ] are "111", the driver strength is maximum. + * | | |When [ UDS, DS1, DS0 ] are "000", the driver strength is minimum. + * |[5] |DS15_DS05 |Port A-N Pin[n] Driver Strength Control Register + * | | |Determine each driver strength of Px.n pins. + * | | |00 = [ DS1n, DS0n] is minimum diver strength. + * | | |11 = [ DS1n, DS0n] is maximum diver strength. + * | | |Note: PH_DS bit20~bit23 are reserved. + * | | |The UDS and DS bits are Px.n driver strength control bits. + * | | |When [ UDS, DS1, DS0 ] are "111", the driver strength is maximum. + * | | |When [ UDS, DS1, DS0 ] are "000", the driver strength is minimum. + * |[6] |DS16_DS06 |Port A-N Pin[n] Driver Strength Control Register + * | | |Determine each driver strength of Px.n pins. + * | | |00 = [ DS1n, DS0n] is minimum diver strength. + * | | |11 = [ DS1n, DS0n] is maximum diver strength. + * | | |Note: PH_DS bit20~bit23 are reserved. + * | | |The UDS and DS bits are Px.n driver strength control bits. + * | | |When [ UDS, DS1, DS0 ] are "111", the driver strength is maximum. + * | | |When [ UDS, DS1, DS0 ] are "000", the driver strength is minimum. + * |[7] |DS17_DS07 |Port A-N Pin[n] Driver Strength Control Register + * | | |Determine each driver strength of Px.n pins. + * | | |00 = [ DS1n, DS0n] is minimum diver strength. + * | | |11 = [ DS1n, DS0n] is maximum diver strength. + * | | |Note: PH_DS bit20~bit23 are reserved. + * | | |The UDS and DS bits are Px.n driver strength control bits. + * | | |When [ UDS, DS1, DS0 ] are "111", the driver strength is maximum. + * | | |When [ UDS, DS1, DS0 ] are "000", the driver strength is minimum. + * |[8] |DS18_DS08 |Port A-N Pin[n] Driver Strength Control Register + * | | |Determine each driver strength of Px.n pins. + * | | |00 = [ DS1n, DS0n] is minimum diver strength. + * | | |11 = [ DS1n, DS0n] is maximum diver strength. + * | | |Note: PH_DS bit20~bit23 are reserved. + * | | |The UDS and DS bits are Px.n driver strength control bits. + * | | |When [ UDS, DS1, DS0 ] are "111", the driver strength is maximum. + * | | |When [ UDS, DS1, DS0 ] are "000", the driver strength is minimum. + * |[9] |DS19_DS09 |Port A-N Pin[n] Driver Strength Control Register + * | | |Determine each driver strength of Px.n pins. + * | | |00 = [ DS1n, DS0n] is minimum diver strength. + * | | |11 = [ DS1n, DS0n] is maximum diver strength. + * | | |Note: PH_DS bit20~bit23 are reserved. + * | | |The UDS and DS bits are Px.n driver strength control bits. + * | | |When [ UDS, DS1, DS0 ] are "111", the driver strength is maximum. + * | | |When [ UDS, DS1, DS0 ] are "000", the driver strength is minimum. + * |[10] |DS110_DS010|Port A-N Pin[n] Driver Strength Control Register + * | | |Determine each driver strength of Px.n pins. + * | | |00 = [ DS1n, DS0n] is minimum diver strength. + * | | |11 = [ DS1n, DS0n] is maximum diver strength. + * | | |Note: PH_DS bit20~bit23 are reserved. + * | | |The UDS and DS bits are Px.n driver strength control bits. + * | | |When [ UDS, DS1, DS0 ] are "111", the driver strength is maximum. + * | | |When [ UDS, DS1, DS0 ] are "000", the driver strength is minimum. + * |[11] |DS111_DS011|Port A-N Pin[n] Driver Strength Control Register + * | | |Determine each driver strength of Px.n pins. + * | | |00 = [ DS1n, DS0n] is minimum diver strength. + * | | |11 = [ DS1n, DS0n] is maximum diver strength. + * | | |Note: PH_DS bit20~bit23 are reserved. + * | | |The UDS and DS bits are Px.n driver strength control bits. + * | | |When [ UDS, DS1, DS0 ] are "111", the driver strength is maximum. + * | | |When [ UDS, DS1, DS0 ] are "000", the driver strength is minimum. + * |[12] |DS112_DS012|Port A-N Pin[n] Driver Strength Control Register + * | | |Determine each driver strength of Px.n pins. + * | | |00 = [ DS1n, DS0n] is minimum diver strength. + * | | |11 = [ DS1n, DS0n] is maximum diver strength. + * | | |Note: PH_DS bit20~bit23 are reserved. + * | | |The UDS and DS bits are Px.n driver strength control bits. + * | | |When [ UDS, DS1, DS0 ] are "111", the driver strength is maximum. + * | | |When [ UDS, DS1, DS0 ] are "000", the driver strength is minimum. + * |[13] |DS113_DS013|Port A-N Pin[n] Driver Strength Control Register + * | | |Determine each driver strength of Px.n pins. + * | | |00 = [ DS1n, DS0n] is minimum diver strength. + * | | |11 = [ DS1n, DS0n] is maximum diver strength. + * | | |Note: PH_DS bit20~bit23 are reserved. + * | | |The UDS and DS bits are Px.n driver strength control bits. + * | | |When [ UDS, DS1, DS0 ] are "111", the driver strength is maximum. + * | | |When [ UDS, DS1, DS0 ] are "000", the driver strength is minimum. + * |[14] |DS114_DS014|Port A-N Pin[n] Driver Strength Control Register + * | | |Determine each driver strength of Px.n pins. + * | | |00 = [ DS1n, DS0n] is minimum diver strength. + * | | |11 = [ DS1n, DS0n] is maximum diver strength. + * | | |Note: PH_DS bit20~bit23 are reserved. + * | | |The UDS and DS bits are Px.n driver strength control bits. + * | | |When [ UDS, DS1, DS0 ] are "111", the driver strength is maximum. + * | | |When [ UDS, DS1, DS0 ] are "000", the driver strength is minimum. + * |[15] |DS115_DS015|Port A-N Pin[n] Driver Strength Control Register + * | | |Determine each driver strength of Px.n pins. + * | | |00 = [ DS1n, DS0n] is minimum diver strength. + * | | |11 = [ DS1n, DS0n] is maximum diver strength. + * | | |Note: PH_DS bit20~bit23 are reserved. + * | | |The UDS and DS bits are Px.n driver strength control bits. + * | | |When [ UDS, DS1, DS0 ] are "111", the driver strength is maximum. + * | | |When [ UDS, DS1, DS0 ] are "000", the driver strength is minimum. + * @var GPIO_T::PA_UDS + * Offset: 0x3C/0x7C/0xBC/0xFC/0x13C/0x17C/0x1BC/0x1FC/0x23C/0x27C/0x2BC/0x2FC/0x33C/0x37C Port A-N Ultra Driver Strength Control Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[0] |UDS0 |Port A-N Pin[n] Ultra Driver Strength Control Register + * | | |Determine each driver strength of Px.n pins. + * | | |0 = Px.n is minimum deiver strength. + * | | |1 = Px.n is maximum deiver strength. + * | | |Note: The UDS and DS bits are Px.n driver strength control bits. + * | | |When [ UDS, DS1, DS0 ] are "111", the driver strength is the maximum. + * | | |When [ UDS, DS1, DS0 ] are "000", the driver strength is the minimum. + * |[1] |UDS1 |Port A-N Pin[n] Ultra Driver Strength Control Register + * | | |Determine each driver strength of Px.n pins. + * | | |0 = Px.n is minimum deiver strength. + * | | |1 = Px.n is maximum deiver strength. + * | | |Note: The UDS and DS bits are Px.n driver strength control bits. + * | | |When [ UDS, DS1, DS0 ] are "111", the driver strength is the maximum. + * | | |When [ UDS, DS1, DS0 ] are "000", the driver strength is the minimum. + * |[2] |UDS2 |Port A-N Pin[n] Ultra Driver Strength Control Register + * | | |Determine each driver strength of Px.n pins. + * | | |0 = Px.n is minimum deiver strength. + * | | |1 = Px.n is maximum deiver strength. + * | | |Note: The UDS and DS bits are Px.n driver strength control bits. + * | | |When [ UDS, DS1, DS0 ] are "111", the driver strength is the maximum. + * | | |When [ UDS, DS1, DS0 ] are "000", the driver strength is the minimum. + * |[3] |UDS3 |Port A-N Pin[n] Ultra Driver Strength Control Register + * | | |Determine each driver strength of Px.n pins. + * | | |0 = Px.n is minimum deiver strength. + * | | |1 = Px.n is maximum deiver strength. + * | | |Note: The UDS and DS bits are Px.n driver strength control bits. + * | | |When [ UDS, DS1, DS0 ] are "111", the driver strength is the maximum. + * | | |When [ UDS, DS1, DS0 ] are "000", the driver strength is the minimum. + * |[4] |UDS4 |Port A-N Pin[n] Ultra Driver Strength Control Register + * | | |Determine each driver strength of Px.n pins. + * | | |0 = Px.n is minimum deiver strength. + * | | |1 = Px.n is maximum deiver strength. + * | | |Note: The UDS and DS bits are Px.n driver strength control bits. + * | | |When [ UDS, DS1, DS0 ] are "111", the driver strength is the maximum. + * | | |When [ UDS, DS1, DS0 ] are "000", the driver strength is the minimum. + * |[5] |UDS5 |Port A-N Pin[n] Ultra Driver Strength Control Register + * | | |Determine each driver strength of Px.n pins. + * | | |0 = Px.n is minimum deiver strength. + * | | |1 = Px.n is maximum deiver strength. + * | | |Note: The UDS and DS bits are Px.n driver strength control bits. + * | | |When [ UDS, DS1, DS0 ] are "111", the driver strength is the maximum. + * | | |When [ UDS, DS1, DS0 ] are "000", the driver strength is the minimum. + * |[6] |UDS6 |Port A-N Pin[n] Ultra Driver Strength Control Register + * | | |Determine each driver strength of Px.n pins. + * | | |0 = Px.n is minimum deiver strength. + * | | |1 = Px.n is maximum deiver strength. + * | | |Note: The UDS and DS bits are Px.n driver strength control bits. + * | | |When [ UDS, DS1, DS0 ] are "111", the driver strength is the maximum. + * | | |When [ UDS, DS1, DS0 ] are "000", the driver strength is the minimum. + * |[7] |UDS7 |Port A-N Pin[n] Ultra Driver Strength Control Register + * | | |Determine each driver strength of Px.n pins. + * | | |0 = Px.n is minimum deiver strength. + * | | |1 = Px.n is maximum deiver strength. + * | | |Note: The UDS and DS bits are Px.n driver strength control bits. + * | | |When [ UDS, DS1, DS0 ] are "111", the driver strength is the maximum. + * | | |When [ UDS, DS1, DS0 ] are "000", the driver strength is the minimum. + * |[8] |UDS8 |Port A-N Pin[n] Ultra Driver Strength Control Register + * | | |Determine each driver strength of Px.n pins. + * | | |0 = Px.n is minimum deiver strength. + * | | |1 = Px.n is maximum deiver strength. + * | | |Note: The UDS and DS bits are Px.n driver strength control bits. + * | | |When [ UDS, DS1, DS0 ] are "111", the driver strength is the maximum. + * | | |When [ UDS, DS1, DS0 ] are "000", the driver strength is the minimum. + * |[9] |UDS9 |Port A-N Pin[n] Ultra Driver Strength Control Register + * | | |Determine each driver strength of Px.n pins. + * | | |0 = Px.n is minimum deiver strength. + * | | |1 = Px.n is maximum deiver strength. + * | | |Note: The UDS and DS bits are Px.n driver strength control bits. + * | | |When [ UDS, DS1, DS0 ] are "111", the driver strength is the maximum. + * | | |When [ UDS, DS1, DS0 ] are "000", the driver strength is the minimum. + * |[10] |UDS10 |Port A-N Pin[n] Ultra Driver Strength Control Register + * | | |Determine each driver strength of Px.n pins. + * | | |0 = Px.n is minimum deiver strength. + * | | |1 = Px.n is maximum deiver strength. + * | | |Note: The UDS and DS bits are Px.n driver strength control bits. + * | | |When [ UDS, DS1, DS0 ] are "111", the driver strength is the maximum. + * | | |When [ UDS, DS1, DS0 ] are "000", the driver strength is the minimum. + * |[11] |UDS11 |Port A-N Pin[n] Ultra Driver Strength Control Register + * | | |Determine each driver strength of Px.n pins. + * | | |0 = Px.n is minimum deiver strength. + * | | |1 = Px.n is maximum deiver strength. + * | | |Note: The UDS and DS bits are Px.n driver strength control bits. + * | | |When [ UDS, DS1, DS0 ] are "111", the driver strength is the maximum. + * | | |When [ UDS, DS1, DS0 ] are "000", the driver strength is the minimum. + * |[12] |UDS12 |Port A-N Pin[n] Ultra Driver Strength Control Register + * | | |Determine each driver strength of Px.n pins. + * | | |0 = Px.n is minimum deiver strength. + * | | |1 = Px.n is maximum deiver strength. + * | | |Note: The UDS and DS bits are Px.n driver strength control bits. + * | | |When [ UDS, DS1, DS0 ] are "111", the driver strength is the maximum. + * | | |When [ UDS, DS1, DS0 ] are "000", the driver strength is the minimum. + * |[13] |UDS13 |Port A-N Pin[n] Ultra Driver Strength Control Register + * | | |Determine each driver strength of Px.n pins. + * | | |0 = Px.n is minimum deiver strength. + * | | |1 = Px.n is maximum deiver strength. + * | | |Note: The UDS and DS bits are Px.n driver strength control bits. + * | | |When [ UDS, DS1, DS0 ] are "111", the driver strength is the maximum. + * | | |When [ UDS, DS1, DS0 ] are "000", the driver strength is the minimum. + * |[14] |UDS14 |Port A-N Pin[n] Ultra Driver Strength Control Register + * | | |Determine each driver strength of Px.n pins. + * | | |0 = Px.n is minimum deiver strength. + * | | |1 = Px.n is maximum deiver strength. + * | | |Note: The UDS and DS bits are Px.n driver strength control bits. + * | | |When [ UDS, DS1, DS0 ] are "111", the driver strength is the maximum. + * | | |When [ UDS, DS1, DS0 ] are "000", the driver strength is the minimum. + * |[15] |UDS15 |Port A-N Pin[n] Ultra Driver Strength Control Register + * | | |Determine each driver strength of Px.n pins. + * | | |0 = Px.n is minimum deiver strength. + * | | |1 = Px.n is maximum deiver strength. + * | | |Note: The UDS and DS bits are Px.n driver strength control bits. + * | | |When [ UDS, DS1, DS0 ] are "111", the driver strength is the maximum. + * | | |When [ UDS, DS1, DS0 ] are "000", the driver strength is the minimum. + */ + + __IO uint32_t MODE; /* Offset: 0x00/0x40/0x80/0xC0/0x100/0x140/0x180/0x1C0/0x200/0x240/0x280/0x2C0/0x300/0x340 Port A-N I/O Mode Control */ + __IO uint32_t DINOFF; /* Offset: 0x04/0x44/0x84/0xC4/0x104/0x144/0x184/0x1C4/0x204/0x244/0x284/0x2C4/0x304/0x344 Port A-N Digital Input Path Disable Control */ + __IO uint32_t DOUT; /* Offset: 0x08/0x48/0x88/0xC8/0x108/0x148/0x188/0x1C8/0x208/0x248/0x288/0x2C8/0x308/0x348 Port A-N Data Output Value */ + __IO uint32_t DATMSK; /* Offset: 0x0C/0x4C/0x8C/0xCC/0x10C/0x14C/0x18C/0x1CC/0x20C/0x24C/0x28C/0x2CC/0x30C/0x34C Port A-N Data Output Write Mask */ + __I uint32_t PIN; /* Offset: 0x10/0x50/0x90/0xD0/0x110/0x150/0x190/0x1D0/0x210/0x250/0x290/0x2D0/0x310/0x350 Port A-N Pin Value */ + __IO uint32_t DBEN; /* Offset: 0x14/0x54/0x94/0xD4/0x114/0x154/0x194/0x1D4/0x214/0x254/0x294/0x2D4/0x314/0x354 Port A-N De-Bounce Enable Control Register */ + __IO uint32_t INTTYPE; /* Offset: 0x18/0x58/0x98/0xD8/0x118/0x158/0x198/0x1D8/0x218/0x258/0x298/0x2D8/0x318/0x358 Port A-N Interrupt Trigger Type Control */ + __IO uint32_t INTEN; /* Offset: 0x1C/0x5C/0x9C/0xDC/0x11C/0x15C/0x19C/0x1DC/0x21C/0x25C/0x29C/0x2DC/0x31C/0x35C Port A-N Interrupt Enable Control Register */ + __IO uint32_t INTSRC; /* Offset: 0x20/0x60/0xA0/0xE0/0x120/0x160/0x1A0/0x1E0/0x220/0x260/0x2A0/0x2E0/0x320/0x360 Port A-N Interrupt Source Flag */ + __IO uint32_t SMTEN; /* Offset: 0x24/0x64/0xA4/0xE4/0x124/0x164/0x1A4/0x1E4/0x224/0x264/0x2A4/0x2E4/0x324/0x364 Port A-N Input Schmitt Trigger Enable Register */ + __IO uint32_t SLEWCTL; /* Offset: 0x28/0x68/0xA8/0xE8/0x128/0x168/0x1A8/0x1E8/0x228/0x268/0x2A8/0x2E8/0x328/0x368 Port A-N High Slew Rate Control Register */ + __IO uint32_t SPW; /* Offset: 0x06C/0xAC/0xEC/0x12C/0x16C/0x1AC/0x26C/0x2AC/0x36C */ + __IO uint32_t PUSEL; /* Offset: 0x30/0x70/0xB0/0xF0/0x130/0x170/0x1B0/0x1F0/0x230/0x270/0x2B0/0x2F0/0x330/0x370 Port A-N Pull-up and Pull-down Enable Register */ + __IO uint32_t DBCTL; /* Offset: 0x34/0x74/0xB4/0xF4/0x134/0x174/0x1B4/0x1F4/0x234/0x274/0x2B4/0x2F4/0x334/0x374 Port A-N Interrupt De-bounce Control Register */ + __IO uint32_t DSL; /* Offset: 0x38/0x78/0xB8/0xF8/0x138/0x178/0x1B8/0x1F8/0x238/0x278/0x2B8/0x2F8/0x338/0x378 Port A-N Low-byte Driver Strength Control Register */ + __IO uint32_t DSH; /* Offset: 0x3c/0x7C/0xBC/0xFC/0x13C/0x17C/0x1BC/0x1FC/0x23C/0x27C/0x2BC/0x2FC/0x33C/0x37C Port A-N High-byte Driver Strength Control Register */ +} GPIO_T; + +/** + @addtogroup GPIO_CONST GPIO Bit Field Definition + Constant Definitions for GPIO Controller +@{ */ + +#define GPIO_MODE_MODE0_Pos (0) /*!< GPIO_T::MODE: MODE0 Position */ +#define GPIO_MODE_MODE0_Msk (0x3ul << GPIO_MODE_MODE0_Pos) /*!< GPIO_T::MODE: MODE0 Mask */ + +#define GPIO_MODE_MODE1_Pos (2) /*!< GPIO_T::MODE: MODE1 Position */ +#define GPIO_MODE_MODE1_Msk (0x3ul << GPIO_MODE_MODE1_Pos) /*!< GPIO_T::MODE: MODE1 Mask */ + +#define GPIO_MODE_MODE2_Pos (4) /*!< GPIO_T::MODE: MODE2 Position */ +#define GPIO_MODE_MODE2_Msk (0x3ul << GPIO_MODE_MODE2_Pos) /*!< GPIO_T::MODE: MODE2 Mask */ + +#define GPIO_MODE_MODE3_Pos (6) /*!< GPIO_T::MODE: MODE3 Position */ +#define GPIO_MODE_MODE3_Msk (0x3ul << GPIO_MODE_MODE3_Pos) /*!< GPIO_T::MODE: MODE3 Mask */ + +#define GPIO_MODE_MODE4_Pos (8) /*!< GPIO_T::MODE: MODE4 Position */ +#define GPIO_MODE_MODE4_Msk (0x3ul << GPIO_MODE_MODE4_Pos) /*!< GPIO_T::MODE: MODE4 Mask */ + +#define GPIO_MODE_MODE5_Pos (10) /*!< GPIO_T::MODE: MODE5 Position */ +#define GPIO_MODE_MODE5_Msk (0x3ul << GPIO_MODE_MODE5_Pos) /*!< GPIO_T::MODE: MODE5 Mask */ + +#define GPIO_MODE_MODE6_Pos (12) /*!< GPIO_T::MODE: MODE6 Position */ +#define GPIO_MODE_MODE6_Msk (0x3ul << GPIO_MODE_MODE6_Pos) /*!< GPIO_T::MODE: MODE6 Mask */ + +#define GPIO_MODE_MODE7_Pos (14) /*!< GPIO_T::MODE: MODE7 Position */ +#define GPIO_MODE_MODE7_Msk (0x3ul << GPIO_MODE_MODE7_Pos) /*!< GPIO_T::MODE: MODE7 Mask */ + +#define GPIO_MODE_MODE8_Pos (16) /*!< GPIO_T::MODE: MODE8 Position */ +#define GPIO_MODE_MODE8_Msk (0x3ul << GPIO_MODE_MODE8_Pos) /*!< GPIO_T::MODE: MODE8 Mask */ + +#define GPIO_MODE_MODE9_Pos (18) /*!< GPIO_T::MODE: MODE9 Position */ +#define GPIO_MODE_MODE9_Msk (0x3ul << GPIO_MODE_MODE9_Pos) /*!< GPIO_T::MODE: MODE9 Mask */ + +#define GPIO_MODE_MODE10_Pos (20) /*!< GPIO_T::MODE: MODE10 Position */ +#define GPIO_MODE_MODE10_Msk (0x3ul << GPIO_MODE_MODE10_Pos) /*!< GPIO_T::MODE: MODE10 Mask */ + +#define GPIO_MODE_MODE11_Pos (22) /*!< GPIO_T::MODE: MODE11 Position */ +#define GPIO_MODE_MODE11_Msk (0x3ul << GPIO_MODE_MODE11_Pos) /*!< GPIO_T::MODE: MODE11 Mask */ + +#define GPIO_MODE_MODE12_Pos (24) /*!< GPIO_T::MODE: MODE12 Position */ +#define GPIO_MODE_MODE12_Msk (0x3ul << GPIO_MODE_MODE12_Pos) /*!< GPIO_T::MODE: MODE12 Mask */ + +#define GPIO_MODE_MODE13_Pos (26) /*!< GPIO_T::MODE: MODE13 Position */ +#define GPIO_MODE_MODE13_Msk (0x3ul << GPIO_MODE_MODE13_Pos) /*!< GPIO_T::MODE: MODE13 Mask */ + +#define GPIO_MODE_MODE14_Pos (28) /*!< GPIO_T::MODE: MODE14 Position */ +#define GPIO_MODE_MODE14_Msk (0x3ul << GPIO_MODE_MODE14_Pos) /*!< GPIO_T::MODE: MODE14 Mask */ + +#define GPIO_MODE_MODE15_Pos (30) /*!< GPIO_T::MODE: MODE15 Position */ +#define GPIO_MODE_MODE15_Msk (0x3ul << GPIO_MODE_MODE15_Pos) /*!< GPIO_T::MODE: MODE15 Mask */ + +#define GPIO_DINOFF_DINOFF0_Pos (16) /*!< GPIO_T::DINOFF: DINOFF0 Position */ +#define GPIO_DINOFF_DINOFF0_Msk (0x1ul << GPIO_DINOFF_DINOFF0_Pos) /*!< GPIO_T::DINOFF: DINOFF0 Mask */ + +#define GPIO_DINOFF_DINOFF1_Pos (17) /*!< GPIO_T::DINOFF: DINOFF1 Position */ +#define GPIO_DINOFF_DINOFF1_Msk (0x1ul << GPIO_DINOFF_DINOFF1_Pos) /*!< GPIO_T::DINOFF: DINOFF1 Mask */ + +#define GPIO_DINOFF_DINOFF2_Pos (18) /*!< GPIO_T::DINOFF: DINOFF2 Position */ +#define GPIO_DINOFF_DINOFF2_Msk (0x1ul << GPIO_DINOFF_DINOFF2_Pos) /*!< GPIO_T::DINOFF: DINOFF2 Mask */ + +#define GPIO_DINOFF_DINOFF3_Pos (19) /*!< GPIO_T::DINOFF: DINOFF3 Position */ +#define GPIO_DINOFF_DINOFF3_Msk (0x1ul << GPIO_DINOFF_DINOFF3_Pos) /*!< GPIO_T::DINOFF: DINOFF3 Mask */ + +#define GPIO_DINOFF_DINOFF4_Pos (20) /*!< GPIO_T::DINOFF: DINOFF4 Position */ +#define GPIO_DINOFF_DINOFF4_Msk (0x1ul << GPIO_DINOFF_DINOFF4_Pos) /*!< GPIO_T::DINOFF: DINOFF4 Mask */ + +#define GPIO_DINOFF_DINOFF5_Pos (21) /*!< GPIO_T::DINOFF: DINOFF5 Position */ +#define GPIO_DINOFF_DINOFF5_Msk (0x1ul << GPIO_DINOFF_DINOFF5_Pos) /*!< GPIO_T::DINOFF: DINOFF5 Mask */ + +#define GPIO_DINOFF_DINOFF6_Pos (22) /*!< GPIO_T::DINOFF: DINOFF6 Position */ +#define GPIO_DINOFF_DINOFF6_Msk (0x1ul << GPIO_DINOFF_DINOFF6_Pos) /*!< GPIO_T::DINOFF: DINOFF6 Mask */ + +#define GPIO_DINOFF_DINOFF7_Pos (23) /*!< GPIO_T::DINOFF: DINOFF7 Position */ +#define GPIO_DINOFF_DINOFF7_Msk (0x1ul << GPIO_DINOFF_DINOFF7_Pos) /*!< GPIO_T::DINOFF: DINOFF7 Mask */ + +#define GPIO_DINOFF_DINOFF8_Pos (24) /*!< GPIO_T::DINOFF: DINOFF8 Position */ +#define GPIO_DINOFF_DINOFF8_Msk (0x1ul << GPIO_DINOFF_DINOFF8_Pos) /*!< GPIO_T::DINOFF: DINOFF8 Mask */ + +#define GPIO_DINOFF_DINOFF9_Pos (25) /*!< GPIO_T::DINOFF: DINOFF9 Position */ +#define GPIO_DINOFF_DINOFF9_Msk (0x1ul << GPIO_DINOFF_DINOFF9_Pos) /*!< GPIO_T::DINOFF: DINOFF9 Mask */ + +#define GPIO_DINOFF_DINOFF10_Pos (26) /*!< GPIO_T::DINOFF: DINOFF10 Position */ +#define GPIO_DINOFF_DINOFF10_Msk (0x1ul << GPIO_DINOFF_DINOFF10_Pos) /*!< GPIO_T::DINOFF: DINOFF10 Mask */ + +#define GPIO_DINOFF_DINOFF11_Pos (27) /*!< GPIO_T::DINOFF: DINOFF11 Position */ +#define GPIO_DINOFF_DINOFF11_Msk (0x1ul << GPIO_DINOFF_DINOFF11_Pos) /*!< GPIO_T::DINOFF: DINOFF11 Mask */ + +#define GPIO_DINOFF_DINOFF12_Pos (28) /*!< GPIO_T::DINOFF: DINOFF12 Position */ +#define GPIO_DINOFF_DINOFF12_Msk (0x1ul << GPIO_DINOFF_DINOFF12_Pos) /*!< GPIO_T::DINOFF: DINOFF12 Mask */ + +#define GPIO_DINOFF_DINOFF13_Pos (29) /*!< GPIO_T::DINOFF: DINOFF13 Position */ +#define GPIO_DINOFF_DINOFF13_Msk (0x1ul << GPIO_DINOFF_DINOFF13_Pos) /*!< GPIO_T::DINOFF: DINOFF13 Mask */ + +#define GPIO_DINOFF_DINOFF14_Pos (30) /*!< GPIO_T::DINOFF: DINOFF14 Position */ +#define GPIO_DINOFF_DINOFF14_Msk (0x1ul << GPIO_DINOFF_DINOFF14_Pos) /*!< GPIO_T::DINOFF: DINOFF14 Mask */ + +#define GPIO_DINOFF_DINOFF15_Pos (31) /*!< GPIO_T::DINOFF: DINOFF15 Position */ +#define GPIO_DINOFF_DINOFF15_Msk (0x1ul << GPIO_DINOFF_DINOFF15_Pos) /*!< GPIO_T::DINOFF: DINOFF15 Mask */ + +#define GPIO_DOUT_DOUT0_Pos (0) /*!< GPIO_T::DOUT: DOUT0 Position */ +#define GPIO_DOUT_DOUT0_Msk (0x1ul << GPIO_DOUT_DOUT0_Pos) /*!< GPIO_T::DOUT: DOUT0 Mask */ + +#define GPIO_DOUT_DOUT1_Pos (1) /*!< GPIO_T::DOUT: DOUT1 Position */ +#define GPIO_DOUT_DOUT1_Msk (0x1ul << GPIO_DOUT_DOUT1_Pos) /*!< GPIO_T::DOUT: DOUT1 Mask */ + +#define GPIO_DOUT_DOUT2_Pos (2) /*!< GPIO_T::DOUT: DOUT2 Position */ +#define GPIO_DOUT_DOUT2_Msk (0x1ul << GPIO_DOUT_DOUT2_Pos) /*!< GPIO_T::DOUT: DOUT2 Mask */ + +#define GPIO_DOUT_DOUT3_Pos (3) /*!< GPIO_T::DOUT: DOUT3 Position */ +#define GPIO_DOUT_DOUT3_Msk (0x1ul << GPIO_DOUT_DOUT3_Pos) /*!< GPIO_T::DOUT: DOUT3 Mask */ + +#define GPIO_DOUT_DOUT4_Pos (4) /*!< GPIO_T::DOUT: DOUT4 Position */ +#define GPIO_DOUT_DOUT4_Msk (0x1ul << GPIO_DOUT_DOUT4_Pos) /*!< GPIO_T::DOUT: DOUT4 Mask */ + +#define GPIO_DOUT_DOUT5_Pos (5) /*!< GPIO_T::DOUT: DOUT5 Position */ +#define GPIO_DOUT_DOUT5_Msk (0x1ul << GPIO_DOUT_DOUT5_Pos) /*!< GPIO_T::DOUT: DOUT5 Mask */ + +#define GPIO_DOUT_DOUT6_Pos (6) /*!< GPIO_T::DOUT: DOUT6 Position */ +#define GPIO_DOUT_DOUT6_Msk (0x1ul << GPIO_DOUT_DOUT6_Pos) /*!< GPIO_T::DOUT: DOUT6 Mask */ + +#define GPIO_DOUT_DOUT7_Pos (7) /*!< GPIO_T::DOUT: DOUT7 Position */ +#define GPIO_DOUT_DOUT7_Msk (0x1ul << GPIO_DOUT_DOUT7_Pos) /*!< GPIO_T::DOUT: DOUT7 Mask */ + +#define GPIO_DOUT_DOUT8_Pos (8) /*!< GPIO_T::DOUT: DOUT8 Position */ +#define GPIO_DOUT_DOUT8_Msk (0x1ul << GPIO_DOUT_DOUT8_Pos) /*!< GPIO_T::DOUT: DOUT8 Mask */ + +#define GPIO_DOUT_DOUT9_Pos (9) /*!< GPIO_T::DOUT: DOUT9 Position */ +#define GPIO_DOUT_DOUT9_Msk (0x1ul << GPIO_DOUT_DOUT9_Pos) /*!< GPIO_T::DOUT: DOUT9 Mask */ + +#define GPIO_DOUT_DOUT10_Pos (10) /*!< GPIO_T::DOUT: DOUT10 Position */ +#define GPIO_DOUT_DOUT10_Msk (0x1ul << GPIO_DOUT_DOUT10_Pos) /*!< GPIO_T::DOUT: DOUT10 Mask */ + +#define GPIO_DOUT_DOUT11_Pos (11) /*!< GPIO_T::DOUT: DOUT11 Position */ +#define GPIO_DOUT_DOUT11_Msk (0x1ul << GPIO_DOUT_DOUT11_Pos) /*!< GPIO_T::DOUT: DOUT11 Mask */ + +#define GPIO_DOUT_DOUT12_Pos (12) /*!< GPIO_T::DOUT: DOUT12 Position */ +#define GPIO_DOUT_DOUT12_Msk (0x1ul << GPIO_DOUT_DOUT12_Pos) /*!< GPIO_T::DOUT: DOUT12 Mask */ + +#define GPIO_DOUT_DOUT13_Pos (13) /*!< GPIO_T::DOUT: DOUT13 Position */ +#define GPIO_DOUT_DOUT13_Msk (0x1ul << GPIO_DOUT_DOUT13_Pos) /*!< GPIO_T::DOUT: DOUT13 Mask */ + +#define GPIO_DOUT_DOUT14_Pos (14) /*!< GPIO_T::DOUT: DOUT14 Position */ +#define GPIO_DOUT_DOUT14_Msk (0x1ul << GPIO_DOUT_DOUT14_Pos) /*!< GPIO_T::DOUT: DOUT14 Mask */ + +#define GPIO_DOUT_DOUT15_Pos (15) /*!< GPIO_T::DOUT: DOUT15 Position */ +#define GPIO_DOUT_DOUT15_Msk (0x1ul << GPIO_DOUT_DOUT15_Pos) /*!< GPIO_T::DOUT: DOUT15 Mask */ + +#define GPIO_DATMSK_DATMSK0_Pos (0) /*!< GPIO_T::DATMSK: DATMSK0 Position */ +#define GPIO_DATMSK_DATMSK0_Msk (0x1ul << GPIO_DATMSK_DATMSK0_Pos) /*!< GPIO_T::DATMSK: DATMSK0 Mask */ + +#define GPIO_DATMSK_DATMSK1_Pos (1) /*!< GPIO_T::DATMSK: DATMSK1 Position */ +#define GPIO_DATMSK_DATMSK1_Msk (0x1ul << GPIO_DATMSK_DATMSK1_Pos) /*!< GPIO_T::DATMSK: DATMSK1 Mask */ + +#define GPIO_DATMSK_DATMSK2_Pos (2) /*!< GPIO_T::DATMSK: DATMSK2 Position */ +#define GPIO_DATMSK_DATMSK2_Msk (0x1ul << GPIO_DATMSK_DATMSK2_Pos) /*!< GPIO_T::DATMSK: DATMSK2 Mask */ + +#define GPIO_DATMSK_DATMSK3_Pos (3) /*!< GPIO_T::DATMSK: DATMSK3 Position */ +#define GPIO_DATMSK_DATMSK3_Msk (0x1ul << GPIO_DATMSK_DATMSK3_Pos) /*!< GPIO_T::DATMSK: DATMSK3 Mask */ + +#define GPIO_DATMSK_DATMSK4_Pos (4) /*!< GPIO_T::DATMSK: DATMSK4 Position */ +#define GPIO_DATMSK_DATMSK4_Msk (0x1ul << GPIO_DATMSK_DATMSK4_Pos) /*!< GPIO_T::DATMSK: DATMSK4 Mask */ + +#define GPIO_DATMSK_DATMSK5_Pos (5) /*!< GPIO_T::DATMSK: DATMSK5 Position */ +#define GPIO_DATMSK_DATMSK5_Msk (0x1ul << GPIO_DATMSK_DATMSK5_Pos) /*!< GPIO_T::DATMSK: DATMSK5 Mask */ + +#define GPIO_DATMSK_DATMSK6_Pos (6) /*!< GPIO_T::DATMSK: DATMSK6 Position */ +#define GPIO_DATMSK_DATMSK6_Msk (0x1ul << GPIO_DATMSK_DATMSK6_Pos) /*!< GPIO_T::DATMSK: DATMSK6 Mask */ + +#define GPIO_DATMSK_DATMSK7_Pos (7) /*!< GPIO_T::DATMSK: DATMSK7 Position */ +#define GPIO_DATMSK_DATMSK7_Msk (0x1ul << GPIO_DATMSK_DATMSK7_Pos) /*!< GPIO_T::DATMSK: DATMSK7 Mask */ + +#define GPIO_DATMSK_DATMSK8_Pos (8) /*!< GPIO_T::DATMSK: DATMSK8 Position */ +#define GPIO_DATMSK_DATMSK8_Msk (0x1ul << GPIO_DATMSK_DATMSK8_Pos) /*!< GPIO_T::DATMSK: DATMSK8 Mask */ + +#define GPIO_DATMSK_DATMSK9_Pos (9) /*!< GPIO_T::DATMSK: DATMSK9 Position */ +#define GPIO_DATMSK_DATMSK9_Msk (0x1ul << GPIO_DATMSK_DATMSK9_Pos) /*!< GPIO_T::DATMSK: DATMSK9 Mask */ + +#define GPIO_DATMSK_DATMSK10_Pos (10) /*!< GPIO_T::DATMSK: DATMSK10 Position */ +#define GPIO_DATMSK_DATMSK10_Msk (0x1ul << GPIO_DATMSK_DATMSK10_Pos) /*!< GPIO_T::DATMSK: DATMSK10 Mask */ + +#define GPIO_DATMSK_DATMSK11_Pos (11) /*!< GPIO_T::DATMSK: DATMSK11 Position */ +#define GPIO_DATMSK_DATMSK11_Msk (0x1ul << GPIO_DATMSK_DATMSK11_Pos) /*!< GPIO_T::DATMSK: DATMSK11 Mask */ + +#define GPIO_DATMSK_DATMSK12_Pos (12) /*!< GPIO_T::DATMSK: DATMSK12 Position */ +#define GPIO_DATMSK_DATMSK12_Msk (0x1ul << GPIO_DATMSK_DATMSK12_Pos) /*!< GPIO_T::DATMSK: DATMSK12 Mask */ + +#define GPIO_DATMSK_DATMSK13_Pos (13) /*!< GPIO_T::DATMSK: DATMSK13 Position */ +#define GPIO_DATMSK_DATMSK13_Msk (0x1ul << GPIO_DATMSK_DATMSK13_Pos) /*!< GPIO_T::DATMSK: DATMSK13 Mask */ + +#define GPIO_DATMSK_DATMSK14_Pos (14) /*!< GPIO_T::DATMSK: DATMSK14 Position */ +#define GPIO_DATMSK_DATMSK14_Msk (0x1ul << GPIO_DATMSK_DATMSK14_Pos) /*!< GPIO_T::DATMSK: DATMSK14 Mask */ + +#define GPIO_DATMSK_DATMSK15_Pos (15) /*!< GPIO_T::DATMSK: DATMSK15 Position */ +#define GPIO_DATMSK_DATMSK15_Msk (0x1ul << GPIO_DATMSK_DATMSK15_Pos) /*!< GPIO_T::DATMSK: DATMSK15 Mask */ + +#define GPIO_PIN_PIN0_Pos (0) /*!< GPIO_T::PIN: PIN0 Position */ +#define GPIO_PIN_PIN0_Msk (0x1ul << GPIO_PIN_PIN0_Pos) /*!< GPIO_T::PIN: PIN0 Mask */ + +#define GPIO_PIN_PIN1_Pos (1) /*!< GPIO_T::PIN: PIN1 Position */ +#define GPIO_PIN_PIN1_Msk (0x1ul << GPIO_PIN_PIN1_Pos) /*!< GPIO_T::PIN: PIN1 Mask */ + +#define GPIO_PIN_PIN2_Pos (2) /*!< GPIO_T::PIN: PIN2 Position */ +#define GPIO_PIN_PIN2_Msk (0x1ul << GPIO_PIN_PIN2_Pos) /*!< GPIO_T::PIN: PIN2 Mask */ + +#define GPIO_PIN_PIN3_Pos (3) /*!< GPIO_T::PIN: PIN3 Position */ +#define GPIO_PIN_PIN3_Msk (0x1ul << GPIO_PIN_PIN3_Pos) /*!< GPIO_T::PIN: PIN3 Mask */ + +#define GPIO_PIN_PIN4_Pos (4) /*!< GPIO_T::PIN: PIN4 Position */ +#define GPIO_PIN_PIN4_Msk (0x1ul << GPIO_PIN_PIN4_Pos) /*!< GPIO_T::PIN: PIN4 Mask */ + +#define GPIO_PIN_PIN5_Pos (5) /*!< GPIO_T::PIN: PIN5 Position */ +#define GPIO_PIN_PIN5_Msk (0x1ul << GPIO_PIN_PIN5_Pos) /*!< GPIO_T::PIN: PIN5 Mask */ + +#define GPIO_PIN_PIN6_Pos (6) /*!< GPIO_T::PIN: PIN6 Position */ +#define GPIO_PIN_PIN6_Msk (0x1ul << GPIO_PIN_PIN6_Pos) /*!< GPIO_T::PIN: PIN6 Mask */ + +#define GPIO_PIN_PIN7_Pos (7) /*!< GPIO_T::PIN: PIN7 Position */ +#define GPIO_PIN_PIN7_Msk (0x1ul << GPIO_PIN_PIN7_Pos) /*!< GPIO_T::PIN: PIN7 Mask */ + +#define GPIO_PIN_PIN8_Pos (8) /*!< GPIO_T::PIN: PIN8 Position */ +#define GPIO_PIN_PIN8_Msk (0x1ul << GPIO_PIN_PIN8_Pos) /*!< GPIO_T::PIN: PIN8 Mask */ + +#define GPIO_PIN_PIN9_Pos (9) /*!< GPIO_T::PIN: PIN9 Position */ +#define GPIO_PIN_PIN9_Msk (0x1ul << GPIO_PIN_PIN9_Pos) /*!< GPIO_T::PIN: PIN9 Mask */ + +#define GPIO_PIN_PIN10_Pos (10) /*!< GPIO_T::PIN: PIN10 Position */ +#define GPIO_PIN_PIN10_Msk (0x1ul << GPIO_PIN_PIN10_Pos) /*!< GPIO_T::PIN: PIN10 Mask */ + +#define GPIO_PIN_PIN11_Pos (11) /*!< GPIO_T::PIN: PIN11 Position */ +#define GPIO_PIN_PIN11_Msk (0x1ul << GPIO_PIN_PIN11_Pos) /*!< GPIO_T::PIN: PIN11 Mask */ + +#define GPIO_PIN_PIN12_Pos (12) /*!< GPIO_T::PIN: PIN12 Position */ +#define GPIO_PIN_PIN12_Msk (0x1ul << GPIO_PIN_PIN12_Pos) /*!< GPIO_T::PIN: PIN12 Mask */ + +#define GPIO_PIN_PIN13_Pos (13) /*!< GPIO_T::PIN: PIN13 Position */ +#define GPIO_PIN_PIN13_Msk (0x1ul << GPIO_PIN_PIN13_Pos) /*!< GPIO_T::PIN: PIN13 Mask */ + +#define GPIO_PIN_PIN14_Pos (14) /*!< GPIO_T::PIN: PIN14 Position */ +#define GPIO_PIN_PIN14_Msk (0x1ul << GPIO_PIN_PIN14_Pos) /*!< GPIO_T::PIN: PIN14 Mask */ + +#define GPIO_PIN_PIN15_Pos (15) /*!< GPIO_T::PIN: PIN15 Position */ +#define GPIO_PIN_PIN15_Msk (0x1ul << GPIO_PIN_PIN15_Pos) /*!< GPIO_T::PIN: PIN15 Mask */ + +#define GPIO_DBEN_DBEN0_Pos (0) /*!< GPIO_T::DBEN: DBEN0 Position */ +#define GPIO_DBEN_DBEN0_Msk (0x1ul << GPIO_DBEN_DBEN0_Pos) /*!< GPIO_T::DBEN: DBEN0 Mask */ + +#define GPIO_DBEN_DBEN1_Pos (1) /*!< GPIO_T::DBEN: DBEN1 Position */ +#define GPIO_DBEN_DBEN1_Msk (0x1ul << GPIO_DBEN_DBEN1_Pos) /*!< GPIO_T::DBEN: DBEN1 Mask */ + +#define GPIO_DBEN_DBEN2_Pos (2) /*!< GPIO_T::DBEN: DBEN2 Position */ +#define GPIO_DBEN_DBEN2_Msk (0x1ul << GPIO_DBEN_DBEN2_Pos) /*!< GPIO_T::DBEN: DBEN2 Mask */ + +#define GPIO_DBEN_DBEN3_Pos (3) /*!< GPIO_T::DBEN: DBEN3 Position */ +#define GPIO_DBEN_DBEN3_Msk (0x1ul << GPIO_DBEN_DBEN3_Pos) /*!< GPIO_T::DBEN: DBEN3 Mask */ + +#define GPIO_DBEN_DBEN4_Pos (4) /*!< GPIO_T::DBEN: DBEN4 Position */ +#define GPIO_DBEN_DBEN4_Msk (0x1ul << GPIO_DBEN_DBEN4_Pos) /*!< GPIO_T::DBEN: DBEN4 Mask */ + +#define GPIO_DBEN_DBEN5_Pos (5) /*!< GPIO_T::DBEN: DBEN5 Position */ +#define GPIO_DBEN_DBEN5_Msk (0x1ul << GPIO_DBEN_DBEN5_Pos) /*!< GPIO_T::DBEN: DBEN5 Mask */ + +#define GPIO_DBEN_DBEN6_Pos (6) /*!< GPIO_T::DBEN: DBEN6 Position */ +#define GPIO_DBEN_DBEN6_Msk (0x1ul << GPIO_DBEN_DBEN6_Pos) /*!< GPIO_T::DBEN: DBEN6 Mask */ + +#define GPIO_DBEN_DBEN7_Pos (7) /*!< GPIO_T::DBEN: DBEN7 Position */ +#define GPIO_DBEN_DBEN7_Msk (0x1ul << GPIO_DBEN_DBEN7_Pos) /*!< GPIO_T::DBEN: DBEN7 Mask */ + +#define GPIO_DBEN_DBEN8_Pos (8) /*!< GPIO_T::DBEN: DBEN8 Position */ +#define GPIO_DBEN_DBEN8_Msk (0x1ul << GPIO_DBEN_DBEN8_Pos) /*!< GPIO_T::DBEN: DBEN8 Mask */ + +#define GPIO_DBEN_DBEN9_Pos (9) /*!< GPIO_T::DBEN: DBEN9 Position */ +#define GPIO_DBEN_DBEN9_Msk (0x1ul << GPIO_DBEN_DBEN9_Pos) /*!< GPIO_T::DBEN: DBEN9 Mask */ + +#define GPIO_DBEN_DBEN10_Pos (10) /*!< GPIO_T::DBEN: DBEN10 Position */ +#define GPIO_DBEN_DBEN10_Msk (0x1ul << GPIO_DBEN_DBEN10_Pos) /*!< GPIO_T::DBEN: DBEN10 Mask */ + +#define GPIO_DBEN_DBEN11_Pos (11) /*!< GPIO_T::DBEN: DBEN11 Position */ +#define GPIO_DBEN_DBEN11_Msk (0x1ul << GPIO_DBEN_DBEN11_Pos) /*!< GPIO_T::DBEN: DBEN11 Mask */ + +#define GPIO_DBEN_DBEN12_Pos (12) /*!< GPIO_T::DBEN: DBEN12 Position */ +#define GPIO_DBEN_DBEN12_Msk (0x1ul << GPIO_DBEN_DBEN12_Pos) /*!< GPIO_T::DBEN: DBEN12 Mask */ + +#define GPIO_DBEN_DBEN13_Pos (13) /*!< GPIO_T::DBEN: DBEN13 Position */ +#define GPIO_DBEN_DBEN13_Msk (0x1ul << GPIO_DBEN_DBEN13_Pos) /*!< GPIO_T::DBEN: DBEN13 Mask */ + +#define GPIO_DBEN_DBEN14_Pos (14) /*!< GPIO_T::DBEN: DBEN14 Position */ +#define GPIO_DBEN_DBEN14_Msk (0x1ul << GPIO_DBEN_DBEN14_Pos) /*!< GPIO_T::DBEN: DBEN14 Mask */ + +#define GPIO_DBEN_DBEN15_Pos (15) /*!< GPIO_T::DBEN: DBEN15 Position */ +#define GPIO_DBEN_DBEN15_Msk (0x1ul << GPIO_DBEN_DBEN15_Pos) /*!< GPIO_T::DBEN: DBEN15 Mask */ + +#define GPIO_INTTYPE_TYPE0_Pos (0) /*!< GPIO_T::INTTYPE: TYPE0 Position */ +#define GPIO_INTTYPE_TYPE0_Msk (0x1ul << GPIO_INTTYPE_TYPE0_Pos) /*!< GPIO_T::INTTYPE: TYPE0 Mask */ + +#define GPIO_INTTYPE_TYPE1_Pos (1) /*!< GPIO_T::INTTYPE: TYPE1 Position */ +#define GPIO_INTTYPE_TYPE1_Msk (0x1ul << GPIO_INTTYPE_TYPE1_Pos) /*!< GPIO_T::INTTYPE: TYPE1 Mask */ + +#define GPIO_INTTYPE_TYPE2_Pos (2) /*!< GPIO_T::INTTYPE: TYPE2 Position */ +#define GPIO_INTTYPE_TYPE2_Msk (0x1ul << GPIO_INTTYPE_TYPE2_Pos) /*!< GPIO_T::INTTYPE: TYPE2 Mask */ + +#define GPIO_INTTYPE_TYPE3_Pos (3) /*!< GPIO_T::INTTYPE: TYPE3 Position */ +#define GPIO_INTTYPE_TYPE3_Msk (0x1ul << GPIO_INTTYPE_TYPE3_Pos) /*!< GPIO_T::INTTYPE: TYPE3 Mask */ + +#define GPIO_INTTYPE_TYPE4_Pos (4) /*!< GPIO_T::INTTYPE: TYPE4 Position */ +#define GPIO_INTTYPE_TYPE4_Msk (0x1ul << GPIO_INTTYPE_TYPE4_Pos) /*!< GPIO_T::INTTYPE: TYPE4 Mask */ + +#define GPIO_INTTYPE_TYPE5_Pos (5) /*!< GPIO_T::INTTYPE: TYPE5 Position */ +#define GPIO_INTTYPE_TYPE5_Msk (0x1ul << GPIO_INTTYPE_TYPE5_Pos) /*!< GPIO_T::INTTYPE: TYPE5 Mask */ + +#define GPIO_INTTYPE_TYPE6_Pos (6) /*!< GPIO_T::INTTYPE: TYPE6 Position */ +#define GPIO_INTTYPE_TYPE6_Msk (0x1ul << GPIO_INTTYPE_TYPE6_Pos) /*!< GPIO_T::INTTYPE: TYPE6 Mask */ + +#define GPIO_INTTYPE_TYPE7_Pos (7) /*!< GPIO_T::INTTYPE: TYPE7 Position */ +#define GPIO_INTTYPE_TYPE7_Msk (0x1ul << GPIO_INTTYPE_TYPE7_Pos) /*!< GPIO_T::INTTYPE: TYPE7 Mask */ + +#define GPIO_INTTYPE_TYPE8_Pos (8) /*!< GPIO_T::INTTYPE: TYPE8 Position */ +#define GPIO_INTTYPE_TYPE8_Msk (0x1ul << GPIO_INTTYPE_TYPE8_Pos) /*!< GPIO_T::INTTYPE: TYPE8 Mask */ + +#define GPIO_INTTYPE_TYPE9_Pos (9) /*!< GPIO_T::INTTYPE: TYPE9 Position */ +#define GPIO_INTTYPE_TYPE9_Msk (0x1ul << GPIO_INTTYPE_TYPE9_Pos) /*!< GPIO_T::INTTYPE: TYPE9 Mask */ + +#define GPIO_INTTYPE_TYPE10_Pos (10) /*!< GPIO_T::INTTYPE: TYPE10 Position */ +#define GPIO_INTTYPE_TYPE10_Msk (0x1ul << GPIO_INTTYPE_TYPE10_Pos) /*!< GPIO_T::INTTYPE: TYPE10 Mask */ + +#define GPIO_INTTYPE_TYPE11_Pos (11) /*!< GPIO_T::INTTYPE: TYPE11 Position */ +#define GPIO_INTTYPE_TYPE11_Msk (0x1ul << GPIO_INTTYPE_TYPE11_Pos) /*!< GPIO_T::INTTYPE: TYPE11 Mask */ + +#define GPIO_INTTYPE_TYPE12_Pos (12) /*!< GPIO_T::INTTYPE: TYPE12 Position */ +#define GPIO_INTTYPE_TYPE12_Msk (0x1ul << GPIO_INTTYPE_TYPE12_Pos) /*!< GPIO_T::INTTYPE: TYPE12 Mask */ + +#define GPIO_INTTYPE_TYPE13_Pos (13) /*!< GPIO_T::INTTYPE: TYPE13 Position */ +#define GPIO_INTTYPE_TYPE13_Msk (0x1ul << GPIO_INTTYPE_TYPE13_Pos) /*!< GPIO_T::INTTYPE: TYPE13 Mask */ + +#define GPIO_INTTYPE_TYPE14_Pos (14) /*!< GPIO_T::INTTYPE: TYPE14 Position */ +#define GPIO_INTTYPE_TYPE14_Msk (0x1ul << GPIO_INTTYPE_TYPE14_Pos) /*!< GPIO_T::INTTYPE: TYPE14 Mask */ + +#define GPIO_INTTYPE_TYPE15_Pos (15) /*!< GPIO_T::INTTYPE: TYPE15 Position */ +#define GPIO_INTTYPE_TYPE15_Msk (0x1ul << GPIO_INTTYPE_TYPE15_Pos) /*!< GPIO_T::INTTYPE: TYPE15 Mask */ + +#define GPIO_INTEN_FLIEN0_Pos (0) /*!< GPIO_T::INTEN: FLIEN0 Position */ +#define GPIO_INTEN_FLIEN0_Msk (0x1ul << GPIO_INTEN_FLIEN0_Pos) /*!< GPIO_T::INTEN: FLIEN0 Mask */ + +#define GPIO_INTEN_FLIEN1_Pos (1) /*!< GPIO_T::INTEN: FLIEN1 Position */ +#define GPIO_INTEN_FLIEN1_Msk (0x1ul << GPIO_INTEN_FLIEN1_Pos) /*!< GPIO_T::INTEN: FLIEN1 Mask */ + +#define GPIO_INTEN_FLIEN2_Pos (2) /*!< GPIO_T::INTEN: FLIEN2 Position */ +#define GPIO_INTEN_FLIEN2_Msk (0x1ul << GPIO_INTEN_FLIEN2_Pos) /*!< GPIO_T::INTEN: FLIEN2 Mask */ + +#define GPIO_INTEN_FLIEN3_Pos (3) /*!< GPIO_T::INTEN: FLIEN3 Position */ +#define GPIO_INTEN_FLIEN3_Msk (0x1ul << GPIO_INTEN_FLIEN3_Pos) /*!< GPIO_T::INTEN: FLIEN3 Mask */ + +#define GPIO_INTEN_FLIEN4_Pos (4) /*!< GPIO_T::INTEN: FLIEN4 Position */ +#define GPIO_INTEN_FLIEN4_Msk (0x1ul << GPIO_INTEN_FLIEN4_Pos) /*!< GPIO_T::INTEN: FLIEN4 Mask */ + +#define GPIO_INTEN_FLIEN5_Pos (5) /*!< GPIO_T::INTEN: FLIEN5 Position */ +#define GPIO_INTEN_FLIEN5_Msk (0x1ul << GPIO_INTEN_FLIEN5_Pos) /*!< GPIO_T::INTEN: FLIEN5 Mask */ + +#define GPIO_INTEN_FLIEN6_Pos (6) /*!< GPIO_T::INTEN: FLIEN6 Position */ +#define GPIO_INTEN_FLIEN6_Msk (0x1ul << GPIO_INTEN_FLIEN6_Pos) /*!< GPIO_T::INTEN: FLIEN6 Mask */ + +#define GPIO_INTEN_FLIEN7_Pos (7) /*!< GPIO_T::INTEN: FLIEN7 Position */ +#define GPIO_INTEN_FLIEN7_Msk (0x1ul << GPIO_INTEN_FLIEN7_Pos) /*!< GPIO_T::INTEN: FLIEN7 Mask */ + +#define GPIO_INTEN_FLIEN8_Pos (8) /*!< GPIO_T::INTEN: FLIEN8 Position */ +#define GPIO_INTEN_FLIEN8_Msk (0x1ul << GPIO_INTEN_FLIEN8_Pos) /*!< GPIO_T::INTEN: FLIEN8 Mask */ + +#define GPIO_INTEN_FLIEN9_Pos (9) /*!< GPIO_T::INTEN: FLIEN9 Position */ +#define GPIO_INTEN_FLIEN9_Msk (0x1ul << GPIO_INTEN_FLIEN9_Pos) /*!< GPIO_T::INTEN: FLIEN9 Mask */ + +#define GPIO_INTEN_FLIEN10_Pos (10) /*!< GPIO_T::INTEN: FLIEN10 Position */ +#define GPIO_INTEN_FLIEN10_Msk (0x1ul << GPIO_INTEN_FLIEN10_Pos) /*!< GPIO_T::INTEN: FLIEN10 Mask */ + +#define GPIO_INTEN_FLIEN11_Pos (11) /*!< GPIO_T::INTEN: FLIEN11 Position */ +#define GPIO_INTEN_FLIEN11_Msk (0x1ul << GPIO_INTEN_FLIEN11_Pos) /*!< GPIO_T::INTEN: FLIEN11 Mask */ + +#define GPIO_INTEN_FLIEN12_Pos (12) /*!< GPIO_T::INTEN: FLIEN12 Position */ +#define GPIO_INTEN_FLIEN12_Msk (0x1ul << GPIO_INTEN_FLIEN12_Pos) /*!< GPIO_T::INTEN: FLIEN12 Mask */ + +#define GPIO_INTEN_FLIEN13_Pos (13) /*!< GPIO_T::INTEN: FLIEN13 Position */ +#define GPIO_INTEN_FLIEN13_Msk (0x1ul << GPIO_INTEN_FLIEN13_Pos) /*!< GPIO_T::INTEN: FLIEN13 Mask */ + +#define GPIO_INTEN_FLIEN14_Pos (14) /*!< GPIO_T::INTEN: FLIEN14 Position */ +#define GPIO_INTEN_FLIEN14_Msk (0x1ul << GPIO_INTEN_FLIEN14_Pos) /*!< GPIO_T::INTEN: FLIEN14 Mask */ + +#define GPIO_INTEN_FLIEN15_Pos (15) /*!< GPIO_T::INTEN: FLIEN15 Position */ +#define GPIO_INTEN_FLIEN15_Msk (0x1ul << GPIO_INTEN_FLIEN15_Pos) /*!< GPIO_T::INTEN: FLIEN15 Mask */ + +#define GPIO_INTEN_RHIEN0_Pos (16) /*!< GPIO_T::INTEN: RHIEN0 Position */ +#define GPIO_INTEN_RHIEN0_Msk (0x1ul << GPIO_INTEN_RHIEN0_Pos) /*!< GPIO_T::INTEN: RHIEN0 Mask */ + +#define GPIO_INTEN_RHIEN1_Pos (17) /*!< GPIO_T::INTEN: RHIEN1 Position */ +#define GPIO_INTEN_RHIEN1_Msk (0x1ul << GPIO_INTEN_RHIEN1_Pos) /*!< GPIO_T::INTEN: RHIEN1 Mask */ + +#define GPIO_INTEN_RHIEN2_Pos (18) /*!< GPIO_T::INTEN: RHIEN2 Position */ +#define GPIO_INTEN_RHIEN2_Msk (0x1ul << GPIO_INTEN_RHIEN2_Pos) /*!< GPIO_T::INTEN: RHIEN2 Mask */ + +#define GPIO_INTEN_RHIEN3_Pos (19) /*!< GPIO_T::INTEN: RHIEN3 Position */ +#define GPIO_INTEN_RHIEN3_Msk (0x1ul << GPIO_INTEN_RHIEN3_Pos) /*!< GPIO_T::INTEN: RHIEN3 Mask */ + +#define GPIO_INTEN_RHIEN4_Pos (20) /*!< GPIO_T::INTEN: RHIEN4 Position */ +#define GPIO_INTEN_RHIEN4_Msk (0x1ul << GPIO_INTEN_RHIEN4_Pos) /*!< GPIO_T::INTEN: RHIEN4 Mask */ + +#define GPIO_INTEN_RHIEN5_Pos (21) /*!< GPIO_T::INTEN: RHIEN5 Position */ +#define GPIO_INTEN_RHIEN5_Msk (0x1ul << GPIO_INTEN_RHIEN5_Pos) /*!< GPIO_T::INTEN: RHIEN5 Mask */ + +#define GPIO_INTEN_RHIEN6_Pos (22) /*!< GPIO_T::INTEN: RHIEN6 Position */ +#define GPIO_INTEN_RHIEN6_Msk (0x1ul << GPIO_INTEN_RHIEN6_Pos) /*!< GPIO_T::INTEN: RHIEN6 Mask */ + +#define GPIO_INTEN_RHIEN7_Pos (23) /*!< GPIO_T::INTEN: RHIEN7 Position */ +#define GPIO_INTEN_RHIEN7_Msk (0x1ul << GPIO_INTEN_RHIEN7_Pos) /*!< GPIO_T::INTEN: RHIEN7 Mask */ + +#define GPIO_INTEN_RHIEN8_Pos (24) /*!< GPIO_T::INTEN: RHIEN8 Position */ +#define GPIO_INTEN_RHIEN8_Msk (0x1ul << GPIO_INTEN_RHIEN8_Pos) /*!< GPIO_T::INTEN: RHIEN8 Mask */ + +#define GPIO_INTEN_RHIEN9_Pos (25) /*!< GPIO_T::INTEN: RHIEN9 Position */ +#define GPIO_INTEN_RHIEN9_Msk (0x1ul << GPIO_INTEN_RHIEN9_Pos) /*!< GPIO_T::INTEN: RHIEN9 Mask */ + +#define GPIO_INTEN_RHIEN10_Pos (26) /*!< GPIO_T::INTEN: RHIEN10 Position */ +#define GPIO_INTEN_RHIEN10_Msk (0x1ul << GPIO_INTEN_RHIEN10_Pos) /*!< GPIO_T::INTEN: RHIEN10 Mask */ + +#define GPIO_INTEN_RHIEN11_Pos (27) /*!< GPIO_T::INTEN: RHIEN11 Position */ +#define GPIO_INTEN_RHIEN11_Msk (0x1ul << GPIO_INTEN_RHIEN11_Pos) /*!< GPIO_T::INTEN: RHIEN11 Mask */ + +#define GPIO_INTEN_RHIEN12_Pos (28) /*!< GPIO_T::INTEN: RHIEN12 Position */ +#define GPIO_INTEN_RHIEN12_Msk (0x1ul << GPIO_INTEN_RHIEN12_Pos) /*!< GPIO_T::INTEN: RHIEN12 Mask */ + +#define GPIO_INTEN_RHIEN13_Pos (29) /*!< GPIO_T::INTEN: RHIEN13 Position */ +#define GPIO_INTEN_RHIEN13_Msk (0x1ul << GPIO_INTEN_RHIEN13_Pos) /*!< GPIO_T::INTEN: RHIEN13 Mask */ + +#define GPIO_INTEN_RHIEN14_Pos (30) /*!< GPIO_T::INTEN: RHIEN14 Position */ +#define GPIO_INTEN_RHIEN14_Msk (0x1ul << GPIO_INTEN_RHIEN14_Pos) /*!< GPIO_T::INTEN: RHIEN14 Mask */ + +#define GPIO_INTEN_RHIEN15_Pos (31) /*!< GPIO_T::INTEN: RHIEN15 Position */ +#define GPIO_INTEN_RHIEN15_Msk (0x1ul << GPIO_INTEN_RHIEN15_Pos) /*!< GPIO_T::INTEN: RHIEN15 Mask */ + +#define GPIO_INTSRC_INTSRC0_Pos (0) /*!< GPIO_T::INTSRC: INTSRC0 Position */ +#define GPIO_INTSRC_INTSRC0_Msk (0x1ul << GPIO_INTSRC_INTSRC0_Pos) /*!< GPIO_T::INTSRC: INTSRC0 Mask */ + +#define GPIO_INTSRC_INTSRC1_Pos (1) /*!< GPIO_T::INTSRC: INTSRC1 Position */ +#define GPIO_INTSRC_INTSRC1_Msk (0x1ul << GPIO_INTSRC_INTSRC1_Pos) /*!< GPIO_T::INTSRC: INTSRC1 Mask */ + +#define GPIO_INTSRC_INTSRC2_Pos (2) /*!< GPIO_T::INTSRC: INTSRC2 Position */ +#define GPIO_INTSRC_INTSRC2_Msk (0x1ul << GPIO_INTSRC_INTSRC2_Pos) /*!< GPIO_T::INTSRC: INTSRC2 Mask */ + +#define GPIO_INTSRC_INTSRC3_Pos (3) /*!< GPIO_T::INTSRC: INTSRC3 Position */ +#define GPIO_INTSRC_INTSRC3_Msk (0x1ul << GPIO_INTSRC_INTSRC3_Pos) /*!< GPIO_T::INTSRC: INTSRC3 Mask */ + +#define GPIO_INTSRC_INTSRC4_Pos (4) /*!< GPIO_T::INTSRC: INTSRC4 Position */ +#define GPIO_INTSRC_INTSRC4_Msk (0x1ul << GPIO_INTSRC_INTSRC4_Pos) /*!< GPIO_T::INTSRC: INTSRC4 Mask */ + +#define GPIO_INTSRC_INTSRC5_Pos (5) /*!< GPIO_T::INTSRC: INTSRC5 Position */ +#define GPIO_INTSRC_INTSRC5_Msk (0x1ul << GPIO_INTSRC_INTSRC5_Pos) /*!< GPIO_T::INTSRC: INTSRC5 Mask */ + +#define GPIO_INTSRC_INTSRC6_Pos (6) /*!< GPIO_T::INTSRC: INTSRC6 Position */ +#define GPIO_INTSRC_INTSRC6_Msk (0x1ul << GPIO_INTSRC_INTSRC6_Pos) /*!< GPIO_T::INTSRC: INTSRC6 Mask */ + +#define GPIO_INTSRC_INTSRC7_Pos (7) /*!< GPIO_T::INTSRC: INTSRC7 Position */ +#define GPIO_INTSRC_INTSRC7_Msk (0x1ul << GPIO_INTSRC_INTSRC7_Pos) /*!< GPIO_T::INTSRC: INTSRC7 Mask */ + +#define GPIO_INTSRC_INTSRC8_Pos (8) /*!< GPIO_T::INTSRC: INTSRC8 Position */ +#define GPIO_INTSRC_INTSRC8_Msk (0x1ul << GPIO_INTSRC_INTSRC8_Pos) /*!< GPIO_T::INTSRC: INTSRC8 Mask */ + +#define GPIO_INTSRC_INTSRC9_Pos (9) /*!< GPIO_T::INTSRC: INTSRC9 Position */ +#define GPIO_INTSRC_INTSRC9_Msk (0x1ul << GPIO_INTSRC_INTSRC9_Pos) /*!< GPIO_T::INTSRC: INTSRC9 Mask */ + +#define GPIO_INTSRC_INTSRC10_Pos (10) /*!< GPIO_T::INTSRC: INTSRC10 Position */ +#define GPIO_INTSRC_INTSRC10_Msk (0x1ul << GPIO_INTSRC_INTSRC10_Pos) /*!< GPIO_T::INTSRC: INTSRC10 Mask */ + +#define GPIO_INTSRC_INTSRC11_Pos (11) /*!< GPIO_T::INTSRC: INTSRC11 Position */ +#define GPIO_INTSRC_INTSRC11_Msk (0x1ul << GPIO_INTSRC_INTSRC11_Pos) /*!< GPIO_T::INTSRC: INTSRC11 Mask */ + +#define GPIO_INTSRC_INTSRC12_Pos (12) /*!< GPIO_T::INTSRC: INTSRC12 Position */ +#define GPIO_INTSRC_INTSRC12_Msk (0x1ul << GPIO_INTSRC_INTSRC12_Pos) /*!< GPIO_T::INTSRC: INTSRC12 Mask */ + +#define GPIO_INTSRC_INTSRC13_Pos (13) /*!< GPIO_T::INTSRC: INTSRC13 Position */ +#define GPIO_INTSRC_INTSRC13_Msk (0x1ul << GPIO_INTSRC_INTSRC13_Pos) /*!< GPIO_T::INTSRC: INTSRC13 Mask */ + +#define GPIO_INTSRC_INTSRC14_Pos (14) /*!< GPIO_T::INTSRC: INTSRC14 Position */ +#define GPIO_INTSRC_INTSRC14_Msk (0x1ul << GPIO_INTSRC_INTSRC14_Pos) /*!< GPIO_T::INTSRC: INTSRC14 Mask */ + +#define GPIO_INTSRC_INTSRC15_Pos (15) /*!< GPIO_T::INTSRC: INTSRC15 Position */ +#define GPIO_INTSRC_INTSRC15_Msk (0x1ul << GPIO_INTSRC_INTSRC15_Pos) /*!< GPIO_T::INTSRC: INTSRC15 Mask */ + +#define GPIO_SMTEN_SMTEN0_Pos (0) /*!< GPIO_T::SMTEN: SMTEN0 Position */ +#define GPIO_SMTEN_SMTEN0_Msk (0x1ul << GPIO_SMTEN_SMTEN0_Pos) /*!< GPIO_T::SMTEN: SMTEN0 Mask */ + +#define GPIO_SMTEN_SMTEN1_Pos (1) /*!< GPIO_T::SMTEN: SMTEN1 Position */ +#define GPIO_SMTEN_SMTEN1_Msk (0x1ul << GPIO_SMTEN_SMTEN1_Pos) /*!< GPIO_T::SMTEN: SMTEN1 Mask */ + +#define GPIO_SMTEN_SMTEN2_Pos (2) /*!< GPIO_T::SMTEN: SMTEN2 Position */ +#define GPIO_SMTEN_SMTEN2_Msk (0x1ul << GPIO_SMTEN_SMTEN2_Pos) /*!< GPIO_T::SMTEN: SMTEN2 Mask */ + +#define GPIO_SMTEN_SMTEN3_Pos (3) /*!< GPIO_T::SMTEN: SMTEN3 Position */ +#define GPIO_SMTEN_SMTEN3_Msk (0x1ul << GPIO_SMTEN_SMTEN3_Pos) /*!< GPIO_T::SMTEN: SMTEN3 Mask */ + +#define GPIO_SMTEN_SMTEN4_Pos (4) /*!< GPIO_T::SMTEN: SMTEN4 Position */ +#define GPIO_SMTEN_SMTEN4_Msk (0x1ul << GPIO_SMTEN_SMTEN4_Pos) /*!< GPIO_T::SMTEN: SMTEN4 Mask */ + +#define GPIO_SMTEN_SMTEN5_Pos (5) /*!< GPIO_T::SMTEN: SMTEN5 Position */ +#define GPIO_SMTEN_SMTEN5_Msk (0x1ul << GPIO_SMTEN_SMTEN5_Pos) /*!< GPIO_T::SMTEN: SMTEN5 Mask */ + +#define GPIO_SMTEN_SMTEN6_Pos (6) /*!< GPIO_T::SMTEN: SMTEN6 Position */ +#define GPIO_SMTEN_SMTEN6_Msk (0x1ul << GPIO_SMTEN_SMTEN6_Pos) /*!< GPIO_T::SMTEN: SMTEN6 Mask */ + +#define GPIO_SMTEN_SMTEN7_Pos (7) /*!< GPIO_T::SMTEN: SMTEN7 Position */ +#define GPIO_SMTEN_SMTEN7_Msk (0x1ul << GPIO_SMTEN_SMTEN7_Pos) /*!< GPIO_T::SMTEN: SMTEN7 Mask */ + +#define GPIO_SMTEN_SMTEN8_Pos (8) /*!< GPIO_T::SMTEN: SMTEN8 Position */ +#define GPIO_SMTEN_SMTEN8_Msk (0x1ul << GPIO_SMTEN_SMTEN8_Pos) /*!< GPIO_T::SMTEN: SMTEN8 Mask */ + +#define GPIO_SMTEN_SMTEN9_Pos (9) /*!< GPIO_T::SMTEN: SMTEN9 Position */ +#define GPIO_SMTEN_SMTEN9_Msk (0x1ul << GPIO_SMTEN_SMTEN9_Pos) /*!< GPIO_T::SMTEN: SMTEN9 Mask */ + +#define GPIO_SMTEN_SMTEN10_Pos (10) /*!< GPIO_T::SMTEN: SMTEN10 Position */ +#define GPIO_SMTEN_SMTEN10_Msk (0x1ul << GPIO_SMTEN_SMTEN10_Pos) /*!< GPIO_T::SMTEN: SMTEN10 Mask */ + +#define GPIO_SMTEN_SMTEN11_Pos (11) /*!< GPIO_T::SMTEN: SMTEN11 Position */ +#define GPIO_SMTEN_SMTEN11_Msk (0x1ul << GPIO_SMTEN_SMTEN11_Pos) /*!< GPIO_T::SMTEN: SMTEN11 Mask */ + +#define GPIO_SMTEN_SMTEN12_Pos (12) /*!< GPIO_T::SMTEN: SMTEN12 Position */ +#define GPIO_SMTEN_SMTEN12_Msk (0x1ul << GPIO_SMTEN_SMTEN12_Pos) /*!< GPIO_T::SMTEN: SMTEN12 Mask */ + +#define GPIO_SMTEN_SMTEN13_Pos (13) /*!< GPIO_T::SMTEN: SMTEN13 Position */ +#define GPIO_SMTEN_SMTEN13_Msk (0x1ul << GPIO_SMTEN_SMTEN13_Pos) /*!< GPIO_T::SMTEN: SMTEN13 Mask */ + +#define GPIO_SMTEN_SMTEN14_Pos (14) /*!< GPIO_T::SMTEN: SMTEN14 Position */ +#define GPIO_SMTEN_SMTEN14_Msk (0x1ul << GPIO_SMTEN_SMTEN14_Pos) /*!< GPIO_T::SMTEN: SMTEN14 Mask */ + +#define GPIO_SMTEN_SMTEN15_Pos (15) /*!< GPIO_T::SMTEN: SMTEN15 Position */ +#define GPIO_SMTEN_SMTEN15_Msk (0x1ul << GPIO_SMTEN_SMTEN15_Pos) /*!< GPIO_T::SMTEN: SMTEN15 Mask */ + +#define GPIO_SLEWCTL_HSREN0_Pos (0) /*!< GPIO_T::SLEWCTL: HSREN0 Position */ +#define GPIO_SLEWCTL_HSREN0_Msk (0x3ul << GPIO_SLEWCTL_HSREN0_Pos) /*!< GPIO_T::SLEWCTL: HSREN0 Mask */ + +#define GPIO_SLEWCTL_HSREN1_Pos (2) /*!< GPIO_T::SLEWCTL: HSREN1 Position */ +#define GPIO_SLEWCTL_HSREN1_Msk (0x3ul << GPIO_SLEWCTL_HSREN1_Pos) /*!< GPIO_T::SLEWCTL: HSREN1 Mask */ + +#define GPIO_SLEWCTL_HSREN2_Pos (4) /*!< GPIO_T::SLEWCTL: HSREN2 Position */ +#define GPIO_SLEWCTL_HSREN2_Msk (0x3ul << GPIO_SLEWCTL_HSREN2_Pos) /*!< GPIO_T::SLEWCTL: HSREN2 Mask */ + +#define GPIO_SLEWCTL_HSREN3_Pos (6) /*!< GPIO_T::SLEWCTL: HSREN3 Position */ +#define GPIO_SLEWCTL_HSREN3_Msk (0x3ul << GPIO_SLEWCTL_HSREN3_Pos) /*!< GPIO_T::SLEWCTL: HSREN3 Mask */ + +#define GPIO_SLEWCTL_HSREN4_Pos (8) /*!< GPIO_T::SLEWCTL: HSREN4 Position */ +#define GPIO_SLEWCTL_HSREN4_Msk (0x3ul << GPIO_SLEWCTL_HSREN4_Pos) /*!< GPIO_T::SLEWCTL: HSREN4 Mask */ + +#define GPIO_SLEWCTL_HSREN5_Pos (10) /*!< GPIO_T::SLEWCTL: HSREN5 Position */ +#define GPIO_SLEWCTL_HSREN5_Msk (0x3ul << GPIO_SLEWCTL_HSREN5_Pos) /*!< GPIO_T::SLEWCTL: HSREN5 Mask */ + +#define GPIO_SLEWCTL_HSREN6_Pos (12) /*!< GPIO_T::SLEWCTL: HSREN6 Position */ +#define GPIO_SLEWCTL_HSREN6_Msk (0x3ul << GPIO_SLEWCTL_HSREN6_Pos) /*!< GPIO_T::SLEWCTL: HSREN6 Mask */ + +#define GPIO_SLEWCTL_HSREN7_Pos (14) /*!< GPIO_T::SLEWCTL: HSREN7 Position */ +#define GPIO_SLEWCTL_HSREN7_Msk (0x3ul << GPIO_SLEWCTL_HSREN7_Pos) /*!< GPIO_T::SLEWCTL: HSREN7 Mask */ + +#define GPIO_SLEWCTL_HSREN8_Pos (16) /*!< GPIO_T::SLEWCTL: HSREN8 Position */ +#define GPIO_SLEWCTL_HSREN8_Msk (0x3ul << GPIO_SLEWCTL_HSREN8_Pos) /*!< GPIO_T::SLEWCTL: HSREN8 Mask */ + +#define GPIO_SLEWCTL_HSREN9_Pos (18) /*!< GPIO_T::SLEWCTL: HSREN9 Position */ +#define GPIO_SLEWCTL_HSREN9_Msk (0x3ul << GPIO_SLEWCTL_HSREN9_Pos) /*!< GPIO_T::SLEWCTL: HSREN9 Mask */ + +#define GPIO_SLEWCTL_HSREN10_Pos (20) /*!< GPIO_T::SLEWCTL: HSREN10 Position */ +#define GPIO_SLEWCTL_HSREN10_Msk (0x3ul << GPIO_SLEWCTL_HSREN10_Pos) /*!< GPIO_T::SLEWCTL: HSREN10 Mask */ + +#define GPIO_SLEWCTL_HSREN11_Pos (22) /*!< GPIO_T::SLEWCTL: HSREN11 Position */ +#define GPIO_SLEWCTL_HSREN11_Msk (0x3ul << GPIO_SLEWCTL_HSREN11_Pos) /*!< GPIO_T::SLEWCTL: HSREN11 Mask */ + +#define GPIO_SLEWCTL_HSREN12_Pos (24) /*!< GPIO_T::SLEWCTL: HSREN12 Position */ +#define GPIO_SLEWCTL_HSREN12_Msk (0x3ul << GPIO_SLEWCTL_HSREN12_Pos) /*!< GPIO_T::SLEWCTL: HSREN12 Mask */ + +#define GPIO_SLEWCTL_HSREN13_Pos (26) /*!< GPIO_T::SLEWCTL: HSREN13 Position */ +#define GPIO_SLEWCTL_HSREN13_Msk (0x3ul << GPIO_SLEWCTL_HSREN13_Pos) /*!< GPIO_T::SLEWCTL: HSREN13 Mask */ + +#define GPIO_SLEWCTL_HSREN14_Pos (28) /*!< GPIO_T::SLEWCTL: HSREN14 Position */ +#define GPIO_SLEWCTL_HSREN14_Msk (0x3ul << GPIO_SLEWCTL_HSREN14_Pos) /*!< GPIO_T::SLEWCTL: HSREN14 Mask */ + +#define GPIO_SLEWCTL_HSREN15_Pos (30) /*!< GPIO_T::SLEWCTL: HSREN15 Position */ +#define GPIO_SLEWCTL_HSREN15_Msk (0x3ul << GPIO_SLEWCTL_HSREN15_Pos) /*!< GPIO_T::SLEWCTL: HSREN15 Mask */ + +#define GPIO_PUSEL_PUSEL0_Pos (0) /*!< GPIO_T::PUSEL: PUSEL0 Position */ +#define GPIO_PUSEL_PUSEL0_Msk (0x3ul << GPIO_PUSEL_PUSEL0_Pos) /*!< GPIO_T::PUSEL: PUSEL0 Mask */ + +#define GPIO_PUSEL_PUSEL1_Pos (2) /*!< GPIO_T::PUSEL: PUSEL1 Position */ +#define GPIO_PUSEL_PUSEL1_Msk (0x3ul << GPIO_PUSEL_PUSEL1_Pos) /*!< GPIO_T::PUSEL: PUSEL1 Mask */ + +#define GPIO_PUSEL_PUSEL2_Pos (4) /*!< GPIO_T::PUSEL: PUSEL2 Position */ +#define GPIO_PUSEL_PUSEL2_Msk (0x3ul << GPIO_PUSEL_PUSEL2_Pos) /*!< GPIO_T::PUSEL: PUSEL2 Mask */ + +#define GPIO_PUSEL_PUSEL3_Pos (6) /*!< GPIO_T::PUSEL: PUSEL3 Position */ +#define GPIO_PUSEL_PUSEL3_Msk (0x3ul << GPIO_PUSEL_PUSEL3_Pos) /*!< GPIO_T::PUSEL: PUSEL3 Mask */ + +#define GPIO_PUSEL_PUSEL4_Pos (8) /*!< GPIO_T::PUSEL: PUSEL4 Position */ +#define GPIO_PUSEL_PUSEL4_Msk (0x3ul << GPIO_PUSEL_PUSEL4_Pos) /*!< GPIO_T::PUSEL: PUSEL4 Mask */ + +#define GPIO_PUSEL_PUSEL5_Pos (10) /*!< GPIO_T::PUSEL: PUSEL5 Position */ +#define GPIO_PUSEL_PUSEL5_Msk (0x3ul << GPIO_PUSEL_PUSEL5_Pos) /*!< GPIO_T::PUSEL: PUSEL5 Mask */ + +#define GPIO_PUSEL_PUSEL6_Pos (12) /*!< GPIO_T::PUSEL: PUSEL6 Position */ +#define GPIO_PUSEL_PUSEL6_Msk (0x3ul << GPIO_PUSEL_PUSEL6_Pos) /*!< GPIO_T::PUSEL: PUSEL6 Mask */ + +#define GPIO_PUSEL_PUSEL7_Pos (14) /*!< GPIO_T::PUSEL: PUSEL7 Position */ +#define GPIO_PUSEL_PUSEL7_Msk (0x3ul << GPIO_PUSEL_PUSEL7_Pos) /*!< GPIO_T::PUSEL: PUSEL7 Mask */ + +#define GPIO_PUSEL_PUSEL8_Pos (16) /*!< GPIO_T::PUSEL: PUSEL8 Position */ +#define GPIO_PUSEL_PUSEL8_Msk (0x3ul << GPIO_PUSEL_PUSEL8_Pos) /*!< GPIO_T::PUSEL: PUSEL8 Mask */ + +#define GPIO_PUSEL_PUSEL9_Pos (18) /*!< GPIO_T::PUSEL: PUSEL9 Position */ +#define GPIO_PUSEL_PUSEL9_Msk (0x3ul << GPIO_PUSEL_PUSEL9_Pos) /*!< GPIO_T::PUSEL: PUSEL9 Mask */ + +#define GPIO_PUSEL_PUSEL10_Pos (20) /*!< GPIO_T::PUSEL: PUSEL10 Position */ +#define GPIO_PUSEL_PUSEL10_Msk (0x3ul << GPIO_PUSEL_PUSEL10_Pos) /*!< GPIO_T::PUSEL: PUSEL10 Mask */ + +#define GPIO_PUSEL_PUSEL11_Pos (22) /*!< GPIO_T::PUSEL: PUSEL11 Position */ +#define GPIO_PUSEL_PUSEL11_Msk (0x3ul << GPIO_PUSEL_PUSEL11_Pos) /*!< GPIO_T::PUSEL: PUSEL11 Mask */ + +#define GPIO_PUSEL_PUSEL12_Pos (24) /*!< GPIO_T::PUSEL: PUSEL12 Position */ +#define GPIO_PUSEL_PUSEL12_Msk (0x3ul << GPIO_PUSEL_PUSEL12_Pos) /*!< GPIO_T::PUSEL: PUSEL12 Mask */ + +#define GPIO_PUSEL_PUSEL13_Pos (26) /*!< GPIO_T::PUSEL: PUSEL13 Position */ +#define GPIO_PUSEL_PUSEL13_Msk (0x3ul << GPIO_PUSEL_PUSEL13_Pos) /*!< GPIO_T::PUSEL: PUSEL13 Mask */ + +#define GPIO_PUSEL_PUSEL14_Pos (28) /*!< GPIO_T::PUSEL: PUSEL14 Position */ +#define GPIO_PUSEL_PUSEL14_Msk (0x3ul << GPIO_PUSEL_PUSEL14_Pos) /*!< GPIO_T::PUSEL: PUSEL14 Mask */ + +#define GPIO_PUSEL_PUSEL15_Pos (30) /*!< GPIO_T::PUSEL: PUSEL15 Position */ +#define GPIO_PUSEL_PUSEL15_Msk (0x3ul << GPIO_PUSEL_PUSEL15_Pos) /*!< GPIO_T::PUSEL: PUSEL15 Mask */ + +#define GPIO_DBCTL_DBCLKSEL_Pos (0) /*!< GPIO_T::DBCTL: DBCLKSEL Position */ +#define GPIO_DBCTL_DBCLKSEL_Msk (0xful << GPIO_DBCTL_DBCLKSEL_Pos) /*!< GPIO_T::DBCTL: DBCLKSEL Mask */ + +#define GPIO_DBCTL_DBCLKSRC_Pos (4) /*!< GPIO_T::DBCTL: DBCLKSRC Position */ +#define GPIO_DBCTL_DBCLKSRC_Msk (0x1ul << GPIO_DBCTL_DBCLKSRC_Pos) /*!< GPIO_T::DBCTL: DBCLKSRC Mask */ + +#define GPIO_DBCTL_ICLKON_Pos (5) /*!< GPIO_T::DBCTL: ICLKON Position */ +#define GPIO_DBCTL_ICLKON_Msk (0x1ul << GPIO_DBCTL_ICLKON_Pos) /*!< GPIO_T::DBCTL: ICLKON Mask */ + + +#define GPIO_DS_DS10_DS00_Pos (0) /*!< GPIO_T::DS: DS10_DS00 Position */ +#define GPIO_DS_DS10_DS00_Msk (0x1ul << GPIO_DS_DS10_DS00_Pos) /*!< GPIO_T::DS: DS10_DS00 Mask */ + +#define GPIO_DS_DS11_DS01_Pos (1) /*!< GPIO_T::DS: DS11_DS01 Position */ +#define GPIO_DS_DS11_DS01_Msk (0x1ul << GPIO_DS_DS11_DS01_Pos) /*!< GPIO_T::DS: DS11_DS01 Mask */ + +#define GPIO_DS_DS12_DS02_Pos (2) /*!< GPIO_T::DS: DS12_DS02 Position */ +#define GPIO_DS_DS12_DS02_Msk (0x1ul << GPIO_DS_DS12_DS02_Pos) /*!< GPIO_T::DS: DS12_DS02 Mask */ + +#define GPIO_DS_DS13_DS03_Pos (3) /*!< GPIO_T::DS: DS13_DS03 Position */ +#define GPIO_DS_DS13_DS03_Msk (0x1ul << GPIO_DS_DS13_DS03_Pos) /*!< GPIO_T::DS: DS13_DS03 Mask */ + +#define GPIO_DS_DS14_DS04_Pos (4) /*!< GPIO_T::DS: DS14_DS04 Position */ +#define GPIO_DS_DS14_DS04_Msk (0x1ul << GPIO_DS_DS14_DS04_Pos) /*!< GPIO_T::DS: DS14_DS04 Mask */ + +#define GPIO_DS_DS15_DS05_Pos (5) /*!< GPIO_T::DS: DS15_DS05 Position */ +#define GPIO_DS_DS15_DS05_Msk (0x1ul << GPIO_DS_DS15_DS05_Pos) /*!< GPIO_T::DS: DS15_DS05 Mask */ + +#define GPIO_DS_DS16_DS06_Pos (6) /*!< GPIO_T::DS: DS16_DS06 Position */ +#define GPIO_DS_DS16_DS06_Msk (0x1ul << GPIO_DS_DS16_DS06_Pos) /*!< GPIO_T::DS: DS16_DS06 Mask */ + +#define GPIO_DS_DS17_DS07_Pos (7) /*!< GPIO_T::DS: DS17_DS07 Position */ +#define GPIO_DS_DS17_DS07_Msk (0x1ul << GPIO_DS_DS17_DS07_Pos) /*!< GPIO_T::DS: DS17_DS07 Mask */ + +#define GPIO_DS_DS18_DS08_Pos (8) /*!< GPIO_T::DS: DS18_DS08 Position */ +#define GPIO_DS_DS18_DS08_Msk (0x1ul << GPIO_DS_DS18_DS08_Pos) /*!< GPIO_T::DS: DS18_DS08 Mask */ + +#define GPIO_DS_DS19_DS09_Pos (9) /*!< GPIO_T::DS: DS19_DS09 Position */ +#define GPIO_DS_DS19_DS09_Msk (0x1ul << GPIO_DS_DS19_DS09_Pos) /*!< GPIO_T::DS: DS19_DS09 Mask */ + +#define GPIO_DS_DS110_DS010_Pos (10) /*!< GPIO_T::DS: DS110_DS010 Position */ +#define GPIO_DS_DS110_DS010_Msk (0x1ul << GPIO_DS_DS110_DS010_Pos) /*!< GPIO_T::DS: DS110_DS010 Mask */ + +#define GPIO_DS_DS111_DS011_Pos (11) /*!< GPIO_T::DS: DS111_DS011 Position */ +#define GPIO_DS_DS111_DS011_Msk (0x1ul << GPIO_DS_DS111_DS011_Pos) /*!< GPIO_T::DS: DS111_DS011 Mask */ + +#define GPIO_DS_DS112_DS012_Pos (12) /*!< GPIO_T::DS: DS112_DS012 Position */ +#define GPIO_DS_DS112_DS012_Msk (0x1ul << GPIO_DS_DS112_DS012_Pos) /*!< GPIO_T::DS: DS112_DS012 Mask */ + +#define GPIO_DS_DS113_DS013_Pos (13) /*!< GPIO_T::DS: DS113_DS013 Position */ +#define GPIO_DS_DS113_DS013_Msk (0x1ul << GPIO_DS_DS113_DS013_Pos) /*!< GPIO_T::DS: DS113_DS013 Mask */ + +#define GPIO_DS_DS114_DS014_Pos (14) /*!< GPIO_T::DS: DS114_DS014 Position */ +#define GPIO_DS_DS114_DS014_Msk (0x1ul << GPIO_DS_DS114_DS014_Pos) /*!< GPIO_T::DS: DS114_DS014 Mask */ + +#define GPIO_DS_DS115_DS015_Pos (15) /*!< GPIO_T::DS: DS115_DS015 Position */ +#define GPIO_DS_DS115_DS015_Msk (0x1ul << GPIO_DS_DS115_DS015_Pos) /*!< GPIO_T::DS: DS115_DS015 Mask */ + +#define GPIO_UDS_UDS0_Pos (0) /*!< GPIO_T::UDS: UDS0 Position */ +#define GPIO_UDS_UDS0_Msk (0x1ul << GPIO_UDS_UDS0_Pos) /*!< GPIO_T::UDS: UDS0 Mask */ + +#define GPIO_UDS_UDS1_Pos (1) /*!< GPIO_T::UDS: UDS1 Position */ +#define GPIO_UDS_UDS1_Msk (0x1ul << GPIO_UDS_UDS1_Pos) /*!< GPIO_T::UDS: UDS1 Mask */ + +#define GPIO_UDS_UDS2_Pos (2) /*!< GPIO_T::UDS: UDS2 Position */ +#define GPIO_UDS_UDS2_Msk (0x1ul << GPIO_UDS_UDS2_Pos) /*!< GPIO_T::UDS: UDS2 Mask */ + +#define GPIO_UDS_UDS3_Pos (3) /*!< GPIO_T::UDS: UDS3 Position */ +#define GPIO_UDS_UDS3_Msk (0x1ul << GPIO_UDS_UDS3_Pos) /*!< GPIO_T::UDS: UDS3 Mask */ + +#define GPIO_UDS_UDS4_Pos (4) /*!< GPIO_T::UDS: UDS4 Position */ +#define GPIO_UDS_UDS4_Msk (0x1ul << GPIO_UDS_UDS4_Pos) /*!< GPIO_T::UDS: UDS4 Mask */ + +#define GPIO_UDS_UDS5_Pos (5) /*!< GPIO_T::UDS: UDS5 Position */ +#define GPIO_UDS_UDS5_Msk (0x1ul << GPIO_UDS_UDS5_Pos) /*!< GPIO_T::UDS: UDS5 Mask */ + +#define GPIO_UDS_UDS6_Pos (6) /*!< GPIO_T::UDS: UDS6 Position */ +#define GPIO_UDS_UDS6_Msk (0x1ul << GPIO_UDS_UDS6_Pos) /*!< GPIO_T::UDS: UDS6 Mask */ + +#define GPIO_UDS_UDS7_Pos (7) /*!< GPIO_T::UDS: UDS7 Position */ +#define GPIO_UDS_UDS7_Msk (0x1ul << GPIO_UDS_UDS7_Pos) /*!< GPIO_T::UDS: UDS7 Mask */ + +#define GPIO_UDS_UDS8_Pos (8) /*!< GPIO_T::UDS: UDS8 Position */ +#define GPIO_UDS_UDS8_Msk (0x1ul << GPIO_UDS_UDS8_Pos) /*!< GPIO_T::UDS: UDS8 Mask */ + +#define GPIO_UDS_UDS9_Pos (9) /*!< GPIO_T::UDS: UDS9 Position */ +#define GPIO_UDS_UDS9_Msk (0x1ul << GPIO_UDS_UDS9_Pos) /*!< GPIO_T::UDS: UDS9 Mask */ + +#define GPIO_UDS_UDS10_Pos (10) /*!< GPIO_T::UDS: UDS10 Position */ +#define GPIO_UDS_UDS10_Msk (0x1ul << GPIO_UDS_UDS10_Pos) /*!< GPIO_T::UDS: UDS10 Mask */ + +#define GPIO_UDS_UDS11_Pos (11) /*!< GPIO_T::UDS: UDS11 Position */ +#define GPIO_UDS_UDS11_Msk (0x1ul << GPIO_UDS_UDS11_Pos) /*!< GPIO_T::UDS: UDS11 Mask */ + +#define GPIO_UDS_UDS12_Pos (12) /*!< GPIO_T::UDS: UDS12 Position */ +#define GPIO_UDS_UDS12_Msk (0x1ul << GPIO_UDS_UDS12_Pos) /*!< GPIO_T::UDS: UDS12 Mask */ + +#define GPIO_UDS_UDS13_Pos (13) /*!< GPIO_T::UDS: UDS13 Position */ +#define GPIO_UDS_UDS13_Msk (0x1ul << GPIO_UDS_UDS13_Pos) /*!< GPIO_T::UDS: UDS13 Mask */ + +#define GPIO_UDS_UDS14_Pos (14) /*!< GPIO_T::UDS: UDS14 Position */ +#define GPIO_UDS_UDS14_Msk (0x1ul << GPIO_UDS_UDS14_Pos) /*!< GPIO_T::UDS: UDS14 Mask */ + +#define GPIO_UDS_UDS15_Pos (15) /*!< GPIO_T::UDS: UDS15 Position */ +#define GPIO_UDS_UDS15_Msk (0x1ul << GPIO_UDS_UDS15_Pos) /*!< GPIO_T::UDS: UDS15 Mask */ +/**@}*/ /* GPIO_CONST */ +/**@}*/ /* end of GPIO register group */ +/**@}*/ /* end of REGISTER group */ + +#if defined ( __CC_ARM ) + #pragma no_anon_unions +#endif + +#endif /* __GPIO_REG_H__ */ diff --git a/bsp/nuvoton/libraries/ma35/Device/Nuvoton/MA35D1/Include/hsusbd_reg.h b/bsp/nuvoton/libraries/ma35/Device/Nuvoton/MA35D1/Include/hsusbd_reg.h new file mode 100644 index 0000000000..ae1d67027a --- /dev/null +++ b/bsp/nuvoton/libraries/ma35/Device/Nuvoton/MA35D1/Include/hsusbd_reg.h @@ -0,0 +1,3108 @@ +/**************************************************************************//** + * @file hsusbd_reg.h + * @brief HSUSBD register definition header file + * + * SPDX-License-Identifier: Apache-2.0 + * @copyright (C) 2021 Nuvoton Technology Corp. All rights reserved. + *****************************************************************************/ +#ifndef __HSUSBD_REG_H__ +#define __HSUSBD_REG_H__ + +#if defined ( __CC_ARM ) + #pragma anon_unions +#endif + + +/******************************************************************************/ +/* Device Specific Peripheral registers structures */ +/******************************************************************************/ + +/** @addtogroup REGISTER Control Register + + @{ + +*/ + + +/*---------------------- High Speed USB 2.0 Device Controller -------------------------*/ +/** + @addtogroup HSUSBD High Speed USB 2.0 Device Controller(HSUSBD) + Memory Mapped Structure for HSUSBD Controller +@{ */ + +/*----- IN Endpoint 1~8 -----*/ +typedef struct +{ + + /** + * @var HSUSBD_T::DIEPCTLn + * Offset: 0x00 Device Control IN Endpoint n Control Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[10:0] |MPS |Maximum Packet Size (MPS) + * | | |The application must program this field with the maximum packet size for the current logical endpoint + * | | |This value is in bytes. + * |[15] |USBActEP |USB Active Endpoint (USBActEP) + * | | |Indicates whether this endpoint is active in the current configuration and interface + * | | |The core clears this bit for all endpoints (other than EP 0) after detecting a USB reset + * | | |After receiving the SetConfiguration and SetInterface commands, the application must program endpoint registers accordingly and set this bit. + * | | |Values: + * | | |0x0 (DISABLED): Not Active + * | | |0x1 (ENABLED): USB Active Endpoint + * |[16] |DPID |Endpoint Data PID (DPID) (Read only) + * | | |Applies to interrupt/bulk IN and OUT endpoints only. + * | | |Contains the PID of the packet to be received or transmitted on this endpoint + * | | |The application must program the PID of the first packet to be received or transmitted on this endpoint, after the endpoint is activated + * | | |The applications use the SetD1PID and SetD0PID fields of this register to program either DATA0 or DATA1 PID. + * | | |1'b0: DATA0 + * | | |1'b1: DATA1 + * | | |Values: + * | | |0x0 (DATA0EVENFRM): DATA0 or Even Frame + * | | |0x1 (DATA1ODDFRM): DATA1 or Odd Frame + * |[17] |NAKSts |NAK Status (NAKSts) (Read only) + * | | |Indicates the following: + * | | |1'b0: The core is transmitting non-NAK handshakes based on the FIFO status. + * | | |1'b1: The core is transmitting NAK handshakes on this endpoint. + * | | |When either the application or the core sets this bit: + * | | |The core stops receiving any data on an OUT endpoint, even if there is space in the RxFIFO to accommodate the incoming packet. + * | | |For non-isochronous IN endpoints: The core stops transmitting any data on an IN endpoint, even if there data is available in the TxFIFO. + * | | |For isochronous IN endpoints: The core sends out a zero-length data packet, even if there data is available in the TxFIFO. + * | | |Irrespective of this bit's setting, the core always responds to SETUP data packets with an ACK handshake. + * | | |Values: + * | | |0x0 (NONNAK): + * | | |The core is transmitting non-NAK handshakes based on the FIFO status + * | | |0x1 (NAK): + * | | |The core is transmitting NAK handshakes on this endpoint + * |[19:18] |EPType |Endpoint Type (EPType) + * | | |This is the transfer type supported by this logical endpoint + * | | |2'b00: Control + * | | |2'b01: Isochronous + * | | |2'b10: Bulk + * | | |2'b11: Interrupt + * | | |Values: + * | | |0x0 (CONTROL): Control + * | | |0x1 (ISOCHRONOUS): Isochronous + * | | |0x2 (BULK): Bulk + * | | |0x3 (INTERRUP): Interrupt + * |[21] |Stall |STALL Handshake (Stall) + * | | |Applies to non-control, non-isochronous IN and OUT endpoints only. + * | | |The application sets this bit to stall all tokens from the USB host to this endpoint + * | | |If a NAK bit, Global Non-periodic IN NAK, or Global OUT NAK is set along with this bit, the STALL bit takes priority + * | | |Only the application can clear this bit, never the core. + * | | |Applies to control endpoints only. + * | | |The application can only set this bit, and the core clears it, when a SETUP token is received for this endpoint + * | | |If a NAK bit, Global Non-periodic IN NAK, or Global OUT NAK is set along with this bit, the STALL bit takes priority + * | | |Irrespective of this bit's setting, the core always responds to SETUP data packets with an ACK handshake. + * | | |Values: + * | | |0x0 (INACTIVE): STALL All non-active tokens + * | | |0x1 (ACTIVE): STALL All Active Tokens + * |[25:22] |TxFNum |TxFIFO Number (TxFNum) + * | | |Dedicated FIFO Operation: These bits specify the FIFO number associated with this endpoint + * | | |Each active IN endpoint must be programmed to a separate FIFO number + * | | |This field is valid only for IN endpoints. + * | | |Values: + * | | |0x0 (TXFIFO0): Tx FIFO 0 + * | | |0x1 (TXFIFO1): Tx FIFO 1 + * | | |0x2 (TXFIFO2): Tx FIFO 2 + * | | |0x3 (TXFIFO3): Tx FIFO 3 + * | | |0x4 (TXFIFO4): Tx FIFO 4 + * | | |0x5 (TXFIFO5): Tx FIFO 5 + * | | |0x6 (TXFIFO6): Tx FIFO 6 + * | | |0x7 (TXFIFO7): Tx FIFO 7 + * | | |0x8 (TXFIFO8): Tx FIFO 8 + * |[26] |CNAK |Clear NAK (CNAK) + * | | |A write to this bit clears the NAK bit for the endpoint. + * | | |Values: + * | | |0x0 (INACTIVE): No Clear NAK + * | | |0x1 (ACTIVE): Clear NAK + * |[27] |SNAK |Set NAK (SNAK) + * | | |A write to this bit sets the NAK bit for the endpoint. + * | | |Using this bit, the application can control the transmission of NAK handshakes on an endpoint + * | | |The core can also Set this bit for an endpoint after a SETUP packet is received on that endpoint. + * | | |Values: + * | | |0x0 (INACTIVE): No Set NAK + * | | |0x1 (ACTIVE): Set NAK + * |[30] |EPDis |Endpoint Disable (EPDis) + * | | |Applies to IN and OUT endpoints. + * | | |The application sets this bit to stop transmitting/receiving data on an endpoint, even before the transfer for that endpoint is complete + * | | |The application must wait for the Endpoint Disabled interrupt before treating the endpoint as disabled + * | | |The core clears this bit before setting the Endpoint Disabled interrupt + * | | |The application must set this bit only if Endpoint Enable is already set for this endpoint. + * | | |Values: + * | | |0x0 (INACTIVE): No Action + * | | |0x1 (ACTIVE): Disable Endpoint + * |[31] |EPEna |Endpoint Enable (EPEna) + * | | |Applies to IN and OUT endpoints. + * | | |When Scatter/Gather DMA mode is enabled, + * | | |For IN endpoints this bit indicates that the descriptor structure and data buffer with data ready to transmit is setup. + * | | |For OUT endpoint it indicates that the descriptor structure and data buffer to receive data is setup. + * | | |The core clears this bit before setting any of the following interrupts on this endpoint: + * | | |SETUP Phase Done + * | | |Endpoint Disabled + * | | |Transfer Completed + * | | |Note: For control endpoints in DMA mode, this bit must be set to be able to transfer SETUP data packets in memory. + * | | |Values: + * | | |0x0 (INACTIVE): No Action + * | | |0x1 (ACTIVE): Enable Endpoint + * @var HSUSBD_T::DIEPINTn + * Offset: 0x08 Device IN Endpoint n Interrupt Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[0] |XferCompl |Transfer Completed Interrupt (XferCompl) + * | | |Applies to IN and OUT endpoints. + * | | |When Scatter/Gather DMA mode is enabled + * | | |For IN endpoint this field indicates that the requested data from the descriptor is moved from external system memory to internal FIFO. + * | | |For OUT endpoint this field indicates that the requested data from the internal FIFO is moved to external system memory + * | | |This interrupt is generated only when the corresponding endpoint descriptor is closed, and the IOC bit for the corresponding descriptor is set. + * | | |Values: + * | | |0x0 (INACTIVE): No Transfer Complete Interrupt + * | | |0x1 (ACTIVE): Transfer Complete Interrupt + * |[1] |EPDisbld |Endpoint Disabled Interrupt (EPDisbld) + * | | |Applies to IN and OUT endpoints. + * | | |This bit indicates that the endpoint is disabled per the application's request. + * | | |Values: + * | | |0x0 (INACTIVE): No Endpoint Disabled Interrupt + * | | |0x1 (ACTIVE): Endpoint Disabled Interrupt + * |[2] |AHBErr |AHB Error (AHBErr) + * | | |Applies to IN and OUT endpoints. + * | | |When there is an AHB error during an AHB read/write + * | | |The application can read the corresponding endpoint DMA address register to get the error address. + * | | |Values: + * | | |0x0 (INACTIVE): No AHB Error Interrupt + * | | |0x1 (ACTIVE): AHB Error interrupt + * |[4] |INTknTXFEmp|IN Token Received When TxFIFO is Empty (INTknTXFEmp) + * | | |Applies to non-periodic IN endpoints only. + * | | |Indicates that an IN token was received when the associated TxFIFO (periodic/non-periodic) was empty + * | | |This interrupt is asserted on the endpoint for which the IN token was received. + * | | |Values: + * | | |0x0 (INACTIVE): No IN Token Received interrupt + * | | |0x1 (ACTIVE): IN Token Received Interrupt + * |[5] |INTknEPMis|IN Token Received with EP Mismatch (INTknEPMis) + * | | |Applies to non-periodic IN endpoints only. + * | | |Indicates that the data in the top of the non-periodic TxFIFO belongs to an endpoint other than the one for which the IN token was received + * | | |This interrupt is asserted on the endpoint for which the IN token was received. + * | | |Values: + * | | |0x0 (INACTIVE): No IN Token Received with EP Mismatch interrupt + * | | |0x1 (ACTIVE): IN Token Received with EP Mismatch interrupt + * |[6] |INEPNakEff|IN Endpoint NAK Effective (INEPNakEff) + * | | |Applies to periodic IN endpoints only. + * | | |This bit can be cleared when the application clears the IN endpoint NAK by writing to DIEPCTLn.CNAK. + * | | |This interrupt indicates that the core has sampled the NAK bit + * | | |Set (either by the application or by the core) + * | | |The interrupt indicates that the IN endpoint NAK bit Set by the application has taken effect in the core. + * | | |This interrupt does not guarantee that a NAK handshake is sent on the USB + * | | |A STALL bit takes priority over a NAK bit. + * | | |Values: + * | | |0x0 (INACTIVE): No Endpoint NAK Effective interrupt + * | | |0x1 (ACTIVE): IN Endpoint NAK Effective interrupt + * |[7] |TxFEmp |Transmit FIFO Empty (TxFEmp) (Read only) + * | | |This bit is valid only for IN endpoints + * | | |This interrupt is asserted when the TxFIFO for this endpoint is either half or completely empty + * | | |The half or completely empty status is determined by the TxFIFO Empty Level bit in the Core AHB Configuration register (GAHBCFG.NPTxFEmpLvl)). + * | | |Values: + * | | |0x0 (INACTIVE): No Transmit FIFO Empty interrupt + * | | |0x1 (ACTIVE): Transmit FIFO Empty interrupt + * |[8] |TxfifoUndrn|Fifo Underrun (TxfifoUndrn) + * | | |Applies to IN endpoints Only + * | | |This bit is valid only If thresholding is enabled + * | | |The core generates this interrupt when it detects a transmit FIFO underrun condition for this endpoint. + * | | |Values: + * | | |0x0 (INACTIVE): No Tx FIFO Underrun interrupt + * | | |0x1 (ACTIVE): TxFIFO Underrun interrupt + * |[9] |BNAIntr |BNA (Buffer Not Available) Interrupt (BNAIntr) + * | | |The core generates this interrupt when the descriptor accessed is not ready for the Core to process, such as Host busy or DMA done. + * | | |Values: + * | | |0x0 (INACTIVE): No BNA interrupt + * | | |0x1 (ACTIVE): BNA interrupt + * |[12] |BbleErr |NAK Interrupt (BbleErr) + * | | |The core generates this interrupt when babble is received for the endpoint. + * | | |Values: + * | | |0x0 (INACTIVE): No interrupt + * | | |0x1 (ACTIVE): BbleErr interrupt + * |[13] |NAKIntrpt |NAK Interrupt (NAKInterrupt) + * | | |The core generates this interrupt when a NAK is transmitted or received by the device + * | | |In case of isochronous IN endpoints the interrupt gets generated when a zero length packet is transmitted due to un-availability of data in the TXFifo. + * | | |Values: + * | | |0x0 (INACTIVE): No NAK interrupt + * | | |0x1 (ACTIVE): NAK Interrupt + * |[14] |NYETIntrpt|NYET Interrupt (NYETIntrpt) + * | | |The core generates this interrupt when a NYET response is transmitted for a non isochronous OUT endpoint. + * | | |Values: + * | | |0x0 (INACTIVE): No NYET interrupt + * | | |0x1 (ACTIVE): NYET Interrupt + * @var HSUSBD_T::DIEPDMAn + * Offset: 0x14 Device IN Endpoint n DMA Address Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[31:0] |DMAAddr |Holds the start address of the external memory for storing or fetching endpoint data + * | | |Note: For control endpoints, this field stores control OUT data packets as well as SETUP transaction data packets + * | | |When more than three SETUP packets are received back-to-back, the SETUP data packet in the memory is overwritten. + * | | |This register is incremented on every AHB transaction + * | | |The application can give only a DWORD-aligned address. + * | | |This field indicates the base pointer for the descriptor list. + * @var HSUSBD_T::DTXFSTSn + * Offset: 0x18 Device IN Endpoint Transmit FIFO Status Register n + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[15:0] |INEPTxFSpcAvail|IN Endpoint TxFIFO Space Avail (INEPTxFSpcAvail) + * | | |Indicates the amount of free space available in the Endpoint TxFIFO. + * | | |Values are in terms of 32-bit words. + * | | |16'h0: Endpoint TxFIFO is full + * | | |16'h1: 1 word available + * | | |16'h2: 2 words available + * | | |16'hn: n words available (where 0 n 32,768) + * | | |16'h8000: 32,768 words available + * | | |Others: Reserved + * @var HSUSBD_T::DIEPDMABn + * Offset: 0x1C Device IN Endpoint n Buffer Address Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[31:0] |DMABufferAddr|Holds the current buffer address This register is updated as and when the data transfer for the corresponding end point is in progress + */ + + + __IO uint32_t DIEPCTL; /*!< [0x000] Device Control IN Endpoint n Control Register */ + __I uint32_t RESERVE1[1]; + __IO uint32_t DIEPINT; /*!< [0x008] Device IN Endpoint n Interrupt Register */ + __I uint32_t RESERVE2[2]; + __IO uint32_t DIEPDMA; /*!< [0x014] Device IN Endpoint n DMA Address Register */ + __I uint32_t DTXFSTS; /*!< [0x018] Device IN Endpoint Transmit FIFO Status Register n */ + __I uint32_t DIEPDMAB; /*!< [0x01c] Device IN Endpoint n Buffer Address Register */ + +} HSUSBD_IEP_T; + + + +/*----- OUT Endpoint 1~8 -----*/ +typedef struct +{ + + /** + + * @var HSUSBD_T::DOEPCTLn + * Offset: 0x00 Device Control OUT Endpoint n Control Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[10:0] |MPS |Maximum Packet Size (MPS)Maximum Packet Size + * | | |The application must program this field with the maximum packet size for the current logical endpoint + * | | |This value is in bytes. + * |[15] |USBActEP |USB Active Endpoint (USBActEP)USB Active Endpoint + * | | |Indicates whether this endpoint is active in the current configuration and interface + * | | |The core clears this bit for all endpoints (other than EP 0) after detecting a USB reset + * | | |After receiving the SetConfiguration and SetInterface commands, the application must program endpoint registers accordingly and set this bit. + * | | |Values: + * | | |0x0 (DISABLED): Not Active + * | | |0x1 (ENABLED): USB Active Endpoint + * |[16] |DPID |Endpoint Data PID (DPID) (Read only)Endpoint Data PID (Read only) + * | | |Applies to interrupt/bulk IN and OUT endpoints only. + * | | |Contains the PID of the packet to be received or transmitted on this endpoint + * | | |The application must program the PID of the first packet to be received or transmitted on this endpoint, after the endpoint is activated + * | | |The applications use the SetD1PID and SetD0PID fields of this register to program either DATA0 or DATA1 PID. + * | | |1'b0: DATA0 + * | | |1'b1: DATA1 + * | | |Values: + * | | |0x0 (INACTIVE): Endpoint Data PID not active + * | | |0x1 (ACTIVE): Endpoint Data PID active + * |[17] |NAKSts |NAK Status (NAKSts) (Read only)NAK Status (Read only) + * | | |Indicates the following: + * | | |1'b0: The core is transmitting non-NAK handshakes based on the FIFO status. + * | | |1'b1: The core is transmitting NAK handshakes on this endpoint. + * | | |When either the application or the core sets this bit: + * | | |The core stops receiving any data on an OUT endpoint, even if there is space in the RxFIFO to accommodate the incoming packet. + * | | |For non-isochronous IN endpoints: The core stops transmitting any data on an IN endpoint, even if there data is available in the TxFIFO. + * | | |For isochronous IN endpoints: The core sends out a zero-length data packet, even if there data is available in the TxFIFO. + * | | |Irrespective of this bit's setting, the core always responds to SETUP data packets with an ACK handshake. + * | | |Values: + * | | |0x0 (NONNAK): + * | | |The core is transmitting non-NAK handshakes based on the FIFO status + * | | |0x1 (NAK): + * | | |The core is transmitting NAK handshakes on this endpoint + * |[19:18] |EPType |Endpoint Type (EPType)Endpoint Type + * | | |This is the transfer type supported by this logical endpoint. + * | | |2'b00: Control + * | | |2'b01: Isochronous + * | | |2'b10: Bulk + * | | |2'b11: Interrupt + * | | |Values: + * | | |0x0 (CONTROL): Control + * | | |0x1 (ISOCHRONOUS): Isochronous + * | | |0x2 (BULK): Bulk + * | | |0x3 (INTERRUPT): Interrupt + * |[20] |Snp |Reserved. + * |[21] |Stall |STALL Handshake (Stall)STALL Handshake + * | | |Applies to non-control, non-isochronous IN and OUT endpoints only. + * | | |The application sets this bit to stall all tokens from the USB host to this endpoint + * | | |If a NAK bit, Global Non-periodic IN NAK, or Global OUT NAK is set along with this bit, the STALL bit takes priority + * | | |Only the application can clear this bit, never the core. + * | | |Applies to control endpoints only. + * | | |The application can only set this bit, and the core clears it, when a SETUP token is received for this endpoint + * | | |If a NAK bit, Global Non-periodic IN NAK, or Global OUT NAK is set along with this bit, the STALL bit takes priority + * | | |Irrespective of this bit's setting, the core always responds to SETUP data packets with an ACK handshake. + * | | |Values: + * | | |0x0 (INACTIVE): STALL All non-active tokens + * | | |0x1 (ACTIVE): STALL All Active Tokens + * |[26] |CNAK |Clear NAK (CNAK)Clear NAK A write to this bit clears the NAK bit for the endpoint + * | | |Values: + * | | |0x0 (INACTIVE): No Clear NAK + * | | |0x1 (ACTIVE): Clear NAK + * |[27] |SNAK |Set NAK (SNAK)Set NAK + * | | |A write to this bit sets the NAK bit for the endpoint. + * | | |Using this bit, the application can control the transmission of NAK handshakes on an endpoint + * | | |The core can also set this bit for an endpoint after a SETUP packet is received on that endpoint. + * | | |Values: + * | | |0x0 (INACTIVE): No Set NAK + * | | |0x1 (ACTIVE): Set NAK + * |[28] |SetD0PID |Set DATA0 PID (SetD0PID)Set DATA0 PID + * | | |Applies to interrupt/bulk IN and OUT endpoints only. + * | | |Writing to this field sets the Endpoint Data PID (DPID) field in this register to DATA0. + * | | |Values: + * | | |0x0 (DISABLED): Disables Set DATA0 PID or Do not force Even Frame + * | | |0x1 (ENABLED): Set Endpoint Data PID to DATA0 or Sets EO_FrNum field to odd (micro)Frame + * |[29] |SetD1PID |Set DATA1 PID (SetD1PID)Set DATA1 PID + * | | |Applies to interrupt and bulk IN and OUT endpoints only. + * | | |Writing to this field sets the Endpoint Data PID (DPID) field in this register to DATA1. + * | | |Values: + * | | |0x0 (DISABLED): Disables Set DATA1 PID or Do not force Odd Frame + * | | |0x1 (ENABLED): Set Endpoint Data PID to DATA1 or Sets EO_FrNum field to odd (micro)Frame + * |[30] |EPDis |Endpoint Disable (EPDis)Endpoint Disable + * | | |Applies to IN and OUT endpoints. + * | | |The application sets this bit to stop transmitting/receiving data on an endpoint, even before the transfer for that endpoint is complete + * | | |The application must wait for the Endpoint Disabled interrupt before treating the endpoint as disabled + * | | |The core clears this bit before setting the Endpoint Disabled interrupt + * | | |The application must set this bit only if Endpoint Enable is already set for this endpoint. + * | | |Values: + * | | |0x0 (INACTIVE): No Action + * | | |0x1 (ACTIVE): Disable Endpoint + * |[31] |EPEna |Endpoint Enable (EPEna)Endpoint Enable + * | | |Applies to IN and OUT endpoints. + * | | |For IN endpoints this bit indicates that the descriptor structure and data buffer with data ready to transmit is setup. + * | | |For OUT endpoint it indicates that the descriptor structure and data buffer to receive data is setup. + * | | |The core clears this bit before setting any of the following interrupts on this endpoint: + * | | |SETUP Phase Done + * | | |Endpoint Disabled + * | | |Transfer Completed + * | | |Note: For control endpoints in DMA mode, this bit must be set for the controller to transfer SETUP data packets to the memory + * | | |This bit will not be cleared on Transfer Completed interrupt of the SETUP packet. + * | | |Values: + * | | |0x0 (INACTIVE): No Action + * | | |0x1 (ACTIVE): Enable Endpoint + * @var HSUSBD_T::DOEPINTn + * Offset: 0x08 Device OUT Endpoint n Interrupt Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[0] |XferCompl |Transfer Completed Interrupt (XferCompl) Transfer Completed Interrupt + * | | |Applies to IN and OUT endpoints. + * | | |When Scatter/Gather DMA mode is enabled + * | | |For IN endpoint this field indicates that the requested data from the descriptor is moved from external system memory to internal FIFO. + * | | |For OUT endpoint this field indicates that the requested data from the internal FIFO is moved to external system memory + * | | |This interrupt is generated only when the corresponding endpoint descriptor is closed, and the IOC bit for the corresponding descriptor is Set. + * | | |Values: + * | | |0x0 (INACTIVE): No Transfer Complete Interrupt + * | | |0x1 (ACTIVE): Transfer Complete Interrupt + * |[1] |EPDisbld |Endpoint Disabled Interrupt (EPDisbld)Endpoint Disabled Interrupt + * | | |Applies to IN and OUT endpoints. + * | | |This bit indicates that the endpoint is disabled per the application's request. + * | | |Values: + * | | |0x0 (INACTIVE): No Endpoint Disabled Interrupt + * | | |0x1 (ACTIVE): Endpoint Disabled Interrupt + * |[2] |AHBErr |AHB Error (AHBErr)AHB Error + * | | |Applies to IN and OUT endpoints. + * | | |When there is an AHB error during an AHB read/write + * | | |The application can read the corresponding endpoint DMA address register to get the error address. + * | | |Values: + * | | |0x0 (INACTIVE): No AHB Error Interrupt + * | | |0x1 (ACTIVE): AHB Error interrupt + * |[3] |SetUp |SETUP Phase Done (SetUp)SETUP Phase Done + * | | |Applies to control OUT endpoints only. + * | | |Indicates that the SETUP phase for the control endpoint is complete and no more back-to-back SETUP packets were received for the current control transfer + * | | |On this interrupt, the application can decode the received SETUP data packet. + * | | |Values: + * | | |0x0 (INACTIVE): No SETUP Phase Done + * | | |0x1 (ACTIVE): SETUP Phase Done + * |[4] |OUTTknEPdis|OUT Token Received When Endpoint Disabled (OUTTknEPdis)OUT Token Received When Endpoint Disabled + * | | |Applies only to control OUT endpoints. + * | | |Indicates that an OUT token was received when the endpoint was not yet enabled + * | | |This interrupt is asserted on the endpoint for which the OUT token was received. + * | | |Values: + * | | |0x0 (INACTIVE): No OUT Token Received When Endpoint Disabled + * | | |0x1 (ACTIVE): OUT Token Received When Endpoint Disabled + * |[5] |StsPhseRcvd|Status Phase Received for Control Write (StsPhseRcvd)Status Phase Received for Control Write + * | | |This interrupt is valid only for Control OUT endpoints. + * | | |This interrupt is generated only after the core has transferred all the data that the host has sent during the data phase of a control write transfer, to the system memory buffer. + * | | |The interrupt indicates to the application that the host has switched from data phase to the status phase of a Control Write transfer + * | | |The application can use this interrupt to ACK or STALL the Status phase, after it has decoded the data phase + * | | |This is applicable only in Case of Scatter Gather DMA mode. + * | | |Values: + * | | |0x0 (INACTIVE): No Status Phase Received for Control Write + * | | |0x1 (ACTIVE): Status Phase Received for Control Write + * |[6] |Back2BackSETup|Back-to-Back SETUP Packets Received (Back2BackSETup)Back-to-Back SETUP Packets Received + * | | |Applies to Control OUT endpoints only. + * | | |This bit indicates that the core has received more than three back-to-back SETUP packets for this particular endpoint + * | | |For information about handling this interrupt, + * | | |Values: + * | | |0x0 (INACTIVE): No Back-to-Back SETUP Packets Received + * | | |0x1 (ACTIVE): Back-to-Back SETUP Packets Received + * |[8] |OutPktErr |OUT Packet Error (OutPktErr)OUT Packet Error + * | | |Applies to OUT endpoints Only + * | | |This interrupt is valid only when thresholding is enabled + * | | |This interrupt is asserted when the core detects an overflow or a CRC error for non-Isochronous OUT packet. + * | | |Values: + * | | |0x0 (INACTIVE): No OUT Packet Error + * | | |0x1 (ACTIVE): OUT Packet Error + * |[9] |BNAIntr |BNA (Buffer Not Available) Interrupt (BNAIntr)Buffer Not Available Interrupt + * | | |The core generates this interrupt when the descriptor accessed is not ready for the Core to process, such as Host busy or DMA done + * | | |Values: + * | | |0x0 (INACTIVE): No BNA interrupt + * | | |0x1 (ACTIVE): BNA interrupt + * |[12] |BbleErr |NAK Interrupt (BbleErr)NAK Interrupt + * | | |The core generates this interrupt when babble is received for the endpoint. + * | | |Values: + * | | |0x0 (INACTIVE): No BbleErr interrupt + * | | |0x1 (ACTIVE): BbleErr interrupt + * |[13] |NAKIntrpt |NAK Interrupt (NAKInterrupt)NAK Interrupt + * | | |The core generates this interrupt when a NAK is transmitted or received by the device. + * | | |In case of isochronous IN endpoints the interrupt gets generated when a zero length packet is transmitted due to un-availability of data in the TXFifo. + * | | |Values: + * | | |0x0 (INACTIVE): No NAK interrupt + * | | |0x1 (ACTIVE): NAK Interrupt + * |[14] |NYETIntrpt|NYET Interrupt (NYETIntrpt)NYET Interrupt + * | | |The core generates this interrupt when a NYET response is transmitted for a non isochronous OUT endpoint. + * | | |Values: + * | | |0x0 (INACTIVE): No NYET interrupt + * | | |0x1 (ACTIVE): NYET Interrupt + * @var HSUSBD_T::DOEPDMAn + * Offset: 0x14 Device OUT Endpoint n DMA Address Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[31:0] |DMAAddr |Holds the start address of the external memory for storing or fetching endpoint data + * | | |Note: For control endpoints, this field stores control OUT data packets as well as SETUP transaction data packets + * | | |When more than three SETUP packets are received back-to-back, the SETUP data packet in the memory is overwritten. + * | | |This register is incremented on every AHB transaction + * | | |The application can give only a DWORD-aligned address + * @var HSUSBD_T::DOEPDMABn + * Offset: 0x1C Device OUT Endpoint n Buffer Address Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[31:0] |DMABufferAddr|Holds the current buffer address This register is updated as and when the data transfer for the corresponding end point is in progress. + */ + + __IO uint32_t DOEPCTL; /*!< [0x000] Device Control OUT Endpoint n Control Register */ + __I uint32_t RESERVE1[1]; + __IO uint32_t DOEPINT; /*!< [0x008] Device OUT Endpoint n Interrupt Register */ + __I uint32_t RESERVE2[2]; + __IO uint32_t DOEPDMA; /*!< [0x014] Device OUT Endpoint n DMA Address Register */ + __I uint32_t RESERVE3[1]; + __I uint32_t DOEPDMAB; /*!< [0x01c] Device OUT Endpoint n Buffer Address Register */ + +} HSUSBD_OEP_T; + + +typedef struct +{ + + + /** + * @var HSUSBD_T::GOTGCTL + * Offset: 0x00 Control and Status Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[27] |ChirpEn |Mode: Device Only + * | | |This bit when programmed to 1'b1 results in the core asserting chirp_on before sending an actual Chirp "K" signal on USB. + * | | |0x0 (CHIRP_DISABLE): The controller does not assert chirp_on before sending an actual Chirp "K" signal on USB. + * | | |0x1 (CHIRP_ENABLE): The controller asserts chirp_on before sending an actual Chirp "K" signal on USB. + * |[31] |Testmode_corr_eUSB2|UTMI IF correction for eUSB2 PHY during Test mode + * | | |This bit is used to modify the behavior of UTMI 8-bit interface signals during test J and test K sequences when eUSB2 PHY is used. + * | | |When this bit is set to 1'b1, the controller asserts utmi_txvalid and utmi_opmode in the same cycle during test J or test K sequence execution. + * | | |Note: This bit is applicable only if eUSB2 PHY is used with 8-bit UTMI interface. + * | | |0x0 (eUSB2_corr_disable): The controller asserts utmi_txvalid one cycle later than utmi_opmode. + * | | |0x1 (eUSB2_corr_enable): The controller asserts utmi_txvalid and utmi_opmode in the same cycle. + * @var HSUSBD_T::GAHBCFG + * Offset: 0x08 AHB Configuration Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[0] |GlblIntrMsk|Global Interrupt Mask (GlblIntrMsk) + * | | |The application uses this bit to mask or unmask the interrupt line assertion to itself + * | | |Irrespective of this bit's setting, the interrupt status registers are updated by the controller. + * | | |1'b0: Mask the interrupt assertion to the application. + * | | |1'b1: Unmask the interrupt assertion to the application. + * | | |Values: + * | | |0x0 (MASK): Mask the interrupt assertion to the application + * | | |0x1 (NOMASK): Unmask the interrupt assertion to the application. + * |[4:1] |HBstLen |Burst Length/Type (HBstLen) + * | | |Internal DMA Mode AHB Master burst type: + * | | |4'b0000 Single + * | | |4'b0001 INCR + * | | |4'b0011 INCR4 + * | | |4'b0101 INCR8 + * | | |4'b0111 INCR16 + * | | |Others: Reserved + * | | |Values: + * | | |0x0 (WORD1ORSINGLE): 1 word or single + * | | |0x1 (WORD4ORINCR): 4 words or INCR + * | | |0x3 (WORD16ORINCR4): 16 words or INCR4 + * | | |0x5 (WORD64ORINCR8): 64 words or INCR8 + * | | |0x7 (WORD256ORINCR16): 256 words or INCR16 + * |[5] |DMAEn |DMA Enable (DMAEn) + * | | |Reset: 1'b0 + * | | |Values: + * | | |0x1 (DMAMODE): Core operates in a DMA mode + * |[23] |AHBSingle |AHB Single Support (AHBSingle) + * | | |This bit when programmed supports Single transfers for the remaining data in a transfer when the core is operating in DMA mode. + * | | |1'b0: The remaining data in the transfer is sent using INCR burst size. + * | | |1'b1: The remaining data in the transfer is sent using Single burst size. + * | | |Note: If this feature is enabled, the AHB RETRY and SPLIT transfers still have INCR burst type + * | | |Enable this feature when the AHB Slave connected to the core does not support INCR burst (and when Split, and Retry transactions are not being used in the bus). + * | | |Values: + * | | |0x0 (INCRBURST): The remaining data in the transfer is sent using INCR burst size + * | | |0x1 (SINGLEBURST): The remaining data in the transfer is sent using Single burst size + * |[24] |InvDescEndianess|Invert Descriptor Endianess (InvDescEndianess) + * | | |1'b0: Descriptor Endianness is same as AHB Master Endianness. + * | | |1'b1: + * | | |If the AHB Master endianness is Big Endian, the Descriptor Endianness is Little Endian. + * | | |If the AHB Master endianness is Little Endian, the Descriptor Endianness is Big Endian. + * | | |Values: + * | | |0x0 (DISABLE): Descriptor Endianness is same as AHB Master Endianness + * | | |0x1 (ENABLE): Descriptor Endianness is opposite to AHB Master Endianness + * @var HSUSBD_T::GUSBCFG + * Offset: 0x0C USB Configuration Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[2:0] |TOutCal |HS/FS Timeout Calibration (TOutCal) + * | | |The number of PHY clocks that the application programs in this field is added to the high-speed/full-speed interpacket timeout duration in the core to account for any additional delays introduced by the PHY + * | | |This can be required, because the delay introduced by the PHY in generating the linestate condition can vary from one PHY to another. + * | | |The USB standard timeout value for high-speed operation is 736 to 816 (inclusive) bit times + * | | |The USB standard timeout value for full-speed operation is 16 to 18 (inclusive) bit times + * | | |The application must program this field based on the speed of enumeration + * | | |The number of bit times added per PHY clock are as follows: + * | | |High-speed operation: + * | | |One 60- MHz PHY clock = 8 bit times. + * | | |Full-speed operation: + * | | |One 60- MHz PHY clock = 0.2 bit times. + * |[13:10] |USBTrdTim |USB Turnaround Time (USBTrdTim) + * | | |Sets the turnaround time in PHY clocks + * | | |Specifies the response time for a MAC request to the Packet FIFO Controller (PFC) to fetch data from the DFIFO (Interanl Storage) + * | | |This must be programmed to + * | | |4'h9: When the MAC interface is 8-bit UTMI+ . + * | | |Values: + * | | |0x9 (TURNTIME8BIT): MAC interface is 8-bit UTMI+. + * |[28] |TxEndDelay|Tx End Delay (TxEndDelay) + * | | |Writing 1'b1 to this bit enables the controller to follow the TxEndDelay timings as per UTMI+ specification 1.05 section 4.1.5 for opmode signal during remote wakeup. + * | | |1'b0 : Normal Mode. + * | | |1'b1 : Tx End delay. + * | | |Values: + * | | |0x0 (DISABLED): Normal Mode + * | | |0x1 (ENABLED): Tx End delay + * @var HSUSBD_T::GRSTCTL + * Offset: 0x10 Reset Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[0] |CSftRst |Core Soft Reset (CSftRst) + * | | |Resets the hclk and phy_clock domains as follows: + * | | |Clears the interrupts and all the CSR registers except the following register bits: + * | | |GUSBCFG.TxEndDelay + * | | |DCFG.DevSpd + * | | |DCTL.SftDiscon + * | | |All module state machines + * | | |All module state machines (except the AHB Slave Unit) are reset to the IDLE state, and all the transmit FIFOs and the receive FIFO are flushed. + * | | |Any transactions on the AHB Master are terminated as soon as possible, after gracefully completing the last data phase of an AHB transfer + * | | |Any transactions on the USB are terminated immediately. + * | | |The application can write to this bit any time it wants to reset the core + * | | |This is a self-clearing bit and the core clears this bit after all the necessary logic is reset in the core, which can take several clocks, depending on the current state of the core + * | | |Once this bit is cleared software must wait at least 3 PHY clocks before doing any access to the PHY domain (synchronization delay) + * | | |Software must also must check that bit 31 of this register is 1 (AHB Master is IDLE) before starting any operation. + * | | |Typically software reset is used during software development and also when you dynamically change the PHY selection bits in the USB configuration registers listed above + * | | |When you change the PHY, the corresponding clock for the PHY is selected and used in the PHY domain + * | | |Once a new clock is selected, the PHY domain has to be reset for proper operation. + * | | |Values: + * | | |0x0 (NOTACTIVE): No reset + * | | |0x1 (ACTIVE): Resets hclk and phy_clock domains + * |[1] |PIUFSSftRst|PIU FS Dedicated Controller Soft Reset (PIUFSSftRst) + * | | |Resets the PIU FS Dedicated Controller + * | | |All module state machines in FS Dedicated Controller of PIU are reset to the IDLE state + * | | |Used to reset the FS Dedicated controller in PIU in case of any PHY Errors like Loss of activity or Babble Error resulting in the PHY remaining in RX state for more than one frame boundary. + * | | |This is a self clearing bit and core clears this bit after all the necessary logic is reset in the core. + * | | |Values: + * | | |0x0 (RESET_INACTIVE): No Reset + * | | |0x1 (RESET_ACTIVE): PIU FS Dedicated Controller Soft Reset + * |[4] |RxFFlsh |RxFIFO Flush (RxFFlsh) + * | | |The application can flush the entire RxFIFO using this bit, but must first ensure that the core is not in the middle of a transaction. + * | | |The application must only write to this bit after checking that the controller is neither reading from the RxFIFO nor writing to the RxFIFO. + * | | |The application must wait until the bit is cleared before performing any other operations + * | | |This bit requires eight clocks (slowest of PHY or AHB clock) to clear. + * | | |Values: + * | | |0x0 (INACTIVE): Does not flush the entire RxFIFO + * | | |0x1 (ACTIVE): Flushes the entire RxFIFO + * |[5] |TxFFlsh |TxFIFO Flush (TxFFlsh) + * | | |This bit selectively flushes a single or all transmit FIFOs, but cannot do so If the core is in the midst of a transaction. + * | | |The application must write this bit only after checking that the core is neither writing to the TxFIFO nor reading from the TxFIFO. + * | | |Verify using these registers: + * | | |ReadNAK Effective Interrupt ensures the core is not reading from the FIFO + * | | |WriteGRSTCTL.AHBIdle ensures the core is not writing anything to the FIFO. + * | | |Flushing is normally recommended when FIFOs are reconfigured + * | | |FIFO flushing is also recommended during device endpoint disable + * | | |The application must wait until the core clears this bit before performing any operations + * | | |This bit takes eight clocks to clear, using the slower clock of phy_clk or hclk. + * | | |Values: + * | | |0x0 (INACTIVE): No Flush + * | | |0x1 (ACTIVE): Selectively flushes a single or all transmit FIFOs + * |[10:6] |TxFNum |TxFIFO Number (TxFNum) + * | | |This is the FIFO number that must be flushed using the TxFIFO Flush bit + * | | |This field must not be changed until the core clears the TxFIFO Flush bit. + * | | |5'h0: + * | | |Tx FIFO 0 flush in device mode when in dedicated FIFO mode + * | | |5'h1: + * | | |TXFIFO 1 flush in device mode when in dedicated FIFO mode + * | | |5'h2: + * | | |TXFIFO 2 flush in device mode when in dedicated FIFO mode + * | | |... + * | | |5'h8 + * | | |TXFIFO 8 flush in device mode when in dedicated FIFO mode + * | | |5'h10: Flush all the transmit FIFOs + * | | |Values: + * | | |0x0 (TXF0): TXFIFO 0 flush in device mode when in dedicated FIFO mode + * | | |0x1 (TXF1): TXFIFO 1 flush in device mode when in dedicated FIFO mode + * | | |0x2 (TXF2): TXFIFO 2 flush in device mode when in dedicated FIFO mode + * | | |0x3 (TXF3): TXFIFO 3 flush in device mode when in dedicated FIFO mode + * | | |0x4 (TXF4): TXFIFO 4 flush in device mode when in dedicated FIFO mode + * | | |0x5 (TXF5): TXFIFO 5 flush in device mode when in dedicated FIFO mode + * | | |0x6 (TXF6): TXFIFO 6 flush in device mode when in dedicated FIFO mode + * | | |0x7 (TXF7): TXFIFO 7 flush in device mode when in dedicated FIFO mode + * | | |0x8 (TXF8): TXFIFO 8 flush in device mode when in dedicated FIFO mode + * | | |0x10 (TXF16): Flush all the transmit FIFOs + * |[31] |AHBIdle |AHB Master Idle (AHBIdle)(Read only) + * | | |Indicates that the AHB Master State Machine is in the IDLE condition. + * | | |Values: + * | | |0x0 (INACTIVE): Not Idle + * | | |0x1 (ACTIVE): AHB Master Idle + * @var HSUSBD_T::GINTSTS + * Offset: 0x14 Interrupt Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[3] |Sof |Start of (micro)Frame (Sof) + * | | |In Device mode, the controller sets this bit to indicate that an SOF token has been received on the USB + * | | |The application can read the Device Status register to get the current (micro)Frame number + * | | |This interrupt is seen only when the core is operating at either HS or FS + * | | |This bit can be set only by the core and the application must write 1 to clear it. + * | | |Note: This register may return 1'b1 if read immediately after power-on reset + * | | |If the register bit reads 1'b1 immediately after power-on reset, it does not indicate that an SOF has been received + * | | |The read value of this interrupt is valid only after a valid connection between host and device is established + * | | |If the bit is set after power on reset the application can clear the bit. + * | | |Values: + * | | |0x0 (INTACTIVE): No Start of Frame + * | | |0x1 (ACTIVE): Start of Frame + * |[4] |RxFLvl |RxFIFO Non-Empty (RxFLvl)(Read only) + * | | |Indicates that there is at least one packet pending to be read from the RxFIFO. + * | | |Values: + * | | |0x0 (INACTIVE): Rx Fifo is empty + * | | |0x1 (ACTIVE): Rx Fifo is not empty + * |[6] |GINNakEff |Global IN Non-periodic NAK Effective (GINNakEff)(Read only) + * | | |Indicates that the Set Global Non-periodic IN NAK bit in the Device Control register (DCTL.SGNPInNak) set by the application, has taken effect in the core + * | | |That is, the core has sampled the Global IN NAK bit Set by the application + * | | |This bit can be cleared by clearing the Clear Global Non-periodic IN NAK bit in the Device Control register (DCTL.CGNPInNak) + * | | |This interrupt does not necessarily mean that a NAK handshake is sent out on the USB + * | | |The STALL bit takes precedence over the NAK bit. + * | | |Values: + * | | |0x0 (INACTIVE): Global Non-periodic IN NAK not active + * | | |0x1 (ACTIVE): Set Global Non-periodic IN NAK bit + * |[7] |GOUTNakEff|Global OUT NAK Effective (GOUTNakEff)(Read only) + * | | |Indicates that the Set Global OUT NAK bit in the Device Control register (DCTL.SGOUTNak), Set by the application, has taken effect in the core + * | | |This bit can be cleared by writing the Clear Global OUT NAK bit in the Device Control register (DCTL.CGOUTNak). + * | | |Values: + * | | |0x0 (INACTIVE): Not Active + * | | |0x1 (ACTIVE): Global OUT NAK Effective + * |[10] |ErlySusp |Early Suspend (ErlySusp) + * | | |The controller sets this bit to indicate that an Idle state has been detected on the USB for 3 ms. + * | | |Values: + * | | |0x0 (INACTIVE): No Idle state detected + * | | |0x1 (ACTIVE): 3ms of Idle state detected + * |[11] |USBSusp |USB Suspend (USBSusp) + * | | |The controller sets this bit to indicate that a suspend was detected on the USB + * | | |The controller enters the Suspended state when there is no activity on the linestate signal for an extended period of time. + * | | |Values: + * | | |0x0 (INACTIVE): Not Active + * | | |0x1 (ACTIVE): USB Suspend + * |[12] |USBRst |USB Reset (USBRst) + * | | |The controller sets this bit to indicate that a reset is detected on the USB. + * | | |Values: + * | | |0x0 (INACTIVE): Not active + * | | |0x1 (ACTIVE): USB Reset + * |[13] |EnumDone |Enumeration Done (EnumDone) + * | | |The core sets this bit to indicate that speed enumeration is complete + * | | |The application must read the Device Status (DSTS) register to obtain the enumerated speed. + * | | |Values: + * | | |0x0 (INACTIVE): Not active + * | | |0x1 (ACTIVE): Enumeration Done + * |[14] |ISOOutDrop|Isochronous OUT Packet Dropped Interrupt (ISOOutDrop) + * | | |The controller sets this bit when it fails to write an isochronous OUT packet into the RxFIFO because the RxFIFO does not have enough space to accommodate a maximum packet size packet for the isochronous OUT endpoint. + * | | |Values: + * | | |0x0 (INACTIVE): Not active + * | | |0x1 (ACTIVE): Isochronous OUT Packet Dropped Interrupt + * |[15] |EOPF |End of Periodic Frame Interrupt (EOPF) + * | | |Indicates that the period specified in the Periodic Frame Interval field of the Device Configuration register (DCFG.PerFrInt) has been reached in the current microframe + * | | |In case of Non-Ignore Frame Number Scatter/Gather (Descriptor DMA) mode, the controller internally handles the following scenarios based on EOPF: + * | | |Read Flush: At the EOPF, the controller checks if there are any pending packets in the FIFO corresponding to the current (micro)Frame. + * | | |If there are any pending packets, then the controller initiates read flush, due to which the read pointer is updated to the starting location of the next micro-frame packet. + * | | |If there are no pending packets corresponding to the current (micro)Frame, the controller does not take any action. + * | | |Write Flush: At the EOPF, if the controller is still fetching the current micro-frame data, then the controller stops pushing data into the TXFIFO but keeps fetching the complete packet from the System Memory + * | | |After completing the scheduled packet size fetch, the controller updates the Status Quadlet Fields (Transmit Status to BUFFLUSH) and closes the Descriptor + * | | |During the descriptor close, the controller initiates write flush, due to which the write pointer is updated to the starting location of the next micro-frame packet + * | | |Because the controller stops pushing the packet to the TxFIFO after EOPF, to bring the write pointer to the starting location of the next micro-frame, write flush is done. + * | | |Values: + * | | |0x0 (INACTIVE): Not active + * | | |0x1 (ACTIVE): End of Periodic Frame Interrupt + * |[18] |IEPInt |IN Endpoints Interrupt (IEPInt)(Read only) + * | | |The core sets this bit to indicate that an interrupt is pending on one of the IN endpoints of the core + * | | |The application must read the Device All Endpoints Interrupt (DAINT) register to determine the exact number of the IN endpoint on Device IN Endpoint-n Interrupt (DIEPINTn) register to determine the exact cause of the interrupt + * | | |The application must clear the appropriate status bit in the corresponding DIEPINTn register to clear this bit. + * | | |Values: + * | | |0x0 (INACTIVE): Not active + * | | |0x1 (ACTIVE): IN Endpoints Interrupt + * |[19] |OEPInt |OUT Endpoints Interrupt (OEPInt)(Read only) + * | | |The controller sets this bit to indicate that an interrupt is pending on one of the OUT endpoints of the core + * | | |The application must read the Device All Endpoints Interrupt (DAINT) register to determine the exact number of the OUT endpoint on which the interrupt occurred, and then read the corresponding Device OUT Endpoint-n Interrupt (DOEPINTn) register to determine the exact cause of the interrupt + * | | |The application must clear the appropriate status bit in the corresponding DOEPINTn register to clear this bit. + * | | |Values: + * | | |0x0 (INACTIVE): Not active + * | | |0x1 (ACTIVE): OUT Endpoints Interrupt + * |[22] |FetSusp |Data Fetch Suspended (FetSusp) + * | | |This interrupt indicates that the core has stopped fetching data + * | | |For IN endpoints due to the unavailability of TxFIFO space or Request Queue space + * | | |This interrupt is used by the application for an endpoint mismatch algorithm. + * | | |For example, after detecting an endpoint mismatch, the application: + * | | |Sets a Global non-periodic IN NAK handshake + * | | |Disables IN endpoints + * | | |Flushes the FIFO + * | | |Determines the token sequence from the IN Token Sequence Learning Queue + * | | |Re-enables the endpoints + * | | |Clears the Global non-periodic IN NAK handshake + * | | |If the Global non-periodic IN NAK is cleared, the core has not yet fetched data for the IN endpoint, and the IN token is received + * | | |The core generates an 'IN token received when FIFO empty' interrupt + * | | |It then sends the host a NAK response + * | | |To avoid this scenario, the application can check the GINTSTS.FetSusp interrupt, which ensures that the FIFO is full before clearing a Global NAK handshake. + * | | |Alternatively, the application can mask the IN token received when FIFO empty interrupt when clearing a Global IN NAK handshake. + * | | |Values: + * | | |0x0 (INACTIVE): Not active + * | | |0x1 (ACTIVE): Data Fetch Suspended + * |[23] |ResetDet |Reset detected Interrupt (ResetDet) + * | | |In Device mode, this interrupt is asserted when a reset is detected on the USB in partial power-down mode when the device is in Suspend. + * | | |Values: + * | | |0x0 (INACTIVE): Not active + * | | |0x1 (ACTIVE): Reset detected Interrupt + * |[27] |LPM_Int |LPM Transaction Received Interrupt + * | | |(LPM_Int) This interrupt is asserted when the device receives an LPM transaction and responds with a non-ERRORed response has completed LPM transactions for the programmed number of times (GLPMCFG.RetryCnt) + * | | |Values: + * | | |0x0 (INACTIVE): Not Active + * | | |0x1 (ACTIVE): LPM Transaction Received Interrupt + * |[31] |WkUpInt |Resume/Remote Wakeup Detected Interrupt (WkUpInt) + * | | |Wakeup Interrupt during Suspend(L2) or LPM(L1) state. + * | | |During Suspend(L2): + * | | |This interrupt is asserted only when Host Initiated Resume is detected on USB. + * | | |During LPM(L1): + * | | |This interrupt is asserted for either Host Initiated Resume or Device Initiated Remote Wakeup on USB. + * | | |Values: + * | | |0x0 (INACTIVE): Not active + * | | |0x1 (ACTIVE): Resume or Remote Wakeup Detected Interrupt + * @var HSUSBD_T::GINTMSK + * Offset: 0x18 Interrupt Mask Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[2] |OTGIntMsk |OTG Interrupt Mask (OTGIntMsk) + * | | |Values: + * | | |0x0 (MASK): OTG Interrupt Mask + * | | |0x1 (NOMASK): No OTG Interrupt Mask + * |[3] |SofMsk |Start of (micro) Frame Mask (SofMsk) + * | | |Values: + * | | |0x0 (MASK): Start of Frame Mask + * | | |0x1 (NOMASK): No Start of Frame Mask + * |[4] |RxFLvlMsk |Receive FIFO Non-Empty Mask (RxFLvlMsk) + * | | |Values: + * | | |0x0 (MASK): Receive FIFO Non-Empty Mask + * | | |0x1 (NOMASK): No Receive FIFO Non-Empty Mask + * |[6] |GINNakEffMsk|Global Non-periodic IN NAK Effective Mask (GINNakEffMsk) + * | | |Values: + * | | |0x0 (MASK): Global Non-periodic IN NAK Effective Mask + * | | |0x1 (NOMASK): No Global Non-periodic IN NAK Effective Mask + * |[7] |GOUTNakEffMsk|Global OUT NAK Effective Mask (GOUTNakEffMsk) + * | | |Values: + * | | |0x0 (MASK): Global OUT NAK Effective Mask + * | | |0x1 (NOMASK): No Global OUT NAK Effective Mask + * |[10] |ErlySuspMsk|Early Suspend Mask (ErlySuspMsk) + * | | |Values: + * | | |0x0 (MASK): Early Suspend Mask + * | | |0x1 (NOMASK): No Early Suspend Mask + * |[11] |USBSuspMsk|USB Suspend Mask (USBSuspMsk) + * | | |Values: + * | | |0x0 (MASK): USB Suspend Mask + * | | |0x1 (NOMASK): No USB Suspend Mask + * |[12] |USBRstMsk |USB Reset Mask (USBRstMsk) + * | | |Values: + * | | |0x0 (MASK): USB Reset Mask + * | | |0x1 (NOMASK): No USB Reset Mask + * |[13] |EnumDoneMsk|Enumeration Done Mask (EnumDoneMsk) + * | | |Values: + * | | |0x0 (MASK): Enumeration Done Mask + * | | |0x1 (NOMASK): No Enumeration Done Mask + * |[14] |ISOOutDropMsk|Isochronous OUT Packet Dropped Interrupt Mask (ISOOutDropMsk) + * | | |Values: + * | | |0x0 (MASK): Isochronous OUT Packet Dropped Interrupt Mask + * | | |0x1 (NOMASK): No Isochronous OUT Packet Dropped Interrupt Mask + * |[15] |EOPFMsk |End of Periodic Frame Interrupt Mask (EOPFMsk) + * | | |Values: + * | | |0x0 (MASK): End of Periodic Frame Interrupt Mask + * | | |0x1 (NOMASK): No End of Periodic Frame Interrupt Mask + * |[17] |EPMisMsk |Endpoint Mismatch Interrupt Mask (EPMisMsk) + * | | |Values: + * | | |0x0 (MASK): Endpoint Mismatch Interrupt Mask + * | | |0x1 (NOMASK): No Endpoint Mismatch Interrupt Mask + * |[18] |IEPIntMsk |IN Endpoints Interrupt Mask (IEPIntMsk) + * | | |Values: + * | | |0x0 (MASK): IN Endpoints Interrupt Mask + * | | |0x1 (NOMASK): No IN Endpoints Interrupt Mask + * |[19] |OEPIntMsk |OUT Endpoints Interrupt Mask (OEPIntMsk) + * | | |Values: + * | | |0x0 (MASK): OUT Endpoints Interrupt Mask + * | | |0x1 (NOMASK): No OUT Endpoints Interrupt Mask + * |[22] |FetSuspMsk|Data Fetch Suspended Mask (FetSuspMsk) + * | | |Values: + * | | |0x0 (MASK): Data Fetch Suspended Mask + * | | |0x1 (NOMASK): No Data Fetch Suspended Mask + * |[23] |ResetDetMsk|Reset detected Interrupt Mask (ResetDetMsk) + * | | |Values: + * | | |0x0 (MASK): Reset detected Interrupt Mask + * | | |0x1 (NOMASK): No Reset detected Interrupt Mask + * |[27] |LPM_IntMsk|LPM Transaction Received Interrupt (LPM_Int) + * | | |LPM Transaction received interrupt Mask + * | | |Values: + * | | |0x0 (MASK): LPM Transaction received interrupt Mask + * | | |0x1 (NOMASK): No LPM Transaction received interrupt Mask + * |[31] |WkUpIntMsk|Resume/Remote Wakeup Detected Interrupt Mask (WkUpIntMsk) + * | | |The WakeUp bit is used for LPM state wake up in a way similar to that of wake up in suspend state. + * | | |Values: + * | | |0x0 (MASK): Resume or Remote Wakeup Detected Interrupt Mask + * | | |0x1 (NOMASK): Unmask Resume Remote Wakeup Detected Interrupt + * @var HSUSBD_T::GRXSTSR + * Offset: 0x1C Receive Status Debug Read Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[3:0] |EPNum |Endpoint Number (EPNum) + * | | |Indicates the endpoint number to which the current received packet belongs. + * |[14:4] |BCnt |Byte Count (BCnt) + * | | |indicates the byte count of the received data packet. + * |[16:15] |DPID |Data PID + * | | |I (DPID) indicates the Data PID of the received OUT data packet + * | | |2'b00: DATA0 + * | | |2'b10: DATA1 + * | | |2'b01: DATA2 + * | | |2'b11: MDATA + * | | |Reset: 2'h0 + * | | |Values: + * | | |0x0 (DATA0): DATA0 + * | | |0x2 (DATA1): DATA1 + * | | |0x1 (DATA2): DATA2 + * | | |0x3 (MDATA): MDATA + * |[20:17] |PktSts |Packet Status + * | | |I(PktSts) indicates the status of the received packet + * | | |4'b0001: Global OUT NAK (triggers an interrupt) + * | | |4'b0010: OUT data packet received + * | | |4'b0011: OUT transfer completed (triggers an interrupt) + * | | |4'b0100: SETUP transaction completed (triggers an interrupt) + * | | |4'b0110: SETUP data packet received + * | | |Others: Reserved + * | | |Reset:4'h0 + * | | |Values: + * | | |0x1 (OUTNAK): Global OUT NAK (triggers an interrupt) + * | | |0x2 (INOUTDPRX): OUT data packet received + * | | |0x3 (INOUTTRCOM): IN or OUT transfer completed (triggers an interrupt) + * | | |0x4 (DSETUPCOM): SETUP transaction completed (triggers an interrupt) + * | | |0x6 (DSETUPRX): SETUP data packet received + * |[24:21] |FN |Frame Number + * | | |(FN) + * | | |This is the least significant 4 bits of the (micro)Frame number in which the packet is received on the USB + * | | |This field is supported only when isochronous OUT endpoints are supported. + * @var HSUSBD_T::GRXSTSP + * Offset: 0x20 Receive Status Read/Pop Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[3:0] |EPNum |Endpoint Number (EPNum) + * | | |Indicates the endpoint number to which the current received packet belongs. + * | | |Values: + * | | |0x0 (CHEP0): Channel or EndPoint 0 + * | | |0x1 (CHEP1): Channel or EndPoint 1 + * | | |0x2 (CHEP2): Channel or EndPoint 2 + * | | |0x3 (CHEP3): Channel or EndPoint 3 + * | | |0x4 (CHEP4): Channel or EndPoint 4 + * | | |0x5 (CHEP5): Channel or EndPoint 5 + * | | |0x6 (CHEP6): Channel or EndPoint 6 + * | | |0x7 (CHEP7): Channel or EndPoint 7 + * | | |0x8 (CHEP8): Channel or EndPoint 8 + * |[14:4] |BCnt |Byte Count + * | | |(BCnt) + * | | |indicates the byte count of the received data packet. + * |[16:15] |DPID |Data PID (DPID) + * | | |iIndicates the Data PID of the received OUT data packet + * | | |2'b00: DATA0 + * | | |2'b10: DATA1 + * | | |2'b01: DATA2 + * | | |2'b11: MDATA + * | | |Reset: 2'h0 + * | | |Values: + * | | |0x0 (DATA0): DATA0 + * | | |0x2 (DATA1): DATA1 + * | | |0x1 (DATA2): DATA2 + * | | |0x3 (MDATA): MDATA + * |[20:17] |PktSts |Packet Status (PktSts) + * | | |iIndicates the status of the received packet + * | | |4'b0001: Global OUT NAK (triggers an interrupt) + * | | |4'b0010: OUT data packet received + * | | |4'b0011: OUT transfer completed (triggers an interrupt) + * | | |4'b0100: SETUP transaction completed (triggers an interrupt) + * | | |4'b0110: SETUP data packet received + * | | |Others: Reserved + * | | |Reset:4'h0 + * | | |Values: + * | | |0x1 (OUTNAK): Global OUT NAK (triggers an interrupt) + * | | |0x2 (INOUTDPRX): OUT data packet received + * | | |0x3 (INOUTTRCOM): IN or OUT transfer completed (triggers an interrupt) + * | | |0x4 (DSETUPCOM): SETUP transaction completed (triggers an interrupt) + * |[24:21] |FN |Frame Number (FN) + * | | |This is the least significant 4 bits of the (micro)Frame number in which the packet is received on the USB + * | | |This field is supported only when isochronous OUT endpoints are supported. + * @var HSUSBD_T::GRXFSIZ + * Offset: 0x24 Receive FIFO Size Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[8:0] |RxFDep |RxFIFO Depth (RxFDep) + * | | |This value is in terms of 32-bit words. + * | | |Minimum value is 16 + * | | |Maximum value is 32,768 + * | | |The power-on reset value of this register is specified as the Largest Rx Data FIFO Depth. + * | | |You can write a new value in this field. Programmed values must not exceed the power-on value. + * @var HSUSBD_T::GNPTXFSIZ + * Offset: 0x28 Non-periodic Transmit FIFO Size Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[8:0] |INEPTxF0StAddr|IN Endpoint FIFO0 Transmit RAM Start Address(INEPTxF0StAddr) + * | | |This field contains the memory start address for IN Endpoint Transmit FIFO# 0. + * | | |Programmed values must not exceed the power-on value. + * |[21:16] |INEPTxF0Dep|IN Endpoint TxFIFO 0 Depth (INEPTxF0Dep) + * | | |This value is in terms of 32-bit words. + * | | |Minimum value is 16 + * | | |Maximum value is 32,768 + * | | |The application can write a new value in this field + * | | |The power-on reset value of this field is specified as Largest IN Endpoint FIFO 0 Depth. + * @var HSUSBD_T::GLPMCFG + * Offset: 0x54 LPM Config Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[0] |LPMCap |LPM-Capable (LPMCap) + * | | |The application uses this bit to control the controller LPM capabilities + * | | |If the core operates as a non-LPM-capable device, it cannot respond to any LPM transactions + * | | |If GLPMCFG.LPMCap is 1'b0, the software must not set any of the remaining fields in the GLPMCFG register and these fields should hold their Reset values. + * | | |1'b0: LPM capability is not enabled. + * | | |1'b1: LPM capability is enabled. + * | | |Values: + * | | |0x0 (DISABLED): LPM capability is not enabled + * | | |0x1 (ENABLED): LPM capability is enabled + * |[1] |AppL1Res |LPM response programmed by application (AppL1Res) + * | | |Handshake response to LPM token pre-programmed by device application software + * | | |The response depends on GLPMCFG.LPMCap + * | | |If GLPMCFG.LPMCap is 1'b0, the core operates as a non-LPM-capable Device and does not respond to any LPM transactions + * | | |If GLPMCFG.LPMCap is 1'b1, the core responds as follows: + * | | |1: ACK + * | | |Even though an ACK is pre-programmed, the core responds with an ACK only on a successful LPM transaction + * | | |The LPM transaction is successful if: + * | | |There are no PID/CRC5 errors in both the EXT token and the LPM token (else ERROR) + * | | |A valid bLinkState = 0001B (L1) is received in the LPM transaction (else STALL). + * | | |No data is pending in the Transmit queue (else NYET) + * | | |0: NYET + * | | |The pre-programmed software bit is overridden for response to LPM token when: + * | | |The received bLinkState is not L1 (STALL response) + * | | |An error is detected in either of the LPM token packets due to corruption (ERROR response). + * | | |Values: + * | | |0x0 (NYET_RESP): The core responds with a NYET when an error is detected in either of the LPM token packets due to corruption + * | | |0x1 (ACK_RESP): The core responds with an ACK only on a successful LPM transaction + * |[5:2] |HIRD |Host-Initiated Resume Duration (HIRD) (Read only) + * | | |EnBESL = 1'b0. + * | | |Host Initiated Resume Duration + * | | |This field is read only and is updated with the Received LPM Token HIRD bmAttribute when an ACK/NYET/STALL response is sent to an LPM transaction + * | | |If HIRD[3:0], + * | | |4'b0000, THIRD(us) = 50. + * | | |4'b0001, THIRD(us) = 125. + * | | |4'b0010, THIRD(us) = 200. + * | | |4'b0011, THIRD(us) = 275. + * | | |4'b0100, THIRD(us) = 350. + * | | |4'b0101, THIRD(us) = 425. + * | | |4'b0110, THIRD(us) = 500. + * | | |4'b0111, THIRD(us) = 575. + * | | |4'b1000, THIRD(us) = 650. + * | | |4'b1001, THIRD(us) = 725. + * | | |4'b1010, THIRD(us) = 800. + * | | |4'b1011, THIRD(us) = 875. + * | | |4'b1100, THIRD(us) = 950. + * | | |4'b1101, THIRD(us) = 1025. + * | | |4'b1110, THIRD(us) = 1100. + * | | |4'b1111, THIRD(us) = 1175. + * | | |EnBESL = 1'b1. + * | | |Best Effort Service Latency (BESL) + * | | |This field is updated with the Received LPM Token BESL bmAttribute when an ACK/NYET/STALL response is sent to an LPM transaction + * | | |If BESL[3:0], + * | | |4'b0000, TBESL(us) = 125. + * | | |4'b0001, TBESL(us) = 150. + * | | |4'b0010, TBESL(us) = 200. + * | | |4'b0011, TBESL(us) = 300. + * | | |4'b0100, TBESL(us) = 400. + * | | |4'b0101, TBESL(us) = 500. + * | | |4'b0110, TBESL(us) = 1000. + * | | |4'b0111, TBESL(us) = 2000. + * | | |4'b1000, TBESL(us) = 3000. + * | | |4'b1001, TBESL(us) = 4000. + * | | |4'b1010, TBESL(us) = 5000. + * | | |4'b1011, TBESL(us) = 6000. + * | | |4'b1100, TBESL(us) = 7000. + * | | |4'b1101, TBESL(us) = 8000. + * | | |4'b1110, TBESL(us) = 9000. + * | | |4'b1111, TBESL(us) = 10000. + * |[6] |bRemoteWake|RemoteWakeEnable (bRemoteWake)(Read only) + * | | |This field is read only + * | | |It is updated with the Received LPM Token bRemoteWake bmAttribute when an ACK/NYET/STALL response is sent to an LPM transaction. + * | | |Values: + * | | |0x0 (DISABLED): Remote Wakeup is disabled + * | | |0x1 (ENABLED): In device mode, this field takes the value of remote wake up + * |[7] |EnblSlpM |Enable utmi_sleep_n (EnblSlpM) + * | | |The application uses this bit to control utmi_sleep_n assertion to the PHY in the L1 state. + * | | |1'b0: utmi_sleep_n assertion from the core is not transferred to the external PHY. + * | | |1'b1: utmi_sleep_n assertion from the core is transferred to the external PHY when utmi_l1_suspend_n cannot be asserted. + * | | |Values: + * | | |0x0 (DISABLED): utmi_sleep_n assertion from the core is not transferred to the external PHY + * | | |0x1 (ENABLED): utmi_sleep_n assertion from the core is transferred to the external PHY when utmi_l1_suspend_n cannot be asserted + * |[12:8] |HIRD_Thres|BESL/HIRD Threshold (HIRD_Thres) + * | | |EnBESL = 1'b0: The core puts the PHY into deep low power mode in L1 (by core asserting L1SuspendM) when HIRD value is greater than or equal to the value defined in this field HIRD_Thres[3:0] and HIRD_Thres[4] is set to 1b1. + * | | |EnBESL = 1'b1: The core puts the PHY into deep low power mode in L1 (by core asserting L1SuspendM) when BESL value is greater than or equal to the value defined in this field BESL_Thres[3:0] and BESL_Thres [4] is set to 1'b1. + * | | |DCTL.DeepSleepBESLReject = 1'b1: In device initiated resume, the core expects the Host to resume service to the device within the BESL value corresponding to L1 exit time specified in HIRD_Thres[3:0] + * | | |The Device sends a NYET response when the received HIRD in LPM token is greater than HIRD threshold + * |[14:13] |CoreL1Res |LPM Response (CoreL1Res) (Read only) + * | | |The response of the core to LPM transaction received is reflected in these two bits. + * | | |Values: + * | | |0x0 (LPMRESP1): ERROR : No handshake response + * | | |0x1 (LPMRESP2): STALL response + * | | |0x2 (LPMRESP3): NYET response + * | | |0x3 (LPMRESP4): ACK response + * |[15] |SlpSts |Port Sleep Status (SlpSts) (Read only) + * | | |This bit is set as long as a Sleep condition is present on the USB bus. + * | | |The core enters the Sleep state when an ACK response is sent to an LPM transaction and the TL1TokenRetry timer has expired + * | | |To stop the PHY clock, the application must set the Port Clock Stop bit, which asserts the PHY Suspend input signal + * | | |The application must rely on SlpSts and not ACK in CoreL1Res to confirm transition into sleep. + * | | |The core comes out of sleep: + * | | |When there is any activity on the USB line_state + * | | |When the application writes to the Remote Wakeup Signaling bit in the Device Control register (DCTL.RmtWkUpSig) or when the application resets or soft-disconnects the device. + * | | |Values: + * | | |0x0 (CORE_NOT_IN_L1): In Device mode, this bit indicates core is not in L1 + * | | |0x1 (CORE_IN_L1): In Device mode, the core enters the Sleep state when an ACK response is sent to an LPM transaction + * |[16] |L1ResumeOK|Sleep State Resume OK (L1ResumeOK)(Read only) + * | | |Indicates that the application or host can start resume from Sleep state + * | | |This bit is valid in LPM sleep (L1) state + * | | |It is set in sleep mode after a delay of 50 micro sec (TL1Residency) + * | | |The bit is reset when SlpSts is 0. + * | | |1'b0: The application/core cannot start resume from Sleep state. + * | | |1'b1: The application/core can start resume from Sleep state. + * | | |Values: + * | | |0x0 (NOTOK): The application/core cannot start Resume from Sleep state + * | | |0x1 (OK): The application/core can start Resume from Sleep state + * |[23:20] |LPM_Accept_Ctrl|Device Mode: LPM Accept Control (LPM_Accept_Ctrl) + * | | |LPM_Accept_Ctrl[0]: The application can use this bit to accept an LPM token even if data is present in the Interrupt endpoint TxFIFO. + * | | |1'b0: Reject (NYET) LPM token when data is present in the TxFIFO for Interrupt endpoints. + * | | |1'b1: Accept(ACK) LPM token when data is present in the TxFIFO for Interrupt endpoints. + * | | |Note: This bit is applicable only for Dedicated TxFIFO configurations (OTG_EN_DED_TX_FIFO=1). + * | | |LPM_Accept_Ctrl[1]: The application can use this bit to reject an LPM token (NYET) between multiple stages of a single control transfer. + * | | |1'b0: Accept(ACK) LPM token during Setup, Data, and Status stage of a control transfer. + * | | |1'b1: Reject(NYET) LPM token during Setup, Data, and Status stage of a control transfer. + * | | |LPM_Accept_Ctrl[2]: The application can use this bit to accept an LPM token even if data is present in the ISOC endpoint TxFIFO. + * | | |1'b0: Reject (NYET) LPM token when data is present in the TxFIFO for ISOC endpoints. + * | | |1'b1: Accept(ACK) LPM token when data is present in the TxFIFO for ISOC endpoints. + * | | |Note: This bit is applicable only for Dedicated TxFIFO configurations (OTG_EN_DED_TX_FIFO=1). + * | | |LPM_Accept_Ctrl[3]: The application can use this bit to accept an LPM token even if data is present in the BULK endpoint TxFIFO. + * | | |1'b0: Reject (NYET) LPM token, when data is present in the TxFIFO for Bulk endpoints. + * | | |1'b1: Accept(ACK) LPM token, when data is present in the TxFIFO for Bulk endpoints. + * | | |Note: This bit is applicable only for Dedicated TxFIFO configurations (OTG_EN_DED_TX_FIFO=1). + * |[28] |LPM_EnBESL|LPM Enable BESL (LPM_EnBESL) + * | | |This bit enables the BESL feature as defined in LPM Errata + * | | |1'b0: The core works as per USB 2.0 Link Power Management Addendum Engineering Change Notice to the USB 2.0 specification as of July 16, 2007 + * | | |1'b1: The core works as per the LPM Errata + * | | |Values: + * | | |0x0 (DISABLED): BESL is disabled + * | | |0x1 (ENABLED): BESL is enabled as defined in LPM Errata + * @var HSUSBD_T::GDFIFOCFG + * Offset: 0x5C Global DFIFO Configuration Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[15:0] |GDFIFOCfg |GDFIFOCfg + * | | |This field is for dynamic programming of the DFIFO Size + * | | |This value takes effect only when the application programs a non zero value to this register + * | | |The value programmed must conform to the guidelines described in 'FIFO RAM Allocation' + * | | |The core does not have any corrective logic if the FIFO sizes are programmed incorrectly. + * | | |Value After Reset: 0xc00 + * |[31:16] |EPInfoBaseAddr|EPInfoBaseAddr + * | | |This field provides the start address of the EP info controller. + * | | |Value After Reset: 0xbb8 + * @var HSUSBD_T::GREFCLK + * Offset: 0x64 ref_clk Control Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[9:0] |SOF_CNT_WKUP_ALERT|This bit indicates the number of SOF's after which the controller should generate an interrupt if the device had been in L1 state until that period + * | | |The interrupt is used by software to initiate remote wakeup in the controller in order to sync to the uF number in the host + * |[14] |RefclkMode|This bit is used to enable or disable ref_clk mode of operation + * | | |Note: + * | | |The default value of this field is 'd0. + * | | |When this field is disabled, DCTL.ServInt cannot be set to 1. + * | | |Values: + * | | |0x1 (ENABLE): Controller uses ref_clk to run internal micro-frame timers + * | | |0x0 (DISABLE): Controller uses phy_clk to run internal micro-frame timers + * |[31:15] |REFCLKPER |This bit indicates the period of ref_clk in terms of pico seconds + * | | |Note: + * | | |The default value of this field is 'd0. + * | | |The period of ref_clk should be an integer multiple of 125us. + * | | |The minimum frequency supported is 12 MHz. + * | | |Other supported frequencies are 16, 17, 19.2, 20, 24, 30, and 40 MHz. + * @var HSUSBD_T::GINTMSK2 + * Offset: 0x68 Interrupt Mask Register 2 + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[0] |WkUpAlertIntMsk|Mode: Device + * | | |Remote WakeUp Alert Interrupt Mask + * | | |This interrupt is used to alert the application to initiate Remote WakeUp sequence. + * | | |Values: + * | | |0x0 (MASK): Mask Remote WakeUp Alert Interrupt + * | | |0x1 (NOMASK): Unmask Remote WakeUp Alert Interrupt + * @var HSUSBD_T::GINTSTS2 + * Offset: 0x6C Interrupt Register 2 + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[0] |WkUpAlertInt|Mode: Device + * | | |Remote WakeUp Alert Interrupt Mask + * | | |This interrupt is used to alert the application to initiate Remote WakeUp sequence. + * | | |Values: + * | | |• 0x0 (INACTIVE): Not Active + * | | |• 0x1 (ACTIVE): Remote WakeUp Alert Interrupt detected + * @var HSUSBD_T::DIEPTXF1 + * Offset: 0x104 Device IN Endpoint Transmit FIFO Size Register 1 + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[8:0] |INEPnTxFStAddr|IN Endpoint FIFOn Transmit RAM Start Address (INEPnTxFStAddr) + * | | |This field contains the memory start address for IN endpoint Transmit FIFO + * | | |The power-on reset value of this register is specified as the Largest Rx Data FIFO Depth + * |[24:16] |INEPnTxFDep|IN Endpoint TxFIFO Depth (INEPnTxFDep) + * | | |This value is in terms of 32-bit words. + * | | |Minimum value is 16 + * | | |Maximum value is 32,768 + * | | |The power-on reset value of this register is specified as the Largest IN Endpoint FIFO number Depth. + * | | |Programmed values must not exceed the power-on value. + * @var HSUSBD_T::DIEPTXF2 + * Offset: 0x108 Device IN Endpoint Transmit FIFO Size Register 2 + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[9:0] |INEPnTxFStAddr|IN Endpoint FIFOn Transmit RAM Start Address (INEPnTxFStAddr) + * | | |This field contains the memory start address for IN endpoint Transmit FIFO + * | | |The power-on reset value of this register is specified as the Largest Rx Data FIFO Depth + * |[24:16] |INEPnTxFDep|IN Endpoint TxFIFO Depth (INEPnTxFDep) + * | | |This value is in terms of 32-bit words. + * | | |Minimum value is 16 + * | | |Maximum value is 32,768 + * | | |The power-on reset value of this register is specified as the Largest IN Endpoint FIFO number Depth. + * | | |Programmed values must not exceed the power-on value. + * @var HSUSBD_T::DIEPTXF3 + * Offset: 0x10C Device IN Endpoint Transmit FIFO Size Register 3 + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[9:0] |INEPnTxFStAddr|IN Endpoint FIFOn Transmit RAM Start Address (INEPnTxFStAddr) + * | | |This field contains the memory start address for IN endpoint Transmit FIFO + * | | |The power-on reset value of this register is specified as the Largest Rx Data FIFO Depth. + * | | |Value After Reset: 0x320 + * |[15:10] |_ |Reserved. + * |[24:16] |INEPnTxFDep|IN Endpoint TxFIFO Depth (INEPnTxFDep) + * | | |This value is in terms of 32-bit words. + * | | |Minimum value is 16 + * | | |Maximum value is 32,768 + * | | |The power-on reset value of this register is specified as the Largest IN Endpoint FIFO number Depth. + * | | |Programmed values must not exceed the power-on value. + * @var HSUSBD_T::DIEPTXF4 + * Offset: 0x110 Device IN Endpoint Transmit FIFO Size Register 4 + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[10:0] |INEPnTxFStAddr|IN Endpoint FIFOn Transmit RAM Start Address (INEPnTxFStAddr) + * | | |This field contains the memory start address for IN endpoint Transmit FIFO + * | | |The power-on reset value of this register is specified as the Largest Rx Data FIFO Depth + * |[24:16] |INEPnTxFDep|IN Endpoint TxFIFO Depth (INEPnTxFDep) + * | | |This value is in terms of 32-bit words. + * | | |Minimum value is 16 + * | | |Maximum value is 32,768 + * | | |The power-on reset value of this register is specified as the Largest IN Endpoint FIFO number Depth. + * | | |Programmed values must not exceed the power-on value + * @var HSUSBD_T::DIEPTXF5 + * Offset: 0x114 Device IN Endpoint Transmit FIFO Size Register 5 + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[10:0] |INEPnTxFStAddr|IN Endpoint FIFOn Transmit RAM Start Address (INEPnTxFStAddr) + * | | |This field contains the memory start address for IN endpoint Transmit FIFO + * | | |The power-on reset value of this register is specified as the Largest Rx Data FIFO Depth + * |[24:16] |INEPnTxFDep|IN Endpoint TxFIFO Depth (INEPnTxFDep) + * | | |This value is in terms of 32-bit words. + * | | |Minimum value is 16 + * | | |Maximum value is 32,768 + * | | |The power-on reset value of this register is specified as the Largest IN Endpoint FIFO number Depth. + * | | |Programmed values must not exceed the power-on value. + * @var HSUSBD_T::DIEPTXF6 + * Offset: 0x118 Device IN Endpoint Transmit FIFO Size Register 6 + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[10:0] |INEPnTxFStAddr|IN Endpoint FIFOn Transmit RAM Start Address (INEPnTxFStAddr) + * | | |This field contains the memory start address for IN endpoint Transmit FIFO + * | | |The power-on reset value of this register is specified as the Largest Rx Data FIFO Depth + * |[24:16] |INEPnTxFDep|IN Endpoint TxFIFO Depth (INEPnTxFDep) + * | | |This value is in terms of 32-bit words. + * | | |Minimum value is 16 + * | | |Maximum value is 32,768 + * | | |The power-on reset value of this register is specified as the Largest IN Endpoint FIFO number Depth. + * | | |Programmed values must not exceed the power-on value. + * @var HSUSBD_T::DIEPTXF7 + * Offset: 0x11C Device IN Endpoint Transmit FIFO Size Register 7 + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[10:0] |INEPnTxFStAddr|IN Endpoint FIFOn Transmit RAM Start Address (INEPnTxFStAddr) + * | | |This field contains the memory start address for IN endpoint Transmit FIFO + * | | |The power-on reset value of this register is specified as the Largest Rx Data FIFO Depth + * |[24:16] |INEPnTxFDep|IN Endpoint TxFIFO Depth (INEPnTxFDep) + * | | |This value is in terms of 32-bit words. + * | | |Minimum value is 16 + * | | |Maximum value is 32,768 + * | | |The power-on reset value of this register is specified as the Largest IN Endpoint FIFO number Depth. + * | | |Programmed values must not exceed the power-on value. + * @var HSUSBD_T::DIEPTXF8 + * Offset: 0x120 Device IN Endpoint Transmit FIFO Size Register 8 + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[11:0] |INEPnTxFStAddr|IN Endpoint FIFOn Transmit RAM Start Address (INEPnTxFStAddr) + * | | |This field contains the memory start address for IN endpoint Transmit FIFO + * | | |The power-on reset value of this register is specified as the Largest Rx Data FIFO Depth + * |[24:16] |INEPnTxFDep|IN Endpoint TxFIFO Depth (INEPnTxFDep) + * | | |This value is in terms of 32-bit words. + * | | |Minimum value is 16 + * | | |Maximum value is 32,768 + * | | |The power-on reset value of this register is specified as the Largest IN Endpoint FIFO number Depth. + * | | |Programmed values must not exceed the power-on value. + * @var HSUSBD_T::DCFG + * Offset: 0x800 Device Configuration Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[1:0] |DevSpd |Device Speed (DevSpd) + * | | |Indicates the speed at which the application requires the core to enumerate, or the maximum speed the application can support + * | | |However, the actual bus speed is determined only after the connect sequence is completed, and is based on the speed of the USB host to which the core is connected. + * | | |Values: + * | | |0x0 (USBHS20): High speed USB 2.0 + * | | |0x1 (USBFS20): Full speed USB 2.0 + * | | |0x2 (Reserved0): Reserved + * | | |0x3 (Reserved1): Reserved + * |[2] |NZStsOUTHShk|Non-Zero-Length Status OUT Handshake (NZStsOUTHShk) + * | | |The application can use this field to select the handshake the core sends on receiving a nonzero-length data packet during the OUT transaction of a control transfer's Status stage. + * | | |1'b1: Send a STALL handshake on a nonzero-length status OUT transaction and do not send the received OUT packet to the application. + * | | |1'b0: Send the received OUT packet to the application (zerolength or nonzero-length) and send a handshake based on the NAK and STALL bits for the endpoint in the Device Endpoint Control register. + * | | |Values: + * | | |0x0 (SENDOUT): + * | | |Send the received OUT packet to the application (zero-length or non-zero length) and send a handshake based on NAK and STALL bits for the endpoint in the Devce Endpoint Control Register + * | | |0x1 (SENDSTALL): + * | | |Send a STALL handshake on a nonzero-length status OUT transaction and do not send the received OUT packet to the application + * |[10:4] |DevAddr |Device Address (DevAddr) + * | | |The application must program this field after every SetAddress control command. + * |[12:11] |PerFrInt |Periodic Frame Interval (PerFrInt) + * | | |Indicates the time within a (micro)Frame at which the application must be notified using the End Of Periodic Frame Interrupt + * | | |This can be used to determine If all the isochronous traffic for that (micro)Frame is complete. + * | | |2'b00: 80% of the (micro)Frame interval + * | | |2'b01: 85% of the (micro)Frame interval + * | | |2'b10: 90% of the (micro)Frame interval + * | | |2'b11: 95% of the (micro)Frame interval + * | | |Values: + * | | |0x0 (EOPF80): 80% of the (micro)Frame interval + * | | |0x1 (EOPF85): 85% of the (micro)Frame interval + * | | |0x2 (EOPF90): 90% of the (micro)Frame interval + * | | |0x3 (EOPF95): 95% of the (micro)Frame interval + * |[13] |EnDevOutNak|Enable Device OUT NAK (EnDevOutNak) + * | | |This bit enables setting NAK for Bulk OUT endpoints after the transfer is completed for Device mode Descriptor DMA + * | | |1'b0 : The core does not set NAK after Bulk OUT transfer complete + * | | |1'b1 : The core sets NAK after Bulk OUT transfer complete + * | | |This bit is one time programmable after reset like any other DCFG register bits. + * | | |Values: + * | | |0x0 (DISABLED): + * | | |The core does not set NAK after Bulk OUT transfer complete + * | | |0x1 (ENABLED): The core sets NAK after Bulk OUT transfer complete + * |[14] |XCVRDLY |XCVRDLY + * | | |Enables or disables delay between xcvr_sel and txvalid during device chirp + * | | |Values: + * | | |0x0 (DISABLE): No delay between xcvr_sel and txvalid during Device chirp + * | | |0x1 (ENABLE): Enable delay between xcvr_sel and txvalid during Device chirp + * |[15] |ErraticIntMsk|Erratic Error Interrupt Mask + * | | |Values: + * | | |0x0 (NOMASK): Early suspend interrupt is generated on erratic error + * | | |0x1 (MASK): Mask early suspend interrupt on erratic error + * |[17] |ipgisocSupt|Worst-Case Inter-Packet Gap ISOC OUT Support (ipgisocSupt) + * | | |This bit indicates that the controller supports the worst-case scenario of Rx followed by Rx Inter Packet Gap (IPG) (32 bit times) as per the UTMI Specification for any token following an ISOC OUT token + * | | |Without this support, when any token follows an ISOC OUT token with the worst-case IPG, the controller will not detect the followed token + * | | |The worst-case IPG of the controller without this support depends on the AHB and PHY Clock frequency. + * | | |Values: + * | | |0x0 (DISABLED): Worst-Case Inter-Packet Gap ISOC OUT Support is disabled + * | | |0x1 (ENABLED): Worst-Case Inter-Packet Gap ISOC OUT Support is enabled + * |[23] |DescDMA |Enable Scatter/gather DMA in device mode (DescDMA) + * | | |The application can Set this bit during initialization to enable the Scatter/Gather DMA operation. + * | | |Note: This bit must be modified only once after a reset + * | | |The following combinations are available for programming: + * | | |GAHBCFG.DMAEn=0,DCFG.DescDMA=0 => Invalid. + * | | |GAHBCFG.DMAEn=0,DCFG.DescDMA=1 => Invalid. + * | | |GAHBCFG.DMAEn=1,DCFG.DescDMA=0 => Invalid. + * | | |GAHBCFG.DMAEn=1,DCFG.DescDMA=1 => Scatter/Gather DMA mode. + * | | |Values: + * | | |0x0 (DISABLED): Disable Scatter/Gather DMA + * | | |0x1 (ENABLED): Enable Scatter/Gather DMA + * |[25:24] |PerSchIntvl|Periodic Scheduling Interval (PerSchIntvl) + * | | |PerSchIntvl must be programmed for Scatter/Gather DMA mode. + * | | |This field specifies the amount of time the Internal DMA engine must allocate for fetching periodic IN endpoint data + * | | |Based on the number of periodic endpoints, this value must be specified as 25,50 or 75% of (micro)Frame. + * | | |When any periodic endpoints are active, the internal DMA engine allocates the specified amount of time in fetching periodic IN endpoint data . + * | | |When no periodic endpoints are active, Then the internal DMA engine services non-periodic endpoints, ignoring this field. + * | | |After the specified time within a (micro)Frame, the DMA switches to fetching for non-periodic endpoints. + * | | |2'b00: 25% of (micro)Frame. + * | | |2'b01: 50% of (micro)Frame. + * | | |2'b10: 75% of (micro)Frame. + * | | |2'b11: Reserved. + * | | |Reset: 2'b00 + * | | |Values: + * | | |0x0 (MF25): 25% of (micro)Frame + * | | |0x1 (MF50): 50% of (micro)Frame + * | | |0x2 (MF75): 75% of (micro)Frame + * | | |0x3 (RESERVED): Reserved + * |[31:26] |ResValid |Resume Validation Period (ResValid) + * | | |This field is effective only when DCFG.Ena32 kHzSusp is set + * | | |It controls the resume period when the core resumes from suspend + * | | |The core counts for ResValid number of clock cycles to detect a valid resume when this bit is set + * @var HSUSBD_T::DCTL + * Offset: 0x804 Device Control Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[0] |RmtWkUpSig|Remote Wakeup Signaling (RmtWkUpSig) + * | | |When the application sets this bit, the core initiates remote signaling to wake up the USB host + * | | |The application must Set this bit to instruct the core to exit the Suspend state + * | | |As specified in the USB 2.0 specification, the application must clear this bit 1-15 ms after setting it. + * | | |If LPM is enabled and the core is in the L1 (Sleep) state, when the application sets this bit, the core initiates L1 remote signaling to wake up the USB host + * | | |The application must set this bit to instruct the core to exit the Sleep state + * | | |As specified in the LPM specification, the hardware automatically clears this bit 50 microseconds (TL1DevDrvResume) after being set by the application + * | | |The application must not set this bit when GLPMCFG bRemoteWake from the previous LPM transaction is zero. + * | | |Values: + * | | |0x0 (DISABLEDRMWKUP): Core does not send Remote Wakeup Signaling + * | | |0x1 (ENABLERMWKUP): Core sends Remote Wakeup Signaling + * |[1] |SftDiscon |Soft Disconnect (SftDiscon) + * | | |The application uses this bit to signal the controller to do a soft disconnect + * | | |As long as this bit is set, the host does not see that the device is connected, and the device does not receive signals on the USB + * | | |The core stays in the disconnected state until the application clears this bit. + * | | |1'b0: Normal operation + * | | |When this bit is cleared after a soft disconnect, the core drives the phy_opmode_o signal on the UTMI+ to 2'b00, which generates a device connect event to the USB host + * | | |When the device is reconnected, the USB host restarts device enumeration. + * | | |1'b1: The core drives the phy_opmode_o signal on the UTMI+ to 2'b01, which generates a device disconnect event to the USB host. + * | | |Note: + * | | |This bit can be also used for ULPI/FS Serial interfaces. + * | | |This bit is not impacted by a soft reset. + * | | |Values: + * | | |0x0 (NODISCONNECT): The core drives the phy_opmode_o signal on the UTMI+ to 2'b00, which generates a device connect event to the USB host + * | | |0x1 (DISCONNECT): The core drives the phy_opmode_o signal on the UTMI+ to 2'b01, which generates a device disconnect event to the USB host + * |[2] |GNPINNakSts|Global Non-periodic IN NAK Status (GNPINNakSts) (Read only) + * | | |1'b0: A handshake is sent out based on the data availability in the transmit FIFO. + * | | |1'b1: A NAK handshake is sent out on all non-periodic IN endpoints, irrespective of the data availability in the transmit FIFO. + * | | |Values: + * | | |0x0 (INACTIVE): A handshake is sent out based on the data availability in the transmit FIFO + * | | |0x1 (ACTIVE): A NAK handshake is sent out on all non-periodic IN endpoints, irrespective of the data availability in the transmit FIFO + * |[3] |GOUTNakSts|Global OUT NAK Status (GOUTNakSts) (Read only) + * | | |1'b0: A handshake is sent based on the FIFO Status and the NAK and STALL bit settings. + * | | |1'b1: No data is written to the RxFIFO, irrespective of space availability + * | | |Sends a NAK handshake on all packets, except on SETUP transactions + * | | |All isochronous OUT packets are dropped. + * | | |Values: + * | | |0x0 (INACTIVE): A handshake is sent based on the FIFO Status and the NAK and STALL bit settings. + * | | |0x1 (ACTIVE): No data is written to the RxFIFO, irrespective of space availability + * | | |Sends a NAK handshake on all packets, except on SETUP transactions + * | | |All isochronous OUT packets are dropped + * |[6:4] |TstCtl |Test Control (TstCtl) + * | | |3'b000: Test mode disabled + * | | |3'b001: Test_J mode + * | | |3'b010: Test_K mode + * | | |3'b011: Test_SE0_NAK mode + * | | |3'b100: Test_Packet mode + * | | |3'b101: Test_Force_Enable + * | | |Others: Reserved + * | | |Values: + * | | |0x0 (DISABLED): Test mode disabled + * | | |0x1 (TESTJ): Test_J mode + * | | |0x2 (TESTK): Test_K mode + * | | |0x3 (TESTSN): Test_SE0_NAK mode + * | | |0x4 (TESTPM): Test_Packet mode + * | | |0x5 (TESTFE): Test_force_Enable + * |[7] |SGNPInNak |Set Global Non-periodic IN NAK (SGNPInNak) + * | | |A write to this field sets the Global Non-periodic IN NAK.The application uses this bit to send a NAK handshake on all non-periodic IN endpoints + * | | |The application must Set this bit only after making sure that the Global IN NAK Effective bit in the Core Interrupt Register (GINTSTS.GINNakEff) is cleared + * | | |Values: + * | | |0x0 (DISABLE): Disable Global Non-periodic IN NAK + * | | |0x1 (ENABLE): Set Global Non-periodic IN NAK + * |[8] |CGNPInNak |Clear Global Non-periodic IN NAK (CGNPInNak) + * | | |A write to this field clears the Global Non-periodic IN NAK. + * | | |Values: + * | | |0x0 (DISABLE): Disable Global Non-periodic IN NAK + * | | |0x1 (ENABLE): Clear Global Non-periodic IN NAK + * |[9] |SGOUTNak |Set Global OUT NAK (SGOUTNak) + * | | |A write to this field sets the Global OUT NAK + * | | |The application uses this bit to send a NAK handshake on all OUT endpoints + * | | |The application must set the this bit only after making sure that the Global OUT NAK Effective bit in the Core Interrupt Register (GINTSTS.GOUTNakEff) is cleared. + * | | |Values: + * | | |0x0 (DISABLED): Disable Global OUT NAK + * | | |0x1 (ENABLED): Set Global OUT NAK + * |[10] |CGOUTNak |Clear Global OUT NAK (CGOUTNak) + * | | |A write to this field clears the Global OUT NAK. + * | | |Values: + * | | |0x0 (DISABLED): Disable Clear Global OUT NAK + * | | |0x1 (ENABLED): Clear Global OUT NAK + * |[11] |PWROnPrgDone|Power-On Programming Done (PWROnPrgDone) + * | | |The application uses this bit to indicate that register programming is completed after a wake-up from Power-down mode. + * | | |Values: + * | | |0x0 (NOTDONE): Power-On Programming not done + * | | |0x1 (DONE): Power-On Programming Done + * |[14:13] |GMC |Global Multi Count (GMC) + * | | |GMC must be programmed only once after initialization + * | | |Applicable only for Scatter/Gather DMA mode + * | | |This indicates the number of packets to be serviced for that end point before moving to the next end point + * | | |It is only for non-periodic endpoints. + * | | |2'b00: Invalid. + * | | |2'b01: 1 packet. + * | | |2'b10: 2 packets. + * | | |2'b11: 3 packets. + * | | |Values: + * | | |0x0 (NOTVALID): Invalid + * | | |0x1 (ONEPACKET): 1 packet + * | | |0x2 (TWOPACKET): 2 packets + * | | |0x3 (THREEPACKET): 3 packets + * |[15] |IgnrFrmNum|Ignore Frame Number Feature for Isochronous Endpoints (IgnrFrmNum) + * | | |Note: Do not program IgnrFrmNum bit to 1'b1 when the core is operating in threshold mode. + * | | |Note: When Scatter/Gather DMA mode is enabled this feature is not applicable to High Speed, High bandwidth transfers. + * | | |When this bit is enabled, there must be only one packet per descriptor. + * | | |0: The core transmits the packets only in the frame number in which they are intended to be transmitted. + * | | |1: The core ignores the frame number, sending packets immediately as the packets are ready. + * | | |In Scatter/Gather DMA mode, if this bit is enabled, the packets are not flushed when a ISOC IN token is received for an elapsed frame. + * | | |Values: + * | | |0x0 (DISABLED): The core transmits the packets only in the frame number in which they are intended to be transmitted. + * | | |0x1 (ENABLED): The core ignores the frame number, sending packets immediately as the packets are ready + * |[16] |NakOnBble |NAK on Babble Error (NakOnBble) + * | | |Set NAK automatically on babble (NakOnBble) + * | | |The core sets NAK automatically for the endpoint on which babble is received. + * | | |Values: + * | | |0x0 (DISABLED): Disable NAK on Babble Error + * | | |0x1 (ENABLED): NAK on Babble Error + * |[17] |EnContOnBNA|Enable Continue on BNA (EnContOnBNA) + * | | |This bit enables the core to continue on BNA for Bulk OUT endpoints + * | | |With this feature enabled, when a Bulk OUT or INTR OUT endpoint receives a BNA interrupt the core starts processing the descriptor that caused the BNA interrupt after the endpoint re-enables the endpoint. + * | | |1'b0: After receiving BNA interrupt,the core disables the endpoint + * | | |When the endpoint is re-enabled by the application, the core starts processing from the DOEPDMA descriptor. + * | | |1'b1: After receiving BNA interrupt, the core disables the endpoint + * | | |When the endpoint is re-enabled by the application, the core starts processing from the descriptor that received the BNA interrupt. + * | | |It is a one-time programmable after reset bit like any other DCTL register bits. + * | | |Values: + * | | |0x0 (DISABLED): Core disables the endpoint after receiving BNA interrupt + * | | |When application re-enables the endpoint, core starts processing from the DOEPDMA descriptor + * | | |0x1 (ENABLED): Core disables the endpoint after receiving BNA interrupt + * | | |When application re-enables the endpoint, core starts processing from the descriptor that received the BNA interrupt + * |[18] |DeepSleepBESLReject|DeepSleepBESLReject + * | | |1: Deep Sleep BESL Reject feature is enabled + * | | |0: Deep Sleep BESL Reject feature is disabled + * | | |Core rejects LPM request with HIRD value greater than HIRD threshold programmed + * | | |NYET response is sent for LPM tokens with HIRD value greater than HIRD threshold + * | | |By default, the Deep Sleep BESL Reject feature is disabled. + * | | |Values: + * | | |0x0 (DISABLED): Deep Sleep BESL Reject feature is disabled + * | | |0x1 (ENABLED): Deep Sleep BESL Reject feature is enabled + * |[19] |ServInt |Service Interval based scheduling for Isochronous IN Endpoints + * | | |Note: This bit is applicable only in device mode and when Scatter/Gather DMA mode is used + * | | |This feature should not be enabled along with DCTL.IgnrFrmNum. + * | | |When this bit is enabled, the frame number field in the ISOC IN descriptor structure is interpreted as the last frame of the service interval + * | | |In Scatter/Gather DMA mode, if this bit is enabled, the pending packets are flushed by the controller at the last frame of the service interval. + * | | |Values: + * | | |0x0 (DISABLED): The controller behavior depends on DCTL.IgnrFrmNum field. + * | | |0x1 (ENABLED): The controller can transmit the packets in any frame of the service interval. + * @var HSUSBD_T::DSTS + * Offset: 0x808 Device Status Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[0] |SuspSts |Suspend Status (SuspSts) + * | | |In Device mode, this bit is set as long as a Suspend condition is detected on the USB + * | | |The core enters the Suspend state when there is no activity on the phy_line_state_i signal for an extended period of time + * | | |The core comes out of the suspend under the following conditions : + * | | |If there is any activity on the phy_line_state_i signal, or + * | | |If the application writes to the Remote Wakeup Signaling bit in the Device Control register (DCTL.RmtWkUpSig). + * | | |When the core comes out of the suspend, this bit is set to 1'b0. + * | | |Values: + * | | |0x0 (INACTIVE): No suspend state + * | | |0x1 (ACTIVE): Suspend state + * |[2:1] |EnumSpd |Enumerated Speed (EnumSpd) + * | | |Indicates the speed at which the controller has come up after speed detection through a connect or reset sequence. + * | | |2'b00: High speed + * | | |2'b01: Full speed + * | | |Values: + * | | |0x0 (HS3060): High speed + * | | |0x1 (FS3060): Full speed + * | | |0x2 (Reserved0): Reserved + * | | |0x3 (Reserved1): Reserved + * |[3] |ErrticErr |Erratic Error (ErrticErr) + * | | |The core sets this bit to report any erratic errors (phy_rxvalid_i/phy_rxvldh_i or phy_rxactive_i is asserted for at least 2 ms, due to PHY error) + * | | |Due to erratic errors, the core goes into Suspended state and an interrupt is generated to the application with Early Suspend bit of the Core Interrupt register (GINTSTS.ErlySusp) + * | | |If the early suspend is asserted due to an erratic error, the application can only perform a soft disconnect recover. + * | | |Values: + * | | |0x0 (INACTIVE): No Erratic Error + * | | |0x1 (ACTIVE): Erratic Error + * |[21:8] |SOFFN |Frame or Microframe Number of the Received SOF (SOFFN) + * | | |When the core is operating at high speed, this field contains a microframe number + * | | |When the core is operating at full or low speed, this field contains a Frame number. + * | | |Note: This register may return a non-zero value if read immediately after power-on reset + * | | |In case the register bit reads non-zero immediately after power-on reset, it does not indicate that SOF has been received from the host + * | | |The read value of this interrupt is valid only after a valid connection between host and device is established. + * |[23:22] |DevLnSts |Device Line Status (DevLnSts) + * | | |Indicates the current logic level USB data lines + * | | |DevLnSts[1]: Logic level of D+ + * | | |DevLnSts[0]: Logic level of D- + * @var HSUSBD_T::DIEPMSK + * Offset: 0x810 Device IN Endpoint Common Interrupt Mask Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[0] |XferComplMsk|Transfer Completed Interrupt Mask (XferComplMsk) + * | | |Values: + * | | |0x0 (MASK): Mask Transfer Completed Interrupt + * | | |0x1 (NOMASK): No Transfer Completed Interrupt Mask + * |[1] |EPDisbldMsk|Endpoint Disabled Interrupt Mask (EPDisbldMsk) + * | | |Values: + * | | |0x0 (MASK): Mask Endpoint Disabled Interrupt + * | | |0x1 (NOMASK): No Endpoint Disabled Interrupt Mask + * |[2] |AHBErrMsk |AHB Error Mask (AHBErrMsk) + * | | |Values: + * | | |0x0 (MASK): Mask AHB Error Interrupt + * | | |0x1 (NOMASK): No AHB Error Interrupt Mask + * |[3] |TimeOUTMsk|Timeout Condition Mask (TimeOUTMsk) (Non-isochronous endpoints) + * | | |Values: + * | | |0x0 (MASK): Mask Timeout Condition Interrupt + * | | |0x1 (NOMASK): No Timeout Condition Interrupt Mask + * |[4] |INTknTXFEmpMsk|IN Token Received When TxFIFO Empty Mask (INTknTXFEmpMsk) + * | | |Values: + * | | |0x0 (MASK): Mask IN Token Received When TxFIFO Empty Interrupt + * | | |0x1 (NOMASK): + * | | |No IN Token Received When TxFIFO Empty Interrupt + * |[5] |INTknEPMisMsk|IN Token received with EP Mismatch Mask (INTknEPMisMsk) + * | | |Values: + * | | |0x0 (MASK): Mask IN Token received with EP Mismatch Interrupt + * | | |0x1 (NOMASK): + * | | |No Mask IN Token received with EP Mismatch Interrupt + * |[6] |INEPNakEffMsk|IN Endpoint NAK Effective Mask (INEPNakEffMsk) + * | | |Values: + * | | |0x0 (MASK): Mask IN Endpoint NAK Effective Interrupt + * | | |0x1 (NOMASK): No IN Endpoint NAK Effective Interrupt Mask + * |[8] |TxfifoUndrnMsk|Fifo Underrun Mask (TxfifoUndrnMsk) + * | | |Values: + * | | |0x0 (MASK): Mask Fifo Underrun Interrupt + * | | |0x1 (NOMASK): No Fifo Underrun Interrupt Mask + * |[9] |BNAInIntrMsk|BNA interrupt Mask (BNAInIntrMsk) + * | | |Values: + * | | |0x0 (MASK): Mask BNA Interrupt + * | | |0x1 (NOMASK): No BNA Interrupt Mask + * |[13] |NAKMsk |NAK interrupt Mask (NAKMsk) + * | | |Values: + * | | |0x0 (MASK): Mask NAK Interrupt + * | | |0x1 (NOMASK): No Mask NAK Interrupt + * @var HSUSBD_T::DOEPMSK + * Offset: 0x814 Device OUT Endpoint Common Interrupt Mask Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[0] |XferComplMsk|Transfer Completed Interrupt Mask (XferComplMsk) + * | | |Values: + * | | |0x0 (MASK): Mask Transfer Completed Interrupt + * | | |0x1 (NOMASK): No Transfer Completed Interrupt Mask + * |[1] |EPDisbldMsk|Endpoint Disabled Interrupt Mask (EPDisbldMsk) + * | | |Values: + * | | |0x0 (MASK): Mask Endpoint Disabled Interrupt + * | | |0x1 (NOMASK): No Endpoint Disabled Interrupt Mask + * |[2] |AHBErrMsk |AHB Error (AHBErrMsk) + * | | |Values: + * | | |0x0 (MASK): Mask AHB Error Interrupt + * | | |0x1 (NOMASK): No AHB Error Interrupt Mask + * |[3] |SetUPMsk |SETUP Phase Done Mask (SetUPMsk) + * | | |Applies to control endpoints only. + * | | |Values: + * | | |0x0 (MASK): Mask SETUP Phase Done Interrupt + * | | |0x1 (NOMASK): No SETUP Phase Done Interrupt Mask + * |[4] |OUTTknEPdisMsk|OUT Token Received when Endpoint Disabled Mask (OUTTknEPdisMsk) + * | | |Applies to control OUT endpoints only. + * | | |Values: + * | | |0x0 (MASK): + * | | |Mask OUT Token Received when Endpoint Disabled Interrupt + * | | |0x1 (NOMASK): + * | | |No OUT Token Received when Endpoint Disabled Interrupt Mask + * |[5] |StsPhseRcvdMsk|Status Phase Received Mask (StsPhseRcvdMsk) + * | | |Applies to control OUT endpoints only. + * | | |Values: + * | | |0x0 (MASK): Status Phase Received Mask + * | | |0x1 (NOMASK): No Status Phase Received Mask + * |[6] |Back2BackSETup|Back-to-Back SETUP Packets Received Mask (Back2BackSETup) + * | | |Applies to control OUT endpoints only. + * | | |Values: + * | | |0x0 (MASK): Mask Back-to-Back SETUP Packets Received Interrupt + * | | |0x1 (NOMASK): + * | | |No Back-to-Back SETUP Packets Received Interrupt Mask + * |[8] |OutPktErrMsk|OUT Packet Error Mask (OutPktErrMsk) + * | | |Values: + * | | |0x0 (MASK): Mask OUT Packet Error Interrupt + * | | |0x1 (NOMASK): No OUT Packet Error Interrupt Mask + * |[9] |BnaOutIntrMsk|BNA interrupt Mask (BnaOutIntrMsk) + * | | |Values: + * | | |0x0 (MASK): Mask BNA Interrupt + * | | |0x1 (NOMASK): No BNA Interrupt Mask + * |[12] |BbleErrMsk|Babble Error interrupt Mask (BbleErrMsk) + * | | |Values: + * | | |0x0 (MASK): Mask Babble Error Interrupt + * | | |0x1 (NOMASK): No Babble Error Interrupt Mask + * |[13] |NAKMsk |NAK interrupt Mask (NAKMsk) + * | | |Values: + * | | |0x0 (MASK): Mask NAK Interrupt + * | | |0x1 (NOMASK): No NAK Interrupt Mask + * |[14] |NYETMsk |NYET interrupt Mask (NYETMsk) + * | | |Values: + * | | |0x0 (MASK): Mask NYET Interrupt + * | | |0x1 (NOMASK): No NYET Interrupt Mask + * @var HSUSBD_T::DAINT + * Offset: 0x818 Device All Endpoints Interrupt Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[0] |InEpInt0 |IN Endpoint 0 Interrupt Bit + * | | |Values: + * | | |0x0 (INACTIVE): No Interrupt + * | | |0x1 (ACTIVE): IN Endpoint 0 Interrupt + * |[1] |InEpInt1 |IN Endpoint 1 Interrupt Bit + * |[2] |InEpInt2 |IN Endpoint 2 Interrupt Bit + * |[3] |InEpInt3 |IN Endpoint 3 Interrupt Bit + * |[4] |InEpInt4 |IN Endpoint 4 Interrupt Bit + * |[5] |InEpInt5 |IN Endpoint 5 Interrupt Bit + * |[6] |InEpInt6 |IN Endpoint 6 Interrupt Bit + * |[7] |InEpInt7 |IN Endpoint 7 Interrupt Bit + * |[8] |InEpInt8 |IN Endpoint 8 Interrupt Bit + * |[16] |OutEPInt0 |OUT Endpoint 0 Interrupt Bit + * | | |Values: + * | | |0x0 (INACTIVE): No Interrupt + * | | |0x1 (ACTIVE): OUT Endpoint 0 Interrupt + * |[17] |OutEPInt1 |OUT Endpoint 1 Interrupt Bit + * |[18] |OutEPInt2 |OUT Endpoint 2 Interrupt Bit + * |[19] |OutEPInt3 |OUT Endpoint 3 Interrupt Bit + * |[20] |OutEPInt4 |OUT Endpoint 4 Interrupt Bit + * |[21] |OutEPInt5 |OUT Endpoint 5 Interrupt Bit + * |[22] |OutEPInt6 |OUT Endpoint 6 Interrupt Bit + * |[23] |OutEPInt7 |OUT Endpoint 7 Interrupt Bit + * |[24] |OutEPInt8 |OUT Endpoint 8 Interrupt Bit + * @var HSUSBD_T::DAINTMSK + * Offset: 0x81C Device All Endpoints Interrupt Mask Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[0] |InEpMsk0 |IN Endpoint 0 Interrupt mask Bit + * | | |Values: + * | | |0x0 (MASK): IN Endpoint 0 Interrupt mask + * | | |0x1 (NOMASK): No Interrupt mask + * |[1] |InEpMsk1 |IN Endpoint 1 Interrupt mask Bit + * |[2] |InEpMsk2 |IN Endpoint 2 Interrupt mask Bit + * |[3] |InEpMsk3 |IN Endpoint 3 Interrupt mask Bit + * |[4] |InEpMsk4 |IN Endpoint 4 Interrupt mask Bit + * |[5] |InEpMsk5 |IN Endpoint 5 Interrupt mask Bit + * |[6] |InEpMsk6 |IN Endpoint 6 Interrupt mask Bit + * |[7] |InEpMsk7 |IN Endpoint 7 Interrupt mask Bit + * |[8] |InEpMsk8 |IN Endpoint 8 Interrupt mask Bit + * |[16] |OutEPMsk0 |OUT Endpoint 0 Interrupt mask Bit + * | | |Values: + * | | |0x0 (MASK): OUT Endpoint 0 Interrupt mask + * | | |0x1 (NOMASK): No Interrupt mask + * |[17] |OutEPMsk1 |OUT Endpoint 1 Interrupt mask Bit + * |[18] |OutEPMsk2 |OUT Endpoint 2 Interrupt mask Bit + * |[19] |OutEPMsk3 |OUT Endpoint 3 Interrupt mask Bit + * |[20] |OutEPMsk4 |OUT Endpoint 4 Interrupt mask Bit + * |[21] |OutEPMsk5 |OUT Endpoint 5 Interrupt mask Bit + * |[22] |OutEPMsk6 |OUT Endpoint 6 Interrupt mask Bit + * |[23] |OutEPMsk7 |OUT Endpoint 7 Interrupt mask Bit + * |[24] |OutEPMsk8 |OUT Endpoint 8 Interrupt mask Bit + * @var HSUSBD_T::DTHRCTL + * Offset: 0x830 Device Threshold Control Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[0] |NonISOThrEn|Non-ISO IN Endpoints Threshold Enable (NonISOThrEn) + * | | |When this bit is Set, the core enables thresholding for Non Isochronous IN endpoints. + * | | |Values: + * | | |0x0 (DISABLED): No thresholding + * | | |0x1 (ENABLED): Enable thresholding for non-isochronous IN endpoints + * |[1] |ISOThrEn |ISO IN Endpoints Threshold Enable (ISOThrEn) + * | | |When this bit is Set, the core enables thresholding for isochronous IN endpoints. + * | | |Values: + * | | |0x0 (DISABLED): No thresholding + * | | |0x1 (ENABLED): Enables thresholding for isochronous IN endpoints + * |[10:2] |TxThrLen |Transmit Threshold Length (TxThrLen) + * | | |This field specifies Transmit thresholding size in DWORDS + * | | |This also forms the MAC threshold and specifies the amount of data in bytes to be in the corresponding endpoint transmit FIFO, before the core can start transmit on the USB + * | | |The threshold length has to be at least eight DWORDS when the value of AHBThrRatio is 2'h00 + * | | |In case the AHBThrRatio is non zero the application needs to ensure that the AHB Threshold value does not go below the recommended eight DWORD + * | | |This field controls both isochronous and non-isochronous IN endpoint thresholds + * | | |The recommended value for ThrLen is to be the same as the programmed AHB Burst Length (GAHBCFG.HBstLen). + * | | |Note: + * | | |When OTG_ARCHITECTURE=2, the reset value of this register field is 8. + * |[12:11] |AHBThrRatio|AHB Threshold Ratio (AHBThrRatio) + * | | |These bits define the ratio between the AHB threshold and the MAC threshold for the transmit path only + * | | |The AHB threshold always remains less than or equal to the USB threshold, because this does not increase overhead + * | | |Both the AHB and the MAC threshold must be DWORD-aligned + * | | |The application needs to program TxThrLen and the AHBThrRatio to make the AHB Threshold value DWORD aligned + * | | |If the AHB threshold value is not DWORD aligned, the core might not behave correctly + * | | |When programming the TxThrLen and AHBThrRatio, the application must ensure that the minimum AHB threshold value does not go below 8 DWORDS to meet the USB turnaround time requirements. + * | | |2'b00: AHB threshold = MAC threshold. + * | | |2'b01: AHB threshold = MAC threshold / 2. + * | | |2'b10: AHB threshold = MAC threshold / 4. + * | | |2'b11: AHB threshold = MAC threshold / 8. + * | | |Values: + * | | |0x0 (THRESZERO): AHB threshold = MAC threshold. + * | | |0x1 (THRESONE): AHB threshold = MAC threshold /2. + * | | |0x2 (THRESTWO): AHB threshold = MAC threshold /4. + * | | |0x3 (THRESTHREE): AHB threshold = MAC threshold /8. + * |[16] |RxThrEn |Receive Threshold Enable (RxThrEn) + * | | |When this bit is set, the core enables thresholding in the receive direction. + * | | |Note: We recommends that you do not enable RxThrEn, because it may cause issues in the RxFIFO especially during error conditions such as RxError and Babble. + * | | |Values: + * | | |0x0 (DISABLED): Disable thresholding + * | | |0x1 (ENABLED): Enable thresholding in the receive direction + * |[25:17] |RxThrLen |Receive Threshold Length (RxThrLen) + * | | |This field specifies Receive thresholding size in DWORDS + * | | |This field also specifies the amount of data received on the USB before the core can start transmitting on the AHB + * | | |The threshold length has to be at least eight DWORDS + * | | |The recommended value for ThrLen is to be the same as the programmed AHB Burst Length (GAHBCFG.HBstLen). + * |[27] |ArbPrkEn |Arbiter Parking Enable (ArbPrkEn) + * | | |This bit controls internal DMA arbiter parking for IN endpoints + * | | |If thresholding is enabled and this bit is set to one, then the arbiter parks on the IN endpoint for which there is a token received on the USB + * | | |This is done to avoid getting into underrun conditions + * | | |By default, arbiter parking is enabled. + * | | |Values: + * | | |0x0 (DISABLED): Disable DMA arbiter parking + * | | |0x1 (ENABLED): Enable DMA arbiter parking for IN endpoints + * @var HSUSBD_T::DIEPEMPMSK + * Offset: 0x834 Device IN Endpoint FIFO Empty Interrupt Mask Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[15:0] |InEpTxfEmpMsk|IN EP Tx FIFO Empty Interrupt Mask Bits (InEpTxfEmpMsk) + * | | |These bits acts as mask bits for DIEPINTn.TxFEmp interrupt, one bit per IN Endpoint: + * | | |Bit 0 for IN EP 0, bit 8 for IN EP 8 + * | | |Values: + * | | |0x1 (EP0_MASK): Mask IN EP0 Tx FIFO Empty Interrupt + * | | |0x2 (EP1_MASK): Mask IN EP1 Tx FIFO Empty Interrupt + * | | |0x4 (EP2_MASK): Mask IN EP2 Tx FIFO Empty Interrupt + * | | |0x8 (EP3_MASK): Mask IN EP3 Tx FIFO Empty Interrupt + * | | |0x10 (EP4_MASK): Mask IN EP4 Tx FIFO Empty Interrupt + * | | |0x20 (EP5_MASK): Mask IN EP5 Tx FIFO Empty Interrupt + * | | |0x40 (EP6_MASK): Mask IN EP6 Tx FIFO Empty Interrupt + * | | |0x80 (EP7_MASK): Mask IN EP7 Tx FIFO Empty Interrupt + * | | |0x100 (EP8_MASK): Mask IN EP8 Tx FIFO Empty Interrupt + * @var HSUSBD_T::DIEPCTL0 + * Offset: 0x900 Device Control IN Endpoint 0 Control Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[1:0] |MPS |Maximum Packet Size (MPS) + * | | |Applies to IN and OUT endpoints. + * | | |The application must program this field with the maximum packet size for the current logical endpoint. + * | | |2'b00: 64 bytes + * | | |2'b01: 32 bytes + * | | |2'b10: 16 bytes + * | | |2'b11: 8 bytes + * | | |Values: + * | | |0x0 (BYTES64): 64 bytes + * | | |0x1 (BYTES32): 32 bytes + * | | |0x2 (BYTES16): 16 bytes + * | | |0x3 (BYTES8): 8 bytes + * |[15] |USBActEP |USB Active Endpoint (USBActEP) (Read only) + * | | |This bit is always SET to 1, indicating that control endpoint 0 is always active in all configurations and interfaces. + * | | |Values: + * | | |0x1 (ACTIVE0): Control endpoint is always active + * |[17] |NAKSts |NAK Status (NAKSts) (Read only) + * | | |Indicates the following: + * | | |1'b0: The core is transmitting non-NAK handshakes based on the FIFO status + * | | |1'b1: The core is transmitting NAK handshakes on this endpoint. + * | | |When this bit is set, either by the application or core, the core stops transmitting data, even If there is data available in the TxFIFO + * | | |Irrespective of this bit's setting, the core always responds to SETUP data packets with an ACK handshake. + * | | |Values: + * | | |0x0 (INACTIVE): + * | | |The core is transmitting non-NAK handshakes based on the FIFO status + * | | |0x1 (ACTIVE): + * | | |The core is transmitting NAK handshakes on this endpoint + * |[19:18] |EPType |Endpoint Type (EPType) (Read only) + * | | |Hardcoded to 00 for control. + * | | |Values: + * | | |0x0 (ACTIVE): Endpoint Control 0 + * |[21] |Stall |STALL Handshake (Stall) + * | | |The application can only set this bit, and the core clears it, when a SETUP token is received for this endpoint + * | | |If a NAK bit, Global Nonperiodic IN NAK, or Global OUT NAK is set along with this bit, the STALL bit takes priority. + * | | |Values: + * | | |0x0 (INACTIVE): No Stall + * | | |0x1 (ACTIVE): Stall Handshake + * |[25:22] |TxFNum |TxFIFO Number (TxFNum) + * | | |For Dedicated FIFO operation, this value is set to the FIFO number that is assigned to IN Endpoint. + * | | |Values: + * | | |0x0 (TXFIFO0): Tx FIFO 0 + * | | |0x1 (TXFIFO1): Tx FIFO 1 + * | | |0x2 (TXFIFO2): Tx FIFO 2 + * | | |0x3 (TXFIFO3): Tx FIFO 3 + * | | |0x4 (TXFIFO4): Tx FIFO 4 + * | | |0x5 (TXFIFO5): Tx FIFO 5 + * | | |0x6 (TXFIFO6): Tx FIFO 6 + * | | |0x7 (TXFIFO7): Tx FIFO 7 + * | | |0x8 (TXFIFO8): Tx FIFO 8 + * |[26] |CNAK |Clear NAK (CNAK) + * | | |A write to this bit clears the NAK bit for the endpoint + * | | |Values: + * | | |0x0 (NOCLEAR): No action + * | | |0x1 (CLEAR): Clear NAK + * |[27] |SNAK |Set NAK (SNAK + * | | |) A write to this bit sets the NAK bit for the endpoint Using this bit, the application can control the transmission of NAK handshakes on an endpoint The core can also set this bit for an endpoint after a SETUP packet is received on that endpoint + * | | |Values: + * | | |0x0 (NOSET): No action + * | | |0x1 (SET): Set NAK + * |[30] |EPDis |Endpoint Disable (EPDis) + * | | |The application sets this bit to stop transmitting data on an endpoint, even before the transfer for that endpoint is complete + * | | |The application must wait for the Endpoint Disabled interrupt before treating the endpoint as disabled + * | | |The core clears this bit before setting the Endpoint Disabled Interrupt + * | | |The application must Set this bit only if Endpoint Enable is already set for this endpoint. + * | | |Values: + * | | |0x0 (INACTIVE): No action + * | | |0x1 (ACTIVE): Disabled Endpoint + * |[31] |EPEna |Endpoint Enable (EPEna) + * | | |When Scatter/Gather DMA mode is enabled for IN endpoints, this bit indicates that the descriptor structure and data buffer with data ready to transmit is setup. + * | | |Values: + * | | |0x0 (INACTIVE): No action + * | | |0x1 (ACTIVE): Enable Endpoint + * @var HSUSBD_T::DIEPINT0 + * Offset: 0x908 Device IN Endpoint 0 Interrupt Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[0] |XferCompl |Transfer Completed Interrupt (XferCompl) + * | | |Applies to IN and OUT endpoints. + * | | |When Scatter/Gather DMA mode is enabled + * | | |For IN endpoint this field indicates that the requested data from the descriptor is moved from external system memory to internal FIFO. + * | | |For OUT endpoint this field indicates that the requested data from the internal FIFO is moved to external system memory + * | | |This interrupt is generated only when the corresponding endpoint descriptor is closed, and the IOC bit for the corresponding descriptor is set. + * | | |Values: + * | | |0x0 (INACTIVE): No Transfer Complete Interrupt + * | | |0x1 (ACTIVE): Transfer Completed Interrupt + * |[1] |EPDisbld |Endpoint Disabled Interrupt (EPDisbld) + * | | |Applies to IN and OUT endpoints. + * | | |This bit indicates that the endpoint is disabled per the application's request. + * | | |Values: + * | | |0x0 (INACTIVE): No Endpoint Disabled Interrupt + * | | |0x1 (ACTIVE): Endpoint Disabled Interrupt + * |[2] |AHBErr |AHB Error (AHBErr) + * | | |Applies to IN and OUT endpoints. + * | | |When there is an AHB error during an AHB read/write + * | | |The application can read the corresponding endpoint DMA address register to get the error address. + * | | |Values: + * | | |0x0 (INACTIVE): No AHB Error Interrupt + * | | |0x1 (ACTIVE): AHB Error interrupt + * |[4] |INTknTXFEmp|IN Token Received When TxFIFO is Empty (INTknTXFEmp) + * | | |Applies to non-periodic IN endpoints only. + * | | |Indicates that an IN token was received when the associated TxFIFO (periodic/non-periodic) was empty + * | | |This interrupt is asserted on the endpoint for which the IN token was received. + * | | |Values: + * | | |0x0 (INACTIVE): No IN Token Received when TxFIFO Empty interrupt + * | | |0x1 (ACTIVE): IN Token Received when TxFIFO Empty Interrupt + * |[5] |INTknEPMis|IN Token Received with EP Mismatch (INTknEPMis) + * | | |Applies to non-periodic IN endpoints only. + * | | |Indicates that the data in the top of the non-periodic TxFIFO belongs to an endpoint other than the one for which the IN token was received + * | | |This interrupt is asserted on the endpoint for which the IN token was received. + * | | |Values: + * | | |0x0 (INACTIVE): No IN Token Received with EP Mismatch interrupt + * | | |0x1 (ACTIVE): IN Token Received with EP Mismatch interrupt + * |[6] |INEPNakEff|IN Endpoint NAK Effective (INEPNakEff) + * | | |Applies to periodic IN endpoints only. + * | | |This bit can be cleared when the application clears the IN endpoint NAK by writing to DIEPCTLn.CNAK. + * | | |This interrupt indicates that the core has sampled the NAK bit + * | | |Set (either by the application or by the core). + * | | |The interrupt indicates that the IN endpoint NAK bit Set by the application has taken effect in the core. + * | | |This interrupt does not guarantee that a NAK handshake is sent on the USB + * | | |A STALL bit takes priority over a NAK bit. + * | | |Values: + * | | |0x0 (INACTIVE): No IN Endpoint NAK Effective interrupt + * | | |0x1 (ACTIVE): IN Endpoint NAK Effective interrupt + * |[7] |TxFEmp |Transmit FIFO Empty (TxFEmp) (Read only) + * | | |This bit is valid only for IN Endpoints + * | | |This interrupt is asserted when the TxFIFO for this endpoint is either half or completely empty + * | | |The half or completely empty status is determined by the TxFIFO Empty Level bit in the Core AHB Configuration register (GAHBCFG.NPTxFEmpLvl)). + * | | |Values: + * | | |0x0 (INACTIVE): No Transmit FIFO Empty interrupt + * | | |0x1 (ACTIVE): Transmit FIFO Empty interrupt + * |[8] |TxfifoUndrn|Fifo Underrun (TxfifoUndrn) + * | | |Applies to IN endpoints only. + * | | |The core generates this interrupt when it detects a transmit FIFO underrun condition in threshold mode for this endpoint. + * | | |Values: + * | | |0x0 (INACTIVE): No Fifo Underrun interrupt + * | | |0x1 (ACTIVE): Fifo Underrun interrupt + * |[9] |BNAIntr |BNA (Buffer Not Available) Interrupt (BNAIntr) + * | | |The core generates this interrupt when the descriptor accessed is not ready for the Core to process, such as DMA done. + * | | |Values: + * | | |0x0 (INACTIVE): No BNA interrupt + * | | |0x1 (ACTIVE): BNA interrupt + * |[12] |BbleErr |NAK Interrupt (BbleErr) + * | | |The core generates this interrupt when babble is received for the endpoint. + * | | |Values: + * | | |0x0 (INACTIVE): No interrupt + * | | |0x1 (ACTIVE): BbleErr interrupt + * |[13] |NAKIntrpt |NAK Interrupt (NAKInterrupt) + * | | |The core generates this interrupt when a NAK is transmitted or received by the device + * | | |= 1). + * | | |F_MCLK = F_I2SCLK (When MCLKDIV is set to 0). + * | | |Note: F_MCLK is the frequency of MCLK, and F_I2SCLK is the frequency of the I2S_CLK + * |[17:8] |BCLKDIV |Bit Clock Divider + * | | |The I2S controller will generate bit clock in Master mode + * | | |Software can program these bit fields to generate sampling rate clock frequency. + * | | |F_BCLK= F_I2SCLK / (2*(BCLKDIV + 1)). + * | | |Note: F_BCLK is the frequency of BCLK and F_I2SCLK is the frequency of I2S_CLK + * @var I2S_T::IEN + * Offset: 0x08 I2S Interrupt Enable Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[0] |RXUDFIEN |Receive FIFO Underflow Interrupt Enable Bit + * | | |0 = Interrupt Disabled. + * | | |1 = Interrupt Enabled. + * | | |Note: If software reads receive FIFO when it is empty then RXUDIF (I2S_STATUS0[8]) flag is set to 1 + * | | |If RXUDFIEN bit is enabled, interrupt occurs. + * |[1] |RXOVFIEN |Receive FIFO Overflow Interrupt Enable Bit + * | | |0 = Interrupt Disabled. + * | | |1 = Interrupt Enabled. + * | | |Note: Interrupt occurs if this bit is set to 1 and RXOVIF (I2S_STATUS0[9]) flag is set to 1 + * |[2] |RXTHIEN |Receive FIFO Threshold Level Interrupt Enable Bit + * | | |0 = Interrupt Disabled. + * | | |1 = Interrupt Enabled. + * | | |Note: Interrupt occurs if this bit is set to 1 and data words in receive FIFO is larger than RXTH (I2S_CTL1[19:16]). + * |[8] |TXUDFIEN |Transmit FIFO Underflow Interrupt Enable Bit + * | | |0 = Interrupt Disabled. + * | | |1 = Interrupt Enabled. + * | | |Note: Interrupt occur if this bit is set to 1 and TXUDIF (I2S_STATUS0[16]) flag is set to 1. + * |[9] |TXOVFIEN |Transmit FIFO Overflow Interrupt Enable Bit + * | | |0 = Interrupt Disabled. + * | | |1 = Interrupt Enabled. + * | | |Note: Interrupt occurs if this bit is set to 1 and TXOVIF (I2S_STATUS0[17]) flag is set to 1 + * |[10] |TXTHIEN |Transmit FIFO Threshold Level Interrupt Enable Bit + * | | |0 = Interrupt Disabled. + * | | |1 = Interrupt Enabled. + * | | |Note: Interrupt occurs if this bit is set to 1 and data words in transmit FIFO is less than or equal to TXTH (I2S_CTL1[11:8]). + * |[16] |CH0ZCIEN |Channel0 Zero-cross Interrupt Enable Bit + * | | |0 = Interrupt Disabled. + * | | |1 = Interrupt Enabled. + * | | |Note 1: Interrupt occurs if this bit is set to 1 and channel0 zero-cross + * | | |Note 2: Channel0 also means left audio channel while I2S (FORMAT[2]=0) or 2-channel PCM mode. + * |[17] |CH1ZCIEN |Channel1 Zero-cross Interrupt Enable Bit + * | | |0 = Interrupt Disabled. + * | | |1 = Interrupt Enabled. + * | | |Note 1: Interrupt occurs if this bit is set to 1 and channel1 zero-cross + * | | |Note 2: Channel1 also means right audio channel while I2S (FORMAT[2]=0) or 2-channel PCM mode. + * |[18] |CH2ZCIEN |Channel2 Zero-cross Interrupt Enable Bit + * | | |0 = Interrupt Disabled. + * | | |1 = Interrupt Enabled. + * | | |Note 1: Interrupt occurs if this bit is set to 1 and channel2 zero-cross + * | | |Note 2: This bit is available while multi-channel PCM mode and TDMCHNUM (I2S_CTL0[31:30]) = 0x1, 0x2, 0x3. + * |[19] |CH3ZCIEN |Channel3 Zero-cross Interrupt Enable Bit + * | | |0 = Interrupt Disabled. + * | | |1 = Interrupt Enabled. + * | | |Note 1: Interrupt occurs if this bit is set to 1 and channel3 zero-cross + * | | |Note 2: This bit is available while multi-channel PCM mode and TDMCHNUM (I2S_CTL0[31:30]) = 0x1, 0x2, 0x3. + * |[20] |CH4ZCIEN |Channel4 Zero-cross Interrupt Enable Bit + * | | |0 = Interrupt Disabled. + * | | |1 = Interrupt Enabled. + * | | |Note 1: Interrupt occurs if this bit is set to 1 and channel4 zero-cross + * | | |Note 2: This bit is available while multi-channel PCM mode and TDMCHNUM (I2S_CTL0[31:30]) = 0x2, 0x3. + * |[21] |CH5ZCIEN |Channel5 Zero-cross Interrupt Enable Bit + * | | |0 = Interrupt Disabled. + * | | |1 = Interrupt Enabled. + * | | |Note 1: Interrupt occurs if this bit is set to 1 and channel5 zero-cross + * | | |Note 2: This bit is available while multi-channel PCM mode and TDMCHNUM (I2S_CTL0[31:30]) = 0x2, 0x3. + * |[22] |CH6ZCIEN |Channel6 Zero-cross Interrupt Enable Bit + * | | |0 = Interrupt Disabled. + * | | |1 = Interrupt Enabled. + * | | |Note 1: Interrupt occurs if this bit is set to 1 and channel6 zero-cross + * | | |Note 2: This bit is available while multi-channel PCM mode and TDMCHNUM (I2S_CTL0[31:30]) = 0x3. + * |[23] |CH7ZCIEN |Channel7 Zero-cross Interrupt Enable Bit + * | | |0 = Interrupt Disabled. + * | | |1 = Interrupt Enabled. + * | | |Note 1: Interrupt occurs if this bit is set to 1 and channel7 zero-cross + * | | |Note 2: This bit is available while multi-channel PCM mode and TDMCHNUM (I2S_CTL0[31:30]) = 0x3. + * @var I2S_T::STATUS0 + * Offset: 0x0C I2S Status Register 0 + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[0] |I2SINT |I2S Interrupt Flag (Read Only) + * | | |0 = No I2S interrupt. + * | | |1 = I2S interrupt. + * | | |Note: It is wire-OR of I2STXINT and I2SRXINT bits. + * |[1] |I2SRXINT |I2S Receive Interrupt (Read Only) + * | | |0 = No receive interrupt. + * | | |1 = Receive interrupt. + * |[2] |I2STXINT |I2S Transmit Interrupt (Read Only) + * | | |0 = No transmit interrupt. + * | | |1 = Transmit interrupt. + * |[5:3] |DATACH |Transmission Data Channel (Read Only) + * | | |This bit fields are used to indicate which audio channel is current transmit data belong. + * | | |000 = channel0 (means left channel while 2-channel I2S/PCM mode). + * | | |001 = channel1 (means right channel while 2-channel I2S/PCM mode). + * | | |010 = channel2 (available while 4-channel TDM PCM mode). + * | | |011 = channel3 (available while 4-channel TDM PCM mode). + * | | |100 = channel4 (available while 6-channel TDM PCM mode). + * | | |101 = channel5 (available while 6-channel TDM PCM mode). + * | | |110 = channel6 (available while 8-channel TDM PCM mode). + * | | |111 = channel7 (available while 8-channel TDM PCM mode). + * |[8] |RXUDIF |Receive FIFO Underflow Interrupt Flag + * | | |0 = No underflow occur. + * | | |1 = Underflow occur. + * | | |Note 1: When receive FIFO is empty, and software reads the receive FIFO again + * | | |This bit will be set to 1, and it indicates underflow situation occurs. + * | | |Note 2: Write 1 to clear this bit to 0 + * |[9] |RXOVIF |Receive FIFO Overflow Interrupt Flag + * | | |0 = No overflow occur. + * | | |1 = Overflow occur. + * | | |Note 1: When receive FIFO is full and receive hardware attempt to write data into receive FIFO then this bit is set to 1, data in 1st buffer is overwritten. + * | | |Note 2: Write 1 to clear this bit to 0. + * |[10] |RXTHIF |Receive FIFO Threshold Interrupt Flag (Read Only) + * | | |0 = Data word(s) in FIFO is less than or equal to threshold level. + * | | |1 = Data word(s) in FIFO is larger than threshold level. + * | | |Note: When data word(s) in receive FIFO is larger than threshold value set in RXTH (I2S_CTL1[19:16]) the RXTHIF bit becomes to 1 + * | | |It keeps at 1 till RXCNT (I2S_STATUS1[20:16]) is less than or equal to RXTH (I2S_CTL1[19:16]) after software read RXFIFO register. + * |[11] |RXFULL |Receive FIFO Full (Read Only) + * | | |0 = Not full. + * | | |1 = Full. + * | | |Note: This bit reflects data words number in receive FIFO is 16. + * |[12] |RXEMPTY |Receive FIFO Empty (Read Only) + * | | |0 = Not empty. + * | | |1 = Empty. + * | | |Note: This bit reflects data words number in receive FIFO is 0. + * |[16] |TXUDIF |Transmit FIFO Underflow Interrupt Flag + * | | |0 = No underflow. + * | | |1 = Underflow. + * | | |Note 1: This bit will be set to 1 when shift logic hardware read data from transmitting FIFO and the filling data level in transmitting FIFO is not enough for one audio frame. + * | | |Note 2: Write 1 to clear this bit to 0. + * |[17] |TXOVIF |Transmit FIFO Overflow Interrupt Flag + * | | |0 = No overflow. + * | | |1 = Overflow. + * | | |Note 1: Write data to transmit FIFO when it is full and this bit set to 1 + * | | |Note 2: Write 1 to clear this bit to 0. + * |[18] |TXTHIF |Transmit FIFO Threshold Interrupt Flag (Read Only) + * | | |0 = Data word(s) in FIFO is larger than threshold level. + * | | |1 = Data word(s) in FIFO is less than or equal to threshold level. + * | | |Note: When data word(s) in transmit FIFO is less than or equal to threshold value set in TXTH (I2S_CTL1[11:8]) the TXTHIF bit becomes to 1 + * | | |It keeps at 1 till TXCNT (I2S_STATUS1[12:8]) is larger than TXTH (I2S_CTL1[11:8]) after software write TXFIFO register. + * |[19] |TXFULL |Transmit FIFO Full (Read Only) + * | | |This bit reflect data word number in transmit FIFO is 16 + * | | |0 = Not full. + * | | |1 = Full. + * |[20] |TXEMPTY |Transmit FIFO Empty (Read Only) + * | | |This bit reflect data word number in transmit FIFO is 0 + * | | |0 = Not empty. + * | | |1 = Empty. + * |[21] |TXBUSY |Transmit Busy (Read Only) + * | | |0 = Transmit shift buffer is empty. + * | | |1 = Transmit shift buffer is busy. + * | | |Note: This bit is cleared to 0 when all data in transmit FIFO and shift buffer is shifted out + * | | |And set to 1 when 1st data is load to shift buffer + * @var I2S_T::TXFIFO + * Offset: 0x10 I2S Transmit FIFO Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[31:0] |TXFIFO |Transmit FIFO Bits + * | | |The I2S contains 16 words (16x32 bits) data buffer for data transmit + * | | |Write data to this register to prepare data for transmit + * | | |The remaining word number is indicated by TXCNT (I2S_STATUS1[12:8]). + * @var I2S_T::RXFIFO + * Offset: 0x14 I2S Receive FIFO Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[31:0] |RXFIFO |Receive FIFO Bits + * | | |I2S contains 16 words (16x32 bits) data buffer for data receive + * | | |Read this register to get data in FIFO + * | | |The remaining data word number is indicated by RXCNT (I2S_STATUS1[20:16]). + * @var I2S_T::CTL1 + * Offset: 0x20 I2S Control Register 1 + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[0] |CH0ZCEN |Channel0 Zero-cross Detection Enable Bit + * | | |0 = channel0 zero-cross detect Disabled. + * | | |1 = channel0 zero-cross detect Enabled. + * | | |Note 1: Channel0 also means left audio channel while I2S (FORMAT[2]=0) or 2-channel PCM mode. + * | | |Note 2: If this bit is set to 1, when channel0 data sign bit change or next shift data bits are all 0 then CH0ZCIF(I2S_STATUS1[0]) flag is set to 1. + * | | |Note 3: If CH0ZCIF flag is set to 1, the channel0 will be mute. + * |[1] |CH1ZCEN |Channel1 Zero-cross Detect Enable Bit + * | | |0 = channel1 zero-cross detect Disabled. + * | | |1 = channel1 zero-cross detect Enabled. + * | | |Note 1: Channel1 also means right audio channel while I2S (FORMAT[2]=0) or 2-channel PCM mode. + * | | |Note 2: If this bit is set to 1, when channel1 data sign bit change or next shift data bits are all 0 then CH1ZCIF(I2S_STATUS1[1]) flag is set to 1. + * | | |Note 3: If CH1ZCIF flag is set to 1, the channel1 will be mute. + * |[2] |CH2ZCEN |Channel2 Zero-cross Detect Enable Bit + * | | |0 = channel2 zero-cross detect Disabled. + * | | |1 = channel2 zero-cross detect Enabled. + * | | |Note 1: This bit is available while multi-channel PCM mode and TDMCHNUM (I2S_CTL0[31:30]) = 0x1, 0x2, 0x3. + * | | |Note 2: If this bit is set to 1, when channel2 data sign bit change or next shift data bits are all 0 then CH2ZCIF(I2S_STATUS1[2]) flag is set to 1. + * | | |Note 3: If CH2ZCIF flag is set to 1, the channel2 will be mute. + * |[3] |CH3ZCEN |Channel3 Zero-cross Detect Enable Bit + * | | |0 = channel3 zero-cross detect Disabled. + * | | |1 = channel3 zero-cross detect Enabled. + * | | |Note 1: This bit is available while multi-channel PCM mode and TDMCHNUM (I2S_CTL0[31:30]) = 0x1, 0x2, 0x3. + * | | |Note 2: If this bit is set to 1, when channel3 data sign bit change or next shift data bits are all 0 then CH3ZCIF(I2S_STATUS1[3]) flag is set to 1. + * | | |Note 3: If CH3ZCIF flag is set to 1, the channel3 will be mute. + * |[4] |CH4ZCEN |Channel4 Zero-cross Detect Enable Bit + * | | |0 = channel4 zero-cross detect Disabled. + * | | |1 = channel4 zero-cross detect Enabled. + * | | |Note 1: This bit is available while multi-channel PCM mode and TDMCHNUM (I2S_CTL0[31:30]) = 0x2, 0x3. + * | | |Note 2: If this bit is set to 1, when channel4 data sign bit change or next shift data bits are all 0 then CH4ZCIF(I2S_STATUS1[4]) flag is set to 1. + * | | |Note 3: If CH4ZCIF flag is set to 1, the channel4 will be mute. + * |[5] |CH5ZCEN |Channel5 Zero-cross Detect Enable Bit + * | | |0 = channel5 zero-cross detect Disabled. + * | | |1 = channel5 zero-cross detect Enabled. + * | | |Note 1: This bit is available while multi-channel PCM mode and TDMCHNUM (I2S_CTL0[31:30]) = 0x2, 0x3. + * | | |Note 2: If this bit is set to 1, when channel5 data sign bit change or next shift data bits are all 0 then CH5ZCIF(I2S_STATUS1[5]) flag is set to 1. + * | | |Note 3: If CH5ZCIF flag is set to 1, the channel5 will be mute. + * |[6] |CH6ZCEN |Channel6 Zero-cross Detect Enable Bit + * | | |0 = channel6 zero-cross detect Disabled. + * | | |1 = channel6 zero-cross detect Enabled. + * | | |Note 1: This bit is available while multi-channel PCM mode and TDMCHNUM (I2S_CTL0[31:30]) = 0x3. + * | | |Note 2: If this bit is set to 1, when channel6 data sign bit change or next shift data bits are all 0 then CH6ZCIF(I2S_STATUS1[6]) flag is set to 1. + * | | |Note 3: If CH6ZCIF flag is set to 1, the channel6 will be mute. + * |[7] |CH7ZCEN |Channel7 Zero-cross Detect Enable Bit + * | | |0 = channel7 zero-cross detect Disabled. + * | | |1 = channel7 zero-cross detect Enabled. + * | | |Note 1: This bit is available while multi-channel PCM mode and TDMCHNUM (I2S_CTL0[31:30]) = 0x3. + * | | |Note 2: If this bit is set to 1, when channel7 data sign bit change or next shift data bits are all 0 then CH7ZCIF (I2S_STATUS1[7]) flag is set to 1. + * | | |Note 3: If CH7ZCIF flag is set to 1, the channel7 will be mute. + * |[11:8] |TXTH |Transmit FIFO Threshold Level + * | | |0000 = 0 data word in transmit FIFO. + * | | |0001 = 1 data word in transmit FIFO. + * | | |0010 = 2 data words in transmit FIFO. + * | | |.... + * | | |1110 = 14 data words in transmit FIFO. + * | | |1111 = 15 data words in transmit FIFO. + * | | |Note: If remain data word number in transmit FIFO is less than or equal to threshold level then TXTHIF (I2S_STATUS0[18]) flag is set. + * |[19:16] |RXTH |Receive FIFO Threshold Level + * | | |0000 = 1 data word in receive FIFO. + * | | |0001 = 2 data words in receive FIFO. + * | | |0010 = 3 data words in receive FIFO. + * | | |.... + * | | |1110 = 15 data words in receive FIFO. + * | | |1111 = 16 data words in receive FIFO. + * | | |Note: When received data word number in receive buffer is larger than threshold level then RXTHIF (I2S_STATUS0[10]) flag is set. + * |[24] |PBWIDTH |Peripheral Bus Data Width Selection + * | | |This bit is used to choice the available data width of APB bus + * | | |It must be set to 1 while PDMA function is enable and it is set to 16-bit transmission mode + * | | |0 = 32 bits data width. + * | | |1 = 16 bits data width. + * | | |Note 1: If PBWIDTH=1, the low 16 bits of 32-bit data bus are available. + * | | |Note 2: If PBWIDTH=1, the transmitting FIFO level will be increased after two FIFO write operations. + * | | |Note 3: If PBWIDTH=1, the receiving FIFO level will be decreased after two FIFO read operations. + * |[25] |PB16ORD |FIFO Read/Write Order in 16-bit Width of Peripheral Bus + * | | |When PBWIDTH = 1, the data FIFO will be increased or decreased by two peripheral bus access + * | | |This bit is used to select the order of FIFO access operations to meet the 32-bit transmitting/receiving FIFO entries. + * | | |0 = Low 16-bit read/write access first. + * | | |1 = High 16-bit read/write access first. + * | | |Note: This bit is available while PBWIDTH = 1. + * @var I2S_T::STATUS1 + * Offset: 0x24 I2S Status Register 1 + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[0] |CH0ZCIF |Channel0 Zero-cross Interrupt Flag + * | | |It indicates channel0 next sample data sign bit is changed or all data bits are 0. + * | | |0 = No zero-cross in channel0. + * | | |1 = Channel0 zero-cross is detected. + * | | |Note 1: Write 1 to clear this bit to 0. + * | | |Note 2: Channel0 also means left audio channel while I2S (FORMAT[2]=0) or 2-channel PCM mode. + * |[1] |CH1ZCIF |Channel1 Zero-cross Interrupt Flag + * | | |It indicates channel1 next sample data sign bit is changed or all data bits are 0. + * | | |0 = No zero-cross in channel1. + * | | |1 = Channel1 zero-cross is detected. + * | | |Note 1: Write 1 to clear this bit to 0. + * | | |Note 2: Channel1 also means right audio channel while I2S (FORMAT[2]=0) or 2-channel PCM mode. + * |[2] |CH2ZCIF |Channel2 Zero-cross Interrupt Flag + * | | |It indicates channel2 next sample data sign bit is changed or all data bits are 0. + * | | |0 = No zero-cross in channel2. + * | | |1 = Channel2 zero-cross is detected. + * | | |Note 1: Write 1 to clear this bit to 0. + * | | |Note 2: This bit is available while multi-channel PCM mode and TDMCHNUM (I2S_CTL0[31:30]) = 0x1, 0x2, 0x3. + * |[3] |CH3ZCIF |Channel3 Zero-cross Interrupt Flag + * | | |It indicates channel3 next sample data sign bit is changed or all data bits are 0. + * | | |0 = No zero-cross in channel3. + * | | |1 = Channel3 zero-cross is detected. + * | | |Note 1: Write 1 to clear this bit to 0. + * | | |Note 2: This bit is available while multi-channel PCM mode and TDMCHNUM (I2S_CTL0[31:30]) = 0x1, 0x2, 0x3. + * |[4] |CH4ZCIF |Channel4 Zero-cross Interrupt Flag + * | | |It indicates channel4 next sample data sign bit is changed or all data bits are 0. + * | | |0 = No zero-cross in channel4. + * | | |1 = Channel4 zero-cross is detected. + * | | |Note 1: Write 1 to clear this bit to 0. + * | | |Note 2: This bit is available while multi-channel PCM mode and TDMCHNUM (I2S_CTL0[31:30]) = 0x2, 0x3. + * |[5] |CH5ZCIF |Channel5 Zero-cross Interrupt Flag + * | | |It indicates channel5 next sample data sign bit is changed or all data bits are 0. + * | | |0 = No zero-cross in channel5. + * | | |1 = Channel5 zero-cross is detected. + * | | |Note 1: Write 1 to clear this bit to 0. + * | | |Note 2: This bit is available while multi-channel PCM mode and TDMCHNUM (I2S_CTL0[31:30]) = 0x2, 0x3. + * |[6] |CH6ZCIF |Channel6 Zero-cross Interrupt Flag + * | | |It indicates channel6 next sample data sign bit is changed or all data bits are 0. + * | | |0 = No zero-cross in channel6. + * | | |1 = Channel6 zero-cross is detected. + * | | |Note 1: Write 1 to clear this bit to 0. + * | | |Note 2: This bit is available while multi-channel PCM mode and TDMCHNUM (I2S_CTL0[31:30]) = 0x3. + * |[7] |CH7ZCIF |Channel7 Zero-cross Interrupt Flag + * | | |It indicates channel7 next sample data sign bit is changed or all data bits are 0. + * | | |0 = No zero-cross in channel7. + * | | |1 = Channel7 zero-cross is detected. + * | | |Note 1: Write 1 to clear this bit to 0. + * | | |Note 2: This bit is available while multi-channel PCM mode and TDMCHNUM (I2S_CTL0[31:30]) = 0x3. + * |[12:8] |TXCNT |Transmit FIFO Level (Read Only) + * | | |These bits indicate the number of available entries in transmit FIFO + * | | |00000 = No data. + * | | |00001 = 1 word in transmit FIFO. + * | | |00010 = 2 words in transmit FIFO. + * | | |.... + * | | |01110 = 14 words in transmit FIFO. + * | | |01111 = 15 words in transmit FIFO. + * | | |10000 = 16 words in transmit FIFO. + * | | |Others are reserved. + * |[20:16] |RXCNT |Receive FIFO Level (Read Only) + * | | |These bits indicate the number of available entries in receive FIFO + * | | |00000 = No data. + * | | |00001 = 1 word in receive FIFO. + * | | |00010 = 2 words in receive FIFO. + * | | |.... + * | | |01110 = 14 words in receive FIFO. + * | | |01111 = 15 words in receive FIFO. + * | | |10000 = 16 words in receive FIFO. + * | | |Others are reserved. + */ + __IO uint32_t CTL0; /*!< [0x0000] I2S Control Register 0 */ + __IO uint32_t CLKDIV; /*!< [0x0004] I2S Clock Divider Register */ + __IO uint32_t IEN; /*!< [0x0008] I2S Interrupt Enable Register */ + __IO uint32_t STATUS0; /*!< [0x000c] I2S Status Register 0 */ + __O uint32_t TXFIFO; /*!< [0x0010] I2S Transmit FIFO Register */ + __I uint32_t RXFIFO; /*!< [0x0014] I2S Receive FIFO Register */ + __I uint32_t RESERVE0[2]; + __IO uint32_t CTL1; /*!< [0x0020] I2S Control Register 1 */ + __IO uint32_t STATUS1; /*!< [0x0024] I2S Status Register 1 */ + +} I2S_T; + +/** + @addtogroup I2S_CONST I2S Bit Field Definition + Constant Definitions for I2S Controller +@{ */ + +#define I2S_CTL0_I2SEN_Pos (0) /*!< I2S_T::CTL0: I2SEN Position */ +#define I2S_CTL0_I2SEN_Msk (0x1ul << I2S_CTL0_I2SEN_Pos) /*!< I2S_T::CTL0: I2SEN Mask */ + +#define I2S_CTL0_TXEN_Pos (1) /*!< I2S_T::CTL0: TXEN Position */ +#define I2S_CTL0_TXEN_Msk (0x1ul << I2S_CTL0_TXEN_Pos) /*!< I2S_T::CTL0: TXEN Mask */ + +#define I2S_CTL0_RXEN_Pos (2) /*!< I2S_T::CTL0: RXEN Position */ +#define I2S_CTL0_RXEN_Msk (0x1ul << I2S_CTL0_RXEN_Pos) /*!< I2S_T::CTL0: RXEN Mask */ + +#define I2S_CTL0_MUTE_Pos (3) /*!< I2S_T::CTL0: MUTE Position */ +#define I2S_CTL0_MUTE_Msk (0x1ul << I2S_CTL0_MUTE_Pos) /*!< I2S_T::CTL0: MUTE Mask */ + +#define I2S_CTL0_DATWIDTH_Pos (4) /*!< I2S_T::CTL0: DATWIDTH Position */ +#define I2S_CTL0_DATWIDTH_Msk (0x3ul << I2S_CTL0_DATWIDTH_Pos) /*!< I2S_T::CTL0: DATWIDTH Mask */ + +#define I2S_CTL0_MONO_Pos (6) /*!< I2S_T::CTL0: MONO Position */ +#define I2S_CTL0_MONO_Msk (0x1ul << I2S_CTL0_MONO_Pos) /*!< I2S_T::CTL0: MONO Mask */ + +#define I2S_CTL0_ORDER_Pos (7) /*!< I2S_T::CTL0: ORDER Position */ +#define I2S_CTL0_ORDER_Msk (0x1ul << I2S_CTL0_ORDER_Pos) /*!< I2S_T::CTL0: ORDER Mask */ + +#define I2S_CTL0_SLAVE_Pos (8) /*!< I2S_T::CTL0: SLAVE Position */ +#define I2S_CTL0_SLAVE_Msk (0x1ul << I2S_CTL0_SLAVE_Pos) /*!< I2S_T::CTL0: SLAVE Mask */ + +#define I2S_CTL0_MCLKEN_Pos (15) /*!< I2S_T::CTL0: MCLKEN Position */ +#define I2S_CTL0_MCLKEN_Msk (0x1ul << I2S_CTL0_MCLKEN_Pos) /*!< I2S_T::CTL0: MCLKEN Mask */ + +#define I2S_CTL0_TXFBCLR_Pos (18) /*!< I2S_T::CTL0: TXFBCLR Position */ +#define I2S_CTL0_TXFBCLR_Msk (0x1ul << I2S_CTL0_TXFBCLR_Pos) /*!< I2S_T::CTL0: TXFBCLR Mask */ + +#define I2S_CTL0_RXFBCLR_Pos (19) /*!< I2S_T::CTL0: RXFBCLR Position */ +#define I2S_CTL0_RXFBCLR_Msk (0x1ul << I2S_CTL0_RXFBCLR_Pos) /*!< I2S_T::CTL0: RXFBCLR Mask */ + +#define I2S_CTL0_TXPDMAEN_Pos (20) /*!< I2S_T::CTL0: TXPDMAEN Position */ +#define I2S_CTL0_TXPDMAEN_Msk (0x1ul << I2S_CTL0_TXPDMAEN_Pos) /*!< I2S_T::CTL0: TXPDMAEN Mask */ + +#define I2S_CTL0_RXPDMAEN_Pos (21) /*!< I2S_T::CTL0: RXPDMAEN Position */ +#define I2S_CTL0_RXPDMAEN_Msk (0x1ul << I2S_CTL0_RXPDMAEN_Pos) /*!< I2S_T::CTL0: RXPDMAEN Mask */ + +#define I2S_CTL0_RXLCH_Pos (23) /*!< I2S_T::CTL0: RXLCH Position */ +#define I2S_CTL0_RXLCH_Msk (0x1ul << I2S_CTL0_RXLCH_Pos) /*!< I2S_T::CTL0: RXLCH Mask */ + +#define I2S_CTL0_FORMAT_Pos (24) /*!< I2S_T::CTL0: FORMAT Position */ +#define I2S_CTL0_FORMAT_Msk (0x7ul << I2S_CTL0_FORMAT_Pos) /*!< I2S_T::CTL0: FORMAT Mask */ + +#define I2S_CTL0_PCMSYNC_Pos (27) /*!< I2S_T::CTL0: PCMSYNC Position */ +#define I2S_CTL0_PCMSYNC_Msk (0x1ul << I2S_CTL0_PCMSYNC_Pos) /*!< I2S_T::CTL0: PCMSYNC Mask */ + +#define I2S_CTL0_CHWIDTH_Pos (28) /*!< I2S_T::CTL0: CHWIDTH Position */ +#define I2S_CTL0_CHWIDTH_Msk (0x3ul << I2S_CTL0_CHWIDTH_Pos) /*!< I2S_T::CTL0: CHWIDTH Mask */ + +#define I2S_CTL0_TDMCHNUM_Pos (30) /*!< I2S_T::CTL0: TDMCHNUM Position */ +#define I2S_CTL0_TDMCHNUM_Msk (0x3ul << I2S_CTL0_TDMCHNUM_Pos) /*!< I2S_T::CTL0: TDMCHNUM Mask */ + +#define I2S_CLKDIV_MCLKDIV_Pos (0) /*!< I2S_T::CLKDIV: MCLKDIV Position */ +#define I2S_CLKDIV_MCLKDIV_Msk (0x7ful << I2S_CLKDIV_MCLKDIV_Pos) /*!< I2S_T::CLKDIV: MCLKDIV Mask */ + +#define I2S_CLKDIV_BCLKDIV_Pos (8) /*!< I2S_T::CLKDIV: BCLKDIV Position */ +#define I2S_CLKDIV_BCLKDIV_Msk (0x3fful << I2S_CLKDIV_BCLKDIV_Pos) /*!< I2S_T::CLKDIV: BCLKDIV Mask */ + +#define I2S_IEN_RXUDFIEN_Pos (0) /*!< I2S_T::IEN: RXUDFIEN Position */ +#define I2S_IEN_RXUDFIEN_Msk (0x1ul << I2S_IEN_RXUDFIEN_Pos) /*!< I2S_T::IEN: RXUDFIEN Mask */ + +#define I2S_IEN_RXOVFIEN_Pos (1) /*!< I2S_T::IEN: RXOVFIEN Position */ +#define I2S_IEN_RXOVFIEN_Msk (0x1ul << I2S_IEN_RXOVFIEN_Pos) /*!< I2S_T::IEN: RXOVFIEN Mask */ + +#define I2S_IEN_RXTHIEN_Pos (2) /*!< I2S_T::IEN: RXTHIEN Position */ +#define I2S_IEN_RXTHIEN_Msk (0x1ul << I2S_IEN_RXTHIEN_Pos) /*!< I2S_T::IEN: RXTHIEN Mask */ + +#define I2S_IEN_TXUDFIEN_Pos (8) /*!< I2S_T::IEN: TXUDFIEN Position */ +#define I2S_IEN_TXUDFIEN_Msk (0x1ul << I2S_IEN_TXUDFIEN_Pos) /*!< I2S_T::IEN: TXUDFIEN Mask */ + +#define I2S_IEN_TXOVFIEN_Pos (9) /*!< I2S_T::IEN: TXOVFIEN Position */ +#define I2S_IEN_TXOVFIEN_Msk (0x1ul << I2S_IEN_TXOVFIEN_Pos) /*!< I2S_T::IEN: TXOVFIEN Mask */ + +#define I2S_IEN_TXTHIEN_Pos (10) /*!< I2S_T::IEN: TXTHIEN Position */ +#define I2S_IEN_TXTHIEN_Msk (0x1ul << I2S_IEN_TXTHIEN_Pos) /*!< I2S_T::IEN: TXTHIEN Mask */ + +#define I2S_IEN_CH0ZCIEN_Pos (16) /*!< I2S_T::IEN: CH0ZCIEN Position */ +#define I2S_IEN_CH0ZCIEN_Msk (0x1ul << I2S_IEN_CH0ZCIEN_Pos) /*!< I2S_T::IEN: CH0ZCIEN Mask */ + +#define I2S_IEN_CH1ZCIEN_Pos (17) /*!< I2S_T::IEN: CH1ZCIEN Position */ +#define I2S_IEN_CH1ZCIEN_Msk (0x1ul << I2S_IEN_CH1ZCIEN_Pos) /*!< I2S_T::IEN: CH1ZCIEN Mask */ + +#define I2S_IEN_CH2ZCIEN_Pos (18) /*!< I2S_T::IEN: CH2ZCIEN Position */ +#define I2S_IEN_CH2ZCIEN_Msk (0x1ul << I2S_IEN_CH2ZCIEN_Pos) /*!< I2S_T::IEN: CH2ZCIEN Mask */ + +#define I2S_IEN_CH3ZCIEN_Pos (19) /*!< I2S_T::IEN: CH3ZCIEN Position */ +#define I2S_IEN_CH3ZCIEN_Msk (0x1ul << I2S_IEN_CH3ZCIEN_Pos) /*!< I2S_T::IEN: CH3ZCIEN Mask */ + +#define I2S_IEN_CH4ZCIEN_Pos (20) /*!< I2S_T::IEN: CH4ZCIEN Position */ +#define I2S_IEN_CH4ZCIEN_Msk (0x1ul << I2S_IEN_CH4ZCIEN_Pos) /*!< I2S_T::IEN: CH4ZCIEN Mask */ + +#define I2S_IEN_CH5ZCIEN_Pos (21) /*!< I2S_T::IEN: CH5ZCIEN Position */ +#define I2S_IEN_CH5ZCIEN_Msk (0x1ul << I2S_IEN_CH5ZCIEN_Pos) /*!< I2S_T::IEN: CH5ZCIEN Mask */ + +#define I2S_IEN_CH6ZCIEN_Pos (22) /*!< I2S_T::IEN: CH6ZCIEN Position */ +#define I2S_IEN_CH6ZCIEN_Msk (0x1ul << I2S_IEN_CH6ZCIEN_Pos) /*!< I2S_T::IEN: CH6ZCIEN Mask */ + +#define I2S_IEN_CH7ZCIEN_Pos (23) /*!< I2S_T::IEN: CH7ZCIEN Position */ +#define I2S_IEN_CH7ZCIEN_Msk (0x1ul << I2S_IEN_CH7ZCIEN_Pos) /*!< I2S_T::IEN: CH7ZCIEN Mask */ + +#define I2S_STATUS0_I2SINT_Pos (0) /*!< I2S_T::STATUS0: I2SINT Position */ +#define I2S_STATUS0_I2SINT_Msk (0x1ul << I2S_STATUS0_I2SINT_Pos) /*!< I2S_T::STATUS0: I2SINT Mask */ + +#define I2S_STATUS0_I2SRXINT_Pos (1) /*!< I2S_T::STATUS0: I2SRXINT Position */ +#define I2S_STATUS0_I2SRXINT_Msk (0x1ul << I2S_STATUS0_I2SRXINT_Pos) /*!< I2S_T::STATUS0: I2SRXINT Mask */ + +#define I2S_STATUS0_I2STXINT_Pos (2) /*!< I2S_T::STATUS0: I2STXINT Position */ +#define I2S_STATUS0_I2STXINT_Msk (0x1ul << I2S_STATUS0_I2STXINT_Pos) /*!< I2S_T::STATUS0: I2STXINT Mask */ + +#define I2S_STATUS0_DATACH_Pos (3) /*!< I2S_T::STATUS0: DATACH Position */ +#define I2S_STATUS0_DATACH_Msk (0x7ul << I2S_STATUS0_DATACH_Pos) /*!< I2S_T::STATUS0: DATACH Mask */ + +#define I2S_STATUS0_RXUDIF_Pos (8) /*!< I2S_T::STATUS0: RXUDIF Position */ +#define I2S_STATUS0_RXUDIF_Msk (0x1ul << I2S_STATUS0_RXUDIF_Pos) /*!< I2S_T::STATUS0: RXUDIF Mask */ + +#define I2S_STATUS0_RXOVIF_Pos (9) /*!< I2S_T::STATUS0: RXOVIF Position */ +#define I2S_STATUS0_RXOVIF_Msk (0x1ul << I2S_STATUS0_RXOVIF_Pos) /*!< I2S_T::STATUS0: RXOVIF Mask */ + +#define I2S_STATUS0_RXTHIF_Pos (10) /*!< I2S_T::STATUS0: RXTHIF Position */ +#define I2S_STATUS0_RXTHIF_Msk (0x1ul << I2S_STATUS0_RXTHIF_Pos) /*!< I2S_T::STATUS0: RXTHIF Mask */ + +#define I2S_STATUS0_RXFULL_Pos (11) /*!< I2S_T::STATUS0: RXFULL Position */ +#define I2S_STATUS0_RXFULL_Msk (0x1ul << I2S_STATUS0_RXFULL_Pos) /*!< I2S_T::STATUS0: RXFULL Mask */ + +#define I2S_STATUS0_RXEMPTY_Pos (12) /*!< I2S_T::STATUS0: RXEMPTY Position */ +#define I2S_STATUS0_RXEMPTY_Msk (0x1ul << I2S_STATUS0_RXEMPTY_Pos) /*!< I2S_T::STATUS0: RXEMPTY Mask */ + +#define I2S_STATUS0_TXUDIF_Pos (16) /*!< I2S_T::STATUS0: TXUDIF Position */ +#define I2S_STATUS0_TXUDIF_Msk (0x1ul << I2S_STATUS0_TXUDIF_Pos) /*!< I2S_T::STATUS0: TXUDIF Mask */ + +#define I2S_STATUS0_TXOVIF_Pos (17) /*!< I2S_T::STATUS0: TXOVIF Position */ +#define I2S_STATUS0_TXOVIF_Msk (0x1ul << I2S_STATUS0_TXOVIF_Pos) /*!< I2S_T::STATUS0: TXOVIF Mask */ + +#define I2S_STATUS0_TXTHIF_Pos (18) /*!< I2S_T::STATUS0: TXTHIF Position */ +#define I2S_STATUS0_TXTHIF_Msk (0x1ul << I2S_STATUS0_TXTHIF_Pos) /*!< I2S_T::STATUS0: TXTHIF Mask */ + +#define I2S_STATUS0_TXFULL_Pos (19) /*!< I2S_T::STATUS0: TXFULL Position */ +#define I2S_STATUS0_TXFULL_Msk (0x1ul << I2S_STATUS0_TXFULL_Pos) /*!< I2S_T::STATUS0: TXFULL Mask */ + +#define I2S_STATUS0_TXEMPTY_Pos (20) /*!< I2S_T::STATUS0: TXEMPTY Position */ +#define I2S_STATUS0_TXEMPTY_Msk (0x1ul << I2S_STATUS0_TXEMPTY_Pos) /*!< I2S_T::STATUS0: TXEMPTY Mask */ + +#define I2S_STATUS0_TXBUSY_Pos (21) /*!< I2S_T::STATUS0: TXBUSY Position */ +#define I2S_STATUS0_TXBUSY_Msk (0x1ul << I2S_STATUS0_TXBUSY_Pos) /*!< I2S_T::STATUS0: TXBUSY Mask */ + +#define I2S_TXFIFO_TXFIFO_Pos (0) /*!< I2S_T::TXFIFO: TXFIFO Position */ +#define I2S_TXFIFO_TXFIFO_Msk (0xfffffffful << I2S_TXFIFO_TXFIFO_Pos) /*!< I2S_T::TXFIFO: TXFIFO Mask */ + +#define I2S_RXFIFO_RXFIFO_Pos (0) /*!< I2S_T::RXFIFO: RXFIFO Position */ +#define I2S_RXFIFO_RXFIFO_Msk (0xfffffffful << I2S_RXFIFO_RXFIFO_Pos) /*!< I2S_T::RXFIFO: RXFIFO Mask */ + +#define I2S_CTL1_CH0ZCEN_Pos (0) /*!< I2S_T::CTL1: CH0ZCEN Position */ +#define I2S_CTL1_CH0ZCEN_Msk (0x1ul << I2S_CTL1_CH0ZCEN_Pos) /*!< I2S_T::CTL1: CH0ZCEN Mask */ + +#define I2S_CTL1_CH1ZCEN_Pos (1) /*!< I2S_T::CTL1: CH1ZCEN Position */ +#define I2S_CTL1_CH1ZCEN_Msk (0x1ul << I2S_CTL1_CH1ZCEN_Pos) /*!< I2S_T::CTL1: CH1ZCEN Mask */ + +#define I2S_CTL1_CH2ZCEN_Pos (2) /*!< I2S_T::CTL1: CH2ZCEN Position */ +#define I2S_CTL1_CH2ZCEN_Msk (0x1ul << I2S_CTL1_CH2ZCEN_Pos) /*!< I2S_T::CTL1: CH2ZCEN Mask */ + +#define I2S_CTL1_CH3ZCEN_Pos (3) /*!< I2S_T::CTL1: CH3ZCEN Position */ +#define I2S_CTL1_CH3ZCEN_Msk (0x1ul << I2S_CTL1_CH3ZCEN_Pos) /*!< I2S_T::CTL1: CH3ZCEN Mask */ + +#define I2S_CTL1_CH4ZCEN_Pos (4) /*!< I2S_T::CTL1: CH4ZCEN Position */ +#define I2S_CTL1_CH4ZCEN_Msk (0x1ul << I2S_CTL1_CH4ZCEN_Pos) /*!< I2S_T::CTL1: CH4ZCEN Mask */ + +#define I2S_CTL1_CH5ZCEN_Pos (5) /*!< I2S_T::CTL1: CH5ZCEN Position */ +#define I2S_CTL1_CH5ZCEN_Msk (0x1ul << I2S_CTL1_CH5ZCEN_Pos) /*!< I2S_T::CTL1: CH5ZCEN Mask */ + +#define I2S_CTL1_CH6ZCEN_Pos (6) /*!< I2S_T::CTL1: CH6ZCEN Position */ +#define I2S_CTL1_CH6ZCEN_Msk (0x1ul << I2S_CTL1_CH6ZCEN_Pos) /*!< I2S_T::CTL1: CH6ZCEN Mask */ + +#define I2S_CTL1_CH7ZCEN_Pos (7) /*!< I2S_T::CTL1: CH7ZCEN Position */ +#define I2S_CTL1_CH7ZCEN_Msk (0x1ul << I2S_CTL1_CH7ZCEN_Pos) /*!< I2S_T::CTL1: CH7ZCEN Mask */ + +#define I2S_CTL1_TXTH_Pos (8) /*!< I2S_T::CTL1: TXTH Position */ +#define I2S_CTL1_TXTH_Msk (0xful << I2S_CTL1_TXTH_Pos) /*!< I2S_T::CTL1: TXTH Mask */ + +#define I2S_CTL1_RXTH_Pos (16) /*!< I2S_T::CTL1: RXTH Position */ +#define I2S_CTL1_RXTH_Msk (0xful << I2S_CTL1_RXTH_Pos) /*!< I2S_T::CTL1: RXTH Mask */ + +#define I2S_CTL1_PBWIDTH_Pos (24) /*!< I2S_T::CTL1: PBWIDTH Position */ +#define I2S_CTL1_PBWIDTH_Msk (0x1ul << I2S_CTL1_PBWIDTH_Pos) /*!< I2S_T::CTL1: PBWIDTH Mask */ + +#define I2S_CTL1_PB16ORD_Pos (25) /*!< I2S_T::CTL1: PB16ORD Position */ +#define I2S_CTL1_PB16ORD_Msk (0x1ul << I2S_CTL1_PB16ORD_Pos) /*!< I2S_T::CTL1: PB16ORD Mask */ + +#define I2S_STATUS1_CH0ZCIF_Pos (0) /*!< I2S_T::STATUS1: CH0ZCIF Position */ +#define I2S_STATUS1_CH0ZCIF_Msk (0x1ul << I2S_STATUS1_CH0ZCIF_Pos) /*!< I2S_T::STATUS1: CH0ZCIF Mask */ + +#define I2S_STATUS1_CH1ZCIF_Pos (1) /*!< I2S_T::STATUS1: CH1ZCIF Position */ +#define I2S_STATUS1_CH1ZCIF_Msk (0x1ul << I2S_STATUS1_CH1ZCIF_Pos) /*!< I2S_T::STATUS1: CH1ZCIF Mask */ + +#define I2S_STATUS1_CH2ZCIF_Pos (2) /*!< I2S_T::STATUS1: CH2ZCIF Position */ +#define I2S_STATUS1_CH2ZCIF_Msk (0x1ul << I2S_STATUS1_CH2ZCIF_Pos) /*!< I2S_T::STATUS1: CH2ZCIF Mask */ + +#define I2S_STATUS1_CH3ZCIF_Pos (3) /*!< I2S_T::STATUS1: CH3ZCIF Position */ +#define I2S_STATUS1_CH3ZCIF_Msk (0x1ul << I2S_STATUS1_CH3ZCIF_Pos) /*!< I2S_T::STATUS1: CH3ZCIF Mask */ + +#define I2S_STATUS1_CH4ZCIF_Pos (4) /*!< I2S_T::STATUS1: CH4ZCIF Position */ +#define I2S_STATUS1_CH4ZCIF_Msk (0x1ul << I2S_STATUS1_CH4ZCIF_Pos) /*!< I2S_T::STATUS1: CH4ZCIF Mask */ + +#define I2S_STATUS1_CH5ZCIF_Pos (5) /*!< I2S_T::STATUS1: CH5ZCIF Position */ +#define I2S_STATUS1_CH5ZCIF_Msk (0x1ul << I2S_STATUS1_CH5ZCIF_Pos) /*!< I2S_T::STATUS1: CH5ZCIF Mask */ + +#define I2S_STATUS1_CH6ZCIF_Pos (6) /*!< I2S_T::STATUS1: CH6ZCIF Position */ +#define I2S_STATUS1_CH6ZCIF_Msk (0x1ul << I2S_STATUS1_CH6ZCIF_Pos) /*!< I2S_T::STATUS1: CH6ZCIF Mask */ + +#define I2S_STATUS1_CH7ZCIF_Pos (7) /*!< I2S_T::STATUS1: CH7ZCIF Position */ +#define I2S_STATUS1_CH7ZCIF_Msk (0x1ul << I2S_STATUS1_CH7ZCIF_Pos) /*!< I2S_T::STATUS1: CH7ZCIF Mask */ + +#define I2S_STATUS1_TXCNT_Pos (8) /*!< I2S_T::STATUS1: TXCNT Position */ +#define I2S_STATUS1_TXCNT_Msk (0x1ful << I2S_STATUS1_TXCNT_Pos) /*!< I2S_T::STATUS1: TXCNT Mask */ + +#define I2S_STATUS1_RXCNT_Pos (16) /*!< I2S_T::STATUS1: RXCNT Position */ +#define I2S_STATUS1_RXCNT_Msk (0x1ful << I2S_STATUS1_RXCNT_Pos) /*!< I2S_T::STATUS1: RXCNT Mask */ + +/**@}*/ /* I2S_CONST */ +/**@}*/ /* end of I2S register group */ +/**@}*/ /* end of REGISTER group */ + +#if defined ( __CC_ARM ) + #pragma no_anon_unions +#endif + +#endif /* __I2S_REG_H__ */ diff --git a/bsp/nuvoton/libraries/ma35/Device/Nuvoton/MA35D1/Include/kpi_reg.h b/bsp/nuvoton/libraries/ma35/Device/Nuvoton/MA35D1/Include/kpi_reg.h new file mode 100644 index 0000000000..74cc94dd85 --- /dev/null +++ b/bsp/nuvoton/libraries/ma35/Device/Nuvoton/MA35D1/Include/kpi_reg.h @@ -0,0 +1,409 @@ +/**************************************************************************//** + * @file kpi_reg.h + * @version V1.00 + * @brief KPI register definition header file + * + * SPDX-License-Identifier: Apache-2.0 + * @copyright (C) 20 Nuvoton Technology Corp. All rights reserved. + *****************************************************************************/ +#ifndef __KPI_REG_H__ +#define __KPI_REG_H__ + +#if defined ( __CC_ARM ) + #pragma anon_unions +#endif + +/** + @addtogroup REGISTER Control Register + @{ +*/ + +/** + @addtogroup Keypad Interface (KPI) + Memory Mapped Structure for KPI Controller +@{ */ + +typedef struct +{ + + + /** + * @var KPI_T::KPICONF + * Offset: 0x00 Keypad Configuration Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[0] |ENKP |Keypad Scan Enable Bit + * | | |Setting this bit high enables the key scan function. + * | | |0 = Keypad scan Disabled. + * | | |1 = Keypad scan Enabled. + * |[1] |PKINTEN |Press Key Interrupt Enable Bit + * | | |The keypad controller will generate an interrupt when the controller detects any effective key press. + * | | |0 = Keypad press interrupt Disabled. + * | | |1 = Keypad press interrupt Enabled. + * | | |Note: The bit will be reset when KPI reset occurs. + * |[2] |RKINTEN |Release Key Interrupt Enable Bit + * | | |The keypad controller will generate an interrupt when the controller detects keypad status changes from press to release. + * | | |0 = Keypad release interrupt Disabled. + * | | |1 = Keypad release interrupt Enabled. + * | | |Note: The bit will be reset when KPI reset occurs. + * |[3] |INTEN |Key Interrupt Enable Bit + * | | |0 = Keypad interrupt Disabled. + * | | |1 = Keypad interrupt Enabled. + * | | |Note: The bit will be reset when KPI reset occurs. + * |[5] |WAKEUP |Lower Power Wakeup Enable Bit + * | | |Setting this bit enables low power wakeup. + * | | |0 = Wakeup Disabled. + * | | |1 = Wakeup Enabled. + * | | |Note: Setting the bit will force all KPI scan out to low. + * |[15:8] |PRESCALE |Row Scan Cycle Pre-scale Value + * | | |This value is used to pre-scale row scan cycle. + * | | |The pre-scale counter is clocked by the divided crystal clock, xCLOCK. + * | | |The divided number is from 1 to 256. + * | | |E.g.If the crystal clock is 1Mhz then the xCLOCK period is 1us. + * | | |If the keypad matric is 3x3 then + * | | |Each row scan time = xCLOCK x PRESCALE x PrescaleDivider. + * | | |Key array scan time = Each row scan time x ROWS. + * | | |Example scan time for PRESCALE = 0x40, and PrescaleDivider = 0x1F. + * | | |Each row scan time = 1us x 65 x 32 = 2.08ms. + * | | |Scan time = 2.08 x 3 = 6.24ms. + * | | |Note: + * | | |When PRESCALE is determined, De-bounce sampling cycle should not exceed the half of (PRESCALE x PrescaleDivider), + * | | |in the above example, and if scan row delay cycle is 4 xclock + * | | |The maximum DBCLKSEL should be 4*256 xCLOCK, bouncing time is 1ms. + * |[19:16] |DBCLKSEL |Scan in De-bounce Sampling Cycle Selection + * | | |0000 = Reserved. + * | | |0001 = Reserved. + * | | |0010 = Reserved. + * | | |0011 = Sample interrupt input once per 8 clocks. + * | | |0100 = Sample interrupt input once per 16 clocks. + * | | |0101 = Sample interrupt input once per 32 clocks. + * | | |0110 = Sample interrupt input once per 64 clocks. + * | | |0111 = Sample interrupt input once per 128 clocks. + * | | |1000 = Sample interrupt input once per 256 clocks. + * | | |1001 = Sample interrupt input once per 512 clocks. + * | | |1010 = Sample interrupt input once per 1024 clocks. + * | | |1011 = Sample interrupt input once per 2048 clocks. + * | | |1100 = Sample interrupt input once per 4096 clocks. + * | | |1101 = Sample interrupt input once per 8192 clocks. + * | | |1110 = reserved. + * | | |1111 = reserved. + * | | |Note: + * | | |scan row delay cycle < debounce sampling cycle. + * | | |row scan time > scan row delay cycle + (2 * debounce sampling cycle). + * | | |row scan time = prescale * 32 (xclock). + * | | |xclock = 1 MHz ~32 kHz. + * | | |bouncing time last for 1ms + * | | |For example, if xclock = 1 MHz,. + * | | |debounce sampling cycle choose 1024 xclock, + * | | |and scan row delay cycle choose 8 xclock, + * | | |row scan time should choose larger than (8+2048) xclock, + * | | |suppose PrescaleDivider = 0x1F, then prescale = 65 (2056/32 = 64.25). + * |[23:22] |SCANROWD |Scan Row Delay + * | | |Setting delay cycle when row change. + * | | |00 = 4 KPI engine clock cycle. + * | | |01 = 8 KPI engine clock cycle. + * | | |10 = 16 KPI engine clock cycle. + * | | |11 = 32 KPI engine clock cycle. + * | | |Note: + * | | |scan row delay cycle < debounce sampling cycle. + * | | |row scan time > scan row delay cycle + (2 * debounce sampling cycle). + * |[26:24] |KCOL |Keypad Matrix COL Number + * | | |The keypad matrix is set by ROW x COL. The COL number can be set 1 to 8. + * | | |000 = 1. + * | | |001 = 2. + * | | |010 = 3. + * | | |011 = 4. + * | | |100 = 5. + * | | |101 = 6. + * | | |110 = 7. + * | | |111 = 8. + * |[30:28] |KROW |Keypad Matrix ROW Number + * | | |The keypad matrix is set by ROW x COL. The ROW number can be set 2 to 6. + * | | |000 = reserved. + * | | |001 = 2. + * | | |010 = 3. + * | | |011 = 4. + * | | |100 = 5. + * | | |101 = 6. + * | | |110 = Reserved. + * | | |111 = Reserved. + * @var KPI_T::KPI3KCONF + * Offset: 0x04 Keypad 3-keys Configuration Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[2:0] |K30C |The #0 Key Column Address + * |[5:3] |K30R |The #0 Key Row Address + * | | |The #0 means the row address and the column address is the lowest of the specified 3-keys + * |[10:8] |K31C |The #1 Key Column Address + * |[13:11] |K31R |The #1 Key Row Address + * | | |The #1 means the row address and the column address is the 2nd of the specified 3-keys + * |[18:16] |K32C |The #2 Key Column Address + * |[21:19] |K32R |The #2 Key Row Address + * | | |The #2 means the row address and the column address is the highest of the specified 3-keys + * |[24] |EN3KYRST |Enable Three-key Reset + * | | |Setting this bit enables hardware reset when three-key is detected + * | | |0 = Three-key function Disabled. + * | | |1 = Three-key function Enabled. + * | | |Note: The bit will be reset when KPI reset occurs. + * @var KPI_T::KPISTATUS + * Offset: 0x08 Keypad Status Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[0] |PDWAKE |Power Down Wakeup Flag + * | | |This flag indicates the chip is woken up from power down by keypad. + * | | |When READ: + * | | |0 = No wakeup. + * | | |1 = Wake-up by keypad. + * | | |When WRITE: + * | | |0 = No operation. + * | | |1 = Clear interrupt flag. + * |[1] |RST3KEY |3-keys Reset Flag + * | | |This bit will be set after 3-keys reset occurs. + * | | |When READ: + * | | |0 = No reset. + * | | |1 = 3 keys reset interrupt occurred. + * | | |When WRITE: + * | | |0 = No operation. + * | | |1 = Clear interrupt flag. + * |[2] |KEYINT |Key Interrupt + * | | |This bit indicates the key scan interrupt is active when any key press or release or three key reset or wake up. + * | | |When READ: + * | | |0 = No reset. + * | | |1 = Key press/release/3-key reset/wakeup interrupt occurred. + * |[3] |RKEYINT |Release Key Interrupt + * | | |This bit indicates that some keys (one or multiple key) have been released. + * | | |When READ: + * | | |0 = No key release. + * | | |1 = At least one key release. + * | | |Note: To clear RKEYINT, software must clear each releasing event that are shown on u201Ckey releasing eventu201D. + * | | |C code example: + * | | |DWORD RKE0, RKE1 + * | | |PKE0 = reg_read(KPIKRE0); PKE1 = reg_read(KPIKRE1);. + * | | |Reg_write(KPIKRE0, RKE0); Reg_write(KPIKRE1, RKE1) + * |[4] |PKEYINT |Press Key Interrupt + * | | |This bit indicates that some keys (one or multiple key) have been pressed. + * | | |When READ: + * | | |0 = No key press. + * | | |1 = At least one key press. + * | | |Note: To clear PKEYINT, software must clear each pressing event that are shown on u201CKPIKPE1, KPIKPE0u201D. + * | | |C code example: + * | | |DWORD PKE0, PKE1 + * | | |PKE0 = reg_read(KPIKPE0); PKE1 = reg_read(KPIKPE1);. + * | | |Reg_write(KPIKPE0, PKE0); Reg_write(KPIKPE1, PKE1) + * @var KPI_T::KPIRSTC + * Offset: 0x0C Keypad Reset Period Control Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[7:0] |RSTC |3-key Reset Period Count + * | | |The keypad controller generates a reset signal when it detects 3-key match condition, if the EN3KYRST (KPI3KCONF[24]) is set + * | | |The RSTC is used to control the reset period. + * | | |Reset period = 64 * RSTC XCLOCK. + * @var KPI_T::KPIKEST0 + * Offset: 0x10 Keypad State Register 0 + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[31:0] |KESTmn |Key State + * | | |KESTm,n: m is row number, n is column number + * | | |0 = Key m,n is pressing. + * | | |1 = Key m,n is releasing. + * @var KPI_T::KPIKEST1 + * Offset: 0x14 Keypad State Register 1 + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[15:0] |KESTmn |Key State + * | | |KESTm,n: m is row number, n is column number + * | | |0 = Key m,n is pressing. + * | | |1 = Key m,n is releasing. + * @var KPI_T::KPIKPE0 + * Offset: 0x18 Lower 32 Key Press Event Indicator + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[31:0] |KPEmn |Lower 32 Key Press Event Change Indicator + * | | |KPE mn[X] = 1, m=row, n=column:. + * | | |0 = No key event. + * | | |1 = Corresponding key has a high to low event change. + * | | |Note: + * | | |Hardware will set this bit, and software should clear this bit by writing 1. + * | | |Software can clear PKEYINT (KPISTATUS[4]) by writing 1 bit by bit to this register. + * @var KPI_T::KPIKPE1 + * Offset: 0x1C Upper 32 Key Press Event Indicator + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[15:0] |KPEmn |Upper 32 Key Press Event Change Indicator + * | | |KPE mn[X] = 1, m=row, n=column:. + * | | |0 = No key event. + * | | |1 = Corresponding key has a high to low event change. + * | | |Note: + * | | |Hardware will set this bit, and software should clear this bit by writing 1. + * | | |Software can clear PKEYINT (KPISTATUS[4]) by writing 1 bit by bit to this register. + * @var KPI_T::KPIKRE0 + * Offset: 0x20 Lower 32 Key Release Event Indicator + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[31:0] |KREmn |Lower 32 Key Release Event Change Indicator + * | | |KRE mn[X] = 1, m=row, n=column:. + * | | |0 = No key event. + * | | |1 = Corresponding key has a low to high event change. + * | | |Note: + * | | |Hardware will set this bit, and software should clear this bit by writing 1. + * | | |Software can clear RKEYINT (KPISTATUS[3]) by writing 1 bit by bit to this register. + * @var KPI_T::KPIKRE1 + * Offset: 0x24 Upper 32 Key Release Event Indicator + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[15:0] |KREmn |Upper 32 Key Release Event Change Indicator + * | | |KRE mn[X] = 1, m=row, n=column:. + * | | |0 = No key event. + * | | |1 = Corresponding key has a low to high event change. + * | | |Note: + * | | |Hardware will set this bit, and software should clear this bit by writing 1. + * | | |Software can clear RKEYINT (KPISTATUS[3]) by writing 1 bit by bit to this register. + * @var KPI_T::KPIPRESCALDIV + * Offset: 0x28 Pre-scale Divider + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[7:0] |PRESCALDIV|Pre-scale Divider + * | | |This value is used to divide RESCALE that is set in KPICONF[15:8] + * | | |The prescale divider counter is clocked by the divided crystal clock, xCLOCK + * | | |The number is from 1 to 256. + * | | |E.g. If the crystal clock is 1Mhz then the xCLOCK period is 1us. If the keypad matrix is 3x3. Then, + * | | |each row scan time = xCLOCK x PRESCALE x PrescaleDivider. + * | | |key array scan time = each row scan time x ROWS. + * | | |example scan time for PRESCALE = 0x40, and PrescaleDivider = 0x1F. + * | | |each row scan time = 1us x 65 x 32 = 2.08ms. + * | | |scan time = 2.08 x 3 = 6.24ms. + * | | |Note: + * | | |When PRESCALE (KPICONF[15:8]) is determined, De-bounce sampling cycle should not exceed the half of (PRESCALE x PrescaleDivider), + * | | |in the above example, and if scan row delay cycle is 4 xclock + * | | |The maximum DBCLKSEL(KPICONF[19:16]) should be 1024 x clock, bouncing time is 1ms. + */ + __IO uint32_t KPICONF; /*!< [0x0000] Keypad Configuration Register */ + __IO uint32_t KPI3KCONF; /*!< [0x0004] Keypad 3-keys Configuration Register */ + __IO uint32_t KPISTATUS; /*!< [0x0008] Keypad Status Register */ + __IO uint32_t KPIRSTC; /*!< [0x000c] Keypad Reset Period Control Register */ + __I uint32_t KPIKEST0; /*!< [0x0010] Keypad State Register 0 */ + __I uint32_t KPIKEST1; /*!< [0x0014] Keypad State Register 1 */ + __IO uint32_t KPIKPE0; /*!< [0x0018] Lower 32 Key Press Event Indicator */ + __IO uint32_t KPIKPE1; /*!< [0x001c] Upper 32 Key Press Event Indicator */ + __IO uint32_t KPIKRE0; /*!< [0x0020] Lower 32 Key Release Event Indicator */ + __IO uint32_t KPIKRE1; /*!< [0x0024] Upper 32 Key Release Event Indicator */ + __IO uint32_t KPIPRESCALDIV; /*!< [0x0028] Pre-scale Divider */ + +} KPI_T; + +/** + @addtogroup KPI_CONST KPI Bit Field Definition + Constant Definitions for KPI Controller +@{ */ + +#define KPI_KPICONF_ENKP_Pos (0) /*!< KPI_T::KPICONF: ENKP Position */ +#define KPI_KPICONF_ENKP_Msk (0x1ul << KPI_KPICONF_ENKP_Pos) /*!< KPI_T::KPICONF: ENKP Mask */ + +#define KPI_KPICONF_PKINTEN_Pos (1) /*!< KPI_T::KPICONF: PKINTEN Position */ +#define KPI_KPICONF_PKINTEN_Msk (0x1ul << KPI_KPICONF_PKINTEN_Pos) /*!< KPI_T::KPICONF: PKINTEN Mask */ + +#define KPI_KPICONF_RKINTEN_Pos (2) /*!< KPI_T::KPICONF: RKINTEN Position */ +#define KPI_KPICONF_RKINTEN_Msk (0x1ul << KPI_KPICONF_RKINTEN_Pos) /*!< KPI_T::KPICONF: RKINTEN Mask */ + +#define KPI_KPICONF_INTEN_Pos (3) /*!< KPI_T::KPICONF: INTEN Position */ +#define KPI_KPICONF_INTEN_Msk (0x1ul << KPI_KPICONF_INTEN_Pos) /*!< KPI_T::KPICONF: INTEN Mask */ + +#define KPI_KPICONF_WAKEUP_Pos (5) /*!< KPI_T::KPICONF: WAKEUP Position */ +#define KPI_KPICONF_WAKEUP_Msk (0x1ul << KPI_KPICONF_WAKEUP_Pos) /*!< KPI_T::KPICONF: WAKEUP Mask */ + +#define KPI_KPICONF_PRESCALE_Pos (8) /*!< KPI_T::KPICONF: PRESCALE Position */ +#define KPI_KPICONF_PRESCALE_Msk (0xfful << KPI_KPICONF_PRESCALE_Pos) /*!< KPI_T::KPICONF: PRESCALE Mask */ + +#define KPI_KPICONF_DBCLKSEL_Pos (16) /*!< KPI_T::KPICONF: DBCLKSEL Position */ +#define KPI_KPICONF_DBCLKSEL_Msk (0xful << KPI_KPICONF_DBCLKSEL_Pos) /*!< KPI_T::KPICONF: DBCLKSEL Mask */ + +#define KPI_KPICONF_SCANROWD_Pos (22) /*!< KPI_T::KPICONF: SCANROWD Position */ +#define KPI_KPICONF_SCANROWD_Msk (0x3ul << KPI_KPICONF_SCANROWD_Pos) /*!< KPI_T::KPICONF: SCANROWD Mask */ + +#define KPI_KPICONF_KCOL_Pos (24) /*!< KPI_T::KPICONF: KCOL Position */ +#define KPI_KPICONF_KCOL_Msk (0x7ul << KPI_KPICONF_KCOL_Pos) /*!< KPI_T::KPICONF: KCOL Mask */ + +#define KPI_KPICONF_KROW_Pos (28) /*!< KPI_T::KPICONF: KROW Position */ +#define KPI_KPICONF_KROW_Msk (0x7ul << KPI_KPICONF_KROW_Pos) /*!< KPI_T::KPICONF: KROW Mask */ + +#define KPI_KPI3KCONF_K30C_Pos (0) /*!< KPI_T::KPI3KCONF: K30C Position */ +#define KPI_KPI3KCONF_K30C_Msk (0x7ul << KPI_KPI3KCONF_K30C_Pos) /*!< KPI_T::KPI3KCONF: K30C Mask */ + +#define KPI_KPI3KCONF_K30R_Pos (3) /*!< KPI_T::KPI3KCONF: K30R Position */ +#define KPI_KPI3KCONF_K30R_Msk (0x7ul << KPI_KPI3KCONF_K30R_Pos) /*!< KPI_T::KPI3KCONF: K30R Mask */ + +#define KPI_KPI3KCONF_K31C_Pos (8) /*!< KPI_T::KPI3KCONF: K31C Position */ +#define KPI_KPI3KCONF_K31C_Msk (0x7ul << KPI_KPI3KCONF_K31C_Pos) /*!< KPI_T::KPI3KCONF: K31C Mask */ + +#define KPI_KPI3KCONF_K31R_Pos (11) /*!< KPI_T::KPI3KCONF: K31R Position */ +#define KPI_KPI3KCONF_K31R_Msk (0x7ul << KPI_KPI3KCONF_K31R_Pos) /*!< KPI_T::KPI3KCONF: K31R Mask */ + +#define KPI_KPI3KCONF_K32C_Pos (16) /*!< KPI_T::KPI3KCONF: K32C Position */ +#define KPI_KPI3KCONF_K32C_Msk (0x7ul << KPI_KPI3KCONF_K32C_Pos) /*!< KPI_T::KPI3KCONF: K32C Mask */ + +#define KPI_KPI3KCONF_K32R_Pos (19) /*!< KPI_T::KPI3KCONF: K32R Position */ +#define KPI_KPI3KCONF_K32R_Msk (0x7ul << KPI_KPI3KCONF_K32R_Pos) /*!< KPI_T::KPI3KCONF: K32R Mask */ + +#define KPI_KPI3KCONF_EN3KYRST_Pos (24) /*!< KPI_T::KPI3KCONF: EN3KYRST Position */ +#define KPI_KPI3KCONF_EN3KYRST_Msk (0x1ul << KPI_KPI3KCONF_EN3KYRST_Pos) /*!< KPI_T::KPI3KCONF: EN3KYRST Mask */ + +#define KPI_KPISTATUS_PDWAKE_Pos (0) /*!< KPI_T::KPISTATUS: PDWAKE Position */ +#define KPI_KPISTATUS_PDWAKE_Msk (0x1ul << KPI_KPISTATUS_PDWAKE_Pos) /*!< KPI_T::KPISTATUS: PDWAKE Mask */ + +#define KPI_KPISTATUS_RST3KEY_Pos (1) /*!< KPI_T::KPISTATUS: RST3KEY Position */ +#define KPI_KPISTATUS_RST3KEY_Msk (0x1ul << KPI_KPISTATUS_RST3KEY_Pos) /*!< KPI_T::KPISTATUS: RST3KEY Mask */ + +#define KPI_KPISTATUS_KEYINT_Pos (2) /*!< KPI_T::KPISTATUS: KEYINT Position */ +#define KPI_KPISTATUS_KEYINT_Msk (0x1ul << KPI_KPISTATUS_KEYINT_Pos) /*!< KPI_T::KPISTATUS: KEYINT Mask */ + +#define KPI_KPISTATUS_RKEYINT_Pos (3) /*!< KPI_T::KPISTATUS: RKEYINT Position */ +#define KPI_KPISTATUS_RKEYINT_Msk (0x1ul << KPI_KPISTATUS_RKEYINT_Pos) /*!< KPI_T::KPISTATUS: RKEYINT Mask */ + +#define KPI_KPISTATUS_PKEYINT_Pos (4) /*!< KPI_T::KPISTATUS: PKEYINT Position */ +#define KPI_KPISTATUS_PKEYINT_Msk (0x1ul << KPI_KPISTATUS_PKEYINT_Pos) /*!< KPI_T::KPISTATUS: PKEYINT Mask */ + +#define KPI_KPIRSTC_RSTC_Pos (0) /*!< KPI_T::KPIRSTC: RSTC Position */ +#define KPI_KPIRSTC_RSTC_Msk (0xfful << KPI_KPIRSTC_RSTC_Pos) /*!< KPI_T::KPIRSTC: RSTC Mask */ + +#define KPI_KPIKEST0_KESTmn_Pos (0) /*!< KPI_T::KPIKEST0: KESTmn Position */ +#define KPI_KPIKEST0_KESTmn_Msk (0xfffffffful << KPI_KPIKEST0_KESTmn_Pos) /*!< KPI_T::KPIKEST0: KESTmn Mask */ + +#define KPI_KPIKEST1_KESTmn_Pos (0) /*!< KPI_T::KPIKEST1: KESTmn Position */ +#define KPI_KPIKEST1_KESTmn_Msk (0xfffful << KPI_KPIKEST1_KESTmn_Pos) /*!< KPI_T::KPIKEST1: KESTmn Mask */ + +#define KPI_KPIKPE0_KPEmn_Pos (0) /*!< KPI_T::KPIKPE0: KPEmn Position */ +#define KPI_KPIKPE0_KPEmn_Msk (0xfffffffful << KPI_KPIKPE0_KPEmn_Pos) /*!< KPI_T::KPIKPE0: KPEmn Mask */ + +#define KPI_KPIKPE1_KPEmn_Pos (0) /*!< KPI_T::KPIKPE1: KPEmn Position */ +#define KPI_KPIKPE1_KPEmn_Msk (0xfffful << KPI_KPIKPE1_KPEmn_Pos) /*!< KPI_T::KPIKPE1: KPEmn Mask */ + +#define KPI_KPIKRE0_KREmn_Pos (0) /*!< KPI_T::KPIKRE0: KREmn Position */ +#define KPI_KPIKRE0_KREmn_Msk (0xfffffffful << KPI_KPIKRE0_KREmn_Pos) /*!< KPI_T::KPIKRE0: KREmn Mask */ + +#define KPI_KPIKRE1_KREmn_Pos (0) /*!< KPI_T::KPIKRE1: KREmn Position */ +#define KPI_KPIKRE1_KREmn_Msk (0xfffful << KPI_KPIKRE1_KREmn_Pos) /*!< KPI_T::KPIKRE1: KREmn Mask */ + +#define KPI_KPIPRESCALDIV_PRESCALDIV_Pos (0) /*!< KPI_T::KPIPRESCALDIV: PRESCALDIV Position*/ +#define KPI_KPIPRESCALDIV_PRESCALDIV_Msk (0xfful << KPI_KPIPRESCALDIV_PRESCALDIV_Pos) /*!< KPI_T::KPIPRESCALDIV: PRESCALDIV Mask */ + +/**@}*/ /* KPI_CONST */ +/**@}*/ /* end of KPI register group */ + +#if defined ( __CC_ARM ) + #pragma no_anon_unions +#endif + +#endif /* __KPI_REG_H__ */ + + diff --git a/bsp/nuvoton/libraries/ma35/Device/Nuvoton/MA35D1/Include/ks_reg.h b/bsp/nuvoton/libraries/ma35/Device/Nuvoton/MA35D1/Include/ks_reg.h new file mode 100644 index 0000000000..a3aac30c73 --- /dev/null +++ b/bsp/nuvoton/libraries/ma35/Device/Nuvoton/MA35D1/Include/ks_reg.h @@ -0,0 +1,473 @@ +/**************************************************************************//** + * @file ks_reg.h + * @brief Key Store register definition header file + * + * SPDX-License-Identifier: Apache-2.0 + * @copyright (C) 2021 Nuvoton Technology Corp. All rights reserved. + *****************************************************************************/ +#ifndef __KS_REG_H__ +#define __KS_REG_H__ + +#if defined ( __CC_ARM ) + #pragma anon_unions +#endif + +/** + @addtogroup REGISTER Control Register + @{ +*/ + +/*---------------------- Key Store -------------------------*/ +/** + @addtogroup KS Key Store(KS) + Memory Mapped Structure for KS Controller +@{ */ + +typedef struct +{ + + + /** + * @var KS_T::CTL + * Offset: 0x00 Key Store Control Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[0] |START |Key Store Start Control Bit + * | | |0 = No operation. + * | | |1 = Start the operation. + * |[3:1] |OPMODE |Key Store Operation Mode + * | | |000 = Read operation. + * | | |001 = Create operation. + * | | |010 = Erase one key operation. + * | | |011 = Erase all keys operation (only for SRAM). + * | | |100 = Revoke key operation. + * | | |101 = Data Remanence prevention operation (only for SRAM). + * | | |Others = reserved. + * |[7] |CONT |Read/Write Key Continue Bit + * | | |0 = Read/Write key operation is not continuous to previous operation. + * | | |1 = Read/Write key operation is continuous to previous operation. + * |[8] |INIT |Key Store Initialization + * | | |User should check BUSY(KS_STS[2]) is 0, and then write 1 to this bit and START(KS_CTL[0[), Key Store will start initialization. + * | | |After the Key Store is initialized, INIT will be cleared. + * |[10] |SILENT |Silent Access Enable Bit + * | | |0 = Silent access Disabled. + * | | |1 = Silent access Enabled. + * |[11] |SCMB |Data Scramble Enable Bit + * | | |0 = Data scramble Disabled. + * | | |1 = Data scramble Enabled. + * |[14] |TCLR |Tamper Event Clear Control Bit + * | | |0 = Key Store does not clear all keys at SRAM and revoke all OTP keys when tamper event occurs. + * | | |1 = Key Store clears all keys at SRAM and revoke all OTP keys when tamper event occurs. + * |[15] |IEN |Key Store Interrupt Enable Bit + * | | |0 = Key Store interrupt Disabled. + * | | |1 = Key Store interrupt Enabled. + * @var KS_T::METADATA + * Offset: 0x04 Key Store Metadata Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[0] |SEC |Secure Key Selection Bit + * | | |0 = Set key as the non-secure key. + * | | |1 = Set key as the secure key. + * |[2] |READABLE |Key Readable Control Bit + * | | |0 = key is un-readable. + * | | |1 = key is readable. + * |[3] |RVK |Key Revoke Control Bit + * | | |0 = Key current selected will not be changed. + * | | |1 = key current selected will be change to revoked state. + * |[4] |BS |Booting State Selection Bit + * | | |0 = Set key used at all state. + * | | |1 = Set key used at boot loader state 1 (BL1 state). + * |[12:8] |SIZE |Key Size Selection Bits + * | | |00000 = 128 bits. + * | | |00001 = 163 bits. + * | | |00010 = 192 bits. + * | | |00011 = 224 bits. + * | | |00100 = 233 bits. + * | | |00101 = 255 bits. + * | | |00110 = 256 bits. + * | | |00111 = 283 bits. + * | | |01000 = 384 bits. + * | | |01001 = 409 bits. + * | | |01010 = 512 bits. + * | | |01011 = 521 bits. + * | | |01100 = 571 bits. + * | | |10000 = 1024 bits. + * | | |10001 = 1536 bits. + * | | |10010 = 2048 bits. + * | | |10011 = 3072 bits. + * | | |10100 = 4096 bits. + * | | |Others = reserved. + * |[18:16] |OWNER |Key Owner Selection Bits + * | | |000 = AES. + * | | |001 = HMAC. + * | | |010 = RSA exponent blind key for SCAP(CRYPTO_RSA_CTL[8]) = 1 and CRT(CRYPTO_RSA_CTL[2]) = 0 . + * | | |011 = RSA middle data, p, q and private key. + * | | |100 = ECC. + * | | |101 = CPU. + * | | |Others = reserved. + * |[25:20] |NUMBER |Key Number + * | | |Before read or erase one key operation is started, user should write the key number to be operated + * | | |When create operation is finished, user can read these bits to get its key number. + * |[31:30] |DST |Key Location Selection Bits + * | | |00 = Key is in SRAM. + * | | |10 = Key is in OTP. + * | | |Others = reserved. + * @var KS_T::STS + * Offset: 0x08 Key Store Status Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[0] |IF |Key Store Finish Interrupt Flag (Write 1 to Clear) + * | | |This bit is cleared by writing 1 and it has no effect by writing 0. + * | | |0 = No Key Store interrupt. + * | | |1 = Key Store operation done interrupt. + * |[1] |EIF |Key Store Error Flag (Write 1 to Clear) + * | | |This bit is cleared by writing 1 and it has no effect by writing 0. + * | | |0 = No Key Store error. + * | | |1 = Key Store error interrupt. + * |[2] |BUSY |Key Store Busy Flag (Read Only) + * | | |0 = Key Store is idle or finished. + * | | |1 = Key Store is busy. + * |[3] |SRAMFULL |Key Storage at SRAM Full Status Bit (Read Only) + * | | |0 = Key Storage at SRAM is not full. + * | | |1 = Key Storage at SRAM is full. + * |[7] |INITDONE |Key Store Initialization Done Status (Read Only) + * | | |0 = Key Store is un-initialized. + * | | |1 = Key Store is initialized. + * |[8] |RAMINV |Key Store SRAM Invert Status (Read Only) + * | | |0 = Key Store key in SRAM is normal. + * | | |1 = Key Store key in SRAM is inverted. + * @var KS_T::REMAIN + * Offset: 0x0C Key Store Remaining Space Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[12:0] |RRMNG |Key Store SRAM Remaining Space + * | | |The RRMNG shows the remaining byte count space of SRAM + * @var KS_T::SCMBKEY0 + * Offset: 0x10 Key Store Scramble Key Word 0 Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[31:0] |SCMBKEY |Key Store Scramble Key + * | | |When SCMB(KS_CTL[]) is set to 1, user should write the scramble key in this register before new key stores in Key Store + * | | |If user does not write the scramble key in this register, the Key Store will use previous scramble key to execute data scramble function. + * @var KS_T::SCMBKEY1 + * Offset: 0x14 Key Store Scramble Key Word 1 Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[31:0] |SCMBKEY |Key Store Scramble Key + * | | |When SCMB(KS_CTL[]) is set to 1, user should write the scramble key in this register before new key stores in Key Store + * | | |If user does not write the scramble key in this register, the Key Store will use previous scramble key to execute data scramble function. + * @var KS_T::SCMBKEY2 + * Offset: 0x18 Key Store Scramble Key Word 2 Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[31:0] |SCMBKEY |Key Store Scramble Key + * | | |When SCMB(KS_CTL[]) is set to 1, user should write the scramble key in this register before new key stores in Key Store + * | | |If user does not write the scramble key in this register, the Key Store will use previous scramble key to execute data scramble function. + * @var KS_T::SCMBKEY3 + * Offset: 0x1C Key Store Scramble Key Word 3 Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[31:0] |SCMBKEY |Key Store Scramble Key + * | | |When SCMB(KS_CTL[]) is set to 1, user should write the scramble key in this register before new key stores in Key Store + * | | |If user does not write the scramble key in this register, the Key Store will use previous scramble key to execute data scramble function. + * @var KS_T::KEY0 + * Offset: 0x20 Key Store Entry Key Word 0 Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[31:0] |KEY |Key Data (Read/Write, Read to Clear) + * | | |These registers will be cleared if Key Store executes the write operation or CPU completes the reading key. + * @var KS_T::KEY1 + * Offset: 0x24 Key Store Entry Key Word 1 Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[31:0] |KEY |Key Data (Read/Write, Read to Clear) + * | | |These registers will be cleared if Key Store executes the write operation or CPU completes the reading key. + * @var KS_T::KEY2 + * Offset: 0x28 Key Store Entry Key Word 2 Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[31:0] |KEY |Key Data (Read/Write, Read to Clear) + * | | |These registers will be cleared if Key Store executes the write operation or CPU completes the reading key. + * @var KS_T::KEY3 + * Offset: 0x2C Key Store Entry Key Word 3 Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[31:0] |KEY |Key Data (Read/Write, Read to Clear) + * | | |These registers will be cleared if Key Store executes the write operation or CPU completes the reading key. + * @var KS_T::KEY4 + * Offset: 0x30 Key Store Entry Key Word 4 Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[31:0] |KEY |Key Data (Read/Write, Read to Clear) + * | | |These registers will be cleared if Key Store executes the write operation or CPU completes the reading key. + * @var KS_T::KEY5 + * Offset: 0x34 Key Store Entry Key Word 5 Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[31:0] |KEY |Key Data (Read/Write, Read to Clear) + * | | |These registers will be cleared if Key Store executes the write operation or CPU completes the reading key. + * @var KS_T::KEY6 + * Offset: 0x38 Key Store Entry Key Word 6 Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[31:0] |KEY |Key Data (Read/Write, Read to Clear) + * | | |These registers will be cleared if Key Store executes the write operation or CPU completes the reading key. + * @var KS_T::KEY7 + * Offset: 0x3C Key Store Entry Key Word 7 Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[31:0] |KEY |Key Data (Read/Write, Read to Clear) + * | | |These registers will be cleared if Key Store executes the write operation or CPU completes the reading key. + * @var KS_T::OTPSTS + * Offset: 0x40 Key Store OTP Keys Status Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[0] |KEY0 |OTP Key 0 Used Status + * | | |0 = OTP key 0 is unused. + * | | |1 = OTP key 0 is used. + * | | |Note: When chip is in RMA stage, this bit will be set to 1 and key is revoked after initialization if key is existed. + * |[1] |KEY1 |OTP Key 1 Used Status + * | | |0 = OTP key 1 is unused. + * | | |1 = OTP key 1 is used. + * | | |Note: When chip is in RMA stage, this bit will be set to 1 and key is revoked after initialization if key is existed. + * |[2] |KEY2 |OTP Key 2 Used Status + * | | |0 = OTP key 2 is unused. + * | | |1 = OTP key 2 is used. + * | | |Note: When chip is in RMA stage, this bit will be set to 1 and key is revoked after initialization if key is existed. + * |[3] |KEY3 |OTP Key 3 Used Status + * | | |0 = OTP key 3 is unused. + * | | |1 = OTP key 3 is used. + * | | |Note: When chip is in RMA stage, this bit will be set to 1 and key is revoked after initialization if key is existed. + * |[4] |KEY4 |OTP Key 4 Used Status + * | | |0 = OTP key 4 is unused. + * | | |1 = OTP key 4 is used. + * | | |Note: When chip is in RMA stage, this bit will be set to 1 and key is revoked after initialization if key is existed. + * |[5] |KEY5 |OTP Key 5 Used Status + * | | |0 = OTP key 5 is unused. + * | | |1 = OTP key 5 is used. + * | | |Note: When chip is in RMA stage, this bit will be set to 1 and key is revoked after initialization if key is existed. + * |[6] |KEY6 |OTP Key 6 Used Status + * | | |0 = OTP key 6 is unused. + * | | |1 = OTP key 6 is used. + * | | |Note: When chip is in RMA stage, this bit will be set to 1 and key is revoked after initialization if key is existed. + * |[7] |KEY7 |OTP Key 7 Used Status + * | | |0 = OTP key 7 is unused. + * | | |1 = OTP key 7 is used. + * | | |Note: When chip is in RMA stage, this bit will be set to 1 and key is revoked after initialization if key is existed. + * |[8] |KEY8 |OTP Key 8 Used Status + * | | |0 = OTP key 8 is unused. + * | | |1 = OTP key 8 is used. + * | | |Note: When chip is in RMA stage, this bit will be set to 1 and key is revoked after initialization if key is existed. + * @var KS_T::REMKCNT + * Offset: 0x44 Key Store Remaining Key Count Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[5:0] |RRMKCNT |Key Store SRAM Remaining Key Count + * | | |The RRMKCNT shows the remaining key count for SRAM. + */ + __IO uint32_t CTL; /*!< [0x0000] Key Store Control Register */ + __IO uint32_t METADATA; /*!< [0x0004] Key Store Metadata Register */ + __IO uint32_t STS; /*!< [0x0008] Key Store Status Register */ + __I uint32_t REMAIN; /*!< [0x000c] Key Store Remaining Space Register */ + __IO uint32_t SCMBKEY0; /*!< [0x0010] Key Store Scramble Key Word 0 Register */ + __IO uint32_t SCMBKEY1; /*!< [0x0014] Key Store Scramble Key Word 1 Register */ + __IO uint32_t SCMBKEY2; /*!< [0x0018] Key Store Scramble Key Word 2 Register */ + __IO uint32_t SCMBKEY3; /*!< [0x001c] Key Store Scramble Key Word 3 Register */ + __IO uint32_t KEY0; /*!< [0x0020] Key Store Entry Key Word 0 Register */ + __IO uint32_t KEY1; /*!< [0x0024] Key Store Entry Key Word 1 Register */ + __IO uint32_t KEY2; /*!< [0x0028] Key Store Entry Key Word 2 Register */ + __IO uint32_t KEY3; /*!< [0x002c] Key Store Entry Key Word 3 Register */ + __IO uint32_t KEY4; /*!< [0x0030] Key Store Entry Key Word 4 Register */ + __IO uint32_t KEY5; /*!< [0x0034] Key Store Entry Key Word 5 Register */ + __IO uint32_t KEY6; /*!< [0x0038] Key Store Entry Key Word 6 Register */ + __IO uint32_t KEY7; /*!< [0x003c] Key Store Entry Key Word 7 Register */ + __I uint32_t OTPSTS; /*!< [0x0040] Key Store OTP Keys Status Register */ + __I uint32_t REMKCNT; /*!< [0x0044] Key Store Remaining Key Count Register */ +} KS_T; + +typedef struct +{ + __IO uint32_t CTL; /*!< [0x0000] Key Store Control Register */ + __IO uint32_t METADATA; /*!< [0x0004] Key Store Metadata Register */ + __IO uint32_t STS; /*!< [0x0008] Key Store Status Register */ + __I uint32_t REMAIN; /*!< [0x000c] Key Store Remaining Space Register */ + __I uint32_t RESERVE0[4]; + __IO uint32_t KEY0; /*!< [0x0020] Key Store Entry Key Word 0 Register */ + __IO uint32_t KEY1; /*!< [0x0024] Key Store Entry Key Word 1 Register */ + __IO uint32_t KEY2; /*!< [0x0028] Key Store Entry Key Word 2 Register */ + __IO uint32_t KEY3; /*!< [0x002c] Key Store Entry Key Word 3 Register */ + __IO uint32_t KEY4; /*!< [0x0030] Key Store Entry Key Word 4 Register */ + __IO uint32_t KEY5; /*!< [0x0034] Key Store Entry Key Word 5 Register */ + __IO uint32_t KEY6; /*!< [0x0038] Key Store Entry Key Word 6 Register */ + __IO uint32_t KEY7; /*!< [0x003c] Key Store Entry Key Word 7 Register */ + __I uint32_t OTPSTS; /*!< [0x0040] Key Store OTP Keys Status Register */ + __I uint32_t REMKCNT; /*!< [0x0044] Key Store Remaining Key Count Register */ +} NS_KS_T; + +/** + @addtogroup KS_CONST KS Bit Field Definition + Constant Definitions for KS Controller +@{ */ + +#define KS_CTL_START_Pos (0) /*!< KS_T::CTL: START Position */ +#define KS_CTL_START_Msk (0x1ul << KS_CTL_START_Pos) /*!< KS_T::CTL: START Mask */ + +#define KS_CTL_OPMODE_Pos (1) /*!< KS_T::CTL: OPMODE Position */ +#define KS_CTL_OPMODE_Msk (0x7ul << KS_CTL_OPMODE_Pos) /*!< KS_T::CTL: OPMODE Mask */ + +#define KS_CTL_CONT_Pos (7) /*!< KS_T::CTL: CONT Position */ +#define KS_CTL_CONT_Msk (0x1ul << KS_CTL_CONT_Pos) /*!< KS_T::CTL: CONT Mask */ + +#define KS_CTL_INIT_Pos (8) /*!< KS_T::CTL: INIT Position */ +#define KS_CTL_INIT_Msk (0x1ul << KS_CTL_INIT_Pos) /*!< KS_T::CTL: INIT Mask */ + +#define KS_CTL_SILENT_Pos (10) /*!< KS_T::CTL: SILENT Position */ +#define KS_CTL_SILENT_Msk (0x1ul << KS_CTL_SILENT_Pos) /*!< KS_T::CTL: SILENT Mask */ + +#define KS_CTL_SCMB_Pos (11) /*!< KS_T::CTL: SCMB Position */ +#define KS_CTL_SCMB_Msk (0x1ul << KS_CTL_SCMB_Pos) /*!< KS_T::CTL: SCMB Mask */ + +#define KS_CTL_TCLR_Pos (14) /*!< KS_T::CTL: TCLR Position */ +#define KS_CTL_TCLR_Msk (0x1ul << KS_CTL_TCLR_Pos) /*!< KS_T::CTL: TCLR Mask */ + +#define KS_CTL_IEN_Pos (15) /*!< KS_T::CTL: IEN Position */ +#define KS_CTL_IEN_Msk (0x1ul << KS_CTL_IEN_Pos) /*!< KS_T::CTL: IEN Mask */ + +#define KS_METADATA_SEC_Pos (0) /*!< KS_T::METADATA: SEC Position */ +#define KS_METADATA_SEC_Msk (0x1ul << KS_METADATA_SEC_Pos) /*!< KS_T::METADATA: SEC Mask */ + +#define KS_METADATA_READABLE_Pos (2) /*!< KS_T::METADATA: READABLE Position */ +#define KS_METADATA_READABLE_Msk (0x1ul << KS_METADATA_READABLE_Pos) /*!< KS_T::METADATA: READABLE Mask */ + +#define KS_METADATA_RVK_Pos (3) /*!< KS_T::METADATA: RVK Position */ +#define KS_METADATA_RVK_Msk (0x1ul << KS_METADATA_RVK_Pos) /*!< KS_T::METADATA: RVK Mask */ + +#define KS_METADATA_BS_Pos (4) /*!< KS_T::METADATA: BS Position */ +#define KS_METADATA_BS_Msk (0x1ul << KS_METADATA_BS_Pos) /*!< KS_T::METADATA: BS Mask */ + +#define KS_METADATA_SIZE_Pos (8) /*!< KS_T::METADATA: SIZE Position */ +#define KS_METADATA_SIZE_Msk (0x1ful << KS_METADATA_SIZE_Pos) /*!< KS_T::METADATA: SIZE Mask */ + +#define KS_METADATA_OWNER_Pos (16) /*!< KS_T::METADATA: OWNER Position */ +#define KS_METADATA_OWNER_Msk (0x7ul << KS_METADATA_OWNER_Pos) /*!< KS_T::METADATA: OWNER Mask */ + +#define KS_METADATA_NUMBER_Pos (20) /*!< KS_T::METADATA: NUMBER Position */ +#define KS_METADATA_NUMBER_Msk (0x3ful << KS_METADATA_NUMBER_Pos) /*!< KS_T::METADATA: NUMBER Mask */ + +#define KS_METADATA_DST_Pos (30) /*!< KS_T::METADATA: DST Position */ +#define KS_METADATA_DST_Msk (0x3ul << KS_METADATA_DST_Pos) /*!< KS_T::METADATA: DST Mask */ + +#define KS_STS_IF_Pos (0) /*!< KS_T::STS: IF Position */ +#define KS_STS_IF_Msk (0x1ul << KS_STS_IF_Pos) /*!< KS_T::STS: IF Mask */ + +#define KS_STS_EIF_Pos (1) /*!< KS_T::STS: EIF Position */ +#define KS_STS_EIF_Msk (0x1ul << KS_STS_EIF_Pos) /*!< KS_T::STS: EIF Mask */ + +#define KS_STS_BUSY_Pos (2) /*!< KS_T::STS: BUSY Position */ +#define KS_STS_BUSY_Msk (0x1ul << KS_STS_BUSY_Pos) /*!< KS_T::STS: BUSY Mask */ + +#define KS_STS_SRAMFULL_Pos (3) /*!< KS_T::STS: SRAMFULL Position */ +#define KS_STS_SRAMFULL_Msk (0x1ul << KS_STS_SRAMFULL_Pos) /*!< KS_T::STS: SRAMFULL Mask */ + +#define KS_STS_INITDONE_Pos (7) /*!< KS_T::STS: INITDONE Position */ +#define KS_STS_INITDONE_Msk (0x1ul << KS_STS_INITDONE_Pos) /*!< KS_T::STS: INITDONE Mask */ + +#define KS_STS_RAMINV_Pos (8) /*!< KS_T::STS: RAMINV Position */ +#define KS_STS_RAMINV_Msk (0x1ul << KS_STS_RAMINV_Pos) /*!< KS_T::STS: RAMINV Mask */ + +#define KS_REMAIN_RRMNG_Pos (0) /*!< KS_T::REMAIN: RRMNG Position */ +#define KS_REMAIN_RRMNG_Msk (0x1ffful << KS_REMAIN_RRMNG_Pos) /*!< KS_T::REMAIN: RRMNG Mask */ + +#define KS_SCMBKEY0_SCMBKEY_Pos (0) /*!< KS_T::SCMBKEY0: SCMBKEY Position */ +#define KS_SCMBKEY0_SCMBKEY_Msk (0xfffffffful << KS_SCMBKEY0_SCMBKEY_Pos) /*!< KS_T::SCMBKEY0: SCMBKEY Mask */ + +#define KS_SCMBKEY1_SCMBKEY_Pos (0) /*!< KS_T::SCMBKEY1: SCMBKEY Position */ +#define KS_SCMBKEY1_SCMBKEY_Msk (0xfffffffful << KS_SCMBKEY1_SCMBKEY_Pos) /*!< KS_T::SCMBKEY1: SCMBKEY Mask */ + +#define KS_SCMBKEY2_SCMBKEY_Pos (0) /*!< KS_T::SCMBKEY2: SCMBKEY Position */ +#define KS_SCMBKEY2_SCMBKEY_Msk (0xfffffffful << KS_SCMBKEY2_SCMBKEY_Pos) /*!< KS_T::SCMBKEY2: SCMBKEY Mask */ + +#define KS_SCMBKEY3_SCMBKEY_Pos (0) /*!< KS_T::SCMBKEY3: SCMBKEY Position */ +#define KS_SCMBKEY3_SCMBKEY_Msk (0xfffffffful << KS_SCMBKEY3_SCMBKEY_Pos) /*!< KS_T::SCMBKEY3: SCMBKEY Mask */ + +#define KS_KEY0_KEY_Pos (0) /*!< KS_T::KEY0: KEY Position */ +#define KS_KEY0_KEY_Msk (0xfffffffful << KS_KEY0_KEY_Pos) /*!< KS_T::KEY0: KEY Mask */ + +#define KS_KEY1_KEY_Pos (0) /*!< KS_T::KEY1: KEY Position */ +#define KS_KEY1_KEY_Msk (0xfffffffful << KS_KEY1_KEY_Pos) /*!< KS_T::KEY1: KEY Mask */ + +#define KS_KEY2_KEY_Pos (0) /*!< KS_T::KEY2: KEY Position */ +#define KS_KEY2_KEY_Msk (0xfffffffful << KS_KEY2_KEY_Pos) /*!< KS_T::KEY2: KEY Mask */ + +#define KS_KEY3_KEY_Pos (0) /*!< KS_T::KEY3: KEY Position */ +#define KS_KEY3_KEY_Msk (0xfffffffful << KS_KEY3_KEY_Pos) /*!< KS_T::KEY3: KEY Mask */ + +#define KS_KEY4_KEY_Pos (0) /*!< KS_T::KEY4: KEY Position */ +#define KS_KEY4_KEY_Msk (0xfffffffful << KS_KEY4_KEY_Pos) /*!< KS_T::KEY4: KEY Mask */ + +#define KS_KEY5_KEY_Pos (0) /*!< KS_T::KEY5: KEY Position */ +#define KS_KEY5_KEY_Msk (0xfffffffful << KS_KEY5_KEY_Pos) /*!< KS_T::KEY5: KEY Mask */ + +#define KS_KEY6_KEY_Pos (0) /*!< KS_T::KEY6: KEY Position */ +#define KS_KEY6_KEY_Msk (0xfffffffful << KS_KEY6_KEY_Pos) /*!< KS_T::KEY6: KEY Mask */ + +#define KS_KEY7_KEY_Pos (0) /*!< KS_T::KEY7: KEY Position */ +#define KS_KEY7_KEY_Msk (0xfffffffful << KS_KEY7_KEY_Pos) /*!< KS_T::KEY7: KEY Mask */ + +#define KS_OTPSTS_KEY0_Pos (0) /*!< KS_T::OTPSTS: KEY0 Position */ +#define KS_OTPSTS_KEY0_Msk (0x1ul << KS_OTPSTS_KEY0_Pos) /*!< KS_T::OTPSTS: KEY0 Mask */ + +#define KS_OTPSTS_KEY1_Pos (1) /*!< KS_T::OTPSTS: KEY1 Position */ +#define KS_OTPSTS_KEY1_Msk (0x1ul << KS_OTPSTS_KEY1_Pos) /*!< KS_T::OTPSTS: KEY1 Mask */ + +#define KS_OTPSTS_KEY2_Pos (2) /*!< KS_T::OTPSTS: KEY2 Position */ +#define KS_OTPSTS_KEY2_Msk (0x1ul << KS_OTPSTS_KEY2_Pos) /*!< KS_T::OTPSTS: KEY2 Mask */ + +#define KS_OTPSTS_KEY3_Pos (3) /*!< KS_T::OTPSTS: KEY3 Position */ +#define KS_OTPSTS_KEY3_Msk (0x1ul << KS_OTPSTS_KEY3_Pos) /*!< KS_T::OTPSTS: KEY3 Mask */ + +#define KS_OTPSTS_KEY4_Pos (4) /*!< KS_T::OTPSTS: KEY4 Position */ +#define KS_OTPSTS_KEY4_Msk (0x1ul << KS_OTPSTS_KEY4_Pos) /*!< KS_T::OTPSTS: KEY4 Mask */ + +#define KS_OTPSTS_KEY5_Pos (5) /*!< KS_T::OTPSTS: KEY5 Position */ +#define KS_OTPSTS_KEY5_Msk (0x1ul << KS_OTPSTS_KEY5_Pos) /*!< KS_T::OTPSTS: KEY5 Mask */ + +#define KS_OTPSTS_KEY6_Pos (6) /*!< KS_T::OTPSTS: KEY6 Position */ +#define KS_OTPSTS_KEY6_Msk (0x1ul << KS_OTPSTS_KEY6_Pos) /*!< KS_T::OTPSTS: KEY6 Mask */ + +#define KS_OTPSTS_KEY7_Pos (7) /*!< KS_T::OTPSTS: KEY7 Position */ +#define KS_OTPSTS_KEY7_Msk (0x1ul << KS_OTPSTS_KEY7_Pos) /*!< KS_T::OTPSTS: KEY7 Mask */ + +#define KS_OTPSTS_KEY8_Pos (8) /*!< KS_T::OTPSTS: KEY8 Position */ +#define KS_OTPSTS_KEY8_Msk (0x1ul << KS_OTPSTS_KEY8_Pos) /*!< KS_T::OTPSTS: KEY8 Mask */ + +#define KS_REMKCNT_RRMKCNT_Pos (0) /*!< KS_T::REMKCNT: RRMKCNT Position */ +#define KS_REMKCNT_RRMKCNT_Msk (0x3ful << KS_REMKCNT_RRMKCNT_Pos) /*!< KS_T::REMKCNT: RRMKCNT Mask */ + +/**@}*/ /* KS_CONST */ +/**@}*/ /* end of KS register group */ +/**@}*/ /* end of REGISTER group */ + +#if defined ( __CC_ARM ) + #pragma no_anon_unions +#endif + +#endif /* __KS_REG_H__ */ diff --git a/bsp/nuvoton/libraries/ma35/Device/Nuvoton/MA35D1/Include/ma35d1.h b/bsp/nuvoton/libraries/ma35/Device/Nuvoton/MA35D1/Include/ma35d1.h new file mode 100644 index 0000000000..0481d1ee39 --- /dev/null +++ b/bsp/nuvoton/libraries/ma35/Device/Nuvoton/MA35D1/Include/ma35d1.h @@ -0,0 +1,1050 @@ +/**************************************************************************//** + * @file ma35d1.h + * @brief Peripheral access layer header file. + * This file contains all the peripheral register's definitions + * and bits definitions and memory mapping. + * + * SPDX-License-Identifier: Apache-2.0 + * @copyright (C) 2020 Nuvoton Technology Corp. All rights reserved. + *****************************************************************************/ +/** + \mainpage NuMicro MA35D1 Driver Reference Guide + * + * Introduction + * + * This user manual describes the usage of MA35D1 device driver + * + * Disclaimer + * + * The Software is furnished "AS IS", without warranty as to performance or results, and + * the entire risk as to performance or results is assumed by YOU. Nuvoton disclaims all + * warranties, express, implied or otherwise, with regard to the Software, its use, or + * operation, including without limitation any and all warranties of merchantability, fitness + * for a particular purpose, and non-infringement of intellectual property rights. + * + * Important Notice + * + * Nuvoton Products are neither intended nor warranted for usage in systems or equipment, + * any malfunction or failure of which may cause loss of human life, bodily injury or severe + * property damage. Such applications are deemed, "Insecure Usage". + * + * Insecure usage includes, but is not limited to: equipment for surgical implementation, + * atomic energy control instruments, airplane or spaceship instruments, the control or + * operation of dynamic, brake or safety systems designed for vehicular use, traffic signal + * instruments, all types of safety devices, and other applications intended to support or + * sustain life. + * + * All Insecure Usage shall be made at customer's risk, and in the event that third parties + * lay claims to Nuvoton as a result of customer's Insecure Usage, customer shall indemnify + * the damages and liabilities thus incurred by Nuvoton. + * + * Please note that all data and specifications are subject to change without notice. All the + * trademarks of products and companies mentioned in this datasheet belong to their respective + * owners. + * + * Copyright Notice + * + * Copyright (C) 2021 Nuvoton Technology Corp. All rights reserved. + */ +#ifndef __MA35D1_H__ +#define __MA35D1_H__ + +#include "rtconfig.h" + +#ifdef __cplusplus +extern "C" { +#endif + +/******************************************************************************/ +/* Processor and Core Peripherals */ +/******************************************************************************/ +/** @addtogroup CMSIS_Device Device CMSIS Definitions + Configuration of the Cortex-M4 Processor and Core Peripherals + @{ +*/ + +/** + * @details Interrupt Number Definition. + */ +#if defined(USE_MA35D1_SUBM) +typedef enum IRQn +{ + /****** Cortex-M4 Processor Exceptions Numbers *************************************************/ + NonMaskableInt_IRQn = -14, /*!< 2 Non Maskable Interrupt */ + MemoryManagement_IRQn = -12, /*!< 4 Memory Management Interrupt */ + BusFault_IRQn = -11, /*!< 5 Bus Fault Interrupt */ + UsageFault_IRQn = -10, /*!< 6 Usage Fault Interrupt */ + SVCall_IRQn = -5, /*!< 11 SV Call Interrupt */ + DebugMonitor_IRQn = -4, /*!< 12 Debug Monitor Interrupt */ + PendSV_IRQn = -2, /*!< 14 Pend SV Interrupt */ + SysTick_IRQn = -1, /*!< 15 System Tick Interrupt */ + + /****** ma35d_rtp Specific Interrupt Numbers **************************************************/ + + LVD_IRQn = 0, + PWRWU_IRQn = 2, + HWSEM0_IRQn = 3, + CKFAIL_IRQn = 4, + WHC0_IRQn = 5, + RTC_IRQn = 6, + TAMPER_IRQn = 7, + WDT2_IRQn = 8, + WWDT2_IRQn = 9, + EINT0_IRQn = 10, + EINT1_IRQn = 11, + EINT2_IRQn = 12, + EINT3_IRQn = 13, + GPA_IRQn = 16, + GPB_IRQn = 17, + GPC_IRQn = 18, + GPD_IRQn = 19, + TMR2_IRQn = 22, + TMR3_IRQn = 23, + BRAKE0_IRQn = 24, + EPWM0P0_IRQn = 25, + EPWM0P1_IRQn = 26, + EPWM0P2_IRQn = 27, + QEI0_IRQn = 28, + ECAP0_IRQn = 29, + QSPI1_IRQn = 31, + UART1_IRQn = 35, + UART2_IRQn = 36, + UART3_IRQn = 37, + UART4_IRQn = 38, + UART5_IRQn = 39, + EADC00_IRQn = 40, + EADC01_IRQn = 41, + EADC02_IRQn = 42, + EADC03_IRQn = 43, + I2C1_IRQn = 45, + I2S0_IRQn = 46, + CANFD00_IRQn = 47, + SC0_IRQn = 48, + GPE_IRQn = 49, + GPF_IRQn = 50, + GPG_IRQn = 51, + GPH_IRQn = 52, + GPI_IRQn = 53, + GPJ_IRQn = 54, + TMR4_IRQn = 55, + TMR5_IRQn = 56, + TMR6_IRQn = 57, + TMR7_IRQn = 58, + BRAKE1_IRQn = 59, + EPWM1P0_IRQn = 60, + EPWM1P1_IRQn = 61, + EPWM1P2_IRQn = 62, + QEI1_IRQn = 63, + ECAP1_IRQn = 64, + SPI0_IRQn = 65, + SPI1_IRQn = 66, + PDMA2_IRQn = 67, + PDMA3_IRQn = 68, + UART6_IRQn = 69, + UART7_IRQn = 70, + UART8_IRQn = 71, + UART9_IRQn = 72, + UART10_IRQn = 73, + UART11_IRQn = 74, + I2C2_IRQn = 75, + I2C3_IRQn = 76, + I2S1_IRQn = 77, + CANFD10_IRQn = 78, + SC1_IRQn = 79, + GPK_IRQn = 80, + GPL_IRQn = 81, + GPM_IRQn = 82, + GPN_IRQn = 83, + TMR8_IRQn = 84, + TMR9_IRQn = 85, + TMR10_IRQn = 86, + TMR11_IRQn = 87, + BRAKE2_IRQn = 88, + EPWM2P0_IRQn = 89, + EPWM2P1_IRQn = 90, + EPWM2P2_IRQn = 91, + QEI2_IRQn = 92, + ECAP2_IRQn = 93, + SPI2_IRQn = 94, + SPI3_IRQn = 95, + UART12_IRQn = 96, + UART13_IRQn = 97, + UART14_IRQn = 98, + UART15_IRQn = 99, + UART16_IRQn = 100, + I2C4_IRQn = 101, + I2C5_IRQn = 102, + CANFD20_IRQn = 103, + CANFD30_IRQn = 104, + KPI_IRQn = 105, + CANFD01_IRQn = 106, + CANFD11_IRQn = 107, + CANFD21_IRQn = 108, + CANFD31_IRQn = 109, + ADC0_IRQn = 110, + IRQn_Max = 128, +} +IRQn_Type; + +/* Configuration of the Cortex-M4 Processor and Core Peripherals */ +#define __CM4_REV 0x0201U /*!< Core Revision r2p1 */ +#define __NVIC_PRIO_BITS 4U /*!< Number of Bits used for Priority Levels */ +#define __Vendor_SysTickConfig 0U /*!< Set to 1 if different SysTick Config is used */ +#define __MPU_PRESENT 1U /*!< MPU present or not */ +#ifdef __FPU_PRESENT +#undef __FPU_PRESENT +#define __FPU_PRESENT 1U /*!< FPU present or not */ +#else +#define __FPU_PRESENT 1U /*!< FPU present or not */ +#endif + +/*@}*/ /* end of group CMSIS_Device */ + + +#include "core_cm4.h" /* Cortex-M4 processor and core peripherals */ +#include "system_ma35d1.h" /* System include file */ +#include + +#else + +typedef enum IRQn +{ + /****** SGI Interrupts Numbers ************************************************/ + SGI0_IRQn = 0, /*!< Software Generated Interrupt 0 */ + SGI1_IRQn = 1, /*!< Software Generated Interrupt 1 */ + SGI2_IRQn = 2, /*!< Software Generated Interrupt 2 */ + SGI3_IRQn = 3, /*!< Software Generated Interrupt 3 */ + SGI4_IRQn = 4, /*!< Software Generated Interrupt 4 */ + SGI5_IRQn = 5, /*!< Software Generated Interrupt 5 */ + SGI6_IRQn = 6, /*!< Software Generated Interrupt 6 */ + SGI7_IRQn = 7, /*!< Software Generated Interrupt 7 */ + SGI8_IRQn = 8, /*!< Software Generated Interrupt 8 */ + SGI9_IRQn = 9, /*!< Software Generated Interrupt 9 */ + SGI10_IRQn = 10, /*!< Software Generated Interrupt 10 */ + SGI11_IRQn = 11, /*!< Software Generated Interrupt 11 */ + SGI12_IRQn = 12, /*!< Software Generated Interrupt 12 */ + SGI13_IRQn = 13, /*!< Software Generated Interrupt 13 */ + SGI14_IRQn = 14, /*!< Software Generated Interrupt 14 */ + SGI15_IRQn = 15, /*!< Software Generated Interrupt 15 */ + + /****** Cortex-35 Processor Exceptions Numbers ****************************************/ + VirtualMachine_IRQn = 25, + HypervisorTimer_IRQn = 26, + VirtualTimer_IRQn = 27, + LegacyFIQ_IRQn = 28, + SecPhysicalTimer_IRQn = 29, + NonSecPhysicalTimer_IRQn = 30, + LegacyIRQ_IRQn = 31, + + /****** Platform Exceptions Numbers ***************************************************/ + LVD_IRQn = 32, /*!< Low Voltage detection Interrupt */ + A35PMU_IRQn = 33, /*!< A35 PMU Interrupt */ + HSEM_IRQn = 34, /*!< Hardware Semaphore Interrupt */ + CKFAIL_IRQn = 35, /*!< Clock failed Interrupt */ + WRHO_IRQn = 36, /*!< Wormhole Interrupt */ + RTC_IRQn = 37, /*!< Real Time Clock Interrupt */ + TAMPER_IRQn = 38, /*!< Tamper detection Interrupt */ + WDT0_IRQn = 39, /*!< Watchdog timer 0 Interrupt */ + WWDT0_IRQn = 40, /*!< Window Watchdog timer 0 Interrupt */ + EINT0_IRQn = 41, /*!< External Input 0 Interrupt */ + EINT1_IRQn = 42, /*!< External Input 1 Interrupt */ + EINT2_IRQn = 43, /*!< External Input 2 Interrupt */ + EINT3_IRQn = 44, /*!< External Input 3 Interrupt */ + I2C0_IRQn = 45, /*!< I2C 0 Interrupt */ + GPA_IRQn = 46, /*!< GPIO Port A Interrupt */ + GPB_IRQn = 47, /*!< GPIO Port B Interrupt */ + GPC_IRQn = 48, /*!< GPIO Port C Interrupt */ + GPD_IRQn = 49, /*!< GPIO Port D Interrupt */ + PDMA0_IRQn = 50, /*!< Peripheral DMA 0 Interrupt */ + PDMA1_IRQn = 51, /*!< Peripheral DMA 1 Interrupt */ + DISP_IRQn = 52, /*!< Display Controller (DCUltra) Interrupt */ + CCAP0_IRQn = 53, /*!< CCAP 0 Interrupt */ + CCAP1_IRQn = 54, /*!< CCAP 1 Interrupt */ + GMAC0RX_IRQn = 55, /*!< GMAC0 RX Interrupt */ + GMAC1RX_IRQn = 56, /*!< GMAC1 RX Interrupt */ + SSMCC_IRQn = 57, /*!< SSMCC Interrupt */ + SSPCC_IRQn = 58, /*!< SSPCC Interrupt */ + GFX_IRQn = 59, /*!< GFX GC520L Interrupt (Graphic Engine) */ + VDE_IRQn = 60, /*!< Video Decoder (VC8000) Interrupt */ + WRHO1_IRQn = 61, /*!< WRHO 1 Interrupt */ + SDH0_IRQn = 62, /*!< SDH 0 Interrupt */ + SDH1_IRQn = 63, /*!< SDH 1 Interrupt */ + HSUSBD_IRQn = 64, /*!< USB 2.0 High-Speed Device Interrupt */ + HSUSBH0_IRQn = 65, /*!< USB 2.0 High-Speed Host 0(EHCI) Interrupt */ + HSUSBH1_IRQn = 66, /*!< USB 2.0 High-Speed Host 1(EHCI) Interrupt */ + USBH0_IRQn = 67, /*!< USB 1.1 Host (OHCI) 0 Interrupt (Synopsys) */ + USBH1_IRQn = 68, /*!< USB 1.1 Host (OHCI) 0 Interrupt (Hydra) */ + USBH2_IRQn = 69, /*!< USB 1.1 Host (OHCI) 0 Interrupt (Hydra) */ + NAND_IRQn = 70, /*!< NAND Controller Interrupt */ + CRPT_IRQn = 71, /*!< Crypto Interrupt */ + TRNG_IRQn = 72, /*!< TRNG Interrupt */ + KS_IRQn = 73, /*!< KeyStore Interrupt */ + OTPC_IRQn = 74, /*!< OTP Controller Interrupt */ + WDT1_IRQn = 75, /*!< Watchdog timer 1 Interrupt */ + WWDT1_IRQn = 76, /*!< Window Watchdog timer 1 Interrupt */ + PDMA2_IRQn = 77, /*!< Peripheral DMA 2 Interrupt */ + PDMA3_IRQn = 78, /*!< Peripheral DMA 3 Interrupt */ + TMR0_IRQn = 79, /*!< Timer 0 Interrupt */ + TMR1_IRQn = 80, /*!< Timer 1 Interrupt */ + TMR2_IRQn = 81, /*!< Timer 2 Interrupt */ + TMR3_IRQn = 82, /*!< Timer 3 Interrupt */ + BRAKE0_IRQn = 83, /*!< BRAKE0 Interrupt */ + EPWM0P0_IRQn = 84, /*!< EPWM0P0 Interrupt */ + EPWM0P1_IRQn = 85, /*!< EPWM0P1 Interrupt */ + EPWM0P2_IRQn = 86, /*!< EPWM0P2 Interrupt */ + QEI0_IRQn = 87, /*!< QEI0 Interrupt */ + ECAP0_IRQn = 88, /*!< ECAP0 Interrupt */ + QSPI0_IRQn = 89, /*!< QSPI0 Interrupt */ + QSPI1_IRQn = 90, /*!< QSPI1 Interrupt */ + UART0_IRQn = 91, /*!< UART 0 Interrupt */ + UART1_IRQn = 92, /*!< UART 1 Interrupt */ + UART2_IRQn = 93, /*!< UART 2 Interrupt */ + UART3_IRQn = 94, /*!< UART 3 Interrupt */ + UART4_IRQn = 95, /*!< UART 4 Interrupt */ + UART5_IRQn = 96, /*!< UART 5 Interrupt */ + EADC00_IRQn = 97, /*!< EADC00 Interrupt */ + EADC01_IRQn = 98, /*!< EADC01 Interrupt */ + EADC02_IRQn = 99, /*!< EADC02 Interrupt */ + EADC03_IRQn = 100, /*!< EADC03 Interrupt */ + I2C1_IRQn = 101, /*!< I2C 1 Interrupt */ + I2S0_IRQn = 102, /*!< I2S 0 Interrupt */ + CANFD00_IRQn = 103, /*!< CAN-FD 00 Interrupt */ + SC0_IRQn = 104, /*!< Smart Card 0 Interrupt */ + GPE_IRQn = 105, /*!< GPIO Port E Interrupt */ + GPF_IRQn = 106, /*!< GPIO Port F Interrupt */ + GPG_IRQn = 107, /*!< GPIO Port G Interrupt */ + GPH_IRQn = 108, /*!< GPIO Port H Interrupt */ + GPI_IRQn = 109, /*!< GPIO Port I Interrupt */ + GPJ_IRQn = 110, /*!< GPIO Port J Interrupt */ + KPI_IRQn = 111, /*!< KPI Interrupt */ + ADC0_IRQn = 112, /*!< ADC 0 (Touch Panel ADC) Interrupt */ + TMR4_IRQn = 113, /*!< Timer 4 Interrupt */ + TMR5_IRQn = 114, /*!< Timer 5 Interrupt */ + BRAKE1_IRQn = 115, /*!< BRAKE1 Interrupt */ + EPWM1P0_IRQn = 116, /*!< EPWM1P0 Interrupt */ + EPWM1P1_IRQn = 117, /*!< EPWM1P1 Interrupt */ + EPWM1P2_IRQn = 118, /*!< EPWM1P2 Interrupt */ + QEI1_IRQn = 119, /*!< QEI1 Interrupt */ + ECAP1_IRQn = 120, /*!< ECAP1 Interrupt */ + SPI0_IRQn = 121, /*!< SPI0 Interrupt */ + SPI1_IRQn = 122, /*!< SPI1 Interrupt */ + UART6_IRQn = 123, /*!< UART 6 Interrupt */ + UART7_IRQn = 124, /*!< UART 7 Interrupt */ + UART8_IRQn = 125, /*!< UART 8 Interrupt */ + UART9_IRQn = 126, /*!< UART 9 Interrupt */ + UART10_IRQn = 127, /*!< UART 10 Interrupt */ + UART11_IRQn = 128, /*!< UART 11 Interrupt */ + I2C2_IRQn = 129, /*!< I2C 2 Interrupt */ + I2C3_IRQn = 130, /*!< I2C 3 Interrupt */ + I2S1_IRQn = 131, /*!< I2S 1 Interrupt */ + CANFD10_IRQn = 132, /*!< CAN-FD 10 Interrupt */ + SC1_IRQn = 133, /*!< Smart Card 1 Interrupt */ + GPK_IRQn = 134, /*!< GPIO Port K Interrupt */ + GPL_IRQn = 135, /*!< GPIO Port L Interrupt */ + GPM_IRQn = 136, /*!< GPIO Port M Interrupt */ + GPN_IRQn = 137, /*!< GPIO Port N Interrupt */ + TMR6_IRQn = 138, /*!< Timer 6 Interrupt */ + TMR7_IRQn = 139, /*!< Timer 7 Interrupt */ + TMR8_IRQn = 140, /*!< Timer 8 Interrupt */ + TMR9_IRQn = 141, /*!< Timer 9 Interrupt */ + BRAKE2_IRQn = 142, /*!< BRAKE2 Interrupt */ + EPWM2P0_IRQn = 143, /*!< EPWM2P0 Interrupt */ + EPWM2P1_IRQn = 144, /*!< EPWM2P1 Interrupt */ + EPWM2P2_IRQn = 145, /*!< EPWM2P2 Interrupt */ + QEI2_IRQn = 146, /*!< QEI2 Interrupt */ + ECAP2_IRQn = 147, /*!< ECAP2 Interrupt */ + SPI2_IRQn = 148, /*!< SPI2 Interrupt */ + SPI3_IRQn = 149, /*!< SPI3 Interrupt */ + UART12_IRQn = 150, /*!< UART 12 Interrupt */ + UART13_IRQn = 151, /*!< UART 13 Interrupt */ + UART14_IRQn = 152, /*!< UART 14 Interrupt */ + UART15_IRQn = 153, /*!< UART 15 Interrupt */ + UART16_IRQn = 154, /*!< UART 16 Interrupt */ + I2C4_IRQn = 155, /*!< I2C 4 Interrupt */ + I2C5_IRQn = 156, /*!< I2C 5 Interrupt */ + CANFD20_IRQn = 157, /*!< CAN-FD 20 Interrupt */ + CANFD30_IRQn = 158, /*!< CAN-FD 30 Interrupt */ + TMR10_IRQn = 159, /*!< Timer 10 Interrupt */ + TMR11_IRQn = 160, /*!< Timer 11 Interrupt */ + EMACAXIDLK_IRQn = 161, /*!< EMAC Fabric deadlock Interrupt */ + A35AXIDLK_IRQn = 162, /*!< A35 Fabric deadlock Interrupt */ + CANFD01_IRQn = 163, /*!< CAN-FD 01 Interrupt */ + CANFD11_IRQn = 164, /*!< CAN-FD 11 Interrupt */ + CANFD21_IRQn = 165, /*!< CAN-FD 21 Interrupt */ + CANFD31_IRQn = 166, /*!< CAN-FD 31 Interrupt */ + PWRWU_IRQn = 167, /*!< Power Down Wake Up Interrupt */ + DDRPOISION_IRQn = 168, /*!< DDR Out of range Interrupt */ + NS_KS_IRQn = 169, /*!< KeyStore Interrupt */ + IRQn_Max = 192, +} IRQn_Type; + + +/* + * ========================================================================== + * ----------- Processor and Core Peripheral Section ------------------------ + * ========================================================================== + */ + +/* -------- Configuration of the Cortex-A35 Processor and Core Peripherals ------- */ +#define __CA_REV 0x0000U /*!< Core revision r0p0 */ +#define __CORTEX_A 35U /*!< Cortex-A35 Core */ +#define __FPU_PRESENT 1U /* FPU present */ +#define __GIC_PRESENT 1U /* GIC present */ +#define __TIM_PRESENT 1U /* TIM present */ +#define __L2C_PRESENT 0U /* L2C present */ + +#define IS_ALIGNED(x,a) (((x) & ((typeof(x))(a)-1U)) == 0) + +#include +#include "system_ma35d1.h" + +#ifdef __cplusplus +#define __I volatile /*!< Defines 'read only' permissions */ +#else +#define __I volatile const /*!< Defines 'read only' permissions */ +#endif +#define __O volatile /*!< Defines 'write only' permissions */ +#define __IO volatile /*!< Defines 'read / write' permissions */ + +#define __STATIC_INLINE static __inline + +/** + \brief No Operation + \details No Operation does nothing. This instruction can be used for code alignment purposes. + */ +#define __NOP() asm("nop") + +#endif /* if defined(USE_MA35D1_SUBM) */ + +#ifndef __CLZ +#if defined(__CC_ARM) +#define __CLZ __clz +#else +#define __CLZ __builtin_clz +#endif +#endif + +#if defined ( __CC_ARM ) +#pragma anon_unions +#endif + +/******************************************************************************/ +/* Register definitions */ +/******************************************************************************/ +#include "sys_reg.h" +#include "clk_reg.h" + +#include "uart_reg.h" +#include "whc_reg.h" +#include "hwsem_reg.h" +#include "wdt_reg.h" +#include "wwdt_reg.h" +#include "adc_reg.h" +#include "eadc_reg.h" +#include "sc_reg.h" +#include "gpio_reg.h" +#include "ecap_reg.h" +#include "qei_reg.h" +#include "i2c_reg.h" +#include "i2s_reg.h" +#include "pdma_reg.h" +#include "qspi_reg.h" +#include "spi_reg.h" +#include "rtc_reg.h" +#include "timer_reg.h" +#include "ebi_reg.h" +#include "epwm_reg.h" +#include "kpi_reg.h" +#include "canfd_reg.h" + +#include "sspcc_reg.h" +#include "ssmcc_reg.h" +#include "umctl2_reg.h" +#include "disp_reg.h" +#include "gmac_reg.h" + +#include "hsusbh_reg.h" +#include "usbh_reg.h" + +#include "sdh_reg.h" +#include "ccap_reg.h" + +/** @addtogroup PERIPHERAL_MEM_MAP Peripheral Memory Base + Memory Mapped Structure for Peripherals + @{ + */ +/* SRAM, SDRAM, External Memory and IBR (Internal Boot ROM) Space */ +#define SRAM0_BASE (0x00000000U) /* SRAM 0 Memory Space (256 KB) */ +#define SDRAM4M_BASE (0x00040000U) /* SDRAM Offset 0x0 Alias Memory Space (4 MB-256 KB) */ +#define SRAM0A_BASE (0x24000000U) /* SRAM 0 Alias Memory Space (256 KB) */ +#define SRAM1_BASE (0x28000000U) /* SRAM 1 Memory Space (256 KB) */ +#define IBR_BASE (0x5FFC0000U) /* Internal Boot ROM Space (128 KB) */ +#define EXTMEM_BASE (0x68000000U) /* External Memory Space (128 MB) */ +#define SDRAM_BASE (0x80000000U) /* SDRAM Memory Space (2GB) */ + + +/* AXI/AHB Peripheral Register Space */ +#define GPIO_BASE (0x40040000U) +#define GPIOA_BASE GPIO_BASE +#define GPIOB_BASE (0x40040040U) +#define GPIOC_BASE (0x40040080U) +#define GPIOD_BASE (0x400400C0U) +#define GPIOE_BASE (0x40040100U) +#define GPIOF_BASE (0x40040140U) +#define GPIOG_BASE (0x40040180U) +#define GPIOH_BASE (0x400401C0U) +#define GPIOI_BASE (0x40040200U) +#define GPIOJ_BASE (0x40040240U) +#define GPIOK_BASE (0x40040280U) +#define GPIOL_BASE (0x400402C0U) +#define GPIOM_BASE (0x40040300U) +#define GPION_BASE (0x40040340U) +#define GPIO_DBCTL_BASE (0x40044440U) +#define GPIO_PIN_DATA_BASE (0x40040800U) + +#define PDMA0_BASE (0x40080000U) +#define PDMA1_BASE (0x40090000U) +#define PDMA2_BASE (0x400A0000U) +#define PDMA3_BASE (0x400B0000U) + +#define EBI_BASE (0x40100000U) + +#define GMAC0_BASE (0x40120000U) +#define GMAC1_BASE (0x40130000U) + +#define HSUSBH0_BASE (0x40140000U) +#define USBH0_BASE (0x40150000U) +#define USBD_BASE (0x40160000U) +#define USBH2_BASE (0x40170000U) + +#define SDH0_BASE (0x40180000U) +#define SDH1_BASE (0x40190000U) + +#define NAND_BASE (0x401A0000U) + +#define HSUSBH1_BASE (0x401C0000U) +#define USBH1_BASE (0x401D0000U) + +#define HSUSBD_BASE (0x40200000U) + +#define CCAP0_BASE (0x40240000U) +#define CCAP1_BASE (0x40250000U) + +#define DISP_BASE (0x40260000U) +#define DISP_MPU_BASE (0x40261C40U) + +#define GFX_BASE (0x40280000U) +#define VDEC_BASE (0x40290000U) + +#define CRYPTO_BASE (0x40300000U) +#define KS_BASE (0x40340000U) +#define OPTC_BASE (0x40350000U) +#define NS_OTPC_BASE (0x40350800U) + +#define CRYPTOSYS_BASE (0x40360000U) +#define CRYPTOCLK_BASE (0x40360200U) + +#define HWSEM_BASE (0x40380000U) +#define WHC0_BASE (0x403A0000U) + +#define MCAN0_BASE (0x403C0000U) +#define MCAN1_BASE (0x403D0000U) +#define MCAN2_BASE (0x403E0000U) +#define MCAN3_BASE (0x403F0000U) +#define CANFD0_BASE MCAN0_BASE +#define CANFD1_BASE MCAN1_BASE +#define CANFD2_BASE MCAN2_BASE +#define CANFD3_BASE MCAN3_BASE + +#define WHC1_BASE (0x503B0000U) + +#define GIC_DISTRIBUTOR_BASE (0x50801000U) +#define GIC_INTERFACE_BASE (0x50802000U) + + +/* APB Peripheral Register Space */ + +#define WDT0_BASE (0x40400000U) +#define RTC_BASE (0x40410000U) +#define ADC0_BASE (0x40420000U) +#define EADC_BASE (0x40430000U) +#define EADC0_BASE EADC_BASE +#define WDT1_BASE (0x40440000U) +#define SYS_BASE (0x40460000U) +#define CLK_BASE (0x40460200U) + +#define NMI_BASE (0x40460300U) +#define I2S0_BASE (0x40480000U) +#define I2S1_BASE (0x40490000U) +#define KPI_BASE (0x404A0000U) + +#define DDRPHY_BASE (0x404C0000U) +#define UMCTL2_BASE (0x404D0000U) + +#define SSMCC_BASE (0x404E0000U) +#define TZC0_BASE (0x404E1000U) +#define TZC1_BASE (0x404E2000U) +#define TZC2_BASE (0x404E3000U) + +#define SSPCC_BASE (0x404F0000U) + +#define TIMER0_BASE (0x40500000U) +#define TIMER1_BASE (0x40500100U) +#define TIMER2_BASE (0x40510000U) +#define TIMER3_BASE (0x40510100U) +#define TIMER4_BASE (0x40520000U) +#define TIMER5_BASE (0x40520100U) +#define TIMER6_BASE (0x40530000U) +#define TIMER7_BASE (0x40530100U) +#define TIMER8_BASE (0x40540000U) +#define TIMER9_BASE (0x40540100U) +#define TIMER10_BASE (0x40550000U) +#define TIMER11_BASE (0x40550100U) + +#define EPWM0_BASE (0x40580000U) +#define EPWM1_BASE (0x40590000U) +#define EPWM2_BASE (0x405A0000U) + +#define SPI0_BASE (0x40600000U) +#define SPI1_BASE (0x40610000U) +#define SPI2_BASE (0x40620000U) +#define SPI3_BASE (0x40630000U) + +#define QSPI0_BASE (0x40680000U) +#define QSPI1_BASE (0x40690000U) + +#define UART0_BASE (0x40700000U) +#define UART1_BASE (0x40710000U) +#define UART2_BASE (0x40720000U) +#define UART3_BASE (0x40730000U) +#define UART4_BASE (0x40740000U) +#define UART5_BASE (0x40750000U) +#define UART6_BASE (0x40760000U) +#define UART7_BASE (0x40770000U) +#define UART8_BASE (0x40780000U) +#define UART9_BASE (0x40790000U) +#define UART10_BASE (0x407A0000U) +#define UART11_BASE (0x407B0000U) +#define UART12_BASE (0x407C0000U) +#define UART13_BASE (0x407D0000U) +#define UART14_BASE (0x407E0000U) +#define UART15_BASE (0x407F0000U) + +#define I2C0_BASE (0x40800000U) +#define I2C1_BASE (0x40810000U) +#define I2C2_BASE (0x40820000U) +#define I2C3_BASE (0x40830000U) +#define I2C4_BASE (0x40840000U) +#define I2C5_BASE (0x40850000U) + +#define UART16_BASE (0x40880000U) + +#define SC0_BASE (0x40900000U) +#define SC1_BASE (0x40910000U) + +#define WDT2_BASE (0x40980000U) + +#define QEI0_BASE (0x40B00000U) +#define QEI1_BASE (0x40B10000U) +#define QEI2_BASE (0x40B20000U) + +#define ECAP0_BASE (0x40B40000U) +#define ECAP1_BASE (0x40B50000U) +#define ECAP2_BASE (0x40B60000U) + + +#define WWDT0_BASE (0x40400100U) +#define WWDT1_BASE (0x40440100U) +#define WWDT2_BASE (0x40980100U) + + + +/*@}*/ /* end of group PERIPHERAL_MEM_MAP */ + + +/** @addtogroup PERIPHERAL_DECLARATION Peripheral Pointer + The Declaration of Peripherals + @{ + */ + +#define SYS ((SYS_T *) SYS_BASE) +#define CLK ((CLK_T *) CLK_BASE) +#define PA ((GPIO_T *) GPIOA_BASE) +#define PB ((GPIO_T *) GPIOB_BASE) +#define PC ((GPIO_T *) GPIOC_BASE) +#define PD ((GPIO_T *) GPIOD_BASE) +#define PE ((GPIO_T *) GPIOE_BASE) +#define PF ((GPIO_T *) GPIOF_BASE) +#define PG ((GPIO_T *) GPIOG_BASE) +#define PH ((GPIO_T *) GPIOH_BASE) +#define PI ((GPIO_T *) GPIOI_BASE) +#define PJ ((GPIO_T *) GPIOJ_BASE) +#define PK ((GPIO_T *) GPIOK_BASE) +#define PL ((GPIO_T *) GPIOL_BASE) +#define PM ((GPIO_T *) GPIOM_BASE) +#define PN ((GPIO_T *) GPION_BASE) +#define PDMA0 ((PDMA_T *) PDMA0_BASE) +#define PDMA1 ((PDMA_T *) PDMA1_BASE) +#define PDMA2 ((PDMA_T *) PDMA2_BASE) +#define PDMA3 ((PDMA_T *) PDMA3_BASE) +#define EBI ((EBI_T *) EBI_BASE) +#define HWSEM0 ((HWSEM_T *) HWSEM_BASE) +#define WHC0 ((WHC_T *) WHC0_BASE) +#define MCAN0 ((MCAN_T *) MCAN0_BASE) +#define MCAN1 ((MCAN_T *) MCAN1_BASE) +#define MCAN2 ((MCAN_T *) MCAN2_BASE) +#define MCAN3 ((MCAN_T *) MCAN3_BASE) +#define RTC ((RTC_T *) RTC_BASE) +#define ADC0 ((ADC_T *) ADC0_BASE) +#define EADC ((EADC_T *) EADC_BASE) +#define EADC0 EADC +#define I2S0 ((I2S_T *) I2S0_BASE) +#define I2S1 ((I2S_T *) I2S1_BASE) +#define KPI ((KPI_T *) KPI_BASE) +#define TIMER0 ((TIMER_T *) TIMER0_BASE) +#define TIMER1 ((TIMER_T *) TIMER1_BASE) +#define TIMER2 ((TIMER_T *) TIMER2_BASE) +#define TIMER3 ((TIMER_T *) TIMER3_BASE) +#define TIMER4 ((TIMER_T *) TIMER4_BASE) +#define TIMER5 ((TIMER_T *) TIMER5_BASE) +#define TIMER6 ((TIMER_T *) TIMER6_BASE) +#define TIMER7 ((TIMER_T *) TIMER7_BASE) +#define TIMER8 ((TIMER_T *) TIMER8_BASE) +#define TIMER9 ((TIMER_T *) TIMER9_BASE) +#define TIMER10 ((TIMER_T *) TIMER10_BASE) +#define TIMER11 ((TIMER_T *) TIMER11_BASE) +#define EPWM0 ((EPWM_T *) EPWM0_BASE) +#define EPWM1 ((EPWM_T *) EPWM1_BASE) +#define EPWM2 ((EPWM_T *) EPWM2_BASE) +#define SPI0 ((SPI_T *) SPI0_BASE) +#define SPI1 ((SPI_T *) SPI1_BASE) +#define SPI2 ((SPI_T *) SPI2_BASE) +#define SPI3 ((SPI_T *) SPI3_BASE) + +#define QSPI0 ((QSPI_T *) QSPI0_BASE) +#define QSPI1 ((QSPI_T *) QSPI1_BASE) + +#define UART0 ((UART_T *) UART0_BASE) +#define UART1 ((UART_T *) UART1_BASE) +#define UART2 ((UART_T *) UART2_BASE) +#define UART3 ((UART_T *) UART3_BASE) +#define UART4 ((UART_T *) UART4_BASE) +#define UART5 ((UART_T *) UART5_BASE) +#define UART6 ((UART_T *) UART6_BASE) +#define UART7 ((UART_T *) UART7_BASE) +#define UART8 ((UART_T *) UART8_BASE) +#define UART9 ((UART_T *) UART9_BASE) +#define UART10 ((UART_T *) UART10_BASE) +#define UART11 ((UART_T *) UART11_BASE) +#define UART12 ((UART_T *) UART12_BASE) +#define UART13 ((UART_T *) UART13_BASE) +#define UART14 ((UART_T *) UART14_BASE) +#define UART15 ((UART_T *) UART15_BASE) +#define UART16 ((UART_T *) UART16_BASE) + +#define I2C0 ((I2C_T *) I2C0_BASE) +#define I2C1 ((I2C_T *) I2C1_BASE) +#define I2C2 ((I2C_T *) I2C2_BASE) +#define I2C3 ((I2C_T *) I2C3_BASE) +#define I2C4 ((I2C_T *) I2C4_BASE) +#define I2C5 ((I2C_T *) I2C5_BASE) +#define SC0 ((SC_T *) SC0_BASE) +#define SC1 ((SC_T *) SC1_BASE) +#define WDT0 ((WDT_T *) WDT0_BASE) +#define WDT1 ((WDT_T *) WDT1_BASE) +#define WDT2 ((WDT_T *) WDT2_BASE) +#define WWDT2 ((WWDT_T *) WWDT2_BASE) +#define QEI0 ((QEI_T *) QEI0_BASE) +#define QEI1 ((QEI_T *) QEI1_BASE) +#define QEI2 ((QEI_T *) QEI2_BASE) +#define ECAP0 ((ECAP_T *) ECAP0_BASE) +#define ECAP1 ((ECAP_T *) ECAP1_BASE) +#define ECAP2 ((ECAP_T *) ECAP2_BASE) +#define CANFD0 ((CANFD_T*) CANFD0_BASE) +#define CANFD1 ((CANFD_T*) CANFD1_BASE) +#define CANFD2 ((CANFD_T*) CANFD2_BASE) +#define CANFD3 ((CANFD_T*) CANFD3_BASE) + +#define SSPCC ((SSPCC_T*) SSPCC_BASE) +#define SSMCC ((SSMCC_T*) SSMCC_BASE) +#define TZC0 ((TZC_T*) TZC0_BASE) +#define TZC2 ((TZC_T*) TZC2_BASE) +#define UMCTL2 ((UMCTL2_T*)UMCTL2_BASE) +#define DISP ((DISP_T*) DISP_BASE) + +#define GMAC0 ((GMAC_T*) GMAC0_BASE) +#define GMAC1 ((GMAC_T*) GMAC1_BASE) + +#define SDH0 ((SDH_T*) SDH0_BASE) +#define SDH1 ((SDH_T*) SDH1_BASE) + +#define CCAP0 ((CCAP_T*) CCAP0_BASE) +#define CCAP1 ((CCAP_T*) CCAP1_BASE) + +/*@}*/ /* end of group ERIPHERAL_DECLARATION */ + +/** @addtogroup IO_ROUTINE I/O Routines + The Declaration of I/O Routines + @{ + */ + +typedef volatile uint8_t vu8; ///< Define 8-bit unsigned volatile data type +typedef volatile uint16_t vu16; ///< Define 16-bit unsigned volatile data type +typedef volatile uint32_t vu32; ///< Define 32-bit unsigned volatile data type +typedef volatile uint64_t vu64; ///< Define 64-bit unsigned volatile data type + +/** + * @brief Get a 8-bit unsigned value from specified address + * @param[in] addr Address to get 8-bit data from + * @return 8-bit unsigned value stored in specified address + */ +#define M8(addr) (*((vu8 *) (addr))) + +/** + * @brief Get a 16-bit unsigned value from specified address + * @param[in] addr Address to get 16-bit data from + * @return 16-bit unsigned value stored in specified address + * @note The input address must be 16-bit aligned + */ +#define M16(addr) (*((vu16 *) (addr))) + +/** + * @brief Get a 32-bit unsigned value from specified address + * @param[in] addr Address to get 32-bit data from + * @return 32-bit unsigned value stored in specified address + * @note The input address must be 32-bit aligned + */ +#define M32(addr) (*((vu32 *) (addr))) + +/** + * @brief Get a 64-bit unsigned value from specified address + * @param[in] addr Address to get 64-bit data from + * @return 64-bit unsigned value stored in specified address + * @note The input address must be 64-bit aligned + */ +#define M64(addr) (*((vu64 *) (addr))) + +/** + * @brief Set a 32-bit unsigned value to specified I/O port + * @param[in] port Port address to set 32-bit data + * @param[in] value Value to write to I/O port + * @return None + * @note The output port must be 32-bit aligned + */ +#define outpw(port,value) *((vu32 *)(port)) = (value) + +/** + * @brief Get a 32-bit unsigned value from specified I/O port + * @param[in] port Port address to get 32-bit data from + * @return 32-bit unsigned value stored in specified I/O port + * @note The input port must be 32-bit aligned + */ +#define inpw(port) (*((vu32 *)(port))) + +/** + * @brief Set a 16-bit unsigned value to specified I/O port + * @param[in] port Port address to set 16-bit data + * @param[in] value Value to write to I/O port + * @return None + * @note The output port must be 16-bit aligned + */ +#define outps(port,value) *((vu16 *)(port)) = (value) + +/** + * @brief Get a 16-bit unsigned value from specified I/O port + * @param[in] port Port address to get 16-bit data from + * @return 16-bit unsigned value stored in specified I/O port + * @note The input port must be 16-bit aligned + */ +#define inps(port) (*((vu16 *)(port))) + +/** + * @brief Set a 8-bit unsigned value to specified I/O port + * @param[in] port Port address to set 8-bit data + * @param[in] value Value to write to I/O port + * @return None + */ +#define outpb(port,value) *((vu8 *)(port)) = (value) + +/** + * @brief Get a 8-bit unsigned value from specified I/O port + * @param[in] port Port address to get 8-bit data from + * @return 8-bit unsigned value stored in specified I/O port + */ +#define inpb(port) (*((vu8 *)(port))) + +/** + * @brief Set a 64-bit unsigned value to specified I/O port + * @param[in] port Port address to set 64-bit data + * @param[in] value Value to write to I/O port + * @return None + * @note The output port must be 64-bit aligned + */ +#define outp64(port,value) *((vu64 *)(port)) = (value) + +/** + * @brief Get a 64-bit unsigned value from specified I/O port + * @param[in] port Port address to get 64-bit data from + * @return 64-bit unsigned value stored in specified I/O port + * @note The input port must be 64-bit aligned + */ +#define inp64(port) (*((vu64 *)(port))) + +/** + * @brief Set a 32-bit unsigned value to specified I/O port + * @param[in] port Port address to set 32-bit data + * @param[in] value Value to write to I/O port + * @return None + * @note The output port must be 32-bit aligned + */ +#define outp32(port,value) *((vu32 *)(port)) = (value) + +/** + * @brief Get a 32-bit unsigned value from specified I/O port + * @param[in] port Port address to get 32-bit data from + * @return 32-bit unsigned value stored in specified I/O port + * @note The input port must be 32-bit aligned + */ +#define inp32(port) (*((vu32 *)(port))) + +/** + * @brief Set a 16-bit unsigned value to specified I/O port + * @param[in] port Port address to set 16-bit data + * @param[in] value Value to write to I/O port + * @return None + * @note The output port must be 16-bit aligned + */ +#define outp16(port,value) *((vu16 *)(port)) = (value) + +/** + * @brief Get a 16-bit unsigned value from specified I/O port + * @param[in] port Port address to get 16-bit data from + * @return 16-bit unsigned value stored in specified I/O port + * @note The input port must be 16-bit aligned + */ +#define inp16(port) (*((vu16 *)(port))) + +/** + * @brief Set a 8-bit unsigned value to specified I/O port + * @param[in] port Port address to set 8-bit data + * @param[in] value Value to write to I/O port + * @return None + */ +#define outp8(port,value) *((vu8 *)(port)) = (value) + +/** + * @brief Get a 8-bit unsigned value from specified I/O port + * @param[in] port Port address to get 8-bit data from + * @return 8-bit unsigned value stored in specified I/O port + */ +#define inp8(port) (*((vu8 *)(port))) + + +/*@}*/ /* end of group IO_ROUTINE */ + +/******************************************************************************/ +/* Legacy Constants */ +/******************************************************************************/ +/** @addtogroup Legacy_Constants Legacy Constants + Legacy Constants + @{ +*/ + +#ifndef NULL +#define NULL (0) ///< NUL pointer +#endif + +#define TRUE (1U) ///< Boolean true, define to use in API parameters or return value +#define FALSE (0U) ///< Boolean false, define to use in API parameters or return value + +#define ENABLE (1U) ///< Enable, define to use in API parameters +#define DISABLE (0U) ///< Disable, define to use in API parameters + +/* Define one bit mask */ +#define BIT0 (0x00000001U) ///< Bit 0 mask of an 32 bit integer +#define BIT1 (0x00000002U) ///< Bit 1 mask of an 32 bit integer +#define BIT2 (0x00000004U) ///< Bit 2 mask of an 32 bit integer +#define BIT3 (0x00000008U) ///< Bit 3 mask of an 32 bit integer +#define BIT4 (0x00000010U) ///< Bit 4 mask of an 32 bit integer +#define BIT5 (0x00000020U) ///< Bit 5 mask of an 32 bit integer +#define BIT6 (0x00000040U) ///< Bit 6 mask of an 32 bit integer +#define BIT7 (0x00000080U) ///< Bit 7 mask of an 32 bit integer +#define BIT8 (0x00000100U) ///< Bit 8 mask of an 32 bit integer +#define BIT9 (0x00000200U) ///< Bit 9 mask of an 32 bit integer +#define BIT10 (0x00000400U) ///< Bit 10 mask of an 32 bit integer +#define BIT11 (0x00000800U) ///< Bit 11 mask of an 32 bit integer +#define BIT12 (0x00001000U) ///< Bit 12 mask of an 32 bit integer +#define BIT13 (0x00002000U) ///< Bit 13 mask of an 32 bit integer +#define BIT14 (0x00004000U) ///< Bit 14 mask of an 32 bit integer +#define BIT15 (0x00008000U) ///< Bit 15 mask of an 32 bit integer +#define BIT16 (0x00010000U) ///< Bit 16 mask of an 32 bit integer +#define BIT17 (0x00020000U) ///< Bit 17 mask of an 32 bit integer +#define BIT18 (0x00040000U) ///< Bit 18 mask of an 32 bit integer +#define BIT19 (0x00080000U) ///< Bit 19 mask of an 32 bit integer +#define BIT20 (0x00100000U) ///< Bit 20 mask of an 32 bit integer +#define BIT21 (0x00200000U) ///< Bit 21 mask of an 32 bit integer +#define BIT22 (0x00400000U) ///< Bit 22 mask of an 32 bit integer +#define BIT23 (0x00800000U) ///< Bit 23 mask of an 32 bit integer +#define BIT24 (0x01000000U) ///< Bit 24 mask of an 32 bit integer +#define BIT25 (0x02000000U) ///< Bit 25 mask of an 32 bit integer +#define BIT26 (0x04000000U) ///< Bit 26 mask of an 32 bit integer +#define BIT27 (0x08000000U) ///< Bit 27 mask of an 32 bit integer +#define BIT28 (0x10000000U) ///< Bit 28 mask of an 32 bit integer +#define BIT29 (0x20000000U) ///< Bit 29 mask of an 32 bit integer +#define BIT30 (0x40000000U) ///< Bit 30 mask of an 32 bit integer +#define BIT31 (0x80000000U) ///< Bit 31 mask of an 32 bit integer + +/* Byte Mask Definitions */ +#define BYTE0_Msk (0x000000FFU) ///< Mask to get bit0~bit7 from a 32 bit integer +#define BYTE1_Msk (0x0000FF00U) ///< Mask to get bit8~bit15 from a 32 bit integer +#define BYTE2_Msk (0x00FF0000U) ///< Mask to get bit16~bit23 from a 32 bit integer +#define BYTE3_Msk (0xFF000000U) ///< Mask to get bit24~bit31 from a 32 bit integer + +#define GET_BYTE0(u32Param) (((u32Param) & BYTE0_Msk) ) /*!< Extract Byte 0 (Bit 0~ 7) from parameter u32Param */ +#define GET_BYTE1(u32Param) (((u32Param) & BYTE1_Msk) >> 8) /*!< Extract Byte 1 (Bit 8~15) from parameter u32Param */ +#define GET_BYTE2(u32Param) (((u32Param) & BYTE2_Msk) >> 16) /*!< Extract Byte 2 (Bit 16~23) from parameter u32Param */ +#define GET_BYTE3(u32Param) (((u32Param) & BYTE3_Msk) >> 24) /*!< Extract Byte 3 (Bit 24~31) from parameter u32Param */ + +/*@}*/ /* end of group Legacy_Constants */ + +/******************************************************************************/ +/* Peripheral header files */ +/******************************************************************************/ +#include "nu_sys.h" +#include "nu_clk.h" +#include "nu_uart.h" +#include "nu_pdma.h" +#include "nu_gpio.h" +#include "nu_hwsem.h" +#include "nu_whc.h" +#include "nu_ecap.h" +#include "nu_qei.h" +#include "nu_timer.h" +#include "nu_timer_pwm.h" +#include "nu_i2c.h" +#include "nu_i2s.h" +#include "nu_epwm.h" +#include "nu_eadc.h" +#include "nu_adc.h" +#include "nu_wdt.h" +#include "nu_wwdt.h" +#include "nu_ebi.h" +#include "nu_scuart.h" +#include "nu_sc.h" +#include "nu_spi.h" +#include "nu_qspi.h" +#include "nu_rtc.h" +#include "nu_kpi.h" +#include "nu_canfd.h" +#include "nu_ssmcc.h" +#include "nu_sspcc.h" +#include "nu_disp.h" +#include "nu_sdh.h" +#include "nu_ccap.h" + +#ifdef __cplusplus +} +#endif + +#endif /* __MA35D1_H__ */ + diff --git a/bsp/nuvoton/libraries/ma35/Device/Nuvoton/MA35D1/Include/nfi_reg.h b/bsp/nuvoton/libraries/ma35/Device/Nuvoton/MA35D1/Include/nfi_reg.h new file mode 100644 index 0000000000..de1320210c --- /dev/null +++ b/bsp/nuvoton/libraries/ma35/Device/Nuvoton/MA35D1/Include/nfi_reg.h @@ -0,0 +1,2850 @@ +/**************************************************************************//** + * @file nfi_reg.h + * @brief NFI register definition header file + * + * SPDX-License-Identifier: Apache-2.0 + * @copyright (C) 2021 Nuvoton Technology Corp. All rights reserved. + *****************************************************************************/ +#ifndef __NFI_REG_H__ +#define __NFI_REG_H__ + +#if defined ( __CC_ARM ) + #pragma anon_unions +#endif + +/******************************************************************************/ +/* Device Specific Peripheral registers structures */ +/******************************************************************************/ + +/** @addtogroup REGISTER Control Register + + @{ + +*/ + +/*---------------------- NAND Flash Interface -------------------------*/ +/** + @addtogroup NFI NAND Flash Interface(NFI) + Memory Mapped Structure for NFI Controller +@{ */ + +typedef struct +{ + + + /** + * @var NFI_T::BUFFER0 + * Offset: 0x00 NFI Embedded Buffer Word n + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[31:0] |Data |NFI Embedded Buffer Word n + * | | |This field indicates a 32-bit data of NAND Flash controller embedded buffer. + * @var NFI_T::BUFFER1 + * Offset: 0x04 NFI Embedded Buffer Word n + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[31:0] |Data |NFI Embedded Buffer Word n + * | | |This field indicates a 32-bit data of NAND Flash controller embedded buffer. + * @var NFI_T::BUFFER2 + * Offset: 0x08 NFI Embedded Buffer Word n + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[31:0] |Data |NFI Embedded Buffer Word n + * | | |This field indicates a 32-bit data of NAND Flash controller embedded buffer. + * @var NFI_T::BUFFER3 + * Offset: 0x0C NFI Embedded Buffer Word n + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[31:0] |Data |NFI Embedded Buffer Word n + * | | |This field indicates a 32-bit data of NAND Flash controller embedded buffer. + * @var NFI_T::BUFFER4 + * Offset: 0x10 NFI Embedded Buffer Word n + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[31:0] |Data |NFI Embedded Buffer Word n + * | | |This field indicates a 32-bit data of NAND Flash controller embedded buffer. + * @var NFI_T::BUFFER5 + * Offset: 0x14 NFI Embedded Buffer Word n + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[31:0] |Data |NFI Embedded Buffer Word n + * | | |This field indicates a 32-bit data of NAND Flash controller embedded buffer. + * @var NFI_T::BUFFER6 + * Offset: 0x18 NFI Embedded Buffer Word n + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[31:0] |Data |NFI Embedded Buffer Word n + * | | |This field indicates a 32-bit data of NAND Flash controller embedded buffer. + * @var NFI_T::BUFFER7 + * Offset: 0x1C NFI Embedded Buffer Word n + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[31:0] |Data |NFI Embedded Buffer Word n + * | | |This field indicates a 32-bit data of NAND Flash controller embedded buffer. + * @var NFI_T::BUFFER8 + * Offset: 0x20 NFI Embedded Buffer Word n + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[31:0] |Data |NFI Embedded Buffer Word n + * | | |This field indicates a 32-bit data of NAND Flash controller embedded buffer. + * @var NFI_T::BUFFER9 + * Offset: 0x24 NFI Embedded Buffer Word n + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[31:0] |Data |NFI Embedded Buffer Word n + * | | |This field indicates a 32-bit data of NAND Flash controller embedded buffer. + * @var NFI_T::BUFFER10 + * Offset: 0x28 NFI Embedded Buffer Word n + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[31:0] |Data |NFI Embedded Buffer Word n + * | | |This field indicates a 32-bit data of NAND Flash controller embedded buffer. + * @var NFI_T::BUFFER11 + * Offset: 0x2C NFI Embedded Buffer Word n + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[31:0] |Data |NFI Embedded Buffer Word n + * | | |This field indicates a 32-bit data of NAND Flash controller embedded buffer. + * @var NFI_T::BUFFER12 + * Offset: 0x30 NFI Embedded Buffer Word n + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[31:0] |Data |NFI Embedded Buffer Word n + * | | |This field indicates a 32-bit data of NAND Flash controller embedded buffer. + * @var NFI_T::BUFFER13 + * Offset: 0x34 NFI Embedded Buffer Word n + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[31:0] |Data |NFI Embedded Buffer Word n + * | | |This field indicates a 32-bit data of NAND Flash controller embedded buffer. + * @var NFI_T::BUFFER14 + * Offset: 0x38 NFI Embedded Buffer Word n + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[31:0] |Data |NFI Embedded Buffer Word n + * | | |This field indicates a 32-bit data of NAND Flash controller embedded buffer. + * @var NFI_T::BUFFER15 + * Offset: 0x3C NFI Embedded Buffer Word n + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[31:0] |Data |NFI Embedded Buffer Word n + * | | |This field indicates a 32-bit data of NAND Flash controller embedded buffer. + * @var NFI_T::BUFFER16 + * Offset: 0x40 NFI Embedded Buffer Word n + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[31:0] |Data |NFI Embedded Buffer Word n + * | | |This field indicates a 32-bit data of NAND Flash controller embedded buffer. + * @var NFI_T::BUFFER17 + * Offset: 0x44 NFI Embedded Buffer Word n + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[31:0] |Data |NFI Embedded Buffer Word n + * | | |This field indicates a 32-bit data of NAND Flash controller embedded buffer. + * @var NFI_T::BUFFER18 + * Offset: 0x48 NFI Embedded Buffer Word n + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[31:0] |Data |NFI Embedded Buffer Word n + * | | |This field indicates a 32-bit data of NAND Flash controller embedded buffer. + * @var NFI_T::BUFFER19 + * Offset: 0x4C NFI Embedded Buffer Word n + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[31:0] |Data |NFI Embedded Buffer Word n + * | | |This field indicates a 32-bit data of NAND Flash controller embedded buffer. + * @var NFI_T::BUFFER20 + * Offset: 0x50 NFI Embedded Buffer Word n + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[31:0] |Data |NFI Embedded Buffer Word n + * | | |This field indicates a 32-bit data of NAND Flash controller embedded buffer. + * @var NFI_T::BUFFER21 + * Offset: 0x54 NFI Embedded Buffer Word n + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[31:0] |Data |NFI Embedded Buffer Word n + * | | |This field indicates a 32-bit data of NAND Flash controller embedded buffer. + * @var NFI_T::BUFFER22 + * Offset: 0x58 NFI Embedded Buffer Word n + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[31:0] |Data |NFI Embedded Buffer Word n + * | | |This field indicates a 32-bit data of NAND Flash controller embedded buffer. + * @var NFI_T::BUFFER23 + * Offset: 0x5C NFI Embedded Buffer Word n + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[31:0] |Data |NFI Embedded Buffer Word n + * | | |This field indicates a 32-bit data of NAND Flash controller embedded buffer. + * @var NFI_T::BUFFER24 + * Offset: 0x60 NFI Embedded Buffer Word n + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[31:0] |Data |NFI Embedded Buffer Word n + * | | |This field indicates a 32-bit data of NAND Flash controller embedded buffer. + * @var NFI_T::BUFFER25 + * Offset: 0x64 NFI Embedded Buffer Word n + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[31:0] |Data |NFI Embedded Buffer Word n + * | | |This field indicates a 32-bit data of NAND Flash controller embedded buffer. + * @var NFI_T::BUFFER26 + * Offset: 0x68 NFI Embedded Buffer Word n + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[31:0] |Data |NFI Embedded Buffer Word n + * | | |This field indicates a 32-bit data of NAND Flash controller embedded buffer. + * @var NFI_T::BUFFER27 + * Offset: 0x6C NFI Embedded Buffer Word n + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[31:0] |Data |NFI Embedded Buffer Word n + * | | |This field indicates a 32-bit data of NAND Flash controller embedded buffer. + * @var NFI_T::BUFFER28 + * Offset: 0x70 NFI Embedded Buffer Word n + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[31:0] |Data |NFI Embedded Buffer Word n + * | | |This field indicates a 32-bit data of NAND Flash controller embedded buffer. + * @var NFI_T::BUFFER29 + * Offset: 0x74 NFI Embedded Buffer Word n + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[31:0] |Data |NFI Embedded Buffer Word n + * | | |This field indicates a 32-bit data of NAND Flash controller embedded buffer. + * @var NFI_T::BUFFER30 + * Offset: 0x78 NFI Embedded Buffer Word n + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[31:0] |Data |NFI Embedded Buffer Word n + * | | |This field indicates a 32-bit data of NAND Flash controller embedded buffer. + * @var NFI_T::BUFFER31 + * Offset: 0x7C NFI Embedded Buffer Word n + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[31:0] |Data |NFI Embedded Buffer Word n + * | | |This field indicates a 32-bit data of NAND Flash controller embedded buffer. + * @var NFI_T::DMACTL + * Offset: 0x400 NFI DMA Control and Status Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[0] |DMACEN |DMA Controller Engine Enable Bit + * | | |0 = DMA Controller Disabled. + * | | |1 = DMA Controller Enabled. + * | | |Note 1: If this bit is cleared, DMA will ignore all requests from NAND Flash and force bus master into IDLE state. + * | | |Note 2: If target abort occurred, DMACEN will be cleared. + * |[1] |DMARST |Software Engine Reset + * | | |0 = No effect. + * | | |1 = Reset internal state machine and pointers + * | | |The contents of control register will not be cleared + * | | |This bit will auto be cleared after a few clock cycles. + * | | |Note: The software reset DMA related registers. + * |[3] |SGEN |Scatter-gather Function for NFI Enable Bit + * | | |0 = Scatter-gather function Disabled (DMA will treat the starting address in DMASA as starting pointer of a single block memory). + * | | |1 = Scatter-gather function Enabled (DMA will treat the starting address in DMASA as a starting address of Physical Address Descriptor (PAD) table + * | | |The format of these Pads' will be described later). + * |[9] |DMABUSY |NFI DMA Transfer in Progress + * | | |This bit indicates if NFI is granted and doing DMA transfer or not. + * | | |0 = NFI DMA transfer is not in progress. + * | | |1 = NFI DMA transfer is in progress. + * @var NFI_T::DMASA + * Offset: 0x408 NFI DMA Transfer Starting Address Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[0] |ORDER |Determined to the PAD Table Fetching Is in Order or Out of Order + * | | |0 = PAD table is fetched in order. + * | | |1 = PAD table is fetched out of order. + * | | |Note: the bit 0 is valid in scatter-gather mode when SGEN (NFI_DMACTL[3]) = 1. + * |[31:1] |DMASA |DMA Transfer Starting Address + * | | |This field pads 0 as least significant bit indicates a 32-bit starting address of system memory (SRAM) for DMA to retrieve or fill in data. + * | | |If DMA is not in normal mode, this field will be interpreted as a starting address of Physical Address Descriptor (PAD) table. + * | | |Note: Starting address of the SRAM must be word aligned, for example, 0x0000_0000, 0x0000_0004. + * @var NFI_T::DMABCNT + * Offset: 0x40C NFI DMA Transfer Byte Count Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[25:0] |BCNT |DMA Transfer Byte Count (Read Only) + * | | |This field indicates the remained byte count of DMA transfer + * | | |The value of this field is valid only when NFI is busy; otherwise, it is zero. + * @var NFI_T::DMAINTEN + * Offset: 0x410 NFI DMA Interrupt Enable Control Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[0] |ABORTIEN |DMA Read/Write Target Abort Interrupt Enable Bit + * | | |0 = Target abort interrupt generation Disabled during DMA transfer. + * | | |1 = Target abort interrupt generation Enabled during DMA transfer. + * |[1] |WEOTIEN |Wrong EOT Encountered Interrupt Enable Bit + * | | |0 = Interrupt generation Disabled when wrong EOT (end of transfer) is encountered. + * | | |1 = Interrupt generation Enabled when wrong EOT (end of transfer) is encountered. + * @var NFI_T::DMAINTSTS + * Offset: 0x414 NFI DMA Interrupt Status Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[0] |ABORTIF |DMA Read/Write Target Abort Interrupt Flag(Read Only) + * | | |0 = No bus ERROR response received. + * | | |1 = Bus ERROR response received. + * | | |Note: This bit is read only, but can be cleared by writing '1' to it. + * | | |Note: When DMA's bus master received ERROR response, it means that target abort happened + * | | |DMA will stop transfer and respond this event by set ABORTIF high + * | | |Then, NFI go to IDLE state + * | | |When target abort occurred or WEOTIF is set, it is necessary to reset NFI's DMA and then transfer those data again. + * |[1] |WEOTIF |Wrong EOT Encountered Interrupt Flag(Read Only) + * | | |When DMA Scatter-Gather function is enabled, and EOT of the descriptor is encountered before DMA transfer finished (that means the total sector count of all PAD is less than the sector count of NFI), this bit will be set. + * | | |0 = No EOT encountered before DMA transfer finished. + * | | |1 = EOT encountered before DMA transfer finished. + * | | |Note: This bit is read only, but can be cleared by writing '1' to it. + * @var NFI_T::GCTL + * Offset: 0x800 NFI Global Control and Status Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[0] |GCTLRST |Software Engine Reset + * | | |0 = No effect. + * | | |1 = Reset all NFI engines. + * | | |Note: The contents of control register will not be cleared + * | | |This bit will auto cleared after a few clock cycles. + * |[3] |NANDEN |NAND Flash Functionality Enable Bit + * | | |0 = NAND Flash functionality of NFI Disabled. + * | | |1 = NAND Flash functionality of NFI Enabled. + * @var NFI_T::GINTEN + * Offset: 0x804 NFI Global Interrupt Control Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[0] |DTAIEN |DMA READ/WRITE Target Abort Interrupt Enable Bit + * | | |0 = DMA READ/WRITE target abort interrupt generation Disabled. + * | | |1 = DMA READ/WRITE target abort interrupt generation Enabled. + * @var NFI_T::GINTSTS + * Offset: 0x808 NFI Global Interrupt Status Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[0] |DTAIF |DMA READ/WRITE Target Abort Interrupt Flag (Read Only) + * | | |This bit indicates DMA received an ERROR response from internal AHB bus during DMA read/write operation + * | | |When Target Abort occurred, please reset all engines. + * | | |0 = No bus ERROR response received. + * | | |1 = Bus ERROR response received. + * | | |Note: This bit is read only, but can be cleared by writing '1' to it. + * @var NFI_T::NANDCTL + * Offset: 0x8A0 NAND Flash Control Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[0] |SWRST |Software Engine Reset + * | | |0 = No effect. + * | | |1 = Reset the internal state machine and counters (include DWREN (NFI_NANDCTL[2]) and DRDEN (NFI_NANDCTL[1])). + * | | |Note: The contents of control register will not be cleared + * | | |This bit will be auto cleared after a few clock cycles. + * |[1] |DRDEN |DMA Read Data Enable Bit + * | | |This bit enables NAND controller to transfer data (1 page) from NAND Flash or NAND type Flash into DMAC's embedded frame buffer. + * | | |0 = No effect. + * | | |1 = DMA read data transfer Enabled. + * | | |Note: When DMA transfer completed, this bit will be cleared automatically. + * |[2] |DWREN |DMA Write Data Enable Bit + * | | |This bit enables NAND controller to transfer data (1 page) from DMAC's embedded frame buffer into NAND Flash or NAND type Flash. + * | | |0 = No effect. + * | | |1 = DMA write data transfer Enabled. + * | | |Note: When DMA transfer completed, this bit will be cleared automatically. + * |[3] |REDUNREN |Redundant Area Read Enable Bit + * | | |This bit enables NAND controller to transfer redundant data from NAND Flash into NFI_NANDRA, the data size is dependent on NFI_NANDRACTL register. + * | | |0 = No effect. + * | | |1 = Read redundant data transfer Enabled. + * | | |Note: When transfer completed, this bit will be cleared automatically. + * |[4] |REDUNAUTOWEN|Redundant Area Auto Write Enable Bit + * | | |This field is used to auto write redundant data out to NAND Flash + * | | |The redundant data area is dependent on NFI_NANDRACTL register. + * | | |0 = Auto write redundant data out to NAND Flash Disabled. + * | | |1 = Auto write redundant data out to NAND Flash Enabled. + * |[7] |ECCCHK |None Used Field ECC Check After Read Page Data + * | | |0 = ECC check Disabled + * | | |The NAND controller will always check ECC result for each field, no matter it is used or not. + * | | |1 = ECC check Enabled + * | | |The NAND controller will check 1's count for byte 2, 3 of redundant data of the ECC in each field + * | | |If the count value is greater than 8, the NAND controller will treat this field as none used field; otherwise, it is used + * | | |If that field is none used field, the NAND controller will ignore its ECC check result. + * |[8] |PROT3BEN |Protect_3Byte Software Data Enable Bit + * | | |The ECC algorithm only protects data area and hardware ECC parity code + * | | |User can choose to protect software redundant data first 3 bytes by setting this bit high. + * | | |0 = Software redundant data is not protected by ECC algorithm. + * | | |1 = Software redundant data first 3 bytes protected by ECC algorithm. + * |[9] |SRAMINT |SRAM Initial + * | | |0 = No effect. + * | | |1 = Reset the internal NFI_NANDRA0~NFI_NANDRA1 to 0xFFFF_FFFF. + * | | |Note: The contents of control register will not be cleared + * | | |This bit will be auto cleared after a few clock cycles. + * |[17:16] |PSIZE |Page Size of NAND + * | | |This bit indicates the page size of NAND + * | | |There are four page sizes for choose, 2048 bytes/page, 4096 bytes/page and 8192 bytes/page + * | | |Before setting PSIZE register, user must set BCHTSEL register at first. + * | | |01 = Page size is 2048 bytes/page. + * | | |10 = Page size is 4096 bytes/page. + * | | |11 = Page size is 8192 bytes/page. + * |[22:18] |BCHTSEL |BCH Correct Bit Selection + * | | |This field is used to select BCH correct bits for data protecting + * | | |For BCH algorithm, T can be 8 or 12 or 24 for choosing (correct 8 or 12 or 24 bits). + * | | |00001 = Using BCH T24 to encode/decode (T24).(.1024 Bytes per block) + * | | |00100 = Using BCH T8 to encode/decode (T8). + * | | |01000 = Using BCH T12 to encode/decode (T12). + * |[23] |ECCEN |ECC Algorithm Enable Bit + * | | |This field is used to select the ECC algorithm for data protecting + * | | |The BCH algorithm can correct 8 or 12 or 24 bits. + * | | |0 = BCH code encode/decode Disabled. + * | | |1 = BCH code encode/decode Enabled. + * | | |Note: If disabling ECCEN and when reading data from NAND, the NAND controller will ignore its ECC check result + * | | |When writing data to NAND, the NAND controller will write out 0xFF to every parity field. + * | | |Note: The ECC algorithm only protects data area and hardware ECC parity code by default + * | | |By setting PROT3BEN (NFI_NANDCTL[8]) high, the first 3 bytes of redundant data are also protected by ECC algorithm. + * |[25] |CS0 |NAND Flash Chip Select 0 Enable Bit + * | | |0 = Chip select 0 Enabled. + * | | |1 = Chip select 0 Disabled. + * @var NFI_T::NANDTMCTL + * Offset: 0x8A4 NAND Flash Timing Control Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[7:0] |LOWID |Read/Write Enable Signal Low Pulse Width + * | | |This field controls the low pulse width of signals -RE and -WE while HARDWARE mode page access is enabled + * | | |The pulse width is a multiple of period of AHB bus clock + * | | |( The actual width time will be [clock period*(LOWID+1)] ) + * |[15:8] |HIWID |Read/Write Enable Signal High Pulse Width + * | | |This field controls the high pulse width of signals -RE and -WE while HARDWARE mode page access is enabled + * | | |The pulse width is a multiple of period of AHB bus clock + * | | |( The actual width time will be [clock period*(HIWID+1)] ) + * |[22:16] |CALESH |CLE/ALE Setup/Hold Time + * | | |This field controls the CLE/ALE setup/hold time to -WE. + * | | |The setup/hold time can be calculated using following equation: + * | | |tCLS = (CALESH+1)*TAHB. + * | | |tCLH = ((CALESH*2)+2)*TAHB. + * | | |tALS = (CALESH+1)*TAHB. + * | | |tALH = ((CALESH*2)+2)*TAHB. + * |[27:24] |EDOD |EDO Mode Delay Time + * | | |Control this field to delay sampling point when NAND Flash enters EDO mode only. + * | | |The EDO mode delay time can be calculated using following equation: + * | | |Delay time = (EDOD+1)*(TAHB/2). + * |[31] |EDOEN |EDO Mode Enable Bit + * | | |This bit specifies NAND Flash to EDO mode + * | | |Before trigger this bit, software should fill EDOD(NFI_NANDTMCTL[27:24]), CALESH(NFI_NANDTMCTL[22:16]), HIWID(NFI_NANDTMCTL[15:8]) and LOWID(NFI_NANDTMCTL[7:0]). + * | | |0 = EDO Mode related function Disabled. + * | | |1 = EDO Mode related function Enabled. + * | | |Note: Only NAND Flash entering EDO mode should set this bit. + * @var NFI_T::NANDINTEN + * Offset: 0x8A8 NAND Flash Interrupt Enable Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[0] |DMAIE |DMA Read/Write Data Complete Interrupt Enable Bit + * | | |0 = DMA read/write data complete interrupt generation Disabled. + * | | |1 = DMA read/write data complete interrupt generation Enabled. + * |[2] |ECCFLDIE |ECC Field Check Error Interrupt Enable Bit + * | | |This bit can check the ECC error on each field (512bytes) of data transfer + * | | |Enable this bit to detect error and do error correction. + * | | |0 = ECC field check error Disabled. + * | | |1 = ECC field check error Enabled. + * |[10] |RB0IE |Ready/-Busy Rising Edge Detect Interrupt Enable Bit + * | | |0 = R/-B rising edge detect interrupt generation Disabled. + * | | |1 = R/-B rising edge detect interrupt generation Enabled. + * @var NFI_T::NANDINTSTS + * Offset: 0x8AC NAND Flash Interrupt Status Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[0] |DMAIF |DMA Read/Write Data Complete Interrupt Flag (Read Only) + * | | |0 = DMA read/write transfer is not finished yet. + * | | |1 = DMA read/write transfer is done. + * | | |Note: This bit is read only, but can be cleared by writing '1' to it. + * |[2] |ECCFLDIF |ECC Field Check Error Interrupt Flag (Read Only) + * | | |This bit can check the ECC error on each field (512bytes) of data transfer + * | | |Read this bit to check if the error occurred. + * | | |0 = No occurrence of ECC error. + * | | |1 = Occurrence of ECC error. + * | | |Note: This bit is read only, but can be cleared by writing '1' to it. + * |[4] |EDOF |EDO Mode Entrance Flag (Read Only) + * | | |0 = NAND Flash did not enter EDO mode. + * | | |1 = NAND Flash entered EDO mode. + * | | |Note: This bit is read only, but can be cleared by writing '1' to it. + * |[10] |RB0IF |Ready/-Busy 0 Rising Edge Detect Interrupt Flag (Read Only) + * | | |0 = R/-B rising edge is not detected. + * | | |1 = R/-B rising edge is detected. + * | | |Note: This bit is read only, but can be cleared by writing '1' to it. + * |[18] |RB0Status |Ready/-Busy 0 Pin Status (Read Only) + * | | |This bit reflects the Ready/-Busy pin status of NAND Flash. + * @var NFI_T::NANDCMD + * Offset: 0x8B0 NAND Flash Command Port Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[7:0] |COMMAND |NAND Flash Command Port + * | | |When CPU writes to this port, NFI will send a command to NAND Flash. + * @var NFI_T::NANDADDR + * Offset: 0x8B4 NAND Flash Address Port Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[7:0] |ADDRESS |NAND Flash Address Port + * | | |By writing this port, NAND Flash control will send an address to NAND Flash. + * |[31] |EOA |End of Address + * | | |Write this bit to indicate if this address is the last one or not + * | | |By writing address port with this bit low, the NAND Flash controller will set ALE pin to active (HIGH) + * | | |After the last address is written (with this bit set high), the NAND Flash controller will set ALE pin to inactive (LOW). + * | | |0 = Not the last address cycle. + * | | |1 = The last one address cycle. + * @var NFI_T::NANDDATA + * Offset: 0x8B8 NAND Flash Data Port Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[7:0] |DATA |NAND Flash Data Port + * | | |CPU can access NAND's memory array through this data port + * | | |When CPU WRITE, the lower 8-bit data from CPU will appear on the data bus of NAND controller + * | | |When CPU READ, NAND controller will get 8-bit data from data bus. + * @var NFI_T::NANDRACTL + * Offset: 0x8BC NAND Flash Redundant Area Control Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[8:0] |RA128EN |Redundant Area 128 Byte Enable Bit + * | | |These bits indicate NAND Flash extended redundant area. + * | | |If PSIZE (NFI_NANDCTL[17:16]) = 2'b01, this field will be set 0x40 (64bytes) automatically. + * | | |If PSIZE (NFI_NANDCTL[17:16]) = 2'b10, this field will be set 0x80 (128 bytes) automatically. + * | | |If PSIZE (NFI_NANDCTL[17:16]) = 2'b11, this field will be set 0x100 (256bytes) automatically. + * | | |Note: The REA128EN must be 4 byte aligned, so bit1 and bit0 can't be filled 1 to it. + * | | |The maximum redundant area of the controller is 472Bytes. + * |[31:16] |MECC |Mask ECC During Write Page Data + * | | |These 16 bits registers indicate NAND controller to write out ECC parity or just 0xFF for each field (every 512 bytes) the real parity data will be write out to NFI_NANDRAx. + * | | |0x00 = Do not mask the ECC parity for each field. + * | | |0x01 = Mask ECC parity and write out FF to NAND ECC parity for 512 Bytes page size or 2K/4K/8K page size first 512 field. + * | | |0x02 = Mask ECC parity and write out FF to NAND ECC parity for 512 Bytes page size or 2K/4K/8K page size second 512 field. + * | | |Others = Mask ECC parity and write out FF to NAND ECC parity for 512 Bytes page size or 2K/4K/8K page size each 512 field. + * @var NFI_T::NANDECTL + * Offset: 0x8C0 NAND Flash Extend Control Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[0] |WP |NAND Flash Write Protect Control + * | | |Set this bit low (low active) to make NAND_nWP functional pin low to prevent the write to NAND Flash device. + * | | |0 = NAND Flash is write-protected and is not writeable. + * | | |1 = NAND Flash is not write-protected and is writeable. + * @var NFI_T::NANDECCES0 + * Offset: 0x8D0 NAND Flash ECC Error Status 0 Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[1:0] |F1STAT |ECC Status of Field 1 + * | | |This field contains the ECC correction status (BCH algorithm) of ECC-field 1. + * | | |00 = No error. + * | | |01 = Correctable error. + * | | |10 = Uncorrectable error. + * | | |11 = Reserved. + * |[6:2] |F1ECNT |Error Count of ECC Field 1 + * | | |This field contains the error counts after ECC correct calculation of Field 1 + * | | |For this ECC core (BCH algorithm), only when F1STAT equals to 0x01, the value in this field is meaningful + * | | |F1ECNT means how many errors depending on which ECC is used. + * |[9:8] |F2STAT |ECC Status of Field 2 + * | | |This field contains the ECC correction status (BCH algorithm) of ECC-field 2. + * | | |00 = No error. + * | | |01 = Correctable error. + * | | |10 = Uncorrectable error. + * | | |11 = Reserved. + * |[14:10] |F2ECNT |Error Count of ECC Field 2 + * | | |This field contains the error counts after ECC correct calculation of Field 2 + * | | |For this ECC core (BCH algorithm), only when F2STAT equals to 0x01, the value in this field is meaningful + * | | |F2ECNT means how many errors depending on which ECC is used. + * |[17:16] |F3STAT |ECC Status of Field 3 + * | | |This field contains the ECC correction status (BCH algorithm) of ECC-field 3. + * | | |00 = No error. + * | | |01 = Correctable error. + * | | |10 = Uncorrectable error. + * | | |11 = Reserved. + * |[22:18] |F3ECNT |Error Count of ECC Field 3 + * | | |This field contains the error counts after ECC correct calculation of Field 3 + * | | |For this ECC core (BCH algorithm), only when F3STAT equals to 0x01, the value in this field is meaningful + * | | |F3ECNT means how many errors depending on which ECC is used. + * |[25:24] |F4STAT |ECC Status of Field 4 + * | | |This field contains the ECC correction status (BCH algorithm) of ECC-field 4. + * | | |00 = No error. + * | | |01 = Correctable error. + * | | |10 = Uncorrectable error. + * | | |11 = Reserved. + * |[30:26] |F4ECNT |Error Count of ECC Field 4 + * | | |This field contains the error counts after ECC correct calculation of Field 4 + * | | |For this ECC core (BCH algorithm), only when F4STAT equals to 0x01, the value in this field is meaningful + * | | |F4ECNT means how many errors depending on which ECC is used. + * @var NFI_T::NANDECCES1 + * Offset: 0x8D4 NAND Flash ECC Error Status 1 Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[1:0] |F5STAT |ECC Status of Field 5 + * | | |This field contains the ECC correction status (BCH algorithm) of ECC-field5. + * | | |00 = No error. + * | | |01 = Correctable error. + * | | |10 = Uncorrectable error. + * | | |11 = Reserved. + * |[6:2] |F5ECNT |Error Count of ECC Field 5 + * | | |This field contains the error counts after ECC correct calculation of Field 5 + * | | |For this ECC core (BCH algorithm), only when F5STAT equals to 0x01, the value in this field is meaningful + * | | |F5ECNT means how many errors depending on which ECC is used. + * |[9:8] |F6STAT |ECC Status of Field 6 + * | | |This field contains the ECC correction status (BCH algorithm) of ECC-field 6. + * | | |00 = No error. + * | | |01 = Correctable error. + * | | |10 = Uncorrectable error. + * | | |11 = Reserved. + * |[14:10] |F6ECNT |Error Count of ECC Field 6 + * | | |This field contains the error counts after ECC correct calculation of Field 6 + * | | |For this ECC core (BCH algorithm), only when F6STAT equals to 0x01, the value in this field is meaningful + * | | |F6ECNT means how many errors depending on which ECC is used. + * |[17:16] |F7STAT |ECC Status of Field 7 + * | | |This field contains the ECC correction status (BCH algorithm) of ECC-field 7. + * | | |00 = No error. + * | | |01 = Correctable error. + * | | |10 = Uncorrectable error. + * | | |11 = Reserved. + * |[22:18] |F7ECNT |Error Count of ECC Field 7 + * | | |This field contains the error counts after ECC correct calculation of Field 7 + * | | |For this ECC core (BCH algorithm), only when F7STAT equals to 0x01, the value in this field is meaningful + * | | |F7ECNT means how many errors depending on which ECC is used. + * |[25:24] |F8STAT |ECC Status of Field 8 + * | | |This field contains the ECC correction status (BCH algorithm) of ECC-field 8. + * | | |00 = No error. + * | | |01 = Correctable error. + * | | |10 = Uncorrectable error. + * | | |11 = Reserved. + * |[30:26] |F8ECNT |Error Count of ECC Field 8 + * | | |This field contains the error counts after ECC correct calculation of Field 8 + * | | |For this ECC core (BCH algorithm), only when F8STAT equals to 0x01, the value in this field is meaningful + * | | |F8ECNT means how many errors depending on which ECC is used. + * @var NFI_T::NANDECCES2 + * Offset: 0x8D8 NAND Flash ECC Error Status 2 Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[1:0] |F9STAT |ECC Status of Field 9 + * | | |This field contains the ECC correction status (BCH algorithm) of ECC-field 9. + * | | |00 = No error. + * | | |01 = Correctable error. + * | | |10 = Uncorrectable error. + * | | |11 = Reserved. + * |[6:2] |F9ECNT |Error Count of ECC Field 9 + * | | |This field contains the error counts after ECC correct calculation of Field 9 + * | | |For this ECC core (BCH algorithm), only when F9STAT equals to 0x01, the value in this field is meaningful + * | | |F9ECNT means how many errors depending on which ECC is used. + * |[9:8] |F10STAT |ECC Status of Field 10 + * | | |This field contains the ECC correction status (BCH algorithm) of ECC-field 10. + * | | |00 = No error. + * | | |01 = Correctable error. + * | | |10 = Uncorrectable error. + * | | |11 = Reserved. + * |[14:10] |F10ECNT |Error Count of ECC Field 10 + * | | |This field contains the error counts after ECC correct calculation of Field 10 + * | | |For this ECC core (BCH algorithm), only when F10STAT equals to 0x01, the value in this field is meaningful + * | | |F10ECNT means how many errors depending on which ECC is used. + * |[17:16] |F11STAT |ECC Status of Field 11 + * | | |This field contains the ECC correction status (BCH algorithm) of ECC-field 11. + * | | |00 = No error. + * | | |01 = Correctable error. + * | | |10 = Uncorrectable error. + * | | |11 = Reserved. + * |[22:18] |F11ECNT |Error Count of ECC Field 11 + * | | |This field contains the error counts after ECC correct calculation of Field 11 + * | | |For this ECC core (BCH algorithm), only when F11STAT equals to 0x01, the value in this field is meaningful + * | | |F11ECNT means how many errors depending on which ECC is used. + * |[25:24] |F12STAT |ECC Status of Field 12 + * | | |This field contains the ECC correction status (BCH algorithm) of ECC-field 12. + * | | |00 = No error. + * | | |01 = Correctable error. + * | | |10 = Uncorrectable error. + * | | |11 = Reserved. + * |[30:26] |F12ECNT |Error Count of ECC Field 12 + * | | |This field contains the error counts after ECC correct calculation of Field 12 + * | | |For this ECC core (BCH algorithm), only when F12STAT equals to 0x01, the value in this field is meaningful + * | | |F12ECNT means how many errors depending on which ECC is used. + * @var NFI_T::NANDECCES3 + * Offset: 0x8DC NAND Flash ECC Error Status 3 Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[1:0] |F13STAT |ECC Status of Field 13 + * | | |This field contains the ECC correction status (BCH algorithm) of ECC-field 13. + * | | |00 = No error. + * | | |01 = Correctable error. + * | | |10 = Uncorrectable error. + * | | |11 = Reserved. + * |[6:2] |F13ECNT |Error Count of ECC Field 13 + * | | |This field contains the error counts after ECC correct calculation of Field 13 + * | | |For this ECC core (BCH algorithm), only when F13STAT equals to 0x01, the value in this field is meaningful + * | | |F13ECNT means how many errors depending on which ECC is used. + * |[9:8] |F14STAT |ECC Status of Field 14 + * | | |This field contains the ECC correction status (BCH algorithm) of ECC-field 14. + * | | |00 = No error. + * | | |01 = Correctable error. + * | | |10 = Uncorrectable error. + * | | |11 = Reserved. + * |[14:10] |F14ECNT |Error Count of ECC Field 14 + * | | |This field contains the error counts after ECC correct calculation of Field 14 + * | | |For this ECC core (BCH algorithm), only when F14STAT equals to 0x01, the value in this field is meaningful + * | | |F14ECNT means how many errors depending on which ECC is used. + * |[17:16] |F15STAT |ECC Status of Field 15 + * | | |This field contains the ECC correction status (BCH algorithm) of ECC-field 15. + * | | |00 = No error. + * | | |01 = Correctable error. + * | | |10 = Uncorrectable error. + * | | |11 = Reserved. + * |[22:18] |F15ECNT |Error Count of ECC Field 15 + * | | |This field contains the error counts after ECC correct calculation of Field 15 + * | | |For this ECC core (BCH algorithm), only when F15STAT equals to 0x01, the value in this field is meaningful + * | | |F15ECNT means how many errors depending on which ECC is used. + * |[25:24] |F16STAT |ECC Status of Field 16 + * | | |This field contains the ECC correction status (BCH algorithm) of ECC-field 16. + * | | |00 = No error. + * | | |01 = Correctable error. + * | | |10 = Uncorrectable error. + * | | |11 = Reserved. + * |[30:26] |F16ECNT |Error Count of ECC Field 16 + * | | |This field contains the error counts after ECC correct calculation of Field 16 + * | | |For this ECC core (BCH algorithm), only when F16STAT equals to 0x01, the value in this field is meaningful + * | | |F16ECNT means how many errors depending on which ECC is used. + * @var NFI_T::NANDECCEA0 + * Offset: 0x900 NAND Flash ECC Error Byte Address 0 Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[10:0] |ERRADDR0 |ECC Error Address First Field of Error 0 + * | | |This field contains an 11-bit ECC error address 0 of first field + * | | |If it is a correctable error, please read the error data, ERRDATA0 (NFI_NANDECCED0[7:0]), to correct this error. + * |[26:16] |ERRADDR1 |ECC Error Address First Field of Error 1 + * | | |This field contains an 11-bit ECC error address 1 of first field + * | | |If it is a correctable error, please read the error data, ERRDATA1 (NFI_NANDECCED0[15:8]), to correct this error. + * @var NFI_T::NANDECCEA1 + * Offset: 0x904 NAND Flash ECC Error Byte Address 1 Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[10:0] |ERRADDR2 |ECC Error Address First Field of Error 2 + * | | |This field contains an 11-bit ECC error address 2 of first field + * | | |If it is a correctable error, please read the error data, ERRDATA2 (NFI_NANDECCED0[23:16]), to correct this error. + * |[26:16] |ERRADDR3 |ECC Error Address First Field of Error 3 + * | | |This field contains an 11-bit ECC error address 3 of first field + * | | |If it is a correctable error, please read the error data, ERRDATA3 (NFI_NANDECCED0[31:24]), to correct this error. + * @var NFI_T::NANDECCEA2 + * Offset: 0x908 NAND Flash ECC Error Byte Address 2 Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[10:0] |ERRADDR4 |ECC Error Address First Field of Error 4 + * | | |This field contains an 11-bit ECC error address 4 of first field + * | | |If it is a correctable error, please read the error data, ERRDATA4 (NFI_NANDECCED1[7:0]), to correct this error. + * |[26:16] |ERRADDR5 |ECC Error Address First Field of Error 5 + * | | |This field contains an 11-bit ECC error address 5 of first field + * | | |If it is a correctable error, please read the error data, ERRDATA5 (NFI_NANDECCED1[15:8]), to correct this error. + * @var NFI_T::NANDECCEA3 + * Offset: 0x90C NAND Flash ECC Error Byte Address 3 Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[10:0] |ERRADDR6 |ECC Error Address First Field of Error 6 + * | | |This field contains an 11-bit ECC error address 6 of first field + * | | |If it is a correctable error, please read the error data, ERRDATA6 (NFI_NANDECCED1[23:16]), to correct this error. + * |[26:16] |ERRADDR7 |ECC Error Address First Field of Error 7 + * | | |This field contains an 11-bit ECC error address 7 of first field + * | | |If it is a correctable error, please read the error data, ERRDATA7 (NFI_NANDECCED1[31:24]), to correct this error. + * @var NFI_T::NANDECCEA4 + * Offset: 0x910 NAND Flash ECC Error Byte Address 4 Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[10:0] |ERRADDR8 |ECC Error Address First Field of Error 8 + * | | |This field contains an 11-bit ECC error address 8 of first field + * | | |If it is a correctable error, please read the error data, ERRDATA8 (NFI_NANDECCED2[7:0]), to correct this error. + * |[26:16] |ERRADDR9 |ECC Error Address First Field of Error 9 + * | | |This field contains an 11-bit ECC error address 9 of first field + * | | |If it is a correctable error, please read the error data, ERRDATA9 (NFI_NANDECCED2[15:8]), to correct this error. + * @var NFI_T::NANDECCEA5 + * Offset: 0x914 NAND Flash ECC Error Byte Address 5 Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[10:0] |ERRADDR10 |ECC Error Address First Field of Error 10 + * | | |This field contains an 11-bit ECC error address 10 of first field + * | | |If it is a correctable error, please read the error data, ERRDATA10 (NFI_NANDECCED2[23:16]), to correct this error. + * |[26:16] |ERRADDR11 |ECC Error Address First Field of Error 11 + * | | |This field contains an 11-bit ECC error address 11 of first field + * | | |If it is a correctable error, please read the error data, ERRDATA11 (NFI_NANDECCED2[31:24]), to correct this error. + * @var NFI_T::NANDECCEA6 + * Offset: 0x918 NAND Flash ECC Error Byte Address 6 Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[10:0] |ERRADDR12 |ECC Error Address First Field of Error 12 + * | | |This field contains an 11-bit ECC error address 12 of first field + * | | |If it is a correctable error, please read the error data, ERRDATA12 (NFI_NANDECCED3[7:0]), to correct this error. + * |[26:16] |ERRADDR13 |ECC Error Address First Field of Error 13 + * | | |This field contains an 11-bit ECC error address 13 of first field + * | | |If it is a correctable error, please read the error data, ERRDATA13 (NFI_NANDECCED3[15:8]), to correct this error. + * @var NFI_T::NANDECCEA7 + * Offset: 0x91C NAND Flash ECC Error Byte Address 7 Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[10:0] |ERRADDR14 |ECC Error Address First Field of Error 14 + * | | |This field contains an 11-bit ECC error address 14 of first field + * | | |If it is a correctable error, please read the error data, ERRDATA14 (NFI_NANDECCED3[23:16]), to correct this error. + * |[26:16] |ERRADDR15 |ECC Error Address First Field of Error 15 + * | | |This field contains an 11-bit ECC error address 15 of first field + * | | |If it is a correctable error, please read the error data, ERRDATA15 (NFI_NANDECCED3[31:24]), to correct this error. + * @var NFI_T::NANDECCEA8 + * Offset: 0x920 NAND Flash ECC Error Byte Address 8 Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[10:0] |ERRADDR16 |ECC Error Address First Field of Error 16 + * | | |This field contains an 11-bit ECC error address 16 of first field + * | | |If it is a correctable error, please read the error data, ERRDATA16 (NFI_NANDECCED4[7:0]), to correct this error. + * |[26:16] |ERRADDR17 |ECC Error Address First Field of Error 17 + * | | |This field contains an 11-bit ECC error address 17 of first field + * | | |If it is a correctable error, please read the error data, ERRDATA17 (NFI_NANDECCED4[15:8]), to correct this error. + * @var NFI_T::NANDECCEA9 + * Offset: 0x924 NAND Flash ECC Error Byte Address 9 Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[10:0] |ERRADDR18 |ECC Error Address First Field of Error 18 + * | | |This field contains an 11-bit ECC error address 18 of first field + * | | |If it is a correctable error, please read the error data, ERRDATA18 (NFI_NANDECCED4[23:16]), to correct this error. + * |[26:16] |ERRADDR19 |ECC Error Address First Field of Error 19 + * | | |This field contains an 11-bit ECC error address 19 of first field + * | | |If it is a correctable error, please read the error data, ERRDATA19 (NFI_NANDECCED4[31:24]), to correct this error. + * @var NFI_T::NANDECCEA10 + * Offset: 0x928 NAND Flash ECC Error Byte Address 10 Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[10:0] |ERRADDR20 |ECC Error Address First Field of Error 20 + * | | |This field contains an 11-bit ECC error address 20 of first field + * | | |If it is a correctable error, please read the error data, ERRDATA20 (NFI_NANDECCED5[7:0]), to correct this error. + * |[26:16] |ERRADDR21 |ECC Error Address First Field of Error 21 + * | | |This field contains an 11-bit ECC error address 21 of first field + * | | |If it is a correctable error, please read the error data, ERRDATA21 (NFI_NANDECCED5[15:8]), to correct this error. + * @var NFI_T::NANDECCEA11 + * Offset: 0x92C NAND Flash ECC Error Byte Address 11 Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[10:0] |ERRADDR22 |ECC Error Address First Field of Error 22 + * | | |This field contains an 11-bit ECC error address 22 of first field + * | | |If it is a correctable error, please read the error data, ERRDATA22 (NFI_NANDECCED5[23:16]), to correct this error. + * |[26:16] |ERRADDR23 |ECC Error Address First Field of Error 23 + * | | |This field contains an 11-bit ECC error address 23 of first field + * | | |If it is a correctable error, please read the error data, ERRDATA23 (NFI_NANDECCED5[31:24]), to correct this error. + * @var NFI_T::NANDECCED0 + * Offset: 0x960 NAND Flash ECC Error Data Register 0 + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[7:0] |ERRDATA0 |ECC Error Data of First Field 0 + * | | |This field contains an 8-bit BCH ECC error data 0 of first field + * | | |If it is a correctable error, please read out the error data in this field and doing bitwise XOR with received data locating at address ERRADDR0 (NFI_ANNDECCEA0[10:0]), and then the result will be the correct data. + * |[15:8] |ERRDATA1 |ECC Error Data of First Field 1 + * | | |This field contains an 8-bit BCH ECC error data 1 of first field + * | | |If it is a correctable error, please read out the error data in this field and doing bitwise XOR with received data locating at address ERRADDR1 (NFI_NANDECCEA0[26:16]), and then the result will be the correct data. + * |[23:16] |ERRDATA2 |ECC Error Data of First Field 2 + * | | |This field contains an 8-bit BCH ECC error data 2 of first field + * | | |If it is a correctable error, please read out the error data in this field and doing bitwise XOR with received data locating at address ERRADDR2 (NFI_NANDECCEA1[10:0]), and then the result will be the correct data. + * |[31:24] |ERRDATA3 |ECC Error Data of First Field 3 + * | | |This field contains an 8-bit BCH ECC error data 3 of first field + * | | |If it is a correctable error, please read out the error data in this field and doing bitwise XOR with received data locating at address ERRADDR3 (NFI_NANDECCEA1[26:16]), and then the result will be the correct data. + * @var NFI_T::NANDECCED1 + * Offset: 0x964 NAND Flash ECC Error Data Register 1 + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[7:0] |ERRDATA4 |ECC Error Data of First Field 4 + * | | |This field contains an 8-bit BCH ECC error data 4 of first field + * | | |If it is a correctable error, please read out the error data in this field and doing bitwise XOR with received data locating at address ERRADDR4 (NFI_NANDECCEA2[10:0]), and then the result will be the correct data. + * |[15:8] |ERRDATA5 |ECC Error Data of First Field 5 + * | | |This field contains an 8-bit BCH ECC error data 5 of first field + * | | |If it is a correctable error, please read out the error data in this field and doing bitwise XOR with received data locating at address ERRADDR5 (NFI_NANDECCEA2[26:16]), and then the result will be the correct data. + * |[23:16] |ERRDATA6 |ECC Error Data of First Field 6 + * | | |This field contains an 8-bit BCH ECC error data 6 of first field + * | | |If it is a correctable error, please read out the error data in this field and doing bitwise XOR with received data locating at address ERRADDR6 (NFI_NANDECCEA3[10:0]), and then the result will be the correct data. + * |[31:24] |ERRDATA7 |ECC Error Data of First Field 7 + * | | |This field contains an 8-bit BCH ECC error data 7 of first field + * | | |If it is a correctable error, please read out the error data in this field and doing bitwise XOR with received data locating at address ERRADDR7 (NFI_NANDECCEA3[26:16]), and then the result will be the correct data. + * @var NFI_T::NANDECCED2 + * Offset: 0x968 NAND Flash ECC Error Data Register 2 + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[7:0] |ERRDATA8 |ECC Error Data of First Field 8 + * | | |This field contains an 8-bit BCH ECC error data 8 of first field + * | | |If it is a correctable error, please read out the error data in this field and doing bitwise XOR with received data locating at address ERRADDR8 (NFI_NANDECCEA4[10:0]), and then the result will be the correct data. + * |[15:8] |ERRDATA9 |ECC Error Data of First Field 9 + * | | |This field contains an 8-bit BCH ECC error data 9 of first field + * | | |If it is a correctable error, please read out the error data in this field and doing bitwise XOR with received data locating at address ERRADDR9 (NFI_NANDECCEA4[26:16]), and then the result will be the correct data. + * |[23:16] |ERRDATA10 |ECC Error Data of First Field 10 + * | | |This field contains an 8-bit BCH ECC error data 10 of first field + * | | |If it is a correctable error, please read out the error data in this field and doing bitwise XOR with received data locating at address ERRADDR10 (NFI_NANDECCEA5[10:0]), and then the result will be the correct data. + * |[31:24] |ERRDATA11 |ECC Error Data of First Field 11 + * | | |This field contains an 8-bit BCH ECC error data 11 of first field + * | | |If it is a correctable error, please read out the error data in this field and doing bitwise XOR with received data locating at address ERRADDR11 (NFI_NANDECCEA5[26:16]), and then the result will be the correct data. + * @var NFI_T::NANDECCED3 + * Offset: 0x96C NAND Flash ECC Error Data Register 3 + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[7:0] |ERRDATA12 |ECC Error Data of First Field 12 + * | | |This field contains an 8-bit BCH ECC error data 12 of first field + * | | |If it is a correctable error, please read out the error data in this field and doing bitwise XOR with received data locating at address ERRADDR12 (NFI_NANDECCEA6[10:0]), and then the result will be the correct data. + * |[15:8] |ERRDATA13 |ECC Error Data of First Field 13 + * | | |This field contains an 8-bit BCH ECC error data 13 of first field + * | | |If it is a correctable error, please read out the error data in this field and doing bitwise XOR with received data locating at address ERRADDR13 (NFI_NANDECCEA6[26:16]), and then the result will be the correct data. + * |[23:16] |ERRDATA14 |ECC Error Data of First Field 14 + * | | |This field contains an 8-bit BCH ECC error data 14 of first field + * | | |If it is a correctable error, please read out the error data in this field and doing bitwise XOR with received data locating at address ERRADDR14 (NFI_NANDECCEA7[10:0]), and then the result will be the correct data. + * |[31:24] |ERRDATA15 |ECC Error Data of First Field 15 + * | | |This field contains an 8-bit BCH ECC error data 15 of first field + * | | |If it is a correctable error, please read out the error data in this field and doing bitwise XOR with received data locating at address ERRADDR15 (NFI_NANDECCEA7[26:16]), and then the result will be the correct data. + * @var NFI_T::NANDECCED4 + * Offset: 0x970 NAND Flash ECC Error Data Register 4 + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[7:0] |ERRDATA16 |ECC Error Data of First Field 16 + * | | |This field contains an 8-bit BCH ECC error data 16 of first field + * | | |If it is a correctable error, please read out the error data in this field and doing bitwise XOR with received data locating at address ERRADDR16 (NFI_NANDECCEA8[10:0]), and then the result will be the correct data. + * |[15:8] |ERRDATA17 |ECC Error Data of First Field 17 + * | | |This field contains an 8-bit BCH ECC error data 17 of first field + * | | |If it is a correctable error, please read out the error data in this field and doing bitwise XOR with received data locating at address ERRADDR17 (NFI_NANDECCEA8[26:16]), and then the result will be the correct data. + * |[23:16] |ERRDATA18 |ECC Error Data of First Field 18 + * | | |This field contains an 8-bit BCH ECC error data 18 of first field + * | | |If it is a correctable error, please read out the error data in this field and doing bitwise XOR with received data locating at address ERRADDR18 (NFI_NANDECCEA9[10:0]), and then the result will be the correct data. + * |[31:24] |ERRDATA19 |ECC Error Data of First Field 19 + * | | |This field contains an 8-bit BCH ECC error data 19 of first field + * | | |If it is a correctable error, please read out the error data in this field and doing bitwise XOR with received data locating at address ERRADDR19 (NFI_NANDECCEA9[26:16]), and then the result will be the correct data. + * @var NFI_T::NANDECCED5 + * Offset: 0x974 NAND Flash ECC Error Data Register 5 + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[7:0] |ERRDATA20 |ECC Error Data of First Field 20 + * | | |This field contains an 8-bit BCH ECC error data 20 of first field + * | | |If it is a correctable error, please read out the error data in this field and doing bitwise XOR with received data locating at address ERRADDR20 (NFI_NANDECCEA10[10:0]), and then the result will be the correct data. + * |[15:8] |ERRDATA21 |ECC Error Data of First Field 21 + * | | |This field contains an 8-bit BCH ECC error data 21 of first field + * | | |If it is a correctable error, please read out the error data in this field and doing bitwise XOR with received data locating at address ERRADDR21 (NFI_NANDECCEA10[26:16]), and then the result will be the correct data. + * |[23:16] |ERRDATA22 |ECC Error Data of First Field 22 + * | | |This field contains an 8-bit BCH ECC error data 22 of first field + * | | |If it is a correctable error, please read out the error data in this field and doing bitwise XOR with received data locating at address ERRADDR22 (NFI_NANDECCEA11[10:0]), and then the result will be the correct data. + * |[31:24] |ERRDATA23 |ECC Error Data of First Field 23 + * | | |This field contains an 8-bit BCH ECC error data 23 of first field + * | | |If it is a correctable error, please read out the error data in this field and doing bitwise XOR with received data locating at address ERRADDR23 (NFI_NANDECCEA11[26:16]), and then the result will be the correct data. + * @var NFI_T::NANDRA0 + * Offset: 0xA00 NAND Flash Redundant Area Word n + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[31:0] |Data |NAND Flash Redundant Area Word n + * | | |This field indicates a 32-bit data of redundant area. + * @var NFI_T::NANDRA1 + * Offset: 0xA04 NAND Flash Redundant Area Word n + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[31:0] |Data |NAND Flash Redundant Area Word n + * | | |This field indicates a 32-bit data of redundant area. + * @var NFI_T::NANDRA2 + * Offset: 0xA08 NAND Flash Redundant Area Word n + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[31:0] |Data |NAND Flash Redundant Area Word n + * | | |This field indicates a 32-bit data of redundant area. + * @var NFI_T::NANDRA3 + * Offset: 0xA0C NAND Flash Redundant Area Word n + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[31:0] |Data |NAND Flash Redundant Area Word n + * | | |This field indicates a 32-bit data of redundant area. + * @var NFI_T::NANDRA4 + * Offset: 0xA10 NAND Flash Redundant Area Word n + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[31:0] |Data |NAND Flash Redundant Area Word n + * | | |This field indicates a 32-bit data of redundant area. + * @var NFI_T::NANDRA5 + * Offset: 0xA14 NAND Flash Redundant Area Word n + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[31:0] |Data |NAND Flash Redundant Area Word n + * | | |This field indicates a 32-bit data of redundant area. + * @var NFI_T::NANDRA6 + * Offset: 0xA18 NAND Flash Redundant Area Word n + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[31:0] |Data |NAND Flash Redundant Area Word n + * | | |This field indicates a 32-bit data of redundant area. + * @var NFI_T::NANDRA7 + * Offset: 0xA1C NAND Flash Redundant Area Word n + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[31:0] |Data |NAND Flash Redundant Area Word n + * | | |This field indicates a 32-bit data of redundant area. + * @var NFI_T::NANDRA8 + * Offset: 0xA20 NAND Flash Redundant Area Word n + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[31:0] |Data |NAND Flash Redundant Area Word n + * | | |This field indicates a 32-bit data of redundant area. + * @var NFI_T::NANDRA9 + * Offset: 0xA24 NAND Flash Redundant Area Word n + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[31:0] |Data |NAND Flash Redundant Area Word n + * | | |This field indicates a 32-bit data of redundant area. + * @var NFI_T::NANDRA10 + * Offset: 0xA28 NAND Flash Redundant Area Word n + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[31:0] |Data |NAND Flash Redundant Area Word n + * | | |This field indicates a 32-bit data of redundant area. + * @var NFI_T::NANDRA11 + * Offset: 0xA2C NAND Flash Redundant Area Word n + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[31:0] |Data |NAND Flash Redundant Area Word n + * | | |This field indicates a 32-bit data of redundant area. + * @var NFI_T::NANDRA12 + * Offset: 0xA30 NAND Flash Redundant Area Word n + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[31:0] |Data |NAND Flash Redundant Area Word n + * | | |This field indicates a 32-bit data of redundant area. + * @var NFI_T::NANDRA13 + * Offset: 0xA34 NAND Flash Redundant Area Word n + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[31:0] |Data |NAND Flash Redundant Area Word n + * | | |This field indicates a 32-bit data of redundant area. + * @var NFI_T::NANDRA14 + * Offset: 0xA38 NAND Flash Redundant Area Word n + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[31:0] |Data |NAND Flash Redundant Area Word n + * | | |This field indicates a 32-bit data of redundant area. + * @var NFI_T::NANDRA15 + * Offset: 0xA3C NAND Flash Redundant Area Word n + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[31:0] |Data |NAND Flash Redundant Area Word n + * | | |This field indicates a 32-bit data of redundant area. + * @var NFI_T::NANDRA16 + * Offset: 0xA40 NAND Flash Redundant Area Word n + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[31:0] |Data |NAND Flash Redundant Area Word n + * | | |This field indicates a 32-bit data of redundant area. + * @var NFI_T::NANDRA17 + * Offset: 0xA44 NAND Flash Redundant Area Word n + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[31:0] |Data |NAND Flash Redundant Area Word n + * | | |This field indicates a 32-bit data of redundant area. + * @var NFI_T::NANDRA18 + * Offset: 0xA48 NAND Flash Redundant Area Word n + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[31:0] |Data |NAND Flash Redundant Area Word n + * | | |This field indicates a 32-bit data of redundant area. + * @var NFI_T::NANDRA19 + * Offset: 0xA4C NAND Flash Redundant Area Word n + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[31:0] |Data |NAND Flash Redundant Area Word n + * | | |This field indicates a 32-bit data of redundant area. + * @var NFI_T::NANDRA20 + * Offset: 0xA50 NAND Flash Redundant Area Word n + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[31:0] |Data |NAND Flash Redundant Area Word n + * | | |This field indicates a 32-bit data of redundant area. + * @var NFI_T::NANDRA21 + * Offset: 0xA54 NAND Flash Redundant Area Word n + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[31:0] |Data |NAND Flash Redundant Area Word n + * | | |This field indicates a 32-bit data of redundant area. + * @var NFI_T::NANDRA22 + * Offset: 0xA58 NAND Flash Redundant Area Word n + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[31:0] |Data |NAND Flash Redundant Area Word n + * | | |This field indicates a 32-bit data of redundant area. + * @var NFI_T::NANDRA23 + * Offset: 0xA5C NAND Flash Redundant Area Word n + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[31:0] |Data |NAND Flash Redundant Area Word n + * | | |This field indicates a 32-bit data of redundant area. + * @var NFI_T::NANDRA24 + * Offset: 0xA60 NAND Flash Redundant Area Word n + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[31:0] |Data |NAND Flash Redundant Area Word n + * | | |This field indicates a 32-bit data of redundant area. + * @var NFI_T::NANDRA25 + * Offset: 0xA64 NAND Flash Redundant Area Word n + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[31:0] |Data |NAND Flash Redundant Area Word n + * | | |This field indicates a 32-bit data of redundant area. + * @var NFI_T::NANDRA26 + * Offset: 0xA68 NAND Flash Redundant Area Word n + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[31:0] |Data |NAND Flash Redundant Area Word n + * | | |This field indicates a 32-bit data of redundant area. + * @var NFI_T::NANDRA27 + * Offset: 0xA6C NAND Flash Redundant Area Word n + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[31:0] |Data |NAND Flash Redundant Area Word n + * | | |This field indicates a 32-bit data of redundant area. + * @var NFI_T::NANDRA28 + * Offset: 0xA70 NAND Flash Redundant Area Word n + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[31:0] |Data |NAND Flash Redundant Area Word n + * | | |This field indicates a 32-bit data of redundant area. + * @var NFI_T::NANDRA29 + * Offset: 0xA74 NAND Flash Redundant Area Word n + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[31:0] |Data |NAND Flash Redundant Area Word n + * | | |This field indicates a 32-bit data of redundant area. + * @var NFI_T::NANDRA30 + * Offset: 0xA78 NAND Flash Redundant Area Word n + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[31:0] |Data |NAND Flash Redundant Area Word n + * | | |This field indicates a 32-bit data of redundant area. + * @var NFI_T::NANDRA31 + * Offset: 0xA7C NAND Flash Redundant Area Word n + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[31:0] |Data |NAND Flash Redundant Area Word n + * | | |This field indicates a 32-bit data of redundant area. + * @var NFI_T::NANDRA32 + * Offset: 0xA80 NAND Flash Redundant Area Word n + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[31:0] |Data |NAND Flash Redundant Area Word n + * | | |This field indicates a 32-bit data of redundant area. + * @var NFI_T::NANDRA33 + * Offset: 0xA84 NAND Flash Redundant Area Word n + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[31:0] |Data |NAND Flash Redundant Area Word n + * | | |This field indicates a 32-bit data of redundant area. + * @var NFI_T::NANDRA34 + * Offset: 0xA88 NAND Flash Redundant Area Word n + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[31:0] |Data |NAND Flash Redundant Area Word n + * | | |This field indicates a 32-bit data of redundant area. + * @var NFI_T::NANDRA35 + * Offset: 0xA8C NAND Flash Redundant Area Word n + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[31:0] |Data |NAND Flash Redundant Area Word n + * | | |This field indicates a 32-bit data of redundant area. + * @var NFI_T::NANDRA36 + * Offset: 0xA90 NAND Flash Redundant Area Word n + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[31:0] |Data |NAND Flash Redundant Area Word n + * | | |This field indicates a 32-bit data of redundant area. + * @var NFI_T::NANDRA37 + * Offset: 0xA94 NAND Flash Redundant Area Word n + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[31:0] |Data |NAND Flash Redundant Area Word n + * | | |This field indicates a 32-bit data of redundant area. + * @var NFI_T::NANDRA38 + * Offset: 0xA98 NAND Flash Redundant Area Word n + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[31:0] |Data |NAND Flash Redundant Area Word n + * | | |This field indicates a 32-bit data of redundant area. + * @var NFI_T::NANDRA39 + * Offset: 0xA9C NAND Flash Redundant Area Word n + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[31:0] |Data |NAND Flash Redundant Area Word n + * | | |This field indicates a 32-bit data of redundant area. + * @var NFI_T::NANDRA40 + * Offset: 0xAA0 NAND Flash Redundant Area Word n + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[31:0] |Data |NAND Flash Redundant Area Word n + * | | |This field indicates a 32-bit data of redundant area. + * @var NFI_T::NANDRA41 + * Offset: 0xAA4 NAND Flash Redundant Area Word n + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[31:0] |Data |NAND Flash Redundant Area Word n + * | | |This field indicates a 32-bit data of redundant area. + * @var NFI_T::NANDRA42 + * Offset: 0xAA8 NAND Flash Redundant Area Word n + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[31:0] |Data |NAND Flash Redundant Area Word n + * | | |This field indicates a 32-bit data of redundant area. + * @var NFI_T::NANDRA43 + * Offset: 0xAAC NAND Flash Redundant Area Word n + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[31:0] |Data |NAND Flash Redundant Area Word n + * | | |This field indicates a 32-bit data of redundant area. + * @var NFI_T::NANDRA44 + * Offset: 0xAB0 NAND Flash Redundant Area Word n + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[31:0] |Data |NAND Flash Redundant Area Word n + * | | |This field indicates a 32-bit data of redundant area. + * @var NFI_T::NANDRA45 + * Offset: 0xAB4 NAND Flash Redundant Area Word n + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[31:0] |Data |NAND Flash Redundant Area Word n + * | | |This field indicates a 32-bit data of redundant area. + * @var NFI_T::NANDRA46 + * Offset: 0xAB8 NAND Flash Redundant Area Word n + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[31:0] |Data |NAND Flash Redundant Area Word n + * | | |This field indicates a 32-bit data of redundant area. + * @var NFI_T::NANDRA47 + * Offset: 0xABC NAND Flash Redundant Area Word n + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[31:0] |Data |NAND Flash Redundant Area Word n + * | | |This field indicates a 32-bit data of redundant area. + * @var NFI_T::NANDRA48 + * Offset: 0xAC0 NAND Flash Redundant Area Word n + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[31:0] |Data |NAND Flash Redundant Area Word n + * | | |This field indicates a 32-bit data of redundant area. + * @var NFI_T::NANDRA49 + * Offset: 0xAC4 NAND Flash Redundant Area Word n + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[31:0] |Data |NAND Flash Redundant Area Word n + * | | |This field indicates a 32-bit data of redundant area. + * @var NFI_T::NANDRA50 + * Offset: 0xAC8 NAND Flash Redundant Area Word n + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[31:0] |Data |NAND Flash Redundant Area Word n + * | | |This field indicates a 32-bit data of redundant area. + * @var NFI_T::NANDRA51 + * Offset: 0xACC NAND Flash Redundant Area Word n + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[31:0] |Data |NAND Flash Redundant Area Word n + * | | |This field indicates a 32-bit data of redundant area. + * @var NFI_T::NANDRA52 + * Offset: 0xAD0 NAND Flash Redundant Area Word n + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[31:0] |Data |NAND Flash Redundant Area Word n + * | | |This field indicates a 32-bit data of redundant area. + * @var NFI_T::NANDRA53 + * Offset: 0xAD4 NAND Flash Redundant Area Word n + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[31:0] |Data |NAND Flash Redundant Area Word n + * | | |This field indicates a 32-bit data of redundant area. + * @var NFI_T::NANDRA54 + * Offset: 0xAD8 NAND Flash Redundant Area Word n + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[31:0] |Data |NAND Flash Redundant Area Word n + * | | |This field indicates a 32-bit data of redundant area. + * @var NFI_T::NANDRA55 + * Offset: 0xADC NAND Flash Redundant Area Word n + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[31:0] |Data |NAND Flash Redundant Area Word n + * | | |This field indicates a 32-bit data of redundant area. + * @var NFI_T::NANDRA56 + * Offset: 0xAE0 NAND Flash Redundant Area Word n + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[31:0] |Data |NAND Flash Redundant Area Word n + * | | |This field indicates a 32-bit data of redundant area. + * @var NFI_T::NANDRA57 + * Offset: 0xAE4 NAND Flash Redundant Area Word n + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[31:0] |Data |NAND Flash Redundant Area Word n + * | | |This field indicates a 32-bit data of redundant area. + * @var NFI_T::NANDRA58 + * Offset: 0xAE8 NAND Flash Redundant Area Word n + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[31:0] |Data |NAND Flash Redundant Area Word n + * | | |This field indicates a 32-bit data of redundant area. + * @var NFI_T::NANDRA59 + * Offset: 0xAEC NAND Flash Redundant Area Word n + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[31:0] |Data |NAND Flash Redundant Area Word n + * | | |This field indicates a 32-bit data of redundant area. + * @var NFI_T::NANDRA60 + * Offset: 0xAF0 NAND Flash Redundant Area Word n + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[31:0] |Data |NAND Flash Redundant Area Word n + * | | |This field indicates a 32-bit data of redundant area. + * @var NFI_T::NANDRA61 + * Offset: 0xAF4 NAND Flash Redundant Area Word n + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[31:0] |Data |NAND Flash Redundant Area Word n + * | | |This field indicates a 32-bit data of redundant area. + * @var NFI_T::NANDRA62 + * Offset: 0xAF8 NAND Flash Redundant Area Word n + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[31:0] |Data |NAND Flash Redundant Area Word n + * | | |This field indicates a 32-bit data of redundant area. + * @var NFI_T::NANDRA63 + * Offset: 0xAFC NAND Flash Redundant Area Word n + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[31:0] |Data |NAND Flash Redundant Area Word n + * | | |This field indicates a 32-bit data of redundant area. + * @var NFI_T::NANDRA64 + * Offset: 0xB00 NAND Flash Redundant Area Word n + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[31:0] |Data |NAND Flash Redundant Area Word n + * | | |This field indicates a 32-bit data of redundant area. + * @var NFI_T::NANDRA65 + * Offset: 0xB04 NAND Flash Redundant Area Word n + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[31:0] |Data |NAND Flash Redundant Area Word n + * | | |This field indicates a 32-bit data of redundant area. + * @var NFI_T::NANDRA66 + * Offset: 0xB08 NAND Flash Redundant Area Word n + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[31:0] |Data |NAND Flash Redundant Area Word n + * | | |This field indicates a 32-bit data of redundant area. + * @var NFI_T::NANDRA67 + * Offset: 0xB0C NAND Flash Redundant Area Word n + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[31:0] |Data |NAND Flash Redundant Area Word n + * | | |This field indicates a 32-bit data of redundant area. + * @var NFI_T::NANDRA68 + * Offset: 0xB10 NAND Flash Redundant Area Word n + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[31:0] |Data |NAND Flash Redundant Area Word n + * | | |This field indicates a 32-bit data of redundant area. + * @var NFI_T::NANDRA69 + * Offset: 0xB14 NAND Flash Redundant Area Word n + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[31:0] |Data |NAND Flash Redundant Area Word n + * | | |This field indicates a 32-bit data of redundant area. + * @var NFI_T::NANDRA70 + * Offset: 0xB18 NAND Flash Redundant Area Word n + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[31:0] |Data |NAND Flash Redundant Area Word n + * | | |This field indicates a 32-bit data of redundant area. + * @var NFI_T::NANDRA71 + * Offset: 0xB1C NAND Flash Redundant Area Word n + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[31:0] |Data |NAND Flash Redundant Area Word n + * | | |This field indicates a 32-bit data of redundant area. + * @var NFI_T::NANDRA72 + * Offset: 0xB20 NAND Flash Redundant Area Word n + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[31:0] |Data |NAND Flash Redundant Area Word n + * | | |This field indicates a 32-bit data of redundant area. + * @var NFI_T::NANDRA73 + * Offset: 0xB24 NAND Flash Redundant Area Word n + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[31:0] |Data |NAND Flash Redundant Area Word n + * | | |This field indicates a 32-bit data of redundant area. + * @var NFI_T::NANDRA74 + * Offset: 0xB28 NAND Flash Redundant Area Word n + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[31:0] |Data |NAND Flash Redundant Area Word n + * | | |This field indicates a 32-bit data of redundant area. + * @var NFI_T::NANDRA75 + * Offset: 0xB2C NAND Flash Redundant Area Word n + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[31:0] |Data |NAND Flash Redundant Area Word n + * | | |This field indicates a 32-bit data of redundant area. + * @var NFI_T::NANDRA76 + * Offset: 0xB30 NAND Flash Redundant Area Word n + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[31:0] |Data |NAND Flash Redundant Area Word n + * | | |This field indicates a 32-bit data of redundant area. + * @var NFI_T::NANDRA77 + * Offset: 0xB34 NAND Flash Redundant Area Word n + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[31:0] |Data |NAND Flash Redundant Area Word n + * | | |This field indicates a 32-bit data of redundant area. + * @var NFI_T::NANDRA78 + * Offset: 0xB38 NAND Flash Redundant Area Word n + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[31:0] |Data |NAND Flash Redundant Area Word n + * | | |This field indicates a 32-bit data of redundant area. + * @var NFI_T::NANDRA79 + * Offset: 0xB3C NAND Flash Redundant Area Word n + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[31:0] |Data |NAND Flash Redundant Area Word n + * | | |This field indicates a 32-bit data of redundant area. + * @var NFI_T::NANDRA80 + * Offset: 0xB40 NAND Flash Redundant Area Word n + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[31:0] |Data |NAND Flash Redundant Area Word n + * | | |This field indicates a 32-bit data of redundant area. + * @var NFI_T::NANDRA81 + * Offset: 0xB44 NAND Flash Redundant Area Word n + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[31:0] |Data |NAND Flash Redundant Area Word n + * | | |This field indicates a 32-bit data of redundant area. + * @var NFI_T::NANDRA82 + * Offset: 0xB48 NAND Flash Redundant Area Word n + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[31:0] |Data |NAND Flash Redundant Area Word n + * | | |This field indicates a 32-bit data of redundant area. + * @var NFI_T::NANDRA83 + * Offset: 0xB4C NAND Flash Redundant Area Word n + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[31:0] |Data |NAND Flash Redundant Area Word n + * | | |This field indicates a 32-bit data of redundant area. + * @var NFI_T::NANDRA84 + * Offset: 0xB50 NAND Flash Redundant Area Word n + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[31:0] |Data |NAND Flash Redundant Area Word n + * | | |This field indicates a 32-bit data of redundant area. + * @var NFI_T::NANDRA85 + * Offset: 0xB54 NAND Flash Redundant Area Word n + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[31:0] |Data |NAND Flash Redundant Area Word n + * | | |This field indicates a 32-bit data of redundant area. + * @var NFI_T::NANDRA86 + * Offset: 0xB58 NAND Flash Redundant Area Word n + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[31:0] |Data |NAND Flash Redundant Area Word n + * | | |This field indicates a 32-bit data of redundant area. + * @var NFI_T::NANDRA87 + * Offset: 0xB5C NAND Flash Redundant Area Word n + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[31:0] |Data |NAND Flash Redundant Area Word n + * | | |This field indicates a 32-bit data of redundant area. + * @var NFI_T::NANDRA88 + * Offset: 0xB60 NAND Flash Redundant Area Word n + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[31:0] |Data |NAND Flash Redundant Area Word n + * | | |This field indicates a 32-bit data of redundant area. + * @var NFI_T::NANDRA89 + * Offset: 0xB64 NAND Flash Redundant Area Word n + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[31:0] |Data |NAND Flash Redundant Area Word n + * | | |This field indicates a 32-bit data of redundant area. + * @var NFI_T::NANDRA90 + * Offset: 0xB68 NAND Flash Redundant Area Word n + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[31:0] |Data |NAND Flash Redundant Area Word n + * | | |This field indicates a 32-bit data of redundant area. + * @var NFI_T::NANDRA91 + * Offset: 0xB6C NAND Flash Redundant Area Word n + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[31:0] |Data |NAND Flash Redundant Area Word n + * | | |This field indicates a 32-bit data of redundant area. + * @var NFI_T::NANDRA92 + * Offset: 0xB70 NAND Flash Redundant Area Word n + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[31:0] |Data |NAND Flash Redundant Area Word n + * | | |This field indicates a 32-bit data of redundant area. + * @var NFI_T::NANDRA93 + * Offset: 0xB74 NAND Flash Redundant Area Word n + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[31:0] |Data |NAND Flash Redundant Area Word n + * | | |This field indicates a 32-bit data of redundant area. + * @var NFI_T::NANDRA94 + * Offset: 0xB78 NAND Flash Redundant Area Word n + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[31:0] |Data |NAND Flash Redundant Area Word n + * | | |This field indicates a 32-bit data of redundant area. + * @var NFI_T::NANDRA95 + * Offset: 0xB7C NAND Flash Redundant Area Word n + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[31:0] |Data |NAND Flash Redundant Area Word n + * | | |This field indicates a 32-bit data of redundant area. + * @var NFI_T::NANDRA96 + * Offset: 0xB80 NAND Flash Redundant Area Word n + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[31:0] |Data |NAND Flash Redundant Area Word n + * | | |This field indicates a 32-bit data of redundant area. + * @var NFI_T::NANDRA97 + * Offset: 0xB84 NAND Flash Redundant Area Word n + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[31:0] |Data |NAND Flash Redundant Area Word n + * | | |This field indicates a 32-bit data of redundant area. + * @var NFI_T::NANDRA98 + * Offset: 0xB88 NAND Flash Redundant Area Word n + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[31:0] |Data |NAND Flash Redundant Area Word n + * | | |This field indicates a 32-bit data of redundant area. + * @var NFI_T::NANDRA99 + * Offset: 0xB8C NAND Flash Redundant Area Word n + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[31:0] |Data |NAND Flash Redundant Area Word n + * | | |This field indicates a 32-bit data of redundant area. + * @var NFI_T::NANDRA100 + * Offset: 0xB90 NAND Flash Redundant Area Word n + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[31:0] |Data |NAND Flash Redundant Area Word n + * | | |This field indicates a 32-bit data of redundant area. + * @var NFI_T::NANDRA101 + * Offset: 0xB94 NAND Flash Redundant Area Word n + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[31:0] |Data |NAND Flash Redundant Area Word n + * | | |This field indicates a 32-bit data of redundant area. + * @var NFI_T::NANDRA102 + * Offset: 0xB98 NAND Flash Redundant Area Word n + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[31:0] |Data |NAND Flash Redundant Area Word n + * | | |This field indicates a 32-bit data of redundant area. + * @var NFI_T::NANDRA103 + * Offset: 0xB9C NAND Flash Redundant Area Word n + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[31:0] |Data |NAND Flash Redundant Area Word n + * | | |This field indicates a 32-bit data of redundant area. + * @var NFI_T::NANDRA104 + * Offset: 0xBA0 NAND Flash Redundant Area Word n + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[31:0] |Data |NAND Flash Redundant Area Word n + * | | |This field indicates a 32-bit data of redundant area. + * @var NFI_T::NANDRA105 + * Offset: 0xBA4 NAND Flash Redundant Area Word n + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[31:0] |Data |NAND Flash Redundant Area Word n + * | | |This field indicates a 32-bit data of redundant area. + * @var NFI_T::NANDRA106 + * Offset: 0xBA8 NAND Flash Redundant Area Word n + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[31:0] |Data |NAND Flash Redundant Area Word n + * | | |This field indicates a 32-bit data of redundant area. + * @var NFI_T::NANDRA107 + * Offset: 0xBAC NAND Flash Redundant Area Word n + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[31:0] |Data |NAND Flash Redundant Area Word n + * | | |This field indicates a 32-bit data of redundant area. + * @var NFI_T::NANDRA108 + * Offset: 0xBB0 NAND Flash Redundant Area Word n + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[31:0] |Data |NAND Flash Redundant Area Word n + * | | |This field indicates a 32-bit data of redundant area. + * @var NFI_T::NANDRA109 + * Offset: 0xBB4 NAND Flash Redundant Area Word n + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[31:0] |Data |NAND Flash Redundant Area Word n + * | | |This field indicates a 32-bit data of redundant area. + * @var NFI_T::NANDRA110 + * Offset: 0xBB8 NAND Flash Redundant Area Word n + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[31:0] |Data |NAND Flash Redundant Area Word n + * | | |This field indicates a 32-bit data of redundant area. + * @var NFI_T::NANDRA111 + * Offset: 0xBBC NAND Flash Redundant Area Word n + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[31:0] |Data |NAND Flash Redundant Area Word n + * | | |This field indicates a 32-bit data of redundant area. + * @var NFI_T::NANDRA112 + * Offset: 0xBC0 NAND Flash Redundant Area Word n + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[31:0] |Data |NAND Flash Redundant Area Word n + * | | |This field indicates a 32-bit data of redundant area. + * @var NFI_T::NANDRA113 + * Offset: 0xBC4 NAND Flash Redundant Area Word n + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[31:0] |Data |NAND Flash Redundant Area Word n + * | | |This field indicates a 32-bit data of redundant area. + * @var NFI_T::NANDRA114 + * Offset: 0xBC8 NAND Flash Redundant Area Word n + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[31:0] |Data |NAND Flash Redundant Area Word n + * | | |This field indicates a 32-bit data of redundant area. + * @var NFI_T::NANDRA115 + * Offset: 0xBCC NAND Flash Redundant Area Word n + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[31:0] |Data |NAND Flash Redundant Area Word n + * | | |This field indicates a 32-bit data of redundant area. + * @var NFI_T::NANDRA116 + * Offset: 0xBD0 NAND Flash Redundant Area Word n + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[31:0] |Data |NAND Flash Redundant Area Word n + * | | |This field indicates a 32-bit data of redundant area. + * @var NFI_T::NANDRA117 + * Offset: 0xBD4 NAND Flash Redundant Area Word n + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[31:0] |Data |NAND Flash Redundant Area Word n + * | | |This field indicates a 32-bit data of redundant area. + */ + __IO uint32_t BUFFER0; /*!< [0x0000] NFI Embedded Buffer Word n */ + __IO uint32_t BUFFER1; /*!< [0x0004] NFI Embedded Buffer Word n */ + __IO uint32_t BUFFER2; /*!< [0x0008] NFI Embedded Buffer Word n */ + __IO uint32_t BUFFER3; /*!< [0x000c] NFI Embedded Buffer Word n */ + __IO uint32_t BUFFER4; /*!< [0x0010] NFI Embedded Buffer Word n */ + __IO uint32_t BUFFER5; /*!< [0x0014] NFI Embedded Buffer Word n */ + __IO uint32_t BUFFER6; /*!< [0x0018] NFI Embedded Buffer Word n */ + __IO uint32_t BUFFER7; /*!< [0x001c] NFI Embedded Buffer Word n */ + __IO uint32_t BUFFER8; /*!< [0x0020] NFI Embedded Buffer Word n */ + __IO uint32_t BUFFER9; /*!< [0x0024] NFI Embedded Buffer Word n */ + __IO uint32_t BUFFER10; /*!< [0x0028] NFI Embedded Buffer Word n */ + __IO uint32_t BUFFER11; /*!< [0x002c] NFI Embedded Buffer Word n */ + __IO uint32_t BUFFER12; /*!< [0x0030] NFI Embedded Buffer Word n */ + __IO uint32_t BUFFER13; /*!< [0x0034] NFI Embedded Buffer Word n */ + __IO uint32_t BUFFER14; /*!< [0x0038] NFI Embedded Buffer Word n */ + __IO uint32_t BUFFER15; /*!< [0x003c] NFI Embedded Buffer Word n */ + __IO uint32_t BUFFER16; /*!< [0x0040] NFI Embedded Buffer Word n */ + __IO uint32_t BUFFER17; /*!< [0x0044] NFI Embedded Buffer Word n */ + __IO uint32_t BUFFER18; /*!< [0x0048] NFI Embedded Buffer Word n */ + __IO uint32_t BUFFER19; /*!< [0x004c] NFI Embedded Buffer Word n */ + __IO uint32_t BUFFER20; /*!< [0x0050] NFI Embedded Buffer Word n */ + __IO uint32_t BUFFER21; /*!< [0x0054] NFI Embedded Buffer Word n */ + __IO uint32_t BUFFER22; /*!< [0x0058] NFI Embedded Buffer Word n */ + __IO uint32_t BUFFER23; /*!< [0x005c] NFI Embedded Buffer Word n */ + __IO uint32_t BUFFER24; /*!< [0x0060] NFI Embedded Buffer Word n */ + __IO uint32_t BUFFER25; /*!< [0x0064] NFI Embedded Buffer Word n */ + __IO uint32_t BUFFER26; /*!< [0x0068] NFI Embedded Buffer Word n */ + __IO uint32_t BUFFER27; /*!< [0x006c] NFI Embedded Buffer Word n */ + __IO uint32_t BUFFER28; /*!< [0x0070] NFI Embedded Buffer Word n */ + __IO uint32_t BUFFER29; /*!< [0x0074] NFI Embedded Buffer Word n */ + __IO uint32_t BUFFER30; /*!< [0x0078] NFI Embedded Buffer Word n */ + __IO uint32_t BUFFER31; /*!< [0x007c] NFI Embedded Buffer Word n */ + __I uint32_t RESERVE0[224]; + __IO uint32_t DMACTL; /*!< [0x0400] NFI DMA Control and Status Register */ + __I uint32_t RESERVE1[1]; + __IO uint32_t DMASA; /*!< [0x0408] NFI DMA Transfer Starting Address Register */ + __I uint32_t DMABCNT; /*!< [0x040c] NFI DMA Transfer Byte Count Register */ + __IO uint32_t DMAINTEN; /*!< [0x0410] NFI DMA Interrupt Enable Control Register */ + __I uint32_t DMAINTSTS; /*!< [0x0414] NFI DMA Interrupt Status Register */ + __I uint32_t RESERVE2[250]; + __IO uint32_t GCTL; /*!< [0x0800] NFI Global Control and Status Register */ + __IO uint32_t GINTEN; /*!< [0x0804] NFI Global Interrupt Control Register */ + __I uint32_t GINTSTS; /*!< [0x0808] NFI Global Interrupt Status Register */ + __I uint32_t RESERVE3[37]; + __IO uint32_t NANDCTL; /*!< [0x08a0] NAND Flash Control Register */ + __IO uint32_t NANDTMCTL; /*!< [0x08a4] NAND Flash Timing Control Register */ + __IO uint32_t NANDINTEN; /*!< [0x08a8] NAND Flash Interrupt Enable Register */ + __IO uint32_t NANDINTSTS; /*!< [0x08ac] NAND Flash Interrupt Status Register */ + __O uint32_t NANDCMD; /*!< [0x08b0] NAND Flash Command Port Register */ + __O uint32_t NANDADDR; /*!< [0x08b4] NAND Flash Address Port Register */ + __IO uint32_t NANDDATA; /*!< [0x08b8] NAND Flash Data Port Register */ + __IO uint32_t NANDRACTL; /*!< [0x08bc] NAND Flash Redundant Area Control Register */ + __IO uint32_t NANDECTL; /*!< [0x08c0] NAND Flash Extend Control Register */ + __I uint32_t RESERVE4[3]; + __I uint32_t NANDECCES0; /*!< [0x08d0] NAND Flash ECC Error Status 0 Register */ + __I uint32_t NANDECCES1; /*!< [0x08d4] NAND Flash ECC Error Status 1 Register */ + __I uint32_t NANDECCES2; /*!< [0x08d8] NAND Flash ECC Error Status 2 Register */ + __I uint32_t NANDECCES3; /*!< [0x08dc] NAND Flash ECC Error Status 3 Register */ + __I uint32_t RESERVE5[8]; + __I uint32_t NANDECCEA0; /*!< [0x0900] NAND Flash ECC Error Byte Address 0 Register */ + __I uint32_t NANDECCEA1; /*!< [0x0904] NAND Flash ECC Error Byte Address 1 Register */ + __I uint32_t NANDECCEA2; /*!< [0x0908] NAND Flash ECC Error Byte Address 2 Register */ + __I uint32_t NANDECCEA3; /*!< [0x090c] NAND Flash ECC Error Byte Address 3 Register */ + __I uint32_t NANDECCEA4; /*!< [0x0910] NAND Flash ECC Error Byte Address 4 Register */ + __I uint32_t NANDECCEA5; /*!< [0x0914] NAND Flash ECC Error Byte Address 5 Register */ + __I uint32_t NANDECCEA6; /*!< [0x0918] NAND Flash ECC Error Byte Address 6 Register */ + __I uint32_t NANDECCEA7; /*!< [0x091c] NAND Flash ECC Error Byte Address 7 Register */ + __I uint32_t NANDECCEA8; /*!< [0x0920] NAND Flash ECC Error Byte Address 8 Register */ + __I uint32_t NANDECCEA9; /*!< [0x0924] NAND Flash ECC Error Byte Address 9 Register */ + __I uint32_t NANDECCEA10; /*!< [0x0928] NAND Flash ECC Error Byte Address 10 Register */ + __I uint32_t NANDECCEA11; /*!< [0x092c] NAND Flash ECC Error Byte Address 11 Register */ + __I uint32_t RESERVE6[12]; + __I uint32_t NANDECCED0; /*!< [0x0960] NAND Flash ECC Error Data Register 0 */ + __I uint32_t NANDECCED1; /*!< [0x0964] NAND Flash ECC Error Data Register 1 */ + __I uint32_t NANDECCED2; /*!< [0x0968] NAND Flash ECC Error Data Register 2 */ + __I uint32_t NANDECCED3; /*!< [0x096c] NAND Flash ECC Error Data Register 3 */ + __I uint32_t NANDECCED4; /*!< [0x0970] NAND Flash ECC Error Data Register 4 */ + __I uint32_t NANDECCED5; /*!< [0x0974] NAND Flash ECC Error Data Register 5 */ + __I uint32_t RESERVE7[34]; + __IO uint32_t NANDRA0; /*!< [0x0a00] NAND Flash Redundant Area Word n */ + __IO uint32_t NANDRA1; /*!< [0x0a04] NAND Flash Redundant Area Word n */ + __IO uint32_t NANDRA2; /*!< [0x0a08] NAND Flash Redundant Area Word n */ + __IO uint32_t NANDRA3; /*!< [0x0a0c] NAND Flash Redundant Area Word n */ + __IO uint32_t NANDRA4; /*!< [0x0a10] NAND Flash Redundant Area Word n */ + __IO uint32_t NANDRA5; /*!< [0x0a14] NAND Flash Redundant Area Word n */ + __IO uint32_t NANDRA6; /*!< [0x0a18] NAND Flash Redundant Area Word n */ + __IO uint32_t NANDRA7; /*!< [0x0a1c] NAND Flash Redundant Area Word n */ + __IO uint32_t NANDRA8; /*!< [0x0a20] NAND Flash Redundant Area Word n */ + __IO uint32_t NANDRA9; /*!< [0x0a24] NAND Flash Redundant Area Word n */ + __IO uint32_t NANDRA10; /*!< [0x0a28] NAND Flash Redundant Area Word n */ + __IO uint32_t NANDRA11; /*!< [0x0a2c] NAND Flash Redundant Area Word n */ + __IO uint32_t NANDRA12; /*!< [0x0a30] NAND Flash Redundant Area Word n */ + __IO uint32_t NANDRA13; /*!< [0x0a34] NAND Flash Redundant Area Word n */ + __IO uint32_t NANDRA14; /*!< [0x0a38] NAND Flash Redundant Area Word n */ + __IO uint32_t NANDRA15; /*!< [0x0a3c] NAND Flash Redundant Area Word n */ + __IO uint32_t NANDRA16; /*!< [0x0a40] NAND Flash Redundant Area Word n */ + __IO uint32_t NANDRA17; /*!< [0x0a44] NAND Flash Redundant Area Word n */ + __IO uint32_t NANDRA18; /*!< [0x0a48] NAND Flash Redundant Area Word n */ + __IO uint32_t NANDRA19; /*!< [0x0a4c] NAND Flash Redundant Area Word n */ + __IO uint32_t NANDRA20; /*!< [0x0a50] NAND Flash Redundant Area Word n */ + __IO uint32_t NANDRA21; /*!< [0x0a54] NAND Flash Redundant Area Word n */ + __IO uint32_t NANDRA22; /*!< [0x0a58] NAND Flash Redundant Area Word n */ + __IO uint32_t NANDRA23; /*!< [0x0a5c] NAND Flash Redundant Area Word n */ + __IO uint32_t NANDRA24; /*!< [0x0a60] NAND Flash Redundant Area Word n */ + __IO uint32_t NANDRA25; /*!< [0x0a64] NAND Flash Redundant Area Word n */ + __IO uint32_t NANDRA26; /*!< [0x0a68] NAND Flash Redundant Area Word n */ + __IO uint32_t NANDRA27; /*!< [0x0a6c] NAND Flash Redundant Area Word n */ + __IO uint32_t NANDRA28; /*!< [0x0a70] NAND Flash Redundant Area Word n */ + __IO uint32_t NANDRA29; /*!< [0x0a74] NAND Flash Redundant Area Word n */ + __IO uint32_t NANDRA30; /*!< [0x0a78] NAND Flash Redundant Area Word n */ + __IO uint32_t NANDRA31; /*!< [0x0a7c] NAND Flash Redundant Area Word n */ + __IO uint32_t NANDRA32; /*!< [0x0a80] NAND Flash Redundant Area Word n */ + __IO uint32_t NANDRA33; /*!< [0x0a84] NAND Flash Redundant Area Word n */ + __IO uint32_t NANDRA34; /*!< [0x0a88] NAND Flash Redundant Area Word n */ + __IO uint32_t NANDRA35; /*!< [0x0a8c] NAND Flash Redundant Area Word n */ + __IO uint32_t NANDRA36; /*!< [0x0a90] NAND Flash Redundant Area Word n */ + __IO uint32_t NANDRA37; /*!< [0x0a94] NAND Flash Redundant Area Word n */ + __IO uint32_t NANDRA38; /*!< [0x0a98] NAND Flash Redundant Area Word n */ + __IO uint32_t NANDRA39; /*!< [0x0a9c] NAND Flash Redundant Area Word n */ + __IO uint32_t NANDRA40; /*!< [0x0aa0] NAND Flash Redundant Area Word n */ + __IO uint32_t NANDRA41; /*!< [0x0aa4] NAND Flash Redundant Area Word n */ + __IO uint32_t NANDRA42; /*!< [0x0aa8] NAND Flash Redundant Area Word n */ + __IO uint32_t NANDRA43; /*!< [0x0aac] NAND Flash Redundant Area Word n */ + __IO uint32_t NANDRA44; /*!< [0x0ab0] NAND Flash Redundant Area Word n */ + __IO uint32_t NANDRA45; /*!< [0x0ab4] NAND Flash Redundant Area Word n */ + __IO uint32_t NANDRA46; /*!< [0x0ab8] NAND Flash Redundant Area Word n */ + __IO uint32_t NANDRA47; /*!< [0x0abc] NAND Flash Redundant Area Word n */ + __IO uint32_t NANDRA48; /*!< [0x0ac0] NAND Flash Redundant Area Word n */ + __IO uint32_t NANDRA49; /*!< [0x0ac4] NAND Flash Redundant Area Word n */ + __IO uint32_t NANDRA50; /*!< [0x0ac8] NAND Flash Redundant Area Word n */ + __IO uint32_t NANDRA51; /*!< [0x0acc] NAND Flash Redundant Area Word n */ + __IO uint32_t NANDRA52; /*!< [0x0ad0] NAND Flash Redundant Area Word n */ + __IO uint32_t NANDRA53; /*!< [0x0ad4] NAND Flash Redundant Area Word n */ + __IO uint32_t NANDRA54; /*!< [0x0ad8] NAND Flash Redundant Area Word n */ + __IO uint32_t NANDRA55; /*!< [0x0adc] NAND Flash Redundant Area Word n */ + __IO uint32_t NANDRA56; /*!< [0x0ae0] NAND Flash Redundant Area Word n */ + __IO uint32_t NANDRA57; /*!< [0x0ae4] NAND Flash Redundant Area Word n */ + __IO uint32_t NANDRA58; /*!< [0x0ae8] NAND Flash Redundant Area Word n */ + __IO uint32_t NANDRA59; /*!< [0x0aec] NAND Flash Redundant Area Word n */ + __IO uint32_t NANDRA60; /*!< [0x0af0] NAND Flash Redundant Area Word n */ + __IO uint32_t NANDRA61; /*!< [0x0af4] NAND Flash Redundant Area Word n */ + __IO uint32_t NANDRA62; /*!< [0x0af8] NAND Flash Redundant Area Word n */ + __IO uint32_t NANDRA63; /*!< [0x0afc] NAND Flash Redundant Area Word n */ + __IO uint32_t NANDRA64; /*!< [0x0b00] NAND Flash Redundant Area Word n */ + __IO uint32_t NANDRA65; /*!< [0x0b04] NAND Flash Redundant Area Word n */ + __IO uint32_t NANDRA66; /*!< [0x0b08] NAND Flash Redundant Area Word n */ + __IO uint32_t NANDRA67; /*!< [0x0b0c] NAND Flash Redundant Area Word n */ + __IO uint32_t NANDRA68; /*!< [0x0b10] NAND Flash Redundant Area Word n */ + __IO uint32_t NANDRA69; /*!< [0x0b14] NAND Flash Redundant Area Word n */ + __IO uint32_t NANDRA70; /*!< [0x0b18] NAND Flash Redundant Area Word n */ + __IO uint32_t NANDRA71; /*!< [0x0b1c] NAND Flash Redundant Area Word n */ + __IO uint32_t NANDRA72; /*!< [0x0b20] NAND Flash Redundant Area Word n */ + __IO uint32_t NANDRA73; /*!< [0x0b24] NAND Flash Redundant Area Word n */ + __IO uint32_t NANDRA74; /*!< [0x0b28] NAND Flash Redundant Area Word n */ + __IO uint32_t NANDRA75; /*!< [0x0b2c] NAND Flash Redundant Area Word n */ + __IO uint32_t NANDRA76; /*!< [0x0b30] NAND Flash Redundant Area Word n */ + __IO uint32_t NANDRA77; /*!< [0x0b34] NAND Flash Redundant Area Word n */ + __IO uint32_t NANDRA78; /*!< [0x0b38] NAND Flash Redundant Area Word n */ + __IO uint32_t NANDRA79; /*!< [0x0b3c] NAND Flash Redundant Area Word n */ + __IO uint32_t NANDRA80; /*!< [0x0b40] NAND Flash Redundant Area Word n */ + __IO uint32_t NANDRA81; /*!< [0x0b44] NAND Flash Redundant Area Word n */ + __IO uint32_t NANDRA82; /*!< [0x0b48] NAND Flash Redundant Area Word n */ + __IO uint32_t NANDRA83; /*!< [0x0b4c] NAND Flash Redundant Area Word n */ + __IO uint32_t NANDRA84; /*!< [0x0b50] NAND Flash Redundant Area Word n */ + __IO uint32_t NANDRA85; /*!< [0x0b54] NAND Flash Redundant Area Word n */ + __IO uint32_t NANDRA86; /*!< [0x0b58] NAND Flash Redundant Area Word n */ + __IO uint32_t NANDRA87; /*!< [0x0b5c] NAND Flash Redundant Area Word n */ + __IO uint32_t NANDRA88; /*!< [0x0b60] NAND Flash Redundant Area Word n */ + __IO uint32_t NANDRA89; /*!< [0x0b64] NAND Flash Redundant Area Word n */ + __IO uint32_t NANDRA90; /*!< [0x0b68] NAND Flash Redundant Area Word n */ + __IO uint32_t NANDRA91; /*!< [0x0b6c] NAND Flash Redundant Area Word n */ + __IO uint32_t NANDRA92; /*!< [0x0b70] NAND Flash Redundant Area Word n */ + __IO uint32_t NANDRA93; /*!< [0x0b74] NAND Flash Redundant Area Word n */ + __IO uint32_t NANDRA94; /*!< [0x0b78] NAND Flash Redundant Area Word n */ + __IO uint32_t NANDRA95; /*!< [0x0b7c] NAND Flash Redundant Area Word n */ + __IO uint32_t NANDRA96; /*!< [0x0b80] NAND Flash Redundant Area Word n */ + __IO uint32_t NANDRA97; /*!< [0x0b84] NAND Flash Redundant Area Word n */ + __IO uint32_t NANDRA98; /*!< [0x0b88] NAND Flash Redundant Area Word n */ + __IO uint32_t NANDRA99; /*!< [0x0b8c] NAND Flash Redundant Area Word n */ + __IO uint32_t NANDRA100; /*!< [0x0b90] NAND Flash Redundant Area Word n */ + __IO uint32_t NANDRA101; /*!< [0x0b94] NAND Flash Redundant Area Word n */ + __IO uint32_t NANDRA102; /*!< [0x0b98] NAND Flash Redundant Area Word n */ + __IO uint32_t NANDRA103; /*!< [0x0b9c] NAND Flash Redundant Area Word n */ + __IO uint32_t NANDRA104; /*!< [0x0ba0] NAND Flash Redundant Area Word n */ + __IO uint32_t NANDRA105; /*!< [0x0ba4] NAND Flash Redundant Area Word n */ + __IO uint32_t NANDRA106; /*!< [0x0ba8] NAND Flash Redundant Area Word n */ + __IO uint32_t NANDRA107; /*!< [0x0bac] NAND Flash Redundant Area Word n */ + __IO uint32_t NANDRA108; /*!< [0x0bb0] NAND Flash Redundant Area Word n */ + __IO uint32_t NANDRA109; /*!< [0x0bb4] NAND Flash Redundant Area Word n */ + __IO uint32_t NANDRA110; /*!< [0x0bb8] NAND Flash Redundant Area Word n */ + __IO uint32_t NANDRA111; /*!< [0x0bbc] NAND Flash Redundant Area Word n */ + __IO uint32_t NANDRA112; /*!< [0x0bc0] NAND Flash Redundant Area Word n */ + __IO uint32_t NANDRA113; /*!< [0x0bc4] NAND Flash Redundant Area Word n */ + __IO uint32_t NANDRA114; /*!< [0x0bc8] NAND Flash Redundant Area Word n */ + __IO uint32_t NANDRA115; /*!< [0x0bcc] NAND Flash Redundant Area Word n */ + __IO uint32_t NANDRA116; /*!< [0x0bd0] NAND Flash Redundant Area Word n */ + __IO uint32_t NANDRA117; /*!< [0x0bd4] NAND Flash Redundant Area Word n */ + +} NFI_T; + +/** + @addtogroup NFI_CONST NFI Bit Field Definition + Constant Definitions for NFI Controller +@{ */ + +#define NFI_BUFFER0_Data_Pos (0) /*!< NFI_T::BUFFER0: Data Position */ +#define NFI_BUFFER0_Data_Msk (0xfffffffful << NFI_BUFFER0_Data_Pos) /*!< NFI_T::BUFFER0: Data Mask */ + +#define NFI_BUFFER1_Data_Pos (0) /*!< NFI_T::BUFFER1: Data Position */ +#define NFI_BUFFER1_Data_Msk (0xfffffffful << NFI_BUFFER1_Data_Pos) /*!< NFI_T::BUFFER1: Data Mask */ + +#define NFI_BUFFER2_Data_Pos (0) /*!< NFI_T::BUFFER2: Data Position */ +#define NFI_BUFFER2_Data_Msk (0xfffffffful << NFI_BUFFER2_Data_Pos) /*!< NFI_T::BUFFER2: Data Mask */ + +#define NFI_BUFFER3_Data_Pos (0) /*!< NFI_T::BUFFER3: Data Position */ +#define NFI_BUFFER3_Data_Msk (0xfffffffful << NFI_BUFFER3_Data_Pos) /*!< NFI_T::BUFFER3: Data Mask */ + +#define NFI_BUFFER4_Data_Pos (0) /*!< NFI_T::BUFFER4: Data Position */ +#define NFI_BUFFER4_Data_Msk (0xfffffffful << NFI_BUFFER4_Data_Pos) /*!< NFI_T::BUFFER4: Data Mask */ + +#define NFI_BUFFER5_Data_Pos (0) /*!< NFI_T::BUFFER5: Data Position */ +#define NFI_BUFFER5_Data_Msk (0xfffffffful << NFI_BUFFER5_Data_Pos) /*!< NFI_T::BUFFER5: Data Mask */ + +#define NFI_BUFFER6_Data_Pos (0) /*!< NFI_T::BUFFER6: Data Position */ +#define NFI_BUFFER6_Data_Msk (0xfffffffful << NFI_BUFFER6_Data_Pos) /*!< NFI_T::BUFFER6: Data Mask */ + +#define NFI_BUFFER7_Data_Pos (0) /*!< NFI_T::BUFFER7: Data Position */ +#define NFI_BUFFER7_Data_Msk (0xfffffffful << NFI_BUFFER7_Data_Pos) /*!< NFI_T::BUFFER7: Data Mask */ + +#define NFI_BUFFER8_Data_Pos (0) /*!< NFI_T::BUFFER8: Data Position */ +#define NFI_BUFFER8_Data_Msk (0xfffffffful << NFI_BUFFER8_Data_Pos) /*!< NFI_T::BUFFER8: Data Mask */ + +#define NFI_BUFFER9_Data_Pos (0) /*!< NFI_T::BUFFER9: Data Position */ +#define NFI_BUFFER9_Data_Msk (0xfffffffful << NFI_BUFFER9_Data_Pos) /*!< NFI_T::BUFFER9: Data Mask */ + +#define NFI_BUFFER10_Data_Pos (0) /*!< NFI_T::BUFFER10: Data Position */ +#define NFI_BUFFER10_Data_Msk (0xfffffffful << NFI_BUFFER10_Data_Pos) /*!< NFI_T::BUFFER10: Data Mask */ + +#define NFI_BUFFER11_Data_Pos (0) /*!< NFI_T::BUFFER11: Data Position */ +#define NFI_BUFFER11_Data_Msk (0xfffffffful << NFI_BUFFER11_Data_Pos) /*!< NFI_T::BUFFER11: Data Mask */ + +#define NFI_BUFFER12_Data_Pos (0) /*!< NFI_T::BUFFER12: Data Position */ +#define NFI_BUFFER12_Data_Msk (0xfffffffful << NFI_BUFFER12_Data_Pos) /*!< NFI_T::BUFFER12: Data Mask */ + +#define NFI_BUFFER13_Data_Pos (0) /*!< NFI_T::BUFFER13: Data Position */ +#define NFI_BUFFER13_Data_Msk (0xfffffffful << NFI_BUFFER13_Data_Pos) /*!< NFI_T::BUFFER13: Data Mask */ + +#define NFI_BUFFER14_Data_Pos (0) /*!< NFI_T::BUFFER14: Data Position */ +#define NFI_BUFFER14_Data_Msk (0xfffffffful << NFI_BUFFER14_Data_Pos) /*!< NFI_T::BUFFER14: Data Mask */ + +#define NFI_BUFFER15_Data_Pos (0) /*!< NFI_T::BUFFER15: Data Position */ +#define NFI_BUFFER15_Data_Msk (0xfffffffful << NFI_BUFFER15_Data_Pos) /*!< NFI_T::BUFFER15: Data Mask */ + +#define NFI_BUFFER16_Data_Pos (0) /*!< NFI_T::BUFFER16: Data Position */ +#define NFI_BUFFER16_Data_Msk (0xfffffffful << NFI_BUFFER16_Data_Pos) /*!< NFI_T::BUFFER16: Data Mask */ + +#define NFI_BUFFER17_Data_Pos (0) /*!< NFI_T::BUFFER17: Data Position */ +#define NFI_BUFFER17_Data_Msk (0xfffffffful << NFI_BUFFER17_Data_Pos) /*!< NFI_T::BUFFER17: Data Mask */ + +#define NFI_BUFFER18_Data_Pos (0) /*!< NFI_T::BUFFER18: Data Position */ +#define NFI_BUFFER18_Data_Msk (0xfffffffful << NFI_BUFFER18_Data_Pos) /*!< NFI_T::BUFFER18: Data Mask */ + +#define NFI_BUFFER19_Data_Pos (0) /*!< NFI_T::BUFFER19: Data Position */ +#define NFI_BUFFER19_Data_Msk (0xfffffffful << NFI_BUFFER19_Data_Pos) /*!< NFI_T::BUFFER19: Data Mask */ + +#define NFI_BUFFER20_Data_Pos (0) /*!< NFI_T::BUFFER20: Data Position */ +#define NFI_BUFFER20_Data_Msk (0xfffffffful << NFI_BUFFER20_Data_Pos) /*!< NFI_T::BUFFER20: Data Mask */ + +#define NFI_BUFFER21_Data_Pos (0) /*!< NFI_T::BUFFER21: Data Position */ +#define NFI_BUFFER21_Data_Msk (0xfffffffful << NFI_BUFFER21_Data_Pos) /*!< NFI_T::BUFFER21: Data Mask */ + +#define NFI_BUFFER22_Data_Pos (0) /*!< NFI_T::BUFFER22: Data Position */ +#define NFI_BUFFER22_Data_Msk (0xfffffffful << NFI_BUFFER22_Data_Pos) /*!< NFI_T::BUFFER22: Data Mask */ + +#define NFI_BUFFER23_Data_Pos (0) /*!< NFI_T::BUFFER23: Data Position */ +#define NFI_BUFFER23_Data_Msk (0xfffffffful << NFI_BUFFER23_Data_Pos) /*!< NFI_T::BUFFER23: Data Mask */ + +#define NFI_BUFFER24_Data_Pos (0) /*!< NFI_T::BUFFER24: Data Position */ +#define NFI_BUFFER24_Data_Msk (0xfffffffful << NFI_BUFFER24_Data_Pos) /*!< NFI_T::BUFFER24: Data Mask */ + +#define NFI_BUFFER25_Data_Pos (0) /*!< NFI_T::BUFFER25: Data Position */ +#define NFI_BUFFER25_Data_Msk (0xfffffffful << NFI_BUFFER25_Data_Pos) /*!< NFI_T::BUFFER25: Data Mask */ + +#define NFI_BUFFER26_Data_Pos (0) /*!< NFI_T::BUFFER26: Data Position */ +#define NFI_BUFFER26_Data_Msk (0xfffffffful << NFI_BUFFER26_Data_Pos) /*!< NFI_T::BUFFER26: Data Mask */ + +#define NFI_BUFFER27_Data_Pos (0) /*!< NFI_T::BUFFER27: Data Position */ +#define NFI_BUFFER27_Data_Msk (0xfffffffful << NFI_BUFFER27_Data_Pos) /*!< NFI_T::BUFFER27: Data Mask */ + +#define NFI_BUFFER28_Data_Pos (0) /*!< NFI_T::BUFFER28: Data Position */ +#define NFI_BUFFER28_Data_Msk (0xfffffffful << NFI_BUFFER28_Data_Pos) /*!< NFI_T::BUFFER28: Data Mask */ + +#define NFI_BUFFER29_Data_Pos (0) /*!< NFI_T::BUFFER29: Data Position */ +#define NFI_BUFFER29_Data_Msk (0xfffffffful << NFI_BUFFER29_Data_Pos) /*!< NFI_T::BUFFER29: Data Mask */ + +#define NFI_BUFFER30_Data_Pos (0) /*!< NFI_T::BUFFER30: Data Position */ +#define NFI_BUFFER30_Data_Msk (0xfffffffful << NFI_BUFFER30_Data_Pos) /*!< NFI_T::BUFFER30: Data Mask */ + +#define NFI_BUFFER31_Data_Pos (0) /*!< NFI_T::BUFFER31: Data Position */ +#define NFI_BUFFER31_Data_Msk (0xfffffffful << NFI_BUFFER31_Data_Pos) /*!< NFI_T::BUFFER31: Data Mask */ + +#define NFI_DMACTL_DMACEN_Pos (0) /*!< NFI_T::DMACTL: DMACEN Position */ +#define NFI_DMACTL_DMACEN_Msk (0x1ul << NFI_DMACTL_DMACEN_Pos) /*!< NFI_T::DMACTL: DMACEN Mask */ + +#define NFI_DMACTL_DMARST_Pos (1) /*!< NFI_T::DMACTL: DMARST Position */ +#define NFI_DMACTL_DMARST_Msk (0x1ul << NFI_DMACTL_DMARST_Pos) /*!< NFI_T::DMACTL: DMARST Mask */ + +#define NFI_DMACTL_SGEN_Pos (3) /*!< NFI_T::DMACTL: SGEN Position */ +#define NFI_DMACTL_SGEN_Msk (0x1ul << NFI_DMACTL_SGEN_Pos) /*!< NFI_T::DMACTL: SGEN Mask */ + +#define NFI_DMACTL_DMABUSY_Pos (9) /*!< NFI_T::DMACTL: DMABUSY Position */ +#define NFI_DMACTL_DMABUSY_Msk (0x1ul << NFI_DMACTL_DMABUSY_Pos) /*!< NFI_T::DMACTL: DMABUSY Mask */ + +#define NFI_DMASA_ORDER_Pos (0) /*!< NFI_T::DMASA: ORDER Position */ +#define NFI_DMASA_ORDER_Msk (0x1ul << NFI_DMASA_ORDER_Pos) /*!< NFI_T::DMASA: ORDER Mask */ + +#define NFI_DMASA_DMASA_Pos (1) /*!< NFI_T::DMASA: DMASA Position */ +#define NFI_DMASA_DMASA_Msk (0x7ffffffful << NFI_DMASA_DMASA_Pos) /*!< NFI_T::DMASA: DMASA Mask */ + +#define NFI_DMABCNT_BCNT_Pos (0) /*!< NFI_T::DMABCNT: BCNT Position */ +#define NFI_DMABCNT_BCNT_Msk (0x3fffffful << NFI_DMABCNT_BCNT_Pos) /*!< NFI_T::DMABCNT: BCNT Mask */ + +#define NFI_DMAINTEN_ABORTIEN_Pos (0) /*!< NFI_T::DMAINTEN: ABORTIEN Position */ +#define NFI_DMAINTEN_ABORTIEN_Msk (0x1ul << NFI_DMAINTEN_ABORTIEN_Pos) /*!< NFI_T::DMAINTEN: ABORTIEN Mask */ + +#define NFI_DMAINTEN_WEOTIEN_Pos (1) /*!< NFI_T::DMAINTEN: WEOTIEN Position */ +#define NFI_DMAINTEN_WEOTIEN_Msk (0x1ul << NFI_DMAINTEN_WEOTIEN_Pos) /*!< NFI_T::DMAINTEN: WEOTIEN Mask */ + +#define NFI_DMAINTSTS_ABORTIF_Pos (0) /*!< NFI_T::DMAINTSTS: ABORTIF Position */ +#define NFI_DMAINTSTS_ABORTIF_Msk (0x1ul << NFI_DMAINTSTS_ABORTIF_Pos) /*!< NFI_T::DMAINTSTS: ABORTIF Mask */ + +#define NFI_DMAINTSTS_WEOTIF_Pos (1) /*!< NFI_T::DMAINTSTS: WEOTIF Position */ +#define NFI_DMAINTSTS_WEOTIF_Msk (0x1ul << NFI_DMAINTSTS_WEOTIF_Pos) /*!< NFI_T::DMAINTSTS: WEOTIF Mask */ + +#define NFI_GCTL_GCTLRST_Pos (0) /*!< NFI_T::GCTL: GCTLRST Position */ +#define NFI_GCTL_GCTLRST_Msk (0x1ul << NFI_GCTL_GCTLRST_Pos) /*!< NFI_T::GCTL: GCTLRST Mask */ + +#define NFI_GCTL_NANDEN_Pos (3) /*!< NFI_T::GCTL: NANDEN Position */ +#define NFI_GCTL_NANDEN_Msk (0x1ul << NFI_GCTL_NANDEN_Pos) /*!< NFI_T::GCTL: NANDEN Mask */ + +#define NFI_GINTEN_DTAIEN_Pos (0) /*!< NFI_T::GINTEN: DTAIEN Position */ +#define NFI_GINTEN_DTAIEN_Msk (0x1ul << NFI_GINTEN_DTAIEN_Pos) /*!< NFI_T::GINTEN: DTAIEN Mask */ + +#define NFI_GINTSTS_DTAIF_Pos (0) /*!< NFI_T::GINTSTS: DTAIF Position */ +#define NFI_GINTSTS_DTAIF_Msk (0x1ul << NFI_GINTSTS_DTAIF_Pos) /*!< NFI_T::GINTSTS: DTAIF Mask */ + +#define NFI_NANDCTL_SWRST_Pos (0) /*!< NFI_T::NANDCTL: SWRST Position */ +#define NFI_NANDCTL_SWRST_Msk (0x1ul << NFI_NANDCTL_SWRST_Pos) /*!< NFI_T::NANDCTL: SWRST Mask */ + +#define NFI_NANDCTL_DRDEN_Pos (1) /*!< NFI_T::NANDCTL: DRDEN Position */ +#define NFI_NANDCTL_DRDEN_Msk (0x1ul << NFI_NANDCTL_DRDEN_Pos) /*!< NFI_T::NANDCTL: DRDEN Mask */ + +#define NFI_NANDCTL_DWREN_Pos (2) /*!< NFI_T::NANDCTL: DWREN Position */ +#define NFI_NANDCTL_DWREN_Msk (0x1ul << NFI_NANDCTL_DWREN_Pos) /*!< NFI_T::NANDCTL: DWREN Mask */ + +#define NFI_NANDCTL_REDUNREN_Pos (3) /*!< NFI_T::NANDCTL: REDUNREN Position */ +#define NFI_NANDCTL_REDUNREN_Msk (0x1ul << NFI_NANDCTL_REDUNREN_Pos) /*!< NFI_T::NANDCTL: REDUNREN Mask */ + +#define NFI_NANDCTL_REDUNAUTOWEN_Pos (4) /*!< NFI_T::NANDCTL: REDUNAUTOWEN Position */ +#define NFI_NANDCTL_REDUNAUTOWEN_Msk (0x1ul << NFI_NANDCTL_REDUNAUTOWEN_Pos) /*!< NFI_T::NANDCTL: REDUNAUTOWEN Mask */ + +#define NFI_NANDCTL_ECCCHK_Pos (7) /*!< NFI_T::NANDCTL: ECCCHK Position */ +#define NFI_NANDCTL_ECCCHK_Msk (0x1ul << NFI_NANDCTL_ECCCHK_Pos) /*!< NFI_T::NANDCTL: ECCCHK Mask */ + +#define NFI_NANDCTL_PROT3BEN_Pos (8) /*!< NFI_T::NANDCTL: PROT3BEN Position */ +#define NFI_NANDCTL_PROT3BEN_Msk (0x1ul << NFI_NANDCTL_PROT3BEN_Pos) /*!< NFI_T::NANDCTL: PROT3BEN Mask */ + +#define NFI_NANDCTL_SRAMINT_Pos (9) /*!< NFI_T::NANDCTL: SRAMINT Position */ +#define NFI_NANDCTL_SRAMINT_Msk (0x1ul << NFI_NANDCTL_SRAMINT_Pos) /*!< NFI_T::NANDCTL: SRAMINT Mask */ + +#define NFI_NANDCTL_PSIZE_Pos (16) /*!< NFI_T::NANDCTL: PSIZE Position */ +#define NFI_NANDCTL_PSIZE_Msk (0x3ul << NFI_NANDCTL_PSIZE_Pos) /*!< NFI_T::NANDCTL: PSIZE Mask */ + +#define NFI_NANDCTL_BCHTSEL_Pos (18) /*!< NFI_T::NANDCTL: BCHTSEL Position */ +#define NFI_NANDCTL_BCHTSEL_Msk (0x1ful << NFI_NANDCTL_BCHTSEL_Pos) /*!< NFI_T::NANDCTL: BCHTSEL Mask */ + +#define NFI_NANDCTL_ECCEN_Pos (23) /*!< NFI_T::NANDCTL: ECCEN Position */ +#define NFI_NANDCTL_ECCEN_Msk (0x1ul << NFI_NANDCTL_ECCEN_Pos) /*!< NFI_T::NANDCTL: ECCEN Mask */ + +#define NFI_NANDCTL_CS0_Pos (25) /*!< NFI_T::NANDCTL: CS0 Position */ +#define NFI_NANDCTL_CS0_Msk (0x1ul << NFI_NANDCTL_CS0_Pos) /*!< NFI_T::NANDCTL: CS0 Mask */ + +#define NFI_NANDTMCTL_LOWID_Pos (0) /*!< NFI_T::NANDTMCTL: LOWID Position */ +#define NFI_NANDTMCTL_LOWID_Msk (0xfful << NFI_NANDTMCTL_LOWID_Pos) /*!< NFI_T::NANDTMCTL: LOWID Mask */ + +#define NFI_NANDTMCTL_HIWID_Pos (8) /*!< NFI_T::NANDTMCTL: HIWID Position */ +#define NFI_NANDTMCTL_HIWID_Msk (0xfful << NFI_NANDTMCTL_HIWID_Pos) /*!< NFI_T::NANDTMCTL: HIWID Mask */ + +#define NFI_NANDTMCTL_CALESH_Pos (16) /*!< NFI_T::NANDTMCTL: CALESH Position */ +#define NFI_NANDTMCTL_CALESH_Msk (0x7ful << NFI_NANDTMCTL_CALESH_Pos) /*!< NFI_T::NANDTMCTL: CALESH Mask */ + +#define NFI_NANDTMCTL_EDOD_Pos (24) /*!< NFI_T::NANDTMCTL: EDOD Position */ +#define NFI_NANDTMCTL_EDOD_Msk (0xful << NFI_NANDTMCTL_EDOD_Pos) /*!< NFI_T::NANDTMCTL: EDOD Mask */ + +#define NFI_NANDTMCTL_EDOEN_Pos (31) /*!< NFI_T::NANDTMCTL: EDOEN Position */ +#define NFI_NANDTMCTL_EDOEN_Msk (0x1ul << NFI_NANDTMCTL_EDOEN_Pos) /*!< NFI_T::NANDTMCTL: EDOEN Mask */ + +#define NFI_NANDINTEN_DMAIE_Pos (0) /*!< NFI_T::NANDINTEN: DMAIE Position */ +#define NFI_NANDINTEN_DMAIE_Msk (0x1ul << NFI_NANDINTEN_DMAIE_Pos) /*!< NFI_T::NANDINTEN: DMAIE Mask */ + +#define NFI_NANDINTEN_ECCFLDIE_Pos (2) /*!< NFI_T::NANDINTEN: ECCFLDIE Position */ +#define NFI_NANDINTEN_ECCFLDIE_Msk (0x1ul << NFI_NANDINTEN_ECCFLDIE_Pos) /*!< NFI_T::NANDINTEN: ECCFLDIE Mask */ + +#define NFI_NANDINTEN_RB0IE_Pos (10) /*!< NFI_T::NANDINTEN: RB0IE Position */ +#define NFI_NANDINTEN_RB0IE_Msk (0x1ul << NFI_NANDINTEN_RB0IE_Pos) /*!< NFI_T::NANDINTEN: RB0IE Mask */ + +#define NFI_NANDINTSTS_DMAIF_Pos (0) /*!< NFI_T::NANDINTSTS: DMAIF Position */ +#define NFI_NANDINTSTS_DMAIF_Msk (0x1ul << NFI_NANDINTSTS_DMAIF_Pos) /*!< NFI_T::NANDINTSTS: DMAIF Mask */ + +#define NFI_NANDINTSTS_ECCFLDIF_Pos (2) /*!< NFI_T::NANDINTSTS: ECCFLDIF Position */ +#define NFI_NANDINTSTS_ECCFLDIF_Msk (0x1ul << NFI_NANDINTSTS_ECCFLDIF_Pos) /*!< NFI_T::NANDINTSTS: ECCFLDIF Mask */ + +#define NFI_NANDINTSTS_EDOF_Pos (4) /*!< NFI_T::NANDINTSTS: EDOF Position */ +#define NFI_NANDINTSTS_EDOF_Msk (0x1ul << NFI_NANDINTSTS_EDOF_Pos) /*!< NFI_T::NANDINTSTS: EDOF Mask */ + +#define NFI_NANDINTSTS_RB0IF_Pos (10) /*!< NFI_T::NANDINTSTS: RB0IF Position */ +#define NFI_NANDINTSTS_RB0IF_Msk (0x1ul << NFI_NANDINTSTS_RB0IF_Pos) /*!< NFI_T::NANDINTSTS: RB0IF Mask */ + +#define NFI_NANDINTSTS_RB0Status_Pos (18) /*!< NFI_T::NANDINTSTS: RB0Status Position */ +#define NFI_NANDINTSTS_RB0Status_Msk (0x1ul << NFI_NANDINTSTS_RB0Status_Pos) /*!< NFI_T::NANDINTSTS: RB0Status Mask */ + +#define NFI_NANDCMD_COMMAND_Pos (0) /*!< NFI_T::NANDCMD: COMMAND Position */ +#define NFI_NANDCMD_COMMAND_Msk (0xfful << NFI_NANDCMD_COMMAND_Pos) /*!< NFI_T::NANDCMD: COMMAND Mask */ + +#define NFI_NANDADDR_ADDRESS_Pos (0) /*!< NFI_T::NANDADDR: ADDRESS Position */ +#define NFI_NANDADDR_ADDRESS_Msk (0xfful << NFI_NANDADDR_ADDRESS_Pos) /*!< NFI_T::NANDADDR: ADDRESS Mask */ + +#define NFI_NANDADDR_EOA_Pos (31) /*!< NFI_T::NANDADDR: EOA Position */ +#define NFI_NANDADDR_EOA_Msk (0x1ul << NFI_NANDADDR_EOA_Pos) /*!< NFI_T::NANDADDR: EOA Mask */ + +#define NFI_NANDDATA_DATA_Pos (0) /*!< NFI_T::NANDDATA: DATA Position */ +#define NFI_NANDDATA_DATA_Msk (0xfful << NFI_NANDDATA_DATA_Pos) /*!< NFI_T::NANDDATA: DATA Mask */ + +#define NFI_NANDRACTL_RA128EN_Pos (0) /*!< NFI_T::NANDRACTL: RA128EN Position */ +#define NFI_NANDRACTL_RA128EN_Msk (0x1fful << NFI_NANDRACTL_RA128EN_Pos) /*!< NFI_T::NANDRACTL: RA128EN Mask */ + +#define NFI_NANDRACTL_MECC_Pos (16) /*!< NFI_T::NANDRACTL: MECC Position */ +#define NFI_NANDRACTL_MECC_Msk (0xfffful << NFI_NANDRACTL_MECC_Pos) /*!< NFI_T::NANDRACTL: MECC Mask */ + +#define NFI_NANDECTL_WP_Pos (0) /*!< NFI_T::NANDECTL: WP Position */ +#define NFI_NANDECTL_WP_Msk (0x1ul << NFI_NANDECTL_WP_Pos) /*!< NFI_T::NANDECTL: WP Mask */ + +#define NFI_NANDECCES0_F1STAT_Pos (0) /*!< NFI_T::NANDECCES0: F1STAT Position */ +#define NFI_NANDECCES0_F1STAT_Msk (0x3ul << NFI_NANDECCES0_F1STAT_Pos) /*!< NFI_T::NANDECCES0: F1STAT Mask */ + +#define NFI_NANDECCES0_F1ECNT_Pos (2) /*!< NFI_T::NANDECCES0: F1ECNT Position */ +#define NFI_NANDECCES0_F1ECNT_Msk (0x1ful << NFI_NANDECCES0_F1ECNT_Pos) /*!< NFI_T::NANDECCES0: F1ECNT Mask */ + +#define NFI_NANDECCES0_F2STAT_Pos (8) /*!< NFI_T::NANDECCES0: F2STAT Position */ +#define NFI_NANDECCES0_F2STAT_Msk (0x3ul << NFI_NANDECCES0_F2STAT_Pos) /*!< NFI_T::NANDECCES0: F2STAT Mask */ + +#define NFI_NANDECCES0_F2ECNT_Pos (10) /*!< NFI_T::NANDECCES0: F2ECNT Position */ +#define NFI_NANDECCES0_F2ECNT_Msk (0x1ful << NFI_NANDECCES0_F2ECNT_Pos) /*!< NFI_T::NANDECCES0: F2ECNT Mask */ + +#define NFI_NANDECCES0_F3STAT_Pos (16) /*!< NFI_T::NANDECCES0: F3STAT Position */ +#define NFI_NANDECCES0_F3STAT_Msk (0x3ul << NFI_NANDECCES0_F3STAT_Pos) /*!< NFI_T::NANDECCES0: F3STAT Mask */ + +#define NFI_NANDECCES0_F3ECNT_Pos (18) /*!< NFI_T::NANDECCES0: F3ECNT Position */ +#define NFI_NANDECCES0_F3ECNT_Msk (0x1ful << NFI_NANDECCES0_F3ECNT_Pos) /*!< NFI_T::NANDECCES0: F3ECNT Mask */ + +#define NFI_NANDECCES0_F4STAT_Pos (24) /*!< NFI_T::NANDECCES0: F4STAT Position */ +#define NFI_NANDECCES0_F4STAT_Msk (0x3ul << NFI_NANDECCES0_F4STAT_Pos) /*!< NFI_T::NANDECCES0: F4STAT Mask */ + +#define NFI_NANDECCES0_F4ECNT_Pos (26) /*!< NFI_T::NANDECCES0: F4ECNT Position */ +#define NFI_NANDECCES0_F4ECNT_Msk (0x1ful << NFI_NANDECCES0_F4ECNT_Pos) /*!< NFI_T::NANDECCES0: F4ECNT Mask */ + +#define NFI_NANDECCES1_F5STAT_Pos (0) /*!< NFI_T::NANDECCES1: F5STAT Position */ +#define NFI_NANDECCES1_F5STAT_Msk (0x3ul << NFI_NANDECCES1_F5STAT_Pos) /*!< NFI_T::NANDECCES1: F5STAT Mask */ + +#define NFI_NANDECCES1_F5ECNT_Pos (2) /*!< NFI_T::NANDECCES1: F5ECNT Position */ +#define NFI_NANDECCES1_F5ECNT_Msk (0x1ful << NFI_NANDECCES1_F5ECNT_Pos) /*!< NFI_T::NANDECCES1: F5ECNT Mask */ + +#define NFI_NANDECCES1_F6STAT_Pos (8) /*!< NFI_T::NANDECCES1: F6STAT Position */ +#define NFI_NANDECCES1_F6STAT_Msk (0x3ul << NFI_NANDECCES1_F6STAT_Pos) /*!< NFI_T::NANDECCES1: F6STAT Mask */ + +#define NFI_NANDECCES1_F6ECNT_Pos (10) /*!< NFI_T::NANDECCES1: F6ECNT Position */ +#define NFI_NANDECCES1_F6ECNT_Msk (0x1ful << NFI_NANDECCES1_F6ECNT_Pos) /*!< NFI_T::NANDECCES1: F6ECNT Mask */ + +#define NFI_NANDECCES1_F7STAT_Pos (16) /*!< NFI_T::NANDECCES1: F7STAT Position */ +#define NFI_NANDECCES1_F7STAT_Msk (0x3ul << NFI_NANDECCES1_F7STAT_Pos) /*!< NFI_T::NANDECCES1: F7STAT Mask */ + +#define NFI_NANDECCES1_F7ECNT_Pos (18) /*!< NFI_T::NANDECCES1: F7ECNT Position */ +#define NFI_NANDECCES1_F7ECNT_Msk (0x1ful << NFI_NANDECCES1_F7ECNT_Pos) /*!< NFI_T::NANDECCES1: F7ECNT Mask */ + +#define NFI_NANDECCES1_F8STAT_Pos (24) /*!< NFI_T::NANDECCES1: F8STAT Position */ +#define NFI_NANDECCES1_F8STAT_Msk (0x3ul << NFI_NANDECCES1_F8STAT_Pos) /*!< NFI_T::NANDECCES1: F8STAT Mask */ + +#define NFI_NANDECCES1_F8ECNT_Pos (26) /*!< NFI_T::NANDECCES1: F8ECNT Position */ +#define NFI_NANDECCES1_F8ECNT_Msk (0x1ful << NFI_NANDECCES1_F8ECNT_Pos) /*!< NFI_T::NANDECCES1: F8ECNT Mask */ + +#define NFI_NANDECCES2_F9STAT_Pos (0) /*!< NFI_T::NANDECCES2: F9STAT Position */ +#define NFI_NANDECCES2_F9STAT_Msk (0x3ul << NFI_NANDECCES2_F9STAT_Pos) /*!< NFI_T::NANDECCES2: F9STAT Mask */ + +#define NFI_NANDECCES2_F9ECNT_Pos (2) /*!< NFI_T::NANDECCES2: F9ECNT Position */ +#define NFI_NANDECCES2_F9ECNT_Msk (0x1ful << NFI_NANDECCES2_F9ECNT_Pos) /*!< NFI_T::NANDECCES2: F9ECNT Mask */ + +#define NFI_NANDECCES2_F10STAT_Pos (8) /*!< NFI_T::NANDECCES2: F10STAT Position */ +#define NFI_NANDECCES2_F10STAT_Msk (0x3ul << NFI_NANDECCES2_F10STAT_Pos) /*!< NFI_T::NANDECCES2: F10STAT Mask */ + +#define NFI_NANDECCES2_F10ECNT_Pos (10) /*!< NFI_T::NANDECCES2: F10ECNT Position */ +#define NFI_NANDECCES2_F10ECNT_Msk (0x1ful << NFI_NANDECCES2_F10ECNT_Pos) /*!< NFI_T::NANDECCES2: F10ECNT Mask */ + +#define NFI_NANDECCES2_F11STAT_Pos (16) /*!< NFI_T::NANDECCES2: F11STAT Position */ +#define NFI_NANDECCES2_F11STAT_Msk (0x3ul << NFI_NANDECCES2_F11STAT_Pos) /*!< NFI_T::NANDECCES2: F11STAT Mask */ + +#define NFI_NANDECCES2_F11ECNT_Pos (18) /*!< NFI_T::NANDECCES2: F11ECNT Position */ +#define NFI_NANDECCES2_F11ECNT_Msk (0x1ful << NFI_NANDECCES2_F11ECNT_Pos) /*!< NFI_T::NANDECCES2: F11ECNT Mask */ + +#define NFI_NANDECCES2_F12STAT_Pos (24) /*!< NFI_T::NANDECCES2: F12STAT Position */ +#define NFI_NANDECCES2_F12STAT_Msk (0x3ul << NFI_NANDECCES2_F12STAT_Pos) /*!< NFI_T::NANDECCES2: F12STAT Mask */ + +#define NFI_NANDECCES2_F12ECNT_Pos (26) /*!< NFI_T::NANDECCES2: F12ECNT Position */ +#define NFI_NANDECCES2_F12ECNT_Msk (0x1ful << NFI_NANDECCES2_F12ECNT_Pos) /*!< NFI_T::NANDECCES2: F12ECNT Mask */ + +#define NFI_NANDECCES3_F13STAT_Pos (0) /*!< NFI_T::NANDECCES3: F13STAT Position */ +#define NFI_NANDECCES3_F13STAT_Msk (0x3ul << NFI_NANDECCES3_F13STAT_Pos) /*!< NFI_T::NANDECCES3: F13STAT Mask */ + +#define NFI_NANDECCES3_F13ECNT_Pos (2) /*!< NFI_T::NANDECCES3: F13ECNT Position */ +#define NFI_NANDECCES3_F13ECNT_Msk (0x1ful << NFI_NANDECCES3_F13ECNT_Pos) /*!< NFI_T::NANDECCES3: F13ECNT Mask */ + +#define NFI_NANDECCES3_F14STAT_Pos (8) /*!< NFI_T::NANDECCES3: F14STAT Position */ +#define NFI_NANDECCES3_F14STAT_Msk (0x3ul << NFI_NANDECCES3_F14STAT_Pos) /*!< NFI_T::NANDECCES3: F14STAT Mask */ + +#define NFI_NANDECCES3_F14ECNT_Pos (10) /*!< NFI_T::NANDECCES3: F14ECNT Position */ +#define NFI_NANDECCES3_F14ECNT_Msk (0x1ful << NFI_NANDECCES3_F14ECNT_Pos) /*!< NFI_T::NANDECCES3: F14ECNT Mask */ + +#define NFI_NANDECCES3_F15STAT_Pos (16) /*!< NFI_T::NANDECCES3: F15STAT Position */ +#define NFI_NANDECCES3_F15STAT_Msk (0x3ul << NFI_NANDECCES3_F15STAT_Pos) /*!< NFI_T::NANDECCES3: F15STAT Mask */ + +#define NFI_NANDECCES3_F15ECNT_Pos (18) /*!< NFI_T::NANDECCES3: F15ECNT Position */ +#define NFI_NANDECCES3_F15ECNT_Msk (0x1ful << NFI_NANDECCES3_F15ECNT_Pos) /*!< NFI_T::NANDECCES3: F15ECNT Mask */ + +#define NFI_NANDECCES3_F16STAT_Pos (24) /*!< NFI_T::NANDECCES3: F16STAT Position */ +#define NFI_NANDECCES3_F16STAT_Msk (0x3ul << NFI_NANDECCES3_F16STAT_Pos) /*!< NFI_T::NANDECCES3: F16STAT Mask */ + +#define NFI_NANDECCES3_F16ECNT_Pos (26) /*!< NFI_T::NANDECCES3: F16ECNT Position */ +#define NFI_NANDECCES3_F16ECNT_Msk (0x1ful << NFI_NANDECCES3_F16ECNT_Pos) /*!< NFI_T::NANDECCES3: F16ECNT Mask */ + +#define NFI_NANDECCEA0_ERRADDR0_Pos (0) /*!< NFI_T::NANDECCEA0: ERRADDR0 Position */ +#define NFI_NANDECCEA0_ERRADDR0_Msk (0x7fful << NFI_NANDECCEA0_ERRADDR0_Pos) /*!< NFI_T::NANDECCEA0: ERRADDR0 Mask */ + +#define NFI_NANDECCEA0_ERRADDR1_Pos (16) /*!< NFI_T::NANDECCEA0: ERRADDR1 Position */ +#define NFI_NANDECCEA0_ERRADDR1_Msk (0x7fful << NFI_NANDECCEA0_ERRADDR1_Pos) /*!< NFI_T::NANDECCEA0: ERRADDR1 Mask */ + +#define NFI_NANDECCEA1_ERRADDR2_Pos (0) /*!< NFI_T::NANDECCEA1: ERRADDR2 Position */ +#define NFI_NANDECCEA1_ERRADDR2_Msk (0x7fful << NFI_NANDECCEA1_ERRADDR2_Pos) /*!< NFI_T::NANDECCEA1: ERRADDR2 Mask */ + +#define NFI_NANDECCEA1_ERRADDR3_Pos (16) /*!< NFI_T::NANDECCEA1: ERRADDR3 Position */ +#define NFI_NANDECCEA1_ERRADDR3_Msk (0x7fful << NFI_NANDECCEA1_ERRADDR3_Pos) /*!< NFI_T::NANDECCEA1: ERRADDR3 Mask */ + +#define NFI_NANDECCEA2_ERRADDR4_Pos (0) /*!< NFI_T::NANDECCEA2: ERRADDR4 Position */ +#define NFI_NANDECCEA2_ERRADDR4_Msk (0x7fful << NFI_NANDECCEA2_ERRADDR4_Pos) /*!< NFI_T::NANDECCEA2: ERRADDR4 Mask */ + +#define NFI_NANDECCEA2_ERRADDR5_Pos (16) /*!< NFI_T::NANDECCEA2: ERRADDR5 Position */ +#define NFI_NANDECCEA2_ERRADDR5_Msk (0x7fful << NFI_NANDECCEA2_ERRADDR5_Pos) /*!< NFI_T::NANDECCEA2: ERRADDR5 Mask */ + +#define NFI_NANDECCEA3_ERRADDR6_Pos (0) /*!< NFI_T::NANDECCEA3: ERRADDR6 Position */ +#define NFI_NANDECCEA3_ERRADDR6_Msk (0x7fful << NFI_NANDECCEA3_ERRADDR6_Pos) /*!< NFI_T::NANDECCEA3: ERRADDR6 Mask */ + +#define NFI_NANDECCEA3_ERRADDR7_Pos (16) /*!< NFI_T::NANDECCEA3: ERRADDR7 Position */ +#define NFI_NANDECCEA3_ERRADDR7_Msk (0x7fful << NFI_NANDECCEA3_ERRADDR7_Pos) /*!< NFI_T::NANDECCEA3: ERRADDR7 Mask */ + +#define NFI_NANDECCEA4_ERRADDR8_Pos (0) /*!< NFI_T::NANDECCEA4: ERRADDR8 Position */ +#define NFI_NANDECCEA4_ERRADDR8_Msk (0x7fful << NFI_NANDECCEA4_ERRADDR8_Pos) /*!< NFI_T::NANDECCEA4: ERRADDR8 Mask */ + +#define NFI_NANDECCEA4_ERRADDR9_Pos (16) /*!< NFI_T::NANDECCEA4: ERRADDR9 Position */ +#define NFI_NANDECCEA4_ERRADDR9_Msk (0x7fful << NFI_NANDECCEA4_ERRADDR9_Pos) /*!< NFI_T::NANDECCEA4: ERRADDR9 Mask */ + +#define NFI_NANDECCEA5_ERRADDR10_Pos (0) /*!< NFI_T::NANDECCEA5: ERRADDR10 Position */ +#define NFI_NANDECCEA5_ERRADDR10_Msk (0x7fful << NFI_NANDECCEA5_ERRADDR10_Pos) /*!< NFI_T::NANDECCEA5: ERRADDR10 Mask */ + +#define NFI_NANDECCEA5_ERRADDR11_Pos (16) /*!< NFI_T::NANDECCEA5: ERRADDR11 Position */ +#define NFI_NANDECCEA5_ERRADDR11_Msk (0x7fful << NFI_NANDECCEA5_ERRADDR11_Pos) /*!< NFI_T::NANDECCEA5: ERRADDR11 Mask */ + +#define NFI_NANDECCEA6_ERRADDR12_Pos (0) /*!< NFI_T::NANDECCEA6: ERRADDR12 Position */ +#define NFI_NANDECCEA6_ERRADDR12_Msk (0x7fful << NFI_NANDECCEA6_ERRADDR12_Pos) /*!< NFI_T::NANDECCEA6: ERRADDR12 Mask */ + +#define NFI_NANDECCEA6_ERRADDR13_Pos (16) /*!< NFI_T::NANDECCEA6: ERRADDR13 Position */ +#define NFI_NANDECCEA6_ERRADDR13_Msk (0x7fful << NFI_NANDECCEA6_ERRADDR13_Pos) /*!< NFI_T::NANDECCEA6: ERRADDR13 Mask */ + +#define NFI_NANDECCEA7_ERRADDR14_Pos (0) /*!< NFI_T::NANDECCEA7: ERRADDR14 Position */ +#define NFI_NANDECCEA7_ERRADDR14_Msk (0x7fful << NFI_NANDECCEA7_ERRADDR14_Pos) /*!< NFI_T::NANDECCEA7: ERRADDR14 Mask */ + +#define NFI_NANDECCEA7_ERRADDR15_Pos (16) /*!< NFI_T::NANDECCEA7: ERRADDR15 Position */ +#define NFI_NANDECCEA7_ERRADDR15_Msk (0x7fful << NFI_NANDECCEA7_ERRADDR15_Pos) /*!< NFI_T::NANDECCEA7: ERRADDR15 Mask */ + +#define NFI_NANDECCEA8_ERRADDR16_Pos (0) /*!< NFI_T::NANDECCEA8: ERRADDR16 Position */ +#define NFI_NANDECCEA8_ERRADDR16_Msk (0x7fful << NFI_NANDECCEA8_ERRADDR16_Pos) /*!< NFI_T::NANDECCEA8: ERRADDR16 Mask */ + +#define NFI_NANDECCEA8_ERRADDR17_Pos (16) /*!< NFI_T::NANDECCEA8: ERRADDR17 Position */ +#define NFI_NANDECCEA8_ERRADDR17_Msk (0x7fful << NFI_NANDECCEA8_ERRADDR17_Pos) /*!< NFI_T::NANDECCEA8: ERRADDR17 Mask */ + +#define NFI_NANDECCEA9_ERRADDR18_Pos (0) /*!< NFI_T::NANDECCEA9: ERRADDR18 Position */ +#define NFI_NANDECCEA9_ERRADDR18_Msk (0x7fful << NFI_NANDECCEA9_ERRADDR18_Pos) /*!< NFI_T::NANDECCEA9: ERRADDR18 Mask */ + +#define NFI_NANDECCEA9_ERRADDR19_Pos (16) /*!< NFI_T::NANDECCEA9: ERRADDR19 Position */ +#define NFI_NANDECCEA9_ERRADDR19_Msk (0x7fful << NFI_NANDECCEA9_ERRADDR19_Pos) /*!< NFI_T::NANDECCEA9: ERRADDR19 Mask */ + +#define NFI_NANDECCEA10_ERRADDR20_Pos (0) /*!< NFI_T::NANDECCEA10: ERRADDR20 Position */ +#define NFI_NANDECCEA10_ERRADDR20_Msk (0x7fful << NFI_NANDECCEA10_ERRADDR20_Pos) /*!< NFI_T::NANDECCEA10: ERRADDR20 Mask */ + +#define NFI_NANDECCEA10_ERRADDR21_Pos (16) /*!< NFI_T::NANDECCEA10: ERRADDR21 Position */ +#define NFI_NANDECCEA10_ERRADDR21_Msk (0x7fful << NFI_NANDECCEA10_ERRADDR21_Pos) /*!< NFI_T::NANDECCEA10: ERRADDR21 Mask */ + +#define NFI_NANDECCEA11_ERRADDR22_Pos (0) /*!< NFI_T::NANDECCEA11: ERRADDR22 Position */ +#define NFI_NANDECCEA11_ERRADDR22_Msk (0x7fful << NFI_NANDECCEA11_ERRADDR22_Pos) /*!< NFI_T::NANDECCEA11: ERRADDR22 Mask */ + +#define NFI_NANDECCEA11_ERRADDR23_Pos (16) /*!< NFI_T::NANDECCEA11: ERRADDR23 Position */ +#define NFI_NANDECCEA11_ERRADDR23_Msk (0x7fful << NFI_NANDECCEA11_ERRADDR23_Pos) /*!< NFI_T::NANDECCEA11: ERRADDR23 Mask */ + +#define NFI_NANDECCED0_ERRDATA0_Pos (0) /*!< NFI_T::NANDECCED0: ERRDATA0 Position */ +#define NFI_NANDECCED0_ERRDATA0_Msk (0xfful << NFI_NANDECCED0_ERRDATA0_Pos) /*!< NFI_T::NANDECCED0: ERRDATA0 Mask */ + +#define NFI_NANDECCED0_ERRDATA1_Pos (8) /*!< NFI_T::NANDECCED0: ERRDATA1 Position */ +#define NFI_NANDECCED0_ERRDATA1_Msk (0xfful << NFI_NANDECCED0_ERRDATA1_Pos) /*!< NFI_T::NANDECCED0: ERRDATA1 Mask */ + +#define NFI_NANDECCED0_ERRDATA2_Pos (16) /*!< NFI_T::NANDECCED0: ERRDATA2 Position */ +#define NFI_NANDECCED0_ERRDATA2_Msk (0xfful << NFI_NANDECCED0_ERRDATA2_Pos) /*!< NFI_T::NANDECCED0: ERRDATA2 Mask */ + +#define NFI_NANDECCED0_ERRDATA3_Pos (24) /*!< NFI_T::NANDECCED0: ERRDATA3 Position */ +#define NFI_NANDECCED0_ERRDATA3_Msk (0xfful << NFI_NANDECCED0_ERRDATA3_Pos) /*!< NFI_T::NANDECCED0: ERRDATA3 Mask */ + +#define NFI_NANDECCED1_ERRDATA4_Pos (0) /*!< NFI_T::NANDECCED1: ERRDATA4 Position */ +#define NFI_NANDECCED1_ERRDATA4_Msk (0xfful << NFI_NANDECCED1_ERRDATA4_Pos) /*!< NFI_T::NANDECCED1: ERRDATA4 Mask */ + +#define NFI_NANDECCED1_ERRDATA5_Pos (8) /*!< NFI_T::NANDECCED1: ERRDATA5 Position */ +#define NFI_NANDECCED1_ERRDATA5_Msk (0xfful << NFI_NANDECCED1_ERRDATA5_Pos) /*!< NFI_T::NANDECCED1: ERRDATA5 Mask */ + +#define NFI_NANDECCED1_ERRDATA6_Pos (16) /*!< NFI_T::NANDECCED1: ERRDATA6 Position */ +#define NFI_NANDECCED1_ERRDATA6_Msk (0xfful << NFI_NANDECCED1_ERRDATA6_Pos) /*!< NFI_T::NANDECCED1: ERRDATA6 Mask */ + +#define NFI_NANDECCED1_ERRDATA7_Pos (24) /*!< NFI_T::NANDECCED1: ERRDATA7 Position */ +#define NFI_NANDECCED1_ERRDATA7_Msk (0xfful << NFI_NANDECCED1_ERRDATA7_Pos) /*!< NFI_T::NANDECCED1: ERRDATA7 Mask */ + +#define NFI_NANDECCED2_ERRDATA8_Pos (0) /*!< NFI_T::NANDECCED2: ERRDATA8 Position */ +#define NFI_NANDECCED2_ERRDATA8_Msk (0xfful << NFI_NANDECCED2_ERRDATA8_Pos) /*!< NFI_T::NANDECCED2: ERRDATA8 Mask */ + +#define NFI_NANDECCED2_ERRDATA9_Pos (8) /*!< NFI_T::NANDECCED2: ERRDATA9 Position */ +#define NFI_NANDECCED2_ERRDATA9_Msk (0xfful << NFI_NANDECCED2_ERRDATA9_Pos) /*!< NFI_T::NANDECCED2: ERRDATA9 Mask */ + +#define NFI_NANDECCED2_ERRDATA10_Pos (16) /*!< NFI_T::NANDECCED2: ERRDATA10 Position */ +#define NFI_NANDECCED2_ERRDATA10_Msk (0xfful << NFI_NANDECCED2_ERRDATA10_Pos) /*!< NFI_T::NANDECCED2: ERRDATA10 Mask */ + +#define NFI_NANDECCED2_ERRDATA11_Pos (24) /*!< NFI_T::NANDECCED2: ERRDATA11 Position */ +#define NFI_NANDECCED2_ERRDATA11_Msk (0xfful << NFI_NANDECCED2_ERRDATA11_Pos) /*!< NFI_T::NANDECCED2: ERRDATA11 Mask */ + +#define NFI_NANDECCED3_ERRDATA12_Pos (0) /*!< NFI_T::NANDECCED3: ERRDATA12 Position */ +#define NFI_NANDECCED3_ERRDATA12_Msk (0xfful << NFI_NANDECCED3_ERRDATA12_Pos) /*!< NFI_T::NANDECCED3: ERRDATA12 Mask */ + +#define NFI_NANDECCED3_ERRDATA13_Pos (8) /*!< NFI_T::NANDECCED3: ERRDATA13 Position */ +#define NFI_NANDECCED3_ERRDATA13_Msk (0xfful << NFI_NANDECCED3_ERRDATA13_Pos) /*!< NFI_T::NANDECCED3: ERRDATA13 Mask */ + +#define NFI_NANDECCED3_ERRDATA14_Pos (16) /*!< NFI_T::NANDECCED3: ERRDATA14 Position */ +#define NFI_NANDECCED3_ERRDATA14_Msk (0xfful << NFI_NANDECCED3_ERRDATA14_Pos) /*!< NFI_T::NANDECCED3: ERRDATA14 Mask */ + +#define NFI_NANDECCED3_ERRDATA15_Pos (24) /*!< NFI_T::NANDECCED3: ERRDATA15 Position */ +#define NFI_NANDECCED3_ERRDATA15_Msk (0xfful << NFI_NANDECCED3_ERRDATA15_Pos) /*!< NFI_T::NANDECCED3: ERRDATA15 Mask */ + +#define NFI_NANDECCED4_ERRDATA16_Pos (0) /*!< NFI_T::NANDECCED4: ERRDATA16 Position */ +#define NFI_NANDECCED4_ERRDATA16_Msk (0xfful << NFI_NANDECCED4_ERRDATA16_Pos) /*!< NFI_T::NANDECCED4: ERRDATA16 Mask */ + +#define NFI_NANDECCED4_ERRDATA17_Pos (8) /*!< NFI_T::NANDECCED4: ERRDATA17 Position */ +#define NFI_NANDECCED4_ERRDATA17_Msk (0xfful << NFI_NANDECCED4_ERRDATA17_Pos) /*!< NFI_T::NANDECCED4: ERRDATA17 Mask */ + +#define NFI_NANDECCED4_ERRDATA18_Pos (16) /*!< NFI_T::NANDECCED4: ERRDATA18 Position */ +#define NFI_NANDECCED4_ERRDATA18_Msk (0xfful << NFI_NANDECCED4_ERRDATA18_Pos) /*!< NFI_T::NANDECCED4: ERRDATA18 Mask */ + +#define NFI_NANDECCED4_ERRDATA19_Pos (24) /*!< NFI_T::NANDECCED4: ERRDATA19 Position */ +#define NFI_NANDECCED4_ERRDATA19_Msk (0xfful << NFI_NANDECCED4_ERRDATA19_Pos) /*!< NFI_T::NANDECCED4: ERRDATA19 Mask */ + +#define NFI_NANDECCED5_ERRDATA20_Pos (0) /*!< NFI_T::NANDECCED5: ERRDATA20 Position */ +#define NFI_NANDECCED5_ERRDATA20_Msk (0xfful << NFI_NANDECCED5_ERRDATA20_Pos) /*!< NFI_T::NANDECCED5: ERRDATA20 Mask */ + +#define NFI_NANDECCED5_ERRDATA21_Pos (8) /*!< NFI_T::NANDECCED5: ERRDATA21 Position */ +#define NFI_NANDECCED5_ERRDATA21_Msk (0xfful << NFI_NANDECCED5_ERRDATA21_Pos) /*!< NFI_T::NANDECCED5: ERRDATA21 Mask */ + +#define NFI_NANDECCED5_ERRDATA22_Pos (16) /*!< NFI_T::NANDECCED5: ERRDATA22 Position */ +#define NFI_NANDECCED5_ERRDATA22_Msk (0xfful << NFI_NANDECCED5_ERRDATA22_Pos) /*!< NFI_T::NANDECCED5: ERRDATA22 Mask */ + +#define NFI_NANDECCED5_ERRDATA23_Pos (24) /*!< NFI_T::NANDECCED5: ERRDATA23 Position */ +#define NFI_NANDECCED5_ERRDATA23_Msk (0xfful << NFI_NANDECCED5_ERRDATA23_Pos) /*!< NFI_T::NANDECCED5: ERRDATA23 Mask */ + +#define NFI_NANDRA0_Data_Pos (0) /*!< NFI_T::NANDRA0: Data Position */ +#define NFI_NANDRA0_Data_Msk (0xfffffffful << NFI_NANDRA0_Data_Pos) /*!< NFI_T::NANDRA0: Data Mask */ + +#define NFI_NANDRA1_Data_Pos (0) /*!< NFI_T::NANDRA1: Data Position */ +#define NFI_NANDRA1_Data_Msk (0xfffffffful << NFI_NANDRA1_Data_Pos) /*!< NFI_T::NANDRA1: Data Mask */ + +#define NFI_NANDRA2_Data_Pos (0) /*!< NFI_T::NANDRA2: Data Position */ +#define NFI_NANDRA2_Data_Msk (0xfffffffful << NFI_NANDRA2_Data_Pos) /*!< NFI_T::NANDRA2: Data Mask */ + +#define NFI_NANDRA3_Data_Pos (0) /*!< NFI_T::NANDRA3: Data Position */ +#define NFI_NANDRA3_Data_Msk (0xfffffffful << NFI_NANDRA3_Data_Pos) /*!< NFI_T::NANDRA3: Data Mask */ + +#define NFI_NANDRA4_Data_Pos (0) /*!< NFI_T::NANDRA4: Data Position */ +#define NFI_NANDRA4_Data_Msk (0xfffffffful << NFI_NANDRA4_Data_Pos) /*!< NFI_T::NANDRA4: Data Mask */ + +#define NFI_NANDRA5_Data_Pos (0) /*!< NFI_T::NANDRA5: Data Position */ +#define NFI_NANDRA5_Data_Msk (0xfffffffful << NFI_NANDRA5_Data_Pos) /*!< NFI_T::NANDRA5: Data Mask */ + +#define NFI_NANDRA6_Data_Pos (0) /*!< NFI_T::NANDRA6: Data Position */ +#define NFI_NANDRA6_Data_Msk (0xfffffffful << NFI_NANDRA6_Data_Pos) /*!< NFI_T::NANDRA6: Data Mask */ + +#define NFI_NANDRA7_Data_Pos (0) /*!< NFI_T::NANDRA7: Data Position */ +#define NFI_NANDRA7_Data_Msk (0xfffffffful << NFI_NANDRA7_Data_Pos) /*!< NFI_T::NANDRA7: Data Mask */ + +#define NFI_NANDRA8_Data_Pos (0) /*!< NFI_T::NANDRA8: Data Position */ +#define NFI_NANDRA8_Data_Msk (0xfffffffful << NFI_NANDRA8_Data_Pos) /*!< NFI_T::NANDRA8: Data Mask */ + +#define NFI_NANDRA9_Data_Pos (0) /*!< NFI_T::NANDRA9: Data Position */ +#define NFI_NANDRA9_Data_Msk (0xfffffffful << NFI_NANDRA9_Data_Pos) /*!< NFI_T::NANDRA9: Data Mask */ + +#define NFI_NANDRA10_Data_Pos (0) /*!< NFI_T::NANDRA10: Data Position */ +#define NFI_NANDRA10_Data_Msk (0xfffffffful << NFI_NANDRA10_Data_Pos) /*!< NFI_T::NANDRA10: Data Mask */ + +#define NFI_NANDRA11_Data_Pos (0) /*!< NFI_T::NANDRA11: Data Position */ +#define NFI_NANDRA11_Data_Msk (0xfffffffful << NFI_NANDRA11_Data_Pos) /*!< NFI_T::NANDRA11: Data Mask */ + +#define NFI_NANDRA12_Data_Pos (0) /*!< NFI_T::NANDRA12: Data Position */ +#define NFI_NANDRA12_Data_Msk (0xfffffffful << NFI_NANDRA12_Data_Pos) /*!< NFI_T::NANDRA12: Data Mask */ + +#define NFI_NANDRA13_Data_Pos (0) /*!< NFI_T::NANDRA13: Data Position */ +#define NFI_NANDRA13_Data_Msk (0xfffffffful << NFI_NANDRA13_Data_Pos) /*!< NFI_T::NANDRA13: Data Mask */ + +#define NFI_NANDRA14_Data_Pos (0) /*!< NFI_T::NANDRA14: Data Position */ +#define NFI_NANDRA14_Data_Msk (0xfffffffful << NFI_NANDRA14_Data_Pos) /*!< NFI_T::NANDRA14: Data Mask */ + +#define NFI_NANDRA15_Data_Pos (0) /*!< NFI_T::NANDRA15: Data Position */ +#define NFI_NANDRA15_Data_Msk (0xfffffffful << NFI_NANDRA15_Data_Pos) /*!< NFI_T::NANDRA15: Data Mask */ + +#define NFI_NANDRA16_Data_Pos (0) /*!< NFI_T::NANDRA16: Data Position */ +#define NFI_NANDRA16_Data_Msk (0xfffffffful << NFI_NANDRA16_Data_Pos) /*!< NFI_T::NANDRA16: Data Mask */ + +#define NFI_NANDRA17_Data_Pos (0) /*!< NFI_T::NANDRA17: Data Position */ +#define NFI_NANDRA17_Data_Msk (0xfffffffful << NFI_NANDRA17_Data_Pos) /*!< NFI_T::NANDRA17: Data Mask */ + +#define NFI_NANDRA18_Data_Pos (0) /*!< NFI_T::NANDRA18: Data Position */ +#define NFI_NANDRA18_Data_Msk (0xfffffffful << NFI_NANDRA18_Data_Pos) /*!< NFI_T::NANDRA18: Data Mask */ + +#define NFI_NANDRA19_Data_Pos (0) /*!< NFI_T::NANDRA19: Data Position */ +#define NFI_NANDRA19_Data_Msk (0xfffffffful << NFI_NANDRA19_Data_Pos) /*!< NFI_T::NANDRA19: Data Mask */ + +#define NFI_NANDRA20_Data_Pos (0) /*!< NFI_T::NANDRA20: Data Position */ +#define NFI_NANDRA20_Data_Msk (0xfffffffful << NFI_NANDRA20_Data_Pos) /*!< NFI_T::NANDRA20: Data Mask */ + +#define NFI_NANDRA21_Data_Pos (0) /*!< NFI_T::NANDRA21: Data Position */ +#define NFI_NANDRA21_Data_Msk (0xfffffffful << NFI_NANDRA21_Data_Pos) /*!< NFI_T::NANDRA21: Data Mask */ + +#define NFI_NANDRA22_Data_Pos (0) /*!< NFI_T::NANDRA22: Data Position */ +#define NFI_NANDRA22_Data_Msk (0xfffffffful << NFI_NANDRA22_Data_Pos) /*!< NFI_T::NANDRA22: Data Mask */ + +#define NFI_NANDRA23_Data_Pos (0) /*!< NFI_T::NANDRA23: Data Position */ +#define NFI_NANDRA23_Data_Msk (0xfffffffful << NFI_NANDRA23_Data_Pos) /*!< NFI_T::NANDRA23: Data Mask */ + +#define NFI_NANDRA24_Data_Pos (0) /*!< NFI_T::NANDRA24: Data Position */ +#define NFI_NANDRA24_Data_Msk (0xfffffffful << NFI_NANDRA24_Data_Pos) /*!< NFI_T::NANDRA24: Data Mask */ + +#define NFI_NANDRA25_Data_Pos (0) /*!< NFI_T::NANDRA25: Data Position */ +#define NFI_NANDRA25_Data_Msk (0xfffffffful << NFI_NANDRA25_Data_Pos) /*!< NFI_T::NANDRA25: Data Mask */ + +#define NFI_NANDRA26_Data_Pos (0) /*!< NFI_T::NANDRA26: Data Position */ +#define NFI_NANDRA26_Data_Msk (0xfffffffful << NFI_NANDRA26_Data_Pos) /*!< NFI_T::NANDRA26: Data Mask */ + +#define NFI_NANDRA27_Data_Pos (0) /*!< NFI_T::NANDRA27: Data Position */ +#define NFI_NANDRA27_Data_Msk (0xfffffffful << NFI_NANDRA27_Data_Pos) /*!< NFI_T::NANDRA27: Data Mask */ + +#define NFI_NANDRA28_Data_Pos (0) /*!< NFI_T::NANDRA28: Data Position */ +#define NFI_NANDRA28_Data_Msk (0xfffffffful << NFI_NANDRA28_Data_Pos) /*!< NFI_T::NANDRA28: Data Mask */ + +#define NFI_NANDRA29_Data_Pos (0) /*!< NFI_T::NANDRA29: Data Position */ +#define NFI_NANDRA29_Data_Msk (0xfffffffful << NFI_NANDRA29_Data_Pos) /*!< NFI_T::NANDRA29: Data Mask */ + +#define NFI_NANDRA30_Data_Pos (0) /*!< NFI_T::NANDRA30: Data Position */ +#define NFI_NANDRA30_Data_Msk (0xfffffffful << NFI_NANDRA30_Data_Pos) /*!< NFI_T::NANDRA30: Data Mask */ + +#define NFI_NANDRA31_Data_Pos (0) /*!< NFI_T::NANDRA31: Data Position */ +#define NFI_NANDRA31_Data_Msk (0xfffffffful << NFI_NANDRA31_Data_Pos) /*!< NFI_T::NANDRA31: Data Mask */ + +#define NFI_NANDRA32_Data_Pos (0) /*!< NFI_T::NANDRA32: Data Position */ +#define NFI_NANDRA32_Data_Msk (0xfffffffful << NFI_NANDRA32_Data_Pos) /*!< NFI_T::NANDRA32: Data Mask */ + +#define NFI_NANDRA33_Data_Pos (0) /*!< NFI_T::NANDRA33: Data Position */ +#define NFI_NANDRA33_Data_Msk (0xfffffffful << NFI_NANDRA33_Data_Pos) /*!< NFI_T::NANDRA33: Data Mask */ + +#define NFI_NANDRA34_Data_Pos (0) /*!< NFI_T::NANDRA34: Data Position */ +#define NFI_NANDRA34_Data_Msk (0xfffffffful << NFI_NANDRA34_Data_Pos) /*!< NFI_T::NANDRA34: Data Mask */ + +#define NFI_NANDRA35_Data_Pos (0) /*!< NFI_T::NANDRA35: Data Position */ +#define NFI_NANDRA35_Data_Msk (0xfffffffful << NFI_NANDRA35_Data_Pos) /*!< NFI_T::NANDRA35: Data Mask */ + +#define NFI_NANDRA36_Data_Pos (0) /*!< NFI_T::NANDRA36: Data Position */ +#define NFI_NANDRA36_Data_Msk (0xfffffffful << NFI_NANDRA36_Data_Pos) /*!< NFI_T::NANDRA36: Data Mask */ + +#define NFI_NANDRA37_Data_Pos (0) /*!< NFI_T::NANDRA37: Data Position */ +#define NFI_NANDRA37_Data_Msk (0xfffffffful << NFI_NANDRA37_Data_Pos) /*!< NFI_T::NANDRA37: Data Mask */ + +#define NFI_NANDRA38_Data_Pos (0) /*!< NFI_T::NANDRA38: Data Position */ +#define NFI_NANDRA38_Data_Msk (0xfffffffful << NFI_NANDRA38_Data_Pos) /*!< NFI_T::NANDRA38: Data Mask */ + +#define NFI_NANDRA39_Data_Pos (0) /*!< NFI_T::NANDRA39: Data Position */ +#define NFI_NANDRA39_Data_Msk (0xfffffffful << NFI_NANDRA39_Data_Pos) /*!< NFI_T::NANDRA39: Data Mask */ + +#define NFI_NANDRA40_Data_Pos (0) /*!< NFI_T::NANDRA40: Data Position */ +#define NFI_NANDRA40_Data_Msk (0xfffffffful << NFI_NANDRA40_Data_Pos) /*!< NFI_T::NANDRA40: Data Mask */ + +#define NFI_NANDRA41_Data_Pos (0) /*!< NFI_T::NANDRA41: Data Position */ +#define NFI_NANDRA41_Data_Msk (0xfffffffful << NFI_NANDRA41_Data_Pos) /*!< NFI_T::NANDRA41: Data Mask */ + +#define NFI_NANDRA42_Data_Pos (0) /*!< NFI_T::NANDRA42: Data Position */ +#define NFI_NANDRA42_Data_Msk (0xfffffffful << NFI_NANDRA42_Data_Pos) /*!< NFI_T::NANDRA42: Data Mask */ + +#define NFI_NANDRA43_Data_Pos (0) /*!< NFI_T::NANDRA43: Data Position */ +#define NFI_NANDRA43_Data_Msk (0xfffffffful << NFI_NANDRA43_Data_Pos) /*!< NFI_T::NANDRA43: Data Mask */ + +#define NFI_NANDRA44_Data_Pos (0) /*!< NFI_T::NANDRA44: Data Position */ +#define NFI_NANDRA44_Data_Msk (0xfffffffful << NFI_NANDRA44_Data_Pos) /*!< NFI_T::NANDRA44: Data Mask */ + +#define NFI_NANDRA45_Data_Pos (0) /*!< NFI_T::NANDRA45: Data Position */ +#define NFI_NANDRA45_Data_Msk (0xfffffffful << NFI_NANDRA45_Data_Pos) /*!< NFI_T::NANDRA45: Data Mask */ + +#define NFI_NANDRA46_Data_Pos (0) /*!< NFI_T::NANDRA46: Data Position */ +#define NFI_NANDRA46_Data_Msk (0xfffffffful << NFI_NANDRA46_Data_Pos) /*!< NFI_T::NANDRA46: Data Mask */ + +#define NFI_NANDRA47_Data_Pos (0) /*!< NFI_T::NANDRA47: Data Position */ +#define NFI_NANDRA47_Data_Msk (0xfffffffful << NFI_NANDRA47_Data_Pos) /*!< NFI_T::NANDRA47: Data Mask */ + +#define NFI_NANDRA48_Data_Pos (0) /*!< NFI_T::NANDRA48: Data Position */ +#define NFI_NANDRA48_Data_Msk (0xfffffffful << NFI_NANDRA48_Data_Pos) /*!< NFI_T::NANDRA48: Data Mask */ + +#define NFI_NANDRA49_Data_Pos (0) /*!< NFI_T::NANDRA49: Data Position */ +#define NFI_NANDRA49_Data_Msk (0xfffffffful << NFI_NANDRA49_Data_Pos) /*!< NFI_T::NANDRA49: Data Mask */ + +#define NFI_NANDRA50_Data_Pos (0) /*!< NFI_T::NANDRA50: Data Position */ +#define NFI_NANDRA50_Data_Msk (0xfffffffful << NFI_NANDRA50_Data_Pos) /*!< NFI_T::NANDRA50: Data Mask */ + +#define NFI_NANDRA51_Data_Pos (0) /*!< NFI_T::NANDRA51: Data Position */ +#define NFI_NANDRA51_Data_Msk (0xfffffffful << NFI_NANDRA51_Data_Pos) /*!< NFI_T::NANDRA51: Data Mask */ + +#define NFI_NANDRA52_Data_Pos (0) /*!< NFI_T::NANDRA52: Data Position */ +#define NFI_NANDRA52_Data_Msk (0xfffffffful << NFI_NANDRA52_Data_Pos) /*!< NFI_T::NANDRA52: Data Mask */ + +#define NFI_NANDRA53_Data_Pos (0) /*!< NFI_T::NANDRA53: Data Position */ +#define NFI_NANDRA53_Data_Msk (0xfffffffful << NFI_NANDRA53_Data_Pos) /*!< NFI_T::NANDRA53: Data Mask */ + +#define NFI_NANDRA54_Data_Pos (0) /*!< NFI_T::NANDRA54: Data Position */ +#define NFI_NANDRA54_Data_Msk (0xfffffffful << NFI_NANDRA54_Data_Pos) /*!< NFI_T::NANDRA54: Data Mask */ + +#define NFI_NANDRA55_Data_Pos (0) /*!< NFI_T::NANDRA55: Data Position */ +#define NFI_NANDRA55_Data_Msk (0xfffffffful << NFI_NANDRA55_Data_Pos) /*!< NFI_T::NANDRA55: Data Mask */ + +#define NFI_NANDRA56_Data_Pos (0) /*!< NFI_T::NANDRA56: Data Position */ +#define NFI_NANDRA56_Data_Msk (0xfffffffful << NFI_NANDRA56_Data_Pos) /*!< NFI_T::NANDRA56: Data Mask */ + +#define NFI_NANDRA57_Data_Pos (0) /*!< NFI_T::NANDRA57: Data Position */ +#define NFI_NANDRA57_Data_Msk (0xfffffffful << NFI_NANDRA57_Data_Pos) /*!< NFI_T::NANDRA57: Data Mask */ + +#define NFI_NANDRA58_Data_Pos (0) /*!< NFI_T::NANDRA58: Data Position */ +#define NFI_NANDRA58_Data_Msk (0xfffffffful << NFI_NANDRA58_Data_Pos) /*!< NFI_T::NANDRA58: Data Mask */ + +#define NFI_NANDRA59_Data_Pos (0) /*!< NFI_T::NANDRA59: Data Position */ +#define NFI_NANDRA59_Data_Msk (0xfffffffful << NFI_NANDRA59_Data_Pos) /*!< NFI_T::NANDRA59: Data Mask */ + +#define NFI_NANDRA60_Data_Pos (0) /*!< NFI_T::NANDRA60: Data Position */ +#define NFI_NANDRA60_Data_Msk (0xfffffffful << NFI_NANDRA60_Data_Pos) /*!< NFI_T::NANDRA60: Data Mask */ + +#define NFI_NANDRA61_Data_Pos (0) /*!< NFI_T::NANDRA61: Data Position */ +#define NFI_NANDRA61_Data_Msk (0xfffffffful << NFI_NANDRA61_Data_Pos) /*!< NFI_T::NANDRA61: Data Mask */ + +#define NFI_NANDRA62_Data_Pos (0) /*!< NFI_T::NANDRA62: Data Position */ +#define NFI_NANDRA62_Data_Msk (0xfffffffful << NFI_NANDRA62_Data_Pos) /*!< NFI_T::NANDRA62: Data Mask */ + +#define NFI_NANDRA63_Data_Pos (0) /*!< NFI_T::NANDRA63: Data Position */ +#define NFI_NANDRA63_Data_Msk (0xfffffffful << NFI_NANDRA63_Data_Pos) /*!< NFI_T::NANDRA63: Data Mask */ + +#define NFI_NANDRA64_Data_Pos (0) /*!< NFI_T::NANDRA64: Data Position */ +#define NFI_NANDRA64_Data_Msk (0xfffffffful << NFI_NANDRA64_Data_Pos) /*!< NFI_T::NANDRA64: Data Mask */ + +#define NFI_NANDRA65_Data_Pos (0) /*!< NFI_T::NANDRA65: Data Position */ +#define NFI_NANDRA65_Data_Msk (0xfffffffful << NFI_NANDRA65_Data_Pos) /*!< NFI_T::NANDRA65: Data Mask */ + +#define NFI_NANDRA66_Data_Pos (0) /*!< NFI_T::NANDRA66: Data Position */ +#define NFI_NANDRA66_Data_Msk (0xfffffffful << NFI_NANDRA66_Data_Pos) /*!< NFI_T::NANDRA66: Data Mask */ + +#define NFI_NANDRA67_Data_Pos (0) /*!< NFI_T::NANDRA67: Data Position */ +#define NFI_NANDRA67_Data_Msk (0xfffffffful << NFI_NANDRA67_Data_Pos) /*!< NFI_T::NANDRA67: Data Mask */ + +#define NFI_NANDRA68_Data_Pos (0) /*!< NFI_T::NANDRA68: Data Position */ +#define NFI_NANDRA68_Data_Msk (0xfffffffful << NFI_NANDRA68_Data_Pos) /*!< NFI_T::NANDRA68: Data Mask */ + +#define NFI_NANDRA69_Data_Pos (0) /*!< NFI_T::NANDRA69: Data Position */ +#define NFI_NANDRA69_Data_Msk (0xfffffffful << NFI_NANDRA69_Data_Pos) /*!< NFI_T::NANDRA69: Data Mask */ + +#define NFI_NANDRA70_Data_Pos (0) /*!< NFI_T::NANDRA70: Data Position */ +#define NFI_NANDRA70_Data_Msk (0xfffffffful << NFI_NANDRA70_Data_Pos) /*!< NFI_T::NANDRA70: Data Mask */ + +#define NFI_NANDRA71_Data_Pos (0) /*!< NFI_T::NANDRA71: Data Position */ +#define NFI_NANDRA71_Data_Msk (0xfffffffful << NFI_NANDRA71_Data_Pos) /*!< NFI_T::NANDRA71: Data Mask */ + +#define NFI_NANDRA72_Data_Pos (0) /*!< NFI_T::NANDRA72: Data Position */ +#define NFI_NANDRA72_Data_Msk (0xfffffffful << NFI_NANDRA72_Data_Pos) /*!< NFI_T::NANDRA72: Data Mask */ + +#define NFI_NANDRA73_Data_Pos (0) /*!< NFI_T::NANDRA73: Data Position */ +#define NFI_NANDRA73_Data_Msk (0xfffffffful << NFI_NANDRA73_Data_Pos) /*!< NFI_T::NANDRA73: Data Mask */ + +#define NFI_NANDRA74_Data_Pos (0) /*!< NFI_T::NANDRA74: Data Position */ +#define NFI_NANDRA74_Data_Msk (0xfffffffful << NFI_NANDRA74_Data_Pos) /*!< NFI_T::NANDRA74: Data Mask */ + +#define NFI_NANDRA75_Data_Pos (0) /*!< NFI_T::NANDRA75: Data Position */ +#define NFI_NANDRA75_Data_Msk (0xfffffffful << NFI_NANDRA75_Data_Pos) /*!< NFI_T::NANDRA75: Data Mask */ + +#define NFI_NANDRA76_Data_Pos (0) /*!< NFI_T::NANDRA76: Data Position */ +#define NFI_NANDRA76_Data_Msk (0xfffffffful << NFI_NANDRA76_Data_Pos) /*!< NFI_T::NANDRA76: Data Mask */ + +#define NFI_NANDRA77_Data_Pos (0) /*!< NFI_T::NANDRA77: Data Position */ +#define NFI_NANDRA77_Data_Msk (0xfffffffful << NFI_NANDRA77_Data_Pos) /*!< NFI_T::NANDRA77: Data Mask */ + +#define NFI_NANDRA78_Data_Pos (0) /*!< NFI_T::NANDRA78: Data Position */ +#define NFI_NANDRA78_Data_Msk (0xfffffffful << NFI_NANDRA78_Data_Pos) /*!< NFI_T::NANDRA78: Data Mask */ + +#define NFI_NANDRA79_Data_Pos (0) /*!< NFI_T::NANDRA79: Data Position */ +#define NFI_NANDRA79_Data_Msk (0xfffffffful << NFI_NANDRA79_Data_Pos) /*!< NFI_T::NANDRA79: Data Mask */ + +#define NFI_NANDRA80_Data_Pos (0) /*!< NFI_T::NANDRA80: Data Position */ +#define NFI_NANDRA80_Data_Msk (0xfffffffful << NFI_NANDRA80_Data_Pos) /*!< NFI_T::NANDRA80: Data Mask */ + +#define NFI_NANDRA81_Data_Pos (0) /*!< NFI_T::NANDRA81: Data Position */ +#define NFI_NANDRA81_Data_Msk (0xfffffffful << NFI_NANDRA81_Data_Pos) /*!< NFI_T::NANDRA81: Data Mask */ + +#define NFI_NANDRA82_Data_Pos (0) /*!< NFI_T::NANDRA82: Data Position */ +#define NFI_NANDRA82_Data_Msk (0xfffffffful << NFI_NANDRA82_Data_Pos) /*!< NFI_T::NANDRA82: Data Mask */ + +#define NFI_NANDRA83_Data_Pos (0) /*!< NFI_T::NANDRA83: Data Position */ +#define NFI_NANDRA83_Data_Msk (0xfffffffful << NFI_NANDRA83_Data_Pos) /*!< NFI_T::NANDRA83: Data Mask */ + +#define NFI_NANDRA84_Data_Pos (0) /*!< NFI_T::NANDRA84: Data Position */ +#define NFI_NANDRA84_Data_Msk (0xfffffffful << NFI_NANDRA84_Data_Pos) /*!< NFI_T::NANDRA84: Data Mask */ + +#define NFI_NANDRA85_Data_Pos (0) /*!< NFI_T::NANDRA85: Data Position */ +#define NFI_NANDRA85_Data_Msk (0xfffffffful << NFI_NANDRA85_Data_Pos) /*!< NFI_T::NANDRA85: Data Mask */ + +#define NFI_NANDRA86_Data_Pos (0) /*!< NFI_T::NANDRA86: Data Position */ +#define NFI_NANDRA86_Data_Msk (0xfffffffful << NFI_NANDRA86_Data_Pos) /*!< NFI_T::NANDRA86: Data Mask */ + +#define NFI_NANDRA87_Data_Pos (0) /*!< NFI_T::NANDRA87: Data Position */ +#define NFI_NANDRA87_Data_Msk (0xfffffffful << NFI_NANDRA87_Data_Pos) /*!< NFI_T::NANDRA87: Data Mask */ + +#define NFI_NANDRA88_Data_Pos (0) /*!< NFI_T::NANDRA88: Data Position */ +#define NFI_NANDRA88_Data_Msk (0xfffffffful << NFI_NANDRA88_Data_Pos) /*!< NFI_T::NANDRA88: Data Mask */ + +#define NFI_NANDRA89_Data_Pos (0) /*!< NFI_T::NANDRA89: Data Position */ +#define NFI_NANDRA89_Data_Msk (0xfffffffful << NFI_NANDRA89_Data_Pos) /*!< NFI_T::NANDRA89: Data Mask */ + +#define NFI_NANDRA90_Data_Pos (0) /*!< NFI_T::NANDRA90: Data Position */ +#define NFI_NANDRA90_Data_Msk (0xfffffffful << NFI_NANDRA90_Data_Pos) /*!< NFI_T::NANDRA90: Data Mask */ + +#define NFI_NANDRA91_Data_Pos (0) /*!< NFI_T::NANDRA91: Data Position */ +#define NFI_NANDRA91_Data_Msk (0xfffffffful << NFI_NANDRA91_Data_Pos) /*!< NFI_T::NANDRA91: Data Mask */ + +#define NFI_NANDRA92_Data_Pos (0) /*!< NFI_T::NANDRA92: Data Position */ +#define NFI_NANDRA92_Data_Msk (0xfffffffful << NFI_NANDRA92_Data_Pos) /*!< NFI_T::NANDRA92: Data Mask */ + +#define NFI_NANDRA93_Data_Pos (0) /*!< NFI_T::NANDRA93: Data Position */ +#define NFI_NANDRA93_Data_Msk (0xfffffffful << NFI_NANDRA93_Data_Pos) /*!< NFI_T::NANDRA93: Data Mask */ + +#define NFI_NANDRA94_Data_Pos (0) /*!< NFI_T::NANDRA94: Data Position */ +#define NFI_NANDRA94_Data_Msk (0xfffffffful << NFI_NANDRA94_Data_Pos) /*!< NFI_T::NANDRA94: Data Mask */ + +#define NFI_NANDRA95_Data_Pos (0) /*!< NFI_T::NANDRA95: Data Position */ +#define NFI_NANDRA95_Data_Msk (0xfffffffful << NFI_NANDRA95_Data_Pos) /*!< NFI_T::NANDRA95: Data Mask */ + +#define NFI_NANDRA96_Data_Pos (0) /*!< NFI_T::NANDRA96: Data Position */ +#define NFI_NANDRA96_Data_Msk (0xfffffffful << NFI_NANDRA96_Data_Pos) /*!< NFI_T::NANDRA96: Data Mask */ + +#define NFI_NANDRA97_Data_Pos (0) /*!< NFI_T::NANDRA97: Data Position */ +#define NFI_NANDRA97_Data_Msk (0xfffffffful << NFI_NANDRA97_Data_Pos) /*!< NFI_T::NANDRA97: Data Mask */ + +#define NFI_NANDRA98_Data_Pos (0) /*!< NFI_T::NANDRA98: Data Position */ +#define NFI_NANDRA98_Data_Msk (0xfffffffful << NFI_NANDRA98_Data_Pos) /*!< NFI_T::NANDRA98: Data Mask */ + +#define NFI_NANDRA99_Data_Pos (0) /*!< NFI_T::NANDRA99: Data Position */ +#define NFI_NANDRA99_Data_Msk (0xfffffffful << NFI_NANDRA99_Data_Pos) /*!< NFI_T::NANDRA99: Data Mask */ + +#define NFI_NANDRA100_Data_Pos (0) /*!< NFI_T::NANDRA100: Data Position */ +#define NFI_NANDRA100_Data_Msk (0xfffffffful << NFI_NANDRA100_Data_Pos) /*!< NFI_T::NANDRA100: Data Mask */ + +#define NFI_NANDRA101_Data_Pos (0) /*!< NFI_T::NANDRA101: Data Position */ +#define NFI_NANDRA101_Data_Msk (0xfffffffful << NFI_NANDRA101_Data_Pos) /*!< NFI_T::NANDRA101: Data Mask */ + +#define NFI_NANDRA102_Data_Pos (0) /*!< NFI_T::NANDRA102: Data Position */ +#define NFI_NANDRA102_Data_Msk (0xfffffffful << NFI_NANDRA102_Data_Pos) /*!< NFI_T::NANDRA102: Data Mask */ + +#define NFI_NANDRA103_Data_Pos (0) /*!< NFI_T::NANDRA103: Data Position */ +#define NFI_NANDRA103_Data_Msk (0xfffffffful << NFI_NANDRA103_Data_Pos) /*!< NFI_T::NANDRA103: Data Mask */ + +#define NFI_NANDRA104_Data_Pos (0) /*!< NFI_T::NANDRA104: Data Position */ +#define NFI_NANDRA104_Data_Msk (0xfffffffful << NFI_NANDRA104_Data_Pos) /*!< NFI_T::NANDRA104: Data Mask */ + +#define NFI_NANDRA105_Data_Pos (0) /*!< NFI_T::NANDRA105: Data Position */ +#define NFI_NANDRA105_Data_Msk (0xfffffffful << NFI_NANDRA105_Data_Pos) /*!< NFI_T::NANDRA105: Data Mask */ + +#define NFI_NANDRA106_Data_Pos (0) /*!< NFI_T::NANDRA106: Data Position */ +#define NFI_NANDRA106_Data_Msk (0xfffffffful << NFI_NANDRA106_Data_Pos) /*!< NFI_T::NANDRA106: Data Mask */ + +#define NFI_NANDRA107_Data_Pos (0) /*!< NFI_T::NANDRA107: Data Position */ +#define NFI_NANDRA107_Data_Msk (0xfffffffful << NFI_NANDRA107_Data_Pos) /*!< NFI_T::NANDRA107: Data Mask */ + +#define NFI_NANDRA108_Data_Pos (0) /*!< NFI_T::NANDRA108: Data Position */ +#define NFI_NANDRA108_Data_Msk (0xfffffffful << NFI_NANDRA108_Data_Pos) /*!< NFI_T::NANDRA108: Data Mask */ + +#define NFI_NANDRA109_Data_Pos (0) /*!< NFI_T::NANDRA109: Data Position */ +#define NFI_NANDRA109_Data_Msk (0xfffffffful << NFI_NANDRA109_Data_Pos) /*!< NFI_T::NANDRA109: Data Mask */ + +#define NFI_NANDRA110_Data_Pos (0) /*!< NFI_T::NANDRA110: Data Position */ +#define NFI_NANDRA110_Data_Msk (0xfffffffful << NFI_NANDRA110_Data_Pos) /*!< NFI_T::NANDRA110: Data Mask */ + +#define NFI_NANDRA111_Data_Pos (0) /*!< NFI_T::NANDRA111: Data Position */ +#define NFI_NANDRA111_Data_Msk (0xfffffffful << NFI_NANDRA111_Data_Pos) /*!< NFI_T::NANDRA111: Data Mask */ + +#define NFI_NANDRA112_Data_Pos (0) /*!< NFI_T::NANDRA112: Data Position */ +#define NFI_NANDRA112_Data_Msk (0xfffffffful << NFI_NANDRA112_Data_Pos) /*!< NFI_T::NANDRA112: Data Mask */ + +#define NFI_NANDRA113_Data_Pos (0) /*!< NFI_T::NANDRA113: Data Position */ +#define NFI_NANDRA113_Data_Msk (0xfffffffful << NFI_NANDRA113_Data_Pos) /*!< NFI_T::NANDRA113: Data Mask */ + +#define NFI_NANDRA114_Data_Pos (0) /*!< NFI_T::NANDRA114: Data Position */ +#define NFI_NANDRA114_Data_Msk (0xfffffffful << NFI_NANDRA114_Data_Pos) /*!< NFI_T::NANDRA114: Data Mask */ + +#define NFI_NANDRA115_Data_Pos (0) /*!< NFI_T::NANDRA115: Data Position */ +#define NFI_NANDRA115_Data_Msk (0xfffffffful << NFI_NANDRA115_Data_Pos) /*!< NFI_T::NANDRA115: Data Mask */ + +#define NFI_NANDRA116_Data_Pos (0) /*!< NFI_T::NANDRA116: Data Position */ +#define NFI_NANDRA116_Data_Msk (0xfffffffful << NFI_NANDRA116_Data_Pos) /*!< NFI_T::NANDRA116: Data Mask */ + +#define NFI_NANDRA117_Data_Pos (0) /*!< NFI_T::NANDRA117: Data Position */ +#define NFI_NANDRA117_Data_Msk (0xfffffffful << NFI_NANDRA117_Data_Pos) /*!< NFI_T::NANDRA117: Data Mask */ + +/**@}*/ /* NFI_CONST */ +/**@}*/ /* end of NFI register group */ +/**@}*/ /* end of REGISTER group */ + +#if defined ( __CC_ARM ) + #pragma no_anon_unions +#endif + +#endif /* __NFI_REG_H__ */ diff --git a/bsp/nuvoton/libraries/ma35/Device/Nuvoton/MA35D1/Include/otp_reg.h b/bsp/nuvoton/libraries/ma35/Device/Nuvoton/MA35D1/Include/otp_reg.h new file mode 100644 index 0000000000..d71d6f1b81 --- /dev/null +++ b/bsp/nuvoton/libraries/ma35/Device/Nuvoton/MA35D1/Include/otp_reg.h @@ -0,0 +1,346 @@ +/**************************************************************************//** +* @file otp_reg.h +* @brief OTP driver header file +* +* SPDX-License-Identifier: Apache-2.0 +* @copyright (C) 2021 Nuvoton Technology Corp. All rights reserved. +*****************************************************************************/ + +#ifndef __OTP_REG_H__ +#define __OTP_REG_H__ + +#if defined ( __CC_ARM ) + #pragma anon_unions +#endif + +/** + @addtogroup REGISTER Control Register + @{ +*/ + +/** + @addtogroup OTP One-Time Programming Controller(OTP) + Memory Mapped Structure for OTP Controller +@{ */ + +typedef struct +{ + + + /** + * @var OTP_T::CTL + * Offset: 0x00 OTP Control Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[0] |START |OTP Start Control Bit + * | | |0 = No operation. + * | | |1 = Start the operation. + * |[7:4] |CMD |OTP Command Selection Bits + * | | |0x0 = Read command. + * | | |0x1 = Program command. + * | | |0x2 = Read only lock command. + * | | |0x3 = Fault Tolerance Mechanism command. + * | | |0x7 = Read checker command. + * | | |0xB = Read company ID + * | | |0xC = Read device ID + * | | |0xD = Read unique ID + * | | |Others = reserved. + * @var OTP_T::STS + * Offset: 0x04 OTP Status Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[0] |BUSY |OTP Busy Flag (Read Only) + * | | |0 = OTP is idle or finished. + * | | |1 = OTP is busy. + * |[1] |PFF |OTP Program Fail Flag (Write 1 to Clear) + * | | |This bit is cleared by writing 1 and it has no effect by writing 0. + * | | |0 = No OTP programming operation failed. + * | | |1 = OTP programming operation is failed. + * |[2] |ADDRFF |OTP Address Fail Flag (Write 1 to Clear) + * | | |This bit is cleared by writing 1 and it has no effect by writing 0. + * | | |0 = OTP Address is legal. + * | | |1 = OTP Address is illegal. + * |[3] |FTMFF |OTP Fault Tolerance Mechanism Fail Flag (Write 1 to Clear) + * | | |This bit is set after Fault Tolerance Mechanism command is triggered and address is assigned to a block without available spare memory. + * | | |This bit is cleared by writing 1 and it has no effect by writing 0. + * | | |0 = No OTP fault tolerance mechanism failed. + * | | |1 = OTP fault tolerance mechanism failed. + * |[4] |CMDFF |OTP Command Fail Flag (Write 1 to Clear) + * | | |This bit is set after program command or Fault Tolerance Mechanism command is triggered and address is assigned a locked block. + * | | |This bit is cleared by writing 1 and it has no effect by writing 0. + * | | |0 = No OTP command failed. + * | | |1 = OTP command is failed. + * @var OTP_T::ADDR + * Offset: 0x08 OTP Address Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[11:0] |ADDR |OTP Address + * | | |OTP_ADDR register is byte addressable. + * | | |If OTP_ADDR is written to illegal region and START(OTP_CTL[0]) bit is triggered, ADDRFF(OTP_STS[2]) will be set and this operation will not be executed. + * @var OTP_T::DATA + * Offset: 0x0C OTP Data Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[31:0] |DATA |OTP Data + * | | |Writing data to OTP_DATA register before OTP program operation. + * | | |Reading data from OTP_DATA register after OTP read operation. + * | | |Writing password, 0x55aa_92d6, before OTP read only lock operation or OTP Fault Tolerance Mechanism operation. + * @var OTP_T::USMSTS0 + * Offset: 0x10 OTP Unused Spare Memory 0 Status Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[3:2] |BLK1 |Block 1 Unused Spare Memory + * | | |Maximum unused spare memory is 2. + * |[5:4] |BLK2 |Block 2 Unused Spare Memory + * | | |Maximum unused spare memory is 0. + * |[7:6] |BLK3 |Block 3 Unused Spare Memory + * | | |Maximum unused spare memory is 2. + * |[9:8] |BLK4 |Block 4 Unused Spare Memory + * | | |Maximum unused spare memory is 2. + * |[11:10] |BLK5 |Block 5 Unused Spare Memory + * | | |Maximum unused spare memory is 0. + * |[13:12] |BLK6 |Block 6 Unused Spare Memory + * | | |Maximum unused spare memory is 0. + * |[15:14] |BLK7 |Block 7 Unused Spare Memory + * | | |Maximum unused spare memory is 0. + * |[17:16] |BLK8 |Block 8 Unused Spare Memory + * | | |Maximum unused spare memory is 1. + * |[19:18] |BLK9 |Block 9 Unused Spare Memory + * | | |Maximum unused spare memory is 1. + * |[21:20] |BLK10 |Block 10 Unused Spare Memory + * | | |Maximum unused spare memory is 1. + * |[23:22] |BLK11 |Block 11 Unused Spare Memory + * | | |Maximum unused spare memory is 1. + * |[25:24] |BLK12 |Block 12 Unused Spare Memory + * | | |Maximum unused spare memory is 1. + * |[27:26] |BLK13 |Block 13 Unused Spare Memory + * | | |Maximum unused spare memory is 1. + * |[29:28] |BLK14 |Block 14 Unused Spare Memory + * | | |Maximum unused spare memory is 1. + * |[31:30] |BLK15 |Block 15 Unused Spare Memory + * | | |Maximum unused spare memory is 1. + * @var OTP_T::USMSTS1 + * Offset: 0x14 OTP Unused Spare Memory 1 Status Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[1:0] |BLK16 |Block 16 Unused Spare Memory + * | | |Maximum unused spare memory is 1. + * @var OTP_T::OTP_CTL + * Offset: 0x800 Non-secure OTP Control Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[0] |START |OTP Start Control Bit + * | | |0 = No operation. + * | | |1 = Start the operation. + * |[6:4] |CMD |OTP Command Selection Bits + * | | |0x0 = Read command. + * | | |0x1 = Program command. + * | | |0x2 = Read only lock command. + * | | |0x3 = Fault Tolerance Mechanism command. + * | | |0x7 = Read checker command. + * | | |0xB = Read company ID + * | | |0xC = Read device ID + * | | |0xD = Read unique ID + * | | |Others = reserved. + * @var OTP_T::OTP_STS + * Offset: 0x804 Non-secure OTP Status Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[0] |BUSY |OTP Busy Flag (Read Only) + * | | |0 = OTP is idle or finished. + * | | |1 = OTP is busy. + * |[1] |PFF |OTP Program Fail Flag (Write 1 to Clear) + * | | |This bit is cleared by writing 1 and it has no effect by writing 0. + * | | |0 = No OTP programming operation failed. + * | | |1 = OTP programming operation failed. + * |[2] |ADDRFF |OTP Address Fail Flag (Write 1 to Clear) + * | | |This bit is cleared by writing 1 and it has no effect by writing 0. + * | | |0 = OTP Address is legal. + * | | |1 = OTP Address is illegal. + * |[3] |FTMFF |OTP Fault Tolerance Mechanism Fail Flag (Write 1 to Clear) + * | | |This bit is set after Fault Tolerance Mechanism command is triggered and address is assigned to a block without available spare memory. + * | | |This bit is cleared by writing 1 and it has no effect by writing 0. + * | | |0 = No OTP fault tolerance mechanism failed. + * | | |1 = OTP fault tolerance mechanism is failed. + * |[4] |CMDFF |OTP Command Fail Flag (Write 1 to Clear) + * | | |This bit is set after program command or Fault Tolerance Mechanism command is triggered and address is assigned to a locked block. + * | | |This bit is cleared by writing 1 and it has no effect by writing 0. + * | | |0 = No OTP command failed. + * | | |1 = OTP command failed. + * @var OTP_T::OTP_ADDR + * Offset: 0x808 Non-secure OTP Address Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[11:0] |ADDR |OTP Address + * | | |OTP_ADDR register is byte addressable. + * | | |If OTP_ADDR is written to illegal region and START(OTP_CTL[0]) bit is triggered, ADDRFF(OTP_STS[2]) will be set and this operation will not be executed. + * @var OTP_T::OTP_DATA + * Offset: 0x80C Non-secure OTP Data Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[31:0] |DATA |OTP Data + * | | |Writing data to OTP_DATA register before OTP program operation. + * | | |Reading data from OTP_DATA register after OTP read operation. + * | | |Writing password, 0x55aa_92d6, before OTP read only lock operation or OTP Fault Tolerance Mechanism operation. + * @var OTP_T::OTP_USMSTS + * Offset: 0x810 Non-secure OTP Unused Spare Memory Status Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[7:6] |BLK3 |Block 3 Unused Spare Memory + * | | |Maximum unused spare memory is 2. + * |[9:8] |BLK4 |Block 4 Unused Spare Memory + * | | |Maximum unused spare memory is 2. + * |[15:14] |BLK7 |Block 7 Unused Spare Memory + * | | |Maximum unused spare memory is 0. + */ + __IO uint32_t CTL; /*!< [0x0000] OTP Control Register */ + __IO uint32_t STS; /*!< [0x0004] OTP Status Register */ + __IO uint32_t ADDR; /*!< [0x0008] OTP Address Register */ + __IO uint32_t DATA; /*!< [0x000c] OTP Data Register */ + __I uint32_t USMSTS0; /*!< [0x0010] OTP Unused Spare Memory 0 Status Register */ + __I uint32_t USMSTS1; /*!< [0x0014] OTP Unused Spare Memory 1 Status Register */ + __I uint32_t RESERVE0[506]; + __IO uint32_t OTP_CTL; /*!< [0x0800] Non-secure OTP Control Register */ + __IO uint32_t OTP_STS; /*!< [0x0804] Non-secure OTP Status Register */ + __IO uint32_t OTP_ADDR; /*!< [0x0808] Non-secure OTP Address Register */ + __IO uint32_t OTP_DATA; /*!< [0x080c] Non-secure OTP Data Register */ + __I uint32_t OTP_USMSTS; /*!< [0x0810] Non-secure OTP Unused Spare Memory Status Register */ + +} OTP_T; + +/** + @addtogroup OTP_CONST OTP Bit Field Definition + Constant Definitions for OTP Controller +@{ */ + +#define OTP_CTL_START_Pos (0) /*!< OTP_T::CTL: START Position */ +#define OTP_CTL_START_Msk (0x1ul << OTP_CTL_START_Pos) /*!< OTP_T::CTL: START Mask */ + +#define OTP_CTL_CMD_Pos (4) /*!< OTP_T::CTL: CMD Position */ +#define OTP_CTL_CMD_Msk (0xful << OTP_CTL_CMD_Pos) /*!< OTP_T::CTL: CMD Mask */ + +#define OTP_STS_BUSY_Pos (0) /*!< OTP_T::STS: BUSY Position */ +#define OTP_STS_BUSY_Msk (0x1ul << OTP_STS_BUSY_Pos) /*!< OTP_T::STS: BUSY Mask */ + +#define OTP_STS_PFF_Pos (1) /*!< OTP_T::STS: PFF Position */ +#define OTP_STS_PFF_Msk (0x1ul << OTP_STS_PFF_Pos) /*!< OTP_T::STS: PFF Mask */ + +#define OTP_STS_ADDRFF_Pos (2) /*!< OTP_T::STS: ADDRFF Position */ +#define OTP_STS_ADDRFF_Msk (0x1ul << OTP_STS_ADDRFF_Pos) /*!< OTP_T::STS: ADDRFF Mask */ + +#define OTP_STS_FTMFF_Pos (3) /*!< OTP_T::STS: FTMFF Position */ +#define OTP_STS_FTMFF_Msk (0x1ul << OTP_STS_FTMFF_Pos) /*!< OTP_T::STS: FTMFF Mask */ + +#define OTP_STS_CMDFF_Pos (4) /*!< OTP_T::STS: CMDFF Position */ +#define OTP_STS_CMDFF_Msk (0x1ul << OTP_STS_CMDFF_Pos) /*!< OTP_T::STS: CMDFF Mask */ + +#define OTP_ADDR_ADDR_Pos (0) /*!< OTP_T::ADDR: ADDR Position */ +#define OTP_ADDR_ADDR_Msk (0xffful << OTP_ADDR_ADDR_Pos) /*!< OTP_T::ADDR: ADDR Mask */ + +#define OTP_DATA_DATA_Pos (0) /*!< OTP_T::DATA: DATA Position */ +#define OTP_DATA_DATA_Msk (0xfffffffful << OTP_DATA_DATA_Pos) /*!< OTP_T::DATA: DATA Mask */ + +#define OTP_USMSTS0_BLK1_Pos (2) /*!< OTP_T::USMSTS0: BLK1 Position */ +#define OTP_USMSTS0_BLK1_Msk (0x3ul << OTP_USMSTS0_BLK1_Pos) /*!< OTP_T::USMSTS0: BLK1 Mask */ + +#define OTP_USMSTS0_BLK2_Pos (4) /*!< OTP_T::USMSTS0: BLK2 Position */ +#define OTP_USMSTS0_BLK2_Msk (0x3ul << OTP_USMSTS0_BLK2_Pos) /*!< OTP_T::USMSTS0: BLK2 Mask */ + +#define OTP_USMSTS0_BLK3_Pos (6) /*!< OTP_T::USMSTS0: BLK3 Position */ +#define OTP_USMSTS0_BLK3_Msk (0x3ul << OTP_USMSTS0_BLK3_Pos) /*!< OTP_T::USMSTS0: BLK3 Mask */ + +#define OTP_USMSTS0_BLK4_Pos (8) /*!< OTP_T::USMSTS0: BLK4 Position */ +#define OTP_USMSTS0_BLK4_Msk (0x3ul << OTP_USMSTS0_BLK4_Pos) /*!< OTP_T::USMSTS0: BLK4 Mask */ + +#define OTP_USMSTS0_BLK5_Pos (10) /*!< OTP_T::USMSTS0: BLK5 Position */ +#define OTP_USMSTS0_BLK5_Msk (0x3ul << OTP_USMSTS0_BLK5_Pos) /*!< OTP_T::USMSTS0: BLK5 Mask */ + +#define OTP_USMSTS0_BLK6_Pos (12) /*!< OTP_T::USMSTS0: BLK6 Position */ +#define OTP_USMSTS0_BLK6_Msk (0x3ul << OTP_USMSTS0_BLK6_Pos) /*!< OTP_T::USMSTS0: BLK6 Mask */ + +#define OTP_USMSTS0_BLK7_Pos (14) /*!< OTP_T::USMSTS0: BLK7 Position */ +#define OTP_USMSTS0_BLK7_Msk (0x3ul << OTP_USMSTS0_BLK7_Pos) /*!< OTP_T::USMSTS0: BLK7 Mask */ + +#define OTP_USMSTS0_BLK8_Pos (16) /*!< OTP_T::USMSTS0: BLK8 Position */ +#define OTP_USMSTS0_BLK8_Msk (0x3ul << OTP_USMSTS0_BLK8_Pos) /*!< OTP_T::USMSTS0: BLK8 Mask */ + +#define OTP_USMSTS0_BLK9_Pos (18) /*!< OTP_T::USMSTS0: BLK9 Position */ +#define OTP_USMSTS0_BLK9_Msk (0x3ul << OTP_USMSTS0_BLK9_Pos) /*!< OTP_T::USMSTS0: BLK9 Mask */ + +#define OTP_USMSTS0_BLK10_Pos (20) /*!< OTP_T::USMSTS0: BLK10 Position */ +#define OTP_USMSTS0_BLK10_Msk (0x3ul << OTP_USMSTS0_BLK10_Pos) /*!< OTP_T::USMSTS0: BLK10 Mask */ + +#define OTP_USMSTS0_BLK11_Pos (22) /*!< OTP_T::USMSTS0: BLK11 Position */ +#define OTP_USMSTS0_BLK11_Msk (0x3ul << OTP_USMSTS0_BLK11_Pos) /*!< OTP_T::USMSTS0: BLK11 Mask */ + +#define OTP_USMSTS0_BLK12_Pos (24) /*!< OTP_T::USMSTS0: BLK12 Position */ +#define OTP_USMSTS0_BLK12_Msk (0x3ul << OTP_USMSTS0_BLK12_Pos) /*!< OTP_T::USMSTS0: BLK12 Mask */ + +#define OTP_USMSTS0_BLK13_Pos (26) /*!< OTP_T::USMSTS0: BLK13 Position */ +#define OTP_USMSTS0_BLK13_Msk (0x3ul << OTP_USMSTS0_BLK13_Pos) /*!< OTP_T::USMSTS0: BLK13 Mask */ + +#define OTP_USMSTS0_BLK14_Pos (28) /*!< OTP_T::USMSTS0: BLK14 Position */ +#define OTP_USMSTS0_BLK14_Msk (0x3ul << OTP_USMSTS0_BLK14_Pos) /*!< OTP_T::USMSTS0: BLK14 Mask */ + +#define OTP_USMSTS0_BLK15_Pos (30) /*!< OTP_T::USMSTS0: BLK15 Position */ +#define OTP_USMSTS0_BLK15_Msk (0x3ul << OTP_USMSTS0_BLK15_Pos) /*!< OTP_T::USMSTS0: BLK15 Mask */ + +#define OTP_USMSTS1_BLK16_Pos (0) /*!< OTP_T::USMSTS1: BLK16 Position */ +#define OTP_USMSTS1_BLK16_Msk (0x3ul << OTP_USMSTS1_BLK16_Pos) /*!< OTP_T::USMSTS1: BLK16 Mask */ + +#define OTP_OTP_CTL_START_Pos (0) /*!< OTP_T::OTP_CTL: START Position */ +#define OTP_OTP_CTL_START_Msk (0x1ul << OTP_OTP_CTL_START_Pos) /*!< OTP_T::OTP_CTL: START Mask */ + +#define OTP_OTP_CTL_CMD_Pos (4) /*!< OTP_T::OTP_CTL: CMD Position */ +#define OTP_OTP_CTL_CMD_Msk (0x7ul << OTP_OTP_CTL_CMD_Pos) /*!< OTP_T::OTP_CTL: CMD Mask */ + +#define OTP_OTP_STS_BUSY_Pos (0) /*!< OTP_T::OTP_STS: BUSY Position */ +#define OTP_OTP_STS_BUSY_Msk (0x1ul << OTP_OTP_STS_BUSY_Pos) /*!< OTP_T::OTP_STS: BUSY Mask */ + +#define OTP_OTP_STS_PFF_Pos (1) /*!< OTP_T::OTP_STS: PFF Position */ +#define OTP_OTP_STS_PFF_Msk (0x1ul << OTP_OTP_STS_PFF_Pos) /*!< OTP_T::OTP_STS: PFF Mask */ + +#define OTP_OTP_STS_ADDRFF_Pos (2) /*!< OTP_T::OTP_STS: ADDRFF Position */ +#define OTP_OTP_STS_ADDRFF_Msk (0x1ul << OTP_OTP_STS_ADDRFF_Pos) /*!< OTP_T::OTP_STS: ADDRFF Mask */ + +#define OTP_OTP_STS_FTMFF_Pos (3) /*!< OTP_T::OTP_STS: FTMFF Position */ +#define OTP_OTP_STS_FTMFF_Msk (0x1ul << OTP_OTP_STS_FTMFF_Pos) /*!< OTP_T::OTP_STS: FTMFF Mask */ + +#define OTP_OTP_STS_CMDFF_Pos (4) /*!< OTP_T::OTP_STS: CMDFF Position */ +#define OTP_OTP_STS_CMDFF_Msk (0x1ul << OTP_OTP_STS_CMDFF_Pos) /*!< OTP_T::OTP_STS: CMDFF Mask */ + +#define OTP_OTP_ADDR_ADDR_Pos (0) /*!< OTP_T::OTP_ADDR: ADDR Position */ +#define OTP_OTP_ADDR_ADDR_Msk (0xffful << OTP_OTP_ADDR_ADDR_Pos) /*!< OTP_T::OTP_ADDR: ADDR Mask */ + +#define OTP_OTP_DATA_DATA_Pos (0) /*!< OTP_T::OTP_DATA: DATA Position */ +#define OTP_OTP_DATA_DATA_Msk (0xfffffffful << OTP_OTP_DATA_DATA_Pos) /*!< OTP_T::OTP_DATA: DATA Mask */ + +#define OTP_OTP_USMSTS_BLK3_Pos (6) /*!< OTP_T::OTP_USMSTS: BLK3 Position */ +#define OTP_OTP_USMSTS_BLK3_Msk (0x3ul << OTP_OTP_USMSTS_BLK3_Pos) /*!< OTP_T::OTP_USMSTS: BLK3 Mask */ + +#define OTP_OTP_USMSTS_BLK4_Pos (8) /*!< OTP_T::OTP_USMSTS: BLK4 Position */ +#define OTP_OTP_USMSTS_BLK4_Msk (0x3ul << OTP_OTP_USMSTS_BLK4_Pos) /*!< OTP_T::OTP_USMSTS: BLK4 Mask */ + +#define OTP_OTP_USMSTS_BLK7_Pos (14) /*!< OTP_T::OTP_USMSTS: BLK7 Position */ +#define OTP_OTP_USMSTS_BLK7_Msk (0x3ul << OTP_OTP_USMSTS_BLK7_Pos) /*!< OTP_T::OTP_USMSTS: BLK7 Mask */ + +/**@}*/ /* OTP_CONST */ +/**@}*/ /* end of OTP register group */ +/**@}*/ /* end of REGISTER group */ + +#if defined ( __CC_ARM ) + #pragma no_anon_unions +#endif + +#endif //__OTP_REG_H__ diff --git a/bsp/nuvoton/libraries/ma35/Device/Nuvoton/MA35D1/Include/pdma_reg.h b/bsp/nuvoton/libraries/ma35/Device/Nuvoton/MA35D1/Include/pdma_reg.h new file mode 100644 index 0000000000..587c0403a5 --- /dev/null +++ b/bsp/nuvoton/libraries/ma35/Device/Nuvoton/MA35D1/Include/pdma_reg.h @@ -0,0 +1,1020 @@ +/**************************************************************************//** + * @file pdma_reg.h + * @brief PDMA register definition header file + * + * SPDX-License-Identifier: Apache-2.0 + * @copyright (C) 2020 Nuvoton Technology Corp. All rights reserved. + *****************************************************************************/ +#ifndef __PDMA_REG_H__ +#define __PDMA_REG_H__ + +#if defined ( __CC_ARM ) + #pragma anon_unions +#endif + +#define PDMA_CH_MAX 10UL /*!< Specify Maximum Channels of PDMA \hideinitializer */ +#define PDMA_CH_Msk ((1ul<= 1,. + * | | |If MCLKDIV = 0,. + * | | |where + * | | |is the frequency of I2S peripheral clock source, which is defined in the clock control register CLK_CLKSEL4 + * | | |In general, the master clock rate is 256 times sampling clock rate. + * |[17:8] |BCLKDIV |Bit Clock Divider + * | | |The I2S controller will generate bit clock in Master mode + * | | |The clock frequency of bit clock, fBCLK, is determined by the following expression: + * | | |where + * | | |is the frequency of I2S peripheral clock source, which is defined in the clock control register CLK_CLKSEL4. + * | | |In I2S Slave mode, this field is used to define the frequency of peripheral clock and it's determined by . + * | | |The peripheral clock frequency in I2S Slave mode must be equal to or faster than 6 times of input bit clock. + * | | |Note: The time interval must be larger than or equal 5 peripheral clock cycles between releasing SPI IP software reset and setting this clock divider register. + * |[24] |I2SMODE |I2S Clock Divider Number Selection for I2S Mode and SPI Mode + * | | |User sets I2SMODE to set frequency of peripheral clock of I2S mode or SPI mode when BCLKDIV (SPIx_I2SCLK[17:8]) or DIVIDER (SPIx_CLKDIV[8:0]) are set. + * | | |User needs to set I2SMODE before I2SEN (SPIx_I2SCTL[0]) or SPIEN (SPIx_CTL[0]) is enabled. + * | | |0 = The frequency of peripheral clock set to SPI mode. + * | | |1 = The frequency of peripheral clock set to I2S mode. + * |[25] |I2SSLAVE |I2S Clock Divider Number Selection for I2S Slave Mode and I2S Master Mode + * | | |User sets I2SSLAVE to set frequency of peripheral clock of I2S master mode and I2S slave mode when BCLKDIV (SPIx_I2SCLK[17:8]) is set. + * | | |User needs to set I2SSLAVE before I2SEN (SPIx_I2SCTL[0]) is enabled. + * | | |0 = The frequency of peripheral clock set to I2S master mode. + * | | |1 = The frequency of peripheral clock set to I2S slave mode. + * @var SPI_T::I2SSTS + * Offset: 0x68 I2S Status Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[4] |RIGHT |Right Channel (Read Only) + * | | |This bit indicates the current transmit data is belong to which channel. + * | | |0 = Left channel. + * | | |1 = Right channel. + * |[8] |RXEMPTY |Receive FIFO Buffer Empty Indicator (Read Only) + * | | |0 = Receive FIFO buffer is not empty. + * | | |1 = Receive FIFO buffer is empty. + * |[9] |RXFULL |Receive FIFO Buffer Full Indicator (Read Only) + * | | |0 = Receive FIFO buffer is not full. + * | | |1 = Receive FIFO buffer is full. + * |[10] |RXTHIF |Receive FIFO Threshold Interrupt Flag (Read Only) + * | | |0 = The valid data count within the receive FIFO buffer is smaller than or equal to the setting value of RXTH. + * | | |1 = The valid data count within the receive FIFO buffer is larger than the setting value of RXTH. + * | | |Note: If RXTHIEN = 1 and RXTHIF = 1, the SPI/I2S controller will generate a SPI interrupt request. + * |[11] |RXOVIF |Receive FIFO Overrun Interrupt Flag + * | | |When the receive FIFO buffer is full, the follow-up data will be dropped and this bit will be set to 1. + * | | |Note: This bit will be cleared by writing 1 to it. + * |[12] |RXTOIF |Receive Time-out Interrupt Flag + * | | |0 = No receive FIFO time-out event. + * | | |1 = Receive FIFO buffer is not empty and no read operation on receive FIFO buffer over 64 SPI peripheral clock period in Master mode or over 576 SPI peripheral clock period in Slave mode + * | | |When the received FIFO buffer is read by software, the time-out status will be cleared automatically. + * | | |Note: This bit will be cleared by writing 1 to it. + * |[15] |I2SENSTS |I2S Enable Status (Read Only) + * | | |0 = The SPI/I2S control logic Disabled. + * | | |1 = The SPI/I2S control logic Enabled. + * | | |Note: The SPI peripheral clock is asynchronous with the system clock + * | | |In order to make sure the SPI/I2S control logic is disabled, this bit indicates the real status of SPI/I2S control logic for user. + * |[16] |TXEMPTY |Transmit FIFO Buffer Empty Indicator (Read Only) + * | | |0 = Transmit FIFO buffer is not empty. + * | | |1 = Transmit FIFO buffer is empty. + * |[17] |TXFULL |Transmit FIFO Buffer Full Indicator (Read Only) + * | | |0 = Transmit FIFO buffer is not full. + * | | |1 = Transmit FIFO buffer is full. + * |[18] |TXTHIF |Transmit FIFO Threshold Interrupt Flag (Read Only) + * | | |0 = The valid data count within the transmit FIFO buffer is larger than the setting value of TXTH. + * | | |1 = The valid data count within the transmit FIFO buffer is less than or equal to the setting value of TXTH. + * | | |Note: If TXTHIEN = 1 and TXTHIF = 1, the SPI/I2S controller will generate a SPI interrupt request. + * |[19] |TXUFIF |Transmit FIFO Underflow Interrupt Flag + * | | |When the transmit FIFO buffer is empty and there is no datum written into the FIFO buffer, if there is more bus clock input, this bit will be set to 1. + * | | |Note: This bit will be cleared by writing 1 to it. + * |[20] |RZCIF |Right Channel Zero Cross Interrupt Flag + * | | |0 = No zero cross event occurred on right channel. + * | | |1 = Zero cross event occurred on right channel. + * |[21] |LZCIF |Left Channel Zero Cross Interrupt Flag + * | | |0 = No zero cross event occurred on left channel. + * | | |1 = Zero cross event occurred on left channel. + * |[22] |SLVERRIF |Bit Number Error Interrupt Flag for Slave Mode + * | | |0 = No bit number error event occurred. + * | | |1 = Bit number error event occurred. + * | | |Note: This bit will be cleared by writing 1 to it. + * |[23] |TXRXRST |TX or RX Reset Status (Read Only) + * | | |0 = The reset function of TXRST or RXRST is done. + * | | |1 = Doing the reset function of TXRST or RXRST. + * | | |Note: Both the reset operations of TXRST and RXRST need 3 system clock cycles + 2 peripheral clock cycles + * | | |User can check the status of this bit to monitor the reset function is doing or done. + * |[26:24] |RXCNT |Receive FIFO Data Count (Read Only) + * | | |This bit field indicates the valid data count of receive FIFO buffer. + * |[30:28] |TXCNT |Transmit FIFO Data Count (Read Only) + * | | |This bit field indicates the valid data count of transmit FIFO buffer. + */ + __IO uint32_t CTL; /*!< [0x0000] SPI Control Register */ + __IO uint32_t CLKDIV; /*!< [0x0004] SPI Clock Divider Register */ + __IO uint32_t SSCTL; /*!< [0x0008] SPI Slave Select Control Register */ + __IO uint32_t PDMACTL; /*!< [0x000c] SPI PDMA Control Register */ + __IO uint32_t FIFOCTL; /*!< [0x0010] SPI FIFO Control Register */ + __IO uint32_t STATUS; /*!< [0x0014] SPI Status Register */ + __I uint32_t STATUS2; /*!< [0x0018] SPI Status2 Register */ + __I uint32_t RESERVE0[1]; + __O uint32_t TX; /*!< [0x0020] SPI Data Transmit Register */ + __I uint32_t RESERVE1[3]; + __I uint32_t RX; /*!< [0x0030] SPI Data Receive Register */ + __I uint32_t RESERVE2[5]; /*!< [0x0034] Reserved */ + __IO uint32_t INTERNAL; /*!< [0x0048] SPI Internal Control Register */ + __I uint32_t RESERVE3; /*!< [0x004C] Reserved */ + __I uint32_t VER_NUM; /*!< [0x0050] SPI Version Number Register */ + __I uint32_t RESERVE4[3]; /*!< [0x0054] Reserved */ + __IO uint32_t I2SCTL; /*!< [0x0060] I2S Control Register */ + __IO uint32_t I2SCLK; /*!< [0x0064] I2S Clock Divider Control Register */ + __IO uint32_t I2SSTS; /*!< [0x0068] I2S Status Register */ + +} SPI_T; + +/** + @addtogroup SPI_CONST SPI Bit Field Definition + Constant Definitions for SPI Controller +@{ */ + +#define SPI_CTL_SPIEN_Pos (0) /*!< SPI_T::CTL: SPIEN Position */ +#define SPI_CTL_SPIEN_Msk (0x1ul << SPI_CTL_SPIEN_Pos) /*!< SPI_T::CTL: SPIEN Mask */ + +#define SPI_CTL_RXNEG_Pos (1) /*!< SPI_T::CTL: RXNEG Position */ +#define SPI_CTL_RXNEG_Msk (0x1ul << SPI_CTL_RXNEG_Pos) /*!< SPI_T::CTL: RXNEG Mask */ + +#define SPI_CTL_TXNEG_Pos (2) /*!< SPI_T::CTL: TXNEG Position */ +#define SPI_CTL_TXNEG_Msk (0x1ul << SPI_CTL_TXNEG_Pos) /*!< SPI_T::CTL: TXNEG Mask */ + +#define SPI_CTL_CLKPOL_Pos (3) /*!< SPI_T::CTL: CLKPOL Position */ +#define SPI_CTL_CLKPOL_Msk (0x1ul << SPI_CTL_CLKPOL_Pos) /*!< SPI_T::CTL: CLKPOL Mask */ + +#define SPI_CTL_SUSPITV_Pos (4) /*!< SPI_T::CTL: SUSPITV Position */ +#define SPI_CTL_SUSPITV_Msk (0xful << SPI_CTL_SUSPITV_Pos) /*!< SPI_T::CTL: SUSPITV Mask */ + +#define SPI_CTL_DWIDTH_Pos (8) /*!< SPI_T::CTL: DWIDTH Position */ +#define SPI_CTL_DWIDTH_Msk (0x1ful << SPI_CTL_DWIDTH_Pos) /*!< SPI_T::CTL: DWIDTH Mask */ + +#define SPI_CTL_LSB_Pos (13) /*!< SPI_T::CTL: LSB Position */ +#define SPI_CTL_LSB_Msk (0x1ul << SPI_CTL_LSB_Pos) /*!< SPI_T::CTL: LSB Mask */ + +#define SPI_CTL_HALFDPX_Pos (14) /*!< SPI_T::CTL: HALFDPX Position */ +#define SPI_CTL_HALFDPX_Msk (0x1ul << SPI_CTL_HALFDPX_Pos) /*!< SPI_T::CTL: HALFDPX Mask */ + +#define SPI_CTL_RXONLY_Pos (15) /*!< SPI_T::CTL: RXONLY Position */ +#define SPI_CTL_RXONLY_Msk (0x1ul << SPI_CTL_RXONLY_Pos) /*!< SPI_T::CTL: RXONLY Mask */ + +#define SPI_CTL_UNITIEN_Pos (17) /*!< SPI_T::CTL: UNITIEN Position */ +#define SPI_CTL_UNITIEN_Msk (0x1ul << SPI_CTL_UNITIEN_Pos) /*!< SPI_T::CTL: UNITIEN Mask */ + +#define SPI_CTL_SLAVE_Pos (18) /*!< SPI_T::CTL: SLAVE Position */ +#define SPI_CTL_SLAVE_Msk (0x1ul << SPI_CTL_SLAVE_Pos) /*!< SPI_T::CTL: SLAVE Mask */ + +#define SPI_CTL_REORDER_Pos (19) /*!< SPI_T::CTL: REORDER Position */ +#define SPI_CTL_REORDER_Msk (0x1ul << SPI_CTL_REORDER_Pos) /*!< SPI_T::CTL: REORDER Mask */ + +#define SPI_CTL_DATDIR_Pos (20) /*!< SPI_T::CTL: DATDIR Position */ +#define SPI_CTL_DATDIR_Msk (0x1ul << SPI_CTL_DATDIR_Pos) /*!< SPI_T::CTL: DATDIR Mask */ + +#define SPI_CLKDIV_DIVIDER_Pos (0) /*!< SPI_T::CLKDIV: DIVIDER Position */ +#define SPI_CLKDIV_DIVIDER_Msk (0x1fful << SPI_CLKDIV_DIVIDER_Pos) /*!< SPI_T::CLKDIV: DIVIDER Mask */ + +#define SPI_SSCTL_SS_Pos (0) /*!< SPI_T::SSCTL: SS Position */ +#define SPI_SSCTL_SS_Msk (0x1ul << SPI_SSCTL_SS_Pos) /*!< SPI_T::SSCTL: SS Mask */ + +#define SPI_SSCTL_SS0_Pos (0) /*!< SPI_T::SSCTL: SS0 Position */ +#define SPI_SSCTL_SS0_Msk (0x1ul << SPI_SSCTL_SS0_Pos) /*!< SPI_T::SSCTL: SS0 Mask */ + +#define SPI_SSCTL_SS1_Pos (1) /*!< SPI_T::SSCTL: SS1 Position */ +#define SPI_SSCTL_SS1_Msk (0x1ul << SPI_SSCTL_SS1_Pos) /*!< SPI_T::SSCTL: SS1 Mask */ + +#define SPI_SSCTL_SSACTPOL_Pos (2) /*!< SPI_T::SSCTL: SSACTPOL Position */ +#define SPI_SSCTL_SSACTPOL_Msk (0x1ul << SPI_SSCTL_SSACTPOL_Pos) /*!< SPI_T::SSCTL: SSACTPOL Mask */ + +#define SPI_SSCTL_AUTOSS_Pos (3) /*!< SPI_T::SSCTL: AUTOSS Position */ +#define SPI_SSCTL_AUTOSS_Msk (0x1ul << SPI_SSCTL_AUTOSS_Pos) /*!< SPI_T::SSCTL: AUTOSS Mask */ + +#define SPI_SSCTL_SLV3WIRE_Pos (4) /*!< SPI_T::SSCTL: SLV3WIRE Position */ +#define SPI_SSCTL_SLV3WIRE_Msk (0x1ul << SPI_SSCTL_SLV3WIRE_Pos) /*!< SPI_T::SSCTL: SLV3WIRE Mask */ + +#define SPI_SSCTL_SLVBEIEN_Pos (8) /*!< SPI_T::SSCTL: SLVBEIEN Position */ +#define SPI_SSCTL_SLVBEIEN_Msk (0x1ul << SPI_SSCTL_SLVBEIEN_Pos) /*!< SPI_T::SSCTL: SLVBEIEN Mask */ + +#define SPI_SSCTL_SLVURIEN_Pos (9) /*!< SPI_T::SSCTL: SLVURIEN Position */ +#define SPI_SSCTL_SLVURIEN_Msk (0x1ul << SPI_SSCTL_SLVURIEN_Pos) /*!< SPI_T::SSCTL: SLVURIEN Mask */ + +#define SPI_SSCTL_SSACTIEN_Pos (12) /*!< SPI_T::SSCTL: SSACTIEN Position */ +#define SPI_SSCTL_SSACTIEN_Msk (0x1ul << SPI_SSCTL_SSACTIEN_Pos) /*!< SPI_T::SSCTL: SSACTIEN Mask */ + +#define SPI_SSCTL_SSINAIEN_Pos (13) /*!< SPI_T::SSCTL: SSINAIEN Position */ +#define SPI_SSCTL_SSINAIEN_Msk (0x1ul << SPI_SSCTL_SSINAIEN_Pos) /*!< SPI_T::SSCTL: SSINAIEN Mask */ + +#define SPI_PDMACTL_TXPDMAEN_Pos (0) /*!< SPI_T::PDMACTL: TXPDMAEN Position */ +#define SPI_PDMACTL_TXPDMAEN_Msk (0x1ul << SPI_PDMACTL_TXPDMAEN_Pos) /*!< SPI_T::PDMACTL: TXPDMAEN Mask */ + +#define SPI_PDMACTL_RXPDMAEN_Pos (1) /*!< SPI_T::PDMACTL: RXPDMAEN Position */ +#define SPI_PDMACTL_RXPDMAEN_Msk (0x1ul << SPI_PDMACTL_RXPDMAEN_Pos) /*!< SPI_T::PDMACTL: RXPDMAEN Mask */ + +#define SPI_PDMACTL_PDMARST_Pos (2) /*!< SPI_T::PDMACTL: PDMARST Position */ +#define SPI_PDMACTL_PDMARST_Msk (0x1ul << SPI_PDMACTL_PDMARST_Pos) /*!< SPI_T::PDMACTL: PDMARST Mask */ + +#define SPI_FIFOCTL_RXRST_Pos (0) /*!< SPI_T::FIFOCTL: RXRST Position */ +#define SPI_FIFOCTL_RXRST_Msk (0x1ul << SPI_FIFOCTL_RXRST_Pos) /*!< SPI_T::FIFOCTL: RXRST Mask */ + +#define SPI_FIFOCTL_TXRST_Pos (1) /*!< SPI_T::FIFOCTL: TXRST Position */ +#define SPI_FIFOCTL_TXRST_Msk (0x1ul << SPI_FIFOCTL_TXRST_Pos) /*!< SPI_T::FIFOCTL: TXRST Mask */ + +#define SPI_FIFOCTL_RXTHIEN_Pos (2) /*!< SPI_T::FIFOCTL: RXTHIEN Position */ +#define SPI_FIFOCTL_RXTHIEN_Msk (0x1ul << SPI_FIFOCTL_RXTHIEN_Pos) /*!< SPI_T::FIFOCTL: RXTHIEN Mask */ + +#define SPI_FIFOCTL_TXTHIEN_Pos (3) /*!< SPI_T::FIFOCTL: TXTHIEN Position */ +#define SPI_FIFOCTL_TXTHIEN_Msk (0x1ul << SPI_FIFOCTL_TXTHIEN_Pos) /*!< SPI_T::FIFOCTL: TXTHIEN Mask */ + +#define SPI_FIFOCTL_RXTOIEN_Pos (4) /*!< SPI_T::FIFOCTL: RXTOIEN Position */ +#define SPI_FIFOCTL_RXTOIEN_Msk (0x1ul << SPI_FIFOCTL_RXTOIEN_Pos) /*!< SPI_T::FIFOCTL: RXTOIEN Mask */ + +#define SPI_FIFOCTL_RXOVIEN_Pos (5) /*!< SPI_T::FIFOCTL: RXOVIEN Position */ +#define SPI_FIFOCTL_RXOVIEN_Msk (0x1ul << SPI_FIFOCTL_RXOVIEN_Pos) /*!< SPI_T::FIFOCTL: RXOVIEN Mask */ + +#define SPI_FIFOCTL_TXUFPOL_Pos (6) /*!< SPI_T::FIFOCTL: TXUFPOL Position */ +#define SPI_FIFOCTL_TXUFPOL_Msk (0x1ul << SPI_FIFOCTL_TXUFPOL_Pos) /*!< SPI_T::FIFOCTL: TXUFPOL Mask */ + +#define SPI_FIFOCTL_TXUFIEN_Pos (7) /*!< SPI_T::FIFOCTL: TXUFIEN Position */ +#define SPI_FIFOCTL_TXUFIEN_Msk (0x1ul << SPI_FIFOCTL_TXUFIEN_Pos) /*!< SPI_T::FIFOCTL: TXUFIEN Mask */ + +#define SPI_FIFOCTL_RXFBCLR_Pos (8) /*!< SPI_T::FIFOCTL: RXFBCLR Position */ +#define SPI_FIFOCTL_RXFBCLR_Msk (0x1ul << SPI_FIFOCTL_RXFBCLR_Pos) /*!< SPI_T::FIFOCTL: RXFBCLR Mask */ + +#define SPI_FIFOCTL_TXFBCLR_Pos (9) /*!< SPI_T::FIFOCTL: TXFBCLR Position */ +#define SPI_FIFOCTL_TXFBCLR_Msk (0x1ul << SPI_FIFOCTL_TXFBCLR_Pos) /*!< SPI_T::FIFOCTL: TXFBCLR Mask */ + +#define SPI_FIFOCTL_SLVBERX_Pos (10) /*!< SPI_T::FIFOCTL: SLVBERX Position */ +#define SPI_FIFOCTL_SLVBERX_Msk (0x1ul << SPI_FIFOCTL_SLVBERX_Pos) /*!< SPI_T::FIFOCTL: SLVBERX Mask */ + +#define SPI_FIFOCTL_RXTH_Pos (24) /*!< SPI_T::FIFOCTL: RXTH Position */ +#define SPI_FIFOCTL_RXTH_Msk (0x7ul << SPI_FIFOCTL_RXTH_Pos) /*!< SPI_T::FIFOCTL: RXTH Mask */ + +#define SPI_FIFOCTL_TXTH_Pos (28) /*!< SPI_T::FIFOCTL: TXTH Position */ +#define SPI_FIFOCTL_TXTH_Msk (0x7ul << SPI_FIFOCTL_TXTH_Pos) /*!< SPI_T::FIFOCTL: TXTH Mask */ + +#define SPI_STATUS_BUSY_Pos (0) /*!< SPI_T::STATUS: BUSY Position */ +#define SPI_STATUS_BUSY_Msk (0x1ul << SPI_STATUS_BUSY_Pos) /*!< SPI_T::STATUS: BUSY Mask */ + +#define SPI_STATUS_UNITIF_Pos (1) /*!< SPI_T::STATUS: UNITIF Position */ +#define SPI_STATUS_UNITIF_Msk (0x1ul << SPI_STATUS_UNITIF_Pos) /*!< SPI_T::STATUS: UNITIF Mask */ + +#define SPI_STATUS_SSACTIF_Pos (2) /*!< SPI_T::STATUS: SSACTIF Position */ +#define SPI_STATUS_SSACTIF_Msk (0x1ul << SPI_STATUS_SSACTIF_Pos) /*!< SPI_T::STATUS: SSACTIF Mask */ + +#define SPI_STATUS_SSINAIF_Pos (3) /*!< SPI_T::STATUS: SSINAIF Position */ +#define SPI_STATUS_SSINAIF_Msk (0x1ul << SPI_STATUS_SSINAIF_Pos) /*!< SPI_T::STATUS: SSINAIF Mask */ + +#define SPI_STATUS_SSLINE_Pos (4) /*!< SPI_T::STATUS: SSLINE Position */ +#define SPI_STATUS_SSLINE_Msk (0x1ul << SPI_STATUS_SSLINE_Pos) /*!< SPI_T::STATUS: SSLINE Mask */ + +#define SPI_STATUS_SLVBEIF_Pos (6) /*!< SPI_T::STATUS: SLVBEIF Position */ +#define SPI_STATUS_SLVBEIF_Msk (0x1ul << SPI_STATUS_SLVBEIF_Pos) /*!< SPI_T::STATUS: SLVBEIF Mask */ + +#define SPI_STATUS_SLVURIF_Pos (7) /*!< SPI_T::STATUS: SLVURIF Position */ +#define SPI_STATUS_SLVURIF_Msk (0x1ul << SPI_STATUS_SLVURIF_Pos) /*!< SPI_T::STATUS: SLVURIF Mask */ + +#define SPI_STATUS_RXEMPTY_Pos (8) /*!< SPI_T::STATUS: RXEMPTY Position */ +#define SPI_STATUS_RXEMPTY_Msk (0x1ul << SPI_STATUS_RXEMPTY_Pos) /*!< SPI_T::STATUS: RXEMPTY Mask */ + +#define SPI_STATUS_RXFULL_Pos (9) /*!< SPI_T::STATUS: RXFULL Position */ +#define SPI_STATUS_RXFULL_Msk (0x1ul << SPI_STATUS_RXFULL_Pos) /*!< SPI_T::STATUS: RXFULL Mask */ + +#define SPI_STATUS_RXTHIF_Pos (10) /*!< SPI_T::STATUS: RXTHIF Position */ +#define SPI_STATUS_RXTHIF_Msk (0x1ul << SPI_STATUS_RXTHIF_Pos) /*!< SPI_T::STATUS: RXTHIF Mask */ + +#define SPI_STATUS_RXOVIF_Pos (11) /*!< SPI_T::STATUS: RXOVIF Position */ +#define SPI_STATUS_RXOVIF_Msk (0x1ul << SPI_STATUS_RXOVIF_Pos) /*!< SPI_T::STATUS: RXOVIF Mask */ + +#define SPI_STATUS_RXTOIF_Pos (12) /*!< SPI_T::STATUS: RXTOIF Position */ +#define SPI_STATUS_RXTOIF_Msk (0x1ul << SPI_STATUS_RXTOIF_Pos) /*!< SPI_T::STATUS: RXTOIF Mask */ + +#define SPI_STATUS_SPIENSTS_Pos (15) /*!< SPI_T::STATUS: SPIENSTS Position */ +#define SPI_STATUS_SPIENSTS_Msk (0x1ul << SPI_STATUS_SPIENSTS_Pos) /*!< SPI_T::STATUS: SPIENSTS Mask */ + +#define SPI_STATUS_TXEMPTY_Pos (16) /*!< SPI_T::STATUS: TXEMPTY Position */ +#define SPI_STATUS_TXEMPTY_Msk (0x1ul << SPI_STATUS_TXEMPTY_Pos) /*!< SPI_T::STATUS: TXEMPTY Mask */ + +#define SPI_STATUS_TXFULL_Pos (17) /*!< SPI_T::STATUS: TXFULL Position */ +#define SPI_STATUS_TXFULL_Msk (0x1ul << SPI_STATUS_TXFULL_Pos) /*!< SPI_T::STATUS: TXFULL Mask */ + +#define SPI_STATUS_TXTHIF_Pos (18) /*!< SPI_T::STATUS: TXTHIF Position */ +#define SPI_STATUS_TXTHIF_Msk (0x1ul << SPI_STATUS_TXTHIF_Pos) /*!< SPI_T::STATUS: TXTHIF Mask */ + +#define SPI_STATUS_TXUFIF_Pos (19) /*!< SPI_T::STATUS: TXUFIF Position */ +#define SPI_STATUS_TXUFIF_Msk (0x1ul << SPI_STATUS_TXUFIF_Pos) /*!< SPI_T::STATUS: TXUFIF Mask */ + +#define SPI_STATUS_FIFOCLR_Pos (22) /*!< SPI_T::STATUS: FIFOCLR Position */ +#define SPI_STATUS_FIFOCLR_Msk (0x1ul << SPI_STATUS_FIFOCLR_Pos) /*!< SPI_T::STATUS: FIFOCLR Mask */ + +#define SPI_STATUS_TXRXRST_Pos (23) /*!< SPI_T::STATUS: TXRXRST Position */ +#define SPI_STATUS_TXRXRST_Msk (0x1ul << SPI_STATUS_TXRXRST_Pos) /*!< SPI_T::STATUS: TXRXRST Mask */ + +#define SPI_STATUS_RXCNT_Pos (24) /*!< SPI_T::STATUS: RXCNT Position */ +#define SPI_STATUS_RXCNT_Msk (0xful << SPI_STATUS_RXCNT_Pos) /*!< SPI_T::STATUS: RXCNT Mask */ + +#define SPI_STATUS_TXCNT_Pos (28) /*!< SPI_T::STATUS: TXCNT Position */ +#define SPI_STATUS_TXCNT_Msk (0xful << SPI_STATUS_TXCNT_Pos) /*!< SPI_T::STATUS: TXCNT Mask */ + +#define SPI_STATUS2_RXCPDMA_Pos (8) /*!< SPI_T::STATUS2: RXCPDMA Position */ +#define SPI_STATUS2_RXCPDMA_Msk (0x1ful << SPI_STATUS2_RXCPDMA_Pos) /*!< SPI_T::STATUS2: RXCPDMA Mask */ + +#define SPI_STATUS2_TXCPDMA_Pos (16) /*!< SPI_T::STATUS2: TXCPDMA Position */ +#define SPI_STATUS2_TXCPDMA_Msk (0x1ful << SPI_STATUS2_TXCPDMA_Pos) /*!< SPI_T::STATUS2: TXCPDMA Mask */ + +#define SPI_STATUS2_SLVBENUM_Pos (24) /*!< SPI_T::STATUS2: SLVBENUM Position */ +#define SPI_STATUS2_SLVBENUM_Msk (0x3ful << SPI_STATUS2_SLVBENUM_Pos) /*!< SPI_T::STATUS2: SLVBENUM Mask */ + +#define SPI_TX_TX_Pos (0) /*!< SPI_T::TX: TX Position */ +#define SPI_TX_TX_Msk (0xfffffffful << SPI_TX_TX_Pos) /*!< SPI_T::TX: TX Mask */ + +#define SPI_RX_RX_Pos (0) /*!< SPI_T::RX: RX Position */ +#define SPI_RX_RX_Msk (0xfffffffful << SPI_RX_RX_Pos) /*!< SPI_T::RX: RX Mask */ + +#define SPI_INTERNAL_MRXPHASE_Pos (12) /*!< SPI_T::INTERNAL: CLKDLY_SEL Position */ +#define SPI_INTERNAL_MRXPHASE_Msk (0xful << SPI_INTERNAL_MRXPHASE_Pos) /*!< SPI_T::INTERNAL: CLKDLY_SEL Mask */ + +#define SPI_I2SCTL_I2SEN_Pos (0) /*!< SPI_T::I2SCTL: I2SEN Position */ +#define SPI_I2SCTL_I2SEN_Msk (0x1ul << SPI_I2SCTL_I2SEN_Pos) /*!< SPI_T::I2SCTL: I2SEN Mask */ + +#define SPI_I2SCTL_TXEN_Pos (1) /*!< SPI_T::I2SCTL: TXEN Position */ +#define SPI_I2SCTL_TXEN_Msk (0x1ul << SPI_I2SCTL_TXEN_Pos) /*!< SPI_T::I2SCTL: TXEN Mask */ + +#define SPI_I2SCTL_RXEN_Pos (2) /*!< SPI_T::I2SCTL: RXEN Position */ +#define SPI_I2SCTL_RXEN_Msk (0x1ul << SPI_I2SCTL_RXEN_Pos) /*!< SPI_T::I2SCTL: RXEN Mask */ + +#define SPI_I2SCTL_MUTE_Pos (3) /*!< SPI_T::I2SCTL: MUTE Position */ +#define SPI_I2SCTL_MUTE_Msk (0x1ul << SPI_I2SCTL_MUTE_Pos) /*!< SPI_T::I2SCTL: MUTE Mask */ + +#define SPI_I2SCTL_WDWIDTH_Pos (4) /*!< SPI_T::I2SCTL: WDWIDTH Position */ +#define SPI_I2SCTL_WDWIDTH_Msk (0x3ul << SPI_I2SCTL_WDWIDTH_Pos) /*!< SPI_T::I2SCTL: WDWIDTH Mask */ + +#define SPI_I2SCTL_MONO_Pos (6) /*!< SPI_T::I2SCTL: MONO Position */ +#define SPI_I2SCTL_MONO_Msk (0x1ul << SPI_I2SCTL_MONO_Pos) /*!< SPI_T::I2SCTL: MONO Mask */ + +#define SPI_I2SCTL_ORDER_Pos (7) /*!< SPI_T::I2SCTL: ORDER Position */ +#define SPI_I2SCTL_ORDER_Msk (0x1ul << SPI_I2SCTL_ORDER_Pos) /*!< SPI_T::I2SCTL: ORDER Mask */ + +#define SPI_I2SCTL_SLAVE_Pos (8) /*!< SPI_T::I2SCTL: SLAVE Position */ +#define SPI_I2SCTL_SLAVE_Msk (0x1ul << SPI_I2SCTL_SLAVE_Pos) /*!< SPI_T::I2SCTL: SLAVE Mask */ + +#define SPI_I2SCTL_MCLKEN_Pos (15) /*!< SPI_T::I2SCTL: MCLKEN Position */ +#define SPI_I2SCTL_MCLKEN_Msk (0x1ul << SPI_I2SCTL_MCLKEN_Pos) /*!< SPI_T::I2SCTL: MCLKEN Mask */ + +#define SPI_I2SCTL_RZCEN_Pos (16) /*!< SPI_T::I2SCTL: RZCEN Position */ +#define SPI_I2SCTL_RZCEN_Msk (0x1ul << SPI_I2SCTL_RZCEN_Pos) /*!< SPI_T::I2SCTL: RZCEN Mask */ + +#define SPI_I2SCTL_LZCEN_Pos (17) /*!< SPI_T::I2SCTL: LZCEN Position */ +#define SPI_I2SCTL_LZCEN_Msk (0x1ul << SPI_I2SCTL_LZCEN_Pos) /*!< SPI_T::I2SCTL: LZCEN Mask */ + +#define SPI_I2SCTL_RXLCH_Pos (23) /*!< SPI_T::I2SCTL: RXLCH Position */ +#define SPI_I2SCTL_RXLCH_Msk (0x1ul << SPI_I2SCTL_RXLCH_Pos) /*!< SPI_T::I2SCTL: RXLCH Mask */ + +#define SPI_I2SCTL_RZCIEN_Pos (24) /*!< SPI_T::I2SCTL: RZCIEN Position */ +#define SPI_I2SCTL_RZCIEN_Msk (0x1ul << SPI_I2SCTL_RZCIEN_Pos) /*!< SPI_T::I2SCTL: RZCIEN Mask */ + +#define SPI_I2SCTL_LZCIEN_Pos (25) /*!< SPI_T::I2SCTL: LZCIEN Position */ +#define SPI_I2SCTL_LZCIEN_Msk (0x1ul << SPI_I2SCTL_LZCIEN_Pos) /*!< SPI_T::I2SCTL: LZCIEN Mask */ + +#define SPI_I2SCTL_FORMAT_Pos (28) /*!< SPI_T::I2SCTL: FORMAT Position */ +#define SPI_I2SCTL_FORMAT_Msk (0x3ul << SPI_I2SCTL_FORMAT_Pos) /*!< SPI_T::I2SCTL: FORMAT Mask */ + +#define SPI_I2SCTL_SLVERRIEN_Pos (31) /*!< SPI_T::I2SCTL: SLVERRIEN Position */ +#define SPI_I2SCTL_SLVERRIEN_Msk (0x1ul << SPI_I2SCTL_SLVERRIEN_Pos) /*!< SPI_T::I2SCTL: SLVERRIEN Mask */ + +#define SPI_I2SCLK_MCLKDIV_Pos (0) /*!< SPI_T::I2SCLK: MCLKDIV Position */ +#define SPI_I2SCLK_MCLKDIV_Msk (0x7ful << SPI_I2SCLK_MCLKDIV_Pos) /*!< SPI_T::I2SCLK: MCLKDIV Mask */ + +#define SPI_I2SCLK_BCLKDIV_Pos (8) /*!< SPI_T::I2SCLK: BCLKDIV Position */ +#define SPI_I2SCLK_BCLKDIV_Msk (0x3fful << SPI_I2SCLK_BCLKDIV_Pos) /*!< SPI_T::I2SCLK: BCLKDIV Mask */ + +#define SPI_I2SCLK_I2SMODE_Pos (24) /*!< SPI_T::I2SCLK: I2SMODE Position */ +#define SPI_I2SCLK_I2SMODE_Msk (0x1ul << SPI_I2SCLK_I2SMODE_Pos) /*!< SPI_T::I2SCLK: I2SMODE Mask */ + +#define SPI_I2SCLK_I2SSLAVE_Pos (25) /*!< SPI_T::I2SCLK: I2SSLAVE Position */ +#define SPI_I2SCLK_I2SSLAVE_Msk (0x1ul << SPI_I2SCLK_I2SSLAVE_Pos) /*!< SPI_T::I2SCLK: I2SSLAVE Mask */ + +#define SPI_I2SSTS_RIGHT_Pos (4) /*!< SPI_T::I2SSTS: RIGHT Position */ +#define SPI_I2SSTS_RIGHT_Msk (0x1ul << SPI_I2SSTS_RIGHT_Pos) /*!< SPI_T::I2SSTS: RIGHT Mask */ + +#define SPI_I2SSTS_RXEMPTY_Pos (8) /*!< SPI_T::I2SSTS: RXEMPTY Position */ +#define SPI_I2SSTS_RXEMPTY_Msk (0x1ul << SPI_I2SSTS_RXEMPTY_Pos) /*!< SPI_T::I2SSTS: RXEMPTY Mask */ + +#define SPI_I2SSTS_RXFULL_Pos (9) /*!< SPI_T::I2SSTS: RXFULL Position */ +#define SPI_I2SSTS_RXFULL_Msk (0x1ul << SPI_I2SSTS_RXFULL_Pos) /*!< SPI_T::I2SSTS: RXFULL Mask */ + +#define SPI_I2SSTS_RXTHIF_Pos (10) /*!< SPI_T::I2SSTS: RXTHIF Position */ +#define SPI_I2SSTS_RXTHIF_Msk (0x1ul << SPI_I2SSTS_RXTHIF_Pos) /*!< SPI_T::I2SSTS: RXTHIF Mask */ + +#define SPI_I2SSTS_RXOVIF_Pos (11) /*!< SPI_T::I2SSTS: RXOVIF Position */ +#define SPI_I2SSTS_RXOVIF_Msk (0x1ul << SPI_I2SSTS_RXOVIF_Pos) /*!< SPI_T::I2SSTS: RXOVIF Mask */ + +#define SPI_I2SSTS_RXTOIF_Pos (12) /*!< SPI_T::I2SSTS: RXTOIF Position */ +#define SPI_I2SSTS_RXTOIF_Msk (0x1ul << SPI_I2SSTS_RXTOIF_Pos) /*!< SPI_T::I2SSTS: RXTOIF Mask */ + +#define SPI_I2SSTS_I2SENSTS_Pos (15) /*!< SPI_T::I2SSTS: I2SENSTS Position */ +#define SPI_I2SSTS_I2SENSTS_Msk (0x1ul << SPI_I2SSTS_I2SENSTS_Pos) /*!< SPI_T::I2SSTS: I2SENSTS Mask */ + +#define SPI_I2SSTS_TXEMPTY_Pos (16) /*!< SPI_T::I2SSTS: TXEMPTY Position */ +#define SPI_I2SSTS_TXEMPTY_Msk (0x1ul << SPI_I2SSTS_TXEMPTY_Pos) /*!< SPI_T::I2SSTS: TXEMPTY Mask */ + +#define SPI_I2SSTS_TXFULL_Pos (17) /*!< SPI_T::I2SSTS: TXFULL Position */ +#define SPI_I2SSTS_TXFULL_Msk (0x1ul << SPI_I2SSTS_TXFULL_Pos) /*!< SPI_T::I2SSTS: TXFULL Mask */ + +#define SPI_I2SSTS_TXTHIF_Pos (18) /*!< SPI_T::I2SSTS: TXTHIF Position */ +#define SPI_I2SSTS_TXTHIF_Msk (0x1ul << SPI_I2SSTS_TXTHIF_Pos) /*!< SPI_T::I2SSTS: TXTHIF Mask */ + +#define SPI_I2SSTS_TXUFIF_Pos (19) /*!< SPI_T::I2SSTS: TXUFIF Position */ +#define SPI_I2SSTS_TXUFIF_Msk (0x1ul << SPI_I2SSTS_TXUFIF_Pos) /*!< SPI_T::I2SSTS: TXUFIF Mask */ + +#define SPI_I2SSTS_RZCIF_Pos (20) /*!< SPI_T::I2SSTS: RZCIF Position */ +#define SPI_I2SSTS_RZCIF_Msk (0x1ul << SPI_I2SSTS_RZCIF_Pos) /*!< SPI_T::I2SSTS: RZCIF Mask */ + +#define SPI_I2SSTS_LZCIF_Pos (21) /*!< SPI_T::I2SSTS: LZCIF Position */ +#define SPI_I2SSTS_LZCIF_Msk (0x1ul << SPI_I2SSTS_LZCIF_Pos) /*!< SPI_T::I2SSTS: LZCIF Mask */ + +#define SPI_I2SSTS_SLVERRIF_Pos (22) /*!< SPI_T::I2SSTS: SLVERRIF Position */ +#define SPI_I2SSTS_SLVERRIF_Msk (0x1ul << SPI_I2SSTS_SLVERRIF_Pos) /*!< SPI_T::I2SSTS: SLVERRIF Mask */ + +#define SPI_I2SSTS_TXRXRST_Pos (23) /*!< SPI_T::I2SSTS: TXRXRST Position */ +#define SPI_I2SSTS_TXRXRST_Msk (0x1ul << SPI_I2SSTS_TXRXRST_Pos) /*!< SPI_T::I2SSTS: TXRXRST Mask */ + +#define SPI_I2SSTS_RXCNT_Pos (24) /*!< SPI_T::I2SSTS: RXCNT Position */ +#define SPI_I2SSTS_RXCNT_Msk (0x7ul << SPI_I2SSTS_RXCNT_Pos) /*!< SPI_T::I2SSTS: RXCNT Mask */ + +#define SPI_I2SSTS_TXCNT_Pos (28) /*!< SPI_T::I2SSTS: TXCNT Position */ +#define SPI_I2SSTS_TXCNT_Msk (0x7ul << SPI_I2SSTS_TXCNT_Pos) /*!< SPI_T::I2SSTS: TXCNT Mask */ + +/**@}*/ /* SPI_CONST */ +/**@}*/ /* end of SPI register group */ +/**@}*/ /* end of REGISTER group */ + +#if defined ( __CC_ARM ) + #pragma no_anon_unions +#endif + +#endif /* __SPI_REG_H__ */ diff --git a/bsp/nuvoton/libraries/ma35/Device/Nuvoton/MA35D1/Include/ssmcc_reg.h b/bsp/nuvoton/libraries/ma35/Device/Nuvoton/MA35D1/Include/ssmcc_reg.h new file mode 100644 index 0000000000..1ad967d3d0 --- /dev/null +++ b/bsp/nuvoton/libraries/ma35/Device/Nuvoton/MA35D1/Include/ssmcc_reg.h @@ -0,0 +1,932 @@ +/**************************************************************************//** + * @file ssmcc_reg.h + * @brief SSMCC register definition header file + * + * SPDX-License-Identifier: Apache-2.0 + * @copyright (C) 2021 Nuvoton Technology Corp. All rights reserved. + *****************************************************************************/ +#ifndef __SSMCC_REG_H__ +#define __SSMCC_REG_H__ + +#if defined ( __CC_ARM ) + #pragma anon_unions +#endif + + +/******************************************************************************/ +/* Device Specific Peripheral registers structures */ +/******************************************************************************/ + +/** @addtogroup REGISTER Control Register + + @{ + +*/ + +typedef struct +{ + /** + * @var FAIL_T::ADDRESS_LOW + * Offset: 0x20 Contains the lower 32 bits of the address of the first access that failed a region permission check in the associated filter unit. + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[31:0] |addr_status_low|If a region permission check fails or a region overlap occurs, this field returns the ACE-Lite address bits [31:0] of the first f. You must clear the associated interrupt status before this field can return the address of accesses of subsequent permission checks or region overlap failures. This occurs even if the ACTION register does not enable the interrupt. If the status flag for the filter unit in the INT_STATUS register is already set, new region permission check failures in the same filter unit do not update the associated fail status group of registers. + * @var FAIL_T::ADDRESS_HIGH + * Offset: 0x24 Reserved + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * @var FAIL_T::CONTROL + * Offset: 0x28 Contains the control status information of the first access that failed a region permission check in the associated filter unit. + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[20] |Privileged|If a region permission check fails or a region overlap occurs, this field indicates whether it was an unprivileged or privileged access attempt You must clear the associated interrupt status before this field can return the values of accesses of subsequent permission checks or region overlap failures 0 Unprivileged access 1 Privileged access If the status flag for the filter unit in the INT_STATUS register is already set, new region permission check failures in the same filter unit do not update the associated fail status group of registers. + * |[21] |Non_secure|If a region permission check fails or a region overlap occurs, this field indicates whether it was a Secure or Non- secure access attempt You must clear the associated interrupt status before this field can return the direction of accesses of subsequent permission checks or region overlap failures 0 Secure access 1 Non-secure access If the status flag for the filter unit in the INT_STATUS register is already set, new region permission check failures in the same filter unit do not update the associated fail status group of registers. + * |[24] |Direction |If a region permission check fails or a region overlap occurs, this field indicates whether the failed access was a read or write access attempt You must clear the associated interrupt status before this field can return the direction of accesses of subsequent permission checks or region overlap failures 0 Read access 1 Write access If the status flag for the filter unit in the INT_STATUS register is already set, new region permission check failures in the same filter unit do not update the associated fail status group of registers. + * @var FAIL_T::ID + * Offset: 0x2C Contains the master ACE-Lite ARID or AWID of the first access that failed a region permission check in the associated filter unit. + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[5:0] |id |If a region permission check fails or a region overlap occurs, this field returns the ACE-Lite ID values of the first failed access If the status flag for the filter unit in the INT_STATUS register is already set, new region permission check failures in the same filter unit do not update the associated fail status group of registers. + * |[27:24] |vnet |If a region permission check fails or a region overlap occurs, this field returns the VN number of the first failed access, from either ARVNET or AWVNET as appropriate If the status flag for the filter unit in the INT_STATUS register is already set, new region permission check failures in the same filter unit do not update the associated fail status group of registers. + */ + __I uint32_t ADDRESS_LOW; /*!< [0x0000] Contains the lower 32 bits of the address of the first access that failed a region permission check in the associated filter unit. */ + __IO uint32_t ADDRESS_HIGH; /*!< [0x0004] Reserved */ + __I uint32_t CONTROL; /*!< [0x0008] Contains the control status information of the first access that failed a region permission check in the associated filter unit. */ + __I uint32_t ID; /*!< [0x000c] Contains the master ACE-Lite ARID or AWID of the first access that failed a region permission check in the associated filter unit. */ +} FAIL_STS_T; + +typedef struct +{ + __IO uint32_t BASE_LOW; /*!< [0x0000] */ + __IO uint32_t BASE_HIGH; /*!< [0x0004] */ + __IO uint32_t TOP_LOW; /*!< [0x0008] */ + __IO uint32_t TOP_HIGH; /*!< [0x000c] */ + __IO uint32_t ATTRIBUTES; /*!< [0x0010] */ + __IO uint32_t ID_ACCESS; /*!< [0x0014] */ + __I uint32_t RESERVE2[2]; /*!< [0x0018] */ +} REGION_T; + +/*---------------------- System Security Memory Configuration Controller -------------------------*/ +/** + @addtogroup SSMCC System Security Memory Configuration Controller(SSMCC) + Memory Mapped Structure for SSMCC Controller +@{ */ + +typedef struct +{ + + + /** + * @var SSMCC_T::SCWP + * Offset: 0x00 Security Configuration Write Protect Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[0] |ENABLE |Write Protection Enable Bit + * | | |0 = Security Configuration Write Protection Disabled. + * | | |1 = Security Configuration Write Protection Enabled. + * |[1] |LOCK |Write Protection Enable and Lock Bit (Write 1 to Set) + * | | |0 = Security Configuration Write Protection Disabled. + * | | |1 = Security Configuration Write Protection Enabled. + * | | |Note: This bit can only be cleared by system reset. + * |[31:16] |WVCODE |Write Verify Code + * | | |Read operation: + * | | |Reserved, all zeros. + * | | |Write operation: + * | | |0x475A = The write verify code, 0x475A, is needed to do a valid write to SSMCC_SCWP. + * | | |Others = Invalid write verify code. + */ + __IO uint32_t SCWP; /*!< [0x0000] Security Configuration Write Protect Register */ + +} SSMCC_T; + +/** + @addtogroup SSMCC_CONST SSMCC Bit Field Definition + Constant Definitions for SSMCC Controller +@{ */ + +#define SSMCC_SCWP_ENABLE_Pos (0) /*!< SSMCC_T::SCWP: ENABLE Position */ +#define SSMCC_SCWP_ENABLE_Msk (0x1ul << SSMCC_SCWP_ENABLE_Pos) /*!< SSMCC_T::SCWP: ENABLE Mask */ + +#define SSMCC_SCWP_LOCK_Pos (1) /*!< SSMCC_T::SCWP: LOCK Position */ +#define SSMCC_SCWP_LOCK_Msk (0x1ul << SSMCC_SCWP_LOCK_Pos) /*!< SSMCC_T::SCWP: LOCK Mask */ + +#define SSMCC_SCWP_WVCODE_Pos (16) /*!< SSMCC_T::SCWP: WVCODE Position */ +#define SSMCC_SCWP_WVCODE_Msk (0xfffful << SSMCC_SCWP_WVCODE_Pos) /*!< SSMCC_T::SCWP: WVCODE Mask */ + +/**@}*/ /* SSMCC_CONST */ +/**@}*/ /* end of SSMCC register group */ + + +/*---------------------- TrustZone Address Space Controller -------------------------*/ +/** + @addtogroup TZC TrustZone Address Space Controller(TZC) + Memory Mapped Structure for TZC Controller +@{ */ + +typedef struct +{ + /** + * @var TZC_T::BUILD_CONFIG + * Offset: 0x00 Provides information about the configuration of the TZC-400. + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[4:0] |no_of_regions|Defines the number of regions that the TZC-400 provides: 0b01000 Nine regions All other values Reserved. + * |[13:8] |address_width|Defines the width of the ACE-Lite address bus: 0b011111 32 bits 0b100011 36 bits 0b100111 40 bits 0b101111 48 bits 0b111111 64 bits All other values Reserved. + * |[25:24] |no_of_filters|Defines the number of filter units in the design implementation: 0b00 One filter unit 0b01 Two filter units 0b10 Reserved 0b11 Four filter units. + * @var TZC_T::ACTION + * Offset: 0x04 Controls the interrupt and bus response signaling behavior of the TZC-400 when region permission failures occur. + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[1:0] |reaction_value|Controls how the TZC-400 uses the BRESPS[1:0], RRESPS[1:0], and TZCINT signals when a region permission failure occurs, excluding region overlap errors The settings for these bits are: 0b00 Sets TZCINT LOW and issues an OKAY response 0b01 Sets TZCINT LOW and issues a DECERR response 0b10 Sets TZCINT HIGH and issues an OKAY response 0b11 Sets TZCINT HIGH and issues a DECERR response When a region overlap for region 1 and higher occurs, this field also determines how TZCINT is set The settings are: 0b00, 0b01 TZCINT LOW 0b10, 0b11 TZCINT HIGH. + * @var TZC_T::GATE_KEEPER + * Offset: 0x08 Provides control and status for the gate keeper in each filter unit implemented + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[3:0] |open_request|Each bit in this field requests the gate of the associated filter unit to be open or closed Each bit is associated as follows: bit 0 Filter 0 bit 1 Filter 1 bit 2 Filter 2 bit 3 Filter 3. Set the open_request bit to 1, to request the gate to be open Set the open_request bit to 0, to request the gate to be closed If any of the associated filter units are not implemented, the corresponding open_request bits are unused, + * |[19:16] |open_status|The current state of the gate keeper in each filter unit The bit associations are as follows: bit 16 Filter 0 gate keeper status bit 17 Filter 1 gate keeper status bit 18 Filter 2 gate keeper status bit 19 Filter 3 gate keeper status When a bit is set to 1, the gate keeper permits access to its associated filter, that is, it is open When a bit is set to 0, the gate keeper no longer permits access to its associated filter, that is, it is closed This bit is set to 0 when both of the following conditions are fulfilled:This means that the gate keeper always waits for outstanding accesses to complete • The gate keeper no longer permits access to its associated filter • All outstanding accesses through the filter unit are complete If any of the associated filter units are not implemented, the corresponding gate keeper bits are unused, + * @var TZC_T::SPECULATION_CTRL + * Offset: 0x0C Controls the read access speculation and write access speculation. + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[0] |read_spec_disable|Controls read access speculation Note This bit is ignored and assumed to be zero at a filter unit if the corresponding QVNENABLE signal is HIGH You can set this bit as follows: 0 Enables read access speculation This is the default setting 1 Disables read access speculation. + * |[1] |write_spec_disable|Controls write acc. Note This bit is ignored and assumed to be zero at a filter unit if the corresponding QVNENABLE signal is HIGH. Set this bit as follows: 0 Enables write access speculation. This is the default setting. 1 Disables write access speculation. + * @var TZC_T::INT_STATUS + * Offset: 0x10 Contains the status of the interrupt signal, TZCINT, that reports access security violations or region overlap errors. + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[3:0] |status |Each bit is associated as follows: bit 0 Filter 0 bit 1 Filter 1 bit 2 Filter 2 bit 3 Filter 3. Each bit in this field indicates the status of the interrupt from each filter unit as follows: 0 Interrupt is not asserted 1 Interrupt is asserted and waiting to be cleared This bit is set even if the ACTION register is set to not drive the interrupt output TZCINT HIGH Therefore, the status acts as an indicator that a region permission check failure or an overlap error has occurred at a particular filter unit. + * |[11:8] |overrun |The bit associations are as follows: bit 8 Filter 0 bit 9 Filter 1 bit 10 Filter 2 bit 11 Filter 3. When a bit is set to 1, it indicates the occurrence of two or more region permission or region overlapping failures at the associated filter unit after the interrupt was cleared by the associated bit This bit is set even if the ACTION register is set to not drive the interrupt Clear the interrupt status of the associated bit in the INT_CLEAR register to also clear this field. + * |[19:16] |overlap |The bit associations are as follows: bit 16 Filter 0 bit 17 Filter 1 bit 18 Filter 2 bit 19 Filter 3 When a bit is set to 1, it indicates a violation of the overlap region configuration rules for the associated filter unit This occurs when an access matches with two enabled regions at the same time unless the overlap is only with Region 0. This bit is set even if the ACTION register is set to not drive the interrupt When this bit is 1, the interrupt status bit is also set to 1. Clear the interrupt status of the associated bit to also clear this field + * @var TZC_T::INT_CLEAR + * Offset: 0x14 Clears the interrupt. + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[3:0] |clear |Contains the control bits to clear interrupts The bit associations are as follows: bit 0 Filter 0 bit 1 Filter 1 bit 2 Filter 2 bit 3 Filter 3. Write a 1 to any of these bits to clear the associated status, overrun, and overlap bits in the INT_STATUS register. + * @var TZC_T::FAIL_ADDRESS_LOW_0 + * Offset: 0x20 Contains the lower 32 bits of the address of the first access that failed a region permission check in the associated filter unit. + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[31:0] |addr_status_low|If a region permission check fails or a region overlap occurs, this field returns the ACE-Lite address bits [31:0] of the first f. You must clear the associated interrupt status before this field can return the address of accesses of subsequent permission checks or region overlap failures. This occurs even if the ACTION register does not enable the interrupt. If the status flag for the filter unit in the INT_STATUS register is already set, new region permission check failures in the same filter unit do not update the associated fail status group of registers. + * @var TZC_T::FAIL_ADDRESS_HIGH_0 + * Offset: 0x24 Reserved + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * @var TZC_T::FAIL_CONTROL_0 + * Offset: 0x28 Contains the control status information of the first access that failed a region permission check in the associated filter unit. + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[20] |Privileged|If a region permission check fails or a region overlap occurs, this field indicates whether it was an unprivileged or privileged access attempt You must clear the associated interrupt status before this field can return the values of accesses of subsequent permission checks or region overlap failures 0 Unprivileged access 1 Privileged access If the status flag for the filter unit in the INT_STATUS register is already set, new region permission check failures in the same filter unit do not update the associated fail status group of registers. + * |[21] |Non_secure|If a region permission check fails or a region overlap occurs, this field indicates whether it was a Secure or Non- secure access attempt You must clear the associated interrupt status before this field can return the direction of accesses of subsequent permission checks or region overlap failures 0 Secure access 1 Non-secure access If the status flag for the filter unit in the INT_STATUS register is already set, new region permission check failures in the same filter unit do not update the associated fail status group of registers. + * |[24] |Direction |If a region permission check fails or a region overlap occurs, this field indicates whether the failed access was a read or write access attempt You must clear the associated interrupt status before this field can return the direction of accesses of subsequent permission checks or region overlap failures 0 Read access 1 Write access If the status flag for the filter unit in the INT_STATUS register is already set, new region permission check failures in the same filter unit do not update the associated fail status group of registers. + * @var TZC_T::FAIL_ID_0 + * Offset: 0x2C Contains the master ACE-Lite ARID or AWID of the first access that failed a region permission check in the associated filter unit. + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[5:0] |id |If a region permission check fails or a region overlap occurs, this field returns the ACE-Lite ID values of the first failed access If the status flag for the filter unit in the INT_STATUS register is already set, new region permission check failures in the same filter unit do not update the associated fail status group of registers. + * |[27:24] |vnet |If a region permission check fails or a region overlap occurs, this field returns the VN number of the first failed access, from either ARVNET or AWVNET as appropriate If the status flag for the filter unit in the INT_STATUS register is already set, new region permission check failures in the same filter unit do not update the associated fail status group of registers. + * @var TZC_T::FAIL_ADDRESS_LOW_1 + * Offset: 0x30 Contains the lower 32 bits of the address of the first access that failed a region permission check in the associated filter unit. + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[31:0] |addr_status_low|If a region permission check fails or a region overlap occurs, this field returns the ACE-Lite address bits [31:0] of the first f. You must clear the associated interrupt status before this field can return the address of accesses of subsequent permission checks or region overlap failures. This occurs even if the ACTION register does not enable the interrupt. If the status flag for the filter unit in the INT_STATUS register is already set, new region permission check failures in the same filter unit do not update the associated fail status group of registers. + * @var TZC_T::FAIL_ADDRESS_HIGH_1 + * Offset: 0x34 Reserved + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * @var TZC_T::FAIL_CONTROL_1 + * Offset: 0x38 Contains the control status information of the first access that failed a region permission check in the associated filter unit. + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[20] |Privileged|If a region permission check fails or a region overlap occurs, this field indicates whether it was an unprivileged or privileged access attempt You must clear the associated interrupt status before this field can return the values of accesses of subsequent permission checks or region overlap failures 0 Unprivileged access 1 Privileged access If the status flag for the filter unit in the INT_STATUS register is already set, new region permission check failures in the same filter unit do not update the associated fail status group of registers. + * |[21] |Non_secure|If a region permission check fails or a region overlap occurs, this field indicates whether it was a Secure or Non- secure access attempt You must clear the associated interrupt status before this field can return the direction of accesses of subsequent permission checks or region overlap failures 0 Secure access 1 Non-secure access If the status flag for the filter unit in the INT_STATUS register is already set, new region permission check failures in the same filter unit do not update the associated fail status group of registers. + * |[24] |Direction |If a region permission check fails or a region overlap occurs, this field indicates whether the failed access was a read or write access attempt You must clear the associated interrupt status before this field can return the direction of accesses of subsequent permission checks or region overlap failures 0 Read access 1 Write access If the status flag for the filter unit in the INT_STATUS register is already set, new region permission check failures in the same filter unit do not update the associated fail status group of registers. + * @var TZC_T::FAIL_ID_1 + * Offset: 0x3C Contains the master ACE-Lite ARID or AWID of the first access that failed a region permission check in the associated filter unit. + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[5:0] |id |If a region permission check fails or a region overlap occurs, this field returns the ACE-Lite ID values of the first failed access If the status flag for the filter unit in the INT_STATUS register is already set, new region permission check failures in the same filter unit do not update the associated fail status group of registers. + * |[27:24] |vnet |If a region permission check fails or a region overlap occurs, this field returns the VN number of the first failed access, from either ARVNET or AWVNET as appropriate If the status flag for the filter unit in the INT_STATUS register is already set, new region permission check failures in the same filter unit do not update the associated fail status group of registers. + * @var TZC_T::FAIL_ADDRESS_LOW_2 + * Offset: 0x40 Contains the lower 32 bits of the address of the first access that failed a region permission check in the associated filter unit. + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[31:0] |addr_status_low|If a region permission check fails or a region overlap occurs, this field returns the ACE-Lite address bits [31:0] of the first f. You must clear the associated interrupt status before this field can return the address of accesses of subsequent permission checks or region overlap failures. This occurs even if the ACTION register does not enable the interrupt. If the status flag for the filter unit in the INT_STATUS register is already set, new region permission check failures in the same filter unit do not update the associated fail status group of registers. + * @var TZC_T::FAIL_ADDRESS_HIGH_2 + * Offset: 0x44 Reserved + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * @var TZC_T::FAIL_CONTROL_2 + * Offset: 0x48 Contains the control status information of the first access that failed a region permission check in the associated filter unit. + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[20] |Privileged|If a region permission check fails or a region overlap occurs, this field indicates whether it was an unprivileged or privileged access attempt You must clear the associated interrupt status before this field can return the values of accesses of subsequent permission checks or region overlap failures 0 Unprivileged access 1 Privileged access If the status flag for the filter unit in the INT_STATUS register is already set, new region permission check failures in the same filter unit do not update the associated fail status group of registers. + * |[21] |Non_secure|If a region permission check fails or a region overlap occurs, this field indicates whether it was a Secure or Non- secure access attempt You must clear the associated interrupt status before this field can return the direction of accesses of subsequent permission checks or region overlap failures 0 Secure access 1 Non-secure access If the status flag for the filter unit in the INT_STATUS register is already set, new region permission check failures in the same filter unit do not update the associated fail status group of registers. + * |[24] |Direction |If a region permission check fails or a region overlap occurs, this field indicates whether the failed access was a read or write access attempt You must clear the associated interrupt status before this field can return the direction of accesses of subsequent permission checks or region overlap failures 0 Read access 1 Write access If the status flag for the filter unit in the INT_STATUS register is already set, new region permission check failures in the same filter unit do not update the associated fail status group of registers. + * @var TZC_T::FAIL_ID_2 + * Offset: 0x4C Contains the master ACE-Lite ARID or AWID of the first access that failed a region permission check in the associated filter unit. + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[5:0] |id |If a region permission check fails or a region overlap occurs, this field returns the ACE-Lite ID values of the first failed access If the status flag for the filter unit in the INT_STATUS register is already set, new region permission check failures in the same filter unit do not update the associated fail status group of registers. + * |[27:24] |vnet |If a region permission check fails or a region overlap occurs, this field returns the VN number of the first failed access, from either ARVNET or AWVNET as appropriate If the status flag for the filter unit in the INT_STATUS register is already set, new region permission check failures in the same filter unit do not update the associated fail status group of registers. + * @var TZC_T::REGION_BASE_LOW_0 + * Offset: 0x100 This register is read-only and is hard-wired to all zeros. + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[31:12] |base_address_low_n_|Controls the base address bits[31:12] of Region + * | | |For Region 0, this field is read-only. The TZC-400 sets the base address of Region 0 to 0x0. + * @var TZC_T::REGION_BASE_HIGH_0 + * Offset: 0x104 This register is read-only and is hard-wired to all zeros. + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * @var TZC_T::REGION_TOP_LOW_0 + * Offset: 0x108 This register is read-only and is hard-wired to all 1. + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[31:12] |top_address_low_n_|Controls the region top address bits[31:12] of region + * | | |For Region 0, this field is read-only and all bits are set HIGH. + * | | |. + * @var TZC_T::REGION_TOP_HIGH_0 + * Offset: 0x10C This register is read-only and is hard-wired to all zeros. + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * @var TZC_T::REGION_ATTRIBUTES_0 + * Offset: 0x110 Controls the permissions for Region 0. + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[3:0] |filter_en |Independent region enable for each filter unit Each bit is associated with a filter unit Set these bits as follows: Bit 0 For Filter 0 Bit 1 For Filter 1 Bit 2 For Filter 2 Bit 3 For Filter 3. When set HIGH, it enables the use of the current region programming for the associated filter For Region 0, all bits are set HIGH and cannot be modified. + * |[30] |s_rd_en |Secure global read enable This control bit defines the permissions for the Secure reads in the region Set this bit as follows: 0 Secure read to the region is not permitted 1 Permits Secure read to the region. + * |[31] |s_wr_en |Secure global write enable This control bit defines the permissions for the Secure writes in the region Set this bit as follows: 0 Secure write to the region is not permitted 1 Permits Secure write to the region. + * @var TZC_T::REGION_ID_ACCESS_0 + * Offset: 0x114 Controls the Non-secure access based on the NSAID inputs for Region 0. + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[15:0] |nsaid_rd_en|NSAID read enables + * | | |This enables NSAID inputs to define Non-secure read access permission Each bit of the nsaid_rd_en register field is associated with a value on the NSAIDR signal as follows: Bit 0 Associated with NSAIDR = 0 + * | | |Bit 1 Associated with NSAIDR = 1 + * | | |Bit 2 Associated with NSAIDR = 2 + * | | |Bit 15 Associated with NSAIDR = 15 + * | | | is the filter unit number + * | | |When any bit in this field is set HIGH, TZC-400 permits Non-secure read access to any access with the associated NSAIDR value + * | | |For example, if NSAIDR is 3 and the corresponding nsaid_rd_en[3] bit is set HIGH then TZC-400 permits the Non-secure read access to progress. + * |[31:16] |nsaid_wr_en|NSAID write enables + * | | |This enables NSAID inputs to define Non-secure write access permission Each bit of the nsaid_wr_en register field is associated with a value on the NSAIDW signal as follows: Bit 16 Associated with NSAIDW = 0 + * | | |Bit 17 Associated with NSAIDW = 1 + * | | |Bit 18 Associated with NSAIDW = 2 + * | | |Bit 31 Associated with NSAIDW = 15 + * | | | is the filter unit number + * | | |When any bit in this field is set to 1, TZC-400 permits Non-secure write access to any access with the associated NSAIDW value + * | | |For example, if NSAIDW is 3 and the corresponding nsaid_wr_en[3] bit is set HIGH then TZC-400 permits the Non-secure write access to progress. + * @var TZC_T::REGION_BASE_LOW_1 + * Offset: 0x120 Controls the base address bits[31:12] of Region . + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[31:12] |base_address_low_n_|Controls the base address bits[31:12] of Region For Region 0, this field is read-only The TZC-400 sets the base address of Region 0 to 0x0 The TZC-400 only permits a region to start at a 4KB aligned address and address bits[11:0] are zeros. + * @var TZC_T::REGION_BASE_HIGH_1 + * Offset: 0x124 Reserved + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * @var TZC_T::REGION_TOP_LOW_1 + * Offset: 0x128 Controls the region top address bits[31:12] of Region . + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[31:12] |top_address_low_n_|Controls the region top address bits[31:12] of region This address points to the start of the next 4KB aligned address immediately outside the region. + * @var TZC_T::REGION_TOP_HIGH_1 + * Offset: 0x12C Reserved + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * @var TZC_T::REGION_ATTRIBUTES_1 + * Offset: 0x130 Controls the permissions and target filter region enables. + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[3:0] |filter_en |Independent region enable for each filter unit Each bit is associated with a filter unit Set these bits as follows: Bit 0 For Filter 0 Bit 1 For Filter 1 Bit 2 For Filter 2 Bit 3 For Filter 3. When set HIGH, it enables the use of the current region programming for the associated filter For Region 0, all bits are set HIGH and cannot be modified. + * |[30] |s_rd_en |Secure global read enable This control bit defines the permissions for the Secure reads in the region Set this bit as follows: 0 Secure read to the region is not permitted 1 Permits Secure read to the region. + * |[31] |s_wr_en |Secure global write enable This control bit defines the permissions for the Secure writes in the region Set this bit as follows: 0 Secure write to the region is not permitted 1 Permits Secure write to the region. + * @var TZC_T::REGION_ID_ACCESS_1 + * Offset: 0x134 Controls the Non-secure access based on the NSAID inputs. + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[15:0] |nsaid_rd_en|NSAID read enables + * | | |This enables NSAID inputs to define Non-secure read access permission Each bit of the nsaid_rd_en register field is associated with a value on the NSAIDR signal as follows: Bit 0 Associated with NSAIDR = 0 + * | | |Bit 1 Associated with NSAIDR = 1 + * | | |Bit 2 Associated with NSAIDR = 2 + * | | |Bit 15 Associated with NSAIDR = 15 + * | | | is the filter unit number + * | | |When any bit in this field is set HIGH, TZC-400 permits Non-secure read access to any access with the associated NSAIDR value + * | | |For example, if NSAIDR is 3 and the corresponding nsaid_rd_en[3] bit is set HIGH then TZC-400 permits the Non-secure read access to progress. + * |[31:16] |nsaid_wr_en|NSAID write enables + * | | |This enables NSAID inputs to define Non-secure write access permission Each bit of the nsaid_wr_en register field is associated with a value on the NSAIDW signal as follows: Bit 16 Associated with NSAIDW = 0 + * | | |Bit 17 Associated with NSAIDW = 1 + * | | |Bit 18 Associated with NSAIDW = 2 + * | | |Bit 31 Associated with NSAIDW = 15 + * | | | is the filter unit number + * | | |When any bit in this field is set to 1, TZC-400 permits Non-secure write access to any access with the associated NSAIDW value + * | | |For example, if NSAIDW is 3 and the corresponding nsaid_wr_en[3] bit is set HIGH then TZC-400 permits the Non-secure write access to progress. + * @var TZC_T::REGION_BASE_LOW_2 + * Offset: 0x140 Controls the base address bits[31:12] of Region . + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[31:12] |base_address_low_n_|Controls the base address bits[31:12] of Region For Region 0, this field is read-only The TZC-400 sets the base address of Region 0 to 0x0 The TZC-400 only permits a region to start at a 4KB aligned address and address bits[11:0] are zeros. + * @var TZC_T::REGION_BASE_HIGH_2 + * Offset: 0x144 Reserved + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * @var TZC_T::REGION_TOP_LOW_2 + * Offset: 0x148 Controls the region top address bits[31:12] of Region . + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[31:12] |top_address_low_n_|Controls the region top address bits[31:12] of region This address points to the start of the next 4KB aligned address immediately outside the region. + * @var TZC_T::REGION_TOP_HIGH_2 + * Offset: 0x14C Reserved + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * @var TZC_T::REGION_ATTRIBUTES_2 + * Offset: 0x150 Controls the permissions and target filter region enables. + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[3:0] |filter_en |Independent region enable for each filter unit Each bit is associated with a filter unit Set these bits as follows: Bit 0 For Filter 0 Bit 1 For Filter 1 Bit 2 For Filter 2 Bit 3 For Filter 3. When set HIGH, it enables the use of the current region programming for the associated filter For Region 0, all bits are set HIGH and cannot be modified. + * |[30] |s_rd_en |Secure global read enable This control bit defines the permissions for the Secure reads in the region Set this bit as follows: 0 Secure read to the region is not permitted 1 Permits Secure read to the region. + * |[31] |s_wr_en |Secure global write enable This control bit defines the permissions for the Secure writes in the region Set this bit as follows: 0 Secure write to the region is not permitted 1 Permits Secure write to the region. + * @var TZC_T::REGION_ID_ACCESS_2 + * Offset: 0x154 Controls the Non-secure access based on the NSAID inputs. + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[15:0] |nsaid_rd_en|NSAID read enables + * | | |This enables NSAID inputs to define Non-secure read access permission Each bit of the nsaid_rd_en register field is associated with a value on the NSAIDR signal as follows: Bit 0 Associated with NSAIDR = 0 + * | | |Bit 1 Associated with NSAIDR = 1 + * | | |Bit 2 Associated with NSAIDR = 2 + * | | |Bit 15 Associated with NSAIDR = 15 + * | | | is the filter unit number + * | | |When any bit in this field is set HIGH, TZC-400 permits Non-secure read access to any access with the associated NSAIDR value + * | | |For example, if NSAIDR is 3 and the corresponding nsaid_rd_en[3] bit is set HIGH then TZC-400 permits the Non-secure read access to progress. + * |[31:16] |nsaid_wr_en|NSAID write enables + * | | |This enables NSAID inputs to define Non-secure write access permission Each bit of the nsaid_wr_en register field is associated with a value on the NSAIDW signal as follows: Bit 16 Associated with NSAIDW = 0 + * | | |Bit 17 Associated with NSAIDW = 1 + * | | |Bit 18 Associated with NSAIDW = 2 + * | | |Bit 31 Associated with NSAIDW = 15 + * | | | is the filter unit number + * | | |When any bit in this field is set to 1, TZC-400 permits Non-secure write access to any access with the associated NSAIDW value + * | | |For example, if NSAIDW is 3 and the corresponding nsaid_wr_en[3] bit is set HIGH then TZC-400 permits the Non-secure write access to progress. + * @var TZC_T::REGION_BASE_LOW_3 + * Offset: 0x160 Controls the base address bits[31:12] of Region . + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[31:12] |base_address_low_n_|Controls the base address bits[31:12] of Region For Region 0, this field is read-only The TZC-400 sets the base address of Region 0 to 0x0 The TZC-400 only permits a region to start at a 4KB aligned address and address bits[11:0] are zeros. + * @var TZC_T::REGION_BASE_HIGH_3 + * Offset: 0x164 Reserved + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * @var TZC_T::REGION_TOP_LOW_3 + * Offset: 0x168 Controls the region top address bits[31:12] of Region . + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[31:12] |top_address_low_n_|Controls the region top address bits[31:12] of region This address points to the start of the next 4KB aligned address immediately outside the region. + * @var TZC_T::REGION_TOP_HIGH_3 + * Offset: 0x16C Reserved + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * @var TZC_T::REGION_ATTRIBUTES_3 + * Offset: 0x170 Controls the permissions and target filter region enables. + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[3:0] |filter_en |Independent region enable for each filter unit Each bit is associated with a filter unit Set these bits as follows: Bit 0 For Filter 0 Bit 1 For Filter 1 Bit 2 For Filter 2 Bit 3 For Filter 3. When set HIGH, it enables the use of the current region programming for the associated filter For Region 0, all bits are set HIGH and cannot be modified. + * |[30] |s_rd_en |Secure global read enable This control bit defines the permissions for the Secure reads in the region Set this bit as follows: 0 Secure read to the region is not permitted 1 Permits Secure read to the region. + * |[31] |s_wr_en |Secure global write enable This control bit defines the permissions for the Secure writes in the region Set this bit as follows: 0 Secure write to the region is not permitted 1 Permits Secure write to the region. + * @var TZC_T::REGION_ID_ACCESS_3 + * Offset: 0x174 Controls the Non-secure access based on the NSAID inputs. + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[15:0] |nsaid_rd_en|NSAID read enables + * | | |This enables NSAID inputs to define Non-secure read access permission Each bit of the nsaid_rd_en register field is associated with a value on the NSAIDR signal as follows: Bit 0 Associated with NSAIDR = 0 + * | | |Bit 1 Associated with NSAIDR = 1 + * | | |Bit 2 Associated with NSAIDR = 2 + * | | |Bit 15 Associated with NSAIDR = 15 + * | | | is the filter unit number + * | | |When any bit in this field is set HIGH, TZC-400 permits Non-secure read access to any access with the associated NSAIDR value + * | | |For example, if NSAIDR is 3 and the corresponding nsaid_rd_en[3] bit is set HIGH then TZC-400 permits the Non-secure read access to progress. + * |[31:16] |nsaid_wr_en|NSAID write enables + * | | |This enables NSAID inputs to define Non-secure write access permission Each bit of the nsaid_wr_en register field is associated with a value on the NSAIDW signal as follows: Bit 16 Associated with NSAIDW = 0 + * | | |Bit 17 Associated with NSAIDW = 1 + * | | |Bit 18 Associated with NSAIDW = 2 + * | | |Bit 31 Associated with NSAIDW = 15 + * | | | is the filter unit number + * | | |When any bit in this field is set to 1, TZC-400 permits Non-secure write access to any access with the associated NSAIDW value + * | | |For example, if NSAIDW is 3 and the corresponding nsaid_wr_en[3] bit is set HIGH then TZC-400 permits the Non-secure write access to progress. + * @var TZC_T::REGION_BASE_LOW_4 + * Offset: 0x180 Controls the base address bits[31:12] of Region . + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[31:12] |base_address_low_n_|Controls the base address bits[31:12] of Region For Region 0, this field is read-only The TZC-400 sets the base address of Region 0 to 0x0 The TZC-400 only permits a region to start at a 4KB aligned address and address bits[11:0] are zeros. + * @var TZC_T::REGION_BASE_HIGH_4 + * Offset: 0x184 Reserved + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * @var TZC_T::REGION_TOP_LOW_4 + * Offset: 0x188 Controls the region top address bits[31:12] of Region . + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[31:12] |top_address_low_n_|Controls the region top address bits[31:12] of region This address points to the start of the next 4KB aligned address immediately outside the region. + * @var TZC_T::REGION_TOP_HIGH_4 + * Offset: 0x18C Reserved + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * @var TZC_T::REGION_ATTRIBUTES_4 + * Offset: 0x190 Controls the permissions and target filter region enables. + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[3:0] |filter_en |Independent region enable for each filter unit Each bit is associated with a filter unit Set these bits as follows: Bit 0 For Filter 0 Bit 1 For Filter 1 Bit 2 For Filter 2 Bit 3 For Filter 3. When set HIGH, it enables the use of the current region programming for the associated filter For Region 0, all bits are set HIGH and cannot be modified. + * |[30] |s_rd_en |Secure global read enable This control bit defines the permissions for the Secure reads in the region Set this bit as follows: 0 Secure read to the region is not permitted 1 Permits Secure read to the region. + * |[31] |s_wr_en |Secure global write enable This control bit defines the permissions for the Secure writes in the region Set this bit as follows: 0 Secure write to the region is not permitted 1 Permits Secure write to the region. + * @var TZC_T::REGION_ID_ACCESS_4 + * Offset: 0x194 Controls the Non-secure access based on the NSAID inputs. + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[15:0] |nsaid_rd_en|NSAID read enables + * | | |This enables NSAID inputs to define Non-secure read access permission Each bit of the nsaid_rd_en register field is associated with a value on the NSAIDR signal as follows: Bit 0 Associated with NSAIDR = 0 + * | | |Bit 1 Associated with NSAIDR = 1 + * | | |Bit 2 Associated with NSAIDR = 2 + * | | |Bit 15 Associated with NSAIDR = 15 + * | | | is the filter unit number + * | | |When any bit in this field is set HIGH, TZC-400 permits Non-secure read access to any access with the associated NSAIDR value + * | | |For example, if NSAIDR is 3 and the corresponding nsaid_rd_en[3] bit is set HIGH then TZC-400 permits the Non-secure read access to progress. + * |[31:16] |nsaid_wr_en|NSAID write enables + * | | |This enables NSAID inputs to define Non-secure write access permission Each bit of the nsaid_wr_en register field is associated with a value on the NSAIDW signal as follows: Bit 16 Associated with NSAIDW = 0 + * | | |Bit 17 Associated with NSAIDW = 1 + * | | |Bit 18 Associated with NSAIDW = 2 + * | | |Bit 31 Associated with NSAIDW = 15 + * | | | is the filter unit number + * | | |When any bit in this field is set to 1, TZC-400 permits Non-secure write access to any access with the associated NSAIDW value + * | | |For example, if NSAIDW is 3 and the corresponding nsaid_wr_en[3] bit is set HIGH then TZC-400 permits the Non-secure write access to progress. + * @var TZC_T::REGION_BASE_LOW_5 + * Offset: 0x1A0 Controls the base address bits[31:12] of Region . + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[31:12] |base_address_low_n_|Controls the base address bits[31:12] of Region For Region 0, this field is read-only The TZC-400 sets the base address of Region 0 to 0x0 The TZC-400 only permits a region to start at a 4KB aligned address and address bits[11:0] are zeros. + * @var TZC_T::REGION_BASE_HIGH_5 + * Offset: 0x1A4 Reserved + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * @var TZC_T::REGION_TOP_LOW_5 + * Offset: 0x1A8 Controls the region top address bits[31:12] of Region . + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[31:12] |top_address_low_n_|Controls the region top address bits[31:12] of region This address points to the start of the next 4KB aligned address immediately outside the region. + * @var TZC_T::REGION_TOP_HIGH_5 + * Offset: 0x1AC Reserved + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * @var TZC_T::REGION_ATTRIBUTES_5 + * Offset: 0x1B0 Controls the permissions and target filter region enables. + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[3:0] |filter_en |Independent region enable for each filter unit Each bit is associated with a filter unit Set these bits as follows: Bit 0 For Filter 0 Bit 1 For Filter 1 Bit 2 For Filter 2 Bit 3 For Filter 3. When set HIGH, it enables the use of the current region programming for the associated filter For Region 0, all bits are set HIGH and cannot be modified. + * |[30] |s_rd_en |Secure global read enable This control bit defines the permissions for the Secure reads in the region Set this bit as follows: 0 Secure read to the region is not permitted 1 Permits Secure read to the region. + * |[31] |s_wr_en |Secure global write enable This control bit defines the permissions for the Secure writes in the region Set this bit as follows: 0 Secure write to the region is not permitted 1 Permits Secure write to the region. + * @var TZC_T::REGION_ID_ACCESS_5 + * Offset: 0x1B4 Controls the Non-secure access based on the NSAID inputs. + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[15:0] |nsaid_rd_en|NSAID read enables + * | | |This enables NSAID inputs to define Non-secure read access permission Each bit of the nsaid_rd_en register field is associated with a value on the NSAIDR signal as follows: Bit 0 Associated with NSAIDR = 0 + * | | |Bit 1 Associated with NSAIDR = 1 + * | | |Bit 2 Associated with NSAIDR = 2 + * | | |Bit 15 Associated with NSAIDR = 15 + * | | | is the filter unit number + * | | |When any bit in this field is set HIGH, TZC-400 permits Non-secure read access to any access with the associated NSAIDR value + * | | |For example, if NSAIDR is 3 and the corresponding nsaid_rd_en[3] bit is set HIGH then TZC-400 permits the Non-secure read access to progress. + * |[31:16] |nsaid_wr_en|NSAID write enables + * | | |This enables NSAID inputs to define Non-secure write access permission Each bit of the nsaid_wr_en register field is associated with a value on the NSAIDW signal as follows: Bit 16 Associated with NSAIDW = 0 + * | | |Bit 17 Associated with NSAIDW = 1 + * | | |Bit 18 Associated with NSAIDW = 2 + * | | |Bit 31 Associated with NSAIDW = 15 + * | | | is the filter unit number + * | | |When any bit in this field is set to 1, TZC-400 permits Non-secure write access to any access with the associated NSAIDW value + * | | |For example, if NSAIDW is 3 and the corresponding nsaid_wr_en[3] bit is set HIGH then TZC-400 permits the Non-secure write access to progress. + * @var TZC_T::REGION_BASE_LOW_6 + * Offset: 0x1C0 Controls the base address bits[31:12] of Region . + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[31:12] |base_address_low_n_|Controls the base address bits[31:12] of Region For Region 0, this field is read-only The TZC-400 sets the base address of Region 0 to 0x0 The TZC-400 only permits a region to start at a 4KB aligned address and address bits[11:0] are zeros. + * @var TZC_T::REGION_BASE_HIGH_6 + * Offset: 0x1C4 Reserved + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * @var TZC_T::REGION_TOP_LOW_6 + * Offset: 0x1C8 Controls the region top address bits[31:12] of Region . + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[31:12] |top_address_low_n_|Controls the region top address bits[31:12] of region This address points to the start of the next 4KB aligned address immediately outside the region. + * @var TZC_T::REGION_TOP_HIGH_6 + * Offset: 0x1CC Reserved + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * @var TZC_T::REGION_ATTRIBUTES_6 + * Offset: 0x1D0 Controls the permissions and target filter region enables. + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[3:0] |filter_en |Independent region enable for each filter unit Each bit is associated with a filter unit Set these bits as follows: Bit 0 For Filter 0 Bit 1 For Filter 1 Bit 2 For Filter 2 Bit 3 For Filter 3. When set HIGH, it enables the use of the current region programming for the associated filter For Region 0, all bits are set HIGH and cannot be modified. + * |[30] |s_rd_en |Secure global read enable This control bit defines the permissions for the Secure reads in the region Set this bit as follows: 0 Secure read to the region is not permitted 1 Permits Secure read to the region. + * |[31] |s_wr_en |Secure global write enable This control bit defines the permissions for the Secure writes in the region Set this bit as follows: 0 Secure write to the region is not permitted 1 Permits Secure write to the region. + * @var TZC_T::REGION_ID_ACCESS_6 + * Offset: 0x1D4 Controls the Non-secure access based on the NSAID inputs. + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[15:0] |nsaid_rd_en|NSAID read enables + * | | |This enables NSAID inputs to define Non-secure read access permission Each bit of the nsaid_rd_en register field is associated with a value on the NSAIDR signal as follows: Bit 0 Associated with NSAIDR = 0 + * | | |Bit 1 Associated with NSAIDR = 1 + * | | |Bit 2 Associated with NSAIDR = 2 + * | | |Bit 15 Associated with NSAIDR = 15 + * | | | is the filter unit number + * | | |When any bit in this field is set HIGH, TZC-400 permits Non-secure read access to any access with the associated NSAIDR value + * | | |For example, if NSAIDR is 3 and the corresponding nsaid_rd_en[3] bit is set HIGH then TZC-400 permits the Non-secure read access to progress. + * |[31:16] |nsaid_wr_en|NSAID write enables + * | | |This enables NSAID inputs to define Non-secure write access permission Each bit of the nsaid_wr_en register field is associated with a value on the NSAIDW signal as follows: Bit 16 Associated with NSAIDW = 0 + * | | |Bit 17 Associated with NSAIDW = 1 + * | | |Bit 18 Associated with NSAIDW = 2 + * | | |Bit 31 Associated with NSAIDW = 15 + * | | | is the filter unit number + * | | |When any bit in this field is set to 1, TZC-400 permits Non-secure write access to any access with the associated NSAIDW value + * | | |For example, if NSAIDW is 3 and the corresponding nsaid_wr_en[3] bit is set HIGH then TZC-400 permits the Non-secure write access to progress. + * @var TZC_T::REGION_BASE_LOW_7 + * Offset: 0x1E0 Controls the base address bits[31:12] of Region . + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[31:12] |base_address_low_n_|Controls the base address bits[31:12] of Region For Region 0, this field is read-only The TZC-400 sets the base address of Region 0 to 0x0 The TZC-400 only permits a region to start at a 4KB aligned address and address bits[11:0] are zeros. + * @var TZC_T::REGION_BASE_HIGH_7 + * Offset: 0x1E4 Reserved + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * @var TZC_T::REGION_TOP_LOW_7 + * Offset: 0x1E8 Controls the region top address bits[31:12] of Region . + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[31:12] |top_address_low_n_|Controls the region top address bits[31:12] of region This address points to the start of the next 4KB aligned address immediately outside the region. + * @var TZC_T::REGION_TOP_HIGH_7 + * Offset: 0x1EC Reserved + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * @var TZC_T::REGION_ATTRIBUTES_7 + * Offset: 0x1F0 Controls the permissions and target filter region enables. + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[3:0] |filter_en |Independent region enable for each filter unit Each bit is associated with a filter unit Set these bits as follows: Bit 0 For Filter 0 Bit 1 For Filter 1 Bit 2 For Filter 2 Bit 3 For Filter 3. When set HIGH, it enables the use of the current region programming for the associated filter For Region 0, all bits are set HIGH and cannot be modified. + * |[30] |s_rd_en |Secure global read enable This control bit defines the permissions for the Secure reads in the region Set this bit as follows: 0 Secure read to the region is not permitted 1 Permits Secure read to the region. + * |[31] |s_wr_en |Secure global write enable This control bit defines the permissions for the Secure writes in the region Set this bit as follows: 0 Secure write to the region is not permitted 1 Permits Secure write to the region. + * @var TZC_T::REGION_ID_ACCESS_7 + * Offset: 0x1F4 Controls the Non-secure access based on the NSAID inputs. + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[15:0] |nsaid_rd_en|NSAID read enables + * | | |This enables NSAID inputs to define Non-secure read access permission Each bit of the nsaid_rd_en register field is associated with a value on the NSAIDR signal as follows: Bit 0 Associated with NSAIDR = 0 + * | | |Bit 1 Associated with NSAIDR = 1 + * | | |Bit 2 Associated with NSAIDR = 2 + * | | |Bit 15 Associated with NSAIDR = 15 + * | | | is the filter unit number + * | | |When any bit in this field is set HIGH, TZC-400 permits Non-secure read access to any access with the associated NSAIDR value + * | | |For example, if NSAIDR is 3 and the corresponding nsaid_rd_en[3] bit is set HIGH then TZC-400 permits the Non-secure read access to progress. + * |[31:16] |nsaid_wr_en|NSAID write enables + * | | |This enables NSAID inputs to define Non-secure write access permission Each bit of the nsaid_wr_en register field is associated with a value on the NSAIDW signal as follows: Bit 16 Associated with NSAIDW = 0 + * | | |Bit 17 Associated with NSAIDW = 1 + * | | |Bit 18 Associated with NSAIDW = 2 + * | | |Bit 31 Associated with NSAIDW = 15 + * | | | is the filter unit number + * | | |When any bit in this field is set to 1, TZC-400 permits Non-secure write access to any access with the associated NSAIDW value + * | | |For example, if NSAIDW is 3 and the corresponding nsaid_wr_en[3] bit is set HIGH then TZC-400 permits the Non-secure write access to progress. + * @var TZC_T::REGION_BASE_LOW_8 + * Offset: 0x200 Controls the base address bits[31:12] of Region . + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[31:12] |base_address_low_n_|Controls the base address bits[31:12] of Region For Region 0, this field is read-only The TZC-400 sets the base address of Region 0 to 0x0 The TZC-400 only permits a region to start at a 4KB aligned address and address bits[11:0] are zeros. + * @var TZC_T::REGION_BASE_HIGH_8 + * Offset: 0x204 Reserved + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * @var TZC_T::REGION_TOP_LOW_8 + * Offset: 0x208 Controls the region top address bits[31:12] of Region . + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[31:12] |top_address_low_n_|Controls the region top address bits[31:12] of region This address points to the start of the next 4KB aligned address immediately outside the region. + * @var TZC_T::REGION_TOP_HIGH_8 + * Offset: 0x20C Reserved + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * @var TZC_T::REGION_ATTRIBUTES_8 + * Offset: 0x210 Controls the permissions and target filter region enables. + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[3:0] |filter_en |Independent region enable for each filter unit Each bit is associated with a filter unit Set these bits as follows: Bit 0 For Filter 0 Bit 1 For Filter 1 Bit 2 For Filter 2 Bit 3 For Filter 3. When set HIGH, it enables the use of the current region programming for the associated filter For Region 0, all bits are set HIGH and cannot be modified. + * |[30] |s_rd_en |Secure global read enable This control bit defines the permissions for the Secure reads in the region Set this bit as follows: 0 Secure read to the region is not permitted 1 Permits Secure read to the region. + * |[31] |s_wr_en |Secure global write enable This control bit defines the permissions for the Secure writes in the region Set this bit as follows: 0 Secure write to the region is not permitted 1 Permits Secure write to the region. + * @var TZC_T::REGION_ID_ACCESS_8 + * Offset: 0x214 Controls the Non-secure access based on the NSAID inputs. + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[15:0] |nsaid_rd_en|NSAID read enables + * | | |This enables NSAID inputs to define Non-secure read access permission Each bit of the nsaid_rd_en register field is associated with a value on the NSAIDR signal as follows: Bit 0 Associated with NSAIDR = 0 + * | | |Bit 1 Associated with NSAIDR = 1 + * | | |Bit 2 Associated with NSAIDR = 2 + * | | |Bit 15 Associated with NSAIDR = 15 + * | | | is the filter unit number + * | | |When any bit in this field is set HIGH, TZC-400 permits Non-secure read access to any access with the associated NSAIDR value + * | | |For example, if NSAIDR is 3 and the corresponding nsaid_rd_en[3] bit is set HIGH then TZC-400 permits the Non-secure read access to progress. + * |[31:16] |nsaid_wr_en|NSAID write enables + * | | |This enables NSAID inputs to define Non-secure write access permission Each bit of the nsaid_wr_en register field is associated with a value on the NSAIDW signal as follows: Bit 16 Associated with NSAIDW = 0 + * | | |Bit 17 Associated with NSAIDW = 1 + * | | |Bit 18 Associated with NSAIDW = 2 + * | | |Bit 31 Associated with NSAIDW = 15 + * | | | is the filter unit number + * | | |When any bit in this field is set to 1, TZC-400 permits Non-secure write access to any access with the associated NSAIDW value + * | | |For example, if NSAIDW is 3 and the corresponding nsaid_wr_en[3] bit is set HIGH then TZC-400 permits the Non-secure write access to progress. + * @var TZC_T::PID4 + * Offset: 0xFD0 Provides the following information about the peripheral configuration u2022 4KB_count. u2022 Jep106_c_code. + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[3:0] |jep106_c_code|The JEP106 continuation code value represents how many 0x7F continuation characters occur in the manufacturer identity code These bits read back as 0x4 For information on the JEP106 standard, see the Additional reading section. + * |[7:4] |4KB_count |The number of 4KB address blocks required to access the registers, expressed in powers of 2 These bits read back as 0x0 This means that the TZC-400 occupies a single 4KB address block. + * @var TZC_T::PID0 + * Offset: 0xFE0 The PID0 register provides the following information about the peripheral configuration: u2022 part_number_0. + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[7:0] |part_number_0|These bits read back as 0x60 + * @var TZC_T::PID1 + * Offset: 0xFE4 The PID1 register provides the following information about the peripheral configuration: u2022 part_number_1. u2022 Jep106_id_3_0. + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[3:0] |part_number_1|These bits read back as 0x4. + * |[7:4] |jep106_id_3_0|JEP106 identity code [3:0] See the JEP106, Standard Manufacturer Identification Code These bits read back as 0xB because ARM is the peripheral designer. + * @var TZC_T::PID2 + * Offset: 0xFE8 The PID2 register provides the following information about the peripheral configuration: u2022 Jep106_id_6_4. u2022 Revision number. u2022 JEDEC use flag. + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[2:0] |jep106_id_6_4|JEP106 identity code [6:4] See the JEP106, Standard Manufacturer Identification Code These bits read back as 0b011 because ARM is the peripheral designer. + * |[3] |jedec_used|This indicates that the TZC-400 uses a manufacturer identity code that was allocated by JEDEC according to JEP106 This bit always reads back as 0x1. + * |[7:4] |revision |Identifies the revision of the TZC-400 For revision r0p1, this field is set to 0x2. + * @var TZC_T::PID3 + * Offset: 0xFEC The PID3 register provides the following information about the peripheral configuration: u2022 Mod Number. u2022 RevAnd. + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[3:0] |mod_number|This is set to 0x0. + * |[7:4] |RevAnd |The top-level RTL provides a 4-bit input, USERPID3REVAND, that is normally tied LOW and provides a read value of 0x0 When silicon is available, and if metal fixes are required, the manufacturer can modify the tie-offs to indicate a revision of the silicon. + * @var TZC_T::CID0 + * Offset: 0xFF0 This is one of four 8-bit registers that together hold a 32-bit component ID value. + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[7:0] |comp_id_0 |These bits read back as 0x0D + * @var TZC_T::CID1 + * Offset: 0xFF4 This is one of four 8-bit registers, that together hold a 32-bit component ID value. + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[7:0] |comp_id_0 |These bits read back as 0xF0 + * @var TZC_T::CID2 + * Offset: 0xFF8 This is one of four 8-bit registers, that together hold a 32-bit component ID value. + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[7:0] |comp_id_2 |These bits read back as 0x05 + * @var TZC_T::CID3 + * Offset: 0xFFC This is one of four 8-bit registers that together hold a 32-bit component ID value. + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[7:0] |comp_id_3 |These bits read back as 0xB1 + */ + __I uint32_t BUILD_CONFIG; /*!< [0x0000] Provides information about the configuration of the TZC-400. */ + __IO uint32_t ACTION; /*!< [0x0004] Controls the interrupt and bus response signaling behavior of the TZC-400 when region permission failures occur. */ + __IO uint32_t GATE_KEEPER; /*!< [0x0008] Provides control and status for the gate keeper in each filter unit implemented */ + __IO uint32_t SPECULATION_CTRL; /*!< [0x000c] Controls the read access speculation and write access speculation. */ + __I uint32_t INT_STATUS; /*!< [0x0010] Contains the status of the interrupt signal, TZCINT, that reports access security violations or region overlap errors. */ + __O uint32_t INT_CLEAR; /*!< [0x0014] Clears the interrupt. */ + __I uint32_t RESERVE0[2]; + FAIL_STS_T FAIL[3]; /*!< [0x0020] Failed regions */ + __I uint32_t RESERVE1[44]; + + /*!< [0x0100] This register is read-only and is hard-wired to all zeros. */ + REGION_T REGION[9]; /*!< [0x0100] All structure regions in TZC. */ + __I uint32_t RESERVE10[876]; + __I uint32_t PID4; /*!< [0x0fd0] Provides the following information about the peripheral configuration u2022 4KB_count. u2022 Jep106_c_code. */ + __I uint32_t RESERVE11[3]; + __I uint32_t PID0; /*!< [0x0fe0] The PID0 register provides the following information about the peripheral configuration: u2022 part_number_0. */ + __I uint32_t PID1; /*!< [0x0fe4] The PID1 register provides the following information about the peripheral configuration: u2022 part_number_1. u2022 Jep106_id_3_0. */ + __I uint32_t PID2; /*!< [0x0fe8] The PID2 register provides the following information about the peripheral configuration: u2022 Jep106_id_6_4. u2022 Revision number. u2022 JEDEC use flag. */ + __I uint32_t PID3; /*!< [0x0fec] The PID3 register provides the following information about the peripheral configuration: u2022 Mod Number. u2022 RevAnd. */ + __I uint32_t CID0; /*!< [0x0ff0] This is one of four 8-bit registers that together hold a 32-bit component ID value. */ + __I uint32_t CID1; /*!< [0x0ff4] This is one of four 8-bit registers, that together hold a 32-bit component ID value. */ + __I uint32_t CID2; /*!< [0x0ff8] This is one of four 8-bit registers, that together hold a 32-bit component ID value. */ + __I uint32_t CID3; /*!< [0x0ffc] This is one of four 8-bit registers that together hold a 32-bit component ID value. */ + +} TZC_T; + +/** + @addtogroup TZC_CONST TZC Bit Field Definition + Constant Definitions for TZC Controller +@{ */ + +#define TZC_BUILD_CONFIG_no_of_regions_Pos (0) /*!< TZC_T::BUILD_CONFIG: no_of_regions Position*/ +#define TZC_BUILD_CONFIG_no_of_regions_Msk (0x1ful << TZC_BUILD_CONFIG_no_of_regions_Pos) /*!< TZC_T::BUILD_CONFIG: no_of_regions Mask*/ + +#define TZC_BUILD_CONFIG_address_width_Pos (8) /*!< TZC_T::BUILD_CONFIG: address_width Position*/ +#define TZC_BUILD_CONFIG_address_width_Msk (0x3ful << TZC_BUILD_CONFIG_address_width_Pos) /*!< TZC_T::BUILD_CONFIG: address_width Mask*/ + +#define TZC_BUILD_CONFIG_no_of_filters_Pos (24) /*!< TZC_T::BUILD_CONFIG: no_of_filters Position*/ +#define TZC_BUILD_CONFIG_no_of_filters_Msk (0x3ul << TZC_BUILD_CONFIG_no_of_filters_Pos) /*!< TZC_T::BUILD_CONFIG: no_of_filters Mask*/ + +#define TZC_ACTION_reaction_value_Pos (0) /*!< TZC_T::ACTION: reaction_value Position*/ +#define TZC_ACTION_reaction_value_Msk (0x3ul << TZC_ACTION_reaction_value_Pos) /*!< TZC_T::ACTION: reaction_value Mask */ + +#define TZC_GATE_KEEPER_open_request_Pos (0) /*!< TZC_T::GATE_KEEPER: open_request Position*/ +#define TZC_GATE_KEEPER_open_request_Msk (0xful << TZC_GATE_KEEPER_open_request_Pos) /*!< TZC_T::GATE_KEEPER: open_request Mask */ + +#define TZC_GATE_KEEPER_open_status_Pos (16) /*!< TZC_T::GATE_KEEPER: open_status Position*/ +#define TZC_GATE_KEEPER_open_status_Msk (0xful << TZC_GATE_KEEPER_open_status_Pos) /*!< TZC_T::GATE_KEEPER: open_status Mask */ + +#define TZC_SPECULATION_CTRL_read_spec_disable_Pos (0) /*!< TZC_T::SPECULATION_CTRL: read_spec_disable Position*/ +#define TZC_SPECULATION_CTRL_read_spec_disable_Msk (0x1ul << TZC_SPECULATION_CTRL_read_spec_disable_Pos) /*!< TZC_T::SPECULATION_CTRL: read_spec_disable Mask*/ + +#define TZC_SPECULATION_CTRL_write_spec_disable_Pos (1) /*!< TZC_T::SPECULATION_CTRL: write_spec_disable Position*/ +#define TZC_SPECULATION_CTRL_write_spec_disable_Msk (0x1ul << TZC_SPECULATION_CTRL_write_spec_disable_Pos) /*!< TZC_T::SPECULATION_CTRL: write_spec_disable Mask*/ + +#define TZC_INT_STATUS_status_Pos (0) /*!< TZC_T::INT_STATUS: status Position */ +#define TZC_INT_STATUS_status_Msk (0xful << TZC_INT_STATUS_status_Pos) /*!< TZC_T::INT_STATUS: status Mask */ + +#define TZC_INT_STATUS_overrun_Pos (8) /*!< TZC_T::INT_STATUS: overrun Position */ +#define TZC_INT_STATUS_overrun_Msk (0xful << TZC_INT_STATUS_overrun_Pos) /*!< TZC_T::INT_STATUS: overrun Mask */ + +#define TZC_INT_STATUS_overlap_Pos (16) /*!< TZC_T::INT_STATUS: overlap Position */ +#define TZC_INT_STATUS_overlap_Msk (0xful << TZC_INT_STATUS_overlap_Pos) /*!< TZC_T::INT_STATUS: overlap Mask */ + +#define TZC_INT_CLEAR_clear_Pos (0) /*!< TZC_T::INT_CLEAR: clear Position */ +#define TZC_INT_CLEAR_clear_Msk (0xful << TZC_INT_CLEAR_clear_Pos) /*!< TZC_T::INT_CLEAR: clear Mask */ + +#define TZC_FAIL_ADDRESS_LOW_addr_status_low_Pos (0) /*!< TZC_T::FAIL_ADDRESS_LOW: addr_status_low Position*/ +#define TZC_FAIL_ADDRESS_LOW_addr_status_low_Msk (0xfffffffful << TZC_FAIL_ADDRESS_LOW_addr_status_low_Pos) /*!< TZC_T::FAIL_ADDRESS_LOW: addr_status_low Mask*/ + +#define TZC_FAIL_CONTROL_Privileged_Pos (20) /*!< TZC_T::FAIL_CONTROL: Privileged Position*/ +#define TZC_FAIL_CONTROL_Privileged_Msk (0x1ul << TZC_FAIL_CONTROL_Privileged_Pos) /*!< TZC_T::FAIL_CONTROL: Privileged Mask*/ + +#define TZC_FAIL_CONTROL_Non_secure_Pos (21) /*!< TZC_T::FAIL_CONTROL: Non_secure Position*/ +#define TZC_FAIL_CONTROL_Non_secure_Msk (0x1ul << TZC_FAIL_CONTROL_Non_secure_Pos) /*!< TZC_T::FAIL_CONTROL: Non_secure Mask*/ + +#define TZC_FAIL_CONTROL_Direction_Pos (24) /*!< TZC_T::FAIL_CONTROL: Direction Position*/ +#define TZC_FAIL_CONTROL_Direction_Msk (0x1ul << TZC_FAIL_CONTROL_Direction_Pos) /*!< TZC_T::FAIL_CONTROL: Direction Mask */ + +#define TZC_FAIL_ID_id_Pos (0) /*!< TZC_T::FAIL_ID: id Position */ +#define TZC_FAIL_ID_id_Msk (0x3ful << TZC_FAIL_ID_id_Pos) /*!< TZC_T::FAIL_ID: id Mask */ + +#define TZC_FAIL_ID_vnet_Pos (24) /*!< TZC_T::FAIL_ID: vnet Position */ +#define TZC_FAIL_ID_vnet_Msk (0xful << TZC_FAIL_ID_vnet_Pos) /*!< TZC_T::FAIL_ID: vnet Mask */ + +#define TZC_REGION_BASE_LOW_base_address_low_n_Pos (12) /*!< TZC_T::REGION_BASE_LOW: base_address_low_n_ Position*/ +#define TZC_REGION_BASE_LOW_base_address_low_n_Msk (0xffffful << TZC_REGION_BASE_LOW_base_address_low_n_Pos) /*!< TZC_T::REGION_BASE_LOW: base_address_low_n_ Mask*/ + +#define TZC_REGION_TOP_LOW_top_address_low_n_Pos (12) /*!< TZC_T::REGION_TOP_LOW: top_address_low_n_ Position*/ +#define TZC_REGION_TOP_LOW_top_address_low_n_Msk (0xffffful << TZC_REGION_TOP_LOW_top_address_low_n_Pos) /*!< TZC_T::REGION_TOP_LOW: top_address_low_n_ Mask*/ + +#define TZC_REGION_ATTRIBUTES_filter_en_Pos (0) /*!< TZC_T::REGION_ATTRIBUTES: filter_en Position*/ +#define TZC_REGION_ATTRIBUTES_filter_en_Msk (0xful << TZC_REGION_ATTRIBUTES_filter_en_Pos) /*!< TZC_T::REGION_ATTRIBUTES: filter_en Mask*/ + +#define TZC_REGION_ATTRIBUTES_s_rd_en_Pos (30) /*!< TZC_T::REGION_ATTRIBUTES: s_rd_en Position*/ +#define TZC_REGION_ATTRIBUTES_s_rd_en_Msk (0x1ul << TZC_REGION_ATTRIBUTES_s_rd_en_Pos) /*!< TZC_T::REGION_ATTRIBUTES: s_rd_en Mask*/ + +#define TZC_REGION_ATTRIBUTES_s_wr_en_Pos (31) /*!< TZC_T::REGION_ATTRIBUTES: s_wr_en Position*/ +#define TZC_REGION_ATTRIBUTES_s_wr_en_Msk (0x1ul << TZC_REGION_ATTRIBUTES_s_wr_en_Pos) /*!< TZC_T::REGION_ATTRIBUTES: s_wr_en Mask*/ + +#define TZC_REGION_ID_ACCESS_nsaid_rd_en_Pos (0) /*!< TZC_T::REGION_ID_ACCESS: nsaid_rd_en Position*/ +#define TZC_REGION_ID_ACCESS_nsaid_rd_en_Msk (0xfffful << TZC_REGION_ID_ACCESS_nsaid_rd_en_Pos) /*!< TZC_T::REGION_ID_ACCESS: nsaid_rd_en Mask*/ + +#define TZC_REGION_ID_ACCESS_nsaid_wr_en_Pos (16) /*!< TZC_T::REGION_ID_ACCESS: nsaid_wr_en Position*/ +#define TZC_REGION_ID_ACCESS_nsaid_wr_en_Msk (0xfffful << TZC_REGION_ID_ACCESS_nsaid_wr_en_Pos) /*!< TZC_T::REGION_ID_ACCESS: nsaid_wr_en Mask*/ + +#define TZC_PID4_jep106_c_code_Pos (0) /*!< TZC_T::PID4: jep106_c_code Position */ +#define TZC_PID4_jep106_c_code_Msk (0xful << TZC_PID4_jep106_c_code_Pos) /*!< TZC_T::PID4: jep106_c_code Mask */ + +#define TZC_PID4_4KB_count_Pos (4) /*!< TZC_T::PID4: 4KB_count Position */ +#define TZC_PID4_4KB_count_Msk (0xful << TZC_PID4_4KB_count_Pos) /*!< TZC_T::PID4: 4KB_count Mask */ + +#define TZC_PID0_part_number_0_Pos (0) /*!< TZC_T::PID0: part_number_0 Position */ +#define TZC_PID0_part_number_0_Msk (0xfful << TZC_PID0_part_number_0_Pos) /*!< TZC_T::PID0: part_number_0 Mask */ + +#define TZC_PID1_part_number_1_Pos (0) /*!< TZC_T::PID1: part_number_1 Position */ +#define TZC_PID1_part_number_1_Msk (0xful << TZC_PID1_part_number_1_Pos) /*!< TZC_T::PID1: part_number_1 Mask */ + +#define TZC_PID1_jep106_id_3_0_Pos (4) /*!< TZC_T::PID1: jep106_id_3_0 Position */ +#define TZC_PID1_jep106_id_3_0_Msk (0xful << TZC_PID1_jep106_id_3_0_Pos) /*!< TZC_T::PID1: jep106_id_3_0 Mask */ + +#define TZC_PID2_jep106_id_6_4_Pos (0) /*!< TZC_T::PID2: jep106_id_6_4 Position */ +#define TZC_PID2_jep106_id_6_4_Msk (0x7ul << TZC_PID2_jep106_id_6_4_Pos) /*!< TZC_T::PID2: jep106_id_6_4 Mask */ + +#define TZC_PID2_jedec_used_Pos (3) /*!< TZC_T::PID2: jedec_used Position */ +#define TZC_PID2_jedec_used_Msk (0x1ul << TZC_PID2_jedec_used_Pos) /*!< TZC_T::PID2: jedec_used Mask */ + +#define TZC_PID2_revision_Pos (4) /*!< TZC_T::PID2: revision Position */ +#define TZC_PID2_revision_Msk (0xful << TZC_PID2_revision_Pos) /*!< TZC_T::PID2: revision Mask */ + +#define TZC_PID3_mod_number_Pos (0) /*!< TZC_T::PID3: mod_number Position */ +#define TZC_PID3_mod_number_Msk (0xful << TZC_PID3_mod_number_Pos) /*!< TZC_T::PID3: mod_number Mask */ + +#define TZC_PID3_RevAnd_Pos (4) /*!< TZC_T::PID3: RevAnd Position */ +#define TZC_PID3_RevAnd_Msk (0xful << TZC_PID3_RevAnd_Pos) /*!< TZC_T::PID3: RevAnd Mask */ + +#define TZC_CID0_comp_id_0_Pos (0) /*!< TZC_T::CID0: comp_id_0 Position */ +#define TZC_CID0_comp_id_0_Msk (0xfful << TZC_CID0_comp_id_0_Pos) /*!< TZC_T::CID0: comp_id_0 Mask */ + +#define TZC_CID1_comp_id_0_Pos (0) /*!< TZC_T::CID1: comp_id_0 Position */ +#define TZC_CID1_comp_id_0_Msk (0xfful << TZC_CID1_comp_id_0_Pos) /*!< TZC_T::CID1: comp_id_0 Mask */ + +#define TZC_CID2_comp_id_2_Pos (0) /*!< TZC_T::CID2: comp_id_2 Position */ +#define TZC_CID2_comp_id_2_Msk (0xfful << TZC_CID2_comp_id_2_Pos) /*!< TZC_T::CID2: comp_id_2 Mask */ + +#define TZC_CID3_comp_id_3_Pos (0) /*!< TZC_T::CID3: comp_id_3 Position */ +#define TZC_CID3_comp_id_3_Msk (0xfful << TZC_CID3_comp_id_3_Pos) /*!< TZC_T::CID3: comp_id_3 Mask */ + +/**@}*/ /* TZC_CONST */ +/**@}*/ /* end of TZC register group */ +/**@}*/ /* end of REGISTER group */ + +#if defined ( __CC_ARM ) + #pragma no_anon_unions +#endif + +#endif /* __SSMCC_REG_H__ */ diff --git a/bsp/nuvoton/libraries/ma35/Device/Nuvoton/MA35D1/Include/sspcc_reg.h b/bsp/nuvoton/libraries/ma35/Device/Nuvoton/MA35D1/Include/sspcc_reg.h new file mode 100644 index 0000000000..5e466df022 --- /dev/null +++ b/bsp/nuvoton/libraries/ma35/Device/Nuvoton/MA35D1/Include/sspcc_reg.h @@ -0,0 +1,2625 @@ +/**************************************************************************//** + * @file sspcc_reg.h + * @brief SSPCC register definition header file + * + * SPDX-License-Identifier: Apache-2.0 + * @copyright (C) 2021 Nuvoton Technology Corp. All rights reserved. + *****************************************************************************/ +#ifndef __SSPCC_REG_H__ +#define __SSPCC_REG_H__ + +#if defined ( __CC_ARM ) + #pragma anon_unions +#endif + + +/******************************************************************************/ +/* Device Specific Peripheral registers structures */ +/******************************************************************************/ + +/** @addtogroup REGISTER Control Register + + @{ + +*/ + +/*---------------------- System Security Peripheral Configuration Controller -------------------------*/ +/** + @addtogroup SSPCC System Security Peripheral Configuration Controller(SSPCC) + Memory Mapped Structure for SSPCC Controller +@{ */ + +typedef struct +{ + + + /** + * @var SSPCC_T::PSSET0 + * Offset: 0x00 Peripheral Security Attribution Set Register 0 (0x4000_0000~0x400F_FFFF) + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[17:16] |PDMA0 |PDMA0 Security Attribution Bits + * | | |00 = Set to TZS. + * | | |01 = Set to TZNS. + * | | |10 = Reserved. + * | | |11 = Reserved. + * |[19:18] |PDMA1 |PDMA1 Security Attribution Bits + * | | |00 = Set to TZS. + * | | |01 = Set to TZNS. + * | | |10 = Reserved. + * | | |11 = Reserved. + * |[21:20] |PDMA2 |PDMA2 Security Attribution Bits + * | | |00 = Reserved. + * | | |01 = Set to TZNS. + * | | |10 = Reserved. + * | | |11 = Set to SubM. + * |[23:22] |PDMA3 |PDMA3 Security Attribution Bits + * | | |00 = Reserved. + * | | |01 = Set to TZNS. + * | | |10 = Reserved. + * | | |11 = Set to SubM. + * @var SSPCC_T::PSSET1 + * Offset: 0x04 Peripheral Security Attribution Set Register 1 (0x4010_0000~0x401F_FFFF) + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[1:0] |EBI |EBI Controller Security Attribution Bits + * | | |00 = Reserved. + * | | |01 = Set to TZNS. + * | | |10 = Reserved. + * | | |11 = Set to SubM. + * |[17:16] |SDH0 |SD Host 0 Security Attribution Bits + * | | |00 = Set to TZS. + * | | |01 = Set to TZNS. + * | | |10 = Reserved. + * | | |11 = Reserved. + * |[19:18] |SDH1 |SD Host 1 Security Attribution Bits + * | | |00 = Set to TZS. + * | | |01 = Set to TZNS. + * | | |10 = Reserved. + * | | |11 = Reserved. + * |[21:20] |NANDC |NAND Controller Security Attribution Bits + * | | |00 = Set to TZS. + * | | |01 = Set to TZNS. + * | | |10 = Reserved. + * | | |11 = Reserved. + * @var SSPCC_T::PSSET2 + * Offset: 0x08 Peripheral Security Attribution Set Register 2 (0x4020_0000~0x402F_FFFF) + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[1:0] |HSUSBD |HS USB Device Security Attribution Bits + * | | |00 = Set to TZS. + * | | |01 = Set to TZNS. + * | | |10 = Reserved. + * | | |11 = Reserved. + * @var SSPCC_T::PSSET3 + * Offset: 0x0C Peripheral Security Attribution Set Register 3 (0x4030_0000~0x403F_FFFF) + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[1:0] |CRYPTO |Crypto Accelerator Security Attribution Bits + * | | |00 = Set to TZS. + * | | |01 = Set to TZNS. + * | | |10 = Reserved. + * | | |11 = Reserved. + * |[25:24] |CANFD0 |CANFD0 Security Attribution Bits + * | | |00 = Reserved. + * | | |01 = Set to TZNS. + * | | |10 = Reserved. + * | | |11 = Set to SubM. + * |[27:26] |CANFD1 |CANFD1 Security Attribution Bits + * | | |00 = Reserved. + * | | |01 = Set to TZNS. + * | | |10 = Reserved. + * | | |11 = Set to SubM. + * |[29:28] |CANFD2 |CANFD2 Security Attribution Bits + * | | |00 = Reserved. + * | | |01 = Set to TZNS. + * | | |10 = Reserved. + * | | |11 = Set to SubM. + * |[31:30] |CANFD3 |CANFD3 Security Attribution Bits + * | | |00 = Reserved. + * | | |01 = Set to TZNS. + * | | |10 = Reserved. + * | | |11 = Set to SubM. + * @var SSPCC_T::PSSET4 + * Offset: 0x10 Peripheral Security Attribution Set Register 4 (0x4040_0000~0x404F_FFFF) + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[5:4] |ADC0 |ADC 0 Security Attribution Bits + * | | |00 = Reserved. + * | | |01 = Set to TZNS. + * | | |10 = Reserved. + * | | |11 = Set to SubM. + * |[7:6] |EADC0 |EADC 0 Security Attribution Bits + * | | |00 = Reserved. + * | | |01 = Set to TZNS. + * | | |10 = Reserved. + * | | |11 = Set to SubM. + * |[9:8] |WDTWWDT1 |WDTWWDT1 Security Attribution Bits + * | | |00 = Set to TZS. + * | | |01 = Set to TZNS. + * | | |10 = Reserved. + * | | |11 = Reserved. + * |[17:16] |I2S0 |I2S 0 Security Attribution Bits + * | | |00 = Reserved. + * | | |01 = Set to TZNS. + * | | |10 = Reserved. + * | | |11 = Set to SubM. + * |[19:18] |I2S1 |I2S 1 Security Attribution Bits + * | | |00 = Reserved. + * | | |01 = Set to TZNS. + * | | |10 = Reserved. + * | | |11 = Set to SubM. + * |[21:20] |KPI |KPI Security Attribution Bits + * | | |00 = Reserved. + * | | |01 = Set to TZNS. + * | | |10 = Reserved. + * | | |11 = Set to SubM. + * |[25:24] |DDRPHYPUB |DDR PHY Security Attribution Bits + * | | |00 = Set to TZS. + * | | |01 = Set to TZNS. + * | | |10 = Reserved. + * | | |11 = Reserved. + * |[27:26] |MCTL |DRAM Controller Security Attribution Bits + * | | |00 = Set to TZS. + * | | |01 = Set to TZNS. + * | | |10 = Reserved. + * | | |11 = Reserved. + * @var SSPCC_T::PSSET5 + * Offset: 0x14 Peripheral Security Attribution Set Register 5 (0x4050_0000~0x405F_FFFF) + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[1:0] |TMR01 |TMR01 Security Attribution Bits + * | | |00 = Set to TZS. + * | | |01 = Set to TZNS. + * | | |10 = Reserved. + * | | |11 = Reserved. + * |[3:2] |TMR23 |TMR23 Security Attribution Bits + * | | |00 = Reserved. + * | | |01 = Set to TZNS. + * | | |10 = Reserved. + * | | |11 = Set to SubM. + * |[5:4] |TMR45 |TMR45 Security Attribution Bits + * | | |00 = Reserved. + * | | |01 = Set to TZNS. + * | | |10 = Reserved. + * | | |11 = Set to SubM. + * |[7:6] |TMR67 |TMR67 Security Attribution Bits + * | | |00 = Reserved. + * | | |01 = Set to TZNS. + * | | |10 = Reserved. + * | | |11 = Set to SubM. + * |[9:8] |TMR89 |TMR89 Security Attribution Bits + * | | |00 = Reserved. + * | | |01 = Set to TZNS. + * | | |10 = Reserved. + * | | |11 = Set to SubM. + * |[11:10] |TMR1011 |TMR1011 Security Attribution Bits + * | | |00 = Reserved. + * | | |01 = Set to TZNS. + * | | |10 = Reserved. + * | | |11 = Set to SubM. + * |[17:16] |EPWM0 |EPWM 0 Security Attribution Bits + * | | |00 = Reserved. + * | | |01 = Set to TZNS. + * | | |10 = Reserved. + * | | |11 = Set to SubM. + * |[19:18] |EPWM1 |EPWM 1 Security Attribution Bits + * | | |00 = Reserved. + * | | |01 = Set to TZNS. + * | | |10 = Reserved. + * | | |11 = Set to SubM. + * |[21:20] |EPWM2 |EPWM 2 Security Attribution Bits + * | | |00 = Reserved. + * | | |01 = Set to TZNS. + * | | |10 = Reserved. + * | | |11 = Set to SubM. + * @var SSPCC_T::PSSET6 + * Offset: 0x18 Peripheral Security Attribution Set Register 6 (0x4060_0000~0x406F_FFFF) + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[1:0] |SPI0 |SPI0 Security Attribution Bits + * | | |00 = Reserved. + * | | |01 = Set to TZNS. + * | | |10 = Reserved. + * | | |11 = Set to SubM. + * |[3:2] |SPI1 |SPI1 Security Attribution Bits + * | | |00 = Reserved. + * | | |01 = Set to TZNS. + * | | |10 = Reserved. + * | | |11 = Set to SubM. + * |[5:4] |SPI2 |SPI2 Security Attribution Bits + * | | |00 = Reserved. + * | | |01 = Set to TZNS. + * | | |10 = Reserved. + * | | |11 = Set to SubM. + * |[7:6] |SPI3 |SPI3 Security Attribution Bits + * | | |00 = Reserved. + * | | |01 = Set to TZNS. + * | | |10 = Reserved. + * | | |11 = Set to SubM. + * |[17:16] |QSPI0 |QSPI0 Security Attribution Bits + * | | |00 = Set to TZS. + * | | |01 = Set to TZNS. + * | | |10 = Reserved. + * | | |11 = Reserved. + * |[19:18] |QSPI1 |QSPI1 Security Attribution Bits + * | | |00 = Reserved. + * | | |01 = Set to TZNS. + * | | |10 = Reserved. + * | | |11 = Set to SubM. + * @var SSPCC_T::PSSET7 + * Offset: 0x1C Peripheral Security Attribution Set Register 7 (0x4070_0000~0x407F_FFFF) + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[1:0] |UART0 |UART0 Security Attribution Bits + * | | |00 = Set to TZS. + * | | |01 = Set to TZNS. + * | | |10 = Reserved. + * | | |11 = Reserved. + * |[3:2] |UART1 |UART1 Security Attribution Bits + * | | |00 = Reserved. + * | | |01 = Set to TZNS. + * | | |10 = Reserved. + * | | |11 = Set to SubM. + * |[5:4] |UART2 |UART2 Security Attribution Bits + * | | |00 = Reserved. + * | | |01 = Set to TZNS. + * | | |10 = Reserved. + * | | |11 = Set to SubM. + * |[7:6] |UART3 |UART3 Security Attribution Bits + * | | |00 = Reserved. + * | | |01 = Set to TZNS. + * | | |10 = Reserved. + * | | |11 = Set to SubM. + * |[9:8] |UART4 |UART4 Security Attribution Bits + * | | |00 = Reserved. + * | | |01 = Set to TZNS. + * | | |10 = Reserved. + * | | |11 = Set to SubM. + * |[11:10] |UART5 |UART5 Security Attribution Bits + * | | |00 = Reserved. + * | | |01 = Set to TZNS. + * | | |10 = Reserved. + * | | |11 = Set to SubM. + * |[13:12] |UART6 |UART6 Security Attribution Bits + * | | |00 = Reserved. + * | | |01 = Set to TZNS. + * | | |10 = Reserved. + * | | |11 = Set to SubM. + * |[15:14] |UART7 |UART7 Security Attribution Bits + * | | |00 = Reserved. + * | | |01 = Set to TZNS. + * | | |10 = Reserved. + * | | |11 = Set to SubM. + * |[17:16] |UART8 |UART8 Security Attribution Bits + * | | |00 = Reserved. + * | | |01 = Set to TZNS. + * | | |10 = Reserved. + * | | |11 = Set to SubM. + * |[19:18] |UART9 |UART9 Security Attribution Bits + * | | |00 = Reserved. + * | | |01 = Set to TZNS. + * | | |10 = Reserved. + * | | |11 = Set to SubM. + * |[21:20] |UART10 |UART10 Security Attribution Bits + * | | |00 = Reserved. + * | | |01 = Set to TZNS. + * | | |10 = Reserved. + * | | |11 = Set to SubM. + * |[23:22] |UART11 |UART11 Security Attribution Bits + * | | |00 = Reserved. + * | | |01 = Set to TZNS. + * | | |10 = Reserved. + * | | |11 = Set to SubM. + * |[25:24] |UART12 |UART12 Security Attribution Bits + * | | |00 = Reserved. + * | | |01 = Set to TZNS. + * | | |10 = Reserved. + * | | |11 = Set to SubM. + * |[27:26] |UART13 |UART13 Security Attribution Bits + * | | |00 = Reserved. + * | | |01 = Set to TZNS. + * | | |10 = Reserved. + * | | |11 = Set to SubM. + * |[29:28] |UART14 |UART14 Security Attribution Bits + * | | |00 = Reserved. + * | | |01 = Set to TZNS. + * | | |10 = Reserved. + * | | |11 = Set to SubM. + * |[31:30] |UART15 |UART15 Security Attribution Bits + * | | |00 = Reserved. + * | | |01 = Set to TZNS. + * | | |10 = Reserved. + * | | |11 = Set to SubM. + * @var SSPCC_T::PSSET8 + * Offset: 0x20 Peripheral Security Attribution Set Register 8 (0x4080_0000~0x408F_FFFF) + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[1:0] |I2C0 |I2C0 Security Attribution Bits + * | | |00 = Set to TZS. + * | | |01 = Set to TZNS. + * | | |10 = Reserved. + * | | |11 = Reserved. + * |[3:2] |I2C1 |I2C1 Security Attribution Bits + * | | |00 = Reserved. + * | | |01 = Set to TZNS. + * | | |10 = Reserved. + * | | |11 = Set to SubM. + * |[5:4] |I2C2 |I2C2 Security Attribution Bits + * | | |00 = Reserved. + * | | |01 = Set to TZNS. + * | | |10 = Reserved. + * | | |11 = Set to SubM. + * |[7:6] |I2C3 |I2C3 Security Attribution Bits + * | | |00 = Reserved. + * | | |01 = Set to TZNS. + * | | |10 = Reserved. + * | | |11 = Set to SubM. + * |[9:8] |I2C4 |I2C4 Security Attribution Bits + * | | |00 = Reserved. + * | | |01 = Set to TZNS. + * | | |10 = Reserved. + * | | |11 = Set to SubM. + * |[11:10] |I2C5 |I2C5 Security Attribution Bits + * | | |00 = Reserved. + * | | |01 = Set to TZNS. + * | | |10 = Reserved. + * | | |11 = Set to SubM. + * |[17:16] |UART16 |UART16 Security Attribution Bits + * | | |00 = Reserved. + * | | |01 = Set to TZNS. + * | | |10 = Reserved. + * | | |11 = Set to SubM. + * @var SSPCC_T::PSSET9 + * Offset: 0x24 Peripheral Security Attribution Set Register 9 (0x4090_0000~0x409F_FFFF) + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[1:0] |SC0 |SC0 Security Attribution Bits + * | | |00 = Reserved. + * | | |01 = Set to TZNS. + * | | |10 = Reserved. + * | | |11 = Set to SubM. + * |[3:2] |SC1 |SC1 Security Attribution Bits + * | | |00 = Reserved. + * | | |01 = Set to TZNS. + * | | |10 = Reserved. + * | | |11 = Set to SubM. + * @var SSPCC_T::PSSET10 + * Offset: 0x28 Peripheral Security Attribution Set Register 10 (0x40A0_0000~0x40AF_FFFF) + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * @var SSPCC_T::PSSET11 + * Offset: 0x2C Peripheral Security Attribution Set Register 11 (0x40B0_0000~0x40BF_FFFF) + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[1:0] |QEI0 |QEI0 Security Attribution Bits + * | | |00 = Reserved. + * | | |01 = Set to TZNS. + * | | |10 = Reserved. + * | | |11 = Set to SubM. + * |[3:2] |QEI1 |QEI1 Security Attribution Bits + * | | |00 = Reserved. + * | | |01 = Set to TZNS. + * | | |10 = Reserved. + * | | |11 = Set to SubM. + * |[5:4] |QEI2 |QEI2 Security Attribution Bits + * | | |00 = Reserved. + * | | |01 = Set to TZNS. + * | | |10 = Reserved. + * | | |11 = Set to SubM. + * |[9:8] |ECAP0 |ECAP0 Security Attribution Bits + * | | |00 = Reserved. + * | | |01 = Set to TZNS. + * | | |10 = Reserved. + * | | |11 = Set to SubM. + * |[11:10] |ECAP1 |ECAP1 Security Attribution Bits + * | | |00 = Reserved. + * | | |01 = Set to TZNS. + * | | |10 = Reserved. + * | | |11 = Set to SubM. + * |[13:12] |ECAP2 |ECAP2 Security Attribution Bits + * | | |00 = Reserved. + * | | |01 = Set to TZNS. + * | | |10 = Reserved. + * | | |11 = Set to SubM. + * |[19:18] |TRNG |TRNG Security Attribution Bits + * | | |00 = Set to TZS. + * | | |01 = Set to TZNS. + * | | |10 = Reserved. + * | | |11 = Reserved. + * @var SSPCC_T::SRAMSB + * Offset: 0x40 SRAM Security Boundary Set Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[4:0] |SR0BOUND |Set SRAM0 Security Boundary + * | | |Set the 16 Kbytes-aligned boundary of SRAM0. + * | | |The SRAM part below the boundary is SubM region and the part higher the boundary is ShareMemory region. + * | | |When the boundary is set to higher than the size of SRAM, the whole SRAM is SubM region. + * |[12:8] |SR1BOUND |Set SRAM1 Security Boundary + * | | |Set the 16 Kbytes-aligned boundary of data SRAM. + * | | |The SRAM part below the boundary is TZS region and the part higher the boundary is TZNS region. + * | | |When the boundary is set to higher than the size of SRAM, the whole SRAM is TZS region. + * @var SSPCC_T::EBISSET + * Offset: 0x50 EBI Memory Security Set Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[1:0] |BANK0 |EBI Memory Bank0 Security Attribution Bits + * | | |00 = Reserved. + * | | |01 = Set to TZNS. + * | | |10 = Reserved. + * | | |11 = Set to SubM. + * |[3:2] |BANK1 |EBI Memory Bank1 Security Attribution Bits + * | | |00 = Reserved. + * | | |01 = Set to TZNS. + * | | |10 = Reserved. + * | | |11 = Set to SubM. + * |[5:4] |BANK2 |EBI Memory Bank2 Security Attribution Bits + * | | |00 = Reserved. + * | | |01 = Set to TZNS. + * | | |10 = Reserved. + * | | |11 = Set to SubM. + * @var SSPCC_T::IOASSET + * Offset: 0x60 GPIO Port A Security Attribution Set Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[1:0] |PIN0 |GPIO Pin 0 Security Attribution Bits + * | | |00 = Set to TZS. + * | | |01 = Set to TZNS. + * | | |10 = Reserved. + * | | |11 = Set to SubM. + * |[3:2] |PIN1 |GPIO Pin 1 Security Attribution Bits + * | | |00 = Set to TZS. + * | | |01 = Set to TZNS. + * | | |10 = Reserved. + * | | |11 = Set to SubM. + * |[5:4] |PIN2 |GPIO Pin 2 Security Attribution Bits + * | | |00 = Set to TZS. + * | | |01 = Set to TZNS. + * | | |10 = Reserved. + * | | |11 = Set to SubM. + * |[7:6] |PIN3 |GPIO Pin 3 Security Attribution Bits + * | | |00 = Set to TZS. + * | | |01 = Set to TZNS. + * | | |10 = Reserved. + * | | |11 = Set to SubM. + * |[9:8] |PIN4 |GPIO Pin 4 Security Attribution Bits + * | | |00 = Set to TZS. + * | | |01 = Set to TZNS. + * | | |10 = Reserved. + * | | |11 = Set to SubM. + * |[11:10] |PIN5 |GPIO Pin 5 Security Attribution Bits + * | | |00 = Set to TZS. + * | | |01 = Set to TZNS. + * | | |10 = Reserved. + * | | |11 = Set to SubM. + * |[13:12] |PIN6 |GPIO Pin 6 Security Attribution Bits + * | | |00 = Set to TZS. + * | | |01 = Set to TZNS. + * | | |10 = Reserved. + * | | |11 = Set to SubM. + * |[15:14] |PIN7 |GPIO Pin 7 Security Attribution Bits + * | | |00 = Set to TZS. + * | | |01 = Set to TZNS. + * | | |10 = Reserved. + * | | |11 = Set to SubM. + * |[17:16] |PIN8 |GPIO Pin 8 Security Attribution Bits + * | | |00 = Set to TZS. + * | | |01 = Set to TZNS. + * | | |10 = Reserved. + * | | |11 = Set to SubM. + * |[19:18] |PIN9 |GPIO Pin 9 Security Attribution Bits + * | | |00 = Set to TZS. + * | | |01 = Set to TZNS. + * | | |10 = Reserved. + * | | |11 = Set to SubM. + * |[21:20] |PIN10 |GPIO Pin 10 Security Attribution Bits + * | | |00 = Set to TZS. + * | | |01 = Set to TZNS. + * | | |10 = Reserved. + * | | |11 = Set to SubM. + * |[23:22] |PIN11 |GPIO Pin 11 Security Attribution Bits + * | | |00 = Set to TZS. + * | | |01 = Set to TZNS. + * | | |10 = Reserved. + * | | |11 = Set to SubM. + * |[25:24] |PIN12 |GPIO Pin 12 Security Attribution Bits + * | | |00 = Set to TZS. + * | | |01 = Set to TZNS. + * | | |10 = Reserved. + * | | |11 = Set to SubM. + * |[27:26] |PIN13 |GPIO Pin 13 Security Attribution Bits + * | | |00 = Set to TZS. + * | | |01 = Set to TZNS. + * | | |10 = Reserved. + * | | |11 = Set to SubM. + * |[29:28] |PIN14 |GPIO Pin 14 Security Attribution Bits + * | | |00 = Set to TZS. + * | | |01 = Set to TZNS. + * | | |10 = Reserved. + * | | |11 = Set to SubM. + * |[31:30] |PIN15 |GPIO Pin 15 Security Attribution Bits + * | | |00 = Set to TZS. + * | | |01 = Set to TZNS. + * | | |10 = Reserved. + * | | |11 = Set to SubM. + * @var SSPCC_T::IOBSSET + * Offset: 0x64 GPIO Port B Security Attribution Set Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[1:0] |PIN0 |GPIO Pin 0 Security Attribution Bits + * | | |00 = Set to TZS. + * | | |01 = Set to TZNS. + * | | |10 = Reserved. + * | | |11 = Set to SubM. + * |[3:2] |PIN1 |GPIO Pin 1 Security Attribution Bits + * | | |00 = Set to TZS. + * | | |01 = Set to TZNS. + * | | |10 = Reserved. + * | | |11 = Set to SubM. + * |[5:4] |PIN2 |GPIO Pin 2 Security Attribution Bits + * | | |00 = Set to TZS. + * | | |01 = Set to TZNS. + * | | |10 = Reserved. + * | | |11 = Set to SubM. + * |[7:6] |PIN3 |GPIO Pin 3 Security Attribution Bits + * | | |00 = Set to TZS. + * | | |01 = Set to TZNS. + * | | |10 = Reserved. + * | | |11 = Set to SubM. + * |[9:8] |PIN4 |GPIO Pin 4 Security Attribution Bits + * | | |00 = Set to TZS. + * | | |01 = Set to TZNS. + * | | |10 = Reserved. + * | | |11 = Set to SubM. + * |[11:10] |PIN5 |GPIO Pin 5 Security Attribution Bits + * | | |00 = Set to TZS. + * | | |01 = Set to TZNS. + * | | |10 = Reserved. + * | | |11 = Set to SubM. + * |[13:12] |PIN6 |GPIO Pin 6 Security Attribution Bits + * | | |00 = Set to TZS. + * | | |01 = Set to TZNS. + * | | |10 = Reserved. + * | | |11 = Set to SubM. + * |[15:14] |PIN7 |GPIO Pin 7 Security Attribution Bits + * | | |00 = Set to TZS. + * | | |01 = Set to TZNS. + * | | |10 = Reserved. + * | | |11 = Set to SubM. + * |[17:16] |PIN8 |GPIO Pin 8 Security Attribution Bits + * | | |00 = Set to TZS. + * | | |01 = Set to TZNS. + * | | |10 = Reserved. + * | | |11 = Set to SubM. + * |[19:18] |PIN9 |GPIO Pin 9 Security Attribution Bits + * | | |00 = Set to TZS. + * | | |01 = Set to TZNS. + * | | |10 = Reserved. + * | | |11 = Set to SubM. + * |[21:20] |PIN10 |GPIO Pin 10 Security Attribution Bits + * | | |00 = Set to TZS. + * | | |01 = Set to TZNS. + * | | |10 = Reserved. + * | | |11 = Set to SubM. + * |[23:22] |PIN11 |GPIO Pin 11 Security Attribution Bits + * | | |00 = Set to TZS. + * | | |01 = Set to TZNS. + * | | |10 = Reserved. + * | | |11 = Set to SubM. + * |[25:24] |PIN12 |GPIO Pin 12 Security Attribution Bits + * | | |00 = Set to TZS. + * | | |01 = Set to TZNS. + * | | |10 = Reserved. + * | | |11 = Set to SubM. + * |[27:26] |PIN13 |GPIO Pin 13 Security Attribution Bits + * | | |00 = Set to TZS. + * | | |01 = Set to TZNS. + * | | |10 = Reserved. + * | | |11 = Set to SubM. + * |[29:28] |PIN14 |GPIO Pin 14 Security Attribution Bits + * | | |00 = Set to TZS. + * | | |01 = Set to TZNS. + * | | |10 = Reserved. + * | | |11 = Set to SubM. + * |[31:30] |PIN15 |GPIO Pin 15 Security Attribution Bits + * | | |00 = Set to TZS. + * | | |01 = Set to TZNS. + * | | |10 = Reserved. + * | | |11 = Set to SubM. + * @var SSPCC_T::IOCSSET + * Offset: 0x68 GPIO Port C Security Attribution Set Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[1:0] |PIN0 |GPIO Pin 0 Security Attribution Bits + * | | |00 = Set to TZS. + * | | |01 = Set to TZNS. + * | | |10 = Reserved. + * | | |11 = Set to SubM. + * |[3:2] |PIN1 |GPIO Pin 1 Security Attribution Bits + * | | |00 = Set to TZS. + * | | |01 = Set to TZNS. + * | | |10 = Reserved. + * | | |11 = Set to SubM. + * |[5:4] |PIN2 |GPIO Pin 2 Security Attribution Bits + * | | |00 = Set to TZS. + * | | |01 = Set to TZNS. + * | | |10 = Reserved. + * | | |11 = Set to SubM. + * |[7:6] |PIN3 |GPIO Pin 3 Security Attribution Bits + * | | |00 = Set to TZS. + * | | |01 = Set to TZNS. + * | | |10 = Reserved. + * | | |11 = Set to SubM. + * |[9:8] |PIN4 |GPIO Pin 4 Security Attribution Bits + * | | |00 = Set to TZS. + * | | |01 = Set to TZNS. + * | | |10 = Reserved. + * | | |11 = Set to SubM. + * |[11:10] |PIN5 |GPIO Pin 5 Security Attribution Bits + * | | |00 = Set to TZS. + * | | |01 = Set to TZNS. + * | | |10 = Reserved. + * | | |11 = Set to SubM. + * |[13:12] |PIN6 |GPIO Pin 6 Security Attribution Bits + * | | |00 = Set to TZS. + * | | |01 = Set to TZNS. + * | | |10 = Reserved. + * | | |11 = Set to SubM. + * |[15:14] |PIN7 |GPIO Pin 7 Security Attribution Bits + * | | |00 = Set to TZS. + * | | |01 = Set to TZNS. + * | | |10 = Reserved. + * | | |11 = Set to SubM. + * |[17:16] |PIN8 |GPIO Pin 8 Security Attribution Bits + * | | |00 = Set to TZS. + * | | |01 = Set to TZNS. + * | | |10 = Reserved. + * | | |11 = Set to SubM. + * |[19:18] |PIN9 |GPIO Pin 9 Security Attribution Bits + * | | |00 = Set to TZS. + * | | |01 = Set to TZNS. + * | | |10 = Reserved. + * | | |11 = Set to SubM. + * |[21:20] |PIN10 |GPIO Pin 10 Security Attribution Bits + * | | |00 = Set to TZS. + * | | |01 = Set to TZNS. + * | | |10 = Reserved. + * | | |11 = Set to SubM. + * |[23:22] |PIN11 |GPIO Pin 11 Security Attribution Bits + * | | |00 = Set to TZS. + * | | |01 = Set to TZNS. + * | | |10 = Reserved. + * | | |11 = Set to SubM. + * |[25:24] |PIN12 |GPIO Pin 12 Security Attribution Bits + * | | |00 = Set to TZS. + * | | |01 = Set to TZNS. + * | | |10 = Reserved. + * | | |11 = Set to SubM. + * |[27:26] |PIN13 |GPIO Pin 13 Security Attribution Bits + * | | |00 = Set to TZS. + * | | |01 = Set to TZNS. + * | | |10 = Reserved. + * | | |11 = Set to SubM. + * |[29:28] |PIN14 |GPIO Pin 14 Security Attribution Bits + * | | |00 = Set to TZS. + * | | |01 = Set to TZNS. + * | | |10 = Reserved. + * | | |11 = Set to SubM. + * |[31:30] |PIN15 |GPIO Pin 15 Security Attribution Bits + * | | |00 = Set to TZS. + * | | |01 = Set to TZNS. + * | | |10 = Reserved. + * | | |11 = Set to SubM. + * @var SSPCC_T::IODSSET + * Offset: 0x6C GPIO Port D Security Attribution Set Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[1:0] |PIN0 |GPIO Pin 0 Security Attribution Bits + * | | |00 = Set to TZS. + * | | |01 = Set to TZNS. + * | | |10 = Reserved. + * | | |11 = Set to SubM. + * |[3:2] |PIN1 |GPIO Pin 1 Security Attribution Bits + * | | |00 = Set to TZS. + * | | |01 = Set to TZNS. + * | | |10 = Reserved. + * | | |11 = Set to SubM. + * |[5:4] |PIN2 |GPIO Pin 2 Security Attribution Bits + * | | |00 = Set to TZS. + * | | |01 = Set to TZNS. + * | | |10 = Reserved. + * | | |11 = Set to SubM. + * |[7:6] |PIN3 |GPIO Pin 3 Security Attribution Bits + * | | |00 = Set to TZS. + * | | |01 = Set to TZNS. + * | | |10 = Reserved. + * | | |11 = Set to SubM. + * |[9:8] |PIN4 |GPIO Pin 4 Security Attribution Bits + * | | |00 = Set to TZS. + * | | |01 = Set to TZNS. + * | | |10 = Reserved. + * | | |11 = Set to SubM. + * |[11:10] |PIN5 |GPIO Pin 5 Security Attribution Bits + * | | |00 = Set to TZS. + * | | |01 = Set to TZNS. + * | | |10 = Reserved. + * | | |11 = Set to SubM. + * |[13:12] |PIN6 |GPIO Pin 6 Security Attribution Bits + * | | |00 = Set to TZS. + * | | |01 = Set to TZNS. + * | | |10 = Reserved. + * | | |11 = Set to SubM. + * |[15:14] |PIN7 |GPIO Pin 7 Security Attribution Bits + * | | |00 = Set to TZS. + * | | |01 = Set to TZNS. + * | | |10 = Reserved. + * | | |11 = Set to SubM. + * |[17:16] |PIN8 |GPIO Pin 8 Security Attribution Bits + * | | |00 = Set to TZS. + * | | |01 = Set to TZNS. + * | | |10 = Reserved. + * | | |11 = Set to SubM. + * |[19:18] |PIN9 |GPIO Pin 9 Security Attribution Bits + * | | |00 = Set to TZS. + * | | |01 = Set to TZNS. + * | | |10 = Reserved. + * | | |11 = Set to SubM. + * |[21:20] |PIN10 |GPIO Pin 10 Security Attribution Bits + * | | |00 = Set to TZS. + * | | |01 = Set to TZNS. + * | | |10 = Reserved. + * | | |11 = Set to SubM. + * |[23:22] |PIN11 |GPIO Pin 11 Security Attribution Bits + * | | |00 = Set to TZS. + * | | |01 = Set to TZNS. + * | | |10 = Reserved. + * | | |11 = Set to SubM. + * |[25:24] |PIN12 |GPIO Pin 12 Security Attribution Bits + * | | |00 = Set to TZS. + * | | |01 = Set to TZNS. + * | | |10 = Reserved. + * | | |11 = Set to SubM. + * |[27:26] |PIN13 |GPIO Pin 13 Security Attribution Bits + * | | |00 = Set to TZS. + * | | |01 = Set to TZNS. + * | | |10 = Reserved. + * | | |11 = Set to SubM. + * |[29:28] |PIN14 |GPIO Pin 14 Security Attribution Bits + * | | |00 = Set to TZS. + * | | |01 = Set to TZNS. + * | | |10 = Reserved. + * | | |11 = Set to SubM. + * |[31:30] |PIN15 |GPIO Pin 15 Security Attribution Bits + * | | |00 = Set to TZS. + * | | |01 = Set to TZNS. + * | | |10 = Reserved. + * | | |11 = Set to SubM. + * @var SSPCC_T::IOESSET + * Offset: 0x70 GPIO Port E Security Attribution Set Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[1:0] |PIN0 |GPIO Pin 0 Security Attribution Bits + * | | |00 = Set to TZS. + * | | |01 = Set to TZNS. + * | | |10 = Reserved. + * | | |11 = Set to SubM. + * |[3:2] |PIN1 |GPIO Pin 1 Security Attribution Bits + * | | |00 = Set to TZS. + * | | |01 = Set to TZNS. + * | | |10 = Reserved. + * | | |11 = Set to SubM. + * |[5:4] |PIN2 |GPIO Pin 2 Security Attribution Bits + * | | |00 = Set to TZS. + * | | |01 = Set to TZNS. + * | | |10 = Reserved. + * | | |11 = Set to SubM. + * |[7:6] |PIN3 |GPIO Pin 3 Security Attribution Bits + * | | |00 = Set to TZS. + * | | |01 = Set to TZNS. + * | | |10 = Reserved. + * | | |11 = Set to SubM. + * |[9:8] |PIN4 |GPIO Pin 4 Security Attribution Bits + * | | |00 = Set to TZS. + * | | |01 = Set to TZNS. + * | | |10 = Reserved. + * | | |11 = Set to SubM. + * |[11:10] |PIN5 |GPIO Pin 5 Security Attribution Bits + * | | |00 = Set to TZS. + * | | |01 = Set to TZNS. + * | | |10 = Reserved. + * | | |11 = Set to SubM. + * |[13:12] |PIN6 |GPIO Pin 6 Security Attribution Bits + * | | |00 = Set to TZS. + * | | |01 = Set to TZNS. + * | | |10 = Reserved. + * | | |11 = Set to SubM. + * |[15:14] |PIN7 |GPIO Pin 7 Security Attribution Bits + * | | |00 = Set to TZS. + * | | |01 = Set to TZNS. + * | | |10 = Reserved. + * | | |11 = Set to SubM. + * |[17:16] |PIN8 |GPIO Pin 8 Security Attribution Bits + * | | |00 = Set to TZS. + * | | |01 = Set to TZNS. + * | | |10 = Reserved. + * | | |11 = Set to SubM. + * |[19:18] |PIN9 |GPIO Pin 9 Security Attribution Bits + * | | |00 = Set to TZS. + * | | |01 = Set to TZNS. + * | | |10 = Reserved. + * | | |11 = Set to SubM. + * |[21:20] |PIN10 |GPIO Pin 10 Security Attribution Bits + * | | |00 = Set to TZS. + * | | |01 = Set to TZNS. + * | | |10 = Reserved. + * | | |11 = Set to SubM. + * |[23:22] |PIN11 |GPIO Pin 11 Security Attribution Bits + * | | |00 = Set to TZS. + * | | |01 = Set to TZNS. + * | | |10 = Reserved. + * | | |11 = Set to SubM. + * |[25:24] |PIN12 |GPIO Pin 12 Security Attribution Bits + * | | |00 = Set to TZS. + * | | |01 = Set to TZNS. + * | | |10 = Reserved. + * | | |11 = Set to SubM. + * |[27:26] |PIN13 |GPIO Pin 13 Security Attribution Bits + * | | |00 = Set to TZS. + * | | |01 = Set to TZNS. + * | | |10 = Reserved. + * | | |11 = Set to SubM. + * |[29:28] |PIN14 |GPIO Pin 14 Security Attribution Bits + * | | |00 = Set to TZS. + * | | |01 = Set to TZNS. + * | | |10 = Reserved. + * | | |11 = Set to SubM. + * |[31:30] |PIN15 |GPIO Pin 15 Security Attribution Bits + * | | |00 = Set to TZS. + * | | |01 = Set to TZNS. + * | | |10 = Reserved. + * | | |11 = Set to SubM. + * @var SSPCC_T::IOFSSET + * Offset: 0x74 GPIO Port F Security Attribution Set Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[1:0] |PIN0 |GPIO Pin 0 Security Attribution Bits + * | | |00 = Set to TZS. + * | | |01 = Set to TZNS. + * | | |10 = Reserved. + * | | |11 = Set to SubM. + * |[3:2] |PIN1 |GPIO Pin 1 Security Attribution Bits + * | | |00 = Set to TZS. + * | | |01 = Set to TZNS. + * | | |10 = Reserved. + * | | |11 = Set to SubM. + * |[5:4] |PIN2 |GPIO Pin 2 Security Attribution Bits + * | | |00 = Set to TZS. + * | | |01 = Set to TZNS. + * | | |10 = Reserved. + * | | |11 = Set to SubM. + * |[7:6] |PIN3 |GPIO Pin 3 Security Attribution Bits + * | | |00 = Set to TZS. + * | | |01 = Set to TZNS. + * | | |10 = Reserved. + * | | |11 = Set to SubM. + * |[9:8] |PIN4 |GPIO Pin 4 Security Attribution Bits + * | | |00 = Set to TZS. + * | | |01 = Set to TZNS. + * | | |10 = Reserved. + * | | |11 = Set to SubM. + * |[11:10] |PIN5 |GPIO Pin 5 Security Attribution Bits + * | | |00 = Set to TZS. + * | | |01 = Set to TZNS. + * | | |10 = Reserved. + * | | |11 = Set to SubM. + * |[13:12] |PIN6 |GPIO Pin 6 Security Attribution Bits + * | | |00 = Set to TZS. + * | | |01 = Set to TZNS. + * | | |10 = Reserved. + * | | |11 = Set to SubM. + * |[15:14] |PIN7 |GPIO Pin 7 Security Attribution Bits + * | | |00 = Set to TZS. + * | | |01 = Set to TZNS. + * | | |10 = Reserved. + * | | |11 = Set to SubM. + * |[17:16] |PIN8 |GPIO Pin 8 Security Attribution Bits + * | | |00 = Set to TZS. + * | | |01 = Set to TZNS. + * | | |10 = Reserved. + * | | |11 = Set to SubM. + * |[19:18] |PIN9 |GPIO Pin 9 Security Attribution Bits + * | | |00 = Set to TZS. + * | | |01 = Set to TZNS. + * | | |10 = Reserved. + * | | |11 = Set to SubM. + * |[21:20] |PIN10 |GPIO Pin 10 Security Attribution Bits + * | | |00 = Set to TZS. + * | | |01 = Set to TZNS. + * | | |10 = Reserved. + * | | |11 = Set to SubM. + * |[23:22] |PIN11 |GPIO Pin 11 Security Attribution Bits + * | | |00 = Set to TZS. + * | | |01 = Set to TZNS. + * | | |10 = Reserved. + * | | |11 = Set to SubM. + * |[25:24] |PIN12 |GPIO Pin 12 Security Attribution Bits + * | | |00 = Set to TZS. + * | | |01 = Set to TZNS. + * | | |10 = Reserved. + * | | |11 = Set to SubM. + * |[27:26] |PIN13 |GPIO Pin 13 Security Attribution Bits + * | | |00 = Set to TZS. + * | | |01 = Set to TZNS. + * | | |10 = Reserved. + * | | |11 = Set to SubM. + * |[29:28] |PIN14 |GPIO Pin 14 Security Attribution Bits + * | | |00 = Set to TZS. + * | | |01 = Set to TZNS. + * | | |10 = Reserved. + * | | |11 = Set to SubM. + * |[31:30] |PIN15 |GPIO Pin 15 Security Attribution Bits + * | | |00 = Set to TZS. + * | | |01 = Set to TZNS. + * | | |10 = Reserved. + * | | |11 = Set to SubM. + * @var SSPCC_T::IOGSSET + * Offset: 0x78 GPIO Port G Security Attribution Set Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[1:0] |PIN0 |GPIO Pin 0 Security Attribution Bits + * | | |00 = Set to TZS. + * | | |01 = Set to TZNS. + * | | |10 = Reserved. + * | | |11 = Set to SubM. + * |[3:2] |PIN1 |GPIO Pin 1 Security Attribution Bits + * | | |00 = Set to TZS. + * | | |01 = Set to TZNS. + * | | |10 = Reserved. + * | | |11 = Set to SubM. + * |[5:4] |PIN2 |GPIO Pin 2 Security Attribution Bits + * | | |00 = Set to TZS. + * | | |01 = Set to TZNS. + * | | |10 = Reserved. + * | | |11 = Set to SubM. + * |[7:6] |PIN3 |GPIO Pin 3 Security Attribution Bits + * | | |00 = Set to TZS. + * | | |01 = Set to TZNS. + * | | |10 = Reserved. + * | | |11 = Set to SubM. + * |[9:8] |PIN4 |GPIO Pin 4 Security Attribution Bits + * | | |00 = Set to TZS. + * | | |01 = Set to TZNS. + * | | |10 = Reserved. + * | | |11 = Set to SubM. + * |[11:10] |PIN5 |GPIO Pin 5 Security Attribution Bits + * | | |00 = Set to TZS. + * | | |01 = Set to TZNS. + * | | |10 = Reserved. + * | | |11 = Set to SubM. + * |[13:12] |PIN6 |GPIO Pin 6 Security Attribution Bits + * | | |00 = Set to TZS. + * | | |01 = Set to TZNS. + * | | |10 = Reserved. + * | | |11 = Set to SubM. + * |[15:14] |PIN7 |GPIO Pin 7 Security Attribution Bits + * | | |00 = Set to TZS. + * | | |01 = Set to TZNS. + * | | |10 = Reserved. + * | | |11 = Set to SubM. + * |[17:16] |PIN8 |GPIO Pin 8 Security Attribution Bits + * | | |00 = Set to TZS. + * | | |01 = Set to TZNS. + * | | |10 = Reserved. + * | | |11 = Set to SubM. + * |[19:18] |PIN9 |GPIO Pin 9 Security Attribution Bits + * | | |00 = Set to TZS. + * | | |01 = Set to TZNS. + * | | |10 = Reserved. + * | | |11 = Set to SubM. + * |[21:20] |PIN10 |GPIO Pin 10 Security Attribution Bits + * | | |00 = Set to TZS. + * | | |01 = Set to TZNS. + * | | |10 = Reserved. + * | | |11 = Set to SubM. + * |[23:22] |PIN11 |GPIO Pin 11 Security Attribution Bits + * | | |00 = Set to TZS. + * | | |01 = Set to TZNS. + * | | |10 = Reserved. + * | | |11 = Set to SubM. + * |[25:24] |PIN12 |GPIO Pin 12 Security Attribution Bits + * | | |00 = Set to TZS. + * | | |01 = Set to TZNS. + * | | |10 = Reserved. + * | | |11 = Set to SubM. + * |[27:26] |PIN13 |GPIO Pin 13 Security Attribution Bits + * | | |00 = Set to TZS. + * | | |01 = Set to TZNS. + * | | |10 = Reserved. + * | | |11 = Set to SubM. + * |[29:28] |PIN14 |GPIO Pin 14 Security Attribution Bits + * | | |00 = Set to TZS. + * | | |01 = Set to TZNS. + * | | |10 = Reserved. + * | | |11 = Set to SubM. + * |[31:30] |PIN15 |GPIO Pin 15 Security Attribution Bits + * | | |00 = Set to TZS. + * | | |01 = Set to TZNS. + * | | |10 = Reserved. + * | | |11 = Set to SubM. + * @var SSPCC_T::IOHSSET + * Offset: 0x7C GPIO Port H Security Attribution Set Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[1:0] |PIN0 |GPIO Pin 0 Security Attribution Bits + * | | |00 = Set to TZS. + * | | |01 = Set to TZNS. + * | | |10 = Reserved. + * | | |11 = Set to SubM. + * |[3:2] |PIN1 |GPIO Pin 1 Security Attribution Bits + * | | |00 = Set to TZS. + * | | |01 = Set to TZNS. + * | | |10 = Reserved. + * | | |11 = Set to SubM. + * |[5:4] |PIN2 |GPIO Pin 2 Security Attribution Bits + * | | |00 = Set to TZS. + * | | |01 = Set to TZNS. + * | | |10 = Reserved. + * | | |11 = Set to SubM. + * |[7:6] |PIN3 |GPIO Pin 3 Security Attribution Bits + * | | |00 = Set to TZS. + * | | |01 = Set to TZNS. + * | | |10 = Reserved. + * | | |11 = Set to SubM. + * |[9:8] |PIN4 |GPIO Pin 4 Security Attribution Bits + * | | |00 = Set to TZS. + * | | |01 = Set to TZNS. + * | | |10 = Reserved. + * | | |11 = Set to SubM. + * |[11:10] |PIN5 |GPIO Pin 5 Security Attribution Bits + * | | |00 = Set to TZS. + * | | |01 = Set to TZNS. + * | | |10 = Reserved. + * | | |11 = Set to SubM. + * |[13:12] |PIN6 |GPIO Pin 6 Security Attribution Bits + * | | |00 = Set to TZS. + * | | |01 = Set to TZNS. + * | | |10 = Reserved. + * | | |11 = Set to SubM. + * |[15:14] |PIN7 |GPIO Pin 7 Security Attribution Bits + * | | |00 = Set to TZS. + * | | |01 = Set to TZNS. + * | | |10 = Reserved. + * | | |11 = Set to SubM. + * |[17:16] |PIN8 |GPIO Pin 8 Security Attribution Bits + * | | |00 = Set to TZS. + * | | |01 = Set to TZNS. + * | | |10 = Reserved. + * | | |11 = Set to SubM. + * |[19:18] |PIN9 |GPIO Pin 9 Security Attribution Bits + * | | |00 = Set to TZS. + * | | |01 = Set to TZNS. + * | | |10 = Reserved. + * | | |11 = Set to SubM. + * |[21:20] |PIN10 |GPIO Pin 10 Security Attribution Bits + * | | |00 = Set to TZS. + * | | |01 = Set to TZNS. + * | | |10 = Reserved. + * | | |11 = Set to SubM. + * |[23:22] |PIN11 |GPIO Pin 11 Security Attribution Bits + * | | |00 = Set to TZS. + * | | |01 = Set to TZNS. + * | | |10 = Reserved. + * | | |11 = Set to SubM. + * |[25:24] |PIN12 |GPIO Pin 12 Security Attribution Bits + * | | |00 = Set to TZS. + * | | |01 = Set to TZNS. + * | | |10 = Reserved. + * | | |11 = Set to SubM. + * |[27:26] |PIN13 |GPIO Pin 13 Security Attribution Bits + * | | |00 = Set to TZS. + * | | |01 = Set to TZNS. + * | | |10 = Reserved. + * | | |11 = Set to SubM. + * |[29:28] |PIN14 |GPIO Pin 14 Security Attribution Bits + * | | |00 = Set to TZS. + * | | |01 = Set to TZNS. + * | | |10 = Reserved. + * | | |11 = Set to SubM. + * |[31:30] |PIN15 |GPIO Pin 15 Security Attribution Bits + * | | |00 = Set to TZS. + * | | |01 = Set to TZNS. + * | | |10 = Reserved. + * | | |11 = Set to SubM. + * @var SSPCC_T::IOISSET + * Offset: 0x80 GPIO Port I Security Attribution Set Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[1:0] |PIN0 |GPIO Pin 0 Security Attribution Bits + * | | |00 = Set to TZS. + * | | |01 = Set to TZNS. + * | | |10 = Reserved. + * | | |11 = Set to SubM. + * |[3:2] |PIN1 |GPIO Pin 1 Security Attribution Bits + * | | |00 = Set to TZS. + * | | |01 = Set to TZNS. + * | | |10 = Reserved. + * | | |11 = Set to SubM. + * |[5:4] |PIN2 |GPIO Pin 2 Security Attribution Bits + * | | |00 = Set to TZS. + * | | |01 = Set to TZNS. + * | | |10 = Reserved. + * | | |11 = Set to SubM. + * |[7:6] |PIN3 |GPIO Pin 3 Security Attribution Bits + * | | |00 = Set to TZS. + * | | |01 = Set to TZNS. + * | | |10 = Reserved. + * | | |11 = Set to SubM. + * |[9:8] |PIN4 |GPIO Pin 4 Security Attribution Bits + * | | |00 = Set to TZS. + * | | |01 = Set to TZNS. + * | | |10 = Reserved. + * | | |11 = Set to SubM. + * |[11:10] |PIN5 |GPIO Pin 5 Security Attribution Bits + * | | |00 = Set to TZS. + * | | |01 = Set to TZNS. + * | | |10 = Reserved. + * | | |11 = Set to SubM. + * |[13:12] |PIN6 |GPIO Pin 6 Security Attribution Bits + * | | |00 = Set to TZS. + * | | |01 = Set to TZNS. + * | | |10 = Reserved. + * | | |11 = Set to SubM. + * |[15:14] |PIN7 |GPIO Pin 7 Security Attribution Bits + * | | |00 = Set to TZS. + * | | |01 = Set to TZNS. + * | | |10 = Reserved. + * | | |11 = Set to SubM. + * |[17:16] |PIN8 |GPIO Pin 8 Security Attribution Bits + * | | |00 = Set to TZS. + * | | |01 = Set to TZNS. + * | | |10 = Reserved. + * | | |11 = Set to SubM. + * |[19:18] |PIN9 |GPIO Pin 9 Security Attribution Bits + * | | |00 = Set to TZS. + * | | |01 = Set to TZNS. + * | | |10 = Reserved. + * | | |11 = Set to SubM. + * |[21:20] |PIN10 |GPIO Pin 10 Security Attribution Bits + * | | |00 = Set to TZS. + * | | |01 = Set to TZNS. + * | | |10 = Reserved. + * | | |11 = Set to SubM. + * |[23:22] |PIN11 |GPIO Pin 11 Security Attribution Bits + * | | |00 = Set to TZS. + * | | |01 = Set to TZNS. + * | | |10 = Reserved. + * | | |11 = Set to SubM. + * |[25:24] |PIN12 |GPIO Pin 12 Security Attribution Bits + * | | |00 = Set to TZS. + * | | |01 = Set to TZNS. + * | | |10 = Reserved. + * | | |11 = Set to SubM. + * |[27:26] |PIN13 |GPIO Pin 13 Security Attribution Bits + * | | |00 = Set to TZS. + * | | |01 = Set to TZNS. + * | | |10 = Reserved. + * | | |11 = Set to SubM. + * |[29:28] |PIN14 |GPIO Pin 14 Security Attribution Bits + * | | |00 = Set to TZS. + * | | |01 = Set to TZNS. + * | | |10 = Reserved. + * | | |11 = Set to SubM. + * |[31:30] |PIN15 |GPIO Pin 15 Security Attribution Bits + * | | |00 = Set to TZS. + * | | |01 = Set to TZNS. + * | | |10 = Reserved. + * | | |11 = Set to SubM. + * @var SSPCC_T::IOJSSET + * Offset: 0x84 GPIO Port J Security Attribution Set Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[1:0] |PIN0 |GPIO Pin 0 Security Attribution Bits + * | | |00 = Set to TZS. + * | | |01 = Set to TZNS. + * | | |10 = Reserved. + * | | |11 = Set to SubM. + * |[3:2] |PIN1 |GPIO Pin 1 Security Attribution Bits + * | | |00 = Set to TZS. + * | | |01 = Set to TZNS. + * | | |10 = Reserved. + * | | |11 = Set to SubM. + * |[5:4] |PIN2 |GPIO Pin 2 Security Attribution Bits + * | | |00 = Set to TZS. + * | | |01 = Set to TZNS. + * | | |10 = Reserved. + * | | |11 = Set to SubM. + * |[7:6] |PIN3 |GPIO Pin 3 Security Attribution Bits + * | | |00 = Set to TZS. + * | | |01 = Set to TZNS. + * | | |10 = Reserved. + * | | |11 = Set to SubM. + * |[9:8] |PIN4 |GPIO Pin 4 Security Attribution Bits + * | | |00 = Set to TZS. + * | | |01 = Set to TZNS. + * | | |10 = Reserved. + * | | |11 = Set to SubM. + * |[11:10] |PIN5 |GPIO Pin 5 Security Attribution Bits + * | | |00 = Set to TZS. + * | | |01 = Set to TZNS. + * | | |10 = Reserved. + * | | |11 = Set to SubM. + * |[13:12] |PIN6 |GPIO Pin 6 Security Attribution Bits + * | | |00 = Set to TZS. + * | | |01 = Set to TZNS. + * | | |10 = Reserved. + * | | |11 = Set to SubM. + * |[15:14] |PIN7 |GPIO Pin 7 Security Attribution Bits + * | | |00 = Set to TZS. + * | | |01 = Set to TZNS. + * | | |10 = Reserved. + * | | |11 = Set to SubM. + * |[17:16] |PIN8 |GPIO Pin 8 Security Attribution Bits + * | | |00 = Set to TZS. + * | | |01 = Set to TZNS. + * | | |10 = Reserved. + * | | |11 = Set to SubM. + * |[19:18] |PIN9 |GPIO Pin 9 Security Attribution Bits + * | | |00 = Set to TZS. + * | | |01 = Set to TZNS. + * | | |10 = Reserved. + * | | |11 = Set to SubM. + * |[21:20] |PIN10 |GPIO Pin 10 Security Attribution Bits + * | | |00 = Set to TZS. + * | | |01 = Set to TZNS. + * | | |10 = Reserved. + * | | |11 = Set to SubM. + * |[23:22] |PIN11 |GPIO Pin 11 Security Attribution Bits + * | | |00 = Set to TZS. + * | | |01 = Set to TZNS. + * | | |10 = Reserved. + * | | |11 = Set to SubM. + * |[25:24] |PIN12 |GPIO Pin 12 Security Attribution Bits + * | | |00 = Set to TZS. + * | | |01 = Set to TZNS. + * | | |10 = Reserved. + * | | |11 = Set to SubM. + * |[27:26] |PIN13 |GPIO Pin 13 Security Attribution Bits + * | | |00 = Set to TZS. + * | | |01 = Set to TZNS. + * | | |10 = Reserved. + * | | |11 = Set to SubM. + * |[29:28] |PIN14 |GPIO Pin 14 Security Attribution Bits + * | | |00 = Set to TZS. + * | | |01 = Set to TZNS. + * | | |10 = Reserved. + * | | |11 = Set to SubM. + * |[31:30] |PIN15 |GPIO Pin 15 Security Attribution Bits + * | | |00 = Set to TZS. + * | | |01 = Set to TZNS. + * | | |10 = Reserved. + * | | |11 = Set to SubM. + * @var SSPCC_T::IOKSSET + * Offset: 0x88 GPIO Port K Security Attribution Set Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[1:0] |PIN0 |GPIO Pin 0 Security Attribution Bits + * | | |00 = Set to TZS. + * | | |01 = Set to TZNS. + * | | |10 = Reserved. + * | | |11 = Set to SubM. + * |[3:2] |PIN1 |GPIO Pin 1 Security Attribution Bits + * | | |00 = Set to TZS. + * | | |01 = Set to TZNS. + * | | |10 = Reserved. + * | | |11 = Set to SubM. + * |[5:4] |PIN2 |GPIO Pin 2 Security Attribution Bits + * | | |00 = Set to TZS. + * | | |01 = Set to TZNS. + * | | |10 = Reserved. + * | | |11 = Set to SubM. + * |[7:6] |PIN3 |GPIO Pin 3 Security Attribution Bits + * | | |00 = Set to TZS. + * | | |01 = Set to TZNS. + * | | |10 = Reserved. + * | | |11 = Set to SubM. + * |[9:8] |PIN4 |GPIO Pin 4 Security Attribution Bits + * | | |00 = Set to TZS. + * | | |01 = Set to TZNS. + * | | |10 = Reserved. + * | | |11 = Set to SubM. + * |[11:10] |PIN5 |GPIO Pin 5 Security Attribution Bits + * | | |00 = Set to TZS. + * | | |01 = Set to TZNS. + * | | |10 = Reserved. + * | | |11 = Set to SubM. + * |[13:12] |PIN6 |GPIO Pin 6 Security Attribution Bits + * | | |00 = Set to TZS. + * | | |01 = Set to TZNS. + * | | |10 = Reserved. + * | | |11 = Set to SubM. + * |[15:14] |PIN7 |GPIO Pin 7 Security Attribution Bits + * | | |00 = Set to TZS. + * | | |01 = Set to TZNS. + * | | |10 = Reserved. + * | | |11 = Set to SubM. + * |[17:16] |PIN8 |GPIO Pin 8 Security Attribution Bits + * | | |00 = Set to TZS. + * | | |01 = Set to TZNS. + * | | |10 = Reserved. + * | | |11 = Set to SubM. + * |[19:18] |PIN9 |GPIO Pin 9 Security Attribution Bits + * | | |00 = Set to TZS. + * | | |01 = Set to TZNS. + * | | |10 = Reserved. + * | | |11 = Set to SubM. + * |[21:20] |PIN10 |GPIO Pin 10 Security Attribution Bits + * | | |00 = Set to TZS. + * | | |01 = Set to TZNS. + * | | |10 = Reserved. + * | | |11 = Set to SubM. + * |[23:22] |PIN11 |GPIO Pin 11 Security Attribution Bits + * | | |00 = Set to TZS. + * | | |01 = Set to TZNS. + * | | |10 = Reserved. + * | | |11 = Set to SubM. + * |[25:24] |PIN12 |GPIO Pin 12 Security Attribution Bits + * | | |00 = Set to TZS. + * | | |01 = Set to TZNS. + * | | |10 = Reserved. + * | | |11 = Set to SubM. + * |[27:26] |PIN13 |GPIO Pin 13 Security Attribution Bits + * | | |00 = Set to TZS. + * | | |01 = Set to TZNS. + * | | |10 = Reserved. + * | | |11 = Set to SubM. + * |[29:28] |PIN14 |GPIO Pin 14 Security Attribution Bits + * | | |00 = Set to TZS. + * | | |01 = Set to TZNS. + * | | |10 = Reserved. + * | | |11 = Set to SubM. + * |[31:30] |PIN15 |GPIO Pin 15 Security Attribution Bits + * | | |00 = Set to TZS. + * | | |01 = Set to TZNS. + * | | |10 = Reserved. + * | | |11 = Set to SubM. + * @var SSPCC_T::IOLSSET + * Offset: 0x8C GPIO Port L Security Attribution Set Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[1:0] |PIN0 |GPIO Pin 0 Security Attribution Bits + * | | |00 = Set to TZS. + * | | |01 = Set to TZNS. + * | | |10 = Reserved. + * | | |11 = Set to SubM. + * |[3:2] |PIN1 |GPIO Pin 1 Security Attribution Bits + * | | |00 = Set to TZS. + * | | |01 = Set to TZNS. + * | | |10 = Reserved. + * | | |11 = Set to SubM. + * |[5:4] |PIN2 |GPIO Pin 2 Security Attribution Bits + * | | |00 = Set to TZS. + * | | |01 = Set to TZNS. + * | | |10 = Reserved. + * | | |11 = Set to SubM. + * |[7:6] |PIN3 |GPIO Pin 3 Security Attribution Bits + * | | |00 = Set to TZS. + * | | |01 = Set to TZNS. + * | | |10 = Reserved. + * | | |11 = Set to SubM. + * |[9:8] |PIN4 |GPIO Pin 4 Security Attribution Bits + * | | |00 = Set to TZS. + * | | |01 = Set to TZNS. + * | | |10 = Reserved. + * | | |11 = Set to SubM. + * |[11:10] |PIN5 |GPIO Pin 5 Security Attribution Bits + * | | |00 = Set to TZS. + * | | |01 = Set to TZNS. + * | | |10 = Reserved. + * | | |11 = Set to SubM. + * |[13:12] |PIN6 |GPIO Pin 6 Security Attribution Bits + * | | |00 = Set to TZS. + * | | |01 = Set to TZNS. + * | | |10 = Reserved. + * | | |11 = Set to SubM. + * |[15:14] |PIN7 |GPIO Pin 7 Security Attribution Bits + * | | |00 = Set to TZS. + * | | |01 = Set to TZNS. + * | | |10 = Reserved. + * | | |11 = Set to SubM. + * |[17:16] |PIN8 |GPIO Pin 8 Security Attribution Bits + * | | |00 = Set to TZS. + * | | |01 = Set to TZNS. + * | | |10 = Reserved. + * | | |11 = Set to SubM. + * |[19:18] |PIN9 |GPIO Pin 9 Security Attribution Bits + * | | |00 = Set to TZS. + * | | |01 = Set to TZNS. + * | | |10 = Reserved. + * | | |11 = Set to SubM. + * |[21:20] |PIN10 |GPIO Pin 10 Security Attribution Bits + * | | |00 = Set to TZS. + * | | |01 = Set to TZNS. + * | | |10 = Reserved. + * | | |11 = Set to SubM. + * |[23:22] |PIN11 |GPIO Pin 11 Security Attribution Bits + * | | |00 = Set to TZS. + * | | |01 = Set to TZNS. + * | | |10 = Reserved. + * | | |11 = Set to SubM. + * |[25:24] |PIN12 |GPIO Pin 12 Security Attribution Bits + * | | |00 = Set to TZS. + * | | |01 = Set to TZNS. + * | | |10 = Reserved. + * | | |11 = Set to SubM. + * |[27:26] |PIN13 |GPIO Pin 13 Security Attribution Bits + * | | |00 = Set to TZS. + * | | |01 = Set to TZNS. + * | | |10 = Reserved. + * | | |11 = Set to SubM. + * |[29:28] |PIN14 |GPIO Pin 14 Security Attribution Bits + * | | |00 = Set to TZS. + * | | |01 = Set to TZNS. + * | | |10 = Reserved. + * | | |11 = Set to SubM. + * |[31:30] |PIN15 |GPIO Pin 15 Security Attribution Bits + * | | |00 = Set to TZS. + * | | |01 = Set to TZNS. + * | | |10 = Reserved. + * | | |11 = Set to SubM. + * @var SSPCC_T::IOMSSET + * Offset: 0x90 GPIO Port M Security Attribution Set Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[1:0] |PIN0 |GPIO Pin 0 Security Attribution Bits + * | | |00 = Set to TZS. + * | | |01 = Set to TZNS. + * | | |10 = Reserved. + * | | |11 = Set to SubM. + * |[3:2] |PIN1 |GPIO Pin 1 Security Attribution Bits + * | | |00 = Set to TZS. + * | | |01 = Set to TZNS. + * | | |10 = Reserved. + * | | |11 = Set to SubM. + * |[5:4] |PIN2 |GPIO Pin 2 Security Attribution Bits + * | | |00 = Set to TZS. + * | | |01 = Set to TZNS. + * | | |10 = Reserved. + * | | |11 = Set to SubM. + * |[7:6] |PIN3 |GPIO Pin 3 Security Attribution Bits + * | | |00 = Set to TZS. + * | | |01 = Set to TZNS. + * | | |10 = Reserved. + * | | |11 = Set to SubM. + * |[9:8] |PIN4 |GPIO Pin 4 Security Attribution Bits + * | | |00 = Set to TZS. + * | | |01 = Set to TZNS. + * | | |10 = Reserved. + * | | |11 = Set to SubM. + * |[11:10] |PIN5 |GPIO Pin 5 Security Attribution Bits + * | | |00 = Set to TZS. + * | | |01 = Set to TZNS. + * | | |10 = Reserved. + * | | |11 = Set to SubM. + * |[13:12] |PIN6 |GPIO Pin 6 Security Attribution Bits + * | | |00 = Set to TZS. + * | | |01 = Set to TZNS. + * | | |10 = Reserved. + * | | |11 = Set to SubM. + * |[15:14] |PIN7 |GPIO Pin 7 Security Attribution Bits + * | | |00 = Set to TZS. + * | | |01 = Set to TZNS. + * | | |10 = Reserved. + * | | |11 = Set to SubM. + * |[17:16] |PIN8 |GPIO Pin 8 Security Attribution Bits + * | | |00 = Set to TZS. + * | | |01 = Set to TZNS. + * | | |10 = Reserved. + * | | |11 = Set to SubM. + * |[19:18] |PIN9 |GPIO Pin 9 Security Attribution Bits + * | | |00 = Set to TZS. + * | | |01 = Set to TZNS. + * | | |10 = Reserved. + * | | |11 = Set to SubM. + * |[21:20] |PIN10 |GPIO Pin 10 Security Attribution Bits + * | | |00 = Set to TZS. + * | | |01 = Set to TZNS. + * | | |10 = Reserved. + * | | |11 = Set to SubM. + * |[23:22] |PIN11 |GPIO Pin 11 Security Attribution Bits + * | | |00 = Set to TZS. + * | | |01 = Set to TZNS. + * | | |10 = Reserved. + * | | |11 = Set to SubM. + * |[25:24] |PIN12 |GPIO Pin 12 Security Attribution Bits + * | | |00 = Set to TZS. + * | | |01 = Set to TZNS. + * | | |10 = Reserved. + * | | |11 = Set to SubM. + * |[27:26] |PIN13 |GPIO Pin 13 Security Attribution Bits + * | | |00 = Set to TZS. + * | | |01 = Set to TZNS. + * | | |10 = Reserved. + * | | |11 = Set to SubM. + * |[29:28] |PIN14 |GPIO Pin 14 Security Attribution Bits + * | | |00 = Set to TZS. + * | | |01 = Set to TZNS. + * | | |10 = Reserved. + * | | |11 = Set to SubM. + * |[31:30] |PIN15 |GPIO Pin 15 Security Attribution Bits + * | | |00 = Set to TZS. + * | | |01 = Set to TZNS. + * | | |10 = Reserved. + * | | |11 = Set to SubM. + * @var SSPCC_T::IONSSET + * Offset: 0x94 GPIO Port N Security Attribution Set Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[1:0] |PIN0 |GPIO Pin 0 Security Attribution Bits + * | | |00 = Set to TZS. + * | | |01 = Set to TZNS. + * | | |10 = Reserved. + * | | |11 = Set to SubM. + * |[3:2] |PIN1 |GPIO Pin 1 Security Attribution Bits + * | | |00 = Set to TZS. + * | | |01 = Set to TZNS. + * | | |10 = Reserved. + * | | |11 = Set to SubM. + * |[5:4] |PIN2 |GPIO Pin 2 Security Attribution Bits + * | | |00 = Set to TZS. + * | | |01 = Set to TZNS. + * | | |10 = Reserved. + * | | |11 = Set to SubM. + * |[7:6] |PIN3 |GPIO Pin 3 Security Attribution Bits + * | | |00 = Set to TZS. + * | | |01 = Set to TZNS. + * | | |10 = Reserved. + * | | |11 = Set to SubM. + * |[9:8] |PIN4 |GPIO Pin 4 Security Attribution Bits + * | | |00 = Set to TZS. + * | | |01 = Set to TZNS. + * | | |10 = Reserved. + * | | |11 = Set to SubM. + * |[11:10] |PIN5 |GPIO Pin 5 Security Attribution Bits + * | | |00 = Set to TZS. + * | | |01 = Set to TZNS. + * | | |10 = Reserved. + * | | |11 = Set to SubM. + * |[13:12] |PIN6 |GPIO Pin 6 Security Attribution Bits + * | | |00 = Set to TZS. + * | | |01 = Set to TZNS. + * | | |10 = Reserved. + * | | |11 = Set to SubM. + * |[15:14] |PIN7 |GPIO Pin 7 Security Attribution Bits + * | | |00 = Set to TZS. + * | | |01 = Set to TZNS. + * | | |10 = Reserved. + * | | |11 = Set to SubM. + * |[17:16] |PIN8 |GPIO Pin 8 Security Attribution Bits + * | | |00 = Set to TZS. + * | | |01 = Set to TZNS. + * | | |10 = Reserved. + * | | |11 = Set to SubM. + * |[19:18] |PIN9 |GPIO Pin 9 Security Attribution Bits + * | | |00 = Set to TZS. + * | | |01 = Set to TZNS. + * | | |10 = Reserved. + * | | |11 = Set to SubM. + * |[21:20] |PIN10 |GPIO Pin 10 Security Attribution Bits + * | | |00 = Set to TZS. + * | | |01 = Set to TZNS. + * | | |10 = Reserved. + * | | |11 = Set to SubM. + * |[23:22] |PIN11 |GPIO Pin 11 Security Attribution Bits + * | | |00 = Set to TZS. + * | | |01 = Set to TZNS. + * | | |10 = Reserved. + * | | |11 = Set to SubM. + * |[25:24] |PIN12 |GPIO Pin 12 Security Attribution Bits + * | | |00 = Set to TZS. + * | | |01 = Set to TZNS. + * | | |10 = Reserved. + * | | |11 = Set to SubM. + * |[27:26] |PIN13 |GPIO Pin 13 Security Attribution Bits + * | | |00 = Set to TZS. + * | | |01 = Set to TZNS. + * | | |10 = Reserved. + * | | |11 = Set to SubM. + * |[29:28] |PIN14 |GPIO Pin 14 Security Attribution Bits + * | | |00 = Set to TZS. + * | | |01 = Set to TZNS. + * | | |10 = Reserved. + * | | |11 = Set to SubM. + * |[31:30] |PIN15 |GPIO Pin 15 Security Attribution Bits + * | | |00 = Set to TZS. + * | | |01 = Set to TZNS. + * | | |10 = Reserved. + * | | |11 = Set to SubM. + * @var SSPCC_T::SVIEN + * Offset: 0xF0 Security Violation Interrupt Enable Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[0] |APB0 |APB0 Security Violation Interrupt Enable Bit + * | | |0 = Interrupt triggered from security violation of APB0 Disabled. + * | | |1 = Interrupt triggered from security violation of APB0 Enabled. + * |[1] |APB3 |APB3 Security Violation Interrupt Enable Bit + * | | |0 = Interrupt triggered from security violation of APB3 Disabled. + * | | |1 = Interrupt triggered from security violation of APB3 Enabled. + * |[2] |SRAM1 |SRAM1 Security Violation Interrupt Enable Bit + * | | |0 = Interrupt triggered from security violation of SRAM1 Disabled. + * | | |1 = Interrupt triggered from security violation of SRAM1 Enabled. + * |[3] |SDH0 |SD Host0 Security Violation Interrupt Enable Bit + * | | |0 = Interrupt triggered from security violation of SD host 0 Disabled. + * | | |1 = Interrupt triggered from security violation of SD host 0 Enabled. + * |[4] |SDH1 |SD Host1 Security Violation Interrupt Enable Bit + * | | |0 = Interrupt triggered from security violation of SD host 1 Disabled. + * | | |1 = Interrupt triggered from security violation of SD host 1 Enabled. + * |[5] |HSUSBD |HighSpeed USB Device Security Violation Interrupt Enable Bit + * | | |0 = Interrupt triggered from security violation of HighSpeed USB Device Disabled. + * | | |1 = Interrupt triggered from security violation of HighSpeed USB Device Enabled. + * |[6] |NANDC |NAND Controller Security Violation Interrupt Enable Bit + * | | |0 = Interrupt triggered from security violation of NAND Controller Disabled. + * | | |1 = Interrupt triggered from security violation of NAND Controller Enabled. + * |[7] |PDMA0 |PDMA0 Security Violation Interrupt Enable Bit + * | | |0 = Interrupt triggered from security violation of PDMA0 Disabled. + * | | |1 = Interrupt triggered from security violation of PDMA0 Enabled. + * |[8] |PDMA1 |PDMA1 Security Violation Interrupt Enable Bit + * | | |0 = Interrupt triggered from security violation of PDMA1 Disabled. + * | | |1 = Interrupt triggered from security violation of PDMA1 Enabled. + * |[9] |TRNG |TRNG Security Violation Interrupt Enable Bit + * | | |0 = Interrupt triggered from security violation of TRNG Disabled. + * | | |1 = Interrupt triggered from security violation of TRNG Enabled. + * |[10] |CRYPTO |CRYPTO Security Violation Interrupt Enable Bit + * | | |0 = Interrupt triggered from security violation of CRYPTO Disabled. + * | | |1 = Interrupt triggered from security violation of CRYPTO Enabled. + * @var SSPCC_T::SVINTSTS + * Offset: 0xF4 Security Violation Interrupt Status Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[0] |APB0 |APB0 Security Violation Interrupt Status + * | | |0 = No APB0 violation interrupt event. + * | | |1 = There is APB0 violation interrupt event. + * | | |Note: Write 1 to clear the interrupt flag. + * |[1] |APB3 |APB3 Security Violation Interrupt Status + * | | |0 = No APB3 violation interrupt event. + * | | |1 = There is APB3 violation interrupt event. + * | | |Note: Write 1 to clear the interrupt flag. + * |[2] |SRAM1 |SRAM1 Security Violation Interrupt Status + * | | |0 = No SRAM1 violation interrupt event. + * | | |1 = There is SRAM1 violation interrupt event. + * | | |Note: Write 1 to clear the interrupt flag. + * |[3] |SDH0 |SDH0 Security Violation Interrupt Status + * | | |0 = No SDH0 violation interrupt event. + * | | |1 = There is SDH0 violation interrupt event. + * | | |Note: Write 1 to clear the interrupt flag. + * |[4] |SDH1 |SDH1 Security Violation Interrupt Status + * | | |0 = No SDH1 violation interrupt event. + * | | |1 = There is SDH1 violation interrupt event. + * | | |Note: Write 1 to clear the interrupt flag. + * |[5] |HSUSBD |High-speed USB Device Security Violation Interrupt Status + * | | |0 = No High-speed USB Device violation interrupt event. + * | | |1 = There is High-speed USB Device violation interrupt event. + * | | |Note: Write 1 to clear the interrupt flag. + * |[6] |NANDC |NAND Controller Security Violation Interrupt Status + * | | |0 = No NAND Controller violation interrupt event. + * | | |1 = There is NAND Controller violation interrupt event. + * | | |Note: Write 1 to clear the interrupt flag. + * |[7] |PDMA0 |PDMA0 Security Violation Interrupt Status + * | | |0 = No PDMA0 violation interrupt event. + * | | |1 = There is PDMA0 violation interrupt event. + * | | |Note: Write 1 to clear the interrupt flag. + * |[8] |PDMA1 |PDMA1 Security Violation Interrupt Status + * | | |0 = No PDMA1 violation interrupt event. + * | | |1 = There is PDMA1 violation interrupt event. + * | | |Note: Write 1 to clear the interrupt flag. + * |[9] |TRNG |TRNG Security Violation Interrupt Status + * | | |0 = No TRNG violation interrupt event. + * | | |1 = There is TRNG violation interrupt event. + * | | |Note: Write 1 to clear the interrupt flag. + * |[10] |CRYPTO |CRYPTO Security Violation Interrupt Status + * | | |0 = No CRYPTO violation interrupt event. + * | | |1 = There is CRYPTO violation interrupt event. + * | | |Note: Write 1 to clear the interrupt flag. + * @var SSPCC_T::APB0VSRC + * Offset: 0x100 APB0 Security Policy Violation Source + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[3:0] |MASTER |Master Violating Security Policy + * | | |Indicate which master invokes the security violation. + * | | |0x0 = CA35. + * | | |0x1 = CoreSight AP. + * | | |0x3 = Crypto Engine + * | | |0x2 = CM4. + * | | |0x4 = PDMA0. + * | | |0x5 = PDMA1. + * | | |0x6 = PDMA2. + * | | |0x7 = PDMA3. + * | | |0x8 = SDH0. + * | | |0x9 = SDH1. + * | | |0xA = USBH2. + * | | |0xB = USBH0/HSUSBH0. + * | | |0xC = USBH1/HSUSBH1. + * | | |0xD = HSUSBD. + * | | |0xE = NAND. + * | | |Others is undefined. + * @var SSPCC_T::APB3VSRC + * Offset: 0x104 APB3 Security Policy Violation Source + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[3:0] |MASTER |Master Violating Security Policy + * | | |Indicate which master invokes the security violation. + * | | |0x0 = CA35. + * | | |0x1 = CoreSight AP. + * | | |0x3 = Crypto Engine + * | | |0x2 = CM4. + * | | |0x4 = PDMA0. + * | | |0x5 = PDMA1. + * | | |0x6 = PDMA2. + * | | |0x7 = PDMA3. + * | | |0x8 = SDH0. + * | | |0x9 = SDH1. + * | | |0xA = USBH2. + * | | |0xB = USBH0/HSUSBH0. + * | | |0xC = USBH1/HSUSBH1. + * | | |0xD = HSUSBD. + * | | |0xE = NAND. + * | | |Others is undefined. + * @var SSPCC_T::SRAM1VSRC + * Offset: 0x108 SRAM1 Security Policy Violation Source + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[3:0] |MASTER |Master Violating Security Policy + * | | |Indicate which master invokes the security violation. + * | | |0x0 = CA35. + * | | |0x1 = CoreSight AP. + * | | |0x3 = Crypto Engine + * | | |0x2 = CM4. + * | | |0x4 = PDMA0. + * | | |0x5 = PDMA1. + * | | |0x6 = PDMA2. + * | | |0x7 = PDMA3. + * | | |0x8 = SDH0. + * | | |0x9 = SDH1. + * | | |0xA = USBH2. + * | | |0xB = USBH0/HSUSBH0. + * | | |0xC = USBH1/HSUSBH1. + * | | |0xD = HSUSBD. + * | | |0xE = NAND. + * | | |Others is undefined. + * @var SSPCC_T::SDH0VSRC + * Offset: 0x10C SDH0 Security Policy Violation Source + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[3:0] |MASTER |Master Violating Security Policy + * | | |Indicate which master invokes the security violation. + * | | |0x0 = CA35. + * | | |0x1 = CoreSight AP. + * | | |0x3 = Crypto Engine + * | | |0x2 = CM4. + * | | |0x4 = PDMA0. + * | | |0x5 = PDMA1. + * | | |0x6 = PDMA2. + * | | |0x7 = PDMA3. + * | | |0x8 = SDH0. + * | | |0x9 = SDH1. + * | | |0xA = USBH2. + * | | |0xB = USBH0/HSUSBH0. + * | | |0xC = USBH1/HSUSBH1. + * | | |0xD = HSUSBD. + * | | |0xE = NAND. + * | | |Others is undefined. + * @var SSPCC_T::SDH1VSRC + * Offset: 0x110 SDH1 Security Policy Violation Source + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[3:0] |MASTER |Master Violating Security Policy + * | | |Indicate which master invokes the security violation. + * | | |0x0 = CA35. + * | | |0x1 = CoreSight AP. + * | | |0x3 = Crypto Engine + * | | |0x2 = CM4. + * | | |0x4 = PDMA0. + * | | |0x5 = PDMA1. + * | | |0x6 = PDMA2. + * | | |0x7 = PDMA3. + * | | |0x8 = SDH0. + * | | |0x9 = SDH1. + * | | |0xA = USBH2. + * | | |0xB = USBH0/HSUSBH0. + * | | |0xC = USBH1/HSUSBH1. + * | | |0xD = HSUSBD. + * | | |0xE = NAND. + * | | |Others is undefined. + * @var SSPCC_T::HSUSBDVSRC + * Offset: 0x114 HSUSBD Security Policy Violation Source + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[3:0] |MASTER |Master Violating Security Policy + * | | |Indicate which master invokes the security violation. + * | | |0x0 = CA35. + * | | |0x1 = CoreSight AP. + * | | |0x3 = Crypto Engine + * | | |0x2 = CM4. + * | | |0x4 = PDMA0. + * | | |0x5 = PDMA1. + * | | |0x6 = PDMA2. + * | | |0x7 = PDMA3. + * | | |0x8 = SDH0. + * | | |0x9 = SDH1. + * | | |0xA = USBH2. + * | | |0xB = USBH0/HSUSBH0. + * | | |0xC = USBH1/HSUSBH1. + * | | |0xD = HSUSBD. + * | | |0xE = NAND. + * | | |Others is undefined. + * @var SSPCC_T::NANDCVSRC + * Offset: 0x118 NANDC Security Policy Violation Source + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[3:0] |MASTER |Master Violating Security Policy + * | | |Indicate which master invokes the security violation. + * | | |0x0 = CA35. + * | | |0x1 = CoreSight AP. + * | | |0x3 = Crypto Engine + * | | |0x2 = CM4. + * | | |0x4 = PDMA0. + * | | |0x5 = PDMA1. + * | | |0x6 = PDMA2. + * | | |0x7 = PDMA3. + * | | |0x8 = SDH0. + * | | |0x9 = SDH1. + * | | |0xA = USBH2. + * | | |0xB = USBH0/HSUSBH0. + * | | |0xC = USBH1/HSUSBH1. + * | | |0xD = HSUSBD. + * | | |0xE = NAND. + * | | |Others is undefined. + * @var SSPCC_T::PDMA0VSRC + * Offset: 0x11C PDMA0 Security Policy Violation Source + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[3:0] |MASTER |Master Violating Security Policy + * | | |Indicate which master invokes the security violation. + * | | |0x0 = CA35. + * | | |0x1 = CoreSight AP. + * | | |0x3 = Crypto Engine + * | | |0x2 = CM4. + * | | |0x4 = PDMA0. + * | | |0x5 = PDMA1. + * | | |0x6 = PDMA2. + * | | |0x7 = PDMA3. + * | | |0x8 = SDH0. + * | | |0x9 = SDH1. + * | | |0xA = USBH2. + * | | |0xB = USBH0/HSUSBH0. + * | | |0xC = USBH1/HSUSBH1. + * | | |0xD = HSUSBD. + * | | |0xE = NAND. + * | | |Others is undefined. + * @var SSPCC_T::PDMA1VSRC + * Offset: 0x120 PDMA1 Security Policy Violation Source + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[3:0] |MASTER |Master Violating Security Policy + * | | |Indicate which master invokes the security violation. + * | | |0x0 = CA35. + * | | |0x1 = CoreSight AP. + * | | |0x3 = Crypto Engine + * | | |0x2 = CM4. + * | | |0x4 = PDMA0. + * | | |0x5 = PDMA1. + * | | |0x6 = PDMA2. + * | | |0x7 = PDMA3. + * | | |0x8 = SDH0. + * | | |0x9 = SDH1. + * | | |0xA = USBH2. + * | | |0xB = USBH0/HSUSBH0. + * | | |0xC = USBH1/HSUSBH1. + * | | |0xD = HSUSBD. + * | | |0xE = NAND. + * | | |Others is undefined. + * @var SSPCC_T::TRNGVSRC + * Offset: 0x124 TRNG Security Policy Violation Source + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[3:0] |MASTER |Master Violating Security Policy + * | | |Indicate which master invokes the security violation. + * | | |0x0 = CA35. + * | | |0x1 = CoreSight AP. + * | | |0x3 = Crypto Engine + * | | |0x2 = CM4. + * | | |0x4 = PDMA0. + * | | |0x5 = PDMA1. + * | | |0x6 = PDMA2. + * | | |0x7 = PDMA3. + * | | |0x8 = SDH0. + * | | |0x9 = SDH1. + * | | |0xA = USBH2. + * | | |0xB = USBH0/HSUSBH0. + * | | |0xC = USBH1/HSUSBH1. + * | | |0xD = HSUSBD. + * | | |0xE = NAND. + * | | |Others is undefined. + * @var SSPCC_T::CRYPTOVSRC + * Offset: 0x128 CRYPTO Security Policy Violation Source + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[3:0] |MASTER |Master Violating Security Policy + * | | |Indicate which master invokes the security violation. + * | | |0x0 = CA35. + * | | |0x1 = CoreSight AP. + * | | |0x3 = Crypto Engine + * | | |0x2 = CM4. + * | | |0x4 = PDMA0. + * | | |0x5 = PDMA1. + * | | |0x6 = PDMA2. + * | | |0x7 = PDMA3. + * | | |0x8 = SDH0. + * | | |0x9 = SDH1. + * | | |0xA = USBH2. + * | | |0xB = USBH0/HSUSBH0. + * | | |0xC = USBH1/HSUSBH1. + * | | |0xD = HSUSBD. + * | | |0xE = NAND. + * | | |Others is undefined. + * @var SSPCC_T::APB0VA + * Offset: 0x180 APB0 Security Policy Violation Address + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[31:0] |VIOADDR |Violation Address + * | | |Indicate the target address of the access, which invokes the security violation. + * @var SSPCC_T::APB3VA + * Offset: 0x184 APB3 Security Policy Violation Address + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[31:0] |VIOADDR |Violation Address + * | | |Indicate the target address of the access, which invokes the security violation. + * @var SSPCC_T::SRAM1VA + * Offset: 0x188 SRAM1 Security Policy Violation Address + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[31:0] |VIOADDR |Violation Address + * | | |Indicate the target address of the access, which invokes the security violation. + * @var SSPCC_T::SDH0VA + * Offset: 0x18C SDH0 Security Policy Violation Address + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[31:0] |VIOADDR |Violation Address + * | | |Indicate the target address of the access, which invokes the security violation. + * @var SSPCC_T::SDH1VA + * Offset: 0x190 SDH1 Security Policy Violation Address + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[31:0] |VIOADDR |Violation Address + * | | |Indicate the target address of the access, which invokes the security violation. + * @var SSPCC_T::HSUSBDVA + * Offset: 0x194 HSUSBD Security Policy Violation Address + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[31:0] |VIOADDR |Violation Address + * | | |Indicate the target address of the access, which invokes the security violation. + * @var SSPCC_T::NANDCVA + * Offset: 0x198 NANDC Security Policy Violation Address + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[31:0] |VIOADDR |Violation Address + * | | |Indicate the target address of the access, which invokes the security violation. + * @var SSPCC_T::PDMA0VA + * Offset: 0x19C PDMA0 Security Policy Violation Address + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[31:0] |VIOADDR |Violation Address + * | | |Indicate the target address of the access, which invokes the security violation. + * @var SSPCC_T::PDMA1VA + * Offset: 0x1A0 PDMA1 Security Policy Violation Address + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[31:0] |VIOADDR |Violation Address + * | | |Indicate the target address of the access, which invokes the security violation. + * @var SSPCC_T::TRNGVA + * Offset: 0x1A4 TRNG Security Policy Violation Address + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[31:0] |VIOADDR |Violation Address + * | | |Indicate the target address of the access, which invokes the security violation. + * @var SSPCC_T::CRYPTOVA + * Offset: 0x1A8 CRYPTO Security Policy Violation Address + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[31:0] |VIOADDR |Violation Address + * | | |Indicate the target address of the access, which invokes the security violation. + * @var SSPCC_T::SINFAEN + * Offset: 0x200 Shared Information Access Enable Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[0] |SSPCCSIAEN|SSPCC Shared Information Access Enable Bit + * | | |0 = SSPCC shared information Disabled. + * | | |1 = SSPCC shared information Enabled. + * |[1] |SYSSIAEN |SYS Shared Information Access Enable Bit + * | | |0 = SYS shared information Disabled. + * | | |1 = SYS shared information Enabled. + * | | |Note: Include clock information. + * |[2] |RTCSIAEN |RTC Shared Information Access Enable Bit + * | | |0 = RTC shared information Disabled. + * | | |1 = RTC shared information Enabled. + * |[6] |OTPSIAEN |OTP Controller Shared Information Access Enable Bit + * | | |0 = OTP controller shared information Disabled. + * | | |1 = OTP controller shared information Enabled. + * |[7] |KSSIAEN |Key Store Shared Information Access Enable Bit + * | | |0 = Key Store shared information Disabled. + * | | |1 = Key Store shared information Enabled. + * @var SSPCC_T::SCWP + * Offset: 0x204 Security Configuration Write Protection Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[0] |ENABLE |Write Protection Enable Bit + * | | |0 = Write Protection Disabled. + * | | |1 = Write Protection Enabled. + * |[1] |LOCK |Enable Write Protection Lock Bit (Write Once) + * | | |0 = Write protection lock Disabled. + * | | |1 = Write protection Enabled and locked. + * | | |Note: This bit cannot be cleared to 0 after set to 1. + * |[31:16] |WVCODE |Write Verify Code + * | | |Read operation: + * | | |Reserved, all zeros. + * | | |Write operation: + * | | |0x475A = The write verify code, 0x475A, is needed to do a valid write to SSPCC_SCWP. + * | | |Others = Invalid write verify code. + */ + __IO uint32_t PSSET0; /*!< [0x0000] Peripheral Security Attribution Set Register 0 (0x4000_0000~0x400F_FFFF) */ + __IO uint32_t PSSET1; /*!< [0x0004] Peripheral Security Attribution Set Register 1 (0x4010_0000~0x401F_FFFF) */ + __IO uint32_t PSSET2; /*!< [0x0008] Peripheral Security Attribution Set Register 2 (0x4020_0000~0x402F_FFFF) */ + __IO uint32_t PSSET3; /*!< [0x000c] Peripheral Security Attribution Set Register 3 (0x4030_0000~0x403F_FFFF) */ + __IO uint32_t PSSET4; /*!< [0x0010] Peripheral Security Attribution Set Register 4 (0x4040_0000~0x404F_FFFF) */ + __IO uint32_t PSSET5; /*!< [0x0014] Peripheral Security Attribution Set Register 5 (0x4050_0000~0x405F_FFFF) */ + __IO uint32_t PSSET6; /*!< [0x0018] Peripheral Security Attribution Set Register 6 (0x4060_0000~0x406F_FFFF) */ + __IO uint32_t PSSET7; /*!< [0x001c] Peripheral Security Attribution Set Register 7 (0x4070_0000~0x407F_FFFF) */ + __IO uint32_t PSSET8; /*!< [0x0020] Peripheral Security Attribution Set Register 8 (0x4080_0000~0x408F_FFFF) */ + __IO uint32_t PSSET9; /*!< [0x0024] Peripheral Security Attribution Set Register 9 (0x4090_0000~0x409F_FFFF) */ + __IO uint32_t PSSET10; /*!< [0x0028] Peripheral Security Attribution Set Register 10 (0x40A0_0000~0x40AF_FFFF) */ + __IO uint32_t PSSET11; /*!< [0x002c] Peripheral Security Attribution Set Register 11 (0x40B0_0000~0x40BF_FFFF) */ + __I uint32_t RESERVE0[4]; + __IO uint32_t SRAMSB; /*!< [0x0040] SRAM Security Boundary Set Register */ + __I uint32_t RESERVE1[3]; + __IO uint32_t EBISSET; /*!< [0x0050] EBI Memory Security Set Register */ + __I uint32_t RESERVE2[3]; + __IO uint32_t IOASSET; /*!< [0x0060] GPIO Port A Security Attribution Set Register */ + __IO uint32_t IOBSSET; /*!< [0x0064] GPIO Port B Security Attribution Set Register */ + __IO uint32_t IOCSSET; /*!< [0x0068] GPIO Port C Security Attribution Set Register */ + __IO uint32_t IODSSET; /*!< [0x006c] GPIO Port D Security Attribution Set Register */ + __IO uint32_t IOESSET; /*!< [0x0070] GPIO Port E Security Attribution Set Register */ + __IO uint32_t IOFSSET; /*!< [0x0074] GPIO Port F Security Attribution Set Register */ + __IO uint32_t IOGSSET; /*!< [0x0078] GPIO Port G Security Attribution Set Register */ + __IO uint32_t IOHSSET; /*!< [0x007c] GPIO Port H Security Attribution Set Register */ + __IO uint32_t IOISSET; /*!< [0x0080] GPIO Port I Security Attribution Set Register */ + __IO uint32_t IOJSSET; /*!< [0x0084] GPIO Port J Security Attribution Set Register */ + __IO uint32_t IOKSSET; /*!< [0x0088] GPIO Port K Security Attribution Set Register */ + __IO uint32_t IOLSSET; /*!< [0x008c] GPIO Port L Security Attribution Set Register */ + __IO uint32_t IOMSSET; /*!< [0x0090] GPIO Port M Security Attribution Set Register */ + __IO uint32_t IONSSET; /*!< [0x0094] GPIO Port N Security Attribution Set Register */ + __I uint32_t RESERVE3[22]; + __IO uint32_t SVIEN; /*!< [0x00f0] Security Violation Interrupt Enable Register */ + __IO uint32_t SVINTSTS; /*!< [0x00f4] Security Violation Interrupt Status Register */ + __I uint32_t RESERVE4[2]; + __I uint32_t APB0VSRC; /*!< [0x0100] APB0 Security Policy Violation Source */ + __I uint32_t APB3VSRC; /*!< [0x0104] APB3 Security Policy Violation Source */ + __I uint32_t SRAM1VSRC; /*!< [0x0108] SRAM1 Security Policy Violation Source */ + __I uint32_t SDH0VSRC; /*!< [0x010c] SDH0 Security Policy Violation Source */ + __I uint32_t SDH1VSRC; /*!< [0x0110] SDH1 Security Policy Violation Source */ + __I uint32_t HSUSBDVSRC; /*!< [0x0114] HSUSBD Security Policy Violation Source */ + __I uint32_t NANDCVSRC; /*!< [0x0118] NANDC Security Policy Violation Source */ + __I uint32_t PDMA0VSRC; /*!< [0x011c] PDMA0 Security Policy Violation Source */ + __I uint32_t PDMA1VSRC; /*!< [0x0120] PDMA1 Security Policy Violation Source */ + __I uint32_t TRNGVSRC; /*!< [0x0124] TRNG Security Policy Violation Source */ + __I uint32_t CRYPTOVSRC; /*!< [0x0128] CRYPTO Security Policy Violation Source */ + __I uint32_t RESERVE5[21]; + __I uint32_t APB0VA; /*!< [0x0180] APB0 Security Policy Violation Address */ + __I uint32_t APB3VA; /*!< [0x0184] APB3 Security Policy Violation Address */ + __I uint32_t SRAM1VA; /*!< [0x0188] SRAM1 Security Policy Violation Address */ + __I uint32_t SDH0VA; /*!< [0x018c] SDH0 Security Policy Violation Address */ + __I uint32_t SDH1VA; /*!< [0x0190] SDH1 Security Policy Violation Address */ + __I uint32_t HSUSBDVA; /*!< [0x0194] HSUSBD Security Policy Violation Address */ + __I uint32_t NANDCVA; /*!< [0x0198] NANDC Security Policy Violation Address */ + __I uint32_t PDMA0VA; /*!< [0x019c] PDMA0 Security Policy Violation Address */ + __I uint32_t PDMA1VA; /*!< [0x01a0] PDMA1 Security Policy Violation Address */ + __I uint32_t TRNGVA; /*!< [0x01a4] TRNG Security Policy Violation Address */ + __I uint32_t CRYPTOVA; /*!< [0x01a8] CRYPTO Security Policy Violation Address */ + __I uint32_t RESERVE6[21]; + __IO uint32_t SINFAEN; /*!< [0x0200] Shared Information Access Enable Register */ + __IO uint32_t SCWP; /*!< [0x0204] Security Configuration Write Protection Register */ + +} SSPCC_T; + +/** + @addtogroup SSPCC_CONST SSPCC Bit Field Definition + Constant Definitions for SSPCC Controller +@{ */ + +#define SSPCC_PSSET0_PDMA0_Pos (16) /*!< SSPCC_T::PSSET0: PDMA0 Position */ +#define SSPCC_PSSET0_PDMA0_Msk (0x3ul << SSPCC_PSSET0_PDMA0_Pos) /*!< SSPCC_T::PSSET0: PDMA0 Mask */ + +#define SSPCC_PSSET0_PDMA1_Pos (18) /*!< SSPCC_T::PSSET0: PDMA1 Position */ +#define SSPCC_PSSET0_PDMA1_Msk (0x3ul << SSPCC_PSSET0_PDMA1_Pos) /*!< SSPCC_T::PSSET0: PDMA1 Mask */ + +#define SSPCC_PSSET0_PDMA2_Pos (20) /*!< SSPCC_T::PSSET0: PDMA2 Position */ +#define SSPCC_PSSET0_PDMA2_Msk (0x3ul << SSPCC_PSSET0_PDMA2_Pos) /*!< SSPCC_T::PSSET0: PDMA2 Mask */ + +#define SSPCC_PSSET0_PDMA3_Pos (22) /*!< SSPCC_T::PSSET0: PDMA3 Position */ +#define SSPCC_PSSET0_PDMA3_Msk (0x3ul << SSPCC_PSSET0_PDMA3_Pos) /*!< SSPCC_T::PSSET0: PDMA3 Mask */ + +#define SSPCC_PSSET1_EBI_Pos (0) /*!< SSPCC_T::PSSET1: EBI Position */ +#define SSPCC_PSSET1_EBI_Msk (0x3ul << SSPCC_PSSET1_EBI_Pos) /*!< SSPCC_T::PSSET1: EBI Mask */ + +#define SSPCC_PSSET1_SDH0_Pos (16) /*!< SSPCC_T::PSSET1: SDH0 Position */ +#define SSPCC_PSSET1_SDH0_Msk (0x3ul << SSPCC_PSSET1_SDH0_Pos) /*!< SSPCC_T::PSSET1: SDH0 Mask */ + +#define SSPCC_PSSET1_SDH1_Pos (18) /*!< SSPCC_T::PSSET1: SDH1 Position */ +#define SSPCC_PSSET1_SDH1_Msk (0x3ul << SSPCC_PSSET1_SDH1_Pos) /*!< SSPCC_T::PSSET1: SDH1 Mask */ + +#define SSPCC_PSSET1_NANDC_Pos (20) /*!< SSPCC_T::PSSET1: NANDC Position */ +#define SSPCC_PSSET1_NANDC_Msk (0x3ul << SSPCC_PSSET1_NANDC_Pos) /*!< SSPCC_T::PSSET1: NANDC Mask */ + +#define SSPCC_PSSET2_HSUSBD_Pos (0) /*!< SSPCC_T::PSSET2: HSUSBD Position */ +#define SSPCC_PSSET2_HSUSBD_Msk (0x3ul << SSPCC_PSSET2_HSUSBD_Pos) /*!< SSPCC_T::PSSET2: HSUSBD Mask */ + +#define SSPCC_PSSET3_CRYPTO_Pos (0) /*!< SSPCC_T::PSSET3: CRYPTO Position */ +#define SSPCC_PSSET3_CRYPTO_Msk (0x3ul << SSPCC_PSSET3_CRYPTO_Pos) /*!< SSPCC_T::PSSET3: CRYPTO Mask */ + +#define SSPCC_PSSET3_CANFD0_Pos (24) /*!< SSPCC_T::PSSET3: CANFD0 Position */ +#define SSPCC_PSSET3_CANFD0_Msk (0x3ul << SSPCC_PSSET3_CANFD0_Pos) /*!< SSPCC_T::PSSET3: CANFD0 Mask */ + +#define SSPCC_PSSET3_CANFD1_Pos (26) /*!< SSPCC_T::PSSET3: CANFD1 Position */ +#define SSPCC_PSSET3_CANFD1_Msk (0x3ul << SSPCC_PSSET3_CANFD1_Pos) /*!< SSPCC_T::PSSET3: CANFD1 Mask */ + +#define SSPCC_PSSET3_CANFD2_Pos (28) /*!< SSPCC_T::PSSET3: CANFD2 Position */ +#define SSPCC_PSSET3_CANFD2_Msk (0x3ul << SSPCC_PSSET3_CANFD2_Pos) /*!< SSPCC_T::PSSET3: CANFD2 Mask */ + +#define SSPCC_PSSET3_CANFD3_Pos (30) /*!< SSPCC_T::PSSET3: CANFD3 Position */ +#define SSPCC_PSSET3_CANFD3_Msk (0x3ul << SSPCC_PSSET3_CANFD3_Pos) /*!< SSPCC_T::PSSET3: CANFD3 Mask */ + +#define SSPCC_PSSET4_ADC0_Pos (4) /*!< SSPCC_T::PSSET4: ADC0 Position */ +#define SSPCC_PSSET4_ADC0_Msk (0x3ul << SSPCC_PSSET4_ADC0_Pos) /*!< SSPCC_T::PSSET4: ADC0 Mask */ + +#define SSPCC_PSSET4_EADC0_Pos (6) /*!< SSPCC_T::PSSET4: EADC0 Position */ +#define SSPCC_PSSET4_EADC0_Msk (0x3ul << SSPCC_PSSET4_EADC0_Pos) /*!< SSPCC_T::PSSET4: EADC0 Mask */ + +#define SSPCC_PSSET4_WDTWWDT1_Pos (8) /*!< SSPCC_T::PSSET4: WDTWWDT1 Position */ +#define SSPCC_PSSET4_WDTWWDT1_Msk (0x3ul << SSPCC_PSSET4_WDTWWDT1_Pos) /*!< SSPCC_T::PSSET4: WDTWWDT1 Mask */ + +#define SSPCC_PSSET4_I2S0_Pos (16) /*!< SSPCC_T::PSSET4: I2S0 Position */ +#define SSPCC_PSSET4_I2S0_Msk (0x3ul << SSPCC_PSSET4_I2S0_Pos) /*!< SSPCC_T::PSSET4: I2S0 Mask */ + +#define SSPCC_PSSET4_I2S1_Pos (18) /*!< SSPCC_T::PSSET4: I2S1 Position */ +#define SSPCC_PSSET4_I2S1_Msk (0x3ul << SSPCC_PSSET4_I2S1_Pos) /*!< SSPCC_T::PSSET4: I2S1 Mask */ + +#define SSPCC_PSSET4_KPI_Pos (20) /*!< SSPCC_T::PSSET4: KPI Position */ +#define SSPCC_PSSET4_KPI_Msk (0x3ul << SSPCC_PSSET4_KPI_Pos) /*!< SSPCC_T::PSSET4: KPI Mask */ + +#define SSPCC_PSSET4_DDRPHYPUB_Pos (24) /*!< SSPCC_T::PSSET4: DDRPHYPUB Position */ +#define SSPCC_PSSET4_DDRPHYPUB_Msk (0x3ul << SSPCC_PSSET4_DDRPHYPUB_Pos) /*!< SSPCC_T::PSSET4: DDRPHYPUB Mask */ + +#define SSPCC_PSSET4_MCTL_Pos (26) /*!< SSPCC_T::PSSET4: MCTL Position */ +#define SSPCC_PSSET4_MCTL_Msk (0x3ul << SSPCC_PSSET4_MCTL_Pos) /*!< SSPCC_T::PSSET4: MCTL Mask */ + +#define SSPCC_PSSET5_TMR01_Pos (0) /*!< SSPCC_T::PSSET5: TMR01 Position */ +#define SSPCC_PSSET5_TMR01_Msk (0x3ul << SSPCC_PSSET5_TMR01_Pos) /*!< SSPCC_T::PSSET5: TMR01 Mask */ + +#define SSPCC_PSSET5_TMR23_Pos (2) /*!< SSPCC_T::PSSET5: TMR23 Position */ +#define SSPCC_PSSET5_TMR23_Msk (0x3ul << SSPCC_PSSET5_TMR23_Pos) /*!< SSPCC_T::PSSET5: TMR23 Mask */ + +#define SSPCC_PSSET5_TMR45_Pos (4) /*!< SSPCC_T::PSSET5: TMR45 Position */ +#define SSPCC_PSSET5_TMR45_Msk (0x3ul << SSPCC_PSSET5_TMR45_Pos) /*!< SSPCC_T::PSSET5: TMR45 Mask */ + +#define SSPCC_PSSET5_TMR67_Pos (6) /*!< SSPCC_T::PSSET5: TMR67 Position */ +#define SSPCC_PSSET5_TMR67_Msk (0x3ul << SSPCC_PSSET5_TMR67_Pos) /*!< SSPCC_T::PSSET5: TMR67 Mask */ + +#define SSPCC_PSSET5_TMR89_Pos (8) /*!< SSPCC_T::PSSET5: TMR89 Position */ +#define SSPCC_PSSET5_TMR89_Msk (0x3ul << SSPCC_PSSET5_TMR89_Pos) /*!< SSPCC_T::PSSET5: TMR89 Mask */ + +#define SSPCC_PSSET5_TMR1011_Pos (10) /*!< SSPCC_T::PSSET5: TMR1011 Position */ +#define SSPCC_PSSET5_TMR1011_Msk (0x3ul << SSPCC_PSSET5_TMR1011_Pos) /*!< SSPCC_T::PSSET5: TMR1011 Mask */ + +#define SSPCC_PSSET5_EPWM0_Pos (16) /*!< SSPCC_T::PSSET5: EPWM0 Position */ +#define SSPCC_PSSET5_EPWM0_Msk (0x3ul << SSPCC_PSSET5_EPWM0_Pos) /*!< SSPCC_T::PSSET5: EPWM0 Mask */ + +#define SSPCC_PSSET5_EPWM1_Pos (18) /*!< SSPCC_T::PSSET5: EPWM1 Position */ +#define SSPCC_PSSET5_EPWM1_Msk (0x3ul << SSPCC_PSSET5_EPWM1_Pos) /*!< SSPCC_T::PSSET5: EPWM1 Mask */ + +#define SSPCC_PSSET5_EPWM2_Pos (20) /*!< SSPCC_T::PSSET5: EPWM2 Position */ +#define SSPCC_PSSET5_EPWM2_Msk (0x3ul << SSPCC_PSSET5_EPWM2_Pos) /*!< SSPCC_T::PSSET5: EPWM2 Mask */ + +#define SSPCC_PSSET6_SPI0_Pos (0) /*!< SSPCC_T::PSSET6: SPI0 Position */ +#define SSPCC_PSSET6_SPI0_Msk (0x3ul << SSPCC_PSSET6_SPI0_Pos) /*!< SSPCC_T::PSSET6: SPI0 Mask */ + +#define SSPCC_PSSET6_SPI1_Pos (2) /*!< SSPCC_T::PSSET6: SPI1 Position */ +#define SSPCC_PSSET6_SPI1_Msk (0x3ul << SSPCC_PSSET6_SPI1_Pos) /*!< SSPCC_T::PSSET6: SPI1 Mask */ + +#define SSPCC_PSSET6_SPI2_Pos (4) /*!< SSPCC_T::PSSET6: SPI2 Position */ +#define SSPCC_PSSET6_SPI2_Msk (0x3ul << SSPCC_PSSET6_SPI2_Pos) /*!< SSPCC_T::PSSET6: SPI2 Mask */ + +#define SSPCC_PSSET6_SPI3_Pos (6) /*!< SSPCC_T::PSSET6: SPI3 Position */ +#define SSPCC_PSSET6_SPI3_Msk (0x3ul << SSPCC_PSSET6_SPI3_Pos) /*!< SSPCC_T::PSSET6: SPI3 Mask */ + +#define SSPCC_PSSET6_QSPI0_Pos (16) /*!< SSPCC_T::PSSET6: QSPI0 Position */ +#define SSPCC_PSSET6_QSPI0_Msk (0x3ul << SSPCC_PSSET6_QSPI0_Pos) /*!< SSPCC_T::PSSET6: QSPI0 Mask */ + +#define SSPCC_PSSET6_QSPI1_Pos (18) /*!< SSPCC_T::PSSET6: QSPI1 Position */ +#define SSPCC_PSSET6_QSPI1_Msk (0x3ul << SSPCC_PSSET6_QSPI1_Pos) /*!< SSPCC_T::PSSET6: QSPI1 Mask */ + +#define SSPCC_PSSET7_UART0_Pos (0) /*!< SSPCC_T::PSSET7: UART0 Position */ +#define SSPCC_PSSET7_UART0_Msk (0x3ul << SSPCC_PSSET7_UART0_Pos) /*!< SSPCC_T::PSSET7: UART0 Mask */ + +#define SSPCC_PSSET7_UART1_Pos (2) /*!< SSPCC_T::PSSET7: UART1 Position */ +#define SSPCC_PSSET7_UART1_Msk (0x3ul << SSPCC_PSSET7_UART1_Pos) /*!< SSPCC_T::PSSET7: UART1 Mask */ + +#define SSPCC_PSSET7_UART2_Pos (4) /*!< SSPCC_T::PSSET7: UART2 Position */ +#define SSPCC_PSSET7_UART2_Msk (0x3ul << SSPCC_PSSET7_UART2_Pos) /*!< SSPCC_T::PSSET7: UART2 Mask */ + +#define SSPCC_PSSET7_UART3_Pos (6) /*!< SSPCC_T::PSSET7: UART3 Position */ +#define SSPCC_PSSET7_UART3_Msk (0x3ul << SSPCC_PSSET7_UART3_Pos) /*!< SSPCC_T::PSSET7: UART3 Mask */ + +#define SSPCC_PSSET7_UART4_Pos (8) /*!< SSPCC_T::PSSET7: UART4 Position */ +#define SSPCC_PSSET7_UART4_Msk (0x3ul << SSPCC_PSSET7_UART4_Pos) /*!< SSPCC_T::PSSET7: UART4 Mask */ + +#define SSPCC_PSSET7_UART5_Pos (10) /*!< SSPCC_T::PSSET7: UART5 Position */ +#define SSPCC_PSSET7_UART5_Msk (0x3ul << SSPCC_PSSET7_UART5_Pos) /*!< SSPCC_T::PSSET7: UART5 Mask */ + +#define SSPCC_PSSET7_UART6_Pos (12) /*!< SSPCC_T::PSSET7: UART6 Position */ +#define SSPCC_PSSET7_UART6_Msk (0x3ul << SSPCC_PSSET7_UART6_Pos) /*!< SSPCC_T::PSSET7: UART6 Mask */ + +#define SSPCC_PSSET7_UART7_Pos (14) /*!< SSPCC_T::PSSET7: UART7 Position */ +#define SSPCC_PSSET7_UART7_Msk (0x3ul << SSPCC_PSSET7_UART7_Pos) /*!< SSPCC_T::PSSET7: UART7 Mask */ + +#define SSPCC_PSSET7_UART8_Pos (16) /*!< SSPCC_T::PSSET7: UART8 Position */ +#define SSPCC_PSSET7_UART8_Msk (0x3ul << SSPCC_PSSET7_UART8_Pos) /*!< SSPCC_T::PSSET7: UART8 Mask */ + +#define SSPCC_PSSET7_UART9_Pos (18) /*!< SSPCC_T::PSSET7: UART9 Position */ +#define SSPCC_PSSET7_UART9_Msk (0x3ul << SSPCC_PSSET7_UART9_Pos) /*!< SSPCC_T::PSSET7: UART9 Mask */ + +#define SSPCC_PSSET7_UART10_Pos (20) /*!< SSPCC_T::PSSET7: UART10 Position */ +#define SSPCC_PSSET7_UART10_Msk (0x3ul << SSPCC_PSSET7_UART10_Pos) /*!< SSPCC_T::PSSET7: UART10 Mask */ + +#define SSPCC_PSSET7_UART11_Pos (22) /*!< SSPCC_T::PSSET7: UART11 Position */ +#define SSPCC_PSSET7_UART11_Msk (0x3ul << SSPCC_PSSET7_UART11_Pos) /*!< SSPCC_T::PSSET7: UART11 Mask */ + +#define SSPCC_PSSET7_UART12_Pos (24) /*!< SSPCC_T::PSSET7: UART12 Position */ +#define SSPCC_PSSET7_UART12_Msk (0x3ul << SSPCC_PSSET7_UART12_Pos) /*!< SSPCC_T::PSSET7: UART12 Mask */ + +#define SSPCC_PSSET7_UART13_Pos (26) /*!< SSPCC_T::PSSET7: UART13 Position */ +#define SSPCC_PSSET7_UART13_Msk (0x3ul << SSPCC_PSSET7_UART13_Pos) /*!< SSPCC_T::PSSET7: UART13 Mask */ + +#define SSPCC_PSSET7_UART14_Pos (28) /*!< SSPCC_T::PSSET7: UART14 Position */ +#define SSPCC_PSSET7_UART14_Msk (0x3ul << SSPCC_PSSET7_UART14_Pos) /*!< SSPCC_T::PSSET7: UART14 Mask */ + +#define SSPCC_PSSET7_UART15_Pos (30) /*!< SSPCC_T::PSSET7: UART15 Position */ +#define SSPCC_PSSET7_UART15_Msk (0x3ul << SSPCC_PSSET7_UART15_Pos) /*!< SSPCC_T::PSSET7: UART15 Mask */ + +#define SSPCC_PSSET8_I2C0_Pos (0) /*!< SSPCC_T::PSSET8: I2C0 Position */ +#define SSPCC_PSSET8_I2C0_Msk (0x3ul << SSPCC_PSSET8_I2C0_Pos) /*!< SSPCC_T::PSSET8: I2C0 Mask */ + +#define SSPCC_PSSET8_I2C1_Pos (2) /*!< SSPCC_T::PSSET8: I2C1 Position */ +#define SSPCC_PSSET8_I2C1_Msk (0x3ul << SSPCC_PSSET8_I2C1_Pos) /*!< SSPCC_T::PSSET8: I2C1 Mask */ + +#define SSPCC_PSSET8_I2C2_Pos (4) /*!< SSPCC_T::PSSET8: I2C2 Position */ +#define SSPCC_PSSET8_I2C2_Msk (0x3ul << SSPCC_PSSET8_I2C2_Pos) /*!< SSPCC_T::PSSET8: I2C2 Mask */ + +#define SSPCC_PSSET8_I2C3_Pos (6) /*!< SSPCC_T::PSSET8: I2C3 Position */ +#define SSPCC_PSSET8_I2C3_Msk (0x3ul << SSPCC_PSSET8_I2C3_Pos) /*!< SSPCC_T::PSSET8: I2C3 Mask */ + +#define SSPCC_PSSET8_I2C4_Pos (8) /*!< SSPCC_T::PSSET8: I2C4 Position */ +#define SSPCC_PSSET8_I2C4_Msk (0x3ul << SSPCC_PSSET8_I2C4_Pos) /*!< SSPCC_T::PSSET8: I2C4 Mask */ + +#define SSPCC_PSSET8_I2C5_Pos (10) /*!< SSPCC_T::PSSET8: I2C5 Position */ +#define SSPCC_PSSET8_I2C5_Msk (0x3ul << SSPCC_PSSET8_I2C5_Pos) /*!< SSPCC_T::PSSET8: I2C5 Mask */ + +#define SSPCC_PSSET8_UART16_Pos (16) /*!< SSPCC_T::PSSET8: UART16 Position */ +#define SSPCC_PSSET8_UART16_Msk (0x3ul << SSPCC_PSSET8_UART16_Pos) /*!< SSPCC_T::PSSET8: UART16 Mask */ + +#define SSPCC_PSSET9_SC0_Pos (0) /*!< SSPCC_T::PSSET9: SC0 Position */ +#define SSPCC_PSSET9_SC0_Msk (0x3ul << SSPCC_PSSET9_SC0_Pos) /*!< SSPCC_T::PSSET9: SC0 Mask */ + +#define SSPCC_PSSET9_SC1_Pos (2) /*!< SSPCC_T::PSSET9: SC1 Position */ +#define SSPCC_PSSET9_SC1_Msk (0x3ul << SSPCC_PSSET9_SC1_Pos) /*!< SSPCC_T::PSSET9: SC1 Mask */ + +#define SSPCC_PSSET11_QEI0_Pos (0) /*!< SSPCC_T::PSSET11: QEI0 Position */ +#define SSPCC_PSSET11_QEI0_Msk (0x3ul << SSPCC_PSSET11_QEI0_Pos) /*!< SSPCC_T::PSSET11: QEI0 Mask */ + +#define SSPCC_PSSET11_QEI1_Pos (2) /*!< SSPCC_T::PSSET11: QEI1 Position */ +#define SSPCC_PSSET11_QEI1_Msk (0x3ul << SSPCC_PSSET11_QEI1_Pos) /*!< SSPCC_T::PSSET11: QEI1 Mask */ + +#define SSPCC_PSSET11_QEI2_Pos (4) /*!< SSPCC_T::PSSET11: QEI2 Position */ +#define SSPCC_PSSET11_QEI2_Msk (0x3ul << SSPCC_PSSET11_QEI2_Pos) /*!< SSPCC_T::PSSET11: QEI2 Mask */ + +#define SSPCC_PSSET11_ECAP0_Pos (8) /*!< SSPCC_T::PSSET11: ECAP0 Position */ +#define SSPCC_PSSET11_ECAP0_Msk (0x3ul << SSPCC_PSSET11_ECAP0_Pos) /*!< SSPCC_T::PSSET11: ECAP0 Mask */ + +#define SSPCC_PSSET11_ECAP1_Pos (10) /*!< SSPCC_T::PSSET11: ECAP1 Position */ +#define SSPCC_PSSET11_ECAP1_Msk (0x3ul << SSPCC_PSSET11_ECAP1_Pos) /*!< SSPCC_T::PSSET11: ECAP1 Mask */ + +#define SSPCC_PSSET11_ECAP2_Pos (12) /*!< SSPCC_T::PSSET11: ECAP2 Position */ +#define SSPCC_PSSET11_ECAP2_Msk (0x3ul << SSPCC_PSSET11_ECAP2_Pos) /*!< SSPCC_T::PSSET11: ECAP2 Mask */ + +#define SSPCC_PSSET11_TRNG_Pos (18) /*!< SSPCC_T::PSSET11: TRNG Position */ +#define SSPCC_PSSET11_TRNG_Msk (0x3ul << SSPCC_PSSET11_TRNG_Pos) /*!< SSPCC_T::PSSET11: TRNG Mask */ + +#define SSPCC_SRAMSB_SR0BOUND_Pos (0) /*!< SSPCC_T::SRAMSB: SR0BOUND Position */ +#define SSPCC_SRAMSB_SR0BOUND_Msk (0x1ful << SSPCC_SRAMSB_SR0BOUND_Pos) /*!< SSPCC_T::SRAMSB: SR0BOUND Mask */ + +#define SSPCC_SRAMSB_SR1BOUND_Pos (8) /*!< SSPCC_T::SRAMSB: SR1BOUND Position */ +#define SSPCC_SRAMSB_SR1BOUND_Msk (0x1ful << SSPCC_SRAMSB_SR1BOUND_Pos) /*!< SSPCC_T::SRAMSB: SR1BOUND Mask */ + +#define SSPCC_EBISSET_BANK0_Pos (0) /*!< SSPCC_T::EBISSET: BANK0 Position */ +#define SSPCC_EBISSET_BANK0_Msk (0x3ul << SSPCC_EBISSET_BANK0_Pos) /*!< SSPCC_T::EBISSET: BANK0 Mask */ + +#define SSPCC_EBISSET_BANK1_Pos (2) /*!< SSPCC_T::EBISSET: BANK1 Position */ +#define SSPCC_EBISSET_BANK1_Msk (0x3ul << SSPCC_EBISSET_BANK1_Pos) /*!< SSPCC_T::EBISSET: BANK1 Mask */ + +#define SSPCC_EBISSET_BANK2_Pos (4) /*!< SSPCC_T::EBISSET: BANK2 Position */ +#define SSPCC_EBISSET_BANK2_Msk (0x3ul << SSPCC_EBISSET_BANK2_Pos) /*!< SSPCC_T::EBISSET: BANK2 Mask */ + +#define SSPCC_IOxSSET_PIN0_Pos (0) /*!< SSPCC_T::IOxSSET: PIN0 Position */ +#define SSPCC_IOxSSET_PIN0_Msk (0x3ul << SSPCC_IOxSSET_PIN0_Pos) /*!< SSPCC_T::IOxSSET: PIN0 Mask */ + +#define SSPCC_IOxSSET_PIN1_Pos (2) /*!< SSPCC_T::IOxSSET: PIN1 Position */ +#define SSPCC_IOxSSET_PIN1_Msk (0x3ul << SSPCC_IOxSSET_PIN1_Pos) /*!< SSPCC_T::IOxSSET: PIN1 Mask */ + +#define SSPCC_IOxSSET_PIN2_Pos (4) /*!< SSPCC_T::IOxSSET: PIN2 Position */ +#define SSPCC_IOxSSET_PIN2_Msk (0x3ul << SSPCC_IOxSSET_PIN2_Pos) /*!< SSPCC_T::IOxSSET: PIN2 Mask */ + +#define SSPCC_IOxSSET_PIN3_Pos (6) /*!< SSPCC_T::IOxSSET: PIN3 Position */ +#define SSPCC_IOxSSET_PIN3_Msk (0x3ul << SSPCC_IOxSSET_PIN3_Pos) /*!< SSPCC_T::IOxSSET: PIN3 Mask */ + +#define SSPCC_IOxSSET_PIN4_Pos (8) /*!< SSPCC_T::IOxSSET: PIN4 Position */ +#define SSPCC_IOxSSET_PIN4_Msk (0x3ul << SSPCC_IOxSSET_PIN4_Pos) /*!< SSPCC_T::IOxSSET: PIN4 Mask */ + +#define SSPCC_IOxSSET_PIN5_Pos (10) /*!< SSPCC_T::IOxSSET: PIN5 Position */ +#define SSPCC_IOxSSET_PIN5_Msk (0x3ul << SSPCC_IOxSSET_PIN5_Pos) /*!< SSPCC_T::IOxSSET: PIN5 Mask */ + +#define SSPCC_IOxSSET_PIN6_Pos (12) /*!< SSPCC_T::IOxSSET: PIN6 Position */ +#define SSPCC_IOxSSET_PIN6_Msk (0x3ul << SSPCC_IOxSSET_PIN6_Pos) /*!< SSPCC_T::IOxSSET: PIN6 Mask */ + +#define SSPCC_IOxSSET_PIN7_Pos (14) /*!< SSPCC_T::IOxSSET: PIN7 Position */ +#define SSPCC_IOxSSET_PIN7_Msk (0x3ul << SSPCC_IOxSSET_PIN7_Pos) /*!< SSPCC_T::IOxSSET: PIN7 Mask */ + +#define SSPCC_IOxSSET_PIN8_Pos (16) /*!< SSPCC_T::IOxSSET: PIN8 Position */ +#define SSPCC_IOxSSET_PIN8_Msk (0x3ul << SSPCC_IOxSSET_PIN8_Pos) /*!< SSPCC_T::IOxSSET: PIN8 Mask */ + +#define SSPCC_IOxSSET_PIN9_Pos (18) /*!< SSPCC_T::IOxSSET: PIN9 Position */ +#define SSPCC_IOxSSET_PIN9_Msk (0x3ul << SSPCC_IOxSSET_PIN9_Pos) /*!< SSPCC_T::IOxSSET: PIN9 Mask */ + +#define SSPCC_IOxSSET_PIN10_Pos (20) /*!< SSPCC_T::IOxSSET: PIN10 Position */ +#define SSPCC_IOxSSET_PIN10_Msk (0x3ul << SSPCC_IOxSSET_PIN10_Pos) /*!< SSPCC_T::IOxSSET: PIN10 Mask */ + +#define SSPCC_IOxSSET_PIN11_Pos (22) /*!< SSPCC_T::IOxSSET: PIN11 Position */ +#define SSPCC_IOxSSET_PIN11_Msk (0x3ul << SSPCC_IOxSSET_PIN11_Pos) /*!< SSPCC_T::IOxSSET: PIN11 Mask */ + +#define SSPCC_IOxSSET_PIN12_Pos (24) /*!< SSPCC_T::IOxSSET: PIN12 Position */ +#define SSPCC_IOxSSET_PIN12_Msk (0x3ul << SSPCC_IOxSSET_PIN12_Pos) /*!< SSPCC_T::IOxSSET: PIN12 Mask */ + +#define SSPCC_IOxSSET_PIN13_Pos (26) /*!< SSPCC_T::IOxSSET: PIN13 Position */ +#define SSPCC_IOxSSET_PIN13_Msk (0x3ul << SSPCC_IOxSSET_PIN13_Pos) /*!< SSPCC_T::IOxSSET: PIN13 Mask */ + +#define SSPCC_IOxSSET_PIN14_Pos (28) /*!< SSPCC_T::IOxSSET: PIN14 Position */ +#define SSPCC_IOxSSET_PIN14_Msk (0x3ul << SSPCC_IOxSSET_PIN14_Pos) /*!< SSPCC_T::IOxSSET: PIN14 Mask */ + +#define SSPCC_IOxSSET_PIN15_Pos (30) /*!< SSPCC_T::IOxSSET: PIN15 Position */ +#define SSPCC_IOxSSET_PIN15_Msk (0x3ul << SSPCC_IOxSSET_PIN15_Pos) /*!< SSPCC_T::IOxSSET: PIN15 Mask */ + +#define SSPCC_SVIEN_APB0_Pos (0) /*!< SSPCC_T::SVIEN: APB0 Position */ +#define SSPCC_SVIEN_APB0_Msk (0x1ul << SSPCC_SVIEN_APB0_Pos) /*!< SSPCC_T::SVIEN: APB0 Mask */ + +#define SSPCC_SVIEN_APB3_Pos (1) /*!< SSPCC_T::SVIEN: APB3 Position */ +#define SSPCC_SVIEN_APB3_Msk (0x1ul << SSPCC_SVIEN_APB3_Pos) /*!< SSPCC_T::SVIEN: APB3 Mask */ + +#define SSPCC_SVIEN_SRAM1_Pos (2) /*!< SSPCC_T::SVIEN: SRAM1 Position */ +#define SSPCC_SVIEN_SRAM1_Msk (0x1ul << SSPCC_SVIEN_SRAM1_Pos) /*!< SSPCC_T::SVIEN: SRAM1 Mask */ + +#define SSPCC_SVIEN_SDH0_Pos (3) /*!< SSPCC_T::SVIEN: SDH0 Position */ +#define SSPCC_SVIEN_SDH0_Msk (0x1ul << SSPCC_SVIEN_SDH0_Pos) /*!< SSPCC_T::SVIEN: SDH0 Mask */ + +#define SSPCC_SVIEN_SDH1_Pos (4) /*!< SSPCC_T::SVIEN: SDH1 Position */ +#define SSPCC_SVIEN_SDH1_Msk (0x1ul << SSPCC_SVIEN_SDH1_Pos) /*!< SSPCC_T::SVIEN: SDH1 Mask */ + +#define SSPCC_SVIEN_HSUSBD_Pos (5) /*!< SSPCC_T::SVIEN: HSUSBD Position */ +#define SSPCC_SVIEN_HSUSBD_Msk (0x1ul << SSPCC_SVIEN_HSUSBD_Pos) /*!< SSPCC_T::SVIEN: HSUSBD Mask */ + +#define SSPCC_SVIEN_NANDC_Pos (6) /*!< SSPCC_T::SVIEN: NANDC Position */ +#define SSPCC_SVIEN_NANDC_Msk (0x1ul << SSPCC_SVIEN_NANDC_Pos) /*!< SSPCC_T::SVIEN: NANDC Mask */ + +#define SSPCC_SVIEN_PDMA0_Pos (7) /*!< SSPCC_T::SVIEN: PDMA0 Position */ +#define SSPCC_SVIEN_PDMA0_Msk (0x1ul << SSPCC_SVIEN_PDMA0_Pos) /*!< SSPCC_T::SVIEN: PDMA0 Mask */ + +#define SSPCC_SVIEN_PDMA1_Pos (8) /*!< SSPCC_T::SVIEN: PDMA1 Position */ +#define SSPCC_SVIEN_PDMA1_Msk (0x1ul << SSPCC_SVIEN_PDMA1_Pos) /*!< SSPCC_T::SVIEN: PDMA1 Mask */ + +#define SSPCC_SVIEN_TRNG_Pos (9) /*!< SSPCC_T::SVIEN: TRNG Position */ +#define SSPCC_SVIEN_TRNG_Msk (0x1ul << SSPCC_SVIEN_TRNG_Pos) /*!< SSPCC_T::SVIEN: TRNG Mask */ + +#define SSPCC_SVIEN_CRYPTO_Pos (10) /*!< SSPCC_T::SVIEN: CRYPTO Position */ +#define SSPCC_SVIEN_CRYPTO_Msk (0x1ul << SSPCC_SVIEN_CRYPTO_Pos) /*!< SSPCC_T::SVIEN: CRYPTO Mask */ + +#define SSPCC_SVINTSTS_APB0_Pos (0) /*!< SSPCC_T::SVINTSTS: APB0 Position */ +#define SSPCC_SVINTSTS_APB0_Msk (0x1ul << SSPCC_SVINTSTS_APB0_Pos) /*!< SSPCC_T::SVINTSTS: APB0 Mask */ + +#define SSPCC_SVINTSTS_APB3_Pos (1) /*!< SSPCC_T::SVINTSTS: APB3 Position */ +#define SSPCC_SVINTSTS_APB3_Msk (0x1ul << SSPCC_SVINTSTS_APB3_Pos) /*!< SSPCC_T::SVINTSTS: APB3 Mask */ + +#define SSPCC_SVINTSTS_SRAM1_Pos (2) /*!< SSPCC_T::SVINTSTS: SRAM1 Position */ +#define SSPCC_SVINTSTS_SRAM1_Msk (0x1ul << SSPCC_SVINTSTS_SRAM1_Pos) /*!< SSPCC_T::SVINTSTS: SRAM1 Mask */ + +#define SSPCC_SVINTSTS_SDH0_Pos (3) /*!< SSPCC_T::SVINTSTS: SDH0 Position */ +#define SSPCC_SVINTSTS_SDH0_Msk (0x1ul << SSPCC_SVINTSTS_SDH0_Pos) /*!< SSPCC_T::SVINTSTS: SDH0 Mask */ + +#define SSPCC_SVINTSTS_SDH1_Pos (4) /*!< SSPCC_T::SVINTSTS: SDH1 Position */ +#define SSPCC_SVINTSTS_SDH1_Msk (0x1ul << SSPCC_SVINTSTS_SDH1_Pos) /*!< SSPCC_T::SVINTSTS: SDH1 Mask */ + +#define SSPCC_SVINTSTS_HSUSBD_Pos (5) /*!< SSPCC_T::SVINTSTS: HSUSBD Position */ +#define SSPCC_SVINTSTS_HSUSBD_Msk (0x1ul << SSPCC_SVINTSTS_HSUSBD_Pos) /*!< SSPCC_T::SVINTSTS: HSUSBD Mask */ + +#define SSPCC_SVINTSTS_NANDC_Pos (6) /*!< SSPCC_T::SVINTSTS: NANDC Position */ +#define SSPCC_SVINTSTS_NANDC_Msk (0x1ul << SSPCC_SVINTSTS_NANDC_Pos) /*!< SSPCC_T::SVINTSTS: NANDC Mask */ + +#define SSPCC_SVINTSTS_PDMA0_Pos (7) /*!< SSPCC_T::SVINTSTS: PDMA0 Position */ +#define SSPCC_SVINTSTS_PDMA0_Msk (0x1ul << SSPCC_SVINTSTS_PDMA0_Pos) /*!< SSPCC_T::SVINTSTS: PDMA0 Mask */ + +#define SSPCC_SVINTSTS_PDMA1_Pos (8) /*!< SSPCC_T::SVINTSTS: PDMA1 Position */ +#define SSPCC_SVINTSTS_PDMA1_Msk (0x1ul << SSPCC_SVINTSTS_PDMA1_Pos) /*!< SSPCC_T::SVINTSTS: PDMA1 Mask */ + +#define SSPCC_SVINTSTS_TRNG_Pos (9) /*!< SSPCC_T::SVINTSTS: TRNG Position */ +#define SSPCC_SVINTSTS_TRNG_Msk (0x1ul << SSPCC_SVINTSTS_TRNG_Pos) /*!< SSPCC_T::SVINTSTS: TRNG Mask */ + +#define SSPCC_SVINTSTS_CRYPTO_Pos (10) /*!< SSPCC_T::SVINTSTS: CRYPTO Position */ +#define SSPCC_SVINTSTS_CRYPTO_Msk (0x1ul << SSPCC_SVINTSTS_CRYPTO_Pos) /*!< SSPCC_T::SVINTSTS: CRYPTO Mask */ + +#define SSPCC_APB0VSRC_MASTER_Pos (0) /*!< SSPCC_T::APB0VSRC: MASTER Position */ +#define SSPCC_APB0VSRC_MASTER_Msk (0xful << SSPCC_APB0VSRC_MASTER_Pos) /*!< SSPCC_T::APB0VSRC: MASTER Mask */ + +#define SSPCC_APB3VSRC_MASTER_Pos (0) /*!< SSPCC_T::APB3VSRC: MASTER Position */ +#define SSPCC_APB3VSRC_MASTER_Msk (0xful << SSPCC_APB3VSRC_MASTER_Pos) /*!< SSPCC_T::APB3VSRC: MASTER Mask */ + +#define SSPCC_SRAM1VSRC_MASTER_Pos (0) /*!< SSPCC_T::SRAM1VSRC: MASTER Position */ +#define SSPCC_SRAM1VSRC_MASTER_Msk (0xful << SSPCC_SRAM1VSRC_MASTER_Pos) /*!< SSPCC_T::SRAM1VSRC: MASTER Mask */ + +#define SSPCC_SDH0VSRC_MASTER_Pos (0) /*!< SSPCC_T::SDH0VSRC: MASTER Position */ +#define SSPCC_SDH0VSRC_MASTER_Msk (0xful << SSPCC_SDH0VSRC_MASTER_Pos) /*!< SSPCC_T::SDH0VSRC: MASTER Mask */ + +#define SSPCC_SDH1VSRC_MASTER_Pos (0) /*!< SSPCC_T::SDH1VSRC: MASTER Position */ +#define SSPCC_SDH1VSRC_MASTER_Msk (0xful << SSPCC_SDH1VSRC_MASTER_Pos) /*!< SSPCC_T::SDH1VSRC: MASTER Mask */ + +#define SSPCC_HSUSBDVSRC_MASTER_Pos (0) /*!< SSPCC_T::HSUSBDVSRC: MASTER Position */ +#define SSPCC_HSUSBDVSRC_MASTER_Msk (0xful << SSPCC_HSUSBDVSRC_MASTER_Pos) /*!< SSPCC_T::HSUSBDVSRC: MASTER Mask */ + +#define SSPCC_NANDCVSRC_MASTER_Pos (0) /*!< SSPCC_T::NANDCVSRC: MASTER Position */ +#define SSPCC_NANDCVSRC_MASTER_Msk (0xful << SSPCC_NANDCVSRC_MASTER_Pos) /*!< SSPCC_T::NANDCVSRC: MASTER Mask */ + +#define SSPCC_PDMA0VSRC_MASTER_Pos (0) /*!< SSPCC_T::PDMA0VSRC: MASTER Position */ +#define SSPCC_PDMA0VSRC_MASTER_Msk (0xful << SSPCC_PDMA0VSRC_MASTER_Pos) /*!< SSPCC_T::PDMA0VSRC: MASTER Mask */ + +#define SSPCC_PDMA1VSRC_MASTER_Pos (0) /*!< SSPCC_T::PDMA1VSRC: MASTER Position */ +#define SSPCC_PDMA1VSRC_MASTER_Msk (0xful << SSPCC_PDMA1VSRC_MASTER_Pos) /*!< SSPCC_T::PDMA1VSRC: MASTER Mask */ + +#define SSPCC_TRNGVSRC_MASTER_Pos (0) /*!< SSPCC_T::TRNGVSRC: MASTER Position */ +#define SSPCC_TRNGVSRC_MASTER_Msk (0xful << SSPCC_TRNGVSRC_MASTER_Pos) /*!< SSPCC_T::TRNGVSRC: MASTER Mask */ + +#define SSPCC_CRYPTOVSRC_MASTER_Pos (0) /*!< SSPCC_T::CRYPTOVSRC: MASTER Position */ +#define SSPCC_CRYPTOVSRC_MASTER_Msk (0xful << SSPCC_CRYPTOVSRC_MASTER_Pos) /*!< SSPCC_T::CRYPTOVSRC: MASTER Mask */ + +#define SSPCC_APB0VA_VIOADDR_Pos (0) /*!< SSPCC_T::APB0VA: VIOADDR Position */ +#define SSPCC_APB0VA_VIOADDR_Msk (0xfffffffful << SSPCC_APB0VA_VIOADDR_Pos) /*!< SSPCC_T::APB0VA: VIOADDR Mask */ + +#define SSPCC_APB3VA_VIOADDR_Pos (0) /*!< SSPCC_T::APB3VA: VIOADDR Position */ +#define SSPCC_APB3VA_VIOADDR_Msk (0xfffffffful << SSPCC_APB3VA_VIOADDR_Pos) /*!< SSPCC_T::APB3VA: VIOADDR Mask */ + +#define SSPCC_SRAM1VA_VIOADDR_Pos (0) /*!< SSPCC_T::SRAM1VA: VIOADDR Position */ +#define SSPCC_SRAM1VA_VIOADDR_Msk (0xfffffffful << SSPCC_SRAM1VA_VIOADDR_Pos) /*!< SSPCC_T::SRAM1VA: VIOADDR Mask */ + +#define SSPCC_SDH0VA_VIOADDR_Pos (0) /*!< SSPCC_T::SDH0VA: VIOADDR Position */ +#define SSPCC_SDH0VA_VIOADDR_Msk (0xfffffffful << SSPCC_SDH0VA_VIOADDR_Pos) /*!< SSPCC_T::SDH0VA: VIOADDR Mask */ + +#define SSPCC_SDH1VA_VIOADDR_Pos (0) /*!< SSPCC_T::SDH1VA: VIOADDR Position */ +#define SSPCC_SDH1VA_VIOADDR_Msk (0xfffffffful << SSPCC_SDH1VA_VIOADDR_Pos) /*!< SSPCC_T::SDH1VA: VIOADDR Mask */ + +#define SSPCC_HSUSBDVA_VIOADDR_Pos (0) /*!< SSPCC_T::HSUSBDVA: VIOADDR Position */ +#define SSPCC_HSUSBDVA_VIOADDR_Msk (0xfffffffful << SSPCC_HSUSBDVA_VIOADDR_Pos) /*!< SSPCC_T::HSUSBDVA: VIOADDR Mask */ + +#define SSPCC_NANDCVA_VIOADDR_Pos (0) /*!< SSPCC_T::NANDCVA: VIOADDR Position */ +#define SSPCC_NANDCVA_VIOADDR_Msk (0xfffffffful << SSPCC_NANDCVA_VIOADDR_Pos) /*!< SSPCC_T::NANDCVA: VIOADDR Mask */ + +#define SSPCC_PDMA0VA_VIOADDR_Pos (0) /*!< SSPCC_T::PDMA0VA: VIOADDR Position */ +#define SSPCC_PDMA0VA_VIOADDR_Msk (0xfffffffful << SSPCC_PDMA0VA_VIOADDR_Pos) /*!< SSPCC_T::PDMA0VA: VIOADDR Mask */ + +#define SSPCC_PDMA1VA_VIOADDR_Pos (0) /*!< SSPCC_T::PDMA1VA: VIOADDR Position */ +#define SSPCC_PDMA1VA_VIOADDR_Msk (0xfffffffful << SSPCC_PDMA1VA_VIOADDR_Pos) /*!< SSPCC_T::PDMA1VA: VIOADDR Mask */ + +#define SSPCC_TRNGVA_VIOADDR_Pos (0) /*!< SSPCC_T::TRNGVA: VIOADDR Position */ +#define SSPCC_TRNGVA_VIOADDR_Msk (0xfffffffful << SSPCC_TRNGVA_VIOADDR_Pos) /*!< SSPCC_T::TRNGVA: VIOADDR Mask */ + +#define SSPCC_CRYPTOVA_VIOADDR_Pos (0) /*!< SSPCC_T::CRYPTOVA: VIOADDR Position */ +#define SSPCC_CRYPTOVA_VIOADDR_Msk (0xfffffffful << SSPCC_CRYPTOVA_VIOADDR_Pos) /*!< SSPCC_T::CRYPTOVA: VIOADDR Mask */ + +#define SSPCC_SINFAEN_SSPCCSIAEN_Pos (0) /*!< SSPCC_T::SINFAEN: SSPCCSIAEN Position */ +#define SSPCC_SINFAEN_SSPCCSIAEN_Msk (0x1ul << SSPCC_SINFAEN_SSPCCSIAEN_Pos) /*!< SSPCC_T::SINFAEN: SSPCCSIAEN Mask */ + +#define SSPCC_SINFAEN_SYSSIAEN_Pos (1) /*!< SSPCC_T::SINFAEN: SYSSIAEN Position */ +#define SSPCC_SINFAEN_SYSSIAEN_Msk (0x1ul << SSPCC_SINFAEN_SYSSIAEN_Pos) /*!< SSPCC_T::SINFAEN: SYSSIAEN Mask */ + +#define SSPCC_SINFAEN_RTCSIAEN_Pos (2) /*!< SSPCC_T::SINFAEN: RTCSIAEN Position */ +#define SSPCC_SINFAEN_RTCSIAEN_Msk (0x1ul << SSPCC_SINFAEN_RTCSIAEN_Pos) /*!< SSPCC_T::SINFAEN: RTCSIAEN Mask */ + +#define SSPCC_SINFAEN_OTPSIAEN_Pos (6) /*!< SSPCC_T::SINFAEN: OTPSIAEN Position */ +#define SSPCC_SINFAEN_OTPSIAEN_Msk (0x1ul << SSPCC_SINFAEN_OTPSIAEN_Pos) /*!< SSPCC_T::SINFAEN: OTPSIAEN Mask */ + +#define SSPCC_SINFAEN_KSSIAEN_Pos (7) /*!< SSPCC_T::SINFAEN: KSSIAEN Position */ +#define SSPCC_SINFAEN_KSSIAEN_Msk (0x1ul << SSPCC_SINFAEN_KSSIAEN_Pos) /*!< SSPCC_T::SINFAEN: KSSIAEN Mask */ + +#define SSPCC_SCWP_ENABLE_Pos (0) /*!< SSPCC_T::SCWP: ENABLE Position */ +#define SSPCC_SCWP_ENABLE_Msk (0x1ul << SSPCC_SCWP_ENABLE_Pos) /*!< SSPCC_T::SCWP: ENABLE Mask */ + +#define SSPCC_SCWP_LOCK_Pos (1) /*!< SSPCC_T::SCWP: LOCK Position */ +#define SSPCC_SCWP_LOCK_Msk (0x1ul << SSPCC_SCWP_LOCK_Pos) /*!< SSPCC_T::SCWP: LOCK Mask */ + +#define SSPCC_SCWP_WVCODE_Pos (16) /*!< SSPCC_T::SCWP: WVCODE Position */ +#define SSPCC_SCWP_WVCODE_Msk (0xfffful << SSPCC_SCWP_WVCODE_Pos) /*!< SSPCC_T::SCWP: WVCODE Mask */ + +/**@}*/ /* SSPCC_CONST */ +/**@}*/ /* end of SSPCC register group */ +/**@}*/ /* end of REGISTER group */ + +#if defined ( __CC_ARM ) + #pragma no_anon_unions +#endif + +#endif /* __SSPCC_REG_H__ */ diff --git a/bsp/nuvoton/libraries/ma35/Device/Nuvoton/MA35D1/Include/sys_reg.h b/bsp/nuvoton/libraries/ma35/Device/Nuvoton/MA35D1/Include/sys_reg.h new file mode 100644 index 0000000000..0b5cedd15b --- /dev/null +++ b/bsp/nuvoton/libraries/ma35/Device/Nuvoton/MA35D1/Include/sys_reg.h @@ -0,0 +1,5816 @@ +/**************************************************************************//** + * @file sys_reg.h + * @brief SYS register definition header file + * + * SPDX-License-Identifier: Apache-2.0 + * @copyright (C) 2020 Nuvoton Technology Corp. All rights reserved. + *****************************************************************************/ +#ifndef __SYS_REG_H__ +#define __SYS_REG_H__ + +#if defined ( __CC_ARM ) + #pragma anon_unions +#endif + +/** + @addtogroup REGISTER Control Register + @{ +*/ + +/** + @addtogroup SYS System Manger Controller(SYS) + Memory Mapped Structure for SYS Controller +@{ */ + +typedef struct +{ + + + /** + * @var SYS_T::PDID + * Offset: 0x00 Product and Device Identifier Register (TZNS) + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[15:0] |PID |Product ID + * | | |This field stores the 16-bit Product ID loaded from OTP memory. + * |[27:16] |DID |Device ID + * | | |This field stores the 8-bit Device ID loaded from OTP memory. + * @var SYS_T::PWRONOTP + * Offset: 0x04 Power-on Setting OTP Source Register (TZNS) + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[0] |PWRONSRC |Power on Setting Source Control (Read Only) + * | | |0 = Power on setting values come from pin. (Default) + * | | |1 = Power on setting values come from OTP. + * |[1] |QSPI0CKSEL|QSPI0_CLK Frequency Selection (Read Only) + * | | |0 = QSPI0_CLK frequency is 30 MHz. + * | | |1 = QSPI0_CLK frequency is 50 MHz. + * | | |Note: The value of WDT0ON latched from OTP when pin nRESET transited from low to high. + * |[2] |WDT0ON |Watchdog Timer 0 ON/OFF Selection (Read Only) + * | | |0 = After power-on, WDT 0 Disabled. + * | | |1 = after power-on WDT 0 Enabled. + * | | |Note: The value of WDT0ON latched from OTP when pin nRESET transited from low to high. + * |[4] |UR0DBGDIS |UART 0 Debug Message Output Disable Bit (Read Only) + * | | |0= UART 0 debug message output Enabled. + * | | |1= UART 0 debug message output Disabled. + * | | |Note: The value of UR0DBGDIS latched from OTP when pin nRESET transited from low to high. + * |[5] |SD0BKEN |SD0 Back Up Boot Enable Bit (Read Only) + * | | |0 = SD0 back up boot Disabled (Default). + * | | |1 = SD0 back up boot Enabled. + * | | |Note: SD0BKEN didn't take effect if BTSRCSEL= 01 and BTOPTION = 00.. + * |[11:10] |BTSRCSEL |Boot Source Selection (Read Only) + * | | |00 = Boot from SPI Flash (Default). + * | | |01 = Boot from SD/eMMC. + * | | |10 = Boot from NAND Flash. + * | | |11 = Boot from USB. + * | | |Note: If PWRONSRC = 0, the value of pin PG[3:2] latched to BTSRCSEL when pin nRESET transited from low to high + * | | |If PWRONSRC = 1, the value of BTSRCSEL latched from OTP's BTSRCSEL. + * |[13:12] |NPAGESEL |NAND Flash Page Size Selection (Read Only) + * | | |00 = NAND Flash page size is 2 KB. + * | | |01 = NAND Flash page size is 4 KB. + * | | |10 = NAND Flash page size is 8 KB. + * | | |11 = Ignore. + * | | |Note: If PWRONSRC = 0, the value of pin PG[5:4] latched to NPAGSEL when pin nRESET transited from low to high + * | | |If PWRONSRC = 1, the value of NPAGSEL latched from OTP's BTNANDPS. + * |[15:14] |MISCCFG |Miscellaneous Configuration (Read Only) + * | | |If BTSRCSEL = 01, boot from SD/eMMC. + * | | |MISCCFG[0]: + * | | |0 = SD0/eMMC0 booting. (Default) + * | | |1 = SD1/eMMC1 booting. + * | | |MISCCFG[1]: + * | | |0 = eMMC 4-bit booting. (Default) + * | | |1 = eMMC 8-bit booting.00 = SD0/eMMC0 booting (Default). + * | | |01 = SD1/eMMC1 booting. + * | | |10 = SD1/eMMC1 booting. + * | | |11 = SD1/eMMC1 booting. + * | | |If BTSRCSEL = 10, boot from NAND Flash. + * | | |00 = No ECC (Default). + * | | |01 = ECC is BCH T12. + * | | |10 = ECC is BCH T24. + * | | |11 = Ignore. + * | | |If BTSRCSEL = 00, the Boot from SPI Flash. + * | | |00 = SPI-NAND Flash with 1-bit mode booting (Default). + * | | |01 = SPI-NAND Flash with 4-bit mode booting. + * | | |10 = SPI-NOR Flash with 1-bit mode booting. + * | | |11 = SPI-NOR Flash with 4-bit mode booting. + * | | |Note: If PWRONSRC = 0, the value of pin PG[7:6] latched to MISCCFG when pin nRESET transited from low to high + * | | |If PWRONSRC = 1, the value of MISCCFG latched from OTP's BTOPTION. + * |[16] |USBP0ID |USB Port 0 ID Pin Status + * | | |0= USB port 0 used as a USB device. + * | | |1= USB port 0 used as a USB host. + * |[31:24] |SECBTPSWD |Secure Boot Disable Password (Read Only) + * | | |If SECBTPSWD is 0x5A, the secure boot Disabled. + * | | |Note 1: SECBTPSWD didn't take effect and PG[0] used as Secure Boot Disable if PWRONSRC = 0. + * | | |Note 2: In RMA mode, SECBTPSWD didn't take effect and PG[0] used as Secure Boot Disable. + * @var SYS_T::PWRONPIN + * Offset: 0x08 Power-on Setting Pin Source Register (TZNS) + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[0] |SECBTDIS |Secure Boot Disable Bit (Read Only) + * | | |0 = Secure Boot Enabled (Default). + * | | |1 = Secure Boot Disabled. + * | | |Note: If PWRONSRC = 0, the value of pin PG[0] latched to SECBTDIS when pin nRESET transited from low to high + * | | |If PWRONSRC = 1, the value of SECBTDIS latched from OTP's SECBTDIS. + * |[3:2] |BTSRCSEL |Boot Source Selection (Read Only) + * | | |00 = Boot from SPI Flash (Default). + * | | |01 = Boot from SD/eMMC. + * | | |10 = Boot from NAND Flash. + * | | |11 = Boot from USB. + * | | |Note: If PWRONSRC = 0, the value of pin PG[3:2] latched to BTSRCSEL when pin nRESET transited from low to high + * | | |If PWRONSRC = 1, the value of BTSRCSEL latched from OTP's BTSRCSEL. + * |[5:4] |NPAGESEL |NAND Flash Page Size Selection (Read Only) + * | | |00 = NAND Flash page size is 2 KB. + * | | |01 = NAND Flash page size is 4 KB. + * | | |10 = NAND Flash page size is 8 KB. + * | | |11 = Ignore. + * | | |Note: If PWRONSRC = 0, the value of pin PG[5:4] latched to NPAGSEL when pin nRESET transited from low to high + * | | |If PWRONSRC = 1, the value of NPAGSEL latched from OTP's BTNANDPS. + * |[7:6] |MISCCFG |Miscellaneous Configuration (Read Only) + * | | |If BTSRCSEL = 01, boot from SD/eMMC. + * | | |MISCCFG[0]: + * | | |0 = SD0/eMMC0 booting. (Default) + * | | |1 = SD1/eMMC1 booting. + * | | |MISCCFG[1]: + * | | |0 = eMMC 4-bit booting. (Default) + * | | |1 = eMMC 8-bit booting.00 = SD0/eMMC0 booting (Default). + * | | |01 = SD1/eMMC1 booting. + * | | |10 = SD1/eMMC1 booting. + * | | |11 = SD1/eMMC1 booting. + * | | |If BTSRCSEL = 10, boot from NAND Flash. + * | | |00 = No ECC (Default). + * | | |01 = ECC is BCH T12. + * | | |10 = ECC is BCH T24. + * | | |11 = Ignore. + * | | |If BTSRCSEL = 00, the Boot from SPI Flash. + * | | |00 = SPI-NAND Flash with 1-bit mode booting (Default). + * | | |01 = SPI-NAND Flash with 4-bit mode booting. + * | | |10 = SPI-NOR Flash with 1-bit mode booting. + * | | |11 = SPI-NOR Flash with 4-bit mode booting. + * | | |Note: If PWRONSRC = 0, the value of pin PG[7:6] latched to MISCCFG when pin nRESET transited from low to high + * | | |If PWRONSRC = 1, the value of MISCCFG latched from OTP's BTOPTION. + * @var SYS_T::RSTSTS + * Offset: 0x10 Reset Source Active Status Register (Shared) + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[0] |PORF |POR Reset Flag + * | | |0 = No reset from POR. + * | | |1 = POR had issued reset signal to reset the chip. + * | | |Note: Write 1 to clear this bit to 0. + * |[1] |PINRF |NRESET Pin Reset Flag + * | | |0 = No reset from nRESET pin. + * | | |1 = nRESET pin had issued reset signal to reset the chip. + * | | |Note: Write 1 to clear this bit to 0. + * |[2] |WDT0RF |WDT 0 Reset Flag + * | | |The WDT 0 reset flag is set by the "Reset Signal" from the Watchdog Timer 0 or Window Watchdog Timer 0 to indicate the previous reset source. + * | | |0 = No reset from watchdog timer 0 or window watchdog timer 0. + * | | |1 = The watchdog timer 0 or window watchdog timer 0 had issued the reset signal to reset the system. + * | | |Note 1: Write 1 to clear this bit to 0. + * | | |Note 2: Watchdog Timer 0 register RSTF(WDT0_CTL[2]) bit is set if the system has been reset by WDT 0 time-out reset + * | | |Window Watchdog Timer 0 register WWDTRF(WWDT0_STATUS[1]) bit is set if the system has been reset by WWDT 0 time-out reset. + * |[3] |LVRF |LVR Reset Flag + * | | |The LVR reset flag is set by the "Reset Signal" from the Low Voltage Reset Controller to indicate the previous reset source. + * | | |0 = No reset from LVR. + * | | |1 = LVR had issued reset signal to reset the chip. + * | | |Note: Write 1 to clear this bit to 0. + * |[4] |CPU0DBGRF |Cortex-A35 Core 0 Debug Reset Flag + * | | |The Cortex-A35 core 0 debug reset flag is set by the "Reset Signal" from DBGRSTREQ of Cortex-A35 core 0 to indicate the previous reset source. + * | | |0 = No reset from DBGRSTREQ of Cortex-A35 core 0. + * | | |1 = The Cortex-A35 core 0 had issued DBGRSTREQ reset signal to reset itself. + * | | |Note: Write 1 to clear this bit to 0. + * |[5] |CPU0WARMRF|Cortex-A35 Core 0 Warm Reset Flag + * | | |The Cortex-A35 core 0 warm reset flag is set by the "Reset Signal" from WARMRSTREQ of Cortex-A35 core 0 to indicate the previous reset source + * | | |The WARMRSTREQ of Cortex-A35 core 0 trigger by writing 1 to the bit RR (RMR[1], Reset Management Register of Cortex-A35 core 0) + * | | |0 = No reset from WARMRSTREQ of Cortex-A35 core 0. + * | | |1 = The Cortex-A35 core 0 had issued WARMRSTREQ reset signal to reset itself. + * | | |Note: Write 1 to clear this bit to 0. + * |[6] |HRESETRF |HRESET Reset Flag + * | | |The HRESET reset flag is set by the "Reset Signal" from the HRESET. + * | | |0 = No reset from HRESET. + * | | |1 = Reset from HRESET. + * | | |Note: Write 1 to clear this bit to 0. + * |[7] |CPU0RF |CPU 0 Reset Flag + * | | |The CPU 0 reset flag is set by hardware if software writes CA35CR0RST (SYS_IPRST0[1]) 1 to reset Cortex-A35 Core 0. + * | | |0 = No reset to CPU. + * | | |1 = The Cortex-A35 Core 0 is reset by software setting CA35CR0RST (SYS_IPRST0[1]) to 1. + * | | |Note: Write 1 to clear this bit to 0. + * |[10] |WDT1RF |WDT 1 Reset Flag + * | | |The WDT 1 reset flag is set by the "Reset Signal" from the Watchdog Timer 1 or Window Watchdog Timer 1 to indicate the previous reset source. + * | | |0 = No reset from watchdog timer 1 or window watchdog timer 1. + * | | |1 = The watchdog timer 1 or window watchdog timer 1 had issued the reset signal to reset the system. + * | | |Note 1: Write 1 to clear this bit to 0. + * | | |Note 2: Watchdog Timer 1 register RSTF (WDT1_CTL[2]) bit is set if the system has been reset by WDT 1 time-out reset + * | | |Window Watchdog Timer 1 register WWDTRF (WWDT1_STATUS[1]) bit is set if the system has been reset by WWDT 1 time-out reset. + * | | |Note 3: This flag only take effect when WDT1RSTAEN (SYS_MISCRFCR[16]) is 1. + * |[11] |WDT2RFA |WDT 2 Reset Flag for Cortex-A35 + * | | |The WDT 2 reset flag is set by the "Reset Signal" from the Watchdog Timer 2 or Window Watchdog Timer 2 to indicate the previous reset source. + * | | |0 = No reset from watchdog timer 2 or window watchdog timer 2. + * | | |1 = The watchdog timer 2 or window watchdog timer 2 had issued the reset signal to reset the system. + * | | |Note 1: Write 1 to clear this bit to 0. + * | | |Note 2: Watchdog Timer 2 register RSTF(WDT2_CTL[2]) bit is set if the system has been reset by WDT 2 time-out reset + * | | |Window Watchdog Timer 2 register WWDTRF(WWDT2_STATUS[1]) bit is set if the system has been reset by WWDT 2 time-out reset. + * | | |Note 3: This flag only take effect when WDT2RSTAEN (SYS_MISCRFCR[17]) is 1. + * |[12] |CPU1DBGRF |Cortex-A35 Core 1 Debug Reset Flag + * | | |The Cortex-A35 core 1 debug reset flag is set by the "Reset Signal" from DBGRSTREQ of Cortex-A35 core 1 to indicate the previous reset source. + * | | |0 = No reset from DBGRSTREQ of Cortex-A35 core 1. + * | | |1 = The Cortex-A35 core 1 had issued DBGRSTREQ reset signal to reset itself. + * | | |Note: Write 1 to clear this bit to 0. + * |[13] |CPU1WARMRF|Cortex-A35 Core 1 Warm Reset Flag + * | | |The Cortex-A35 core 1 warm reset flag is set by the "Reset Signal" from WARMRSTREQ of Cortex-A35 core 1 to indicate the previous reset source + * | | |The WARMRSTREQ of Cortex-A35 core 1 trigger by writing 1 to the bit RR (RMR[1], Reset Management Register of Cortex-A35 core 1) + * | | |0 = No reset from WARMRSTREQ of Cortex-A35 core 1. + * | | |1 = The Cortex-A35 core 1 had issued WARMRSTREQ reset signal to reset itself. + * | | |Note: Write 1 to clear this bit to 0. + * |[15] |CPU1RF |Cortex-A35 Core 1 Reset Flag + * | | |The Cortex-A35 Core 1 reset flag is set by hardware if software writes CA35CR1RST (SYS_IPRST0[2]) 1 to reset Cortex-A35 Core 1. + * | | |0 = No reset to Cortex-A35 Core 1. + * | | |1 = The Cortex-A35 Core 1 is reset by software setting CA35CR1RST (SYS_IPRST0[2]) to 1. + * | | |Note: Write 1 to clear this bit to 0. + * |[18] |WDT1RFM |WDT 1 Reset Flag for RTP Cortex-M4 + * | | |The WDT 1 reset flag is set by the "Reset Signal" from the Watchdog Timer 1 or Window Watchdog Timer 1 to indicate the previous reset source. + * | | |0 = No reset from watchdog timer 1 or window watchdog timer 1. + * | | |1 = The watchdog timer 1 or window watchdog timer 1 had issued the reset signal to reset the system. + * | | |Note 1: Write 1 to clear this bit to 0. + * | | |Note 2: Watchdog Timer 1 register RSTF(WDT1_CTL[2]) bit is set if the system has been reset by WDT 1 time-out reset + * | | |Window Watchdog Timer 1 register WWDTRF(WWDT1_STATUS[1]) bit is set if the system has been reset by WWDT 1 time-out reset. + * | | |Note 3: This flag only take effect when WDT1RSTMEN (SYS_MISCRFCR[18]) is 1. + * |[19] |WDT2RF |WDT 2 Reset Flag for RTP Cortex-M4 + * | | |The WDT 2 reset flag is set by the "Reset Signal" from the Watchdog Timer 2 or Window Watchdog Timer 2 to indicate the previous reset source. + * | | |0 = No reset from watchdog timer 2 or window watchdog timer 2. + * | | |1 = The watchdog timer 2 or window watchdog timer 2 had issued the reset signal to reset the system. + * | | |Note 1: Write 1 to clear this bit to 0. + * | | |Note 2: Watchdog Timer 2 register RSTF(WDT2_CTL[2]) bit is set if the system has been reset by WDT 2 time-out reset + * | | |Window Watchdog Timer 2 register WWDTRF(WWDT2_STATUS[1]) bit is set if the system has been reset by WWDT 2 time-out reset. + * |[20] |RTPM4LKRF |RTP M4 CPU Lockup Reset Flag + * | | |0 = No reset from RTP M4 CPU lockup happened. + * | | |1 = The RTP Cortex-M4 lockup happened and chip is reset. + * | | |Note 1: Write 1 to clear this bit to 0. + * | | |Note 2: When CPU lockup happened under ICE is connected, this flag will set to 1 but chip will not reset. + * |[21] |RTPM4SYSRF|RTP M4 System Reset Flag + * | | |The system reset flag is set by the "Reset Signal" from the Cortex-M4 Core to indicate the previous reset source. + * | | |0 = No reset from Cortex-M4. + * | | |1 = The Cortex-M4 had issued the reset signal to reset the system by writing 1 to the bit SYSRESETREQ(AIRCR[2], Application Interrupt and Reset Control Register, address = 0xE000ED0C) in system control registers of Cortex-M4 core. + * | | |Note: Write 1 to clear this bit to 0. + * |[22] |RTPPMUSYSRF|RTP PMU System Reset Flag + * | | |The system reset flag is set by the "Reset Signal" from the PMU of Cortex-M4 Core to indicate the previous reset source. + * | | |0 = No reset from PMU of Cortex-M4. + * | | |1 = The PMU of Cortex-M4 had issued the reset signal (PMURESETREQ) to reset the system. + * | | |Note: Write 1 to clear this bit to 0. + * |[23] |RTPM4CPURF|RTP M4 CPU Reset Flag + * | | |The RTP M4 CPU reset flag is set by hardware if software writes CM4RST (SYS_IPRST0[3]) 1 to reset Cortex-M4 Core. + * | | |0 = No reset to RTP M4 CPU. + * | | |1 = The RTP M4 CPU core is reset by software setting CM4RST (SYS_IPRST0[3]) to 1. + * | | |Note: Write 1 to clear this bit to 0. + * @var SYS_T::MISCRFCR + * Offset: 0x14 Miscellaneous Reset Function Control Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[15:0] |PORDISCODE|Power-on-reset Disable Code (Write Protect) + * | | |When powered on, the Power-On-Reset (POR) circuit generates a reset signal to reset whole chip function + * | | |However, after power is ready, the POR circuit would consume a few power + * | | |To minimize the POR circuit power consumption, user to disable POR circuit by writing 0x5AA5 to this field. + * | | |The POR circuit will become active again when this field is set to other value or chip is reset by other reset source, including /RESET pin, Watchdog, LVR reset and the software chip reset function. + * | | |Note: This bit is write protected. Refer to the SYS_RLKTZS register. + * |[16] |WDT1RSTAEN|WDT 1 Reset Cortex-A35 Enable Bit (Write Protect) + * | | |0 = WDT 1 reset Cortex-A35 Disabled. (Default) + * | | |1 = WDT 1 reset Cortex-A35 Enabled. + * | | |Note: This bit is write protected. Refer to the SYS_RLKTZS register. + * |[17] |WDT2RSTAEN|WDT 2 Reset Cortex-A35 Enable Bit (Write Protect) + * | | |0 = WDT 2 reset Cortex-A35 Disabled. (Default) + * | | |1 = WDT 2 reset Cortex-A35 Enabled. + * | | |Note: This bit is write protected. Refer to the SYS_RLKTZS register. + * |[18] |WDT1RSTMEN|WDT 1 Reset Real Time Cortex-M4 Sub-system Enable Bit (Write Protect) + * | | |0 = WDT 1 reset real time Cortex-M4 sub-system Disabled. (Default) + * | | |1 = WDT 1 reset real time Cortex-M4 sub-system Enabled. + * | | |Note: This bit is write protected. Refer to the SYS_RLKTZS register. + * @var SYS_T::RSTDEBCTL + * Offset: 0x18 Reset Pin De-bounce Control Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[15:0] |DEBCNT |Power-on-reset Disable Code (Write Protect) + * | | |This 16-bit external RESET De-bounce Counter can specify the external RESET de-bounce time up to around 5.46ms (0xFFFF) @ XIN=12 MHz. + * | | |The default external RESET de-bounce time is 0.1ms (0x04B0) @ XIN = 12 MHz. + * | | |Note: This bit is write protected. Refer to the SYS_RLKTZS register. + * |[31] |RSTDEBEN |Reset Pin De-bounce Enable Bit (Write Protect) + * | | |0 = Reset pin de-bounce Disabled. + * | | |1 = Reset pin de-bounce Enabled. (Default) + * | | |Note: This bit is write protected. Refer to the SYS_RLKTZS register. + * @var SYS_T::LVRDCR + * Offset: 0x1C Low Voltage Reset & Detect Control Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[0] |LVREN |Low Voltage Reset Enable Bit (Write Protect) + * | | |0 = Low voltage reset function Disabled. + * | | |1 = Low voltage reset function Enabled. + * | | |Note: This bit is write protected. Refer to the SYS_RLKTZS register. + * |[3:1] |LVRDGSEL |LVR Output De-glitch Time Select (Write Protect) + * | | |000 = Without de-glitch function. + * | | |001 = 4 system clock (LVRDGCLK). + * | | |010 = 8 system clock (LVRDGCLK). + * | | |011 = 16 system clock (LVRDGCLK). + * | | |100 = 32 system clock (LVRDGCLK). + * | | |101 = 64 system clock (LVRDGCLK). + * | | |110 = 128 system clock (LVRDGCLK). + * | | |111 = 256 system clock (LVRDGCLK). + * | | |Note 1: These bits are write protected. Refer to the SYS_RLKTZS register. + * | | |Note 2: Refer to LVRDBSEL (CLK_CLKSEL0[3]) for LVRDGCLK clock source selection. + * |[8] |LVDEN |Low Voltage Detect Enable Bit (Write Protect) + * | | |0 = Low voltage detect function Disabled. + * | | |1 = Low voltage detect function Enabled. + * | | |Note: This bit is write protected. Refer to the SYS_RLKTZS register. + * |[9] |LVDSEL |Low Voltage Detect Threshold Selection (Write Protect) + * | | |0 = Low voltage detection level is 2.8V. + * | | |1 = Low voltage detection level is 2.6V. + * | | |Note: This bit is write protected. Refer to the SYS_RLKTZS register. + * |[10] |LVDWKA35EN|Low Voltage Detect Wake-up Cortex-A35 Enable Control Bit (Write Protect) + * | | |0 = Low voltage detection wakeup A35 Disabled. + * | | |1 = Low voltage detection wakeup A35 Enabled. + * | | |Note: This bit is write protected. Refer to the SYS_RLKTZS register. + * |[11] |LVDWKRTPEN|Low Voltage Detect Wake-up RTP Cortex-M4 Enable Control Bit (Write Protect) + * | | |0 = Low voltage detection wakeup RTP Cortex-M4 Disabled. + * | | |1 = Low voltage detection wakeup RTP Cortex-M4 Enabled. + * | | |Note: This bit is write protected. Refer to the SYS_RLKTZS register. + * |[14:12] |LVDODGSEL |LVD Output De-glitch Time Select (Write Protect) + * | | |000 = Without de-glitch function. + * | | |001 = 4 system clock (LVRDGCLK). + * | | |010 = 8 system clock (LVRDGCLK). + * | | |011 = 16 system clock (LVRDGCLK). + * | | |100 = 32 system clock (LVRDGCLK). + * | | |101 = 64 system clock (LVRDGCLK). + * | | |110 = 128 system clock (LVRDGCLK). + * | | |111 = 256 system clock (LVRDGCLK). + * | | |Note 1: These bits are write protected. Refer to the SYS_RLKTZS register. + * | | |Note 2: Refer to LVRDBSEL (CLK_CLKSEL0[3]) for LVRDGCLK clock source selection. + * @var SYS_T::IPRST0 + * Offset: 0x20 Reset Control Register 0 (Shared) + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[0] |CHIPRST |Chip One-shot Reset Enable Bit (Write Protect) + * | | |0 = Chip one-shot reset Disabled. + * | | |1 = Chip one-shot reset Enabled. + * | | |Note: This bit is write protected + * | | |Refer to the SYS_RLKTZS, SYS_RLKTZNS or SYS_RLKSUBM register according to security attribute of each circuit. + * |[1] |CA35CR0RST|Cortex-A35 Core 0 One-shot Reset (Write Protect) + * | | |0 = Cortex-A35 core 0 one-shot reset Disabled. + * | | |1 = Cortex-A35 core 0 one-shot reset Enabled. + * | | |Note: This bit is write protected + * | | |Refer to the SYS_RLKTZS, SYS_RLKTZNS or SYS_RLKSUBM register according to security attribute of each circuit. + * |[2] |CA35CR1RST|Cortex-A35 Core 1 One-shot Reset (Write Protect) + * | | |0 = Cortex-A35 core 1 one-shot reset Disabled. + * | | |1 = Cortex-A35 core 1 one-shot reset Enabled. + * | | |Note: This bit is write protected + * | | |Refer to the SYS_RLKTZS, SYS_RLKTZNS or SYS_RLKSUBM register according to security attribute of each circuit. + * |[3] |CM4RST |Cortex-M4 Core Reset (Write Protect) + * | | |0 = Cortex-M4 core reset Disabled. + * | | |1 = Cortex-M4 core reset Enabled. + * | | |Note: This bit is write protected + * | | |Refer to the SYS_RLKTZS, SYS_RLKTZNS or SYS_RLKSUBM register according to security attribute of each circuit. + * |[4] |PDMA0RST |PDMA 0 Reset Enable Bit (Write Protect) + * | | |0 = PDMA 0 reset Disabled. + * | | |1 = PDMA 0 reset Enabled. + * | | |Note: This bit is write protected + * | | |Refer to the SYS_RLKTZS, SYS_RLKTZNS or SYS_RLKSUBM register according to security attribute of each circuit. + * |[5] |PDMA1RST |PDMA 1 Reset Enable Bit (Write Protect) + * | | |0 = PDMA 1 reset Disabled. + * | | |1 = PDMA 1 reset Enabled. + * | | |Note: This bit is write protected + * | | |Refer to the SYS_RLKTZS, SYS_RLKTZNS or SYS_RLKSUBM register according to security attribute of each circuit. + * |[6] |PDMA2RST |PDMA2 Reset Enable Bit (Write Protect) + * | | |0 = PDMA 2 reset Disabled. + * | | |1 = PDMA 2 reset Enabled. + * | | |Note: This bit is write protected + * | | |Refer to the SYS_RLKTZS, SYS_RLKTZNS or SYS_RLKSUBM register according to security attribute of each circuit. + * |[7] |PDMA3RST |PDMA 3 Reset Enable Bit (Write Protect) + * | | |0 = PDMA 3 reset Disabled. + * | | |1 = PDMA 3 reset Enabled. + * | | |Note: This bit is write protected + * | | |Refer to the SYS_RLKTZS, SYS_RLKTZNS or SYS_RLKSUBM register according to security attribute of each circuit. + * |[9] |DISPCRST |LCD Display Controller Reset Enable Bit (Write Protect) + * | | |0 = LCD Display Controller reset Disabled. + * | | |1 = LCD Display Controller reset Enabled. + * | | |Note: This bit is write protected + * | | |Refer to the SYS_RLKTZS, SYS_RLKTZNS or SYS_RLKSUBM register according to security attribute of each circuit. + * |[10] |VCAP0RST |Video Capture Sensor Interface 0 Reset Enable Bit (Write Protect) + * | | |0 = Video Capture sensor interface 0 reset Disabled. + * | | |1 = Video Capture sensor interface 0 reset Enabled. + * | | |Note: This bit is write protected + * | | |Refer to the SYS_RLKTZS, SYS_RLKTZNS or SYS_RLKSUBM register according to security attribute of each circuit. + * |[11] |VCAP1RST |Video Capture Sensor Interface 1 Reset Enable Bit (Write Protect) + * | | |0 = Video Capture sensor interface 1 reset Disabled. + * | | |1 = Video Capture sensor interface 1 reset Enabled. + * | | |Note: This bit is write protected + * | | |Refer to the SYS_RLKTZS, SYS_RLKTZNS or SYS_RLKSUBM register according to security attribute of each circuit. + * |[12] |GFXRST |Graphic Engine Reset Enable Bit (Write Protect) + * | | |0 = Graphic Engine reset Disabled. + * | | |1 = Graphic Engine reset Enabled. + * | | |Note: This bit is write protected + * | | |Refer to the SYS_RLKTZS, SYS_RLKTZNS or SYS_RLKSUBM register according to security attribute of each circuit. + * |[13] |VDECRST |Video Decoder Reset Enable Bit (Write Protect) + * | | |0 = Video Decoder (H.264/JPEG) reset Disabled. + * | | |1 = Video Decoder (H.264/JPEG) reset Enabled. + * | | |Note: This bit is write protected + * | | |Refer to the SYS_RLKTZS, SYS_RLKTZNS or SYS_RLKSUBM register according to security attribute of each circuit. + * |[14] |WRHO0RST |Wormhole 0 Reset Enable Bit (Write Protect) + * | | |0 = Wormhole 0 reset Disabled. + * | | |1 = Wormhole 0 reset Enabled. + * | | |Note: This bit is write protected + * | | |Refer to the SYS_RLKTZS, SYS_RLKTZNS or SYS_RLKSUBM register according to security attribute of each circuit. + * |[15] |WRHO1RST |Wormhole 1 Reset Enable Bit (Write Protect) + * | | |0 = Wormhole 1 reset Disabled. + * | | |1 = Wormhole 1 reset Enabled. + * | | |Note: This bit is write protected + * | | |Refer to the SYS_RLKTZS, SYS_RLKTZNS or SYS_RLKSUBM register according to security attribute of each circuit. + * |[16] |GMAC0RST |Gigabit Ethernet MAC 0 Reset Enable Bit (Write Protect) + * | | |0 = Gigabit Ethernet MAC 0 reset Disabled. + * | | |1 = Gigabit Ethernet MAC 0 reset Enabled. + * | | |Note: This bit is write protected + * | | |Refer to the SYS_RLKTZS, SYS_RLKTZNS or SYS_RLKSUBM register according to security attribute of each circuit. + * |[17] |GMAC1RST |Gigabit Ethernet MAC 1 Reset Enable Bit (Write Protect) + * | | |0 = Gigabit Ethernet MAC 1 reset Disabled. + * | | |1 = Gigabit Ethernet MAC 1 reset Enabled. + * | | |Note: This bit is write protected + * | | |Refer to the SYS_RLKTZS, SYS_RLKTZNS or SYS_RLKSUBM register according to security attribute of each circuit. + * |[18] |HWSEMRST |Hardware Semaphore Reset Enable Bit (Write Protect) + * | | |0 = Hardware Semaphore reset Disabled. + * | | |1 = Hardware Semaphore reset Enabled. + * | | |Note: This bit is write protected + * | | |Refer to the SYS_RLKTZS, SYS_RLKTZNS or SYS_RLKSUBM register according to security attribute of each circuit. + * |[19] |EBIRST |EBI Controller Reset (Write Protect) + * | | |0 = EBI controller reset Disabled. + * | | |1 = EBI controller reset Enabled. + * | | |Note: This bit is write protected + * | | |Refer to the SYS_RLKTZS, SYS_RLKTZNS or SYS_RLKSUBM register according to security attribute of each circuit. + * |[20] |HSUSBH0RST|High-speed USB Host Controller 0 Reset Enable Bit (Write Protect) + * | | |0 = High-Speed USB host controller 0 reset Disabled. + * | | |1 = High-Speed USB host controller 0 reset Enabled. + * | | |Note: This bit is write protected + * | | |Refer to the SYS_RLKTZS, SYS_RLKTZNS or SYS_RLKSUBM register according to security attribute of each circuit. + * |[21] |HSUSBH1RST|High-speed USB Host Controller 1 Reset Enable Bit (Write Protect) + * | | |0 = High-Speed USB host controller 1 reset Disabled. + * | | |1 = High-Speed USB host controller 1 reset Enabled. + * | | |Note: This bit is write protected + * | | |Refer to the SYS_RLKTZS, SYS_RLKTZNS or SYS_RLKSUBM register according to security attribute of each circuit. + * |[22] |HSUSBDRST |High-speed USB Device Controller Reset Enable Bit (Write Protect) + * | | |0 = High-Speed USB device controller reset Disabled. + * | | |1 = High-Speed USB device controller reset Enabled. + * | | |Note: This bit is write protected + * | | |Refer to the SYS_RLKTZS, SYS_RLKTZNS or SYS_RLKSUBM register according to security attribute of each circuit. + * |[24] |SDH0RST |SDIO Controller 0 Reset Enable Bit (Write Protect) + * | | |0 = SDIO controller 0 reset Disabled. + * | | |1 = SDIO controller 0 reset Enabled. + * | | |Note: This bit is write protected + * | | |Refer to the SYS_RLKTZS, SYS_RLKTZNS or SYS_RLKSUBM register according to security attribute of each circuit. + * |[25] |SDH1RST |SDIO Controller 1 Reset Enable Bit (Write Protect) + * | | |0 = SDIO controller 1 reset Disabled. + * | | |1 = SDIO controller 1 reset Enabled. + * | | |Note: This bit is write protected + * | | |Refer to the SYS_RLKTZS, SYS_RLKTZNS or SYS_RLKSUBM register according to security attribute of each circuit. + * |[26] |NANDRST |NAND Flash Controller Reset Enable Bit (Write Protect) + * | | |0 = NAND Flash controller reset Disabled. + * | | |1 = NAND Flash controller reset Enabled. + * | | |Note: This bit is write protected + * | | |Refer to the SYS_RLKTZS, SYS_RLKTZNS or SYS_RLKSUBM register according to security attribute of each circuit. + * |[27] |GPIORST |GPIO Reset Enable Bit (Write Protect) + * | | |0 = GPIO reset Disabled. + * | | |1 = GPIO reset Enabled. + * | | |Note: This bit is write protected + * | | |Refer to the SYS_RLKTZS, SYS_RLKTZNS or SYS_RLKSUBM register according to security attribute of each circuit. + * |[28] |MCTLPRST |DDR Memory Controller MCTL2 APB Interface Reset Enable Bit (Write Protect) + * | | |Write 1 to enable MCTL2 APB reset to reset APB interface logic of MCTL2. + * | | |Write 0 to trigger a reset disable procedure and this bit cleared automatically after 128 pclk. + * | | |0 = DDR Memory Controller MCTL2 APB interface reset Disabled. + * | | |1 = DDR Memory Controller MCTL2 APB interface reset Enabled. + * | | |Note 1: Once trigger reset disable procedure, it's necessary to poll MCTLPRST till its 0. + * | | |Note 2: This bit is write protected + * | | |Refer to the SYS_RLKTZS, SYS_RLKTZNS or SYS_RLKSUBM register according to security attribute of each circuit. + * |[29] |MCTLCRST |DDR Memory Controller MCTL2 Core Reset Enable Bit (Write Protect) + * | | |0 = DDR Memory Controller MCTL2 core reset Disabled. + * | | |1 = DDR Memory Controller MCTL2 core reset Enabled. + * | | |Note: This bit is write protected + * | | |Refer to the SYS_RLKTZS, SYS_RLKTZNS or SYS_RLKSUBM register according to security attribute of each circuit. + * |[30] |DDRPUBRST |DDR PHY PUB Reset Enable Bit (Write Protect) + * | | |0 = DDR PHY PUB reset Disabled. + * | | |1 = DDR PHY PUB reset Enabled. + * | | |Note: This bit is write protected + * | | |Refer to the SYS_RLKTZS, SYS_RLKTZNS or SYS_RLKSUBM register according to security attribute of each circuit. + * @var SYS_T::IPRST1 + * Offset: 0x24 Reset Control Register 1 (Shared) + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[2] |TMR0RST |TIMER 0 Reset Enable Bit (Write Protect) + * | | |0 = TIMER 0 reset Disabled. + * | | |1 = TIMER 0 reset Enabled. + * | | |Note: This bit is write protected + * | | |Refer to the SYS_RLKTZS, SYS_RLKTZNS or SYS_RLKSUBM register according to security attribute of each circuit. + * |[3] |TMR1RST |TIMER 1 Reset Enable Bit (Write Protect) + * | | |0 = TIMER 1 reset Disabled. + * | | |1 = TIMER 1 reset Enabled. + * | | |Note: This bit is write protected + * | | |Refer to the SYS_RLKTZS, SYS_RLKTZNS or SYS_RLKSUBM register according to security attribute of each circuit. + * |[4] |TMR2RST |TIMER 2 Reset Enable Bit (Write Protect) + * | | |0 = TIMER 2 reset Disabled. + * | | |1 = TIMER 2 reset Enabled. + * | | |Note: This bit is write protected + * | | |Refer to the SYS_RLKTZS, SYS_RLKTZNS or SYS_RLKSUBM register according to security attribute of each circuit. + * |[5] |TMR3RST |TIMER 3 Reset Enable Bit (Write Protect) + * | | |0 = TIMER 3 reset Disabled. + * | | |1 = TIMER 3 reset Enabled. + * | | |Note: This bit is write protected + * | | |Refer to the SYS_RLKTZS, SYS_RLKTZNS or SYS_RLKSUBM register according to security attribute of each circuit. + * |[8] |I2C0RST |I2C 0 Reset Enable Bit (Write Protect) + * | | |0 = I2C 0 reset Disabled. + * | | |1 = I2C 0 reset Enabled. + * | | |Note: This bit is write protected + * | | |Refer to the SYS_RLKTZS, SYS_RLKTZNS or SYS_RLKSUBM register according to security attribute of each circuit. + * |[9] |I2C1RST |I2C 1 Reset Enable Bit (Write Protect) + * | | |0 = I2C 1 reset Disabled. + * | | |1 = I2C 1 reset Enabled. + * | | |Note: This bit is write protected + * | | |Refer to the SYS_RLKTZS, SYS_RLKTZNS or SYS_RLKSUBM register according to security attribute of each circuit. + * |[10] |I2C2RST |I2C 2 Reset Enable Bit (Write Protect) + * | | |0 = I2C 2 reset Disabled. + * | | |1 = I2C 2 reset Enabled. + * | | |Note: This bit is write protected + * | | |Refer to the SYS_RLKTZS, SYS_RLKTZNS or SYS_RLKSUBM register according to security attribute of each circuit. + * |[11] |I2C3RST |I2C 3 Reset Enable Bit (Write Protect) + * | | |0 = I2C 3 reset Disabled. + * | | |1 = I2C 3 reset Enabled. + * | | |Note: This bit is write protected + * | | |Refer to the SYS_RLKTZS, SYS_RLKTZNS or SYS_RLKSUBM register according to security attribute of each circuit. + * |[12] |QSPI0RST |QSPI 0 Reset Enable Bit (Write Protect) + * | | |0 = QSPI 0 reset Disabled. + * | | |1 = QSPI 0 reset Enabled. + * | | |Note: This bit is write protected + * | | |Refer to the SYS_RLKTZS, SYS_RLKTZNS or SYS_RLKSUBM register according to security attribute of each circuit. + * |[13] |SPI0RST |SPI 0 Reset Enable Bit (Write Protect) + * | | |0 = SPI 0 reset Disabled. + * | | |1 = SPI 0 reset Enabled. + * | | |Note: This bit is write protected + * | | |Refer to the SYS_RLKTZS, SYS_RLKTZNS or SYS_RLKSUBM register according to security attribute of each circuit. + * |[14] |SPI1RST |SPI 1 Reset Enable Bit (Write Protect) + * | | |0 = SPI 1 reset Disabled. + * | | |1 = SPI 1 reset Enabled. + * | | |Note: This bit is write protected + * | | |Refer to the SYS_RLKTZS, SYS_RLKTZNS or SYS_RLKSUBM register according to security attribute of each circuit. + * |[15] |SPI2RST |SPI 2 Reset Enable Bit (Write Protect) + * | | |0 = SPI 2 reset Disabled. + * | | |1 = SPI 2 reset Enabled. + * | | |Note: This bit is write protected + * | | |Refer to the SYS_RLKTZS, SYS_RLKTZNS or SYS_RLKSUBM register according to security attribute of each circuit. + * |[16] |UART0RST |UART 0 Reset Enable Bit (Write Protect) + * | | |0 = UART 0 reset Disabled. + * | | |1 = UART 0 reset Enabled. + * | | |Note: This bit is write protected + * | | |Refer to the SYS_RLKTZS, SYS_RLKTZNS or SYS_RLKSUBM register according to security attribute of each circuit. + * |[17] |UART1RST |UART 1 Reset Enable Bit (Write Protect) + * | | |0 = UART 1 reset Disabled. + * | | |1 = UART 1 reset Enabled. + * | | |Note: This bit is write protected + * | | |Refer to the SYS_RLKTZS, SYS_RLKTZNS or SYS_RLKSUBM register according to security attribute of each circuit. + * |[18] |UART2RST |UART 2 Reset Enable Bit (Write Protect) + * | | |0 = UART 2 reset Disabled. + * | | |1 = UART 2 reset Enabled. + * | | |Note: This bit is write protected + * | | |Refer to the SYS_RLKTZS, SYS_RLKTZNS or SYS_RLKSUBM register according to security attribute of each circuit. + * |[19] |UART3RST |UART 3 Reset Enable Bit (Write Protect) + * | | |0 = UART 3 reset Disabled. + * | | |1 = UART 3 reset Enabled. + * | | |Note: This bit is write protected + * | | |Refer to the SYS_RLKTZS, SYS_RLKTZNS or SYS_RLKSUBM register according to security attribute of each circuit. + * |[20] |UART4RST |UART 4 Reset Enable Bit (Write Protect) + * | | |0 = UART 4 reset Disabled. + * | | |1 = UART 4 reset Enabled. + * | | |Note: This bit is write protected + * | | |Refer to the SYS_RLKTZS, SYS_RLKTZNS or SYS_RLKSUBM register according to security attribute of each circuit. + * |[21] |UART5RST |UART 5 Reset Enable Bit (Write Protect) + * | | |0 = UART 5 reset Disabled. + * | | |1 = UART 5 reset Enabled. + * | | |Note: This bit is write protected + * | | |Refer to the SYS_RLKTZS, SYS_RLKTZNS or SYS_RLKSUBM register according to security attribute of each circuit. + * |[22] |UART6RST |UART 6 Reset Enable Bit (Write Protect) + * | | |0 = UART 6 reset Disabled. + * | | |1 = UART 6 reset Enabled. + * | | |Note: This bit is write protected + * | | |Refer to the SYS_RLKTZS, SYS_RLKTZNS or SYS_RLKSUBM register according to security attribute of each circuit. + * |[23] |UART7RST |UART 7 Reset Enable Bit (Write Protect) + * | | |0 = UART 7 reset Disabled. + * | | |1 = UART 7 reset Enabled. + * | | |Note: This bit is write protected + * | | |Refer to the SYS_RLKTZS, SYS_RLKTZNS or SYS_RLKSUBM register according to security attribute of each circuit. + * |[24] |CANFD0RST |CAN FD 1 Reset Enable Bit (Write Protect) + * | | |0 = CAN FD 1 reset Disabled. + * | | |1 = CAN FD 1 reset Enabled. + * | | |Note: This bit is write protected + * | | |Refer to the SYS_RLKTZS, SYS_RLKTZNS or SYS_RLKSUBM register according to security attribute of each circuit. + * |[25] |CANFD1RST |CAN FD 1 Reset Enable Bit (Write Protect) + * | | |0 = CAN FD 1 reset Disabled. + * | | |1 = CAN FD 1 reset Enabled. + * | | |Note: This bit is write protected + * | | |Refer to the SYS_RLKTZS, SYS_RLKTZNS or SYS_RLKSUBM register according to security attribute of each circuit. + * |[28] |EADC0RST |EADC 0 Reset Enable Bit (Write Protect) + * | | |0 = EADC 0 reset Disabled. + * | | |1 = EADC 0 reset Enabled. + * | | |Note: This bit is write protected + * | | |Refer to the SYS_RLKTZS, SYS_RLKTZNS or SYS_RLKSUBM register according to security attribute of each circuit. + * |[29] |I2S0RST |I2S 0 Reset Enable Bit (Write Protect) + * | | |0 = I2S 0 reset Disabled. + * | | |1 = I2S 0 reset Enabled. + * | | |Note: This bit is write protected + * | | |Refer to the SYS_RLKTZS, SYS_RLKTZNS or SYS_RLKSUBM register according to security attribute of each circuit. + * @var SYS_T::IPRST2 + * Offset: 0x28 Reset Control Register 2 (Shared) + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[0] |SC0RST |SC 0 Reset Enable Bit (Write Protect) + * | | |0 = SC 0 reset Disabled. + * | | |1 = SC 0 reset Enabled. + * | | |Note: This bit is write protected + * | | |Refer to the SYS_RLKTZS, SYS_RLKTZNS or SYS_RLKSUBM register according to security attribute of each circuit. + * |[1] |SC1RST |SC 1 Reset Enable Bit (Write Protect) + * | | |0 = SC 1 reset Disabled. + * | | |1 = SC 1 reset Enabled. + * | | |Note: This bit is write protected + * | | |Refer to the SYS_RLKTZS, SYS_RLKTZNS or SYS_RLKSUBM register according to security attribute of each circuit. + * |[4] |QSPI1RST |QSPI 1 Reset Enable Bit (Write Protect) + * | | |0 = QSPI 1 reset Disabled. + * | | |1 = QSPI 1 reset Enabled. + * | | |Note: This bit is write protected + * | | |Refer to the SYS_RLKTZS, SYS_RLKTZNS or SYS_RLKSUBM register according to security attribute of each circuit. + * |[6] |SPI3RST |SPI 3 Reset Enable Bit (Write Protect) + * | | |0 = SPI 3 reset Disabled. + * | | |1 = SPI 3 reset Enabled. + * | | |Note: This bit is write protected + * | | |Refer to the SYS_RLKTZS, SYS_RLKTZNS or SYS_RLKSUBM register according to security attribute of each circuit. + * |[16] |EPWM0RST |EPWM 0 Reset Enable Bit (Write Protect) + * | | |0 = EPWM 0 reset Disabled. + * | | |1 = EPWM 0 reset Enabled. + * | | |Note: This bit is write protected + * | | |Refer to the SYS_RLKTZS, SYS_RLKTZNS or SYS_RLKSUBM register according to security attribute of each circuit. + * |[17] |EPWM1RST |EPWM 1 Reset Enable Bit (Write Protect) + * | | |0 = EPWM 1 reset Disabled. + * | | |1 = EPWM 1 reset Enabled. + * | | |Note: This bit is write protected + * | | |Refer to the SYS_RLKTZS, SYS_RLKTZNS or SYS_RLKSUBM register according to security attribute of each circuit. + * |[22] |QEI0RST |QEI 0 Reset Enable Bit (Write Protect) + * | | |0 = QEI 0 reset Disabled. + * | | |1 = QEI 0 reset Enabled. + * | | |Note: This bit is write protected + * | | |Refer to the SYS_RLKTZS, SYS_RLKTZNS or SYS_RLKSUBM register according to security attribute of each circuit. + * |[23] |QEI1RST |QEI 1 Reset Enable Bit (Write Protect) + * | | |0 = QEI 1 reset Disabled. + * | | |1 = QEI 1 reset Enabled. + * | | |Note: This bit is write protected + * | | |Refer to the SYS_RLKTZS, SYS_RLKTZNS or SYS_RLKSUBM register according to security attribute of each circuit. + * |[26] |ECAP0RST |ECAP 0 Reset Enable Bit (Write Protect) + * | | |0 = ECAP 0 reset Disabled. + * | | |1 = ECAP 0 reset Enabled. + * | | |Note: This bit is write protected + * | | |Refer to the SYS_RLKTZS, SYS_RLKTZNS or SYS_RLKSUBM register according to security attribute of each circuit. + * |[27] |ECAP1RST |ECAP 1 Reset Enable Bit (Write Protect) + * | | |0 = ECAP 1 reset Disabled. + * | | |1 = ECAP 1 reset Enabled. + * | | |Note: This bit is write protected + * | | |Refer to the SYS_RLKTZS, SYS_RLKTZNS or SYS_RLKSUBM register according to security attribute of each circuit. + * |[28] |CANFD2RST |CAN FD 2 Reset Enable Bit (Write Protect) + * | | |0 = CAN FD 2 reset Disabled. + * | | |1 = CAN FD 2 reset Enabled. + * | | |Note: This bit is write protected + * | | |Refer to the SYS_RLKTZS, SYS_RLKTZNS or SYS_RLKSUBM register according to security attribute of each circuit. + * |[31] |ADC0RST |ADC 0 Reset Enable Bit (Write Protect) + * | | |0 = ADC 0 reset Disabled. + * | | |1 = ADC 0 reset Enabled. + * | | |Note: This bit is write protected + * | | |Refer to the SYS_RLKTZS, SYS_RLKTZNS or SYS_RLKSUBM register according to security attribute of each circuit. + * @var SYS_T::IPRST3 + * Offset: 0x2C Reset Control Register 3 (Shared) + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[0] |TMR4RST |TIMER 4 Reset Enable Bit (Write Protect) + * | | |0 = TIMER 4 reset Disabled. + * | | |1 = TIMER 4 reset Enabled. + * | | |Note: This bit is write protected + * | | |Refer to the SYS_RLKTZS, SYS_RLKTZNS or SYS_RLKSUBM register according to security attribute of each circuit. + * |[1] |TMR5RST |TIMER 5 Reset Enable Bit (Write Protect) + * | | |0 = TIMER 5 reset Disabled. + * | | |1 = TIMER 5 reset Enabled. + * | | |Note: This bit is write protected + * | | |Refer to the SYS_RLKTZS, SYS_RLKTZNS or SYS_RLKSUBM register according to security attribute of each circuit. + * |[2] |TMR6RST |TIMER 6 Reset Enable Bit (Write Protect) + * | | |0 = TIMER 6 reset Disabled. + * | | |1 = TIMER 6 reset Enabled. + * | | |Note: This bit is write protected + * | | |Refer to the SYS_RLKTZS, SYS_RLKTZNS or SYS_RLKSUBM register according to security attribute of each circuit. + * |[3] |TMR7RST |TIMER 7 Reset Enable Bit (Write Protect) + * | | |0 = TIMER 7 reset Disabled. + * | | |1 = TIMER 7 reset Enabled. + * | | |Note: This bit is write protected + * | | |Refer to the SYS_RLKTZS, SYS_RLKTZNS or SYS_RLKSUBM register according to security attribute of each circuit. + * |[4] |TMR8RST |TIMER 8 Reset Enable Bit (Write Protect) + * | | |0 = TIMER 8 reset Disabled. + * | | |1 = TIMER 8 reset Enabled. + * | | |Note: This bit is write protected + * | | |Refer to the SYS_RLKTZS, SYS_RLKTZNS or SYS_RLKSUBM register according to security attribute of each circuit. + * |[5] |TMR9RST |TIMER 9 Reset Enable Bit (Write Protect) + * | | |0 = TIMER 9 reset Disabled. + * | | |1 = TIMER 9 reset Enabled. + * | | |Note: This bit is write protected + * | | |Refer to the SYS_RLKTZS, SYS_RLKTZNS or SYS_RLKSUBM register according to security attribute of each circuit. + * |[6] |TMR10RST |TIMER 10 Reset Enable Bit (Write Protect) + * | | |0 = TIMER 10 reset Disabled. + * | | |1 = TIMER 10 reset Enabled. + * | | |Note: This bit is write protected + * | | |Refer to the SYS_RLKTZS, SYS_RLKTZNS or SYS_RLKSUBM register according to security attribute of each circuit. + * |[7] |TMR11RST |TIMER 11 Reset Enable Bit (Write Protect) + * | | |0 = TIMER 11 reset Disabled. + * | | |1 = TIMER 11 reset Enabled. + * | | |Note: This bit is write protected + * | | |Refer to the SYS_RLKTZS, SYS_RLKTZNS or SYS_RLKSUBM register according to security attribute of each circuit. + * |[8] |UART8RST |UART 8 Reset Enable Bit (Write Protect) + * | | |0 = UART 8 reset Disabled. + * | | |1 = UART 8 reset Enabled. + * | | |Note: This bit is write protected + * | | |Refer to the SYS_RLKTZS, SYS_RLKTZNS or SYS_RLKSUBM register according to security attribute of each circuit. + * |[9] |UART9RST |UART 9 Reset Enable Bit (Write Protect) + * | | |0 = UART 9 reset Disabled. + * | | |1 = UART 9 reset Enabled. + * | | |Note: This bit is write protected + * | | |Refer to the SYS_RLKTZS, SYS_RLKTZNS or SYS_RLKSUBM register according to security attribute of each circuit. + * |[10] |UART10RST |UART 10 Reset Enable Bit (Write Protect) + * | | |0 = UART 10 reset Disabled. + * | | |1 = UART 10 reset Enabled. + * | | |Note: This bit is write protected + * | | |Refer to the SYS_RLKTZS, SYS_RLKTZNS or SYS_RLKSUBM register according to security attribute of each circuit. + * |[11] |UART11RST |UART 11 Reset Enable Bit (Write Protect) + * | | |0 = UART 11 reset Disabled. + * | | |1 = UART 11 reset Enabled. + * | | |Note: This bit is write protected + * | | |Refer to the SYS_RLKTZS, SYS_RLKTZNS or SYS_RLKSUBM register according to security attribute of each circuit. + * |[12] |UART12RST |UART 12 Reset Enable Bit (Write Protect) + * | | |0 = UART 12 reset Disabled. + * | | |1 = UART 12 reset Enabled. + * | | |Note: This bit is write protected + * | | |Refer to the SYS_RLKTZS, SYS_RLKTZNS or SYS_RLKSUBM register according to security attribute of each circuit. + * |[13] |UART13RST |UART 13 Reset Enable Bit (Write Protect) + * | | |0 = UART 13 reset Disabled. + * | | |1 = UART 13 reset Enabled. + * | | |Note: This bit is write protected + * | | |Refer to the SYS_RLKTZS, SYS_RLKTZNS or SYS_RLKSUBM register according to security attribute of each circuit. + * |[14] |UART14RST |UART 14 Reset Enable Bit (Write Protect) + * | | |0 = UART 14 reset Disabled. + * | | |1 = UART 14 reset Enabled. + * | | |Note: This bit is write protected + * | | |Refer to the SYS_RLKTZS, SYS_RLKTZNS or SYS_RLKSUBM register according to security attribute of each circuit. + * |[15] |UART15RST |UART 15 Reset Enable Bit (Write Protect) + * | | |0 = UART 15 reset Disabled. + * | | |1 = UART 15 reset Enabled. + * | | |Note: This bit is write protected + * | | |Refer to the SYS_RLKTZS, SYS_RLKTZNS or SYS_RLKSUBM register according to security attribute of each circuit. + * |[16] |UART16RST |UART 16 Reset Enable Bit (Write Protect) + * | | |0 = UART 16 reset Disabled. + * | | |1 = UART 16 reset Enabled. + * | | |Note: This bit is write protected + * | | |Refer to the SYS_RLKTZS, SYS_RLKTZNS or SYS_RLKSUBM register according to security attribute of each circuit. + * |[17] |I2S1RST |I2S 1 Reset Enable Bit (Write Protect) + * | | |0 = I2S 1 reset Disabled. + * | | |1 = I2S 1 reset Enabled. + * | | |Note: This bit is write protected + * | | |Refer to the SYS_RLKTZS, SYS_RLKTZNS or SYS_RLKSUBM register according to security attribute of each circuit. + * |[18] |I2C4RST |I2C 4 Reset Enable Bit (Write Protect) + * | | |0 = I2C 4 reset Disabled. + * | | |1 = I2C 4reset Enabled. + * | | |Note: This bit is write protected + * | | |Refer to the SYS_RLKTZS, SYS_RLKTZNS or SYS_RLKSUBM register according to security attribute of each circuit. + * |[19] |I2C5RST |I2C 5 Reset Enable Bit (Write Protect) + * | | |0 = I2C 5 reset Disabled. + * | | |1 = I2C 5 reset Enabled. + * | | |Note: This bit is write protected + * | | |Refer to the SYS_RLKTZS, SYS_RLKTZNS or SYS_RLKSUBM register according to security attribute of each circuit. + * |[20] |EPWM2RST |EPWM 2 Reset Enable Bit (Write Protect) + * | | |0 = EPWM 2 reset Disabled. + * | | |1 = EPWM 2 reset Enabled. + * | | |Note: This bit is write protected + * | | |Refer to the SYS_RLKTZS, SYS_RLKTZNS or SYS_RLKSUBM register according to security attribute of each circuit. + * |[21] |ECAP2RST |ECAP 2 Reset Enable Bit (Write Protect) + * | | |0 = ECAP 2 reset Disabled. + * | | |1 = ECAP 2 reset Enabled. + * | | |Note: This bit is write protected + * | | |Refer to the SYS_RLKTZS, SYS_RLKTZNS or SYS_RLKSUBM register according to security attribute of each circuit. + * |[22] |QEI2RST |QEI 2 Reset Enable Bit (Write Protect) + * | | |0 = QEI 2 reset Disabled. + * | | |1 = QEI 2 reset Enabled. + * | | |Note: This bit is write protected + * | | |Refer to the SYS_RLKTZS, SYS_RLKTZNS or SYS_RLKSUBM register according to security attribute of each circuit. + * |[23] |CANFD3RST |CAN FD 3 Reset Enable Bit (Write Protect) + * | | |0 = CAN FD 3 reset Disabled. + * | | |1 = CAN FD 3 reset Enabled. + * | | |Note: This bit is write protected + * | | |Refer to the SYS_RLKTZS, SYS_RLKTZNS or SYS_RLKSUBM register according to security attribute of each circuit. + * |[24] |KPIRST |KPI Reset Enable Bit (Write Protect) + * | | |0 = KPI reset Disabled. + * | | |1 = KPI reset Enabled. + * | | |Note: This bit is write protected + * | | |Refer to the SYS_RLKTZS, SYS_RLKTZNS or SYS_RLKSUBM register according to security attribute of each circuit. + * |[28] |GICRST |GIC Reset Enable Bit (Write Protect) + * | | |0 = GIC reset Disabled. + * | | |1 = GIC reset Enabled. + * | | |Note: This bit is write protected + * | | |Refer to the SYS_RLKTZS, SYS_RLKTZNS or SYS_RLKSUBM register according to security attribute of each circuit. + * |[30] |SSMCCRST |SSMCC Reset Enable Bit (Write Protect) + * | | |0 = SSMCC reset Disabled. + * | | |1 = SSMCC reset Enabled. + * | | |Note: This bit is write protected + * | | |Refer to the SYS_RLKTZS, SYS_RLKTZNS or SYS_RLKSUBM register according to security attribute of each circuit. + * |[31] |SSPCCRST |SSPCC Reset Enable Bit (Write Protect) + * | | |0 = SSPCC reset Disabled. + * | | |1 = SSPCC reset Enabled. + * | | |Note: This bit is write protected + * | | |Refer to the SYS_RLKTZS, SYS_RLKTZNS or SYS_RLKSUBM register according to security attribute of each circuit. + * @var SYS_T::PMUCR + * Offset: 0x30 Power Management Unit Control Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[0] |A35PGEN |Cortex-A35 Power Gating Enable (Write Protect) + * | | |0 = Cortex-A35 dual core power gating Disabled. + * | | |1 = Cortex-A35 dual core power gating Enabled. + * | | |Note: This bit is write protected. Refer to the SYS_RLKTZS register. + * |[4] |AUTOL2FDIS|Automatic L2 Cache Flush Disable (Write Protect) + * | | |0 = Automatic L2 cache flush Enabled. + * | | |1 = Automatic L2 cache flush Disabled. + * | | |Note: This bit is write protected. Refer to the SYS_RLKTZS register. + * |[6] |PDWKDLY |Wake-up Delay Counter Enable Bit (Write Protect) + * | | |When the Cortex-A35 wakes up from Power-down mode, the clock control will delay certain clock cycles to wait system clock stable. + * | | |The delayed clock cycle is 4096 clock cycles when chip works at 24 Mhz external high speed crystal oscillator (HXT), and 256 clock cycles when chip works at 12 MHz internal high speed RC oscillator (HIRC). + * | | |0 = Wake-up delay counter Disabled. + * | | |1 = Wake-up delay counter Enabled. + * | | |Note: This bit is write protected. Refer to the SYS_RLKTZS register. + * |[11:8] |PWRSTBTM |Power Gating Acknowledgement Stable Time (Write Protect) + * | | |The PWRSTBTM indicates the stable time after receiving power gating acknowledgement. + * | | |0000 = 5us (Default). + * | | |0001 = 10us. + * | | |0010 = 20us. + * | | |0011 = 40us. + * | | |0100 = 60us. + * | | |0101 = 80us. + * | | |0110 = 100us. + * | | |0111 = 200us. + * | | |1000 = 400us. + * | | |1001 = 600us. + * | | |1010 = 800us. + * | | |1011 = 1ms. + * | | |1100 = 2ms. + * | | |1101 = 4ms. + * | | |1110 = 5.4ms. + * | | |1111 = 0us. + * | | |Note: This bit is write protected. Refer to the SYS_RLKTZS register. + * |[15:12] |PWRACKTO |Power Gating Acknowledgement Time Out Selection (Write Protect) + * | | |0000 = 20us (Default). + * | | |0001 = 30us. + * | | |0010 = 40us. + * | | |0011 = 50us. + * | | |0100 = 60us. + * | | |0101 = 80us. + * | | |0110 = 100us. + * | | |0111 = 200us. + * | | |1000 = 400us. + * | | |1001 = 600us. + * | | |1010 = 800us. + * | | |1011 = 1ms. + * | | |1100 = 2ms. + * | | |1101 = 4ms. + * | | |1110 = 5.4ms. + * | | |1111 = 0us. + * | | |Note: This bit is write protected. Refer to the SYS_RLKTZS register. + * |[16] |A35PDEN |Cortex-A35 Power Down Enable Bit (Write Protect) + * | | |When this bit is set to 1, Power-down mode is enabled and the chip keeps active till the CPU sleep mode is also active and then the chip enters Power-down mode. + * | | |When chip wakes up from Power-down mode, this bit is auto cleared + * | | |Users need to set this bit again for next Power-down. + * | | |In Power-down mode, HXT, HIRC, HIRC48, PLL and system clock will be disabled and ignored the clock source selection + * | | |The clocks of peripheral are not controlled by Power-down mode, if the peripheral clock source is from LXT or LIRC. + * | | |0 = Chip operating normally or chip in idle mode because of WFI command. + * | | |1 = Chip waits CPU sleep command WFI and then enters Power-down mode. + * | | |Note: This bit is write protected. Refer to the SYS_RLKTZS register. + * |[18] |A35DBPDEN |Cortex-A35 Entering Power-down Even ICE Connected (Write Protect) + * | | |0 = Cortex-A35 does not enter Power-down during Debug mode. + * | | |1 = Cortex-A35 enters power-down in Debug mode. + * | | |Note: This bit is write protected. Refer to the SYS_RLKTZS register. + * |[24] |RTPPDEN |RTP M4 Power Down Enable (Write Protect) + * | | |When this bit is set to 1, Power-down mode is enabled and the chip keeps active till the CPU sleep mode is also active and then the chip enters Power-down mode. + * | | |When chip wakes up from Power-down mode, this bit is auto cleared + * | | |Users need to set this bit again for next Power-down. + * | | |In Power-down mode, HXT, HIRC, HIRC48, PLL and system clock will be disabled and ignored the clock source selection + * | | |The clocks of peripheral are not controlled by Power-down mode, if the peripheral clock source is from LXT or LIRC. + * | | |0 = Chip operating normally or chip in idle mode because of WFI command. + * | | |1 = Chip waits CPU sleep command WFI and then enters Power-down mode. + * | | |Note: This bit is write protected. Refer to the SYS_RLKTZS register. + * |[26] |RTPDBPDEN |RTP M4 Entering Power-down Even ICE Connected (Write Protect) + * | | |0 = RTP M4 does not enter Power-down during Debug mode. + * | | |1 = RTP M4 enters power-down in Debug mode. + * | | |Note: This bit is write protected. Refer to the SYS_RLKSUBM register. + * @var SYS_T::DDRCQCSR + * Offset: 0x34 DDR Controller Q Channel Control and Status Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[7:0] |AXIQBYPAS |DDR Controller AXI Port 7 ~ Port 0 Q Channel Handshake Bypass (Write Protect) + * | | |The AXIQBYPAS indicates to bypass DDR controller's AXI port Q channel handshake mechanism + * | | |The each bit of AXIQBYPAS is for corresponding AXI port of DDR controller. + * | | |AXIQBYPAS[x] + * | | |0 = Q channel handshake mechanism of AXI port x Not Bypassed (x=0, 1, ?? 7). + * | | |1 = Q channel handshake mechanism of AXI port x Bypassed (x=0, 1, ?? 7). + * | | |Note: This bit is write protected. Refer to the SYS_RLKTZS register. + * |[15:8] |AXIQDENYIF|DDR Controller AXI Port 7 ~ Port 0 Q Channel Interrupt Flag + * | | |0 = Q channel power down request accept by DDR controller AXI port x (x=0, 1, ?? 7). + * | | |1 = Q channel power down request reject by DDR controller AXI port x, AXI port x wouldn't enter low power mode and clock of AXI port x keep clocking (x=0, 1, ?? 7). + * |[16] |DDRCQBYPAS|DDR Controller Core Q Channel Handshake Bypass (Write Protect) + * | | |0 = Q channel handshake of DDR controller core Not Bypassed. + * | | |1 = Q channel handshake of DDR controller core Bypassed. + * | | |Note: This bit is write protected. Refer to the SYS_RLKTZS register. + * |[17] |DDRCQDENYIF|DDR Controller Core Q Channel Deny Interrupt Flag + * | | |0 = Q channel power down request accept by DDR controller core. + * | | |1 = Q channel power down request reject by DDR controller core and DDR controller wouldn't enter self-refresh mode. + * |[27:24] |DDRQREQDLY|DDR Controller Q Channel Request Delay Time Selection (Write Protect) + * | | |0000 = 20us (Default). + * | | |0001 = 30us. + * | | |0010 = 40us. + * | | |0011 = 50us. + * | | |0100 = 60us. + * | | |0101 = 80us. + * | | |0110 = 100us. + * | | |0111 = 200us. + * | | |1000 = 400us. + * | | |1001 = 600us. + * | | |1010 = 800us. + * | | |1011 = 1ms. + * | | |1100 = 2ms. + * | | |1101 = 3ms. + * | | |1110 = 5.4ms. + * | | |1111 = 0us. + * | | |Note: This bit is write protected. Refer to the SYS_RLKTZS register. + * |[31:28] |DDRQACKTO |DDR Controller Q Channel Acknowledgement Time Out Selection (Write Protect) + * | | |0000 = 20us (Default). + * | | |0001 = 30us. + * | | |0010 = 40us. + * | | |0011 = 50us. + * | | |0100 = 60us. + * | | |0101 = 80us. + * | | |0110 = 100us. + * | | |0111 = 200us. + * | | |1000 = 400us. + * | | |1001 = 600us. + * | | |1010 = 800us. + * | | |1011 = 1ms. + * | | |1100 = 2ms. + * | | |1101 = 3ms. + * | | |1110 = 5.4ms. + * | | |1111 = 0us. + * | | |Note: This bit is write protected. Refer to the SYS_RLKTZS register. + * @var SYS_T::PMUIEN + * Offset: 0x38 Power Management Unit Interrupt Enable Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[0] |PMUIEN |PMU Interrupt Enable Control Bit (Write Protect) + * | | |0 = PMU interrupt Disabled. + * | | |1 = PMU interrupt Enabled. + * | | |Note: This bit is write protected. Refer to the SYS_RLKTZS register. + * |[8] |A35PDWKIEN|Cortex-A35 Power-down Wake-up Interrupt Enable Control Bit (Write Protect) + * | | |0 = Cortex-a35 wake-up interrupt Disabled. + * | | |1 = Cortex-a35 wake-up interrupt Enabled. + * | | |Note: This bit is write protected. Refer to the SYS_RLKTZS register. + * |[12] |RTPPDWKIEN|RTP M4 Power-down Wake-up Interrupt Enable Control Bit (Write Protect) + * | | |0 = RTP M4 wake-up interrupt Disabled. + * | | |1 = RTP M4 wake-up interrupt Enabled. + * | | |Note: This bit is write protected. Refer to the SYS_RLKSUBM register. + * @var SYS_T::PMUSTS + * Offset: 0x3C Power Management Unit Status Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[0] |PMUIF |PMU Interrupt Flag + * | | |When PMUIEN high, this bit high to indicate that PGTOIF, DDRCQDENYIF or AXIQDENYIF is active + * | | |When PMUIEN low, this bit didn't take effect. + * | | |0 = PGTOIF, DDRCQDENYIF and AXIQDENYIF are not active. + * | | |1 = PGTOIF, DDRCQDENYIF or AXIQDENYIF is active. + * |[1] |PGTOIF |Power Gating Time Out Interrupt Flag + * | | |0 = Power gating acknowledgement counter is not time-out yet. + * | | |1 = Power gating acknowledgement counter is time-out. + * |[5] |L2FDONE |Cortex-A35 L2 Cache Flush Done Status + * | | |0 = Cortex-A35 L2 cache flush didn't finish yet. + * | | |1 = Cortex-A35 L2 cache flush done. + * |[8] |A35PDWKIF |Cortex-A35 Power-down Wake-up Interrupt Flag + * | | |0 = Cortex-A35 didn't wake-up from power-down mode. + * | | |1 = Cortex-A35 receive a wake-up event and wake-up from power-down mode. + * |[12] |RTPPDWKIF |RTP M4 Power-down Wake-up Interrupt Flag + * | | |0 = RTP M4 didn't wake-up from power-down mode. + * | | |1 = RTP M4 receive a wake-up event and wake-up from power-down mode. + * |[31:16] |PWRACKCNT |Power Gating Acknowledgement Timing Counter Value + * | | |The PWRACKCNT show the value of power gating acknowledgement time-out counter. + * @var SYS_T::CA35WRBADR0 + * Offset: 0x40 Cortexu00AE-A35 Core 0 Warm-boot Address Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[31:0] |WRMBTADDR |Warm Boot Address + * | | |The WRMBTADDR indicates the warm boot run address for Cortex-A35 Core 0. + * @var SYS_T::CA35WRBPAR0 + * Offset: 0x44 Cortexu00AE-A35 Core 0 Warm-boot Parameter Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[31:0] |WRMBTPARA |Warm Boot Parameter + * | | |The WRMBTPARA indicates the warm boot parameters for Cortex-A35 Core 0. + * @var SYS_T::CA35WRBADR1 + * Offset: 0x48 Cortexu00AE-A35 Core 1 Warm-boot Address Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[31:0] |WRMBTADDR |Warm Boot Address + * | | |The WRMBTADDR indicates the warm boot run address for Cortex-A35 Core 1. + * @var SYS_T::CA35WRBPAR1 + * Offset: 0x4C Cortexu00AE-A35 Core 1 Warm-boot Parameter Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[31:0] |WRMBTPARA |Warm Boot Parameter + * | | |The WRMBTPARA indicates the warm boot parameters for Cortex-A35 Core 1. + * @var SYS_T::USBPMISCR + * Offset: 0x60 USB PHY Miscellaneous Control Register (TZNS) + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[0] |PHY0POR |USB 2.0 Port 0 High-speed PHY Power-On Reset Control Bit + * | | |0 = All test registers and state machines in the USB 2.0 port 0 high-speed PHY are not in reset state. + * | | |1 = All test registers and state machines in the USB 2.0 port 0 high-speed PHY are in reset state. + * |[1] |PHY0SUSPEND|USB 2.0 Port 0 High-speed PHY Suspend Control Bit + * | | |0 = USB 2.0 port 0 high-speed PHY is in Suspend mode. + * | | |1 = USB 2.0 port 0 high-speed PHY is in Normal operating mode. + * |[2] |PHY0COMN |USB 2.0 Port 0 High-speed PHY Common Block Power-Down Control Bit + * | | |0 = In Suspend or Sleep modes, the REFCLK_LOGIC, Bias and PLL blocks of USB 2.0 port 0 high-speed PHY remain powered + * | | |With this setting, the input reference clock must remain on and valid during suspend or sleep. + * | | |1 = In Suspend mode, the REFCLK_LOGIC, Bias and PLL blocks of USB 2.0 port 0 high-speed PHY are powered down + * | | |In Sleep mode, the Bias and PLL blocks of USB 2.0 port 0 high-speed PHY are powered down. + * |[6:4] |VBUSDGSEL |VBUS Detect De-glitch Time Select + * | | |000 = Without de-glitch function. + * | | |001 = 4 HIRC clock. + * | | |010 = 8 HIRC clock. + * | | |011 = 16 HIRC clock. + * | | |100 = 32 HIRC clock. + * | | |101 = 64 HIRC clock. + * | | |110 = 128 HIRC clock. + * | | |111 = 256 HIRC clock. + * |[7] |EFUSESEL0 |USB 2.0 Port 0 High-speed PHY Resistor Calibration with External Resistor Control Bit + * | | |0 = An external resistor (REXT) is needed and internal digital calibration code is based on REXT. + * | | |1 = Enable the internal resistor method with RCALCODE1 resistance control up to +/- 18%, allowing the removal of the REXT resistor. + * |[8] |PHY0HSTCKSTB|USB 2.0 Port 0 High-speed PHY 60 MHz UTMI Interface Clock for Host Stable Flag + * | | |0 = USB 2.0 port 0 high-speed PHY UTMI Interface clock for Host is not stable. + * | | |1 = USB 2.0 port 0 high-speed PHY UTMI Interface clock for Host is stable. + * |[9] |PHY0CK12MSTB|USB 2.0 Port 0 High-speed PHY 12 MHz Clock Stable Flag + * | | |0 = USB 2.0 port 0 high-speed PHY 12 MHz clock is not stable. + * | | |1 = USB 2.0 port 0 high-speed PHY 12 MHz clock is stable. + * |[10] |PHY0DEVCKSTB|USB 2.0 Port 0 High-speed PHY 60 MHz UTMI Interface Clock for Device Stable Flag + * | | |0 = USB 2.0 port 0 high-speed PHY UTMI Interface clock for Device is not stable. + * | | |1 = USB 2.0 port 0 high-speed PHY UTMI Interface clock for Device is stable. + * |[11] |RTUNESEL0 |USB 2.0 Port 0 High-speed PHY Source Impedance Tuning Method Selection + * | | |0 = Internal digital calibration codes are used for tuning the high-speed source impedance. + * | | |1 = The RCALCODE0 value is used for tuning the high-speed source impedance. + * |[15:12] |RCALCODE0 |USB 2.0 Port 0 High-Speed PHY Internal Resistor Trim Code + * | | |If RTUNESEL0 = 1, RCALCODE0 provides the tuning code for high-speed source impedance directly. + * | | |If RTUNESEL0 = 0, RCALCODE0 provides the tuning code for on-chip resistor within +/- 18% resistance tuning range. + * | | |0000 = +18% (236 u03A9). + * | | |0001 = +15.6%. + * | | |0010 = +13.2%. + * | | |0011 = +10.8%. + * | | |0100 = +8.4%. + * | | |0101 = +6%. + * | | |0110 = +3.6%. + * | | |0111 = +1.2%. + * | | |1000 = -1.2%. + * | | |1001 = -3.6%. + * | | |1010 = -6%. + * | | |1011 = -8.4%. + * | | |1100 = -10.8%. + * | | |1101 = -13.2%. + * | | |1110 = -15.6%. + * | | |1111 = -18% (164 u03A9). + * |[16] |PHY1POR |USB 2.0 Port 1 High-speed PHY Power-On Reset Control Bit + * | | |0 = All test registers and state machines in the USB 2.0 port 1 high-speed PHY are not in reset state. + * | | |1 = All test registers and state machines in the USB 2.0 port 1 high-speed PHY are in reset state. + * |[17] |PHY1SUSPEND|USB 2.0 Port 1 High-speed PHY Suspend Control Bit + * | | |0 = USB 2.0 port 1 high-speed PHY is in Suspend mode. + * | | |1 = USB 2.0 port 1 high-speed PHY is in Normal operating mode. + * |[18] |PHY1COMN |USB 2.0 Port 1 High-speed PHY Common Block Power-Down Control Bit + * | | |0 = In Suspend or Sleep modes, the REFCLK_LOGIC, Bias and PLL blocks of USB 2.0 port 1 high-speed PHY remain powered + * | | |With this setting, the input reference clock must remain on and valid during suspend or sleep. + * | | |1 = In Suspend mode, the REFCLK_LOGIC, Bias and PLL blocks of USB 2.0 port 1 high-speed PHY are powered down + * | | |In Sleep mode, the Bias and PLL blocks of USB 2.0 port 1 high-speed PHY are powered down. + * |[23] |EFUSESEL1 |USB 2.0 Port 1 High-speed PHY Resistor Calibration with External Resistor Control Bit + * | | |0 = An external resistor (REXT) is needed and internal digital calibration code is based on REXT. + * | | |1 = Enable the internal resistor method with RCALCODE1 resistance control up to +/- 18%, allowing the removal of the REXT resistor. + * |[24] |PHY1HSTCKSTB|USB 2.0 Port 1 High-speed PHY 60 MHz UTMI Interface Clock for Host Stable Flag + * | | |0 = USB 2.0 port 1 high-speed PHY UTMI Interface clock for Host is not stable. + * | | |1 = USB 2.0 port 1 high-speed PHY UTMI Interface clock for Host is stable. + * |[25] |PHY1CK12MSTB|USB 2.0 Port 1 High-speed PHY 12 MHz Clock Stable Flag + * | | |0 = USB 2.0 port 1 high-speed PHY 12 MHz clock is not stable. + * | | |1 = USB 2.0 port 1 high-speed PHY 12 MHz clock is stable. + * |[27] |RTUNESEL1 |USB 2.0 Port 1 High-speed PHY Source Impedance Tuning Method Selection + * | | |0 = Internal digital calibration codes are used for tuning the high-speed source impedance. + * | | |1 = The RCALCODE1 value is used for tuning the high-speed source impedance. + * |[31:28] |RCALCODE1 |USB 2.0 Port 1 High-Speed PHY Internal Resistor Trim Code + * | | |If RTUNESEL1 = 1, RCALCODE1 provides the tuning code for high-speed source impedance directly. + * | | |If RTUNESEL1 = 0, RCALCODE1 provides the tuning code for on-chip resistor within +/- 18% resistance tuning range. + * | | |0000 = +18% (236 u03A9). + * | | |0001 = +15.6%. + * | | |0010 = +13.2%. + * | | |0011 = +10.8%. + * | | |0100 = +8.4%. + * | | |0101 = +6%. + * | | |0110 = +3.6%. + * | | |0111 = +1.2%. + * | | |1000 = -1.2%. + * | | |1001 = -3.6%. + * | | |1010 = -6%. + * | | |1011 = -8.4%. + * | | |1100 = -10.8%. + * | | |1101 = -13.2%. + * | | |1110 = -15.6%. + * | | |1111 = -18% (164 u03A9). + * @var SYS_T::USBP0PCR + * Offset: 0x64 USB Port 0 PHY Control Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[2:0] |COMPDISTUNE|USB 2.0 High-speed Disconnect Threshold Adjustment + * | | |The SQRXTUNE adjusts the voltage level for the threshold used to detect a disconnect event at the host. + * | | |000 = -5.48%. + * | | |001 = 0. (Default) + * | | |010 = +6.04%. + * | | |011 = +12.75%. + * | | |100 = +19.66%. + * | | |101 = +28.24%. + * | | |110 = +38.31%. + * | | |111 = +50.28%. + * |[3] |EQBYPASSENB|USB 2.0 High-speed PHY Squelch Equalizer Bypass Control Bit + * | | |0 = Equalizer is Enabled. + * | | |1 = Equalizer is bypassed and acts as a simple differential input amplifier. + * |[6:4] |SQRXTUNE |USB 2.0 High-speed PHY Squelch Threshold Adjustment + * | | |The SQRXTUNE adjusts the voltage level for the threshold used to detect valid high-speed data. + * | | |000 = +15.5%. + * | | |001 = +10.87%. + * | | |010 = +5.86%. + * | | |011 = 0 (Default). + * | | |100 = -5.86%. + * | | |101 = -13.33%. + * | | |110 = -21.56%. + * | | |111 = -31.54%. + * |[7] |TXPREEMPPULSETUNE|USB 2.0 High-speed PHY Squelch Equalizer Bypass Control Bit + * | | |0 = Equalizer is Enabled. + * | | |1 = Equalizer is bypassed and acts as a simple differential input amplifier. + * |[11:8] |PLLPTUNE |USB 2.0 High-speed PHY PLL Proportional Path Tune + * | | |The value of PLLPTUNE should be keep in default. + * | | |0000 = 4.0x. + * | | |0001 = 4.5x. + * | | |0010 = 5.0x. + * | | |0011 = 5.5x. + * | | |0100 = 6.0x. + * | | |0101 = 6.5x. + * | | |0110 = 7.0x. + * | | |0111 = 7.5x. + * | | |1000 = 8.0x. + * | | |1001 = 8.5x. + * | | |1010 = 9.0x. + * | | |1011 = 9.5x. + * | | |1100 = 10.0x (Default). + * | | |1101 = 10.5x. + * | | |1110 = 11.0x. + * | | |1111 = 11.5x. + * |[15:12] |TXFSLSTUNE|USB 2.0 High-speed PHY FS/LS Source Impedance Adjustment + * | | |The TXFSLSTUNE adjusts the low- and full-speed single-ended source impedance while driving high. + * | | |0000 = +14.2%. + * | | |0001 = +6.60% + * | | |0011 = 0 (Default). + * | | |0111 = -5.48% + * | | |1111 = -10.29% + * |[17:16] |PLLITUNE |USB 2.0 High-speed PHY Integral Path Tune + * | | |The value of PLLITUNE should be keep in default. + * | | |00 = 1.0x (Default). + * | | |01 = 2.0x + * | | |10 = 3.0x + * | | |11 = 4.0x + * |[21:20] |TXPREEMPAMPTUNE|USB 2.0 High-speed PHY HS Transmitter Pre-Emphasis Current Control + * | | |00 = HS Transmitter pre-emphasis is disabled. (Default) + * | | |01 = HS Transmitter pre-emphasis circuit sources 1x pre-emphasis current. + * | | |10 = HS Transmitter pre-emphasis circuit sources 2x pre-emphasis current. + * | | |11 = HS Transmitter pre-emphasis circuit sources 3x pre-emphasis current. + * |[23:22] |TXRISETUNE|USB 2.0 High-speed PHY HS Transmitter Rise/Fall Time Adjustment + * | | |The TXRISETUNE adjusts the rise/fall times of the high-speed waveform. + * | | |00 = +7.34%. + * | | |01 = 0 (Default) + * | | |10 = -5.98%. + * | | |11 = -7.49% + * |[27:24] |TXVREFTUNE|USB 2.0 High-speed PHY HS DC Voltage Level Adjustment + * | | |The TXVREFTUNE adjusts the high-speed DC level voltage. + * | | |0000 = -9.37%. + * | | |0001 = -6.24%. + * | | |0010 = -3.12%. + * | | |0011 = 0 (Default) + * | | |0100 = +2.75%. + * | | |0101 = +5.87%. + * | | |0110 = +8.99%. + * | | |0111 = +12.11%. + * | | |1000 = +14.71%. + * | | |1001 = +17.82%. + * | | |1010 = +20.94%. + * | | |1011 = +24.06%. + * | | |1100 = +26.81%. + * | | |1101 = +29.94%. + * | | |1110 = +33.06%. + * | | |1111 = +36.18%. + * |[29:28] |TXHSXVTUNE|USB 2.0 High-speed PHY Transmitter High-Speed Crossover Adjustment + * | | |The TXHSXVTUNE adjusts the voltage at which the DP and DM signals cross while transmitting in HS mode. + * | | |00 = Reserved + * | | |01 = -9.16mV + * | | |10 = +9.42mV + * | | |11 = 0 (Default) + * |[31:30] |TXRESTUNE |USB 2.0 High-speed PHY USB Source Impedance Adjustment + * | | |00 = Source Impedance is increased by approximately 3.03 u03A9 + * | | |01 = 0 (Default) + * | | |10 = Source Impedance is increased by approximately 2.11 u03A9 + * | | |11 = Source Impedance is increased by approximately 4.51 u03A9 + * @var SYS_T::USBP1PCR + * Offset: 0x68 USB Port 1 PHY Control Register (TZNS) + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[2:0] |COMPDISTUNE|USB 2.0 High-speed Disconnect Threshold Adjustment + * | | |The SQRXTUNE adjusts the voltage level for the threshold used to detect a disconnect event at the host. + * | | |000 = -5.48%. + * | | |001 = 0. (Default) + * | | |010 = +6.04%. + * | | |011 = +12.75%. + * | | |100 = +19.66%. + * | | |101 = +28.24%. + * | | |110 = +38.31%. + * | | |111 = +50.28%. + * |[3] |EQBYPASSENB|USB 2.0 High-speed PHY Squelch Equalizer Bypass Control Bit + * | | |0 = Equalizer is Enabled. + * | | |1 = Equalizer is bypassed and acts as a simple differential input amplifier. + * |[6:4] |SQRXTUNE |USB 2.0 High-speed PHY Squelch Threshold Adjustment + * | | |The SQRXTUNE adjusts the voltage level for the threshold used to detect valid high-speed data. + * | | |000 = +15.5%. + * | | |001 = +10.87%. + * | | |010 = +5.86%. + * | | |011 = 0 (Default). + * | | |100 = -5.86%. + * | | |101 = -13.33%. + * | | |110 = -21.56%. + * | | |111 = -31.54%. + * |[7] |TXPREEMPPULSETUNE|USB 2.0 High-speed PHY Squelch Equalizer Bypass Control Bit + * | | |0 = Equalizer is Enabled. + * | | |1 = Equalizer is bypassed and acts as a simple differential input amplifier. + * |[11:8] |PLLPTUNE |USB 2.0 High-speed PHY PLL Proportional Path Tune + * | | |The value of PLLPTUNE should be keep in default. + * | | |0000 = 4.0x. + * | | |0001 = 4.5x. + * | | |0010 = 5.0x. + * | | |0011 = 5.5x. + * | | |0100 = 6.0x. + * | | |0101 = 6.5x. + * | | |0110 = 7.0x. + * | | |0111 = 7.5x. + * | | |1000 = 8.0x. + * | | |1001 = 8.5x. + * | | |1010 = 9.0x. + * | | |1011 = 9.5x. + * | | |1100 = 10.0x (Default). + * | | |1101 = 10.5x. + * | | |1110 = 11.0x. + * | | |1111 = 11.5x. + * |[15:12] |TXFSLSTUNE|USB 2.0 High-speed PHY FS/LS Source Impedance Adjustment + * | | |The TXFSLSTUNE adjusts the low- and full-speed single-ended source impedance while driving high. + * | | |0000 = +14.2%. + * | | |0001 = +6.60% + * | | |0011 = 0 (Default). + * | | |0111 = -5.48% + * | | |1111 = -10.29% + * |[17:16] |PLLITUNE |USB 2.0 High-speed PHY Integral Path Tune + * | | |The value of PLLITUNE should be keep in default. + * | | |00 = 1.0x (Default). + * | | |01 = 2.0x + * | | |10 = 3.0x + * | | |11 = 4.0x + * |[21:20] |TXPREEMPAMPTUNE|USB 2.0 High-speed PHY HS Transmitter Pre-Emphasis Current Control + * | | |00 = HS Transmitter pre-emphasis is disabled. (Default) + * | | |01 = HS Transmitter pre-emphasis circuit sources 1x pre-emphasis current. + * | | |10 = HS Transmitter pre-emphasis circuit sources 2x pre-emphasis current. + * | | |11 = HS Transmitter pre-emphasis circuit sources 3x pre-emphasis current. + * |[23:22] |TXRISETUNE|USB 2.0 High-speed PHY HS Transmitter Rise/Fall Time Adjustment + * | | |The TXRISETUNE adjusts the rise/fall times of the high-speed waveform. + * | | |00 = +7.34%. + * | | |01 = 0 (Default) + * | | |10 = -5.98%. + * | | |11 = -7.49% + * |[27:24] |TXVREFTUNE|USB 2.0 High-speed PHY HS DC Voltage Level Adjustment + * | | |The TXVREFTUNE adjusts the high-speed DC level voltage. + * | | |0000 = -9.37%. + * | | |0001 = -6.24%. + * | | |0010 = -3.12%. + * | | |0011 = 0 (Default) + * | | |0100 = +2.75%. + * | | |0101 = +5.87%. + * | | |0110 = +8.99%. + * | | |0111 = +12.11%. + * | | |1000 = +14.71%. + * | | |1001 = +17.82%. + * | | |1010 = +20.94%. + * | | |1011 = +24.06%. + * | | |1100 = +26.81%. + * | | |1101 = +29.94%. + * | | |1110 = +33.06%. + * | | |1111 = +36.18%. + * |[29:28] |TXHSXVTUNE|USB 2.0 High-speed PHY Transmitter High-Speed Crossover Adjustment + * | | |The TXHSXVTUNE adjusts the voltage at which the DP and DM signals cross while transmitting in HS mode. + * | | |00 = Reserved + * | | |01 = -9.16mV + * | | |10 = +9.42mV + * | | |11 = 0 (Default) + * |[31:30] |TXRESTUNE |USB 2.0 High-speed PHY USB Source Impedance Adjustment + * | | |00 = Source Impedance is increased by approximately 3.03 u03A9 + * | | |01 = 0 (Default) + * | | |10 = Source Impedance is increased by approximately 2.11 u03A9 + * | | |11 = Source Impedance is increased by approximately 4.51 u03A9 + * @var SYS_T::MISCFCR0 + * Offset: 0x70 Miscellaneous Function Control Register 0 (Shared) + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[0] |RTPICACHEN|Real-time Cortex-M4 Processor Instruction Cache Enable Bit (SUBM) + * | | |0 = Real-Time Cortex-M4 processor instruction cache Disabled. + * | | |1 = Real-Time Cortex-M4 processor instruction cache Enabled. + * |[1] |RTPDCACHEN|Real-time Cortex-M4 Processor Data Cache Enable Bit (SUBM) + * | | |0 = Real-Time Cortex-M4 processor data cache Disabled. + * | | |1 = Real-Time Cortex-M4 processor data cache Enabled. + * |[8] |WDT0RSTEN |WatchDog Timer 0 Reset Connection Enable Bit + * | | |This bit is use to enable the function that connect watch-dog timer 0 reset to nRESET pin + * | | |If this bit is enabled, the watch-dog timer 0 reset is connected to nRESET pin internally + * | | |0 = Watch-dog timer 0 reset not connected to nRESET pin internally. + * | | |1 = Watch-dog timer 0 reset connected to nRESET pin internally. + * |[9] |HDSPUEN |HDS Pin Internal Pull-up Enable Bit (TZNS) + * | | |0 = HDS pin internal pull-up resister Disabled. + * | | |1 = HDS pin internal pull-up resister Enabled. + * |[12] |UHOVRCURH |USB Host Overcurrent Detection High Active (TZNS) + * | | |0 = USB host overcurrent detection signal is low active. + * | | |1 = USB host overcurrent detection signal is high active. + * |[13] |SELFTEST |Self-test Mode Enable Bit + * | | |0 = Self-Test mode Disabled. + * | | |1 = Self-Test mode Enabled. + * |[14] |WDT1RSTEN |WatchDog Timer 1 Reset Connection Enable Bit (TZNS) + * | | |This bit is use to enable the function that connect watch-dog timer 1 reset to nRESET pin + * | | |If this bit is enabled, the watch-dog timer 1 reset is connected to nRESET pin internally + * | | |0 = Watch-dog timer 1 reset not connected to nRESET pin internally. + * | | |1 = Watch-dog timer 1 reset connected to nRESET pin internally. + * |[15] |WDT2RSTEN |WatchDog Timer 2 Reset Connection Enable Bit (SUBM) + * | | |This bit is use to enable the function that connect watch-dog timer 2 reset to nRESET pin + * | | |If this bit is enabled, the watch-dog timer 2 reset is connected to nRESET pin internally + * | | |0 = Watch-dog timer 2 reset not connected to nRESET pin internally. + * | | |1 = Watch-dog timer 2 reset connected to nRESET pin internally. + * |[16] |SDH0VSTB |Voltage Stable Indicator to SDH 0 (TZNS) + * | | |Set this bit high to indicate SDH 0 that I/O voltage is stable. + * | | |0 = Voltage of I/O used as SDH 0 is not stable. + * | | |1 = Voltage of I/O used as SDH 0 is stable. + * |[17] |SDH1VSTB |Voltage Stable Indicator to SDH 1 (TZNS) + * | | |Set this bit high to indicate SDH 1 that I/O voltage is stable. + * | | |0 = Voltage of I/O used as SDH 1 is not stable. + * | | |1 = Voltage of I/O used as SDH 1 is stable. + * |[18] |VBUSWKEN |HSUSBD VBUS Detect Wakeup Enable Control Bit (TZNS) + * | | |0 = HSUSBD VBUS detect wakeup system from Power-down mode Disabled. + * | | |1 = HSUSBD VBUS detect wakeup system from Power-down mode Enabled. + * |[19] |LNSTWKEN |HSUSBD Line State Wakeup Enable Control Bit (TZNS) + * | | |0 = HSUSBD line state wakeup system from Power-down mode Disabled. + * | | |1 = HSUSBD line state wakeup system from Power-down mode Enabled. + * |[23] |DDRCGDIS |DDR Controller Core Clock Gating Disable Bit + * | | |0 = DDR controller core clock gating in auto self-refresh mode Enabled. + * | | |1 = DDR controller core clock gating in auto self-refresh mode Disabled. + * | | |Note: This register needs to be set to 1'b1 to bypass clock gating function of DDR core clock before user writes/reads control registers or status registers of DDR memory controller. + * | | |Therefore the signals in PCLK domain of DDR memory controller can be synchronous to core clock domain of DDR memory controller, and the signals in core clock domain of DDR memory controller can be synchronous to PCLK domain of DDR memory controller correctly. + * | | |After user writes/reads control registers or status registers of DDR memory controller, this register can be set to 1'b0 to enable clock gating function of DDR core clock. + * |[31:24] |DRATSRDLY |DDR Auto Self Refresh Delay Count + * | | |This register uses to set the delay cycles of DDR memory controller before the core clock of DDR memory controller is gating + * | | |It allows for the self-refresh status to propagate to the APB domain so the STAT.selfref_type register field also reflects the status. + * | | |It is sufficient to set this delay cycles to 31 cycles normally + * | | |In particular, if the AXI frequency is much less than the DDRC frequency, a higher value may be required in order to ensure that all read data is synchronized to the AXI domain before the clock is removed. + * | | |Note: User can set this register value during core reset of DDR memory controller is asserted (i.e + * | | |MCTLCRST (SYS_IPRST0[29]) set to 1'b1). + * @var SYS_T::MISCFCR1 + * Offset: 0x74 Miscellaneous Function Control Register 1 (Shared) + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[0] |CANFD0PDEN|CAN FD 0 Power Down Enable Bit + * | | |0 = CAN FD 0 Power-down mode Disabled. + * | | |1 = CAN FD 0 Power-down mode Enabled. + * |[1] |CANFD1PDEN|CAN FD 1 Power Down Enable Bit + * | | |0 = CAN FD 1 Power-down mode Disabled. + * | | |1 = CAN FD 1 Power-down mode Enabled. + * |[2] |CANFD2PDEN|CAN FD 2 Power Down Enable Bit + * | | |0 = CAN FD 2 Power-down mode Disabled. + * | | |1 = CAN FD 2 Power-down mode Enabled. + * |[3] |CANFD3PDEN|CAN FD 3 Power Down Enable Bit + * | | |0 = CAN FD 3 Power-down mode Disabled. + * | | |1 = CAN FD 3 Power-down mode Enabled. + * |[4] |CANFD0CKSTP|CAN FD 0 Clock Stop Acknowledgement (Read Only) + * | | |0 = CAN FD 0 clock didn't stop. + * | | |1 = CAN FD 0 clock stop. + * |[5] |CANFD1CKSTP|CAN FD 1 Clock Stop Acknowledgement (Read Only) + * | | |0 = CAN FD 1 clock didn't stop. + * | | |1 = CAN FD 1 clock stop. + * |[6] |CANFD2CKSTP|CAN FD 2 Clock Stop Acknowledgement (Read Only) + * | | |0 = CAN FD 2 clock didn't stop. + * | | |1 = CAN FD 2 clock stop. + * |[7] |CANFD3CKSTP|CAN FD 3 Clock Stop Acknowledgement (Read Only) + * | | |0 = CAN FD 3 clock didn't stop. + * | | |1 = CAN FD 3 clock stop. + * |[9:8] |HXTDS |HXT Driving Current Selection (Write Protect) + * | | |00 = Low power consumption mode for 2.5V~3.3V operating voltage. + * | | |01 = High noise immunity mode for 2.5V~3.3V operating voltage. + * | | |10 = Low power consumption mode for 1.8V~2.5V operating voltage. + * | | |11 = High noise immunity mode for 1.8V~2.5V operating voltage. + * | | |Note: This bit is write protected + * | | |Refer to the SYS_RLKTZS, SYS_RLKTZNS or SYS_RLKSUBM register according to security attribute of each circuit. + * |[15:12] |TSENSRTRIM|Temperature Sensor VTRIM (Write Protect) + * | | |Trimming for temperature sensor calibration. + * | | |Note: This bit is write protected + * | | |Refer to the SYS_RLKTZS, SYS_RLKTZNS or SYS_RLKSUBM register according to security attribute of each circuit. + * |[16] |RMEL1RAM |Cortex-A35 L1 Cache SRAM Macro RME Control Bit (Write Protect) + * | | |0 = Default read-write margin of Cortex-A35 L1 cache SRAM selected. + * | | |1 = High speed read-write margin of Cortex-A35 L1 cache SRAM selected. + * | | |Note: This bit is write protected + * | | |Refer to the SYS_RLKTZS, SYS_RLKTZNS or SYS_RLKSUBM register according to security attribute of each circuit. + * |[17] |RMESYSRAM |System SRAM Macro RME Control Bit (Write Protect) + * | | |0 = Default read-write margin of system SRAM selected. + * | | |1 = High speed read-write margin of system SRAM selected. + * | | |Note: This bit is write protected + * | | |Refer to the SYS_RLKTZS, SYS_RLKTZNS or SYS_RLKSUBM register according to security attribute of each circuit. + * @var SYS_T::MISCIER + * Offset: 0x78 Miscellaneous Interrupt Enable Register (TZNS) + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[0] |LVDIEN |Low Voltage Detect Interrupt Enable Bit + * | | |0 = Low voltage detect interrupt Disabled. + * | | |1 = Low voltage detect interrupt Enabled. + * |[1] |USB0IDCHGIEN|USB0_ID Pin Status Change Interrupt Enable Bit + * | | |0 = USB0_ID pin status change interrupt Disabled. + * | | |1 = USB0_ID pin status change interrupt Enabled. + * |[2] |VBUSCHGIEN|USUSB0_VBUSVLD Pin Status Change Interrupt Enable Bit + * | | |0 = USUSB0_VBUSVLD pin status change interrupt Disabled. + * | | |1 = USUSB0_VBUSVLD pin status change interrupt Enabled. + * @var SYS_T::MISCISR + * Offset: 0x7C Miscellaneous Interrupt Status Register (TZNS) + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[0] |LVDIF |Low Voltage Detect Interrupt Flag + * | | |0 = No low voltage event. + * | | |1 = Low voltage event detected. + * |[1] |USB0IDCHGIF|USB0_ID Pin State Change Interrupt Flag + * | | |0 = USB0_ID state didn't change. + * | | |1 = USB0_ID state changed from low to high or from high to low. + * |[2] |VBUSCHGIF |USUSB0_VBUSVLD Pin State Change Interrupt Flag + * | | |0 = USUSB0_VBUSVLD pin state didn't change. + * | | |1 = USUSB0_VBUSVLD pin state changed from low to high or from high to low. + * |[16] |LVDSTS |Low Voltage Detect State + * | | |0 = Low voltage detect state is low. + * | | |1 = Low voltage detect state is high. + * |[17] |USB0IDSTS |USB0_ID Pin State + * | | |0 = USB port 0 used as a USB device port. + * | | |1 = USB port 0 used as a USB host port. + * |[18] |VBUSSTS |VBUS Detect Pin State + * | | |0 = VBUS detect pin state is low. + * | | |1 = VBUS detect pin state is high. + * @var SYS_T::GPA_MFPL + * Offset: 0x80 GPIOA Low Byte Multiple Function Control Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[3:0] |PA0MFP |PA.0 Multi-function Pin Selection + * |[7:4] |PA1MFP |PA.1 Multi-function Pin Selection + * |[11:8] |PA2MFP |PA.2 Multi-function Pin Selection + * |[15:12] |PA3MFP |PA.3 Multi-function Pin Selection + * |[19:16] |PA4MFP |PA.4 Multi-function Pin Selection + * |[23:20] |PA5MFP |PA.5 Multi-function Pin Selection + * |[27:24] |PA6MFP |PA.6 Multi-function Pin Selection + * |[31:28] |PA7MFP |PA.7 Multi-function Pin Selection + * @var SYS_T::GPA_MFPH + * Offset: 0x84 GPIOA High Byte Multiple Function Control Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[3:0] |PA8MFP |PA.8 Multi-function Pin Selection + * |[7:4] |PA9MFP |PA.9 Multi-function Pin Selection + * |[11:8] |PA10MFP |PA.10 Multi-function Pin Selection + * |[15:12] |PA11MFP |PA.11 Multi-function Pin Selection + * |[19:16] |PA12MFP |PA.12 Multi-function Pin Selection + * |[23:20] |PA13MFP |PA.13 Multi-function Pin Selection + * |[27:24] |PA14MFP |PA.14 Multi-function Pin Selection + * |[31:28] |PA15MFP |PA.15 Multi-function Pin Selection + * @var SYS_T::GPB_MFPL + * Offset: 0x88 GPIOB Low Byte Multiple Function Control Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[3:0] |PB0MFP |PB.0 Multi-function Pin Selection + * |[7:4] |PB1MFP |PB.1 Multi-function Pin Selection + * |[11:8] |PB2MFP |PB.2 Multi-function Pin Selection + * |[15:12] |PB3MFP |PB.3 Multi-function Pin Selection + * |[19:16] |PB4MFP |PB.4 Multi-function Pin Selection + * |[23:20] |PB5MFP |PB.5 Multi-function Pin Selection + * |[27:24] |PB6MFP |PB.6 Multi-function Pin Selection + * |[31:28] |PB7MFP |PB.7 Multi-function Pin Selection + * @var SYS_T::GPB_MFPH + * Offset: 0x8C GPIOB High Byte Multiple Function Control Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[3:0] |PB8MFP |PB.8 Multi-function Pin Selection + * |[7:4] |PB9MFP |PB.9 Multi-function Pin Selection + * |[11:8] |PB10MFP |PB.10 Multi-function Pin Selection + * |[15:12] |PB11MFP |PB.11 Multi-function Pin Selection + * |[19:16] |PB12MFP |PB.12 Multi-function Pin Selection + * |[23:20] |PB13MFP |PB.13 Multi-function Pin Selection + * |[27:24] |PB14MFP |PB.14 Multi-function Pin Selection + * |[31:28] |PB15MFP |PB.15 Multi-function Pin Selection + * @var SYS_T::GPC_MFPL + * Offset: 0x90 GPIOC Low Byte Multiple Function Control Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[3:0] |PC0MFP |PC.0 Multi-function Pin Selection + * |[7:4] |PC1MFP |PC.1 Multi-function Pin Selection + * |[11:8] |PC2MFP |PC.2 Multi-function Pin Selection + * |[15:12] |PC3MFP |PC.3 Multi-function Pin Selection + * |[19:16] |PC4MFP |PC.4 Multi-function Pin Selection + * |[23:20] |PC5MFP |PC.5 Multi-function Pin Selection + * |[27:24] |PC6MFP |PC.6 Multi-function Pin Selection + * |[31:28] |PC7MFP |PC.7 Multi-function Pin Selection + * @var SYS_T::GPC_MFPH + * Offset: 0x94 GPIOC High Byte Multiple Function Control Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[3:0] |PC8MFP |PC.8 Multi-function Pin Selection + * |[7:4] |PC9MFP |PC.9 Multi-function Pin Selection + * |[11:8] |PC10MFP |PC.10 Multi-function Pin Selection + * |[15:12] |PC11MFP |PC.11 Multi-function Pin Selection + * |[19:16] |PC12MFP |PC.12 Multi-function Pin Selection + * |[23:20] |PC13MFP |PC.13 Multi-function Pin Selection + * |[27:24] |PC14MFP |PC.14 Multi-function Pin Selection + * |[31:28] |PC15MFP |PC.15 Multi-function Pin Selection + * @var SYS_T::GPD_MFPL + * Offset: 0x98 GPIOD Low Byte Multiple Function Control Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[3:0] |PD0MFP |PD.0 Multi-function Pin Selection + * |[7:4] |PD1MFP |PD.1 Multi-function Pin Selection + * |[11:8] |PD2MFP |PD.2 Multi-function Pin Selection + * |[15:12] |PD3MFP |PD.3 Multi-function Pin Selection + * |[19:16] |PD4MFP |PD.4 Multi-function Pin Selection + * |[23:20] |PD5MFP |PD.5 Multi-function Pin Selection + * |[27:24] |PD6MFP |PD.6 Multi-function Pin Selection + * |[31:28] |PD7MFP |PD.7 Multi-function Pin Selection + * @var SYS_T::GPD_MFPH + * Offset: 0x9C GPIOD High Byte Multiple Function Control Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[3:0] |PD8MFP |PD.8 Multi-function Pin Selection + * |[7:4] |PD9MFP |PD.9 Multi-function Pin Selection + * |[11:8] |PD10MFP |PD.10 Multi-function Pin Selection + * |[15:12] |PD11MFP |PD.11 Multi-function Pin Selection + * |[19:16] |PD12MFP |PD.12 Multi-function Pin Selection + * |[23:20] |PD13MFP |PD.13 Multi-function Pin Selection + * |[27:24] |PD14MFP |PD.14 Multi-function Pin Selection + * |[31:28] |PD15MFP |PD.15 Multi-function Pin Selection + * @var SYS_T::GPE_MFPL + * Offset: 0xA0 GPIOE Low Byte Multiple Function Control Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[3:0] |PE0MFP |PE.0 Multi-function Pin Selection + * |[7:4] |PE1MFP |PE.1 Multi-function Pin Selection + * |[11:8] |PE2MFP |PE.2 Multi-function Pin Selection + * |[15:12] |PE3MFP |PE.3 Multi-function Pin Selection + * |[19:16] |PE4MFP |PE.4 Multi-function Pin Selection + * |[23:20] |PE5MFP |PE.5 Multi-function Pin Selection + * |[27:24] |PE6MFP |PE.6 Multi-function Pin Selection + * |[31:28] |PE7MFP |PE.7 Multi-function Pin Selection + * @var SYS_T::GPE_MFPH + * Offset: 0xA4 GPIOE High Byte Multiple Function Control Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[3:0] |PE8MFP |PE.8 Multi-function Pin Selection + * |[7:4] |PE9MFP |PE.9 Multi-function Pin Selection + * |[11:8] |PE10MFP |PE.10 Multi-function Pin Selection + * |[15:12] |PE11MFP |PE.11 Multi-function Pin Selection + * |[19:16] |PE12MFP |PE.12 Multi-function Pin Selection + * |[23:20] |PE13MFP |PE.13 Multi-function Pin Selection + * |[27:24] |PE14MFP |PE.14 Multi-function Pin Selection + * |[31:28] |PE15MFP |PE.15 Multi-function Pin Selection + * @var SYS_T::GPF_MFPL + * Offset: 0xA8 GPIOF Low Byte Multiple Function Control Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[3:0] |PF0MFP |PF.0 Multi-function Pin Selection + * |[7:4] |PF1MFP |PF.1 Multi-function Pin Selection + * |[11:8] |PF2MFP |PF.2 Multi-function Pin Selection + * |[15:12] |PF3MFP |PF.3 Multi-function Pin Selection + * |[19:16] |PF4MFP |PF.4 Multi-function Pin Selection + * |[23:20] |PF5MFP |PF.5 Multi-function Pin Selection + * |[27:24] |PF6MFP |PF.6 Multi-function Pin Selection + * |[31:28] |PF7MFP |PF.7 Multi-function Pin Selection + * @var SYS_T::GPF_MFPH + * Offset: 0xAC GPIOF High Byte Multiple Function Control Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[3:0] |PF8MFP |PF.8 Multi-function Pin Selection + * |[7:4] |PF9MFP |PF.9 Multi-function Pin Selection + * |[11:8] |PF10MFP |PF.10 Multi-function Pin Selection + * |[15:12] |PF11MFP |PF.11 Multi-function Pin Selection + * |[19:16] |PF12MFP |PF.12 Multi-function Pin Selection + * |[23:20] |PF13MFP |PF.13 Multi-function Pin Selection + * |[27:24] |PF14MFP |PF.14 Multi-function Pin Selection + * |[31:28] |PF15MFP |PF.15 Multi-function Pin Selection + * @var SYS_T::GPG_MFPL + * Offset: 0xB0 GPIOG Low Byte Multiple Function Control Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[3:0] |PG0MFP |PG.0 Multi-function Pin Selection + * |[7:4] |PG1MFP |PG.1 Multi-function Pin Selection + * |[11:8] |PG2MFP |PG.2 Multi-function Pin Selection + * |[15:12] |PG3MFP |PG.3 Multi-function Pin Selection + * |[19:16] |PG4MFP |PG.4 Multi-function Pin Selection + * |[23:20] |PG5MFP |PG.5 Multi-function Pin Selection + * |[27:24] |PG6MFP |PG.6 Multi-function Pin Selection + * |[31:28] |PG7MFP |PG.7 Multi-function Pin Selection + * @var SYS_T::GPG_MFPH + * Offset: 0xB4 GPIOG High Byte Multiple Function Control Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[3:0] |PG8MFP |PG.8 Multi-function Pin Selection + * |[7:4] |PG9MFP |PG.9 Multi-function Pin Selection + * |[11:8] |PG10MFP |PG.10 Multi-function Pin Selection + * |[15:12] |PG11MFP |PG.11 Multi-function Pin Selection + * |[19:16] |PG12MFP |PG.12 Multi-function Pin Selection + * |[23:20] |PG13MFP |PG.13 Multi-function Pin Selection + * |[27:24] |PG14MFP |PG.14 Multi-function Pin Selection + * |[31:28] |PG15MFP |PG.15 Multi-function Pin Selection + * @var SYS_T::GPH_MFPL + * Offset: 0xB8 GPIOH Low Byte Multiple Function Control Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[3:0] |PH0MFP |PH.0 Multi-function Pin Selection + * |[7:4] |PH1MFP |PH.1 Multi-function Pin Selection + * |[11:8] |PH2MFP |PH.2 Multi-function Pin Selection + * |[15:12] |PH3MFP |PH.3 Multi-function Pin Selection + * |[19:16] |PH4MFP |PH.4 Multi-function Pin Selection + * |[23:20] |PH5MFP |PH.5 Multi-function Pin Selection + * |[27:24] |PH6MFP |PH.6 Multi-function Pin Selection + * |[31:28] |PH7MFP |PH.7 Multi-function Pin Selection + * @var SYS_T::GPH_MFPH + * Offset: 0xBC GPIOH High Byte Multiple Function Control Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[3:0] |PH8MFP |PH.8 Multi-function Pin Selection + * |[7:4] |PH9MFP |PH.9 Multi-function Pin Selection + * |[11:8] |PH10MFP |PH.10 Multi-function Pin Selection + * |[15:12] |PH11MFP |PH.11 Multi-function Pin Selection + * |[19:16] |PH12MFP |PH.12 Multi-function Pin Selection + * |[23:20] |PH13MFP |PH.13 Multi-function Pin Selection + * |[27:24] |PH14MFP |PH.14 Multi-function Pin Selection + * |[31:28] |PH15MFP |PH.15 Multi-function Pin Selection + * @var SYS_T::GPI_MFPL + * Offset: 0xC0 GPIOI Low Byte Multiple Function Control Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[3:0] |PI0MFP |PI.0 Multi-function Pin Selection + * |[7:4] |PI1MFP |PI.1 Multi-function Pin Selection + * |[11:8] |PI2MFP |PI.2 Multi-function Pin Selection + * |[15:12] |PI3MFP |PI.3 Multi-function Pin Selection + * |[19:16] |PI4MFP |PI.4 Multi-function Pin Selection + * |[23:20] |PI5MFP |PI.5 Multi-function Pin Selection + * |[27:24] |PI6MFP |PI.6 Multi-function Pin Selection + * |[31:28] |PI7MFP |PI.7 Multi-function Pin Selection + * @var SYS_T::GPI_MFPH + * Offset: 0xC4 GPIOI High Byte Multiple Function Control Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[3:0] |PI8MFP |PI.8 Multi-function Pin Selection + * |[7:4] |PI9MFP |PI.9 Multi-function Pin Selection + * |[11:8] |PI10MFP |PI.10 Multi-function Pin Selection + * |[15:12] |PI11MFP |PI.11 Multi-function Pin Selection + * |[19:16] |PI12MFP |PI.12 Multi-function Pin Selection + * |[23:20] |PI13MFP |PI.13 Multi-function Pin Selection + * |[27:24] |PI14MFP |PI.14 Multi-function Pin Selection + * |[31:28] |PI15MFP |PI.15 Multi-function Pin Selection + * @var SYS_T::GPJ_MFPL + * Offset: 0xC8 GPIOJ Low Byte Multiple Function Control Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[3:0] |PJ0MFP |PJ.0 Multi-function Pin Selection + * |[7:4] |PJ1MFP |PJ.1 Multi-function Pin Selection + * |[11:8] |PJ2MFP |PJ.2 Multi-function Pin Selection + * |[15:12] |PJ3MFP |PJ.3 Multi-function Pin Selection + * |[19:16] |PJ4MFP |PJ.4 Multi-function Pin Selection + * |[23:20] |PJ5MFP |PJ.5 Multi-function Pin Selection + * |[27:24] |PJ6MFP |PJ.6 Multi-function Pin Selection + * |[31:28] |PJ7MFP |PJ.7 Multi-function Pin Selection + * @var SYS_T::GPJ_MFPH + * Offset: 0xCC GPIOJ High Byte Multiple Function Control Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[3:0] |PJ8MFP |PJ.8 Multi-function Pin Selection + * |[7:4] |PJ9MFP |PJ.9 Multi-function Pin Selection + * |[11:8] |PJ10MFP |PJ.10 Multi-function Pin Selection + * |[15:12] |PJ11MFP |PJ.11 Multi-function Pin Selection + * |[19:16] |PJ12MFP |PJ.12 Multi-function Pin Selection + * |[23:20] |PJ13MFP |PJ.13 Multi-function Pin Selection + * |[27:24] |PJ14MFP |PJ.14 Multi-function Pin Selection + * |[31:28] |PJ15MFP |PJ.15 Multi-function Pin Selection + * @var SYS_T::GPK_MFPL + * Offset: 0xD0 GPIOK Low Byte Multiple Function Control Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[3:0] |PK0MFP |PK.0 Multi-function Pin Selection + * |[7:4] |PK1MFP |PK.1 Multi-function Pin Selection + * |[11:8] |PK2MFP |PK.2 Multi-function Pin Selection + * |[15:12] |PK3MFP |PK.3 Multi-function Pin Selection + * |[19:16] |PK4MFP |PK.4 Multi-function Pin Selection + * |[23:20] |PK5MFP |PK.5 Multi-function Pin Selection + * |[27:24] |PK6MFP |PK.6 Multi-function Pin Selection + * |[31:28] |PK7MFP |PK.7 Multi-function Pin Selection + * @var SYS_T::GPK_MFPH + * Offset: 0xD4 GPIOK High Byte Multiple Function Control Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[3:0] |PK8MFP |PK.8 Multi-function Pin Selection + * |[7:4] |PK9MFP |PK.9 Multi-function Pin Selection + * |[11:8] |PK10MFP |PK.10 Multi-function Pin Selection + * |[15:12] |PK11MFP |PK.11 Multi-function Pin Selection + * |[19:16] |PK12MFP |PK.12 Multi-function Pin Selection + * |[23:20] |PK13MFP |PK.13 Multi-function Pin Selection + * |[27:24] |PK14MFP |PK.14 Multi-function Pin Selection + * |[31:28] |PK15MFP |PK.15 Multi-function Pin Selection + * @var SYS_T::GPL_MFPL + * Offset: 0xD8 GPIOL Low Byte Multiple Function Control Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[3:0] |PL0MFP |PL.0 Multi-function Pin Selection + * |[7:4] |PL1MFP |PL.1 Multi-function Pin Selection + * |[11:8] |PL2MFP |PL.2 Multi-function Pin Selection + * |[15:12] |PL3MFP |PL.3 Multi-function Pin Selection + * |[19:16] |PL4MFP |PL.4 Multi-function Pin Selection + * |[23:20] |PL5MFP |PL.5 Multi-function Pin Selection + * |[27:24] |PL6MFP |PL.6 Multi-function Pin Selection + * |[31:28] |PL7MFP |PL.7 Multi-function Pin Selection + * @var SYS_T::GPL_MFPH + * Offset: 0xDC GPIOL High Byte Multiple Function Control Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[3:0] |PL8MFP |PL.8 Multi-function Pin Selection + * |[7:4] |PL9MFP |PL.9 Multi-function Pin Selection + * |[11:8] |PL10MFP |PL.10 Multi-function Pin Selection + * |[15:12] |PL11MFP |PL.11 Multi-function Pin Selection + * |[19:16] |PL12MFP |PL.12 Multi-function Pin Selection + * |[23:20] |PL13MFP |PL.13 Multi-function Pin Selection + * |[27:24] |PL14MFP |PL.14 Multi-function Pin Selection + * |[31:28] |PL15MFP |PL.15 Multi-function Pin Selection + * @var SYS_T::GPM_MFPL + * Offset: 0xE0 GPIOM Low Byte Multiple Function Control Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[3:0] |PM0MFP |PM.0 Multi-function Pin Selection + * |[7:4] |PM1MFP |PM.1 Multi-function Pin Selection + * |[11:8] |PM2MFP |PM.2 Multi-function Pin Selection + * |[15:12] |PM3MFP |PM.3 Multi-function Pin Selection + * |[19:16] |PM4MFP |PM.4 Multi-function Pin Selection + * |[23:20] |PM5MFP |PM.5 Multi-function Pin Selection + * |[27:24] |PM6MFP |PM.6 Multi-function Pin Selection + * |[31:28] |PM7MFP |PM.7 Multi-function Pin Selection + * @var SYS_T::GPM_MFPH + * Offset: 0xE4 GPIOM High Byte Multiple Function Control Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[3:0] |PM8MFP |PM.8 Multi-function Pin Selection + * |[7:4] |PM9MFP |PM.9 Multi-function Pin Selection + * |[11:8] |PM10MFP |PM.10 Multi-function Pin Selection + * |[15:12] |PM11MFP |PM.11 Multi-function Pin Selection + * |[19:16] |PM12MFP |PM.12 Multi-function Pin Selection + * |[23:20] |PM13MFP |PM.13 Multi-function Pin Selection + * |[27:24] |PM14MFP |PM.14 Multi-function Pin Selection + * |[31:28] |PM15MFP |PM.15 Multi-function Pin Selection + * @var SYS_T::GPN_MFPL + * Offset: 0xE8 GPION Low Byte Multiple Function Control Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[3:0] |PN0MFP |PN.0 Multi-function Pin Selection + * |[7:4] |PN1MFP |PN.1 Multi-function Pin Selection + * |[11:8] |PN2MFP |PN.2 Multi-function Pin Selection + * |[15:12] |PN3MFP |PN.3 Multi-function Pin Selection + * |[19:16] |PN4MFP |PN.4 Multi-function Pin Selection + * |[23:20] |PN5MFP |PN.5 Multi-function Pin Selection + * |[27:24] |PN6MFP |PN.6 Multi-function Pin Selection + * |[31:28] |PN7MFP |PN.7 Multi-function Pin Selection + * @var SYS_T::GPN_MFPH + * Offset: 0xEC GPION High Byte Multiple Function Control Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[3:0] |PN8MFP |PN.8 Multi-function Pin Selection + * |[7:4] |PN9MFP |PN.9 Multi-function Pin Selection + * |[11:8] |PN10MFP |PN.10 Multi-function Pin Selection + * |[15:12] |PN11MFP |PN.11 Multi-function Pin Selection + * |[19:16] |PN12MFP |PN.12 Multi-function Pin Selection + * |[23:20] |PN13MFP |PN.13 Multi-function Pin Selection + * |[27:24] |PN14MFP |PN.14 Multi-function Pin Selection + * |[31:28] |PN15MFP |PN.15 Multi-function Pin Selection + * @var SYS_T::TSENSRFCR + * Offset: 0x104 Temperature Sensor Function Control Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[7:0] |TSENSRREF0|Temperature Sensor Reference Value 0 + * | | |TSENSRREF0 keeps 8-bit value measured at 25C for temperature conversion formula variable A calibration. + * |[15:8] |TSENSRREF1|Temperature Sensor Reference Value 1 + * | | |TSENSRREF1 keeps 8-bit value measured at 25C for temperature conversion formula variable B calibration. + * |[27:16] |TSENSRDATA|Temperature Sensor Data + * | | |TSENSRDATA keeps 12-bit value measured by temperature sensor. + * |[28] |PD |Temperature Sensor Power Down + * | | |0 = Temperature sensor data is in normal operation. + * | | |1 = Temperature sensor data is in power down. + * |[29] |REFUDEN |Temperature Sensor Reference Data Update Enable Bit + * | | |0 = Write to update TSENSRREF0 and TSENSRREF1 is Disabled. + * | | |1 = Write to update TSENSRREF0 and TSENSRREF1 is Enabled. + * |[31] |DATAVALID |Temperature Sensor Data Valid + * | | |0 = Temperature sensor data in TSENSRDATA is not valid. + * | | |1 = Temperature sensor data in TSENSRDATA is valid. + * | | |Note: This bit is only cleared by writing 1 to it. + * @var SYS_T::GMAC0MISCR + * Offset: 0x108 GMAC 0 Miscellaneous Control Register (TZNS) + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[0] |RMIIEN |RMII Mode Enable Bit + * | | |0 = GMAC 0 is in RGMII mode. + * | | |1 = GMAC 0 is in RMII mode. + * |[1] |PFRMTXEN |Pause Frame Transmit Enable Bit + * | | |0 = Pause frame transmit Disabled. + * | | |1 = Pause frame transmit Enabled. + * |[8] |TXCLKINV |Transmit Clock Inverter Enable Bit + * | | |0 = Transmit clock (output) inverter Disabled. + * | | |1 = Transmit clock (output) inverter Enabled. + * | | |Note: This bit is reserved when GMAC 0 is in RMII mode. + * |[9] |TXCLKGEN |Transmit Clock Gating Enable Bit + * | | |0 = Transmit clock (output) gating when entered LPI mode Disabled. + * | | |1 = Transmit clock (output) gating when entered LPI mode Enabled. + * | | |Note: This bit is reserved when GMAC 0 is in RMII mode. + * |[12] |RXCLKINV |Receive Clock Inverter Enable Bit + * | | |0 = Receive clock (input) inverter Disabled. + * | | |1 = Receive clock (input) inverter Enabled. + * | | |Note: This bit is reserved when GMAC 0 is in RMII mode. + * |[19:16] |TXCLKDLY |Transmit Clock Path Delay Control + * | | |0000 = 0.00ns (Default). + * | | |0001 = 0.13ns. + * | | |0010 = 0.27ns. + * | | |0011 = 0.40ns. + * | | |0100 = 0.53ns. + * | | |0101 = 0.67ns. + * | | |0110 = 0.80ns. + * | | |0111 = 0.93ns. + * | | |1000 = 1.07ns. + * | | |1001 = 1.20ns. + * | | |1010 = 1.33ns. + * | | |1011 = 1.47ns. + * | | |1100 = 1.60ns. + * | | |1101 = 1.73ns. + * | | |1110 = 1.87ns. + * | | |1111 = 2.00ns. + * | | |Note: These bits are reserved when GMAC 0 is in RMII mode. + * |[23:20] |RXCLKDLY |Receive Clock Path Delay Control + * | | |0000 = 0.00ns (Default). + * | | |0001 = 0.13ns. + * | | |0010 = 0.27ns. + * | | |0011 = 0.40ns. + * | | |0100 = 0.53ns. + * | | |0101 = 0.67ns. + * | | |0110 = 0.80ns. + * | | |0111 = 0.93ns. + * | | |1000 = 1.07ns. + * | | |1001 = 1.20ns. + * | | |1010 = 1.33ns. + * | | |1011 = 1.47ns. + * | | |1100 = 1.60ns. + * | | |1101 = 1.73ns. + * | | |1110 = 1.87ns. + * | | |1111 = 2.00ns. + * | | |Note: These bits are reserved when GMAC 0 is in RMII mode. + * @var SYS_T::GMAC1MISCR + * Offset: 0x10C GMAC 1 Miscellaneous Control Register (TZNS) + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[0] |RMIIEN |RMII Mode Enable Bit + * | | |0 = GMAC 1 is in RGMII mode. + * | | |1 = GMAC 1 is in RMII mode. + * |[1] |PFRMTXEN |Pause Frame Transmit Enable Bit + * | | |0 = Pause frame transmit Disabled. + * | | |1 = Pause frame transmit Enabled. + * |[8] |TXCLKINV |Transmit Clock Inverter Enable Bit + * | | |0 = Transmit clock (output) inverter Disabled. + * | | |1 = Transmit clock (output) inverter Enabled. + * | | |Note: This bit is reserved when GMAC 1 is in RMII mode. + * |[9] |TXCLKGEN |Transmit Clock Gating Enable Bit + * | | |0 = Transmit clock (output) gating when entered LPI mode Disabled. + * | | |1 = Transmit clock (output) gating when entered LPI mode Enabled. + * | | |Note: This bit is reserved when GMAC 1 is in RMII mode. + * |[12] |RXCLKINV |Receive Clock Inverter Enable Bit + * | | |0 = Receive clock (input) inverter Disabled. + * | | |1 = Receive clock (input) inverter Enabled. + * | | |Note: This bit is reserved when GMAC 1 is in RMII mode. + * |[19:16] |TXCLKDLY |Transmit Clock Path Delay Control + * | | |0000 = 0.00ns (Default). + * | | |0001 = 0.13ns. + * | | |0010 = 0.27ns. + * | | |0011 = 0.40ns. + * | | |0100 = 0.53ns. + * | | |0101 = 0.67ns. + * | | |0110 = 0.80ns. + * | | |0111 = 0.93ns. + * | | |1000 = 1.07ns. + * | | |1001 = 1.20ns. + * | | |1010 = 1.33ns. + * | | |1011 = 1.47ns. + * | | |1100 = 1.60ns. + * | | |1101 = 1.73ns. + * | | |1110 = 1.87ns. + * | | |1111 = 2.00ns. + * | | |Note: These bits are reserved when GMAC 1 is in RMII mode. + * |[23:20] |RXCLKDLY |Receive Clock Path Delay Control + * | | |0000 = 0.00ns (Default). + * | | |0001 = 0.13ns. + * | | |0010 = 0.27ns. + * | | |0011 = 0.40ns. + * | | |0100 = 0.53ns. + * | | |0101 = 0.67ns. + * | | |0110 = 0.80ns. + * | | |0111 = 0.93ns. + * | | |1000 = 1.07ns. + * | | |1001 = 1.20ns. + * | | |1010 = 1.33ns. + * | | |1011 = 1.47ns. + * | | |1100 = 1.60ns. + * | | |1101 = 1.73ns. + * | | |1110 = 1.87ns. + * | | |1111 = 2.00ns. + * | | |Note: These bits are reserved when GMAC 1 is in RMII mode. + * @var SYS_T::MACAD0LSR + * Offset: 0x110 MAC Address 0 Low Significant Word Register (TZNS) + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[31:0] |MACADRLSR |MAC Address Low Significant Word Register + * @var SYS_T::MACAD0HSR + * Offset: 0x114 MAC Address 0 High Significant Word Register (TZNS) + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[15:0] |MACADRHSR |MAC Address High Significant Word Register + * @var SYS_T::MACAD1LSR + * Offset: 0x118 MAC Address 1 Low Significant Word Register (TZNS) + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[31:0] |MACADRLSR |MAC Address Low Significant Word Register + * @var SYS_T::MACAD1HSR + * Offset: 0x11C MAC Address 1 High Significant Word Register (TZNS) + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[15:0] |MACADRHSR |MAC Address High Significant Word Register + * @var SYS_T::CSDBGCTL + * Offset: 0x120 CoreSight Debug Control Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[0] |DBGRST |Debug Reset Bit + * | | |0 = Release the reset for all debug component including A35, RTP and Coresight + * | | |1 = Reset all debug component including A35, RTP and Coresight + * |[1] |DBGPWRUPREQ|Debug Power Up Request Bit + * | | |0 = Disable the power-up request. + * | | |1 = Enable the power-up request + * | | |Note: If user wants to do self-hosted debug, it has to write the DBGPWRUPREQ to 1, and check the DBGPWRUPACK to 1 before self-hosted debug start + * | | |This bit will enable A35 power and clock and RTP clock. + * |[2] |DBGPWRUPACK|Debug Power Up Acknowledge Bit + * | | |0 = Debug power-up request is not ready + * | | |1 = Debug power-up request is ready + * |[3] |LPEMU |Low Power Emulation Enable Bit + * | | |0 = Low power Emulation Enabled. + * | | |1 = Low power Emulation Disabled. + * | | |When this bit is on, CA35 and RTP's clock and power will be maintained even the SOC in power-down mode. + * @var SYS_T::GPAB_MFOS + * Offset: 0x140 GPIOA and GPIOB Multiple Function Output Mode Select Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[0] |GPIOxMFOS0|GPIOx Pin[m] Multiple Function Pin Output Mode Select + * | | |This bit used to select multiple function pin output mode type for Px.m pin + * | | |0 = Multiple function pin output mode type is Push-pull mode. + * | | |1 = Multiple function pin output mode type is Open-drain mode. + * | | |Note: Max. m=15. + * | | |Note: y= A, C, E, F, I, K, M + * |[1] |GPIOxMFOS1|GPIOx Pin[m] Multiple Function Pin Output Mode Select + * | | |This bit used to select multiple function pin output mode type for Px.m pin + * | | |0 = Multiple function pin output mode type is Push-pull mode. + * | | |1 = Multiple function pin output mode type is Open-drain mode. + * | | |Note: Max. m=15. + * | | |Note: y= A, C, E, F, I, K, M + * |[2] |GPIOxMFOS2|GPIOx Pin[m] Multiple Function Pin Output Mode Select + * | | |This bit used to select multiple function pin output mode type for Px.m pin + * | | |0 = Multiple function pin output mode type is Push-pull mode. + * | | |1 = Multiple function pin output mode type is Open-drain mode. + * | | |Note: Max. m=15. + * | | |Note: y= A, C, E, F, I, K, M + * |[3] |GPIOxMFOS3|GPIOx Pin[m] Multiple Function Pin Output Mode Select + * | | |This bit used to select multiple function pin output mode type for Px.m pin + * | | |0 = Multiple function pin output mode type is Push-pull mode. + * | | |1 = Multiple function pin output mode type is Open-drain mode. + * | | |Note: Max. m=15. + * | | |Note: y= A, C, E, F, I, K, M + * |[4] |GPIOxMFOS4|GPIOx Pin[m] Multiple Function Pin Output Mode Select + * | | |This bit used to select multiple function pin output mode type for Px.m pin + * | | |0 = Multiple function pin output mode type is Push-pull mode. + * | | |1 = Multiple function pin output mode type is Open-drain mode. + * | | |Note: Max. m=15. + * | | |Note: y= A, C, E, F, I, K, M + * |[5] |GPIOxMFOS5|GPIOx Pin[m] Multiple Function Pin Output Mode Select + * | | |This bit used to select multiple function pin output mode type for Px.m pin + * | | |0 = Multiple function pin output mode type is Push-pull mode. + * | | |1 = Multiple function pin output mode type is Open-drain mode. + * | | |Note: Max. m=15. + * | | |Note: y= A, C, E, F, I, K, M + * |[6] |GPIOxMFOS6|GPIOx Pin[m] Multiple Function Pin Output Mode Select + * | | |This bit used to select multiple function pin output mode type for Px.m pin + * | | |0 = Multiple function pin output mode type is Push-pull mode. + * | | |1 = Multiple function pin output mode type is Open-drain mode. + * | | |Note: Max. m=15. + * | | |Note: y= A, C, E, F, I, K, M + * |[7] |GPIOxMFOS7|GPIOx Pin[m] Multiple Function Pin Output Mode Select + * | | |This bit used to select multiple function pin output mode type for Px.m pin + * | | |0 = Multiple function pin output mode type is Push-pull mode. + * | | |1 = Multiple function pin output mode type is Open-drain mode. + * | | |Note: Max. m=15. + * | | |Note: y= A, C, E, F, I, K, M + * |[8] |GPIOxMFOS8|GPIOx Pin[m] Multiple Function Pin Output Mode Select + * | | |This bit used to select multiple function pin output mode type for Px.m pin + * | | |0 = Multiple function pin output mode type is Push-pull mode. + * | | |1 = Multiple function pin output mode type is Open-drain mode. + * | | |Note: Max. m=15. + * | | |Note: y= A, C, E, F, I, K, M + * |[9] |GPIOxMFOS9|GPIOx Pin[m] Multiple Function Pin Output Mode Select + * | | |This bit used to select multiple function pin output mode type for Px.m pin + * | | |0 = Multiple function pin output mode type is Push-pull mode. + * | | |1 = Multiple function pin output mode type is Open-drain mode. + * | | |Note: Max. m=15. + * | | |Note: y= A, C, E, F, I, K, M + * |[10] |GPIOxMFOS10|GPIOx Pin[m] Multiple Function Pin Output Mode Select + * | | |This bit used to select multiple function pin output mode type for Px.m pin + * | | |0 = Multiple function pin output mode type is Push-pull mode. + * | | |1 = Multiple function pin output mode type is Open-drain mode. + * | | |Note: Max. m=15. + * | | |Note: y= A, C, E, F, I, K, M + * |[11] |GPIOxMFOS11|GPIOx Pin[m] Multiple Function Pin Output Mode Select + * | | |This bit used to select multiple function pin output mode type for Px.m pin + * | | |0 = Multiple function pin output mode type is Push-pull mode. + * | | |1 = Multiple function pin output mode type is Open-drain mode. + * | | |Note: Max. m=15. + * | | |Note: y= A, C, E, F, I, K, M + * |[12] |GPIOxMFOS12|GPIOx Pin[m] Multiple Function Pin Output Mode Select + * | | |This bit used to select multiple function pin output mode type for Px.m pin + * | | |0 = Multiple function pin output mode type is Push-pull mode. + * | | |1 = Multiple function pin output mode type is Open-drain mode. + * | | |Note: Max. m=15. + * | | |Note: y= A, C, E, F, I, K, M + * |[13] |GPIOxMFOS13|GPIOx Pin[m] Multiple Function Pin Output Mode Select + * | | |This bit used to select multiple function pin output mode type for Px.m pin + * | | |0 = Multiple function pin output mode type is Push-pull mode. + * | | |1 = Multiple function pin output mode type is Open-drain mode. + * | | |Note: Max. m=15. + * | | |Note: y= A, C, E, F, I, K, M + * |[14] |GPIOxMFOS14|GPIOx Pin[m] Multiple Function Pin Output Mode Select + * | | |This bit used to select multiple function pin output mode type for Px.m pin + * | | |0 = Multiple function pin output mode type is Push-pull mode. + * | | |1 = Multiple function pin output mode type is Open-drain mode. + * | | |Note: Max. m=15. + * | | |Note: y= A, C, E, F, I, K, M + * |[15] |GPIOxMFOS15|GPIOx Pin[m] Multiple Function Pin Output Mode Select + * | | |This bit used to select multiple function pin output mode type for Px.m pin + * | | |0 = Multiple function pin output mode type is Push-pull mode. + * | | |1 = Multiple function pin output mode type is Open-drain mode. + * | | |Note: Max. m=15. + * | | |Note: y= A, C, E, F, I, K, M + * |[16] |GPIOyMFOS16|GPIOy Pin[n] Multiple Function Pin Output Mode Select + * | | |This bit used to select multiple function pin output mode type for Py.n pin + * | | |0 = Multiple function pin output mode type is Push-pull mode. + * | | |1 = Multiple function pin output mode type is Open-drain mode. + * | | |Note: n=0, 1..15, Max. n=15. + * | | |Note: y= B, D, F, H, J, L, N + * |[17] |GPIOyMFOS17|GPIOy Pin[n] Multiple Function Pin Output Mode Select + * | | |This bit used to select multiple function pin output mode type for Py.n pin + * | | |0 = Multiple function pin output mode type is Push-pull mode. + * | | |1 = Multiple function pin output mode type is Open-drain mode. + * | | |Note: n=0, 1..15, Max. n=15. + * | | |Note: y= B, D, F, H, J, L, N + * |[18] |GPIOyMFOS18|GPIOy Pin[n] Multiple Function Pin Output Mode Select + * | | |This bit used to select multiple function pin output mode type for Py.n pin + * | | |0 = Multiple function pin output mode type is Push-pull mode. + * | | |1 = Multiple function pin output mode type is Open-drain mode. + * | | |Note: n=0, 1..15, Max. n=15. + * | | |Note: y= B, D, F, H, J, L, N + * |[19] |GPIOyMFOS19|GPIOy Pin[n] Multiple Function Pin Output Mode Select + * | | |This bit used to select multiple function pin output mode type for Py.n pin + * | | |0 = Multiple function pin output mode type is Push-pull mode. + * | | |1 = Multiple function pin output mode type is Open-drain mode. + * | | |Note: n=0, 1..15, Max. n=15. + * | | |Note: y= B, D, F, H, J, L, N + * |[20] |GPIOyMFOS20|GPIOy Pin[n] Multiple Function Pin Output Mode Select + * | | |This bit used to select multiple function pin output mode type for Py.n pin + * | | |0 = Multiple function pin output mode type is Push-pull mode. + * | | |1 = Multiple function pin output mode type is Open-drain mode. + * | | |Note: n=0, 1..15, Max. n=15. + * | | |Note: y= B, D, F, H, J, L, N + * |[21] |GPIOyMFOS21|GPIOy Pin[n] Multiple Function Pin Output Mode Select + * | | |This bit used to select multiple function pin output mode type for Py.n pin + * | | |0 = Multiple function pin output mode type is Push-pull mode. + * | | |1 = Multiple function pin output mode type is Open-drain mode. + * | | |Note: n=0, 1..15, Max. n=15. + * | | |Note: y= B, D, F, H, J, L, N + * |[22] |GPIOyMFOS22|GPIOy Pin[n] Multiple Function Pin Output Mode Select + * | | |This bit used to select multiple function pin output mode type for Py.n pin + * | | |0 = Multiple function pin output mode type is Push-pull mode. + * | | |1 = Multiple function pin output mode type is Open-drain mode. + * | | |Note: n=0, 1..15, Max. n=15. + * | | |Note: y= B, D, F, H, J, L, N + * |[23] |GPIOyMFOS23|GPIOy Pin[n] Multiple Function Pin Output Mode Select + * | | |This bit used to select multiple function pin output mode type for Py.n pin + * | | |0 = Multiple function pin output mode type is Push-pull mode. + * | | |1 = Multiple function pin output mode type is Open-drain mode. + * | | |Note: n=0, 1..15, Max. n=15. + * | | |Note: y= B, D, F, H, J, L, N + * |[24] |GPIOyMFOS24|GPIOy Pin[n] Multiple Function Pin Output Mode Select + * | | |This bit used to select multiple function pin output mode type for Py.n pin + * | | |0 = Multiple function pin output mode type is Push-pull mode. + * | | |1 = Multiple function pin output mode type is Open-drain mode. + * | | |Note: n=0, 1..15, Max. n=15. + * | | |Note: y= B, D, F, H, J, L, N + * |[25] |GPIOyMFOS25|GPIOy Pin[n] Multiple Function Pin Output Mode Select + * | | |This bit used to select multiple function pin output mode type for Py.n pin + * | | |0 = Multiple function pin output mode type is Push-pull mode. + * | | |1 = Multiple function pin output mode type is Open-drain mode. + * | | |Note: n=0, 1..15, Max. n=15. + * | | |Note: y= B, D, F, H, J, L, N + * |[26] |GPIOyMFOS26|GPIOy Pin[n] Multiple Function Pin Output Mode Select + * | | |This bit used to select multiple function pin output mode type for Py.n pin + * | | |0 = Multiple function pin output mode type is Push-pull mode. + * | | |1 = Multiple function pin output mode type is Open-drain mode. + * | | |Note: n=0, 1..15, Max. n=15. + * | | |Note: y= B, D, F, H, J, L, N + * |[27] |GPIOyMFOS27|GPIOy Pin[n] Multiple Function Pin Output Mode Select + * | | |This bit used to select multiple function pin output mode type for Py.n pin + * | | |0 = Multiple function pin output mode type is Push-pull mode. + * | | |1 = Multiple function pin output mode type is Open-drain mode. + * | | |Note: n=0, 1..15, Max. n=15. + * | | |Note: y= B, D, F, H, J, L, N + * |[28] |GPIOyMFOS28|GPIOy Pin[n] Multiple Function Pin Output Mode Select + * | | |This bit used to select multiple function pin output mode type for Py.n pin + * | | |0 = Multiple function pin output mode type is Push-pull mode. + * | | |1 = Multiple function pin output mode type is Open-drain mode. + * | | |Note: n=0, 1..15, Max. n=15. + * | | |Note: y= B, D, F, H, J, L, N + * |[29] |GPIOyMFOS29|GPIOy Pin[n] Multiple Function Pin Output Mode Select + * | | |This bit used to select multiple function pin output mode type for Py.n pin + * | | |0 = Multiple function pin output mode type is Push-pull mode. + * | | |1 = Multiple function pin output mode type is Open-drain mode. + * | | |Note: n=0, 1..15, Max. n=15. + * | | |Note: y= B, D, F, H, J, L, N + * |[30] |GPIOyMFOS30|GPIOy Pin[n] Multiple Function Pin Output Mode Select + * | | |This bit used to select multiple function pin output mode type for Py.n pin + * | | |0 = Multiple function pin output mode type is Push-pull mode. + * | | |1 = Multiple function pin output mode type is Open-drain mode. + * | | |Note: n=0, 1..15, Max. n=15. + * | | |Note: y= B, D, F, H, J, L, N + * |[31] |GPIOyMFOS31|GPIOy Pin[n] Multiple Function Pin Output Mode Select + * | | |This bit used to select multiple function pin output mode type for Py.n pin + * | | |0 = Multiple function pin output mode type is Push-pull mode. + * | | |1 = Multiple function pin output mode type is Open-drain mode. + * | | |Note: n=0, 1..15, Max. n=15. + * | | |Note: y= B, D, F, H, J, L, N + * @var SYS_T::GPCD_MFOS + * Offset: 0x144 GPIOC and GPIOD Multiple Function Output Mode Select Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[0] |GPIOxMFOS0|GPIOx Pin[m] Multiple Function Pin Output Mode Select + * | | |This bit used to select multiple function pin output mode type for Px.m pin + * | | |0 = Multiple function pin output mode type is Push-pull mode. + * | | |1 = Multiple function pin output mode type is Open-drain mode. + * | | |Note: Max. m=15. + * | | |Note: y= A, C, E, F, I, K, M + * |[1] |GPIOxMFOS1|GPIOx Pin[m] Multiple Function Pin Output Mode Select + * | | |This bit used to select multiple function pin output mode type for Px.m pin + * | | |0 = Multiple function pin output mode type is Push-pull mode. + * | | |1 = Multiple function pin output mode type is Open-drain mode. + * | | |Note: Max. m=15. + * | | |Note: y= A, C, E, F, I, K, M + * |[2] |GPIOxMFOS2|GPIOx Pin[m] Multiple Function Pin Output Mode Select + * | | |This bit used to select multiple function pin output mode type for Px.m pin + * | | |0 = Multiple function pin output mode type is Push-pull mode. + * | | |1 = Multiple function pin output mode type is Open-drain mode. + * | | |Note: Max. m=15. + * | | |Note: y= A, C, E, F, I, K, M + * |[3] |GPIOxMFOS3|GPIOx Pin[m] Multiple Function Pin Output Mode Select + * | | |This bit used to select multiple function pin output mode type for Px.m pin + * | | |0 = Multiple function pin output mode type is Push-pull mode. + * | | |1 = Multiple function pin output mode type is Open-drain mode. + * | | |Note: Max. m=15. + * | | |Note: y= A, C, E, F, I, K, M + * |[4] |GPIOxMFOS4|GPIOx Pin[m] Multiple Function Pin Output Mode Select + * | | |This bit used to select multiple function pin output mode type for Px.m pin + * | | |0 = Multiple function pin output mode type is Push-pull mode. + * | | |1 = Multiple function pin output mode type is Open-drain mode. + * | | |Note: Max. m=15. + * | | |Note: y= A, C, E, F, I, K, M + * |[5] |GPIOxMFOS5|GPIOx Pin[m] Multiple Function Pin Output Mode Select + * | | |This bit used to select multiple function pin output mode type for Px.m pin + * | | |0 = Multiple function pin output mode type is Push-pull mode. + * | | |1 = Multiple function pin output mode type is Open-drain mode. + * | | |Note: Max. m=15. + * | | |Note: y= A, C, E, F, I, K, M + * |[6] |GPIOxMFOS6|GPIOx Pin[m] Multiple Function Pin Output Mode Select + * | | |This bit used to select multiple function pin output mode type for Px.m pin + * | | |0 = Multiple function pin output mode type is Push-pull mode. + * | | |1 = Multiple function pin output mode type is Open-drain mode. + * | | |Note: Max. m=15. + * | | |Note: y= A, C, E, F, I, K, M + * |[7] |GPIOxMFOS7|GPIOx Pin[m] Multiple Function Pin Output Mode Select + * | | |This bit used to select multiple function pin output mode type for Px.m pin + * | | |0 = Multiple function pin output mode type is Push-pull mode. + * | | |1 = Multiple function pin output mode type is Open-drain mode. + * | | |Note: Max. m=15. + * | | |Note: y= A, C, E, F, I, K, M + * |[8] |GPIOxMFOS8|GPIOx Pin[m] Multiple Function Pin Output Mode Select + * | | |This bit used to select multiple function pin output mode type for Px.m pin + * | | |0 = Multiple function pin output mode type is Push-pull mode. + * | | |1 = Multiple function pin output mode type is Open-drain mode. + * | | |Note: Max. m=15. + * | | |Note: y= A, C, E, F, I, K, M + * |[9] |GPIOxMFOS9|GPIOx Pin[m] Multiple Function Pin Output Mode Select + * | | |This bit used to select multiple function pin output mode type for Px.m pin + * | | |0 = Multiple function pin output mode type is Push-pull mode. + * | | |1 = Multiple function pin output mode type is Open-drain mode. + * | | |Note: Max. m=15. + * | | |Note: y= A, C, E, F, I, K, M + * |[10] |GPIOxMFOS10|GPIOx Pin[m] Multiple Function Pin Output Mode Select + * | | |This bit used to select multiple function pin output mode type for Px.m pin + * | | |0 = Multiple function pin output mode type is Push-pull mode. + * | | |1 = Multiple function pin output mode type is Open-drain mode. + * | | |Note: Max. m=15. + * | | |Note: y= A, C, E, F, I, K, M + * |[11] |GPIOxMFOS11|GPIOx Pin[m] Multiple Function Pin Output Mode Select + * | | |This bit used to select multiple function pin output mode type for Px.m pin + * | | |0 = Multiple function pin output mode type is Push-pull mode. + * | | |1 = Multiple function pin output mode type is Open-drain mode. + * | | |Note: Max. m=15. + * | | |Note: y= A, C, E, F, I, K, M + * |[12] |GPIOxMFOS12|GPIOx Pin[m] Multiple Function Pin Output Mode Select + * | | |This bit used to select multiple function pin output mode type for Px.m pin + * | | |0 = Multiple function pin output mode type is Push-pull mode. + * | | |1 = Multiple function pin output mode type is Open-drain mode. + * | | |Note: Max. m=15. + * | | |Note: y= A, C, E, F, I, K, M + * |[13] |GPIOxMFOS13|GPIOx Pin[m] Multiple Function Pin Output Mode Select + * | | |This bit used to select multiple function pin output mode type for Px.m pin + * | | |0 = Multiple function pin output mode type is Push-pull mode. + * | | |1 = Multiple function pin output mode type is Open-drain mode. + * | | |Note: Max. m=15. + * | | |Note: y= A, C, E, F, I, K, M + * |[14] |GPIOxMFOS14|GPIOx Pin[m] Multiple Function Pin Output Mode Select + * | | |This bit used to select multiple function pin output mode type for Px.m pin + * | | |0 = Multiple function pin output mode type is Push-pull mode. + * | | |1 = Multiple function pin output mode type is Open-drain mode. + * | | |Note: Max. m=15. + * | | |Note: y= A, C, E, F, I, K, M + * |[15] |GPIOxMFOS15|GPIOx Pin[m] Multiple Function Pin Output Mode Select + * | | |This bit used to select multiple function pin output mode type for Px.m pin + * | | |0 = Multiple function pin output mode type is Push-pull mode. + * | | |1 = Multiple function pin output mode type is Open-drain mode. + * | | |Note: Max. m=15. + * | | |Note: y= A, C, E, F, I, K, M + * |[16] |GPIOyMFOS16|GPIOy Pin[n] Multiple Function Pin Output Mode Select + * | | |This bit used to select multiple function pin output mode type for Py.n pin + * | | |0 = Multiple function pin output mode type is Push-pull mode. + * | | |1 = Multiple function pin output mode type is Open-drain mode. + * | | |Note: n=0, 1..15, Max. n=15. + * | | |Note: y= B, D, F, H, J, L, N + * |[17] |GPIOyMFOS17|GPIOy Pin[n] Multiple Function Pin Output Mode Select + * | | |This bit used to select multiple function pin output mode type for Py.n pin + * | | |0 = Multiple function pin output mode type is Push-pull mode. + * | | |1 = Multiple function pin output mode type is Open-drain mode. + * | | |Note: n=0, 1..15, Max. n=15. + * | | |Note: y= B, D, F, H, J, L, N + * |[18] |GPIOyMFOS18|GPIOy Pin[n] Multiple Function Pin Output Mode Select + * | | |This bit used to select multiple function pin output mode type for Py.n pin + * | | |0 = Multiple function pin output mode type is Push-pull mode. + * | | |1 = Multiple function pin output mode type is Open-drain mode. + * | | |Note: n=0, 1..15, Max. n=15. + * | | |Note: y= B, D, F, H, J, L, N + * |[19] |GPIOyMFOS19|GPIOy Pin[n] Multiple Function Pin Output Mode Select + * | | |This bit used to select multiple function pin output mode type for Py.n pin + * | | |0 = Multiple function pin output mode type is Push-pull mode. + * | | |1 = Multiple function pin output mode type is Open-drain mode. + * | | |Note: n=0, 1..15, Max. n=15. + * | | |Note: y= B, D, F, H, J, L, N + * |[20] |GPIOyMFOS20|GPIOy Pin[n] Multiple Function Pin Output Mode Select + * | | |This bit used to select multiple function pin output mode type for Py.n pin + * | | |0 = Multiple function pin output mode type is Push-pull mode. + * | | |1 = Multiple function pin output mode type is Open-drain mode. + * | | |Note: n=0, 1..15, Max. n=15. + * | | |Note: y= B, D, F, H, J, L, N + * |[21] |GPIOyMFOS21|GPIOy Pin[n] Multiple Function Pin Output Mode Select + * | | |This bit used to select multiple function pin output mode type for Py.n pin + * | | |0 = Multiple function pin output mode type is Push-pull mode. + * | | |1 = Multiple function pin output mode type is Open-drain mode. + * | | |Note: n=0, 1..15, Max. n=15. + * | | |Note: y= B, D, F, H, J, L, N + * |[22] |GPIOyMFOS22|GPIOy Pin[n] Multiple Function Pin Output Mode Select + * | | |This bit used to select multiple function pin output mode type for Py.n pin + * | | |0 = Multiple function pin output mode type is Push-pull mode. + * | | |1 = Multiple function pin output mode type is Open-drain mode. + * | | |Note: n=0, 1..15, Max. n=15. + * | | |Note: y= B, D, F, H, J, L, N + * |[23] |GPIOyMFOS23|GPIOy Pin[n] Multiple Function Pin Output Mode Select + * | | |This bit used to select multiple function pin output mode type for Py.n pin + * | | |0 = Multiple function pin output mode type is Push-pull mode. + * | | |1 = Multiple function pin output mode type is Open-drain mode. + * | | |Note: n=0, 1..15, Max. n=15. + * | | |Note: y= B, D, F, H, J, L, N + * |[24] |GPIOyMFOS24|GPIOy Pin[n] Multiple Function Pin Output Mode Select + * | | |This bit used to select multiple function pin output mode type for Py.n pin + * | | |0 = Multiple function pin output mode type is Push-pull mode. + * | | |1 = Multiple function pin output mode type is Open-drain mode. + * | | |Note: n=0, 1..15, Max. n=15. + * | | |Note: y= B, D, F, H, J, L, N + * |[25] |GPIOyMFOS25|GPIOy Pin[n] Multiple Function Pin Output Mode Select + * | | |This bit used to select multiple function pin output mode type for Py.n pin + * | | |0 = Multiple function pin output mode type is Push-pull mode. + * | | |1 = Multiple function pin output mode type is Open-drain mode. + * | | |Note: n=0, 1..15, Max. n=15. + * | | |Note: y= B, D, F, H, J, L, N + * |[26] |GPIOyMFOS26|GPIOy Pin[n] Multiple Function Pin Output Mode Select + * | | |This bit used to select multiple function pin output mode type for Py.n pin + * | | |0 = Multiple function pin output mode type is Push-pull mode. + * | | |1 = Multiple function pin output mode type is Open-drain mode. + * | | |Note: n=0, 1..15, Max. n=15. + * | | |Note: y= B, D, F, H, J, L, N + * |[27] |GPIOyMFOS27|GPIOy Pin[n] Multiple Function Pin Output Mode Select + * | | |This bit used to select multiple function pin output mode type for Py.n pin + * | | |0 = Multiple function pin output mode type is Push-pull mode. + * | | |1 = Multiple function pin output mode type is Open-drain mode. + * | | |Note: n=0, 1..15, Max. n=15. + * | | |Note: y= B, D, F, H, J, L, N + * |[28] |GPIOyMFOS28|GPIOy Pin[n] Multiple Function Pin Output Mode Select + * | | |This bit used to select multiple function pin output mode type for Py.n pin + * | | |0 = Multiple function pin output mode type is Push-pull mode. + * | | |1 = Multiple function pin output mode type is Open-drain mode. + * | | |Note: n=0, 1..15, Max. n=15. + * | | |Note: y= B, D, F, H, J, L, N + * |[29] |GPIOyMFOS29|GPIOy Pin[n] Multiple Function Pin Output Mode Select + * | | |This bit used to select multiple function pin output mode type for Py.n pin + * | | |0 = Multiple function pin output mode type is Push-pull mode. + * | | |1 = Multiple function pin output mode type is Open-drain mode. + * | | |Note: n=0, 1..15, Max. n=15. + * | | |Note: y= B, D, F, H, J, L, N + * |[30] |GPIOyMFOS30|GPIOy Pin[n] Multiple Function Pin Output Mode Select + * | | |This bit used to select multiple function pin output mode type for Py.n pin + * | | |0 = Multiple function pin output mode type is Push-pull mode. + * | | |1 = Multiple function pin output mode type is Open-drain mode. + * | | |Note: n=0, 1..15, Max. n=15. + * | | |Note: y= B, D, F, H, J, L, N + * |[31] |GPIOyMFOS31|GPIOy Pin[n] Multiple Function Pin Output Mode Select + * | | |This bit used to select multiple function pin output mode type for Py.n pin + * | | |0 = Multiple function pin output mode type is Push-pull mode. + * | | |1 = Multiple function pin output mode type is Open-drain mode. + * | | |Note: n=0, 1..15, Max. n=15. + * | | |Note: y= B, D, F, H, J, L, N + * @var SYS_T::GPEF_MFOS + * Offset: 0x148 GPIOE and GPIOF Multiple Function Output Mode Select Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[0] |GPIOxMFOS0|GPIOx Pin[m] Multiple Function Pin Output Mode Select + * | | |This bit used to select multiple function pin output mode type for Px.m pin + * | | |0 = Multiple function pin output mode type is Push-pull mode. + * | | |1 = Multiple function pin output mode type is Open-drain mode. + * | | |Note: Max. m=15. + * | | |Note: y= A, C, E, F, I, K, M + * |[1] |GPIOxMFOS1|GPIOx Pin[m] Multiple Function Pin Output Mode Select + * | | |This bit used to select multiple function pin output mode type for Px.m pin + * | | |0 = Multiple function pin output mode type is Push-pull mode. + * | | |1 = Multiple function pin output mode type is Open-drain mode. + * | | |Note: Max. m=15. + * | | |Note: y= A, C, E, F, I, K, M + * |[2] |GPIOxMFOS2|GPIOx Pin[m] Multiple Function Pin Output Mode Select + * | | |This bit used to select multiple function pin output mode type for Px.m pin + * | | |0 = Multiple function pin output mode type is Push-pull mode. + * | | |1 = Multiple function pin output mode type is Open-drain mode. + * | | |Note: Max. m=15. + * | | |Note: y= A, C, E, F, I, K, M + * |[3] |GPIOxMFOS3|GPIOx Pin[m] Multiple Function Pin Output Mode Select + * | | |This bit used to select multiple function pin output mode type for Px.m pin + * | | |0 = Multiple function pin output mode type is Push-pull mode. + * | | |1 = Multiple function pin output mode type is Open-drain mode. + * | | |Note: Max. m=15. + * | | |Note: y= A, C, E, F, I, K, M + * |[4] |GPIOxMFOS4|GPIOx Pin[m] Multiple Function Pin Output Mode Select + * | | |This bit used to select multiple function pin output mode type for Px.m pin + * | | |0 = Multiple function pin output mode type is Push-pull mode. + * | | |1 = Multiple function pin output mode type is Open-drain mode. + * | | |Note: Max. m=15. + * | | |Note: y= A, C, E, F, I, K, M + * |[5] |GPIOxMFOS5|GPIOx Pin[m] Multiple Function Pin Output Mode Select + * | | |This bit used to select multiple function pin output mode type for Px.m pin + * | | |0 = Multiple function pin output mode type is Push-pull mode. + * | | |1 = Multiple function pin output mode type is Open-drain mode. + * | | |Note: Max. m=15. + * | | |Note: y= A, C, E, F, I, K, M + * |[6] |GPIOxMFOS6|GPIOx Pin[m] Multiple Function Pin Output Mode Select + * | | |This bit used to select multiple function pin output mode type for Px.m pin + * | | |0 = Multiple function pin output mode type is Push-pull mode. + * | | |1 = Multiple function pin output mode type is Open-drain mode. + * | | |Note: Max. m=15. + * | | |Note: y= A, C, E, F, I, K, M + * |[7] |GPIOxMFOS7|GPIOx Pin[m] Multiple Function Pin Output Mode Select + * | | |This bit used to select multiple function pin output mode type for Px.m pin + * | | |0 = Multiple function pin output mode type is Push-pull mode. + * | | |1 = Multiple function pin output mode type is Open-drain mode. + * | | |Note: Max. m=15. + * | | |Note: y= A, C, E, F, I, K, M + * |[8] |GPIOxMFOS8|GPIOx Pin[m] Multiple Function Pin Output Mode Select + * | | |This bit used to select multiple function pin output mode type for Px.m pin + * | | |0 = Multiple function pin output mode type is Push-pull mode. + * | | |1 = Multiple function pin output mode type is Open-drain mode. + * | | |Note: Max. m=15. + * | | |Note: y= A, C, E, F, I, K, M + * |[9] |GPIOxMFOS9|GPIOx Pin[m] Multiple Function Pin Output Mode Select + * | | |This bit used to select multiple function pin output mode type for Px.m pin + * | | |0 = Multiple function pin output mode type is Push-pull mode. + * | | |1 = Multiple function pin output mode type is Open-drain mode. + * | | |Note: Max. m=15. + * | | |Note: y= A, C, E, F, I, K, M + * |[10] |GPIOxMFOS10|GPIOx Pin[m] Multiple Function Pin Output Mode Select + * | | |This bit used to select multiple function pin output mode type for Px.m pin + * | | |0 = Multiple function pin output mode type is Push-pull mode. + * | | |1 = Multiple function pin output mode type is Open-drain mode. + * | | |Note: Max. m=15. + * | | |Note: y= A, C, E, F, I, K, M + * |[11] |GPIOxMFOS11|GPIOx Pin[m] Multiple Function Pin Output Mode Select + * | | |This bit used to select multiple function pin output mode type for Px.m pin + * | | |0 = Multiple function pin output mode type is Push-pull mode. + * | | |1 = Multiple function pin output mode type is Open-drain mode. + * | | |Note: Max. m=15. + * | | |Note: y= A, C, E, F, I, K, M + * |[12] |GPIOxMFOS12|GPIOx Pin[m] Multiple Function Pin Output Mode Select + * | | |This bit used to select multiple function pin output mode type for Px.m pin + * | | |0 = Multiple function pin output mode type is Push-pull mode. + * | | |1 = Multiple function pin output mode type is Open-drain mode. + * | | |Note: Max. m=15. + * | | |Note: y= A, C, E, F, I, K, M + * |[13] |GPIOxMFOS13|GPIOx Pin[m] Multiple Function Pin Output Mode Select + * | | |This bit used to select multiple function pin output mode type for Px.m pin + * | | |0 = Multiple function pin output mode type is Push-pull mode. + * | | |1 = Multiple function pin output mode type is Open-drain mode. + * | | |Note: Max. m=15. + * | | |Note: y= A, C, E, F, I, K, M + * |[14] |GPIOxMFOS14|GPIOx Pin[m] Multiple Function Pin Output Mode Select + * | | |This bit used to select multiple function pin output mode type for Px.m pin + * | | |0 = Multiple function pin output mode type is Push-pull mode. + * | | |1 = Multiple function pin output mode type is Open-drain mode. + * | | |Note: Max. m=15. + * | | |Note: y= A, C, E, F, I, K, M + * |[15] |GPIOxMFOS15|GPIOx Pin[m] Multiple Function Pin Output Mode Select + * | | |This bit used to select multiple function pin output mode type for Px.m pin + * | | |0 = Multiple function pin output mode type is Push-pull mode. + * | | |1 = Multiple function pin output mode type is Open-drain mode. + * | | |Note: Max. m=15. + * | | |Note: y= A, C, E, F, I, K, M + * |[16] |GPIOyMFOS16|GPIOy Pin[n] Multiple Function Pin Output Mode Select + * | | |This bit used to select multiple function pin output mode type for Py.n pin + * | | |0 = Multiple function pin output mode type is Push-pull mode. + * | | |1 = Multiple function pin output mode type is Open-drain mode. + * | | |Note: n=0, 1..15, Max. n=15. + * | | |Note: y= B, D, F, H, J, L, N + * |[17] |GPIOyMFOS17|GPIOy Pin[n] Multiple Function Pin Output Mode Select + * | | |This bit used to select multiple function pin output mode type for Py.n pin + * | | |0 = Multiple function pin output mode type is Push-pull mode. + * | | |1 = Multiple function pin output mode type is Open-drain mode. + * | | |Note: n=0, 1..15, Max. n=15. + * | | |Note: y= B, D, F, H, J, L, N + * |[18] |GPIOyMFOS18|GPIOy Pin[n] Multiple Function Pin Output Mode Select + * | | |This bit used to select multiple function pin output mode type for Py.n pin + * | | |0 = Multiple function pin output mode type is Push-pull mode. + * | | |1 = Multiple function pin output mode type is Open-drain mode. + * | | |Note: n=0, 1..15, Max. n=15. + * | | |Note: y= B, D, F, H, J, L, N + * |[19] |GPIOyMFOS19|GPIOy Pin[n] Multiple Function Pin Output Mode Select + * | | |This bit used to select multiple function pin output mode type for Py.n pin + * | | |0 = Multiple function pin output mode type is Push-pull mode. + * | | |1 = Multiple function pin output mode type is Open-drain mode. + * | | |Note: n=0, 1..15, Max. n=15. + * | | |Note: y= B, D, F, H, J, L, N + * |[20] |GPIOyMFOS20|GPIOy Pin[n] Multiple Function Pin Output Mode Select + * | | |This bit used to select multiple function pin output mode type for Py.n pin + * | | |0 = Multiple function pin output mode type is Push-pull mode. + * | | |1 = Multiple function pin output mode type is Open-drain mode. + * | | |Note: n=0, 1..15, Max. n=15. + * | | |Note: y= B, D, F, H, J, L, N + * |[21] |GPIOyMFOS21|GPIOy Pin[n] Multiple Function Pin Output Mode Select + * | | |This bit used to select multiple function pin output mode type for Py.n pin + * | | |0 = Multiple function pin output mode type is Push-pull mode. + * | | |1 = Multiple function pin output mode type is Open-drain mode. + * | | |Note: n=0, 1..15, Max. n=15. + * | | |Note: y= B, D, F, H, J, L, N + * |[22] |GPIOyMFOS22|GPIOy Pin[n] Multiple Function Pin Output Mode Select + * | | |This bit used to select multiple function pin output mode type for Py.n pin + * | | |0 = Multiple function pin output mode type is Push-pull mode. + * | | |1 = Multiple function pin output mode type is Open-drain mode. + * | | |Note: n=0, 1..15, Max. n=15. + * | | |Note: y= B, D, F, H, J, L, N + * |[23] |GPIOyMFOS23|GPIOy Pin[n] Multiple Function Pin Output Mode Select + * | | |This bit used to select multiple function pin output mode type for Py.n pin + * | | |0 = Multiple function pin output mode type is Push-pull mode. + * | | |1 = Multiple function pin output mode type is Open-drain mode. + * | | |Note: n=0, 1..15, Max. n=15. + * | | |Note: y= B, D, F, H, J, L, N + * |[24] |GPIOyMFOS24|GPIOy Pin[n] Multiple Function Pin Output Mode Select + * | | |This bit used to select multiple function pin output mode type for Py.n pin + * | | |0 = Multiple function pin output mode type is Push-pull mode. + * | | |1 = Multiple function pin output mode type is Open-drain mode. + * | | |Note: n=0, 1..15, Max. n=15. + * | | |Note: y= B, D, F, H, J, L, N + * |[25] |GPIOyMFOS25|GPIOy Pin[n] Multiple Function Pin Output Mode Select + * | | |This bit used to select multiple function pin output mode type for Py.n pin + * | | |0 = Multiple function pin output mode type is Push-pull mode. + * | | |1 = Multiple function pin output mode type is Open-drain mode. + * | | |Note: n=0, 1..15, Max. n=15. + * | | |Note: y= B, D, F, H, J, L, N + * |[26] |GPIOyMFOS26|GPIOy Pin[n] Multiple Function Pin Output Mode Select + * | | |This bit used to select multiple function pin output mode type for Py.n pin + * | | |0 = Multiple function pin output mode type is Push-pull mode. + * | | |1 = Multiple function pin output mode type is Open-drain mode. + * | | |Note: n=0, 1..15, Max. n=15. + * | | |Note: y= B, D, F, H, J, L, N + * |[27] |GPIOyMFOS27|GPIOy Pin[n] Multiple Function Pin Output Mode Select + * | | |This bit used to select multiple function pin output mode type for Py.n pin + * | | |0 = Multiple function pin output mode type is Push-pull mode. + * | | |1 = Multiple function pin output mode type is Open-drain mode. + * | | |Note: n=0, 1..15, Max. n=15. + * | | |Note: y= B, D, F, H, J, L, N + * |[28] |GPIOyMFOS28|GPIOy Pin[n] Multiple Function Pin Output Mode Select + * | | |This bit used to select multiple function pin output mode type for Py.n pin + * | | |0 = Multiple function pin output mode type is Push-pull mode. + * | | |1 = Multiple function pin output mode type is Open-drain mode. + * | | |Note: n=0, 1..15, Max. n=15. + * | | |Note: y= B, D, F, H, J, L, N + * |[29] |GPIOyMFOS29|GPIOy Pin[n] Multiple Function Pin Output Mode Select + * | | |This bit used to select multiple function pin output mode type for Py.n pin + * | | |0 = Multiple function pin output mode type is Push-pull mode. + * | | |1 = Multiple function pin output mode type is Open-drain mode. + * | | |Note: n=0, 1..15, Max. n=15. + * | | |Note: y= B, D, F, H, J, L, N + * |[30] |GPIOyMFOS30|GPIOy Pin[n] Multiple Function Pin Output Mode Select + * | | |This bit used to select multiple function pin output mode type for Py.n pin + * | | |0 = Multiple function pin output mode type is Push-pull mode. + * | | |1 = Multiple function pin output mode type is Open-drain mode. + * | | |Note: n=0, 1..15, Max. n=15. + * | | |Note: y= B, D, F, H, J, L, N + * |[31] |GPIOyMFOS31|GPIOy Pin[n] Multiple Function Pin Output Mode Select + * | | |This bit used to select multiple function pin output mode type for Py.n pin + * | | |0 = Multiple function pin output mode type is Push-pull mode. + * | | |1 = Multiple function pin output mode type is Open-drain mode. + * | | |Note: n=0, 1..15, Max. n=15. + * | | |Note: y= B, D, F, H, J, L, N + * @var SYS_T::GPGH_MFOS + * Offset: 0x14C GPIOG and GPIOH Multiple Function Output Mode Select Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[0] |GPIOxMFOS0|GPIOx Pin[m] Multiple Function Pin Output Mode Select + * | | |This bit used to select multiple function pin output mode type for Px.m pin + * | | |0 = Multiple function pin output mode type is Push-pull mode. + * | | |1 = Multiple function pin output mode type is Open-drain mode. + * | | |Note: Max. m=15. + * | | |Note: y= A, C, E, F, I, K, M + * |[1] |GPIOxMFOS1|GPIOx Pin[m] Multiple Function Pin Output Mode Select + * | | |This bit used to select multiple function pin output mode type for Px.m pin + * | | |0 = Multiple function pin output mode type is Push-pull mode. + * | | |1 = Multiple function pin output mode type is Open-drain mode. + * | | |Note: Max. m=15. + * | | |Note: y= A, C, E, F, I, K, M + * |[2] |GPIOxMFOS2|GPIOx Pin[m] Multiple Function Pin Output Mode Select + * | | |This bit used to select multiple function pin output mode type for Px.m pin + * | | |0 = Multiple function pin output mode type is Push-pull mode. + * | | |1 = Multiple function pin output mode type is Open-drain mode. + * | | |Note: Max. m=15. + * | | |Note: y= A, C, E, F, I, K, M + * |[3] |GPIOxMFOS3|GPIOx Pin[m] Multiple Function Pin Output Mode Select + * | | |This bit used to select multiple function pin output mode type for Px.m pin + * | | |0 = Multiple function pin output mode type is Push-pull mode. + * | | |1 = Multiple function pin output mode type is Open-drain mode. + * | | |Note: Max. m=15. + * | | |Note: y= A, C, E, F, I, K, M + * |[4] |GPIOxMFOS4|GPIOx Pin[m] Multiple Function Pin Output Mode Select + * | | |This bit used to select multiple function pin output mode type for Px.m pin + * | | |0 = Multiple function pin output mode type is Push-pull mode. + * | | |1 = Multiple function pin output mode type is Open-drain mode. + * | | |Note: Max. m=15. + * | | |Note: y= A, C, E, F, I, K, M + * |[5] |GPIOxMFOS5|GPIOx Pin[m] Multiple Function Pin Output Mode Select + * | | |This bit used to select multiple function pin output mode type for Px.m pin + * | | |0 = Multiple function pin output mode type is Push-pull mode. + * | | |1 = Multiple function pin output mode type is Open-drain mode. + * | | |Note: Max. m=15. + * | | |Note: y= A, C, E, F, I, K, M + * |[6] |GPIOxMFOS6|GPIOx Pin[m] Multiple Function Pin Output Mode Select + * | | |This bit used to select multiple function pin output mode type for Px.m pin + * | | |0 = Multiple function pin output mode type is Push-pull mode. + * | | |1 = Multiple function pin output mode type is Open-drain mode. + * | | |Note: Max. m=15. + * | | |Note: y= A, C, E, F, I, K, M + * |[7] |GPIOxMFOS7|GPIOx Pin[m] Multiple Function Pin Output Mode Select + * | | |This bit used to select multiple function pin output mode type for Px.m pin + * | | |0 = Multiple function pin output mode type is Push-pull mode. + * | | |1 = Multiple function pin output mode type is Open-drain mode. + * | | |Note: Max. m=15. + * | | |Note: y= A, C, E, F, I, K, M + * |[8] |GPIOxMFOS8|GPIOx Pin[m] Multiple Function Pin Output Mode Select + * | | |This bit used to select multiple function pin output mode type for Px.m pin + * | | |0 = Multiple function pin output mode type is Push-pull mode. + * | | |1 = Multiple function pin output mode type is Open-drain mode. + * | | |Note: Max. m=15. + * | | |Note: y= A, C, E, F, I, K, M + * |[9] |GPIOxMFOS9|GPIOx Pin[m] Multiple Function Pin Output Mode Select + * | | |This bit used to select multiple function pin output mode type for Px.m pin + * | | |0 = Multiple function pin output mode type is Push-pull mode. + * | | |1 = Multiple function pin output mode type is Open-drain mode. + * | | |Note: Max. m=15. + * | | |Note: y= A, C, E, F, I, K, M + * |[10] |GPIOxMFOS10|GPIOx Pin[m] Multiple Function Pin Output Mode Select + * | | |This bit used to select multiple function pin output mode type for Px.m pin + * | | |0 = Multiple function pin output mode type is Push-pull mode. + * | | |1 = Multiple function pin output mode type is Open-drain mode. + * | | |Note: Max. m=15. + * | | |Note: y= A, C, E, F, I, K, M + * |[11] |GPIOxMFOS11|GPIOx Pin[m] Multiple Function Pin Output Mode Select + * | | |This bit used to select multiple function pin output mode type for Px.m pin + * | | |0 = Multiple function pin output mode type is Push-pull mode. + * | | |1 = Multiple function pin output mode type is Open-drain mode. + * | | |Note: Max. m=15. + * | | |Note: y= A, C, E, F, I, K, M + * |[12] |GPIOxMFOS12|GPIOx Pin[m] Multiple Function Pin Output Mode Select + * | | |This bit used to select multiple function pin output mode type for Px.m pin + * | | |0 = Multiple function pin output mode type is Push-pull mode. + * | | |1 = Multiple function pin output mode type is Open-drain mode. + * | | |Note: Max. m=15. + * | | |Note: y= A, C, E, F, I, K, M + * |[13] |GPIOxMFOS13|GPIOx Pin[m] Multiple Function Pin Output Mode Select + * | | |This bit used to select multiple function pin output mode type for Px.m pin + * | | |0 = Multiple function pin output mode type is Push-pull mode. + * | | |1 = Multiple function pin output mode type is Open-drain mode. + * | | |Note: Max. m=15. + * | | |Note: y= A, C, E, F, I, K, M + * |[14] |GPIOxMFOS14|GPIOx Pin[m] Multiple Function Pin Output Mode Select + * | | |This bit used to select multiple function pin output mode type for Px.m pin + * | | |0 = Multiple function pin output mode type is Push-pull mode. + * | | |1 = Multiple function pin output mode type is Open-drain mode. + * | | |Note: Max. m=15. + * | | |Note: y= A, C, E, F, I, K, M + * |[15] |GPIOxMFOS15|GPIOx Pin[m] Multiple Function Pin Output Mode Select + * | | |This bit used to select multiple function pin output mode type for Px.m pin + * | | |0 = Multiple function pin output mode type is Push-pull mode. + * | | |1 = Multiple function pin output mode type is Open-drain mode. + * | | |Note: Max. m=15. + * | | |Note: y= A, C, E, F, I, K, M + * |[16] |GPIOyMFOS16|GPIOy Pin[n] Multiple Function Pin Output Mode Select + * | | |This bit used to select multiple function pin output mode type for Py.n pin + * | | |0 = Multiple function pin output mode type is Push-pull mode. + * | | |1 = Multiple function pin output mode type is Open-drain mode. + * | | |Note: n=0, 1..15, Max. n=15. + * | | |Note: y= B, D, F, H, J, L, N + * |[17] |GPIOyMFOS17|GPIOy Pin[n] Multiple Function Pin Output Mode Select + * | | |This bit used to select multiple function pin output mode type for Py.n pin + * | | |0 = Multiple function pin output mode type is Push-pull mode. + * | | |1 = Multiple function pin output mode type is Open-drain mode. + * | | |Note: n=0, 1..15, Max. n=15. + * | | |Note: y= B, D, F, H, J, L, N + * |[18] |GPIOyMFOS18|GPIOy Pin[n] Multiple Function Pin Output Mode Select + * | | |This bit used to select multiple function pin output mode type for Py.n pin + * | | |0 = Multiple function pin output mode type is Push-pull mode. + * | | |1 = Multiple function pin output mode type is Open-drain mode. + * | | |Note: n=0, 1..15, Max. n=15. + * | | |Note: y= B, D, F, H, J, L, N + * |[19] |GPIOyMFOS19|GPIOy Pin[n] Multiple Function Pin Output Mode Select + * | | |This bit used to select multiple function pin output mode type for Py.n pin + * | | |0 = Multiple function pin output mode type is Push-pull mode. + * | | |1 = Multiple function pin output mode type is Open-drain mode. + * | | |Note: n=0, 1..15, Max. n=15. + * | | |Note: y= B, D, F, H, J, L, N + * |[20] |GPIOyMFOS20|GPIOy Pin[n] Multiple Function Pin Output Mode Select + * | | |This bit used to select multiple function pin output mode type for Py.n pin + * | | |0 = Multiple function pin output mode type is Push-pull mode. + * | | |1 = Multiple function pin output mode type is Open-drain mode. + * | | |Note: n=0, 1..15, Max. n=15. + * | | |Note: y= B, D, F, H, J, L, N + * |[21] |GPIOyMFOS21|GPIOy Pin[n] Multiple Function Pin Output Mode Select + * | | |This bit used to select multiple function pin output mode type for Py.n pin + * | | |0 = Multiple function pin output mode type is Push-pull mode. + * | | |1 = Multiple function pin output mode type is Open-drain mode. + * | | |Note: n=0, 1..15, Max. n=15. + * | | |Note: y= B, D, F, H, J, L, N + * |[22] |GPIOyMFOS22|GPIOy Pin[n] Multiple Function Pin Output Mode Select + * | | |This bit used to select multiple function pin output mode type for Py.n pin + * | | |0 = Multiple function pin output mode type is Push-pull mode. + * | | |1 = Multiple function pin output mode type is Open-drain mode. + * | | |Note: n=0, 1..15, Max. n=15. + * | | |Note: y= B, D, F, H, J, L, N + * |[23] |GPIOyMFOS23|GPIOy Pin[n] Multiple Function Pin Output Mode Select + * | | |This bit used to select multiple function pin output mode type for Py.n pin + * | | |0 = Multiple function pin output mode type is Push-pull mode. + * | | |1 = Multiple function pin output mode type is Open-drain mode. + * | | |Note: n=0, 1..15, Max. n=15. + * | | |Note: y= B, D, F, H, J, L, N + * |[24] |GPIOyMFOS24|GPIOy Pin[n] Multiple Function Pin Output Mode Select + * | | |This bit used to select multiple function pin output mode type for Py.n pin + * | | |0 = Multiple function pin output mode type is Push-pull mode. + * | | |1 = Multiple function pin output mode type is Open-drain mode. + * | | |Note: n=0, 1..15, Max. n=15. + * | | |Note: y= B, D, F, H, J, L, N + * |[25] |GPIOyMFOS25|GPIOy Pin[n] Multiple Function Pin Output Mode Select + * | | |This bit used to select multiple function pin output mode type for Py.n pin + * | | |0 = Multiple function pin output mode type is Push-pull mode. + * | | |1 = Multiple function pin output mode type is Open-drain mode. + * | | |Note: n=0, 1..15, Max. n=15. + * | | |Note: y= B, D, F, H, J, L, N + * |[26] |GPIOyMFOS26|GPIOy Pin[n] Multiple Function Pin Output Mode Select + * | | |This bit used to select multiple function pin output mode type for Py.n pin + * | | |0 = Multiple function pin output mode type is Push-pull mode. + * | | |1 = Multiple function pin output mode type is Open-drain mode. + * | | |Note: n=0, 1..15, Max. n=15. + * | | |Note: y= B, D, F, H, J, L, N + * |[27] |GPIOyMFOS27|GPIOy Pin[n] Multiple Function Pin Output Mode Select + * | | |This bit used to select multiple function pin output mode type for Py.n pin + * | | |0 = Multiple function pin output mode type is Push-pull mode. + * | | |1 = Multiple function pin output mode type is Open-drain mode. + * | | |Note: n=0, 1..15, Max. n=15. + * | | |Note: y= B, D, F, H, J, L, N + * |[28] |GPIOyMFOS28|GPIOy Pin[n] Multiple Function Pin Output Mode Select + * | | |This bit used to select multiple function pin output mode type for Py.n pin + * | | |0 = Multiple function pin output mode type is Push-pull mode. + * | | |1 = Multiple function pin output mode type is Open-drain mode. + * | | |Note: n=0, 1..15, Max. n=15. + * | | |Note: y= B, D, F, H, J, L, N + * |[29] |GPIOyMFOS29|GPIOy Pin[n] Multiple Function Pin Output Mode Select + * | | |This bit used to select multiple function pin output mode type for Py.n pin + * | | |0 = Multiple function pin output mode type is Push-pull mode. + * | | |1 = Multiple function pin output mode type is Open-drain mode. + * | | |Note: n=0, 1..15, Max. n=15. + * | | |Note: y= B, D, F, H, J, L, N + * |[30] |GPIOyMFOS30|GPIOy Pin[n] Multiple Function Pin Output Mode Select + * | | |This bit used to select multiple function pin output mode type for Py.n pin + * | | |0 = Multiple function pin output mode type is Push-pull mode. + * | | |1 = Multiple function pin output mode type is Open-drain mode. + * | | |Note: n=0, 1..15, Max. n=15. + * | | |Note: y= B, D, F, H, J, L, N + * |[31] |GPIOyMFOS31|GPIOy Pin[n] Multiple Function Pin Output Mode Select + * | | |This bit used to select multiple function pin output mode type for Py.n pin + * | | |0 = Multiple function pin output mode type is Push-pull mode. + * | | |1 = Multiple function pin output mode type is Open-drain mode. + * | | |Note: n=0, 1..15, Max. n=15. + * | | |Note: y= B, D, F, H, J, L, N + * @var SYS_T::GPIJ_MFOS + * Offset: 0x150 GPIOI and GPIOJ Multiple Function Output Mode Select Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[0] |GPIOxMFOS0|GPIOx Pin[m] Multiple Function Pin Output Mode Select + * | | |This bit used to select multiple function pin output mode type for Px.m pin + * | | |0 = Multiple function pin output mode type is Push-pull mode. + * | | |1 = Multiple function pin output mode type is Open-drain mode. + * | | |Note: Max. m=15. + * | | |Note: y= A, C, E, F, I, K, M + * |[1] |GPIOxMFOS1|GPIOx Pin[m] Multiple Function Pin Output Mode Select + * | | |This bit used to select multiple function pin output mode type for Px.m pin + * | | |0 = Multiple function pin output mode type is Push-pull mode. + * | | |1 = Multiple function pin output mode type is Open-drain mode. + * | | |Note: Max. m=15. + * | | |Note: y= A, C, E, F, I, K, M + * |[2] |GPIOxMFOS2|GPIOx Pin[m] Multiple Function Pin Output Mode Select + * | | |This bit used to select multiple function pin output mode type for Px.m pin + * | | |0 = Multiple function pin output mode type is Push-pull mode. + * | | |1 = Multiple function pin output mode type is Open-drain mode. + * | | |Note: Max. m=15. + * | | |Note: y= A, C, E, F, I, K, M + * |[3] |GPIOxMFOS3|GPIOx Pin[m] Multiple Function Pin Output Mode Select + * | | |This bit used to select multiple function pin output mode type for Px.m pin + * | | |0 = Multiple function pin output mode type is Push-pull mode. + * | | |1 = Multiple function pin output mode type is Open-drain mode. + * | | |Note: Max. m=15. + * | | |Note: y= A, C, E, F, I, K, M + * |[4] |GPIOxMFOS4|GPIOx Pin[m] Multiple Function Pin Output Mode Select + * | | |This bit used to select multiple function pin output mode type for Px.m pin + * | | |0 = Multiple function pin output mode type is Push-pull mode. + * | | |1 = Multiple function pin output mode type is Open-drain mode. + * | | |Note: Max. m=15. + * | | |Note: y= A, C, E, F, I, K, M + * |[5] |GPIOxMFOS5|GPIOx Pin[m] Multiple Function Pin Output Mode Select + * | | |This bit used to select multiple function pin output mode type for Px.m pin + * | | |0 = Multiple function pin output mode type is Push-pull mode. + * | | |1 = Multiple function pin output mode type is Open-drain mode. + * | | |Note: Max. m=15. + * | | |Note: y= A, C, E, F, I, K, M + * |[6] |GPIOxMFOS6|GPIOx Pin[m] Multiple Function Pin Output Mode Select + * | | |This bit used to select multiple function pin output mode type for Px.m pin + * | | |0 = Multiple function pin output mode type is Push-pull mode. + * | | |1 = Multiple function pin output mode type is Open-drain mode. + * | | |Note: Max. m=15. + * | | |Note: y= A, C, E, F, I, K, M + * |[7] |GPIOxMFOS7|GPIOx Pin[m] Multiple Function Pin Output Mode Select + * | | |This bit used to select multiple function pin output mode type for Px.m pin + * | | |0 = Multiple function pin output mode type is Push-pull mode. + * | | |1 = Multiple function pin output mode type is Open-drain mode. + * | | |Note: Max. m=15. + * | | |Note: y= A, C, E, F, I, K, M + * |[8] |GPIOxMFOS8|GPIOx Pin[m] Multiple Function Pin Output Mode Select + * | | |This bit used to select multiple function pin output mode type for Px.m pin + * | | |0 = Multiple function pin output mode type is Push-pull mode. + * | | |1 = Multiple function pin output mode type is Open-drain mode. + * | | |Note: Max. m=15. + * | | |Note: y= A, C, E, F, I, K, M + * |[9] |GPIOxMFOS9|GPIOx Pin[m] Multiple Function Pin Output Mode Select + * | | |This bit used to select multiple function pin output mode type for Px.m pin + * | | |0 = Multiple function pin output mode type is Push-pull mode. + * | | |1 = Multiple function pin output mode type is Open-drain mode. + * | | |Note: Max. m=15. + * | | |Note: y= A, C, E, F, I, K, M + * |[10] |GPIOxMFOS10|GPIOx Pin[m] Multiple Function Pin Output Mode Select + * | | |This bit used to select multiple function pin output mode type for Px.m pin + * | | |0 = Multiple function pin output mode type is Push-pull mode. + * | | |1 = Multiple function pin output mode type is Open-drain mode. + * | | |Note: Max. m=15. + * | | |Note: y= A, C, E, F, I, K, M + * |[11] |GPIOxMFOS11|GPIOx Pin[m] Multiple Function Pin Output Mode Select + * | | |This bit used to select multiple function pin output mode type for Px.m pin + * | | |0 = Multiple function pin output mode type is Push-pull mode. + * | | |1 = Multiple function pin output mode type is Open-drain mode. + * | | |Note: Max. m=15. + * | | |Note: y= A, C, E, F, I, K, M + * |[12] |GPIOxMFOS12|GPIOx Pin[m] Multiple Function Pin Output Mode Select + * | | |This bit used to select multiple function pin output mode type for Px.m pin + * | | |0 = Multiple function pin output mode type is Push-pull mode. + * | | |1 = Multiple function pin output mode type is Open-drain mode. + * | | |Note: Max. m=15. + * | | |Note: y= A, C, E, F, I, K, M + * |[13] |GPIOxMFOS13|GPIOx Pin[m] Multiple Function Pin Output Mode Select + * | | |This bit used to select multiple function pin output mode type for Px.m pin + * | | |0 = Multiple function pin output mode type is Push-pull mode. + * | | |1 = Multiple function pin output mode type is Open-drain mode. + * | | |Note: Max. m=15. + * | | |Note: y= A, C, E, F, I, K, M + * |[14] |GPIOxMFOS14|GPIOx Pin[m] Multiple Function Pin Output Mode Select + * | | |This bit used to select multiple function pin output mode type for Px.m pin + * | | |0 = Multiple function pin output mode type is Push-pull mode. + * | | |1 = Multiple function pin output mode type is Open-drain mode. + * | | |Note: Max. m=15. + * | | |Note: y= A, C, E, F, I, K, M + * |[15] |GPIOxMFOS15|GPIOx Pin[m] Multiple Function Pin Output Mode Select + * | | |This bit used to select multiple function pin output mode type for Px.m pin + * | | |0 = Multiple function pin output mode type is Push-pull mode. + * | | |1 = Multiple function pin output mode type is Open-drain mode. + * | | |Note: Max. m=15. + * | | |Note: y= A, C, E, F, I, K, M + * |[16] |GPIOyMFOS16|GPIOy Pin[n] Multiple Function Pin Output Mode Select + * | | |This bit used to select multiple function pin output mode type for Py.n pin + * | | |0 = Multiple function pin output mode type is Push-pull mode. + * | | |1 = Multiple function pin output mode type is Open-drain mode. + * | | |Note: n=0, 1..15, Max. n=15. + * | | |Note: y= B, D, F, H, J, L, N + * |[17] |GPIOyMFOS17|GPIOy Pin[n] Multiple Function Pin Output Mode Select + * | | |This bit used to select multiple function pin output mode type for Py.n pin + * | | |0 = Multiple function pin output mode type is Push-pull mode. + * | | |1 = Multiple function pin output mode type is Open-drain mode. + * | | |Note: n=0, 1..15, Max. n=15. + * | | |Note: y= B, D, F, H, J, L, N + * |[18] |GPIOyMFOS18|GPIOy Pin[n] Multiple Function Pin Output Mode Select + * | | |This bit used to select multiple function pin output mode type for Py.n pin + * | | |0 = Multiple function pin output mode type is Push-pull mode. + * | | |1 = Multiple function pin output mode type is Open-drain mode. + * | | |Note: n=0, 1..15, Max. n=15. + * | | |Note: y= B, D, F, H, J, L, N + * |[19] |GPIOyMFOS19|GPIOy Pin[n] Multiple Function Pin Output Mode Select + * | | |This bit used to select multiple function pin output mode type for Py.n pin + * | | |0 = Multiple function pin output mode type is Push-pull mode. + * | | |1 = Multiple function pin output mode type is Open-drain mode. + * | | |Note: n=0, 1..15, Max. n=15. + * | | |Note: y= B, D, F, H, J, L, N + * |[20] |GPIOyMFOS20|GPIOy Pin[n] Multiple Function Pin Output Mode Select + * | | |This bit used to select multiple function pin output mode type for Py.n pin + * | | |0 = Multiple function pin output mode type is Push-pull mode. + * | | |1 = Multiple function pin output mode type is Open-drain mode. + * | | |Note: n=0, 1..15, Max. n=15. + * | | |Note: y= B, D, F, H, J, L, N + * |[21] |GPIOyMFOS21|GPIOy Pin[n] Multiple Function Pin Output Mode Select + * | | |This bit used to select multiple function pin output mode type for Py.n pin + * | | |0 = Multiple function pin output mode type is Push-pull mode. + * | | |1 = Multiple function pin output mode type is Open-drain mode. + * | | |Note: n=0, 1..15, Max. n=15. + * | | |Note: y= B, D, F, H, J, L, N + * |[22] |GPIOyMFOS22|GPIOy Pin[n] Multiple Function Pin Output Mode Select + * | | |This bit used to select multiple function pin output mode type for Py.n pin + * | | |0 = Multiple function pin output mode type is Push-pull mode. + * | | |1 = Multiple function pin output mode type is Open-drain mode. + * | | |Note: n=0, 1..15, Max. n=15. + * | | |Note: y= B, D, F, H, J, L, N + * |[23] |GPIOyMFOS23|GPIOy Pin[n] Multiple Function Pin Output Mode Select + * | | |This bit used to select multiple function pin output mode type for Py.n pin + * | | |0 = Multiple function pin output mode type is Push-pull mode. + * | | |1 = Multiple function pin output mode type is Open-drain mode. + * | | |Note: n=0, 1..15, Max. n=15. + * | | |Note: y= B, D, F, H, J, L, N + * |[24] |GPIOyMFOS24|GPIOy Pin[n] Multiple Function Pin Output Mode Select + * | | |This bit used to select multiple function pin output mode type for Py.n pin + * | | |0 = Multiple function pin output mode type is Push-pull mode. + * | | |1 = Multiple function pin output mode type is Open-drain mode. + * | | |Note: n=0, 1..15, Max. n=15. + * | | |Note: y= B, D, F, H, J, L, N + * |[25] |GPIOyMFOS25|GPIOy Pin[n] Multiple Function Pin Output Mode Select + * | | |This bit used to select multiple function pin output mode type for Py.n pin + * | | |0 = Multiple function pin output mode type is Push-pull mode. + * | | |1 = Multiple function pin output mode type is Open-drain mode. + * | | |Note: n=0, 1..15, Max. n=15. + * | | |Note: y= B, D, F, H, J, L, N + * |[26] |GPIOyMFOS26|GPIOy Pin[n] Multiple Function Pin Output Mode Select + * | | |This bit used to select multiple function pin output mode type for Py.n pin + * | | |0 = Multiple function pin output mode type is Push-pull mode. + * | | |1 = Multiple function pin output mode type is Open-drain mode. + * | | |Note: n=0, 1..15, Max. n=15. + * | | |Note: y= B, D, F, H, J, L, N + * |[27] |GPIOyMFOS27|GPIOy Pin[n] Multiple Function Pin Output Mode Select + * | | |This bit used to select multiple function pin output mode type for Py.n pin + * | | |0 = Multiple function pin output mode type is Push-pull mode. + * | | |1 = Multiple function pin output mode type is Open-drain mode. + * | | |Note: n=0, 1..15, Max. n=15. + * | | |Note: y= B, D, F, H, J, L, N + * |[28] |GPIOyMFOS28|GPIOy Pin[n] Multiple Function Pin Output Mode Select + * | | |This bit used to select multiple function pin output mode type for Py.n pin + * | | |0 = Multiple function pin output mode type is Push-pull mode. + * | | |1 = Multiple function pin output mode type is Open-drain mode. + * | | |Note: n=0, 1..15, Max. n=15. + * | | |Note: y= B, D, F, H, J, L, N + * |[29] |GPIOyMFOS29|GPIOy Pin[n] Multiple Function Pin Output Mode Select + * | | |This bit used to select multiple function pin output mode type for Py.n pin + * | | |0 = Multiple function pin output mode type is Push-pull mode. + * | | |1 = Multiple function pin output mode type is Open-drain mode. + * | | |Note: n=0, 1..15, Max. n=15. + * | | |Note: y= B, D, F, H, J, L, N + * |[30] |GPIOyMFOS30|GPIOy Pin[n] Multiple Function Pin Output Mode Select + * | | |This bit used to select multiple function pin output mode type for Py.n pin + * | | |0 = Multiple function pin output mode type is Push-pull mode. + * | | |1 = Multiple function pin output mode type is Open-drain mode. + * | | |Note: n=0, 1..15, Max. n=15. + * | | |Note: y= B, D, F, H, J, L, N + * |[31] |GPIOyMFOS31|GPIOy Pin[n] Multiple Function Pin Output Mode Select + * | | |This bit used to select multiple function pin output mode type for Py.n pin + * | | |0 = Multiple function pin output mode type is Push-pull mode. + * | | |1 = Multiple function pin output mode type is Open-drain mode. + * | | |Note: n=0, 1..15, Max. n=15. + * | | |Note: y= B, D, F, H, J, L, N + * @var SYS_T::GPKL_MFOS + * Offset: 0x154 GPIOK and GPIOL Multiple Function Output Mode Select Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[0] |GPIOxMFOS0|GPIOx Pin[m] Multiple Function Pin Output Mode Select + * | | |This bit used to select multiple function pin output mode type for Px.m pin + * | | |0 = Multiple function pin output mode type is Push-pull mode. + * | | |1 = Multiple function pin output mode type is Open-drain mode. + * | | |Note: Max. m=15. + * | | |Note: y= A, C, E, F, I, K, M + * |[1] |GPIOxMFOS1|GPIOx Pin[m] Multiple Function Pin Output Mode Select + * | | |This bit used to select multiple function pin output mode type for Px.m pin + * | | |0 = Multiple function pin output mode type is Push-pull mode. + * | | |1 = Multiple function pin output mode type is Open-drain mode. + * | | |Note: Max. m=15. + * | | |Note: y= A, C, E, F, I, K, M + * |[2] |GPIOxMFOS2|GPIOx Pin[m] Multiple Function Pin Output Mode Select + * | | |This bit used to select multiple function pin output mode type for Px.m pin + * | | |0 = Multiple function pin output mode type is Push-pull mode. + * | | |1 = Multiple function pin output mode type is Open-drain mode. + * | | |Note: Max. m=15. + * | | |Note: y= A, C, E, F, I, K, M + * |[3] |GPIOxMFOS3|GPIOx Pin[m] Multiple Function Pin Output Mode Select + * | | |This bit used to select multiple function pin output mode type for Px.m pin + * | | |0 = Multiple function pin output mode type is Push-pull mode. + * | | |1 = Multiple function pin output mode type is Open-drain mode. + * | | |Note: Max. m=15. + * | | |Note: y= A, C, E, F, I, K, M + * |[4] |GPIOxMFOS4|GPIOx Pin[m] Multiple Function Pin Output Mode Select + * | | |This bit used to select multiple function pin output mode type for Px.m pin + * | | |0 = Multiple function pin output mode type is Push-pull mode. + * | | |1 = Multiple function pin output mode type is Open-drain mode. + * | | |Note: Max. m=15. + * | | |Note: y= A, C, E, F, I, K, M + * |[5] |GPIOxMFOS5|GPIOx Pin[m] Multiple Function Pin Output Mode Select + * | | |This bit used to select multiple function pin output mode type for Px.m pin + * | | |0 = Multiple function pin output mode type is Push-pull mode. + * | | |1 = Multiple function pin output mode type is Open-drain mode. + * | | |Note: Max. m=15. + * | | |Note: y= A, C, E, F, I, K, M + * |[6] |GPIOxMFOS6|GPIOx Pin[m] Multiple Function Pin Output Mode Select + * | | |This bit used to select multiple function pin output mode type for Px.m pin + * | | |0 = Multiple function pin output mode type is Push-pull mode. + * | | |1 = Multiple function pin output mode type is Open-drain mode. + * | | |Note: Max. m=15. + * | | |Note: y= A, C, E, F, I, K, M + * |[7] |GPIOxMFOS7|GPIOx Pin[m] Multiple Function Pin Output Mode Select + * | | |This bit used to select multiple function pin output mode type for Px.m pin + * | | |0 = Multiple function pin output mode type is Push-pull mode. + * | | |1 = Multiple function pin output mode type is Open-drain mode. + * | | |Note: Max. m=15. + * | | |Note: y= A, C, E, F, I, K, M + * |[8] |GPIOxMFOS8|GPIOx Pin[m] Multiple Function Pin Output Mode Select + * | | |This bit used to select multiple function pin output mode type for Px.m pin + * | | |0 = Multiple function pin output mode type is Push-pull mode. + * | | |1 = Multiple function pin output mode type is Open-drain mode. + * | | |Note: Max. m=15. + * | | |Note: y= A, C, E, F, I, K, M + * |[9] |GPIOxMFOS9|GPIOx Pin[m] Multiple Function Pin Output Mode Select + * | | |This bit used to select multiple function pin output mode type for Px.m pin + * | | |0 = Multiple function pin output mode type is Push-pull mode. + * | | |1 = Multiple function pin output mode type is Open-drain mode. + * | | |Note: Max. m=15. + * | | |Note: y= A, C, E, F, I, K, M + * |[10] |GPIOxMFOS10|GPIOx Pin[m] Multiple Function Pin Output Mode Select + * | | |This bit used to select multiple function pin output mode type for Px.m pin + * | | |0 = Multiple function pin output mode type is Push-pull mode. + * | | |1 = Multiple function pin output mode type is Open-drain mode. + * | | |Note: Max. m=15. + * | | |Note: y= A, C, E, F, I, K, M + * |[11] |GPIOxMFOS11|GPIOx Pin[m] Multiple Function Pin Output Mode Select + * | | |This bit used to select multiple function pin output mode type for Px.m pin + * | | |0 = Multiple function pin output mode type is Push-pull mode. + * | | |1 = Multiple function pin output mode type is Open-drain mode. + * | | |Note: Max. m=15. + * | | |Note: y= A, C, E, F, I, K, M + * |[12] |GPIOxMFOS12|GPIOx Pin[m] Multiple Function Pin Output Mode Select + * | | |This bit used to select multiple function pin output mode type for Px.m pin + * | | |0 = Multiple function pin output mode type is Push-pull mode. + * | | |1 = Multiple function pin output mode type is Open-drain mode. + * | | |Note: Max. m=15. + * | | |Note: y= A, C, E, F, I, K, M + * |[13] |GPIOxMFOS13|GPIOx Pin[m] Multiple Function Pin Output Mode Select + * | | |This bit used to select multiple function pin output mode type for Px.m pin + * | | |0 = Multiple function pin output mode type is Push-pull mode. + * | | |1 = Multiple function pin output mode type is Open-drain mode. + * | | |Note: Max. m=15. + * | | |Note: y= A, C, E, F, I, K, M + * |[14] |GPIOxMFOS14|GPIOx Pin[m] Multiple Function Pin Output Mode Select + * | | |This bit used to select multiple function pin output mode type for Px.m pin + * | | |0 = Multiple function pin output mode type is Push-pull mode. + * | | |1 = Multiple function pin output mode type is Open-drain mode. + * | | |Note: Max. m=15. + * | | |Note: y= A, C, E, F, I, K, M + * |[15] |GPIOxMFOS15|GPIOx Pin[m] Multiple Function Pin Output Mode Select + * | | |This bit used to select multiple function pin output mode type for Px.m pin + * | | |0 = Multiple function pin output mode type is Push-pull mode. + * | | |1 = Multiple function pin output mode type is Open-drain mode. + * | | |Note: Max. m=15. + * | | |Note: y= A, C, E, F, I, K, M + * |[16] |GPIOyMFOS16|GPIOy Pin[n] Multiple Function Pin Output Mode Select + * | | |This bit used to select multiple function pin output mode type for Py.n pin + * | | |0 = Multiple function pin output mode type is Push-pull mode. + * | | |1 = Multiple function pin output mode type is Open-drain mode. + * | | |Note: n=0, 1..15, Max. n=15. + * | | |Note: y= B, D, F, H, J, L, N + * |[17] |GPIOyMFOS17|GPIOy Pin[n] Multiple Function Pin Output Mode Select + * | | |This bit used to select multiple function pin output mode type for Py.n pin + * | | |0 = Multiple function pin output mode type is Push-pull mode. + * | | |1 = Multiple function pin output mode type is Open-drain mode. + * | | |Note: n=0, 1..15, Max. n=15. + * | | |Note: y= B, D, F, H, J, L, N + * |[18] |GPIOyMFOS18|GPIOy Pin[n] Multiple Function Pin Output Mode Select + * | | |This bit used to select multiple function pin output mode type for Py.n pin + * | | |0 = Multiple function pin output mode type is Push-pull mode. + * | | |1 = Multiple function pin output mode type is Open-drain mode. + * | | |Note: n=0, 1..15, Max. n=15. + * | | |Note: y= B, D, F, H, J, L, N + * |[19] |GPIOyMFOS19|GPIOy Pin[n] Multiple Function Pin Output Mode Select + * | | |This bit used to select multiple function pin output mode type for Py.n pin + * | | |0 = Multiple function pin output mode type is Push-pull mode. + * | | |1 = Multiple function pin output mode type is Open-drain mode. + * | | |Note: n=0, 1..15, Max. n=15. + * | | |Note: y= B, D, F, H, J, L, N + * |[20] |GPIOyMFOS20|GPIOy Pin[n] Multiple Function Pin Output Mode Select + * | | |This bit used to select multiple function pin output mode type for Py.n pin + * | | |0 = Multiple function pin output mode type is Push-pull mode. + * | | |1 = Multiple function pin output mode type is Open-drain mode. + * | | |Note: n=0, 1..15, Max. n=15. + * | | |Note: y= B, D, F, H, J, L, N + * |[21] |GPIOyMFOS21|GPIOy Pin[n] Multiple Function Pin Output Mode Select + * | | |This bit used to select multiple function pin output mode type for Py.n pin + * | | |0 = Multiple function pin output mode type is Push-pull mode. + * | | |1 = Multiple function pin output mode type is Open-drain mode. + * | | |Note: n=0, 1..15, Max. n=15. + * | | |Note: y= B, D, F, H, J, L, N + * |[22] |GPIOyMFOS22|GPIOy Pin[n] Multiple Function Pin Output Mode Select + * | | |This bit used to select multiple function pin output mode type for Py.n pin + * | | |0 = Multiple function pin output mode type is Push-pull mode. + * | | |1 = Multiple function pin output mode type is Open-drain mode. + * | | |Note: n=0, 1..15, Max. n=15. + * | | |Note: y= B, D, F, H, J, L, N + * |[23] |GPIOyMFOS23|GPIOy Pin[n] Multiple Function Pin Output Mode Select + * | | |This bit used to select multiple function pin output mode type for Py.n pin + * | | |0 = Multiple function pin output mode type is Push-pull mode. + * | | |1 = Multiple function pin output mode type is Open-drain mode. + * | | |Note: n=0, 1..15, Max. n=15. + * | | |Note: y= B, D, F, H, J, L, N + * |[24] |GPIOyMFOS24|GPIOy Pin[n] Multiple Function Pin Output Mode Select + * | | |This bit used to select multiple function pin output mode type for Py.n pin + * | | |0 = Multiple function pin output mode type is Push-pull mode. + * | | |1 = Multiple function pin output mode type is Open-drain mode. + * | | |Note: n=0, 1..15, Max. n=15. + * | | |Note: y= B, D, F, H, J, L, N + * |[25] |GPIOyMFOS25|GPIOy Pin[n] Multiple Function Pin Output Mode Select + * | | |This bit used to select multiple function pin output mode type for Py.n pin + * | | |0 = Multiple function pin output mode type is Push-pull mode. + * | | |1 = Multiple function pin output mode type is Open-drain mode. + * | | |Note: n=0, 1..15, Max. n=15. + * | | |Note: y= B, D, F, H, J, L, N + * |[26] |GPIOyMFOS26|GPIOy Pin[n] Multiple Function Pin Output Mode Select + * | | |This bit used to select multiple function pin output mode type for Py.n pin + * | | |0 = Multiple function pin output mode type is Push-pull mode. + * | | |1 = Multiple function pin output mode type is Open-drain mode. + * | | |Note: n=0, 1..15, Max. n=15. + * | | |Note: y= B, D, F, H, J, L, N + * |[27] |GPIOyMFOS27|GPIOy Pin[n] Multiple Function Pin Output Mode Select + * | | |This bit used to select multiple function pin output mode type for Py.n pin + * | | |0 = Multiple function pin output mode type is Push-pull mode. + * | | |1 = Multiple function pin output mode type is Open-drain mode. + * | | |Note: n=0, 1..15, Max. n=15. + * | | |Note: y= B, D, F, H, J, L, N + * |[28] |GPIOyMFOS28|GPIOy Pin[n] Multiple Function Pin Output Mode Select + * | | |This bit used to select multiple function pin output mode type for Py.n pin + * | | |0 = Multiple function pin output mode type is Push-pull mode. + * | | |1 = Multiple function pin output mode type is Open-drain mode. + * | | |Note: n=0, 1..15, Max. n=15. + * | | |Note: y= B, D, F, H, J, L, N + * |[29] |GPIOyMFOS29|GPIOy Pin[n] Multiple Function Pin Output Mode Select + * | | |This bit used to select multiple function pin output mode type for Py.n pin + * | | |0 = Multiple function pin output mode type is Push-pull mode. + * | | |1 = Multiple function pin output mode type is Open-drain mode. + * | | |Note: n=0, 1..15, Max. n=15. + * | | |Note: y= B, D, F, H, J, L, N + * |[30] |GPIOyMFOS30|GPIOy Pin[n] Multiple Function Pin Output Mode Select + * | | |This bit used to select multiple function pin output mode type for Py.n pin + * | | |0 = Multiple function pin output mode type is Push-pull mode. + * | | |1 = Multiple function pin output mode type is Open-drain mode. + * | | |Note: n=0, 1..15, Max. n=15. + * | | |Note: y= B, D, F, H, J, L, N + * |[31] |GPIOyMFOS31|GPIOy Pin[n] Multiple Function Pin Output Mode Select + * | | |This bit used to select multiple function pin output mode type for Py.n pin + * | | |0 = Multiple function pin output mode type is Push-pull mode. + * | | |1 = Multiple function pin output mode type is Open-drain mode. + * | | |Note: n=0, 1..15, Max. n=15. + * | | |Note: y= B, D, F, H, J, L, N + * @var SYS_T::GPMN_MFOS + * Offset: 0x158 GPIOM and GPION Multiple Function Output Mode Select Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[0] |GPIOxMFOS0|GPIOx Pin[m] Multiple Function Pin Output Mode Select + * | | |This bit used to select multiple function pin output mode type for Px.m pin + * | | |0 = Multiple function pin output mode type is Push-pull mode. + * | | |1 = Multiple function pin output mode type is Open-drain mode. + * | | |Note: Max. m=15. + * | | |Note: y= A, C, E, F, I, K, M + * |[1] |GPIOxMFOS1|GPIOx Pin[m] Multiple Function Pin Output Mode Select + * | | |This bit used to select multiple function pin output mode type for Px.m pin + * | | |0 = Multiple function pin output mode type is Push-pull mode. + * | | |1 = Multiple function pin output mode type is Open-drain mode. + * | | |Note: Max. m=15. + * | | |Note: y= A, C, E, F, I, K, M + * |[2] |GPIOxMFOS2|GPIOx Pin[m] Multiple Function Pin Output Mode Select + * | | |This bit used to select multiple function pin output mode type for Px.m pin + * | | |0 = Multiple function pin output mode type is Push-pull mode. + * | | |1 = Multiple function pin output mode type is Open-drain mode. + * | | |Note: Max. m=15. + * | | |Note: y= A, C, E, F, I, K, M + * |[3] |GPIOxMFOS3|GPIOx Pin[m] Multiple Function Pin Output Mode Select + * | | |This bit used to select multiple function pin output mode type for Px.m pin + * | | |0 = Multiple function pin output mode type is Push-pull mode. + * | | |1 = Multiple function pin output mode type is Open-drain mode. + * | | |Note: Max. m=15. + * | | |Note: y= A, C, E, F, I, K, M + * |[4] |GPIOxMFOS4|GPIOx Pin[m] Multiple Function Pin Output Mode Select + * | | |This bit used to select multiple function pin output mode type for Px.m pin + * | | |0 = Multiple function pin output mode type is Push-pull mode. + * | | |1 = Multiple function pin output mode type is Open-drain mode. + * | | |Note: Max. m=15. + * | | |Note: y= A, C, E, F, I, K, M + * |[5] |GPIOxMFOS5|GPIOx Pin[m] Multiple Function Pin Output Mode Select + * | | |This bit used to select multiple function pin output mode type for Px.m pin + * | | |0 = Multiple function pin output mode type is Push-pull mode. + * | | |1 = Multiple function pin output mode type is Open-drain mode. + * | | |Note: Max. m=15. + * | | |Note: y= A, C, E, F, I, K, M + * |[6] |GPIOxMFOS6|GPIOx Pin[m] Multiple Function Pin Output Mode Select + * | | |This bit used to select multiple function pin output mode type for Px.m pin + * | | |0 = Multiple function pin output mode type is Push-pull mode. + * | | |1 = Multiple function pin output mode type is Open-drain mode. + * | | |Note: Max. m=15. + * | | |Note: y= A, C, E, F, I, K, M + * |[7] |GPIOxMFOS7|GPIOx Pin[m] Multiple Function Pin Output Mode Select + * | | |This bit used to select multiple function pin output mode type for Px.m pin + * | | |0 = Multiple function pin output mode type is Push-pull mode. + * | | |1 = Multiple function pin output mode type is Open-drain mode. + * | | |Note: Max. m=15. + * | | |Note: y= A, C, E, F, I, K, M + * |[8] |GPIOxMFOS8|GPIOx Pin[m] Multiple Function Pin Output Mode Select + * | | |This bit used to select multiple function pin output mode type for Px.m pin + * | | |0 = Multiple function pin output mode type is Push-pull mode. + * | | |1 = Multiple function pin output mode type is Open-drain mode. + * | | |Note: Max. m=15. + * | | |Note: y= A, C, E, F, I, K, M + * |[9] |GPIOxMFOS9|GPIOx Pin[m] Multiple Function Pin Output Mode Select + * | | |This bit used to select multiple function pin output mode type for Px.m pin + * | | |0 = Multiple function pin output mode type is Push-pull mode. + * | | |1 = Multiple function pin output mode type is Open-drain mode. + * | | |Note: Max. m=15. + * | | |Note: y= A, C, E, F, I, K, M + * |[10] |GPIOxMFOS10|GPIOx Pin[m] Multiple Function Pin Output Mode Select + * | | |This bit used to select multiple function pin output mode type for Px.m pin + * | | |0 = Multiple function pin output mode type is Push-pull mode. + * | | |1 = Multiple function pin output mode type is Open-drain mode. + * | | |Note: Max. m=15. + * | | |Note: y= A, C, E, F, I, K, M + * |[11] |GPIOxMFOS11|GPIOx Pin[m] Multiple Function Pin Output Mode Select + * | | |This bit used to select multiple function pin output mode type for Px.m pin + * | | |0 = Multiple function pin output mode type is Push-pull mode. + * | | |1 = Multiple function pin output mode type is Open-drain mode. + * | | |Note: Max. m=15. + * | | |Note: y= A, C, E, F, I, K, M + * |[12] |GPIOxMFOS12|GPIOx Pin[m] Multiple Function Pin Output Mode Select + * | | |This bit used to select multiple function pin output mode type for Px.m pin + * | | |0 = Multiple function pin output mode type is Push-pull mode. + * | | |1 = Multiple function pin output mode type is Open-drain mode. + * | | |Note: Max. m=15. + * | | |Note: y= A, C, E, F, I, K, M + * |[13] |GPIOxMFOS13|GPIOx Pin[m] Multiple Function Pin Output Mode Select + * | | |This bit used to select multiple function pin output mode type for Px.m pin + * | | |0 = Multiple function pin output mode type is Push-pull mode. + * | | |1 = Multiple function pin output mode type is Open-drain mode. + * | | |Note: Max. m=15. + * | | |Note: y= A, C, E, F, I, K, M + * |[14] |GPIOxMFOS14|GPIOx Pin[m] Multiple Function Pin Output Mode Select + * | | |This bit used to select multiple function pin output mode type for Px.m pin + * | | |0 = Multiple function pin output mode type is Push-pull mode. + * | | |1 = Multiple function pin output mode type is Open-drain mode. + * | | |Note: Max. m=15. + * | | |Note: y= A, C, E, F, I, K, M + * |[15] |GPIOxMFOS15|GPIOx Pin[m] Multiple Function Pin Output Mode Select + * | | |This bit used to select multiple function pin output mode type for Px.m pin + * | | |0 = Multiple function pin output mode type is Push-pull mode. + * | | |1 = Multiple function pin output mode type is Open-drain mode. + * | | |Note: Max. m=15. + * | | |Note: y= A, C, E, F, I, K, M + * |[16] |GPIOyMFOS16|GPIOy Pin[n] Multiple Function Pin Output Mode Select + * | | |This bit used to select multiple function pin output mode type for Py.n pin + * | | |0 = Multiple function pin output mode type is Push-pull mode. + * | | |1 = Multiple function pin output mode type is Open-drain mode. + * | | |Note: n=0, 1..15, Max. n=15. + * | | |Note: y= B, D, F, H, J, L, N + * |[17] |GPIOyMFOS17|GPIOy Pin[n] Multiple Function Pin Output Mode Select + * | | |This bit used to select multiple function pin output mode type for Py.n pin + * | | |0 = Multiple function pin output mode type is Push-pull mode. + * | | |1 = Multiple function pin output mode type is Open-drain mode. + * | | |Note: n=0, 1..15, Max. n=15. + * | | |Note: y= B, D, F, H, J, L, N + * |[18] |GPIOyMFOS18|GPIOy Pin[n] Multiple Function Pin Output Mode Select + * | | |This bit used to select multiple function pin output mode type for Py.n pin + * | | |0 = Multiple function pin output mode type is Push-pull mode. + * | | |1 = Multiple function pin output mode type is Open-drain mode. + * | | |Note: n=0, 1..15, Max. n=15. + * | | |Note: y= B, D, F, H, J, L, N + * |[19] |GPIOyMFOS19|GPIOy Pin[n] Multiple Function Pin Output Mode Select + * | | |This bit used to select multiple function pin output mode type for Py.n pin + * | | |0 = Multiple function pin output mode type is Push-pull mode. + * | | |1 = Multiple function pin output mode type is Open-drain mode. + * | | |Note: n=0, 1..15, Max. n=15. + * | | |Note: y= B, D, F, H, J, L, N + * |[20] |GPIOyMFOS20|GPIOy Pin[n] Multiple Function Pin Output Mode Select + * | | |This bit used to select multiple function pin output mode type for Py.n pin + * | | |0 = Multiple function pin output mode type is Push-pull mode. + * | | |1 = Multiple function pin output mode type is Open-drain mode. + * | | |Note: n=0, 1..15, Max. n=15. + * | | |Note: y= B, D, F, H, J, L, N + * |[21] |GPIOyMFOS21|GPIOy Pin[n] Multiple Function Pin Output Mode Select + * | | |This bit used to select multiple function pin output mode type for Py.n pin + * | | |0 = Multiple function pin output mode type is Push-pull mode. + * | | |1 = Multiple function pin output mode type is Open-drain mode. + * | | |Note: n=0, 1..15, Max. n=15. + * | | |Note: y= B, D, F, H, J, L, N + * |[22] |GPIOyMFOS22|GPIOy Pin[n] Multiple Function Pin Output Mode Select + * | | |This bit used to select multiple function pin output mode type for Py.n pin + * | | |0 = Multiple function pin output mode type is Push-pull mode. + * | | |1 = Multiple function pin output mode type is Open-drain mode. + * | | |Note: n=0, 1..15, Max. n=15. + * | | |Note: y= B, D, F, H, J, L, N + * |[23] |GPIOyMFOS23|GPIOy Pin[n] Multiple Function Pin Output Mode Select + * | | |This bit used to select multiple function pin output mode type for Py.n pin + * | | |0 = Multiple function pin output mode type is Push-pull mode. + * | | |1 = Multiple function pin output mode type is Open-drain mode. + * | | |Note: n=0, 1..15, Max. n=15. + * | | |Note: y= B, D, F, H, J, L, N + * |[24] |GPIOyMFOS24|GPIOy Pin[n] Multiple Function Pin Output Mode Select + * | | |This bit used to select multiple function pin output mode type for Py.n pin + * | | |0 = Multiple function pin output mode type is Push-pull mode. + * | | |1 = Multiple function pin output mode type is Open-drain mode. + * | | |Note: n=0, 1..15, Max. n=15. + * | | |Note: y= B, D, F, H, J, L, N + * |[25] |GPIOyMFOS25|GPIOy Pin[n] Multiple Function Pin Output Mode Select + * | | |This bit used to select multiple function pin output mode type for Py.n pin + * | | |0 = Multiple function pin output mode type is Push-pull mode. + * | | |1 = Multiple function pin output mode type is Open-drain mode. + * | | |Note: n=0, 1..15, Max. n=15. + * | | |Note: y= B, D, F, H, J, L, N + * |[26] |GPIOyMFOS26|GPIOy Pin[n] Multiple Function Pin Output Mode Select + * | | |This bit used to select multiple function pin output mode type for Py.n pin + * | | |0 = Multiple function pin output mode type is Push-pull mode. + * | | |1 = Multiple function pin output mode type is Open-drain mode. + * | | |Note: n=0, 1..15, Max. n=15. + * | | |Note: y= B, D, F, H, J, L, N + * |[27] |GPIOyMFOS27|GPIOy Pin[n] Multiple Function Pin Output Mode Select + * | | |This bit used to select multiple function pin output mode type for Py.n pin + * | | |0 = Multiple function pin output mode type is Push-pull mode. + * | | |1 = Multiple function pin output mode type is Open-drain mode. + * | | |Note: n=0, 1..15, Max. n=15. + * | | |Note: y= B, D, F, H, J, L, N + * |[28] |GPIOyMFOS28|GPIOy Pin[n] Multiple Function Pin Output Mode Select + * | | |This bit used to select multiple function pin output mode type for Py.n pin + * | | |0 = Multiple function pin output mode type is Push-pull mode. + * | | |1 = Multiple function pin output mode type is Open-drain mode. + * | | |Note: n=0, 1..15, Max. n=15. + * | | |Note: y= B, D, F, H, J, L, N + * |[29] |GPIOyMFOS29|GPIOy Pin[n] Multiple Function Pin Output Mode Select + * | | |This bit used to select multiple function pin output mode type for Py.n pin + * | | |0 = Multiple function pin output mode type is Push-pull mode. + * | | |1 = Multiple function pin output mode type is Open-drain mode. + * | | |Note: n=0, 1..15, Max. n=15. + * | | |Note: y= B, D, F, H, J, L, N + * |[30] |GPIOyMFOS30|GPIOy Pin[n] Multiple Function Pin Output Mode Select + * | | |This bit used to select multiple function pin output mode type for Py.n pin + * | | |0 = Multiple function pin output mode type is Push-pull mode. + * | | |1 = Multiple function pin output mode type is Open-drain mode. + * | | |Note: n=0, 1..15, Max. n=15. + * | | |Note: y= B, D, F, H, J, L, N + * |[31] |GPIOyMFOS31|GPIOy Pin[n] Multiple Function Pin Output Mode Select + * | | |This bit used to select multiple function pin output mode type for Py.n pin + * | | |0 = Multiple function pin output mode type is Push-pull mode. + * | | |1 = Multiple function pin output mode type is Open-drain mode. + * | | |Note: n=0, 1..15, Max. n=15. + * | | |Note: y= B, D, F, H, J, L, N + * @var SYS_T::UID0 + * Offset: 0x180 Unique Identifier Word 0 Register (TZNS) + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[31:0] |UID |Unique ID + * | | |Unique identify number of the chip. + * | | |Loaded from OTP automatically during chip power on. + * @var SYS_T::UID1 + * Offset: 0x184 Unique Identifier Word 1 Register (TZNS) + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[31:0] |UID |Unique ID + * | | |Unique identify number of the chip. + * | | |Loaded from OTP automatically during chip power on. + * @var SYS_T::UID2 + * Offset: 0x188 Unique Identifier Word 2 Register (TZNS) + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[31:0] |UID |Unique ID + * | | |Unique identify number of the chip. + * | | |Loaded from OTP automatically during chip power on. + * @var SYS_T::UCID0 + * Offset: 0x190 Unique Customer Identifier Word 0 Register (TZNS) + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[31:0] |UCID |Unique Customer ID + * | | |Unique customer identifier number of the chip. + * | | |Loaded from OTP automatically during chip power on. + * @var SYS_T::UCID1 + * Offset: 0x194 Unique Customer Identifier Word 1 Register (TZNS) + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[31:0] |UCID |Unique Customer ID + * | | |Unique customer identifier number of the chip. + * | | |Loaded from OTP automatically during chip power on. + * @var SYS_T::UCID2 + * Offset: 0x198 Unique Customer Identifier Word 2 Register (TZNS) + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[31:0] |UCID |Unique Customer ID + * | | |Unique customer identifier number of the chip. + * | | |Loaded from OTP automatically during chip power on. + * @var SYS_T::RLKTZS + * Offset: 0x1A0 TZS Register Lock Control Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[7:0] |REGLCTL |Register Lock Control Code (Write Only) + * | | |Some registers have write-protection function + * | | |Writing these registers have to disable the protected function by writing the sequence value "59h", "16h", "88h" to this field + * | | |After this sequence is completed, the REGLCTL bit will be set to 1 and write-protection registers can be normal write. + * | | |REGLCTL[0] + * | | |Register Lock Control Disable Index (Read Only) + * | | |0 = Write-protection Enabled for writing protected registers + * | | |Any write to the protected register is ignored. + * | | |1 = Write-protection Disabled for writing protected registers. + * @var SYS_T::RLKTZNS + * Offset: 0x1A4 TZNS Register Lock Control Register (TZNS) + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[7:0] |REGLCTL |Register Lock Control Code (Write Only) + * | | |Some registers have write-protection function + * | | |Writing these registers have to disable the protected function by writing the sequence value "59h", "16h", "88h" to this field + * | | |After this sequence is completed, the REGLCTL bit will be set to 1 and write-protection registers can be normal write. + * | | |REGLCTL[0] + * | | |Register Lock Control Disable Index (Read Only) + * | | |0 = Write-protection Enabled for writing protected registers + * | | |Any write to the protected register is ignored. + * | | |1 = Write-protection Disabled for writing protected registers. + * @var SYS_T::RLKSUBM + * Offset: 0x1A8 SUBM Register Lock Control Register (SUBM) + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[7:0] |REGLCTL |Register Lock Control Code (Write Only) + * | | |Some registers have write-protection function + * | | |Writing these registers have to disable the protected function by writing the sequence value "59h", "16h", "88h" to this field + * | | |After this sequence is completed, the REGLCTL bit will be set to 1 and write-protection registers can be normal write. + * | | |REGLCTL[0] + * | | |Register Lock Control Disable Index (Read Only) + * | | |0 = Write-protection Enabled for writing protected registers + * | | |Any write to the protected register is ignored. + * | | |1 = Write-protection Disabled for writing protected registers. + */ + __I uint32_t PDID; /*!< [0x0000] Product and Device Identifier Register (TZNS) */ + __I uint32_t PWRONOTP; /*!< [0x0004] Power-on Setting OTP Source Register (TZNS) */ + __I uint32_t PWRONPIN; /*!< [0x0008] Power-on Setting Pin Source Register (TZNS) */ + __I uint32_t RESERVE0[1]; + __IO uint32_t RSTSTS; /*!< [0x0010] Reset Source Active Status Register (Shared) */ + __IO uint32_t MISCRFCR; /*!< [0x0014] Miscellaneous Reset Function Control Register */ + __IO uint32_t RSTDEBCTL; /*!< [0x0018] Reset Pin De-bounce Control Register */ + __IO uint32_t LVRDCR; /*!< [0x001c] Low Voltage Reset & Detect Control Register */ + __IO uint32_t IPRST0; /*!< [0x0020] Reset Control Register 0 (Shared) */ + __IO uint32_t IPRST1; /*!< [0x0024] Reset Control Register 1 (Shared) */ + __IO uint32_t IPRST2; /*!< [0x0028] Reset Control Register 2 (Shared) */ + __IO uint32_t IPRST3; /*!< [0x002c] Reset Control Register 3 (Shared) */ + __IO uint32_t PMUCR; /*!< [0x0030] Power Management Unit Control Register */ + __IO uint32_t DDRCQCSR; /*!< [0x0034] DDR Controller Q Channel Control and Status Register */ + __IO uint32_t PMUIEN; /*!< [0x0038] Power Management Unit Interrupt Enable Register */ + __IO uint32_t PMUSTS; /*!< [0x003c] Power Management Unit Status Register */ + __IO uint32_t CA35WRBADR0; /*!< [0x0040] Cortexu00AE-A35 Core 0 Warm-boot Address Register */ + __IO uint32_t CA35WRBPAR0; /*!< [0x0044] Cortexu00AE-A35 Core 0 Warm-boot Parameter Register */ + __IO uint32_t CA35WRBADR1; /*!< [0x0048] Cortexu00AE-A35 Core 1 Warm-boot Address Register */ + __IO uint32_t CA35WRBPAR1; /*!< [0x004c] Cortexu00AE-A35 Core 1 Warm-boot Parameter Register */ + __I uint32_t RESERVE1[4]; + __IO uint32_t USBPMISCR; /*!< [0x0060] USB PHY Miscellaneous Control Register (TZNS) */ + __IO uint32_t USBP0PCR; /*!< [0x0064] USB Port 0 PHY Control Register */ + __IO uint32_t USBP1PCR; /*!< [0x0068] USB Port 1 PHY Control Register (TZNS) */ + __I uint32_t RESERVE2[1]; + __IO uint32_t MISCFCR0; /*!< [0x0070] Miscellaneous Function Control Register 0 (Shared) */ + __IO uint32_t MISCFCR1; /*!< [0x0074] Miscellaneous Function Control Register 1 (Shared) */ + __IO uint32_t MISCIER; /*!< [0x0078] Miscellaneous Interrupt Enable Register (TZNS) */ + __IO uint32_t MISCISR; /*!< [0x007c] Miscellaneous Interrupt Status Register (TZNS) */ + __IO uint32_t GPA_MFPL; /*!< [0x0080] GPIOA Low Byte Multiple Function Control Register */ + __IO uint32_t GPA_MFPH; /*!< [0x0084] GPIOA High Byte Multiple Function Control Register */ + __IO uint32_t GPB_MFPL; /*!< [0x0088] GPIOB Low Byte Multiple Function Control Register */ + __IO uint32_t GPB_MFPH; /*!< [0x008c] GPIOB High Byte Multiple Function Control Register */ + __IO uint32_t GPC_MFPL; /*!< [0x0090] GPIOC Low Byte Multiple Function Control Register */ + __IO uint32_t GPC_MFPH; /*!< [0x0094] GPIOC High Byte Multiple Function Control Register */ + __IO uint32_t GPD_MFPL; /*!< [0x0098] GPIOD Low Byte Multiple Function Control Register */ + __IO uint32_t GPD_MFPH; /*!< [0x009c] GPIOD High Byte Multiple Function Control Register */ + __IO uint32_t GPE_MFPL; /*!< [0x00a0] GPIOE Low Byte Multiple Function Control Register */ + __IO uint32_t GPE_MFPH; /*!< [0x00a4] GPIOE High Byte Multiple Function Control Register */ + __IO uint32_t GPF_MFPL; /*!< [0x00a8] GPIOF Low Byte Multiple Function Control Register */ + __IO uint32_t GPF_MFPH; /*!< [0x00ac] GPIOF High Byte Multiple Function Control Register */ + __IO uint32_t GPG_MFPL; /*!< [0x00b0] GPIOG Low Byte Multiple Function Control Register */ + __IO uint32_t GPG_MFPH; /*!< [0x00b4] GPIOG High Byte Multiple Function Control Register */ + __IO uint32_t GPH_MFPL; /*!< [0x00b8] GPIOH Low Byte Multiple Function Control Register */ + __IO uint32_t GPH_MFPH; /*!< [0x00bc] GPIOH High Byte Multiple Function Control Register */ + __IO uint32_t GPI_MFPL; /*!< [0x00c0] GPIOI Low Byte Multiple Function Control Register */ + __IO uint32_t GPI_MFPH; /*!< [0x00c4] GPIOI High Byte Multiple Function Control Register */ + __IO uint32_t GPJ_MFPL; /*!< [0x00c8] GPIOJ Low Byte Multiple Function Control Register */ + __IO uint32_t GPJ_MFPH; /*!< [0x00cc] GPIOJ High Byte Multiple Function Control Register */ + __IO uint32_t GPK_MFPL; /*!< [0x00d0] GPIOK Low Byte Multiple Function Control Register */ + __IO uint32_t GPK_MFPH; /*!< [0x00d4] GPIOK High Byte Multiple Function Control Register */ + __IO uint32_t GPL_MFPL; /*!< [0x00d8] GPIOL Low Byte Multiple Function Control Register */ + __IO uint32_t GPL_MFPH; /*!< [0x00dc] GPIOL High Byte Multiple Function Control Register */ + __IO uint32_t GPM_MFPL; /*!< [0x00e0] GPIOM Low Byte Multiple Function Control Register */ + __IO uint32_t GPM_MFPH; /*!< [0x00e4] GPIOM High Byte Multiple Function Control Register */ + __IO uint32_t GPN_MFPL; /*!< [0x00e8] GPION Low Byte Multiple Function Control Register */ + __IO uint32_t GPN_MFPH; /*!< [0x00ec] GPION High Byte Multiple Function Control Register */ + __I uint32_t RESERVE3[5]; + __IO uint32_t TSENSRFCR; /*!< [0x0104] Temperature Sensor Function Control Register */ + __IO uint32_t GMAC0MISCR; /*!< [0x0108] GMAC 0 Miscellaneous Control Register (TZNS) */ + __IO uint32_t GMAC1MISCR; /*!< [0x010c] GMAC 1 Miscellaneous Control Register (TZNS) */ + __I uint32_t MACAD0LSR; /*!< [0x0110] MAC Address 0 Low Significant Word Register (TZNS) */ + __I uint32_t MACAD0HSR; /*!< [0x0114] MAC Address 0 High Significant Word Register (TZNS) */ + __I uint32_t MACAD1LSR; /*!< [0x0118] MAC Address 1 Low Significant Word Register (TZNS) */ + __I uint32_t MACAD1HSR; /*!< [0x011c] MAC Address 1 High Significant Word Register (TZNS) */ + __IO uint32_t CSDBGCTL; /*!< [0x0120] CoreSight Debug Control Register */ + __I uint32_t RESERVE4[7]; + __IO uint32_t GPAB_MFOS; /*!< [0x0140] GPIOA and GPIOB Multiple Function Output Mode Select Register */ + __IO uint32_t GPCD_MFOS; /*!< [0x0144] GPIOC and GPIOD Multiple Function Output Mode Select Register */ + __IO uint32_t GPEF_MFOS; /*!< [0x0148] GPIOE and GPIOF Multiple Function Output Mode Select Register */ + __IO uint32_t GPGH_MFOS; /*!< [0x014c] GPIOG and GPIOH Multiple Function Output Mode Select Register */ + __IO uint32_t GPIJ_MFOS; /*!< [0x0150] GPIOI and GPIOJ Multiple Function Output Mode Select Register */ + __IO uint32_t GPKL_MFOS; /*!< [0x0154] GPIOK and GPIOL Multiple Function Output Mode Select Register */ + __IO uint32_t GPMN_MFOS; /*!< [0x0158] GPIOM and GPION Multiple Function Output Mode Select Register */ + __I uint32_t RESERVE5[9]; + __I uint32_t UID0; /*!< [0x0180] Unique Identifier Word 0 Register (TZNS) */ + __I uint32_t UID1; /*!< [0x0184] Unique Identifier Word 1 Register (TZNS) */ + __I uint32_t UID2; /*!< [0x0188] Unique Identifier Word 2 Register (TZNS) */ + __I uint32_t RESERVE6[1]; + __I uint32_t UCID0; /*!< [0x0190] Unique Customer Identifier Word 0 Register (TZNS) */ + __I uint32_t UCID1; /*!< [0x0194] Unique Customer Identifier Word 1 Register (TZNS) */ + __I uint32_t UCID2; /*!< [0x0198] Unique Customer Identifier Word 2 Register (TZNS) */ + __I uint32_t RESERVE7[1]; + __O uint32_t RLKTZS; /*!< [0x01a0] TZS Register Lock Control Register */ + __O uint32_t RLKTZNS; /*!< [0x01a4] TZNS Register Lock Control Register (TZNS) */ + __O uint32_t RLKSUBM; /*!< [0x01a8] SUBM Register Lock Control Register (SUBM) */ + +} SYS_T; + +/** + @addtogroup SYS_CONST SYS Bit Field Definition + Constant Definitions for SYS Controller +@{ */ + +#define SYS_PDID_PID_Pos (0) /*!< SYS_T::PDID: PID Position */ +#define SYS_PDID_PID_Msk (0xfffful << SYS_PDID_PID_Pos) /*!< SYS_T::PDID: PID Mask */ + +#define SYS_PDID_DID_Pos (16) /*!< SYS_T::PDID: DID Position */ +#define SYS_PDID_DID_Msk (0xffful << SYS_PDID_DID_Pos) /*!< SYS_T::PDID: DID Mask */ + +#define SYS_PWRONOTP_PWRONSRC_Pos (0) /*!< SYS_T::PWRONOTP: PWRONSRC Position */ +#define SYS_PWRONOTP_PWRONSRC_Msk (0x1ul << SYS_PWRONOTP_PWRONSRC_Pos) /*!< SYS_T::PWRONOTP: PWRONSRC Mask */ + +#define SYS_PWRONOTP_QSPI0CKSEL_Pos (1) /*!< SYS_T::PWRONOTP: QSPI0CKSEL Position */ +#define SYS_PWRONOTP_QSPI0CKSEL_Msk (0x1ul << SYS_PWRONOTP_QSPI0CKSEL_Pos) /*!< SYS_T::PWRONOTP: QSPI0CKSEL Mask */ + +#define SYS_PWRONOTP_WDT0ON_Pos (2) /*!< SYS_T::PWRONOTP: WDT0ON Position */ +#define SYS_PWRONOTP_WDT0ON_Msk (0x1ul << SYS_PWRONOTP_WDT0ON_Pos) /*!< SYS_T::PWRONOTP: WDT0ON Mask */ + +#define SYS_PWRONOTP_UR0DBGDIS_Pos (4) /*!< SYS_T::PWRONOTP: UR0DBGDIS Position */ +#define SYS_PWRONOTP_UR0DBGDIS_Msk (0x1ul << SYS_PWRONOTP_UR0DBGDIS_Pos) /*!< SYS_T::PWRONOTP: UR0DBGDIS Mask */ + +#define SYS_PWRONOTP_SD0BKEN_Pos (5) /*!< SYS_T::PWRONOTP: SD0BKEN Position */ +#define SYS_PWRONOTP_SD0BKEN_Msk (0x1ul << SYS_PWRONOTP_SD0BKEN_Pos) /*!< SYS_T::PWRONOTP: SD0BKEN Mask */ + +#define SYS_PWRONOTP_BTSRCSEL_Pos (10) /*!< SYS_T::PWRONOTP: BTSRCSEL Position */ +#define SYS_PWRONOTP_BTSRCSEL_Msk (0x3ul << SYS_PWRONOTP_BTSRCSEL_Pos) /*!< SYS_T::PWRONOTP: BTSRCSEL Mask */ + +#define SYS_PWRONOTP_NPAGESEL_Pos (12) /*!< SYS_T::PWRONOTP: NPAGESEL Position */ +#define SYS_PWRONOTP_NPAGESEL_Msk (0x3ul << SYS_PWRONOTP_NPAGESEL_Pos) /*!< SYS_T::PWRONOTP: NPAGESEL Mask */ + +#define SYS_PWRONOTP_MISCCFG_Pos (14) /*!< SYS_T::PWRONOTP: MISCCFG Position */ +#define SYS_PWRONOTP_MISCCFG_Msk (0x3ul << SYS_PWRONOTP_MISCCFG_Pos) /*!< SYS_T::PWRONOTP: MISCCFG Mask */ + +#define SYS_PWRONOTP_USBP0ID_Pos (16) /*!< SYS_T::PWRONOTP: USBP0ID Position */ +#define SYS_PWRONOTP_USBP0ID_Msk (0x1ul << SYS_PWRONOTP_USBP0ID_Pos) /*!< SYS_T::PWRONOTP: USBP0ID Mask */ + +#define SYS_PWRONOTP_SECBTPSWD_Pos (24) /*!< SYS_T::PWRONOTP: SECBTPSWD Position */ +#define SYS_PWRONOTP_SECBTPSWD_Msk (0xfful << SYS_PWRONOTP_SECBTPSWD_Pos) /*!< SYS_T::PWRONOTP: SECBTPSWD Mask */ + +#define SYS_PWRONPIN_SECBTDIS_Pos (0) /*!< SYS_T::PWRONPIN: SECBTDIS Position */ +#define SYS_PWRONPIN_SECBTDIS_Msk (0x1ul << SYS_PWRONPIN_SECBTDIS_Pos) /*!< SYS_T::PWRONPIN: SECBTDIS Mask */ + +#define SYS_PWRONPIN_BTSRCSEL_Pos (2) /*!< SYS_T::PWRONPIN: BTSRCSEL Position */ +#define SYS_PWRONPIN_BTSRCSEL_Msk (0x3ul << SYS_PWRONPIN_BTSRCSEL_Pos) /*!< SYS_T::PWRONPIN: BTSRCSEL Mask */ + +#define SYS_PWRONPIN_NPAGESEL_Pos (4) /*!< SYS_T::PWRONPIN: NPAGESEL Position */ +#define SYS_PWRONPIN_NPAGESEL_Msk (0x3ul << SYS_PWRONPIN_NPAGESEL_Pos) /*!< SYS_T::PWRONPIN: NPAGESEL Mask */ + +#define SYS_PWRONPIN_MISCCFG_Pos (6) /*!< SYS_T::PWRONPIN: MISCCFG Position */ +#define SYS_PWRONPIN_MISCCFG_Msk (0x3ul << SYS_PWRONPIN_MISCCFG_Pos) /*!< SYS_T::PWRONPIN: MISCCFG Mask */ + +#define SYS_RSTSTS_PORF_Pos (0) /*!< SYS_T::RSTSTS: PORF Position */ +#define SYS_RSTSTS_PORF_Msk (0x1ul << SYS_RSTSTS_PORF_Pos) /*!< SYS_T::RSTSTS: PORF Mask */ + +#define SYS_RSTSTS_PINRF_Pos (1) /*!< SYS_T::RSTSTS: PINRF Position */ +#define SYS_RSTSTS_PINRF_Msk (0x1ul << SYS_RSTSTS_PINRF_Pos) /*!< SYS_T::RSTSTS: PINRF Mask */ + +#define SYS_RSTSTS_WDT0RF_Pos (2) /*!< SYS_T::RSTSTS: WDT0RF Position */ +#define SYS_RSTSTS_WDT0RF_Msk (0x1ul << SYS_RSTSTS_WDT0RF_Pos) /*!< SYS_T::RSTSTS: WDT0RF Mask */ + +#define SYS_RSTSTS_LVRF_Pos (3) /*!< SYS_T::RSTSTS: LVRF Position */ +#define SYS_RSTSTS_LVRF_Msk (0x1ul << SYS_RSTSTS_LVRF_Pos) /*!< SYS_T::RSTSTS: LVRF Mask */ + +#define SYS_RSTSTS_CPU0DBGRF_Pos (4) /*!< SYS_T::RSTSTS: CPU0DBGRF Position */ +#define SYS_RSTSTS_CPU0DBGRF_Msk (0x1ul << SYS_RSTSTS_CPU0DBGRF_Pos) /*!< SYS_T::RSTSTS: CPU0DBGRF Mask */ + +#define SYS_RSTSTS_CPU0WARMRF_Pos (5) /*!< SYS_T::RSTSTS: CPU0WARMRF Position */ +#define SYS_RSTSTS_CPU0WARMRF_Msk (0x1ul << SYS_RSTSTS_CPU0WARMRF_Pos) /*!< SYS_T::RSTSTS: CPU0WARMRF Mask */ + +#define SYS_RSTSTS_HRESETRF_Pos (6) /*!< SYS_T::RSTSTS: HRESETRF Position */ +#define SYS_RSTSTS_HRESETRF_Msk (0x1ul << SYS_RSTSTS_HRESETRF_Pos) /*!< SYS_T::RSTSTS: HRESETRF Mask */ + +#define SYS_RSTSTS_CPU0RF_Pos (7) /*!< SYS_T::RSTSTS: CPU0RF Position */ +#define SYS_RSTSTS_CPU0RF_Msk (0x1ul << SYS_RSTSTS_CPU0RF_Pos) /*!< SYS_T::RSTSTS: CPU0RF Mask */ + +#define SYS_RSTSTS_WDT1RF_Pos (10) /*!< SYS_T::RSTSTS: WDT1RF Position */ +#define SYS_RSTSTS_WDT1RF_Msk (0x1ul << SYS_RSTSTS_WDT1RF_Pos) /*!< SYS_T::RSTSTS: WDT1RF Mask */ + +#define SYS_RSTSTS_WDT2RFA_Pos (11) /*!< SYS_T::RSTSTS: WDT2RFA Position */ +#define SYS_RSTSTS_WDT2RFA_Msk (0x1ul << SYS_RSTSTS_WDT2RFA_Pos) /*!< SYS_T::RSTSTS: WDT2RFA Mask */ + +#define SYS_RSTSTS_CPU1DBGRF_Pos (12) /*!< SYS_T::RSTSTS: CPU1DBGRF Position */ +#define SYS_RSTSTS_CPU1DBGRF_Msk (0x1ul << SYS_RSTSTS_CPU1DBGRF_Pos) /*!< SYS_T::RSTSTS: CPU1DBGRF Mask */ + +#define SYS_RSTSTS_CPU1WARMRF_Pos (13) /*!< SYS_T::RSTSTS: CPU1WARMRF Position */ +#define SYS_RSTSTS_CPU1WARMRF_Msk (0x1ul << SYS_RSTSTS_CPU1WARMRF_Pos) /*!< SYS_T::RSTSTS: CPU1WARMRF Mask */ + +#define SYS_RSTSTS_CPU1RF_Pos (15) /*!< SYS_T::RSTSTS: CPU1RF Position */ +#define SYS_RSTSTS_CPU1RF_Msk (0x1ul << SYS_RSTSTS_CPU1RF_Pos) /*!< SYS_T::RSTSTS: CPU1RF Mask */ + +#define SYS_RSTSTS_WDT1RFM_Pos (18) /*!< SYS_T::RSTSTS: WDT1RFM Position */ +#define SYS_RSTSTS_WDT1RFM_Msk (0x1ul << SYS_RSTSTS_WDT1RFM_Pos) /*!< SYS_T::RSTSTS: WDT1RFM Mask */ + +#define SYS_RSTSTS_WDT2RF_Pos (19) /*!< SYS_T::RSTSTS: WDT2RF Position */ +#define SYS_RSTSTS_WDT2RF_Msk (0x1ul << SYS_RSTSTS_WDT2RF_Pos) /*!< SYS_T::RSTSTS: WDT2RF Mask */ + +#define SYS_RSTSTS_RTPM4LKRF_Pos (20) /*!< SYS_T::RSTSTS: RTPM4LKRF Position */ +#define SYS_RSTSTS_RTPM4LKRF_Msk (0x1ul << SYS_RSTSTS_RTPM4LKRF_Pos) /*!< SYS_T::RSTSTS: RTPM4LKRF Mask */ + +#define SYS_RSTSTS_RTPM4SYSRF_Pos (21) /*!< SYS_T::RSTSTS: RTPM4SYSRF Position */ +#define SYS_RSTSTS_RTPM4SYSRF_Msk (0x1ul << SYS_RSTSTS_RTPM4SYSRF_Pos) /*!< SYS_T::RSTSTS: RTPM4SYSRF Mask */ + +#define SYS_RSTSTS_RTPPMUSYSRF_Pos (22) /*!< SYS_T::RSTSTS: RTPPMUSYSRF Position */ +#define SYS_RSTSTS_RTPPMUSYSRF_Msk (0x1ul << SYS_RSTSTS_RTPPMUSYSRF_Pos) /*!< SYS_T::RSTSTS: RTPPMUSYSRF Mask */ + +#define SYS_RSTSTS_RTPM4CPURF_Pos (23) /*!< SYS_T::RSTSTS: RTPM4CPURF Position */ +#define SYS_RSTSTS_RTPM4CPURF_Msk (0x1ul << SYS_RSTSTS_RTPM4CPURF_Pos) /*!< SYS_T::RSTSTS: RTPM4CPURF Mask */ + +#define SYS_MISCRFCR_PORDISCODE_Pos (0) /*!< SYS_T::MISCRFCR: PORDISCODE Position */ +#define SYS_MISCRFCR_PORDISCODE_Msk (0xfffful << SYS_MISCRFCR_PORDISCODE_Pos) /*!< SYS_T::MISCRFCR: PORDISCODE Mask */ + +#define SYS_MISCRFCR_WDT1RSTAEN_Pos (16) /*!< SYS_T::MISCRFCR: WDT1RSTAEN Position */ +#define SYS_MISCRFCR_WDT1RSTAEN_Msk (0x1ul << SYS_MISCRFCR_WDT1RSTAEN_Pos) /*!< SYS_T::MISCRFCR: WDT1RSTAEN Mask */ + +#define SYS_MISCRFCR_WDT2RSTAEN_Pos (17) /*!< SYS_T::MISCRFCR: WDT2RSTAEN Position */ +#define SYS_MISCRFCR_WDT2RSTAEN_Msk (0x1ul << SYS_MISCRFCR_WDT2RSTAEN_Pos) /*!< SYS_T::MISCRFCR: WDT2RSTAEN Mask */ + +#define SYS_MISCRFCR_WDT1RSTMEN_Pos (18) /*!< SYS_T::MISCRFCR: WDT1RSTMEN Position */ +#define SYS_MISCRFCR_WDT1RSTMEN_Msk (0x1ul << SYS_MISCRFCR_WDT1RSTMEN_Pos) /*!< SYS_T::MISCRFCR: WDT1RSTMEN Mask */ + +#define SYS_RSTDEBCTL_DEBCNT_Pos (0) /*!< SYS_T::RSTDEBCTL: DEBCNT Position */ +#define SYS_RSTDEBCTL_DEBCNT_Msk (0xfffful << SYS_RSTDEBCTL_DEBCNT_Pos) /*!< SYS_T::RSTDEBCTL: DEBCNT Mask */ + +#define SYS_RSTDEBCTL_RSTDEBEN_Pos (31) /*!< SYS_T::RSTDEBCTL: RSTDEBEN Position */ +#define SYS_RSTDEBCTL_RSTDEBEN_Msk (0x1ul << SYS_RSTDEBCTL_RSTDEBEN_Pos) /*!< SYS_T::RSTDEBCTL: RSTDEBEN Mask */ + +#define SYS_LVRDCR_LVREN_Pos (0) /*!< SYS_T::LVRDCR: LVREN Position */ +#define SYS_LVRDCR_LVREN_Msk (0x1ul << SYS_LVRDCR_LVREN_Pos) /*!< SYS_T::LVRDCR: LVREN Mask */ + +#define SYS_LVRDCR_LVRDGSEL_Pos (1) /*!< SYS_T::LVRDCR: LVRDGSEL Position */ +#define SYS_LVRDCR_LVRDGSEL_Msk (0x7ul << SYS_LVRDCR_LVRDGSEL_Pos) /*!< SYS_T::LVRDCR: LVRDGSEL Mask */ + +#define SYS_LVRDCR_LVDEN_Pos (8) /*!< SYS_T::LVRDCR: LVDEN Position */ +#define SYS_LVRDCR_LVDEN_Msk (0x1ul << SYS_LVRDCR_LVDEN_Pos) /*!< SYS_T::LVRDCR: LVDEN Mask */ + +#define SYS_LVRDCR_LVDSEL_Pos (9) /*!< SYS_T::LVRDCR: LVDSEL Position */ +#define SYS_LVRDCR_LVDSEL_Msk (0x1ul << SYS_LVRDCR_LVDSEL_Pos) /*!< SYS_T::LVRDCR: LVDSEL Mask */ + +#define SYS_LVRDCR_LVDWKA35EN_Pos (10) /*!< SYS_T::LVRDCR: LVDWKA35EN Position */ +#define SYS_LVRDCR_LVDWKA35EN_Msk (0x1ul << SYS_LVRDCR_LVDWKA35EN_Pos) /*!< SYS_T::LVRDCR: LVDWKA35EN Mask */ + +#define SYS_LVRDCR_LVDWKRTPEN_Pos (11) /*!< SYS_T::LVRDCR: LVDWKRTPEN Position */ +#define SYS_LVRDCR_LVDWKRTPEN_Msk (0x1ul << SYS_LVRDCR_LVDWKRTPEN_Pos) /*!< SYS_T::LVRDCR: LVDWKRTPEN Mask */ + +#define SYS_LVRDCR_LVDODGSEL_Pos (12) /*!< SYS_T::LVRDCR: LVDODGSEL Position */ +#define SYS_LVRDCR_LVDODGSEL_Msk (0x7ul << SYS_LVRDCR_LVDODGSEL_Pos) /*!< SYS_T::LVRDCR: LVDODGSEL Mask */ + +#define SYS_IPRST0_CHIPRST_Pos (0) /*!< SYS_T::IPRST0: CHIPRST Position */ +#define SYS_IPRST0_CHIPRST_Msk (0x1ul << SYS_IPRST0_CHIPRST_Pos) /*!< SYS_T::IPRST0: CHIPRST Mask */ + +#define SYS_IPRST0_CA35CR0RST_Pos (1) /*!< SYS_T::IPRST0: CA35CR0RST Position */ +#define SYS_IPRST0_CA35CR0RST_Msk (0x1ul << SYS_IPRST0_CA35CR0RST_Pos) /*!< SYS_T::IPRST0: CA35CR0RST Mask */ + +#define SYS_IPRST0_CA35CR1RST_Pos (2) /*!< SYS_T::IPRST0: CA35CR1RST Position */ +#define SYS_IPRST0_CA35CR1RST_Msk (0x1ul << SYS_IPRST0_CA35CR1RST_Pos) /*!< SYS_T::IPRST0: CA35CR1RST Mask */ + +#define SYS_IPRST0_CM4RST_Pos (3) /*!< SYS_T::IPRST0: CM4RST Position */ +#define SYS_IPRST0_CM4RST_Msk (0x1ul << SYS_IPRST0_CM4RST_Pos) /*!< SYS_T::IPRST0: CM4RST Mask */ + +#define SYS_IPRST0_PDMA0RST_Pos (4) /*!< SYS_T::IPRST0: PDMA0RST Position */ +#define SYS_IPRST0_PDMA0RST_Msk (0x1ul << SYS_IPRST0_PDMA0RST_Pos) /*!< SYS_T::IPRST0: PDMA0RST Mask */ + +#define SYS_IPRST0_PDMA1RST_Pos (5) /*!< SYS_T::IPRST0: PDMA1RST Position */ +#define SYS_IPRST0_PDMA1RST_Msk (0x1ul << SYS_IPRST0_PDMA1RST_Pos) /*!< SYS_T::IPRST0: PDMA1RST Mask */ + +#define SYS_IPRST0_PDMA2RST_Pos (6) /*!< SYS_T::IPRST0: PDMA2RST Position */ +#define SYS_IPRST0_PDMA2RST_Msk (0x1ul << SYS_IPRST0_PDMA2RST_Pos) /*!< SYS_T::IPRST0: PDMA2RST Mask */ + +#define SYS_IPRST0_PDMA3RST_Pos (7) /*!< SYS_T::IPRST0: PDMA3RST Position */ +#define SYS_IPRST0_PDMA3RST_Msk (0x1ul << SYS_IPRST0_PDMA3RST_Pos) /*!< SYS_T::IPRST0: PDMA3RST Mask */ + +#define SYS_IPRST0_DISPCRST_Pos (9) /*!< SYS_T::IPRST0: DISPCRST Position */ +#define SYS_IPRST0_DISPCRST_Msk (0x1ul << SYS_IPRST0_DISPCRST_Pos) /*!< SYS_T::IPRST0: DISPCRST Mask */ + +#define SYS_IPRST0_CCAP0RST_Pos (10) /*!< SYS_T::IPRST0: CCAP0RST Position */ +#define SYS_IPRST0_CCAP0RST_Msk (0x1ul << SYS_IPRST0_CCAP0RST_Pos) /*!< SYS_T::IPRST0: CCAP0RST Mask */ + +#define SYS_IPRST0_CCAP1RST_Pos (11) /*!< SYS_T::IPRST0: CCAP1RST Position */ +#define SYS_IPRST0_CCAP1RST_Msk (0x1ul << SYS_IPRST0_CCAP1RST_Pos) /*!< SYS_T::IPRST0: CCAP1RST Mask */ + +#define SYS_IPRST0_GFXRST_Pos (12) /*!< SYS_T::IPRST0: GFXRST Position */ +#define SYS_IPRST0_GFXRST_Msk (0x1ul << SYS_IPRST0_GFXRST_Pos) /*!< SYS_T::IPRST0: GFXRST Mask */ + +#define SYS_IPRST0_VDECRST_Pos (13) /*!< SYS_T::IPRST0: VDECRST Position */ +#define SYS_IPRST0_VDECRST_Msk (0x1ul << SYS_IPRST0_VDECRST_Pos) /*!< SYS_T::IPRST0: VDECRST Mask */ + +#define SYS_IPRST0_WRHO0RST_Pos (14) /*!< SYS_T::IPRST0: WRHO0RST Position */ +#define SYS_IPRST0_WRHO0RST_Msk (0x1ul << SYS_IPRST0_WRHO0RST_Pos) /*!< SYS_T::IPRST0: WRHO0RST Mask */ + +#define SYS_IPRST0_WRHO1RST_Pos (15) /*!< SYS_T::IPRST0: WRHO1RST Position */ +#define SYS_IPRST0_WRHO1RST_Msk (0x1ul << SYS_IPRST0_WRHO1RST_Pos) /*!< SYS_T::IPRST0: WRHO1RST Mask */ + +#define SYS_IPRST0_GMAC0RST_Pos (16) /*!< SYS_T::IPRST0: GMAC0RST Position */ +#define SYS_IPRST0_GMAC0RST_Msk (0x1ul << SYS_IPRST0_GMAC0RST_Pos) /*!< SYS_T::IPRST0: GMAC0RST Mask */ + +#define SYS_IPRST0_GMAC1RST_Pos (17) /*!< SYS_T::IPRST0: GMAC1RST Position */ +#define SYS_IPRST0_GMAC1RST_Msk (0x1ul << SYS_IPRST0_GMAC1RST_Pos) /*!< SYS_T::IPRST0: GMAC1RST Mask */ + +#define SYS_IPRST0_HWSEMRST_Pos (18) /*!< SYS_T::IPRST0: HWSEMRST Position */ +#define SYS_IPRST0_HWSEMRST_Msk (0x1ul << SYS_IPRST0_HWSEMRST_Pos) /*!< SYS_T::IPRST0: HWSEMRST Mask */ + +#define SYS_IPRST0_EBIRST_Pos (19) /*!< SYS_T::IPRST0: EBIRST Position */ +#define SYS_IPRST0_EBIRST_Msk (0x1ul << SYS_IPRST0_EBIRST_Pos) /*!< SYS_T::IPRST0: EBIRST Mask */ + +#define SYS_IPRST0_HSUSBH0RST_Pos (20) /*!< SYS_T::IPRST0: HSUSBH0RST Position */ +#define SYS_IPRST0_HSUSBH0RST_Msk (0x1ul << SYS_IPRST0_HSUSBH0RST_Pos) /*!< SYS_T::IPRST0: HSUSBH0RST Mask */ + +#define SYS_IPRST0_HSUSBH1RST_Pos (21) /*!< SYS_T::IPRST0: HSUSBH1RST Position */ +#define SYS_IPRST0_HSUSBH1RST_Msk (0x1ul << SYS_IPRST0_HSUSBH1RST_Pos) /*!< SYS_T::IPRST0: HSUSBH1RST Mask */ + +#define SYS_IPRST0_HSUSBDRST_Pos (22) /*!< SYS_T::IPRST0: HSUSBDRST Position */ +#define SYS_IPRST0_HSUSBDRST_Msk (0x1ul << SYS_IPRST0_HSUSBDRST_Pos) /*!< SYS_T::IPRST0: HSUSBDRST Mask */ + +#define SYS_IPRST0_SDH0RST_Pos (24) /*!< SYS_T::IPRST0: SDH0RST Position */ +#define SYS_IPRST0_SDH0RST_Msk (0x1ul << SYS_IPRST0_SDH0RST_Pos) /*!< SYS_T::IPRST0: SDH0RST Mask */ + +#define SYS_IPRST0_SDH1RST_Pos (25) /*!< SYS_T::IPRST0: SDH1RST Position */ +#define SYS_IPRST0_SDH1RST_Msk (0x1ul << SYS_IPRST0_SDH1RST_Pos) /*!< SYS_T::IPRST0: SDH1RST Mask */ + +#define SYS_IPRST0_NANDRST_Pos (26) /*!< SYS_T::IPRST0: NANDRST Position */ +#define SYS_IPRST0_NANDRST_Msk (0x1ul << SYS_IPRST0_NANDRST_Pos) /*!< SYS_T::IPRST0: NANDRST Mask */ + +#define SYS_IPRST0_GPIORST_Pos (27) /*!< SYS_T::IPRST0: GPIORST Position */ +#define SYS_IPRST0_GPIORST_Msk (0x1ul << SYS_IPRST0_GPIORST_Pos) /*!< SYS_T::IPRST0: GPIORST Mask */ + +#define SYS_IPRST0_MCTLPRST_Pos (28) /*!< SYS_T::IPRST0: MCTLPRST Position */ +#define SYS_IPRST0_MCTLPRST_Msk (0x1ul << SYS_IPRST0_MCTLPRST_Pos) /*!< SYS_T::IPRST0: MCTLPRST Mask */ + +#define SYS_IPRST0_MCTLCRST_Pos (29) /*!< SYS_T::IPRST0: MCTLCRST Position */ +#define SYS_IPRST0_MCTLCRST_Msk (0x1ul << SYS_IPRST0_MCTLCRST_Pos) /*!< SYS_T::IPRST0: MCTLCRST Mask */ + +#define SYS_IPRST0_DDRPUBRST_Pos (30) /*!< SYS_T::IPRST0: DDRPUBRST Position */ +#define SYS_IPRST0_DDRPUBRST_Msk (0x1ul << SYS_IPRST0_DDRPUBRST_Pos) /*!< SYS_T::IPRST0: DDRPUBRST Mask */ + +#define SYS_IPRST1_TMR0RST_Pos (2) /*!< SYS_T::IPRST1: TMR0RST Position */ +#define SYS_IPRST1_TMR0RST_Msk (0x1ul << SYS_IPRST1_TMR0RST_Pos) /*!< SYS_T::IPRST1: TMR0RST Mask */ + +#define SYS_IPRST1_TMR1RST_Pos (3) /*!< SYS_T::IPRST1: TMR1RST Position */ +#define SYS_IPRST1_TMR1RST_Msk (0x1ul << SYS_IPRST1_TMR1RST_Pos) /*!< SYS_T::IPRST1: TMR1RST Mask */ + +#define SYS_IPRST1_TMR2RST_Pos (4) /*!< SYS_T::IPRST1: TMR2RST Position */ +#define SYS_IPRST1_TMR2RST_Msk (0x1ul << SYS_IPRST1_TMR2RST_Pos) /*!< SYS_T::IPRST1: TMR2RST Mask */ + +#define SYS_IPRST1_TMR3RST_Pos (5) /*!< SYS_T::IPRST1: TMR3RST Position */ +#define SYS_IPRST1_TMR3RST_Msk (0x1ul << SYS_IPRST1_TMR3RST_Pos) /*!< SYS_T::IPRST1: TMR3RST Mask */ + +#define SYS_IPRST1_I2C0RST_Pos (8) /*!< SYS_T::IPRST1: I2C0RST Position */ +#define SYS_IPRST1_I2C0RST_Msk (0x1ul << SYS_IPRST1_I2C0RST_Pos) /*!< SYS_T::IPRST1: I2C0RST Mask */ + +#define SYS_IPRST1_I2C1RST_Pos (9) /*!< SYS_T::IPRST1: I2C1RST Position */ +#define SYS_IPRST1_I2C1RST_Msk (0x1ul << SYS_IPRST1_I2C1RST_Pos) /*!< SYS_T::IPRST1: I2C1RST Mask */ + +#define SYS_IPRST1_I2C2RST_Pos (10) /*!< SYS_T::IPRST1: I2C2RST Position */ +#define SYS_IPRST1_I2C2RST_Msk (0x1ul << SYS_IPRST1_I2C2RST_Pos) /*!< SYS_T::IPRST1: I2C2RST Mask */ + +#define SYS_IPRST1_I2C3RST_Pos (11) /*!< SYS_T::IPRST1: I2C3RST Position */ +#define SYS_IPRST1_I2C3RST_Msk (0x1ul << SYS_IPRST1_I2C3RST_Pos) /*!< SYS_T::IPRST1: I2C3RST Mask */ + +#define SYS_IPRST1_QSPI0RST_Pos (12) /*!< SYS_T::IPRST1: QSPI0RST Position */ +#define SYS_IPRST1_QSPI0RST_Msk (0x1ul << SYS_IPRST1_QSPI0RST_Pos) /*!< SYS_T::IPRST1: QSPI0RST Mask */ + +#define SYS_IPRST1_SPI0RST_Pos (13) /*!< SYS_T::IPRST1: SPI0RST Position */ +#define SYS_IPRST1_SPI0RST_Msk (0x1ul << SYS_IPRST1_SPI0RST_Pos) /*!< SYS_T::IPRST1: SPI0RST Mask */ + +#define SYS_IPRST1_SPI1RST_Pos (14) /*!< SYS_T::IPRST1: SPI1RST Position */ +#define SYS_IPRST1_SPI1RST_Msk (0x1ul << SYS_IPRST1_SPI1RST_Pos) /*!< SYS_T::IPRST1: SPI1RST Mask */ + +#define SYS_IPRST1_SPI2RST_Pos (15) /*!< SYS_T::IPRST1: SPI2RST Position */ +#define SYS_IPRST1_SPI2RST_Msk (0x1ul << SYS_IPRST1_SPI2RST_Pos) /*!< SYS_T::IPRST1: SPI2RST Mask */ + +#define SYS_IPRST1_UART0RST_Pos (16) /*!< SYS_T::IPRST1: UART0RST Position */ +#define SYS_IPRST1_UART0RST_Msk (0x1ul << SYS_IPRST1_UART0RST_Pos) /*!< SYS_T::IPRST1: UART0RST Mask */ + +#define SYS_IPRST1_UART1RST_Pos (17) /*!< SYS_T::IPRST1: UART1RST Position */ +#define SYS_IPRST1_UART1RST_Msk (0x1ul << SYS_IPRST1_UART1RST_Pos) /*!< SYS_T::IPRST1: UART1RST Mask */ + +#define SYS_IPRST1_UART2RST_Pos (18) /*!< SYS_T::IPRST1: UART2RST Position */ +#define SYS_IPRST1_UART2RST_Msk (0x1ul << SYS_IPRST1_UART2RST_Pos) /*!< SYS_T::IPRST1: UART2RST Mask */ + +#define SYS_IPRST1_UART3RST_Pos (19) /*!< SYS_T::IPRST1: UART3RST Position */ +#define SYS_IPRST1_UART3RST_Msk (0x1ul << SYS_IPRST1_UART3RST_Pos) /*!< SYS_T::IPRST1: UART3RST Mask */ + +#define SYS_IPRST1_UART4RST_Pos (20) /*!< SYS_T::IPRST1: UART4RST Position */ +#define SYS_IPRST1_UART4RST_Msk (0x1ul << SYS_IPRST1_UART4RST_Pos) /*!< SYS_T::IPRST1: UART4RST Mask */ + +#define SYS_IPRST1_UART5RST_Pos (21) /*!< SYS_T::IPRST1: UART5RST Position */ +#define SYS_IPRST1_UART5RST_Msk (0x1ul << SYS_IPRST1_UART5RST_Pos) /*!< SYS_T::IPRST1: UART5RST Mask */ + +#define SYS_IPRST1_UART6RST_Pos (22) /*!< SYS_T::IPRST1: UART6RST Position */ +#define SYS_IPRST1_UART6RST_Msk (0x1ul << SYS_IPRST1_UART6RST_Pos) /*!< SYS_T::IPRST1: UART6RST Mask */ + +#define SYS_IPRST1_UART7RST_Pos (23) /*!< SYS_T::IPRST1: UART7RST Position */ +#define SYS_IPRST1_UART7RST_Msk (0x1ul << SYS_IPRST1_UART7RST_Pos) /*!< SYS_T::IPRST1: UART7RST Mask */ + +#define SYS_IPRST1_CANFD0RST_Pos (24) /*!< SYS_T::IPRST1: CANFD0RST Position */ +#define SYS_IPRST1_CANFD0RST_Msk (0x1ul << SYS_IPRST1_CANFD0RST_Pos) /*!< SYS_T::IPRST1: CANFD0RST Mask */ + +#define SYS_IPRST1_CANFD1RST_Pos (25) /*!< SYS_T::IPRST1: CANFD1RST Position */ +#define SYS_IPRST1_CANFD1RST_Msk (0x1ul << SYS_IPRST1_CANFD1RST_Pos) /*!< SYS_T::IPRST1: CANFD1RST Mask */ + +#define SYS_IPRST1_EADC0RST_Pos (28) /*!< SYS_T::IPRST1: EADC0RST Position */ +#define SYS_IPRST1_EADC0RST_Msk (0x1ul << SYS_IPRST1_EADC0RST_Pos) /*!< SYS_T::IPRST1: EADC0RST Mask */ + +#define SYS_IPRST1_I2S0RST_Pos (29) /*!< SYS_T::IPRST1: I2S0RST Position */ +#define SYS_IPRST1_I2S0RST_Msk (0x1ul << SYS_IPRST1_I2S0RST_Pos) /*!< SYS_T::IPRST1: I2S0RST Mask */ + +#define SYS_IPRST2_SC0RST_Pos (0) /*!< SYS_T::IPRST2: SC0RST Position */ +#define SYS_IPRST2_SC0RST_Msk (0x1ul << SYS_IPRST2_SC0RST_Pos) /*!< SYS_T::IPRST2: SC0RST Mask */ + +#define SYS_IPRST2_SC1RST_Pos (1) /*!< SYS_T::IPRST2: SC1RST Position */ +#define SYS_IPRST2_SC1RST_Msk (0x1ul << SYS_IPRST2_SC1RST_Pos) /*!< SYS_T::IPRST2: SC1RST Mask */ + +#define SYS_IPRST2_QSPI1RST_Pos (4) /*!< SYS_T::IPRST2: QSPI1RST Position */ +#define SYS_IPRST2_QSPI1RST_Msk (0x1ul << SYS_IPRST2_QSPI1RST_Pos) /*!< SYS_T::IPRST2: QSPI1RST Mask */ + +#define SYS_IPRST2_SPI3RST_Pos (6) /*!< SYS_T::IPRST2: SPI3RST Position */ +#define SYS_IPRST2_SPI3RST_Msk (0x1ul << SYS_IPRST2_SPI3RST_Pos) /*!< SYS_T::IPRST2: SPI3RST Mask */ + +#define SYS_IPRST2_EPWM0RST_Pos (16) /*!< SYS_T::IPRST2: EPWM0RST Position */ +#define SYS_IPRST2_EPWM0RST_Msk (0x1ul << SYS_IPRST2_EPWM0RST_Pos) /*!< SYS_T::IPRST2: EPWM0RST Mask */ + +#define SYS_IPRST2_EPWM1RST_Pos (17) /*!< SYS_T::IPRST2: EPWM1RST Position */ +#define SYS_IPRST2_EPWM1RST_Msk (0x1ul << SYS_IPRST2_EPWM1RST_Pos) /*!< SYS_T::IPRST2: EPWM1RST Mask */ + +#define SYS_IPRST2_QEI0RST_Pos (22) /*!< SYS_T::IPRST2: QEI0RST Position */ +#define SYS_IPRST2_QEI0RST_Msk (0x1ul << SYS_IPRST2_QEI0RST_Pos) /*!< SYS_T::IPRST2: QEI0RST Mask */ + +#define SYS_IPRST2_QEI1RST_Pos (23) /*!< SYS_T::IPRST2: QEI1RST Position */ +#define SYS_IPRST2_QEI1RST_Msk (0x1ul << SYS_IPRST2_QEI1RST_Pos) /*!< SYS_T::IPRST2: QEI1RST Mask */ + +#define SYS_IPRST2_ECAP0RST_Pos (26) /*!< SYS_T::IPRST2: ECAP0RST Position */ +#define SYS_IPRST2_ECAP0RST_Msk (0x1ul << SYS_IPRST2_ECAP0RST_Pos) /*!< SYS_T::IPRST2: ECAP0RST Mask */ + +#define SYS_IPRST2_ECAP1RST_Pos (27) /*!< SYS_T::IPRST2: ECAP1RST Position */ +#define SYS_IPRST2_ECAP1RST_Msk (0x1ul << SYS_IPRST2_ECAP1RST_Pos) /*!< SYS_T::IPRST2: ECAP1RST Mask */ + +#define SYS_IPRST2_CANFD2RST_Pos (28) /*!< SYS_T::IPRST2: CANFD2RST Position */ +#define SYS_IPRST2_CANFD2RST_Msk (0x1ul << SYS_IPRST2_CANFD2RST_Pos) /*!< SYS_T::IPRST2: CANFD2RST Mask */ + +#define SYS_IPRST2_ADC0RST_Pos (31) /*!< SYS_T::IPRST2: ADC0RST Position */ +#define SYS_IPRST2_ADC0RST_Msk (0x1ul << SYS_IPRST2_ADC0RST_Pos) /*!< SYS_T::IPRST2: ADC0RST Mask */ + +#define SYS_IPRST3_TMR4RST_Pos (0) /*!< SYS_T::IPRST3: TMR4RST Position */ +#define SYS_IPRST3_TMR4RST_Msk (0x1ul << SYS_IPRST3_TMR4RST_Pos) /*!< SYS_T::IPRST3: TMR4RST Mask */ + +#define SYS_IPRST3_TMR5RST_Pos (1) /*!< SYS_T::IPRST3: TMR5RST Position */ +#define SYS_IPRST3_TMR5RST_Msk (0x1ul << SYS_IPRST3_TMR5RST_Pos) /*!< SYS_T::IPRST3: TMR5RST Mask */ + +#define SYS_IPRST3_TMR6RST_Pos (2) /*!< SYS_T::IPRST3: TMR6RST Position */ +#define SYS_IPRST3_TMR6RST_Msk (0x1ul << SYS_IPRST3_TMR6RST_Pos) /*!< SYS_T::IPRST3: TMR6RST Mask */ + +#define SYS_IPRST3_TMR7RST_Pos (3) /*!< SYS_T::IPRST3: TMR7RST Position */ +#define SYS_IPRST3_TMR7RST_Msk (0x1ul << SYS_IPRST3_TMR7RST_Pos) /*!< SYS_T::IPRST3: TMR7RST Mask */ + +#define SYS_IPRST3_TMR8RST_Pos (4) /*!< SYS_T::IPRST3: TMR8RST Position */ +#define SYS_IPRST3_TMR8RST_Msk (0x1ul << SYS_IPRST3_TMR8RST_Pos) /*!< SYS_T::IPRST3: TMR8RST Mask */ + +#define SYS_IPRST3_TMR9RST_Pos (5) /*!< SYS_T::IPRST3: TMR9RST Position */ +#define SYS_IPRST3_TMR9RST_Msk (0x1ul << SYS_IPRST3_TMR9RST_Pos) /*!< SYS_T::IPRST3: TMR9RST Mask */ + +#define SYS_IPRST3_TMR10RST_Pos (6) /*!< SYS_T::IPRST3: TMR10RST Position */ +#define SYS_IPRST3_TMR10RST_Msk (0x1ul << SYS_IPRST3_TMR10RST_Pos) /*!< SYS_T::IPRST3: TMR10RST Mask */ + +#define SYS_IPRST3_TMR11RST_Pos (7) /*!< SYS_T::IPRST3: TMR11RST Position */ +#define SYS_IPRST3_TMR11RST_Msk (0x1ul << SYS_IPRST3_TMR11RST_Pos) /*!< SYS_T::IPRST3: TMR11RST Mask */ + +#define SYS_IPRST3_UART8RST_Pos (8) /*!< SYS_T::IPRST3: UART8RST Position */ +#define SYS_IPRST3_UART8RST_Msk (0x1ul << SYS_IPRST3_UART8RST_Pos) /*!< SYS_T::IPRST3: UART8RST Mask */ + +#define SYS_IPRST3_UART9RST_Pos (9) /*!< SYS_T::IPRST3: UART9RST Position */ +#define SYS_IPRST3_UART9RST_Msk (0x1ul << SYS_IPRST3_UART9RST_Pos) /*!< SYS_T::IPRST3: UART9RST Mask */ + +#define SYS_IPRST3_UART10RST_Pos (10) /*!< SYS_T::IPRST3: UART10RST Position */ +#define SYS_IPRST3_UART10RST_Msk (0x1ul << SYS_IPRST3_UART10RST_Pos) /*!< SYS_T::IPRST3: UART10RST Mask */ + +#define SYS_IPRST3_UART11RST_Pos (11) /*!< SYS_T::IPRST3: UART11RST Position */ +#define SYS_IPRST3_UART11RST_Msk (0x1ul << SYS_IPRST3_UART11RST_Pos) /*!< SYS_T::IPRST3: UART11RST Mask */ + +#define SYS_IPRST3_UART12RST_Pos (12) /*!< SYS_T::IPRST3: UART12RST Position */ +#define SYS_IPRST3_UART12RST_Msk (0x1ul << SYS_IPRST3_UART12RST_Pos) /*!< SYS_T::IPRST3: UART12RST Mask */ + +#define SYS_IPRST3_UART13RST_Pos (13) /*!< SYS_T::IPRST3: UART13RST Position */ +#define SYS_IPRST3_UART13RST_Msk (0x1ul << SYS_IPRST3_UART13RST_Pos) /*!< SYS_T::IPRST3: UART13RST Mask */ + +#define SYS_IPRST3_UART14RST_Pos (14) /*!< SYS_T::IPRST3: UART14RST Position */ +#define SYS_IPRST3_UART14RST_Msk (0x1ul << SYS_IPRST3_UART14RST_Pos) /*!< SYS_T::IPRST3: UART14RST Mask */ + +#define SYS_IPRST3_UART15RST_Pos (15) /*!< SYS_T::IPRST3: UART15RST Position */ +#define SYS_IPRST3_UART15RST_Msk (0x1ul << SYS_IPRST3_UART15RST_Pos) /*!< SYS_T::IPRST3: UART15RST Mask */ + +#define SYS_IPRST3_UART16RST_Pos (16) /*!< SYS_T::IPRST3: UART16RST Position */ +#define SYS_IPRST3_UART16RST_Msk (0x1ul << SYS_IPRST3_UART16RST_Pos) /*!< SYS_T::IPRST3: UART16RST Mask */ + +#define SYS_IPRST3_I2S1RST_Pos (17) /*!< SYS_T::IPRST3: I2S1RST Position */ +#define SYS_IPRST3_I2S1RST_Msk (0x1ul << SYS_IPRST3_I2S1RST_Pos) /*!< SYS_T::IPRST3: I2S1RST Mask */ + +#define SYS_IPRST3_I2C4RST_Pos (18) /*!< SYS_T::IPRST3: I2C4RST Position */ +#define SYS_IPRST3_I2C4RST_Msk (0x1ul << SYS_IPRST3_I2C4RST_Pos) /*!< SYS_T::IPRST3: I2C4RST Mask */ + +#define SYS_IPRST3_I2C5RST_Pos (19) /*!< SYS_T::IPRST3: I2C5RST Position */ +#define SYS_IPRST3_I2C5RST_Msk (0x1ul << SYS_IPRST3_I2C5RST_Pos) /*!< SYS_T::IPRST3: I2C5RST Mask */ + +#define SYS_IPRST3_EPWM2RST_Pos (20) /*!< SYS_T::IPRST3: EPWM2RST Position */ +#define SYS_IPRST3_EPWM2RST_Msk (0x1ul << SYS_IPRST3_EPWM2RST_Pos) /*!< SYS_T::IPRST3: EPWM2RST Mask */ + +#define SYS_IPRST3_ECAP2RST_Pos (21) /*!< SYS_T::IPRST3: ECAP2RST Position */ +#define SYS_IPRST3_ECAP2RST_Msk (0x1ul << SYS_IPRST3_ECAP2RST_Pos) /*!< SYS_T::IPRST3: ECAP2RST Mask */ + +#define SYS_IPRST3_QEI2RST_Pos (22) /*!< SYS_T::IPRST3: QEI2RST Position */ +#define SYS_IPRST3_QEI2RST_Msk (0x1ul << SYS_IPRST3_QEI2RST_Pos) /*!< SYS_T::IPRST3: QEI2RST Mask */ + +#define SYS_IPRST3_CANFD3RST_Pos (23) /*!< SYS_T::IPRST3: CANFD3RST Position */ +#define SYS_IPRST3_CANFD3RST_Msk (0x1ul << SYS_IPRST3_CANFD3RST_Pos) /*!< SYS_T::IPRST3: CANFD3RST Mask */ + +#define SYS_IPRST3_KPIRST_Pos (24) /*!< SYS_T::IPRST3: KPIRST Position */ +#define SYS_IPRST3_KPIRST_Msk (0x1ul << SYS_IPRST3_KPIRST_Pos) /*!< SYS_T::IPRST3: KPIRST Mask */ + +#define SYS_IPRST3_GICRST_Pos (28) /*!< SYS_T::IPRST3: GICRST Position */ +#define SYS_IPRST3_GICRST_Msk (0x1ul << SYS_IPRST3_GICRST_Pos) /*!< SYS_T::IPRST3: GICRST Mask */ + +#define SYS_IPRST3_SSMCCRST_Pos (30) /*!< SYS_T::IPRST3: SSMCCRST Position */ +#define SYS_IPRST3_SSMCCRST_Msk (0x1ul << SYS_IPRST3_SSMCCRST_Pos) /*!< SYS_T::IPRST3: SSMCCRST Mask */ + +#define SYS_IPRST3_SSPCCRST_Pos (31) /*!< SYS_T::IPRST3: SSPCCRST Position */ +#define SYS_IPRST3_SSPCCRST_Msk (0x1ul << SYS_IPRST3_SSPCCRST_Pos) /*!< SYS_T::IPRST3: SSPCCRST Mask */ + +#define SYS_PMUCR_A35PGEN_Pos (0) /*!< SYS_T::PMUCR: A35PGEN Position */ +#define SYS_PMUCR_A35PGEN_Msk (0x1ul << SYS_PMUCR_A35PGEN_Pos) /*!< SYS_T::PMUCR: A35PGEN Mask */ + +#define SYS_PMUCR_AUTOL2FDIS_Pos (4) /*!< SYS_T::PMUCR: AUTOL2FDIS Position */ +#define SYS_PMUCR_AUTOL2FDIS_Msk (0x1ul << SYS_PMUCR_AUTOL2FDIS_Pos) /*!< SYS_T::PMUCR: AUTOL2FDIS Mask */ + +#define SYS_PMUCR_PDWKDLY_Pos (6) /*!< SYS_T::PMUCR: PDWKDLY Position */ +#define SYS_PMUCR_PDWKDLY_Msk (0x1ul << SYS_PMUCR_PDWKDLY_Pos) /*!< SYS_T::PMUCR: PDWKDLY Mask */ + +#define SYS_PMUCR_PWRSTBTM_Pos (8) /*!< SYS_T::PMUCR: PWRSTBTM Position */ +#define SYS_PMUCR_PWRSTBTM_Msk (0xful << SYS_PMUCR_PWRSTBTM_Pos) /*!< SYS_T::PMUCR: PWRSTBTM Mask */ + +#define SYS_PMUCR_PWRACKTO_Pos (12) /*!< SYS_T::PMUCR: PWRACKTO Position */ +#define SYS_PMUCR_PWRACKTO_Msk (0xful << SYS_PMUCR_PWRACKTO_Pos) /*!< SYS_T::PMUCR: PWRACKTO Mask */ + +#define SYS_PMUCR_A35PDEN_Pos (16) /*!< SYS_T::PMUCR: A35PDEN Position */ +#define SYS_PMUCR_A35PDEN_Msk (0x1ul << SYS_PMUCR_A35PDEN_Pos) /*!< SYS_T::PMUCR: A35PDEN Mask */ + +#define SYS_PMUCR_A35DBPDEN_Pos (18) /*!< SYS_T::PMUCR: A35DBPDEN Position */ +#define SYS_PMUCR_A35DBPDEN_Msk (0x1ul << SYS_PMUCR_A35DBPDEN_Pos) /*!< SYS_T::PMUCR: A35DBPDEN Mask */ + +#define SYS_PMUCR_RTPPDEN_Pos (24) /*!< SYS_T::PMUCR: RTPPDEN Position */ +#define SYS_PMUCR_RTPPDEN_Msk (0x1ul << SYS_PMUCR_RTPPDEN_Pos) /*!< SYS_T::PMUCR: RTPPDEN Mask */ + +#define SYS_PMUCR_RTPDBPDEN_Pos (26) /*!< SYS_T::PMUCR: RTPDBPDEN Position */ +#define SYS_PMUCR_RTPDBPDEN_Msk (0x1ul << SYS_PMUCR_RTPDBPDEN_Pos) /*!< SYS_T::PMUCR: RTPDBPDEN Mask */ + +#define SYS_DDRCQCSR_AXIQBYPAS_Pos (0) /*!< SYS_T::DDRCQCSR: AXIQBYPAS Position */ +#define SYS_DDRCQCSR_AXIQBYPAS_Msk (0xfful << SYS_DDRCQCSR_AXIQBYPAS_Pos) /*!< SYS_T::DDRCQCSR: AXIQBYPAS Mask */ + +#define SYS_DDRCQCSR_AXIQDENYIF_Pos (8) /*!< SYS_T::DDRCQCSR: AXIQDENYIF Position */ +#define SYS_DDRCQCSR_AXIQDENYIF_Msk (0xfful << SYS_DDRCQCSR_AXIQDENYIF_Pos) /*!< SYS_T::DDRCQCSR: AXIQDENYIF Mask */ + +#define SYS_DDRCQCSR_DDRCQBYPAS_Pos (16) /*!< SYS_T::DDRCQCSR: DDRCQBYPAS Position */ +#define SYS_DDRCQCSR_DDRCQBYPAS_Msk (0x1ul << SYS_DDRCQCSR_DDRCQBYPAS_Pos) /*!< SYS_T::DDRCQCSR: DDRCQBYPAS Mask */ + +#define SYS_DDRCQCSR_DDRCQDENYIF_Pos (17) /*!< SYS_T::DDRCQCSR: DDRCQDENYIF Position */ +#define SYS_DDRCQCSR_DDRCQDENYIF_Msk (0x1ul << SYS_DDRCQCSR_DDRCQDENYIF_Pos) /*!< SYS_T::DDRCQCSR: DDRCQDENYIF Mask */ + +#define SYS_DDRCQCSR_DDRQREQDLY_Pos (24) /*!< SYS_T::DDRCQCSR: DDRQREQDLY Position */ +#define SYS_DDRCQCSR_DDRQREQDLY_Msk (0xful << SYS_DDRCQCSR_DDRQREQDLY_Pos) /*!< SYS_T::DDRCQCSR: DDRQREQDLY Mask */ + +#define SYS_DDRCQCSR_DDRQACKTO_Pos (28) /*!< SYS_T::DDRCQCSR: DDRQACKTO Position */ +#define SYS_DDRCQCSR_DDRQACKTO_Msk (0xful << SYS_DDRCQCSR_DDRQACKTO_Pos) /*!< SYS_T::DDRCQCSR: DDRQACKTO Mask */ + +#define SYS_PMUIEN_PMUIEN_Pos (0) /*!< SYS_T::PMUIEN: PMUIEN Position */ +#define SYS_PMUIEN_PMUIEN_Msk (0x1ul << SYS_PMUIEN_PMUIEN_Pos) /*!< SYS_T::PMUIEN: PMUIEN Mask */ + +#define SYS_PMUIEN_A35PDWKIEN_Pos (8) /*!< SYS_T::PMUIEN: A35PDWKIEN Position */ +#define SYS_PMUIEN_A35PDWKIEN_Msk (0x1ul << SYS_PMUIEN_A35PDWKIEN_Pos) /*!< SYS_T::PMUIEN: A35PDWKIEN Mask */ + +#define SYS_PMUIEN_RTPPDWKIEN_Pos (12) /*!< SYS_T::PMUIEN: RTPPDWKIEN Position */ +#define SYS_PMUIEN_RTPPDWKIEN_Msk (0x1ul << SYS_PMUIEN_RTPPDWKIEN_Pos) /*!< SYS_T::PMUIEN: RTPPDWKIEN Mask */ + +#define SYS_PMUSTS_PMUIF_Pos (0) /*!< SYS_T::PMUSTS: PMUIF Position */ +#define SYS_PMUSTS_PMUIF_Msk (0x1ul << SYS_PMUSTS_PMUIF_Pos) /*!< SYS_T::PMUSTS: PMUIF Mask */ + +#define SYS_PMUSTS_PGTOIF_Pos (1) /*!< SYS_T::PMUSTS: PGTOIF Position */ +#define SYS_PMUSTS_PGTOIF_Msk (0x1ul << SYS_PMUSTS_PGTOIF_Pos) /*!< SYS_T::PMUSTS: PGTOIF Mask */ + +#define SYS_PMUSTS_L2FDONE_Pos (5) /*!< SYS_T::PMUSTS: L2FDONE Position */ +#define SYS_PMUSTS_L2FDONE_Msk (0x1ul << SYS_PMUSTS_L2FDONE_Pos) /*!< SYS_T::PMUSTS: L2FDONE Mask */ + +#define SYS_PMUSTS_A35PDWKIF_Pos (8) /*!< SYS_T::PMUSTS: A35PDWKIF Position */ +#define SYS_PMUSTS_A35PDWKIF_Msk (0x1ul << SYS_PMUSTS_A35PDWKIF_Pos) /*!< SYS_T::PMUSTS: A35PDWKIF Mask */ + +#define SYS_PMUSTS_RTPPDWKIF_Pos (12) /*!< SYS_T::PMUSTS: RTPPDWKIF Position */ +#define SYS_PMUSTS_RTPPDWKIF_Msk (0x1ul << SYS_PMUSTS_RTPPDWKIF_Pos) /*!< SYS_T::PMUSTS: RTPPDWKIF Mask */ + +#define SYS_PMUSTS_PWRACKCNT_Pos (16) /*!< SYS_T::PMUSTS: PWRACKCNT Position */ +#define SYS_PMUSTS_PWRACKCNT_Msk (0xfffful << SYS_PMUSTS_PWRACKCNT_Pos) /*!< SYS_T::PMUSTS: PWRACKCNT Mask */ + +#define SYS_CA35WRBADR0_WRMBTADDR_Pos (0) /*!< SYS_T::CA35WRBADR0: WRMBTADDR Position */ +#define SYS_CA35WRBADR0_WRMBTADDR_Msk (0xfffffffful << SYS_CA35WRBADR0_WRMBTADDR_Pos) /*!< SYS_T::CA35WRBADR0: WRMBTADDR Mask */ + +#define SYS_CA35WRBPAR0_WRMBTPARA_Pos (0) /*!< SYS_T::CA35WRBPAR0: WRMBTPARA Position */ +#define SYS_CA35WRBPAR0_WRMBTPARA_Msk (0xfffffffful << SYS_CA35WRBPAR0_WRMBTPARA_Pos) /*!< SYS_T::CA35WRBPAR0: WRMBTPARA Mask */ + +#define SYS_CA35WRBADR1_WRMBTADDR_Pos (0) /*!< SYS_T::CA35WRBADR1: WRMBTADDR Position */ +#define SYS_CA35WRBADR1_WRMBTADDR_Msk (0xfffffffful << SYS_CA35WRBADR1_WRMBTADDR_Pos) /*!< SYS_T::CA35WRBADR1: WRMBTADDR Mask */ + +#define SYS_CA35WRBPAR1_WRMBTPARA_Pos (0) /*!< SYS_T::CA35WRBPAR1: WRMBTPARA Position */ +#define SYS_CA35WRBPAR1_WRMBTPARA_Msk (0xfffffffful << SYS_CA35WRBPAR1_WRMBTPARA_Pos) /*!< SYS_T::CA35WRBPAR1: WRMBTPARA Mask */ + +#define SYS_USBPMISCR_PHY0POR_Pos (0) /*!< SYS_T::USBPMISCR: PHY0POR Position */ +#define SYS_USBPMISCR_PHY0POR_Msk (0x1ul << SYS_USBPMISCR_PHY0POR_Pos) /*!< SYS_T::USBPMISCR: PHY0POR Mask */ + +#define SYS_USBPMISCR_PHY0SUSPEND_Pos (1) /*!< SYS_T::USBPMISCR: PHY0SUSPEND Position */ +#define SYS_USBPMISCR_PHY0SUSPEND_Msk (0x1ul << SYS_USBPMISCR_PHY0SUSPEND_Pos) /*!< SYS_T::USBPMISCR: PHY0SUSPEND Mask */ + +#define SYS_USBPMISCR_PHY0COMN_Pos (2) /*!< SYS_T::USBPMISCR: PHY0COMN Position */ +#define SYS_USBPMISCR_PHY0COMN_Msk (0x1ul << SYS_USBPMISCR_PHY0COMN_Pos) /*!< SYS_T::USBPMISCR: PHY0COMN Mask */ + +#define SYS_USBPMISCR_VBUSDGSEL_Pos (4) /*!< SYS_T::USBPMISCR: VBUSDGSEL Position */ +#define SYS_USBPMISCR_VBUSDGSEL_Msk (0x7ul << SYS_USBPMISCR_VBUSDGSEL_Pos) /*!< SYS_T::USBPMISCR: VBUSDGSEL Mask */ + +#define SYS_USBPMISCR_EFUSESEL0_Pos (7) /*!< SYS_T::USBPMISCR: EFUSESEL0 Position */ +#define SYS_USBPMISCR_EFUSESEL0_Msk (0x1ul << SYS_USBPMISCR_EFUSESEL0_Pos) /*!< SYS_T::USBPMISCR: EFUSESEL0 Mask */ + +#define SYS_USBPMISCR_PHY0HSTCKSTB_Pos (8) /*!< SYS_T::USBPMISCR: PHY0HSTCKSTB Position*/ +#define SYS_USBPMISCR_PHY0HSTCKSTB_Msk (0x1ul << SYS_USBPMISCR_PHY0HSTCKSTB_Pos) /*!< SYS_T::USBPMISCR: PHY0HSTCKSTB Mask */ + +#define SYS_USBPMISCR_PHY0CK12MSTB_Pos (9) /*!< SYS_T::USBPMISCR: PHY0CK12MSTB Position*/ +#define SYS_USBPMISCR_PHY0CK12MSTB_Msk (0x1ul << SYS_USBPMISCR_PHY0CK12MSTB_Pos) /*!< SYS_T::USBPMISCR: PHY0CK12MSTB Mask */ + +#define SYS_USBPMISCR_PHY0DEVCKSTB_Pos (10) /*!< SYS_T::USBPMISCR: PHY0DEVCKSTB Position*/ +#define SYS_USBPMISCR_PHY0DEVCKSTB_Msk (0x1ul << SYS_USBPMISCR_PHY0DEVCKSTB_Pos) /*!< SYS_T::USBPMISCR: PHY0DEVCKSTB Mask */ + +#define SYS_USBPMISCR_RTUNESEL0_Pos (11) /*!< SYS_T::USBPMISCR: RTUNESEL0 Position */ +#define SYS_USBPMISCR_RTUNESEL0_Msk (0x1ul << SYS_USBPMISCR_RTUNESEL0_Pos) /*!< SYS_T::USBPMISCR: RTUNESEL0 Mask */ + +#define SYS_USBPMISCR_RCALCODE0_Pos (12) /*!< SYS_T::USBPMISCR: RCALCODE0 Position */ +#define SYS_USBPMISCR_RCALCODE0_Msk (0xful << SYS_USBPMISCR_RCALCODE0_Pos) /*!< SYS_T::USBPMISCR: RCALCODE0 Mask */ + +#define SYS_USBPMISCR_PHY1POR_Pos (16) /*!< SYS_T::USBPMISCR: PHY1POR Position */ +#define SYS_USBPMISCR_PHY1POR_Msk (0x1ul << SYS_USBPMISCR_PHY1POR_Pos) /*!< SYS_T::USBPMISCR: PHY1POR Mask */ + +#define SYS_USBPMISCR_PHY1SUSPEND_Pos (17) /*!< SYS_T::USBPMISCR: PHY1SUSPEND Position */ +#define SYS_USBPMISCR_PHY1SUSPEND_Msk (0x1ul << SYS_USBPMISCR_PHY1SUSPEND_Pos) /*!< SYS_T::USBPMISCR: PHY1SUSPEND Mask */ + +#define SYS_USBPMISCR_PHY1COMN_Pos (18) /*!< SYS_T::USBPMISCR: PHY1COMN Position */ +#define SYS_USBPMISCR_PHY1COMN_Msk (0x1ul << SYS_USBPMISCR_PHY1COMN_Pos) /*!< SYS_T::USBPMISCR: PHY1COMN Mask */ + +#define SYS_USBPMISCR_EFUSESEL1_Pos (23) /*!< SYS_T::USBPMISCR: EFUSESEL1 Position */ +#define SYS_USBPMISCR_EFUSESEL1_Msk (0x1ul << SYS_USBPMISCR_EFUSESEL1_Pos) /*!< SYS_T::USBPMISCR: EFUSESEL1 Mask */ + +#define SYS_USBPMISCR_PHY1HSTCKSTB_Pos (24) /*!< SYS_T::USBPMISCR: PHY1HSTCKSTB Position*/ +#define SYS_USBPMISCR_PHY1HSTCKSTB_Msk (0x1ul << SYS_USBPMISCR_PHY1HSTCKSTB_Pos) /*!< SYS_T::USBPMISCR: PHY1HSTCKSTB Mask */ + +#define SYS_USBPMISCR_PHY1CK12MSTB_Pos (25) /*!< SYS_T::USBPMISCR: PHY1CK12MSTB Position*/ +#define SYS_USBPMISCR_PHY1CK12MSTB_Msk (0x1ul << SYS_USBPMISCR_PHY1CK12MSTB_Pos) /*!< SYS_T::USBPMISCR: PHY1CK12MSTB Mask */ + +#define SYS_USBPMISCR_RTUNESEL1_Pos (27) /*!< SYS_T::USBPMISCR: RTUNESEL1 Position */ +#define SYS_USBPMISCR_RTUNESEL1_Msk (0x1ul << SYS_USBPMISCR_RTUNESEL1_Pos) /*!< SYS_T::USBPMISCR: RTUNESEL1 Mask */ + +#define SYS_USBPMISCR_RCALCODE1_Pos (28) /*!< SYS_T::USBPMISCR: RCALCODE1 Position */ +#define SYS_USBPMISCR_RCALCODE1_Msk (0xful << SYS_USBPMISCR_RCALCODE1_Pos) /*!< SYS_T::USBPMISCR: RCALCODE1 Mask */ + +#define SYS_USBP0PCR_COMPDISTUNE_Pos (0) /*!< SYS_T::USBP0PCR: COMPDISTUNE Position */ +#define SYS_USBP0PCR_COMPDISTUNE_Msk (0x7ul << SYS_USBP0PCR_COMPDISTUNE_Pos) /*!< SYS_T::USBP0PCR: COMPDISTUNE Mask */ + +#define SYS_USBP0PCR_EQBYPASSENB_Pos (3) /*!< SYS_T::USBP0PCR: EQBYPASSENB Position */ +#define SYS_USBP0PCR_EQBYPASSENB_Msk (0x1ul << SYS_USBP0PCR_EQBYPASSENB_Pos) /*!< SYS_T::USBP0PCR: EQBYPASSENB Mask */ + +#define SYS_USBP0PCR_SQRXTUNE_Pos (4) /*!< SYS_T::USBP0PCR: SQRXTUNE Position */ +#define SYS_USBP0PCR_SQRXTUNE_Msk (0x7ul << SYS_USBP0PCR_SQRXTUNE_Pos) /*!< SYS_T::USBP0PCR: SQRXTUNE Mask */ + +#define SYS_USBP0PCR_TXPREEMPPULSETUNE_Pos (7) /*!< SYS_T::USBP0PCR: TXPREEMPPULSETUNE Position*/ +#define SYS_USBP0PCR_TXPREEMPPULSETUNE_Msk (0x1ul << SYS_USBP0PCR_TXPREEMPPULSETUNE_Pos) /*!< SYS_T::USBP0PCR: TXPREEMPPULSETUNE Mask*/ + +#define SYS_USBP0PCR_PLLPTUNE_Pos (8) /*!< SYS_T::USBP0PCR: PLLPTUNE Position */ +#define SYS_USBP0PCR_PLLPTUNE_Msk (0xful << SYS_USBP0PCR_PLLPTUNE_Pos) /*!< SYS_T::USBP0PCR: PLLPTUNE Mask */ + +#define SYS_USBP0PCR_TXFSLSTUNE_Pos (12) /*!< SYS_T::USBP0PCR: TXFSLSTUNE Position */ +#define SYS_USBP0PCR_TXFSLSTUNE_Msk (0xful << SYS_USBP0PCR_TXFSLSTUNE_Pos) /*!< SYS_T::USBP0PCR: TXFSLSTUNE Mask */ + +#define SYS_USBP0PCR_PLLITUNE_Pos (16) /*!< SYS_T::USBP0PCR: PLLITUNE Position */ +#define SYS_USBP0PCR_PLLITUNE_Msk (0x3ul << SYS_USBP0PCR_PLLITUNE_Pos) /*!< SYS_T::USBP0PCR: PLLITUNE Mask */ + +#define SYS_USBP0PCR_TXPREEMPAMPTUNE_Pos (20) /*!< SYS_T::USBP0PCR: TXPREEMPAMPTUNE Position*/ +#define SYS_USBP0PCR_TXPREEMPAMPTUNE_Msk (0x3ul << SYS_USBP0PCR_TXPREEMPAMPTUNE_Pos) /*!< SYS_T::USBP0PCR: TXPREEMPAMPTUNE Mask */ + +#define SYS_USBP0PCR_TXRISETUNE_Pos (22) /*!< SYS_T::USBP0PCR: TXRISETUNE Position */ +#define SYS_USBP0PCR_TXRISETUNE_Msk (0x3ul << SYS_USBP0PCR_TXRISETUNE_Pos) /*!< SYS_T::USBP0PCR: TXRISETUNE Mask */ + +#define SYS_USBP0PCR_TXVREFTUNE_Pos (24) /*!< SYS_T::USBP0PCR: TXVREFTUNE Position */ +#define SYS_USBP0PCR_TXVREFTUNE_Msk (0xful << SYS_USBP0PCR_TXVREFTUNE_Pos) /*!< SYS_T::USBP0PCR: TXVREFTUNE Mask */ + +#define SYS_USBP0PCR_TXHSXVTUNE_Pos (28) /*!< SYS_T::USBP0PCR: TXHSXVTUNE Position */ +#define SYS_USBP0PCR_TXHSXVTUNE_Msk (0x3ul << SYS_USBP0PCR_TXHSXVTUNE_Pos) /*!< SYS_T::USBP0PCR: TXHSXVTUNE Mask */ + +#define SYS_USBP0PCR_TXRESTUNE_Pos (30) /*!< SYS_T::USBP0PCR: TXRESTUNE Position */ +#define SYS_USBP0PCR_TXRESTUNE_Msk (0x3ul << SYS_USBP0PCR_TXRESTUNE_Pos) /*!< SYS_T::USBP0PCR: TXRESTUNE Mask */ + +#define SYS_USBP1PCR_COMPDISTUNE_Pos (0) /*!< SYS_T::USBP1PCR: COMPDISTUNE Position */ +#define SYS_USBP1PCR_COMPDISTUNE_Msk (0x7ul << SYS_USBP1PCR_COMPDISTUNE_Pos) /*!< SYS_T::USBP1PCR: COMPDISTUNE Mask */ + +#define SYS_USBP1PCR_EQBYPASSENB_Pos (3) /*!< SYS_T::USBP1PCR: EQBYPASSENB Position */ +#define SYS_USBP1PCR_EQBYPASSENB_Msk (0x1ul << SYS_USBP1PCR_EQBYPASSENB_Pos) /*!< SYS_T::USBP1PCR: EQBYPASSENB Mask */ + +#define SYS_USBP1PCR_SQRXTUNE_Pos (4) /*!< SYS_T::USBP1PCR: SQRXTUNE Position */ +#define SYS_USBP1PCR_SQRXTUNE_Msk (0x7ul << SYS_USBP1PCR_SQRXTUNE_Pos) /*!< SYS_T::USBP1PCR: SQRXTUNE Mask */ + +#define SYS_USBP1PCR_TXPREEMPPULSETUNE_Pos (7) /*!< SYS_T::USBP1PCR: TXPREEMPPULSETUNE Position*/ +#define SYS_USBP1PCR_TXPREEMPPULSETUNE_Msk (0x1ul << SYS_USBP1PCR_TXPREEMPPULSETUNE_Pos) /*!< SYS_T::USBP1PCR: TXPREEMPPULSETUNE Mask*/ + +#define SYS_USBP1PCR_PLLPTUNE_Pos (8) /*!< SYS_T::USBP1PCR: PLLPTUNE Position */ +#define SYS_USBP1PCR_PLLPTUNE_Msk (0xful << SYS_USBP1PCR_PLLPTUNE_Pos) /*!< SYS_T::USBP1PCR: PLLPTUNE Mask */ + +#define SYS_USBP1PCR_TXFSLSTUNE_Pos (12) /*!< SYS_T::USBP1PCR: TXFSLSTUNE Position */ +#define SYS_USBP1PCR_TXFSLSTUNE_Msk (0xful << SYS_USBP1PCR_TXFSLSTUNE_Pos) /*!< SYS_T::USBP1PCR: TXFSLSTUNE Mask */ + +#define SYS_USBP1PCR_PLLITUNE_Pos (16) /*!< SYS_T::USBP1PCR: PLLITUNE Position */ +#define SYS_USBP1PCR_PLLITUNE_Msk (0x3ul << SYS_USBP1PCR_PLLITUNE_Pos) /*!< SYS_T::USBP1PCR: PLLITUNE Mask */ + +#define SYS_USBP1PCR_TXPREEMPAMPTUNE_Pos (20) /*!< SYS_T::USBP1PCR: TXPREEMPAMPTUNE Position*/ +#define SYS_USBP1PCR_TXPREEMPAMPTUNE_Msk (0x3ul << SYS_USBP1PCR_TXPREEMPAMPTUNE_Pos) /*!< SYS_T::USBP1PCR: TXPREEMPAMPTUNE Mask */ + +#define SYS_USBP1PCR_TXRISETUNE_Pos (22) /*!< SYS_T::USBP1PCR: TXRISETUNE Position */ +#define SYS_USBP1PCR_TXRISETUNE_Msk (0x3ul << SYS_USBP1PCR_TXRISETUNE_Pos) /*!< SYS_T::USBP1PCR: TXRISETUNE Mask */ + +#define SYS_USBP1PCR_TXVREFTUNE_Pos (24) /*!< SYS_T::USBP1PCR: TXVREFTUNE Position */ +#define SYS_USBP1PCR_TXVREFTUNE_Msk (0xful << SYS_USBP1PCR_TXVREFTUNE_Pos) /*!< SYS_T::USBP1PCR: TXVREFTUNE Mask */ + +#define SYS_USBP1PCR_TXHSXVTUNE_Pos (28) /*!< SYS_T::USBP1PCR: TXHSXVTUNE Position */ +#define SYS_USBP1PCR_TXHSXVTUNE_Msk (0x3ul << SYS_USBP1PCR_TXHSXVTUNE_Pos) /*!< SYS_T::USBP1PCR: TXHSXVTUNE Mask */ + +#define SYS_USBP1PCR_TXRESTUNE_Pos (30) /*!< SYS_T::USBP1PCR: TXRESTUNE Position */ +#define SYS_USBP1PCR_TXRESTUNE_Msk (0x3ul << SYS_USBP1PCR_TXRESTUNE_Pos) /*!< SYS_T::USBP1PCR: TXRESTUNE Mask */ + +#define SYS_MISCFCR0_RTPICACHEN_Pos (0) /*!< SYS_T::MISCFCR0: RTPICACHEN Position */ +#define SYS_MISCFCR0_RTPICACHEN_Msk (0x1ul << SYS_MISCFCR0_RTPICACHEN_Pos) /*!< SYS_T::MISCFCR0: RTPICACHEN Mask */ + +#define SYS_MISCFCR0_RTPDCACHEN_Pos (1) /*!< SYS_T::MISCFCR0: RTPDCACHEN Position */ +#define SYS_MISCFCR0_RTPDCACHEN_Msk (0x1ul << SYS_MISCFCR0_RTPDCACHEN_Pos) /*!< SYS_T::MISCFCR0: RTPDCACHEN Mask */ + +#define SYS_MISCFCR0_RTPDRMAEN_Pos (2) /*!< SYS_T::MISCFCR0: RTPDRMAEN Position */ +#define SYS_MISCFCR0_RTPDRMAEN_Msk (0x1ul << SYS_MISCFCR0_RTPDRMAEN_Pos) /*!< SYS_T::MISCFCR0: RTPDRMAEN Mask */ + +#define SYS_MISCFCR0_WDT0RSTEN_Pos (8) /*!< SYS_T::MISCFCR0: WDT0RSTEN Position */ +#define SYS_MISCFCR0_WDT0RSTEN_Msk (0x1ul << SYS_MISCFCR0_WDT0RSTEN_Pos) /*!< SYS_T::MISCFCR0: WDT0RSTEN Mask */ + +#define SYS_MISCFCR0_HDSPUEN_Pos (9) /*!< SYS_T::MISCFCR0: HDSPUEN Position */ +#define SYS_MISCFCR0_HDSPUEN_Msk (0x1ul << SYS_MISCFCR0_HDSPUEN_Pos) /*!< SYS_T::MISCFCR0: HDSPUEN Mask */ + +#define SYS_MISCFCR0_UHOVRCURH_Pos (12) /*!< SYS_T::MISCFCR0: UHOVRCURH Position */ +#define SYS_MISCFCR0_UHOVRCURH_Msk (0x1ul << SYS_MISCFCR0_UHOVRCURH_Pos) /*!< SYS_T::MISCFCR0: UHOVRCURH Mask */ + +#define SYS_MISCFCR0_SELFTEST_Pos (13) /*!< SYS_T::MISCFCR0: SELFTEST Position */ +#define SYS_MISCFCR0_SELFTEST_Msk (0x1ul << SYS_MISCFCR0_SELFTEST_Pos) /*!< SYS_T::MISCFCR0: SELFTEST Mask */ + +#define SYS_MISCFCR0_WDT1RSTEN_Pos (14) /*!< SYS_T::MISCFCR0: WDT1RSTEN Position */ +#define SYS_MISCFCR0_WDT1RSTEN_Msk (0x1ul << SYS_MISCFCR0_WDT1RSTEN_Pos) /*!< SYS_T::MISCFCR0: WDT1RSTEN Mask */ + +#define SYS_MISCFCR0_WDT2RSTEN_Pos (15) /*!< SYS_T::MISCFCR0: WDT2RSTEN Position */ +#define SYS_MISCFCR0_WDT2RSTEN_Msk (0x1ul << SYS_MISCFCR0_WDT2RSTEN_Pos) /*!< SYS_T::MISCFCR0: WDT2RSTEN Mask */ + +#define SYS_MISCFCR0_SDH0VSTB_Pos (16) /*!< SYS_T::MISCFCR0: SDH0VSTB Position */ +#define SYS_MISCFCR0_SDH0VSTB_Msk (0x1ul << SYS_MISCFCR0_SDH0VSTB_Pos) /*!< SYS_T::MISCFCR0: SDH0VSTB Mask */ + +#define SYS_MISCFCR0_SDH1VSTB_Pos (17) /*!< SYS_T::MISCFCR0: SDH1VSTB Position */ +#define SYS_MISCFCR0_SDH1VSTB_Msk (0x1ul << SYS_MISCFCR0_SDH1VSTB_Pos) /*!< SYS_T::MISCFCR0: SDH1VSTB Mask */ + +#define SYS_MISCFCR0_VBUSWKEN_Pos (18) /*!< SYS_T::MISCFCR0: VBUSWKEN Position */ +#define SYS_MISCFCR0_VBUSWKEN_Msk (0x1ul << SYS_MISCFCR0_VBUSWKEN_Pos) /*!< SYS_T::MISCFCR0: VBUSWKEN Mask */ + +#define SYS_MISCFCR0_LNSTWKEN_Pos (19) /*!< SYS_T::MISCFCR0: LNSTWKEN Position */ +#define SYS_MISCFCR0_LNSTWKEN_Msk (0x1ul << SYS_MISCFCR0_LNSTWKEN_Pos) /*!< SYS_T::MISCFCR0: LNSTWKEN Mask */ + +#define SYS_MISCFCR0_DDRCGDIS_Pos (23) /*!< SYS_T::MISCFCR0: DDRCGDIS Position */ +#define SYS_MISCFCR0_DDRCGDIS_Msk (0x1ul << SYS_MISCFCR0_DDRCGDIS_Pos) /*!< SYS_T::MISCFCR0: DDRCGDIS Mask */ + +#define SYS_MISCFCR0_DRATSRDLY_Pos (24) /*!< SYS_T::MISCFCR0: DRATSRDLY Position */ +#define SYS_MISCFCR0_DRATSRDLY_Msk (0xfful << SYS_MISCFCR0_DRATSRDLY_Pos) /*!< SYS_T::MISCFCR0: DRATSRDLY Mask */ + +#define SYS_MISCFCR1_CANFD0PDEN_Pos (0) /*!< SYS_T::MISCFCR1: CANFD0PDEN Position */ +#define SYS_MISCFCR1_CANFD0PDEN_Msk (0x1ul << SYS_MISCFCR1_CANFD0PDEN_Pos) /*!< SYS_T::MISCFCR1: CANFD0PDEN Mask */ + +#define SYS_MISCFCR1_CANFD1PDEN_Pos (1) /*!< SYS_T::MISCFCR1: CANFD1PDEN Position */ +#define SYS_MISCFCR1_CANFD1PDEN_Msk (0x1ul << SYS_MISCFCR1_CANFD1PDEN_Pos) /*!< SYS_T::MISCFCR1: CANFD1PDEN Mask */ + +#define SYS_MISCFCR1_CANFD2PDEN_Pos (2) /*!< SYS_T::MISCFCR1: CANFD2PDEN Position */ +#define SYS_MISCFCR1_CANFD2PDEN_Msk (0x1ul << SYS_MISCFCR1_CANFD2PDEN_Pos) /*!< SYS_T::MISCFCR1: CANFD2PDEN Mask */ + +#define SYS_MISCFCR1_CANFD3PDEN_Pos (3) /*!< SYS_T::MISCFCR1: CANFD3PDEN Position */ +#define SYS_MISCFCR1_CANFD3PDEN_Msk (0x1ul << SYS_MISCFCR1_CANFD3PDEN_Pos) /*!< SYS_T::MISCFCR1: CANFD3PDEN Mask */ + +#define SYS_MISCFCR1_CANFD0CKSTP_Pos (4) /*!< SYS_T::MISCFCR1: CANFD0CKSTP Position */ +#define SYS_MISCFCR1_CANFD0CKSTP_Msk (0x1ul << SYS_MISCFCR1_CANFD0CKSTP_Pos) /*!< SYS_T::MISCFCR1: CANFD0CKSTP Mask */ + +#define SYS_MISCFCR1_CANFD1CKSTP_Pos (5) /*!< SYS_T::MISCFCR1: CANFD1CKSTP Position */ +#define SYS_MISCFCR1_CANFD1CKSTP_Msk (0x1ul << SYS_MISCFCR1_CANFD1CKSTP_Pos) /*!< SYS_T::MISCFCR1: CANFD1CKSTP Mask */ + +#define SYS_MISCFCR1_CANFD2CKSTP_Pos (6) /*!< SYS_T::MISCFCR1: CANFD2CKSTP Position */ +#define SYS_MISCFCR1_CANFD2CKSTP_Msk (0x1ul << SYS_MISCFCR1_CANFD2CKSTP_Pos) /*!< SYS_T::MISCFCR1: CANFD2CKSTP Mask */ + +#define SYS_MISCFCR1_CANFD3CKSTP_Pos (7) /*!< SYS_T::MISCFCR1: CANFD3CKSTP Position */ +#define SYS_MISCFCR1_CANFD3CKSTP_Msk (0x1ul << SYS_MISCFCR1_CANFD3CKSTP_Pos) /*!< SYS_T::MISCFCR1: CANFD3CKSTP Mask */ + +#define SYS_MISCFCR1_HXTDS_Pos (8) /*!< SYS_T::MISCFCR1: HXTDS Position */ +#define SYS_MISCFCR1_HXTDS_Msk (0x3ul << SYS_MISCFCR1_HXTDS_Pos) /*!< SYS_T::MISCFCR1: HXTDS Mask */ + +#define SYS_MISCFCR1_TSENSRTRIM_Pos (12) /*!< SYS_T::MISCFCR1: TSENSRTRIM Position */ +#define SYS_MISCFCR1_TSENSRTRIM_Msk (0xful << SYS_MISCFCR1_TSENSRTRIM_Pos) /*!< SYS_T::MISCFCR1: TSENSRTRIM Mask */ + +#define SYS_MISCFCR1_RMEL1RAM_Pos (16) /*!< SYS_T::MISCFCR1: RMEL1RAM Position */ +#define SYS_MISCFCR1_RMEL1RAM_Msk (0x1ul << SYS_MISCFCR1_RMEL1RAM_Pos) /*!< SYS_T::MISCFCR1: RMEL1RAM Mask */ + +#define SYS_MISCFCR1_RMESYSRAM_Pos (17) /*!< SYS_T::MISCFCR1: RMESYSRAM Position */ +#define SYS_MISCFCR1_RMESYSRAM_Msk (0x1ul << SYS_MISCFCR1_RMESYSRAM_Pos) /*!< SYS_T::MISCFCR1: RMESYSRAM Mask */ + +#define SYS_MISCIER_LVDIEN_Pos (0) /*!< SYS_T::MISCIER: LVDIEN Position */ +#define SYS_MISCIER_LVDIEN_Msk (0x1ul << SYS_MISCIER_LVDIEN_Pos) /*!< SYS_T::MISCIER: LVDIEN Mask */ + +#define SYS_MISCIER_USB0IDCHGIEN_Pos (1) /*!< SYS_T::MISCIER: USB0IDCHGIEN Position */ +#define SYS_MISCIER_USB0IDCHGIEN_Msk (0x1ul << SYS_MISCIER_USB0IDCHGIEN_Pos) /*!< SYS_T::MISCIER: USB0IDCHGIEN Mask */ + +#define SYS_MISCIER_VBUSCHGIEN_Pos (2) /*!< SYS_T::MISCIER: VBUSCHGIEN Position */ +#define SYS_MISCIER_VBUSCHGIEN_Msk (0x1ul << SYS_MISCIER_VBUSCHGIEN_Pos) /*!< SYS_T::MISCIER: VBUSCHGIEN Mask */ + +#define SYS_MISCISR_LVDIF_Pos (0) /*!< SYS_T::MISCISR: LVDIF Position */ +#define SYS_MISCISR_LVDIF_Msk (0x1ul << SYS_MISCISR_LVDIF_Pos) /*!< SYS_T::MISCISR: LVDIF Mask */ + +#define SYS_MISCISR_USB0IDCHGIF_Pos (1) /*!< SYS_T::MISCISR: USB0IDCHGIF Position */ +#define SYS_MISCISR_USB0IDCHGIF_Msk (0x1ul << SYS_MISCISR_USB0IDCHGIF_Pos) /*!< SYS_T::MISCISR: USB0IDCHGIF Mask */ + +#define SYS_MISCISR_VBUSCHGIF_Pos (2) /*!< SYS_T::MISCISR: VBUSCHGIF Position */ +#define SYS_MISCISR_VBUSCHGIF_Msk (0x1ul << SYS_MISCISR_VBUSCHGIF_Pos) /*!< SYS_T::MISCISR: VBUSCHGIF Mask */ + +#define SYS_MISCISR_LVDSTS_Pos (16) /*!< SYS_T::MISCISR: LVDSTS Position */ +#define SYS_MISCISR_LVDSTS_Msk (0x1ul << SYS_MISCISR_LVDSTS_Pos) /*!< SYS_T::MISCISR: LVDSTS Mask */ + +#define SYS_MISCISR_USB0IDSTS_Pos (17) /*!< SYS_T::MISCISR: USB0IDSTS Position */ +#define SYS_MISCISR_USB0IDSTS_Msk (0x1ul << SYS_MISCISR_USB0IDSTS_Pos) /*!< SYS_T::MISCISR: USB0IDSTS Mask */ + +#define SYS_MISCISR_VBUSSTS_Pos (18) /*!< SYS_T::MISCISR: VBUSSTS Position */ +#define SYS_MISCISR_VBUSSTS_Msk (0x1ul << SYS_MISCISR_VBUSSTS_Pos) /*!< SYS_T::MISCISR: VBUSSTS Mask */ + +#define SYS_GPA_MFPL_PA0MFP_Pos (0) /*!< SYS_T::GPA_MFPL: PA0MFP Position */ +#define SYS_GPA_MFPL_PA0MFP_Msk (0xful << SYS_GPA_MFPL_PA0MFP_Pos) /*!< SYS_T::GPA_MFPL: PA0MFP Mask */ + +#define SYS_GPA_MFPL_PA1MFP_Pos (4) /*!< SYS_T::GPA_MFPL: PA1MFP Position */ +#define SYS_GPA_MFPL_PA1MFP_Msk (0xful << SYS_GPA_MFPL_PA1MFP_Pos) /*!< SYS_T::GPA_MFPL: PA1MFP Mask */ + +#define SYS_GPA_MFPL_PA2MFP_Pos (8) /*!< SYS_T::GPA_MFPL: PA2MFP Position */ +#define SYS_GPA_MFPL_PA2MFP_Msk (0xful << SYS_GPA_MFPL_PA2MFP_Pos) /*!< SYS_T::GPA_MFPL: PA2MFP Mask */ + +#define SYS_GPA_MFPL_PA3MFP_Pos (12) /*!< SYS_T::GPA_MFPL: PA3MFP Position */ +#define SYS_GPA_MFPL_PA3MFP_Msk (0xful << SYS_GPA_MFPL_PA3MFP_Pos) /*!< SYS_T::GPA_MFPL: PA3MFP Mask */ + +#define SYS_GPA_MFPL_PA4MFP_Pos (16) /*!< SYS_T::GPA_MFPL: PA4MFP Position */ +#define SYS_GPA_MFPL_PA4MFP_Msk (0xful << SYS_GPA_MFPL_PA4MFP_Pos) /*!< SYS_T::GPA_MFPL: PA4MFP Mask */ + +#define SYS_GPA_MFPL_PA5MFP_Pos (20) /*!< SYS_T::GPA_MFPL: PA5MFP Position */ +#define SYS_GPA_MFPL_PA5MFP_Msk (0xful << SYS_GPA_MFPL_PA5MFP_Pos) /*!< SYS_T::GPA_MFPL: PA5MFP Mask */ + +#define SYS_GPA_MFPL_PA6MFP_Pos (24) /*!< SYS_T::GPA_MFPL: PA6MFP Position */ +#define SYS_GPA_MFPL_PA6MFP_Msk (0xful << SYS_GPA_MFPL_PA6MFP_Pos) /*!< SYS_T::GPA_MFPL: PA6MFP Mask */ + +#define SYS_GPA_MFPL_PA7MFP_Pos (28) /*!< SYS_T::GPA_MFPL: PA7MFP Position */ +#define SYS_GPA_MFPL_PA7MFP_Msk (0xful << SYS_GPA_MFPL_PA7MFP_Pos) /*!< SYS_T::GPA_MFPL: PA7MFP Mask */ + +#define SYS_GPA_MFPH_PA8MFP_Pos (0) /*!< SYS_T::GPA_MFPH: PA8MFP Position */ +#define SYS_GPA_MFPH_PA8MFP_Msk (0xful << SYS_GPA_MFPH_PA8MFP_Pos) /*!< SYS_T::GPA_MFPH: PA8MFP Mask */ + +#define SYS_GPA_MFPH_PA9MFP_Pos (4) /*!< SYS_T::GPA_MFPH: PA9MFP Position */ +#define SYS_GPA_MFPH_PA9MFP_Msk (0xful << SYS_GPA_MFPH_PA9MFP_Pos) /*!< SYS_T::GPA_MFPH: PA9MFP Mask */ + +#define SYS_GPA_MFPH_PA10MFP_Pos (8) /*!< SYS_T::GPA_MFPH: PA10MFP Position */ +#define SYS_GPA_MFPH_PA10MFP_Msk (0xful << SYS_GPA_MFPH_PA10MFP_Pos) /*!< SYS_T::GPA_MFPH: PA10MFP Mask */ + +#define SYS_GPA_MFPH_PA11MFP_Pos (12) /*!< SYS_T::GPA_MFPH: PA11MFP Position */ +#define SYS_GPA_MFPH_PA11MFP_Msk (0xful << SYS_GPA_MFPH_PA11MFP_Pos) /*!< SYS_T::GPA_MFPH: PA11MFP Mask */ + +#define SYS_GPA_MFPH_PA12MFP_Pos (16) /*!< SYS_T::GPA_MFPH: PA12MFP Position */ +#define SYS_GPA_MFPH_PA12MFP_Msk (0xful << SYS_GPA_MFPH_PA12MFP_Pos) /*!< SYS_T::GPA_MFPH: PA12MFP Mask */ + +#define SYS_GPA_MFPH_PA13MFP_Pos (20) /*!< SYS_T::GPA_MFPH: PA13MFP Position */ +#define SYS_GPA_MFPH_PA13MFP_Msk (0xful << SYS_GPA_MFPH_PA13MFP_Pos) /*!< SYS_T::GPA_MFPH: PA13MFP Mask */ + +#define SYS_GPA_MFPH_PA14MFP_Pos (24) /*!< SYS_T::GPA_MFPH: PA14MFP Position */ +#define SYS_GPA_MFPH_PA14MFP_Msk (0xful << SYS_GPA_MFPH_PA14MFP_Pos) /*!< SYS_T::GPA_MFPH: PA14MFP Mask */ + +#define SYS_GPA_MFPH_PA15MFP_Pos (28) /*!< SYS_T::GPA_MFPH: PA15MFP Position */ +#define SYS_GPA_MFPH_PA15MFP_Msk (0xful << SYS_GPA_MFPH_PA15MFP_Pos) /*!< SYS_T::GPA_MFPH: PA15MFP Mask */ + +#define SYS_GPB_MFPL_PB0MFP_Pos (0) /*!< SYS_T::GPB_MFPL: PB0MFP Position */ +#define SYS_GPB_MFPL_PB0MFP_Msk (0xful << SYS_GPB_MFPL_PB0MFP_Pos) /*!< SYS_T::GPB_MFPL: PB0MFP Mask */ + +#define SYS_GPB_MFPL_PB1MFP_Pos (4) /*!< SYS_T::GPB_MFPL: PB1MFP Position */ +#define SYS_GPB_MFPL_PB1MFP_Msk (0xful << SYS_GPB_MFPL_PB1MFP_Pos) /*!< SYS_T::GPB_MFPL: PB1MFP Mask */ + +#define SYS_GPB_MFPL_PB2MFP_Pos (8) /*!< SYS_T::GPB_MFPL: PB2MFP Position */ +#define SYS_GPB_MFPL_PB2MFP_Msk (0xful << SYS_GPB_MFPL_PB2MFP_Pos) /*!< SYS_T::GPB_MFPL: PB2MFP Mask */ + +#define SYS_GPB_MFPL_PB3MFP_Pos (12) /*!< SYS_T::GPB_MFPL: PB3MFP Position */ +#define SYS_GPB_MFPL_PB3MFP_Msk (0xful << SYS_GPB_MFPL_PB3MFP_Pos) /*!< SYS_T::GPB_MFPL: PB3MFP Mask */ + +#define SYS_GPB_MFPL_PB4MFP_Pos (16) /*!< SYS_T::GPB_MFPL: PB4MFP Position */ +#define SYS_GPB_MFPL_PB4MFP_Msk (0xful << SYS_GPB_MFPL_PB4MFP_Pos) /*!< SYS_T::GPB_MFPL: PB4MFP Mask */ + +#define SYS_GPB_MFPL_PB5MFP_Pos (20) /*!< SYS_T::GPB_MFPL: PB5MFP Position */ +#define SYS_GPB_MFPL_PB5MFP_Msk (0xful << SYS_GPB_MFPL_PB5MFP_Pos) /*!< SYS_T::GPB_MFPL: PB5MFP Mask */ + +#define SYS_GPB_MFPL_PB6MFP_Pos (24) /*!< SYS_T::GPB_MFPL: PB6MFP Position */ +#define SYS_GPB_MFPL_PB6MFP_Msk (0xful << SYS_GPB_MFPL_PB6MFP_Pos) /*!< SYS_T::GPB_MFPL: PB6MFP Mask */ + +#define SYS_GPB_MFPL_PB7MFP_Pos (28) /*!< SYS_T::GPB_MFPL: PB7MFP Position */ +#define SYS_GPB_MFPL_PB7MFP_Msk (0xful << SYS_GPB_MFPL_PB7MFP_Pos) /*!< SYS_T::GPB_MFPL: PB7MFP Mask */ + +#define SYS_GPB_MFPH_PB8MFP_Pos (0) /*!< SYS_T::GPB_MFPH: PB8MFP Position */ +#define SYS_GPB_MFPH_PB8MFP_Msk (0xful << SYS_GPB_MFPH_PB8MFP_Pos) /*!< SYS_T::GPB_MFPH: PB8MFP Mask */ + +#define SYS_GPB_MFPH_PB9MFP_Pos (4) /*!< SYS_T::GPB_MFPH: PB9MFP Position */ +#define SYS_GPB_MFPH_PB9MFP_Msk (0xful << SYS_GPB_MFPH_PB9MFP_Pos) /*!< SYS_T::GPB_MFPH: PB9MFP Mask */ + +#define SYS_GPB_MFPH_PB10MFP_Pos (8) /*!< SYS_T::GPB_MFPH: PB10MFP Position */ +#define SYS_GPB_MFPH_PB10MFP_Msk (0xful << SYS_GPB_MFPH_PB10MFP_Pos) /*!< SYS_T::GPB_MFPH: PB10MFP Mask */ + +#define SYS_GPB_MFPH_PB11MFP_Pos (12) /*!< SYS_T::GPB_MFPH: PB11MFP Position */ +#define SYS_GPB_MFPH_PB11MFP_Msk (0xful << SYS_GPB_MFPH_PB11MFP_Pos) /*!< SYS_T::GPB_MFPH: PB11MFP Mask */ + +#define SYS_GPB_MFPH_PB12MFP_Pos (16) /*!< SYS_T::GPB_MFPH: PB12MFP Position */ +#define SYS_GPB_MFPH_PB12MFP_Msk (0xful << SYS_GPB_MFPH_PB12MFP_Pos) /*!< SYS_T::GPB_MFPH: PB12MFP Mask */ + +#define SYS_GPB_MFPH_PB13MFP_Pos (20) /*!< SYS_T::GPB_MFPH: PB13MFP Position */ +#define SYS_GPB_MFPH_PB13MFP_Msk (0xful << SYS_GPB_MFPH_PB13MFP_Pos) /*!< SYS_T::GPB_MFPH: PB13MFP Mask */ + +#define SYS_GPB_MFPH_PB14MFP_Pos (24) /*!< SYS_T::GPB_MFPH: PB14MFP Position */ +#define SYS_GPB_MFPH_PB14MFP_Msk (0xful << SYS_GPB_MFPH_PB14MFP_Pos) /*!< SYS_T::GPB_MFPH: PB14MFP Mask */ + +#define SYS_GPB_MFPH_PB15MFP_Pos (28) /*!< SYS_T::GPB_MFPH: PB15MFP Position */ +#define SYS_GPB_MFPH_PB15MFP_Msk (0xful << SYS_GPB_MFPH_PB15MFP_Pos) /*!< SYS_T::GPB_MFPH: PB15MFP Mask */ + +#define SYS_GPC_MFPL_PC0MFP_Pos (0) /*!< SYS_T::GPC_MFPL: PC0MFP Position */ +#define SYS_GPC_MFPL_PC0MFP_Msk (0xful << SYS_GPC_MFPL_PC0MFP_Pos) /*!< SYS_T::GPC_MFPL: PC0MFP Mask */ + +#define SYS_GPC_MFPL_PC1MFP_Pos (4) /*!< SYS_T::GPC_MFPL: PC1MFP Position */ +#define SYS_GPC_MFPL_PC1MFP_Msk (0xful << SYS_GPC_MFPL_PC1MFP_Pos) /*!< SYS_T::GPC_MFPL: PC1MFP Mask */ + +#define SYS_GPC_MFPL_PC2MFP_Pos (8) /*!< SYS_T::GPC_MFPL: PC2MFP Position */ +#define SYS_GPC_MFPL_PC2MFP_Msk (0xful << SYS_GPC_MFPL_PC2MFP_Pos) /*!< SYS_T::GPC_MFPL: PC2MFP Mask */ + +#define SYS_GPC_MFPL_PC3MFP_Pos (12) /*!< SYS_T::GPC_MFPL: PC3MFP Position */ +#define SYS_GPC_MFPL_PC3MFP_Msk (0xful << SYS_GPC_MFPL_PC3MFP_Pos) /*!< SYS_T::GPC_MFPL: PC3MFP Mask */ + +#define SYS_GPC_MFPL_PC4MFP_Pos (16) /*!< SYS_T::GPC_MFPL: PC4MFP Position */ +#define SYS_GPC_MFPL_PC4MFP_Msk (0xful << SYS_GPC_MFPL_PC4MFP_Pos) /*!< SYS_T::GPC_MFPL: PC4MFP Mask */ + +#define SYS_GPC_MFPL_PC5MFP_Pos (20) /*!< SYS_T::GPC_MFPL: PC5MFP Position */ +#define SYS_GPC_MFPL_PC5MFP_Msk (0xful << SYS_GPC_MFPL_PC5MFP_Pos) /*!< SYS_T::GPC_MFPL: PC5MFP Mask */ + +#define SYS_GPC_MFPL_PC6MFP_Pos (24) /*!< SYS_T::GPC_MFPL: PC6MFP Position */ +#define SYS_GPC_MFPL_PC6MFP_Msk (0xful << SYS_GPC_MFPL_PC6MFP_Pos) /*!< SYS_T::GPC_MFPL: PC6MFP Mask */ + +#define SYS_GPC_MFPL_PC7MFP_Pos (28) /*!< SYS_T::GPC_MFPL: PC7MFP Position */ +#define SYS_GPC_MFPL_PC7MFP_Msk (0xful << SYS_GPC_MFPL_PC7MFP_Pos) /*!< SYS_T::GPC_MFPL: PC7MFP Mask */ + +#define SYS_GPC_MFPH_PC8MFP_Pos (0) /*!< SYS_T::GPC_MFPH: PC8MFP Position */ +#define SYS_GPC_MFPH_PC8MFP_Msk (0xful << SYS_GPC_MFPH_PC8MFP_Pos) /*!< SYS_T::GPC_MFPH: PC8MFP Mask */ + +#define SYS_GPC_MFPH_PC9MFP_Pos (4) /*!< SYS_T::GPC_MFPH: PC9MFP Position */ +#define SYS_GPC_MFPH_PC9MFP_Msk (0xful << SYS_GPC_MFPH_PC9MFP_Pos) /*!< SYS_T::GPC_MFPH: PC9MFP Mask */ + +#define SYS_GPC_MFPH_PC10MFP_Pos (8) /*!< SYS_T::GPC_MFPH: PC10MFP Position */ +#define SYS_GPC_MFPH_PC10MFP_Msk (0xful << SYS_GPC_MFPH_PC10MFP_Pos) /*!< SYS_T::GPC_MFPH: PC10MFP Mask */ + +#define SYS_GPC_MFPH_PC11MFP_Pos (12) /*!< SYS_T::GPC_MFPH: PC11MFP Position */ +#define SYS_GPC_MFPH_PC11MFP_Msk (0xful << SYS_GPC_MFPH_PC11MFP_Pos) /*!< SYS_T::GPC_MFPH: PC11MFP Mask */ + +#define SYS_GPC_MFPH_PC12MFP_Pos (16) /*!< SYS_T::GPC_MFPH: PC12MFP Position */ +#define SYS_GPC_MFPH_PC12MFP_Msk (0xful << SYS_GPC_MFPH_PC12MFP_Pos) /*!< SYS_T::GPC_MFPH: PC12MFP Mask */ + +#define SYS_GPC_MFPH_PC13MFP_Pos (20) /*!< SYS_T::GPC_MFPH: PC13MFP Position */ +#define SYS_GPC_MFPH_PC13MFP_Msk (0xful << SYS_GPC_MFPH_PC13MFP_Pos) /*!< SYS_T::GPC_MFPH: PC13MFP Mask */ + +#define SYS_GPC_MFPH_PC14MFP_Pos (24) /*!< SYS_T::GPC_MFPH: PC14MFP Position */ +#define SYS_GPC_MFPH_PC14MFP_Msk (0xful << SYS_GPC_MFPH_PC14MFP_Pos) /*!< SYS_T::GPC_MFPH: PC14MFP Mask */ + +#define SYS_GPC_MFPH_PC15MFP_Pos (28) /*!< SYS_T::GPC_MFPH: PC15MFP Position */ +#define SYS_GPC_MFPH_PC15MFP_Msk (0xful << SYS_GPC_MFPH_PC15MFP_Pos) /*!< SYS_T::GPC_MFPH: PC15MFP Mask */ + +#define SYS_GPD_MFPL_PD0MFP_Pos (0) /*!< SYS_T::GPD_MFPL: PD0MFP Position */ +#define SYS_GPD_MFPL_PD0MFP_Msk (0xful << SYS_GPD_MFPL_PD0MFP_Pos) /*!< SYS_T::GPD_MFPL: PD0MFP Mask */ + +#define SYS_GPD_MFPL_PD1MFP_Pos (4) /*!< SYS_T::GPD_MFPL: PD1MFP Position */ +#define SYS_GPD_MFPL_PD1MFP_Msk (0xful << SYS_GPD_MFPL_PD1MFP_Pos) /*!< SYS_T::GPD_MFPL: PD1MFP Mask */ + +#define SYS_GPD_MFPL_PD2MFP_Pos (8) /*!< SYS_T::GPD_MFPL: PD2MFP Position */ +#define SYS_GPD_MFPL_PD2MFP_Msk (0xful << SYS_GPD_MFPL_PD2MFP_Pos) /*!< SYS_T::GPD_MFPL: PD2MFP Mask */ + +#define SYS_GPD_MFPL_PD3MFP_Pos (12) /*!< SYS_T::GPD_MFPL: PD3MFP Position */ +#define SYS_GPD_MFPL_PD3MFP_Msk (0xful << SYS_GPD_MFPL_PD3MFP_Pos) /*!< SYS_T::GPD_MFPL: PD3MFP Mask */ + +#define SYS_GPD_MFPL_PD4MFP_Pos (16) /*!< SYS_T::GPD_MFPL: PD4MFP Position */ +#define SYS_GPD_MFPL_PD4MFP_Msk (0xful << SYS_GPD_MFPL_PD4MFP_Pos) /*!< SYS_T::GPD_MFPL: PD4MFP Mask */ + +#define SYS_GPD_MFPL_PD5MFP_Pos (20) /*!< SYS_T::GPD_MFPL: PD5MFP Position */ +#define SYS_GPD_MFPL_PD5MFP_Msk (0xful << SYS_GPD_MFPL_PD5MFP_Pos) /*!< SYS_T::GPD_MFPL: PD5MFP Mask */ + +#define SYS_GPD_MFPL_PD6MFP_Pos (24) /*!< SYS_T::GPD_MFPL: PD6MFP Position */ +#define SYS_GPD_MFPL_PD6MFP_Msk (0xful << SYS_GPD_MFPL_PD6MFP_Pos) /*!< SYS_T::GPD_MFPL: PD6MFP Mask */ + +#define SYS_GPD_MFPL_PD7MFP_Pos (28) /*!< SYS_T::GPD_MFPL: PD7MFP Position */ +#define SYS_GPD_MFPL_PD7MFP_Msk (0xful << SYS_GPD_MFPL_PD7MFP_Pos) /*!< SYS_T::GPD_MFPL: PD7MFP Mask */ + +#define SYS_GPD_MFPH_PD8MFP_Pos (0) /*!< SYS_T::GPD_MFPH: PD8MFP Position */ +#define SYS_GPD_MFPH_PD8MFP_Msk (0xful << SYS_GPD_MFPH_PD8MFP_Pos) /*!< SYS_T::GPD_MFPH: PD8MFP Mask */ + +#define SYS_GPD_MFPH_PD9MFP_Pos (4) /*!< SYS_T::GPD_MFPH: PD9MFP Position */ +#define SYS_GPD_MFPH_PD9MFP_Msk (0xful << SYS_GPD_MFPH_PD9MFP_Pos) /*!< SYS_T::GPD_MFPH: PD9MFP Mask */ + +#define SYS_GPD_MFPH_PD10MFP_Pos (8) /*!< SYS_T::GPD_MFPH: PD10MFP Position */ +#define SYS_GPD_MFPH_PD10MFP_Msk (0xful << SYS_GPD_MFPH_PD10MFP_Pos) /*!< SYS_T::GPD_MFPH: PD10MFP Mask */ + +#define SYS_GPD_MFPH_PD11MFP_Pos (12) /*!< SYS_T::GPD_MFPH: PD11MFP Position */ +#define SYS_GPD_MFPH_PD11MFP_Msk (0xful << SYS_GPD_MFPH_PD11MFP_Pos) /*!< SYS_T::GPD_MFPH: PD11MFP Mask */ + +#define SYS_GPD_MFPH_PD12MFP_Pos (16) /*!< SYS_T::GPD_MFPH: PD12MFP Position */ +#define SYS_GPD_MFPH_PD12MFP_Msk (0xful << SYS_GPD_MFPH_PD12MFP_Pos) /*!< SYS_T::GPD_MFPH: PD12MFP Mask */ + +#define SYS_GPD_MFPH_PD13MFP_Pos (20) /*!< SYS_T::GPD_MFPH: PD13MFP Position */ +#define SYS_GPD_MFPH_PD13MFP_Msk (0xful << SYS_GPD_MFPH_PD13MFP_Pos) /*!< SYS_T::GPD_MFPH: PD13MFP Mask */ + +#define SYS_GPD_MFPH_PD14MFP_Pos (24) /*!< SYS_T::GPD_MFPH: PD14MFP Position */ +#define SYS_GPD_MFPH_PD14MFP_Msk (0xful << SYS_GPD_MFPH_PD14MFP_Pos) /*!< SYS_T::GPD_MFPH: PD14MFP Mask */ + +#define SYS_GPD_MFPH_PD15MFP_Pos (28) /*!< SYS_T::GPD_MFPH: PD15MFP Position */ +#define SYS_GPD_MFPH_PD15MFP_Msk (0xful << SYS_GPD_MFPH_PD15MFP_Pos) /*!< SYS_T::GPD_MFPH: PD15MFP Mask */ + +#define SYS_GPE_MFPL_PE0MFP_Pos (0) /*!< SYS_T::GPE_MFPL: PE0MFP Position */ +#define SYS_GPE_MFPL_PE0MFP_Msk (0xful << SYS_GPE_MFPL_PE0MFP_Pos) /*!< SYS_T::GPE_MFPL: PE0MFP Mask */ + +#define SYS_GPE_MFPL_PE1MFP_Pos (4) /*!< SYS_T::GPE_MFPL: PE1MFP Position */ +#define SYS_GPE_MFPL_PE1MFP_Msk (0xful << SYS_GPE_MFPL_PE1MFP_Pos) /*!< SYS_T::GPE_MFPL: PE1MFP Mask */ + +#define SYS_GPE_MFPL_PE2MFP_Pos (8) /*!< SYS_T::GPE_MFPL: PE2MFP Position */ +#define SYS_GPE_MFPL_PE2MFP_Msk (0xful << SYS_GPE_MFPL_PE2MFP_Pos) /*!< SYS_T::GPE_MFPL: PE2MFP Mask */ + +#define SYS_GPE_MFPL_PE3MFP_Pos (12) /*!< SYS_T::GPE_MFPL: PE3MFP Position */ +#define SYS_GPE_MFPL_PE3MFP_Msk (0xful << SYS_GPE_MFPL_PE3MFP_Pos) /*!< SYS_T::GPE_MFPL: PE3MFP Mask */ + +#define SYS_GPE_MFPL_PE4MFP_Pos (16) /*!< SYS_T::GPE_MFPL: PE4MFP Position */ +#define SYS_GPE_MFPL_PE4MFP_Msk (0xful << SYS_GPE_MFPL_PE4MFP_Pos) /*!< SYS_T::GPE_MFPL: PE4MFP Mask */ + +#define SYS_GPE_MFPL_PE5MFP_Pos (20) /*!< SYS_T::GPE_MFPL: PE5MFP Position */ +#define SYS_GPE_MFPL_PE5MFP_Msk (0xful << SYS_GPE_MFPL_PE5MFP_Pos) /*!< SYS_T::GPE_MFPL: PE5MFP Mask */ + +#define SYS_GPE_MFPL_PE6MFP_Pos (24) /*!< SYS_T::GPE_MFPL: PE6MFP Position */ +#define SYS_GPE_MFPL_PE6MFP_Msk (0xful << SYS_GPE_MFPL_PE6MFP_Pos) /*!< SYS_T::GPE_MFPL: PE6MFP Mask */ + +#define SYS_GPE_MFPL_PE7MFP_Pos (28) /*!< SYS_T::GPE_MFPL: PE7MFP Position */ +#define SYS_GPE_MFPL_PE7MFP_Msk (0xful << SYS_GPE_MFPL_PE7MFP_Pos) /*!< SYS_T::GPE_MFPL: PE7MFP Mask */ + +#define SYS_GPE_MFPH_PE8MFP_Pos (0) /*!< SYS_T::GPE_MFPH: PE8MFP Position */ +#define SYS_GPE_MFPH_PE8MFP_Msk (0xful << SYS_GPE_MFPH_PE8MFP_Pos) /*!< SYS_T::GPE_MFPH: PE8MFP Mask */ + +#define SYS_GPE_MFPH_PE9MFP_Pos (4) /*!< SYS_T::GPE_MFPH: PE9MFP Position */ +#define SYS_GPE_MFPH_PE9MFP_Msk (0xful << SYS_GPE_MFPH_PE9MFP_Pos) /*!< SYS_T::GPE_MFPH: PE9MFP Mask */ + +#define SYS_GPE_MFPH_PE10MFP_Pos (8) /*!< SYS_T::GPE_MFPH: PE10MFP Position */ +#define SYS_GPE_MFPH_PE10MFP_Msk (0xful << SYS_GPE_MFPH_PE10MFP_Pos) /*!< SYS_T::GPE_MFPH: PE10MFP Mask */ + +#define SYS_GPE_MFPH_PE11MFP_Pos (12) /*!< SYS_T::GPE_MFPH: PE11MFP Position */ +#define SYS_GPE_MFPH_PE11MFP_Msk (0xful << SYS_GPE_MFPH_PE11MFP_Pos) /*!< SYS_T::GPE_MFPH: PE11MFP Mask */ + +#define SYS_GPE_MFPH_PE12MFP_Pos (16) /*!< SYS_T::GPE_MFPH: PE12MFP Position */ +#define SYS_GPE_MFPH_PE12MFP_Msk (0xful << SYS_GPE_MFPH_PE12MFP_Pos) /*!< SYS_T::GPE_MFPH: PE12MFP Mask */ + +#define SYS_GPE_MFPH_PE13MFP_Pos (20) /*!< SYS_T::GPE_MFPH: PE13MFP Position */ +#define SYS_GPE_MFPH_PE13MFP_Msk (0xful << SYS_GPE_MFPH_PE13MFP_Pos) /*!< SYS_T::GPE_MFPH: PE13MFP Mask */ + +#define SYS_GPE_MFPH_PE14MFP_Pos (24) /*!< SYS_T::GPE_MFPH: PE14MFP Position */ +#define SYS_GPE_MFPH_PE14MFP_Msk (0xful << SYS_GPE_MFPH_PE14MFP_Pos) /*!< SYS_T::GPE_MFPH: PE14MFP Mask */ + +#define SYS_GPE_MFPH_PE15MFP_Pos (28) /*!< SYS_T::GPE_MFPH: PE15MFP Position */ +#define SYS_GPE_MFPH_PE15MFP_Msk (0xful << SYS_GPE_MFPH_PE15MFP_Pos) /*!< SYS_T::GPE_MFPH: PE15MFP Mask */ + +#define SYS_GPF_MFPL_PF0MFP_Pos (0) /*!< SYS_T::GPF_MFPL: PF0MFP Position */ +#define SYS_GPF_MFPL_PF0MFP_Msk (0xful << SYS_GPF_MFPL_PF0MFP_Pos) /*!< SYS_T::GPF_MFPL: PF0MFP Mask */ + +#define SYS_GPF_MFPL_PF1MFP_Pos (4) /*!< SYS_T::GPF_MFPL: PF1MFP Position */ +#define SYS_GPF_MFPL_PF1MFP_Msk (0xful << SYS_GPF_MFPL_PF1MFP_Pos) /*!< SYS_T::GPF_MFPL: PF1MFP Mask */ + +#define SYS_GPF_MFPL_PF2MFP_Pos (8) /*!< SYS_T::GPF_MFPL: PF2MFP Position */ +#define SYS_GPF_MFPL_PF2MFP_Msk (0xful << SYS_GPF_MFPL_PF2MFP_Pos) /*!< SYS_T::GPF_MFPL: PF2MFP Mask */ + +#define SYS_GPF_MFPL_PF3MFP_Pos (12) /*!< SYS_T::GPF_MFPL: PF3MFP Position */ +#define SYS_GPF_MFPL_PF3MFP_Msk (0xful << SYS_GPF_MFPL_PF3MFP_Pos) /*!< SYS_T::GPF_MFPL: PF3MFP Mask */ + +#define SYS_GPF_MFPL_PF4MFP_Pos (16) /*!< SYS_T::GPF_MFPL: PF4MFP Position */ +#define SYS_GPF_MFPL_PF4MFP_Msk (0xful << SYS_GPF_MFPL_PF4MFP_Pos) /*!< SYS_T::GPF_MFPL: PF4MFP Mask */ + +#define SYS_GPF_MFPL_PF5MFP_Pos (20) /*!< SYS_T::GPF_MFPL: PF5MFP Position */ +#define SYS_GPF_MFPL_PF5MFP_Msk (0xful << SYS_GPF_MFPL_PF5MFP_Pos) /*!< SYS_T::GPF_MFPL: PF5MFP Mask */ + +#define SYS_GPF_MFPL_PF6MFP_Pos (24) /*!< SYS_T::GPF_MFPL: PF6MFP Position */ +#define SYS_GPF_MFPL_PF6MFP_Msk (0xful << SYS_GPF_MFPL_PF6MFP_Pos) /*!< SYS_T::GPF_MFPL: PF6MFP Mask */ + +#define SYS_GPF_MFPL_PF7MFP_Pos (28) /*!< SYS_T::GPF_MFPL: PF7MFP Position */ +#define SYS_GPF_MFPL_PF7MFP_Msk (0xful << SYS_GPF_MFPL_PF7MFP_Pos) /*!< SYS_T::GPF_MFPL: PF7MFP Mask */ + +#define SYS_GPF_MFPH_PF8MFP_Pos (0) /*!< SYS_T::GPF_MFPH: PF8MFP Position */ +#define SYS_GPF_MFPH_PF8MFP_Msk (0xful << SYS_GPF_MFPH_PF8MFP_Pos) /*!< SYS_T::GPF_MFPH: PF8MFP Mask */ + +#define SYS_GPF_MFPH_PF9MFP_Pos (4) /*!< SYS_T::GPF_MFPH: PF9MFP Position */ +#define SYS_GPF_MFPH_PF9MFP_Msk (0xful << SYS_GPF_MFPH_PF9MFP_Pos) /*!< SYS_T::GPF_MFPH: PF9MFP Mask */ + +#define SYS_GPF_MFPH_PF10MFP_Pos (8) /*!< SYS_T::GPF_MFPH: PF10MFP Position */ +#define SYS_GPF_MFPH_PF10MFP_Msk (0xful << SYS_GPF_MFPH_PF10MFP_Pos) /*!< SYS_T::GPF_MFPH: PF10MFP Mask */ + +#define SYS_GPF_MFPH_PF11MFP_Pos (12) /*!< SYS_T::GPF_MFPH: PF11MFP Position */ +#define SYS_GPF_MFPH_PF11MFP_Msk (0xful << SYS_GPF_MFPH_PF11MFP_Pos) /*!< SYS_T::GPF_MFPH: PF11MFP Mask */ + +#define SYS_GPF_MFPH_PF12MFP_Pos (16) /*!< SYS_T::GPF_MFPH: PF12MFP Position */ +#define SYS_GPF_MFPH_PF12MFP_Msk (0xful << SYS_GPF_MFPH_PF12MFP_Pos) /*!< SYS_T::GPF_MFPH: PF12MFP Mask */ + +#define SYS_GPF_MFPH_PF13MFP_Pos (20) /*!< SYS_T::GPF_MFPH: PF13MFP Position */ +#define SYS_GPF_MFPH_PF13MFP_Msk (0xful << SYS_GPF_MFPH_PF13MFP_Pos) /*!< SYS_T::GPF_MFPH: PF13MFP Mask */ + +#define SYS_GPF_MFPH_PF14MFP_Pos (24) /*!< SYS_T::GPF_MFPH: PF14MFP Position */ +#define SYS_GPF_MFPH_PF14MFP_Msk (0xful << SYS_GPF_MFPH_PF14MFP_Pos) /*!< SYS_T::GPF_MFPH: PF14MFP Mask */ + +#define SYS_GPF_MFPH_PF15MFP_Pos (28) /*!< SYS_T::GPF_MFPH: PF15MFP Position */ +#define SYS_GPF_MFPH_PF15MFP_Msk (0xful << SYS_GPF_MFPH_PF15MFP_Pos) /*!< SYS_T::GPF_MFPH: PF15MFP Mask */ + +#define SYS_GPG_MFPL_PG0MFP_Pos (0) /*!< SYS_T::GPG_MFPL: PG0MFP Position */ +#define SYS_GPG_MFPL_PG0MFP_Msk (0xful << SYS_GPG_MFPL_PG0MFP_Pos) /*!< SYS_T::GPG_MFPL: PG0MFP Mask */ + +#define SYS_GPG_MFPL_PG1MFP_Pos (4) /*!< SYS_T::GPG_MFPL: PG1MFP Position */ +#define SYS_GPG_MFPL_PG1MFP_Msk (0xful << SYS_GPG_MFPL_PG1MFP_Pos) /*!< SYS_T::GPG_MFPL: PG1MFP Mask */ + +#define SYS_GPG_MFPL_PG2MFP_Pos (8) /*!< SYS_T::GPG_MFPL: PG2MFP Position */ +#define SYS_GPG_MFPL_PG2MFP_Msk (0xful << SYS_GPG_MFPL_PG2MFP_Pos) /*!< SYS_T::GPG_MFPL: PG2MFP Mask */ + +#define SYS_GPG_MFPL_PG3MFP_Pos (12) /*!< SYS_T::GPG_MFPL: PG3MFP Position */ +#define SYS_GPG_MFPL_PG3MFP_Msk (0xful << SYS_GPG_MFPL_PG3MFP_Pos) /*!< SYS_T::GPG_MFPL: PG3MFP Mask */ + +#define SYS_GPG_MFPL_PG4MFP_Pos (16) /*!< SYS_T::GPG_MFPL: PG4MFP Position */ +#define SYS_GPG_MFPL_PG4MFP_Msk (0xful << SYS_GPG_MFPL_PG4MFP_Pos) /*!< SYS_T::GPG_MFPL: PG4MFP Mask */ + +#define SYS_GPG_MFPL_PG5MFP_Pos (20) /*!< SYS_T::GPG_MFPL: PG5MFP Position */ +#define SYS_GPG_MFPL_PG5MFP_Msk (0xful << SYS_GPG_MFPL_PG5MFP_Pos) /*!< SYS_T::GPG_MFPL: PG5MFP Mask */ + +#define SYS_GPG_MFPL_PG6MFP_Pos (24) /*!< SYS_T::GPG_MFPL: PG6MFP Position */ +#define SYS_GPG_MFPL_PG6MFP_Msk (0xful << SYS_GPG_MFPL_PG6MFP_Pos) /*!< SYS_T::GPG_MFPL: PG6MFP Mask */ + +#define SYS_GPG_MFPL_PG7MFP_Pos (28) /*!< SYS_T::GPG_MFPL: PG7MFP Position */ +#define SYS_GPG_MFPL_PG7MFP_Msk (0xful << SYS_GPG_MFPL_PG7MFP_Pos) /*!< SYS_T::GPG_MFPL: PG7MFP Mask */ + +#define SYS_GPG_MFPH_PG8MFP_Pos (0) /*!< SYS_T::GPG_MFPH: PG8MFP Position */ +#define SYS_GPG_MFPH_PG8MFP_Msk (0xful << SYS_GPG_MFPH_PG8MFP_Pos) /*!< SYS_T::GPG_MFPH: PG8MFP Mask */ + +#define SYS_GPG_MFPH_PG9MFP_Pos (4) /*!< SYS_T::GPG_MFPH: PG9MFP Position */ +#define SYS_GPG_MFPH_PG9MFP_Msk (0xful << SYS_GPG_MFPH_PG9MFP_Pos) /*!< SYS_T::GPG_MFPH: PG9MFP Mask */ + +#define SYS_GPG_MFPH_PG10MFP_Pos (8) /*!< SYS_T::GPG_MFPH: PG10MFP Position */ +#define SYS_GPG_MFPH_PG10MFP_Msk (0xful << SYS_GPG_MFPH_PG10MFP_Pos) /*!< SYS_T::GPG_MFPH: PG10MFP Mask */ + +#define SYS_GPG_MFPH_PG11MFP_Pos (12) /*!< SYS_T::GPG_MFPH: PG11MFP Position */ +#define SYS_GPG_MFPH_PG11MFP_Msk (0xful << SYS_GPG_MFPH_PG11MFP_Pos) /*!< SYS_T::GPG_MFPH: PG11MFP Mask */ + +#define SYS_GPG_MFPH_PG12MFP_Pos (16) /*!< SYS_T::GPG_MFPH: PG12MFP Position */ +#define SYS_GPG_MFPH_PG12MFP_Msk (0xful << SYS_GPG_MFPH_PG12MFP_Pos) /*!< SYS_T::GPG_MFPH: PG12MFP Mask */ + +#define SYS_GPG_MFPH_PG13MFP_Pos (20) /*!< SYS_T::GPG_MFPH: PG13MFP Position */ +#define SYS_GPG_MFPH_PG13MFP_Msk (0xful << SYS_GPG_MFPH_PG13MFP_Pos) /*!< SYS_T::GPG_MFPH: PG13MFP Mask */ + +#define SYS_GPG_MFPH_PG14MFP_Pos (24) /*!< SYS_T::GPG_MFPH: PG14MFP Position */ +#define SYS_GPG_MFPH_PG14MFP_Msk (0xful << SYS_GPG_MFPH_PG14MFP_Pos) /*!< SYS_T::GPG_MFPH: PG14MFP Mask */ + +#define SYS_GPG_MFPH_PG15MFP_Pos (28) /*!< SYS_T::GPG_MFPH: PG15MFP Position */ +#define SYS_GPG_MFPH_PG15MFP_Msk (0xful << SYS_GPG_MFPH_PG15MFP_Pos) /*!< SYS_T::GPG_MFPH: PG15MFP Mask */ + +#define SYS_GPH_MFPL_PH0MFP_Pos (0) /*!< SYS_T::GPH_MFPL: PH0MFP Position */ +#define SYS_GPH_MFPL_PH0MFP_Msk (0xful << SYS_GPH_MFPL_PH0MFP_Pos) /*!< SYS_T::GPH_MFPL: PH0MFP Mask */ + +#define SYS_GPH_MFPL_PH1MFP_Pos (4) /*!< SYS_T::GPH_MFPL: PH1MFP Position */ +#define SYS_GPH_MFPL_PH1MFP_Msk (0xful << SYS_GPH_MFPL_PH1MFP_Pos) /*!< SYS_T::GPH_MFPL: PH1MFP Mask */ + +#define SYS_GPH_MFPL_PH2MFP_Pos (8) /*!< SYS_T::GPH_MFPL: PH2MFP Position */ +#define SYS_GPH_MFPL_PH2MFP_Msk (0xful << SYS_GPH_MFPL_PH2MFP_Pos) /*!< SYS_T::GPH_MFPL: PH2MFP Mask */ + +#define SYS_GPH_MFPL_PH3MFP_Pos (12) /*!< SYS_T::GPH_MFPL: PH3MFP Position */ +#define SYS_GPH_MFPL_PH3MFP_Msk (0xful << SYS_GPH_MFPL_PH3MFP_Pos) /*!< SYS_T::GPH_MFPL: PH3MFP Mask */ + +#define SYS_GPH_MFPL_PH4MFP_Pos (16) /*!< SYS_T::GPH_MFPL: PH4MFP Position */ +#define SYS_GPH_MFPL_PH4MFP_Msk (0xful << SYS_GPH_MFPL_PH4MFP_Pos) /*!< SYS_T::GPH_MFPL: PH4MFP Mask */ + +#define SYS_GPH_MFPL_PH5MFP_Pos (20) /*!< SYS_T::GPH_MFPL: PH5MFP Position */ +#define SYS_GPH_MFPL_PH5MFP_Msk (0xful << SYS_GPH_MFPL_PH5MFP_Pos) /*!< SYS_T::GPH_MFPL: PH5MFP Mask */ + +#define SYS_GPH_MFPL_PH6MFP_Pos (24) /*!< SYS_T::GPH_MFPL: PH6MFP Position */ +#define SYS_GPH_MFPL_PH6MFP_Msk (0xful << SYS_GPH_MFPL_PH6MFP_Pos) /*!< SYS_T::GPH_MFPL: PH6MFP Mask */ + +#define SYS_GPH_MFPL_PH7MFP_Pos (28) /*!< SYS_T::GPH_MFPL: PH7MFP Position */ +#define SYS_GPH_MFPL_PH7MFP_Msk (0xful << SYS_GPH_MFPL_PH7MFP_Pos) /*!< SYS_T::GPH_MFPL: PH7MFP Mask */ + +#define SYS_GPH_MFPH_PH8MFP_Pos (0) /*!< SYS_T::GPH_MFPH: PH8MFP Position */ +#define SYS_GPH_MFPH_PH8MFP_Msk (0xful << SYS_GPH_MFPH_PH8MFP_Pos) /*!< SYS_T::GPH_MFPH: PH8MFP Mask */ + +#define SYS_GPH_MFPH_PH9MFP_Pos (4) /*!< SYS_T::GPH_MFPH: PH9MFP Position */ +#define SYS_GPH_MFPH_PH9MFP_Msk (0xful << SYS_GPH_MFPH_PH9MFP_Pos) /*!< SYS_T::GPH_MFPH: PH9MFP Mask */ + +#define SYS_GPH_MFPH_PH10MFP_Pos (8) /*!< SYS_T::GPH_MFPH: PH10MFP Position */ +#define SYS_GPH_MFPH_PH10MFP_Msk (0xful << SYS_GPH_MFPH_PH10MFP_Pos) /*!< SYS_T::GPH_MFPH: PH10MFP Mask */ + +#define SYS_GPH_MFPH_PH11MFP_Pos (12) /*!< SYS_T::GPH_MFPH: PH11MFP Position */ +#define SYS_GPH_MFPH_PH11MFP_Msk (0xful << SYS_GPH_MFPH_PH11MFP_Pos) /*!< SYS_T::GPH_MFPH: PH11MFP Mask */ + +#define SYS_GPH_MFPH_PH12MFP_Pos (16) /*!< SYS_T::GPH_MFPH: PH12MFP Position */ +#define SYS_GPH_MFPH_PH12MFP_Msk (0xful << SYS_GPH_MFPH_PH12MFP_Pos) /*!< SYS_T::GPH_MFPH: PH12MFP Mask */ + +#define SYS_GPH_MFPH_PH13MFP_Pos (20) /*!< SYS_T::GPH_MFPH: PH13MFP Position */ +#define SYS_GPH_MFPH_PH13MFP_Msk (0xful << SYS_GPH_MFPH_PH13MFP_Pos) /*!< SYS_T::GPH_MFPH: PH13MFP Mask */ + +#define SYS_GPH_MFPH_PH14MFP_Pos (24) /*!< SYS_T::GPH_MFPH: PH14MFP Position */ +#define SYS_GPH_MFPH_PH14MFP_Msk (0xful << SYS_GPH_MFPH_PH14MFP_Pos) /*!< SYS_T::GPH_MFPH: PH14MFP Mask */ + +#define SYS_GPH_MFPH_PH15MFP_Pos (28) /*!< SYS_T::GPH_MFPH: PH15MFP Position */ +#define SYS_GPH_MFPH_PH15MFP_Msk (0xful << SYS_GPH_MFPH_PH15MFP_Pos) /*!< SYS_T::GPH_MFPH: PH15MFP Mask */ + +#define SYS_GPI_MFPL_PI0MFP_Pos (0) /*!< SYS_T::GPI_MFPL: PI0MFP Position */ +#define SYS_GPI_MFPL_PI0MFP_Msk (0xful << SYS_GPI_MFPL_PI0MFP_Pos) /*!< SYS_T::GPI_MFPL: PI0MFP Mask */ + +#define SYS_GPI_MFPL_PI1MFP_Pos (4) /*!< SYS_T::GPI_MFPL: PI1MFP Position */ +#define SYS_GPI_MFPL_PI1MFP_Msk (0xful << SYS_GPI_MFPL_PI1MFP_Pos) /*!< SYS_T::GPI_MFPL: PI1MFP Mask */ + +#define SYS_GPI_MFPL_PI2MFP_Pos (8) /*!< SYS_T::GPI_MFPL: PI2MFP Position */ +#define SYS_GPI_MFPL_PI2MFP_Msk (0xful << SYS_GPI_MFPL_PI2MFP_Pos) /*!< SYS_T::GPI_MFPL: PI2MFP Mask */ + +#define SYS_GPI_MFPL_PI3MFP_Pos (12) /*!< SYS_T::GPI_MFPL: PI3MFP Position */ +#define SYS_GPI_MFPL_PI3MFP_Msk (0xful << SYS_GPI_MFPL_PI3MFP_Pos) /*!< SYS_T::GPI_MFPL: PI3MFP Mask */ + +#define SYS_GPI_MFPL_PI4MFP_Pos (16) /*!< SYS_T::GPI_MFPL: PI4MFP Position */ +#define SYS_GPI_MFPL_PI4MFP_Msk (0xful << SYS_GPI_MFPL_PI4MFP_Pos) /*!< SYS_T::GPI_MFPL: PI4MFP Mask */ + +#define SYS_GPI_MFPL_PI5MFP_Pos (20) /*!< SYS_T::GPI_MFPL: PI5MFP Position */ +#define SYS_GPI_MFPL_PI5MFP_Msk (0xful << SYS_GPI_MFPL_PI5MFP_Pos) /*!< SYS_T::GPI_MFPL: PI5MFP Mask */ + +#define SYS_GPI_MFPL_PI6MFP_Pos (24) /*!< SYS_T::GPI_MFPL: PI6MFP Position */ +#define SYS_GPI_MFPL_PI6MFP_Msk (0xful << SYS_GPI_MFPL_PI6MFP_Pos) /*!< SYS_T::GPI_MFPL: PI6MFP Mask */ + +#define SYS_GPI_MFPL_PI7MFP_Pos (28) /*!< SYS_T::GPI_MFPL: PI7MFP Position */ +#define SYS_GPI_MFPL_PI7MFP_Msk (0xful << SYS_GPI_MFPL_PI7MFP_Pos) /*!< SYS_T::GPI_MFPL: PI7MFP Mask */ + +#define SYS_GPI_MFPH_PI8MFP_Pos (0) /*!< SYS_T::GPI_MFPH: PI8MFP Position */ +#define SYS_GPI_MFPH_PI8MFP_Msk (0xful << SYS_GPI_MFPH_PI8MFP_Pos) /*!< SYS_T::GPI_MFPH: PI8MFP Mask */ + +#define SYS_GPI_MFPH_PI9MFP_Pos (4) /*!< SYS_T::GPI_MFPH: PI9MFP Position */ +#define SYS_GPI_MFPH_PI9MFP_Msk (0xful << SYS_GPI_MFPH_PI9MFP_Pos) /*!< SYS_T::GPI_MFPH: PI9MFP Mask */ + +#define SYS_GPI_MFPH_PI10MFP_Pos (8) /*!< SYS_T::GPI_MFPH: PI10MFP Position */ +#define SYS_GPI_MFPH_PI10MFP_Msk (0xful << SYS_GPI_MFPH_PI10MFP_Pos) /*!< SYS_T::GPI_MFPH: PI10MFP Mask */ + +#define SYS_GPI_MFPH_PI11MFP_Pos (12) /*!< SYS_T::GPI_MFPH: PI11MFP Position */ +#define SYS_GPI_MFPH_PI11MFP_Msk (0xful << SYS_GPI_MFPH_PI11MFP_Pos) /*!< SYS_T::GPI_MFPH: PI11MFP Mask */ + +#define SYS_GPI_MFPH_PI12MFP_Pos (16) /*!< SYS_T::GPI_MFPH: PI12MFP Position */ +#define SYS_GPI_MFPH_PI12MFP_Msk (0xful << SYS_GPI_MFPH_PI12MFP_Pos) /*!< SYS_T::GPI_MFPH: PI12MFP Mask */ + +#define SYS_GPI_MFPH_PI13MFP_Pos (20) /*!< SYS_T::GPI_MFPH: PI13MFP Position */ +#define SYS_GPI_MFPH_PI13MFP_Msk (0xful << SYS_GPI_MFPH_PI13MFP_Pos) /*!< SYS_T::GPI_MFPH: PI13MFP Mask */ + +#define SYS_GPI_MFPH_PI14MFP_Pos (24) /*!< SYS_T::GPI_MFPH: PI14MFP Position */ +#define SYS_GPI_MFPH_PI14MFP_Msk (0xful << SYS_GPI_MFPH_PI14MFP_Pos) /*!< SYS_T::GPI_MFPH: PI14MFP Mask */ + +#define SYS_GPI_MFPH_PI15MFP_Pos (28) /*!< SYS_T::GPI_MFPH: PI15MFP Position */ +#define SYS_GPI_MFPH_PI15MFP_Msk (0xful << SYS_GPI_MFPH_PI15MFP_Pos) /*!< SYS_T::GPI_MFPH: PI15MFP Mask */ + +#define SYS_GPJ_MFPL_PJ0MFP_Pos (0) /*!< SYS_T::GPJ_MFPL: PJ0MFP Position */ +#define SYS_GPJ_MFPL_PJ0MFP_Msk (0xful << SYS_GPJ_MFPL_PJ0MFP_Pos) /*!< SYS_T::GPJ_MFPL: PJ0MFP Mask */ + +#define SYS_GPJ_MFPL_PJ1MFP_Pos (4) /*!< SYS_T::GPJ_MFPL: PJ1MFP Position */ +#define SYS_GPJ_MFPL_PJ1MFP_Msk (0xful << SYS_GPJ_MFPL_PJ1MFP_Pos) /*!< SYS_T::GPJ_MFPL: PJ1MFP Mask */ + +#define SYS_GPJ_MFPL_PJ2MFP_Pos (8) /*!< SYS_T::GPJ_MFPL: PJ2MFP Position */ +#define SYS_GPJ_MFPL_PJ2MFP_Msk (0xful << SYS_GPJ_MFPL_PJ2MFP_Pos) /*!< SYS_T::GPJ_MFPL: PJ2MFP Mask */ + +#define SYS_GPJ_MFPL_PJ3MFP_Pos (12) /*!< SYS_T::GPJ_MFPL: PJ3MFP Position */ +#define SYS_GPJ_MFPL_PJ3MFP_Msk (0xful << SYS_GPJ_MFPL_PJ3MFP_Pos) /*!< SYS_T::GPJ_MFPL: PJ3MFP Mask */ + +#define SYS_GPJ_MFPL_PJ4MFP_Pos (16) /*!< SYS_T::GPJ_MFPL: PJ4MFP Position */ +#define SYS_GPJ_MFPL_PJ4MFP_Msk (0xful << SYS_GPJ_MFPL_PJ4MFP_Pos) /*!< SYS_T::GPJ_MFPL: PJ4MFP Mask */ + +#define SYS_GPJ_MFPL_PJ5MFP_Pos (20) /*!< SYS_T::GPJ_MFPL: PJ5MFP Position */ +#define SYS_GPJ_MFPL_PJ5MFP_Msk (0xful << SYS_GPJ_MFPL_PJ5MFP_Pos) /*!< SYS_T::GPJ_MFPL: PJ5MFP Mask */ + +#define SYS_GPJ_MFPL_PJ6MFP_Pos (24) /*!< SYS_T::GPJ_MFPL: PJ6MFP Position */ +#define SYS_GPJ_MFPL_PJ6MFP_Msk (0xful << SYS_GPJ_MFPL_PJ6MFP_Pos) /*!< SYS_T::GPJ_MFPL: PJ6MFP Mask */ + +#define SYS_GPJ_MFPL_PJ7MFP_Pos (28) /*!< SYS_T::GPJ_MFPL: PJ7MFP Position */ +#define SYS_GPJ_MFPL_PJ7MFP_Msk (0xful << SYS_GPJ_MFPL_PJ7MFP_Pos) /*!< SYS_T::GPJ_MFPL: PJ7MFP Mask */ + +#define SYS_GPJ_MFPH_PJ8MFP_Pos (0) /*!< SYS_T::GPJ_MFPH: PJ8MFP Position */ +#define SYS_GPJ_MFPH_PJ8MFP_Msk (0xful << SYS_GPJ_MFPH_PJ8MFP_Pos) /*!< SYS_T::GPJ_MFPH: PJ8MFP Mask */ + +#define SYS_GPJ_MFPH_PJ9MFP_Pos (4) /*!< SYS_T::GPJ_MFPH: PJ9MFP Position */ +#define SYS_GPJ_MFPH_PJ9MFP_Msk (0xful << SYS_GPJ_MFPH_PJ9MFP_Pos) /*!< SYS_T::GPJ_MFPH: PJ9MFP Mask */ + +#define SYS_GPJ_MFPH_PJ10MFP_Pos (8) /*!< SYS_T::GPJ_MFPH: PJ10MFP Position */ +#define SYS_GPJ_MFPH_PJ10MFP_Msk (0xful << SYS_GPJ_MFPH_PJ10MFP_Pos) /*!< SYS_T::GPJ_MFPH: PJ10MFP Mask */ + +#define SYS_GPJ_MFPH_PJ11MFP_Pos (12) /*!< SYS_T::GPJ_MFPH: PJ11MFP Position */ +#define SYS_GPJ_MFPH_PJ11MFP_Msk (0xful << SYS_GPJ_MFPH_PJ11MFP_Pos) /*!< SYS_T::GPJ_MFPH: PJ11MFP Mask */ + +#define SYS_GPJ_MFPH_PJ12MFP_Pos (16) /*!< SYS_T::GPJ_MFPH: PJ12MFP Position */ +#define SYS_GPJ_MFPH_PJ12MFP_Msk (0xful << SYS_GPJ_MFPH_PJ12MFP_Pos) /*!< SYS_T::GPJ_MFPH: PJ12MFP Mask */ + +#define SYS_GPJ_MFPH_PJ13MFP_Pos (20) /*!< SYS_T::GPJ_MFPH: PJ13MFP Position */ +#define SYS_GPJ_MFPH_PJ13MFP_Msk (0xful << SYS_GPJ_MFPH_PJ13MFP_Pos) /*!< SYS_T::GPJ_MFPH: PJ13MFP Mask */ + +#define SYS_GPJ_MFPH_PJ14MFP_Pos (24) /*!< SYS_T::GPJ_MFPH: PJ14MFP Position */ +#define SYS_GPJ_MFPH_PJ14MFP_Msk (0xful << SYS_GPJ_MFPH_PJ14MFP_Pos) /*!< SYS_T::GPJ_MFPH: PJ14MFP Mask */ + +#define SYS_GPJ_MFPH_PJ15MFP_Pos (28) /*!< SYS_T::GPJ_MFPH: PJ15MFP Position */ +#define SYS_GPJ_MFPH_PJ15MFP_Msk (0xful << SYS_GPJ_MFPH_PJ15MFP_Pos) /*!< SYS_T::GPJ_MFPH: PJ15MFP Mask */ + +#define SYS_GPK_MFPL_PK0MFP_Pos (0) /*!< SYS_T::GPK_MFPL: PK0MFP Position */ +#define SYS_GPK_MFPL_PK0MFP_Msk (0xful << SYS_GPK_MFPL_PK0MFP_Pos) /*!< SYS_T::GPK_MFPL: PK0MFP Mask */ + +#define SYS_GPK_MFPL_PK1MFP_Pos (4) /*!< SYS_T::GPK_MFPL: PK1MFP Position */ +#define SYS_GPK_MFPL_PK1MFP_Msk (0xful << SYS_GPK_MFPL_PK1MFP_Pos) /*!< SYS_T::GPK_MFPL: PK1MFP Mask */ + +#define SYS_GPK_MFPL_PK2MFP_Pos (8) /*!< SYS_T::GPK_MFPL: PK2MFP Position */ +#define SYS_GPK_MFPL_PK2MFP_Msk (0xful << SYS_GPK_MFPL_PK2MFP_Pos) /*!< SYS_T::GPK_MFPL: PK2MFP Mask */ + +#define SYS_GPK_MFPL_PK3MFP_Pos (12) /*!< SYS_T::GPK_MFPL: PK3MFP Position */ +#define SYS_GPK_MFPL_PK3MFP_Msk (0xful << SYS_GPK_MFPL_PK3MFP_Pos) /*!< SYS_T::GPK_MFPL: PK3MFP Mask */ + +#define SYS_GPK_MFPL_PK4MFP_Pos (16) /*!< SYS_T::GPK_MFPL: PK4MFP Position */ +#define SYS_GPK_MFPL_PK4MFP_Msk (0xful << SYS_GPK_MFPL_PK4MFP_Pos) /*!< SYS_T::GPK_MFPL: PK4MFP Mask */ + +#define SYS_GPK_MFPL_PK5MFP_Pos (20) /*!< SYS_T::GPK_MFPL: PK5MFP Position */ +#define SYS_GPK_MFPL_PK5MFP_Msk (0xful << SYS_GPK_MFPL_PK5MFP_Pos) /*!< SYS_T::GPK_MFPL: PK5MFP Mask */ + +#define SYS_GPK_MFPL_PK6MFP_Pos (24) /*!< SYS_T::GPK_MFPL: PK6MFP Position */ +#define SYS_GPK_MFPL_PK6MFP_Msk (0xful << SYS_GPK_MFPL_PK6MFP_Pos) /*!< SYS_T::GPK_MFPL: PK6MFP Mask */ + +#define SYS_GPK_MFPL_PK7MFP_Pos (28) /*!< SYS_T::GPK_MFPL: PK7MFP Position */ +#define SYS_GPK_MFPL_PK7MFP_Msk (0xful << SYS_GPK_MFPL_PK7MFP_Pos) /*!< SYS_T::GPK_MFPL: PK7MFP Mask */ + +#define SYS_GPK_MFPH_PK8MFP_Pos (0) /*!< SYS_T::GPK_MFPH: PK8MFP Position */ +#define SYS_GPK_MFPH_PK8MFP_Msk (0xful << SYS_GPK_MFPH_PK8MFP_Pos) /*!< SYS_T::GPK_MFPH: PK8MFP Mask */ + +#define SYS_GPK_MFPH_PK9MFP_Pos (4) /*!< SYS_T::GPK_MFPH: PK9MFP Position */ +#define SYS_GPK_MFPH_PK9MFP_Msk (0xful << SYS_GPK_MFPH_PK9MFP_Pos) /*!< SYS_T::GPK_MFPH: PK9MFP Mask */ + +#define SYS_GPK_MFPH_PK10MFP_Pos (8) /*!< SYS_T::GPK_MFPH: PK10MFP Position */ +#define SYS_GPK_MFPH_PK10MFP_Msk (0xful << SYS_GPK_MFPH_PK10MFP_Pos) /*!< SYS_T::GPK_MFPH: PK10MFP Mask */ + +#define SYS_GPK_MFPH_PK11MFP_Pos (12) /*!< SYS_T::GPK_MFPH: PK11MFP Position */ +#define SYS_GPK_MFPH_PK11MFP_Msk (0xful << SYS_GPK_MFPH_PK11MFP_Pos) /*!< SYS_T::GPK_MFPH: PK11MFP Mask */ + +#define SYS_GPK_MFPH_PK12MFP_Pos (16) /*!< SYS_T::GPK_MFPH: PK12MFP Position */ +#define SYS_GPK_MFPH_PK12MFP_Msk (0xful << SYS_GPK_MFPH_PK12MFP_Pos) /*!< SYS_T::GPK_MFPH: PK12MFP Mask */ + +#define SYS_GPK_MFPH_PK13MFP_Pos (20) /*!< SYS_T::GPK_MFPH: PK13MFP Position */ +#define SYS_GPK_MFPH_PK13MFP_Msk (0xful << SYS_GPK_MFPH_PK13MFP_Pos) /*!< SYS_T::GPK_MFPH: PK13MFP Mask */ + +#define SYS_GPK_MFPH_PK14MFP_Pos (24) /*!< SYS_T::GPK_MFPH: PK14MFP Position */ +#define SYS_GPK_MFPH_PK14MFP_Msk (0xful << SYS_GPK_MFPH_PK14MFP_Pos) /*!< SYS_T::GPK_MFPH: PK14MFP Mask */ + +#define SYS_GPK_MFPH_PK15MFP_Pos (28) /*!< SYS_T::GPK_MFPH: PK15MFP Position */ +#define SYS_GPK_MFPH_PK15MFP_Msk (0xful << SYS_GPK_MFPH_PK15MFP_Pos) /*!< SYS_T::GPK_MFPH: PK15MFP Mask */ + +#define SYS_GPL_MFPL_PL0MFP_Pos (0) /*!< SYS_T::GPL_MFPL: PL0MFP Position */ +#define SYS_GPL_MFPL_PL0MFP_Msk (0xful << SYS_GPL_MFPL_PL0MFP_Pos) /*!< SYS_T::GPL_MFPL: PL0MFP Mask */ + +#define SYS_GPL_MFPL_PL1MFP_Pos (4) /*!< SYS_T::GPL_MFPL: PL1MFP Position */ +#define SYS_GPL_MFPL_PL1MFP_Msk (0xful << SYS_GPL_MFPL_PL1MFP_Pos) /*!< SYS_T::GPL_MFPL: PL1MFP Mask */ + +#define SYS_GPL_MFPL_PL2MFP_Pos (8) /*!< SYS_T::GPL_MFPL: PL2MFP Position */ +#define SYS_GPL_MFPL_PL2MFP_Msk (0xful << SYS_GPL_MFPL_PL2MFP_Pos) /*!< SYS_T::GPL_MFPL: PL2MFP Mask */ + +#define SYS_GPL_MFPL_PL3MFP_Pos (12) /*!< SYS_T::GPL_MFPL: PL3MFP Position */ +#define SYS_GPL_MFPL_PL3MFP_Msk (0xful << SYS_GPL_MFPL_PL3MFP_Pos) /*!< SYS_T::GPL_MFPL: PL3MFP Mask */ + +#define SYS_GPL_MFPL_PL4MFP_Pos (16) /*!< SYS_T::GPL_MFPL: PL4MFP Position */ +#define SYS_GPL_MFPL_PL4MFP_Msk (0xful << SYS_GPL_MFPL_PL4MFP_Pos) /*!< SYS_T::GPL_MFPL: PL4MFP Mask */ + +#define SYS_GPL_MFPL_PL5MFP_Pos (20) /*!< SYS_T::GPL_MFPL: PL5MFP Position */ +#define SYS_GPL_MFPL_PL5MFP_Msk (0xful << SYS_GPL_MFPL_PL5MFP_Pos) /*!< SYS_T::GPL_MFPL: PL5MFP Mask */ + +#define SYS_GPL_MFPL_PL6MFP_Pos (24) /*!< SYS_T::GPL_MFPL: PL6MFP Position */ +#define SYS_GPL_MFPL_PL6MFP_Msk (0xful << SYS_GPL_MFPL_PL6MFP_Pos) /*!< SYS_T::GPL_MFPL: PL6MFP Mask */ + +#define SYS_GPL_MFPL_PL7MFP_Pos (28) /*!< SYS_T::GPL_MFPL: PL7MFP Position */ +#define SYS_GPL_MFPL_PL7MFP_Msk (0xful << SYS_GPL_MFPL_PL7MFP_Pos) /*!< SYS_T::GPL_MFPL: PL7MFP Mask */ + +#define SYS_GPL_MFPH_PL8MFP_Pos (0) /*!< SYS_T::GPL_MFPH: PL8MFP Position */ +#define SYS_GPL_MFPH_PL8MFP_Msk (0xful << SYS_GPL_MFPH_PL8MFP_Pos) /*!< SYS_T::GPL_MFPH: PL8MFP Mask */ + +#define SYS_GPL_MFPH_PL9MFP_Pos (4) /*!< SYS_T::GPL_MFPH: PL9MFP Position */ +#define SYS_GPL_MFPH_PL9MFP_Msk (0xful << SYS_GPL_MFPH_PL9MFP_Pos) /*!< SYS_T::GPL_MFPH: PL9MFP Mask */ + +#define SYS_GPL_MFPH_PL10MFP_Pos (8) /*!< SYS_T::GPL_MFPH: PL10MFP Position */ +#define SYS_GPL_MFPH_PL10MFP_Msk (0xful << SYS_GPL_MFPH_PL10MFP_Pos) /*!< SYS_T::GPL_MFPH: PL10MFP Mask */ + +#define SYS_GPL_MFPH_PL11MFP_Pos (12) /*!< SYS_T::GPL_MFPH: PL11MFP Position */ +#define SYS_GPL_MFPH_PL11MFP_Msk (0xful << SYS_GPL_MFPH_PL11MFP_Pos) /*!< SYS_T::GPL_MFPH: PL11MFP Mask */ + +#define SYS_GPL_MFPH_PL12MFP_Pos (16) /*!< SYS_T::GPL_MFPH: PL12MFP Position */ +#define SYS_GPL_MFPH_PL12MFP_Msk (0xful << SYS_GPL_MFPH_PL12MFP_Pos) /*!< SYS_T::GPL_MFPH: PL12MFP Mask */ + +#define SYS_GPL_MFPH_PL13MFP_Pos (20) /*!< SYS_T::GPL_MFPH: PL13MFP Position */ +#define SYS_GPL_MFPH_PL13MFP_Msk (0xful << SYS_GPL_MFPH_PL13MFP_Pos) /*!< SYS_T::GPL_MFPH: PL13MFP Mask */ + +#define SYS_GPL_MFPH_PL14MFP_Pos (24) /*!< SYS_T::GPL_MFPH: PL14MFP Position */ +#define SYS_GPL_MFPH_PL14MFP_Msk (0xful << SYS_GPL_MFPH_PL14MFP_Pos) /*!< SYS_T::GPL_MFPH: PL14MFP Mask */ + +#define SYS_GPL_MFPH_PL15MFP_Pos (28) /*!< SYS_T::GPL_MFPH: PL15MFP Position */ +#define SYS_GPL_MFPH_PL15MFP_Msk (0xful << SYS_GPL_MFPH_PL15MFP_Pos) /*!< SYS_T::GPL_MFPH: PL15MFP Mask */ + +#define SYS_GPM_MFPL_PM0MFP_Pos (0) /*!< SYS_T::GPM_MFPL: PM0MFP Position */ +#define SYS_GPM_MFPL_PM0MFP_Msk (0xful << SYS_GPM_MFPL_PM0MFP_Pos) /*!< SYS_T::GPM_MFPL: PM0MFP Mask */ + +#define SYS_GPM_MFPL_PM1MFP_Pos (4) /*!< SYS_T::GPM_MFPL: PM1MFP Position */ +#define SYS_GPM_MFPL_PM1MFP_Msk (0xful << SYS_GPM_MFPL_PM1MFP_Pos) /*!< SYS_T::GPM_MFPL: PM1MFP Mask */ + +#define SYS_GPM_MFPL_PM2MFP_Pos (8) /*!< SYS_T::GPM_MFPL: PM2MFP Position */ +#define SYS_GPM_MFPL_PM2MFP_Msk (0xful << SYS_GPM_MFPL_PM2MFP_Pos) /*!< SYS_T::GPM_MFPL: PM2MFP Mask */ + +#define SYS_GPM_MFPL_PM3MFP_Pos (12) /*!< SYS_T::GPM_MFPL: PM3MFP Position */ +#define SYS_GPM_MFPL_PM3MFP_Msk (0xful << SYS_GPM_MFPL_PM3MFP_Pos) /*!< SYS_T::GPM_MFPL: PM3MFP Mask */ + +#define SYS_GPM_MFPL_PM4MFP_Pos (16) /*!< SYS_T::GPM_MFPL: PM4MFP Position */ +#define SYS_GPM_MFPL_PM4MFP_Msk (0xful << SYS_GPM_MFPL_PM4MFP_Pos) /*!< SYS_T::GPM_MFPL: PM4MFP Mask */ + +#define SYS_GPM_MFPL_PM5MFP_Pos (20) /*!< SYS_T::GPM_MFPL: PM5MFP Position */ +#define SYS_GPM_MFPL_PM5MFP_Msk (0xful << SYS_GPM_MFPL_PM5MFP_Pos) /*!< SYS_T::GPM_MFPL: PM5MFP Mask */ + +#define SYS_GPM_MFPL_PM6MFP_Pos (24) /*!< SYS_T::GPM_MFPL: PM6MFP Position */ +#define SYS_GPM_MFPL_PM6MFP_Msk (0xful << SYS_GPM_MFPL_PM6MFP_Pos) /*!< SYS_T::GPM_MFPL: PM6MFP Mask */ + +#define SYS_GPM_MFPL_PM7MFP_Pos (28) /*!< SYS_T::GPM_MFPL: PM7MFP Position */ +#define SYS_GPM_MFPL_PM7MFP_Msk (0xful << SYS_GPM_MFPL_PM7MFP_Pos) /*!< SYS_T::GPM_MFPL: PM7MFP Mask */ + +#define SYS_GPM_MFPH_PM8MFP_Pos (0) /*!< SYS_T::GPM_MFPH: PM8MFP Position */ +#define SYS_GPM_MFPH_PM8MFP_Msk (0xful << SYS_GPM_MFPH_PM8MFP_Pos) /*!< SYS_T::GPM_MFPH: PM8MFP Mask */ + +#define SYS_GPM_MFPH_PM9MFP_Pos (4) /*!< SYS_T::GPM_MFPH: PM9MFP Position */ +#define SYS_GPM_MFPH_PM9MFP_Msk (0xful << SYS_GPM_MFPH_PM9MFP_Pos) /*!< SYS_T::GPM_MFPH: PM9MFP Mask */ + +#define SYS_GPM_MFPH_PM10MFP_Pos (8) /*!< SYS_T::GPM_MFPH: PM10MFP Position */ +#define SYS_GPM_MFPH_PM10MFP_Msk (0xful << SYS_GPM_MFPH_PM10MFP_Pos) /*!< SYS_T::GPM_MFPH: PM10MFP Mask */ + +#define SYS_GPM_MFPH_PM11MFP_Pos (12) /*!< SYS_T::GPM_MFPH: PM11MFP Position */ +#define SYS_GPM_MFPH_PM11MFP_Msk (0xful << SYS_GPM_MFPH_PM11MFP_Pos) /*!< SYS_T::GPM_MFPH: PM11MFP Mask */ + +#define SYS_GPM_MFPH_PM12MFP_Pos (16) /*!< SYS_T::GPM_MFPH: PM12MFP Position */ +#define SYS_GPM_MFPH_PM12MFP_Msk (0xful << SYS_GPM_MFPH_PM12MFP_Pos) /*!< SYS_T::GPM_MFPH: PM12MFP Mask */ + +#define SYS_GPM_MFPH_PM13MFP_Pos (20) /*!< SYS_T::GPM_MFPH: PM13MFP Position */ +#define SYS_GPM_MFPH_PM13MFP_Msk (0xful << SYS_GPM_MFPH_PM13MFP_Pos) /*!< SYS_T::GPM_MFPH: PM13MFP Mask */ + +#define SYS_GPM_MFPH_PM14MFP_Pos (24) /*!< SYS_T::GPM_MFPH: PM14MFP Position */ +#define SYS_GPM_MFPH_PM14MFP_Msk (0xful << SYS_GPM_MFPH_PM14MFP_Pos) /*!< SYS_T::GPM_MFPH: PM14MFP Mask */ + +#define SYS_GPM_MFPH_PM15MFP_Pos (28) /*!< SYS_T::GPM_MFPH: PM15MFP Position */ +#define SYS_GPM_MFPH_PM15MFP_Msk (0xful << SYS_GPM_MFPH_PM15MFP_Pos) /*!< SYS_T::GPM_MFPH: PM15MFP Mask */ + +#define SYS_GPN_MFPL_PN0MFP_Pos (0) /*!< SYS_T::GPN_MFPL: PN0MFP Position */ +#define SYS_GPN_MFPL_PN0MFP_Msk (0xful << SYS_GPN_MFPL_PN0MFP_Pos) /*!< SYS_T::GPN_MFPL: PN0MFP Mask */ + +#define SYS_GPN_MFPL_PN1MFP_Pos (4) /*!< SYS_T::GPN_MFPL: PN1MFP Position */ +#define SYS_GPN_MFPL_PN1MFP_Msk (0xful << SYS_GPN_MFPL_PN1MFP_Pos) /*!< SYS_T::GPN_MFPL: PN1MFP Mask */ + +#define SYS_GPN_MFPL_PN2MFP_Pos (8) /*!< SYS_T::GPN_MFPL: PN2MFP Position */ +#define SYS_GPN_MFPL_PN2MFP_Msk (0xful << SYS_GPN_MFPL_PN2MFP_Pos) /*!< SYS_T::GPN_MFPL: PN2MFP Mask */ + +#define SYS_GPN_MFPL_PN3MFP_Pos (12) /*!< SYS_T::GPN_MFPL: PN3MFP Position */ +#define SYS_GPN_MFPL_PN3MFP_Msk (0xful << SYS_GPN_MFPL_PN3MFP_Pos) /*!< SYS_T::GPN_MFPL: PN3MFP Mask */ + +#define SYS_GPN_MFPL_PN4MFP_Pos (16) /*!< SYS_T::GPN_MFPL: PN4MFP Position */ +#define SYS_GPN_MFPL_PN4MFP_Msk (0xful << SYS_GPN_MFPL_PN4MFP_Pos) /*!< SYS_T::GPN_MFPL: PN4MFP Mask */ + +#define SYS_GPN_MFPL_PN5MFP_Pos (20) /*!< SYS_T::GPN_MFPL: PN5MFP Position */ +#define SYS_GPN_MFPL_PN5MFP_Msk (0xful << SYS_GPN_MFPL_PN5MFP_Pos) /*!< SYS_T::GPN_MFPL: PN5MFP Mask */ + +#define SYS_GPN_MFPL_PN6MFP_Pos (24) /*!< SYS_T::GPN_MFPL: PN6MFP Position */ +#define SYS_GPN_MFPL_PN6MFP_Msk (0xful << SYS_GPN_MFPL_PN6MFP_Pos) /*!< SYS_T::GPN_MFPL: PN6MFP Mask */ + +#define SYS_GPN_MFPL_PN7MFP_Pos (28) /*!< SYS_T::GPN_MFPL: PN7MFP Position */ +#define SYS_GPN_MFPL_PN7MFP_Msk (0xful << SYS_GPN_MFPL_PN7MFP_Pos) /*!< SYS_T::GPN_MFPL: PN7MFP Mask */ + +#define SYS_GPN_MFPH_PN8MFP_Pos (0) /*!< SYS_T::GPN_MFPH: PN8MFP Position */ +#define SYS_GPN_MFPH_PN8MFP_Msk (0xful << SYS_GPN_MFPH_PN8MFP_Pos) /*!< SYS_T::GPN_MFPH: PN8MFP Mask */ + +#define SYS_GPN_MFPH_PN9MFP_Pos (4) /*!< SYS_T::GPN_MFPH: PN9MFP Position */ +#define SYS_GPN_MFPH_PN9MFP_Msk (0xful << SYS_GPN_MFPH_PN9MFP_Pos) /*!< SYS_T::GPN_MFPH: PN9MFP Mask */ + +#define SYS_GPN_MFPH_PN10MFP_Pos (8) /*!< SYS_T::GPN_MFPH: PN10MFP Position */ +#define SYS_GPN_MFPH_PN10MFP_Msk (0xful << SYS_GPN_MFPH_PN10MFP_Pos) /*!< SYS_T::GPN_MFPH: PN10MFP Mask */ + +#define SYS_GPN_MFPH_PN11MFP_Pos (12) /*!< SYS_T::GPN_MFPH: PN11MFP Position */ +#define SYS_GPN_MFPH_PN11MFP_Msk (0xful << SYS_GPN_MFPH_PN11MFP_Pos) /*!< SYS_T::GPN_MFPH: PN11MFP Mask */ + +#define SYS_GPN_MFPH_PN12MFP_Pos (16) /*!< SYS_T::GPN_MFPH: PN12MFP Position */ +#define SYS_GPN_MFPH_PN12MFP_Msk (0xful << SYS_GPN_MFPH_PN12MFP_Pos) /*!< SYS_T::GPN_MFPH: PN12MFP Mask */ + +#define SYS_GPN_MFPH_PN13MFP_Pos (20) /*!< SYS_T::GPN_MFPH: PN13MFP Position */ +#define SYS_GPN_MFPH_PN13MFP_Msk (0xful << SYS_GPN_MFPH_PN13MFP_Pos) /*!< SYS_T::GPN_MFPH: PN13MFP Mask */ + +#define SYS_GPN_MFPH_PN14MFP_Pos (24) /*!< SYS_T::GPN_MFPH: PN14MFP Position */ +#define SYS_GPN_MFPH_PN14MFP_Msk (0xful << SYS_GPN_MFPH_PN14MFP_Pos) /*!< SYS_T::GPN_MFPH: PN14MFP Mask */ + +#define SYS_GPN_MFPH_PN15MFP_Pos (28) /*!< SYS_T::GPN_MFPH: PN15MFP Position */ +#define SYS_GPN_MFPH_PN15MFP_Msk (0xful << SYS_GPN_MFPH_PN15MFP_Pos) /*!< SYS_T::GPN_MFPH: PN15MFP Mask */ + +#define SYS_TSENSRFCR_TSENSRREF0_Pos (0) /*!< SYS_T::TSENSRFCR: TSENSRREF0 Position */ +#define SYS_TSENSRFCR_TSENSRREF0_Msk (0xfful << SYS_TSENSRFCR_TSENSRREF0_Pos) /*!< SYS_T::TSENSRFCR: TSENSRREF0 Mask */ + +#define SYS_TSENSRFCR_TSENSRREF1_Pos (8) /*!< SYS_T::TSENSRFCR: TSENSRREF1 Position */ +#define SYS_TSENSRFCR_TSENSRREF1_Msk (0xfful << SYS_TSENSRFCR_TSENSRREF1_Pos) /*!< SYS_T::TSENSRFCR: TSENSRREF1 Mask */ + +#define SYS_TSENSRFCR_TSENSRDATA_Pos (16) /*!< SYS_T::TSENSRFCR: TSENSRDATA Position */ +#define SYS_TSENSRFCR_TSENSRDATA_Msk (0xffful << SYS_TSENSRFCR_TSENSRDATA_Pos) /*!< SYS_T::TSENSRFCR: TSENSRDATA Mask */ + +#define SYS_TSENSRFCR_PD_Pos (28) /*!< SYS_T::TSENSRFCR: PD Position */ +#define SYS_TSENSRFCR_PD_Msk (0x1ul << SYS_TSENSRFCR_PD_Pos) /*!< SYS_T::TSENSRFCR: PD Mask */ + +#define SYS_TSENSRFCR_REFUDEN_Pos (29) /*!< SYS_T::TSENSRFCR: REFUDEN Position */ +#define SYS_TSENSRFCR_REFUDEN_Msk (0x1ul << SYS_TSENSRFCR_REFUDEN_Pos) /*!< SYS_T::TSENSRFCR: REFUDEN Mask */ + +#define SYS_TSENSRFCR_DATAVALID_Pos (31) /*!< SYS_T::TSENSRFCR: DATAVALID Position */ +#define SYS_TSENSRFCR_DATAVALID_Msk (0x1ul << SYS_TSENSRFCR_DATAVALID_Pos) /*!< SYS_T::TSENSRFCR: DATAVALID Mask */ + +#define SYS_GMAC0MISCR_RMIIEN_Pos (0) /*!< SYS_T::GMAC0MISCR: RMIIEN Position */ +#define SYS_GMAC0MISCR_RMIIEN_Msk (0x1ul << SYS_GMAC0MISCR_RMIIEN_Pos) /*!< SYS_T::GMAC0MISCR: RMIIEN Mask */ + +#define SYS_GMAC0MISCR_PFRMTXEN_Pos (1) /*!< SYS_T::GMAC0MISCR: PFRMTXEN Position */ +#define SYS_GMAC0MISCR_PFRMTXEN_Msk (0x1ul << SYS_GMAC0MISCR_PFRMTXEN_Pos) /*!< SYS_T::GMAC0MISCR: PFRMTXEN Mask */ + +#define SYS_GMAC0MISCR_TXCLKINV_Pos (8) /*!< SYS_T::GMAC0MISCR: TXCLKINV Position */ +#define SYS_GMAC0MISCR_TXCLKINV_Msk (0x1ul << SYS_GMAC0MISCR_TXCLKINV_Pos) /*!< SYS_T::GMAC0MISCR: TXCLKINV Mask */ + +#define SYS_GMAC0MISCR_TXCLKGEN_Pos (9) /*!< SYS_T::GMAC0MISCR: TXCLKGEN Position */ +#define SYS_GMAC0MISCR_TXCLKGEN_Msk (0x1ul << SYS_GMAC0MISCR_TXCLKGEN_Pos) /*!< SYS_T::GMAC0MISCR: TXCLKGEN Mask */ + +#define SYS_GMAC0MISCR_RXCLKINV_Pos (12) /*!< SYS_T::GMAC0MISCR: RXCLKINV Position */ +#define SYS_GMAC0MISCR_RXCLKINV_Msk (0x1ul << SYS_GMAC0MISCR_RXCLKINV_Pos) /*!< SYS_T::GMAC0MISCR: RXCLKINV Mask */ + +#define SYS_GMAC0MISCR_TXCLKDLY_Pos (16) /*!< SYS_T::GMAC0MISCR: TXCLKDLY Position */ +#define SYS_GMAC0MISCR_TXCLKDLY_Msk (0xful << SYS_GMAC0MISCR_TXCLKDLY_Pos) /*!< SYS_T::GMAC0MISCR: TXCLKDLY Mask */ + +#define SYS_GMAC0MISCR_RXCLKDLY_Pos (20) /*!< SYS_T::GMAC0MISCR: RXCLKDLY Position */ +#define SYS_GMAC0MISCR_RXCLKDLY_Msk (0xful << SYS_GMAC0MISCR_RXCLKDLY_Pos) /*!< SYS_T::GMAC0MISCR: RXCLKDLY Mask */ + +#define SYS_GMAC1MISCR_RMIIEN_Pos (0) /*!< SYS_T::GMAC1MISCR: RMIIEN Position */ +#define SYS_GMAC1MISCR_RMIIEN_Msk (0x1ul << SYS_GMAC1MISCR_RMIIEN_Pos) /*!< SYS_T::GMAC1MISCR: RMIIEN Mask */ + +#define SYS_GMAC1MISCR_PFRMTXEN_Pos (1) /*!< SYS_T::GMAC1MISCR: PFRMTXEN Position */ +#define SYS_GMAC1MISCR_PFRMTXEN_Msk (0x1ul << SYS_GMAC1MISCR_PFRMTXEN_Pos) /*!< SYS_T::GMAC1MISCR: PFRMTXEN Mask */ + +#define SYS_GMAC1MISCR_TXCLKINV_Pos (8) /*!< SYS_T::GMAC1MISCR: TXCLKINV Position */ +#define SYS_GMAC1MISCR_TXCLKINV_Msk (0x1ul << SYS_GMAC1MISCR_TXCLKINV_Pos) /*!< SYS_T::GMAC1MISCR: TXCLKINV Mask */ + +#define SYS_GMAC1MISCR_TXCLKGEN_Pos (9) /*!< SYS_T::GMAC1MISCR: TXCLKGEN Position */ +#define SYS_GMAC1MISCR_TXCLKGEN_Msk (0x1ul << SYS_GMAC1MISCR_TXCLKGEN_Pos) /*!< SYS_T::GMAC1MISCR: TXCLKGEN Mask */ + +#define SYS_GMAC1MISCR_RXCLKINV_Pos (12) /*!< SYS_T::GMAC1MISCR: RXCLKINV Position */ +#define SYS_GMAC1MISCR_RXCLKINV_Msk (0x1ul << SYS_GMAC1MISCR_RXCLKINV_Pos) /*!< SYS_T::GMAC1MISCR: RXCLKINV Mask */ + +#define SYS_GMAC1MISCR_TXCLKDLY_Pos (16) /*!< SYS_T::GMAC1MISCR: TXCLKDLY Position */ +#define SYS_GMAC1MISCR_TXCLKDLY_Msk (0xful << SYS_GMAC1MISCR_TXCLKDLY_Pos) /*!< SYS_T::GMAC1MISCR: TXCLKDLY Mask */ + +#define SYS_GMAC1MISCR_RXCLKDLY_Pos (20) /*!< SYS_T::GMAC1MISCR: RXCLKDLY Position */ +#define SYS_GMAC1MISCR_RXCLKDLY_Msk (0xful << SYS_GMAC1MISCR_RXCLKDLY_Pos) /*!< SYS_T::GMAC1MISCR: RXCLKDLY Mask */ + +#define SYS_MACAD0LSR_MACADRLSR_Pos (0) /*!< SYS_T::MACAD0LSR: MACADRLSR Position */ +#define SYS_MACAD0LSR_MACADRLSR_Msk (0xfffffffful << SYS_MACAD0LSR_MACADRLSR_Pos) /*!< SYS_T::MACAD0LSR: MACADRLSR Mask */ + +#define SYS_MACAD0HSR_MACADRHSR_Pos (0) /*!< SYS_T::MACAD0HSR: MACADRHSR Position */ +#define SYS_MACAD0HSR_MACADRHSR_Msk (0xfffful << SYS_MACAD0HSR_MACADRHSR_Pos) /*!< SYS_T::MACAD0HSR: MACADRHSR Mask */ + +#define SYS_MACAD1LSR_MACADRLSR_Pos (0) /*!< SYS_T::MACAD1LSR: MACADRLSR Position */ +#define SYS_MACAD1LSR_MACADRLSR_Msk (0xfffffffful << SYS_MACAD1LSR_MACADRLSR_Pos) /*!< SYS_T::MACAD1LSR: MACADRLSR Mask */ + +#define SYS_MACAD1HSR_MACADRHSR_Pos (0) /*!< SYS_T::MACAD1HSR: MACADRHSR Position */ +#define SYS_MACAD1HSR_MACADRHSR_Msk (0xfffful << SYS_MACAD1HSR_MACADRHSR_Pos) /*!< SYS_T::MACAD1HSR: MACADRHSR Mask */ + +#define SYS_CSDBGCTL_DBGRST_Pos (0) /*!< SYS_T::CSDBGCTL: DBGRST Position */ +#define SYS_CSDBGCTL_DBGRST_Msk (0x1ul << SYS_CSDBGCTL_DBGRST_Pos) /*!< SYS_T::CSDBGCTL: DBGRST Mask */ + +#define SYS_CSDBGCTL_DBGPWRUPREQ_Pos (1) /*!< SYS_T::CSDBGCTL: DBGPWRUPREQ Position */ +#define SYS_CSDBGCTL_DBGPWRUPREQ_Msk (0x1ul << SYS_CSDBGCTL_DBGPWRUPREQ_Pos) /*!< SYS_T::CSDBGCTL: DBGPWRUPREQ Mask */ + +#define SYS_CSDBGCTL_DBGPWRUPACK_Pos (2) /*!< SYS_T::CSDBGCTL: DBGPWRUPACK Position */ +#define SYS_CSDBGCTL_DBGPWRUPACK_Msk (0x1ul << SYS_CSDBGCTL_DBGPWRUPACK_Pos) /*!< SYS_T::CSDBGCTL: DBGPWRUPACK Mask */ + +#define SYS_CSDBGCTL_LPEMU_Pos (3) /*!< SYS_T::CSDBGCTL: LPEMU Position */ +#define SYS_CSDBGCTL_LPEMU_Msk (0x1ul << SYS_CSDBGCTL_LPEMU_Pos) /*!< SYS_T::CSDBGCTL: LPEMU Mask */ + +#define SYS_GPAB_MFOS_GPIOxMFOS0_Pos (0) /*!< SYS_T::GPAB_MFOS: GPIOxMFOS0 Position */ +#define SYS_GPAB_MFOS_GPIOxMFOS0_Msk (0x1ul << SYS_GPAB_MFOS_GPIOxMFOS0_Pos) /*!< SYS_T::GPAB_MFOS: GPIOxMFOS0 Mask */ + +#define SYS_GPAB_MFOS_GPIOxMFOS1_Pos (1) /*!< SYS_T::GPAB_MFOS: GPIOxMFOS1 Position */ +#define SYS_GPAB_MFOS_GPIOxMFOS1_Msk (0x1ul << SYS_GPAB_MFOS_GPIOxMFOS1_Pos) /*!< SYS_T::GPAB_MFOS: GPIOxMFOS1 Mask */ + +#define SYS_GPAB_MFOS_GPIOxMFOS2_Pos (2) /*!< SYS_T::GPAB_MFOS: GPIOxMFOS2 Position */ +#define SYS_GPAB_MFOS_GPIOxMFOS2_Msk (0x1ul << SYS_GPAB_MFOS_GPIOxMFOS2_Pos) /*!< SYS_T::GPAB_MFOS: GPIOxMFOS2 Mask */ + +#define SYS_GPAB_MFOS_GPIOxMFOS3_Pos (3) /*!< SYS_T::GPAB_MFOS: GPIOxMFOS3 Position */ +#define SYS_GPAB_MFOS_GPIOxMFOS3_Msk (0x1ul << SYS_GPAB_MFOS_GPIOxMFOS3_Pos) /*!< SYS_T::GPAB_MFOS: GPIOxMFOS3 Mask */ + +#define SYS_GPAB_MFOS_GPIOxMFOS4_Pos (4) /*!< SYS_T::GPAB_MFOS: GPIOxMFOS4 Position */ +#define SYS_GPAB_MFOS_GPIOxMFOS4_Msk (0x1ul << SYS_GPAB_MFOS_GPIOxMFOS4_Pos) /*!< SYS_T::GPAB_MFOS: GPIOxMFOS4 Mask */ + +#define SYS_GPAB_MFOS_GPIOxMFOS5_Pos (5) /*!< SYS_T::GPAB_MFOS: GPIOxMFOS5 Position */ +#define SYS_GPAB_MFOS_GPIOxMFOS5_Msk (0x1ul << SYS_GPAB_MFOS_GPIOxMFOS5_Pos) /*!< SYS_T::GPAB_MFOS: GPIOxMFOS5 Mask */ + +#define SYS_GPAB_MFOS_GPIOxMFOS6_Pos (6) /*!< SYS_T::GPAB_MFOS: GPIOxMFOS6 Position */ +#define SYS_GPAB_MFOS_GPIOxMFOS6_Msk (0x1ul << SYS_GPAB_MFOS_GPIOxMFOS6_Pos) /*!< SYS_T::GPAB_MFOS: GPIOxMFOS6 Mask */ + +#define SYS_GPAB_MFOS_GPIOxMFOS7_Pos (7) /*!< SYS_T::GPAB_MFOS: GPIOxMFOS7 Position */ +#define SYS_GPAB_MFOS_GPIOxMFOS7_Msk (0x1ul << SYS_GPAB_MFOS_GPIOxMFOS7_Pos) /*!< SYS_T::GPAB_MFOS: GPIOxMFOS7 Mask */ + +#define SYS_GPAB_MFOS_GPIOxMFOS8_Pos (8) /*!< SYS_T::GPAB_MFOS: GPIOxMFOS8 Position */ +#define SYS_GPAB_MFOS_GPIOxMFOS8_Msk (0x1ul << SYS_GPAB_MFOS_GPIOxMFOS8_Pos) /*!< SYS_T::GPAB_MFOS: GPIOxMFOS8 Mask */ + +#define SYS_GPAB_MFOS_GPIOxMFOS9_Pos (9) /*!< SYS_T::GPAB_MFOS: GPIOxMFOS9 Position */ +#define SYS_GPAB_MFOS_GPIOxMFOS9_Msk (0x1ul << SYS_GPAB_MFOS_GPIOxMFOS9_Pos) /*!< SYS_T::GPAB_MFOS: GPIOxMFOS9 Mask */ + +#define SYS_GPAB_MFOS_GPIOxMFOS10_Pos (10) /*!< SYS_T::GPAB_MFOS: GPIOxMFOS10 Position */ +#define SYS_GPAB_MFOS_GPIOxMFOS10_Msk (0x1ul << SYS_GPAB_MFOS_GPIOxMFOS10_Pos) /*!< SYS_T::GPAB_MFOS: GPIOxMFOS10 Mask */ + +#define SYS_GPAB_MFOS_GPIOxMFOS11_Pos (11) /*!< SYS_T::GPAB_MFOS: GPIOxMFOS11 Position */ +#define SYS_GPAB_MFOS_GPIOxMFOS11_Msk (0x1ul << SYS_GPAB_MFOS_GPIOxMFOS11_Pos) /*!< SYS_T::GPAB_MFOS: GPIOxMFOS11 Mask */ + +#define SYS_GPAB_MFOS_GPIOxMFOS12_Pos (12) /*!< SYS_T::GPAB_MFOS: GPIOxMFOS12 Position */ +#define SYS_GPAB_MFOS_GPIOxMFOS12_Msk (0x1ul << SYS_GPAB_MFOS_GPIOxMFOS12_Pos) /*!< SYS_T::GPAB_MFOS: GPIOxMFOS12 Mask */ + +#define SYS_GPAB_MFOS_GPIOxMFOS13_Pos (13) /*!< SYS_T::GPAB_MFOS: GPIOxMFOS13 Position */ +#define SYS_GPAB_MFOS_GPIOxMFOS13_Msk (0x1ul << SYS_GPAB_MFOS_GPIOxMFOS13_Pos) /*!< SYS_T::GPAB_MFOS: GPIOxMFOS13 Mask */ + +#define SYS_GPAB_MFOS_GPIOxMFOS14_Pos (14) /*!< SYS_T::GPAB_MFOS: GPIOxMFOS14 Position */ +#define SYS_GPAB_MFOS_GPIOxMFOS14_Msk (0x1ul << SYS_GPAB_MFOS_GPIOxMFOS14_Pos) /*!< SYS_T::GPAB_MFOS: GPIOxMFOS14 Mask */ + +#define SYS_GPAB_MFOS_GPIOxMFOS15_Pos (15) /*!< SYS_T::GPAB_MFOS: GPIOxMFOS15 Position */ +#define SYS_GPAB_MFOS_GPIOxMFOS15_Msk (0x1ul << SYS_GPAB_MFOS_GPIOxMFOS15_Pos) /*!< SYS_T::GPAB_MFOS: GPIOxMFOS15 Mask */ + +#define SYS_GPAB_MFOS_GPIOyMFOS16_Pos (16) /*!< SYS_T::GPAB_MFOS: GPIOyMFOS16 Position */ +#define SYS_GPAB_MFOS_GPIOyMFOS16_Msk (0x1ul << SYS_GPAB_MFOS_GPIOyMFOS16_Pos) /*!< SYS_T::GPAB_MFOS: GPIOyMFOS16 Mask */ + +#define SYS_GPAB_MFOS_GPIOyMFOS17_Pos (17) /*!< SYS_T::GPAB_MFOS: GPIOyMFOS17 Position */ +#define SYS_GPAB_MFOS_GPIOyMFOS17_Msk (0x1ul << SYS_GPAB_MFOS_GPIOyMFOS17_Pos) /*!< SYS_T::GPAB_MFOS: GPIOyMFOS17 Mask */ + +#define SYS_GPAB_MFOS_GPIOyMFOS18_Pos (18) /*!< SYS_T::GPAB_MFOS: GPIOyMFOS18 Position */ +#define SYS_GPAB_MFOS_GPIOyMFOS18_Msk (0x1ul << SYS_GPAB_MFOS_GPIOyMFOS18_Pos) /*!< SYS_T::GPAB_MFOS: GPIOyMFOS18 Mask */ + +#define SYS_GPAB_MFOS_GPIOyMFOS19_Pos (19) /*!< SYS_T::GPAB_MFOS: GPIOyMFOS19 Position */ +#define SYS_GPAB_MFOS_GPIOyMFOS19_Msk (0x1ul << SYS_GPAB_MFOS_GPIOyMFOS19_Pos) /*!< SYS_T::GPAB_MFOS: GPIOyMFOS19 Mask */ + +#define SYS_GPAB_MFOS_GPIOyMFOS20_Pos (20) /*!< SYS_T::GPAB_MFOS: GPIOyMFOS20 Position */ +#define SYS_GPAB_MFOS_GPIOyMFOS20_Msk (0x1ul << SYS_GPAB_MFOS_GPIOyMFOS20_Pos) /*!< SYS_T::GPAB_MFOS: GPIOyMFOS20 Mask */ + +#define SYS_GPAB_MFOS_GPIOyMFOS21_Pos (21) /*!< SYS_T::GPAB_MFOS: GPIOyMFOS21 Position */ +#define SYS_GPAB_MFOS_GPIOyMFOS21_Msk (0x1ul << SYS_GPAB_MFOS_GPIOyMFOS21_Pos) /*!< SYS_T::GPAB_MFOS: GPIOyMFOS21 Mask */ + +#define SYS_GPAB_MFOS_GPIOyMFOS22_Pos (22) /*!< SYS_T::GPAB_MFOS: GPIOyMFOS22 Position */ +#define SYS_GPAB_MFOS_GPIOyMFOS22_Msk (0x1ul << SYS_GPAB_MFOS_GPIOyMFOS22_Pos) /*!< SYS_T::GPAB_MFOS: GPIOyMFOS22 Mask */ + +#define SYS_GPAB_MFOS_GPIOyMFOS23_Pos (23) /*!< SYS_T::GPAB_MFOS: GPIOyMFOS23 Position */ +#define SYS_GPAB_MFOS_GPIOyMFOS23_Msk (0x1ul << SYS_GPAB_MFOS_GPIOyMFOS23_Pos) /*!< SYS_T::GPAB_MFOS: GPIOyMFOS23 Mask */ + +#define SYS_GPAB_MFOS_GPIOyMFOS24_Pos (24) /*!< SYS_T::GPAB_MFOS: GPIOyMFOS24 Position */ +#define SYS_GPAB_MFOS_GPIOyMFOS24_Msk (0x1ul << SYS_GPAB_MFOS_GPIOyMFOS24_Pos) /*!< SYS_T::GPAB_MFOS: GPIOyMFOS24 Mask */ + +#define SYS_GPAB_MFOS_GPIOyMFOS25_Pos (25) /*!< SYS_T::GPAB_MFOS: GPIOyMFOS25 Position */ +#define SYS_GPAB_MFOS_GPIOyMFOS25_Msk (0x1ul << SYS_GPAB_MFOS_GPIOyMFOS25_Pos) /*!< SYS_T::GPAB_MFOS: GPIOyMFOS25 Mask */ + +#define SYS_GPAB_MFOS_GPIOyMFOS26_Pos (26) /*!< SYS_T::GPAB_MFOS: GPIOyMFOS26 Position */ +#define SYS_GPAB_MFOS_GPIOyMFOS26_Msk (0x1ul << SYS_GPAB_MFOS_GPIOyMFOS26_Pos) /*!< SYS_T::GPAB_MFOS: GPIOyMFOS26 Mask */ + +#define SYS_GPAB_MFOS_GPIOyMFOS27_Pos (27) /*!< SYS_T::GPAB_MFOS: GPIOyMFOS27 Position */ +#define SYS_GPAB_MFOS_GPIOyMFOS27_Msk (0x1ul << SYS_GPAB_MFOS_GPIOyMFOS27_Pos) /*!< SYS_T::GPAB_MFOS: GPIOyMFOS27 Mask */ + +#define SYS_GPAB_MFOS_GPIOyMFOS28_Pos (28) /*!< SYS_T::GPAB_MFOS: GPIOyMFOS28 Position */ +#define SYS_GPAB_MFOS_GPIOyMFOS28_Msk (0x1ul << SYS_GPAB_MFOS_GPIOyMFOS28_Pos) /*!< SYS_T::GPAB_MFOS: GPIOyMFOS28 Mask */ + +#define SYS_GPAB_MFOS_GPIOyMFOS29_Pos (29) /*!< SYS_T::GPAB_MFOS: GPIOyMFOS29 Position */ +#define SYS_GPAB_MFOS_GPIOyMFOS29_Msk (0x1ul << SYS_GPAB_MFOS_GPIOyMFOS29_Pos) /*!< SYS_T::GPAB_MFOS: GPIOyMFOS29 Mask */ + +#define SYS_GPAB_MFOS_GPIOyMFOS30_Pos (30) /*!< SYS_T::GPAB_MFOS: GPIOyMFOS30 Position */ +#define SYS_GPAB_MFOS_GPIOyMFOS30_Msk (0x1ul << SYS_GPAB_MFOS_GPIOyMFOS30_Pos) /*!< SYS_T::GPAB_MFOS: GPIOyMFOS30 Mask */ + +#define SYS_GPAB_MFOS_GPIOyMFOS31_Pos (31) /*!< SYS_T::GPAB_MFOS: GPIOyMFOS31 Position */ +#define SYS_GPAB_MFOS_GPIOyMFOS31_Msk (0x1ul << SYS_GPAB_MFOS_GPIOyMFOS31_Pos) /*!< SYS_T::GPAB_MFOS: GPIOyMFOS31 Mask */ + +#define SYS_GPCD_MFOS_GPIOxMFOS0_Pos (0) /*!< SYS_T::GPCD_MFOS: GPIOxMFOS0 Position */ +#define SYS_GPCD_MFOS_GPIOxMFOS0_Msk (0x1ul << SYS_GPCD_MFOS_GPIOxMFOS0_Pos) /*!< SYS_T::GPCD_MFOS: GPIOxMFOS0 Mask */ + +#define SYS_GPCD_MFOS_GPIOxMFOS1_Pos (1) /*!< SYS_T::GPCD_MFOS: GPIOxMFOS1 Position */ +#define SYS_GPCD_MFOS_GPIOxMFOS1_Msk (0x1ul << SYS_GPCD_MFOS_GPIOxMFOS1_Pos) /*!< SYS_T::GPCD_MFOS: GPIOxMFOS1 Mask */ + +#define SYS_GPCD_MFOS_GPIOxMFOS2_Pos (2) /*!< SYS_T::GPCD_MFOS: GPIOxMFOS2 Position */ +#define SYS_GPCD_MFOS_GPIOxMFOS2_Msk (0x1ul << SYS_GPCD_MFOS_GPIOxMFOS2_Pos) /*!< SYS_T::GPCD_MFOS: GPIOxMFOS2 Mask */ + +#define SYS_GPCD_MFOS_GPIOxMFOS3_Pos (3) /*!< SYS_T::GPCD_MFOS: GPIOxMFOS3 Position */ +#define SYS_GPCD_MFOS_GPIOxMFOS3_Msk (0x1ul << SYS_GPCD_MFOS_GPIOxMFOS3_Pos) /*!< SYS_T::GPCD_MFOS: GPIOxMFOS3 Mask */ + +#define SYS_GPCD_MFOS_GPIOxMFOS4_Pos (4) /*!< SYS_T::GPCD_MFOS: GPIOxMFOS4 Position */ +#define SYS_GPCD_MFOS_GPIOxMFOS4_Msk (0x1ul << SYS_GPCD_MFOS_GPIOxMFOS4_Pos) /*!< SYS_T::GPCD_MFOS: GPIOxMFOS4 Mask */ + +#define SYS_GPCD_MFOS_GPIOxMFOS5_Pos (5) /*!< SYS_T::GPCD_MFOS: GPIOxMFOS5 Position */ +#define SYS_GPCD_MFOS_GPIOxMFOS5_Msk (0x1ul << SYS_GPCD_MFOS_GPIOxMFOS5_Pos) /*!< SYS_T::GPCD_MFOS: GPIOxMFOS5 Mask */ + +#define SYS_GPCD_MFOS_GPIOxMFOS6_Pos (6) /*!< SYS_T::GPCD_MFOS: GPIOxMFOS6 Position */ +#define SYS_GPCD_MFOS_GPIOxMFOS6_Msk (0x1ul << SYS_GPCD_MFOS_GPIOxMFOS6_Pos) /*!< SYS_T::GPCD_MFOS: GPIOxMFOS6 Mask */ + +#define SYS_GPCD_MFOS_GPIOxMFOS7_Pos (7) /*!< SYS_T::GPCD_MFOS: GPIOxMFOS7 Position */ +#define SYS_GPCD_MFOS_GPIOxMFOS7_Msk (0x1ul << SYS_GPCD_MFOS_GPIOxMFOS7_Pos) /*!< SYS_T::GPCD_MFOS: GPIOxMFOS7 Mask */ + +#define SYS_GPCD_MFOS_GPIOxMFOS8_Pos (8) /*!< SYS_T::GPCD_MFOS: GPIOxMFOS8 Position */ +#define SYS_GPCD_MFOS_GPIOxMFOS8_Msk (0x1ul << SYS_GPCD_MFOS_GPIOxMFOS8_Pos) /*!< SYS_T::GPCD_MFOS: GPIOxMFOS8 Mask */ + +#define SYS_GPCD_MFOS_GPIOxMFOS9_Pos (9) /*!< SYS_T::GPCD_MFOS: GPIOxMFOS9 Position */ +#define SYS_GPCD_MFOS_GPIOxMFOS9_Msk (0x1ul << SYS_GPCD_MFOS_GPIOxMFOS9_Pos) /*!< SYS_T::GPCD_MFOS: GPIOxMFOS9 Mask */ + +#define SYS_GPCD_MFOS_GPIOxMFOS10_Pos (10) /*!< SYS_T::GPCD_MFOS: GPIOxMFOS10 Position */ +#define SYS_GPCD_MFOS_GPIOxMFOS10_Msk (0x1ul << SYS_GPCD_MFOS_GPIOxMFOS10_Pos) /*!< SYS_T::GPCD_MFOS: GPIOxMFOS10 Mask */ + +#define SYS_GPCD_MFOS_GPIOxMFOS11_Pos (11) /*!< SYS_T::GPCD_MFOS: GPIOxMFOS11 Position */ +#define SYS_GPCD_MFOS_GPIOxMFOS11_Msk (0x1ul << SYS_GPCD_MFOS_GPIOxMFOS11_Pos) /*!< SYS_T::GPCD_MFOS: GPIOxMFOS11 Mask */ + +#define SYS_GPCD_MFOS_GPIOxMFOS12_Pos (12) /*!< SYS_T::GPCD_MFOS: GPIOxMFOS12 Position */ +#define SYS_GPCD_MFOS_GPIOxMFOS12_Msk (0x1ul << SYS_GPCD_MFOS_GPIOxMFOS12_Pos) /*!< SYS_T::GPCD_MFOS: GPIOxMFOS12 Mask */ + +#define SYS_GPCD_MFOS_GPIOxMFOS13_Pos (13) /*!< SYS_T::GPCD_MFOS: GPIOxMFOS13 Position */ +#define SYS_GPCD_MFOS_GPIOxMFOS13_Msk (0x1ul << SYS_GPCD_MFOS_GPIOxMFOS13_Pos) /*!< SYS_T::GPCD_MFOS: GPIOxMFOS13 Mask */ + +#define SYS_GPCD_MFOS_GPIOxMFOS14_Pos (14) /*!< SYS_T::GPCD_MFOS: GPIOxMFOS14 Position */ +#define SYS_GPCD_MFOS_GPIOxMFOS14_Msk (0x1ul << SYS_GPCD_MFOS_GPIOxMFOS14_Pos) /*!< SYS_T::GPCD_MFOS: GPIOxMFOS14 Mask */ + +#define SYS_GPCD_MFOS_GPIOxMFOS15_Pos (15) /*!< SYS_T::GPCD_MFOS: GPIOxMFOS15 Position */ +#define SYS_GPCD_MFOS_GPIOxMFOS15_Msk (0x1ul << SYS_GPCD_MFOS_GPIOxMFOS15_Pos) /*!< SYS_T::GPCD_MFOS: GPIOxMFOS15 Mask */ + +#define SYS_GPCD_MFOS_GPIOyMFOS16_Pos (16) /*!< SYS_T::GPCD_MFOS: GPIOyMFOS16 Position */ +#define SYS_GPCD_MFOS_GPIOyMFOS16_Msk (0x1ul << SYS_GPCD_MFOS_GPIOyMFOS16_Pos) /*!< SYS_T::GPCD_MFOS: GPIOyMFOS16 Mask */ + +#define SYS_GPCD_MFOS_GPIOyMFOS17_Pos (17) /*!< SYS_T::GPCD_MFOS: GPIOyMFOS17 Position */ +#define SYS_GPCD_MFOS_GPIOyMFOS17_Msk (0x1ul << SYS_GPCD_MFOS_GPIOyMFOS17_Pos) /*!< SYS_T::GPCD_MFOS: GPIOyMFOS17 Mask */ + +#define SYS_GPCD_MFOS_GPIOyMFOS18_Pos (18) /*!< SYS_T::GPCD_MFOS: GPIOyMFOS18 Position */ +#define SYS_GPCD_MFOS_GPIOyMFOS18_Msk (0x1ul << SYS_GPCD_MFOS_GPIOyMFOS18_Pos) /*!< SYS_T::GPCD_MFOS: GPIOyMFOS18 Mask */ + +#define SYS_GPCD_MFOS_GPIOyMFOS19_Pos (19) /*!< SYS_T::GPCD_MFOS: GPIOyMFOS19 Position */ +#define SYS_GPCD_MFOS_GPIOyMFOS19_Msk (0x1ul << SYS_GPCD_MFOS_GPIOyMFOS19_Pos) /*!< SYS_T::GPCD_MFOS: GPIOyMFOS19 Mask */ + +#define SYS_GPCD_MFOS_GPIOyMFOS20_Pos (20) /*!< SYS_T::GPCD_MFOS: GPIOyMFOS20 Position */ +#define SYS_GPCD_MFOS_GPIOyMFOS20_Msk (0x1ul << SYS_GPCD_MFOS_GPIOyMFOS20_Pos) /*!< SYS_T::GPCD_MFOS: GPIOyMFOS20 Mask */ + +#define SYS_GPCD_MFOS_GPIOyMFOS21_Pos (21) /*!< SYS_T::GPCD_MFOS: GPIOyMFOS21 Position */ +#define SYS_GPCD_MFOS_GPIOyMFOS21_Msk (0x1ul << SYS_GPCD_MFOS_GPIOyMFOS21_Pos) /*!< SYS_T::GPCD_MFOS: GPIOyMFOS21 Mask */ + +#define SYS_GPCD_MFOS_GPIOyMFOS22_Pos (22) /*!< SYS_T::GPCD_MFOS: GPIOyMFOS22 Position */ +#define SYS_GPCD_MFOS_GPIOyMFOS22_Msk (0x1ul << SYS_GPCD_MFOS_GPIOyMFOS22_Pos) /*!< SYS_T::GPCD_MFOS: GPIOyMFOS22 Mask */ + +#define SYS_GPCD_MFOS_GPIOyMFOS23_Pos (23) /*!< SYS_T::GPCD_MFOS: GPIOyMFOS23 Position */ +#define SYS_GPCD_MFOS_GPIOyMFOS23_Msk (0x1ul << SYS_GPCD_MFOS_GPIOyMFOS23_Pos) /*!< SYS_T::GPCD_MFOS: GPIOyMFOS23 Mask */ + +#define SYS_GPCD_MFOS_GPIOyMFOS24_Pos (24) /*!< SYS_T::GPCD_MFOS: GPIOyMFOS24 Position */ +#define SYS_GPCD_MFOS_GPIOyMFOS24_Msk (0x1ul << SYS_GPCD_MFOS_GPIOyMFOS24_Pos) /*!< SYS_T::GPCD_MFOS: GPIOyMFOS24 Mask */ + +#define SYS_GPCD_MFOS_GPIOyMFOS25_Pos (25) /*!< SYS_T::GPCD_MFOS: GPIOyMFOS25 Position */ +#define SYS_GPCD_MFOS_GPIOyMFOS25_Msk (0x1ul << SYS_GPCD_MFOS_GPIOyMFOS25_Pos) /*!< SYS_T::GPCD_MFOS: GPIOyMFOS25 Mask */ + +#define SYS_GPCD_MFOS_GPIOyMFOS26_Pos (26) /*!< SYS_T::GPCD_MFOS: GPIOyMFOS26 Position */ +#define SYS_GPCD_MFOS_GPIOyMFOS26_Msk (0x1ul << SYS_GPCD_MFOS_GPIOyMFOS26_Pos) /*!< SYS_T::GPCD_MFOS: GPIOyMFOS26 Mask */ + +#define SYS_GPCD_MFOS_GPIOyMFOS27_Pos (27) /*!< SYS_T::GPCD_MFOS: GPIOyMFOS27 Position */ +#define SYS_GPCD_MFOS_GPIOyMFOS27_Msk (0x1ul << SYS_GPCD_MFOS_GPIOyMFOS27_Pos) /*!< SYS_T::GPCD_MFOS: GPIOyMFOS27 Mask */ + +#define SYS_GPCD_MFOS_GPIOyMFOS28_Pos (28) /*!< SYS_T::GPCD_MFOS: GPIOyMFOS28 Position */ +#define SYS_GPCD_MFOS_GPIOyMFOS28_Msk (0x1ul << SYS_GPCD_MFOS_GPIOyMFOS28_Pos) /*!< SYS_T::GPCD_MFOS: GPIOyMFOS28 Mask */ + +#define SYS_GPCD_MFOS_GPIOyMFOS29_Pos (29) /*!< SYS_T::GPCD_MFOS: GPIOyMFOS29 Position */ +#define SYS_GPCD_MFOS_GPIOyMFOS29_Msk (0x1ul << SYS_GPCD_MFOS_GPIOyMFOS29_Pos) /*!< SYS_T::GPCD_MFOS: GPIOyMFOS29 Mask */ + +#define SYS_GPCD_MFOS_GPIOyMFOS30_Pos (30) /*!< SYS_T::GPCD_MFOS: GPIOyMFOS30 Position */ +#define SYS_GPCD_MFOS_GPIOyMFOS30_Msk (0x1ul << SYS_GPCD_MFOS_GPIOyMFOS30_Pos) /*!< SYS_T::GPCD_MFOS: GPIOyMFOS30 Mask */ + +#define SYS_GPCD_MFOS_GPIOyMFOS31_Pos (31) /*!< SYS_T::GPCD_MFOS: GPIOyMFOS31 Position */ +#define SYS_GPCD_MFOS_GPIOyMFOS31_Msk (0x1ul << SYS_GPCD_MFOS_GPIOyMFOS31_Pos) /*!< SYS_T::GPCD_MFOS: GPIOyMFOS31 Mask */ + +#define SYS_GPEF_MFOS_GPIOxMFOS0_Pos (0) /*!< SYS_T::GPEF_MFOS: GPIOxMFOS0 Position */ +#define SYS_GPEF_MFOS_GPIOxMFOS0_Msk (0x1ul << SYS_GPEF_MFOS_GPIOxMFOS0_Pos) /*!< SYS_T::GPEF_MFOS: GPIOxMFOS0 Mask */ + +#define SYS_GPEF_MFOS_GPIOxMFOS1_Pos (1) /*!< SYS_T::GPEF_MFOS: GPIOxMFOS1 Position */ +#define SYS_GPEF_MFOS_GPIOxMFOS1_Msk (0x1ul << SYS_GPEF_MFOS_GPIOxMFOS1_Pos) /*!< SYS_T::GPEF_MFOS: GPIOxMFOS1 Mask */ + +#define SYS_GPEF_MFOS_GPIOxMFOS2_Pos (2) /*!< SYS_T::GPEF_MFOS: GPIOxMFOS2 Position */ +#define SYS_GPEF_MFOS_GPIOxMFOS2_Msk (0x1ul << SYS_GPEF_MFOS_GPIOxMFOS2_Pos) /*!< SYS_T::GPEF_MFOS: GPIOxMFOS2 Mask */ + +#define SYS_GPEF_MFOS_GPIOxMFOS3_Pos (3) /*!< SYS_T::GPEF_MFOS: GPIOxMFOS3 Position */ +#define SYS_GPEF_MFOS_GPIOxMFOS3_Msk (0x1ul << SYS_GPEF_MFOS_GPIOxMFOS3_Pos) /*!< SYS_T::GPEF_MFOS: GPIOxMFOS3 Mask */ + +#define SYS_GPEF_MFOS_GPIOxMFOS4_Pos (4) /*!< SYS_T::GPEF_MFOS: GPIOxMFOS4 Position */ +#define SYS_GPEF_MFOS_GPIOxMFOS4_Msk (0x1ul << SYS_GPEF_MFOS_GPIOxMFOS4_Pos) /*!< SYS_T::GPEF_MFOS: GPIOxMFOS4 Mask */ + +#define SYS_GPEF_MFOS_GPIOxMFOS5_Pos (5) /*!< SYS_T::GPEF_MFOS: GPIOxMFOS5 Position */ +#define SYS_GPEF_MFOS_GPIOxMFOS5_Msk (0x1ul << SYS_GPEF_MFOS_GPIOxMFOS5_Pos) /*!< SYS_T::GPEF_MFOS: GPIOxMFOS5 Mask */ + +#define SYS_GPEF_MFOS_GPIOxMFOS6_Pos (6) /*!< SYS_T::GPEF_MFOS: GPIOxMFOS6 Position */ +#define SYS_GPEF_MFOS_GPIOxMFOS6_Msk (0x1ul << SYS_GPEF_MFOS_GPIOxMFOS6_Pos) /*!< SYS_T::GPEF_MFOS: GPIOxMFOS6 Mask */ + +#define SYS_GPEF_MFOS_GPIOxMFOS7_Pos (7) /*!< SYS_T::GPEF_MFOS: GPIOxMFOS7 Position */ +#define SYS_GPEF_MFOS_GPIOxMFOS7_Msk (0x1ul << SYS_GPEF_MFOS_GPIOxMFOS7_Pos) /*!< SYS_T::GPEF_MFOS: GPIOxMFOS7 Mask */ + +#define SYS_GPEF_MFOS_GPIOxMFOS8_Pos (8) /*!< SYS_T::GPEF_MFOS: GPIOxMFOS8 Position */ +#define SYS_GPEF_MFOS_GPIOxMFOS8_Msk (0x1ul << SYS_GPEF_MFOS_GPIOxMFOS8_Pos) /*!< SYS_T::GPEF_MFOS: GPIOxMFOS8 Mask */ + +#define SYS_GPEF_MFOS_GPIOxMFOS9_Pos (9) /*!< SYS_T::GPEF_MFOS: GPIOxMFOS9 Position */ +#define SYS_GPEF_MFOS_GPIOxMFOS9_Msk (0x1ul << SYS_GPEF_MFOS_GPIOxMFOS9_Pos) /*!< SYS_T::GPEF_MFOS: GPIOxMFOS9 Mask */ + +#define SYS_GPEF_MFOS_GPIOxMFOS10_Pos (10) /*!< SYS_T::GPEF_MFOS: GPIOxMFOS10 Position */ +#define SYS_GPEF_MFOS_GPIOxMFOS10_Msk (0x1ul << SYS_GPEF_MFOS_GPIOxMFOS10_Pos) /*!< SYS_T::GPEF_MFOS: GPIOxMFOS10 Mask */ + +#define SYS_GPEF_MFOS_GPIOxMFOS11_Pos (11) /*!< SYS_T::GPEF_MFOS: GPIOxMFOS11 Position */ +#define SYS_GPEF_MFOS_GPIOxMFOS11_Msk (0x1ul << SYS_GPEF_MFOS_GPIOxMFOS11_Pos) /*!< SYS_T::GPEF_MFOS: GPIOxMFOS11 Mask */ + +#define SYS_GPEF_MFOS_GPIOxMFOS12_Pos (12) /*!< SYS_T::GPEF_MFOS: GPIOxMFOS12 Position */ +#define SYS_GPEF_MFOS_GPIOxMFOS12_Msk (0x1ul << SYS_GPEF_MFOS_GPIOxMFOS12_Pos) /*!< SYS_T::GPEF_MFOS: GPIOxMFOS12 Mask */ + +#define SYS_GPEF_MFOS_GPIOxMFOS13_Pos (13) /*!< SYS_T::GPEF_MFOS: GPIOxMFOS13 Position */ +#define SYS_GPEF_MFOS_GPIOxMFOS13_Msk (0x1ul << SYS_GPEF_MFOS_GPIOxMFOS13_Pos) /*!< SYS_T::GPEF_MFOS: GPIOxMFOS13 Mask */ + +#define SYS_GPEF_MFOS_GPIOxMFOS14_Pos (14) /*!< SYS_T::GPEF_MFOS: GPIOxMFOS14 Position */ +#define SYS_GPEF_MFOS_GPIOxMFOS14_Msk (0x1ul << SYS_GPEF_MFOS_GPIOxMFOS14_Pos) /*!< SYS_T::GPEF_MFOS: GPIOxMFOS14 Mask */ + +#define SYS_GPEF_MFOS_GPIOxMFOS15_Pos (15) /*!< SYS_T::GPEF_MFOS: GPIOxMFOS15 Position */ +#define SYS_GPEF_MFOS_GPIOxMFOS15_Msk (0x1ul << SYS_GPEF_MFOS_GPIOxMFOS15_Pos) /*!< SYS_T::GPEF_MFOS: GPIOxMFOS15 Mask */ + +#define SYS_GPEF_MFOS_GPIOyMFOS16_Pos (16) /*!< SYS_T::GPEF_MFOS: GPIOyMFOS16 Position */ +#define SYS_GPEF_MFOS_GPIOyMFOS16_Msk (0x1ul << SYS_GPEF_MFOS_GPIOyMFOS16_Pos) /*!< SYS_T::GPEF_MFOS: GPIOyMFOS16 Mask */ + +#define SYS_GPEF_MFOS_GPIOyMFOS17_Pos (17) /*!< SYS_T::GPEF_MFOS: GPIOyMFOS17 Position */ +#define SYS_GPEF_MFOS_GPIOyMFOS17_Msk (0x1ul << SYS_GPEF_MFOS_GPIOyMFOS17_Pos) /*!< SYS_T::GPEF_MFOS: GPIOyMFOS17 Mask */ + +#define SYS_GPEF_MFOS_GPIOyMFOS18_Pos (18) /*!< SYS_T::GPEF_MFOS: GPIOyMFOS18 Position */ +#define SYS_GPEF_MFOS_GPIOyMFOS18_Msk (0x1ul << SYS_GPEF_MFOS_GPIOyMFOS18_Pos) /*!< SYS_T::GPEF_MFOS: GPIOyMFOS18 Mask */ + +#define SYS_GPEF_MFOS_GPIOyMFOS19_Pos (19) /*!< SYS_T::GPEF_MFOS: GPIOyMFOS19 Position */ +#define SYS_GPEF_MFOS_GPIOyMFOS19_Msk (0x1ul << SYS_GPEF_MFOS_GPIOyMFOS19_Pos) /*!< SYS_T::GPEF_MFOS: GPIOyMFOS19 Mask */ + +#define SYS_GPEF_MFOS_GPIOyMFOS20_Pos (20) /*!< SYS_T::GPEF_MFOS: GPIOyMFOS20 Position */ +#define SYS_GPEF_MFOS_GPIOyMFOS20_Msk (0x1ul << SYS_GPEF_MFOS_GPIOyMFOS20_Pos) /*!< SYS_T::GPEF_MFOS: GPIOyMFOS20 Mask */ + +#define SYS_GPEF_MFOS_GPIOyMFOS21_Pos (21) /*!< SYS_T::GPEF_MFOS: GPIOyMFOS21 Position */ +#define SYS_GPEF_MFOS_GPIOyMFOS21_Msk (0x1ul << SYS_GPEF_MFOS_GPIOyMFOS21_Pos) /*!< SYS_T::GPEF_MFOS: GPIOyMFOS21 Mask */ + +#define SYS_GPEF_MFOS_GPIOyMFOS22_Pos (22) /*!< SYS_T::GPEF_MFOS: GPIOyMFOS22 Position */ +#define SYS_GPEF_MFOS_GPIOyMFOS22_Msk (0x1ul << SYS_GPEF_MFOS_GPIOyMFOS22_Pos) /*!< SYS_T::GPEF_MFOS: GPIOyMFOS22 Mask */ + +#define SYS_GPEF_MFOS_GPIOyMFOS23_Pos (23) /*!< SYS_T::GPEF_MFOS: GPIOyMFOS23 Position */ +#define SYS_GPEF_MFOS_GPIOyMFOS23_Msk (0x1ul << SYS_GPEF_MFOS_GPIOyMFOS23_Pos) /*!< SYS_T::GPEF_MFOS: GPIOyMFOS23 Mask */ + +#define SYS_GPEF_MFOS_GPIOyMFOS24_Pos (24) /*!< SYS_T::GPEF_MFOS: GPIOyMFOS24 Position */ +#define SYS_GPEF_MFOS_GPIOyMFOS24_Msk (0x1ul << SYS_GPEF_MFOS_GPIOyMFOS24_Pos) /*!< SYS_T::GPEF_MFOS: GPIOyMFOS24 Mask */ + +#define SYS_GPEF_MFOS_GPIOyMFOS25_Pos (25) /*!< SYS_T::GPEF_MFOS: GPIOyMFOS25 Position */ +#define SYS_GPEF_MFOS_GPIOyMFOS25_Msk (0x1ul << SYS_GPEF_MFOS_GPIOyMFOS25_Pos) /*!< SYS_T::GPEF_MFOS: GPIOyMFOS25 Mask */ + +#define SYS_GPEF_MFOS_GPIOyMFOS26_Pos (26) /*!< SYS_T::GPEF_MFOS: GPIOyMFOS26 Position */ +#define SYS_GPEF_MFOS_GPIOyMFOS26_Msk (0x1ul << SYS_GPEF_MFOS_GPIOyMFOS26_Pos) /*!< SYS_T::GPEF_MFOS: GPIOyMFOS26 Mask */ + +#define SYS_GPEF_MFOS_GPIOyMFOS27_Pos (27) /*!< SYS_T::GPEF_MFOS: GPIOyMFOS27 Position */ +#define SYS_GPEF_MFOS_GPIOyMFOS27_Msk (0x1ul << SYS_GPEF_MFOS_GPIOyMFOS27_Pos) /*!< SYS_T::GPEF_MFOS: GPIOyMFOS27 Mask */ + +#define SYS_GPEF_MFOS_GPIOyMFOS28_Pos (28) /*!< SYS_T::GPEF_MFOS: GPIOyMFOS28 Position */ +#define SYS_GPEF_MFOS_GPIOyMFOS28_Msk (0x1ul << SYS_GPEF_MFOS_GPIOyMFOS28_Pos) /*!< SYS_T::GPEF_MFOS: GPIOyMFOS28 Mask */ + +#define SYS_GPEF_MFOS_GPIOyMFOS29_Pos (29) /*!< SYS_T::GPEF_MFOS: GPIOyMFOS29 Position */ +#define SYS_GPEF_MFOS_GPIOyMFOS29_Msk (0x1ul << SYS_GPEF_MFOS_GPIOyMFOS29_Pos) /*!< SYS_T::GPEF_MFOS: GPIOyMFOS29 Mask */ + +#define SYS_GPEF_MFOS_GPIOyMFOS30_Pos (30) /*!< SYS_T::GPEF_MFOS: GPIOyMFOS30 Position */ +#define SYS_GPEF_MFOS_GPIOyMFOS30_Msk (0x1ul << SYS_GPEF_MFOS_GPIOyMFOS30_Pos) /*!< SYS_T::GPEF_MFOS: GPIOyMFOS30 Mask */ + +#define SYS_GPEF_MFOS_GPIOyMFOS31_Pos (31) /*!< SYS_T::GPEF_MFOS: GPIOyMFOS31 Position */ +#define SYS_GPEF_MFOS_GPIOyMFOS31_Msk (0x1ul << SYS_GPEF_MFOS_GPIOyMFOS31_Pos) /*!< SYS_T::GPEF_MFOS: GPIOyMFOS31 Mask */ + +#define SYS_GPGH_MFOS_GPIOxMFOS0_Pos (0) /*!< SYS_T::GPGH_MFOS: GPIOxMFOS0 Position */ +#define SYS_GPGH_MFOS_GPIOxMFOS0_Msk (0x1ul << SYS_GPGH_MFOS_GPIOxMFOS0_Pos) /*!< SYS_T::GPGH_MFOS: GPIOxMFOS0 Mask */ + +#define SYS_GPGH_MFOS_GPIOxMFOS1_Pos (1) /*!< SYS_T::GPGH_MFOS: GPIOxMFOS1 Position */ +#define SYS_GPGH_MFOS_GPIOxMFOS1_Msk (0x1ul << SYS_GPGH_MFOS_GPIOxMFOS1_Pos) /*!< SYS_T::GPGH_MFOS: GPIOxMFOS1 Mask */ + +#define SYS_GPGH_MFOS_GPIOxMFOS2_Pos (2) /*!< SYS_T::GPGH_MFOS: GPIOxMFOS2 Position */ +#define SYS_GPGH_MFOS_GPIOxMFOS2_Msk (0x1ul << SYS_GPGH_MFOS_GPIOxMFOS2_Pos) /*!< SYS_T::GPGH_MFOS: GPIOxMFOS2 Mask */ + +#define SYS_GPGH_MFOS_GPIOxMFOS3_Pos (3) /*!< SYS_T::GPGH_MFOS: GPIOxMFOS3 Position */ +#define SYS_GPGH_MFOS_GPIOxMFOS3_Msk (0x1ul << SYS_GPGH_MFOS_GPIOxMFOS3_Pos) /*!< SYS_T::GPGH_MFOS: GPIOxMFOS3 Mask */ + +#define SYS_GPGH_MFOS_GPIOxMFOS4_Pos (4) /*!< SYS_T::GPGH_MFOS: GPIOxMFOS4 Position */ +#define SYS_GPGH_MFOS_GPIOxMFOS4_Msk (0x1ul << SYS_GPGH_MFOS_GPIOxMFOS4_Pos) /*!< SYS_T::GPGH_MFOS: GPIOxMFOS4 Mask */ + +#define SYS_GPGH_MFOS_GPIOxMFOS5_Pos (5) /*!< SYS_T::GPGH_MFOS: GPIOxMFOS5 Position */ +#define SYS_GPGH_MFOS_GPIOxMFOS5_Msk (0x1ul << SYS_GPGH_MFOS_GPIOxMFOS5_Pos) /*!< SYS_T::GPGH_MFOS: GPIOxMFOS5 Mask */ + +#define SYS_GPGH_MFOS_GPIOxMFOS6_Pos (6) /*!< SYS_T::GPGH_MFOS: GPIOxMFOS6 Position */ +#define SYS_GPGH_MFOS_GPIOxMFOS6_Msk (0x1ul << SYS_GPGH_MFOS_GPIOxMFOS6_Pos) /*!< SYS_T::GPGH_MFOS: GPIOxMFOS6 Mask */ + +#define SYS_GPGH_MFOS_GPIOxMFOS7_Pos (7) /*!< SYS_T::GPGH_MFOS: GPIOxMFOS7 Position */ +#define SYS_GPGH_MFOS_GPIOxMFOS7_Msk (0x1ul << SYS_GPGH_MFOS_GPIOxMFOS7_Pos) /*!< SYS_T::GPGH_MFOS: GPIOxMFOS7 Mask */ + +#define SYS_GPGH_MFOS_GPIOxMFOS8_Pos (8) /*!< SYS_T::GPGH_MFOS: GPIOxMFOS8 Position */ +#define SYS_GPGH_MFOS_GPIOxMFOS8_Msk (0x1ul << SYS_GPGH_MFOS_GPIOxMFOS8_Pos) /*!< SYS_T::GPGH_MFOS: GPIOxMFOS8 Mask */ + +#define SYS_GPGH_MFOS_GPIOxMFOS9_Pos (9) /*!< SYS_T::GPGH_MFOS: GPIOxMFOS9 Position */ +#define SYS_GPGH_MFOS_GPIOxMFOS9_Msk (0x1ul << SYS_GPGH_MFOS_GPIOxMFOS9_Pos) /*!< SYS_T::GPGH_MFOS: GPIOxMFOS9 Mask */ + +#define SYS_GPGH_MFOS_GPIOxMFOS10_Pos (10) /*!< SYS_T::GPGH_MFOS: GPIOxMFOS10 Position */ +#define SYS_GPGH_MFOS_GPIOxMFOS10_Msk (0x1ul << SYS_GPGH_MFOS_GPIOxMFOS10_Pos) /*!< SYS_T::GPGH_MFOS: GPIOxMFOS10 Mask */ + +#define SYS_GPGH_MFOS_GPIOxMFOS11_Pos (11) /*!< SYS_T::GPGH_MFOS: GPIOxMFOS11 Position */ +#define SYS_GPGH_MFOS_GPIOxMFOS11_Msk (0x1ul << SYS_GPGH_MFOS_GPIOxMFOS11_Pos) /*!< SYS_T::GPGH_MFOS: GPIOxMFOS11 Mask */ + +#define SYS_GPGH_MFOS_GPIOxMFOS12_Pos (12) /*!< SYS_T::GPGH_MFOS: GPIOxMFOS12 Position */ +#define SYS_GPGH_MFOS_GPIOxMFOS12_Msk (0x1ul << SYS_GPGH_MFOS_GPIOxMFOS12_Pos) /*!< SYS_T::GPGH_MFOS: GPIOxMFOS12 Mask */ + +#define SYS_GPGH_MFOS_GPIOxMFOS13_Pos (13) /*!< SYS_T::GPGH_MFOS: GPIOxMFOS13 Position */ +#define SYS_GPGH_MFOS_GPIOxMFOS13_Msk (0x1ul << SYS_GPGH_MFOS_GPIOxMFOS13_Pos) /*!< SYS_T::GPGH_MFOS: GPIOxMFOS13 Mask */ + +#define SYS_GPGH_MFOS_GPIOxMFOS14_Pos (14) /*!< SYS_T::GPGH_MFOS: GPIOxMFOS14 Position */ +#define SYS_GPGH_MFOS_GPIOxMFOS14_Msk (0x1ul << SYS_GPGH_MFOS_GPIOxMFOS14_Pos) /*!< SYS_T::GPGH_MFOS: GPIOxMFOS14 Mask */ + +#define SYS_GPGH_MFOS_GPIOxMFOS15_Pos (15) /*!< SYS_T::GPGH_MFOS: GPIOxMFOS15 Position */ +#define SYS_GPGH_MFOS_GPIOxMFOS15_Msk (0x1ul << SYS_GPGH_MFOS_GPIOxMFOS15_Pos) /*!< SYS_T::GPGH_MFOS: GPIOxMFOS15 Mask */ + +#define SYS_GPGH_MFOS_GPIOyMFOS16_Pos (16) /*!< SYS_T::GPGH_MFOS: GPIOyMFOS16 Position */ +#define SYS_GPGH_MFOS_GPIOyMFOS16_Msk (0x1ul << SYS_GPGH_MFOS_GPIOyMFOS16_Pos) /*!< SYS_T::GPGH_MFOS: GPIOyMFOS16 Mask */ + +#define SYS_GPGH_MFOS_GPIOyMFOS17_Pos (17) /*!< SYS_T::GPGH_MFOS: GPIOyMFOS17 Position */ +#define SYS_GPGH_MFOS_GPIOyMFOS17_Msk (0x1ul << SYS_GPGH_MFOS_GPIOyMFOS17_Pos) /*!< SYS_T::GPGH_MFOS: GPIOyMFOS17 Mask */ + +#define SYS_GPGH_MFOS_GPIOyMFOS18_Pos (18) /*!< SYS_T::GPGH_MFOS: GPIOyMFOS18 Position */ +#define SYS_GPGH_MFOS_GPIOyMFOS18_Msk (0x1ul << SYS_GPGH_MFOS_GPIOyMFOS18_Pos) /*!< SYS_T::GPGH_MFOS: GPIOyMFOS18 Mask */ + +#define SYS_GPGH_MFOS_GPIOyMFOS19_Pos (19) /*!< SYS_T::GPGH_MFOS: GPIOyMFOS19 Position */ +#define SYS_GPGH_MFOS_GPIOyMFOS19_Msk (0x1ul << SYS_GPGH_MFOS_GPIOyMFOS19_Pos) /*!< SYS_T::GPGH_MFOS: GPIOyMFOS19 Mask */ + +#define SYS_GPGH_MFOS_GPIOyMFOS20_Pos (20) /*!< SYS_T::GPGH_MFOS: GPIOyMFOS20 Position */ +#define SYS_GPGH_MFOS_GPIOyMFOS20_Msk (0x1ul << SYS_GPGH_MFOS_GPIOyMFOS20_Pos) /*!< SYS_T::GPGH_MFOS: GPIOyMFOS20 Mask */ + +#define SYS_GPGH_MFOS_GPIOyMFOS21_Pos (21) /*!< SYS_T::GPGH_MFOS: GPIOyMFOS21 Position */ +#define SYS_GPGH_MFOS_GPIOyMFOS21_Msk (0x1ul << SYS_GPGH_MFOS_GPIOyMFOS21_Pos) /*!< SYS_T::GPGH_MFOS: GPIOyMFOS21 Mask */ + +#define SYS_GPGH_MFOS_GPIOyMFOS22_Pos (22) /*!< SYS_T::GPGH_MFOS: GPIOyMFOS22 Position */ +#define SYS_GPGH_MFOS_GPIOyMFOS22_Msk (0x1ul << SYS_GPGH_MFOS_GPIOyMFOS22_Pos) /*!< SYS_T::GPGH_MFOS: GPIOyMFOS22 Mask */ + +#define SYS_GPGH_MFOS_GPIOyMFOS23_Pos (23) /*!< SYS_T::GPGH_MFOS: GPIOyMFOS23 Position */ +#define SYS_GPGH_MFOS_GPIOyMFOS23_Msk (0x1ul << SYS_GPGH_MFOS_GPIOyMFOS23_Pos) /*!< SYS_T::GPGH_MFOS: GPIOyMFOS23 Mask */ + +#define SYS_GPGH_MFOS_GPIOyMFOS24_Pos (24) /*!< SYS_T::GPGH_MFOS: GPIOyMFOS24 Position */ +#define SYS_GPGH_MFOS_GPIOyMFOS24_Msk (0x1ul << SYS_GPGH_MFOS_GPIOyMFOS24_Pos) /*!< SYS_T::GPGH_MFOS: GPIOyMFOS24 Mask */ + +#define SYS_GPGH_MFOS_GPIOyMFOS25_Pos (25) /*!< SYS_T::GPGH_MFOS: GPIOyMFOS25 Position */ +#define SYS_GPGH_MFOS_GPIOyMFOS25_Msk (0x1ul << SYS_GPGH_MFOS_GPIOyMFOS25_Pos) /*!< SYS_T::GPGH_MFOS: GPIOyMFOS25 Mask */ + +#define SYS_GPGH_MFOS_GPIOyMFOS26_Pos (26) /*!< SYS_T::GPGH_MFOS: GPIOyMFOS26 Position */ +#define SYS_GPGH_MFOS_GPIOyMFOS26_Msk (0x1ul << SYS_GPGH_MFOS_GPIOyMFOS26_Pos) /*!< SYS_T::GPGH_MFOS: GPIOyMFOS26 Mask */ + +#define SYS_GPGH_MFOS_GPIOyMFOS27_Pos (27) /*!< SYS_T::GPGH_MFOS: GPIOyMFOS27 Position */ +#define SYS_GPGH_MFOS_GPIOyMFOS27_Msk (0x1ul << SYS_GPGH_MFOS_GPIOyMFOS27_Pos) /*!< SYS_T::GPGH_MFOS: GPIOyMFOS27 Mask */ + +#define SYS_GPGH_MFOS_GPIOyMFOS28_Pos (28) /*!< SYS_T::GPGH_MFOS: GPIOyMFOS28 Position */ +#define SYS_GPGH_MFOS_GPIOyMFOS28_Msk (0x1ul << SYS_GPGH_MFOS_GPIOyMFOS28_Pos) /*!< SYS_T::GPGH_MFOS: GPIOyMFOS28 Mask */ + +#define SYS_GPGH_MFOS_GPIOyMFOS29_Pos (29) /*!< SYS_T::GPGH_MFOS: GPIOyMFOS29 Position */ +#define SYS_GPGH_MFOS_GPIOyMFOS29_Msk (0x1ul << SYS_GPGH_MFOS_GPIOyMFOS29_Pos) /*!< SYS_T::GPGH_MFOS: GPIOyMFOS29 Mask */ + +#define SYS_GPGH_MFOS_GPIOyMFOS30_Pos (30) /*!< SYS_T::GPGH_MFOS: GPIOyMFOS30 Position */ +#define SYS_GPGH_MFOS_GPIOyMFOS30_Msk (0x1ul << SYS_GPGH_MFOS_GPIOyMFOS30_Pos) /*!< SYS_T::GPGH_MFOS: GPIOyMFOS30 Mask */ + +#define SYS_GPGH_MFOS_GPIOyMFOS31_Pos (31) /*!< SYS_T::GPGH_MFOS: GPIOyMFOS31 Position */ +#define SYS_GPGH_MFOS_GPIOyMFOS31_Msk (0x1ul << SYS_GPGH_MFOS_GPIOyMFOS31_Pos) /*!< SYS_T::GPGH_MFOS: GPIOyMFOS31 Mask */ + +#define SYS_GPIJ_MFOS_GPIOxMFOS0_Pos (0) /*!< SYS_T::GPIJ_MFOS: GPIOxMFOS0 Position */ +#define SYS_GPIJ_MFOS_GPIOxMFOS0_Msk (0x1ul << SYS_GPIJ_MFOS_GPIOxMFOS0_Pos) /*!< SYS_T::GPIJ_MFOS: GPIOxMFOS0 Mask */ + +#define SYS_GPIJ_MFOS_GPIOxMFOS1_Pos (1) /*!< SYS_T::GPIJ_MFOS: GPIOxMFOS1 Position */ +#define SYS_GPIJ_MFOS_GPIOxMFOS1_Msk (0x1ul << SYS_GPIJ_MFOS_GPIOxMFOS1_Pos) /*!< SYS_T::GPIJ_MFOS: GPIOxMFOS1 Mask */ + +#define SYS_GPIJ_MFOS_GPIOxMFOS2_Pos (2) /*!< SYS_T::GPIJ_MFOS: GPIOxMFOS2 Position */ +#define SYS_GPIJ_MFOS_GPIOxMFOS2_Msk (0x1ul << SYS_GPIJ_MFOS_GPIOxMFOS2_Pos) /*!< SYS_T::GPIJ_MFOS: GPIOxMFOS2 Mask */ + +#define SYS_GPIJ_MFOS_GPIOxMFOS3_Pos (3) /*!< SYS_T::GPIJ_MFOS: GPIOxMFOS3 Position */ +#define SYS_GPIJ_MFOS_GPIOxMFOS3_Msk (0x1ul << SYS_GPIJ_MFOS_GPIOxMFOS3_Pos) /*!< SYS_T::GPIJ_MFOS: GPIOxMFOS3 Mask */ + +#define SYS_GPIJ_MFOS_GPIOxMFOS4_Pos (4) /*!< SYS_T::GPIJ_MFOS: GPIOxMFOS4 Position */ +#define SYS_GPIJ_MFOS_GPIOxMFOS4_Msk (0x1ul << SYS_GPIJ_MFOS_GPIOxMFOS4_Pos) /*!< SYS_T::GPIJ_MFOS: GPIOxMFOS4 Mask */ + +#define SYS_GPIJ_MFOS_GPIOxMFOS5_Pos (5) /*!< SYS_T::GPIJ_MFOS: GPIOxMFOS5 Position */ +#define SYS_GPIJ_MFOS_GPIOxMFOS5_Msk (0x1ul << SYS_GPIJ_MFOS_GPIOxMFOS5_Pos) /*!< SYS_T::GPIJ_MFOS: GPIOxMFOS5 Mask */ + +#define SYS_GPIJ_MFOS_GPIOxMFOS6_Pos (6) /*!< SYS_T::GPIJ_MFOS: GPIOxMFOS6 Position */ +#define SYS_GPIJ_MFOS_GPIOxMFOS6_Msk (0x1ul << SYS_GPIJ_MFOS_GPIOxMFOS6_Pos) /*!< SYS_T::GPIJ_MFOS: GPIOxMFOS6 Mask */ + +#define SYS_GPIJ_MFOS_GPIOxMFOS7_Pos (7) /*!< SYS_T::GPIJ_MFOS: GPIOxMFOS7 Position */ +#define SYS_GPIJ_MFOS_GPIOxMFOS7_Msk (0x1ul << SYS_GPIJ_MFOS_GPIOxMFOS7_Pos) /*!< SYS_T::GPIJ_MFOS: GPIOxMFOS7 Mask */ + +#define SYS_GPIJ_MFOS_GPIOxMFOS8_Pos (8) /*!< SYS_T::GPIJ_MFOS: GPIOxMFOS8 Position */ +#define SYS_GPIJ_MFOS_GPIOxMFOS8_Msk (0x1ul << SYS_GPIJ_MFOS_GPIOxMFOS8_Pos) /*!< SYS_T::GPIJ_MFOS: GPIOxMFOS8 Mask */ + +#define SYS_GPIJ_MFOS_GPIOxMFOS9_Pos (9) /*!< SYS_T::GPIJ_MFOS: GPIOxMFOS9 Position */ +#define SYS_GPIJ_MFOS_GPIOxMFOS9_Msk (0x1ul << SYS_GPIJ_MFOS_GPIOxMFOS9_Pos) /*!< SYS_T::GPIJ_MFOS: GPIOxMFOS9 Mask */ + +#define SYS_GPIJ_MFOS_GPIOxMFOS10_Pos (10) /*!< SYS_T::GPIJ_MFOS: GPIOxMFOS10 Position */ +#define SYS_GPIJ_MFOS_GPIOxMFOS10_Msk (0x1ul << SYS_GPIJ_MFOS_GPIOxMFOS10_Pos) /*!< SYS_T::GPIJ_MFOS: GPIOxMFOS10 Mask */ + +#define SYS_GPIJ_MFOS_GPIOxMFOS11_Pos (11) /*!< SYS_T::GPIJ_MFOS: GPIOxMFOS11 Position */ +#define SYS_GPIJ_MFOS_GPIOxMFOS11_Msk (0x1ul << SYS_GPIJ_MFOS_GPIOxMFOS11_Pos) /*!< SYS_T::GPIJ_MFOS: GPIOxMFOS11 Mask */ + +#define SYS_GPIJ_MFOS_GPIOxMFOS12_Pos (12) /*!< SYS_T::GPIJ_MFOS: GPIOxMFOS12 Position */ +#define SYS_GPIJ_MFOS_GPIOxMFOS12_Msk (0x1ul << SYS_GPIJ_MFOS_GPIOxMFOS12_Pos) /*!< SYS_T::GPIJ_MFOS: GPIOxMFOS12 Mask */ + +#define SYS_GPIJ_MFOS_GPIOxMFOS13_Pos (13) /*!< SYS_T::GPIJ_MFOS: GPIOxMFOS13 Position */ +#define SYS_GPIJ_MFOS_GPIOxMFOS13_Msk (0x1ul << SYS_GPIJ_MFOS_GPIOxMFOS13_Pos) /*!< SYS_T::GPIJ_MFOS: GPIOxMFOS13 Mask */ + +#define SYS_GPIJ_MFOS_GPIOxMFOS14_Pos (14) /*!< SYS_T::GPIJ_MFOS: GPIOxMFOS14 Position */ +#define SYS_GPIJ_MFOS_GPIOxMFOS14_Msk (0x1ul << SYS_GPIJ_MFOS_GPIOxMFOS14_Pos) /*!< SYS_T::GPIJ_MFOS: GPIOxMFOS14 Mask */ + +#define SYS_GPIJ_MFOS_GPIOxMFOS15_Pos (15) /*!< SYS_T::GPIJ_MFOS: GPIOxMFOS15 Position */ +#define SYS_GPIJ_MFOS_GPIOxMFOS15_Msk (0x1ul << SYS_GPIJ_MFOS_GPIOxMFOS15_Pos) /*!< SYS_T::GPIJ_MFOS: GPIOxMFOS15 Mask */ + +#define SYS_GPIJ_MFOS_GPIOyMFOS16_Pos (16) /*!< SYS_T::GPIJ_MFOS: GPIOyMFOS16 Position */ +#define SYS_GPIJ_MFOS_GPIOyMFOS16_Msk (0x1ul << SYS_GPIJ_MFOS_GPIOyMFOS16_Pos) /*!< SYS_T::GPIJ_MFOS: GPIOyMFOS16 Mask */ + +#define SYS_GPIJ_MFOS_GPIOyMFOS17_Pos (17) /*!< SYS_T::GPIJ_MFOS: GPIOyMFOS17 Position */ +#define SYS_GPIJ_MFOS_GPIOyMFOS17_Msk (0x1ul << SYS_GPIJ_MFOS_GPIOyMFOS17_Pos) /*!< SYS_T::GPIJ_MFOS: GPIOyMFOS17 Mask */ + +#define SYS_GPIJ_MFOS_GPIOyMFOS18_Pos (18) /*!< SYS_T::GPIJ_MFOS: GPIOyMFOS18 Position */ +#define SYS_GPIJ_MFOS_GPIOyMFOS18_Msk (0x1ul << SYS_GPIJ_MFOS_GPIOyMFOS18_Pos) /*!< SYS_T::GPIJ_MFOS: GPIOyMFOS18 Mask */ + +#define SYS_GPIJ_MFOS_GPIOyMFOS19_Pos (19) /*!< SYS_T::GPIJ_MFOS: GPIOyMFOS19 Position */ +#define SYS_GPIJ_MFOS_GPIOyMFOS19_Msk (0x1ul << SYS_GPIJ_MFOS_GPIOyMFOS19_Pos) /*!< SYS_T::GPIJ_MFOS: GPIOyMFOS19 Mask */ + +#define SYS_GPIJ_MFOS_GPIOyMFOS20_Pos (20) /*!< SYS_T::GPIJ_MFOS: GPIOyMFOS20 Position */ +#define SYS_GPIJ_MFOS_GPIOyMFOS20_Msk (0x1ul << SYS_GPIJ_MFOS_GPIOyMFOS20_Pos) /*!< SYS_T::GPIJ_MFOS: GPIOyMFOS20 Mask */ + +#define SYS_GPIJ_MFOS_GPIOyMFOS21_Pos (21) /*!< SYS_T::GPIJ_MFOS: GPIOyMFOS21 Position */ +#define SYS_GPIJ_MFOS_GPIOyMFOS21_Msk (0x1ul << SYS_GPIJ_MFOS_GPIOyMFOS21_Pos) /*!< SYS_T::GPIJ_MFOS: GPIOyMFOS21 Mask */ + +#define SYS_GPIJ_MFOS_GPIOyMFOS22_Pos (22) /*!< SYS_T::GPIJ_MFOS: GPIOyMFOS22 Position */ +#define SYS_GPIJ_MFOS_GPIOyMFOS22_Msk (0x1ul << SYS_GPIJ_MFOS_GPIOyMFOS22_Pos) /*!< SYS_T::GPIJ_MFOS: GPIOyMFOS22 Mask */ + +#define SYS_GPIJ_MFOS_GPIOyMFOS23_Pos (23) /*!< SYS_T::GPIJ_MFOS: GPIOyMFOS23 Position */ +#define SYS_GPIJ_MFOS_GPIOyMFOS23_Msk (0x1ul << SYS_GPIJ_MFOS_GPIOyMFOS23_Pos) /*!< SYS_T::GPIJ_MFOS: GPIOyMFOS23 Mask */ + +#define SYS_GPIJ_MFOS_GPIOyMFOS24_Pos (24) /*!< SYS_T::GPIJ_MFOS: GPIOyMFOS24 Position */ +#define SYS_GPIJ_MFOS_GPIOyMFOS24_Msk (0x1ul << SYS_GPIJ_MFOS_GPIOyMFOS24_Pos) /*!< SYS_T::GPIJ_MFOS: GPIOyMFOS24 Mask */ + +#define SYS_GPIJ_MFOS_GPIOyMFOS25_Pos (25) /*!< SYS_T::GPIJ_MFOS: GPIOyMFOS25 Position */ +#define SYS_GPIJ_MFOS_GPIOyMFOS25_Msk (0x1ul << SYS_GPIJ_MFOS_GPIOyMFOS25_Pos) /*!< SYS_T::GPIJ_MFOS: GPIOyMFOS25 Mask */ + +#define SYS_GPIJ_MFOS_GPIOyMFOS26_Pos (26) /*!< SYS_T::GPIJ_MFOS: GPIOyMFOS26 Position */ +#define SYS_GPIJ_MFOS_GPIOyMFOS26_Msk (0x1ul << SYS_GPIJ_MFOS_GPIOyMFOS26_Pos) /*!< SYS_T::GPIJ_MFOS: GPIOyMFOS26 Mask */ + +#define SYS_GPIJ_MFOS_GPIOyMFOS27_Pos (27) /*!< SYS_T::GPIJ_MFOS: GPIOyMFOS27 Position */ +#define SYS_GPIJ_MFOS_GPIOyMFOS27_Msk (0x1ul << SYS_GPIJ_MFOS_GPIOyMFOS27_Pos) /*!< SYS_T::GPIJ_MFOS: GPIOyMFOS27 Mask */ + +#define SYS_GPIJ_MFOS_GPIOyMFOS28_Pos (28) /*!< SYS_T::GPIJ_MFOS: GPIOyMFOS28 Position */ +#define SYS_GPIJ_MFOS_GPIOyMFOS28_Msk (0x1ul << SYS_GPIJ_MFOS_GPIOyMFOS28_Pos) /*!< SYS_T::GPIJ_MFOS: GPIOyMFOS28 Mask */ + +#define SYS_GPIJ_MFOS_GPIOyMFOS29_Pos (29) /*!< SYS_T::GPIJ_MFOS: GPIOyMFOS29 Position */ +#define SYS_GPIJ_MFOS_GPIOyMFOS29_Msk (0x1ul << SYS_GPIJ_MFOS_GPIOyMFOS29_Pos) /*!< SYS_T::GPIJ_MFOS: GPIOyMFOS29 Mask */ + +#define SYS_GPIJ_MFOS_GPIOyMFOS30_Pos (30) /*!< SYS_T::GPIJ_MFOS: GPIOyMFOS30 Position */ +#define SYS_GPIJ_MFOS_GPIOyMFOS30_Msk (0x1ul << SYS_GPIJ_MFOS_GPIOyMFOS30_Pos) /*!< SYS_T::GPIJ_MFOS: GPIOyMFOS30 Mask */ + +#define SYS_GPIJ_MFOS_GPIOyMFOS31_Pos (31) /*!< SYS_T::GPIJ_MFOS: GPIOyMFOS31 Position */ +#define SYS_GPIJ_MFOS_GPIOyMFOS31_Msk (0x1ul << SYS_GPIJ_MFOS_GPIOyMFOS31_Pos) /*!< SYS_T::GPIJ_MFOS: GPIOyMFOS31 Mask */ + +#define SYS_GPKL_MFOS_GPIOxMFOS0_Pos (0) /*!< SYS_T::GPKL_MFOS: GPIOxMFOS0 Position */ +#define SYS_GPKL_MFOS_GPIOxMFOS0_Msk (0x1ul << SYS_GPKL_MFOS_GPIOxMFOS0_Pos) /*!< SYS_T::GPKL_MFOS: GPIOxMFOS0 Mask */ + +#define SYS_GPKL_MFOS_GPIOxMFOS1_Pos (1) /*!< SYS_T::GPKL_MFOS: GPIOxMFOS1 Position */ +#define SYS_GPKL_MFOS_GPIOxMFOS1_Msk (0x1ul << SYS_GPKL_MFOS_GPIOxMFOS1_Pos) /*!< SYS_T::GPKL_MFOS: GPIOxMFOS1 Mask */ + +#define SYS_GPKL_MFOS_GPIOxMFOS2_Pos (2) /*!< SYS_T::GPKL_MFOS: GPIOxMFOS2 Position */ +#define SYS_GPKL_MFOS_GPIOxMFOS2_Msk (0x1ul << SYS_GPKL_MFOS_GPIOxMFOS2_Pos) /*!< SYS_T::GPKL_MFOS: GPIOxMFOS2 Mask */ + +#define SYS_GPKL_MFOS_GPIOxMFOS3_Pos (3) /*!< SYS_T::GPKL_MFOS: GPIOxMFOS3 Position */ +#define SYS_GPKL_MFOS_GPIOxMFOS3_Msk (0x1ul << SYS_GPKL_MFOS_GPIOxMFOS3_Pos) /*!< SYS_T::GPKL_MFOS: GPIOxMFOS3 Mask */ + +#define SYS_GPKL_MFOS_GPIOxMFOS4_Pos (4) /*!< SYS_T::GPKL_MFOS: GPIOxMFOS4 Position */ +#define SYS_GPKL_MFOS_GPIOxMFOS4_Msk (0x1ul << SYS_GPKL_MFOS_GPIOxMFOS4_Pos) /*!< SYS_T::GPKL_MFOS: GPIOxMFOS4 Mask */ + +#define SYS_GPKL_MFOS_GPIOxMFOS5_Pos (5) /*!< SYS_T::GPKL_MFOS: GPIOxMFOS5 Position */ +#define SYS_GPKL_MFOS_GPIOxMFOS5_Msk (0x1ul << SYS_GPKL_MFOS_GPIOxMFOS5_Pos) /*!< SYS_T::GPKL_MFOS: GPIOxMFOS5 Mask */ + +#define SYS_GPKL_MFOS_GPIOxMFOS6_Pos (6) /*!< SYS_T::GPKL_MFOS: GPIOxMFOS6 Position */ +#define SYS_GPKL_MFOS_GPIOxMFOS6_Msk (0x1ul << SYS_GPKL_MFOS_GPIOxMFOS6_Pos) /*!< SYS_T::GPKL_MFOS: GPIOxMFOS6 Mask */ + +#define SYS_GPKL_MFOS_GPIOxMFOS7_Pos (7) /*!< SYS_T::GPKL_MFOS: GPIOxMFOS7 Position */ +#define SYS_GPKL_MFOS_GPIOxMFOS7_Msk (0x1ul << SYS_GPKL_MFOS_GPIOxMFOS7_Pos) /*!< SYS_T::GPKL_MFOS: GPIOxMFOS7 Mask */ + +#define SYS_GPKL_MFOS_GPIOxMFOS8_Pos (8) /*!< SYS_T::GPKL_MFOS: GPIOxMFOS8 Position */ +#define SYS_GPKL_MFOS_GPIOxMFOS8_Msk (0x1ul << SYS_GPKL_MFOS_GPIOxMFOS8_Pos) /*!< SYS_T::GPKL_MFOS: GPIOxMFOS8 Mask */ + +#define SYS_GPKL_MFOS_GPIOxMFOS9_Pos (9) /*!< SYS_T::GPKL_MFOS: GPIOxMFOS9 Position */ +#define SYS_GPKL_MFOS_GPIOxMFOS9_Msk (0x1ul << SYS_GPKL_MFOS_GPIOxMFOS9_Pos) /*!< SYS_T::GPKL_MFOS: GPIOxMFOS9 Mask */ + +#define SYS_GPKL_MFOS_GPIOxMFOS10_Pos (10) /*!< SYS_T::GPKL_MFOS: GPIOxMFOS10 Position */ +#define SYS_GPKL_MFOS_GPIOxMFOS10_Msk (0x1ul << SYS_GPKL_MFOS_GPIOxMFOS10_Pos) /*!< SYS_T::GPKL_MFOS: GPIOxMFOS10 Mask */ + +#define SYS_GPKL_MFOS_GPIOxMFOS11_Pos (11) /*!< SYS_T::GPKL_MFOS: GPIOxMFOS11 Position */ +#define SYS_GPKL_MFOS_GPIOxMFOS11_Msk (0x1ul << SYS_GPKL_MFOS_GPIOxMFOS11_Pos) /*!< SYS_T::GPKL_MFOS: GPIOxMFOS11 Mask */ + +#define SYS_GPKL_MFOS_GPIOxMFOS12_Pos (12) /*!< SYS_T::GPKL_MFOS: GPIOxMFOS12 Position */ +#define SYS_GPKL_MFOS_GPIOxMFOS12_Msk (0x1ul << SYS_GPKL_MFOS_GPIOxMFOS12_Pos) /*!< SYS_T::GPKL_MFOS: GPIOxMFOS12 Mask */ + +#define SYS_GPKL_MFOS_GPIOxMFOS13_Pos (13) /*!< SYS_T::GPKL_MFOS: GPIOxMFOS13 Position */ +#define SYS_GPKL_MFOS_GPIOxMFOS13_Msk (0x1ul << SYS_GPKL_MFOS_GPIOxMFOS13_Pos) /*!< SYS_T::GPKL_MFOS: GPIOxMFOS13 Mask */ + +#define SYS_GPKL_MFOS_GPIOxMFOS14_Pos (14) /*!< SYS_T::GPKL_MFOS: GPIOxMFOS14 Position */ +#define SYS_GPKL_MFOS_GPIOxMFOS14_Msk (0x1ul << SYS_GPKL_MFOS_GPIOxMFOS14_Pos) /*!< SYS_T::GPKL_MFOS: GPIOxMFOS14 Mask */ + +#define SYS_GPKL_MFOS_GPIOxMFOS15_Pos (15) /*!< SYS_T::GPKL_MFOS: GPIOxMFOS15 Position */ +#define SYS_GPKL_MFOS_GPIOxMFOS15_Msk (0x1ul << SYS_GPKL_MFOS_GPIOxMFOS15_Pos) /*!< SYS_T::GPKL_MFOS: GPIOxMFOS15 Mask */ + +#define SYS_GPKL_MFOS_GPIOyMFOS16_Pos (16) /*!< SYS_T::GPKL_MFOS: GPIOyMFOS16 Position */ +#define SYS_GPKL_MFOS_GPIOyMFOS16_Msk (0x1ul << SYS_GPKL_MFOS_GPIOyMFOS16_Pos) /*!< SYS_T::GPKL_MFOS: GPIOyMFOS16 Mask */ + +#define SYS_GPKL_MFOS_GPIOyMFOS17_Pos (17) /*!< SYS_T::GPKL_MFOS: GPIOyMFOS17 Position */ +#define SYS_GPKL_MFOS_GPIOyMFOS17_Msk (0x1ul << SYS_GPKL_MFOS_GPIOyMFOS17_Pos) /*!< SYS_T::GPKL_MFOS: GPIOyMFOS17 Mask */ + +#define SYS_GPKL_MFOS_GPIOyMFOS18_Pos (18) /*!< SYS_T::GPKL_MFOS: GPIOyMFOS18 Position */ +#define SYS_GPKL_MFOS_GPIOyMFOS18_Msk (0x1ul << SYS_GPKL_MFOS_GPIOyMFOS18_Pos) /*!< SYS_T::GPKL_MFOS: GPIOyMFOS18 Mask */ + +#define SYS_GPKL_MFOS_GPIOyMFOS19_Pos (19) /*!< SYS_T::GPKL_MFOS: GPIOyMFOS19 Position */ +#define SYS_GPKL_MFOS_GPIOyMFOS19_Msk (0x1ul << SYS_GPKL_MFOS_GPIOyMFOS19_Pos) /*!< SYS_T::GPKL_MFOS: GPIOyMFOS19 Mask */ + +#define SYS_GPKL_MFOS_GPIOyMFOS20_Pos (20) /*!< SYS_T::GPKL_MFOS: GPIOyMFOS20 Position */ +#define SYS_GPKL_MFOS_GPIOyMFOS20_Msk (0x1ul << SYS_GPKL_MFOS_GPIOyMFOS20_Pos) /*!< SYS_T::GPKL_MFOS: GPIOyMFOS20 Mask */ + +#define SYS_GPKL_MFOS_GPIOyMFOS21_Pos (21) /*!< SYS_T::GPKL_MFOS: GPIOyMFOS21 Position */ +#define SYS_GPKL_MFOS_GPIOyMFOS21_Msk (0x1ul << SYS_GPKL_MFOS_GPIOyMFOS21_Pos) /*!< SYS_T::GPKL_MFOS: GPIOyMFOS21 Mask */ + +#define SYS_GPKL_MFOS_GPIOyMFOS22_Pos (22) /*!< SYS_T::GPKL_MFOS: GPIOyMFOS22 Position */ +#define SYS_GPKL_MFOS_GPIOyMFOS22_Msk (0x1ul << SYS_GPKL_MFOS_GPIOyMFOS22_Pos) /*!< SYS_T::GPKL_MFOS: GPIOyMFOS22 Mask */ + +#define SYS_GPKL_MFOS_GPIOyMFOS23_Pos (23) /*!< SYS_T::GPKL_MFOS: GPIOyMFOS23 Position */ +#define SYS_GPKL_MFOS_GPIOyMFOS23_Msk (0x1ul << SYS_GPKL_MFOS_GPIOyMFOS23_Pos) /*!< SYS_T::GPKL_MFOS: GPIOyMFOS23 Mask */ + +#define SYS_GPKL_MFOS_GPIOyMFOS24_Pos (24) /*!< SYS_T::GPKL_MFOS: GPIOyMFOS24 Position */ +#define SYS_GPKL_MFOS_GPIOyMFOS24_Msk (0x1ul << SYS_GPKL_MFOS_GPIOyMFOS24_Pos) /*!< SYS_T::GPKL_MFOS: GPIOyMFOS24 Mask */ + +#define SYS_GPKL_MFOS_GPIOyMFOS25_Pos (25) /*!< SYS_T::GPKL_MFOS: GPIOyMFOS25 Position */ +#define SYS_GPKL_MFOS_GPIOyMFOS25_Msk (0x1ul << SYS_GPKL_MFOS_GPIOyMFOS25_Pos) /*!< SYS_T::GPKL_MFOS: GPIOyMFOS25 Mask */ + +#define SYS_GPKL_MFOS_GPIOyMFOS26_Pos (26) /*!< SYS_T::GPKL_MFOS: GPIOyMFOS26 Position */ +#define SYS_GPKL_MFOS_GPIOyMFOS26_Msk (0x1ul << SYS_GPKL_MFOS_GPIOyMFOS26_Pos) /*!< SYS_T::GPKL_MFOS: GPIOyMFOS26 Mask */ + +#define SYS_GPKL_MFOS_GPIOyMFOS27_Pos (27) /*!< SYS_T::GPKL_MFOS: GPIOyMFOS27 Position */ +#define SYS_GPKL_MFOS_GPIOyMFOS27_Msk (0x1ul << SYS_GPKL_MFOS_GPIOyMFOS27_Pos) /*!< SYS_T::GPKL_MFOS: GPIOyMFOS27 Mask */ + +#define SYS_GPKL_MFOS_GPIOyMFOS28_Pos (28) /*!< SYS_T::GPKL_MFOS: GPIOyMFOS28 Position */ +#define SYS_GPKL_MFOS_GPIOyMFOS28_Msk (0x1ul << SYS_GPKL_MFOS_GPIOyMFOS28_Pos) /*!< SYS_T::GPKL_MFOS: GPIOyMFOS28 Mask */ + +#define SYS_GPKL_MFOS_GPIOyMFOS29_Pos (29) /*!< SYS_T::GPKL_MFOS: GPIOyMFOS29 Position */ +#define SYS_GPKL_MFOS_GPIOyMFOS29_Msk (0x1ul << SYS_GPKL_MFOS_GPIOyMFOS29_Pos) /*!< SYS_T::GPKL_MFOS: GPIOyMFOS29 Mask */ + +#define SYS_GPKL_MFOS_GPIOyMFOS30_Pos (30) /*!< SYS_T::GPKL_MFOS: GPIOyMFOS30 Position */ +#define SYS_GPKL_MFOS_GPIOyMFOS30_Msk (0x1ul << SYS_GPKL_MFOS_GPIOyMFOS30_Pos) /*!< SYS_T::GPKL_MFOS: GPIOyMFOS30 Mask */ + +#define SYS_GPKL_MFOS_GPIOyMFOS31_Pos (31) /*!< SYS_T::GPKL_MFOS: GPIOyMFOS31 Position */ +#define SYS_GPKL_MFOS_GPIOyMFOS31_Msk (0x1ul << SYS_GPKL_MFOS_GPIOyMFOS31_Pos) /*!< SYS_T::GPKL_MFOS: GPIOyMFOS31 Mask */ + +#define SYS_GPMN_MFOS_GPIOxMFOS0_Pos (0) /*!< SYS_T::GPMN_MFOS: GPIOxMFOS0 Position */ +#define SYS_GPMN_MFOS_GPIOxMFOS0_Msk (0x1ul << SYS_GPMN_MFOS_GPIOxMFOS0_Pos) /*!< SYS_T::GPMN_MFOS: GPIOxMFOS0 Mask */ + +#define SYS_GPMN_MFOS_GPIOxMFOS1_Pos (1) /*!< SYS_T::GPMN_MFOS: GPIOxMFOS1 Position */ +#define SYS_GPMN_MFOS_GPIOxMFOS1_Msk (0x1ul << SYS_GPMN_MFOS_GPIOxMFOS1_Pos) /*!< SYS_T::GPMN_MFOS: GPIOxMFOS1 Mask */ + +#define SYS_GPMN_MFOS_GPIOxMFOS2_Pos (2) /*!< SYS_T::GPMN_MFOS: GPIOxMFOS2 Position */ +#define SYS_GPMN_MFOS_GPIOxMFOS2_Msk (0x1ul << SYS_GPMN_MFOS_GPIOxMFOS2_Pos) /*!< SYS_T::GPMN_MFOS: GPIOxMFOS2 Mask */ + +#define SYS_GPMN_MFOS_GPIOxMFOS3_Pos (3) /*!< SYS_T::GPMN_MFOS: GPIOxMFOS3 Position */ +#define SYS_GPMN_MFOS_GPIOxMFOS3_Msk (0x1ul << SYS_GPMN_MFOS_GPIOxMFOS3_Pos) /*!< SYS_T::GPMN_MFOS: GPIOxMFOS3 Mask */ + +#define SYS_GPMN_MFOS_GPIOxMFOS4_Pos (4) /*!< SYS_T::GPMN_MFOS: GPIOxMFOS4 Position */ +#define SYS_GPMN_MFOS_GPIOxMFOS4_Msk (0x1ul << SYS_GPMN_MFOS_GPIOxMFOS4_Pos) /*!< SYS_T::GPMN_MFOS: GPIOxMFOS4 Mask */ + +#define SYS_GPMN_MFOS_GPIOxMFOS5_Pos (5) /*!< SYS_T::GPMN_MFOS: GPIOxMFOS5 Position */ +#define SYS_GPMN_MFOS_GPIOxMFOS5_Msk (0x1ul << SYS_GPMN_MFOS_GPIOxMFOS5_Pos) /*!< SYS_T::GPMN_MFOS: GPIOxMFOS5 Mask */ + +#define SYS_GPMN_MFOS_GPIOxMFOS6_Pos (6) /*!< SYS_T::GPMN_MFOS: GPIOxMFOS6 Position */ +#define SYS_GPMN_MFOS_GPIOxMFOS6_Msk (0x1ul << SYS_GPMN_MFOS_GPIOxMFOS6_Pos) /*!< SYS_T::GPMN_MFOS: GPIOxMFOS6 Mask */ + +#define SYS_GPMN_MFOS_GPIOxMFOS7_Pos (7) /*!< SYS_T::GPMN_MFOS: GPIOxMFOS7 Position */ +#define SYS_GPMN_MFOS_GPIOxMFOS7_Msk (0x1ul << SYS_GPMN_MFOS_GPIOxMFOS7_Pos) /*!< SYS_T::GPMN_MFOS: GPIOxMFOS7 Mask */ + +#define SYS_GPMN_MFOS_GPIOxMFOS8_Pos (8) /*!< SYS_T::GPMN_MFOS: GPIOxMFOS8 Position */ +#define SYS_GPMN_MFOS_GPIOxMFOS8_Msk (0x1ul << SYS_GPMN_MFOS_GPIOxMFOS8_Pos) /*!< SYS_T::GPMN_MFOS: GPIOxMFOS8 Mask */ + +#define SYS_GPMN_MFOS_GPIOxMFOS9_Pos (9) /*!< SYS_T::GPMN_MFOS: GPIOxMFOS9 Position */ +#define SYS_GPMN_MFOS_GPIOxMFOS9_Msk (0x1ul << SYS_GPMN_MFOS_GPIOxMFOS9_Pos) /*!< SYS_T::GPMN_MFOS: GPIOxMFOS9 Mask */ + +#define SYS_GPMN_MFOS_GPIOxMFOS10_Pos (10) /*!< SYS_T::GPMN_MFOS: GPIOxMFOS10 Position */ +#define SYS_GPMN_MFOS_GPIOxMFOS10_Msk (0x1ul << SYS_GPMN_MFOS_GPIOxMFOS10_Pos) /*!< SYS_T::GPMN_MFOS: GPIOxMFOS10 Mask */ + +#define SYS_GPMN_MFOS_GPIOxMFOS11_Pos (11) /*!< SYS_T::GPMN_MFOS: GPIOxMFOS11 Position */ +#define SYS_GPMN_MFOS_GPIOxMFOS11_Msk (0x1ul << SYS_GPMN_MFOS_GPIOxMFOS11_Pos) /*!< SYS_T::GPMN_MFOS: GPIOxMFOS11 Mask */ + +#define SYS_GPMN_MFOS_GPIOxMFOS12_Pos (12) /*!< SYS_T::GPMN_MFOS: GPIOxMFOS12 Position */ +#define SYS_GPMN_MFOS_GPIOxMFOS12_Msk (0x1ul << SYS_GPMN_MFOS_GPIOxMFOS12_Pos) /*!< SYS_T::GPMN_MFOS: GPIOxMFOS12 Mask */ + +#define SYS_GPMN_MFOS_GPIOxMFOS13_Pos (13) /*!< SYS_T::GPMN_MFOS: GPIOxMFOS13 Position */ +#define SYS_GPMN_MFOS_GPIOxMFOS13_Msk (0x1ul << SYS_GPMN_MFOS_GPIOxMFOS13_Pos) /*!< SYS_T::GPMN_MFOS: GPIOxMFOS13 Mask */ + +#define SYS_GPMN_MFOS_GPIOxMFOS14_Pos (14) /*!< SYS_T::GPMN_MFOS: GPIOxMFOS14 Position */ +#define SYS_GPMN_MFOS_GPIOxMFOS14_Msk (0x1ul << SYS_GPMN_MFOS_GPIOxMFOS14_Pos) /*!< SYS_T::GPMN_MFOS: GPIOxMFOS14 Mask */ + +#define SYS_GPMN_MFOS_GPIOxMFOS15_Pos (15) /*!< SYS_T::GPMN_MFOS: GPIOxMFOS15 Position */ +#define SYS_GPMN_MFOS_GPIOxMFOS15_Msk (0x1ul << SYS_GPMN_MFOS_GPIOxMFOS15_Pos) /*!< SYS_T::GPMN_MFOS: GPIOxMFOS15 Mask */ + +#define SYS_GPMN_MFOS_GPIOyMFOS16_Pos (16) /*!< SYS_T::GPMN_MFOS: GPIOyMFOS16 Position */ +#define SYS_GPMN_MFOS_GPIOyMFOS16_Msk (0x1ul << SYS_GPMN_MFOS_GPIOyMFOS16_Pos) /*!< SYS_T::GPMN_MFOS: GPIOyMFOS16 Mask */ + +#define SYS_GPMN_MFOS_GPIOyMFOS17_Pos (17) /*!< SYS_T::GPMN_MFOS: GPIOyMFOS17 Position */ +#define SYS_GPMN_MFOS_GPIOyMFOS17_Msk (0x1ul << SYS_GPMN_MFOS_GPIOyMFOS17_Pos) /*!< SYS_T::GPMN_MFOS: GPIOyMFOS17 Mask */ + +#define SYS_GPMN_MFOS_GPIOyMFOS18_Pos (18) /*!< SYS_T::GPMN_MFOS: GPIOyMFOS18 Position */ +#define SYS_GPMN_MFOS_GPIOyMFOS18_Msk (0x1ul << SYS_GPMN_MFOS_GPIOyMFOS18_Pos) /*!< SYS_T::GPMN_MFOS: GPIOyMFOS18 Mask */ + +#define SYS_GPMN_MFOS_GPIOyMFOS19_Pos (19) /*!< SYS_T::GPMN_MFOS: GPIOyMFOS19 Position */ +#define SYS_GPMN_MFOS_GPIOyMFOS19_Msk (0x1ul << SYS_GPMN_MFOS_GPIOyMFOS19_Pos) /*!< SYS_T::GPMN_MFOS: GPIOyMFOS19 Mask */ + +#define SYS_GPMN_MFOS_GPIOyMFOS20_Pos (20) /*!< SYS_T::GPMN_MFOS: GPIOyMFOS20 Position */ +#define SYS_GPMN_MFOS_GPIOyMFOS20_Msk (0x1ul << SYS_GPMN_MFOS_GPIOyMFOS20_Pos) /*!< SYS_T::GPMN_MFOS: GPIOyMFOS20 Mask */ + +#define SYS_GPMN_MFOS_GPIOyMFOS21_Pos (21) /*!< SYS_T::GPMN_MFOS: GPIOyMFOS21 Position */ +#define SYS_GPMN_MFOS_GPIOyMFOS21_Msk (0x1ul << SYS_GPMN_MFOS_GPIOyMFOS21_Pos) /*!< SYS_T::GPMN_MFOS: GPIOyMFOS21 Mask */ + +#define SYS_GPMN_MFOS_GPIOyMFOS22_Pos (22) /*!< SYS_T::GPMN_MFOS: GPIOyMFOS22 Position */ +#define SYS_GPMN_MFOS_GPIOyMFOS22_Msk (0x1ul << SYS_GPMN_MFOS_GPIOyMFOS22_Pos) /*!< SYS_T::GPMN_MFOS: GPIOyMFOS22 Mask */ + +#define SYS_GPMN_MFOS_GPIOyMFOS23_Pos (23) /*!< SYS_T::GPMN_MFOS: GPIOyMFOS23 Position */ +#define SYS_GPMN_MFOS_GPIOyMFOS23_Msk (0x1ul << SYS_GPMN_MFOS_GPIOyMFOS23_Pos) /*!< SYS_T::GPMN_MFOS: GPIOyMFOS23 Mask */ + +#define SYS_GPMN_MFOS_GPIOyMFOS24_Pos (24) /*!< SYS_T::GPMN_MFOS: GPIOyMFOS24 Position */ +#define SYS_GPMN_MFOS_GPIOyMFOS24_Msk (0x1ul << SYS_GPMN_MFOS_GPIOyMFOS24_Pos) /*!< SYS_T::GPMN_MFOS: GPIOyMFOS24 Mask */ + +#define SYS_GPMN_MFOS_GPIOyMFOS25_Pos (25) /*!< SYS_T::GPMN_MFOS: GPIOyMFOS25 Position */ +#define SYS_GPMN_MFOS_GPIOyMFOS25_Msk (0x1ul << SYS_GPMN_MFOS_GPIOyMFOS25_Pos) /*!< SYS_T::GPMN_MFOS: GPIOyMFOS25 Mask */ + +#define SYS_GPMN_MFOS_GPIOyMFOS26_Pos (26) /*!< SYS_T::GPMN_MFOS: GPIOyMFOS26 Position */ +#define SYS_GPMN_MFOS_GPIOyMFOS26_Msk (0x1ul << SYS_GPMN_MFOS_GPIOyMFOS26_Pos) /*!< SYS_T::GPMN_MFOS: GPIOyMFOS26 Mask */ + +#define SYS_GPMN_MFOS_GPIOyMFOS27_Pos (27) /*!< SYS_T::GPMN_MFOS: GPIOyMFOS27 Position */ +#define SYS_GPMN_MFOS_GPIOyMFOS27_Msk (0x1ul << SYS_GPMN_MFOS_GPIOyMFOS27_Pos) /*!< SYS_T::GPMN_MFOS: GPIOyMFOS27 Mask */ + +#define SYS_GPMN_MFOS_GPIOyMFOS28_Pos (28) /*!< SYS_T::GPMN_MFOS: GPIOyMFOS28 Position */ +#define SYS_GPMN_MFOS_GPIOyMFOS28_Msk (0x1ul << SYS_GPMN_MFOS_GPIOyMFOS28_Pos) /*!< SYS_T::GPMN_MFOS: GPIOyMFOS28 Mask */ + +#define SYS_GPMN_MFOS_GPIOyMFOS29_Pos (29) /*!< SYS_T::GPMN_MFOS: GPIOyMFOS29 Position */ +#define SYS_GPMN_MFOS_GPIOyMFOS29_Msk (0x1ul << SYS_GPMN_MFOS_GPIOyMFOS29_Pos) /*!< SYS_T::GPMN_MFOS: GPIOyMFOS29 Mask */ + +#define SYS_GPMN_MFOS_GPIOyMFOS30_Pos (30) /*!< SYS_T::GPMN_MFOS: GPIOyMFOS30 Position */ +#define SYS_GPMN_MFOS_GPIOyMFOS30_Msk (0x1ul << SYS_GPMN_MFOS_GPIOyMFOS30_Pos) /*!< SYS_T::GPMN_MFOS: GPIOyMFOS30 Mask */ + +#define SYS_GPMN_MFOS_GPIOyMFOS31_Pos (31) /*!< SYS_T::GPMN_MFOS: GPIOyMFOS31 Position */ +#define SYS_GPMN_MFOS_GPIOyMFOS31_Msk (0x1ul << SYS_GPMN_MFOS_GPIOyMFOS31_Pos) /*!< SYS_T::GPMN_MFOS: GPIOyMFOS31 Mask */ + +#define SYS_UID0_UID_Pos (0) /*!< SYS_T::UID0: UID Position */ +#define SYS_UID0_UID_Msk (0xfffffffful << SYS_UID0_UID_Pos) /*!< SYS_T::UID0: UID Mask */ + +#define SYS_UID1_UID_Pos (0) /*!< SYS_T::UID1: UID Position */ +#define SYS_UID1_UID_Msk (0xfffffffful << SYS_UID1_UID_Pos) /*!< SYS_T::UID1: UID Mask */ + +#define SYS_UID2_UID_Pos (0) /*!< SYS_T::UID2: UID Position */ +#define SYS_UID2_UID_Msk (0xfffffffful << SYS_UID2_UID_Pos) /*!< SYS_T::UID2: UID Mask */ + +#define SYS_UCID0_UCID_Pos (0) /*!< SYS_T::UCID0: UCID Position */ +#define SYS_UCID0_UCID_Msk (0xfffffffful << SYS_UCID0_UCID_Pos) /*!< SYS_T::UCID0: UCID Mask */ + +#define SYS_UCID1_UCID_Pos (0) /*!< SYS_T::UCID1: UCID Position */ +#define SYS_UCID1_UCID_Msk (0xfffffffful << SYS_UCID1_UCID_Pos) /*!< SYS_T::UCID1: UCID Mask */ + +#define SYS_UCID2_UCID_Pos (0) /*!< SYS_T::UCID2: UCID Position */ +#define SYS_UCID2_UCID_Msk (0xfffffffful << SYS_UCID2_UCID_Pos) /*!< SYS_T::UCID2: UCID Mask */ + +#define SYS_RLKTZS_REGLCTL_Pos (0) /*!< SYS_T::RLKTZS: REGLCTL Position */ +#define SYS_RLKTZS_REGLCTL_Msk (0xfful << SYS_RLKTZS_REGLCTL_Pos) /*!< SYS_T::RLKTZS: REGLCTL Mask */ + +#define SYS_RLKTZNS_REGLCTL_Pos (0) /*!< SYS_T::RLKTZNS: REGLCTL Position */ +#define SYS_RLKTZNS_REGLCTL_Msk (0xfful << SYS_RLKTZNS_REGLCTL_Pos) /*!< SYS_T::RLKTZNS: REGLCTL Mask */ + +#define SYS_RLKSUBM_REGLCTL_Pos (0) /*!< SYS_T::RLKSUBM: REGLCTL Position */ +#define SYS_RLKSUBM_REGLCTL_Msk (0xfful << SYS_RLKSUBM_REGLCTL_Pos) + +/**@}*/ /* SYS_CONST */ +/**@}*/ /* end of SYS register group */ +/**@}*/ /* end of REGISTER group */ + +#if defined ( __CC_ARM ) + #pragma no_anon_unions +#endif + +#endif /* __SYS_REG_H__ */ diff --git a/bsp/nuvoton/libraries/ma35/Device/Nuvoton/MA35D1/Include/system_ma35d1.h b/bsp/nuvoton/libraries/ma35/Device/Nuvoton/MA35D1/Include/system_ma35d1.h new file mode 100644 index 0000000000..5891fad76f --- /dev/null +++ b/bsp/nuvoton/libraries/ma35/Device/Nuvoton/MA35D1/Include/system_ma35d1.h @@ -0,0 +1,65 @@ +/**************************************************************************//** + * @file system_ma35d1_rtp.h + * @brief CMSIS Cortex-M4 Core Peripheral Access Layer Header File + * + * SPDX-License-Identifier: Apache-2.0 + * @copyright (C) 2020 Nuvoton Technology Corp. All rights reserved. + *****************************************************************************/ + +#ifndef __SYSTEM_MA35D1_RTP_H__ +#define __SYSTEM_MA35D1_RTP_H__ + +#ifdef __cplusplus +extern "C" { +#endif + +#include + + +/*---------------------------------------------------------------------------- + Define clocks + *----------------------------------------------------------------------------*/ + +#define __HSI (24000000UL) /*!< PLL default output is 50MHz */ +#define __HXT (24000000UL) /*!< External Crystal Clock Frequency */ +#define __LXT (32768UL) /*!< External Crystal Clock Frequency 32.768KHz */ +#define __HIRC (12000000UL) /*!< Internal 12M RC Oscillator Frequency */ +#define __LIRC (30000UL) /*!< Internal 10K RC Oscillator Frequency */ +#define __SYS_OSC_CLK ( ___HSI) /* Main oscillator frequency */ + + +#define __SYSTEM_CLOCK (1UL*__HXT) + +extern uint32_t SystemCoreClock; /*!< System Clock Frequency (Core Clock) */ +extern uint32_t CyclesPerUs; /*!< Cycles per micro second */ +extern uint32_t PllClock; /*!< PLL Output Clock Frequency */ + + +/** + * Initialize the system + * + * @param none + * @return none + * + * @brief Setup the micro controller system. + * Initialize the System and update the SystemCoreClock variable. + */ +extern void SystemInit(void); + +/** + * Update SystemCoreClock variable + * + * @param none + * @return none + * + * @brief Updates the SystemCoreClock with current core Clock + * retrieved from cpu registers. + */ +extern void SystemCoreClockUpdate(void); + +#ifdef __cplusplus +} +#endif + +#endif /* __SYSTEM_MA35D1_RTP_H__ */ + diff --git a/bsp/nuvoton/libraries/ma35/Device/Nuvoton/MA35D1/Include/timer_reg.h b/bsp/nuvoton/libraries/ma35/Device/Nuvoton/MA35D1/Include/timer_reg.h new file mode 100644 index 0000000000..a401e163f6 --- /dev/null +++ b/bsp/nuvoton/libraries/ma35/Device/Nuvoton/MA35D1/Include/timer_reg.h @@ -0,0 +1,1069 @@ +/**************************************************************************//** + * @file timer_reg.h + * @brief TIMER register definition header file + * + * SPDX-License-Identifier: Apache-2.0 + * @copyright (C) 2020 Nuvoton Technology Corp. All rights reserved. + *****************************************************************************/ +#ifndef __TIMER_REG_H__ +#define __TIMER_REG_H__ + +#if defined ( __CC_ARM ) + #pragma anon_unions +#endif + +/** + @addtogroup REGISTER Control Register + @{ +*/ + +/** + @addtogroup TIMER Timer Controller(TIMER) + Memory Mapped Structure for TIMER Controller +@{ */ + +typedef struct +{ + + + /** + * @var TIMER_T::CTL + * Offset: 0x00 Timer Control Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[7:0] |PSC |Prescale Counter + * | | |Timer input clock or event source is divided by (PSC+1) before it is fed to the timer up counter + * | | |If this field is 0 (PSC = 0), then there is no scaling. + * | | |Note: Update prescale counter value will reset internal 8-bit prescale counter and 24-bit up counter value. + * |[19] |INTRGEN |Inter-timer Trigger Mode Enable Bit + * | | |Setting this bit will enable the inter-timer trigger capture function. + * | | |The Timer0/2/4/6/8/10 will be in event counter mode and counting with external clock source or event + * | | |Also, Timer1/3/5/7/9/11 will be in trigger-counting mode of capture function. + * | | |0 = Inter-Timer Trigger Capture mode Disabled. + * | | |1 = Inter-Timer Trigger Capture mode Enabled. + * | | |Note: For Timer1/3/5/7/9/11, this bit is ignored and the read back value is always 0. + * |[20] |PERIOSEL |Periodic Mode Behavior Selection Enable Bit + * | | |0 = The behavior selection in periodic mode is Disabled. + * | | |When user updates CMPDAT while timer is running in periodic mode, + * | | |CNT will be reset to default value. + * | | |1 = The behavior selection in periodic mode is Enabled. + * | | |When user update CMPDAT while timer is running in periodic mode, the limitations as bellows list, + * | | |If updated CMPDAT value > CNT, CMPDAT will be updated and CNT keep running continually. + * | | |If updated CMPDAT value = CNT, timer time-out interrupt will be asserted immediately. + * | | |If updated CMPDAT value < CNT, CNT will be reset to default value. + * |[21] |TGLPINSEL |Toggle-output Pin Select + * | | |0 = Toggle mode output to TMx (Timer Event Counter Pin). + * | | |1 = Toggle mode output to TMx_EXT (Timer External Capture Pin). + * |[22] |CAPSRC |Capture Pin Source Selection + * | | |0 = Capture Function source is from TMx_EXT (x= 0~11) pin. + * | | |1 = Capture Function source is from internal clock source (HIRC 12M, LIRC) or external clock (HXT, LXT). + * | | |Note: When CAPSRC = 1, user can set ICAPSSEL (TIMERx_EXTCTL[10:8]) to decide which clock is as timer capture source. + * |[23] |WKEN |Wake-up Function Enable Bit + * | | |If this bit is set to 1, while timer interrupt flag TIF (TIMERx_INTSTS[0]) is 1 and INTEN (TIMERx_CTL[29]) is enabled, the timer interrupt signal will generate a wake-up trigger event to CPU. + * | | |0 = Wake-up function Disabled if timer interrupt signal generated. + * | | |1 = Wake-up function Enabled if timer interrupt signal generated. + * |[24] |EXTCNTEN |Event Counter Mode Enable Bit + * | | |This bit is for external counting pin function enabled. + * | | |0 = Event counter mode Disabled. + * | | |1 = Event counter mode Enabled. + * | | |Note: When timer is used as an event counter, this bit should be set to 1 and select PCLK as timer clock source. + * |[25] |ACTSTS |Timer Active Status Bit (Read Only) + * | | |This bit indicates the 24-bit up counter status. + * | | |0 = 24-bit up counter is not active. + * | | |1 = 24-bit up counter is active. + * | | |Note: This bit may active when CNT 0 transition to CNT 1. + * |[28:27] |OPMODE |Timer Counting Mode Select + * | | |00 = The Timer controller is operated in One-shot mode. + * | | |01 = The Timer controller is operated in Periodic mode. + * | | |10 = The Timer controller is operated in Toggle-output mode. + * | | |11 = The Timer controller is operated in Continuous Counting mode. + * |[29] |INTEN |Timer Interrupt Enable Bit + * | | |0 = Timer time-out interrupt Disabled. + * | | |1 = Timer time-out interrupt Enabled. + * | | |Note: If this bit is enabled, when the timer time-out interrupt flag TIF is set to 1, the timer interrupt signal is generated and inform to CPU. + * |[30] |CNTEN |Timer Counting Enable Bit + * | | |0 = Stops/Suspends counting. + * | | |1 = Starts counting. + * | | |Note 1: In stop status, and then set CNTEN to 1 will enable the 24-bit up counter to keep counting from the last stop counting value. + * | | |Note 2: This bit is auto-cleared by hardware in one-shot mode (TIMER_CTL[28:27] = 00) when the timer time-out interrupt flag TIF (TIMERx_INTSTS[0]) is generated. + * | | |Note 3: Set enable/disable this bit needs 2 * TMR_CLK period to become active, user can read ACTSTS (TIMERx_CTL[25]) to check enable/disable command is completed or not. + * |[31] |ICEDEBUG |ICE Debug Mode Acknowledge Disable Bit (Write Protect) + * | | |0 = ICE debug mode acknowledgement effects TIMER counting. + * | | |TIMER counter will be held while CPU is held by ICE. + * | | |1 = ICE debug mode acknowledgement Disabled. + * | | |TIMER counter will keep going no matter CPU is held by ICE or not. + * | | |Note: This bit is write protected + * | | |Refer to the SYS_RLKTZS register or SYS_RLKTZNS register or SYS_RLKSUBM register. + * @var TIMER_T::CMP + * Offset: 0x04 Timer Comparator Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[23:0] |CMPDAT |Timer Comparator Value + * | | |CMPDAT is a 24-bit compared value register + * | | |When the internal 24-bit up counter value is equal to CMPDAT value, the TIF (TIMERx_INTSTS[0] Timer Interrupt Flag) will set to 1. + * | | |Time-out period = (Period of timer clock input) * (8-bit PSC + 1) * (24-bit CMPDAT). + * | | |Note 1: Never write 0x0 or 0x1 in CMPDAT field, or the core will run into unknown state. + * | | |Note 2: When timer is operating at continuous counting mode, the 24-bit up counter will keep counting continuously even if user writes a new value into CMPDAT field + * | | |But if timer is operating at other modes, the 24-bit up counter will restart counting from 0 and using newest CMPDAT value to be the timer compared value while user writes a new value into CMPDAT field. + * @var TIMER_T::INTSTS + * Offset: 0x08 Timer Interrupt Status Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[0] |TIF |Timer Interrupt Flag + * | | |This bit indicates the interrupt flag status of Timer while 24-bit timer up counter CNT (TIMERx_CNT[23:0]) value reaches to CMPDAT (TIMERx_CMP[23:0]) value. + * | | |0 = No effect. + * | | |1 = CNT value matches the CMPDAT value. + * | | |Note: This bit is cleared by writing 1 to it. + * |[1] |TWKF |Timer Wake-up Flag + * | | |This bit indicates the interrupt wake-up flag status of timer. + * | | |0 = Timer does not cause CPU wake-up. + * | | |1 = CPU wake-up from Idle or Power-down mode if timer time-out interrupt signal generated. + * | | |Note: This bit is cleared by writing 1 to it. + * @var TIMER_T::CNT + * Offset: 0x0C Timer Data Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[23:0] |CNT |Timer Data Register + * | | |Read operation. + * | | |Read this register to get CNT value. For example: + * | | |If EXTCNTEN (TIMERx_CTL[24]) is 0, user can read CNT value for getting current 24-bit counter value. + * | | |If EXTCNTEN (TIMERx_CTL[24]) is 1, user can read CNT value for getting current 24-bit event input counter value. + * | | |Write operation. + * | | |Writing any value to this register will reset current CNT value to 0 and reload internal 8-bit prescale counter. + * |[31] |RSTACT |Timer Data Register Reset Active (Read Only) + * | | |This bit indicates if the counter reset operation active. + * | | |When user writes this CNT register, timer starts to reset its internal 24-bit timer up-counter to 0 and reload 8-bit pre-scale counter + * | | |At the same time, timer set this flag to 1 to indicate the counter reset operation is in progress + * | | |Once the counter reset operation done, timer clear this bit to 0 automatically. + * | | |0 = Reset operation is done. + * | | |1 = Reset operation triggered by writing TIMERx_CNT is in progress. + * @var TIMER_T::CAP + * Offset: 0x10 Timer Capture Data Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[23:0] |CAPDAT |Timer Capture Data Register + * | | |When CAPEN (TIMERx_EXTCTL[3]) bit is set, CAPFUNCS (TIMERx_EXTCTL[4]) bit is 0, and a transition on TMx_EXT pin matched the CAPEDGE (TIMERx_EXTCTL[14:12]) setting, CAPIF (TIMERx_EINTSTS[0]) will set to 1 and the current timer counter value CNT (TIMERx_CNT[23:0]) will be auto-loaded into this CAPDAT field. + * @var TIMER_T::EXTCTL + * Offset: 0x14 Timer External Control Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[0] |CNTPHASE |Timer External Count Phase + * | | |This bit indicates the detection phase of external counting pin TMx (x= 0~11). + * | | |0 = A falling edge of external counting pin will be counted. + * | | |1 = A rising edge of external counting pin will be counted. + * |[3] |CAPEN |Timer External Capture Pin Enable Bit + * | | |This bit enables the TMx_EXT capture pin input function. + * | | |0 =TMx_EXT (x= 0~11) pin Disabled. + * | | |1 =TMx_EXT (x= 0~11) pin Enabled. + * |[4] |CAPFUNCS |Capture Function Selection + * | | |0 = External Capture Mode Enabled. + * | | |1 = External Reset Mode Enabled. + * | | |Note 1: When CAPFUNCS is 0, transition on TMx_EXT (x= 0~11) pin is using to save current 24-bit timer counter value (CNT value) to CAPDAT field. + * | | |Note 2: When CAPFUNCS is 1, transition on TMx_EXT (x= 0~11) pin is using to save current 24-bit timer counter value (CNT value) to CAPDAT field then CNT value will be reset immediately. + * |[5] |CAPIEN |Timer External Capture Interrupt Enable Bit + * | | |0 = TMx_EXT (x= 0~11) pin detection Interrupt Disabled. + * | | |1 = TMx_EXT (x= 0~11) pin detection Interrupt Enabled. + * | | |Note: CAPIEN is used to enable timer external interrupt + * | | |If CAPIEN enabled, timer will rise an interrupt when CAPIF (TIMERx_EINTSTS[0]) is 1. + * | | |For example, while CAPIEN = 1, CAPEN = 1, and CAPEDGE = 00, a 1 to 0 transition on the TMx_EXT pin will cause the CAPIF to be set then the interrupt signal is generated and sent to NVIC to inform CPU. + * |[6] |CAPDBEN |Timer External Capture Pin De-bounce Enable Bit + * | | |0 = TMx_EXT (x= 0~11) pin de-bounce Disabled. + * | | |1 = TMx_EXT (x= 0~11) pin de-bounce Enabled. + * | | |Note: If this bit is enabled, the edge detection of TMx_EXT pin is detected with de-bounce circuit. + * |[7] |CNTDBEN |Timer Counter Pin De-bounce Enable Bit + * | | |0 = TMx (x= 0~11) pin de-bounce Disabled. + * | | |1 = TMx (x= 0~11) pin de-bounce Enabled. + * | | |Note: If this bit is enabled, the edge detection of TMx pin is detected with de-bounce circuit. + * |[10:8] |ICAPSSEL |Internal Capture Source Selection + * | | |010 = Capture Function source is from HXT. + * | | |011 = Capture Function source is from LXT. + * | | |100 = Capture Function source is from HIRC. + * | | |101 = Capture Function source is from LIRC. + * | | |110 = Reserved. + * | | |111 = Reserved. + * | | |Note: these bits only available when CAPSRC (TIMERx_CTL[22]) is 1. + * |[14:12] |CAPEDGE |Timer External Capture Pin Edge Detect + * | | |When first capture event is generated, the CNT (TIMERx_CNT[23:0]) will be reset to 0 and first CAPDAT (TIMERx_CAP[23:0]) should be to 0. + * | | |000 = Capture event occurred when detect falling edge transfer on TMx_EXT (x= 0~11) pin. + * | | |001 = Capture event occurred when detect rising edge transfer on TMx_EXT (x= 0~11) pin. + * | | |010 = Capture event occurred when detect both falling and rising edge transfer on TMx_EXT (x= 0~11) pin, and first capture event occurred at falling edge transfer. + * | | |011 = Capture event occurred when detect both rising and falling edge transfer on TMx_EXT (x= 0~11) pin, and first capture event occurred at rising edge transfer. + * | | |110 = First capture event occurred at falling edge, follows capture events are at rising edge transfer on TMx_EXT (x= 0~11) pin. + * | | |111 = First capture event occurred at rising edge, follows capture events are at falling edge transfer on TMx_EXT (x= 0~11) pin. + * | | |100, 101 = Reserved. + * |[16] |ECNTSSEL |Event Counter Source Selection to Trigger Event Counter Function + * | | |0 = Event Counter input source is from TMx (x= 0~11) pin. + * |[31:28] |CAPSDIV |Timer Capture Source Divider + * | | |This bits indicate the divide scale for capture source. + * | | |0000 = Capture source/1. + * | | |0001 = Capture source/2. + * | | |0010 = Capture source/4. + * | | |0011 = Capture source/8. + * | | |0100 = Capture source/16. + * | | |0101 = Capture source/32. + * | | |0110 = Capture source/64. + * | | |0111 = Capture source/128. + * | | |1000 = Capture source/256. + * | | |1001~1111 = Reserved. + * | | |Note: Sets ICAPSSEL (TIMERx_EXTCTL[10:8]) and CAPSRC (TIMERx_CTL[22]) to select capture source. + * @var TIMER_T::EINTSTS + * Offset: 0x18 Timer External Interrupt Status Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[0] |CAPIF |Timer External Capture Interrupt Flag + * | | |This bit indicates the timer external capture interrupt flag status. + * | | |0 = TMx_EXT (x= 0~11) pin interrupt did not occur. + * | | |1 = TMx_EXT (x= 0~11) pin interrupt occurred. + * | | |Note 1: This bit is cleared by writing 1 to it. + * | | |Note 2: When CAPEN (TIMERx_EXTCTL[3]) bit is set, CAPFUNCS (TIMERx_EXTCTL[4]) bit is 0, and a transition on TMx_EXT (x= 0~11) pin matched the CAPEDGE (TIMERx_EXTCTL[2:1]) setting, this bit will set to 1 by hardware. + * | | |Note 3: There is a new incoming capture event detected before CPU clearing the CAPIF status + * | | |If the above condition occurred, the Timer will keep register TIMERx_CAP unchanged and drop the new capture value. + * @var TIMER_T::TRGCTL + * Offset: 0x1C Timer Trigger Control Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[0] |TRGSSEL |Trigger Source Select Bit + * | | |This bit is used to select internal trigger source is form timer time-out interrupt signal or capture interrupt signal. + * | | |0 = Time-out interrupt signal is used to internal trigger EPWM, BPWM, PDMA and ADC. + * | | |1 = Capture interrupt signal is used to internal trigger EPWM, BPWM, PDMA and ADC. + * |[1] |TRGPWM |Trigger EPWM and BPWM Enable Bit + * | | |If this bit is set to 1, each timer time-out event or capture event can be as EPWM and BPWM counter clock source. + * | | |0 = Timer interrupt trigger EPWM and BPWM Disabled. + * | | |1 = Timer interrupt trigger EPWM and BPWM Enabled. + * | | |Note: If TRGSSEL (TIMERx_TRGCTL[0]) = 0, time-out interrupt signal as EPWM and BPWM counter clock source. + * | | |If TRGSSEL (TIMERx_TRGCTL[0]) = 1, capture interrupt signal as EPWM and BPWM counter clock source. + * |[2] |TRGEADC |Trigger EADC Enable Bit + * | | |If this bit is set to 1, each timer time-out event or capture event can be triggered EADC conversion. + * | | |0 = Timer interrupt trigger EADC Disabled. + * | | |1 = Timer interrupt trigger EADC Enabled. + * | | |Note: If TRGSSEL (TIMERx_TRGCTL[0]) = 0, time-out interrupt signal will trigger EADC conversion. + * | | |If TRGSSEL (TIMERx_TRGCTL[0]) = 1, capture interrupt signal will trigger EADC conversion. + * |[4] |TRGPDMA |Trigger PDMA Enable Bit + * | | |If this bit is set to 1, each timer time-out event or capture event can be triggered PDMA transfer. + * | | |0 = Timer interrupt trigger PDMA Disabled. + * | | |1 = Timer interrupt trigger PDMA Enabled. + * | | |Note: If TRGSSEL (TIMERx_TRGCTL[0]) = 0, time-out interrupt signal will trigger PDMA transfer. + * | | |If TRGSSEL (TIMERx_TRGCTL[0]) = 1, capture interrupt signal will trigger PDMA transfer. + * @var TIMER_T::ALTCTL + * Offset: 0x20 Timer Alternative Control Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[0] |FUNCSEL |Function Selection + * | | |0 = Timer controller is used as timer function. + * | | |1 = Timer controller is used as PWM function. + * | | |Note: When timer is used as PWM, the clock source of time controller will be forced to PCLKx automatically. + * @var TIMER_T::PWMCTL + * Offset: 0x40 Timer PWM Control Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[0] |CNTEN |PWM Counter Enable Bit + * | | |0 = PWM counter and clock prescale Stop Running. + * | | |1 = PWM counter and clock prescale Start Running. + * |[2:1] |CNTTYPE |PWM Counter Behavior Type + * | | |00 = Up count type. + * | | |01 = Down count type. + * | | |10 = Up-down count type. + * | | |11 = Reserved. + * |[3] |CNTMODE |PWM Counter Mode + * | | |0 = Auto-reload mode. + * | | |1 = One-shot mode. + * |[8] |CTRLD |Center Re-load + * | | |In up-down count type, PERIOD will load to PBUF when current PWM period is completed always and CMP will load to CMPBUF at the center point of current period. + * |[9] |IMMLDEN |Immediately Load Enable Bit + * | | |0 = PERIOD will load to PBUF when current PWM period is completed no matter CTRLD is enabled/disabled + * | | |If CTRLD is disabled, CMP will load to CMPBUF when current PWM period is completed; if CTRLD is enabled in up-down count type, CMP will load to CMPBUF at the center point of current period. + * | | |1 = PERIOD/CMP will load to PBUF/CMPBUF immediately when user update PERIOD/CMP. + * | | |Note: If IMMLDEN is enabled, CTRLD will be invalid. + * |[16] |OUTMODE |PWM Output Mode + * | | |This bit controls the output mode of corresponding PWM channel. + * | | |0 = PWM independent mode. + * | | |1 = PWM complementary mode. + * |[30] |DBGHALT |ICE Debug Mode Counter Halt (Write Protect) + * | | |If debug mode counter halt is enabled, PWM counter will keep current value until exit ICE debug mode. + * | | |0 = ICE debug mode counter halt disable. + * | | |1 = ICE debug mode counter halt enable. + * | | |Note: This bit is write protected. Refer to SYS_RLKTZS or SYS_RLKTZND or SYS_RLKSUBM register. + * |[31] |DBGTRIOFF |ICE Debug Mode Acknowledge Disable Bit (Write Protect) + * | | |0 = ICE debug mode acknowledgement effects PWM output. + * | | |PWM output pin will be forced as tri-state while ICE debug mode acknowledged. + * | | |1 = ICE debug mode acknowledgement disabled. + * | | |PWM output pin will keep output no matter ICE debug mode acknowledged or not. + * | | |Note: This bit is write protected + * | | |Refer to the SYS_RLKTZS register or SYS_RLKTZNS register or SYS_RLKSUBM register + * @var TIMER_T::PWMCLKSRC + * Offset: 0x44 Timer PWM Counter Clock Source Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[3:0] |CLKSRC |PWM Counter Clock Source Select + * | | |The PWM counter clock source can be selected from TMRx_CLK or internal timer time-out or capture event. + * | | |0000 = TMRx_CLK. + * | | |0001 = Internal TIMER0 time-out or capture event. + * | | |0010 = Internal TIMER1 time-out or capture event. + * | | |0011 = Internal TIMER2 time-out or capture event. + * | | |0100 = Internal TIMER3 time-out or capture event. + * | | |0101 = Internal TIMER4 time-out or capture event. + * | | |0110 = Internal TIMER5 time-out or capture event. + * | | |0111 = Internal TIMER6 time-out or capture event. + * | | |1000 = Internal TIMER7 time-out or capture event. + * | | |1001 = Internal TIMER8 time-out or capture event. + * | | |1010 = Internal TIMER9 time-out or capture event. + * | | |1011 = Internal TIMER10 time-out or capture event. + * | | |1100 = Internal TIMER11 time-out or capture event. + * | | |Others = Reserved. + * | | |Note: If TIMER0 PWM function is enabled, the PWM counter clock source can be selected from TMR0_CLK, TIMER1 interrupt events, TIMER2 interrupt events, or TIMER3 interrupt events. + * @var TIMER_T::PWMCLKPSC + * Offset: 0x48 Timer PWM Counter Clock Pre-scale Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[11:0] |CLKPSC |PWM Counter Clock Pre-scale + * | | |The active clock of PWM counter is decided by counter clock prescale and divided by (CLKPSC + 1) + * | | |If CLKPSC is 0, then there is no scaling in PWM counter clock source. + * @var TIMER_T::PWMCNTCLR + * Offset: 0x4C Timer PWM Clear Counter Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[0] |CNTCLR |Clear PWM Counter Control Bit + * | | |It is automatically cleared by hardware. + * | | |0 = No effect. + * | | |1 = Clear 16-bit PWM counter to 0x10000 in up and up-down count type and reset counter value to PERIOD in down count type. + * @var TIMER_T::PWMPERIOD + * Offset: 0x50 Timer PWM Period Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[15:0] |PERIOD |PWM Period Register + * | | |In up count type: PWM counter counts from 0 to PERIOD, and restarts from 0. + * | | |In down count type: PWM counter counts from PERIOD to 0, and restarts from PERIOD. + * | | |In up-down count type: PWM counter counts from 0 to PERIOD, then decrements to 0 and repeats again. + * | | |In up and down count type: + * | | |PWM period time = (PERIOD + 1) * (CLKPSC + 1) * TMRx_PWMCLK. + * | | |In up-down count type: + * | | |PWM period time = 2 * PERIOD * (CLKPSC+ 1) * TMRx_PWMCLK. + * | | |Note: User should take care DIRF (TIMERx_PWMCNT[16]) bit in up/down/up-down count type to monitor current counter direction in each count type. + * @var TIMER_T::PWMCMPDAT + * Offset: 0x54 Timer PWM Comparator Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[15:0] |CMP |PWM Comparator Register + * | | |PWM CMP is used to compare with PWM CNT to generate PWM output waveform, interrupt events and trigger ADC to start conversion. + * @var TIMER_T::PWMDTCTL + * Offset: 0x58 Timer PWM Dead-time Control Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[11:0] |DTCNT |Dead-time Counter (Write Protect) + * | | |The dead-time can be calculated from the following two formulas: + * | | |Dead-time = (DTCNT[11:0] + 1) * TMRx_PWMCLK, if DTCKSEL is 0. + * | | |Dead-time = (DTCNT[11:0] + 1) * TMRx_PWMCLK * (CLKPSC + 1), if DTCKSEL is 1. + * | | |Note: This bit is write protected + * | | |Refer to the SYS_RLKTZS register or SYS_RLKTZNS register or SYS_RLKSUBM register + * |[16] |DTEN |Enable Dead-time Insertion for PWMx_CH0 and PWMx_CH1 (Write Protect) + * | | |Dead-time insertion function is only active when PWM complementary mode is enabled + * | | |If dead- time insertion is inactive, the outputs of PWMx_CH0 and PWMx_CH1 are complementary without any delay. + * | | |0 = Dead-time insertion Disabled on the pin pair. + * | | |1 = Dead-time insertion Enabled on the pin pair. + * | | |Note: This bit is write protected + * | | |Refer to the SYS_RLKTZS register or SYS_RLKTZNS register or SYS_RLKSUBM register + * |[24] |DTCKSEL |Dead-time Clock Select (Write Protect) + * | | |0 = Dead-time clock source from TMRx_PWMCLK without counter clock prescale. + * | | |1 = Dead-time clock source from TMRx_PWMCLK with counter clock prescale. + * | | |Note: This bit is write protected + * | | |Refer to the SYS_RLKTZS register or SYS_RLKTZNS register or SYS_RLKSUBM register + * @var TIMER_T::PWMCNT + * Offset: 0x5C Timer PWM Counter Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[15:0] |CNT |PWM Counter Value Register (Read Only) + * | | |User can monitor CNT to know the current counter value in 16-bit period counter. + * |[16] |DIRF |PWM Counter Direction Indicator Flag (Read Only) + * | | |0 = Counter is active in down count. + * | | |1 = Counter is active up count. + * @var TIMER_T::PWMMSKEN + * Offset: 0x60 Timer PWM Output Mask Enable Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[0] |MSKEN0 |PWMx_CH0 Output Mask Enable Bit + * | | |The PWMx_CH0 output signal will be masked when this bit is enabled + * | | |The PWMx_CH0 will output MSKDAT0 (TIMER_PWMMSK[0]) data. + * | | |0 = PWMx_CH0 output signal is non-masked. + * | | |1 = PWMx_CH0 output signal is masked and output MSKDAT0 data. + * |[1] |MSKEN1 |PWMx_CH1 Output Mask Enable Bit + * | | |The PWMx_CH1 output signal will be masked when this bit is enabled + * | | |The PWMx_CH1 will output MSKDAT1 (TIMER_PWMMSK[1]) data. + * | | |0 = PWMx_CH1 output signal is non-masked. + * | | |1 = PWMx_CH1 output signal is masked and output MSKDAT1 data. + * @var TIMER_T::PWMMSK + * Offset: 0x64 Timer PWM Output Mask Data Control Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[0] |MSKDAT0 |PWMx_CH0 Output Mask Data Control Bit + * | | |This bit is used to control the output state of PWMx_CH0 pin when PWMx_CH0 output mask function is enabled (MSKEN0 = 1). + * | | |0 = Output logic Low to PWMx_CH0. + * | | |1 = Output logic High to PWMx_CH0. + * |[1] |MSKDAT1 |PWMx_CH1 Output Mask Data Control Bit + * | | |This bit is used to control the output state of PWMx_CH1 pin when PWMx_CH1 output mask function is enabled (MSKEN1 = 1). + * | | |0 = Output logic Low to PWMx_CH1. + * | | |1 = Output logic High to PWMx_CH1. + * @var TIMER_T::PWMBNF + * Offset: 0x68 Timer PWM Brake Pin Noise Filter Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[0] |BRKNFEN |Brake Pin Noise Filter Enable Bit + * | | |0 = Pin noise filter detect of PWMx_BRAKEy Disabled. + * | | |1 = Pin noise filter detect of PWMx_BRAKEy Enabled. + * |[3:1] |BRKNFSEL |Brake Pin Noise Filter Clock Selection + * | | |000 = Noise filter clock is PCLKx. + * | | |001 = Noise filter clock is PCLKx/2. + * | | |010 = Noise filter clock is PCLKx/4. + * | | |011 = Noise filter clock is PCLKx/8. + * | | |100 = Noise filter clock is PCLKx/16. + * | | |101 = Noise filter clock is PCLKx/32. + * | | |110 = Noise filter clock is PCLKx/64. + * | | |111 = Noise filter clock is PCLKx/128. + * |[6:4] |BRKFCNT |Brake Pin Noise Filter Count + * | | |The fields is used to control the active noise filter sample time. + * | | |Once noise filter sample time = (Period time of BRKDBCS) * BRKFCNT. + * |[7] |BRKPINV |Brake Pin Detection Control Bit + * | | |0 = Brake pin event will be detected if PWMx_BRAKEy pin status transfer from low to high in edge-detect, or pin status is high in level-detect. + * | | |1 = Brake pin event will be detected if PWMx_BRAKEy pin status transfer from high to low in edge-detect, or pin status is low in level-detect . + * |[18:16] |BKPINSRC |Brake Pin Source Select + * | | |000 = Brake pin source comes from PWM0_BRAKE0 pin. + * | | |001 = Brake pin source comes from PWM0_BRAKE1 pin. + * | | |010 = Brake pin source comes from PWM1_BRAKE0 pin. + * | | |011 = Brake pin source comes from PWM1_BRAKE1 pin. + * | | |100 = Brake pin source comes from PWM2_BRAKE0 pin. + * | | |101 = Brake pin source comes from PWM2_BRAKE1 pin. + * @var TIMER_T::PWMFAILBRK + * Offset: 0x6C Timer PWM System Fail Brake Control Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[0] |CSSBRKEN |Clock Security System Detection Trigger PWM Brake Function Enable Bit + * | | |0 = Brake Function triggered by clock fail detection Disabled. + * | | |1 = Brake Function triggered by clock fail detection Enabled. + * |[1] |LVDBRKEN |Low Voltage Interrupt Flag Detection Trigger PWM Brake Function Enable Bit + * | | |0 = Brake Function triggered by LVD interrupt flag event Disabled. + * | | |1 = Brake Function triggered by LVD interrupt flag event Enabled. + * |[3] |CORBRKEN |Core Lockup Detection Trigger PWM Brake Function Enable Bit + * | | |0 = Brake Function triggered by core lockup event Disabled. + * | | |1 = Brake Function triggered by core lockup event Enabled. + * @var TIMER_T::PWMBRKCTL + * Offset: 0x70 Timer PWM Brake Control Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[4] |BRKPEEN |Enable TM_BRAKEx Pin As Edge-detect Brake Source (Write Protect) + * | | |0 = PWMx_BRAKEy pin event as edge-detect brake source Disabled. + * | | |1 = PWMx_BRAKEy pin event as edge-detect brake source Enabled. + * | | |Note: This bit is write protected + * | | |Refer to the SYS_RLKTZS register or SYS_RLKTZNS register or SYS_RLKSUBM register + * |[7] |SYSEBEN |Enable System Fail As Edge-detect Brake Source (Write Protect) + * | | |0 = System fail condition as edge-detect brake source Disabled. + * | | |1 = System fail condition as edge-detect brake source Enabled. + * | | |Note: This bit is write protected + * | | |Refer to the SYS_RLKTZS register or SYS_RLKTZNS register or SYS_RLKSUBM register + * |[12] |BRKPLEN |Enable TM_BRAKEx Pin As Level-detect Brake Source (Write Protect) + * | | |0 = PWMx_BRAKEy pin event as level-detect brake source Disabled. + * | | |1 = PWMx_BRAKEy pin event as level-detect brake source Enabled. + * | | |Note: This bit is write protected + * | | |Refer to the SYS_RLKTZS register or SYS_RLKTZNS register or SYS_RLKSUBM register + * |[15] |SYSLBEN |Enable System Fail As Level-detect Brake Source (Write Protect) + * | | |0 = System fail condition as level-detect brake source Disabled. + * | | |1 = System fail condition as level-detect brake source Enabled. + * | | |Note: This bit is write protected + * | | |Refer to the SYS_RLKTZS register or SYS_RLKTZNS register or SYS_RLKSUBM register + * |[17:16] |BRKAEVEN |PWM Brake Action Select for PWMx_CH0 (Write Protect) + * | | |00 = PWMx_BRAKEy brake event will not affect PWMx_CH0 output. + * | | |01 = PWMx_CH0 output tri-state when PWMx_BRAKEy brake event happened. + * | | |10 = PWMx_CH0 output low level when PWMx_BRAKEy brake event happened. + * | | |11 = PWMx_CH0 output high level when PWMx_BRAKEy brake event happened. + * | | |Note: This bit is write protected + * | | |Refer to the SYS_RLKTZS register or SYS_RLKTZNS register or SYS_RLKSUBM register + * |[19:18] |BRKAODD |PWM Brake Action Select for PWMx_CH1 (Write Protect) + * | | |00 = PWMx_BRAKEy brake event will not affect PWMx_CH1 output. + * | | |01 = PWMx_CH1 output tri-state when PWMx_BRAKEy brake event happened. + * | | |10 = PWMx_CH1 output low level when PWMx_BRAKEy brake event happened. + * | | |11 = PWMx_CH1 output high level when PWMx_BRAKEy brake event happened. + * | | |Note: This bit is write protected + * | | |Refer to the SYS_RLKTZS register or SYS_RLKTZNS register or SYS_RLKSUBM register + * @var TIMER_T::PWMPOLCTL + * Offset: 0x74 Timer PWM Pin Output Polar Control Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[0] |PINV0 |PWMx_CH0 Output Pin Polar Control Bit + * | | |The bit is used to control polarity state of PWMx_CH0 output pin. + * | | |0 = PWMx_CH0 output pin polar inverse Disabled. + * | | |1 = PWMx_CH0 output pin polar inverse Enabled. + * |[1] |PINV1 |PWMx_CH1 Output Pin Polar Control Bit + * | | |The bit is used to control polarity state of PWMx_CH1 output pin. + * | | |0 = PWMx_CH1 output pin polar inverse Disabled. + * | | |1 = PWMx_CH1 output pin polar inverse Enabled. + * @var TIMER_T::PWMPOEN + * Offset: 0x78 Timer PWM Pin Output Enable Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[0] |POEN0 |PWMx_CH0 Output Pin Enable Bit + * | | |0 = PWMx_CH0 pin at tri-state mode. + * | | |1 = PWMx_CH0 pin in output mode. + * |[1] |POEN1 |PWMx_CH1 Output Pin Enable Bit + * | | |0 = PWMx_CH1 pin at tri-state mode. + * | | |1 = PWMx_CH1 pin in output mode. + * @var TIMER_T::PWMSWBRK + * Offset: 0x7C Timer PWM Software Trigger Brake Control Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[0] |BRKETRG |Software Trigger Edge-detect Brake Source (Write Only) (Write Protect) + * | | |Write 1 to this bit will trigger PWM edge-detect brake source, then BRKEIF0 and BRKEIF1 will set to 1 automatically in TIMERx_PWMINTSTS1 register. + * | | |Note: This bit is write protected + * | | |Refer to the SYS_RLKTZS register or SYS_RLKTZNS register or SYS_RLKSUBM register + * |[8] |BRKLTRG |Software Trigger Level-detect Brake Source (Write Only) (Write Protect) + * | | |Write 1 to this bit will trigger PWM level-detect brake source, then BRKLIF0 and BRKLIF1 will set to 1 automatically in TIMERx_PWMINTSTS1 register. + * | | |Note: This bit is write protected + * | | |Refer to the SYS_RLKTZS register or SYS_RLKTZNS register or SYS_RLKSUBM register + * @var TIMER_T::PWMINTEN0 + * Offset: 0x80 Timer PWM Interrupt Enable Register 0 + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[0] |ZIEN |PWM Zero Point Interrupt Enable Bit + * | | |0 = Zero point interrupt Disabled. + * | | |1 = Zero point interrupt Enabled. + * |[1] |PIEN |PWM Period Point Interrupt Enable Bit + * | | |0 = Period point interrupt Disabled. + * | | |1 = Period point interrupt Enabled. + * | | |Note: In up-down count type, period point means the center point of current PWM period. + * |[2] |CMPUIEN |PWM Compare Up Count Interrupt Enable Bit + * | | |0 = Compare up count interrupt Disabled. + * | | |1 = Compare up count interrupt Enabled. + * |[3] |CMPDIEN |PWM Compare Down Count Interrupt Enable Bit + * | | |0 = Compare down count interrupt Disabled. + * | | |1 = Compare down count interrupt Enabled. + * @var TIMER_T::PWMINTEN1 + * Offset: 0x84 Timer PWM Interrupt Enable Register 1 + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[0] |BRKEIEN |PWM Edge-detect Brake Interrupt Enable Bit + * | | |0 = PWM edge-detect brake interrupt Disabled. + * | | |1 = PWM edge-detect brake interrupt Enabled. + * |[8] |BRKLIEN |PWM Level-detect Brake Interrupt Enable Bit + * | | |0 = PWM level-detect brake interrupt Disabled. + * | | |1 = PWM level-detect brake interrupt Enabled. + * @var TIMER_T::PWMINTSTS0 + * Offset: 0x88 Timer PWM Interrupt Status Register 0 + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[0] |ZIF |PWM Zero Point Interrupt Flag + * | | |This bit is set by hardware when TIMERx_PWM counter reaches 0. + * | | |Note: This bit is cleared by writing 1 to it. + * |[1] |PIF |PWM Period Point Interrupt Flag + * | | |This bit is set by hardware when TIMERx_PWM counter reaches PERIOD. + * | | |Note 1: In up-down count type, PIF flag means the center point flag of current PWM period. + * | | |Note 2: This bit is cleared by writing 1 to it. + * |[2] |CMPUIF |PWM Compare Up Count Interrupt Flag + * | | |This bit is set by hardware when TIMERx_PWM counter in up count direction and reaches CMP. + * | | |Note 1: If CMP equal to PERIOD, there is no CMPUIF flag in up count type and up-down count type. + * | | |Note 2: This bit is cleared by writing 1 to it. + * |[3] |CMPDIF |PWM Compare Down Count Interrupt Flag + * | | |This bit is set by hardware when TIMERx_PWM counter in down count direction and reaches CMP. + * | | |Note 1: If CMP equal to PERIOD, there is no CMPDIF flag in down count type. + * | | |Note 2: This bit is cleared by writing 1 to it. + * @var TIMER_T::PWMINTSTS1 + * Offset: 0x8C Timer PWM Interrupt Status Register 1 + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[0] |BRKEIF0 |Edge-detect Brake Interrupt Flag on PWMx_CH0 (Write Protect) + * | | |0 = PWMx_CH0 edge-detect brake event do not happened. + * | | |1 = PWMx_CH0 edge-detect brake event happened. + * | | |Note 1: This bit is cleared by writing 1 to it. + * | | |Note 2: This bit is write protected + * | | |Refer to the SYS_RLKTZS register or SYS_RLKTZNS register or SYS_RLKSUBM register + * |[1] |BRKEIF1 |Edge-detect Brake Interrupt Flag PWMx_CH1 (Write Protect) + * | | |0 = PWMx_CH1 edge-detect brake event do not happened. + * | | |1 = PWMx_CH1 edge-detect brake event happened. + * | | |Note 1: This bit is cleared by writing 1 to it. + * | | |Note 2: This bit is write protected + * | | |Refer to the SYS_RLKTZS register or SYS_RLKTZNS register or SYS_RLKSUBM register + * |[8] |BRKLIF0 |Level-detect Brake Interrupt Flag on PWMx_CH0 (Write Protect) + * | | |0 = PWMx_CH0 level-detect brake event do not happened. + * | | |1 = PWMx_CH0 level-detect brake event happened. + * | | |Note 1: This bit is cleared by writing 1 to it. + * | | |Note 2: This bit is write protected + * | | |Refer to the SYS_RLKTZS register or SYS_RLKTZNS register or SYS_RLKSUBM register + * |[9] |BRKLIF1 |Level-detect Brake Interrupt Flag on PWMx_CH1 (Write Protect) + * | | |0 = PWMx_CH1 level-detect brake event do not happened. + * | | |1 = PWMx_CH1 level-detect brake event happened. + * | | |Note 1: This bit is cleared by writing 1 to it. + * | | |Note 2: This bit is write protected + * | | |Refer to the SYS_RLKTZS register or SYS_RLKTZNS register or SYS_RLKSUBM register + * |[16] |BRKESTS0 |Edge -detect Brake Status of PWMx_CH0 (Read Only) + * | | |0 = PWMx_CH0 edge-detect brake state is released. + * | | |1 = PWMx_CH0 at edge-detect brake state. + * | | |Note: User can set BRKEIF0 1 to clear BRKEIF0 flag and PWMx_CH0 will release brake state when current PWM period finished and resume PWMx_CH0 output waveform start from next full PWM period. + * |[17] |BRKESTS1 |Edge-detect Brake Status of PWMx_CH1 (Read Only) + * | | |0 = PWMx_CH1 edge-detect brake state is released. + * | | |1 = PWMx_CH1 at edge-detect brake state. + * | | |Note: User can set BRKEIF1 1 to clear BRKEIF1 flag and PWMx_CH1 will release brake state when current PWM period finished and resume PWMx_CH1 output waveform start from next full PWM period. + * |[24] |BRKLSTS0 |Level-detect Brake Status of PWMx_CH0 (Read Only) + * | | |0 = PWMx_CH0 level-detect brake state is released. + * | | |1 = PWMx_CH0 at level-detect brake state. + * | | |Note: If TIMERx_PWM level-detect brake source has released, both PWMx_CH0 and PWMx_CH1 will release brake state when current PWM period finished and resume PWMx_CH0 and PWMx_CH1 output waveform start from next full PWM period. + * |[25] |BRKLSTS1 |Level-detect Brake Status of PWMx_CH1 (Read Only) + * | | |0 = PWMx_CH1 level-detect brake state is released. + * | | |1 = PWMx_CH1 at level-detect brake state. + * | | |Note: If TIMERx_PWM level-detect brake source has released, both PWMx_CH0 and PWMx_CH1 will release brake state when current PWM period finished and resume PWMx_CH0 and PWMx_CH1 output waveform start from next full PWM period. + * @var TIMER_T::PWMEADCTS + * Offset: 0x90 Timer PWM EADC Trigger Source Select Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[2:0] |TRGSEL |PWM Counter Event Source Select to Trigger EADC Conversion + * | | |000 = Trigger EADC conversion at zero point (ZIF). + * | | |001 = Trigger EADC conversion at period point (PIF). + * | | |010 = Trigger EADC conversion at zero or period point (ZIF or PIF). + * | | |011 = Trigger EADC conversion at compare up count point (CMPUIF). + * | | |100 = Trigger EADC conversion at compare down count point (CMPDIF). + * | | |Others = Reserved. + * |[7] |TRGEN |PWM Counter Event Trigger EADC Conversion Enable Bit + * | | |0 = PWM counter event trigger EADC conversion Disabled. + * | | |1 = PWM counter event trigger EADC conversion Enabled. + * @var TIMER_T::PWMSCTL + * Offset: 0x94 Timer PWM Synchronous Control Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[1:0] |SYNCMODE |PWM Synchronous Mode Enable Select + * | | |00 = PWM synchronous function Disabled. + * | | |01 = PWM synchronous counter start function Enabled. + * | | |10 = Reserved. + * | | |11 = PWM synchronous counter clear function Enabled. + * |[10:8] |SYNCSRC |PWM Synchronous Counter Start/Clear Source Select + * | | |000 = Counter synchronous start/clear by trigger TIMER0_PWMSTRG STRGEN. + * | | |001 = Counter synchronous start/clear by trigger TIMER2_PWMSTRG STRGEN. + * | | |010 = Counter synchronous start/clear by trigger TIMER4_PWMSTRG STRGEN. + * | | |011 = Counter synchronous start/clear by trigger TIMER6_PWMSTRG STRGEN. + * | | |100 = Counter synchronous start/clear by trigger TIMER8_PWMSTRG STRGEN. + * | | |101 = Counter synchronous start/clear by trigger TIMER10_PWMSTRG STRGEN. + * | | |Note 1: If TIMER0/1/2/3 PWM counter synchronous source are from TIMER0, TIMER0_PWMSCTL[8], TIMER1_PWMSCTL[8], TIMER2_PWMSCTL[8] and TIMER3_PWMSCTL[8] should be 0. + * | | |Note 2: If TIMER0/1/ PWM counter synchronous source are from TIMER0, TIMER0_PWMSCTL[8] and TIMER1_PWMSCTL[8] should be set 0, and TIMER2/3/ PWM counter synchronous source are from TIMER2, TIME2_PWMSCTL[8] and TIMER3_PWMSCTL[8] should be set 1. + * @var TIMER_T::PWMSTRG + * Offset: 0x98 Timer PWM Synchronous Trigger Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[0] |STRGEN |PWM Counter Synchronous Trigger Enable Bit (Write Only) + * | | |PMW counter synchronous function is used to make selected PWM channels (include TIMER0/1/2/3 PWM, TIMER0/1 PWM and TIMER2/3 PWM) start counting or clear counter at the same time according to TIMERx_PWMSCTL setting. + * | | |Note: This bit is only available in TIMER0 and TIMER2. + * @var TIMER_T::PWMSTATUS + * Offset: 0x9C Timer PWM Status Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[0] |CNTMAXF |PWM Counter Equal to 0xFFFF Flag + * | | |0 = The PWM counter value never reached its maximum value 0xFFFF. + * | | |1 = The PWM counter value has reached its maximum value. + * | | |Note: This bit is cleared by writing 1 to it. + * |[16] |EADCTRGF |Trigger EADC Start Conversion Flag + * | | |0 = PWM counter event trigger EADC start conversion is not occurred. + * | | |1 = PWM counter event trigger EADC start conversion has occurred. + * | | |Note: This bit is cleared by writing 1 to it. + * @var TIMER_T::PWMPBUF + * Offset: 0xA0 Timer PWM Period Buffer Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[15:0] |PBUF |PWM Period Buffer Register (Read Only) + * | | |Used as PERIOD active register. + * @var TIMER_T::PWMCMPBUF + * Offset: 0xA4 Timer PWM Comparator Buffer Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[15:0] |CMPBUF |PWM Comparator Buffer Register (Read Only) + * | | |Used as CMP active register. + */ + __IO uint32_t CTL; /*!< [0x0000] Timer Control Register */ + __IO uint32_t CMP; /*!< [0x0004] Timer Comparator Register */ + __IO uint32_t INTSTS; /*!< [0x0008] Timer Interrupt Status Register */ + __IO uint32_t CNT; /*!< [0x000c] Timer Data Register */ + __I uint32_t CAP; /*!< [0x0010] Timer Capture Data Register */ + __IO uint32_t EXTCTL; /*!< [0x0014] Timer External Control Register */ + __IO uint32_t EINTSTS; /*!< [0x0018] Timer External Interrupt Status Register */ + __IO uint32_t TRGCTL; /*!< [0x001c] Timer Trigger Control Register */ + __IO uint32_t ALTCTL; /*!< [0x0020] Timer Alternative Control Register */ + __I uint32_t RESERVE0[7]; + __IO uint32_t PWMCTL; /*!< [0x0040] Timer PWM Control Register */ + __IO uint32_t PWMCLKSRC; /*!< [0x0044] Timer PWM Counter Clock Source Register */ + __IO uint32_t PWMCLKPSC; /*!< [0x0048] Timer PWM Counter Clock Pre-scale Register */ + __IO uint32_t PWMCNTCLR; /*!< [0x004c] Timer PWM Clear Counter Register */ + __IO uint32_t PWMPERIOD; /*!< [0x0050] Timer PWM Period Register */ + __IO uint32_t PWMCMPDAT; /*!< [0x0054] Timer PWM Comparator Register */ + __IO uint32_t PWMDTCTL; /*!< [0x0058] Timer PWM Dead-time Control Register */ + __I uint32_t PWMCNT; /*!< [0x005c] Timer PWM Counter Register */ + __IO uint32_t PWMMSKEN; /*!< [0x0060] Timer PWM Output Mask Enable Register */ + __IO uint32_t PWMMSK; /*!< [0x0064] Timer PWM Output Mask Data Control Register */ + __IO uint32_t PWMBNF; /*!< [0x0068] Timer PWM Brake Pin Noise Filter Register */ + __IO uint32_t PWMFAILBRK; /*!< [0x006c] Timer PWM System Fail Brake Control Register */ + __IO uint32_t PWMBRKCTL; /*!< [0x0070] Timer PWM Brake Control Register */ + __IO uint32_t PWMPOLCTL; /*!< [0x0074] Timer PWM Pin Output Polar Control Register */ + __IO uint32_t PWMPOEN; /*!< [0x0078] Timer PWM Pin Output Enable Register */ + __O uint32_t PWMSWBRK; /*!< [0x007c] Timer PWM Software Trigger Brake Control Register */ + __IO uint32_t PWMINTEN0; /*!< [0x0080] Timer PWM Interrupt Enable Register 0 */ + __IO uint32_t PWMINTEN1; /*!< [0x0084] Timer PWM Interrupt Enable Register 1 */ + __IO uint32_t PWMINTSTS0; /*!< [0x0088] Timer PWM Interrupt Status Register 0 */ + __IO uint32_t PWMINTSTS1; /*!< [0x008c] Timer PWM Interrupt Status Register 1 */ + __IO uint32_t PWMEADCTS; /*!< [0x0090] Timer PWM EADC Trigger Source Select Register */ + __IO uint32_t PWMSCTL; /*!< [0x0094] Timer PWM Synchronous Control Register */ + __O uint32_t PWMSTRG; /*!< [0x0098] Timer PWM Synchronous Trigger Register */ + __IO uint32_t PWMSTATUS; /*!< [0x009c] Timer PWM Status Register */ + __I uint32_t PWMPBUF; /*!< [0x00a0] Timer PWM Period Buffer Register */ + __I uint32_t PWMCMPBUF; /*!< [0x00a4] Timer PWM Comparator Buffer Register */ + +} TIMER_T; + +/** + @addtogroup TIMER_CONST TIMER Bit Field Definition + Constant Definitions for TIMER Controller +@{ */ + +#define TIMER_CTL_PSC_Pos (0) /*!< TIMER_T::CTL: PSC Position */ +#define TIMER_CTL_PSC_Msk (0xfful << TIMER_CTL_PSC_Pos) /*!< TIMER_T::CTL: PSC Mask */ + +#define TIMER_CTL_INTRGEN_Pos (19) /*!< TIMER_T::CTL: INTRGEN Position */ +#define TIMER_CTL_INTRGEN_Msk (0x1ul << TIMER_CTL_INTRGEN_Pos) /*!< TIMER_T::CTL: INTRGEN Mask */ + +#define TIMER_CTL_PERIOSEL_Pos (20) /*!< TIMER_T::CTL: PERIOSEL Position */ +#define TIMER_CTL_PERIOSEL_Msk (0x1ul << TIMER_CTL_PERIOSEL_Pos) /*!< TIMER_T::CTL: PERIOSEL Mask */ + +#define TIMER_CTL_TGLPINSEL_Pos (21) /*!< TIMER_T::CTL: TGLPINSEL Position */ +#define TIMER_CTL_TGLPINSEL_Msk (0x1ul << TIMER_CTL_TGLPINSEL_Pos) /*!< TIMER_T::CTL: TGLPINSEL Mask */ + +#define TIMER_CTL_CAPSRC_Pos (22) /*!< TIMER_T::CTL: CAPSRC Position */ +#define TIMER_CTL_CAPSRC_Msk (0x1ul << TIMER_CTL_CAPSRC_Pos) /*!< TIMER_T::CTL: CAPSRC Mask */ + +#define TIMER_CTL_WKEN_Pos (23) /*!< TIMER_T::CTL: WKEN Position */ +#define TIMER_CTL_WKEN_Msk (0x1ul << TIMER_CTL_WKEN_Pos) /*!< TIMER_T::CTL: WKEN Mask */ + +#define TIMER_CTL_EXTCNTEN_Pos (24) /*!< TIMER_T::CTL: EXTCNTEN Position */ +#define TIMER_CTL_EXTCNTEN_Msk (0x1ul << TIMER_CTL_EXTCNTEN_Pos) /*!< TIMER_T::CTL: EXTCNTEN Mask */ + +#define TIMER_CTL_ACTSTS_Pos (25) /*!< TIMER_T::CTL: ACTSTS Position */ +#define TIMER_CTL_ACTSTS_Msk (0x1ul << TIMER_CTL_ACTSTS_Pos) /*!< TIMER_T::CTL: ACTSTS Mask */ + +#define TIMER_CTL_OPMODE_Pos (27) /*!< TIMER_T::CTL: OPMODE Position */ +#define TIMER_CTL_OPMODE_Msk (0x3ul << TIMER_CTL_OPMODE_Pos) /*!< TIMER_T::CTL: OPMODE Mask */ + +#define TIMER_CTL_INTEN_Pos (29) /*!< TIMER_T::CTL: INTEN Position */ +#define TIMER_CTL_INTEN_Msk (0x1ul << TIMER_CTL_INTEN_Pos) /*!< TIMER_T::CTL: INTEN Mask */ + +#define TIMER_CTL_CNTEN_Pos (30) /*!< TIMER_T::CTL: CNTEN Position */ +#define TIMER_CTL_CNTEN_Msk (0x1ul << TIMER_CTL_CNTEN_Pos) /*!< TIMER_T::CTL: CNTEN Mask */ + +#define TIMER_CTL_ICEDEBUG_Pos (31) /*!< TIMER_T::CTL: ICEDEBUG Position */ +#define TIMER_CTL_ICEDEBUG_Msk (0x1ul << TIMER_CTL_ICEDEBUG_Pos) /*!< TIMER_T::CTL: ICEDEBUG Mask */ + +#define TIMER_CMP_CMPDAT_Pos (0) /*!< TIMER_T::CMP: CMPDAT Position */ +#define TIMER_CMP_CMPDAT_Msk (0xfffffful << TIMER_CMP_CMPDAT_Pos) /*!< TIMER_T::CMP: CMPDAT Mask */ + +#define TIMER_INTSTS_TIF_Pos (0) /*!< TIMER_T::INTSTS: TIF Position */ +#define TIMER_INTSTS_TIF_Msk (0x1ul << TIMER_INTSTS_TIF_Pos) /*!< TIMER_T::INTSTS: TIF Mask */ + +#define TIMER_INTSTS_TWKF_Pos (1) /*!< TIMER_T::INTSTS: TWKF Position */ +#define TIMER_INTSTS_TWKF_Msk (0x1ul << TIMER_INTSTS_TWKF_Pos) /*!< TIMER_T::INTSTS: TWKF Mask */ + +#define TIMER_CNT_CNT_Pos (0) /*!< TIMER_T::CNT: CNT Position */ +#define TIMER_CNT_CNT_Msk (0xfffffful << TIMER_CNT_CNT_Pos) /*!< TIMER_T::CNT: CNT Mask */ + +#define TIMER_CNT_RSTACT_Pos (31) /*!< TIMER_T::CNT: RSTACT Position */ +#define TIMER_CNT_RSTACT_Msk (0x1ul << TIMER_CNT_RSTACT_Pos) /*!< TIMER_T::CNT: RSTACT Mask */ + +#define TIMER_CAP_CAPDAT_Pos (0) /*!< TIMER_T::CAP: CAPDAT Position */ +#define TIMER_CAP_CAPDAT_Msk (0xfffffful << TIMER_CAP_CAPDAT_Pos) /*!< TIMER_T::CAP: CAPDAT Mask */ + +#define TIMER_EXTCTL_CNTPHASE_Pos (0) /*!< TIMER_T::EXTCTL: CNTPHASE Position */ +#define TIMER_EXTCTL_CNTPHASE_Msk (0x1ul << TIMER_EXTCTL_CNTPHASE_Pos) /*!< TIMER_T::EXTCTL: CNTPHASE Mask */ + +#define TIMER_EXTCTL_CAPEN_Pos (3) /*!< TIMER_T::EXTCTL: CAPEN Position */ +#define TIMER_EXTCTL_CAPEN_Msk (0x1ul << TIMER_EXTCTL_CAPEN_Pos) /*!< TIMER_T::EXTCTL: CAPEN Mask */ + +#define TIMER_EXTCTL_CAPFUNCS_Pos (4) /*!< TIMER_T::EXTCTL: CAPFUNCS Position */ +#define TIMER_EXTCTL_CAPFUNCS_Msk (0x1ul << TIMER_EXTCTL_CAPFUNCS_Pos) /*!< TIMER_T::EXTCTL: CAPFUNCS Mask */ + +#define TIMER_EXTCTL_CAPIEN_Pos (5) /*!< TIMER_T::EXTCTL: CAPIEN Position */ +#define TIMER_EXTCTL_CAPIEN_Msk (0x1ul << TIMER_EXTCTL_CAPIEN_Pos) /*!< TIMER_T::EXTCTL: CAPIEN Mask */ + +#define TIMER_EXTCTL_CAPDBEN_Pos (6) /*!< TIMER_T::EXTCTL: CAPDBEN Position */ +#define TIMER_EXTCTL_CAPDBEN_Msk (0x1ul << TIMER_EXTCTL_CAPDBEN_Pos) /*!< TIMER_T::EXTCTL: CAPDBEN Mask */ + +#define TIMER_EXTCTL_CNTDBEN_Pos (7) /*!< TIMER_T::EXTCTL: CNTDBEN Position */ +#define TIMER_EXTCTL_CNTDBEN_Msk (0x1ul << TIMER_EXTCTL_CNTDBEN_Pos) /*!< TIMER_T::EXTCTL: CNTDBEN Mask */ + +#define TIMER_EXTCTL_ICAPSSEL_Pos (8) /*!< TIMER_T::EXTCTL: ICAPSSEL Position */ +#define TIMER_EXTCTL_ICAPSSEL_Msk (0x7ul << TIMER_EXTCTL_ICAPSSEL_Pos) /*!< TIMER_T::EXTCTL: ICAPSSEL Mask */ + +#define TIMER_EXTCTL_CAPEDGE_Pos (12) /*!< TIMER_T::EXTCTL: CAPEDGE Position */ +#define TIMER_EXTCTL_CAPEDGE_Msk (0x7ul << TIMER_EXTCTL_CAPEDGE_Pos) /*!< TIMER_T::EXTCTL: CAPEDGE Mask */ + +#define TIMER_EXTCTL_ECNTSSEL_Pos (16) /*!< TIMER_T::EXTCTL: ECNTSSEL Position */ +#define TIMER_EXTCTL_ECNTSSEL_Msk (0x1ul << TIMER_EXTCTL_ECNTSSEL_Pos) /*!< TIMER_T::EXTCTL: ECNTSSEL Mask */ + +#define TIMER_EXTCTL_CAPSDIV_Pos (28) /*!< TIMER_T::EXTCTL: CAPSDIV Position */ +#define TIMER_EXTCTL_CAPSDIV_Msk (0xful << TIMER_EXTCTL_CAPSDIV_Pos) /*!< TIMER_T::EXTCTL: CAPSDIV Mask */ + +#define TIMER_EINTSTS_CAPIF_Pos (0) /*!< TIMER_T::EINTSTS: CAPIF Position */ +#define TIMER_EINTSTS_CAPIF_Msk (0x1ul << TIMER_EINTSTS_CAPIF_Pos) /*!< TIMER_T::EINTSTS: CAPIF Mask */ + +#define TIMER_TRGCTL_TRGSSEL_Pos (0) /*!< TIMER_T::TRGCTL: TRGSSEL Position */ +#define TIMER_TRGCTL_TRGSSEL_Msk (0x1ul << TIMER_TRGCTL_TRGSSEL_Pos) /*!< TIMER_T::TRGCTL: TRGSSEL Mask */ + +#define TIMER_TRGCTL_TRGPWM_Pos (1) /*!< TIMER_T::TRGCTL: TRGPWM Position */ +#define TIMER_TRGCTL_TRGPWM_Msk (0x1ul << TIMER_TRGCTL_TRGPWM_Pos) /*!< TIMER_T::TRGCTL: TRGPWM Mask */ + +#define TIMER_TRGCTL_TRGEADC_Pos (2) /*!< TIMER_T::TRGCTL: TRGEADC Position */ +#define TIMER_TRGCTL_TRGEADC_Msk (0x1ul << TIMER_TRGCTL_TRGEADC_Pos) /*!< TIMER_T::TRGCTL: TRGEADC Mask */ + +#define TIMER_TRGCTL_TRGPDMA_Pos (4) /*!< TIMER_T::TRGCTL: TRGPDMA Position */ +#define TIMER_TRGCTL_TRGPDMA_Msk (0x1ul << TIMER_TRGCTL_TRGPDMA_Pos) /*!< TIMER_T::TRGCTL: TRGPDMA Mask */ + +#define TIMER_ALTCTL_FUNCSEL_Pos (0) /*!< TIMER_T::ALTCTL: FUNCSEL Position */ +#define TIMER_ALTCTL_FUNCSEL_Msk (0x1ul << TIMER_ALTCTL_FUNCSEL_Pos) /*!< TIMER_T::ALTCTL: FUNCSEL Mask */ + +#define TIMER_PWMCTL_CNTEN_Pos (0) /*!< TIMER_T::PWMCTL: CNTEN Position */ +#define TIMER_PWMCTL_CNTEN_Msk (0x1ul << TIMER_PWMCTL_CNTEN_Pos) /*!< TIMER_T::PWMCTL: CNTEN Mask */ + +#define TIMER_PWMCTL_CNTTYPE_Pos (1) /*!< TIMER_T::PWMCTL: CNTTYPE Position */ +#define TIMER_PWMCTL_CNTTYPE_Msk (0x3ul << TIMER_PWMCTL_CNTTYPE_Pos) /*!< TIMER_T::PWMCTL: CNTTYPE Mask */ + +#define TIMER_PWMCTL_CNTMODE_Pos (3) /*!< TIMER_T::PWMCTL: CNTMODE Position */ +#define TIMER_PWMCTL_CNTMODE_Msk (0x1ul << TIMER_PWMCTL_CNTMODE_Pos) /*!< TIMER_T::PWMCTL: CNTMODE Mask */ + +#define TIMER_PWMCTL_CTRLD_Pos (8) /*!< TIMER_T::PWMCTL: CTRLD Position */ +#define TIMER_PWMCTL_CTRLD_Msk (0x1ul << TIMER_PWMCTL_CTRLD_Pos) /*!< TIMER_T::PWMCTL: CTRLD Mask */ + +#define TIMER_PWMCTL_IMMLDEN_Pos (9) /*!< TIMER_T::PWMCTL: IMMLDEN Position */ +#define TIMER_PWMCTL_IMMLDEN_Msk (0x1ul << TIMER_PWMCTL_IMMLDEN_Pos) /*!< TIMER_T::PWMCTL: IMMLDEN Mask */ + +#define TIMER_PWMCTL_OUTMODE_Pos (16) /*!< TIMER_T::PWMCTL: OUTMODE Position */ +#define TIMER_PWMCTL_OUTMODE_Msk (0x1ul << TIMER_PWMCTL_OUTMODE_Pos) /*!< TIMER_T::PWMCTL: OUTMODE Mask */ + +#define TIMER_PWMCTL_DBGHALT_Pos (30) /*!< TIMER_T::PWMCTL: DBGHALT Position */ +#define TIMER_PWMCTL_DBGHALT_Msk (0x1ul << TIMER_PWMCTL_DBGHALT_Pos) /*!< TIMER_T::PWMCTL: DBGHALT Mask */ + +#define TIMER_PWMCTL_DBGTRIOFF_Pos (31) /*!< TIMER_T::PWMCTL: DBGTRIOFF Position */ +#define TIMER_PWMCTL_DBGTRIOFF_Msk (0x1ul << TIMER_PWMCTL_DBGTRIOFF_Pos) /*!< TIMER_T::PWMCTL: DBGTRIOFF Mask */ + +#define TIMER_PWMCLKSRC_CLKSRC_Pos (0) /*!< TIMER_T::PWMCLKSRC: CLKSRC Position */ +#define TIMER_PWMCLKSRC_CLKSRC_Msk (0xful << TIMER_PWMCLKSRC_CLKSRC_Pos) /*!< TIMER_T::PWMCLKSRC: CLKSRC Mask */ + +#define TIMER_PWMCLKPSC_CLKPSC_Pos (0) /*!< TIMER_T::PWMCLKPSC: CLKPSC Position */ +#define TIMER_PWMCLKPSC_CLKPSC_Msk (0xffful << TIMER_PWMCLKPSC_CLKPSC_Pos) /*!< TIMER_T::PWMCLKPSC: CLKPSC Mask */ + +#define TIMER_PWMCNTCLR_CNTCLR_Pos (0) /*!< TIMER_T::PWMCNTCLR: CNTCLR Position */ +#define TIMER_PWMCNTCLR_CNTCLR_Msk (0x1ul << TIMER_PWMCNTCLR_CNTCLR_Pos) /*!< TIMER_T::PWMCNTCLR: CNTCLR Mask */ + +#define TIMER_PWMPERIOD_PERIOD_Pos (0) /*!< TIMER_T::PWMPERIOD: PERIOD Position */ +#define TIMER_PWMPERIOD_PERIOD_Msk (0xfffful << TIMER_PWMPERIOD_PERIOD_Pos) /*!< TIMER_T::PWMPERIOD: PERIOD Mask */ + +#define TIMER_PWMCMPDAT_CMP_Pos (0) /*!< TIMER_T::PWMCMPDAT: CMP Position */ +#define TIMER_PWMCMPDAT_CMP_Msk (0xfffful << TIMER_PWMCMPDAT_CMP_Pos) /*!< TIMER_T::PWMCMPDAT: CMP Mask */ + +#define TIMER_PWMDTCTL_DTCNT_Pos (0) /*!< TIMER_T::PWMDTCTL: DTCNT Position */ +#define TIMER_PWMDTCTL_DTCNT_Msk (0xffful << TIMER_PWMDTCTL_DTCNT_Pos) /*!< TIMER_T::PWMDTCTL: DTCNT Mask */ + +#define TIMER_PWMDTCTL_DTEN_Pos (16) /*!< TIMER_T::PWMDTCTL: DTEN Position */ +#define TIMER_PWMDTCTL_DTEN_Msk (0x1ul << TIMER_PWMDTCTL_DTEN_Pos) /*!< TIMER_T::PWMDTCTL: DTEN Mask */ + +#define TIMER_PWMDTCTL_DTCKSEL_Pos (24) /*!< TIMER_T::PWMDTCTL: DTCKSEL Position */ +#define TIMER_PWMDTCTL_DTCKSEL_Msk (0x1ul << TIMER_PWMDTCTL_DTCKSEL_Pos) /*!< TIMER_T::PWMDTCTL: DTCKSEL Mask */ + +#define TIMER_PWMCNT_CNT_Pos (0) /*!< TIMER_T::PWMCNT: CNT Position */ +#define TIMER_PWMCNT_CNT_Msk (0xfffful << TIMER_PWMCNT_CNT_Pos) /*!< TIMER_T::PWMCNT: CNT Mask */ + +#define TIMER_PWMCNT_DIRF_Pos (16) /*!< TIMER_T::PWMCNT: DIRF Position */ +#define TIMER_PWMCNT_DIRF_Msk (0x1ul << TIMER_PWMCNT_DIRF_Pos) /*!< TIMER_T::PWMCNT: DIRF Mask */ + +#define TIMER_PWMMSKEN_MSKEN0_Pos (0) /*!< TIMER_T::PWMMSKEN: MSKEN0 Position */ +#define TIMER_PWMMSKEN_MSKEN0_Msk (0x1ul << TIMER_PWMMSKEN_MSKEN0_Pos) /*!< TIMER_T::PWMMSKEN: MSKEN0 Mask */ + +#define TIMER_PWMMSKEN_MSKEN1_Pos (1) /*!< TIMER_T::PWMMSKEN: MSKEN1 Position */ +#define TIMER_PWMMSKEN_MSKEN1_Msk (0x1ul << TIMER_PWMMSKEN_MSKEN1_Pos) /*!< TIMER_T::PWMMSKEN: MSKEN1 Mask */ + +#define TIMER_PWMMSK_MSKDAT0_Pos (0) /*!< TIMER_T::PWMMSK: MSKDAT0 Position */ +#define TIMER_PWMMSK_MSKDAT0_Msk (0x1ul << TIMER_PWMMSK_MSKDAT0_Pos) /*!< TIMER_T::PWMMSK: MSKDAT0 Mask */ + +#define TIMER_PWMMSK_MSKDAT1_Pos (1) /*!< TIMER_T::PWMMSK: MSKDAT1 Position */ +#define TIMER_PWMMSK_MSKDAT1_Msk (0x1ul << TIMER_PWMMSK_MSKDAT1_Pos) /*!< TIMER_T::PWMMSK: MSKDAT1 Mask */ + +#define TIMER_PWMBNF_BRKNFEN_Pos (0) /*!< TIMER_T::PWMBNF: BRKNFEN Position */ +#define TIMER_PWMBNF_BRKNFEN_Msk (0x1ul << TIMER_PWMBNF_BRKNFEN_Pos) /*!< TIMER_T::PWMBNF: BRKNFEN Mask */ + +#define TIMER_PWMBNF_BRKNFSEL_Pos (1) /*!< TIMER_T::PWMBNF: BRKNFSEL Position */ +#define TIMER_PWMBNF_BRKNFSEL_Msk (0x7ul << TIMER_PWMBNF_BRKNFSEL_Pos) /*!< TIMER_T::PWMBNF: BRKNFSEL Mask */ + +#define TIMER_PWMBNF_BRKFCNT_Pos (4) /*!< TIMER_T::PWMBNF: BRKFCNT Position */ +#define TIMER_PWMBNF_BRKFCNT_Msk (0x7ul << TIMER_PWMBNF_BRKFCNT_Pos) /*!< TIMER_T::PWMBNF: BRKFCNT Mask */ + +#define TIMER_PWMBNF_BRKPINV_Pos (7) /*!< TIMER_T::PWMBNF: BRKPINV Position */ +#define TIMER_PWMBNF_BRKPINV_Msk (0x1ul << TIMER_PWMBNF_BRKPINV_Pos) /*!< TIMER_T::PWMBNF: BRKPINV Mask */ + +#define TIMER_PWMBNF_BKPINSRC_Pos (16) /*!< TIMER_T::PWMBNF: BKPINSRC Position */ +#define TIMER_PWMBNF_BKPINSRC_Msk (0x7ul << TIMER_PWMBNF_BKPINSRC_Pos) /*!< TIMER_T::PWMBNF: BKPINSRC Mask */ + +#define TIMER_PWMFAILBRK_CSSBRKEN_Pos (0) /*!< TIMER_T::PWMFAILBRK: CSSBRKEN Position */ +#define TIMER_PWMFAILBRK_CSSBRKEN_Msk (0x1ul << TIMER_PWMFAILBRK_CSSBRKEN_Pos) /*!< TIMER_T::PWMFAILBRK: CSSBRKEN Mask */ + +#define TIMER_PWMFAILBRK_LVDBRKEN_Pos (1) /*!< TIMER_T::PWMFAILBRK: LVDBRKEN Position */ +#define TIMER_PWMFAILBRK_LVDBRKEN_Msk (0x1ul << TIMER_PWMFAILBRK_LVDBRKEN_Pos) /*!< TIMER_T::PWMFAILBRK: LVDBRKEN Mask */ + +#define TIMER_PWMFAILBRK_CORBRKEN_Pos (3) /*!< TIMER_T::PWMFAILBRK: CORBRKEN Position */ +#define TIMER_PWMFAILBRK_CORBRKEN_Msk (0x1ul << TIMER_PWMFAILBRK_CORBRKEN_Pos) /*!< TIMER_T::PWMFAILBRK: CORBRKEN Mask */ + +#define TIMER_PWMBRKCTL_BRKPEEN_Pos (4) /*!< TIMER_T::PWMBRKCTL: BRKPEEN Position */ +#define TIMER_PWMBRKCTL_BRKPEEN_Msk (0x1ul << TIMER_PWMBRKCTL_BRKPEEN_Pos) /*!< TIMER_T::PWMBRKCTL: BRKPEEN Mask */ + +#define TIMER_PWMBRKCTL_SYSEBEN_Pos (7) /*!< TIMER_T::PWMBRKCTL: SYSEBEN Position */ +#define TIMER_PWMBRKCTL_SYSEBEN_Msk (0x1ul << TIMER_PWMBRKCTL_SYSEBEN_Pos) /*!< TIMER_T::PWMBRKCTL: SYSEBEN Mask */ + +#define TIMER_PWMBRKCTL_BRKPLEN_Pos (12) /*!< TIMER_T::PWMBRKCTL: BRKPLEN Position */ +#define TIMER_PWMBRKCTL_BRKPLEN_Msk (0x1ul << TIMER_PWMBRKCTL_BRKPLEN_Pos) /*!< TIMER_T::PWMBRKCTL: BRKPLEN Mask */ + +#define TIMER_PWMBRKCTL_SYSLBEN_Pos (15) /*!< TIMER_T::PWMBRKCTL: SYSLBEN Position */ +#define TIMER_PWMBRKCTL_SYSLBEN_Msk (0x1ul << TIMER_PWMBRKCTL_SYSLBEN_Pos) /*!< TIMER_T::PWMBRKCTL: SYSLBEN Mask */ + +#define TIMER_PWMBRKCTL_BRKAEVEN_Pos (16) /*!< TIMER_T::PWMBRKCTL: BRKAEVEN Position */ +#define TIMER_PWMBRKCTL_BRKAEVEN_Msk (0x3ul << TIMER_PWMBRKCTL_BRKAEVEN_Pos) /*!< TIMER_T::PWMBRKCTL: BRKAEVEN Mask */ + +#define TIMER_PWMBRKCTL_BRKAODD_Pos (18) /*!< TIMER_T::PWMBRKCTL: BRKAODD Position */ +#define TIMER_PWMBRKCTL_BRKAODD_Msk (0x3ul << TIMER_PWMBRKCTL_BRKAODD_Pos) /*!< TIMER_T::PWMBRKCTL: BRKAODD Mask */ + +#define TIMER_PWMPOLCTL_PINV0_Pos (0) /*!< TIMER_T::PWMPOLCTL: PINV0 Position */ +#define TIMER_PWMPOLCTL_PINV0_Msk (0x1ul << TIMER_PWMPOLCTL_PINV0_Pos) /*!< TIMER_T::PWMPOLCTL: PINV0 Mask */ + +#define TIMER_PWMPOLCTL_PINV1_Pos (1) /*!< TIMER_T::PWMPOLCTL: PINV1 Position */ +#define TIMER_PWMPOLCTL_PINV1_Msk (0x1ul << TIMER_PWMPOLCTL_PINV1_Pos) /*!< TIMER_T::PWMPOLCTL: PINV1 Mask */ + +#define TIMER_PWMPOEN_POEN0_Pos (0) /*!< TIMER_T::PWMPOEN: POEN0 Position */ +#define TIMER_PWMPOEN_POEN0_Msk (0x1ul << TIMER_PWMPOEN_POEN0_Pos) /*!< TIMER_T::PWMPOEN: POEN0 Mask */ + +#define TIMER_PWMPOEN_POEN1_Pos (1) /*!< TIMER_T::PWMPOEN: POEN1 Position */ +#define TIMER_PWMPOEN_POEN1_Msk (0x1ul << TIMER_PWMPOEN_POEN1_Pos) /*!< TIMER_T::PWMPOEN: POEN1 Mask */ + +#define TIMER_PWMSWBRK_BRKETRG_Pos (0) /*!< TIMER_T::PWMSWBRK: BRKETRG Position */ +#define TIMER_PWMSWBRK_BRKETRG_Msk (0x1ul << TIMER_PWMSWBRK_BRKETRG_Pos) /*!< TIMER_T::PWMSWBRK: BRKETRG Mask */ + +#define TIMER_PWMSWBRK_BRKLTRG_Pos (8) /*!< TIMER_T::PWMSWBRK: BRKLTRG Position */ +#define TIMER_PWMSWBRK_BRKLTRG_Msk (0x1ul << TIMER_PWMSWBRK_BRKLTRG_Pos) /*!< TIMER_T::PWMSWBRK: BRKLTRG Mask */ + +#define TIMER_PWMINTEN0_ZIEN_Pos (0) /*!< TIMER_T::PWMINTEN0: ZIEN Position */ +#define TIMER_PWMINTEN0_ZIEN_Msk (0x1ul << TIMER_PWMINTEN0_ZIEN_Pos) /*!< TIMER_T::PWMINTEN0: ZIEN Mask */ + +#define TIMER_PWMINTEN0_PIEN_Pos (1) /*!< TIMER_T::PWMINTEN0: PIEN Position */ +#define TIMER_PWMINTEN0_PIEN_Msk (0x1ul << TIMER_PWMINTEN0_PIEN_Pos) /*!< TIMER_T::PWMINTEN0: PIEN Mask */ + +#define TIMER_PWMINTEN0_CMPUIEN_Pos (2) /*!< TIMER_T::PWMINTEN0: CMPUIEN Position */ +#define TIMER_PWMINTEN0_CMPUIEN_Msk (0x1ul << TIMER_PWMINTEN0_CMPUIEN_Pos) /*!< TIMER_T::PWMINTEN0: CMPUIEN Mask */ + +#define TIMER_PWMINTEN0_CMPDIEN_Pos (3) /*!< TIMER_T::PWMINTEN0: CMPDIEN Position */ +#define TIMER_PWMINTEN0_CMPDIEN_Msk (0x1ul << TIMER_PWMINTEN0_CMPDIEN_Pos) /*!< TIMER_T::PWMINTEN0: CMPDIEN Mask */ + +#define TIMER_PWMINTEN1_BRKEIEN_Pos (0) /*!< TIMER_T::PWMINTEN1: BRKEIEN Position */ +#define TIMER_PWMINTEN1_BRKEIEN_Msk (0x1ul << TIMER_PWMINTEN1_BRKEIEN_Pos) /*!< TIMER_T::PWMINTEN1: BRKEIEN Mask */ + +#define TIMER_PWMINTEN1_BRKLIEN_Pos (8) /*!< TIMER_T::PWMINTEN1: BRKLIEN Position */ +#define TIMER_PWMINTEN1_BRKLIEN_Msk (0x1ul << TIMER_PWMINTEN1_BRKLIEN_Pos) /*!< TIMER_T::PWMINTEN1: BRKLIEN Mask */ + +#define TIMER_PWMINTSTS0_ZIF_Pos (0) /*!< TIMER_T::PWMINTSTS0: ZIF Position */ +#define TIMER_PWMINTSTS0_ZIF_Msk (0x1ul << TIMER_PWMINTSTS0_ZIF_Pos) /*!< TIMER_T::PWMINTSTS0: ZIF Mask */ + +#define TIMER_PWMINTSTS0_PIF_Pos (1) /*!< TIMER_T::PWMINTSTS0: PIF Position */ +#define TIMER_PWMINTSTS0_PIF_Msk (0x1ul << TIMER_PWMINTSTS0_PIF_Pos) /*!< TIMER_T::PWMINTSTS0: PIF Mask */ + +#define TIMER_PWMINTSTS0_CMPUIF_Pos (2) /*!< TIMER_T::PWMINTSTS0: CMPUIF Position */ +#define TIMER_PWMINTSTS0_CMPUIF_Msk (0x1ul << TIMER_PWMINTSTS0_CMPUIF_Pos) /*!< TIMER_T::PWMINTSTS0: CMPUIF Mask */ + +#define TIMER_PWMINTSTS0_CMPDIF_Pos (3) /*!< TIMER_T::PWMINTSTS0: CMPDIF Position */ +#define TIMER_PWMINTSTS0_CMPDIF_Msk (0x1ul << TIMER_PWMINTSTS0_CMPDIF_Pos) /*!< TIMER_T::PWMINTSTS0: CMPDIF Mask */ + +#define TIMER_PWMINTSTS1_BRKEIF0_Pos (0) /*!< TIMER_T::PWMINTSTS1: BRKEIF0 Position */ +#define TIMER_PWMINTSTS1_BRKEIF0_Msk (0x1ul << TIMER_PWMINTSTS1_BRKEIF0_Pos) /*!< TIMER_T::PWMINTSTS1: BRKEIF0 Mask */ + +#define TIMER_PWMINTSTS1_BRKEIF1_Pos (1) /*!< TIMER_T::PWMINTSTS1: BRKEIF1 Position */ +#define TIMER_PWMINTSTS1_BRKEIF1_Msk (0x1ul << TIMER_PWMINTSTS1_BRKEIF1_Pos) /*!< TIMER_T::PWMINTSTS1: BRKEIF1 Mask */ + +#define TIMER_PWMINTSTS1_BRKLIF0_Pos (8) /*!< TIMER_T::PWMINTSTS1: BRKLIF0 Position */ +#define TIMER_PWMINTSTS1_BRKLIF0_Msk (0x1ul << TIMER_PWMINTSTS1_BRKLIF0_Pos) /*!< TIMER_T::PWMINTSTS1: BRKLIF0 Mask */ + +#define TIMER_PWMINTSTS1_BRKLIF1_Pos (9) /*!< TIMER_T::PWMINTSTS1: BRKLIF1 Position */ +#define TIMER_PWMINTSTS1_BRKLIF1_Msk (0x1ul << TIMER_PWMINTSTS1_BRKLIF1_Pos) /*!< TIMER_T::PWMINTSTS1: BRKLIF1 Mask */ + +#define TIMER_PWMINTSTS1_BRKESTS0_Pos (16) /*!< TIMER_T::PWMINTSTS1: BRKESTS0 Position */ +#define TIMER_PWMINTSTS1_BRKESTS0_Msk (0x1ul << TIMER_PWMINTSTS1_BRKESTS0_Pos) /*!< TIMER_T::PWMINTSTS1: BRKESTS0 Mask */ + +#define TIMER_PWMINTSTS1_BRKESTS1_Pos (17) /*!< TIMER_T::PWMINTSTS1: BRKESTS1 Position */ +#define TIMER_PWMINTSTS1_BRKESTS1_Msk (0x1ul << TIMER_PWMINTSTS1_BRKESTS1_Pos) /*!< TIMER_T::PWMINTSTS1: BRKESTS1 Mask */ + +#define TIMER_PWMINTSTS1_BRKLSTS0_Pos (24) /*!< TIMER_T::PWMINTSTS1: BRKLSTS0 Position */ +#define TIMER_PWMINTSTS1_BRKLSTS0_Msk (0x1ul << TIMER_PWMINTSTS1_BRKLSTS0_Pos) /*!< TIMER_T::PWMINTSTS1: BRKLSTS0 Mask */ + +#define TIMER_PWMINTSTS1_BRKLSTS1_Pos (25) /*!< TIMER_T::PWMINTSTS1: BRKLSTS1 Position */ +#define TIMER_PWMINTSTS1_BRKLSTS1_Msk (0x1ul << TIMER_PWMINTSTS1_BRKLSTS1_Pos) /*!< TIMER_T::PWMINTSTS1: BRKLSTS1 Mask */ + +#define TIMER_PWMEADCTS_TRGSEL_Pos (0) /*!< TIMER_T::PWMEADCTS: TRGSEL Position */ +#define TIMER_PWMEADCTS_TRGSEL_Msk (0x7ul << TIMER_PWMEADCTS_TRGSEL_Pos) /*!< TIMER_T::PWMEADCTS: TRGSEL Mask */ + +#define TIMER_PWMEADCTS_TRGEN_Pos (7) /*!< TIMER_T::PWMEADCTS: TRGEN Position */ +#define TIMER_PWMEADCTS_TRGEN_Msk (0x1ul << TIMER_PWMEADCTS_TRGEN_Pos) /*!< TIMER_T::PWMEADCTS: TRGEN Mask */ + +#define TIMER_PWMSCTL_SYNCMODE_Pos (0) /*!< TIMER_T::PWMSCTL: SYNCMODE Position */ +#define TIMER_PWMSCTL_SYNCMODE_Msk (0x3ul << TIMER_PWMSCTL_SYNCMODE_Pos) /*!< TIMER_T::PWMSCTL: SYNCMODE Mask */ + +#define TIMER_PWMSCTL_SYNCSRC_Pos (8) /*!< TIMER_T::PWMSCTL: SYNCSRC Position */ +#define TIMER_PWMSCTL_SYNCSRC_Msk (0x7ul << TIMER_PWMSCTL_SYNCSRC_Pos) /*!< TIMER_T::PWMSCTL: SYNCSRC Mask */ + +#define TIMER_PWMSTRG_STRGEN_Pos (0) /*!< TIMER_T::PWMSTRG: STRGEN Position */ +#define TIMER_PWMSTRG_STRGEN_Msk (0x1ul << TIMER_PWMSTRG_STRGEN_Pos) /*!< TIMER_T::PWMSTRG: STRGEN Mask */ + +#define TIMER_PWMSTATUS_CNTMAXF_Pos (0) /*!< TIMER_T::PWMSTATUS: CNTMAXF Position */ +#define TIMER_PWMSTATUS_CNTMAXF_Msk (0x1ul << TIMER_PWMSTATUS_CNTMAXF_Pos) /*!< TIMER_T::PWMSTATUS: CNTMAXF Mask */ + +#define TIMER_PWMSTATUS_EADCTRGF_Pos (16) /*!< TIMER_T::PWMSTATUS: EADCTRGF Position */ +#define TIMER_PWMSTATUS_EADCTRGF_Msk (0x1ul << TIMER_PWMSTATUS_EADCTRGF_Pos) /*!< TIMER_T::PWMSTATUS: EADCTRGF Mask */ + +#define TIMER_PWMPBUF_PBUF_Pos (0) /*!< TIMER_T::PWMPBUF: PBUF Position */ +#define TIMER_PWMPBUF_PBUF_Msk (0xfffful << TIMER_PWMPBUF_PBUF_Pos) /*!< TIMER_T::PWMPBUF: PBUF Mask */ + +#define TIMER_PWMCMPBUF_CMPBUF_Pos (0) /*!< TIMER_T::PWMCMPBUF: CMPBUF Position */ +#define TIMER_PWMCMPBUF_CMPBUF_Msk (0xfffful << TIMER_PWMCMPBUF_CMPBUF_Pos) /*!< TIMER_T::PWMCMPBUF: CMPBUF Mask */ + +/**@}*/ /* TIMER_CONST */ +/**@}*/ /* end of TIMER register group */ +/**@}*/ /* end of REGISTER group */ + +#if defined ( __CC_ARM ) + #pragma no_anon_unions +#endif + +#endif /* __TIMER_REG_H__ */ diff --git a/bsp/nuvoton/libraries/ma35/Device/Nuvoton/MA35D1/Include/trng_reg.h b/bsp/nuvoton/libraries/ma35/Device/Nuvoton/MA35D1/Include/trng_reg.h new file mode 100644 index 0000000000..64ed957e56 --- /dev/null +++ b/bsp/nuvoton/libraries/ma35/Device/Nuvoton/MA35D1/Include/trng_reg.h @@ -0,0 +1,922 @@ +/**************************************************************************//** + * @file trng_reg.h + * @brief True Random Number Generator register definition header file + * + * SPDX-License-Identifier: Apache-2.0 + * @copyright (C) 2021 Nuvoton Technology Corp. All rights reserved. + *****************************************************************************/ +#ifndef __TRNG_REG_H__ +#define __TRNG_REG_H__ + +#if defined ( __CC_ARM ) + #pragma anon_unions +#endif + +/** + @addtogroup REGISTER Control Register + @{ +*/ + +/*---------------------- True Random Number Generator -------------------------*/ +/** + @addtogroup TRNG True Random Number Generator(TRNG) + Memory Mapped Structure for TRNG Controller +@{ */ + +typedef struct +{ + /** + * @var TRNG_T::CTL + * Offset: 0x00 The CTRL register is used to cause the TRNG NIST to execute one of a number of actions. + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[3:0] |CMD |Execute a Command + * | | |Enumerated values not listed are 'reserved'. + * | | |0000 = (NOP): Execute a NOP. + * | | |0001 = (GEN_NOISE): Generate full-entropy seed from noise. + * | | |0010 = (GEN_NONCE): Generate seed from host-written nonce. + * | | |0011 = (CREATE_STATE): Move DRBG to create state. + * | | |0100 = (RENEW_STATE): Move DRBG to renew state. + * | | |0101 = (REFRESH_ADDIN): Move DRBG to refresh addin. + * | | |0110 = (GEN_RANDOM): Generate a random number. + * | | |0111 = (ADVANCE_STATE): Advance DRBG state. + * | | |1000 = (RUN_KAT): Run KAT on DRBG or entropy source. + * | | |1111 = (ZEROIZE): Zeroize. + * @var TRNG_T::MODE + * Offset: 0x04 The MODE register is used to enable or disable certain run-time features within the TRNG NIST. + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[0] |SEC_ALG |Select Security Strength in DRBG + * | | |0 = (SEC_128): AES-128. + * | | |1 = (SEC_256): AES-256. + * |[3] |PRED_RESIST|Prediction Resistance + * | | |0 = (PRED_DISABLE): Prediction resistance is not required. + * | | |1 = (PRED_ENABLED): Prediction resistance is required. + * |[4] |ADDIN_PRESENT|Availability of the Additional Input + * | | |0 = (ADDIN_NOT_REQ): No Additional Input required from host. + * | | |1 = (ADDIN_REQ): Additional input must be provided by host. + * |[6:5] |KAT_VEC |Select Test Vectors for Known-answer Test + * | | |00 = (KAT_VEC0): KAT vector 0. + * | | |01 = (KAT_VEC1): KAT vector 1. + * | | |10 = (KAT_VEC2): KAT vector 2. + * | | |11 = (KAT_ALL): Run all 3 KAT vectors. + * |[8:7] |KAT_SEL |Select Test Component for Known-answer Test + * | | |00 = (KAT_DRBG): KAT on DRBG. + * | | |01 = (KAT_DF): KAT on conditioning component (Derivation Function). + * | | |10 = (KAT_BOTH): KAT on both DRBG and DF. + * | | |11 = Reserved. + * @var TRNG_T::SMODE + * Offset: 0x08 The SMODE register is used to enable or disable certain MISSION mode run-time features. + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[0] |NONCE |Set the Core in Nonce Seeding Mode + * | | |0 = (NONCE_DISABLED): Disable nonce mode. + * | | |1 = (NONCE_ENABLED): Enable nonce mode. + * |[1] |MISSION_MODE|Operating Mode + * | | |0 = (RST_TEST_MODE): test mode. + * | | |1 = (RST_MISSION_MODE): mission mode. + * | | |Note: Any change to the state of this field (1 to 0 or 0 to 1) causes the TRNG NIST to zeroize itself. + * |[9:2] |MAX_REJECTS|Maximum Number of Consecutive Bit Rejections Before Issuing Ring Tweak + * | | |Default is to 10 (0xa). + * |[23:16] |INDIV_HT_DISABLE|Statistical Health Tests Individually + * | | |0 = Disable. + * | | |1 = Enable. + * | | |INDIV_HT_DISABLE[0] = Repetition Count test on raw entropy. + * | | |INDIV_HT_DISABLE[1] = Adaptive Proportion test on raw entropy. + * | | |INDIV_HT_DISABLE[2] = Monobit test on raw entropy. + * | | |INDIV_HT_DISABLE[3] = Poker test on raw entropy. + * | | |INDIV_HT_DISABLE[4] = Run test on raw entropy. + * | | |INDIV_HT_DISABLE[5] = Long Run test on raw entropy. + * | | |INDIV_HT_DISABLE[6] = Auto-correlation test on raw entropy. + * | | |INDIV_HT_DISABLE[7] = Repetition Count test on entropy source output. + * | | |Note: Users only can enable/disable statistical health test in TEST mode + * | | |This field cannot change in MISSION mode and its value is always 0 in MISSION mode. + * |[31] |NOISE_COLLECT|Raw Noise Collection Mode + * | | |0 = Disable. + * | | |1 = Enable. + * | | |Note: Users only can enable/disable raw noise collection in TEST mode + * | | |This bit cannot be set to 1 in MISSION mode. + * @var TRNG_T::STAT + * Offset: 0x0C The STAT register allows the user to monitor the internal status of the TRNG NIST. + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[3:0] |LAST_CMD |Last Command + * | | |0000 = (NOP). + * | | |0001 = (GEN_NOISE). + * | | |0011 = (GEN_NONCE). + * | | |0011 = (CREATE_STATE). + * | | |0100 = (RENEW_STATE). + * | | |0101 = (REFRESH_ADDIN). + * | | |0110 = (GEN_RANDOM). + * | | |0111 = (ADVANCE_STATE). + * | | |1000 = (RUN_KAT). + * | | |1111 = (ZEROIZE). + * | | |Others = Reserved. + * |[4] |SEC_ALG |Reflects State of MODE.SEC_ALG + * | | |0 = (SEC_ALG_0): Maximum security strength set to 128. + * | | |1 =(SEC_ALG_1): Maximum security strength set to 256. + * |[5] |NONCE_MODE|Reflects State of SMODE.NONCE + * | | |0 = (NONCE_DISABLE): Nonce mode disabled. + * | | |1 = (NONCE_ENABLE): Nonce mode enabled (allows CTRL.CMD value of 2). + * |[6] |MISSION_MODE|Reflects State of SMODE.MISSION_MODE + * | | |0 = (SEC_MODE_MISSION): Core is in TEST mode. + * | | |1 = (SEC_MODE_TEST): Core is in MISSION mode. + * |[8:7] |DRBG_STATE|Reflects How a DRBG State Is Instantiated + * | | |00 = (DRBG_NOT_INIT): State is not instantiated. + * | | |01 = (DRBG_NS): State is instantiated using the built-in noise source. + * | | |10 = (DRBG_HOST): State is instantiated using the host-provided nonce. + * | | |11 = Reserved. + * |[9] |STARTUP_TEST_STUCK|Indicates Whether the Startup Test Is Stuck + * | | |0 = (STARTUP_TEST_NOT_STUCK): Startup test is not stuck (yet). + * | | |1 = (STARTUP_TEST_IS_STUCK): Startup test is highly likely stuck. + * | | |Note: Only valid when sticky startup test feature Is enabled. + * |[10] |STARTUP_TEST_IN_PROG|Indicates Whether the Startup Test Is in Progress + * | | |0 = (STARTUP_TEST_NOT_STUCK): Startup test is finished. + * | | |1 = (STARTUP_TEST_IS_STUCK): Startup test is in progress. + * |[31] |BUSY |State of the Core + * | | |0 = (BUSY_NOT): Idle. + * | | |1 = (BUSY_EXEC): Currently executing a command. + * @var TRNG_T::IE + * Offset: 0x10 The IE register is used to enable or disable interrupts within the TRNG NIST. + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[0] |ZEROIZED |Include or Exclude ZEROIZED Interrupt Contribution + * | | |0 = (ZEROIZED_DIS): Disable ZEROIZED interrupt contribution. + * | | |1 = (ZEROIZED_EN): Enable ZEROIZED interrupt contribution. + * |[1] |KAT_COMPLETED|Include or Exclude KAT_COMPLETED Interrupt Contribution + * | | |0 = (KAT_COMPLETED_DIS): Disable KAT_COMPLETED interrupt contribution. + * | | |1 = (KAT_COMPLETED_EN): Enable KAT_COMPLETED interrupt contribution. + * |[2] |NOISE_RDY |Include or Exclude NOISE_RDY Interrupt Contribution + * | | |0 = (NOISE_RDY_DIS): Disable NOISE_RDY interrupt contribution. + * | | |1 = (NOISE_RDY_EN): Enable NOISE_RDY interrupt contribution. + * |[3] |ALARMS |Include or Exclude ALARMS Interrupt Contribution + * | | |0 = (ALARMS_DIS): Disable ALARMS interrupt contribution. + * | | |1 = (ALARMS_EN): Enable ALARMS interrupt contribution. + * |[4] |DONE |Include or Exclude DONE Interrupt Contribution + * | | |0 = (DONE_DIS): Disable DONE interrupt contribution. + * | | |1 = (DONE_EN): Enable DONE interrupt contribution. + * |[31] |GLBL |Global Interrupt Enable Signal for the TRNG NIST + * | | |0 = (GLBL_DIS): Disable GLBL interrupt contribution. + * | | |1 = (GLBL_EN): Enable GLBL interrupt contribution. + * @var TRNG_T::ISTAT + * Offset: 0x14 The ISTAT register allows the user to monitor the interrupt contributions of the TRNG NIST. + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[0] |ZEROIZED |ZEROIZED Flag + * | | |Indicates the Completion of the ZEROIZE Operation + * | | |0 = (ZEROIZED_R0): R0: No unacknowledged ZEROIZED. + * | | | (ZEROIZED_W0): W0: NOP. + * | | |1 = (ZEROIZED_R1): R1: Unacknowledged ZEROIZED. + * | | | (ZEROIZED_W1): W1: Clear ZEROIZED flag. + * |[1] |KAT_COMPLETED|KAT_COMPLETED Flag + * | | |Indicates the Completion of the RUN_KAT Command + * | | |0 = (KAT_COMPLETED_R0): R0: No unacknowledged KAT_COMPLETED. + * | | | (KAT_COMPLETED_W0): W0: NOP. + * | | |1 = (KAT_COMPLETED_R1): R1: Unacknowledged KAT_COMPLETED. + * | | | (KAT_COMPLETED_W1): W1: Clear KAT_COMPLETED flag. + * |[2] |NOISE_RDY |NOISE_RDY Flag + * | | |When TRNG NIST is generating a full-entropy seed in the self-seeding mode, MISSION_MODE(TRNG_SMODE[1]) is 0 (TEST mode) and SMODE.NOISE_COLLECT is set to 1, the NOISE_RDY bit informs the user when 512 bits of noise have been generated + * | | |This interrupt never happens in the MISSION mode of operation. + * | | |0 = (NOISE_RDY_R0): R0: No unacknowledged noise generation completion. + * | | | (NOISE_RDY_W0): W0: NOP. + * | | |1 = (NOISE_RDY_R1): R1: Unacknowledged noise generation completion. + * | | | (NOISE_RDY_W1): W1: Clear NOISE_RDY flag. + * |[3] |ALARMS |ALARMS Flag + * | | |The ALARMS bit allows the user to poll failures + * | | |When an alarm occurs, an automatic zeroize happens + * | | |Clearing this interrupt also clears the O_alarm pin. + * | | |0 = (ALARMS_R0): R0: No unacknowledged ALARMS. + * | | | (ALARMS_W0): W0: NOP. + * | | |1 = (ALARMS_R1): R1: Unacknowledged ALARMS. + * | | | (ALARMS_W1): W1: Clear ALARMS flag. + * |[4] |DONE |DONE Flag + * | | |The DONE bit allows the user to poll the completion of all commands except RUN_KAT and ZEROIZE which have their own interrupt. + * | | |0 = (DONE_R0): R0: No unacknowledged command completion. + * | | | (DONE_W0): W0: NOP. + * | | |1 = (DONE_R1): R1: Unacknowledged command completion. + * | | | (DONE_W1): W1: Clear DONE flag. + * @var TRNG_T::ALARMS + * Offset: 0x18 The ALARMS register allows the user to monitor the source of critical alarms. + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[3:0] |FAILED_TEST_ID|FAILED_TEST_ID Error Flag + * | | |When an alarm is issued, the FAILED_TEST_ID field shows which test has failed + * | | |This fields only shows the first detected failed test and it should not be assumed that the remaining statistical tests are passed. + * | | |0000 = (FAILED_TEST_ID_0): no failure. + * | | |0001 = (FAILED_TEST_ID_1): failure in both KAT and statistical tests. + * | | |0010 = (FAILED_TEST_ID_2): KAT test failure. + * | | |0011 = (FAILED_TEST_ID_3): Monobit test failure. + * | | |0100 = (FAILED_TEST_ID_4): Run test failure. + * | | |0101 = (FAILED_TEST_ID_5): Long Run test failure. + * | | |0110 = (FAILED_TEST_ID_6): Auto-correlation test failure. + * | | |0111 = (FAILED_TEST_ID_7): Poker test failure. + * | | |1000 = (FAILED_TEST_ID_8): Repetition Count test failure. + * | | |1001 = (FAILED_TEST_ID_9): Adaptive Proportion test failure. + * | | |Others = Reserved. + * |[4] |ILLEGAL_CMD_SEQ|ILLEGAL_CMD_SEQ Error Flag + * | | |The ILLEGAL_CMD_SEQ field indicates that the SOFTWARE Driver has executed an illegal command sequence. + * | | |0 = (ILLEGAL_CMD_SEQ _0): no failure. + * | | |1 = (ILLEGAL_CMD_SEQ _1): Executed an illegal command sequence. + * |[5] |FAILED_SEED_ST_HT|FAILED_SEED_ST_HT Error Flag + * | | |The FAILED_SEED_ST_HT field indicates that the statistical tests applied on the entropy source output is failed (Only valid when entropy source output statistical health test feature is included). + * | | |0 = (FAILED_SEED_ST_HT_0): no failure. + * | | |1 = (FAILED_SEED_ST_HT_1): Entropy source health test is failed. + * @var TRNG_T::COREKIT_REL + * Offset: 0x1C Contains the static coreKit release information. + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[15:0] |REL_NUM |The CoreKit Release Version In Pseudo-BCD + * | | |For example, release '2.35e-lca04' is encoded as 0x235e. + * | | |This TRNG version is 0x300a. + * |[23:16] |EXT_VER |The CoreKit Release Extension Version Number + * | | |For example, release '2.35e-lp04' is encoded as 0x4. + * | | |GA releases has a value of 0. + * |[31:28] |EXT_ENUM |The CoreKit Release Extension Type + * | | |For example, release '2.35e-lca04' is encoded as 0x1. + * | | |0000 = (EXT_ENUM_GA): GA release. + * | | |0001 = (EXT_ENUM_LCA): LCA release. + * | | |0010 = (EXT_ENUM_EA): EA release. + * | | |0011 = (EXT_ENUM_LP): LP release. + * | | |0100 = (EXT_ENUM_LPC): LPC release. + * | | |0101 = (EXT_ENUM_SOW): SOW release. + * | | |Others = Reserved. + * @var TRNG_T::FEATURES + * Offset: 0x20 The FEATURES register returns the state of various build-time parameter values. + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[0] |SECURE_RST_STATE|The Core Resets to MISSION or TEST Mode + * | | |0 = test mode. + * | | |1 = mission mode. + * |[3:1] |DIAG_LEVEL_ST_HLT|Level Of Diagnostic Circuitry For The Health Test + * |[6:4] |DIAG_LEVEL_CLP800|Level Of Diagnostic Circuitry For TRNG When Noise Source + * |[7] |DIAG_LEVEL_NS|Level Of Diagnostic Circuitry For Noise Source Output Registers + * |[8] |PS_PRESENT|The NPA_DATAx Registers Is used As A Personalization String During The Create_State Command + * | | |0 = No. + * | | |1 = Yes. + * |[9] |AES_256 |The Instantiated AES + * | | |0 = AES-128. + * | | |1 = AES-256. + * @var TRNG_T::RAND0 + * Offset: 0x24 The RAND0 register is used by the host to read bits [31:0] of the newly generated 128-bit random data. + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[31:0] |RAND |Random Data Word + * @var TRNG_T::RAND1 + * Offset: 0x28 The RAND1 register is used by the host to read bits [63:32] of the newly generated 128-bit random data. + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[31:0] |RAND |Random Data Word + * @var TRNG_T::RAND2 + * Offset: 0x2C The RAND2 register is used by the host to read bits [95:64] of the newly generated 128-bit random data. + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[31:0] |RAND |Random Data Word + * @var TRNG_T::RAND3 + * Offset: 0x30 The RAND3 register is used by the host to read bits [127:96] of the newly generated 128-bit random data. + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[31:0] |RAND |Random Data Word + * @var TRNG_T::NPA_DATA0 + * Offset: 0x34 The NPA_DATA0 register holds Noise/Nonce/Personalization String/Additional Input - bits [31:0]. + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[31:0] |NPA_DATA |NPA data word + * | | |Noise/Nonce can be stored in register NPA_DATA0 ~ NPA_DATA15. + * | | |Personalization String/Additional Input can be stored in register NPA_DATA0 ~ NPA_DATA11. + * @var TRNG_T::NPA_DATA1 + * Offset: 0x38 The NPA_DATA1 register holds Noise/Nonce/Personalization String/Additional Input - bits [63:32]. + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[31:0] |NPA_DATA |NPA data word + * | | |Noise/Nonce can be stored in register NPA_DATA0 ~ NPA_DATA15. + * | | |Personalization String/Additional Input can be stored in register NPA_DATA0 ~ NPA_DATA11. + * @var TRNG_T::NPA_DATA2 + * Offset: 0x3C The NPA_DATA2 register holds Noise/Nonce/Personalization String/Additional Input - bits [95:64]. + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[31:0] |NPA_DATA |NPA data word + * | | |Noise/Nonce can be stored in register NPA_DATA0 ~ NPA_DATA15. + * | | |Personalization String/Additional Input can be stored in register NPA_DATA0 ~ NPA_DATA11. + * @var TRNG_T::NPA_DATA3 + * Offset: 0x40 The NPA_DATA3 register holds Noise/Nonce/Personalization String/Additional Input - bits [127:96]. + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[31:0] |NPA_DATA |NPA data word + * | | |Noise/Nonce can be stored in register NPA_DATA0 ~ NPA_DATA15. + * | | |Personalization String/Additional Input can be stored in register NPA_DATA0 ~ NPA_DATA11. + * @var TRNG_T::NPA_DATA4 + * Offset: 0x44 The NPA_DATA4 register holds Noise/Nonce/Personalization String/Additional Input - bits [159:128]. + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[31:0] |NPA_DATA |NPA data word + * | | |Noise/Nonce can be stored in register NPA_DATA0 ~ NPA_DATA15. + * | | |Personalization String/Additional Input can be stored in register NPA_DATA0 ~ NPA_DATA11. + * @var TRNG_T::NPA_DATA5 + * Offset: 0x48 The NPA_DATA5 register holds Noise/Nonce/Personalization String/Additional Input - bits [191:160]. + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[31:0] |NPA_DATA |NPA data word + * | | |Noise/Nonce can be stored in register NPA_DATA0 ~ NPA_DATA15. + * | | |Personalization String/Additional Input can be stored in register NPA_DATA0 ~ NPA_DATA11. + * @var TRNG_T::NPA_DATA6 + * Offset: 0x4C The NPA_DATA6 register holds Noise/Nonce/Personalization String/Additional Input - bits [223:192]. + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[31:0] |NPA_DATA |NPA data word + * | | |Noise/Nonce can be stored in register NPA_DATA0 ~ NPA_DATA15. + * | | |Personalization String/Additional Input can be stored in register NPA_DATA0 ~ NPA_DATA11. + * @var TRNG_T::NPA_DATA7 + * Offset: 0x50 The NPA_DATA7 register holds Noise/Nonce/Personalization String/Additional Input - bits [255:224]. + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[31:0] |NPA_DATA |NPA data word + * | | |Noise/Nonce can be stored in register NPA_DATA0 ~ NPA_DATA15. + * | | |Personalization String/Additional Input can be stored in register NPA_DATA0 ~ NPA_DATA11. + * @var TRNG_T::NPA_DATA8 + * Offset: 0x54 The NPA_DATA8 register holds Noise/Nonce/Personalization String/Additional Input - bits [287:256]. + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[31:0] |NPA_DATA |NPA data word + * | | |Noise/Nonce can be stored in register NPA_DATA0 ~ NPA_DATA15. + * | | |Personalization String/Additional Input can be stored in register NPA_DATA0 ~ NPA_DATA11. + * @var TRNG_T::NPA_DATA9 + * Offset: 0x58 The NPA_DATA9 register holds Noise/Nonce/Personalization String/Additional Input - bits [319:288]. + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[31:0] |NPA_DATA |NPA data word + * | | |Noise/Nonce can be stored in register NPA_DATA0 ~ NPA_DATA15. + * | | |Personalization String/Additional Input can be stored in register NPA_DATA0 ~ NPA_DATA11. + * @var TRNG_T::NPA_DATA10 + * Offset: 0x5C The NPA_DATA10 register holds Noise/Nonce/Personalization String/Additional Input - bits [351:320]. + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[31:0] |NPA_DATA |NPA data word + * | | |Noise/Nonce can be stored in register NPA_DATA0 ~ NPA_DATA15. + * | | |Personalization String/Additional Input can be stored in register NPA_DATA0 ~ NPA_DATA11. + * @var TRNG_T::NPA_DATA11 + * Offset: 0x60 The NPA_DATA11 register holds Noise/Nonce/Personalization String/Additional Input - bits [383:352]. + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[31:0] |NPA_DATA |NPA data word + * | | |Noise/Nonce can be stored in register NPA_DATA0 ~ NPA_DATA15. + * | | |Personalization String/Additional Input can be stored in register NPA_DATA0 ~ NPA_DATA11. + * @var TRNG_T::NPA_DATA12 + * Offset: 0x64 The NPA_DATA12 register holds Noise/Nonce - bits [415:384]. + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[31:0] |NPA_DATA |NPA data word + * | | |Noise/Nonce can be stored in register NPA_DATA0 ~ NPA_DATA15. + * | | |Personalization String/Additional Input can be stored in register NPA_DATA0 ~ NPA_DATA11. + * @var TRNG_T::NPA_DATA13 + * Offset: 0x68 The NPA_DATA13 register holds Noise/Nonce - bits [447:416]. + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[31:0] |NPA_DATA |NPA data word + * | | |Noise/Nonce can be stored in register NPA_DATA0 ~ NPA_DATA15. + * | | |Personalization String/Additional Input can be stored in register NPA_DATA0 ~ NPA_DATA11. + * @var TRNG_T::NPA_DATA14 + * Offset: 0x6C The NPA_DATA14 register holds Noise/Nonce - bits [479:448]. + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[31:0] |NPA_DATA |NPA data word + * | | |Noise/Nonce can be stored in register NPA_DATA0 ~ NPA_DATA15. + * | | |Personalization String/Additional Input can be stored in register NPA_DATA0 ~ NPA_DATA11. + * @var TRNG_T::NPA_DATA15 + * Offset: 0x70 The NPA_DATA15 register holds Noise/Nonce - bits [511:480]. + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[31:0] |NPA_DATA |NPA data word + * | | |Noise/Nonce can be stored in register NPA_DATA0 ~ NPA_DATA15. + * | | |Personalization String/Additional Input can be stored in register NPA_DATA0 ~ NPA_DATA11. + * @var TRNG_T::SEED0 + * Offset: 0x74 The SEED0 register holds seed value used in the DRBG - bits [31:0]. + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[31:0] |SEED |SEED data word + * @var TRNG_T::SEED1 + * Offset: 0x78 The SEED1 register holds seed value used in the DRBG - bits [63:32]. + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[31:0] |SEED |SEED data word + * @var TRNG_T::SEED2 + * Offset: 0x7C The SEED2 register holds seed value used in the DRBG - bits [95:64]. + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[31:0] |SEED |SEED data word + * @var TRNG_T::SEED3 + * Offset: 0x80 The SEED3 register holds seed value used in the DRBG - bits [127:96]. + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[31:0] |SEED |SEED data word + * @var TRNG_T::SEED4 + * Offset: 0x84 The SEED4 register holds seed value used in the DRBG - bits [159:128]. + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[31:0] |SEED |SEED data word + * @var TRNG_T::SEED5 + * Offset: 0x88 The SEED5 register holds seed value used in the DRBG - bits [191:160]. + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[31:0] |SEED |SEED data word + * @var TRNG_T::SEED6 + * Offset: 0x8C The SEED6 register holds seed value used in the DRBG - bits [223:192]. + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[31:0] |SEED |SEED data word + * @var TRNG_T::SEED7 + * Offset: 0x90 The SEED7 register holds seed value used in the DRBG - bits [255:224]. + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[31:0] |SEED |SEED data word + * @var TRNG_T::SEED8 + * Offset: 0x94 The SEED8 register holds seed value used in the DRBG - bits [287:256]. + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[31:0] |SEED |SEED data word + * @var TRNG_T::SEED9 + * Offset: 0x98 The SEED9 register holds seed value used in the DRBG - bits [319:288]. + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[31:0] |SEED |SEED data word + * @var TRNG_T::SEED10 + * Offset: 0x9C The SEED10 register holds seed value used in the DRBG - bits [351:320]. + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[31:0] |SEED |SEED data word + * @var TRNG_T::SEED11 + * Offset: 0xA0 The SEED11 register holds seed value used in the DRBG - bits [383:352]. + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[31:0] |SEED |SEED data word + * @var TRNG_T::TIME_TO_SEED + * Offset: 0xD0 The Time-to-Seed (TTS) register records the number of clock cycles taken to collect the set of raw noise bits used by the previous GEN_NOISE command. + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[31:0] |TTS |TRNG Time To Seed Shows the number of system clock cycles taken to generate raw noise for the last GEN_NOISE command. + * @var TRNG_T::BUILD_CFG0 + * Offset: 0xF0 Contains build-time TRNG NIST parameter settings. + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[1:0] |CORE_TYPE |Core Type + * | | |00 = (CORE_TYPE_BASE_TRNG): TRNG. + * | | |01 = (CORE_TYPE_BASE_TRNG_WITH_ESM_NONCE): TRNG with ESM nonce I/O. + * | | |10 = (CORE_TYPE_NIST_TRNG): TRNG NIST. + * | | |11 = (CORE_TYPE_NIST_TRNG_WITH_EDU): TRNG NIST with EDU. + * |[7] |BG8 |Indicates Number Of Bit Generators Present + * | | |0 = (SIX_BGS): 6 Bit Generators present. + * | | |1 = (EIGHT_BGS): 8 Bit Generators present.. + * |[9:8] |CDC_SYNC_DEPTH|Depth Of The CDC Resynchronizer Chains + * | | |00 = (CDC_RESYNC_4): CDC resynchronizer depth 4. + * | | |01 = Reserved. + * | | |10 = (CDC_RESYNC_2): CDC resynchronizer depth 2. + * | | |11 = (CDC_RESYNC_3): CDC resynchronizer depth 3. + * |[10] |BACKGROUND_NOISE|Indicates Background Noise Collection Is Present + * | | |0 = (BACKGROUND_NOISE _NOT_PRESENT): not present. + * | | |1 = (BACKGROUND_NOISE_PRESENT): present.. + * |[11] |EDU_PRESENT|Indicates EDU Is Present + * | | |0 = (EDU_PRESENT_NOT_PRESENT): not present. + * | | |1 = (EDU_PRESENT_PRESENT): present.. + * |[12] |AES_DATAPATH|AES Datapath Width + * | | |0 = (AES_DATAPATH_32): 32-bit datapath. + * | | |1 = (AES_DATAPATH_128): 128-bit datapath. + * |[13] |AES_MAX_KEY_SIZE|AES Max Key Size + * | | |0 = (AES_MAX_KEY_SIZE_128): 128-bit key. + * | | |1 = (AES_MAX_KEY_SIZE_256): 256-bit key. + * |[14] |PERSONALIZATION_STR|Personalization String Used + * | | |0 = (PS_NOT_PRESENT): not present. + * | | |1 = (PS_PRESENT): present. + * @var TRNG_T::BUILD_CFG1 + * Offset: 0xF4 Contains additional build-time TRNG NIST parameter settings. + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[7:0] |NUM_RAW_NOISE_BLKS|Number of Raw Noise Blocks Used for Start-up Test + * |[8] |STICKY_STARTUP|Sticky-startup Test Present + * | | |0 = (STICKY_STARTUP_TEST_NOT_PRESENT): not present. + * | | |1 = (STICKY_STARTUP_TEST_PRESENT): present. + * |[12] |AUTO_CORRELATION_TEST|Auto-correlation Test Present + * | | |0 = (AUTO_CORRELATION_TEST_NOT_PRESENT): not present. + * | | |1 = (AUTO_CORRELATION_TEST_PRESENT): present. + * |[13] |MONOBIT_TEST|Monobit Test Present + * | | |0 = (MONOBIT_TEST_NOT_PRESENT): not present. + * | | |1 = (MONOBIT_TEST_PRESENT): present. + * |[14] |RUN_TEST |Run Test Present + * | | |0 = (RUN_TEST_NOT_PRESENT): not present. + * | | |1 = (RUN_TEST_PRESENT): present. + * |[15] |POKER_TEST|Poker Test Present + * | | |0 = (POKER_TEST_NOT_PRESENT): not present. + * | | |1 = (POKER_TEST_PRESENT): present. + * |[18:16] |RAW_HT_ADAP_TEST|Raw Health Adaptive Proportion Test + * | | |000 = (RAW_HT_ADAP_TEST_NOT_PRESENT): not present. + * | | |001 = (RAW_HT_ADAP_TEST_1K_SAMPLES): 1k samples per window. + * | | |010 = (RAW_HT_ADAP_TEST_2K_SAMPLES): 2k samples per window. + * | | |011 = (RAW_HT_ADAP_TEST_4K_SAMPLES): 4k samples per window. + * | | |100 = (RAW_HT_ADAP_TEST_8K_SAMPLES): 8k samples per window. + * | | |101 = (RAW_HT_ADAP_TEST_16K_SAMPLES): 16k samples per window. + * | | |110 = (RAW_HT_ADAP_TEST_32K_SAMPLES): 32k samples per window. + * | | |111 = (RAW_HT_ADAP_TEST_64K_SAMPLES): 64k samples per window. + * |[19] |RAW_HT_REP_TEST|Raw Health Repetition Test Present + * | | |0 = (RAW_HT_REP_TEST_NOT_PRESENT): not present. + * | | |1 = (RAW_HT_REP_TEST_PRESENT): present. + * |[22:20] |ENT_SRC_REP_SMPL_SIZE|Entropy Source: Sample Size + * | | |000 = (ENT_SRC_REP_SMPL_SIZE_1): Sample size 1. + * | | |001 = (ENT_SRC_REP_SMPL_SIZE_2): Sample size 2. + * | | |010 = (ENT_SRC_REP_SMPL_SIZE_4): Sample size 4. + * | | |011 = (ENT_SRC_REP_SMPL_SIZE_8): Sample size 8. + * | | |100 = (ENT_SRC_REP_SMPL_SIZE_16): Sample size 16. + * | | |101 = (ENT_SRC_REP_SMPL_SIZE_32): Sample size 32. + * | | |110 = (ENT_SRC_REP_SMPL_SIZE_64): Sample size 64. + * | | |111 = (ENT_SRC_REP_SMPL_SIZE_128): Sample size 128. + * |[23] |ENT_SRC_REP_TEST|Entropy Source Repetition Test Present + * | | |0 = (ENT_SRC_REP_TEST_NOT_PRESENT): not present. + * | | |1 = (ENT_SRC_REP_TEST_PRESENT): present. + * |[30:24] |ENT_SRC_REP_MIN_ENTROPY|Entropy Source Repetition Minimum Entropy Per Bit + */ + __O uint32_t CTL; /*!< [0x0000] The CTRL register is used to cause the TRNG NIST to execute one of a number of actions. */ + __IO uint32_t MODE; /*!< [0x0004] The MODE register is used to enable or disable certain run-time features within the TRNG NIST. */ + __IO uint32_t SMODE; /*!< [0x0008] The SMODE register is used to enable or disable certain MISSION mode run-time features. */ + __I uint32_t STAT; /*!< [0x000c] The STAT register allows the user to monitor the internal status of the TRNG NIST. */ + __IO uint32_t IE; /*!< [0x0010] The IE register is used to enable or disable interrupts within the TRNG NIST. */ + __IO uint32_t ISTAT; /*!< [0x0014] The ISTAT register allows the user to monitor the interrupt contributions of the TRNG NIST. */ + __IO uint32_t ALARMS; /*!< [0x0018] The ALARMS register allows the user to monitor the source of critical alarms. */ + __I uint32_t COREKIT_REL; /*!< [0x001c] Contains the static coreKit release information. */ + __I uint32_t FEATURES; /*!< [0x0020] The FEATURES register returns the state of various build-time parameter values. */ + __I uint32_t RAND0; /*!< [0x0024] The RAND0 register is used by the host to read bits [31:0] of the newly generated 128-bit random data. */ + __I uint32_t RAND1; /*!< [0x0028] The RAND1 register is used by the host to read bits [63:32] of the newly generated 128-bit random data. */ + __I uint32_t RAND2; /*!< [0x002c] The RAND2 register is used by the host to read bits [95:64] of the newly generated 128-bit random data. */ + __I uint32_t RAND3; /*!< [0x0030] The RAND3 register is used by the host to read bits [127:96] of the newly generated 128-bit random data. */ + __IO uint32_t NPA_DATA0; /*!< [0x0034] The NPA_DATA0 register holds Noise/Nonce/Personalization String/Additional Input - bits [31:0]. */ + __IO uint32_t NPA_DATA1; /*!< [0x0038] The NPA_DATA1 register holds Noise/Nonce/Personalization String/Additional Input - bits [63:32]. */ + __IO uint32_t NPA_DATA2; /*!< [0x003c] The NPA_DATA2 register holds Noise/Nonce/Personalization String/Additional Input - bits [95:64]. */ + __IO uint32_t NPA_DATA3; /*!< [0x0040] The NPA_DATA3 register holds Noise/Nonce/Personalization String/Additional Input - bits [127:96]. */ + __IO uint32_t NPA_DATA4; /*!< [0x0044] The NPA_DATA4 register holds Noise/Nonce/Personalization String/Additional Input - bits [159:128]. */ + __IO uint32_t NPA_DATA5; /*!< [0x0048] The NPA_DATA5 register holds Noise/Nonce/Personalization String/Additional Input - bits [191:160]. */ + __IO uint32_t NPA_DATA6; /*!< [0x004c] The NPA_DATA6 register holds Noise/Nonce/Personalization String/Additional Input - bits [223:192]. */ + __IO uint32_t NPA_DATA7; /*!< [0x0050] The NPA_DATA7 register holds Noise/Nonce/Personalization String/Additional Input - bits [255:224]. */ + __IO uint32_t NPA_DATA8; /*!< [0x0054] The NPA_DATA8 register holds Noise/Nonce/Personalization String/Additional Input - bits [287:256]. */ + __IO uint32_t NPA_DATA9; /*!< [0x0058] The NPA_DATA9 register holds Noise/Nonce/Personalization String/Additional Input - bits [319:288]. */ + __IO uint32_t NPA_DATA10; /*!< [0x005c] The NPA_DATA10 register holds Noise/Nonce/Personalization String/Additional Input - bits [351:320]. */ + __IO uint32_t NPA_DATA11; /*!< [0x0060] The NPA_DATA11 register holds Noise/Nonce/Personalization String/Additional Input - bits [383:352]. */ + __IO uint32_t NPA_DATA12; /*!< [0x0064] The NPA_DATA12 register holds Noise/Nonce - bits [415:384]. */ + __IO uint32_t NPA_DATA13; /*!< [0x0068] The NPA_DATA13 register holds Noise/Nonce - bits [447:416]. */ + __IO uint32_t NPA_DATA14; /*!< [0x006c] The NPA_DATA14 register holds Noise/Nonce - bits [479:448]. */ + __IO uint32_t NPA_DATA15; /*!< [0x0070] The NPA_DATA15 register holds Noise/Nonce - bits [511:480]. */ + __IO uint32_t SEED0; /*!< [0x0074] The SEED0 register holds seed value used in the DRBG - bits [31:0]. */ + __IO uint32_t SEED1; /*!< [0x0078] The SEED1 register holds seed value used in the DRBG - bits [63:32]. */ + __IO uint32_t SEED2; /*!< [0x007c] The SEED2 register holds seed value used in the DRBG - bits [95:64]. */ + __IO uint32_t SEED3; /*!< [0x0080] The SEED3 register holds seed value used in the DRBG - bits [127:96]. */ + __IO uint32_t SEED4; /*!< [0x0084] The SEED4 register holds seed value used in the DRBG - bits [159:128]. */ + __IO uint32_t SEED5; /*!< [0x0088] The SEED5 register holds seed value used in the DRBG - bits [191:160]. */ + __IO uint32_t SEED6; /*!< [0x008c] The SEED6 register holds seed value used in the DRBG - bits [223:192]. */ + __IO uint32_t SEED7; /*!< [0x0090] The SEED7 register holds seed value used in the DRBG - bits [255:224]. */ + __IO uint32_t SEED8; /*!< [0x0094] The SEED8 register holds seed value used in the DRBG - bits [287:256]. */ + __IO uint32_t SEED9; /*!< [0x0098] The SEED9 register holds seed value used in the DRBG - bits [319:288]. */ + __IO uint32_t SEED10; /*!< [0x009c] The SEED10 register holds seed value used in the DRBG - bits [351:320]. */ + __IO uint32_t SEED11; /*!< [0x00a0] The SEED11 register holds seed value used in the DRBG - bits [383:352]. */ + __I uint32_t RESERVE0[11]; + __I uint32_t TIME_TO_SEED; /*!< [0x00d0] The Time-to-Seed (TTS) register records the number of clock cycles taken to collect the set of raw noise bits used by the previous GEN_NOISE command. */ + __I uint32_t RESERVE1[7]; + __I uint32_t BUILD_CFG0; /*!< [0x00f0] Contains build-time TRNG NIST parameter settings. */ + __I uint32_t BUILD_CFG1; /*!< [0x00f4] Contains additional build-time TRNG NIST parameter settings. */ + +} TRNG_T; + +/** + @addtogroup TRNG_CONST TRNG Bit Field Definition + Constant Definitions for TRNG Controller +@{ */ + +#define TRNG_CTL_CMD_Pos (0) /*!< TRNG_T::CTL: CMD Position */ +#define TRNG_CTL_CMD_Msk (0xful << TRNG_CTL_CMD_Pos) /*!< TRNG_T::CTL: CMD Mask */ + +#define TRNG_MODE_SEC_ALG_Pos (0) /*!< TRNG_T::MODE: SEC_ALG Position */ +#define TRNG_MODE_SEC_ALG_Msk (0x1ul << TRNG_MODE_SEC_ALG_Pos) /*!< TRNG_T::MODE: SEC_ALG Mask */ + +#define TRNG_MODE_PRED_RESIST_Pos (3) /*!< TRNG_T::MODE: PRED_RESIST Position */ +#define TRNG_MODE_PRED_RESIST_Msk (0x1ul << TRNG_MODE_PRED_RESIST_Pos) /*!< TRNG_T::MODE: PRED_RESIST Mask */ + +#define TRNG_MODE_ADDIN_PRESENT_Pos (4) /*!< TRNG_T::MODE: ADDIN_PRESENT Position */ +#define TRNG_MODE_ADDIN_PRESENT_Msk (0x1ul << TRNG_MODE_ADDIN_PRESENT_Pos) /*!< TRNG_T::MODE: ADDIN_PRESENT Mask */ + +#define TRNG_MODE_KAT_VEC_Pos (5) /*!< TRNG_T::MODE: KAT_VEC Position */ +#define TRNG_MODE_KAT_VEC_Msk (0x3ul << TRNG_MODE_KAT_VEC_Pos) /*!< TRNG_T::MODE: KAT_VEC Mask */ + +#define TRNG_MODE_KAT_SEL_Pos (7) /*!< TRNG_T::MODE: KAT_SEL Position */ +#define TRNG_MODE_KAT_SEL_Msk (0x3ul << TRNG_MODE_KAT_SEL_Pos) /*!< TRNG_T::MODE: KAT_SEL Mask */ + +#define TRNG_SMODE_NONCE_Pos (0) /*!< TRNG_T::SMODE: NONCE Position */ +#define TRNG_SMODE_NONCE_Msk (0x1ul << TRNG_SMODE_NONCE_Pos) /*!< TRNG_T::SMODE: NONCE Mask */ + +#define TRNG_SMODE_MISSION_MODE_Pos (1) /*!< TRNG_T::SMODE: MISSION_MODE Position */ +#define TRNG_SMODE_MISSION_MODE_Msk (0x1ul << TRNG_SMODE_MISSION_MODE_Pos) /*!< TRNG_T::SMODE: MISSION_MODE Mask */ + +#define TRNG_SMODE_MAX_REJECTS_Pos (2) /*!< TRNG_T::SMODE: MAX_REJECTS Position */ +#define TRNG_SMODE_MAX_REJECTS_Msk (0xfful << TRNG_SMODE_MAX_REJECTS_Pos) /*!< TRNG_T::SMODE: MAX_REJECTS Mask */ + +#define TRNG_SMODE_INDIV_HT_DISABLE_Pos (16) /*!< TRNG_T::SMODE: INDIV_HT_DISABLE Position*/ +#define TRNG_SMODE_INDIV_HT_DISABLE_Msk (0xfful << TRNG_SMODE_INDIV_HT_DISABLE_Pos) /*!< TRNG_T::SMODE: INDIV_HT_DISABLE Mask */ + +#define TRNG_SMODE_NOISE_COLLECT_Pos (31) /*!< TRNG_T::SMODE: NOISE_COLLECT Position */ +#define TRNG_SMODE_NOISE_COLLECT_Msk (0x1ul << TRNG_SMODE_NOISE_COLLECT_Pos) /*!< TRNG_T::SMODE: NOISE_COLLECT Mask */ + +#define TRNG_STAT_LAST_CMD_Pos (0) /*!< TRNG_T::STAT: LAST_CMD Position */ +#define TRNG_STAT_LAST_CMD_Msk (0xful << TRNG_STAT_LAST_CMD_Pos) /*!< TRNG_T::STAT: LAST_CMD Mask */ + +#define TRNG_STAT_SEC_ALG_Pos (4) /*!< TRNG_T::STAT: SEC_ALG Position */ +#define TRNG_STAT_SEC_ALG_Msk (0x1ul << TRNG_STAT_SEC_ALG_Pos) /*!< TRNG_T::STAT: SEC_ALG Mask */ + +#define TRNG_STAT_NONCE_MODE_Pos (5) /*!< TRNG_T::STAT: NONCE_MODE Position */ +#define TRNG_STAT_NONCE_MODE_Msk (0x1ul << TRNG_STAT_NONCE_MODE_Pos) /*!< TRNG_T::STAT: NONCE_MODE Mask */ + +#define TRNG_STAT_MISSION_MODE_Pos (6) /*!< TRNG_T::STAT: MISSION_MODE Position */ +#define TRNG_STAT_MISSION_MODE_Msk (0x1ul << TRNG_STAT_MISSION_MODE_Pos) /*!< TRNG_T::STAT: MISSION_MODE Mask */ + +#define TRNG_STAT_DRBG_STATE_Pos (7) /*!< TRNG_T::STAT: DRBG_STATE Position */ +#define TRNG_STAT_DRBG_STATE_Msk (0x3ul << TRNG_STAT_DRBG_STATE_Pos) /*!< TRNG_T::STAT: DRBG_STATE Mask */ + +#define TRNG_STAT_STARTUP_TEST_STUCK_Pos (9) /*!< TRNG_T::STAT: STARTUP_TEST_STUCK Position*/ +#define TRNG_STAT_STARTUP_TEST_STUCK_Msk (0x1ul << TRNG_STAT_STARTUP_TEST_STUCK_Pos) /*!< TRNG_T::STAT: STARTUP_TEST_STUCK Mask */ + +#define TRNG_STAT_STARTUP_TEST_IN_PROG_Pos (10) /*!< TRNG_T::STAT: STARTUP_TEST_IN_PROG Position*/ +#define TRNG_STAT_STARTUP_TEST_IN_PROG_Msk (0x1ul << TRNG_STAT_STARTUP_TEST_IN_PROG_Pos) /*!< TRNG_T::STAT: STARTUP_TEST_IN_PROG Mask*/ + +#define TRNG_STAT_BUSY_Pos (31) /*!< TRNG_T::STAT: BUSY Position */ +#define TRNG_STAT_BUSY_Msk (0x1ul << TRNG_STAT_BUSY_Pos) /*!< TRNG_T::STAT: BUSY Mask */ + +#define TRNG_IE_ZEROIZED_Pos (0) /*!< TRNG_T::IE: ZEROIZED Position */ +#define TRNG_IE_ZEROIZED_Msk (0x1ul << TRNG_IE_ZEROIZED_Pos) /*!< TRNG_T::IE: ZEROIZED Mask */ + +#define TRNG_IE_KAT_COMPLETED_Pos (1) /*!< TRNG_T::IE: KAT_COMPLETED Position */ +#define TRNG_IE_KAT_COMPLETED_Msk (0x1ul << TRNG_IE_KAT_COMPLETED_Pos) /*!< TRNG_T::IE: KAT_COMPLETED Mask */ + +#define TRNG_IE_NOISE_RDY_Pos (2) /*!< TRNG_T::IE: NOISE_RDY Position */ +#define TRNG_IE_NOISE_RDY_Msk (0x1ul << TRNG_IE_NOISE_RDY_Pos) /*!< TRNG_T::IE: NOISE_RDY Mask */ + +#define TRNG_IE_ALARMS_Pos (3) /*!< TRNG_T::IE: ALARMS Position */ +#define TRNG_IE_ALARMS_Msk (0x1ul << TRNG_IE_ALARMS_Pos) /*!< TRNG_T::IE: ALARMS Mask */ + +#define TRNG_IE_DONE_Pos (4) /*!< TRNG_T::IE: DONE Position */ +#define TRNG_IE_DONE_Msk (0x1ul << TRNG_IE_DONE_Pos) /*!< TRNG_T::IE: DONE Mask */ + +#define TRNG_IE_GLBL_Pos (31) /*!< TRNG_T::IE: GLBL Position */ +#define TRNG_IE_GLBL_Msk (0x1ul << TRNG_IE_GLBL_Pos) /*!< TRNG_T::IE: GLBL Mask */ + +#define TRNG_ISTAT_ZEROIZED_Pos (0) /*!< TRNG_T::ISTAT: ZEROIZED Position */ +#define TRNG_ISTAT_ZEROIZED_Msk (0x1ul << TRNG_ISTAT_ZEROIZED_Pos) /*!< TRNG_T::ISTAT: ZEROIZED Mask */ + +#define TRNG_ISTAT_KAT_COMPLETED_Pos (1) /*!< TRNG_T::ISTAT: KAT_COMPLETED Position */ +#define TRNG_ISTAT_KAT_COMPLETED_Msk (0x1ul << TRNG_ISTAT_KAT_COMPLETED_Pos) /*!< TRNG_T::ISTAT: KAT_COMPLETED Mask */ + +#define TRNG_ISTAT_NOISE_RDY_Pos (2) /*!< TRNG_T::ISTAT: NOISE_RDY Position */ +#define TRNG_ISTAT_NOISE_RDY_Msk (0x1ul << TRNG_ISTAT_NOISE_RDY_Pos) /*!< TRNG_T::ISTAT: NOISE_RDY Mask */ + +#define TRNG_ISTAT_ALARMS_Pos (3) /*!< TRNG_T::ISTAT: ALARMS Position */ +#define TRNG_ISTAT_ALARMS_Msk (0x1ul << TRNG_ISTAT_ALARMS_Pos) /*!< TRNG_T::ISTAT: ALARMS Mask */ + +#define TRNG_ISTAT_DONE_Pos (4) /*!< TRNG_T::ISTAT: DONE Position */ +#define TRNG_ISTAT_DONE_Msk (0x1ul << TRNG_ISTAT_DONE_Pos) /*!< TRNG_T::ISTAT: DONE Mask */ + +#define TRNG_ALARMS_FAILED_TEST_ID_Pos (0) /*!< TRNG_T::ALARMS: FAILED_TEST_ID Position*/ +#define TRNG_ALARMS_FAILED_TEST_ID_Msk (0xful << TRNG_ALARMS_FAILED_TEST_ID_Pos) /*!< TRNG_T::ALARMS: FAILED_TEST_ID Mask */ + +#define TRNG_ALARMS_ILLEGAL_CMD_SEQ_Pos (4) /*!< TRNG_T::ALARMS: ILLEGAL_CMD_SEQ Position*/ +#define TRNG_ALARMS_ILLEGAL_CMD_SEQ_Msk (0x1ul << TRNG_ALARMS_ILLEGAL_CMD_SEQ_Pos) /*!< TRNG_T::ALARMS: ILLEGAL_CMD_SEQ Mask */ + +#define TRNG_ALARMS_FAILED_SEED_ST_HT_Pos (5) /*!< TRNG_T::ALARMS: FAILED_SEED_ST_HT Position*/ +#define TRNG_ALARMS_FAILED_SEED_ST_HT_Msk (0x1ul << TRNG_ALARMS_FAILED_SEED_ST_HT_Pos) /*!< TRNG_T::ALARMS: FAILED_SEED_ST_HT Mask */ + +#define TRNG_COREKIT_REL_REL_NUM_Pos (0) /*!< TRNG_T::COREKIT_REL: REL_NUM Position */ +#define TRNG_COREKIT_REL_REL_NUM_Msk (0xfffful << TRNG_COREKIT_REL_REL_NUM_Pos) /*!< TRNG_T::COREKIT_REL: REL_NUM Mask */ + +#define TRNG_COREKIT_REL_EXT_VER_Pos (16) /*!< TRNG_T::COREKIT_REL: EXT_VER Position */ +#define TRNG_COREKIT_REL_EXT_VER_Msk (0xfful << TRNG_COREKIT_REL_EXT_VER_Pos) /*!< TRNG_T::COREKIT_REL: EXT_VER Mask */ + +#define TRNG_COREKIT_REL_EXT_ENUM_Pos (28) /*!< TRNG_T::COREKIT_REL: EXT_ENUM Position */ +#define TRNG_COREKIT_REL_EXT_ENUM_Msk (0xful << TRNG_COREKIT_REL_EXT_ENUM_Pos) /*!< TRNG_T::COREKIT_REL: EXT_ENUM Mask */ + +#define TRNG_FEATURES_SECURE_RST_STATE_Pos (0) /*!< TRNG_T::FEATURES: SECURE_RST_STATE Position*/ +#define TRNG_FEATURES_SECURE_RST_STATE_Msk (0x1ul << TRNG_FEATURES_SECURE_RST_STATE_Pos) /*!< TRNG_T::FEATURES: SECURE_RST_STATE Mask*/ + +#define TRNG_FEATURES_DIAG_LEVEL_ST_HLT_Pos (1) /*!< TRNG_T::FEATURES: DIAG_LEVEL_ST_HLT Position*/ +#define TRNG_FEATURES_DIAG_LEVEL_ST_HLT_Msk (0x7ul << TRNG_FEATURES_DIAG_LEVEL_ST_HLT_Pos) /*!< TRNG_T::FEATURES: DIAG_LEVEL_ST_HLT Mask*/ + +#define TRNG_FEATURES_DIAG_LEVEL_CLP800_Pos (4) /*!< TRNG_T::FEATURES: DIAG_LEVEL_CLP800 Position*/ +#define TRNG_FEATURES_DIAG_LEVEL_CLP800_Msk (0x7ul << TRNG_FEATURES_DIAG_LEVEL_CLP800_Pos) /*!< TRNG_T::FEATURES: DIAG_LEVEL_CLP800 Mask*/ + +#define TRNG_FEATURES_DIAG_LEVEL_NS_Pos (7) /*!< TRNG_T::FEATURES: DIAG_LEVEL_NS Position*/ +#define TRNG_FEATURES_DIAG_LEVEL_NS_Msk (0x1ul << TRNG_FEATURES_DIAG_LEVEL_NS_Pos) /*!< TRNG_T::FEATURES: DIAG_LEVEL_NS Mask */ + +#define TRNG_FEATURES_PS_PRESENT_Pos (8) /*!< TRNG_T::FEATURES: PS_PRESENT Position */ +#define TRNG_FEATURES_PS_PRESENT_Msk (0x1ul << TRNG_FEATURES_PS_PRESENT_Pos) /*!< TRNG_T::FEATURES: PS_PRESENT Mask */ + +#define TRNG_FEATURES_AES_256_Pos (9) /*!< TRNG_T::FEATURES: AES_256 Position */ +#define TRNG_FEATURES_AES_256_Msk (0x1ul << TRNG_FEATURES_AES_256_Pos) /*!< TRNG_T::FEATURES: AES_256 Mask */ + +#define TRNG_RAND0_RAND_Pos (0) /*!< TRNG_T::RAND0: RAND Position */ +#define TRNG_RAND0_RAND_Msk (0xfffffffful << TRNG_RAND0_RAND_Pos) /*!< TRNG_T::RAND0: RAND Mask */ + +#define TRNG_RAND1_RAND_Pos (0) /*!< TRNG_T::RAND1: RAND Position */ +#define TRNG_RAND1_RAND_Msk (0xfffffffful << TRNG_RAND1_RAND_Pos) /*!< TRNG_T::RAND1: RAND Mask */ + +#define TRNG_RAND2_RAND_Pos (0) /*!< TRNG_T::RAND2: RAND Position */ +#define TRNG_RAND2_RAND_Msk (0xfffffffful << TRNG_RAND2_RAND_Pos) /*!< TRNG_T::RAND2: RAND Mask */ + +#define TRNG_RAND3_RAND_Pos (0) /*!< TRNG_T::RAND3: RAND Position */ +#define TRNG_RAND3_RAND_Msk (0xfffffffful << TRNG_RAND3_RAND_Pos) /*!< TRNG_T::RAND3: RAND Mask */ + +#define TRNG_NPA_DATA0_NPA_DATA_Pos (0) /*!< TRNG_T::NPA_DATA0: NPA_DATA Position */ +#define TRNG_NPA_DATA0_NPA_DATA_Msk (0xfffffffful << TRNG_NPA_DATA0_NPA_DATA_Pos) /*!< TRNG_T::NPA_DATA0: NPA_DATA Mask */ + +#define TRNG_NPA_DATA1_NPA_DATA_Pos (0) /*!< TRNG_T::NPA_DATA1: NPA_DATA Position */ +#define TRNG_NPA_DATA1_NPA_DATA_Msk (0xfffffffful << TRNG_NPA_DATA1_NPA_DATA_Pos) /*!< TRNG_T::NPA_DATA1: NPA_DATA Mask */ + +#define TRNG_NPA_DATA2_NPA_DATA_Pos (0) /*!< TRNG_T::NPA_DATA2: NPA_DATA Position */ +#define TRNG_NPA_DATA2_NPA_DATA_Msk (0xfffffffful << TRNG_NPA_DATA2_NPA_DATA_Pos) /*!< TRNG_T::NPA_DATA2: NPA_DATA Mask */ + +#define TRNG_NPA_DATA3_NPA_DATA_Pos (0) /*!< TRNG_T::NPA_DATA3: NPA_DATA Position */ +#define TRNG_NPA_DATA3_NPA_DATA_Msk (0xfffffffful << TRNG_NPA_DATA3_NPA_DATA_Pos) /*!< TRNG_T::NPA_DATA3: NPA_DATA Mask */ + +#define TRNG_NPA_DATA4_NPA_DATA_Pos (0) /*!< TRNG_T::NPA_DATA4: NPA_DATA Position */ +#define TRNG_NPA_DATA4_NPA_DATA_Msk (0xfffffffful << TRNG_NPA_DATA4_NPA_DATA_Pos) /*!< TRNG_T::NPA_DATA4: NPA_DATA Mask */ + +#define TRNG_NPA_DATA5_NPA_DATA_Pos (0) /*!< TRNG_T::NPA_DATA5: NPA_DATA Position */ +#define TRNG_NPA_DATA5_NPA_DATA_Msk (0xfffffffful << TRNG_NPA_DATA5_NPA_DATA_Pos) /*!< TRNG_T::NPA_DATA5: NPA_DATA Mask */ + +#define TRNG_NPA_DATA6_NPA_DATA_Pos (0) /*!< TRNG_T::NPA_DATA6: NPA_DATA Position */ +#define TRNG_NPA_DATA6_NPA_DATA_Msk (0xfffffffful << TRNG_NPA_DATA6_NPA_DATA_Pos) /*!< TRNG_T::NPA_DATA6: NPA_DATA Mask */ + +#define TRNG_NPA_DATA7_NPA_DATA_Pos (0) /*!< TRNG_T::NPA_DATA7: NPA_DATA Position */ +#define TRNG_NPA_DATA7_NPA_DATA_Msk (0xfffffffful << TRNG_NPA_DATA7_NPA_DATA_Pos) /*!< TRNG_T::NPA_DATA7: NPA_DATA Mask */ + +#define TRNG_NPA_DATA8_NPA_DATA_Pos (0) /*!< TRNG_T::NPA_DATA8: NPA_DATA Position */ +#define TRNG_NPA_DATA8_NPA_DATA_Msk (0xfffffffful << TRNG_NPA_DATA8_NPA_DATA_Pos) /*!< TRNG_T::NPA_DATA8: NPA_DATA Mask */ + +#define TRNG_NPA_DATA9_NPA_DATA_Pos (0) /*!< TRNG_T::NPA_DATA9: NPA_DATA Position */ +#define TRNG_NPA_DATA9_NPA_DATA_Msk (0xfffffffful << TRNG_NPA_DATA9_NPA_DATA_Pos) /*!< TRNG_T::NPA_DATA9: NPA_DATA Mask */ + +#define TRNG_NPA_DATA10_NPA_DATA_Pos (0) /*!< TRNG_T::NPA_DATA10: NPA_DATA Position */ +#define TRNG_NPA_DATA10_NPA_DATA_Msk (0xfffffffful << TRNG_NPA_DATA10_NPA_DATA_Pos) /*!< TRNG_T::NPA_DATA10: NPA_DATA Mask */ + +#define TRNG_NPA_DATA11_NPA_DATA_Pos (0) /*!< TRNG_T::NPA_DATA11: NPA_DATA Position */ +#define TRNG_NPA_DATA11_NPA_DATA_Msk (0xfffffffful << TRNG_NPA_DATA11_NPA_DATA_Pos) /*!< TRNG_T::NPA_DATA11: NPA_DATA Mask */ + +#define TRNG_NPA_DATA12_NPA_DATA_Pos (0) /*!< TRNG_T::NPA_DATA12: NPA_DATA Position */ +#define TRNG_NPA_DATA12_NPA_DATA_Msk (0xfffffffful << TRNG_NPA_DATA12_NPA_DATA_Pos) /*!< TRNG_T::NPA_DATA12: NPA_DATA Mask */ + +#define TRNG_NPA_DATA13_NPA_DATA_Pos (0) /*!< TRNG_T::NPA_DATA13: NPA_DATA Position */ +#define TRNG_NPA_DATA13_NPA_DATA_Msk (0xfffffffful << TRNG_NPA_DATA13_NPA_DATA_Pos) /*!< TRNG_T::NPA_DATA13: NPA_DATA Mask */ + +#define TRNG_NPA_DATA14_NPA_DATA_Pos (0) /*!< TRNG_T::NPA_DATA14: NPA_DATA Position */ +#define TRNG_NPA_DATA14_NPA_DATA_Msk (0xfffffffful << TRNG_NPA_DATA14_NPA_DATA_Pos) /*!< TRNG_T::NPA_DATA14: NPA_DATA Mask */ + +#define TRNG_NPA_DATA15_NPA_DATA_Pos (0) /*!< TRNG_T::NPA_DATA15: NPA_DATA Position */ +#define TRNG_NPA_DATA15_NPA_DATA_Msk (0xfffffffful << TRNG_NPA_DATA15_NPA_DATA_Pos) /*!< TRNG_T::NPA_DATA15: NPA_DATA Mask */ + +#define TRNG_SEED0_SEED_Pos (0) /*!< TRNG_T::SEED0: SEED Position */ +#define TRNG_SEED0_SEED_Msk (0xfffffffful << TRNG_SEED0_SEED_Pos) /*!< TRNG_T::SEED0: SEED Mask */ + +#define TRNG_SEED1_SEED_Pos (0) /*!< TRNG_T::SEED1: SEED Position */ +#define TRNG_SEED1_SEED_Msk (0xfffffffful << TRNG_SEED1_SEED_Pos) /*!< TRNG_T::SEED1: SEED Mask */ + +#define TRNG_SEED2_SEED_Pos (0) /*!< TRNG_T::SEED2: SEED Position */ +#define TRNG_SEED2_SEED_Msk (0xfffffffful << TRNG_SEED2_SEED_Pos) /*!< TRNG_T::SEED2: SEED Mask */ + +#define TRNG_SEED3_SEED_Pos (0) /*!< TRNG_T::SEED3: SEED Position */ +#define TRNG_SEED3_SEED_Msk (0xfffffffful << TRNG_SEED3_SEED_Pos) /*!< TRNG_T::SEED3: SEED Mask */ + +#define TRNG_SEED4_SEED_Pos (0) /*!< TRNG_T::SEED4: SEED Position */ +#define TRNG_SEED4_SEED_Msk (0xfffffffful << TRNG_SEED4_SEED_Pos) /*!< TRNG_T::SEED4: SEED Mask */ + +#define TRNG_SEED5_SEED_Pos (0) /*!< TRNG_T::SEED5: SEED Position */ +#define TRNG_SEED5_SEED_Msk (0xfffffffful << TRNG_SEED5_SEED_Pos) /*!< TRNG_T::SEED5: SEED Mask */ + +#define TRNG_SEED6_SEED_Pos (0) /*!< TRNG_T::SEED6: SEED Position */ +#define TRNG_SEED6_SEED_Msk (0xfffffffful << TRNG_SEED6_SEED_Pos) /*!< TRNG_T::SEED6: SEED Mask */ + +#define TRNG_SEED7_SEED_Pos (0) /*!< TRNG_T::SEED7: SEED Position */ +#define TRNG_SEED7_SEED_Msk (0xfffffffful << TRNG_SEED7_SEED_Pos) /*!< TRNG_T::SEED7: SEED Mask */ + +#define TRNG_SEED8_SEED_Pos (0) /*!< TRNG_T::SEED8: SEED Position */ +#define TRNG_SEED8_SEED_Msk (0xfffffffful << TRNG_SEED8_SEED_Pos) /*!< TRNG_T::SEED8: SEED Mask */ + +#define TRNG_SEED9_SEED_Pos (0) /*!< TRNG_T::SEED9: SEED Position */ +#define TRNG_SEED9_SEED_Msk (0xfffffffful << TRNG_SEED9_SEED_Pos) /*!< TRNG_T::SEED9: SEED Mask */ + +#define TRNG_SEED10_SEED_Pos (0) /*!< TRNG_T::SEED10: SEED Position */ +#define TRNG_SEED10_SEED_Msk (0xfffffffful << TRNG_SEED10_SEED_Pos) /*!< TRNG_T::SEED10: SEED Mask */ + +#define TRNG_SEED11_SEED_Pos (0) /*!< TRNG_T::SEED11: SEED Position */ +#define TRNG_SEED11_SEED_Msk (0xfffffffful << TRNG_SEED11_SEED_Pos) /*!< TRNG_T::SEED11: SEED Mask */ + +#define TRNG_TIME_TO_SEED_TTS_Pos (0) /*!< TRNG_T::TIME_TO_SEED: TTS Position */ +#define TRNG_TIME_TO_SEED_TTS_Msk (0xfffffffful << TRNG_TIME_TO_SEED_TTS_Pos) /*!< TRNG_T::TIME_TO_SEED: TTS Mask */ + +#define TRNG_BUILD_CFG0_CORE_TYPE_Pos (0) /*!< TRNG_T::BUILD_CFG0: CORE_TYPE Position */ +#define TRNG_BUILD_CFG0_CORE_TYPE_Msk (0x3ul << TRNG_BUILD_CFG0_CORE_TYPE_Pos) /*!< TRNG_T::BUILD_CFG0: CORE_TYPE Mask */ + +#define TRNG_BUILD_CFG0_BG8_Pos (7) /*!< TRNG_T::BUILD_CFG0: BG8 Position */ +#define TRNG_BUILD_CFG0_BG8_Msk (0x1ul << TRNG_BUILD_CFG0_BG8_Pos) /*!< TRNG_T::BUILD_CFG0: BG8 Mask */ + +#define TRNG_BUILD_CFG0_CDC_SYNC_DEPTH_Pos (8) /*!< TRNG_T::BUILD_CFG0: CDC_SYNC_DEPTH Position*/ +#define TRNG_BUILD_CFG0_CDC_SYNC_DEPTH_Msk (0x3ul << TRNG_BUILD_CFG0_CDC_SYNC_DEPTH_Pos) /*!< TRNG_T::BUILD_CFG0: CDC_SYNC_DEPTH Mask*/ + +#define TRNG_BUILD_CFG0_BACKGROUND_NOISE_Pos (10) /*!< TRNG_T::BUILD_CFG0: BACKGROUND_NOISE Position*/ +#define TRNG_BUILD_CFG0_BACKGROUND_NOISE_Msk (0x1ul << TRNG_BUILD_CFG0_BACKGROUND_NOISE_Pos) /*!< TRNG_T::BUILD_CFG0: BACKGROUND_NOISE Mask*/ + +#define TRNG_BUILD_CFG0_EDU_PRESENT_Pos (11) /*!< TRNG_T::BUILD_CFG0: EDU_PRESENT Position*/ +#define TRNG_BUILD_CFG0_EDU_PRESENT_Msk (0x1ul << TRNG_BUILD_CFG0_EDU_PRESENT_Pos) /*!< TRNG_T::BUILD_CFG0: EDU_PRESENT Mask */ + +#define TRNG_BUILD_CFG0_AES_DATAPATH_Pos (12) /*!< TRNG_T::BUILD_CFG0: AES_DATAPATH Position*/ +#define TRNG_BUILD_CFG0_AES_DATAPATH_Msk (0x1ul << TRNG_BUILD_CFG0_AES_DATAPATH_Pos) /*!< TRNG_T::BUILD_CFG0: AES_DATAPATH Mask */ + +#define TRNG_BUILD_CFG0_AES_MAX_KEY_SIZE_Pos (13) /*!< TRNG_T::BUILD_CFG0: AES_MAX_KEY_SIZE Position*/ +#define TRNG_BUILD_CFG0_AES_MAX_KEY_SIZE_Msk (0x1ul << TRNG_BUILD_CFG0_AES_MAX_KEY_SIZE_Pos) /*!< TRNG_T::BUILD_CFG0: AES_MAX_KEY_SIZE Mask*/ + +#define TRNG_BUILD_CFG0_PERSONALIZATION_STR_Pos (14) /*!< TRNG_T::BUILD_CFG0: PERSONALIZATION_STR Position*/ +#define TRNG_BUILD_CFG0_PERSONALIZATION_STR_Msk (0x1ul << TRNG_BUILD_CFG0_PERSONALIZATION_STR_Pos) /*!< TRNG_T::BUILD_CFG0: PERSONALIZATION_STR Mask*/ + +#define TRNG_BUILD_CFG1_NUM_RAW_NOISE_BLKS_Pos (0) /*!< TRNG_T::BUILD_CFG1: NUM_RAW_NOISE_BLKS Position*/ +#define TRNG_BUILD_CFG1_NUM_RAW_NOISE_BLKS_Msk (0xfful << TRNG_BUILD_CFG1_NUM_RAW_NOISE_BLKS_Pos) /*!< TRNG_T::BUILD_CFG1: NUM_RAW_NOISE_BLKS Mask*/ + +#define TRNG_BUILD_CFG1_STICKY_STARTUP_Pos (8) /*!< TRNG_T::BUILD_CFG1: STICKY_STARTUP Position*/ +#define TRNG_BUILD_CFG1_STICKY_STARTUP_Msk (0x1ul << TRNG_BUILD_CFG1_STICKY_STARTUP_Pos) /*!< TRNG_T::BUILD_CFG1: STICKY_STARTUP Mask*/ + +#define TRNG_BUILD_CFG1_AUTO_CORRELATION_TEST_Pos (12) /*!< TRNG_T::BUILD_CFG1: AUTO_CORRELATION_TEST Position*/ +#define TRNG_BUILD_CFG1_AUTO_CORRELATION_TEST_Msk (0x1ul << TRNG_BUILD_CFG1_AUTO_CORRELATION_TEST_Pos) /*!< TRNG_T::BUILD_CFG1: AUTO_CORRELATION_TEST Mask*/ + +#define TRNG_BUILD_CFG1_MONOBIT_TEST_Pos (13) /*!< TRNG_T::BUILD_CFG1: MONOBIT_TEST Position*/ +#define TRNG_BUILD_CFG1_MONOBIT_TEST_Msk (0x1ul << TRNG_BUILD_CFG1_MONOBIT_TEST_Pos) /*!< TRNG_T::BUILD_CFG1: MONOBIT_TEST Mask */ + +#define TRNG_BUILD_CFG1_RUN_TEST_Pos (14) /*!< TRNG_T::BUILD_CFG1: RUN_TEST Position */ +#define TRNG_BUILD_CFG1_RUN_TEST_Msk (0x1ul << TRNG_BUILD_CFG1_RUN_TEST_Pos) /*!< TRNG_T::BUILD_CFG1: RUN_TEST Mask */ + +#define TRNG_BUILD_CFG1_POKER_TEST_Pos (15) /*!< TRNG_T::BUILD_CFG1: POKER_TEST Position*/ +#define TRNG_BUILD_CFG1_POKER_TEST_Msk (0x1ul << TRNG_BUILD_CFG1_POKER_TEST_Pos) /*!< TRNG_T::BUILD_CFG1: POKER_TEST Mask */ + +#define TRNG_BUILD_CFG1_RAW_HT_ADAP_TEST_Pos (16) /*!< TRNG_T::BUILD_CFG1: RAW_HT_ADAP_TEST Position*/ +#define TRNG_BUILD_CFG1_RAW_HT_ADAP_TEST_Msk (0x7ul << TRNG_BUILD_CFG1_RAW_HT_ADAP_TEST_Pos) /*!< TRNG_T::BUILD_CFG1: RAW_HT_ADAP_TEST Mask*/ + +#define TRNG_BUILD_CFG1_RAW_HT_REP_TEST_Pos (19) /*!< TRNG_T::BUILD_CFG1: RAW_HT_REP_TEST Position*/ +#define TRNG_BUILD_CFG1_RAW_HT_REP_TEST_Msk (0x1ul << TRNG_BUILD_CFG1_RAW_HT_REP_TEST_Pos) /*!< TRNG_T::BUILD_CFG1: RAW_HT_REP_TEST Mask*/ + +#define TRNG_BUILD_CFG1_ENT_SRC_REP_SMPL_SIZE_Pos (20) /*!< TRNG_T::BUILD_CFG1: ENT_SRC_REP_SMPL_SIZE Position*/ +#define TRNG_BUILD_CFG1_ENT_SRC_REP_SMPL_SIZE_Msk (0x7ul << TRNG_BUILD_CFG1_ENT_SRC_REP_SMPL_SIZE_Pos) /*!< TRNG_T::BUILD_CFG1: ENT_SRC_REP_SMPL_SIZE Mask*/ + +#define TRNG_BUILD_CFG1_ENT_SRC_REP_TEST_Pos (23) /*!< TRNG_T::BUILD_CFG1: ENT_SRC_REP_TEST Position*/ +#define TRNG_BUILD_CFG1_ENT_SRC_REP_TEST_Msk (0x1ul << TRNG_BUILD_CFG1_ENT_SRC_REP_TEST_Pos) /*!< TRNG_T::BUILD_CFG1: ENT_SRC_REP_TEST Mask*/ + +#define TRNG_BUILD_CFG1_ENT_SRC_REP_MIN_ENTROPY_Pos (24) /*!< TRNG_T::BUILD_CFG1: ENT_SRC_REP_MIN_ENTROPY Position*/ +#define TRNG_BUILD_CFG1_ENT_SRC_REP_MIN_ENTROPY_Msk (0x7ful << TRNG_BUILD_CFG1_ENT_SRC_REP_MIN_ENTROPY_Pos) /*!< TRNG_T::BUILD_CFG1: ENT_SRC_REP_MIN_ENTROPY Mask*/ + +/**@}*/ /* TRNG_CONST */ +/**@}*/ /* end of TRNG register group */ +/**@}*/ /* end of REGISTER group */ + +#if defined ( __CC_ARM ) + #pragma no_anon_unions +#endif + +#endif /* __TRNG_REG_H__ */ diff --git a/bsp/nuvoton/libraries/ma35/Device/Nuvoton/MA35D1/Include/uart_reg.h b/bsp/nuvoton/libraries/ma35/Device/Nuvoton/MA35D1/Include/uart_reg.h new file mode 100644 index 0000000000..299b1fb873 --- /dev/null +++ b/bsp/nuvoton/libraries/ma35/Device/Nuvoton/MA35D1/Include/uart_reg.h @@ -0,0 +1,1061 @@ +/**************************************************************************//** + * @file uart_reg.h + * @brief UART register definition header file + * + * SPDX-License-Identifier: Apache-2.0 + * @copyright (C) 2020 Nuvoton Technology Corp. All rights reserved. + *****************************************************************************/ +#ifndef __UART_REG_H__ +#define __UART_REG_H__ + +#if defined ( __CC_ARM ) + #pragma anon_unions +#endif + +/** + @addtogroup REGISTER Control Register + @{ +*/ + +/** + @addtogroup UART Universal Asynchronous Receiver/Transmitter Controller(UART) + Memory Mapped Structure for UART Controller +@{ */ + +typedef struct +{ + + + /** + * @var UART_T::DAT + * Offset: 0x00 UART Receive/Transmit Buffer Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[7:0] |DAT |Data Receive/Transmit Buffer + * | | |Write Operation: + * | | |By writing one byte to this register, the data byte will be stored in transmitter FIFO + * | | |The UART controller will send out the data stored in transmitter FIFO top location through the UART_TXD. + * | | |Read Operation: + * | | |By reading this register, the UART controller will return an 8-bit data received from receiver FIFO. + * |[8] |PARITY |Parity Bit Receive/Transmit Buffer + * | | |Write Operation: + * | | |By writing to this bit, the parity bit will be stored in transmitter FIFO + * | | |If PBE (UART_LINE[3]) and PSS (UART_LINE[7]) are set, + * | | |the UART controller will send out this bit follow the DAT (UART_DAT[7:0]) through the UART_TXD. + * | | |Read Operation: + * | | |If PBE (UART_LINE[3]) and PSS (UART_LINE[7]) are enabled, the parity bit can be read by this bit. + * | | |Note: This bit has effect only when PBE (UART_LINE[3]) and PSS (UART_LINE[7]) are set. + * @var UART_T::INTEN + * Offset: 0x04 UART Interrupt Enable Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[0] |RDAIEN |Receive Data Available Interrupt Enable Bit + * | | |0 = Receive data available interrupt Disabled. + * | | |1 = Receive data available interrupt Enabled. + * |[1] |THREIEN |Transmit Holding Register Empty Interrupt Enable Bit + * | | |0 = Transmit holding register empty interrupt Disabled. + * | | |1 = Transmit holding register empty interrupt Enabled. + * |[2] |RLSIEN |Receive Line Status Interrupt Enable Bit + * | | |0 = Receive Line Status interrupt Disabled. + * | | |1 = Receive Line Status interrupt Enabled. + * |[3] |MODEMIEN |Modem Status Interrupt Enable Bit + * | | |0 = Modem status interrupt Disabled. + * | | |1 = Modem status interrupt Enabled. + * |[4] |RXTOIEN |RX Time-out Interrupt Enable Bit + * | | |0 = RX time-out interrupt Disabled. + * | | |1 = RX time-out interrupt Enabled. + * |[5] |BUFEIEN |Buffer Error Interrupt Enable Bit + * | | |0 = Buffer error interrupt Disabled. + * | | |1 = Buffer error interrupt Enabled. + * |[6] |WKIEN |Wake-up Interrupt Enable Bit + * | | |0 = Wake-up Interrupt Disabled. + * | | |1 = Wake-up Interrupt Enabled. + * |[11] |TOCNTEN |Receive Buffer Time-out Counter Enable Bit + * | | |0 = Receive Buffer Time-out counter Disabled. + * | | |1 = Receive Buffer Time-out counter Enabled. + * |[12] |ATORTSEN |nRTS Auto-flow Control Enable Bit + * | | |0 = nRTS auto-flow control Disabled. + * | | |1 = nRTS auto-flow control Enabled. + * | | |Note: When nRTS auto-flow is enabled, if the number of bytes in the RX FIFO equals the RTSTRGLV (UART_FIFO[19:16]), the UART will de-assert nRTS signal. + * |[13] |ATOCTSEN |nCTS Auto-flow Control Enable Bit + * | | |0 = nCTS auto-flow control Disabled. + * | | |1 = nCTS auto-flow control Enabled. + * | | |Note: When nCTS auto-flow is enabled, the UART will send data to external device if nCTS input assert (UART will not send data to device until nCTS is asserted). + * |[14] |TXPDMAEN |TX PDMA Enable Bit + * | | |0 = TX PDMA Disabled. + * | | |1 = TX PDMA Enabled. + * | | |Note: If RLSIEN (UART_INTEN[2]) is enabled and HWRLSINT (UART_INTSTS[26]) is set to 1, the RLS (Receive Line Status) Interrupt is caused + * | | |If RLS interrupt is caused by Break Error Flag BIF(UART_FIFOSTS[6]), Frame Error Flag FEF(UART_FIFO[5]) or Parity Error Flag PEF(UART_FIFOSTS[4]), UART PDMA transmit request operation is stopped + * | | |Clear Break Error Flag BIF or Frame Error Flag FEF or Parity Error Flag PEF by writing '1' to corresponding BIF, FEF and PEF to make UART PDMA transmit request operation continue. + * |[15] |RXPDMAEN |RX PDMA Enable Bit + * | | |This bit can enable or disable RX PDMA service. + * | | |0 = RX PDMA Disabled. + * | | |1 = RX PDMA Enabled. + * | | |Note: If RLSIEN (UART_INTEN[2]) is enabled and HWRLSINT (UART_INTSTS[26]) is set to 1, the RLS (Receive Line Status) Interrupt is caused + * | | |If RLS interrupt is caused by Break Error Flag BIF(UART_FIFOSTS[6]), Frame Error Flag FEF(UART_FIFO[5]) or Parity Error Flag PEF(UART_FIFOSTS[4]), UART PDMA receive request operation is stopped + * | | |Clear Break Error Flag BIF or Frame Error Flag FEF or Parity Error Flag PEF by writing '1' to corresponding BIF, FEF and PEF to make UART PDMA receive request operation continue. + * |[16] |SWBEIEN |Single-wire Bit Error Detection Interrupt Enable Bit + * | | |Set this bit, the Single-wire Half Duplex Bit Error Detection Interrupt SWBEINT(UART_INTSTS[24]) is generated when Single-wire Bit Error Detection SWBEIF(UART_INTSTS[16]) is set. + * | | |0 = Single-wire Bit Error Detect Interrupt Disabled. + * | | |1 = Single-wire Bit Error Detect Interrupt Enabled. + * | | |Note: This bit is valid when FUNCSEL (UART_FUNCSEL[2:0]) is select UART Single-wire mode. + * |[18] |ABRIEN |Auto-baud Rate Interrupt Enable Bit + * | | |0 = Auto-baud rate interrupt Disabled. + * | | |1 = Auto-baud rate interrupt Enabled. + * |[22] |TXENDIEN |Transmitter Empty Interrupt Enable Bit + * | | |If TXENDIEN (UART_INTEN[22]) is enabled, the Transmitter Empty interrupt TXENDINT (UART_INTSTS[30]) will be generated when TXENDIF (UART_INTSTS[22]) is set (TX FIFO (UART_DAT) is empty and the STOP bit of the last byte has been transmitted). + * | | |0 = Transmitter empty interrupt Disabled. + * | | |1 = Transmitter empty interrupt Enabled. + * @var UART_T::FIFO + * Offset: 0x08 UART FIFO Control Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[1] |RXRST |RX Field Software Reset + * | | |When RXRST (UART_FIFO[1]) is set, all the byte in the receiver FIFO and RX internal state machine are cleared. + * | | |0 = No effect. + * | | |1 = Reset the RX internal state machine and pointers. + * | | |Note 1: This bit will automatically clear at least 3 UART peripheral clock cycles. + * | | |Note 2: Before setting this bit, it should wait for the RXIDLE (UART_FIFOSTS[29]) be set. + * |[2] |TXRST |TX Field Software Reset + * | | |When TXRST (UART_FIFO[2]) is set, all the byte in the transmit FIFO and TX internal state machine are cleared. + * | | |0 = No effect. + * | | |1 = Reset the TX internal state machine and pointers. + * | | |Note 1: This bit will automatically clear at least 3 UART peripheral clock cycles. + * | | |Note 2: Before setting this bit, it should wait for the TXEMPTYF (UART_FIFOSTS[28]) be set. + * |[7:4] |RFITL |RX FIFO Interrupt Trigger Level + * | | |When the number of bytes in the receive FIFO equals the RFITL, the RDAIF (UART_INTSTS[0]) will be set (if RDAIEN (UART_INTEN [0]) enabled, and an interrupt will be generated). + * | | |0000 = RX FIFO Interrupt Trigger Level is 1 byte. + * | | |0001 = RX FIFO Interrupt Trigger Level is 4 bytes. + * | | |0010 = RX FIFO Interrupt Trigger Level is 8 bytes. + * | | |0011 = RX FIFO Interrupt Trigger Level is 14 bytes. + * | | |Others = Reserved. + * |[8] |RXOFF |Receiver Disable Bit + * | | |The receiver is disabled or not (set 1 to disable receiver). + * | | |0 = Receiver Enabled. + * | | |1 = Receiver Disabled. + * | | |Note: This bit is used for RS-485 Normal Multi-drop mode + * | | |It should be programmed before RS485NMM (UART_ALTCTL [8]) is programmed. + * |[19:16] |RTSTRGLV |nRTS Trigger Level for Auto-flow Control + * | | |0000 = nRTS Trigger Level is 1 byte. + * | | |0001 = nRTS Trigger Level is 4 bytes. + * | | |0010 = nRTS Trigger Level is 8 bytes. + * | | |0011 = nRTS Trigger Level is 14 bytes. + * | | |Others = Reserved. + * | | |Note: This field is used for auto nRTS flow control. + * @var UART_T::LINE + * Offset: 0x0C UART Line Control Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[1:0] |WLS |Word Length Selection + * | | |This field sets UART word length. + * | | |00 = 5 bits. + * | | |01 = 6 bits. + * | | |10 = 7 bits. + * | | |11 = 8 bits. + * |[2] |NSB |Number of 'STOP Bit' + * | | |0 = One 'STOP bit' is generated in the transmitted data. + * | | |1 = When select 5-bit word length, 1.5 'STOP bit' is generated in the transmitted data + * | | |When select 6-, 7- and 8-bit word length, 2 'STOP bit' is generated in the transmitted data. + * |[3] |PBE |Parity Bit Enable Bit + * | | |0 = Parity bit generated Disabled. + * | | |1 = Parity bit generated Enabled. + * | | |Note: Parity bit is generated on each outgoing character and is checked on each incoming data. + * |[4] |EPE |Even Parity Enable Bit + * | | |0 = Odd number of logic 1's is transmitted and checked in each word. + * | | |1 = Even number of logic 1's is transmitted and checked in each word. + * | | |Note: This bit has effect only when PBE (UART_LINE[3]) is set. + * |[5] |SPE |Stick Parity Enable Bit + * | | |0 = Stick parity Disabled. + * | | |1 = Stick parity Enabled. + * | | |Note: If PBE (UART_LINE[3]) and EPE (UART_LINE[4]) are logic 1, the parity bit is transmitted and checked as logic 0 + * | | |If PBE (UART_LINE[3]) is 1 and EPE (UART_LINE[4]) is 0 then the parity bit is transmitted and checked as 1. + * |[6] |BCB |Break Control Bit + * | | |0 = Break Control Disabled. + * | | |1 = Break Control Enabled. + * | | |Note: When this bit is set to logic 1, the transmitted serial data output (TX) is forced to the Spacing State (logic 0) + * | | |This bit acts only on TX line and has no effect on the transmitter logic. + * |[7] |PSS |Parity Bit Source Selection + * | | |The parity bit can be selected to be generated and checked automatically or by software. + * | | |0 = Parity bit is generated by EPE (UART_LINE[4]) and SPE (UART_LINE[5]) setting and checked automatically. + * | | |1 = Parity bit generated and checked by software. + * | | |Note 1: This bit has effect only when PBE (UART_LINE[3]) is set. + * | | |Note 2: If PSS is 0, the parity bit is transmitted and checked automatically + * | | |If PSS is 1, the transmitted parity bit value can be determined by writing PARITY (UART_DAT[8]) and the parity bit can be read by reading PARITY (UART_DAT[8]). + * |[8] |TXDINV |TX Data Inverted + * | | |0 = Transmitted data signal inverted Disabled. + * | | |1 = Transmitted data signal inverted Enabled. + * | | |Note 1: Before setting this bit, TXRXDIS (UART_FUNCSEL[3]) should be set then waited for TXRXACT (UART_FIFOSTS[31]) is cleared + * | | |When the configuration is done, cleared TXRXDIS (UART_FUNCSEL[3]) to activate UART controller. + * | | |Note 2: This bit is valid when FUNCSEL (UART_FUNCSEL[2:0]) is select UART or RS485 function. + * |[9] |RXDINV |RX Data Inverted + * | | |0 = Received data signal inverted Disabled. + * | | |1 = Received data signal inverted Enabled. + * | | |Note 1: Before setting this bit, TXRXDIS (UART_FUNCSEL[3]) should be set then waited for TXRXACT (UART_FIFOSTS[31]) is cleared + * | | |When the configuration is done, cleared TXRXDIS (UART_FUNCSEL[3]) to activate UART controller. + * | | |Note 2: This bit is valid when FUNCSEL (UART_FUNCSEL[2:0]) is select UART, LIN or RS485 function. + * @var UART_T::MODEM + * Offset: 0x10 UART Modem Control Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[1] |RTS |nRTS Signal Control + * | | |This bit is direct control internal nRTS (Request-to-send) signal active or not, and then drive the nRTS pin output with RTSACTLV bit configuration. + * | | |0 = nRTS signal is active. + * | | |1 = nRTS signal is inactive. + * | | |Note 1: The nRTS signal control bit is not effective when nRTS auto-flow control is enabled in UART function mode. + * | | |Note 2: The nRTS signal control bit is not effective when RS-485 auto direction mode (AUD) is enabled in RS-485 function mode. + * | | |Note 3: Single-wire mode is support this feature. + * |[9] |RTSACTLV |nRTS Pin Active Level + * | | |This bit defines the active level state of nRTS pin output. + * | | |0 = nRTS pin output is high level active. + * | | |1 = nRTS pin output is low level active. (Default) + * | | |Note 1: Refer to Figure 6.24-13 and Figure 6.24-14 for UART function mode. + * | | |Note 2: Refer to Figure 6.24-17 and Figure 6.24-18 for RS-485 function mode. + * | | |Note 3: Before setting this bit, TXRXDIS (UART_FUNCSEL[3]) should be set then waited for TXRXACT (UART_FIFOSTS[31]) is cleared + * | | |When the configuration is done, cleared TXRXDIS (UART_FUNCSEL[3]) to activate UART controller. + * |[13] |RTSSTS |nRTS Pin Status (Read Only) + * | | |This bit mirror from nRTS pin output of voltage logic status. + * | | |0 = nRTS pin output is low level voltage logic state. + * | | |1 = nRTS pin output is high level voltage logic state. + * @var UART_T::MODEMSTS + * Offset: 0x14 UART Modem Status Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[0] |CTSDETF |Detect nCTS State Change Flag + * | | |This bit is set whenever nCTS input has change state, and it will generate Modem interrupt to CPU when MODEMIEN (UART_INTEN [3]) is set to 1. + * | | |0 = nCTS input has not change state. + * | | |1 = nCTS input has change state. + * | | |Note: This bit can be cleared by writing '1' to it. + * |[4] |CTSSTS |nCTS Pin Status (Read Only) + * | | |This bit mirror from nCTS pin input of voltage logic status. + * | | |0 = nCTS pin input is low level voltage logic state. + * | | |1 = nCTS pin input is high level voltage logic state. + * | | |Note: This bit echoes when UART controller peripheral clock is enabled, and nCTS multi-function port is selected. + * |[8] |CTSACTLV |nCTS Pin Active Level + * | | |This bit defines the active level state of nCTS pin input. + * | | |0 = nCTS pin input is high level active. + * | | |1 = nCTS pin input is low level active. (Default) + * | | |Note: Before setting this bit, TXRXDIS (UART_FUNCSEL[3]) should be set then waited for TXRXACT (UART_FIFOSTS[31]) is cleared + * | | |When the configuration is done, cleared TXRXDIS (UART_FUNCSEL[3]) to activate UART controller. + * @var UART_T::FIFOSTS + * Offset: 0x18 UART FIFO Status Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[0] |RXOVIF |RX Overflow Error Interrupt Flag + * | | |This bit is set when RX FIFO overflow. + * | | |If the number of bytes of received data is greater than RX_FIFO (UART_DAT) size 16 bytes, this bit will be set. + * | | |0 = RX FIFO is not overflow. + * | | |1 = RX FIFO is overflow. + * | | |Note: This bit can be cleared by writing '1' to it. + * |[1] |ABRDIF |Auto-baud Rate Detect Interrupt Flag + * | | |This bit is set to logic '1' when auto-baud rate detect function is finished. + * | | |0 = Auto-baud rate detect function is not finished. + * | | |1 = Auto-baud rate detect function is finished. + * | | |Note: This bit can be cleared by writing '1' to it. + * |[2] |ABRDTOIF |Auto-baud Rate Detect Time-out Interrupt Flag + * | | |This bit is set to logic '1' in Auto-baud Rate Detect mode when the baud rate counter is overflow. + * | | |0 = Auto-baud rate counter is underflow. + * | | |1 = Auto-baud rate counter is overflow. + * | | |Note: This bit can be cleared by writing '1' to it. + * |[3] |ADDRDETF |RS-485 Address Byte Detect Flag + * | | |0 = Receiver detects a data that is not an address bit (bit 9 ='0'). + * | | |1 = Receiver detects a data that is an address bit (bit 9 ='1'). + * | | |Note 1: This field is used for RS-485 function mode and ADDRDEN (UART_ALTCTL[15]) is set to 1 to enable Address detection mode. + * | | |Note 2: This bit can be cleared by writing '1' to it. + * |[4] |PEF |Parity Error Flag + * | | |This bit is set to logic 1 whenever the received character does not have a valid 'parity bit'. + * | | |0 = No parity error is generated. + * | | |1 = Parity error is generated. + * | | |Note: This bit can be cleared by writing '1' to it. + * |[5] |FEF |Framing Error Flag + * | | |This bit is set to logic 1 whenever the received character does not have a valid 'stop bit' + * | | |(that is, the stop bit following the last data bit or parity bit is detected as logic 0). + * | | |0 = No framing error is generated. + * | | |1 = Framing error is generated. + * | | |Note: This bit can be cleared by writing '1' to it. + * |[6] |BIF |Break Interrupt Flag + * | | |This bit is set to logic 1 whenever the received data input (RX) is held in the 'spacing state' (logic 0) + * | | |for longer than a full word transmission time (that is, the total time of 'start bit' + data bits + parity + stop bits). + * | | |0 = No Break interrupt is generated. + * | | |1 = Break interrupt is generated. + * | | |Note: This bit can be cleared by writing '1' to it. + * |[13:8] |RXPTR |RX FIFO Pointer (Read Only) + * | | |This field indicates the RX FIFO Buffer Pointer + * | | |When UART receives one byte from external device, RXPTR increases one + * | | |When one byte of RX FIFO is read by CPU, RXPTR decreases one. + * | | |The Maximum value shown in RXPTR is 15 + * | | |When the using level of RX FIFO Buffer equal to 16, the RXFULL bit is set to 1 and RXPTR will show 0 + * | | |As one byte of RX FIFO is read by CPU, the RXFULL bit is cleared to 0 and RXPTR will show 15 + * |[14] |RXEMPTY |Receiver FIFO Empty (Read Only) + * | | |This bit initiate RX FIFO empty or not. + * | | |0 = RX FIFO is not empty. + * | | |1 = RX FIFO is empty. + * | | |Note: When the last byte of RX FIFO has been read by CPU, hardware sets this bit high + * | | |It will be cleared when UART receives any new data. + * |[15] |RXFULL |Receiver FIFO Full (Read Only) + * | | |This bit initiates RX FIFO full or not. + * | | |0 = RX FIFO is not full. + * | | |1 = RX FIFO is full. + * | | |Note: This bit is set when the number of usage in RX FIFO Buffer is equal to 16, otherwise it is cleared by hardware. + * |[21:16] |TXPTR |TX FIFO Pointer (Read Only) + * | | |This field indicates the TX FIFO Buffer Pointer + * | | |When CPU writes one byte into UART_DAT, TXPTR increases one + * | | |When one byte of TX FIFO is transferred to Transmitter Shift Register, TXPTR decreases one. + * | | |The Maximum value shown in TXPTR is 15 + * | | |When the using level of TX FIFO Buffer equal to 16, the TXFULL bit is set to 1 and TXPTR will show 0 + * | | |As one byte of TX FIFO is transferred to Transmitter Shift Register, the TXFULL bit is cleared to 0 and TXPTR will show 15 + * |[22] |TXEMPTY |Transmitter FIFO Empty (Read Only) + * | | |This bit indicates TX FIFO empty or not. + * | | |0 = TX FIFO is not empty. + * | | |1 = TX FIFO is empty. + * | | |Note: When the last byte of TX FIFO has been transferred to Transmitter Shift Register, hardware sets this bit high + * | | |It will be cleared when writing data into UART_DAT (TX FIFO not empty). + * |[23] |TXFULL |Transmitter FIFO Full (Read Only) + * | | |This bit indicates TX FIFO full or not. + * | | |0 = TX FIFO is not full. + * | | |1 = TX FIFO is full. + * | | |Note: This bit is set when the number of usage in TX FIFO Buffer is equal to 16, otherwise it is cleared by hardware. + * |[24] |TXOVIF |TX Overflow Error Interrupt Flag + * | | |If TX FIFO (UART_DAT) is full, an additional write to UART_DAT will cause this bit to logic 1. + * | | |0 = TX FIFO is not overflow. + * | | |1 = TX FIFO is overflow. + * | | |Note: This bit can be cleared by writing '1' to it. + * |[28] |TXEMPTYF |Transmitter Empty Flag (Read Only) + * | | |This bit is set by hardware when TX FIFO (UART_DAT) is empty and the STOP bit of the last byte has been transmitted. + * | | |0 = TX FIFO is not empty or the STOP bit of the last byte has been not transmitted. + * | | |1 = TX FIFO is empty and the STOP bit of the last byte has been transmitted. + * | | |Note: This bit is cleared automatically when TX FIFO is not empty or the last byte transmission has not completed. + * |[29] |RXIDLE |RX Idle Status (Read Only) + * | | |This bit is set by hardware when RX is idle. + * | | |0 = RX is busy. + * | | |1 = RX is idle. (Default) + * |[31] |TXRXACT |TX and RX Active Status (Read Only) + * | | |This bit indicates TX and RX are active or inactive. + * | | |0 = TX and RX are inactive. + * | | |1 = TX and RX are active. (Default) + * | | |Note: When TXRXDIS (UART_FUNCSEL[3]) is set and both TX and RX are in idle state, this bit is cleared + * | | |The UART controller cannot transmit or receive data at this moment + * | | |Otherwise this bit is set. + * @var UART_T::INTSTS + * Offset: 0x1C UART Interrupt Status Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[0] |RDAIF |Receive Data Available Interrupt Flag + * | | |When the number of bytes in the RX FIFO equals the RFITL then the RDAIF(UART_INTSTS[0]) will be set + * | | |If RDAIEN (UART_INTEN [0]) is enabled, the RDA interrupt will be generated. + * | | |0 = No RDA interrupt flag is generated. + * | | |1 = RDA interrupt flag is generated. + * | | |Note: This bit is read only and it will be cleared when the number of unread bytes of RX FIFO drops below the threshold level (RFITL(UART_FIFO[7:4]). + * |[1] |THREIF |Transmit Holding Register Empty Interrupt Flag + * | | |This bit is set when the last data of TX FIFO is transferred to Transmitter Shift Register + * | | |If THREIEN (UART_INTEN[1]) is enabled, the THRE interrupt will be generated. + * | | |0 = No THRE interrupt flag is generated. + * | | |1 = THRE interrupt flag is generated. + * | | |Note: This bit is read only and it will be cleared when writing data into UART_DAT (TX FIFO not empty). + * |[2] |RLSIF |Receive Line Interrupt Flag (Read Only) + * | | |This bit is set when the RX receive data have parity error, frame error or break error (at least one of 3 bits, BIF(UART_FIFOSTS[6]), FEF(UART_FIFOSTS[5]) and PEF(UART_FIFOSTS[4]), is set) + * | | |If RLSIEN (UART_INTEN [2]) is enabled, the RLS interrupt will be generated. + * | | |0 = No RLS interrupt flag is generated. + * | | |1 = RLS interrupt flag is generated. + * | | |Note 1: In RS-485 function mode, this field is set include "receiver detect and received address byte character (bit9 = '1') bit" + * | | |At the same time, the bit of ADDRDETF (UART_FIFOSTS[3]) is also set. + * | | |Note 2: This bit is read only and reset to 0 when all bits of BIF (UART_FIFOSTS[6]), FEF(UART_FIFOSTS[5]) and PEF(UART_FIFOSTS[4]) are cleared. + * | | |Note 3: In RS-485 function mode, this bit is read only and reset to 0 when all bits of BIF (UART_FIFOSTS[6]), FEF(UART_FIFOSTS[5]), PEF(UART_FIFOSTS[4]) and ADDRDETF (UART_FIFOSTS[3]) are cleared. + * |[3] |MODEMIF |MODEM Interrupt Flag (Read Only) + * | | |This bit is set when the nCTS pin has state change (CTSDETF (UART_MODEMSTS[0]) = 1) + * | | |If MODEMIEN (UART_INTEN [3]) is enabled, the Modem interrupt will be generated. + * | | |0 = No Modem interrupt flag is generated. + * | | |1 = Modem interrupt flag is generated. + * | | |Note: This bit is read only and reset to 0 when bit CTSDETF is cleared by a write 1 on CTSDETF(UART_MODEMSTS[0]). + * |[4] |RXTOIF |RX Time-out Interrupt Flag (Read Only) + * | | |This bit is set when the RX FIFO is not empty and no activities occurred in the RX FIFO and the time-out counter equal to TOIC (UART_TOUT[7:0]) + * | | |If RXTOIEN (UART_INTEN [4]) is enabled, the RX time-out interrupt will be generated. + * | | |0 = No RX time-out interrupt flag is generated. + * | | |1 = RX time-out interrupt flag is generated. + * | | |Note: This bit is read only and user can read UART_DAT (RX is in active) to clear it. + * |[5] |BUFEIF |Buffer Error Interrupt Flag (Read Only) + * | | |This bit is set when the TX FIFO or RX FIFO overflows (TXOVIF (UART_FIFOSTS[24]) or RXOVIF (UART_FIFOSTS[0]) is set) + * | | |When BUFERRIF (UART_INTSTS[5]) is set, the transfer is not correct + * | | |If BUFERRIEN (UART_INTEN [5]) is enabled, the buffer error interrupt will be generated. + * | | |0 = No buffer error interrupt flag is generated. + * | | |1 = Buffer error interrupt flag is generated. + * | | |Note: This bit is cleared if both of RXOVIF(UART_FIFOSTS[0]) and TXOVIF(UART_FIFOSTS[24]) are cleared to 0 by writing 1 to RXOVIF(UART_FIFOSTS[0]) and TXOVIF(UART_FIFOSTS[24]). + * |[6] |WKIF |UART Wake-up Interrupt Flag (Read Only) + * | | |This bit is set when TOUTWKF (UART_WKSTS[4]), RS485WKF (UART_WKSTS[3]), RFRTWKF (UART_WKSTS[2]), DATWKF (UART_WKSTS[1]) or CTSWKF(UART_WKSTS[0]) is set to 1. + * | | |0 = No UART wake-up interrupt flag is generated. + * | | |1 = UART wake-up interrupt flag is generated. + * | | |Note: This bit is cleared if all of TOUTWKF, RS485WKF, RFRTWKF, DATWKF and CTSWKF are cleared to 0 by writing 1 to the corresponding interrupt flag. + * |[8] |RDAINT |Receive Data Available Interrupt Indicator (Read Only) + * | | |This bit is set if RDAIEN (UART_INTEN[0]) and RDAIF (UART_INTSTS[0]) are both set to 1. + * | | |0 = No RDA interrupt is generated. + * | | |1 = RDA interrupt is generated. + * |[9] |THREINT |Transmit Holding Register Empty Interrupt Indicator (Read Only) + * | | |This bit is set if THREIEN (UART_INTEN[1]) and THREIF(UART_INTSTS[1]) are both set to 1. + * | | |0 = No THRE interrupt is generated. + * | | |1 = THRE interrupt is generated. + * |[10] |RLSINT |Receive Line Status Interrupt Indicator (Read Only) + * | | |This bit is set if RLSIEN (UART_INTEN[2]) and RLSIF(UART_INTSTS[2]) are both set to 1. + * | | |0 = No RLS interrupt is generated. + * | | |1 = RLS interrupt is generated. + * |[11] |MODEMINT |MODEM Status Interrupt Indicator (Read Only) + * | | |This bit is set if MODEMIEN(UART_INTEN[3]) and MODEMIF(UART_INTSTS[3]) are both set to 1 + * | | |0 = No Modem interrupt is generated. + * | | |1 = Modem interrupt is generated. + * |[12] |RXTOINT |RX Time-out Interrupt Indicator (Read Only) + * | | |This bit is set if RXTOIEN (UART_INTEN[4]) and RXTOIF(UART_INTSTS[4]) are both set to 1. + * | | |0 = No RX time-out interrupt is generated. + * | | |1 = RX time-out interrupt is generated. + * |[13] |BUFEINT |Buffer Error Interrupt Indicator (Read Only) + * | | |This bit is set if BUFERRIEN(UART_INTEN[5]) and BUFERRIF(UART_ INTSTS[5]) are both set to 1. + * | | |0 = No buffer error interrupt is generated. + * | | |1 = Buffer error interrupt is generated. + * |[14] |WKINT |UART Wake-up Interrupt Indicator (Read Only) + * | | |This bit is set if WKIEN (UART_INTEN[6]) and WKIF (UART_INTSTS[6]) are both set to 1. + * | | |0 = No UART wake-up interrupt is generated. + * | | |1 = UART wake-up interrupt is generated. + * |[16] |SWBEIF |Single-wire Bit Error Detection Interrupt Flag + * | | |This bit is set when the single wire bus state not equals to UART controller TX state in Single-wire mode. + * | | |0 = No single-wire bit error detection interrupt flag is generated. + * | | |1 = Single-wire bit error detection interrupt flag is generated. + * | | |Note 1: This bit is active when FUNCSEL (UART_FUNCSEL[2:0]) is select UART Single-wire mode. + * | | |Note 2: This bit can be cleared by writing '1' to it. + * |[18] |PRLSIF |PDMA Mode Receive Line Status Flag (Read Only) + * | | |This bit is set when the RX receive data have parity error, frame error or break error (at least one of 3 bits, BIF (UART_FIFOSTS[6]), FEF (UART_FIFOSTS[5]) and PEF (UART_FIFOSTS[4]) is set) + * | | |If RLSIEN (UART_INTEN [2]) is enabled, the RLS interrupt will be generated. + * | | |0 = No RLS interrupt flag is generated in PDMA mode. + * | | |1 = RLS interrupt flag is generated in PDMA mode. + * | | |Note 1: In RS-485 function mode, this field include "receiver detect any address byte received address byte character (bit9 = '1') bit". + * | | |Note 2: In UART function mode, this bit is read only and reset to 0 when all bits of BIF(UART_FIFOSTS[6]), FEF(UART_FIFOSTS[5]) and PEF(UART_FIFOSTS[4]) are cleared. + * | | |Note 3: In RS-485 function mode, this bit is read only and reset to 0 when all bits of BIF(UART_FIFOSTS[6]), FEF(UART_FIFOSTS[5]), PEF(UART_FIFOSTS[4]) and ADDRDETF (UART_FIFOSTS[3]) are cleared + * |[19] |PMODIF |PDMA Mode MODEM Interrupt Flag (Read Only) + * | | |This bit is set when the nCTS pin has state change (CTSDETF (UART_MODEMSTS [0] =1)) + * | | |If MODEMIEN (UART_INTEN [3]) is enabled, the Modem interrupt will be generated. + * | | |0 = No Modem interrupt flag is generated in PDMA mode. + * | | |1 = Modem interrupt flag is generated in PDMA mode. + * | | |Note: This bit is read only and reset to 0 when the bit CTSDETF (UART_MODEMSTS[0]) is cleared by writing 1 on CTSDETF (UART_MODEMSTS [0]). + * |[20] |PTOIF |PDMA Mode RX Time-out Interrupt Flag (Read Only) + * | | |This bit is set when the RX FIFO is not empty and no activities occurred in the RX FIFO and the time-out counter equal to TOIC (UART_TOUT[7:0]) + * | | |If RXTOIEN (UART_INTEN [4]) is enabled, the RX time-out interrupt will be generated . + * | | |0 = No RX time-out interrupt flag is generated in PDMA mode. + * | | |1 = RX time-out interrupt flag is generated in PDMA mode. + * | | |Note: This bit is read only and user can read UART_DAT (RX is in active) to clear it. + * |[21] |PBUFEIF |PDMA Mode Buffer Error Interrupt Flag (Read Only) + * | | |This bit is set when the TX or RX FIFO overflows (TXOVIF (UART_FIFOSTS [24]) or RXOVIF (UART_FIFOSTS[0]) is set) + * | | |When BUFERRIF (UART_INTSTS[5]) is set, the transfer maybe is not correct + * | | |If BUFERRIEN (UART_INTEN [5]) is enabled, the buffer error interrupt will be generated. + * | | |0 = No buffer error interrupt flag is generated in PDMA mode. + * | | |1 = Buffer error interrupt flag is generated in PDMA mode. + * | | |Note: This bit is cleared when both TXOVIF (UART_FIFOSTS[24]) and RXOVIF (UART_FIFOSTS[0]) are cleared. + * |[22] |TXENDIF |Transmitter Empty Interrupt Flag + * | | |This bit is set when TX FIFO (UART_DAT) is empty and the STOP bit of the last byte has been transmitted (TXEMPTYF (UART_FIFOSTS[28]) is set) + * | | |If TXENDIEN (UART_INTEN[22]) is enabled, the Transmitter Empty interrupt will be generated. + * | | |0 = No transmitter empty interrupt flag is generated. + * | | |1 = Transmitter empty interrupt flag is generated. + * | | |Note: This bit is cleared automatically when TX FIFO is not empty or the last byte transmission has not completed. + * |[24] |SWBEINT |Single-wire Bit Error Detect Interrupt Indicator (Read Only) + * | | |This bit is set if SWBEIEN (UART_INTEN[16]) and SWBEIF (UART_INTSTS[16]) are both set to 1. + * | | |0 = No Single-wire Bit Error Detection Interrupt generated. + * | | |1 = Single-wire Bit Error Detection Interrupt generated. + * |[26] |PRLSINT |PDMA Mode Receive Line Status Interrupt Indicator (Read Only) + * | | |This bit is set if RLSIEN (UART_INTEN[2]) and HWRLSIF(UART_INTSTS[18]) are both set to 1. + * | | |0 = No RLS interrupt is generated in PDMA mode. + * | | |1 = RLS interrupt is generated in PDMA mode. + * |[27] |PMODINT |PDMA Mode MODEM Status Interrupt Indicator (Read Only) + * | | |This bit is set if MODEMIEN (UART_INTEN[3]) and HWMODIF(UART_INTSTS[19]) are both set to 1. + * | | |0 = No Modem interrupt is generated in PDMA mode. + * | | |1 = Modem interrupt is generated in PDMA mode. + * |[28] |PTOINT |PDMA Mode RX Time-out Interrupt Indicator (Read Only) + * | | |This bit is set if RXTOIEN (UART_INTEN[4]) and HWTOIF(UART_INTSTS[20]) are both set to 1. + * | | |0 = No RX time-out interrupt is generated in PDMA mode. + * | | |1 = RX time-out interrupt is generated in PDMA mode. + * |[29] |PBUFEINT |PDMA Mode Buffer Error Interrupt Indicator (Read Only) + * | | |This bit is set if BUFERRIEN (UART_INTEN[5]) and HWBUFEIF (UART_INTSTS[21]) are both set to 1. + * | | |0 = No buffer error interrupt is generated in PDMA mode. + * | | |1 = Buffer error interrupt is generated in PDMA mode. + * |[30] |TXENDINT |Transmitter Empty Interrupt Indicator (Read Only) + * | | |This bit is set if TXENDIEN (UART_INTEN[22]) and TXENDIF(UART_INTSTS[22]) are both set to 1. + * | | |0 = No Transmitter Empty interrupt is generated. + * | | |1 = Transmitter Empty interrupt is generated. + * |[31] |ABRINT |Auto-baud Rate Interrupt Indicator (Read Only) + * | | |This bit is set if ABRIEN (UART_INTEN[18]) and ABRIF (UART_ALTCTL[17]) are both set to 1. + * | | |0 = No Auto-baud Rate interrupt is generated. + * | | |1 = The Auto-baud Rate interrupt is generated. + * @var UART_T::TOUT + * Offset: 0x20 UART Time-out Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[7:0] |TOIC |Time-out Interrupt Comparator + * | | |The time-out counter resets and starts counting (the counting clock = baud rate) whenever the RX FIFO receives a new data word if time out counter is enabled by setting TOCNTEN (UART_INTEN[11]) + * | | |Once the content of time-out counter is equal to that of time-out interrupt comparator (TOIC (UART_TOUT[7:0])), a receiver time-out interrupt (RXTOINT(UART_INTSTS[12])) is generated if RXTOIEN (UART_INTEN [4]) enabled + * | | |A new incoming data word or RX FIFO empty will clear RXTOIF (UART_INTSTS[4]) + * | | |In order to avoid receiver time-out interrupt generation immediately during one character is being received, TOIC value should be set between 40 and 255 + * | | |So, for example, if TOIC is set with 40, the time-out interrupt is generated after four characters are not received when 1 stop bit and no parity check is set for UART transfer. + * |[15:8] |DLY |TX Delay Time Value + * | | |This field is used to programming the transfer delay time between the last stop bit and next start bit + * | | |The unit is bit time. + * @var UART_T::BAUD + * Offset: 0x24 UART Baud Rate Divider Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[15:0] |BRD |Baud Rate Divider + * | | |The field indicates the baud rate divider + * | | |This filed is used in baud rate calculation + * | | |The detail description is shown in Table 6.24-4. + * |[27:24] |EDIVM1 |Extra Divider for BAUD Rate Mode 1 + * | | |This field is used for baud rate calculation in mode 1 and has no effect for baud rate calculation in mode 0 and mode 2 + * | | |The detail description is shown in Table 6.24-4 + * |[28] |BAUDM0 |BAUD Rate Mode Selection Bit 0 + * | | |This bit is baud rate mode selection bit 0 + * | | |UART provides three baud rate calculation modes + * | | |This bit combines with BAUDM1 (UART_BAUD[29]) to select baud rate calculation mode + * | | |The detail description is shown in Table 6.24-4. + * |[29] |BAUDM1 |BAUD Rate Mode Selection Bit 1 + * | | |This bit is baud rate mode selection bit 1 + * | | |UART provides three baud rate calculation modes + * | | |This bit combines with BAUDM0 (UART_BAUD[28]) to select baud rate calculation mode + * | | |The detail description is shown in Table 6.24-4. + * | | |Note: In IrDA mode must be operated in mode 0. + * @var UART_T::IRDA + * Offset: 0x28 UART IrDA Control Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[1] |TXEN |IrDA Receiver/Transmitter Selection Enable Bit + * | | |0 = IrDA Transmitter Disabled and Receiver Enabled. (Default) + * | | |1 = IrDA Transmitter Enabled and Receiver Disabled. + * |[5] |TXINV |IrDA Inverse Transmitting Output Signal + * | | |0 = None inverse transmitting signal. (Default). + * | | |1 = Inverse transmitting output signal. + * | | |Note 1: Before setting this bit, TXRXDIS (UART_FUNCSEL[3]) should be set then waited for TXRXACT (UART_FIFOSTS[31]) is cleared + * | | |When the configuration is done, cleared TXRXDIS (UART_FUNCSEL[3]) to activate UART controller. + * | | |Note 2: This bit is valid when FUNCSEL (UART_FUNCSEL[2:0]) is select IrDA function. + * |[6] |RXINV |IrDA Inverse Receive Input Signal + * | | |0 = None inverse receiving input signal. + * | | |1 = Inverse receiving input signal. (Default) + * | | |Note 1: Before setting this bit, TXRXDIS (UART_FUNCSEL[3]) should be set then waited for TXRXACT (UART_FIFOSTS[31]) is cleared + * | | |When the configuration is done, cleared TXRXDIS (UART_FUNCSEL[3]) to activate UART controller. + * | | |Note 2: This bit is valid when FUNCSEL (UART_FUNCSEL[2:0]) is select IrDA function. + * @var UART_T::ALTCTL + * Offset: 0x2C UART Alternate Control/Status Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[8] |RS485NMM |RS-485 Normal Multi-drop Operation Mode + * | | |0 = RS-485 Normal Multi-drop Operation mode (NMM) Disabled. + * | | |1 = RS-485 Normal Multi-drop Operation mode (NMM) Enabled. + * | | |Note: It cannot be active with RS-485_AAD operation mode. + * |[9] |RS485AAD |RS-485 Auto Address Detection Operation Mode + * | | |0 = RS-485 Auto Address Detection Operation mode (AAD) Disabled. + * | | |1 = RS-485 Auto Address Detection Operation mode (AAD) Enabled. + * | | |Note: It cannot be active with RS-485_NMM operation mode. + * |[10] |RS485AUD |RS-485 Auto Direction Function + * | | |0 = RS-485 Auto Direction Operation function (AUD) Disabled. + * | | |1 = RS-485 Auto Direction Operation function (AUD) Enabled. + * | | |Note: It can be active with RS-485_AAD or RS-485_NMM operation mode. + * |[15] |ADDRDEN |RS-485 Address Detection Enable Bit + * | | |This bit is used to enable RS-485 Address Detection mode. + * | | |0 = Address detection mode Disabled. + * | | |1 = Address detection mode Enabled. + * | | |Note: This bit is used for RS-485 any operation mode. + * |[17] |ABRIF |Auto-baud Rate Interrupt Flag (Read Only) + * | | |This bit is set when auto-baud rate detection function finished or the auto-baud rate counter was overflow and if ABRIEN(UART_INTEN [18]) is set then the auto-baud rate interrupt will be generated. + * | | |0 = No auto-baud rate interrupt flag is generated. + * | | |1 = Auto-baud rate interrupt flag is generated. + * | | |Note: This bit is read only, but it can be cleared by writing '1' to ABRDTOIF (UART_FIFOSTS[2]) and ABRDIF(UART_FIFOSTS[1]) + * |[18] |ABRDEN |Auto-baud Rate Detect Enable Bit + * | | |0 = Auto-baud rate detect function Disabled. + * | | |1 = Auto-baud rate detect function Enabled. + * | | |Note : This bit is cleared automatically after auto-baud detection is finished. + * |[20:19] |ABRDBITS |Auto-baud Rate Detect Bit Length + * | | |00 = 1-bit time from Start bit to the 1st rising edge. The input pattern shall be 0x01. + * | | |01 = 2-bit time from Start bit to the 1st rising edge. The input pattern shall be 0x02. + * | | |10 = 4-bit time from Start bit to the 1st rising edge. The input pattern shall be 0x08. + * | | |11 = 8-bit time from Start bit to the 1st rising edge. The input pattern shall be 0x80. + * | | |Note : The calculation of bit number includes the START bit. + * |[31:24] |ADDRMV |Address Match Value + * | | |This field contains the RS-485 address match values. + * | | |Note: This field is used for RS-485 auto address detection mode. + * @var UART_T::FUNCSEL + * Offset: 0x30 UART Function Select Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[2:0] |FUNCSEL |Function Select + * | | |000 = UART function. + * | | |010 = IrDA function. + * | | |011 = RS-485 function. + * | | |100 = UART Single-wire function. + * | | |Others = Reserved. + * |[3] |TXRXDIS |TX and RX Disable Bit + * | | |Setting this bit can disable TX and RX. + * | | |0 = TX and RX Enabled. + * | | |1 = TX and RX Disabled. + * | | |Note: The TX and RX will not be disabled immediately when this bit is set + * | | |The TX and RX complete current task before disable TX and RX are disabled + * | | |When TX and RX are disabled, the TXRXACT (UART_FIFOSTS[31]) is cleared. + * @var UART_T::BRCOMP + * Offset: 0x3C UART Baud Rate Compensation Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[8:0] |BRCOMP |Baud Rate Compensation Patten + * | | |These 9-bits are used to define the relative bit is compensated or not. + * | | |BRCOMP[7:0] is used to define the compensation of DAT (UART_DAT[7:0]) and BRCOM[8] is used to define PARITY (UART_DAT[8]). + * |[31] |BRCOMPD |Baud Rate Compensation Decrease + * | | |0 = Positive (increase one module clock) compensation for each compensated bit. + * | | |1 = Negative (decrease one module clock) compensation for each compensated bit. + * @var UART_T::WKCTL + * Offset: 0x40 UART Wake-up Control Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[0] |WKCTSEN |nCTS Wake-up Enable Bit + * | | |0 = nCTS Wake-up system function Disabled. + * | | |1 = nCTS Wake-up system function Enabled. + * | | |Note: When the system is in Power-down mode, an external nCTS change will wake up system from Power-down mode. + * |[1] |WKDATEN |Incoming Data Wake-up Enable Bit + * | | |0 = Incoming data wake-up system function Disabled. + * | | |1 = Incoming data wake-up system function Enabled. + * | | |Note: When the system is in Power-down mode, incoming data will wake-up system from Power-down mode. + * |[2] |WKRFRTEN |Received Data FIFO Reached Threshold Wake-up Enable Bit + * | | |0 = Received Data FIFO reached threshold wake-up system function Disabled. + * | | |1 = Received Data FIFO reached threshold wake-up system function Enabled. + * | | |Note: When the system is in Power-down mode, Received Data FIFO reached threshold will wake-up system from Power-down mode. + * |[3] |WKAADEN |RS-485 Address Match Wake-up Enable Bit + * | | |0 = RS-485 Address Match (AAD mode) wake-up system function Disabled. + * | | |1 = RS-485 Address Match (AAD mode) wake-up system function Enabled. + * | | |Note 1: When the system is in .Power-down mode, RS-485 Address Match will wake -up system from Power-down mode. + * | | |Note 2: This bit is used for RS-485 Auto Address Detection (AAD) mode in RS-485 function mode and ADDRDEN (UART_ALTCTL[15]) is set to 1. + * |[4] |WKTOUTEN |Received Data FIFO Reached Threshold Time-out Wake-up Enable Bit + * | | |0 = Received Data FIFO reached threshold time-out wake-up system function Disabled. + * | | |1 = Received Data FIFO reached threshold time-out wake-up system function Enabled. + * | | |Note 1: When the system is in Power-down mode, Received Data FIFO reached threshold time-out will wake up system from Power-down mode. + * | | |Note 2: It is suggested the function is enabled when the WKRFRTEN (UART_WKCTL[2]) is set to 1. + * @var UART_T::WKSTS + * Offset: 0x44 UART Wake-up Status Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[0] |CTSWKF |nCTS Wake-up Flag + * | | |This bit is set if chip wake-up from power-down state by nCTS wake-up. + * | | |0 = Chip stays in power-down state. + * | | |1 = Chip wake-up from power-down state by nCTS wake-up. + * | | |Note 1: If WKCTSEN (UART_WKCTL[0]) is enabled, the nCTS wake-up cause this bit is set to '1'. + * | | |Note 2: This bit can be cleared by writing '1' to it. + * |[1] |DATWKF |Incoming Data Wake-up Flag + * | | |This bit is set if chip wake-up from power-down state by data wake-up. + * | | |0 = Chip stays in power-down state. + * | | |1 = Chip wake-up from power-down state by Incoming Data wake-up. + * | | |Note 1: If WKDATEN (UART_WKCTL[1]) is enabled, the Incoming Data wake-up cause this bit is set to '1'. + * | | |Note 2: This bit can be cleared by writing '1' to it. + * |[2] |RFRTWKF |Received Data FIFO Reached Threshold Wake-up Flag + * | | |This bit is set if chip wake-up from power-down state by Received Data FIFO reached threshold + * | | |wake-up . + * | | |0 = Chip stays in power-down state. + * | | |1 = Chip wake-up from power-down state by Received Data FIFO Reached Threshold wake-up. + * | | |Note 1: If WKRFRTEN (UART_WKCTL[2]) is enabled, the Received Data FIFO Reached Threshold wake-up cause this bit is set to '1'. + * | | |Note 2: This bit can be cleared by writing '1' to it. + * |[3] |RS485WKF |RS-485 Address Match Wake-up Flag + * | | |This bit is set if chip wake-up from power-down state by RS-485 Address Match (AAD mode). + * | | |0 = Chip stays in power-down state. + * | | |1 = Chip wake-up from power-down state by RS-485 Address Match (AAD mode) wake-up. + * | | |Note 1: If WKRS485EN (UART_WKCTL[3]) is enabled, the RS-485 Address Match (AAD mode) wake-up cause this bit is set to '1'. + * | | |Note 2: This bit can be cleared by writing '1' to it. + * |[4] |TOUTWKF |Received Data FIFO Threshold Time-out Wake-up Flag + * | | |This bit is set if chip wake-up from power-down state by Received Data FIFO Threshold Time-out wake-up. + * | | |0 = Chip stays in power-down state. + * | | |1 = Chip wake-up from power-down state by Received Data FIFO reached threshold time-out. + * | | |Note 1: If WKTOUTEN (UART_WKCTL[4]) is enabled, the Received Data FIFO reached threshold time-out wake-up cause this bit is set to '1'. + * | | |Note 2: This bit can be cleared by writing '1' to it. + * @var UART_T::DWKCOMP + * Offset: 0x48 UART Incoming Data Wake-up Compensation Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[15:0] |STCOMP |Start Bit Compensation Value + * | | |These bits field indicate how many clock cycle selected by UART_CLK do the UART controller can get the 1st bit (start bit) when the device is woken up from Power-down mode. + * | | |Note: It is valid only when WKDATEN (UART_WKCTL[1]) is set. + */ + __IO uint32_t DAT; /*!< [0x0000] UART Receive/Transmit Buffer Register */ + __IO uint32_t INTEN; /*!< [0x0004] UART Interrupt Enable Register */ + __IO uint32_t FIFO; /*!< [0x0008] UART FIFO Control Register */ + __IO uint32_t LINE; /*!< [0x000c] UART Line Control Register */ + __IO uint32_t MODEM; /*!< [0x0010] UART Modem Control Register */ + __IO uint32_t MODEMSTS; /*!< [0x0014] UART Modem Status Register */ + __IO uint32_t FIFOSTS; /*!< [0x0018] UART FIFO Status Register */ + __IO uint32_t INTSTS; /*!< [0x001c] UART Interrupt Status Register */ + __IO uint32_t TOUT; /*!< [0x0020] UART Time-out Register */ + __IO uint32_t BAUD; /*!< [0x0024] UART Baud Rate Divider Register */ + __IO uint32_t IRDA; /*!< [0x0028] UART IrDA Control Register */ + __IO uint32_t ALTCTL; /*!< [0x002c] UART Alternate Control/Status Register */ + __IO uint32_t FUNCSEL; /*!< [0x0030] UART Function Select Register */ + __I uint32_t RESERVE0[2]; + __IO uint32_t BRCOMP; /*!< [0x003c] UART Baud Rate Compensation Register */ + __IO uint32_t WKCTL; /*!< [0x0040] UART Wake-up Control Register */ + __IO uint32_t WKSTS; /*!< [0x0044] UART Wake-up Status Register */ + __IO uint32_t DWKCOMP; /*!< [0x0048] UART Incoming Data Wake-up Compensation Register */ + +} UART_T; + +/** + @addtogroup UART_CONST UART Bit Field Definition + Constant Definitions for UART Controller +@{ */ + +#define UART_DAT_DAT_Pos (0) /*!< UART_T::DAT: DAT Position */ +#define UART_DAT_DAT_Msk (0xfful << UART_DAT_DAT_Pos) /*!< UART_T::DAT: DAT Mask */ + +#define UART_DAT_PARITY_Pos (8) /*!< UART_T::DAT: PARITY Position */ +#define UART_DAT_PARITY_Msk (0x1ul << UART_DAT_PARITY_Pos) /*!< UART_T::DAT: PARITY Mask */ + +#define UART_INTEN_RDAIEN_Pos (0) /*!< UART_T::INTEN: RDAIEN Position */ +#define UART_INTEN_RDAIEN_Msk (0x1ul << UART_INTEN_RDAIEN_Pos) /*!< UART_T::INTEN: RDAIEN Mask */ + +#define UART_INTEN_THREIEN_Pos (1) /*!< UART_T::INTEN: THREIEN Position */ +#define UART_INTEN_THREIEN_Msk (0x1ul << UART_INTEN_THREIEN_Pos) /*!< UART_T::INTEN: THREIEN Mask */ + +#define UART_INTEN_RLSIEN_Pos (2) /*!< UART_T::INTEN: RLSIEN Position */ +#define UART_INTEN_RLSIEN_Msk (0x1ul << UART_INTEN_RLSIEN_Pos) /*!< UART_T::INTEN: RLSIEN Mask */ + +#define UART_INTEN_MODEMIEN_Pos (3) /*!< UART_T::INTEN: MODEMIEN Position */ +#define UART_INTEN_MODEMIEN_Msk (0x1ul << UART_INTEN_MODEMIEN_Pos) /*!< UART_T::INTEN: MODEMIEN Mask */ + +#define UART_INTEN_RXTOIEN_Pos (4) /*!< UART_T::INTEN: RXTOIEN Position */ +#define UART_INTEN_RXTOIEN_Msk (0x1ul << UART_INTEN_RXTOIEN_Pos) /*!< UART_T::INTEN: RXTOIEN Mask */ + +#define UART_INTEN_BUFEIEN_Pos (5) /*!< UART_T::INTEN: BUFEIEN Position */ +#define UART_INTEN_BUFEIEN_Msk (0x1ul << UART_INTEN_BUFEIEN_Pos) /*!< UART_T::INTEN: BUFEIEN Mask */ + +#define UART_INTEN_WKIEN_Pos (6) /*!< UART_T::INTEN: WKIEN Position */ +#define UART_INTEN_WKIEN_Msk (0x1ul << UART_INTEN_WKIEN_Pos) /*!< UART_T::INTEN: WKIEN Mask */ + +#define UART_INTEN_TOCNTEN_Pos (11) /*!< UART_T::INTEN: TOCNTEN Position */ +#define UART_INTEN_TOCNTEN_Msk (0x1ul << UART_INTEN_TOCNTEN_Pos) /*!< UART_T::INTEN: TOCNTEN Mask */ + +#define UART_INTEN_ATORTSEN_Pos (12) /*!< UART_T::INTEN: ATORTSEN Position */ +#define UART_INTEN_ATORTSEN_Msk (0x1ul << UART_INTEN_ATORTSEN_Pos) /*!< UART_T::INTEN: ATORTSEN Mask */ + +#define UART_INTEN_ATOCTSEN_Pos (13) /*!< UART_T::INTEN: ATOCTSEN Position */ +#define UART_INTEN_ATOCTSEN_Msk (0x1ul << UART_INTEN_ATOCTSEN_Pos) /*!< UART_T::INTEN: ATOCTSEN Mask */ + +#define UART_INTEN_TXPDMAEN_Pos (14) /*!< UART_T::INTEN: TXPDMAEN Position */ +#define UART_INTEN_TXPDMAEN_Msk (0x1ul << UART_INTEN_TXPDMAEN_Pos) /*!< UART_T::INTEN: TXPDMAEN Mask */ + +#define UART_INTEN_RXPDMAEN_Pos (15) /*!< UART_T::INTEN: RXPDMAEN Position */ +#define UART_INTEN_RXPDMAEN_Msk (0x1ul << UART_INTEN_RXPDMAEN_Pos) /*!< UART_T::INTEN: RXPDMAEN Mask */ + +#define UART_INTEN_SWBEIEN_Pos (16) /*!< UART_T::INTEN: SWBEIEN Position */ +#define UART_INTEN_SWBEIEN_Msk (0x1ul << UART_INTEN_SWBEIEN_Pos) /*!< UART_T::INTEN: SWBEIEN Mask */ + +#define UART_INTEN_ABRIEN_Pos (18) /*!< UART_T::INTEN: ABRIEN Position */ +#define UART_INTEN_ABRIEN_Msk (0x1ul << UART_INTEN_ABRIEN_Pos) /*!< UART_T::INTEN: ABRIEN Mask */ + +#define UART_INTEN_TXENDIEN_Pos (22) /*!< UART_T::INTEN: TXENDIEN Position */ +#define UART_INTEN_TXENDIEN_Msk (0x1ul << UART_INTEN_TXENDIEN_Pos) /*!< UART_T::INTEN: TXENDIEN Mask */ + +#define UART_FIFO_RXRST_Pos (1) /*!< UART_T::FIFO: RXRST Position */ +#define UART_FIFO_RXRST_Msk (0x1ul << UART_FIFO_RXRST_Pos) /*!< UART_T::FIFO: RXRST Mask */ + +#define UART_FIFO_TXRST_Pos (2) /*!< UART_T::FIFO: TXRST Position */ +#define UART_FIFO_TXRST_Msk (0x1ul << UART_FIFO_TXRST_Pos) /*!< UART_T::FIFO: TXRST Mask */ + +#define UART_FIFO_RFITL_Pos (4) /*!< UART_T::FIFO: RFITL Position */ +#define UART_FIFO_RFITL_Msk (0xful << UART_FIFO_RFITL_Pos) /*!< UART_T::FIFO: RFITL Mask */ + +#define UART_FIFO_RXOFF_Pos (8) /*!< UART_T::FIFO: RXOFF Position */ +#define UART_FIFO_RXOFF_Msk (0x1ul << UART_FIFO_RXOFF_Pos) /*!< UART_T::FIFO: RXOFF Mask */ + +#define UART_FIFO_RTSTRGLV_Pos (16) /*!< UART_T::FIFO: RTSTRGLV Position */ +#define UART_FIFO_RTSTRGLV_Msk (0xful << UART_FIFO_RTSTRGLV_Pos) /*!< UART_T::FIFO: RTSTRGLV Mask */ + +#define UART_LINE_WLS_Pos (0) /*!< UART_T::LINE: WLS Position */ +#define UART_LINE_WLS_Msk (0x3ul << UART_LINE_WLS_Pos) /*!< UART_T::LINE: WLS Mask */ + +#define UART_LINE_NSB_Pos (2) /*!< UART_T::LINE: NSB Position */ +#define UART_LINE_NSB_Msk (0x1ul << UART_LINE_NSB_Pos) /*!< UART_T::LINE: NSB Mask */ + +#define UART_LINE_PBE_Pos (3) /*!< UART_T::LINE: PBE Position */ +#define UART_LINE_PBE_Msk (0x1ul << UART_LINE_PBE_Pos) /*!< UART_T::LINE: PBE Mask */ + +#define UART_LINE_EPE_Pos (4) /*!< UART_T::LINE: EPE Position */ +#define UART_LINE_EPE_Msk (0x1ul << UART_LINE_EPE_Pos) /*!< UART_T::LINE: EPE Mask */ + +#define UART_LINE_SPE_Pos (5) /*!< UART_T::LINE: SPE Position */ +#define UART_LINE_SPE_Msk (0x1ul << UART_LINE_SPE_Pos) /*!< UART_T::LINE: SPE Mask */ + +#define UART_LINE_BCB_Pos (6) /*!< UART_T::LINE: BCB Position */ +#define UART_LINE_BCB_Msk (0x1ul << UART_LINE_BCB_Pos) /*!< UART_T::LINE: BCB Mask */ + +#define UART_LINE_PSS_Pos (7) /*!< UART_T::LINE: PSS Position */ +#define UART_LINE_PSS_Msk (0x1ul << UART_LINE_PSS_Pos) /*!< UART_T::LINE: PSS Mask */ + +#define UART_LINE_TXDINV_Pos (8) /*!< UART_T::LINE: TXDINV Position */ +#define UART_LINE_TXDINV_Msk (0x1ul << UART_LINE_TXDINV_Pos) /*!< UART_T::LINE: TXDINV Mask */ + +#define UART_LINE_RXDINV_Pos (9) /*!< UART_T::LINE: RXDINV Position */ +#define UART_LINE_RXDINV_Msk (0x1ul << UART_LINE_RXDINV_Pos) /*!< UART_T::LINE: RXDINV Mask */ + +#define UART_MODEM_RTS_Pos (1) /*!< UART_T::MODEM: RTS Position */ +#define UART_MODEM_RTS_Msk (0x1ul << UART_MODEM_RTS_Pos) /*!< UART_T::MODEM: RTS Mask */ + +#define UART_MODEM_RTSACTLV_Pos (9) /*!< UART_T::MODEM: RTSACTLV Position */ +#define UART_MODEM_RTSACTLV_Msk (0x1ul << UART_MODEM_RTSACTLV_Pos) /*!< UART_T::MODEM: RTSACTLV Mask */ + +#define UART_MODEM_RTSSTS_Pos (13) /*!< UART_T::MODEM: RTSSTS Position */ +#define UART_MODEM_RTSSTS_Msk (0x1ul << UART_MODEM_RTSSTS_Pos) /*!< UART_T::MODEM: RTSSTS Mask */ + +#define UART_MODEMSTS_CTSDETF_Pos (0) /*!< UART_T::MODEMSTS: CTSDETF Position */ +#define UART_MODEMSTS_CTSDETF_Msk (0x1ul << UART_MODEMSTS_CTSDETF_Pos) /*!< UART_T::MODEMSTS: CTSDETF Mask */ + +#define UART_MODEMSTS_CTSSTS_Pos (4) /*!< UART_T::MODEMSTS: CTSSTS Position */ +#define UART_MODEMSTS_CTSSTS_Msk (0x1ul << UART_MODEMSTS_CTSSTS_Pos) /*!< UART_T::MODEMSTS: CTSSTS Mask */ + +#define UART_MODEMSTS_CTSACTLV_Pos (8) /*!< UART_T::MODEMSTS: CTSACTLV Position */ +#define UART_MODEMSTS_CTSACTLV_Msk (0x1ul << UART_MODEMSTS_CTSACTLV_Pos) /*!< UART_T::MODEMSTS: CTSACTLV Mask */ + +#define UART_FIFOSTS_RXOVIF_Pos (0) /*!< UART_T::FIFOSTS: RXOVIF Position */ +#define UART_FIFOSTS_RXOVIF_Msk (0x1ul << UART_FIFOSTS_RXOVIF_Pos) /*!< UART_T::FIFOSTS: RXOVIF Mask */ + +#define UART_FIFOSTS_ABRDIF_Pos (1) /*!< UART_T::FIFOSTS: ABRDIF Position */ +#define UART_FIFOSTS_ABRDIF_Msk (0x1ul << UART_FIFOSTS_ABRDIF_Pos) /*!< UART_T::FIFOSTS: ABRDIF Mask */ + +#define UART_FIFOSTS_ABRDTOIF_Pos (2) /*!< UART_T::FIFOSTS: ABRDTOIF Position */ +#define UART_FIFOSTS_ABRDTOIF_Msk (0x1ul << UART_FIFOSTS_ABRDTOIF_Pos) /*!< UART_T::FIFOSTS: ABRDTOIF Mask */ + +#define UART_FIFOSTS_ADDRDETF_Pos (3) /*!< UART_T::FIFOSTS: ADDRDETF Position */ +#define UART_FIFOSTS_ADDRDETF_Msk (0x1ul << UART_FIFOSTS_ADDRDETF_Pos) /*!< UART_T::FIFOSTS: ADDRDETF Mask */ + +#define UART_FIFOSTS_PEF_Pos (4) /*!< UART_T::FIFOSTS: PEF Position */ +#define UART_FIFOSTS_PEF_Msk (0x1ul << UART_FIFOSTS_PEF_Pos) /*!< UART_T::FIFOSTS: PEF Mask */ + +#define UART_FIFOSTS_FEF_Pos (5) /*!< UART_T::FIFOSTS: FEF Position */ +#define UART_FIFOSTS_FEF_Msk (0x1ul << UART_FIFOSTS_FEF_Pos) /*!< UART_T::FIFOSTS: FEF Mask */ + +#define UART_FIFOSTS_BIF_Pos (6) /*!< UART_T::FIFOSTS: BIF Position */ +#define UART_FIFOSTS_BIF_Msk (0x1ul << UART_FIFOSTS_BIF_Pos) /*!< UART_T::FIFOSTS: BIF Mask */ + +#define UART_FIFOSTS_RXPTR_Pos (8) /*!< UART_T::FIFOSTS: RXPTR Position */ +#define UART_FIFOSTS_RXPTR_Msk (0x3ful << UART_FIFOSTS_RXPTR_Pos) /*!< UART_T::FIFOSTS: RXPTR Mask */ + +#define UART_FIFOSTS_RXEMPTY_Pos (14) /*!< UART_T::FIFOSTS: RXEMPTY Position */ +#define UART_FIFOSTS_RXEMPTY_Msk (0x1ul << UART_FIFOSTS_RXEMPTY_Pos) /*!< UART_T::FIFOSTS: RXEMPTY Mask */ + +#define UART_FIFOSTS_RXFULL_Pos (15) /*!< UART_T::FIFOSTS: RXFULL Position */ +#define UART_FIFOSTS_RXFULL_Msk (0x1ul << UART_FIFOSTS_RXFULL_Pos) /*!< UART_T::FIFOSTS: RXFULL Mask */ + +#define UART_FIFOSTS_TXPTR_Pos (16) /*!< UART_T::FIFOSTS: TXPTR Position */ +#define UART_FIFOSTS_TXPTR_Msk (0x3ful << UART_FIFOSTS_TXPTR_Pos) /*!< UART_T::FIFOSTS: TXPTR Mask */ + +#define UART_FIFOSTS_TXEMPTY_Pos (22) /*!< UART_T::FIFOSTS: TXEMPTY Position */ +#define UART_FIFOSTS_TXEMPTY_Msk (0x1ul << UART_FIFOSTS_TXEMPTY_Pos) /*!< UART_T::FIFOSTS: TXEMPTY Mask */ + +#define UART_FIFOSTS_TXFULL_Pos (23) /*!< UART_T::FIFOSTS: TXFULL Position */ +#define UART_FIFOSTS_TXFULL_Msk (0x1ul << UART_FIFOSTS_TXFULL_Pos) /*!< UART_T::FIFOSTS: TXFULL Mask */ + +#define UART_FIFOSTS_TXOVIF_Pos (24) /*!< UART_T::FIFOSTS: TXOVIF Position */ +#define UART_FIFOSTS_TXOVIF_Msk (0x1ul << UART_FIFOSTS_TXOVIF_Pos) /*!< UART_T::FIFOSTS: TXOVIF Mask */ + +#define UART_FIFOSTS_TXEMPTYF_Pos (28) /*!< UART_T::FIFOSTS: TXEMPTYF Position */ +#define UART_FIFOSTS_TXEMPTYF_Msk (0x1ul << UART_FIFOSTS_TXEMPTYF_Pos) /*!< UART_T::FIFOSTS: TXEMPTYF Mask */ + +#define UART_FIFOSTS_RXIDLE_Pos (29) /*!< UART_T::FIFOSTS: RXIDLE Position */ +#define UART_FIFOSTS_RXIDLE_Msk (0x1ul << UART_FIFOSTS_RXIDLE_Pos) /*!< UART_T::FIFOSTS: RXIDLE Mask */ + +#define UART_FIFOSTS_TXRXACT_Pos (31) /*!< UART_T::FIFOSTS: TXRXACT Position */ +#define UART_FIFOSTS_TXRXACT_Msk (0x1ul << UART_FIFOSTS_TXRXACT_Pos) /*!< UART_T::FIFOSTS: TXRXACT Mask */ + +#define UART_INTSTS_RDAIF_Pos (0) /*!< UART_T::INTSTS: RDAIF Position */ +#define UART_INTSTS_RDAIF_Msk (0x1ul << UART_INTSTS_RDAIF_Pos) /*!< UART_T::INTSTS: RDAIF Mask */ + +#define UART_INTSTS_THREIF_Pos (1) /*!< UART_T::INTSTS: THREIF Position */ +#define UART_INTSTS_THREIF_Msk (0x1ul << UART_INTSTS_THREIF_Pos) /*!< UART_T::INTSTS: THREIF Mask */ + +#define UART_INTSTS_RLSIF_Pos (2) /*!< UART_T::INTSTS: RLSIF Position */ +#define UART_INTSTS_RLSIF_Msk (0x1ul << UART_INTSTS_RLSIF_Pos) /*!< UART_T::INTSTS: RLSIF Mask */ + +#define UART_INTSTS_MODEMIF_Pos (3) /*!< UART_T::INTSTS: MODEMIF Position */ +#define UART_INTSTS_MODEMIF_Msk (0x1ul << UART_INTSTS_MODEMIF_Pos) /*!< UART_T::INTSTS: MODEMIF Mask */ + +#define UART_INTSTS_RXTOIF_Pos (4) /*!< UART_T::INTSTS: RXTOIF Position */ +#define UART_INTSTS_RXTOIF_Msk (0x1ul << UART_INTSTS_RXTOIF_Pos) /*!< UART_T::INTSTS: RXTOIF Mask */ + +#define UART_INTSTS_BUFEIF_Pos (5) /*!< UART_T::INTSTS: BUFEIF Position */ +#define UART_INTSTS_BUFEIF_Msk (0x1ul << UART_INTSTS_BUFEIF_Pos) /*!< UART_T::INTSTS: BUFEIF Mask */ + +#define UART_INTSTS_WKIF_Pos (6) /*!< UART_T::INTSTS: WKIF Position */ +#define UART_INTSTS_WKIF_Msk (0x1ul << UART_INTSTS_WKIF_Pos) /*!< UART_T::INTSTS: WKIF Mask */ + +#define UART_INTSTS_RDAINT_Pos (8) /*!< UART_T::INTSTS: RDAINT Position */ +#define UART_INTSTS_RDAINT_Msk (0x1ul << UART_INTSTS_RDAINT_Pos) /*!< UART_T::INTSTS: RDAINT Mask */ + +#define UART_INTSTS_THREINT_Pos (9) /*!< UART_T::INTSTS: THREINT Position */ +#define UART_INTSTS_THREINT_Msk (0x1ul << UART_INTSTS_THREINT_Pos) /*!< UART_T::INTSTS: THREINT Mask */ + +#define UART_INTSTS_RLSINT_Pos (10) /*!< UART_T::INTSTS: RLSINT Position */ +#define UART_INTSTS_RLSINT_Msk (0x1ul << UART_INTSTS_RLSINT_Pos) /*!< UART_T::INTSTS: RLSINT Mask */ + +#define UART_INTSTS_MODEMINT_Pos (11) /*!< UART_T::INTSTS: MODEMINT Position */ +#define UART_INTSTS_MODEMINT_Msk (0x1ul << UART_INTSTS_MODEMINT_Pos) /*!< UART_T::INTSTS: MODEMINT Mask */ + +#define UART_INTSTS_RXTOINT_Pos (12) /*!< UART_T::INTSTS: RXTOINT Position */ +#define UART_INTSTS_RXTOINT_Msk (0x1ul << UART_INTSTS_RXTOINT_Pos) /*!< UART_T::INTSTS: RXTOINT Mask */ + +#define UART_INTSTS_BUFEINT_Pos (13) /*!< UART_T::INTSTS: BUFEINT Position */ +#define UART_INTSTS_BUFEINT_Msk (0x1ul << UART_INTSTS_BUFEINT_Pos) /*!< UART_T::INTSTS: BUFEINT Mask */ + +#define UART_INTSTS_WKINT_Pos (14) /*!< UART_T::INTSTS: WKINT Position */ +#define UART_INTSTS_WKINT_Msk (0x1ul << UART_INTSTS_WKINT_Pos) /*!< UART_T::INTSTS: WKINT Mask */ + +#define UART_INTSTS_SWBEIF_Pos (16) /*!< UART_T::INTSTS: SWBEIF Position */ +#define UART_INTSTS_SWBEIF_Msk (0x1ul << UART_INTSTS_SWBEIF_Pos) /*!< UART_T::INTSTS: SWBEIF Mask */ + +#define UART_INTSTS_PRLSIF_Pos (18) /*!< UART_T::INTSTS: PRLSIF Position */ +#define UART_INTSTS_PRLSIF_Msk (0x1ul << UART_INTSTS_PRLSIF_Pos) /*!< UART_T::INTSTS: PRLSIF Mask */ + +#define UART_INTSTS_PMODIF_Pos (19) /*!< UART_T::INTSTS: PMODIF Position */ +#define UART_INTSTS_PMODIF_Msk (0x1ul << UART_INTSTS_PMODIF_Pos) /*!< UART_T::INTSTS: PMODIF Mask */ + +#define UART_INTSTS_PTOIF_Pos (20) /*!< UART_T::INTSTS: PTOIF Position */ +#define UART_INTSTS_PTOIF_Msk (0x1ul << UART_INTSTS_PTOIF_Pos) /*!< UART_T::INTSTS: PTOIF Mask */ + +#define UART_INTSTS_PBUFEIF_Pos (21) /*!< UART_T::INTSTS: PBUFEIF Position */ +#define UART_INTSTS_PBUFEIF_Msk (0x1ul << UART_INTSTS_PBUFEIF_Pos) /*!< UART_T::INTSTS: PBUFEIF Mask */ + +#define UART_INTSTS_TXENDIF_Pos (22) /*!< UART_T::INTSTS: TXENDIF Position */ +#define UART_INTSTS_TXENDIF_Msk (0x1ul << UART_INTSTS_TXENDIF_Pos) /*!< UART_T::INTSTS: TXENDIF Mask */ + +#define UART_INTSTS_SWBEINT_Pos (24) /*!< UART_T::INTSTS: SWBEINT Position */ +#define UART_INTSTS_SWBEINT_Msk (0x1ul << UART_INTSTS_SWBEINT_Pos) /*!< UART_T::INTSTS: SWBEINT Mask */ + +#define UART_INTSTS_PRLSINT_Pos (26) /*!< UART_T::INTSTS: PRLSINT Position */ +#define UART_INTSTS_PRLSINT_Msk (0x1ul << UART_INTSTS_PRLSINT_Pos) /*!< UART_T::INTSTS: PRLSINT Mask */ + +#define UART_INTSTS_PMODINT_Pos (27) /*!< UART_T::INTSTS: PMODINT Position */ +#define UART_INTSTS_PMODINT_Msk (0x1ul << UART_INTSTS_PMODINT_Pos) /*!< UART_T::INTSTS: PMODINT Mask */ + +#define UART_INTSTS_PTOINT_Pos (28) /*!< UART_T::INTSTS: PTOINT Position */ +#define UART_INTSTS_PTOINT_Msk (0x1ul << UART_INTSTS_PTOINT_Pos) /*!< UART_T::INTSTS: PTOINT Mask */ + +#define UART_INTSTS_PBUFEINT_Pos (29) /*!< UART_T::INTSTS: PBUFEINT Position */ +#define UART_INTSTS_PBUFEINT_Msk (0x1ul << UART_INTSTS_PBUFEINT_Pos) /*!< UART_T::INTSTS: PBUFEINT Mask */ + +#define UART_INTSTS_TXENDINT_Pos (30) /*!< UART_T::INTSTS: TXENDINT Position */ +#define UART_INTSTS_TXENDINT_Msk (0x1ul << UART_INTSTS_TXENDINT_Pos) /*!< UART_T::INTSTS: TXENDINT Mask */ + +#define UART_INTSTS_ABRINT_Pos (31) /*!< UART_T::INTSTS: ABRINT Position */ +#define UART_INTSTS_ABRINT_Msk (0x1ul << UART_INTSTS_ABRINT_Pos) /*!< UART_T::INTSTS: ABRINT Mask */ + +#define UART_TOUT_TOIC_Pos (0) /*!< UART_T::TOUT: TOIC Position */ +#define UART_TOUT_TOIC_Msk (0xfful << UART_TOUT_TOIC_Pos) /*!< UART_T::TOUT: TOIC Mask */ + +#define UART_TOUT_DLY_Pos (8) /*!< UART_T::TOUT: DLY Position */ +#define UART_TOUT_DLY_Msk (0xfful << UART_TOUT_DLY_Pos) /*!< UART_T::TOUT: DLY Mask */ + +#define UART_BAUD_BRD_Pos (0) /*!< UART_T::BAUD: BRD Position */ +#define UART_BAUD_BRD_Msk (0xfffful << UART_BAUD_BRD_Pos) /*!< UART_T::BAUD: BRD Mask */ + +#define UART_BAUD_EDIVM1_Pos (24) /*!< UART_T::BAUD: EDIVM1 Position */ +#define UART_BAUD_EDIVM1_Msk (0xful << UART_BAUD_EDIVM1_Pos) /*!< UART_T::BAUD: EDIVM1 Mask */ + +#define UART_BAUD_BAUDM0_Pos (28) /*!< UART_T::BAUD: BAUDM0 Position */ +#define UART_BAUD_BAUDM0_Msk (0x1ul << UART_BAUD_BAUDM0_Pos) /*!< UART_T::BAUD: BAUDM0 Mask */ + +#define UART_BAUD_BAUDM1_Pos (29) /*!< UART_T::BAUD: BAUDM1 Position */ +#define UART_BAUD_BAUDM1_Msk (0x1ul << UART_BAUD_BAUDM1_Pos) /*!< UART_T::BAUD: BAUDM1 Mask */ + +#define UART_IRDA_TXEN_Pos (1) /*!< UART_T::IRDA: TXEN Position */ +#define UART_IRDA_TXEN_Msk (0x1ul << UART_IRDA_TXEN_Pos) /*!< UART_T::IRDA: TXEN Mask */ + +#define UART_IRDA_TXINV_Pos (5) /*!< UART_T::IRDA: TXINV Position */ +#define UART_IRDA_TXINV_Msk (0x1ul << UART_IRDA_TXINV_Pos) /*!< UART_T::IRDA: TXINV Mask */ + +#define UART_IRDA_RXINV_Pos (6) /*!< UART_T::IRDA: RXINV Position */ +#define UART_IRDA_RXINV_Msk (0x1ul << UART_IRDA_RXINV_Pos) /*!< UART_T::IRDA: RXINV Mask */ + +#define UART_ALTCTL_RS485NMM_Pos (8) /*!< UART_T::ALTCTL: RS485NMM Position */ +#define UART_ALTCTL_RS485NMM_Msk (0x1ul << UART_ALTCTL_RS485NMM_Pos) /*!< UART_T::ALTCTL: RS485NMM Mask */ + +#define UART_ALTCTL_RS485AAD_Pos (9) /*!< UART_T::ALTCTL: RS485AAD Position */ +#define UART_ALTCTL_RS485AAD_Msk (0x1ul << UART_ALTCTL_RS485AAD_Pos) /*!< UART_T::ALTCTL: RS485AAD Mask */ + +#define UART_ALTCTL_RS485AUD_Pos (10) /*!< UART_T::ALTCTL: RS485AUD Position */ +#define UART_ALTCTL_RS485AUD_Msk (0x1ul << UART_ALTCTL_RS485AUD_Pos) /*!< UART_T::ALTCTL: RS485AUD Mask */ + +#define UART_ALTCTL_ADDRDEN_Pos (15) /*!< UART_T::ALTCTL: ADDRDEN Position */ +#define UART_ALTCTL_ADDRDEN_Msk (0x1ul << UART_ALTCTL_ADDRDEN_Pos) /*!< UART_T::ALTCTL: ADDRDEN Mask */ + +#define UART_ALTCTL_ABRIF_Pos (17) /*!< UART_T::ALTCTL: ABRIF Position */ +#define UART_ALTCTL_ABRIF_Msk (0x1ul << UART_ALTCTL_ABRIF_Pos) /*!< UART_T::ALTCTL: ABRIF Mask */ + +#define UART_ALTCTL_ABRDEN_Pos (18) /*!< UART_T::ALTCTL: ABRDEN Position */ +#define UART_ALTCTL_ABRDEN_Msk (0x1ul << UART_ALTCTL_ABRDEN_Pos) /*!< UART_T::ALTCTL: ABRDEN Mask */ + +#define UART_ALTCTL_ABRDBITS_Pos (19) /*!< UART_T::ALTCTL: ABRDBITS Position */ +#define UART_ALTCTL_ABRDBITS_Msk (0x3ul << UART_ALTCTL_ABRDBITS_Pos) /*!< UART_T::ALTCTL: ABRDBITS Mask */ + +#define UART_ALTCTL_ADDRMV_Pos (24) /*!< UART_T::ALTCTL: ADDRMV Position */ +#define UART_ALTCTL_ADDRMV_Msk (0xfful << UART_ALTCTL_ADDRMV_Pos) /*!< UART_T::ALTCTL: ADDRMV Mask */ + +#define UART_FUNCSEL_FUNCSEL_Pos (0) /*!< UART_T::FUNCSEL: FUNCSEL Position */ +#define UART_FUNCSEL_FUNCSEL_Msk (0x7ul << UART_FUNCSEL_FUNCSEL_Pos) /*!< UART_T::FUNCSEL: FUNCSEL Mask */ + +#define UART_FUNCSEL_TXRXDIS_Pos (3) /*!< UART_T::FUNCSEL: TXRXDIS Position */ +#define UART_FUNCSEL_TXRXDIS_Msk (0x1ul << UART_FUNCSEL_TXRXDIS_Pos) /*!< UART_T::FUNCSEL: TXRXDIS Mask */ + +#define UART_BRCOMP_BRCOMP_Pos (0) /*!< UART_T::BRCOMP: BRCOMP Position */ +#define UART_BRCOMP_BRCOMP_Msk (0x1fful << UART_BRCOMP_BRCOMP_Pos) /*!< UART_T::BRCOMP: BRCOMP Mask */ + +#define UART_BRCOMP_BRCOMPD_Pos (31) /*!< UART_T::BRCOMP: BRCOMPD Position */ +#define UART_BRCOMP_BRCOMPD_Msk (0x1ul << UART_BRCOMP_BRCOMPD_Pos) /*!< UART_T::BRCOMP: BRCOMPD Mask */ + +#define UART_WKCTL_WKCTSEN_Pos (0) /*!< UART_T::WKCTL: WKCTSEN Position */ +#define UART_WKCTL_WKCTSEN_Msk (0x1ul << UART_WKCTL_WKCTSEN_Pos) /*!< UART_T::WKCTL: WKCTSEN Mask */ + +#define UART_WKCTL_WKDATEN_Pos (1) /*!< UART_T::WKCTL: WKDATEN Position */ +#define UART_WKCTL_WKDATEN_Msk (0x1ul << UART_WKCTL_WKDATEN_Pos) /*!< UART_T::WKCTL: WKDATEN Mask */ + +#define UART_WKCTL_WKRFRTEN_Pos (2) /*!< UART_T::WKCTL: WKRFRTEN Position */ +#define UART_WKCTL_WKRFRTEN_Msk (0x1ul << UART_WKCTL_WKRFRTEN_Pos) /*!< UART_T::WKCTL: WKRFRTEN Mask */ + +#define UART_WKCTL_WKAADEN_Pos (3) /*!< UART_T::WKCTL: WKAADEN Position */ +#define UART_WKCTL_WKAADEN_Msk (0x1ul << UART_WKCTL_WKAADEN_Pos) /*!< UART_T::WKCTL: WKAADEN Mask */ + +#define UART_WKCTL_WKTOUTEN_Pos (4) /*!< UART_T::WKCTL: WKTOUTEN Position */ +#define UART_WKCTL_WKTOUTEN_Msk (0x1ul << UART_WKCTL_WKTOUTEN_Pos) /*!< UART_T::WKCTL: WKTOUTEN Mask */ + +#define UART_WKSTS_CTSWKF_Pos (0) /*!< UART_T::WKSTS: CTSWKF Position */ +#define UART_WKSTS_CTSWKF_Msk (0x1ul << UART_WKSTS_CTSWKF_Pos) /*!< UART_T::WKSTS: CTSWKF Mask */ + +#define UART_WKSTS_DATWKF_Pos (1) /*!< UART_T::WKSTS: DATWKF Position */ +#define UART_WKSTS_DATWKF_Msk (0x1ul << UART_WKSTS_DATWKF_Pos) /*!< UART_T::WKSTS: DATWKF Mask */ + +#define UART_WKSTS_RFRTWKF_Pos (2) /*!< UART_T::WKSTS: RFRTWKF Position */ +#define UART_WKSTS_RFRTWKF_Msk (0x1ul << UART_WKSTS_RFRTWKF_Pos) /*!< UART_T::WKSTS: RFRTWKF Mask */ + +#define UART_WKSTS_RS485WKF_Pos (3) /*!< UART_T::WKSTS: RS485WKF Position */ +#define UART_WKSTS_RS485WKF_Msk (0x1ul << UART_WKSTS_RS485WKF_Pos) /*!< UART_T::WKSTS: RS485WKF Mask */ + +#define UART_WKSTS_TOUTWKF_Pos (4) /*!< UART_T::WKSTS: TOUTWKF Position */ +#define UART_WKSTS_TOUTWKF_Msk (0x1ul << UART_WKSTS_TOUTWKF_Pos) /*!< UART_T::WKSTS: TOUTWKF Mask */ + +#define UART_DWKCOMP_STCOMP_Pos (0) /*!< UART_T::DWKCOMP: STCOMP Position */ +#define UART_DWKCOMP_STCOMP_Msk (0xfffful << UART_DWKCOMP_STCOMP_Pos) /*!< UART_T::DWKCOMP: STCOMP Mask */ + +/**@}*/ /* UART_CONST */ +/**@}*/ /* end of UART register group */ +/**@}*/ /* end of REGISTER group */ + +#if defined ( __CC_ARM ) + #pragma no_anon_unions +#endif + +#endif /* __UART_REG_H__ */ diff --git a/bsp/nuvoton/libraries/ma35/Device/Nuvoton/MA35D1/Include/umctl2_reg.h b/bsp/nuvoton/libraries/ma35/Device/Nuvoton/MA35D1/Include/umctl2_reg.h new file mode 100644 index 0000000000..e886370146 --- /dev/null +++ b/bsp/nuvoton/libraries/ma35/Device/Nuvoton/MA35D1/Include/umctl2_reg.h @@ -0,0 +1,3918 @@ +/**************************************************************************//** + * @file umctl2_reg.h + * @brief UMCTL2 register definition header file + * + * SPDX-License-Identifier: Apache-2.0 + * @copyright (C) 2020 Nuvoton Technology Corp. All rights reserved. + *****************************************************************************/ +#ifndef __UMCTL2_REG_H__ +#define __UMCTL2_REG_H__ + +#if defined ( __CC_ARM ) + #pragma anon_unions +#endif + +/** @addtogroup REGISTER Control Register + + @{ + +*/ + + +/*---------------------- DDR Memory Controller -------------------------*/ +/** + @addtogroup UMCTL2 DDR Memory Controller (UMCTL2) + Memory Mapped Structure for UMCTL2 Controller +@{ */ + +typedef struct +{ + + + /** + * @var UMCTL2_T::MSTR + * Offset: 0x00 Master Register0 + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[0] |ddr3 |DDR3 SDRAM Type Enable Bit + * | | |Selects DDR3 SDRAM. + * | | |u00B7 1 - DDR3 SDRAM device in use + * | | |u00B7 0 - non-DDR3 SDRAM device in use + * | | |Present only in designs configured to support DDR3. + * | | |Programming Mode: Static + * |[9] |burstchop |Burst-Chop Enable Bit + * | | |When this bit is set, enables burst-chop (BC4 or 8 on-the-fly) in DDR3. + * | | |Burst Chop for reads is exercised only: + * | | |u00B7 If in full bus width mode (MSTR.data_bus_width = 00) + * | | |Burst Chop for writes is exercised only: + * | | |u00B7 If CRC is disabled (CRCPARCTL1.crc_enable = 0) + * | | |BC4 (fixed) mode is not supported. + * | | |Programming Mode: Static + * |[10] |en_2t_timing_mode|2T Timing Mode Enable Bit + * | | |If 1, then uMCTL2 uses 2T timing, otherwise uses 1T timing. + * | | |In 2T timing, all command signals (except chip select) are held for 2 clocks on the SDRAM bus + * | | |Chip select is asserted on the second cycle of the command. + * | | |Programming Mode: Static + * |[13:12] |data_bus_width|DQ Bus Width + * | | |Selects proportion of DQ bus width that is used by the SDRAM. + * | | |u00B7 00 - Full DQ bus width to SDRAM + * | | |u00B7 01 - Half DQ bus width to SDRAM + * | | |u00B7 10 - Reserved + * | | |u00B7 11 - Reserved + * | | |Note that half bus width mode is only supported when the SDRAM bus width is a multiple of 16 + * | | |Bus width refers to DQ bus width (excluding any ECC width). + * | | |Programming Mode: Static + * |[15] |dll_off_mode|DLL Off Mode Enable Bit + * | | |u00B7 1 - When the uMCTL2 and DRAM has to be put in DLL-off mode for low frequency operation + * | | |u00B7 0 - To put uMCTL2 and DRAM in DLL-on mode for normal frequency operation + * | | |Programming Mode: Quasi-dynamic Group 2 + * |[19:16] |burst_rdwr|Burst Length for Read and Write + * | | |Indicates SDRAM burst length used: + * | | |u00B7 0010 - Burst length of 4 + * | | |u00B7 0100 - Burst length of 8 + * | | |All other values are reserved. + * | | |This bit controls the burst size used to access the SDRAM + * | | |This must match the burst length mode register setting in the SDRAM + * | | |(For BC4/8 on-the-fly mode of DDR3, set this field to 0x0100) Burst length of 2 is not supported with AXI ports when MEMC_BURST_LENGTH is 8. + * | | |Burst length of 2 is only supported when the controller is operating in 1:1 frequency mode. + * | | |For DDR3, this must be set to 0x0100 (BL8). + * | | |Programming Mode: Static + * |[25:24] |active_ranks|Active Ranks + * | | |u00B7 01 - One rank + * | | |u00B7 11 - Two ranks + * | | |u00B7 Others - Reserved + * | | |Programming Mode: Static + * @var UMCTL2_T::STAT + * Offset: 0x04 Operating Mode Status Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[1:0] |operating_mode|Operating Mode + * | | |u00B7 00 - Init + * | | |u00B7 01 - Normal + * | | |u00B7 10 - Power-down + * | | |u00B7 11 - Self-refresh + * | | |Programming Mode: Static + * |[5:4] |selfref_type|Self-Refresh Type + * | | |Flags if self-refresh is entered, and if it is under automatic self-refresh control only or not. + * | | |u00B7 00 - SDRAM is not in self-refresh + * | | |If retry is enabled by CRCPARCTL1.crc_parity_retry_enable, this also indicates that the SRE command is still in parity error window or retry is in-progress. + * | | |u00B7 11 - SDRAM is in self-refresh, which was caused by Automatic self-refresh only + * | | |If retry is enabled, this ensures that the SRE command is executed correctly without parity error. + * | | |u00B7 10 - SDRAM is in self-refresh, which was not caused solely under automatic self-refresh control + * | | |It could have been caused by Hardware Low Power Interface and/or Software (PWRCTL.selfref_sw) + * | | |If retry is enabled, this ensures that the SRE command is executed correctly without parity error. + * | | |u00B7 01 - SDRAM is in self-refresh, which is caused by PHY Master Request. + * | | |Programming Mode: Static + * |[12] |selfref_cam_not_empty|Self-Refresh with CAMs Not Empty. + * | | |Set to 1 when self-refresh is entered but CAMs are not drained. + * | | |Cleared after exiting self-refresh. + * | | |Programming Mode: Static + * @var UMCTL2_T::MRCTRL0 + * Offset: 0x10 Mode Register Read/Write Control Register 0 + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[5:4] |mr_rank |Mode Register Accessing Rank + * | | |Controls which rank is accessed by MRCTRL0.mr_wr. + * | | |Normally, it is desired to access all ranks, so all bits must be set to 1. + * | | |Examples (assuming uMCTL2 is configured for 2 ranks): + * | | |u00B7 0x1 - Select rank 0 only + * | | |u00B7 0x2 - Select rank 1 only + * | | |u00B7 0x3 - Select ranks 0 and 1 + * | | |Programming Mode: Dynamic + * |[15:12] |mr_addr |Mode Register Address + * | | |Address of the mode register that is to be written to. + * | | |u00B7 0000 - MR0 + * | | |u00B7 0001 - MR1 + * | | |u00B7 0010 - MR2 + * | | |u00B7 0011 - MR3 + * | | |u00B7 0100 - MR4 + * | | |u00B7 0101 - MR5 + * | | |u00B7 0110 - MR6 + * | | |u00B7 0111 - MR7 + * | | |Programming Mode: Dynamic + * |[31] |mr_wr |Mode Register Read or Write Operation Trigger + * | | |Setting this register bit to 1 triggers a mode register read or write operation. + * | | |When the MR operation is complete, the uMCTL2 automatically clears this bit. + * | | |The other fields of this register must be written in a separate APB transaction, before setting this mr_wr bit. + * | | |It is recommended NOT to set this signal if in Init, Deep power-down, or MPSM operating modes. + * | | |Testable: readOnly + * | | |Programming Mode: Dynamic + * @var UMCTL2_T::MRCTRL1 + * Offset: 0x14 Mode Register Read/Write Control Register 1 + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[15:0] |mr_data |Mode Register Write Data + * | | |Mode register write data for all DDR2/DDR3 modes. + * | | |Programming Mode: Dynamic + * @var UMCTL2_T::MRSTAT + * Offset: 0x18 Mode Register Read/Write Status Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[0] |mr_wr_busy|Mode Register Write Busy + * | | |The SoC might initiate a MR write operation only if this signal is low. + * | | |This signal goes: + * | | |u00B7 High in the clock after the uMCTL2 accepts the MRW/MRR request + * | | |u00B7 Low when the MRW/MRR command is issued to the SDRAM + * | | |It is recommended not to perform MRW/MRR commands when 'MRSTAT.mr_wr_busy' is high. + * | | |u00B7 0 - Indicates that the SoC can initiate a mode register write operation + * | | |u00B7 1 - Indicates that mode register write operation is in progress + * | | |Programming Mode: Dynamic + * @var UMCTL2_T::PWRCTL + * Offset: 0x30 Low Power Control Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[0] |selfref_en|Self-Refresh Enable Bit + * | | |If it is true, then the uMCTL2 puts the SDRAM into self-refresh after a programmable number of cycles "maximum idle clocks before self-refresh (PWRTMG.selfref_to_x32)". + * | | |This register bit may be re-programmed during the course of normal operation. + * | | |Programming Mode: Dynamic + * |[1] |powerdown_en|Power-Down Enable Bit + * | | |If it is true, then the uMCTL2 goes into power-down after a programmable number of cycles "maximum idle clocks before power down" (PWRTMG.powerdown_to_x32). + * | | |This register bit may be re-programmed during the course of normal operation. + * | | |Programming Mode: Dynamic + * |[3] |en_dfi_dram_clk_disable|dfi_dram_clk_disable Enable Bit + * | | |Enables the assertion of dfi_dram_clk_disable whenever a clock is not required by the SDRAM. + * | | |If set to 0, dfi_dram_clk_disable is never asserted. + * | | |Assertion of dfi_dram_clk_disable is as follows: + * | | |In DDR2/DDR3, can only be asserted in self-refresh. + * | | |Programming Mode: Dynamic + * |[5] |selfref_sw|Self-Refresh Entry/Exit by Software + * | | |A value of 1 to this register causes system to move to self-refresh state immediately, as long as it is not in INIT or DPD/MPSM operating_mode. + * | | |This is referred to as Software Entry/Exit to self-refresh. + * | | |u00B7 1 - Software Entry to self-refresh + * | | |u00B7 0 - Software Exit from self-refresh + * | | |Programming Mode: Dynamic + * |[7] |dis_cam_drain_selfref|Disable CAM Drain Before Entering Self-Refresh + * | | |Indicates whether skipping CAM draining is allowed when entering self-refresh. + * | | |This register field cannot be modified while PWRCTL.selfref_sw == 1. + * | | |u00B7 0 - CAMs must be empty before entering SR + * | | |u00B7 1 - CAMs are not emptied before entering SR (unsupported) Note, PWRCTL.dis_cam_drain_selfref=1 is unsupported in this release + * | | |PWRCTL.dis_cam_drain_selfref=0 is required. + * | | |Programming Mode: Dynamic + * @var UMCTL2_T::PWRTMG + * Offset: 0x34 Low Power Timing Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[4:0] |powerdown_to_x32|SDRAM Power-Down Enter After This Clock Number + * | | |After this many clocks of the DDRC command channel being idle the uMCTL2 automatically puts the SDRAM into power-down. + * | | |The DDRC command channel is considered idle when there are no HIF commands outstanding + * | | |This must be enabled in the PWRCTL.powerdown_en. + * | | |FOR PERFORMANCE ONLY. + * | | |Unit: Multiples of 32 DFI clock cycles. + * | | |Programming Mode: Quasi-dynamic Group 4 + * |[23:16] |selfref_to_x32|SDRAM Self-Refresh Enter After This Clock Number + * | | |After this many clocks of the DDRC command channel being idle the uMCTL2 automatically puts the SDRAM into self-refresh. + * | | |The DDRC command channel is considered idle when there are no HIF commands outstanding + * | | |This must be enabled in the PWRCTL.selfref_en. + * | | |FOR PERFORMANCE ONLY. + * | | |Unit: Multiples of 32 DFI clock cycles. + * | | |Programming Mode: Quasi-dynamic Group 4 + * @var UMCTL2_T::HWLPCTL + * Offset: 0x38 Hardware Low Power Control Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[0] |hw_lp_en |Hardware Low Power Interface Enable Bit + * | | |Programming Mode: Quasi-dynamic Group 2 + * |[1] |hw_lp_exit_idle_en|Hardware Exit Idle Enable Bit + * | | |When this bit is programmed to 1 the cactive_in_ddrc pin of the DDRC can be used to exit from the automatic clock stop, automatic power down or automatic self-refresh modes. + * | | |Note, it does not cause exit of self-refresh that was caused by Hardware Low Power Interface and/or Software (PWRCTL.selfref_sw). + * | | |Programming Mode: Static + * |[27:16] |hw_lp_idle_x32|Hardware idle period. + * | | |The cactive_ddrc output is driven low if the DDRC command channel is idle for hw_lp_idle * 32 cycles if not in INIT or DPD/MPSM operating_mode. + * | | |The DDRC command channel is considered idle when there are no HIF commands outstanding + * | | |The hardware idle function is disabled when hw_lp_idle_x32=0 + * | | |hw_lp_idle_x32=1 is an illegal value. + * | | |FOR PERFORMANCE ONLY. + * | | |Unit: Multiples of 32 DFI clock cycles. + * | | |Programming Mode: Static + * @var UMCTL2_T::RFSHCTL0 + * Offset: 0x50 Refresh Control Register 0 + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[9:4] |refresh_burst|Refresh Burst Number + * | | |The programmed value + 1 is the number of refresh timeouts that is allowed to accumulate before traffic is blocked and the refreshes are forced to execute. + * | | |Closing pages to perform a refresh is a one-time penalty that must be paid for each group of refreshes + * | | |Therefore, performing refreshes in a burst reduces the per-refresh penalty of these page closings. + * | | |Higher numbers for RFSHCTL.refresh_burst slightly increase utilization; lower numbers decrease the worst-case latency associated with refreshes. + * | | |u00B7 0 - Single refresh + * | | |u00B7 1 - Burst-of-2 refresh + * | | |u00B7 7 - Burst-of-8 refresh + * | | |For more information on burst refresh feature, see section 3.9 of DDR2 JEDEC specification - JESD79-2F.pdf. + * | | |For DDR2/3, the refresh is always per-rank and not per-bank + * | | |The rank refresh can be accumulated over 8*tREFI cycles using the burst refresh feature. + * | | |If using PHY-initiated updates, care must be taken in the setting of RFSHCTL0.refresh_burst, to ensure that tRFCmax is not violated due to a PHY-initiated update occurring shortly before a refresh burst is due. + * | | |In this situation, the refresh burst is delayed until the PHY-initiated update is complete. + * | | |Programming Mode: Dynamic - Refresh Related + * |[16:12] |refresh_to_x1_x32|SDRAM Bus Idle Period + * | | |If the refresh timer (tRFCnom, also known as tREFI) has expired at least once, then a speculative refresh may be performed. + * | | |A speculative refresh is a refresh performed at a time when refresh would be useful + * | | |When the SDRAM bus is idle for a period of time determined by this RFSHCTL0.refresh_to_x1_x32 and the refresh timer has expired at least once since the last refresh, then a speculative refresh is performed. + * | | |Speculative refreshes continue successively until there are no refreshes pending or until new reads or writes are issued to the uMCTL2. + * | | |FOR PERFORMANCE ONLY. + * | | |Unit: DFI clock cycles or multiples of 32 DFI clock cycles, depending on RFSHTMG.t_rfc_nom_x1_sel. + * | | |Programming Mode: Dynamic - Refresh Related + * |[23:20] |refresh_margin|Refresh Margin + * | | |Threshold value in number of DFI clock cycles before the critical refresh or page timer expires. + * | | |A critical refresh is to be issued before this threshold is reached. + * | | |It is recommended that this not be changed from the default value, currently shown as 0x2. + * | | |It must always be less than internally used t_rfc_nom/32. + * | | |Note that internally used t_rfc_nom is equal to RFSHTMG.t_rfc_nom_x1_x32 * 32 if RFSHTMG.t_rfc_nom_x1_sel=0. + * | | |Unit: Multiples of 32 DFI clock cycles. + * | | |Programming Mode: Dynamic - Refresh Related + * @var UMCTL2_T::RFSHCTL1 + * Offset: 0x54 Refresh Control Register 1 + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[11:0] |refresh_timer0_start_value_x32|Refresh Timer Start Value for Rank 0 + * | | |only present in multi-rank configurations + * | | |This is useful in staggering the refreshes to multiple ranks to help traffic to proceed. + * | | |FOR PERFORMANCE ONLY. + * | | |Unit: Multiples of 32 DFI clock cycles. + * | | |Programming Mode: Dynamic - Refresh Related + * |[27:16] |refresh_timer1_start_value_x32|Refresh Timer Start Value for Rank 1 + * | | |only present in multi-rank configurations + * | | |This is useful in staggering the refreshes to multiple ranks to help traffic to proceed. + * | | |FOR PERFORMANCE ONLY. + * | | |Unit: Multiples of 32 DFI clock cycles. + * | | |Programming Mode: Dynamic - Refresh Related + * @var UMCTL2_T::RFSHCTL3 + * Offset: 0x60 Refresh Control Register 3 + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[0] |dis_auto_refresh|Disable Auto-Refresh Enable Bit + * | | |When '1', disable auto-refresh generated by the uMCTL2. + * | | |When auto-refresh is disabled, the SoC must generate refreshes using the registers DBGCMD.rankn_refresh. + * | | |When dis_auto_refresh transitions from 0 to 1, any pending refreshes are immediately scheduled by the uMCTL2. + * | | |This register field is changeable on the fly. + * | | |Programming Mode: Dynamic - Refresh Related + * |[1] |refresh_update_level|Refresh Registers Updated Operation + * | | |Toggle this signal (either from 0 to 1 or from 1 to 0) to indicate that the refresh registers have been updated. + * | | |refresh_update_level must not be toggled when the DDRC is in reset (core_ddrc_rstn = 0). + * | | |The refresh registers are automatically updated when exiting reset. + * | | |Programming Mode: Dynamic + * @var UMCTL2_T::RFSHTMG + * Offset: 0x64 Refresh Timing Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[9:0] |t_rfc_min |Minimum Time from Refresh to Refresh or Activate + * | | |tRFC (min) + * | | |When the controller is operating in 1:1 mode, t_rfc_min must be set to RoundUp(tRFCmin/tCK). + * | | |When the controller is operating in 1:2 mode, t_rfc_min must be set to RoundUp(RoundUp(tRFCmin/tCK)/2). + * | | |Unit: DFI clock cycles. + * | | |Programming Mode: Dynamic - Refresh Related + * |[27:16] |t_rfc_nom_x1_x32|Average Time Interval between Refreshes per Rank + * | | |(Specification: 7.8us for DDR2 and DDR3). + * | | |When the controller is operating in 1:1 mode, set this register to RoundDown(tREFI/tCK) + * | | |When the controller is operating in 1:2 mode, set this register to RoundDown(RoundDown(tREFI/tCK)/2) + * | | |In both the previous cases, if RFSHTMG.t_rfc_nom_x1_sel = 0, divide the previous result by 32 and round down. + * | | |Note: + * | | |u00B7 RFSHTMG.t_rfc_nom_x1_x32 must be greater than 0x1 + * | | |u00B7 If RFSHTMG.t_rfc_nom_x1_sel == 1, RFSHTMG.t_rfc_nom_x1_x32 must be greater than RFSHTMG.t_rfc_min + * | | |u00B7 If RFSHTMG.t_rfc_nom_x1_sel == 0, RFSHTMG.t_rfc_nom_x1_x32 * 32 must be greater than RFSHTMG.t_rfc_min + * | | |u00B7 In DDR2/DDR3: RFSHTMG.t_rfc_nom_x1_x32 must be less than or equal to 0xFFE + * | | |Unit: DFI clock cycles or multiples of 32 DFI clock cycles, depending on RFSHTMG.t_rfc_nom_x1_sel. + * | | |Programming Mode: Dynamic - Refresh Related + * @var UMCTL2_T::CRCPARCTL0 + * Offset: 0xC0 CRC Parity Control Register0 + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[0] |dfi_alert_err_int_en|DFI Alert Error Interrupt Enable Bit + * | | |If this bit is set, any parity/CRC error detected on the dfi_alert_n input results in an interrupt being set on CRCPARSTAT.dfi_alert_err_int. + * | | |Programming Mode: Dynamic + * |[1] |dfi_alert_err_int_clr|DFI Alert Error Interrupt Clear Bit + * | | |Interrupt clear bit for DFI alert error + * | | |If this bit is set, the alert error interrupt on CRCPARSTAT.dfi_alert_err_int is cleared + * | | |uMCTL2 automatically clears this bit. + * | | |Testable: readOnly + * | | |Programming Mode: Dynamic + * |[2] |dfi_alert_err_cnt_clr|DFI Alert Error Counter Clear Bit + * | | |Indicates the clear bit for DFI alert error counter. + * | | |Asserting this bit clears the DFI alert error counter, CRCPARSTAT.dfi_alert_err_cnt + * | | |uMCTL2 automatically clears this bit. + * | | |Testable: readOnly + * | | |Programming Mode: Dynamic + * @var UMCTL2_T::CRCPARSTAT + * Offset: 0xCC CRC Parity Status Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[15:0] |dfi_alert_err_cnt|DFI Alert Error Count + * | | |If a parity/CRC error is detected on dfi_alert_n, this counter be incremented + * | | |This is independent of the setting of CRCPARCTL0.dfi_alert_err_int_en + * | | |It saturates at 0xFFFF, and can be cleared by asserting CRCPARCTL0.dfi_alert_err_cnt_clr. + * | | |Programming Mode: Static + * |[16] |dfi_alert_err_int|DFI Alert Error Interrupt + * | | |If a parity/CRC error is detected on dfi_alert_n, and the interrupt is enabled by CRCPARCTL0.dfi_alert_err_int_en, this interrupt bit is set + * | | |It remains set until cleared by CRCPARCTL0.dfi_alert_err_int_clr. + * | | |Programming Mode: Static + * @var UMCTL2_T::INIT0 + * Offset: 0xD0 SDRAM Initialization Register 0 + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[11:0] |pre_cke_x1024|Number of Cycles to Wait after Reset before Driving CKE High to Start SDRAM Initialization + * | | |Indicates the number of cycles to wait after reset before driving CKE high to start the SDRAM initialization sequence. + * | | |DDR2 specifications typically require this to be programmed for a delay of >= 200 us. + * | | |When the controller is operating in 1:2 frequency ratio mode, program this to JEDEC spec value divided by 2, and round it up to the next integer value. + * | | |For DDR3 RDIMMs, this must include the time needed to satisfy tSTAB. + * | | |Unit: Multiples of 1024 DFI clock cycles. + * | | |Programming Mode: Static + * |[25:16] |post_cke_x1024|Number of Cycles to Wait after Driving CKE High to Start the SDRAM Initialization + * | | |Indicates the number of cycles to wait after driving CKE high to start the SDRAM initialization sequence. + * | | |DDR2 typically requires a 400 ns delay, requiring this value to be programmed to 2 at all clock speeds. + * | | |When the controller is operating in 1:2 frequency ratio mode, program this to JEDEC spec value divided by 2, and round it up to the next integer value. + * | | |Unit: Multiples of 1024 DFI clock cycles. + * | | |Programming Mode: Static + * |[31:30] |skip_dram_init|SDRAM Initialization Routine Skipped Enable Bit + * | | |If lower bit is enabled the SDRAM initialization routine is skipped + * | | |The upper bit decides what state the controller starts up in when reset is removed. + * | | |u00B7 00 - SDRAM Initialization routine is run after power-up + * | | |u00B7 01 - SDRAM Initialization routine is skipped after power-up + * | | |The controller starts up in normal Mode + * | | |u00B7 11 - SDRAM Initialization routine is skipped after power-up + * | | |The controller starts up in self-refresh Mode + * | | |u00B7 10 - Reserved + * | | |Programming Mode: Quasi-dynamic Group 2 + * @var UMCTL2_T::INIT1 + * Offset: 0xD4 SDRAM Initialization Register 1 + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[3:0] |pre_ocd_x32|Wait Period before Driving OCD Complete Command to SDRAM + * | | |Indicates the wait period before driving the OCD complete command to SDRAM. + * | | |There is no known specific requirement for this; it may be set to zero. + * | | |Unit: Multiples of 32 DFI clock cycles. + * | | |Programming Mode: Static + * |[24:16] |dram_rstn_x1024|SDRAM Reset During Initialization sequence + * | | |Indicates the number of cycles to assert SDRAM reset signal during initialization sequence. + * | | |This is only present for designs supporting DDR3 devices + * | | |For use with a Synopsys DDR PHY, this must be set to a minimum of 1. + * | | |When the controller is operating in 1:2 frequency ratio mode, program this to JEDEC spec value divided by 2, and round it up to the next integer value. + * | | |Unit: Multiples of 1024 DFI clock cycles. + * | | |Programming Mode: Static + * @var UMCTL2_T::INIT3 + * Offset: 0xDC SDRAM Initialization Register 3 + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[15:0] |emr |Write Value to EMR Register + * | | |DDR2: Indicates the value to write to EMR register + * | | |Bits 9:7 are for OCD and the setting in this register is ignored + * | | |The uMCTL2 sets those bits appropriately. + * | | |DDR3: Value to write to MR1 register Set bit 7 to 0. + * | | |Programming Mode: Quasi-dynamic Group 4 + * |[31:16] |mr |Write Value to MR Register + * | | |DDR2:Indicates the value to write to MR register + * | | |Bit 8 is for DLL and the setting here is ignored + * | | |The uMCTL2 sets this bit appropriately. + * | | |DDR3: Value loaded into MR0 register. + * | | |Programming Mode: Quasi-dynamic Group 1, Group 4 + * @var UMCTL2_T::INIT4 + * Offset: 0xE0 SDRAM Initialization Register 4 + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[15:0] |emr3 |Write Value to EMR3 Register + * | | |DDR2: Indicates the value to write to EMR3 register. + * | | |DDR3: Value to write to MR3 register. + * | | |Programming Mode: Quasi-dynamic Group 2, Group 4 + * |[31:16] |emr2 |Write Value to EMR2 Register + * | | |DDR2: Indicates the value to write to EMR2 register. + * | | |DDR3: Value to write to MR2 register. + * | | |Programming Mode: Quasi-dynamic Group 4 + * @var UMCTL2_T::INIT5 + * Offset: 0xE4 SDRAM Initialization Register 5 + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[23:16] |dev_zqinit_x32|ZQ initial calibration, tZQINIT. + * | | |Present only in designs configured to support DDR3. + * | | |DDR3 typically requires 512 SDRAM clock cycles. + * | | |When the controller is operating in 1:2 frequency ratio mode, program this to JEDEC spec value divided by 2, and round it up to the next integer value. + * | | |Unit: Multiples of 32 DFI clock cycles. + * | | |Programming Mode: Static + * @var UMCTL2_T::DIMMCTL + * Offset: 0xF0 DIMM Control Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[0] |dimm_stagger_cs_en|DIMM Staggering Enable Bit + * | | |Staggering enable for multi-rank accesses (for multi-rank UDIMM, RDIMM and LRDIMM implementations only). + * | | |Note: Even if this bit is set it does not take care of software driven MR commands (through MRCTRL0/MRCTRL1), where software is responsible to send them to separate ranks as appropriate. + * | | |u00B7 1 - DDR2/DDR3 Send all commands to even and odd ranks separately + * | | |u00B7 0 - Do not stagger accesses + * | | |Programming Mode: Static + * |[1] |dimm_addr_mirr_en|DIMM Address Mirroring Enable Bit + * | | |Enables address mirroring (for multi-rank UDIMM implementations). + * | | |Some UDIMMs implement address mirroring for odd ranks, which means that the following address, bank address and bank group bits are swapped: (A3, A4), (A5, A6), (A7, A8), (BA0, BA1). + * | | |Setting this bit ensures that, for mode register accesses during the automatic initialization routine, these bits are swapped within the uMCTL2 to compensate for this UDIMM/RDIMM/LRDIMM swapping. + * | | |Note: This has no effect on the address of any other memory accesses, or of software-driven mode register accesses. + * | | |u00B7 1 - For odd ranks, implement address mirroring for MRS commands during initialization + * | | |u00B7 0 - Do not implement address mirroring + * | | |Programming Mode: Static + * @var UMCTL2_T::RANKCTL + * Offset: 0xF4 Rank Control Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[3:0] |max_rank_rd|Maximum Number of Reads that Can be Scheduled Consecutively to Same Rank + * | | |Only present for multi-rank configurations. + * | | |Background: Reads to the same rank can be performed back-to-back + * | | |Reads to different ranks require additional gap dictated by the register RANKCTL.diff_rank_rd_gap. + * | | |This is to avoid possible data bus contention as well as to give PHY enough time to switch the delay when changing ranks. + * | | |The uMCTL2 arbitrates for bus access on a cycle-by-cycle basis; therefore after a read is scheduled, there are few clock cycles (determined by the value on RANKCTL.diff_rank_rd_gap register) in which only reads from the same rank are eligible to be scheduled. + * | | |This prevents reads from other ranks from having fair access to the data bus. + * | | |This parameter represents the maximum number of reads that can be scheduled consecutively to the same rank. + * | | |After this number is reached, a delay equal to RANKCTL.diff_rank_rd_gap is inserted by the scheduler to allow all ranks a fair opportunity to be scheduled. + * | | |Higher numbers increase bandwidth utilization, lower numbers increase fairness. + * | | |This feature can be DISABLED by setting this register to 0 + * | | |When set to 0, the controller stays on the same rank as long as commands are available for it. + * | | |Minimum programmable value is 0 (feature disabled) and maximum programmable value is 0xF. + * | | |For uPCTL2, this register field must be set to 0 (feature disabled) + * | | |FOR PERFORMANCE ONLY. + * | | |Programming Mode: Static + * |[7:4] |diff_rank_rd_gap|Number of Clocks of Gap in Data Responses when Performing Consecutive Reads to Different Ranks + * | | |Only present for multi-rank configurations. + * | | |Indicates the number of clocks of gap in data responses when performing consecutive reads to different ranks. + * | | |This is used to switch the delays in the PHY to match the rank requirements. + * | | |This value must consider both PHY requirement and ODT requirement. + * | | |u00B7 PHY requirement:tphy_rdcsgap (For more information on value of tphy_rdcsgap, see PHY databook) + * | | |u00B7 ODT requirement: The value programmed in this register takes care of the ODT switch off timing requirement when switching ranks during reads: + * | | |diff_rank_rd_gap must be a minimum of ODTCFG.rd_odt_hold - BL/2 + * | | |when the controller is operating in 1:1 mode, program this to the larger of PHY requirement or ODT requirement. + * | | |When the controller is operating in 1:2 mode, program this to the larger value divided by two and round it up to the next integer. + * | | |After PHY has completed training the value programmed may need to be increased + * | | |For more information, see relevant PHY documentation. + * | | |If a value greater than 0xF is needed, the RANKCTL.diff_rank_rd_gap_msb field must be used as extension + * | | |For DFI 1:2 mode, a maximum value of {diff_rank_rd_gap_msb,diff_rank_rd_gap} < 'h11 is supported + * | | |For DFI 1:1 mode a maximum value of {diff_rank_rd_gap_msb,diff_rank_rd_gap} <= 'h1F is supported. + * | | |Unit: DFI clock cycles. + * | | |Programming Mode: Quasi-dynamic Group 2 + * |[11:8] |diff_rank_wr_gap|Number of Clocks of Gap in Data Responses when Performing Consecutive Writes to Different Ranks + * | | |Only present for multi-rank configurations. + * | | |Indicates the number of clocks of gap in data responses when performing consecutive writes to different ranks. + * | | |This is used to switch the delays in the PHY to match the rank requirements + * | | |This value must consider both PHY requirement and ODT requirement. + * | | |u00B7 PHY requirement - tphy_wrcsgap (For more information on value of tphy_wrcsgap, see PHY databook) + * | | |If CRC feature is enabled, must be increased by 1. + * | | |u00B7 ODT requirement - The value programmed in this register takes care of the ODT switch off timing requirement when switching ranks during writes. + * | | |For other cases, diff_rank_wr_gap must be a minimum of ODTCFG.wr_odt_hold - BL/2 + * | | |When the controller is operating in 1:1 mode, program this to the larger of PHY requirement or ODT requirement. + * | | |If CRC is enabled, the value can be decreased by 2 because the programmed value is internally increased by 1 (it is always 2 in terms of DFI PHY clock cycle as CRC is supported only with 1:2 frequency ratio). + * | | |When the controller is operating in 1:2 mode, program this to the larger value divided by two and round it up to the next integer. + * | | |After PHY has completed training the value programmed may need to be increased + * | | |For more information, see relevant PHY documentation. + * | | |If a value greater than 0xF is needed, the RANKCTL.diff_rank_wr_gap_msb field must be used as extension + * | | |For DFI 1:2 mode, a maximum value of {diff_rank_wr_gap_msb,diff_rank_wr_gap} < 'h11 is supported + * | | |For DFI 1:1 mode a maximum value of {diff_rank_wr_gap_msb,diff_rank_wr_gap} <= 'h1F is supported. + * | | |Unit: DFI clock cycles. + * | | |Programming Mode: Quasi-dynamic Group 2 + * |[15:12] |max_rank_wr|Maximum Number of Writes that Can be Scheduled Consecutively to Same Rank + * | | |Only present for multi-rank configurations. + * | | |Background: Writes to the same rank can be performed back-to-back + * | | |Writes to different ranks require additional gap dictated by the register RANKCTL.diff_rank_wr_gap. + * | | |This is to avoid possible data bus contention as well as to give PHY enough time to switch the delay when changing ranks. + * | | |The uMCTL2 arbitrates for bus access on a cycle-by-cycle basis; therefore after a write is scheduled, there are few clock cycles (determined by the value on RANKCTL.diff_rank_wr_gap register) in which only writes from the same rank are eligible to be scheduled. + * | | |This prevents writes from other ranks from having fair access to the data bus. + * | | |This parameter represents the maximum number of writes that can be scheduled consecutively to the same rank + * | | |After this number is reached, a delay equal to RANKCTL.diff_rank_wr_gap is inserted by the scheduler to allow all ranks a fair opportunity to be scheduled + * | | |Higher numbers increase bandwidth utilization, lower numbers increase fairness. + * | | |This feature can be DISABLED by setting this register to 0 + * | | |When set to 0, the controller stays on the same rank as long as commands are available for it. + * | | |Minimum programmable value is 0 (feature disabled) and maximum programmable value is 0xF. + * | | |For uPCTL2, this register field must be set to 0 (feature disabled) + * | | |FOR PERFORMANCE ONLY. + * | | |Programming Mode: Static + * |[24] |diff_rank_rd_gap_msb|Different Rank Read Gap Extension Bit + * | | |Only present for multi-rank configurations. + * | | |1-bit extension to be used when RANKCTL.diff_rank_rd_gap field needs to be set to a value greater than 0xF. + * | | |Programming Mode: Quasi-dynamic Group 2 + * |[26] |diff_rank_wr_gap_msb|Different Rank Write Gap Extension Bit + * | | |Only present for multi-rank configurations. + * | | |1-bit extension to be used when RANKCTL.diff_rank_wr_gap field needs to be set to a value greater than 0xF. + * | | |Programming Mode: Quasi-dynamic Group 2 + * @var UMCTL2_T::DRAMTMG0 + * Offset: 0x100 SDRAM Timing Register 0 + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[5:0] |t_ras_min |Minimum Time Between Activate and Precharge to the Same Bank (tRAS(min)) + * | | |When the controller is operating in 1:1 frequency ratio mode, t_ras_min must be set to RoundUp(tRASmin/tCK) + * | | |When the controller is operating in 1:2 frequency ratio mode, 1T mode, t_ras_min must be set to RoundDown(RoundUp(tRASmin/tCK)/2) + * | | |When the controller is operating in 1:2 frequency ratio mode, 2T mode, geardown mode or LPDDR4 mode, t_ras min must be set to RoundUp(RoundUp(tRASmin/tCK)/2) + * | | |Unit: DFI clock cycles. + * | | |Programming Mode: Quasi-dynamic Group 2, Group 4 + * |[14:8] |t_ras_max |Maximum Time Between Activate and Precharge to the Same Bank (tRAS(max)) + * | | |This is the maximum time that a page can be kept open Minimum value of this register is 1 + * | | |Zero is invalid. + * | | |When the controller is operating in 1:1 frequency ratio mode, t_ras_max must be set to RoundDown(tRAS(max)/tCK/1024). + * | | |When the controller is operating in 1:2 frequency ratio mode, t_ras_max must be set to RoundDown((RoundDown(tRAS(max)/tCK/1024)-1)/2). + * | | |Unit: Multiples of 1024 DFI clock cycles. + * | | |Programming Mode: Quasi-dynamic Group 2, Group 4 + * |[21:16] |t_faw |Four Active Window for 2 Kbytes Page Size + * | | |tFAW - valid only when 8 or more banks(or banks x bank groups) are present. + * | | |In 8-bank design, at most 4 banks must be activated in a rolling window of tFAW cycles. + * | | |When the controller is operating in 1:2 frequency ratio mode, program this to (tFAW/2) and round up to next integer value. + * | | |In a 4-bank design, set this register to 0x1 independent of the 1:1/1:2 frequency mode. + * | | |Unit: DFI clock cycles. + * | | |Programming Mode: Quasi-dynamic Group 2, Group 4 + * |[30:24] |wr2pre |Minimum Time Between Write and Precharge to Same Bank. + * | | |Specifications: WL + BL/2 + tWR = approximately 8 cycles + 15 ns = 14 clocks @400 MHz and less for lower frequencies. + * | | |where: + * | | |u00B7 WL: Write latency + * | | |u00B7 BL: Burst length + * | | |This must match the value programmed in the BL bit of the mode register to the SDRAM + * | | |BST (burst terminate) is not supported at present + * | | |u00B7 tWR: Write recovery time. This comes directly from the SDRAM specification + * | | |When the controller is operating in 1:2 frequency ratio mode, 1T mode, divide the previous value by 2 + * | | |No rounding up. + * | | |When the controller is operating in 1:2 frequency ratio mode, 2T mode, geardown mode, divide the previous value by 2 and round it up to the next integer value. + * | | |Note that, depending on the PHY, if using LRDIMM, it may be necessary to adjust the value of this parameter to compensate for the extra cycle of latency through the LRDIMM. + * | | |Unit: DFI clock cycles. + * | | |Programming Mode: Quasi-dynamic Group 1, Group 2, Group 4 + * @var UMCTL2_T::DRAMTMG1 + * Offset: 0x104 SDRAM Timing Register 1 + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[6:0] |t_rc |Minimum Time Between Activates to Same Bank (tRC) + * | | |When the controller is operating in 1:2 frequency ratio mode, program this to (tRC/2) and round up to next integer value. + * | | |Unit: DFI clock cycles. + * | | |Programming Mode: Quasi-dynamic Group 2, Group 4 + * |[13:8] |rd2pre |Minimum Time from Read to Precharge of Same Bank (tRTP) + * | | |u00B7 DDR2 - tAL + BL/2 + max(RoundUp(tRTP/tCK), 2) - 2 + * | | |u00B7 DDR3 - tAL + max (RoundUp(tRTP/tCK), 4) + * | | |When the controller is operating in 1:2 mode, 1T mode, divide the previous value by 2. No rounding up. + * | | |When the controller is operating in 1:2 mode, 2T mode, geardown mode, divide the previous value by 2 and round it up to the next integer value. + * | | |Unit: DFI clock cycles. + * | | |Programming Mode: Quasi-dynamic Group 1, Group 2, Group 4 + * |[20:16] |t_xp |Minimum Time after Power-Down Exit to Any Operation (tXP) + * | | |For DDR3, this must be programmed to tXPDLL if slow power down exit is selected in MR0[12]. + * | | |When the controller is operating in 1:2 frequency ratio mode, program this to (tXP/2) and round it up to the next integer value. + * | | |Units: DFI clock cycles. + * | | |Programming Mode: Quasi-dynamic Group 2, Group 4 + * @var UMCTL2_T::DRAMTMG2 + * Offset: 0x108 SDRAM Timing Register 2 + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[5:0] |wr2rd |Minimum Time from Write Command to Read Command + * | | |This must include time for bus turn-around and all PHY and system requirements. + * | | |After the PHY has completed training, the value programmed may need to be increased + * | | |Please see the relevant PHY databook for details of what should be included here. + * | | |The following calculations are minimum values, and do not include the PHY/system requirements mentioned above: + * | | |DDR2/DDR3: CWL + BL/2 + tWTR + * | | |Where: + * | | |u00B7 CWL: CAS write latency + * | | |u00B7 WL: Write latency + * | | |u00B7 BL: Burst length + * | | |This must match the value programmed in the BL bit of the mode register to the SDRAM + * | | |u00B7 tWTR: Internal write to read command delay. This comes directly from the SDRAM specification + * | | |Add one extra cycle for LPDDR2/LPDDR3/LPDDR4 operation. + * | | |When the controller is operating in 1:2 mode, divide the value calculated using the previous equation by 2, and round it up to next integer. + * | | |If your configuration has RANKCTL1.wr2rd_dr, write to read bus turn-around between different physical ranks are controlled by RANKCTL1.wr2rd_dr. + * | | |Unit: DFI clock cycles. + * | | |Programming Mode: Quasi-dynamic Group 1, Group 2, Group 4 + * |[13:8] |rd2wr |Minimum Time from Read Command to Write Command + * | | |This must include time for bus turnaround (both within ranks and between ranks) and all PHY and system requirements. + * | | |After the PHY has completed training, the value programmed may need to be increased + * | | |Please see the relevant PHY databook for details of what should be included here. + * | | |The following calculations are minimum values, and do not include the PHY/system requirements mentioned above: + * | | |DDR2/3 : RL + BL/2 + 2 - WL + * | | |Where: + * | | |u00B7 WL: Write latency + * | | |u00B7 BL: Burst length + * | | |This must match the value programmed in the BL bit of the mode register to the SDRAM + * | | |u00B7 RL: Read latency = CAS latency + * | | |When the controller is operating in 1:2 frequency ratio mode, divide the value calculated using the previous equation by 2, and round it up to next integer. + * | | |Unit: DFI clock cycles. + * | | |Programming Mode: Quasi-dynamic Group 1, Group 2, Group 4 + * @var UMCTL2_T::DRAMTMG3 + * Offset: 0x10C SDRAM Timing Register 3 + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[9:0] |t_mod |Number of Cycles Between Load Mode Command and Following Non-Load Mode Command (tMOD) + * | | |Used only in DDR3. + * | | |Indicates the number of cycles between load mode command and following non-load mode command. + * | | |If CAL mode is enabled (DFITMG1.dfi_t_cmd_lat > 0), tCAL (=DFITMG1.dfi_cmd_lat) must be added to the previous calculations. + * | | |Set to tMOD if controller is operating in 1:1 frequency ratio mode, or tMOD/2 (rounded up to next integer) if controller is operating in 1:2 frequency ratio mode. + * | | |Unit: DFI clock cycles. + * | | |Programming Mode: Quasi-dynamic Group 2, Group 4 + * |[17:12] |t_mrd |Number of Cycles to Wait after a Mode Register Write or Read (tMRD) + * | | |Depending on the connected SDRAM, tMRD represents: + * | | |u00B7 DDR2: Time from MRS to any command + * | | |u00B7 DDR3: Time from MRS to MRS command + * | | |When the controller is operating in 1:2 frequency ratio mode, program this to (tMRD/2) and round it up to the next integer value. + * | | |If CAL mode is enabled (DFITMG1.dfi_t_cmd_lat > 0), tCAL (=DFITMG1.dfi_cmd_lat) must be added to the previous calculations. + * | | |Unit: DFI clock cycles. + * | | |Programming Mode: Quasi-dynamic Group 2, Group 4 + * @var UMCTL2_T::DRAMTMG4 + * Offset: 0x110 SDRAM Timing Register 4 + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[4:0] |t_rp |Minimum Time from Single-Bank Precharge to Activate of Same Bank (tRP) + * | | |When the controller is operating in 1:1 frequency ratio mode, t_rp must be set to RoundUp(tRP/tCK). + * | | |When the controller is operating in 1:2 frequency ratio mode, t_rp must be set to RoundDown(RoundUp(tRP/tCK)/2) + 1. + * | | |Unit: DFI clock cycles. + * | | |Programming Mode: Quasi-dynamic Group 2, Group 4 + * |[11:8] |t_rrd |Minimum Time Between Activates from Bank "a" to Bank "b" for Others (tRRD) + * | | |When the controller is operating in 1:2 frequency ratio mode, program this to (tRRD/2) and round it up to the next integer value. + * | | |Unit: DFI clock cycles. + * | | |Programming Mode: Quasi-dynamic Group 2, Group 4 + * |[19:16] |t_ccd |Minimum Time Between Two Reads or Two Writes for Others (tCCD) + * | | |When the controller is operating in 1:2 frequency ratio mode, program this to (tCCD_L/2 or tCCD/2) and round it up to the next integer value. + * | | |Unit: DFI clock cycles. + * | | |Programming Mode: Quasi-dynamic Group 2, Group 4 + * |[28:24] |t_rcd |Minimum Time from Activate to Read or Write Command to Same Bank (tRCD - tAL) + * | | |When the controller is operating in 1:2 frequency ratio mode, program this to ((tRCD - tAL)/2) and round it up to the next integer value. + * | | |Minimum value allowed for this register is 1, which implies minimum (tRCD - tAL) value to be 2 when the controller is operating in 1:2 frequency ratio mode. + * | | |Unit: DFI clock cycles. + * | | |Programming Mode: Quasi-dynamic Group 1, Group 2, Group 4 + * @var UMCTL2_T::DRAMTMG5 + * Offset: 0x114 SDRAM Timing Register 5 + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[4:0] |t_cke |Minimum Number of Cycles of CKE HIGH/LOW During Power-Down and Self-Refresh. + * | | |u00B7 DDR2/DDR3: Set this to tCKE value + * | | |When the controller is operating in 1:2 frequency ratio mode, program this to (value described above)/2 and round it up to the next integer value. + * | | |Unit: DFI clock cycles. + * | | |Programming Mode: Quasi-dynamic Group 2, Group 4 + * |[13:8] |t_ckesr |Minimum CKE Low Width for Self-Refresh or Self-Refresh Power Down Entry to Exit Timing in Memory Clock Cycles. + * | | |Recommended settings: + * | | |u00B7 DDR2 : tCKE + * | | |u00B7 DDR3 : tCKE + 1 + * | | |When the controller is operating in 1:2 frequency ratio mode, program this to recommended value divided by two and round it up to next integer. + * | | |Unit: DFI clock cycles. + * | | |Programming Mode: Quasi-dynamic Group 2, Group 4 + * |[22:16] |t_cksre |Time After Self-Refresh Down Entry that CK is Maintained as a Valid Clock. + * | | |Specifies the clock disable delay after SRE. + * | | |Recommended settings: + * | | |u00B7 DDR2 : 1 + * | | |u00B7 DDR3 : Max (10 ns, 5 tCK) + * | | |When the controller is operating in 1:2 frequency ratio mode, program this to recommended value divided by two and round it up to next integer. + * | | |Unit: DFI clock cycles. + * | | |Programming Mode: Quasi-dynamic Group 2, Group 4 + * |[27:24] |t_cksrx |Time Before Self-Refresh Exit that CK is Maintained as a Valid Clock Before Issuing SRX. + * | | |Specifies the clock stable time before SRX. + * | | |Recommended settings: + * | | |u00B7 DDR2 : 1 + * | | |u00B7 DDR3 : tCKSRX + * | | |When the controller is operating in 1:2 frequency ratio mode, program this to recommended value divided by two and round it up to next integer. + * | | |Unit: DFI clock cycles. + * | | |Programming Mode: Quasi-dynamic Group 2, Group 4 + * @var UMCTL2_T::DRAMTMG8 + * Offset: 0x120 SDRAM Timing Register 8 + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[6:0] |t_xs_x32 |Exit Self-Refresh to Commands Not Requiring a Locked DLL (tXS) + * | | |When the controller is operating in 1:2 frequency ratio mode, program this to the previous value divided by 2 and round up to next integer value. + * | | |Note: Used only for DDR2 and DDR3 SDRAMs. + * | | |Unit: Multiples of 32 DFI clock cycles. + * | | |Programming Mode: Quasi-dynamic Group 2, Group 4 + * |[14:8] |t_xs_dll_x32|Exit Self-Refresh to Commands Requiring a Locked DLL (tXSDLL) + * | | |When the controller is operating in 1:2 frequency ratio mode, program this to the previous value divided by 2 and round up to next integer value. + * | | |Note: Used only for DDR2 and DDR3 SDRAMs. + * | | |Unit: Multiples of 32 DFI clock cycles. + * | | |Programming Mode: Quasi-dynamic Group 2, Group 4 + * @var UMCTL2_T::DRAMTMG15 + * Offset: 0x13C SDRAM Timing Register 15 + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[7:0] |t_stab_x32|Stabilization time (tSTAB) + * | | |It is required in the following two cases for DDR3 RDIMM: + * | | |u00B7 When exiting power saving mode, if the clock is stopped, after re-enabling it the clock must be stable for a time specified by tSTAB + * | | |u00B7 After issuing control words that refers to clock timing (Specification: 6us for DDR3) + * | | |When the controller is operating in 1:2 frequency ratio mode, program this to recommended value divided by two and round it up to next integer. + * | | |Unit: Multiples of 32 DFI clock cycles. + * | | |Programming Mode: Quasi-dynamic Group 2, Group 4 + * |[31] |en_dfi_lp_t_stab|Enable Bit for Using tSTAB When Exiting DFI LP + * | | |u00B7 1 - Enable using tSTAB when exiting DFI LP + * | | |This must be set when the PHY is stopping the clock during DFI LP to save maximum power. + * | | |u00B7 0 - Disable using tSTAB when exiting DFI LP. + * | | |Programming Mode: Quasi-dynamic Group 2, Group 4 + * @var UMCTL2_T::ZQCTL0 + * Offset: 0x180 ZQ Control Register 0 + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[9:0] |t_zq_short_nop|Number of DFI Clock Cycles of NOP Required After a ZQCS (ZQ Calibration Short)/MPC(ZQ Latch) Command is Issued to SDRAM + * | | |tZQCS for DDR3 + * | | |When the controller is operating in 1:2 frequency ratio mode, program this to tZQCS/2 and round it up to the next integer value. + * | | |This is only present for designs supporting DDR3 devices. + * | | |Unit: DFI clock cycles. + * | | |Programming Mode: Static + * |[26:16] |t_zq_long_nop|Number of DFI Clock Cycles of NOP Required After a ZQCL (ZQ Calibration Long)/MPC (ZQ Start) Command is Issued to SDRAM + * | | |tZQoper for DDR3 + * | | |When the controller is operating in 1:2 frequency ratio mode: + * | | |DDR3: program this to tZQoper/2 and round it up to the next integer value. + * | | |This is only present for designs supporting DDR3 devices. + * | | |Unit: DFI clock cycles. + * | | |Programming Mode: Static + * |[29] |zq_resistor_shared|ZQ Resistor Shared Between Ranks + * | | |u00B7 1 - Denotes that ZQ resistor is shared between ranks + * | | |Means ZQinit/ZQCL/ZQCS/MPC(ZQ calibration) commands are sent to one rank at a time with tZQinit/tZQCL/tZQCS/tZQCAL/tZQLAT timing met between commands so that commands to different ranks do not overlap + * | | |u00B7 0 - ZQ resistor is not shared + * | | |This is only present for designs supporting DDR3 devices. + * | | |Programming Mode: Static + * |[30] |dis_srx_zqcl|Disable Issuing of ZQCL/MPC(ZQ Calibration) Command at Self-Refresh/SR-Power Down Exit + * | | |u00B7 1 - Disable issuing of ZQCL/MPC(ZQ calibration) command at self-refresh/SR-Power down exit + * | | |Only applicable when run in DDR3 mode + * | | |u00B7 0 - Enable issuing of ZQCL/MPC(ZQ calibration) command at self-refresh/SR-Power down exit + * | | |Only applicable when run in DDR3 mode + * | | |This is only present for designs supporting DDR3 devices. + * | | |Programming Mode: Quasi-dynamic Group 2, Group 4 + * |[31] |dis_auto_zq|Disable Auto Generation of ZQCS/MPC(ZQ Calibration) Command + * | | |u00B7 1 - Disable uMCTL2 generation of ZQCS/MPC(ZQ calibration) command + * | | |Register DBGCMD.zq_calib_short can be used instead to issue ZQ calibration request from APB module + * | | |u00B7 0 - Internally generate ZQCS/MPC(ZQ calibration) commands based on ZQCTL1.t_zq_short_interval_x1024 + * | | |This is only present for designs supporting DDR3 devices. + * | | |Programming Mode: Dynamic + * @var UMCTL2_T::ZQCTL1 + * Offset: 0x184 ZQ Control Register 1 + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[19:0] |t_zq_short_interval_x1024|Average Interval to Wait Between Automatically Issuing ZQCS + * | | |Average Interval to Wait Between Automatically Issuing ZQCS (ZQ Calibration Short)/MPC(ZQ Calibration) Commands to DDR3 Devices. + * | | |Meaningless, if ZQCTL0.dis_auto_zq=1. + * | | |This is only present for designs supporting DDR3 devices. + * | | |Unit: Multiples of 1024 DFI clock cycles. + * | | |Programming Mode: Static + * @var UMCTL2_T::DFITMG0 + * Offset: 0x190 DFI Timing Register 0 + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[5:0] |dfi_tphy_wrlat|Write latency + * | | |Number of clocks from the write command to write data enable (dfi_wrdata_en) + * | | |This corresponds to the DFI timing parameter tphy_wrlat. + * | | |Refer to PHY specification for correct value. + * | | |Unit: DFI clock cycles or DFI PHY clock cycles, depending on DFITMG0.dfi_wrdata_use_dfi_phy_clk. + * | | |Programming Mode: Quasi-dynamic Group 2, Group 4 + * |[13:8] |dfi_tphy_wrdata|Number of Clock Cycles Between When dfi_wrdata_en is Asserted to When the Associated Write Data is Driven on the dfi_wrdata Signal + * | | |This corresponds to the DFI timing parameter tphy_wrdata + * | | |For more information on correct value, see PHY specification + * | | |Note, maximum supported value is 8. + * | | |Unit: DFI clock cycles or DFI PHY clock cycles, depending on DFITMG0.dfi_wrdata_use_dfi_phy_clk. + * | | |Programming Mode: Quasi-dynamic Group 4 + * |[15] |dfi_wrdata_use_dfi_phy_clk|dfi_wrdata_en/dfi_wrdata/dfi_wrdata_mask is Generated Using HDR (DFI Clock) or SDR (DFI PHY Clock) Values + * | | |Selects whether value in DFITMG0.dfi_tphy_wrlat is in terms of HDR (DFI clock) or SDR (DFI PHY clock) cycles. + * | | |Selects whether value in DFITMG0.dfi_tphy_wrdata is in terms of HDR (DFI clock) or SDR (DFI PHY clock) cycles. + * | | |u00B7 0 in terms of HDR (DFI clock) cycles + * | | |Refer to PHY specification for correct value + * | | |If using a Synopsys DWC DDR3/2 PHY, this field must be set to 0. + * | | |Programming Mode: Static + * |[22:16] |dfi_t_rddata_en|Time from the Assertion of a Read Command on the DFI Interface to the Assertion of the dfi_rddata_en Signal + * | | |Refer to PHY specification for correct value. + * | | |This corresponds to the DFI parameter trddata_en. + * | | |Unit: DFI clock cycles or DFI PHY clock cycles, depending on DFITMG0.dfi_rddata_use_dfi_phy_clk. + * | | |Programming Mode: Quasi-dynamic Group 1, Group 4 + * |[23] |dfi_rddata_use_dfi_phy_clk|dfi_rddata_en/dfi_rddata/dfi_rddata_valid is Generated Using HDR (DFI Clock) or SDR (DFI PHY Clock) Values + * | | |Selects whether value in DFITMG0.dfi_t_rddata_en is in terms of HDR (DFI clock) or SDR (DFI PHY clock) cycles: + * | | |u00B7 0 in terms of HDR (DFI clock) cycles + * | | |Refer to PHY specification for correct value. + * | | |If using a Synopsys DWC DDR3/2 PHY, this field must be set to 0. + * | | |Programming Mode: Static + * |[28:24] |dfi_t_ctrl_delay|Number of DFI Clock Cycles After an Assertion or De-assertion of the DFI Control Signals that the Control Signals at the PHY-DRAM Interface Reflect the Assertion or De-assertion + * | | |If the DFI clock and the memory clock are not phase-aligned, this timing parameter must be rounded up to the next integer value. + * | | |Unit: DFI clock cycles. + * | | |Programming Mode: Quasi-dynamic Group 4 + * @var UMCTL2_T::DFITMG1 + * Offset: 0x194 DFI Timing Register 1 + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[4:0] |dfi_t_dram_clk_enable|Number of DFI Clock Cycles from the De-assertion of the dfi_dram_clk_disable Signal on the DFI Until the First Valid Rising Edge of the Clock to the DRAM Memory Devices, at the PHY-DRAM Boundary + * | | |If the DFI clock and the memory clock are not phase aligned, this timing parameter must be rounded up to the next integer value. + * | | |Unit: DFI clock cycles. + * | | |Programming Mode: Quasi-dynamic Group 4 + * |[12:8] |dfi_t_dram_clk_disable|Number of DFI Clock Cycles from the Assertion of the dfi_dram_clk_disable Signal on the DFI Until the Clock to the DRAM Memory Devices, at the PHY-DRAM Boundary, Maintains a Low Value + * | | |If the DFI clock and the memory clock are not phase aligned, this timing parameter must be rounded up to the next integer value. + * | | |Unit: DFI clock cycles. + * | | |Programming Mode: Quasi-dynamic Group 4 + * |[20:16] |dfi_t_wrdata_delay|Number of DFI Clock Cycles Between When the dfi_wrdata_en Signal is Asserted and When the Corresponding Write Data Transfer is Completed on the DRAM Bus + * | | |This corresponds to the DFI timing parameter twrdata_delay. + * | | |For more information on correct value, see PHY specification. + * | | |For DFI 2.1 PHY, set to tphy_wrdata + (delay of DFI write data to the DRAM). + * | | |Value to be programmed is in terms of DFI clocks, not PHY clocks. + * | | |In FREQ_RATIO=2, divide PHY's value by 2 and round up to next integer. + * | | |If using DFITMG0.dfi_wrdata_use_dfi_phy_clk=1, add 1 to the value. + * | | |Unit: DFI clock cycles. + * | | |Programming Mode: Quasi-dynamic Group 4 + * |[25:24] |dfi_t_parin_lat|Number of DFI PHY Clock Cycles Between When the dfi_cs signal is Asserted and When the Associated dfi_parity_in Signal is Driven + * | | |Unit: DFI PHY clock cycles. + * | | |Programming Mode: Quasi-dynamic Group 4 + * @var UMCTL2_T::DFILPCFG0 + * Offset: 0x198 DFI Low Power Configuration Register 0 + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[0] |dfi_lp_en_pd|Enable Bit for DFI Low Power Interface Handshaking During Power Down Entry/Exit + * | | |u00B7 0 - Disabled + * | | |u00B7 1 - Enabled + * | | |Programming Mode: Static + * |[7:4] |dfi_lp_wakeup_pd|Value in DFI Clock Cycles to Drive on dfi_lp_wakeup Signal When Power-Down Mode is Entered + * | | |Determines the DFI's tlp_wakeup time: + * | | |u00B7 0x0 - 16 cycles + * | | |u00B7 0x1 - 32 cycles + * | | |u00B7 0x2 - 64 cycles + * | | |u00B7 0x3 - 128 cycles + * | | |u00B7 0x4 - 256 cycles + * | | |u00B7 0x5 - 512 cycles + * | | |u00B7 0x6 - 1024 cycles + * | | |u00B7 0x7 - 2048 cycles + * | | |u00B7 0x8 - 4096 cycles + * | | |u00B7 0x9 - 8192 cycles + * | | |u00B7 0xA - 16384 cycles + * | | |u00B7 0xB - 32768 cycles + * | | |u00B7 0xC - 65536 cycles + * | | |u00B7 0xD - 131072 cycles + * | | |u00B7 0xE - 262144 cycles + * | | |u00B7 0xF - Unlimited + * | | |Unit: DFI clock cycles. + * | | |Programming Mode: Static + * |[8] |dfi_lp_en_sr|Enable Bit for DFI Low Power Interface Handshaking During Self-Refresh Entry/Exit + * | | |u00B7 0 - Disabled + * | | |u00B7 1 - Enabled + * | | |Programming Mode: Static + * |[15:12] |dfi_lp_wakeup_sr|Value in DFI Clock Cycles to Drive on dfi_lp_wakeup Signal When Self-Refresh Mode is Entered + * | | |Determines the DFI's tlp_wakeup time: + * | | |u00B7 0x0 - 16 cycles + * | | |u00B7 0x1 - 32 cycles + * | | |u00B7 0x2 - 64 cycles + * | | |u00B7 0x3 - 128 cycles + * | | |u00B7 0x4 - 256 cycles + * | | |u00B7 0x5 - 512 cycles + * | | |u00B7 0x6 - 1024 cycles + * | | |u00B7 0x7 - 2048 cycles + * | | |u00B7 0x8 - 4096 cycles + * | | |u00B7 0x9 - 8192 cycles + * | | |u00B7 0xA - 16384 cycles + * | | |u00B7 0xB - 32768 cycles + * | | |u00B7 0xC - 65536 cycles + * | | |u00B7 0xD - 131072 cycles + * | | |u00B7 0xE - 262144 cycles + * | | |u00B7 0xF - Unlimited + * | | |Unit: DFI clock cycles. + * | | |Programming Mode: Static + * |[28:24] |dfi_tlp_resp|Setting in DFI Clock Cycles for DFI's tlp_resp Time + * | | |Same value is used for both Power Down, self-refresh, Deep Power Down and Maximum Power Saving modes. + * | | |For more information on recommended values, see PHY databook + * | | |Unit: DFI clock cycles. + * | | |Programming Mode: Static + * @var UMCTL2_T::DFIUPD0 + * Offset: 0x1A0 DFI Update Register 0 + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[9:0] |dfi_t_ctrlup_min|Minimum Number of DFI Clock Cycles that the dfi_ctrlupd_req Signal must be Asserted The uMCTL2 expects the PHY to respond within this time. If the PHY does not respond, the uMCTL2 de-asserts dfi_ctrlupd_req after dfi_t_ctrlup_min + 2 cycles. Lowest value to assign to this variable is 0x1. + * | | |Unit: DFI clock cycles. + * | | |Programming Mode: Static + * |[25:16] |dfi_t_ctrlup_max|Maximum Number of DFI Clock Cycles that the dfi_ctrlupd_req Signal Can Assert + * | | |Lowest value to assign to this variable is 0x40. + * | | |Unit: DFI clock cycles. + * | | |Programming Mode: Static + * |[29] |ctrlupd_pre_srx|dfi_ctrlupd_req Selection at SRX + * | | |u00B7 0 - Send ctrlupd after SRX + * | | |u00B7 1 - Send ctrlupd before SRX If DFIUPD0.dis_auto_ctrlupd_srx=1, this register has no impact, because no dfi_ctrlupd_req is issued when SRX. + * | | |Programming Mode: Static + * |[30] |dis_auto_ctrlupd_srx|Disable Bit for Automatic dfi_ctrlupd_req Generation by uMCTL2 at Self-Refresh Exit + * | | |When '1', disable the automatic dfi_ctrlupd_req generation by the uMCTL2 at self-refresh exit. + * | | |When '0', uMCTL2 issues a dfi_ctrlupd_req before or after exiting self-refresh, depending on DFIUPD0.ctrlupd_pre_srx. + * | | |Programming Mode: Static + * |[31] |dis_auto_ctrlupd|Disable Bit for Automatic dfi_ctrlupd_req Generation by uMCTL2 + * | | |When '1', disable the automatic dfi_ctrlupd_req generation by the uMCTL2. + * | | |The controller must issue the dfi_ctrlupd_req signal using register DBGCMD.ctrlupd. + * | | |When '0', uMCTL2 issues dfi_ctrlupd_req periodically. + * | | |Programming Mode: Quasi-dynamic Group 3 + * @var UMCTL2_T::DFIUPD1 + * Offset: 0x1A4 DFI Update Register 1 + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[7:0] |dfi_t_ctrlupd_interval_max_x1024|Maximum Amount of Time Between uMCTL2 Initiated DFI Update Requests + * | | |This timer resets with each update request; when the timer expires dfi_ctrlupd_req is sent and traffic is blocked until the dfi_ctrlupd_ackx is received. + * | | |PHY can use this idle time to recalibrate the delay lines to the DLLs + * | | |The DFI controller update is also used to reset PHY FIFO pointers in case of data capture errors. + * | | |Updates are required to maintain calibration over PVT, but frequent updates may impact performance + * | | |Minimum allowed value for this field is 1. + * | | |Note: Value programmed for DFIUPD1.dfi_t_ctrlupd_interval_max_x1024 must be greater than DFIUPD1.dfi_t_ctrlupd_interval_min_x1024. + * | | |Unit: Multiples of 1024 DFI clock cycles. + * | | |Programming Mode: Static + * |[23:16] |dfi_t_ctrlupd_interval_min_x1024|Minimum Amount of Time Between uMCTL2 Initiated DFI Update Requests (which is Executed whenever the uMCTL2 is Idle) + * | | |Set this number higher to reduce the frequency of update requests, which can have a small impact on the latency of the first read request when the uMCTL2 is idle. + * | | |The minimum allowed value for this field is 1. + * | | |Unit: Multiples of 1024 DFI clock cycles. + * | | |Programming Mode: Static + * @var UMCTL2_T::DFIUPD2 + * Offset: 0x1A8 DFI Update Register 2 + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[31] |dfi_phyupd_en|Enable Bit for Acknowledging PHY-Initiated Updates + * | | |u00B7 0 - Disabled + * | | |u00B7 1 - Enabled + * | | |Programming Mode: Static + * @var UMCTL2_T::DFIMISC + * Offset: 0x1B0 DFI Miscellaneous Control Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[0] |dfi_init_complete_en|PHY Initialization Complete Enable Bit + * | | |When asserted the dfi_init_complete signal can be used to trigger SDRAM initialisation + * | | |Programming Mode: Quasi-dynamic Group 3 + * |[4] |ctl_idle_en|Enable Bit for ctl_idle Signal + * | | |It is non-DFI related pin specific to certain Synopsys PHYs. + * | | |For more information on ctl_idle functionality, see signal description of ctl_idle signal. + * | | |Programming Mode: Static + * |[5] |dfi_init_start|PHY Initialization Start Request Signal + * | | |When asserted it triggers the PHY init start request. + * | | |Programming Mode: Quasi-dynamic Group 3 + * |[12:8] |dfi_frequency|Operating Frequency of System + * | | |The number of supported frequencies and the mapping of signal values to clock frequencies are defined by the PHY. + * | | |Programming Mode: Quasi-dynamic Group 1 + * @var UMCTL2_T::DFISTAT + * Offset: 0x1BC DFI Status Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[0] |dfi_init_complete|Status flag when the DFI initialization has been completed + * | | |The DFI INIT triggered by dfi_init_start signal and then the dfi_init_complete flag is polled to know when the initialization is done. + * | | |Programming Mode: Dynamic + * |[1] |dfi_lp_ack|Value of the dfi_lp_ack to the controller + * | | |Programming Mode: Dynamic + * @var UMCTL2_T::DFIPHYMSTR + * Offset: 0x1C4 DFI PHY Master + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[0] |dfi_phymstr_en|PHY Master Interface Enable Bit + * | | |u00B7 0 - Disabled + * | | |u00B7 1 - Enabled + * | | |Programming Mode: Static + * @var UMCTL2_T::ADDRMAP0 + * Offset: 0x200 Address Map Register 0 + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[4:0] |addrmap_cs_bit0|HIF Address Bits for Rank Address Bit 0 + * | | |Valid Range: 0 to 29, and 31 + * | | |Internal Base: 6 + * | | |The selected HIF address bit is determined by adding the internal base to the value of this field. + * | | |If unused, set to 31 and then rank address bit 0 is set to 0. + * | | |Programming Mode: Static + * @var UMCTL2_T::ADDRMAP1 + * Offset: 0x204 Address Map Register 1 + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[5:0] |addrmap_bank_b0|HIF Address Bits for Bank Address Bit 0 + * | | |Valid Range: 0 to 32, and 63 + * | | |Internal Base: 2 + * | | |The selected HIF address bit for each of the bank address bits is determined by adding the internal base to the value of this field. + * | | |If unused, set to 63 and then bank address bit 0 is set to 0. + * | | |Programming Mode: Static + * |[13:8] |addrmap_bank_b1|HIF Address Bits for Bank Address Bit 1 + * | | |Valid Range: 0 to 32, and 63 + * | | |Internal Base: 3 + * | | |The selected HIF address bit for each of the bank address bits is determined by adding the internal base to the value of this field. + * | | |If unused, set to 63 and then bank address bit 1 is set to 0. + * | | |Programming Mode: Static + * |[21:16] |addrmap_bank_b2|HIF Address Bits for Bank Address Bit 2 + * | | |Valid Range: 0 to 31, and 63 + * | | |Internal Base: 4 + * | | |The selected HIF address bit is determined by adding the internal base to the value of this field. + * | | |If unused, set to 63 and then bank address bit 2 is set to 0. + * | | |Programming Mode: Static + * @var UMCTL2_T::ADDRMAP2 + * Offset: 0x208 Address Map Register 2 + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[3:0] |addrmap_col_b2|HIF Address Bit for Column Address Bit for Three Bus Width Modes + * | | |u00B7 Full bus width mode - Selects the HIF address bit used as column address bit 2 + * | | |u00B7 Half bus width mode - Selects the HIF address bit used as column address bit 3 + * | | |Valid Range: 0 to 7 + * | | |Internal Base: 2 + * | | |The selected HIF address bit is determined by adding the internal base to the value of this field. + * | | |In our chip, we configure hardware parameter "MEMC_BURST_LENGTH" to equal to 8 and Full Bus Width (MSTR.data_bus_width==00), it is recommended to program this to 0 so that HIF[2] maps to column address bit 2. + * | | |Programming Mode: Static + * |[12:8] |addrmap_col_b3|HIF Address Bit for Column Address Bit for Three Bus Width Modes + * | | |u00B7 Full bus width mode - Selects the HIF address bit used as column address bit 3 + * | | |u00B7 Half bus width mode - Selects the HIF address bit used as column address bit 4 + * | | |Valid Range: 0 to 7. + * | | |Internal Base: 3 + * | | |The selected HIF address bit is determined by adding the internal base to the value of this field. + * | | |Programming Mode: Static + * |[19:16] |addrmap_col_b4|HIF Address Bit for Column Address Bit for Three Bus Width Modes + * | | |u00B7 Full bus width mode - Selects the HIF address bit used as column address bit 4 + * | | |u00B7 Half bus width mode - Selects the HIF address bit used as column address bit 5 + * | | |Valid Range: 0 to 7, and 15 + * | | |Internal Base: 4 + * | | |The selected HIF address bit is determined by adding the internal base to the value of this field. + * | | |If unused, set to 15 and then this column address bit is set to 0. + * | | |Programming Mode: Static + * |[27:24] |addrmap_col_b5|HIF Address Bit for Column Address Bit for Three Bus Width Modes + * | | |u00B7 Full bus width mode - Selects the HIF address bit used as column address bit 5 + * | | |u00B7 Half bus width mode - Selects the HIF address bit used as column address bit 6 + * | | |Valid Range: 0 to 7, and 15 + * | | |Internal Base: 5 + * | | |The selected HIF address bit is determined by adding the internal base to the value of this field. + * | | |If unused, set to 15 and then this column address bit is set to 0. + * | | |Programming Mode: Static + * @var UMCTL2_T::ADDRMAP3 + * Offset: 0x20C Address Map Register 3 + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[4:0] |addrmap_col_b6|HIF Address Bit for Column Address Bit for Three Bus Width Modes + * | | |u00B7 Full bus width mode - Selects the HIF address bit used as column address bit 6. + * | | |u00B7 Half bus width mode - Selects the HIF address bit used as column address bit 7. + * | | |Valid Range: 0 to 7, and 31. + * | | |Internal Base: 6 + * | | |The selected HIF address bit is determined by adding the internal base to the value of this field. + * | | |If unused, set to 31 and then this column address bit is set to 0. + * | | |Programming Mode: Static + * |[12:8] |addrmap_col_b7|HIF Address Bit for Column Address Bit for Three Bus Width Modes + * | | |u00B7 Full bus width mode - Selects the HIF address bit used as column address bit 7 + * | | |u00B7 Half bus width mode - Selects the HIF address bit used as column address bit 8 + * | | |Valid Range: 0 to 7, and 31. + * | | |Internal Base: 7 + * | | |The selected HIF address bit is determined by adding the internal base to the value of this field. + * | | |If unused, set to 31 and then this column address bit is set to 0. + * | | |Programming Mode: Static + * |[20:16] |addrmap_col_b8|HIF Address Bit for Column Address Bit for Three Bus Width Modes + * | | |u00B7 Full bus width mode - Selects the HIF address bit used as column address bit 8 + * | | |u00B7 Half bus width mode - Selects the HIF address bit used as column address bit 9 + * | | |Valid Range: 0 to 7, and 31. + * | | |Internal Base: 8 + * | | |The selected HIF address bit is determined by adding the internal base to the value of this field. + * | | |Note: Per JEDEC DDR2/3 specification, column address bit 10 is reserved for indicating auto-precharge, and hence no source address bit can be mapped to column address bit 10. + * | | |If unused, set to 31 and then this column address bit is set to 0. + * | | |Programming Mode: Static + * |[28:24] |addrmap_col_b9|HIF Address Bit for Column Address Bit for Three Bus Width Modes + * | | |u00B7 Full bus width mode - Selects the HIF address bit used as column address bit 9 + * | | |u00B7 Half bus width mode - Selects the HIF address bit used as column address bit 11 + * | | |Valid Range: 0 to 7. + * | | |Internal Base: 9 + * | | |The selected HIF address bit is determined by adding the internal base to the value of this field. + * | | |Note: Per JEDEC DDR2/3 specification, column address bit 10 is reserved for indicating auto-precharge, and hence no source address bit can be mapped to column address bit 10. + * | | |If unused, set to 31 and then this column address bit is set to 0. + * | | |Programming Mode: Static + * @var UMCTL2_T::ADDRMAP4 + * Offset: 0x210 Address Map Register 4 + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[4:0] |addrmap_col_b10|HIF Address Bit for Column Address Bit for Three Bus Width Modes + * | | |u00B7 Full bus width mode: Selects the HIF address bit used as column address bit 11 + * | | |u00B7 Half bus width mode: Selects the HIF address bit used as column address bit 13 + * | | |Valid Range: 0 to 7, and 31. + * | | |Internal Base: 10 + * | | |The selected HIF address bit is determined by adding the internal base to the value of this field. + * | | |Note: Per JEDEC DDR2/3 specification, column address bit 10 is reserved for indicating auto-precharge, and hence no source address bit can be mapped to column address bit 10. + * | | |If unused, set to 31 and then this column address bit is set to 0. + * | | |Programming Mode: Static + * |[12:8] |addrmap_col_b11|HIF Address Bit for Column Address Bit for Three Bus Width Modes + * | | |u00B7 Full bus width mode - Selects the HIF address bit used as column address bit 13 + * | | |u00B7 Half bus width mode - UNUSED + * | | |See later in this description for value you need to set to make it unused + * | | |Valid Range: 0 to 7, and 31. + * | | |Internal Base: 11 + * | | |The selected HIF address bit is determined by adding the internal base to the value of this field. + * | | |Note: Per JEDEC DDR2/3 specification, column address bit 10 is reserved for indicating auto-precharge, and hence no source address bit can be mapped to column address bit 10. + * | | |If unused, set to 31 and then this column address bit is set to 0. + * | | |Programming Mode: Static + * @var UMCTL2_T::ADDRMAP5 + * Offset: 0x214 Address Map Register 5 + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[3:0] |addrmap_row_b0|HIF Address Bits for Row Address Bit 0 + * | | |Valid Range: 0 to 11 + * | | |Internal Base: 6 + * | | |The selected HIF address bit for each of the row address bits is determined by adding the internal base to the value of this field. + * | | |Programming Mode: Static + * |[11:8] |addrmap_row_b1|HIF Address Bits for Row Address Bit 1 + * | | |Valid Range: 0 to 11 + * | | |Internal Base: 7 + * | | |The selected HIF address bit for each of the row address bits is determined by adding the internal base to the value of this field. + * | | |Programming Mode: Static + * |[19:16] |addrmap_row_b2_10|HIF Address Bits for Row Address Bits 2 to 10 + * | | |Valid Range: 0 to 11, and 15 + * | | |Internal Base: 8 (for row address bit 2), 9 (for row address bit 3), 10 (for row address bit 4) and so on, increasing to 16 (for row address bit 10) + * | | |The selected HIF address bit for each of the row address bits is determined by adding the internal base to the value of this field. + * | | |When set to 15, the values of row address bits 2 to 10 are defined by registers ADDRMAP9, ADDRMAP10, ADDRMAP11. + * | | |Programming Mode: Static + * |[27:24] |addrmap_row_b11|HIF Address Bits for Row Address Bit 11 + * | | |Valid Range: 0 to 11, and 15 + * | | |Internal Base: 17 + * | | |The selected HIF address bit is determined by adding the internal base to the value of this field. + * | | |If unused, set to 15 and then row address bit 11 is set to 0. + * | | |Programming Mode: Static + * @var UMCTL2_T::ADDRMAP6 + * Offset: 0x218 Address Map Register 6 + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[3:0] |addrmap_row_b12|HIF Address Bit for Row Address Bit 12 + * | | |Valid Range: 0 to 11, and 15 + * | | |Internal Base: 18 + * | | |The selected HIF address bit is determined by adding the internal base to the value of this field. + * | | |If unused, set to 15 and then row address bit 12 is set to 0. + * | | |Programming Mode: Static + * |[11:8] |addrmap_row_b13|HIF Address Bit for Row Address Bit 13 + * | | |Valid Range: 0 to 11, and 15 + * | | |Internal Base: 19 + * | | |The selected HIF address bit is determined by adding the internal base to the value of this field. + * | | |If unused, set to 15 and then row address bit 13 is set to 0. + * | | |Programming Mode: Static + * |[19:16] |addrmap_row_b14|HIF Address Bit for Row Address Bit 14 + * | | |Valid Range: 0 to 11, and 15 + * | | |Internal Base: 20 + * | | |The selected HIF address bit is determined by adding the internal base to the value of this field. + * | | |If unused, set to 15 and then row address bit 14 is set to 0. + * | | |Programming Mode: Static + * |[27:24] |addrmap_row_b15|HIF Address Bit for Row Address Bit 15 + * | | |Valid Range: 0 to 11, and 15 + * | | |Internal Base: 21 + * | | |The selected HIF address bit is determined by adding the internal base to the value of this field. + * | | |If unused, set to 15 and then row address bit 15 is set to 0. + * | | |Programming Mode: Static + * @var UMCTL2_T::ADDRMAP9 + * Offset: 0x224 Address Map Register 9 + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[3:0] |addrmap_row_b2|HIF Address Bits for Row Address Bit 2 + * | | |Valid Range: 0 to 11 + * | | |Internal Base: 8 + * | | |The selected HIF address bit for each of the row address bits is determined by adding the internal base to the value of this field + * | | |This register field is used only when ADDRMAP5.addrmap_row_b2_10 is set to value 15. + * | | |Programming Mode: Static + * |[11:8] |addrmap_row_b3|HIF Address Bits for Row Address Bit 3 + * | | |Valid Range: 0 to 11 + * | | |Internal Base: 9 + * | | |The selected HIF address bit for each of the row address bits is determined by adding the internal base to the value of this field + * | | |This register field is used only when ADDRMAP5.addrmap_row_b2_10 is set to value 15. + * | | |Programming Mode: Static + * |[19:16] |addrmap_row_b4|HIF Address Bits for Row Address Bit 4 + * | | |Valid Range: 0 to 11 + * | | |Internal Base: 10 + * | | |The selected HIF address bit for each of the row address bits is determined by adding the internal base to the value of this field + * | | |This register field is used only when ADDRMAP5.addrmap_row_b2_10 is set to value 15. + * | | |Programming Mode: Static + * |[27:24] |addrmap_row_b5|HIF Address Bits for Row Address Bit 5 + * | | |Valid Range: 0 to 11 + * | | |Internal Base: 11 + * | | |The selected HIF address bit for each of the row address bits is determined by adding the internal base to the value of this field + * | | |This register field is used only when ADDRMAP5.addrmap_row_b2_10 is set to value 15. + * | | |Programming Mode: Static + * @var UMCTL2_T::ADDRMAP10 + * Offset: 0x228 Address Map Register 10 + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[3:0] |addrmap_row_b6|HIF Address Bits for Row Address Bit 6 + * | | |Valid Range: 0 to 11 + * | | |Internal Base: 12 + * | | |The selected HIF address bit for each of the row address bits is determined by adding the internal base to the value of this field + * | | |This register field is used only when ADDRMAP5.addrmap_row_b2_10 is set to value 15. + * | | |Programming Mode: Static + * |[11:8] |addrmap_row_b7|HIF Address Bits for Row Address Bit 7 + * | | |Valid Range: 0 to 11 + * | | |Internal Base: 13 + * | | |The selected HIF address bit for each of the row address bits is determined by adding the internal base to the value of this field + * | | |This register field is used only when ADDRMAP5.addrmap_row_b2_10 is set to value 15. + * | | |Programming Mode: Static + * |[19:16] |addrmap_row_b8|HIF Address Bits for Row Address Bit 8 + * | | |Valid Range: 0 to 11 + * | | |Internal Base: 14 + * | | |The selected HIF address bit for each of the row address bits is determined by adding the internal base to the value of this field + * | | |This register field is used only when ADDRMAP5.addrmap_row_b2_10 is set to value 15. + * | | |Programming Mode: Static + * |[27:24] |addrmap_row_b9|HIF Address Bits for Row Address Bit 9 + * | | |Valid Range: 0 to 11 + * | | |Internal Base: 15 + * | | |The selected HIF address bit for each of the row address bits is determined by adding the internal base to the value of this field + * | | |This register field is used only when ADDRMAP5.addrmap_row_b2_10 is set to value 15. + * | | |Programming Mode: Static + * @var UMCTL2_T::ADDRMAP11 + * Offset: 0x22C Address Map Register 11 + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[3:0] |addrmap_row_b10|HIF Address Bits for Row Address Bit 10 + * | | |Valid Range: 0 to 11 + * | | |Internal Base: 16 + * | | |The selected HIF address bit for each of the row address bits is determined by adding the internal base to the value of this field + * | | |This register field is used only when ADDRMAP5.addrmap_row_b2_10 is set to value 15. + * | | |Programming Mode: Static + * @var UMCTL2_T::ODTCFG + * Offset: 0x240 ODT Configuration Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[6:2] |rd_odt_delay|Delay in DFI PHY Clock Cycles from Issuing a Read Command to Setting ODT Values Associated with that Command + * | | |ODT setting must remain constant for the entire time that DQS is driven by the uMCTL2. + * | | |Recommended values: + * | | |DDR2: + * | | |u00B7 CL + AL - 4 (not DDR2-1066), + * | | |u00B7 CL + AL - 5 (DDR2-1066) If (CL + AL - 4 < 0), uMCTL2 does not support ODT for read operation. + * | | |DDR3: + * | | |u00B7 CL - CWL + * | | |Unit: DFI PHY clock cycles. + * | | |Programming Mode: Quasi-dynamic Group 1, Group 4 + * |[11:8] |rd_odt_hold|DFI PHY Clock Cycles to Hold ODT for a Read Command + * | | |The minimum supported value is 2. + * | | |Recommended values: + * | | |DDR2: + * | | |u00B7 BL8 - 0x6 (not DDR2-1066), 0x7 (DDR2-1066) + * | | |u00B7 BL4 - 0x4 (not DDR2-1066), 0x5 (DDR2-1066) + * | | |DDR3: + * | | |u00B7 BL8 - 0x6 + * | | |Unit: DFI PHY clock cycles. + * | | |Programming Mode: Quasi-dynamic Group 1, Group 4 + * |[20:16] |wr_odt_delay|Delay in DFI PHY Clock Cycles from Issuing a Write Command to Setting ODT Values Associated with that Command + * | | |ODT setting must remain constant for the entire time that DQS is driven by the uMCTL2. + * | | |Recommended values: + * | | |DDR2: + * | | |u00B7 CWL + AL - 3 (DDR2-400/533/667), + * | | |u00B7 CWL + AL - 4 (DDR2-800), + * | | |u00B7 CWL + AL - 5 (DDR2-1066) If (CWL + AL - 3 < 0), uMCTL2 does not support ODT for write operation. + * | | |DDR3: + * | | |u00B7 0x0 + * | | |Unit: DFI PHY clock cycles. + * | | |Programming Mode: Quasi-dynamic Group 1, Group 4 + * |[27:24] |wr_odt_hold|DFI PHY Clock Cycles to Hold ODT for a Write Command + * | | |The minimum supported value is 2. + * | | |Recommended values: + * | | |DDR2: + * | | |u00B7 BL8 - 0x5 (DDR2-400/533/667), 0x6 (DDR2-800), 0x7 (DDR2-1066) + * | | |u00B7 BL4 - 0x3 (DDR2-400/533/667), 0x4 (DDR2-800), 0x5 (DDR2-1066) + * | | |DDR3: + * | | |u00B7 BL8 - 0x6 + * | | |Unit: DFI PHY clock cycles. + * | | |Programming Mode: Quasi-dynamic Group 1, Group 4 + * @var UMCTL2_T::ODTMAP + * Offset: 0x244 ODT/Rank Map Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[1:0] |rank0_wr_odt|Remote ODTs Must be Turned on During a Write to Rank 0. + * | | |Each rank has a remote ODT (in the SDRAM) which can be turned on by setting the appropriate bit here. + * | | |Rank 0 is controlled by the LSB; rank 1 is controlled by bit next to the LSB, and so on. + * | | |For each rank, set its bit to 1 to enable its ODT. + * | | |Programming Mode: Static + * |[5:4] |rank0_rd_odt|Remote ODTs Must be Turned on During a Read from Rank 0 + * | | |Each rank has a remote ODT (in the SDRAM) which can be turned on by setting the appropriate bit here. + * | | |Rank 0 is controlled by the LSB; rank 1 is controlled by bit next to the LSB, and so on. + * | | |For each rank, set its bit to 1 to enable its ODT. + * | | |Programming Mode: Static + * |[9:8] |rank1_wr_odt|Remote ODTs Must be Turned on During a Write to Rank 1 + * | | |Each rank has a remote ODT (in the SDRAM) which can be turned on by setting the appropriate bit here. + * | | |Rank 0 is controlled by the LSB; rank 1 is controlled by bit next to the LSB, and so on. + * | | |For each rank, set its bit to 1 to enable its ODT. + * | | |Present only in configurations that have 2 or more ranks. + * | | |Programming Mode: Static + * |[13:12] |rank1_rd_odt|Remote ODTs Must be Turned on During a Read from Rank 1 + * | | |Each rank has a remote ODT (in the SDRAM) which can be turned on by setting the appropriate bit here. + * | | |Rank 0 is controlled by the LSB; rank 1 is controlled by bit next to the LSB, and so on. + * | | |For each rank, set its bit to 1 to enable its ODT. + * | | |Present only in configurations that have 2 or more ranks. + * | | |Programming Mode: Static + * @var UMCTL2_T::SCHED + * Offset: 0x250 Scheduler Control Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[1] |prefer_write|Setting Bit for Bank Selector Prefers Writes over Reads + * | | |If set, then the bank selector prefers writes over reads. + * | | |FOR DEBUG ONLY. + * | | |Programming Mode: Static + * |[2] |Pageclose |Page Close Bit + * | | |If true, bank is kept open only while there are page hit transactions available in the CAM to that bank. + * | | |The last read or write command in the CAM with a bank and page hit is executed with auto-precharge if SCHED1.pageclose_timer=0. + * | | |Even if this register set to 1 and SCHED1.pageclose_timer is set to 0, explicit precharge (and not auto-precharge) may be issued in some cases where there is a mode switch between Write and Read or between LPR and HPR + * | | |The Read and Write commands that are executed as part of the ECC scrub requests are also executed without auto-precharge. + * | | |If false, the bank remains open until there is a need to close it (to open a different page, or for page timeout or refresh timeout) - also known as open page policy + * | | |The open page policy can be overridden by setting the per-command-autopre bit on the HIF interface (hif_cmd_autopre). + * | | |The pageclose feature provids a midway between Open and Close page policies. + * | | |FOR PERFORMANCE ONLY. + * | | |Programming Mode: Quasi-dynamic Group 3 + * |[12:8] |lpr_num_entries|Number of Entries in the Low Priority Transaction Store + * | | |It is this value + 1. + * | | |(MEMC_NO_OF_ENTRY (hardware configures to 32) - (SCHED.lpr_num_entries + 1)) is the number of entries available for the high priority transaction store. + * | | |Setting this to maximum value allocates all entries to low priority transaction store. + * | | |Setting this to 0 allocates 1 entry to low priority transaction store and the rest to high priority transaction store. + * | | |Programming Mode: Static + * |[23:16] |go2critical_hysteresis|UNUSED. + * | | |Programming Mode: Static + * |[30:24] |rdwr_idle_gap|Switch Clock Cycles Between Different Transaction Store + * | | |When the preferred transaction store is empty for these many clock cycles, switch to the alternate transaction store if it is non-empty. + * | | |The read transaction store (both high and low priority) is the default preferred transaction store and the write transaction store is the alternative store. + * | | |When prefer write over read is set this is reversed. + * | | |0x0 is a legal value for this register + * | | |When set to 0x0, the transaction store switching happens immediately when the switching conditions become true. + * | | |FOR PERFORMANCE ONLY. + * | | |Unit: DFI clock cycles. + * | | |Programming Mode: Static + * @var UMCTL2_T::SCHED1 + * Offset: 0x254 Scheduler Control Register 1 + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[7:0] |pageclose_timer|Page Close Timer + * | | |This field works in conjunction with SCHED.pageclose + * | | |It only has meaning if SCHED.pageclose equals to 1. + * | | |If SCHED.pageclose==1 and pageclose_timer==0, then an auto-precharge may be scheduled for last read or write command in the CAM with a bank and page hit. + * | | |Note, sometimes an explicit precharge is scheduled instead of the auto-precharge + * | | |For more information, see SCHED.pageclose. + * | | |If SCHED.pageclose==1 and pageclose_timer>0, then an auto-precharge is not scheduled for last read or write command in the CAM with a bank and page hit. + * | | |Instead, a timer is started, with pageclose_timer as the initial value. + * | | |There is a timer on a per bank basis. + * | | |The timer decrements unless the next read or write in the CAM to a bank is a page hit. + * | | |It gets reset to pageclose_timer value if the next read or write in the CAM to a bank is a page hit. + * | | |Once the timer has reached zero, an explicit precharge is attempted to be scheduled. + * | | |Unit: DFI clock cycles. + * | | |Programming Mode: Static + * @var UMCTL2_T::PERFHPR1 + * Offset: 0x25C High Priority Read CAM Register 1 + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[15:0] |hpr_max_starve|Number of DFI Clocks that the HPR Queue can be Starved Before It Goes Critical + * | | |Indicates the number of DFI clocks that the HPR queue can be starved before it goes critical. + * | | |The minimum valid functional value for this register is 0x1. + * | | |Programming it to 0x0 disables the starvation functionality. + * | | |During normal operation, this function must not be disabled as it causes excessive latencies. + * | | |FOR PERFORMANCE ONLY. + * | | |Unit: DFI clock cycles. + * | | |Programming Mode: Quasi-dynamic Group 3 + * |[31:24] |hpr_xact_run_length|Number of Transactions that are Serviced once the HPR Queue Goes Critical + * | | |Indicates the number of transactions that are serviced once the HPR queue goes critical is the smaller of: + * | | |u00B7 (a) This number + * | | |u00B7 (b) Number of transactions available + * | | |Unit: Transaction. + * | | |FOR PERFORMANCE ONLY. + * | | |Programming Mode: Quasi-dynamic Group 3 + * @var UMCTL2_T::PERFLPR1 + * Offset: 0x264 Low Priority Read CAM Register 1 + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[15:0] |lpr_max_starve|Number of DFI Clocks that the LPR Queue can be Starved Before It Goes Critical + * | | |Indicates the number of DFI clocks that the LPR queue can be starved before it goes critical. + * | | |The minimum valid functional value for this register is 0x1. + * | | |Programming it to 0x0 disables the starvation functionality. + * | | |During normal operation, this function must not be disabled as it causes excessive latencies. + * | | |FOR PERFORMANCE ONLY. + * | | |Unit: DFI clock cycles. + * | | |Programming Mode: Quasi-dynamic Group 3 + * |[31:24] |lpr_xact_run_length|Number of Transactions that are Serviced Once the LPR Queue Goes Critical + * | | |Indicates the number of transactions that are serviced once the LPR queue goes critical is the smaller of: + * | | |u00B7 (a) This number + * | | |u00B7 (b) Number of transactions available + * | | |Unit: Transaction. + * | | |FOR PERFORMANCE ONLY. + * | | |Programming Mode: Quasi-dynamic Group 3 + * @var UMCTL2_T::PERFWR1 + * Offset: 0x26C Write CAM Register 1 + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[15:0] |w_max_starve|Number of DFI Clocks that the WR Queue can be Starved Before It Goes Critical + * | | |Indicates the number of DFI clocks that the WR queue can be starved before it goes critical. + * | | |The minimum valid functional value for this register is 0x1. + * | | |Programming it to 0x0 disables the starvation functionality. + * | | |During normal operation, this function must not be disabled as it causes excessive latencies. + * | | |FOR PERFORMANCE ONLY. + * | | |Unit: DFI clock cycles. + * | | |Programming Mode: Quasi-dynamic Group 3 + * |[31:24] |w_xact_run_length|Number of Transactions that are Serviced Once the WR Queue Goes Critical + * | | |Indicates the number of transactions that are serviced once the WR queue goes critical is the smaller of: + * | | |u00B7 (a) This number + * | | |u00B7 (b) Number of transactions available + * | | |Unit: Transaction. + * | | |FOR PERFORMANCE ONLY. + * | | |Programming Mode: Quasi-dynamic Group 3 + * @var UMCTL2_T::DBG0 + * Offset: 0x300 Debug Register 0 + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[0] |dis_wc |Disable Bit for Write Combine + * | | |When 1, disable write combine. + * | | |FOR DEBUG ONLY. + * | | |Programming Mode: Static + * |[1] |dis_rd_bypass|Disable Bit for Bypass Path for High Priority Read Page Hits + * | | |Only present in designs supporting read bypass. + * | | |When 1, disable bypass path for high priority read page hits. + * | | |FOR DEBUG ONLY. + * | | |Programming Mode: Static + * |[2] |dis_act_bypass|Disable Bit for Bypass Path for High Priority Read Activates + * | | |Only present in designs supporting activate bypass. + * | | |When 1, disable bypass path for high priority read activates. + * | | |FOR DEBUG ONLY. + * | | |Programming Mode: Static + * |[4] |dis_collision_page_opt|Disable Bit for Collision Page Option + * | | |When this is set to '0', auto-precharge is disabled for the flushed command in a collision case. + * | | |Collision cases are write followed by read to same address, read followed by write to same address, or write followed by write to same address with DBG0.dis_wc bit = 1 (where same address comparisons exclude the two address bits representing critical word). + * | | |FOR DEBUG ONLY. + * | | |Programming Mode: Static + * |[6] |dis_max_rank_rd_opt|Disable Bit to Optimize max_rank_rd and max_logical_rank_rd + * | | |This register is for debug purpose only. + * | | |For normal operation, this register must be set to 0. + * | | |Programming Mode: Static + * |[7] |dis_max_rank_wr_opt|Disable Bit to Optimize max_rank_wr and max_logical_rank_wr + * | | |This register is for debug purpose only. + * | | |For normal operation, this register must be set to 0. + * | | |Programming Mode: Static + * @var UMCTL2_T::DBG1 + * Offset: 0x304 Debug Register 1 + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[0] |dis_dq |Disable Bit for De-queue Transactions + * | | |When 1, uMCTL2 does not de-queue any transactions from the CAM. + * | | |Bypass is also disabled. + * | | |All transactions are queued in the CAM + * | | |No reads or writes are issued to SDRAM as long as this is asserted. + * | | |This bit may be used to prevent reads or writes being issued by the uMCTL2, which makes it safe to modify certain register fields associated with reads and writes. + * | | |After setting this bit, it is strongly recommended to poll DBGCAM.wr_data_pipeline_empty and DBGCAM.rd_data_pipeline_empty, before making changes to any registers which affect reads and writes. + * | | |This ensures that the relevant logic in the DDRC is idle. + * | | |This bit is intended to be switched on-the-fly. + * | | |Programming Mode: Dynamic + * |[1] |dis_hif |Disable Bit for HIF Command + * | | |When 1, uMCTL2 asserts the HIF command signal hif_cmd_stall. + * | | |uMCTL2 ignores the hif_cmd_valid and all other associated request signals. + * | | |This bit is intended to be switched on-the-fly. + * | | |Programming Mode: Dynamic + * @var UMCTL2_T::DBGCAM + * Offset: 0x308 CAM Debug Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[5:0] |dbg_hpr_q_depth|High Priority Read Queue Depth + * | | |FOR DEBUG ONLY. + * | | |Programming Mode: Dynamic + * |[13:8] |dbg_lpr_q_depth|Low Priority Read Queue Depth + * | | |The last entry of LPR queue is reserved for ECC SCRUB operation + * | | |This entry is not included in the calculation of the queue depth. + * | | |FOR DEBUG ONLY + * | | |Programming Mode: Dynamic + * |[21:16] |dbg_w_q_depth|Write Queue Depth + * | | |The last entry of WR queue is reserved for ECC SCRUB operation + * | | |This entry is not included in the calculation of the queue depth. + * | | |FOR DEBUG ONLY + * | | |Programming Mode: Dynamic + * |[24] |dbg_stall |Command Queues and Data Buffers Stall + * | | |FOR DEBUG ONLY. + * | | |Programming Mode: Dynamic + * |[25] |dbg_rd_q_empty|Read Command Queues and Read Data Buffers Empty + * | | |When 1, all the Read command queues and Read data buffers inside DDRC are empty. + * | | |This register is to be used for debug purpose. + * | | |An example use-case scenario: When the controller enters self-refresh using the Low-Power entry sequence, controller is expected to have executed all the commands in its queues and the write and read data drained + * | | |Hence this register must be 1 at that time. + * | | |FOR DEBUG ONLY + * | | |Programming Mode: Dynamic + * |[26] |dbg_wr_q_empty|Write Command Queues and Write Data Buffers Empty + * | | |When 1, all the Write command queues and Write data buffers inside DDRC are empty. + * | | |This register is to be used for debug purpose. + * | | |An example use-case scenario: When the controller enters self-refresh using the Low-Power entry sequence, controller is expected to have executed all the commands in its queues and the write and read data drained + * | | |Hence this register must be 1 at that time. + * | | |FOR DEBUG ONLY + * | | |Programming Mode: Dynamic + * |[28] |rd_data_pipeline_empty|Read Data Pipeline Empty + * | | |This bit indicates that the read data pipeline on the DFI interface is empty. + * | | |This register is intended to be polled at least twice after setting DBG1.dis_dq, to ensure that all remaining commands/data have completed. + * | | |Programming Mode: Dynamic + * |[29] |wr_data_pipeline_empty|Write Data Pipeline Empty + * | | |This bit indicates that the write data pipeline on the DFI interface is empty. + * | | |This register is intended to be polled at least twice after setting DBG1.dis_dq, to ensure that all remaining commands/data have completed. + * | | |Programming Mode: Dynamic + * @var UMCTL2_T::DBGCMD + * Offset: 0x30C Command Debug Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[0] |rank0_refresh|Signal for uMCTL2 to Issue Refresh to Rank 0 + * | | |Setting this register bit to 1 indicates to the uMCTL2 to issue a refresh to rank 0. + * | | |Writing to this bit causes DBGSTAT.rank0_refresh_busy to be set. + * | | |When DBGSTAT.rank0_refresh_busy is cleared, the command has been stored in uMCTL2. + * | | |For 3DS configuration, refresh is sent to rank index 0. + * | | |This operation can be performed only when RFSHCTL3.dis_auto_refresh=1. + * | | |It is recommended NOT to set this register bit if in Init or Deep power-down operating modes or Maximum Power Saving Mode. + * | | |Testable: readOnly + * | | |Programming Mode: Dynamic + * |[1] |rank1_refresh|Signal for uMCTL2 to Issue Refresh to Rank 1 + * | | |Setting this register bit to 1 indicates to the uMCTL2 to issue a refresh to rank 1. + * | | |Writing to this bit causes DBGSTAT.rank1_refresh_busy to be set. + * | | |When DBGSTAT.rank1_refresh_busy is cleared, the command has been stored in uMCTL2. + * | | |For 3DS configuration, refresh is sent to rank index 1. + * | | |This operation can be performed only when RFSHCTL3.dis_auto_refresh=1. + * | | |It is recommended NOT to set this register bit if in Init or Deep power-down operating modes or Maximum Power Saving Mode. + * | | |Testable: readOnly + * | | |Programming Mode: Dynamic + * |[4] |zq_calib_short|Signal for uMCTL2 to Issue ZQCS to SDRAM + * | | |Setting this register bit to 1 indicates to the uMCTL2 to issue a ZQCS (ZQ calibration short)/MPC(ZQ calibration) command to the SDRAM. + * | | |When this request is stored in the uMCTL2, the bit is automatically cleared. + * | | |This operation can be performed only when ZQCTL0.dis_auto_zq=1. + * | | |It is recommended NOT to set this register bit if in Init, in self-refresh or Deep power-down operating modes or Maximum Power Saving Mode. + * | | |For Deep power down and Maximum Power Saving Mode, it is not scheduled, although DBGSTAT.zq_calib_short_busy is de-asserted. + * | | |Testable: readOnly + * | | |Programming Mode: Dynamic + * |[5] |ctrlupd |Signal for uMCTL2 to Issue dfi_ctrlupd_req to PHY + * | | |Setting this register bit to 1 indicates to the uMCTL2 to issue a dfi_ctrlupd_req to the PHY. + * | | |When this request is stored in the uMCTL2, the bit is automatically cleared. + * | | |This operation must only be performed when DFIUPD0.dis_auto_ctrlupd=1. + * | | |Testable: readOnly + * | | |Programming Mode: Dynamic + * @var UMCTL2_T::DBGSTAT + * Offset: 0x310 Status Debug Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[0] |rank0_refresh_busy|Rank0 Refresh Operation Busy + * | | |SoC might initiate a rank0_refresh operation (refresh operation to rank 0) only if this signal is low. + * | | |This signal goes high in the clock after DBGCMD.rank0_refresh is set to one + * | | |It goes low when the rank0_refresh operation is stored in the uMCTL2. + * | | |It is recommended not to perform rank0_refresh operations when this signal is high. + * | | |u00B7 0 - Indicates that the SoC can initiate a rank0_refresh operation + * | | |u00B7 1 - Indicates that rank0_refresh operation has not been stored yet in the uMCTL2 + * | | |Programming Mode: Dynamic + * |[1] |rank1_refresh_busy|Rank1 Refresh Operation Busy + * | | |SoC might initiate a rank1_refresh operation (refresh operation to rank 1) only if this signal is low. + * | | |This signal goes high in the clock after DBGCMD.rank1_refresh is set to one + * | | |It goes low when the rank1_refresh operation is stored in the uMCTL2. + * | | |It is recommended not to perform rank1_refresh operations when this signal is high. + * | | |u00B7 0 - Indicates that the SoC can initiate a rank1_refresh operation + * | | |u00B7 1 - Indicates that rank1_refresh operation has not been stored yet in the uMCTL2 + * | | |Programming Mode: Dynamic + * |[4] |zq_calib_short_busy|ZQCS Operation Busy State + * | | |SoC might initiate a ZQCS (ZQ calibration short) operation only if this signal is low. + * | | |This signal goes high in the clock after the uMCTL2 accepts the ZQCS request. + * | | |It goes low when the ZQCS operation is initiated in the uMCTL2 + * | | |It is recommended not to perform ZQCS operations when this signal is high. + * | | |u00B7 0 - Indicates that the SoC can initiate a ZQCS operation + * | | |u00B7 1 - Indicates that ZQCS operation has not been initiated yet in the uMCTL2 + * | | |Programming Mode: Dynamic + * |[5] |ctrlupd_busy|ctrlupd Operation Busy State + * | | |SoC might initiate a ctrlupd operation only if this signal is low. + * | | |This signal goes high in the clock after the uMCTL2 accepts the ctrlupd request. + * | | |It goes low when the ctrlupd operation is initiated in the uMCTL2. + * | | |It is recommended not to perform ctrlupd operations when this signal is high. + * | | |u00B7 0 - Indicates that the SoC can initiate a ctrlupd operation + * | | |u00B7 1 - Indicates that ctrlupd operation has not been initiated yet in the uMCTL2 + * | | |Programming Mode: Dynamic + * @var UMCTL2_T::SWCTL + * Offset: 0x320 Software Register Programming Control Enable + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[0] |sw_done |Quasi-Dynamic Register Programming Enable Bit + * | | |Enables quasi-dynamic register programming outside reset. + * | | |Program this register to 0 to enable quasi-dynamic programming. + * | | |Set back register to 1 once programming is done. + * | | |Programming Mode: Dynamic + * @var UMCTL2_T::SWSTAT + * Offset: 0x324 Software Register Programming Control Status + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[0] |sw_done_ack|Register Programming Done ACK + * | | |This register is the echo of SWCTL.sw_done. + * | | |Wait for sw_done value 1 to propagate to sw_done_ack at the end of the programming sequence to ensure that the correct registers values are propagated to the destination clock domains. + * | | |Testable: untestable + * | | |Programming Mode: Static + * @var UMCTL2_T::SWCTLSTATIC + * Offset: 0x328 Static Registers Write Enable + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[0] |sw_static_unlock|Static Register Programming Unlock Bit + * | | |Enables static register programming outside reset. + * | | |Program this register to 1 to enable static register programming. + * | | |Set register back to 0 once programming is done. + * | | |Programming Mode: Dynamic + * @var UMCTL2_T::POISONCFG + * Offset: 0x36C AXI Poison Configuration Register. Common for all AXI ports. + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[0] |wr_poison_slverr_en|Write Transaction Poisoning SLVERR Response Enable Bit + * | | |If set to 1, enables SLVERR response for write transaction poisoning. + * | | |Programming Mode: Dynamic + * |[4] |wr_poison_intr_en|Write Transaction Poisoning Interrupt Enable Bit + * | | |If set to 1, enables interrupts for write transaction poisoning. + * | | |Programming Mode: Dynamic + * |[8] |wr_poison_intr_clr|Write Transaction Poisoning Interrupt Clear Bit + * | | |Interrupt clear for write transaction poisoning. + * | | |Allow 2/3 clock cycles for correct value to propagate to controller logic and clear the interrupts. + * | | |uMCTL2 automatically clears this bit. + * | | |Testable: readOnly + * | | |Programming Mode: Dynamic + * |[16] |rd_poison_slverr_en|Read Transaction Poisoning SLVERR Response Enable Bit + * | | |If set to 1, enables SLVERR response for read transaction poisoning. + * | | |Programming Mode: Dynamic + * |[20] |rd_poison_intr_en|Read Transaction Poisoning Interrupt Enable Bit + * | | |If set to 1, enables interrupts for read transaction poisoning. + * | | |Programming Mode: Dynamic + * |[24] |rd_poison_intr_clr|Read Transaction Poisoning Interrupt Clear Bit + * | | |Allow 2/3 clock cycles for correct value to propagate to controller logic and clear the interrupts. + * | | |uMCTL2 automatically clears this bit. + * | | |Testable: readOnly + * | | |Programming Mode: Dynamic + * @var UMCTL2_T::POISONSTAT + * Offset: 0x370 AXI Poison Status Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[0] |wr_poison_intr_0|Write Transaction Poisoning Error Interrupt for Port 0 + * | | |This register is a APB clock copy (double register synchronizer) of the interrupt asserted when a transaction is poisoned on the corresponding AXI port's write address channel. + * | | |Bit 0 corresponds to Port 0, and so on + * | | |Interrupt is cleared by register wr_poison_intr_clr, then value propagated to APB clock. + * | | |Programming Mode: Dynamic + * |[1] |wr_poison_intr_1|Write Transaction Poisoning Error Interrupt for Port 1 + * | | |This register is a APB clock copy (double register synchronizer) of the interrupt asserted when a transaction is poisoned on the corresponding AXI port's write address channel. + * | | |Bit 0 corresponds to Port 0, and so on + * | | |Interrupt is cleared by register wr_poison_intr_clr, then value propagated to APB clock. + * | | |Programming Mode: Dynamic + * |[2] |wr_poison_intr_2|Write Transaction Poisoning Error Interrupt for Port 2 + * | | |This register is a APB clock copy (double register synchronizer) of the interrupt asserted when a transaction is poisoned on the corresponding AXI port's write address channel. + * | | |Bit 0 corresponds to Port 0, and so on + * | | |Interrupt is cleared by register wr_poison_intr_clr, then value propagated to APB clock. + * | | |Programming Mode: Dynamic + * |[3] |wr_poison_intr_3|Write Transaction Poisoning Error Interrupt for Port 3 + * | | |This register is a APB clock copy (double register synchronizer) of the interrupt asserted when a transaction is poisoned on the corresponding AXI port's write address channel. + * | | |Bit 0 corresponds to Port 0, and so on + * | | |Interrupt is cleared by register wr_poison_intr_clr, then value propagated to APB clock. + * | | |Programming Mode: Dynamic + * |[4] |wr_poison_intr_4|Write Transaction Poisoning Error Interrupt for Port 4 + * | | |This register is a APB clock copy (double register synchronizer) of the interrupt asserted when a transaction is poisoned on the corresponding AXI port's write address channel. + * | | |Bit 0 corresponds to Port 0, and so on + * | | |Interrupt is cleared by register wr_poison_intr_clr, then value propagated to APB clock. + * | | |Programming Mode: Dynamic + * |[5] |wr_poison_intr_5|Write Transaction Poisoning Error Interrupt for Port 5 + * | | |This register is a APB clock copy (double register synchronizer) of the interrupt asserted when a transaction is poisoned on the corresponding AXI port's write address channel. + * | | |Bit 0 corresponds to Port 0, and so on + * | | |Interrupt is cleared by register wr_poison_intr_clr, then value propagated to APB clock. + * | | |Programming Mode: Dynamic + * |[6] |wr_poison_intr_6|Write Transaction Poisoning Error Interrupt for Port 6 + * | | |This register is a APB clock copy (double register synchronizer) of the interrupt asserted when a transaction is poisoned on the corresponding AXI port's write address channel. + * | | |Bit 0 corresponds to Port 0, and so on + * | | |Interrupt is cleared by register wr_poison_intr_clr, then value propagated to APB clock. + * | | |Programming Mode: Dynamic + * |[7] |wr_poison_intr_7|Write Transaction Poisoning Error Interrupt for Port 7 + * | | |This register is a APB clock copy (double register synchronizer) of the interrupt asserted when a transaction is poisoned on the corresponding AXI port's write address channel. + * | | |Bit 0 corresponds to Port 0, and so on + * | | |Interrupt is cleared by register wr_poison_intr_clr, then value propagated to APB clock. + * | | |Programming Mode: Dynamic + * |[16] |rd_poison_intr_0|Read Transaction Poisoning Error Interrupt for Port 0 + * | | |This register is a APB clock copy (double register synchronizer) of the interrupt asserted when a transaction is poisoned on the corresponding AXI port's read address channel. + * | | |Bit 0 corresponds to Port 0, and so on + * | | |Interrupt is cleared by register rd_poison_intr_clr, then value propagated to APB clock. + * | | |Programming Mode: Dynamic + * |[17] |rd_poison_intr_1|Read Transaction Poisoning Error Interrupt for Port 1 + * | | |This register is a APB clock copy (double register synchronizer) of the interrupt asserted when a transaction is poisoned on the corresponding AXI port's read address channel. + * | | |Bit 0 corresponds to Port 0, and so on + * | | |Interrupt is cleared by register rd_poison_intr_clr, then value propagated to APB clock. + * | | |Programming Mode: Dynamic + * |[18] |rd_poison_intr_2|Read Transaction Poisoning Error Interrupt for Port 2 + * | | |This register is a APB clock copy (double register synchronizer) of the interrupt asserted when a transaction is poisoned on the corresponding AXI port's read address channel. + * | | |Bit 0 corresponds to Port 0, and so on + * | | |Interrupt is cleared by register rd_poison_intr_clr, then value propagated to APB clock. + * | | |Programming Mode: Dynamic + * |[19] |rd_poison_intr_3|Read Transaction Poisoning Error Interrupt for Port 3 + * | | |This register is a APB clock copy (double register synchronizer) of the interrupt asserted when a transaction is poisoned on the corresponding AXI port's read address channel. + * | | |Bit 0 corresponds to Port 0, and so on + * | | |Interrupt is cleared by register rd_poison_intr_clr, then value propagated to APB clock. + * | | |Programming Mode: Dynamic + * |[20] |rd_poison_intr_4|Read Transaction Poisoning Error Interrupt for Port 4 + * | | |This register is a APB clock copy (double register synchronizer) of the interrupt asserted when a transaction is poisoned on the corresponding AXI port's read address channel. + * | | |Bit 0 corresponds to Port 0, and so on + * | | |Interrupt is cleared by register rd_poison_intr_clr, then value propagated to APB clock. + * | | |Programming Mode: Dynamic + * |[21] |rd_poison_intr_5|Read Transaction Poisoning Error Interrupt for Port 5 + * | | |This register is a APB clock copy (double register synchronizer) of the interrupt asserted when a transaction is poisoned on the corresponding AXI port's read address channel. + * | | |Bit 0 corresponds to Port 0, and so on + * | | |Interrupt is cleared by register rd_poison_intr_clr, then value propagated to APB clock. + * | | |Programming Mode: Dynamic + * |[22] |rd_poison_intr_6|Read Transaction Poisoning Error Interrupt for Port 6 + * | | |This register is a APB clock copy (double register synchronizer) of the interrupt asserted when a transaction is poisoned on the corresponding AXI port's read address channel. + * | | |Bit 0 corresponds to Port 0, and so on + * | | |Interrupt is cleared by register rd_poison_intr_clr, then value propagated to APB clock. + * | | |Programming Mode: Dynamic + * |[23] |rd_poison_intr_7|Read Transaction Poisoning Error Interrupt for Port 7 + * | | |This register is a APB clock copy (double register synchronizer) of the interrupt asserted when a transaction is poisoned on the corresponding AXI port's read address channel. + * | | |Bit 0 corresponds to Port 0, and so on + * | | |Interrupt is cleared by register rd_poison_intr_clr, then value propagated to APB clock. + * | | |Programming Mode: Dynamic + * @var UMCTL2_T::PSTAT + * Offset: 0x3FC Port Status Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[0] |rd_port_busy_0|Outstanding Reads for AXI Port 0 + * | | |Indicates if there are outstanding reads for AXI port 0. + * | | |Programming Mode: Dynamic + * |[1] |rd_port_busy_1|Outstanding Reads for AXI Port 1 + * | | |Indicates if there are outstanding reads for AXI port 1. + * | | |Programming Mode: Dynamic + * |[2] |rd_port_busy_2|Outstanding Reads for AXI Port 2 + * | | |Indicates if there are outstanding reads for AXI port 2. + * | | |Programming Mode: Dynamic + * |[3] |rd_port_busy_3|Outstanding Reads for AXI Port 3 + * | | |Indicates if there are outstanding reads for AXI port 3. + * | | |Programming Mode: Dynamic + * |[4] |rd_port_busy_4|Outstanding Reads for AXI Port 4 + * | | |Indicates if there are outstanding reads for AXI port 4. + * | | |Programming Mode: Dynamic + * |[5] |rd_port_busy_5|Outstanding Reads for AXI Port 5 + * | | |Indicates if there are outstanding reads for AXI port 5. + * | | |Programming Mode: Dynamic + * |[6] |rd_port_busy_6|Outstanding Reads for AXI Port 6 + * | | |Indicates if there are outstanding reads for AXI port 6. + * | | |Programming Mode: Dynamic + * |[7] |rd_port_busy_7|Outstanding Reads for AXI Port 7 + * | | |Indicates if there are outstanding reads for AXI port 7. + * | | |Programming Mode: Dynamic + * |[16] |wr_port_busy_0|Outstanding Writes for AXI Port 0 + * | | |Indicates if there are outstanding writes for AXI port 0. + * | | |Programming Mode: Dynamic + * |[17] |wr_port_busy_1|Outstanding Writes for AXI Port 1 + * | | |Indicates if there are outstanding writes for AXI port 1. + * | | |Programming Mode: Dynamic + * |[18] |wr_port_busy_2|Outstanding Writes for AXI Port 2 + * | | |Indicates if there are outstanding writes for AXI port 2. + * | | |Programming Mode: Dynamic + * |[19] |wr_port_busy_3|Outstanding Writes for AXI Port 3 + * | | |Indicates if there are outstanding writes for AXI port 3. + * | | |Programming Mode: Dynamic + * |[20] |wr_port_busy_4|Outstanding Writes for AXI Port 4 + * | | |Indicates if there are outstanding writes for AXI port 4. + * | | |Programming Mode: Dynamic + * |[21] |wr_port_busy_5|Outstanding Writes for AXI Port 5 + * | | |Indicates if there are outstanding writes for AXI port 5. + * | | |Programming Mode: Dynamic + * |[22] |wr_port_busy_6|Outstanding Writes for AXI Port 6 + * | | |Indicates if there are outstanding writes for AXI port 6. + * | | |Programming Mode: Dynamic + * |[23] |wr_port_busy_7|Outstanding Writes for AXI Port 7 + * | | |Indicates if there are outstanding writes for AXI port 7. + * | | |Programming Mode: Dynamic + * @var UMCTL2_T::PCCFG + * Offset: 0x400 Port Common Configuration Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[0] |go2critical_en|go2critical Function Enable Bit + * | | |If set to 1 (enabled), sets co_gs_go2critical_wr and co_gs_go2critical_lpr/co_gs_go2critical_hpr signals going to DDRC based on urgent input (awurgent, arurgent) coming from AXI master. + * | | |If set to 0 (disabled), co_gs_go2critical_wr and co_gs_go2critical_lpr/co_gs_go2critical_hpr signals at DDRC are driven to 1b'0. + * | | |For uPCTL2, this register field must be set to 0. + * | | |Programming Mode: Static + * |[4] |pagematch_limit|Page Match Four Limit + * | | |If set to 1, limits the number of consecutive same page DDRC transactions that can be granted by the Port Arbiter to four when Page Match feature is enabled. + * | | |If set to 0, there is no limit imposed on number of consecutive same page DDRC transactions. + * | | |Programming Mode: Static + * |[8] |bl_exp_mode|Burst Length Expansion Mode + * | | |By default, (that is, bl_exp_mode==0) XPI expands every AXI burst into multiple HIF commands, using the memory burst length as a unit + * | | |If set to 1, then XPI uses half of the memory burst length as a unit. + * | | |This applies to both reads and writes + * | | |When MSTR.data_bus_width==00, setting bl_exp_mode to 1 has no effect. + * | | |Functionality is also not supported if Data Channel Interleave is enabled. + * | | |Programming Mode: Static + * @var UMCTL2_T::PCFGR_0 + * Offset: 0x404 Port n Configuration Read Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[9:0] |rd_port_priority|Read Channel of Port Priority + * | | |Determines the initial load value of read aging counters. + * | | |These counters are parallel loaded after reset, or after each grant to the corresponding port. + * | | |The aging counters down-count every clock cycle where the port is requesting but not granted + * | | |The higher significant 5-bits of the read aging counter sets the priority of the read channel of a given port. + * | | |Port's priority increases as the higher significant 5-bits of the counter starts to decrease. + * | | |When the aging counter becomes 0, the corresponding port channel has the highest priority level (timeout condition - Priority0). + * | | |For multi-port configurations, the aging counters cannot be used to set port priorities when external dynamic priority inputs (arqos) are enabled (timeout is still applicable). + * | | |For single port configurations, the aging counters are only used when they timeout (become 0) to force read-write direction switching. + * | | |In this case, external dynamic priority input, arqos (for reads only) can still be used to set the DDRC read priority (2 priority levels: low priority read - LPR, high priority read - HPR) on a command by command basis. + * | | |Note: The two LSBs of this register field are tied internally to 2'b00. + * | | |Programming Mode: Static + * |[12] |rd_port_aging_en|Read Channel of Port Aging Function Enable Bit + * | | |If set to 1, enables aging function for the read channel of the port. + * | | |Programming Mode: Static + * |[13] |rd_port_urgent_en|AXI Urgent Sideband Signal (arurgent) Enable Bit + * | | |If set to 1, enables the AXI urgent sideband signal (arurgent) + * | | |When enabled and arurgent is asserted by the master, that port becomes the highest priority and co_gs_go2critical_lpr/co_gs_go2critical_hpr signal to DDRC is asserted if enabled in PCCFG.go2critical_en register. + * | | |Note that arurgent signal can be asserted anytime and as long as required which is independent of address handshaking (it is not associated with any particular command). + * | | |Programming Mode: Static + * |[14] |rd_port_pagematch_en|Read Page Match Enable Bit + * | | |If set to 1, enables the Page Match feature + * | | |If enabled, once a requesting port is granted, the port is continued to be granted if the following immediate commands are to the same memory page (same rank, same bank and same row). + * | | |See also related PCCFG.pagematch_limit register. + * | | |Programming Mode: Static + * |[16] |rdwr_ordered_en|Read/Writes Ordered Enable Bit + * | | |If set to 1, preserves the ordering between read transaction and write transaction issued to the same address, on a given port. + * | | |In other words, the controller ensures that all same address read and write commands from the application port interface are transported to the DFI interface in the order of acceptance. + * | | |This feature is useful in cases where software coherency is desired for masters issuing back-to-back read/write transactions without waiting for write/read responses. + * | | |Note that this register has an effect only if necessary logic is instantiated through the UMCTL2_RDWR_ORDERED_n parameter. + * | | |Programming Mode: Static + * @var UMCTL2_T::PCFGW_0 + * Offset: 0x408 Port n Configuration Write Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[9:0] |wr_port_priority|Write Channel of Port Priority + * | | |Determines the initial load value of write aging counters. + * | | |These counters are parallel loaded after reset, or after each grant to the corresponding port. + * | | |The aging counters down-count every clock cycle where the port is requesting but not granted. + * | | |The higher significant 5-bits of the write aging counter sets the initial priority of the write channel of a given port. + * | | |Port's priority increases as the higher significant 5-bits of the counter starts to decrease + * | | |When the aging counter becomes 0, the corresponding port channel has the highest priority level. + * | | |For multi-port configurations, the aging counters cannot be used to set port priorities when external dynamic priority inputs (awqos) are enabled (timeout is still applicable). + * | | |For single port configurations, the aging counters are only used when they timeout (become 0) to force read-write direction switching. + * | | |Note: The two LSBs of this register field are tied internally to 2'b00. + * | | |Programming Mode: Static + * |[12] |wr_port_aging_en|Write Channel of Port Aging Function Enable Bit + * | | |If set to 1, enables aging function for the write channel of the port. + * | | |Programming Mode: Static + * |[13] |wr_port_urgent_en|AXI Urgent Sideband Signal (awurgent) Enable Bit + * | | |If set to 1, enables the AXI urgent sideband signal (awurgent). + * | | |When enabled and awurgent is asserted by the master, that port becomes the highest priority and co_gs_go2critical_wr signal to DDRC is asserted if enabled in PCCFG.go2critical_en register. + * | | |Note that awurgent signal can be asserted anytime and as long as required which is independent of address handshaking (it is not associated with any particular command). + * | | |Programming Mode: Static + * |[14] |wr_port_pagematch_en|Write Page Match Enable Bit + * | | |If set to 1, enables the Page Match feature. + * | | |If enabled, once a requesting port is granted, the port is continued to be granted if the following immediate commands are to the same memory page (same rank, same bank and same row). + * | | |See also related PCCFG.pagematch_limit register. + * | | |Programming Mode: Static + * @var UMCTL2_T::PCTRL_0 + * Offset: 0x490 Port n Control Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[0] |port_en |AXI Port n Enable Bit + * | | |Programming Mode: Dynamic + * @var UMCTL2_T::PCFGQOS0_0 + * Offset: 0x494 Port n Read QoS Configuration Register 0 + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[3:0] |rqos_map_level1|End of Region0 Mapping + * | | |Separation level1 indicating the end of region0 mapping; start of region0 is 0 + * | | |Possible values for level1 are 0 to 13 (for dual RAQ) or 0 to 14 (for single RAQ) which corresponds to arqos. + * | | |Note that for PA, arqos values are used directly as port priorities, where the higher the value corresponds to higher port priority. + * | | |All of the map_level* registers must be set to distinct values. + * | | |Programming Mode: Quasi-dynamic Group 3 + * |[17:16] |rqos_map_region0|Traffic Class of Region 0 + * | | |This bit field indicates the traffic class of region 0. + * | | |Valid values are: + * | | |u00B7 0 - LPR + * | | |u00B7 1 - VPR + * | | |u00B7 2 - HPR + * | | |For dual address queue configurations, region 0 maps to the blue address queue. + * | | |In this case, valid values are: + * | | |0: LPR and 1: VPR only. + * | | |When VPR support is disabled (UMCTL2_VPR_EN = 0) and traffic class of region0 is set to 1 (VPR), VPR traffic is aliased to LPR traffic. + * | | |Programming Mode: Quasi-dynamic Group 3 + * |[21:20] |rqos_map_region1|Traffic Class of Region 1 + * | | |This bit field indicates the traffic class of region 1. + * | | |Valid values are: + * | | |u00B7 0 - LPR + * | | |u00B7 1 - VPR + * | | |u00B7 2 - HPR + * | | |For dual address queue configurations, region1 maps to the blue address queue. + * | | |In this case, valid values are + * | | |u00B7 0 - LPR + * | | |u00B7 1 - VPR only + * | | |When VPR support is disabled (UMCTL2_VPR_EN = 0) and traffic class of region 1 is set to 1 (VPR), VPR traffic is aliased to LPR traffic. + * | | |Programming Mode: Quasi-dynamic Group 3 + * @var UMCTL2_T::PCFGR_1 + * Offset: 0x4B4 Port n Configuration Read Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[9:0] |rd_port_priority|Read Channel of Port Priority + * | | |Determines the initial load value of read aging counters. + * | | |These counters are parallel loaded after reset, or after each grant to the corresponding port. + * | | |The aging counters down-count every clock cycle where the port is requesting but not granted + * | | |The higher significant 5-bits of the read aging counter sets the priority of the read channel of a given port. + * | | |Port's priority increases as the higher significant 5-bits of the counter starts to decrease. + * | | |When the aging counter becomes 0, the corresponding port channel has the highest priority level (timeout condition - Priority0). + * | | |For multi-port configurations, the aging counters cannot be used to set port priorities when external dynamic priority inputs (arqos) are enabled (timeout is still applicable). + * | | |For single port configurations, the aging counters are only used when they timeout (become 0) to force read-write direction switching. + * | | |In this case, external dynamic priority input, arqos (for reads only) can still be used to set the DDRC read priority (2 priority levels: low priority read - LPR, high priority read - HPR) on a command by command basis. + * | | |Note: The two LSBs of this register field are tied internally to 2'b00. + * | | |Programming Mode: Static + * |[12] |rd_port_aging_en|Read Channel of Port Aging Function Enable Bit + * | | |If set to 1, enables aging function for the read channel of the port. + * | | |Programming Mode: Static + * |[13] |rd_port_urgent_en|AXI Urgent Sideband Signal (arurgent) Enable Bit + * | | |If set to 1, enables the AXI urgent sideband signal (arurgent) + * | | |When enabled and arurgent is asserted by the master, that port becomes the highest priority and co_gs_go2critical_lpr/co_gs_go2critical_hpr signal to DDRC is asserted if enabled in PCCFG.go2critical_en register. + * | | |Note that arurgent signal can be asserted anytime and as long as required which is independent of address handshaking (it is not associated with any particular command). + * | | |Programming Mode: Static + * |[14] |rd_port_pagematch_en|Read Page Match Enable Bit + * | | |If set to 1, enables the Page Match feature + * | | |If enabled, once a requesting port is granted, the port is continued to be granted if the following immediate commands are to the same memory page (same rank, same bank and same row). + * | | |See also related PCCFG.pagematch_limit register. + * | | |Programming Mode: Static + * |[16] |rdwr_ordered_en|Read/Writes Ordered Enable Bit + * | | |If set to 1, preserves the ordering between read transaction and write transaction issued to the same address, on a given port. + * | | |In other words, the controller ensures that all same address read and write commands from the application port interface are transported to the DFI interface in the order of acceptance. + * | | |This feature is useful in cases where software coherency is desired for masters issuing back-to-back read/write transactions without waiting for write/read responses. + * | | |Programming Mode: Static + * @var UMCTL2_T::PCFGW_1 + * Offset: 0x4B8 Port n Configuration Write Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[9:0] |wr_port_priority|Write Channel of Port Priority + * | | |Determines the initial load value of write aging counters. + * | | |These counters are parallel loaded after reset, or after each grant to the corresponding port. + * | | |The aging counters down-count every clock cycle where the port is requesting but not granted. + * | | |The higher significant 5-bits of the write aging counter sets the initial priority of the write channel of a given port. + * | | |Port's priority increases as the higher significant 5-bits of the counter starts to decrease + * | | |When the aging counter becomes 0, the corresponding port channel has the highest priority level. + * | | |For multi-port configurations, the aging counters cannot be used to set port priorities when external dynamic priority inputs (awqos) are enabled (timeout is still applicable). + * | | |For single port configurations, the aging counters are only used when they timeout (become 0) to force read-write direction switching. + * | | |Note: The two LSBs of this register field are tied internally to 2'b00. + * | | |Programming Mode: Static + * |[12] |wr_port_aging_en|Write Channel of Port Aging Function Enable Bit + * | | |If set to 1, enables aging function for the write channel of the port. + * | | |Programming Mode: Static + * |[13] |wr_port_urgent_en|AXI Urgent Sideband Signal (awurgent) Enable Bit + * | | |If set to 1, enables the AXI urgent sideband signal (awurgent). + * | | |When enabled and awurgent is asserted by the master, that port becomes the highest priority and co_gs_go2critical_wr signal to DDRC is asserted if enabled in PCCFG.go2critical_en register. + * | | |Note that awurgent signal can be asserted anytime and as long as required which is independent of address handshaking (it is not associated with any particular command). + * | | |Programming Mode: Static + * |[14] |wr_port_pagematch_en|Write Page Match Enable Bit + * | | |If set to 1, enables the Page Match feature. + * | | |If enabled, once a requesting port is granted, the port is continued to be granted if the following immediate commands are to the same memory page (same rank, same bank and same row). + * | | |See also related PCCFG.pagematch_limit register. + * | | |Programming Mode: Static + * @var UMCTL2_T::PCTRL_1 + * Offset: 0x540 Port n Control Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[0] |port_en |AXI Port n Enable Bit + * | | |Programming Mode: Dynamic + * @var UMCTL2_T::PCFGQOS0_1 + * Offset: 0x544 Port n Read QoS Configuration Register 0 + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[3:0] |rqos_map_level1|End of Region0 Mapping + * | | |Separation level1 indicating the end of region0 mapping; start of region0 is 0 + * | | |Possible values for level1 are 0 to 13 (for dual RAQ) or 0 to 14 (for single RAQ) which corresponds to arqos. + * | | |Note that for PA, arqos values are used directly as port priorities, where the higher the value corresponds to higher port priority. + * | | |All of the map_level* registers must be set to distinct values. + * | | |Programming Mode: Quasi-dynamic Group 3 + * |[17:16] |rqos_map_region0|Traffic Class of Region 0 + * | | |This bit field indicates the traffic class of region 0. + * | | |Valid values are: + * | | |u00B7 0 - LPR + * | | |u00B7 1 - VPR + * | | |u00B7 2 - HPR + * | | |For dual address queue configurations, region 0 maps to the blue address queue. + * | | |In this case, valid values are: + * | | |0: LPR and 1: VPR only. + * | | |When VPR support is disabled (UMCTL2_VPR_EN = 0) and traffic class of region0 is set to 1 (VPR), VPR traffic is aliased to LPR traffic. + * | | |Programming Mode: Quasi-dynamic Group 3 + * |[21:20] |rqos_map_region1|Traffic Class of Region 1 + * | | |This bit field indicates the traffic class of region 1. + * | | |Valid values are: + * | | |u00B7 0 - LPR + * | | |u00B7 1 - VPR + * | | |u00B7 2 - HPR + * | | |For dual address queue configurations, region1 maps to the blue address queue. + * | | |In this case, valid values are + * | | |u00B7 0 - LPR + * | | |u00B7 1 - VPR only + * | | |When VPR support is disabled (UMCTL2_VPR_EN = 0) and traffic class of region 1 is set to 1 (VPR), VPR traffic is aliased to LPR traffic. + * | | |Programming Mode: Quasi-dynamic Group 3 + * @var UMCTL2_T::PCFGR_2 + * Offset: 0x564 Port n Configuration Read Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[9:0] |rd_port_priority|Read Channel of Port Priority + * | | |Determines the initial load value of read aging counters. + * | | |These counters are parallel loaded after reset, or after each grant to the corresponding port. + * | | |The aging counters down-count every clock cycle where the port is requesting but not granted + * | | |The higher significant 5-bits of the read aging counter sets the priority of the read channel of a given port. + * | | |Port's priority increases as the higher significant 5-bits of the counter starts to decrease. + * | | |When the aging counter becomes 0, the corresponding port channel has the highest priority level (timeout condition - Priority0). + * | | |For multi-port configurations, the aging counters cannot be used to set port priorities when external dynamic priority inputs (arqos) are enabled (timeout is still applicable). + * | | |For single port configurations, the aging counters are only used when they timeout (become 0) to force read-write direction switching. + * | | |In this case, external dynamic priority input, arqos (for reads only) can still be used to set the DDRC read priority (2 priority levels: low priority read - LPR, high priority read - HPR) on a command by command basis. + * | | |Note: The two LSBs of this register field are tied internally to 2'b00. + * | | |Programming Mode: Static + * |[12] |rd_port_aging_en|Read Channel of Port Aging Function Enable Bit + * | | |If set to 1, enables aging function for the read channel of the port. + * | | |Programming Mode: Static + * |[13] |rd_port_urgent_en|AXI Urgent Sideband Signal (arurgent) Enable Bit + * | | |If set to 1, enables the AXI urgent sideband signal (arurgent) + * | | |When enabled and arurgent is asserted by the master, that port becomes the highest priority and co_gs_go2critical_lpr/co_gs_go2critical_hpr signal to DDRC is asserted if enabled in PCCFG.go2critical_en register. + * | | |Note that arurgent signal can be asserted anytime and as long as required which is independent of address handshaking (it is not associated with any particular command). + * | | |Programming Mode: Static + * |[14] |rd_port_pagematch_en|Read Page Match Enable Bit + * | | |If set to 1, enables the Page Match feature + * | | |If enabled, once a requesting port is granted, the port is continued to be granted if the following immediate commands are to the same memory page (same rank, same bank and same row). + * | | |See also related PCCFG.pagematch_limit register. + * | | |Programming Mode: Static + * |[16] |rdwr_ordered_en|Read/Writes Ordered Enable Bit + * | | |If set to 1, preserves the ordering between read transaction and write transaction issued to the same address, on a given port. + * | | |In other words, the controller ensures that all same address read and write commands from the application port interface are transported to the DFI interface in the order of acceptance. + * | | |This feature is useful in cases where software coherency is desired for masters issuing back-to-back read/write transactions without waiting for write/read responses. + * | | |Programming Mode: Static + * @var UMCTL2_T::PCFGW_2 + * Offset: 0x568 Port n Configuration Write Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[9:0] |wr_port_priority|Write Channel of Port Priority + * | | |Determines the initial load value of write aging counters. + * | | |These counters are parallel loaded after reset, or after each grant to the corresponding port. + * | | |The aging counters down-count every clock cycle where the port is requesting but not granted. + * | | |The higher significant 5-bits of the write aging counter sets the initial priority of the write channel of a given port. + * | | |Port's priority increases as the higher significant 5-bits of the counter starts to decrease + * | | |When the aging counter becomes 0, the corresponding port channel has the highest priority level. + * | | |For multi-port configurations, the aging counters cannot be used to set port priorities when external dynamic priority inputs (awqos) are enabled (timeout is still applicable). + * | | |For single port configurations, the aging counters are only used when they timeout (become 0) to force read-write direction switching. + * | | |Note: The two LSBs of this register field are tied internally to 2'b00. + * | | |Programming Mode: Static + * |[12] |wr_port_aging_en|Write Channel of Port Aging Function Enable Bit + * | | |If set to 1, enables aging function for the write channel of the port. + * | | |Programming Mode: Static + * |[13] |wr_port_urgent_en|AXI Urgent Sideband Signal (awurgent) Enable Bit + * | | |If set to 1, enables the AXI urgent sideband signal (awurgent). + * | | |When enabled and awurgent is asserted by the master, that port becomes the highest priority and co_gs_go2critical_wr signal to DDRC is asserted if enabled in PCCFG.go2critical_en register. + * | | |Note that awurgent signal can be asserted anytime and as long as required which is independent of address handshaking (it is not associated with any particular command). + * | | |Programming Mode: Static + * |[14] |wr_port_pagematch_en|Write Page Match Enable Bit + * | | |If set to 1, enables the Page Match feature. + * | | |If enabled, once a requesting port is granted, the port is continued to be granted if the following immediate commands are to the same memory page (same rank, same bank and same row). + * | | |See also related PCCFG.pagematch_limit register. + * | | |Programming Mode: Static + * @var UMCTL2_T::PCTRL_2 + * Offset: 0x5F0 Port n Control Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[0] |port_en |AXI Port n Enable Bit + * | | |Programming Mode: Dynamic + * @var UMCTL2_T::PCFGQOS0_2 + * Offset: 0x5F4 Port n Read QoS Configuration Register 0 + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[3:0] |rqos_map_level1|End of Region0 Mapping + * | | |Separation level1 indicating the end of region0 mapping; start of region0 is 0 + * | | |Possible values for level1 are 0 to 13 (for dual RAQ) or 0 to 14 (for single RAQ) which corresponds to arqos. + * | | |Note that for PA, arqos values are used directly as port priorities, where the higher the value corresponds to higher port priority. + * | | |All of the map_level* registers must be set to distinct values. + * | | |Programming Mode: Quasi-dynamic Group 3 + * |[17:16] |rqos_map_region0|Traffic Class of Region 0 + * | | |This bit field indicates the traffic class of region 0. + * | | |Valid values are: + * | | |u00B7 0 - LPR + * | | |u00B7 1 - VPR + * | | |u00B7 2 - HPR + * | | |For dual address queue configurations, region 0 maps to the blue address queue. + * | | |In this case, valid values are: + * | | |0: LPR and 1: VPR only. + * | | |When VPR support is disabled (UMCTL2_VPR_EN = 0) and traffic class of region0 is set to 1 (VPR), VPR traffic is aliased to LPR traffic. + * | | |Programming Mode: Quasi-dynamic Group 3 + * |[21:20] |rqos_map_region1|Traffic Class of Region 1 + * | | |This bit field indicates the traffic class of region 1. + * | | |Valid values are: + * | | |u00B7 0 - LPR + * | | |u00B7 1 - VPR + * | | |u00B7 2 - HPR + * | | |For dual address queue configurations, region1 maps to the blue address queue. + * | | |In this case, valid values are + * | | |u00B7 0 - LPR + * | | |u00B7 1 - VPR only + * | | |When VPR support is disabled (UMCTL2_VPR_EN = 0) and traffic class of region 1 is set to 1 (VPR), VPR traffic is aliased to LPR traffic. + * | | |Programming Mode: Quasi-dynamic Group 3 + * @var UMCTL2_T::PCFGR_3 + * Offset: 0x614 Port n Configuration Read Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[9:0] |rd_port_priority|Read Channel of Port Priority + * | | |Determines the initial load value of read aging counters. + * | | |These counters are parallel loaded after reset, or after each grant to the corresponding port. + * | | |The aging counters down-count every clock cycle where the port is requesting but not granted + * | | |The higher significant 5-bits of the read aging counter sets the priority of the read channel of a given port. + * | | |Port's priority increases as the higher significant 5-bits of the counter starts to decrease. + * | | |When the aging counter becomes 0, the corresponding port channel has the highest priority level (timeout condition - Priority0). + * | | |For multi-port configurations, the aging counters cannot be used to set port priorities when external dynamic priority inputs (arqos) are enabled (timeout is still applicable). + * | | |For single port configurations, the aging counters are only used when they timeout (become 0) to force read-write direction switching. + * | | |In this case, external dynamic priority input, arqos (for reads only) can still be used to set the DDRC read priority (2 priority levels: low priority read - LPR, high priority read - HPR) on a command by command basis. + * | | |Note: The two LSBs of this register field are tied internally to 2'b00. + * | | |Programming Mode: Static + * |[12] |rd_port_aging_en|Read Channel of Port Aging Function Enable Bit + * | | |If set to 1, enables aging function for the read channel of the port. + * | | |Programming Mode: Static + * |[13] |rd_port_urgent_en|AXI Urgent Sideband Signal (arurgent) Enable Bit + * | | |If set to 1, enables the AXI urgent sideband signal (arurgent) + * | | |When enabled and arurgent is asserted by the master, that port becomes the highest priority and co_gs_go2critical_lpr/co_gs_go2critical_hpr signal to DDRC is asserted if enabled in PCCFG.go2critical_en register. + * | | |Note that arurgent signal can be asserted anytime and as long as required which is independent of address handshaking (it is not associated with any particular command). + * | | |Programming Mode: Static + * |[14] |rd_port_pagematch_en|Read Page Match Enable Bit + * | | |If set to 1, enables the Page Match feature + * | | |If enabled, once a requesting port is granted, the port is continued to be granted if the following immediate commands are to the same memory page (same rank, same bank and same row). + * | | |See also related PCCFG.pagematch_limit register. + * | | |Programming Mode: Static + * |[16] |rdwr_ordered_en|Read/Writes Ordered Enable Bit + * | | |If set to 1, preserves the ordering between read transaction and write transaction issued to the same address, on a given port. + * | | |In other words, the controller ensures that all same address read and write commands from the application port interface are transported to the DFI interface in the order of acceptance. + * | | |This feature is useful in cases where software coherency is desired for masters issuing back-to-back read/write transactions without waiting for write/read responses. + * | | |Programming Mode: Static + * @var UMCTL2_T::PCFGW_3 + * Offset: 0x618 Port n Configuration Write Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[9:0] |wr_port_priority|Write Channel of Port Priority + * | | |Determines the initial load value of write aging counters. + * | | |These counters are parallel loaded after reset, or after each grant to the corresponding port. + * | | |The aging counters down-count every clock cycle where the port is requesting but not granted. + * | | |The higher significant 5-bits of the write aging counter sets the initial priority of the write channel of a given port. + * | | |Port's priority increases as the higher significant 5-bits of the counter starts to decrease + * | | |When the aging counter becomes 0, the corresponding port channel has the highest priority level. + * | | |For multi-port configurations, the aging counters cannot be used to set port priorities when external dynamic priority inputs (awqos) are enabled (timeout is still applicable). + * | | |For single port configurations, the aging counters are only used when they timeout (become 0) to force read-write direction switching. + * | | |Note: The two LSBs of this register field are tied internally to 2'b00. + * | | |Programming Mode: Static + * |[12] |wr_port_aging_en|Write Channel of Port Aging Function Enable Bit + * | | |If set to 1, enables aging function for the write channel of the port. + * | | |Programming Mode: Static + * |[13] |wr_port_urgent_en|AXI Urgent Sideband Signal (awurgent) Enable Bit + * | | |If set to 1, enables the AXI urgent sideband signal (awurgent). + * | | |When enabled and awurgent is asserted by the master, that port becomes the highest priority and co_gs_go2critical_wr signal to DDRC is asserted if enabled in PCCFG.go2critical_en register. + * | | |Note that awurgent signal can be asserted anytime and as long as required which is independent of address handshaking (it is not associated with any particular command). + * | | |Programming Mode: Static + * |[14] |wr_port_pagematch_en|Write Page Match Enable Bit + * | | |If set to 1, enables the Page Match feature. + * | | |If enabled, once a requesting port is granted, the port is continued to be granted if the following immediate commands are to the same memory page (same rank, same bank and same row). + * | | |See also related PCCFG.pagematch_limit register. + * | | |Programming Mode: Static + * @var UMCTL2_T::PCTRL_3 + * Offset: 0x6A0 Port n Control Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[0] |port_en |AXI Port n Enable Bit + * | | |Programming Mode: Dynamic + * @var UMCTL2_T::PCFGQOS0_3 + * Offset: 0x6A4 Port n Read QoS Configuration Register 0 + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[3:0] |rqos_map_level1|End of Region0 Mapping + * | | |Separation level1 indicating the end of region0 mapping; start of region0 is 0 + * | | |Possible values for level1 are 0 to 13 (for dual RAQ) or 0 to 14 (for single RAQ) which corresponds to arqos. + * | | |Note that for PA, arqos values are used directly as port priorities, where the higher the value corresponds to higher port priority. + * | | |All of the map_level* registers must be set to distinct values. + * | | |Programming Mode: Quasi-dynamic Group 3 + * |[17:16] |rqos_map_region0|Traffic Class of Region 0 + * | | |This bit field indicates the traffic class of region 0. + * | | |Valid values are: + * | | |u00B7 0 - LPR + * | | |u00B7 1 - VPR + * | | |u00B7 2 - HPR + * | | |For dual address queue configurations, region 0 maps to the blue address queue. + * | | |In this case, valid values are: + * | | |0: LPR and 1: VPR only. + * | | |When VPR support is disabled (UMCTL2_VPR_EN = 0) and traffic class of region0 is set to 1 (VPR), VPR traffic is aliased to LPR traffic. + * | | |Programming Mode: Quasi-dynamic Group 3 + * |[21:20] |rqos_map_region1|Traffic Class of Region 1 + * | | |This bit field indicates the traffic class of region 1. + * | | |Valid values are: + * | | |u00B7 0 - LPR + * | | |u00B7 1 - VPR + * | | |u00B7 2 - HPR + * | | |For dual address queue configurations, region1 maps to the blue address queue. + * | | |In this case, valid values are + * | | |u00B7 0 - LPR + * | | |u00B7 1 - VPR only + * | | |When VPR support is disabled (UMCTL2_VPR_EN = 0) and traffic class of region 1 is set to 1 (VPR), VPR traffic is aliased to LPR traffic. + * | | |Programming Mode: Quasi-dynamic Group 3 + * @var UMCTL2_T::PCFGR_4 + * Offset: 0x6C4 Port n Configuration Read Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[9:0] |rd_port_priority|Read Channel of Port Priority + * | | |Determines the initial load value of read aging counters. + * | | |These counters are parallel loaded after reset, or after each grant to the corresponding port. + * | | |The aging counters down-count every clock cycle where the port is requesting but not granted + * | | |The higher significant 5-bits of the read aging counter sets the priority of the read channel of a given port. + * | | |Port's priority increases as the higher significant 5-bits of the counter starts to decrease. + * | | |When the aging counter becomes 0, the corresponding port channel has the highest priority level (timeout condition - Priority0). + * | | |For multi-port configurations, the aging counters cannot be used to set port priorities when external dynamic priority inputs (arqos) are enabled (timeout is still applicable). + * | | |For single port configurations, the aging counters are only used when they timeout (become 0) to force read-write direction switching. + * | | |In this case, external dynamic priority input, arqos (for reads only) can still be used to set the DDRC read priority (2 priority levels: low priority read - LPR, high priority read - HPR) on a command by command basis. + * | | |Note: The two LSBs of this register field are tied internally to 2'b00. + * | | |Programming Mode: Static + * |[12] |rd_port_aging_en|Read Channel of Port Aging Function Enable Bit + * | | |If set to 1, enables aging function for the read channel of the port. + * | | |Programming Mode: Static + * |[13] |rd_port_urgent_en|AXI Urgent Sideband Signal (arurgent) Enable Bit + * | | |If set to 1, enables the AXI urgent sideband signal (arurgent) + * | | |When enabled and arurgent is asserted by the master, that port becomes the highest priority and co_gs_go2critical_lpr/co_gs_go2critical_hpr signal to DDRC is asserted if enabled in PCCFG.go2critical_en register. + * | | |Note that arurgent signal can be asserted anytime and as long as required which is independent of address handshaking (it is not associated with any particular command). + * | | |Programming Mode: Static + * |[14] |rd_port_pagematch_en|Read Page Match Enable Bit + * | | |If set to 1, enables the Page Match feature + * | | |If enabled, once a requesting port is granted, the port is continued to be granted if the following immediate commands are to the same memory page (same rank, same bank and same row). + * | | |See also related PCCFG.pagematch_limit register. + * | | |Programming Mode: Static + * |[16] |rdwr_ordered_en|Read/Writes Ordered Enable Bit + * | | |If set to 1, preserves the ordering between read transaction and write transaction issued to the same address, on a given port. + * | | |In other words, the controller ensures that all same address read and write commands from the application port interface are transported to the DFI interface in the order of acceptance. + * | | |This feature is useful in cases where software coherency is desired for masters issuing back-to-back read/write transactions without waiting for write/read responses. + * | | |Programming Mode: Static + * @var UMCTL2_T::PCFGW_4 + * Offset: 0x6C8 Port n Configuration Write Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[9:0] |wr_port_priority|Write Channel of Port Priority + * | | |Determines the initial load value of write aging counters. + * | | |These counters are parallel loaded after reset, or after each grant to the corresponding port. + * | | |The aging counters down-count every clock cycle where the port is requesting but not granted. + * | | |The higher significant 5-bits of the write aging counter sets the initial priority of the write channel of a given port. + * | | |Port's priority increases as the higher significant 5-bits of the counter starts to decrease + * | | |When the aging counter becomes 0, the corresponding port channel has the highest priority level. + * | | |For multi-port configurations, the aging counters cannot be used to set port priorities when external dynamic priority inputs (awqos) are enabled (timeout is still applicable). + * | | |For single port configurations, the aging counters are only used when they timeout (become 0) to force read-write direction switching. + * | | |Note: The two LSBs of this register field are tied internally to 2'b00. + * | | |Programming Mode: Static + * |[12] |wr_port_aging_en|Write Channel of Port Aging Function Enable Bit + * | | |If set to 1, enables aging function for the write channel of the port. + * | | |Programming Mode: Static + * |[13] |wr_port_urgent_en|AXI Urgent Sideband Signal (awurgent) Enable Bit + * | | |If set to 1, enables the AXI urgent sideband signal (awurgent). + * | | |When enabled and awurgent is asserted by the master, that port becomes the highest priority and co_gs_go2critical_wr signal to DDRC is asserted if enabled in PCCFG.go2critical_en register. + * | | |Note that awurgent signal can be asserted anytime and as long as required which is independent of address handshaking (it is not associated with any particular command). + * | | |Programming Mode: Static + * |[14] |wr_port_pagematch_en|Write Page Match Enable Bit + * | | |If set to 1, enables the Page Match feature. + * | | |If enabled, once a requesting port is granted, the port is continued to be granted if the following immediate commands are to the same memory page (same rank, same bank and same row). + * | | |See also related PCCFG.pagematch_limit register. + * | | |Programming Mode: Static + * @var UMCTL2_T::PCTRL_4 + * Offset: 0x750 Port n Control Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[0] |port_en |AXI Port n Enable Bit + * | | |Programming Mode: Dynamic + * @var UMCTL2_T::PCFGQOS0_4 + * Offset: 0x754 Port n Read QoS Configuration Register 0 + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[3:0] |rqos_map_level1|End of Region0 Mapping + * | | |Separation level1 indicating the end of region0 mapping; start of region0 is 0 + * | | |Possible values for level1 are 0 to 13 (for dual RAQ) or 0 to 14 (for single RAQ) which corresponds to arqos. + * | | |Note that for PA, arqos values are used directly as port priorities, where the higher the value corresponds to higher port priority. + * | | |All of the map_level* registers must be set to distinct values. + * | | |Programming Mode: Quasi-dynamic Group 3 + * |[17:16] |rqos_map_region0|Traffic Class of Region 0 + * | | |This bit field indicates the traffic class of region 0. + * | | |Valid values are: + * | | |u00B7 0 - LPR + * | | |u00B7 1 - VPR + * | | |u00B7 2 - HPR + * | | |For dual address queue configurations, region 0 maps to the blue address queue. + * | | |In this case, valid values are: + * | | |0: LPR and 1: VPR only. + * | | |When VPR support is disabled (UMCTL2_VPR_EN = 0) and traffic class of region0 is set to 1 (VPR), VPR traffic is aliased to LPR traffic. + * | | |Programming Mode: Quasi-dynamic Group 3 + * |[21:20] |rqos_map_region1|Traffic Class of Region 1 + * | | |This bit field indicates the traffic class of region 1. + * | | |Valid values are: + * | | |u00B7 0 - LPR + * | | |u00B7 1 - VPR + * | | |u00B7 2 - HPR + * | | |For dual address queue configurations, region1 maps to the blue address queue. + * | | |In this case, valid values are + * | | |u00B7 0 - LPR + * | | |u00B7 1 - VPR only + * | | |When VPR support is disabled (UMCTL2_VPR_EN = 0) and traffic class of region 1 is set to 1 (VPR), VPR traffic is aliased to LPR traffic. + * | | |Programming Mode: Quasi-dynamic Group 3 + * @var UMCTL2_T::PCFGR_5 + * Offset: 0x774 Port n Configuration Read Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[9:0] |rd_port_priority|Read Channel of Port Priority + * | | |Determines the initial load value of read aging counters. + * | | |These counters are parallel loaded after reset, or after each grant to the corresponding port. + * | | |The aging counters down-count every clock cycle where the port is requesting but not granted + * | | |The higher significant 5-bits of the read aging counter sets the priority of the read channel of a given port. + * | | |Port's priority increases as the higher significant 5-bits of the counter starts to decrease. + * | | |When the aging counter becomes 0, the corresponding port channel has the highest priority level (timeout condition - Priority0). + * | | |For multi-port configurations, the aging counters cannot be used to set port priorities when external dynamic priority inputs (arqos) are enabled (timeout is still applicable). + * | | |For single port configurations, the aging counters are only used when they timeout (become 0) to force read-write direction switching. + * | | |In this case, external dynamic priority input, arqos (for reads only) can still be used to set the DDRC read priority (2 priority levels: low priority read - LPR, high priority read - HPR) on a command by command basis. + * | | |Note: The two LSBs of this register field are tied internally to 2'b00. + * | | |Programming Mode: Static + * |[12] |rd_port_aging_en|Read Channel of Port Aging Function Enable Bit + * | | |If set to 1, enables aging function for the read channel of the port. + * | | |Programming Mode: Static + * |[13] |rd_port_urgent_en|AXI Urgent Sideband Signal (arurgent) Enable Bit + * | | |If set to 1, enables the AXI urgent sideband signal (arurgent) + * | | |When enabled and arurgent is asserted by the master, that port becomes the highest priority and co_gs_go2critical_lpr/co_gs_go2critical_hpr signal to DDRC is asserted if enabled in PCCFG.go2critical_en register. + * | | |Note that arurgent signal can be asserted anytime and as long as required which is independent of address handshaking (it is not associated with any particular command). + * | | |Programming Mode: Static + * |[14] |rd_port_pagematch_en|Read Page Match Enable Bit + * | | |If set to 1, enables the Page Match feature + * | | |If enabled, once a requesting port is granted, the port is continued to be granted if the following immediate commands are to the same memory page (same rank, same bank and same row). + * | | |See also related PCCFG.pagematch_limit register. + * | | |Programming Mode: Static + * |[16] |rdwr_ordered_en|Read/Writes Ordered Enable Bit + * | | |If set to 1, preserves the ordering between read transaction and write transaction issued to the same address, on a given port. + * | | |In other words, the controller ensures that all same address read and write commands from the application port interface are transported to the DFI interface in the order of acceptance. + * | | |This feature is useful in cases where software coherency is desired for masters issuing back-to-back read/write transactions without waiting for write/read responses. + * | | |Programming Mode: Static + * @var UMCTL2_T::PCFGW_5 + * Offset: 0x778 Port n Configuration Write Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[9:0] |wr_port_priority|Write Channel of Port Priority + * | | |Determines the initial load value of write aging counters. + * | | |These counters are parallel loaded after reset, or after each grant to the corresponding port. + * | | |The aging counters down-count every clock cycle where the port is requesting but not granted. + * | | |The higher significant 5-bits of the write aging counter sets the initial priority of the write channel of a given port. + * | | |Port's priority increases as the higher significant 5-bits of the counter starts to decrease + * | | |When the aging counter becomes 0, the corresponding port channel has the highest priority level. + * | | |For multi-port configurations, the aging counters cannot be used to set port priorities when external dynamic priority inputs (awqos) are enabled (timeout is still applicable). + * | | |For single port configurations, the aging counters are only used when they timeout (become 0) to force read-write direction switching. + * | | |Note: The two LSBs of this register field are tied internally to 2'b00. + * | | |Programming Mode: Static + * |[12] |wr_port_aging_en|Write Channel of Port Aging Function Enable Bit + * | | |If set to 1, enables aging function for the write channel of the port. + * | | |Programming Mode: Static + * |[13] |wr_port_urgent_en|AXI Urgent Sideband Signal (awurgent) Enable Bit + * | | |If set to 1, enables the AXI urgent sideband signal (awurgent). + * | | |When enabled and awurgent is asserted by the master, that port becomes the highest priority and co_gs_go2critical_wr signal to DDRC is asserted if enabled in PCCFG.go2critical_en register. + * | | |Note that awurgent signal can be asserted anytime and as long as required which is independent of address handshaking (it is not associated with any particular command). + * | | |Programming Mode: Static + * |[14] |wr_port_pagematch_en|Write Page Match Enable Bit + * | | |If set to 1, enables the Page Match feature. + * | | |If enabled, once a requesting port is granted, the port is continued to be granted if the following immediate commands are to the same memory page (same rank, same bank and same row). + * | | |See also related PCCFG.pagematch_limit register. + * | | |Programming Mode: Static + * @var UMCTL2_T::PCTRL_5 + * Offset: 0x800 Port n Control Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[0] |port_en |AXI Port n Enable Bit + * | | |Programming Mode: Dynamic + * @var UMCTL2_T::PCFGQOS0_5 + * Offset: 0x804 Port n Read QoS Configuration Register 0 + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[3:0] |rqos_map_level1|End of Region0 Mapping + * | | |Separation level1 indicating the end of region0 mapping; start of region0 is 0 + * | | |Possible values for level1 are 0 to 13 (for dual RAQ) or 0 to 14 (for single RAQ) which corresponds to arqos. + * | | |Note that for PA, arqos values are used directly as port priorities, where the higher the value corresponds to higher port priority. + * | | |All of the map_level* registers must be set to distinct values. + * | | |Programming Mode: Quasi-dynamic Group 3 + * |[17:16] |rqos_map_region0|Traffic Class of Region 0 + * | | |This bit field indicates the traffic class of region 0. + * | | |Valid values are: + * | | |u00B7 0 - LPR + * | | |u00B7 1 - VPR + * | | |u00B7 2 - HPR + * | | |For dual address queue configurations, region 0 maps to the blue address queue. + * | | |In this case, valid values are: + * | | |0: LPR and 1: VPR only. + * | | |When VPR support is disabled (UMCTL2_VPR_EN = 0) and traffic class of region0 is set to 1 (VPR), VPR traffic is aliased to LPR traffic. + * | | |Programming Mode: Quasi-dynamic Group 3 + * |[21:20] |rqos_map_region1|Traffic Class of Region 1 + * | | |This bit field indicates the traffic class of region 1. + * | | |Valid values are: + * | | |u00B7 0 - LPR + * | | |u00B7 1 - VPR + * | | |u00B7 2 - HPR + * | | |For dual address queue configurations, region1 maps to the blue address queue. + * | | |In this case, valid values are + * | | |u00B7 0 - LPR + * | | |u00B7 1 - VPR only + * | | |When VPR support is disabled (UMCTL2_VPR_EN = 0) and traffic class of region 1 is set to 1 (VPR), VPR traffic is aliased to LPR traffic. + * | | |Programming Mode: Quasi-dynamic Group 3 + * @var UMCTL2_T::PCFGR_6 + * Offset: 0x824 Port n Configuration Read Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[9:0] |rd_port_priority|Read Channel of Port Priority + * | | |Determines the initial load value of read aging counters. + * | | |These counters are parallel loaded after reset, or after each grant to the corresponding port. + * | | |The aging counters down-count every clock cycle where the port is requesting but not granted + * | | |The higher significant 5-bits of the read aging counter sets the priority of the read channel of a given port. + * | | |Port's priority increases as the higher significant 5-bits of the counter starts to decrease. + * | | |When the aging counter becomes 0, the corresponding port channel has the highest priority level (timeout condition - Priority0). + * | | |For multi-port configurations, the aging counters cannot be used to set port priorities when external dynamic priority inputs (arqos) are enabled (timeout is still applicable). + * | | |For single port configurations, the aging counters are only used when they timeout (become 0) to force read-write direction switching. + * | | |In this case, external dynamic priority input, arqos (for reads only) can still be used to set the DDRC read priority (2 priority levels: low priority read - LPR, high priority read - HPR) on a command by command basis. + * | | |Note: The two LSBs of this register field are tied internally to 2'b00. + * | | |Programming Mode: Static + * |[12] |rd_port_aging_en|Read Channel of Port Aging Function Enable Bit + * | | |If set to 1, enables aging function for the read channel of the port. + * | | |Programming Mode: Static + * |[13] |rd_port_urgent_en|AXI Urgent Sideband Signal (arurgent) Enable Bit + * | | |If set to 1, enables the AXI urgent sideband signal (arurgent) + * | | |When enabled and arurgent is asserted by the master, that port becomes the highest priority and co_gs_go2critical_lpr/co_gs_go2critical_hpr signal to DDRC is asserted if enabled in PCCFG.go2critical_en register. + * | | |Note that arurgent signal can be asserted anytime and as long as required which is independent of address handshaking (it is not associated with any particular command). + * | | |Programming Mode: Static + * |[14] |rd_port_pagematch_en|Read Page Match Enable Bit + * | | |If set to 1, enables the Page Match feature + * | | |If enabled, once a requesting port is granted, the port is continued to be granted if the following immediate commands are to the same memory page (same rank, same bank and same row). + * | | |See also related PCCFG.pagematch_limit register. + * | | |Programming Mode: Static + * |[16] |rdwr_ordered_en|Read/Writes Ordered Enable Bit + * | | |If set to 1, preserves the ordering between read transaction and write transaction issued to the same address, on a given port. + * | | |In other words, the controller ensures that all same address read and write commands from the application port interface are transported to the DFI interface in the order of acceptance. + * | | |This feature is useful in cases where software coherency is desired for masters issuing back-to-back read/write transactions without waiting for write/read responses. + * | | |Programming Mode: Static + * @var UMCTL2_T::PCFGW_6 + * Offset: 0x828 Port n Configuration Write Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[9:0] |wr_port_priority|Write Channel of Port Priority + * | | |Determines the initial load value of write aging counters. + * | | |These counters are parallel loaded after reset, or after each grant to the corresponding port. + * | | |The aging counters down-count every clock cycle where the port is requesting but not granted. + * | | |The higher significant 5-bits of the write aging counter sets the initial priority of the write channel of a given port. + * | | |Port's priority increases as the higher significant 5-bits of the counter starts to decrease + * | | |When the aging counter becomes 0, the corresponding port channel has the highest priority level. + * | | |For multi-port configurations, the aging counters cannot be used to set port priorities when external dynamic priority inputs (awqos) are enabled (timeout is still applicable). + * | | |For single port configurations, the aging counters are only used when they timeout (become 0) to force read-write direction switching. + * | | |Note: The two LSBs of this register field are tied internally to 2'b00. + * | | |Programming Mode: Static + * |[12] |wr_port_aging_en|Write Channel of Port Aging Function Enable Bit + * | | |If set to 1, enables aging function for the write channel of the port. + * | | |Programming Mode: Static + * |[13] |wr_port_urgent_en|AXI Urgent Sideband Signal (awurgent) Enable Bit + * | | |If set to 1, enables the AXI urgent sideband signal (awurgent). + * | | |When enabled and awurgent is asserted by the master, that port becomes the highest priority and co_gs_go2critical_wr signal to DDRC is asserted if enabled in PCCFG.go2critical_en register. + * | | |Note that awurgent signal can be asserted anytime and as long as required which is independent of address handshaking (it is not associated with any particular command). + * | | |Programming Mode: Static + * |[14] |wr_port_pagematch_en|Write Page Match Enable Bit + * | | |If set to 1, enables the Page Match feature. + * | | |If enabled, once a requesting port is granted, the port is continued to be granted if the following immediate commands are to the same memory page (same rank, same bank and same row). + * | | |See also related PCCFG.pagematch_limit register. + * | | |Programming Mode: Static + * @var UMCTL2_T::PCTRL_6 + * Offset: 0x8B0 Port n Control Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[0] |port_en |AXI Port n Enable Bit + * | | |Programming Mode: Dynamic + * @var UMCTL2_T::PCFGQOS0_6 + * Offset: 0x8B4 Port n Read QoS Configuration Register 0 + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[3:0] |rqos_map_level1|End of Region0 Mapping + * | | |Separation level1 indicating the end of region0 mapping; start of region0 is 0 + * | | |Possible values for level1 are 0 to 13 (for dual RAQ) or 0 to 14 (for single RAQ) which corresponds to arqos. + * | | |Note that for PA, arqos values are used directly as port priorities, where the higher the value corresponds to higher port priority. + * | | |All of the map_level* registers must be set to distinct values. + * | | |Programming Mode: Quasi-dynamic Group 3 + * |[17:16] |rqos_map_region0|Traffic Class of Region 0 + * | | |This bit field indicates the traffic class of region 0. + * | | |Valid values are: + * | | |u00B7 0 - LPR + * | | |u00B7 1 - VPR + * | | |u00B7 2 - HPR + * | | |For dual address queue configurations, region 0 maps to the blue address queue. + * | | |In this case, valid values are: + * | | |0: LPR and 1: VPR only. + * | | |When VPR support is disabled (UMCTL2_VPR_EN = 0) and traffic class of region0 is set to 1 (VPR), VPR traffic is aliased to LPR traffic. + * | | |Programming Mode: Quasi-dynamic Group 3 + * |[21:20] |rqos_map_region1|Traffic Class of Region 1 + * | | |This bit field indicates the traffic class of region 1. + * | | |Valid values are: + * | | |u00B7 0 - LPR + * | | |u00B7 1 - VPR + * | | |u00B7 2 - HPR + * | | |For dual address queue configurations, region1 maps to the blue address queue. + * | | |In this case, valid values are + * | | |u00B7 0 - LPR + * | | |u00B7 1 - VPR only + * | | |When VPR support is disabled (UMCTL2_VPR_EN = 0) and traffic class of region 1 is set to 1 (VPR), VPR traffic is aliased to LPR traffic. + * | | |Programming Mode: Quasi-dynamic Group 3 + * @var UMCTL2_T::PCFGR_7 + * Offset: 0x8D4 Port n Configuration Read Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[9:0] |rd_port_priority|Read Channel of Port Priority + * | | |Determines the initial load value of read aging counters. + * | | |These counters are parallel loaded after reset, or after each grant to the corresponding port. + * | | |The aging counters down-count every clock cycle where the port is requesting but not granted + * | | |The higher significant 5-bits of the read aging counter sets the priority of the read channel of a given port. + * | | |Port's priority increases as the higher significant 5-bits of the counter starts to decrease. + * | | |When the aging counter becomes 0, the corresponding port channel has the highest priority level (timeout condition - Priority0). + * | | |For multi-port configurations, the aging counters cannot be used to set port priorities when external dynamic priority inputs (arqos) are enabled (timeout is still applicable). + * | | |For single port configurations, the aging counters are only used when they timeout (become 0) to force read-write direction switching. + * | | |In this case, external dynamic priority input, arqos (for reads only) can still be used to set the DDRC read priority (2 priority levels: low priority read - LPR, high priority read - HPR) on a command by command basis. + * | | |Note: The two LSBs of this register field are tied internally to 2'b00. + * | | |Programming Mode: Static + * |[12] |rd_port_aging_en|Read Channel of Port Aging Function Enable Bit + * | | |If set to 1, enables aging function for the read channel of the port. + * | | |Programming Mode: Static + * |[13] |rd_port_urgent_en|AXI Urgent Sideband Signal (arurgent) Enable Bit + * | | |If set to 1, enables the AXI urgent sideband signal (arurgent) + * | | |When enabled and arurgent is asserted by the master, that port becomes the highest priority and co_gs_go2critical_lpr/co_gs_go2critical_hpr signal to DDRC is asserted if enabled in PCCFG.go2critical_en register. + * | | |Note that arurgent signal can be asserted anytime and as long as required which is independent of address handshaking (it is not associated with any particular command). + * | | |Programming Mode: Static + * |[14] |rd_port_pagematch_en|Read Page Match Enable Bit + * | | |If set to 1, enables the Page Match feature + * | | |If enabled, once a requesting port is granted, the port is continued to be granted if the following immediate commands are to the same memory page (same rank, same bank and same row). + * | | |See also related PCCFG.pagematch_limit register. + * | | |Programming Mode: Static + * |[16] |rdwr_ordered_en|Read/Writes Ordered Enable Bit + * | | |If set to 1, preserves the ordering between read transaction and write transaction issued to the same address, on a given port. + * | | |In other words, the controller ensures that all same address read and write commands from the application port interface are transported to the DFI interface in the order of acceptance. + * | | |This feature is useful in cases where software coherency is desired for masters issuing back-to-back read/write transactions without waiting for write/read responses. + * | | |Programming Mode: Static + * @var UMCTL2_T::PCFGW_7 + * Offset: 0x8D8 Port n Configuration Write Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[9:0] |wr_port_priority|Write Channel of Port Priority + * | | |Determines the initial load value of write aging counters. + * | | |These counters are parallel loaded after reset, or after each grant to the corresponding port. + * | | |The aging counters down-count every clock cycle where the port is requesting but not granted. + * | | |The higher significant 5-bits of the write aging counter sets the initial priority of the write channel of a given port. + * | | |Port's priority increases as the higher significant 5-bits of the counter starts to decrease + * | | |When the aging counter becomes 0, the corresponding port channel has the highest priority level. + * | | |For multi-port configurations, the aging counters cannot be used to set port priorities when external dynamic priority inputs (awqos) are enabled (timeout is still applicable). + * | | |For single port configurations, the aging counters are only used when they timeout (become 0) to force read-write direction switching. + * | | |Note: The two LSBs of this register field are tied internally to 2'b00. + * | | |Programming Mode: Static + * |[12] |wr_port_aging_en|Write Channel of Port Aging Function Enable Bit + * | | |If set to 1, enables aging function for the write channel of the port. + * | | |Programming Mode: Static + * |[13] |wr_port_urgent_en|AXI Urgent Sideband Signal (awurgent) Enable Bit + * | | |If set to 1, enables the AXI urgent sideband signal (awurgent). + * | | |When enabled and awurgent is asserted by the master, that port becomes the highest priority and co_gs_go2critical_wr signal to DDRC is asserted if enabled in PCCFG.go2critical_en register. + * | | |Note that awurgent signal can be asserted anytime and as long as required which is independent of address handshaking (it is not associated with any particular command). + * | | |Programming Mode: Static + * |[14] |wr_port_pagematch_en|Write Page Match Enable Bit + * | | |If set to 1, enables the Page Match feature. + * | | |If enabled, once a requesting port is granted, the port is continued to be granted if the following immediate commands are to the same memory page (same rank, same bank and same row). + * | | |See also related PCCFG.pagematch_limit register. + * | | |Programming Mode: Static + * @var UMCTL2_T::PCTRL_7 + * Offset: 0x960 Port n Control Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[0] |port_en |AXI Port n Enable Bit + * | | |Programming Mode: Dynamic + * @var UMCTL2_T::PCFGQOS0_7 + * Offset: 0x964 Port n Read QoS Configuration Register 0 + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[3:0] |rqos_map_level1|End of Region0 Mapping + * | | |Separation level1 indicating the end of region0 mapping; start of region0 is 0 + * | | |Possible values for level1 are 0 to 13 (for dual RAQ) or 0 to 14 (for single RAQ) which corresponds to arqos. + * | | |Note that for PA, arqos values are used directly as port priorities, where the higher the value corresponds to higher port priority. + * | | |All of the map_level* registers must be set to distinct values. + * | | |Programming Mode: Quasi-dynamic Group 3 + * |[17:16] |rqos_map_region0|Traffic Class of Region 0 + * | | |This bit field indicates the traffic class of region 0. + * | | |Valid values are: + * | | |u00B7 0 - LPR + * | | |u00B7 1 - VPR + * | | |u00B7 2 - HPR + * | | |For dual address queue configurations, region 0 maps to the blue address queue. + * | | |In this case, valid values are: + * | | |0: LPR and 1: VPR only. + * | | |When VPR support is disabled (UMCTL2_VPR_EN = 0) and traffic class of region0 is set to 1 (VPR), VPR traffic is aliased to LPR traffic. + * | | |Programming Mode: Quasi-dynamic Group 3 + * |[21:20] |rqos_map_region1|Traffic Class of Region 1 + * | | |This bit field indicates the traffic class of region 1. + * | | |Valid values are: + * | | |u00B7 0 - LPR + * | | |u00B7 1 - VPR + * | | |u00B7 2 - HPR + * | | |For dual address queue configurations, region1 maps to the blue address queue. + * | | |In this case, valid values are + * | | |u00B7 0 - LPR + * | | |u00B7 1 - VPR only + * | | |When VPR support is disabled (UMCTL2_VPR_EN = 0) and traffic class of region 1 is set to 1 (VPR), VPR traffic is aliased to LPR traffic. + * | | |Programming Mode: Quasi-dynamic Group 3 + * @var UMCTL2_T::SARBASE0 + * Offset: 0xF04 SAR Base Address Register n + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[1:0] |base_addr |Base Address for Address Region n + * | | |Base address for address region n specified as awaddr[UMCTL2_A_ADDRW-1:x] and araddr[UMCTL2_A_ADDRW-1:x], + * | | |where x is determined by the minimum block size parameter UMCTL2_SARMINSIZE: (x=log2(block size)). + * | | |Programming Mode: Static + * @var UMCTL2_T::SARSIZE0 + * Offset: 0xF08 SAR Size Register n + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[7:0] |nblocks |Number of Blocks for Address Region n. + * | | |This register determines the total size of the region in multiples of minimum block size as specified by the hardware parameter UMCTL2_SARMINSIZE + * | | |The register value is encoded as number of blocks = nblocks + 1 + * | | |For example, if register is programmed to 0, region can have 1 block. + * | | |Programming Mode: Static + * @var UMCTL2_T::VER_NUMBER + * Offset: 0xFF0 UMCTL2 Version Number Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[31:0] |ver_number|Device Version Number Value + * | | |This is in ASCII format, with each byte corresponding to a character of the version number + * | | |Programming Mode: Static + * @var UMCTL2_T::VER_TYPE + * Offset: 0xFF4 UMCTL2 Version Type Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[31:0] |ver_type |Device Version Type Value + * | | |This is in ASCII format, with each byte corresponding to a character of the version type + * | | |Programming Mode: Static + */ + __IO uint32_t MSTR; /*!< [0x0000] Master Register0 */ + __I uint32_t STAT; /*!< [0x0004] Operating Mode Status Register */ + __I uint32_t RESERVE0[2]; + __IO uint32_t MRCTRL0; /*!< [0x0010] Mode Register Read/Write Control Register 0 */ + __IO uint32_t MRCTRL1; /*!< [0x0014] Mode Register Read/Write Control Register 1 */ + __I uint32_t MRSTAT; /*!< [0x0018] Mode Register Read/Write Status Register */ + __I uint32_t RESERVE1[5]; + __IO uint32_t PWRCTL; /*!< [0x0030] Low Power Control Register */ + __IO uint32_t PWRTMG; /*!< [0x0034] Low Power Timing Register */ + __IO uint32_t HWLPCTL; /*!< [0x0038] Hardware Low Power Control Register */ + __I uint32_t RESERVE2[5]; + __IO uint32_t RFSHCTL0; /*!< [0x0050] Refresh Control Register 0 */ + __IO uint32_t RFSHCTL1; /*!< [0x0054] Refresh Control Register 1 */ + __I uint32_t RESERVE3[2]; + __IO uint32_t RFSHCTL3; /*!< [0x0060] Refresh Control Register 3 */ + __IO uint32_t RFSHTMG; /*!< [0x0064] Refresh Timing Register */ + __I uint32_t RESERVE4[22]; + __IO uint32_t CRCPARCTL0; /*!< [0x00c0] CRC Parity Control Register0 */ + __I uint32_t RESERVE5[2]; + __I uint32_t CRCPARSTAT; /*!< [0x00cc] CRC Parity Status Register */ + __IO uint32_t INIT0; /*!< [0x00d0] SDRAM Initialization Register 0 */ + __IO uint32_t INIT1; /*!< [0x00d4] SDRAM Initialization Register 1 */ + __I uint32_t RESERVE6[1]; + __IO uint32_t INIT3; /*!< [0x00dc] SDRAM Initialization Register 3 */ + __IO uint32_t INIT4; /*!< [0x00e0] SDRAM Initialization Register 4 */ + __IO uint32_t INIT5; /*!< [0x00e4] SDRAM Initialization Register 5 */ + __I uint32_t RESERVE7[2]; + __IO uint32_t DIMMCTL; /*!< [0x00f0] DIMM Control Register */ + __IO uint32_t RANKCTL; /*!< [0x00f4] Rank Control Register */ + __I uint32_t RESERVE8[2]; + __IO uint32_t DRAMTMG0; /*!< [0x0100] SDRAM Timing Register 0 */ + __IO uint32_t DRAMTMG1; /*!< [0x0104] SDRAM Timing Register 1 */ + __IO uint32_t DRAMTMG2; /*!< [0x0108] SDRAM Timing Register 2 */ + __IO uint32_t DRAMTMG3; /*!< [0x010c] SDRAM Timing Register 3 */ + __IO uint32_t DRAMTMG4; /*!< [0x0110] SDRAM Timing Register 4 */ + __IO uint32_t DRAMTMG5; /*!< [0x0114] SDRAM Timing Register 5 */ + __I uint32_t RESERVE9[2]; + __IO uint32_t DRAMTMG8; /*!< [0x0120] SDRAM Timing Register 8 */ + __I uint32_t RESERVE10[6]; + __IO uint32_t DRAMTMG15; /*!< [0x013c] SDRAM Timing Register 15 */ + __I uint32_t RESERVE11[16]; + __IO uint32_t ZQCTL0; /*!< [0x0180] ZQ Control Register 0 */ + __IO uint32_t ZQCTL1; /*!< [0x0184] ZQ Control Register 1 */ + __I uint32_t RESERVE12[2]; + __IO uint32_t DFITMG0; /*!< [0x0190] DFI Timing Register 0 */ + __IO uint32_t DFITMG1; /*!< [0x0194] DFI Timing Register 1 */ + __IO uint32_t DFILPCFG0; /*!< [0x0198] DFI Low Power Configuration Register 0 */ + __I uint32_t RESERVE13[1]; + __IO uint32_t DFIUPD0; /*!< [0x01a0] DFI Update Register 0 */ + __IO uint32_t DFIUPD1; /*!< [0x01a4] DFI Update Register 1 */ + __IO uint32_t DFIUPD2; /*!< [0x01a8] DFI Update Register 2 */ + __I uint32_t RESERVE14[1]; + __IO uint32_t DFIMISC; /*!< [0x01b0] DFI Miscellaneous Control Register */ + __I uint32_t RESERVE15[2]; + __I uint32_t DFISTAT; /*!< [0x01bc] DFI Status Register */ + __I uint32_t RESERVE16[1]; + __IO uint32_t DFIPHYMSTR; /*!< [0x01c4] DFI PHY Master */ + __I uint32_t RESERVE17[14]; + __IO uint32_t ADDRMAP0; /*!< [0x0200] Address Map Register 0 */ + __IO uint32_t ADDRMAP1; /*!< [0x0204] Address Map Register 1 */ + __IO uint32_t ADDRMAP2; /*!< [0x0208] Address Map Register 2 */ + __IO uint32_t ADDRMAP3; /*!< [0x020c] Address Map Register 3 */ + __IO uint32_t ADDRMAP4; /*!< [0x0210] Address Map Register 4 */ + __IO uint32_t ADDRMAP5; /*!< [0x0214] Address Map Register 5 */ + __IO uint32_t ADDRMAP6; /*!< [0x0218] Address Map Register 6 */ + __I uint32_t RESERVE18[2]; + __IO uint32_t ADDRMAP9; /*!< [0x0224] Address Map Register 9 */ + __IO uint32_t ADDRMAP10; /*!< [0x0228] Address Map Register 10 */ + __IO uint32_t ADDRMAP11; /*!< [0x022c] Address Map Register 11 */ + __I uint32_t RESERVE19[4]; + __IO uint32_t ODTCFG; /*!< [0x0240] ODT Configuration Register */ + __IO uint32_t ODTMAP; /*!< [0x0244] ODT/Rank Map Register */ + __I uint32_t RESERVE20[2]; + __IO uint32_t SCHED; /*!< [0x0250] Scheduler Control Register */ + __IO uint32_t SCHED1; /*!< [0x0254] Scheduler Control Register 1 */ + __I uint32_t RESERVE21[1]; + __IO uint32_t PERFHPR1; /*!< [0x025c] High Priority Read CAM Register 1 */ + __I uint32_t RESERVE22[1]; + __IO uint32_t PERFLPR1; /*!< [0x0264] Low Priority Read CAM Register 1 */ + __I uint32_t RESERVE23[1]; + __IO uint32_t PERFWR1; /*!< [0x026c] Write CAM Register 1 */ + __I uint32_t RESERVE24[36]; + __IO uint32_t DBG0; /*!< [0x0300] Debug Register 0 */ + __IO uint32_t DBG1; /*!< [0x0304] Debug Register 1 */ + __I uint32_t DBGCAM; /*!< [0x0308] CAM Debug Register */ + __IO uint32_t DBGCMD; /*!< [0x030c] Command Debug Register */ + __I uint32_t DBGSTAT; /*!< [0x0310] Status Debug Register */ + __I uint32_t RESERVE25[3]; + __IO uint32_t SWCTL; /*!< [0x0320] Software Register Programming Control Enable */ + __I uint32_t SWSTAT; /*!< [0x0324] Software Register Programming Control Status */ + __IO uint32_t SWCTLSTATIC; /*!< [0x0328] Static Registers Write Enable */ + __I uint32_t RESERVE26[16]; + __IO uint32_t POISONCFG; /*!< [0x036c] AXI Poison Configuration Register. Common for all AXI ports. */ + __I uint32_t POISONSTAT; /*!< [0x0370] AXI Poison Status Register */ + __I uint32_t RESERVE27[34]; + __I uint32_t PSTAT; /*!< [0x03fc] Port Status Register */ + __IO uint32_t PCCFG; /*!< [0x0400] Port Common Configuration Register */ + __IO uint32_t PCFGR_0; /*!< [0x0404] Port n Configuration Read Register */ + __IO uint32_t PCFGW_0; /*!< [0x0408] Port n Configuration Write Register */ + __I uint32_t RESERVE28[33]; + __IO uint32_t PCTRL_0; /*!< [0x0490] Port n Control Register */ + __IO uint32_t PCFGQOS0_0; /*!< [0x0494] Port n Read QoS Configuration Register 0 */ + __I uint32_t RESERVE29[7]; + __IO uint32_t PCFGR_1; /*!< [0x04b4] Port n Configuration Read Register */ + __IO uint32_t PCFGW_1; /*!< [0x04b8] Port n Configuration Write Register */ + __I uint32_t RESERVE30[33]; + __IO uint32_t PCTRL_1; /*!< [0x0540] Port n Control Register */ + __IO uint32_t PCFGQOS0_1; /*!< [0x0544] Port n Read QoS Configuration Register 0 */ + __I uint32_t RESERVE31[7]; + __IO uint32_t PCFGR_2; /*!< [0x0564] Port n Configuration Read Register */ + __IO uint32_t PCFGW_2; /*!< [0x0568] Port n Configuration Write Register */ + __I uint32_t RESERVE32[33]; + __IO uint32_t PCTRL_2; /*!< [0x05f0] Port n Control Register */ + __IO uint32_t PCFGQOS0_2; /*!< [0x05f4] Port n Read QoS Configuration Register 0 */ + __I uint32_t RESERVE33[7]; + __IO uint32_t PCFGR_3; /*!< [0x0614] Port n Configuration Read Register */ + __IO uint32_t PCFGW_3; /*!< [0x0618] Port n Configuration Write Register */ + __I uint32_t RESERVE34[33]; + __IO uint32_t PCTRL_3; /*!< [0x06a0] Port n Control Register */ + __IO uint32_t PCFGQOS0_3; /*!< [0x06a4] Port n Read QoS Configuration Register 0 */ + __I uint32_t RESERVE35[7]; + __IO uint32_t PCFGR_4; /*!< [0x06c4] Port n Configuration Read Register */ + __IO uint32_t PCFGW_4; /*!< [0x06c8] Port n Configuration Write Register */ + __I uint32_t RESERVE36[33]; + __IO uint32_t PCTRL_4; /*!< [0x0750] Port n Control Register */ + __IO uint32_t PCFGQOS0_4; /*!< [0x0754] Port n Read QoS Configuration Register 0 */ + __I uint32_t RESERVE37[7]; + __IO uint32_t PCFGR_5; /*!< [0x0774] Port n Configuration Read Register */ + __IO uint32_t PCFGW_5; /*!< [0x0778] Port n Configuration Write Register */ + __I uint32_t RESERVE38[33]; + __IO uint32_t PCTRL_5; /*!< [0x0800] Port n Control Register */ + __IO uint32_t PCFGQOS0_5; /*!< [0x0804] Port n Read QoS Configuration Register 0 */ + __I uint32_t RESERVE39[7]; + __IO uint32_t PCFGR_6; /*!< [0x0824] Port n Configuration Read Register */ + __IO uint32_t PCFGW_6; /*!< [0x0828] Port n Configuration Write Register */ + __I uint32_t RESERVE40[33]; + __IO uint32_t PCTRL_6; /*!< [0x08b0] Port n Control Register */ + __IO uint32_t PCFGQOS0_6; /*!< [0x08b4] Port n Read QoS Configuration Register 0 */ + __I uint32_t RESERVE41[7]; + __IO uint32_t PCFGR_7; /*!< [0x08d4] Port n Configuration Read Register */ + __IO uint32_t PCFGW_7; /*!< [0x08d8] Port n Configuration Write Register */ + __I uint32_t RESERVE42[33]; + __IO uint32_t PCTRL_7; /*!< [0x0960] Port n Control Register */ + __IO uint32_t PCFGQOS0_7; /*!< [0x0964] Port n Read QoS Configuration Register 0 */ + __I uint32_t RESERVE43[359]; + __IO uint32_t SARBASE0; /*!< [0x0f04] SAR Base Address Register n */ + __IO uint32_t SARSIZE0; /*!< [0x0f08] SAR Size Register n */ + __I uint32_t RESERVE44[57]; + __I uint32_t VER_NUMBER; /*!< [0x0ff0] UMCTL2 Version Number Register */ + __I uint32_t VER_TYPE; /*!< [0x0ff4] UMCTL2 Version Type Register */ + +} UMCTL2_T; + +/** + @addtogroup UMCTL2_CONST UMCTL2 Bit Field Definition + Constant Definitions for UMCTL2 Controller +@{ */ + +#define UMCTL2_MSTR_ddr3_Pos (0) /*!< UMCTL2_T::MSTR: ddr3 Position */ +#define UMCTL2_MSTR_ddr3_Msk (0x1ul << UMCTL2_MSTR_ddr3_Pos) /*!< UMCTL2_T::MSTR: ddr3 Mask */ + +#define UMCTL2_MSTR_burstchop_Pos (9) /*!< UMCTL2_T::MSTR: burstchop Position */ +#define UMCTL2_MSTR_burstchop_Msk (0x1ul << UMCTL2_MSTR_burstchop_Pos) /*!< UMCTL2_T::MSTR: burstchop Mask */ + +#define UMCTL2_MSTR_en_2t_timing_mode_Pos (10) /*!< UMCTL2_T::MSTR: en_2t_timing_mode Position*/ +#define UMCTL2_MSTR_en_2t_timing_mode_Msk (0x1ul << UMCTL2_MSTR_en_2t_timing_mode_Pos) /*!< UMCTL2_T::MSTR: en_2t_timing_mode Mask */ + +#define UMCTL2_MSTR_data_bus_width_Pos (12) /*!< UMCTL2_T::MSTR: data_bus_width Position*/ +#define UMCTL2_MSTR_data_bus_width_Msk (0x3ul << UMCTL2_MSTR_data_bus_width_Pos) /*!< UMCTL2_T::MSTR: data_bus_width Mask */ + +#define UMCTL2_MSTR_dll_off_mode_Pos (15) /*!< UMCTL2_T::MSTR: dll_off_mode Position */ +#define UMCTL2_MSTR_dll_off_mode_Msk (0x1ul << UMCTL2_MSTR_dll_off_mode_Pos) /*!< UMCTL2_T::MSTR: dll_off_mode Mask */ + +#define UMCTL2_MSTR_burst_rdwr_Pos (16) /*!< UMCTL2_T::MSTR: burst_rdwr Position */ +#define UMCTL2_MSTR_burst_rdwr_Msk (0xful << UMCTL2_MSTR_burst_rdwr_Pos) /*!< UMCTL2_T::MSTR: burst_rdwr Mask */ + +#define UMCTL2_MSTR_active_ranks_Pos (24) /*!< UMCTL2_T::MSTR: active_ranks Position */ +#define UMCTL2_MSTR_active_ranks_Msk (0x3ul << UMCTL2_MSTR_active_ranks_Pos) /*!< UMCTL2_T::MSTR: active_ranks Mask */ + +#define UMCTL2_STAT_operating_mode_Pos (0) /*!< UMCTL2_T::STAT: operating_mode Position*/ +#define UMCTL2_STAT_operating_mode_Msk (0x3ul << UMCTL2_STAT_operating_mode_Pos) /*!< UMCTL2_T::STAT: operating_mode Mask */ + +#define UMCTL2_STAT_selfref_type_Pos (4) /*!< UMCTL2_T::STAT: selfref_type Position */ +#define UMCTL2_STAT_selfref_type_Msk (0x3ul << UMCTL2_STAT_selfref_type_Pos) /*!< UMCTL2_T::STAT: selfref_type Mask */ + +#define UMCTL2_STAT_selfref_cam_not_empty_Pos (12) /*!< UMCTL2_T::STAT: selfref_cam_not_empty Position*/ +#define UMCTL2_STAT_selfref_cam_not_empty_Msk (0x1ul << UMCTL2_STAT_selfref_cam_not_empty_Pos) /*!< UMCTL2_T::STAT: selfref_cam_not_empty Mask*/ + +#define UMCTL2_MRCTRL0_mr_rank_Pos (4) /*!< UMCTL2_T::MRCTRL0: mr_rank Position */ +#define UMCTL2_MRCTRL0_mr_rank_Msk (0x3ul << UMCTL2_MRCTRL0_mr_rank_Pos) /*!< UMCTL2_T::MRCTRL0: mr_rank Mask */ + +#define UMCTL2_MRCTRL0_mr_addr_Pos (12) /*!< UMCTL2_T::MRCTRL0: mr_addr Position */ +#define UMCTL2_MRCTRL0_mr_addr_Msk (0xful << UMCTL2_MRCTRL0_mr_addr_Pos) /*!< UMCTL2_T::MRCTRL0: mr_addr Mask */ + +#define UMCTL2_MRCTRL0_mr_wr_Pos (31) /*!< UMCTL2_T::MRCTRL0: mr_wr Position */ +#define UMCTL2_MRCTRL0_mr_wr_Msk (0x1ul << UMCTL2_MRCTRL0_mr_wr_Pos) /*!< UMCTL2_T::MRCTRL0: mr_wr Mask */ + +#define UMCTL2_MRCTRL1_mr_data_Pos (0) /*!< UMCTL2_T::MRCTRL1: mr_data Position */ +#define UMCTL2_MRCTRL1_mr_data_Msk (0xfffful << UMCTL2_MRCTRL1_mr_data_Pos) /*!< UMCTL2_T::MRCTRL1: mr_data Mask */ + +#define UMCTL2_MRSTAT_mr_wr_busy_Pos (0) /*!< UMCTL2_T::MRSTAT: mr_wr_busy Position */ +#define UMCTL2_MRSTAT_mr_wr_busy_Msk (0x1ul << UMCTL2_MRSTAT_mr_wr_busy_Pos) /*!< UMCTL2_T::MRSTAT: mr_wr_busy Mask */ + +#define UMCTL2_PWRCTL_selfref_en_Pos (0) /*!< UMCTL2_T::PWRCTL: selfref_en Position */ +#define UMCTL2_PWRCTL_selfref_en_Msk (0x1ul << UMCTL2_PWRCTL_selfref_en_Pos) /*!< UMCTL2_T::PWRCTL: selfref_en Mask */ + +#define UMCTL2_PWRCTL_powerdown_en_Pos (1) /*!< UMCTL2_T::PWRCTL: powerdown_en Position*/ +#define UMCTL2_PWRCTL_powerdown_en_Msk (0x1ul << UMCTL2_PWRCTL_powerdown_en_Pos) /*!< UMCTL2_T::PWRCTL: powerdown_en Mask */ + +#define UMCTL2_PWRCTL_en_dfi_dram_clk_disable_Pos (3) /*!< UMCTL2_T::PWRCTL: en_dfi_dram_clk_disable Position*/ +#define UMCTL2_PWRCTL_en_dfi_dram_clk_disable_Msk (0x1ul << UMCTL2_PWRCTL_en_dfi_dram_clk_disable_Pos) /*!< UMCTL2_T::PWRCTL: en_dfi_dram_clk_disable Mask*/ + +#define UMCTL2_PWRCTL_selfref_sw_Pos (5) /*!< UMCTL2_T::PWRCTL: selfref_sw Position */ +#define UMCTL2_PWRCTL_selfref_sw_Msk (0x1ul << UMCTL2_PWRCTL_selfref_sw_Pos) /*!< UMCTL2_T::PWRCTL: selfref_sw Mask */ + +#define UMCTL2_PWRCTL_dis_cam_drain_selfref_Pos (7) /*!< UMCTL2_T::PWRCTL: dis_cam_drain_selfref Position*/ +#define UMCTL2_PWRCTL_dis_cam_drain_selfref_Msk (0x1ul << UMCTL2_PWRCTL_dis_cam_drain_selfref_Pos) /*!< UMCTL2_T::PWRCTL: dis_cam_drain_selfref Mask*/ + +#define UMCTL2_PWRTMG_powerdown_to_x32_Pos (0) /*!< UMCTL2_T::PWRTMG: powerdown_to_x32 Position*/ +#define UMCTL2_PWRTMG_powerdown_to_x32_Msk (0x1ful << UMCTL2_PWRTMG_powerdown_to_x32_Pos) /*!< UMCTL2_T::PWRTMG: powerdown_to_x32 Mask*/ + +#define UMCTL2_PWRTMG_selfref_to_x32_Pos (16) /*!< UMCTL2_T::PWRTMG: selfref_to_x32 Position*/ +#define UMCTL2_PWRTMG_selfref_to_x32_Msk (0xfful << UMCTL2_PWRTMG_selfref_to_x32_Pos) /*!< UMCTL2_T::PWRTMG: selfref_to_x32 Mask */ + +#define UMCTL2_HWLPCTL_hw_lp_en_Pos (0) /*!< UMCTL2_T::HWLPCTL: hw_lp_en Position */ +#define UMCTL2_HWLPCTL_hw_lp_en_Msk (0x1ul << UMCTL2_HWLPCTL_hw_lp_en_Pos) /*!< UMCTL2_T::HWLPCTL: hw_lp_en Mask */ + +#define UMCTL2_HWLPCTL_hw_lp_exit_idle_en_Pos (1) /*!< UMCTL2_T::HWLPCTL: hw_lp_exit_idle_en Position*/ +#define UMCTL2_HWLPCTL_hw_lp_exit_idle_en_Msk (0x1ul << UMCTL2_HWLPCTL_hw_lp_exit_idle_en_Pos) /*!< UMCTL2_T::HWLPCTL: hw_lp_exit_idle_en Mask*/ + +#define UMCTL2_HWLPCTL_hw_lp_idle_x32_Pos (16) /*!< UMCTL2_T::HWLPCTL: hw_lp_idle_x32 Position*/ +#define UMCTL2_HWLPCTL_hw_lp_idle_x32_Msk (0xffful << UMCTL2_HWLPCTL_hw_lp_idle_x32_Pos) /*!< UMCTL2_T::HWLPCTL: hw_lp_idle_x32 Mask */ + +#define UMCTL2_RFSHCTL0_refresh_burst_Pos (4) /*!< UMCTL2_T::RFSHCTL0: refresh_burst Position*/ +#define UMCTL2_RFSHCTL0_refresh_burst_Msk (0x3ful << UMCTL2_RFSHCTL0_refresh_burst_Pos) /*!< UMCTL2_T::RFSHCTL0: refresh_burst Mask */ + +#define UMCTL2_RFSHCTL0_refresh_to_x1_x32_Pos (12) /*!< UMCTL2_T::RFSHCTL0: refresh_to_x1_x32 Position*/ +#define UMCTL2_RFSHCTL0_refresh_to_x1_x32_Msk (0x1ful << UMCTL2_RFSHCTL0_refresh_to_x1_x32_Pos) /*!< UMCTL2_T::RFSHCTL0: refresh_to_x1_x32 Mask*/ + +#define UMCTL2_RFSHCTL0_refresh_margin_Pos (20) /*!< UMCTL2_T::RFSHCTL0: refresh_margin Position*/ +#define UMCTL2_RFSHCTL0_refresh_margin_Msk (0xful << UMCTL2_RFSHCTL0_refresh_margin_Pos) /*!< UMCTL2_T::RFSHCTL0: refresh_margin Mask*/ + +#define UMCTL2_RFSHCTL1_refresh_timer0_start_value_x32_Pos (0) /*!< UMCTL2_T::RFSHCTL1: refresh_timer0_start_value_x32 Position*/ +#define UMCTL2_RFSHCTL1_refresh_timer0_start_value_x32_Msk (0xffful << UMCTL2_RFSHCTL1_refresh_timer0_start_value_x32_Pos) /*!< UMCTL2_T::RFSHCTL1: refresh_timer0_start_value_x32 Mask*/ + +#define UMCTL2_RFSHCTL1_refresh_timer1_start_value_x32_Pos (16) /*!< UMCTL2_T::RFSHCTL1: refresh_timer1_start_value_x32 Position*/ +#define UMCTL2_RFSHCTL1_refresh_timer1_start_value_x32_Msk (0xffful << UMCTL2_RFSHCTL1_refresh_timer1_start_value_x32_Pos) /*!< UMCTL2_T::RFSHCTL1: refresh_timer1_start_value_x32 Mask*/ + +#define UMCTL2_RFSHCTL3_dis_auto_refresh_Pos (0) /*!< UMCTL2_T::RFSHCTL3: dis_auto_refresh Position*/ +#define UMCTL2_RFSHCTL3_dis_auto_refresh_Msk (0x1ul << UMCTL2_RFSHCTL3_dis_auto_refresh_Pos) /*!< UMCTL2_T::RFSHCTL3: dis_auto_refresh Mask*/ + +#define UMCTL2_RFSHCTL3_refresh_update_level_Pos (1) /*!< UMCTL2_T::RFSHCTL3: refresh_update_level Position*/ +#define UMCTL2_RFSHCTL3_refresh_update_level_Msk (0x1ul << UMCTL2_RFSHCTL3_refresh_update_level_Pos) /*!< UMCTL2_T::RFSHCTL3: refresh_update_level Mask*/ + +#define UMCTL2_RFSHTMG_t_rfc_min_Pos (0) /*!< UMCTL2_T::RFSHTMG: t_rfc_min Position */ +#define UMCTL2_RFSHTMG_t_rfc_min_Msk (0x3fful << UMCTL2_RFSHTMG_t_rfc_min_Pos) /*!< UMCTL2_T::RFSHTMG: t_rfc_min Mask */ + +#define UMCTL2_RFSHTMG_t_rfc_nom_x1_x32_Pos (16) /*!< UMCTL2_T::RFSHTMG: t_rfc_nom_x1_x32 Position*/ +#define UMCTL2_RFSHTMG_t_rfc_nom_x1_x32_Msk (0xffful << UMCTL2_RFSHTMG_t_rfc_nom_x1_x32_Pos) /*!< UMCTL2_T::RFSHTMG: t_rfc_nom_x1_x32 Mask*/ + +#define UMCTL2_CRCPARCTL0_dfi_alert_err_int_en_Pos (0) /*!< UMCTL2_T::CRCPARCTL0: dfi_alert_err_int_en Position*/ +#define UMCTL2_CRCPARCTL0_dfi_alert_err_int_en_Msk (0x1ul << UMCTL2_CRCPARCTL0_dfi_alert_err_int_en_Pos) /*!< UMCTL2_T::CRCPARCTL0: dfi_alert_err_int_en Mask*/ + +#define UMCTL2_CRCPARCTL0_dfi_alert_err_int_clr_Pos (1) /*!< UMCTL2_T::CRCPARCTL0: dfi_alert_err_int_clr Position*/ +#define UMCTL2_CRCPARCTL0_dfi_alert_err_int_clr_Msk (0x1ul << UMCTL2_CRCPARCTL0_dfi_alert_err_int_clr_Pos) /*!< UMCTL2_T::CRCPARCTL0: dfi_alert_err_int_clr Mask*/ + +#define UMCTL2_CRCPARCTL0_dfi_alert_err_cnt_clr_Pos (2) /*!< UMCTL2_T::CRCPARCTL0: dfi_alert_err_cnt_clr Position*/ +#define UMCTL2_CRCPARCTL0_dfi_alert_err_cnt_clr_Msk (0x1ul << UMCTL2_CRCPARCTL0_dfi_alert_err_cnt_clr_Pos) /*!< UMCTL2_T::CRCPARCTL0: dfi_alert_err_cnt_clr Mask*/ + +#define UMCTL2_CRCPARSTAT_dfi_alert_err_cnt_Pos (0) /*!< UMCTL2_T::CRCPARSTAT: dfi_alert_err_cnt Position*/ +#define UMCTL2_CRCPARSTAT_dfi_alert_err_cnt_Msk (0xfffful << UMCTL2_CRCPARSTAT_dfi_alert_err_cnt_Pos) /*!< UMCTL2_T::CRCPARSTAT: dfi_alert_err_cnt Mask*/ + +#define UMCTL2_CRCPARSTAT_dfi_alert_err_int_Pos (16) /*!< UMCTL2_T::CRCPARSTAT: dfi_alert_err_int Position*/ +#define UMCTL2_CRCPARSTAT_dfi_alert_err_int_Msk (0x1ul << UMCTL2_CRCPARSTAT_dfi_alert_err_int_Pos) /*!< UMCTL2_T::CRCPARSTAT: dfi_alert_err_int Mask*/ + +#define UMCTL2_INIT0_pre_cke_x1024_Pos (0) /*!< UMCTL2_T::INIT0: pre_cke_x1024 Position*/ +#define UMCTL2_INIT0_pre_cke_x1024_Msk (0xffful << UMCTL2_INIT0_pre_cke_x1024_Pos) /*!< UMCTL2_T::INIT0: pre_cke_x1024 Mask */ + +#define UMCTL2_INIT0_post_cke_x1024_Pos (16) /*!< UMCTL2_T::INIT0: post_cke_x1024 Position*/ +#define UMCTL2_INIT0_post_cke_x1024_Msk (0x3fful << UMCTL2_INIT0_post_cke_x1024_Pos) /*!< UMCTL2_T::INIT0: post_cke_x1024 Mask */ + +#define UMCTL2_INIT0_skip_dram_init_Pos (30) /*!< UMCTL2_T::INIT0: skip_dram_init Position*/ +#define UMCTL2_INIT0_skip_dram_init_Msk (0x3ul << UMCTL2_INIT0_skip_dram_init_Pos) /*!< UMCTL2_T::INIT0: skip_dram_init Mask */ + +#define UMCTL2_INIT1_pre_ocd_x32_Pos (0) /*!< UMCTL2_T::INIT1: pre_ocd_x32 Position */ +#define UMCTL2_INIT1_pre_ocd_x32_Msk (0xful << UMCTL2_INIT1_pre_ocd_x32_Pos) /*!< UMCTL2_T::INIT1: pre_ocd_x32 Mask */ + +#define UMCTL2_INIT1_dram_rstn_x1024_Pos (16) /*!< UMCTL2_T::INIT1: dram_rstn_x1024 Position*/ +#define UMCTL2_INIT1_dram_rstn_x1024_Msk (0x1fful << UMCTL2_INIT1_dram_rstn_x1024_Pos) /*!< UMCTL2_T::INIT1: dram_rstn_x1024 Mask */ + +#define UMCTL2_INIT3_emr_Pos (0) /*!< UMCTL2_T::INIT3: emr Position */ +#define UMCTL2_INIT3_emr_Msk (0xfffful << UMCTL2_INIT3_emr_Pos) /*!< UMCTL2_T::INIT3: emr Mask */ + +#define UMCTL2_INIT3_mr_Pos (16) /*!< UMCTL2_T::INIT3: mr Position */ +#define UMCTL2_INIT3_mr_Msk (0xfffful << UMCTL2_INIT3_mr_Pos) /*!< UMCTL2_T::INIT3: mr Mask */ + +#define UMCTL2_INIT4_emr3_Pos (0) /*!< UMCTL2_T::INIT4: emr3 Position */ +#define UMCTL2_INIT4_emr3_Msk (0xfffful << UMCTL2_INIT4_emr3_Pos) /*!< UMCTL2_T::INIT4: emr3 Mask */ + +#define UMCTL2_INIT4_emr2_Pos (16) /*!< UMCTL2_T::INIT4: emr2 Position */ +#define UMCTL2_INIT4_emr2_Msk (0xfffful << UMCTL2_INIT4_emr2_Pos) /*!< UMCTL2_T::INIT4: emr2 Mask */ + +#define UMCTL2_INIT5_dev_zqinit_x32_Pos (16) /*!< UMCTL2_T::INIT5: dev_zqinit_x32 Position*/ +#define UMCTL2_INIT5_dev_zqinit_x32_Msk (0xfful << UMCTL2_INIT5_dev_zqinit_x32_Pos) /*!< UMCTL2_T::INIT5: dev_zqinit_x32 Mask */ + +#define UMCTL2_DIMMCTL_dimm_stagger_cs_en_Pos (0) /*!< UMCTL2_T::DIMMCTL: dimm_stagger_cs_en Position*/ +#define UMCTL2_DIMMCTL_dimm_stagger_cs_en_Msk (0x1ul << UMCTL2_DIMMCTL_dimm_stagger_cs_en_Pos) /*!< UMCTL2_T::DIMMCTL: dimm_stagger_cs_en Mask*/ + +#define UMCTL2_DIMMCTL_dimm_addr_mirr_en_Pos (1) /*!< UMCTL2_T::DIMMCTL: dimm_addr_mirr_en Position*/ +#define UMCTL2_DIMMCTL_dimm_addr_mirr_en_Msk (0x1ul << UMCTL2_DIMMCTL_dimm_addr_mirr_en_Pos) /*!< UMCTL2_T::DIMMCTL: dimm_addr_mirr_en Mask*/ + +#define UMCTL2_RANKCTL_max_rank_rd_Pos (0) /*!< UMCTL2_T::RANKCTL: max_rank_rd Position*/ +#define UMCTL2_RANKCTL_max_rank_rd_Msk (0xful << UMCTL2_RANKCTL_max_rank_rd_Pos) /*!< UMCTL2_T::RANKCTL: max_rank_rd Mask */ + +#define UMCTL2_RANKCTL_diff_rank_rd_gap_Pos (4) /*!< UMCTL2_T::RANKCTL: diff_rank_rd_gap Position*/ +#define UMCTL2_RANKCTL_diff_rank_rd_gap_Msk (0xful << UMCTL2_RANKCTL_diff_rank_rd_gap_Pos) /*!< UMCTL2_T::RANKCTL: diff_rank_rd_gap Mask*/ + +#define UMCTL2_RANKCTL_diff_rank_wr_gap_Pos (8) /*!< UMCTL2_T::RANKCTL: diff_rank_wr_gap Position*/ +#define UMCTL2_RANKCTL_diff_rank_wr_gap_Msk (0xful << UMCTL2_RANKCTL_diff_rank_wr_gap_Pos) /*!< UMCTL2_T::RANKCTL: diff_rank_wr_gap Mask*/ + +#define UMCTL2_RANKCTL_max_rank_wr_Pos (12) /*!< UMCTL2_T::RANKCTL: max_rank_wr Position*/ +#define UMCTL2_RANKCTL_max_rank_wr_Msk (0xful << UMCTL2_RANKCTL_max_rank_wr_Pos) /*!< UMCTL2_T::RANKCTL: max_rank_wr Mask */ + +#define UMCTL2_RANKCTL_diff_rank_rd_gap_msb_Pos (24) /*!< UMCTL2_T::RANKCTL: diff_rank_rd_gap_msb Position*/ +#define UMCTL2_RANKCTL_diff_rank_rd_gap_msb_Msk (0x1ul << UMCTL2_RANKCTL_diff_rank_rd_gap_msb_Pos) /*!< UMCTL2_T::RANKCTL: diff_rank_rd_gap_msb Mask*/ + +#define UMCTL2_RANKCTL_diff_rank_wr_gap_msb_Pos (26) /*!< UMCTL2_T::RANKCTL: diff_rank_wr_gap_msb Position*/ +#define UMCTL2_RANKCTL_diff_rank_wr_gap_msb_Msk (0x1ul << UMCTL2_RANKCTL_diff_rank_wr_gap_msb_Pos) /*!< UMCTL2_T::RANKCTL: diff_rank_wr_gap_msb Mask*/ + +#define UMCTL2_DRAMTMG0_t_ras_min_Pos (0) /*!< UMCTL2_T::DRAMTMG0: t_ras_min Position */ +#define UMCTL2_DRAMTMG0_t_ras_min_Msk (0x3ful << UMCTL2_DRAMTMG0_t_ras_min_Pos) /*!< UMCTL2_T::DRAMTMG0: t_ras_min Mask */ + +#define UMCTL2_DRAMTMG0_t_ras_max_Pos (8) /*!< UMCTL2_T::DRAMTMG0: t_ras_max Position */ +#define UMCTL2_DRAMTMG0_t_ras_max_Msk (0x7ful << UMCTL2_DRAMTMG0_t_ras_max_Pos) /*!< UMCTL2_T::DRAMTMG0: t_ras_max Mask */ + +#define UMCTL2_DRAMTMG0_t_faw_Pos (16) /*!< UMCTL2_T::DRAMTMG0: t_faw Position */ +#define UMCTL2_DRAMTMG0_t_faw_Msk (0x3ful << UMCTL2_DRAMTMG0_t_faw_Pos) /*!< UMCTL2_T::DRAMTMG0: t_faw Mask */ + +#define UMCTL2_DRAMTMG0_wr2pre_Pos (24) /*!< UMCTL2_T::DRAMTMG0: wr2pre Position */ +#define UMCTL2_DRAMTMG0_wr2pre_Msk (0x7ful << UMCTL2_DRAMTMG0_wr2pre_Pos) /*!< UMCTL2_T::DRAMTMG0: wr2pre Mask */ + +#define UMCTL2_DRAMTMG1_t_rc_Pos (0) /*!< UMCTL2_T::DRAMTMG1: t_rc Position */ +#define UMCTL2_DRAMTMG1_t_rc_Msk (0x7ful << UMCTL2_DRAMTMG1_t_rc_Pos) /*!< UMCTL2_T::DRAMTMG1: t_rc Mask */ + +#define UMCTL2_DRAMTMG1_rd2pre_Pos (8) /*!< UMCTL2_T::DRAMTMG1: rd2pre Position */ +#define UMCTL2_DRAMTMG1_rd2pre_Msk (0x3ful << UMCTL2_DRAMTMG1_rd2pre_Pos) /*!< UMCTL2_T::DRAMTMG1: rd2pre Mask */ + +#define UMCTL2_DRAMTMG1_t_xp_Pos (16) /*!< UMCTL2_T::DRAMTMG1: t_xp Position */ +#define UMCTL2_DRAMTMG1_t_xp_Msk (0x1ful << UMCTL2_DRAMTMG1_t_xp_Pos) /*!< UMCTL2_T::DRAMTMG1: t_xp Mask */ + +#define UMCTL2_DRAMTMG2_wr2rd_Pos (0) /*!< UMCTL2_T::DRAMTMG2: wr2rd Position */ +#define UMCTL2_DRAMTMG2_wr2rd_Msk (0x3ful << UMCTL2_DRAMTMG2_wr2rd_Pos) /*!< UMCTL2_T::DRAMTMG2: wr2rd Mask */ + +#define UMCTL2_DRAMTMG2_rd2wr_Pos (8) /*!< UMCTL2_T::DRAMTMG2: rd2wr Position */ +#define UMCTL2_DRAMTMG2_rd2wr_Msk (0x3ful << UMCTL2_DRAMTMG2_rd2wr_Pos) /*!< UMCTL2_T::DRAMTMG2: rd2wr Mask */ + +#define UMCTL2_DRAMTMG3_t_mod_Pos (0) /*!< UMCTL2_T::DRAMTMG3: t_mod Position */ +#define UMCTL2_DRAMTMG3_t_mod_Msk (0x3fful << UMCTL2_DRAMTMG3_t_mod_Pos) /*!< UMCTL2_T::DRAMTMG3: t_mod Mask */ + +#define UMCTL2_DRAMTMG3_t_mrd_Pos (12) /*!< UMCTL2_T::DRAMTMG3: t_mrd Position */ +#define UMCTL2_DRAMTMG3_t_mrd_Msk (0x3ful << UMCTL2_DRAMTMG3_t_mrd_Pos) /*!< UMCTL2_T::DRAMTMG3: t_mrd Mask */ + +#define UMCTL2_DRAMTMG4_t_rp_Pos (0) /*!< UMCTL2_T::DRAMTMG4: t_rp Position */ +#define UMCTL2_DRAMTMG4_t_rp_Msk (0x1ful << UMCTL2_DRAMTMG4_t_rp_Pos) /*!< UMCTL2_T::DRAMTMG4: t_rp Mask */ + +#define UMCTL2_DRAMTMG4_t_rrd_Pos (8) /*!< UMCTL2_T::DRAMTMG4: t_rrd Position */ +#define UMCTL2_DRAMTMG4_t_rrd_Msk (0xful << UMCTL2_DRAMTMG4_t_rrd_Pos) /*!< UMCTL2_T::DRAMTMG4: t_rrd Mask */ + +#define UMCTL2_DRAMTMG4_t_ccd_Pos (16) /*!< UMCTL2_T::DRAMTMG4: t_ccd Position */ +#define UMCTL2_DRAMTMG4_t_ccd_Msk (0xful << UMCTL2_DRAMTMG4_t_ccd_Pos) /*!< UMCTL2_T::DRAMTMG4: t_ccd Mask */ + +#define UMCTL2_DRAMTMG4_t_rcd_Pos (24) /*!< UMCTL2_T::DRAMTMG4: t_rcd Position */ +#define UMCTL2_DRAMTMG4_t_rcd_Msk (0x1ful << UMCTL2_DRAMTMG4_t_rcd_Pos) /*!< UMCTL2_T::DRAMTMG4: t_rcd Mask */ + +#define UMCTL2_DRAMTMG5_t_cke_Pos (0) /*!< UMCTL2_T::DRAMTMG5: t_cke Position */ +#define UMCTL2_DRAMTMG5_t_cke_Msk (0x1ful << UMCTL2_DRAMTMG5_t_cke_Pos) /*!< UMCTL2_T::DRAMTMG5: t_cke Mask */ + +#define UMCTL2_DRAMTMG5_t_ckesr_Pos (8) /*!< UMCTL2_T::DRAMTMG5: t_ckesr Position */ +#define UMCTL2_DRAMTMG5_t_ckesr_Msk (0x3ful << UMCTL2_DRAMTMG5_t_ckesr_Pos) /*!< UMCTL2_T::DRAMTMG5: t_ckesr Mask */ + +#define UMCTL2_DRAMTMG5_t_cksre_Pos (16) /*!< UMCTL2_T::DRAMTMG5: t_cksre Position */ +#define UMCTL2_DRAMTMG5_t_cksre_Msk (0x7ful << UMCTL2_DRAMTMG5_t_cksre_Pos) /*!< UMCTL2_T::DRAMTMG5: t_cksre Mask */ + +#define UMCTL2_DRAMTMG5_t_cksrx_Pos (24) /*!< UMCTL2_T::DRAMTMG5: t_cksrx Position */ +#define UMCTL2_DRAMTMG5_t_cksrx_Msk (0xful << UMCTL2_DRAMTMG5_t_cksrx_Pos) /*!< UMCTL2_T::DRAMTMG5: t_cksrx Mask */ + +#define UMCTL2_DRAMTMG8_t_xs_x32_Pos (0) /*!< UMCTL2_T::DRAMTMG8: t_xs_x32 Position */ +#define UMCTL2_DRAMTMG8_t_xs_x32_Msk (0x7ful << UMCTL2_DRAMTMG8_t_xs_x32_Pos) /*!< UMCTL2_T::DRAMTMG8: t_xs_x32 Mask */ + +#define UMCTL2_DRAMTMG8_t_xs_dll_x32_Pos (8) /*!< UMCTL2_T::DRAMTMG8: t_xs_dll_x32 Position*/ +#define UMCTL2_DRAMTMG8_t_xs_dll_x32_Msk (0x7ful << UMCTL2_DRAMTMG8_t_xs_dll_x32_Pos) /*!< UMCTL2_T::DRAMTMG8: t_xs_dll_x32 Mask */ + +#define UMCTL2_DRAMTMG15_t_stab_x32_Pos (0) /*!< UMCTL2_T::DRAMTMG15: t_stab_x32 Position*/ +#define UMCTL2_DRAMTMG15_t_stab_x32_Msk (0xfful << UMCTL2_DRAMTMG15_t_stab_x32_Pos) /*!< UMCTL2_T::DRAMTMG15: t_stab_x32 Mask */ + +#define UMCTL2_DRAMTMG15_en_dfi_lp_t_stab_Pos (31) /*!< UMCTL2_T::DRAMTMG15: en_dfi_lp_t_stab Position*/ +#define UMCTL2_DRAMTMG15_en_dfi_lp_t_stab_Msk (0x1ul << UMCTL2_DRAMTMG15_en_dfi_lp_t_stab_Pos) /*!< UMCTL2_T::DRAMTMG15: en_dfi_lp_t_stab Mask*/ + +#define UMCTL2_ZQCTL0_t_zq_short_nop_Pos (0) /*!< UMCTL2_T::ZQCTL0: t_zq_short_nop Position*/ +#define UMCTL2_ZQCTL0_t_zq_short_nop_Msk (0x3fful << UMCTL2_ZQCTL0_t_zq_short_nop_Pos) /*!< UMCTL2_T::ZQCTL0: t_zq_short_nop Mask */ + +#define UMCTL2_ZQCTL0_t_zq_long_nop_Pos (16) /*!< UMCTL2_T::ZQCTL0: t_zq_long_nop Position*/ +#define UMCTL2_ZQCTL0_t_zq_long_nop_Msk (0x7fful << UMCTL2_ZQCTL0_t_zq_long_nop_Pos) /*!< UMCTL2_T::ZQCTL0: t_zq_long_nop Mask */ + +#define UMCTL2_ZQCTL0_zq_resistor_shared_Pos (29) /*!< UMCTL2_T::ZQCTL0: zq_resistor_shared Position*/ +#define UMCTL2_ZQCTL0_zq_resistor_shared_Msk (0x1ul << UMCTL2_ZQCTL0_zq_resistor_shared_Pos) /*!< UMCTL2_T::ZQCTL0: zq_resistor_shared Mask*/ + +#define UMCTL2_ZQCTL0_dis_srx_zqcl_Pos (30) /*!< UMCTL2_T::ZQCTL0: dis_srx_zqcl Position*/ +#define UMCTL2_ZQCTL0_dis_srx_zqcl_Msk (0x1ul << UMCTL2_ZQCTL0_dis_srx_zqcl_Pos) /*!< UMCTL2_T::ZQCTL0: dis_srx_zqcl Mask */ + +#define UMCTL2_ZQCTL0_dis_auto_zq_Pos (31) /*!< UMCTL2_T::ZQCTL0: dis_auto_zq Position */ +#define UMCTL2_ZQCTL0_dis_auto_zq_Msk (0x1ul << UMCTL2_ZQCTL0_dis_auto_zq_Pos) /*!< UMCTL2_T::ZQCTL0: dis_auto_zq Mask */ + +#define UMCTL2_ZQCTL1_t_zq_short_interval_x1024_Pos (0) /*!< UMCTL2_T::ZQCTL1: t_zq_short_interval_x1024 Position*/ +#define UMCTL2_ZQCTL1_t_zq_short_interval_x1024_Msk (0xffffful << UMCTL2_ZQCTL1_t_zq_short_interval_x1024_Pos) /*!< UMCTL2_T::ZQCTL1: t_zq_short_interval_x1024 Mask*/ + +#define UMCTL2_DFITMG0_dfi_tphy_wrlat_Pos (0) /*!< UMCTL2_T::DFITMG0: dfi_tphy_wrlat Position*/ +#define UMCTL2_DFITMG0_dfi_tphy_wrlat_Msk (0x3ful << UMCTL2_DFITMG0_dfi_tphy_wrlat_Pos) /*!< UMCTL2_T::DFITMG0: dfi_tphy_wrlat Mask */ + +#define UMCTL2_DFITMG0_dfi_tphy_wrdata_Pos (8) /*!< UMCTL2_T::DFITMG0: dfi_tphy_wrdata Position*/ +#define UMCTL2_DFITMG0_dfi_tphy_wrdata_Msk (0x3ful << UMCTL2_DFITMG0_dfi_tphy_wrdata_Pos) /*!< UMCTL2_T::DFITMG0: dfi_tphy_wrdata Mask*/ + +#define UMCTL2_DFITMG0_dfi_wrdata_use_dfi_phy_clk_Pos (15) /*!< UMCTL2_T::DFITMG0: dfi_wrdata_use_dfi_phy_clk Position*/ +#define UMCTL2_DFITMG0_dfi_wrdata_use_dfi_phy_clk_Msk (0x1ul << UMCTL2_DFITMG0_dfi_wrdata_use_dfi_phy_clk_Pos) /*!< UMCTL2_T::DFITMG0: dfi_wrdata_use_dfi_phy_clk Mask*/ + +#define UMCTL2_DFITMG0_dfi_t_rddata_en_Pos (16) /*!< UMCTL2_T::DFITMG0: dfi_t_rddata_en Position*/ +#define UMCTL2_DFITMG0_dfi_t_rddata_en_Msk (0x7ful << UMCTL2_DFITMG0_dfi_t_rddata_en_Pos) /*!< UMCTL2_T::DFITMG0: dfi_t_rddata_en Mask*/ + +#define UMCTL2_DFITMG0_dfi_rddata_use_dfi_phy_clk_Pos (23) /*!< UMCTL2_T::DFITMG0: dfi_rddata_use_dfi_phy_clk Position*/ +#define UMCTL2_DFITMG0_dfi_rddata_use_dfi_phy_clk_Msk (0x1ul << UMCTL2_DFITMG0_dfi_rddata_use_dfi_phy_clk_Pos) /*!< UMCTL2_T::DFITMG0: dfi_rddata_use_dfi_phy_clk Mask*/ + +#define UMCTL2_DFITMG0_dfi_t_ctrl_delay_Pos (24) /*!< UMCTL2_T::DFITMG0: dfi_t_ctrl_delay Position*/ +#define UMCTL2_DFITMG0_dfi_t_ctrl_delay_Msk (0x1ful << UMCTL2_DFITMG0_dfi_t_ctrl_delay_Pos) /*!< UMCTL2_T::DFITMG0: dfi_t_ctrl_delay Mask*/ + +#define UMCTL2_DFITMG1_dfi_t_dram_clk_enable_Pos (0) /*!< UMCTL2_T::DFITMG1: dfi_t_dram_clk_enable Position*/ +#define UMCTL2_DFITMG1_dfi_t_dram_clk_enable_Msk (0x1ful << UMCTL2_DFITMG1_dfi_t_dram_clk_enable_Pos) /*!< UMCTL2_T::DFITMG1: dfi_t_dram_clk_enable Mask*/ + +#define UMCTL2_DFITMG1_dfi_t_dram_clk_disable_Pos (8) /*!< UMCTL2_T::DFITMG1: dfi_t_dram_clk_disable Position*/ +#define UMCTL2_DFITMG1_dfi_t_dram_clk_disable_Msk (0x1ful << UMCTL2_DFITMG1_dfi_t_dram_clk_disable_Pos) /*!< UMCTL2_T::DFITMG1: dfi_t_dram_clk_disable Mask*/ + +#define UMCTL2_DFITMG1_dfi_t_wrdata_delay_Pos (16) /*!< UMCTL2_T::DFITMG1: dfi_t_wrdata_delay Position*/ +#define UMCTL2_DFITMG1_dfi_t_wrdata_delay_Msk (0x1ful << UMCTL2_DFITMG1_dfi_t_wrdata_delay_Pos) /*!< UMCTL2_T::DFITMG1: dfi_t_wrdata_delay Mask*/ + +#define UMCTL2_DFITMG1_dfi_t_parin_lat_Pos (24) /*!< UMCTL2_T::DFITMG1: dfi_t_parin_lat Position*/ +#define UMCTL2_DFITMG1_dfi_t_parin_lat_Msk (0x3ul << UMCTL2_DFITMG1_dfi_t_parin_lat_Pos) /*!< UMCTL2_T::DFITMG1: dfi_t_parin_lat Mask*/ + +#define UMCTL2_DFILPCFG0_dfi_lp_en_pd_Pos (0) /*!< UMCTL2_T::DFILPCFG0: dfi_lp_en_pd Position*/ +#define UMCTL2_DFILPCFG0_dfi_lp_en_pd_Msk (0x1ul << UMCTL2_DFILPCFG0_dfi_lp_en_pd_Pos) /*!< UMCTL2_T::DFILPCFG0: dfi_lp_en_pd Mask */ + +#define UMCTL2_DFILPCFG0_dfi_lp_wakeup_pd_Pos (4) /*!< UMCTL2_T::DFILPCFG0: dfi_lp_wakeup_pd Position*/ +#define UMCTL2_DFILPCFG0_dfi_lp_wakeup_pd_Msk (0xful << UMCTL2_DFILPCFG0_dfi_lp_wakeup_pd_Pos) /*!< UMCTL2_T::DFILPCFG0: dfi_lp_wakeup_pd Mask*/ + +#define UMCTL2_DFILPCFG0_dfi_lp_en_sr_Pos (8) /*!< UMCTL2_T::DFILPCFG0: dfi_lp_en_sr Position*/ +#define UMCTL2_DFILPCFG0_dfi_lp_en_sr_Msk (0x1ul << UMCTL2_DFILPCFG0_dfi_lp_en_sr_Pos) /*!< UMCTL2_T::DFILPCFG0: dfi_lp_en_sr Mask */ + +#define UMCTL2_DFILPCFG0_dfi_lp_wakeup_sr_Pos (12) /*!< UMCTL2_T::DFILPCFG0: dfi_lp_wakeup_sr Position*/ +#define UMCTL2_DFILPCFG0_dfi_lp_wakeup_sr_Msk (0xful << UMCTL2_DFILPCFG0_dfi_lp_wakeup_sr_Pos) /*!< UMCTL2_T::DFILPCFG0: dfi_lp_wakeup_sr Mask*/ + +#define UMCTL2_DFILPCFG0_dfi_tlp_resp_Pos (24) /*!< UMCTL2_T::DFILPCFG0: dfi_tlp_resp Position*/ +#define UMCTL2_DFILPCFG0_dfi_tlp_resp_Msk (0x1ful << UMCTL2_DFILPCFG0_dfi_tlp_resp_Pos) /*!< UMCTL2_T::DFILPCFG0: dfi_tlp_resp Mask */ + +#define UMCTL2_DFIUPD0_dfi_t_ctrlup_min_Pos (0) /*!< UMCTL2_T::DFIUPD0: dfi_t_ctrlup_min Position*/ +#define UMCTL2_DFIUPD0_dfi_t_ctrlup_min_Msk (0x3fful << UMCTL2_DFIUPD0_dfi_t_ctrlup_min_Pos) /*!< UMCTL2_T::DFIUPD0: dfi_t_ctrlup_min Mask*/ + +#define UMCTL2_DFIUPD0_dfi_t_ctrlup_max_Pos (16) /*!< UMCTL2_T::DFIUPD0: dfi_t_ctrlup_max Position*/ +#define UMCTL2_DFIUPD0_dfi_t_ctrlup_max_Msk (0x3fful << UMCTL2_DFIUPD0_dfi_t_ctrlup_max_Pos) /*!< UMCTL2_T::DFIUPD0: dfi_t_ctrlup_max Mask*/ + +#define UMCTL2_DFIUPD0_ctrlupd_pre_srx_Pos (29) /*!< UMCTL2_T::DFIUPD0: ctrlupd_pre_srx Position*/ +#define UMCTL2_DFIUPD0_ctrlupd_pre_srx_Msk (0x1ul << UMCTL2_DFIUPD0_ctrlupd_pre_srx_Pos) /*!< UMCTL2_T::DFIUPD0: ctrlupd_pre_srx Mask*/ + +#define UMCTL2_DFIUPD0_dis_auto_ctrlupd_srx_Pos (30) /*!< UMCTL2_T::DFIUPD0: dis_auto_ctrlupd_srx Position*/ +#define UMCTL2_DFIUPD0_dis_auto_ctrlupd_srx_Msk (0x1ul << UMCTL2_DFIUPD0_dis_auto_ctrlupd_srx_Pos) /*!< UMCTL2_T::DFIUPD0: dis_auto_ctrlupd_srx Mask*/ + +#define UMCTL2_DFIUPD0_dis_auto_ctrlupd_Pos (31) /*!< UMCTL2_T::DFIUPD0: dis_auto_ctrlupd Position*/ +#define UMCTL2_DFIUPD0_dis_auto_ctrlupd_Msk (0x1ul << UMCTL2_DFIUPD0_dis_auto_ctrlupd_Pos) /*!< UMCTL2_T::DFIUPD0: dis_auto_ctrlupd Mask*/ + +#define UMCTL2_DFIUPD1_dfi_t_ctrlupd_interval_max_x1024_Pos (0) /*!< UMCTL2_T::DFIUPD1: dfi_t_ctrlupd_interval_max_x1024 Position*/ +#define UMCTL2_DFIUPD1_dfi_t_ctrlupd_interval_max_x1024_Msk (0xfful << UMCTL2_DFIUPD1_dfi_t_ctrlupd_interval_max_x1024_Pos) /*!< UMCTL2_T::DFIUPD1: dfi_t_ctrlupd_interval_max_x1024 Mask*/ + +#define UMCTL2_DFIUPD1_dfi_t_ctrlupd_interval_min_x1024_Pos (16) /*!< UMCTL2_T::DFIUPD1: dfi_t_ctrlupd_interval_min_x1024 Position*/ +#define UMCTL2_DFIUPD1_dfi_t_ctrlupd_interval_min_x1024_Msk (0xfful << UMCTL2_DFIUPD1_dfi_t_ctrlupd_interval_min_x1024_Pos) /*!< UMCTL2_T::DFIUPD1: dfi_t_ctrlupd_interval_min_x1024 Mask*/ + +#define UMCTL2_DFIUPD2_dfi_phyupd_en_Pos (31) /*!< UMCTL2_T::DFIUPD2: dfi_phyupd_en Position*/ +#define UMCTL2_DFIUPD2_dfi_phyupd_en_Msk (0x1ul << UMCTL2_DFIUPD2_dfi_phyupd_en_Pos) /*!< UMCTL2_T::DFIUPD2: dfi_phyupd_en Mask */ + +#define UMCTL2_DFIMISC_dfi_init_complete_en_Pos (0) /*!< UMCTL2_T::DFIMISC: dfi_init_complete_en Position*/ +#define UMCTL2_DFIMISC_dfi_init_complete_en_Msk (0x1ul << UMCTL2_DFIMISC_dfi_init_complete_en_Pos) /*!< UMCTL2_T::DFIMISC: dfi_init_complete_en Mask*/ + +#define UMCTL2_DFIMISC_ctl_idle_en_Pos (4) /*!< UMCTL2_T::DFIMISC: ctl_idle_en Position*/ +#define UMCTL2_DFIMISC_ctl_idle_en_Msk (0x1ul << UMCTL2_DFIMISC_ctl_idle_en_Pos) /*!< UMCTL2_T::DFIMISC: ctl_idle_en Mask */ + +#define UMCTL2_DFIMISC_dfi_init_start_Pos (5) /*!< UMCTL2_T::DFIMISC: dfi_init_start Position*/ +#define UMCTL2_DFIMISC_dfi_init_start_Msk (0x1ul << UMCTL2_DFIMISC_dfi_init_start_Pos) /*!< UMCTL2_T::DFIMISC: dfi_init_start Mask */ + +#define UMCTL2_DFIMISC_dfi_frequency_Pos (8) /*!< UMCTL2_T::DFIMISC: dfi_frequency Position*/ +#define UMCTL2_DFIMISC_dfi_frequency_Msk (0x1ful << UMCTL2_DFIMISC_dfi_frequency_Pos) /*!< UMCTL2_T::DFIMISC: dfi_frequency Mask */ + +#define UMCTL2_DFISTAT_dfi_init_complete_Pos (0) /*!< UMCTL2_T::DFISTAT: dfi_init_complete Position*/ +#define UMCTL2_DFISTAT_dfi_init_complete_Msk (0x1ul << UMCTL2_DFISTAT_dfi_init_complete_Pos) /*!< UMCTL2_T::DFISTAT: dfi_init_complete Mask*/ + +#define UMCTL2_DFISTAT_dfi_lp_ack_Pos (1) /*!< UMCTL2_T::DFISTAT: dfi_lp_ack Position */ +#define UMCTL2_DFISTAT_dfi_lp_ack_Msk (0x1ul << UMCTL2_DFISTAT_dfi_lp_ack_Pos) /*!< UMCTL2_T::DFISTAT: dfi_lp_ack Mask */ + +#define UMCTL2_DFIPHYMSTR_dfi_phymstr_en_Pos (0) /*!< UMCTL2_T::DFIPHYMSTR: dfi_phymstr_en Position*/ +#define UMCTL2_DFIPHYMSTR_dfi_phymstr_en_Msk (0x1ul << UMCTL2_DFIPHYMSTR_dfi_phymstr_en_Pos) /*!< UMCTL2_T::DFIPHYMSTR: dfi_phymstr_en Mask*/ + +#define UMCTL2_ADDRMAP0_addrmap_cs_bit0_Pos (0) /*!< UMCTL2_T::ADDRMAP0: addrmap_cs_bit0 Position*/ +#define UMCTL2_ADDRMAP0_addrmap_cs_bit0_Msk (0x1ful << UMCTL2_ADDRMAP0_addrmap_cs_bit0_Pos) /*!< UMCTL2_T::ADDRMAP0: addrmap_cs_bit0 Mask*/ + +#define UMCTL2_ADDRMAP1_addrmap_bank_b0_Pos (0) /*!< UMCTL2_T::ADDRMAP1: addrmap_bank_b0 Position*/ +#define UMCTL2_ADDRMAP1_addrmap_bank_b0_Msk (0x3ful << UMCTL2_ADDRMAP1_addrmap_bank_b0_Pos) /*!< UMCTL2_T::ADDRMAP1: addrmap_bank_b0 Mask*/ + +#define UMCTL2_ADDRMAP1_addrmap_bank_b1_Pos (8) /*!< UMCTL2_T::ADDRMAP1: addrmap_bank_b1 Position*/ +#define UMCTL2_ADDRMAP1_addrmap_bank_b1_Msk (0x3ful << UMCTL2_ADDRMAP1_addrmap_bank_b1_Pos) /*!< UMCTL2_T::ADDRMAP1: addrmap_bank_b1 Mask*/ + +#define UMCTL2_ADDRMAP1_addrmap_bank_b2_Pos (16) /*!< UMCTL2_T::ADDRMAP1: addrmap_bank_b2 Position*/ +#define UMCTL2_ADDRMAP1_addrmap_bank_b2_Msk (0x3ful << UMCTL2_ADDRMAP1_addrmap_bank_b2_Pos) /*!< UMCTL2_T::ADDRMAP1: addrmap_bank_b2 Mask*/ + +#define UMCTL2_ADDRMAP2_addrmap_col_b2_Pos (0) /*!< UMCTL2_T::ADDRMAP2: addrmap_col_b2 Position*/ +#define UMCTL2_ADDRMAP2_addrmap_col_b2_Msk (0xful << UMCTL2_ADDRMAP2_addrmap_col_b2_Pos) /*!< UMCTL2_T::ADDRMAP2: addrmap_col_b2 Mask*/ + +#define UMCTL2_ADDRMAP2_addrmap_col_b3_Pos (8) /*!< UMCTL2_T::ADDRMAP2: addrmap_col_b3 Position*/ +#define UMCTL2_ADDRMAP2_addrmap_col_b3_Msk (0x1ful << UMCTL2_ADDRMAP2_addrmap_col_b3_Pos) /*!< UMCTL2_T::ADDRMAP2: addrmap_col_b3 Mask*/ + +#define UMCTL2_ADDRMAP2_addrmap_col_b4_Pos (16) /*!< UMCTL2_T::ADDRMAP2: addrmap_col_b4 Position*/ +#define UMCTL2_ADDRMAP2_addrmap_col_b4_Msk (0xful << UMCTL2_ADDRMAP2_addrmap_col_b4_Pos) /*!< UMCTL2_T::ADDRMAP2: addrmap_col_b4 Mask*/ + +#define UMCTL2_ADDRMAP2_addrmap_col_b5_Pos (24) /*!< UMCTL2_T::ADDRMAP2: addrmap_col_b5 Position*/ +#define UMCTL2_ADDRMAP2_addrmap_col_b5_Msk (0xful << UMCTL2_ADDRMAP2_addrmap_col_b5_Pos) /*!< UMCTL2_T::ADDRMAP2: addrmap_col_b5 Mask*/ + +#define UMCTL2_ADDRMAP3_addrmap_col_b6_Pos (0) /*!< UMCTL2_T::ADDRMAP3: addrmap_col_b6 Position*/ +#define UMCTL2_ADDRMAP3_addrmap_col_b6_Msk (0x1ful << UMCTL2_ADDRMAP3_addrmap_col_b6_Pos) /*!< UMCTL2_T::ADDRMAP3: addrmap_col_b6 Mask*/ + +#define UMCTL2_ADDRMAP3_addrmap_col_b7_Pos (8) /*!< UMCTL2_T::ADDRMAP3: addrmap_col_b7 Position*/ +#define UMCTL2_ADDRMAP3_addrmap_col_b7_Msk (0x1ful << UMCTL2_ADDRMAP3_addrmap_col_b7_Pos) /*!< UMCTL2_T::ADDRMAP3: addrmap_col_b7 Mask*/ + +#define UMCTL2_ADDRMAP3_addrmap_col_b8_Pos (16) /*!< UMCTL2_T::ADDRMAP3: addrmap_col_b8 Position*/ +#define UMCTL2_ADDRMAP3_addrmap_col_b8_Msk (0x1ful << UMCTL2_ADDRMAP3_addrmap_col_b8_Pos) /*!< UMCTL2_T::ADDRMAP3: addrmap_col_b8 Mask*/ + +#define UMCTL2_ADDRMAP3_addrmap_col_b9_Pos (24) /*!< UMCTL2_T::ADDRMAP3: addrmap_col_b9 Position*/ +#define UMCTL2_ADDRMAP3_addrmap_col_b9_Msk (0x1ful << UMCTL2_ADDRMAP3_addrmap_col_b9_Pos) /*!< UMCTL2_T::ADDRMAP3: addrmap_col_b9 Mask*/ + +#define UMCTL2_ADDRMAP4_addrmap_col_b10_Pos (0) /*!< UMCTL2_T::ADDRMAP4: addrmap_col_b10 Position*/ +#define UMCTL2_ADDRMAP4_addrmap_col_b10_Msk (0x1ful << UMCTL2_ADDRMAP4_addrmap_col_b10_Pos) /*!< UMCTL2_T::ADDRMAP4: addrmap_col_b10 Mask*/ + +#define UMCTL2_ADDRMAP4_addrmap_col_b11_Pos (8) /*!< UMCTL2_T::ADDRMAP4: addrmap_col_b11 Position*/ +#define UMCTL2_ADDRMAP4_addrmap_col_b11_Msk (0x1ful << UMCTL2_ADDRMAP4_addrmap_col_b11_Pos) /*!< UMCTL2_T::ADDRMAP4: addrmap_col_b11 Mask*/ + +#define UMCTL2_ADDRMAP5_addrmap_row_b0_Pos (0) /*!< UMCTL2_T::ADDRMAP5: addrmap_row_b0 Position*/ +#define UMCTL2_ADDRMAP5_addrmap_row_b0_Msk (0xful << UMCTL2_ADDRMAP5_addrmap_row_b0_Pos) /*!< UMCTL2_T::ADDRMAP5: addrmap_row_b0 Mask*/ + +#define UMCTL2_ADDRMAP5_addrmap_row_b1_Pos (8) /*!< UMCTL2_T::ADDRMAP5: addrmap_row_b1 Position*/ +#define UMCTL2_ADDRMAP5_addrmap_row_b1_Msk (0xful << UMCTL2_ADDRMAP5_addrmap_row_b1_Pos) /*!< UMCTL2_T::ADDRMAP5: addrmap_row_b1 Mask*/ + +#define UMCTL2_ADDRMAP5_addrmap_row_b2_10_Pos (16) /*!< UMCTL2_T::ADDRMAP5: addrmap_row_b2_10 Position*/ +#define UMCTL2_ADDRMAP5_addrmap_row_b2_10_Msk (0xful << UMCTL2_ADDRMAP5_addrmap_row_b2_10_Pos) /*!< UMCTL2_T::ADDRMAP5: addrmap_row_b2_10 Mask*/ + +#define UMCTL2_ADDRMAP5_addrmap_row_b11_Pos (24) /*!< UMCTL2_T::ADDRMAP5: addrmap_row_b11 Position*/ +#define UMCTL2_ADDRMAP5_addrmap_row_b11_Msk (0xful << UMCTL2_ADDRMAP5_addrmap_row_b11_Pos) /*!< UMCTL2_T::ADDRMAP5: addrmap_row_b11 Mask*/ + +#define UMCTL2_ADDRMAP6_addrmap_row_b12_Pos (0) /*!< UMCTL2_T::ADDRMAP6: addrmap_row_b12 Position*/ +#define UMCTL2_ADDRMAP6_addrmap_row_b12_Msk (0xful << UMCTL2_ADDRMAP6_addrmap_row_b12_Pos) /*!< UMCTL2_T::ADDRMAP6: addrmap_row_b12 Mask*/ + +#define UMCTL2_ADDRMAP6_addrmap_row_b13_Pos (8) /*!< UMCTL2_T::ADDRMAP6: addrmap_row_b13 Position*/ +#define UMCTL2_ADDRMAP6_addrmap_row_b13_Msk (0xful << UMCTL2_ADDRMAP6_addrmap_row_b13_Pos) /*!< UMCTL2_T::ADDRMAP6: addrmap_row_b13 Mask*/ + +#define UMCTL2_ADDRMAP6_addrmap_row_b14_Pos (16) /*!< UMCTL2_T::ADDRMAP6: addrmap_row_b14 Position*/ +#define UMCTL2_ADDRMAP6_addrmap_row_b14_Msk (0xful << UMCTL2_ADDRMAP6_addrmap_row_b14_Pos) /*!< UMCTL2_T::ADDRMAP6: addrmap_row_b14 Mask*/ + +#define UMCTL2_ADDRMAP6_addrmap_row_b15_Pos (24) /*!< UMCTL2_T::ADDRMAP6: addrmap_row_b15 Position*/ +#define UMCTL2_ADDRMAP6_addrmap_row_b15_Msk (0xful << UMCTL2_ADDRMAP6_addrmap_row_b15_Pos) /*!< UMCTL2_T::ADDRMAP6: addrmap_row_b15 Mask*/ + +#define UMCTL2_ADDRMAP9_addrmap_row_b2_Pos (0) /*!< UMCTL2_T::ADDRMAP9: addrmap_row_b2 Position*/ +#define UMCTL2_ADDRMAP9_addrmap_row_b2_Msk (0xful << UMCTL2_ADDRMAP9_addrmap_row_b2_Pos) /*!< UMCTL2_T::ADDRMAP9: addrmap_row_b2 Mask*/ + +#define UMCTL2_ADDRMAP9_addrmap_row_b3_Pos (8) /*!< UMCTL2_T::ADDRMAP9: addrmap_row_b3 Position*/ +#define UMCTL2_ADDRMAP9_addrmap_row_b3_Msk (0xful << UMCTL2_ADDRMAP9_addrmap_row_b3_Pos) /*!< UMCTL2_T::ADDRMAP9: addrmap_row_b3 Mask*/ + +#define UMCTL2_ADDRMAP9_addrmap_row_b4_Pos (16) /*!< UMCTL2_T::ADDRMAP9: addrmap_row_b4 Position*/ +#define UMCTL2_ADDRMAP9_addrmap_row_b4_Msk (0xful << UMCTL2_ADDRMAP9_addrmap_row_b4_Pos) /*!< UMCTL2_T::ADDRMAP9: addrmap_row_b4 Mask*/ + +#define UMCTL2_ADDRMAP9_addrmap_row_b5_Pos (24) /*!< UMCTL2_T::ADDRMAP9: addrmap_row_b5 Position*/ +#define UMCTL2_ADDRMAP9_addrmap_row_b5_Msk (0xful << UMCTL2_ADDRMAP9_addrmap_row_b5_Pos) /*!< UMCTL2_T::ADDRMAP9: addrmap_row_b5 Mask*/ + +#define UMCTL2_ADDRMAP10_addrmap_row_b6_Pos (0) /*!< UMCTL2_T::ADDRMAP10: addrmap_row_b6 Position*/ +#define UMCTL2_ADDRMAP10_addrmap_row_b6_Msk (0xful << UMCTL2_ADDRMAP10_addrmap_row_b6_Pos) /*!< UMCTL2_T::ADDRMAP10: addrmap_row_b6 Mask*/ + +#define UMCTL2_ADDRMAP10_addrmap_row_b7_Pos (8) /*!< UMCTL2_T::ADDRMAP10: addrmap_row_b7 Position*/ +#define UMCTL2_ADDRMAP10_addrmap_row_b7_Msk (0xful << UMCTL2_ADDRMAP10_addrmap_row_b7_Pos) /*!< UMCTL2_T::ADDRMAP10: addrmap_row_b7 Mask*/ + +#define UMCTL2_ADDRMAP10_addrmap_row_b8_Pos (16) /*!< UMCTL2_T::ADDRMAP10: addrmap_row_b8 Position*/ +#define UMCTL2_ADDRMAP10_addrmap_row_b8_Msk (0xful << UMCTL2_ADDRMAP10_addrmap_row_b8_Pos) /*!< UMCTL2_T::ADDRMAP10: addrmap_row_b8 Mask*/ + +#define UMCTL2_ADDRMAP10_addrmap_row_b9_Pos (24) /*!< UMCTL2_T::ADDRMAP10: addrmap_row_b9 Position*/ +#define UMCTL2_ADDRMAP10_addrmap_row_b9_Msk (0xful << UMCTL2_ADDRMAP10_addrmap_row_b9_Pos) /*!< UMCTL2_T::ADDRMAP10: addrmap_row_b9 Mask*/ + +#define UMCTL2_ADDRMAP11_addrmap_row_b10_Pos (0) /*!< UMCTL2_T::ADDRMAP11: addrmap_row_b10 Position*/ +#define UMCTL2_ADDRMAP11_addrmap_row_b10_Msk (0xful << UMCTL2_ADDRMAP11_addrmap_row_b10_Pos) /*!< UMCTL2_T::ADDRMAP11: addrmap_row_b10 Mask*/ + +#define UMCTL2_ODTCFG_rd_odt_delay_Pos (2) /*!< UMCTL2_T::ODTCFG: rd_odt_delay Position*/ +#define UMCTL2_ODTCFG_rd_odt_delay_Msk (0x1ful << UMCTL2_ODTCFG_rd_odt_delay_Pos) /*!< UMCTL2_T::ODTCFG: rd_odt_delay Mask */ + +#define UMCTL2_ODTCFG_rd_odt_hold_Pos (8) /*!< UMCTL2_T::ODTCFG: rd_odt_hold Position */ +#define UMCTL2_ODTCFG_rd_odt_hold_Msk (0xful << UMCTL2_ODTCFG_rd_odt_hold_Pos) /*!< UMCTL2_T::ODTCFG: rd_odt_hold Mask */ + +#define UMCTL2_ODTCFG_wr_odt_delay_Pos (16) /*!< UMCTL2_T::ODTCFG: wr_odt_delay Position*/ +#define UMCTL2_ODTCFG_wr_odt_delay_Msk (0x1ful << UMCTL2_ODTCFG_wr_odt_delay_Pos) /*!< UMCTL2_T::ODTCFG: wr_odt_delay Mask */ + +#define UMCTL2_ODTCFG_wr_odt_hold_Pos (24) /*!< UMCTL2_T::ODTCFG: wr_odt_hold Position */ +#define UMCTL2_ODTCFG_wr_odt_hold_Msk (0xful << UMCTL2_ODTCFG_wr_odt_hold_Pos) /*!< UMCTL2_T::ODTCFG: wr_odt_hold Mask */ + +#define UMCTL2_ODTMAP_rank0_wr_odt_Pos (0) /*!< UMCTL2_T::ODTMAP: rank0_wr_odt Position*/ +#define UMCTL2_ODTMAP_rank0_wr_odt_Msk (0x3ul << UMCTL2_ODTMAP_rank0_wr_odt_Pos) /*!< UMCTL2_T::ODTMAP: rank0_wr_odt Mask */ + +#define UMCTL2_ODTMAP_rank0_rd_odt_Pos (4) /*!< UMCTL2_T::ODTMAP: rank0_rd_odt Position*/ +#define UMCTL2_ODTMAP_rank0_rd_odt_Msk (0x3ul << UMCTL2_ODTMAP_rank0_rd_odt_Pos) /*!< UMCTL2_T::ODTMAP: rank0_rd_odt Mask */ + +#define UMCTL2_ODTMAP_rank1_wr_odt_Pos (8) /*!< UMCTL2_T::ODTMAP: rank1_wr_odt Position*/ +#define UMCTL2_ODTMAP_rank1_wr_odt_Msk (0x3ul << UMCTL2_ODTMAP_rank1_wr_odt_Pos) /*!< UMCTL2_T::ODTMAP: rank1_wr_odt Mask */ + +#define UMCTL2_ODTMAP_rank1_rd_odt_Pos (12) /*!< UMCTL2_T::ODTMAP: rank1_rd_odt Position*/ +#define UMCTL2_ODTMAP_rank1_rd_odt_Msk (0x3ul << UMCTL2_ODTMAP_rank1_rd_odt_Pos) /*!< UMCTL2_T::ODTMAP: rank1_rd_odt Mask */ + +#define UMCTL2_SCHED_prefer_write_Pos (1) /*!< UMCTL2_T::SCHED: prefer_write Position */ +#define UMCTL2_SCHED_prefer_write_Msk (0x1ul << UMCTL2_SCHED_prefer_write_Pos) /*!< UMCTL2_T::SCHED: prefer_write Mask */ + +#define UMCTL2_SCHED_Pageclose_Pos (2) /*!< UMCTL2_T::SCHED: Pageclose Position */ +#define UMCTL2_SCHED_Pageclose_Msk (0x1ul << UMCTL2_SCHED_Pageclose_Pos) /*!< UMCTL2_T::SCHED: Pageclose Mask */ + +#define UMCTL2_SCHED_lpr_num_entries_Pos (8) /*!< UMCTL2_T::SCHED: lpr_num_entries Position*/ +#define UMCTL2_SCHED_lpr_num_entries_Msk (0x1ful << UMCTL2_SCHED_lpr_num_entries_Pos) /*!< UMCTL2_T::SCHED: lpr_num_entries Mask */ + +#define UMCTL2_SCHED_go2critical_hysteresis_Pos (16) /*!< UMCTL2_T::SCHED: go2critical_hysteresis Position*/ +#define UMCTL2_SCHED_go2critical_hysteresis_Msk (0xfful << UMCTL2_SCHED_go2critical_hysteresis_Pos) /*!< UMCTL2_T::SCHED: go2critical_hysteresis Mask*/ + +#define UMCTL2_SCHED_rdwr_idle_gap_Pos (24) /*!< UMCTL2_T::SCHED: rdwr_idle_gap Position*/ +#define UMCTL2_SCHED_rdwr_idle_gap_Msk (0x7ful << UMCTL2_SCHED_rdwr_idle_gap_Pos) /*!< UMCTL2_T::SCHED: rdwr_idle_gap Mask */ + +#define UMCTL2_SCHED1_pageclose_timer_Pos (0) /*!< UMCTL2_T::SCHED1: pageclose_timer Position*/ +#define UMCTL2_SCHED1_pageclose_timer_Msk (0xfful << UMCTL2_SCHED1_pageclose_timer_Pos) /*!< UMCTL2_T::SCHED1: pageclose_timer Mask */ + +#define UMCTL2_PERFHPR1_hpr_max_starve_Pos (0) /*!< UMCTL2_T::PERFHPR1: hpr_max_starve Position*/ +#define UMCTL2_PERFHPR1_hpr_max_starve_Msk (0xfffful << UMCTL2_PERFHPR1_hpr_max_starve_Pos) /*!< UMCTL2_T::PERFHPR1: hpr_max_starve Mask*/ + +#define UMCTL2_PERFHPR1_hpr_xact_run_length_Pos (24) /*!< UMCTL2_T::PERFHPR1: hpr_xact_run_length Position*/ +#define UMCTL2_PERFHPR1_hpr_xact_run_length_Msk (0xfful << UMCTL2_PERFHPR1_hpr_xact_run_length_Pos) /*!< UMCTL2_T::PERFHPR1: hpr_xact_run_length Mask*/ + +#define UMCTL2_PERFLPR1_lpr_max_starve_Pos (0) /*!< UMCTL2_T::PERFLPR1: lpr_max_starve Position*/ +#define UMCTL2_PERFLPR1_lpr_max_starve_Msk (0xfffful << UMCTL2_PERFLPR1_lpr_max_starve_Pos) /*!< UMCTL2_T::PERFLPR1: lpr_max_starve Mask*/ + +#define UMCTL2_PERFLPR1_lpr_xact_run_length_Pos (24) /*!< UMCTL2_T::PERFLPR1: lpr_xact_run_length Position*/ +#define UMCTL2_PERFLPR1_lpr_xact_run_length_Msk (0xfful << UMCTL2_PERFLPR1_lpr_xact_run_length_Pos) /*!< UMCTL2_T::PERFLPR1: lpr_xact_run_length Mask*/ + +#define UMCTL2_PERFWR1_w_max_starve_Pos (0) /*!< UMCTL2_T::PERFWR1: w_max_starve Position*/ +#define UMCTL2_PERFWR1_w_max_starve_Msk (0xfffful << UMCTL2_PERFWR1_w_max_starve_Pos) /*!< UMCTL2_T::PERFWR1: w_max_starve Mask */ + +#define UMCTL2_PERFWR1_w_xact_run_length_Pos (24) /*!< UMCTL2_T::PERFWR1: w_xact_run_length Position*/ +#define UMCTL2_PERFWR1_w_xact_run_length_Msk (0xfful << UMCTL2_PERFWR1_w_xact_run_length_Pos) /*!< UMCTL2_T::PERFWR1: w_xact_run_length Mask*/ + +#define UMCTL2_DBG0_dis_wc_Pos (0) /*!< UMCTL2_T::DBG0: dis_wc Position */ +#define UMCTL2_DBG0_dis_wc_Msk (0x1ul << UMCTL2_DBG0_dis_wc_Pos) /*!< UMCTL2_T::DBG0: dis_wc Mask */ + +#define UMCTL2_DBG0_dis_rd_bypass_Pos (1) /*!< UMCTL2_T::DBG0: dis_rd_bypass Position */ +#define UMCTL2_DBG0_dis_rd_bypass_Msk (0x1ul << UMCTL2_DBG0_dis_rd_bypass_Pos) /*!< UMCTL2_T::DBG0: dis_rd_bypass Mask */ + +#define UMCTL2_DBG0_dis_act_bypass_Pos (2) /*!< UMCTL2_T::DBG0: dis_act_bypass Position*/ +#define UMCTL2_DBG0_dis_act_bypass_Msk (0x1ul << UMCTL2_DBG0_dis_act_bypass_Pos) /*!< UMCTL2_T::DBG0: dis_act_bypass Mask */ + +#define UMCTL2_DBG0_dis_collision_page_opt_Pos (4) /*!< UMCTL2_T::DBG0: dis_collision_page_opt Position*/ +#define UMCTL2_DBG0_dis_collision_page_opt_Msk (0x1ul << UMCTL2_DBG0_dis_collision_page_opt_Pos) /*!< UMCTL2_T::DBG0: dis_collision_page_opt Mask*/ + +#define UMCTL2_DBG0_dis_max_rank_rd_opt_Pos (6) /*!< UMCTL2_T::DBG0: dis_max_rank_rd_opt Position*/ +#define UMCTL2_DBG0_dis_max_rank_rd_opt_Msk (0x1ul << UMCTL2_DBG0_dis_max_rank_rd_opt_Pos) /*!< UMCTL2_T::DBG0: dis_max_rank_rd_opt Mask*/ + +#define UMCTL2_DBG0_dis_max_rank_wr_opt_Pos (7) /*!< UMCTL2_T::DBG0: dis_max_rank_wr_opt Position*/ +#define UMCTL2_DBG0_dis_max_rank_wr_opt_Msk (0x1ul << UMCTL2_DBG0_dis_max_rank_wr_opt_Pos) /*!< UMCTL2_T::DBG0: dis_max_rank_wr_opt Mask*/ + +#define UMCTL2_DBG1_dis_dq_Pos (0) /*!< UMCTL2_T::DBG1: dis_dq Position */ +#define UMCTL2_DBG1_dis_dq_Msk (0x1ul << UMCTL2_DBG1_dis_dq_Pos) /*!< UMCTL2_T::DBG1: dis_dq Mask */ + +#define UMCTL2_DBG1_dis_hif_Pos (1) /*!< UMCTL2_T::DBG1: dis_hif Position */ +#define UMCTL2_DBG1_dis_hif_Msk (0x1ul << UMCTL2_DBG1_dis_hif_Pos) /*!< UMCTL2_T::DBG1: dis_hif Mask */ + +#define UMCTL2_DBGCAM_dbg_hpr_q_depth_Pos (0) /*!< UMCTL2_T::DBGCAM: dbg_hpr_q_depth Position*/ +#define UMCTL2_DBGCAM_dbg_hpr_q_depth_Msk (0x3ful << UMCTL2_DBGCAM_dbg_hpr_q_depth_Pos) /*!< UMCTL2_T::DBGCAM: dbg_hpr_q_depth Mask */ + +#define UMCTL2_DBGCAM_dbg_lpr_q_depth_Pos (8) /*!< UMCTL2_T::DBGCAM: dbg_lpr_q_depth Position*/ +#define UMCTL2_DBGCAM_dbg_lpr_q_depth_Msk (0x3ful << UMCTL2_DBGCAM_dbg_lpr_q_depth_Pos) /*!< UMCTL2_T::DBGCAM: dbg_lpr_q_depth Mask */ + +#define UMCTL2_DBGCAM_dbg_w_q_depth_Pos (16) /*!< UMCTL2_T::DBGCAM: dbg_w_q_depth Position*/ +#define UMCTL2_DBGCAM_dbg_w_q_depth_Msk (0x3ful << UMCTL2_DBGCAM_dbg_w_q_depth_Pos) /*!< UMCTL2_T::DBGCAM: dbg_w_q_depth Mask */ + +#define UMCTL2_DBGCAM_dbg_stall_Pos (24) /*!< UMCTL2_T::DBGCAM: dbg_stall Position */ +#define UMCTL2_DBGCAM_dbg_stall_Msk (0x1ul << UMCTL2_DBGCAM_dbg_stall_Pos) /*!< UMCTL2_T::DBGCAM: dbg_stall Mask */ + +#define UMCTL2_DBGCAM_dbg_rd_q_empty_Pos (25) /*!< UMCTL2_T::DBGCAM: dbg_rd_q_empty Position*/ +#define UMCTL2_DBGCAM_dbg_rd_q_empty_Msk (0x1ul << UMCTL2_DBGCAM_dbg_rd_q_empty_Pos) /*!< UMCTL2_T::DBGCAM: dbg_rd_q_empty Mask */ + +#define UMCTL2_DBGCAM_dbg_wr_q_empty_Pos (26) /*!< UMCTL2_T::DBGCAM: dbg_wr_q_empty Position*/ +#define UMCTL2_DBGCAM_dbg_wr_q_empty_Msk (0x1ul << UMCTL2_DBGCAM_dbg_wr_q_empty_Pos) /*!< UMCTL2_T::DBGCAM: dbg_wr_q_empty Mask */ + +#define UMCTL2_DBGCAM_rd_data_pipeline_empty_Pos (28) /*!< UMCTL2_T::DBGCAM: rd_data_pipeline_empty Position*/ +#define UMCTL2_DBGCAM_rd_data_pipeline_empty_Msk (0x1ul << UMCTL2_DBGCAM_rd_data_pipeline_empty_Pos) /*!< UMCTL2_T::DBGCAM: rd_data_pipeline_empty Mask*/ + +#define UMCTL2_DBGCAM_wr_data_pipeline_empty_Pos (29) /*!< UMCTL2_T::DBGCAM: wr_data_pipeline_empty Position*/ +#define UMCTL2_DBGCAM_wr_data_pipeline_empty_Msk (0x1ul << UMCTL2_DBGCAM_wr_data_pipeline_empty_Pos) /*!< UMCTL2_T::DBGCAM: wr_data_pipeline_empty Mask*/ + +#define UMCTL2_DBGCMD_rank0_refresh_Pos (0) /*!< UMCTL2_T::DBGCMD: rank0_refresh Position*/ +#define UMCTL2_DBGCMD_rank0_refresh_Msk (0x1ul << UMCTL2_DBGCMD_rank0_refresh_Pos) /*!< UMCTL2_T::DBGCMD: rank0_refresh Mask */ + +#define UMCTL2_DBGCMD_rank1_refresh_Pos (1) /*!< UMCTL2_T::DBGCMD: rank1_refresh Position*/ +#define UMCTL2_DBGCMD_rank1_refresh_Msk (0x1ul << UMCTL2_DBGCMD_rank1_refresh_Pos) /*!< UMCTL2_T::DBGCMD: rank1_refresh Mask */ + +#define UMCTL2_DBGCMD_zq_calib_short_Pos (4) /*!< UMCTL2_T::DBGCMD: zq_calib_short Position*/ +#define UMCTL2_DBGCMD_zq_calib_short_Msk (0x1ul << UMCTL2_DBGCMD_zq_calib_short_Pos) /*!< UMCTL2_T::DBGCMD: zq_calib_short Mask */ + +#define UMCTL2_DBGCMD_ctrlupd_Pos (5) /*!< UMCTL2_T::DBGCMD: ctrlupd Position */ +#define UMCTL2_DBGCMD_ctrlupd_Msk (0x1ul << UMCTL2_DBGCMD_ctrlupd_Pos) /*!< UMCTL2_T::DBGCMD: ctrlupd Mask */ + +#define UMCTL2_DBGSTAT_rank0_refresh_busy_Pos (0) /*!< UMCTL2_T::DBGSTAT: rank0_refresh_busy Position*/ +#define UMCTL2_DBGSTAT_rank0_refresh_busy_Msk (0x1ul << UMCTL2_DBGSTAT_rank0_refresh_busy_Pos) /*!< UMCTL2_T::DBGSTAT: rank0_refresh_busy Mask*/ + +#define UMCTL2_DBGSTAT_rank1_refresh_busy_Pos (1) /*!< UMCTL2_T::DBGSTAT: rank1_refresh_busy Position*/ +#define UMCTL2_DBGSTAT_rank1_refresh_busy_Msk (0x1ul << UMCTL2_DBGSTAT_rank1_refresh_busy_Pos) /*!< UMCTL2_T::DBGSTAT: rank1_refresh_busy Mask*/ + +#define UMCTL2_DBGSTAT_zq_calib_short_busy_Pos (4) /*!< UMCTL2_T::DBGSTAT: zq_calib_short_busy Position*/ +#define UMCTL2_DBGSTAT_zq_calib_short_busy_Msk (0x1ul << UMCTL2_DBGSTAT_zq_calib_short_busy_Pos) /*!< UMCTL2_T::DBGSTAT: zq_calib_short_busy Mask*/ + +#define UMCTL2_DBGSTAT_ctrlupd_busy_Pos (5) /*!< UMCTL2_T::DBGSTAT: ctrlupd_busy Position*/ +#define UMCTL2_DBGSTAT_ctrlupd_busy_Msk (0x1ul << UMCTL2_DBGSTAT_ctrlupd_busy_Pos) /*!< UMCTL2_T::DBGSTAT: ctrlupd_busy Mask */ + +#define UMCTL2_SWCTL_sw_done_Pos (0) /*!< UMCTL2_T::SWCTL: sw_done Position */ +#define UMCTL2_SWCTL_sw_done_Msk (0x1ul << UMCTL2_SWCTL_sw_done_Pos) /*!< UMCTL2_T::SWCTL: sw_done Mask */ + +#define UMCTL2_SWSTAT_sw_done_ack_Pos (0) /*!< UMCTL2_T::SWSTAT: sw_done_ack Position */ +#define UMCTL2_SWSTAT_sw_done_ack_Msk (0x1ul << UMCTL2_SWSTAT_sw_done_ack_Pos) /*!< UMCTL2_T::SWSTAT: sw_done_ack Mask */ + +#define UMCTL2_SWCTLSTATIC_sw_static_unlock_Pos (0) /*!< UMCTL2_T::SWCTLSTATIC: sw_static_unlock Position*/ +#define UMCTL2_SWCTLSTATIC_sw_static_unlock_Msk (0x1ul << UMCTL2_SWCTLSTATIC_sw_static_unlock_Pos) /*!< UMCTL2_T::SWCTLSTATIC: sw_static_unlock Mask*/ + +#define UMCTL2_POISONCFG_wr_poison_slverr_en_Pos (0) /*!< UMCTL2_T::POISONCFG: wr_poison_slverr_en Position*/ +#define UMCTL2_POISONCFG_wr_poison_slverr_en_Msk (0x1ul << UMCTL2_POISONCFG_wr_poison_slverr_en_Pos) /*!< UMCTL2_T::POISONCFG: wr_poison_slverr_en Mask*/ + +#define UMCTL2_POISONCFG_wr_poison_intr_en_Pos (4) /*!< UMCTL2_T::POISONCFG: wr_poison_intr_en Position*/ +#define UMCTL2_POISONCFG_wr_poison_intr_en_Msk (0x1ul << UMCTL2_POISONCFG_wr_poison_intr_en_Pos) /*!< UMCTL2_T::POISONCFG: wr_poison_intr_en Mask*/ + +#define UMCTL2_POISONCFG_wr_poison_intr_clr_Pos (8) /*!< UMCTL2_T::POISONCFG: wr_poison_intr_clr Position*/ +#define UMCTL2_POISONCFG_wr_poison_intr_clr_Msk (0x1ul << UMCTL2_POISONCFG_wr_poison_intr_clr_Pos) /*!< UMCTL2_T::POISONCFG: wr_poison_intr_clr Mask*/ + +#define UMCTL2_POISONCFG_rd_poison_slverr_en_Pos (16) /*!< UMCTL2_T::POISONCFG: rd_poison_slverr_en Position*/ +#define UMCTL2_POISONCFG_rd_poison_slverr_en_Msk (0x1ul << UMCTL2_POISONCFG_rd_poison_slverr_en_Pos) /*!< UMCTL2_T::POISONCFG: rd_poison_slverr_en Mask*/ + +#define UMCTL2_POISONCFG_rd_poison_intr_en_Pos (20) /*!< UMCTL2_T::POISONCFG: rd_poison_intr_en Position*/ +#define UMCTL2_POISONCFG_rd_poison_intr_en_Msk (0x1ul << UMCTL2_POISONCFG_rd_poison_intr_en_Pos) /*!< UMCTL2_T::POISONCFG: rd_poison_intr_en Mask*/ + +#define UMCTL2_POISONCFG_rd_poison_intr_clr_Pos (24) /*!< UMCTL2_T::POISONCFG: rd_poison_intr_clr Position*/ +#define UMCTL2_POISONCFG_rd_poison_intr_clr_Msk (0x1ul << UMCTL2_POISONCFG_rd_poison_intr_clr_Pos) /*!< UMCTL2_T::POISONCFG: rd_poison_intr_clr Mask*/ + +#define UMCTL2_POISONSTAT_wr_poison_intr_0_Pos (0) /*!< UMCTL2_T::POISONSTAT: wr_poison_intr_0 Position*/ +#define UMCTL2_POISONSTAT_wr_poison_intr_0_Msk (0x1ul << UMCTL2_POISONSTAT_wr_poison_intr_0_Pos) /*!< UMCTL2_T::POISONSTAT: wr_poison_intr_0 Mask*/ + +#define UMCTL2_POISONSTAT_wr_poison_intr_1_Pos (1) /*!< UMCTL2_T::POISONSTAT: wr_poison_intr_1 Position*/ +#define UMCTL2_POISONSTAT_wr_poison_intr_1_Msk (0x1ul << UMCTL2_POISONSTAT_wr_poison_intr_1_Pos) /*!< UMCTL2_T::POISONSTAT: wr_poison_intr_1 Mask*/ + +#define UMCTL2_POISONSTAT_wr_poison_intr_2_Pos (2) /*!< UMCTL2_T::POISONSTAT: wr_poison_intr_2 Position*/ +#define UMCTL2_POISONSTAT_wr_poison_intr_2_Msk (0x1ul << UMCTL2_POISONSTAT_wr_poison_intr_2_Pos) /*!< UMCTL2_T::POISONSTAT: wr_poison_intr_2 Mask*/ + +#define UMCTL2_POISONSTAT_wr_poison_intr_3_Pos (3) /*!< UMCTL2_T::POISONSTAT: wr_poison_intr_3 Position*/ +#define UMCTL2_POISONSTAT_wr_poison_intr_3_Msk (0x1ul << UMCTL2_POISONSTAT_wr_poison_intr_3_Pos) /*!< UMCTL2_T::POISONSTAT: wr_poison_intr_3 Mask*/ + +#define UMCTL2_POISONSTAT_wr_poison_intr_4_Pos (4) /*!< UMCTL2_T::POISONSTAT: wr_poison_intr_4 Position*/ +#define UMCTL2_POISONSTAT_wr_poison_intr_4_Msk (0x1ul << UMCTL2_POISONSTAT_wr_poison_intr_4_Pos) /*!< UMCTL2_T::POISONSTAT: wr_poison_intr_4 Mask*/ + +#define UMCTL2_POISONSTAT_wr_poison_intr_5_Pos (5) /*!< UMCTL2_T::POISONSTAT: wr_poison_intr_5 Position*/ +#define UMCTL2_POISONSTAT_wr_poison_intr_5_Msk (0x1ul << UMCTL2_POISONSTAT_wr_poison_intr_5_Pos) /*!< UMCTL2_T::POISONSTAT: wr_poison_intr_5 Mask*/ + +#define UMCTL2_POISONSTAT_wr_poison_intr_6_Pos (6) /*!< UMCTL2_T::POISONSTAT: wr_poison_intr_6 Position*/ +#define UMCTL2_POISONSTAT_wr_poison_intr_6_Msk (0x1ul << UMCTL2_POISONSTAT_wr_poison_intr_6_Pos) /*!< UMCTL2_T::POISONSTAT: wr_poison_intr_6 Mask*/ + +#define UMCTL2_POISONSTAT_wr_poison_intr_7_Pos (7) /*!< UMCTL2_T::POISONSTAT: wr_poison_intr_7 Position*/ +#define UMCTL2_POISONSTAT_wr_poison_intr_7_Msk (0x1ul << UMCTL2_POISONSTAT_wr_poison_intr_7_Pos) /*!< UMCTL2_T::POISONSTAT: wr_poison_intr_7 Mask*/ + +#define UMCTL2_POISONSTAT_rd_poison_intr_0_Pos (16) /*!< UMCTL2_T::POISONSTAT: rd_poison_intr_0 Position*/ +#define UMCTL2_POISONSTAT_rd_poison_intr_0_Msk (0x1ul << UMCTL2_POISONSTAT_rd_poison_intr_0_Pos) /*!< UMCTL2_T::POISONSTAT: rd_poison_intr_0 Mask*/ + +#define UMCTL2_POISONSTAT_rd_poison_intr_1_Pos (17) /*!< UMCTL2_T::POISONSTAT: rd_poison_intr_1 Position*/ +#define UMCTL2_POISONSTAT_rd_poison_intr_1_Msk (0x1ul << UMCTL2_POISONSTAT_rd_poison_intr_1_Pos) /*!< UMCTL2_T::POISONSTAT: rd_poison_intr_1 Mask*/ + +#define UMCTL2_POISONSTAT_rd_poison_intr_2_Pos (18) /*!< UMCTL2_T::POISONSTAT: rd_poison_intr_2 Position*/ +#define UMCTL2_POISONSTAT_rd_poison_intr_2_Msk (0x1ul << UMCTL2_POISONSTAT_rd_poison_intr_2_Pos) /*!< UMCTL2_T::POISONSTAT: rd_poison_intr_2 Mask*/ + +#define UMCTL2_POISONSTAT_rd_poison_intr_3_Pos (19) /*!< UMCTL2_T::POISONSTAT: rd_poison_intr_3 Position*/ +#define UMCTL2_POISONSTAT_rd_poison_intr_3_Msk (0x1ul << UMCTL2_POISONSTAT_rd_poison_intr_3_Pos) /*!< UMCTL2_T::POISONSTAT: rd_poison_intr_3 Mask*/ + +#define UMCTL2_POISONSTAT_rd_poison_intr_4_Pos (20) /*!< UMCTL2_T::POISONSTAT: rd_poison_intr_4 Position*/ +#define UMCTL2_POISONSTAT_rd_poison_intr_4_Msk (0x1ul << UMCTL2_POISONSTAT_rd_poison_intr_4_Pos) /*!< UMCTL2_T::POISONSTAT: rd_poison_intr_4 Mask*/ + +#define UMCTL2_POISONSTAT_rd_poison_intr_5_Pos (21) /*!< UMCTL2_T::POISONSTAT: rd_poison_intr_5 Position*/ +#define UMCTL2_POISONSTAT_rd_poison_intr_5_Msk (0x1ul << UMCTL2_POISONSTAT_rd_poison_intr_5_Pos) /*!< UMCTL2_T::POISONSTAT: rd_poison_intr_5 Mask*/ + +#define UMCTL2_POISONSTAT_rd_poison_intr_6_Pos (22) /*!< UMCTL2_T::POISONSTAT: rd_poison_intr_6 Position*/ +#define UMCTL2_POISONSTAT_rd_poison_intr_6_Msk (0x1ul << UMCTL2_POISONSTAT_rd_poison_intr_6_Pos) /*!< UMCTL2_T::POISONSTAT: rd_poison_intr_6 Mask*/ + +#define UMCTL2_POISONSTAT_rd_poison_intr_7_Pos (23) /*!< UMCTL2_T::POISONSTAT: rd_poison_intr_7 Position*/ +#define UMCTL2_POISONSTAT_rd_poison_intr_7_Msk (0x1ul << UMCTL2_POISONSTAT_rd_poison_intr_7_Pos) /*!< UMCTL2_T::POISONSTAT: rd_poison_intr_7 Mask*/ + +#define UMCTL2_PSTAT_rd_port_busy_0_Pos (0) /*!< UMCTL2_T::PSTAT: rd_port_busy_0 Position*/ +#define UMCTL2_PSTAT_rd_port_busy_0_Msk (0x1ul << UMCTL2_PSTAT_rd_port_busy_0_Pos) /*!< UMCTL2_T::PSTAT: rd_port_busy_0 Mask */ + +#define UMCTL2_PSTAT_rd_port_busy_1_Pos (1) /*!< UMCTL2_T::PSTAT: rd_port_busy_1 Position*/ +#define UMCTL2_PSTAT_rd_port_busy_1_Msk (0x1ul << UMCTL2_PSTAT_rd_port_busy_1_Pos) /*!< UMCTL2_T::PSTAT: rd_port_busy_1 Mask */ + +#define UMCTL2_PSTAT_rd_port_busy_2_Pos (2) /*!< UMCTL2_T::PSTAT: rd_port_busy_2 Position*/ +#define UMCTL2_PSTAT_rd_port_busy_2_Msk (0x1ul << UMCTL2_PSTAT_rd_port_busy_2_Pos) /*!< UMCTL2_T::PSTAT: rd_port_busy_2 Mask */ + +#define UMCTL2_PSTAT_rd_port_busy_3_Pos (3) /*!< UMCTL2_T::PSTAT: rd_port_busy_3 Position*/ +#define UMCTL2_PSTAT_rd_port_busy_3_Msk (0x1ul << UMCTL2_PSTAT_rd_port_busy_3_Pos) /*!< UMCTL2_T::PSTAT: rd_port_busy_3 Mask */ + +#define UMCTL2_PSTAT_rd_port_busy_4_Pos (4) /*!< UMCTL2_T::PSTAT: rd_port_busy_4 Position*/ +#define UMCTL2_PSTAT_rd_port_busy_4_Msk (0x1ul << UMCTL2_PSTAT_rd_port_busy_4_Pos) /*!< UMCTL2_T::PSTAT: rd_port_busy_4 Mask */ + +#define UMCTL2_PSTAT_rd_port_busy_5_Pos (5) /*!< UMCTL2_T::PSTAT: rd_port_busy_5 Position*/ +#define UMCTL2_PSTAT_rd_port_busy_5_Msk (0x1ul << UMCTL2_PSTAT_rd_port_busy_5_Pos) /*!< UMCTL2_T::PSTAT: rd_port_busy_5 Mask */ + +#define UMCTL2_PSTAT_rd_port_busy_6_Pos (6) /*!< UMCTL2_T::PSTAT: rd_port_busy_6 Position*/ +#define UMCTL2_PSTAT_rd_port_busy_6_Msk (0x1ul << UMCTL2_PSTAT_rd_port_busy_6_Pos) /*!< UMCTL2_T::PSTAT: rd_port_busy_6 Mask */ + +#define UMCTL2_PSTAT_rd_port_busy_7_Pos (7) /*!< UMCTL2_T::PSTAT: rd_port_busy_7 Position*/ +#define UMCTL2_PSTAT_rd_port_busy_7_Msk (0x1ul << UMCTL2_PSTAT_rd_port_busy_7_Pos) /*!< UMCTL2_T::PSTAT: rd_port_busy_7 Mask */ + +#define UMCTL2_PSTAT_wr_port_busy_0_Pos (16) /*!< UMCTL2_T::PSTAT: wr_port_busy_0 Position*/ +#define UMCTL2_PSTAT_wr_port_busy_0_Msk (0x1ul << UMCTL2_PSTAT_wr_port_busy_0_Pos) /*!< UMCTL2_T::PSTAT: wr_port_busy_0 Mask */ + +#define UMCTL2_PSTAT_wr_port_busy_1_Pos (17) /*!< UMCTL2_T::PSTAT: wr_port_busy_1 Position*/ +#define UMCTL2_PSTAT_wr_port_busy_1_Msk (0x1ul << UMCTL2_PSTAT_wr_port_busy_1_Pos) /*!< UMCTL2_T::PSTAT: wr_port_busy_1 Mask */ + +#define UMCTL2_PSTAT_wr_port_busy_2_Pos (18) /*!< UMCTL2_T::PSTAT: wr_port_busy_2 Position*/ +#define UMCTL2_PSTAT_wr_port_busy_2_Msk (0x1ul << UMCTL2_PSTAT_wr_port_busy_2_Pos) /*!< UMCTL2_T::PSTAT: wr_port_busy_2 Mask */ + +#define UMCTL2_PSTAT_wr_port_busy_3_Pos (19) /*!< UMCTL2_T::PSTAT: wr_port_busy_3 Position*/ +#define UMCTL2_PSTAT_wr_port_busy_3_Msk (0x1ul << UMCTL2_PSTAT_wr_port_busy_3_Pos) /*!< UMCTL2_T::PSTAT: wr_port_busy_3 Mask */ + +#define UMCTL2_PSTAT_wr_port_busy_4_Pos (20) /*!< UMCTL2_T::PSTAT: wr_port_busy_4 Position*/ +#define UMCTL2_PSTAT_wr_port_busy_4_Msk (0x1ul << UMCTL2_PSTAT_wr_port_busy_4_Pos) /*!< UMCTL2_T::PSTAT: wr_port_busy_4 Mask */ + +#define UMCTL2_PSTAT_wr_port_busy_5_Pos (21) /*!< UMCTL2_T::PSTAT: wr_port_busy_5 Position*/ +#define UMCTL2_PSTAT_wr_port_busy_5_Msk (0x1ul << UMCTL2_PSTAT_wr_port_busy_5_Pos) /*!< UMCTL2_T::PSTAT: wr_port_busy_5 Mask */ + +#define UMCTL2_PSTAT_wr_port_busy_6_Pos (22) /*!< UMCTL2_T::PSTAT: wr_port_busy_6 Position*/ +#define UMCTL2_PSTAT_wr_port_busy_6_Msk (0x1ul << UMCTL2_PSTAT_wr_port_busy_6_Pos) /*!< UMCTL2_T::PSTAT: wr_port_busy_6 Mask */ + +#define UMCTL2_PSTAT_wr_port_busy_7_Pos (23) /*!< UMCTL2_T::PSTAT: wr_port_busy_7 Position*/ +#define UMCTL2_PSTAT_wr_port_busy_7_Msk (0x1ul << UMCTL2_PSTAT_wr_port_busy_7_Pos) /*!< UMCTL2_T::PSTAT: wr_port_busy_7 Mask */ + +#define UMCTL2_PCCFG_go2critical_en_Pos (0) /*!< UMCTL2_T::PCCFG: go2critical_en Position*/ +#define UMCTL2_PCCFG_go2critical_en_Msk (0x1ul << UMCTL2_PCCFG_go2critical_en_Pos) /*!< UMCTL2_T::PCCFG: go2critical_en Mask */ + +#define UMCTL2_PCCFG_pagematch_limit_Pos (4) /*!< UMCTL2_T::PCCFG: pagematch_limit Position*/ +#define UMCTL2_PCCFG_pagematch_limit_Msk (0x1ul << UMCTL2_PCCFG_pagematch_limit_Pos) /*!< UMCTL2_T::PCCFG: pagematch_limit Mask */ + +#define UMCTL2_PCCFG_bl_exp_mode_Pos (8) /*!< UMCTL2_T::PCCFG: bl_exp_mode Position */ +#define UMCTL2_PCCFG_bl_exp_mode_Msk (0x1ul << UMCTL2_PCCFG_bl_exp_mode_Pos) /*!< UMCTL2_T::PCCFG: bl_exp_mode Mask */ + +#define UMCTL2_PCFGR_0_rd_port_priority_Pos (0) /*!< UMCTL2_T::PCFGR_0: rd_port_priority Position */ +#define UMCTL2_PCFGR_0_rd_port_priority_Msk (0x3fful << UMCTL2_PCFGR_0_rd_port_priority_Pos) /*!< UMCTL2_T::PCFGR_0: rd_port_priority Mask */ + +#define UMCTL2_PCFGR_0_rd_port_aging_en_Pos (12) /*!< UMCTL2_T::PCFGR_0: rd_port_aging_en Position */ +#define UMCTL2_PCFGR_0_rd_port_aging_en_Msk (0x1ul << UMCTL2_PCFGR_0_rd_port_aging_en_Pos) /*!< UMCTL2_T::PCFGR_0: rd_port_aging_en Mask */ + +#define UMCTL2_PCFGR_0_rd_port_urgent_en_Pos (13) /*!< UMCTL2_T::PCFGR_0: rd_port_urgent_en Position*/ +#define UMCTL2_PCFGR_0_rd_port_urgent_en_Msk (0x1ul << UMCTL2_PCFGR_0_rd_port_urgent_en_Pos) /*!< UMCTL2_T::PCFGR_0: rd_port_urgent_en Mask */ + +#define UMCTL2_PCFGR_0_rd_port_pagematch_en_Pos (14) /*!< UMCTL2_T::PCFGR_0: rd_port_pagematch_en Position*/ +#define UMCTL2_PCFGR_0_rd_port_pagematch_en_Msk (0x1ul << UMCTL2_PCFGR_0_rd_port_pagematch_en_Pos) /*!< UMCTL2_T::PCFGR_0: rd_port_pagematch_en Mask */ + +#define UMCTL2_PCFGR_0_rdwr_ordered_en_Pos (16) /*!< UMCTL2_T::PCFGR_0: rdwr_ordered_en Position */ +#define UMCTL2_PCFGR_00_rdwr_ordered_en_Msk (0x1ul << UMCTL2_PCFGR_0_rdwr_ordered_en_Pos) /*!< UMCTL2_T::PCFGR_0: rdwr_ordered_en Mask */ + +#define UMCTL2_PCFGW_0_wr_port_priority_Pos (0) /*!< UMCTL2_T::PCFGW_0: wr_port_priority Position */ +#define UMCTL2_PCFGW_0_wr_port_priority_Msk (0x3fful << UMCTL2_PCFGW_0_wr_port_priority_Pos) /*!< UMCTL2_T::PCFGW_0: wr_port_priority Mask */ + +#define UMCTL2_PCFGW_0_wr_port_aging_en_Pos (12) /*!< UMCTL2_T::PCFGW_0: wr_port_aging_en Position */ +#define UMCTL2_PCFGW_0_wr_port_aging_en_Msk (0x1ul << UMCTL2_PCFGW_0_wr_port_aging_en_Pos) /*!< UMCTL2_T::PCFGW_0: wr_port_aging_en Mask */ + +#define UMCTL2_PCFGW_0_wr_port_urgent_en_Pos (13) /*!< UMCTL2_T::PCFGW_0: wr_port_urgent_en Position*/ +#define UMCTL2_PCFGW_0_wr_port_urgent_en_Msk (0x1ul << UMCTL2_PCFGW_0_wr_port_urgent_en_Pos) /*!< UMCTL2_T::PCFGW_0: wr_port_urgent_en Mask */ + +#define UMCTL2_PCFGW_0_wr_port_pagematch_en_Pos (14) /*!< UMCTL2_T::PCFGW_0: wr_port_pagematch_en Position*/ +#define UMCTL2_PCFGW_0_wr_port_pagematch_en_Msk (0x1ul << UMCTL2_PCFGW_0_wr_port_pagematch_en_Pos) /*!< UMCTL2_T::PCFGW_0: wr_port_pagematch_en Mask */ + +#define UMCTL2_PCTRL_0_port_en_Pos (0) /*!< UMCTL2_T::PCTRL_0: port_en Position */ +#define UMCTL2_PCTRL_0_port_en_Msk (0x1ul << UMCTL2_PCTRL_0_port_en_Pos) /*!< UMCTL2_T::PCTRL_0: port_en Mask */ + +#define UMCTL2_PCFGQOS0_0_rqos_map_level1_Pos (0) /*!< UMCTL2_T::PCFGQOS0_0: rqos_map_level1 Position */ +#define UMCTL2_PCFGQOS0_0_rqos_map_level1_Msk (0xful << UMCTL2_PCFGQOS0_0_rqos_map_level1_Pos) /*!< UMCTL2_T::PCFGQOS0_0: rqos_map_level1 Mask */ + +#define UMCTL2_PCFGQOS0_0_rqos_map_region0_Pos (16) /*!< UMCTL2_T::PCFGQOS0_0: rqos_map_region0 Position */ +#define UMCTL2_PCFGQOS0_0_rqos_map_region0_Msk (0x3ul << UMCTL2_PCFGQOS0_0_rqos_map_region0_Pos) /*!< UMCTL2_T::PCFGQOS0_0: rqos_map_region0 Mask */ + +#define UMCTL2_PCFGQOS0_0_rqos_map_region1_Pos (20) /*!< UMCTL2_T::0: rqos_map_region1 Position */ +#define UMCTL2_PCFGQOS0_0_rqos_map_region1_Msk (0x3ul << UMCTL2_PCFGQOS0_0_rqos_map_region1_Pos) /*!< UMCTL2_T::0: rqos_map_region1 Mask */ + +#define UMCTL2_PCFGR_1_rd_port_priority_Pos (0) /*!< UMCTL2_T::PCFGR_1: rd_port_priority Position */ +#define UMCTL2_PCFGR_1_rd_port_priority_Msk (0x3fful << UMCTL2_PCFGR_1_rd_port_priority_Pos) /*!< UMCTL2_T::PCFGR_1: rd_port_priority Mask */ + +#define UMCTL2_PCFGR_1_rd_port_aging_en_Pos (12) /*!< UMCTL2_T::PCFGR_1: rd_port_aging_en Position */ +#define UMCTL2_PCFGR_1_rd_port_aging_en_Msk (0x1ul << UMCTL2_PCFGR_1_rd_port_aging_en_Pos) /*!< UMCTL2_T::PCFGR_1: rd_port_aging_en Mask */ + +#define UMCTL2_PCFGR_1_rd_port_urgent_en_Pos (13) /*!< UMCTL2_T::PCFGR_1: rd_port_urgent_en Position*/ +#define UMCTL2_PCFGR_1_rd_port_urgent_en_Msk (0x1ul << UMCTL2_PCFGR_1_rd_port_urgent_en_Pos) /*!< UMCTL2_T::PCFGR_1: rd_port_urgent_en Mask */ + +#define UMCTL2_PCFGR_1_rd_port_pagematch_en_Pos (14) /*!< UMCTL2_T::PCFGR_1: rd_port_pagematch_en Position*/ +#define UMCTL2_PCFGR_1_rd_port_pagematch_en_Msk (0x1ul << UMCTL2_PCFGR_1_rd_port_pagematch_en_Pos) /*!< UMCTL2_T::PCFGR_1: rd_port_pagematch_en Mask */ + +#define UMCTL2_PCFGR_1_rdwr_ordered_en_Pos (16) /*!< UMCTL2_T::PCFGR_1: rdwr_ordered_en Position */ +#define UMCTL2_PCFGR_1_rdwr_ordered_en_Msk (0x1ul << UMCTL2_PCFGR_1_rdwr_ordered_en_Pos) /*!< UMCTL2_T::PCFGR_1: rdwr_ordered_en Mask */ + +#define UMCTL2_PCFGW_1_wr_port_priority_Pos (0) /*!< UMCTL2_T::PCFGW_1: wr_port_priority Position */ +#define UMCTL2_PCFGW_1_wr_port_priority_Msk (0x3fful << UMCTL2_PCFGW_1_wr_port_priority_Pos) /*!< UMCTL2_T::PCFGW_1: wr_port_priority Mask */ + +#define UMCTL2_PCFGW_1_wr_port_aging_en_Pos (12) /*!< UMCTL2_T::PCFGW_1: wr_port_aging_en Position */ +#define UMCTL2_PCFGW_1_wr_port_aging_en_Msk (0x1ul << UMCTL2_PCFGW_1_wr_port_aging_en_Pos) /*!< UMCTL2_T::PCFGW_1: wr_port_aging_en Mask */ + +#define UMCTL2_PCFGW_1_wr_port_urgent_en_Pos (13) /*!< UMCTL2_T::PCFGW_1: wr_port_urgent_en Position*/ +#define UMCTL2_PCFGW_1_wr_port_urgent_en_Msk (0x1ul << UMCTL2_PCFGW_1_wr_port_urgent_en_Pos) /*!< UMCTL2_T::PCFGW_1: wr_port_urgent_en Mask */ + +#define UMCTL2_PCFGW_1_wr_port_pagematch_en_Pos (14) /*!< UMCTL2_T::PCFGW_1: wr_port_pagematch_en Position*/ +#define UMCTL2_PCFGW_1_wr_port_pagematch_en_Msk (0x1ul << UMCTL2_PCFGW_1_wr_port_pagematch_en_Pos) /*!< UMCTL2_T::PCFGW_1: wr_port_pagematch_en Mask */ + +#define UMCTL2_PCTRL_1_port_en_Pos (0) /*!< UMCTL2_T::PCTRL_1: port_en Position */ +#define UMCTL2_PCTRL_1_port_en_Msk (0x1ul << UMCTL2_PCTRL_1_port_en_Pos) /*!< UMCTL2_T::PCTRL_1: port_en Mask */ + +#define UMCTL2_PCFGQOS0_1_rqos_map_level1_Pos (0) /*!< UMCTL2_T::PCFGQOS0_1: rqos_map_level1 Position */ +#define UMCTL2_PCFGQOS0_1_rqos_map_level1_Msk (0xful << UMCTL2_PCFGQOS0_1_rqos_map_level1_Pos) /*!< UMCTL2_T::PCFGQOS0_1: rqos_map_level1 Mask */ + +#define UMCTL2_PCFGQOS0_1_rqos_map_region0_Pos (16) /*!< UMCTL2_T::PCFGQOS0_1: rqos_map_region0 Position */ +#define UMCTL2_PCFGQOS0_1_rqos_map_region0_Msk (0x3ul << UMCTL2_PCFGQOS0_1_rqos_map_region0_Pos) /*!< UMCTL2_T::PCFGQOS0_1: rqos_map_region0 Mask */ + +#define UMCTL2_PCFGQOS0_1_rqos_map_region1_Pos (20) /*!< UMCTL2_T::PCFGQOS0_1: rqos_map_region1 Position */ +#define UMCTL2_PCFGQOS0_1_rqos_map_region1_Msk (0x3ul << UMCTL2_PCFGQOS0_1_rqos_map_region1_Pos) /*!< UMCTL2_T::PCFGQOS0_1: rqos_map_region1 Mask */ + +#define UMCTL2_PCFGR_2_rd_port_priority_Pos (0) /*!< UMCTL2_T::PCFGR_2: rd_port_priority Position */ +#define UMCTL2_PCFGR_2_rd_port_priority_Msk (0x3fful << UMCTL2_PCFGR_2_rd_port_priority_Pos) /*!< UMCTL2_T::PCFGR_2: rd_port_priority Mask */ + +#define UMCTL2_PCFGR_2_rd_port_aging_en_Pos (12) /*!< UMCTL2_T::PCFGR_2: rd_port_aging_en Position */ +#define UMCTL2_PCFGR_2_rd_port_aging_en_Msk (0x1ul << UMCTL2_PCFGR_2_rd_port_aging_en_Pos) /*!< UMCTL2_T::PCFGR_2: rd_port_aging_en Mask */ + +#define UMCTL2_PCFGR_2_rd_port_urgent_en_Pos (13) /*!< UMCTL2_T::PCFGR_2: rd_port_urgent_en Position*/ +#define UMCTL2_PCFGR_2_rd_port_urgent_en_Msk (0x1ul << UMCTL2_PCFGR_2_rd_port_urgent_en_Pos) /*!< UMCTL2_T::PCFGR_2: rd_port_urgent_en Mask */ + +#define UMCTL2_PCFGR_2_rd_port_pagematch_en_Pos (14) /*!< UMCTL2_T::PCFGR_2: rd_port_pagematch_en Position*/ +#define UMCTL2_PCFGR_2_rd_port_pagematch_en_Msk (0x1ul << UMCTL2_PCFGR_2_rd_port_pagematch_en_Pos) /*!< UMCTL2_T::PCFGR_2: rd_port_pagematch_en Mask */ + +#define UMCTL2_PCFGR_2_rdwr_ordered_en_Pos (16) /*!< UMCTL2_T::2: rdwr_ordered_en Position */ +#define UMCTL2_PCFGR_2_rdwr_ordered_en_Msk (0x1ul << UMCTL2_PCFGR_2_rdwr_ordered_en_Pos) /*!< UMCTL2_T::2: rdwr_ordered_en Mask */ + +#define UMCTL2_PCFGW_2_wr_port_priority_Pos (0) /*!< UMCTL2_T::PCFGW_2: wr_port_priority Position */ +#define UMCTL2_PCFGW_2_wr_port_priority_Msk (0x3fful << UMCTL2_PCFGW_2_wr_port_priority_Pos) /*!< UMCTL2_T::PCFGW_2: wr_port_priority Mask */ + +#define UMCTL2_PCFGW_2_wr_port_aging_en_Pos (12) /*!< UMCTL2_T::PCFGW_2: wr_port_aging_en Position */ +#define UMCTL2_PCFGW_2_wr_port_aging_en_Msk (0x1ul << UMCTL2_PCFGW_2_wr_port_aging_en_Pos) /*!< UMCTL2_T::PCFGW_2: wr_port_aging_en Mask */ + +#define UMCTL2_PCFGW_2_wr_port_urgent_en_Pos (13) /*!< UMCTL2_T::PCFGW_2: wr_port_urgent_en Position*/ +#define UMCTL2_PCFGW_2_wr_port_urgent_en_Msk (0x1ul << UMCTL2_PCFGW_2_wr_port_urgent_en_Pos) /*!< UMCTL2_T::PCFGW_2: wr_port_urgent_en Mask */ + +#define UMCTL2_PCFGW_2_wr_port_pagematch_en_Pos (14) /*!< UMCTL2_T::PCFGW_2: wr_port_pagematch_en Position*/ +#define UMCTL2_PCFGW_2_wr_port_pagematch_en_Msk (0x1ul << UMCTL2_PCFGW_2_wr_port_pagematch_en_Pos) /*!< UMCTL2_T::PCFGW_2: wr_port_pagematch_en Mask */ + +#define UMCTL2_PCTRL_2_port_en_Pos (0) /*!< UMCTL2_T::PCTRL_2: port_en Position */ +#define UMCTL2_PCTRL_2_port_en_Msk (0x1ul << UMCTL2_PCTRL_2_port_en_Pos) /*!< UMCTL2_T::PCTRL_2: port_en Mask */ + +#define UMCTL2_PCFGQOS0_2_rqos_map_level1_Pos (0) /*!< UMCTL2_T::PCFGQOS0_2: rqos_map_level1 Position */ +#define UMCTL2_PCFGQOS0_2_rqos_map_level1_Msk (0xful << UMCTL2_PCFGQOS0_2_rqos_map_level1_Pos) /*!< UMCTL2_T::PCFGQOS0_2: rqos_map_level1 Mask */ + +#define UMCTL2_PCFGQOS0_2_rqos_map_region0_Pos (16) /*!< UMCTL2_T::PCFGQOS0_2: rqos_map_region0 Position */ +#define UMCTL2_PCFGQOS0_2_rqos_map_region0_Msk (0x3ul << UMCTL2_PCFGQOS0_2_rqos_map_region0_Pos) /*!< UMCTL2_T::PCFGQOS0_2: rqos_map_region0 Mask */ + +#define UMCTL2_PCFGQOS0_2_rqos_map_region1_Pos (20) /*!< UMCTL2_T::PCFGQOS0_2: rqos_map_region1 Position */ +#define UMCTL2_PCFGQOS0_2_rqos_map_region1_Msk (0x3ul << UMCTL2_PCFGQOS0_2_rqos_map_region1_Pos) /*!< UMCTL2_T::PCFGQOS0_2: rqos_map_region1 Mask */ + +#define UMCTL2_PCFGR_3_rd_port_priority_Pos (0) /*!< UMCTL2_T::PCFGR_3: rd_port_priority Position */ +#define UMCTL2_PCFGR_3_rd_port_priority_Msk (0x3fful << UMCTL2_PCFGR_3_rd_port_priority_Pos) /*!< UMCTL2_T::PCFGR_3: rd_port_priority Mask */ + +#define UMCTL2_PCFGR_3_rd_port_aging_en_Pos (12) /*!< UMCTL2_T::PCFGR_3: rd_port_aging_en Position */ +#define UMCTL2_PCFGR_3_rd_port_aging_en_Msk (0x1ul << UMCTL2_PCFGR_3_rd_port_aging_en_Pos) /*!< UMCTL2_T::PCFGR_3: rd_port_aging_en Mask */ + +#define UMCTL2_PCFGR_3_rd_port_urgent_en_Pos (13) /*!< UMCTL2_T::PCFGR_3: rd_port_urgent_en Position*/ +#define UMCTL2_PCFGR_3_rd_port_urgent_en_Msk (0x1ul << UMCTL2_PCFGR_3_rd_port_urgent_en_Pos) /*!< UMCTL2_T::PCFGR_3: rd_port_urgent_en Mask */ + +#define UMCTL2_PCFGR_3_rd_port_pagematch_en_Pos (14) /*!< UMCTL2_T::PCFGR_3: rd_port_pagematch_en Position*/ +#define UMCTL2_PCFGR_3_rd_port_pagematch_en_Msk (0x1ul << UMCTL2_PCFGR_3_rd_port_pagematch_en_Pos) /*!< UMCTL2_T::PCFGR_3: rd_port_pagematch_en Mask */ + +#define UMCTL2_PCFGR_3_rdwr_ordered_en_Pos (16) /*!< UMCTL2_T::PCFGR_3: rdwr_ordered_en Position */ +#define UMCTL2_PCFGR_3_rdwr_ordered_en_Msk (0x1ul << UMCTL2_PCFGR_3_rdwr_ordered_en_Pos) /*!< UMCTL2_T::PCFGR_3: rdwr_ordered_en Mask */ + +#define UMCTL2_PCFGW_3_wr_port_priority_Pos (0) /*!< UMCTL2_T::PCFGW_3: wr_port_priority Position */ +#define UMCTL2_PCFGW_3_wr_port_priority_Msk (0x3fful << UMCTL2_PCFGW_3_wr_port_priority_Pos) /*!< UMCTL2_T::PCFGW_3: wr_port_priority Mask */ + +#define UMCTL2_PCFGW_3_wr_port_aging_en_Pos (12) /*!< UMCTL2_T::PCFGW_3: wr_port_aging_en Position */ +#define UMCTL2_PCFGW_3_wr_port_aging_en_Msk (0x1ul << UMCTL2_PCFGW_3_wr_port_aging_en_Pos) /*!< UMCTL2_T::PCFGW_3: wr_port_aging_en Mask */ + +#define UMCTL2_PCFGW_3_wr_port_urgent_en_Pos (13) /*!< UMCTL2_T::PCFGW_3: wr_port_urgent_en Position*/ +#define UMCTL2_PCFGW_3_wr_port_urgent_en_Msk (0x1ul << UMCTL2_PCFGW_3_wr_port_urgent_en_Pos) /*!< UMCTL2_T::PCFGW_3: wr_port_urgent_en Mask */ + +#define UMCTL2_PCFGW_3_wr_port_pagematch_en_Pos (14) /*!< UMCTL2_T::3: wr_port_pagematch_en Position*/ +#define UMCTL2_PCFGW_3_wr_port_pagematch_en_Msk (0x1ul << UMCTL2_PCFGW_3_wr_port_pagematch_en_Pos) /*!< UMCTL2_T::3: wr_port_pagematch_en Mask */ + +#define UMCTL2_PCTRL_3_port_en_Pos (0) /*!< UMCTL2_T::PCTRL_3: port_en Position */ +#define UMCTL2_PCTRL_3_port_en_Msk (0x1ul << UMCTL2_PCTRL_3_port_en_Pos) /*!< UMCTL2_T::PCTRL_3: port_en Mask */ + +#define UMCTL2_PCFGQOS0_3_rqos_map_level1_Pos (0) /*!< UMCTL2_T::PCFGQOS0_3: rqos_map_level1 Position */ +#define UMCTL2_PCFGQOS0_3_rqos_map_level1_Msk (0xful << UMCTL2_PCFGQOS0_3_rqos_map_level1_Pos) /*!< UMCTL2_T::PCFGQOS0_3: rqos_map_level1 Mask */ + +#define UMCTL2_PCFGQOS0_3_rqos_map_region0_Pos (16) /*!< UMCTL2_T::PCFGQOS0_3: rqos_map_region0 Position */ +#define UMCTL2_PCFGQOS0_3_rqos_map_region0_Msk (0x3ul << UMCTL2_PCFGQOS0_3_rqos_map_region0_Pos) /*!< UMCTL2_T::PCFGQOS0_3: rqos_map_region0 Mask */ + +#define UMCTL2_PCFGQOS0_3_rqos_map_region1_Pos (20) /*!< UMCTL2_T::PCFGQOS0_3: rqos_map_region1 Position */ +#define UMCTL2_PCFGQOS0_3_rqos_map_region1_Msk (0x3ul << UMCTL2_PCFGQOS0_3_rqos_map_region1_Pos) /*!< UMCTL2_T::PCFGQOS0_3: rqos_map_region1 Mask */ + +#define UMCTL2_PCFGR_4_rd_port_priority_Pos (0) /*!< UMCTL2_T::PCFGR_4: rd_port_priority Position */ +#define UMCTL2_PCFGR_4_rd_port_priority_Msk (0x3fful << UMCTL2_PCFGR_4_rd_port_priority_Pos) /*!< UMCTL2_T::PCFGR_4: rd_port_priority Mask */ + +#define UMCTL2_PCFGR_4_rd_port_aging_en_Pos (12) /*!< UMCTL2_T::PCFGR_4: rd_port_aging_en Position */ +#define UMCTL2_PCFGR_4_rd_port_aging_en_Msk (0x1ul << UMCTL2_PCFGR_4_rd_port_aging_en_Pos) /*!< UMCTL2_T::PCFGR_4: rd_port_aging_en Mask */ + +#define UMCTL2_PCFGR_4_rd_port_urgent_en_Pos (13) /*!< UMCTL2_T::PCFGR_4: rd_port_urgent_en Position*/ +#define UMCTL2_PCFGR_4_rd_port_urgent_en_Msk (0x1ul << UMCTL2_PCFGR_4_rd_port_urgent_en_Pos) /*!< UMCTL2_T::PCFGR_4: rd_port_urgent_en Mask */ + +#define UMCTL2_PCFGR_4_rd_port_pagematch_en_Pos (14) /*!< UMCTL2_T::PCFGR_4: rd_port_pagematch_en Position*/ +#define UMCTL2_PCFGR_4_rd_port_pagematch_en_Msk (0x1ul << UMCTL2_PCFGR_4_rd_port_pagematch_en_Pos) /*!< UMCTL2_T::PCFGR_4: rd_port_pagematch_en Mask */ + +#define UMCTL2_PCFGR_4_rdwr_ordered_en_Pos (16) /*!< UMCTL2_T::PCFGR_4: rdwr_ordered_en Position */ +#define UMCTL2_PCFGR_4_rdwr_ordered_en_Msk (0x1ul << UMCTL2_PCFGR_4_rdwr_ordered_en_Pos) /*!< UMCTL2_T::PCFGR_4: rdwr_ordered_en Mask */ + +#define UMCTL2_PCFGW_4_wr_port_priority_Pos (0) /*!< UMCTL2_T::PCFGW_4: wr_port_priority Position */ +#define UMCTL2_PCFGW_4_wr_port_priority_Msk (0x3fful << UMCTL2_PCFGW_4_wr_port_priority_Pos) /*!< UMCTL2_T::PCFGW_4: wr_port_priority Mask */ + +#define UMCTL2_PCFGW_4_wr_port_aging_en_Pos (12) /*!< UMCTL2_T::PCFGW_4: wr_port_aging_en Position */ +#define UMCTL2_PCFGW_4_wr_port_aging_en_Msk (0x1ul << UMCTL2_PCFGW_4_wr_port_aging_en_Pos) /*!< UMCTL2_T::PCFGW_4: wr_port_aging_en Mask */ + +#define UMCTL2_PCFGW_4_wr_port_urgent_en_Pos (13) /*!< UMCTL2_T::PCFGW_4: wr_port_urgent_en Position*/ +#define UMCTL2_PCFGW_4_wr_port_urgent_en_Msk (0x1ul << UMCTL2_PCFGW_4_wr_port_urgent_en_Pos) /*!< UMCTL2_T::PCFGW_4: wr_port_urgent_en Mask */ + +#define UMCTL2_PCFGW_4_wr_port_pagematch_en_Pos (14) /*!< UMCTL2_T::PCFGW_4: wr_port_pagematch_en Position*/ +#define UMCTL2_PCFGW_4_wr_port_pagematch_en_Msk (0x1ul << UMCTL2_PCFGW_4_wr_port_pagematch_en_Pos) /*!< UMCTL2_T::PCFGW_4: wr_port_pagematch_en Mask */ + +#define UMCTL2_PCTRL_4_port_en_Pos (0) /*!< UMCTL2_T::PCTRL_4: port_en Position */ +#define UMCTL2_PCTRL_4_port_en_Msk (0x1ul << UMCTL2_PCTRL_4_port_en_Pos) /*!< UMCTL2_T::PCTRL_4: port_en Mask */ + +#define UMCTL2_PCFGQOS0_4_rqos_map_level1_Pos (0) /*!< UMCTL2_T::PCFGQOS0_4: rqos_map_level1 Position */ +#define UMCTL2_PCFGQOS0_4_rqos_map_level1_Msk (0xful << UMCTL2_PCFGQOS0_4_rqos_map_level1_Pos) /*!< UMCTL2_T::PCFGQOS0_4: rqos_map_level1 Mask */ + +#define UMCTL2_PCFGQOS0_4_rqos_map_region0_Pos (16) /*!< UMCTL2_T::PCFGQOS0_4: rqos_map_region0 Position */ +#define UMCTL2_PCFGQOS0_4_rqos_map_region0_Msk (0x3ul << UMCTL2_PCFGQOS0_4_rqos_map_region0_Pos) /*!< UMCTL2_T::PCFGQOS0_4: rqos_map_region0 Mask */ + +#define UMCTL2_PCFGQOS0_4_rqos_map_region1_Pos (20) /*!< UMCTL2_T::PCFGQOS0_4: rqos_map_region1 Position */ +#define UMCTL2_PCFGQOS0_4_rqos_map_region1_Msk (0x3ul << UMCTL2_PCFGQOS0_4_rqos_map_region1_Pos) /*!< UMCTL2_T::PCFGQOS0_4: rqos_map_region1 Mask */ + +#define UMCTL2_PCFGR_5_rd_port_priority_Pos (0) /*!< UMCTL2_T::PCFGR_5: rd_port_priority Position */ +#define UMCTL2_PCFGR_5_rd_port_priority_Msk (0x3fful << UMCTL2_PCFGR_5_rd_port_priority_Pos) /*!< UMCTL2_T::PCFGR_5: rd_port_priority Mask */ + +#define UMCTL2_PCFGR_5_rd_port_aging_en_Pos (12) /*!< UMCTL2_T::PCFGR_5: rd_port_aging_en Position */ +#define UMCTL2_PCFGR_5_rd_port_aging_en_Msk (0x1ul << UMCTL2_PCFGR_5_rd_port_aging_en_Pos) /*!< UMCTL2_T::PCFGR_5: rd_port_aging_en Mask */ + +#define UMCTL2_PCFGR_5_rd_port_urgent_en_Pos (13) /*!< UMCTL2_T::PCFGR_5: rd_port_urgent_en Position*/ +#define UMCTL2_PCFGR_5_rd_port_urgent_en_Msk (0x1ul << UMCTL2_PCFGR_5_rd_port_urgent_en_Pos) /*!< UMCTL2_T::PCFGR_5: rd_port_urgent_en Mask */ + +#define UMCTL2_PCFGR_5_rd_port_pagematch_en_Pos (14) /*!< UMCTL2_T::PCFGR_5: rd_port_pagematch_en Position*/ +#define UMCTL2_PCFGR_5_rd_port_pagematch_en_Msk (0x1ul << UMCTL2_PCFGR_5_rd_port_pagematch_en_Pos) /*!< UMCTL2_T::PCFGR_5: rd_port_pagematch_en Mask */ + +#define UMCTL2_PCFGR_5_rdwr_ordered_en_Pos (16) /*!< UMCTL2_T::5: rdwr_ordered_en Position */ +#define UMCTL2_PCFGR_5_rdwr_ordered_en_Msk (0x1ul << UMCTL2_PCFGR_5_rdwr_ordered_en_Pos) /*!< UMCTL2_T::5: rdwr_ordered_en Mask */ + +#define UMCTL2_PCFGW_5_wr_port_priority_Pos (0) /*!< UMCTL2_T::PCFGW_5: wr_port_priority Position */ +#define UMCTL2_PCFGW_5_wr_port_priority_Msk (0x3fful << UMCTL2_PCFGW_5_wr_port_priority_Pos) /*!< UMCTL2_T::PCFGW_5: wr_port_priority Mask */ + +#define UMCTL2_PCFGW_5_wr_port_aging_en_Pos (12) /*!< UMCTL2_T::PCFGW_5: wr_port_aging_en Position */ +#define UMCTL2_PCFGW_5_wr_port_aging_en_Msk (0x1ul << UMCTL2_PCFGW_5_wr_port_aging_en_Pos) /*!< UMCTL2_T::PCFGW_5: wr_port_aging_en Mask */ + +#define UMCTL2_PCFGW_5_wr_port_urgent_en_Pos (13) /*!< UMCTL2_T::PCFGW_5: wr_port_urgent_en Position*/ +#define UMCTL2_PCFGW_5_wr_port_urgent_en_Msk (0x1ul << UMCTL2_PCFGW_5_wr_port_urgent_en_Pos) /*!< UMCTL2_T::PCFGW_5: wr_port_urgent_en Mask */ + +#define UMCTL2_PCFGW_5_wr_port_pagematch_en_Pos (14) /*!< UMCTL2_T::PCFGW_5: wr_port_pagematch_en Position*/ +#define UMCTL2_PCFGW_5_wr_port_pagematch_en_Msk (0x1ul << UMCTL2_PCFGW_5_wr_port_pagematch_en_Pos) /*!< UMCTL2_T::PCFGW_5: wr_port_pagematch_en Mask */ + +#define UMCTL2_PCTRL_5_port_en_Pos (0) /*!< UMCTL2_T::PCTRL_5: port_en Position */ +#define UMCTL2_PCTRL_5_port_en_Msk (0x1ul << UMCTL2_PCTRL_5_port_en_Pos) /*!< UMCTL2_T::PCTRL_5: port_en Mask */ + +#define UMCTL2_PCFGQOS0_5_rqos_map_level1_Pos (0) /*!< UMCTL2_T::PCFGQOS0_5: rqos_map_level1 Position */ +#define UMCTL2_PCFGQOS0_5_rqos_map_level1_Msk (0xful << UMCTL2_PCFGQOS0_5_rqos_map_level1_Pos) /*!< UMCTL2_T::PCFGQOS0_5: rqos_map_level1 Mask */ + +#define UMCTL2_PCFGQOS0_5_rqos_map_region0_Pos (16) /*!< UMCTL2_T::PCFGQOS0_5: rqos_map_region0 Position */ +#define UMCTL2_PCFGQOS0_5_rqos_map_region0_Msk (0x3ul << UMCTL2_PCFGQOS0_5_rqos_map_region0_Pos) /*!< UMCTL2_T::PCFGQOS0_5: rqos_map_region0 Mask */ + +#define UMCTL2_PCFGQOS0_5_rqos_map_region1_Pos (20) /*!< UMCTL2_T::PCFGQOS0_5: rqos_map_region1 Position */ +#define UMCTL2_PCFGQOS0_5_rqos_map_region1_Msk (0x3ul << UMCTL2_PCFGQOS0_5_rqos_map_region1_Pos) /*!< UMCTL2_T::PCFGQOS0_5: rqos_map_region1 Mask */ + +#define UMCTL2_PCFGR_6_rd_port_priority_Pos (0) /*!< UMCTL2_T::PCFGR_6: rd_port_priority Position */ +#define UMCTL2_PCFGR_6_rd_port_priority_Msk (0x3fful << UMCTL2_PCFGR_6_rd_port_priority_Pos) /*!< UMCTL2_T::PCFGR_6: rd_port_priority Mask */ + +#define UMCTL2_PCFGR_6_rd_port_aging_en_Pos (12) /*!< UMCTL2_T::PCFGR_6: rd_port_aging_en Position */ +#define UMCTL2_PCFGR_6_rd_port_aging_en_Msk (0x1ul << UMCTL2_PCFGR_6_rd_port_aging_en_Pos) /*!< UMCTL2_T::PCFGR_6: rd_port_aging_en Mask */ + +#define UMCTL2_PCFGR_6_rd_port_urgent_en_Pos (13) /*!< UMCTL2_T::PCFGR_6: rd_port_urgent_en Position*/ +#define UMCTL2_PCFGR_6_rd_port_urgent_en_Msk (0x1ul << UMCTL2_PCFGR_6_rd_port_urgent_en_Pos) /*!< UMCTL2_T::PCFGR_6: rd_port_urgent_en Mask */ + +#define UMCTL2_PCFGR_6_rd_port_pagematch_en_Pos (14) /*!< UMCTL2_T::PCFGR_6: rd_port_pagematch_en Position*/ +#define UMCTL2_PCFGR_6_rd_port_pagematch_en_Msk (0x1ul << UMCTL2_PCFGR_6_rd_port_pagematch_en_Pos) /*!< UMCTL2_T::PCFGR_6: rd_port_pagematch_en Mask */ + +#define UMCTL2_PCFGR_6_rdwr_ordered_en_Pos (16) /*!< UMCTL2_T::PCFGR_6: rdwr_ordered_en Position */ +#define UMCTL2_PCFGR_6_rdwr_ordered_en_Msk (0x1ul << UMCTL2_PCFGR_6_rdwr_ordered_en_Pos) /*!< UMCTL2_T::PCFGR_6: rdwr_ordered_en Mask */ + +#define UMCTL2_PCFGW_6_wr_port_priority_Pos (0) /*!< UMCTL2_T::PCFGW_6: wr_port_priority Position */ +#define UMCTL2_PCFGW_6_wr_port_priority_Msk (0x3fful << UMCTL2_PCFGW_6_wr_port_priority_Pos) /*!< UMCTL2_T::PCFGW_6: wr_port_priority Mask */ + +#define UMCTL2_PCFGW_6_wr_port_aging_en_Pos (12) /*!< UMCTL2_T::PCFGW_6: wr_port_aging_en Position */ +#define UMCTL2_PCFGW_6_wr_port_aging_en_Msk (0x1ul << UMCTL2_PCFGW_6_wr_port_aging_en_Pos) /*!< UMCTL2_T::PCFGW_6: wr_port_aging_en Mask */ + +#define UMCTL2_PCFGW_6_wr_port_urgent_en_Pos (13) /*!< UMCTL2_T::PCFGW_6: wr_port_urgent_en Position*/ +#define UMCTL2_PCFGW_6_wr_port_urgent_en_Msk (0x1ul << UMCTL2_PCFGW_6_wr_port_urgent_en_Pos) /*!< UMCTL2_T::PCFGW_6: wr_port_urgent_en Mask */ + +#define UMCTL2_PCFGW_6_wr_port_pagematch_en_Pos (14) /*!< UMCTL2_T::PCFGW_6: wr_port_pagematch_en Position*/ +#define UMCTL2_PCFGW_6_wr_port_pagematch_en_Msk (0x1ul << UMCTL2_PCFGW_6_wr_port_pagematch_en_Pos) /*!< UMCTL2_T::PCFGW_6: wr_port_pagematch_en Mask */ + +#define UMCTL2_PCTRL_6_port_en_Pos (0) /*!< UMCTL2_T::PCTRL_6: port_en Position */ +#define UMCTL2_PCTRL_6_port_en_Msk (0x1ul << UMCTL2_PCTRL_6_port_en_Pos) /*!< UMCTL2_T::PCTRL_6: port_en Mask */ + +#define UMCTL2_PCFGQOS0_6_rqos_map_level1_Pos (0) /*!< UMCTL2_T::PCFGQOS0_6: rqos_map_level1 Position */ +#define UMCTL2_PCFGQOS0_6_rqos_map_level1_Msk (0xful << UMCTL2_PCFGQOS0_6_rqos_map_level1_Pos) /*!< UMCTL2_T::PCFGQOS0_6: rqos_map_level1 Mask */ + +#define UMCTL2_PCFGQOS0_6_rqos_map_region0_Pos (16) /*!< UMCTL2_T::PCFGQOS0_6: rqos_map_region0 Position */ +#define UMCTL2_PCFGQOS0_6_rqos_map_region0_Msk (0x3ul << UMCTL2_PCFGQOS0_6_rqos_map_region0_Pos) /*!< UMCTL2_T::PCFGQOS0_6: rqos_map_region0 Mask */ + +#define UMCTL2_PCFGQOS0_6_rqos_map_region1_Pos (20) /*!< UMCTL2_T::PCFGQOS0_6: rqos_map_region1 Position */ +#define UMCTL2_PCFGQOS0_6_rqos_map_region1_Msk (0x3ul << UMCTL2_PCFGQOS0_6_rqos_map_region1_Pos) /*!< UMCTL2_T::PCFGQOS0_6: rqos_map_region1 Mask */ + +#define UMCTL2_PCFGR_7_rd_port_priority_Pos (0) /*!< UMCTL2_T::PCFGR_7: rd_port_priority Position */ +#define UMCTL2_PCFGR_7_rd_port_priority_Msk (0x3fful << UMCTL2_PCFGR_7_rd_port_priority_Pos) /*!< UMCTL2_T::PCFGR_7: rd_port_priority Mask */ + +#define UMCTL2_PCFGR_7_rd_port_aging_en_Pos (12) /*!< UMCTL2_T::PCFGR_7: rd_port_aging_en Position */ +#define UMCTL2_PCFGR_7_rd_port_aging_en_Msk (0x1ul << UMCTL2_PCFGR_7_rd_port_aging_en_Pos) /*!< UMCTL2_T::PCFGR_7: rd_port_aging_en Mask */ + +#define UMCTL2_PCFGR_7_rd_port_urgent_en_Pos (13) /*!< UMCTL2_T::PCFGR_7: rd_port_urgent_en Position*/ +#define UMCTL2_PCFGR_7_rd_port_urgent_en_Msk (0x1ul << UMCTL2_PCFGR_7_rd_port_urgent_en_Pos) /*!< UMCTL2_T::PCFGR_7: rd_port_urgent_en Mask */ + +#define UMCTL2_PCFGR_7_rd_port_pagematch_en_Pos (14) /*!< UMCTL2_T::PCFGR_7: rd_port_pagematch_en Position*/ +#define UMCTL2_PCFGR_7_rd_port_pagematch_en_Msk (0x1ul << UMCTL2_PCFGR_7_rd_port_pagematch_en_Pos) /*!< UMCTL2_T::PCFGR_7: rd_port_pagematch_en Mask */ + +#define UMCTL2_PCFGR_7_rdwr_ordered_en_Pos (16) /*!< UMCTL2_T::PCFGR_7: rdwr_ordered_en Position */ +#define UMCTL2_PCFGR_7_rdwr_ordered_en_Msk (0x1ul << UMCTL2_PCFGR_7_rdwr_ordered_en_Pos) /*!< UMCTL2_T::PCFGR_7: rdwr_ordered_en Mask */ + +#define UMCTL2_PCFGW_7_wr_port_priority_Pos (0) /*!< UMCTL2_T::PCFGW_7: wr_port_priority Position */ +#define UMCTL2_PCFGW_7_wr_port_priority_Msk (0x3fful << UMCTL2_PCFGW_7_wr_port_priority_Pos) /*!< UMCTL2_T::PCFGW_7: wr_port_priority Mask */ + +#define UMCTL2_PCFGW_7_wr_port_aging_en_Pos (12) /*!< UMCTL2_T::PCFGW_7: wr_port_aging_en Position */ +#define UMCTL2_PCFGW_7_wr_port_aging_en_Msk (0x1ul << UMCTL2_PCFGW_7_wr_port_aging_en_Pos) /*!< UMCTL2_T::PCFGW_7: wr_port_aging_en Mask */ + +#define UMCTL2_PCFGW_7_wr_port_urgent_en_Pos (13) /*!< UMCTL2_T::PCFGW_7: wr_port_urgent_en Position*/ +#define UMCTL2_PCFGW_7_wr_port_urgent_en_Msk (0x1ul << UMCTL2_PCFGW_7_wr_port_urgent_en_Pos) /*!< UMCTL2_T::PCFGW_7: wr_port_urgent_en Mask */ + +#define UMCTL2_PCFGW_7_wr_port_pagematch_en_Pos (14) /*!< UMCTL2_T::PCFGW_7: wr_port_pagematch_en Position*/ +#define UMCTL2_PCFGW_7_wr_port_pagematch_en_Msk (0x1ul << UMCTL2_PCFGW_7_wr_port_pagematch_en_Pos) /*!< UMCTL2_T::PCFGW_7: wr_port_pagematch_en Mask */ + +#define UMCTL2_PCTRL_7_port_en_Pos (0) /*!< UMCTL2_T::PCTRL_7: port_en Position */ +#define UMCTL2_PCTRL_7_port_en_Msk (0x1ul << UMCTL2_PCTRL_7_port_en_Pos) /*!< UMCTL2_T::PCTRL_7: port_en Mask */ + +#define UMCTL2_PCFGQOS0_7_rqos_map_level1_Pos (0) /*!< UMCTL2_T::PCFGQOS0_7: rqos_map_level1 Position */ +#define UMCTL2_PCFGQOS0_7_rqos_map_level1_Msk (0xful << UMCTL2_PCFGQOS0_7_rqos_map_level1_Pos) /*!< UMCTL2_T::PCFGQOS0_7: rqos_map_level1 Mask */ + +#define UMCTL2_PCFGQOS0_7_rqos_map_region0_Pos (16) /*!< UMCTL2_T::PCFGQOS0_7: rqos_map_region0 Position */ +#define UMCTL2_PCFGQOS0_7_rqos_map_region0_Msk (0x3ul << UMCTL2_PCFGQOS0_7_rqos_map_region0_Pos) /*!< UMCTL2_T::PCFGQOS0_7: rqos_map_region0 Mask */ + +#define UMCTL2_PCFGQOS0_7_rqos_map_region1_Pos (20) /*!< UMCTL2_T::PCFGQOS0_7: rqos_map_region1 Position */ +#define UMCTL2_PCFGQOS0_7_rqos_map_region1_Msk (0x3ul << UMCTL2_PCFGQOS0_7_rqos_map_region1_Pos) /*!< UMCTL2_T::PCFGQOS0_7: rqos_map_region1 Mask */ + +#define UMCTL2_SARBASE0_base_addr_Pos (0) /*!< UMCTL2_T::SARBASE0: base_addr Position */ +#define UMCTL2_SARBASE0_base_addr_Msk (0x3ul << UMCTL2_SARBASE0_base_addr_Pos) /*!< UMCTL2_T::SARBASE0: base_addr Mask */ + +#define UMCTL2_SARSIZE0_nblocks_Pos (0) /*!< UMCTL2_T::SARSIZE0: nblocks Position */ +#define UMCTL2_SARSIZE0_nblocks_Msk (0xfful << UMCTL2_SARSIZE0_nblocks_Pos) /*!< UMCTL2_T::SARSIZE0: nblocks Mask */ + +#define UMCTL2_VER_NUMBER_ver_number_Pos (0) /*!< UMCTL2_T::VER_NUMBER: ver_number Position*/ +#define UMCTL2_VER_NUMBER_ver_number_Msk (0xfffffffful << UMCTL2_VER_NUMBER_ver_number_Pos) /*!< UMCTL2_T::VER_NUMBER: ver_number Mask */ + +#define UMCTL2_VER_TYPE_ver_type_Pos (0) /*!< UMCTL2_T::VER_TYPE: ver_type Position */ +#define UMCTL2_VER_TYPE_ver_type_Msk (0xfffffffful << UMCTL2_VER_TYPE_ver_type_Pos) /*!< UMCTL2_T::VER_TYPE: ver_type Mask */ + +/**@}*/ /* UMCTL2_CONST */ +/**@}*/ /* end of UMCTL2 register group */ + + +/**@}*/ /* end of REGISTER group */ + +#if defined ( __CC_ARM ) + #pragma no_anon_unions +#endif + +#endif /* __UMCTL2_REG_H__ */ + + diff --git a/bsp/nuvoton/libraries/ma35/Device/Nuvoton/MA35D1/Include/usbh_reg.h b/bsp/nuvoton/libraries/ma35/Device/Nuvoton/MA35D1/Include/usbh_reg.h new file mode 100644 index 0000000000..368cdc2fb1 --- /dev/null +++ b/bsp/nuvoton/libraries/ma35/Device/Nuvoton/MA35D1/Include/usbh_reg.h @@ -0,0 +1,796 @@ +/**************************************************************************//** + * @file usbh_reg.h + * @brief USBH register definition header file + * + * SPDX-License-Identifier: Apache-2.0 + * @copyright (C) 2021 Nuvoton Technology Corp. All rights reserved. + *****************************************************************************/ +#ifndef __USBH_REG_H__ +#define __USBH_REG_H__ + +#if defined ( __CC_ARM ) + #pragma anon_unions +#endif + +/** + @addtogroup REGISTER Control Register + @{ +*/ + +/** + @addtogroup USBH USB Host Controller(USBH) + Memory Mapped Structure for USBH Controller +@{ */ + +typedef struct +{ + + + /** + * @var USBH_T::HcRevision + * Offset: 0x00 Host Controller Revision Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[7:0] |REV |Revision Number + * | | |Indicates the Open HCI Specification revision number implemented by the Hardware + * | | |Host Controller supports 1.1 specification. + * | | |(X.Y = XYh). + * @var USBH_T::HcControl + * Offset: 0x04 Host Controller Control Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[1:0] |CBSR |Control Bulk Service Ratio + * | | |This specifies the service ratio between Control and Bulk EDs + * | | |Before processing any of the non-periodic lists, HC must compare the ratio specified with its internal count on how many nonempty Control EDs have been processed, in determining whether to continue serving another Control ED or switching to Bulk EDs + * | | |The internal count will be retained when crossing the frame boundary + * | | |In case of reset, HCD is responsible for restoring this value. + * | | |00 = Number of Control EDs over Bulk EDs served is 1:1. + * | | |01 = Number of Control EDs over Bulk EDs served is 2:1. + * | | |10 = Number of Control EDs over Bulk EDs served is 3:1. + * | | |11 = Number of Control EDs over Bulk EDs served is 4:1. + * |[2] |PLE |Periodic List Enable Bit + * | | |When set, this bit enables processing of the Periodic (interrupt and isochronous) list + * | | |The Host Controller checks this bit prior to attempting any periodic transfers in a frame. + * | | |0 = Processing of the Periodic (Interrupt and Isochronous) list after next SOF (Start-Of-Frame) Disabled. + * | | |1 = Processing of the Periodic (Interrupt and Isochronous) list in the next frame Enabled. + * | | |Note: To enable the processing of the Isochronous list, user has to set both PLE and IE (HcControl[3]) high. + * |[3] |IE |Isochronous List Enable Bit + * | | |Both ISOEn and PLE (HcControl[2]) high enables Host Controller to process the Isochronous list + * | | |Either ISOEn or PLE (HcControl[2]) is low disables Host Controller to process the Isochronous list. + * | | |0 = Processing of the Isochronous list after next SOF (Start-Of-Frame) Disabled. + * | | |1 = Processing of the Isochronous list in the next frame Enabled, if the PLE (HcControl[2]) is high, too. + * |[4] |CLE |Control List Enable Bit + * | | |0 = Processing of the Control list after next SOF (Start-Of-Frame) Disabled. + * | | |1 = Processing of the Control list in the next frame Enabled. + * |[5] |BLE |Bulk List Enable Bit + * | | |0 = Processing of the Bulk list after next SOF (Start-Of-Frame) Disabled. + * | | |1 = Processing of the Bulk list in the next frame Enabled. + * |[7:6] |HCFS |Host Controller Functional State + * | | |This field sets the Host Controller state + * | | |The Controller may force a state change from USBSUSPEND to USBRESUME after detecting resume signaling from a downstream port + * | | |States are: + * | | |00 = USBSUSPEND. + * | | |01 = USBOPERATIONAL. + * | | |10 = USBRESUME. + * | | |11 = USBRESET. + * @var USBH_T::HcCommandStatus + * Offset: 0x08 Host Controller Command Status Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[0] |HCR |Host Controller Reset + * | | |This bit is set to initiate the software reset of Host Controller + * | | |This bit is cleared by the Host Controller, upon completed of the reset operation. + * | | |This bit, when set, didn't reset the Root Hub and no subsequent reset signaling be asserted to its downstream ports. + * | | |0 = Host Controller is not in software reset state. + * | | |1 = Host Controller is in software reset state. + * |[1] |CLF |Control List Filled + * | | |Set high to indicate there is an active TD on the Control List + * | | |It may be set by either software or the Host Controller and cleared by the Host Controller each time it begins processing the head of the Control List. + * | | |0 = No active TD found or Host Controller begins to process the head of the Control list. + * | | |1 = An active TD added or found on the Control list. + * |[2] |BLF |Bulk List Filled + * | | |Set high to indicate there is an active TD on the Bulk list + * | | |This bit may be set by either software or the Host Controller and cleared by the Host Controller each time it begins processing the head of the Bulk list. + * | | |0 = No active TD found or Host Controller begins to process the head of the Bulk list. + * | | |1 = An active TD added or found on the Bulk list. + * |[17:16] |SOC |Schedule Overrun Count (Read Only) + * | | |These bits are incremented on each scheduling overrun error + * | | |It is initialized to 00b and wraps around at 11b + * | | |This will be incremented when a scheduling overrun is detected even if SO (HcInterruptStatus[0]) has already been set. + * @var USBH_T::HcInterruptStatus + * Offset: 0x0C Host Controller Interrupt Status Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[0] |SO |Scheduling Overrun + * | | |Set when the List Processor determines a Schedule Overrun has occurred. + * | | |0 = Schedule Overrun didn't occur. + * | | |1 = Schedule Overrun has occurred. + * | | |Note: This bit is cleared by writing 1 to it. + * |[1] |WDH |Write Back Done Head + * | | |Set after the Host Controller has written HcDoneHead to HccaDoneHead + * | | |Further updates of the HccaDoneHead will not occur until this bit has been cleared. + * | | |0 = Host Controller didn't update HccaDoneHead. + * | | |1 = Host Controller has written HcDoneHead to HccaDoneHead. + * | | |Note: This bit is cleared by writing 1 to it. + * |[2] |SF |Start of Frame + * | | |Set when the Frame Management functional block signals a 'Start of Frame' event + * | | |Host Control generates a SOF token at the same time. + * | | |0 = Not the start of a frame. + * | | |1 = Indicate the start of a frame and Host Controller generates a SOF token. + * | | |Note: This bit is cleared by writing 1 to it. + * |[3] |RD |Resume Detected + * | | |Set when Host Controller detects resume signaling on a downstream port. + * | | |0 = No resume signaling detected on a downstream port. + * | | |1 = Resume signaling detected on a downstream port. + * | | |Note: This bit is cleared by writing 1 to it. + * |[5] |FNO |Frame Number Overflow + * | | |This bit is set when bit 15 of Frame Number changes from 1 to 0 or from 0 to 1. + * | | |0 = The bit 15 of Frame Number didn't change. + * | | |1 = The bit 15 of Frame Number changes from 1 to 0 or from 0 to 1. + * | | |Note: This bit is cleared by writing 1 to it. + * |[6] |RHSC |Root Hub Status Change + * | | |This bit is set when the content of HcRhStatus or the content of HcRhPortStatus register has changed. + * | | |0 = The content of HcRhStatus and the content of HcRhPortStatus register didn't change. + * | | |1 = The content of HcRhStatus or the content of HcRhPortStatus register has changed. + * | | |Note: This bit is cleared by writing h'1f to HcRhPortStatus6[20:16]. + * @var USBH_T::HcInterruptEnable + * Offset: 0x10 Host Controller Interrupt Enable Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[0] |SO |Scheduling Overrun Enable Bit + * | | |Write Operation: + * | | |0 = No effect. + * | | |1 = Interrupt generation due to SO (HcInterruptStatus[0]) Enabled. + * | | |Read Operation: + * | | |0 = Interrupt generation due to SO (HcInterruptStatus[0]) Disabled. + * | | |1 = Interrupt generation due to SO (HcInterruptStatus[0]) Enabled. + * |[1] |WDH |Write Back Done Head Enable Bit + * | | |Write Operation: + * | | |0 = No effect. + * | | |1 = Interrupt generation due to WDH (HcInterruptStatus[1]) Enabled. + * | | |Read Operation: + * | | |0 = Interrupt generation due to WDH (HcInterruptStatus[1]) Disabled. + * | | |1 = Interrupt generation due to WDH (HcInterruptStatus[1]) Enabled. + * |[2] |SF |Start of Frame Enable Bit + * | | |Write Operation: + * | | |0 = No effect. + * | | |1 = Interrupt generation due to SF (HcInterruptStatus[2]) Enabled. + * | | |Read Operation: + * | | |0 = Interrupt generation due to SF (HcInterruptStatus[2]) Disabled. + * | | |1 = Interrupt generation due to SF (HcInterruptStatus[2]) Enabled. + * |[3] |RD |Resume Detected Enable Bit + * | | |Write Operation: + * | | |0 = No effect. + * | | |1 = Interrupt generation due to RD (HcInterruptStatus[3]) Enabled. + * | | |Read Operation: + * | | |0 = Interrupt generation due to RD (HcInterruptStatus[3]) Disabled. + * | | |1 = Interrupt generation due to RD (HcInterruptStatus[3]) Enabled. + * |[5] |FNO |Frame Number Overflow Enable Bit + * | | |Write Operation: + * | | |0 = No effect. + * | | |1 = Interrupt generation due to FNO (HcInterruptStatus[5]) Enabled. + * | | |Read Operation: + * | | |0 = Interrupt generation due to FNO (HcInterruptStatus[5]) Disabled. + * | | |1 = Interrupt generation due to FNO (HcInterruptStatus[5]) Enabled. + * |[6] |RHSC |Root Hub Status Change Enable Bit + * | | |Write Operation: + * | | |0 = No effect. + * | | |1 = Interrupt generation due to RHSC (HcInterruptStatus[6]) Enabled. + * | | |Read Operation: + * | | |0 = Interrupt generation due to RHSC (HcInterruptStatus[6]) Disabled. + * | | |1 = Interrupt generation due to RHSC (HcInterruptStatus[6]) Enabled. + * |[31] |MIE |Master Interrupt Enable Bit + * | | |This bit is a global interrupt enable + * | | |A write of '1' allows interrupts to be enabled via the specific enable bits listed above. + * | | |Write Operation: + * | | |0 = No effect. + * | | |1 = Interrupt generation due to RHSC (HcInterruptStatus[6]), FNO (HcInterruptStatus[5]), RD (HcInterruptStatus[3]), SF (HcInterruptStatus[2]), WDH (HcInterruptStatus[1]) or SO (HcInterruptStatus[0]) Enabled if the corresponding bit in HcInterruptEnable is high. + * | | |Read Operation: + * | | |0 = Interrupt generation due to RHSC (HcInterruptStatus[6]), FNO (HcInterruptStatus[5]), RD (HcInterruptStatus[3]), SF (HcInterruptStatus[2]), WDH (HcInterruptStatus[1]) or SO (HcInterruptStatus[0]) Disabled even if the corresponding bit in HcInterruptEnable is high. + * | | |1 = Interrupt generation due to RHSC (HcInterruptStatus[6]), FNO (HcInterruptStatus[5]), RD (HcInterruptStatus[3]), SF (HcInterruptStatus[2]), WDH (HcInterruptStatus[1]) or SO (HcInterruptStatus[0]) Enabled if the corresponding bit in HcInterruptEnable is high. + * @var USBH_T::HcInterruptDisable + * Offset: 0x14 Host Controller Interrupt Disable Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[0] |SO |Scheduling Overrun Disable Bit + * | | |Write Operation: + * | | |0 = No effect. + * | | |1 = Interrupt generation due to SO (HcInterruptStatus[0]) Disabled. + * | | |Read Operation: + * | | |0 = Interrupt generation due to SO (HcInterruptStatus[0]) Disabled. + * | | |1 = Interrupt generation due to SO (HcInterruptStatus[0]) Enabled. + * |[1] |WDH |Write Back Done Head Disable Bit + * | | |Write Operation: + * | | |0 = No effect. + * | | |1 = Interrupt generation due to WDH (HcInterruptStatus[1]) Disabled. + * | | |Read Operation: + * | | |0 = Interrupt generation due to WDH (HcInterruptStatus[1]) Disabled. + * | | |1 = Interrupt generation due to WDH (HcInterruptStatus[1]) Enabled. + * |[2] |SF |Start of Frame Disable Bit + * | | |Write Operation: + * | | |0 = No effect. + * | | |1 = Interrupt generation due to SF (HcInterruptStatus[2]) Disabled. + * | | |Read Operation: + * | | |0 = Interrupt generation due to SF (HcInterruptStatus[2]) Disabled. + * | | |1 = Interrupt generation due to SF (HcInterruptStatus[2]) Enabled. + * |[3] |RD |Resume Detected Disable Bit + * | | |Write Operation: + * | | |0 = No effect. + * | | |1 = Interrupt generation due to RD (HcInterruptStatus[3]) Disabled. + * | | |Read Operation: + * | | |0 = Interrupt generation due to RD (HcInterruptStatus[3]) Disabled. + * | | |1 = Interrupt generation due to RD (HcInterruptStatus[3]) Enabled. + * |[5] |FNO |Frame Number Overflow Disable Bit + * | | |Write Operation: + * | | |0 = No effect. + * | | |1 = Interrupt generation due to FNO (HcInterruptStatus[5]) Disabled. + * | | |Read Operation: + * | | |0 = Interrupt generation due to FNO (HcInterruptStatus[5]) Disabled. + * | | |1 = Interrupt generation due to FNO (HcInterruptStatus[5]) Enabled. + * |[6] |RHSC |Root Hub Status Change Disable Bit + * | | |Write Operation: + * | | |0 = No effect. + * | | |1 = Interrupt generation due to RHSC (HcInterruptStatus[6]) Disabled. + * | | |Read Operation: + * | | |0 = Interrupt generation due to RHSC (HcInterruptStatus[6]) Disabled. + * | | |1 = Interrupt generation due to RHSC (HcInterruptStatus[6]) Enabled. + * |[31] |MIE |Master Interrupt Disable Bit + * | | |Global interrupt disable. Writing '1' to disable all interrupts. + * | | |Write Operation: + * | | |0 = No effect. + * | | |1 = Interrupt generation due to RHSC (HcInterruptStatus[6]), FNO (HcInterruptStatus[5]), RD (HcInterruptStatus[3]), SF (HcInterruptStatus[2]), WDH (HcInterruptStatus[1]) or SO (HcInterruptStatus[0]) Disabled if the corresponding bit in HcInterruptEnable is high. + * | | |Read Operation: + * | | |0 = Interrupt generation due to RHSC (HcInterruptStatus[6]), FNO (HcInterruptStatus[5]), RD (HcInterruptStatus[3]), SF (HcInterruptStatus[2]), WDH (HcInterruptStatus[1]) or SO (HcInterruptStatus[0]) Disabled even if the corresponding bit in HcInterruptEnable is high. + * | | |1 = Interrupt generation due to RHSC (HcInterruptStatus[6]), FNO (HcInterruptStatus[5]), RD (HcInterruptStatus[3]), SF (HcInterruptStatus[2]), WDH (HcInterruptStatus[1]) or SO (HcInterruptStatus[0]) Enabled if the corresponding bit in HcInterruptEnable is high. + * @var USBH_T::HcHCCA + * Offset: 0x18 Host Controller Communication Area Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[31:8] |HCCA |Host Controller Communication Area + * | | |Pointer to indicate base address of the Host Controller Communication Area (HCCA). + * @var USBH_T::HcPeriodCurrentED + * Offset: 0x1C Host Controller Period Current ED Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[31:4] |PCED |Periodic Current ED + * | | |Pointer to indicate physical address of the current Isochronous or Interrupt Endpoint Descriptor. + * @var USBH_T::HcControlHeadED + * Offset: 0x20 Host Controller Control Head ED Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[31:4] |CHED |Control Head ED + * | | |Pointer to indicate physical address of the first Endpoint Descriptor of the Control list. + * @var USBH_T::HcControlCurrentED + * Offset: 0x24 Host Controller Control Current ED Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[31:4] |CCED |Control Current Head ED + * | | |Pointer to indicate the physical address of the current Endpoint Descriptor of the Control list. + * @var USBH_T::HcBulkHeadED + * Offset: 0x28 Host Controller Bulk Head ED Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[31:4] |BHED |Bulk Head ED + * | | |Pointer to indicate the physical address of the first Endpoint Descriptor of the Bulk list. + * @var USBH_T::HcBulkCurrentED + * Offset: 0x2C Host Controller Bulk Current ED Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[31:4] |BCED |Bulk Current Head ED + * | | |Pointer to indicate the physical address of the current endpoint of the Bulk list. + * @var USBH_T::HcDoneHead + * Offset: 0x30 Host Controller Done Head Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[31:4] |DH |Done Head + * | | |Pointer to indicate the physical address of the last completed Transfer Descriptor that was added to the Done queue. + * @var USBH_T::HcFmInterval + * Offset: 0x34 Host Controller Frame Interval Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[13:0] |FI |Frame Interval + * | | |This field specifies the length of a frame as (bit times - 1) + * | | |For 12,000 bit times in a frame, a value of 11,999 is stored here. + * |[29:16] |FSMPS |FS Largest Data Packet + * | | |This field specifies a value that is loaded into the Largest Data Packet Counter at the beginning of each frame. + * |[31] |FIT |Frame Interval Toggle + * | | |This bit is toggled by Host Controller Driver when it loads a new value into FI (HcFmInterval[13:0]). + * | | |0 = Host Controller Driver didn't load new value into FI (HcFmInterval[13:0]). + * | | |1 = Host Controller Driver loads a new value into FI (HcFmInterval[13:0]). + * @var USBH_T::HcFmRemaining + * Offset: 0x38 Host Controller Frame Remaining Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[13:0] |FR |Frame Remaining + * | | |When the Host Controller is in the USBOPERATIONAL state, this 14-bit field decrements each 12 MHz clock period + * | | |When the count reaches 0, (end of frame) the counter reloads with Frame Interval + * | | |In addition, the counter loads when the Host Controller transitions into USBOPERATIONAL. + * |[31] |FRT |Frame Remaining Toggle + * | | |This bit is loaded from the FIT (HcFmInterval[31]) whenever FR (HcFmRemaining[13:0]) reaches 0. + * @var USBH_T::HcFmNumber + * Offset: 0x3C Host Controller Frame Number Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[15:0] |FN |Frame Number + * | | |This 16-bit incrementing counter field is incremented coincident with the re-load of FR (HcFmRemaining[13:0]) + * | | |The count rolls over from 'FFFFh' to '0h.' + * @var USBH_T::HcPeriodicStart + * Offset: 0x40 Host Controller Periodic Start Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[13:0] |PS |Periodic Start + * | | |This field contains a value used by the List Processor to determine where in a frame the Periodic List processing must begin. + * @var USBH_T::HcLSThreshold + * Offset: 0x44 Host Controller Low-speed Threshold Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[11:0] |LST |Low-speed Threshold + * | | |This field contains a value which is compared to the FR (HcFmRemaining[13:0]) field prior to initiating a Low-speed transaction + * | | |The transaction is started only if FR (HcFmRemaining[13:0]) >= this field + * | | |The value is calculated by Host Controller Driver with the consideration of transmission and setup overhead. + * @var USBH_T::HcRhDescriptorA + * Offset: 0x48 Host Controller Root Hub Descriptor A Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[7:0] |NDP |Number Downstream Ports + * | | |USB host control supports two downstream ports and only one port is available in this series of chip. + * | | |Note: NDP = 6 in this series of chip. + * |[8] |PSM |Power Switching Mode + * | | |This bit is used to specify how the power switching of the Root Hub ports is controlled. + * | | |0 = Global switching. + * | | |1 = Individual switching. + * |[11] |OCPM |Overcurrent Protection Mode + * | | |This bit describes how the overcurrent status for the Root Hub ports reported + * | | |This bit is only valid when NOCP (HcRhDescriptorA[12]) is cleared. + * | | |0 = Global overcurrent. + * | | |1 = Individual overcurrent. + * |[12] |NOCP |No overcurrent Protection + * | | |This bit describes how the overcurrent status for the Root Hub ports reported. + * | | |0 = Overcurrent status is reported. + * | | |1 = Overcurrent status is not reported. + * @var USBH_T::HcRhDescriptorB + * Offset: 0x4C Host Controller Root Hub Descriptor B Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[31:16] |PPCM |Port Power Control Mask + * | | |Global power switching + * | | |This field is only valid if PowerSwitchingMode is set (individual port switching) + * | | |When set, the port only responds to individual port power switching commands (Set/Clear Port Power) + * | | |When cleared, the port only responds to global power switching commands (Set/Clear Global Power). + * | | |0 = Port power controlled by global power switching. + * | | |1 = Port power controlled by port power switching. + * | | |Note: PPCM[15:2] and PPCM[0] are reserved. + * @var USBH_T::HcRhStatus + * Offset: 0x50 Host Controller Root Hub Status Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[0] |LPS |Clear Global Power + * | | |In global power mode (PSM (HcRhDescriptorA[8]) = 0), this bit is written to one to clear all ports' power. + * | | |This bit always read as zero. + * | | |Write Operation: + * | | |0 = No effect. + * | | |1 = Clear global power. + * |[1] |OCI |Overcurrent Indicator (Read Only) + * | | |This bit reflects the state of the overcurrent status pin + * | | |This field is only valid if NOCP (HcRhDescriptorA[12]) and OCPM (HcRhDescriptorA[11]) are cleared. + * | | |0 = No overcurrent condition. + * | | |1 = Overcurrent condition. + * |[15] |DRWE |Device Remote Wakeup Enable Bit + * | | |This bit controls if port's Connect Status Change as a remote wake-up event. + * | | |Write Operation: + * | | |0 = No effect. + * | | |1 = Connect Status Change as a remote wake-up event Enabled. + * | | |Read Operation: + * | | |0 = Connect Status Change as a remote wake-up event Disabled. + * | | |1 = Connect Status Change as a remote wake-up event Enabled. + * |[16] |LPSC |Set Global Power + * | | |In global power mode (PSM (HcRhDescriptorA[8]) = 0), this bit is written to one to enable power to all ports. + * | | |This bit always read as zero. + * | | |Write Operation: + * | | |0 = No effect. + * | | |1 = Set global power. + * |[17] |OCIC |Overcurrent Indicator Change + * | | |This bit is set by hardware when a change has occurred in OCI (HcRhStatus[1]). + * | | |Write 1 to clear this bit to zero. + * | | |0 = OCI (HcRhStatus[1]) didn't change. + * | | |1 = OCI (HcRhStatus[1]) change. + * |[31] |CRWE |Clear Remote Wake-up Enable Bit + * | | |This bit is use to clear DRWE (HcRhStatus[15]). + * | | |This bit always read as zero. + * | | |Write Operation: + * | | |0 = No effect. + * | | |1 = Clear DRWE (HcRhStatus[15]). + * @var USBH_T::HcRhPortStatus + * Offset: 0x54 Host Controller Root Hub Port Status + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[0] |CCS |Current Connect Status or Clear Port Enable + * | | |Write Operation: + * | | |0 = No effect. + * | | |1 = Clear port enable. + * | | |Read Operation: + * | | |0 = No device connected. + * | | |1 = Device connected. + * |[1] |PES |Port Enable Status or Set Port Enable + * | | |Write Operation: + * | | |0 = No effect. + * | | |1 = Set port enable. + * | | |Read Operation: + * | | |0 = Port Disabled. + * | | |1 = Port Enabled. + * |[2] |PSS |Port Suspend Status or Set Port Suspend + * | | |This bit indicates the port is suspended + * | | |Write Operation: + * | | |0 = No effect. + * | | |1 = Set port suspend. + * | | |Read Operation: + * | | |0 = Port is not suspended. + * | | |1 = Port is selectively suspended. + * |[3] |POCI |Port overcurrent Indicator or Clear Port Suspend + * | | |This bit reflects the state of the overcurrent status pin dedicated to this port + * | | |This field is only valid if NOCP (HcRhDescriptorA[12]) is cleared and OCPM (HcRhDescriptorA[11]) is set. + * | | |This bit is also used to initiate the selective result sequence for the port. + * | | |Write Operation: + * | | |0 = No effect. + * | | |1 = Clear port suspend. + * | | |Read Operation: + * | | |0 = No overcurrent condition. + * | | |1 = Overcurrent condition. + * |[4] |PRS |Port Reset Status or Set Port Reset + * | | |This bit reflects the reset state of the port. + * | | |Write Operation: + * | | |0 = No effect. + * | | |1 = Set port reset. + * | | |Read Operation + * | | |0 = Port reset signal is not active. + * | | |1 = Port reset signal is active. + * |[8] |PPS |Port Power Status or Set Port Power + * | | |This bit reflects the power state of the port regardless of the power switching mode. + * | | |Write Operation: + * | | |0 = No effect. + * | | |1 = Port Power Enabled. + * | | |Read Operation: + * | | |0 = Port power is Disabled. + * | | |1 = Port power is Enabled. + * |[9] |LSDA |Low Speed Device Attached or Clear Port Power + * | | |This bit defines the speed (and bus idle) of the attached device + * | | |It is only valid when CCS (HcRhPortStatus[0]) is set. + * | | |This bit is also used to clear port power. + * | | |Write Operation: + * | | |0 = No effect. + * | | |1 = Clear PPS (HcRhPortStatus[8]). + * | | |Read Operation: + * | | |0 = Full Speed device. + * | | |1 = Low-speed device. + * |[16] |CSC |Connect Status Change + * | | |This bit indicates connect or disconnect event has been detected (CCS (HcRhPortStatus[0]) changed). + * | | |Write 1 to clear this bit to zero. + * | | |0 = No connect/disconnect event (CCS (HcRhPortStatus[0]) didn't change). + * | | |1 = Hardware detection of connect/disconnect event (CCS (HcRhPortStatus[0]) changed). + * |[17] |PESC |Port Enable Status Change + * | | |This bit indicates that the port has been disabled (PES (HcRhPortStatus6[1]) cleared) due to a hardware event. + * | | |Write 1 to clear this bit to zero. + * | | |0 = PES (HcRhPortStatus[1]) didn't change. + * | | |1 = PES (HcRhPortStatus[1]) changed. + * |[18] |PSSC |Port Suspend Status Change + * | | |This bit indicates the completion of the selective resume sequence for the port. + * | | |Write 1 to clear this bit to zero. + * | | |0 = Port resume is not completed. + * | | |1 = Port resume completed. + * |[19] |OCIC |Port overcurrent Indicator Change + * | | |This bit is set when POCI (HcRhPortStatus[3]) changes. + * | | |Write 1 to clear this bit to zero. + * | | |0 = POCI (HcRhPortStatus[3]) didn't change. + * | | |1 = POCI (HcRhPortStatus[3]) changes. + * |[20] |PRSC |Port Reset Status Change + * | | |This bit indicates that the port reset signal has completed. + * | | |Write 1 to clear this bit to zero. + * | | |0 = Port reset is not complete. + * | | |1 = Port reset is complete. + * @var USBH_T::HcPhyControl + * Offset: 0x200 Host Controller PHY Control Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[1] |ABORT |AHB Bus ERROR Response + * | | |This bit indicates there is an ERROR response received in AHB bus. + * | | |0 = No ERROR response received. + * | | |1 = ERROR response received. + * | | |Note: This bit is cleared by writing 1 to it. + * |[3] |OCAL |Overcurrent Active Low + * | | |This bit controls the polarity of overcurrent flag from external power IC. + * | | |0 = Overcurrent flag is high active. + * | | |1 = Overcurrent flag is low active. + * |[4] |PPCAL |Port Power Control Active Low + * | | |This bit controls the polarity of port power control to external power IC. + * | | |0 = Port power control is high active. + * | | |1 = Port power control is low active. + * |[16] |DPRT1 |Disable Port 1 + * | | |This bit controls if the connection between USB host controller and transceiver of port 1 is disabled + * | | |If the connection is disabled, the USB host controller will not recognize any event of USB bus. + * | | |Set this bit high, the transceiver of port 1 will also be forced into the standby mode no matter what USB host controller operation is. + * | | |0 = The connection between USB host controller and transceiver of port 1 Enabled. + * | | |1 = The connection between USB host controller and transceiver of port 1 Disabled and the transceiver of port 1 will also be forced into the standby mode. + */ + __I uint32_t HcRevision; /*!< [0x0000] Host Controller Revision Register */ + __IO uint32_t HcControl; /*!< [0x0004] Host Controller Control Register */ + __IO uint32_t HcCommandStatus; /*!< [0x0008] Host Controller Command Status Register */ + __IO uint32_t HcInterruptStatus; /*!< [0x000c] Host Controller Interrupt Status Register */ + __IO uint32_t HcInterruptEnable; /*!< [0x0010] Host Controller Interrupt Enable Register */ + __IO uint32_t HcInterruptDisable; /*!< [0x0014] Host Controller Interrupt Disable Register */ + __IO uint32_t HcHCCA; /*!< [0x0018] Host Controller Communication Area Register */ + __IO uint32_t HcPeriodCurrentED; /*!< [0x001c] Host Controller Period Current ED Register */ + __IO uint32_t HcControlHeadED; /*!< [0x0020] Host Controller Control Head ED Register */ + __IO uint32_t HcControlCurrentED; /*!< [0x0024] Host Controller Control Current ED Register */ + __IO uint32_t HcBulkHeadED; /*!< [0x0028] Host Controller Bulk Head ED Register */ + __IO uint32_t HcBulkCurrentED; /*!< [0x002c] Host Controller Bulk Current ED Register */ + __IO uint32_t HcDoneHead; /*!< [0x0030] Host Controller Done Head Register */ + __IO uint32_t HcFmInterval; /*!< [0x0034] Host Controller Frame Interval Register */ + __I uint32_t HcFmRemaining; /*!< [0x0038] Host Controller Frame Remaining Register */ + __I uint32_t HcFmNumber; /*!< [0x003c] Host Controller Frame Number Register */ + __IO uint32_t HcPeriodicStart; /*!< [0x0040] Host Controller Periodic Start Register */ + __IO uint32_t HcLSThreshold; /*!< [0x0044] Host Controller Low-speed Threshold Register */ + __IO uint32_t HcRhDescriptorA; /*!< [0x0048] Host Controller Root Hub Descriptor A Register */ + __IO uint32_t HcRhDescriptorB; /*!< [0x004c] Host Controller Root Hub Descriptor B Register */ + __IO uint32_t HcRhStatus; /*!< [0x0050] Host Controller Root Hub Status Register */ + __IO uint32_t HcRhPortStatus[1]; /*!< [0x0054] Host Controller Root Hub Port Status */ + __I uint32_t RESERVE0[106]; + __IO uint32_t HcPhyControl; /*!< [0x0200] Host Controller PHY Control Register */ + +} USBH_T; + +/** + @addtogroup USBH_CONST USBH Bit Field Definition + Constant Definitions for USBH Controller +@{ */ + +#define USBH_HcRevision_REV_Pos (0) /*!< USBH_T::HcRevision: REV Position */ +#define USBH_HcRevision_REV_Msk (0xfful << USBH_HcRevision_REV_Pos) /*!< USBH_T::HcRevision: REV Mask */ + +#define USBH_HcControl_CBSR_Pos (0) /*!< USBH_T::HcControl: CBSR Position */ +#define USBH_HcControl_CBSR_Msk (0x3ul << USBH_HcControl_CBSR_Pos) /*!< USBH_T::HcControl: CBSR Mask */ + +#define USBH_HcControl_PLE_Pos (2) /*!< USBH_T::HcControl: PLE Position */ +#define USBH_HcControl_PLE_Msk (0x1ul << USBH_HcControl_PLE_Pos) /*!< USBH_T::HcControl: PLE Mask */ + +#define USBH_HcControl_IE_Pos (3) /*!< USBH_T::HcControl: IE Position */ +#define USBH_HcControl_IE_Msk (0x1ul << USBH_HcControl_IE_Pos) /*!< USBH_T::HcControl: IE Mask */ + +#define USBH_HcControl_CLE_Pos (4) /*!< USBH_T::HcControl: CLE Position */ +#define USBH_HcControl_CLE_Msk (0x1ul << USBH_HcControl_CLE_Pos) /*!< USBH_T::HcControl: CLE Mask */ + +#define USBH_HcControl_BLE_Pos (5) /*!< USBH_T::HcControl: BLE Position */ +#define USBH_HcControl_BLE_Msk (0x1ul << USBH_HcControl_BLE_Pos) /*!< USBH_T::HcControl: BLE Mask */ + +#define USBH_HcControl_HCFS_Pos (6) /*!< USBH_T::HcControl: HCFS Position */ +#define USBH_HcControl_HCFS_Msk (0x3ul << USBH_HcControl_HCFS_Pos) /*!< USBH_T::HcControl: HCFS Mask */ + +#define USBH_HcCommandStatus_HCR_Pos (0) /*!< USBH_T::HcCommandStatus: HCR Position*/ +#define USBH_HcCommandStatus_HCR_Msk (0x1ul << USBH_HcCommandStatus_HCR_Pos) /*!< USBH_T::HcCommandStatus: HCR Mask */ + +#define USBH_HcCommandStatus_CLF_Pos (1) /*!< USBH_T::HcCommandStatus: CLF Position*/ +#define USBH_HcCommandStatus_CLF_Msk (0x1ul << USBH_HcCommandStatus_CLF_Pos) /*!< USBH_T::HcCommandStatus: CLF Mask */ + +#define USBH_HcCommandStatus_BLF_Pos (2) /*!< USBH_T::HcCommandStatus: BLF Position*/ +#define USBH_HcCommandStatus_BLF_Msk (0x1ul << USBH_HcCommandStatus_BLF_Pos) /*!< USBH_T::HcCommandStatus: BLF Mask */ + +#define USBH_HcCommandStatus_SOC_Pos (16) /*!< USBH_T::HcCommandStatus: SOC Position*/ +#define USBH_HcCommandStatus_SOC_Msk (0x3ul << USBH_HcCommandStatus_SOC_Pos) /*!< USBH_T::HcCommandStatus: SOC Mask */ + +#define USBH_HcInterruptStatus_SO_Pos (0) /*!< USBH_T::HcInterruptStatus: SO Position*/ +#define USBH_HcInterruptStatus_SO_Msk (0x1ul << USBH_HcInterruptStatus_SO_Pos) /*!< USBH_T::HcInterruptStatus: SO Mask */ + +#define USBH_HcInterruptStatus_WDH_Pos (1) /*!< USBH_T::HcInterruptStatus: WDH Position*/ +#define USBH_HcInterruptStatus_WDH_Msk (0x1ul << USBH_HcInterruptStatus_WDH_Pos) /*!< USBH_T::HcInterruptStatus: WDH Mask */ + +#define USBH_HcInterruptStatus_SF_Pos (2) /*!< USBH_T::HcInterruptStatus: SF Position*/ +#define USBH_HcInterruptStatus_SF_Msk (0x1ul << USBH_HcInterruptStatus_SF_Pos) /*!< USBH_T::HcInterruptStatus: SF Mask */ + +#define USBH_HcInterruptStatus_RD_Pos (3) /*!< USBH_T::HcInterruptStatus: RD Position*/ +#define USBH_HcInterruptStatus_RD_Msk (0x1ul << USBH_HcInterruptStatus_RD_Pos) /*!< USBH_T::HcInterruptStatus: RD Mask */ + +#define USBH_HcInterruptStatus_FNO_Pos (5) /*!< USBH_T::HcInterruptStatus: FNO Position*/ +#define USBH_HcInterruptStatus_FNO_Msk (0x1ul << USBH_HcInterruptStatus_FNO_Pos) /*!< USBH_T::HcInterruptStatus: FNO Mask */ + +#define USBH_HcInterruptStatus_RHSC_Pos (6) /*!< USBH_T::HcInterruptStatus: RHSC Position*/ +#define USBH_HcInterruptStatus_RHSC_Msk (0x1ul << USBH_HcInterruptStatus_RHSC_Pos) /*!< USBH_T::HcInterruptStatus: RHSC Mask */ + +#define USBH_HcInterruptEnable_SO_Pos (0) /*!< USBH_T::HcInterruptEnable: SO Position*/ +#define USBH_HcInterruptEnable_SO_Msk (0x1ul << USBH_HcInterruptEnable_SO_Pos) /*!< USBH_T::HcInterruptEnable: SO Mask */ + +#define USBH_HcInterruptEnable_WDH_Pos (1) /*!< USBH_T::HcInterruptEnable: WDH Position*/ +#define USBH_HcInterruptEnable_WDH_Msk (0x1ul << USBH_HcInterruptEnable_WDH_Pos) /*!< USBH_T::HcInterruptEnable: WDH Mask */ + +#define USBH_HcInterruptEnable_SF_Pos (2) /*!< USBH_T::HcInterruptEnable: SF Position*/ +#define USBH_HcInterruptEnable_SF_Msk (0x1ul << USBH_HcInterruptEnable_SF_Pos) /*!< USBH_T::HcInterruptEnable: SF Mask */ + +#define USBH_HcInterruptEnable_RD_Pos (3) /*!< USBH_T::HcInterruptEnable: RD Position*/ +#define USBH_HcInterruptEnable_RD_Msk (0x1ul << USBH_HcInterruptEnable_RD_Pos) /*!< USBH_T::HcInterruptEnable: RD Mask */ + +#define USBH_HcInterruptEnable_FNO_Pos (5) /*!< USBH_T::HcInterruptEnable: FNO Position*/ +#define USBH_HcInterruptEnable_FNO_Msk (0x1ul << USBH_HcInterruptEnable_FNO_Pos) /*!< USBH_T::HcInterruptEnable: FNO Mask */ + +#define USBH_HcInterruptEnable_RHSC_Pos (6) /*!< USBH_T::HcInterruptEnable: RHSC Position*/ +#define USBH_HcInterruptEnable_RHSC_Msk (0x1ul << USBH_HcInterruptEnable_RHSC_Pos) /*!< USBH_T::HcInterruptEnable: RHSC Mask */ + +#define USBH_HcInterruptEnable_MIE_Pos (31) /*!< USBH_T::HcInterruptEnable: MIE Position*/ +#define USBH_HcInterruptEnable_MIE_Msk (0x1ul << USBH_HcInterruptEnable_MIE_Pos) /*!< USBH_T::HcInterruptEnable: MIE Mask */ + +#define USBH_HcInterruptDisable_SO_Pos (0) /*!< USBH_T::HcInterruptDisable: SO Position*/ +#define USBH_HcInterruptDisable_SO_Msk (0x1ul << USBH_HcInterruptDisable_SO_Pos) /*!< USBH_T::HcInterruptDisable: SO Mask */ + +#define USBH_HcInterruptDisable_WDH_Pos (1) /*!< USBH_T::HcInterruptDisable: WDH Position*/ +#define USBH_HcInterruptDisable_WDH_Msk (0x1ul << USBH_HcInterruptDisable_WDH_Pos) /*!< USBH_T::HcInterruptDisable: WDH Mask */ + +#define USBH_HcInterruptDisable_SF_Pos (2) /*!< USBH_T::HcInterruptDisable: SF Position*/ +#define USBH_HcInterruptDisable_SF_Msk (0x1ul << USBH_HcInterruptDisable_SF_Pos) /*!< USBH_T::HcInterruptDisable: SF Mask */ + +#define USBH_HcInterruptDisable_RD_Pos (3) /*!< USBH_T::HcInterruptDisable: RD Position*/ +#define USBH_HcInterruptDisable_RD_Msk (0x1ul << USBH_HcInterruptDisable_RD_Pos) /*!< USBH_T::HcInterruptDisable: RD Mask */ + +#define USBH_HcInterruptDisable_FNO_Pos (5) /*!< USBH_T::HcInterruptDisable: FNO Position*/ +#define USBH_HcInterruptDisable_FNO_Msk (0x1ul << USBH_HcInterruptDisable_FNO_Pos) /*!< USBH_T::HcInterruptDisable: FNO Mask */ + +#define USBH_HcInterruptDisable_RHSC_Pos (6) /*!< USBH_T::HcInterruptDisable: RHSC Position*/ +#define USBH_HcInterruptDisable_RHSC_Msk (0x1ul << USBH_HcInterruptDisable_RHSC_Pos) /*!< USBH_T::HcInterruptDisable: RHSC Mask*/ + +#define USBH_HcInterruptDisable_MIE_Pos (31) /*!< USBH_T::HcInterruptDisable: MIE Position*/ +#define USBH_HcInterruptDisable_MIE_Msk (0x1ul << USBH_HcInterruptDisable_MIE_Pos) /*!< USBH_T::HcInterruptDisable: MIE Mask */ + +#define USBH_HcHCCA_HCCA_Pos (8) /*!< USBH_T::HcHCCA: HCCA Position */ +#define USBH_HcHCCA_HCCA_Msk (0xfffffful << USBH_HcHCCA_HCCA_Pos) /*!< USBH_T::HcHCCA: HCCA Mask */ + +#define USBH_HcPeriodCurrentED_PCED_Pos (4) /*!< USBH_T::HcPeriodCurrentED: PCED Position*/ +#define USBH_HcPeriodCurrentED_PCED_Msk (0xffffffful << USBH_HcPeriodCurrentED_PCED_Pos) /*!< USBH_T::HcPeriodCurrentED: PCED Mask */ + +#define USBH_HcControlHeadED_CHED_Pos (4) /*!< USBH_T::HcControlHeadED: CHED Position*/ +#define USBH_HcControlHeadED_CHED_Msk (0xffffffful << USBH_HcControlHeadED_CHED_Pos) /*!< USBH_T::HcControlHeadED: CHED Mask */ + +#define USBH_HcControlCurrentED_CCED_Pos (4) /*!< USBH_T::HcControlCurrentED: CCED Position*/ +#define USBH_HcControlCurrentED_CCED_Msk (0xffffffful << USBH_HcControlCurrentED_CCED_Pos) /*!< USBH_T::HcControlCurrentED: CCED Mask*/ + +#define USBH_HcBulkHeadED_BHED_Pos (4) /*!< USBH_T::HcBulkHeadED: BHED Position */ +#define USBH_HcBulkHeadED_BHED_Msk (0xffffffful << USBH_HcBulkHeadED_BHED_Pos) /*!< USBH_T::HcBulkHeadED: BHED Mask */ + +#define USBH_HcBulkCurrentED_BCED_Pos (4) /*!< USBH_T::HcBulkCurrentED: BCED Position*/ +#define USBH_HcBulkCurrentED_BCED_Msk (0xffffffful << USBH_HcBulkCurrentED_BCED_Pos) /*!< USBH_T::HcBulkCurrentED: BCED Mask */ + +#define USBH_HcDoneHead_DH_Pos (4) /*!< USBH_T::HcDoneHead: DH Position */ +#define USBH_HcDoneHead_DH_Msk (0xffffffful << USBH_HcDoneHead_DH_Pos) /*!< USBH_T::HcDoneHead: DH Mask */ + +#define USBH_HcFmInterval_FI_Pos (0) /*!< USBH_T::HcFmInterval: FI Position */ +#define USBH_HcFmInterval_FI_Msk (0x3ffful << USBH_HcFmInterval_FI_Pos) /*!< USBH_T::HcFmInterval: FI Mask */ + +#define USBH_HcFmInterval_FSMPS_Pos (16) /*!< USBH_T::HcFmInterval: FSMPS Position */ +#define USBH_HcFmInterval_FSMPS_Msk (0x3ffful << USBH_HcFmInterval_FSMPS_Pos) /*!< USBH_T::HcFmInterval: FSMPS Mask */ + +#define USBH_HcFmInterval_FIT_Pos (31) /*!< USBH_T::HcFmInterval: FIT Position */ +#define USBH_HcFmInterval_FIT_Msk (0x1ul << USBH_HcFmInterval_FIT_Pos) /*!< USBH_T::HcFmInterval: FIT Mask */ + +#define USBH_HcFmRemaining_FR_Pos (0) /*!< USBH_T::HcFmRemaining: FR Position */ +#define USBH_HcFmRemaining_FR_Msk (0x3ffful << USBH_HcFmRemaining_FR_Pos) /*!< USBH_T::HcFmRemaining: FR Mask */ + +#define USBH_HcFmRemaining_FRT_Pos (31) /*!< USBH_T::HcFmRemaining: FRT Position */ +#define USBH_HcFmRemaining_FRT_Msk (0x1ul << USBH_HcFmRemaining_FRT_Pos) /*!< USBH_T::HcFmRemaining: FRT Mask */ + +#define USBH_HcFmNumber_FN_Pos (0) /*!< USBH_T::HcFmNumber: FN Position */ +#define USBH_HcFmNumber_FN_Msk (0xfffful << USBH_HcFmNumber_FN_Pos) /*!< USBH_T::HcFmNumber: FN Mask */ + +#define USBH_HcPeriodicStart_PS_Pos (0) /*!< USBH_T::HcPeriodicStart: PS Position */ +#define USBH_HcPeriodicStart_PS_Msk (0x3ffful << USBH_HcPeriodicStart_PS_Pos) /*!< USBH_T::HcPeriodicStart: PS Mask */ + +#define USBH_HcLSThreshold_LST_Pos (0) /*!< USBH_T::HcLSThreshold: LST Position */ +#define USBH_HcLSThreshold_LST_Msk (0xffful << USBH_HcLSThreshold_LST_Pos) /*!< USBH_T::HcLSThreshold: LST Mask */ + +#define USBH_HcRhDescriptorA_NDP_Pos (0) /*!< USBH_T::HcRhDescriptorA: NDP Position*/ +#define USBH_HcRhDescriptorA_NDP_Msk (0xfful << USBH_HcRhDescriptorA_NDP_Pos) /*!< USBH_T::HcRhDescriptorA: NDP Mask */ + +#define USBH_HcRhDescriptorA_PSM_Pos (8) /*!< USBH_T::HcRhDescriptorA: PSM Position*/ +#define USBH_HcRhDescriptorA_PSM_Msk (0x1ul << USBH_HcRhDescriptorA_PSM_Pos) /*!< USBH_T::HcRhDescriptorA: PSM Mask */ + +#define USBH_HcRhDescriptorA_OCPM_Pos (11) /*!< USBH_T::HcRhDescriptorA: OCPM Position*/ +#define USBH_HcRhDescriptorA_OCPM_Msk (0x1ul << USBH_HcRhDescriptorA_OCPM_Pos) /*!< USBH_T::HcRhDescriptorA: OCPM Mask */ + +#define USBH_HcRhDescriptorA_NOCP_Pos (12) /*!< USBH_T::HcRhDescriptorA: NOCP Position*/ +#define USBH_HcRhDescriptorA_NOCP_Msk (0x1ul << USBH_HcRhDescriptorA_NOCP_Pos) /*!< USBH_T::HcRhDescriptorA: NOCP Mask */ + +#define USBH_HcRhDescriptorB_PPCM_Pos (16) /*!< USBH_T::HcRhDescriptorB: PPCM Position*/ +#define USBH_HcRhDescriptorB_PPCM_Msk (0xfffful << USBH_HcRhDescriptorB_PPCM_Pos) /*!< USBH_T::HcRhDescriptorB: PPCM Mask */ + +#define USBH_HcRhStatus_LPS_Pos (0) /*!< USBH_T::HcRhStatus: LPS Position */ +#define USBH_HcRhStatus_LPS_Msk (0x1ul << USBH_HcRhStatus_LPS_Pos) /*!< USBH_T::HcRhStatus: LPS Mask */ + +#define USBH_HcRhStatus_OCI_Pos (1) /*!< USBH_T::HcRhStatus: OCI Position */ +#define USBH_HcRhStatus_OCI_Msk (0x1ul << USBH_HcRhStatus_OCI_Pos) /*!< USBH_T::HcRhStatus: OCI Mask */ + +#define USBH_HcRhStatus_DRWE_Pos (15) /*!< USBH_T::HcRhStatus: DRWE Position */ +#define USBH_HcRhStatus_DRWE_Msk (0x1ul << USBH_HcRhStatus_DRWE_Pos) /*!< USBH_T::HcRhStatus: DRWE Mask */ + +#define USBH_HcRhStatus_LPSC_Pos (16) /*!< USBH_T::HcRhStatus: LPSC Position */ +#define USBH_HcRhStatus_LPSC_Msk (0x1ul << USBH_HcRhStatus_LPSC_Pos) /*!< USBH_T::HcRhStatus: LPSC Mask */ + +#define USBH_HcRhStatus_OCIC_Pos (17) /*!< USBH_T::HcRhStatus: OCIC Position */ +#define USBH_HcRhStatus_OCIC_Msk (0x1ul << USBH_HcRhStatus_OCIC_Pos) /*!< USBH_T::HcRhStatus: OCIC Mask */ + +#define USBH_HcRhStatus_CRWE_Pos (31) /*!< USBH_T::HcRhStatus: CRWE Position */ +#define USBH_HcRhStatus_CRWE_Msk (0x1ul << USBH_HcRhStatus_CRWE_Pos) /*!< USBH_T::HcRhStatus: CRWE Mask */ + +#define USBH_HcRhPortStatus_CCS_Pos (0) /*!< USBH_T::HcRhPortStatus: CCS Position */ +#define USBH_HcRhPortStatus_CCS_Msk (0x1ul << USBH_HcRhPortStatus_CCS_Pos) /*!< USBH_T::HcRhPortStatus: CCS Mask */ + +#define USBH_HcRhPortStatus_PES_Pos (1) /*!< USBH_T::HcRhPortStatus: PES Position */ +#define USBH_HcRhPortStatus_PES_Msk (0x1ul << USBH_HcRhPortStatus_PES_Pos) /*!< USBH_T::HcRhPortStatus: PES Mask */ + +#define USBH_HcRhPortStatus_PSS_Pos (2) /*!< USBH_T::HcRhPortStatus: PSS Position */ +#define USBH_HcRhPortStatus_PSS_Msk (0x1ul << USBH_HcRhPortStatus_PSS_Pos) /*!< USBH_T::HcRhPortStatus: PSS Mask */ + +#define USBH_HcRhPortStatus_POCI_Pos (3) /*!< USBH_T::HcRhPortStatus: POCI Position*/ +#define USBH_HcRhPortStatus_POCI_Msk (0x1ul << USBH_HcRhPortStatus_POCI_Pos) /*!< USBH_T::HcRhPortStatus: POCI Mask */ + +#define USBH_HcRhPortStatus_PRS_Pos (4) /*!< USBH_T::HcRhPortStatus: PRS Position */ +#define USBH_HcRhPortStatus_PRS_Msk (0x1ul << USBH_HcRhPortStatus_PRS_Pos) /*!< USBH_T::HcRhPortStatus: PRS Mask */ + +#define USBH_HcRhPortStatus_PPS_Pos (8) /*!< USBH_T::HcRhPortStatus: PPS Position */ +#define USBH_HcRhPortStatus_PPS_Msk (0x1ul << USBH_HcRhPortStatus_PPS_Pos) /*!< USBH_T::HcRhPortStatus: PPS Mask */ + +#define USBH_HcRhPortStatus_LSDA_Pos (9) /*!< USBH_T::HcRhPortStatus: LSDA Position*/ +#define USBH_HcRhPortStatus_LSDA_Msk (0x1ul << USBH_HcRhPortStatus_LSDA_Pos) /*!< USBH_T::HcRhPortStatus: LSDA Mask */ + +#define USBH_HcRhPortStatus_CSC_Pos (16) /*!< USBH_T::HcRhPortStatus: CSC Position */ +#define USBH_HcRhPortStatus_CSC_Msk (0x1ul << USBH_HcRhPortStatus_CSC_Pos) /*!< USBH_T::HcRhPortStatus: CSC Mask */ + +#define USBH_HcRhPortStatus_PESC_Pos (17) /*!< USBH_T::HcRhPortStatus: PESC Position*/ +#define USBH_HcRhPortStatus_PESC_Msk (0x1ul << USBH_HcRhPortStatus_PESC_Pos) /*!< USBH_T::HcRhPortStatus: PESC Mask */ + +#define USBH_HcRhPortStatus_PSSC_Pos (18) /*!< USBH_T::HcRhPortStatus: PSSC Position*/ +#define USBH_HcRhPortStatus_PSSC_Msk (0x1ul << USBH_HcRhPortStatus_PSSC_Pos) /*!< USBH_T::HcRhPortStatus: PSSC Mask */ + +#define USBH_HcRhPortStatus_OCIC_Pos (19) /*!< USBH_T::HcRhPortStatus: OCIC Position*/ +#define USBH_HcRhPortStatus_OCIC_Msk (0x1ul << USBH_HcRhPortStatus_OCIC_Pos) /*!< USBH_T::HcRhPortStatus: OCIC Mask */ + +#define USBH_HcRhPortStatus_PRSC_Pos (20) /*!< USBH_T::HcRhPortStatus: PRSC Position*/ +#define USBH_HcRhPortStatus_PRSC_Msk (0x1ul << USBH_HcRhPortStatus_PRSC_Pos) /*!< USBH_T::HcRhPortStatus: PRSC Mask */ + +#define USBH_HcPhyControl_ABORT_Pos (1) /*!< USBH_T::HcPhyControl: ABORT Position */ +#define USBH_HcPhyControl_ABORT_Msk (0x1ul << USBH_HcPhyControl_ABORT_Pos) /*!< USBH_T::HcPhyControl: ABORT Mask */ + +#define USBH_HcPhyControl_OCAL_Pos (3) /*!< USBH_T::HcPhyControl: OCAL Position */ +#define USBH_HcPhyControl_OCAL_Msk (0x1ul << USBH_HcPhyControl_OCAL_Pos) /*!< USBH_T::HcPhyControl: OCAL Mask */ + +#define USBH_HcPhyControl_PPCAL_Pos (4) /*!< USBH_T::HcPhyControl: PPCAL Position */ +#define USBH_HcPhyControl_PPCAL_Msk (0x1ul << USBH_HcPhyControl_PPCAL_Pos) /*!< USBH_T::HcPhyControl: PPCAL Mask */ + +#define USBH_HcPhyControl_DPRT1_Pos (16) /*!< USBH_T::HcPhyControl: DPRT1 Position */ +#define USBH_HcPhyControl_DPRT1_Msk (0x1ul << USBH_HcPhyControl_DPRT1_Pos) /*!< USBH_T::HcPhyControl: DPRT1 Mask */ + +/**@}*/ /* USBH_CONST */ +/**@}*/ /* end of USBH register group */ +/**@}*/ /* end of REGISTER group */ + +#if defined ( __CC_ARM ) + #pragma no_anon_unions +#endif + +#endif /* __USBH_REG_H__ */ diff --git a/bsp/nuvoton/libraries/ma35/Device/Nuvoton/MA35D1/Include/wdt_reg.h b/bsp/nuvoton/libraries/ma35/Device/Nuvoton/MA35D1/Include/wdt_reg.h new file mode 100644 index 0000000000..e621d5c7fe --- /dev/null +++ b/bsp/nuvoton/libraries/ma35/Device/Nuvoton/MA35D1/Include/wdt_reg.h @@ -0,0 +1,179 @@ +/**************************************************************************//** + * @file wdt_reg.h + * @brief WDT register definition header file + * + * SPDX-License-Identifier: Apache-2.0 + * @copyright (C) 2020 Nuvoton Technology Corp. All rights reserved. + *****************************************************************************/ +#ifndef __WDT_REG_H__ +#define __WDT_REG_H__ + +#if defined ( __CC_ARM ) + #pragma anon_unions +#endif + +/** + @addtogroup REGISTER Control Register + @{ +*/ + +/** + @addtogroup WDT Watch Dog Timer Controller(WDT) + Memory Mapped Structure for WDT Controller +@{ */ + +typedef struct +{ + + + /** + * @var WDT_T::CTL + * Offset: 0x00 WDT Control Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[1] |RSTEN |WDT Time-out Reset Enable Bit (Write Protect) + * | | |Setting this bit will enable the WDT time-out reset function if the WDT up counter value has not been cleared after the specific WDT reset delay period expires. + * | | |0 = WDT time-out reset function Disabled. + * | | |1 = WDT time-out reset function Enabled. + * | | |Note: This bit is write protected + * | | |Refer to the SYS_RLKTZS register or SYS_RLKTZNS register or SYS_RLKSUBM register. + * |[2] |RSTF |WDT Time-out Reset Flag + * | | |This bit indicates the system has been reset by WDT time-out reset or not. + * | | |0 = WDT time-out reset did not occur. + * | | |1 = WDT time-out reset occurred. + * | | |Note: This bit is cleared by writing 1 to it. + * |[3] |IF |WDT Time-out Interrupt Flag + * | | |This bit will be set to 1 while WDT up counter value reaches the selected WDT time-out interval. + * | | |0 = WDT time-out interrupt did not occur. + * | | |1 = WDT time-out interrupt occurred. + * | | |Note: This bit is cleared by writing 1 to it. + * |[4] |WKEN |WDT Time-out Wake-up Function Control (Write Protect) + * | | |If this bit is set to 1, while WDT time-out interrupt flag IF (WDT_CTL[3]) is generated to 1 and interrupt enable bit INTEN (WDT_CTL[6]) is enabled, the WDT time-out interrupt signal will generate a wake-up trigger event to chip. + * | | |0 = Wake-up trigger event Disabled if WDT time-out interrupt signal generated. + * | | |1 = Wake-up trigger event Enabled if WDT time-out interrupt signal generated. + * | | |Note 1: This bit is write protected + * | | |Refer to the SYS_RLKTZS register or SYS_RLKTZNS register or SYS_RLKSUBM register. + * | | |Note 2: Chip can be woken up by WDT time-out interrupt signal generated only if WDT clock source is selected to 32 kHz internal low speed RC oscillator (LIRC) or LXT. + * |[5] |WKF |WDT Time-out Wake-up Flag + * | | |This bit indicates the interrupt wake-up flag status of WDT + * | | |0 = WDT does not cause chip wake-up. + * | | |1 = Chip wake-up from Idle or Power-down mode if WDT time-out interrupt signal generated. + * | | |Note: This bit is cleared by writing 1 to it. + * |[6] |INTEN |WDT Time-out Interrupt Enable Bit (Write Protect) + * | | |If this bit is enabled, the WDT time-out interrupt signal is generated and inform to CPU. + * | | |0 = WDT time-out interrupt Disabled. + * | | |1 = WDT time-out interrupt Enabled. + * | | |Note: This bit is write protected + * | | |Refer to the SYS_RLKTZS register or SYS_RLKTZNS register or SYS_RLKSUBM register. + * |[7] |WDTEN |WDT Enable Bit (Write Protect) + * | | |0 = WDT Disabled (This action will reset the internal up counter value). + * | | |1 = WDT Enabled. + * | | |Note 1: This bit is write protected + * | | |Refer to the SYS_RLKTZS register or SYS_RLKTZNS register or SYS_RLKSUBM register. + * | | |Note 2: If CWDTEN[2:0] (combined by Config0[31] and Config0[4:3]) bits is not configured to 111, this bit is forced as 1 and user cannot change this bit to 0. + * |[11:8] |TOUTSEL |WDT Time-out Interval Selection (Write Protect) + * | | |These three bits select the time-out interval period for the WDT. + * | | |0000 = 24 * WDT_CLK. + * | | |0001 = 26 * WDT_CLK. + * | | |0010 = 28 * WDT_CLK. + * | | |0011 = 210 * WDT_CLK. + * | | |0100= 212 * WDT_CLK. + * | | |0101 = 214 * WDT_CLK. + * | | |0110 = 216 * WDT_CLK. + * | | |0111 = 218 * WDT_CLK. + * | | |1000 = 220 * WDT_CLK. + * | | |Note: This bit is write protected + * | | |Refer to the SYS_RLKTZS register or SYS_RLKTZNS register or SYS_RLKSUBM register. + * |[30] |SYNC |WDT Enable Control SYNC Flag Indicator (Read Only) + * | | |If user executes enable/disable WDTEN (WDT_CTL[7]), this flag can be indicated enable/disable WDTEN function is completed or not. + * | | |0 = Set WDTEN bit is completed. + * | | |1 = Set WDTEN bit is synchronizing and not become active yet. + * | | |Note: Performing enable or disable WDTEN bit needs 2 * WDT_CLK period to become active. + * |[31] |ICEDEBUG |ICE Debug Mode Acknowledge Disable Bit (Write Protect) + * | | |0 = ICE debug mode acknowledgement affects WDT counting. + * | | |WDT up counter will be held while CPU is held by ICE. + * | | |1 = ICE debug mode acknowledgement Disabled. + * | | |WDT up counter will keep going no matter CPU is held by ICE or not. + * | | |Note: This bit is write protected + * | | |Refer to the SYS_RLKTZS register or SYS_RLKTZNS register or SYS_RLKSUBM register + * @var WDT_T::ALTCTL + * Offset: 0x04 WDT Alternative Control Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[1:0] |RSTDSEL |WDT Reset Delay Selection (Write Protect) + * | | |When WDT time-out happened, user has a time named WDT Reset Delay Period to clear WDT counter by programming 0x5AA5 to RSTCNT to prevent WDT time-out reset happened. + * | | |User can select a suitable setting of RSTDSEL for different WDT Reset Delay Period. + * | | |00 = WDT Reset Delay Period is 1026 * WDT_CLK. + * | | |01 = WDT Reset Delay Period is 130 * WDT_CLK. + * | | |10 = WDT Reset Delay Period is 18 * WDT_CLK. + * | | |11 = WDT Reset Delay Period is 3 * WDT_CLK. + * | | |Note 1: This bit is write protected + * | | |Refer to the SYS_RLKTZS register or SYS_RLKTZNS register or SYS_RLKSUBM register. + * | | |Note 2: This register will be reset to 0 if WDT time-out reset happened. + * @var WDT_T::RSTCNT + * Offset: 0x08 WDT Reset Counter Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[31:0] |RSTCNT |WDT Reset Counter Register + * | | |Writing 0x00005AA5 to this field will reset the internal 20-bit WDT up counter value to 0. + * | | |Note: Performing RSTCNT to reset counter needs 2 * WDT_CLK period to become active. + */ + __IO uint32_t CTL; /*!< [0x0000] WDT Control Register */ + __IO uint32_t ALTCTL; /*!< [0x0004] WDT Alternative Control Register */ + __O uint32_t RSTCNT; /*!< [0x0008] WDT Reset Counter Register */ + +} WDT_T; + +/** + @addtogroup WDT_CONST WDT Bit Field Definition + Constant Definitions for WDT Controller +@{ */ + +#define WDT_CTL_RSTEN_Pos (1) /*!< WDT_T::CTL: RSTEN Position */ +#define WDT_CTL_RSTEN_Msk (0x1ul << WDT_CTL_RSTEN_Pos) /*!< WDT_T::CTL: RSTEN Mask */ + +#define WDT_CTL_RSTF_Pos (2) /*!< WDT_T::CTL: RSTF Position */ +#define WDT_CTL_RSTF_Msk (0x1ul << WDT_CTL_RSTF_Pos) /*!< WDT_T::CTL: RSTF Mask */ + +#define WDT_CTL_IF_Pos (3) /*!< WDT_T::CTL: IF Position */ +#define WDT_CTL_IF_Msk (0x1ul << WDT_CTL_IF_Pos) /*!< WDT_T::CTL: IF Mask */ + +#define WDT_CTL_WKEN_Pos (4) /*!< WDT_T::CTL: WKEN Position */ +#define WDT_CTL_WKEN_Msk (0x1ul << WDT_CTL_WKEN_Pos) /*!< WDT_T::CTL: WKEN Mask */ + +#define WDT_CTL_WKF_Pos (5) /*!< WDT_T::CTL: WKF Position */ +#define WDT_CTL_WKF_Msk (0x1ul << WDT_CTL_WKF_Pos) /*!< WDT_T::CTL: WKF Mask */ + +#define WDT_CTL_INTEN_Pos (6) /*!< WDT_T::CTL: INTEN Position */ +#define WDT_CTL_INTEN_Msk (0x1ul << WDT_CTL_INTEN_Pos) /*!< WDT_T::CTL: INTEN Mask */ + +#define WDT_CTL_WDTEN_Pos (7) /*!< WDT_T::CTL: WDTEN Position */ +#define WDT_CTL_WDTEN_Msk (0x1ul << WDT_CTL_WDTEN_Pos) /*!< WDT_T::CTL: WDTEN Mask */ + +#define WDT_CTL_TOUTSEL_Pos (8) /*!< WDT_T::CTL: TOUTSEL Position */ +#define WDT_CTL_TOUTSEL_Msk (0xful << WDT_CTL_TOUTSEL_Pos) /*!< WDT_T::CTL: TOUTSEL Mask */ + +#define WDT_CTL_SYNC_Pos (30) /*!< WDT_T::CTL: SYNC Position */ +#define WDT_CTL_SYNC_Msk (0x1ul << WDT_CTL_SYNC_Pos) /*!< WDT_T::CTL: SYNC Mask */ + +#define WDT_CTL_ICEDEBUG_Pos (31) /*!< WDT_T::CTL: ICEDEBUG Position */ +#define WDT_CTL_ICEDEBUG_Msk (0x1ul << WDT_CTL_ICEDEBUG_Pos) /*!< WDT_T::CTL: ICEDEBUG Mask */ + +#define WDT_ALTCTL_RSTDSEL_Pos (0) /*!< WDT_T::ALTCTL: RSTDSEL Position */ +#define WDT_ALTCTL_RSTDSEL_Msk (0x3ul << WDT_ALTCTL_RSTDSEL_Pos) /*!< WDT_T::ALTCTL: RSTDSEL Mask */ + +#define WDT_RSTCNT_RSTCNT_Pos (0) /*!< WDT_T::RSTCNT: RSTCNT Position */ +#define WDT_RSTCNT_RSTCNT_Msk (0xfffffffful << WDT_RSTCNT_RSTCNT_Pos) /*!< WDT_T::RSTCNT: RSTCNT Mask */ + +/**@}*/ /* WDT_CONST */ +/**@}*/ /* end of WDT register group */ +/**@}*/ /* end of REGISTER group */ + +#if defined ( __CC_ARM ) + #pragma no_anon_unions +#endif + +#endif /* __WDT_REG_H__ */ diff --git a/bsp/nuvoton/libraries/ma35/Device/Nuvoton/MA35D1/Include/whc_reg.h b/bsp/nuvoton/libraries/ma35/Device/Nuvoton/MA35D1/Include/whc_reg.h new file mode 100644 index 0000000000..8a3cdf5131 --- /dev/null +++ b/bsp/nuvoton/libraries/ma35/Device/Nuvoton/MA35D1/Include/whc_reg.h @@ -0,0 +1,1034 @@ +/**************************************************************************//** + * @file whc_reg.h + * @brief Wormhole controller register definition header file + * + * SPDX-License-Identifier: Apache-2.0 + * @copyright (C) 2020~2021 Nuvoton Technology Corp. All rights reserved. + *****************************************************************************/ +#ifndef __WHC_REG_H__ +#define __WHC_REG_H__ + +#if defined ( __CC_ARM ) + #pragma anon_unions +#endif + +/** + @addtogroup REGISTER Control Register + @{ +*/ +/** + @addtogroup WHC Wormhole Controller (WHC) + Memory Mapped Structure for WHC Controller +@{ */ + +typedef struct +{ + + + /** + * @var WHC_T::WKCTL + * Offset: 0x00 WHC Wakeup Event Control Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[0] |RST0WKEN |Counterpart First Core Reset Interrupt Wake-up Enable Bit + * | | |Counterpart reset event interrupt wake-up trigger event enable. + * | | |0 = Counterpart reset event interrupt wake-up trigger event Disabled. + * | | |1 = Counterpart reset event interrupt wake-up trigger event Enabled. + * |[1] |POFF0WKEN |Counterpart First Core Power Off State Interrupt Wake-up Enable Bit + * | | |Counterpart power off interrupt wake-up trigger event enable. + * | | |0 = Counterpart power off interrupt wake-up trigger event Disabled. + * | | |1 = Counterpart power off interrupt wake-up trigger event Enabled. + * |[2] |PD0WKEN |Counterpart First Core Power Down State Interrupt Wake-up Enable Bit + * | | |Counterpart power down interrupt wake-up trigger event enable. + * | | |0 = Counterpart power down interrupt wake-up trigger event Disabled. + * | | |1 = Counterpart power down interrupt wake-up trigger event Enabled. + * |[3] |RST1WKEN |A35 Second Core Reset Interrupt Wake-up Enable Bit + * | | |Counterpart reset event interrupt wake-up trigger event enable. + * | | |0 = Counterpart reset event interrupt wake-up trigger event Disabled. + * | | |1 = Counterpart reset event interrupt wake-up trigger event Enabled. + * | | |Note: This bit which indicates the second A35 core is only available for M4 side. + * |[4] |POFF1WKEN |A35 Second Core Power Off State Interrupt Wake-up Enable Bit + * | | |Counterpart power off interrupt wake-up trigger event enable. + * | | |0 = Counterpart power off interrupt wake-up trigger event Disabled. + * | | |1 = Counterpart power off interrupt wake-up trigger event Enabled. + * | | |Note: This bit which indicates the second A35 core is only available for M4 side. + * |[5] |PD1WKEN |A35 Second Core Power Down State Interrupt Wake-up Enable Bit + * | | |Counterpart power down interrupt wake-up trigger event enable. + * | | |0 = Counterpart power down interrupt wake-up trigger event Disabled. + * | | |1 = Counterpart power down interrupt wake-up trigger event Enabled. + * | | |Note: This bit which indicates the second A35 core is only available for M4 side. + * |[8] |GI0WKEN |General Interrupt 0 Wake-up Enable + * | | |If this bit is set to 1, while general interrupt flag is set to 1 and interrupt enable bit is enabled, the general interrupt signal will generate a wake-up trigger event to chip. + * | | |0 = Wake-up trigger event disabled if general interrupt 0 signal generated. + * | | |1 = Wake-up trigger event enabled if general interrupt 0 signal generated. + * |[9] |GI1WKEN |General Interrupt 1 Wake-up Enable + * | | |If this bit is set to 1, while general interrupt flag is set to 1 and interrupt enable bit is enabled, the general interrupt signal will generate a wake-up trigger event to chip. + * | | |0 = Wake-up trigger event disabled if general interrupt 1 signal generated. + * | | |1 = Wake-up trigger event enabled if general interrupt 1 signal generated. + * |[10] |GI2WKEN |General Interrupt 2 Wake-up Enable + * | | |If this bit is set to 1, while general interrupt flag is set to 1 and interrupt enable bit is enabled, the general interrupt signal will generate a wake-up trigger event to chip. + * | | |0 = Wake-up trigger event disabled if general interrupt 2 signal generated. + * | | |1 = Wake-up trigger event enabled if general interrupt 2 signal generated. + * |[11] |GI3WKEN |General Interrupt 3 Wake-up Enable + * | | |If this bit is set to 1, while general interrupt flag is set to 1 and interrupt enable bit is enabled, the general interrupt signal will generate a wake-up trigger event to chip. + * | | |0 = Wake-up trigger event disabled if general interrupt 3 signal generated. + * | | |1 = Wake-up trigger event enabled if general interrupt 3 signal generated. + * |[16] |TX0WKEN |TX Message Channel 0 Interrupt Wake-up Enable Bit + * | | |TX message channel 0 interrupt wake-up trigger event enable. + * | | |0 = Channel 0 interrupt wake-up trigger event Disabled. + * | | |1 = Channel 0 interrupt wake-up trigger event Enabled. + * |[17] |TX1WKEN |TX Message Channel 1 Interrupt Wake-up Enable Bit + * | | |TX message channel 1 interrupt wake-up trigger event enable. + * | | |0 = Channel 1 interrupt wake-up trigger event Disabled. + * | | |1 = Channel 1 interrupt wake-up trigger event Enabled. + * |[18] |TX2WKEN |TX Message Channel 2 Interrupt Wake-up Enable Bit + * | | |TX message channel 2 interrupt wake-up trigger event enable. + * | | |0 = Channel 2 interrupt wake-up trigger event Disabled. + * | | |1 = Channel 2 interrupt wake-up trigger event Enabled. + * |[19] |TX3WKEN |TX Message Channel 3 Interrupt Wake-up Enable Bit + * | | |TX message channel 3 interrupt wake-up trigger event enable. + * | | |0 = Channel 3 interrupt wake-up trigger event Disabled. + * | | |1 = Channel 3 interrupt wake-up trigger event Enabled. + * |[24] |RX0WKEN |RX Message Channel 0 Interrupt Wake-up Enable Bit + * | | |RX message channel 0 interrupt wake-up trigger event enable. + * | | |0 = Channel 0 interrupt wake-up trigger event Disabled. + * | | |1 = Channel 0 interrupt wake-up trigger event Enabled. + * |[25] |RX1WKEN |RX Message Channel 1 Interrupt Wake-up Enable Bit + * | | |RX message channel 1 interrupt wake-up trigger event enable. + * | | |0 = Channel 1 interrupt wake-up trigger event Disabled. + * | | |1 = Channel 1 interrupt wake-up trigger event Enabled. + * |[26] |RX2WKEN |RX Message Channel 2 Interrupt Wake-up Enable Bit + * | | |RX message Channel 2 interrupt wake-up trigger event enable. + * | | |0 = Channel 2 interrupt wake-up trigger event Disabled. + * | | |1 = Channel 2 interrupt wake-up trigger event Enabled. + * |[27] |RX3WKEN |RX Message Channel 3 Interrupt Wake-up Enable Bit + * | | |RX message channel 3 interrupt wake-up trigger event enable. + * | | |0 = Channel 3 interrupt wake-up trigger event Disabled. + * | | |1 = Channel 3 interrupt wake-up trigger event Enabled. + * @var WHC_T::INTEN + * Offset: 0x04 WHC Interrupt Enable Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[0] |RST0IEN |Counterpart First Core Reset Event Interrupt Enable Bit + * | | |Counterpart reset event interrupt enable. + * | | |0 = Counterpart status change interrupt Disabled. + * | | |1 = Counterpart status change interrupt Enabled. + * |[1] |POFF0IEN |Counterpart First Core Enter/Exit Power Off Mode Interrupt Enable Bit + * | | |Counterpart Enter/Exit Power Off Mode Interrupt Enable + * | | |0 = Counterpart power Off status change interrupt Disabled. + * | | |1 = Counterpart power Off status change interrupt Enabled. + * |[2] |PD0IEN |Counterpart First Core Enter/Exit Power-down mode Interrupt Enable Bit + * | | |Counterpart Enter/Exit Power-down mode Interrupt Enable + * | | |0 = Counterpart power down status change interrupt Disabled. + * | | |1 = Counterpart power down status change interrupt Enabled. + * |[3] |RST1IEN |A35 Second Core Reset Event Interrupt Enable Bit + * | | |Counterpart reset event interrupt enable. + * | | |0 = Counterpart status change interrupt Disabled. + * | | |1 = Counterpart status change interrupt Enabled. + * | | |Note: This bit which indicates the second A35 core is only available for M4 side. + * |[4] |POFF1IEN |A35 Second Core Enter/Exit Power Off Mode Interrupt Enable Bit + * | | |Counterpart Enter/Exit Power Off Mode Interrupt Enable + * | | |0 = Counterpart power Off status change interrupt Disabled. + * | | |1 = Counterpart power Off status change interrupt Enabled. + * | | |Note: This bit which indicates the second A35 core is only available for M4 side. + * |[5] |PD1IEN |A35 Second Core Enter/Exit Power-down mode Interrupt Enable Bit + * | | |Counterpart Enter/Exit Power-down mode Interrupt Enable + * | | |0 = Counterpart power down status change interrupt Disabled. + * | | |1 = Counterpart power down status change interrupt Enabled. + * | | |Note: This bit which indicates the second A35 core is only available for M4 side. + * |[8] |GI0IEN |General Interrupt 0 Enable Bit + * | | |General interrupt 0 interrupt enable. + * | | |0 = General interrupt 0 interrupt Disabled. + * | | |1 = General interrupt 0 interrupt Enabled. + * |[9] |GI1IEN |General Interrupt 1 Enable Bit + * | | |General interrupt 1 interrupt enable. + * | | |0 = General interrupt 1 interrupt Disabled. + * | | |1 = General interrupt 1 interrupt Enabled. + * |[10] |GI2IEN |General Interrupt 2 Enable Bit + * | | |General interrupt 2 interrupt enable. + * | | |0 = General interrupt 2 interrupt Disabled. + * | | |1 = General interrupt 2 interrupt Enabled. + * |[11] |GI3IEN |General Interrupt 3 Enable Bit + * | | |General interrupt 3 interrupt enable. + * | | |0 = General interrupt 3 interrupt Disabled. + * | | |1 = General interrupt 3 interrupt Enabled. + * |[16] |TX0IEN |TX Message Channel 0 Interrupt Enable Bit + * | | |TX message channel 0 ACK interrupt enable + * | | |0 = Channel 0 ACK interrupt Disabled. + * | | |1 = Channel 0 ACK interrupt Enabled. + * |[17] |TX1IEN |TX Message Channel 1 Interrupt Enable Bit + * | | |TX message channel 1 ACK interrupt enable. + * | | |0 = Channel 1 ACK interrupt Disabled. + * | | |1 = Channel 1 ACK interrupt Enabled. + * |[18] |TX2IEN |TX Message Channel 2 Interrupt Enable Bit + * | | |TX message channel 2 ACK interrupt enable. + * | | |0 = Channel 2 ACK interrupt Disabled. + * | | |1 = Channel 2 ACK interrupt Enabled. + * |[19] |TX3IEN |TX Message Channel 3 Interrupt Enable Bit + * | | |TX message channel 3 ACK interrupt enable + * | | |0 = Channel 3 ACK interrupt Disabled. + * | | |1 = Channel 3 ACK interrupt Enabled. + * |[24] |RX0IEN |RX Message Channel 0 Interrupt Enable Bit + * | | |RX message channel 0 arrive or recall interrupt enable + * | | |0 = Channel 0 arrive or recall interrupt Disabled. + * | | |1 = Channel 0 arrive or recall interrupt Enabled. + * |[25] |RX1IEN |RX Message Channel 1 Interrupt Enable Bit + * | | |RX message channel 1 arrive or recall interrupt enable. + * | | |0 = Channel 1 arrive or recall interrupt Disabled. + * | | |1 = Channel 1 arrive or recall interrupt Enabled. + * |[26] |RX2IEN |RX Message Channel 2 Interrupt Enable Bit + * | | |RX message channel 2 arrive or recall interrupt enable. + * | | |0 = Channel 2 arrive or recall interrupt Disabled. + * | | |1 = Channel 2 arrive or recall interrupt Enabled. + * |[27] |RX3IEN |RX Message Channel 3 Interrupt Enable Bit + * | | |RX message channel 3 arrive or recall interrupt enable + * | | |0 = Channel 3 arrive or recall interrupt Disabled. + * | | |1 = Channel 3 arrive or recall interrupt Enabled. + * @var WHC_T::INTSTS + * Offset: 0x08 WHC Interrupt Status Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[0] |RST0IF |Counterpart First Core Reset Event Interrupt Flag + * | | |Counterpart reset event interrupt flag. + * | | |0 = No counterpart reset status change interrupt generated. + * | | |1 = Counterpart reset status change interrupt generated. + * | | |Note: Write 1 to clear this bit to 0. + * |[1] |POFF0IF |Counterpart First Core Enter/Exit Power Off Mode Interrupt Flag + * | | |Counterpart Enter/Exit Power Off Mode Interrupt Flag + * | | |0 = No counterpart power off mode status change interrupt generated. + * | | |1 = Counterpart power off mode status change interrupt generated. + * | | |Note: Write 1 to clear this bit to 0.. + * |[2] |PD0IF |Counterpart First Core Enter/Exit Power-down mode Interrupt Flag + * | | |Counterpart Enter/Exit Power-down mode Interrupt Flag + * | | |0 = No counterpart Power-down mode status change interrupt generated. + * | | |1 = Counterpart Power-down mode status change interrupt generated. + * | | |Note: Write 1 to clear this bit to 0. + * |[3] |RST1IF |A35 Second Core Reset Event Interrupt Flag + * | | |Counterpart reset event interrupt flag. + * | | |0 = No counterpart reset status change interrupt generated. + * | | |1 = Counterpart reset status change interrupt generated. + * | | |Note: Write 1 to clear this bit to 0. + * | | |Note: This bit which indicates the second A35 core is only available for M4 side. + * |[4] |POFF1IF |A35 Second Core Enter/Exit Power Off Mode Interrupt Flag + * | | |Counterpart Enter/Exit Power Off Mode Interrupt Flag + * | | |0 = No counterpart power off mode status change interrupt generated. + * | | |1 = Counterpart power off mode status change interrupt generated. + * | | |Note: Write 1 to clear this bit to 0. + * | | |Note: This bit which indicates the second A35 core is only available for M4 side. + * |[5] |PD1IF |A35 Second Core Enter/Exit Power-down mode Interrupt Flag + * | | |Counterpart Enter/Exit Power-down mode Interrupt Flag + * | | |0 = No counterpart Power-down mode status change interrupt generated. + * | | |1 = Counterpart Power-down mode status change interrupt generated. + * | | |Note: Write 1 to clear this bit to 0. + * | | |Note: This bit which indicates the second A35 core is only available for M4 side. + * |[8] |GI0IF |General Event 0 Flag + * | | |General event 0 interrupt flag. + * | | |0 = No general event 0 interrupt generated. + * | | |1 = General event 0 interrupt generated. + * | | |Note: Write 1 to clear this bit to 0. + * |[9] |GI1IF |General Event 1 Flag + * | | |General event 1 interrupt flag. + * | | |0 = No general event 1 interrupt generated. + * | | |1 = General event 1 interrupt generated. + * | | |Note: Write 1 to clear this bit to 0. + * |[10] |GI2IF |General Event 2 Flag + * | | |General event 2 interrupt flag. + * | | |0 = No general event 2 interrupt generated. + * | | |1 = General event 2 interrupt generated. + * | | |Note: Write 1 to clear this bit to 0. + * |[11] |GI3IF |General Event 3 Flag + * | | |General event 3 interrupt flag. + * | | |0 = No general event 3 interrupt generated. + * | | |1 = General event 3 interrupt generated. + * | | |Note: Write 1 to clear this bit to 0. + * |[16] |TX0IF |TX Message Channel 0 Interrupt Flag + * | | |Tx message channel 0 ACK interrupt flag. + * | | |0 = No channel 0 ACK interrupt generated. + * | | |1 = Channel 0 ACK interrupt generated. + * | | |Note: Write 1 to clear this bit to 0. + * |[17] |TX1IF |TX Message Channel 1 Interrupt Flag + * | | |Tx message channel 1 ACK interrupt flag. + * | | |0 = No channel 1 ACK interrupt generated. + * | | |1 = Channel 1 ACK interrupt generated. + * | | |Note: Write 1 to clear this bit to 0. + * |[18] |TX2IF |TX Message Channel 2 Interrupt Flag + * | | |Tx message channel 2 ACK interrupt flag. + * | | |0 = No channel 2 ACK interrupt generated. + * | | |1 = Channel 2 ACK interrupt generated. + * | | |Note: Write 1 to clear this bit to 0. + * |[19] |TX3IF |TX Message Channel 3 Interrupt Flag + * | | |Tx message channel 3 ACK interrupt flag. + * | | |0 = No channel 3 ACK interrupt generated. + * | | |1 = Channel 3 ACK interrupt generated. + * | | |Note: Write 1 to clear this bit to 0. + * |[24] |RX0IF |RX Message Channel 0 Interrupt Flag + * | | |Short message channel 0 arrive or recall interrupt flag. + * | | |0 = No channel 0 arrive or recall interrupt generated. + * | | |1 = Channel 0 arrive or recall interrupt generated. + * | | |Note: Write 1 to clear this bit to 0. + * |[25] |RX1IF |RX Message Channel 1 Interrupt Flag + * | | |Short message channel 1 arrive or recall interrupt flag. + * | | |0 = No channel 1 arrive or recall interrupt generated. + * | | |1 = Channel 1 arrive or recall interrupt generated. + * | | |Note: Write 1 to clear this bit to 0. + * |[26] |RX2IF |RX Message Channel 2 Interrupt Flag + * | | |Short message channel 2 arrive or recall interrupt flag. + * | | |0 = No channel 2 arrive or recall interrupt generated. + * | | |1 = Channel 2 arrive or recall interrupt generated. + * | | |Note: Write 1 to clear this bit to 0. + * |[27] |RX3IF |RX Message Channel 3 Interrupt Flag + * | | |RX message channel 3 arrive or recall interrupt flag. + * | | |0 = No channel 3 arrive or recall interrupt generated. + * | | |1 = Channel 3 arrive or recall interrupt generated. + * | | |Note: Write 1 to clear this bit to 0. + * @var WHC_T::CPSTS + * Offset: 0x40 WHC Counterpart Status Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[2] |WDTRF |WDT Reset Flag + * | | |The WDT reset flag is set by the Reset Signal from the Watchdog Timer or Window Watchdog Timer to indicate the previous reset source. + * | | |0 = No reset from watchdog timer or window watchdog timer. + * | | |1 = The watchdog timer or window watchdog timer had issued the reset signal to reset the system. + * | | |Note 1: Read only, write 1 to clear this bit to 0. + * | | |Note 2: Watchdog Timer register RSTF(WDT_CTL[2]) bit is set if the system has been reset by WDT time-out reset + * | | |Window Watchdog Timer register WWDTRF(WWDT_STATUS[1]) bit is set if the system has been reset by WWDT time-out reset. + * |[5] |SYSRF |System Reset Flag + * | | |The system reset flag is set by the Reset Signal from the Cortex-M4 Core to indicate the previous reset source. + * | | |0 = No reset from Cortex-M4. + * | | |1 = The Cortex-M4 had issued the reset signal to reset the system by writing 1 to the bit SYSRESETREQ(AIRCR[2], Application Interrupt and Reset Control Register, address = 0xE000ED0C) in system control registers of Cortex-M4 core. + * | | |Note: Read only, write 1 to clear this bit to 0. + * |[7] |CPURF |CPU Reset Flag + * | | |The CPU reset flag is set by hardware if software writes CPURST (SYS_IPRST0[1]) 1 to reset Cortex-M4 Core and Flash Memory Controller (FMC). + * | | |0 = No reset from CPU. + * | | |1 = The Cortex-M4 Core and FMC are reset by software setting CPURST to 1. + * | | |Note: Read only, write 1 to clear this bit to 0. + * |[8] |CPULKRF |CPU Lockup Reset Flag + * | | |0 = No reset from CPU lockup happened. + * | | |1 = The Cortex-M4 lockup happened and chip is reset. + * | | |Note 1: Read only, write 1 to clear this bit to 0. + * | | |Note 2: When CPU lockup happened under ICE is connected, This flag will set to 1 but chip will not reset. + * |[27:24] |OPMODE0 |Operating Mode of Other Side Core 0, Representing A35/M4 Core 0 (Read Only) + * | | |This bit field indicates the operating mode of the core 0 of the other side. + * | | |0000 = Run mode. + * | | |0001 = Power off mode. + * | | |0010 = Power-down mode. + * | | |Others = Reserved. + * |[31:28] |OPMODE1 |Operating Mode of Other Side Core 1, Representing A35 Core 1 (Read Only) + * | | |This bit field indicates the operating mode of the core 1 of the other side. + * | | |0000 = Run mode. + * | | |0001 = Power off mode. + * | | |0010 = Power-down mode. + * | | |Others = Reserved. + * | | |Note 1: This field can only be accessed by M4 side. + * @var WHC_T::GINTTRG + * Offset: 0x80 WHC General Interrupt Trigger Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[0] |TRGGI0 |Trigger General Interrupt 0 + * | | |Write this bit 1 to trigger general interrupt 0. + * |[1] |TRGGI1 |Trigger General Interrupt 1 + * | | |Write this bit 1 to trigger general interrupt 1. + * |[2] |TRGGI2 |Trigger General Interrupt 2 + * | | |Write this bit 1 to trigger general interrupt 2. + * |[3] |TRGGI3 |Trigger General Interrupt 3 + * | | |Write this bit 1 to trigger general interrupt 3. + * @var WHC_T::TXCTL + * Offset: 0xC0 WHC TX Message Control Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[0] |CH0SND |Send Channel 0 Message + * | | |Write 1 to this bit to send TX channel 0 message + * | | |Before write 1 to this bit, sender should check the corresponding CHxRDY bit in TXSTS is 1 or not + * | | |Otherwise, the receiver may get unpredictable data. + * | | |Note: Write 0 to this bit has no effect + * | | |Write 1 to SND and RC bits of the same channel simultaneously will yield unpredictable result. + * |[1] |CH1SND |Send Channel 1 Message + * | | |Write 1 to this bit to send TX channel 1 message + * | | |Before write 1 to this bit, sender should check the corresponding CHxRDY bit in TXSTS is 1 or not + * | | |Otherwise, the receiver may get unpredictable data. + * | | |Note: Write 0 to this bit has no effect + * | | |Write 1 to SND and RC bits of the same channel simultaneously will yield unpredictable result. + * |[2] |CH2SND |Send Channel 2 Message + * | | |Write 1 to this bit to send TX channel 2 message + * | | |Before write 1 to this bit, sender should check the corresponding CHxRDY bit in TXSTS is 1 or not + * | | |Otherwise, the receiver may get unpredictable data. + * | | |Note: Write 0 to this bit has no effect + * | | |Write 1 to SND and RC bits of the same channel simultaneously will yield unpredictable result. + * |[3] |CH3SND |Send Channel 3 Message + * | | |Write 1 to this bit to send TX channel 3 message + * | | |Before write 1 to this bit, sender should check the corresponding CHxRDY bit in TXSTS is 1 or not + * | | |Otherwise, the receiver may get unpredictable data. + * | | |Note: Write 0 to this bit has no effect + * | | |Write 1 to SND and RC bits of the same channel simultaneously will yield unpredictable result. + * |[16] |CH0RC |Recall Channel 1 Message + * | | |Write 1 to this bit to recall TX channel 1 message + * | | |Before write 1 to this bit, sender should check the corresponding CHxRDY bit in TXSTS is 0 or not. + * | | |Note: Write 0 to this bit has no effect + * | | |Write 1 to SND and RC bits of the same channel simultaneously will yield unpredictable result. + * |[17] |CH1RC |Recall Channel 1 Message + * | | |Write 1 to this bit to recall TX channel 1 message + * | | |Before write 1 to this bit, sender should check the corresponding CHxRDY bit in TXSTS is 0 or not. + * | | |Note: Write 0 to this bit has no effect + * | | |Write 1 to SND and RC bits of the same channel simultaneously will yield unpredictable result. + * |[18] |CH2RC |Recall Channel 2 Message + * | | |Write 1 to this bit to recall TX channel 2 message + * | | |Before write 1 to this bit, sender should check the corresponding CHxRDY bit in TXSTS is 0 or not. + * | | |Note: Write 0 to this bit has no effect + * | | |Write 1 to SND and RC bits of the same channel simultaneously will yield unpredictable result. + * |[19] |CH3RC |Recall Channel 3 Message + * | | |Write 1 to this bit to recall TX channel 3 message + * | | |Before write 1 to this bit, sender should check the corresponding CHxRDY bit in TXSTS is 0 or not. + * | | |Note: Write 0 to this bit has no effect + * | | |Write 1 to SND and RC bits of the same channel simultaneously will yield unpredictable result. + * @var WHC_T::TXSTS + * Offset: 0xC4 WHC TX Message Status Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[0] |CH0RDY |Channel 0 Message Ready + * | | |0 = No recall event. + * | | |1 = Message channel is available to send new data. + * | | |This bit automatically cleared to 0 after write 1 to CH0SND + * | | |Automatically set to 1 after recall complete or receiver notify message read. + * |[1] |CH1RDY |Channel 1 Message Ready + * | | |0 = No recall event. + * | | |1 = Message channel is available to send new data. + * | | |This bit automatically cleared to 0 after write 1 to CH1SND + * | | |Automatically set to 1 after recall complete or receiver notify message read. + * |[2] |CH2RDY |Channel 2 Message Ready + * | | |0 = No recall event. + * | | |1 = Message channel is available to send new data. + * | | |This bit automatically cleared to 0 after write 1 to CH2SND + * | | |Automatically set to 1 after recall complete or receiver notify message read. + * |[3] |CH3RDY |Channel 3 Message Ready + * | | |0 = No recall event. + * | | |1 = Message channel is available to send new data. + * | | |This bit automatically cleared to 0 after write 1 to CH3SND + * | | |Automatically set to 1 after recall complete or receiver notify message read. + * @var WHC_T::RXCTL + * Offset: 0xC8 WHC RX Message Control Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[0] |CH0ACK |RX Message Channel 0 ACK + * | | |Write 1 to notify sender that channel 0 message has been read. Write 0 to this bit has no effect. + * | | |Write 1 will clear CH0RDY. + * |[1] |CH1ACK |RX Message Channel 1 ACK + * | | |Write 1 to notify sender that channel 1 message has been read. Write 0 to this bit has no effect. + * | | |Write 1 will clear CH1RDY. + * |[2] |CH2ACK |RX Message Channel 2 ACK + * | | |Write 1 to notify sender that channel 2 message has been read. Write 0 to this bit has no effect. + * | | |Write 1 will clear CH2RDY. + * |[3] |CH3ACK |RX Message Channel 3 ACK + * | | |Write 1 to notify sender that channel 3 message has been read. Write 0 to this bit has no effect. + * | | |Write 1 will clear CH3RDY. + * @var WHC_T::RXSTS + * Offset: 0xCC WHC RX Message Status Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[0] |CH0RDY |RX Channel 0 Message Ready + * | | |0 = RX channel 0 message data is not ready. + * | | |1 = RX channel 0 message data is ready. + * | | |Note: This bit is automatically set to 1 after sender writes 1 to CH0SND + * | | |It is automatically cleared to 0 after recall complete or write 1 to CH0ACK. + * |[1] |CH1RDY |RX Channel 1 Message Ready + * | | |0 = RX channel 1 message data is not ready. + * | | |1 = RX channel 1 message data is ready. + * | | |Note: This bit is automatically set to 1 after sender writes 1 to CH1SND + * | | |It is automatically cleared to 0 after recall complete or write 1 to CH1ACK. + * |[2] |CH2RDY |RX Channel 2 Message Ready + * | | |0 = RX channel 2 message data is not ready. + * | | |1 = RX channel 2 message data is ready. + * | | |Note: This bit is automatically set to 1 after sender writes 1 to CH2SND + * | | |It is automatically cleared to 0 after recall complete or write 1 to CH2ACK. + * |[3] |CH3RDY |RX Channel 3 Message Ready + * | | |0 = RX channel 3 message data is not ready. + * | | |1 = RX channel 3 message data is ready. + * | | |Note: This bit is automatically set to 1 after sender writes 1 to CH3SND + * | | |It is automatically cleared to 0 after recall complete or write 1 to CH3ACK. + * @var WHC_T::TM0DAT0 + * Offset: 0x100 WHC TX Message Channel 0 Data 0 Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[31:0] |DATA |TX Message Data + * | | |This field contains the TX message data field + * | | |Sender should only write these registers while ready bit in TXSTS register is 1 + * | | |Otherwise, the receiver can read unpredictable data. + * @var WHC_T::TM0DAT1 + * Offset: 0x104 WHC TX Message Channel 0 Data 1 Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[31:0] |DATA |TX Message Data + * | | |This field contains the TX message data field + * | | |Sender should only write these registers while ready bit in TXSTS register is 1 + * | | |Otherwise, the receiver can read unpredictable data. + * @var WHC_T::TM0DAT2 + * Offset: 0x108 WHC TX Message Channel 0 Data 2 Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[31:0] |DATA |TX Message Data + * | | |This field contains the TX message data field + * | | |Sender should only write these registers while ready bit in TXSTS register is 1 + * | | |Otherwise, the receiver can read unpredictable data. + * @var WHC_T::TM0DAT3 + * Offset: 0x10C WHC TX Message Channel 0 Data 3 Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[31:0] |DATA |TX Message Data + * | | |This field contains the TX message data field + * | | |Sender should only write these registers while ready bit in TXSTS register is 1 + * | | |Otherwise, the receiver can read unpredictable data. + * @var WHC_T::TM1DAT0 + * Offset: 0x110 WHC TX Message Channel 1 Data 0 Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[31:0] |DATA |TX Message Data + * | | |This field contains the TX message data field + * | | |Sender should only write these registers while ready bit in TXSTS register is 1 + * | | |Otherwise, the receiver can read unpredictable data. + * @var WHC_T::TM1DAT1 + * Offset: 0x114 WHC TX Message Channel 1 Data 1 Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[31:0] |DATA |TX Message Data + * | | |This field contains the TX message data field + * | | |Sender should only write these registers while ready bit in TXSTS register is 1 + * | | |Otherwise, the receiver can read unpredictable data. + * @var WHC_T::TM1DAT2 + * Offset: 0x118 WHC TX Message Channel 1 Data 2 Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[31:0] |DATA |TX Message Data + * | | |This field contains the TX message data field + * | | |Sender should only write these registers while ready bit in TXSTS register is 1 + * | | |Otherwise, the receiver can read unpredictable data. + * @var WHC_T::TM1DAT3 + * Offset: 0x11C WHC TX Message Channel 1 Data 3 Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[31:0] |DATA |TX Message Data + * | | |This field contains the TX message data field + * | | |Sender should only write these registers while ready bit in TXSTS register is 1 + * | | |Otherwise, the receiver can read unpredictable data. + * @var WHC_T::TM2DAT0 + * Offset: 0x120 WHC TX Message Channel 2 Data 0 Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[31:0] |DATA |TX Message Data + * | | |This field contains the TX message data field + * | | |Sender should only write these registers while ready bit in TXSTS register is 1 + * | | |Otherwise, the receiver can read unpredictable data. + * @var WHC_T::TM2DAT1 + * Offset: 0x124 WHC TX Message Channel 2 Data 1 Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[31:0] |DATA |TX Message Data + * | | |This field contains the TX message data field + * | | |Sender should only write these registers while ready bit in TXSTS register is 1 + * | | |Otherwise, the receiver can read unpredictable data. + * @var WHC_T::TM2DAT2 + * Offset: 0x128 WHC TX Message Channel 2 Data 2 Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[31:0] |DATA |TX Message Data + * | | |This field contains the TX message data field + * | | |Sender should only write these registers while ready bit in TXSTS register is 1 + * | | |Otherwise, the receiver can read unpredictable data. + * @var WHC_T::TM2DAT3 + * Offset: 0x12C WHC TX Message Channel 2 Data 3 Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[31:0] |DATA |TX Message Data + * | | |This field contains the TX message data field + * | | |Sender should only write these registers while ready bit in TXSTS register is 1 + * | | |Otherwise, the receiver can read unpredictable data. + * @var WHC_T::TM3DAT0 + * Offset: 0x130 WHC TX Message Channel 3 Data 0 Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[31:0] |DATA |TX Message Data + * | | |This field contains the TX message data field + * | | |Sender should only write these registers while ready bit in TXSTS register is 1 + * | | |Otherwise, the receiver can read unpredictable data. + * @var WHC_T::TM3DAT1 + * Offset: 0x134 WHC TX Message Channel 3 Data 1 Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[31:0] |DATA |TX Message Data + * | | |This field contains the TX message data field + * | | |Sender should only write these registers while ready bit in TXSTS register is 1 + * | | |Otherwise, the receiver can read unpredictable data. + * @var WHC_T::TM3DAT2 + * Offset: 0x138 WHC TX Message Channel 3 Data 2 Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[31:0] |DATA |TX Message Data + * | | |This field contains the TX message data field + * | | |Sender should only write these registers while ready bit in TXSTS register is 1 + * | | |Otherwise, the receiver can read unpredictable data. + * @var WHC_T::TM3DAT3 + * Offset: 0x13C WHC TX Message Channel 3 Data 3 Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[31:0] |DATA |TX Message Data + * | | |This field contains the TX message data field + * | | |Sender should only write these registers while ready bit in TXSTS register is 1 + * | | |Otherwise, the receiver can read unpredictable data. + * @var WHC_T::RM0DAT0 + * Offset: 0x200 WHC RX Message Channel 0 Data 0 Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[31:0] |DATA |RX Message Data + * | | |This field contains the RX message data field + * | | |Receiver should only read these registers while ready bit in RXSTS register is 1 + * | | |Otherwise, the receiver can read unpredictable data. + * @var WHC_T::RM0DAT1 + * Offset: 0x204 WHC RX Message Channel 0 Data 1 Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[31:0] |DATA |RX Message Data + * | | |This field contains the RX message data field + * | | |Receiver should only read these registers while ready bit in RXSTS register is 1 + * | | |Otherwise, the receiver can read unpredictable data. + * @var WHC_T::RM0DAT2 + * Offset: 0x208 WHC RX Message Channel 0 Data 2 Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[31:0] |DATA |RX Message Data + * | | |This field contains the RX message data field + * | | |Receiver should only read these registers while ready bit in RXSTS register is 1 + * | | |Otherwise, the receiver can read unpredictable data. + * @var WHC_T::RM0DAT3 + * Offset: 0x20C WHC RX Message Channel 0 Data 3 Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[31:0] |DATA |RX Message Data + * | | |This field contains the RX message data field + * | | |Receiver should only read these registers while ready bit in RXSTS register is 1 + * | | |Otherwise, the receiver can read unpredictable data. + * @var WHC_T::RM1DAT0 + * Offset: 0x210 WHC RX Message Channel 1 Data 0 Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[31:0] |DATA |RX Message Data + * | | |This field contains the RX message data field + * | | |Receiver should only read these registers while ready bit in RXSTS register is 1 + * | | |Otherwise, the receiver can read unpredictable data. + * @var WHC_T::RM1DAT1 + * Offset: 0x214 WHC RX Message Channel 1 Data 1 Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[31:0] |DATA |RX Message Data + * | | |This field contains the RX message data field + * | | |Receiver should only read these registers while ready bit in RXSTS register is 1 + * | | |Otherwise, the receiver can read unpredictable data. + * @var WHC_T::RM1DAT2 + * Offset: 0x218 WHC RX Message Channel 1 Data 2 Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[31:0] |DATA |RX Message Data + * | | |This field contains the RX message data field + * | | |Receiver should only read these registers while ready bit in RXSTS register is 1 + * | | |Otherwise, the receiver can read unpredictable data. + * @var WHC_T::RM1DAT3 + * Offset: 0x21C WHC RX Message Channel 1 Data 3 Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[31:0] |DATA |RX Message Data + * | | |This field contains the RX message data field + * | | |Receiver should only read these registers while ready bit in RXSTS register is 1 + * | | |Otherwise, the receiver can read unpredictable data. + * @var WHC_T::RM2DAT0 + * Offset: 0x220 WHC RX Message Channel 2 Data 0 Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[31:0] |DATA |RX Message Data + * | | |This field contains the RX message data field + * | | |Receiver should only read these registers while ready bit in RXSTS register is 1 + * | | |Otherwise, the receiver can read unpredictable data. + * @var WHC_T::RM2DAT1 + * Offset: 0x224 WHC RX Message Channel 2 Data 1 Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[31:0] |DATA |RX Message Data + * | | |This field contains the RX message data field + * | | |Receiver should only read these registers while ready bit in RXSTS register is 1 + * | | |Otherwise, the receiver can read unpredictable data. + * @var WHC_T::RM2DAT2 + * Offset: 0x228 WHC RX Message Channel 2 Data 2 Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[31:0] |DATA |RX Message Data + * | | |This field contains the RX message data field + * | | |Receiver should only read these registers while ready bit in RXSTS register is 1 + * | | |Otherwise, the receiver can read unpredictable data. + * @var WHC_T::RM2DAT3 + * Offset: 0x22C WHC RX Message Channel 2 Data 3 Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[31:0] |DATA |RX Message Data + * | | |This field contains the RX message data field + * | | |Receiver should only read these registers while ready bit in RXSTS register is 1 + * | | |Otherwise, the receiver can read unpredictable data. + * @var WHC_T::RM3DAT0 + * Offset: 0x230 WHC RX Message Channel 3 Data 0 Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[31:0] |DATA |RX Message Data + * | | |This field contains the RX message data field + * | | |Receiver should only read these registers while ready bit in RXSTS register is 1 + * | | |Otherwise, the receiver can read unpredictable data. + * @var WHC_T::RM3DAT1 + * Offset: 0x234 WHC RX Message Channel 3 Data 1 Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[31:0] |DATA |RX Message Data + * | | |This field contains the RX message data field + * | | |Receiver should only read these registers while ready bit in RXSTS register is 1 + * | | |Otherwise, the receiver can read unpredictable data. + * @var WHC_T::RM3DAT2 + * Offset: 0x238 WHC RX Message Channel 3 Data 2 Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[31:0] |DATA |RX Message Data + * | | |This field contains the RX message data field + * | | |Receiver should only read these registers while ready bit in RXSTS register is 1 + * | | |Otherwise, the receiver can read unpredictable data. + * @var WHC_T::RM3DAT3 + * Offset: 0x23C WHC RX Message Channel 3 Data 3 Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[31:0] |DATA |RX Message Data + * | | |This field contains the RX message data field + * | | |Receiver should only read these registers while ready bit in RXSTS register is 1 + * | | |Otherwise, the receiver can read unpredictable data. + */ + __IO uint32_t WKCTL; /*!< [0x0000] WHC Wakeup Event Control Register */ + __IO uint32_t INTEN; /*!< [0x0004] WHC Interrupt Enable Register */ + __IO uint32_t INTSTS; /*!< [0x0008] WHC Interrupt Status Register */ + __I uint32_t RESERVE0[13]; + __IO uint32_t CPSTS; /*!< [0x0040] WHC Counterpart Status Register */ + __I uint32_t RESERVE1[15]; + __O uint32_t GINTTRG; /*!< [0x0080] WHC General Interrupt Trigger Register */ + __I uint32_t RESERVE2[15]; + __O uint32_t TXCTL; /*!< [0x00c0] WHC TX Message Control Register */ + __I uint32_t TXSTS; /*!< [0x00c4] WHC TX Message Status Register */ + __O uint32_t RXCTL; /*!< [0x00c8] WHC RX Message Control Register */ + __I uint32_t RXSTS; /*!< [0x00cc] WHC RX Message Status Register */ + __I uint32_t RESERVE3[12]; + __O uint32_t TMDAT[4][4]; /*!< [0x0100~0x013C] WHC TX Message Data Register */ + __I uint32_t RESERVE4[48]; + __I uint32_t RMDAT[4][4]; /*!< [0x0200~0x023C] WHC RX Message Data Register */ +} WHC_T; + +/** + @addtogroup WHC_CONST WHC Bit Field Definition + Constant Definitions for WHC Controller +@{ */ + +#define WHC_WKCTL_RST0WKEN_Pos (0) /*!< WHC_T::WKCTL: RST0WKEN Position */ +#define WHC_WKCTL_RST0WKEN_Msk (0x1ul << WHC_WKCTL_RST0WKEN_Pos) /*!< WHC_T::WKCTL: RST0WKEN Mask */ + +#define WHC_WKCTL_POFF0WKEN_Pos (1) /*!< WHC_T::WKCTL: POFF0WKEN Position */ +#define WHC_WKCTL_POFF0WKEN_Msk (0x1ul << WHC_WKCTL_POFF0WKEN_Pos) /*!< WHC_T::WKCTL: POFF0WKEN Mask */ + +#define WHC_WKCTL_PD0WKEN_Pos (2) /*!< WHC_T::WKCTL: PD0WKEN Position */ +#define WHC_WKCTL_PD0WKEN_Msk (0x1ul << WHC_WKCTL_PD0WKEN_Pos) /*!< WHC_T::WKCTL: PD0WKEN Mask */ + +#define WHC_WKCTL_RST1WKEN_Pos (3) /*!< WHC_T::WKCTL: RST1WKEN Position */ +#define WHC_WKCTL_RST1WKEN_Msk (0x1ul << WHC_WKCTL_RST1WKEN_Pos) /*!< WHC_T::WKCTL: RST1WKEN Mask */ + +#define WHC_WKCTL_POFF1WKEN_Pos (4) /*!< WHC_T::WKCTL: POFF1WKEN Position */ +#define WHC_WKCTL_POFF1WKEN_Msk (0x1ul << WHC_WKCTL_POFF1WKEN_Pos) /*!< WHC_T::WKCTL: POFF1WKEN Mask */ + +#define WHC_WKCTL_PD1WKEN_Pos (5) /*!< WHC_T::WKCTL: PD1WKEN Position */ +#define WHC_WKCTL_PD1WKEN_Msk (0x1ul << WHC_WKCTL_PD1WKEN_Pos) /*!< WHC_T::WKCTL: PD1WKEN Mask */ + +#define WHC_WKCTL_GI0WKEN_Pos (8) /*!< WHC_T::WKCTL: GI0WKEN Position */ +#define WHC_WKCTL_GI0WKEN_Msk (0x1ul << WHC_WKCTL_GI0WKEN_Pos) /*!< WHC_T::WKCTL: GI0WKEN Mask */ + +#define WHC_WKCTL_GI1WKEN_Pos (9) /*!< WHC_T::WKCTL: GI1WKEN Position */ +#define WHC_WKCTL_GI1WKEN_Msk (0x1ul << WHC_WKCTL_GI1WKEN_Pos) /*!< WHC_T::WKCTL: GI1WKEN Mask */ + +#define WHC_WKCTL_GI2WKEN_Pos (10) /*!< WHC_T::WKCTL: GI2WKEN Position */ +#define WHC_WKCTL_GI2WKEN_Msk (0x1ul << WHC_WKCTL_GI2WKEN_Pos) /*!< WHC_T::WKCTL: GI2WKEN Mask */ + +#define WHC_WKCTL_GI3WKEN_Pos (11) /*!< WHC_T::WKCTL: GI3WKEN Position */ +#define WHC_WKCTL_GI3WKEN_Msk (0x1ul << WHC_WKCTL_GI3WKEN_Pos) /*!< WHC_T::WKCTL: GI3WKEN Mask */ + +#define WHC_WKCTL_TX0WKEN_Pos (16) /*!< WHC_T::WKCTL: TX0WKEN Position */ +#define WHC_WKCTL_TX0WKEN_Msk (0x1ul << WHC_WKCTL_TX0WKEN_Pos) /*!< WHC_T::WKCTL: TX0WKEN Mask */ + +#define WHC_WKCTL_TX1WKEN_Pos (17) /*!< WHC_T::WKCTL: TX1WKEN Position */ +#define WHC_WKCTL_TX1WKEN_Msk (0x1ul << WHC_WKCTL_TX1WKEN_Pos) /*!< WHC_T::WKCTL: TX1WKEN Mask */ + +#define WHC_WKCTL_TX2WKEN_Pos (18) /*!< WHC_T::WKCTL: TX2WKEN Position */ +#define WHC_WKCTL_TX2WKEN_Msk (0x1ul << WHC_WKCTL_TX2WKEN_Pos) /*!< WHC_T::WKCTL: TX2WKEN Mask */ + +#define WHC_WKCTL_TX3WKEN_Pos (19) /*!< WHC_T::WKCTL: TX3WKEN Position */ +#define WHC_WKCTL_TX3WKEN_Msk (0x1ul << WHC_WKCTL_TX3WKEN_Pos) /*!< WHC_T::WKCTL: TX3WKEN Mask */ + +#define WHC_WKCTL_RX0WKEN_Pos (24) /*!< WHC_T::WKCTL: RX0WKEN Position */ +#define WHC_WKCTL_RX0WKEN_Msk (0x1ul << WHC_WKCTL_RX0WKEN_Pos) /*!< WHC_T::WKCTL: RX0WKEN Mask */ + +#define WHC_WKCTL_RX1WKEN_Pos (25) /*!< WHC_T::WKCTL: RX1WKEN Position */ +#define WHC_WKCTL_RX1WKEN_Msk (0x1ul << WHC_WKCTL_RX1WKEN_Pos) /*!< WHC_T::WKCTL: RX1WKEN Mask */ + +#define WHC_WKCTL_RX2WKEN_Pos (26) /*!< WHC_T::WKCTL: RX2WKEN Position */ +#define WHC_WKCTL_RX2WKEN_Msk (0x1ul << WHC_WKCTL_RX2WKEN_Pos) /*!< WHC_T::WKCTL: RX2WKEN Mask */ + +#define WHC_WKCTL_RX3WKEN_Pos (27) /*!< WHC_T::WKCTL: RX3WKEN Position */ +#define WHC_WKCTL_RX3WKEN_Msk (0x1ul << WHC_WKCTL_RX3WKEN_Pos) /*!< WHC_T::WKCTL: RX3WKEN Mask */ + +#define WHC_INTEN_RST0IEN_Pos (0) /*!< WHC_T::INTEN: RST0IEN Position */ +#define WHC_INTEN_RST0IEN_Msk (0x1ul << WHC_INTEN_RST0IEN_Pos) /*!< WHC_T::INTEN: RST0IEN Mask */ + +#define WHC_INTEN_POFF0IEN_Pos (1) /*!< WHC_T::INTEN: POFF0IEN Position */ +#define WHC_INTEN_POFF0IEN_Msk (0x1ul << WHC_INTEN_POFF0IEN_Pos) /*!< WHC_T::INTEN: POFF0IEN Mask */ + +#define WHC_INTEN_PD0IEN_Pos (2) /*!< WHC_T::INTEN: PD0IEN Position */ +#define WHC_INTEN_PD0IEN_Msk (0x1ul << WHC_INTEN_PD0IEN_Pos) /*!< WHC_T::INTEN: PD0IEN Mask */ + +#define WHC_INTEN_RST1IEN_Pos (3) /*!< WHC_T::INTEN: RST1IEN Position */ +#define WHC_INTEN_RST1IEN_Msk (0x1ul << WHC_INTEN_RST1IEN_Pos) /*!< WHC_T::INTEN: RST1IEN Mask */ + +#define WHC_INTEN_POFF1IEN_Pos (4) /*!< WHC_T::INTEN: POFF1IEN Position */ +#define WHC_INTEN_POFF1IEN_Msk (0x1ul << WHC_INTEN_POFF1IEN_Pos) /*!< WHC_T::INTEN: POFF1IEN Mask */ + +#define WHC_INTEN_PD1IEN_Pos (5) /*!< WHC_T::INTEN: PD1IEN Position */ +#define WHC_INTEN_PD1IEN_Msk (0x1ul << WHC_INTEN_PD1IEN_Pos) /*!< WHC_T::INTEN: PD1IEN Mask */ + +#define WHC_INTEN_GI0IEN_Pos (8) /*!< WHC_T::INTEN: GI0IEN Position */ +#define WHC_INTEN_GI0IEN_Msk (0x1ul << WHC_INTEN_GI0IEN_Pos) /*!< WHC_T::INTEN: GI0IEN Mask */ + +#define WHC_INTEN_GI1IEN_Pos (9) /*!< WHC_T::INTEN: GI1IEN Position */ +#define WHC_INTEN_GI1IEN_Msk (0x1ul << WHC_INTEN_GI1IEN_Pos) /*!< WHC_T::INTEN: GI1IEN Mask */ + +#define WHC_INTEN_GI2IEN_Pos (10) /*!< WHC_T::INTEN: GI2IEN Position */ +#define WHC_INTEN_GI2IEN_Msk (0x1ul << WHC_INTEN_GI2IEN_Pos) /*!< WHC_T::INTEN: GI2IEN Mask */ + +#define WHC_INTEN_GI3IEN_Pos (11) /*!< WHC_T::INTEN: GI3IEN Position */ +#define WHC_INTEN_GI3IEN_Msk (0x1ul << WHC_INTEN_GI3IEN_Pos) /*!< WHC_T::INTEN: GI3IEN Mask */ + +#define WHC_INTEN_TX0IEN_Pos (16) /*!< WHC_T::INTEN: TX0IEN Position */ +#define WHC_INTEN_TX0IEN_Msk (0x1ul << WHC_INTEN_TX0IEN_Pos) /*!< WHC_T::INTEN: TX0IEN Mask */ + +#define WHC_INTEN_TX1IEN_Pos (17) /*!< WHC_T::INTEN: TX1IEN Position */ +#define WHC_INTEN_TX1IEN_Msk (0x1ul << WHC_INTEN_TX1IEN_Pos) /*!< WHC_T::INTEN: TX1IEN Mask */ + +#define WHC_INTEN_TX2IEN_Pos (18) /*!< WHC_T::INTEN: TX2IEN Position */ +#define WHC_INTEN_TX2IEN_Msk (0x1ul << WHC_INTEN_TX2IEN_Pos) /*!< WHC_T::INTEN: TX2IEN Mask */ + +#define WHC_INTEN_TX3IEN_Pos (19) /*!< WHC_T::INTEN: TX3IEN Position */ +#define WHC_INTEN_TX3IEN_Msk (0x1ul << WHC_INTEN_TX3IEN_Pos) /*!< WHC_T::INTEN: TX3IEN Mask */ + +#define WHC_INTEN_RX0IEN_Pos (24) /*!< WHC_T::INTEN: RX0IEN Position */ +#define WHC_INTEN_RX0IEN_Msk (0x1ul << WHC_INTEN_RX0IEN_Pos) /*!< WHC_T::INTEN: RX0IEN Mask */ + +#define WHC_INTEN_RX1IEN_Pos (25) /*!< WHC_T::INTEN: RX1IEN Position */ +#define WHC_INTEN_RX1IEN_Msk (0x1ul << WHC_INTEN_RX1IEN_Pos) /*!< WHC_T::INTEN: RX1IEN Mask */ + +#define WHC_INTEN_RX2IEN_Pos (26) /*!< WHC_T::INTEN: RX2IEN Position */ +#define WHC_INTEN_RX2IEN_Msk (0x1ul << WHC_INTEN_RX2IEN_Pos) /*!< WHC_T::INTEN: RX2IEN Mask */ + +#define WHC_INTEN_RX3IEN_Pos (27) /*!< WHC_T::INTEN: RX3IEN Position */ +#define WHC_INTEN_RX3IEN_Msk (0x1ul << WHC_INTEN_RX3IEN_Pos) /*!< WHC_T::INTEN: RX3IEN Mask */ + +#define WHC_INTSTS_RST0IF_Pos (0) /*!< WHC_T::INTSTS: RST0IF Position */ +#define WHC_INTSTS_RST0IF_Msk (0x1ul << WHC_INTSTS_RST0IF_Pos) /*!< WHC_T::INTSTS: RST0IF Mask */ + +#define WHC_INTSTS_POFF0IF_Pos (1) /*!< WHC_T::INTSTS: POFF0IF Position */ +#define WHC_INTSTS_POFF0IF_Msk (0x1ul << WHC_INTSTS_POFF0IF_Pos) /*!< WHC_T::INTSTS: POFF0IF Mask */ + +#define WHC_INTSTS_PD0IF_Pos (2) /*!< WHC_T::INTSTS: PD0IF Position */ +#define WHC_INTSTS_PD0IF_Msk (0x1ul << WHC_INTSTS_PD0IF_Pos) /*!< WHC_T::INTSTS: PD0IF Mask */ + +#define WHC_INTSTS_RST1IF_Pos (3) /*!< WHC_T::INTSTS: RST1IF Position */ +#define WHC_INTSTS_RST1IF_Msk (0x1ul << WHC_INTSTS_RST1IF_Pos) /*!< WHC_T::INTSTS: RST1IF Mask */ + +#define WHC_INTSTS_POFF1IF_Pos (4) /*!< WHC_T::INTSTS: POFF1IF Position */ +#define WHC_INTSTS_POFF1IF_Msk (0x1ul << WHC_INTSTS_POFF1IF_Pos) /*!< WHC_T::INTSTS: POFF1IF Mask */ + +#define WHC_INTSTS_PD1IF_Pos (5) /*!< WHC_T::INTSTS: PD1IF Position */ +#define WHC_INTSTS_PD1IF_Msk (0x1ul << WHC_INTSTS_PD1IF_Pos) /*!< WHC_T::INTSTS: PD1IF Mask */ + +#define WHC_INTSTS_GI0IF_Pos (8) /*!< WHC_T::INTSTS: GI0IF Position */ +#define WHC_INTSTS_GI0IF_Msk (0x1ul << WHC_INTSTS_GI0IF_Pos) /*!< WHC_T::INTSTS: GI0IF Mask */ + +#define WHC_INTSTS_GI1IF_Pos (9) /*!< WHC_T::INTSTS: GI1IF Position */ +#define WHC_INTSTS_GI1IF_Msk (0x1ul << WHC_INTSTS_GI1IF_Pos) /*!< WHC_T::INTSTS: GI1IF Mask */ + +#define WHC_INTSTS_GI2IF_Pos (10) /*!< WHC_T::INTSTS: GI2IF Position */ +#define WHC_INTSTS_GI2IF_Msk (0x1ul << WHC_INTSTS_GI2IF_Pos) /*!< WHC_T::INTSTS: GI2IF Mask */ + +#define WHC_INTSTS_GI3IF_Pos (11) /*!< WHC_T::INTSTS: GI3IF Position */ +#define WHC_INTSTS_GI3IF_Msk (0x1ul << WHC_INTSTS_GI3IF_Pos) /*!< WHC_T::INTSTS: GI3IF Mask */ + +#define WHC_INTSTS_TX0IF_Pos (16) /*!< WHC_T::INTSTS: TX0IF Position */ +#define WHC_INTSTS_TX0IF_Msk (0x1ul << WHC_INTSTS_TX0IF_Pos) /*!< WHC_T::INTSTS: TX0IF Mask */ + +#define WHC_INTSTS_TX1IF_Pos (17) /*!< WHC_T::INTSTS: TX1IF Position */ +#define WHC_INTSTS_TX1IF_Msk (0x1ul << WHC_INTSTS_TX1IF_Pos) /*!< WHC_T::INTSTS: TX1IF Mask */ + +#define WHC_INTSTS_TX2IF_Pos (18) /*!< WHC_T::INTSTS: TX2IF Position */ +#define WHC_INTSTS_TX2IF_Msk (0x1ul << WHC_INTSTS_TX2IF_Pos) /*!< WHC_T::INTSTS: TX2IF Mask */ + +#define WHC_INTSTS_TX3IF_Pos (19) /*!< WHC_T::INTSTS: TX3IF Position */ +#define WHC_INTSTS_TX3IF_Msk (0x1ul << WHC_INTSTS_TX3IF_Pos) /*!< WHC_T::INTSTS: TX3IF Mask */ + +#define WHC_INTSTS_RX0IF_Pos (24) /*!< WHC_T::INTSTS: RX0IF Position */ +#define WHC_INTSTS_RX0IF_Msk (0x1ul << WHC_INTSTS_RX0IF_Pos) /*!< WHC_T::INTSTS: RX0IF Mask */ + +#define WHC_INTSTS_RX1IF_Pos (25) /*!< WHC_T::INTSTS: RX1IF Position */ +#define WHC_INTSTS_RX1IF_Msk (0x1ul << WHC_INTSTS_RX1IF_Pos) /*!< WHC_T::INTSTS: RX1IF Mask */ + +#define WHC_INTSTS_RX2IF_Pos (26) /*!< WHC_T::INTSTS: RX2IF Position */ +#define WHC_INTSTS_RX2IF_Msk (0x1ul << WHC_INTSTS_RX2IF_Pos) /*!< WHC_T::INTSTS: RX2IF Mask */ + +#define WHC_INTSTS_RX3IF_Pos (27) /*!< WHC_T::INTSTS: RX3IF Position */ +#define WHC_INTSTS_RX3IF_Msk (0x1ul << WHC_INTSTS_RX3IF_Pos) /*!< WHC_T::INTSTS: RX3IF Mask */ + +#define WHC_CPSTS_WDTRF_Pos (2) /*!< WHC_T::CPSTS: WDTRF Position */ +#define WHC_CPSTS_WDTRF_Msk (0x1ul << WHC_CPSTS_WDTRF_Pos) /*!< WHC_T::CPSTS: WDTRF Mask */ + +#define WHC_CPSTS_SYSRF_Pos (5) /*!< WHC_T::CPSTS: SYSRF Position */ +#define WHC_CPSTS_SYSRF_Msk (0x1ul << WHC_CPSTS_SYSRF_Pos) /*!< WHC_T::CPSTS: SYSRF Mask */ + +#define WHC_CPSTS_CPURF_Pos (7) /*!< WHC_T::CPSTS: CPURF Position */ +#define WHC_CPSTS_CPURF_Msk (0x1ul << WHC_CPSTS_CPURF_Pos) /*!< WHC_T::CPSTS: CPURF Mask */ + +#define WHC_CPSTS_CPULKRF_Pos (8) /*!< WHC_T::CPSTS: CPULKRF Position */ +#define WHC_CPSTS_CPULKRF_Msk (0x1ul << WHC_CPSTS_CPULKRF_Pos) /*!< WHC_T::CPSTS: CPULKRF Mask */ + +#define WHC_CPSTS_OPMODE0_Pos (24) /*!< WHC_T::CPSTS: OPMODE0 Position */ +#define WHC_CPSTS_OPMODE0_Msk (0xful << WHC_CPSTS_OPMODE0_Pos) /*!< WHC_T::CPSTS: OPMODE0 Mask */ + +#define WHC_CPSTS_OPMODE1_Pos (28) /*!< WHC_T::CPSTS: OPMODE1 Position */ +#define WHC_CPSTS_OPMODE1_Msk (0xful << WHC_CPSTS_OPMODE1_Pos) /*!< WHC_T::CPSTS: OPMODE1 Mask */ + +#define WHC_GINTTRG_TRGGI0_Pos (0) /*!< WHC_T::GINTTRG: TRGGI0 Position */ +#define WHC_GINTTRG_TRGGI0_Msk (0x1ul << WHC_GINTTRG_TRGGI0_Pos) /*!< WHC_T::GINTTRG: TRGGI0 Mask */ + +#define WHC_GINTTRG_TRGGI1_Pos (1) /*!< WHC_T::GINTTRG: TRGGI1 Position */ +#define WHC_GINTTRG_TRGGI1_Msk (0x1ul << WHC_GINTTRG_TRGGI1_Pos) /*!< WHC_T::GINTTRG: TRGGI1 Mask */ + +#define WHC_GINTTRG_TRGGI2_Pos (2) /*!< WHC_T::GINTTRG: TRGGI2 Position */ +#define WHC_GINTTRG_TRGGI2_Msk (0x1ul << WHC_GINTTRG_TRGGI2_Pos) /*!< WHC_T::GINTTRG: TRGGI2 Mask */ + +#define WHC_GINTTRG_TRGGI3_Pos (3) /*!< WHC_T::GINTTRG: TRGGI3 Position */ +#define WHC_GINTTRG_TRGGI3_Msk (0x1ul << WHC_GINTTRG_TRGGI3_Pos) /*!< WHC_T::GINTTRG: TRGGI3 Mask */ + +#define WHC_TXCTL_CH0SND_Pos (0) /*!< WHC_T::TXCTL: CH0SND Position */ +#define WHC_TXCTL_CH0SND_Msk (0x1ul << WHC_TXCTL_CH0SND_Pos) /*!< WHC_T::TXCTL: CH0SND Mask */ + +#define WHC_TXCTL_CH1SND_Pos (1) /*!< WHC_T::TXCTL: CH1SND Position */ +#define WHC_TXCTL_CH1SND_Msk (0x1ul << WHC_TXCTL_CH1SND_Pos) /*!< WHC_T::TXCTL: CH1SND Mask */ + +#define WHC_TXCTL_CH2SND_Pos (2) /*!< WHC_T::TXCTL: CH2SND Position */ +#define WHC_TXCTL_CH2SND_Msk (0x1ul << WHC_TXCTL_CH2SND_Pos) /*!< WHC_T::TXCTL: CH2SND Mask */ + +#define WHC_TXCTL_CH3SND_Pos (3) /*!< WHC_T::TXCTL: CH3SND Position */ +#define WHC_TXCTL_CH3SND_Msk (0x1ul << WHC_TXCTL_CH3SND_Pos) /*!< WHC_T::TXCTL: CH3SND Mask */ + +#define WHC_TXCTL_CH0RC_Pos (16) /*!< WHC_T::TXCTL: CH0RC Position */ +#define WHC_TXCTL_CH0RC_Msk (0x1ul << WHC_TXCTL_CH0RC_Pos) /*!< WHC_T::TXCTL: CH0RC Mask */ + +#define WHC_TXCTL_CH1RC_Pos (17) /*!< WHC_T::TXCTL: CH1RC Position */ +#define WHC_TXCTL_CH1RC_Msk (0x1ul << WHC_TXCTL_CH1RC_Pos) /*!< WHC_T::TXCTL: CH1RC Mask */ + +#define WHC_TXCTL_CH2RC_Pos (18) /*!< WHC_T::TXCTL: CH2RC Position */ +#define WHC_TXCTL_CH2RC_Msk (0x1ul << WHC_TXCTL_CH2RC_Pos) /*!< WHC_T::TXCTL: CH2RC Mask */ + +#define WHC_TXCTL_CH3RC_Pos (19) /*!< WHC_T::TXCTL: CH3RC Position */ +#define WHC_TXCTL_CH3RC_Msk (0x1ul << WHC_TXCTL_CH3RC_Pos) /*!< WHC_T::TXCTL: CH3RC Mask */ + +#define WHC_TXSTS_CH0RDY_Pos (0) /*!< WHC_T::TXSTS: CH0RDY Position */ +#define WHC_TXSTS_CH0RDY_Msk (0x1ul << WHC_TXSTS_CH0RDY_Pos) /*!< WHC_T::TXSTS: CH0RDY Mask */ + +#define WHC_TXSTS_CH1RDY_Pos (1) /*!< WHC_T::TXSTS: CH1RDY Position */ +#define WHC_TXSTS_CH1RDY_Msk (0x1ul << WHC_TXSTS_CH1RDY_Pos) /*!< WHC_T::TXSTS: CH1RDY Mask */ + +#define WHC_TXSTS_CH2RDY_Pos (2) /*!< WHC_T::TXSTS: CH2RDY Position */ +#define WHC_TXSTS_CH2RDY_Msk (0x1ul << WHC_TXSTS_CH2RDY_Pos) /*!< WHC_T::TXSTS: CH2RDY Mask */ + +#define WHC_TXSTS_CH3RDY_Pos (3) /*!< WHC_T::TXSTS: CH3RDY Position */ +#define WHC_TXSTS_CH3RDY_Msk (0x1ul << WHC_TXSTS_CH3RDY_Pos) /*!< WHC_T::TXSTS: CH3RDY Mask */ + +#define WHC_RXCTL_CH0ACK_Pos (0) /*!< WHC_T::RXCTL: CH0ACK Position */ +#define WHC_RXCTL_CH0ACK_Msk (0x1ul << WHC_RXCTL_CH0ACK_Pos) /*!< WHC_T::RXCTL: CH0ACK Mask */ + +#define WHC_RXCTL_CH1ACK_Pos (1) /*!< WHC_T::RXCTL: CH1ACK Position */ +#define WHC_RXCTL_CH1ACK_Msk (0x1ul << WHC_RXCTL_CH1ACK_Pos) /*!< WHC_T::RXCTL: CH1ACK Mask */ + +#define WHC_RXCTL_CH2ACK_Pos (2) /*!< WHC_T::RXCTL: CH2ACK Position */ +#define WHC_RXCTL_CH2ACK_Msk (0x1ul << WHC_RXCTL_CH2ACK_Pos) /*!< WHC_T::RXCTL: CH2ACK Mask */ + +#define WHC_RXCTL_CH3ACK_Pos (3) /*!< WHC_T::RXCTL: CH3ACK Position */ +#define WHC_RXCTL_CH3ACK_Msk (0x1ul << WHC_RXCTL_CH3ACK_Pos) /*!< WHC_T::RXCTL: CH3ACK Mask */ + +#define WHC_RXSTS_CH0RDY_Pos (0) /*!< WHC_T::RXSTS: CH0RDY Position */ +#define WHC_RXSTS_CH0RDY_Msk (0x1ul << WHC_RXSTS_CH0RDY_Pos) /*!< WHC_T::RXSTS: CH0RDY Mask */ + +#define WHC_RXSTS_CH1RDY_Pos (1) /*!< WHC_T::RXSTS: CH1RDY Position */ +#define WHC_RXSTS_CH1RDY_Msk (0x1ul << WHC_RXSTS_CH1RDY_Pos) /*!< WHC_T::RXSTS: CH1RDY Mask */ + +#define WHC_RXSTS_CH2RDY_Pos (2) /*!< WHC_T::RXSTS: CH2RDY Position */ +#define WHC_RXSTS_CH2RDY_Msk (0x1ul << WHC_RXSTS_CH2RDY_Pos) /*!< WHC_T::RXSTS: CH2RDY Mask */ + +#define WHC_RXSTS_CH3RDY_Pos (3) /*!< WHC_T::RXSTS: CH3RDY Position */ +#define WHC_RXSTS_CH3RDY_Msk (0x1ul << WHC_RXSTS_CH3RDY_Pos) /*!< WHC_T::RXSTS: CH3RDY Mask */ + +#define WHC_TMDAT_DAT_Pos (0) /*!< WHC_T::TMDAT: DATA Position */ +#define WHC_TMDAT_DAT_Msk (0xfffffffful << WHC_TMDAT_DAT_Pos) /*!< WHC_T::TMDAT: DATA Mask */ + +#define WHC_RMDAT_DAT_Pos (0) /*!< WHC_T::RMDAT: DATA Position */ +#define WHC_RMDAT_DAT_Msk (0xfffffffful << WHC_RMDAT_DAT_Pos) /*!< WHC_T::RMDAT: DATA Mask */ + +/**@}*/ /* WHC_CONST */ +/**@}*/ /* end of WHC register group */ +/**@}*/ /* end of REGISTER group */ + +#if defined ( __CC_ARM ) + #pragma no_anon_unions +#endif + +#endif /* __WHC_REG_H__ */ diff --git a/bsp/nuvoton/libraries/ma35/Device/Nuvoton/MA35D1/Include/wwdt_reg.h b/bsp/nuvoton/libraries/ma35/Device/Nuvoton/MA35D1/Include/wwdt_reg.h new file mode 100644 index 0000000000..d87c7e534e --- /dev/null +++ b/bsp/nuvoton/libraries/ma35/Device/Nuvoton/MA35D1/Include/wwdt_reg.h @@ -0,0 +1,147 @@ +/**************************************************************************//** + * @file wwdt_reg.h + * @brief WWDT register definition header file + * + * SPDX-License-Identifier: Apache-2.0 + * @copyright (C) 2020 Nuvoton Technology Corp. All rights reserved. + *****************************************************************************/ +#ifndef __WWDT_REG_H__ +#define __WWDT_REG_H__ + +#if defined ( __CC_ARM ) + #pragma anon_unions +#endif + +/** + @addtogroup REGISTER Control Register + @{ +*/ + +/** + @addtogroup WWDT Window Watchdog Timer(WWDT) + Memory Mapped Structure for WWDT Controller +@{ */ + +typedef struct +{ + + + /** + * @var WWDT_T::RLDCNT + * Offset: 0x00 WWDT Reload Counter Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[31:0] |RLDCNT |WWDT Reload Counter Register + * | | |Writing 0x00005AA5 to this register will reload the WWDT counter value to 0x3F. + * | | |Note: User can only write WWDT_RLDCNT register to reload WWDT counter value when current WWDT counter value between 0 and CMPDAT (WWDT_CTL[21:16]) + * | | |If user writes WWDT_RLDCNT when current WWDT counter value is larger than CMPDAT, WWDT reset signal will be generated. + * @var WWDT_T::CTL + * Offset: 0x04 WWDT Control Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[0] |WWDTEN |WWDT Enable Bit + * | | |0 = WWDT counter is stopped. + * | | |1 = WWDT counter starts counting. + * |[1] |INTEN |WWDT Interrupt Enable Bit + * | | |If this bit is enabled, the WWDT counter compare match interrupt signal is generated and inform to CPU. + * | | |0 = WWDT counter compare match interrupt Disabled. + * | | |1 = WWDT counter compare match interrupt Enabled. + * |[11:8] |PSCSEL |WWDT Counter Prescale Period Selection + * | | |0000 = Pre-scale is 1; Max time-out period is 1 * 64 * WWDT_CLK. + * | | |0001 = Pre-scale is 2; Max time-out period is 2 * 64 * WWDT_CLK. + * | | |0010 = Pre-scale is 4; Max time-out period is 4 * 64 * WWDT_CLK. + * | | |0011 = Pre-scale is 8; Max time-out period is 8 * 64 * WWDT_CLK. + * | | |0100 = Pre-scale is 16; Max time-out period is 16 * 64 * WWDT_CLK. + * | | |0101 = Pre-scale is 32; Max time-out period is 32 * 64 * WWDT_CLK. + * | | |0110 = Pre-scale is 64; Max time-out period is 64 * 64 * WWDT_CLK. + * | | |0111 = Pre-scale is 128; Max time-out period is 128 * 64 * WWDT_CLK. + * | | |1000 = Pre-scale is 192; Max time-out period is 192 * 64 * WWDT_CLK. + * | | |1001 = Pre-scale is 256; Max time-out period is 256 * 64 * WWDT_CLK. + * | | |1010 = Pre-scale is 384; Max time-out period is 384 * 64 * WWDT_CLK. + * | | |1011 = Pre-scale is 512; Max time-out period is 512 * 64 * WWDT_CLK. + * | | |1100 = Pre-scale is 768; Max time-out period is 768 * 64 * WWDT_CLK. + * | | |1101 = Pre-scale is 1024; Max time-out period is 1024 * 64 * WWDT_CLK. + * | | |1110 = Pre-scale is 1536; Max time-out period is 1536 * 64 * WWDT_CLK. + * | | |1111 = Pre-scale is 2048; Max time-out period is 2048 * 64 * WWDT_CLK. + * |[21:16] |CMPDAT |WWDT Window Compare Register + * | | |Set this register to adjust the valid reload window. + * | | |Note: User can only write WWDT_RLDCNT register to reload WWDT counter value when current WWDT counter value between 0 and CMPDAT + * | | |If user writes WWDT_RLDCNT register when current WWDT counter value larger than CMPDAT, WWDT reset signal will generate. + * |[31] |ICEDEBUG |ICE Debug Mode Acknowledge Disable Bit + * | | |0 = ICE debug mode acknowledgement effects WWDT counting. + * | | |WWDT down counter will be held while CPU is held by ICE. + * | | |1 = ICE debug mode acknowledgement Disabled. + * | | |Note: WWDT down counter will keep going no matter CPU is held by ICE or not. + * @var WWDT_T::STATUS + * Offset: 0x08 WWDT Status Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[0] |WWDTIF |WWDT Compare Match Interrupt Flag + * | | |This bit indicates the interrupt flag status of WWDT while WWDT counter value matches CMPDAT (WWDT_CTL[21:16]). + * | | |0 = No effect. + * | | |1 = WWDT counter value matches CMPDAT. + * | | |Note: This bit is cleared by writing 1 to it. + * |[1] |WWDTRF |WWDT Timer-out Reset Flag + * | | |This bit indicates the system has been reset by WWDT time-out reset or not. + * | | |0 = WWDT time-out reset did not occur. + * | | |1 = WWDT time-out reset occurred. + * | | |Note: This bit is cleared by writing 1 to it. + * @var WWDT_T::CNT + * Offset: 0x0C WWDT Counter Value Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[5:0] |CNTDAT |WWDT Counter Value + * | | |CNTDAT will be updated continuously to monitor 6-bit WWDT down counter value. + */ + __O uint32_t RLDCNT; /*!< [0x0000] WWDT Reload Counter Register */ + __IO uint32_t CTL; /*!< [0x0004] WWDT Control Register */ + __IO uint32_t STATUS; /*!< [0x0008] WWDT Status Register */ + __I uint32_t CNT; /*!< [0x000c] WWDT Counter Value Register */ + +} WWDT_T; + +/** + @addtogroup WWDT_CONST WWDT Bit Field Definition + Constant Definitions for WWDT Controller +@{ */ + +#define WWDT_RLDCNT_RLDCNT_Pos (0) /*!< WWDT_T::RLDCNT: RLDCNT Position */ +#define WWDT_RLDCNT_RLDCNT_Msk (0xfffffffful << WWDT_RLDCNT_RLDCNT_Pos) /*!< WWDT_T::RLDCNT: RLDCNT Mask */ + +#define WWDT_CTL_WWDTEN_Pos (0) /*!< WWDT_T::CTL: WWDTEN Position */ +#define WWDT_CTL_WWDTEN_Msk (0x1ul << WWDT_CTL_WWDTEN_Pos) /*!< WWDT_T::CTL: WWDTEN Mask */ + +#define WWDT_CTL_INTEN_Pos (1) /*!< WWDT_T::CTL: INTEN Position */ +#define WWDT_CTL_INTEN_Msk (0x1ul << WWDT_CTL_INTEN_Pos) /*!< WWDT_T::CTL: INTEN Mask */ + +#define WWDT_CTL_PSCSEL_Pos (8) /*!< WWDT_T::CTL: PSCSEL Position */ +#define WWDT_CTL_PSCSEL_Msk (0xful << WWDT_CTL_PSCSEL_Pos) /*!< WWDT_T::CTL: PSCSEL Mask */ + +#define WWDT_CTL_CMPDAT_Pos (16) /*!< WWDT_T::CTL: CMPDAT Position */ +#define WWDT_CTL_CMPDAT_Msk (0x3ful << WWDT_CTL_CMPDAT_Pos) /*!< WWDT_T::CTL: CMPDAT Mask */ + +#define WWDT_CTL_ICEDEBUG_Pos (31) /*!< WWDT_T::CTL: ICEDEBUG Position */ +#define WWDT_CTL_ICEDEBUG_Msk (0x1ul << WWDT_CTL_ICEDEBUG_Pos) /*!< WWDT_T::CTL: ICEDEBUG Mask */ + +#define WWDT_STATUS_WWDTIF_Pos (0) /*!< WWDT_T::STATUS: WWDTIF Position */ +#define WWDT_STATUS_WWDTIF_Msk (0x1ul << WWDT_STATUS_WWDTIF_Pos) /*!< WWDT_T::STATUS: WWDTIF Mask */ + +#define WWDT_STATUS_WWDTRF_Pos (1) /*!< WWDT_T::STATUS: WWDTRF Position */ +#define WWDT_STATUS_WWDTRF_Msk (0x1ul << WWDT_STATUS_WWDTRF_Pos) /*!< WWDT_T::STATUS: WWDTRF Mask */ + +#define WWDT_CNT_CNTDAT_Pos (0) /*!< WWDT_T::CNT: CNTDAT Position */ +#define WWDT_CNT_CNTDAT_Msk (0x3ful << WWDT_CNT_CNTDAT_Pos) /*!< WWDT_T::CNT: CNTDAT Mask */ + +/**@}*/ /* WWDT_CONST */ +/**@}*/ /* end of WWDT register group */ +/**@}*/ /* end of REGISTER group */ + +#if defined ( __CC_ARM ) + #pragma no_anon_unions +#endif + +#endif /* __WWDT_REG_H__ */ diff --git a/bsp/nuvoton/libraries/ma35/Device/Nuvoton/MA35D1/Source/ARM/startup_ma35d1_subm.s b/bsp/nuvoton/libraries/ma35/Device/Nuvoton/MA35D1/Source/ARM/startup_ma35d1_subm.s new file mode 100644 index 0000000000..a8e1659dff --- /dev/null +++ b/bsp/nuvoton/libraries/ma35/Device/Nuvoton/MA35D1/Source/ARM/startup_ma35d1_subm.s @@ -0,0 +1,488 @@ +;/****************************************************************************** +; * @file startup_ma35d1_subm.s +; * @brief CMSIS Cortex-M4 Core Device Startup File +; * +; * SPDX-License-Identifier: Apache-2.0 +; * @copyright (C) 2020 Nuvoton Technology Corp. All rights reserved. +;*****************************************************************************/ +;/* +;//-------- <<< Use Configuration Wizard in Context Menu >>> ------------------ +;*/ + + +; Stack Configuration +; Stack Size (in Bytes) <0x0-0xFFFFFFFF:8> +; + + IF :LNOT: :DEF: Stack_Size +Stack_Size EQU 0x00001000 + ENDIF + + AREA STACK, NOINIT, READWRITE, ALIGN=3 +Stack_Mem SPACE Stack_Size + EXPORT __initial_sp +__initial_sp + +; Heap Configuration +; Heap Size (in Bytes) <0x0-0xFFFFFFFF:8> +; + + IF :LNOT: :DEF: Heap_Size +Heap_Size EQU 0x00000100 + ENDIF + + AREA HEAP, NOINIT, READWRITE, ALIGN=3 +__heap_base +Heap_Mem SPACE Heap_Size +__heap_limit + + + PRESERVE8 + THUMB + + +; Vector Table Mapped to Address 0 at Reset + + AREA RESET, DATA, READONLY + EXPORT __Vectors + EXPORT __Vectors_End + EXPORT __Vectors_Size + +__Vectors DCD __initial_sp ; Top of Stack + DCD Reset_Handler ; Reset Handler + DCD NMI_Handler ; NMI Handler + DCD HardFault_Handler ; Hard Fault Handler + DCD MemManage_Handler ; MPU Fault Handler + DCD BusFault_Handler ; Bus Fault Handler + DCD UsageFault_Handler ; Usage Fault Handler + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD SVC_Handler ; SVCall Handler + DCD DebugMon_Handler ; Debug Monitor Handler + DCD 0 ; Reserved + DCD PendSV_Handler ; PendSV Handler + DCD SysTick_Handler ; SysTick Handler + + ; External Interrupts + DCD LVD_IRQHandler ; 0 + DCD Default_Handler ; 1 + DCD PWRWU_IRQHandler ; 2 + DCD HWSEM0_IRQHandler ; 3 + DCD CKFAIL_IRQHandler ; 4 + DCD WHC0_IRQHandler ; 5 + DCD RTC_IRQHandler ; 6 + DCD TAMPER_IRQHandler ; 7 + DCD WDT2_IRQHandler ; 8 + DCD WWDT2_IRQHandler ; 9 + DCD EINT0_IRQHandler ; 10 + DCD EINT1_IRQHandler ; 11 + DCD EINT2_IRQHandler ; 12 + DCD EINT3_IRQHandler ; 13 + DCD Default_Handler ; 14 + DCD Default_Handler ; 15 + DCD GPA_IRQHandler ; 16 + DCD GPB_IRQHandler ; 17 + DCD GPC_IRQHandler ; 18 + DCD GPD_IRQHandler ; 19 + DCD Default_Handler ; 20 + DCD Default_Handler ; 21 + DCD TMR2_IRQHandler ; 22 + DCD TMR3_IRQHandler ; 23 + DCD BRAKE0_IRQHandler ; 24 + DCD EPWM0P0_IRQHandler ; 25 + DCD EPWM0P1_IRQHandler ; 26 + DCD EPWM0P2_IRQHandler ; 27 + DCD QEI0_IRQHandler ; 28 + DCD ECAP0_IRQHandler ; 29 + DCD Default_Handler ; 30 + DCD QSPI1_IRQHandler ; 31 + DCD Default_Handler ; 32 + DCD Default_Handler ; 33 + DCD Default_Handler ; 34 + DCD UART1_IRQHandler ; 35 + DCD UART2_IRQHandler ; 36 + DCD UART3_IRQHandler ; 37 + DCD UART4_IRQHandler ; 38 + DCD UART5_IRQHandler ; 39 + DCD EADC00_IRQHandler ; 40 + DCD EADC01_IRQHandler ; 41 + DCD EADC02_IRQHandler ; 42 + DCD EADC03_IRQHandler ; 43 + DCD Default_Handler ; 44 + DCD I2C1_IRQHandler ; 45 + DCD I2S0_IRQHandler ; 46 + DCD CANFD00_IRQHandler ; 47 + DCD SC0_IRQHandler ; 48 + DCD GPE_IRQHandler ; 49 + DCD GPF_IRQHandler ; 50 + DCD GPG_IRQHandler ; 51 + DCD GPH_IRQHandler ; 52 + DCD GPI_IRQHandler ; 53 + DCD GPJ_IRQHandler ; 54 + DCD TMR4_IRQHandler ; 55 + DCD TMR5_IRQHandler ; 56 + DCD TMR6_IRQHandler ; 57 + DCD TMR7_IRQHandler ; 58 + DCD BRAKE1_IRQHandler ; 59 + DCD EPWM1P0_IRQHandler ; 60 + DCD EPWM1P1_IRQHandler ; 61 + DCD EPWM1P2_IRQHandler ; 62 + DCD QEI1_IRQHandler ; 63 + DCD ECAP1_IRQHandler ; 64 + DCD SPI0_IRQHandler ; 65 + DCD SPI1_IRQHandler ; 66 + DCD PDMA2_IRQHandler ; 67 + DCD PDMA3_IRQHandler ; 68 + DCD UART6_IRQHandler ; 69 + DCD UART7_IRQHandler ; 70 + DCD UART8_IRQHandler ; 71 + DCD UART9_IRQHandler ; 72 + DCD UART10_IRQHandler ; 73 + DCD UART11_IRQHandler ; 74 + DCD I2C2_IRQHandler ; 75 + DCD I2C3_IRQHandler ; 76 + DCD I2S1_IRQHandler ; 77 + DCD CANFD10_IRQHandler ; 78 + DCD SC1_IRQHandler ; 79 + DCD GPK_IRQHandler ; 80 + DCD GPL_IRQHandler ; 81 + DCD GPM_IRQHandler ; 82 + DCD GPN_IRQHandler ; 83 + DCD TMR8_IRQHandler ; 84 + DCD TMR9_IRQHandler ; 85 + DCD TMR10_IRQHandler ; 86 + DCD TMR11_IRQHandler ; 87 + DCD BRAKE2_IRQHandler ; 88 + DCD EPWM2P0_IRQHandle ; 89 + DCD EPWM2P1_IRQHandle ; 90 + DCD EPWM2P2_IRQHandle ; 91 + DCD QEI2_IRQHandler ; 92 + DCD ECAP2_IRQHandler ; 93 + DCD SPI2_IRQHandler ; 94 + DCD SPI3_IRQHandler ; 95 + DCD UART12_IRQHandler ; 96 + DCD UART13_IRQHandler ; 97 + DCD UART14_IRQHandler ; 98 + DCD UART15_IRQHandler ; 99 + DCD UART16_IRQHandler ; 100 + DCD I2C4_IRQHandler ; 101 + DCD I2C5_IRQHandler ; 102 + DCD CANFD20_IRQHandler ; 103 + DCD CANFD30_IRQHandler ; 104 + DCD KPI_IRQHandler ; 105 + DCD CANFD01_IRQHandler ; 106 + DCD CANFD11_IRQHandler ; 107 + DCD CANFD21_IRQHandler ; 108 + DCD CANFD31_IRQHandler ; 109 + DCD ADC0_IRQHandler ; 110 +__Vectors_End + +__Vectors_Size EQU __Vectors_End - __Vectors + + AREA |.text|, CODE, READONLY + + +; Reset Handler + +Reset_Handler PROC + EXPORT Reset_Handler [WEAK] + IMPORT SystemInit + IMPORT __main + + LDR R0, =SystemInit + BLX R0 + + LDR R0, =__main + BX R0 + + ENDP + + +; Dummy Exception Handlers (infinite loops which can be modified) + +NMI_Handler PROC + EXPORT NMI_Handler [WEAK] + B . + ENDP +HardFault_Handler\ + PROC + EXPORT HardFault_Handler [WEAK] + B . + ENDP +MemManage_Handler\ + PROC + EXPORT MemManage_Handler [WEAK] + B . + ENDP +BusFault_Handler\ + PROC + EXPORT BusFault_Handler [WEAK] + B . + ENDP +UsageFault_Handler\ + PROC + EXPORT UsageFault_Handler [WEAK] + B . + ENDP +SVC_Handler PROC + EXPORT SVC_Handler [WEAK] + B . + ENDP +DebugMon_Handler\ + PROC + EXPORT DebugMon_Handler [WEAK] + B . + ENDP +PendSV_Handler\ + PROC + EXPORT PendSV_Handler [WEAK] + B . + ENDP +SysTick_Handler\ + PROC + EXPORT SysTick_Handler [WEAK] + B . + ENDP + +Default_Handler PROC + + EXPORT LVD_IRQHandler [WEAK] + EXPORT PWRWU_IRQHandler [WEAK] + EXPORT HWSEM0_IRQHandler [WEAK] + EXPORT CKFAIL_IRQHandler [WEAK] + EXPORT WHC0_IRQHandler [WEAK] + EXPORT RTC_IRQHandler [WEAK] + EXPORT TAMPER_IRQHandler [WEAK] + EXPORT WDT2_IRQHandler [WEAK] + EXPORT WWDT2_IRQHandler [WEAK] + EXPORT EINT0_IRQHandler [WEAK] + EXPORT EINT1_IRQHandler [WEAK] + EXPORT EINT2_IRQHandler [WEAK] + EXPORT EINT3_IRQHandler [WEAK] + EXPORT GPA_IRQHandler [WEAK] + EXPORT GPB_IRQHandler [WEAK] + EXPORT GPC_IRQHandler [WEAK] + EXPORT GPD_IRQHandler [WEAK] + EXPORT TMR2_IRQHandler [WEAK] + EXPORT TMR3_IRQHandler [WEAK] + EXPORT BRAKE0_IRQHandler [WEAK] + EXPORT EPWM0P0_IRQHandler [WEAK] + EXPORT EPWM0P1_IRQHandler [WEAK] + EXPORT EPWM0P2_IRQHandler [WEAK] + EXPORT QEI0_IRQHandler [WEAK] + EXPORT ECAP0_IRQHandler [WEAK] + EXPORT QSPI1_IRQHandler [WEAK] + EXPORT UART1_IRQHandler [WEAK] + EXPORT UART2_IRQHandler [WEAK] + EXPORT UART3_IRQHandler [WEAK] + EXPORT UART4_IRQHandler [WEAK] + EXPORT UART5_IRQHandler [WEAK] + EXPORT EADC00_IRQHandler [WEAK] + EXPORT EADC01_IRQHandler [WEAK] + EXPORT EADC02_IRQHandler [WEAK] + EXPORT EADC03_IRQHandler [WEAK] + EXPORT I2C1_IRQHandler [WEAK] + EXPORT I2S0_IRQHandler [WEAK] + EXPORT CANFD00_IRQHandler [WEAK] + EXPORT SC0_IRQHandler [WEAK] + EXPORT GPE_IRQHandler [WEAK] + EXPORT GPF_IRQHandler [WEAK] + EXPORT GPG_IRQHandler [WEAK] + EXPORT GPH_IRQHandler [WEAK] + EXPORT GPI_IRQHandler [WEAK] + EXPORT GPJ_IRQHandler [WEAK] + EXPORT TMR4_IRQHandler [WEAK] + EXPORT TMR5_IRQHandler [WEAK] + EXPORT TMR6_IRQHandler [WEAK] + EXPORT TMR7_IRQHandler [WEAK] + EXPORT BRAKE1_IRQHandler [WEAK] + EXPORT EPWM1P0_IRQHandler [WEAK] + EXPORT EPWM1P1_IRQHandler [WEAK] + EXPORT EPWM1P2_IRQHandler [WEAK] + EXPORT QEI1_IRQHandler [WEAK] + EXPORT ECAP1_IRQHandler [WEAK] + EXPORT SPI0_IRQHandler [WEAK] + EXPORT SPI1_IRQHandler [WEAK] + EXPORT PDMA2_IRQHandler [WEAK] + EXPORT PDMA3_IRQHandler [WEAK] + EXPORT UART6_IRQHandler [WEAK] + EXPORT UART7_IRQHandler [WEAK] + EXPORT UART8_IRQHandler [WEAK] + EXPORT UART9_IRQHandler [WEAK] + EXPORT UART10_IRQHandler [WEAK] + EXPORT UART11_IRQHandler [WEAK] + EXPORT I2C2_IRQHandler [WEAK] + EXPORT I2C3_IRQHandler [WEAK] + EXPORT I2S1_IRQHandler [WEAK] + EXPORT CANFD10_IRQHandler [WEAK] + EXPORT SC1_IRQHandler [WEAK] + EXPORT GPK_IRQHandler [WEAK] + EXPORT GPL_IRQHandler [WEAK] + EXPORT GPM_IRQHandler [WEAK] + EXPORT GPN_IRQHandler [WEAK] + EXPORT TMR8_IRQHandler [WEAK] + EXPORT TMR9_IRQHandler [WEAK] + EXPORT TMR10_IRQHandler [WEAK] + EXPORT TMR11_IRQHandler [WEAK] + EXPORT BRAKE2_IRQHandler [WEAK] + EXPORT EPWM2P0_IRQHandle [WEAK] + EXPORT EPWM2P1_IRQHandle [WEAK] + EXPORT EPWM2P2_IRQHandle [WEAK] + EXPORT QEI2_IRQHandler [WEAK] + EXPORT ECAP2_IRQHandler [WEAK] + EXPORT SPI2_IRQHandler [WEAK] + EXPORT SPI3_IRQHandler [WEAK] + EXPORT UART12_IRQHandler [WEAK] + EXPORT UART13_IRQHandler [WEAK] + EXPORT UART14_IRQHandler [WEAK] + EXPORT UART15_IRQHandler [WEAK] + EXPORT UART16_IRQHandler [WEAK] + EXPORT I2C4_IRQHandler [WEAK] + EXPORT I2C5_IRQHandler [WEAK] + EXPORT CANFD20_IRQHandler [WEAK] + EXPORT CANFD30_IRQHandler [WEAK] + EXPORT KPI_IRQHandler [WEAK] + EXPORT CANFD01_IRQHandler [WEAK] + EXPORT CANFD11_IRQHandler [WEAK] + EXPORT CANFD21_IRQHandler [WEAK] + EXPORT CANFD31_IRQHandler [WEAK] + EXPORT ADC0_IRQHandler [WEAK] + +LVD_IRQHandler +PWRWU_IRQHandler +HWSEM0_IRQHandler +CKFAIL_IRQHandler +WHC0_IRQHandler +RTC_IRQHandler +TAMPER_IRQHandler +WDT2_IRQHandler +WWDT2_IRQHandler +EINT0_IRQHandler +EINT1_IRQHandler +EINT2_IRQHandler +EINT3_IRQHandler +GPA_IRQHandler +GPB_IRQHandler +GPC_IRQHandler +GPD_IRQHandler +TMR2_IRQHandler +TMR3_IRQHandler +BRAKE0_IRQHandler +EPWM0P0_IRQHandler +EPWM0P1_IRQHandler +EPWM0P2_IRQHandler +QEI0_IRQHandler +ECAP0_IRQHandler +QSPI1_IRQHandler +UART1_IRQHandler +UART2_IRQHandler +UART3_IRQHandler +UART4_IRQHandler +UART5_IRQHandler +EADC00_IRQHandler +EADC01_IRQHandler +EADC02_IRQHandler +EADC03_IRQHandler +I2C1_IRQHandler +I2S0_IRQHandler +CANFD00_IRQHandler +SC0_IRQHandler +GPE_IRQHandler +GPF_IRQHandler +GPG_IRQHandler +GPH_IRQHandler +GPI_IRQHandler +GPJ_IRQHandler +TMR4_IRQHandler +TMR5_IRQHandler +TMR6_IRQHandler +TMR7_IRQHandler +BRAKE1_IRQHandler +EPWM1P0_IRQHandler +EPWM1P1_IRQHandler +EPWM1P2_IRQHandler +QEI1_IRQHandler +ECAP1_IRQHandler +SPI0_IRQHandler +SPI1_IRQHandler +PDMA2_IRQHandler +PDMA3_IRQHandler +UART6_IRQHandler +UART7_IRQHandler +UART8_IRQHandler +UART9_IRQHandler +UART10_IRQHandler +UART11_IRQHandler +I2C2_IRQHandler +I2C3_IRQHandler +I2S1_IRQHandler +CANFD10_IRQHandler +SC1_IRQHandler +GPK_IRQHandler +GPL_IRQHandler +GPM_IRQHandler +GPN_IRQHandler +TMR8_IRQHandler +TMR9_IRQHandler +TMR10_IRQHandler +TMR11_IRQHandler +BRAKE2_IRQHandler +EPWM2P0_IRQHandle +EPWM2P1_IRQHandle +EPWM2P2_IRQHandle +QEI2_IRQHandler +ECAP2_IRQHandler +SPI2_IRQHandler +SPI3_IRQHandler +UART12_IRQHandler +UART13_IRQHandler +UART14_IRQHandler +UART15_IRQHandler +UART16_IRQHandler +I2C4_IRQHandler +I2C5_IRQHandler +CANFD20_IRQHandler +CANFD30_IRQHandler +KPI_IRQHandler +CANFD01_IRQHandler +CANFD11_IRQHandler +CANFD21_IRQHandler +CANFD31_IRQHandler +ADC0_IRQHandler + B . + ENDP + + + ALIGN + + +; User Initial Stack & Heap + + IF :DEF:__MICROLIB + + EXPORT __initial_sp + EXPORT __heap_base + EXPORT __heap_limit + + ELSE + + IMPORT __use_two_region_memory + EXPORT __user_initial_stackheap + +__user_initial_stackheap PROC + LDR R0, = Heap_Mem + LDR R1, =(Stack_Mem + Stack_Size) + LDR R2, = (Heap_Mem + Heap_Size) + LDR R3, = Stack_Mem + BX LR + ENDP + + ALIGN + + ENDIF + + + END + diff --git a/bsp/nuvoton/libraries/ma35/Device/Nuvoton/MA35D1/Source/GCC/startup_ma35d1_subm.S b/bsp/nuvoton/libraries/ma35/Device/Nuvoton/MA35D1/Source/GCC/startup_ma35d1_subm.S new file mode 100644 index 0000000000..c6fdf676f3 --- /dev/null +++ b/bsp/nuvoton/libraries/ma35/Device/Nuvoton/MA35D1/Source/GCC/startup_ma35d1_subm.S @@ -0,0 +1,352 @@ +/****************************************************************************//** + * @file startup_ma35d1_subm.S + * @brief CMSIS Cortex-M4 Core Device Startup File + * + * SPDX-License-Identifier: Apache-2.0 + * @copyright (C) 2020 Nuvoton Technology Corp. All rights reserved. + *****************************************************************************/ + .syntax unified + .cpu cortex-m4 + .thumb + +.global g_pfnVectors +.global Default_Handler + +/* start address for the initialization values of the .data section. +defined in linker script */ +.word _sidata +/* start address for the .data section. defined in linker script */ +.word _sdata +/* end address for the .data section. defined in linker script */ +.word _edata +/* start address for the .bss section. defined in linker script */ +.word _sbss +/* end address for the .bss section. defined in linker script */ +.word _ebss + +/** + * @brief This is the code that gets called when the processor first + * starts execution following a reset event. Only the absolutely + * necessary set is performed, after which the application + * supplied main() routine is called. + * @param None + * @retval : None +*/ + + .section .text.Reset_Handler + .weak Reset_Handler + .type Reset_Handler, %function +Reset_Handler: + +#ifndef __NO_SYSTEM_INIT + bl SystemInit +#endif + +/* Copy the data segment initializers from flash to SRAM */ + movs r1, #0 + b LoopCopyDataInit + +CopyDataInit: + ldr r3, =_sidata + ldr r3, [r3, r1] + str r3, [r0, r1] + adds r1, r1, #4 + +LoopCopyDataInit: + ldr r0, =_sdata + ldr r3, =_edata + adds r2, r0, r1 + cmp r2, r3 + bcc CopyDataInit + ldr r2, =_sbss + b LoopFillZerobss +/* Zero fill the bss segment. */ +FillZerobss: + movs r3, #0 + str r3, [r2], #4 + +LoopFillZerobss: + ldr r3, = _ebss + cmp r2, r3 + bcc FillZerobss + +/* Call the application's entry point.*/ + bl entry + bx lr +.size Reset_Handler, .-Reset_Handler + +/** + * @brief This is the code that gets called when the processor receives an + * unexpected interrupt. This simply enters an infinite loop, preserving + * the system state for examination by a debugger. + * @param None + * @retval None +*/ + .section .text.Default_Handler,"ax",%progbits +Default_Handler: +Infinite_Loop: + b Infinite_Loop + .size Default_Handler, .-Default_Handler +/****************************************************************************** +* +* The minimal vector table for a Cortex M4. Note that the proper constructs +* must be placed on this to ensure that it ends up at physical address +* 0x0000.0000. +* +******************************************************************************/ + .section .isr_vector,"a",%progbits + .type g_pfnVectors, %object + .size g_pfnVectors, .-g_pfnVectors + +g_pfnVectors: + .word _estack /* Top of Stack */ + .word Reset_Handler /* Reset Handler */ + .word NMI_Handler /* NMI Handler */ + .word HardFault_Handler /* Hard Fault Handler */ + .word MemManage_Handler /* MPU Fault Handler */ + .word BusFault_Handler /* Bus Fault Handler */ + .word UsageFault_Handler /* Usage Fault Handler */ + .word 0 /* Reserved */ + .word 0 /* Reserved */ + .word 0 /* Reserved */ + .word 0 /* Reserved */ + .word SVC_Handler /* SVCall Handler */ + .word DebugMon_Handler /* Debug Monitor Handler */ + .word 0 /* Reserved */ + .word PendSV_Handler /* PendSV Handler */ + .word SysTick_Handler /* SysTick Handler */ + + /* External interrupts */ + .word LVD_IRQHandler /* 0 */ + .word 0 /* 1 */ + .word PWRWU_IRQHandler /* 2 */ + .word HWSEM0_IRQHandler /* 3 */ + .word CKFAIL_IRQHandler /* 4 */ + .word WHC0_IRQHandler /* 5 */ + .word RTC_IRQHandler /* 6 */ + .word TAMPER_IRQHandler /* 7 */ + .word WDT2_IRQHandler /* 8 */ + .word WWDT2_IRQHandler /* 9 */ + .word EINT0_IRQHandler /* 10 */ + .word EINT1_IRQHandler /* 11 */ + .word EINT2_IRQHandler /* 12 */ + .word EINT3_IRQHandler /* 13 */ + .word 0 /* 14 */ + .word 0 /* 15 */ + .word GPA_IRQHandler /* 16 */ + .word GPB_IRQHandler /* 17 */ + .word GPC_IRQHandler /* 18 */ + .word GPD_IRQHandler /* 19 */ + .word 0 /* 20 */ + .word 0 /* 21 */ + .word TMR2_IRQHandler /* 22 */ + .word TMR3_IRQHandler /* 23 */ + .word BRAKE0_IRQHandler /* 24 */ + .word EPWM0P0_IRQHandler /* 25 */ + .word EPWM0P1_IRQHandler /* 26 */ + .word EPWM0P2_IRQHandler /* 27 */ + .word QEI0_IRQHandler /* 28 */ + .word ECAP0_IRQHandler /* 29 */ + .word 0 /* 30 */ + .word QSPI1_IRQHandler /* 31 */ + .word 0 /* 32 */ + .word 0 /* 33 */ + .word 0 /* 34 */ + .word UART1_IRQHandler /* 35 */ + .word UART2_IRQHandler /* 36 */ + .word UART3_IRQHandler /* 37 */ + .word UART4_IRQHandler /* 38 */ + .word UART5_IRQHandler /* 39 */ + .word EADC00_IRQHandler /* 40 */ + .word EADC01_IRQHandler /* 41 */ + .word EADC02_IRQHandler /* 42 */ + .word EADC03_IRQHandler /* 43 */ + .word 0 /* 44 */ + .word I2C1_IRQHandler /* 45 */ + .word I2S0_IRQHandler /* 46 */ + .word MCAN00_IRQHandler /* 47 */ + .word SC0_IRQHandler /* 48 */ + .word GPE_IRQHandler /* 49 */ + .word GPF_IRQHandler /* 50 */ + .word GPG_IRQHandler /* 51 */ + .word GPH_IRQHandler /* 52 */ + .word GPI_IRQHandler /* 53 */ + .word GPJ_IRQHandler /* 54 */ + .word TMR4_IRQHandler /* 55 */ + .word TMR5_IRQHandler /* 56 */ + .word TMR6_IRQHandler /* 57 */ + .word TMR7_IRQHandler /* 58 */ + .word BRAKE1_IRQHandler /* 59 */ + .word EPWM1P0_IRQHandler /* 60 */ + .word EPWM1P1_IRQHandler /* 61 */ + .word EPWM1P2_IRQHandler /* 62 */ + .word QEI1_IRQHandler /* 63 */ + .word ECAP1_IRQHandler /* 64 */ + .word SPI0_IRQHandler /* 65 */ + .word SPI1_IRQHandler /* 66 */ + .word PDMA2_IRQHandler /* 67 */ + .word PDMA3_IRQHandler /* 68 */ + .word UART6_IRQHandler /* 69 */ + .word UART7_IRQHandler /* 70 */ + .word UART8_IRQHandler /* 71 */ + .word UART9_IRQHandler /* 72 */ + .word UART10_IRQHandler /* 73 */ + .word UART11_IRQHandler /* 74 */ + .word I2C2_IRQHandler /* 75 */ + .word I2C3_IRQHandler /* 76 */ + .word I2S1_IRQHandler /* 77 */ + .word MACN10_IRQHandler /* 78 */ + .word SC1_IRQHandler /* 79 */ + .word GPK_IRQHandler /* 80 */ + .word GPL_IRQHandler /* 81 */ + .word GPM_IRQHandler /* 82 */ + .word GPN_IRQHandler /* 83 */ + .word TMR8_IRQHandler /* 84 */ + .word TMR9_IRQHandler /* 85 */ + .word TMR10_IRQHandler /* 86 */ + .word TMR11_IRQHandler /* 87 */ + .word BRAKE2_IRQHandler /* 88 */ + .word EPWM2P0_IRQHandler /* 89 */ + .word EPWM2P1_IRQHandler /* 90 */ + .word EPWM2P2_IRQHandler /* 91 */ + .word QEI2_IRQHandler /* 92 */ + .word ECAP2_IRQHandler /* 93 */ + .word SPI2_IRQHandler /* 94 */ + .word SPI3_IRQHandler /* 95 */ + .word UART12_IRQHandler /* 96 */ + .word UART13_IRQHandler /* 97 */ + .word UART14_IRQHandler /* 98 */ + .word UART15_IRQHandler /* 99 */ + .word UART16_IRQHandler /* 100 */ + .word I2C4_IRQHandler /* 101 */ + .word I2C5_IRQHandler /* 102 */ + .word MCAN20_IRQHandler /* 103 */ + .word MCAN30_IRQHandler /* 104 */ + .word KPI_IRQHandler /* 105 */ + .word MCAN01_IRQHandler /* 106 */ + .word MCAN11_IRQHandler /* 107 */ + .word MCAN21_IRQHandler /* 108 */ + .word MCAN31_IRQHandler /* 109 */ + .word ADC0_IRQHandler /* 110 */ + + +/* Macro to define default handlers. Default handler + * will be weak symbol and just dead loops. They can be + * overwritten by other handlers */ + .macro def_irq_handler handler_name + .weak \handler_name + .set \handler_name, Default_Handler + .endm + + def_irq_handler NMI_Handler + def_irq_handler HardFault_Handler + def_irq_handler MemManage_Handler + def_irq_handler BusFault_Handler + def_irq_handler UsageFault_Handler + def_irq_handler SVC_Handler + def_irq_handler DebugMon_Handler + def_irq_handler PendSV_Handler + def_irq_handler SysTick_Handler + + def_irq_handler LVD_IRQHandler + def_irq_handler PWRWU_IRQHandler + def_irq_handler HWSEM0_IRQHandler + def_irq_handler CKFAIL_IRQHandler + def_irq_handler WHC0_IRQHandler + def_irq_handler RTC_IRQHandler + def_irq_handler TAMPER_IRQHandler + def_irq_handler WDT2_IRQHandler + def_irq_handler WWDT2_IRQHandler + def_irq_handler EINT0_IRQHandler + def_irq_handler EINT1_IRQHandler + def_irq_handler EINT2_IRQHandler + def_irq_handler EINT3_IRQHandler + def_irq_handler GPA_IRQHandler + def_irq_handler GPB_IRQHandler + def_irq_handler GPC_IRQHandler + def_irq_handler GPD_IRQHandler + def_irq_handler TMR2_IRQHandler + def_irq_handler TMR3_IRQHandler + def_irq_handler BRAKE0_IRQHandler + def_irq_handler EPWM0P0_IRQHandler + def_irq_handler EPWM0P1_IRQHandler + def_irq_handler EPWM0P2_IRQHandler + def_irq_handler QEI0_IRQHandler + def_irq_handler ECAP0_IRQHandler + def_irq_handler QSPI1_IRQHandler + def_irq_handler UART1_IRQHandler + def_irq_handler UART2_IRQHandler + def_irq_handler UART3_IRQHandler + def_irq_handler UART4_IRQHandler + def_irq_handler UART5_IRQHandler + def_irq_handler EADC00_IRQHandler + def_irq_handler EADC01_IRQHandler + def_irq_handler EADC02_IRQHandler + def_irq_handler EADC03_IRQHandler + def_irq_handler I2C1_IRQHandler + def_irq_handler I2S0_IRQHandler + def_irq_handler MCAN00_IRQHandler + def_irq_handler SC0_IRQHandler + def_irq_handler GPE_IRQHandler + def_irq_handler GPF_IRQHandler + def_irq_handler GPG_IRQHandler + def_irq_handler GPH_IRQHandler + def_irq_handler GPI_IRQHandler + def_irq_handler GPJ_IRQHandler + def_irq_handler TMR4_IRQHandler + def_irq_handler TMR5_IRQHandler + def_irq_handler TMR6_IRQHandler + def_irq_handler TMR7_IRQHandler + def_irq_handler BRAKE1_IRQHandler + def_irq_handler EPWM1P0_IRQHandler + def_irq_handler EPWM1P1_IRQHandler + def_irq_handler EPWM1P2_IRQHandler + def_irq_handler QEI1_IRQHandler + def_irq_handler ECAP1_IRQHandler + def_irq_handler SPI0_IRQHandler + def_irq_handler SPI1_IRQHandler + def_irq_handler PDMA2_IRQHandler + def_irq_handler PDMA3_IRQHandler + def_irq_handler UART6_IRQHandler + def_irq_handler UART7_IRQHandler + def_irq_handler UART8_IRQHandler + def_irq_handler UART9_IRQHandler + def_irq_handler UART10_IRQHandler + def_irq_handler UART11_IRQHandler + def_irq_handler I2C2_IRQHandler + def_irq_handler I2C3_IRQHandler + def_irq_handler I2S1_IRQHandler + def_irq_handler MACN10_IRQHandler + def_irq_handler SC1_IRQHandler + def_irq_handler GPK_IRQHandler + def_irq_handler GPL_IRQHandler + def_irq_handler GPM_IRQHandler + def_irq_handler GPN_IRQHandler + def_irq_handler TMR8_IRQHandler + def_irq_handler TMR9_IRQHandler + def_irq_handler TMR10_IRQHandler + def_irq_handler TMR11_IRQHandler + def_irq_handler BRAKE2_IRQHandler + def_irq_handler EPWM2P0_IRQHandler + def_irq_handler EPWM2P1_IRQHandler + def_irq_handler EPWM2P2_IRQHandler + def_irq_handler QEI2_IRQHandler + def_irq_handler ECAP2_IRQHandler + def_irq_handler SPI2_IRQHandler + def_irq_handler SPI3_IRQHandler + def_irq_handler UART12_IRQHandler + def_irq_handler UART13_IRQHandler + def_irq_handler UART14_IRQHandler + def_irq_handler UART15_IRQHandler + def_irq_handler UART16_IRQHandler + def_irq_handler I2C4_IRQHandler + def_irq_handler I2C5_IRQHandler + def_irq_handler MCAN20_IRQHandler + def_irq_handler MCAN30_IRQHandler + def_irq_handler KPI_IRQHandler + def_irq_handler MCAN01_IRQHandler + def_irq_handler MCAN11_IRQHandler + def_irq_handler MCAN21_IRQHandler + def_irq_handler MCAN31_IRQHandler + def_irq_handler ADC0_IRQHandler + .end diff --git a/bsp/nuvoton/libraries/ma35/Device/Nuvoton/MA35D1/Source/IAR/startup_ma35d1_subm.s b/bsp/nuvoton/libraries/ma35/Device/Nuvoton/MA35D1/Source/IAR/startup_ma35d1_subm.s new file mode 100644 index 0000000000..486e6fa384 --- /dev/null +++ b/bsp/nuvoton/libraries/ma35/Device/Nuvoton/MA35D1/Source/IAR/startup_ma35d1_subm.s @@ -0,0 +1,430 @@ +;/****************************************************************************** +; * @file startup_subm.s +; * @brief CMSIS Cortex-M4 Core Device Startup File +; * +; * SPDX-License-Identifier: Apache-2.0 +; * @copyright (C) 2020 Nuvoton Technology Corp. All rights reserved. +;*****************************************************************************/ + + MODULE ?cstartup + + ;; Forward declaration of sections. + SECTION CSTACK:DATA:NOROOT(3) + + SECTION .intvec:CODE:NOROOT(2) + + EXTERN __iar_program_start + EXTERN HardFault_Handler + EXTERN SystemInit + PUBLIC __vector_table + PUBLIC __vector_table_0x1c + PUBLIC __Vectors + PUBLIC __Vectors_End + PUBLIC __Vectors_Size + + DATA + +__vector_table + DCD sfe(CSTACK) + DCD Reset_Handler + + DCD NMI_Handler + DCD HardFault_Handler + DCD MemManage_Handler + DCD BusFault_Handler + DCD UsageFault_Handler +__vector_table_0x1c + DCD 0 + DCD 0 + DCD 0 + DCD 0 + DCD SVC_Handler + DCD DebugMon_Handler + DCD 0 + DCD PendSV_Handler + DCD SysTick_Handler + + ; External Interrupts + DCD LVD_IRQHandler ; 0 + DCD Default_Handler ; 1 + DCD PWRWU_IRQHandler ; 2 + DCD HWSEM0_IRQHandler ; 3 + DCD CKFAIL_IRQHandler ; 4 + DCD WHC0_IRQHandler ; 5 + DCD RTC_IRQHandler ; 6 + DCD TAMPER_IRQHandler ; 7 + DCD WDT2_IRQHandler ; 8 + DCD WWDT2_IRQHandler ; 9 + DCD EINT0_IRQHandler ; 10 + DCD EINT1_IRQHandler ; 11 + DCD EINT2_IRQHandler ; 12 + DCD EINT3_IRQHandler ; 13 + DCD Default_Handler ; 14 + DCD Default_Handler ; 15 + DCD GPA_IRQHandler ; 16 + DCD GPB_IRQHandler ; 17 + DCD GPC_IRQHandler ; 18 + DCD GPD_IRQHandler ; 19 + DCD Default_Handler ; 20 + DCD Default_Handler ; 21 + DCD TMR2_IRQHandler ; 22 + DCD TMR3_IRQHandler ; 23 + DCD BRAKE0_IRQHandler ; 24 + DCD EPWM0P0_IRQHandler ; 25 + DCD EPWM0P1_IRQHandler ; 26 + DCD EPWM0P2_IRQHandler ; 27 + DCD QEI0_IRQHandler ; 28 + DCD ECAP0_IRQHandler ; 29 + DCD Default_Handler ; 30 + DCD QSPI1_IRQHandler ; 31 + DCD Default_Handler ; 32 + DCD Default_Handler ; 33 + DCD Default_Handler ; 34 + DCD UART1_IRQHandler ; 35 + DCD UART2_IRQHandler ; 36 + DCD UART3_IRQHandler ; 37 + DCD UART4_IRQHandler ; 38 + DCD UART5_IRQHandler ; 39 + DCD EADC00_IRQHandler ; 40 + DCD EADC01_IRQHandler ; 41 + DCD EADC02_IRQHandler ; 42 + DCD EADC03_IRQHandler ; 43 + DCD Default_Handler ; 44 + DCD I2C1_IRQHandler ; 45 + DCD I2S0_IRQHandler ; 46 + DCD MCAN00_IRQHandler ; 47 + DCD SC0_IRQHandler ; 48 + DCD GPE_IRQHandler ; 49 + DCD GPF_IRQHandler ; 50 + DCD GPG_IRQHandler ; 51 + DCD GPH_IRQHandler ; 52 + DCD GPI_IRQHandler ; 53 + DCD GPJ_IRQHandler ; 54 + DCD TMR4_IRQHandler ; 55 + DCD TMR5_IRQHandler ; 56 + DCD TMR6_IRQHandler ; 57 + DCD TMR7_IRQHandler ; 58 + DCD BRAKE1_IRQHandler ; 59 + DCD EPWM1P0_IRQHandler ; 60 + DCD EPWM1P1_IRQHandler ; 61 + DCD EPWM1P2_IRQHandler ; 62 + DCD QEI1_IRQHandler ; 63 + DCD ECAP1_IRQHandler ; 64 + DCD SPI0_IRQHandler ; 65 + DCD SPI1_IRQHandler ; 66 + DCD PDMA2_IRQHandler ; 67 + DCD PDMA3_IRQHandler ; 68 + DCD UART6_IRQHandler ; 69 + DCD UART7_IRQHandler ; 70 + DCD UART8_IRQHandler ; 71 + DCD UART9_IRQHandler ; 72 + DCD UART10_IRQHandler ; 73 + DCD UART11_IRQHandler ; 74 + DCD I2C2_IRQHandler ; 75 + DCD I2C3_IRQHandler ; 76 + DCD I2S1_IRQHandler ; 77 + DCD MACN10_IRQHandler ; 78 + DCD SC1_IRQHandler ; 79 + DCD GPK_IRQHandler ; 80 + DCD GPL_IRQHandler ; 81 + DCD GPM_IRQHandler ; 82 + DCD GPN_IRQHandler ; 83 + DCD TMR8_IRQHandler ; 84 + DCD TMR9_IRQHandler ; 85 + DCD TMR10_IRQHandler ; 86 + DCD TMR11_IRQHandler ; 87 + DCD BRAKE2_IRQHandler ; 88 + DCD EPWM2P0_IRQHandle ; 89 + DCD EPWM2P1_IRQHandle ; 90 + DCD EPWM2P2_IRQHandle ; 91 + DCD QEI2_IRQHandler ; 92 + DCD ECAP2_IRQHandler ; 93 + DCD SPI2_IRQHandler ; 94 + DCD SPI3_IRQHandler ; 95 + DCD UART12_IRQHandler ; 96 + DCD UART13_IRQHandler ; 97 + DCD UART14_IRQHandler ; 98 + DCD UART15_IRQHandler ; 99 + DCD UART16_IRQHandler ; 100 + DCD I2C4_IRQHandler ; 101 + DCD I2C5_IRQHandler ; 102 + DCD MCAN20_IRQHandler ; 103 + DCD MCAN30_IRQHandler ; 104 + DCD KPI_IRQHandler ; 105 + DCD MCAN01_IRQHandler ; 106 + DCD MCAN11_IRQHandler ; 107 + DCD MCAN21_IRQHandler ; 108 + DCD MCAN31_IRQHandler ; 109 + DCD ADC0_IRQHandler ; 110 +__Vectors_End + +__Vectors EQU __vector_table +__Vectors_Size EQU __Vectors_End - __Vectors + + +;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; +;; +;; Default interrupt handlers. +;; + THUMB + + PUBWEAK Reset_Handler + SECTION .text:CODE:REORDER:NOROOT(2) +Reset_Handler + + LDR R0, =SystemInit + BLX R0 + + LDR R0, =__iar_program_start + BX R0 + + PUBWEAK NMI_Handler + SECTION .text:CODE:REORDER:NOROOT(1) +NMI_Handler + B NMI_Handler + + PUBWEAK MemManage_Handler + SECTION .text:CODE:REORDER:NOROOT(1) +MemManage_Handler + B MemManage_Handler + + PUBWEAK BusFault_Handler + SECTION .text:CODE:REORDER:NOROOT(1) +BusFault_Handler + B BusFault_Handler + + PUBWEAK UsageFault_Handler + SECTION .text:CODE:REORDER:NOROOT(1) +UsageFault_Handler + B UsageFault_Handler + + PUBWEAK SVC_Handler + SECTION .text:CODE:REORDER:NOROOT(1) +SVC_Handler + B SVC_Handler + + PUBWEAK DebugMon_Handler + SECTION .text:CODE:REORDER:NOROOT(1) +DebugMon_Handler + B DebugMon_Handler + + PUBWEAK PendSV_Handler + SECTION .text:CODE:REORDER:NOROOT(1) +PendSV_Handler + B PendSV_Handler + + PUBWEAK SysTick_Handler + SECTION .text:CODE:REORDER:NOROOT(1) +SysTick_Handler + B SysTick_Handler + + PUBWEAK LVD_IRQHandler + PUBWEAK PWRWU_IRQHandler + PUBWEAK HWSEM0_IRQHandler + PUBWEAK CKFAIL_IRQHandler + PUBWEAK WHC0_IRQHandler + PUBWEAK RTC_IRQHandler + PUBWEAK TAMPER_IRQHandler + PUBWEAK WDT2_IRQHandler + PUBWEAK WWDT2_IRQHandler + PUBWEAK EINT0_IRQHandler + PUBWEAK EINT1_IRQHandler + PUBWEAK EINT2_IRQHandler + PUBWEAK EINT3_IRQHandler + PUBWEAK GPA_IRQHandler + PUBWEAK GPB_IRQHandler + PUBWEAK GPC_IRQHandler + PUBWEAK GPD_IRQHandler + PUBWEAK TMR2_IRQHandler + PUBWEAK TMR3_IRQHandler + PUBWEAK BRAKE0_IRQHandler + PUBWEAK EPWM0P0_IRQHandler + PUBWEAK EPWM0P1_IRQHandler + PUBWEAK EPWM0P2_IRQHandler + PUBWEAK QEI0_IRQHandler + PUBWEAK ECAP0_IRQHandler + PUBWEAK QSPI1_IRQHandler + PUBWEAK UART1_IRQHandler + PUBWEAK UART2_IRQHandler + PUBWEAK UART3_IRQHandler + PUBWEAK UART4_IRQHandler + PUBWEAK UART5_IRQHandler + PUBWEAK EADC00_IRQHandler + PUBWEAK EADC01_IRQHandler + PUBWEAK EADC02_IRQHandler + PUBWEAK EADC03_IRQHandler + PUBWEAK I2C1_IRQHandler + PUBWEAK I2S0_IRQHandler + PUBWEAK MCAN00_IRQHandler + PUBWEAK SC0_IRQHandler + PUBWEAK GPE_IRQHandler + PUBWEAK GPF_IRQHandler + PUBWEAK GPG_IRQHandler + PUBWEAK GPH_IRQHandler + PUBWEAK GPI_IRQHandler + PUBWEAK GPJ_IRQHandler + PUBWEAK TMR4_IRQHandler + PUBWEAK TMR5_IRQHandler + PUBWEAK TMR6_IRQHandler + PUBWEAK TMR7_IRQHandler + PUBWEAK BRAKE1_IRQHandler + PUBWEAK EPWM1P0_IRQHandler + PUBWEAK EPWM1P1_IRQHandler + PUBWEAK EPWM1P2_IRQHandler + PUBWEAK QEI1_IRQHandler + PUBWEAK ECAP1_IRQHandler + PUBWEAK SPI0_IRQHandler + PUBWEAK SPI1_IRQHandler + PUBWEAK PDMA2_IRQHandler + PUBWEAK PDMA3_IRQHandler + PUBWEAK UART6_IRQHandler + PUBWEAK UART7_IRQHandler + PUBWEAK UART8_IRQHandler + PUBWEAK UART9_IRQHandler + PUBWEAK UART10_IRQHandler + PUBWEAK UART11_IRQHandler + PUBWEAK I2C2_IRQHandler + PUBWEAK I2C3_IRQHandler + PUBWEAK I2S1_IRQHandler + PUBWEAK MACN10_IRQHandler + PUBWEAK SC1_IRQHandler + PUBWEAK GPK_IRQHandler + PUBWEAK GPL_IRQHandler + PUBWEAK GPM_IRQHandler + PUBWEAK GPN_IRQHandler + PUBWEAK TMR8_IRQHandler + PUBWEAK TMR9_IRQHandler + PUBWEAK TMR10_IRQHandler + PUBWEAK TMR11_IRQHandler + PUBWEAK BRAKE2_IRQHandler + PUBWEAK EPWM2P0_IRQHandle + PUBWEAK EPWM2P1_IRQHandle + PUBWEAK EPWM2P2_IRQHandle + PUBWEAK QEI2_IRQHandler + PUBWEAK ECAP2_IRQHandler + PUBWEAK SPI2_IRQHandler + PUBWEAK SPI3_IRQHandler + PUBWEAK UART12_IRQHandler + PUBWEAK UART13_IRQHandler + PUBWEAK UART14_IRQHandler + PUBWEAK UART15_IRQHandler + PUBWEAK UART16_IRQHandler + PUBWEAK I2C4_IRQHandler + PUBWEAK I2C5_IRQHandler + PUBWEAK MCAN20_IRQHandler + PUBWEAK MCAN30_IRQHandler + PUBWEAK KPI_IRQHandler + PUBWEAK MCAN01_IRQHandler + PUBWEAK MCAN11_IRQHandler + PUBWEAK MCAN21_IRQHandler + PUBWEAK MCAN31_IRQHandler + PUBWEAK ADC0_IRQHandler + + SECTION .text:CODE:REORDER:NOROOT(1) + +LVD_IRQHandler +PWRWU_IRQHandler +HWSEM0_IRQHandler +CKFAIL_IRQHandler +WHC0_IRQHandler +RTC_IRQHandler +TAMPER_IRQHandler +WDT2_IRQHandler +WWDT2_IRQHandler +EINT0_IRQHandler +EINT1_IRQHandler +EINT2_IRQHandler +EINT3_IRQHandler +GPA_IRQHandler +GPB_IRQHandler +GPC_IRQHandler +GPD_IRQHandler +TMR2_IRQHandler +TMR3_IRQHandler +BRAKE0_IRQHandler +EPWM0P0_IRQHandler +EPWM0P1_IRQHandler +EPWM0P2_IRQHandler +QEI0_IRQHandler +ECAP0_IRQHandler +QSPI1_IRQHandler +UART1_IRQHandler +UART2_IRQHandler +UART3_IRQHandler +UART4_IRQHandler +UART5_IRQHandler +EADC00_IRQHandler +EADC01_IRQHandler +EADC02_IRQHandler +EADC03_IRQHandler +I2C1_IRQHandler +I2S0_IRQHandler +MCAN00_IRQHandler +SC0_IRQHandler +GPE_IRQHandler +GPF_IRQHandler +GPG_IRQHandler +GPH_IRQHandler +GPI_IRQHandler +GPJ_IRQHandler +TMR4_IRQHandler +TMR5_IRQHandler +TMR6_IRQHandler +TMR7_IRQHandler +BRAKE1_IRQHandler +EPWM1P0_IRQHandler +EPWM1P1_IRQHandler +EPWM1P2_IRQHandler +QEI1_IRQHandler +ECAP1_IRQHandler +SPI0_IRQHandler +SPI1_IRQHandler +PDMA2_IRQHandler +PDMA3_IRQHandler +UART6_IRQHandler +UART7_IRQHandler +UART8_IRQHandler +UART9_IRQHandler +UART10_IRQHandler +UART11_IRQHandler +I2C2_IRQHandler +I2C3_IRQHandler +I2S1_IRQHandler +MACN10_IRQHandler +SC1_IRQHandler +GPK_IRQHandler +GPL_IRQHandler +GPM_IRQHandler +GPN_IRQHandler +TMR8_IRQHandler +TMR9_IRQHandler +TMR10_IRQHandler +TMR11_IRQHandler +BRAKE2_IRQHandler +EPWM2P0_IRQHandle +EPWM2P1_IRQHandle +EPWM2P2_IRQHandle +QEI2_IRQHandler +ECAP2_IRQHandler +SPI2_IRQHandler +SPI3_IRQHandler +UART12_IRQHandler +UART13_IRQHandler +UART14_IRQHandler +UART15_IRQHandler +UART16_IRQHandler +I2C4_IRQHandler +I2C5_IRQHandler +MCAN20_IRQHandler +MCAN30_IRQHandler +KPI_IRQHandler +MCAN01_IRQHandler +MCAN11_IRQHandler +MCAN21_IRQHandler +MCAN31_IRQHandler +ADC0_IRQHandler +Default_Handler + B Default_Handler + + END + diff --git a/bsp/nuvoton/libraries/ma35/Device/Nuvoton/MA35D1/Source/system_ma35d1_subm.c b/bsp/nuvoton/libraries/ma35/Device/Nuvoton/MA35D1/Source/system_ma35d1_subm.c new file mode 100644 index 0000000000..1e27bee553 --- /dev/null +++ b/bsp/nuvoton/libraries/ma35/Device/Nuvoton/MA35D1/Source/system_ma35d1_subm.c @@ -0,0 +1,67 @@ +/**************************************************************************//** + * @file startup_subm.c + * @brief CMSIS Cortex-M4 Core Peripheral Access Layer Source File + * + * SPDX-License-Identifier: Apache-2.0 + * @copyright (C) 2020 Nuvoton Technology Corp. All rights reserved. + *****************************************************************************/ + +#include "NuMicro.h" + + +/*---------------------------------------------------------------------------- + DEFINES + *----------------------------------------------------------------------------*/ + + +/*---------------------------------------------------------------------------- + Clock Variable definitions + *----------------------------------------------------------------------------*/ +uint32_t SystemCoreClock = __SYSTEM_CLOCK; /*!< System Clock Frequency (Core Clock)*/ +uint32_t CyclesPerUs = (__HSI / 1000000UL); /* Cycles per micro second */ + + +/*---------------------------------------------------------------------------- + Clock functions + *----------------------------------------------------------------------------*/ +void SystemCoreClockUpdate(void) /* Get Core Clock Frequency */ +{ + + /* Update System Core Clock */ + SystemCoreClock = 180000000; + CyclesPerUs = (SystemCoreClock + 500000UL) / 1000000UL; + +} + +/** + * @brief Set PF.2 and PF.3 to input mode + * @param None + * @return None + * @details GPIO default state could be configured as input or quasi through user config. + * To use HXT, PF.2 and PF.3 must not set as quasi mode. This function changes + * PF.2 and PF.3 to input mode no matter which mode they are working at. + */ + + +/** + * @brief Initialize the System + * + * @param none + * @return none + */ +void SystemInit(void) +{ + /* Add your system initialize code here. + Do not use global variables because this function is called before + reaching pre-main. RW section maybe overwritten afterwards. */ + + + /* FPU settings ------------------------------------------------------------*/ +#if (__FPU_PRESENT == 1U) && (__FPU_USED == 1U) + SCB->CPACR |= ((3UL << 10 * 2) | /* set CP10 Full Access */ + (3UL << 11 * 2)); /* set CP11 Full Access */ +#endif + + +} + diff --git a/bsp/nuvoton/libraries/ma35/Device/SConscript b/bsp/nuvoton/libraries/ma35/Device/SConscript new file mode 100644 index 0000000000..dadef0e3b0 --- /dev/null +++ b/bsp/nuvoton/libraries/ma35/Device/SConscript @@ -0,0 +1,22 @@ +import rtconfig +Import('RTT_ROOT') +from building import * + +# get current directory +cwd = GetCurrentDir() +src = [] + +if GetDepend('USE_MA35D1_SUBM'): + src += ['Nuvoton/MA35D1/Source/system_ma35d1_subm.c'] + if rtconfig.CROSS_TOOL == 'gcc': + src = src + ['Nuvoton/MA35D1/Source/GCC/startup_ma35d1_subm.S'] + elif rtconfig.CROSS_TOOL == 'keil': + src = src + ['Nuvoton/MA35D1/Source/ARM/startup_ma35d1_subm.s'] + elif rtconfig.CROSS_TOOL == 'iar': + src = src + ['Nuvoton/MA35D1/Source/IAR/startup_ma35d1_subm.s'] + +path = [cwd + '/Nuvoton/MA35D1/Include',] + +group = DefineGroup('Drivers', src, depend = [''], CPPPATH = path) + +Return('group') diff --git a/bsp/nuvoton/libraries/ma35/README.md b/bsp/nuvoton/libraries/ma35/README.md new file mode 100644 index 0000000000..2d80b4c86b --- /dev/null +++ b/bsp/nuvoton/libraries/ma35/README.md @@ -0,0 +1,38 @@ +# MA35 Series + +## MA35D1 Series Supported drivers + +| Peripheral | rt_device_class_type | Device name | +| ------ | ---- | :------: | +| ADC_TOUCH | RT_Device_Class_Touch | ***adc_touch*** | +| CANFD | RT_Device_Class_CAN | ***canfd[0-3]*** | +| CCAP | RT_Device_Class_Miscellaneous | ***ccap[0-1]*** | +| DISP | RT_Device_Class_Grapnis () | ***dac[0-1]*** | +| EADC | RT_Device_Class_Miscellaneous (ADC) | ***eadc[0-1]*** | +| ECAP | RT_Device_Class_Miscellaneous (Input capture) | ***ecap[0-1]i[0-2]*** | +| GMAC | RT_Device_Class_NetIf | ***e[0-1]*** | +| EPWM | RT_Device_Class_Miscellaneous (PWM) | ***epwm[0-1]*** | +| EPWM (Capture function) | RT_Device_Class_Miscellaneous (Input capture) | ***epwm[0-1]i[0-5]*** | +| GPIO | RT_Device_Class_Miscellaneous (Pin) | ***gpio*** | +| GPIO | RT_Device_Class_I2CBUS | ***softi2c0[0-1]*** | +| I2C | RT_Device_Class_I2CBUS | ***i2c[0-4]*** | +| I2S | RT_Device_Class_Sound/RT_Device_Class_Pipe | ***sound[0, 1]*** | +| PDMA | N/A | ***N/A*** | +| QEI | RT_Device_Class_Miscellaneous (Pulse encoder) | ***qei[0-1]*** | +| QSPI | RT_Device_Class_SPIBUS | ***qspi[0-1]*** | +| RTC | RT_Device_Class_RTC | ***rtc*** | +| RTP | N/A | N/A | +| SC (UART function) | RT_Device_Class_Char | ***scuart[0-2]*** | +| SDIO | RT_Device_Class_Sdio | ***sdio[0-1]*** | +| SPI | RT_Device_Class_SPIBUS | ***spi[0-10]*** | +| SPI (I2S function) | RT_Device_Class_Sound/RT_Device_Class_Pipe | ***spii2s[0-10]*** | +| TIMER | RT_Device_Class_Timer | ***timer[0-3]*** | +| TIMER (PWM function) | RT_Device_Class_Miscellaneous (PWM) | ***tpwm[0-3]*** | +| UART | RT_Device_Class_Char | ***uart[0-7]*** | +| USBH, HSUSBH | RT_Device_Class_USBHost | ***usbh*** | +| WDT | RT_Device_Class_Miscellaneous (Watchdog) | ***wdt*** | + +## Resources +* [Download MA35D1 TRM][1] + + [1]: diff --git a/bsp/nuvoton/libraries/ma35/SConscript b/bsp/nuvoton/libraries/ma35/SConscript new file mode 100644 index 0000000000..4c815c49b8 --- /dev/null +++ b/bsp/nuvoton/libraries/ma35/SConscript @@ -0,0 +1,15 @@ +# RT-Thread building script for bridge + +import os +from building import * + +cwd = GetCurrentDir() +objs = [] +list = os.listdir(cwd) + +for d in list: + path = os.path.join(cwd, d) + if os.path.isfile(os.path.join(path, 'SConscript')): + objs = objs + SConscript(os.path.join(d, 'SConscript')) + +Return('objs') diff --git a/bsp/nuvoton/libraries/ma35/StdDriver/SConscript b/bsp/nuvoton/libraries/ma35/StdDriver/SConscript new file mode 100644 index 0000000000..9431744b64 --- /dev/null +++ b/bsp/nuvoton/libraries/ma35/StdDriver/SConscript @@ -0,0 +1,13 @@ +# RT-Thread building script for component +Import('rtconfig') +from building import * + +cwd = GetCurrentDir() +libs = [] +src = Glob('*src/*.c') + Glob('src/*.cpp') +cpppath = [cwd + '/inc'] +libpath = [cwd + '/lib'] + +group = DefineGroup('Libraries', src, depend = [''], CPPPATH = cpppath) + +Return('group') diff --git a/bsp/nuvoton/libraries/ma35/StdDriver/inc/nu_adc.h b/bsp/nuvoton/libraries/ma35/StdDriver/inc/nu_adc.h new file mode 100644 index 0000000000..7d57468d13 --- /dev/null +++ b/bsp/nuvoton/libraries/ma35/StdDriver/inc/nu_adc.h @@ -0,0 +1,287 @@ +/**************************************************************************//** + * @file nu_adc.h + * @brief ADC driver header file + * + * SPDX-License-Identifier: Apache-2.0 + * @copyright(C) 2020 Nuvoton Technology Corp. All rights reserved. + *****************************************************************************/ +#ifndef __NU_ADC_H__ +#define __NU_ADC_H__ + +#ifdef __cplusplus +extern "C" +{ +#endif + + +/** @addtogroup Standard_Driver Standard Driver + @{ +*/ + +/** @addtogroup ADC_Driver ADC Driver + @{ +*/ + +/** @addtogroup ADC_EXPORTED_CONSTANTS ADC Exported Constants + @{ +*/ + +#include "adc_reg.h" + +#define ADC_CH_0_MASK (1UL << 0) /*!< ADC channel 0 mask \hideinitializer */ +#define ADC_CH_1_MASK (1UL << 1) /*!< ADC channel 1 mask \hideinitializer */ +#define ADC_CH_2_MASK (1UL << 2) /*!< ADC channel 2 mask \hideinitializer */ +#define ADC_CH_3_MASK (1UL << 3) /*!< ADC channel 3 mask \hideinitializer */ +#define ADC_CH_4_MASK (1UL << 4) /*!< ADC channel 4 mask \hideinitializer */ +#define ADC_CH_5_MASK (1UL << 5) /*!< ADC channel 5 mask \hideinitializer */ +#define ADC_CH_6_MASK (1UL << 6) /*!< ADC channel 6 mask \hideinitializer */ +#define ADC_CH_7_MASK (1UL << 7) /*!< ADC channel 7 mask \hideinitializer */ +#define ADC_CH_NUM 8 /*!< Total Channel number \hideinitializer */ +#define ADC_HIGH_SPEED_MODE ADC_CONF_SPEED_Msk /*!< ADC working in high speed mode (3.2MHz <= ECLK <= 16MHz) \hideinitializer */ +#define ADC_NORMAL_SPEED_MODE 0 /*!< ADC working in normal speed mode (ECLK < 3.2MHz) \hideinitializer */ +#define ADC_REFSEL_VREF 0 /*!< ADC reference voltage source selection set to VREF \hideinitializer */ +#define ADC_REFSEL_AVDD (3UL << ADC_CONF_REFSEL_Pos) /*!< ADC reference voltage source selection set to AVDD \hideinitializer */ + +#define ADC_INPUT_MODE_NORMAL_CONV 0 /*!< ADC works in normal conversion mode \hideinitializer */ +#define ADC_INPUT_MODE_4WIRE_TOUCH 1 /*!< ADC works in 4-wire touch screen mode \hideinitializer */ +#define ADC_INPUT_MODE_5WIRE_TOUCH 2 /*!< ADC works in 5-wire touch screen mode \hideinitializer */ + +/*@}*/ /* end of group ADC_EXPORTED_CONSTANTS */ + + +/** @addtogroup ADC_EXPORTED_FUNCTIONS ADC Exported Functions + @{ +*/ + +/** + * @brief Get the latest ADC conversion data + * @param[in] adc Base address of ADC module + * @param[in] u32ChNum Currently not used + * @return Latest ADC conversion data + * \hideinitializer + */ +#define ADC_GET_CONVERSION_DATA(adc, u32ChNum) ((adc)->DATA) + +/** + * @brief Get the latest ADC conversion X data + * @param[in] adc Base address of ADC module + * @return Latest ADC conversion X data + * \hideinitializer + */ +#define ADC_GET_CONVERSION_XDATA(adc) ((adc)->XYDATA & ADC_XYDATA_XDATA_Msk) + +/** + * @brief Get the latest ADC conversion Y data + * @param[in] adc Base address of ADC module + * @return Latest ADC conversion Y data + * \hideinitializer + */ +#define ADC_GET_CONVERSION_YDATA(adc) ((adc)->XYDATA >> ADC_XYDATA_YDATA_Pos) + +/** + * @brief Get the latest ADC conversion Z1 data + * @param[in] adc Base address of ADC module + * @return Latest ADC conversion Z1 data + * \hideinitializer + */ +#define ADC_GET_CONVERSION_Z1DATA(adc) ((adc)->ZDATA & ADC_ZDATA_Z1DATA_Msk) + +/** + * @brief Get the latest ADC conversion Z2 data + * @param[in] adc Base address of ADC module + * @return Latest ADC conversion Z2 data + * \hideinitializer + */ +#define ADC_GET_CONVERSION_Z2DATA(adc) ((adc)->ZDATA >> ADC_ZDATA_Z2DATA_Pos) + +/** + * @brief Return the user-specified interrupt flags + * @param[in] adc Base address of ADC module + * @param[in] u32Mask Could be \ref ADC_IER_MIEN_Msk + * @return User specified interrupt flags + * \hideinitializer + */ +#define ADC_GET_INT_FLAG(adc, u32Mask) ((adc)->ISR & (u32Mask)) + +/** + * @brief This macro clear the selected interrupt status bits + * @param[in] adc Base address of ADC module + * @param[in] u32Mask Could be \ref ADC_IER_MIEN_Msk + * @return None + * \hideinitializer + */ +#define ADC_CLR_INT_FLAG(adc, u32Mask) ((adc)->ISR = (u32Mask)) + +/** + * @brief Return the user-specified interrupt flags + * @param[in] adc Base address of ADC module + * @param[in] u32Mask Could be \ref ADC_IER_MIEN_Msk + * @return User specified interrupt flags + * \hideinitializer + */ +#define ADC_GET_WKINT_FLAG(adc, u32Mask) ((adc)->WKISR & (u32Mask)) + +/** + * @brief Enable the interrupt(s) selected by u32Mask parameter. + * @param[in] adc Base address of ADC module + * @param[in] u32Mask Could be \ref ADC_IER_MIEN_Msk + * @return None + */ +#define ADC_ENABLE_INT(adc, u32Mask) ((adc)->IER |= u32Mask) + +/** + * @brief Disable the interrupt(s) selected by u32Mask parameter. + * @param[in] adc Base address of ADC module + * @param[in] u32Mask Could be \ref ADC_IER_MIEN_Msk + * @return None + */ +#define ADC_DISABLE_INT(adc, u32Mask) ((adc)->IER &= ~u32Mask) + +/** + * @brief Power down ADC module + * @param[in] adc Base address of ADC module + * @return None + * \hideinitializer + */ +#define ADC_POWER_DOWN(adc) ((adc)->CTL &= ~ADC_CTL_ADEN_Msk) + +/** + * @brief Power on ADC module + * @param[in] adc Base address of ADC module + * @return None + * \hideinitializer + */ +#define ADC_POWER_ON(adc) ((adc)->CTL |= ADC_CTL_ADEN_Msk) + + +/** + * @brief Set ADC input channel. Enabled channel will be converted while ADC starts. + * @param[in] adc Base address of ADC module + * @param[in] u32Mask Channel enable bit. Each bit corresponds to a input channel. Bit 0 is channel 0, bit 1 is channel 1... + * @return None + * @note ADC can only convert 1 channel at a time. If more than 1 channels are enabled, only channel + * with smallest number will be convert. + * \hideinitializer + */ +#define ADC_SET_INPUT_CHANNEL(adc, u32Mask) do {uint32_t u32Ch = 0, i;\ + for(i = 0; i < ADC_CH_NUM; i++) {\ + if((u32Mask) & (1 << i)) {\ + u32Ch = i;\ + break;\ + }\ + }\ + (adc)->CONF = ((adc)->CONF & ~ADC_CONF_CHSEL_Msk) | (u32Ch << ADC_CONF_CHSEL_Pos);\ + }while(0) + +/** + * @brief Start the A/D conversion. + * @param[in] adc Base address of ADC module + * @return None + * \hideinitializer + */ +#define ADC_START_CONV(adc) ((adc)->CTL |= ADC_CTL_MST_Msk) + +/** + * @brief Set the reference voltage selection. + * @param[in] adc Base address of ADC module + * @param[in] u32Ref The reference voltage selection. Valid values are: + * - \ref ADC_REFSEL_VREF + * - \ref ADC_REFSEL_AVDD + * @return None + * \hideinitializer + */ +#define ADC_SET_REF_VOLTAGE(adc, u32Ref) ((adc)->CONF = ((adc)->CONF & ~ADC_CONF_REFSEL_Msk) | (u32Ref)) + +/** + * @brief Set ADC to convert X/Y coordinate + * @param[in] adc Base address of ADC module + * @return None + * \hideinitializer + */ +#define ADC_CONVERT_XY_MODE(adc) do {(adc)->CTL &= ~ADC_CTL_PEDEEN_Msk;\ + (adc)->CONF |= ADC_CONF_TEN_Msk | ADC_CONF_ZEN_Msk;} while(0) + +/** + * @brief Set ADC to detect pen down event + * @param[in] adc Base address of ADC module + * @return None + * \hideinitializer + */ +#define ADC_DETECT_PD_MODE(adc) do {(adc)->CONF &= ~(ADC_CONF_TEN_Msk | ADC_CONF_ZEN_Msk);\ + (adc)->CTL |= ADC_CTL_PEDEEN_Msk;} while(0) + + +#define ADC_CONF_REFSEL_VREF (0<PSR & CANFD_PSR_ACT_Msk) >> CANFD_PSR_ACT_Pos) + + +/* CAN FD frame data field size. */ +typedef enum +{ + eCANFD_BYTE8 = 0, /*!< 8 byte data field. */ + eCANFD_BYTE12 = 1, /*!< 12 byte data field. */ + eCANFD_BYTE16 = 2, /*!< 16 byte data field. */ + eCANFD_BYTE20 = 3, /*!< 20 byte data field. */ + eCANFD_BYTE24 = 4, /*!< 24 byte data field. */ + eCANFD_BYTE32 = 5, /*!< 32 byte data field. */ + eCANFD_BYTE48 = 6, /*!< 48 byte data field. */ + eCANFD_BYTE64 = 7 /*!< 64 byte data field. */ +} E_CANFD_DATA_FIELD_SIZE; + +/* CAN FD Tx FIFO/Queue Mode. */ +typedef enum +{ + eCANFD_QUEUE_MODE = 0, /*!< Tx FIFO operation. */ + eCANFD_FIFO_MODE = 1 /*!< Tx Queue operation. */ +} E_CANFD_MODE; + +/* CAN FD Test & Bus monitor Mode. */ +typedef enum +{ + eCANFD_NORMAL = 0, /*!< None, Normal mode. */ + + /* + Support: + (1) to receive data frames + (2) to receive remote frames + (3) to give acknowledge to valid frames + Not support: + (1) data frames sending + (2) remote frames sending + (3) active error frames or overload frames sending + */ + eCANFD_RESTRICTED_OPERATION, /*!< Receive external RX frame and always keep recessive state or send dominate bit on ACK bit on TX pin. */ + + /* + Support: + (1) to receive valid data frames + (2) to receive valid remote frames + Not support: + (1) transmission start + (2) acknowledge to valid frames + */ + eCANFD_BUS_MONITOR, /*!< Receive external RX frame and always keep recessive state on TX pin. */ + + /* + Support: + (1) Loopback + (2) Also send out frames + Not support: + (1) to receive external frame + */ + eCANFD_LOOPBACK_EXTERNAL, /*!< Won't receive external RX frame. */ + /* + Support: + (1) Loopback + Not support: + (1) to receive external frame + (2) transmission start + */ + eCANFD_LOOPBACK_INTERNAL /*!< Won't receive external RX frame and always keep recessive state on TX pin */ +} E_CANFD_TEST_MODE; + +/* TX Buffer Configuration Parameters */ +typedef struct +{ + E_CANFD_DATA_FIELD_SIZE eDataFieldSize; /*!< TX Buffer Data Field Size (8byte .. 64byte) */ + E_CANFD_MODE eModeSel; /*!< select: CANFD_QUEUE_MODE/CANFD_FIFO_MODE */ + uint32_t u32ElemCnt; /*!< Elements in FIFO/Queue */ + uint32_t u32DBufNumber; /*!< Number of dedicated TX buffers */ +} CANFD_TX_BUF_CONFIG_T; + + +/* Nominal Bit Timing Parameters */ +typedef struct +{ + uint32_t u32BitRate; /*!< Transceiver baud rate in bps */ + uint16_t u16TDCOffset; /*!< Transceiver Delay Compensation Offset */ + uint16_t u16TDCFltrWin; /*!< Transceiver Delay Compensation Filter Window Length */ + uint8_t u8TDC; /*!< Transceiver Delay Compensation (1:Yes, 0:No) */ +} CANFD_NBT_CONFIG_T; + + +/* Data Bit Timing Parameters */ +typedef struct +{ + uint32_t u32BitRate; /*!< Transceiver baud rate in bps */ + uint16_t u16TDCOffset; /*!< Transceiver Delay Compensation Offset */ + uint16_t u16TDCFltrWin; /*!< Transceiver Delay Compensation Filter Window Length */ + uint8_t u8TDC; /*!< Transceiver Delay Compensation (1:Yes, 0:No) */ +} CANFD_DBT_CONFIG_T; + +/*! CAN FD protocol timing characteristic configuration structure. */ +typedef struct +{ + uint8_t u8PreDivider; /*!< Global Clock Division Factor. */ + uint16_t u16NominalPrescaler; /*!< Nominal clock prescaler. */ + uint8_t u8NominalRJumpwidth; /*!< Nominal Re-sync Jump Width. */ + uint8_t u8NominalPhaseSeg1; /*!< Nominal Phase Segment 1. */ + uint8_t u8NominalPhaseSeg2; /*!< Nominal Phase Segment 2. */ + uint8_t u8NominalPropSeg; /*!< Nominal Propagation Segment. */ + uint8_t u8DataPrescaler; /*!< Data clock prescaler. */ + uint8_t u8DataRJumpwidth; /*!< Data Re-sync Jump Width. */ + uint8_t u8DataPhaseSeg1; /*!< Data Phase Segment 1. */ + uint8_t u8DataPhaseSeg2; /*!< Data Phase Segment 2. */ + uint8_t u8DataPropSeg; /*!< Data Propagation Segment. */ + +} CANFD_TIMEING_CONFIG_T; + +/* CAN FD module configuration structure. */ +typedef struct +{ + CANFD_NBT_CONFIG_T sNormBitRate; /*!< Normal bit rate. */ + CANFD_DBT_CONFIG_T sDataBitRate; /*!< Data bit rate. */ + CANFD_TIMEING_CONFIG_T sConfigBitTing; /*!< Bit timing config*/ + uint8_t bFDEn; /*!< 1 == FD Operation enabled. */ + uint8_t bBitRateSwitch; /*!< 1 == Bit Rate Switch enabled (only evaluated in HW, if FD operation enabled). */ + E_CANFD_TEST_MODE evTestMode; /*!< See E_CANFD_TEST_MODE declaration. */ +} CANFD_FD_BT_CONFIG_T; + +/* CAN FD Message RAM Partitioning - i.e. Start Addresses (BYTE) */ +typedef struct +{ + uint32_t u32SIDFC_FLSSA; /*! EFID1), XIDAM not applied */ +} E_CANFD_XID_FLTR_ELEM_TYPE; + +/* Filter Element Configuration - Can be used for SFEC(Standard Id filter configuration) and EFEC(Extended Id filter configuration) */ +typedef enum +{ + eCANFD_FLTR_ELEM_DIS = 0x0, /*!< Filter Element Disable */ + eCANFD_FLTR_ELEM_STO_FIFO0 = 0x1, /*!< Filter Element Store In Fifo0 */ + eCANFD_FLTR_ELEM_STO_FIFO1 = 0x2, /*!< Filter Element Store In Fifo1 */ + eCANFD_FLTR_ELEM_REJ_ID = 0x3, /*!< Filter Element RejectId */ + eCANFD_FLTR_ELEM_SET_PRI = 0x4, /*!< Filter Element Set Priority */ + eCANFD_FLTR_ELEM_SET_PRI_STO_FIFO0 = 0x5, /*!< Filter Element Set Priority And Store In Fifo0 */ + eCANFD_FLTR_ELEM_SET_PRI_STO_FIFO1 = 0x6, /*!< Filter Element Set Priority And Store In Fifo1 */ + eCANFD_FLTR_ELEM_STO_RX_BUF_OR_DBG_MSG = 0x7 /*!< Filter Element Store In Rx Buf Or Debug Msg */ +} E_CANFD_FLTR_CONFIG; + +/* TX Event FIFO Element Struct */ +typedef struct +{ + E_CANFD_ID_TYPE eIdType; /*!< Standard ID or Extended ID */ + uint32_t u32Id; /*!< Standard ID (11bits) or Extended ID (29bits) */ + uint32_t u32DLC; /*!< Data Length Code used in the frame on the bus */ + uint32_t u32TxTs; /*!< Tx Timestamp */ + uint32_t u32MsgMarker; /*!< Message marker */ + uint8_t bErrStaInd; /*!< Error State Indicator */ + uint8_t bRemote; /*!< Remote transmission request */ + uint8_t bFDFormat; /*!< FD Format */ + uint8_t bBitRateSwitch; /*!< Bit Rate Switch */ +} CANFD_TX_EVNT_ELEM_T; + +#define CANFD_TIMEOUT 1000000 /* 1 second time-out */ +#define CANFD_OK ( 0L) /*!< CANFD operation OK */ +#define CANFD_ERR_FAIL (-1L) /*!< CANFD operation failed */ +#define CANFD_ERR_TIMEOUT (-2L) /*!< CANFD operation abort due to timeout error */ +#define CANFD_READ_REG_TIMEOUT (48UL) /*!< CANFD read register time-out count */ + +void CANFD_Open(CANFD_T *canfd, CANFD_FD_T *psCanfdStr); +void CANFD_Close(CANFD_T *canfd); +void CANFD_EnableInt(CANFD_T *canfd, uint32_t u32IntLine0, uint32_t u32IntLine1, uint32_t u32TXBTIE, uint32_t u32TXBCIE); +void CANFD_DisableInt(CANFD_T *canfd, uint32_t u32IntLine0, uint32_t u32IntLine1, uint32_t u32TXBTIE, uint32_t u32TXBCIE); +uint32_t CANFD_TransmitTxMsg(CANFD_T *canfd, uint32_t u32TxBufIdx, CANFD_FD_MSG_T *psTxMsg); +uint32_t CANFD_TransmitDMsg(CANFD_T *canfd, uint32_t u32TxBufIdx, CANFD_FD_MSG_T *psTxMsg); +void CANFD_SetGFC(CANFD_T *canfd, E_CANFD_ACC_NON_MATCH_FRM eNMStdFrm, E_CANFD_ACC_NON_MATCH_FRM eEMExtFrm, uint32_t u32RejRmtStdFrm, uint32_t u32RejRmtExtFrm); +void CANFD_SetSIDFltr(CANFD_T *canfd, uint32_t u32FltrIdx, uint32_t u32Filter); +void CANFD_SetXIDFltr(CANFD_T *canfd, uint32_t u32FltrIdx, uint32_t u32FilterLow, uint32_t u32FilterHigh); +uint32_t CANFD_ReadRxBufMsg(CANFD_T *canfd, uint8_t u8MbIdx, CANFD_FD_MSG_T *psMsgBuf); +uint32_t CANFD_ReadRxFifoMsg(CANFD_T *canfd, uint8_t u8FifoIdx, CANFD_FD_MSG_T *psMsgBuf); +void CANFD_CopyDBufToMsgBuf(CANFD_BUF_T *psRxBuffer, CANFD_FD_MSG_T *psMsgBuf); +void CANFD_CopyRxFifoToMsgBuf(CANFD_BUF_T *psRxBuf, CANFD_FD_MSG_T *psMsgBuf); +uint32_t CANFD_GetRxFifoWaterLvl(CANFD_T *canfd, uint32_t u32RxFifoNum); +void CANFD_TxBufCancelReq(CANFD_T *canfd, uint32_t u32TxBufIdx); +uint32_t CANFD_IsTxBufCancelFin(CANFD_T *canfd, uint32_t u32TxBufIdx); +uint32_t CANFD_IsTxBufTransmitOccur(CANFD_T *canfd, uint32_t u32TxBufIdx); +uint32_t CANFD_GetTxEvntFifoWaterLvl(CANFD_T *canfd); +void CANFD_CopyTxEvntFifoToUsrBuf(CANFD_T *canfd, uint32_t u32TxEvntNum, CANFD_TX_EVNT_ELEM_T *psTxEvntElem); +void CANFD_GetBusErrCount(CANFD_T *canfd, uint8_t *pu8TxErrBuf, uint8_t *pu8RxErrBuf); +int32_t CANFD_RunToNormal(CANFD_T *canfd, uint8_t u8Enable); +void CANFD_GetDefaultConfig(CANFD_FD_T *psConfig, uint8_t u8OpMode); +void CANFD_ClearStatusFlag(CANFD_T *canfd, uint32_t u32InterruptFlag); +uint32_t CANFD_GetStatusFlag(CANFD_T *canfd, uint32_t u32IntTypeFlag); +uint32_t CANFD_ReadReg(__I uint32_t *pu32RegAddr); + +/*@}*/ /* end of group CANFD_EXPORTED_FUNCTIONS */ + +/*@}*/ /* end of group CANFD_Driver */ + +/*@}*/ /* end of group Standard_Driver */ + +#ifdef __cplusplus +} +#endif + +#if defined ( __CC_ARM ) + #pragma no_anon_unions +#endif + +#endif /* __NU_CANFD_H__ */ diff --git a/bsp/nuvoton/libraries/ma35/StdDriver/inc/nu_ccap.h b/bsp/nuvoton/libraries/ma35/StdDriver/inc/nu_ccap.h new file mode 100644 index 0000000000..5b885b77d7 --- /dev/null +++ b/bsp/nuvoton/libraries/ma35/StdDriver/inc/nu_ccap.h @@ -0,0 +1,175 @@ +/**************************************************************************//** + * @file nu_ccap.h + * @version V3.00 + * @brief M460 Series CCAP Driver Header File + * + * @copyright SPDX-License-Identifier: Apache-2.0 + * @copyright Copyright (C) 2021 Nuvoton Technology Corp. All rights reserved. + ******************************************************************************/ +#ifndef __NU_CCAP_H__ +#define __NU_CCAP_H__ + +#ifdef __cplusplus +extern "C" +{ +#endif + +/** @addtogroup Standard_Driver Standard Driver + @{ +*/ + +/** @addtogroup CCAP_Driver CCAP Driver + @{ +*/ + +/** @addtogroup CCAP_EXPORTED_CONSTANTS CCAP Exported Constants + @{ +*/ + +/*---------------------------------------------------------------------------------------------------------*/ +/* CTL constant definitions */ +/*---------------------------------------------------------------------------------------------------------*/ +#define CCAP_CTL_CCAPEN (1ul<CTL & CCAP_CTL_CCAPEN_Msk)?0:1) + +/** + * @brief Clear CCAP flag + * + * @param[in] u32IntMask interrupt flags settings. It could be + * - \ref CCAP_INT_VINTF_Msk + * - \ref CCAP_INT_MEINTF_Msk + * - \ref CCAP_INT_ADDRMINTF_Msk + * - \ref CCAP_INT_MDINTF_Msk + * + * @return None + * + * @details Clear Camera Capture Interface interrupt flag + * \hideinitializer + */ +#define CCAP_CLR_INT_FLAG(ccap, u32IntMask) (ccap->INT |= (u32IntMask)) + +/** + * @brief Get CCAP Interrupt status + * + * @param None + * + * @return CCAP Interrupt Register + * + * @details Get Camera Capture Interface interrupt status. + * \hideinitializer + */ +#define CCAP_GET_INT_STS(ccap) (ccap->INT) + +#define CCAP_SET_CTL(ccap, u32IntMask) (ccap->CTL |= u32IntMask) +#define CCAP_CLR_CTL(ccap, u32IntMask) (ccap->CTL &= ~u32IntMask) + +void CCAP_Open(CCAP_T *ccap, uint32_t u32InFormat, uint32_t u32OutFormat); +void CCAP_SetCroppingWindow(CCAP_T *ccap, uint32_t u32VStart, uint32_t u32HStart, uint32_t u32Height, uint32_t u32Width); +void CCAP_SetPacketBuf(CCAP_T *ccap, uint32_t u32Address); +void CCAP_Close(CCAP_T *ccap); +void CCAP_EnableInt(CCAP_T *ccap, uint32_t u32IntMask); +void CCAP_DisableInt(CCAP_T *ccap, uint32_t u32IntMask); +void CCAP_Start(CCAP_T *ccap); +void CCAP_Stop(CCAP_T *ccap, uint32_t u32FrameComplete); +void CCAP_SetPacketScaling(CCAP_T *ccap, uint32_t u32VNumerator, uint32_t u32VDenominator, uint32_t u32HNumerator, uint32_t u32HDenominator); +void CCAP_SetPacketStride(CCAP_T *ccap, uint32_t u32Stride); +void CCAP_EnableMono(CCAP_T *ccap, uint32_t u32Interface); +void CCAP_DisableMono(CCAP_T *ccap); +void CCAP_EnableLumaYOne(CCAP_T *ccap, uint32_t u32th); +void CCAP_DisableLumaYOne(CCAP_T *ccap); + +void CCAP_SetPlanarYBuf(CCAP_T *ccap, uint32_t u32Address); +void CCAP_SetPlanarUBuf(CCAP_T *ccap, uint32_t u32Address); +void CCAP_SetPlanarVBuf(CCAP_T *ccap, uint32_t u32Address); +void CCAP_SetPlanarScaling(CCAP_T *ccap, uint32_t u32VNumerator, uint32_t u32VDenominator, uint32_t u32HNumerator, uint32_t u32HDenominator); +void CCAP_SetPlanarStride(CCAP_T *ccap, uint32_t u32Stride); + + +/*@}*/ /* end of group CCAP_EXPORTED_FUNCTIONS */ + +/*@}*/ /* end of group CCAP_Driver */ + +/*@}*/ /* end of group Standard_Driver */ + +#ifdef __cplusplus +} +#endif + +#endif //__NU_CCAP_H__ diff --git a/bsp/nuvoton/libraries/ma35/StdDriver/inc/nu_clk.h b/bsp/nuvoton/libraries/ma35/StdDriver/inc/nu_clk.h new file mode 100644 index 0000000000..07cffd0bf3 --- /dev/null +++ b/bsp/nuvoton/libraries/ma35/StdDriver/inc/nu_clk.h @@ -0,0 +1,622 @@ +/**************************************************************************//** + * @file CLK.h + * @brief CLK Driver Header File + * + * SPDX-License-Identifier: Apache-2.0 + * @copyright (C) 2020 Nuvoton Technology Corp. All rights reserved. + ******************************************************************************/ +#ifndef __NU_CLK_H__ +#define __NU_CLK_H__ + +#ifdef __cplusplus +extern "C" +{ +#endif + + +/** @addtogroup Standard_Driver Standard Driver + @{ +*/ + +/** @addtogroup CLK_Driver CLK Driver + @{ +*/ + +/** @addtogroup CLK_EXPORTED_CONSTANTS CLK Exported Constants + @{ +*/ + + +#define FREQ_180MHZ 180000000UL /*!< 180 MHz \hideinitializer */ + +#define CAPLL (0x0UL) +#define SYSPLL (0x1UL) +#define DDRPLL (0x2UL) +#define APLL (0x3UL) +#define EPLL (0x4UL) +#define VPLL (0x5UL) + +#define PLL_OPMODE_INTEGER (0x0UL) +#define PLL_OPMODE_FRACTIONAL (0x1UL) +#define PLL_OPMODE_SPREAD_SPECTRUM (0x2UL) +/*---------------------------------------------------------------------------------------------------------*/ +/* CLKSEL0 constant definitions. (Write-protection) */ +/*---------------------------------------------------------------------------------------------------------*/ +#define CLK_CLKSEL0_CA35CKSEL_HXT (0x0UL<>29) & 0x7UL) /*!< Calculate SYSCLK/APBCLK offset on MODULE index, 0x0:SYSCLK0, 0x1:SYSCLK1, 0x2:APBCLK0, 0x3:APBCLK1, 0x4:APBCLK2 \hideinitializer */ +#define MODULE_CLKSEL(x) (((x) >>26) & 0x7UL) /*!< Calculate CLKSEL offset on MODULE index, 0x0:CLKSEL0, 0x1:CLKSEL1, 0x2:CLKSEL2, 0x3:CLKSEL3, 0x4:CLKSEL4 \hideinitializer */ +#define MODULE_CLKSEL_Msk(x) (((x) >>22) & 0xfUL) /*!< Calculate CLKSEL mask offset on MODULE index \hideinitializer */ +#define MODULE_CLKSEL_Pos(x) (((x) >>17) & 0x1fUL) /*!< Calculate CLKSEL position offset on MODULE index \hideinitializer */ +#define MODULE_CLKDIV(x) (((x) >>14) & 0x7UL) /*!< Calculate APBCLK CLKDIV on MODULE index, 0x0:CLKDIV0, 0x1:CLKDIV1, 0x2:CLKDIV2, 0x3:CLKDIV3, 0x4:CLKDIV4 \hideinitializer */ +#define MODULE_CLKDIV_Msk(x) (((x) >>10) & 0xfUL) /*!< Calculate CLKDIV mask offset on MODULE index \hideinitializer */ +#define MODULE_CLKDIV_Pos(x) (((x) >>5 ) & 0x1fUL) /*!< Calculate CLKDIV position offset on MODULE index \hideinitializer */ +#define MODULE_IP_EN_Pos(x) (((x) >>0 ) & 0x1fUL) /*!< Calculate APBCLK offset on MODULE index \hideinitializer */ +#define MODULE_NoMsk 0x0UL /*!< Not mask on MODULE index \hideinitializer */ +#define NA MODULE_NoMsk /*!< Not Available \hideinitializer */ + +#define MODULE_APBCLK_ENC(x) (((x) & 0x07UL) << 29) /*!< MODULE index, 0x0:SYSCLK0, 0x1:SYSCLK1, 0x2:APBCLK0, 0x3:APBCLK1, 0x4:APBCLK2 \hideinitializer */ +#define MODULE_CLKSEL_ENC(x) (((x) & 0x07UL) << 26) /*!< CLKSEL offset on MODULE index, 0x0:CLKSEL0, 0x1:CLKSEL1, 0x2:CLKSEL2, 0x3:CLKSEL3, 0x4:CLKSEL4 \hideinitializer */ +#define MODULE_CLKSEL_Msk_ENC(x) (((x) & 0x0fUL) << 22) /*!< CLKSEL mask offset on MODULE index \hideinitializer */ +#define MODULE_CLKSEL_Pos_ENC(x) (((x) & 0x1fUL) << 17) /*!< CLKSEL position offset on MODULE index \hideinitializer */ +#define MODULE_CLKDIV_ENC(x) (((x) & 0x07UL) << 14) /*!< APBCLK CLKDIV on MODULE index, 0x0:CLKDIV0, 0x1:CLKDIV1, 0x2:CLKDIV2, 0x3:CLKDIV3, 0x4:CLKDIV4 \hideinitializer */ +#define MODULE_CLKDIV_Msk_ENC(x) (((x) & 0x0fUL) << 10) /*!< CLKDIV mask offset on MODULE index \hideinitializer */ +#define MODULE_CLKDIV_Pos_ENC(x) (((x) & 0x1fUL) << 5 ) /*!< CLKDIV position offset on MODULE index \hideinitializer */ +#define MODULE_IP_EN_Pos_ENC(x) (((x) & 0x1fUL) << 0 ) /*!< AHBCLK/APBCLK offset on MODULE index \hideinitializer */ + +#define PDMA0_MODULE ((1UL<<29)|(MODULE_NoMsk<<26)|(MODULE_NoMsk<<22)|(MODULE_NoMsk<<17)|(MODULE_NoMsk<<14)|(MODULE_NoMsk<<10)|(MODULE_NoMsk<<5)|(0UL<<0)) /*!< PDMA0 Module \hideinitializer */ +#define PDMA1_MODULE ((1UL<<29)|(MODULE_NoMsk<<26)|(MODULE_NoMsk<<22)|(MODULE_NoMsk<<17)|(MODULE_NoMsk<<14)|(MODULE_NoMsk<<10)|(MODULE_NoMsk<<5)|(1UL<<0)) /*!< PDMA1 Module \hideinitializer */ +#define PDMA2_MODULE ((1UL<<29)|(MODULE_NoMsk<<26)|(MODULE_NoMsk<<22)|(MODULE_NoMsk<<17)|(MODULE_NoMsk<<14)|(MODULE_NoMsk<<10)|(MODULE_NoMsk<<5)|(2UL<<0)) /*!< PDMA2 Module \hideinitializer */ +#define PDMA3_MODULE ((1UL<<29)|(MODULE_NoMsk<<26)|(MODULE_NoMsk<<22)|(MODULE_NoMsk<<17)|(MODULE_NoMsk<<14)|(MODULE_NoMsk<<10)|(MODULE_NoMsk<<5)|(3UL<<0)) /*!< PDMA3 Module \hideinitializer */ +#define WH0_MODULE ((1UL<<29)|(MODULE_NoMsk<<26)|(MODULE_NoMsk<<22)|(MODULE_NoMsk<<17)|(MODULE_NoMsk<<14)|(MODULE_NoMsk<<10)|(MODULE_NoMsk<<5)|(4UL<<0)) /*!< WH0 Module \hideinitializer */ +#define WH1_MODULE ((1UL<<29)|(MODULE_NoMsk<<26)|(MODULE_NoMsk<<22)|(MODULE_NoMsk<<17)|(MODULE_NoMsk<<14)|(MODULE_NoMsk<<10)|(MODULE_NoMsk<<5)|(5UL<<0)) /*!< WH1 Module \hideinitializer */ +#define HWS_MODULE ((1UL<<29)|(MODULE_NoMsk<<26)|(MODULE_NoMsk<<22)|(MODULE_NoMsk<<17)|(MODULE_NoMsk<<14)|(MODULE_NoMsk<<10)|(MODULE_NoMsk<<5)|(6UL<<0)) /*!< HWS Module \hideinitializer */ +#define EBI_MODULE ((1UL<<29)|(MODULE_NoMsk<<26)|(MODULE_NoMsk<<22)|(MODULE_NoMsk<<17)|(MODULE_NoMsk<<14)|(MODULE_NoMsk<<10)|(MODULE_NoMsk<<5)|(7UL<<0)) /*!< EBI Module \hideinitializer */ +#define SRAM0_MODULE ((1UL<<29)|(MODULE_NoMsk<<26)|(MODULE_NoMsk<<22)|(MODULE_NoMsk<<17)|(MODULE_NoMsk<<14)|(MODULE_NoMsk<<10)|(MODULE_NoMsk<<5)|(8UL<<0)) /*!< SRAM0 Module \hideinitializer */ +#define SRAM1_MODULE ((1UL<<29)|(MODULE_NoMsk<<26)|(MODULE_NoMsk<<22)|(MODULE_NoMsk<<17)|(MODULE_NoMsk<<14)|(MODULE_NoMsk<<10)|(MODULE_NoMsk<<5)|(9UL<<0)) /*!< SRAM1 Module \hideinitializer */ +#define ROM_MODULE ((1UL<<29)|(MODULE_NoMsk<<26)|(MODULE_NoMsk<<22)|(MODULE_NoMsk<<17)|(MODULE_NoMsk<<14)|(MODULE_NoMsk<<10)|(MODULE_NoMsk<<5)|(10UL<<0)) /*!< ROM Module \hideinitializer */ +#define TRA_MODULE ((1UL<<29)|(MODULE_NoMsk<<26)|(MODULE_NoMsk<<22)|(MODULE_NoMsk<<17)|(MODULE_NoMsk<<14)|(MODULE_NoMsk<<10)|(MODULE_NoMsk<<5)|(11UL<<0)) /*!< TRA Module \hideinitializer */ +#define DBG_MODULE ((1UL<<29)|(MODULE_NoMsk<<26)|(MODULE_NoMsk<<22)|(MODULE_NoMsk<<17)|(MODULE_NoMsk<<14)|(MODULE_NoMsk<<10)|(MODULE_NoMsk<<5)|(12UL<<0)) /*!< DBG Module \hideinitializer */ +#define CLKO_MODULE ((1UL<<29)|(MODULE_NoMsk<<26)|(MODULE_NoMsk<<22)|(MODULE_NoMsk<<17)|(MODULE_NoMsk<<14)|(MODULE_NoMsk<<10)|(MODULE_NoMsk<<5)|(13UL<<0)) /*!< CLKO Module \hideinitializer */ +#define GTMR_MODULE ((1UL<<29)|(MODULE_NoMsk<<26)|(MODULE_NoMsk<<22)|(MODULE_NoMsk<<17)|(MODULE_NoMsk<<14)|(MODULE_NoMsk<<10)|(MODULE_NoMsk<<5)|(14UL<<0)) /*!< GTMR Module \hideinitializer */ +#define GPA_MODULE ((1UL<<29)|(MODULE_NoMsk<<26)|(MODULE_NoMsk<<22)|(MODULE_NoMsk<<17)|(MODULE_NoMsk<<14)|(MODULE_NoMsk<<10)|(MODULE_NoMsk<<5)|(16UL<<0)) /*!< GPA Module \hideinitializer */ +#define GPB_MODULE ((1UL<<29)|(MODULE_NoMsk<<26)|(MODULE_NoMsk<<22)|(MODULE_NoMsk<<17)|(MODULE_NoMsk<<14)|(MODULE_NoMsk<<10)|(MODULE_NoMsk<<5)|(17UL<<0)) /*!< GPB Module \hideinitializer */ +#define GPC_MODULE ((1UL<<29)|(MODULE_NoMsk<<26)|(MODULE_NoMsk<<22)|(MODULE_NoMsk<<17)|(MODULE_NoMsk<<14)|(MODULE_NoMsk<<10)|(MODULE_NoMsk<<5)|(18UL<<0)) /*!< GPC Module \hideinitializer */ +#define GPD_MODULE ((1UL<<29)|(MODULE_NoMsk<<26)|(MODULE_NoMsk<<22)|(MODULE_NoMsk<<17)|(MODULE_NoMsk<<14)|(MODULE_NoMsk<<10)|(MODULE_NoMsk<<5)|(19UL<<0)) /*!< GPD Module \hideinitializer */ +#define GPE_MODULE ((1UL<<29)|(MODULE_NoMsk<<26)|(MODULE_NoMsk<<22)|(MODULE_NoMsk<<17)|(MODULE_NoMsk<<14)|(MODULE_NoMsk<<10)|(MODULE_NoMsk<<5)|(20UL<<0)) /*!< GPE Module \hideinitializer */ +#define GPF_MODULE ((1UL<<29)|(MODULE_NoMsk<<26)|(MODULE_NoMsk<<22)|(MODULE_NoMsk<<17)|(MODULE_NoMsk<<14)|(MODULE_NoMsk<<10)|(MODULE_NoMsk<<5)|(21UL<<0)) /*!< GPF Module \hideinitializer */ +#define GPG_MODULE ((1UL<<29)|(MODULE_NoMsk<<26)|(MODULE_NoMsk<<22)|(MODULE_NoMsk<<17)|(MODULE_NoMsk<<14)|(MODULE_NoMsk<<10)|(MODULE_NoMsk<<5)|(22UL<<0)) /*!< GPG Module \hideinitializer */ +#define GPH_MODULE ((1UL<<29)|(MODULE_NoMsk<<26)|(MODULE_NoMsk<<22)|(MODULE_NoMsk<<17)|(MODULE_NoMsk<<14)|(MODULE_NoMsk<<10)|(MODULE_NoMsk<<5)|(23UL<<0)) /*!< GPH Module \hideinitializer */ +#define GPI_MODULE ((1UL<<29)|(MODULE_NoMsk<<26)|(MODULE_NoMsk<<22)|(MODULE_NoMsk<<17)|(MODULE_NoMsk<<14)|(MODULE_NoMsk<<10)|(MODULE_NoMsk<<5)|(24UL<<0)) /*!< GPI Module \hideinitializer */ +#define GPJ_MODULE ((1UL<<29)|(MODULE_NoMsk<<26)|(MODULE_NoMsk<<22)|(MODULE_NoMsk<<17)|(MODULE_NoMsk<<14)|(MODULE_NoMsk<<10)|(MODULE_NoMsk<<5)|(25UL<<0)) /*!< GPJ Module \hideinitializer */ +#define GPK_MODULE ((1UL<<29)|(MODULE_NoMsk<<26)|(MODULE_NoMsk<<22)|(MODULE_NoMsk<<17)|(MODULE_NoMsk<<14)|(MODULE_NoMsk<<10)|(MODULE_NoMsk<<5)|(26UL<<0)) /*!< GPK Module \hideinitializer */ +#define GPL_MODULE ((1UL<<29)|(MODULE_NoMsk<<26)|(MODULE_NoMsk<<22)|(MODULE_NoMsk<<17)|(MODULE_NoMsk<<14)|(MODULE_NoMsk<<10)|(MODULE_NoMsk<<5)|(27UL<<0)) /*!< GPL Module \hideinitializer */ +#define GPM_MODULE ((1UL<<29)|(MODULE_NoMsk<<26)|(MODULE_NoMsk<<22)|(MODULE_NoMsk<<17)|(MODULE_NoMsk<<14)|(MODULE_NoMsk<<10)|(MODULE_NoMsk<<5)|(28UL<<0)) /*!< GPM Module \hideinitializer */ +#define GPN_MODULE ((1UL<<29)|(MODULE_NoMsk<<26)|(MODULE_NoMsk<<22)|(MODULE_NoMsk<<17)|(MODULE_NoMsk<<14)|(MODULE_NoMsk<<10)|(MODULE_NoMsk<<5)|(29UL<<0)) /*!< GPN Module \hideinitializer */ +#define CA35_MODULE ((0UL<<29)|(MODULE_NoMsk<<26)|(MODULE_NoMsk<<22)|(MODULE_NoMsk<<17)|(MODULE_NoMsk<<14)|(MODULE_NoMsk<<10)|(MODULE_NoMsk<<5)|(0UL<<0)) /*!< CA35 Module \hideinitializer */ +#define RTP_MODULE ((0UL<<29)|(MODULE_NoMsk<<26)|(MODULE_NoMsk<<22)|(MODULE_NoMsk<<17)|(MODULE_NoMsk<<14)|(MODULE_NoMsk<<10)|(MODULE_NoMsk<<5)|(1UL<<0)) /*!< RTP Module \hideinitializer */ +#define TAHB_MODULE ((0UL<<29)|(MODULE_NoMsk<<26)|(MODULE_NoMsk<<22)|(MODULE_NoMsk<<17)|(MODULE_NoMsk<<14)|(MODULE_NoMsk<<10)|(MODULE_NoMsk<<5)|(2UL<<0)) /*!< TAHB Module \hideinitializer */ +#define LVRDB_MODULE ((0UL<<29)|(0UL<<26) |(0x1UL<<22) |(3UL<<17) |(MODULE_NoMsk<<14)|(MODULE_NoMsk<<10)|(MODULE_NoMsk<<5)|(3UL<<0)) /*!< LVRDB Module \hideinitializer */ +#define DDR0_MODULE ((0UL<<29)|(MODULE_NoMsk<<26)|(MODULE_NoMsk<<22)|(MODULE_NoMsk<<17)|(MODULE_NoMsk<<14)|(MODULE_NoMsk<<10)|(MODULE_NoMsk<<5)|(4UL<<0)) /*!< DDR0 Module \hideinitializer */ +#define DDR6_MODULE ((0UL<<29)|(MODULE_NoMsk<<26)|(MODULE_NoMsk<<22)|(MODULE_NoMsk<<17)|(MODULE_NoMsk<<14)|(MODULE_NoMsk<<10)|(MODULE_NoMsk<<5)|(5UL<<0)) /*!< DDR6 Module \hideinitializer */ +#define CANFD0_MODULE ((0UL<<29)|(4<<26)|(1<<22)|(16<<17)|(0<<14)|(7<<10)|(0<<5)|(8UL<<0)) /*!< CANFD0 Module \hideinitializer */ +#define CANFD1_MODULE ((0UL<<29)|(4<<26)|(1<<22)|(17<<17)|(0<<14)|(7<<10)|(4<<5)|(9UL<<0)) /*!< CANFD1 Module \hideinitializer */ +#define CANFD2_MODULE ((0UL<<29)|(4<<26)|(1<<22)|(18<<17)|(0<<14)|(7<<10)|(8<<5)|(10UL<<0)) /*!< CANFD2 Module \hideinitializer */ +#define CANFD3_MODULE ((0UL<<29)|(4<<26)|(1<<22)|(19<<17)|(0<<14)|(7<<10)|(12<<5)|(11UL<<0)) /*!< CANFD3 Module \hideinitializer */ +#define SDH0_MODULE ((0UL<<29)|(0UL<<26) |(0x3UL<<22) |(0x10UL<<17) |(MODULE_NoMsk<<14)|(MODULE_NoMsk<<10)|(MODULE_NoMsk<<5)|(16UL<<0)) /*!< SDH0 Module */ +#define SDH1_MODULE ((0UL<<29)|(0UL<<26) |(0x3UL<<22) |(0x12UL<<17) |(MODULE_NoMsk<<14)|(MODULE_NoMsk<<10)|(MODULE_NoMsk<<5)|(17UL<<0)) /*!< SDH1 Module */ +#define NAND_MODULE ((0UL<<29)|(MODULE_NoMsk<<26)|(MODULE_NoMsk<<22)|(MODULE_NoMsk<<17)|(MODULE_NoMsk<<14)|(MODULE_NoMsk<<10)|(MODULE_NoMsk<<5)|(18UL<<0)) /*!< NAND Module \hideinitializer */ +#define USBD_MODULE ((0UL<<29)|(MODULE_NoMsk<<26)|(MODULE_NoMsk<<22)|(MODULE_NoMsk<<17)|(MODULE_NoMsk<<14)|(MODULE_NoMsk<<10)|(MODULE_NoMsk<<5)|(19UL<<0)) /*!< USBD Module \hideinitializer */ +#define USBH_MODULE ((0UL<<29)|(MODULE_NoMsk<<26)|(MODULE_NoMsk<<22)|(MODULE_NoMsk<<17)|(MODULE_NoMsk<<14)|(MODULE_NoMsk<<10)|(MODULE_NoMsk<<5)|(20UL<<0)) /*!< USBH Module \hideinitializer */ +#define HUSBH0_MODULE ((0UL<<29)|(MODULE_NoMsk<<26)|(MODULE_NoMsk<<22)|(MODULE_NoMsk<<17)|(MODULE_NoMsk<<14)|(MODULE_NoMsk<<10)|(MODULE_NoMsk<<5)|(21UL<<0)) /*!< HUSBH0 Module \hideinitializer */ +#define HUSBH1_MODULE ((0UL<<29)|(MODULE_NoMsk<<26)|(MODULE_NoMsk<<22)|(MODULE_NoMsk<<17)|(MODULE_NoMsk<<14)|(MODULE_NoMsk<<10)|(MODULE_NoMsk<<5)|(22UL<<0)) /*!< HUSBH1 Module \hideinitializer */ +#define GFX_MODULE ((0UL<<29)|(0UL<<26) |(0x1UL<<22) |(26UL<<17) |(MODULE_NoMsk<<14)|(MODULE_NoMsk<<10)|(MODULE_NoMsk<<5)|(24UL<<0)) /*!< GFX Module \hideinitializer */ +#define VDEC_MODULE ((0UL<<29)|(MODULE_NoMsk<<26)|(MODULE_NoMsk<<22)|(MODULE_NoMsk<<17)|(MODULE_NoMsk<<14)|(MODULE_NoMsk<<10)|(MODULE_NoMsk<<5)|(25UL<<0)) /*!< VDEC Module \hideinitializer */ +#define DCU_MODULE ((0UL<<29)|(0UL<<26) |(0x1UL<<22) |(24UL<<17) |(MODULE_NoMsk<<14)|(MODULE_NoMsk<<10)|(MODULE_NoMsk<<5)|(26UL<<0)) /*!< DCU Module \hideinitializer */ +#define GMAC0_MODULE ((0UL<<29)|(MODULE_NoMsk<<26)|(MODULE_NoMsk<<22)|(MODULE_NoMsk<<17)|(0UL<<14) |(0x3UL<<10) |(28UL<<5) |(27UL<<0)) /*!< GMAC0 Module \hideinitializer */ +#define GMAC1_MODULE ((0UL<<29)|(MODULE_NoMsk<<26)|(MODULE_NoMsk<<22)|(MODULE_NoMsk<<17)|(0UL<<14) |(0x3UL<<10) |(30UL<<5) |(28UL<<0)) /*!< GMAC1 Module \hideinitializer */ +#define CCAP0_MODULE ((0UL<<29)|(0UL<<26) |(0x3UL<<22) |(12UL<<17) |(1UL<<14) |(0xFUL<<10) |(8UL<<5) |(29UL<<0)) /*!< CCAP0 Module \hideinitializer */ +#define CCAP1_MODULE ((0UL<<29)|(0UL<<26) |(0x3UL<<22) |(14UL<<17) |(1UL<<14) |(0xFUL<<10) |(12UL<<5) |(30UL<<0)) /*!< CCAP1 Module \hideinitializer */ +#define TMR0_MODULE ((2UL<<29)|(MODULE_NoMsk<<26)|(MODULE_NoMsk<<22)|(MODULE_NoMsk<<17)|(MODULE_NoMsk<<14)|(MODULE_NoMsk<<10)|(MODULE_NoMsk<<5)|(0UL<<0)) /*!< TMR0 Module \hideinitializer */ +#define TMR1_MODULE ((2UL<<29)|(MODULE_NoMsk<<26)|(MODULE_NoMsk<<22)|(MODULE_NoMsk<<17)|(MODULE_NoMsk<<14)|(MODULE_NoMsk<<10)|(MODULE_NoMsk<<5)|(1UL<<0)) /*!< TMR1 Module \hideinitializer */ +#define TMR2_MODULE ((2UL<<29)|(MODULE_NoMsk<<26)|(MODULE_NoMsk<<22)|(MODULE_NoMsk<<17)|(MODULE_NoMsk<<14)|(MODULE_NoMsk<<10)|(MODULE_NoMsk<<5)|(2UL<<0)) /*!< TMR2 Module \hideinitializer */ +#define TMR3_MODULE ((2UL<<29)|(MODULE_NoMsk<<26)|(MODULE_NoMsk<<22)|(MODULE_NoMsk<<17)|(MODULE_NoMsk<<14)|(MODULE_NoMsk<<10)|(MODULE_NoMsk<<5)|(3UL<<0)) /*!< TMR3 Module \hideinitializer */ +#define TMR4_MODULE ((2UL<<29)|(MODULE_NoMsk<<26)|(MODULE_NoMsk<<22)|(MODULE_NoMsk<<17)|(MODULE_NoMsk<<14)|(MODULE_NoMsk<<10)|(MODULE_NoMsk<<5)|(4UL<<0)) /*!< TMR4 Module \hideinitializer */ +#define TMR5_MODULE ((2UL<<29)|(MODULE_NoMsk<<26)|(MODULE_NoMsk<<22)|(MODULE_NoMsk<<17)|(MODULE_NoMsk<<14)|(MODULE_NoMsk<<10)|(MODULE_NoMsk<<5)|(5UL<<0)) /*!< TMR5 Module \hideinitializer */ +#define TMR6_MODULE ((2UL<<29)|(MODULE_NoMsk<<26)|(MODULE_NoMsk<<22)|(MODULE_NoMsk<<17)|(MODULE_NoMsk<<14)|(MODULE_NoMsk<<10)|(MODULE_NoMsk<<5)|(6UL<<0)) /*!< TMR6 Module \hideinitializer */ +#define TMR7_MODULE ((2UL<<29)|(MODULE_NoMsk<<26)|(MODULE_NoMsk<<22)|(MODULE_NoMsk<<17)|(MODULE_NoMsk<<14)|(MODULE_NoMsk<<10)|(MODULE_NoMsk<<5)|(7UL<<0)) /*!< TMR7 Module \hideinitializer */ +#define TMR8_MODULE ((2UL<<29)|(MODULE_NoMsk<<26)|(MODULE_NoMsk<<22)|(MODULE_NoMsk<<17)|(MODULE_NoMsk<<14)|(MODULE_NoMsk<<10)|(MODULE_NoMsk<<5)|(8UL<<0)) /*!< TMR8 Module \hideinitializer */ +#define TMR9_MODULE ((2UL<<29)|(MODULE_NoMsk<<26)|(MODULE_NoMsk<<22)|(MODULE_NoMsk<<17)|(MODULE_NoMsk<<14)|(MODULE_NoMsk<<10)|(MODULE_NoMsk<<5)|(9UL<<0)) /*!< TMR9 Module \hideinitializer */ +#define TMR10_MODULE ((2UL<<29)|(MODULE_NoMsk<<26)|(MODULE_NoMsk<<22)|(MODULE_NoMsk<<17)|(MODULE_NoMsk<<14)|(MODULE_NoMsk<<10)|(MODULE_NoMsk<<5)|(10UL<<0)) /*!< TMR10 Module \hideinitializer */ +#define TMR11_MODULE ((2UL<<29)|(MODULE_NoMsk<<26)|(MODULE_NoMsk<<22)|(MODULE_NoMsk<<17)|(MODULE_NoMsk<<14)|(MODULE_NoMsk<<10)|(MODULE_NoMsk<<5)|(11UL<<0)) /*!< TMR11 Module \hideinitializer */ +#define UART0_MODULE ((2UL<<29)|(MODULE_NoMsk<<26)|(MODULE_NoMsk<<22)|(MODULE_NoMsk<<17)|(MODULE_NoMsk<<14)|(MODULE_NoMsk<<10)|(MODULE_NoMsk<<5)|(12UL<<0)) /*!< UART0 Module \hideinitializer */ +#define UART1_MODULE ((2UL<<29)|(MODULE_NoMsk<<26)|(MODULE_NoMsk<<22)|(MODULE_NoMsk<<17)|(MODULE_NoMsk<<14)|(MODULE_NoMsk<<10)|(MODULE_NoMsk<<5)|(13UL<<0)) /*!< UART1 Module \hideinitializer */ +#define UART2_MODULE ((2UL<<29)|(MODULE_NoMsk<<26)|(MODULE_NoMsk<<22)|(MODULE_NoMsk<<17)|(MODULE_NoMsk<<14)|(MODULE_NoMsk<<10)|(MODULE_NoMsk<<5)|(14UL<<0)) /*!< UART2 Module \hideinitializer */ +#define UART3_MODULE ((2UL<<29)|(MODULE_NoMsk<<26)|(MODULE_NoMsk<<22)|(MODULE_NoMsk<<17)|(MODULE_NoMsk<<14)|(MODULE_NoMsk<<10)|(MODULE_NoMsk<<5)|(15UL<<0)) /*!< UART3 Module \hideinitializer */ +#define UART4_MODULE ((2UL<<29)|(MODULE_NoMsk<<26)|(MODULE_NoMsk<<22)|(MODULE_NoMsk<<17)|(MODULE_NoMsk<<14)|(MODULE_NoMsk<<10)|(MODULE_NoMsk<<5)|(16UL<<0)) /*!< UART4 Module \hideinitializer */ +#define UART5_MODULE ((2UL<<29)|(MODULE_NoMsk<<26)|(MODULE_NoMsk<<22)|(MODULE_NoMsk<<17)|(MODULE_NoMsk<<14)|(MODULE_NoMsk<<10)|(MODULE_NoMsk<<5)|(17UL<<0)) /*!< UART5 Module \hideinitializer */ +#define UART6_MODULE ((2UL<<29)|(MODULE_NoMsk<<26)|(MODULE_NoMsk<<22)|(MODULE_NoMsk<<17)|(MODULE_NoMsk<<14)|(MODULE_NoMsk<<10)|(MODULE_NoMsk<<5)|(18UL<<0)) /*!< UART6 Module \hideinitializer */ +#define UART7_MODULE ((2UL<<29)|(MODULE_NoMsk<<26)|(MODULE_NoMsk<<22)|(MODULE_NoMsk<<17)|(MODULE_NoMsk<<14)|(MODULE_NoMsk<<10)|(MODULE_NoMsk<<5)|(19UL<<0)) /*!< UART7 Module \hideinitializer */ +#define UART8_MODULE ((2UL<<29)|(MODULE_NoMsk<<26)|(MODULE_NoMsk<<22)|(MODULE_NoMsk<<17)|(MODULE_NoMsk<<14)|(MODULE_NoMsk<<10)|(MODULE_NoMsk<<5)|(20UL<<0)) /*!< UART8 Module \hideinitializer */ +#define UART9_MODULE ((2UL<<29)|(MODULE_NoMsk<<26)|(MODULE_NoMsk<<22)|(MODULE_NoMsk<<17)|(MODULE_NoMsk<<14)|(MODULE_NoMsk<<10)|(MODULE_NoMsk<<5)|(21UL<<0)) /*!< UART9 Module \hideinitializer */ +#define UART10_MODULE ((2UL<<29)|(MODULE_NoMsk<<26)|(MODULE_NoMsk<<22)|(MODULE_NoMsk<<17)|(MODULE_NoMsk<<14)|(MODULE_NoMsk<<10)|(MODULE_NoMsk<<5)|(22UL<<0)) /*!< UART10 Module \hideinitializer */ +#define UART11_MODULE ((2UL<<29)|(MODULE_NoMsk<<26)|(MODULE_NoMsk<<22)|(MODULE_NoMsk<<17)|(MODULE_NoMsk<<14)|(MODULE_NoMsk<<10)|(MODULE_NoMsk<<5)|(23UL<<0)) /*!< UART11 Module \hideinitializer */ +#define UART12_MODULE ((2UL<<29)|(MODULE_NoMsk<<26)|(MODULE_NoMsk<<22)|(MODULE_NoMsk<<17)|(MODULE_NoMsk<<14)|(MODULE_NoMsk<<10)|(MODULE_NoMsk<<5)|(24UL<<0)) /*!< UART12 Module \hideinitializer */ +#define UART13_MODULE ((2UL<<29)|(MODULE_NoMsk<<26)|(MODULE_NoMsk<<22)|(MODULE_NoMsk<<17)|(MODULE_NoMsk<<14)|(MODULE_NoMsk<<10)|(MODULE_NoMsk<<5)|(25UL<<0)) /*!< UART13 Module \hideinitializer */ +#define UART14_MODULE ((2UL<<29)|(MODULE_NoMsk<<26)|(MODULE_NoMsk<<22)|(MODULE_NoMsk<<17)|(MODULE_NoMsk<<14)|(MODULE_NoMsk<<10)|(MODULE_NoMsk<<5)|(26UL<<0)) /*!< UART14 Module \hideinitializer */ +#define UART15_MODULE ((2UL<<29)|(MODULE_NoMsk<<26)|(MODULE_NoMsk<<22)|(MODULE_NoMsk<<17)|(MODULE_NoMsk<<14)|(MODULE_NoMsk<<10)|(MODULE_NoMsk<<5)|(27UL<<0)) /*!< UART15 Module \hideinitializer */ +#define UART16_MODULE ((2UL<<29)|(MODULE_NoMsk<<26)|(MODULE_NoMsk<<22)|(MODULE_NoMsk<<17)|(MODULE_NoMsk<<14)|(MODULE_NoMsk<<10)|(MODULE_NoMsk<<5)|(28UL<<0)) /*!< UART16 Module \hideinitializer */ +#define RTC_MODULE ((2UL<<29)|(MODULE_NoMsk<<26)|(MODULE_NoMsk<<22)|(MODULE_NoMsk<<17)|(MODULE_NoMsk<<14)|(MODULE_NoMsk<<10)|(MODULE_NoMsk<<5)|(29UL<<0)) /*!< RTC Module \hideinitializer */ +#define DDRP_MODULE ((2UL<<29)|(MODULE_NoMsk<<26)|(MODULE_NoMsk<<22)|(MODULE_NoMsk<<17)|(MODULE_NoMsk<<14)|(MODULE_NoMsk<<10)|(MODULE_NoMsk<<5)|(30UL<<0)) /*!< DDRP Module \hideinitializer */ +#define KPI_MODULE ((2UL<<29)|(MODULE_NoMsk<<26)|(MODULE_NoMsk<<22)|(MODULE_NoMsk<<17)|(MODULE_NoMsk<<14)|(MODULE_NoMsk<<10)|(MODULE_NoMsk<<5)|(31UL<<0)) /*!< KPI Module \hideinitializer */ +#define I2C0_MODULE ((3UL<<29)|(MODULE_NoMsk<<26)|(MODULE_NoMsk<<22)|(MODULE_NoMsk<<17)|(MODULE_NoMsk<<14)|(MODULE_NoMsk<<10)|(MODULE_NoMsk<<5)|(0UL<<0)) /*!< I2C0 Module \hideinitializer */ +#define I2C1_MODULE ((3UL<<29)|(MODULE_NoMsk<<26)|(MODULE_NoMsk<<22)|(MODULE_NoMsk<<17)|(MODULE_NoMsk<<14)|(MODULE_NoMsk<<10)|(MODULE_NoMsk<<5)|(1UL<<0)) /*!< I2C1 Module \hideinitializer */ +#define I2C2_MODULE ((3UL<<29)|(MODULE_NoMsk<<26)|(MODULE_NoMsk<<22)|(MODULE_NoMsk<<17)|(MODULE_NoMsk<<14)|(MODULE_NoMsk<<10)|(MODULE_NoMsk<<5)|(2UL<<0)) /*!< I2C2 Module \hideinitializer */ +#define I2C3_MODULE ((3UL<<29)|(MODULE_NoMsk<<26)|(MODULE_NoMsk<<22)|(MODULE_NoMsk<<17)|(MODULE_NoMsk<<14)|(MODULE_NoMsk<<10)|(MODULE_NoMsk<<5)|(3UL<<0)) /*!< I2C3 Module \hideinitializer */ +#define I2C4_MODULE ((3UL<<29)|(MODULE_NoMsk<<26)|(MODULE_NoMsk<<22)|(MODULE_NoMsk<<17)|(MODULE_NoMsk<<14)|(MODULE_NoMsk<<10)|(MODULE_NoMsk<<5)|(4UL<<0)) /*!< I2C4 Module \hideinitializer */ +#define I2C5_MODULE ((3UL<<29)|(MODULE_NoMsk<<26)|(MODULE_NoMsk<<22)|(MODULE_NoMsk<<17)|(MODULE_NoMsk<<14)|(MODULE_NoMsk<<10)|(MODULE_NoMsk<<5)|(5UL<<0)) /*!< I2C5 Module \hideinitializer */ +#define QSPI0_MODULE ((3UL<<29)|(4UL<<26) |(0x3UL<<22) |(8UL<<17) |(MODULE_NoMsk<<14)|(MODULE_NoMsk<<10)|(MODULE_NoMsk<<5)|(6UL<<0)) /*!< QSPI0 Module \hideinitializer */ +#define QSPI1_MODULE ((3UL<<29)|(4UL<<26) |(0x3UL<<22) |(10UL<<17) |(MODULE_NoMsk<<14)|(MODULE_NoMsk<<10)|(MODULE_NoMsk<<5)|(7UL<<0)) /*!< QSPI1 Module \hideinitializer */ +#define SC0_MODULE ((3UL<<29)|(MODULE_NoMsk<<26)|(MODULE_NoMsk<<22)|(MODULE_NoMsk<<17)|(MODULE_NoMsk<<14)|(MODULE_NoMsk<<10)|(MODULE_NoMsk<<5)|(12UL<<0)) /*!< SC0 Module \hideinitializer */ +#define SC1_MODULE ((3UL<<29)|(MODULE_NoMsk<<26)|(MODULE_NoMsk<<22)|(MODULE_NoMsk<<17)|(MODULE_NoMsk<<14)|(MODULE_NoMsk<<10)|(MODULE_NoMsk<<5)|(13UL<<0)) /*!< SC1 Module \hideinitializer */ +#define WDT0_MODULE ((3UL<<29)|(3UL<<26) |(0x3UL<<22) |(20UL<<17) |(MODULE_NoMsk<<14)|(MODULE_NoMsk<<10)|(MODULE_NoMsk<<5)|(16UL<<0)) /*!< WDT0 Module \hideinitializer */ +#define WDT1_MODULE ((3UL<<29)|(3UL<<26) |(0x3UL<<22) |(24UL<<17) |(MODULE_NoMsk<<14)|(MODULE_NoMsk<<10)|(MODULE_NoMsk<<5)|(17UL<<0)) /*!< WDT1 Module \hideinitializer */ +#define WDT2_MODULE ((3UL<<29)|(3UL<<26) |(0x3UL<<22) |(28UL<<17) |(MODULE_NoMsk<<14)|(MODULE_NoMsk<<10)|(MODULE_NoMsk<<5)|(18UL<<0)) /*!< WDT2 Module \hideinitializer */ +#define EPWM0_MODULE ((3UL<<29)|(MODULE_NoMsk<<26)|(MODULE_NoMsk<<22)|(MODULE_NoMsk<<17)|(MODULE_NoMsk<<14)|(MODULE_NoMsk<<10)|(MODULE_NoMsk<<5)|(24UL<<0)) /*!< EPWM0 Module \hideinitializer */ +#define EPWM1_MODULE ((3UL<<29)|(MODULE_NoMsk<<26)|(MODULE_NoMsk<<22)|(MODULE_NoMsk<<17)|(MODULE_NoMsk<<14)|(MODULE_NoMsk<<10)|(MODULE_NoMsk<<5)|(25UL<<0)) /*!< EPWM1 Module \hideinitializer */ +#define EPWM2_MODULE ((3UL<<29)|(MODULE_NoMsk<<26)|(MODULE_NoMsk<<22)|(MODULE_NoMsk<<17)|(MODULE_NoMsk<<14)|(MODULE_NoMsk<<10)|(MODULE_NoMsk<<5)|(26UL<<0)) /*!< EPWM2 Module \hideinitializer */ +#define I2S0_MODULE ((4UL<<29)|(MODULE_NoMsk<<26)|(MODULE_NoMsk<<22)|(MODULE_NoMsk<<17)|(MODULE_NoMsk<<14)|(MODULE_NoMsk<<10)|(MODULE_NoMsk<<5)|(0UL<<0)) /*!< I2S0 Module \hideinitializer */ +#define I2S1_MODULE ((4UL<<29)|(MODULE_NoMsk<<26)|(MODULE_NoMsk<<22)|(MODULE_NoMsk<<17)|(MODULE_NoMsk<<14)|(MODULE_NoMsk<<10)|(MODULE_NoMsk<<5)|(1UL<<0)) /*!< I2S1 Module \hideinitializer */ +#define SSMCC_MODULE ((4UL<<29)|(MODULE_NoMsk<<26)|(MODULE_NoMsk<<22)|(MODULE_NoMsk<<17)|(MODULE_NoMsk<<14)|(MODULE_NoMsk<<10)|(MODULE_NoMsk<<5)|(2UL<<0)) /*!< SSMCC Module \hideinitializer */ +#define SSPCC_MODULE ((4UL<<29)|(MODULE_NoMsk<<26)|(MODULE_NoMsk<<22)|(MODULE_NoMsk<<17)|(MODULE_NoMsk<<14)|(MODULE_NoMsk<<10)|(MODULE_NoMsk<<5)|(3UL<<0)) /*!< SSPCC Module \hideinitializer */ +#define SPI0_MODULE ((4UL<<29)|(MODULE_NoMsk<<26)|(MODULE_NoMsk<<22)|(MODULE_NoMsk<<17)|(MODULE_NoMsk<<14)|(MODULE_NoMsk<<10)|(MODULE_NoMsk<<5)|(4UL<<0)) /*!< SPI0 Module \hideinitializer */ +#define SPI1_MODULE ((4UL<<29)|(MODULE_NoMsk<<26)|(MODULE_NoMsk<<22)|(MODULE_NoMsk<<17)|(MODULE_NoMsk<<14)|(MODULE_NoMsk<<10)|(MODULE_NoMsk<<5)|(5UL<<0)) /*!< SPI1 Module \hideinitializer */ +#define SPI2_MODULE ((4UL<<29)|(MODULE_NoMsk<<26)|(MODULE_NoMsk<<22)|(MODULE_NoMsk<<17)|(MODULE_NoMsk<<14)|(MODULE_NoMsk<<10)|(MODULE_NoMsk<<5)|(6UL<<0)) /*!< SPI2 Module \hideinitializer */ +#define SPI3_MODULE ((4UL<<29)|(MODULE_NoMsk<<26)|(MODULE_NoMsk<<22)|(MODULE_NoMsk<<17)|(MODULE_NoMsk<<14)|(MODULE_NoMsk<<10)|(MODULE_NoMsk<<5)|(7UL<<0)) /*!< SPI3 Module \hideinitializer */ +#define ECAP0_MODULE ((4UL<<29)|(MODULE_NoMsk<<26)|(MODULE_NoMsk<<22)|(MODULE_NoMsk<<17)|(MODULE_NoMsk<<14)|(MODULE_NoMsk<<10)|(MODULE_NoMsk<<5)|(8UL<<0)) /*!< ECAP0 Module \hideinitializer */ +#define ECAP1_MODULE ((4UL<<29)|(MODULE_NoMsk<<26)|(MODULE_NoMsk<<22)|(MODULE_NoMsk<<17)|(MODULE_NoMsk<<14)|(MODULE_NoMsk<<10)|(MODULE_NoMsk<<5)|(9UL<<0)) /*!< ECAP1 Module \hideinitializer */ +#define ECAP2_MODULE ((4UL<<29)|(MODULE_NoMsk<<26)|(MODULE_NoMsk<<22)|(MODULE_NoMsk<<17)|(MODULE_NoMsk<<14)|(MODULE_NoMsk<<10)|(MODULE_NoMsk<<5)|(10UL<<0)) /*!< ECAP2 Module \hideinitializer */ +#define QEI0_MODULE ((4UL<<29)|(MODULE_NoMsk<<26)|(MODULE_NoMsk<<22)|(MODULE_NoMsk<<17)|(MODULE_NoMsk<<14)|(MODULE_NoMsk<<10)|(MODULE_NoMsk<<5)|(12UL<<0)) /*!< QEI0 Module \hideinitializer */ +#define QEI1_MODULE ((4UL<<29)|(MODULE_NoMsk<<26)|(MODULE_NoMsk<<22)|(MODULE_NoMsk<<17)|(MODULE_NoMsk<<14)|(MODULE_NoMsk<<10)|(MODULE_NoMsk<<5)|(13UL<<0)) /*!< QEI1 Module \hideinitializer */ +#define QEI2_MODULE ((4UL<<29)|(MODULE_NoMsk<<26)|(MODULE_NoMsk<<22)|(MODULE_NoMsk<<17)|(MODULE_NoMsk<<14)|(MODULE_NoMsk<<10)|(MODULE_NoMsk<<5)|(14UL<<0)) /*!< QEI2 Module \hideinitializer */ +#define ADC_MODULE ((4UL<<29)|(MODULE_NoMsk<<26)|(MODULE_NoMsk<<22)|(MODULE_NoMsk<<17)|(MODULE_NoMsk<<14)|(MODULE_NoMsk<<10)|(MODULE_NoMsk<<5)|(24UL<<0)) /*!< ADCModule \hideinitializer */ +#define EADC0_MODULE ((4UL<<29)|(MODULE_NoMsk<<26)|(MODULE_NoMsk<<22)|(MODULE_NoMsk<<17)|(MODULE_NoMsk<<14)|(MODULE_NoMsk<<10)|(MODULE_NoMsk<<5)|(25UL<<0)) /*!< EADC0 Module \hideinitializer */ + +/*@}*/ /* end of group CLK_EXPORTED_CONSTANTS */ + +/** @addtogroup CLK_EXPORTED_FUNCTIONS CLK Exported Functions + @{ +*/ + + +#if defined (USE_MA35D1_SUBM) +/*---------------------------------------------------------------------------------------------------------*/ +/* static inline functions */ +/*---------------------------------------------------------------------------------------------------------*/ +/* Declare these inline functions here to avoid MISRA C 2004 rule 8.1 error */ +__STATIC_INLINE void CLK_SysTickDelay(uint32_t us); +__STATIC_INLINE void CLK_SysTickLongDelay(uint32_t us); + +/** + * @brief This function execute delay function. + * @param[in] us Delay time. The Max value is 2^24 / CPU Clock(MHz). Ex: + * 72MHz => 233016us, 50MHz => 335544us, + * 48MHz => 349525us, 28MHz => 699050us ... + * @return None + * @details Use the SysTick to generate the delay time and the unit is in us. + * The SysTick clock source is from HCLK, i.e the same as system core clock. + */ +__STATIC_INLINE void CLK_SysTickDelay(uint32_t us) +{ + SysTick->LOAD = us * CyclesPerUs; + SysTick->VAL = 0x0UL; + SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk | SysTick_CTRL_ENABLE_Msk; + + /* Waiting for down-count to zero */ + while ((SysTick->CTRL & SysTick_CTRL_COUNTFLAG_Msk) == 0UL) + { + } + + /* Disable SysTick counter */ + SysTick->CTRL = 0UL; +} + +/** + * @brief This function execute long delay function. + * @param[in] us Delay time. + * @return None + * @details Use the SysTick to generate the long delay time and the UNIT is in us. + * The SysTick clock source is from HCLK, i.e the same as system core clock. + * User can use SystemCoreClockUpdate() to calculate CyclesPerUs automatically before using this function. + */ +__STATIC_INLINE void CLK_SysTickLongDelay(uint32_t us) +{ + uint32_t delay; + + /* It should <= 349525us for each delay loop */ + delay = 349525UL; + + do + { + if (us > delay) + { + us -= delay; + } + else + { + delay = us; + us = 0UL; + } + + SysTick->LOAD = delay * CyclesPerUs; + SysTick->VAL = (0x0UL); + SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk | SysTick_CTRL_ENABLE_Msk; + + /* Waiting for down-count to zero */ + while ((SysTick->CTRL & SysTick_CTRL_COUNTFLAG_Msk) == 0UL); + + /* Disable SysTick counter */ + SysTick->CTRL = 0UL; + + } + while (us > 0UL); + +} +#else +void SystemCoreClockUpdate(void); +#endif + +__STATIC_INLINE void CLK_SetPLLPowerDown(uint32_t u32PllIdx) +{ + CLK->PLL[u32PllIdx].CTL1 |= CLK_PLLnCTL1_PD_Msk; +} + +void CLK_DisableCKO(void); +void CLK_EnableCKO(uint32_t u32ClkSrc, uint32_t u32ClkDiv, uint32_t u32ClkDivBy1En); +void CLK_PowerDown(void); +uint32_t CLK_GetHXTFreq(void); +uint32_t CLK_GetLXTFreq(void); +uint32_t CLK_GetSYSCLK0Freq(void); +uint32_t CLK_GetSYSCLK1Freq(void); +uint32_t CLK_GetPCLK3Freq(void); +uint32_t CLK_GetCPUFreq(void); +uint32_t CLK_SetCoreClock(uint32_t u32Hclk); +void CLK_SetModuleClock(uint32_t u32ModuleIdx, uint32_t u32ClkSrc, uint32_t u32ClkDiv); +void CLK_SetSysTickClockSrc(uint32_t u32ClkSrc); +void CLK_EnableXtalRC(uint32_t u32ClkMask); +void CLK_DisableXtalRC(uint32_t u32ClkMask); +void CLK_EnableModuleClock(uint32_t u32ModuleIdx); +void CLK_DisableModuleClock(uint32_t u32ModuleIdx); +void CLK_DisablePLL(uint32_t u32PllIdx); +uint32_t CLK_WaitClockReady(uint32_t u32ClkMask); +void CLK_EnableSysTick(uint32_t u32ClkSrc, uint32_t u32Count); +void CLK_DisableSysTick(void); +uint32_t CLK_GetCAPLLClockFreq(void); +uint32_t CLK_GetPLLClockFreq(uint32_t u32PllIdx); +uint32_t CLK_GetModuleClockSource(uint32_t u32ModuleIdx); +uint32_t CLK_GetModuleClockDivider(uint32_t u32ModuleIdx); +uint32_t CLK_GetCAPLLClockFreq(void); +uint64_t CLK_SetPLLFreq(uint32_t u32PllIdx, uint32_t u32OpMode, uint64_t PllSrcClk, uint64_t u64PllFreq); +uint32_t CLK_GetPLLClockFreq(uint32_t u32PllIdx); +uint32_t CLK_GetPLLOpMode(uint32_t u32PllIdx); + +#define CLK_GetPCLK0Freq() CLK_GetSYSCLK1Freq() +#define CLK_GetPCLK1Freq() CLK_GetSYSCLK1Freq() +#define CLK_GetPCLK2Freq() CLK_GetSYSCLK1Freq() +#define CLK_GetPCLK3Freq() (CLK_GetSYSCLK1Freq() / 2) +#define CLK_GetPCLK4Freq() (CLK_GetSYSCLK1Freq() / 2) + +#define CLK_GetHCLK0Freq() CLK_GetSYSCLK1Freq() +#define CLK_GetHCLK1Freq() CLK_GetSYSCLK1Freq() +#define CLK_GetHCLK2Freq() CLK_GetSYSCLK1Freq() +#define CLK_GetHCLK3Freq() (CLK_GetSYSCLK1Freq() / 2) + +#define CLK_GetCA35CPUFreq CLK_GetCAPLLClockFreq + +/*@}*/ /* end of group CLK_EXPORTED_FUNCTIONS */ + +/*@}*/ /* end of group CLK_Driver */ + +/*@}*/ /* end of group Standard_Driver */ + +#ifdef __cplusplus +} +#endif + +#endif /* __NU_CLK_H__ */ + diff --git a/bsp/nuvoton/libraries/ma35/StdDriver/inc/nu_disp.h b/bsp/nuvoton/libraries/ma35/StdDriver/inc/nu_disp.h new file mode 100644 index 0000000000..5bd63f9060 --- /dev/null +++ b/bsp/nuvoton/libraries/ma35/StdDriver/inc/nu_disp.h @@ -0,0 +1,205 @@ +/**************************************************************************//** + * @file nu_disp.h + * @brief DISP driver header file + * + * SPDX-License-Identifier: Apache-2.0 + * @copyright (C) 2020 Nuvoton Technology Corp. All rights reserved. + *****************************************************************************/ +#ifndef __NU_DISP_H__ +#define __NU_DISP_H__ + +#ifdef __cplusplus +extern "C" +{ +#endif + + +/** @addtogroup Standard_Driver Standard Driver + @{ +*/ + +/** @addtogroup DISP_Driver DISP Driver + @{ +*/ + +/** @addtogroup DISP_EXPORTED_CONSTANTS DISP Exported Constants + @{ +*/ + +typedef enum +{ + eDispLcd_1024x600 = 0, + eDispLcd_800x480 = 1, + eDispLcd_1920x1080 = 2, + eDispLcd_Cnt +} E_DISP_LCD; + + +typedef enum +{ + ePolarity_Disable = -1, + ePolarity_Positive = 0, + ePolarity_Negative = 1 +} E_POLARITY; + +typedef enum +{ + eDPIFmt_D16CFG1, + eDPIFmt_D16CFG2, + eDPIFmt_D16CFG3, + eDPIFmt_D18CFG1, + eDPIFmt_D18CFG2, + eDPIFmt_D24 +} E_DPI_DATA_FMT; + +typedef enum +{ + eLayer_Video = 0, + eLayer_Overlay = 1, + eLayer_Cnt +} E_DISP_LAYER; + +typedef enum +{ + eYUV_709_BT709 = 1, + eYUV_2020_BT2020 = 3, +} E_YUV_STANDARD; + +typedef enum +{ + eFBFmt_X4R4G4B4 = 0, + eFBFmt_A4R4G4B4 = 1, + eFBFmt_X1R5G5B5 = 2, + eFBFmt_A1R5G5B5 = 3, + eFBFmt_R5G6B5 = 4, + eFBFmt_X8R8G8B8 = 5, + eFBFmt_A8R8G8B8 = 6, + eFBFmt_YUY2 = 7, + eFBFmt_UYVY = 8, + eFBFmt_INDEX8 = 9, + eFBFmt_MONOCHROME = 10, + eFBFmt_YV12 = 15, + eFBFmt_A8 = 16, + eFBFmt_NV12 = 17, + eFBFmt_NV16 = 18, + eFBFmt_RG16 = 19, + eFBFmt_R8 = 20, + eFBFmt_NV12_10BIT = 21, + eFBFmt_A2R10G10B10 = 22, + eFBFmt_NV16_10BIT = 23, + eFBFmt_INDEX1 = 24, + eFBFmt_INDEX2 = 25, + eFBFmt_INDEX4 = 26, + eFBFmt_P010 = 27, + eFBFmt_NV12_10BIT_L1 = 28, + eFBFmt_NV16_10BIT_L1 = 29 +} E_FB_FMT; + +typedef enum +{ + eOPAQUE, + eMASK, + eKEY +} E_TRANSPARENCY_MODE; + +typedef enum +{ + DC_BLEND_MODE_CLEAR, + DC_BLEND_MODE_SRC, + DC_BLEND_MODE_DST, + DC_BLEND_MODE_SRC_OVER, + DC_BLEND_MODE_DST_OVER, + DC_BLEND_MODE_SRC_IN, + DC_BLEND_MODE_DST_IN, + DC_BLEND_MODE_SRC_OUT +} E_DC_BLEND_MODE; + +typedef enum +{ + eGloAM_NORMAL, + eGloAM_GLOBAL, + eGloAM_SCALED +} E_GLOBAL_ALPHA_MODE; + + +typedef enum +{ + eBM_ZERO, + eBM_ONE, + eBM_NORMAL, + eBM_INVERSED, + eBM_COLOR, + eBM_COLOR_INVERSED, + eBM_SATURATED_ALPHA, + eBM_SATURATED_DEST_ALPHA +} E_BLENDING_MODE; + +typedef struct +{ + /* + htotal: u32HA + u32HBP + u32HFP + u32HSL + vtotal: u32VA + u32VBP + u32VFP + u32VSL + clock-frequency: htotal * vtotal * fps + */ + uint32_t u32PCF; // Pixel Clock Frequency + + uint32_t u32HA; // Horizontal Active + uint32_t u32HSL; // Horizontal Sync Length + uint32_t u32HFP; // Horizontal Front Porch + uint32_t u32HBP; // Horizontal Back Porch + uint32_t u32VA; // Vertical Active + uint32_t u32VSL; // Vertical Sync Len + uint32_t u32VFP; // Vertical Front Porch + uint32_t u32VBP; // Vertical Back Porch + + E_POLARITY eHSPP; // HSync Pulse Polarity + E_POLARITY eVSPP; // VSync Pulse Polarity + +} DISP_LCD_TIMING; + +typedef struct +{ + E_DPI_DATA_FMT eDpiFmt; // DPI Data Format + E_POLARITY eDEP; // DE Polarity + E_POLARITY eDP; // DATA Polarity + E_POLARITY eCP; // CLOCK Polarity +} DISP_PANEL_CONF; + +typedef struct +{ + uint32_t u32ResolutionWidth; + uint32_t u32ResolutionHeight; + DISP_LCD_TIMING sLcdTiming; + DISP_PANEL_CONF sPanelConf; +} DISP_LCD_INFO; + +#define DISP_ENABLE_INT() (DISP->DisplayIntrEnable |= DISP_DisplayIntrEnable_DISP0_Msk) +#define DISP_DISABLE_INT() (DISP->DisplayIntrEnable &= ~DISP_DisplayIntrEnable_DISP0_Msk) +#define DISP_GET_INTSTS() (DISP->DisplayIntr & DISP_DisplayIntr_DISP0_Msk) + +const DISP_LCD_INFO *DISP_GetLCDInst(E_DISP_LCD eDispLcd); +int32_t DISP_LCDInit(const DISP_LCD_INFO *psLCDInfo); +int32_t DISP_LCDDeinit(void); +int DISP_SetFBConfig(E_DISP_LAYER eLayer, E_FB_FMT eFbFmt, uint32_t u32ResWidth, uint32_t u32ResHeight, uint32_t u32DMAFBStartAddr); +void DISP_SetPanelConf(DISP_PANEL_CONF *psPanelConf); +void DISP_SetTiming(DISP_LCD_TIMING *psLCDTiming); +int DISP_Trigger(E_DISP_LAYER eLayer, uint32_t u32Action); +int DISP_SetTransparencyMode(E_DISP_LAYER eLayer, E_TRANSPARENCY_MODE eTM); +int DISP_SetBlendOpMode(E_DC_BLEND_MODE eDCBM, E_GLOBAL_ALPHA_MODE eGloAM_Src, E_GLOBAL_ALPHA_MODE eGloAM_Dst); +void DISP_SetBlendValue(uint32_t u32GloAV_Src, uint32_t u32GloAV_Dst); +void DISP_SetColorKeyValue(uint32_t u32ColorKeyLow, uint32_t u32ColorKeyHigh); +int DISP_SetFBAddr(E_DISP_LAYER eLayer, uint32_t u32DMAFBStartAddr); +int DISP_SetFBFmt(E_DISP_LAYER eLayer, E_FB_FMT eFbFmt, uint32_t u32Pitch); + +/*@}*/ /* end of group DISP_EXPORTED_FUNCTIONS */ + +/*@}*/ /* end of group DISP_Driver */ + +/*@}*/ /* end of group Standard_Driver */ + +#ifdef __cplusplus +} +#endif + +#endif /* __NU_DISP_H__ */ + diff --git a/bsp/nuvoton/libraries/ma35/StdDriver/inc/nu_eadc.h b/bsp/nuvoton/libraries/ma35/StdDriver/inc/nu_eadc.h new file mode 100644 index 0000000000..a25919e2d1 --- /dev/null +++ b/bsp/nuvoton/libraries/ma35/StdDriver/inc/nu_eadc.h @@ -0,0 +1,630 @@ +/**************************************************************************//** + * @file nu_eadc.h + * @brief EADC driver header file + * + * SPDX-License-Identifier: Apache-2.0 + * @copyright (C) 2020 Nuvoton Technology Corp. All rights reserved. + *****************************************************************************/ +#ifndef __NU_EADC_H__ +#define __NU_EADC_H__ + +#ifdef __cplusplus +extern "C" +{ +#endif + + +/** @addtogroup Standard_Driver Standard Driver + @{ +*/ + +/** @addtogroup EADC_Driver EADC Driver + @{ +*/ + +/** @addtogroup EADC_EXPORTED_CONSTANTS EADC Exported Constants + @{ +*/ + +/*---------------------------------------------------------------------------------------------------------*/ +/* EADC_CTL Constant Definitions */ +/*---------------------------------------------------------------------------------------------------------*/ +#define EADC_CTL_DIFFEN_SINGLE_END (0UL<CTL |= EADC_CTL_ADCRST_Msk) + +/** + * @brief Enable PDMA transfer. + * @param[in] eadc The pointer of the specified EADC module. + * @return None + * @details When A/D conversion is completed, the converted data is loaded into EADC_DATn (n: 0 ~ 18) register, + * user can enable this bit to generate a PDMA data transfer request. + * @note When set PDMAEN bit (EADC_CTL[11]), user must set ADINTENn (EADC_CTL[5:2], n=0~3) = 0 to disable interrupt. + * \hideinitializer + */ +#define EADC_ENABLE_PDMA(eadc) ((eadc)->CTL |= EADC_CTL_PDMAEN_Msk) + +/** + * @brief Disable PDMA transfer. + * @param[in] eadc The pointer of the specified EADC module. + * @return None + * @details This macro is used to disable PDMA transfer. + * \hideinitializer + */ +#define EADC_DISABLE_PDMA(eadc) ((eadc)->CTL &= (~EADC_CTL_PDMAEN_Msk)) + +/** + * @brief Enable Sample Module PDMA transfer. + * @param[in] eadc The pointer of the specified EADC module. + * @param[in] u32ModuleMask the combination of sample module interrupt status bits. Each bit corresponds to a sample module interrupt status. + * This parameter decides which sample module interrupts will be disabled, valid range are between 1~0x7FFFF. + * @return None + * @details When A/D conversion is completed, the converted data is loaded into EADC_DATn (n: 0 ~ 18) register, + * user can enable this bit to generate a PDMA data transfer request. + * \hideinitializer + */ +#define EADC_ENABLE_SAMPLE_MODULE_PDMA(eadc, u32ModuleMask) ((eadc)->PDMACTL |= u32ModuleMask) + +/** + * @brief Disable Sample Module PDMA transfer. + * @param[in] eadc The pointer of the specified EADC module. + * @param[in] u32ModuleMask the combination of sample module interrupt status bits. Each bit corresponds to a sample module interrupt status. + * This parameter decides which sample module interrupts will be disabled, valid range are between 1~0x7FFFF. + * @return None + * @details This macro is used to disable sample module PDMA transfer. + * \hideinitializer + */ +#define EADC_DISABLE_SAMPLE_MODULE_PDMA(eadc, u32ModuleMask) ((eadc)->PDMACTL &= (~u32ModuleMask)) + +/** + * @brief Enable double buffer mode. + * @param[in] eadc The pointer of the specified EADC module. + * @param[in] u32ModuleNum Decides the sample module number, valid value are from 0 to 3. + * @return None + * @details The ADC controller supports a double buffer mode in sample module 0~3. + * If user enable DBMEN (EADC_SCTLn[23], n=0~3), the double buffer mode will enable. + * \hideinitializer + */ +#define EADC_ENABLE_DOUBLE_BUFFER(eadc, u32ModuleNum) ((eadc)->SCTL[(u32ModuleNum)] |= EADC_SCTL_DBMEN_Msk) + +/** + * @brief Disable double buffer mode. + * @param[in] eadc The pointer of the specified EADC module. + * @param[in] u32ModuleNum Decides the sample module number, valid value are from 0 to 3. + * @return None + * @details Sample has one sample result register. + * \hideinitializer + */ +#define EADC_DISABLE_DOUBLE_BUFFER(eadc, u32ModuleNum) ((eadc)->SCTL[(u32ModuleNum)] &= ~EADC_SCTL_DBMEN_Msk) + +/** + * @brief Set ADIFn at A/D end of conversion. + * @param[in] eadc The pointer of the specified EADC module. + * @param[in] u32ModuleNum Decides the sample module number, valid value are from 0 to 15. + * @return None + * @details The A/D converter generates ADIFn (EADC_STATUS2[3:0], n=0~3) at the start of conversion. + * \hideinitializer + */ +#define EADC_ENABLE_INT_POSITION(eadc, u32ModuleNum) ((eadc)->SCTL[(u32ModuleNum)] |= EADC_SCTL_INTPOS_Msk) + +/** + * @brief Set ADIFn at A/D start of conversion. + * @param[in] eadc The pointer of the specified EADC module. + * @param[in] u32ModuleNum Decides the sample module number, valid value are from 0 to 15. + * @return None + * @details The A/D converter generates ADIFn (EADC_STATUS2[3:0], n=0~3) at the end of conversion. + * \hideinitializer + */ +#define EADC_DISABLE_INT_POSITION(eadc, u32ModuleNum) ((eadc)->SCTL[(u32ModuleNum)] &= ~EADC_SCTL_INTPOS_Msk) + +/** + * @brief Enable the interrupt. + * @param[in] eadc The pointer of the specified EADC module. + * @param[in] u32Mask Decides the combination of interrupt status bits. Each bit corresponds to a interrupt status. + * This parameter decides which interrupts will be enabled. Bit 0 is ADCIEN0, bit 1 is ADCIEN1..., bit 3 is ADCIEN3. + * @return None + * @details The A/D converter generates a conversion end ADIFn (EADC_STATUS2[n]) upon the end of specific sample module A/D conversion. + * If ADCIENn bit (EADC_CTL[n+2]) is set then conversion end interrupt request ADINTn is generated (n=0~3). + * \hideinitializer + */ +#define EADC_ENABLE_INT(eadc, u32Mask) ((eadc)->CTL |= ((u32Mask) << EADC_CTL_ADCIEN0_Pos)) + +/** + * @brief Disable the interrupt. + * @param[in] eadc The pointer of the specified EADC module. + * @param[in] u32Mask Decides the combination of interrupt status bits. Each bit corresponds to a interrupt status. + * This parameter decides which interrupts will be disabled. Bit 0 is ADCIEN0, bit 1 is ADCIEN1..., bit 3 is ADCIEN3. + * @return None + * @details Specific sample module A/D ADINT0 interrupt function Disabled. + * \hideinitializer + */ +#define EADC_DISABLE_INT(eadc, u32Mask) ((eadc)->CTL &= ~((u32Mask) << EADC_CTL_ADCIEN0_Pos)) + +/** + * @brief Enable the sample module interrupt. + * @param[in] eadc The pointer of the specified EADC module. + * @param[in] u32IntSel Decides which interrupt source will be used, valid value are from 0 to 3. + * @param[in] u32ModuleMask the combination of sample module interrupt status bits. Each bit corresponds to a sample module interrupt status. + * This parameter decides which sample module interrupts will be enabled, valid range are between 1~0x7FFFF. + * @return None + * @details There are 4 ADC interrupts ADINT0~3, and each of these interrupts has its own interrupt vector address. + * \hideinitializer + */ +#define EADC_ENABLE_SAMPLE_MODULE_INT(eadc, u32IntSel, u32ModuleMask) ((eadc)->INTSRC[(u32IntSel)] |= (u32ModuleMask)) + +/** + * @brief Disable the sample module interrupt. + * @param[in] eadc The pointer of the specified EADC module. + * @param[in] u32IntSel Decides which interrupt source will be used, valid value are from 0 to 3. + * @param[in] u32ModuleMask the combination of sample module interrupt status bits. Each bit corresponds to a sample module interrupt status. + * This parameter decides which sample module interrupts will be disabled, valid range are between 1~0x7FFFF. + * @return None + * @details There are 4 ADC interrupts ADINT0~3, and each of these interrupts has its own interrupt vector address. + * \hideinitializer + */ +#define EADC_DISABLE_SAMPLE_MODULE_INT(eadc, u32IntSel, u32ModuleMask) ((eadc)->INTSRC[(u32IntSel)] &= ~(u32ModuleMask)) + +/** + * @brief Set the input mode output format. + * @param[in] eadc The pointer of the specified EADC module. + * @param[in] u32Format Decides the output format. Valid values are: + * - EADC_CTL_DMOF_STRAIGHT_BINARY :Select the straight binary format as the output format of the conversion result. + * - EADC_CTL_DMOF_TWOS_COMPLEMENT :Select the 2's complement format as the output format of the conversion result. + * @return None + * @details The macro is used to set A/D input mode output format. + * \hideinitializer + */ +#define EADC_SET_DMOF(eadc, u32Format) ((eadc)->CTL = ((eadc)->CTL & ~EADC_CTL_DMOF_Msk) | (u32Format)) + +/** + * @brief Start the A/D conversion. + * @param[in] eadc The pointer of the specified EADC module. + * @param[in] u32ModuleMask The combination of sample module. Each bit corresponds to a sample module. + * This parameter decides which sample module will be conversion, valid range are between 1~0x7FFFF. + * Bit 0 is sample module 0, bit 1 is sample module 1..., bit 18 is sample module 18. + * @return None + * @details After write EADC_SWTRG register to start ADC conversion, the EADC_PENDSTS register will show which SAMPLE will conversion. + * \hideinitializer + */ +#define EADC_START_CONV(eadc, u32ModuleMask) ((eadc)->SWTRG = (u32ModuleMask)) + +/** + * @brief Cancel the conversion for sample module. + * @param[in] eadc The pointer of the specified EADC module. + * @param[in] u32ModuleMask The combination of sample module. Each bit corresponds to a sample module. + * This parameter decides which sample module will stop the conversion, valid range are between 1~0x7FFFF. + * Bit 0 is sample module 0, bit 1 is sample module 1..., bit 18 is sample module18. + * @return None + * @details If user want to disable the conversion of the sample module, user can write EADC_PENDSTS register to clear it. + * \hideinitializer + */ +#define EADC_STOP_CONV(eadc, u32ModuleMask) ((eadc)->PENDSTS = (u32ModuleMask)) + +/** + * @brief Get the conversion pending flag. + * @param[in] eadc The pointer of the specified EADC module. + * @return Return the conversion pending sample module. + * @details This STPFn(EADC_PENDSTS[18:0]) bit remains 1 during pending state, when the respective ADC conversion is end, + * the STPFn (n=0~18) bit is automatically cleared to 0. + * \hideinitializer + */ +#define EADC_GET_PENDING_CONV(eadc) ((eadc)->PENDSTS) + +/** + * @brief Get the conversion data of the user-specified sample module. + * @param[in] eadc The pointer of the specified EADC module. + * @param[in] u32ModuleNum Decides the sample module number, valid value are from 0 to 18. + * @return Return the conversion data of the user-specified sample module. + * @details This macro is used to read RESULT bit (EADC_DATn[15:0], n=0~18) field to get conversion data. + * \hideinitializer + */ +#define EADC_GET_CONV_DATA(eadc, u32ModuleNum) ((eadc)->DAT[(u32ModuleNum)] & EADC_DAT_RESULT_Msk) + +/** + * @brief Get the data overrun flag of the user-specified sample module. + * @param[in] eadc The pointer of the specified EADC module. + * @param[in] u32ModuleMask The combination of data overrun status bits. Each bit corresponds to a data overrun status, valid range are between 1~0x7FFFF. + * @return Return the data overrun flag of the user-specified sample module. + * @details This macro is used to read OV bit (EADC_STATUS0[31:16], EADC_STATUS1[18:16]) field to get data overrun status. + * \hideinitializer + */ +#define EADC_GET_DATA_OVERRUN_FLAG(eadc, u32ModuleMask) ((((eadc)->STATUS0 >> EADC_STATUS0_OV_Pos) | ((eadc)->STATUS1 & EADC_STATUS1_OV_Msk)) & (u32ModuleMask)) + +/** + * @brief Get the data valid flag of the user-specified sample module. + * @param[in] eadc The pointer of the specified EADC module. + * @param[in] u32ModuleMask The combination of data valid status bits. Each bit corresponds to a data valid status, valid range are between 1~0x7FFFF. + * @return Return the data valid flag of the user-specified sample module. + * @details This macro is used to read VALID bit (EADC_STATUS0[15:0], EADC_STATUS1[2:0]) field to get data valid status. + * \hideinitializer + */ +#define EADC_GET_DATA_VALID_FLAG(eadc, u32ModuleMask) ((((eadc)->STATUS0 & EADC_STATUS0_VALID_Msk) | (((eadc)->STATUS1 & EADC_STATUS1_VALID_Msk) << 16)) & (u32ModuleMask)) + +/** + * @brief Get the double data of the user-specified sample module. + * @param[in] eadc The pointer of the specified EADC module. + * @param[in] u32ModuleNum Decides the sample module number, valid value are from 0 to 18. + * @return Return the double data of the user-specified sample module. + * @details This macro is used to read RESULT bit (EADC_DDATn[15:0], n=0~3) field to get conversion data. + * \hideinitializer + */ +#define EADC_GET_DOUBLE_DATA(eadc, u32ModuleNum) ((eadc)->DDAT[(u32ModuleNum)] & EADC_DDAT0_RESULT_Msk) + +/** + * @brief Get the user-specified interrupt flags. + * @param[in] eadc The pointer of the specified EADC module. + * @param[in] u32Mask The combination of interrupt status bits. Each bit corresponds to a interrupt status. + * Bit 0 is ADIF0, bit 1 is ADIF1..., bit 3 is ADIF3. + * Bit 4 is ADCMPF0, bit 5 is ADCMPF1..., bit 7 is ADCMPF3. + * @return Return the user-specified interrupt flags. + * @details This macro is used to get the user-specified interrupt flags. + * \hideinitializer + */ +#define EADC_GET_INT_FLAG(eadc, u32Mask) ((eadc)->STATUS2 & (u32Mask)) + +/** + * @brief Get the user-specified sample module overrun flags. + * @param[in] eadc The pointer of the specified EADC module. + * @param[in] u32ModuleMask The combination of sample module overrun status bits. Each bit corresponds to a sample module overrun status, valid range are between 1~0x7FFFF. + * @return Return the user-specified sample module overrun flags. + * @details This macro is used to get the user-specified sample module overrun flags. + * \hideinitializer + */ +#define EADC_GET_SAMPLE_MODULE_OV_FLAG(eadc, u32ModuleMask) ((eadc)->OVSTS & (u32ModuleMask)) + +/** + * @brief Clear the selected interrupt status bits. + * @param[in] eadc The pointer of the specified EADC module. + * @param[in] u32Mask The combination of compare interrupt status bits. Each bit corresponds to a compare interrupt status. + * Bit 0 is ADIF0, bit 1 is ADIF1..., bit 3 is ADIF3. + * Bit 4 is ADCMPF0, bit 5 is ADCMPF1..., bit 7 is ADCMPF3. + * @return None + * @details This macro is used to clear clear the selected interrupt status bits. + * \hideinitializer + */ +#define EADC_CLR_INT_FLAG(eadc, u32Mask) ((eadc)->STATUS2 = (u32Mask)) + +/** + * @brief Clear the selected sample module overrun status bits. + * @param[in] eadc The pointer of the specified EADC module. + * @param[in] u32ModuleMask The combination of sample module overrun status bits. Each bit corresponds to a sample module overrun status. + * Bit 0 is SPOVF0, bit 1 is SPOVF1..., bit 18 is SPOVF18. + * @return None + * @details This macro is used to clear the selected sample module overrun status bits. + * \hideinitializer + */ +#define EADC_CLR_SAMPLE_MODULE_OV_FLAG(eadc, u32ModuleMask) ((eadc)->OVSTS = (u32ModuleMask)) + +/** + * @brief Check all sample module A/D result data register overrun flags. + * @param[in] eadc The pointer of the specified EADC module. + * @retval 0 None of sample module data register overrun flag is set to 1. + * @retval 1 Any one of sample module data register overrun flag is set to 1. + * @details The AOV bit (EADC_STATUS2[27]) will keep 1 when any one of sample module data register overrun flag OVn (EADC_DATn[16]) is set to 1. + * \hideinitializer + */ +#define EADC_IS_DATA_OV(eadc) (((eadc)->STATUS2 & EADC_STATUS2_AOV_Msk) >> EADC_STATUS2_AOV_Pos) + +/** + * @brief Check all sample module A/D result data register valid flags. + * @param[in] eadc The pointer of the specified EADC module. + * @retval 0 None of sample module data register valid flag is set to 1. + * @retval 1 Any one of sample module data register valid flag is set to 1. + * @details The AVALID bit (EADC_STATUS2[26]) will keep 1 when any one of sample module data register valid flag VALIDn (EADC_DATn[17]) is set to 1. + * \hideinitializer + */ +#define EADC_IS_DATA_VALID(eadc) (((eadc)->STATUS2 & EADC_STATUS2_AVALID_Msk) >> EADC_STATUS2_AVALID_Pos) + +/** + * @brief Check all A/D sample module start of conversion overrun flags. + * @param[in] eadc The pointer of the specified EADC module. + * @retval 0 None of sample module event overrun flag is set to 1. + * @retval 1 Any one of sample module event overrun flag is set to 1. + * @details The STOVF bit (EADC_STATUS2[25]) will keep 1 when any one of sample module event overrun flag SPOVFn (EADC_OVSTS[n]) is set to 1. + * \hideinitializer + */ +#define EADC_IS_SAMPLE_MODULE_OV(eadc) (((eadc)->STATUS2 & EADC_STATUS2_STOVF_Msk) >> EADC_STATUS2_STOVF_Pos) + +/** + * @brief Check all A/D interrupt flag overrun bits. + * @param[in] eadc The pointer of the specified EADC module. + * @retval 0 None of ADINT interrupt flag is overwritten to 1. + * @retval 1 Any one of ADINT interrupt flag is overwritten to 1. + * @details The ADOVIF bit (EADC_STATUS2[24]) will keep 1 when any one of ADINT interrupt flag ADOVIFn (EADC_STATUS2[11:8]) is overwritten to 1. + * \hideinitializer + */ +#define EADC_IS_INT_FLAG_OV(eadc) (((eadc)->STATUS2 & EADC_STATUS2_ADOVIF_Msk) >> EADC_STATUS2_ADOVIF_Pos) + +/** + * @brief Get the busy state of EADC. + * @param[in] eadc The pointer of the specified EADC module. + * @retval 0 Idle state. + * @retval 1 Busy state. + * @details This macro is used to read BUSY bit (EADC_STATUS2[23]) to get busy state. + * \hideinitializer + */ +#define EADC_IS_BUSY(eadc) (((eadc)->STATUS2 & EADC_STATUS2_BUSY_Msk) >> EADC_STATUS2_BUSY_Pos) + +/** + * @brief Configure the comparator 0 and enable it. + * @param[in] eadc The pointer of the specified EADC module. + * @param[in] u32ModuleNum specifies the compare sample module, valid value are from 0 to 18. + * @param[in] u32Condition specifies the compare condition. Valid values are: + * - \ref EADC_CMP_CMPCOND_LESS_THAN :The compare condition is "less than the compare value" + * - \ref EADC_CMP_CMPCOND_GREATER_OR_EQUAL :The compare condition is "greater than or equal to the compare value + * @param[in] u16CMPData specifies the compare value, valid range are between 0~0xFFF. + * @param[in] u32MatchCount specifies the match count setting, valid range are between 0~0xF. + * @return None + * @details For example, ADC_ENABLE_CMP0(EADC, 5, ADC_ADCMPR_CMPCOND_GREATER_OR_EQUAL, 0x800, 10, EADC_CMP_CMPWEN_DISABLE, EADC_CMP_ADCMPIE_ENABLE); + * Means EADC will assert comparator 0 flag if sample module 5 conversion result is greater or + * equal to 0x800 for 10 times continuously, and a compare interrupt request is generated. + * \hideinitializer + */ +#define EADC_ENABLE_CMP0(eadc,\ + u32ModuleNum,\ + u32Condition,\ + u16CMPData,\ + u32MatchCount) ((eadc)->CMP[0] = (((eadc)->CMP[0] & ~(EADC_CMP_CMPSPL_Msk|EADC_CMP_CMPCOND_Msk|EADC_CMP_CMPDAT_Msk|EADC_CMP_CMPMCNT_Msk))|\ + (((u32ModuleNum) << EADC_CMP_CMPSPL_Pos)|\ + (u32Condition) |\ + ((u16CMPData) << EADC_CMP_CMPDAT_Pos)| \ + (((u32MatchCount) - 1) << EADC_CMP_CMPMCNT_Pos)|\ + EADC_CMP_ADCMPEN_Msk))) + +/** + * @brief Configure the comparator 1 and enable it. + * @param[in] eadc The pointer of the specified EADC module. + * @param[in] u32ModuleNum specifies the compare sample module, valid value are from 0 to 18. + * @param[in] u32Condition specifies the compare condition. Valid values are: + * - \ref EADC_CMP_CMPCOND_LESS_THAN :The compare condition is "less than the compare value" + * - \ref EADC_CMP_CMPCOND_GREATER_OR_EQUAL :The compare condition is "greater than or equal to the compare value + * @param[in] u16CMPData specifies the compare value, valid range are between 0~0xFFF. + * @param[in] u32MatchCount specifies the match count setting, valid range are between 0~0xF. + * @return None + * @details For example, ADC_ENABLE_CMP1(EADC, 5, ADC_ADCMPR_CMPCOND_GREATER_OR_EQUAL, 0x800, 10, EADC_CMP_ADCMPIE_ENABLE); + * Means EADC will assert comparator 1 flag if sample module 5 conversion result is greater or + * equal to 0x800 for 10 times continuously, and a compare interrupt request is generated. + * \hideinitializer + */ +#define EADC_ENABLE_CMP1(eadc,\ + u32ModuleNum,\ + u32Condition,\ + u16CMPData,\ + u32MatchCount) ((eadc)->CMP[1] = (((eadc)->CMP[1] & ~(EADC_CMP_CMPSPL_Msk|EADC_CMP_CMPCOND_Msk|EADC_CMP_CMPDAT_Msk|EADC_CMP_CMPMCNT_Msk))|\ + (((u32ModuleNum) << EADC_CMP_CMPSPL_Pos)|\ + (u32Condition) |\ + ((u16CMPData) << EADC_CMP_CMPDAT_Pos)| \ + (((u32MatchCount) - 1) << EADC_CMP_CMPMCNT_Pos)|\ + EADC_CMP_ADCMPEN_Msk))) + +/** + * @brief Configure the comparator 2 and enable it. + * @param[in] eadc The pointer of the specified EADC module. + * @param[in] u32ModuleNum specifies the compare sample module, valid value are from 0 to 18. + * @param[in] u32Condition specifies the compare condition. Valid values are: + * - \ref EADC_CMP_CMPCOND_LESS_THAN :The compare condition is "less than the compare value" + * - \ref EADC_CMP_CMPCOND_GREATER_OR_EQUAL :The compare condition is "greater than or equal to the compare value + * @param[in] u16CMPData specifies the compare value, valid range are between 0~0xFFF. + * @param[in] u32MatchCount specifies the match count setting, valid range are between 0~0xF. + * @return None + * @details For example, ADC_ENABLE_CMP2(EADC, 5, ADC_ADCMPR_CMPCOND_GREATER_OR_EQUAL, 0x800, 10, EADC_CMP_CMPWEN_DISABLE, EADC_CMP_ADCMPIE_ENABLE); + * Means EADC will assert comparator 2 flag if sample module 5 conversion result is greater or + * equal to 0x800 for 10 times continuously, and a compare interrupt request is generated. + * \hideinitializer + */ +#define EADC_ENABLE_CMP2(eadc,\ + u32ModuleNum,\ + u32Condition,\ + u16CMPData,\ + u32MatchCount) ((eadc)->CMP[2] = (((eadc)->CMP[2] & ~(EADC_CMP_CMPSPL_Msk|EADC_CMP_CMPCOND_Msk|EADC_CMP_CMPDAT_Msk|EADC_CMP_CMPMCNT_Msk))|\ + (((u32ModuleNum) << EADC_CMP_CMPSPL_Pos)|\ + (u32Condition) |\ + ((u16CMPData) << EADC_CMP_CMPDAT_Pos)| \ + (((u32MatchCount) - 1) << EADC_CMP_CMPMCNT_Pos)|\ + EADC_CMP_ADCMPEN_Msk))) + +/** + * @brief Configure the comparator 3 and enable it. + * @param[in] eadc The pointer of the specified EADC module. + * @param[in] u32ModuleNum specifies the compare sample module, valid value are from 0 to 18. + * @param[in] u32Condition specifies the compare condition. Valid values are: + * - \ref EADC_CMP_CMPCOND_LESS_THAN :The compare condition is "less than the compare value" + * - \ref EADC_CMP_CMPCOND_GREATER_OR_EQUAL :The compare condition is "greater than or equal to the compare value + * @param[in] u16CMPData specifies the compare value, valid range are between 0~0xFFF. + * @param[in] u32MatchCount specifies the match count setting, valid range are between 1~0xF. + * @return None + * @details For example, ADC_ENABLE_CMP3(EADC, 5, ADC_ADCMPR_CMPCOND_GREATER_OR_EQUAL, 0x800, 10, EADC_CMP_ADCMPIE_ENABLE); + * Means EADC will assert comparator 3 flag if sample module 5 conversion result is greater or + * equal to 0x800 for 10 times continuously, and a compare interrupt request is generated. + * \hideinitializer + */ +#define EADC_ENABLE_CMP3(eadc,\ + u32ModuleNum,\ + u32Condition,\ + u16CMPData,\ + u32MatchCount) ((eadc)->CMP[3] = (((eadc)->CMP[3] & ~(EADC_CMP_CMPSPL_Msk|EADC_CMP_CMPCOND_Msk|EADC_CMP_CMPDAT_Msk|EADC_CMP_CMPMCNT_Msk))|\ + (((u32ModuleNum) << EADC_CMP_CMPSPL_Pos)|\ + (u32Condition) |\ + ((u16CMPData) << EADC_CMP_CMPDAT_Pos)| \ + (((u32MatchCount) - 1) << EADC_CMP_CMPMCNT_Pos)|\ + EADC_CMP_ADCMPEN_Msk))) + +/** + * @brief Enable the compare window mode. + * @param[in] eadc The pointer of the specified EADC module. + * @param[in] u32CMP Specifies the compare register, valid value are 0 and 2. + * @return None + * @details ADCMPF0 (EADC_STATUS2[4]) will be set when both EADC_CMP0 and EADC_CMP1 compared condition matched. + * \hideinitializer + */ +#define EADC_ENABLE_CMP_WINDOW_MODE(eadc, u32CMP) ((eadc)->CMP[(u32CMP)] |= EADC_CMP_CMPWEN_Msk) + +/** + * @brief Disable the compare window mode. + * @param[in] eadc The pointer of the specified EADC module. + * @param[in] u32CMP Specifies the compare register, valid value are 0 and 2. + * @return None + * @details ADCMPF2 (EADC_STATUS2[6]) will be set when both EADC_CMP2 and EADC_CMP3 compared condition matched. + * \hideinitializer + */ +#define EADC_DISABLE_CMP_WINDOW_MODE(eadc, u32CMP) ((eadc)->CMP[(u32CMP)] &= ~EADC_CMP_CMPWEN_Msk) + +/** + * @brief Enable the compare interrupt. + * @param[in] eadc The pointer of the specified EADC module. + * @param[in] u32CMP Specifies the compare register, valid value are from 0 to 3. + * @return None + * @details If the compare function is enabled and the compare condition matches the setting of CMPCOND (EADC_CMPn[2], n=0~3) + * and CMPMCNT (EADC_CMPn[11:8], n=0~3), ADCMPFn (EADC_STATUS2[7:4], n=0~3) will be asserted, in the meanwhile, + * if ADCMPIE is set to 1, a compare interrupt request is generated. + * \hideinitializer + */ +#define EADC_ENABLE_CMP_INT(eadc, u32CMP) ((eadc)->CMP[(u32CMP)] |= EADC_CMP_ADCMPIE_Msk) + +/** + * @brief Disable the compare interrupt. + * @param[in] eadc The pointer of the specified EADC module. + * @param[in] u32CMP Specifies the compare register, valid value are from 0 to 3. + * @return None + * @details This macro is used to disable the compare interrupt. + * \hideinitializer + */ +#define EADC_DISABLE_CMP_INT(eadc, u32CMP) ((eadc)->CMP[(u32CMP)] &= ~EADC_CMP_ADCMPIE_Msk) + +/** + * @brief Disable comparator 0. + * @param[in] eadc The pointer of the specified EADC module. + * @return None + * @details This macro is used to disable comparator 0. + * \hideinitializer + */ +#define EADC_DISABLE_CMP0(eadc) ((eadc)->CMP[0] = 0) + +/** + * @brief Disable comparator 1. + * @param[in] eadc The pointer of the specified EADC module. + * @return None + * @details This macro is used to disable comparator 1. + * \hideinitializer + */ +#define EADC_DISABLE_CMP1(eadc) ((eadc)->CMP[1] = 0) + +/** + * @brief Disable comparator 2. + * @param[in] eadc The pointer of the specified EADC module. + * @return None + * @details This macro is used to disable comparator 2. + * \hideinitializer + */ +#define EADC_DISABLE_CMP2(eadc) ((eadc)->CMP[2] = 0) + +/** + * @brief Disable comparator 3. + * @param[in] eadc The pointer of the specified EADC module. + * @return None + * @details This macro is used to disable comparator 3. + * \hideinitializer + */ +#define EADC_DISABLE_CMP3(eadc) ((eadc)->CMP[3] = 0) + +/*---------------------------------------------------------------------------------------------------------*/ +/* Define EADC functions prototype */ +/*---------------------------------------------------------------------------------------------------------*/ +void EADC_Open(EADC_T *eadc, uint32_t u32InputMode); +void EADC_Close(EADC_T *eadc); +void EADC_ConfigSampleModule(EADC_T *eadc, uint32_t u32ModuleNum, uint32_t u32TriggerSrc, uint32_t u32Channel); +void EADC_SetTriggerDelayTime(EADC_T *eadc, uint32_t u32ModuleNum, uint32_t u32TriggerDelayTime, uint32_t u32DelayClockDivider); +void EADC_SetExtendSampleTime(EADC_T *eadc, uint32_t u32ModuleNum, uint32_t u32ExtendSampleTime); + +/*@}*/ /* end of group EADC_EXPORTED_FUNCTIONS */ + +/*@}*/ /* end of group EADC_Driver */ + +/*@}*/ /* end of group Standard_Driver */ + +#ifdef __cplusplus +} +#endif + +#endif /* __NU_EADC_H__ */ + diff --git a/bsp/nuvoton/libraries/ma35/StdDriver/inc/nu_ebi.h b/bsp/nuvoton/libraries/ma35/StdDriver/inc/nu_ebi.h new file mode 100644 index 0000000000..83b6a68687 --- /dev/null +++ b/bsp/nuvoton/libraries/ma35/StdDriver/inc/nu_ebi.h @@ -0,0 +1,350 @@ +/**************************************************************************//** + * @file nu_ebi.h + * @brief External Bus Interface(EBI) driver header file + * + * SPDX-License-Identifier: Apache-2.0 + * @copyright (C) 2020 Nuvoton Technology Corp. All rights reserved. + *****************************************************************************/ +#ifndef __NU_EBI_H__ +#define __NU_EBI_H__ + +#ifdef __cplusplus +extern "C" +{ +#endif + + +/** @addtogroup Standard_Driver Standard Driver + @{ +*/ + +/** @addtogroup EBI_Driver EBI Driver + @{ +*/ + +/** @addtogroup EBI_EXPORTED_CONSTANTS EBI Exported Constants + @{ +*/ +/*---------------------------------------------------------------------------------------------------------*/ +/* Miscellaneous Constant Definitions */ +/*---------------------------------------------------------------------------------------------------------*/ +#define EBI_BANK0_BASE_ADDR 0x68000000UL /*!< EBI bank0 base address \hideinitializer */ +#define EBI_BANK1_BASE_ADDR 0x68100000UL /*!< EBI bank1 base address \hideinitializer */ +#define EBI_BANK2_BASE_ADDR 0x68200000UL /*!< EBI bank2 base address \hideinitializer */ +#define EBI_MAX_SIZE 0x00100000UL /*!< Maximum EBI size for each bank is 1 MB \hideinitializer */ + +/*---------------------------------------------------------------------------------------------------------*/ +/* Constants for EBI bank number */ +/*---------------------------------------------------------------------------------------------------------*/ +#define EBI_BANK0 0UL /*!< EBI bank 0 \hideinitializer */ +#define EBI_BANK1 1UL /*!< EBI bank 1 \hideinitializer */ +#define EBI_BANK2 2UL /*!< EBI bank 2 \hideinitializer */ + +/*---------------------------------------------------------------------------------------------------------*/ +/* Constants for EBI data bus width */ +/*---------------------------------------------------------------------------------------------------------*/ +#define EBI_BUSWIDTH_8BIT 8UL /*!< EBI bus width is 8-bit \hideinitializer */ +#define EBI_BUSWIDTH_16BIT 16UL /*!< EBI bus width is 16-bit \hideinitializer */ + +/*---------------------------------------------------------------------------------------------------------*/ +/* Constants for EBI CS Active Level */ +/*---------------------------------------------------------------------------------------------------------*/ +#define EBI_CS_ACTIVE_LOW 0UL /*!< EBI CS active level is low \hideinitializer */ +#define EBI_CS_ACTIVE_HIGH 1UL /*!< EBI CS active level is high \hideinitializer */ + +/*---------------------------------------------------------------------------------------------------------*/ +/* Constants for EBI MCLK divider and Timing */ +/*---------------------------------------------------------------------------------------------------------*/ +#define EBI_MCLKDIV_1 0x0UL /*!< EBI output clock(MCLK) is HCLK/1 \hideinitializer */ +#define EBI_MCLKDIV_2 0x1UL /*!< EBI output clock(MCLK) is HCLK/2 \hideinitializer */ +#define EBI_MCLKDIV_4 0x2UL /*!< EBI output clock(MCLK) is HCLK/4 \hideinitializer */ +#define EBI_MCLKDIV_8 0x3UL /*!< EBI output clock(MCLK) is HCLK/8 \hideinitializer */ +#define EBI_MCLKDIV_16 0x4UL /*!< EBI output clock(MCLK) is HCLK/16 \hideinitializer */ +#define EBI_MCLKDIV_32 0x5UL /*!< EBI output clock(MCLK) is HCLK/32 \hideinitializer */ +#define EBI_MCLKDIV_64 0x6UL /*!< EBI output clock(MCLK) is HCLK/64 \hideinitializer */ +#define EBI_MCLKDIV_128 0x7UL /*!< EBI output clock(MCLK) is HCLK/128 \hideinitializer */ + +#define EBI_TIMING_FASTEST 0x0UL /*!< EBI timing is the fastest \hideinitializer */ +#define EBI_TIMING_VERYFAST 0x1UL /*!< EBI timing is very fast \hideinitializer */ +#define EBI_TIMING_FAST 0x2UL /*!< EBI timing is fast \hideinitializer */ +#define EBI_TIMING_NORMAL 0x3UL /*!< EBI timing is normal \hideinitializer */ +#define EBI_TIMING_SLOW 0x4UL /*!< EBI timing is slow \hideinitializer */ +#define EBI_TIMING_VERYSLOW 0x5UL /*!< EBI timing is very slow \hideinitializer */ +#define EBI_TIMING_SLOWEST 0x6UL /*!< EBI timing is the slowest \hideinitializer */ + +#define EBI_OPMODE_NORMAL 0x0UL /*!< EBI bus operate in normal mode \hideinitializer */ +#define EBI_OPMODE_CACCESS (EBI_CTL_CACCESS_Msk) /*!< EBI bus operate in Continuous Data Access mode \hideinitializer */ +#define EBI_OPMODE_ADSEPARATE (EBI_CTL_ADSEPEN_Msk) /*!< EBI bus operate in AD Separate mode \hideinitializer */ + +/*@}*/ /* end of group EBI_EXPORTED_CONSTANTS */ + + +/** @addtogroup EBI_EXPORTED_FUNCTIONS EBI Exported Functions + @{ +*/ + +/** + * @brief Read 8-bit data on EBI bank0 + * + * @param[in] u32Addr The data address on EBI bank0. + * + * @return 8-bit Data + * + * @details This macro is used to read 8-bit data from specify address on EBI bank0. + * \hideinitializer + */ +#define EBI0_READ_DATA8(u32Addr) (*((volatile unsigned char *)(EBI_BANK0_BASE_ADDR+(u32Addr)))) + +/** + * @brief Write 8-bit data to EBI bank0 + * + * @param[in] u32Addr The data address on EBI bank0. + * @param[in] u32Data Specify data to be written. + * + * @return None + * + * @details This macro is used to write 8-bit data to specify address on EBI bank0. + * \hideinitializer + */ +#define EBI0_WRITE_DATA8(u32Addr, u32Data) (*((volatile unsigned char *)(EBI_BANK0_BASE_ADDR+(u32Addr))) = (u32Data)) + +/** + * @brief Read 16-bit data on EBI bank0 + * + * @param[in] u32Addr The data address on EBI bank0. + * + * @return 16-bit Data + * + * @details This macro is used to read 16-bit data from specify address on EBI bank0. + * \hideinitializer + */ +#define EBI0_READ_DATA16(u32Addr) (*((volatile unsigned short *)(EBI_BANK0_BASE_ADDR+(u32Addr)))) + +/** + * @brief Write 16-bit data to EBI bank0 + * + * @param[in] u32Addr The data address on EBI bank0. + * @param[in] u32Data Specify data to be written. + * + * @return None + * + * @details This macro is used to write 16-bit data to specify address on EBI bank0. + * \hideinitializer + */ +#define EBI0_WRITE_DATA16(u32Addr, u32Data) (*((volatile unsigned short *)(EBI_BANK0_BASE_ADDR+(u32Addr))) = (u32Data)) + +/** + * @brief Read 32-bit data on EBI bank0 + * + * @param[in] u32Addr The data address on EBI bank0. + * + * @return 32-bit Data + * + * @details This macro is used to read 32-bit data from specify address on EBI bank0. + * \hideinitializer + */ +#define EBI0_READ_DATA32(u32Addr) (*((volatile unsigned int *)(EBI_BANK0_BASE_ADDR+(u32Addr)))) + +/** + * @brief Write 32-bit data to EBI bank0 + * + * @param[in] u32Addr The data address on EBI bank0. + * @param[in] u32Data Specify data to be written. + * + * @return None + * + * @details This macro is used to write 32-bit data to specify address on EBI bank0. + * \hideinitializer + */ +#define EBI0_WRITE_DATA32(u32Addr, u32Data) (*((volatile unsigned int *)(EBI_BANK0_BASE_ADDR+(u32Addr))) = (u32Data)) + +/** + * @brief Read 8-bit data on EBI bank1 + * + * @param[in] u32Addr The data address on EBI bank1. + * + * @return 8-bit Data + * + * @details This macro is used to read 8-bit data from specify address on EBI bank1. + * \hideinitializer + */ +#define EBI1_READ_DATA8(u32Addr) (*((volatile unsigned char *)(EBI_BANK1_BASE_ADDR+(u32Addr)))) + +/** + * @brief Write 8-bit data to EBI bank1 + * + * @param[in] u32Addr The data address on EBI bank1. + * @param[in] u32Data Specify data to be written. + * + * @return None + * + * @details This macro is used to write 8-bit data to specify address on EBI bank1. + * \hideinitializer + */ +#define EBI1_WRITE_DATA8(u32Addr, u32Data) (*((volatile unsigned char *)(EBI_BANK1_BASE_ADDR+(u32Addr))) = (u32Data)) + +/** + * @brief Read 16-bit data on EBI bank1 + * + * @param[in] u32Addr The data address on EBI bank1. + * + * @return 16-bit Data + * + * @details This macro is used to read 16-bit data from specify address on EBI bank1. + * \hideinitializer + */ +#define EBI1_READ_DATA16(u32Addr) (*((volatile unsigned short *)(EBI_BANK1_BASE_ADDR+(u32Addr)))) + +/** + * @brief Write 16-bit data to EBI bank1 + * + * @param[in] u32Addr The data address on EBI bank1. + * @param[in] u32Data Specify data to be written. + * + * @return None + * + * @details This macro is used to write 16-bit data to specify address on EBI bank1. + * \hideinitializer + */ +#define EBI1_WRITE_DATA16(u32Addr, u32Data) (*((volatile unsigned short *)(EBI_BANK1_BASE_ADDR+(u32Addr))) = (u32Data)) + +/** + * @brief Read 32-bit data on EBI bank1 + * + * @param[in] u32Addr The data address on EBI bank1. + * + * @return 32-bit Data + * + * @details This macro is used to read 32-bit data from specify address on EBI bank1. + * \hideinitializer + */ +#define EBI1_READ_DATA32(u32Addr) (*((volatile unsigned int *)(EBI_BANK1_BASE_ADDR+(u32Addr)))) + +/** + * @brief Write 32-bit data to EBI bank1 + * + * @param[in] u32Addr The data address on EBI bank1. + * @param[in] u32Data Specify data to be written. + * + * @return None + * + * @details This macro is used to write 32-bit data to specify address on EBI bank1. + * \hideinitializer + */ +#define EBI1_WRITE_DATA32(u32Addr, u32Data) (*((volatile unsigned int *)(EBI_BANK1_BASE_ADDR+(u32Addr))) = (u32Data)) + +/** + * @brief Read 8-bit data on EBI bank2 + * + * @param[in] u32Addr The data address on EBI bank2. + * + * @return 8-bit Data + * + * @details This macro is used to read 8-bit data from specify address on EBI bank2. + * \hideinitializer + */ +#define EBI2_READ_DATA8(u32Addr) (*((volatile unsigned char *)(EBI_BANK2_BASE_ADDR+(u32Addr)))) + +/** + * @brief Write 8-bit data to EBI bank2 + * + * @param[in] u32Addr The data address on EBI bank2. + * @param[in] u32Data Specify data to be written. + * + * @return None + * + * @details This macro is used to write 8-bit data to specify address on EBI bank2. + * \hideinitializer + */ +#define EBI2_WRITE_DATA8(u32Addr, u32Data) (*((volatile unsigned char *)(EBI_BANK2_BASE_ADDR+(u32Addr))) = (u32Data)) + +/** + * @brief Read 16-bit data on EBI bank2 + * + * @param[in] u32Addr The data address on EBI bank2. + * + * @return 16-bit Data + * + * @details This macro is used to read 16-bit data from specify address on EBI bank2. + * \hideinitializer + */ +#define EBI2_READ_DATA16(u32Addr) (*((volatile unsigned short *)(EBI_BANK2_BASE_ADDR+(u32Addr)))) + +/** + * @brief Write 16-bit data to EBI bank2 + * + * @param[in] u32Addr The data address on EBI bank2. + * @param[in] u32Data Specify data to be written. + * + * @return None + * + * @details This macro is used to write 16-bit data to specify address on EBI bank2. + * \hideinitializer + */ +#define EBI2_WRITE_DATA16(u32Addr, u32Data) (*((volatile unsigned short *)(EBI_BANK2_BASE_ADDR+(u32Addr))) = (u32Data)) + +/** + * @brief Read 32-bit data on EBI bank2 + * + * @param[in] u32Addr The data address on EBI bank2. + * + * @return 32-bit Data + * + * @details This macro is used to read 32-bit data from specify address on EBI bank2. + * \hideinitializer + */ +#define EBI2_READ_DATA32(u32Addr) (*((volatile unsigned int *)(EBI_BANK2_BASE_ADDR+(u32Addr)))) + +/** + * @brief Write 32-bit data to EBI bank2 + * + * @param[in] u32Addr The data address on EBI bank2. + * @param[in] u32Data Specify data to be written. + * + * @return None + * + * @details This macro is used to write 32-bit data to specify address on EBI bank2. + * \hideinitializer + */ +#define EBI2_WRITE_DATA32(u32Addr, u32Data) (*((volatile unsigned int *)(EBI_BANK2_BASE_ADDR+(u32Addr))) = (u32Data)) + +/** + * @brief Enable EBI Write Buffer + * + * @param None + * + * @return None + * + * @details This macro is used to improve EBI write operation for all EBI banks. + * \hideinitializer + */ +#define EBI_ENABLE_WRITE_BUFFER() (EBI->CTL0 |= EBI_CTL_WBUFEN_Msk); + +/** + * @brief Disable EBI Write Buffer + * + * @param None + * + * @return None + * + * @details This macro is used to disable EBI write buffer function. + * \hideinitializer + */ +#define EBI_DISABLE_WRITE_BUFFER() (EBI->CTL0 &= ~EBI_CTL_WBUFEN_Msk); + +void EBI_Open(uint32_t u32Bank, uint32_t u32DataWidth, uint32_t u32TimingClass, uint32_t u32BusMode, uint32_t u32CSActiveLevel); +void EBI_Close(uint32_t u32Bank); +void EBI_SetBusTiming(uint32_t u32Bank, uint32_t u32TimingConfig, uint32_t u32MclkDiv); + +/*@}*/ /* end of group EBI_EXPORTED_FUNCTIONS */ + +/*@}*/ /* end of group EBI_Driver */ + +/*@}*/ /* end of group Standard_Driver */ + +#ifdef __cplusplus +} +#endif + +#endif + diff --git a/bsp/nuvoton/libraries/ma35/StdDriver/inc/nu_ecap.h b/bsp/nuvoton/libraries/ma35/StdDriver/inc/nu_ecap.h new file mode 100644 index 0000000000..a17981ceec --- /dev/null +++ b/bsp/nuvoton/libraries/ma35/StdDriver/inc/nu_ecap.h @@ -0,0 +1,453 @@ +/**************************************************************************//** + * @file nu_ecap.h + * @brief EnHanced Input Capture Timer(ECAP) driver header file + * + * SPDX-License-Identifier: Apache-2.0 + * @copyright (C) 2020 Nuvoton Technology Corp. All rights reserved. + *****************************************************************************/ +#ifndef __NU_ECAP_H__ +#define __NU_ECAP_H__ + +#ifdef __cplusplus +extern "C" +{ +#endif + + +/** @addtogroup Standard_Driver Standard Driver + @{ +*/ + +/** @addtogroup ECAP_Driver ECAP Driver + @{ +*/ + +/** @addtogroup ECAP_EXPORTED_CONSTANTS ECAP Exported Constants + @{ +*/ + +#define ECAP_IC0 (0UL) /*!< ECAP IC0 Unit \hideinitializer */ +#define ECAP_IC1 (1UL) /*!< ECAP IC1 Unit \hideinitializer */ +#define ECAP_IC2 (2UL) /*!< ECAP IC2 Unit \hideinitializer */ + +/*---------------------------------------------------------------------------------------------------------*/ +/* ECAP CTL0 constant definitions */ +/*---------------------------------------------------------------------------------------------------------*/ +#define ECAP_NOISE_FILTER_CLKDIV_1 (0UL<CTL0 = ((ecap)->CTL0 & ~ECAP_CTL0_NFCLKSEL_Msk)|(u32ClkSel)) + +/** + * @brief This macro is used to disable noise filter + * @param[in] ecap Specify ECAP port + * @return None + * @details This macro will disable the noise filter of input capture. + * \hideinitializer + */ +#define ECAP_NOISE_FILTER_DISABLE(ecap) ((ecap)->CTL0 |= ECAP_CTL0_CAPNFDIS_Msk) + +/** + * @brief This macro is used to enable noise filter + * @param[in] ecap Specify ECAP port + * @param[in] u32ClkSel Select noise filter clock divide number + * - \ref ECAP_NOISE_FILTER_CLKDIV_1 + * - \ref ECAP_NOISE_FILTER_CLKDIV_2 + * - \ref ECAP_NOISE_FILTER_CLKDIV_4 + * - \ref ECAP_NOISE_FILTER_CLKDIV_16 + * - \ref ECAP_NOISE_FILTER_CLKDIV_32 + * - \ref ECAP_NOISE_FILTER_CLKDIV_64 + * @return None + * @details This macro will enable the noise filter of input capture and set noise filter clock divide. + * \hideinitializer + */ +#define ECAP_NOISE_FILTER_ENABLE(ecap, u32ClkSel) ((ecap)->CTL0 = ((ecap)->CTL0 & ~(ECAP_CTL0_CAPNFDIS_Msk|ECAP_CTL0_NFCLKSEL_Msk))|(u32ClkSel)) + +/** + * @brief This macro is used to enable input channel unit + * @param[in] ecap Specify ECAP port + * @param[in] u32Mask The input channel mask + * - \ref ECAP_CTL0_IC0EN_Msk + * - \ref ECAP_CTL0_IC1EN_Msk + * - \ref ECAP_CTL0_IC2EN_Msk + * @return None + * @details This macro will enable the input channel_n to input capture. + * \hideinitializer + */ +#define ECAP_ENABLE_INPUT_CHANNEL(ecap, u32Mask) ((ecap)->CTL0 |= (u32Mask)) + +/** + * @brief This macro is used to disable input channel unit + * @param[in] ecap Specify ECAP port + * @param[in] u32Mask The input channel mask + * - \ref ECAP_CTL0_IC0EN_Msk + * - \ref ECAP_CTL0_IC1EN_Msk + * - \ref ECAP_CTL0_IC2EN_Msk + * @return None + * @details This macro will disable the input channel_n to input capture. + * \hideinitializer + */ +#define ECAP_DISABLE_INPUT_CHANNEL(ecap, u32Mask) ((ecap)->CTL0 &= ~(u32Mask)) + +/** + * @brief This macro is used to select input channel source + * @param[in] ecap Specify ECAP port + * @param[in] u32Index The input channel number + * - \ref ECAP_IC0 + * - \ref ECAP_IC1 + * - \ref ECAP_IC2 + * @param[in] u32Src The input source + * - \ref ECAP_CAP_INPUT_SRC_FROM_IC + * - \ref ECAP_CAP_INPUT_SRC_FROM_CH + * @return None + * @details This macro will select the input source from ICx, CHx. + * \hideinitializer + */ +#define ECAP_SEL_INPUT_SRC(ecap, u32Index, u32Src) ((ecap)->CTL0 = ((ecap)->CTL0 & ~(ECAP_CTL0_CAPSEL0_Msk<<((u32Index)<<1)))|(((u32Src)<CTL0 |= (u32Mask)) + +/** + * @brief This macro is used to disable input channel interrupt + * @param[in] ecap Specify ECAP port + * @param[in] u32Mask The input channel mask + * - \ref ECAP_IC0 + * - \ref ECAP_IC1 + * - \ref ECAP_IC2 + * @return None + * @details This macro will disable the input channel_n interrupt. + * \hideinitializer + */ +#define ECAP_DISABLE_INT(ecap, u32Mask) ((ecap)->CTL0 &= ~(u32Mask)) + +/** + * @brief This macro is used to enable input channel overflow interrupt + * @param[in] ecap Specify ECAP port + * @return None + * @details This macro will enable the input channel overflow interrupt. + * \hideinitializer + */ +#define ECAP_ENABLE_OVF_INT(ecap) ((ecap)->CTL0 |= ECAP_CTL0_OVIEN_Msk) + +/** + * @brief This macro is used to disable input channel overflow interrupt + * @param[in] ecap Specify ECAP port + * @return None + * @details This macro will disable the input channel overflow interrupt. + * \hideinitializer + */ +#define ECAP_DISABLE_OVF_INT(ecap) ((ecap)->CTL0 &= ~ECAP_CTL0_OVIEN_Msk) + +/** + * @brief This macro is used to enable input channel compare-match interrupt + * @param[in] ecap Specify ECAP port + * @return None + * @details This macro will enable the input channel compare-match interrupt. + * \hideinitializer + */ +#define ECAP_ENABLE_CMP_MATCH_INT(ecap) ((ecap)->CTL0 |= ECAP_CTL0_CMPIEN_Msk) + +/** + * @brief This macro is used to disable input channel compare-match interrupt + * @param[in] ecap Specify ECAP port + * @return None + * @details This macro will disable the input channel compare-match interrupt. + * \hideinitializer + */ +#define ECAP_DISABLE_CMP_MATCH_INT(ecap) ((ecap)->CTL0 &= ~ECAP_CTL0_CMPIEN_Msk) + +/** + * @brief This macro is used to start capture counter + * @param[in] ecap Specify ECAP port + * @return None + * @details This macro will start capture counter up-counting. + * \hideinitializer + */ +#define ECAP_CNT_START(ecap) ((ecap)->CTL0 |= ECAP_CTL0_CNTEN_Msk) + +/** + * @brief This macro is used to stop capture counter + * @param[in] ecap Specify ECAP port + * @return None + * @details This macro will stop capture counter up-counting. + * \hideinitializer + */ +#define ECAP_CNT_STOP(ecap) ((ecap)->CTL0 &= ~ECAP_CTL0_CNTEN_Msk) + +/** + * @brief This macro is used to set event to clear capture counter + * @param[in] ecap Specify ECAP port + * @param[in] u32Event The input channel number + * - \ref ECAP_CTL1_CAP0CLREN_Msk + * - \ref ECAP_CTL1_CAP1CLREN_Msk + * - \ref ECAP_CTL1_CAP2CLREN_Msk + * @return None + * @details This macro will enable and select compare or capture event that can clear capture counter. + * \hideinitializer + */ +#define ECAP_SET_CNT_CLEAR_EVENT(ecap, u32Event) do{ \ + if((u32Event) & ECAP_CTL0_CMPCLREN_Msk) \ + (ecap)->CTL0 |= ECAP_CTL0_CMPCLREN_Msk; \ + else \ + (ecap)->CTL0 &= ~ECAP_CTL0_CMPCLREN_Msk; \ + (ecap)->CTL1 = ((ecap)->CTL1 &~0x700000) | ((u32Event) & 0x700000); \ + }while(0); + +/** + * @brief This macro is used to enable compare function + * @param[in] ecap Specify ECAP port + * @return None + * @details This macro will enable the compare function. + * \hideinitializer + */ +#define ECAP_ENABLE_CMP(ecap) ((ecap)->CTL0 |= ECAP_CTL0_CMPEN_Msk) + +/** + * @brief This macro is used to disable compare function + * @param[in] ecap Specify ECAP port + * @return None + * @details This macro will disable the compare function. + * \hideinitializer + */ +#define ECAP_DISABLE_CMP(ecap) ((ecap)->CTL0 &= ~ECAP_CTL0_CMPEN_Msk) + +/** + * @brief This macro is used to enable input capture function. + * @param[in] ecap Specify ECAP port + * @return None + * @details This macro will enable input capture timer/counter. + * \hideinitializer + */ +#define ECAP_ENABLE_CNT(ecap) ((ecap)->CTL0 |= ECAP_CTL0_CAPEN_Msk) + +/** + * @brief This macro is used to disable input capture function. + * @param[in] ecap Specify ECAP port + * @return None + * @details This macro will disable input capture timer/counter. + * \hideinitializer + */ +#define ECAP_DISABLE_CNT(ecap) ((ecap)->CTL0 &= ~ECAP_CTL0_CAPEN_Msk) + +/** + * @brief This macro is used to select input channel edge detection + * @param[in] ecap Specify ECAP port + * @param[in] u32Index The input channel number + * - \ref ECAP_IC0 + * - \ref ECAP_IC1 + * - \ref ECAP_IC2 + * @param[in] u32Edge The input source + * - \ref ECAP_RISING_EDGE + * - \ref ECAP_FALLING_EDGE + * - \ref ECAP_RISING_FALLING_EDGE + * @return None + * @details This macro will select input capture can detect falling edge, rising edge or either rising or falling edge change. + * \hideinitializer + */ +#define ECAP_SEL_CAPTURE_EDGE(ecap, u32Index, u32Edge) ((ecap)->CTL1 = ((ecap)->CTL1 & ~(ECAP_CTL1_EDGESEL0_Msk<<((u32Index)<<1)))|((u32Edge)<<((u32Index)<<1))) + +/** + * @brief This macro is used to select ECAP counter reload trigger source + * @param[in] ecap Specify ECAP port + * @param[in] u32TrigSrc The input source + * - \ref ECAP_CTL1_CAP0RLDEN_Msk + * - \ref ECAP_CTL1_CAP1RLDEN_Msk + * - \ref ECAP_CTL1_CAP2RLDEN_Msk + * - \ref ECAP_CTL1_OVRLDEN_Msk + * @return None + * @details This macro will select capture counter reload trigger source. + * \hideinitializer + */ +#define ECAP_SEL_RELOAD_TRIG_SRC(ecap, u32TrigSrc) ((ecap)->CTL1 = ((ecap)->CTL1 & ~0xF00)|(u32TrigSrc)) + +/** + * @brief This macro is used to select capture timer clock divide. + * @param[in] ecap Specify ECAP port + * @param[in] u32Clkdiv The input source + * - \ref ECAP_CAPTURE_TIMER_CLKDIV_1 + * - \ref ECAP_CAPTURE_TIMER_CLKDIV_4 + * - \ref ECAP_CAPTURE_TIMER_CLKDIV_16 + * - \ref ECAP_CAPTURE_TIMER_CLKDIV_32 + * - \ref ECAP_CAPTURE_TIMER_CLKDIV_64 + * - \ref ECAP_CAPTURE_TIMER_CLKDIV_96 + * - \ref ECAP_CAPTURE_TIMER_CLKDIV_112 + * - \ref ECAP_CAPTURE_TIMER_CLKDIV_128 + * @return None + * @details This macro will select capture timer clock has a pre-divider with eight divided option. + * \hideinitializer + */ +#define ECAP_SEL_TIMER_CLK_DIV(ecap, u32Clkdiv) ((ecap)->CTL1 = ((ecap)->CTL1 & ~ECAP_CTL1_CLKSEL_Msk)|(u32Clkdiv)) + +/** + * @brief This macro is used to select capture timer/counter clock source + * @param[in] ecap Specify ECAP port + * @param[in] u32ClkSrc The input source + * - \ref ECAP_CAPTURE_TIMER_CLK_SRC_CAP_CLK + * - \ref ECAP_CAPTURE_TIMER_CLK_SRC_CAP0 + * - \ref ECAP_CAPTURE_TIMER_CLK_SRC_CAP1 + * - \ref ECAP_CAPTURE_TIMER_CLK_SRC_CAP2 + * @return None + * @details This macro will select capture timer/clock clock source. + * \hideinitializer + */ +#define ECAP_SEL_TIMER_CLK_SRC(ecap, u32ClkSrc) ((ecap)->CTL1 = ((ecap)->CTL1 & ~ECAP_CTL1_CNTSRCSEL_Msk)|(u32ClkSrc)) + +/** + * @brief This macro is used to read input capture status + * @param[in] ecap Specify ECAP port + * @return Input capture status flags + * @details This macro will get the input capture interrupt status. + * \hideinitializer + */ +#define ECAP_GET_INT_STATUS(ecap) ((ecap)->STATUS) + +/** + * @brief This macro is used to get input channel interrupt flag + * @param[in] ecap Specify ECAP port + * @param[in] u32Mask The input channel mask + * - \ref ECAP_STATUS_CAPTF0_Msk + * - \ref ECAP_STATUS_CAPTF1_Msk + * - \ref ECAP_STATUS_CAPTF2_Msk + * - \ref ECAP_STATUS_CAPOVF_Msk + * - \ref ECAP_STATUS_CAPCMPF_Msk + * @return None + * @details This macro will write 1 to get the input channel_n interrupt flag. + * \hideinitializer + */ +#define ECAP_GET_CAPTURE_FLAG(ecap, u32Mask) (((ecap)->STATUS & (u32Mask))?1:0) + +/** + * @brief This macro is used to clear input channel interrupt flag + * @param[in] ecap Specify ECAP port + * @param[in] u32Mask The input channel mask + * - \ref ECAP_STATUS_CAPTF0_Msk + * - \ref ECAP_STATUS_CAPTF1_Msk + * - \ref ECAP_STATUS_CAPTF2_Msk + * - \ref ECAP_STATUS_CAPOVF_Msk + * - \ref ECAP_STATUS_CAPCMPF_Msk + * @return None + * @details This macro will write 1 to clear the input channel_n interrupt flag. + * \hideinitializer + */ +#define ECAP_CLR_CAPTURE_FLAG(ecap, u32Mask) ((ecap)->STATUS = (u32Mask)) + +/** + * @brief This macro is used to set input capture counter value + * @param[in] ecap Specify ECAP port + * @param[in] u32Val Counter value + * @return None + * @details This macro will set a counter value of input capture. + * \hideinitializer + */ +#define ECAP_SET_CNT_VALUE(ecap, u32Val) ((ecap)->CNT = (u32Val)) + +/** + * @brief This macro is used to get input capture counter value + * @param[in] ecap Specify ECAP port + * @return Capture counter value + * @details This macro will get a counter value of input capture. + * \hideinitializer + */ +#define ECAP_GET_CNT_VALUE(ecap) ((ecap)->CNT) + +/** + * @brief This macro is used to get input capture counter hold value + * @param[in] ecap Specify ECAP port + * @param[in] u32Index The input channel number + * - \ref ECAP_IC0 + * - \ref ECAP_IC1 + * - \ref ECAP_IC2 + * @return Capture counter hold value + * @details This macro will get a hold value of input capture channel_n. + * \hideinitializer + */ +#define ECAP_GET_CNT_HOLD_VALUE(ecap, u32Index) (*(__IO uint32_t *) (&((ecap)->HLD0) + (u32Index))) + +/** + * @brief This macro is used to set input capture counter compare value + * @param[in] ecap Specify ECAP port + * @param[in] u32Val Input capture compare value + * @return None + * @details This macro will set a compare value of input capture counter. + * \hideinitializer + */ +#define ECAP_SET_CNT_CMP(ecap, u32Val) ((ecap)->CNTCMP = (u32Val)) + +void ECAP_Open(ECAP_T *ecap, uint32_t u32FuncMask); +void ECAP_Close(ECAP_T *ecap); +void ECAP_EnableINT(ECAP_T *ecap, uint32_t u32Mask); +void ECAP_DisableINT(ECAP_T *ecap, uint32_t u32Mask); +/*@}*/ /* end of group ECAP_EXPORTED_FUNCTIONS */ + +/*@}*/ /* end of group ECAP_Driver */ + +/*@}*/ /* end of group Standard_Driver */ + +#ifdef __cplusplus +} +#endif + +#endif /* __NU_ECAP_H__ */ + diff --git a/bsp/nuvoton/libraries/ma35/StdDriver/inc/nu_epwm.h b/bsp/nuvoton/libraries/ma35/StdDriver/inc/nu_epwm.h new file mode 100644 index 0000000000..261ec688e3 --- /dev/null +++ b/bsp/nuvoton/libraries/ma35/StdDriver/inc/nu_epwm.h @@ -0,0 +1,643 @@ +/**************************************************************************//** + * @file nu_epwm.h + * @brief EPWM driver header file + * + * SPDX-License-Identifier: Apache-2.0 + * @copyright (C) 2020 Nuvoton Technology Corp. All rights reserved. + *****************************************************************************/ +#ifndef __NU_EPWM_H__ +#define __NU_EPWM_H__ + +#ifdef __cplusplus +extern "C" +{ +#endif + + +/** @addtogroup Standard_Driver Standard Driver + @{ +*/ + +/** @addtogroup EPWM_Driver EPWM Driver + @{ +*/ + +/** @addtogroup EPWM_EXPORTED_CONSTANTS EPWM Exported Constants + @{ +*/ +#define EPWM_CHANNEL_NUM (6U) /*!< EPWM channel number \hideinitializer */ +#define EPWM_CH_0_MASK (0x1U) /*!< EPWM channel 0 mask \hideinitializer */ +#define EPWM_CH_1_MASK (0x2U) /*!< EPWM channel 1 mask \hideinitializer */ +#define EPWM_CH_2_MASK (0x4U) /*!< EPWM channel 2 mask \hideinitializer */ +#define EPWM_CH_3_MASK (0x8U) /*!< EPWM channel 3 mask \hideinitializer */ +#define EPWM_CH_4_MASK (0x10U) /*!< EPWM channel 4 mask \hideinitializer */ +#define EPWM_CH_5_MASK (0x20U) /*!< EPWM channel 5 mask \hideinitializer */ + +/*---------------------------------------------------------------------------------------------------------*/ +/* Counter Type Constant Definitions */ +/*---------------------------------------------------------------------------------------------------------*/ +#define EPWM_UP_COUNTER (0U) /*!< Up counter type \hideinitializer */ +#define EPWM_DOWN_COUNTER (1U) /*!< Down counter type \hideinitializer */ +#define EPWM_UP_DOWN_COUNTER (2U) /*!< Up-Down counter type \hideinitializer */ + +/*---------------------------------------------------------------------------------------------------------*/ +/* Aligned Type Constant Definitions */ +/*---------------------------------------------------------------------------------------------------------*/ +#define EPWM_EDGE_ALIGNED (1U) /*!< EPWM working in edge aligned type(down count) \hideinitializer */ +#define EPWM_CENTER_ALIGNED (2U) /*!< EPWM working in center aligned type \hideinitializer */ + +/*---------------------------------------------------------------------------------------------------------*/ +/* Output Level Constant Definitions */ +/*---------------------------------------------------------------------------------------------------------*/ +#define EPWM_OUTPUT_NOTHING (0U) /*!< EPWM output nothing \hideinitializer */ +#define EPWM_OUTPUT_LOW (1U) /*!< EPWM output low \hideinitializer */ +#define EPWM_OUTPUT_HIGH (2U) /*!< EPWM output high \hideinitializer */ +#define EPWM_OUTPUT_TOGGLE (3U) /*!< EPWM output toggle \hideinitializer */ + +/*---------------------------------------------------------------------------------------------------------*/ +/* Synchronous Start Function Control Constant Definitions */ +/*---------------------------------------------------------------------------------------------------------*/ +#define EPWM_SSCTL_SSRC_EPWM0 (0U<CTL1 = (epwm)->CTL1 | (0x7ul<CTL1 = (epwm)->CTL1 & ~(0x7ul<CTL0 = (epwm)->CTL0 | EPWM_CTL0_GROUPEN_Msk) + +/** + * @brief This macro disable group mode + * @param[in] epwm The pointer of the specified EPWM module + * @return None + * @details This macro is used to disable group mode of EPWM module. + * \hideinitializer + */ +#define EPWM_DISABLE_GROUP_MODE(epwm) ((epwm)->CTL0 = (epwm)->CTL0 & ~EPWM_CTL0_GROUPEN_Msk) + +/** + * @brief Enable timer synchronous start counting function of specified channel(s) + * @param[in] epwm The pointer of the specified EPWM module + * @param[in] u32ChannelMask Combination of enabled channels. Each bit corresponds to a channel + * Bit 0 represents channel 0, bit 1 represents channel 1... + * @param[in] u32SyncSrc Synchronous start source selection, valid values are: + * - \ref EPWM_SSCTL_SSRC_EPWM0 + * - \ref EPWM_SSCTL_SSRC_EPWM1 + * - \ref EPWM_SSCTL_SSRC_BPWM0 + * - \ref EPWM_SSCTL_SSRC_BPWM1 + * @return None + * @details This macro is used to enable timer synchronous start counting function of specified channel(s). + * \hideinitializer + */ +#define EPWM_ENABLE_TIMER_SYNC(epwm, u32ChannelMask, u32SyncSrc) ((epwm)->SSCTL = ((epwm)->SSCTL & ~EPWM_SSCTL_SSRC_Msk) | (u32SyncSrc) | (u32ChannelMask)) + +/** + * @brief Disable timer synchronous start counting function of specified channel(s) + * @param[in] epwm The pointer of the specified EPWM module + * @param[in] u32ChannelMask Combination of enabled channels. Each bit corresponds to a channel + * Bit 0 represents channel 0, bit 1 represents channel 1... + * @return None + * @details This macro is used to disable timer synchronous start counting function of specified channel(s). + * \hideinitializer + */ +#define EPWM_DISABLE_TIMER_SYNC(epwm, u32ChannelMask) \ + do{ \ + int i;\ + for(i = 0; i < 6; i++) { \ + if((u32ChannelMask) & (1 << i)) \ + (epwm)->SSCTL &= ~(1UL << i); \ + } \ + }while(0) + +/** + * @brief This macro enable EPWM counter synchronous start counting function. + * @param[in] epwm The pointer of the specified EPWM module + * @return None + * @details This macro is used to make selected EPWM0 and EPWM1 channel(s) start counting at the same time. + * To configure synchronous start counting channel(s) by EPWM_ENABLE_TIMER_SYNC() and EPWM_DISABLE_TIMER_SYNC(). + * \hideinitializer + */ +#define EPWM_TRIGGER_SYNC_START(epwm) ((epwm)->SSTRG = EPWM_SSTRG_CNTSEN_Msk) + +/** + * @brief This macro enable output inverter of specified channel(s) + * @param[in] epwm The pointer of the specified EPWM module + * @param[in] u32ChannelMask Combination of enabled channels. Each bit corresponds to a channel + * Bit 0 represents channel 0, bit 1 represents channel 1... + * @return None + * @details This macro is used to enable output inverter of specified channel(s). + * \hideinitializer + */ +#define EPWM_ENABLE_OUTPUT_INVERTER(epwm, u32ChannelMask) ((epwm)->POLCTL = (u32ChannelMask)) + +/** + * @brief This macro get captured rising data + * @param[in] epwm The pointer of the specified EPWM module + * @param[in] u32ChannelNum EPWM channel number. Valid values are between 0~5 + * @return None + * @details This macro is used to get captured rising data of specified channel. + * \hideinitializer + */ +#define EPWM_GET_CAPTURE_RISING_DATA(epwm, u32ChannelNum) ((epwm)->CAPDAT[(u32ChannelNum)].RCAPDAT) + +/** + * @brief This macro get captured falling data + * @param[in] epwm The pointer of the specified EPWM module + * @param[in] u32ChannelNum EPWM channel number. Valid values are between 0~5 + * @return None + * @details This macro is used to get captured falling data of specified channel. + * \hideinitializer + */ +#define EPWM_GET_CAPTURE_FALLING_DATA(epwm, u32ChannelNum) ((epwm)->CAPDAT[(u32ChannelNum)].FCAPDAT) + +/** + * @brief This macro mask output logic to high or low + * @param[in] epwm The pointer of the specified EPWM module + * @param[in] u32ChannelMask Combination of enabled channels. Each bit corresponds to a channel + * Bit 0 represents channel 0, bit 1 represents channel 1... + * @param[in] u32LevelMask Output logic to high or low + * @return None + * @details This macro is used to mask output logic to high or low of specified channel(s). + * @note If u32ChannelMask parameter is 0, then mask function will be disabled. + * \hideinitializer + */ +#define EPWM_MASK_OUTPUT(epwm, u32ChannelMask, u32LevelMask) \ + { \ + (epwm)->MSKEN = (u32ChannelMask); \ + (epwm)->MSK = (u32LevelMask); \ + } + +/** + * @brief This macro set the prescaler of the selected channel + * @param[in] epwm The pointer of the specified EPWM module + * @param[in] u32ChannelNum EPWM channel number. Valid values are between 0~5 + * @param[in] u32Prescaler Clock prescaler of specified channel. Valid values are between 0 ~ 0xFFF + * @return None + * @details This macro is used to set the prescaler of specified channel. + * @note Every even channel N, and channel (N + 1) share a prescaler. So if channel 0 prescaler changed, channel 1 will also be affected. + * The clock of EPWM counter is divided by (u32Prescaler + 1). + * \hideinitializer + */ +#define EPWM_SET_PRESCALER(epwm, u32ChannelNum, u32Prescaler) ((epwm)->CLKPSC[(u32ChannelNum) >> 1] = (u32Prescaler)) + +/** + * @brief This macro get the prescaler of the selected channel + * @param[in] epwm The pointer of the specified EPWM module + * @param[in] u32ChannelNum EPWM channel number. Valid values are between 0~5 + * @return Return Clock prescaler of specified channel. Valid values are between 0 ~ 0xFFF + * @details This macro is used to get the prescaler of specified channel. + * @note Every even channel N, and channel (N + 1) share a prescaler. So if channel 0 prescaler changed, channel 1 will also be affected. + * The clock of EPWM counter is divided by (u32Prescaler + 1). + * \hideinitializer + */ +#define EPWM_GET_PRESCALER(epwm, u32ChannelNum) ((epwm)->CLKPSC[(u32ChannelNum) >> 1U]) + +/** + * @brief This macro set the comparator of the selected channel + * @param[in] epwm The pointer of the specified EPWM module + * @param[in] u32ChannelNum EPWM channel number. Valid values are between 0~5 + * @param[in] u32CMR Comparator of specified channel. Valid values are between 0~0xFFFF + * @return None + * @details This macro is used to set the comparator of specified channel. + * @note This new setting will take effect on next EPWM period. + * \hideinitializer + */ +#define EPWM_SET_CMR(epwm, u32ChannelNum, u32CMR) ((epwm)->CMPDAT[(u32ChannelNum)]= (u32CMR)) + +/** + * @brief This macro get the comparator of the selected channel + * @param[in] epwm The pointer of the specified EPWM module + * @param[in] u32ChannelNum EPWM channel number. Valid values are between 0~5 + * @return Return the comparator of specified channel. Valid values are between 0~0xFFFF + * @details This macro is used to get the comparator of specified channel. + * \hideinitializer + */ +#define EPWM_GET_CMR(epwm, u32ChannelNum) ((epwm)->CMPDAT[(u32ChannelNum)]) + +/** + * @brief This macro set the free trigger comparator of the selected channel + * @param[in] epwm The pointer of the specified EPWM module + * @param[in] u32ChannelNum EPWM channel number. Valid values are between 0~5 + * @param[in] u32FTCMR Free trigger comparator of specified channel. Valid values are between 0~0xFFFF + * @return None + * @details This macro is used to set the free trigger comparator of specified channel. + * @note This new setting will take effect on next EPWM period. + * \hideinitializer + */ +#define EPWM_SET_FTCMR(epwm, u32ChannelNum, u32FTCMR) (((epwm)->FTCMPDAT[((u32ChannelNum) >> 1U)]) = (u32FTCMR)) + +/** + * @brief This macro set the period of the selected channel + * @param[in] epwm The pointer of the specified EPWM module + * @param[in] u32ChannelNum EPWM channel number. Valid values are between 0~5 + * @param[in] u32CNR Period of specified channel. Valid values are between 0~0xFFFF + * @return None + * @details This macro is used to set the period of specified channel. + * @note This new setting will take effect on next EPWM period. + * @note EPWM counter will stop if period length set to 0. + * \hideinitializer + */ +#define EPWM_SET_CNR(epwm, u32ChannelNum, u32CNR) ((epwm)->PERIOD[(u32ChannelNum)] = (u32CNR)) + +/** + * @brief This macro get the period of the selected channel + * @param[in] epwm The pointer of the specified EPWM module + * @param[in] u32ChannelNum EPWM channel number. Valid values are between 0~5 + * @return Return the period of specified channel. Valid values are between 0~0xFFFF + * @details This macro is used to get the period of specified channel. + * \hideinitializer + */ +#define EPWM_GET_CNR(epwm, u32ChannelNum) ((epwm)->PERIOD[(u32ChannelNum)]) + +/** + * @brief This macro set the EPWM aligned type + * @param[in] epwm The pointer of the specified EPWM module + * @param[in] u32ChannelMask Combination of enabled channels. Each bit corresponds to a channel + * Bit 0 represents channel 0, bit 1 represents channel 1... + * @param[in] u32AlignedType EPWM aligned type, valid values are: + * - \ref EPWM_EDGE_ALIGNED + * - \ref EPWM_CENTER_ALIGNED + * @return None + * @details This macro is used to set the EPWM aligned type of specified channel(s). + * \hideinitializer + */ +#define EPWM_SET_ALIGNED_TYPE(epwm, u32ChannelMask, u32AlignedType) \ + do{ \ + int i; \ + for(i = 0; i < 6; i++) { \ + if((u32ChannelMask) & (1 << i)) \ + (epwm)->CTL1 = (((epwm)->CTL1 & ~(3UL << (i << 1))) | ((u32AlignedType) << (i << 1))); \ + } \ + }while(0) + +/** + * @brief Set load window of window loading mode for specified channel(s) + * @param[in] epwm The pointer of the specified EPWM module + * @param[in] u32ChannelMask Combination of enabled channels. Each bit corresponds to a channel + * Bit 0 represents channel 0, bit 1 represents channel 1... + * @return None + * @details This macro is used to set load window of window loading mode for specified channel(s). + * \hideinitializer + */ +#define EPWM_SET_LOAD_WINDOW(epwm, u32ChannelMask) ((epwm)->LOAD |= (u32ChannelMask)) + +/** + * @brief Trigger synchronous event from specified channel(s) + * @param[in] epwm The pointer of the specified EPWM module + * @param[in] u32ChannelNum EPWM channel number. Valid values are 0, 2, 4 + * Bit 0 represents channel 0, bit 1 represents channel 2 and bit 2 represents channel 4 + * @return None + * @details This macro is used to trigger synchronous event from specified channel(s). + * \hideinitializer + */ +#define EPWM_TRIGGER_SYNC(epwm, u32ChannelNum) ((epwm)->SWSYNC |= (1 << ((u32ChannelNum) >> 1))) + +/** + * @brief Clear counter of specified channel(s) + * @param[in] epwm The pointer of the specified EPWM module + * @param[in] u32ChannelMask Combination of enabled channels. Each bit corresponds to a channel + * Bit 0 represents channel 0, bit 1 represents channel 1... + * @return None + * @details This macro is used to clear counter of specified channel(s). + * \hideinitializer + */ +#define EPWM_CLR_COUNTER(epwm, u32ChannelMask) ((epwm)->CNTCLR |= (u32ChannelMask)) + +/** + * @brief Set output level at zero, compare up, period(center) and compare down of specified channel(s) + * @param[in] epwm The pointer of the specified EPWM module + * @param[in] u32ChannelMask Combination of enabled channels. Each bit corresponds to a channel + * Bit 0 represents channel 0, bit 1 represents channel 1... + * @param[in] u32ZeroLevel output level at zero point, valid values are: + * - \ref EPWM_OUTPUT_NOTHING + * - \ref EPWM_OUTPUT_LOW + * - \ref EPWM_OUTPUT_HIGH + * - \ref EPWM_OUTPUT_TOGGLE + * @param[in] u32CmpUpLevel output level at compare up point, valid values are: + * - \ref EPWM_OUTPUT_NOTHING + * - \ref EPWM_OUTPUT_LOW + * - \ref EPWM_OUTPUT_HIGH + * - \ref EPWM_OUTPUT_TOGGLE + * @param[in] u32PeriodLevel output level at period(center) point, valid values are: + * - \ref EPWM_OUTPUT_NOTHING + * - \ref EPWM_OUTPUT_LOW + * - \ref EPWM_OUTPUT_HIGH + * - \ref EPWM_OUTPUT_TOGGLE + * @param[in] u32CmpDownLevel output level at compare down point, valid values are: + * - \ref EPWM_OUTPUT_NOTHING + * - \ref EPWM_OUTPUT_LOW + * - \ref EPWM_OUTPUT_HIGH + * - \ref EPWM_OUTPUT_TOGGLE + * @return None + * @details This macro is used to Set output level at zero, compare up, period(center) and compare down of specified channel(s). + * \hideinitializer + */ +#define EPWM_SET_OUTPUT_LEVEL(epwm, u32ChannelMask, u32ZeroLevel, u32CmpUpLevel, u32PeriodLevel, u32CmpDownLevel) \ + do{ \ + int i; \ + for(i = 0; i < 6; i++) { \ + if((u32ChannelMask) & (1 << i)) { \ + (epwm)->WGCTL0 = (((epwm)->WGCTL0 & ~(3UL << (i << 1))) | ((u32ZeroLevel) << (i << 1))); \ + (epwm)->WGCTL0 = (((epwm)->WGCTL0 & ~(3UL << (EPWM_WGCTL0_PRDPCTL0_Pos + (i << 1)))) | ((u32PeriodLevel) << (EPWM_WGCTL0_PRDPCTL0_Pos + (i << 1)))); \ + (epwm)->WGCTL1 = (((epwm)->WGCTL1 & ~(3UL << (i << 1))) | ((u32CmpUpLevel) << (i << 1))); \ + (epwm)->WGCTL1 = (((epwm)->WGCTL1 & ~(3UL << (EPWM_WGCTL1_CMPDCTL0_Pos + (i << 1)))) | ((u32CmpDownLevel) << (EPWM_WGCTL1_CMPDCTL0_Pos + (i << 1)))); \ + } \ + } \ + }while(0) + +/** + * @brief Trigger brake event from specified channel(s) + * @param[in] epwm The pointer of the specified EPWM module + * @param[in] u32ChannelMask Combination of enabled channels. Each bit corresponds to a channel + * Bit 0 represents channel 0, bit 1 represents channel 2 and bit 2 represents channel 4 + * @param[in] u32BrakeType Type of brake trigger. + * - \ref EPWM_FB_EDGE + * - \ref EPWM_FB_LEVEL + * @return None + * @details This macro is used to trigger brake event from specified channel(s). + * \hideinitializer + */ +#define EPWM_TRIGGER_BRAKE(epwm, u32ChannelMask, u32BrakeType) ((epwm)->SWBRK |= ((u32ChannelMask) << (u32BrakeType))) + +/** + * @brief Set Dead zone clock source + * @param[in] epwm The pointer of the specified EPWM module + * @param[in] u32ChannelNum EPWM channel number. Valid values are between 0~5 + * @param[in] u32AfterPrescaler Dead zone clock source is from prescaler output. Valid values are TRUE (after prescaler) or FALSE (before prescaler). + * @return None + * @details This macro is used to set Dead zone clock source. Every two channels share the same setting. + * @note The write-protection function should be disabled before using this function. + * \hideinitializer + */ +#define EPWM_SET_DEADZONE_CLK_SRC(epwm, u32ChannelNum, u32AfterPrescaler) \ + ((epwm)->DTCTL[(u32ChannelNum) >> 1] = (((epwm)->DTCTL[(u32ChannelNum) >> 1] & ~EPWM_DTCTL0_1_DTCKSEL_Msk) | \ + ((u32AfterPrescaler) << EPWM_DTCTL0_1_DTCKSEL_Pos))) + +/*---------------------------------------------------------------------------------------------------------*/ +/* Define EPWM functions prototype */ +/*---------------------------------------------------------------------------------------------------------*/ +uint32_t EPWM_ConfigCaptureChannel(EPWM_T *epwm, uint32_t u32ChannelNum, uint32_t u32UnitTimeNsec, uint32_t u32CaptureEdge); +uint32_t EPWM_ConfigOutputChannel(EPWM_T *epwm, uint32_t u32ChannelNum, uint32_t u32Frequency, uint32_t u32DutyCycle); +void EPWM_Start(EPWM_T *epwm, uint32_t u32ChannelMask); +void EPWM_Stop(EPWM_T *epwm, uint32_t u32ChannelMask); +void EPWM_ForceStop(EPWM_T *epwm, uint32_t u32ChannelMask); +void EPWM_EnableADCTrigger(EPWM_T *epwm, uint32_t u32ChannelNum, uint32_t u32Condition); +void EPWM_DisableADCTrigger(EPWM_T *epwm, uint32_t u32ChannelNum); +int32_t EPWM_EnableADCTriggerPrescale(EPWM_T *epwm, uint32_t u32ChannelNum, uint32_t u32Prescale, uint32_t u32PrescaleCnt); +void EPWM_DisableADCTriggerPrescale(EPWM_T *epwm, uint32_t u32ChannelNum); +void EPWM_ClearADCTriggerFlag(EPWM_T *epwm, uint32_t u32ChannelNum, uint32_t u32Condition); +uint32_t EPWM_GetADCTriggerFlag(EPWM_T *epwm, uint32_t u32ChannelNum); +void EPWM_EnableDACTrigger(EPWM_T *epwm, uint32_t u32ChannelNum, uint32_t u32Condition); +void EPWM_DisableDACTrigger(EPWM_T *epwm, uint32_t u32ChannelNum); +void EPWM_ClearDACTriggerFlag(EPWM_T *epwm, uint32_t u32ChannelNum, uint32_t u32Condition); +uint32_t EPWM_GetDACTriggerFlag(EPWM_T *epwm, uint32_t u32ChannelNum); +void EPWM_EnableFaultBrake(EPWM_T *epwm, uint32_t u32ChannelMask, uint32_t u32LevelMask, uint32_t u32BrakeSource); +void EPWM_EnableCapture(EPWM_T *epwm, uint32_t u32ChannelMask); +void EPWM_DisableCapture(EPWM_T *epwm, uint32_t u32ChannelMask); +void EPWM_EnableOutput(EPWM_T *epwm, uint32_t u32ChannelMask); +void EPWM_DisableOutput(EPWM_T *epwm, uint32_t u32ChannelMask); +void EPWM_EnablePDMA(EPWM_T *epwm, uint32_t u32ChannelNum, uint32_t u32RisingFirst, uint32_t u32Mode); +void EPWM_DisablePDMA(EPWM_T *epwm, uint32_t u32ChannelNum); +void EPWM_EnableDeadZone(EPWM_T *epwm, uint32_t u32ChannelNum, uint32_t u32Duration); +void EPWM_DisableDeadZone(EPWM_T *epwm, uint32_t u32ChannelNum); +void EPWM_EnableCaptureInt(EPWM_T *epwm, uint32_t u32ChannelNum, uint32_t u32Edge); +void EPWM_DisableCaptureInt(EPWM_T *epwm, uint32_t u32ChannelNum, uint32_t u32Edge); +void EPWM_ClearCaptureIntFlag(EPWM_T *epwm, uint32_t u32ChannelNum, uint32_t u32Edge); +uint32_t EPWM_GetCaptureIntFlag(EPWM_T *epwm, uint32_t u32ChannelNum); +void EPWM_EnableDutyInt(EPWM_T *epwm, uint32_t u32ChannelNum, uint32_t u32IntDutyType); +void EPWM_DisableDutyInt(EPWM_T *epwm, uint32_t u32ChannelNum); +void EPWM_ClearDutyIntFlag(EPWM_T *epwm, uint32_t u32ChannelNum); +uint32_t EPWM_GetDutyIntFlag(EPWM_T *epwm, uint32_t u32ChannelNum); +void EPWM_EnableFaultBrakeInt(EPWM_T *epwm, uint32_t u32BrakeSource); +void EPWM_DisableFaultBrakeInt(EPWM_T *epwm, uint32_t u32BrakeSource); +void EPWM_ClearFaultBrakeIntFlag(EPWM_T *epwm, uint32_t u32BrakeSource); +uint32_t EPWM_GetFaultBrakeIntFlag(EPWM_T *epwm, uint32_t u32BrakeSource); +void EPWM_EnablePeriodInt(EPWM_T *epwm, uint32_t u32ChannelNum, uint32_t u32IntPeriodType); +void EPWM_DisablePeriodInt(EPWM_T *epwm, uint32_t u32ChannelNum); +void EPWM_ClearPeriodIntFlag(EPWM_T *epwm, uint32_t u32ChannelNum); +uint32_t EPWM_GetPeriodIntFlag(EPWM_T *epwm, uint32_t u32ChannelNum); +void EPWM_EnableZeroInt(EPWM_T *epwm, uint32_t u32ChannelNum); +void EPWM_DisableZeroInt(EPWM_T *epwm, uint32_t u32ChannelNum); +void EPWM_ClearZeroIntFlag(EPWM_T *epwm, uint32_t u32ChannelNum); +uint32_t EPWM_GetZeroIntFlag(EPWM_T *epwm, uint32_t u32ChannelNum); +void EPWM_EnableAcc(EPWM_T *epwm, uint32_t u32ChannelNum, uint32_t u32IntFlagCnt, uint32_t u32IntAccSrc); +void EPWM_DisableAcc(EPWM_T *epwm, uint32_t u32ChannelNum); +void EPWM_EnableAccInt(EPWM_T *epwm, uint32_t u32ChannelNum); +void EPWM_DisableAccInt(EPWM_T *epwm, uint32_t u32ChannelNum); +void EPWM_ClearAccInt(EPWM_T *epwm, uint32_t u32ChannelNum); +uint32_t EPWM_GetAccInt(EPWM_T *epwm, uint32_t u32ChannelNum); +void EPWM_EnableAccPDMA(EPWM_T *epwm, uint32_t u32ChannelNum); +void EPWM_DisableAccPDMA(EPWM_T *epwm, uint32_t u32ChannelNum); +void EPWM_EnableAccStopMode(EPWM_T *epwm, uint32_t u32ChannelNum); +void EPWM_DisableAccStopMode(EPWM_T *epwm, uint32_t u32ChannelNum); +void EPWM_ClearFTDutyIntFlag(EPWM_T *epwm, uint32_t u32ChannelNum); +uint32_t EPWM_GetFTDutyIntFlag(EPWM_T *epwm, uint32_t u32ChannelNum); +void EPWM_EnableLoadMode(EPWM_T *epwm, uint32_t u32ChannelNum, uint32_t u32LoadMode); +void EPWM_DisableLoadMode(EPWM_T *epwm, uint32_t u32ChannelNum, uint32_t u32LoadMode); +void EPWM_ConfigSyncPhase(EPWM_T *epwm, uint32_t u32ChannelNum, uint32_t u32SyncSrc, uint32_t u32Direction, uint32_t u32StartPhase); +void EPWM_EnableSyncPhase(EPWM_T *epwm, uint32_t u32ChannelMask); +void EPWM_DisableSyncPhase(EPWM_T *epwm, uint32_t u32ChannelMask); +void EPWM_EnableSyncNoiseFilter(EPWM_T *epwm, uint32_t u32ClkCnt, uint32_t u32ClkDivSel); +void EPWM_DisableSyncNoiseFilter(EPWM_T *epwm); +void EPWM_EnableSyncPinInverse(EPWM_T *epwm); +void EPWM_DisableSyncPinInverse(EPWM_T *epwm); +void EPWM_SetClockSource(EPWM_T *epwm, uint32_t u32ChannelNum, uint32_t u32ClkSrcSel); +void EPWM_EnableBrakeNoiseFilter(EPWM_T *epwm, uint32_t u32BrakePinNum, uint32_t u32ClkCnt, uint32_t u32ClkDivSel); +void EPWM_DisableBrakeNoiseFilter(EPWM_T *epwm, uint32_t u32BrakePinNum); +void EPWM_EnableBrakePinInverse(EPWM_T *epwm, uint32_t u32BrakePinNum); +void EPWM_DisableBrakePinInverse(EPWM_T *epwm, uint32_t u32BrakePinNum); +void EPWM_SetBrakePinSource(EPWM_T *epwm, uint32_t u32BrakePinNum, uint32_t u32SelAnotherModule); +void EPWM_SetLeadingEdgeBlanking(EPWM_T *epwm, uint32_t u32TrigSrcSel, uint32_t u32TrigType, uint32_t u32BlankingCnt, uint32_t u32BlankingEnable); +uint32_t EPWM_GetWrapAroundFlag(EPWM_T *epwm, uint32_t u32ChannelNum); +void EPWM_ClearWrapAroundFlag(EPWM_T *epwm, uint32_t u32ChannelNum); +void EPWM_EnableFaultDetect(EPWM_T *epwm, uint32_t u32ChannelNum, uint32_t u32AfterPrescaler, uint32_t u32ClkSel); +void EPWM_DisableFaultDetect(EPWM_T *epwm, uint32_t u32ChannelNum); +void EPWM_EnableFaultDetectOutput(EPWM_T *epwm, uint32_t u32ChannelNum); +void EPWM_DisableFaultDetectOutput(EPWM_T *epwm, uint32_t u32ChannelNum); +void EPWM_EnableFaultDetectDeglitch(EPWM_T *epwm, uint32_t u32ChannelNum, uint32_t u32DeglitchSmpCycle); +void EPWM_DisableFaultDetectDeglitch(EPWM_T *epwm, uint32_t u32ChannelNum); +void EPWM_EnableFaultDetectMask(EPWM_T *epwm, uint32_t u32ChannelNum, uint32_t u32MaskCnt); +void EPWM_DisableFaultDetectMask(EPWM_T *epwm, uint32_t u32ChannelNum); +void EPWM_EnableFaultDetectInt(EPWM_T *epwm, uint32_t u32ChannelNum); +void EPWM_DisableFaultDetectInt(EPWM_T *epwm, uint32_t u32ChannelNum); +void EPWM_ClearFaultDetectInt(EPWM_T *epwm, uint32_t u32ChannelNum); +uint32_t EPWM_GetFaultDetectInt(EPWM_T *epwm, uint32_t u32ChannelNum); + +/*@}*/ /* end of group EPWM_EXPORTED_FUNCTIONS */ + +/*@}*/ /* end of group EPWM_Driver */ + +/*@}*/ /* end of group Standard_Driver */ + +#ifdef __cplusplus +} +#endif + +#endif /* __NU_EPWM_H__ */ + diff --git a/bsp/nuvoton/libraries/ma35/StdDriver/inc/nu_gpio.h b/bsp/nuvoton/libraries/ma35/StdDriver/inc/nu_gpio.h new file mode 100644 index 0000000000..ad033cb432 --- /dev/null +++ b/bsp/nuvoton/libraries/ma35/StdDriver/inc/nu_gpio.h @@ -0,0 +1,600 @@ +/**************************************************************************//** + * @file GPIO.h + * @brief GPIO driver header file + * + * SPDX-License-Identifier: Apache-2.0 + * @copyright (C) 2020 Nuvoton Technology Corp. All rights reserved. + ******************************************************************************/ +#ifndef __NU_GPIO_H__ +#define __NU_GPIO_H__ + + +#ifdef __cplusplus +extern "C" +{ +#endif + +/** @addtogroup Standard_Driver Standard Driver + @{ +*/ + +/** @addtogroup GPIO_Driver GPIO Driver + @{ +*/ + +/** @addtogroup GPIO_EXPORTED_CONSTANTS GPIO Exported Constants + @{ +*/ + + +#define GPIO_PIN_MAX 16UL /*!< Specify Maximum Pins of Each GPIO Port \hideinitializer */ + + +/*---------------------------------------------------------------------------------------------------------*/ +/* GPIO_MODE Constant Definitions */ +/*---------------------------------------------------------------------------------------------------------*/ +#define GPIO_MODE_INPUT 0x0UL /*!< Input Mode \hideinitializer */ +#define GPIO_MODE_OUTPUT 0x1UL /*!< Output Mode \hideinitializer */ +#define GPIO_MODE_OPEN_DRAIN 0x2UL /*!< Open-Drain Mode \hideinitializer */ +#define GPIO_MODE_QUASI 0x3UL /*!< Quasi-bidirectional Mode \hideinitializer */ + + +/*---------------------------------------------------------------------------------------------------------*/ +/* GPIO Interrupt Type Constant Definitions */ +/*---------------------------------------------------------------------------------------------------------*/ +#define GPIO_INT_RISING 0x00010000UL /*!< Interrupt enable by Input Rising Edge \hideinitializer */ +#define GPIO_INT_FALLING 0x00000001UL /*!< Interrupt enable by Input Falling Edge \hideinitializer */ +#define GPIO_INT_BOTH_EDGE 0x00010001UL /*!< Interrupt enable by both Rising Edge and Falling Edge \hideinitializer */ +#define GPIO_INT_HIGH 0x01010000UL /*!< Interrupt enable by Level-High \hideinitializer */ +#define GPIO_INT_LOW 0x01000001UL /*!< Interrupt enable by Level-Level \hideinitializer */ + + +/*---------------------------------------------------------------------------------------------------------*/ +/* GPIO_INTTYPE Constant Definitions */ +/*---------------------------------------------------------------------------------------------------------*/ +#define GPIO_INTTYPE_EDGE 0UL /*!< GPIO_INTTYPE Setting for Edge Trigger Mode \hideinitializer */ +#define GPIO_INTTYPE_LEVEL 1UL /*!< GPIO_INTTYPE Setting for Edge Level Mode \hideinitializer */ + +/*---------------------------------------------------------------------------------------------------------*/ +/* GPIO Slew Rate Type Constant Definitions */ +/*---------------------------------------------------------------------------------------------------------*/ +#define GPIO_SLEWCTL_NORMAL 0x0UL /*!< GPIO slew setting for normal Mode \hideinitializer */ +#define GPIO_SLEWCTL_HIGH 0x1UL /*!< GPIO slew setting for high Mode \hideinitializer */ +#define GPIO_SLEWCTL_FAST 0x2UL /*!< GPIO slew setting for fast Mode \hideinitializer */ + +/*---------------------------------------------------------------------------------------------------------*/ +/* GPIO Pull-up And Pull-down Type Constant Definitions */ +/*---------------------------------------------------------------------------------------------------------*/ +#define GPIO_PUSEL_DISABLE 0x0UL /*!< GPIO PUSEL setting for Disable Mode \hideinitializer */ +#define GPIO_PUSEL_PULL_UP 0x1UL /*!< GPIO PUSEL setting for Pull-up Mode \hideinitializer */ +#define GPIO_PUSEL_PULL_DOWN 0x2UL /*!< GPIO PUSEL setting for Pull-down Mode \hideinitializer */ + + +/*---------------------------------------------------------------------------------------------------------*/ +/* GPIO_DBCTL Constant Definitions */ +/*---------------------------------------------------------------------------------------------------------*/ +#define GPIO_DBCTL_ICLK_ON 0x00000020UL /*!< GPIO_DBCTL setting for all IO pins edge detection circuit is always active after reset \hideinitializer */ +#define GPIO_DBCTL_ICLK_OFF 0x00000000UL /*!< GPIO_DBCTL setting for edge detection circuit is active only if IO pin corresponding GPIOx_IEN bit is set to 1 \hideinitializer */ + +#define GPIO_DBCTL_DBCLKSRC_LIRC 0x00000010UL /*!< GPIO_DBCTL setting for de-bounce counter clock source is the internal 10 kHz \hideinitializer */ +#define GPIO_DBCTL_DBCLKSRC_HXT 0x00000000UL /*!< GPIO_DBCTL setting for de-bounce counter clock source is the HCLK \hideinitializer */ + +#define GPIO_DBCTL_DBCLKSEL_1 0x00000000UL /*!< GPIO_DBCTL setting for sampling cycle = 1 clocks \hideinitializer */ +#define GPIO_DBCTL_DBCLKSEL_2 0x00000001UL /*!< GPIO_DBCTL setting for sampling cycle = 2 clocks \hideinitializer */ +#define GPIO_DBCTL_DBCLKSEL_4 0x00000002UL /*!< GPIO_DBCTL setting for sampling cycle = 4 clocks \hideinitializer */ +#define GPIO_DBCTL_DBCLKSEL_8 0x00000003UL /*!< GPIO_DBCTL setting for sampling cycle = 8 clocks \hideinitializer */ +#define GPIO_DBCTL_DBCLKSEL_16 0x00000004UL /*!< GPIO_DBCTL setting for sampling cycle = 16 clocks \hideinitializer */ +#define GPIO_DBCTL_DBCLKSEL_32 0x00000005UL /*!< GPIO_DBCTL setting for sampling cycle = 32 clocks \hideinitializer */ +#define GPIO_DBCTL_DBCLKSEL_64 0x00000006UL /*!< GPIO_DBCTL setting for sampling cycle = 64 clocks \hideinitializer */ +#define GPIO_DBCTL_DBCLKSEL_128 0x00000007UL /*!< GPIO_DBCTL setting for sampling cycle = 128 clocks \hideinitializer */ +#define GPIO_DBCTL_DBCLKSEL_256 0x00000008UL /*!< GPIO_DBCTL setting for sampling cycle = 256 clocks \hideinitializer */ +#define GPIO_DBCTL_DBCLKSEL_512 0x00000009UL /*!< GPIO_DBCTL setting for sampling cycle = 512 clocks \hideinitializer */ +#define GPIO_DBCTL_DBCLKSEL_1024 0x0000000AUL /*!< GPIO_DBCTL setting for sampling cycle = 1024 clocks \hideinitializer */ +#define GPIO_DBCTL_DBCLKSEL_2048 0x0000000BUL /*!< GPIO_DBCTL setting for sampling cycle = 2048 clocks \hideinitializer */ +#define GPIO_DBCTL_DBCLKSEL_4096 0x0000000CUL /*!< GPIO_DBCTL setting for sampling cycle = 4096 clocks \hideinitializer */ +#define GPIO_DBCTL_DBCLKSEL_8192 0x0000000DUL /*!< GPIO_DBCTL setting for sampling cycle = 8192 clocks \hideinitializer */ +#define GPIO_DBCTL_DBCLKSEL_16384 0x0000000EUL /*!< GPIO_DBCTL setting for sampling cycle = 16384 clocks \hideinitializer */ +#define GPIO_DBCTL_DBCLKSEL_32768 0x0000000FUL /*!< GPIO_DBCTL setting for sampling cycle = 32768 clocks \hideinitializer */ + + +/* Define GPIO Pin Data Input/Output. It could be used to control each I/O pin by pin address mapping. + Example 1: + + PA0 = 1; + + It is used to set GPIO PA.0 to high; + + Example 2: + + if (PA0) + PA0 = 0; + + If GPIO PA.0 pin status is high, then set GPIO PA.0 data output to low. + */ +#define GPIO_PIN_DATA(port, pin) (*((volatile uint32_t *)((GPIO_PIN_DATA_BASE+(0x40*(port))) + ((pin)<<2)))) /*!< Pin Data Input/Output \hideinitializer */ +#define PA0 GPIO_PIN_DATA(0, 0 ) /*!< Specify PA.0 Pin Data Input/Output \hideinitializer */ +#define PA1 GPIO_PIN_DATA(0, 1 ) /*!< Specify PA.1 Pin Data Input/Output \hideinitializer */ +#define PA2 GPIO_PIN_DATA(0, 2 ) /*!< Specify PA.2 Pin Data Input/Output \hideinitializer */ +#define PA3 GPIO_PIN_DATA(0, 3 ) /*!< Specify PA.3 Pin Data Input/Output \hideinitializer */ +#define PA4 GPIO_PIN_DATA(0, 4 ) /*!< Specify PA.4 Pin Data Input/Output \hideinitializer */ +#define PA5 GPIO_PIN_DATA(0, 5 ) /*!< Specify PA.5 Pin Data Input/Output \hideinitializer */ +#define PA6 GPIO_PIN_DATA(0, 6 ) /*!< Specify PA.6 Pin Data Input/Output \hideinitializer */ +#define PA7 GPIO_PIN_DATA(0, 7 ) /*!< Specify PA.7 Pin Data Input/Output \hideinitializer */ +#define PA8 GPIO_PIN_DATA(0, 8 ) /*!< Specify PA.8 Pin Data Input/Output \hideinitializer */ +#define PA9 GPIO_PIN_DATA(0, 9 ) /*!< Specify PA.9 Pin Data Input/Output \hideinitializer */ +#define PA10 GPIO_PIN_DATA(0, 10) /*!< Specify PA.10 Pin Data Input/Output \hideinitializer */ +#define PA11 GPIO_PIN_DATA(0, 11) /*!< Specify PA.11 Pin Data Input/Output \hideinitializer */ +#define PA12 GPIO_PIN_DATA(0, 12) /*!< Specify PA.12 Pin Data Input/Output \hideinitializer */ +#define PA13 GPIO_PIN_DATA(0, 13) /*!< Specify PA.13 Pin Data Input/Output \hideinitializer */ +#define PA14 GPIO_PIN_DATA(0, 14) /*!< Specify PA.14 Pin Data Input/Output \hideinitializer */ +#define PA15 GPIO_PIN_DATA(0, 15) /*!< Specify PA.15 Pin Data Input/Output \hideinitializer */ +#define PB0 GPIO_PIN_DATA(1, 0 ) /*!< Specify PB.0 Pin Data Input/Output \hideinitializer */ +#define PB1 GPIO_PIN_DATA(1, 1 ) /*!< Specify PB.1 Pin Data Input/Output \hideinitializer */ +#define PB2 GPIO_PIN_DATA(1, 2 ) /*!< Specify PB.2 Pin Data Input/Output \hideinitializer */ +#define PB3 GPIO_PIN_DATA(1, 3 ) /*!< Specify PB.3 Pin Data Input/Output \hideinitializer */ +#define PB4 GPIO_PIN_DATA(1, 4 ) /*!< Specify PB.4 Pin Data Input/Output \hideinitializer */ +#define PB5 GPIO_PIN_DATA(1, 5 ) /*!< Specify PB.5 Pin Data Input/Output \hideinitializer */ +#define PB6 GPIO_PIN_DATA(1, 6 ) /*!< Specify PB.6 Pin Data Input/Output \hideinitializer */ +#define PB7 GPIO_PIN_DATA(1, 7 ) /*!< Specify PB.7 Pin Data Input/Output \hideinitializer */ +#define PB8 GPIO_PIN_DATA(1, 8 ) /*!< Specify PB.8 Pin Data Input/Output \hideinitializer */ +#define PB9 GPIO_PIN_DATA(1, 9 ) /*!< Specify PB.9 Pin Data Input/Output \hideinitializer */ +#define PB10 GPIO_PIN_DATA(1, 10) /*!< Specify PB.10 Pin Data Input/Output \hideinitializer */ +#define PB11 GPIO_PIN_DATA(1, 11) /*!< Specify PB.11 Pin Data Input/Output \hideinitializer */ +#define PB12 GPIO_PIN_DATA(1, 12) /*!< Specify PB.12 Pin Data Input/Output \hideinitializer */ +#define PB13 GPIO_PIN_DATA(1, 13) /*!< Specify PB.13 Pin Data Input/Output \hideinitializer */ +#define PB14 GPIO_PIN_DATA(1, 14) /*!< Specify PB.14 Pin Data Input/Output \hideinitializer */ +#define PB15 GPIO_PIN_DATA(1, 15) /*!< Specify PB.15 Pin Data Input/Output \hideinitializer */ +#define PC0 GPIO_PIN_DATA(2, 0 ) /*!< Specify PC.0 Pin Data Input/Output \hideinitializer */ +#define PC1 GPIO_PIN_DATA(2, 1 ) /*!< Specify PC.1 Pin Data Input/Output \hideinitializer */ +#define PC2 GPIO_PIN_DATA(2, 2 ) /*!< Specify PC.2 Pin Data Input/Output \hideinitializer */ +#define PC3 GPIO_PIN_DATA(2, 3 ) /*!< Specify PC.3 Pin Data Input/Output \hideinitializer */ +#define PC4 GPIO_PIN_DATA(2, 4 ) /*!< Specify PC.4 Pin Data Input/Output \hideinitializer */ +#define PC5 GPIO_PIN_DATA(2, 5 ) /*!< Specify PC.5 Pin Data Input/Output \hideinitializer */ +#define PC6 GPIO_PIN_DATA(2, 6 ) /*!< Specify PC.6 Pin Data Input/Output \hideinitializer */ +#define PC7 GPIO_PIN_DATA(2, 7 ) /*!< Specify PC.7 Pin Data Input/Output \hideinitializer */ +#define PC8 GPIO_PIN_DATA(2, 8 ) /*!< Specify PC.8 Pin Data Input/Output \hideinitializer */ +#define PC9 GPIO_PIN_DATA(2, 9 ) /*!< Specify PC.9 Pin Data Input/Output \hideinitializer */ +#define PC10 GPIO_PIN_DATA(2, 10) /*!< Specify PC.10 Pin Data Input/Output \hideinitializer */ +#define PC11 GPIO_PIN_DATA(2, 11) /*!< Specify PC.11 Pin Data Input/Output \hideinitializer */ +#define PC12 GPIO_PIN_DATA(2, 12) /*!< Specify PC.12 Pin Data Input/Output \hideinitializer */ +#define PC13 GPIO_PIN_DATA(2, 13) /*!< Specify PC.13 Pin Data Input/Output \hideinitializer */ +#define PC14 GPIO_PIN_DATA(2, 14) /*!< Specify PC.14 Pin Data Input/Output \hideinitializer */ +#define PD0 GPIO_PIN_DATA(3, 0 ) /*!< Specify PD.0 Pin Data Input/Output \hideinitializer */ +#define PD1 GPIO_PIN_DATA(3, 1 ) /*!< Specify PD.1 Pin Data Input/Output \hideinitializer */ +#define PD2 GPIO_PIN_DATA(3, 2 ) /*!< Specify PD.2 Pin Data Input/Output \hideinitializer */ +#define PD3 GPIO_PIN_DATA(3, 3 ) /*!< Specify PD.3 Pin Data Input/Output \hideinitializer */ +#define PD4 GPIO_PIN_DATA(3, 4 ) /*!< Specify PD.4 Pin Data Input/Output \hideinitializer */ +#define PD5 GPIO_PIN_DATA(3, 5 ) /*!< Specify PD.5 Pin Data Input/Output \hideinitializer */ +#define PD6 GPIO_PIN_DATA(3, 6 ) /*!< Specify PD.6 Pin Data Input/Output \hideinitializer */ +#define PD7 GPIO_PIN_DATA(3, 7 ) /*!< Specify PD.7 Pin Data Input/Output \hideinitializer */ +#define PD8 GPIO_PIN_DATA(3, 8 ) /*!< Specify PD.8 Pin Data Input/Output \hideinitializer */ +#define PD9 GPIO_PIN_DATA(3, 9 ) /*!< Specify PD.9 Pin Data Input/Output \hideinitializer */ +#define PD10 GPIO_PIN_DATA(3, 10) /*!< Specify PD.10 Pin Data Input/Output \hideinitializer */ +#define PD11 GPIO_PIN_DATA(3, 11) /*!< Specify PD.11 Pin Data Input/Output \hideinitializer */ +#define PD12 GPIO_PIN_DATA(3, 12) /*!< Specify PD.12 Pin Data Input/Output \hideinitializer */ +#define PD13 GPIO_PIN_DATA(3, 13) /*!< Specify PD.13 Pin Data Input/Output \hideinitializer */ +#define PD14 GPIO_PIN_DATA(3, 14) /*!< Specify PD.14 Pin Data Input/Output \hideinitializer */ +#define PE0 GPIO_PIN_DATA(4, 0 ) /*!< Specify PE.0 Pin Data Input/Output \hideinitializer */ +#define PE1 GPIO_PIN_DATA(4, 1 ) /*!< Specify PE.1 Pin Data Input/Output \hideinitializer */ +#define PE2 GPIO_PIN_DATA(4, 2 ) /*!< Specify PE.2 Pin Data Input/Output \hideinitializer */ +#define PE3 GPIO_PIN_DATA(4, 3 ) /*!< Specify PE.3 Pin Data Input/Output \hideinitializer */ +#define PE4 GPIO_PIN_DATA(4, 4 ) /*!< Specify PE.4 Pin Data Input/Output \hideinitializer */ +#define PE5 GPIO_PIN_DATA(4, 5 ) /*!< Specify PE.5 Pin Data Input/Output \hideinitializer */ +#define PE6 GPIO_PIN_DATA(4, 6 ) /*!< Specify PE.6 Pin Data Input/Output \hideinitializer */ +#define PE7 GPIO_PIN_DATA(4, 7 ) /*!< Specify PE.7 Pin Data Input/Output \hideinitializer */ +#define PE8 GPIO_PIN_DATA(4, 8 ) /*!< Specify PE.8 Pin Data Input/Output \hideinitializer */ +#define PE9 GPIO_PIN_DATA(4, 9 ) /*!< Specify PE.9 Pin Data Input/Output \hideinitializer */ +#define PE10 GPIO_PIN_DATA(4, 10) /*!< Specify PE.10 Pin Data Input/Output \hideinitializer */ +#define PE11 GPIO_PIN_DATA(4, 11) /*!< Specify PE.11 Pin Data Input/Output \hideinitializer */ +#define PE12 GPIO_PIN_DATA(4, 12) /*!< Specify PE.12 Pin Data Input/Output \hideinitializer */ +#define PE13 GPIO_PIN_DATA(4, 13) /*!< Specify PE.13 Pin Data Input/Output \hideinitializer */ +#define PE14 GPIO_PIN_DATA(4, 14) /*!< Specify PE.14 Pin Data Input/Output \hideinitializer */ +#define PE15 GPIO_PIN_DATA(4, 15) /*!< Specify PE.15 Pin Data Input/Output \hideinitializer */ +#define PF0 GPIO_PIN_DATA(5, 0 ) /*!< Specify PF.0 Pin Data Input/Output \hideinitializer */ +#define PF1 GPIO_PIN_DATA(5, 1 ) /*!< Specify PF.1 Pin Data Input/Output \hideinitializer */ +#define PF2 GPIO_PIN_DATA(5, 2 ) /*!< Specify PF.2 Pin Data Input/Output \hideinitializer */ +#define PF3 GPIO_PIN_DATA(5, 3 ) /*!< Specify PF.3 Pin Data Input/Output \hideinitializer */ +#define PF4 GPIO_PIN_DATA(5, 4 ) /*!< Specify PF.4 Pin Data Input/Output \hideinitializer */ +#define PF5 GPIO_PIN_DATA(5, 5 ) /*!< Specify PF.5 Pin Data Input/Output \hideinitializer */ +#define PF6 GPIO_PIN_DATA(5, 6 ) /*!< Specify PF.6 Pin Data Input/Output \hideinitializer */ +#define PF7 GPIO_PIN_DATA(5, 7 ) /*!< Specify PF.7 Pin Data Input/Output \hideinitializer */ +#define PF8 GPIO_PIN_DATA(5, 8 ) /*!< Specify PF.8 Pin Data Input/Output \hideinitializer */ +#define PF9 GPIO_PIN_DATA(5, 9 ) /*!< Specify PF.9 Pin Data Input/Output \hideinitializer */ +#define PF10 GPIO_PIN_DATA(5, 10) /*!< Specify PF.10 Pin Data Input/Output \hideinitializer */ +#define PF11 GPIO_PIN_DATA(5, 11) /*!< Specify PF.11 Pin Data Input/Output \hideinitializer */ +#define PG0 GPIO_PIN_DATA(6, 0 ) /*!< Specify PG.0 Pin Data Input/Output \hideinitializer */ +#define PG1 GPIO_PIN_DATA(6, 1 ) /*!< Specify PG.1 Pin Data Input/Output \hideinitializer */ +#define PG2 GPIO_PIN_DATA(6, 2 ) /*!< Specify PG.2 Pin Data Input/Output \hideinitializer */ +#define PG3 GPIO_PIN_DATA(6, 3 ) /*!< Specify PG.3 Pin Data Input/Output \hideinitializer */ +#define PG4 GPIO_PIN_DATA(6, 4 ) /*!< Specify PG.4 Pin Data Input/Output \hideinitializer */ +#define PG5 GPIO_PIN_DATA(6, 5 ) /*!< Specify PG.5 Pin Data Input/Output \hideinitializer */ +#define PG6 GPIO_PIN_DATA(6, 6 ) /*!< Specify PG.6 Pin Data Input/Output \hideinitializer */ +#define PG7 GPIO_PIN_DATA(6, 7 ) /*!< Specify PG.7 Pin Data Input/Output \hideinitializer */ +#define PG8 GPIO_PIN_DATA(6, 8 ) /*!< Specify PG.8 Pin Data Input/Output \hideinitializer */ +#define PG9 GPIO_PIN_DATA(6, 9 ) /*!< Specify PG.9 Pin Data Input/Output \hideinitializer */ +#define PG10 GPIO_PIN_DATA(6, 10) /*!< Specify PG.10 Pin Data Input/Output \hideinitializer */ +#define PG11 GPIO_PIN_DATA(6, 11) /*!< Specify PG.11 Pin Data Input/Output \hideinitializer */ +#define PG12 GPIO_PIN_DATA(6, 12) /*!< Specify PG.12 Pin Data Input/Output \hideinitializer */ +#define PG13 GPIO_PIN_DATA(6, 13) /*!< Specify PG.13 Pin Data Input/Output \hideinitializer */ +#define PG14 GPIO_PIN_DATA(6, 14) /*!< Specify PG.14 Pin Data Input/Output \hideinitializer */ +#define PG15 GPIO_PIN_DATA(6, 15) /*!< Specify PG.15 Pin Data Input/Output \hideinitializer */ +#define PH0 GPIO_PIN_DATA(7, 0 ) /*!< Specify PH.0 Pin Data Input/Output \hideinitializer */ +#define PH1 GPIO_PIN_DATA(7, 1 ) /*!< Specify PH.1 Pin Data Input/Output \hideinitializer */ +#define PH2 GPIO_PIN_DATA(7, 2 ) /*!< Specify PH.2 Pin Data Input/Output \hideinitializer */ +#define PH3 GPIO_PIN_DATA(7, 3 ) /*!< Specify PH.3 Pin Data Input/Output \hideinitializer */ +#define PH4 GPIO_PIN_DATA(7, 4 ) /*!< Specify PH.4 Pin Data Input/Output \hideinitializer */ +#define PH5 GPIO_PIN_DATA(7, 5 ) /*!< Specify PH.5 Pin Data Input/Output \hideinitializer */ +#define PH6 GPIO_PIN_DATA(7, 6 ) /*!< Specify PH.6 Pin Data Input/Output \hideinitializer */ +#define PH7 GPIO_PIN_DATA(7, 7 ) /*!< Specify PH.7 Pin Data Input/Output \hideinitializer */ +#define PH8 GPIO_PIN_DATA(7, 8 ) /*!< Specify PH.8 Pin Data Input/Output \hideinitializer */ +#define PH9 GPIO_PIN_DATA(7, 9 ) /*!< Specify PH.9 Pin Data Input/Output \hideinitializer */ +#define PH10 GPIO_PIN_DATA(7, 10) /*!< Specify PH.10 Pin Data Input/Output \hideinitializer */ +#define PH11 GPIO_PIN_DATA(7, 11) /*!< Specify PH.11 Pin Data Input/Output \hideinitializer */ +#define PH12 GPIO_PIN_DATA(7, 12) /*!< Specify PH.12 Pin Data Input/Output \hideinitializer */ +#define PH13 GPIO_PIN_DATA(7, 13) /*!< Specify PH.13 Pin Data Input/Output \hideinitializer */ +#define PH14 GPIO_PIN_DATA(7, 14) /*!< Specify PH.14 Pin Data Input/Output \hideinitializer */ +#define PH15 GPIO_PIN_DATA(7, 15) /*!< Specify PH.15 Pin Data Input/Output \hideinitializer */ +#define PI0 GPIO_PIN_DATA(8, 0 ) /*!< Specify PI.0 Pin Data Input/Output \hideinitializer */ +#define PI1 GPIO_PIN_DATA(8, 1 ) /*!< Specify PI.1 Pin Data Input/Output \hideinitializer */ +#define PI2 GPIO_PIN_DATA(8, 2 ) /*!< Specify PI.2 Pin Data Input/Output \hideinitializer */ +#define PI3 GPIO_PIN_DATA(8, 3 ) /*!< Specify PI.3 Pin Data Input/Output \hideinitializer */ +#define PI4 GPIO_PIN_DATA(8, 4 ) /*!< Specify PI.4 Pin Data Input/Output \hideinitializer */ +#define PI5 GPIO_PIN_DATA(8, 5 ) /*!< Specify PI.5 Pin Data Input/Output \hideinitializer */ +#define PI6 GPIO_PIN_DATA(8, 6 ) /*!< Specify PI.6 Pin Data Input/Output \hideinitializer */ +#define PI7 GPIO_PIN_DATA(8, 7 ) /*!< Specify PI.7 Pin Data Input/Output \hideinitializer */ +#define PI8 GPIO_PIN_DATA(8, 8 ) /*!< Specify PI.8 Pin Data Input/Output \hideinitializer */ +#define PI9 GPIO_PIN_DATA(8, 9 ) /*!< Specify PI.9 Pin Data Input/Output \hideinitializer */ +#define PI10 GPIO_PIN_DATA(8, 10) /*!< Specify PI.10 Pin Data Input/Output \hideinitializer */ +#define PI11 GPIO_PIN_DATA(8, 11) /*!< Specify PI.11 Pin Data Input/Output \hideinitializer */ +#define PI12 GPIO_PIN_DATA(8, 12) /*!< Specify PI.12 Pin Data Input/Output \hideinitializer */ +#define PI13 GPIO_PIN_DATA(8, 13) /*!< Specify PI.13 Pin Data Input/Output \hideinitializer */ +#define PI14 GPIO_PIN_DATA(8, 14) /*!< Specify PI.14 Pin Data Input/Output \hideinitializer */ +#define PI15 GPIO_PIN_DATA(8, 15) /*!< Specify PI.15 Pin Data Input/Output \hideinitializer */ +#define PJ0 GPIO_PIN_DATA(9, 0 ) /*!< Specify PJ.0 Pin Data Input/Output \hideinitializer */ +#define PJ1 GPIO_PIN_DATA(9, 1 ) /*!< Specify PJ.1 Pin Data Input/Output \hideinitializer */ +#define PJ2 GPIO_PIN_DATA(9, 2 ) /*!< Specify PJ.2 Pin Data Input/Output \hideinitializer */ +#define PJ3 GPIO_PIN_DATA(9, 3 ) /*!< Specify PJ.3 Pin Data Input/Output \hideinitializer */ +#define PJ4 GPIO_PIN_DATA(9, 4 ) /*!< Specify PJ.4 Pin Data Input/Output \hideinitializer */ +#define PJ5 GPIO_PIN_DATA(9, 5 ) /*!< Specify PJ.5 Pin Data Input/Output \hideinitializer */ +#define PJ6 GPIO_PIN_DATA(9, 6 ) /*!< Specify PJ.6 Pin Data Input/Output \hideinitializer */ +#define PJ7 GPIO_PIN_DATA(9, 7 ) /*!< Specify PJ.7 Pin Data Input/Output \hideinitializer */ +#define PJ8 GPIO_PIN_DATA(9, 8 ) /*!< Specify PJ.8 Pin Data Input/Output \hideinitializer */ +#define PJ9 GPIO_PIN_DATA(9, 9 ) /*!< Specify PJ.9 Pin Data Input/Output \hideinitializer */ +#define PJ10 GPIO_PIN_DATA(9, 10) /*!< Specify PJ.10 Pin Data Input/Output \hideinitializer */ +#define PJ11 GPIO_PIN_DATA(9, 11) /*!< Specify PJ.11 Pin Data Input/Output \hideinitializer */ +#define PJ12 GPIO_PIN_DATA(9, 12) /*!< Specify PJ.12 Pin Data Input/Output \hideinitializer */ +#define PJ13 GPIO_PIN_DATA(9, 13) /*!< Specify PJ.13 Pin Data Input/Output \hideinitializer */ +#define PJ14 GPIO_PIN_DATA(9, 14) /*!< Specify PJ.14 Pin Data Input/Output \hideinitializer */ +#define PJ15 GPIO_PIN_DATA(9, 15) /*!< Specify PJ.15 Pin Data Input/Output \hideinitializer */ +#define PK0 GPIO_PIN_DATA(10 , 0 ) /*!< Specify PK.0 Pin Data Input/Output \hideinitializer */ +#define PK1 GPIO_PIN_DATA(10 , 1 ) /*!< Specify PK.1 Pin Data Input/Output \hideinitializer */ +#define PK2 GPIO_PIN_DATA(10 , 2 ) /*!< Specify PK.2 Pin Data Input/Output \hideinitializer */ +#define PK3 GPIO_PIN_DATA(10 , 3 ) /*!< Specify PK.3 Pin Data Input/Output \hideinitializer */ +#define PK4 GPIO_PIN_DATA(10 , 4 ) /*!< Specify PK.4 Pin Data Input/Output \hideinitializer */ +#define PK5 GPIO_PIN_DATA(10 , 5 ) /*!< Specify PK.5 Pin Data Input/Output \hideinitializer */ +#define PK6 GPIO_PIN_DATA(10 , 6 ) /*!< Specify PK.6 Pin Data Input/Output \hideinitializer */ +#define PK7 GPIO_PIN_DATA(10 , 7 ) /*!< Specify PK.7 Pin Data Input/Output \hideinitializer */ +#define PK8 GPIO_PIN_DATA(10 , 8 ) /*!< Specify PK.8 Pin Data Input/Output \hideinitializer */ +#define PK9 GPIO_PIN_DATA(10 , 9 ) /*!< Specify PK.9 Pin Data Input/Output \hideinitializer */ +#define PK10 GPIO_PIN_DATA(10 , 10) /*!< Specify PK.10 Pin Data Input/Output \hideinitializer */ +#define PK11 GPIO_PIN_DATA(10 , 11) /*!< Specify PK.11 Pin Data Input/Output \hideinitializer */ +#define PK12 GPIO_PIN_DATA(10 , 12) /*!< Specify PK.12 Pin Data Input/Output \hideinitializer */ +#define PK13 GPIO_PIN_DATA(10 , 13) /*!< Specify PK.13 Pin Data Input/Output \hideinitializer */ +#define PK14 GPIO_PIN_DATA(10 , 14) /*!< Specify PK.14 Pin Data Input/Output \hideinitializer */ +#define PK15 GPIO_PIN_DATA(10 , 15) /*!< Specify PK.15 Pin Data Input/Output \hideinitializer */ +#define PL0 GPIO_PIN_DATA(11, 0 ) /*!< Specify PL.0 Pin Data Input/Output \hideinitializer */ +#define PL1 GPIO_PIN_DATA(11, 1 ) /*!< Specify PL.1 Pin Data Input/Output \hideinitializer */ +#define PL2 GPIO_PIN_DATA(11, 2 ) /*!< Specify PL.2 Pin Data Input/Output \hideinitializer */ +#define PL3 GPIO_PIN_DATA(11, 3 ) /*!< Specify PL.3 Pin Data Input/Output \hideinitializer */ +#define PL4 GPIO_PIN_DATA(11, 4 ) /*!< Specify PL.4 Pin Data Input/Output \hideinitializer */ +#define PL5 GPIO_PIN_DATA(11, 5 ) /*!< Specify PL.5 Pin Data Input/Output \hideinitializer */ +#define PL6 GPIO_PIN_DATA(11, 6 ) /*!< Specify PL.6 Pin Data Input/Output \hideinitializer */ +#define PL7 GPIO_PIN_DATA(11, 7 ) /*!< Specify PL.7 Pin Data Input/Output \hideinitializer */ +#define PL8 GPIO_PIN_DATA(11, 8 ) /*!< Specify PL.8 Pin Data Input/Output \hideinitializer */ +#define PL9 GPIO_PIN_DATA(11, 9 ) /*!< Specify PL.9 Pin Data Input/Output \hideinitializer */ +#define PL10 GPIO_PIN_DATA(11, 10) /*!< Specify PL.10 Pin Data Input/Output \hideinitializer */ +#define PL11 GPIO_PIN_DATA(11, 11) /*!< Specify PL.11 Pin Data Input/Output \hideinitializer */ +#define PL12 GPIO_PIN_DATA(11, 12) /*!< Specify PL.12 Pin Data Input/Output \hideinitializer */ +#define PL13 GPIO_PIN_DATA(11, 13) /*!< Specify PL.13 Pin Data Input/Output \hideinitializer */ +#define PL14 GPIO_PIN_DATA(11, 14) /*!< Specify PL.14 Pin Data Input/Output \hideinitializer */ +#define PL15 GPIO_PIN_DATA(11, 15) /*!< Specify PL.15 Pin Data Input/Output \hideinitializer */ +#define PM0 GPIO_PIN_DATA(12, 0 ) /*!< Specify PH.0 Pin Data Input/Output \hideinitializer */ +#define PM1 GPIO_PIN_DATA(12, 1 ) /*!< Specify PH.1 Pin Data Input/Output \hideinitializer */ +#define PM2 GPIO_PIN_DATA(12, 2 ) /*!< Specify PH.2 Pin Data Input/Output \hideinitializer */ +#define PM3 GPIO_PIN_DATA(12, 3 ) /*!< Specify PH.3 Pin Data Input/Output \hideinitializer */ +#define PM4 GPIO_PIN_DATA(12, 4 ) /*!< Specify PH.4 Pin Data Input/Output \hideinitializer */ +#define PM5 GPIO_PIN_DATA(12, 5 ) /*!< Specify PH.5 Pin Data Input/Output \hideinitializer */ +#define PM6 GPIO_PIN_DATA(12, 6 ) /*!< Specify PH.6 Pin Data Input/Output \hideinitializer */ +#define PM7 GPIO_PIN_DATA(12, 7 ) /*!< Specify PH.7 Pin Data Input/Output \hideinitializer */ +#define PM8 GPIO_PIN_DATA(12, 8 ) /*!< Specify PH.8 Pin Data Input/Output \hideinitializer */ +#define PM9 GPIO_PIN_DATA(12, 9 ) /*!< Specify PH.9 Pin Data Input/Output \hideinitializer */ +#define PM10 GPIO_PIN_DATA(12, 10) /*!< Specify PH.10 Pin Data Input/Output \hideinitializer */ +#define PM11 GPIO_PIN_DATA(12, 11) /*!< Specify PH.11 Pin Data Input/Output \hideinitializer */ +#define PM12 GPIO_PIN_DATA(12, 12) /*!< Specify PH.12 Pin Data Input/Output \hideinitializer */ +#define PM13 GPIO_PIN_DATA(12, 13) /*!< Specify PH.13 Pin Data Input/Output \hideinitializer */ +#define PM14 GPIO_PIN_DATA(12, 14) /*!< Specify PH.14 Pin Data Input/Output \hideinitializer */ +#define PM15 GPIO_PIN_DATA(12, 15) /*!< Specify PH.15 Pin Data Input/Output \hideinitializer */ +#define PN0 GPIO_PIN_DATA(13, 0 ) /*!< Specify PH.0 Pin Data Input/Output \hideinitializer */ +#define PN1 GPIO_PIN_DATA(13, 1 ) /*!< Specify PH.1 Pin Data Input/Output \hideinitializer */ +#define PN2 GPIO_PIN_DATA(13, 2 ) /*!< Specify PH.2 Pin Data Input/Output \hideinitializer */ +#define PN3 GPIO_PIN_DATA(13, 3 ) /*!< Specify PH.3 Pin Data Input/Output \hideinitializer */ +#define PN4 GPIO_PIN_DATA(13, 4 ) /*!< Specify PH.4 Pin Data Input/Output \hideinitializer */ +#define PN5 GPIO_PIN_DATA(13, 5 ) /*!< Specify PH.5 Pin Data Input/Output \hideinitializer */ +#define PN6 GPIO_PIN_DATA(13, 6 ) /*!< Specify PH.6 Pin Data Input/Output \hideinitializer */ +#define PN7 GPIO_PIN_DATA(13, 7 ) /*!< Specify PH.7 Pin Data Input/Output \hideinitializer */ +#define PN8 GPIO_PIN_DATA(13, 8 ) /*!< Specify PH.8 Pin Data Input/Output \hideinitializer */ +#define PN9 GPIO_PIN_DATA(13, 9 ) /*!< Specify PH.9 Pin Data Input/Output \hideinitializer */ +#define PN10 GPIO_PIN_DATA(13, 10) /*!< Specify PH.10 Pin Data Input/Output \hideinitializer */ +#define PN11 GPIO_PIN_DATA(13, 11) /*!< Specify PH.11 Pin Data Input/Output \hideinitializer */ +#define PN12 GPIO_PIN_DATA(13, 12) /*!< Specify PH.12 Pin Data Input/Output \hideinitializer */ +#define PN13 GPIO_PIN_DATA(13, 13) /*!< Specify PH.13 Pin Data Input/Output \hideinitializer */ +#define PN14 GPIO_PIN_DATA(13, 14) /*!< Specify PH.14 Pin Data Input/Output \hideinitializer */ +#define PN15 GPIO_PIN_DATA(13, 15) /*!< Specify PH.15 Pin Data Input/Output \hideinitializer */ + +/*@}*/ /* end of group GPIO_EXPORTED_CONSTANTS */ + + +/** @addtogroup GPIO_EXPORTED_FUNCTIONS GPIO Exported Functions + @{ +*/ + +/** + * @brief Clear GPIO Pin Interrupt Flag + * + * @param[in] port GPIO port. It could be PA, PB, PC, PD, PE, PF, PG, PH, PI, PJ, PK,PL, PM and PN. + * @param[in] u32PinMask The single or multiple pins of specified GPIO port. + * It could be BIT0 ~ BIT15 for PA, PB, PC, PD, PF and PH GPIO port. + * It could be BIT0 ~ BIT13 for PE GPIO port. + * It could be BIT0 ~ BIT11 for PG GPIO port. + * + * @return None + * + * @details Clear the interrupt status of specified GPIO pin. + * \hideinitializer + */ +#define GPIO_CLR_INT_FLAG(port, u32PinMask) ((port)->INTSRC = (u32PinMask)) + +/** + * @brief Disable Pin De-bounce Function + * + * @param[in] port GPIO port. It could be PA, PB, PC, PD, PE, PF, PG, PH, PI, PJ, PK,PL, PM and PN. + * @param[in] u32PinMask The single or multiple pins of specified GPIO port. + * It could be BIT0 ~ BIT15 for PA, PB, PC, PD, PF and PH GPIO port. + * It could be BIT0 ~ BIT13 for PE GPIO port. + * It could be BIT0 ~ BIT11 for PG GPIO port. + * + * @return None + * + * @details Disable the interrupt de-bounce function of specified GPIO pin. + * \hideinitializer + */ +#define GPIO_DISABLE_DEBOUNCE(port, u32PinMask) ((port)->DBEN &= ~(u32PinMask)) + +/** + * @brief Enable Pin De-bounce Function + * + * @param[in] port GPIO port. It could be PA, PB, PC, PD, PE, PF, PG or PH. + * @param[in] u32PinMask The single or multiple pins of specified GPIO port. + * It could be BIT0 ~ BIT15 for PA, PB, PC, PD, PF and PH GPIO port. + * It could be BIT0 ~ BIT13 for PE GPIO port. + * It could be BIT0 ~ BIT11 for PG GPIO port. + * @return None + * + * @details Enable the interrupt de-bounce function of specified GPIO pin. + * \hideinitializer + */ +#define GPIO_ENABLE_DEBOUNCE(port, u32PinMask) ((port)->DBEN |= (u32PinMask)) + +/** + * @brief Disable I/O Digital Input Path + * + * @param[in] port GPIO port. It could be PA, PB, PC, PD, PE, PF, PG, PH, PI, PJ, PK,PL, PM and PN. + * @param[in] u32PinMask The single or multiple pins of specified GPIO port. + * It could be BIT0 ~ BIT15 for PA, PB, PC, PD, PF and PH GPIO port. + * It could be BIT0 ~ BIT13 for PE GPIO port. + * It could be BIT0 ~ BIT11 for PG GPIO port. + * + * @return None + * + * @details Disable I/O digital input path of specified GPIO pin. + * \hideinitializer + */ +#define GPIO_DISABLE_DIGITAL_PATH(port, u32PinMask) ((port)->DINOFF |= ((u32PinMask)<<16)) + +/** + * @brief Enable I/O Digital Input Path + * + * @param[in] port GPIO port. It could be PA, PB, PC, PD, PE, PF, PG or PH. + * @param[in] u32PinMask The single or multiple pins of specified GPIO port. + * It could be BIT0 ~ BIT15 for PA, PB, PC, PD, PF and PH GPIO port. + * It could be BIT0 ~ BIT13 for PE GPIO port. + * It could be BIT0 ~ BIT11 for PG GPIO port. + * + * @return None + * + * @details Enable I/O digital input path of specified GPIO pin. + * \hideinitializer + */ +#define GPIO_ENABLE_DIGITAL_PATH(port, u32PinMask) ((port)->DINOFF &= ~((u32PinMask)<<16)) + +/** + * @brief Disable I/O DOUT mask + * + * @param[in] port GPIO port. It could be PA, PB, PC, PD, PE, PF, PG, PH, PI, PJ, PK,PL, PM and PN. + * @param[in] u32PinMask The single or multiple pins of specified GPIO port. + * It could be BIT0 ~ BIT15 for PA, PB, PC, PD, PF and PH GPIO port. + * It could be BIT0 ~ BIT13 for PE GPIO port. + * It could be BIT0 ~ BIT11 for PG GPIO port. + * + * @return None + * + * @details Disable I/O DOUT mask of specified GPIO pin. + * \hideinitializer + */ +#define GPIO_DISABLE_DOUT_MASK(port, u32PinMask) ((port)->DATMSK &= ~(u32PinMask)) + +/** + * @brief Enable I/O DOUT mask + * + * @param[in] port GPIO port. It could be PA, PB, PC, PD, PE, PF, PG or PH. + * @param[in] u32PinMask The single or multiple pins of specified GPIO port. + * It could be BIT0 ~ BIT15 for PA, PB, PC, PD, PF and PH GPIO port. + * It could be BIT0 ~ BIT13 for PE GPIO port. + * It could be BIT0 ~ BIT11 for PG GPIO port. + * + * @return None + * + * @details Enable I/O DOUT mask of specified GPIO pin. + * \hideinitializer + */ +#define GPIO_ENABLE_DOUT_MASK(port, u32PinMask) ((port)->DATMSK |= (u32PinMask)) + +/** + * @brief Get GPIO Pin Interrupt Flag + * + * @param[in] port GPIO port. It could be PA, PB, PC, PD, PE, PF, PG, PH, PI, PJ, PK,PL, PM and PN. + * @param[in] u32PinMask The single or multiple pins of specified GPIO port. + * It could be BIT0 ~ BIT15 for PA, PB, PC, PD, PF and PH GPIO port. + * It could be BIT0 ~ BIT13 for PE GPIO port. + * It could be BIT0 ~ BIT11 for PG GPIO port. + * + * @retval 0 No interrupt at specified GPIO pin + * @retval 1 The specified GPIO pin generate an interrupt + * + * @details Get the interrupt status of specified GPIO pin. + * \hideinitializer + */ +#define GPIO_GET_INT_FLAG(port, u32PinMask) ((port)->INTSRC & (u32PinMask)) + +/** + * @brief Set De-bounce Sampling Cycle Time + * + * @param[in] u32Port GPIO port. It could be PA, PB, PC, PD, PE, PF, PG, PH, PI, PJ, PK,PL, PM and PN. + * @param[in] u32ClkSrc The de-bounce counter clock source. It could be GPIO_DBCTL_DBCLKSRC_HXT or GPIO_DBCTL_DBCLKSRC_LIRC. + * @param[in] u32ClkSel The de-bounce sampling cycle selection. It could be + * - \ref GPIO_DBCTL_DBCLKSEL_1 + * - \ref GPIO_DBCTL_DBCLKSEL_2 + * - \ref GPIO_DBCTL_DBCLKSEL_4 + * - \ref GPIO_DBCTL_DBCLKSEL_8 + * - \ref GPIO_DBCTL_DBCLKSEL_16 + * - \ref GPIO_DBCTL_DBCLKSEL_32 + * - \ref GPIO_DBCTL_DBCLKSEL_64 + * - \ref GPIO_DBCTL_DBCLKSEL_128 + * - \ref GPIO_DBCTL_DBCLKSEL_256 + * - \ref GPIO_DBCTL_DBCLKSEL_512 + * - \ref GPIO_DBCTL_DBCLKSEL_1024 + * - \ref GPIO_DBCTL_DBCLKSEL_2048 + * - \ref GPIO_DBCTL_DBCLKSEL_4096 + * - \ref GPIO_DBCTL_DBCLKSEL_8192 + * - \ref GPIO_DBCTL_DBCLKSEL_16384 + * - \ref GPIO_DBCTL_DBCLKSEL_32768 + * + * @return None + * + * @details Set the interrupt de-bounce sampling cycle time based on the debounce counter clock source. \n + * Example: _GPIO_SET_DEBOUNCE_TIME(GPIO_DBCTL_DBCLKSRC_LIRC, GPIO_DBCTL_DBCLKSEL_4). \n + * It's meaning the De-debounce counter clock source is internal 10 KHz and sampling cycle selection is 4. \n + * Then the target de-bounce sampling cycle time is (4)*(1/(10*1000)) s = 4*0.0001 s = 400 us, + * and system will sampling interrupt input once per 00 us. + * \hideinitializer + */ +#define GPIO_SET_DEBOUNCE_TIME(u32Port, u32ClkSrc, u32ClkSel) (u32Port->DBCTL = (GPIO_DBCTL_ICLKON_Msk | (u32ClkSrc) | (u32ClkSel))) + +/** + * @brief Get GPIO Port IN Data + * + * @param[in] port GPIO port. It could be PA, PB, PC, PD, PE, PF, PG, PH, PI, PJ, PK,PL, PM and PN. + * + * @return The specified port data + * + * @details Get the PIN register of specified GPIO port. + * \hideinitializer + */ +#define GPIO_GET_IN_DATA(port) ((port)->PIN) + +/** + * @brief Set GPIO Port OUT Data + * + * @param[in] port GPIO port. It could be PA, PB, PC, PD, PE, PF, PG, PH, PI, PJ, PK,PL, PM and PN. + * @param[in] u32Data GPIO port data. + * + * @return None + * + * @details Set the Data into specified GPIO port. + * \hideinitializer + */ +#define GPIO_SET_OUT_DATA(port, u32Data) ((port)->DOUT = (u32Data)) + +/** + * @brief Toggle Specified GPIO pin + * + * @param[in] u32Pin Pxy + * + * @return None + * + * @details Toggle the specified GPIO pint. + * \hideinitializer + */ +#define GPIO_TOGGLE(u32Pin) ((u32Pin) ^= 1) + + +/** + * @brief Enable External GPIO interrupt + * + * @param[in] port GPIO port. It could be PA, PB, PC, PD, PE, PF, PG, PH, PI, PJ, PK,PL, PM and PN. + * @param[in] u32Pin The pin of specified GPIO port. + * It could be 0 ~ 15 for PA, PB, PC, PD, PF and PH GPIO port. + * It could be 0 ~ 13 for PE GPIO port. + * It could be 0 ~ 11 for PG GPIO port. + * @param[in] u32IntAttribs The interrupt attribute of specified GPIO pin. It could be \n + * GPIO_INT_RISING, GPIO_INT_FALLING, GPIO_INT_BOTH_EDGE, GPIO_INT_HIGH, GPIO_INT_LOW. + * + * @return None + * + * @details This function is used to enable specified GPIO pin interrupt. + * \hideinitializer + */ +#define GPIO_EnableEINT GPIO_EnableInt + +/** + * @brief Disable External GPIO interrupt + * + * @param[in] port GPIO port. It could be PA, PB, PC, PD, PE, PF, PG, PH, PI, PJ, PK,PL, PM and PN. + * @param[in] u32Pin The pin of specified GPIO port. + * It could be 0 ~ 15 for PA, PB, PC, PD, PF and PH GPIO port. + * It could be 0 ~ 13 for PE GPIO port. + * It could be 0 ~ 11 for PG GPIO port. + * + * @return None + * + * @details This function is used to enable specified GPIO pin interrupt. + * \hideinitializer + */ +#define GPIO_DisableEINT GPIO_DisableInt + + +void GPIO_SetMode(GPIO_T *port, uint32_t u32PinMask, uint32_t u32Mode); +void GPIO_EnableInt(GPIO_T *port, uint32_t u32Pin, uint32_t u32IntAttribs); +void GPIO_DisableInt(GPIO_T *port, uint32_t u32Pin); +void GPIO_SetSlewCtl(GPIO_T *port, uint32_t u32PinMask, uint32_t u32Mode); +void GPIO_SetPullCtl(GPIO_T *port, uint32_t u32PinMask, uint32_t u32Mode); +void GPIO_SetDrivingCtl(GPIO_T *port, uint32_t u32PinMask, uint32_t u32Driving); +void GPIO_SetSchmittTriggere(GPIO_T *port, uint32_t u32PinMask, uint32_t u32SchmittTrigger); +void GPIO_SetPowerMode(GPIO_T *port, uint32_t u32PinMask, uint32_t u32PowerMode); +uint32_t GPIO_GetPowerMode(GPIO_T *port, uint32_t u32PinNo); +uint32_t GPIO_GetSchmittTriggere(GPIO_T *port, uint32_t u32PinNo); +uint32_t GPIO_GetDrivingCtl(GPIO_T *port, uint32_t u32PinNo); + + +/*@}*/ /* end of group GPIO_EXPORTED_FUNCTIONS */ + +/*@}*/ /* end of group GPIO_Driver */ + +/*@}*/ /* end of group Standard_Driver */ + + +#ifdef __cplusplus +} +#endif + +#endif /* __GPIO_H__ */ diff --git a/bsp/nuvoton/libraries/ma35/StdDriver/inc/nu_hwsem.h b/bsp/nuvoton/libraries/ma35/StdDriver/inc/nu_hwsem.h new file mode 100644 index 0000000000..551df1471d --- /dev/null +++ b/bsp/nuvoton/libraries/ma35/StdDriver/inc/nu_hwsem.h @@ -0,0 +1,174 @@ +/**************************************************************************//** + * @file nu_hwsem.h + * @brief HWSEM driver header file + * + * SPDX-License-Identifier: Apache-2.0 + * @copyright (C) 2020 Nuvoton Technology Corp. All rights reserved. + *****************************************************************************/ +#ifndef __NU_HWSEM_H__ +#define __NU_HWSEM_H__ + +#ifdef __cplusplus +extern "C" +{ +#endif + + +/** @addtogroup Standard_Driver Standard Driver + @{ +*/ + +/** @addtogroup HWSEM_Driver HWSEM Driver + @{ +*/ + +/** @addtogroup HWSEM_EXPORTED_CONSTANTS HWSEM Exported Constants + @{ +*/ +#define HWSEM_CNT 8ul /*!CTL |= (HWSEM_CTL_SEM0RST_Msk << (u32Num))) + +/** + * @brief + * + * @param[in] hwsem The pointer of the specified HWSEM module. + * @param[in] u32Num HWSEM number, valid values are between 0~7 + * + * @retval 0 The specified semaphore is not locked. + * Otherwise The specified semaphore is locked. + * \hideinitializer + */ +#define HWSEM_IS_LOCKED(hwsem, u32Num) ((hwsem)->SEM[(u32Num)] & (HWSEM_SEM_ID_Msk)) + +/** + * @brief Enable specified HWSEM interrupt + * + * @param[in] hwsem The pointer of the specified HWSEM module. + * @param[in] u32Num HWSEM number, valid values are between 0~7 + * + * + * \hideinitializer + */ +#define HWSEM_ENABLE_INT(hwsem, u32Num) ((hwsem)->INTENM4 |= (HWSEM_INTENM4_SEM0IEN_Msk << (u32Num))) + + +/** + * @brief Disable specified HWSEM interrupt + * + * @param[in] hwsem The pointer of the specified HWSEM module. + * @param[in] u32Num HWSEM number, valid values are between 0~7 + * + * + * \hideinitializer + */ +#define HWSEM_DISABLE_INT(hwsem, u32Num) ((hwsem)->INTENM4 &= ~(HWSEM_INTENM4_SEM0IEN_Msk << (u32Num))) + +/** + * @brief Get specified interrupt flag + * + * @param[in] hwsem The pointer of the specified HWSEM module. + * @param[in] u32Num HWSEM number, valid values are between 0~7 + * + * @retval 0 The specified interrupt is not happened. + * Otherwise The specified interrupt is happened. + * \hideinitializer + */ +#define HWSEM_GET_INT_FLAG(hwsem, u32Num) ((hwsem)->INTSTSM4 & (HWSEM_INTSTSM4_SEM0IF_Msk << (u32Num))) + + +/** + * @brief Clear specified interrupt flag + * + * @param[in] hwsem The pointer of the specified HWSEM module. + * @param[in] u32Num HWSEM number, valid values are between 0~7 + * + * \hideinitializer + */ +#define HWSEM_CLR_INT_FLAG(hwsem, u32Num) ((hwsem)->INTSTSM4 = (HWSEM_INTSTSM4_SEM0IF_Msk << (u32Num))) + + +/** + * @brief Unlock specified semaphore + * + * @param[in] hwsem The pointer of the specified HWSEM module. + * @param[in] u32Num HWSEM number, valid values are between 0~7 + * @param[in] u8Key HWSEM channel key + * + * \hideinitializer + */ +#define HWSEM_UNLOCK(hwsem, u32Num, u8Key) ((hwsem)->SEM[(u32Num)] = ((u8Key) << HWSEM_SEM_KEY_Pos) & HWSEM_SEM_KEY_Msk) + +/* Declare these inline functions here to avoid MISRA C 2004 rule 8.1 error */ +__STATIC_INLINE int32_t HWSEM_Try_Lock(HWSEM_T *hwsem, uint32_t u32Num, uint8_t u8Key); +__STATIC_INLINE void HWSEM_Spin_Lock(HWSEM_T *hwsem, uint32_t u32Num, uint8_t u8Key); + +/** + * @brief Try to lock specified semaphore + * + * @param[in] hwsem The pointer of the specified HWSEM module. + * @param[in] u32Num HWSEM number, valid values are between 0~7 + * @param[in] u8Key HWSEM channel key + * @retval 0 Successfully acquire semaphore + * @retval -1 Failed to acquire semaphore + * \hideinitializer + */ +__STATIC_INLINE int32_t HWSEM_Try_Lock(HWSEM_T *hwsem, uint32_t u32Num, uint8_t u8Key) +{ + hwsem->SEM[u32Num] = (u8Key << HWSEM_SEM_KEY_Pos); + if ((hwsem->SEM[u32Num] & HWSEM_SEM_ID_Msk) == HWSEM_LOCK_BY_M4 && + (hwsem->SEM[u32Num] & HWSEM_SEM_KEY_Msk) == (u8Key << HWSEM_SEM_KEY_Pos)) + return 0; + else + return -1; +} + +/** + * @brief Spin until lock specified semaphore + * + * @param[in] hwsem The pointer of the specified HWSEM module. + * @param[in] u32Num HWSEM number, valid values are between 0~7 + * @param[in] u8Key HWSEM channel key + * + * \hideinitializer + */ +__STATIC_INLINE void HWSEM_Spin_Lock(HWSEM_T *hwsem, uint32_t u32Num, uint8_t u8Key) +{ + while (1) + { + hwsem->SEM[u32Num] = (u8Key << HWSEM_SEM_KEY_Pos); + if ((hwsem->SEM[u32Num] & HWSEM_SEM_ID_Msk) == HWSEM_LOCK_BY_M4 && + (hwsem->SEM[u32Num] & HWSEM_SEM_KEY_Msk) == (u8Key << HWSEM_SEM_KEY_Pos)) + break; + } +} + +/*@}*/ /* end of group HWSEM_EXPORTED_FUNCTIONS */ + +/*@}*/ /* end of group HWSEM_Driver */ + +/*@}*/ /* end of group Standard_Driver */ + +#ifdef __cplusplus +} +#endif + +#endif + diff --git a/bsp/nuvoton/libraries/ma35/StdDriver/inc/nu_i2c.h b/bsp/nuvoton/libraries/ma35/StdDriver/inc/nu_i2c.h new file mode 100644 index 0000000000..373b02d8c7 --- /dev/null +++ b/bsp/nuvoton/libraries/ma35/StdDriver/inc/nu_i2c.h @@ -0,0 +1,296 @@ +/****************************************************************************//** + * @file nu_i2c.h + * @brief I2C driver header file + * + * SPDX-License-Identifier: Apache-2.0 + * @copyright (C) 2020 Nuvoton Technology Corp. All rights reserved. + *****************************************************************************/ +#ifndef __NU_I2C_H__ +#define __NU_I2C_H__ + +#ifdef __cplusplus +extern "C" +{ +#endif + + +/** @addtogroup Standard_Driver Standard Driver + @{ +*/ + +/** @addtogroup I2C_Driver I2C Driver + @{ +*/ + +/** @addtogroup I2C_EXPORTED_CONSTANTS I2C Exported Constants + @{ +*/ + +/*---------------------------------------------------------------------------------------------------------*/ +/* I2C_CTL constant definitions. */ +/*---------------------------------------------------------------------------------------------------------*/ +#define I2C_CTL_STA_SI 0x28UL /*!< I2C_CTL setting for I2C control bits. It would set STA and SI bits \hideinitializer */ +#define I2C_CTL_STA_SI_AA 0x2CUL /*!< I2C_CTL setting for I2C control bits. It would set STA, SI and AA bits \hideinitializer */ +#define I2C_CTL_STO_SI 0x18UL /*!< I2C_CTL setting for I2C control bits. It would set STO and SI bits \hideinitializer */ +#define I2C_CTL_STO_SI_AA 0x1CUL /*!< I2C_CTL setting for I2C control bits. It would set STO, SI and AA bits \hideinitializer */ +#define I2C_CTL_SI 0x08UL /*!< I2C_CTL setting for I2C control bits. It would set SI bit \hideinitializer */ +#define I2C_CTL_SI_AA 0x0CUL /*!< I2C_CTL setting for I2C control bits. It would set SI and AA bits \hideinitializer */ +#define I2C_CTL_STA 0x20UL /*!< I2C_CTL setting for I2C control bits. It would set STA bit \hideinitializer */ +#define I2C_CTL_STO 0x10UL /*!< I2C_CTL setting for I2C control bits. It would set STO bit \hideinitializer */ +#define I2C_CTL_AA 0x04UL /*!< I2C_CTL setting for I2C control bits. It would set AA bit \hideinitializer */ + +/*---------------------------------------------------------------------------------------------------------*/ +/* I2C GCMode constant definitions. */ +/*---------------------------------------------------------------------------------------------------------*/ +#define I2C_GCMODE_ENABLE 1 /*!< Enable I2C GC Mode \hideinitializer */ +#define I2C_GCMODE_DISABLE 0 /*!< Disable I2C GC Mode \hideinitializer */ + +/*@}*/ /* end of group I2C_EXPORTED_CONSTANTS */ + +/** @addtogroup I2C_EXPORTED_FUNCTIONS I2C Exported Functions + @{ +*/ +/** + * @brief The macro is used to set I2C bus condition at One Time + * + * @param[in] i2c Specify I2C port + * @param[in] u8Ctrl A byte writes to I2C control register + * + * @return None + * + * @details Set I2C_CTL register to control I2C bus conditions of START, STOP, SI, ACK. + * \hideinitializer + */ +#define I2C_SET_CONTROL_REG(i2c, u8Ctrl) ((i2c)->CTL0 = ((i2c)->CTL0 & ~0x3c) | (u8Ctrl)) + +/** + * @brief The macro is used to set START condition of I2C Bus + * + * @param[in] i2c Specify I2C port + * + * @return None + * + * @details Set the I2C bus START condition in I2C_CTL register. + * \hideinitializer + */ +#define I2C_START(i2c) ((i2c)->CTL0 = ((i2c)->CTL0 & ~I2C_CTL0_SI_Msk) | I2C_CTL0_STA_Msk) + +/** + * @brief The macro is used to wait I2C bus status get ready + * + * @param[in] i2c Specify I2C port + * + * @return None + * + * @details When a new status is presented of I2C bus, the SI flag will be set in I2C_CTL register. + * \hideinitializer + */ +#define I2C_WAIT_READY(i2c) while(!((i2c)->CTL0 & I2C_CTL0_SI_Msk)) + +/** + * @brief The macro is used to Read I2C Bus Data Register + * + * @param[in] i2c Specify I2C port + * + * @return A byte of I2C data register + * + * @details I2C controller read data from bus and save it in I2CDAT register. + * \hideinitializer + */ +#define I2C_GET_DATA(i2c) ((i2c)->DAT) + +/** + * @brief Write a Data to I2C Data Register + * + * @param[in] i2c Specify I2C port + * @param[in] u8Data A byte that writes to data register + * + * @return None + * + * @details When write a data to I2C_DAT register, the I2C controller will shift it to I2C bus. + * \hideinitializer + */ +#define I2C_SET_DATA(i2c, u8Data) ((i2c)->DAT = (u8Data)) + +/** + * @brief Get I2C Bus status code + * + * @param[in] i2c Specify I2C port + * + * @return I2C status code + * + * @details To get this status code to monitor I2C bus event. + * \hideinitializer + */ +#define I2C_GET_STATUS(i2c) ((i2c)->STATUS0) + +/** + * @brief Get Time-out flag from I2C Bus + * + * @param[in] i2c Specify I2C port + * + * @retval 0 I2C Bus time-out is not happened + * @retval 1 I2C Bus time-out is happened + * + * @details When I2C bus occurs time-out event, the time-out flag will be set. + * \hideinitializer + */ +#define I2C_GET_TIMEOUT_FLAG(i2c) ( ((i2c)->TOCTL & I2C_TOCTL_TOIF_Msk) == I2C_TOCTL_TOIF_Msk ? 1:0 ) + +/** + * @brief To get wake-up flag from I2C Bus + * + * @param[in] i2c Specify I2C port + * + * @retval 0 Chip is not woken-up from power-down mode + * @retval 1 Chip is woken-up from power-down mode + * + * @details I2C bus occurs wake-up event, wake-up flag will be set. + * \hideinitializer + */ +#define I2C_GET_WAKEUP_FLAG(i2c) ( ((i2c)->WKSTS & I2C_WKSTS_WKIF_Msk) == I2C_WKSTS_WKIF_Msk ? 1:0 ) + +/** + * @brief To clear wake-up flag + * + * @param[in] i2c Specify I2C port + * + * @return None + * + * @details If wake-up flag is set, use this macro to clear it. + * \hideinitializer + */ +#define I2C_CLEAR_WAKEUP_FLAG(i2c) ((i2c)->WKSTS = I2C_WKSTS_WKIF_Msk) + +/** + * @brief Enable RX PDMA function. + * @param[in] i2c The pointer of the specified I2C module. + * @return None. + * @details Set RXPDMAEN bit of I2C_CTL1 register to enable RX PDMA transfer function. + * \hideinitializer + */ +#define I2C_ENABLE_RX_PDMA(i2c) ((i2c)->CTL1 |= I2C_CTL1_RXPDMAEN_Msk) + +/** + * @brief Enable TX PDMA function. + * @param[in] i2c The pointer of the specified I2C module. + * @return None. + * @details Set TXPDMAEN bit of I2C_CTL1 register to enable TX PDMA transfer function. + * \hideinitializer + */ +#define I2C_ENABLE_TX_PDMA(i2c) ((i2c)->CTL1 |= I2C_CTL1_TXPDMAEN_Msk) + +/** + * @brief Disable RX PDMA transfer. + * @param[in] i2c The pointer of the specified I2C module. + * @return None. + * @details Clear RXPDMAEN bit of I2C_CTL1 register to disable RX PDMA transfer function. + * \hideinitializer + */ +#define I2C_DISABLE_RX_PDMA(i2c) ((i2c)->CTL1 &= ~I2C_CTL1_RXPDMAEN_Msk) + +/** + * @brief Disable TX PDMA transfer. + * @param[in] i2c The pointer of the specified I2C module. + * @return None. + * @details Clear TXPDMAEN bit of I2C_CTL1 register to disable TX PDMA transfer function. + * \hideinitializer + */ +#define I2C_DISABLE_TX_PDMA(i2c) ((i2c)->CTL1 &= ~I2C_CTL1_TXPDMAEN_Msk) + +/** + * @brief Enable PDMA stretch function. + * @param[in] i2c The pointer of the specified I2C module. + * @return None. + * @details Enable this function is to stretch bus by hardware after PDMA transfer is done if SI is not cleared. + * \hideinitializer + */ +#define I2C_ENABLE_PDMA_STRETCH(i2c) ((i2c)->CTL1 |= I2C_CTL1_PDMASTR_Msk) + +/** + * @brief Disable PDMA stretch function. + * @param[in] i2c The pointer of the specified I2C module. + * @return None. + * @details I2C will send STOP after PDMA transfers done automatically. + * \hideinitializer + */ +#define I2C_DISABLE_PDMA_STRETCH(i2c) ((i2c)->CTL1 &= ~I2C_CTL1_PDMASTR_Msk) + +/** + * @brief Reset PDMA function. + * @param[in] i2c The pointer of the specified I2C module. + * @return None. + * @details I2C PDMA engine will be reset after this function is called. + * \hideinitializer + */ +#define I2C_DISABLE_RST_PDMA(i2c) ((i2c)->CTL1 |= I2C_CTL1_PDMARST_Msk) + +/*---------------------------------------------------------------------------------------------------------*/ +/* inline functions */ +/*---------------------------------------------------------------------------------------------------------*/ + +/* Declare these inline functions here to avoid MISRA C 2004 rule 8.1 error */ +__STATIC_INLINE void I2C_STOP(I2C_T *i2c); + +/** + * @brief The macro is used to set STOP condition of I2C Bus + * + * @param[in] i2c Specify I2C port + * + * @return None + * + * @details Set the I2C bus STOP condition in I2C_CTL register. + */ +__STATIC_INLINE void I2C_STOP(I2C_T *i2c) +{ + + (i2c)->CTL0 |= (I2C_CTL0_SI_Msk | I2C_CTL0_STO_Msk); + while (i2c->CTL0 & I2C_CTL0_STO_Msk) + { + } +} + +void I2C_ClearTimeoutFlag(I2C_T *i2c); +void I2C_Close(I2C_T *i2c); +void I2C_Trigger(I2C_T *i2c, uint8_t u8Start, uint8_t u8Stop, uint8_t u8Si, uint8_t u8Ack); +void I2C_DisableInt(I2C_T *i2c); +void I2C_EnableInt(I2C_T *i2c); +uint32_t I2C_GetBusClockFreq(I2C_T *i2c); +uint32_t I2C_GetIntFlag(I2C_T *i2c); +uint32_t I2C_GetStatus(I2C_T *i2c); +uint32_t I2C_Open(I2C_T *i2c, uint32_t u32BusClock); +uint8_t I2C_GetData(I2C_T *i2c); +void I2C_SetSlaveAddr(I2C_T *i2c, uint8_t u8SlaveNo, uint8_t u8SlaveAddr, uint8_t u8GCMode); +void I2C_SetSlaveAddrMask(I2C_T *i2c, uint8_t u8SlaveNo, uint8_t u8SlaveAddrMask); +uint32_t I2C_SetBusClockFreq(I2C_T *i2c, uint32_t u32BusClock); +void I2C_EnableTimeout(I2C_T *i2c, uint8_t u8LongTimeout); +void I2C_DisableTimeout(I2C_T *i2c); +void I2C_EnableWakeup(I2C_T *i2c); +void I2C_DisableWakeup(I2C_T *i2c); +void I2C_SetData(I2C_T *i2c, uint8_t u8Data); +uint8_t I2C_WriteByte(I2C_T *i2c, uint8_t u8SlaveAddr, uint8_t data); +uint32_t I2C_WriteMultiBytes(I2C_T *i2c, uint8_t u8SlaveAddr, uint8_t data[], uint32_t u32wLen); +uint8_t I2C_WriteByteOneReg(I2C_T *i2c, uint8_t u8SlaveAddr, uint8_t u8DataAddr, uint8_t data); +uint32_t I2C_WriteMultiBytesOneReg(I2C_T *i2c, uint8_t u8SlaveAddr, uint8_t u8DataAddr, uint8_t data[], uint32_t u32wLen); +uint8_t I2C_WriteByteTwoRegs(I2C_T *i2c, uint8_t u8SlaveAddr, uint16_t u16DataAddr, uint8_t data); +uint32_t I2C_WriteMultiBytesTwoRegs(I2C_T *i2c, uint8_t u8SlaveAddr, uint16_t u16DataAddr, uint8_t data[], uint32_t u32wLen); +uint8_t I2C_ReadByte(I2C_T *i2c, uint8_t u8SlaveAddr); +uint32_t I2C_ReadMultiBytes(I2C_T *i2c, uint8_t u8SlaveAddr, uint8_t rdata[], uint32_t u32rLen); +uint8_t I2C_ReadByteOneReg(I2C_T *i2c, uint8_t u8SlaveAddr, uint8_t u8DataAddr); +uint32_t I2C_ReadMultiBytesOneReg(I2C_T *i2c, uint8_t u8SlaveAddr, uint8_t u8DataAddr, uint8_t rdata[], uint32_t u32rLen); +uint8_t I2C_ReadByteTwoRegs(I2C_T *i2c, uint8_t u8SlaveAddr, uint16_t u16DataAddr); +uint32_t I2C_ReadMultiBytesTwoRegs(I2C_T *i2c, uint8_t u8SlaveAddr, uint16_t u16DataAddr, uint8_t rdata[], uint32_t u32rLen); + +/*@}*/ /* end of group I2C_EXPORTED_FUNCTIONS */ + +/*@}*/ /* end of group I2C_Driver */ + +/*@}*/ /* end of group Standard_Driver */ + +#ifdef __cplusplus +} +#endif + +#endif + + diff --git a/bsp/nuvoton/libraries/ma35/StdDriver/inc/nu_i2s.h b/bsp/nuvoton/libraries/ma35/StdDriver/inc/nu_i2s.h new file mode 100644 index 0000000000..b5ac0b597a --- /dev/null +++ b/bsp/nuvoton/libraries/ma35/StdDriver/inc/nu_i2s.h @@ -0,0 +1,351 @@ +/****************************************************************************//** + * @file nu_i2s.h + * @brief I2S driver header file + * + * SPDX-License-Identifier: Apache-2.0 + * @copyright (C) 2020 Nuvoton Technology Corp. All rights reserved. + *****************************************************************************/ +#ifndef __NU_I2S_H__ +#define __NU_I2S_H__ + +#ifdef __cplusplus +extern "C" +{ +#endif + +/** @addtogroup Standard_Driver Standard Driver + @{ +*/ + +/** @addtogroup I2S_Driver I2S Driver + @{ +*/ + +/** @addtogroup I2S_EXPORTED_CONSTANTS I2S Exported Constants + @{ +*/ +#define I2S_DATABIT_8 (0U << I2S_CTL0_DATWIDTH_Pos) /*!< I2S data width is 8-bit \hideinitializer */ +#define I2S_DATABIT_16 (1U << I2S_CTL0_DATWIDTH_Pos) /*!< I2S data width is 16-bit \hideinitializer */ +#define I2S_DATABIT_24 (2U << I2S_CTL0_DATWIDTH_Pos) /*!< I2S data width is 24-bit \hideinitializer */ +#define I2S_DATABIT_32 (3U << I2S_CTL0_DATWIDTH_Pos) /*!< I2S data width is 32-bit \hideinitializer */ + +/* Audio Format */ +#define I2S_ENABLE_MONO I2S_CTL0_MONO_Msk /*!< Mono channel \hideinitializer */ +#define I2S_DISABLE_MONO (0U) /*!< Stereo channel \hideinitializer */ + +/* I2S Data Format */ +#define I2S_FORMAT_I2S (0U << I2S_CTL0_FORMAT_Pos) /*!< I2S data format \hideinitializer */ +#define I2S_FORMAT_I2S_MSB (1U << I2S_CTL0_FORMAT_Pos) /*!< I2S MSB data format \hideinitializer */ +#define I2S_FORMAT_I2S_LSB (2U << I2S_CTL0_FORMAT_Pos) /*!< I2S LSB data format \hideinitializer */ +#define I2S_FORMAT_PCM (4U << I2S_CTL0_FORMAT_Pos) /*!< PCM data format \hideinitializer */ +#define I2S_FORMAT_PCM_MSB (5U << I2S_CTL0_FORMAT_Pos) /*!< PCM MSB data format \hideinitializer */ +#define I2S_FORMAT_PCM_LSB (6U << I2S_CTL0_FORMAT_Pos) /*!< PCM LSB data format \hideinitializer */ + +/* I2S Data Format */ +#define I2S_ORDER_AT_MSB (0U) /*!< Channel data is at MSB \hideinitializer */ +#define I2S_ORDER_AT_LSB I2S_CTL0_ORDER_Msk /*!< Channel data is at LSB \hideinitializer */ + +/* I2S TDM Channel Number */ +#define I2S_TDM_2CH 0U /*!< Use TDM 2 channel \hideinitializer */ +#define I2S_TDM_4CH 1U /*!< Use TDM 4 channel \hideinitializer */ +#define I2S_TDM_6CH 2U /*!< Use TDM 6 channel \hideinitializer */ +#define I2S_TDM_8CH 3U /*!< Use TDM 8 channel \hideinitializer */ + +/* I2S TDM Channel Width */ +#define I2S_TDM_WIDTH_8BIT 0U /*!< TDM channel witch is 8-bit \hideinitializer */ +#define I2S_TDM_WIDTH_16BIT 1U /*!< TDM channel witch is 16-bit \hideinitializer */ +#define I2S_TDM_WIDTH_24BIT 2U /*!< TDM channel witch is 24-bit \hideinitializer */ +#define I2S_TDM_WIDTH_32BIT 3U /*!< TDM channel witch is 32-bit \hideinitializer */ + +/* I2S TDM Sync Width */ +#define I2S_TDM_SYNC_ONE_BCLK 0U /*!< TDM sync widht is one BLCK period \hideinitializer */ +#define I2S_TDM_SYNC_ONE_CHANNEL 1U /*!< TDM sync widht is one channel period \hideinitializer */ + +/* I2S Operation mode */ +#define I2S_MODE_SLAVE I2S_CTL0_SLAVE_Msk /*!< As slave mode \hideinitializer */ +#define I2S_MODE_MASTER (0u) /*!< As master mode \hideinitializer */ + +/* I2S FIFO Threshold */ +#define I2S_FIFO_TX_LEVEL_WORD_0 (0U) /*!< TX threshold is 0 word \hideinitializer */ +#define I2S_FIFO_TX_LEVEL_WORD_1 (1U << I2S_CTL1_TXTH_Pos) /*!< TX threshold is 1 word \hideinitializer */ +#define I2S_FIFO_TX_LEVEL_WORD_2 (2U << I2S_CTL1_TXTH_Pos) /*!< TX threshold is 2 words \hideinitializer */ +#define I2S_FIFO_TX_LEVEL_WORD_3 (3U << I2S_CTL1_TXTH_Pos) /*!< TX threshold is 3 words \hideinitializer */ +#define I2S_FIFO_TX_LEVEL_WORD_4 (4U << I2S_CTL1_TXTH_Pos) /*!< TX threshold is 4 words \hideinitializer */ +#define I2S_FIFO_TX_LEVEL_WORD_5 (5U << I2S_CTL1_TXTH_Pos) /*!< TX threshold is 5 words \hideinitializer */ +#define I2S_FIFO_TX_LEVEL_WORD_6 (6U << I2S_CTL1_TXTH_Pos) /*!< TX threshold is 6 words \hideinitializer */ +#define I2S_FIFO_TX_LEVEL_WORD_7 (7U << I2S_CTL1_TXTH_Pos) /*!< TX threshold is 7 words \hideinitializer */ +#define I2S_FIFO_TX_LEVEL_WORD_8 (8U << I2S_CTL1_TXTH_Pos) /*!< TX threshold is 8 words \hideinitializer */ +#define I2S_FIFO_TX_LEVEL_WORD_9 (9U << I2S_CTL1_TXTH_Pos) /*!< TX threshold is 9 words \hideinitializer */ +#define I2S_FIFO_TX_LEVEL_WORD_10 (10U << I2S_CTL1_TXTH_Pos) /*!< TX threshold is 10 words \hideinitializer */ +#define I2S_FIFO_TX_LEVEL_WORD_11 (11U << I2S_CTL1_TXTH_Pos) /*!< TX threshold is 11 words \hideinitializer */ +#define I2S_FIFO_TX_LEVEL_WORD_12 (12U << I2S_CTL1_TXTH_Pos) /*!< TX threshold is 12 words \hideinitializer */ +#define I2S_FIFO_TX_LEVEL_WORD_13 (13U << I2S_CTL1_TXTH_Pos) /*!< TX threshold is 13 words \hideinitializer */ +#define I2S_FIFO_TX_LEVEL_WORD_14 (14U << I2S_CTL1_TXTH_Pos) /*!< TX threshold is 14 words \hideinitializer */ +#define I2S_FIFO_TX_LEVEL_WORD_15 (15U << I2S_CTL1_TXTH_Pos) /*!< TX threshold is 15 words \hideinitializer */ + +#define I2S_FIFO_RX_LEVEL_WORD_1 (0U) /*!< RX threshold is 1 word \hideinitializer */ +#define I2S_FIFO_RX_LEVEL_WORD_2 (1U << I2S_CTL1_RXTH_Pos) /*!< RX threshold is 2 words \hideinitializer */ +#define I2S_FIFO_RX_LEVEL_WORD_3 (2U << I2S_CTL1_RXTH_Pos) /*!< RX threshold is 3 words \hideinitializer */ +#define I2S_FIFO_RX_LEVEL_WORD_4 (3U << I2S_CTL1_RXTH_Pos) /*!< RX threshold is 4 words \hideinitializer */ +#define I2S_FIFO_RX_LEVEL_WORD_5 (4U << I2S_CTL1_RXTH_Pos) /*!< RX threshold is 5 words \hideinitializer */ +#define I2S_FIFO_RX_LEVEL_WORD_6 (5U << I2S_CTL1_RXTH_Pos) /*!< RX threshold is 6 words \hideinitializer */ +#define I2S_FIFO_RX_LEVEL_WORD_7 (6U << I2S_CTL1_RXTH_Pos) /*!< RX threshold is 7 words \hideinitializer */ +#define I2S_FIFO_RX_LEVEL_WORD_8 (7U << I2S_CTL1_RXTH_Pos) /*!< RX threshold is 8 words \hideinitializer */ +#define I2S_FIFO_RX_LEVEL_WORD_9 (8U << I2S_CTL1_RXTH_Pos) /*!< RX threshold is 9 words \hideinitializer */ +#define I2S_FIFO_RX_LEVEL_WORD_10 (9U << I2S_CTL1_RXTH_Pos) /*!< RX threshold is 10 words \hideinitializer */ +#define I2S_FIFO_RX_LEVEL_WORD_11 (10U << I2S_CTL1_RXTH_Pos) /*!< RX threshold is 11 words \hideinitializer */ +#define I2S_FIFO_RX_LEVEL_WORD_12 (11U << I2S_CTL1_RXTH_Pos) /*!< RX threshold is 12 words \hideinitializer */ +#define I2S_FIFO_RX_LEVEL_WORD_13 (12U << I2S_CTL1_RXTH_Pos) /*!< RX threshold is 13 words \hideinitializer */ +#define I2S_FIFO_RX_LEVEL_WORD_14 (13U << I2S_CTL1_RXTH_Pos) /*!< RX threshold is 14 words \hideinitializer */ +#define I2S_FIFO_RX_LEVEL_WORD_15 (14U << I2S_CTL1_RXTH_Pos) /*!< RX threshold is 15 words \hideinitializer */ +#define I2S_FIFO_RX_LEVEL_WORD_16 (15U << I2S_CTL1_RXTH_Pos) /*!< RX threshold is 16 words \hideinitializer */ + +/* I2S Record Channel */ +#define I2S_MONO_RIGHT (0U) /*!< Record mono right channel \hideinitializer */ +#define I2S_MONO_LEFT I2S_CTL0_RXLCH_Msk /*!< Record mono left channel \hideinitializer */ + +/* I2S Channel */ +#define I2S_RIGHT (0U) /*!< Select right channel \hideinitializer */ +#define I2S_LEFT (1U) /*!< Select left channel \hideinitializer */ + +/*@}*/ /* end of group I2S_EXPORTED_CONSTANTS */ + +/** @addtogroup I2S_EXPORTED_FUNCTIONS I2S Exported Functions + @{ +*/ +/*---------------------------------------------------------------------------------------------------------*/ +/* inline functions */ +/*---------------------------------------------------------------------------------------------------------*/ +/** + * @brief Enable zero cross detect function. + * @param[in] i2s is the base address of I2S module. + * @param[in] u32ChMask is the mask for channel number (valid value is from (1~8). + * @return none + * \hideinitializer + */ +__STATIC_INLINE void I2S_ENABLE_TX_ZCD(I2S_T *i2s, uint32_t u32ChMask) +{ + if ((u32ChMask > 0U) && (u32ChMask < 9U)) + { + i2s->CTL1 |= ((uint32_t)1U << (u32ChMask - 1U)); + } +} + +/** + * @brief Disable zero cross detect function. + * @param[in] i2s is the base address of I2S module. + * @param[in] u32ChMask is the mask for channel number (valid value is from (1~8). + * @return none + * \hideinitializer + */ +__STATIC_INLINE void I2S_DISABLE_TX_ZCD(I2S_T *i2s, uint32_t u32ChMask) +{ + if ((u32ChMask > 0U) && (u32ChMask < 9U)) + { + i2s->CTL1 &= ~((uint32_t)1U << (u32ChMask - 1U)); + } +} + +/** + * @brief Enable I2S Tx DMA function. I2S requests DMA to transfer data to Tx FIFO. + * @param[in] i2s is the base address of I2S module. + * @return none + * \hideinitializer + */ +#define I2S_ENABLE_TXDMA(i2s) ( (i2s)->CTL0 |= I2S_CTL0_TXPDMAEN_Msk ) + +/** + * @brief Disable I2S Tx DMA function. I2S requests DMA to transfer data to Tx FIFO. + * @param[in] i2s is the base address of I2S module. + * @return none + * \hideinitializer + */ +#define I2S_DISABLE_TXDMA(i2s) ( (i2s)->CTL0 &= ~I2S_CTL0_TXPDMAEN_Msk ) + +/** + * @brief Enable I2S Rx DMA function. I2S requests DMA to transfer data from Rx FIFO. + * @param[in] i2s is the base address of I2S module. + * @return none + * \hideinitializer + */ +#define I2S_ENABLE_RXDMA(i2s) ( (i2s)->CTL0 |= I2S_CTL0_RXPDMAEN_Msk ) + +/** + * @brief Disable I2S Rx DMA function. I2S requests DMA to transfer data from Rx FIFO. + * @param[in] i2s is the base address of I2S module. + * @return none + * \hideinitializer + */ +#define I2S_DISABLE_RXDMA(i2s) ( (i2s)->CTL0 &= ~I2S_CTL0_RXPDMAEN_Msk ) + +/** + * @brief Enable I2S Tx function . + * @param[in] i2s is the base address of I2S module. + * @return none + * \hideinitializer + */ +#define I2S_ENABLE_TX(i2s) ( (i2s)->CTL0 |= I2S_CTL0_TXEN_Msk ) + +/** + * @brief Disable I2S Tx function . + * @param[in] i2s is the base address of I2S module. + * @return none + * \hideinitializer + */ +#define I2S_DISABLE_TX(i2s) ( (i2s)->CTL0 &= ~I2S_CTL0_TXEN_Msk ) + +/** + * @brief Enable I2S Rx function . + * @param[in] i2s is the base address of I2S module. + * @return none + * \hideinitializer + */ +#define I2S_ENABLE_RX(i2s) ( (i2s)->CTL0 |= I2S_CTL0_RXEN_Msk ) + +/** + * @brief Disable I2S Rx function . + * @param[in] i2s is the base address of I2S module. + * @return none + * \hideinitializer + */ +#define I2S_DISABLE_RX(i2s) ( (i2s)->CTL0 &= ~I2S_CTL0_RXEN_Msk ) + +/** + * @brief Enable Tx Mute function . + * @param[in] i2s is the base address of I2S module. + * @return none + * \hideinitializer + */ +#define I2S_ENABLE_TX_MUTE(i2s) ( (i2s)->CTL0 |= I2S_CTL0_MUTE_Msk ) + +/** + * @brief Disable Tx Mute function . + * @param[in] i2s is the base address of I2S module. + * @return none + * \hideinitializer + */ +#define I2S_DISABLE_TX_MUTE(i2s) ( (i2s)->CTL0 &= ~I2S_CTL0_MUTE_Msk ) + +/** + * @brief Clear Tx FIFO. Internal pointer is reset to FIFO start point. + * @param[in] i2s is the base address of I2S module. + * @return none + * \hideinitializer + */ +#define I2S_CLR_TX_FIFO(i2s) ( (i2s)->CTL0 |= I2S_CTL0_TXFBCLR_Msk ) + +/** + * @brief Clear Rx FIFO. Internal pointer is reset to FIFO start point. + * @param[in] i2s is the base address of I2S module. + * @return none + * \hideinitializer + */ +#define I2S_CLR_RX_FIFO(i2s) ( (i2s)->CTL0 |= I2S_CTL0_RXFBCLR_Msk ) + +/** + * @brief This function sets the recording source channel when mono mode is used. + * @param[in] i2s is the base address of I2S module. + * @param[in] u32Ch left or right channel. Valid values are: + * - \ref I2S_MONO_LEFT + * - \ref I2S_MONO_RIGHT + * @return none + * \hideinitializer + */ +__STATIC_INLINE void I2S_SET_MONO_RX_CHANNEL(I2S_T *i2s, uint32_t u32Ch) +{ + u32Ch == I2S_MONO_LEFT ? + (i2s->CTL0 |= I2S_CTL0_RXLCH_Msk) : + (i2s->CTL0 &= ~I2S_CTL0_RXLCH_Msk); +} + +/** + * @brief Write data to I2S Tx FIFO. + * @param[in] i2s is the base address of I2S module. + * @param[in] u32Data: The data written to FIFO. + * @return none + * \hideinitializer + */ +#define I2S_WRITE_TX_FIFO(i2s, u32Data) ( (i2s)->TXFIFO = (u32Data) ) + +/** + * @brief Read Rx FIFO. + * @param[in] i2s is the base address of I2S module. + * @return Data in Rx FIFO. + * \hideinitializer + */ +#define I2S_READ_RX_FIFO(i2s) ( (i2s)->RXFIFO ) + +/** + * @brief This function gets the interrupt flag according to the mask parameter. + * @param[in] i2s is the base address of I2S module. + * @param[in] u32Mask is the mask for the all interrupt flags. + * @return The masked bit value of interrupt flag. + * \hideinitializer + */ +#define I2S_GET_INT_FLAG(i2s, u32Mask) ( (i2s)->STATUS0 & (u32Mask) ) + +/** + * @brief This function clears the interrupt flag according to the mask parameter. + * @param[in] i2s is the base address of I2S module. + * @param[in] u32Mask is the mask for the all interrupt flags. + * @return none + * \hideinitializer + */ +#define I2S_CLR_INT_FLAG(i2s, u32Mask) ( (i2s)->STATUS0 |= (u32Mask) ) + +/** + * @brief This function gets the zero crossing interrupt flag according to the mask parameter. + * @param[in] i2s is the base address of I2S module. + * @param[in] u32Mask is the mask for the all interrupt flags. + * @return The masked bit value of interrupt flag. + * \hideinitializer + */ +#define I2S_GET_ZC_INT_FLAG(i2s, u32Mask) ( (i2s)->STATUS1 & (u32Mask) ) + +/** + * @brief This function clears the zero crossing interrupt flag according to the mask parameter. + * @param[in] i2s is the base address of I2S module. + * @param[in] u32Mask is the mask for the all interrupt flags. + * @return none + * \hideinitializer + */ +#define I2S_CLR_ZC_INT_FLAG(i2s, u32Mask) ( (i2s)->STATUS1 |= (u32Mask) ) + +/** + * @brief Get transmit FIFO level + * @param[in] i2s is the base address of I2S module. + * @return FIFO level + * \hideinitializer + */ +#define I2S_GET_TX_FIFO_LEVEL(i2s) ( (((i2s)->STATUS1 & I2S_STATUS1_TXCNT_Msk) >> I2S_STATUS1_TXCNT_Pos) & 0xF ) + +/** + * @brief Get receive FIFO level + * @param[in] i2s is the base address of I2S module. + * @return FIFO level + * \hideinitializer + */ +#define I2S_GET_RX_FIFO_LEVEL(i2s) ( (((i2s)->STATUS1 & I2S_STATUS1_RXCNT_Msk) >> I2S_STATUS1_RXCNT_Pos) & 0xF ) + +void I2S_Close(I2S_T *i2s); +void I2S_EnableInt(I2S_T *i2s, uint32_t u32Mask); +void I2S_DisableInt(I2S_T *i2s, uint32_t u32Mask); +uint32_t I2S_EnableMCLK(I2S_T *i2s, uint32_t u32BusClock); +void I2S_DisableMCLK(I2S_T *i2s); +void I2S_SetFIFO(I2S_T *i2s, uint32_t u32TxThreshold, uint32_t u32RxThreshold); +void I2S_ConfigureTDM(I2S_T *i2s, uint32_t u32ChannelWidth, uint32_t u32ChannelNum, uint32_t u32SyncWidth); +uint32_t I2S_Open(I2S_T *i2s, uint32_t u32MasterSlave, uint32_t u32SampleRate, uint32_t u32WordWidth, uint32_t u32MonoData, uint32_t u32DataFormat); + +/*@}*/ /* end of group I2S_EXPORTED_FUNCTIONS */ + + +/*@}*/ /* end of group I2S_Driver */ + +/*@}*/ /* end of group Standard_Driver */ +#ifdef __cplusplus +} +#endif + +#endif + + diff --git a/bsp/nuvoton/libraries/ma35/StdDriver/inc/nu_kpi.h b/bsp/nuvoton/libraries/ma35/StdDriver/inc/nu_kpi.h new file mode 100644 index 0000000000..ff7fbdcbc1 --- /dev/null +++ b/bsp/nuvoton/libraries/ma35/StdDriver/inc/nu_kpi.h @@ -0,0 +1,169 @@ +/**************************************************************************//** + * @file nu_kpi.h + * @brief KPI driver header file + * + * SPDX-License-Identifier: Apache-2.0 + * @copyright (C) 2020 Nuvoton Technology Corp. All rights reserved. + *****************************************************************************/ +#ifndef __NU_KPI_H__ +#define __NU_KPI_H__ + +#ifdef __cplusplus +extern "C" +{ +#endif + + +/** @addtogroup Standard_Driver Standard Driver + @{ +*/ + +/** @addtogroup KPI_Driver KPI Driver + @{ +*/ + +/** @addtogroup KPI_EXPORTED_CONSTANTS KPI Exported Constants + @{ +*/ + +#define KPI_ROW_SCAN_DELAY4CLK (0x0 << KPI_KPICONF_SCANROWD_Pos) /*!< Delay cycle when row change */ +#define KPI_ROW_SCAN_DELAY8CLK (0x1 << KPI_KPICONF_SCANROWD_Pos) /*!< Delay cycle when row change */ +#define KPI_ROW_SCAN_DELAY16CLK (0x2 << KPI_KPICONF_SCANROWD_Pos) /*!< Delay cycle when row change */ +#define KPI_ROW_SCAN_DELAY32CLK (0x3 << KPI_KPICONF_SCANROWD_Pos) /*!< Delay cycle when row change */ + +#define KPI_KEY00 (KPI_KPIKEST0_KEST00_Msk) /*!< Press / Release Key Indicator */ +#define KPI_KEY01 (KPI_KPIKEST0_KEST01_Msk) /*!< Press / Release Key Indicator */ +#define KPI_KEY02 (KPI_KPIKEST0_KEST02_Msk) /*!< Press / Release Key Indicator */ +#define KPI_KEY03 (KPI_KPIKEST0_KEST03_Msk) /*!< Press / Release Key Indicator */ +#define KPI_KEY04 (KPI_KPIKEST0_KEST04_Msk) /*!< Press / Release Key Indicator */ +#define KPI_KEY05 (KPI_KPIKEST0_KEST05_Msk) /*!< Press / Release Key Indicator */ +#define KPI_KEY06 (KPI_KPIKEST0_KEST06_Msk) /*!< Press / Release Key Indicator */ +#define KPI_KEY07 (KPI_KPIKEST0_KEST07_Msk) /*!< Press / Release Key Indicator */ +#define KPI_KEY10 (KPI_KPIKEST0_KEST10_Msk) /*!< Press / Release Key Indicator */ +#define KPI_KEY11 (KPI_KPIKEST0_KEST11_Msk) /*!< Press / Release Key Indicator */ +#define KPI_KEY12 (KPI_KPIKEST0_KEST12_Msk) /*!< Press / Release Key Indicator */ +#define KPI_KEY13 (KPI_KPIKEST0_KEST13_Msk) /*!< Press / Release Key Indicator */ +#define KPI_KEY14 (KPI_KPIKEST0_KEST14_Msk) /*!< Press / Release Key Indicator */ +#define KPI_KEY15 (KPI_KPIKEST0_KEST15_Msk) /*!< Press / Release Key Indicator */ +#define KPI_KEY16 (KPI_KPIKEST0_KEST16_Msk) /*!< Press / Release Key Indicator */ +#define KPI_KEY17 (KPI_KPIKEST0_KEST17_Msk) /*!< Press / Release Key Indicator */ +#define KPI_KEY20 (KPI_KPIKEST0_KEST20_Msk) /*!< Press / Release Key Indicator */ +#define KPI_KEY21 (KPI_KPIKEST0_KEST21_Msk) /*!< Press / Release Key Indicator */ +#define KPI_KEY22 (KPI_KPIKEST0_KEST22_Msk) /*!< Press / Release Key Indicator */ +#define KPI_KEY23 (KPI_KPIKEST0_KEST23_Msk) /*!< Press / Release Key Indicator */ +#define KPI_KEY24 (KPI_KPIKEST0_KEST24_Msk) /*!< Press / Release Key Indicator */ +#define KPI_KEY25 (KPI_KPIKEST0_KEST25_Msk) /*!< Press / Release Key Indicator */ +#define KPI_KEY26 (KPI_KPIKEST0_KEST26_Msk) /*!< Press / Release Key Indicator */ +#define KPI_KEY27 (KPI_KPIKEST0_KEST27_Msk) /*!< Press / Release Key Indicator */ +#define KPI_KEY30 (KPI_KPIKEST0_KEST30_Msk) /*!< Press / Release Key Indicator */ +#define KPI_KEY31 (KPI_KPIKEST0_KEST31_Msk) /*!< Press / Release Key Indicator */ +#define KPI_KEY32 (KPI_KPIKEST0_KEST32_Msk) /*!< Press / Release Key Indicator */ +#define KPI_KEY33 (KPI_KPIKEST0_KEST33_Msk) /*!< Press / Release Key Indicator */ +#define KPI_KEY34 (KPI_KPIKEST0_KEST34_Msk) /*!< Press / Release Key Indicator */ +#define KPI_KEY35 (KPI_KPIKEST0_KEST35_Msk) /*!< Press / Release Key Indicator */ +#define KPI_KEY36 (KPI_KPIKEST0_KEST36_Msk) /*!< Press / Release Key Indicator */ +#define KPI_KEY37 (KPI_KPIKEST0_KEST37_Msk) /*!< Press / Release Key Indicator */ +#define KPI_KEY40 (KPI_KPIKEST0_KEST40_Msk) /*!< Press / Release Key Indicator */ +#define KPI_KEY41 (KPI_KPIKEST0_KEST41_Msk) /*!< Press / Release Key Indicator */ +#define KPI_KEY42 (KPI_KPIKEST0_KEST42_Msk) /*!< Press / Release Key Indicator */ +#define KPI_KEY43 (KPI_KPIKEST0_KEST43_Msk) /*!< Press / Release Key Indicator */ +#define KPI_KEY44 (KPI_KPIKEST0_KEST44_Msk) /*!< Press / Release Key Indicator */ +#define KPI_KEY45 (KPI_KPIKEST0_KEST45_Msk) /*!< Press / Release Key Indicator */ +#define KPI_KEY46 (KPI_KPIKEST0_KEST46_Msk) /*!< Press / Release Key Indicator */ +#define KPI_KEY47 (KPI_KPIKEST0_KEST47_Msk) /*!< Press / Release Key Indicator */ +#define KPI_KEY50 (KPI_KPIKEST0_KEST50_Msk) /*!< Press / Release Key Indicator */ +#define KPI_KEY51 (KPI_KPIKEST0_KEST51_Msk) /*!< Press / Release Key Indicator */ +#define KPI_KEY52 (KPI_KPIKEST0_KEST52_Msk) /*!< Press / Release Key Indicator */ +#define KPI_KEY53 (KPI_KPIKEST0_KEST53_Msk) /*!< Press / Release Key Indicator */ +#define KPI_KEY54 (KPI_KPIKEST0_KEST54_Msk) /*!< Press / Release Key Indicator */ +#define KPI_KEY55 (KPI_KPIKEST0_KEST55_Msk) /*!< Press / Release Key Indicator */ +#define KPI_KEY56 (KPI_KPIKEST0_KEST56_Msk) /*!< Press / Release Key Indicator */ +#define KPI_KEY57 (KPI_KPIKEST0_KEST57_Msk) /*!< Press / Release Key Indicator */ + +#define KPI_GET_KEY_STA_REG0(kpi) (kpi->KPIKEST0) /*!< Get Keypad State Register 0 */ +#define KPI_GET_KEY_STA_REG1(kpi) (kpi->KPIKEST1) /*!< Get Keypad State Register 1 */ +#define KPI_GET_PRESS_KEY_REG0(kpi) (kpi->KPIKPE0) /*!< Get Lower 32 Key Press Event Indicator */ +#define KPI_GET_PRESS_KEY_REG1(kpi) (kpi->KPIKPE1) /*!< Get Upper 32 Key Press Event Indicator */ +#define KPI_GET_RELEASE_KEY_REG0(kpi) (kpi->KPIKRE0) /*!< Get Lower 32 Key Release Event Indicator */ +#define KPI_GET_RELEASE_KEY_REG1(kpi) (kpi->KPIKRE1) /*!< Get Upper 32 Key Release Event Indicator */ + +#define KPI_EN_WAKEUP(kpi) (kpi->KPICONF |= KPI_KPICONF_WAKEUP_Msk) /*!< Enable Lower Power Wakeup */ +#define KPI_DIS_WAKEUP(kpi) (kpi->KPICONF &= ~KPI_KPICONF_WAKEUP_Msk) /*!< Disable Lower Power Wakeup */ + +/** + * @brief Enable KPI specified interrupt + * + * @param[in] u32InterruptFlag The specified interrupt of KPI module. + * - \ref KPI_KPICONF_PKINTEN_Msk : Press Key Interrupt Enable + * - \ref KPI_KPICONF_RKINTEN_Msk : Release Key Interrupt + * - \ref KPI_KPICONF_INTEN_Msk : Key Interrupt Enable + * + * @return None + * + * @details The function is used to enable KPI specified interrupt. + * \hideinitializer + */ +#define KPI_ENABLE_INT(kpi,u32InterruptFlag) (kpi->KPICONF |= u32InterruptFlag) + +/** + * @brief Disable KPI specified interrupt + * + * @param[in] u32InterruptFlag The specified interrupt of KPI module. + * - \ref KPI_KPICONF_PKINTEN_Msk : Press Key Interrupt Enable + * - \ref KPI_KPICONF_RKINTEN_Msk : Release Key Interrupt + * - \ref KPI_KPICONF_INTEN_Msk : Key Interrupt Enable + * + * @return None + * + * @details The function is used to enable KPI specified interrupt. + * \hideinitializer + */ +#define KPI_DISABLE_INT(kpi,u32InterruptFlag) (kpi->KPICONF &= ~u32IntSel) + +/** + * @brief Disable 3Key Reset + * + * @return None + * + * @details The function is used to disable 3key Reset. + * \hideinitializer + */ +#define KPI_DISABLE_3KEY_RESET(kpi) (kpi->KPI3KCONF &= ~KPI_KPI3KCONF_EN3KYRST_Msk) + +/** + * @brief Get interrupt flag + * + * @return \ref KPI_KPISTATUS_PDWAKE_Msk + * \ref KPI_KPISTATUS_RST3KEY_Msk + * \ref KPI_KPISTATUS_KEYINT_Msk + * \ref KPI_KPISTATUS_RKEYINT_Msk + * \ref KPI_KPISTATUS_PKEYINT_Msk + * + * @details The function is used to disable 3key Reset. + * \hideinitializer + */ +#define KPI_GET_INT_FLAG(kpi) (kpi->KPISTATUS) + +void KPI_Open(KPI_T *kpi, uint32_t u32Row, uint32_t u32Col); +void KPI_Close(KPI_T *kpi); +void KPI_ConfigKeyScanTiming(KPI_T *kpi, uint32_t u32PreScale, uint32_t u32Debounce, uint32_t u32ScanDelay); +void KPI_Set3KeyReset(KPI_T *kpi, uint32_t u32Key1, uint32_t u32Key2, uint32_t u32Key3, uint32_t u32RstCnt); + + +/*@}*/ /* end of group KPI_EXPORTED_FUNCTIONS */ + +/*@}*/ /* end of group KPI_Driver */ + +/*@}*/ /* end of group Standard_Driver */ + +#ifdef __cplusplus +} +#endif + +#endif /*__NU_KPI_H__*/ + + + + + + diff --git a/bsp/nuvoton/libraries/ma35/StdDriver/inc/nu_pdma.h b/bsp/nuvoton/libraries/ma35/StdDriver/inc/nu_pdma.h new file mode 100644 index 0000000000..d50726a8bf --- /dev/null +++ b/bsp/nuvoton/libraries/ma35/StdDriver/inc/nu_pdma.h @@ -0,0 +1,421 @@ +/**************************************************************************//** + * @file nu_pdma.h + * @brief PDMA driver header file + * + * SPDX-License-Identifier: Apache-2.0 + * @copyright (C) 2020 Nuvoton Technology Corp. All rights reserved. + *****************************************************************************/ +#ifndef __NU_PDMA_H__ +#define __NU_PDMA_H__ + +#ifdef __cplusplus +extern "C" +{ +#endif + + +/** @addtogroup Standard_Driver Standard Driver + @{ +*/ + +/** @addtogroup PDMA_Driver PDMA Driver + @{ +*/ + +/** @addtogroup PDMA_EXPORTED_CONSTANTS PDMA Exported Constants + @{ +*/ +/*---------------------------------------------------------------------------------------------------------*/ +/* Operation Mode Constant Definitions */ +/*---------------------------------------------------------------------------------------------------------*/ +#define PDMA_OP_STOP 0x00000000UL /*!INTSTS)) + +/** + * @brief Get Transfer Done Interrupt Status + * + * @param[in] pdma The pointer of the specified PDMA module + * + * @return None + * + * @details Get the transfer done Interrupt status. + * \hideinitializer + */ +#define PDMA_GET_TD_STS(pdma) ((uint32_t)(pdma->TDSTS)) + +/** + * @brief Clear Transfer Done Interrupt Status + * + * @param[in] pdma The pointer of the specified PDMA module + * + * @param[in] u32Mask The channel mask + * + * @return None + * + * @details Clear the transfer done Interrupt status. + * \hideinitializer + */ +#define PDMA_CLR_TD_FLAG(pdma,u32Mask) ((uint32_t)(pdma->TDSTS = (u32Mask))) + +/** + * @brief Get Target Abort Interrupt Status + * + * @param[in] pdma The pointer of the specified PDMA module + * + * @return None + * + * @details Get the target abort Interrupt status. + * \hideinitializer + */ +#define PDMA_GET_ABORT_STS(pdma) ((uint32_t)(pdma->ABTSTS)) + +/** + * @brief Clear Target Abort Interrupt Status + * + * @param[in] pdma The pointer of the specified PDMA module + * + * @param[in] u32Mask The channel mask + * + * @return None + * + * @details Clear the target abort Interrupt status. + * \hideinitializer + */ +#define PDMA_CLR_ABORT_FLAG(pdma,u32Mask) ((uint32_t)(pdma->ABTSTS = (u32Mask))) + +/** + * @brief Get Alignment Interrupt Status + * + * @param[in] pdma The pointer of the specified PDMA module + * + * @return None + * + * @details Get Alignment Interrupt status. + * \hideinitializer + */ +#define PDMA_GET_ALIGN_STS(pdma) ((uint32_t)(PDMA->ALIGN)) + +/** + * @brief Clear Alignment Interrupt Status + * + * @param[in] pdma The pointer of the specified PDMA module + * @param[in] u32Mask The channel mask + * + * @return None + * + * @details Clear the Alignment Interrupt status. + * \hideinitializer + */ +#define PDMA_CLR_ALIGN_FLAG(pdma,u32Mask) ((uint32_t)(pdma->ALIGN = (u32Mask))) + +/** + * @brief Clear Timeout Interrupt Status + * + * @param[in] pdma The pointer of the specified PDMA module + * @param[in] u32Ch The selected channel + * + * @return None + * + * @details Clear the selected channel timeout interrupt status. + * \hideinitializer + */ +#define PDMA_CLR_TMOUT_FLAG(pdma,u32Ch) ((uint32_t)(pdma->INTSTS = (1 << ((u32Ch) + 8)))) + +/** + * @brief Check Channel Status + * + * @param[in] pdma The pointer of the specified PDMA module + * @param[in] u32Ch The selected channel + * + * @retval 0 Idle state + * @retval 1 Busy state + * + * @details Check the selected channel is busy or not. + * \hideinitializer + */ +#define PDMA_IS_CH_BUSY(pdma,u32Ch) ((uint32_t)(pdma->TRGSTS & (1 << (u32Ch)))? 1 : 0) + +/** + * @brief Set Source Address + * + * @param[in] pdma The pointer of the specified PDMA module + * @param[in] u32Ch The selected channel + * @param[in] u32Addr The selected address + * + * @return None + * + * @details This macro set the selected channel source address. + * \hideinitializer + */ +#define PDMA_SET_SRC_ADDR(pdma,u32Ch, u32Addr) ((uint32_t)(pdma->DSCT[(u32Ch)].SA = (u32Addr))) + +/** + * @brief Set Destination Address + * + * @param[in] pdma The pointer of the specified PDMA module + * @param[in] u32Ch The selected channel + * @param[in] u32Addr The selected address + * + * @return None + * + * @details This macro set the selected channel destination address. + * \hideinitializer + */ +#define PDMA_SET_DST_ADDR(pdma,u32Ch, u32Addr) ((uint32_t)(pdma->DSCT[(u32Ch)].DA = (u32Addr))) + +/** + * @brief Set Transfer Count + * + * @param[in] pdma The pointer of the specified PDMA module + * @param[in] u32Ch The selected channel + * @param[in] u32TransCount Transfer Count + * + * @return None + * + * @details This macro set the selected channel transfer count. + * \hideinitializer + */ +#define PDMA_SET_TRANS_CNT(pdma,u32Ch, u32TransCount) ((uint32_t)(pdma->DSCT[(u32Ch)].CTL=(pdma->DSCT[(u32Ch)].CTL&~PDMA_DSCT_CTL_TXCNT_Msk)|(((u32TransCount)-1) << PDMA_DSCT_CTL_TXCNT_Pos))) + +/** + * @brief Set Scatter-gather descriptor Address + * + * @param[in] pdma The pointer of the specified PDMA module + * @param[in] u32Ch The selected channel + * @param[in] u32Addr The descriptor address + * + * @return None + * + * @details This macro set the selected channel scatter-gather descriptor address. + * \hideinitializer + */ +#define PDMA_SET_SCATTER_DESC(pdma,u32Ch, u32Addr) ((uint32_t)(pdma->DSCT[(u32Ch)].NEXT = (u32Addr) - (pdma->SCATBA))) + +/** + * @brief Stop the channel + * + * @param[in] pdma The pointer of the specified PDMA module + * + * @param[in] u32Ch The selected channel + * + * @return None + * + * @details This macro stop the selected channel. + * \hideinitializer + */ +#define PDMA_STOP(pdma,u32Ch) ((uint32_t)(pdma->PAUSE = (1 << (u32Ch)))) + +/** + * @brief Pause the channel + * + * @param[in] pdma The pointer of the specified PDMA module + * + * @param[in] u32Ch The selected channel + * + * @return None + * + * @details This macro pause the selected channel. + * \hideinitializer + */ +#define PDMA_PAUSE(pdma,u32Ch) ((uint32_t)(pdma->PAUSE = (1 << (u32Ch)))) + +/*---------------------------------------------------------------------------------------------------------*/ +/* Define PDMA functions prototype */ +/*---------------------------------------------------------------------------------------------------------*/ +void PDMA_Open(PDMA_T *pdma, uint32_t u32Mask); +void PDMA_Close(PDMA_T *pdma); +void PDMA_SetTransferCnt(PDMA_T *pdma, uint32_t u32Ch, uint32_t u32Width, uint32_t u32TransCount); +void PDMA_SetTransferAddr(PDMA_T *pdma, uint32_t u32Ch, uint32_t u32SrcAddr, uint32_t u32SrcCtrl, uint32_t u32DstAddr, uint32_t u32DstCtrl); +void PDMA_SetTransferMode(PDMA_T *pdma, uint32_t u32Ch, uint32_t u32Peripheral, uint32_t u32ScatterEn, uint32_t u32DescAddr); +void PDMA_SetBurstType(PDMA_T *pdma, uint32_t u32Ch, uint32_t u32BurstType, uint32_t u32BurstSize); +void PDMA_EnableTimeout(PDMA_T *pdma, uint32_t u32Mask); +void PDMA_DisableTimeout(PDMA_T *pdma, uint32_t u32Mask); +void PDMA_SetTimeOut(PDMA_T *pdma, uint32_t u32Ch, uint32_t u32OnOff, uint32_t u32TimeOutCnt); +void PDMA_Trigger(PDMA_T *pdma, uint32_t u32Ch); +void PDMA_EnableInt(PDMA_T *pdma, uint32_t u32Ch, uint32_t u32Mask); +void PDMA_DisableInt(PDMA_T *pdma, uint32_t u32Ch, uint32_t u32Mask); +void PDMA_SetStride(PDMA_T *pdma, uint32_t u32Ch, uint32_t u32DestLen, uint32_t u32SrcLen, uint32_t u32TransCount); +void PDMA_SetRepeat(PDMA_T *pdma, uint32_t u32Ch, uint32_t u32DestInterval, uint32_t u32SrcInterval, uint32_t u32RepeatCount); + + +/*@}*/ /* end of group PDMA_EXPORTED_FUNCTIONS */ + +/*@}*/ /* end of group PDMA_Driver */ + +/*@}*/ /* end of group Standard_Driver */ + +#ifdef __cplusplus +} +#endif + +#endif /* __PDMA_H__ */ + diff --git a/bsp/nuvoton/libraries/ma35/StdDriver/inc/nu_qei.h b/bsp/nuvoton/libraries/ma35/StdDriver/inc/nu_qei.h new file mode 100644 index 0000000000..4707e192a4 --- /dev/null +++ b/bsp/nuvoton/libraries/ma35/StdDriver/inc/nu_qei.h @@ -0,0 +1,388 @@ +/**************************************************************************//** + * @file nu_qei.h + * @brief Quadrature Encoder Interface (QEI) driver header file + * + * SPDX-License-Identifier: Apache-2.0 + * @copyright (C) 2020 Nuvoton Technology Corp. All rights reserved. + *****************************************************************************/ +#ifndef __NU_QEI_H__ +#define __NU_QEI_H__ + +#ifdef __cplusplus +extern "C" +{ +#endif + + +/** @addtogroup Standard_Driver Standard Driver + @{ +*/ + +/** @addtogroup QEI_Driver QEI Driver + @{ +*/ + +/** @addtogroup QEI_EXPORTED_CONSTANTS QEI Exported Constants + @{ +*/ + +/*---------------------------------------------------------------------------------------------------------*/ +/* QEI counting mode selection constants definitions */ +/*---------------------------------------------------------------------------------------------------------*/ +#define QEI_CTL_X4_FREE_COUNTING_MODE (0x0<CTL &= (~QEI_CTL_CMPEN_Msk)) + +/** + * @brief Enable QEI compare function + * @param[in] qei The pointer of the specified QEI module. + * @return None + * @details This macro enable QEI counter compare function. + * \hideinitializer + */ +#define QEI_ENABLE_CNT_CMP(qei) ((qei)->CTL |= QEI_CTL_CMPEN_Msk) + +/** + * @brief Disable QEI index latch function + * @param[in] qei The pointer of the specified QEI module. + * @return None + * @details This macro disable QEI index trigger counter latch function. + * \hideinitializer + */ +#define QEI_DISABLE_INDEX_LATCH(qei) ((qei)->CTL &= (~QEI_CTL_IDXLATEN_Msk)) + +/** + * @brief Enable QEI index latch function + * @param[in] qei The pointer of the specified QEI module. + * @return None + * @details This macro enable QEI index trigger counter latch function. + * \hideinitializer + */ +#define QEI_ENABLE_INDEX_LATCH(qei) ((qei)->CTL |= QEI_CTL_IDXLATEN_Msk) + +/** + * @brief Disable QEI index reload function + * @param[in] qei The pointer of the specified QEI module. + * @return None + * @details This macro disable QEI index trigger counter reload function. + * \hideinitializer + */ +#define QEI_DISABLE_INDEX_RELOAD(qei) ((qei)->CTL &= (~QEI_CTL_IDXRLDEN_Msk)) + +/** + * @brief Enable QEI index reload function + * @param[in] qei The pointer of the specified QEI module. + * @return None + * @details This macro enable QEI index trigger counter reload function. + * \hideinitializer + */ +#define QEI_ENABLE_INDEX_RELOAD(qei) ((qei)->CTL |= QEI_CTL_IDXRLDEN_Msk) + +/** + * @brief Disable QEI input + * @param[in] qei The pointer of the specified QEI module. + * @param[in] u32InputType Input signal type. + * - \ref QEI_CTL_CHAEN_Msk : QEA input + * - \ref QEI_CTL_CHAEN_Msk : QEB input + * - \ref QEI_CTL_IDXEN_Msk : IDX input + * @return None + * @details This macro disable specified QEI signal input. + * \hideinitializer + */ +#define QEI_DISABLE_INPUT(qei, u32InputType) ((qei)->CTL &= ~(u32InputType)) + +/** + * @brief Enable QEI input + * @param[in] qei The pointer of the specified QEI module. + * @param[in] u32InputType Input signal type . + * - \ref QEI_CTL_CHAEN_Msk : QEA input + * - \ref QEI_CTL_CHBEN_Msk : QEB input + * - \ref QEI_CTL_IDXEN_Msk : IDX input + * @return None + * @details This macro enable specified QEI signal input. + * \hideinitializer + */ +#define QEI_ENABLE_INPUT(qei, u32InputType) ((qei)->CTL |= (u32InputType)) + +/** + * @brief Disable inverted input polarity + * @param[in] qei The pointer of the specified QEI module. + * @param[in] u32InputType Input signal type . + * - \ref QEI_CTL_CHAINV_Msk : QEA Input + * - \ref QEI_CTL_CHBINV_Msk : QEB Input + * - \ref QEI_CTL_IDXINV_Msk : IDX Input + * @return None + * @details This macro disable specified QEI signal inverted input polarity. + * \hideinitializer + */ +#define QEI_DISABLE_INPUT_INV(qei, u32InputType) ((qei)->CTL &= ~(u32InputType)) + +/** + * @brief Enable inverted input polarity + * @param[in] qei The pointer of the specified QEI module. + * @param[in] u32InputType Input signal type. + * - \ref QEI_CTL_CHAINV_Msk : QEA Input + * - \ref QEI_CTL_CHBINV_Msk : QEB Input + * - \ref QEI_CTL_IDXINV_Msk : IDX Input + * @return None + * @details This macro inverse specified QEI signal input polarity. + * \hideinitializer + */ +#define QEI_ENABLE_INPUT_INV(qei, u32InputType) ((qei)->CTL |= (u32InputType)) + +/** + * @brief Disable QEI interrupt + * @param[in] qei The pointer of the specified QEI module. + * @param[in] u32IntSel Interrupt type selection. + * - \ref QEI_CTL_DIRIEN_Msk : Direction change interrupt + * - \ref QEI_CTL_OVUNIEN_Msk : Counter overflow or underflow interrupt + * - \ref QEI_CTL_CMPIEN_Msk : Compare-match interrupt + * - \ref QEI_CTL_IDXIEN_Msk : Index detected interrupt + * @return None + * @details This macro disable specified QEI interrupt. + * \hideinitializer + */ +#define QEI_DISABLE_INT(qei, u32IntSel) ((qei)->CTL &= ~(u32IntSel)) + +/** + * @brief Enable QEI interrupt + * @param[in] qei The pointer of the specified QEI module. + * @param[in] u32IntSel Interrupt type selection. + * - \ref QEI_CTL_DIRIEN_Msk : Direction change interrupt + * - \ref QEI_CTL_OVUNIEN_Msk : Counter overflow or underflow interrupt + * - \ref QEI_CTL_CMPIEN_Msk : Compare-match interrupt + * - \ref QEI_CTL_IDXIEN_Msk : Index detected interrupt + * @return None + * @details This macro enable specified QEI interrupt. + * \hideinitializer + */ +#define QEI_ENABLE_INT(qei, u32IntSel) ((qei)->CTL |= (u32IntSel)) + +/** + * @brief Disable QEI noise filter + * @param[in] qei The pointer of the specified QEI module. + * @return None + * @details This macro disable QEI noise filter function. + * \hideinitializer + */ +#define QEI_DISABLE_NOISE_FILTER(qei) ((qei)->CTL |= QEI_CTL_NFDIS_Msk) + +/** + * @brief Enable QEI noise filter + * @param[in] qei The pointer of the specified QEI module. + * @param[in] u32ClkSel The sampling frequency of the noise filter clock. + * - \ref QEI_CTL_NFCLKSEL_DIV1 + * - \ref QEI_CTL_NFCLKSEL_DIV2 + * - \ref QEI_CTL_NFCLKSEL_DIV4 + * - \ref QEI_CTL_NFCLKSEL_DIV16 + * - \ref QEI_CTL_NFCLKSEL_DIV32 + * - \ref QEI_CTL_NFCLKSEL_DIV64 + * @return None + * @details This macro enable QEI noise filter function and select noise filter clock. + * \hideinitializer + */ +#define QEI_ENABLE_NOISE_FILTER(qei, u32ClkSel) ((qei)->CTL = ((qei)->CTL & (~(QEI_CTL_NFDIS_Msk|QEI_CTL_NFCLKSEL_Msk))) | (u32ClkSel)) + +/** + * @brief Get QEI counter value + * @param[in] qei The pointer of the specified QEI module. + * @return QEI pulse counter register value. + * @details This macro get QEI pulse counter value. + * \hideinitializer + */ +#define QEI_GET_CNT_VALUE(qei) ((qei)->CNT) + +/** + * @brief Get QEI counting direction + * @param[in] qei The pointer of the specified QEI module. + * @retval 0 QEI counter is in down-counting. + * @retval 1 QEI counter is in up-counting. + * @details This macro get QEI counting direction. + * \hideinitializer + */ +#define QEI_GET_DIR(qei) (((qei)->STATUS & (QEI_STATUS_DIRF_Msk))?1:0) + +/** + * @brief Get QEI counter hold value + * @param[in] qei The pointer of the specified QEI module. + * @return QEI pulse counter hold register value. + * @details This macro get QEI pulse counter hold value, which is updated with counter value in hold counter value control. + * \hideinitializer + */ +#define QEI_GET_HOLD_VALUE(qei) ((qei)->CNTHOLD) + +/** + * @brief Get QEI counter index latch value + * @param[in] qei The pointer of the specified QEI module. + * @return QEI pulse counter index latch value + * @details This macro get QEI pulse counter index latch value, which is updated with counter value when the index is detected. + * \hideinitializer + */ +#define QEI_GET_INDEX_LATCH_VALUE(qei) ((qei)->CNTLATCH) + +/** + * @brief Set QEI counter index latch value + * @param[in] qei The pointer of the specified QEI module. + * @param[in] u32Val The latch value. + * @return QEI pulse counter index latch value + * @details This macro set QEI pulse counter index latch value, which is updated with counter value when the index is detected. + * \hideinitializer + */ +#define QEI_SET_INDEX_LATCH_VALUE(qei,u32Val) ((qei)->CNTLATCH = (u32Val)) + +/** + * @brief Get QEI interrupt flag status + * @param[in] qei The pointer of the specified QEI module. + * @param[in] u32IntSel Interrupt type selection. +* - \ref QEI_STATUS_DIRF_Msk : Counting direction flag + * - \ref QEI_STATUS_DIRCHGF_Msk : Direction change flag + * - \ref QEI_STATUS_OVUNF_Msk : Counter overflow or underflow flag + * - \ref QEI_STATUS_CMPF_Msk : Compare-match flag + * - \ref QEI_STATUS_IDXF_Msk : Index detected flag + * @retval 0 QEI specified interrupt flag is not set. + * @retval 1 QEI specified interrupt flag is set. + * @details This macro get QEI specified interrupt flag status. + * \hideinitializer + */ +#define QEI_GET_INT_FLAG(qei, u32IntSel) (((qei)->STATUS & (u32IntSel))?1:0) + + +/** + * @brief Clear QEI interrupt flag + * @param[in] qei The pointer of the specified QEI module. + * @param[in] u32IntSel Interrupt type selection. + * - \ref QEI_STATUS_DIRCHGF_Msk : Direction change flag + * - \ref QEI_STATUS_OVUNF_Msk : Counter overflow or underflow flag + * - \ref QEI_STATUS_CMPF_Msk : Compare-match flag + * - \ref QEI_STATUS_IDXF_Msk : Index detected flag + * @return None + * @details This macro clear QEI specified interrupt flag. + * \hideinitializer + */ +#define QEI_CLR_INT_FLAG(qei, u32IntSel) ((qei)->STATUS = (u32IntSel)) + +/** + * @brief Set QEI counter compare value + * @param[in] qei The pointer of the specified QEI module. + * @param[in] u32Value The counter compare value. + * @return None + * @details This macro set QEI pulse counter compare value. + * \hideinitializer + */ +#define QEI_SET_CNT_CMP(qei, u32Value) ((qei)->CNTCMP = (u32Value)) + +/** + * @brief Set QEI counter value + * @param[in] qei The pointer of the specified QEI module. + * @param[in] u32Value The counter compare value. + * @return None + * @details This macro set QEI pulse counter value. + * \hideinitializer + */ +#define QEI_SET_CNT_VALUE(qei, u32Value) ((qei)->CNT = (u32Value)) + +/** + * @brief Enable QEI counter hold mode + * @param[in] qei The pointer of the specified QEI module. + * @param[in] u32Type The triggered type. + * - \ref QEI_CTL_HOLDCNT_Msk : Hold QEI_CNT control + * - \ref QEI_CTL_HOLDTMR0_Msk : Hold QEI_CNT by Timer0 + * - \ref QEI_CTL_HOLDTMR1_Msk : Hold QEI_CNT by Timer1 + * - \ref QEI_CTL_HOLDTMR2_Msk : Hold QEI_CNT by Timer2 + * - \ref QEI_CTL_HOLDTMR3_Msk : Hold QEI_CNT by Timer3 + * @return None + * @details This macro enable QEI counter hold mode. + * \hideinitializer + */ +#define QEI_ENABLE_HOLD_TRG_SRC(qei, u32Type) ((qei)->CTL |= (u32Type)) + +/** + * @brief Disable QEI counter hold mode + * @param[in] qei The pointer of the specified QEI module. + * @param[in] u32Type The triggered type. + * - \ref QEI_CTL_HOLDCNT_Msk : Hold QEI_CNT control + * - \ref QEI_CTL_HOLDTMR0_Msk : Hold QEI_CNT by Timer0 + * - \ref QEI_CTL_HOLDTMR1_Msk : Hold QEI_CNT by Timer1 + * - \ref QEI_CTL_HOLDTMR2_Msk : Hold QEI_CNT by Timer2 + * - \ref QEI_CTL_HOLDTMR3_Msk : Hold QEI_CNT by Timer3 + * @return None + * @details This macro disable QEI counter hold mode. + * \hideinitializer + */ +#define QEI_DISABLE_HOLD_TRG_SRC(qei, u32Type) ((qei)->CTL &= ~(u32Type)) + +/** + * @brief Set QEI maximum count value + * @param[in] qei The pointer of the specified QEI module. + * @param[in] u32Value The counter maximum value. + * @return QEI maximum count value + * @details This macro set QEI maximum count value. + * \hideinitializer + */ +#define QEI_SET_CNT_MAX(qei, u32Value) ((qei)->CNTMAX = (u32Value)) + +/** + * @brief Set QEI counting mode + * @param[in] qei The pointer of the specified QEI module. + * @param[in] u32Mode QEI counting mode. + * - \ref QEI_CTL_X4_FREE_COUNTING_MODE + * - \ref QEI_CTL_X2_FREE_COUNTING_MODE + * - \ref QEI_CTL_X4_COMPARE_COUNTING_MODE + * - \ref QEI_CTL_X2_COMPARE_COUNTING_MODE + * @return None + * @details This macro set QEI counting mode. + * \hideinitializer + */ +#define QEI_SET_CNT_MODE(qei, u32Mode) ((qei)->CTL = ((qei)->CTL & (~QEI_CTL_MODE_Msk)) | (u32Mode)) + + +void QEI_Close(QEI_T *qei); +void QEI_DisableInt(QEI_T *qei, uint32_t u32IntSel); +void QEI_EnableInt(QEI_T *qei, uint32_t u32IntSel); +void QEI_Open(QEI_T *qei, uint32_t u32Mode, uint32_t u32Value); +void QEI_Start(QEI_T *qei); +void QEI_Stop(QEI_T *qei); + + +/*@}*/ /* end of group QEI_EXPORTED_FUNCTIONS */ + +/*@}*/ /* end of group QEI_Driver */ + +/*@}*/ /* end of group Standard_Driver */ + +#ifdef __cplusplus +} +#endif + +#endif /* __NU_QEI_H__ */ + diff --git a/bsp/nuvoton/libraries/ma35/StdDriver/inc/nu_qspi.h b/bsp/nuvoton/libraries/ma35/StdDriver/inc/nu_qspi.h new file mode 100644 index 0000000000..28f5fe67c9 --- /dev/null +++ b/bsp/nuvoton/libraries/ma35/StdDriver/inc/nu_qspi.h @@ -0,0 +1,379 @@ +/**************************************************************************//** + * @file nu_qspi.h + * @brief QSPI driver header file + * + * SPDX-License-Identifier: Apache-2.0 + * @copyright (C) 2020 Nuvoton Technology Corp. All rights reserved. + *****************************************************************************/ +#ifndef __NU_QSPI_H__ +#define __NU_QSPI_H__ + +#ifdef __cplusplus +extern "C" +{ +#endif + + +/** @addtogroup Standard_Driver Standard Driver + @{ +*/ + +/** @addtogroup QSPI_Driver QSPI Driver + @{ +*/ + +/** @addtogroup QSPI_EXPORTED_CONSTANTS QSPI Exported Constants + @{ +*/ + +#define QSPI_MODE_0 (QSPI_CTL_TXNEG_Msk) /*!< CLKPOL=0; RXNEG=0; TXNEG=1 \hideinitializer */ +#define QSPI_MODE_1 (QSPI_CTL_RXNEG_Msk) /*!< CLKPOL=0; RXNEG=1; TXNEG=0 \hideinitializer */ +#define QSPI_MODE_2 (QSPI_CTL_CLKPOL_Msk | QSPI_CTL_RXNEG_Msk) /*!< CLKPOL=1; RXNEG=1; TXNEG=0 \hideinitializer */ +#define QSPI_MODE_3 (QSPI_CTL_CLKPOL_Msk | QSPI_CTL_TXNEG_Msk) /*!< CLKPOL=1; RXNEG=0; TXNEG=1 \hideinitializer */ + +#define QSPI_SLAVE (QSPI_CTL_SLAVE_Msk) /*!< Set as slave \hideinitializer */ +#define QSPI_MASTER (0x0U) /*!< Set as master \hideinitializer */ + +#define QSPI_SS (QSPI_SSCTL_SS_Msk) /*!< Set SS \hideinitializer */ +#define QSPI_SS_ACTIVE_HIGH (QSPI_SSCTL_SSACTPOL_Msk) /*!< SS active high \hideinitializer */ +#define QSPI_SS_ACTIVE_LOW (0x0U) /*!< SS active low \hideinitializer */ + +/* QSPI Interrupt Mask */ +#define QSPI_UNIT_INT_MASK (0x001U) /*!< Unit transfer interrupt mask \hideinitializer */ +#define QSPI_SSACT_INT_MASK (0x002U) /*!< Slave selection signal active interrupt mask \hideinitializer */ +#define QSPI_SSINACT_INT_MASK (0x004U) /*!< Slave selection signal inactive interrupt mask \hideinitializer */ +#define QSPI_SLVUR_INT_MASK (0x008U) /*!< Slave under run interrupt mask \hideinitializer */ +#define QSPI_SLVBE_INT_MASK (0x010U) /*!< Slave bit count error interrupt mask \hideinitializer */ +#define QSPI_TXUF_INT_MASK (0x040U) /*!< Slave TX underflow interrupt mask \hideinitializer */ +#define QSPI_FIFO_TXTH_INT_MASK (0x080U) /*!< FIFO TX threshold interrupt mask \hideinitializer */ +#define QSPI_FIFO_RXTH_INT_MASK (0x100U) /*!< FIFO RX threshold interrupt mask \hideinitializer */ +#define QSPI_FIFO_RXOV_INT_MASK (0x200U) /*!< FIFO RX overrun interrupt mask \hideinitializer */ +#define QSPI_FIFO_RXTO_INT_MASK (0x400U) /*!< FIFO RX time-out interrupt mask \hideinitializer */ + +/* QSPI Status Mask */ +#define QSPI_BUSY_MASK (0x01U) /*!< Busy status mask \hideinitializer */ +#define QSPI_RX_EMPTY_MASK (0x02U) /*!< RX empty status mask \hideinitializer */ +#define QSPI_RX_FULL_MASK (0x04U) /*!< RX full status mask \hideinitializer */ +#define QSPI_TX_EMPTY_MASK (0x08U) /*!< TX empty status mask \hideinitializer */ +#define QSPI_TX_FULL_MASK (0x10U) /*!< TX full status mask \hideinitializer */ +#define QSPI_TXRX_RESET_MASK (0x20U) /*!< TX or RX reset status mask \hideinitializer */ +#define QSPI_QSPIEN_STS_MASK (0x40U) /*!< QSPIEN status mask \hideinitializer */ +#define QSPI_SSLINE_STS_MASK (0x80U) /*!< QSPIx_SS line status mask \hideinitializer */ + +/*@}*/ /* end of group QSPI_EXPORTED_CONSTANTS */ + + +/** @addtogroup QSPI_EXPORTED_FUNCTIONS QSPI Exported Functions + @{ +*/ + +/** + * @brief Clear the unit transfer interrupt flag. + * @param[in] qspi The pointer of the specified QSPI module. + * @return None. + * @details Write 1 to UNITIF bit of QSPI_STATUS register to clear the unit transfer interrupt flag. + * \hideinitializer + */ +#define QSPI_CLR_UNIT_TRANS_INT_FLAG(qspi) ((qspi)->STATUS = QSPI_STATUS_UNITIF_Msk) + +/** + * @brief Trigger RX PDMA function. + * @param[in] qspi The pointer of the specified QSPI module. + * @return None. + * @details Set RXPDMAEN bit of QSPI_PDMACTL register to enable RX PDMA transfer function. + * \hideinitializer + */ +#define QSPI_TRIGGER_RX_PDMA(qspi) ((qspi)->PDMACTL |= QSPI_PDMACTL_RXPDMAEN_Msk) + +/** + * @brief Trigger TX PDMA function. + * @param[in] qspi The pointer of the specified QSPI module. + * @return None. + * @details Set TXPDMAEN bit of QSPI_PDMACTL register to enable TX PDMA transfer function. + * \hideinitializer + */ +#define QSPI_TRIGGER_TX_PDMA(qspi) ((qspi)->PDMACTL |= QSPI_PDMACTL_TXPDMAEN_Msk) + +/** + * @brief Trigger TX and RX PDMA function. + * @param[in] qspi The pointer of the specified QSPI module. + * @return None. + * @details Set TXPDMAEN bit and RXPDMAEN bit of QSPI_PDMACTL register to enable TX and RX PDMA transfer function. + * \hideinitializer + */ +#define QSPI_TRIGGER_TX_RX_PDMA(qspi) ((qspi)->PDMACTL |= (QSPI_PDMACTL_TXPDMAEN_Msk | QSPI_PDMACTL_RXPDMAEN_Msk)) + +/** + * @brief Disable RX PDMA transfer. + * @param[in] qspi The pointer of the specified QSPI module. + * @return None. + * @details Clear RXPDMAEN bit of QSPI_PDMACTL register to disable RX PDMA transfer function. + * \hideinitializer + */ +#define QSPI_DISABLE_RX_PDMA(qspi) ( (qspi)->PDMACTL &= ~QSPI_PDMACTL_RXPDMAEN_Msk ) + +/** + * @brief Disable TX PDMA transfer. + * @param[in] qspi The pointer of the specified QSPI module. + * @return None. + * @details Clear TXPDMAEN bit of QSPI_PDMACTL register to disable TX PDMA transfer function. + * \hideinitializer + */ +#define QSPI_DISABLE_TX_PDMA(qspi) ( (qspi)->PDMACTL &= ~QSPI_PDMACTL_TXPDMAEN_Msk ) + +/** + * @brief Disable TX and RX PDMA transfer. + * @param[in] qspi The pointer of the specified QSPI module. + * @return None. + * @details Clear TXPDMAEN bit and RXPDMAEN bit of QSPI_PDMACTL register to disable TX and RX PDMA transfer function. + * \hideinitializer + */ +#define QSPI_DISABLE_TX_RX_PDMA(qspi) ( (qspi)->PDMACTL &= ~(QSPI_PDMACTL_TXPDMAEN_Msk | QSPI_PDMACTL_RXPDMAEN_Msk) ) + +/** + * @brief Get the count of available data in RX FIFO. + * @param[in] qspi The pointer of the specified QSPI module. + * @return The count of available data in RX FIFO. + * @details Read RXCNT (QSPI_STATUS[27:24]) to get the count of available data in RX FIFO. + * \hideinitializer + */ +#define QSPI_GET_RX_FIFO_COUNT(qspi) (((qspi)->STATUS & QSPI_STATUS_RXCNT_Msk) >> QSPI_STATUS_RXCNT_Pos) + +/** + * @brief Get the RX FIFO empty flag. + * @param[in] qspi The pointer of the specified QSPI module. + * @retval 0 RX FIFO is not empty. + * @retval 1 RX FIFO is empty. + * @details Read RXEMPTY bit of QSPI_STATUS register to get the RX FIFO empty flag. + * \hideinitializer + */ +#define QSPI_GET_RX_FIFO_EMPTY_FLAG(qspi) (((qspi)->STATUS & QSPI_STATUS_RXEMPTY_Msk)>>QSPI_STATUS_RXEMPTY_Pos) + +/** + * @brief Get the TX FIFO empty flag. + * @param[in] qspi The pointer of the specified QSPI module. + * @retval 0 TX FIFO is not empty. + * @retval 1 TX FIFO is empty. + * @details Read TXEMPTY bit of QSPI_STATUS register to get the TX FIFO empty flag. + * \hideinitializer + */ +#define QSPI_GET_TX_FIFO_EMPTY_FLAG(qspi) (((qspi)->STATUS & QSPI_STATUS_TXEMPTY_Msk)>>QSPI_STATUS_TXEMPTY_Pos) + +/** + * @brief Get the TX FIFO full flag. + * @param[in] qspi The pointer of the specified QSPI module. + * @retval 0 TX FIFO is not full. + * @retval 1 TX FIFO is full. + * @details Read TXFULL bit of QSPI_STATUS register to get the TX FIFO full flag. + * \hideinitializer + */ +#define QSPI_GET_TX_FIFO_FULL_FLAG(qspi) (((qspi)->STATUS & QSPI_STATUS_TXFULL_Msk)>>QSPI_STATUS_TXFULL_Pos) + +/** + * @brief Get the datum read from RX register. + * @param[in] qspi The pointer of the specified QSPI module. + * @return Data in RX register. + * @details Read QSPI_RX register to get the received datum. + * \hideinitializer + */ +#define QSPI_READ_RX(qspi) ((qspi)->RX) + +/** + * @brief Write datum to TX register. + * @param[in] qspi The pointer of the specified QSPI module. + * @param[in] u32TxData The datum which user attempt to transfer through QSPI bus. + * @return None. + * @details Write u32TxData to QSPI_TX register. + * \hideinitializer + */ +#define QSPI_WRITE_TX(qspi, u32TxData) ((qspi)->TX = (u32TxData)) + +/** + * @brief Set QSPIx_SS pin to high state. + * @param[in] qspi The pointer of the specified QSPI module. + * @return None. + * @details Disable automatic slave selection function and set QSPIx_SS pin to high state. + * \hideinitializer + */ +#define QSPI_SET_SS_HIGH(qspi) ((qspi)->SSCTL = ((qspi)->SSCTL & (~QSPI_SSCTL_AUTOSS_Msk)) | (QSPI_SSCTL_SSACTPOL_Msk | QSPI_SSCTL_SS_Msk)) + +/** + * @brief Set QSPIx_SS pin to low state. + * @param[in] qspi The pointer of the specified QSPI module. + * @return None. + * @details Disable automatic slave selection function and set QSPIx_SS pin to low state. + * \hideinitializer + */ +#define QSPI_SET_SS_LOW(qspi) ((qspi)->SSCTL = ((qspi)->SSCTL & (~(QSPI_SSCTL_AUTOSS_Msk | QSPI_SSCTL_SSACTPOL_Msk))) | QSPI_SSCTL_SS_Msk) + +/** + * @brief Enable Byte Reorder function. + * @param[in] qspi The pointer of the specified QSPI module. + * @return None. + * @details Enable Byte Reorder function. The suspend interval depends on the setting of SUSPITV (QSPI_CTL[7:4]). + * \hideinitializer + */ +#define QSPI_ENABLE_BYTE_REORDER(qspi) ((qspi)->CTL |= QSPI_CTL_REORDER_Msk) + +/** + * @brief Disable Byte Reorder function. + * @param[in] qspi The pointer of the specified QSPI module. + * @return None. + * @details Clear REORDER bit field of QSPI_CTL register to disable Byte Reorder function. + * \hideinitializer + */ +#define QSPI_DISABLE_BYTE_REORDER(qspi) ((qspi)->CTL &= ~QSPI_CTL_REORDER_Msk) + +/** + * @brief Set the length of suspend interval. + * @param[in] qspi The pointer of the specified QSPI module. + * @param[in] u32SuspCycle Decides the length of suspend interval. It could be 0 ~ 15. + * @return None. + * @details Set the length of suspend interval according to u32SuspCycle. + * The length of suspend interval is ((u32SuspCycle + 0.5) * the length of one QSPI bus clock cycle). + * \hideinitializer + */ +#define QSPI_SET_SUSPEND_CYCLE(qspi, u32SuspCycle) ((qspi)->CTL = ((qspi)->CTL & ~QSPI_CTL_SUSPITV_Msk) | ((u32SuspCycle) << QSPI_CTL_SUSPITV_Pos)) + +/** + * @brief Set the QSPI transfer sequence with LSB first. + * @param[in] qspi The pointer of the specified QSPI module. + * @return None. + * @details Set LSB bit of QSPI_CTL register to set the QSPI transfer sequence with LSB first. + * \hideinitializer + */ +#define QSPI_SET_LSB_FIRST(qspi) ((qspi)->CTL |= QSPI_CTL_LSB_Msk) + +/** + * @brief Set the QSPI transfer sequence with MSB first. + * @param[in] qspi The pointer of the specified SPI module. + * @return None. + * @details Clear LSB bit of QSPI_CTL register to set the QSPI transfer sequence with MSB first. + * \hideinitializer + */ +#define QSPI_SET_MSB_FIRST(qspi) ((qspi)->CTL &= ~QSPI_CTL_LSB_Msk) + +/** + * @brief Set the data width of a QSPI transaction. + * @param[in] qspi The pointer of the specified QSPI module. + * @param[in] u32Width The bit width of one transaction. + * @return None. + * @details The data width can be 8 ~ 32 bits. + * \hideinitializer + */ +#define QSPI_SET_DATA_WIDTH(qspi, u32Width) ((qspi)->CTL = ((qspi)->CTL & ~QSPI_CTL_DWIDTH_Msk) | (((u32Width)&0x1F) << QSPI_CTL_DWIDTH_Pos)) + +/** + * @brief Get the QSPI busy state. + * @param[in] qspi The pointer of the specified QSPI module. + * @retval 0 QSPI controller is not busy. + * @retval 1 QSPI controller is busy. + * @details This macro will return the busy state of QSPI controller. + * \hideinitializer + */ +#define QSPI_IS_BUSY(qspi) ( ((qspi)->STATUS & QSPI_STATUS_BUSY_Msk)>>QSPI_STATUS_BUSY_Pos ) + +/** + * @brief Enable QSPI controller. + * @param[in] qspi The pointer of the specified QSPI module. + * @return None. + * @details Set QSPIEN (QSPI_CTL[0]) to enable QSPI controller. + * \hideinitializer + */ +#define QSPI_ENABLE(qspi) ((qspi)->CTL |= QSPI_CTL_QSPIEN_Msk) + +/** + * @brief Disable QSPI controller. + * @param[in] qspi The pointer of the specified QSPI module. + * @return None. + * @details Clear QSPIEN (QSPI_CTL[0]) to disable QSPI controller. + * \hideinitializer + */ +#define QSPI_DISABLE(qspi) ((qspi)->CTL &= ~QSPI_CTL_QSPIEN_Msk) + +/** + * @brief Disable QSPI Dual IO function. + * @param[in] qspi is the base address of QSPI module. + * @return none + * \hideinitializer + */ +#define QSPI_DISABLE_DUAL_MODE(qspi) ( (qspi)->CTL &= ~QSPI_CTL_DUALIOEN_Msk ) + +/** + * @brief Enable Dual IO function and set QSPI Dual IO direction to input. + * @param[in] qspi is the base address of QSPI module. + * @return none + * \hideinitializer + */ +#define QSPI_ENABLE_DUAL_INPUT_MODE(qspi) ( (qspi)->CTL = ((qspi)->CTL & ~QSPI_CTL_DATDIR_Msk) | QSPI_CTL_DUALIOEN_Msk ) + +/** + * @brief Enable Dual IO function and set QSPI Dual IO direction to output. + * @param[in] qspi is the base address of QSPI module. + * @return none + * \hideinitializer + */ +#define QSPI_ENABLE_DUAL_OUTPUT_MODE(qspi) ( (qspi)->CTL |= QSPI_CTL_DATDIR_Msk | QSPI_CTL_DUALIOEN_Msk ) + +/** + * @brief Disable QSPI Dual IO function. + * @param[in] qspi is the base address of QSPI module. + * @return none + * \hideinitializer + */ +#define QSPI_DISABLE_QUAD_MODE(qspi) ( (qspi)->CTL &= ~QSPI_CTL_QUADIOEN_Msk ) + +/** + * @brief Set QSPI Quad IO direction to input. + * @param[in] qspi is the base address of QSPI module. + * @return none + * \hideinitializer + */ +#define QSPI_ENABLE_QUAD_INPUT_MODE(qspi) ( (qspi)->CTL = ((qspi)->CTL & ~QSPI_CTL_DATDIR_Msk) | QSPI_CTL_QUADIOEN_Msk ) + +/** + * @brief Set QSPI Quad IO direction to output. + * @param[in] qspi is the base address of QSPI module. + * @return none + * \hideinitializer + */ +#define QSPI_ENABLE_QUAD_OUTPUT_MODE(qspi) ( (qspi)->CTL |= QSPI_CTL_DATDIR_Msk | QSPI_CTL_QUADIOEN_Msk ) + +/** + * @brief Set QSPI Master Receive Phase. + * @param[in] qspi is the base address of QSPI module. + * @param[in] rxdly is the clock cycle of delay for rx phase. + * @return none + * \hideinitializer + */ +#define QSPI_SET_MRXPHASE(qspi, rxdly) ( (qspi)->INTERNAL = ((qspi)->INTERNAL & ~QSPI_INTERNAL_MRXPHASE_Msk) | (rxdly<TALM_M +#define REG_RTC_CALM RTC->CALM_M +#define REG_RTC_INTEN RTC->INTEN_M +#define REG_RTC_INTSTS RTC->INTSTS_M +#define REG_RTC_TICK RTC->TICK_M +#define REG_RTC_TAMSK RTC->TAMSK_M +#define REG_RTC_CAMSK RTC->CAMSK_M +#else +#define REG_RTC_TALM RTC->TALM +#define REG_RTC_CALM RTC->CALM +#define REG_RTC_INTEN RTC->INTEN +#define REG_RTC_INTSTS RTC->INTSTS +#define REG_RTC_TICK RTC->TICK +#define REG_RTC_TAMSK RTC->TAMSK +#define REG_RTC_CAMSK RTC->CAMSK +#endif + +/** @addtogroup Standard_Driver Standard Driver + @{ +*/ + +/** @addtogroup RTC_Driver RTC Driver + @{ +*/ + +/** @addtogroup RTC_EXPORTED_CONSTANTS RTC Exported Constants + @{ +*/ +/*---------------------------------------------------------------------------------------------------------*/ +/* RTC Initial Keyword Constant Definitions */ +/*---------------------------------------------------------------------------------------------------------*/ +#define RTC_INIT_KEY 0xA5EB1357UL /*!< RTC Initiation Key to make RTC leaving reset state \hideinitializer */ + +/*---------------------------------------------------------------------------------------------------------*/ +/* RTC Time Attribute Constant Definitions */ +/*---------------------------------------------------------------------------------------------------------*/ +#define RTC_CLOCK_12 0UL /*!< RTC as 12-hour time scale with AM and PM indication \hideinitializer */ +#define RTC_CLOCK_24 1UL /*!< RTC as 24-hour time scale \hideinitializer */ +#define RTC_AM 1UL /*!< RTC as AM indication \hideinitializer */ +#define RTC_PM 2UL /*!< RTC as PM indication \hideinitializer */ + +/*---------------------------------------------------------------------------------------------------------*/ +/* RTC Tick Period Constant Definitions */ +/*---------------------------------------------------------------------------------------------------------*/ +#define RTC_TICK_1_SEC 0x0UL /*!< RTC time tick period is 1 second \hideinitializer */ +#define RTC_TICK_1_2_SEC 0x1UL /*!< RTC time tick period is 1/2 second \hideinitializer */ +#define RTC_TICK_1_4_SEC 0x2UL /*!< RTC time tick period is 1/4 second \hideinitializer */ +#define RTC_TICK_1_8_SEC 0x3UL /*!< RTC time tick period is 1/8 second \hideinitializer */ +#define RTC_TICK_1_16_SEC 0x4UL /*!< RTC time tick period is 1/16 second \hideinitializer */ +#define RTC_TICK_1_32_SEC 0x5UL /*!< RTC time tick period is 1/32 second \hideinitializer */ +#define RTC_TICK_1_64_SEC 0x6UL /*!< RTC time tick period is 1/64 second \hideinitializer */ +#define RTC_TICK_1_128_SEC 0x7UL /*!< RTC time tick period is 1/128 second \hideinitializer */ + +/*---------------------------------------------------------------------------------------------------------*/ +/* RTC Day of Week Constant Definitions */ +/*---------------------------------------------------------------------------------------------------------*/ +#define RTC_SUNDAY 0x0UL /*!< Day of the Week is Sunday \hideinitializer */ +#define RTC_MONDAY 0x1UL /*!< Day of the Week is Monday \hideinitializer */ +#define RTC_TUESDAY 0x2UL /*!< Day of the Week is Tuesday \hideinitializer */ +#define RTC_WEDNESDAY 0x3UL /*!< Day of the Week is Wednesday \hideinitializer */ +#define RTC_THURSDAY 0x4UL /*!< Day of the Week is Thursday \hideinitializer */ +#define RTC_FRIDAY 0x5UL /*!< Day of the Week is Friday \hideinitializer */ +#define RTC_SATURDAY 0x6UL /*!< Day of the Week is Saturday \hideinitializer */ + +/*---------------------------------------------------------------------------------------------------------*/ +/* RTC Miscellaneous Constant Definitions */ +/*---------------------------------------------------------------------------------------------------------*/ +#define RTC_WAIT_COUNT 0xFFFFFFFFUL /*!< Initial Time-out Value \hideinitializer */ +#define RTC_YEAR2000 2000UL /*!< RTC Reference for compute year data \hideinitializer */ + +/*@}*/ /* end of group RTC_EXPORTED_CONSTANTS */ + + +/** @addtogroup RTC_EXPORTED_STRUCTS RTC Exported Structs + @{ +*/ +/** + * @details RTC define Time Data Struct + */ +typedef struct +{ + uint32_t u32Year; /*!< Year value */ + uint32_t u32Month; /*!< Month value */ + uint32_t u32Day; /*!< Day value */ + uint32_t u32DayOfWeek; /*!< Day of week value */ + uint32_t u32Hour; /*!< Hour value */ + uint32_t u32Minute; /*!< Minute value */ + uint32_t u32Second; /*!< Second value */ + uint32_t u32TimeScale; /*!< 12-Hour, 24-Hour */ + uint32_t u32AmPm; /*!< Only Time Scale select 12-hr used */ +} S_RTC_TIME_DATA_T; + +/*@}*/ /* end of group RTC_EXPORTED_STRUCTS */ + + +/** @addtogroup RTC_EXPORTED_FUNCTIONS RTC Exported Functions + @{ +*/ + +/** + * @brief Indicate is Leap Year or not + * + * @param None + * + * @retval 0 This year is not a leap year + * @retval 1 This year is a leap year + * + * @details According to current date, return this year is leap year or not. + * \hideinitializer + */ +#define RTC_IS_LEAP_YEAR() (RTC->LEAPYEAR & RTC_LEAPYEAR_LEAPYEAR_Msk ? 1:0) + +/** + * @brief Clear RTC Alarm Interrupt Flag + * + * @param None + * + * @return None + * + * @details This macro is used to clear RTC alarm interrupt flag. + * \hideinitializer + */ +#define RTC_CLEAR_ALARM_INT_FLAG() (REG_RTC_INTSTS = RTC_INTSTS_ALMIF_Msk) + +/** + * @brief Clear RTC Tick Interrupt Flag + * + * @param None + * + * @return None + * + * @details This macro is used to clear RTC tick interrupt flag. + * \hideinitializer + */ +#define RTC_CLEAR_TICK_INT_FLAG() (REG_RTC_INTSTS = RTC_INTSTS_TICKIF_Msk) + +/** + * @brief Get RTC Alarm Interrupt Flag + * + * @param None + * + * @retval 0 RTC alarm interrupt did not occur + * @retval 1 RTC alarm interrupt occurred + * + * @details This macro indicates RTC alarm interrupt occurred or not. + * \hideinitializer + */ +#define RTC_GET_ALARM_INT_FLAG() ((REG_RTC_INTSTS & RTC_INTSTS_ALMIF_Msk)? 1:0) + +/** + * @brief Get RTC Time Tick Interrupt Flag + * + * @param None + * + * @retval 0 RTC time tick interrupt did not occur + * @retval 1 RTC time tick interrupt occurred + * + * @details This macro indicates RTC time tick interrupt occurred or not. + * \hideinitializer + */ +#define RTC_GET_TICK_INT_FLAG() ((REG_RTC_INTSTS & RTC_INTSTS_TICKIF_Msk)? 1:0) + +/** + * @brief Read Spare Register + * + * @param[in] u32RegNum The spare register number, 0~19. + * + * @return Spare register content + * + * @details Read the specify spare register content. + * @note The returned value is valid only when SPRRDY(SPRCTL[7] SPR Register Ready) bit is set. \n + * And its controlled by RTC Access Enable Register. + * \hideinitializer + */ +#define RTC_READ_SPARE_REGISTER(u32RegNum) (RTC->SPR[(u32RegNum)]) + +int32_t RTC_Open(S_RTC_TIME_DATA_T *sPt); +void RTC_Close(void); + +void RTC_GetDateAndTime(S_RTC_TIME_DATA_T *sPt); +void RTC_GetAlarmDateAndTime(S_RTC_TIME_DATA_T *sPt); +void RTC_SetDateAndTime(S_RTC_TIME_DATA_T *sPt); +void RTC_SetAlarmDateAndTime(S_RTC_TIME_DATA_T *sPt); +void RTC_SetDate(uint32_t u32Year, uint32_t u32Month, uint32_t u32Day, uint32_t u32DayOfWeek); +void RTC_SetTime(uint32_t u32Hour, uint32_t u32Minute, uint32_t u32Second, uint32_t u32TimeMode, uint32_t u32AmPm); +void RTC_SetAlarmDate(uint32_t u32Year, uint32_t u32Month, uint32_t u32Day); +void RTC_SetAlarmTime(uint32_t u32Hour, uint32_t u32Minute, uint32_t u32Second, uint32_t u32TimeMode, uint32_t u32AmPm); +void RTC_SetAlarmDateMask(uint8_t u8IsTenYMsk, uint8_t u8IsYMsk, uint8_t u8IsTenMMsk, uint8_t u8IsMMsk, uint8_t u8IsTenDMsk, uint8_t u8IsDMsk); +void RTC_SetAlarmTimeMask(uint8_t u8IsTenHMsk, uint8_t u8IsHMsk, uint8_t u8IsTenMMsk, uint8_t u8IsMMsk, uint8_t u8IsTenSMsk, uint8_t u8IsSMsk); +uint32_t RTC_GetDayOfWeek(void); +void RTC_SetTickPeriod(uint32_t u32TickSelection); +void RTC_EnableInt(uint32_t u32IntFlagMask); +void RTC_DisableInt(uint32_t u32IntFlagMask); + +/*@}*/ /* end of group RTC_EXPORTED_FUNCTIONS */ + +/*@}*/ /* end of group RTC_Driver */ + +/*@}*/ /* end of group Standard_Driver */ + +#ifdef __cplusplus +} +#endif + +#endif /* __NU_RTC_H__ */ + diff --git a/bsp/nuvoton/libraries/ma35/StdDriver/inc/nu_sc.h b/bsp/nuvoton/libraries/ma35/StdDriver/inc/nu_sc.h new file mode 100644 index 0000000000..6ebb7bddc5 --- /dev/null +++ b/bsp/nuvoton/libraries/ma35/StdDriver/inc/nu_sc.h @@ -0,0 +1,266 @@ +/**************************************************************************//** + * @file nu_sc.h + * @brief Smartcard (SC) driver header file + * + * SPDX-License-Identifier: Apache-2.0 + * @copyright (C) 2020 Nuvoton Technology Corp. All rights reserved. + *****************************************************************************/ +#ifndef __NU_SC_H__ +#define __NU_SC_H__ + +#ifdef __cplusplus +extern "C" +{ +#endif + + +/** @addtogroup Standard_Driver Standard Driver + @{ +*/ + +/** @addtogroup SC_Driver SC Driver + @{ +*/ + +/** @addtogroup SC_EXPORTED_CONSTANTS SC Exported Constants + @{ +*/ +#define SC_INTERFACE_NUM 2 /*!< Smartcard interface numbers \hideinitializer */ +#define SC_PIN_STATE_HIGH 1 /*!< Smartcard pin status high \hideinitializer */ +#define SC_PIN_STATE_LOW 0 /*!< Smartcard pin status low \hideinitializer */ +#define SC_PIN_STATE_IGNORE 0xFFFFFFFF /*!< Ignore pin status \hideinitializer */ +#define SC_CLK_ON 1 /*!< Smartcard clock on \hideinitializer */ +#define SC_CLK_OFF 0 /*!< Smartcard clock off \hideinitializer */ + +#define SC_TMR_MODE_0 (0ul << SC_TMRCTL0_OPMODE_Pos) /*!INTEN |= (u32Mask)) + +/** + * @brief This macro disable smartcard interrupt + * @param[in] sc Base address of smartcard module + * @param[in] u32Mask Interrupt mask to be disabled. A combination of + * - \ref SC_INTEN_ACERRIEN_Msk + * - \ref SC_INTEN_RXTOIEN_Msk + * - \ref SC_INTEN_INITIEN_Msk + * - \ref SC_INTEN_CDIEN_Msk + * - \ref SC_INTEN_BGTIEN_Msk + * - \ref SC_INTEN_TMR2IEN_Msk + * - \ref SC_INTEN_TMR1IEN_Msk + * - \ref SC_INTEN_TMR0IEN_Msk + * - \ref SC_INTEN_TERRIEN_Msk + * - \ref SC_INTEN_TBEIEN_Msk + * - \ref SC_INTEN_RDAIEN_Msk + * @return None + * \hideinitializer + */ +#define SC_DISABLE_INT(sc, u32Mask) ((sc)->INTEN &= ~(u32Mask)) + +/** + * @brief This macro set VCC pin state of smartcard interface + * @param[in] sc Base address of smartcard module + * @param[in] u32State Pin state of VCC pin, valid parameters are \ref SC_PIN_STATE_HIGH and \ref SC_PIN_STATE_LOW + * @return None + * \hideinitializer + */ +#define SC_SET_VCC_PIN(sc, u32State) \ + do {\ + while((sc)->PINCTL & SC_PINCTL_SYNC_Msk);\ + if(u32State)\ + (sc)->PINCTL |= SC_PINCTL_PWREN_Msk;\ + else\ + (sc)->PINCTL &= ~SC_PINCTL_PWREN_Msk;\ + }while(0) + + +/** + * @brief This macro turns CLK output on or off + * @param[in] sc Base address of smartcard module + * @param[in] u32OnOff Clock on or off for selected smartcard module, valid values are \ref SC_CLK_ON and \ref SC_CLK_OFF + * @return None + * \hideinitializer + */ +#define SC_SET_CLK_PIN(sc, u32OnOff)\ + do {\ + while((sc)->PINCTL & SC_PINCTL_SYNC_Msk);\ + if(u32OnOff)\ + (sc)->PINCTL |= SC_PINCTL_CLKKEEP_Msk;\ + else\ + (sc)->PINCTL &= ~(SC_PINCTL_CLKKEEP_Msk);\ + }while(0) + +/** + * @brief This macro set I/O pin state of smartcard interface + * @param[in] sc Base address of smartcard module + * @param[in] u32State Pin state of I/O pin, valid parameters are \ref SC_PIN_STATE_HIGH and \ref SC_PIN_STATE_LOW + * @return None + * \hideinitializer + */ +#define SC_SET_IO_PIN(sc, u32State)\ + do {\ + while((sc)->PINCTL & SC_PINCTL_SYNC_Msk);\ + if(u32State)\ + (sc)->PINCTL |= SC_PINCTL_SCDATA_Msk;\ + else\ + (sc)->PINCTL &= ~SC_PINCTL_SCDATA_Msk;\ + }while(0) + +/** + * @brief This macro set RST pin state of smartcard interface + * @param[in] sc Base address of smartcard module + * @param[in] u32State Pin state of RST pin, valid parameters are \ref SC_PIN_STATE_HIGH and \ref SC_PIN_STATE_LOW + * @return None + * \hideinitializer + */ +#define SC_SET_RST_PIN(sc, u32State)\ + do {\ + while((sc)->PINCTL & SC_PINCTL_SYNC_Msk);\ + if(u32State)\ + (sc)->PINCTL |= SC_PINCTL_RSTEN_Msk;\ + else\ + (sc)->PINCTL &= ~SC_PINCTL_RSTEN_Msk;\ + }while(0) + +/** + * @brief This macro read one byte from smartcard module receive FIFO + * @param[in] sc Base address of smartcard module + * @return One byte read from receive FIFO + * \hideinitializer + */ +#define SC_READ(sc) ((char)((sc)->DAT)) + +/** + * @brief This macro write one byte to smartcard module transmit FIFO + * @param[in] sc Base address of smartcard module + * @param[in] u8Data Data to write to transmit FIFO + * @return None + * \hideinitializer + */ +#define SC_WRITE(sc, u8Data) ((sc)->DAT = (u8Data)) + +/** + * @brief This macro set smartcard stop bit length + * @param[in] sc Base address of smartcard module + * @param[in] u32Len Stop bit length, ether 1 or 2. + * @return None + * @details Stop bit length must be 1 for T = 1 protocol and 2 for T = 0 protocol. + * \hideinitializer + */ +#define SC_SET_STOP_BIT_LEN(sc, u32Len) ((sc)->CTL = ((sc)->CTL & ~SC_CTL_NSB_Msk) | ((u32Len) == 1 ? SC_CTL_NSB_Msk : 0)) + +/* Declare these inline functions here to avoid MISRA C 2004 rule 8.1 error */ +__STATIC_INLINE void SC_SetTxRetry(SC_T *sc, uint32_t u32Count); +__STATIC_INLINE void SC_SetRxRetry(SC_T *sc, uint32_t u32Count); + +/** + * @brief Enable/Disable Tx error retry, and set Tx error retry count + * @param[in] sc Base address of smartcard module + * @param[in] u32Count The number of times of Tx error retry count, between 0~8. 0 means disable Tx error retry + * @return None + */ +__STATIC_INLINE void SC_SetTxRetry(SC_T *sc, uint32_t u32Count) +{ + while ((sc)->CTL & SC_CTL_SYNC_Msk) + { + ; + } + /* Retry count must set while enable bit disabled, so disable it first */ + (sc)->CTL &= ~(SC_CTL_TXRTY_Msk | SC_CTL_TXRTYEN_Msk); + + if ((u32Count) != 0UL) + { + while ((sc)->CTL & SC_CTL_SYNC_Msk) + { + ; + } + (sc)->CTL |= (((u32Count) - 1UL) << SC_CTL_TXRTY_Pos) | SC_CTL_TXRTYEN_Msk; + } +} + +/** + * @brief Enable/Disable Rx error retry, and set Rx error retry count + * @param[in] sc Base address of smartcard module + * @param[in] u32Count The number of times of Rx error retry count, between 0~8. 0 means disable Rx error retry + * @return None + */ +__STATIC_INLINE void SC_SetRxRetry(SC_T *sc, uint32_t u32Count) +{ + while ((sc)->CTL & SC_CTL_SYNC_Msk) + { + ; + } + /* Retry count must set while enable bit disabled, so disable it first */ + (sc)->CTL &= ~(SC_CTL_RXRTY_Msk | SC_CTL_RXRTYEN_Msk); + + if ((u32Count) != 0UL) + { + while ((sc)->CTL & SC_CTL_SYNC_Msk) + { + ; + } + (sc)->CTL |= (((u32Count) - 1UL) << SC_CTL_RXRTY_Pos) | SC_CTL_RXRTYEN_Msk; + } + +} + + +uint32_t SC_IsCardInserted(SC_T *sc); +void SC_ClearFIFO(SC_T *sc); +void SC_Close(SC_T *sc); +void SC_Open(SC_T *sc, uint32_t u32CardDet, uint32_t u32PWR); +void SC_ResetReader(SC_T *sc); +void SC_SetBlockGuardTime(SC_T *sc, uint32_t u32BGT); +void SC_SetCharGuardTime(SC_T *sc, uint32_t u32CGT); +void SC_StopAllTimer(SC_T *sc); +void SC_StartTimer(SC_T *sc, uint32_t u32TimerNum, uint32_t u32Mode, uint32_t u32ETUCount); +void SC_StopTimer(SC_T *sc, uint32_t u32TimerNum); +uint32_t SC_GetInterfaceClock(SC_T *sc); + + +/*@}*/ /* end of group SC_EXPORTED_FUNCTIONS */ + +/*@}*/ /* end of group SC_Driver */ + +/*@}*/ /* end of group Standard_Driver */ + +#ifdef __cplusplus +} +#endif + +#endif /* __NU_SC_H__ */ + diff --git a/bsp/nuvoton/libraries/ma35/StdDriver/inc/nu_scuart.h b/bsp/nuvoton/libraries/ma35/StdDriver/inc/nu_scuart.h new file mode 100644 index 0000000000..1224df48ed --- /dev/null +++ b/bsp/nuvoton/libraries/ma35/StdDriver/inc/nu_scuart.h @@ -0,0 +1,265 @@ +/**************************************************************************//** + * @file nu_scuart.h + * @brief Smartcard UART mode (SCUART) driver header file + * + * SPDX-License-Identifier: Apache-2.0 + * @copyright (C) 2020 Nuvoton Technology Corp. All rights reserved. + *****************************************************************************/ +#ifndef __NU_SCUART_H__ +#define __NU_SCUART_H__ + +#ifdef __cplusplus +extern "C" +{ +#endif + + +/** @addtogroup Standard_Driver Standard Driver + @{ +*/ + +/** @addtogroup SCUART_Driver SCUART Driver + @{ +*/ + +/** @addtogroup SCUART_EXPORTED_CONSTANTS SCUART Exported Constants + @{ +*/ +#define SCUART_CHAR_LEN_5 (0x3ul << SC_UARTCTL_WLS_Pos) /*!< Set SCUART word length to 5 bits \hideinitializer */ +#define SCUART_CHAR_LEN_6 (0x2ul << SC_UARTCTL_WLS_Pos) /*!< Set SCUART word length to 6 bits \hideinitializer */ +#define SCUART_CHAR_LEN_7 (0x1ul << SC_UARTCTL_WLS_Pos) /*!< Set SCUART word length to 7 bits \hideinitializer */ +#define SCUART_CHAR_LEN_8 (0UL) /*!< Set SCUART word length to 8 bits \hideinitializer */ + +#define SCUART_PARITY_NONE (SC_UARTCTL_PBOFF_Msk) /*!< Set SCUART transfer with no parity \hideinitializer */ +#define SCUART_PARITY_ODD (SC_UARTCTL_OPE_Msk) /*!< Set SCUART transfer with odd parity \hideinitializer */ +#define SCUART_PARITY_EVEN (0UL) /*!< Set SCUART transfer with even parity \hideinitializer */ + +#define SCUART_STOP_BIT_1 (SC_CTL_NSB_Msk) /*!< Set SCUART transfer with one stop bit \hideinitializer */ +#define SCUART_STOP_BIT_2 (0UL) /*!< Set SCUART transfer with two stop bits \hideinitializer */ + + +/*@}*/ /* end of group SCUART_EXPORTED_CONSTANTS */ + + +/** @addtogroup SCUART_EXPORTED_FUNCTIONS SCUART Exported Functions + @{ +*/ + +/* TX Macros */ +/** + * @brief Write Data to Tx data register + * @param[in] sc The base address of smartcard module. + * @param[in] u8Data Data byte to transmit + * @return None + * \hideinitializer + */ +#define SCUART_WRITE(sc, u8Data) ((sc)->DAT = (u8Data)) + +/** + * @brief Get TX FIFO empty flag status from register + * @param[in] sc The base address of smartcard module + * @return Transmit FIFO empty status + * @retval 0 Transmit FIFO is not empty + * @retval SC_STATUS_TXEMPTY_Msk Transmit FIFO is empty + * \hideinitializer + */ +#define SCUART_GET_TX_EMPTY(sc) ((sc)->STATUS & SC_STATUS_TXEMPTY_Msk) + +/** + * @brief Get TX FIFO full flag status from register + * @param[in] sc The base address of smartcard module + * @return Transmit FIFO full status + * @retval 0 Transmit FIFO is not full + * @retval SC_STATUS_TXFULL_Msk Transmit FIFO is full + * \hideinitializer + */ +#define SCUART_GET_TX_FULL(sc) ((sc)->STATUS & SC_STATUS_TXFULL_Msk) + +/** + * @brief Wait specified smartcard port transmission complete + * @param[in] sc The base address of smartcard module + * @return None + * @note This Macro blocks until transmit complete. + * \hideinitializer + */ +#define SCUART_WAIT_TX_EMPTY(sc) while((sc)->STATUS & SC_STATUS_TXACT_Msk) + +/** + * @brief Check specified smartcard port transmit FIFO is full or not + * @param[in] sc The base address of smartcard module + * @return Transmit FIFO full status + * @retval 0 Transmit FIFO is not full + * @retval 1 Transmit FIFO is full + * \hideinitializer + */ +#define SCUART_IS_TX_FULL(sc) ((sc)->STATUS & SC_STATUS_TXFULL_Msk ? 1 : 0) + +/** + * @brief Check specified smartcard port transmission is over + * @param[in] sc The base address of smartcard module + * @return Transmit complete status + * @retval 0 Transmit is not complete + * @retval 1 Transmit complete + * \hideinitializer + */ +#define SCUART_IS_TX_EMPTY(sc) ((sc)->STATUS & SC_STATUS_TXACT_Msk ? 0 : 1) + +/** + * @brief Check specified Smartcard port Transmission Status + * @param[in] sc The pointer of smartcard module. + * @retval 0 Transmit is completed + * @retval 1 Transmit is active + * @details TXACT (SC_STATUS[31]) is set by hardware when Tx transfer is in active and the STOP bit of the last byte has been transmitted. + * \hideinitializer + */ +#define SCUART_IS_TX_ACTIVE(sc) (((sc)->STATUS & SC_STATUS_TXACT_Msk)? 1 : 0) + +/* RX Macros */ + +/** + * @brief Read Rx data register + * @param[in] sc The base address of smartcard module + * @return The oldest data byte in RX FIFO + * \hideinitializer + */ +#define SCUART_READ(sc) ((sc)->DAT) + +/** + * @brief Get RX FIFO empty flag status from register + * @param[in] sc The base address of smartcard module + * @return Receive FIFO empty status + * @retval 0 Receive FIFO is not empty + * @retval SC_STATUS_RXEMPTY_Msk Receive FIFO is empty + * \hideinitializer + */ +#define SCUART_GET_RX_EMPTY(sc) ((sc)->STATUS & SC_STATUS_RXEMPTY_Msk) + + +/** + * @brief Get RX FIFO full flag status from register + * @param[in] sc The base address of smartcard module + * @return Receive FIFO full status + * @retval 0 Receive FIFO is not full + * @retval SC_STATUS_RXFULLF_Msk Receive FIFO is full + * \hideinitializer + */ +#define SCUART_GET_RX_FULL(sc) ((sc)->STATUS & SC_STATUS_RXFULL_Msk) + +/** + * @brief Check if receive data number in FIFO reach FIFO trigger level or not + * @param[in] sc The base address of smartcard module + * @return Receive FIFO data status + * @retval 0 The number of bytes in receive FIFO is less than trigger level + * @retval 1 The number of bytes in receive FIFO equals or larger than trigger level + * @note If receive trigger level is \b not 1 byte, this macro return 0 does not necessary indicates there is \b no data in FIFO + * \hideinitializer + */ +#define SCUART_IS_RX_READY(sc) ((sc)->INTSTS & SC_INTSTS_RDAIF_Msk ? 1 : 0) + +/** + * @brief Check specified smartcard port receive FIFO is full or not + * @param[in] sc The base address of smartcard module + * @return Receive FIFO full status + * @retval 0 Receive FIFO is not full + * @retval 1 Receive FIFO is full + * \hideinitializer + */ +#define SCUART_IS_RX_FULL(sc) ((sc)->STATUS & SC_STATUS_RXFULL_Msk ? 1 : 0) + +/* Interrupt Macros */ + +/** + * @brief Enable specified interrupts + * @param[in] sc The base address of smartcard module + * @param[in] u32Mask Interrupt masks to enable, a combination of following bits + * - \ref SC_INTEN_RXTOIEN_Msk + * - \ref SC_INTEN_TERRIEN_Msk + * - \ref SC_INTEN_TBEIEN_Msk + * - \ref SC_INTEN_RDAIEN_Msk + * @return None + * \hideinitializer + */ +#define SCUART_ENABLE_INT(sc, u32Mask) ((sc)->INTEN |= (u32Mask)) + +/** + * @brief Disable specified interrupts + * @param[in] sc The base address of smartcard module + * @param[in] u32Mask Interrupt masks to disable, a combination of following bits + * - \ref SC_INTEN_RXTOIEN_Msk + * - \ref SC_INTEN_TERRIEN_Msk + * - \ref SC_INTEN_TBEIEN_Msk + * - \ref SC_INTEN_RDAIEN_Msk + * @return None + * \hideinitializer + */ +#define SCUART_DISABLE_INT(sc, u32Mask) ((sc)->INTEN &= ~(u32Mask)) + +/** + * @brief Get specified interrupt flag/status + * @param[in] sc The base address of smartcard module + * @param[in] u32Type Interrupt flag/status to check, could be one of following value + * - \ref SC_INTSTS_RXTOIF_Msk + * - \ref SC_INTSTS_TERRIF_Msk + * - \ref SC_INTSTS_TBEIF_Msk + * - \ref SC_INTSTS_RDAIF_Msk + * @return The status of specified interrupt + * @retval 0 Specified interrupt does not happened + * @retval 1 Specified interrupt happened + * \hideinitializer + */ +#define SCUART_GET_INT_FLAG(sc, u32Type) ((sc)->INTSTS & (u32Type) ? 1 : 0) + +/** + * @brief Clear specified interrupt flag/status + * @param[in] sc The base address of smartcard module + * @param[in] u32Type Interrupt flag/status to clear, could be the combination of following values + * - \ref SC_INTSTS_RXTOIF_Msk + * - \ref SC_INTSTS_TERRIF_Msk + * - \ref SC_INTSTS_TBEIF_Msk + * @return None + * \hideinitializer + */ +#define SCUART_CLR_INT_FLAG(sc, u32Type) ((sc)->INTSTS = (u32Type)) + +/** + * @brief Get receive error flag/status + * @param[in] sc The base address of smartcard module + * @return Current receive error status, could one of following errors: + * @retval SC_STATUS_PEF_Msk Parity error + * @retval SC_STATUS_FEF_Msk Frame error + * @retval SC_STATUS_BEF_Msk Break error + * \hideinitializer + */ +#define SCUART_GET_ERR_FLAG(sc) ((sc)->STATUS & (SC_STATUS_PEF_Msk | SC_STATUS_FEF_Msk | SC_STATUS_BEF_Msk)) + +/** + * @brief Clear specified receive error flag/status + * @param[in] sc The base address of smartcard module + * @param[in] u32Mask Receive error flag/status to clear, combination following values + * - \ref SC_STATUS_PEF_Msk + * - \ref SC_STATUS_FEF_Msk + * - \ref SC_STATUS_BEF_Msk + * @return None + * \hideinitializer + */ +#define SCUART_CLR_ERR_FLAG(sc, u32Mask) ((sc)->STATUS = (u32Mask)) + +void SCUART_Close(SC_T *sc); +uint32_t SCUART_Open(SC_T *sc, uint32_t u32baudrate); +uint32_t SCUART_Read(SC_T *sc, uint8_t pu8RxBuf[], uint32_t u32ReadBytes); +uint32_t SCUART_SetLineConfig(SC_T *sc, uint32_t u32Baudrate, uint32_t u32DataWidth, uint32_t u32Parity, uint32_t u32StopBits); +void SCUART_SetTimeoutCnt(SC_T *sc, uint32_t u32TOC); +void SCUART_Write(SC_T *sc, uint8_t pu8TxBuf[], uint32_t u32WriteBytes); + +/*@}*/ /* end of group SCUART_EXPORTED_FUNCTIONS */ + +/*@}*/ /* end of group SCUART_Driver */ + +/*@}*/ /* end of group Standard_Driver */ + +#ifdef __cplusplus +} +#endif + +#endif /* __NU_SCUART_H__ */ + diff --git a/bsp/nuvoton/libraries/ma35/StdDriver/inc/nu_sdh.h b/bsp/nuvoton/libraries/ma35/StdDriver/inc/nu_sdh.h new file mode 100644 index 0000000000..4473f6fba1 --- /dev/null +++ b/bsp/nuvoton/libraries/ma35/StdDriver/inc/nu_sdh.h @@ -0,0 +1,121 @@ +/****************************************************************************//** + * @file nu_sdh.h + * @brief SDH driver header file + * + * SPDX-License-Identifier: Apache-2.0 + * @copyright (C) 2020 Nuvoton Technology Corp. All rights reserved. + *****************************************************************************/ +#ifndef __NU_SDH_H__ +#define __NU_SDH_H__ + +#ifdef __cplusplus +extern "C" +{ +#endif + +/** @addtogroup Standard_Driver Standard Driver + @{ +*/ + +/** @addtogroup SDH_Driver SDH Driver + @{ +*/ + +/** @addtogroup SDH_EXPORTED_CONSTANTS SDH Exported Constants + @{ +*/ + +#define SDH_POWER_ON 0x01 +#define SDH_POWER_180 0x0A +#define SDH_POWER_300 0x0C +#define SDH_POWER_330 0x0E + +#define SDH_RESET_ALL 0x01 +#define SDH_RESET_CMD 0x02 +#define SDH_RESET_DATA 0x04 + +#define SDH_CMD_RESP_MASK 0x03 +#define SDH_CMD_CRC 0x08 +#define SDH_CMD_INDEX 0x10 +#define SDH_CMD_DATA 0x20 +#define SDH_CMD_ABORTCMD 0xC0 + +#define SDH_CMD_RESP_NONE 0x00 +#define SDH_CMD_RESP_LONG 0x01 +#define SDH_CMD_RESP_SHORT 0x02 +#define SDH_CMD_RESP_SHORT_BUSY 0x03 + + +/* MMC command */ +#define MMC_CMD_STOP_TRANSMISSION 12 + +/* MMC response */ +#define MMC_RSP_PRESENT (1 << 0) +#define MMC_RSP_136 (1 << 1) /* 136 bit response */ +#define MMC_RSP_CRC (1 << 2) /* expect valid crc */ +#define MMC_RSP_BUSY (1 << 3) /* card may send busy */ +#define MMC_RSP_OPCODE (1 << 4) /* response contains opcode */ + +#define MMC_RSP_NONE (0) +#define MMC_RSP_R1 (MMC_RSP_PRESENT|MMC_RSP_CRC|MMC_RSP_OPCODE) +#define MMC_RSP_R1b (MMC_RSP_PRESENT|MMC_RSP_CRC|MMC_RSP_OPCODE|MMC_RSP_BUSY) +#define MMC_RSP_R2 (MMC_RSP_PRESENT|MMC_RSP_136|MMC_RSP_CRC) +#define MMC_RSP_R3 (MMC_RSP_PRESENT) +#define MMC_RSP_R4 (MMC_RSP_PRESENT) +#define MMC_RSP_R5 (MMC_RSP_PRESENT|MMC_RSP_CRC|MMC_RSP_OPCODE) +#define MMC_RSP_R6 (MMC_RSP_PRESENT|MMC_RSP_CRC|MMC_RSP_OPCODE) +#define MMC_RSP_R7 (MMC_RSP_PRESENT|MMC_RSP_CRC|MMC_RSP_OPCODE) + +#define MMC_DATA_READ 1 +#define MMC_DATA_WRITE 2 + +#define SDH_BLOCK_SIZE 512ul + +struct mmc_cmd +{ + unsigned short cmdidx; + unsigned int resp_type; + unsigned int cmdarg; + unsigned int response[4]; +}; + +struct mmc_data +{ + union + { + char *dest; + const char *src; /* src buffers don't get written to */ + }; + unsigned int flags; + unsigned int blocks; + unsigned int blocksize; +}; + +#define SDH_ISCARDINSERTED(SDH) (SDH->S_PSTATE.CARD_INSERTED && SDH->S_PSTATE.CARD_STABLE) + + +/*@}*/ /* end of group SDH_EXPORTED_CONSTANTS */ + +/** @addtogroup SDH_EXPORTED_FUNCTIONS SDH Exported Functions + @{ +*/ + +void SDH_DumpReg(SDH_T *sdh); +void SDH_Reset(SDH_T *sdh, uint8_t u8Mask); +int SDH_SetBusWidth(SDH_T *sdh, uint32_t u32BusWidth); +uint32_t SDH_SetClock(SDH_T *sdh, uint32_t u32SrcFreqInHz, uint32_t u32ExceptedFreqInHz); +int SD_GetBusStatus(SDH_T *sdh, uint32_t cmdidx); +void SDH_SetPower(SDH_T *sdh, uint32_t u32OnOff); + +/*@}*/ /* end of group SDH_EXPORTED_FUNCTIONS */ + +/*@}*/ /* end of group SDH_Driver */ + +/*@}*/ /* end of group Standard_Driver */ +#ifdef __cplusplus +} +#endif + +#endif + + diff --git a/bsp/nuvoton/libraries/ma35/StdDriver/inc/nu_spi.h b/bsp/nuvoton/libraries/ma35/StdDriver/inc/nu_spi.h new file mode 100644 index 0000000000..873f849c1d --- /dev/null +++ b/bsp/nuvoton/libraries/ma35/StdDriver/inc/nu_spi.h @@ -0,0 +1,607 @@ +/**************************************************************************//** + * @file nu_spi.h + * @brief SPI driver header file + * + * SPDX-License-Identifier: Apache-2.0 + * @copyright (C) 2020 Nuvoton Technology Corp. All rights reserved. + *****************************************************************************/ +#ifndef __NU_SPI_H__ +#define __NU_SPI_H__ + +#ifdef __cplusplus +extern "C" +{ +#endif + + +/** @addtogroup Standard_Driver Standard Driver + @{ +*/ + +/** @addtogroup SPI_Driver SPI Driver + @{ +*/ + +/** @addtogroup SPI_EXPORTED_CONSTANTS SPI Exported Constants + @{ +*/ + +#define SPI_MODE_0 (SPI_CTL_TXNEG_Msk) /*!< CLKPOL=0; RXNEG=0; TXNEG=1 \hideinitializer */ +#define SPI_MODE_1 (SPI_CTL_RXNEG_Msk) /*!< CLKPOL=0; RXNEG=1; TXNEG=0 \hideinitializer */ +#define SPI_MODE_2 (SPI_CTL_CLKPOL_Msk | SPI_CTL_RXNEG_Msk) /*!< CLKPOL=1; RXNEG=1; TXNEG=0 \hideinitializer */ +#define SPI_MODE_3 (SPI_CTL_CLKPOL_Msk | SPI_CTL_TXNEG_Msk) /*!< CLKPOL=1; RXNEG=0; TXNEG=1 \hideinitializer */ + +#define SPI_SLAVE (SPI_CTL_SLAVE_Msk) /*!< Set as slave \hideinitializer */ +#define SPI_MASTER (0x0U) /*!< Set as master \hideinitializer */ + +#define SPI_SS (SPI_SSCTL_SS_Msk) /*!< Set SS \hideinitializer */ +#define SPI_SS_ACTIVE_HIGH (SPI_SSCTL_SSACTPOL_Msk) /*!< SS active high \hideinitializer */ +#define SPI_SS_ACTIVE_LOW (0x0U) /*!< SS active low \hideinitializer */ + +/* SPI Interrupt Mask */ +#define SPI_UNIT_INT_MASK (0x001U) /*!< Unit transfer interrupt mask \hideinitializer */ +#define SPI_SSACT_INT_MASK (0x002U) /*!< Slave selection signal active interrupt mask \hideinitializer */ +#define SPI_SSINACT_INT_MASK (0x004U) /*!< Slave selection signal inactive interrupt mask \hideinitializer */ +#define SPI_SLVUR_INT_MASK (0x008U) /*!< Slave under run interrupt mask \hideinitializer */ +#define SPI_SLVBE_INT_MASK (0x010U) /*!< Slave bit count error interrupt mask \hideinitializer */ +#define SPI_TXUF_INT_MASK (0x040U) /*!< Slave TX underflow interrupt mask \hideinitializer */ +#define SPI_FIFO_TXTH_INT_MASK (0x080U) /*!< FIFO TX threshold interrupt mask \hideinitializer */ +#define SPI_FIFO_RXTH_INT_MASK (0x100U) /*!< FIFO RX threshold interrupt mask \hideinitializer */ +#define SPI_FIFO_RXOV_INT_MASK (0x200U) /*!< FIFO RX overrun interrupt mask \hideinitializer */ +#define SPI_FIFO_RXTO_INT_MASK (0x400U) /*!< FIFO RX time-out interrupt mask \hideinitializer */ + +/* SPI Status Mask */ +#define SPI_BUSY_MASK (0x01U) /*!< Busy status mask \hideinitializer */ +#define SPI_RX_EMPTY_MASK (0x02U) /*!< RX empty status mask \hideinitializer */ +#define SPI_RX_FULL_MASK (0x04U) /*!< RX full status mask \hideinitializer */ +#define SPI_TX_EMPTY_MASK (0x08U) /*!< TX empty status mask \hideinitializer */ +#define SPI_TX_FULL_MASK (0x10U) /*!< TX full status mask \hideinitializer */ +#define SPI_TXRX_RESET_MASK (0x20U) /*!< TX or RX reset status mask \hideinitializer */ +#define SPI_SPIEN_STS_MASK (0x40U) /*!< SPIEN status mask \hideinitializer */ +#define SPI_SSLINE_STS_MASK (0x80U) /*!< SPIx_SS line status mask \hideinitializer */ + + +/* I2S Data Width */ +#define SPII2S_DATABIT_8 (0U << SPI_I2SCTL_WDWIDTH_Pos) /*!< I2S data width is 8-bit \hideinitializer */ +#define SPII2S_DATABIT_16 (1U << SPI_I2SCTL_WDWIDTH_Pos) /*!< I2S data width is 16-bit \hideinitializer */ +#define SPII2S_DATABIT_24 (2U << SPI_I2SCTL_WDWIDTH_Pos) /*!< I2S data width is 24-bit \hideinitializer */ +#define SPII2S_DATABIT_32 (3U << SPI_I2SCTL_WDWIDTH_Pos) /*!< I2S data width is 32-bit \hideinitializer */ + +/* I2S Audio Format */ +#define SPII2S_MONO SPI_I2SCTL_MONO_Msk /*!< Monaural channel \hideinitializer */ +#define SPII2S_STEREO (0U) /*!< Stereo channel \hideinitializer */ + +/* I2S Data Format */ +#define SPII2S_FORMAT_I2S (0U<STATUS = SPI_STATUS_UNITIF_Msk) + +/** + * @brief Trigger RX PDMA function. + * @param[in] spi The pointer of the specified SPI module. + * @return None. + * @details Set RXPDMAEN bit of SPI_PDMACTL register to enable RX PDMA transfer function. + * \hideinitializer + */ +#define SPI_TRIGGER_RX_PDMA(spi) ((spi)->PDMACTL |= SPI_PDMACTL_RXPDMAEN_Msk) + +/** + * @brief Trigger TX PDMA function. + * @param[in] spi The pointer of the specified SPI module. + * @return None. + * @details Set TXPDMAEN bit of SPI_PDMACTL register to enable TX PDMA transfer function. + * \hideinitializer + */ +#define SPI_TRIGGER_TX_PDMA(spi) ((spi)->PDMACTL |= SPI_PDMACTL_TXPDMAEN_Msk) + +/** + * @brief Trigger TX and RX PDMA function. + * @param[in] spi The pointer of the specified SPI module. + * @return None. + * @details Set TXPDMAEN bit and RXPDMAEN bit of SPI_PDMACTL register to enable TX and RX PDMA transfer function. + * \hideinitializer + */ +#define SPI_TRIGGER_TX_RX_PDMA(spi) ((spi)->PDMACTL |= (SPI_PDMACTL_TXPDMAEN_Msk | SPI_PDMACTL_RXPDMAEN_Msk)) + +/** + * @brief Disable RX PDMA transfer. + * @param[in] spi The pointer of the specified SPI module. + * @return None. + * @details Clear RXPDMAEN bit of SPI_PDMACTL register to disable RX PDMA transfer function. + * \hideinitializer + */ +#define SPI_DISABLE_RX_PDMA(spi) ( (spi)->PDMACTL &= ~SPI_PDMACTL_RXPDMAEN_Msk ) + +/** + * @brief Disable TX PDMA transfer. + * @param[in] spi The pointer of the specified SPI module. + * @return None. + * @details Clear TXPDMAEN bit of SPI_PDMACTL register to disable TX PDMA transfer function. + * \hideinitializer + */ +#define SPI_DISABLE_TX_PDMA(spi) ( (spi)->PDMACTL &= ~SPI_PDMACTL_TXPDMAEN_Msk ) + +/** + * @brief Disable TX and RX PDMA transfer. + * @param[in] spi The pointer of the specified SPI module. + * @return None. + * @details Clear TXPDMAEN bit and RXPDMAEN bit of SPI_PDMACTL register to disable TX and RX PDMA transfer function. + * \hideinitializer + */ +#define SPI_DISABLE_TX_RX_PDMA(spi) ( (spi)->PDMACTL &= ~(SPI_PDMACTL_TXPDMAEN_Msk | SPI_PDMACTL_RXPDMAEN_Msk) ) + +/** + * @brief Get the count of available data in RX FIFO. + * @param[in] spi The pointer of the specified SPI module. + * @return The count of available data in RX FIFO. + * @details Read RXCNT (SPI_STATUS[27:24]) to get the count of available data in RX FIFO. + * \hideinitializer + */ +#define SPI_GET_RX_FIFO_COUNT(spi) (((spi)->STATUS & SPI_STATUS_RXCNT_Msk) >> SPI_STATUS_RXCNT_Pos) + +/** + * @brief Get the RX FIFO empty flag. + * @param[in] spi The pointer of the specified SPI module. + * @retval 0 RX FIFO is not empty. + * @retval 1 RX FIFO is empty. + * @details Read RXEMPTY bit of SPI_STATUS register to get the RX FIFO empty flag. + * \hideinitializer + */ +#define SPI_GET_RX_FIFO_EMPTY_FLAG(spi) (((spi)->STATUS & SPI_STATUS_RXEMPTY_Msk)>>SPI_STATUS_RXEMPTY_Pos) + +/** + * @brief Get the TX FIFO empty flag. + * @param[in] spi The pointer of the specified SPI module. + * @retval 0 TX FIFO is not empty. + * @retval 1 TX FIFO is empty. + * @details Read TXEMPTY bit of SPI_STATUS register to get the TX FIFO empty flag. + * \hideinitializer + */ +#define SPI_GET_TX_FIFO_EMPTY_FLAG(spi) (((spi)->STATUS & SPI_STATUS_TXEMPTY_Msk)>>SPI_STATUS_TXEMPTY_Pos) + +/** + * @brief Get the TX FIFO full flag. + * @param[in] spi The pointer of the specified SPI module. + * @retval 0 TX FIFO is not full. + * @retval 1 TX FIFO is full. + * @details Read TXFULL bit of SPI_STATUS register to get the TX FIFO full flag. + * \hideinitializer + */ +#define SPI_GET_TX_FIFO_FULL_FLAG(spi) (((spi)->STATUS & SPI_STATUS_TXFULL_Msk)>>SPI_STATUS_TXFULL_Pos) + +/** + * @brief Get the datum read from RX register. + * @param[in] spi The pointer of the specified SPI module. + * @return Data in RX register. + * @details Read SPI_RX register to get the received datum. + * \hideinitializer + */ +#define SPI_READ_RX(spi) ((spi)->RX) + +/** + * @brief Write datum to TX register. + * @param[in] spi The pointer of the specified SPI module. + * @param[in] u32TxData The datum which user attempt to transfer through SPI bus. + * @return None. + * @details Write u32TxData to SPI_TX register. + * \hideinitializer + */ +#define SPI_WRITE_TX(spi, u32TxData) ((spi)->TX = (u32TxData)) + +/** + * @brief Set SPIx_SS pin to high state. + * @param[in] spi The pointer of the specified SPI module. + * @return None. + * @details Disable automatic slave selection function and set SPIx_SS pin to high state. + * \hideinitializer + */ +#define SPI_SET_SS_HIGH(spi) ((spi)->SSCTL = ((spi)->SSCTL & (~SPI_SSCTL_AUTOSS_Msk)) | (SPI_SSCTL_SSACTPOL_Msk | SPI_SSCTL_SS_Msk)) + +/** + * @brief Set SPIx_SS pin to low state. + * @param[in] spi The pointer of the specified SPI module. + * @return None. + * @details Disable automatic slave selection function and set SPIx_SS pin to low state. + * \hideinitializer + */ +#define SPI_SET_SS_LOW(spi) ((spi)->SSCTL = ((spi)->SSCTL & (~(SPI_SSCTL_AUTOSS_Msk | SPI_SSCTL_SSACTPOL_Msk))) | SPI_SSCTL_SS_Msk) + +/** + * @brief Enable Byte Reorder function. + * @param[in] spi The pointer of the specified SPI module. + * @return None. + * @details Enable Byte Reorder function. The suspend interval depends on the setting of SUSPITV (SPI_CTL[7:4]). + * \hideinitializer + */ +#define SPI_ENABLE_BYTE_REORDER(spi) ((spi)->CTL |= SPI_CTL_REORDER_Msk) + +/** + * @brief Disable Byte Reorder function. + * @param[in] spi The pointer of the specified SPI module. + * @return None. + * @details Clear REORDER bit field of SPI_CTL register to disable Byte Reorder function. + * \hideinitializer + */ +#define SPI_DISABLE_BYTE_REORDER(spi) ((spi)->CTL &= ~SPI_CTL_REORDER_Msk) + +/** + * @brief Set the length of suspend interval. + * @param[in] spi The pointer of the specified SPI module. + * @param[in] u32SuspCycle Decides the length of suspend interval. It could be 0 ~ 15. + * @return None. + * @details Set the length of suspend interval according to u32SuspCycle. + * The length of suspend interval is ((u32SuspCycle + 0.5) * the length of one SPI bus clock cycle). + * \hideinitializer + */ +#define SPI_SET_SUSPEND_CYCLE(spi, u32SuspCycle) ((spi)->CTL = ((spi)->CTL & ~SPI_CTL_SUSPITV_Msk) | ((u32SuspCycle) << SPI_CTL_SUSPITV_Pos)) + +/** + * @brief Set the SPI transfer sequence with LSB first. + * @param[in] spi The pointer of the specified SPI module. + * @return None. + * @details Set LSB bit of SPI_CTL register to set the SPI transfer sequence with LSB first. + * \hideinitializer + */ +#define SPI_SET_LSB_FIRST(spi) ((spi)->CTL |= SPI_CTL_LSB_Msk) + +/** + * @brief Set the SPI transfer sequence with MSB first. + * @param[in] spi The pointer of the specified SPI module. + * @return None. + * @details Clear LSB bit of SPI_CTL register to set the SPI transfer sequence with MSB first. + * \hideinitializer + */ +#define SPI_SET_MSB_FIRST(spi) ((spi)->CTL &= ~SPI_CTL_LSB_Msk) + +/** + * @brief Set the data width of a SPI transaction. + * @param[in] spi The pointer of the specified SPI module. + * @param[in] u32Width The bit width of one transaction. + * @return None. + * @details The data width can be 8 ~ 32 bits. + * \hideinitializer + */ +#define SPI_SET_DATA_WIDTH(spi, u32Width) ((spi)->CTL = ((spi)->CTL & ~SPI_CTL_DWIDTH_Msk) | (((u32Width)&0x1F) << SPI_CTL_DWIDTH_Pos)) + +/** + * @brief Get the SPI busy state. + * @param[in] spi The pointer of the specified SPI module. + * @retval 0 SPI controller is not busy. + * @retval 1 SPI controller is busy. + * @details This macro will return the busy state of SPI controller. + * \hideinitializer + */ +#define SPI_IS_BUSY(spi) ( ((spi)->STATUS & SPI_STATUS_BUSY_Msk)>>SPI_STATUS_BUSY_Pos ) + +/** + * @brief Enable SPI controller. + * @param[in] spi The pointer of the specified SPI module. + * @return None. + * @details Set SPIEN (SPI_CTL[0]) to enable SPI controller. + * \hideinitializer + */ +#define SPI_ENABLE(spi) ((spi)->CTL |= SPI_CTL_SPIEN_Msk) + +/** + * @brief Disable SPI controller. + * @param[in] spi The pointer of the specified SPI module. + * @return None. + * @details Clear SPIEN (SPI_CTL[0]) to disable SPI controller. + * \hideinitializer + */ +#define SPI_DISABLE(spi) ((spi)->CTL &= ~SPI_CTL_SPIEN_Msk) + +/* Declare these inline functions here to avoid MISRA C 2004 rule 8.1 error */ +__STATIC_INLINE void SPII2S_ENABLE_TX_ZCD(SPI_T *i2s, uint32_t u32ChMask); +__STATIC_INLINE void SPII2S_DISABLE_TX_ZCD(SPI_T *i2s, uint32_t u32ChMask); +__STATIC_INLINE void SPII2S_SET_MONO_RX_CHANNEL(SPI_T *i2s, uint32_t u32Ch); + +/** + * @brief Enable zero cross detection function. + * @param[in] i2s The pointer of the specified I2S module. + * @param[in] u32ChMask The mask for left or right channel. Valid values are: + * - \ref SPII2S_RIGHT + * - \ref SPII2S_LEFT + * @return None + * @details This function will set RZCEN or LZCEN bit of SPI_I2SCTL register to enable zero cross detection function. + */ +__STATIC_INLINE void SPII2S_ENABLE_TX_ZCD(SPI_T *i2s, uint32_t u32ChMask) +{ + if (u32ChMask == SPII2S_RIGHT) + { + i2s->I2SCTL |= SPI_I2SCTL_RZCEN_Msk; + } + else + { + i2s->I2SCTL |= SPI_I2SCTL_LZCEN_Msk; + } +} + +/** + * @brief Disable zero cross detection function. + * @param[in] i2s The pointer of the specified I2S module. + * @param[in] u32ChMask The mask for left or right channel. Valid values are: + * - \ref SPII2S_RIGHT + * - \ref SPII2S_LEFT + * @return None + * @details This function will clear RZCEN or LZCEN bit of SPI_I2SCTL register to disable zero cross detection function. + */ +__STATIC_INLINE void SPII2S_DISABLE_TX_ZCD(SPI_T *i2s, uint32_t u32ChMask) +{ + if (u32ChMask == SPII2S_RIGHT) + { + i2s->I2SCTL &= ~SPI_I2SCTL_RZCEN_Msk; + } + else + { + i2s->I2SCTL &= ~SPI_I2SCTL_LZCEN_Msk; + } +} + +/** + * @brief Enable I2S TX DMA function. + * @param[in] i2s The pointer of the specified I2S module. + * @return None + * @details This macro will set TXPDMAEN bit of SPI_PDMACTL register to transmit data with PDMA. + * \hideinitializer + */ +#define SPII2S_ENABLE_TXDMA(i2s) ( (i2s)->PDMACTL |= SPI_PDMACTL_TXPDMAEN_Msk ) + +/** + * @brief Disable I2S TX DMA function. + * @param[in] i2s The pointer of the specified I2S module. + * @return None + * @details This macro will clear TXPDMAEN bit of SPI_PDMACTL register to disable TX DMA function. + * \hideinitializer + */ +#define SPII2S_DISABLE_TXDMA(i2s) ( (i2s)->PDMACTL &= ~SPI_PDMACTL_TXPDMAEN_Msk ) + +/** + * @brief Enable I2S RX DMA function. + * @param[in] i2s The pointer of the specified I2S module. + * @return None + * @details This macro will set RXPDMAEN bit of SPI_PDMACTL register to receive data with PDMA. + * \hideinitializer + */ +#define SPII2S_ENABLE_RXDMA(i2s) ( (i2s)->PDMACTL |= SPI_PDMACTL_RXPDMAEN_Msk ) + +/** + * @brief Disable I2S RX DMA function. + * @param[in] i2s The pointer of the specified I2S module. + * @return None + * @details This macro will clear RXPDMAEN bit of SPI_PDMACTL register to disable RX DMA function. + * \hideinitializer + */ +#define SPII2S_DISABLE_RXDMA(i2s) ( (i2s)->PDMACTL &= ~SPI_PDMACTL_RXPDMAEN_Msk ) + +/** + * @brief Enable I2S TX function. + * @param[in] i2s The pointer of the specified I2S module. + * @return None + * @details This macro will set TXEN bit of SPI_I2SCTL register to enable I2S TX function. + * \hideinitializer + */ +#define SPII2S_ENABLE_TX(i2s) ( (i2s)->I2SCTL |= SPI_I2SCTL_TXEN_Msk ) + +/** + * @brief Disable I2S TX function. + * @param[in] i2s The pointer of the specified I2S module. + * @return None + * @details This macro will clear TXEN bit of SPI_I2SCTL register to disable I2S TX function. + * \hideinitializer + */ +#define SPII2S_DISABLE_TX(i2s) ( (i2s)->I2SCTL &= ~SPI_I2SCTL_TXEN_Msk ) + +/** + * @brief Enable I2S RX function. + * @param[in] i2s The pointer of the specified I2S module. + * @return None + * @details This macro will set RXEN bit of SPI_I2SCTL register to enable I2S RX function. + * \hideinitializer + */ +#define SPII2S_ENABLE_RX(i2s) ( (i2s)->I2SCTL |= SPI_I2SCTL_RXEN_Msk ) + +/** + * @brief Disable I2S RX function. + * @param[in] i2s The pointer of the specified I2S module. + * @return None + * @details This macro will clear RXEN bit of SPI_I2SCTL register to disable I2S RX function. + * \hideinitializer + */ +#define SPII2S_DISABLE_RX(i2s) ( (i2s)->I2SCTL &= ~SPI_I2SCTL_RXEN_Msk ) + +/** + * @brief Enable TX Mute function. + * @param[in] i2s The pointer of the specified I2S module. + * @return None + * @details This macro will set MUTE bit of SPI_I2SCTL register to enable I2S TX mute function. + * \hideinitializer + */ +#define SPII2S_ENABLE_TX_MUTE(i2s) ( (i2s)->I2SCTL |= SPI_I2SCTL_MUTE_Msk ) + +/** + * @brief Disable TX Mute function. + * @param[in] i2s The pointer of the specified I2S module. + * @return None + * @details This macro will clear MUTE bit of SPI_I2SCTL register to disable I2S TX mute function. + * \hideinitializer + */ +#define SPII2S_DISABLE_TX_MUTE(i2s) ( (i2s)->I2SCTL &= ~SPI_I2SCTL_MUTE_Msk ) + +/** + * @brief Clear TX FIFO. + * @param[in] i2s The pointer of the specified I2S module. + * @return None + * @details This macro will clear TX FIFO. The internal TX FIFO pointer will be reset to FIFO start point. + * \hideinitializer + */ +#define SPII2S_CLR_TX_FIFO(i2s) ( (i2s)->FIFOCTL |= SPI_FIFOCTL_TXFBCLR_Msk ) + +/** + * @brief Clear RX FIFO. + * @param[in] i2s The pointer of the specified I2S module. + * @return None + * @details This macro will clear RX FIFO. The internal RX FIFO pointer will be reset to FIFO start point. + * \hideinitializer + */ +#define SPII2S_CLR_RX_FIFO(i2s) ( (i2s)->FIFOCTL |= SPI_FIFOCTL_RXFBCLR_Msk ) + +/** + * @brief This function sets the recording source channel when mono mode is used. + * @param[in] i2s The pointer of the specified I2S module. + * @param[in] u32Ch left or right channel. Valid values are: + * - \ref SPII2S_MONO_LEFT + * - \ref SPII2S_MONO_RIGHT + * @return None + * @details This function selects the recording source channel of monaural mode. + * \hideinitializer + */ +__STATIC_INLINE void SPII2S_SET_MONO_RX_CHANNEL(SPI_T *i2s, uint32_t u32Ch) +{ + u32Ch == SPII2S_MONO_LEFT ? + (i2s->I2SCTL |= SPI_I2SCTL_RXLCH_Msk) : + (i2s->I2SCTL &= ~SPI_I2SCTL_RXLCH_Msk); +} + +/** + * @brief Write data to I2S TX FIFO. + * @param[in] i2s The pointer of the specified I2S module. + * @param[in] u32Data The value written to TX FIFO. + * @return None + * @details This macro will write a value to TX FIFO. + * \hideinitializer + */ +#define SPII2S_WRITE_TX_FIFO(i2s, u32Data) ( (i2s)->TX = (u32Data) ) + +/** + * @brief Read RX FIFO. + * @param[in] i2s The pointer of the specified I2S module. + * @return The value read from RX FIFO. + * @details This function will return a value read from RX FIFO. + * \hideinitializer + */ +#define SPII2S_READ_RX_FIFO(i2s) ( (i2s)->RX ) + +/** + * @brief Get the interrupt flag. + * @param[in] i2s The pointer of the specified I2S module. + * @param[in] u32Mask The mask value for all interrupt flags. + * @return The interrupt flags specified by the u32mask parameter. + * @details This macro will return the combination interrupt flags of SPI_I2SSTS register. The flags are specified by the u32mask parameter. + * \hideinitializer + */ +#define SPII2S_GET_INT_FLAG(i2s, u32Mask) ( (i2s)->I2SSTS & (u32Mask) ) + +/** + * @brief Clear the interrupt flag. + * @param[in] i2s The pointer of the specified I2S module. + * @param[in] u32Mask The mask value for all interrupt flags. + * @return None + * @details This macro will clear the interrupt flags specified by the u32mask parameter. + * @note Except TX and RX FIFO threshold interrupt flags, the other interrupt flags can be cleared by writing 1 to itself. + * \hideinitializer + */ +#define SPII2S_CLR_INT_FLAG(i2s, u32Mask) ( (i2s)->I2SSTS = (u32Mask) ) + +/** + * @brief Get transmit FIFO level + * @param[in] i2s The pointer of the specified I2S module. + * @return TX FIFO level + * @details This macro will return the number of available words in TX FIFO. + * \hideinitializer + */ +#define SPII2S_GET_TX_FIFO_LEVEL(i2s) ( ((i2s)->I2SSTS & SPI_I2SSTS_TXCNT_Msk) >> SPI_I2SSTS_TXCNT_Pos ) + +/** + * @brief Get receive FIFO level + * @param[in] i2s The pointer of the specified I2S module. + * @return RX FIFO level + * @details This macro will return the number of available words in RX FIFO. + * \hideinitializer + */ +#define SPII2S_GET_RX_FIFO_LEVEL(i2s) ( ((i2s)->I2SSTS & SPI_I2SSTS_RXCNT_Msk) >> SPI_I2SSTS_RXCNT_Pos ) + +/** + * @brief Set SPI Master Receive Phase. + * @param[in] spi is the base address of SPI module. + * @param[in] rxdly is the clock cycle of delay for rx phase. + * @return none + * \hideinitializer + */ +#define SPI_SET_MRXPHASE(spi, rxdly) ( (spi)->INTERNAL = ((spi)->INTERNAL & ~SPI_INTERNAL_MRXPHASE_Msk) | (rxdly<GPA_MFPL = (SYS->GPA_MFPL & (~SYS_GPA_MFPL_PA0MFP_Msk) ) | SYS_GPA_MFPL_PA0_MFP_SC0_CLK ; + +*/ +/********************* Bit definition of GPA_MFPL register **********************/ +#define SYS_GPA_MFPL_PA0MFP_GPIO (0x00UL<RLKSUBM = 0x59UL; + SYS->RLKSUBM = 0x16UL; + SYS->RLKSUBM = 0x88UL; + } + while (SYS->RLKSUBM == 0UL); +#else + do + { + SYS->RLKTZS = 0x59UL; + SYS->RLKTZS = 0x16UL; + SYS->RLKTZS = 0x88UL; + } + while (SYS->RLKTZS == 0UL); +#endif +} + +/** + * @brief Enable register write-protection function + * @param None + * @return None + * @details This function is used to enable register write-protection function. + * To lock the protected register to forbid write access. + */ +__STATIC_INLINE void SYS_LockReg(void) +{ +#if defined(USE_MA35D1_SUBM) + SYS->RLKSUBM = 0UL; +#else + SYS->RLKTZS = 0UL; +#endif +} + +/** + * @brief Query write-protection is locked or not + * @param None + * @return true or false + * @details + */ +__STATIC_INLINE uint32_t SYS_IsRegLocked(void) +{ +#if defined(USE_MA35D1_SUBM) + return (SYS->RLKSUBM == 0) ? 1 : 0; +#else + return (SYS->RLKTZS == 0) ? 1 : 0; +#endif +} + +void SYS_ResetModule(uint32_t u32ModuleIndex); + +/*@}*/ /* end of group SYS_EXPORTED_FUNCTIONS */ + +/*@}*/ /* end of group SYS_Driver */ + +/*@}*/ /* end of group Standard_Driver */ + + +#ifdef __cplusplus +} +#endif + +#endif /* __NU_SYS_H__ */ + diff --git a/bsp/nuvoton/libraries/ma35/StdDriver/inc/nu_timer.h b/bsp/nuvoton/libraries/ma35/StdDriver/inc/nu_timer.h new file mode 100644 index 0000000000..4c3f21c1e4 --- /dev/null +++ b/bsp/nuvoton/libraries/ma35/StdDriver/inc/nu_timer.h @@ -0,0 +1,522 @@ +/**************************************************************************//** + * @file nu_timer.h + * @brief Timer Controller(Timer) driver header file + * + * SPDX-License-Identifier: Apache-2.0 + * @copyright (C) 2020 Nuvoton Technology Corp. All rights reserved. + *****************************************************************************/ +#ifndef __NU_TIMER_H__ +#define __NU_TIMER_H__ + +#ifdef __cplusplus +extern "C" +{ +#endif + + +/** @addtogroup Standard_Driver Standard Driver + @{ +*/ + +/** @addtogroup TIMER_Driver TIMER Driver + @{ +*/ + +/** @addtogroup TIMER_EXPORTED_CONSTANTS TIMER Exported Constants + @{ +*/ +/*---------------------------------------------------------------------------------------------------------*/ +/* TIMER Operation Mode, External Counter and Capture Mode Constant Definitions */ +/*---------------------------------------------------------------------------------------------------------*/ +#define TIMER_ONESHOT_MODE (0UL << TIMER_CTL_OPMODE_Pos) /*!< Timer working in one-shot mode \hideinitializer */ +#define TIMER_PERIODIC_MODE (1UL << TIMER_CTL_OPMODE_Pos) /*!< Timer working in periodic mode \hideinitializer */ +#define TIMER_TOGGLE_MODE (2UL << TIMER_CTL_OPMODE_Pos) /*!< Timer working in toggle-output mode \hideinitializer */ +#define TIMER_CONTINUOUS_MODE (3UL << TIMER_CTL_OPMODE_Pos) /*!< Timer working in continuous counting mode \hideinitializer */ +#define TIMER_TOUT_PIN_FROM_TMX (0UL << TIMER_CTL_TGLPINSEL_Pos) /*!< Timer toggle-output pin is from TMx pin \hideinitializer */ +#define TIMER_TOUT_PIN_FROM_TMX_EXT (1UL << TIMER_CTL_TGLPINSEL_Pos) /*!< Timer toggle-output pin is from TMx_EXT pin \hideinitializer */ + +#define TIMER_COUNTER_EVENT_FALLING (0UL << TIMER_EXTCTL_CNTPHASE_Pos) /*!< Counter increase on falling edge detection \hideinitializer */ +#define TIMER_COUNTER_EVENT_RISING (1UL << TIMER_EXTCTL_CNTPHASE_Pos) /*!< Counter increase on rising edge detection \hideinitializer */ +#define TIMER_CAPTURE_FREE_COUNTING_MODE (0UL << TIMER_EXTCTL_CAPFUNCS_Pos) /*!< Timer capture event to get timer counter value \hideinitializer */ +#define TIMER_CAPTURE_COUNTER_RESET_MODE (1UL << TIMER_EXTCTL_CAPFUNCS_Pos) /*!< Timer capture event to reset timer counter \hideinitializer */ + +#define TIMER_CAPTURE_EVENT_FALLING (0UL << TIMER_EXTCTL_CAPEDGE_Pos) /*!< Falling edge detection to trigger capture event \hideinitializer */ +#define TIMER_CAPTURE_EVENT_RISING (1UL << TIMER_EXTCTL_CAPEDGE_Pos) /*!< Rising edge detection to trigger capture event \hideinitializer */ +#define TIMER_CAPTURE_EVENT_FALLING_RISING (2UL << TIMER_EXTCTL_CAPEDGE_Pos) /*!< Both falling and rising edge detection to trigger capture event, and first event at falling edge \hideinitializer */ +#define TIMER_CAPTURE_EVENT_RISING_FALLING (3UL << TIMER_EXTCTL_CAPEDGE_Pos) /*!< Both rising and falling edge detection to trigger capture event, and first event at rising edge \hideinitializer */ +#define TIMER_CAPTURE_EVENT_GET_LOW_PERIOD (6UL << TIMER_EXTCTL_CAPEDGE_Pos) /*!< First capture event is at falling edge, follows are at at rising edge \hideinitializer */ +#define TIMER_CAPTURE_EVENT_GET_HIGH_PERIOD (7UL << TIMER_EXTCTL_CAPEDGE_Pos) /*!< First capture event is at rising edge, follows are at at falling edge \hideinitializer */ + +#define TIMER_TRGSRC_TIMEOUT_EVENT (0UL << TIMER_TRGCTL_TRGSSEL_Pos) /*!< Select internal trigger source from timer time-out event \hideinitializer */ +#define TIMER_TRGSRC_CAPTURE_EVENT (1UL << TIMER_TRGCTL_TRGSSEL_Pos) /*!< Select internal trigger source from timer capture event \hideinitializer */ +#define TIMER_TRG_TO_EPWM (TIMER_TRGCTL_TRGEPWM_Msk) /*!< Each timer event as EPWM counter clock source \hideinitializer */ +#define TIMER_TRG_TO_EADC (TIMER_TRGCTL_TRGEADC_Msk) /*!< Each timer event to start ADC conversion \hideinitializer */ +#define TIMER_TRG_TO_DAC (TIMER_TRGCTL_TRGDAC_Msk) /*!< Each timer event to start DAC conversion \hideinitializer */ +#define TIMER_TRG_TO_PDMA (TIMER_TRGCTL_TRGPDMA_Msk) /*!< Each timer event to trigger PDMA transfer \hideinitializer */ + +/*@}*/ /* end of group TIMER_EXPORTED_CONSTANTS */ + + +/** @addtogroup TIMER_EXPORTED_FUNCTIONS TIMER Exported Functions + @{ +*/ + +/** + * @brief Set Timer Compared Value + * + * @param[in] timer The pointer of the specified Timer module. It could be TIMER0, TIMER1, TIMER2, TIMER3. + * @param[in] u32Value Timer compare value. Valid values are between 2 to 0xFFFFFF. + * + * @return None + * + * @details This macro is used to set timer compared value to adjust timer time-out interval. + * @note 1. Never write 0x0 or 0x1 in this field, or the core will run into unknown state. \n + * 2. If update timer compared value in continuous counting mode, timer counter value will keep counting continuously. \n + * But if timer is operating at other modes, the timer up counter will restart counting and start from 0. + * \hideinitializer + */ +#define TIMER_SET_CMP_VALUE(timer, u32Value) ((timer)->CMP = (u32Value)) + +/** + * @brief Set Timer Prescale Value + * + * @param[in] timer The pointer of the specified Timer module. It could be TIMER0, TIMER1, TIMER2, TIMER3. + * @param[in] u32Value Timer prescale value. Valid values are between 0 to 0xFF. + * + * @return None + * + * @details This macro is used to set timer prescale value and timer source clock will be divided by (prescale + 1) \n + * before it is fed into timer. + * \hideinitializer + */ +#define TIMER_SET_PRESCALE_VALUE(timer, u32Value) ((timer)->CTL = ((timer)->CTL & ~TIMER_CTL_PSC_Msk) | (u32Value)) + +/** + * @brief Check specify Timer Status + * + * @param[in] timer The pointer of the specified Timer module. It could be TIMER0, TIMER1, TIMER2, TIMER3. + * + * @retval 0 Timer 24-bit up counter is inactive + * @retval 1 Timer 24-bit up counter is active + * + * @details This macro is used to check if specify Timer counter is inactive or active. + * \hideinitializer + */ +#define TIMER_IS_ACTIVE(timer) (((timer)->CTL & TIMER_CTL_ACTSTS_Msk)? 1 : 0) + +/** + * @brief Select Toggle-output Pin + * + * @param[in] timer The pointer of the specified Timer module. It could be TIMER0, TIMER1, TIMER2, TIMER3. + * @param[in] u32ToutSel Toggle-output pin selection, valid values are: + * - \ref TIMER_TOUT_PIN_FROM_TMX + * - \ref TIMER_TOUT_PIN_FROM_TMX_EXT + * + * @return None + * + * @details This macro is used to select timer toggle-output pin is output on TMx or TMx_EXT pin. + * \hideinitializer + */ +#define TIMER_SELECT_TOUT_PIN(timer, u32ToutSel) ((timer)->CTL = ((timer)->CTL & ~TIMER_CTL_TGLPINSEL_Msk) | (u32ToutSel)) + +/** + * @brief Select Timer operating mode + * + * @param[in] timer The pointer of the specified Timer module. It could be TIMER0, TIMER1, TIMER2, TIMER3. + * @param[in] u32OpMode Operation mode. Possible options are + * - \ref TIMER_ONESHOT_MODE + * - \ref TIMER_PERIODIC_MODE + * - \ref TIMER_TOGGLE_MODE + * - \ref TIMER_CONTINUOUS_MODE + * + * @return None + * \hideinitializer + */ +#define TIMER_SET_OPMODE(timer, u32OpMode) ((timer)->CTL = ((timer)->CTL & ~TIMER_CTL_OPMODE_Msk) | (u32OpMode)) + +/* Declare these inline functions here to avoid MISRA C 2004 rule 8.1 error */ +__STATIC_INLINE void TIMER_Start(TIMER_T *timer); +__STATIC_INLINE void TIMER_Stop(TIMER_T *timer); +__STATIC_INLINE void TIMER_EnableWakeup(TIMER_T *timer); +__STATIC_INLINE void TIMER_DisableWakeup(TIMER_T *timer); +__STATIC_INLINE void TIMER_StartCapture(TIMER_T *timer); +__STATIC_INLINE void TIMER_StopCapture(TIMER_T *timer); +__STATIC_INLINE void TIMER_EnableCaptureDebounce(TIMER_T *timer); +__STATIC_INLINE void TIMER_DisableCaptureDebounce(TIMER_T *timer); +__STATIC_INLINE void TIMER_EnableEventCounterDebounce(TIMER_T *timer); +__STATIC_INLINE void TIMER_DisableEventCounterDebounce(TIMER_T *timer); +__STATIC_INLINE void TIMER_EnableInt(TIMER_T *timer); +__STATIC_INLINE void TIMER_DisableInt(TIMER_T *timer); +__STATIC_INLINE void TIMER_EnableCaptureInt(TIMER_T *timer); +__STATIC_INLINE void TIMER_DisableCaptureInt(TIMER_T *timer); +__STATIC_INLINE uint32_t TIMER_GetIntFlag(TIMER_T *timer); +__STATIC_INLINE void TIMER_ClearIntFlag(TIMER_T *timer); +__STATIC_INLINE uint32_t TIMER_GetCaptureIntFlag(TIMER_T *timer); +__STATIC_INLINE void TIMER_ClearCaptureIntFlag(TIMER_T *timer); +__STATIC_INLINE uint32_t TIMER_GetWakeupFlag(TIMER_T *timer); +__STATIC_INLINE void TIMER_ClearWakeupFlag(TIMER_T *timer); +__STATIC_INLINE uint32_t TIMER_GetCaptureData(TIMER_T *timer); +__STATIC_INLINE uint32_t TIMER_GetCounter(TIMER_T *timer); +__STATIC_INLINE void TIMER_ResetCounter(TIMER_T *timer); + +/** + * @brief Start Timer Counting + * + * @param[in] timer The pointer of the specified Timer module. It could be TIMER0, TIMER1, TIMER2, TIMER3. + * + * @return None + * + * @details This function is used to start Timer counting. + */ +__STATIC_INLINE void TIMER_Start(TIMER_T *timer) +{ + timer->CTL |= TIMER_CTL_CNTEN_Msk; +} + +/** + * @brief Stop Timer Counting + * + * @param[in] timer The pointer of the specified Timer module. It could be TIMER0, TIMER1, TIMER2, TIMER3. + * + * @return None + * + * @details This function is used to stop/suspend Timer counting. + */ +__STATIC_INLINE void TIMER_Stop(TIMER_T *timer) +{ + timer->CTL &= ~TIMER_CTL_CNTEN_Msk; +} + +/** + * @brief Enable Timer Interrupt Wake-up Function + * + * @param[in] timer The pointer of the specified Timer module. It could be TIMER0, TIMER1, TIMER2, TIMER3. + * + * @return None + * + * @details This function is used to enable the timer interrupt wake-up function and interrupt source could be time-out interrupt, \n + * counter event interrupt or capture trigger interrupt. + * @note To wake the system from Power-down mode, timer clock source must be ether LXT or LIRC. + */ +__STATIC_INLINE void TIMER_EnableWakeup(TIMER_T *timer) +{ + timer->CTL |= TIMER_CTL_WKEN_Msk; +} + +/** + * @brief Disable Timer Wake-up Function + * + * @param[in] timer The pointer of the specified Timer module. It could be TIMER0, TIMER1, TIMER2, TIMER3. + * + * @return None + * + * @details This function is used to disable the timer interrupt wake-up function. + */ +__STATIC_INLINE void TIMER_DisableWakeup(TIMER_T *timer) +{ + timer->CTL &= ~TIMER_CTL_WKEN_Msk; +} + +/** + * @brief Start Timer Capture Function + * + * @param[in] timer The pointer of the specified Timer module. It could be TIMER0, TIMER1, TIMER2, TIMER3. + * + * @return None + * + * @details This function is used to start Timer capture function. + */ +__STATIC_INLINE void TIMER_StartCapture(TIMER_T *timer) +{ + timer->EXTCTL |= TIMER_EXTCTL_CAPEN_Msk; +} + +/** + * @brief Stop Timer Capture Function + * + * @param[in] timer The pointer of the specified Timer module. It could be TIMER0, TIMER1, TIMER2, TIMER3. + * + * @return None + * + * @details This function is used to stop Timer capture function. + */ +__STATIC_INLINE void TIMER_StopCapture(TIMER_T *timer) +{ + timer->EXTCTL &= ~TIMER_EXTCTL_CAPEN_Msk; +} + +/** + * @brief Enable Capture Pin De-bounce + * + * @param[in] timer The pointer of the specified Timer module. It could be TIMER0, TIMER1, TIMER2, TIMER3. + * + * @return None + * + * @details This function is used to enable the detect de-bounce function of capture pin. + */ +__STATIC_INLINE void TIMER_EnableCaptureDebounce(TIMER_T *timer) +{ + timer->EXTCTL |= TIMER_EXTCTL_CAPDBEN_Msk; +} + +/** + * @brief Disable Capture Pin De-bounce + * + * @param[in] timer The pointer of the specified Timer module. It could be TIMER0, TIMER1, TIMER2, TIMER3. + * + * @return None + * + * @details This function is used to disable the detect de-bounce function of capture pin. + */ +__STATIC_INLINE void TIMER_DisableCaptureDebounce(TIMER_T *timer) +{ + timer->EXTCTL &= ~TIMER_EXTCTL_CAPDBEN_Msk; +} + +/** + * @brief Enable Counter Pin De-bounce + * + * @param[in] timer The pointer of the specified Timer module. It could be TIMER0, TIMER1, TIMER2, TIMER3. + * + * @return None + * + * @details This function is used to enable the detect de-bounce function of counter pin. + */ +__STATIC_INLINE void TIMER_EnableEventCounterDebounce(TIMER_T *timer) +{ + timer->EXTCTL |= TIMER_EXTCTL_CNTDBEN_Msk; +} + +/** + * @brief Disable Counter Pin De-bounce + * + * @param[in] timer The pointer of the specified Timer module. It could be TIMER0, TIMER1, TIMER2, TIMER3. + * + * @return None + * + * @details This function is used to disable the detect de-bounce function of counter pin. + */ +__STATIC_INLINE void TIMER_DisableEventCounterDebounce(TIMER_T *timer) +{ + timer->EXTCTL &= ~TIMER_EXTCTL_CNTDBEN_Msk; +} + +/** + * @brief Enable Timer Time-out Interrupt + * + * @param[in] timer The pointer of the specified Timer module. It could be TIMER0, TIMER1, TIMER2, TIMER3. + * + * @return None + * + * @details This function is used to enable the timer time-out interrupt function. + */ +__STATIC_INLINE void TIMER_EnableInt(TIMER_T *timer) +{ + timer->CTL |= TIMER_CTL_INTEN_Msk; +} + +/** + * @brief Disable Timer Time-out Interrupt + * + * @param[in] timer The pointer of the specified Timer module. It could be TIMER0, TIMER1, TIMER2, TIMER3. + * + * @return None + * + * @details This function is used to disable the timer time-out interrupt function. + */ +__STATIC_INLINE void TIMER_DisableInt(TIMER_T *timer) +{ + timer->CTL &= ~TIMER_CTL_INTEN_Msk; +} + +/** + * @brief Enable Capture Trigger Interrupt + * + * @param[in] timer The pointer of the specified Timer module. It could be TIMER0, TIMER1, TIMER2, TIMER3. + * + * @return None + * + * @details This function is used to enable the timer capture trigger interrupt function. + */ +__STATIC_INLINE void TIMER_EnableCaptureInt(TIMER_T *timer) +{ + timer->EXTCTL |= TIMER_EXTCTL_CAPIEN_Msk; +} + +/** + * @brief Disable Capture Trigger Interrupt + * + * @param[in] timer The pointer of the specified Timer module. It could be TIMER0, TIMER1, TIMER2, TIMER3. + * + * @return None + * + * @details This function is used to disable the timer capture trigger interrupt function. + */ +__STATIC_INLINE void TIMER_DisableCaptureInt(TIMER_T *timer) +{ + timer->EXTCTL &= ~TIMER_EXTCTL_CAPIEN_Msk; +} + +/** + * @brief Get Timer Time-out Interrupt Flag + * + * @param[in] timer The pointer of the specified Timer module. It could be TIMER0, TIMER1, TIMER2, TIMER3. + * + * @retval 0 Timer time-out interrupt did not occur + * @retval 1 Timer time-out interrupt occurred + * + * @details This function indicates timer time-out interrupt occurred or not. + */ +__STATIC_INLINE uint32_t TIMER_GetIntFlag(TIMER_T *timer) +{ + return ((timer->INTSTS & TIMER_INTSTS_TIF_Msk) ? 1UL : 0UL); +} + +/** + * @brief Clear Timer Time-out Interrupt Flag + * + * @param[in] timer The pointer of the specified Timer module. It could be TIMER0, TIMER1, TIMER2, TIMER3. + * + * @return None + * + * @details This function clears timer time-out interrupt flag to 0. + */ +__STATIC_INLINE void TIMER_ClearIntFlag(TIMER_T *timer) +{ + timer->INTSTS = TIMER_INTSTS_TIF_Msk; +} + +/** + * @brief Get Timer Capture Interrupt Flag + * + * @param[in] timer The pointer of the specified Timer module. It could be TIMER0, TIMER1, TIMER2, TIMER3. + * + * @retval 0 Timer capture interrupt did not occur + * @retval 1 Timer capture interrupt occurred + * + * @details This function indicates timer capture trigger interrupt occurred or not. + */ +__STATIC_INLINE uint32_t TIMER_GetCaptureIntFlag(TIMER_T *timer) +{ + return timer->EINTSTS; +} + +/** + * @brief Clear Timer Capture Interrupt Flag + * + * @param[in] timer The pointer of the specified Timer module. It could be TIMER0, TIMER1, TIMER2, TIMER3. + * + * @return None + * + * @details This function clears timer capture trigger interrupt flag to 0. + */ +__STATIC_INLINE void TIMER_ClearCaptureIntFlag(TIMER_T *timer) +{ + timer->EINTSTS = TIMER_EINTSTS_CAPIF_Msk; +} + +/** + * @brief Get Timer Wake-up Flag + * + * @param[in] timer The pointer of the specified Timer module. It could be TIMER0, TIMER1, TIMER2, TIMER3. + * + * @retval 0 Timer does not cause CPU wake-up + * @retval 1 Timer interrupt event cause CPU wake-up + * + * @details This function indicates timer interrupt event has waked up system or not. + */ +__STATIC_INLINE uint32_t TIMER_GetWakeupFlag(TIMER_T *timer) +{ + return (timer->INTSTS & TIMER_INTSTS_TWKF_Msk ? 1UL : 0UL); +} + +/** + * @brief Clear Timer Wake-up Flag + * + * @param[in] timer The pointer of the specified Timer module. It could be TIMER0, TIMER1, TIMER2, TIMER3. + * + * @return None + * + * @details This function clears the timer wake-up system flag to 0. + */ +__STATIC_INLINE void TIMER_ClearWakeupFlag(TIMER_T *timer) +{ + timer->INTSTS = TIMER_INTSTS_TWKF_Msk; +} + +/** + * @brief Get Capture value + * + * @param[in] timer The pointer of the specified Timer module. It could be TIMER0, TIMER1, TIMER2, TIMER3. + * + * @return 24-bit Capture Value + * + * @details This function reports the current 24-bit timer capture value. + */ +__STATIC_INLINE uint32_t TIMER_GetCaptureData(TIMER_T *timer) +{ + return timer->CAP; +} + +/** + * @brief Get Counter value + * + * @param[in] timer The pointer of the specified Timer module. It could be TIMER0, TIMER1, TIMER2, TIMER3. + * + * @return 24-bit Counter Value + * + * @details This function reports the current 24-bit timer counter value. + */ +__STATIC_INLINE uint32_t TIMER_GetCounter(TIMER_T *timer) +{ + return timer->CNT; +} + +/** + * @brief Reset Counter + * + * @param[in] timer The pointer of the specified Timer module. It could be TIMER0, TIMER1, TIMER2, TIMER3. + * + * @return None + * + * @details This function is used to reset current counter value and internal prescale counter value. + */ +__STATIC_INLINE void TIMER_ResetCounter(TIMER_T *timer) +{ + timer->CNT = 0UL; + while ((timer->CNT & TIMER_CNT_RSTACT_Msk) == TIMER_CNT_RSTACT_Msk) + { + ; + } +} + + +uint32_t TIMER_Open(TIMER_T *timer, uint32_t u32Mode, uint32_t u32Freq); +void TIMER_Close(TIMER_T *timer); +void TIMER_Delay(TIMER_T *timer, uint32_t u32Usec); +void TIMER_EnableCapture(TIMER_T *timer, uint32_t u32CapMode, uint32_t u32Edge); +void TIMER_DisableCapture(TIMER_T *timer); +void TIMER_EnableEventCounter(TIMER_T *timer, uint32_t u32Edge); +void TIMER_DisableEventCounter(TIMER_T *timer); +uint32_t TIMER_GetModuleClock(TIMER_T *timer); +void TIMER_EnableFreqCounter(TIMER_T *timer, + uint32_t u32DropCount, + uint32_t u32Timeout, + uint32_t u32EnableInt); +void TIMER_DisableFreqCounter(TIMER_T *timer); +void TIMER_SetTriggerSource(TIMER_T *timer, uint32_t u32Src); +void TIMER_SetTriggerTarget(TIMER_T *timer, uint32_t u32Mask); + +/*@}*/ /* end of group TIMER_EXPORTED_FUNCTIONS */ + +/*@}*/ /* end of group TIMER_Driver */ + +/*@}*/ /* end of group Standard_Driver */ + +#ifdef __cplusplus +} +#endif + +#endif /* __NU_TIMER_H__ */ + + diff --git a/bsp/nuvoton/libraries/ma35/StdDriver/inc/nu_timer_pwm.h b/bsp/nuvoton/libraries/ma35/StdDriver/inc/nu_timer_pwm.h new file mode 100644 index 0000000000..05291bc2cc --- /dev/null +++ b/bsp/nuvoton/libraries/ma35/StdDriver/inc/nu_timer_pwm.h @@ -0,0 +1,745 @@ +/**************************************************************************//** + * @file nu_timer_pwm.h + * @brief Timer PWM Controller(Timer PWM) driver header file + * + * SPDX-License-Identifier: Apache-2.0 + * @copyright (C) 2020 Nuvoton Technology Corp. All rights reserved. + *****************************************************************************/ +#ifndef __NU_TIMER_PWM_H__ +#define __NU_TIMER_PWM_H__ + +#ifdef __cplusplus +extern "C" +{ +#endif + + + +/** @addtogroup Standard_Driver Standard Driver + @{ +*/ +/** @addtogroup TIMER_PWM_Driver TIMER PWM Driver + @{ +*/ + +/** @addtogroup TIMER_PWM_EXPORTED_CONSTANTS TIMER PWM Exported Constants + @{ +*/ +/*---------------------------------------------------------------------------------------------------------*/ +/* Output Channel Constant Definitions */ +/*---------------------------------------------------------------------------------------------------------*/ +#define TPWM_CH0 (BIT0) /*!< Indicate PWMx_CH0 \hideinitializer */ +#define TPWM_CH1 (BIT1) /*!< Indicate PWMx_CH1 \hideinitializer */ + +/*---------------------------------------------------------------------------------------------------------*/ +/* Counter Type Constant Definitions */ +/*---------------------------------------------------------------------------------------------------------*/ +#define TPWM_UP_COUNT (0UL << TIMER_PWMCTL_CNTTYPE_Pos) /*!< Up count type \hideinitializer */ +#define TPWM_DOWN_COUNT (1UL << TIMER_PWMCTL_CNTTYPE_Pos) /*!< Down count type \hideinitializer */ +#define TPWM_UP_DOWN_COUNT (2UL << TIMER_PWMCTL_CNTTYPE_Pos) /*!< Up-Down count type \hideinitializer */ + +/*---------------------------------------------------------------------------------------------------------*/ +/* Counter Mode Constant Definitions */ +/*---------------------------------------------------------------------------------------------------------*/ +#define TPWM_AUTO_RELOAD_MODE (0UL) /*!< Auto-reload mode \hideinitializer */ +#define TPWM_ONE_SHOT_MODE (TIMER_PWMCTL_CNTMODE_Msk) /*!< One-shot mode \hideinitializer */ + +/*---------------------------------------------------------------------------------------------------------*/ +/* Output Level Constant Definitions */ +/*---------------------------------------------------------------------------------------------------------*/ +#define TPWM_OUTPUT_TOGGLE (0UL) /*!< Timer PWM output toggle \hideinitializer */ +#define TPWM_OUTPUT_NOTHING (1UL) /*!< Timer PWM output nothing \hideinitializer */ +#define TPWM_OUTPUT_LOW (2UL) /*!< Timer PWM output low \hideinitializer */ +#define TPWM_OUTPUT_HIGH (3UL) /*!< Timer PWM output high \hideinitializer */ + +/*---------------------------------------------------------------------------------------------------------*/ +/* Trigger ADC Source Select Constant Definitions */ +/*---------------------------------------------------------------------------------------------------------*/ +#define TPWM_TRIGGER_ADC_AT_ZERO_POINT (0UL << TIMER_PWMEADCTS_TRGSEL_Pos) /*!< Timer PWM trigger ADC while counter zero point event occurred \hideinitializer */ +#define TPWM_TRIGGER_ADC_AT_PERIOD_POINT (1UL << TIMER_PWMEADCTS_TRGSEL_Pos) /*!< Timer PWM trigger ADC while counter period point event occurred \hideinitializer */ +#define TPWM_TRIGGER_ADC_AT_ZERO_OR_PERIOD_POINT (2UL << TIMER_PWMEADCTS_TRGSEL_Pos) /*!< Timer PWM trigger ADC while counter zero or period point event occurred \hideinitializer */ +#define TPWM_TRIGGER_ADC_AT_COMPARE_UP_COUNT_POINT (3UL << TIMER_PWMEADCTS_TRGSEL_Pos) /*!< Timer PWM trigger ADC while counter up count compare point event occurred \hideinitializer */ +#define TPWM_TRIGGER_ADC_AT_COMPARE_DOWN_COUNT_POINT (4UL << TIMER_PWMEADCTS_TRGSEL_Pos) /*!< Timer PWM trigger ADC while counter down count compare point event occurred \hideinitializer */ + +/*---------------------------------------------------------------------------------------------------------*/ +/* Brake Control Constant Definitions */ +/*---------------------------------------------------------------------------------------------------------*/ +#define TPWM_BRAKE_SOURCE_EDGE_ACMP0 (TIMER_PWMBRKCTL_CPO0EBEN_Msk) /*!< Comparator 0 as edge-detect fault brake source \hideinitializer */ +#define TPWM_BRAKE_SOURCE_EDGE_ACMP1 (TIMER_PWMBRKCTL_CPO1EBEN_Msk) /*!< Comparator 1 as edge-detect fault brake source \hideinitializer */ +#define TPWM_BRAKE_SOURCE_EDGE_BKPIN (TIMER_PWMBRKCTL_BRKPEEN_Msk) /*!< Brake pin as edge-detect fault brake source \hideinitializer */ +#define TPWM_BRAKE_SOURCE_EDGE_SYS_CSS (TIMER_PWMBRKCTL_SYSEBEN_Msk | (TIMER_PWMFAILBRK_CSSBRKEN_Msk << 16)) /*!< System fail condition: clock security system detection as edge-detect fault brake source \hideinitializer */ +#define TPWM_BRAKE_SOURCE_EDGE_SYS_BOD (TIMER_PWMBRKCTL_SYSEBEN_Msk | (TIMER_PWMFAILBRK_BODBRKEN_Msk << 16)) /*!< System fail condition: brown-out detection as edge-detect fault brake source \hideinitializer */ +#define TPWM_BRAKE_SOURCE_EDGE_SYS_COR (TIMER_PWMBRKCTL_SYSEBEN_Msk | (TIMER_PWMFAILBRK_CORBRKEN_Msk << 16)) /*!< System fail condition: core lockup detection as edge-detect fault brake source \hideinitializer */ +#define TPWM_BRAKE_SOURCE_EDGE_SYS_RAM (TIMER_PWMBRKCTL_SYSEBEN_Msk | (TIMER_PWMFAILBRK_RAMBRKEN_Msk << 16)) /*!< System fail condition: SRAM parity error detection as edge-detect fault brake source \hideinitializer */ + + +#define TPWM_BRAKE_SOURCE_LEVEL_ACMP0 (TIMER_PWMBRKCTL_CPO0LBEN_Msk) /*!< Comparator 0 as level-detect fault brake source \hideinitializer */ +#define TPWM_BRAKE_SOURCE_LEVEL_ACMP1 (TIMER_PWMBRKCTL_CPO1LBEN_Msk) /*!< Comparator 1 as level-detect fault brake source \hideinitializer */ +#define TPWM_BRAKE_SOURCE_LEVEL_BKPIN (TIMER_PWMBRKCTL_BRKPLEN_Msk) /*!< Brake pin as level-detect fault brake source \hideinitializer */ +#define TPWM_BRAKE_SOURCE_LEVEL_SYS_CSS (TIMER_PWMBRKCTL_SYSLBEN_Msk | (TIMER_PWMFAILBRK_CSSBRKEN_Msk << 16)) /*!< System fail condition: clock security system detection as level-detect fault brake source \hideinitializer */ +#define TPWM_BRAKE_SOURCE_LEVEL_SYS_BOD (TIMER_PWMBRKCTL_SYSLBEN_Msk | (TIMER_PWMFAILBRK_BODBRKEN_Msk << 16)) /*!< System fail condition: brown-out detection as level-detect fault brake source \hideinitializer */ +#define TPWM_BRAKE_SOURCE_LEVEL_SYS_COR (TIMER_PWMBRKCTL_SYSLBEN_Msk | (TIMER_PWMFAILBRK_CORBRKEN_Msk << 16)) /*!< System fail condition: core lockup detection as level-detect fault brake source \hideinitializer */ +#define TPWM_BRAKE_SOURCE_LEVEL_SYS_RAM (TIMER_PWMBRKCTL_SYSLBEN_Msk | (TIMER_PWMFAILBRK_RAMBRKEN_Msk << 16)) /*!< System fail condition: SRAM parity error detection as level-detect fault brake source \hideinitializer */ + +#define TPWM_BRAKE_EDGE (TIMER_PWMSWBRK_BRKETRG_Msk) /*!< Edge-detect fault brake \hideinitializer */ +#define TPWM_BRAKE_LEVEL (TIMER_PWMSWBRK_BRKLTRG_Msk) /*!< Level-detect fault brake \hideinitializer */ + +/*---------------------------------------------------------------------------------------------------------*/ +/* Load Mode Constant Definitions */ +/*---------------------------------------------------------------------------------------------------------*/ +#define TPWM_LOAD_MODE_PERIOD (0UL) /*!< Timer PWM period load mode \hideinitializer */ +#define TPWM_LOAD_MODE_IMMEDIATE (TIMER_PWMCTL_IMMLDEN_Msk) /*!< Timer PWM immediately load mode \hideinitializer */ +#define TPWM_LOAD_MODE_CENTER (TIMER_PWMCTL_CTRLD_Msk) /*!< Timer PWM center load mode \hideinitializer */ + +/*---------------------------------------------------------------------------------------------------------*/ +/* Brake Pin De-bounce Clock Source Select Constant Definitions */ +/*---------------------------------------------------------------------------------------------------------*/ +#define TPWM_BKP_DBCLK_PCLK_DIV_1 (0UL) /*!< De-bounce clock is PCLK divide by 1 \hideinitializer */ +#define TPWM_BKP_DBCLK_PCLK_DIV_2 (1UL) /*!< De-bounce clock is PCLK divide by 2 \hideinitializer */ +#define TPWM_BKP_DBCLK_PCLK_DIV_4 (2UL) /*!< De-bounce clock is PCLK divide by 4 \hideinitializer */ +#define TPWM_BKP_DBCLK_PCLK_DIV_8 (3UL) /*!< De-bounce clock is PCLK divide by 8 \hideinitializer */ +#define TPWM_BKP_DBCLK_PCLK_DIV_16 (4UL) /*!< De-bounce clock is PCLK divide by 16 \hideinitializer */ +#define TPWM_BKP_DBCLK_PCLK_DIV_32 (5UL) /*!< De-bounce clock is PCLK divide by 32 \hideinitializer */ +#define TPWM_BKP_DBCLK_PCLK_DIV_64 (6UL) /*!< De-bounce clock is PCLK divide by 64 \hideinitializer */ +#define TPWM_BKP_DBCLK_PCLK_DIV_128 (7UL) /*!< De-bounce clock is PCLK divide by 128 \hideinitializer */ + +/*---------------------------------------------------------------------------------------------------------*/ +/* Brake Pin Source Select Constant Definitions */ +/*---------------------------------------------------------------------------------------------------------*/ +#define TPWM_TM_BRAKE0 (0UL) /*!< Brake pin source comes from TM_BRAKE0 \hideinitializer */ +#define TPWM_TM_BRAKE1 (1UL) /*!< Brake pin source comes from TM_BRAKE1 \hideinitializer */ +#define TPWM_TM_BRAKE2 (2UL) /*!< Brake pin source comes from TM_BRAKE2 \hideinitializer */ +#define TPWM_TM_BRAKE3 (3UL) /*!< Brake pin source comes from TM_BRAKE3 \hideinitializer */ + +/*---------------------------------------------------------------------------------------------------------*/ +/* Counter Clock Source Select Constant Definitions */ +/*---------------------------------------------------------------------------------------------------------*/ +#define TPWM_CNTR_CLKSRC_TMR_CLK (0UL) /*!< Timer PWM Clock source selects to TMR_CLK \hideinitializer */ +#define TPWM_CNTR_CLKSRC_TIMER0_INT (1UL) /*!< Timer PWM Clock source selects to TIMER0 interrupt event \hideinitializer */ +#define TPWM_CNTR_CLKSRC_TIMER1_INT (2UL) /*!< Timer PWM Clock source selects to TIMER1 interrupt event \hideinitializer */ +#define TPWM_CNTR_CLKSRC_TIMER2_INT (3UL) /*!< Timer PWM Clock source selects to TIMER2 interrupt event \hideinitializer */ +#define TPWM_CNTR_CLKSRC_TIMER3_INT (4UL) /*!< Timer PWM Clock source selects to TIMER3 interrupt event \hideinitializer */ + +/*---------------------------------------------------------------------------------------------------------*/ +/* Counter Synchronous Mode Constant Definitions */ +/*---------------------------------------------------------------------------------------------------------*/ +#define TPWM_CNTR_SYNC_DISABLE (0UL) /*!< Disable TIMER PWM synchronous function \hideinitializer */ +#define TPWM_CNTR_SYNC_START_BY_TIMER0 ((0<ALTCTL = (1 << TIMER_ALTCTL_FUNCSEL_Pos)) + +/** + * @brief Disable PWM Counter Mode + * + * @param[in] timer The pointer of the specified Timer module. It could be TIMER0, TIMER1, TIMER2, TIMER3. + * + * @return None + * + * @details This macro is used to disable specified Timer channel as PWM counter mode, then timer counter mode is available. + * @note All registers about PWM counter function will be cleared to 0 after executing this macro. + * \hideinitializer + */ +#define TPWM_DISABLE_PWM_MODE(timer) ((timer)->ALTCTL = (0 << TIMER_ALTCTL_FUNCSEL_Pos)) + +/** + * @brief Enable Independent Mode + * + * @param[in] timer The pointer of the specified Timer module. It could be TIMER0, TIMER1, TIMER2, TIMER3. + * + * @return None + * + * @details This macro is used to enable independent mode of TIMER PWM module and complementary mode will be disabled. + * \hideinitializer + */ +#define TPWM_ENABLE_INDEPENDENT_MODE(timer) ((timer)->PWMCTL &= ~(1 << TIMER_PWMCTL_OUTMODE_Pos)) + +/** + * @brief Enable Complementary Mode + * + * @param[in] timer The pointer of the specified Timer module. It could be TIMER0, TIMER1, TIMER2, TIMER3. + * + * @return None + * + * @details This macro is used to enable complementary mode of Timer PWM module and independent mode will be disabled. + * \hideinitializer + */ +#define TPWM_ENABLE_COMPLEMENTARY_MODE(timer) ((timer)->PWMCTL |= (1 << TIMER_PWMCTL_OUTMODE_Pos)) + +/** + * @brief Set Counter Type + * + * @param[in] timer The pointer of the specified Timer module. It could be TIMER0, TIMER1, TIMER2, TIMER3. + * @param[in] type Timer PWM count type, could be one of the following type + * - \ref TPWM_UP_COUNT + * - \ref TPWM_DOWN_COUNT + * - \ref TPWM_UP_DOWN_COUNT + * + * @return None + * + * @details This macro is used to set Timer PWM counter type. + * \hideinitializer + */ +#define TPWM_SET_COUNTER_TYPE(timer, type) ((timer)->PWMCTL = ((timer)->PWMCTL & ~TIMER_PWMCTL_CNTTYPE_Msk) | (type)) + +/** + * @brief Start PWM Counter + * + * @param[in] timer The pointer of the specified Timer module. It could be TIMER0, TIMER1, TIMER2, TIMER3. + * + * @return None + * + * @details This macro is used to enable PWM generator and start counter counting. + * \hideinitializer + */ +#define TPWM_START_COUNTER(timer) ((timer)->PWMCTL |= TIMER_PWMCTL_CNTEN_Msk) + +/** + * @brief Stop PWM Counter + * + * @param[in] timer The pointer of the specified Timer module. It could be TIMER0, TIMER1, TIMER2, TIMER3. + * + * @return None + * + * @details This macro is used to stop PWM counter after current period is completed. + * \hideinitializer + */ +#define TPWM_STOP_COUNTER(timer) ((timer)->PWMPERIOD = 0x0) + +/** + * @brief Set Counter Clock Prescaler + * + * @param[in] timer The pointer of the specified Timer module. It could be TIMER0, TIMER1, TIMER2, TIMER3. + * + * @param[in] prescaler Clock prescaler of specified channel. Valid values are between 0x0~0xFFF. + * + * @return None + * + * @details This macro is used to set the prescaler of specified TIMER PWM. + * @note If prescaler is 0, then there is no scaling in counter clock source. + * \hideinitializer + */ +#define TPWM_SET_PRESCALER(timer, prescaler) ((timer)->PWMCLKPSC = (prescaler)) + +/** + * @brief Get Counter Clock Prescaler + * + * @param[in] timer The pointer of the specified Timer module. It could be TIMER0, TIMER1, TIMER2, TIMER3. + * + * @return Target prescaler setting, CLKPSC (TIMERx_PWMCLKPSC[11:0]) + * + * @details Get the prescaler setting, the target counter clock divider is (CLKPSC + 1). + * \hideinitializer + */ +#define TPWM_GET_PRESCALER(timer) ((timer)->PWMCLKPSC) + +/** + * @brief Set Counter Period + * + * @param[in] timer The pointer of the specified Timer module. It could be TIMER0, TIMER1, TIMER2, TIMER3. + * + * @param[in] period Period of specified channel. Valid values are between 0x0~0xFFFF. + * + * @return None + * + * @details This macro is used to set the period of specified TIMER PWM. + * \hideinitializer + */ +#define TPWM_SET_PERIOD(timer, period) ((timer)->PWMPERIOD = (period)) + +/** + * @brief Get Counter Period + * + * @param[in] timer The pointer of the specified Timer module. It could be TIMER0, TIMER1, TIMER2, TIMER3. + * + * @return Target period setting, PERIOD (TIMERx_PWMPERIOD[15:0]) + * + * @details This macro is used to get the period of specified TIMER PWM. + * \hideinitializer + */ +#define TPWM_GET_PERIOD(timer) ((timer)->PWMPERIOD) + +/** + * @brief Set Comparator Value + * + * @param[in] timer The pointer of the specified Timer module. It could be TIMER0, TIMER1, TIMER2, TIMER3. + * + * @param[in] cmp Comparator of specified channel. Valid values are between 0x0~0xFFFF. + * + * @return None + * + * @details This macro is used to set the comparator value of specified TIMER PWM. + * \hideinitializer + */ +#define TPWM_SET_CMPDAT(timer, cmp) ((timer)->PWMCMPDAT = (cmp)) + +/** + * @brief Get Comparator Value + * + * @param[in] timer The pointer of the specified Timer module. It could be TIMER0, TIMER1, TIMER2, TIMER3. + * + * @return Target comparator setting, CMPDAT (TIMERx_PWMCMPDAT[15:0]) + * + * @details This macro is used to get the comparator value of specified TIMER PWM. + * \hideinitializer + */ +#define TPWM_GET_CMPDAT(timer) ((timer)->PWMCMPDAT) + +/** + * @brief Clear Counter + * + * @param[in] timer The pointer of the specified Timer module. It could be TIMER0, TIMER1, TIMER2, TIMER3. + * + * @return None + * + * @details This macro is used to clear counter of specified TIMER PWM. + * \hideinitializer + */ +#define TPWM_CLEAR_COUNTER(timer) ((timer)->PWMCNTCLR = TIMER_PWMCNTCLR_CNTCLR_Msk) + +/** + * @brief Software Trigger Brake Event + * + * @param[in] timer The pointer of the specified Timer module. It could be TIMER0, TIMER1, TIMER2, TIMER3. + * + * @param[in] type Type of brake trigger. Valid values are: + * - \ref TPWM_BRAKE_EDGE + * - \ref TPWM_BRAKE_LEVEL + * + * @return None + * + * @details This macro is used to trigger brake event by writing PWMSWBRK register. + * \hideinitializer + */ +#define TPWM_SW_TRIGGER_BRAKE(timer, type) ((timer)->PWMSWBRK = (type)) + +/** + * @brief Enable Output Function + * + * @param[in] timer The pointer of the specified Timer module. It could be TIMER0, TIMER1, TIMER2, TIMER3. + * + * @param[in] ch Enable specified channel output function. Valid values are the combination of: + * - \ref TPWM_CH0 + * - \ref TPWM_CH1 + * + * @return None + * + * @details This macro is used to enable output function of specified output pins. + * @note If the corresponding bit in ch parameter is 0, then output function will be disabled in this channel. + * \hideinitializer + */ +#define TPWM_ENABLE_OUTPUT(timer, ch) ((timer)->PWMPOEN = (ch)) + +/** + * @brief Set Output Inverse + * + * @param[in] timer The pointer of the specified Timer module. It could be TIMER0, TIMER1, TIMER2, TIMER3. + * + * @param[in] ch Set specified channel output is inversed or not. Valid values are the combination of: + * - \ref TPWM_CH0 + * - \ref TPWM_CH1 + * + * @return None + * + * @details This macro is used to enable output inverse of specified output pins. + * @note If ch parameter is 0, then output inverse function will be disabled. + * \hideinitializer + */ +#define TPWM_SET_OUTPUT_INVERSE(timer, ch) ((timer)->PWMPOLCTL = (ch)) + +/** + * @brief Enable Output Function + * + * @param[in] timer The pointer of the specified Timer module. It could be TIMER0, TIMER1, TIMER2, TIMER3. + * + * @param[in] ch Enable specified channel output mask function. Valid values are the combination of: + * - \ref TPWM_CH0 + * - \ref TPWM_CH1 + * + * @param[in] level Output to high or low on specified mask channel. + * + * @return None + * + * @details This macro is used to enable output function of specified output pins. + * @note If ch parameter is 0, then output mask function will be disabled. + * \hideinitializer + */ +#define TPWM_SET_MASK_OUTPUT(timer, ch, level) do {(timer)->PWMMSKEN = (ch); (timer)->PWMMSK = (level); }while(0) + +/** + * @brief Set Counter Synchronous Mode + * + * @param[in] timer The pointer of the specified Timer module. It could be TIMER0, TIMER1, TIMER2, TIMER3. + * + * @param[in] mode Synchronous mode. Possible options are: + * - \ref TPWM_CNTR_SYNC_DISABLE + * - \ref TPWM_CNTR_SYNC_START_BY_TIMER0 + * - \ref TPWM_CNTR_SYNC_CLEAR_BY_TIMER0 + * - \ref TPWM_CNTR_SYNC_START_BY_TIMER2 + * - \ref TPWM_CNTR_SYNC_CLEAR_BY_TIMER2 + * + * @return None + * + * @details This macro is used to set counter synchronous mode of specified Timer PWM module. + * @note Only support all PWM counters are synchronous by TIMER0 PWM or TIMER0~1 PWM counter synchronous by TIMER0 PWM and + * TIMER2~3 PWM counter synchronous by TIMER2 PWM. + * \hideinitializer + */ +#define TPWM_SET_COUNTER_SYNC_MODE(timer, mode) ((timer)->PWMSCTL = (mode)) + +/** + * @brief Trigger Counter Synchronous + * + * @param[in] timer The pointer of the specified Timer module. It could be TIMER0, TIMER1, TIMER2, TIMER3. + * + * @return None + * + * @details This macro is used to trigger synchronous event by specified TIMER PWM. + * @note 1. This macro is only available for TIMER0 PWM and TIMER2 PWM. \n + * 2. STRGEN (PWMSTRG[0]) is write only and always read as 0. + * \hideinitializer + */ +#define TPWM_TRIGGER_COUNTER_SYNC(timer) ((timer)->PWMSTRG = TIMER_PWMSTRG_STRGEN_Msk) + +/** + * @brief Enable Zero Event Interrupt + * + * @param[in] timer The pointer of the specified Timer module. It could be TIMER0, TIMER1, TIMER2, TIMER3. + * + * @return None + * + * @details This macro is used to enable the zero event interrupt function. + * \hideinitializer + */ +#define TPWM_ENABLE_ZERO_INT(timer) ((timer)->PWMINTEN0 |= TIMER_PWMINTEN0_ZIEN_Msk) + +/** + * @brief Disable Zero Event Interrupt + * + * @param[in] timer The pointer of the specified Timer module. It could be TIMER0, TIMER1, TIMER2, TIMER3. + * + * @return None + * + * @details This macro is used to disable the zero event interrupt function. + * \hideinitializer + */ +#define TPWM_DISABLE_ZERO_INT(timer) ((timer)->PWMINTEN0 &= ~TIMER_PWMINTEN0_ZIEN_Msk) + +/** + * @brief Get Zero Event Interrupt Flag + * + * @param[in] timer The pointer of the specified Timer module. It could be TIMER0, TIMER1, TIMER2, TIMER3. + * + * @retval 0 Zero event interrupt did not occur + * @retval 1 Zero event interrupt occurred + * + * @details This macro indicates zero event occurred or not. + * \hideinitializer + */ +#define TPWM_GET_ZERO_INT_FLAG(timer) (((timer)->PWMINTSTS0 & TIMER_PWMINTSTS0_ZIF_Msk)? 1 : 0) + +/** + * @brief Clear Zero Event Interrupt Flag + * + * @param[in] timer The pointer of the specified Timer module. It could be TIMER0, TIMER1, TIMER2, TIMER3. + * + * @return None + * + * @details This macro clears zero event interrupt flag. + * \hideinitializer + */ +#define TPWM_CLEAR_ZERO_INT_FLAG(timer) ((timer)->PWMINTSTS0 = TIMER_PWMINTSTS0_ZIF_Msk) + +/** + * @brief Enable Period Event Interrupt + * + * @param[in] timer The pointer of the specified Timer module. It could be TIMER0, TIMER1, TIMER2, TIMER3. + * + * @return None + * + * @details This macro is used to enable the period event interrupt function. + * \hideinitializer + */ +#define TPWM_ENABLE_PERIOD_INT(timer) ((timer)->PWMINTEN0 |= TIMER_PWMINTEN0_PIEN_Msk) + +/** + * @brief Disable Period Event Interrupt + * + * @param[in] timer The pointer of the specified Timer module. It could be TIMER0, TIMER1, TIMER2, TIMER3. + * + * @return None + * + * @details This macro is used to disable the period event interrupt function. + * \hideinitializer + */ +#define TPWM_DISABLE_PERIOD_INT(timer) ((timer)->PWMINTEN0 &= ~TIMER_PWMINTEN0_PIEN_Msk) + +/** + * @brief Get Period Event Interrupt Flag + * + * @param[in] timer The pointer of the specified Timer module. It could be TIMER0, TIMER1, TIMER2, TIMER3. + * + * @retval 0 Period event interrupt did not occur + * @retval 1 Period event interrupt occurred + * + * @details This macro indicates period event occurred or not. + * \hideinitializer + */ +#define TPWM_GET_PERIOD_INT_FLAG(timer) (((timer)->PWMINTSTS0 & TIMER_PWMINTSTS0_PIF_Msk)? 1 : 0) + +/** + * @brief Clear Period Event Interrupt Flag + * + * @param[in] timer The pointer of the specified Timer module. It could be TIMER0, TIMER1, TIMER2, TIMER3. + * + * @return None + * + * @details This macro clears period event interrupt flag. + * \hideinitializer + */ +#define TPWM_CLEAR_PERIOD_INT_FLAG(timer) ((timer)->PWMINTSTS0 = TIMER_PWMINTSTS0_PIF_Msk) + +/** + * @brief Enable Compare Up Event Interrupt + * + * @param[in] timer The pointer of the specified Timer module. It could be TIMER0, TIMER1, TIMER2, TIMER3. + * + * @return None + * + * @details This macro is used to enable the compare up event interrupt function. + * \hideinitializer + */ +#define TPWM_ENABLE_CMP_UP_INT(timer) ((timer)->PWMINTEN0 |= TIMER_PWMINTEN0_CMPUIEN_Msk) + +/** + * @brief Disable Compare Up Event Interrupt + * + * @param[in] timer The pointer of the specified Timer module. It could be TIMER0, TIMER1, TIMER2, TIMER3. + * + * @return None + * + * @details This macro is used to disable the compare up event interrupt function. + * \hideinitializer + */ +#define TPWM_DISABLE_CMP_UP_INT(timer) ((timer)->PWMINTEN0 &= ~TIMER_PWMINTEN0_CMPUIEN_Msk) + +/** + * @brief Get Compare Up Event Interrupt Flag + * + * @param[in] timer The pointer of the specified Timer module. It could be TIMER0, TIMER1, TIMER2, TIMER3. + * + * @retval 0 Compare up event interrupt did not occur + * @retval 1 Compare up event interrupt occurred + * + * @details This macro indicates compare up event occurred or not. + * \hideinitializer + */ +#define TPWM_GET_CMP_UP_INT_FLAG(timer) (((timer)->PWMINTSTS0 & TIMER_PWMINTSTS0_CMPUIF_Msk)? 1 : 0) + +/** + * @brief Clear Compare Up Event Interrupt Flag + * + * @param[in] timer The pointer of the specified Timer module. It could be TIMER0, TIMER1, TIMER2, TIMER3. + * + * @return None + * + * @details This macro clears compare up event interrupt flag. + * \hideinitializer + */ +#define TPWM_CLEAR_CMP_UP_INT_FLAG(timer) ((timer)->PWMINTSTS0 = TIMER_PWMINTSTS0_CMPUIF_Msk) + +/** + * @brief Enable Compare Down Event Interrupt + * + * @param[in] timer The pointer of the specified Timer module. It could be TIMER0, TIMER1, TIMER2, TIMER3. + * + * @return None + * + * @details This macro is used to enable the compare down event interrupt function. + * \hideinitializer + */ +#define TPWM_ENABLE_CMP_DOWN_INT(timer) ((timer)->PWMINTEN0 |= TIMER_PWMINTEN0_CMPDIEN_Msk) + +/** + * @brief Disable Compare Down Event Interrupt + * + * @param[in] timer The pointer of the specified Timer module. It could be TIMER0, TIMER1, TIMER2, TIMER3. + * + * @return None + * + * @details This macro is used to disable the compare down event interrupt function. + * \hideinitializer + */ +#define TPWM_DISABLE_CMP_DOWN_INT(timer) ((timer)->PWMINTEN0 &= ~TIMER_PWMINTEN0_CMPDIEN_Msk) + +/** + * @brief Get Compare Down Event Interrupt Flag + * + * @param[in] timer The pointer of the specified Timer module. It could be TIMER0, TIMER1, TIMER2, TIMER3. + * + * @retval 0 Compare down event interrupt did not occur + * @retval 1 Compare down event interrupt occurred + * + * @details This macro indicates compare down event occurred or not. + * \hideinitializer + */ +#define TPWM_GET_CMP_DOWN_INT_FLAG(timer) (((timer)->PWMINTSTS0 & TIMER_PWMINTSTS0_CMPDIF_Msk)? 1 : 0) + +/** + * @brief Clear Compare Down Event Interrupt Flag + * + * @param[in] timer The pointer of the specified Timer module. It could be TIMER0, TIMER1, TIMER2, TIMER3. + * + * @return None + * + * @details This macro clears compare down event interrupt flag. + * \hideinitializer + */ +#define TPWM_CLEAR_CMP_DOWN_INT_FLAG(timer) ((timer)->PWMINTSTS0 = TIMER_PWMINTSTS0_CMPDIF_Msk) + +/** + * @brief Get Counter Reach Maximum Count Status + * + * @param[in] timer The pointer of the specified Timer module. It could be TIMER0, TIMER1, TIMER2, TIMER3. + * + * @retval 0 Timer PWM counter never counts to maximum value + * @retval 1 Timer PWM counter counts to maximum value, 0xFFFF + * + * @details This macro indicates Timer PWM counter has count to 0xFFFF or not. + * \hideinitializer + */ +#define TPWM_GET_REACH_MAX_CNT_STATUS(timer) (((timer)->PWMSTATUS & TIMER_PWMSTATUS_CNTMAXF_Msk)? 1 : 0) + +/** + * @brief Clear Counter Reach Maximum Count Status + * + * @param[in] timer The pointer of the specified Timer module. It could be TIMER0, TIMER1, TIMER2, TIMER3. + * + * @return None + * + * @details This macro clears reach maximum count status. + * \hideinitializer + */ +#define TPWM_CLEAR_REACH_MAX_CNT_STATUS(timer) ((timer)->PWMSTATUS = TIMER_PWMSTATUS_CNTMAXF_Msk) + +/** + * @brief Get Trigger ADC Status + * + * @param[in] timer The pointer of the specified Timer module. It could be TIMER0, TIMER1, TIMER2, TIMER3. + * + * @retval 0 Trigger ADC start conversion is not occur + * @retval 1 Specified counter compare event has trigger ADC start conversion + * + * @details This macro is used to indicate PWM counter compare event has triggered ADC start conversion. + * \hideinitializer + */ +#define TPWM_GET_TRG_ADC_STATUS(timer) (((timer)->PWMSTATUS & TIMER_PWMSTATUS_EADCTRGF_Msk)? 1 : 0) + +/** + * @brief Clear Trigger ADC Status + * + * @param[in] timer The pointer of the specified Timer module. It could be TIMER0, TIMER1, TIMER2, TIMER3. + * + * @return None + * + * @details This macro is used to clear PWM counter compare event trigger ADC status. + * \hideinitializer + */ +#define TPWM_CLEAR_TRG_ADC_STATUS(timer) ((timer)->PWMSTATUS = TIMER_PWMSTATUS_EADCTRGF_Msk) + +/** + * @brief Set Brake Event at Brake Pin High or Low-to-High + * + * @param[in] timer The pointer of the specified Timer module. It could be TIMER0, TIMER1, TIMER2, TIMER3. + * + * @return None + * + * @details This macro is used to set detect brake event when external brake pin at high level or transfer from low to high. + * @note The default brake pin detection is high level or from low to high. + * \hideinitializer + */ +#define TPWM_SET_BRAKE_PIN_HIGH_DETECT(timer) ((timer)->PWMBNF &= ~TIMER_PWMBNF_BRKPINV_Msk) + +/** + * @brief Set Brake Event at Brake Pin Low or High-to-Low + * + * @param[in] timer The pointer of the specified Timer module. It could be TIMER0, TIMER1, TIMER2, TIMER3. + * + * @return None + * + * @details This macro is used to set detect brake event when external brake pin at low level or transfer from high to low. + * \hideinitializer + */ +#define TPWM_SET_BRAKE_PIN_LOW_DETECT(timer) ((timer)->PWMBNF |= TIMER_PWMBNF_BRKPINV_Msk) + +/** + * @brief Set External Brake Pin Source + * + * @param[in] timer The pointer of the specified Timer module. It could be TIMER0, TIMER1, TIMER2, TIMER3. + * @param[in] pin The external brake pin source, could be one of following source + * - \ref TPWM_TM_BRAKE0 + * - \ref TPWM_TM_BRAKE1 + * - \ref TPWM_TM_BRAKE2 + * - \ref TPWM_TM_BRAKE3 + * + * @return None + * + * @details This macro is used to set detect brake event when external brake pin at high level or transfer from low to high. + * \hideinitializer + */ +#define TPWM_SET_BRAKE_PIN_SOURCE(timer, pin) ((timer)->PWMBNF = ((timer)->PWMBNF & ~TIMER_PWMBNF_BKPINSRC_Msk) | ((pin)<> 4ul)-2ul) + + +/** + * @brief Calculate UART baudrate mode2 divider + * + * @param[in] u32SrcFreq UART clock frequency + * @param[in] u32BaudRate Baudrate of UART module + * + * @return UART baudrate mode2 divider + * + * @details This macro calculate UART baudrate mode2 divider. + * \hideinitializer + */ +#define UART_BAUD_MODE2_DIVIDER(u32SrcFreq, u32BaudRate) ((((u32SrcFreq) + ((u32BaudRate)/2ul)) / (u32BaudRate))-2ul) + + +/** + * @brief Write UART data + * + * @param[in] uart The pointer of the specified UART module + * @param[in] u8Data Data byte to transmit. + * + * @return None + * + * @details This macro write Data to Tx data register. + * \hideinitializer + */ +#define UART_WRITE(uart, u8Data) ((uart)->DAT = (u8Data)) + + +/** + * @brief Read UART data + * + * @param[in] uart The pointer of the specified UART module + * + * @return The oldest data byte in RX FIFO. + * + * @details This macro read Rx data register. + * \hideinitializer + */ +#define UART_READ(uart) ((uart)->DAT) + + +/** + * @brief Get Tx empty + * + * @param[in] uart The pointer of the specified UART module + * + * @retval 0 Tx FIFO is not empty + * @retval >=1 Tx FIFO is empty + * + * @details This macro get Transmitter FIFO empty register value. + * \hideinitializer + */ +#define UART_GET_TX_EMPTY(uart) ((uart)->FIFOSTS & UART_FIFOSTS_TXEMPTY_Msk) + + +/** + * @brief Get Rx empty + * + * @param[in] uart The pointer of the specified UART module + * + * @retval 0 Rx FIFO is not empty + * @retval >=1 Rx FIFO is empty + * + * @details This macro get Receiver FIFO empty register value. + * \hideinitializer + */ +#define UART_GET_RX_EMPTY(uart) ((uart)->FIFOSTS & UART_FIFOSTS_RXEMPTY_Msk) + + +/** + * @brief Check specified UART port transmission is over. + * + * @param[in] uart The pointer of the specified UART module + * + * @retval 0 Tx transmission is not over + * @retval 1 Tx transmission is over + * + * @details This macro return Transmitter Empty Flag register bit value. + * It indicates if specified UART port transmission is over nor not. + * \hideinitializer + */ +#define UART_IS_TX_EMPTY(uart) (((uart)->FIFOSTS & UART_FIFOSTS_TXEMPTYF_Msk) >> UART_FIFOSTS_TXEMPTYF_Pos) + + +/** + * @brief Wait specified UART port transmission is over + * + * @param[in] uart The pointer of the specified UART module + * + * @return None + * + * @details This macro wait specified UART port transmission is over. + * \hideinitializer + */ +#define UART_WAIT_TX_EMPTY(uart) while(!((((uart)->FIFOSTS) & UART_FIFOSTS_TXEMPTYF_Msk) >> UART_FIFOSTS_TXEMPTYF_Pos)) + + +/** + * @brief Check RX is ready or not + * + * @param[in] uart The pointer of the specified UART module + * + * @retval 0 The number of bytes in the RX FIFO is less than the RFITL + * @retval 1 The number of bytes in the RX FIFO equals or larger than RFITL + * + * @details This macro check receive data available interrupt flag is set or not. + * \hideinitializer + */ +#define UART_IS_RX_READY(uart) (((uart)->INTSTS & UART_INTSTS_RDAIF_Msk)>>UART_INTSTS_RDAIF_Pos) + + +/** + * @brief Check TX FIFO is full or not + * + * @param[in] uart The pointer of the specified UART module + * + * @retval 1 TX FIFO is full + * @retval 0 TX FIFO is not full + * + * @details This macro check TX FIFO is full or not. + * \hideinitializer + */ +#define UART_IS_TX_FULL(uart) (((uart)->FIFOSTS & UART_FIFOSTS_TXFULL_Msk)>>UART_FIFOSTS_TXFULL_Pos) + + +/** + * @brief Check RX FIFO is full or not + * + * @param[in] uart The pointer of the specified UART module + * + * @retval 1 RX FIFO is full + * @retval 0 RX FIFO is not full + * + * @details This macro check RX FIFO is full or not. + * \hideinitializer + */ +#define UART_IS_RX_FULL(uart) (((uart)->FIFOSTS & UART_FIFOSTS_RXFULL_Msk)>>UART_FIFOSTS_RXFULL_Pos) + + +/** + * @brief Get Tx full register value + * + * @param[in] uart The pointer of the specified UART module + * + * @retval 0 Tx FIFO is not full. + * @retval >=1 Tx FIFO is full. + * + * @details This macro get Tx full register value. + * \hideinitializer + */ +#define UART_GET_TX_FULL(uart) ((uart)->FIFOSTS & UART_FIFOSTS_TXFULL_Msk) + + +/** + * @brief Get Rx full register value + * + * @param[in] uart The pointer of the specified UART module + * + * @retval 0 Rx FIFO is not full. + * @retval >=1 Rx FIFO is full. + * + * @details This macro get Rx full register value. + * \hideinitializer + */ +#define UART_GET_RX_FULL(uart) ((uart)->FIFOSTS & UART_FIFOSTS_RXFULL_Msk) + + +/** + * @brief Enable specified UART interrupt + * + * @param[in] uart The pointer of the specified UART module + * @param[in] u32eIntSel Interrupt type select + * - \ref UART_INTEN_ABRIEN_Msk : Auto baud rate interrupt + * - \ref UART_INTEN_WKIEN_Msk : Wakeup interrupt + * - \ref UART_INTEN_BUFEIEN_Msk : Buffer Error interrupt + * - \ref UART_INTEN_RXTOIEN_Msk : Rx time-out interrupt + * - \ref UART_INTEN_MODEMIEN_Msk : Modem interrupt + * - \ref UART_INTEN_RLSIEN_Msk : Rx Line status interrupt + * - \ref UART_INTEN_THREIEN_Msk : Tx empty interrupt + * - \ref UART_INTEN_RDAIEN_Msk : Rx ready interrupt + * + * @return None + * + * @details This macro enable specified UART interrupt. + * \hideinitializer + */ +#define UART_ENABLE_INT(uart, u32eIntSel) ((uart)->INTEN |= (u32eIntSel)) + + +/** + * @brief Disable specified UART interrupt + * + * @param[in] uart The pointer of the specified UART module + * @param[in] u32eIntSel Interrupt type select + * - \ref UART_INTEN_ABRIEN_Msk : Auto baud rate interrupt + * - \ref UART_INTEN_WKIEN_Msk : Wakeup interrupt + * - \ref UART_INTEN_BUFEIEN_Msk : Buffer Error interrupt + * - \ref UART_INTEN_RXTOIEN_Msk : Rx time-out interrupt + * - \ref UART_INTEN_MODEMIEN_Msk : Modem status interrupt + * - \ref UART_INTEN_RLSIEN_Msk : Receive Line status interrupt + * - \ref UART_INTEN_THREIEN_Msk : Tx empty interrupt + * - \ref UART_INTEN_RDAIEN_Msk : Rx ready interrupt + * + * @return None + * + * @details This macro enable specified UART interrupt. + * \hideinitializer + */ +#define UART_DISABLE_INT(uart, u32eIntSel) ((uart)->INTEN &= ~ (u32eIntSel)) + + +/** + * @brief Get specified interrupt flag/status + * + * @param[in] uart The pointer of the specified UART module + * @param[in] u32eIntTypeFlag Interrupt Type Flag, should be + * - \ref UART_INTSTS_PBUFEINT_Msk : PDMA Mode Buffer Error Interrupt Indicator + * - \ref UART_INTSTS_PTOINT_Msk : PDMA Mode Time-out Interrupt Indicator + * - \ref UART_INTSTS_PMODINT_Msk : PDMA Mode MODEM Status Interrupt Indicator + * - \ref UART_INTSTS_PRLSINT_Msk : PDMA Mode Receive Line Status Interrupt Indicator + * - \ref UART_INTSTS_PBUFEIF_Msk : PDMA Mode Buffer Error Interrupt Flag + * - \ref UART_INTSTS_PTOIF_Msk : PDMA Mode Time-out Interrupt Flag + * - \ref UART_INTSTS_PMODIF_Msk : PDMA Mode MODEM Interrupt Flag + * - \ref UART_INTSTS_PRLSIF_Msk : PDMA Mode Receive Line Status Flag + * - \ref UART_INTSTS_BUFEINT_Msk : Buffer Error Interrupt Indicator + * - \ref UART_INTSTS_RXTOINT_Msk : Time-out Interrupt Indicator + * - \ref UART_INTSTS_MODEMINT_Msk : Modem Status Interrupt Indicator + * - \ref UART_INTSTS_RLSINT_Msk : Receive Line Status Interrupt Indicator + * - \ref UART_INTSTS_THREINT_Msk : Transmit Holding Register Empty Interrupt Indicator + * - \ref UART_INTSTS_RDAINT_Msk : Receive Data Available Interrupt Indicator + * - \ref UART_INTSTS_BUFEIF_Msk : Buffer Error Interrupt Flag + * - \ref UART_INTSTS_RXTOIF_Msk : Rx Time-out Interrupt Flag + * - \ref UART_INTSTS_MODEMIF_Msk : Modem Interrupt Flag + * - \ref UART_INTSTS_RLSIF_Msk : Receive Line Status Interrupt Flag + * - \ref UART_INTSTS_THREIF_Msk : Tx Empty Interrupt Flag + * - \ref UART_INTSTS_RDAIF_Msk : Rx Ready Interrupt Flag + * + * @retval 0 The specified interrupt is not happened. + * 1 The specified interrupt is happened. + * + * @details This macro get specified interrupt flag or interrupt indicator status. + * \hideinitializer + */ +#define UART_GET_INT_FLAG(uart,u32eIntTypeFlag) (((uart)->INTSTS & (u32eIntTypeFlag))?1:0) + + +/** + * @brief Clear RS-485 Address Byte Detection Flag + * + * @param[in] uart The pointer of the specified UART module + * + * @return None + * + * @details This macro clear RS-485 address byte detection flag. + * \hideinitializer + */ +#define UART_RS485_CLEAR_ADDR_FLAG(uart) ((uart)->FIFOSTS = UART_FIFOSTS_ADDRDETF_Msk) + + +/** + * @brief Get RS-485 Address Byte Detection Flag + * + * @param[in] uart The pointer of the specified UART module + * + * @retval 0 Receiver detects a data that is not an address bit. + * @retval 1 Receiver detects a data that is an address bit. + * + * @details This macro get RS-485 address byte detection flag. + * \hideinitializer + */ +#define UART_RS485_GET_ADDR_FLAG(uart) (((uart)->FIFOSTS & UART_FIFOSTS_ADDRDETF_Msk) >> UART_FIFOSTS_ADDRDETF_Pos) + +/* Declare these inline functions here to avoid MISRA C 2004 rule 8.1 error */ +__STATIC_INLINE void UART_CLEAR_RTS(UART_T *uart); +__STATIC_INLINE void UART_SET_RTS(UART_T *uart); + + +/** + * @brief Set RTS pin to low + * + * @param[in] uart The pointer of the specified UART module + * + * @return None + * + * @details This macro set RTS pin to low. + */ +__STATIC_INLINE void UART_CLEAR_RTS(UART_T *uart) +{ + uart->MODEM |= UART_MODEM_RTSACTLV_Msk; + uart->MODEM &= ~UART_MODEM_RTS_Msk; +} + + +/** + * @brief Set RTS pin to high + * + * @param[in] uart The pointer of the specified UART module + * + * @return None + * + * @details This macro set RTS pin to high. + */ +__STATIC_INLINE void UART_SET_RTS(UART_T *uart) +{ + uart->MODEM |= UART_MODEM_RTSACTLV_Msk | UART_MODEM_RTS_Msk; +} + +/** + * @brief Enable specified UART PDMA function + * + * @param[in] uart The pointer of the specified UART module + * @param[in] u32FuncSel Combination of following functions + * - \ref UART_INTEN_TXPDMAEN_Msk + * - \ref UART_INTEN_RXPDMAEN_Msk + * + * @return None + * + * \hideinitializer + */ +#define UART_PDMA_ENABLE(uart, u32FuncSel) ((uart)->INTEN |= (u32FuncSel)) +/** + * @brief Disable specified UART PDMA function + * + * @param[in] uart The pointer of the specified UART module + * @param[in] u32FuncSel Combination of following functions + * - \ref UART_INTEN_TXPDMAEN_Msk + * - \ref UART_INTEN_RXPDMAEN_Msk + * + * @return None + * + * \hideinitializer + */ +#define UART_PDMA_DISABLE(uart, u32FuncSel) ((uart)->INTEN &= ~(u32FuncSel)) + + +void UART_ClearIntFlag(UART_T *uart, uint32_t u32InterruptFlag); +void UART_Close(UART_T *uart); +void UART_DisableFlowCtrl(UART_T *uart); +void UART_DisableInt(UART_T *uart, uint32_t u32InterruptFlag); +void UART_EnableFlowCtrl(UART_T *uart); +void UART_EnableInt(UART_T *uart, uint32_t u32InterruptFlag); +void UART_Open(UART_T *uart, uint32_t u32baudrate); +uint32_t UART_Read(UART_T *uart, uint8_t pu8RxBuf[], uint32_t u32ReadBytes); +void UART_SetLineConfig(UART_T *uart, uint32_t u32baudrate, uint32_t u32data_width, uint32_t u32parity, uint32_t u32stop_bits); +void UART_SetTimeoutCnt(UART_T *uart, uint32_t u32TOC); +void UART_SelectIrDAMode(UART_T *uart, uint32_t u32Buadrate, uint32_t u32Direction); +void UART_SelectRS485Mode(UART_T *uart, uint32_t u32Mode, uint32_t u32Addr); +uint32_t UART_Write(UART_T *uart, uint8_t pu8TxBuf[], uint32_t u32WriteBytes); + + + + +/*@}*/ /* end of group UART_EXPORTED_FUNCTIONS */ + +/*@}*/ /* end of group UART_Driver */ + +/*@}*/ /* end of group Standard_Driver */ + +#ifdef __cplusplus +} +#endif + +#endif /*__NU_UART_H__*/ + diff --git a/bsp/nuvoton/libraries/ma35/StdDriver/inc/nu_wdt.h b/bsp/nuvoton/libraries/ma35/StdDriver/inc/nu_wdt.h new file mode 100644 index 0000000000..5e8398e383 --- /dev/null +++ b/bsp/nuvoton/libraries/ma35/StdDriver/inc/nu_wdt.h @@ -0,0 +1,214 @@ +/**************************************************************************//** + * @file nu_wdt.h + * @brief WDT driver header file + * + * SPDX-License-Identifier: Apache-2.0 + * @copyright (C) 2020 Nuvoton Technology Corp. All rights reserved. + *****************************************************************************/ +#ifndef __NU_WDT_H__ +#define __NU_WDT_H__ + +#ifdef __cplusplus +extern "C" +{ +#endif + + +/** @addtogroup Standard_Driver Standard Driver + @{ +*/ + +/** @addtogroup WDT_Driver WDT Driver + @{ +*/ + +/** @addtogroup WDT_EXPORTED_CONSTANTS WDT Exported Constants + @{ +*/ +/*---------------------------------------------------------------------------------------------------------*/ +/* WDT Time-out Interval Period Constant Definitions */ +/*---------------------------------------------------------------------------------------------------------*/ +#define WDT_TIMEOUT_2POW4 (0UL << WDT_CTL_TOUTSEL_Pos) /*!< Setting WDT time-out interval to 2^4 * WDT clocks \hideinitializer */ +#define WDT_TIMEOUT_2POW6 (1UL << WDT_CTL_TOUTSEL_Pos) /*!< Setting WDT time-out interval to 2^6 * WDT clocks \hideinitializer */ +#define WDT_TIMEOUT_2POW8 (2UL << WDT_CTL_TOUTSEL_Pos) /*!< Setting WDT time-out interval to 2^8 * WDT clocks \hideinitializer */ +#define WDT_TIMEOUT_2POW10 (3UL << WDT_CTL_TOUTSEL_Pos) /*!< Setting WDT time-out interval to 2^10 * WDT clocks \hideinitializer */ +#define WDT_TIMEOUT_2POW12 (4UL << WDT_CTL_TOUTSEL_Pos) /*!< Setting WDT time-out interval to 2^12 * WDT clocks \hideinitializer */ +#define WDT_TIMEOUT_2POW14 (5UL << WDT_CTL_TOUTSEL_Pos) /*!< Setting WDT time-out interval to 2^14 * WDT clocks \hideinitializer */ +#define WDT_TIMEOUT_2POW16 (6UL << WDT_CTL_TOUTSEL_Pos) /*!< Setting WDT time-out interval to 2^16 * WDT clocks \hideinitializer */ +#define WDT_TIMEOUT_2POW18 (7UL << WDT_CTL_TOUTSEL_Pos) /*!< Setting WDT time-out interval to 2^18 * WDT clocks \hideinitializer */ + +/*---------------------------------------------------------------------------------------------------------*/ +/* WDT Reset Delay Period Constant Definitions */ +/*---------------------------------------------------------------------------------------------------------*/ +#define WDT_RESET_DELAY_1026CLK (0UL << WDT_ALTCTL_RSTDSEL_Pos) /*!< Setting WDT reset delay period to 1026 * WDT clocks \hideinitializer */ +#define WDT_RESET_DELAY_130CLK (1UL << WDT_ALTCTL_RSTDSEL_Pos) /*!< Setting WDT reset delay period to 130 * WDT clocks \hideinitializer */ +#define WDT_RESET_DELAY_18CLK (2UL << WDT_ALTCTL_RSTDSEL_Pos) /*!< Setting WDT reset delay period to 18 * WDT clocks \hideinitializer */ +#define WDT_RESET_DELAY_3CLK (3UL << WDT_ALTCTL_RSTDSEL_Pos) /*!< Setting WDT reset delay period to 3 * WDT clocks \hideinitializer */ + +/*---------------------------------------------------------------------------------------------------------*/ +/* WDT Free Reset Counter Keyword Constant Definitions */ +/*---------------------------------------------------------------------------------------------------------*/ +#define WDT_RESET_COUNTER_KEYWORD (0x00005AA5UL) /*!< Fill this value to WDT_RSTCNT register to free reset WDT counter \hideinitializer */ + +/*@}*/ /* end of group WDT_EXPORTED_CONSTANTS */ + + +/** @addtogroup WDT_EXPORTED_FUNCTIONS WDT Exported Functions + @{ +*/ + +/** + * @brief Clear WDT Reset System Flag + * + * @param wdt + * + * @return None + * + * @details This macro clears WDT time-out reset system flag. + * \hideinitializer + */ +#define WDT_CLEAR_RESET_FLAG(wdt) (wdt->CTL = (wdt->CTL & ~(WDT_CTL_IF_Msk | WDT_CTL_WKF_Msk)) | WDT_CTL_RSTF_Msk) + +/** + * @brief Clear WDT Time-out Interrupt Flag + * + * @param wdt + * + * @return None + * + * @details This macro clears WDT time-out interrupt flag. + * \hideinitializer + */ +#define WDT_CLEAR_TIMEOUT_INT_FLAG(wdt) (wdt->CTL = (wdt->CTL & ~(WDT_CTL_RSTF_Msk | WDT_CTL_WKF_Msk)) | WDT_CTL_IF_Msk) + +/** + * @brief Clear WDT Wake-up Flag + * + * @param wdt + * + * @return None + * + * @details This macro clears WDT time-out wake-up system flag. + * \hideinitializer + */ +#define WDT_CLEAR_TIMEOUT_WAKEUP_FLAG(wdt) (wdt->CTL = (wdt->CTL & ~(WDT_CTL_RSTF_Msk | WDT_CTL_IF_Msk)) | WDT_CTL_WKF_Msk) + +/** + * @brief Get WDT Time-out Reset Flag + * + * @param wdt + * + * @retval 0 WDT time-out reset system did not occur + * @retval 1 WDT time-out reset system occurred + * + * @details This macro indicates system has been reset by WDT time-out reset or not. + * \hideinitializer + */ +#define WDT_GET_RESET_FLAG(wdt) ((wdt->CTL & WDT_CTL_RSTF_Msk)? 1UL : 0UL) + +/** + * @brief Get WDT Time-out Interrupt Flag + * + * @param wdt + * + * @retval 0 WDT time-out interrupt did not occur + * @retval 1 WDT time-out interrupt occurred + * + * @details This macro indicates WDT time-out interrupt occurred or not. + * \hideinitializer + */ +#define WDT_GET_TIMEOUT_INT_FLAG(wdt) ((wdt->CTL & WDT_CTL_IF_Msk)? 1UL : 0UL) + +/** + * @brief Get WDT Time-out Wake-up Flag + * + * @param wdt + * + * @retval 0 WDT time-out interrupt does not cause CPU wake-up + * @retval 1 WDT time-out interrupt event cause CPU wake-up + * + * @details This macro indicates WDT time-out interrupt event has waked up system or not. + * \hideinitializer + */ +#define WDT_GET_TIMEOUT_WAKEUP_FLAG(wdt) ((wdt->CTL & WDT_CTL_WKF_Msk)? 1UL : 0UL) + +/** + * @brief Reset WDT Counter + * + * @param wdt + * + * @return None + * + * @details This macro is used to reset the internal 18-bit WDT up counter value. + * @note If WDT is activated and time-out reset system function is enabled also, user should \n + * reset the 18-bit WDT up counter value to avoid generate WDT time-out reset signal to \n + * reset system before the WDT time-out reset delay period expires. + * \hideinitializer + */ +#define WDT_RESET_COUNTER(wdt) (wdt->RSTCNT = WDT_RESET_COUNTER_KEYWORD) + +/* Declare these inline functions here to avoid MISRA C 2004 rule 8.1 error */ +__STATIC_INLINE void WDT_Close(WDT_T *wdt); +__STATIC_INLINE void WDT_EnableInt(WDT_T *wdt); +__STATIC_INLINE void WDT_DisableInt(WDT_T *wdt); + +/** + * @brief Stop WDT Counting + * + * @param None + * + * @return None + * + * @details This function will stop WDT counting and disable WDT module. + */ +__STATIC_INLINE void WDT_Close(WDT_T *wdt) +{ + wdt->CTL = 0UL; + return; +} + +/** + * @brief Enable WDT Time-out Interrupt + * + * @param None + * + * @return None + * + * @details This function will enable the WDT time-out interrupt function. + */ +__STATIC_INLINE void WDT_EnableInt(WDT_T *wdt) +{ + wdt->CTL |= WDT_CTL_INTEN_Msk; + return; +} + +/** + * @brief Disable WDT Time-out Interrupt + * + * @param None + * + * @return None + * + * @details This function will disable the WDT time-out interrupt function. + */ +__STATIC_INLINE void WDT_DisableInt(WDT_T *wdt) +{ + /* Do not touch another write 1 clear bits */ + wdt->CTL &= ~(WDT_CTL_INTEN_Msk | WDT_CTL_RSTF_Msk | WDT_CTL_IF_Msk | WDT_CTL_WKF_Msk); + return; +} + +void WDT_Open(WDT_T *wdt, uint32_t u32TimeoutInterval, uint32_t u32ResetDelay, uint32_t u32EnableReset, uint32_t u32EnableWakeup); + +/*@}*/ /* end of group WDT_EXPORTED_FUNCTIONS */ + +/*@}*/ /* end of group WDT_Driver */ + +/*@}*/ /* end of group Standard_Driver */ + +#ifdef __cplusplus +} +#endif + +#endif /* __NU_WDT_H__ */ + diff --git a/bsp/nuvoton/libraries/ma35/StdDriver/inc/nu_whc.h b/bsp/nuvoton/libraries/ma35/StdDriver/inc/nu_whc.h new file mode 100644 index 0000000000..32ccc070b7 --- /dev/null +++ b/bsp/nuvoton/libraries/ma35/StdDriver/inc/nu_whc.h @@ -0,0 +1,279 @@ +/**************************************************************************//** + * @file nu_whc.h + * @brief WHC driver header file + * + * SPDX-License-Identifier: Apache-2.0 + * @copyright (C) 2020 Nuvoton Technology Corp. All rights reserved. + *****************************************************************************/ +#ifndef __NU_WHC_H__ +#define __NU_WHC_H__ + +#ifdef __cplusplus +extern "C" +{ +#endif + + +/** @addtogroup Standard_Driver Standard Driver + @{ +*/ + +/** @addtogroup WHC_Driver WHC Driver + @{ +*/ + +/** @addtogroup WHC_EXPORTED_CONSTANTS WHC Exported Constants + @{ +*/ +#define WHC_CH 4ul /*!TXCTL |= (1ul << (u32Ch + WHC_TXCTL_CH0RC_Pos))) + +/** + * @brief + * + * @param[in] whc The pointer of the specified WHC module. + * @param[in] u32Ch WHC channel, valid channel numbers are 0~3 + * \hideinitializer + */ +#define WHC_IS_TX_READY(whc, u32Ch) ((whc)->TXSTS & (1 << u32Ch)) + +/** + * @brief + * + * @param[in] whc The pointer of the specified WHC module. + * @param[in] u32Ch WHC channel, valid channel numbers are 0~3 + * \hideinitializer + */ +#define WHC_IS_RX_READY(whc, u32Ch) ((whc)->RXSTS & (1 << u32Ch)) + +/** + * @brief Enable specified WHC interrupt + * + * @param[in] whc The pointer of the specified WHC module + * @param[in] u32IntSel Interrupt type select + * - \ref WHC_INTEN_RST0IEN_Msk + * - \ref WHC_INTEN_POFF0IEN_Msk + * - \ref WHC_INTEN_PD0IEN_Msk + * - \ref WHC_INTEN_RST1IEN_Msk + * - \ref WHC_INTEN_POFF1IEN_Msk + * - \ref WHC_INTEN_PD1IEN_Msk + * - \ref WHC_INTEN_GI0IEN_Msk + * - \ref WHC_INTEN_GI1IEN_Msk + * - \ref WHC_INTEN_GI2IEN_Msk + * - \ref WHC_INTEN_GI3IEN_Msk + * - \ref WHC_INTEN_TX0IEN_Msk + * - \ref WHC_INTEN_TX1IEN_Msk + * - \ref WHC_INTEN_TX2IEN_Msk + * - \ref WHC_INTEN_TX3IEN_Msk + * - \ref WHC_INTEN_RX0IEN_Msk + * - \ref WHC_INTEN_RX1IEN_Msk + * - \ref WHC_INTEN_RX2IEN_Msk + * - \ref WHC_INTEN_RX3IEN_Msk + * \hideinitializer + */ +#define WHC_ENABLE_INT(whc, u32IntSel) ((whc)->INTEN |= (u32IntSel)) + + +/** + * @brief Disable specified WHC interrupt + * + * @param[in] whc The pointer of the specified WHC module + * @param[in] u32IntSel Interrupt type select + * - \ref WHC_INTEN_RST0IEN_Msk + * - \ref WHC_INTEN_POFF0IEN_Msk + * - \ref WHC_INTEN_PD0IEN_Msk + * - \ref WHC_INTEN_RST1IEN_Msk + * - \ref WHC_INTEN_POFF1IEN_Msk + * - \ref WHC_INTEN_PD1IEN_Msk + * - \ref WHC_INTEN_GI0IEN_Msk + * - \ref WHC_INTEN_GI1IEN_Msk + * - \ref WHC_INTEN_GI2IEN_Msk + * - \ref WHC_INTEN_GI3IEN_Msk + * - \ref WHC_INTEN_TX0IEN_Msk + * - \ref WHC_INTEN_TX1IEN_Msk + * - \ref WHC_INTEN_TX2IEN_Msk + * - \ref WHC_INTEN_TX3IEN_Msk + * - \ref WHC_INTEN_RX0IEN_Msk + * - \ref WHC_INTEN_RX1IEN_Msk + * - \ref WHC_INTEN_RX2IEN_Msk + * - \ref WHC_INTEN_RX3IEN_Msk + * \hideinitializer + */ +#define WHC_DISABLE_INT(whc, u32IntSel) ((whc)->INTEN &= ~(u32IntSel)) + +/** + * @brief Get specified interrupt flag + * + * @param[in] whc The pointer of the specified WHC module + * @param[in] u32IntTypeFlag Interrupt Type Flag, should be + * - \ref WHC_INTSTS_RST0IF_Msk + * - \ref WHC_INTSTS_POFF0IF_Msk + * - \ref WHC_INTSTS_PD0IF_Msk + * - \ref WHC_INTSTS_RST1IF_Msk + * - \ref WHC_INTSTS_POFF1IF_Msk + * - \ref WHC_INTSTS_PD1IF_Msk + * - \ref WHC_INTSTS_GI0IF_Msk + * - \ref WHC_INTSTS_GI1IF_Msk + * - \ref WHC_INTSTS_GI2IF_Msk + * - \ref WHC_INTSTS_GI3IF_Msk + * - \ref WHC_INTSTS_TX0IF_Msk + * - \ref WHC_INTSTS_TX1IF_Msk + * - \ref WHC_INTSTS_TX2IF_Msk + * - \ref WHC_INTSTS_TX3IF_Msk + * - \ref WHC_INTSTS_RX0IF_Msk + * - \ref WHC_INTSTS_RX1IF_Msk + * - \ref WHC_INTSTS_RX2IF_Msk + * - \ref WHC_INTSTS_RX3IF_Msk + * + * @retval 0 The specified interrupt is not happened. + * 1 The specified interrupt is happened. + * \hideinitializer + */ +#define WHC_GET_INT_FLAG(whc, u32IntTypeFlag) (((whc)->INTSTS & (u32IntTypeFlag))?1:0) + +/** + * @brief Clear specified interrupt flag + * + * @param[in] whc The pointer of the specified WHC module + * @param[in] u32IntTypeFlag Interrupt Type Flag, should be + * - \ref WHC_INTSTS_RST0IF_Msk + * - \ref WHC_INTSTS_POFF0IF_Msk + * - \ref WHC_INTSTS_PD0IF_Msk + * - \ref WHC_INTSTS_RST1IF_Msk + * - \ref WHC_INTSTS_POFF1IF_Msk + * - \ref WHC_INTSTS_PD1IF_Msk + * - \ref WHC_INTSTS_GI0IF_Msk + * - \ref WHC_INTSTS_GI1IF_Msk + * - \ref WHC_INTSTS_GI2IF_Msk + * - \ref WHC_INTSTS_GI3IF_Msk + * - \ref WHC_INTSTS_TX0IF_Msk + * - \ref WHC_INTSTS_TX1IF_Msk + * - \ref WHC_INTSTS_TX2IF_Msk + * - \ref WHC_INTSTS_TX3IF_Msk + * - \ref WHC_INTSTS_RX0IF_Msk + * - \ref WHC_INTSTS_RX1IF_Msk + * - \ref WHC_INTSTS_RX2IF_Msk + * - \ref WHC_INTSTS_RX3IF_Msk + * \hideinitializer + */ +#define WHC_CLR_INT_FLAG(whc, u32IntTypeFlag) ((whc)->INTSTS = (u32IntTypeFlag)) + +/** + * @brief Trigger WHC general event interrupt + * @param[in] whc The pointer of the specified WHC module + * @param[in] u32IntNum General event interrupt number, valid number are 0~3 + * + * \hideinitializer + */ +#define WHC_TRIGGER_GINT(whc, u32IntNum) ((whc)->GINTTRG = (1ul << u32IntNum)) + +/** + * @brief Get counter part reset flag + * @param[in] whc The pointer of the specified WHC module + * @retval The combination of WHC_CPSTS_WDTRF_Msk, WHC_CPSTS_SYSRF_Msk, and WHC_CPSTS_CPURF_Msk + * + * \hideinitializer + */ +#define WHC_GET_RST_FLAG(whc) ((whc)->CPSTS & (WHC_CPSTS_WDTRF_Msk | WHC_CPSTS_SYSRF_Msk | WHC_CPSTS_CPURF_Msk)) + +/** + * @brief Clear counter part reset flag + * @param[in] whc The pointer of the specified WHC module + * + * \hideinitializer + */ +#define WHC_CLR_RST_FLAG(whc) ((whc)->CPSTS = (whc)->CPSTS) + + +/** + * @brief Set wakeup up source + * + * @param[in] whc The pointer of the specified WHC module + * @param[in] u32WakeupSrc Wake up source. Should be the combination of: + * - \ref WHC_WKCTL_RST0WKEN_Msk + * - \ref WHC_WKCTL_POFF0WKEN_Msk + * - \ref WHC_WKCTL_PD0WKEN_Msk + * - \ref WHC_WKCTL_RST1WKEN_Msk + * - \ref WHC_WKCTL_POFF1WKEN_Msk + * - \ref WHC_WKCTL_PD1WKEN_Msk + * - \ref WHC_WKCTL_GI0WKEN_Msk + * - \ref WHC_WKCTL_GI1WKEN_Msk + * - \ref WHC_WKCTL_GI2WKEN_Msk + * - \ref WHC_WKCTL_GI3WKEN_Msk + * - \ref WHC_WKCTL_TX0WKEN_Msk + * - \ref WHC_WKCTL_TX1WKEN_Msk + * - \ref WHC_WKCTL_TX2WKEN_Msk + * - \ref WHC_WKCTL_TX3WKEN_Msk + * - \ref WHC_WKCTL_RX0WKEN_Msk + * - \ref WHC_WKCTL_RX1WKEN_Msk + * - \ref WHC_WKCTL_RX2WKEN_Msk + * - \ref WHC_WKCTL_RX3WKEN_Msk + * \hideinitializer + */ +#define WHC_SET_WAKEUP_SRC(whc,u32WakeFlag) ((whc)->WKCTL |= (u32WakeFlag)) + + +/** + * @brief Clear wakeup up source + * + * @param[in] whc The pointer of the specified WHC module + * @param[in] u32WakeupSrc Wake up source. Should be the combination of: + * - \ref WHC_WKCTL_RST0WKEN_Msk + * - \ref WHC_WKCTL_POFF0WKEN_Msk + * - \ref WHC_WKCTL_PD0WKEN_Msk + * - \ref WHC_WKCTL_RST1WKEN_Msk + * - \ref WHC_WKCTL_POFF1WKEN_Msk + * - \ref WHC_WKCTL_PD1WKEN_Msk + * - \ref WHC_WKCTL_GI0WKEN_Msk + * - \ref WHC_WKCTL_GI1WKEN_Msk + * - \ref WHC_WKCTL_GI2WKEN_Msk + * - \ref WHC_WKCTL_GI3WKEN_Msk + * - \ref WHC_WKCTL_TX0WKEN_Msk + * - \ref WHC_WKCTL_TX1WKEN_Msk + * - \ref WHC_WKCTL_TX2WKEN_Msk + * - \ref WHC_WKCTL_TX3WKEN_Msk + * - \ref WHC_WKCTL_RX0WKEN_Msk + * - \ref WHC_WKCTL_RX1WKEN_Msk + * - \ref WHC_WKCTL_RX2WKEN_Msk + * - \ref WHC_WKCTL_RX3WKEN_Msk + * \hideinitializer + */ +#define WHC_CLR_WAKEUP_SRC(whc,u32WakeFlag) ((whc)->WKCTL &= ~(u32WakeFlag)) + +int WHC_Send(WHC_T *whc, uint32_t u32Ch, uint32_t *pu32TxBuf); +int WHC_Recv(WHC_T *whc, uint32_t u32Ch, uint32_t *pu32RxBuf); +int WHC_GetCPSts(WHC_T *whc, uint32_t u32Core); + + +/*@}*/ /* end of group WHC_EXPORTED_FUNCTIONS */ + +/*@}*/ /* end of group WHC_Driver */ + +/*@}*/ /* end of group Standard_Driver */ + +#ifdef __cplusplus +} +#endif + +#endif + diff --git a/bsp/nuvoton/libraries/ma35/StdDriver/inc/nu_wwdt.h b/bsp/nuvoton/libraries/ma35/StdDriver/inc/nu_wwdt.h new file mode 100644 index 0000000000..054876a92d --- /dev/null +++ b/bsp/nuvoton/libraries/ma35/StdDriver/inc/nu_wwdt.h @@ -0,0 +1,150 @@ +/**************************************************************************//** + * @file nu_wwdt.h + * @brief WWDT driver header file + * + * SPDX-License-Identifier: Apache-2.0 + * @copyright (C) 2020 Nuvoton Technology Corp. All rights reserved. + *****************************************************************************/ +#ifndef __NU_WWDT_H__ +#define __NU_WWDT_H__ + +#ifdef __cplusplus +extern "C" +{ +#endif + + +/** @addtogroup Standard_Driver Standard Driver + @{ +*/ + +/** @addtogroup WWDT_Driver WWDT Driver + @{ +*/ + +/** @addtogroup WWDT_EXPORTED_CONSTANTS WWDT Exported Constants + @{ +*/ +/*---------------------------------------------------------------------------------------------------------*/ +/* WWDT Prescale Period Constant Definitions */ +/*---------------------------------------------------------------------------------------------------------*/ +#define WWDT_PRESCALER_1 (0 << WWDT_CTL_PSCSEL_Pos) /*!< Select max time-out period to 1 * (64*WWDT_CLK) \hideinitializer */ +#define WWDT_PRESCALER_2 (1 << WWDT_CTL_PSCSEL_Pos) /*!< Select max time-out period to 2 * (64*WWDT_CLK) \hideinitializer */ +#define WWDT_PRESCALER_4 (2 << WWDT_CTL_PSCSEL_Pos) /*!< Select max time-out period to 4 * (64*WWDT_CLK) \hideinitializer */ +#define WWDT_PRESCALER_8 (3 << WWDT_CTL_PSCSEL_Pos) /*!< Select max time-out period to 8 * (64*WWDT_CLK) \hideinitializer */ +#define WWDT_PRESCALER_16 (4 << WWDT_CTL_PSCSEL_Pos) /*!< Select max time-out period to 16 * (64*WWDT_CLK) \hideinitializer */ +#define WWDT_PRESCALER_32 (5 << WWDT_CTL_PSCSEL_Pos) /*!< Select max time-out period to 32 * (64*WWDT_CLK) \hideinitializer */ +#define WWDT_PRESCALER_64 (6 << WWDT_CTL_PSCSEL_Pos) /*!< Select max time-out period to 64 * (64*WWDT_CLK) \hideinitializer */ +#define WWDT_PRESCALER_128 (7 << WWDT_CTL_PSCSEL_Pos) /*!< Select max time-out period to 128 * (64*WWDT_CLK) \hideinitializer */ +#define WWDT_PRESCALER_192 (8 << WWDT_CTL_PSCSEL_Pos) /*!< Select max time-out period to 192 * (64*WWDT_CLK) \hideinitializer */ +#define WWDT_PRESCALER_256 (9 << WWDT_CTL_PSCSEL_Pos) /*!< Select max time-out period to 256 * (64*WWDT_CLK) \hideinitializer */ +#define WWDT_PRESCALER_384 (10 << WWDT_CTL_PSCSEL_Pos) /*!< Select max time-out period to 384 * (64*WWDT_CLK) \hideinitializer */ +#define WWDT_PRESCALER_512 (11 << WWDT_CTL_PSCSEL_Pos) /*!< Select max time-out period to 512 * (64*WWDT_CLK) \hideinitializer */ +#define WWDT_PRESCALER_768 (12 << WWDT_CTL_PSCSEL_Pos) /*!< Select max time-out period to 768 * (64*WWDT_CLK) \hideinitializer */ +#define WWDT_PRESCALER_1024 (13 << WWDT_CTL_PSCSEL_Pos) /*!< Select max time-out period to 1024 * (64*WWDT_CLK) \hideinitializer */ +#define WWDT_PRESCALER_1536 (14 << WWDT_CTL_PSCSEL_Pos) /*!< Select max time-out period to 1536 * (64*WWDT_CLK) \hideinitializer */ +#define WWDT_PRESCALER_2048 (15 << WWDT_CTL_PSCSEL_Pos) /*!< Select max time-out period to 2048 * (64*WWDT_CLK) \hideinitializer */ + +/*---------------------------------------------------------------------------------------------------------*/ +/* WWDT Reload Counter Keyword Constant Definitions */ +/*---------------------------------------------------------------------------------------------------------*/ +#define WWDT_RELOAD_WORD (0x00005AA5) /*!< Fill this value to WWDT_RLDCNT register to reload WWDT counter \hideinitializer */ + +/*@}*/ /* end of group WWDT_EXPORTED_CONSTANTS */ + + +/** @addtogroup WWDT_EXPORTED_FUNCTIONS WWDT Exported Functions + @{ +*/ + +/** + * @brief Clear WWDT Reset System Flag + * + * @param None + * + * @return None + * + * @details This macro is used to clear WWDT time-out reset system flag. + * \hideinitializer + */ +#define WWDT_CLEAR_RESET_FLAG() (WWDT2->STATUS = WWDT_STATUS_WWDTRF_Msk) + +/** + * @brief Clear WWDT Compared Match Interrupt Flag + * + * @param None + * + * @return None + * + * @details This macro is used to clear WWDT compared match interrupt flag. + * \hideinitializer + */ +#define WWDT_CLEAR_INT_FLAG() (WWDT2->STATUS = WWDT_STATUS_WWDTIF_Msk) + +/** + * @brief Get WWDT Reset System Flag + * + * @param None + * + * @retval 0 WWDT time-out reset system did not occur + * @retval 1 WWDT time-out reset system occurred + * + * @details This macro is used to indicate system has been reset by WWDT time-out reset or not. + * \hideinitializer + */ +#define WWDT_GET_RESET_FLAG() ((WWDT2->STATUS & WWDT_STATUS_WWDTRF_Msk)? 1 : 0) + +/** + * @brief Get WWDT Compared Match Interrupt Flag + * + * @param None + * + * @retval 0 WWDT compare match interrupt did not occur + * @retval 1 WWDT compare match interrupt occurred + * + * @details This macro is used to indicate WWDT counter value matches CMPDAT value or not. + * \hideinitializer + */ +#define WWDT_GET_INT_FLAG() ((WWDT2->STATUS & WWDT_STATUS_WWDTIF_Msk)? 1 : 0) + +/** + * @brief Get WWDT Counter + * + * @param None + * + * @return WWDT Counter Value + * + * @details This macro reflects the current WWDT counter value. + * \hideinitializer + */ +#define WWDT_GET_COUNTER() (WWDT2->CNT) + +/** + * @brief Reload WWDT Counter + * + * @param None + * + * @return None + * + * @details This macro is used to reload the WWDT counter value to 0x3F. + * @note User can only write WWDT_RLDCNT register to reload WWDT counter value when current WWDT counter value \n + * between 0 and CMPDAT value. If user writes WWDT_RLDCNT when current WWDT counter value is larger than CMPDAT, \n + * WWDT reset signal will generate immediately to reset system. + * \hideinitializer + */ +#define WWDT_RELOAD_COUNTER() (WWDT2->RLDCNT = WWDT_RELOAD_WORD) + +void WWDT_Open(uint32_t u32PreScale, uint32_t u32CmpValue, uint32_t u32EnableInt); + +/*@}*/ /* end of group WWDT_EXPORTED_FUNCTIONS */ + +/*@}*/ /* end of group WWDT_Driver */ + +/*@}*/ /* end of group Standard_Driver */ + +#ifdef __cplusplus +} +#endif + +#endif /* __NU_WWDT_H__ */ + diff --git a/bsp/nuvoton/libraries/ma35/StdDriver/src/nu_adc.c b/bsp/nuvoton/libraries/ma35/StdDriver/src/nu_adc.c new file mode 100644 index 0000000000..d8dfdf1342 --- /dev/null +++ b/bsp/nuvoton/libraries/ma35/StdDriver/src/nu_adc.c @@ -0,0 +1,87 @@ +/**************************************************************************//** + * @file adc.c + * @brief ADC driver source file + * + * SPDX-License-Identifier: Apache-2.0 + * @copyright(C) 2020 Nuvoton Technology Corp. All rights reserved. + *****************************************************************************/ +#include "NuMicro.h" + +/** @addtogroup Standard_Driver Standard Driver + @{ +*/ + +/** @addtogroup ADC_Driver ADC Driver + @{ +*/ + + +/** @addtogroup ADC_EXPORTED_FUNCTIONS ADC Exported Functions + @{ +*/ + +/** + * @brief This API configures ADC module to be ready for convert the input from selected channel + * @param[in] adc Base address of ADC module + * @param[in] u32InputMode Input mode. Valid values are: + * - \ref ADC_INPUT_MODE_NORMAL_CONV + * - \ref ADC_INPUT_MODE_4WIRE_TOUCH + * - \ref ADC_INPUT_MODE_5WIRE_TOUCH + * @param[in] u32OpMode Could be + * - \ref ADC_HIGH_SPEED_MODE + * - \ref ADC_NORMAL_SPEED_MODE + * @param[in] u32ChMask Channel enable bit. Each bit corresponds to a input channel. Bit 0 is channel 0, bit 1 is channel 1... + * This parameter is only used while u32InputMode set to ADC_INPUT_MODE_NORMAL_CONV. + * @return None + * @note ADC can only convert 1 channel at a time. If more than 1 channels are enabled, only channel + * with smallest number will be convert. + * @note This API does not turn on ADC power nor does trigger ADC conversion + */ +void ADC_Open(ADC_T *adc, + uint32_t u32InputMode, + uint32_t u32OpMode, + uint32_t u32ChMask) +{ + uint32_t u32Ch = 0, i; + + if (u32InputMode == ADC_INPUT_MODE_NORMAL_CONV) + { + for (i = 0; i < ADC_CH_NUM; i++) + { + if (u32ChMask & (1 << i)) + { + u32Ch = i; + break; + } + } + adc->CONF = (u32Ch << ADC_CONF_CHSEL_Pos) | u32OpMode | ADC_CONF_NACEN_Msk; + } + else if (u32InputMode == ADC_INPUT_MODE_4WIRE_TOUCH) + { + adc->CONF = 0; + } + else // 5-wire mode + { + adc->CTL |= ADC_CTL_WMSWCH_Msk; + adc->CONF = 0; + } +} + +/** + * @brief Disable ADC module + * @param[in] adc Base address of ADC module + * @return None + */ +void ADC_Close(ADC_T *adc) +{ + adc->CTL = 0; + adc->CONF = 0; + adc->IER = 0; + adc->ISR = adc->ISR; +} + +/*@}*/ /* end of group ADC_EXPORTED_FUNCTIONS */ + +/*@}*/ /* end of group ADC_Driver */ + +/*@}*/ /* end of group Standard_Driver */ diff --git a/bsp/nuvoton/libraries/ma35/StdDriver/src/nu_canfd.c b/bsp/nuvoton/libraries/ma35/StdDriver/src/nu_canfd.c new file mode 100644 index 0000000000..55c15dfaec --- /dev/null +++ b/bsp/nuvoton/libraries/ma35/StdDriver/src/nu_canfd.c @@ -0,0 +1,1894 @@ +/**************************************************************************//** + * @file canfd.c + * @brief CANFD driver source file + * + * SPDX-License-Identifier: Apache-2.0 + * @copyright (C) 2020 Nuvoton Technology Corp. All rights reserved. + *****************************************************************************/ + +#include "NuMicro.h" +#include "string.h" + +/******************************************************************************* + * Definitions + ******************************************************************************/ + +/* Minimum number of time quanta in a bit. */ +#define MIN_TIME_QUANTA 9ul +/* Maximum number of time quanta in a bit. */ +#define MAX_TIME_QUANTA 20ul +/* Number of receive FIFOs (1 - 2) */ +#define CANFD_NUM_RX_FIFOS 2ul + +/*CANFD max nominal bit rate*/ +#define MAX_NOMINAL_BAUDRATE (1000000UL) + +/* Tx Event FIFO Element ESI(Error State Indicator) */ +#define TX_FIFO_E0_EVENT_ESI_Pos (31) +#define TX_FIFO_E0_EVENT_ESI_Msk (0x1ul << TX_FIFO_E0_EVENT_ESI_Pos) + +/* Tx Event FIFO Element XTD(Extended Identifier) */ +#define TX_FIFO_E0_EVENT_XTD_Pos (30) +#define TX_FIFO_E0_EVENT_XTD_Msk (0x1ul << TX_FIFO_E0_EVENT_XTD_Pos) + +/* Tx Event FIFO Element RTR(Remote Transmission Request) */ +#define TX_FIFO_E0_EVENT_RTR_Pos (29) +#define TX_FIFO_E0_EVENT_RTR_Msk (0x1ul << TX_FIFO_E0_EVENT_RTR_Pos) + +/* Tx Event FIFO Element ID(Identifier) */ +#define TX_FIFO_E0_EVENT_ID_Pos (0) +#define TX_FIFO_E0_EVENT_ID_Msk (0x1FFFFFFFul << TX_FIFO_E0_EVENT_ID_Pos) + +/* Tx Event FIFO Element MM(Message Marker) */ +#define TX_FIFO_E1_EVENT_MM_Pos (24) +#define TX_FIFO_E1_EVENT_MM_Msk (0xFFul << TX_FIFO_E1_EVENT_MM_Pos) + +/* Tx Event FIFO Element ET(Event Type) */ +#define TX_FIFO_E1_EVENT_ET_Pos (22) +#define TX_FIFO_E1_EVENT_ET_Msk (0x3ul << TX_FIFO_E1_EVENT_ET_Pos) + +/* Tx Event FIFO Element FDF(FD Format) */ +#define TX_FIFO_E1_EVENT_FDF_Pos (21) +#define TX_FIFO_E1_EVENT_FDF_Msk (0x1ul << TX_FIFO_E1_EVENT_FDF_Pos) + +/* Tx Event FIFO Element BRS(Bit Rate Switch) */ +#define TX_FIFO_E1_EVENT_BRS_Pos (20) +#define TX_FIFO_E1_EVENT_BRS_Msk (0x1ul << TX_FIFO_E1_EVENT_BRS_Pos) + +/* Tx Event FIFO Element DLC(Data Length Code) */ +#define TX_FIFO_E1_EVENT_DLC_Pos (16) +#define TX_FIFO_E1_EVENT_DLC_Msk (0xFul << TX_FIFO_E1_EVENT_DLC_Pos) + +/* Tx Event FIFO Element TXTS(Tx Timestamp) */ +#define TX_FIFO_E1A_EVENT_TXTS_Pos (0) +#define TX_FIFO_E1A_EVENT_TXTS_Msk (0xFFFFul << TX_FIFO_E1A_EVENT_TXTS_Pos) + +/* Tx Event FIFO Element MM(Message Marker) */ +#define TX_FIFO_E1B_EVENT_MM_Pos (8) +#define TX_FIFO_E1B_EVENT_MM_Msk (0xFFul << TX_FIFO_E1B_EVENT_MM_Pos) + +/* Tx Event FIFO Element TSC(Timestamp Captured) */ +#define TX_FIFO_E1B_EVENT_TSC_Pos (4) +#define TX_FIFO_E1B_EVENT_TSC_Msk (0x1ul << TX_FIFO_E1B_EVENT_TSC_Pos) + +/* Tx Event FIFO Element TSC(Timestamp Captured) */ +#define TX_FIFO_E1B_EVENT_TXTS_Pos (0) +#define TX_FIFO_E1B_EVENT_TXTS_Msk (0xFul << TX_FIFO_E1B_EVENT_TSC_Pos) + +/* Rx Buffer and FIFO Element ESI2(Error State Indicator) */ +#define RX_BUFFER_AND_FIFO_R0_ELEM_ESI_Pos (31) +#define RX_BUFFER_AND_FIFO_R0_ELEM_ESI_Msk (0x1ul << RX_BUFFER_AND_FIFO_R0_ELEM_ESI_Pos) + +/* Rx Buffer and FIFO Element XTD(Extended Identifier) */ +#define RX_BUFFER_AND_FIFO_R0_ELEM_XTD_Pos (30) +#define RX_BUFFER_AND_FIFO_R0_ELEM_XTD_Msk (0x1ul << RX_BUFFER_AND_FIFO_R0_ELEM_XTD_Pos) + +/* Rx Buffer and FIFO Element RTR(Remote Transmission Request) */ +#define RX_BUFFER_AND_FIFO_R0_ELEM_RTR_Pos (29) +#define RX_BUFFER_AND_FIFO_R0_ELEM_RTR_Msk (0x1ul << RX_BUFFER_AND_FIFO_R0_ELEM_RTR_Pos) + +/* Rx Buffer and FIFO Element ID(Identifier) */ +#define RX_BUFFER_AND_FIFO_R0_ELEM_ID_Pos (0) +#define RX_BUFFER_AND_FIFO_R0_ELEM_ID_Msk (0x1FFFFFFFul << RX_BUFFER_AND_FIFO_R0_ELEM_ID_Pos) + +/* Rx Buffer and FIFO Element ANMF(Accepted Non-matching Frame) */ +#define RX_BUFFER_AND_FIFO_R1_ELEM_ANMF_Pos (31) +#define RX_BUFFER_AND_FIFO_R1_ELEM_ANMF_Msk (0x1ul << RX_BUFFER_AND_FIFO_R1_ELEM_ANMF_Pos) + +/* Rx Buffer and FIFO Element FIDX(Filter Index) */ +#define RX_BUFFER_AND_FIFO_R1_ELEM_FIDX_Pos (24) +#define RX_BUFFER_AND_FIFO_R1_ELEM_FIDX_Msk (0x7Ful << RX_BUFFER_AND_FIFO_R1_ELEM_FIDX_Pos) + +/* Rx Buffer and FIFO Element FDF(FD Format) */ +#define RX_BUFFER_AND_FIFO_R1_ELEM_FDF_Pos (21) +#define RX_BUFFER_AND_FIFO_R1_ELEM_FDF_Msk (0x1ul << RX_BUFFER_AND_FIFO_R1_ELEM_FDF_Pos) + +/* Rx Buffer and FIFO Element BRS(Bit Rate Swit) */ +#define RX_BUFFER_AND_FIFO_R1_ELEM_BSR_Pos (20) +#define RX_BUFFER_AND_FIFO_R1_ELEM_BSR_Msk (0x1ul << RX_BUFFER_AND_FIFO_R1_ELEM_BSR_Pos) + +/* Rx Buffer and FIFO Element DLC(Bit Rate Swit) */ +#define RX_BUFFER_AND_FIFO_R1_ELEM_DLC_Pos (16) +#define RX_BUFFER_AND_FIFO_R1_ELEM_DLC_Msk (0xFul << RX_BUFFER_AND_FIFO_R1_ELEM_DLC_Pos) + +/* Rx Buffer and FIFO Element RXTS(Rx Timestamp) */ +#define RX_BUFFER_AND_FIFO_R1_ELEM_RXTS_Pos (0) +#define RX_BUFFER_AND_FIFO_R1_ELEM_RXTS_Msk (0xFFFFul << RX_BUFFER_AND_FIFO_R1_ELEM_RXTS_Pos) + +/* Tx Buffer Element ESI(Error State Indicator) */ +#define TX_BUFFER_T0_ELEM_ESI_Pos (31) +#define TX_BUFFER_T0_ELEM_ESI_Msk (0x1ul << TX_BUFFER_T0_ELEM_ESI_Pos) + +/* Tx Buffer Element XTD(Extended Identifier) */ +#define TX_BUFFER_T0_ELEM_XTD_Pos (30) +#define TX_BUFFER_T0_ELEM_XTD_Msk (0x1ul << TX_BUFFER_T0_ELEM_XTD_Pos) + +/* Tx Buffer RTR(Remote Transmission Request) */ +#define TX_BUFFER_T0_ELEM_RTR_Pos (29) +#define TX_BUFFER_T0_ELEM_RTR_Msk (0x1ul << TX_BUFFER_T0_ELEM_RTR_Pos) + +/* Tx Buffer Element ID(Identifier) */ +#define TX_BUFFER_T0_ELEM_ID_Pos (0) +#define TX_BUFFER_T0_ELEM_ID_Msk (0x1FFFFFFFul << TX_BUFFER_T0_ELEM_ID_Pos) + +/* Tx Buffer Element MM(Message Marker) */ +#define TX_BUFFER_T1_ELEM_MM1_Pos (24) +#define TX_BUFFER_T1_ELEM_MM1_Msk (0xFFul << TX_BUFFER_T1_ELEM_MM1_Pos) + +/* Tx Buffer Element EFC(Event FIFO Control) */ +#define TX_BUFFER_T1_ELEM_EFC_Pos (23) +#define TX_BUFFER_T1_ELEM_EFC_Msk (0xFFul << TX_BUFFER_T1_ELEM_EFC_Pos) + +/* Tx Buffer Element TSCE(Time Stamp Capture Enable for TSU) */ +#define TX_BUFFER_T1_ELEM_TSCE_Pos (22) +#define TX_BUFFER_T1_ELEM_TSCE_Msk (0x1ul << TX_BUFFER_T1_ELEM_TSCE_Pos) + +/* Tx Buffer Element FDF(FD Format) */ +#define TX_BUFFER_T1_ELEM_FDF_Pos (21) +#define TX_BUFFER_T1_ELEM_FDF_Msk (0x1ul << TX_BUFFER_T1_ELEM_FDF_Pos) + +/* Tx Buffer Element BRS(Bit Rate Swit) */ +#define TX_BUFFER_T1_ELEM_BSR_Pos (20) +#define TX_BUFFER_T1_ELEM_BSR_Msk (0x1ul << TX_BUFFER_T1_ELEM_BSR_Pos) + +/* Tx Buffer Element DLC(Bit Rate Swit) */ +#define TX_BUFFER_T1_ELEM_DLC_Pos (16) +#define TX_BUFFER_T1_ELEM_DLC_Msk (0xFul << TX_BUFFER_T1_ELEM_DLC_Pos) + +/* Tx Buffer Element MM(Message Marker) */ +#define TX_BUFFER_T1_ELEM_MM0_Pos (8) +#define TX_BUFFER_T1_ELEM_MM0_Msk (0xFFul << TX_BUFFER_T1_ELEM_MM0_Pos) + +#define CANFD_RXFS_RFL CANFD_RXF0S_RF0L_Msk + +/** @addtogroup Standard_Driver Standard Driver + @{ +*/ + +/** @addtogroup CANFD_Driver CAN_FD Driver + @{ +*/ + +/** @addtogroup CANFD_EXPORTED_FUNCTIONS CAN_FD Exported Functions + @{ +*/ + +static void CANFD_InitRxFifo(CANFD_T *canfd, uint32_t u32RxFifoNum, CANFD_RAM_PART_T *psRamConfig, CANFD_ELEM_SIZE_T *psElemSize, uint32_t u32FifoWM, E_CANFD_DATA_FIELD_SIZE eFifoSize); +static void CANFD_InitRxDBuf(CANFD_T *canfd, CANFD_RAM_PART_T *psRamConfig, CANFD_ELEM_SIZE_T *psElemSize, E_CANFD_DATA_FIELD_SIZE eRxBufSize); +static void CANFD_InitTxDBuf(CANFD_T *canfd, CANFD_RAM_PART_T *psRamConfig, CANFD_ELEM_SIZE_T *psElemSize, E_CANFD_DATA_FIELD_SIZE eTxBufSize); +static void CANFD_InitTxEvntFifo(CANFD_T *canfd, CANFD_RAM_PART_T *psRamConfig, CANFD_ELEM_SIZE_T *psElemSize, uint32_t u32FifoWaterLvl); +static void CANFD_ConfigSIDFC(CANFD_T *canfd, CANFD_RAM_PART_T *psRamConfig, CANFD_ELEM_SIZE_T *psElemSize); +static void CANFD_ConfigXIDFC(CANFD_T *canfd, CANFD_RAM_PART_T *psRamConfig, CANFD_ELEM_SIZE_T *psElemSize); + +uint32_t CANFD_ReadReg(__I uint32_t *pu32RegAddr) +{ + uint32_t u32ReadReg; + uint32_t u32TimeOutCnt = CANFD_READ_REG_TIMEOUT; + u32ReadReg = 0UL; + + do + { + u32ReadReg = inpw(pu32RegAddr); + if (--u32TimeOutCnt == 0UL) + { + break; + } + } + while (u32ReadReg == 0UL); + + return u32ReadReg; +} + +/** + * @brief Calculates the CAN FD RAM buffer address. + * + * @param[in] psConfigAddr CAN FD element star address structure. + * @param[in] psConfigSize CAN FD element size structure. + * + * @return None. + * + * @details Calculates the CAN FD RAM buffer address. + */ +static void CANFD_CalculateRamAddress(CANFD_RAM_PART_T *psConfigAddr, CANFD_ELEM_SIZE_T *psConfigSize) +{ + uint32_t u32RamAddrOffset = 0; + + /* Get the Standard Message ID Filter element address */ + if (psConfigSize->u32SIDFC > 0) + { + psConfigAddr->u32SIDFC_FLSSA = 0; + u32RamAddrOffset += psConfigSize->u32SIDFC * sizeof(CANFD_STD_FILTER_T); + } + + /* Get the Extended Message ID Filter element address */ + if (psConfigSize->u32XIDFC > 0) + { + psConfigAddr->u32XIDFC_FLESA = u32RamAddrOffset; + u32RamAddrOffset += psConfigSize->u32XIDFC * sizeof(CANFD_EXT_FILTER_T); + } + + /* Get the Rx FIFO0 element address */ + if (psConfigSize->u32RxFifo0 > 0) + { + psConfigAddr->u32RXF0C_F0SA = u32RamAddrOffset; + u32RamAddrOffset += psConfigSize->u32RxFifo0 * sizeof(CANFD_BUF_T); + } + + /* Get the Rx FIFO1 element address */ + if (psConfigSize->u32RxFifo1 > 0) + { + psConfigAddr->u32RXF1C_F1SA = u32RamAddrOffset; + u32RamAddrOffset += psConfigSize->u32RxFifo1 * sizeof(CANFD_BUF_T); + } + + /* Get the Rx Buffer element address */ + if (psConfigSize->u32RxBuf > 0) + { + psConfigAddr->u32RXBC_RBSA = u32RamAddrOffset; + u32RamAddrOffset += psConfigSize->u32RxBuf * sizeof(CANFD_BUF_T); + } + + /* Get the TX Event FIFO element address */ + if (psConfigSize->u32TxEventFifo > 0) + { + psConfigAddr->u32TXEFC_EFSA = u32RamAddrOffset; + u32RamAddrOffset += psConfigSize->u32TxEventFifo * sizeof(CANFD_EXT_FILTER_T); + } + + /* Get the Tx Buffer element address */ + if (psConfigSize->u32TxBuf > 0) + { + psConfigAddr->u32TXBC_TBSA = u32RamAddrOffset; + u32RamAddrOffset += psConfigSize->u32TxBuf * sizeof(CANFD_BUF_T); + } +} + +/** + * @brief Get the default configuration structure. + * + * @param[in] psConfig Pointer to CAN FD configuration structure. + * @param[in] u8OpMode Setting the CAN FD Operating mode. + * + * @return None. + * + * @details This function initializes the CAN FD configure structure to default value. + * The default value are: + * sNormBitRate.u32BitRate = 500000bps; + * u32DataBaudRate = 0(CAN mode) or 1000000(CAN FD mode) ; + * u32MRamSize = 8k bytes (2k words); + * bEnableLoopBack = FALSE; + * bBitRateSwitch = FALSE(CAN Mode) or TRUE(CAN FD Mode); + * bFDEn = FALSE(CAN Mode) or TRUE(CAN FD Mode); +*/ +void CANFD_GetDefaultConfig(CANFD_FD_T *psConfig, uint8_t u8OpMode) +{ + memset(psConfig, 0, sizeof(CANFD_FD_T)); + + psConfig->sBtConfig.sNormBitRate.u32BitRate = 500000; + + if (u8OpMode == CANFD_OP_CAN_MODE) + { + psConfig->sBtConfig.sDataBitRate.u32BitRate = 0; + psConfig->sBtConfig.bFDEn = FALSE; + psConfig->sBtConfig.bBitRateSwitch = FALSE; + } + else + { + psConfig->sBtConfig.sDataBitRate.u32BitRate = 10000000; + psConfig->sBtConfig.bFDEn = TRUE; + psConfig->sBtConfig.bBitRateSwitch = TRUE; + } + + /* Set normal mode by default */ + psConfig->sBtConfig.evTestMode = eCANFD_NORMAL; + + /*Get the CAN FD memory address*/ + psConfig->u32MRamSize = CANFD_SRAM_SIZE; + + /* CAN FD Standard message ID elements as 64 elements */ + psConfig->sElemSize.u32SIDFC = 64; + /* CAN FD Extended message ID elements as 64 elements */ + psConfig->sElemSize.u32XIDFC = 64; + /* CAN FD TX Buffer elements as 8 elements */ + psConfig->sElemSize.u32TxBuf = 8; + /* CAN FD RX Buffer elements as 8 elements */ + psConfig->sElemSize.u32RxBuf = 8; + /* CAN FD RX FIFO0 elements as 48 elements */ + psConfig->sElemSize.u32RxFifo0 = 48; + /* CAN FD RX FIFO1 elements as 8 elements */ + psConfig->sElemSize.u32RxFifo1 = 8; + /* CAN FD TX Event FOFI elements as 8 elements */ + psConfig->sElemSize.u32TxEventFifo = 8; + /*Calculates the CAN FD RAM buffer address*/ + CANFD_CalculateRamAddress(&psConfig->sMRamStartAddr, &psConfig->sElemSize); +} + + +/** + * @brief Encode the Data Length Code. + * + * @param[in] u8NumberOfBytes Number of bytes in a message. + * + * @return Data Length Code. + * + * @details Converts number of bytes in a message into a Data Length Code. + */ +static uint8_t CANFD_EncodeDLC(uint8_t u8NumberOfBytes) +{ + if (u8NumberOfBytes <= 8) return u8NumberOfBytes; + else if (u8NumberOfBytes <= 12) return 9; + else if (u8NumberOfBytes <= 16) return 10; + else if (u8NumberOfBytes <= 20) return 11; + else if (u8NumberOfBytes <= 24) return 12; + else if (u8NumberOfBytes <= 32) return 13; + else if (u8NumberOfBytes <= 48) return 14; + else return 15; +} + + +/** + * @brief Decode the Data Length Code. + * + * @param[in] u8Dlc Data Length Code. + * + * @return Number of bytes in a message. + * + * @details Converts a Data Length Code into a number of message bytes. + */ +static uint8_t CANFD_DecodeDLC(uint8_t u8Dlc) +{ + if (u8Dlc <= 8) return u8Dlc; + else if (u8Dlc == 9) return 12; + else if (u8Dlc == 10) return 16; + else if (u8Dlc == 11) return 20; + else if (u8Dlc == 12) return 24; + else if (u8Dlc == 13) return 32; + else if (u8Dlc == 14) return 48; + else return 64; +} + + +/** + * @brief Sets the CAN FD protocol timing characteristic. + * + * @param[in] psCanfd The pointer of the specified CANFD module. + * @param[in] psConfig Pointer to the timing configuration structure. + * + * @return None. + * + * @details This function gives user settings to CAN bus timing characteristic. + * The function is for an experienced user. For less experienced users, call + * the CANFD_Open() and fill the baud rate field with a desired value. + * This provides the default timing characteristics to the module. + */ +static void CANFD_SetTimingConfig(CANFD_T *psCanfd, const CANFD_TIMEING_CONFIG_T *psConfig) +{ + if (psCanfd == (CANFD_T *)CANFD0) + { + /* Set CANFD0 clock divider number */ + CLK->CLKDIV0 = (CLK->CLKDIV0 & ~CLK_CLKDIV0_CANFD0DIV_Msk) | CLK_CLKDIV0_CANFD0(psConfig->u8PreDivider) ; + } + else if (psCanfd == (CANFD_T *)CANFD1) + { + /* Set CANFD1 clock divider number */ + CLK->CLKDIV0 = (CLK->CLKDIV0 & ~CLK_CLKDIV0_CANFD1DIV_Msk) | CLK_CLKDIV0_CANFD1(psConfig->u8PreDivider) ; + } + else if (psCanfd == (CANFD_T *)CANFD2) + { + /* Set CANFD2 clock divider number */ + CLK->CLKDIV0 = (CLK->CLKDIV0 & ~CLK_CLKDIV0_CANFD2DIV_Msk) | CLK_CLKDIV0_CANFD2(psConfig->u8PreDivider) ; + } + else if (psCanfd == (CANFD_T *)CANFD3) + { + /* Set CANFD3 clock divider number */ + CLK->CLKDIV0 = (CLK->CLKDIV0 & ~CLK_CLKDIV0_CANFD3DIV_Msk) | CLK_CLKDIV0_CANFD3(psConfig->u8PreDivider) ; + } + else + { + return; + } + + /* configuration change enable */ + psCanfd->CCCR |= CANFD_CCCR_CCE_Msk; + + /* nominal bit rate */ + psCanfd->NBTP = (((psConfig->u8NominalRJumpwidth & 0x7F) - 1) << 25) + + (((psConfig->u16NominalPrescaler & 0x1FF) - 1) << 16) + + ((((psConfig->u8NominalPhaseSeg1 + psConfig->u8NominalPropSeg) & 0xFF) - 1) << 8) + + (((psConfig->u8NominalPhaseSeg2 & 0x7F) - 1) << 0); + + + /* canfd->DBTP */ + if (psCanfd->CCCR & CANFD_CCCR_FDOE_Msk) + { + psCanfd->DBTP = (((psConfig->u8DataPrescaler & 0x1F) - 1) << 16) + + ((((psConfig->u8DataPhaseSeg1 + psConfig->u8DataPropSeg) & 0x1F) - 1) << 8) + + (((psConfig->u8DataPhaseSeg2 & 0xF) - 1) << 4) + + (((psConfig->u8DataRJumpwidth & 0xF) - 1) << 0); + } +} + + +/** + * @brief Get the segment values. + * + * @param[in] u32NominalBaudRate The nominal speed in bps. + * @param[in] u32DataBaudRate The data speed in bps. + * @param[in] u32Ntq Number of nominal time quanta per bit. + * @param[in] u32Dtq Number of data time quanta per bit. + * @param[in] psConfig Passed is a configuration structure, on return the configuration is stored in the structure + * + * @return None. + * + * @details Calculates the segment values for a single bit time for nominal and data baudrates. + */ +static void CANFD_GetSegments(uint32_t u32NominalBaudRate, uint32_t u32DataBaudRate, uint32_t u32Ntq, uint32_t u32Dtq, CANFD_TIMEING_CONFIG_T *psConfig) +{ + float ideal_sp; + int int32P1; + + /* get ideal sample point */ + if (u32NominalBaudRate >= 1000000) ideal_sp = 0.750; + else if (u32NominalBaudRate >= 800000) ideal_sp = 0.800; + else ideal_sp = 0.875; + + /* distribute time quanta */ + int32P1 = (int)(u32Ntq * ideal_sp); + /* can controller doesn't separate prop seg and phase seg 1 */ + psConfig->u8NominalPropSeg = 0; + /* subtract one TQ for sync seg */ + psConfig->u8NominalPhaseSeg1 = int32P1 - 1; + psConfig->u8NominalPhaseSeg2 = u32Ntq - int32P1; + /* sjw is 20% of total TQ, rounded to nearest int */ + psConfig->u8NominalRJumpwidth = (u32Ntq + (5 - 1)) / 5; + + + /* if using baud rate switching then distribute time quanta for data rate */ + if (u32Dtq > 0) + { + /* get ideal sample point */ + if (u32DataBaudRate >= 1000000) ideal_sp = 0.750; + else if (u32DataBaudRate >= 800000) ideal_sp = 0.800; + else ideal_sp = 0.875; + + /* distribute time quanta */ + int32P1 = (int)(u32Dtq * ideal_sp); + /* can controller doesn't separate prop seg and phase seg 1 */ + psConfig->u8DataPropSeg = 0; + /* subtract one TQ for sync seg */ + psConfig->u8DataPhaseSeg1 = int32P1 - 1; + psConfig->u8DataPhaseSeg2 = u32Dtq - int32P1; + /* sjw is 20% of total TQ, rounded to nearest int */ + psConfig->u8DataRJumpwidth = (u32Dtq + (5 - 1)) / 5; + } + else + { + psConfig->u8DataPropSeg = 0; + psConfig->u8DataPhaseSeg1 = 0; + psConfig->u8DataPhaseSeg2 = 0; + psConfig->u8DataRJumpwidth = 0; + } +} + + +/** + * @brief Calculates the CAN controller timing values for specific baudrates. + * + * @param[in] u32NominalBaudRate The nominal speed in bps. + * @param[in] u32DataBaudRate The data speed in bps. Zero to disable baudrate switching. + * @param[in] u32SourceClock_Hz CAN FD Protocol Engine clock source frequency in Hz. + * @param[in] psConfig Passed is a configuration structure, on return the configuration is stored in the structure + * + * @return true if timing configuration found, false if failed to find configuration. + * + * @details Calculates the CAN controller timing values for specific baudrates. + */ +static uint32_t CANFD_CalculateTimingValues(CANFD_T *psCanfd, uint32_t u32NominalBaudRate, uint32_t u32DataBaudRate, uint32_t u32SourceClock_Hz, CANFD_TIMEING_CONFIG_T *psConfig) +{ + int i32Nclk; + int i32Nclk2; + int i32Ntq; + int i32Dclk; + int i32Dclk2; + int i32Dtq; + + /* observe baud rate maximums */ + if (u32NominalBaudRate > MAX_NOMINAL_BAUDRATE) u32NominalBaudRate = MAX_NOMINAL_BAUDRATE; + + for (i32Ntq = MAX_TIME_QUANTA; i32Ntq >= MIN_TIME_QUANTA; i32Ntq--) + { + i32Nclk = u32NominalBaudRate * i32Ntq; + + for (psConfig->u16NominalPrescaler = 0x001; psConfig->u16NominalPrescaler <= 0x400; (psConfig->u16NominalPrescaler)++) + { + i32Nclk2 = i32Nclk * psConfig->u16NominalPrescaler; + + if (((u32SourceClock_Hz / i32Nclk2) <= 5) && ((u32SourceClock_Hz % i32Nclk2) == 0)) + { + psConfig->u8PreDivider = u32SourceClock_Hz / i32Nclk2; + + /* FD Operation? */ + if (psCanfd->CCCR & CANFD_CCCR_FDOE_Msk) + { + /* Exception case: Let u32DataBaudRate is same with u32NominalBaudRate. */ + if (u32DataBaudRate == 0) + u32DataBaudRate = u32NominalBaudRate; + + /* if baudrates are the same and the solution for nominal will work for + data, then use the nominal settings for both */ + if ((u32DataBaudRate == u32NominalBaudRate) && (psConfig->u16NominalPrescaler <= 0x20)) + { + i32Dtq = i32Ntq; + psConfig->u8DataPrescaler = (uint8_t)psConfig->u16NominalPrescaler; + CANFD_GetSegments(u32NominalBaudRate, u32DataBaudRate, i32Ntq, i32Dtq, psConfig); + return TRUE; + } + + /* calculate data settings */ + for (i32Dtq = MAX_TIME_QUANTA; i32Dtq >= MIN_TIME_QUANTA; i32Dtq--) + { + i32Dclk = u32DataBaudRate * i32Dtq; + + for (psConfig->u8DataPrescaler = 0x01; psConfig->u8DataPrescaler <= 0x20; (psConfig->u8DataPrescaler)++) + { + i32Dclk2 = i32Dclk * psConfig->u8DataPrescaler; + if (u32SourceClock_Hz == ((uint32_t)i32Dclk2 * psConfig->u8PreDivider)) + { + CANFD_GetSegments(u32NominalBaudRate, u32DataBaudRate, i32Ntq, i32Dtq, psConfig); + return TRUE; + } + } + } + } + else + { + psConfig->u8DataPrescaler = 0; + CANFD_GetSegments(u32NominalBaudRate, 0, 0, 0, psConfig); + return TRUE; + } + } + } + } + + /* failed to find solution */ + return FALSE; +} + + +/** + * @brief Config message ram and Set bit-time. + * + * @param[in] psCanfd The pointer to CAN FD module base address. + * @param[in] psCanfdStr message ram setting and bit-time setting + * + * @return None. + * + * @details Converts a Data Length Code into a number of message bytes. + */ +void CANFD_Open(CANFD_T *psCanfd, CANFD_FD_T *psCanfdStr) +{ + uint32_t u32SrcCLK; + uint32_t u32RegLockLevel = SYS_IsRegLocked(); + + if (u32RegLockLevel) + SYS_UnlockReg(); + + if (psCanfd == (CANFD_T *)CANFD0) + { + CLK_EnableModuleClock(CANFD0_MODULE); + SYS_ResetModule(CANFD0_RST); + if (CLK_GetModuleClockSource(CANFD0_MODULE) == 1) + { + u32SrcCLK = CLK_GetPLLClockFreq(VPLL); + } + else + { + u32SrcCLK = CLK_GetPLLClockFreq(APLL); + } + } + else if (psCanfd == (CANFD_T *)CANFD1) + { + CLK_EnableModuleClock(CANFD1_MODULE); + SYS_ResetModule(CANFD1_RST); + if (CLK_GetModuleClockSource(CANFD1_MODULE) == 1) + { + u32SrcCLK = CLK_GetPLLClockFreq(VPLL); + } + else + { + u32SrcCLK = CLK_GetPLLClockFreq(APLL); + } + } + else if (psCanfd == (CANFD_T *)CANFD2) + { + CLK_EnableModuleClock(CANFD2_MODULE); + SYS_ResetModule(CANFD2_RST); + if (CLK_GetModuleClockSource(CANFD2_MODULE) == 1) + { + u32SrcCLK = CLK_GetPLLClockFreq(VPLL); + } + else + { + u32SrcCLK = CLK_GetPLLClockFreq(APLL); + } + } + else if (psCanfd == (CANFD_T *)CANFD3) + { + CLK_EnableModuleClock(CANFD3_MODULE); + SYS_ResetModule(CANFD3_RST); + if (CLK_GetModuleClockSource(CANFD3_MODULE) == 1) + { + u32SrcCLK = CLK_GetPLLClockFreq(VPLL); + } + else + { + u32SrcCLK = CLK_GetPLLClockFreq(APLL); + } + } + else + { + if (u32RegLockLevel) + SYS_LockReg(); + + return; + } + + /* Initialization & un-lock */ + CANFD_RunToNormal(psCanfd, FALSE); + + if (psCanfdStr->sBtConfig.bBitRateSwitch) + { + /* enable FD and baud-rate switching */ + psCanfd->CCCR |= CANFD_CCCR_BRSE_Msk; + } + + if (psCanfdStr->sBtConfig.bFDEn) + { + /*FD Operation enabled*/ + psCanfd->CCCR |= CANFD_CCCR_FDOE_Msk; + } + + /*Clear the Rx Fifo0 element setting */ + psCanfd->RXF0C = 0; + /*Clear the Rx Fifo1 element setting */ + psCanfd->RXF1C = 0; + + /* calculate and apply timing */ + if (CANFD_CalculateTimingValues(psCanfd, psCanfdStr->sBtConfig.sNormBitRate.u32BitRate, psCanfdStr->sBtConfig.sDataBitRate.u32BitRate, + u32SrcCLK, &psCanfdStr->sBtConfig.sConfigBitTing)) + { + CANFD_SetTimingConfig(psCanfd, &psCanfdStr->sBtConfig.sConfigBitTing); + } + + if (u32RegLockLevel) + SYS_LockReg(); + + /* Configures the Standard ID Filter element */ + if (psCanfdStr->sElemSize.u32SIDFC != 0) + CANFD_ConfigSIDFC(psCanfd, &psCanfdStr->sMRamStartAddr, &psCanfdStr->sElemSize); + + /*Configures the Extended ID Filter element */ + if (psCanfdStr->sElemSize.u32XIDFC != 0) + CANFD_ConfigXIDFC(psCanfd, &psCanfdStr->sMRamStartAddr, &psCanfdStr->sElemSize); + + /*Configures the Tx Buffer element */ + if (psCanfdStr->sElemSize.u32RxBuf != 0) + CANFD_InitTxDBuf(psCanfd, &psCanfdStr->sMRamStartAddr, &psCanfdStr->sElemSize, eCANFD_BYTE64); + + /*Configures the Rx Buffer element */ + if (psCanfdStr->sElemSize.u32RxBuf != 0) + CANFD_InitRxDBuf(psCanfd, &psCanfdStr->sMRamStartAddr, &psCanfdStr->sElemSize, eCANFD_BYTE64); + + /*Configures the Rx Fifo0 element */ + if (psCanfdStr->sElemSize.u32RxFifo0 != 0) + CANFD_InitRxFifo(psCanfd, 0, &psCanfdStr->sMRamStartAddr, &psCanfdStr->sElemSize, 0, eCANFD_BYTE64); + + /*Configures the Rx Fifo1 element */ + if (psCanfdStr->sElemSize.u32RxFifo1 != 0) + CANFD_InitRxFifo(psCanfd, 1, &psCanfdStr->sMRamStartAddr, &psCanfdStr->sElemSize, 0, eCANFD_BYTE64); + + /*Configures the Tx Event FIFO element */ + if (psCanfdStr->sElemSize.u32TxEventFifo != 0) + CANFD_InitTxEvntFifo(psCanfd, &psCanfdStr->sMRamStartAddr, &psCanfdStr->sElemSize, 0); + + /*Reject all Non-matching Frames Extended ID and Frames Standard ID,Reject all remote frames with 11-bit standard IDs and 29-bit extended IDs */ + CANFD_SetGFC(psCanfd, eCANFD_REJ_NON_MATCH_FRM, eCANFD_REJ_NON_MATCH_FRM, 1, 1); + + /* Test mode configuration */ + switch (psCanfdStr->sBtConfig.evTestMode) + { + case eCANFD_RESTRICTED_OPERATION: + psCanfd->CCCR |= (CANFD_CCCR_TEST_Msk | CANFD_CCCR_ASM_Msk); + break; + + case eCANFD_BUS_MONITOR: + psCanfd->CCCR |= (CANFD_CCCR_TEST_Msk | CANFD_CCCR_MON_Msk); + break; + + case eCANFD_LOOPBACK_EXTERNAL: + psCanfd->CCCR |= CANFD_CCCR_TEST_Msk; + psCanfd->TEST |= CANFD_TEST_LBCK_Msk; + break; + + case eCANFD_LOOPBACK_INTERNAL: + psCanfd->CCCR |= (CANFD_CCCR_TEST_Msk | CANFD_CCCR_MON_Msk); + psCanfd->TEST |= CANFD_TEST_LBCK_Msk; + break; + + case eCANFD_NORMAL: /* Normal mode */ + default: + psCanfd->CCCR &= ~(CANFD_CCCR_MON_Msk | CANFD_CCCR_TEST_Msk | CANFD_CCCR_ASM_Msk); + psCanfd->TEST &= ~CANFD_TEST_LBCK_Msk; + break; + } +} + + +/** + * @brief Close the CAN FD Bus. + * + * @param[in] psCanfd The pointer to CANFD module base address. + * + * @return None. + * + * @details Disable the CAN FD clock and Interrupt. + */ +void CANFD_Close(CANFD_T *psCanfd) +{ + if (psCanfd == (CANFD_T *)CANFD0) + { + CLK_DisableModuleClock(CANFD0_MODULE); + } + else if (psCanfd == (CANFD_T *)CANFD1) + { + CLK_DisableModuleClock(CANFD1_MODULE); + } + else if (psCanfd == (CANFD_T *)CANFD2) + { + CLK_DisableModuleClock(CANFD2_MODULE); + } + else if (psCanfd == (CANFD_T *)CANFD3) + { + CLK_DisableModuleClock(CANFD3_MODULE); + } +} + + +/** + * @brief Get the element's address when read transmit buffer. + * + * @param[in] psCanfd The pointer of the specified CAN FD module. + * @param[in] u32Idx The number of the transmit buffer element + * + * @return Address of the element in transmit buffer. + * + * @details The function is used to get the element's address when read transmit buffer. + */ +static uint32_t CANFD_GetTxBufferElementAddress(CANFD_T *psCanfd, uint32_t u32Idx) +{ + uint32_t u32Size = 0; + u32Size = (CANFD_ReadReg(&psCanfd->TXESC) & CANFD_TXESC_TBDS_Msk) >> CANFD_TXESC_TBDS_Pos; + + if (u32Size < 5U) + { + u32Size += 4U; + } + else + { + u32Size = u32Size * 4U - 10U; + } + + return (CANFD_ReadReg(&psCanfd->TXBC) & CANFD_TXBC_TBSA_Msk) + u32Idx * u32Size * 4U; +} + +/** + * @brief Enables CAN FD interrupts according to provided mask . + * + * @param[in] psCanfd The pointer of the specified CAN FD module. + * @param[in] u32IntLine0 The Interrupt Line 0 type select. + * @param[in] u32IntLine1 The Interrupt Line 1 type select. + * - \ref CANFD_IE_ARAE_Msk : Access to Reserved Address Interrupt + * - \ref CANFD_IE_PEDE_Msk : Protocol Error in Data Phase Interrupt + * - \ref CANFD_IE_PEAE_Msk : Protocol Error in Arbitration Phase Interrupt + * - \ref CANFD_IE_WDIE_Msk : Watchdog Interrupt + * - \ref CANFD_IE_BOE_Msk : Bus_Off Status Interrupt + * - \ref CANFD_IE_EWE_Msk : Warning Status Interrupt + * - \ref CANFD_IE_EPE_Msk : Error Passive Interrupt + * - \ref CANFD_IE_ELOE_Msk : Error Logging Overflow Interrupt + * - \ref CANFD_IE_BEUE_Msk : Bit Error Uncorrected Interrupt + * - \ref CANFD_IE_BECE_Msk : Bit Error Corrected Interrupt + * - \ref CANFD_IE_DRXE_Msk : Message stored to Dedicated Rx Buffer Interrupt + * - \ref CANFD_IE_TOOE_Msk : Timeout Occurred Interrupt + * - \ref CANFD_IE_MRAFE_Msk : Message RAM Access Failure Interrupt + * - \ref CANFD_IE_TSWE_Msk : Timestamp Wraparound Interrupt + * - \ref CANFD_IE_TEFLE_Msk : Tx Event FIFO Event Lost Interrupt + * - \ref CANFD_IE_TEFFE_Msk : Tx Event FIFO Full Interrupt + * - \ref CANFD_IE_TEFWE_Msk : Tx Event FIFO Watermark Reached Interrupt + * - \ref CANFD_IE_TEFNE_Msk : Tx Event FIFO New Entry Interrupt + * - \ref CANFD_IE_TFEE_Msk : Tx FIFO Empty Interrupt + * - \ref CANFD_IE_TCFE_Msk : Transmission Cancellation Finished Interrupt + * - \ref CANFD_IE_TCE_Msk : Transmission Completed Interrupt + * - \ref CANFD_IE_HPME_Msk : High Priority Message Interrupt + * - \ref CANFD_IE_RF1LE_Msk : Rx FIFO 1 Message Lost Interrupt + * - \ref CANFD_IE_RF1FE_Msk : Rx FIFO 1 Full Interrupt + * - \ref CANFD_IE_RF1WE_Msk : Rx FIFO 1 Watermark Reached Interrupt + * - \ref CANFD_IE_RF1NE_Msk : Rx FIFO 1 New Message Interrupt + * - \ref CANFD_IE_RF0LE_Msk : Rx FIFO 0 Message Lost Interrupt + * - \ref CANFD_IE_RF0FE_Msk : Rx FIFO 0 Full Interrupt + * - \ref CANFD_IE_RF0WE_Msk : Rx FIFO 0 Watermark Reached Interrupt + * - \ref CANFD_IE_RF0NE_Msk : Rx FIFO 0 New Message Interrupt + * + * @param[in] u32TXBTIE Enable Tx Buffer Transmission 0-31 Interrupt. + * @param[in] u32TXBCIE Enable Tx Buffer Cancellation Finished 0-31 Interrupt. + * @return None. + * + * @details This macro enable specified CAN FD interrupt. + */ +void CANFD_EnableInt(CANFD_T *psCanfd, uint32_t u32IntLine0, uint32_t u32IntLine1, uint32_t u32TXBTIE, uint32_t u32TXBCIE) +{ + /*Setting the CANFD Interrupt Enabling*/ + psCanfd->IE = CANFD_ReadReg(&psCanfd->IE) | u32IntLine0 | u32IntLine1; + + if (u32IntLine0 != 0) + { + /* Select specified interrupt event of Line0. */ + psCanfd->ILS = CANFD_ReadReg(&psCanfd->ILS) & ~u32IntLine0; + /* Enable Line0 interrupt. */ + psCanfd->ILE = CANFD_ReadReg(&psCanfd->ILE) | CANFD_ILE_ENT0_Msk; + } + + if (u32IntLine1 != 0) + { + /* Select specified interrupt event of Line1. */ + psCanfd->ILS = CANFD_ReadReg(&psCanfd->ILS) | u32IntLine1; + /* Enable Line1 interrupt. */ + psCanfd->ILE = CANFD_ReadReg(&psCanfd->ILE) | CANFD_ILE_ENT1_Msk; + } + + /*Setting the Tx Buffer Transmission Interrupt Enable*/ + psCanfd->TXBTIE = CANFD_ReadReg(&psCanfd->TXBTIE) | u32TXBTIE; + + /*Tx Buffer Cancellation Finished Interrupt Enable*/ + psCanfd->TXBCIE = CANFD_ReadReg(&psCanfd->TXBCIE) | u32TXBCIE; +} + + +/** + * @brief Disables CAN FD interrupts according to provided mask . + * + * @param[in] psCanfd The pointer of the specified CAN FD module. + * @param[in] u32IntLine0 The Interrupt Line 0 type select. + * @param[in] u32IntLine1 The Interrupt Line 1 type select. + * - \ref CANFD_IE_ARAE_Msk : Access to Reserved Address Interrupt + * - \ref CANFD_IE_PEDE_Msk : Protocol Error in Data Phase Interrupt + * - \ref CANFD_IE_PEAE_Msk : Protocol Error in Arbitration Phase Interrupt + * - \ref CANFD_IE_WDIE_Msk : Watchdog Interrupt + * - \ref CANFD_IE_BOE_Msk : Bus_Off Status Interrupt + * - \ref CANFD_IE_EWE_Msk : Warning Status Interrupt + * - \ref CANFD_IE_EPE_Msk : Error Passive Interrupt + * - \ref CANFD_IE_ELOE_Msk : Error Logging Overflow Interrupt + * - \ref CANFD_IE_BEUE_Msk : Bit Error Uncorrected Interrupt + * - \ref CANFD_IE_BECE_Msk : Bit Error Corrected Interrupt + * - \ref CANFD_IE_DRXE_Msk : Message stored to Dedicated Rx Buffer Interrupt + * - \ref CANFD_IE_TOOE_Msk : Timeout Occurred Interrupt + * - \ref CANFD_IE_MRAFE_Msk : Message RAM Access Failure Interrupt + * - \ref CANFD_IE_TSWE_Msk : Timestamp Wraparound Interrupt + * - \ref CANFD_IE_TEFLE_Msk : Tx Event FIFO Event Lost Interrupt + * - \ref CANFD_IE_TEFFE_Msk : Tx Event FIFO Full Interrupt + * - \ref CANFD_IE_TEFWE_Msk : Tx Event FIFO Watermark Reached Interrupt + * - \ref CANFD_IE_TEFNE_Msk : Tx Event FIFO New Entry Interrupt + * - \ref CANFD_IE_TFEE_Msk : Tx FIFO Empty Interrupt + * - \ref CANFD_IE_TCFE_Msk : Transmission Cancellation Finished Interrupt + * - \ref CANFD_IE_TCE_Msk : Transmission Completed Interrupt + * - \ref CANFD_IE_HPME_Msk : High Priority Message Interrupt + * - \ref CANFD_IE_RF1LE_Msk : Rx FIFO 1 Message Lost Interrupt + * - \ref CANFD_IE_RF1FE_Msk : Rx FIFO 1 Full Interrupt + * - \ref CANFD_IE_RF1WE_Msk : Rx FIFO 1 Watermark Reached Interrupt + * - \ref CANFD_IE_RF1NE_Msk : Rx FIFO 1 New Message Interrupt + * - \ref CANFD_IE_RF0LE_Msk : Rx FIFO 0 Message Lost Interrupt + * - \ref CANFD_IE_RF0FE_Msk : Rx FIFO 0 Full Interrupt + * - \ref CANFD_IE_RF0WE_Msk : Rx FIFO 0 Watermark Reached Interrupt + * - \ref CANFD_IE_RF0NE_Msk : Rx FIFO 0 New Message Interrupt + * + * @param[in] u32TXBTIE Disable Tx Buffer Transmission 0-31 Interrupt. + * @param[in] u32TXBCIE Disable Tx Buffer Cancellation Finished 0-31 Interrupt. + * @return None. + * + * @details This macro disable specified CAN FD interrupt. + */ +void CANFD_DisableInt(CANFD_T *psCanfd, uint32_t u32IntLine0, uint32_t u32IntLine1, uint32_t u32TXBTIE, uint32_t u32TXBCIE) +{ + psCanfd->IE = CANFD_ReadReg(&psCanfd->IE) & ~(u32IntLine0 | u32IntLine1); + + if (u32IntLine0 != 0) + { + /* Cancel specified interrupt event of Line0. */ + psCanfd->ILS = CANFD_ReadReg(&psCanfd->ILS) | u32IntLine0; + } + if (CANFD_ReadReg(&psCanfd->ILS) == ~0) + { + /* Disable Line0 interrupt */ + psCanfd->ILE = CANFD_ReadReg(&psCanfd->ILE) & ~CANFD_ILE_ENT0_Msk; + } + + if (u32IntLine1 != 0) + { + /* Select specified interrupt event of Line1. */ + psCanfd->ILS = CANFD_ReadReg(&psCanfd->ILS) & ~u32IntLine1; + } + if (CANFD_ReadReg(&psCanfd->ILS) == 0) + { + /* Disable Line1 interrupt */ + psCanfd->ILE = CANFD_ReadReg(&psCanfd->ILE) & ~CANFD_ILE_ENT1_Msk; + } + + /*Setting the Tx Buffer Transmission Interrupt Disable*/ + psCanfd->TXBTIE = CANFD_ReadReg(&psCanfd->TXBTIE) & ~u32TXBTIE; + + /*Tx Buffer Cancellation Finished Interrupt Disable*/ + psCanfd->TXBCIE = CANFD_ReadReg(&psCanfd->TXBCIE) & ~u32TXBCIE; +} + + +/** + * @brief Copy Tx Message to TX buffer and Request transmission. + * + * @param[in] psCanfd The pointer to CAN FD module base address. + * @param[in] u32TxBufIdx The Message Buffer index. + * @param[in] psTxMsg Message to be copied. + * + * @return number of tx requests set: 0= Tx Message Buffer is currently in use. + * 1= Write Tx Message Buffer Successfully. + * + * @details Copy Tx Message to FIFO/Queue TX buffer and Request transmission. + */ +uint32_t CANFD_TransmitTxMsg(CANFD_T *psCanfd, uint32_t u32TxBufIdx, CANFD_FD_MSG_T *psTxMsg) +{ + uint32_t u32Success = 0; + uint32_t u32TimeOutCnt = CANFD_TIMEOUT; + + /* write the message to the message buffer */ + u32Success = CANFD_TransmitDMsg(psCanfd, u32TxBufIdx, psTxMsg); + + if (u32Success == 1) + { + /* wait for completion */ + while (!(psCanfd->TXBRP & (1UL << u32TxBufIdx))) + { + if (--u32TimeOutCnt == 0) + { + u32Success = 0; + break; + } + + } + } + + return u32Success; +} + + +/** + * @brief Writes a Tx Message to Transmit Message Buffer. + * + * @param[in] psCanfd The pointer of the specified CAN FD module. + * @param[in] u32TxBufIdx The Message Buffer index. + * @param[in] psTxMsg Pointer to CAN FD message frame to be sent. + * + * @return 1 Write Tx Message Buffer Successfully. + * 0 Tx Message Buffer is currently in use. + * + * @details This function writes a CANFD Message to the specified Transmit Message Buffer + * and changes the Message Buffer state to start CANFD Message transmit. After + * that the function returns immediately. + */ +uint32_t CANFD_TransmitDMsg(CANFD_T *psCanfd, uint32_t u32TxBufIdx, CANFD_FD_MSG_T *psTxMsg) +{ + CANFD_BUF_T *psTxBuffer; + uint32_t u32Idx = 0, u32Success = 1; + uint32_t u32TimeOutCnt = CANFD_TIMEOUT; + + if (u32TxBufIdx >= CANFD_MAX_TX_BUF_ELEMS) return 0; + + /* transmission is pending in this message buffer */ + if (CANFD_ReadReg(&(psCanfd->TXBRP)) & (1UL << u32TxBufIdx)) return 0; + + /*Get the TX Buffer Start Address in the RAM*/ + psTxBuffer = (CANFD_BUF_T *)(CANFD_SRAM_BASE_ADDR(psCanfd) + (CANFD_ReadReg(&psCanfd->TXBC) & 0xFFFF) + (u32TxBufIdx * sizeof(CANFD_BUF_T))); + + if (psTxMsg->eIdType == eCANFD_XID) + { + psTxBuffer->u32Id = TX_BUFFER_T0_ELEM_XTD_Msk | (psTxMsg->u32Id & 0x1FFFFFFF); + } + else + { + psTxBuffer->u32Id = (psTxMsg->u32Id & 0x7FF) << 18; + } + + if (psTxMsg->eFrmType == eCANFD_REMOTE_FRM) psTxBuffer->u32Id |= TX_BUFFER_T0_ELEM_RTR_Msk; + + psTxBuffer->u32Config = (CANFD_EncodeDLC(psTxMsg->u32DLC) << 16); + + if (psTxMsg->bFDFormat) psTxBuffer->u32Config |= TX_BUFFER_T1_ELEM_FDF_Msk; + + if (psTxMsg->bBitRateSwitch) psTxBuffer->u32Config |= TX_BUFFER_T1_ELEM_BSR_Msk; + + + for (u32Idx = 0; u32Idx < (psTxMsg->u32DLC + (4 - 1)) / 4; u32Idx++) + { + psTxBuffer->au32Data[u32Idx] = psTxMsg->au32Data[u32Idx]; + } + + while (CANFD_GET_COMMUNICATION_STATE(psCanfd) != eCANFD_IDLE) + { + if (--u32TimeOutCnt == 0) return 0; + } + + psCanfd->TXBAR = (1 << u32TxBufIdx); + + return u32Success; +} + + +/** + * @brief Global Filter Configuration (GFC). + * + * @param[in] psCanfd The pointer to CAN FD module base address. + * @param[in] eNMStdFrm Accept/Reject Non-Matching Standard(11-bits) Frames. + * @param[in] eEMExtFrm Accept/Reject Non-Matching Extended(29-bits) Frames. + * @param[in] u32RejRmtStdFrm Reject/Filter Remote Standard Frames. + * @param[in] u32RejRmtExtFrm Reject/Filter Remote Extended Frames. + * + * @return None. + * + * @details Global Filter Configuration. + */ +void CANFD_SetGFC(CANFD_T *psCanfd, E_CANFD_ACC_NON_MATCH_FRM eNMStdFrm, E_CANFD_ACC_NON_MATCH_FRM eEMExtFrm, uint32_t u32RejRmtStdFrm, uint32_t u32RejRmtExtFrm) +{ + psCanfd->GFC &= ~(CANFD_GFC_ANFS_Msk | CANFD_GFC_ANFE_Msk | CANFD_GFC_RRFS_Msk | CANFD_GFC_RRFE_Msk); + psCanfd->GFC = (eNMStdFrm << CANFD_GFC_ANFS_Pos) | + (eEMExtFrm << CANFD_GFC_ANFE_Pos) | + (u32RejRmtStdFrm << CANFD_GFC_RRFS_Pos) | + (u32RejRmtExtFrm << CANFD_GFC_RRFE_Pos); +} + + +/** + * @brief Rx FIFO Configuration for RX_FIFO_0 and RX_FIFO_1. + * + * @param[in] psCanfd The pointer to CAN FD module base address. + * @param[in] u32RxFifoNum 0: RX FIFO_0, 1: RX_FIFO_1. + * @param[in] psRamConfig Rx FIFO Size in number of configuration ram address. + * @param[in] psElemSize Rx FIFO Size in number of Rx FIFO elements (element number (max. = 64)). + * @param[in] u32FifoWM Watermark in number of Rx FIFO elements + * @param[in] eFifoSize Maximum data field size that should be stored in this Rx FIFO + * (configure BYTE64 if you are unsure, as this is the largest data field allowed in CAN FD) + * + * @return None. + * + * @details Rx FIFO Configuration for RX_FIFO_0 and RX_FIFO_1. + */ +static void CANFD_InitRxFifo(CANFD_T *psCanfd, uint32_t u32RxFifoNum, CANFD_RAM_PART_T *psRamConfig, CANFD_ELEM_SIZE_T *psElemSize, uint32_t u32FifoWM, E_CANFD_DATA_FIELD_SIZE eFifoSize) +{ + uint32_t u32Address; + uint32_t u32Size; + + /* ignore if index is too high */ + if (u32RxFifoNum > CANFD_NUM_RX_FIFOS)return; + + /* ignore if index is too high */ + if (psElemSize-> u32RxFifo0 > CANFD_MAX_RX_FIFO0_ELEMS) return; + + /* ignore if index is too high */ + if (psElemSize-> u32RxFifo1 > CANFD_MAX_RX_FIFO1_ELEMS) return; + + switch (u32RxFifoNum) + { + case 0: + if (psElemSize-> u32RxFifo0) + { + /* set size of Rx FIFO 0, set offset, blocking mode */ + psCanfd->RXF0C = (psRamConfig->u32RXF0C_F0SA) | (psElemSize->u32RxFifo0 << CANFD_RXF0C_F0S_Pos) + | (u32FifoWM << CANFD_RXF0C_F0WM_Pos); + psCanfd->RXESC = (psCanfd->RXESC & (~CANFD_RXESC_F0DS_Msk)) | (eFifoSize << CANFD_RXESC_F0DS_Pos); + + /*Get the RX FIFO 0 Start Address in the RAM*/ + u32Address = CANFD_SRAM_BASE_ADDR(psCanfd) + (psRamConfig->u32RXF0C_F0SA & CANFD_RXF0C_F0SA_Msk); + u32Size = eFifoSize; + + if (u32Size < 5U) + { + u32Size += 4U; + } + else + { + u32Size = u32Size * 4U - 10U; + } + + /*Clear the RX FIFO 0 Memory*/ + memset((uint32_t *)(u32Address), 0x00, (u32Size * 4 * psElemSize->u32RxFifo0)); + } + else + { + psCanfd->RXF0C = 0; + } + + break; + + case 1: + if (psElemSize-> u32RxFifo1) + { + /* set size of Rx FIFO 1, set offset, blocking mode */ + psCanfd->RXF1C = (psRamConfig->u32RXF1C_F1SA) | (psElemSize->u32RxFifo1 << CANFD_RXF1C_F1S_Pos) + | (u32FifoWM << CANFD_RXF1C_F1WM_Pos); + psCanfd->RXESC = (psCanfd->RXESC & (~CANFD_RXESC_F1DS_Msk)) | (eFifoSize << CANFD_RXESC_F1DS_Pos); + + /*Get the RX FIFO 1 Start Address in the RAM*/ + u32Address = CANFD_SRAM_BASE_ADDR(psCanfd) + (psRamConfig->u32RXF1C_F1SA & CANFD_RXF1C_F1SA_Msk); + + u32Size = eFifoSize; + + if (u32Size < 5U) + { + u32Size += 4U; + } + else + { + u32Size = u32Size * 4U - 10U; + } + + /*Clear the RX FIFO 0 Memory*/ + memset((uint32_t *)(u32Address), 0x00, (u32Size * 4 * psElemSize->u32RxFifo1)); + } + else + { + psCanfd->RXF1C = 0; + } + + break; + } +} + + +/** + * @brief Function configures the data structures used by a dedicated Rx Buffer. + * + * @param[in] psCanfd The pointer to CAN FD module base address. + * @param[in] psRamConfig Tx buffer configuration ram address. + * @param[in] psElemSize Tx buffer configuration element size. + * @param[in] eTxBufSize Maximum data field size that should be stored in a dedicated Tx Buffer + * (configure BYTE64 if you are unsure, as this is the largest data field allowed in CAN FD)largest data field allowed in CAN FD) + * + * @return None. + * + * @details Function configures the data structures used by a dedicated Rx Buffer. + */ +static void CANFD_InitTxDBuf(CANFD_T *psCanfd, CANFD_RAM_PART_T *psRamConfig, CANFD_ELEM_SIZE_T *psElemSize, E_CANFD_DATA_FIELD_SIZE eTxBufSize) +{ + uint32_t u32Address; + uint32_t u32Size; + + /*Setting the Tx Buffer Start Address*/ + psCanfd->TXBC = ((psElemSize->u32TxBuf & 0x3F) << CANFD_TXBC_NDTB_Pos) | (psRamConfig->u32TXBC_TBSA & CANFD_TXBC_TBSA_Msk); + + /*Get the TX Buffer Start Address in the RAM*/ + u32Address = CANFD_SRAM_BASE_ADDR(psCanfd) + (psRamConfig->u32TXBC_TBSA & CANFD_TXBC_TBSA_Msk); + + /*Setting the Tx Buffer Data Field Size*/ + psCanfd->TXESC = (psCanfd->TXESC & (~CANFD_TXESC_TBDS_Msk)) | (eTxBufSize << CANFD_TXESC_TBDS_Pos); + + /*Get the Buffer Data Field Size*/ + u32Size = eTxBufSize; + + if (u32Size < 5U) + { + u32Size += 4U; + } + else + { + u32Size = u32Size * 4U - 10U; + } + + /*Clear the TX Buffer Memory*/ + memset((uint32_t *)(u32Address), 0x00, (u32Size * 4 * psElemSize->u32TxBuf)); +} + + +/** + * @brief Function configures the data structures used by a dedicated Rx Buffer. + * + * @param[in] psCanfd The pointer to CAN FD module base address. + * @param[in] psRamConfig Rx buffer configuration ram address. + * @param[in] psElemSize Rx buffer configuration element size. + * @param[in] eRxBufSize Maximum data field size that should be stored in a dedicated Rx Buffer + * (configure BYTE64 if you are unsure, as this is the largest data field allowed in CAN FD)largest data field allowed in CAN FD) + * + * @return None. + * + * @details Function configures the data structures used by a dedicated Rx Buffer. + */ +static void CANFD_InitRxDBuf(CANFD_T *psCanfd, CANFD_RAM_PART_T *psRamConfig, CANFD_ELEM_SIZE_T *psElemSize, E_CANFD_DATA_FIELD_SIZE eRxBufSize) +{ + uint32_t u32Address; + uint32_t u32Size; + + /*Setting the Rx Buffer Start Address*/ + psCanfd->RXBC = (psRamConfig->u32RXBC_RBSA & CANFD_RXBC_RBSA_Msk); + + /*Get the RX Buffer Start Address in the RAM*/ + u32Address = CANFD_SRAM_BASE_ADDR(psCanfd) + (psRamConfig->u32RXBC_RBSA & CANFD_RXBC_RBSA_Msk); + + /*Setting the Rx Buffer Data Field Size*/ + psCanfd->RXESC = (psCanfd->RXESC & (~CANFD_RXESC_RBDS_Msk)) | (eRxBufSize << CANFD_RXESC_RBDS_Pos); + /*Get the Buffer Data Field Size*/ + u32Size = eRxBufSize; + + if (u32Size < 5U) + { + u32Size += 4U; + } + else + { + u32Size = u32Size * 4U - 10U; + } + + /*Clear the RX Buffer Memory*/ + memset((uint32_t *)(u32Address), 0x00, (u32Size * 4 * psElemSize->u32RxBuf)); +} + + +/** + * @brief Configures the register SIDFC for the 11-bit Standard Message ID Filter elements. + * + * @param[in] psCanfd The pointer to CAN FD module base address. + * @param[in] psRamConfig Standard ID filter configuration ram address + * @param[in] psElemSize Standard ID filter configuration element size + * + * @return None. + * + * @details Function configures the data structures used by a dedicated Rx Buffer. + */ +static void CANFD_ConfigSIDFC(CANFD_T *psCanfd, CANFD_RAM_PART_T *psRamConfig, CANFD_ELEM_SIZE_T *psElemSize) +{ + uint32_t u32Address; + + /*Setting the Filter List Standard Start Address and List Size */ + psCanfd->SIDFC = ((psElemSize->u32SIDFC & 0xFF) << CANFD_SIDFC_LSS_Pos) | (psRamConfig->u32SIDFC_FLSSA & CANFD_SIDFC_FLSSA_Msk); + + /*Get the Filter List Standard Start Address in the RAM*/ + u32Address = CANFD_SRAM_BASE_ADDR(psCanfd) + (psRamConfig->u32SIDFC_FLSSA & CANFD_SIDFC_FLSSA_Msk); + + /*Clear the Filter List Memory*/ + memset((uint32_t *)(u32Address), 0x00, (psElemSize->u32SIDFC * sizeof(CANFD_STD_FILTER_T))); +} + + +/** + * @brief Configures the register XIDFC for the 29-bit Extended Message ID Filter elements. + * + * @param[in] psCanfd The pointer to CAN FD module base address. + * @param[in] psRamConfig Extended ID filter configuration ram address + * @param[in] psElemSize Extended ID filter configuration element size + * + * @return None. + * + * @details Configures the register XIDFC for the 29-bit Extended Message ID Filter elements. + */ +static void CANFD_ConfigXIDFC(CANFD_T *psCanfd, CANFD_RAM_PART_T *psRamConfig, CANFD_ELEM_SIZE_T *psElemSize) +{ + uint32_t u32Address; + + /*Setting the Filter List Extended Start Address and List Size */ + psCanfd->XIDFC = ((psElemSize->u32XIDFC & 0xFF) << CANFD_XIDFC_LSE_Pos) | (psRamConfig->u32XIDFC_FLESA & CANFD_XIDFC_FLESA_Msk); + + /*Get the Filter List Standard Start Address in the RAM*/ + u32Address = CANFD_SRAM_BASE_ADDR(psCanfd) + (psRamConfig->u32XIDFC_FLESA & CANFD_XIDFC_FLESA_Msk); + + /*Clear the Filter List Memory*/ + memset((uint32_t *)(u32Address), 0x00, (psElemSize->u32XIDFC * sizeof(CANFD_EXT_FILTER_T))); +} + + +/** + * @brief Writes a 11-bit Standard ID filter element in the Message RAM. + * + * @param[in] psCanfd The pointer to CAN FD module base address. + * @param[in] u32FltrIdx Index at which the filter element should be written in the '11-bit Filter' section of Message RAM + * @param[in] u32Filter Rx Individual filter value. + * + * @return None. + * + * @details Writes a 11-bit Standard ID filter element in the Message RAM. + */ +void CANFD_SetSIDFltr(CANFD_T *psCanfd, uint32_t u32FltrIdx, uint32_t u32Filter) +{ + CANFD_STD_FILTER_T *psFilter; + + /* ignore if index is too high */ + if (u32FltrIdx >= CANFD_MAX_11_BIT_FTR_ELEMS) return; + + /*Get the Filter List Configuration Address in the RAM*/ + psFilter = (CANFD_STD_FILTER_T *)(CANFD_SRAM_BASE_ADDR(psCanfd) + (psCanfd->SIDFC & CANFD_SIDFC_FLSSA_Msk) + (u32FltrIdx * sizeof(CANFD_STD_FILTER_T))); + + /*Wirted the Standard ID filter element to RAM */ + psFilter->VALUE = u32Filter; +} + + +/** + * @brief Writes a 29-bit extended id filter element in the Message RAM. + * Size of an Extended Id filter element is 2 words. So 2 words are written into the Message RAM for each filter element + * + * @param[in] psCanfd The pointer to CAN FD module base address. + * @param[in] u32FltrIdx Index at which the filter element should be written in the '29-bit Filter' section of Message RAM. + * @param[in] u32FilterLow Rx Individual filter low value. + * @param[in] u32FilterHigh Rx Individual filter high value. + * + * @return None. + * + * @details Writes a 29-bit extended id filter element in the Message RAM. + */ +void CANFD_SetXIDFltr(CANFD_T *psCanfd, uint32_t u32FltrIdx, uint32_t u32FilterLow, uint32_t u32FilterHigh) +{ + CANFD_EXT_FILTER_T *psFilter; + + /* ignore if index is too high */ + if (u32FltrIdx >= CANFD_MAX_29_BIT_FTR_ELEMS) return; + + /*Get the Filter List Configuration Address on RAM*/ + psFilter = (CANFD_EXT_FILTER_T *)(CANFD_SRAM_BASE_ADDR(psCanfd) + (psCanfd->XIDFC & CANFD_XIDFC_FLESA_Msk) + (u32FltrIdx * sizeof(CANFD_EXT_FILTER_T))); + + /*Wirted the Extended ID filter element to RAM */ + psFilter->LOWVALUE = u32FilterLow; + psFilter->HIGHVALUE = u32FilterHigh; +} + + +/** + * @brief Reads a CAN FD Message from Receive Message Buffer. + * + * @param[in] psCanfd The pointer of the specified CAN FD module. + * @param[in] u8MbIdx The CANFD Message Buffer index. + * @param[in] psMsgBuf Pointer to CAN FD message frame structure for reception. + * + * @return 1:Rx Message Buffer is full and has been read successfully. + * 0:Rx Message Buffer is empty. + * + * @details This function reads a CAN message from a specified Receive Message Buffer. + * The function fills a receive CAN message frame structure with just received data + * and activates the Message Buffer again.The function returns immediately. +*/ +uint32_t CANFD_ReadRxBufMsg(CANFD_T *psCanfd, uint8_t u8MbIdx, CANFD_FD_MSG_T *psMsgBuf) +{ + CANFD_BUF_T *psRxBuffer; + uint32_t u32Success = 0; + uint32_t newData = 0; + + if (u8MbIdx < CANFD_MAX_RX_BUF_ELEMS) + { + if (u8MbIdx < 32) + newData = (CANFD_ReadReg(&psCanfd->NDAT1) >> u8MbIdx) & 1; + else + newData = (CANFD_ReadReg(&psCanfd->NDAT2) >> (u8MbIdx - 32)) & 1; + + /* new message is waiting to be read */ + if (newData) + { + /* get memory location of rx buffer */ + psRxBuffer = (CANFD_BUF_T *)(CANFD_SRAM_BASE_ADDR(psCanfd) + (CANFD_ReadReg(&psCanfd->RXBC) & 0xFFFF) + (u8MbIdx * sizeof(CANFD_BUF_T))); + + /* read the message */ + CANFD_CopyDBufToMsgBuf(psRxBuffer, psMsgBuf); + + /* clear 'new data' flag */ + if (u8MbIdx < 32) + psCanfd->NDAT1 = CANFD_ReadReg(&psCanfd->NDAT1) | (1UL << u8MbIdx); + else + psCanfd->NDAT2 = CANFD_ReadReg(&psCanfd->NDAT2) | (1UL << (u8MbIdx - 32)); + + u32Success = 1; + } + } + + return u32Success; +} + + +/** + * @brief Reads a CAN FD Message from Rx FIFO. + * + * @param[in] psCanfd The pointer of the specified CANFD module. + * @param[in] u8FifoIdx Number of the FIFO, 0 or 1. + * @param[in] psMsgBuf Pointer to CANFD message frame structure for reception. + * + * @return 1 Read Message from Rx FIFO successfully. + * 2 Rx FIFO is already overflowed and has been read successfully + * 0 Rx FIFO is not enabled. + * + * @details This function reads a CAN message from the CANFD build-in Rx FIFO. + */ +uint32_t CANFD_ReadRxFifoMsg(CANFD_T *psCanfd, uint8_t u8FifoIdx, CANFD_FD_MSG_T *psMsgBuf) +{ + CANFD_BUF_T *pRxBuffer; + uint8_t GetIndex; + uint32_t u32Success = 0; + __I uint32_t *pRXFS; + __IO uint32_t *pRXFC, *pRXFA; + uint8_t msgLostBit; + + /* check for valid FIFO number */ + if (u8FifoIdx < CANFD_NUM_RX_FIFOS) + { + if (u8FifoIdx == 0) + { + pRXFS = &(psCanfd->RXF0S); + pRXFC = &(psCanfd->RXF0C); + pRXFA = &(psCanfd->RXF0A); + msgLostBit = 3; + } + else + { + pRXFS = &(psCanfd->RXF1S); + pRXFC = &(psCanfd->RXF1C); + pRXFA = &(psCanfd->RXF1A); + msgLostBit = 7; + } + + /* if FIFO is not empty */ + if ((CANFD_ReadReg(pRXFS) & 0x7F) > 0) + { + GetIndex = (uint8_t)((CANFD_ReadReg(pRXFS) >> 8) & 0x3F); + pRxBuffer = (CANFD_BUF_T *)(CANFD_SRAM_BASE_ADDR(psCanfd) + (CANFD_ReadReg(pRXFC) & 0xFFFF) + (GetIndex * sizeof(CANFD_BUF_T))); + + CANFD_CopyRxFifoToMsgBuf(pRxBuffer, psMsgBuf); + + /* we got the message */ + *pRXFA = GetIndex; + + /* check for overflow */ + if (CANFD_ReadReg(pRXFS) & CANFD_RXFS_RFL) + { + /* clear overflow flag */ + psCanfd->IR = (1UL << msgLostBit); + u32Success = 2; + } + else + { + u32Success = 1; + } + } + } + + return u32Success; +} + + +/** + * @brief Copies a message from a dedicated Rx buffer into a message buffer. + * + * @param[in] psRxBuf Buffer to read from. + * @param[in] psMsgBuf Location to store read message. + * + * @return None. + * + * @details Copies a message from a dedicated Rx buffer into a message buffer. + */ +void CANFD_CopyDBufToMsgBuf(CANFD_BUF_T *psRxBuf, CANFD_FD_MSG_T *psMsgBuf) +{ + uint32_t u32Idx; + + if (psRxBuf->u32Id & RX_BUFFER_AND_FIFO_R0_ELEM_ESI_Msk) + psMsgBuf->bErrStaInd = TRUE; + else + psMsgBuf->bErrStaInd = FALSE; + + /* if 29-bit ID */ + if (psRxBuf->u32Id & RX_BUFFER_AND_FIFO_R0_ELEM_XTD_Msk) + { + psMsgBuf->u32Id = (psRxBuf->u32Id & RX_BUFFER_AND_FIFO_R0_ELEM_ID_Msk); + psMsgBuf->eIdType = eCANFD_XID; + } + /* if 11-bit ID */ + else + { + psMsgBuf->u32Id = (psRxBuf->u32Id >> 18) & 0x7FF; + psMsgBuf->eIdType = eCANFD_SID; + } + + if (psRxBuf->u32Id & RX_BUFFER_AND_FIFO_R0_ELEM_RTR_Msk) + psMsgBuf->eFrmType = eCANFD_REMOTE_FRM; + else + psMsgBuf->eFrmType = eCANFD_DATA_FRM; + + + if (psRxBuf->u32Config & RX_BUFFER_AND_FIFO_R1_ELEM_FDF_Msk) + psMsgBuf->bFDFormat = TRUE; + else + psMsgBuf->bFDFormat = FALSE; + + if (psRxBuf->u32Config & RX_BUFFER_AND_FIFO_R1_ELEM_BSR_Msk) + psMsgBuf->bBitRateSwitch = TRUE; + else + psMsgBuf->bBitRateSwitch = FALSE; + + psMsgBuf->u32DLC = CANFD_DecodeDLC((psRxBuf->u32Config & RX_BUFFER_AND_FIFO_R1_ELEM_DLC_Msk) >> RX_BUFFER_AND_FIFO_R1_ELEM_DLC_Pos); + + for (u32Idx = 0 ; u32Idx < psMsgBuf->u32DLC ; u32Idx++) + { + psMsgBuf->au8Data[u32Idx] = psRxBuf->au8Data[u32Idx]; + } +} + + +/** + * @brief Get Rx FIFO water level. + * + * @param[in] psCanfd The pointer to CANFD module base address. + * @param[in] u32RxFifoNum 0: RX FIFO_0, 1: RX_FIFO_1 + * + * @return Rx FIFO water level. + * + * @details Get Rx FIFO water level. + */ +uint32_t CANFD_GetRxFifoWaterLvl(CANFD_T *psCanfd, uint32_t u32RxFifoNum) +{ + uint32_t u32WaterLevel = 0; + + if (u32RxFifoNum == 0) + u32WaterLevel = ((CANFD_ReadReg(&psCanfd->RXF0C) & CANFD_RXF0C_F0WM_Msk) >> CANFD_RXF0C_F0WM_Pos); + else + u32WaterLevel = ((CANFD_ReadReg(&psCanfd->RXF1C) & CANFD_RXF1C_F1WM_Msk) >> CANFD_RXF1C_F1WM_Pos); + + return u32WaterLevel; +} + + +/** + * @brief Copies messages from FIFO into a message buffert. + * + * @param[in] psRxBuf Buffer to read from. + * @param[in] psMsgBuf Location to store read message. + * + * @return None. + * + * @details Copies messages from FIFO into a message buffert. + */ +void CANFD_CopyRxFifoToMsgBuf(CANFD_BUF_T *psRxBuf, CANFD_FD_MSG_T *psMsgBuf) +{ + /*Copies a message from a dedicated Rx FIFO into a message buffer*/ + CANFD_CopyDBufToMsgBuf(psRxBuf, psMsgBuf); +} + + +/** + * @brief Cancel a Tx buffer transmission request. + * + * @param[in] psCanfd The pointer to CANFD module base address. + * @param[in] u32TxBufIdx Tx buffer index number + * + * @return None. + * + * @details Cancel a Tx buffer transmission request. + */ +void CANFD_TxBufCancelReq(CANFD_T *psCanfd, uint32_t u32TxBufIdx) +{ + psCanfd->TXBCR = CANFD_ReadReg(&psCanfd->TXBCR) | (0x1ul << u32TxBufIdx); +} + + +/** + * @brief Checks if a Tx buffer cancellation request has been finished or not. + * + * @param[in] psCanfd The pointer to CAN FD module base address. + * @param[in] u32TxBufIdx Tx buffer index number + * + * @return 0: cancellation finished. + * 1: cancellation fail + * + * @details Checks if a Tx buffer cancellation request has been finished or not. + */ +uint32_t CANFD_IsTxBufCancelFin(CANFD_T *psCanfd, uint32_t u32TxBufIdx) +{ + /* wait for completion */ + return ((CANFD_ReadReg(&psCanfd->TXBCR) & (0x1ul << u32TxBufIdx)) >> u32TxBufIdx); +} + + +/** + * @brief Checks if a Tx buffer transmission has occurred or not. + * + * @param[in] psCanfd The pointer to CAN FD module base address. + * @param[in] u32TxBufIdx Tx buffer index number + * + * @return 0: No transmission occurred. + * 1: Transmission occurred + * + * @details Checks if a Tx buffer transmission has occurred or not. + */ +uint32_t CANFD_IsTxBufTransmitOccur(CANFD_T *psCanfd, uint32_t u32TxBufIdx) +{ + return ((CANFD_ReadReg(&psCanfd->TXBTO) & (0x1ul << u32TxBufIdx)) >> u32TxBufIdx); +} + + +/** + * @brief Init Tx event fifo + * + * @param[in] psCanfd The pointer to CAN FD module base address. + * @param[in] psRamConfig Tx Event Fifo configuration ram address. + * @param[in] psElemSize Tx Event Fifo configuration element size + * @param[in] u32FifoWaterLvl FIFO water level + * + * @return None. + * + * @details Init Tx event fifo. + */ +static void CANFD_InitTxEvntFifo(CANFD_T *psCanfd, CANFD_RAM_PART_T *psRamConfig, CANFD_ELEM_SIZE_T *psElemSize, uint32_t u32FifoWaterLvl) +{ + /* Set TX Event FIFO element size,watermark,start address. */ + psCanfd->TXEFC = (u32FifoWaterLvl << CANFD_TXEFC_EFWN_Pos) | (psElemSize->u32TxEventFifo << CANFD_TXEFC_EFS_Pos) + | (psRamConfig->u32TXEFC_EFSA & CANFD_TXEFC_EFSA_Msk); +} + + +/** + * @brief Get Tx event fifo water level + * + * @param[in] psCanfd The pointer to CANFD module base address. + * + * @return Tx event fifo water level. + * + * @details Get Tx event fifo water level. + */ +uint32_t CANFD_GetTxEvntFifoWaterLvl(CANFD_T *psCanfd) +{ + return ((CANFD_ReadReg(&psCanfd->TXEFC) & CANFD_TXEFC_EFWN_Msk) >> CANFD_TXEFC_EFWN_Pos); +} + + +/** + * @brief Copy Event Elements from TX Event FIFO to user buffer + * + * @param[in] psCanfd The pointer to CAN FD module base address. + * @param[in] u32TxEvntNum Tx Event FIFO number + * @param[in] psTxEvntElem Tx Event Message struct + * + * @return None. + * + * @details Copy all Event Elements from TX Event FIFO to the Software Event List . + */ +void CANFD_CopyTxEvntFifoToUsrBuf(CANFD_T *psCanfd, uint32_t u32TxEvntNum, CANFD_TX_EVNT_ELEM_T *psTxEvntElem) +{ + uint32_t *pu32TxEvnt; + /*Get the Tx Event FIFO Address*/ + pu32TxEvnt = (uint32_t *)CANFD_GetTxBufferElementAddress(psCanfd, u32TxEvntNum); + + /*Get the Error State Indicator*/ + if ((pu32TxEvnt[0] & TX_FIFO_E0_EVENT_ESI_Msk) > 0) + psTxEvntElem->bErrStaInd = TRUE; //Transmitting node is error passive + else + psTxEvntElem->bErrStaInd = FALSE;//Transmitting node is error active + + /*Get the Tx FIFO Identifier type and Identifier*/ + + if ((pu32TxEvnt[0] & TX_FIFO_E0_EVENT_XTD_Msk) > 0) + { + psTxEvntElem-> eIdType = eCANFD_XID; + psTxEvntElem->u32Id = (pu32TxEvnt[0] & TX_FIFO_E0_EVENT_ID_Msk);// Extended ID + } + else + { + psTxEvntElem-> eIdType = eCANFD_SID; + psTxEvntElem->u32Id = (pu32TxEvnt[0] & TX_FIFO_E0_EVENT_ID_Msk) >> 18;// Standard ID + } + + /*Get the Frame type*/ + if ((pu32TxEvnt[0] & TX_FIFO_E0_EVENT_RTR_Msk) > 0) + psTxEvntElem->bRemote = TRUE; //Remote frame + else + psTxEvntElem->bRemote = FALSE; //Data frame + + /*Get the FD Format type*/ + if ((pu32TxEvnt[0] & TX_FIFO_E1_EVENT_FDF_Msk) > 0) + psTxEvntElem->bFDFormat = TRUE; //CAN FD frame format + else + psTxEvntElem->bFDFormat = FALSE; //Classical CAN frame format + + /*Get the Bit Rate Switch type*/ + if ((pu32TxEvnt[0] & TX_FIFO_E1_EVENT_BRS_Msk) > 0) + psTxEvntElem->bBitRateSwitch = TRUE; //Frame transmitted with bit rate switching + else + psTxEvntElem->bBitRateSwitch = FALSE; //Frame transmitted without bit rate switching + + /*Get the Tx FIFO Data Length */ + psTxEvntElem->u32DLC = CANFD_DecodeDLC((uint8_t)((pu32TxEvnt[1] & TX_FIFO_E1_EVENT_DLC_Msk) >> TX_FIFO_E1_EVENT_DLC_Pos)); + + /*Get the Tx FIFO Timestamp */ + psTxEvntElem->u32TxTs = (((pu32TxEvnt[1] & TX_FIFO_E1A_EVENT_TXTS_Msk) >> TX_FIFO_E1A_EVENT_TXTS_Pos)); + /*Get the Tx FIFO Message marker */ + psTxEvntElem->u32MsgMarker = (((pu32TxEvnt[1] & TX_FIFO_E1_EVENT_MM_Msk) >> TX_FIFO_E1_EVENT_MM_Pos)); +} + + +/** + * @brief Get CAN FD interrupts status. + * + * @param[in] psCanfd The pointer of the specified CAN FD module. + * @param[in] u32IntTypeFlag Interrupt Type Flag, should be + * - \ref CANFD_IR_ARA_Msk : Access to Reserved Address interrupt Indicator + * - \ref CANFD_IR_PED_Msk : Protocol Error in Data Phase interrupt Indicator + * - \ref CANFD_IR_PEA_Msk : Protocol Error in Arbitration Phase interrupt Indicator + * - \ref CANFD_IR_WDI_Msk : Watchdog interrupt Indicator + * - \ref CANFD_IR_BO_Msk : Bus_Off Status interrupt Indicator + * - \ref CANFD_IR_EW_Msk : Warning Status interrupt Indicator + * - \ref CANFD_IR_EP_Msk : Error Passive interrupt Indicator + * - \ref CANFD_IR_ELO_Msk : Error Logging Overflow interrupt Indicator + * - \ref CANFD_IR_DRX_Msk : Message stored to Dedicated Rx Buffer interrupt Indicator + * - \ref CANFD_IR_TOO_Msk : Timeout Occurred interrupt Indicator + * - \ref CANFD_IR_MRAF_Msk : Message RAM Access Failure interrupt Indicator + * - \ref CANFD_IR_TSW_Msk : Timestamp Wraparound interrupt Indicator + * - \ref CANFD_IR_TEFL_Msk : Tx Event FIFO Event Lost interrupt Indicator + * - \ref CANFD_IR_TEFF_Msk : Tx Event FIFO Full Indicator + * - \ref CANFD_IR_TEFW_Msk : Tx Event FIFO Watermark Reached Interrupt Indicator + * - \ref CANFD_IR_TEFN_Msk : Tx Event FIFO New Entry Interrupt Indicator + * - \ref CANFD_IR_TFE_Msk : Tx FIFO Empty Interrupt Indicator + * - \ref CANFD_IR_TCF_Msk : Transmission Cancellation Finished Interrupt Indicator + * - \ref CANFD_IR_TC_Msk : Transmission Completed interrupt Indicator + * - \ref CANFD_IR_HPM_Msk : High Priority Message Interrupt Indicator + * - \ref CANFD_IR_RF1L_Msk : Rx FIFO 1 Message Lost Interrupt Indicator + * - \ref CANFD_IR_RF1F_Msk : Rx FIFO 1 Full Interrupt Indicator + * - \ref CANFD_IR_RF1W_Msk : Rx FIFO 1 Watermark Reached Interrupt Indicator + * - \ref CANFD_IR_RF1N_Msk : Rx FIFO 1 New Message Interrupt Indicator + * - \ref CANFD_IR_RF0L_Msk : Rx FIFO 0 Message Lost Interrupt Indicator + * - \ref CANFD_IR_RF0F_Msk : Rx FIFO 0 Full Interrupt Indicator + * - \ref CANFD_IR_RF0W_Msk : Rx FIFO 0 Watermark Reached Interrupt Indicator + * - \ref CANFD_IR_RF0N_Msk : Rx FIFO 0 New Message Interrupt Indicator + * + * @return None. + * + * @details This function gets all CAN FD interrupt status flags. + */ +uint32_t CANFD_GetStatusFlag(CANFD_T *psCanfd, uint32_t u32IntTypeFlag) +{ + return (CANFD_ReadReg(&psCanfd->IR) & u32IntTypeFlag); +} + + +/** + * @brief Clears the CAN FD module interrupt flags + * + * @param[in] psCanfd The pointer of the specified CANFD module. + * @param[in] u32InterruptFlag The specified interrupt of CAN FD module + * - \ref CANFD_IR_ARA_Msk : Access to Reserved Address interrupt Indicator + * - \ref CANFD_IR_PED_Msk : Protocol Error in Data Phase interrupt Indicator + * - \ref CANFD_IR_PEA_Msk : Protocol Error in Arbitration Phase interrupt Indicator + * - \ref CANFD_IR_WDI_Msk : Watchdog interrupt Indicator + * - \ref CANFD_IR_BO_Msk : Bus_Off Status interrupt Indicator + * - \ref CANFD_IR_EW_Msk : Warning Status interrupt Indicator + * - \ref CANFD_IR_EP_Msk : Error Passive interrupt Indicator + * - \ref CANFD_IR_ELO_Msk : Error Logging Overflow interrupt Indicator + * - \ref CANFD_IR_DRX_Msk : Message stored to Dedicated Rx Buffer interrupt Indicator + * - \ref CANFD_IR_TOO_Msk : Timeout Occurred interrupt Indicator + * - \ref CANFD_IR_MRAF_Msk : Message RAM Access Failure interrupt Indicator + * - \ref CANFD_IR_TSW_Msk : Timestamp Wraparound interrupt Indicator + * - \ref CANFD_IR_TEFL_Msk : Tx Event FIFO Event Lost interrupt Indicator + * - \ref CANFD_IR_TEFF_Msk : Tx Event FIFO Full Indicator + * - \ref CANFD_IR_TEFW_Msk : Tx Event FIFO Watermark Reached Interrupt Indicator + * - \ref CANFD_IR_TEFN_Msk : Tx Event FIFO New Entry Interrupt Indicator + * - \ref CANFD_IR_TFE_Msk : Tx FIFO Empty Interrupt Indicator + * - \ref CANFD_IR_TCF_Msk : Transmission Cancellation Finished Interrupt Indicator + * - \ref CANFD_IR_TC_Msk : Transmission Completed interrupt Indicator + * - \ref CANFD_IR_HPM_Msk : High Priority Message Interrupt Indicator + * - \ref CANFD_IR_RF1L_Msk : Rx FIFO 1 Message Lost Interrupt Indicator + * - \ref CANFD_IR_RF1F_Msk : Rx FIFO 1 Full Interrupt Indicator + * - \ref CANFD_IR_RF1W_Msk : Rx FIFO 1 Watermark Reached Interrupt Indicator + * - \ref CANFD_IR_RF1N_Msk : Rx FIFO 1 New Message Interrupt Indicator + * - \ref CANFD_IR_RF0L_Msk : Rx FIFO 0 Message Lost Interrupt Indicator + * - \ref CANFD_IR_RF0F_Msk : Rx FIFO 0 Full Interrupt Indicator + * - \ref CANFD_IR_RF0W_Msk : Rx FIFO 0 Watermark Reached Interrupt Indicator + * - \ref CANFD_IR_RF0N_Msk : Rx FIFO 0 New Message Interrupt Indicator + * + * @return None. + * + * @details This function clears CAN FD interrupt status flags. + */ +void CANFD_ClearStatusFlag(CANFD_T *psCanfd, uint32_t u32InterruptFlag) +{ + /* Write 1 to clear status flag. */ + psCanfd->IR = CANFD_ReadReg(&psCanfd->IR) | u32InterruptFlag; +} + + +/** + * @brief Gets the CAN FD Bus Error Counter value. + * + * @param[in] psCanfd The pointer of the specified CAN FD module. + * @param[in] pu8TxErrBuf TxErrBuf Buffer to store Tx Error Counter value. + * @param[in] pu8RxErrBuf RxErrBuf Buffer to store Rx Error Counter value. + * + * @return None. + * + * @details This function gets the CAN FD Bus Error Counter value for both Tx and Rx direction. + * These values may be needed in the upper layer error handling. + */ +void CANFD_GetBusErrCount(CANFD_T *psCanfd, uint8_t *pu8TxErrBuf, uint8_t *pu8RxErrBuf) +{ + if (pu8TxErrBuf) + { + *pu8TxErrBuf = (uint8_t)((CANFD_ReadReg(&psCanfd->ECR) >> CANFD_ECR_TEC_Pos) & CANFD_ECR_TEC_Msk); + } + + if (pu8RxErrBuf) + { + *pu8RxErrBuf = (uint8_t)((CANFD_ReadReg(&psCanfd->ECR) >> CANFD_ECR_REC_Pos) & CANFD_ECR_REC_Msk); + } +} + + +/** + * @brief CAN FD Run to the Normal Operation. + * + * @param[in] psCanfd The pointer of the specified CAN FD module. + * @param[in] u8Enable TxErrBuf Buffer to store Tx Error Counter value. + * + * @retval CANFD_OK CANFD operation OK. + * @retval CANFD_ERR_TIMEOUT CANFD operation abort due to timeout error. + * + * @details This function gets the CAN FD Bus Error Counter value for both Tx and Rx direction. + * These values may be needed in the upper layer error handling. + */ +int32_t CANFD_RunToNormal(CANFD_T *psCanfd, uint8_t u8Enable) +{ + uint32_t u32TimeOutCnt = CANFD_TIMEOUT; + + if (u8Enable) + { + /* start operation */ + psCanfd->CCCR = CANFD_ReadReg(&psCanfd->CCCR) & ~(CANFD_CCCR_CCE_Msk | CANFD_CCCR_INIT_Msk); + + while (psCanfd->CCCR & CANFD_CCCR_INIT_Msk) + { + if (--u32TimeOutCnt == 0) return CANFD_ERR_TIMEOUT; + } + } + else + { + /* init mode */ + psCanfd->CCCR = CANFD_ReadReg(&psCanfd->CCCR) | CANFD_CCCR_INIT_Msk | CANFD_CCCR_CCE_Msk; + + while (!(psCanfd->CCCR & CANFD_CCCR_INIT_Msk)) + { + if (--u32TimeOutCnt == 0) return CANFD_ERR_TIMEOUT; + } + } + + return CANFD_OK; +} + + + +/*@}*/ /* end of group CANFD_EXPORTED_FUNCTIONS */ + +/*@}*/ /* end of group CANFD_Driver */ + +/*@}*/ /* end of group Standard_Driver */ diff --git a/bsp/nuvoton/libraries/ma35/StdDriver/src/nu_ccap.c b/bsp/nuvoton/libraries/ma35/StdDriver/src/nu_ccap.c new file mode 100644 index 0000000000..a192b7e77a --- /dev/null +++ b/bsp/nuvoton/libraries/ma35/StdDriver/src/nu_ccap.c @@ -0,0 +1,406 @@ +/**************************************************************************//** + * @file ccap.c + * @version V3.00 + * @brief M460 Series CCAP Driver Source File + * + * @copyright SPDX-License-Identifier: Apache-2.0 + * @copyright Copyright (C) 2021 Nuvoton Technology Corp. All rights reserved. + *****************************************************************************/ + +#include "NuMicro.h" +/** @addtogroup Standard_Driver Standard Driver + @{ +*/ + +/** @addtogroup CCAP_Driver CCAP Driver + @{ +*/ + +int32_t g_CCAP_i32ErrCode = 0; /*!< CCAP global error code */ + +/** @addtogroup CCAP_EXPORTED_FUNCTIONS CCAP Exported Functions + @{ +*/ + +/** + * @brief Open and set CCAP function + * + * @param[in] u32InFormat The bits corresponding VSP, HSP, PCLK, INFMT, SNRTYPE, OUTFMT and PDORD configurations. + * - VSP Sensor Vsync Polarity. It should be either \ref CCAP_PAR_VSP_LOW or \ref CCAP_PAR_VSP_HIGH + * - HSP Sensor Hsync Polarity. It should be either \ref CCAP_PAR_HSP_LOW or \ref CCAP_PAR_HSP_HIGH + * - PCLK Sensor Pixel Clock Polarity. It should be either \ref CCAP_PAR_PCLKP_LOW or \ref CCAP_PAR_PCLKP_HIGH + * - INFMT Sensor Input Data Format. It should be either \ref CCAP_PAR_INFMT_YUV422 or \ref CCAP_PAR_INFMT_RGB565 + * - SNRTYPE Sensor Input Type. It should be either \ref CCAP_PAR_SENTYPE_CCIR601 or \ref CCAP_PAR_SENTYPE_CCIR656 + * - PLNFMT Planar Output YUV Format + * - \ref 0 = YUV422 + * - OUTFMT Image Data Format Output to System Memory. It should be one of the following settings + * - \ref CCAP_PAR_OUTFMT_YUV422 + * - \ref CCAP_PAR_OUTFMT_ONLY_Y + * - \ref CCAP_PAR_OUTFMT_RGB555 + * - \ref CCAP_PAR_OUTFMT_RGB565 + * - PDORD Sensor Input Data Order. It should be one of the following settings + * - \ref CCAP_PAR_INDATORD_YUYV + * - \ref CCAP_PAR_INDATORD_YVYU + * - \ref CCAP_PAR_INDATORD_UYVY + * - \ref CCAP_PAR_INDATORD_VYUY + * - \ref CCAP_PAR_INDATORD_RGGB + * - \ref CCAP_PAR_INDATORD_BGGR + * - \ref CCAP_PAR_INDATORD_GBRG + * - \ref CCAP_PAR_INDATORD_GRBG + * @param[in] u32OutFormat Image Data Output Format. It should be + * - \ref CCAP_CTL_PKTEN + * + * @return None + * + * @details Initialize the Camera Capture Interface. + */ +void CCAP_Open(CCAP_T *ccap, uint32_t u32InFormat, uint32_t u32OutFormat) +{ + ccap->PAR = (ccap->PAR & ~(0x000007BFUL)) | u32InFormat; + ccap->CTL = (ccap->CTL & ~(0x00000060UL)) | u32OutFormat; +} + +/** + * @brief Set Cropping Window Starting Address and Size + * + * @param[in] u32VStart: Cropping Window Vertical Starting Address. It should be 0 ~ 0x7FF. + * @param[in] u32HStart: Cropping Window Horizontal Starting Address. It should be 0 ~ 0x7FF. + * @param[in] u32Height: Cropping Window Height. It should be 0 ~ 0x7FF. + * @param[in] u32Width: Cropping Window Width. It should be 0 ~ 0x7FF. + * + * @return None + * + * @details This function is used to set cropping window starting address and size. + */ +void CCAP_SetCroppingWindow(CCAP_T *ccap, uint32_t u32VStart, uint32_t u32HStart, uint32_t u32Height, uint32_t u32Width) +{ + ccap->CWSP = (ccap->CWSP & ~(CCAP_CWSP_CWSADDRV_Msk | CCAP_CWSP_CWSADDRH_Msk)) + | (((u32VStart << 16) | u32HStart)); + + ccap->CWS = (ccap->CWS & ~(CCAP_CWS_CWH_Msk | CCAP_CWS_CWW_Msk)) + | ((u32Height << 16) | u32Width); +} + +/** + * @brief Set System Memory Packet Base Address + * + * @param[in] u32Address: Set CCAP_PKTBA0 register. It should be 0x0 ~ 0xFFFFFFFF. + * + * @return None + * + * @details This function is used to set System Memory Packet Base Address 0 Register. + */ +void CCAP_SetPacketBuf(CCAP_T *ccap, uint32_t u32Address) +{ + ccap->PKTBA0 = u32Address; + ccap->CTL |= CCAP_CTL_UPDATE_Msk; +} + +/** + * @brief Set System Memory Planar Y Base Address + * + * @param[in] u32Address: Set CCAP_YBA register. It should be 0x0 ~ 0xFFFFFFFF. + * + * @return None + * + * @details This function is used to set System Memory Planar Y Base Address 0 Register. + */ +void CCAP_SetPlanarYBuf(CCAP_T *ccap, uint32_t u32Address) +{ + ccap->YBA = u32Address; + ccap->CTL |= CCAP_CTL_UPDATE_Msk; +} + +/** + * @brief Set System Memory Planar U Base Address + * + * @param[in] u32Address: Set CCAP_UBA register. It should be 0x0 ~ 0xFFFFFFFF. + * + * @return None + * + * @details This function is used to set System Memory Planar U Base Address 0 Register. + */ +void CCAP_SetPlanarUBuf(CCAP_T *ccap, uint32_t u32Address) +{ + ccap->UBA = u32Address; + ccap->CTL |= CCAP_CTL_UPDATE_Msk; +} + +/** + * @brief Set System Memory Planar V Base Address + * + * @param[in] u32Address: Set CCAP_VBA register. It should be 0x0 ~ 0xFFFFFFFF. + * + * @return None + * + * @details This function is used to set System Memory Planar V Base Address 0 Register. + */ +void CCAP_SetPlanarVBuf(CCAP_T *ccap, uint32_t u32Address) +{ + ccap->VBA = u32Address; + ccap->CTL |= CCAP_CTL_UPDATE_Msk; +} + +/** + * @brief Close Camera Capture Interface + * + * @param None + * + * @return None + * + * @details This function is used to disable Camera Capture Interface. + */ +void CCAP_Close(CCAP_T *ccap) +{ + ccap->CTL &= ~CCAP_CTL_CCAPEN; +} + +/** + * @brief Enable CCAP Interrupt + * + * @param[in] u32IntMask Interrupt settings. It could be + * - \ref CCAP_INT_VIEN_Msk + * - \ref CCAP_INT_MEIEN_Msk + * - \ref CCAP_INT_ADDRMIEN_Msk + * + * @return None + * + * @details This function is used to enable Video Frame End Interrupt, + * Bus Master Transfer Error Interrupt and Memory Address Match Interrupt. + */ +void CCAP_EnableInt(CCAP_T *ccap, uint32_t u32IntMask) +{ + ccap->INT = (ccap->INT & ~(CCAP_INT_VIEN_Msk | CCAP_INT_MEIEN_Msk | CCAP_INT_ADDRMIEN_Msk)) + | u32IntMask; +} + +/** + * @brief Disable CCAP Interrupt + * + * @param[in] u32IntMask Interrupt settings. It could be + * - \ref CCAP_INT_VINTF_Msk + * - \ref CCAP_INT_MEINTF_Msk + * - \ref CCAP_INT_ADDRMINTF_Msk + * + * @return None + * + * @details This function is used to disable Video Frame End Interrupt, + * Bus Master Transfer Error Interrupt and Memory Address Match Interrupt. + */ +void CCAP_DisableInt(CCAP_T *ccap, uint32_t u32IntMask) +{ + ccap->INT = (ccap->INT & ~(u32IntMask)); +} + +/** + * @brief Enable Monochrome CMOS Sensor + * + * @param[in] u32Interface Data I/O interface setting. It could be + * - \ref CCAP_CTL_MY8_MY4 + * - \ref CCAP_CTL_MY8_MY8 + * @return None + * + * @details This function is used to select monochrome CMOS sensor and set data width. + */ +void CCAP_EnableMono(CCAP_T *ccap, uint32_t u32Interface) +{ + ccap->CTL = (ccap->CTL & ~CCAP_CTL_MY8_MY4) | CCAP_CTL_MONO_Msk | u32Interface; +} + +/** + * @brief Disable Monochrome CMOS Sensor + * + * @param None + * + * @return None + * + * @details This function is used to disable monochrome CMOS sensor selection. + */ +void CCAP_DisableMono(CCAP_T *ccap) +{ + ccap->CTL &= ~CCAP_CTL_MONO_Msk; +} + +/** + * @brief Enable Luminance 8-bit Y to 1-bit Y Conversion + * + * @param[in] u32th Luminance Y8 to Y1 Threshold Value. It should be 0 ~ 255. + * + * @return None + * + * @details This function is used to enable luminance Y8 to Y1 function and set its threshold value. + */ +void CCAP_EnableLumaYOne(CCAP_T *ccap, uint32_t u32th) +{ + ccap->CTL |= CCAP_CTL_Luma_Y_One_Msk; + ccap->LUMA_Y1_THD = u32th & 0xff; +} + +/** + * @brief Disable Luminance 8-bit Y to 1-bit Y Conversion + * + * @param None + * + * @return None + * + * @details This function is used to disable luminance Y8 to Y1 function. + * + */ +void CCAP_DisableLumaYOne(CCAP_T *ccap) +{ + ccap->CTL &= ~CCAP_CTL_Luma_Y_One_Msk; +} + +/** + * @brief Start Camera Capture Interface + * + * @param None + * + * @return None + * + * @details This function is used to start Camera Capture Interface function. + */ +void CCAP_Start(CCAP_T *ccap) +{ + ccap->CTL |= CCAP_CTL_CCAPEN; +} + +/** + * @brief Stop Camera Capture Interface + * + * @param[in] u32FrameComplete: + * - \ref TRUE: Capture module disables the CCAP module automatically after a frame had been captured. + * - \ref FALSE: Stop Capture module now. + * + * @return None + * + * @details If u32FrameComplete is set to TRUE then get a new frame and disable CCAP module. + * + * @note This function sets g_CCAP_i32ErrCode to CCAP_TIMEOUT_ERR if the CCAP_IS_STOPPED() longer than expected. + */ +void CCAP_Stop(CCAP_T *ccap, uint32_t u32FrameComplete) +{ + uint32_t u32TimeOutCount = 94539453; + + if (u32FrameComplete == FALSE) + ccap->CTL &= ~CCAP_CTL_CCAPEN; + else + { + ccap->CTL |= CCAP_CTL_SHUTTER_Msk; + while (!CCAP_IS_STOPPED(ccap)) + { + if (--u32TimeOutCount == 0) + { + g_CCAP_i32ErrCode = CCAP_TIMEOUT_ERR; + break; + } + } + } +} + +/** + * @brief Set Packet Scaling Factor + * + * @param[in] u32VNumerator: Packet Scaling Vertical Factor N. It should be 0x0 ~ 0xFFFF. + * @param[in] u32VDenominator: Packet Scaling Vertical Factor M. It should be 0x0 ~ 0xFFFF. + * @param[in] u32HNumerator: Packet Scaling Horizontal Factor N. It should be 0x0 ~ 0xFFFF. + * @param[in] u32HDenominator: Packet Scaling Horizontal Factor M. It should be 0x0 ~ 0xFFFF. + * + * @return None + * + * @details This function is used to set Packet Scaling Vertical and Horizontal Factor register. + */ +void CCAP_SetPacketScaling(CCAP_T *ccap, uint32_t u32VNumerator, uint32_t u32VDenominator, uint32_t u32HNumerator, uint32_t u32HDenominator) +{ + uint32_t u32NumeratorL, u32NumeratorH; + uint32_t u32DenominatorL, u32DenominatorH; + + u32NumeratorL = u32VNumerator & 0xFF; + u32NumeratorH = u32VNumerator >> 8; + u32DenominatorL = u32VDenominator & 0xFF; + u32DenominatorH = u32VDenominator >> 8; + ccap->PKTSL = (ccap->PKTSL & ~(CCAP_PKTSL_PKTSVNL_Msk | CCAP_PKTSL_PKTSVML_Msk)) + | ((u32NumeratorL << CCAP_PKTSL_PKTSVNL_Pos) | (u32DenominatorL << CCAP_PKTSL_PKTSVML_Pos)); + ccap->PKTSM = (ccap->PKTSM & ~(CCAP_PKTSM_PKTSVNH_Msk | CCAP_PKTSM_PKTSVMH_Msk)) + | ((u32NumeratorH << CCAP_PKTSL_PKTSVNL_Pos) | (u32DenominatorH << CCAP_PKTSL_PKTSVML_Pos)); + + u32NumeratorL = u32HNumerator & 0xFF; + u32NumeratorH = u32HNumerator >> 8; + u32DenominatorL = u32HDenominator & 0xFF; + u32DenominatorH = u32HDenominator >> 8; + ccap->PKTSL = (ccap->PKTSL & ~(CCAP_PKTSL_PKTSHNL_Msk | CCAP_PKTSL_PKTSHML_Msk)) + | ((u32NumeratorL << CCAP_PKTSL_PKTSHNL_Pos) | (u32DenominatorL << CCAP_PKTSL_PKTSHML_Pos)); + ccap->PKTSM = (ccap->PKTSM & ~(CCAP_PKTSM_PKTSHNH_Msk | CCAP_PKTSM_PKTSHMH_Msk)) + | ((u32NumeratorH << CCAP_PKTSL_PKTSHNL_Pos) | (u32DenominatorH << CCAP_PKTSL_PKTSHML_Pos)); +} + +/** + * @brief Set Planar Scaling Factor + * + * @param[in] u32VNumerator: Planar Scaling Vertical Factor N. It should be 0x0 ~ 0xFFFF. + * @param[in] u32VDenominator: Planar Scaling Vertical Factor M. It should be 0x0 ~ 0xFFFF. + * @param[in] u32HNumerator: Planar Scaling Horizontal Factor N. It should be 0x0 ~ 0xFFFF. + * @param[in] u32HDenominator: Planar Scaling Horizontal Factor M. It should be 0x0 ~ 0xFFFF. + * + * @return None + * + * @details This function is used to set Planar Scaling Vertical and Horizontal Factor register. + */ +void CCAP_SetPlanarScaling(CCAP_T *ccap, uint32_t u32VNumerator, uint32_t u32VDenominator, uint32_t u32HNumerator, uint32_t u32HDenominator) +{ + uint32_t u32NumeratorL, u32NumeratorH; + uint32_t u32DenominatorL, u32DenominatorH; + + u32NumeratorL = u32VNumerator & 0xFF; + u32NumeratorH = u32VNumerator >> 8; + u32DenominatorL = u32VDenominator & 0xFF; + u32DenominatorH = u32VDenominator >> 8; + ccap->PLNSL = (ccap->PLNSL & ~(CCAP_PLNSL_PLNSVNL_Msk | CCAP_PLNSL_PLNSVML_Msk)) + | ((u32NumeratorL << CCAP_PLNSL_PLNSVNL_Pos) | (u32DenominatorL << CCAP_PLNSL_PLNSVML_Pos)); + ccap->PLNSM = (ccap->PLNSM & ~(CCAP_PLNSM_PLNSVNH_Msk | CCAP_PLNSM_PLNSVMH_Msk)) + | ((u32NumeratorH << CCAP_PLNSL_PLNSVNL_Pos) | (u32DenominatorH << CCAP_PLNSL_PLNSVML_Pos)); + + u32NumeratorL = u32HNumerator & 0xFF; + u32NumeratorH = u32HNumerator >> 8; + u32DenominatorL = u32HDenominator & 0xFF; + u32DenominatorH = u32HDenominator >> 8; + ccap->PLNSL = (ccap->PLNSL & ~(CCAP_PLNSL_PLNSHNL_Msk | CCAP_PLNSL_PLNSHML_Msk)) + | ((u32NumeratorL << CCAP_PLNSL_PLNSHNL_Pos) | (u32DenominatorL << CCAP_PLNSL_PLNSHML_Pos)); + ccap->PLNSM = (ccap->PLNSM & ~(CCAP_PLNSM_PLNSHNH_Msk | CCAP_PLNSM_PLNSHMH_Msk)) + | ((u32NumeratorH << CCAP_PLNSL_PLNSHNL_Pos) | (u32DenominatorH << CCAP_PLNSL_PLNSHML_Pos)); +} + +/** + * @brief Set Packet Frame Output Pixel Stride Width + * + * @param[in] u32Stride: Set CCAP_STRIDE register. It should be 0x0 ~ 0x3FFF. + * + * @return None + * + * @details This function is used to set Packet Frame Output Pixel Stride Width. + */ +void CCAP_SetPacketStride(CCAP_T *ccap, uint32_t u32Stride) +{ + ccap->STRIDE = (ccap->STRIDE & ~CCAP_STRIDE_PKTSTRIDE_Msk) | (u32Stride << CCAP_STRIDE_PKTSTRIDE_Pos); +} + +/** + * @brief Set Planar Frame Output Pixel Stride Width + * + * @param[in] u32Stride: Set CCAP_STRIDE register. It should be 0x0 ~ 0x3FFF. + * + * @return None + * + * @details This function is used to set Planar Frame Output Pixel Stride Width. + */ +void CCAP_SetPlanarStride(CCAP_T *ccap, uint32_t u32Stride) +{ + ccap->STRIDE = (ccap->STRIDE & ~CCAP_STRIDE_PLNSTRIDE_Msk) | (u32Stride << CCAP_STRIDE_PLNSTRIDE_Pos); +} + + +/*@}*/ /* end of group CCAP_EXPORTED_FUNCTIONS */ + +/*@}*/ /* end of group CCAP_Driver */ + +/*@}*/ /* end of group Standard_Driver */ diff --git a/bsp/nuvoton/libraries/ma35/StdDriver/src/nu_clk.c b/bsp/nuvoton/libraries/ma35/StdDriver/src/nu_clk.c new file mode 100644 index 0000000000..50b1637c8c --- /dev/null +++ b/bsp/nuvoton/libraries/ma35/StdDriver/src/nu_clk.c @@ -0,0 +1,1763 @@ +/**************************************************************************//** + * @file clk.c + * @brief series CLK driver source file + * + * SPDX-License-Identifier: Apache-2.0 + * @copyright (C) 2020 Nuvoton Technology Corp. All rights reserved. + *****************************************************************************/ + +#include "NuMicro.h" + +/** @addtogroup Standard_Driver Standard Driver + @{ +*/ + +/** @addtogroup CLK_Driver CLK Driver + @{ +*/ + +/** @addtogroup CLK_EXPORTED_FUNCTIONS CLK Exported Functions + @{ +*/ +#define SYSPLLFREQCLK FREQ_180MHZ + +/** + * @brief Disable clock divider output function + * @param None + * @return None + * @details This function disable clock divider output function. + */ +void CLK_DisableCKO(void) +{ + /* Disable CKO clock source */ + CLK_DisableModuleClock(CLKO_MODULE); +} + +/** + * @brief This function enable clock divider output module clock, + * enable clock divider output function and set frequency selection. + * @param[in] u32ClkSrc is frequency divider function clock source. Including : + * - \ref CLK_CLKSEL4_CKOSEL_HXT + * - \ref CLK_CLKSEL4_CKOSEL_LXT + * - \ref CLK_CLKSEL4_CKOSEL_LIRC + * - \ref CLK_CLKSEL4_CKOSEL_HIRC + * - \ref CLK_CLKSEL4_CKOSEL_CAPLL + * - \ref CLK_CLKSEL4_CKOSEL_SYSPLL + * - \ref CLK_CLKSEL4_CKOSEL_APLL + * - \ref CLK_CLKSEL4_CKOSEL_EPLL + * - \ref CLK_CLKSEL4_CKOSEL_VPLL + * @param[in] u32ClkDiv is divider output frequency selection. It could be 0~15. + * @param[in] u32ClkDivBy1En is clock divided by one enabled. + * @return None + * @details Output selected clock to CKO. The output clock frequency is divided by u32ClkDiv. \n + * The formula is: \n + * CKO frequency = (Clock source frequency) / 2^(u32ClkDiv + 1) \n + * This function is just used to set CKO clock. + * User must enable I/O for CKO clock output pin by themselves. \n + */ +void CLK_EnableCKO(uint32_t u32ClkSrc, uint32_t u32ClkDiv, uint32_t u32ClkDivBy1En) +{ + /* CKO = clock source / 2^(u32ClkDiv + 1) */ + CLK->CLKOCTL = CLK_CLKOCTL_CLKOEN_Msk | (u32ClkDiv) | (u32ClkDivBy1En << CLK_CLKOCTL_DIV1EN_Pos); + + /* Enable CKO clock source */ + CLK_EnableModuleClock(CLKO_MODULE); + + /* Select CKO clock source */ + CLK_SetModuleClock(CLKO_MODULE, u32ClkSrc, 0UL); +} + +#if defined(USE_MA35D1_SUBM) +/** + * @brief Enter to Power-down mode + * @param None + * @return None + * @details This function is used to let system enter to Power-down mode. \n + * The register write-protection function should be disabled before using this function. + */ +void CLK_PowerDown(void) +{ + /* Set the processor uses deep sleep as its low power mode */ + SCB->SCR |= SCB_SCR_SLEEPDEEP_Msk; + + /* Set system Power-down enabled */ + SYS->PMUCR |= (SYS_PMUCR_RTPPDEN_Msk); + + /* Chip enter Power-down mode after CPU run WFI instruction */ + __WFI(); + +} + +/** + * @brief Enter to Idle mode + * @param None + * @return None + * @details This function let system enter to Idle mode. \n + * The register write-protection function should be disabled before using this function. + */ +void CLK_Idle(void) +{ + /* Set the processor uses sleep as its low power mode */ + SCB->SCR &= ~SCB_SCR_SLEEPDEEP_Msk; + + /* Set chip in idle mode because of WFI command */ + SYS->PMUCR &= ~(SYS_PMUCR_RTPPDEN_Msk); + + /* Chip enter idle mode after CPU run WFI instruction */ + __WFI(); +} +#else +void SystemCoreClockUpdate(void) +{ + +} +#endif + +/** + * @brief Get external high speed crystal clock frequency + * @param None + * @return External high frequency crystal frequency + * @details This function get external high frequency crystal frequency. The frequency unit is Hz. + */ +uint32_t CLK_GetHXTFreq(void) +{ + uint32_t u32Freq; + + if ((CLK->PWRCTL & CLK_PWRCTL_HXTEN_Msk) == CLK_PWRCTL_HXTEN_Msk) + { + u32Freq = __HXT; + } + else + { + u32Freq = 0UL; + } + + return u32Freq; +} + + +/** + * @brief Get external low speed crystal clock frequency + * @param None + * @return External low speed crystal clock frequency + * @details This function get external low frequency crystal frequency. The frequency unit is Hz. + */ +uint32_t CLK_GetLXTFreq(void) +{ + uint32_t u32Freq; + + if ((CLK->PWRCTL & CLK_PWRCTL_LXTEN_Msk) == CLK_PWRCTL_LXTEN_Msk) + { + u32Freq = __LXT; + } + else + { + u32Freq = 0UL; + } + + return u32Freq; +} + +/** + * @brief Get SYSCLK0 frequency + * @param None + * @return SYSCLK0 frequency + * @details This function get SYSCLK0 frequency. The frequency unit is Hz. + */ +uint32_t CLK_GetSYSCLK0Freq(void) +{ + uint32_t u32Freq; + + if ((CLK->CLKSEL0 & CLK_CLKSEL0_SYSCK0SEL_Msk) == CLK_CLKSEL0_SYSCK0SEL_EPLL_DIV2) + { + u32Freq = CLK_GetPLLClockFreq(EPLL) / 2; + } + else + { + u32Freq = SYSPLLFREQCLK; + } + + return u32Freq; +} + +/** + * @brief Get SYSCLK1 frequency + * @param None + * @return SYSCLK1 frequency + * @details This function get SYSCLK1 frequency. The frequency unit is Hz. + */ +uint32_t CLK_GetSYSCLK1Freq(void) +{ + uint32_t u32Freq; + + if ((CLK->CLKSEL0 & CLK_CLKSEL0_SYSCK1SEL_Msk) == CLK_CLKSEL0_SYSCK1SEL_HXT) + { + u32Freq = __HXT; + } + else + { + u32Freq = SYSPLLFREQCLK; + } + + return u32Freq; +} + +/** + * @brief Get CPU frequency + * @param None + * @return CPU frequency + * @details This function get CPU frequency. The frequency unit is Hz. + */ +uint32_t CLK_GetCPUFreq(void) +{ + return CLK_GetSYSCLK1Freq(); +} + +/** + * @brief Set HCLK frequency + * @param[in] u32Hclk is HCLK frequency. The range of u32Hclk is running up to 180MHz. + * @return HCLK frequency + * @details This function is used to set HCLK frequency. The frequency unit is Hz. \n + * The register write-protection function should be disabled before using this function. + */ +uint32_t CLK_SetCoreClock(uint32_t u32Hclk) +{ + /* The range of u32Hclk is running up to SYSPLLFREQCLK MHz */ + if (u32Hclk > SYSPLLFREQCLK) + { + u32Hclk = SYSPLLFREQCLK; + } + + /* Return actually HCLK frequency is PLL frequency divide 1 */ + return u32Hclk; +} + +/** + * @brief This function set HCLK clock source and HCLK clock divider + * @param[in] u32ClkSrc is HCLK clock source. Including : + * - \ref CLK_CLKSEL0_HCLKSEL_HXT + * - \ref CLK_CLKSEL0_HCLKSEL_LXT + * - \ref CLK_CLKSEL0_HCLKSEL_PLL + * - \ref CLK_CLKSEL0_HCLKSEL_LIRC + * - \ref CLK_CLKSEL0_HCLKSEL_HIRC + * @param[in] u32ClkDiv is HCLK clock divider. Including : + * - \ref CLK_CLKDIV0_HCLK(x) + * @return None + * @details This function set HCLK clock source and HCLK clock divider. \n + * The register write-protection function should be disabled before using this function. + */ +void CLK_SetHCLK(uint32_t u32ClkSrc, uint32_t u32ClkDiv) +{ +} + +/** + * @brief This function set selected module clock source and module clock divider + * @param[in] u32ModuleIdx is module index. + * @param[in] u32ClkSrc is module clock source. + * @param[in] u32ClkDiv is module clock divider. + * @return None + * @details Valid parameter combinations listed in following table: + * + * |Module index |Clock source |Divider | + * | :---------------- | :----------------------------------- | :------------------------ | + * |\ref CA35CK_MODULE |\ref CLK_CLKSEL0_CA35CKSEL_HXT | x | + * |\ref CA35CK_MODULE |\ref CLK_CLKSEL0_CA35CKSEL_CAPLL | x | + * |\ref SYSCK0_MODULE |\ref CLK_CLKSEL0_SYSCK0SEL_SYSPLL | x | + * |\ref SYSCK0_MODULE |\ref CLK_CLKSEL0_SYSCK0SEL_EPLL | x | + * |\ref LVRDB_MODULE |\ref CLK_CLKSEL0_LVRDBSEL_LIRC | x | + * |\ref LVRDB_MODULE |\ref CLK_CLKSEL0_LVRDBSEL_HIRC | x | + * |\ref SYSCK1_MODULE |\ref CLK_CLKSEL0_SYSCK1SEL_HXT | x | + * |\ref SYSCK1_MODULE |\ref CLK_CLKSEL0_SYSCK1SEL_SYSPLL | x | + * |\ref RTPST_MODULE |\ref CLK_CLKSEL0_RTPSTSEL_HXT | x | + * |\ref RTPST_MODULE |\ref CLK_CLKSEL0_RTPSTSEL_LXT | x | + * |\ref RTPST_MODULE |\ref CLK_CLKSEL0_RTPSTSEL_HXT_DIV2 | x | + * |\ref RTPST_MODULE |\ref CLK_CLKSEL0_RTPSTSEL_SYSCLK1_DIV2 | x | + * |\ref RTPST_MODULE |\ref CLK_CLKSEL0_RTPSTSEL_HIRC | x | + * |\ref CCAP0_MODULE |\ref CLK_CLKSEL0_CCAP0SEL_HXT |\ref CLK_CLKDIV1_CCAP0(x) | + * |\ref CCAP0_MODULE |\ref CLK_CLKSEL0_CCAP0SEL_SYSPLL |\ref CLK_CLKDIV1_CCAP0(x) | + * |\ref CCAP0_MODULE |\ref CLK_CLKSEL0_CCAP0SEL_APLL |\ref CLK_CLKDIV1_CCAP0(x) | + * |\ref CCAP0_MODULE |\ref CLK_CLKSEL0_CCAP0SEL_VPLL |\ref CLK_CLKDIV1_CCAP0(x) | + * |\ref CCAP1_MODULE |\ref CLK_CLKSEL0_CCAP1SEL_HXT |\ref CLK_CLKDIV1_CCAP1(x) | + * |\ref CCAP1_MODULE |\ref CLK_CLKSEL0_CCAP1SEL_SYSPLL |\ref CLK_CLKDIV1_CCAP1(x) | + * |\ref CCAP1_MODULE |\ref CLK_CLKSEL0_CCAP1SEL_APLL |\ref CLK_CLKDIV1_CCAP1(x) | + * |\ref CCAP1_MODULE |\ref CLK_CLKSEL0_CCAP1SEL_VPLL |\ref CLK_CLKDIV1_CCAP1(x) | + * |\ref SD0_MODULE |\ref CLK_CLKSEL0_SD0SEL_SYSPLL | x | + * |\ref SD0_MODULE |\ref CLK_CLKSEL0_SD0SEL_APLL | x | + * |\ref SD1_MODULE |\ref CLK_CLKSEL0_SD1SEL_SYSPLL | x | + * |\ref SD1_MODULE |\ref CLK_CLKSEL0_SD1SEL_APLL | x | + * |\ref DCU_MODULE |\ref CLK_CLKSEL0_DCUSEL_SYSPLL | x | + * |\ref DCU_MODULE |\ref CLK_CLKSEL0_DCUSEL_EPLL | x | + * |\ref GFX_MODULE |\ref CLK_CLKSEL0_GFXSEL_SYSPLL | x | + * |\ref GFX_MODULE |\ref CLK_CLKSEL0_GFXSEL_EPLL | x | + * |\ref DBG_MODULE |\ref CLK_CLKSEL0_DBGSEL_HIRC |\ref CLK_CLKDIV3_DBG(x) | + * |\ref DBG_MODULE |\ref CLK_CLKSEL0_DBGSEL_SYSPLL |\ref CLK_CLKDIV3_DBG(x) | + * |\ref TMR0_MODULE |\ref CLK_CLKSEL1_TMR0SEL_HXT | x | + * |\ref TMR0_MODULE |\ref CLK_CLKSEL1_TMR0SEL_LXT | x | + * |\ref TMR0_MODULE |\ref CLK_CLKSEL1_TMR0SEL_LIRC | x | + * |\ref TMR0_MODULE |\ref CLK_CLKSEL1_TMR0SEL_HIRC | x | + * |\ref TMR0_MODULE |\ref CLK_CLKSEL1_TMR0SEL_PCLK0 | x | + * |\ref TMR0_MODULE |\ref CLK_CLKSEL1_TMR0SEL_EXT | x | + * |\ref TMR1_MODULE |\ref CLK_CLKSEL1_TMR1SEL_HXT | x | + * |\ref TMR1_MODULE |\ref CLK_CLKSEL1_TMR1SEL_LXT | x | + * |\ref TMR1_MODULE |\ref CLK_CLKSEL1_TMR1SEL_LIRC | x | + * |\ref TMR1_MODULE |\ref CLK_CLKSEL1_TMR1SEL_HIRC | x | + * |\ref TMR1_MODULE |\ref CLK_CLKSEL1_TMR1SEL_PCLK0 | x | + * |\ref TMR1_MODULE |\ref CLK_CLKSEL1_TMR1SEL_EXT | x | + * |\ref TMR2_MODULE |\ref CLK_CLKSEL1_TMR2SEL_HXT | x | + * |\ref TMR2_MODULE |\ref CLK_CLKSEL1_TMR2SEL_LXT | x | + * |\ref TMR2_MODULE |\ref CLK_CLKSEL1_TMR2SEL_LIRC | x | + * |\ref TMR2_MODULE |\ref CLK_CLKSEL1_TMR2SEL_HIRC | x | + * |\ref TMR2_MODULE |\ref CLK_CLKSEL1_TMR2SEL_PCLK1 | x | + * |\ref TMR2_MODULE |\ref CLK_CLKSEL1_TMR2SEL_EXT | x | + * |\ref TMR3_MODULE |\ref CLK_CLKSEL1_TMR3SEL_HXT | x | + * |\ref TMR3_MODULE |\ref CLK_CLKSEL1_TMR3SEL_LXT | x | + * |\ref TMR3_MODULE |\ref CLK_CLKSEL1_TMR3SEL_LIRC | x | + * |\ref TMR3_MODULE |\ref CLK_CLKSEL1_TMR3SEL_HIRC | x | + * |\ref TMR3_MODULE |\ref CLK_CLKSEL1_TMR3SEL_PCLK1 | x | + * |\ref TMR3_MODULE |\ref CLK_CLKSEL1_TMR3SEL_EXT | x | + * |\ref TMR4_MODULE |\ref CLK_CLKSEL1_TMR4SEL_HXT | x | + * |\ref TMR4_MODULE |\ref CLK_CLKSEL1_TMR4SEL_LXT | x | + * |\ref TMR4_MODULE |\ref CLK_CLKSEL1_TMR4SEL_LIRC | x | + * |\ref TMR4_MODULE |\ref CLK_CLKSEL1_TMR4SEL_HIRC | x | + * |\ref TMR4_MODULE |\ref CLK_CLKSEL1_TMR4SEL_EXT | x | + * |\ref TMR4_MODULE |\ref CLK_CLKSEL1_TMR4SEL_PCLK2 | x | + * |\ref TMR5_MODULE |\ref CLK_CLKSEL1_TMR5SEL_HXT | x | + * |\ref TMR5_MODULE |\ref CLK_CLKSEL1_TMR5SEL_LXT | x | + * |\ref TMR5_MODULE |\ref CLK_CLKSEL1_TMR5SEL_LIRC | x | + * |\ref TMR5_MODULE |\ref CLK_CLKSEL1_TMR5SEL_HIRC | x | + * |\ref TMR5_MODULE |\ref CLK_CLKSEL1_TMR5SEL_EXT | x | + * |\ref TMR5_MODULE |\ref CLK_CLKSEL1_TMR5SEL_PCLK2 | x | + * |\ref TMR6_MODULE |\ref CLK_CLKSEL1_TMR6SEL_HXT | x | + * |\ref TMR6_MODULE |\ref CLK_CLKSEL1_TMR6SEL_LXT | x | + * |\ref TMR6_MODULE |\ref CLK_CLKSEL1_TMR6SEL_LIRC | x | + * |\ref TMR6_MODULE |\ref CLK_CLKSEL1_TMR6SEL_HIRC | x | + * |\ref TMR6_MODULE |\ref CLK_CLKSEL1_TMR6SEL_PCLK0 | x | + * |\ref TMR6_MODULE |\ref CLK_CLKSEL1_TMR6SEL_EXT | x | + * |\ref TMR7_MODULE |\ref CLK_CLKSEL1_TMR7SEL_HXT | x | + * |\ref TMR7_MODULE |\ref CLK_CLKSEL1_TMR7SEL_LXT | x | + * |\ref TMR7_MODULE |\ref CLK_CLKSEL1_TMR7SEL_LIRC | x | + * |\ref TMR7_MODULE |\ref CLK_CLKSEL1_TMR7SEL_HIRC | x | + * |\ref TMR7_MODULE |\ref CLK_CLKSEL1_TMR7SEL_PCLK0 | x | + * |\ref TMR7_MODULE |\ref CLK_CLKSEL1_TMR7SEL_EXT | x | + * |\ref TMR8_MODULE |\ref CLK_CLKSEL2_TMR8SEL_HXT | x | + * |\ref TMR8_MODULE |\ref CLK_CLKSEL2_TMR8SEL_LXT | x | + * |\ref TMR8_MODULE |\ref CLK_CLKSEL2_TMR8SEL_LIRC | x | + * |\ref TMR8_MODULE |\ref CLK_CLKSEL2_TMR8SEL_HIRC | x | + * |\ref TMR8_MODULE |\ref CLK_CLKSEL2_TMR8SEL_PCLK1 | x | + * |\ref TMR8_MODULE |\ref CLK_CLKSEL2_TMR8SEL_EXT | x | + * |\ref TMR9_MODULE |\ref CLK_CLKSEL2_TMR9SEL_HXT | x | + * |\ref TMR9_MODULE |\ref CLK_CLKSEL2_TMR9SEL_LXT | x | + * |\ref TMR9_MODULE |\ref CLK_CLKSEL2_TMR9SEL_LIRC | x | + * |\ref TMR9_MODULE |\ref CLK_CLKSEL2_TMR9SEL_HIRC | x | + * |\ref TMR9_MODULE |\ref CLK_CLKSEL2_TMR9SEL_PCLK1 | x | + * |\ref TMR9_MODULE |\ref CLK_CLKSEL2_TMR9SEL_EXT | x | + * |\ref TMR10_MODULE |\ref CLK_CLKSEL2_TMR10SEL_HXT | x | + * |\ref TMR10_MODULE |\ref CLK_CLKSEL2_TMR10SEL_LXT | x | + * |\ref TMR10_MODULE |\ref CLK_CLKSEL2_TMR10SEL_LIRC | x | + * |\ref TMR10_MODULE |\ref CLK_CLKSEL2_TMR10SEL_HIRC | x | + * |\ref TMR10_MODULE |\ref CLK_CLKSEL2_TMR10SEL_EXT | x | + * |\ref TMR10_MODULE |\ref CLK_CLKSEL2_TMR10SEL_PCLK2 | x | + * |\ref TMR11_MODULE |\ref CLK_CLKSEL2_TMR11SEL_HXT | x | + * |\ref TMR11_MODULE |\ref CLK_CLKSEL2_TMR11SEL_LXT | x | + * |\ref TMR11_MODULE |\ref CLK_CLKSEL2_TMR11SEL_LIRC | x | + * |\ref TMR11_MODULE |\ref CLK_CLKSEL2_TMR11SEL_HIRC | x | + * |\ref TMR11_MODULE |\ref CLK_CLKSEL2_TMR11SEL_EXT | x | + * |\ref TMR11_MODULE |\ref CLK_CLKSEL2_TMR11SEL_PCLK2 | x | + * |\ref UART0_MODULE |\ref CLK_CLKSEL2_UART0SEL_HXT |\ref CLK_CLKDIV1_UART0(x) | + * |\ref UART0_MODULE |\ref CLK_CLKSEL2_UART0SEL_SYSCLK1 |\ref CLK_CLKDIV1_UART0(x) | + * |\ref UART1_MODULE |\ref CLK_CLKSEL2_UART1SEL_HXT |\ref CLK_CLKDIV1_UART1(x) | + * |\ref UART1_MODULE |\ref CLK_CLKSEL2_UART1SEL_SYSCLK1 |\ref CLK_CLKDIV1_UART1(x) | + * |\ref UART2_MODULE |\ref CLK_CLKSEL2_UART2SEL_HXT |\ref CLK_CLKDIV1_UART2(x) | + * |\ref UART2_MODULE |\ref CLK_CLKSEL2_UART2SEL_SYSCLK1 |\ref CLK_CLKDIV1_UART2(x) | + * |\ref UART3_MODULE |\ref CLK_CLKSEL2_UART3SEL_HXT |\ref CLK_CLKDIV1_UART3(x) | + * |\ref UART3_MODULE |\ref CLK_CLKSEL2_UART3SEL_SYSCLK1 |\ref CLK_CLKDIV1_UART3(x) | + * |\ref UART4_MODULE |\ref CLK_CLKSEL2_UART4SEL_HXT |\ref CLK_CLKDIV2_UART4(x) | + * |\ref UART4_MODULE |\ref CLK_CLKSEL2_UART4SEL_SYSCLK1 |\ref CLK_CLKDIV2_UART4(x) | + * |\ref UART5_MODULE |\ref CLK_CLKSEL2_UART5SEL_HXT |\ref CLK_CLKDIV2_UART5(x) | + * |\ref UART5_MODULE |\ref CLK_CLKSEL2_UART5SEL_SYSCLK1 |\ref CLK_CLKDIV2_UART5(x) | + * |\ref UART6_MODULE |\ref CLK_CLKSEL2_UART6SEL_HXT |\ref CLK_CLKDIV2_UART6(x) | + * |\ref UART6_MODULE |\ref CLK_CLKSEL2_UART6SEL_SYSCLK1 |\ref CLK_CLKDIV2_UART6(x) | + * |\ref UART7_MODULE |\ref CLK_CLKSEL2_UART7SEL_HXT |\ref CLK_CLKDIV2_UART7(x) | + * |\ref UART7_MODULE |\ref CLK_CLKSEL2_UART7SEL_SYSCLK1 |\ref CLK_CLKDIV2_UART7(x) | + * |\ref UART8_MODULE |\ref CLK_CLKSEL3_UART8SEL_HXT |\ref CLK_CLKDIV2_UART8(x) | + * |\ref UART8_MODULE |\ref CLK_CLKSEL3_UART8SEL_SYSCLK1 |\ref CLK_CLKDIV2_UART8(x) | + * |\ref UART9_MODULE |\ref CLK_CLKSEL3_UART9SEL_HXT |\ref CLK_CLKDIV2_UART9(x) | + * |\ref UART9_MODULE |\ref CLK_CLKSEL3_UART9SEL_SYSCLK1 |\ref CLK_CLKDIV2_UART9(x) | + * |\ref UART10_MODULE |\ref CLK_CLKSEL3_UART10SEL_HXT |\ref CLK_CLKDIV1_UART1(x) | + * |\ref UART10_MODULE |\ref CLK_CLKSEL3_UART10SEL_SYSCLK1 |\ref CLK_CLKDIV1_UART1(x) | + * |\ref UART11_MODULE |\ref CLK_CLKSEL3_UART11SEL_HXT |\ref CLK_CLKDIV1_UART1(x) | + * |\ref UART11_MODULE |\ref CLK_CLKSEL3_UART11SEL_SYSCLK1 |\ref CLK_CLKDIV1_UART1(x) | + * |\ref UART12_MODULE |\ref CLK_CLKSEL3_UART12SEL_HXT |\ref CLK_CLKDIV1_UART1(x) | + * |\ref UART12_MODULE |\ref CLK_CLKSEL3_UART12SEL_SYSCLK1 |\ref CLK_CLKDIV1_UART1(x) | + * |\ref UART13_MODULE |\ref CLK_CLKSEL3_UART13SEL_HXT |\ref CLK_CLKDIV1_UART1(x) | + * |\ref UART13_MODULE |\ref CLK_CLKSEL3_UART13SEL_SYSCLK1 |\ref CLK_CLKDIV1_UART1(x) | + * |\ref UART14_MODULE |\ref CLK_CLKSEL3_UART14SEL_HXT |\ref CLK_CLKDIV1_UART1(x) | + * |\ref UART14_MODULE |\ref CLK_CLKSEL3_UART14SEL_SYSCLK1 |\ref CLK_CLKDIV1_UART1(x) | + * |\ref UART15_MODULE |\ref CLK_CLKSEL3_UART15SEL_HXT |\ref CLK_CLKDIV1_UART1(x) | + * |\ref UART15_MODULE |\ref CLK_CLKSEL3_UART15SEL_SYSCLK1 |\ref CLK_CLKDIV1_UART1(x) | + * |\ref UART16_MODULE |\ref CLK_CLKSEL3_UART16SEL_HXT |\ref CLK_CLKDIV1_UART1(x) | + * |\ref UART16_MODULE |\ref CLK_CLKSEL3_UART16SEL_SYSCLK1 |\ref CLK_CLKDIV1_UART1(x) | + * |\ref WDT0_MODULE |\ref CLK_CLKSEL3_WDT0SEL_HXT | x | + * |\ref WDT0_MODULE |\ref CLK_CLKSEL3_WDT0SEL_LXT | x | + * |\ref WDT0_MODULE |\ref CLK_CLKSEL3_WDT0SEL_LIRC | x | + * |\ref WDT0_MODULE |\ref CLK_CLKSEL3_WDT0SEL_PCLK3 | x | + * |\ref WWDT0_MODULE |\ref CLK_CLKSEL3_WWDT0SEL_HXT | x | + * |\ref WWDT0_MODULE |\ref CLK_CLKSEL3_WWDT0SEL_LXT | x | + * |\ref WWDT0_MODULE |\ref CLK_CLKSEL3_WWDT0SEL_LIRC | x | + * |\ref WWDT0_MODULE |\ref CLK_CLKSEL3_WWDT0SEL_PCLK3 | x | + * |\ref WDT1_MODULE |\ref CLK_CLKSEL3_WDT1SEL_HXT | x | + * |\ref WDT1_MODULE |\ref CLK_CLKSEL3_WDT1SEL_LXT | x | + * |\ref WDT1_MODULE |\ref CLK_CLKSEL3_WDT1SEL_LIRC | x | + * |\ref WDT1_MODULE |\ref CLK_CLKSEL3_WDT1SEL_PCLK3 | x | + * |\ref WWDT1_MODULE |\ref CLK_CLKSEL3_WWDT1SEL_HXT | x | + * |\ref WWDT1_MODULE |\ref CLK_CLKSEL3_WWDT1SEL_LXT | x | + * |\ref WWDT1_MODULE |\ref CLK_CLKSEL3_WWDT1SEL_LIRC | x | + * |\ref WWDT1_MODULE |\ref CLK_CLKSEL3_WWDT1SEL_PCLK3 | x | + * |\ref WDT2_MODULE |\ref CLK_CLKSEL3_WDT2SEL_HXT | x | + * |\ref WDT2_MODULE |\ref CLK_CLKSEL3_WDT2SEL_LXT | x | + * |\ref WDT2_MODULE |\ref CLK_CLKSEL3_WDT2SEL_LIRC | x | + * |\ref WDT2_MODULE |\ref CLK_CLKSEL3_WDT2SEL_PCLK4 | x | + * |\ref WWDT2_MODULE |\ref CLK_CLKSEL3_WWDT2SEL_HXT | x | + * |\ref WWDT2_MODULE |\ref CLK_CLKSEL3_WWDT2SEL_LXT | x | + * |\ref WWDT2_MODULE |\ref CLK_CLKSEL3_WWDT2SEL_LIRC | x | + * |\ref WWDT2_MODULE |\ref CLK_CLKSEL3_WWDT2SEL_PCLK4 | x | + * |\ref SPI0_MODULE |\ref CLK_CLKSEL4_SPI0SEL_PCLK1 | x | + * |\ref SPI0_MODULE |\ref CLK_CLKSEL4_SPI0SEL_APLL | x | + * |\ref SPI1_MODULE |\ref CLK_CLKSEL4_SPI1SEL_APLL | x | + * |\ref SPI1_MODULE |\ref CLK_CLKSEL4_SPI1SEL_PCLK2 | x | + * |\ref SPI2_MODULE |\ref CLK_CLKSEL4_SPI2SEL_PCLK1 | x | + * |\ref SPI2_MODULE |\ref CLK_CLKSEL4_SPI2SEL_APLL | x | + * |\ref SPI3_MODULE |\ref CLK_CLKSEL4_SPI3SEL_APLL | x | + * |\ref SPI3_MODULE |\ref CLK_CLKSEL4_SPI3SEL_PCLK2 | x | + * |\ref QSPI0_MODULE |\ref CLK_CLKSEL4_QSPI0SEL_PCLK0 | x | + * |\ref QSPI0_MODULE |\ref CLK_CLKSEL4_QSPI0SEL_APLL | x | + * |\ref QSPI1_MODULE |\ref CLK_CLKSEL4_QSPI1SEL_PCLK0 | x | + * |\ref QSPI1_MODULE |\ref CLK_CLKSEL4_QSPI1SEL_APLL | x | + * |\ref I2S0_MODULE |\ref CLK_CLKSEL4_I2S0SEL_APLL | x | + * |\ref I2S0_MODULE |\ref CLK_CLKSEL4_I2S0SEL_SYSCLK1 | x | + * |\ref I2S1_MODULE |\ref CLK_CLKSEL4_I2S1SEL_APLL | x | + * |\ref I2S1_MODULE |\ref CLK_CLKSEL4_I2S1SEL_SYSCLK1 | x | + * |\ref CANFD0_MODULE |\ref CLK_CLKSEL4_CANFD0SEL_APLL |\ref CLK_CLKDIV0_CANFD0(x) | + * |\ref CANFD0_MODULE |\ref CLK_CLKSEL4_CANFD0SEL_VPLL |\ref CLK_CLKDIV0_CANFD0(x) | + * |\ref CANFD1_MODULE |\ref CLK_CLKSEL4_CANFD1SEL_APLL |\ref CLK_CLKDIV0_CANFD1(x) | + * |\ref CANFD1_MODULE |\ref CLK_CLKSEL4_CANFD1SEL_VPLL |\ref CLK_CLKDIV0_CANFD1(x) | + * |\ref CANFD2_MODULE |\ref CLK_CLKSEL4_CANFD2SEL_APLL |\ref CLK_CLKDIV0_CANFD2(x) | + * |\ref CANFD2_MODULE |\ref CLK_CLKSEL4_CANFD2SEL_VPLL |\ref CLK_CLKDIV0_CANFD2(x) | + * |\ref CANFD3_MODULE |\ref CLK_CLKSEL4_CANFD3SEL_APLL |\ref CLK_CLKDIV0_CANFD3(x) | + * |\ref CANFD3_MODULE |\ref CLK_CLKSEL4_CANFD3SEL_VPLL |\ref CLK_CLKDIV0_CANFD3(x) | + * |\ref CLKO_MODULE |\ref CLK_CLKSEL4_CKOSEL_HXT | x | + * |\ref CLKO_MODULE |\ref CLK_CLKSEL4_CKOSEL_LXT | x | + * |\ref CLKO_MODULE |\ref CLK_CLKSEL4_CKOSEL_LIRC | x | + * |\ref CLKO_MODULE |\ref CLK_CLKSEL4_CKOSEL_HIRC | x | + * |\ref CLKO_MODULE |\ref CLK_CLKSEL4_CKOSEL_CAPLL | x | + * |\ref CLKO_MODULE |\ref CLK_CLKSEL4_CKOSEL_SYSPLL | x | + * |\ref CLKO_MODULE |\ref CLK_CLKSEL4_CKOSEL_APLL | x | + * |\ref CLKO_MODULE |\ref CLK_CLKSEL4_CKOSEL_EPLL | x | + * |\ref CLKO_MODULE |\ref CLK_CLKSEL4_CKOSEL_VPLL | x | + * |\ref SC0_MODULE |\ref CLK_CLKSEL4_SC0SEL_HXT |\ref CLK_CLKDIV1_SC0(x) | + * |\ref SC0_MODULE |\ref CLK_CLKSEL4_SC0SEL_PCLK4 |\ref CLK_CLKDIV1_SC0(x) | + * |\ref SC1_MODULE |\ref CLK_CLKSEL4_SC1SEL_HXT |\ref CLK_CLKDIV1_SC1(x) | + * |\ref SC1_MODULE |\ref CLK_CLKSEL4_SC1SEL_PCLK4 |\ref CLK_CLKDIV1_SC1(x) | + * |\ref KPI_MODULE |\ref CLK_CLKSEL4_KPISEL_HXT |\ref CLK_CLKDIV4_KPI(x) | + * |\ref KPI_MODULE |\ref CLK_CLKSEL4_KPISEL_LXT |\ref CLK_CLKDIV4_KPI(x) | + * |\ref CA35CK_MODULE |\ref CLK_CLKSEL0_CA35CKSEL_HXT | x | + * |\ref CA35CK_MODULE |\ref CLK_CLKSEL0_CA35CKSEL_CAPLL | x | + + * + */ +void CLK_SetModuleClock(uint32_t u32ModuleIdx, uint32_t u32ClkSrc, uint32_t u32ClkDiv) +{ + uint32_t u32sel = 0U, u32div = 0U; + + if (u32ModuleIdx == KPI_MODULE) + { + CLK->CLKDIV4 = (CLK->CLKDIV4 & ~(CLK_CLKDIV4_KPIDIV_Msk)) | u32ClkDiv; + CLK->CLKSEL4 = (CLK->CLKSEL4 & ~(CLK_CLKSEL4_KPISEL_Msk)) | u32ClkSrc; + CLK->APBCLK0 = (CLK->APBCLK0 & ~(CLK_APBCLK0_KPICKEN_Msk)) | CLK_APBCLK0_KPICKEN_Msk; + } + else if (u32ModuleIdx == ADC_MODULE) + { + CLK->CLKDIV4 = (CLK->CLKDIV4 & ~(CLK_CLKDIV4_ADCDIV_Msk)) | u32ClkDiv; + CLK->APBCLK2 = (CLK->APBCLK2 & ~(CLK_APBCLK2_ADCCKEN_Msk)) | CLK_APBCLK2_ADCCKEN_Msk; + } + else + { + if (MODULE_CLKDIV_Msk(u32ModuleIdx) != MODULE_NoMsk) + { + /* Get clock divider control register address */ + u32div = (uint32_t)&CLK->CLKDIV0 + ((MODULE_CLKDIV(u32ModuleIdx)) * 4U); + /* Apply new divider */ + M32(u32div) = (M32(u32div) & (~(MODULE_CLKDIV_Msk(u32ModuleIdx) << MODULE_CLKDIV_Pos(u32ModuleIdx)))) | u32ClkDiv; + } + + if (MODULE_CLKSEL_Msk(u32ModuleIdx) != MODULE_NoMsk) + { + /* Get clock select control register address */ + u32sel = (uint32_t)&CLK->CLKSEL0 + ((MODULE_CLKSEL(u32ModuleIdx)) * 4U); + /* Set new clock selection setting */ + M32(u32sel) = (M32(u32sel) & (~(MODULE_CLKSEL_Msk(u32ModuleIdx) << MODULE_CLKSEL_Pos(u32ModuleIdx)))) | u32ClkSrc; + } + } +} + +/** + * @brief Set SysTick clock source + * @param[in] u32ClkSrc is module clock source. Including: + * - \ref CLK_CLKSEL0_RTPSTSEL_HXT + * - \ref CLK_CLKSEL0_RTPSTSEL_LXT + * - \ref CLK_CLKSEL0_RTPSTSEL_HXT_DIV2 + * - \ref CLK_CLKSEL0_RTPSTSEL_SYSCLK1_DIV2 + * - \ref CLK_CLKSEL0_RTPSTSEL_HIRC + * @return None + * @details This function set SysTick clock source. \n + * The register write-protection function should be disabled before using this function. + */ +void CLK_SetSysTickClockSrc(uint32_t u32ClkSrc) +{ + CLK->CLKSEL0 = (CLK->CLKSEL0 & ~CLK_CLKSEL0_RTPSTSEL_Msk) | u32ClkSrc; +} + +/** + * @brief Enable clock source + * @param[in] u32ClkMask is clock source mask. Including : + * - \ref CLK_PWRCTL_HXTEN_Msk + * - \ref CLK_PWRCTL_LXTEN_Msk + * - \ref CLK_PWRCTL_HIRCEN_Msk + * - \ref CLK_PWRCTL_LIRCEN_Msk + * @return None + * @details This function enable clock source. \n + * The register write-protection function should be disabled before using this function. + */ +void CLK_EnableXtalRC(uint32_t u32ClkMask) +{ + CLK->PWRCTL |= u32ClkMask; +} + +/** + * @brief Disable clock source + * @param[in] u32ClkMask is clock source mask. Including : + * - \ref CLK_PWRCTL_HXTEN_Msk + * - \ref CLK_PWRCTL_LXTEN_Msk + * - \ref CLK_PWRCTL_HIRCEN_Msk + * - \ref CLK_PWRCTL_LIRCEN_Msk + * @return None + * @details This function disable clock source. \n + * The register write-protection function should be disabled before using this function. + */ +void CLK_DisableXtalRC(uint32_t u32ClkMask) +{ + CLK->PWRCTL &= ~u32ClkMask; +} + +/** + * @brief Enable module clock + * @param[in] u32ModuleIdx is module index. Including : + * - \ref PDMA0_MODULE + * - \ref PDMA1_MODULE + * - \ref PDMA2_MODULE + * - \ref PDMA3_MODULE + * - \ref WH0_MODULE + * - \ref WH1_MODULE + * - \ref HWS_MODULE + * - \ref EBI_MODULE + * - \ref SRAM0_MODULE + * - \ref SRAM1_MODULE + * - \ref ROM_MODULE + * - \ref TRA_MODULE + * - \ref DBG_MODULE + * - \ref CLKO_MODULE + * - \ref GTMR_MODULE + * - \ref GPA_MODULE + * - \ref GPB_MODULE + * - \ref GPC_MODULE + * - \ref GPD_MODULE + * - \ref GPE_MODULE + * - \ref GPF_MODULE + * - \ref GPG_MODULE + * - \ref GPH_MODULE + * - \ref GPI_MODULE + * - \ref GPJ_MODULE + * - \ref GPK_MODULE + * - \ref GPL_MODULE + * - \ref GPM_MODULE + * - \ref GPN_MODULE + * - \ref CA35_MODULE + * - \ref RTP_MODULE + * - \ref TAHB_MODULE + * - \ref LVRDB_MODULE + * - \ref DDR0_MODULE + * - \ref DDR6_MODULE + * - \ref CANFD0_MODULE + * - \ref CANFD1_MODULE + * - \ref CANFD2_MODULE + * - \ref CANFD3_MODULE + * - \ref SDH0_MODULE + * - \ref SDH1_MODULE + * - \ref NAND_MODULE + * - \ref USBD_MODULE + * - \ref USBH_MODULE + * - \ref HUSBH0_MODULE + * - \ref HUSBH1_MODULE + * - \ref GFX_MODULE + * - \ref VDEC_MODULE + * - \ref DCU_MODULE + * - \ref GMAC0_MODULE + * - \ref GMAC1_MODULE + * - \ref CCAP0_MODULE + * - \ref CCAP1_MODULE + * - \ref TMR0_MODULE + * - \ref TMR1_MODULE + * - \ref TMR2_MODULE + * - \ref TMR3_MODULE + * - \ref TMR4_MODULE + * - \ref TMR5_MODULE + * - \ref TMR6_MODULE + * - \ref TMR7_MODULE + * - \ref TMR8_MODULE + * - \ref TMR9_MODULE + * - \ref TMR10_MODULE + * - \ref TMR11_MODULE + * - \ref UART0_MODULE + * - \ref UART1_MODULE + * - \ref UART2_MODULE + * - \ref UART3_MODULE + * - \ref UART4_MODULE + * - \ref UART5_MODULE + * - \ref UART6_MODULE + * - \ref UART7_MODULE + * - \ref UART8_MODULE + * - \ref UART9_MODULE + * - \ref UART10_MODULE + * - \ref UART11_MODULE + * - \ref UART12_MODULE + * - \ref UART13_MODULE + * - \ref UART14_MODULE + * - \ref UART15_MODULE + * - \ref UART16_MODULE + * - \ref RTC_MODULE + * - \ref DDRP_MODULE + * - \ref KPI_MODULE + * - \ref I2C0_MODULE + * - \ref I2C1_MODULE + * - \ref I2C2_MODULE + * - \ref I2C3_MODULE + * - \ref I2C4_MODULE + * - \ref I2C5_MODULE + * - \ref QSPI0_MODULE + * - \ref QSPI1_MODULE + * - \ref SC0_MODULE + * - \ref SC1_MODULE + * - \ref WDT0_MODULE + * - \ref WDT1_MODULE + * - \ref WDT2_MODULE + * - \ref EPWM0_MODULE + * - \ref EPWM1_MODULE + * - \ref EPWM2_MODULE + * - \ref I2S0_MODULE + * - \ref I2S1_MODULE + * - \ref SSMCC_MODULE + * - \ref SSPCC_MODULE + * - \ref SPI0_MODULE + * - \ref SPI1_MODULE + * - \ref SPI2_MODULE + * - \ref SPI3_MODULE + * - \ref ECAP0_MODULE + * - \ref ECAP1_MODULE + * - \ref ECAP2_MODULE + * - \ref QEI0_MODULE + * - \ref QEI1_MODULE + * - \ref QEI2_MODULE + * - \ref ADC_MODULE + * - \ref EADC_MODULE + * @return None + * @details This function is used to enable module clock. + */ +void CLK_EnableModuleClock(uint32_t u32ModuleIdx) +{ + vu32 u32tmpVal = 0UL, u32tmpAddr = 0UL; + + u32tmpVal = (1UL << MODULE_IP_EN_Pos(u32ModuleIdx)); + u32tmpAddr = (uint32_t)&CLK->SYSCLK0; + u32tmpAddr += ((MODULE_APBCLK(u32ModuleIdx) * 4UL)); + + *(vu32 *)u32tmpAddr |= u32tmpVal; +} + +/** + * @brief Disable module clock + * @param[in] u32ModuleIdx is module index. Including : + * - \ref PDMA0_MODULE + * - \ref PDMA1_MODULE + * - \ref PDMA2_MODULE + * - \ref PDMA3_MODULE + * - \ref WH0_MODULE + * - \ref WH1_MODULE + * - \ref HWS_MODULE + * - \ref EBI_MODULE + * - \ref SRAM0_MODULE + * - \ref SRAM1_MODULE + * - \ref ROM_MODULE + * - \ref TRA_MODULE + * - \ref DBG_MODULE + * - \ref CLKO_MODULE + * - \ref GTMR_MODULE + * - \ref GPA_MODULE + * - \ref GPB_MODULE + * - \ref GPC_MODULE + * - \ref GPD_MODULE + * - \ref GPE_MODULE + * - \ref GPF_MODULE + * - \ref GPG_MODULE + * - \ref GPH_MODULE + * - \ref GPI_MODULE + * - \ref GPJ_MODULE + * - \ref GPK_MODULE + * - \ref GPL_MODULE + * - \ref GPM_MODULE + * - \ref GPN_MODULE + * - \ref CA35_MODULE + * - \ref RTP_MODULE + * - \ref TAHB_MODULE + * - \ref LVRDB_MODULE + * - \ref DDR0_MODULE + * - \ref DDR6_MODULE + * - \ref CANFD0_MODULE + * - \ref CANFD1_MODULE + * - \ref CANFD2_MODULE + * - \ref CANFD3_MODULE + * - \ref SDH0_MODULE + * - \ref SDH1_MODULE + * - \ref NAND_MODULE + * - \ref USBD_MODULE + * - \ref USBH_MODULE + * - \ref HUSBH0_MODULE + * - \ref HUSBH1_MODULE + * - \ref GFX_MODULE + * - \ref VDEC_MODULE + * - \ref DCU_MODULE + * - \ref GMAC0_MODULE + * - \ref GMAC1_MODULE + * - \ref CCAP0_MODULE + * - \ref CCAP1_MODULE + * - \ref TMR0_MODULE + * - \ref TMR1_MODULE + * - \ref TMR2_MODULE + * - \ref TMR3_MODULE + * - \ref TMR4_MODULE + * - \ref TMR5_MODULE + * - \ref TMR6_MODULE + * - \ref TMR7_MODULE + * - \ref TMR8_MODULE + * - \ref TMR9_MODULE + * - \ref TMR10_MODULE + * - \ref TMR11_MODULE + * - \ref UART0_MODULE + * - \ref UART1_MODULE + * - \ref UART2_MODULE + * - \ref UART3_MODULE + * - \ref UART4_MODULE + * - \ref UART5_MODULE + * - \ref UART6_MODULE + * - \ref UART7_MODULE + * - \ref UART8_MODULE + * - \ref UART9_MODULE + * - \ref UART10_MODULE + * - \ref UART11_MODULE + * - \ref UART12_MODULE + * - \ref UART13_MODULE + * - \ref UART14_MODULE + * - \ref UART15_MODULE + * - \ref UART16_MODULE + * - \ref RTC_MODULE + * - \ref DDRP_MODULE + * - \ref KPI_MODULE + * - \ref I2C0_MODULE + * - \ref I2C1_MODULE + * - \ref I2C2_MODULE + * - \ref I2C3_MODULE + * - \ref I2C4_MODULE + * - \ref I2C5_MODULE + * - \ref QSPI0_MODULE + * - \ref QSPI1_MODULE + * - \ref SC0_MODULE + * - \ref SC1_MODULE + * - \ref WDT0_MODULE + * - \ref WDT1_MODULE + * - \ref WDT2_MODULE + * - \ref EPWM0_MODULE + * - \ref EPWM1_MODULE + * - \ref EPWM2_MODULE + * - \ref I2S0_MODULE + * - \ref I2S1_MODULE + * - \ref SSMCC_MODULE + * - \ref SSPCC_MODULE + * - \ref SPI0_MODULE + * - \ref SPI1_MODULE + * - \ref SPI2_MODULE + * - \ref SPI3_MODULE + * - \ref ECAP0_MODULE + * - \ref ECAP1_MODULE + * - \ref ECAP2_MODULE + * - \ref QEI0_MODULE + * - \ref QEI1_MODULE + * - \ref QEI2_MODULE + * - \ref ADC_MODULE + * - \ref EADC_MODULE + * @return None + * @details This function is used to disable module clock. + */ +void CLK_DisableModuleClock(uint32_t u32ModuleIdx) +{ + vu32 u32tmpVal = 0UL, u32tmpAddr = 0UL; + + u32tmpVal = ~(1UL << MODULE_IP_EN_Pos(u32ModuleIdx)); + u32tmpAddr = (uint32_t)&CLK->SYSCLK0; + u32tmpAddr += ((MODULE_APBCLK(u32ModuleIdx) * 4UL)); + + *((vu32 *)u32tmpAddr) &= u32tmpVal; +} + +/** + * @brief Get VSI PLL Operation Mode + * @param[in] u32PllIdx is PLL clock index. Including : + * - \ref DDRPLL + * - \ref APLL + * - \ref EPLL + * - \ref VPLL + * @return VSI PLL Operation Mode + * @details This function get VSI PLL Operation Mode. + */ +uint32_t CLK_GetPLLOpMode(uint32_t u32PllIdx) +{ + return (CLK->PLL[u32PllIdx].CTL0 & CLK_PLLnCTL0_MODE_Msk) >> CLK_PLLnCTL0_MODE_Pos; +} + +/** + * @brief This function check selected clock source status + * @param[in] u32ClkMask is selected clock source. Including : + * - \ref CLK_STATUS_HXTSTB_Msk + * - \ref CLK_STATUS_LXTSTB_Msk + * - \ref CLK_STATUS_HIRCSTB_Msk + * - \ref CLK_STATUS_LIRCSTB_Msk + * - \ref CLK_STATUS_CAPLLSTB_Msk + * - \ref CLK_STATUS_DDRPLLSTB_Msk + * - \ref CLK_STATUS_EPLLSTB_Msk + * - \ref CLK_STATUS_APLLSTB_Msk + * - \ref CLK_STATUS_VPLLSTB_Msk + * @retval 0 clock is not stable + * @retval 1 clock is stable + * @details To wait for clock ready by specified clock source stable flag or timeout (~300ms) + */ +uint32_t CLK_WaitClockReady(uint32_t u32ClkMask) +{ + int32_t i32TimeOutCnt = 2160000; + uint32_t u32Ret = 1U; + + while ((CLK->STATUS & u32ClkMask) != u32ClkMask) + { + if (i32TimeOutCnt-- <= 0) + { + u32Ret = 0U; + break; + } + } + + return u32Ret; +} + +#if defined(USE_MA35D1_SUBM) +/** + * @brief Enable System Tick counter + * @param[in] u32ClkSrc is System Tick clock source. Including: + * - \ref CLK_CLKSEL0_RTPSTSEL_HXT + * - \ref CLK_CLKSEL0_RTPSTSEL_LXT + * - \ref CLK_CLKSEL0_RTPSTSEL_HXT_DIV2 + * - \ref CLK_CLKSEL0_RTPSTSEL_SYSCLK1_DIV2 + * - \ref CLK_CLKSEL0_RTPSTSEL_HIRC + * @param[in] u32Count is System Tick reload value. It could be 0~0xFFFFFF. + * @return None + * @details This function set System Tick clock source, reload value, enable System Tick counter and interrupt. \n + * The register write-protection function should be disabled before using this function. + */ +void CLK_EnableSysTick(uint32_t u32ClkSrc, uint32_t u32Count) +{ + /* Set System Tick counter disabled */ + SysTick->CTRL = 0UL; + + /* Set System Tick clock source */ + if (u32ClkSrc == CLK_CLKSEL0_RTPSTSEL_HIRC) + { + SysTick->CTRL |= SysTick_CTRL_CLKSOURCE_Msk; + } + else + { + CLK->CLKSEL0 = (CLK->CLKSEL0 & ~CLK_CLKSEL0_RTPSTSEL_Msk) | u32ClkSrc; + } + + /* Set System Tick reload value */ + SysTick->LOAD = u32Count; + + /* Clear System Tick current value and counter flag */ + SysTick->VAL = 0UL; + + /* Set System Tick interrupt enabled and counter enabled */ + SysTick->CTRL |= SysTick_CTRL_TICKINT_Msk | SysTick_CTRL_ENABLE_Msk; +} + +/** + * @brief Disable System Tick counter + * @param None + * @return None + * @details This function disable System Tick counter. + */ +void CLK_DisableSysTick(void) +{ + /* Set System Tick counter disabled */ + SysTick->CTRL = 0UL; +} +#endif + +/** + * @brief Get CAPLL clock frequency + * @param None + * @return PLL frequency + * @details This function get PLL frequency. The frequency unit is Hz. + */ +uint32_t CLK_GetCAPLLClockFreq(void) +{ + uint32_t u32M, u32N, u32P; + uint32_t u32PllClk, u32RefClk; + uint32_t val; + + val = CLK->PLL0CTL0; + + u32N = (val & CLK_PLL0CTL0_FBDIV_Msk); + u32M = (val & CLK_PLL0CTL0_INDIV_Msk) >> (CLK_PLL0CTL0_INDIV_Pos); + u32P = (val & CLK_PLL0CTL0_OUTDIV_Msk) >> (CLK_PLL0CTL0_OUTDIV_Pos); + + if (val & CLK_PLL0CTL0_BP_Msk) + { + u32PllClk = __HXT; + } + else + { + /* u32RefClk is shifted to avoid overflow */ + u32RefClk = __HXT / 100; + + /* Actual PLL output clock frequency */ + u32PllClk = ((u32RefClk * u32N) / ((0x1 << u32P) * u32M)) * 100; + } + + return u32PllClk; +} + +/** + * @brief Get Advanced PLL clock frequency + * @param[in] u32PllIdx is Advanced PLL clock index. Including : + * - \ref DDRPLL + * - \ref APLL + * - \ref EPLL + * - \ref VPLL + * @return Advanced PLL frequency + * @details This function get Advanced PLL frequency. The frequency unit is Hz. + */ +static uint32_t CLK_GetVSIPLLClockFreq(uint32_t u32PllIdx) +{ + uint32_t u32M, u32N, u32P, u32X, u32Mode; + uint32_t u32CTLVal0, u32CTLVal1, u32PllClk = 0ul; + + /* Set PLL Operation mode. */ + u32CTLVal0 = CLK->PLL[u32PllIdx].CTL0; + u32CTLVal1 = CLK->PLL[u32PllIdx].CTL1; + + /* If is power down state, it will return 0 directly. */ + if (u32CTLVal1 & CLK_PLLnCTL1_PD_Msk) + return 0U; + + u32Mode = (u32CTLVal0 & CLK_PLLnCTL0_MODE_Msk) >> CLK_PLLnCTL0_MODE_Pos; + + u32N = (u32CTLVal0 & CLK_PLLnCTL0_FBDIV_Msk); + u32M = (u32CTLVal0 & CLK_PLLnCTL0_INDIV_Msk) >> CLK_PLLnCTL0_INDIV_Pos; + u32P = (u32CTLVal1 & CLK_PLLnCTL1_OUTDIV_Msk) >> CLK_PLLnCTL1_OUTDIV_Pos; + u32X = (u32CTLVal1 & CLK_PLLnCTL1_FRAC_Msk) >> CLK_PLLnCTL1_FRAC_Pos; + + if (u32Mode == 0) + { + /* Actual PLL output clock frequency */ + u32PllClk = (__HXT / (u32P * u32M)) * u32N; + } + else if (u32Mode == 1) + { + /* Actual PLL output clock frequency */ + u32X = (((u32X * 1000) + 500) >> 24); + u32PllClk = (__HXT / 1000) * ((u32N * 1000) + u32X) / (u32P * u32M); + } + else if (u32Mode == 2) + { + //uint32_t u32SR, u32FMOD, u32CTLVal2; + + //u32CTLVal2 = CLK->PLLCTL[u32PllIdx].REG2; + //u32SR = (u32CTLVal0 & (CLK_PLLnCTL0_SSRATE_Msk)) >> CLK_PLLnCTL0_SSRATE_Pos; + //u32FMOD = u32CTLVal2 & CLK_PLLnCTL2_SLOPE_Msk; + + /* Actual PLL output clock frequency */ + u32X = ((u32X * 1000) >> 24); + u32PllClk = (__HXT / 1000) * ((u32N * 1000) + u32X) / (u32P * u32M); + } + + return u32PllClk; +} + +/* VSI-PLL Specification limits */ +#define VSIPLL_FREF_MAX_FREQ 200000000U +#define VSIPLL_FREF_MIN_FREQ 1000000U + +#define VSIPLL_FREFDIVM_MAX_FREQ 40000000U +#define VSIPLL_FREFDIVM_MIN_FREQ0 1000000U +#define VSIPLL_FREFDIVM_MIN_FREQ1 10000000U + +#define VSIPLL_FCLK_MAX_FREQ 2400000000U +#define VSIPLL_FCLK_MIN_FREQ 600000000U + +#define VSIPLL_FCLKO_MAX_FREQ 2400000000U +#define VSIPLL_FCLKO_MIN_FREQ 85700000U + +#define VSIPLL_SPREAD_RANGE 194 +#define VSIPLL_MODULATION_FREQ 50000 + +struct S_PLL_FREQ_MAP +{ + uint64_t freq; + uint32_t mode; + uint32_t ctl0_reg; + uint32_t ctl1_reg; + uint32_t ctl2_reg; +} ; + +static const struct S_PLL_FREQ_MAP s_sVsiPllFreqTbl[] = +{ + { 1000000000, PLL_OPMODE_INTEGER, 0x307d, 0x10, 0 }, /* Mode0 */ + { 884736000, PLL_OPMODE_FRACTIONAL, 0x41024, 0xdd2f1b11, 0 }, /* Mode1 */ + { 533000000, PLL_OPMODE_SPREAD_SPECTRUM, 0x12b8102c, 0x6aaaab20, 0x12317 }, /* Mode2 */ + { } +}; + +static uint64_t CLK_CalPLLFreq_Mode0(uint64_t u64PllSrcClk, uint64_t u64PllFreq, uint32_t *u32Reg) +{ + uint32_t u32Tmp, u32Min, u32MinN, u32MinM, u32MinP; + + uint64_t u64PllClk; + uint64_t u64Con1, u64Con2, u64Con3; + + /* Find best solution */ + u32Min = (uint32_t) - 1; + u32MinM = 0UL; + u32MinN = 0UL; + u32MinP = 0UL; + + if ((u64PllFreq < VSIPLL_FCLKO_MIN_FREQ) || (u64PllFreq > VSIPLL_FCLKO_MAX_FREQ)) + { + u32Reg[0] = s_sVsiPllFreqTbl[0].ctl0_reg; + u32Reg[1] = s_sVsiPllFreqTbl[0].ctl1_reg; + u64PllClk = s_sVsiPllFreqTbl[0].freq; + } + else + { + uint32_t u32TmpM, u32TmpN, u32TmpP; + uint32_t u32RngMinN, u32RngMinM, u32RngMinP; + uint32_t u32RngMaxN, u32RngMaxM, u32RngMaxP; + + /* Find best solution */ + u32RngMinM = 1UL; + u32RngMaxM = 63UL; + + u32RngMinM = ((u64PllSrcClk / VSIPLL_FREFDIVM_MAX_FREQ) > 1) ? + (u64PllSrcClk / VSIPLL_FREFDIVM_MAX_FREQ) : 1; + u32RngMaxM = ((u64PllSrcClk / VSIPLL_FREFDIVM_MIN_FREQ0) < u32RngMaxM) ? + (u64PllSrcClk / VSIPLL_FREFDIVM_MIN_FREQ0) : u32RngMaxM; + + for (u32TmpM = u32RngMinM; u32TmpM < (u32RngMaxM + 1); u32TmpM++) + { + u64Con1 = u64PllSrcClk / u32TmpM; + + u32RngMinN = 16UL; + u32RngMaxN = 2047UL; + + u32RngMinN = ((VSIPLL_FCLK_MIN_FREQ / u64Con1) > u32RngMinN) ? + (VSIPLL_FCLK_MIN_FREQ / u64Con1) : u32RngMinN; + u32RngMaxN = ((VSIPLL_FCLK_MAX_FREQ / u64Con1) < u32RngMaxN) ? + (VSIPLL_FCLK_MAX_FREQ / u64Con1) : u32RngMaxN; + + for (u32TmpN = u32RngMinN; u32TmpN < (u32RngMaxN + 1); u32TmpN++) + { + u64Con2 = u64Con1 * u32TmpN; + + u32RngMinP = 1UL; + u32RngMaxP = 7UL; + + u32RngMinP = ((u64Con2 / VSIPLL_FCLKO_MAX_FREQ) > 1) ? (u64Con2 / + VSIPLL_FCLKO_MAX_FREQ) : 1; + u32RngMaxP = ((u64Con2 / VSIPLL_FCLKO_MIN_FREQ) < u32RngMaxP) ? + (u64Con2 / VSIPLL_FCLKO_MIN_FREQ) : u32RngMaxP; + + for (u32TmpP = u32RngMinP; u32TmpP < (u32RngMaxP + 1); u32TmpP++) + { + u64Con3 = u64Con2 / u32TmpP; + if (u64Con3 > u64PllFreq) + u32Tmp = u64Con3 - u64PllFreq; + else + u32Tmp = u64PllFreq - u64Con3; + + if (u32Tmp < u32Min) + { + u32Min = u32Tmp; + u32MinM = u32TmpM; + u32MinN = u32TmpN; + u32MinP = u32TmpP; + + /* Break when get good results */ + if (u32Min == 0UL) + { + u32Reg[0] = (u32MinM << 12) | (u32MinN); + u32Reg[1] = (u32MinP << 4); + + return ((u64PllSrcClk * u32MinN) / (u32MinP * u32MinM)); + } + } + } + } + + } + + /* Enable and apply new PLL setting. */ + u32Reg[0] = (u32MinM << 12) | (u32MinN); + u32Reg[1] = (u32MinP << 4); + + /* Actual PLL output clock frequency */ + u64PllClk = (u64PllSrcClk * u32MinN) / (u32MinP * u32MinM); + } + + return u64PllClk; +} + + +static uint64_t CLK_CalPLLFreq_Mode1(uint64_t u64PllSrcClk, uint64_t u64PllFreq, uint32_t *u32Reg) +{ + uint64_t u64X, u64N, u64M, u64P, u64tmp, u64tmpP, u64tmpM; + uint64_t u64PllClk, u64FCLKO; + uint32_t u32FRAC, i; + + // check condition 1 + if ((u64PllSrcClk > VSIPLL_FREF_MAX_FREQ) || (u64PllSrcClk < VSIPLL_FREF_MIN_FREQ)) + { + // Fref is incorrect, return fail + return 0; + } + + // check condition 4 + if (u64PllFreq < VSIPLL_FCLKO_MIN_FREQ) + { + // Adjust u64FCLKO + u64FCLKO = 0; + + for (i = 2; i < 100; i++) + { + u64tmp = (i * u64PllFreq); + if (u64tmp > VSIPLL_FCLKO_MIN_FREQ) + { + u64FCLKO = u64tmp; + break; + } + } + + if (u64FCLKO == 0) return 0; + } + else if (u64PllFreq >= VSIPLL_FCLKO_MAX_FREQ) + { + u32Reg[0] = 0x30FA; + u32Reg[1] = (0x2 << 4); + u64PllClk = 1000000000; + return u64PllClk; + } + else + u64FCLKO = u64PllFreq; + + // Find P + u64P = 0; + for (i = 1; i < 8; i++) + { + u64tmpP = i * u64FCLKO; + // it should be condition 3 + if ((u64tmpP <= VSIPLL_FCLKO_MAX_FREQ) && (u64tmpP >= 600000000)) + { + u64P = i; + break; + } + } + + // No reasonable P is found, return fail. + if (u64P == 0) return 0; + + // Find M + u64M = 0; // Initialize it, and use it to judge reasonable M is found or not + for (i = 1; i < 64; i++) + { + u64tmpM = u64PllSrcClk / i; + if ((u64tmpM <= 40000000) && (u64tmpM >= 10000000)) // condition 2 + { + u64M = i; + break; + } + } + + if (u64M == 0) + { + // No reasonable M is found + return 0; + } + + u64tmp = (u64FCLKO * u64P * u64M * 1000) / u64PllSrcClk; + u64N = u64tmp / 1000; + u64X = u64tmp % 1000; + u32FRAC = ((u64X << 24) + 500) / 1000; + + u32Reg[0] = (u64M << 12) | (u64N); + u32Reg[1] = (u64P << 4) | (u32FRAC << 8); + + /* Actual PLL output clock frequency */ + u64PllClk = (u64PllSrcClk * u64tmp) / u64P / u64M / 1000; + + return u64PllClk; +} + +static uint64_t CLK_CalPLLFreq_Mode2(uint64_t PllSrcClk, uint64_t u64PllFreq, uint32_t u32SR, uint32_t u32Fmod, uint32_t *u32Reg) +{ + uint64_t u64PllClk; + uint64_t u64X, u64N, u64M, u64P, u64tmp, u64tmpP, u64tmpM; + uint64_t u64FCLKO, u64SSRATE, u64SLOPE; + uint32_t u32FRAC, i; + + // check condition 1 + if ((PllSrcClk > 200000000) || (PllSrcClk < 1000000)) + { + // Fref is incorrect, return fail case + return 0; + } + + // check condition 4 + if (u64PllFreq < 85700000) + { + u64FCLKO = 0; + for (i = 2; i < 8; i++) + { + u64tmp = (i * u64PllFreq); + if (u64tmp > 85700000) + { + u64FCLKO = u64tmp; + } + } + + if (u64FCLKO == 0) return 0; + } + else if (u64PllFreq >= 2400000000) + { + u32Reg[0] = 0x30FA; + u32Reg[1] = (0x2 << 4); + u64PllClk = 1000000000; + return u64PllClk; + } + else + u64FCLKO = u64PllFreq; + + // Find P + u64P = 0; + for (i = 1; i < 8; i++) + { + u64tmpP = i * u64FCLKO; + if ((u64tmpP <= 2400000000) && (u64tmpP >= 600000000)) + { + u64P = i; + break; + } + } + + // No reasonable P is found, return fail. + if (u64P == 0) return 0; + + // Find M + u64M = 0; // Initialize it, and use it to judge reasonable M is found or not + for (i = 1; i < 64; i++) + { + u64tmpM = PllSrcClk / i; + if ((u64tmpM <= 40000000) && (u64tmpM >= 10000000)) // condition 2 + { + u64M = i; + break; + } + } + + if (u64M == 0) // No reasonable M is found + { + return 0; + } + + u64tmp = (u64FCLKO * u64P * u64M * 1000) / PllSrcClk; + u64N = u64tmp / 1000; + u64X = u64tmp % 1000; + u32FRAC = ((u64X << 24) + 500) / 1000; + + u64SSRATE = ((PllSrcClk >> 1) / (u32Fmod * 2)) - 1; + u64SLOPE = ((u64tmp * u32SR / u64SSRATE) << 24) / 100 / 1000; + + u32Reg[0] = (u64SSRATE << 20) | (u64M << 12) | (u64N); + u32Reg[1] = (u64P << 4) | (u32FRAC << 8); + u32Reg[2] = u64SLOPE; + + /* Actual PLL output clock frequency */ + u64PllClk = (PllSrcClk * u64tmp) / u64P / u64M / 1000; + + return u64PllClk; +} + +/** + * @brief Get Advanced PLL clock frequency + * @param[in] u32PllIdx is Advanced PLL clock index. Including : + * - \ref CAPLL + * - \ref + * - \ref DDRPLL + * - \ref APLL + * - \ref EPLL + * - \ref VPLL + * @return Advanced PLL frequency + * @details This function get Advanced PLL frequency. The frequency unit is Hz. + */ +uint32_t CLK_GetPLLClockFreq(uint32_t u32PllIdx) +{ + uint32_t u32Pllout = 0; + + switch (u32PllIdx) + { + /* SMIC */ + case CAPLL: + u32Pllout = CLK_GetCAPLLClockFreq(); + break; + + case SYSPLL: + u32Pllout = SYSPLLFREQCLK; + break; + + /* VSI */ + case DDRPLL: + case EPLL: + case APLL: + case VPLL: + u32Pllout = CLK_GetVSIPLLClockFreq(u32PllIdx); + break; + + default: + break; + } + + return u32Pllout; +} + +/* CPU-PLL: 1000MHz 800MHz 700MHz */ +static const struct S_PLL_FREQ_MAP s_au32CAPLLMap[] = +{ + { 1000000000u, PLL_OPMODE_INTEGER, 0x000006FA, 0, 0 }, /* 1000 MHz */ + { 800000000u, PLL_OPMODE_INTEGER, 0x00000364, 0, 0 }, /* 800 MHz */ + { 700000000u, PLL_OPMODE_INTEGER, 0x000006AF, 0, 0 }, /* 700 MHz */ +}; +#define ARRARSIZE_CAPLLPLLMAP (sizeof(s_au32CAPLLMap)/sizeof(struct S_PLL_FREQ_MAP)) + +static uint64_t CLK_SetCAPLLClockFreq(uint32_t u32PllIdx, uint32_t u32OpMode, uint64_t PllSrcClk, uint64_t u64PllFreq) +{ + // TODO + uint32_t i; + + for (i = 0; i < ARRARSIZE_CAPLLPLLMAP; i++) + { + if ((u32OpMode == PLL_OPMODE_INTEGER) && (u64PllFreq == s_au32CAPLLMap[i].freq)) + { + CLK->PLL0CTL0 = s_au32CAPLLMap[i].ctl0_reg; + return s_au32CAPLLMap[i].freq; + } + } + + return 0; +} + +static uint64_t CLK_SetVSIPLLFreq(uint32_t u32PllIdx, uint32_t u32OpMode, uint64_t PllSrcClk, uint64_t u64PllFreq) +{ + uint32_t u32CTLVal0, u32CTLVal1, u32CTLVal2; + uint32_t u32Reg[3] = {0}; + uint64_t u64PllClk = 0; + + /* Set PLL Operation mode. */ + u32CTLVal0 = CLK->PLL[u32PllIdx].CTL0; + u32CTLVal1 = CLK->PLL[u32PllIdx].CTL1; + u32CTLVal2 = CLK->PLL[u32PllIdx].CTL2; + + /* Set PLL Operation mode. */ + u32CTLVal0 = (u32CTLVal0 & ~CLK_PLLnCTL0_MODE_Msk) | (u32OpMode << CLK_PLLnCTL0_MODE_Pos); + + if (u32OpMode == PLL_OPMODE_INTEGER) + { + u64PllClk = CLK_CalPLLFreq_Mode0(PllSrcClk, u64PllFreq, &u32Reg[0]); + u32CTLVal0 = (u32CTLVal0 & ~(CLK_PLLnCTL0_INDIV_Msk | CLK_PLLnCTL0_FBDIV_Msk)) | u32Reg[0]; + u32CTLVal1 = (u32CTLVal1 & ~CLK_PLLnCTL1_OUTDIV_Msk) | u32Reg[1]; + } + else if (u32OpMode == PLL_OPMODE_FRACTIONAL) + { + u64PllClk = CLK_CalPLLFreq_Mode1(PllSrcClk, u64PllFreq, &u32Reg[0]); + u32CTLVal0 = (u32CTLVal0 & ~(CLK_PLLnCTL0_INDIV_Msk | CLK_PLLnCTL0_FBDIV_Msk)) | u32Reg[0]; + u32CTLVal1 = (u32CTLVal1 & ~(CLK_PLLnCTL1_OUTDIV_Msk | CLK_PLLnCTL1_FRAC_Msk)) | u32Reg[1]; + } + else if (u32OpMode == PLL_OPMODE_SPREAD_SPECTRUM) + { + u64PllClk = CLK_CalPLLFreq_Mode2(PllSrcClk, u64PllFreq, 50000, 194, &u32Reg[0]); /* 50 khz, 1.94% */ + u32CTLVal0 = (u32CTLVal0 & ~(CLK_PLLnCTL0_SSRATE_Msk | CLK_PLLnCTL0_INDIV_Msk | CLK_PLLnCTL0_FBDIV_Msk)) | u32Reg[0]; + u32CTLVal1 = (u32CTLVal1 & ~(CLK_PLLnCTL1_OUTDIV_Msk | CLK_PLLnCTL1_FRAC_Msk)) | u32Reg[1]; + u32CTLVal2 = u32Reg[2]; + } + else + { + return 0; + } + + CLK->PLL[u32PllIdx].CTL0 = u32CTLVal0; + CLK->PLL[u32PllIdx].CTL1 = u32CTLVal1 & (~CLK_PLLnCTL1_PD_Msk); + CLK->PLL[u32PllIdx].CTL2 = u32CTLVal2; + + return u64PllClk; +} + +uint64_t CLK_SetPLLFreq(uint32_t u32PllIdx, uint32_t u32OpMode, uint64_t PllSrcClk, uint64_t u64PllFreq) +{ + uint64_t u64Pllout = 0; + + switch (u32PllIdx) + { + /* SMIC */ + case CAPLL: + u64Pllout = CLK_SetCAPLLClockFreq(u32PllIdx, u32OpMode, PllSrcClk, u64PllFreq); + break; + + case SYSPLL: + u64Pllout = SYSPLLFREQCLK; + break; + + /* VSI */ + case DDRPLL: + case EPLL: + case APLL: + case VPLL: + u64Pllout = CLK_SetVSIPLLFreq(u32PllIdx, u32OpMode, PllSrcClk, u64PllFreq); + break; + + default: + break; + } + + return u64Pllout; +} + +/** + * @brief Get selected module clock source + * @param[in] u32ModuleIdx is module index. + * - \ref PDMA0_MODULE + * - \ref PDMA1_MODULE + * - \ref PDMA2_MODULE + * - \ref PDMA3_MODULE + * - \ref WH0_MODULE + * - \ref WH1_MODULE + * - \ref HWS_MODULE + * - \ref EBI_MODULE + * - \ref SRAM0_MODULE + * - \ref SRAM1_MODULE + * - \ref ROM_MODULE + * - \ref TRA_MODULE + * - \ref DBG_MODULE + * - \ref CLKO_MODULE + * - \ref GTMR_MODULE + * - \ref GPA_MODULE + * - \ref GPB_MODULE + * - \ref GPC_MODULE + * - \ref GPD_MODULE + * - \ref GPE_MODULE + * - \ref GPF_MODULE + * - \ref GPG_MODULE + * - \ref GPH_MODULE + * - \ref GPI_MODULE + * - \ref GPJ_MODULE + * - \ref GPK_MODULE + * - \ref GPL_MODULE + * - \ref GPM_MODULE + * - \ref GPN_MODULE + * - \ref CA35_MODULE + * - \ref RTP_MODULE + * - \ref TAHB_MODULE + * - \ref LVRDB_MODULE + * - \ref DDR0_MODULE + * - \ref DDR6_MODULE + * - \ref CANFD0_MODULE + * - \ref CANFD1_MODULE + * - \ref CANFD2_MODULE + * - \ref CANFD3_MODULE + * - \ref SDH0_MODULE + * - \ref SDH1_MODULE + * - \ref NAND_MODULE + * - \ref USBD_MODULE + * - \ref USBH_MODULE + * - \ref HUSBH0_MODULE + * - \ref HUSBH1_MODULE + * - \ref GFX_MODULE + * - \ref VDEC_MODULE + * - \ref DCU_MODULE + * - \ref GMAC0_MODULE + * - \ref GMAC1_MODULE + * - \ref CCAP0_MODULE + * - \ref CCAP1_MODULE + * - \ref TMR0_MODULE + * - \ref TMR1_MODULE + * - \ref TMR2_MODULE + * - \ref TMR3_MODULE + * - \ref TMR4_MODULE + * - \ref TMR5_MODULE + * - \ref TMR6_MODULE + * - \ref TMR7_MODULE + * - \ref TMR8_MODULE + * - \ref TMR9_MODULE + * - \ref TMR10_MODULE + * - \ref TMR11_MODULE + * - \ref UART0_MODULE + * - \ref UART1_MODULE + * - \ref UART2_MODULE + * - \ref UART3_MODULE + * - \ref UART4_MODULE + * - \ref UART5_MODULE + * - \ref UART6_MODULE + * - \ref UART7_MODULE + * - \ref UART8_MODULE + * - \ref UART9_MODULE + * - \ref UART10_MODULE + * - \ref UART11_MODULE + * - \ref UART12_MODULE + * - \ref UART13_MODULE + * - \ref UART14_MODULE + * - \ref UART15_MODULE + * - \ref UART16_MODULE + * - \ref RTC_MODULE + * - \ref DDRP_MODULE + * - \ref KPI_MODULE + * - \ref I2C0_MODULE + * - \ref I2C1_MODULE + * - \ref I2C2_MODULE + * - \ref I2C3_MODULE + * - \ref I2C4_MODULE + * - \ref I2C5_MODULE + * - \ref QSPI0_MODULE + * - \ref QSPI1_MODULE + * - \ref SC0_MODULE + * - \ref SC1_MODULE + * - \ref WDT0_MODULE + * - \ref WDT1_MODULE + * - \ref WDT2_MODULE + * - \ref EPWM0_MODULE + * - \ref EPWM1_MODULE + * - \ref EPWM2_MODULE + * - \ref I2S0_MODULE + * - \ref I2S1_MODULE + * - \ref SSMCC_MODULE + * - \ref SSPCC_MODULE + * - \ref SPI0_MODULE + * - \ref SPI1_MODULE + * - \ref SPI2_MODULE + * - \ref SPI3_MODULE + * - \ref ECAP0_MODULE + * - \ref ECAP1_MODULE + * - \ref ECAP2_MODULE + * - \ref QEI0_MODULE + * - \ref QEI1_MODULE + * - \ref QEI2_MODULE + * - \ref ADC_MODULE + * - \ref EADC_MODULE + * @return Selected module clock source setting + * @details This function get selected module clock source. + */ +uint32_t CLK_GetModuleClockSource(uint32_t u32ModuleIdx) +{ + uint32_t u32sel = 0; + uint32_t u32SelTbl[5] = {0x0, 0x4, 0x8, 0xC, 0x10}; + + /* Get clock source selection setting */ + if (MODULE_CLKSEL_Msk(u32ModuleIdx) != MODULE_NoMsk) + { + /* Get clock select control register address */ + u32sel = (uint32_t)&CLK->CLKSEL0 + (u32SelTbl[MODULE_CLKSEL(u32ModuleIdx)]); + /* Get clock source selection setting */ + return ((M32(u32sel) & (MODULE_CLKSEL_Msk(u32ModuleIdx) << MODULE_CLKSEL_Pos(u32ModuleIdx))) >> MODULE_CLKSEL_Pos(u32ModuleIdx)); + } + else + return 0; +} + +/** + * @brief Get selected module clock divider number + * @param[in] u32ModuleIdx is module index. + * - \ref PDMA0_MODULE + * - \ref PDMA1_MODULE + * - \ref PDMA2_MODULE + * - \ref PDMA3_MODULE + * - \ref WH0_MODULE + * - \ref WH1_MODULE + * - \ref HWS_MODULE + * - \ref EBI_MODULE + * - \ref SRAM0_MODULE + * - \ref SRAM1_MODULE + * - \ref ROM_MODULE + * - \ref TRA_MODULE + * - \ref DBG_MODULE + * - \ref CLKO_MODULE + * - \ref GTMR_MODULE + * - \ref GPA_MODULE + * - \ref GPB_MODULE + * - \ref GPC_MODULE + * - \ref GPD_MODULE + * - \ref GPE_MODULE + * - \ref GPF_MODULE + * - \ref GPG_MODULE + * - \ref GPH_MODULE + * - \ref GPI_MODULE + * - \ref GPJ_MODULE + * - \ref GPK_MODULE + * - \ref GPL_MODULE + * - \ref GPM_MODULE + * - \ref GPN_MODULE + * - \ref CA35_MODULE + * - \ref RTP_MODULE + * - \ref TAHB_MODULE + * - \ref LVRDB_MODULE + * - \ref DDR0_MODULE + * - \ref DDR6_MODULE + * - \ref CANFD0_MODULE + * - \ref CANFD1_MODULE + * - \ref CANFD2_MODULE + * - \ref CANFD3_MODULE + * - \ref SDH0_MODULE + * - \ref SDH1_MODULE + * - \ref NAND_MODULE + * - \ref USBD_MODULE + * - \ref USBH_MODULE + * - \ref HUSBH0_MODULE + * - \ref HUSBH1_MODULE + * - \ref GFX_MODULE + * - \ref VDEC_MODULE + * - \ref DCU_MODULE + * - \ref GMAC0_MODULE + * - \ref GMAC1_MODULE + * - \ref CCAP0_MODULE + * - \ref CCAP1_MODULE + * - \ref TMR0_MODULE + * - \ref TMR1_MODULE + * - \ref TMR2_MODULE + * - \ref TMR3_MODULE + * - \ref TMR4_MODULE + * - \ref TMR5_MODULE + * - \ref TMR6_MODULE + * - \ref TMR7_MODULE + * - \ref TMR8_MODULE + * - \ref TMR9_MODULE + * - \ref TMR10_MODULE + * - \ref TMR11_MODULE + * - \ref UART0_MODULE + * - \ref UART1_MODULE + * - \ref UART2_MODULE + * - \ref UART3_MODULE + * - \ref UART4_MODULE + * - \ref UART5_MODULE + * - \ref UART6_MODULE + * - \ref UART7_MODULE + * - \ref UART8_MODULE + * - \ref UART9_MODULE + * - \ref UART10_MODULE + * - \ref UART11_MODULE + * - \ref UART12_MODULE + * - \ref UART13_MODULE + * - \ref UART14_MODULE + * - \ref UART15_MODULE + * - \ref UART16_MODULE + * - \ref RTC_MODULE + * - \ref DDRP_MODULE + * - \ref KPI_MODULE + * - \ref I2C0_MODULE + * - \ref I2C1_MODULE + * - \ref I2C2_MODULE + * - \ref I2C3_MODULE + * - \ref I2C4_MODULE + * - \ref I2C5_MODULE + * - \ref QSPI0_MODULE + * - \ref QSPI1_MODULE + * - \ref SC0_MODULE + * - \ref SC1_MODULE + * - \ref WDT0_MODULE + * - \ref WDT1_MODULE + * - \ref WDT2_MODULE + * - \ref EPWM0_MODULE + * - \ref EPWM1_MODULE + * - \ref EPWM2_MODULE + * - \ref I2S0_MODULE + * - \ref I2S1_MODULE + * - \ref SSMCC_MODULE + * - \ref SSPCC_MODULE + * - \ref SPI0_MODULE + * - \ref SPI1_MODULE + * - \ref SPI2_MODULE + * - \ref SPI3_MODULE + * - \ref ECAP0_MODULE + * - \ref ECAP1_MODULE + * - \ref ECAP2_MODULE + * - \ref QEI0_MODULE + * - \ref QEI1_MODULE + * - \ref QEI2_MODULE + * - \ref ADC_MODULE + * - \ref EADC_MODULE + * @return Selected module clock divider number setting + * @details This function get selected module clock divider number. + */ +uint32_t CLK_GetModuleClockDivider(uint32_t u32ModuleIdx) +{ + vu32 u32div = 0; + uint32_t u32DivTbl[5] = {0x0, 0x4, 0xc, 0xc, 0x10}; + + if (MODULE_CLKDIV_Msk(u32ModuleIdx) != MODULE_NoMsk) + { + if (u32ModuleIdx == KPI_MODULE) + { + u32div = (CLK->CLKDIV4 & CLK_CLKDIV4_KPIDIV_Msk) >> CLK_CLKDIV4_KPIDIV_Pos; + return u32div; + } + else if (u32ModuleIdx == ADC_MODULE) + { + u32div = (CLK->CLKDIV4 & CLK_CLKDIV4_ADCDIV_Msk) >> CLK_CLKDIV4_ADCDIV_Pos; + return u32div; + } + else + { + /* Get clock divider control register address */ + u32div = (vu32)&CLK->CLKDIV0 + (u32DivTbl[MODULE_CLKDIV(u32ModuleIdx)]); + /* Get clock divider number setting */ + return ((M32(u32div) & (MODULE_CLKDIV_Msk(u32ModuleIdx) << MODULE_CLKDIV_Pos(u32ModuleIdx))) >> MODULE_CLKDIV_Pos(u32ModuleIdx)); + } + } + else + return 0; +} + + +/*@}*/ /* end of group CLK_EXPORTED_FUNCTIONS */ + +/*@}*/ /* end of group CLK_Driver */ + +/*@}*/ /* end of group Standard_Driver */ + diff --git a/bsp/nuvoton/libraries/ma35/StdDriver/src/nu_disp.c b/bsp/nuvoton/libraries/ma35/StdDriver/src/nu_disp.c new file mode 100644 index 0000000000..f92ce1537a --- /dev/null +++ b/bsp/nuvoton/libraries/ma35/StdDriver/src/nu_disp.c @@ -0,0 +1,560 @@ +/**************************************************************************//** + * @file nu_disp.c + * @brief DISP driver source file + * + * SPDX-License-Identifier: Apache-2.0 + * @copyright (C) 2020 Nuvoton Technology Corp. All rights reserved. + *****************************************************************************/ + +#include "NuMicro.h" + +/** @addtogroup Standard_Driver Standard Driver + @{ +*/ + +/** @addtogroup DISP_Driver DISP Driver + @{ +*/ + +/** @addtogroup DISP_EXPORTED_FUNCTIONS DISP Exported Functions + @{ +*/ + +static const DISP_LCD_INFO *g_psDispLcdInfo_Curr = NULL; + +const static DISP_LCD_INFO g_sLcdInfo_arr [eDispLcd_Cnt] = +{ + { + /* eDispLcd_1024x600 */ + .u32ResolutionWidth = 1024, + .u32ResolutionHeight = 600, + .sLcdTiming = + { + .u32PCF = 51000000, + .u32HA = 1024, + .u32HSL = 1, + .u32HFP = 160, + .u32HBP = 160, + .u32VA = 600, + .u32VSL = 1, + .u32VFP = 23, + .u32VBP = 12, + .eHSPP = ePolarity_Positive, + .eVSPP = ePolarity_Positive + }, + .sPanelConf = + { + .eDpiFmt = eDPIFmt_D24, + .eDEP = ePolarity_Positive, + .eDP = ePolarity_Positive, + .eCP = ePolarity_Positive + }, + }, + { + /* eDispLcd_800x480 */ + .u32ResolutionWidth = 800, + .u32ResolutionHeight = 480, + .sLcdTiming = + { + .u32PCF = 45000000, + .u32HA = 800, + .u32HSL = 1, + .u32HFP = 210, + .u32HBP = 46, + .u32VA = 480, + .u32VSL = 1, + .u32VFP = 22, + .u32VBP = 23, + .eHSPP = ePolarity_Positive, + .eVSPP = ePolarity_Positive + }, + .sPanelConf = + { + .eDpiFmt = eDPIFmt_D24, + .eDEP = ePolarity_Positive, + .eDP = ePolarity_Positive, + .eCP = ePolarity_Positive + }, + }, + { + /* eDispLcd_1920x1080 */ + .u32ResolutionWidth = 1920, + .u32ResolutionHeight = 1080, + .sLcdTiming = + { + .u32PCF = 125000000, + .u32HA = 1920, + .u32HSL = 32, + .u32HFP = 120, + .u32HBP = 128, + .u32VA = 1080, + .u32VSL = 14, + .u32VFP = 21, + .u32VBP = 10, + .eHSPP = ePolarity_Positive, + .eVSPP = ePolarity_Positive + }, + .sPanelConf = + { + .eDpiFmt = eDPIFmt_D24, + .eDEP = ePolarity_Positive, + .eDP = ePolarity_Positive, + .eCP = ePolarity_Positive + }, + }, +}; + +static uint32_t DISP_GetBitPerPixel(E_FB_FMT eFbFmt) +{ + uint32_t u32bpp; + + switch (eFbFmt) + { + case eFBFmt_MONOCHROME: + case eFBFmt_R8: + case eFBFmt_INDEX8: + case eFBFmt_NV12: + case eFBFmt_NV16: + u32bpp = 8U; + break; + + case eFBFmt_X4R4G4B4: + case eFBFmt_A4R4G4B4: + case eFBFmt_X1R5G5B5: + case eFBFmt_A1R5G5B5: + case eFBFmt_R5G6B5: + case eFBFmt_YUY2: + case eFBFmt_UYVY: + case eFBFmt_YV12: + case eFBFmt_RG16: + u32bpp = 16U; + break; + + case eFBFmt_INDEX1: + u32bpp = 1U; + break; + + case eFBFmt_INDEX2: + u32bpp = 2U; + break; + + case eFBFmt_INDEX4: + u32bpp = 4U; + break; + + default: + u32bpp = 32U; + break; + } + return u32bpp; +} + +uint64_t DISP_GeneratePixelClk(uint32_t u32PixClkInHz) +{ + uint64_t u64PixClkOut; + + /* Set new VPLL clock frequency. */ + u32PixClkInHz <<= 1U; + u64PixClkOut = CLK_SetPLLFreq(VPLL, PLL_OPMODE_INTEGER, __HXT, (uint64_t)u32PixClkInHz); + + /* Waiting clock ready */ + CLK_WaitClockReady(CLK_STATUS_VPLLSTB_Msk); + + return u64PixClkOut; +} + +void DISP_SuspendPixelClk(void) +{ + /* Stop VPLL forcely. */ + CLK_SetPLLPowerDown(VPLL); +} + +void DISP_SetTiming(DISP_LCD_TIMING *psLCDTiming) +{ + uint32_t u32HEnd, u32HTotal, u32HSyncStart, u32HSyncEnd; + uint32_t u32VEnd, u32VTotal, u32VSyncStart, u32VSyncEnd; + uint32_t u32Value; + + /* Set H- timing */ + u32HEnd = psLCDTiming->u32HA; + u32HTotal = u32HEnd + psLCDTiming->u32HFP + psLCDTiming->u32HBP + psLCDTiming->u32HSL; + u32HSyncStart = u32HEnd + psLCDTiming->u32HFP; + u32HSyncEnd = u32HSyncStart + psLCDTiming->u32HSL; + + u32Value = (u32HTotal << DISP_HDisplay0_TOTAL_Pos) | (u32HEnd << DISP_HDisplay0_DISPLAY_END_Pos); + DISP->HDisplay0 = u32Value; + + u32Value = 0U; + if (psLCDTiming->eHSPP != ePolarity_Disable) + { + u32Value = (psLCDTiming->eHSPP << DISP_HSync0_POLARITY_Pos) | DISP_HSync0_PULSE_Msk; + } + + u32Value |= (u32HSyncEnd << DISP_HSync0_END_Pos) | (u32HSyncStart << DISP_HSync0_START_Pos); + DISP->HSync0 = u32Value; + + /* Set V- timing */ + u32VEnd = psLCDTiming->u32VA; + u32VTotal = u32VEnd + psLCDTiming->u32VFP + psLCDTiming->u32VBP + psLCDTiming->u32VSL; + u32VSyncStart = u32VEnd + psLCDTiming->u32VFP; + u32VSyncEnd = u32VSyncStart + psLCDTiming->u32VSL; + + u32Value = (u32VTotal << DISP_VDisplay0_TOTAL_Pos) | (u32VEnd << DISP_VDisplay0_DISPLAY_END_Pos); + DISP->VDisplay0 = u32Value; + + u32Value = 0U; + if (psLCDTiming->eVSPP != ePolarity_Disable) + { + u32Value = (psLCDTiming->eVSPP << DISP_VSync0_POLARITY_Pos) | DISP_VSync0_PULSE_Msk; + } + + u32Value |= (u32VSyncEnd << DISP_VSync0_END_Pos) | (u32VSyncStart << DISP_VSync0_START_Pos); + DISP->VSync0 = u32Value; +} + +void DISP_SetPanelConf(DISP_PANEL_CONF *psPanelConf) +{ + uint32_t u32Value = 0U; + + if (psPanelConf->eDEP != ePolarity_Disable) + { + u32Value = (psPanelConf->eDEP << DISP_PanelConfig0_DE_POLARITY_Pos) | DISP_PanelConfig0_DE_Msk; + } + + if (psPanelConf->eDP != ePolarity_Disable) + { + u32Value |= ((psPanelConf->eDP << DISP_PanelConfig0_DATA_POLARITY_Pos) | DISP_PanelConfig0_DATA_ENABLE_Msk); + } + + if (psPanelConf->eCP != ePolarity_Disable) + { + u32Value |= ((psPanelConf->eCP << DISP_PanelConfig0_CLOCK_POLARITY_Pos) | DISP_PanelConfig0_CLOCK_Msk); + } + + DISP->DbiConfig0 = 0x00000080U; + DISP->DpiConfig0 = psPanelConf->eDpiFmt << DISP_DpiConfig0_DPI_DATA_FORMAT_Pos; + DISP->PanelConfig0 = u32Value; +} + +int DISP_SetTransparencyMode(E_DISP_LAYER eLayer, E_TRANSPARENCY_MODE eTM) +{ + switch (eLayer) + { + + case eLayer_Video: + DISP->FrameBufferConfig0 &= ~DISP_FrameBufferConfig0_TRANSPARENCY_Msk; + DISP->FrameBufferConfig0 |= (eTM << DISP_FrameBufferConfig0_TRANSPARENCY_Pos); + break; + + case eLayer_Overlay: + DISP->OverlayConfig0 &= ~DISP_OverlayConfig0_TRANSPARENCY_Msk; + DISP->OverlayConfig0 |= (eTM << DISP_OverlayConfig0_TRANSPARENCY_Pos); + break; + + default: + return -1; + } + + return 0; +} + +int DISP_Trigger(E_DISP_LAYER eLayer, uint32_t u32Action) +{ + switch (eLayer) + { + case eLayer_Video: + if (u32Action) + { + /* Start engine clock. */ + CLK_EnableModuleClock(DCU_MODULE); + + /* Generate Pixel clock */ + DISP_GeneratePixelClk(g_psDispLcdInfo_Curr->sLcdTiming.u32PCF); + + DISP->FrameBufferConfig0 |= DISP_FrameBufferConfig0_OUTPUT_Msk; + } + else + { + DISP->FrameBufferConfig0 &= ~DISP_FrameBufferConfig0_OUTPUT_Msk; + + /* Stop pixel clock. */ + DISP_SuspendPixelClk(); + + /* Stop engine clock. */ + CLK_DisableModuleClock(DCU_MODULE); + } + break; + + case eLayer_Overlay: + if (u32Action) + { + DISP->OverlayConfig0 = (DISP->OverlayConfig0 & ~DISP_OverlayConfig0_ENABLE_Msk) | DISP_OverlayConfig0_ENABLE_Msk; + } + else + { + DISP->OverlayConfig0 &= ~DISP_OverlayConfig0_ENABLE_Msk; + } + break; + + default: + return -1; + } + + return 0; +} + +int DISP_SetBlendOpMode(E_DC_BLEND_MODE eDCBM, E_GLOBAL_ALPHA_MODE eGloAM_Src, E_GLOBAL_ALPHA_MODE eGloAM_Dst) +{ + uint32_t u32Value; + + u32Value = (eGloAM_Dst << DISP_OverlayAlphaBlendConfig0_DST_GLOBAL_ALPHA_MODE_Pos) | + (eGloAM_Src << DISP_OverlayAlphaBlendConfig0_SRC_GLOBAL_ALPHA_MODE_Pos); + + switch (eDCBM) + { + case DC_BLEND_MODE_CLEAR: + u32Value |= (eBM_ZERO << DISP_OverlayAlphaBlendConfig0_SRC_BLENDING_MODE_Pos) | + (eBM_ZERO << DISP_OverlayAlphaBlendConfig0_DST_BLENDING_MODE_Pos); + break; + case DC_BLEND_MODE_SRC: + u32Value |= (eBM_ONE << DISP_OverlayAlphaBlendConfig0_SRC_BLENDING_MODE_Pos) | + (eBM_ZERO << DISP_OverlayAlphaBlendConfig0_DST_BLENDING_MODE_Pos); + break; + case DC_BLEND_MODE_DST: + u32Value |= (eBM_ZERO << DISP_OverlayAlphaBlendConfig0_SRC_BLENDING_MODE_Pos) | + (eBM_ONE << DISP_OverlayAlphaBlendConfig0_DST_BLENDING_MODE_Pos); + break; + case DC_BLEND_MODE_SRC_OVER: + u32Value |= (eBM_ONE << DISP_OverlayAlphaBlendConfig0_SRC_BLENDING_MODE_Pos) | + (eBM_INVERSED << DISP_OverlayAlphaBlendConfig0_DST_BLENDING_MODE_Pos); + break; + case DC_BLEND_MODE_DST_OVER: + u32Value |= (eBM_INVERSED << DISP_OverlayAlphaBlendConfig0_SRC_BLENDING_MODE_Pos) | + (eBM_ONE << DISP_OverlayAlphaBlendConfig0_DST_BLENDING_MODE_Pos); + break; + case DC_BLEND_MODE_SRC_IN: + u32Value |= (eBM_NORMAL << DISP_OverlayAlphaBlendConfig0_SRC_BLENDING_MODE_Pos) | + (eBM_ZERO << DISP_OverlayAlphaBlendConfig0_DST_BLENDING_MODE_Pos); + break; + case DC_BLEND_MODE_DST_IN: + u32Value |= (eBM_ZERO << DISP_OverlayAlphaBlendConfig0_SRC_BLENDING_MODE_Pos) | + (eBM_NORMAL << DISP_OverlayAlphaBlendConfig0_DST_BLENDING_MODE_Pos); + break; + case DC_BLEND_MODE_SRC_OUT: + u32Value |= (eBM_INVERSED << DISP_OverlayAlphaBlendConfig0_SRC_BLENDING_MODE_Pos) | + (eBM_ZERO << DISP_OverlayAlphaBlendConfig0_DST_BLENDING_MODE_Pos); + break; + default: + return -1; + } + + DISP->OverlayAlphaBlendConfig0 = u32Value; + + return 0; +} + +void DISP_SetBlendValue(uint32_t u32GloAV_Src, uint32_t u32GloAV_Dst) +{ + DISP->OverlaySrcGlobalColor0 = u32GloAV_Src; + DISP->OverlayDstGlobalColor0 = u32GloAV_Dst; +} + +void DISP_SetColorKeyValue(uint32_t u32ColorKeyLow, uint32_t u32ColorKeyHigh) +{ + DISP->OverlayColorKey0 = u32ColorKeyLow; + DISP->OverlayColorKeyHigh0 = u32ColorKeyHigh; +} + +int DISP_SetFBAddr(E_DISP_LAYER eLayer, uint32_t u32DMAFBStartAddr) +{ + /* Check Start address is 128B alignment. */ + if ((u32DMAFBStartAddr % 128) != 0) + return -1; + + switch (eLayer) + { + case eLayer_Video: + /* Set frame buffer address registers */ + DISP->FrameBufferAddress0 = u32DMAFBStartAddr; + break; + case eLayer_Overlay: + /* Set frame buffer address registers */ + DISP->OverlayAddress0 = u32DMAFBStartAddr; + break; + default: + return -1; + } + return 0; +} + +int DISP_SetFBFmt(E_DISP_LAYER eLayer, E_FB_FMT eFbFmt, uint32_t u32Pitch) +{ + switch (eLayer) + { + case eLayer_Video: + { + uint32_t u32FBConf = DISP->FrameBufferConfig0; + + DISP->FrameBufferConfig0 = 0; + DISP->FrameBufferStride0 = u32Pitch; + u32FBConf = (u32FBConf & ~DISP_FrameBufferConfig0_FORMAT_Msk) | + (eFbFmt << DISP_FrameBufferConfig0_FORMAT_Pos) | + DISP_FrameBufferConfig0_RESET_Msk; + + DISP->FrameBufferConfig0 = u32FBConf; + + break; + } + default: + return -2; + } + + return 0; +} + + +int DISP_SetFBConfig(E_DISP_LAYER eLayer, E_FB_FMT eFbFmt, uint32_t u32ResWidth, uint32_t u32ResHeight, uint32_t u32DMAFBStartAddr) +{ + uint32_t u32bpp; + + /* Check Start address is 128B alignment. */ + if ((u32DMAFBStartAddr % 128) != 0) + return -1; + + u32bpp = DISP_GetBitPerPixel(eFbFmt); + + switch (eLayer) + { + case eLayer_Video: + DISP->FrameBufferUPlanarAddress0 = 0U; + DISP->FrameBufferVPlanarAddress0 = 0U; + DISP->FrameBufferUStride0 = 0U; + DISP->FrameBufferVStride0 = 0U; + DISP->IndexColorTableIndex0 = 0U; + + DISP->FrameBufferSize0 = (u32ResHeight << DISP_FrameBufferSize0_HEIGHT_Pos) | + (u32ResWidth << DISP_FrameBufferSize0_WIDTH_Pos); + + DISP->FrameBufferStride0 = u32ResWidth * (u32bpp >> 3U); + + /* Set frame buffer address registers */ + DISP->FrameBufferAddress0 = u32DMAFBStartAddr; + + DISP->FrameBufferConfig0 = (eFbFmt << DISP_FrameBufferConfig0_FORMAT_Pos) | + (eYUV_709_BT709 << DISP_FrameBufferConfig0_YUV_Pos) | + (DISP_FrameBufferConfig0_RESET_Msk); + + break; + + case eLayer_Overlay: + + DISP->OverlayStride0 = u32ResWidth * (u32bpp >> 3U); + + /* + * eFbFmt is fixed in eFBFmt_A8R8G8B8. + */ + DISP->OverlayConfig0 = (eFBFmt_A8R8G8B8 << DISP_OverlayConfig0_FORMAT_Pos) | + (0 << DISP_OverlayConfig0_SWIZZLE_Pos) | + (0 << DISP_OverlayConfig0_TRANSPARENCY_Pos) | + (eYUV_709_BT709 << DISP_OverlayConfig0_YUV_Pos) | + (0 << DISP_OverlayConfig0_CLEAR_Pos); + + /* Set frame buffer address registers */ + DISP->OverlayAddress0 = u32DMAFBStartAddr; + + DISP->OverlayVStride0 = 0U; + + DISP->OverlayUStride0 = 0U; + DISP->OverlayVStride0 = 0U; + + DISP->OverlaySize0 = (u32ResHeight << DISP_OverlaySize0_HEIGHT_Pos) | + (u32ResWidth << DISP_OverlaySize0_WIDTH_Pos); + + DISP->OverlayTL0 = (0U << DISP_OverlayTL0_Y_Pos) | (0 << DISP_OverlayTL0_X_Pos); + DISP->OverlayBR0 = (u32ResHeight << DISP_OverlayBR0_Y_Pos) | (u32ResWidth << DISP_OverlayBR0_X_Pos); + + /* Default setting */ + DISP_SetBlendOpMode(DC_BLEND_MODE_SRC_OVER, eGloAM_NORMAL, eGloAM_NORMAL); + DISP->OverlayClearValue0 = 0U; + DISP_SetColorKeyValue(0U, 0U); + + DISP->OverlayUPlanarAddress0 = 0U; + DISP->OverlayVPlanarAddress0 = 0U; + + break; + + default: + return -2; + } + + return 0; +} + +int32_t DISP_LCDInit(const DISP_LCD_INFO *psLCDInfo) +{ + vu32 vu32UsDelay = CLK_GetPLLClockFreq(CAPLL) / 1000000; + vu32 vu32Timeout; + DISP_LCD_TIMING *psLCDTiming = (DISP_LCD_TIMING *)&psLCDInfo->sLcdTiming; + DISP_PANEL_CONF *psPanelConf = (DISP_PANEL_CONF *)&psLCDInfo->sPanelConf; + + /* Store to current. */ + g_psDispLcdInfo_Curr = psLCDInfo; + + /* Start engine clock. */ + DISP_SuspendPixelClk(); + + /* Reset */ + SYS->IPRST0 |= SYS_IPRST0_DISPCRST_Msk; + vu32Timeout = 100 * vu32UsDelay; + while (vu32Timeout--); + SYS->IPRST0 &= ~SYS_IPRST0_DISPCRST_Msk; + vu32Timeout = 100 * vu32UsDelay; + while (vu32Timeout--); + + DISP->FrameBufferConfig0 = 0U; + DISP->AQHiClockControl = 0x00071900U; + DISP->AQHiClockControl = 0x00070900U; + + /* Delay 5ms */ + vu32Timeout = 5000 * vu32UsDelay; + while (vu32Timeout--); + + /* Set timing */ + DISP_SetTiming(psLCDTiming); + + /* Set Panel config */ + DISP_SetPanelConf(psPanelConf); + + return 0; +} + +int32_t DISP_LCDDeinit(void) +{ + /* Stop engine clock */ + DISP_SuspendPixelClk(); + + /* Stop engine clock. */ + CLK_DisableModuleClock(DCU_MODULE); + + g_psDispLcdInfo_Curr = NULL; + + return 0; +} + +const DISP_LCD_INFO *DISP_GetLCDInst(E_DISP_LCD eDispLcd) +{ + if (eDispLcd < eDispLcd_Cnt) + return &g_sLcdInfo_arr[eDispLcd]; + + return (const DISP_LCD_INFO *)NULL; +} + +/*@}*/ /* end of group DISP_EXPORTED_FUNCTIONS */ + +/*@}*/ /* end of group DISP_Driver */ + +/*@}*/ /* end of group Standard_Driver */ + + + + diff --git a/bsp/nuvoton/libraries/ma35/StdDriver/src/nu_eadc.c b/bsp/nuvoton/libraries/ma35/StdDriver/src/nu_eadc.c new file mode 100644 index 0000000000..647e089b21 --- /dev/null +++ b/bsp/nuvoton/libraries/ma35/StdDriver/src/nu_eadc.c @@ -0,0 +1,141 @@ +/**************************************************************************//** + * @file eadc.c + * @brief series EADC driver source file + * + * SPDX-License-Identifier: Apache-2.0 + * @copyright (C) 2020 Nuvoton Technology Corp. All rights reserved. + *****************************************************************************/ +#include "NuMicro.h" + +/** @addtogroup Standard_Driver Standard Driver + @{ +*/ + +/** @addtogroup EADC_Driver EADC Driver + @{ +*/ + +/** @addtogroup EADC_EXPORTED_FUNCTIONS EADC Exported Functions + @{ +*/ + +/** + * @brief This function make EADC_module be ready to convert. + * @param[in] eadc The pointer of the specified EADC module. + * @param[in] u32InputMode Decides the input mode. + * - \ref EADC_CTL_DIFFEN_SINGLE_END :Single end input mode. + * - \ref EADC_CTL_DIFFEN_DIFFERENTIAL :Differential input type. + * @return None + * @details This function is used to set analog input mode and enable A/D Converter. + * Before starting A/D conversion function, ADCEN bit (EADC_CTL[0]) should be set to 1. + * @note + */ +void EADC_Open(EADC_T *eadc, uint32_t u32InputMode) +{ + eadc->CTL &= (~EADC_CTL_DIFFEN_Msk); + + eadc->CTL |= (u32InputMode | EADC_CTL_ADCEN_Msk); + while (!(eadc->PWRM & EADC_PWRM_PWUPRDY_Msk)) {} +} + +/** + * @brief Disable EADC_module. + * @param[in] eadc The pointer of the specified EADC module.. + * @return None + * @details Clear ADCEN bit (EADC_CTL[0]) to disable A/D converter analog circuit power consumption. + */ +void EADC_Close(EADC_T *eadc) +{ + eadc->CTL &= ~EADC_CTL_ADCEN_Msk; +} + +/** + * @brief Configure the sample control logic module. + * @param[in] eadc The pointer of the specified EADC module. + * @param[in] u32ModuleNum Decides the sample module number, valid value are from 0 to 15. + * @param[in] u32TriggerSrc Decides the trigger source. Valid values are: + * - \ref EADC_SOFTWARE_TRIGGER : Disable trigger + * - \ref EADC_FALLING_EDGE_TRIGGER : STADC pin falling edge trigger + * - \ref EADC_RISING_EDGE_TRIGGER : STADC pin rising edge trigger + * - \ref EADC_FALLING_RISING_EDGE_TRIGGER : STADC pin both falling and rising edge trigger + * - \ref EADC_ADINT0_TRIGGER : EADC ADINT0 interrupt EOC pulse trigger + * - \ref EADC_ADINT1_TRIGGER : EADC ADINT1 interrupt EOC pulse trigger + * - \ref EADC_TIMER0_TRIGGER : Timer0 overflow pulse trigger + * - \ref EADC_TIMER1_TRIGGER : Timer1 overflow pulse trigger + * - \ref EADC_TIMER2_TRIGGER : Timer2 overflow pulse trigger + * - \ref EADC_TIMER3_TRIGGER : Timer3 overflow pulse trigger + * - \ref EADC_EPWM0TG0_TRIGGER : EPWM0TG0 trigger + * - \ref EADC_EPWM0TG1_TRIGGER : EPWM0TG1 trigger + * - \ref EADC_EPWM0TG2_TRIGGER : EPWM0TG2 trigger + * - \ref EADC_EPWM0TG3_TRIGGER : EPWM0TG3 trigger + * - \ref EADC_EPWM0TG4_TRIGGER : EPWM0TG4 trigger + * - \ref EADC_EPWM0TG5_TRIGGER : EPWM0TG5 trigger + * - \ref EADC_EPWM1TG0_TRIGGER : EPWM1TG0 trigger + * - \ref EADC_EPWM1TG1_TRIGGER : EPWM1TG1 trigger + * - \ref EADC_EPWM1TG2_TRIGGER : EPWM1TG2 trigger + * - \ref EADC_EPWM1TG3_TRIGGER : EPWM1TG3 trigger + * - \ref EADC_EPWM1TG4_TRIGGER : EPWM1TG4 trigger + * - \ref EADC_EPWM1TG5_TRIGGER : EPWM1TG5 trigger + * - \ref EADC_BPWM0TG_TRIGGER : BPWM0TG trigger + * - \ref EADC_BPWM1TG_TRIGGER : BPWM1TG trigger + * @param[in] u32Channel Specifies the sample module channel, valid value are from 0 to 15. + * @return None + * @details Each of ADC control logic modules 0~15 which is configurable for ADC converter channel EADC_CH0~15 and trigger source. + * sample module 16~18 is fixed for ADC channel 16, 17, 18 input sources as band-gap voltage, temperature sensor, and battery power (VBAT). + */ +void EADC_ConfigSampleModule(EADC_T *eadc, \ + uint32_t u32ModuleNum, \ + uint32_t u32TriggerSrc, \ + uint32_t u32Channel) +{ + eadc->SCTL[u32ModuleNum] &= ~(EADC_SCTL_EXTFEN_Msk | EADC_SCTL_EXTREN_Msk | EADC_SCTL_TRGSEL_Msk | EADC_SCTL_CHSEL_Msk); + eadc->SCTL[u32ModuleNum] |= (u32TriggerSrc | u32Channel); +} + + +/** + * @brief Set trigger delay time. + * @param[in] eadc The pointer of the specified EADC module. + * @param[in] u32ModuleNum Decides the sample module number, valid value are from 0 to 15. + * @param[in] u32TriggerDelayTime Decides the trigger delay time, valid range are between 0~0xFF. + * @param[in] u32DelayClockDivider Decides the trigger delay clock divider. Valid values are: + * - \ref EADC_SCTL_TRGDLYDIV_DIVIDER_1 : Trigger delay clock frequency is ADC_CLK/1 + * - \ref EADC_SCTL_TRGDLYDIV_DIVIDER_2 : Trigger delay clock frequency is ADC_CLK/2 + * - \ref EADC_SCTL_TRGDLYDIV_DIVIDER_4 : Trigger delay clock frequency is ADC_CLK/4 + * - \ref EADC_SCTL_TRGDLYDIV_DIVIDER_16 : Trigger delay clock frequency is ADC_CLK/16 + * @return None + * @details User can configure the trigger delay time by setting TRGDLYCNT (EADC_SCTLn[15:8], n=0~15) and TRGDLYDIV (EADC_SCTLn[7:6], n=0~15). + * Trigger delay time = (u32TriggerDelayTime) x Trigger delay clock period. + */ +void EADC_SetTriggerDelayTime(EADC_T *eadc, \ + uint32_t u32ModuleNum, \ + uint32_t u32TriggerDelayTime, \ + uint32_t u32DelayClockDivider) +{ + eadc->SCTL[u32ModuleNum] &= ~(EADC_SCTL_TRGDLYDIV_Msk | EADC_SCTL_TRGDLYCNT_Msk); + eadc->SCTL[u32ModuleNum] |= ((u32TriggerDelayTime << EADC_SCTL_TRGDLYCNT_Pos) | u32DelayClockDivider); +} + +/** + * @brief Set ADC extend sample time. + * @param[in] eadc The pointer of the specified EADC module. + * @param[in] u32ModuleNum Decides the sample module number, valid value are from 0 to 18. + * @param[in] u32ExtendSampleTime Decides the extend sampling time, the range is from 0~255 ADC clock. Valid value are from 0 to 0xFF. + * @return None + * @details When A/D converting at high conversion rate, the sampling time of analog input voltage may not enough if input channel loading is heavy, + * user can extend A/D sampling time after trigger source is coming to get enough sampling time. + */ +void EADC_SetExtendSampleTime(EADC_T *eadc, uint32_t u32ModuleNum, uint32_t u32ExtendSampleTime) +{ + eadc->SCTL[u32ModuleNum] &= ~EADC_SCTL_EXTSMPT_Msk; + + eadc->SCTL[u32ModuleNum] |= (u32ExtendSampleTime << EADC_SCTL_EXTSMPT_Pos); + +} + +/*@}*/ /* end of group EADC_EXPORTED_FUNCTIONS */ + +/*@}*/ /* end of group EADC_Driver */ + +/*@}*/ /* end of group Standard_Driver */ + diff --git a/bsp/nuvoton/libraries/ma35/StdDriver/src/nu_ebi.c b/bsp/nuvoton/libraries/ma35/StdDriver/src/nu_ebi.c new file mode 100644 index 0000000000..5bb90872a9 --- /dev/null +++ b/bsp/nuvoton/libraries/ma35/StdDriver/src/nu_ebi.c @@ -0,0 +1,193 @@ +/**************************************************************************//** + * @file ebi.c + * @brief External Bus Interface(EBI) driver source file + * + * SPDX-License-Identifier: Apache-2.0 + * @copyright (C) 2020 Nuvoton Technology Corp. All rights reserved. + *****************************************************************************/ +#include "NuMicro.h" + +/** @addtogroup Standard_Driver Standard Driver + @{ +*/ + +/** @addtogroup EBI_Driver EBI Driver + @{ +*/ + + +/** @addtogroup EBI_EXPORTED_FUNCTIONS EBI Exported Functions + @{ +*/ + +/** + * @brief Initialize EBI for specify Bank + * + * @param[in] u32Bank Bank number for EBI. Valid values are: + * - \ref EBI_BANK0 + * - \ref EBI_BANK1 + * - \ref EBI_BANK2 + * @param[in] u32DataWidth Data bus width. Valid values are: + * - \ref EBI_BUSWIDTH_8BIT + * - \ref EBI_BUSWIDTH_16BIT + * @param[in] u32TimingClass Default timing configuration. Valid values are: + * - \ref EBI_TIMING_FASTEST + * - \ref EBI_TIMING_VERYFAST + * - \ref EBI_TIMING_FAST + * - \ref EBI_TIMING_NORMAL + * - \ref EBI_TIMING_SLOW + * - \ref EBI_TIMING_VERYSLOW + * - \ref EBI_TIMING_SLOWEST + * @param[in] u32BusMode Set EBI bus operate mode. Valid values are: + * - \ref EBI_OPMODE_NORMAL + * - \ref EBI_OPMODE_CACCESS + * - \ref EBI_OPMODE_ADSEPARATE + * @param[in] u32CSActiveLevel CS is active High/Low. Valid values are: + * - \ref EBI_CS_ACTIVE_HIGH + * - \ref EBI_CS_ACTIVE_LOW + * + * @return None + * + * @details This function is used to open specify EBI bank with different bus width, timing setting and \n + * active level of CS pin to access EBI device. + * @note Write Buffer Enable(WBUFEN) and Extend Time Of ALE(TALE) are only available in EBI bank0 control register. + */ +void EBI_Open(uint32_t u32Bank, uint32_t u32DataWidth, uint32_t u32TimingClass, uint32_t u32BusMode, uint32_t u32CSActiveLevel) +{ + uint32_t u32Index0 = (uint32_t)&EBI->CTL0 + (uint32_t)u32Bank * 0x10U; + uint32_t u32Index1 = (uint32_t)&EBI->TCTL0 + (uint32_t)u32Bank * 0x10U; + volatile uint32_t *pu32EBICTL = (uint32_t *)(u32Index0); + volatile uint32_t *pu32EBITCTL = (uint32_t *)(u32Index1); + + if (u32DataWidth == EBI_BUSWIDTH_8BIT) + { + *pu32EBICTL &= ~EBI_CTL_DW16_Msk; + } + else + { + *pu32EBICTL |= EBI_CTL_DW16_Msk; + } + + *pu32EBICTL |= u32BusMode; + + switch (u32TimingClass) + { + case EBI_TIMING_FASTEST: + *pu32EBICTL = (*pu32EBICTL & ~(EBI_CTL_MCLKDIV_Msk | EBI_CTL_TALE_Msk)) | + (EBI_MCLKDIV_1 << EBI_CTL_MCLKDIV_Pos) | + (u32CSActiveLevel << EBI_CTL_CSPOLINV_Pos) | EBI_CTL_EN_Msk; + *pu32EBITCTL = 0x0U; + break; + + case EBI_TIMING_VERYFAST: + *pu32EBICTL = (*pu32EBICTL & ~(EBI_CTL_MCLKDIV_Msk | EBI_CTL_TALE_Msk)) | + (EBI_MCLKDIV_1 << EBI_CTL_MCLKDIV_Pos) | + (u32CSActiveLevel << EBI_CTL_CSPOLINV_Pos) | EBI_CTL_EN_Msk | + (0x3U << EBI_CTL_TALE_Pos) ; + *pu32EBITCTL = 0x03003318U; + break; + + case EBI_TIMING_FAST: + *pu32EBICTL = (*pu32EBICTL & ~(EBI_CTL_MCLKDIV_Msk | EBI_CTL_TALE_Msk)) | + (EBI_MCLKDIV_2 << EBI_CTL_MCLKDIV_Pos) | + (u32CSActiveLevel << EBI_CTL_CSPOLINV_Pos) | EBI_CTL_EN_Msk; + *pu32EBITCTL = 0x0U; + break; + + case EBI_TIMING_NORMAL: + *pu32EBICTL = (*pu32EBICTL & ~(EBI_CTL_MCLKDIV_Msk | EBI_CTL_TALE_Msk)) | + (EBI_MCLKDIV_2 << EBI_CTL_MCLKDIV_Pos) | + (u32CSActiveLevel << EBI_CTL_CSPOLINV_Pos) | EBI_CTL_EN_Msk | + (0x3U << EBI_CTL_TALE_Pos) ; + *pu32EBITCTL = 0x03003318U; + break; + + case EBI_TIMING_SLOW: + *pu32EBICTL = (*pu32EBICTL & ~(EBI_CTL_MCLKDIV_Msk | EBI_CTL_TALE_Msk)) | + (EBI_MCLKDIV_2 << EBI_CTL_MCLKDIV_Pos) | + (u32CSActiveLevel << EBI_CTL_CSPOLINV_Pos) | EBI_CTL_EN_Msk | + (0x7U << EBI_CTL_TALE_Pos) ; + *pu32EBITCTL = 0x07007738U; + break; + + case EBI_TIMING_VERYSLOW: + *pu32EBICTL = (*pu32EBICTL & ~(EBI_CTL_MCLKDIV_Msk | EBI_CTL_TALE_Msk)) | + (EBI_MCLKDIV_8 << EBI_CTL_MCLKDIV_Pos) | + (u32CSActiveLevel << EBI_CTL_CSPOLINV_Pos) | EBI_CTL_EN_Msk | + (0x7U << EBI_CTL_TALE_Pos) ; + *pu32EBITCTL = 0x07007738U; + break; + + case EBI_TIMING_SLOWEST: + *pu32EBICTL = (*pu32EBICTL & ~(EBI_CTL_MCLKDIV_Msk | EBI_CTL_TALE_Msk)) | + (EBI_MCLKDIV_16 << EBI_CTL_MCLKDIV_Pos) | + (u32CSActiveLevel << EBI_CTL_CSPOLINV_Pos) | EBI_CTL_EN_Msk | + (0x7U << EBI_CTL_TALE_Pos) ; + *pu32EBITCTL = 0x07007738U; + break; + + default: + *pu32EBICTL &= ~EBI_CTL_EN_Msk; + break; + } +} + +/** + * @brief Disable EBI on specify Bank + * + * @param[in] u32Bank Bank number for EBI. Valid values are: + * - \ref EBI_BANK0 + * - \ref EBI_BANK1 + * - \ref EBI_BANK2 + * + * @return None + * + * @details This function is used to close specify EBI function. + */ +void EBI_Close(uint32_t u32Bank) +{ + uint32_t u32Index = (uint32_t)&EBI->CTL0 + u32Bank * 0x10U; + volatile uint32_t *pu32EBICTL = (uint32_t *)(u32Index); + + *pu32EBICTL &= ~EBI_CTL_EN_Msk; +} + +/** + * @brief Set EBI Bus Timing for specify Bank + * + * @param[in] u32Bank Bank number for EBI. Valid values are: + * - \ref EBI_BANK0 + * - \ref EBI_BANK1 + * - \ref EBI_BANK2 + * @param[in] u32TimingConfig Configure EBI timing settings, includes TACC, TAHD, W2X and R2R setting. + * @param[in] u32MclkDiv Divider for MCLK. Valid values are: + * - \ref EBI_MCLKDIV_1 + * - \ref EBI_MCLKDIV_2 + * - \ref EBI_MCLKDIV_4 + * - \ref EBI_MCLKDIV_8 + * - \ref EBI_MCLKDIV_16 + * - \ref EBI_MCLKDIV_32 + * - \ref EBI_MCLKDIV_64 + * - \ref EBI_MCLKDIV_128 + * + * @return None + * + * @details This function is used to configure specify EBI bus timing for access EBI device. + */ +void EBI_SetBusTiming(uint32_t u32Bank, uint32_t u32TimingConfig, uint32_t u32MclkDiv) +{ + uint32_t u32Index0 = (uint32_t)&EBI->CTL0 + (uint32_t)u32Bank * 0x10U; + uint32_t u32Index1 = (uint32_t)&EBI->TCTL0 + (uint32_t)u32Bank * 0x10U; + volatile uint32_t *pu32EBICTL = (uint32_t *)(u32Index0); + volatile uint32_t *pu32EBITCTL = (uint32_t *)(u32Index1); + + *pu32EBICTL = (*pu32EBICTL & ~EBI_CTL_MCLKDIV_Msk) | (u32MclkDiv << EBI_CTL_MCLKDIV_Pos); + *pu32EBITCTL = u32TimingConfig; +} + +/*@}*/ /* end of group EBI_EXPORTED_FUNCTIONS */ + +/*@}*/ /* end of group EBI_Driver */ + +/*@}*/ /* end of group Standard_Driver */ + diff --git a/bsp/nuvoton/libraries/ma35/StdDriver/src/nu_ecap.c b/bsp/nuvoton/libraries/ma35/StdDriver/src/nu_ecap.c new file mode 100644 index 0000000000..2e28c0810a --- /dev/null +++ b/bsp/nuvoton/libraries/ma35/StdDriver/src/nu_ecap.c @@ -0,0 +1,96 @@ +/**************************************************************************//** + * @file ecap.c + * @brief Enhanced Input Capture Timer (ECAP) driver source file + * + * SPDX-License-Identifier: Apache-2.0 + * @copyright (C) 2020 Nuvoton Technology Corp. All rights reserved. +*****************************************************************************/ +#include "NuMicro.h" + + +/** @addtogroup Standard_Driver Standard Driver + @{ +*/ + +/** @addtogroup ECAP_Driver ECAP Driver + @{ +*/ + +/** @addtogroup ECAP_EXPORTED_FUNCTIONS ECAP Exported Functions + @{ +*/ + +/** + * @brief Enable ECAP function + * @param[in] ecap The pointer of the specified ECAP module. + * @param[in] u32FuncMask Input capture function select + * - \ref ECAP_DISABLE_COMPARE + * - \ref ECAP_COMPARE_FUNCTION + * @return None + * @details This macro enable input capture function and select compare and reload function. + */ +void ECAP_Open(ECAP_T *ecap, uint32_t u32FuncMask) +{ + /* Clear Input capture mode*/ + ecap->CTL0 = ecap->CTL0 & ~(ECAP_CTL0_CMPEN_Msk); + + /* Enable Input Capture and set mode */ + ecap->CTL0 |= ECAP_CTL0_CAPEN_Msk | (u32FuncMask); +} + + + +/** + * @brief Disable ECAP function + * @param[in] ecap The pointer of the specified ECAP module. + * @return None + * @details This macro disable input capture function. + */ +void ECAP_Close(ECAP_T *ecap) +{ + /* Disable Input Capture*/ + ecap->CTL0 &= ~ECAP_CTL0_CAPEN_Msk; +} + +/** + * @brief This macro is used to enable input channel interrupt + * @param[in] ecap Specify ECAP port + * @param[in] u32Mask The input channel Mask + * - \ref ECAP_CTL0_CAPIEN0_Msk + * - \ref ECAP_CTL0_CAPIEN1_Msk + * - \ref ECAP_CTL0_CAPIEN2_Msk + * - \ref ECAP_CTL0_OVIEN_Msk + * - \ref ECAP_CTL0_CMPIEN_Msk + * @return None + * @details This macro will enable the input channel_n interrupt. + */ +void ECAP_EnableINT(ECAP_T *ecap, uint32_t u32Mask) +{ + /* Enable input channel interrupt */ + ecap->CTL0 |= (u32Mask); +} + +/** + * @brief This macro is used to disable input channel interrupt + * @param[in] ecap Specify ECAP port + * @param[in] u32Mask The input channel number + * - \ref ECAP_CTL0_CAPIEN0_Msk + * - \ref ECAP_CTL0_CAPIEN1_Msk + * - \ref ECAP_CTL0_CAPIEN2_Msk + * - \ref ECAP_CTL0_OVIEN_Msk + * - \ref ECAP_CTL0_CMPIEN_Msk + * @return None + * @details This macro will disable the input channel_n interrupt. + */ +void ECAP_DisableINT(ECAP_T *ecap, uint32_t u32Mask) +{ + /* Disable input channel interrupt */ + ecap->CTL0 &= ~(u32Mask); +} + +/*@}*/ /* end of group ECAP_EXPORTED_FUNCTIONS */ + +/*@}*/ /* end of group ECAP_Driver */ + +/*@}*/ /* end of group Standard_Driver */ + diff --git a/bsp/nuvoton/libraries/ma35/StdDriver/src/nu_epwm.c b/bsp/nuvoton/libraries/ma35/StdDriver/src/nu_epwm.c new file mode 100644 index 0000000000..c28e78d647 --- /dev/null +++ b/bsp/nuvoton/libraries/ma35/StdDriver/src/nu_epwm.c @@ -0,0 +1,1616 @@ +/**************************************************************************//** + * @file epwm.c + * @brief EPWM driver source file + * + * SPDX-License-Identifier: Apache-2.0 + * @copyright (C) 2020 Nuvoton Technology Corp. All rights reserved. + *****************************************************************************/ +#include "NuMicro.h" + +/** @addtogroup Standard_Driver Standard Driver + @{ +*/ + +/** @addtogroup EPWM_Driver EPWM Driver + @{ +*/ + + +/** @addtogroup EPWM_EXPORTED_FUNCTIONS EPWM Exported Functions + @{ +*/ + +/** + * @brief Configure EPWM capture and get the nearest unit time. + * @param[in] epwm The pointer of the specified EPWM module + * - EPWM0 : EPWM Group 0 + * - EPWM1 : EPWM Group 1 + * @param[in] u32ChannelNum EPWM channel number. Valid values are between 0~5 + * @param[in] u32UnitTimeNsec The unit time of counter + * @param[in] u32CaptureEdge The condition to latch the counter. This parameter is not used + * @return The nearest unit time in nano second. + * @details This function is used to Configure EPWM capture and get the nearest unit time. + */ +uint32_t EPWM_ConfigCaptureChannel(EPWM_T *epwm, uint32_t u32ChannelNum, uint32_t u32UnitTimeNsec, uint32_t u32CaptureEdge) +{ + uint32_t u32EPWMClockSrc; + uint32_t u32NearestUnitTimeNsec; + uint32_t u16Prescale = 1U, u16CNR = 0xFFFFU; + + /* clock source is from PCLK */ + SystemCoreClockUpdate(); + u32EPWMClockSrc = CLK_GetPCLK0Freq(); + + u32EPWMClockSrc /= 1000U; + for (u16Prescale = 1U; u16Prescale <= 0x1000U; u16Prescale++) + { + uint32_t u32Exit = 0U; + u32NearestUnitTimeNsec = (1000000U * u16Prescale) / u32EPWMClockSrc; + if (u32NearestUnitTimeNsec < u32UnitTimeNsec) + { + if (u16Prescale == 0x1000U) /* limit to the maximum unit time(nano second) */ + { + u32Exit = 1U; + } + else + { + u32Exit = 0U; + } + if (!((1000000U * (u16Prescale + 1U) > (u32NearestUnitTimeNsec * u32EPWMClockSrc)))) + { + u32Exit = 1U; + } + else + { + u32Exit = 0U; + } + } + else + { + u32Exit = 1U; + } + if (u32Exit == 1U) + { + break; + } + else {} + } + + /* convert to real register value */ + /* every two channels share a prescaler */ + u16Prescale -= 1U; + EPWM_SET_PRESCALER(epwm, u32ChannelNum, u16Prescale); + + /* set EPWM to down count type(edge aligned) */ + (epwm)->CTL1 = ((epwm)->CTL1 & ~(EPWM_CTL1_CNTTYPE0_Msk << (u32ChannelNum << 1U))) | (1UL << (u32ChannelNum << 1U)); + /* set EPWM to auto-reload mode */ + (epwm)->CTL1 &= ~(EPWM_CTL1_CNTMODE0_Msk << u32ChannelNum); + EPWM_SET_CNR(epwm, u32ChannelNum, u16CNR); + + return (u32NearestUnitTimeNsec); +} + +/** + * @brief This function Configure EPWM generator and get the nearest frequency in edge aligned(up counter type) auto-reload mode + * @param[in] epwm The pointer of the specified EPWM module + * - EPWM0 : EPWM Group 0 + * - EPWM1 : EPWM Group 1 + * @param[in] u32ChannelNum EPWM channel number. Valid values are between 0~5 + * @param[in] u32Frequency Target generator frequency + * @param[in] u32DutyCycle Target generator duty cycle percentage. Valid range are between 0 ~ 100. 10 means 10%, 20 means 20%... + * @return Nearest frequency clock in nano second + * @note Since every two channels, (0 & 1), (2 & 3), shares a prescaler. Call this API to configure EPWM frequency may affect + * existing frequency of other channel. + * @note This function is used for initial stage. + * To change duty cycle later, it should get the configured period value and calculate the new comparator value. + */ +uint32_t EPWM_ConfigOutputChannel(EPWM_T *epwm, uint32_t u32ChannelNum, uint32_t u32Frequency, uint32_t u32DutyCycle) +{ + uint32_t u32EPWMClockSrc; + uint32_t i; + uint32_t u32Prescale = 1U, u32CNR = 0xFFFFU; + + /* clock source is from PCLK */ + SystemCoreClockUpdate(); + u32EPWMClockSrc = CLK_GetPCLK0Freq(); + + for (u32Prescale = 1U; u32Prescale < 0xFFFU; u32Prescale++) /* prescale could be 0~0xFFF */ + { + i = (u32EPWMClockSrc / u32Frequency) / u32Prescale; + /* If target value is larger than CNR, need to use a larger prescaler */ + if (i < (0x10000U)) + { + u32CNR = i; + break; + } + } + /* Store return value here 'cos we're gonna change u16Prescale & u16CNR to the real value to fill into register */ + i = u32EPWMClockSrc / (u32Prescale * u32CNR); + + /* convert to real register value */ + /* every two channels share a prescaler */ + u32Prescale -= 1U; + EPWM_SET_PRESCALER(epwm, u32ChannelNum, u32Prescale); + /* set EPWM to up counter type(edge aligned) and auto-reload mode */ + (epwm)->CTL1 = ((epwm)->CTL1 & ~((EPWM_CTL1_CNTTYPE0_Msk << (u32ChannelNum << 1U)) | ((1UL << EPWM_CTL1_CNTMODE0_Pos) << u32ChannelNum))); + + u32CNR -= 1U; + EPWM_SET_CNR(epwm, u32ChannelNum, u32CNR); + EPWM_SET_CMR(epwm, u32ChannelNum, u32DutyCycle * (u32CNR + 1U) / 100U); + + (epwm)->WGCTL0 = ((epwm)->WGCTL0 & ~((EPWM_WGCTL0_PRDPCTL0_Msk | EPWM_WGCTL0_ZPCTL0_Msk) << (u32ChannelNum << 1U))) | \ + ((uint32_t)EPWM_OUTPUT_HIGH << ((u32ChannelNum << 1U) + (uint32_t)EPWM_WGCTL0_ZPCTL0_Pos)); + (epwm)->WGCTL1 = ((epwm)->WGCTL1 & ~((EPWM_WGCTL1_CMPDCTL0_Msk | EPWM_WGCTL1_CMPUCTL0_Msk) << (u32ChannelNum << 1U))) | \ + ((uint32_t)EPWM_OUTPUT_LOW << ((u32ChannelNum << 1U) + (uint32_t)EPWM_WGCTL1_CMPUCTL0_Pos)); + + return (i); +} + +/** + * @brief Start EPWM module + * @param[in] epwm The pointer of the specified EPWM module + * - EPWM0 : EPWM Group 0 + * - EPWM1 : EPWM Group 1 + * @param[in] u32ChannelMask Combination of enabled channels. Each bit corresponds to a channel. + * Bit 0 is channel 0, bit 1 is channel 1... + * @return None + * @details This function is used to start EPWM module. + */ +void EPWM_Start(EPWM_T *epwm, uint32_t u32ChannelMask) +{ + (epwm)->CNTEN |= u32ChannelMask; +} + +/** + * @brief Stop EPWM module + * @param[in] epwm The pointer of the specified EPWM module + * - EPWM0 : EPWM Group 0 + * - EPWM1 : EPWM Group 1 + * @param[in] u32ChannelMask Combination of enabled channels. Each bit corresponds to a channel. + * Bit 0 is channel 0, bit 1 is channel 1... + * @return None + * @details This function is used to stop EPWM module. + */ +void EPWM_Stop(EPWM_T *epwm, uint32_t u32ChannelMask) +{ + uint32_t i; + for (i = 0U; i < EPWM_CHANNEL_NUM; i ++) + { + if (u32ChannelMask & (1UL << i)) + { + (epwm)->PERIOD[i] = 0U; + } + } +} + +/** + * @brief Stop EPWM generation immediately by clear channel enable bit + * @param[in] epwm The pointer of the specified EPWM module + * - EPWM0 : EPWM Group 0 + * - EPWM1 : EPWM Group 1 + * @param[in] u32ChannelMask Combination of enabled channels. Each bit corresponds to a channel. + * Bit 0 is channel 0, bit 1 is channel 1... + * @return None + * @details This function is used to stop EPWM generation immediately by clear channel enable bit. + */ +void EPWM_ForceStop(EPWM_T *epwm, uint32_t u32ChannelMask) +{ + (epwm)->CNTEN &= ~u32ChannelMask; +} + +/** + * @brief Enable selected channel to trigger ADC + * @param[in] epwm The pointer of the specified EPWM module + * - EPWM0 : EPWM Group 0 + * - EPWM1 : EPWM Group 1 + * @param[in] u32ChannelNum EPWM channel number. Valid values are between 0~5 + * @param[in] u32Condition The condition to trigger ADC. Combination of following conditions: + * - \ref EPWM_TRG_ADC_EVEN_ZERO + * - \ref EPWM_TRG_ADC_EVEN_PERIOD + * - \ref EPWM_TRG_ADC_EVEN_ZERO_PERIOD + * - \ref EPWM_TRG_ADC_EVEN_COMPARE_UP + * - \ref EPWM_TRG_ADC_EVEN_COMPARE_DOWN + * - \ref EPWM_TRG_ADC_ODD_ZERO + * - \ref EPWM_TRG_ADC_ODD_PERIOD + * - \ref EPWM_TRG_ADC_ODD_ZERO_PERIOD + * - \ref EPWM_TRG_ADC_ODD_COMPARE_UP + * - \ref EPWM_TRG_ADC_ODD_COMPARE_DOWN + * - \ref EPWM_TRG_ADC_CH_0_FREE_CMP_UP + * - \ref EPWM_TRG_ADC_CH_0_FREE_CMP_DOWN + * - \ref EPWM_TRG_ADC_CH_2_FREE_CMP_UP + * - \ref EPWM_TRG_ADC_CH_2_FREE_CMP_DOWN + * - \ref EPWM_TRG_ADC_CH_4_FREE_CMP_UP + * - \ref EPWM_TRG_ADC_CH_4_FREE_CMP_DOWN + * @return None + * @details This function is used to enable selected channel to trigger ADC. + */ +void EPWM_EnableADCTrigger(EPWM_T *epwm, uint32_t u32ChannelNum, uint32_t u32Condition) +{ + if (u32ChannelNum < 4U) + { + (epwm)->EADCTS0 &= ~((EPWM_EADCTS0_TRGSEL0_Msk) << (u32ChannelNum << 3U)); + (epwm)->EADCTS0 |= ((EPWM_EADCTS0_TRGEN0_Msk | u32Condition) << (u32ChannelNum << 3)); + } + else + { + (epwm)->EADCTS1 &= ~((EPWM_EADCTS1_TRGSEL4_Msk) << ((u32ChannelNum - 4U) << 3U)); + (epwm)->EADCTS1 |= ((EPWM_EADCTS1_TRGEN4_Msk | u32Condition) << ((u32ChannelNum - 4U) << 3U)); + } +} + +/** + * @brief Disable selected channel to trigger ADC + * @param[in] epwm The pointer of the specified EPWM module + * - EPWM0 : EPWM Group 0 + * - EPWM1 : EPWM Group 1 + * @param[in] u32ChannelNum EPWM channel number. Valid values are between 0~5 + * @return None + * @details This function is used to disable selected channel to trigger ADC. + */ +void EPWM_DisableADCTrigger(EPWM_T *epwm, uint32_t u32ChannelNum) +{ + if (u32ChannelNum < 4U) + { + (epwm)->EADCTS0 &= ~(EPWM_EADCTS0_TRGEN0_Msk << (u32ChannelNum << 3U)); + } + else + { + (epwm)->EADCTS1 &= ~(EPWM_EADCTS1_TRGEN4_Msk << ((u32ChannelNum - 4U) << 3U)); + } +} + +/** + * @brief Enable and configure trigger ADC prescale + * @param[in] epwm The pointer of the specified EPWM module + * - EPWM0 : EPWM Group 0 + * - EPWM1 : EPWM Group 1 + * @param[in] u32ChannelNum EPWM channel number. Valid values are between 0~5. + * @param[in] u32Prescale ADC prescale. Valid values are between 0 to 0xF. + * @param[in] u32PrescaleCnt ADC prescale counter. Valid values are between 0 to 0xF. + * @retval 0 Success. + * @retval -1 Failed. + * @details This function is used to enable and configure trigger ADC prescale. + * @note User can configure only when ADC trigger prescale is disabled. + * @note ADC prescale counter must less than ADC prescale. + */ +int32_t EPWM_EnableADCTriggerPrescale(EPWM_T *epwm, uint32_t u32ChannelNum, uint32_t u32Prescale, uint32_t u32PrescaleCnt) +{ + /* User can write only when PSCENn(n = 0 ~ 5) is 0 */ + if ((epwm)->EADCPSCCTL & (1UL << u32ChannelNum)) + return (-1); + + if (u32ChannelNum < 4UL) + { + (epwm)->EADCPSC0 = ((epwm)->EADCPSC0 & ~((EPWM_EADCPSC0_EADCPSC0_Msk) << (u32ChannelNum << 3))) | \ + (u32Prescale << (u32ChannelNum << 3)); + (epwm)->EADCPSCNT0 = ((epwm)->EADCPSCNT0 & ~((EPWM_EADCPSCNT0_PSCNT0_Msk) << (u32ChannelNum << 3))) | \ + (u32PrescaleCnt << (u32ChannelNum << 3)); + } + else + { + (epwm)->EADCPSC1 = ((epwm)->EADCPSC1 & ~((EPWM_EADCPSC1_EADCPSC4_Msk) << ((u32ChannelNum - 4UL) << 3))) | \ + (u32Prescale << ((u32ChannelNum - 4UL) << 3)); + (epwm)->EADCPSCNT1 = ((epwm)->EADCPSCNT1 & ~((EPWM_EADCPSCNT1_PSCNT4_Msk) << ((u32ChannelNum - 4UL) << 3))) | \ + (u32PrescaleCnt << ((u32ChannelNum - 4UL) << 3)); + } + + (epwm)->EADCPSCCTL |= EPWM_EADCPSCCTL_PSCEN0_Msk << u32ChannelNum; + + return 0; +} + +/** + * @brief Disable Trigger ADC prescale function + * @param[in] epwm The pointer of the specified EPWM module + * - EPWM0 : EPWM Group 0 + * - EPWM1 : EPWM Group 1 + * @param[in] u32ChannelNum EPWM channel number. Valid values are between 0~5 + * @return None + * @details This function is used to disable trigger ADC prescale. + */ +void EPWM_DisableADCTriggerPrescale(EPWM_T *epwm, uint32_t u32ChannelNum) +{ + (epwm)->EADCPSCCTL &= ~(EPWM_EADCPSCCTL_PSCEN0_Msk << u32ChannelNum); +} + +/** + * @brief Clear selected channel trigger ADC flag + * @param[in] epwm The pointer of the specified EPWM module + * - EPWM0 : EPWM Group 0 + * - EPWM1 : EPWM Group 1 + * @param[in] u32ChannelNum EPWM channel number. Valid values are between 0~5 + * @param[in] u32Condition This parameter is not used + * @return None + * @details This function is used to clear selected channel trigger ADC flag. + */ +void EPWM_ClearADCTriggerFlag(EPWM_T *epwm, uint32_t u32ChannelNum, uint32_t u32Condition) +{ + (epwm)->STATUS = (EPWM_STATUS_EADCTRGF0_Msk << u32ChannelNum); +} + +/** + * @brief Get selected channel trigger ADC flag + * @param[in] epwm The pointer of the specified EPWM module + * - EPWM0 : EPWM Group 0 + * - EPWM1 : EPWM Group 1 + * @param[in] u32ChannelNum EPWM channel number. Valid values are between 0~5 + * @retval 0 The specified channel trigger ADC to start of conversion flag is not set + * @retval 1 The specified channel trigger ADC to start of conversion flag is set + * @details This function is used to get EPWM trigger ADC to start of conversion flag for specified channel. + */ +uint32_t EPWM_GetADCTriggerFlag(EPWM_T *epwm, uint32_t u32ChannelNum) +{ + return (((epwm)->STATUS & (EPWM_STATUS_EADCTRGF0_Msk << u32ChannelNum)) ? 1UL : 0UL); +} + +/** + * @brief Enable selected channel to trigger DAC + * @param[in] epwm The pointer of the specified EPWM module + * - EPWM0 : EPWM Group 0 + * - EPWM1 : EPWM Group 1 + * @param[in] u32ChannelNum EPWM channel number. Valid values are between 0~5 + * @param[in] u32Condition The condition to trigger DAC. Combination of following conditions: + * - \ref EPWM_TRIGGER_DAC_ZERO + * - \ref EPWM_TRIGGER_DAC_PERIOD + * - \ref EPWM_TRIGGER_DAC_COMPARE_UP + * - \ref EPWM_TRIGGER_DAC_COMPARE_DOWN + * @return None + * @details This function is used to enable selected channel to trigger DAC. + */ +void EPWM_EnableDACTrigger(EPWM_T *epwm, uint32_t u32ChannelNum, uint32_t u32Condition) +{ + (epwm)->DACTRGEN |= (u32Condition << u32ChannelNum); +} + +/** + * @brief Disable selected channel to trigger DAC + * @param[in] epwm The pointer of the specified EPWM module + * - EPWM0 : EPWM Group 0 + * - EPWM1 : EPWM Group 1 + * @param[in] u32ChannelNum EPWM channel number. Valid values are between 0~5 + * @return None + * @details This function is used to disable selected channel to trigger DAC. + */ +void EPWM_DisableDACTrigger(EPWM_T *epwm, uint32_t u32ChannelNum) +{ + (epwm)->DACTRGEN &= ~((EPWM_TRIGGER_DAC_ZERO | EPWM_TRIGGER_DAC_PERIOD | EPWM_TRIGGER_DAC_COMPARE_UP | \ + EPWM_TRIGGER_DAC_COMPARE_DOWN) << u32ChannelNum); +} + +/** + * @brief This function enable fault brake of selected channel(s) + * @param[in] epwm The pointer of the specified EPWM module + * - EPWM0 : EPWM Group 0 + * - EPWM1 : EPWM Group 1 + * @param[in] u32ChannelMask Combination of enabled channels. Each bit corresponds to a channel. + * @param[in] u32LevelMask Output high or low while fault brake occurs, each bit represent the level of a channel + * while fault brake occurs. Bit 0 represents channel 0, bit 1 represents channel 1... + * @param[in] u32BrakeSource Fault brake source, could be one of following source + * - \ref EPWM_FB_EDGE_ADCRM + * - \ref EPWM_FB_EDGE_ACMP0 + * - \ref EPWM_FB_EDGE_ACMP1 + * - \ref EPWM_FB_EDGE_BKP0 + * - \ref EPWM_FB_EDGE_BKP1 + * - \ref EPWM_FB_EDGE_SYS_CSS + * - \ref EPWM_FB_EDGE_SYS_BOD + * - \ref EPWM_FB_EDGE_SYS_RAM + * - \ref EPWM_FB_EDGE_SYS_COR + * - \ref EPWM_FB_LEVEL_ADCRM + * - \ref EPWM_FB_LEVEL_ACMP0 + * - \ref EPWM_FB_LEVEL_ACMP1 + * - \ref EPWM_FB_LEVEL_BKP0 + * - \ref EPWM_FB_LEVEL_BKP1 + * - \ref EPWM_FB_LEVEL_SYS_CSS + * - \ref EPWM_FB_LEVEL_SYS_BOD + * - \ref EPWM_FB_LEVEL_SYS_RAM + * - \ref EPWM_FB_LEVEL_SYS_COR + * @return None + * @details This function is used to enable fault brake of selected channel(s). + * The write-protection function should be disabled before using this function. + */ +void EPWM_EnableFaultBrake(EPWM_T *epwm, uint32_t u32ChannelMask, uint32_t u32LevelMask, uint32_t u32BrakeSource) +{ + uint32_t i; + + for (i = 0U; i < EPWM_CHANNEL_NUM; i ++) + { + if (u32ChannelMask & (1UL << i)) + { + if ((u32BrakeSource == EPWM_FB_EDGE_SYS_CSS) || (u32BrakeSource == EPWM_FB_EDGE_SYS_BOD) || \ + (u32BrakeSource == EPWM_FB_EDGE_SYS_RAM) || (u32BrakeSource == EPWM_FB_EDGE_SYS_COR) || \ + (u32BrakeSource == EPWM_FB_LEVEL_SYS_CSS) || (u32BrakeSource == EPWM_FB_LEVEL_SYS_BOD) || \ + (u32BrakeSource == EPWM_FB_LEVEL_SYS_RAM) || (u32BrakeSource == EPWM_FB_LEVEL_SYS_COR)) + { + (epwm)->BRKCTL[i >> 1U] |= (u32BrakeSource & (EPWM_BRKCTL0_1_SYSEBEN_Msk | EPWM_BRKCTL0_1_SYSLBEN_Msk)); + (epwm)->FAILBRK |= (u32BrakeSource & 0xFU); + } + else + { + (epwm)->BRKCTL[i >> 1U] |= u32BrakeSource; + } + } + + if (u32LevelMask & (1UL << i)) + { + if ((i & 0x1U) == 0U) + { + /* set brake action as high level for even channel */ + (epwm)->BRKCTL[i >> 1] &= ~EPWM_BRKCTL0_1_BRKAEVEN_Msk; + (epwm)->BRKCTL[i >> 1] |= ((3U) << EPWM_BRKCTL0_1_BRKAEVEN_Pos); + } + else + { + /* set brake action as high level for odd channel */ + (epwm)->BRKCTL[i >> 1] &= ~EPWM_BRKCTL0_1_BRKAODD_Msk; + (epwm)->BRKCTL[i >> 1] |= ((3U) << EPWM_BRKCTL0_1_BRKAODD_Pos); + } + } + else + { + if ((i & 0x1U) == 0U) + { + /* set brake action as low level for even channel */ + (epwm)->BRKCTL[i >> 1U] &= ~EPWM_BRKCTL0_1_BRKAEVEN_Msk; + (epwm)->BRKCTL[i >> 1U] |= ((2U) << EPWM_BRKCTL0_1_BRKAEVEN_Pos); + } + else + { + /* set brake action as low level for odd channel */ + (epwm)->BRKCTL[i >> 1U] &= ~EPWM_BRKCTL0_1_BRKAODD_Msk; + (epwm)->BRKCTL[i >> 1U] |= ((2U) << EPWM_BRKCTL0_1_BRKAODD_Pos); + } + } + } +} + +/** + * @brief Enable capture of selected channel(s) + * @param[in] epwm The pointer of the specified EPWM module + * - EPWM0 : EPWM Group 0 + * - EPWM1 : EPWM Group 1 + * @param[in] u32ChannelMask Combination of enabled channels. Each bit corresponds to a channel. + * Bit 0 is channel 0, bit 1 is channel 1... + * @return None + * @details This function is used to enable capture of selected channel(s). + */ +void EPWM_EnableCapture(EPWM_T *epwm, uint32_t u32ChannelMask) +{ + (epwm)->CAPINEN |= u32ChannelMask; + (epwm)->CAPCTL |= u32ChannelMask; +} + +/** + * @brief Disable capture of selected channel(s) + * @param[in] epwm The pointer of the specified EPWM module + * - EPWM0 : EPWM Group 0 + * - EPWM1 : EPWM Group 1 + * @param[in] u32ChannelMask Combination of enabled channels. Each bit corresponds to a channel. + * Bit 0 is channel 0, bit 1 is channel 1... + * @return None + * @details This function is used to disable capture of selected channel(s). + */ +void EPWM_DisableCapture(EPWM_T *epwm, uint32_t u32ChannelMask) +{ + (epwm)->CAPINEN &= ~u32ChannelMask; + (epwm)->CAPCTL &= ~u32ChannelMask; +} + +/** + * @brief Enables EPWM output generation of selected channel(s) + * @param[in] epwm The pointer of the specified EPWM module + * - EPWM0 : EPWM Group 0 + * - EPWM1 : EPWM Group 1 + * @param[in] u32ChannelMask Combination of enabled channels. Each bit corresponds to a channel. + * Set bit 0 to 1 enables channel 0 output, set bit 1 to 1 enables channel 1 output... + * @return None + * @details This function is used to enable EPWM output generation of selected channel(s). + */ +void EPWM_EnableOutput(EPWM_T *epwm, uint32_t u32ChannelMask) +{ + (epwm)->POEN |= u32ChannelMask; +} + +/** + * @brief Disables EPWM output generation of selected channel(s) + * @param[in] epwm The pointer of the specified EPWM module + * - EPWM0 : EPWM Group 0 + * - EPWM1 : EPWM Group 1 + * @param[in] u32ChannelMask Combination of enabled channels. Each bit corresponds to a channel + * Set bit 0 to 1 disables channel 0 output, set bit 1 to 1 disables channel 1 output... + * @return None + * @details This function is used to disable EPWM output generation of selected channel(s). + */ +void EPWM_DisableOutput(EPWM_T *epwm, uint32_t u32ChannelMask) +{ + (epwm)->POEN &= ~u32ChannelMask; +} + +/** + * @brief Enables PDMA transfer of selected channel for EPWM capture + * @param[in] epwm The pointer of the specified EPWM module + * - EPWM0 : EPWM Group 0 + * - EPWM1 : EPWM Group 1 + * @param[in] u32ChannelNum EPWM channel number. + * @param[in] u32RisingFirst The capture order is rising, falling first. Every two channels share the same setting. Valid values are TRUE and FALSE. + * @param[in] u32Mode Captured data transferred by PDMA interrupt type. It could be either + * - \ref EPWM_CAPTURE_PDMA_RISING_LATCH + * - \ref EPWM_CAPTURE_PDMA_FALLING_LATCH + * - \ref EPWM_CAPTURE_PDMA_RISING_FALLING_LATCH + * @return None + * @details This function is used to enable PDMA transfer of selected channel(s) for EPWM capture. + * @note This function can only selects even or odd channel of pairs to do PDMA transfer. + */ +void EPWM_EnablePDMA(EPWM_T *epwm, uint32_t u32ChannelNum, uint32_t u32RisingFirst, uint32_t u32Mode) +{ + uint32_t u32IsOddCh; + u32IsOddCh = u32ChannelNum & 0x1U; + (epwm)->PDMACTL = ((epwm)->PDMACTL & ~((EPWM_PDMACTL_CHSEL0_1_Msk | EPWM_PDMACTL_CAPORD0_1_Msk | EPWM_PDMACTL_CAPMOD0_1_Msk) << ((u32ChannelNum >> 1U) << 3U))) | \ + (((u32IsOddCh << EPWM_PDMACTL_CHSEL0_1_Pos) | (u32RisingFirst << EPWM_PDMACTL_CAPORD0_1_Pos) | \ + u32Mode | EPWM_PDMACTL_CHEN0_1_Msk) << ((u32ChannelNum >> 1U) << 3U)); +} + +/** + * @brief Disables PDMA transfer of selected channel for EPWM capture + * @param[in] epwm The pointer of the specified EPWM module + * - EPWM0 : EPWM Group 0 + * - EPWM1 : EPWM Group 1 + * @param[in] u32ChannelNum EPWM channel number. + * @return None + * @details This function is used to enable PDMA transfer of selected channel(s) for EPWM capture. + */ +void EPWM_DisablePDMA(EPWM_T *epwm, uint32_t u32ChannelNum) +{ + (epwm)->PDMACTL &= ~(EPWM_PDMACTL_CHEN0_1_Msk << ((u32ChannelNum >> 1U) << 3U)); +} + +/** + * @brief Enable Dead zone of selected channel + * @param[in] epwm The pointer of the specified EPWM module + * - EPWM0 : EPWM Group 0 + * - EPWM1 : EPWM Group 1 + * @param[in] u32ChannelNum EPWM channel number. Valid values are between 0~5 + * @param[in] u32Duration Dead zone length in EPWM clock count, valid values are between 0~0xFFF, but 0 means there is no Dead zone. + * @return None + * @details This function is used to enable Dead zone of selected channel. + * The write-protection function should be disabled before using this function. + * @note Every two channels share the same setting. + */ +void EPWM_EnableDeadZone(EPWM_T *epwm, uint32_t u32ChannelNum, uint32_t u32Duration) +{ + /* every two channels share the same setting */ + (epwm)->DTCTL[(u32ChannelNum) >> 1U] &= ~EPWM_DTCTL0_1_DTCNT_Msk; + (epwm)->DTCTL[(u32ChannelNum) >> 1U] |= EPWM_DTCTL0_1_DTEN_Msk | u32Duration; +} + +/** + * @brief Disable Dead zone of selected channel + * @param[in] epwm The pointer of the specified EPWM module + * - EPWM0 : EPWM Group 0 + * - EPWM1 : EPWM Group 1 + * @param[in] u32ChannelNum EPWM channel number. Valid values are between 0~5 + * @return None + * @details This function is used to disable Dead zone of selected channel. + * The write-protection function should be disabled before using this function. + */ +void EPWM_DisableDeadZone(EPWM_T *epwm, uint32_t u32ChannelNum) +{ + /* every two channels shares the same setting */ + (epwm)->DTCTL[(u32ChannelNum) >> 1U] &= ~EPWM_DTCTL0_1_DTEN_Msk; +} + +/** + * @brief Enable capture interrupt of selected channel. + * @param[in] epwm The pointer of the specified EPWM module + * - EPWM0 : EPWM Group 0 + * - EPWM1 : EPWM Group 1 + * @param[in] u32ChannelNum EPWM channel number. Valid values are between 0~5 + * @param[in] u32Edge Rising or falling edge to latch counter. + * - \ref EPWM_CAPTURE_INT_RISING_LATCH + * - \ref EPWM_CAPTURE_INT_FALLING_LATCH + * @return None + * @details This function is used to enable capture interrupt of selected channel. + */ +void EPWM_EnableCaptureInt(EPWM_T *epwm, uint32_t u32ChannelNum, uint32_t u32Edge) +{ + (epwm)->CAPIEN |= (u32Edge << u32ChannelNum); +} + +/** + * @brief Disable capture interrupt of selected channel. + * @param[in] epwm The pointer of the specified EPWM module + * - EPWM0 : EPWM Group 0 + * - EPWM1 : EPWM Group 1 + * @param[in] u32ChannelNum EPWM channel number. Valid values are between 0~5 + * @param[in] u32Edge Rising or falling edge to latch counter. + * - \ref EPWM_CAPTURE_INT_RISING_LATCH + * - \ref EPWM_CAPTURE_INT_FALLING_LATCH + * @return None + * @details This function is used to disable capture interrupt of selected channel. + */ +void EPWM_DisableCaptureInt(EPWM_T *epwm, uint32_t u32ChannelNum, uint32_t u32Edge) +{ + (epwm)->CAPIEN &= ~(u32Edge << u32ChannelNum); +} + +/** + * @brief Clear capture interrupt of selected channel. + * @param[in] epwm The pointer of the specified EPWM module + * - EPWM0 : EPWM Group 0 + * - EPWM1 : EPWM Group 1 + * @param[in] u32ChannelNum EPWM channel number. Valid values are between 0~5 + * @param[in] u32Edge Rising or falling edge to latch counter. + * - \ref EPWM_CAPTURE_INT_RISING_LATCH + * - \ref EPWM_CAPTURE_INT_FALLING_LATCH + * @return None + * @details This function is used to clear capture interrupt of selected channel. + */ +void EPWM_ClearCaptureIntFlag(EPWM_T *epwm, uint32_t u32ChannelNum, uint32_t u32Edge) +{ + (epwm)->CAPIF = (u32Edge << u32ChannelNum); +} + +/** + * @brief Get capture interrupt of selected channel. + * @param[in] epwm The pointer of the specified EPWM module + * - EPWM0 : EPWM Group 0 + * - EPWM1 : EPWM Group 1 + * @param[in] u32ChannelNum EPWM channel number. Valid values are between 0~5 + * @retval 0 No capture interrupt + * @retval 1 Rising edge latch interrupt + * @retval 2 Falling edge latch interrupt + * @retval 3 Rising and falling latch interrupt + * @details This function is used to get capture interrupt of selected channel. + */ +uint32_t EPWM_GetCaptureIntFlag(EPWM_T *epwm, uint32_t u32ChannelNum) +{ + return (((((epwm)->CAPIF & (EPWM_CAPIF_CFLIF0_Msk << u32ChannelNum)) ? 1UL : 0UL) << 1) | \ + (((epwm)->CAPIF & (EPWM_CAPIF_CRLIF0_Msk << u32ChannelNum)) ? 1UL : 0UL)); +} +/** + * @brief Enable duty interrupt of selected channel + * @param[in] epwm The pointer of the specified EPWM module + * - EPWM0 : EPWM Group 0 + * - EPWM1 : EPWM Group 1 + * @param[in] u32ChannelNum EPWM channel number. Valid values are between 0~5 + * @param[in] u32IntDutyType Duty interrupt type, could be either + * - \ref EPWM_DUTY_INT_DOWN_COUNT_MATCH_CMP + * - \ref EPWM_DUTY_INT_UP_COUNT_MATCH_CMP + * @return None + * @details This function is used to enable duty interrupt of selected channel. + */ +void EPWM_EnableDutyInt(EPWM_T *epwm, uint32_t u32ChannelNum, uint32_t u32IntDutyType) +{ + (epwm)->INTEN0 |= (u32IntDutyType << u32ChannelNum); +} + +/** + * @brief Disable duty interrupt of selected channel + * @param[in] epwm The pointer of the specified EPWM module + * - EPWM0 : EPWM Group 0 + * - EPWM1 : EPWM Group 1 + * @param[in] u32ChannelNum EPWM channel number. Valid values are between 0~5 + * @return None + * @details This function is used to disable duty interrupt of selected channel. + */ +void EPWM_DisableDutyInt(EPWM_T *epwm, uint32_t u32ChannelNum) +{ + (epwm)->INTEN0 &= ~((uint32_t)(EPWM_DUTY_INT_DOWN_COUNT_MATCH_CMP | EPWM_DUTY_INT_UP_COUNT_MATCH_CMP) << u32ChannelNum); +} + +/** + * @brief Clear duty interrupt flag of selected channel + * @param[in] epwm The pointer of the specified EPWM module + * - EPWM0 : EPWM Group 0 + * - EPWM1 : EPWM Group 1 + * @param[in] u32ChannelNum EPWM channel number. Valid values are between 0~5 + * @return None + * @details This function is used to clear duty interrupt flag of selected channel. + */ +void EPWM_ClearDutyIntFlag(EPWM_T *epwm, uint32_t u32ChannelNum) +{ + (epwm)->INTSTS0 = (EPWM_INTSTS0_CMPUIF0_Msk | EPWM_INTSTS0_CMPDIF0_Msk) << u32ChannelNum; +} + +/** + * @brief Get duty interrupt flag of selected channel + * @param[in] epwm The pointer of the specified EPWM module + * - EPWM0 : EPWM Group 0 + * - EPWM1 : EPWM Group 1 + * @param[in] u32ChannelNum EPWM channel number. Valid values are between 0~5 + * @return Duty interrupt flag of specified channel + * @retval 0 Duty interrupt did not occur + * @retval 1 Duty interrupt occurred + * @details This function is used to get duty interrupt flag of selected channel. + */ +uint32_t EPWM_GetDutyIntFlag(EPWM_T *epwm, uint32_t u32ChannelNum) +{ + return ((((epwm)->INTSTS0 & ((EPWM_INTSTS0_CMPDIF0_Msk | EPWM_INTSTS0_CMPUIF0_Msk) << u32ChannelNum))) ? 1UL : 0UL); +} + +/** + * @brief This function enable fault brake interrupt + * @param[in] epwm The pointer of the specified EPWM module + * @param[in] u32BrakeSource Fault brake source. + * - \ref EPWM_FB_EDGE + * - \ref EPWM_FB_LEVEL + * @return None + * @details This function is used to enable fault brake interrupt. + * The write-protection function should be disabled before using this function. + * @note Every two channels share the same setting. + */ +void EPWM_EnableFaultBrakeInt(EPWM_T *epwm, uint32_t u32BrakeSource) +{ + (epwm)->INTEN1 |= (0x7UL << u32BrakeSource); +} + +/** + * @brief This function disable fault brake interrupt + * @param[in] epwm The pointer of the specified EPWM module + * @param[in] u32BrakeSource Fault brake source. + * - \ref EPWM_FB_EDGE + * - \ref EPWM_FB_LEVEL + * @return None + * @details This function is used to disable fault brake interrupt. + * The write-protection function should be disabled before using this function. + * @note Every two channels share the same setting. + */ +void EPWM_DisableFaultBrakeInt(EPWM_T *epwm, uint32_t u32BrakeSource) +{ + (epwm)->INTEN1 &= ~(0x7UL << u32BrakeSource); +} + +/** + * @brief This function clear fault brake interrupt of selected source + * @param[in] epwm The pointer of the specified EPWM module + * @param[in] u32BrakeSource Fault brake source. + * - \ref EPWM_FB_EDGE + * - \ref EPWM_FB_LEVEL + * @return None + * @details This function is used to clear fault brake interrupt of selected source. + * The write-protection function should be disabled before using this function. + */ +void EPWM_ClearFaultBrakeIntFlag(EPWM_T *epwm, uint32_t u32BrakeSource) +{ + (epwm)->INTSTS1 = (0x3fUL << u32BrakeSource); +} + +/** + * @brief This function get fault brake interrupt flag of selected source + * @param[in] epwm The pointer of the specified EPWM module + * @param[in] u32BrakeSource Fault brake source, could be either + * - \ref EPWM_FB_EDGE + * - \ref EPWM_FB_LEVEL + * @return Fault brake interrupt flag of specified source + * @retval 0 Fault brake interrupt did not occurred + * @retval 1 Fault brake interrupt occurred + * @details This function is used to get fault brake interrupt flag of selected source. + */ +uint32_t EPWM_GetFaultBrakeIntFlag(EPWM_T *epwm, uint32_t u32BrakeSource) +{ + return (((epwm)->INTSTS1 & (0x3fUL << u32BrakeSource)) ? 1UL : 0UL); +} + +/** + * @brief Enable period interrupt of selected channel + * @param[in] epwm The pointer of the specified EPWM module + * - EPWM0 : EPWM Group 0 + * - EPWM1 : EPWM Group 1 + * @param[in] u32ChannelNum EPWM channel number. Valid values are between 0~5 + * @param[in] u32IntPeriodType Period interrupt type. This parameter is not used. + * @return None + * @details This function is used to enable period interrupt of selected channel. + */ +void EPWM_EnablePeriodInt(EPWM_T *epwm, uint32_t u32ChannelNum, uint32_t u32IntPeriodType) +{ + (epwm)->INTEN0 |= ((1UL << EPWM_INTEN0_PIEN0_Pos) << u32ChannelNum); +} + +/** + * @brief Disable period interrupt of selected channel + * @param[in] epwm The pointer of the specified EPWM module + * - EPWM0 : EPWM Group 0 + * - EPWM1 : EPWM Group 1 + * @param[in] u32ChannelNum EPWM channel number. Valid values are between 0~5 + * @return None + * @details This function is used to disable period interrupt of selected channel. + */ +void EPWM_DisablePeriodInt(EPWM_T *epwm, uint32_t u32ChannelNum) +{ + (epwm)->INTEN0 &= ~((1UL << EPWM_INTEN0_PIEN0_Pos) << u32ChannelNum); +} + +/** + * @brief Clear period interrupt of selected channel + * @param[in] epwm The pointer of the specified EPWM module + * - EPWM0 : EPWM Group 0 + * - EPWM1 : EPWM Group 1 + * @param[in] u32ChannelNum EPWM channel number. Valid values are between 0~5 + * @return None + * @details This function is used to clear period interrupt of selected channel. + */ +void EPWM_ClearPeriodIntFlag(EPWM_T *epwm, uint32_t u32ChannelNum) +{ + (epwm)->INTSTS0 = ((1UL << EPWM_INTSTS0_PIF0_Pos) << u32ChannelNum); +} + +/** + * @brief Get period interrupt of selected channel + * @param[in] epwm The pointer of the specified EPWM module + * - EPWM0 : EPWM Group 0 + * - EPWM1 : EPWM Group 1 + * @param[in] u32ChannelNum EPWM channel number. Valid values are between 0~5 + * @return Period interrupt flag of specified channel + * @retval 0 Period interrupt did not occur + * @retval 1 Period interrupt occurred + * @details This function is used to get period interrupt of selected channel. + */ +uint32_t EPWM_GetPeriodIntFlag(EPWM_T *epwm, uint32_t u32ChannelNum) +{ + return ((((epwm)->INTSTS0 & ((1UL << EPWM_INTSTS0_PIF0_Pos) << u32ChannelNum))) ? 1UL : 0UL); +} + +/** + * @brief Enable zero interrupt of selected channel + * @param[in] epwm The pointer of the specified EPWM module + * - EPWM0 : EPWM Group 0 + * - EPWM1 : EPWM Group 1 + * @param[in] u32ChannelNum EPWM channel number. Valid values are between 0~5 + * @return None + * @details This function is used to enable zero interrupt of selected channel. + */ +void EPWM_EnableZeroInt(EPWM_T *epwm, uint32_t u32ChannelNum) +{ + (epwm)->INTEN0 |= ((1UL << EPWM_INTEN0_ZIEN0_Pos) << u32ChannelNum); +} + +/** + * @brief Disable zero interrupt of selected channel + * @param[in] epwm The pointer of the specified EPWM module + * - EPWM0 : EPWM Group 0 + * - EPWM1 : EPWM Group 1 + * @param[in] u32ChannelNum EPWM channel number. Valid values are between 0~5 + * @return None + * @details This function is used to disable zero interrupt of selected channel. + */ +void EPWM_DisableZeroInt(EPWM_T *epwm, uint32_t u32ChannelNum) +{ + (epwm)->INTEN0 &= ~((1UL << EPWM_INTEN0_ZIEN0_Pos) << u32ChannelNum); +} + +/** + * @brief Clear zero interrupt of selected channel + * @param[in] epwm The pointer of the specified EPWM module + * - EPWM0 : EPWM Group 0 + * - EPWM1 : EPWM Group 1 + * @param[in] u32ChannelNum EPWM channel number. Valid values are between 0~5 + * @return None + * @details This function is used to clear zero interrupt of selected channel. + */ +void EPWM_ClearZeroIntFlag(EPWM_T *epwm, uint32_t u32ChannelNum) +{ + (epwm)->INTSTS0 = ((1UL << EPWM_INTEN0_ZIEN0_Pos) << u32ChannelNum); +} + +/** + * @brief Get zero interrupt of selected channel + * @param[in] epwm The pointer of the specified EPWM module + * - EPWM0 : EPWM Group 0 + * - EPWM1 : EPWM Group 1 + * @param[in] u32ChannelNum EPWM channel number. Valid values are between 0~5 + * @return Zero interrupt flag of specified channel + * @retval 0 Zero interrupt did not occur + * @retval 1 Zero interrupt occurred + * @details This function is used to get zero interrupt of selected channel. + */ +uint32_t EPWM_GetZeroIntFlag(EPWM_T *epwm, uint32_t u32ChannelNum) +{ + return ((((epwm)->INTSTS0 & ((1UL << EPWM_INTEN0_ZIEN0_Pos) << u32ChannelNum))) ? 1UL : 0UL); +} + +/** + * @brief Enable interrupt flag accumulator of selected channel + * @param[in] epwm The pointer of the specified EPWM module + * - EPWM0 : EPWM Group 0 + * - EPWM1 : EPWM Group 1 + * @param[in] u32ChannelNum EPWM channel number. Valid values are between 0~5 + * @param[in] u32IntFlagCnt Interrupt flag counter. Valid values are between 0~65535. + * @param[in] u32IntAccSrc Interrupt flag accumulator source selection. + * - \ref EPWM_IFA_ZERO_POINT + * - \ref EPWM_IFA_PERIOD_POINT + * - \ref EPWM_IFA_COMPARE_UP_COUNT_POINT + * - \ref EPWM_IFA_COMPARE_DOWN_COUNT_POINT + * @return None + * @details This function is used to enable interrupt flag accumulator of selected channel. + */ +void EPWM_EnableAcc(EPWM_T *epwm, uint32_t u32ChannelNum, uint32_t u32IntFlagCnt, uint32_t u32IntAccSrc) +{ + (epwm)->IFA[u32ChannelNum] = (((epwm)->IFA[u32ChannelNum] & ~((EPWM_IFA0_IFACNT_Msk | EPWM_IFA0_IFASEL_Msk))) | \ + (EPWM_IFA0_IFAEN_Msk | (u32IntAccSrc << EPWM_IFA0_IFASEL_Pos) | u32IntFlagCnt)); +} + +/** + * @brief Disable interrupt flag accumulator of selected channel + * @param[in] epwm The pointer of the specified EPWM module + * - EPWM0 : EPWM Group 0 + * - EPWM1 : EPWM Group 1 + * @param[in] u32ChannelNum EPWM channel number. Valid values are between 0~5 + * @return None + * @details This function is used to Disable interrupt flag accumulator of selected channel. + */ +void EPWM_DisableAcc(EPWM_T *epwm, uint32_t u32ChannelNum) +{ + (epwm)->IFA[u32ChannelNum] = ((epwm)->IFA[u32ChannelNum] & ~(EPWM_IFA0_IFAEN_Msk)); +} + +/** + * @brief Enable interrupt flag accumulator interrupt of selected channel + * @param[in] epwm The pointer of the specified EPWM module + * - EPWM0 : EPWM Group 0 + * - EPWM1 : EPWM Group 1 + * @param[in] u32ChannelNum EPWM channel number. Valid values are between 0~5 + * @return None + * @details This function is used to enable interrupt flag accumulator interrupt of selected channel. + */ +void EPWM_EnableAccInt(EPWM_T *epwm, uint32_t u32ChannelNum) +{ + (epwm)->AINTEN |= (1UL << (u32ChannelNum)); +} + +/** + * @brief Disable interrupt flag accumulator interrupt of selected channel + * @param[in] epwm The pointer of the specified EPWM module + * - EPWM0 : EPWM Group 0 + * - EPWM1 : EPWM Group 1 + * @param[in] u32ChannelNum EPWM channel number. Valid values are between 0~5 + * @return None + * @details This function is used to disable interrupt flag accumulator interrupt of selected channel. + */ +void EPWM_DisableAccInt(EPWM_T *epwm, uint32_t u32ChannelNum) +{ + (epwm)->AINTEN &= ~(1UL << (u32ChannelNum)); +} + +/** + * @brief Clear interrupt flag accumulator interrupt of selected channel + * @param[in] epwm The pointer of the specified EPWM module + * - EPWM0 : EPWM Group 0 + * - EPWM1 : EPWM Group 1 + * @param[in] u32ChannelNum EPWM channel number. Valid values are between 0~5 + * @return None + * @details This function is used to clear interrupt flag accumulator interrupt of selected channel. + */ +void EPWM_ClearAccInt(EPWM_T *epwm, uint32_t u32ChannelNum) +{ + (epwm)->AINTSTS = (1UL << (u32ChannelNum)); +} + +/** + * @brief Get interrupt flag accumulator interrupt of selected channel + * @param[in] epwm The pointer of the specified EPWM module + * - EPWM0 : EPWM Group 0 + * - EPWM1 : EPWM Group 1 + * @param[in] u32ChannelNum EPWM channel number. Valid values are between 0~5 + * @retval 0 Accumulator interrupt did not occur + * @retval 1 Accumulator interrupt occurred + * @details This function is used to Get interrupt flag accumulator interrupt of selected channel. + */ +uint32_t EPWM_GetAccInt(EPWM_T *epwm, uint32_t u32ChannelNum) +{ + return (((epwm)->AINTSTS & (1UL << (u32ChannelNum))) ? 1UL : 0UL); +} + +/** + * @brief Enable accumulator PDMA of selected channel + * @param[in] epwm The pointer of the specified EPWM module + * - EPWM0 : EPWM Group 0 + * - EPWM1 : EPWM Group 1 + * @param[in] u32ChannelNum EPWM channel number. Valid values are between 0~5 + * @return None + * @details This function is used to enable accumulator interrupt trigger PDMA of selected channel. + */ +void EPWM_EnableAccPDMA(EPWM_T *epwm, uint32_t u32ChannelNum) +{ + (epwm)->APDMACTL |= (1UL << (u32ChannelNum)); +} + +/** + * @brief Disable accumulator PDMA of selected channel + * @param[in] epwm The pointer of the specified EPWM module + * - EPWM0 : EPWM Group 0 + * - EPWM1 : EPWM Group 1 + * @param[in] u32ChannelNum EPWM channel number. Valid values are between 0~5 + * @return None + * @details This function is used to disable accumulator interrupt trigger PDMA of selected channel. + */ +void EPWM_DisableAccPDMA(EPWM_T *epwm, uint32_t u32ChannelNum) +{ + (epwm)->APDMACTL &= ~(1UL << (u32ChannelNum)); +} + +/** + * @brief Enable interrupt flag accumulator stop mode of selected channel + * @param[in] epwm The pointer of the specified EPWM module + * - EPWM0 : EPWM Group 0 + * - EPWM1 : EPWM Group 1 + * @param[in] u32ChannelNum EPWM channel number. Valid values are between 0~5 + * @return None + * @details This function is used to enable interrupt flag accumulator stop mode of selected channel. + */ +void EPWM_EnableAccStopMode(EPWM_T *epwm, uint32_t u32ChannelNum) +{ + (epwm)->IFA[u32ChannelNum] |= EPWM_IFA0_STPMOD_Msk; +} + +/** + * @brief Disable interrupt flag accumulator stop mode of selected channel + * @param[in] epwm The pointer of the specified EPWM module + * - EPWM0 : EPWM Group 0 + * - EPWM1 : EPWM Group 1 + * @param[in] u32ChannelNum EPWM channel number. Valid values are between 0~5 + * @return None + * @details This function is used to disable interrupt flag accumulator stop mode of selected channel. + */ +void EPWM_DisableAccStopMode(EPWM_T *epwm, uint32_t u32ChannelNum) +{ + (epwm)->IFA[u32ChannelNum] &= ~EPWM_IFA0_STPMOD_Msk; +} + +/** + * @brief Clear free trigger duty interrupt flag of selected channel + * @param[in] epwm The pointer of the specified EPWM module + * - EPWM0 : EPWM Group 0 + * - EPWM1 : EPWM Group 1 + * @param[in] u32ChannelNum EPWM channel number. Valid values are between 0~5 + * @return None + * @details This function is used to clear free trigger duty interrupt flag of selected channel. + */ +void EPWM_ClearFTDutyIntFlag(EPWM_T *epwm, uint32_t u32ChannelNum) +{ + (epwm)->FTCI = ((EPWM_FTCI_FTCMU0_Msk | EPWM_FTCI_FTCMD0_Msk) << (u32ChannelNum >> 1U)); +} + +/** + * @brief Get free trigger duty interrupt flag of selected channel + * @param[in] epwm The pointer of the specified EPWM module + * - EPWM0 : EPWM Group 0 + * - EPWM1 : EPWM Group 1 + * @param[in] u32ChannelNum EPWM channel number. Valid values are between 0~5 + * @return Duty interrupt flag of specified channel + * @retval 0 Free trigger duty interrupt did not occur + * @retval 1 Free trigger duty interrupt occurred + * @details This function is used to get free trigger duty interrupt flag of selected channel. + */ +uint32_t EPWM_GetFTDutyIntFlag(EPWM_T *epwm, uint32_t u32ChannelNum) +{ + return (((epwm)->FTCI & ((EPWM_FTCI_FTCMU0_Msk | EPWM_FTCI_FTCMD0_Msk) << (u32ChannelNum >> 1U))) ? 1UL : 0UL); +} + +/** + * @brief Enable load mode of selected channel + * @param[in] epwm The pointer of the specified EPWM module + * - EPWM0 : EPWM Group 0 + * - EPWM1 : EPWM Group 1 + * @param[in] u32ChannelNum EPWM channel number. Valid values are between 0~5 + * @param[in] u32LoadMode EPWM counter loading mode. + * - \ref EPWM_LOAD_MODE_IMMEDIATE + * - \ref EPWM_LOAD_MODE_WINDOW + * - \ref EPWM_LOAD_MODE_CENTER + * @return None + * @details This function is used to enable load mode of selected channel. + */ +void EPWM_EnableLoadMode(EPWM_T *epwm, uint32_t u32ChannelNum, uint32_t u32LoadMode) +{ + (epwm)->CTL0 |= (u32LoadMode << u32ChannelNum); +} + +/** + * @brief Disable load mode of selected channel + * @param[in] epwm The pointer of the specified EPWM module + * - EPWM0 : EPWM Group 0 + * - EPWM1 : EPWM Group 1 + * @param[in] u32ChannelNum EPWM channel number. Valid values are between 0~5 + * @param[in] u32LoadMode EPWM counter loading mode. + * - \ref EPWM_LOAD_MODE_IMMEDIATE + * - \ref EPWM_LOAD_MODE_WINDOW + * - \ref EPWM_LOAD_MODE_CENTER + * @return None + * @details This function is used to disable load mode of selected channel. + */ +void EPWM_DisableLoadMode(EPWM_T *epwm, uint32_t u32ChannelNum, uint32_t u32LoadMode) +{ + (epwm)->CTL0 &= ~(u32LoadMode << u32ChannelNum); +} + +/** + * @brief Configure synchronization phase of selected channel + * @param[in] epwm The pointer of the specified EPWM module + * - EPWM0 : EPWM Group 0 + * - EPWM1 : EPWM Group 1 + * @param[in] u32ChannelNum EPWM channel number. Valid values are between 0~5 + * @param[in] u32SyncSrc EPWM synchronize source selection. + * - \ref EPWM_SYNC_OUT_FROM_SYNCIN_SWSYNC + * - \ref EPWM_SYNC_OUT_FROM_COUNT_TO_ZERO + * - \ref EPWM_SYNC_OUT_FROM_COUNT_TO_COMPARATOR + * - \ref EPWM_SYNC_OUT_DISABLE + * @param[in] u32Direction Phase direction. Control EPWM counter count decrement or increment after synchronizing. + * - \ref EPWM_PHS_DIR_DECREMENT + * - \ref EPWM_PHS_DIR_INCREMENT + * @param[in] u32StartPhase Synchronous start phase value. Valid values are between 0~65535. + * @return None + * @details This function is used to configure synchronization phase of selected channel. + * @note Every two channels share the same setting. + */ +void EPWM_ConfigSyncPhase(EPWM_T *epwm, uint32_t u32ChannelNum, uint32_t u32SyncSrc, uint32_t u32Direction, uint32_t u32StartPhase) +{ + /* every two channels shares the same setting */ + u32ChannelNum >>= 1U; + (epwm)->SYNC = (((epwm)->SYNC & ~(((3UL << EPWM_SYNC_SINSRC0_Pos) << (u32ChannelNum << 1U)) | ((1UL << EPWM_SYNC_PHSDIR0_Pos) << u32ChannelNum))) | \ + (u32Direction << EPWM_SYNC_PHSDIR0_Pos << u32ChannelNum) | ((u32SyncSrc << EPWM_SYNC_SINSRC0_Pos) << (u32ChannelNum << 1U))); + (epwm)->PHS[(u32ChannelNum)] = u32StartPhase; +} + + +/** + * @brief Enable SYNC phase of selected channel(s) + * @param[in] epwm The pointer of the specified EPWM module + * - EPWM0 : EPWM Group 0 + * - EPWM1 : EPWM Group 1 + * @param[in] u32ChannelMask Combination of enabled channels. Each bit corresponds to a channel. + * Bit 0 is channel 0, bit 1 is channel 1... + * @return None + * @details This function is used to enable SYNC phase of selected channel(s). + * @note Every two channels share the same setting. + */ +void EPWM_EnableSyncPhase(EPWM_T *epwm, uint32_t u32ChannelMask) +{ + uint32_t i; + for (i = 0U; i < EPWM_CHANNEL_NUM; i ++) + { + if (u32ChannelMask & (1UL << i)) + { + (epwm)->SYNC |= ((1UL << EPWM_SYNC_PHSEN0_Pos) << (i >> 1U)); + } + } +} + +/** + * @brief Disable SYNC phase of selected channel(s) + * @param[in] epwm The pointer of the specified EPWM module + * - EPWM0 : EPWM Group 0 + * - EPWM1 : EPWM Group 1 + * @param[in] u32ChannelMask Combination of enabled channels. Each bit corresponds to a channel. + * Bit 0 is channel 0, bit 1 is channel 1... + * @return None + * @details This function is used to disable SYNC phase of selected channel(s). + * @note Every two channels share the same setting. + */ +void EPWM_DisableSyncPhase(EPWM_T *epwm, uint32_t u32ChannelMask) +{ + uint32_t i; + for (i = 0U; i < EPWM_CHANNEL_NUM; i ++) + { + if (u32ChannelMask & (1UL << i)) + { + (epwm)->SYNC &= ~((1UL << EPWM_SYNC_PHSEN0_Pos) << (i >> 1U)); + } + } +} + +/** + * @brief Enable EPWM SYNC_IN noise filter function + * @param[in] epwm The pointer of the specified EPWM module + * - EPWM0 : EPWM Group 0 + * - EPWM1 : EPWM Group 1 + * @param[in] u32ClkCnt SYNC Edge Detector Filter Count. This controls the counter number of edge detector. + * The valid value is 0~7. + * @param[in] u32ClkDivSel SYNC Edge Detector Filter Clock Selection. + * - \ref EPWM_NF_CLK_DIV_1 + * - \ref EPWM_NF_CLK_DIV_2 + * - \ref EPWM_NF_CLK_DIV_4 + * - \ref EPWM_NF_CLK_DIV_8 + * - \ref EPWM_NF_CLK_DIV_16 + * - \ref EPWM_NF_CLK_DIV_32 + * - \ref EPWM_NF_CLK_DIV_64 + * - \ref EPWM_NF_CLK_DIV_128 + * @return None + * @details This function is used to enable EPWM SYNC_IN noise filter function. + */ +void EPWM_EnableSyncNoiseFilter(EPWM_T *epwm, uint32_t u32ClkCnt, uint32_t u32ClkDivSel) +{ + (epwm)->SYNC = ((epwm)->SYNC & ~(EPWM_SYNC_SFLTCNT_Msk | EPWM_SYNC_SFLTCSEL_Msk)) | \ + ((u32ClkCnt << EPWM_SYNC_SFLTCNT_Pos) | (u32ClkDivSel << EPWM_SYNC_SFLTCSEL_Pos) | EPWM_SYNC_SNFLTEN_Msk); +} + +/** + * @brief Disable EPWM SYNC_IN noise filter function + * @param[in] epwm The pointer of the specified EPWM module + * - EPWM0 : EPWM Group 0 + * - EPWM1 : EPWM Group 1 + * @return None + * @details This function is used to Disable EPWM SYNC_IN noise filter function. + */ +void EPWM_DisableSyncNoiseFilter(EPWM_T *epwm) +{ + (epwm)->SYNC &= ~EPWM_SYNC_SNFLTEN_Msk; +} + +/** + * @brief Enable EPWM SYNC input pin inverse function + * @param[in] epwm The pointer of the specified EPWM module + * - EPWM0 : EPWM Group 0 + * - EPWM1 : EPWM Group 1 + * @return None + * @details This function is used to enable EPWM SYNC input pin inverse function. + */ +void EPWM_EnableSyncPinInverse(EPWM_T *epwm) +{ + (epwm)->SYNC |= EPWM_SYNC_SINPINV_Msk; +} + +/** + * @brief Disable EPWM SYNC input pin inverse function + * @param[in] epwm The pointer of the specified EPWM module + * - EPWM0 : EPWM Group 0 + * - EPWM1 : EPWM Group 1 + * @return None + * @details This function is used to Disable EPWM SYNC input pin inverse function. + */ +void EPWM_DisableSyncPinInverse(EPWM_T *epwm) +{ + (epwm)->SYNC &= (~EPWM_SYNC_SINPINV_Msk); +} + +/** + * @brief Set EPWM clock source + * @param[in] epwm The pointer of the specified EPWM module + * - EPWM0 : EPWM Group 0 + * - EPWM1 : EPWM Group 1 + * @param[in] u32ChannelNum EPWM channel number. Valid values are between 0~5 + * @param[in] u32ClkSrcSel EPWM external clock source. + * - \ref EPWM_CLKSRC_EPWM_CLK + * - \ref EPWM_CLKSRC_TIMER0 + * - \ref EPWM_CLKSRC_TIMER1 + * - \ref EPWM_CLKSRC_TIMER2 + * - \ref EPWM_CLKSRC_TIMER3 + * @return None + * @details This function is used to set EPWM clock source. + * @note Every two channels share the same setting. + * @note If the clock source of EPWM counter is selected from TIMERn interrupt events, the TRGEPWM(TIMERn_TRGCTL[1], n=0,1..3) bit must be set as 1. + */ +void EPWM_SetClockSource(EPWM_T *epwm, uint32_t u32ChannelNum, uint32_t u32ClkSrcSel) +{ + (epwm)->CLKSRC = ((epwm)->CLKSRC & ~(EPWM_CLKSRC_ECLKSRC0_Msk << ((u32ChannelNum >> 1U) << 3U))) | \ + (u32ClkSrcSel << ((u32ChannelNum >> 1U) << 3U)); +} + +/** + * @brief Enable EPWM brake noise filter function + * @param[in] epwm The pointer of the specified EPWM module + * - EPWM0 : EPWM Group 0 + * - EPWM1 : EPWM Group 1 + * @param[in] u32BrakePinNum Brake pin selection. Valid values are 0 or 1. + * @param[in] u32ClkCnt SYNC Edge Detector Filter Count. This controls the counter number of edge detector + * @param[in] u32ClkDivSel SYNC Edge Detector Filter Clock Selection. + * - \ref EPWM_NF_CLK_DIV_1 + * - \ref EPWM_NF_CLK_DIV_2 + * - \ref EPWM_NF_CLK_DIV_4 + * - \ref EPWM_NF_CLK_DIV_8 + * - \ref EPWM_NF_CLK_DIV_16 + * - \ref EPWM_NF_CLK_DIV_32 + * - \ref EPWM_NF_CLK_DIV_64 + * - \ref EPWM_NF_CLK_DIV_128 + * @return None + * @details This function is used to enable EPWM brake noise filter function. + */ +void EPWM_EnableBrakeNoiseFilter(EPWM_T *epwm, uint32_t u32BrakePinNum, uint32_t u32ClkCnt, uint32_t u32ClkDivSel) +{ + (epwm)->BNF = ((epwm)->BNF & ~((EPWM_BNF_BRK0FCNT_Msk | EPWM_BNF_BRK0NFSEL_Msk) << (u32BrakePinNum << 3U))) | \ + (((u32ClkCnt << EPWM_BNF_BRK0FCNT_Pos) | (u32ClkDivSel << EPWM_BNF_BRK0NFSEL_Pos) | EPWM_BNF_BRK0NFEN_Msk) << (u32BrakePinNum << 3U)); +} + +/** + * @brief Disable EPWM brake noise filter function + * @param[in] epwm The pointer of the specified EPWM module + * - EPWM0 : EPWM Group 0 + * - EPWM1 : EPWM Group 1 + * @param[in] u32BrakePinNum Brake pin selection. Valid values are 0 or 1. + * @return None + * @details This function is used to disable EPWM brake noise filter function. + */ +void EPWM_DisableBrakeNoiseFilter(EPWM_T *epwm, uint32_t u32BrakePinNum) +{ + (epwm)->BNF &= ~(EPWM_BNF_BRK0NFEN_Msk << (u32BrakePinNum << 3U)); +} + +/** + * @brief Enable EPWM brake pin inverse function + * @param[in] epwm The pointer of the specified EPWM module + * - EPWM0 : EPWM Group 0 + * - EPWM1 : EPWM Group 1 + * @param[in] u32BrakePinNum Brake pin selection. Valid values are 0 or 1. + * @return None + * @details This function is used to enable EPWM brake pin inverse function. + */ +void EPWM_EnableBrakePinInverse(EPWM_T *epwm, uint32_t u32BrakePinNum) +{ + (epwm)->BNF |= (EPWM_BNF_BRK0PINV_Msk << (u32BrakePinNum << 3U)); +} + +/** + * @brief Disable EPWM brake pin inverse function + * @param[in] epwm The pointer of the specified EPWM module + * - EPWM0 : EPWM Group 0 + * - EPWM1 : EPWM Group 1 + * @param[in] u32BrakePinNum Brake pin selection. Valid values are 0 or 1. + * @return None + * @details This function is used to disable EPWM brake pin inverse function. + */ +void EPWM_DisableBrakePinInverse(EPWM_T *epwm, uint32_t u32BrakePinNum) +{ + (epwm)->BNF &= ~(EPWM_BNF_BRK0PINV_Msk << (u32BrakePinNum * (uint32_t)EPWM_BNF_BRK1NFEN_Pos)); +} + +/** + * @brief Set EPWM brake pin source + * @param[in] epwm The pointer of the specified EPWM module + * - EPWM0 : EPWM Group 0 + * - EPWM1 : EPWM Group 1 + * @param[in] u32BrakePinNum Brake pin selection. Valid values are 0 or 1. + * @param[in] u32SelAnotherModule Select to another module. Valid values are TRUE or FALSE. + * @return None + * @details This function is used to set EPWM brake pin source. + */ +void EPWM_SetBrakePinSource(EPWM_T *epwm, uint32_t u32BrakePinNum, uint32_t u32SelAnotherModule) +{ + (epwm)->BNF = ((epwm)->BNF & ~(EPWM_BNF_BK0SRC_Msk << (u32BrakePinNum << 3U))) | (u32SelAnotherModule << ((uint32_t)EPWM_BNF_BK0SRC_Pos + (u32BrakePinNum << 3U))); +} + +/** + * @brief Set EPWM leading edge blanking function + * @param[in] epwm The pointer of the specified EPWM module + * - EPWM0 : EPWM Group 0 + * - EPWM1 : EPWM Group 1 + * @param[in] u32TrigSrcSel Leading edge blanking source selection. + * - \ref EPWM_LEBCTL_SRCEN0 + * - \ref EPWM_LEBCTL_SRCEN2 + * - \ref EPWM_LEBCTL_SRCEN4 + * - \ref EPWM_LEBCTL_SRCEN0_2 + * - \ref EPWM_LEBCTL_SRCEN0_4 + * - \ref EPWM_LEBCTL_SRCEN2_4 + * - \ref EPWM_LEBCTL_SRCEN0_2_4 + * @param[in] u32TrigType Leading edge blanking trigger type. + * - \ref EPWM_LEBCTL_TRGTYPE_RISING + * - \ref EPWM_LEBCTL_TRGTYPE_FALLING + * - \ref EPWM_LEBCTL_TRGTYPE_RISING_OR_FALLING + * @param[in] u32BlankingCnt Leading Edge Blanking Counter. Valid values are between 1~512. + This counter value decides leading edge blanking window size, and this counter clock base is ECLK. + * @param[in] u32BlankingEnable Enable EPWM leading edge blanking function. Valid values are TRUE (ENABLE) or FALSE (DISABLE). + * - \ref FALSE + * - \ref TRUE + * @return None + * @details This function is used to configure EPWM leading edge blanking function that blank the false trigger from ACMP brake source which may cause by EPWM output transition. + * @note EPWM leading edge blanking function is only used for brake source from ACMP. + */ +void EPWM_SetLeadingEdgeBlanking(EPWM_T *epwm, uint32_t u32TrigSrcSel, uint32_t u32TrigType, uint32_t u32BlankingCnt, uint32_t u32BlankingEnable) +{ + (epwm)->LEBCTL = (u32TrigType) | (u32TrigSrcSel) | (u32BlankingEnable); + /* Blanking window size = LEBCNT + 1, so LEBCNT = u32BlankingCnt - 1 */ + (epwm)->LEBCNT = (u32BlankingCnt) - 1U; +} + +/** + * @brief Get the time-base counter reached its maximum value flag of selected channel + * @param[in] epwm The pointer of the specified EPWM module + * - EPWM0 : EPWM Group 0 + * - EPWM1 : EPWM Group 1 + * @param[in] u32ChannelNum EPWM channel number. Valid values are between 0~5 + * @return Count to max interrupt flag of specified channel + * @retval 0 Count to max interrupt did not occur + * @retval 1 Count to max interrupt occurred + * @details This function is used to get the time-base counter reached its maximum value flag of selected channel. + */ +uint32_t EPWM_GetWrapAroundFlag(EPWM_T *epwm, uint32_t u32ChannelNum) +{ + return (((epwm)->STATUS & (EPWM_STATUS_CNTMAXF0_Msk << u32ChannelNum)) ? 1UL : 0UL); +} + +/** + * @brief Clear the time-base counter reached its maximum value flag of selected channel + * @param[in] epwm The pointer of the specified EPWM module + * - EPWM0 : EPWM Group 0 + * - EPWM1 : EPWM Group 1 + * @param[in] u32ChannelNum EPWM channel number. Valid values are between 0~5 + * @return None + * @details This function is used to clear the time-base counter reached its maximum value flag of selected channel. + */ +void EPWM_ClearWrapAroundFlag(EPWM_T *epwm, uint32_t u32ChannelNum) +{ + (epwm)->STATUS = (EPWM_STATUS_CNTMAXF0_Msk << u32ChannelNum); +} + +/** + * @brief Enable fault detect of selected channel. + * @param[in] epwm The pointer of the specified EPWM module. + * - EPWM0 : EPWM Group 0 + * - EPWM1 : EPWM Group 1 + * @param[in] u32ChannelNum EPWM channel number. Valid values are between 0~5. + * @param[in] u32AfterPrescaler Fault Detect Clock Source is from prescaler output. Valid values are TRUE (after prescaler) or FALSE (before prescaler). + * @param[in] u32ClkSel Fault Detect Clock Select. + * - \ref EPWM_FDCTL_FDCKSEL_CLK_DIV_1 + * - \ref EPWM_FDCTL_FDCKSEL_CLK_DIV_2 + * - \ref EPWM_FDCTL_FDCKSEL_CLK_DIV_4 + * - \ref EPWM_FDCTL_FDCKSEL_CLK_DIV_8 + * @return None + * @details This function is used to enable fault detect of selected channel. + */ +void EPWM_EnableFaultDetect(EPWM_T *epwm, uint32_t u32ChannelNum, uint32_t u32AfterPrescaler, uint32_t u32ClkSel) +{ + (epwm)->FDEN = ((epwm)->FDEN & ~(EPWM_FDEN_FDCKS0_Msk << (u32ChannelNum))) | \ + ((EPWM_FDEN_FDEN0_Msk | ((u32AfterPrescaler) << EPWM_FDEN_FDCKS0_Pos)) << (u32ChannelNum)); + (epwm)->FDCTL[(u32ChannelNum)] = ((epwm)->FDCTL[(u32ChannelNum)] & ~EPWM_FDCTL0_FDCKSEL_Msk) | (u32ClkSel); +} + +/** + * @brief Disable fault detect of selected channel. + * @param[in] epwm The pointer of the specified EPWM module. + * - EPWM0 : EPWM Group 0 + * - EPWM1 : EPWM Group 1 + * @param[in] u32ChannelNum EPWM channel number. Valid values are between 0~5. + * @return None + * @details This function is used to disable fault detect of selected channel. + */ +void EPWM_DisableFaultDetect(EPWM_T *epwm, uint32_t u32ChannelNum) +{ + (epwm)->FDEN &= ~(EPWM_FDEN_FDEN0_Msk << (u32ChannelNum)); +} + +/** + * @brief Enable fault detect output of selected channel. + * @param[in] epwm The pointer of the specified EPWM module. + * - EPWM0 : EPWM Group 0 + * - EPWM1 : EPWM Group 1 + * @param[in] u32ChannelNum EPWM channel number. Valid values are between 0~5. + * @return None + * @details This function is used to enable fault detect output of selected channel. + */ +void EPWM_EnableFaultDetectOutput(EPWM_T *epwm, uint32_t u32ChannelNum) +{ + (epwm)->FDEN &= ~(EPWM_FDEN_FDODIS0_Msk << (u32ChannelNum)); +} + +/** + * @brief Disable fault detect output of selected channel. + * @param[in] epwm The pointer of the specified EPWM module. + * - EPWM0 : EPWM Group 0 + * - EPWM1 : EPWM Group 1 + * @param[in] u32ChannelNum EPWM channel number. Valid values are between 0~5. + * @return None + * @details This function is used to disable fault detect output of selected channel. + */ +void EPWM_DisableFaultDetectOutput(EPWM_T *epwm, uint32_t u32ChannelNum) +{ + (epwm)->FDEN |= (EPWM_FDEN_FDODIS0_Msk << (u32ChannelNum)); +} + +/** + * @brief Enable fault detect deglitch function of selected channel. + * @param[in] epwm The pointer of the specified EPWM module. + * - EPWM0 : EPWM Group 0 + * - EPWM1 : EPWM Group 1 + * @param[in] u32ChannelNum EPWM channel number. Valid values are between 0~5. + * @param[in] u32DeglitchSmpCycle Deglitch Sampling Cycle. Valid values are between 0~7. + * @return None + * @details This function is used to enable fault detect deglitch function of selected channel. + */ +void EPWM_EnableFaultDetectDeglitch(EPWM_T *epwm, uint32_t u32ChannelNum, uint32_t u32DeglitchSmpCycle) +{ + (epwm)->FDCTL[(u32ChannelNum)] = ((epwm)->FDCTL[(u32ChannelNum)] & (~EPWM_FDCTL0_DGSMPCYC_Msk)) | \ + (EPWM_FDCTL0_FDDGEN_Msk | ((u32DeglitchSmpCycle) << EPWM_FDCTL0_DGSMPCYC_Pos)); +} + +/** + * @brief Disable fault detect deglitch function of selected channel. + * @param[in] epwm The pointer of the specified EPWM module. + * - EPWM0 : EPWM Group 0 + * - EPWM1 : EPWM Group 1 + * @param[in] u32ChannelNum EPWM channel number. Valid values are between 0~5. + * @return None + * @details This function is used to disable fault detect deglitch function of selected channel. + */ +void EPWM_DisableFaultDetectDeglitch(EPWM_T *epwm, uint32_t u32ChannelNum) +{ + (epwm)->FDCTL[(u32ChannelNum)] &= ~EPWM_FDCTL0_FDDGEN_Msk; +} + +/** + * @brief Enable fault detect mask function of selected channel. + * @param[in] epwm The pointer of the specified EPWM module. + * - EPWM0 : EPWM Group 0 + * - EPWM1 : EPWM Group 1 + * @param[in] u32ChannelNum EPWM channel number. Valid values are between 0~5. + * @param[in] u32MaskCnt Transition mask counter. Valid values are between 0~0x7F. + * @return None + * @details This function is used to enable fault detect mask function of selected channel. + */ +void EPWM_EnableFaultDetectMask(EPWM_T *epwm, uint32_t u32ChannelNum, uint32_t u32MaskCnt) +{ + (epwm)->FDCTL[(u32ChannelNum)] = ((epwm)->FDCTL[(u32ChannelNum)] & (~EPWM_FDCTL0_TRMSKCNT_Msk)) | (EPWM_FDCTL0_FDMSKEN_Msk | (u32MaskCnt)); +} + +/** + * @brief Disable fault detect mask function of selected channel. + * @param[in] epwm The pointer of the specified EPWM module. + * - EPWM0 : EPWM Group 0 + * - EPWM1 : EPWM Group 1 + * @param[in] u32ChannelNum EPWM channel number. Valid values are between 0~5. + * @return None + * @details This function is used to disable fault detect mask function of selected channel. + */ +void EPWM_DisableFaultDetectMask(EPWM_T *epwm, uint32_t u32ChannelNum) +{ + (epwm)->FDCTL[(u32ChannelNum)] &= ~EPWM_FDCTL0_FDMSKEN_Msk; +} + +/** + * @brief Enable fault detect interrupt of selected channel. + * @param[in] epwm The pointer of the specified EPWM module. + * - EPWM0 : EPWM Group 0 + * - EPWM1 : EPWM Group 1 + * @param[in] u32ChannelNum EPWM channel number. Valid values are between 0~5. + * @return None + * @details This function is used to enable fault detect interrupt of selected channel. + */ +void EPWM_EnableFaultDetectInt(EPWM_T *epwm, uint32_t u32ChannelNum) +{ + (epwm)->FDIEN |= (EPWM_FDIEN_FDIEN0_Msk << (u32ChannelNum)); +} + +/** + * @brief Disable fault detect interrupt of selected channel. + * @param[in] epwm The pointer of the specified EPWM module. + * - EPWM0 : EPWM Group 0 + * - EPWM1 : EPWM Group 1 + * @param[in] u32ChannelNum EPWM channel number. Valid values are between 0~5. + * @return None + * @details This function is used to disable fault detect interrupt of selected channel. + */ +void EPWM_DisableFaultDetectInt(EPWM_T *epwm, uint32_t u32ChannelNum) +{ + (epwm)->FDIEN &= ~(EPWM_FDIEN_FDIEN0_Msk << (u32ChannelNum)); +} + +/** + * @brief Clear fault detect interrupt of selected channel. + * @param[in] epwm The pointer of the specified EPWM module. + * - EPWM0 : EPWM Group 0 + * - EPWM1 : EPWM Group 1 + * @param[in] u32ChannelNum EPWM channel number. Valid values are between 0~5. + * @return None + * @details This function is used to clear fault detect interrupt of selected channel. + */ +void EPWM_ClearFaultDetectInt(EPWM_T *epwm, uint32_t u32ChannelNum) +{ + (epwm)->FDSTS = (EPWM_FDSTS_FDIF0_Msk << (u32ChannelNum)); +} + +/** + * @brief Get fault detect interrupt of selected channel. + * @param[in] epwm The pointer of the specified EPWM module. + * - EPWM0 : EPWM Group 0 + * - EPWM1 : EPWM Group 1 + * @param[in] u32ChannelNum EPWM channel number. Valid values are between 0~5. + * @retval 0 Fault detect interrupt did not occur. + * @retval 1 Fault detect interrupt occurred. + * @details This function is used to Get fault detect interrupt of selected channel. + */ +uint32_t EPWM_GetFaultDetectInt(EPWM_T *epwm, uint32_t u32ChannelNum) +{ + return (((epwm)->FDSTS & (EPWM_FDSTS_FDIF0_Msk << (u32ChannelNum))) ? 1UL : 0UL); +} + +/*@}*/ /* end of group EPWM_EXPORTED_FUNCTIONS */ + +/*@}*/ /* end of group EPWM_Driver */ + +/*@}*/ /* end of group Standard_Driver */ + diff --git a/bsp/nuvoton/libraries/ma35/StdDriver/src/nu_gpio.c b/bsp/nuvoton/libraries/ma35/StdDriver/src/nu_gpio.c new file mode 100644 index 0000000000..7ea2713ea7 --- /dev/null +++ b/bsp/nuvoton/libraries/ma35/StdDriver/src/nu_gpio.c @@ -0,0 +1,255 @@ +/**************************************************************************//** + * @file gpio.c + * @brief GPIO driver source file + * + * SPDX-License-Identifier: Apache-2.0 + * @copyright (C) 2020 Nuvoton Technology Corp. All rights reserved. + *****************************************************************************/ + +#include "NuMicro.h" + +/** @addtogroup Standard_Driver Standard Driver + @{ +*/ + +/** @addtogroup GPIO_Driver GPIO Driver + @{ +*/ + +/** @addtogroup GPIO_EXPORTED_FUNCTIONS GPIO Exported Functions + @{ +*/ + +/** + * @brief Set GPIO operation mode + * + * @param[in] port GPIO port. It could be PA, PB, PC, PD, PE, PF, PG or PH. + * @param[in] u32PinMask The single or multiple pins of specified GPIO port. + * It could be BIT0 ~ BIT15 for PA, PB, PC, PD, PF and PH GPIO port. + * It could be BIT0 ~ BIT13 for PE GPIO port. + * It could be BIT0 ~ BIT11 for PG GPIO port. + * @param[in] u32Mode Operation mode. It could be \n + * GPIO_MODE_INPUT, GPIO_MODE_OUTPUT, GPIO_MODE_OPEN_DRAIN, GPIO_MODE_QUASI. + * + * @return None + * + * @details This function is used to set specified GPIO operation mode. + */ +void GPIO_SetMode(GPIO_T *port, uint32_t u32PinMask, uint32_t u32Mode) +{ + uint32_t i; + + for (i = 0ul; i < GPIO_PIN_MAX; i++) + { + if ((u32PinMask & (1ul << i)) == (1ul << i)) + { + port->MODE = (port->MODE & ~(0x3ul << (i << 1))) | (u32Mode << (i << 1)); + } + } +} + +/** + * @brief Enable GPIO interrupt + * + * @param[in] port GPIO port. It could be PA, PB, PC, PD, PE, PF, PG or PH. + * @param[in] u32Pin The pin of specified GPIO port. + * It could be 0 ~ 15 for PA, PB, PC, PD, PF and PH GPIO port. + * It could be 0 ~ 13 for PE GPIO port. + * It could be 0 ~ 11 for PG GPIO port. + * @param[in] u32IntAttribs The interrupt attribute of specified GPIO pin. It could be \n + * GPIO_INT_RISING, GPIO_INT_FALLING, GPIO_INT_BOTH_EDGE, GPIO_INT_HIGH, GPIO_INT_LOW. + * + * @return None + * + * @details This function is used to enable specified GPIO pin interrupt. + */ +void GPIO_EnableInt(GPIO_T *port, uint32_t u32Pin, uint32_t u32IntAttribs) +{ + port->INTTYPE = (port->INTTYPE & ~(1ul << u32Pin)) | (((u32IntAttribs >> 24) & 0xFFUL) << u32Pin); + port->INTEN = (port->INTEN & ~(0x00010001ul << u32Pin)) | ((u32IntAttribs & 0xFFFFFFUL) << u32Pin); +} + + +/** + * @brief Disable GPIO interrupt + * + * @param[in] port GPIO port. It could be PA, PB, PC, PD, PE, PF, PG or PH. + * @param[in] u32Pin The pin of specified GPIO port. + * It could be 0 ~ 15 for PA, PB, PC, PD, PF and PH GPIO port. + * It could be 0 ~ 13 for PE GPIO port. + * It could be 0 ~ 11 for PG GPIO port. + * + * @return None + * + * @details This function is used to disable specified GPIO pin interrupt. + */ +void GPIO_DisableInt(GPIO_T *port, uint32_t u32Pin) +{ + port->INTTYPE &= ~(1UL << u32Pin); + port->INTEN &= ~((0x00010001UL) << u32Pin); +} + +/** + * @brief Set GPIO slew rate control + * + * @param[in] port GPIO port. It could be \ref PA, \ref PB, ... or \ref GPH + * @param[in] u32PinMask The single or multiple pins of specified GPIO port. + * @param[in] u32Mode Slew rate mode. \ref GPIO_SLEWCTL_NORMAL (maximum 40 MHz at 2.7V) + * \ref GPIO_SLEWCTL_HIGH (maximum 80 MHz at 2.7V) + * \ref GPIO_SLEWCTL_FAST (maximum 100 MHz at 2.7V) + * + * @return None + * + * @details This function is used to set specified GPIO operation mode. + */ +void GPIO_SetSlewCtl(GPIO_T *port, uint32_t u32PinMask, uint32_t u32Mode) +{ + uint32_t i; + + for (i = 0ul; i < GPIO_PIN_MAX; i++) + { + if (u32PinMask & (1ul << i)) + { + port->SLEWCTL = (port->SLEWCTL & ~(0x3ul << (i << 1))) | (u32Mode << (i << 1)); + } + } +} + +/** + * @brief Set GPIO Pull-up and Pull-down control + * + * @param[in] port GPIO port. It could be \ref PA, \ref PB, ... or \ref GPH + * @param[in] u32PinMask The pin of specified GPIO port. It could be 0 ~ 15. + * @param[in] u32Mode The pin mode of specified GPIO pin. It could be + * \ref GPIO_PUSEL_DISABLE + * \ref GPIO_PUSEL_PULL_UP + * \ref GPIO_PUSEL_PULL_DOWN + * + * @return None + * + * @details Set the pin mode of specified GPIO pin. + */ +void GPIO_SetPullCtl(GPIO_T *port, uint32_t u32PinMask, uint32_t u32Mode) +{ + uint32_t i; + + for (i = 0ul; i < GPIO_PIN_MAX; i++) + { + if (u32PinMask & (1ul << i)) + { + port->PUSEL = (port->PUSEL & ~(0x3ul << (i << 1))) | (u32Mode << (i << 1)); + } + } +} + +/** + * @brief Set GPIO Driving Strength control + * + * @param[in] port GPIO port. It could be \ref PA, \ref PB, ... or \ref GPH + * @param[in] u32PinMask The pin of specified GPIO port. It could be 0 ~ 15. + * @param[in] u32Driving The pin driving strength of specified GPIO pin. It could be + * \ref 000 = Px.n is minimum deiver strength. + * \ref 111 = Px.n is maximum deiver strength. + * + * @return None + * + * @details Set the driving strength of specified GPIO pin. + */ +void GPIO_SetDrivingCtl(GPIO_T *port, uint32_t u32PinMask, uint32_t u32Driving) +{ + uint32_t i; + + for (i = 0ul; i < GPIO_PIN_MAX; i++) + { + if (u32PinMask & (1ul << i)) + { + volatile uint32_t *pu32DS = &port->DSL + (i / 8); + uint32_t u32Offset = 4 * (i % 8); + *pu32DS = (*pu32DS & ~(0x7ul << u32Offset)) | ((u32Driving & 0x7) << u32Offset); + } + } +} + +uint32_t GPIO_GetDrivingCtl(GPIO_T *port, uint32_t u32PinNo) +{ + volatile uint32_t *pu32DS = &port->DSL + (u32PinNo / 8); + uint32_t u32Offset = 4 * (u32PinNo % 8) ; + return (*pu32DS >> u32Offset) & 0x7; +} + +/** + * @brief Set GPIO Power Mode + * + * @param[in] port GPIO port. It could be \ref PA, \ref PB, ... or \ref GPH + * @param[in] u32PinMask The pin of specified GPIO port. It could be 0 ~ 15. + * @param[in] u32PowerMode The pin driving strength of specified GPIO pin. It could be + * \ref 0 = Px.n is 1.8v. + * \ref 1 = Px.n is 3.3v. + * + * @return None + * + * @details Set the power mode of specified GPIO pin. + * Only PB.0~15, PD.1, PE.2~13, PF.0~13, PG.10, PJ.0~11, PK.9~10, PN.10~11 pad voltage can be selected. + */ +void GPIO_SetPowerMode(GPIO_T *port, uint32_t u32PinMask, uint32_t u32PowerMode) +{ + uint32_t i; + + for (i = 0ul; i < GPIO_PIN_MAX; i++) + { + if (u32PinMask & (1ul << i)) + { + uint32_t value = port->SPW; + value &= ~(1 << i); + value |= ((u32PowerMode ? 1 : 0) << i); + port->SPW = value; + } + } +} + +uint32_t GPIO_GetPowerMode(GPIO_T *port, uint32_t u32PinNo) +{ + return (port->SPW & (1 << u32PinNo)) >> u32PinNo; +} + +/** + * @brief Set GPIO Input Schmitt Trigger + * + * @param[in] port GPIO port. It could be \ref PA, \ref PB, ... or \ref GPH + * @param[in] u32PinMask The pin of specified GPIO port. It could be 0 ~ 15. + * @param[in] u32SchmittTrigger The pin driving strength of specified GPIO pin. It could be + * \ref 0 = Px.n input schmitt trigger function Disabled. + * \ref 1 = Px.n input schmitt trigger function Enabled. + * + * @return None + * + * @details Set the power mode of specified GPIO pin. + * Only PB.0~15, PD.1, PE.2~13, PF.0~13, PG.10, PJ.0~11, PK.9~10, PN.10~11 pad voltage can be selected. + */ +void GPIO_SetSchmittTriggere(GPIO_T *port, uint32_t u32PinMask, uint32_t u32SchmittTrigger) +{ + uint32_t i; + + for (i = 0ul; i < GPIO_PIN_MAX; i++) + { + if (u32PinMask & (1ul << i)) + { + uint32_t value = port->SMTEN; + value &= ~(1 << i); + value |= ((u32SchmittTrigger ? 1 : 0) << i); + port->SMTEN = value; + } + } +} + +uint32_t GPIO_GetSchmittTriggere(GPIO_T *port, uint32_t u32PinNo) +{ + return (port->SMTEN & (1 << u32PinNo)) >> u32PinNo; +} + +/*@}*/ /* end of group GPIO_EXPORTED_FUNCTIONS */ + +/*@}*/ /* end of group GPIO_Driver */ + +/*@}*/ /* end of group Standard_Driver */ + diff --git a/bsp/nuvoton/libraries/ma35/StdDriver/src/nu_i2c.c b/bsp/nuvoton/libraries/ma35/StdDriver/src/nu_i2c.c new file mode 100644 index 0000000000..6baf9e91fb --- /dev/null +++ b/bsp/nuvoton/libraries/ma35/StdDriver/src/nu_i2c.c @@ -0,0 +1,1244 @@ +/**************************************************************************//** + * @file i2c.c + * @brief I2C driver source file + * + * SPDX-License-Identifier: Apache-2.0 + * @copyright (C) 2020 Nuvoton Technology Corp. All rights reserved. + *****************************************************************************/ +#include "NuMicro.h" + +/** @addtogroup Standard_Driver Standard Driver + @{ +*/ + +/** @addtogroup I2C_Driver I2C Driver + @{ +*/ + + +/** @addtogroup I2C_EXPORTED_FUNCTIONS I2C Exported Functions + @{ +*/ + +/** + * @brief Enable specify I2C Controller and set Clock Divider + * + * @param[in] i2c Specify I2C port + * @param[in] u32BusClock The target I2C bus clock in Hz + * + * @return Actual I2C bus clock frequency + * + * @details The function enable the specify I2C Controller and set proper Clock Divider + * in I2C CLOCK DIVIDED REGISTER (I2CLK) according to the target I2C Bus clock. + * I2C Bus clock = PCLK / (4*(divider+1). + * + */ +uint32_t I2C_Open(I2C_T *i2c, uint32_t u32BusClock) +{ + uint32_t u32Div; + uint32_t u32Pclk; + + u32Pclk = CLK_GetPCLK0Freq(); + + u32Div = (uint32_t)(((u32Pclk * 10U) / (u32BusClock * 4U) + 5U) / 10U - 1U); /* Compute proper divider for I2C clock */ + i2c->CLKDIV = u32Div; + + /* Enable I2C */ + i2c->CTL0 |= I2C_CTL0_I2CEN_Msk; + + return (u32Pclk / ((u32Div + 1U) << 2U)); +} + +/** + * @brief Disable specify I2C Controller + * + * @param[in] i2c Specify I2C port + * + * @return None + * + * @details Reset I2C Controller and disable specify I2C port. + * + */ + +void I2C_Close(I2C_T *i2c) +{ + /* Reset I2C Controller */ + if ((uint32_t)i2c == I2C0_BASE) + { + SYS->IPRST1 |= SYS_IPRST1_I2C0RST_Msk; + SYS->IPRST1 &= ~SYS_IPRST1_I2C0RST_Msk; + } + else if ((uint32_t)i2c == I2C1_BASE) + { + SYS->IPRST1 |= SYS_IPRST1_I2C1RST_Msk; + SYS->IPRST1 &= ~SYS_IPRST1_I2C1RST_Msk; + } + else if ((uint32_t)i2c == I2C2_BASE) + { + SYS->IPRST1 |= SYS_IPRST1_I2C2RST_Msk; + SYS->IPRST1 &= ~SYS_IPRST1_I2C2RST_Msk; + } + else if ((uint32_t)i2c == I2C3_BASE) + { + SYS->IPRST1 |= SYS_IPRST1_I2C3RST_Msk; + SYS->IPRST1 &= ~SYS_IPRST1_I2C3RST_Msk; + } + else if ((uint32_t)i2c == I2C4_BASE) + { + SYS->IPRST1 |= SYS_IPRST3_I2C4RST_Pos; + SYS->IPRST1 &= ~SYS_IPRST3_I2C4RST_Pos; + } + else if ((uint32_t)i2c == I2C5_BASE) + { + SYS->IPRST1 |= SYS_IPRST3_I2C5RST_Pos; + SYS->IPRST1 &= ~SYS_IPRST3_I2C5RST_Pos; + } + + /* Disable I2C */ + i2c->CTL0 &= ~I2C_CTL0_I2CEN_Msk; +} + +/** + * @brief Clear Time-out Counter flag + * + * @param[in] i2c Specify I2C port + * + * @return None + * + * @details When Time-out flag will be set, use this function to clear I2C Bus Time-out counter flag . + * + */ +void I2C_ClearTimeoutFlag(I2C_T *i2c) +{ + i2c->TOCTL |= I2C_TOCTL_TOIF_Msk; +} + +/** + * @brief Set Control bit of I2C Controller + * + * @param[in] i2c Specify I2C port + * @param[in] u8Start Set I2C START condition + * @param[in] u8Stop Set I2C STOP condition + * @param[in] u8Si Clear SI flag + * @param[in] u8Ack Set I2C ACK bit + * + * @return None + * + * @details The function set I2C Control bit of I2C Bus protocol. + * + */ +void I2C_Trigger(I2C_T *i2c, uint8_t u8Start, uint8_t u8Stop, uint8_t u8Si, uint8_t u8Ack) +{ + uint32_t u32Reg = 0U; + + if (u8Start) + { + u32Reg |= I2C_CTL_STA; + } + + if (u8Stop) + { + u32Reg |= I2C_CTL_STO; + } + + if (u8Si) + { + u32Reg |= I2C_CTL_SI; + } + + if (u8Ack) + { + u32Reg |= I2C_CTL_AA; + } + + i2c->CTL0 = (i2c->CTL0 & ~0x3CU) | u32Reg; +} + +/** + * @brief Disable Interrupt of I2C Controller + * + * @param[in] i2c Specify I2C port + * + * @return None + * + * @details The function is used for disable I2C interrupt + * + */ +void I2C_DisableInt(I2C_T *i2c) +{ + i2c->CTL0 &= ~I2C_CTL0_INTEN_Msk; +} + +/** + * @brief Enable Interrupt of I2C Controller + * + * @param[in] i2c Specify I2C port + * + * @return None + * + * @details The function is used for enable I2C interrupt + * + */ +void I2C_EnableInt(I2C_T *i2c) +{ + i2c->CTL0 |= I2C_CTL0_INTEN_Msk; +} + +/** + * @brief Get I2C Bus Clock + * + * @param[in] i2c Specify I2C port + * + * @return The actual I2C Bus clock in Hz + * + * @details To get the actual I2C Bus Clock frequency. + */ +uint32_t I2C_GetBusClockFreq(I2C_T *i2c) +{ + uint32_t u32Divider = i2c->CLKDIV; + uint32_t u32Pclk; + + u32Pclk = CLK_GetPCLK0Freq(); + + return (u32Pclk / ((u32Divider + 1U) << 2U)); +} + +/** + * @brief Set I2C Bus Clock + * + * @param[in] i2c Specify I2C port + * @param[in] u32BusClock The target I2C Bus Clock in Hz + * + * @return The actual I2C Bus Clock in Hz + * + * @details To set the actual I2C Bus Clock frequency. + */ +uint32_t I2C_SetBusClockFreq(I2C_T *i2c, uint32_t u32BusClock) +{ + uint32_t u32Div; + uint32_t u32Pclk; + + u32Pclk = CLK_GetPCLK0Freq(); + + u32Div = (uint32_t)(((u32Pclk * 10U) / (u32BusClock * 4U) + 5U) / 10U - 1U); /* Compute proper divider for I2C clock */ + i2c->CLKDIV = u32Div; + + return (u32Pclk / ((u32Div + 1U) << 2U)); +} + +/** + * @brief Get Interrupt Flag + * + * @param[in] i2c Specify I2C port + * + * @return I2C interrupt flag status + * + * @details To get I2C Bus interrupt flag. + */ +uint32_t I2C_GetIntFlag(I2C_T *i2c) +{ + uint32_t u32Value; + + if ((i2c->CTL0 & I2C_CTL0_SI_Msk) == I2C_CTL0_SI_Msk) + { + u32Value = 1U; + } + else + { + u32Value = 0U; + } + + return u32Value; +} + +/** + * @brief Get I2C Bus Status Code + * + * @param[in] i2c Specify I2C port + * + * @return I2C Status Code + * + * @details To get I2C Bus Status Code. + */ +uint32_t I2C_GetStatus(I2C_T *i2c) +{ + return (i2c->STATUS0); +} + +/** + * @brief Read a Byte from I2C Bus + * + * @param[in] i2c Specify I2C port + * + * @return I2C Data + * + * @details To read a bytes data from specify I2C port. + */ +uint8_t I2C_GetData(I2C_T *i2c) +{ + return (uint8_t)(i2c->DAT); +} + +/** + * @brief Send a byte to I2C Bus + * + * @param[in] i2c Specify I2C port + * @param[in] u8Data The data to send to I2C bus + * + * @return None + * + * @details This function is used to write a byte to specified I2C port + */ +void I2C_SetData(I2C_T *i2c, uint8_t u8Data) +{ + i2c->DAT = u8Data; +} + +/** + * @brief Set 7-bit Slave Address and GC Mode + * + * @param[in] i2c Specify I2C port + * @param[in] u8SlaveNo Set the number of I2C address register (0~3) + * @param[in] u8SlaveAddr 7-bit slave address + * @param[in] u8GCMode Enable/Disable GC mode (I2C_GCMODE_ENABLE / I2C_GCMODE_DISABLE) + * + * @return None + * + * @details This function is used to set 7-bit slave addresses in I2C SLAVE ADDRESS REGISTER (I2CADDR0~3) + * and enable GC Mode. + * + */ +void I2C_SetSlaveAddr(I2C_T *i2c, uint8_t u8SlaveNo, uint8_t u8SlaveAddr, uint8_t u8GCMode) +{ + switch (u8SlaveNo) + { + case 1: + i2c->ADDR1 = ((uint32_t)u8SlaveAddr << 1U) | u8GCMode; + break; + case 2: + i2c->ADDR2 = ((uint32_t)u8SlaveAddr << 1U) | u8GCMode; + break; + case 3: + i2c->ADDR3 = ((uint32_t)u8SlaveAddr << 1U) | u8GCMode; + break; + case 0: + default: + i2c->ADDR0 = ((uint32_t)u8SlaveAddr << 1U) | u8GCMode; + break; + } +} + +/** + * @brief Configure the mask bits of 7-bit Slave Address + * + * @param[in] i2c Specify I2C port + * @param[in] u8SlaveNo Set the number of I2C address mask register (0~3) + * @param[in] u8SlaveAddrMask A byte for slave address mask + * + * @return None + * + * @details This function is used to set 7-bit slave addresses. + * + */ +void I2C_SetSlaveAddrMask(I2C_T *i2c, uint8_t u8SlaveNo, uint8_t u8SlaveAddrMask) +{ + switch (u8SlaveNo) + { + case 1: + i2c->ADDRMSK1 = (uint32_t)u8SlaveAddrMask << 1U; + break; + case 2: + i2c->ADDRMSK2 = (uint32_t)u8SlaveAddrMask << 1U; + break; + case 3: + i2c->ADDRMSK3 = (uint32_t)u8SlaveAddrMask << 1U; + break; + case 0: + default: + i2c->ADDRMSK0 = (uint32_t)u8SlaveAddrMask << 1U; + break; + } +} + +/** + * @brief Enable Time-out Counter Function and support Long Time-out + * + * @param[in] i2c Specify I2C port + * @param[in] u8LongTimeout Configure DIV4 to enable Long Time-out (0/1) + * + * @return None + * + * @details This function enable Time-out Counter function and configure DIV4 to support Long + * Time-out. + * + */ +void I2C_EnableTimeout(I2C_T *i2c, uint8_t u8LongTimeout) +{ + if (u8LongTimeout) + { + i2c->TOCTL |= I2C_TOCTL_TOCDIV4_Msk; + } + else + { + i2c->TOCTL &= ~I2C_TOCTL_TOCDIV4_Msk; + } + + i2c->TOCTL |= I2C_TOCTL_TOCEN_Msk; +} + +/** + * @brief Disable Time-out Counter Function + * + * @param[in] i2c Specify I2C port + * + * @return None + * + * @details To disable Time-out Counter function in I2CTOC register. + * + */ +void I2C_DisableTimeout(I2C_T *i2c) +{ + i2c->TOCTL &= ~I2C_TOCTL_TOCEN_Msk; +} + +/** + * @brief Enable I2C Wake-up Function + * + * @param[in] i2c Specify I2C port + * + * @return None + * + * @details To enable Wake-up function of I2C Wake-up control register. + * + */ +void I2C_EnableWakeup(I2C_T *i2c) +{ + i2c->WKCTL |= I2C_WKCTL_WKEN_Msk; +} + +/** + * @brief Disable I2C Wake-up Function + * + * @param[in] i2c Specify I2C port + * + * @return None + * + * @details To disable Wake-up function of I2C Wake-up control register. + * + */ +void I2C_DisableWakeup(I2C_T *i2c) +{ + i2c->WKCTL &= ~I2C_WKCTL_WKEN_Msk; +} + +/** + * @brief Write a byte to Slave + * + * @param[in] *i2c Point to I2C peripheral + * @param[in] u8SlaveAddr Access Slave address(7-bit) + * @param[in] data Write a byte data to Slave + * + * @retval 0 Write data success + * @retval 1 Write data fail, or bus occurs error events + * + * @details The function is used for I2C Master write a byte data to Slave. + * + */ + +uint8_t I2C_WriteByte(I2C_T *i2c, uint8_t u8SlaveAddr, uint8_t data) +{ + uint8_t u8Xfering = 1u, u8Err = 0u, u8Ctrl = 0u; + + I2C_START(i2c); + while (u8Xfering && (u8Err == 0u)) + { + I2C_WAIT_READY(i2c) {} + switch (I2C_GET_STATUS(i2c)) + { + case 0x08u: + I2C_SET_DATA(i2c, (uint8_t)(u8SlaveAddr << 1u | 0x00u)); /* Write SLA+W to Register I2CDAT */ + u8Ctrl = I2C_CTL_SI; /* Clear SI */ + break; + case 0x18u: /* Slave Address ACK */ + I2C_SET_DATA(i2c, data); /* Write data to I2CDAT */ + break; + case 0x20u: /* Slave Address NACK */ + case 0x30u: /* Master transmit data NACK */ + u8Ctrl = I2C_CTL_STO_SI; /* Clear SI and send STOP */ + u8Err = 1u; + break; + case 0x28u: + u8Ctrl = I2C_CTL_STO_SI; /* Clear SI and send STOP */ + u8Xfering = 0u; + break; + case 0x38u: /* Arbitration Lost */ + default: /* Unknow status */ + I2C_SET_CONTROL_REG(i2c, I2C_CTL_STO_SI); /* Clear SI and send STOP */ + u8Ctrl = I2C_CTL_SI; + u8Err = 1u; + break; + } + I2C_SET_CONTROL_REG(i2c, u8Ctrl); /* Write controlbit to I2C_CTL register */ + } + return (u8Err | u8Xfering); /* return (Success)/(Fail) status */ +} + +/** + * @brief Write multi bytes to Slave + * + * @param[in] *i2c Point to I2C peripheral + * @param[in] u8SlaveAddr Access Slave address(7-bit) + * @param[in] *data Pointer to array to write data to Slave + * @param[in] u32wLen How many bytes need to write to Slave + * + * @return A length of how many bytes have been transmitted. + * + * @details The function is used for I2C Master write multi bytes data to Slave. + * + */ + +uint32_t I2C_WriteMultiBytes(I2C_T *i2c, uint8_t u8SlaveAddr, uint8_t data[], uint32_t u32wLen) +{ + uint8_t u8Xfering = 1u, u8Err = 0u, u8Ctrl = 0u; + uint32_t u32txLen = 0u; + + I2C_START(i2c); /* Send START */ + while (u8Xfering && (u8Err == 0u)) + { + I2C_WAIT_READY(i2c) {} + switch (I2C_GET_STATUS(i2c)) + { + case 0x08u: + I2C_SET_DATA(i2c, (uint8_t)(u8SlaveAddr << 1u | 0x00u)); /* Write SLA+W to Register I2CDAT */ + u8Ctrl = I2C_CTL_SI; /* Clear SI */ + break; + case 0x18u: /* Slave Address ACK */ + case 0x28u: + if (u32txLen < u32wLen) + { + I2C_SET_DATA(i2c, data[u32txLen++]); /* Write Data to I2CDAT */ + } + else + { + u8Ctrl = I2C_CTL_STO_SI; /* Clear SI and send STOP */ + u8Xfering = 0u; + } + break; + case 0x20u: /* Slave Address NACK */ + case 0x30u: /* Master transmit data NACK */ + u8Ctrl = I2C_CTL_STO_SI; /* Clear SI and send STOP */ + u8Err = 1u; + break; + case 0x38u: /* Arbitration Lost */ + default: /* Unknow status */ + I2C_SET_CONTROL_REG(i2c, I2C_CTL_STO_SI); /* Clear SI and send STOP */ + u8Ctrl = I2C_CTL_SI; + u8Err = 1u; + break; + } + I2C_SET_CONTROL_REG(i2c, u8Ctrl); /* Write controlbit to I2C_CTL register */ + } + return u32txLen; /* Return bytes length that have been transmitted */ +} + +/** + * @brief Specify a byte register address and write a byte to Slave + * + * @param[in] *i2c Point to I2C peripheral + * @param[in] u8SlaveAddr Access Slave address(7-bit) + * @param[in] u8DataAddr Specify a address (1 byte) of data write to + * @param[in] data A byte data to write it to Slave + * + * @retval 0 Write data success + * @retval 1 Write data fail, or bus occurs error events + * + * @details The function is used for I2C Master specify a address that data write to in Slave. + * + */ + +uint8_t I2C_WriteByteOneReg(I2C_T *i2c, uint8_t u8SlaveAddr, uint8_t u8DataAddr, uint8_t data) +{ + uint8_t u8Xfering = 1u, u8Err = 0u, u8Ctrl = 0u; + uint32_t u32txLen = 0u; + + I2C_START(i2c); /* Send START */ + while (u8Xfering && (u8Err == 0u)) + { + I2C_WAIT_READY(i2c) {} + switch (I2C_GET_STATUS(i2c)) + { + case 0x08u: + I2C_SET_DATA(i2c, (uint8_t)(u8SlaveAddr << 1u | 0x00u)); /* Send Slave address with write bit */ + u8Ctrl = I2C_CTL_SI; /* Clear SI */ + break; + case 0x18u: /* Slave Address ACK */ + I2C_SET_DATA(i2c, u8DataAddr); /* Write Lo byte address of register */ + break; + case 0x20u: /* Slave Address NACK */ + case 0x30u: /* Master transmit data NACK */ + u8Ctrl = I2C_CTL_STO_SI; /* Clear SI and send STOP */ + u8Err = 1u; + break; + case 0x28u: + if (u32txLen < 1u) + { + I2C_SET_DATA(i2c, data); + u32txLen++; + } + else + { + u8Ctrl = I2C_CTL_STO_SI; /* Clear SI and send STOP */ + u8Xfering = 0u; + } + break; + case 0x38u: /* Arbitration Lost */ + default: /* Unknow status */ + I2C_SET_CONTROL_REG(i2c, I2C_CTL_STO_SI); /* Clear SI and send STOP */ + u8Ctrl = I2C_CTL_SI; + u8Err = 1u; + break; + } + I2C_SET_CONTROL_REG(i2c, u8Ctrl); /* Write controlbit to I2C_CTL register */ + } + return (u8Err | u8Xfering); /* return (Success)/(Fail) status */ +} + + +/** + * @brief Specify a byte register address and write multi bytes to Slave + * + * @param[in] *i2c Point to I2C peripheral + * @param[in] u8SlaveAddr Access Slave address(7-bit) + * @param[in] u8DataAddr Specify a address (1 byte) of data write to + * @param[in] *data Pointer to array to write data to Slave + * @param[in] u32wLen How many bytes need to write to Slave + * + * @return A length of how many bytes have been transmitted. + * + * @details The function is used for I2C Master specify a byte address that multi data bytes write to in Slave. + * + */ + +uint32_t I2C_WriteMultiBytesOneReg(I2C_T *i2c, uint8_t u8SlaveAddr, uint8_t u8DataAddr, uint8_t data[], uint32_t u32wLen) +{ + uint8_t u8Xfering = 1u, u8Err = 0u, u8Ctrl = 0u; + uint32_t u32txLen = 0u; + + I2C_START(i2c); /* Send START */ + while (u8Xfering && (u8Err == 0u)) + { + I2C_WAIT_READY(i2c) {} + switch (I2C_GET_STATUS(i2c)) + { + case 0x08u: + I2C_SET_DATA(i2c, (uint8_t)(u8SlaveAddr << 1u | 0x00u)); /* Write SLA+W to Register I2CDAT */ + u8Ctrl = I2C_CTL_SI; + break; + case 0x18u: /* Slave Address ACK */ + I2C_SET_DATA(i2c, u8DataAddr); /* Write Lo byte address of register */ + break; + case 0x20u: /* Slave Address NACK */ + case 0x30u: /* Master transmit data NACK */ + u8Ctrl = I2C_CTL_STO_SI; /* Clear SI and send STOP */ + u8Err = 1u; + break; + case 0x28u: + if (u32txLen < u32wLen) + { + I2C_SET_DATA(i2c, data[u32txLen++]); + } + else + { + u8Ctrl = I2C_CTL_STO_SI; /* Clear SI and send STOP */ + u8Xfering = 0u; + } + break; + case 0x38u: /* Arbitration Lost */ + default: /* Unknow status */ + I2C_SET_CONTROL_REG(i2c, I2C_CTL_STO_SI); /* Clear SI and send STOP */ + u8Ctrl = I2C_CTL_SI; + u8Err = 1u; + break; + } + I2C_SET_CONTROL_REG(i2c, u8Ctrl); /* Write controlbit to I2C_CTL register */ + } + + return u32txLen; /* Return bytes length that have been transmitted */ +} + +/** + * @brief Specify two bytes register address and Write a byte to Slave + * + * @param[in] *i2c Point to I2C peripheral + * @param[in] u8SlaveAddr Access Slave address(7-bit) + * @param[in] u16DataAddr Specify a address (2 byte) of data write to + * @param[in] data Write a byte data to Slave + * + * @retval 0 Write data success + * @retval 1 Write data fail, or bus occurs error events + * + * @details The function is used for I2C Master specify two bytes address that data write to in Slave. + * + */ + +uint8_t I2C_WriteByteTwoRegs(I2C_T *i2c, uint8_t u8SlaveAddr, uint16_t u16DataAddr, uint8_t data) +{ + uint8_t u8Xfering = 1u, u8Err = 0u, u8Addr = 1u, u8Ctrl = 0u; + uint32_t u32txLen = 0u; + + I2C_START(i2c); /* Send START */ + while (u8Xfering && (u8Err == 0u)) + { + I2C_WAIT_READY(i2c) {} + switch (I2C_GET_STATUS(i2c)) + { + case 0x08u: + I2C_SET_DATA(i2c, (uint8_t)(u8SlaveAddr << 1u | 0x00u)); /* Write SLA+W to Register I2CDAT */ + u8Ctrl = I2C_CTL_SI; /* Clear SI */ + break; + case 0x18u: /* Slave Address ACK */ + I2C_SET_DATA(i2c, (uint8_t)((u16DataAddr & 0xFF00u) >> 8u)); /* Write Hi byte address of register */ + break; + case 0x20u: /* Slave Address NACK */ + case 0x30u: /* Master transmit data NACK */ + u8Ctrl = I2C_CTL_STO_SI; /* Clear SI and send STOP */ + u8Err = 1u; + break; + case 0x28u: + if (u8Addr) + { + I2C_SET_DATA(i2c, (uint8_t)(u16DataAddr & 0xFFu)); /* Write Lo byte address of register */ + u8Addr = 0u; + } + else if ((u32txLen < 1u) && (u8Addr == 0u)) + { + I2C_SET_DATA(i2c, data); + u32txLen++; + } + else + { + u8Ctrl = I2C_CTL_STO_SI; /* Clear SI and send STOP */ + u8Xfering = 0u; + } + break; + case 0x38u: /* Arbitration Lost */ + default: /* Unknow status */ + I2C_SET_CONTROL_REG(i2c, I2C_CTL_STO_SI); /* Clear SI and send STOP */ + u8Ctrl = I2C_CTL_SI; + u8Err = 1u; + break; + } + I2C_SET_CONTROL_REG(i2c, u8Ctrl); /* Write controlbit to I2C_CTL register */ + } + return (u8Err | u8Xfering); /* return (Success)/(Fail) status */ +} + + +/** + * @brief Specify two bytes register address and write multi bytes to Slave + * + * @param[in] *i2c Point to I2C peripheral + * @param[in] u8SlaveAddr Access Slave address(7-bit) + * @param[in] u16DataAddr Specify a address (2 bytes) of data write to + * @param[in] data[] A data array for write data to Slave + * @param[in] u32wLen How many bytes need to write to Slave + * + * @return A length of how many bytes have been transmitted. + * + * @details The function is used for I2C Master specify a byte address that multi data write to in Slave. + * + */ + +uint32_t I2C_WriteMultiBytesTwoRegs(I2C_T *i2c, uint8_t u8SlaveAddr, uint16_t u16DataAddr, uint8_t data[], uint32_t u32wLen) +{ + uint8_t u8Xfering = 1u, u8Err = 0u, u8Addr = 1u, u8Ctrl = 0u; + uint32_t u32txLen = 0u; + + I2C_START(i2c); /* Send START */ + while (u8Xfering && (u8Err == 0u)) + { + I2C_WAIT_READY(i2c) {} + switch (I2C_GET_STATUS(i2c)) + { + case 0x08u: + I2C_SET_DATA(i2c, (uint8_t)(u8SlaveAddr << 1u | 0x00u)); /* Write SLA+W to Register I2CDAT */ + u8Ctrl = I2C_CTL_SI; /* Clear SI */ + break; + case 0x18u: /* Slave Address ACK */ + I2C_SET_DATA(i2c, (uint8_t)((u16DataAddr & 0xFF00u) >> 8u)); /* Write Hi byte address of register */ + break; + case 0x20u: /* Slave Address NACK */ + case 0x30u: /* Master transmit data NACK */ + u8Ctrl = I2C_CTL_STO_SI; /* Clear SI and send STOP */ + u8Err = 1u; + break; + case 0x28u: + if (u8Addr) + { + I2C_SET_DATA(i2c, (uint8_t)(u16DataAddr & 0xFFu)); /* Write Lo byte address of register */ + u8Addr = 0u; + } + else if ((u32txLen < u32wLen) && (u8Addr == 0u)) + { + I2C_SET_DATA(i2c, data[u32txLen++]); /* Write data to Register I2CDAT*/ + } + else + { + u8Ctrl = I2C_CTL_STO_SI; /* Clear SI and send STOP */ + u8Xfering = 0u; + } + break; + case 0x38u: /* Arbitration Lost */ + default: /* Unknow status */ + I2C_SET_CONTROL_REG(i2c, I2C_CTL_STO_SI); /* Clear SI and send STOP */ + u8Ctrl = I2C_CTL_SI; + u8Err = 1u; + break; + } + I2C_SET_CONTROL_REG(i2c, u8Ctrl); /* Write controlbit to I2C_CTL register */ + } + return u32txLen; /* Return bytes length that have been transmitted */ +} + +/** + * @brief Read a byte from Slave + * + * @param[in] *i2c Point to I2C peripheral + * @param[in] u8SlaveAddr Access Slave address(7-bit) + * + * @return Read a byte data from Slave + * + * @details The function is used for I2C Master to read a byte data from Slave. + * + */ +uint8_t I2C_ReadByte(I2C_T *i2c, uint8_t u8SlaveAddr) +{ + uint8_t u8Xfering = 1u, u8Err = 0u, rdata = 0u, u8Ctrl = 0u; + + I2C_START(i2c); /* Send START */ + while (u8Xfering && (u8Err == 0u)) + { + I2C_WAIT_READY(i2c) {} + switch (I2C_GET_STATUS(i2c)) + { + case 0x08u: + I2C_SET_DATA(i2c, (uint8_t)((u8SlaveAddr << 1u) | 0x01u)); /* Write SLA+R to Register I2CDAT */ + u8Ctrl = I2C_CTL_SI; /* Clear SI */ + break; + case 0x40u: /* Slave Address ACK */ + u8Ctrl = I2C_CTL_SI; /* Clear SI */ + break; + case 0x48u: /* Slave Address NACK */ + u8Ctrl = I2C_CTL_STO_SI; /* Clear SI and send STOP */ + u8Err = 1u; + break; + case 0x58u: + rdata = (unsigned char) I2C_GET_DATA(i2c); /* Receive Data */ + u8Ctrl = I2C_CTL_STO_SI; /* Clear SI and send STOP */ + u8Xfering = 0u; + break; + case 0x38u: /* Arbitration Lost */ + default: /* Unknow status */ + I2C_SET_CONTROL_REG(i2c, I2C_CTL_STO_SI); /* Clear SI and send STOP */ + u8Ctrl = I2C_CTL_SI; + u8Err = 1u; + break; + } + I2C_SET_CONTROL_REG(i2c, u8Ctrl); /* Write controlbit to I2C_CTL register */ + } + if (u8Err) + { + rdata = 0u; /* If occurs error, return 0 */ + } + return rdata; /* Return read data */ +} + + +/** + * @brief Read multi bytes from Slave + * + * @param[in] *i2c Point to I2C peripheral + * @param[in] u8SlaveAddr Access Slave address(7-bit) + * @param[out] rdata[] A data array to store data from Slave + * @param[in] u32rLen How many bytes need to read from Slave + * + * @return A length of how many bytes have been received + * + * @details The function is used for I2C Master to read multi data bytes from Slave. + * + * + */ +uint32_t I2C_ReadMultiBytes(I2C_T *i2c, uint8_t u8SlaveAddr, uint8_t rdata[], uint32_t u32rLen) +{ + uint8_t u8Xfering = 1u, u8Err = 0u, u8Ctrl = 0u; + uint32_t u32rxLen = 0u; + + I2C_START(i2c); /* Send START */ + while (u8Xfering && (u8Err == 0u)) + { + I2C_WAIT_READY(i2c) {} + switch (I2C_GET_STATUS(i2c)) + { + case 0x08u: + I2C_SET_DATA(i2c, (uint8_t)((u8SlaveAddr << 1u) | 0x01u)); /* Write SLA+R to Register I2CDAT */ + u8Ctrl = I2C_CTL_SI; /* Clear SI */ + break; + case 0x40u: /* Slave Address ACK */ + u8Ctrl = I2C_CTL_SI_AA; /* Clear SI and set ACK */ + break; + case 0x48u: /* Slave Address NACK */ + u8Ctrl = I2C_CTL_STO_SI; /* Clear SI and send STOP */ + u8Err = 1u; + break; + case 0x50u: + rdata[u32rxLen++] = (unsigned char) I2C_GET_DATA(i2c); /* Receive Data */ + if (u32rxLen < (u32rLen - 1u)) + { + u8Ctrl = I2C_CTL_SI_AA; /* Clear SI and set ACK */ + } + else + { + u8Ctrl = I2C_CTL_SI; /* Clear SI */ + } + break; + case 0x58u: + rdata[u32rxLen++] = (unsigned char) I2C_GET_DATA(i2c); /* Receive Data */ + u8Ctrl = I2C_CTL_STO_SI; /* Clear SI and send STOP */ + u8Xfering = 0u; + break; + case 0x38u: /* Arbitration Lost */ + default: /* Unknow status */ + I2C_SET_CONTROL_REG(i2c, I2C_CTL_STO_SI); /* Clear SI and send STOP */ + u8Ctrl = I2C_CTL_SI; + u8Err = 1u; + break; + } + I2C_SET_CONTROL_REG(i2c, u8Ctrl); /* Write controlbit to I2C_CTL register */ + } + return u32rxLen; /* Return bytes length that have been received */ +} + + +/** + * @brief Specify a byte register address and read a byte from Slave + * + * @param[in] *i2c Point to I2C peripheral + * @param[in] u8SlaveAddr Access Slave address(7-bit) + * @param[in] u8DataAddr Specify a address(1 byte) of data read from + * + * @return Read a byte data from Slave + * + * @details The function is used for I2C Master specify a byte address that a data byte read from Slave. + * + * + */ +uint8_t I2C_ReadByteOneReg(I2C_T *i2c, uint8_t u8SlaveAddr, uint8_t u8DataAddr) +{ + uint8_t u8Xfering = 1u, u8Err = 0u, rdata = 0u, u8Ctrl = 0u; + + I2C_START(i2c); /* Send START */ + while (u8Xfering && (u8Err == 0u)) + { + I2C_WAIT_READY(i2c) {} + switch (I2C_GET_STATUS(i2c)) + { + case 0x08u: + I2C_SET_DATA(i2c, (uint8_t)(u8SlaveAddr << 1u | 0x00u)); /* Write SLA+W to Register I2CDAT */ + u8Ctrl = I2C_CTL_SI; /* Clear SI */ + break; + case 0x18u: /* Slave Address ACK */ + I2C_SET_DATA(i2c, u8DataAddr); /* Write Lo byte address of register */ + break; + case 0x20u: /* Slave Address NACK */ + case 0x30u: /* Master transmit data NACK */ + u8Ctrl = I2C_CTL_STO_SI; /* Clear SI and send STOP */ + u8Err = 1u; + break; + case 0x28u: + u8Ctrl = I2C_CTL_STA_SI; /* Send repeat START */ + break; + case 0x10u: + I2C_SET_DATA(i2c, (uint8_t)((u8SlaveAddr << 1u) | 0x01u)); /* Write SLA+R to Register I2CDAT */ + u8Ctrl = I2C_CTL_SI; /* Clear SI */ + break; + case 0x40u: /* Slave Address ACK */ + u8Ctrl = I2C_CTL_SI; /* Clear SI */ + break; + case 0x48u: /* Slave Address NACK */ + u8Ctrl = I2C_CTL_STO_SI; /* Clear SI and send STOP */ + u8Err = 1u; + break; + case 0x58u: + rdata = (uint8_t) I2C_GET_DATA(i2c); /* Receive Data */ + u8Ctrl = I2C_CTL_STO_SI; /* Clear SI and send STOP */ + u8Xfering = 0u; + break; + case 0x38u: /* Arbitration Lost */ + default: /* Unknow status */ + I2C_SET_CONTROL_REG(i2c, I2C_CTL_STO_SI); /* Clear SI and send STOP */ + u8Ctrl = I2C_CTL_SI; + u8Err = 1u; + break; + } + I2C_SET_CONTROL_REG(i2c, u8Ctrl); /* Write controlbit to I2C_CTL register */ + } + if (u8Err) + { + rdata = 0u; /* If occurs error, return 0 */ + } + return rdata; /* Return read data */ +} + +/** + * @brief Specify a byte register address and read multi bytes from Slave + * + * @param[in] *i2c Point to I2C peripheral + * @param[in] u8SlaveAddr Access Slave address(7-bit) + * @param[in] u8DataAddr Specify a address (1 bytes) of data read from + * @param[out] rdata[] A data array to store data from Slave + * @param[in] u32rLen How many bytes need to read from Slave + * + * @return A length of how many bytes have been received + * + * @details The function is used for I2C Master specify a byte address that multi data bytes read from Slave. + * + * + */ +uint32_t I2C_ReadMultiBytesOneReg(I2C_T *i2c, uint8_t u8SlaveAddr, uint8_t u8DataAddr, uint8_t rdata[], uint32_t u32rLen) +{ + uint8_t u8Xfering = 1u, u8Err = 0u, u8Ctrl = 0u; + uint32_t u32rxLen = 0u; + + I2C_START(i2c); /* Send START */ + while (u8Xfering && (u8Err == 0u)) + { + I2C_WAIT_READY(i2c) {} + switch (I2C_GET_STATUS(i2c)) + { + case 0x08u: + I2C_SET_DATA(i2c, (uint8_t)(u8SlaveAddr << 1u | 0x00u)); /* Write SLA+W to Register I2CDAT */ + u8Ctrl = I2C_CTL_SI; /* Clear SI */ + break; + case 0x18u: /* Slave Address ACK */ + I2C_SET_DATA(i2c, u8DataAddr); /* Write Lo byte address of register */ + break; + case 0x20u: /* Slave Address NACK */ + case 0x30u: /* Master transmit data NACK */ + u8Ctrl = I2C_CTL_STO_SI; /* Clear SI and send STOP */ + u8Err = 1u; + break; + case 0x28u: + u8Ctrl = I2C_CTL_STA_SI; /* Send repeat START */ + break; + case 0x10u: + I2C_SET_DATA(i2c, (uint8_t)((u8SlaveAddr << 1u) | 0x01u)); /* Write SLA+R to Register I2CDAT */ + u8Ctrl = I2C_CTL_SI; /* Clear SI */ + break; + case 0x40u: /* Slave Address ACK */ + u8Ctrl = I2C_CTL_SI_AA; /* Clear SI and set ACK */ + break; + case 0x48u: /* Slave Address NACK */ + u8Ctrl = I2C_CTL_STO_SI; /* Clear SI and send STOP */ + u8Err = 1u; + break; + case 0x50u: + rdata[u32rxLen++] = (uint8_t) I2C_GET_DATA(i2c); /* Receive Data */ + if (u32rxLen < (u32rLen - 1u)) + { + u8Ctrl = I2C_CTL_SI_AA; /* Clear SI and set ACK */ + } + else + { + u8Ctrl = I2C_CTL_SI; /* Clear SI */ + } + break; + case 0x58u: + rdata[u32rxLen++] = (uint8_t) I2C_GET_DATA(i2c); /* Receive Data */ + u8Ctrl = I2C_CTL_STO_SI; /* Clear SI and send STOP */ + u8Xfering = 0u; + break; + case 0x38u: /* Arbitration Lost */ + default: /* Unknow status */ + I2C_SET_CONTROL_REG(i2c, I2C_CTL_STO_SI); /* Clear SI and send STOP */ + u8Ctrl = I2C_CTL_SI; + u8Err = 1u; + break; + } + I2C_SET_CONTROL_REG(i2c, u8Ctrl); /* Write controlbit to I2C_CTL register */ + } + return u32rxLen; /* Return bytes length that have been received */ +} + +/** + * @brief Specify two bytes register address and read a byte from Slave + * + * @param[in] *i2c Point to I2C peripheral + * @param[in] u8SlaveAddr Access Slave address(7-bit) + * @param[in] u16DataAddr Specify an address(2 bytes) of data read from + * + * @return Read a byte data from Slave + * + * @details The function is used for I2C Master specify two bytes address that a data byte read from Slave. + * + * + */ +uint8_t I2C_ReadByteTwoRegs(I2C_T *i2c, uint8_t u8SlaveAddr, uint16_t u16DataAddr) +{ + uint8_t u8Xfering = 1u, u8Err = 0u, rdata = 0u, u8Addr = 1u, u8Ctrl = 0u; + + I2C_START(i2c); /* Send START */ + while (u8Xfering && (u8Err == 0u)) + { + I2C_WAIT_READY(i2c) {} + switch (I2C_GET_STATUS(i2c)) + { + case 0x08u: + I2C_SET_DATA(i2c, (uint8_t)(u8SlaveAddr << 1u | 0x00u)); /* Write SLA+W to Register I2CDAT */ + u8Ctrl = I2C_CTL_SI; /* Clear SI */ + break; + case 0x18u: /* Slave Address ACK */ + I2C_SET_DATA(i2c, (uint8_t)((u16DataAddr & 0xFF00u) >> 8u)); /* Write Hi byte address of register */ + break; + case 0x20u: /* Slave Address NACK */ + case 0x30u: /* Master transmit data NACK */ + u8Ctrl = I2C_CTL_STO_SI; /* Clear SI and send STOP */ + u8Err = 1u; + break; + case 0x28u: + if (u8Addr) + { + I2C_SET_DATA(i2c, (uint8_t)(u16DataAddr & 0xFFu)); /* Write Lo byte address of register */ + u8Addr = 0u; + } + else + { + u8Ctrl = I2C_CTL_STA_SI; /* Clear SI and send repeat START */ + } + break; + case 0x10u: + I2C_SET_DATA(i2c, (uint8_t)((u8SlaveAddr << 1u) | 0x01u)); /* Write SLA+R to Register I2CDAT */ + u8Ctrl = I2C_CTL_SI; /* Clear SI */ + break; + case 0x40u: /* Slave Address ACK */ + u8Ctrl = I2C_CTL_SI; /* Clear SI */ + break; + case 0x48u: /* Slave Address NACK */ + u8Ctrl = I2C_CTL_STO_SI; /* Clear SI and send STOP */ + u8Err = 1u; + break; + case 0x58u: + rdata = (unsigned char) I2C_GET_DATA(i2c); /* Receive Data */ + u8Ctrl = I2C_CTL_STO_SI; /* Clear SI and send STOP */ + u8Xfering = 0u; + break; + case 0x38u: /* Arbitration Lost */ + default: /* Unknow status */ + I2C_SET_CONTROL_REG(i2c, I2C_CTL_STO_SI); /* Clear SI and send STOP */ + u8Ctrl = I2C_CTL_SI; + u8Err = 1u; + break; + } + I2C_SET_CONTROL_REG(i2c, u8Ctrl); /* Write controlbit to I2C_CTL register */ + } + if (u8Err) + { + rdata = 0u; /* If occurs error, return 0 */ + } + return rdata; /* Return read data */ +} + +/** + * @brief Specify two bytes register address and read multi bytes from Slave + * + * @param[in] *i2c Point to I2C peripheral + * @param[in] u8SlaveAddr Access Slave address(7-bit) + * @param[in] u16DataAddr Specify a address (2 bytes) of data read from + * @param[out] rdata[] A data array to store data from Slave + * @param[in] u32rLen How many bytes need to read from Slave + * + * @return A length of how many bytes have been received + * + * @details The function is used for I2C Master specify two bytes address that multi data bytes read from Slave. + * + * + */ +uint32_t I2C_ReadMultiBytesTwoRegs(I2C_T *i2c, uint8_t u8SlaveAddr, uint16_t u16DataAddr, uint8_t rdata[], uint32_t u32rLen) +{ + uint8_t u8Xfering = 1u, u8Err = 0u, u8Addr = 1u, u8Ctrl = 0u; + uint32_t u32rxLen = 0u; + + I2C_START(i2c); /* Send START */ + while (u8Xfering && (u8Err == 0u)) + { + I2C_WAIT_READY(i2c) {} + switch (I2C_GET_STATUS(i2c)) + { + case 0x08u: + I2C_SET_DATA(i2c, (uint8_t)(u8SlaveAddr << 1u | 0x00u)); /* Write SLA+W to Register I2CDAT */ + u8Ctrl = I2C_CTL_SI; /* Clear SI */ + break; + case 0x18u: /* Slave Address ACK */ + I2C_SET_DATA(i2c, (uint8_t)((u16DataAddr & 0xFF00u) >> 8u)); /* Write Hi byte address of register */ + break; + case 0x20u: /* Slave Address NACK */ + case 0x30u: /* Master transmit data NACK */ + u8Ctrl = I2C_CTL_STO_SI; /* Clear SI and send STOP */ + u8Err = 1u; + break; + case 0x28u: + if (u8Addr) + { + I2C_SET_DATA(i2c, (uint8_t)(u16DataAddr & 0xFFu)); /* Write Lo byte address of register */ + u8Addr = 0u; + } + else + { + u8Ctrl = I2C_CTL_STA_SI; /* Clear SI and send repeat START */ + } + break; + case 0x10u: + I2C_SET_DATA(i2c, (uint8_t)((u8SlaveAddr << 1u) | 0x01u)); /* Write SLA+R to Register I2CDAT */ + u8Ctrl = I2C_CTL_SI; /* Clear SI */ + break; + case 0x40u: /* Slave Address ACK */ + u8Ctrl = I2C_CTL_SI_AA; /* Clear SI and set ACK */ + break; + case 0x48u: /* Slave Address NACK */ + u8Ctrl = I2C_CTL_STO_SI; /* Clear SI and send STOP */ + u8Err = 1u; + break; + case 0x50u: + rdata[u32rxLen++] = (unsigned char) I2C_GET_DATA(i2c); /* Receive Data */ + if (u32rxLen < (u32rLen - 1u)) + { + u8Ctrl = I2C_CTL_SI_AA; /* Clear SI and set ACK */ + } + else + { + u8Ctrl = I2C_CTL_SI; /* Clear SI */ + } + break; + case 0x58u: + rdata[u32rxLen++] = (unsigned char) I2C_GET_DATA(i2c); /* Receive Data */ + u8Ctrl = I2C_CTL_STO_SI; /* Clear SI and send STOP */ + u8Xfering = 0u; + break; + case 0x38u: /* Arbitration Lost */ + default: /* Unknow status */ + I2C_SET_CONTROL_REG(i2c, I2C_CTL_STO_SI); /* Clear SI and send STOP */ + u8Ctrl = I2C_CTL_SI; + u8Err = 1u; + break; + } + I2C_SET_CONTROL_REG(i2c, u8Ctrl); /* Write control bit to I2C_CTL register */ + } + return u32rxLen; /* Return bytes length that have been received */ +} + + +/*@}*/ /* end of group I2C_EXPORTED_FUNCTIONS */ + +/*@}*/ /* end of group I2C_Driver */ + +/*@}*/ /* end of group Standard_Driver */ + diff --git a/bsp/nuvoton/libraries/ma35/StdDriver/src/nu_i2s.c b/bsp/nuvoton/libraries/ma35/StdDriver/src/nu_i2s.c new file mode 100644 index 0000000000..6fd974f097 --- /dev/null +++ b/bsp/nuvoton/libraries/ma35/StdDriver/src/nu_i2s.c @@ -0,0 +1,269 @@ +/**************************************************************************//** + * @file i2s.c + * @brief I2S driver source file + * + * SPDX-License-Identifier: Apache-2.0 + * @copyright (C) 2020 Nuvoton Technology Corp. All rights reserved. + *****************************************************************************/ + +#include +#include "NuMicro.h" + +/** @addtogroup Standard_Driver Standard Driver + @{ +*/ + +/** @addtogroup I2S_Driver I2S Driver + @{ +*/ + +/** @addtogroup I2S_EXPORTED_FUNCTIONS I2S Exported Functions + @{ +*/ + +static uint32_t I2S_GetSourceClockFreq(I2S_T *i2s); + +/** + * @brief This function make I2S module be ready to transfer. + * @param[in] i2s The pointer of the specified I2S module. + * @return Source clock frequency of I2S peripheral. + * @details + * 0: _HXT + * 1: APLL + * 2: PCLK0 + * 3: HIRC + */ + +static uint32_t I2S_GetSourceClockFreq(I2S_T *i2s) +{ + uint32_t u32Freq = 0UL, u32ClkSrcSel; + uint32_t u32ClkSelMsk = 0U; + + if (i2s == I2S0) + { + u32ClkSelMsk = CLK_CLKSEL4_I2S0SEL_Msk; + } + else if (i2s == I2S1) + { + u32ClkSelMsk = CLK_CLKSEL4_I2S1SEL_Msk; + } + else + { + return 0U; + } + + /* get I2S selection clock source */ + u32ClkSrcSel = CLK->CLKSEL4 & u32ClkSelMsk; + + switch (u32ClkSrcSel) + { + case CLK_CLKSEL4_I2S0SEL_APLL: + u32Freq = CLK_GetPLLClockFreq(APLL); + break; + + case CLK_CLKSEL4_I2S0SEL_SYSCLK1_DIV2: + u32Freq = CLK_GetSYSCLK1Freq() / 2; + break; + + default: + u32Freq = CLK_GetPLLClockFreq(APLL); + break; + } + + return u32Freq; +} + +/** + * @brief This function configures some parameters of I2S interface for general purpose use. + * The sample rate may not be used from the parameter, it depends on system's clock settings, + * but real sample rate used by system will be returned for reference. + * @param[in] i2s is the base address of I2S module. + * @param[in] u32MasterSlave I2S operation mode. Valid values are: + * - \ref I2S_MODE_MASTER + * - \ref I2S_MODE_SLAVE + * @param[in] u32SampleRate Sample rate + * @param[in] u32WordWidth Data length. Valid values are: + * - \ref I2S_DATABIT_8 + * - \ref I2S_DATABIT_16 + * - \ref I2S_DATABIT_24 + * - \ref I2S_DATABIT_32 + * @param[in] u32MonoData: Set audio data to mono or not. Valid values are: + * - \ref I2S_ENABLE_MONO + * - \ref I2S_DISABLE_MONO + * @param[in] u32DataFormat: Data format. This is also used to select I2S or PCM(TDM) function. Valid values are: + * - \ref I2S_FORMAT_I2S + * - \ref I2S_FORMAT_I2S_MSB + * - \ref I2S_FORMAT_I2S_LSB + * - \ref I2S_FORMAT_PCM + * - \ref I2S_FORMAT_PCM_MSB + * - \ref I2S_FORMAT_PCM_LSB + * @return Real sample rate. + */ +uint32_t I2S_Open(I2S_T *i2s, uint32_t u32MasterSlave, uint32_t u32SampleRate, uint32_t u32WordWidth, uint32_t u32MonoData, uint32_t u32DataFormat) +{ + uint16_t u16Divider; + uint32_t u32BitRate, u32SrcClk; + + /* Reset I2S */ + if (i2s == I2S0) + { + SYS->IPRST1 |= SYS_IPRST1_I2S0RST_Msk; + SYS->IPRST1 &= ~SYS_IPRST1_I2S0RST_Msk; + } + else + { + SYS->IPRST3 |= SYS_IPRST3_I2S1RST_Msk; + SYS->IPRST3 &= ~SYS_IPRST3_I2S1RST_Msk; + } + + i2s->CTL0 = u32MasterSlave | u32WordWidth | u32MonoData | u32DataFormat; + i2s->CTL1 = I2S_FIFO_TX_LEVEL_WORD_8 | I2S_FIFO_RX_LEVEL_WORD_8; + + u32SrcClk = I2S_GetSourceClockFreq(i2s); + + u32BitRate = u32SampleRate * (((u32WordWidth >> 4U) & 0x3U) + 1U) * 16U; + //u16Divider = (uint16_t)((u32SrcClk/u32BitRate) >> 1U) - 1U; + u16Divider = (uint16_t)((((u32SrcClk * 10UL / u32BitRate) >> 1U) + 5UL) / 10UL) - 1U; + i2s->CLKDIV = (i2s->CLKDIV & ~I2S_CLKDIV_BCLKDIV_Msk) | ((uint32_t)u16Divider << 8U); + + /* calculate real sample rate */ + u32BitRate = u32SrcClk / (2U * ((uint32_t)u16Divider + 1U)); + u32SampleRate = u32BitRate / ((((u32WordWidth >> 4U) & 0x3U) + 1U) * 16U); + + i2s->CTL0 |= I2S_CTL0_I2SEN_Msk; + + return u32SampleRate; +} + +/** + * @brief Disable I2S function and I2S clock. + * @param[in] i2s is the base address of I2S module. + * @return none + */ +void I2S_Close(I2S_T *i2s) +{ + i2s->CTL0 &= ~I2S_CTL0_I2SEN_Msk; +} + +/** + * @brief This function enables the interrupt according to the mask parameter. + * @param[in] i2s is the base address of I2S module. + * @param[in] u32Mask is the combination of all related interrupt enable bits. + * Each bit corresponds to a interrupt bit. + * @return none + */ +void I2S_EnableInt(I2S_T *i2s, uint32_t u32Mask) +{ + i2s->IEN |= u32Mask; +} + +/** + * @brief This function disables the interrupt according to the mask parameter. + * @param[in] i2s is the base address of I2S module. + * @param[in] u32Mask is the combination of all related interrupt enable bits. + * Each bit corresponds to a interrupt bit. + * @return none + */ +void I2S_DisableInt(I2S_T *i2s, uint32_t u32Mask) +{ + i2s->IEN &= ~u32Mask; +} + +/** + * @brief Enable MCLK . + * @param[in] i2s is the base address of I2S module. + * @param[in] u32BusClock is the target MCLK clock + * @return Actual MCLK clock + */ +uint32_t I2S_EnableMCLK(I2S_T *i2s, uint32_t u32BusClock) +{ + uint8_t u8Divider; + uint32_t u32SrcClk, u32Reg, u32Clock; + + u32SrcClk = I2S_GetSourceClockFreq(i2s); + if (u32BusClock == u32SrcClk) + { + u8Divider = 0U; + } + else + { + u8Divider = (uint8_t)(u32SrcClk / u32BusClock) >> 1U; + } + + i2s->CLKDIV = (i2s->CLKDIV & ~I2S_CLKDIV_MCLKDIV_Msk) | u8Divider; + + i2s->CTL0 |= I2S_CTL0_MCLKEN_Msk; + + u32Reg = i2s->CLKDIV & I2S_CLKDIV_MCLKDIV_Msk; + + if (u32Reg == 0U) + { + u32Clock = u32SrcClk; + } + else + { + u32Clock = ((u32SrcClk >> 1U) / u32Reg); + } + + return u32Clock; +} + +/** + * @brief Disable MCLK . + * @param[in] i2s is the base address of I2S module. + * @return none + */ +void I2S_DisableMCLK(I2S_T *i2s) +{ + i2s->CTL0 &= ~I2S_CTL0_MCLKEN_Msk; +} + +/** + * @brief Configure FIFO threshold setting. + * @param[in] i2s The pointer of the specified I2S module. + * @param[in] u32TxThreshold Decides the TX FIFO threshold. It could be 0 ~ 7. + * @param[in] u32RxThreshold Decides the RX FIFO threshold. It could be 0 ~ 7. + * @return None + * @details Set TX FIFO threshold and RX FIFO threshold configurations. + */ +void I2S_SetFIFO(I2S_T *i2s, uint32_t u32TxThreshold, uint32_t u32RxThreshold) +{ + i2s->CTL1 = ((i2s->CTL1 & ~(I2S_CTL1_TXTH_Msk | I2S_CTL1_RXTH_Msk)) | + (u32TxThreshold << I2S_CTL1_TXTH_Pos) | + (u32RxThreshold << I2S_CTL1_RXTH_Pos)); +} + + +/** + * @brief Configure PCM(TDM) function parameters, such as channel width, channel number and sync pulse width + * @param[in] i2s The pointer of the specified I2S module. + * @param[in] u32ChannelWidth Channel width. Valid values are: + * - \ref I2S_TDM_WIDTH_8BIT + * - \ref I2S_TDM_WIDTH_16BIT + * - \ref I2S_TDM_WIDTH_24BIT + * - \ref I2S_TDM_WIDTH_32BIT + * @param[in] u32ChannelNum Channel number. Valid values are: + * - \ref I2S_TDM_2CH + * - \ref I2S_TDM_4CH + * - \ref I2S_TDM_6CH + * - \ref I2S_TDM_8CH + * @param[in] u32SyncWidth Width for sync pulse. Valid values are: + * - \ref I2S_TDM_SYNC_ONE_BCLK + * - \ref I2S_TDM_SYNC_ONE_CHANNEL + * @return None + * @details Set TX FIFO threshold and RX FIFO threshold configurations. + */ +void I2S_ConfigureTDM(I2S_T *i2s, uint32_t u32ChannelWidth, uint32_t u32ChannelNum, uint32_t u32SyncWidth) +{ + i2s->CTL0 = ((i2s->CTL0 & ~(I2S_CTL0_TDMCHNUM_Msk | I2S_CTL0_CHWIDTH_Msk | I2S_CTL0_PCMSYNC_Msk)) | + (u32ChannelWidth << I2S_CTL0_CHWIDTH_Pos) | + (u32ChannelNum << I2S_CTL0_TDMCHNUM_Pos) | + (u32SyncWidth << I2S_CTL0_PCMSYNC_Pos)); +} + +/*@}*/ /* end of group I2S_EXPORTED_FUNCTIONS */ + +/*@}*/ /* end of group I2S_Driver */ + +/*@}*/ /* end of group Standard_Driver */ + diff --git a/bsp/nuvoton/libraries/ma35/StdDriver/src/nu_kpi.c b/bsp/nuvoton/libraries/ma35/StdDriver/src/nu_kpi.c new file mode 100644 index 0000000000..435f43cc3e --- /dev/null +++ b/bsp/nuvoton/libraries/ma35/StdDriver/src/nu_kpi.c @@ -0,0 +1,135 @@ +/**************************************************************************//** + * @file kpi.c + * @brief KPI driver source file + * + * SPDX-License-Identifier: Apache-2.0 + * @copyright (C) 2020 Nuvoton Technology Corp. All rights reserved. + *****************************************************************************/ + +#include +#include "NuMicro.h" + +/** @addtogroup Standard_Driver Standard Driver + @{ +*/ + +/** @addtogroup KPI_Driver KPI Driver + @{ +*/ + +/** @addtogroup KPI_EXPORTED_FUNCTIONS KPI Exported Functions + @{ +*/ + + +/// @cond HIDDEN_SYMBOLS +#define KPICONF_VALUE 0x00288059 +/// @endcond HIDDEN_SYMBOLS + + +/** + * @brief Open KPI function. + * + * @return TRUE: Success \n + * FALSE: KPI function already open + * + */ +void KPI_Open(KPI_T *kpi, uint32_t u32Row, uint32_t u32Col) +{ + uint32_t u32Reg; + + kpi->KPICONF = 0x0; + kpi->KPI3KCONF = 0x0; + kpi->KPIRSTC = 0x0; + + if (u32Row < 2) + u32Row = 1; + else if (u32Row > 6) + u32Row = 6; + else + u32Row = u32Row - 1; + + if (u32Col < 2) + u32Col = 1; + else if (u32Col > 8) + u32Col = 8; + else + u32Col = u32Col - 1; + + u32Reg = (KPICONF_VALUE | (u32Row << 28) | (u32Col << 24)); + kpi->KPICONF = u32Reg; +} + +/** + * @brief Close KPI function. + * + * @return Successful: Success \n + * kpiNotOpen: KPI function not open + */ +void KPI_Close(KPI_T *kpi) +{ + kpi->KPICONF &= ~KPI_KPICONF_ENKP_Msk; +} + + +/** + * @brief Config KPI scan key timing. + * + * @param[in] u32PreScale: Row Scan Cycle Pre-scale Value. The divided number is from 1 to 256 + * @param[in] u32Debounce: De-bounce Sampling Cycle. The value is from 3 to 13 + * @param[in] u32ScanDelay: Setting delay cycle when row change: + * \ref KPI_ROW_SCAN_DELAY4CLK + * \ref KPI_ROW_SCAN_DELAY8CLK + * \ref KPI_ROW_SCAN_DELAY16CLK + * \ref KPI_ROW_SCAN_DELAY32CLK + * + * @return None + * + */ +void KPI_ConfigKeyScanTiming(KPI_T *kpi, uint32_t u32PreScale, uint32_t u32Debounce, uint32_t u32ScanDelay) +{ + if (u32Debounce < 3) u32Debounce = 3; + if (u32Debounce > 13) u32Debounce = 13; + + kpi->KPICONF &= ~(KPI_KPICONF_PRESCALE_Msk | KPI_KPICONF_DBCLKSEL_Msk | KPI_KPICONF_SCANROWD_Msk); + kpi->KPICONF |= (u32PreScale << KPI_KPICONF_PRESCALE_Pos) | (u32Debounce << KPI_KPICONF_DBCLKSEL_Pos) | + (u32ScanDelay << KPI_KPICONF_SCANROWD_Pos); +} + +/** + * @brief Read KPI Release key Status. + * + * @param[in] u32Key1: \ref KPI_KEY00 ~ \ref KPI_KEY58 + * @param[in] u32Key2: \ref KPI_KEY00 ~ \ref KPI_KEY58 + * @param[in] u32Key3: \ref KPI_KEY00 ~ \ref KPI_KEY58 + * @param[in] u32RSTC: Reset Period Count. The value is from 0 ~ 255. + * + * @return None + */ +void KPI_Set3KeyReset(KPI_T *kpi, uint32_t u32Key1, uint32_t u32Key2, uint32_t u32Key3, uint32_t u32RstCnt) +{ + kpi->KPI3KCONF &= ~(KPI_KPI3KCONF_K30C_Msk | KPI_KPI3KCONF_K30R_Msk | + KPI_KPI3KCONF_K31C_Msk | KPI_KPI3KCONF_K31R_Msk | + KPI_KPI3KCONF_K32C_Msk | KPI_KPI3KCONF_K32R_Msk); + + // Set Key + kpi->KPI3KCONF |= ((u32Key1 / 8) << 3) | (u32Key1 % 8); + kpi->KPI3KCONF |= ((((u32Key1 / 8) << 3) | (u32Key1 % 8)) << 8); + kpi->KPI3KCONF |= ((((u32Key1 / 8) << 3) | (u32Key1 % 16)) << 8); + + // Set Reset Period Count + kpi->KPIRSTC = u32RstCnt; + + // Enable 3Key Reset + kpi->KPI3KCONF |= KPI_KPI3KCONF_EN3KYRST_Msk; +} + +/*@}*/ /* end of group KPI_EXPORTED_FUNCTIONS */ + +/*@}*/ /* end of group KPI_Driver */ + +/*@}*/ /* end of group Standard_Driver */ + + + + diff --git a/bsp/nuvoton/libraries/ma35/StdDriver/src/nu_pdma.c b/bsp/nuvoton/libraries/ma35/StdDriver/src/nu_pdma.c new file mode 100644 index 0000000000..ff56e0ccb8 --- /dev/null +++ b/bsp/nuvoton/libraries/ma35/StdDriver/src/nu_pdma.c @@ -0,0 +1,443 @@ +/**************************************************************************//** + * @file pdma.c + * @brief PDMA driver source file + * + * SPDX-License-Identifier: Apache-2.0 + * @copyright (C) 2020 Nuvoton Technology Corp. All rights reserved. + *****************************************************************************/ +#include "NuMicro.h" + +/** @addtogroup Standard_Driver Standard Driver + @{ +*/ + +/** @addtogroup PDMA_Driver PDMA Driver + @{ +*/ + + +/** @addtogroup PDMA_EXPORTED_FUNCTIONS PDMA Exported Functions + @{ +*/ + +/** + * @brief PDMA Open + * + * @param[in] pdma The pointer of the specified PDMA module + * + * @param[in] u32Mask Channel enable bits. + * + * @return None + * + * @details This function enable the PDMA channels. + */ +void PDMA_Open(PDMA_T *pdma, uint32_t u32Mask) +{ + uint32_t i; + + for (i = 0UL; i < PDMA_CH_MAX; i++) + { + if ((1 << i) & u32Mask) + { + pdma->DSCT[i].CTL = 0UL; + } + } + + pdma->CHCTL |= u32Mask; +} + +/** + * @brief PDMA Close + * + * @param[in] pdma The pointer of the specified PDMA module + * + * @return None + * + * @details This function disable all PDMA channels. + */ +void PDMA_Close(PDMA_T *pdma) +{ + pdma->CHCTL = 0UL; +} + +/** + * @brief Set PDMA Transfer Count + * + * @param[in] pdma The pointer of the specified PDMA module + * @param[in] u32Ch The selected channel + * @param[in] u32Width Data width. Valid values are + * - \ref PDMA_WIDTH_8 + * - \ref PDMA_WIDTH_16 + * - \ref PDMA_WIDTH_32 + * @param[in] u32TransCount Transfer count + * + * @return None + * + * @details This function set the selected channel data width and transfer count. + */ +void PDMA_SetTransferCnt(PDMA_T *pdma, uint32_t u32Ch, uint32_t u32Width, uint32_t u32TransCount) +{ + pdma->DSCT[u32Ch].CTL &= ~(PDMA_DSCT_CTL_TXCNT_Msk | PDMA_DSCT_CTL_TXWIDTH_Msk); + pdma->DSCT[u32Ch].CTL |= (u32Width | ((u32TransCount - 1UL) << PDMA_DSCT_CTL_TXCNT_Pos)); +} + +/** + * @brief Set PDMA Stride Mode + * + * @param[in] pdma The pointer of the specified PDMA module + * @param[in] u32Ch The selected channel + * @param[in] u32DestLen Destination stride count + * @param[in] u32SrcLen Source stride count + * @param[in] u32TransCount Transfer count + * + * @return None + * + * @details This function set the selected stride mode. + */ +void PDMA_SetStride(PDMA_T *pdma, uint32_t u32Ch, uint32_t u32DestLen, uint32_t u32SrcLen, uint32_t u32TransCount) +{ + pdma->DSCT[u32Ch].CTL |= PDMA_DSCT_CTL_STRIDEEN_Msk; + pdma->STRIDE[u32Ch].ASOCR = ((u32DestLen - 1) << 16) | (u32SrcLen - 1); + pdma->STRIDE[u32Ch].STCR = u32TransCount - 1; +} + +/** + * @brief Set PDMA Repeat + * + * @param[in] pdma The pointer of the specified PDMA module + * @param[in] u32Ch The selected channel + * @param[in] u32DestInterval Destination address interval count + * @param[in] u32SrcInterval Source address interval count + * @param[in] u32RepeatCount Repeat count + * + * @return None + * + * @details This function set the selected repeat. + */ +void PDMA_SetRepeat(PDMA_T *pdma, uint32_t u32Ch, uint32_t u32DestInterval, uint32_t u32SrcInterval, uint32_t u32RepeatCount) +{ + pdma->DSCT[u32Ch].CTL |= PDMA_DSCT_CTL_STRIDEEN_Msk; + pdma->REPEAT[u32Ch].AICTL = ((u32DestInterval) << 16) | (u32SrcInterval); + pdma->REPEAT[u32Ch].RCNT = u32RepeatCount; +} + +/** + * @brief Set PDMA Transfer Address + * + * @param[in] pdma The pointer of the specified PDMA module + * @param[in] u32Ch The selected channel + * @param[in] u32SrcAddr Source address + * @param[in] u32SrcCtrl Source control attribute. Valid values are + * - \ref PDMA_SAR_INC + * - \ref PDMA_SAR_FIX + * @param[in] u32DstAddr destination address + * @param[in] u32DstCtrl destination control attribute. Valid values are + * - \ref PDMA_DAR_INC + * - \ref PDMA_DAR_FIX + * + * @return None + * + * @details This function set the selected channel source/destination address and attribute. + */ +void PDMA_SetTransferAddr(PDMA_T *pdma, uint32_t u32Ch, uint32_t u32SrcAddr, uint32_t u32SrcCtrl, uint32_t u32DstAddr, uint32_t u32DstCtrl) +{ + pdma->DSCT[u32Ch].SA = u32SrcAddr; + pdma->DSCT[u32Ch].DA = u32DstAddr; + pdma->DSCT[u32Ch].CTL &= ~(PDMA_DSCT_CTL_SAINC_Msk | PDMA_DSCT_CTL_DAINC_Msk); + pdma->DSCT[u32Ch].CTL |= (u32SrcCtrl | u32DstCtrl); +} + +/** + * @brief Set PDMA Transfer Mode + * + * @param[in] pdma The pointer of the specified PDMA module + * @param[in] u32Ch The selected channel + * @param[in] u32Peripheral The selected peripheral. Valid values are + * - \ref PDMA_MEM + * - \ref PDMA_USB_TX + * - \ref PDMA_USB_RX + * - \ref PDMA_UART0_TX + * - \ref PDMA_UART0_RX + * - \ref PDMA_UART1_TX + * - \ref PDMA_UART1_RX + * - \ref PDMA_UART2_TX + * - \ref PDMA_UART2_RX + * - \ref PDMA_UART3_TX + * - \ref PDMA_UART3_RX + * - \ref PDMA_UART4_TX + * - \ref PDMA_UART4_RX + * - \ref PDMA_UART5_TX + * - \ref PDMA_UART5_RX + * - \ref PDMA_USCI0_TX + * - \ref PDMA_USCI0_RX + * - \ref PDMA_USCI1_TX + * - \ref PDMA_USCI1_RX + * - \ref PDMA_QSPI0_TX + * - \ref PDMA_QSPI0_RX + * - \ref PDMA_SPI0_TX + * - \ref PDMA_SPI0_RX + * - \ref PDMA_SPI1_TX + * - \ref PDMA_SPI1_RX + * - \ref PDMA_SPI2_TX + * - \ref PDMA_SPI2_RX + * - \ref PDMA_SPI3_TX + * - \ref PDMA_SPI3_RX + * - \ref PDMA_EPWM0_P1_RX + * - \ref PDMA_EPWM0_P2_RX + * - \ref PDMA_EPWM0_P3_RX + * - \ref PDMA_EPWM1_P1_RX + * - \ref PDMA_EPWM1_P2_RX + * - \ref PDMA_EPWM1_P3_RX + * - \ref PDMA_I2C0_TX + * - \ref PDMA_I2C0_RX + * - \ref PDMA_I2C1_TX + * - \ref PDMA_I2C1_RX + * - \ref PDMA_I2C2_TX + * - \ref PDMA_I2C2_RX + * - \ref PDMA_I2S0_TX + * - \ref PDMA_I2S0_RX + * - \ref PDMA_TMR0 + * - \ref PDMA_TMR1 + * - \ref PDMA_TMR2 + * - \ref PDMA_TMR3 + * - \ref PDMA_EADC0_RX + * - \ref PDMA_DAC0_TX + * - \ref PDMA_DAC1_TX + * - \ref PDMA_EPWM0_CH0_TX + * - \ref PDMA_EPWM0_CH1_TX + * - \ref PDMA_EPWM0_CH2_TX + * - \ref PDMA_EPWM0_CH3_TX + * - \ref PDMA_EPWM0_CH4_TX + * - \ref PDMA_EPWM0_CH5_TX + * - \ref PDMA_EPWM1_CH0_TX + * - \ref PDMA_EPWM1_CH1_TX + * - \ref PDMA_EPWM1_CH2_TX + * - \ref PDMA_EPWM1_CH3_TX + * - \ref PDMA_EPWM1_CH4_TX + * - \ref PDMA_EPWM1_CH5_TX + * - \ref PDMA_UART6_TX + * - \ref PDMA_UART6_RX + * - \ref PDMA_UART7_TX + * - \ref PDMA_UART7_RX + * - \ref PDMA_EADC1_RX + * @param[in] u32ScatterEn Scatter-gather mode enable + * @param[in] u32DescAddr Scatter-gather descriptor address + * + * @return None + * + * @details This function set the selected channel transfer mode. Include peripheral setting. + */ +void PDMA_SetTransferMode(PDMA_T *pdma, uint32_t u32Ch, uint32_t u32Peripheral, uint32_t u32ScatterEn, uint32_t u32DescAddr) +{ + if (u32Ch < PDMA_CH_MAX) + { + __IO uint32_t *pau32REQSEL = (__IO uint32_t *)&pdma->REQSEL0_3; + uint32_t u32REQSEL_Pos, u32REQSEL_Msk; + + u32REQSEL_Pos = (u32Ch % 4) * 8 ; + u32REQSEL_Msk = PDMA_REQSEL0_3_REQSRC0_Msk << u32REQSEL_Pos; + pau32REQSEL[u32Ch / 4] = (pau32REQSEL[u32Ch / 4] & ~u32REQSEL_Msk) | (u32Peripheral << u32REQSEL_Pos); + + if (u32ScatterEn) + { + pdma->DSCT[u32Ch].CTL = (pdma->DSCT[u32Ch].CTL & ~PDMA_DSCT_CTL_OPMODE_Msk) | PDMA_OP_SCATTER; + pdma->DSCT[u32Ch].NEXT = u32DescAddr; + } + else + { + pdma->DSCT[u32Ch].CTL = (pdma->DSCT[u32Ch].CTL & ~PDMA_DSCT_CTL_OPMODE_Msk) | PDMA_OP_BASIC; + } + } + else {} +} + +/** + * @brief Set PDMA Burst Type and Size + * + * @param[in] pdma The pointer of the specified PDMA module + * @param[in] u32Ch The selected channel + * @param[in] u32BurstType Burst mode or single mode. Valid values are + * - \ref PDMA_REQ_SINGLE + * - \ref PDMA_REQ_BURST + * @param[in] u32BurstSize Set the size of burst mode. Valid values are + * - \ref PDMA_BURST_128 + * - \ref PDMA_BURST_64 + * - \ref PDMA_BURST_32 + * - \ref PDMA_BURST_16 + * - \ref PDMA_BURST_8 + * - \ref PDMA_BURST_4 + * - \ref PDMA_BURST_2 + * - \ref PDMA_BURST_1 + * + * @return None + * + * @details This function set the selected channel burst type and size. + */ +void PDMA_SetBurstType(PDMA_T *pdma, uint32_t u32Ch, uint32_t u32BurstType, uint32_t u32BurstSize) +{ + pdma->DSCT[u32Ch].CTL &= ~(PDMA_DSCT_CTL_TXTYPE_Msk | PDMA_DSCT_CTL_BURSIZE_Msk); + pdma->DSCT[u32Ch].CTL |= (u32BurstType | u32BurstSize); +} + +/** + * @brief Enable timeout function + * + * @param[in] pdma The pointer of the specified PDMA module + * + * @param[in] u32Mask Channel enable bits. + * + * @return None + * + * @details This function enable timeout function of the selected channel(s). + */ +void PDMA_EnableTimeout(PDMA_T *pdma, uint32_t u32Mask) +{ + pdma->TOUTEN |= u32Mask; +} + +/** + * @brief Disable timeout function + * + * @param[in] pdma The pointer of the specified PDMA module + * + * @param[in] u32Mask Channel enable bits. + * + * @return None + * + * @details This function disable timeout function of the selected channel(s). + */ +void PDMA_DisableTimeout(PDMA_T *pdma, uint32_t u32Mask) +{ + pdma->TOUTEN &= ~u32Mask; +} + +/** + * @brief Set PDMA Timeout Count + * + * @param[in] pdma The pointer of the specified PDMA module + * @param[in] u32Ch The selected channel, + * @param[in] u32OnOff Enable/disable time out function + * @param[in] u32TimeOutCnt Timeout count + * + * @return None + * + * @details This function set the timeout count. + */ +void PDMA_SetTimeOut(PDMA_T *pdma, uint32_t u32Ch, uint32_t u32OnOff, uint32_t u32TimeOutCnt) +{ + if (u32Ch < PDMA_CH_MAX) + { + __IO uint32_t *pau32TOC = (__IO uint32_t *)&pdma->TOC0_1; + uint32_t u32TOC_Pos, u32TOC_Msk; + + u32TOC_Pos = (u32Ch % 2) * 16 ; + u32TOC_Msk = PDMA_TOC0_1_TOC0_Msk << u32TOC_Pos; + pau32TOC[u32Ch / 2] = (pau32TOC[u32Ch / 2] & ~u32TOC_Msk) | (u32TimeOutCnt << u32TOC_Pos); + + if (u32OnOff) + pdma->TOUTEN |= (1 << u32Ch); + else + pdma->TOUTEN &= ~(1 << u32Ch); + } + else {} +} + +/** + * @brief Trigger PDMA + * + * @param[in] pdma The pointer of the specified PDMA module + * @param[in] u32Ch The selected channel + * + * @return None + * + * @details This function trigger the selected channel. + */ +void PDMA_Trigger(PDMA_T *pdma, uint32_t u32Ch) +{ + __IO uint32_t *pau32REQSEL = (__IO uint32_t *)&pdma->REQSEL0_3; + uint32_t u32REQSEL_Pos, u32REQSEL_Msk, u32ChReq; + + u32REQSEL_Pos = (u32Ch % 4) * 8 ; + u32REQSEL_Msk = PDMA_REQSEL0_3_REQSRC0_Msk << u32REQSEL_Pos; + + u32ChReq = (pau32REQSEL[u32Ch / 4] & u32REQSEL_Msk) >> u32REQSEL_Pos; + + if (u32ChReq == PDMA_MEM) + { + pdma->SWREQ = (1ul << u32Ch); + } + else {} +} + +/** + * @brief Enable Interrupt + * + * @param[in] pdma The pointer of the specified PDMA module + * @param[in] u32Ch The selected channel + * @param[in] u32Mask The Interrupt Type. Valid values are + * - \ref PDMA_INT_TRANS_DONE + * - \ref PDMA_INT_TEMPTY + * - \ref PDMA_INT_TIMEOUT + * + * @return None + * + * @details This function enable the selected channel interrupt. + */ +void PDMA_EnableInt(PDMA_T *pdma, uint32_t u32Ch, uint32_t u32Mask) +{ + switch (u32Mask) + { + case PDMA_INT_TRANS_DONE: + pdma->INTEN |= (1ul << u32Ch); + break; + case PDMA_INT_TEMPTY: + pdma->DSCT[u32Ch].CTL &= ~PDMA_DSCT_CTL_TBINTDIS_Msk; + break; + case PDMA_INT_TIMEOUT: + pdma->TOUTIEN |= (1ul << u32Ch); + break; + + default: + break; + } +} + +/** + * @brief Disable Interrupt + * + * @param[in] pdma The pointer of the specified PDMA module + * @param[in] u32Ch The selected channel + * @param[in] u32Mask The Interrupt Type. Valid values are + * - \ref PDMA_INT_TRANS_DONE + * - \ref PDMA_INT_TEMPTY + * - \ref PDMA_INT_TIMEOUT + * + * @return None + * + * @details This function disable the selected channel interrupt. + */ +void PDMA_DisableInt(PDMA_T *pdma, uint32_t u32Ch, uint32_t u32Mask) +{ + switch (u32Mask) + { + case PDMA_INT_TRANS_DONE: + pdma->INTEN &= ~(1ul << u32Ch); + break; + case PDMA_INT_TEMPTY: + pdma->DSCT[u32Ch].CTL |= PDMA_DSCT_CTL_TBINTDIS_Msk; + break; + case PDMA_INT_TIMEOUT: + pdma->TOUTIEN &= ~(1ul << u32Ch); + break; + + default: + break; + } +} + +/*@}*/ /* end of group PDMA_EXPORTED_FUNCTIONS */ + +/*@}*/ /* end of group PDMA_Driver */ + +/*@}*/ /* end of group Standard_Driver */ + diff --git a/bsp/nuvoton/libraries/ma35/StdDriver/src/nu_qei.c b/bsp/nuvoton/libraries/ma35/StdDriver/src/nu_qei.c new file mode 100644 index 0000000000..a4470a8975 --- /dev/null +++ b/bsp/nuvoton/libraries/ma35/StdDriver/src/nu_qei.c @@ -0,0 +1,122 @@ +/**************************************************************************//** + * @file qei.c + * @brief Quadrature Encoder Interface (QEI) driver source file + * + * SPDX-License-Identifier: Apache-2.0 + * @copyright (C) 2020 Nuvoton Technology Corp. All rights reserved. +*****************************************************************************/ +#include "NuMicro.h" + + +/** @addtogroup Standard_Driver Standard Driver + @{ +*/ + +/** @addtogroup QEI_Driver QEI Driver + @{ +*/ + +/** @addtogroup QEI_EXPORTED_FUNCTIONS QEI Exported Functions + @{ +*/ + +/** + * @brief Close QEI function + * @param[in] qei The pointer of the specified QEI module. + * @return None + * @details This function reset QEI configuration and stop QEI counting. + */ +void QEI_Close(QEI_T *qei) +{ + /* Reset QEI configuration */ + qei->CTL = (uint32_t)0; +} + +/** + * @brief Disable QEI interrupt + * @param[in] qei The pointer of the specified QEI module. + * @param[in] u32IntSel Interrupt type selection. + * - \ref QEI_CTL_DIRIEN_Msk : Direction change interrupt + * - \ref QEI_CTL_OVUNIEN_Msk : Counter overflow or underflow interrupt + * - \ref QEI_CTL_CMPIEN_Msk : Compare-match interrupt + * - \ref QEI_CTL_IDXIEN_Msk : Index detected interrupt + * @return None + * @details This function disable QEI specified interrupt. + */ +void QEI_DisableInt(QEI_T *qei, uint32_t u32IntSel) +{ + /* Disable QEI specified interrupt */ + QEI_DISABLE_INT(qei, u32IntSel); +} + +/** + * @brief Enable QEI interrupt + * @param[in] qei The pointer of the specified QEI module. + * @param[in] u32IntSel Interrupt type selection. + * - \ref QEI_CTL_DIRIEN_Msk : Direction change interrupt + * - \ref QEI_CTL_OVUNIEN_Msk : Counter overflow or underflow interrupt + * - \ref QEI_CTL_CMPIEN_Msk : Compare-match interrupt + * - \ref QEI_CTL_IDXIEN_Msk : Index detected interrupt + * @return None + * @details This function enable QEI specified interrupt. + */ +void QEI_EnableInt(QEI_T *qei, uint32_t u32IntSel) +{ + /* Enable QEI specified interrupt */ + QEI_ENABLE_INT(qei, u32IntSel); +} + +/** + * @brief Open QEI in specified mode and enable input + * @param[in] qei The pointer of the specified QEI module. + * @param[in] u32Mode QEI counting mode. + * - \ref QEI_CTL_X4_FREE_COUNTING_MODE + * - \ref QEI_CTL_X2_FREE_COUNTING_MODE + * - \ref QEI_CTL_X4_COMPARE_COUNTING_MODE + * - \ref QEI_CTL_X2_COMPARE_COUNTING_MODE + * @param[in] u32Value The counter maximum value in compare-counting mode. + * @return None + * @details This function set QEI in specified mode and enable input. + */ +void QEI_Open(QEI_T *qei, uint32_t u32Mode, uint32_t u32Value) +{ + /* Set QEI function configuration */ + /* Set QEI counting mode */ + /* Enable IDX, QEA and QEB input to QEI controller */ + qei->CTL = (qei->CTL & (~QEI_CTL_MODE_Msk)) | ((u32Mode) | QEI_CTL_CHAEN_Msk | QEI_CTL_CHBEN_Msk | QEI_CTL_IDXEN_Msk); + + /* Set QEI maximum count value in in compare-counting mode */ + qei->CNTMAX = u32Value; +} + +/** + * @brief Start QEI function + * @param[in] qei The pointer of the specified QEI module. + * @return None + * @details This function enable QEI function and start QEI counting. + */ +void QEI_Start(QEI_T *qei) +{ + /* Enable QEI controller function */ + qei->CTL |= QEI_CTL_QEIEN_Msk; +} + +/** + * @brief Stop QEI function + * @param[in] qei The pointer of the specified QEI module. + * @return None + * @details This function disable QEI function and stop QEI counting. + */ +void QEI_Stop(QEI_T *qei) +{ + /* Disable QEI controller function */ + qei->CTL &= (~QEI_CTL_QEIEN_Msk); +} + + +/*@}*/ /* end of group QEI_EXPORTED_FUNCTIONS */ + +/*@}*/ /* end of group QEI_Driver */ + +/*@}*/ /* end of group Standard_Driver */ + diff --git a/bsp/nuvoton/libraries/ma35/StdDriver/src/nu_qspi.c b/bsp/nuvoton/libraries/ma35/StdDriver/src/nu_qspi.c new file mode 100644 index 0000000000..e9a037a2e4 --- /dev/null +++ b/bsp/nuvoton/libraries/ma35/StdDriver/src/nu_qspi.c @@ -0,0 +1,788 @@ +/**************************************************************************//** + * @file qspi.c + * @brief QSPI driver source file + * + * SPDX-License-Identifier: Apache-2.0 + * @copyright (C) 2020 Nuvoton Technology Corp. All rights reserved. + *****************************************************************************/ +#include "NuMicro.h" + +/** @addtogroup Standard_Driver Standard Driver + @{ +*/ + +/** @addtogroup QSPI_Driver QSPI Driver + @{ +*/ + + +/** @addtogroup QSPI_EXPORTED_FUNCTIONS QSPI Exported Functions + @{ +*/ +static uint32_t QSPI_GetSrcClkSetting(QSPI_T *qspi); + +/** + * @brief This function make QSPI module be ready to transfer. + * @param[in] qspi The pointer of the specified QSPI module. + * @return Source clock frequency of QSPI peripheral. + * @details + * 0: APLL + * 1: PCLK0 + */ +static uint32_t QSPI_GetSrcClkSetting(QSPI_T *qspi) +{ + uint32_t u32ClkSrcFreq = 0UL, u32ClkSrcSel; + uint32_t u32ClkSelMsk = 0U, u32ClkSelPos = 0U; + + if (qspi == QSPI0) + { + u32ClkSelMsk = CLK_CLKSEL4_QSPI0SEL_Msk; + u32ClkSelPos = CLK_CLKSEL4_QSPI0SEL_Pos; + } + else if (qspi == QSPI1) + { + u32ClkSelMsk = CLK_CLKSEL4_QSPI1SEL_Msk; + u32ClkSelPos = CLK_CLKSEL4_QSPI1SEL_Pos; + } + else + { + goto Exit_QSPI_GetSrcClkSetting; + } + + u32ClkSrcSel = (CLK->CLKSEL4 & u32ClkSelMsk) >> u32ClkSelPos; + + switch (u32ClkSrcSel) + { + case 0x0U: + /* Clock source is PCLK0 */ + u32ClkSrcFreq = CLK_GetPCLK0Freq(); + break; + case 0x1U: + /* Clock source is APLL */ + u32ClkSrcFreq = CLK_GetPLLClockFreq(APLL); + break; + default: + break; + } + +Exit_QSPI_GetSrcClkSetting: + + return u32ClkSrcFreq; +} + +/** + * @brief This function make QSPI module be ready to transfer. + * @param[in] qspi The pointer of the specified QSPI module. + * @return None. + */ +static void QSPI_SetSrcClkToPCLK(QSPI_T *qspi) +{ + uint32_t u32ClkSelMsk = 0U, u32ClkSelPos = 0U; + + if (qspi == QSPI0) + { + u32ClkSelMsk = CLK_CLKSEL4_QSPI0SEL_Msk; + u32ClkSelPos = CLK_CLKSEL4_QSPI0SEL_Pos; + } + else if (qspi == QSPI1) + { + u32ClkSelMsk = CLK_CLKSEL4_QSPI1SEL_Msk; + u32ClkSelPos = CLK_CLKSEL4_QSPI1SEL_Pos; + } + + /* Select PCLK as the clock source of QSPI */ + CLK->CLKSEL4 = (CLK->CLKSEL4 & (~u32ClkSelMsk)) | (0x2UL << u32ClkSelPos); +} + +/** + * @brief This function make QSPI module be ready to transfer. + * @param[in] qspi The pointer of the specified QSPI module. + * @param[in] u32MasterSlave Decides the QSPI module is operating in master mode or in slave mode. (QSPI_SLAVE, QSPI_MASTER) + * @param[in] u32QSPIMode Decides the transfer timing. (QSPI_MODE_0, QSPI_MODE_1, QSPI_MODE_2, QSPI_MODE_3) + * @param[in] u32DataWidth Decides the data width of a QSPI transaction. + * @param[in] u32BusClock The expected frequency of QSPI bus clock in Hz. + * @return Actual frequency of QSPI peripheral clock. + * @details By default, the QSPI transfer sequence is MSB first, the slave selection signal is active low and the automatic + * slave selection function is disabled. + * In Slave mode, the u32BusClock shall be NULL and the QSPI clock divider setting will be 0. + * The actual clock rate may be different from the target QSPI clock rate. + * For example, if the QSPI source clock rate is 12 MHz and the target QSPI bus clock rate is 7 MHz, the + * actual QSPI clock rate will be 6MHz. + * @note If u32BusClock = 0, DIVIDER setting will be set to the maximum value. + * @note If u32BusClock >= system clock frequency, QSPI peripheral clock source will be set to APB clock and DIVIDER will be set to 0. + * @note If u32BusClock >= QSPI peripheral clock source, DIVIDER will be set to 0. + * @note In slave mode, the QSPI peripheral clock rate will be equal to APB clock rate. + */ +uint32_t QSPI_Open(QSPI_T *qspi, + uint32_t u32MasterSlave, + uint32_t u32QSPIMode, + uint32_t u32DataWidth, + uint32_t u32BusClock) +{ + uint32_t u32ClkSrcFreq = 0U, u32Div, u32HCLKFreq, u32RetValue = 0U; + + if (u32DataWidth == 32U) + { + u32DataWidth = 0U; + } + + + if (u32MasterSlave == QSPI_MASTER) + { + /* Default setting: slave selection signal is active low; disable automatic slave selection function. */ + qspi->SSCTL = QSPI_SS_ACTIVE_LOW; + + /* Default setting: MSB first, disable unit transfer interrupt, SP_CYCLE = 0. */ + qspi->CTL = u32MasterSlave | (u32DataWidth << QSPI_CTL_DWIDTH_Pos) | (u32QSPIMode) | QSPI_CTL_SPIEN_Msk; + + /* Get system clock frequency */ + u32HCLKFreq = CLK_GetSYSCLK0Freq(); + if (u32BusClock >= u32HCLKFreq) + { + /* Select PCLK as the clock source of QSPI */ + QSPI_SetSrcClkToPCLK(qspi); + } + + /* Check clock source of QSPI */ + u32ClkSrcFreq = QSPI_GetSrcClkSetting(qspi); + + if ((u32BusClock >= u32HCLKFreq) || (u32BusClock >= u32ClkSrcFreq)) + { + /* Set DIVIDER = 0 */ + qspi->CLKDIV = 0U; + /* Return master peripheral clock rate */ + u32RetValue = u32ClkSrcFreq; + } + else if (u32BusClock == 0U) + { + /* Set DIVIDER to the maximum value 0xFF. f_qspi = f_qspi_clk_src / (DIVIDER + 1) */ + qspi->CLKDIV |= QSPI_CLKDIV_DIVIDER_Msk; + /* Return master peripheral clock rate */ + u32RetValue = (u32ClkSrcFreq / (0xFFU + 1U)); + } + else + { + u32Div = (((u32ClkSrcFreq * 10U) / u32BusClock + 5U) / 10U) - 1U; /* Round to the nearest integer */ + if (u32Div > 0xFFU) + { + u32Div = 0xFFU; + qspi->CLKDIV |= QSPI_CLKDIV_DIVIDER_Msk; + /* Return master peripheral clock rate */ + u32RetValue = (u32ClkSrcFreq / (0xFFU + 1U)); + } + else + { + qspi->CLKDIV = (qspi->CLKDIV & (~QSPI_CLKDIV_DIVIDER_Msk)) | (u32Div << QSPI_CLKDIV_DIVIDER_Pos); + /* Return master peripheral clock rate */ + u32RetValue = (u32ClkSrcFreq / (u32Div + 1U)); + } + } + } + else /* For slave mode, force the QSPI peripheral clock rate to equal APB clock rate. */ + { + /* Default setting: slave selection signal is low level active. */ + qspi->SSCTL = QSPI_SS_ACTIVE_LOW; + + /* Default setting: MSB first, disable unit transfer interrupt, SP_CYCLE = 0. */ + qspi->CTL = u32MasterSlave | (u32DataWidth << QSPI_CTL_DWIDTH_Pos) | (u32QSPIMode) | QSPI_CTL_SPIEN_Msk; + + /* Set DIVIDER = 0 */ + qspi->CLKDIV = 0U; + + /* Select PCLK as the clock source of QSPI */ + QSPI_SetSrcClkToPCLK(qspi); + + /* Return slave peripheral clock rate */ + u32RetValue = CLK_GetPCLK0Freq(); + } + + return u32RetValue; +} + +/** + * @brief Disable QSPI controller. + * @param[in] qspi The pointer of the specified QSPI module. + * @return None + * @details This function will reset QSPI controller. + */ +void QSPI_Close(QSPI_T *qspi) +{ + /* Reset QSPI */ + if (qspi == QSPI0) + { + SYS->IPRST1 |= SYS_IPRST1_QSPI0RST_Msk; + SYS->IPRST1 &= ~SYS_IPRST1_QSPI0RST_Msk; + } + else + { + SYS->IPRST2 |= SYS_IPRST2_QSPI1RST_Msk; + SYS->IPRST2 &= ~SYS_IPRST2_QSPI1RST_Msk; + } +} + +/** + * @brief Clear RX FIFO buffer. + * @param[in] qspi The pointer of the specified QSPI module. + * @return None + * @details This function will clear QSPI RX FIFO buffer. The RXEMPTY (QSPI_STATUS[8]) will be set to 1. + */ +void QSPI_ClearRxFIFO(QSPI_T *qspi) +{ + qspi->FIFOCTL |= QSPI_FIFOCTL_RXFBCLR_Msk; +} + +/** + * @brief Clear TX FIFO buffer. + * @param[in] qspi The pointer of the specified QSPI module. + * @return None + * @details This function will clear QSPI TX FIFO buffer. The TXEMPTY (QSPI_STATUS[16]) will be set to 1. + * @note The TX shift register will not be cleared. + */ +void QSPI_ClearTxFIFO(QSPI_T *qspi) +{ + qspi->FIFOCTL |= QSPI_FIFOCTL_TXFBCLR_Msk; +} + +/** + * @brief Disable the automatic slave selection function. + * @param[in] qspi The pointer of the specified QSPI module. + * @return None + * @details This function will disable the automatic slave selection function and set slave selection signal to inactive state. + */ +void QSPI_DisableAutoSS(QSPI_T *qspi) +{ + qspi->SSCTL &= ~(QSPI_SSCTL_AUTOSS_Msk | QSPI_SSCTL_SS_Msk); +} + +/** + * @brief Enable the automatic slave selection function. + * @param[in] qspi The pointer of the specified QSPI module. + * @param[in] u32SSPinMask Specifies slave selection pins. (QSPI_SS) + * @param[in] u32ActiveLevel Specifies the active level of slave selection signal. (QSPI_SS_ACTIVE_HIGH, QSPI_SS_ACTIVE_LOW) + * @return None + * @details This function will enable the automatic slave selection function. Only available in Master mode. + * The slave selection pin and the active level will be set in this function. + */ +void QSPI_EnableAutoSS(QSPI_T *qspi, uint32_t u32SSPinMask, uint32_t u32ActiveLevel) +{ + qspi->SSCTL = (qspi->SSCTL & (~(QSPI_SSCTL_AUTOSS_Msk | QSPI_SSCTL_SSACTPOL_Msk | QSPI_SSCTL_SS_Msk))) | (u32SSPinMask | u32ActiveLevel | QSPI_SSCTL_AUTOSS_Msk); +} + +/** + * @brief Set the QSPI bus clock. + * @param[in] qspi The pointer of the specified QSPI module. + * @param[in] u32BusClock The expected frequency of QSPI bus clock in Hz. + * @return Actual frequency of QSPI bus clock. + * @details This function is only available in Master mode. The actual clock rate may be different from the target QSPI bus clock rate. + * For example, if the QSPI source clock rate is 12 MHz and the target QSPI bus clock rate is 7 MHz, the actual QSPI bus clock + * rate will be 6 MHz. + * @note If u32BusClock = 0, DIVIDER setting will be set to the maximum value. + * @note If u32BusClock >= system clock frequency, QSPI peripheral clock source will be set to APB clock and DIVIDER will be set to 0. + * @note If u32BusClock >= QSPI peripheral clock source, DIVIDER will be set to 0. + */ +uint32_t QSPI_SetBusClock(QSPI_T *qspi, uint32_t u32BusClock) +{ + uint32_t u32ClkSrcFreq, u32HCLKFreq; + uint32_t u32Div, u32RetValue; + + /* Get system clock frequency */ + u32HCLKFreq = CLK_GetSYSCLK0Freq(); + if (u32BusClock >= u32HCLKFreq) + { + /* Select PCLK as the clock source of QSPI */ + QSPI_SetSrcClkToPCLK(qspi); + } + + /* Check clock source of QSPI */ + u32ClkSrcFreq = QSPI_GetSrcClkSetting(qspi); + if (u32BusClock >= u32HCLKFreq) + { + /* Set DIVIDER = 0 */ + qspi->CLKDIV = 0U; + /* Return master peripheral clock rate */ + u32RetValue = u32ClkSrcFreq; + } + else if (u32BusClock >= u32ClkSrcFreq) + { + /* Set DIVIDER = 0 */ + qspi->CLKDIV = 0U; + /* Return master peripheral clock rate */ + u32RetValue = u32ClkSrcFreq; + } + else if (u32BusClock == 0U) + { + /* Set DIVIDER to the maximum value 0xFF. f_qspi = f_qspi_clk_src / (DIVIDER + 1) */ + qspi->CLKDIV |= QSPI_CLKDIV_DIVIDER_Msk; + /* Return master peripheral clock rate */ + u32RetValue = (u32ClkSrcFreq / (0xFFU + 1U)); + } + else + { + u32Div = (((u32ClkSrcFreq * 10U) / u32BusClock + 5U) / 10U) - 1U; /* Round to the nearest integer */ + if (u32Div > 0x1FFU) + { + u32Div = 0x1FFU; + qspi->CLKDIV |= QSPI_CLKDIV_DIVIDER_Msk; + /* Return master peripheral clock rate */ + u32RetValue = (u32ClkSrcFreq / (0xFFU + 1U)); + } + else + { + qspi->CLKDIV = (qspi->CLKDIV & (~QSPI_CLKDIV_DIVIDER_Msk)) | (u32Div << QSPI_CLKDIV_DIVIDER_Pos); + /* Return master peripheral clock rate */ + u32RetValue = (u32ClkSrcFreq / (u32Div + 1U)); + } + } + + return u32RetValue; +} + +/** + * @brief Configure FIFO threshold setting. + * @param[in] qspi The pointer of the specified QSPI module. + * @param[in] u32TxThreshold Decides the TX FIFO threshold. It could be 0 ~ 7. + * @param[in] u32RxThreshold Decides the RX FIFO threshold. It could be 0 ~ 7. + * @return None + * @details Set TX FIFO threshold and RX FIFO threshold configurations. + */ +void QSPI_SetFIFO(QSPI_T *qspi, uint32_t u32TxThreshold, uint32_t u32RxThreshold) +{ + qspi->FIFOCTL = (qspi->FIFOCTL & ~(QSPI_FIFOCTL_TXTH_Msk | QSPI_FIFOCTL_RXTH_Msk)) | + (u32TxThreshold << QSPI_FIFOCTL_TXTH_Pos) | + (u32RxThreshold << QSPI_FIFOCTL_RXTH_Pos); +} + +/** + * @brief Get the actual frequency of QSPI bus clock. Only available in Master mode. + * @param[in] qspi The pointer of the specified QSPI module. + * @return Actual QSPI bus clock frequency in Hz. + * @details This function will calculate the actual QSPI bus clock rate according to the QSPInSEL and DIVIDER settings. Only available in Master mode. + */ +uint32_t QSPI_GetBusClock(QSPI_T *qspi) +{ + uint32_t u32Div; + uint32_t u32ClkSrcFreq; + + /* Check clock source of QSPI */ + u32ClkSrcFreq = QSPI_GetSrcClkSetting(qspi); + + /* Get DIVIDER setting */ + u32Div = (qspi->CLKDIV & QSPI_CLKDIV_DIVIDER_Msk) >> QSPI_CLKDIV_DIVIDER_Pos; + + /* Return QSPI bus clock rate */ + return (u32ClkSrcFreq / (u32Div + 1U)); +} + +/** + * @brief Enable interrupt function. + * @param[in] qspi The pointer of the specified QSPI module. + * @param[in] u32Mask The combination of all related interrupt enable bits. + * Each bit corresponds to a interrupt enable bit. + * This parameter decides which interrupts will be enabled. It is combination of: + * - \ref QSPI_UNIT_INT_MASK + * - \ref QSPI_SSACT_INT_MASK + * - \ref QSPI_SSINACT_INT_MASK + * - \ref QSPI_SLVUR_INT_MASK + * - \ref QSPI_SLVBE_INT_MASK + * - \ref QSPI_TXUF_INT_MASK + * - \ref QSPI_FIFO_TXTH_INT_MASK + * - \ref QSPI_FIFO_RXTH_INT_MASK + * - \ref QSPI_FIFO_RXOV_INT_MASK + * - \ref QSPI_FIFO_RXTO_INT_MASK + * + * @return None + * @details Enable QSPI related interrupts specified by u32Mask parameter. + */ +void QSPI_EnableInt(QSPI_T *qspi, uint32_t u32Mask) +{ + /* Enable unit transfer interrupt flag */ + if ((u32Mask & QSPI_UNIT_INT_MASK) == QSPI_UNIT_INT_MASK) + { + qspi->CTL |= QSPI_CTL_UNITIEN_Msk; + } + + /* Enable slave selection signal active interrupt flag */ + if ((u32Mask & QSPI_SSACT_INT_MASK) == QSPI_SSACT_INT_MASK) + { + qspi->SSCTL |= QSPI_SSCTL_SSACTIEN_Msk; + } + + /* Enable slave selection signal inactive interrupt flag */ + if ((u32Mask & QSPI_SSINACT_INT_MASK) == QSPI_SSINACT_INT_MASK) + { + qspi->SSCTL |= QSPI_SSCTL_SSINAIEN_Msk; + } + + /* Enable slave TX under run interrupt flag */ + if ((u32Mask & QSPI_SLVUR_INT_MASK) == QSPI_SLVUR_INT_MASK) + { + qspi->SSCTL |= QSPI_SSCTL_SLVURIEN_Msk; + } + + /* Enable slave bit count error interrupt flag */ + if ((u32Mask & QSPI_SLVBE_INT_MASK) == QSPI_SLVBE_INT_MASK) + { + qspi->SSCTL |= QSPI_SSCTL_SLVBEIEN_Msk; + } + + /* Enable slave TX underflow interrupt flag */ + if ((u32Mask & QSPI_TXUF_INT_MASK) == QSPI_TXUF_INT_MASK) + { + qspi->FIFOCTL |= QSPI_FIFOCTL_TXUFIEN_Msk; + } + + /* Enable TX threshold interrupt flag */ + if ((u32Mask & QSPI_FIFO_TXTH_INT_MASK) == QSPI_FIFO_TXTH_INT_MASK) + { + qspi->FIFOCTL |= QSPI_FIFOCTL_TXTHIEN_Msk; + } + + /* Enable RX threshold interrupt flag */ + if ((u32Mask & QSPI_FIFO_RXTH_INT_MASK) == QSPI_FIFO_RXTH_INT_MASK) + { + qspi->FIFOCTL |= QSPI_FIFOCTL_RXTHIEN_Msk; + } + + /* Enable RX overrun interrupt flag */ + if ((u32Mask & QSPI_FIFO_RXOV_INT_MASK) == QSPI_FIFO_RXOV_INT_MASK) + { + qspi->FIFOCTL |= QSPI_FIFOCTL_RXOVIEN_Msk; + } + + /* Enable RX time-out interrupt flag */ + if ((u32Mask & QSPI_FIFO_RXTO_INT_MASK) == QSPI_FIFO_RXTO_INT_MASK) + { + qspi->FIFOCTL |= QSPI_FIFOCTL_RXTOIEN_Msk; + } +} + +/** + * @brief Disable interrupt function. + * @param[in] qspi The pointer of the specified QSPI module. + * @param[in] u32Mask The combination of all related interrupt enable bits. + * Each bit corresponds to a interrupt bit. + * This parameter decides which interrupts will be disabled. It is combination of: + * - \ref QSPI_UNIT_INT_MASK + * - \ref QSPI_SSACT_INT_MASK + * - \ref QSPI_SSINACT_INT_MASK + * - \ref QSPI_SLVUR_INT_MASK + * - \ref QSPI_SLVBE_INT_MASK + * - \ref QSPI_TXUF_INT_MASK + * - \ref QSPI_FIFO_TXTH_INT_MASK + * - \ref QSPI_FIFO_RXTH_INT_MASK + * - \ref QSPI_FIFO_RXOV_INT_MASK + * - \ref QSPI_FIFO_RXTO_INT_MASK + * + * @return None + * @details Disable QSPI related interrupts specified by u32Mask parameter. + */ +void QSPI_DisableInt(QSPI_T *qspi, uint32_t u32Mask) +{ + /* Disable unit transfer interrupt flag */ + if ((u32Mask & QSPI_UNIT_INT_MASK) == QSPI_UNIT_INT_MASK) + { + qspi->CTL &= ~QSPI_CTL_UNITIEN_Msk; + } + + /* Disable slave selection signal active interrupt flag */ + if ((u32Mask & QSPI_SSACT_INT_MASK) == QSPI_SSACT_INT_MASK) + { + qspi->SSCTL &= ~QSPI_SSCTL_SSACTIEN_Msk; + } + + /* Disable slave selection signal inactive interrupt flag */ + if ((u32Mask & QSPI_SSINACT_INT_MASK) == QSPI_SSINACT_INT_MASK) + { + qspi->SSCTL &= ~QSPI_SSCTL_SSINAIEN_Msk; + } + + /* Disable slave TX under run interrupt flag */ + if ((u32Mask & QSPI_SLVUR_INT_MASK) == QSPI_SLVUR_INT_MASK) + { + qspi->SSCTL &= ~QSPI_SSCTL_SLVURIEN_Msk; + } + + /* Disable slave bit count error interrupt flag */ + if ((u32Mask & QSPI_SLVBE_INT_MASK) == QSPI_SLVBE_INT_MASK) + { + qspi->SSCTL &= ~QSPI_SSCTL_SLVBEIEN_Msk; + } + + /* Disable slave TX underflow interrupt flag */ + if ((u32Mask & QSPI_TXUF_INT_MASK) == QSPI_TXUF_INT_MASK) + { + qspi->FIFOCTL &= ~QSPI_FIFOCTL_TXUFIEN_Msk; + } + + /* Disable TX threshold interrupt flag */ + if ((u32Mask & QSPI_FIFO_TXTH_INT_MASK) == QSPI_FIFO_TXTH_INT_MASK) + { + qspi->FIFOCTL &= ~QSPI_FIFOCTL_TXTHIEN_Msk; + } + + /* Disable RX threshold interrupt flag */ + if ((u32Mask & QSPI_FIFO_RXTH_INT_MASK) == QSPI_FIFO_RXTH_INT_MASK) + { + qspi->FIFOCTL &= ~QSPI_FIFOCTL_RXTHIEN_Msk; + } + + /* Disable RX overrun interrupt flag */ + if ((u32Mask & QSPI_FIFO_RXOV_INT_MASK) == QSPI_FIFO_RXOV_INT_MASK) + { + qspi->FIFOCTL &= ~QSPI_FIFOCTL_RXOVIEN_Msk; + } + + /* Disable RX time-out interrupt flag */ + if ((u32Mask & QSPI_FIFO_RXTO_INT_MASK) == QSPI_FIFO_RXTO_INT_MASK) + { + qspi->FIFOCTL &= ~QSPI_FIFOCTL_RXTOIEN_Msk; + } +} + +/** + * @brief Get interrupt flag. + * @param[in] qspi The pointer of the specified QSPI module. + * @param[in] u32Mask The combination of all related interrupt sources. + * Each bit corresponds to a interrupt source. + * This parameter decides which interrupt flags will be read. It is combination of: + * - \ref QSPI_UNIT_INT_MASK + * - \ref QSPI_SSACT_INT_MASK + * - \ref QSPI_SSINACT_INT_MASK + * - \ref QSPI_SLVUR_INT_MASK + * - \ref QSPI_SLVBE_INT_MASK + * - \ref QSPI_TXUF_INT_MASK + * - \ref QSPI_FIFO_TXTH_INT_MASK + * - \ref QSPI_FIFO_RXTH_INT_MASK + * - \ref QSPI_FIFO_RXOV_INT_MASK + * - \ref QSPI_FIFO_RXTO_INT_MASK + * + * @return Interrupt flags of selected sources. + * @details Get QSPI related interrupt flags specified by u32Mask parameter. + */ +uint32_t QSPI_GetIntFlag(QSPI_T *qspi, uint32_t u32Mask) +{ + uint32_t u32IntFlag = 0U, u32TmpVal; + + u32TmpVal = qspi->STATUS & QSPI_STATUS_UNITIF_Msk; + /* Check unit transfer interrupt flag */ + if ((u32Mask & QSPI_UNIT_INT_MASK) && (u32TmpVal)) + { + u32IntFlag |= QSPI_UNIT_INT_MASK; + } + + u32TmpVal = qspi->STATUS & QSPI_STATUS_SSACTIF_Msk; + /* Check slave selection signal active interrupt flag */ + if ((u32Mask & QSPI_SSACT_INT_MASK) && (u32TmpVal)) + { + u32IntFlag |= QSPI_SSACT_INT_MASK; + } + + u32TmpVal = qspi->STATUS & QSPI_STATUS_SSINAIF_Msk; + /* Check slave selection signal inactive interrupt flag */ + if ((u32Mask & QSPI_SSINACT_INT_MASK) && (u32TmpVal)) + { + u32IntFlag |= QSPI_SSINACT_INT_MASK; + } + + u32TmpVal = qspi->STATUS & QSPI_STATUS_SLVURIF_Msk; + /* Check slave TX under run interrupt flag */ + if ((u32Mask & QSPI_SLVUR_INT_MASK) && (u32TmpVal)) + { + u32IntFlag |= QSPI_SLVUR_INT_MASK; + } + + u32TmpVal = qspi->STATUS & QSPI_STATUS_SLVBEIF_Msk; + /* Check slave bit count error interrupt flag */ + if ((u32Mask & QSPI_SLVBE_INT_MASK) && (u32TmpVal)) + { + u32IntFlag |= QSPI_SLVBE_INT_MASK; + } + + u32TmpVal = qspi->STATUS & QSPI_STATUS_TXUFIF_Msk; + /* Check slave TX underflow interrupt flag */ + if ((u32Mask & QSPI_TXUF_INT_MASK) && (u32TmpVal)) + { + u32IntFlag |= QSPI_TXUF_INT_MASK; + } + + u32TmpVal = qspi->STATUS & QSPI_STATUS_TXTHIF_Msk; + /* Check TX threshold interrupt flag */ + if ((u32Mask & QSPI_FIFO_TXTH_INT_MASK) && (u32TmpVal)) + { + u32IntFlag |= QSPI_FIFO_TXTH_INT_MASK; + } + + u32TmpVal = qspi->STATUS & QSPI_STATUS_RXTHIF_Msk; + /* Check RX threshold interrupt flag */ + if ((u32Mask & QSPI_FIFO_RXTH_INT_MASK) && (u32TmpVal)) + { + u32IntFlag |= QSPI_FIFO_RXTH_INT_MASK; + } + + u32TmpVal = qspi->STATUS & QSPI_STATUS_RXOVIF_Msk; + /* Check RX overrun interrupt flag */ + if ((u32Mask & QSPI_FIFO_RXOV_INT_MASK) && (u32TmpVal)) + { + u32IntFlag |= QSPI_FIFO_RXOV_INT_MASK; + } + + u32TmpVal = qspi->STATUS & QSPI_STATUS_RXTOIF_Msk; + /* Check RX time-out interrupt flag */ + if ((u32Mask & QSPI_FIFO_RXTO_INT_MASK) && (u32TmpVal)) + { + u32IntFlag |= QSPI_FIFO_RXTO_INT_MASK; + } + + return u32IntFlag; +} + +/** + * @brief Clear interrupt flag. + * @param[in] qspi The pointer of the specified QSPI module. + * @param[in] u32Mask The combination of all related interrupt sources. + * Each bit corresponds to a interrupt source. + * This parameter decides which interrupt flags will be cleared. It could be the combination of: + * - \ref QSPI_UNIT_INT_MASK + * - \ref QSPI_SSACT_INT_MASK + * - \ref QSPI_SSINACT_INT_MASK + * - \ref QSPI_SLVUR_INT_MASK + * - \ref QSPI_SLVBE_INT_MASK + * - \ref QSPI_TXUF_INT_MASK + * - \ref QSPI_FIFO_RXOV_INT_MASK + * - \ref QSPI_FIFO_RXTO_INT_MASK + * + * @return None + * @details Clear QSPI related interrupt flags specified by u32Mask parameter. + */ +void QSPI_ClearIntFlag(QSPI_T *qspi, uint32_t u32Mask) +{ + if (u32Mask & QSPI_UNIT_INT_MASK) + { + qspi->STATUS = QSPI_STATUS_UNITIF_Msk; /* Clear unit transfer interrupt flag */ + } + + if (u32Mask & QSPI_SSACT_INT_MASK) + { + qspi->STATUS = QSPI_STATUS_SSACTIF_Msk; /* Clear slave selection signal active interrupt flag */ + } + + if (u32Mask & QSPI_SSINACT_INT_MASK) + { + qspi->STATUS = QSPI_STATUS_SSINAIF_Msk; /* Clear slave selection signal inactive interrupt flag */ + } + + if (u32Mask & QSPI_SLVUR_INT_MASK) + { + qspi->STATUS = QSPI_STATUS_SLVURIF_Msk; /* Clear slave TX under run interrupt flag */ + } + + if (u32Mask & QSPI_SLVBE_INT_MASK) + { + qspi->STATUS = QSPI_STATUS_SLVBEIF_Msk; /* Clear slave bit count error interrupt flag */ + } + + if (u32Mask & QSPI_TXUF_INT_MASK) + { + qspi->STATUS = QSPI_STATUS_TXUFIF_Msk; /* Clear slave TX underflow interrupt flag */ + } + + if (u32Mask & QSPI_FIFO_RXOV_INT_MASK) + { + qspi->STATUS = QSPI_STATUS_RXOVIF_Msk; /* Clear RX overrun interrupt flag */ + } + + if (u32Mask & QSPI_FIFO_RXTO_INT_MASK) + { + qspi->STATUS = QSPI_STATUS_RXTOIF_Msk; /* Clear RX time-out interrupt flag */ + } +} + +/** + * @brief Get QSPI status. + * @param[in] qspi The pointer of the specified QSPI module. + * @param[in] u32Mask The combination of all related sources. + * Each bit corresponds to a source. + * This parameter decides which flags will be read. It is combination of: + * - \ref QSPI_BUSY_MASK + * - \ref QSPI_RX_EMPTY_MASK + * - \ref QSPI_RX_FULL_MASK + * - \ref QSPI_TX_EMPTY_MASK + * - \ref QSPI_TX_FULL_MASK + * - \ref QSPI_TXRX_RESET_MASK + * - \ref QSPI_QSPIEN_STS_MASK + * - \ref QSPI_SSLINE_STS_MASK + * + * @return Flags of selected sources. + * @details Get QSPI related status specified by u32Mask parameter. + */ +uint32_t QSPI_GetStatus(QSPI_T *qspi, uint32_t u32Mask) +{ + uint32_t u32Flag = 0U, u32TmpValue; + + u32TmpValue = qspi->STATUS & QSPI_STATUS_BUSY_Msk; + /* Check busy status */ + if ((u32Mask & QSPI_BUSY_MASK) && (u32TmpValue)) + { + u32Flag |= QSPI_BUSY_MASK; + } + + u32TmpValue = qspi->STATUS & QSPI_STATUS_RXEMPTY_Msk; + /* Check RX empty flag */ + if ((u32Mask & QSPI_RX_EMPTY_MASK) && (u32TmpValue)) + { + u32Flag |= QSPI_RX_EMPTY_MASK; + } + + u32TmpValue = qspi->STATUS & QSPI_STATUS_RXFULL_Msk; + /* Check RX full flag */ + if ((u32Mask & QSPI_RX_FULL_MASK) && (u32TmpValue)) + { + u32Flag |= QSPI_RX_FULL_MASK; + } + + u32TmpValue = qspi->STATUS & QSPI_STATUS_TXEMPTY_Msk; + /* Check TX empty flag */ + if ((u32Mask & QSPI_TX_EMPTY_MASK) && (u32TmpValue)) + { + u32Flag |= QSPI_TX_EMPTY_MASK; + } + + u32TmpValue = qspi->STATUS & QSPI_STATUS_TXFULL_Msk; + /* Check TX full flag */ + if ((u32Mask & QSPI_TX_FULL_MASK) && (u32TmpValue)) + { + u32Flag |= QSPI_TX_FULL_MASK; + } + + u32TmpValue = qspi->STATUS & QSPI_STATUS_TXRXRST_Msk; + /* Check TX/RX reset flag */ + if ((u32Mask & QSPI_TXRX_RESET_MASK) && (u32TmpValue)) + { + u32Flag |= QSPI_TXRX_RESET_MASK; + } + + u32TmpValue = qspi->STATUS & QSPI_STATUS_SPIENSTS_Msk; + /* Check QSPIEN flag */ + if ((u32Mask & QSPI_QSPIEN_STS_MASK) && (u32TmpValue)) + { + u32Flag |= QSPI_QSPIEN_STS_MASK; + } + + u32TmpValue = qspi->STATUS & QSPI_STATUS_SSLINE_Msk; + /* Check QSPIx_SS line status */ + if ((u32Mask & QSPI_SSLINE_STS_MASK) && (u32TmpValue)) + { + u32Flag |= QSPI_SSLINE_STS_MASK; + } + + return u32Flag; +} + + + +/*@}*/ /* end of group QSPI_EXPORTED_FUNCTIONS */ + +/*@}*/ /* end of group QSPI_Driver */ + +/*@}*/ /* end of group Standard_Driver */ + diff --git a/bsp/nuvoton/libraries/ma35/StdDriver/src/nu_rtc.c b/bsp/nuvoton/libraries/ma35/StdDriver/src/nu_rtc.c new file mode 100644 index 0000000000..4f16700b96 --- /dev/null +++ b/bsp/nuvoton/libraries/ma35/StdDriver/src/nu_rtc.c @@ -0,0 +1,731 @@ +/**************************************************************************//** + * @file rtc.c + * @brief RTC driver source file + * + * SPDX-License-Identifier: Apache-2.0 + * @copyright (C) 2020 Nuvoton Technology Corp. All rights reserved. + *****************************************************************************/ +#include "NuMicro.h" + + +/** @cond HIDDEN_SYMBOLS */ + +/*---------------------------------------------------------------------------------------------------------*/ +/* Macro, type and constant definitions */ +/*---------------------------------------------------------------------------------------------------------*/ +#define RTC_GLOBALS + +/*---------------------------------------------------------------------------------------------------------*/ +/* Global file scope (static) variables */ +/*---------------------------------------------------------------------------------------------------------*/ +static volatile uint32_t g_u32hiYear, g_u32loYear, g_u32hiMonth, g_u32loMonth, g_u32hiDay, g_u32loDay; +static volatile uint32_t g_u32hiHour, g_u32loHour, g_u32hiMin, g_u32loMin, g_u32hiSec, g_u32loSec; + +/** @endcond HIDDEN_SYMBOLS */ + + + + +/** @addtogroup Standard_Driver Standard Driver + @{ +*/ + +/** @addtogroup RTC_Driver RTC Driver + @{ +*/ + +/** @addtogroup RTC_EXPORTED_FUNCTIONS RTC Exported Functions + @{ +*/ + +/** + * @brief Initialize RTC module and start counting + * + * @param[in] sPt Specify the time property and current date and time. It includes: \n + * u32Year: Year value, range between 2000 ~ 2099. \n + * u32Month: Month value, range between 1 ~ 12. \n + * u32Day: Day value, range between 1 ~ 31. \n + * u32DayOfWeek: Day of the week. [RTC_SUNDAY / RTC_MONDAY / RTC_TUESDAY / + * RTC_WEDNESDAY / RTC_THURSDAY / RTC_FRIDAY / + * RTC_SATURDAY] \n + * u32Hour: Hour value, range between 0 ~ 23. \n + * u32Minute: Minute value, range between 0 ~ 59. \n + * u32Second: Second value, range between 0 ~ 59. \n + * u32TimeScale: [RTC_CLOCK_12 / RTC_CLOCK_24] \n + * u8AmPm: [RTC_AM / RTC_PM] \n + * + * @return None + * + * @details This function is used to: \n + * 1. Write initial key to let RTC start count. \n + * 2. Input parameter indicates start date/time. \n + * 3. User has to make sure that parameters of RTC date/time are reasonable. \n + * @note Null pointer for using default starting date/time. + */ +int32_t RTC_Open(S_RTC_TIME_DATA_T *sPt) +{ + RTC->INIT = RTC_INIT_KEY; + if (RTC->INIT != RTC_INIT_ACTIVE_Msk) + { + uint32_t u32Timeout = 10000000ul; + + RTC->INIT = RTC_INIT_KEY; + while ((u32Timeout > 0) && (RTC->INIT != RTC_INIT_ACTIVE_Msk)) + { + u32Timeout--; + } + if (u32Timeout == 0) return -1; + } + + if (sPt == 0) + { + } + else + { + /* Set RTC date and time */ + RTC_SetDateAndTime(sPt); + } + return 0; +} + +/** + * @brief Disable RTC Clock + * + * @param None + * + * @return None + * + * @details This API will disable RTC peripheral clock and stops RTC counting. + */ +void RTC_Close(void) +{ + CLK->APBCLK0 &= ~CLK_APBCLK0_RTCCKEN_Msk; +} + +/** + * @brief Get Current RTC Date and Time + * + * @param[out] sPt The returned pointer is specified the current RTC value. It includes: \n + * u32Year: Year value \n + * u32Month: Month value \n + * u32Day: Day value \n + * u32DayOfWeek: Day of week \n + * u32Hour: Hour value \n + * u32Minute: Minute value \n + * u32Second: Second value \n + * u32TimeScale: [RTC_CLOCK_12 / RTC_CLOCK_24] \n + * u8AmPm: [RTC_AM / RTC_PM] \n + * + * @return None + * + * @details This API is used to get the current RTC date and time value. + */ +void RTC_GetDateAndTime(S_RTC_TIME_DATA_T *sPt) +{ + uint32_t u32Tmp; + + sPt->u32TimeScale = RTC->CLKFMT & RTC_CLKFMT_24HEN_Msk; /* 12/24-hour */ + sPt->u32DayOfWeek = RTC->WEEKDAY & RTC_WEEKDAY_WEEKDAY_Msk; /* Day of the week */ + + /* Get [Date digit] data */ + g_u32hiYear = (RTC->CAL & RTC_CAL_TENYEAR_Msk) >> RTC_CAL_TENYEAR_Pos; + g_u32loYear = (RTC->CAL & RTC_CAL_YEAR_Msk) >> RTC_CAL_YEAR_Pos; + g_u32hiMonth = (RTC->CAL & RTC_CAL_TENMON_Msk) >> RTC_CAL_TENMON_Pos; + g_u32loMonth = (RTC->CAL & RTC_CAL_MON_Msk) >> RTC_CAL_MON_Pos; + g_u32hiDay = (RTC->CAL & RTC_CAL_TENDAY_Msk) >> RTC_CAL_TENDAY_Pos; + g_u32loDay = (RTC->CAL & RTC_CAL_DAY_Msk) >> RTC_CAL_DAY_Pos; + + /* Get [Time digit] data */ + g_u32hiHour = (RTC->TIME & RTC_TIME_TENHR_Msk) >> RTC_TIME_TENHR_Pos; + g_u32loHour = (RTC->TIME & RTC_TIME_HR_Msk) >> RTC_TIME_HR_Pos; + g_u32hiMin = (RTC->TIME & RTC_TIME_TENMIN_Msk) >> RTC_TIME_TENMIN_Pos; + g_u32loMin = (RTC->TIME & RTC_TIME_MIN_Msk) >> RTC_TIME_MIN_Pos; + g_u32hiSec = (RTC->TIME & RTC_TIME_TENSEC_Msk) >> RTC_TIME_TENSEC_Pos; + g_u32loSec = (RTC->TIME & RTC_TIME_SEC_Msk) >> RTC_TIME_SEC_Pos; + + /* Compute to 20XX year */ + u32Tmp = (g_u32hiYear * 10ul); + u32Tmp += g_u32loYear; + sPt->u32Year = u32Tmp + RTC_YEAR2000; + + /* Compute 0~12 month */ + u32Tmp = (g_u32hiMonth * 10ul); + sPt->u32Month = u32Tmp + g_u32loMonth; + + /* Compute 0~31 day */ + u32Tmp = (g_u32hiDay * 10ul); + sPt->u32Day = u32Tmp + g_u32loDay; + + /* Compute 12/24 hour */ + if (sPt->u32TimeScale == RTC_CLOCK_12) + { + u32Tmp = (g_u32hiHour * 10ul); + u32Tmp += g_u32loHour; + sPt->u32Hour = u32Tmp; /* AM: 1~12. PM: 21~32. */ + + if (sPt->u32Hour >= 21ul) + { + sPt->u32AmPm = RTC_PM; + sPt->u32Hour -= 20ul; + } + else + { + sPt->u32AmPm = RTC_AM; + } + + u32Tmp = (g_u32hiMin * 10ul); + u32Tmp += g_u32loMin; + sPt->u32Minute = u32Tmp; + + u32Tmp = (g_u32hiSec * 10ul); + u32Tmp += g_u32loSec; + sPt->u32Second = u32Tmp; + } + else + { + u32Tmp = (g_u32hiHour * 10ul); + u32Tmp += g_u32loHour; + sPt->u32Hour = u32Tmp; + + u32Tmp = (g_u32hiMin * 10ul); + u32Tmp += g_u32loMin; + sPt->u32Minute = u32Tmp; + + u32Tmp = (g_u32hiSec * 10ul); + u32Tmp += g_u32loSec; + sPt->u32Second = u32Tmp; + } +} + +/** + * @brief Get RTC Alarm Date and Time + * + * @param[out] sPt The returned pointer is specified the RTC alarm value. It includes: \n + * u32Year: Year value \n + * u32Month: Month value \n + * u32Day: Day value \n + * u32DayOfWeek: Day of week \n + * u32Hour: Hour value \n + * u32Minute: Minute value \n + * u32Second: Second value \n + * u32TimeScale: [RTC_CLOCK_12 / RTC_CLOCK_24] \n + * u8AmPm: [RTC_AM / RTC_PM] \n + * + * @return None + * + * @details This API is used to get the RTC alarm date and time setting. + */ +void RTC_GetAlarmDateAndTime(S_RTC_TIME_DATA_T *sPt) +{ + uint32_t u32Tmp; + + sPt->u32TimeScale = RTC->CLKFMT & RTC_CLKFMT_24HEN_Msk; /* 12/24-hour */ + sPt->u32DayOfWeek = RTC->WEEKDAY & RTC_WEEKDAY_WEEKDAY_Msk; /* Day of the week */ + + /* Get alarm [Date digit] data */ + g_u32hiYear = (REG_RTC_CALM & RTC_CALM_TENYEAR_Msk) >> RTC_CALM_TENYEAR_Pos; + g_u32loYear = (REG_RTC_CALM & RTC_CALM_YEAR_Msk) >> RTC_CALM_YEAR_Pos; + g_u32hiMonth = (REG_RTC_CALM & RTC_CALM_TENMON_Msk) >> RTC_CALM_TENMON_Pos; + g_u32loMonth = (REG_RTC_CALM & RTC_CALM_MON_Msk) >> RTC_CALM_MON_Pos; + g_u32hiDay = (REG_RTC_CALM & RTC_CALM_TENDAY_Msk) >> RTC_CALM_TENDAY_Pos; + g_u32loDay = (REG_RTC_CALM & RTC_CALM_DAY_Msk) >> RTC_CALM_DAY_Pos; + + /* Get alarm [Time digit] data */ + g_u32hiHour = (REG_RTC_TALM & RTC_TALM_TENHR_Msk) >> RTC_TALM_TENHR_Pos; + g_u32loHour = (REG_RTC_TALM & RTC_TALM_HR_Msk) >> RTC_TALM_HR_Pos; + g_u32hiMin = (REG_RTC_TALM & RTC_TALM_TENMIN_Msk) >> RTC_TALM_TENMIN_Pos; + g_u32loMin = (REG_RTC_TALM & RTC_TALM_MIN_Msk) >> RTC_TALM_MIN_Pos; + g_u32hiSec = (REG_RTC_TALM & RTC_TALM_TENSEC_Msk) >> RTC_TALM_TENSEC_Pos; + g_u32loSec = (REG_RTC_TALM & RTC_TALM_SEC_Msk) >> RTC_TALM_SEC_Pos; + + /* Compute to 20XX year */ + u32Tmp = (g_u32hiYear * 10ul); + u32Tmp += g_u32loYear; + sPt->u32Year = u32Tmp + RTC_YEAR2000; + + /* Compute 0~12 month */ + u32Tmp = (g_u32hiMonth * 10ul); + sPt->u32Month = u32Tmp + g_u32loMonth; + + /* Compute 0~31 day */ + u32Tmp = (g_u32hiDay * 10ul); + sPt->u32Day = u32Tmp + g_u32loDay; + + /* Compute 12/24 hour */ + if (sPt->u32TimeScale == RTC_CLOCK_12) + { + u32Tmp = (g_u32hiHour * 10ul); + u32Tmp += g_u32loHour; + sPt->u32Hour = u32Tmp; /* AM: 1~12. PM: 21~32. */ + + if (sPt->u32Hour >= 21ul) + { + sPt->u32AmPm = RTC_PM; + sPt->u32Hour -= 20ul; + } + else + { + sPt->u32AmPm = RTC_AM; + } + + u32Tmp = (g_u32hiMin * 10ul); + u32Tmp += g_u32loMin; + sPt->u32Minute = u32Tmp; + + u32Tmp = (g_u32hiSec * 10ul); + u32Tmp += g_u32loSec; + sPt->u32Second = u32Tmp; + + } + else + { + u32Tmp = (g_u32hiHour * 10ul); + u32Tmp += g_u32loHour; + sPt->u32Hour = u32Tmp; + + u32Tmp = (g_u32hiMin * 10ul); + u32Tmp += g_u32loMin; + sPt->u32Minute = u32Tmp; + + u32Tmp = (g_u32hiSec * 10ul); + u32Tmp += g_u32loSec; + sPt->u32Second = u32Tmp; + } +} + +/** + * @brief Update Current RTC Date and Time + * + * @param[in] sPt Specify the time property and current date and time. It includes: \n + * u32Year: Year value, range between 2000 ~ 2099. \n + * u32Month: Month value, range between 1 ~ 12. \n + * u32Day: Day value, range between 1 ~ 31. \n + * u32DayOfWeek: Day of the week. [RTC_SUNDAY / RTC_MONDAY / RTC_TUESDAY / + * RTC_WEDNESDAY / RTC_THURSDAY / RTC_FRIDAY / + * RTC_SATURDAY] \n + * u32Hour: Hour value, range between 0 ~ 23. \n + * u32Minute: Minute value, range between 0 ~ 59. \n + * u32Second: Second value, range between 0 ~ 59. \n + * u32TimeScale: [RTC_CLOCK_12 / RTC_CLOCK_24] \n + * u8AmPm: [RTC_AM / RTC_PM] \n + * + * @return None + * + * @details This API is used to update current date and time to RTC. + */ +void RTC_SetDateAndTime(S_RTC_TIME_DATA_T *sPt) +{ + uint32_t u32RegCAL, u32RegTIME; + + if (sPt == 0ul) + { + } + else + { +#if !defined(USE_MA35D1_SUBM) + /*-----------------------------------------------------------------------------------------------------*/ + /* Set RTC 24/12 hour setting and Day of the Week */ + /*-----------------------------------------------------------------------------------------------------*/ + if (sPt->u32TimeScale == RTC_CLOCK_12) + { + RTC->CLKFMT &= ~RTC_CLKFMT_24HEN_Msk; + + /*-------------------------------------------------------------------------------------------------*/ + /* Important, range of 12-hour PM mode is 21 up to 32 */ + /*-------------------------------------------------------------------------------------------------*/ + if (sPt->u32AmPm == RTC_PM) + { + sPt->u32Hour += 20ul; + } + } + else + { + RTC->CLKFMT |= RTC_CLKFMT_24HEN_Msk; + } +#endif + + /* Set Day of the Week */ + RTC->WEEKDAY = sPt->u32DayOfWeek; + + /*-----------------------------------------------------------------------------------------------------*/ + /* Set RTC Current Date and Time */ + /*-----------------------------------------------------------------------------------------------------*/ + u32RegCAL = ((sPt->u32Year - RTC_YEAR2000) / 10ul) << 20; + u32RegCAL |= (((sPt->u32Year - RTC_YEAR2000) % 10ul) << 16); + u32RegCAL |= ((sPt->u32Month / 10ul) << 12); + u32RegCAL |= ((sPt->u32Month % 10ul) << 8); + u32RegCAL |= ((sPt->u32Day / 10ul) << 4); + u32RegCAL |= (sPt->u32Day % 10ul); + + u32RegTIME = ((sPt->u32Hour / 10ul) << 20); + u32RegTIME |= ((sPt->u32Hour % 10ul) << 16); + u32RegTIME |= ((sPt->u32Minute / 10ul) << 12); + u32RegTIME |= ((sPt->u32Minute % 10ul) << 8); + u32RegTIME |= ((sPt->u32Second / 10ul) << 4); + u32RegTIME |= (sPt->u32Second % 10ul); + + /*-----------------------------------------------------------------------------------------------------*/ + /* Set RTC Calender and Time Loading */ + /*-----------------------------------------------------------------------------------------------------*/ + RTC->CAL = (uint32_t)u32RegCAL; + RTC->TIME = (uint32_t)u32RegTIME; + } +} + +/** + * @brief Update RTC Alarm Date and Time + * + * @param[in] sPt Specify the time property and alarm date and time. It includes: \n + * u32Year: Year value, range between 2000 ~ 2099. \n + * u32Month: Month value, range between 1 ~ 12. \n + * u32Day: Day value, range between 1 ~ 31. \n + * u32DayOfWeek: Day of the week. [RTC_SUNDAY / RTC_MONDAY / RTC_TUESDAY / + * RTC_WEDNESDAY / RTC_THURSDAY / RTC_FRIDAY / + * RTC_SATURDAY] \n + * u32Hour: Hour value, range between 0 ~ 23. \n + * u32Minute: Minute value, range between 0 ~ 59. \n + * u32Second: Second value, range between 0 ~ 59. \n + * u32TimeScale: [RTC_CLOCK_12 / RTC_CLOCK_24] \n + * u8AmPm: [RTC_AM / RTC_PM] \n + * + * @return None + * + * @details This API is used to update alarm date and time setting to RTC. + */ +void RTC_SetAlarmDateAndTime(S_RTC_TIME_DATA_T *sPt) +{ + uint32_t u32RegCALM, u32RegTALM; + + if (sPt == 0) + { + } + else + { +#if !defined(USE_MA35D1_SUBM) + /*-----------------------------------------------------------------------------------------------------*/ + /* Set RTC 24/12 hour setting and Day of the Week */ + /*-----------------------------------------------------------------------------------------------------*/ + if (sPt->u32TimeScale == RTC_CLOCK_12) + { + RTC->CLKFMT &= ~RTC_CLKFMT_24HEN_Msk; + + /*-------------------------------------------------------------------------------------------------*/ + /* Important, range of 12-hour PM mode is 21 up to 32 */ + /*-------------------------------------------------------------------------------------------------*/ + if (sPt->u32AmPm == RTC_PM) + { + sPt->u32Hour += 20ul; + } + } + else + { + RTC->CLKFMT |= RTC_CLKFMT_24HEN_Msk; + } +#endif + + /*-----------------------------------------------------------------------------------------------------*/ + /* Set RTC Alarm Date and Time */ + /*-----------------------------------------------------------------------------------------------------*/ + u32RegCALM = ((sPt->u32Year - RTC_YEAR2000) / 10ul) << 20; + u32RegCALM |= (((sPt->u32Year - RTC_YEAR2000) % 10ul) << 16); + u32RegCALM |= ((sPt->u32Month / 10ul) << 12); + u32RegCALM |= ((sPt->u32Month % 10ul) << 8); + u32RegCALM |= ((sPt->u32Day / 10ul) << 4); + u32RegCALM |= (sPt->u32Day % 10ul); + + u32RegTALM = ((sPt->u32Hour / 10ul) << 20); + u32RegTALM |= ((sPt->u32Hour % 10ul) << 16); + u32RegTALM |= ((sPt->u32Minute / 10ul) << 12); + u32RegTALM |= ((sPt->u32Minute % 10ul) << 8); + u32RegTALM |= ((sPt->u32Second / 10ul) << 4); + u32RegTALM |= (sPt->u32Second % 10ul); + + REG_RTC_CALM = (uint32_t)u32RegCALM; + REG_RTC_TALM = (uint32_t)u32RegTALM; + } +} + +/** + * @brief Update RTC Current Date + * + * @param[in] u32Year The year calendar digit of current RTC setting. + * @param[in] u32Month The month calendar digit of current RTC setting. + * @param[in] u32Day The day calendar digit of current RTC setting. + * @param[in] u32DayOfWeek The Day of the week. [RTC_SUNDAY / RTC_MONDAY / RTC_TUESDAY / + * RTC_WEDNESDAY / RTC_THURSDAY / RTC_FRIDAY / + * RTC_SATURDAY] + * + * @return None + * + * @details This API is used to update current date to RTC. + */ +void RTC_SetDate(uint32_t u32Year, uint32_t u32Month, uint32_t u32Day, uint32_t u32DayOfWeek) +{ + uint32_t u32RegCAL; + + u32RegCAL = ((u32Year - RTC_YEAR2000) / 10ul) << 20; + u32RegCAL |= (((u32Year - RTC_YEAR2000) % 10ul) << 16); + u32RegCAL |= ((u32Month / 10ul) << 12); + u32RegCAL |= ((u32Month % 10ul) << 8); + u32RegCAL |= ((u32Day / 10ul) << 4); + u32RegCAL |= (u32Day % 10ul); + + /* Set Day of the Week */ + RTC->WEEKDAY = u32DayOfWeek & RTC_WEEKDAY_WEEKDAY_Msk; + + /* Set RTC Calender Loading */ + RTC->CAL = (uint32_t)u32RegCAL; +} + +/** + * @brief Update RTC Current Time + * + * @param[in] u32Hour The hour time digit of current RTC setting. + * @param[in] u32Minute The minute time digit of current RTC setting. + * @param[in] u32Second The second time digit of current RTC setting. + * @param[in] u32TimeMode The 24-Hour / 12-Hour Time Scale Selection. [RTC_CLOCK_12 / RTC_CLOCK_24] + * @param[in] u32AmPm 12-hour time scale with AM and PM indication. Only Time Scale select 12-hour used. [RTC_AM / RTC_PM] + * + * @return None + * + * @details This API is used to update current time to RTC. + */ +void RTC_SetTime(uint32_t u32Hour, uint32_t u32Minute, uint32_t u32Second, uint32_t u32TimeMode, uint32_t u32AmPm) +{ + uint32_t u32RegTIME; + + /* Important, range of 12-hour PM mode is 21 up to 32 */ + if ((u32TimeMode == RTC_CLOCK_12) && (u32AmPm == RTC_PM)) + { + u32Hour += 20ul; + } + + u32RegTIME = ((u32Hour / 10ul) << 20); + u32RegTIME |= ((u32Hour % 10ul) << 16); + u32RegTIME |= ((u32Minute / 10ul) << 12); + u32RegTIME |= ((u32Minute % 10ul) << 8); + u32RegTIME |= ((u32Second / 10ul) << 4); + u32RegTIME |= (u32Second % 10ul); + +#if !defined(USE_MA35D1_SUBM) + /*-----------------------------------------------------------------------------------------------------*/ + /* Set RTC 24/12 hour setting and Day of the Week */ + /*-----------------------------------------------------------------------------------------------------*/ + if (u32TimeMode == RTC_CLOCK_12) + { + RTC->CLKFMT &= ~RTC_CLKFMT_24HEN_Msk; + } + else + { + RTC->CLKFMT |= RTC_CLKFMT_24HEN_Msk; + } +#endif + + RTC->TIME = (uint32_t)u32RegTIME; +} + +/** + * @brief Update RTC Alarm Date + * + * @param[in] u32Year The year calendar digit of RTC alarm setting. + * @param[in] u32Month The month calendar digit of RTC alarm setting. + * @param[in] u32Day The day calendar digit of RTC alarm setting. + * + * @return None + * + * @details This API is used to update alarm date setting to RTC. + */ +void RTC_SetAlarmDate(uint32_t u32Year, uint32_t u32Month, uint32_t u32Day) +{ + uint32_t u32RegCALM; + + u32RegCALM = ((u32Year - RTC_YEAR2000) / 10ul) << 20; + u32RegCALM |= (((u32Year - RTC_YEAR2000) % 10ul) << 16); + u32RegCALM |= ((u32Month / 10ul) << 12); + u32RegCALM |= ((u32Month % 10ul) << 8); + u32RegCALM |= ((u32Day / 10ul) << 4); + u32RegCALM |= (u32Day % 10ul); + + /* Set RTC Alarm Date */ + REG_RTC_CALM = (uint32_t)u32RegCALM; +} + +/** + * @brief Update RTC Alarm Time + * + * @param[in] u32Hour The hour time digit of RTC alarm setting. + * @param[in] u32Minute The minute time digit of RTC alarm setting. + * @param[in] u32Second The second time digit of RTC alarm setting. + * @param[in] u32TimeMode The 24-Hour / 12-Hour Time Scale Selection. [RTC_CLOCK_12 / RTC_CLOCK_24] + * @param[in] u32AmPm 12-hour time scale with AM and PM indication. Only Time Scale select 12-hour used. [RTC_AM / RTC_PM] + * + * @return None + * + * @details This API is used to update alarm time setting to RTC. + */ +void RTC_SetAlarmTime(uint32_t u32Hour, uint32_t u32Minute, uint32_t u32Second, uint32_t u32TimeMode, uint32_t u32AmPm) +{ + uint32_t u32RegTALM; + + /* Important, range of 12-hour PM mode is 21 up to 32 */ + if ((u32TimeMode == RTC_CLOCK_12) && (u32AmPm == RTC_PM)) + { + u32Hour += 20ul; + } + + u32RegTALM = ((u32Hour / 10ul) << 20); + u32RegTALM |= ((u32Hour % 10ul) << 16); + u32RegTALM |= ((u32Minute / 10ul) << 12); + u32RegTALM |= ((u32Minute % 10ul) << 8); + u32RegTALM |= ((u32Second / 10ul) << 4); + u32RegTALM |= (u32Second % 10ul); + +#if !defined(USE_MA35D1_SUBM) + /*-----------------------------------------------------------------------------------------------------*/ + /* Set RTC 24/12 hour setting and Day of the Week */ + /*-----------------------------------------------------------------------------------------------------*/ + if (u32TimeMode == RTC_CLOCK_12) + { + RTC->CLKFMT &= ~RTC_CLKFMT_24HEN_Msk; + } + else + { + RTC->CLKFMT |= RTC_CLKFMT_24HEN_Msk; + } +#endif + + /* Set RTC Alarm Time */ + REG_RTC_TALM = (uint32_t)u32RegTALM; +} + +/** + * @brief Set RTC Alarm Date Mask Function + * + * @param[in] u8IsTenYMsk 1: enable 10-Year digit alarm mask; 0: disabled. + * @param[in] u8IsYMsk 1: enable 1-Year digit alarm mask; 0: disabled. + * @param[in] u8IsTenMMsk 1: enable 10-Mon digit alarm mask; 0: disabled. + * @param[in] u8IsMMsk 1: enable 1-Mon digit alarm mask; 0: disabled. + * @param[in] u8IsTenDMsk 1: enable 10-Day digit alarm mask; 0: disabled. + * @param[in] u8IsDMsk 1: enable 1-Day digit alarm mask; 0: disabled. + * + * @return None + * + * @details This API is used to enable or disable RTC alarm date mask function. + */ +void RTC_SetAlarmDateMask(uint8_t u8IsTenYMsk, uint8_t u8IsYMsk, uint8_t u8IsTenMMsk, uint8_t u8IsMMsk, uint8_t u8IsTenDMsk, uint8_t u8IsDMsk) +{ + REG_RTC_CAMSK = ((uint32_t)u8IsTenYMsk << RTC_CAMSK_MTENYEAR_Pos) | + ((uint32_t)u8IsYMsk << RTC_CAMSK_MYEAR_Pos) | + ((uint32_t)u8IsTenMMsk << RTC_CAMSK_MTENMON_Pos) | + ((uint32_t)u8IsMMsk << RTC_CAMSK_MMON_Pos) | + ((uint32_t)u8IsTenDMsk << RTC_CAMSK_MTENDAY_Pos) | + ((uint32_t)u8IsDMsk << RTC_CAMSK_MDAY_Pos); +} + +/** + * @brief Set RTC Alarm Time Mask Function + * + * @param[in] u8IsTenHMsk 1: enable 10-Hour digit alarm mask; 0: disabled. + * @param[in] u8IsHMsk 1: enable 1-Hour digit alarm mask; 0: disabled. + * @param[in] u8IsTenMMsk 1: enable 10-Min digit alarm mask; 0: disabled. + * @param[in] u8IsMMsk 1: enable 1-Min digit alarm mask; 0: disabled. + * @param[in] u8IsTenSMsk 1: enable 10-Sec digit alarm mask; 0: disabled. + * @param[in] u8IsSMsk 1: enable 1-Sec digit alarm mask; 0: disabled. + * + * @return None + * + * @details This API is used to enable or disable RTC alarm time mask function. + */ +void RTC_SetAlarmTimeMask(uint8_t u8IsTenHMsk, uint8_t u8IsHMsk, uint8_t u8IsTenMMsk, uint8_t u8IsMMsk, uint8_t u8IsTenSMsk, uint8_t u8IsSMsk) +{ + REG_RTC_TAMSK = ((uint32_t)u8IsTenHMsk << RTC_TAMSK_MTENHR_Pos) | + ((uint32_t)u8IsHMsk << RTC_TAMSK_MHR_Pos) | + ((uint32_t)u8IsTenMMsk << RTC_TAMSK_MTENMIN_Pos) | + ((uint32_t)u8IsMMsk << RTC_TAMSK_MMIN_Pos) | + ((uint32_t)u8IsTenSMsk << RTC_TAMSK_MTENSEC_Pos) | + ((uint32_t)u8IsSMsk << RTC_TAMSK_MSEC_Pos); +} + +/** + * @brief Get Day of the Week + * + * @param None + * + * @retval 0 Sunday + * @retval 1 Monday + * @retval 2 Tuesday + * @retval 3 Wednesday + * @retval 4 Thursday + * @retval 5 Friday + * @retval 6 Saturday + * + * @details This API is used to get day of the week of current RTC date. + */ +uint32_t RTC_GetDayOfWeek(void) +{ + return (RTC->WEEKDAY & RTC_WEEKDAY_WEEKDAY_Msk); +} + +/** + * @brief Set RTC Tick Period Time + * + * @param[in] u32TickSelection It is used to set the RTC tick period time for Periodic Time Tick request. \n + * It consists of: + * - \ref RTC_TICK_1_SEC : Time tick is 1 second + * - \ref RTC_TICK_1_2_SEC : Time tick is 1/2 second + * - \ref RTC_TICK_1_4_SEC : Time tick is 1/4 second + * - \ref RTC_TICK_1_8_SEC : Time tick is 1/8 second + * - \ref RTC_TICK_1_16_SEC : Time tick is 1/16 second + * - \ref RTC_TICK_1_32_SEC : Time tick is 1/32 second + * - \ref RTC_TICK_1_64_SEC : Time tick is 1/64 second + * - \ref RTC_TICK_1_128_SEC : Time tick is 1/128 second + * + * @return None + * + * @details This API is used to set RTC tick period time for each tick interrupt. + */ +void RTC_SetTickPeriod(uint32_t u32TickSelection) +{ + REG_RTC_TICK = (REG_RTC_TICK & ~RTC_TICK_TICK_Msk) | u32TickSelection; +} + +/** + * @brief Enable RTC Interrupt + * + * @param[in] u32IntFlagMask Specify the interrupt source. It consists of: + * - \ref RTC_INTEN_ALMIEN_Msk : Alarm interrupt + * - \ref RTC_INTEN_TICKIEN_Msk : Tick interrupt + * + * @return None + * + * @details This API is used to enable the specify RTC interrupt function. + */ +void RTC_EnableInt(uint32_t u32IntFlagMask) +{ + REG_RTC_INTEN |= u32IntFlagMask; +} + +/** + * @brief Disable RTC Interrupt + * + * @param[in] u32IntFlagMask Specify the interrupt source. It consists of: + * - \ref RTC_INTEN_ALMIEN_Msk : Alarm interrupt + * - \ref RTC_INTEN_TICKIEN_Msk : Tick interrupt + * + * @return None + * + * @details This API is used to disable the specify RTC interrupt function. + */ +void RTC_DisableInt(uint32_t u32IntFlagMask) +{ + REG_RTC_INTEN &= ~u32IntFlagMask; + REG_RTC_INTSTS = u32IntFlagMask; +} + + +/*@}*/ /* end of group RTC_EXPORTED_FUNCTIONS */ + +/*@}*/ /* end of group RTC_Driver */ + +/*@}*/ /* end of group Standard_Driver */ + diff --git a/bsp/nuvoton/libraries/ma35/StdDriver/src/nu_sc.c b/bsp/nuvoton/libraries/ma35/StdDriver/src/nu_sc.c new file mode 100644 index 0000000000..f3286844dd --- /dev/null +++ b/bsp/nuvoton/libraries/ma35/StdDriver/src/nu_sc.c @@ -0,0 +1,368 @@ +/**************************************************************************//** + * @file sc.c + * @brief Smartcard(SC) driver source file + * + * SPDX-License-Identifier: Apache-2.0 + * @copyright (C) 2020 Nuvoton Technology Corp. All rights reserved. + *****************************************************************************/ +#include "NuMicro.h" + +/* Below are variables used locally by SC driver and does not want to parse by doxygen unless HIDDEN_SYMBOLS is defined */ +/** @cond HIDDEN_SYMBOLS */ +static uint32_t u32CardStateIgnore[SC_INTERFACE_NUM] = {0UL, 0UL}; + +/** @endcond HIDDEN_SYMBOLS */ + +/** @addtogroup Standard_Driver Standard Driver + @{ +*/ + +/** @addtogroup SC_Driver SC Driver + @{ +*/ + +/** @addtogroup SC_EXPORTED_FUNCTIONS SC Exported Functions + @{ +*/ + +/** + * @brief This function indicates specified smartcard slot status + * @param[in] sc Base address of smartcard module + * @return Card insert status + * @retval TRUE Card insert + * @retval FALSE Card remove + */ +uint32_t SC_IsCardInserted(SC_T *sc) +{ + uint32_t ret; + /* put conditions into two variable to remove IAR compilation warning */ + uint32_t cond1 = ((sc->STATUS & SC_STATUS_CDPINSTS_Msk) >> SC_STATUS_CDPINSTS_Pos); + uint32_t cond2 = ((sc->CTL & SC_CTL_CDLV_Msk) >> SC_CTL_CDLV_Pos); + + if ((sc == SC0) && (u32CardStateIgnore[0] == 1UL)) + { + ret = (uint32_t)TRUE; + } + else if ((sc == SC1) && (u32CardStateIgnore[1] == 1UL)) + { + ret = (uint32_t)TRUE; + } + else if (cond1 != cond2) + { + ret = (uint32_t)FALSE; + } + else + { + ret = (uint32_t)TRUE; + } + return ret; +} + +/** + * @brief This function reset both transmit and receive FIFO of specified smartcard module + * @param[in] sc Base address of smartcard module + * @return None + */ +void SC_ClearFIFO(SC_T *sc) +{ + while (sc->ALTCTL & SC_ALTCTL_SYNC_Msk) + { + ; + } + sc->ALTCTL |= (SC_ALTCTL_TXRST_Msk | SC_ALTCTL_RXRST_Msk); +} + +/** + * @brief This function disable specified smartcard module + * @param[in] sc Base address of smartcard module + * @return None + */ +void SC_Close(SC_T *sc) +{ + sc->INTEN = 0UL; + while (sc->PINCTL & SC_PINCTL_SYNC_Msk) + { + ; + } + sc->PINCTL = 0UL; + sc->ALTCTL = 0UL; + while (sc->CTL & SC_CTL_SYNC_Msk) + { + ; + } + sc->CTL = 0UL; +} + +/** + * @brief This function initialized smartcard module + * @param[in] sc Base address of smartcard module + * @param[in] u32CardDet Card detect polarity, select the CD pin state which indicates card absent. Could be + * -\ref SC_PIN_STATE_HIGH + * -\ref SC_PIN_STATE_LOW + * -\ref SC_PIN_STATE_IGNORE, no card detect pin, always assumes card present + * @param[in] u32PWR Power on polarity, select the PWR pin state which could set smartcard VCC to high level. Could be + * -\ref SC_PIN_STATE_HIGH + * -\ref SC_PIN_STATE_LOW + * @return None + */ +void SC_Open(SC_T *sc, uint32_t u32CardDet, uint32_t u32PWR) +{ + uint32_t u32Reg = 0UL, u32Intf; + + if (sc == SC0) + { + u32Intf = 0UL; + } + else + { + u32Intf = 1UL; + } + + if (u32CardDet != SC_PIN_STATE_IGNORE) + { + u32Reg = u32CardDet ? 0UL : SC_CTL_CDLV_Msk; + u32CardStateIgnore[u32Intf] = 0UL; + } + else + { + u32CardStateIgnore[u32Intf] = 1UL; + } + sc->PINCTL = u32PWR ? 0UL : SC_PINCTL_PWRINV_Msk; + while (sc->CTL & SC_CTL_SYNC_Msk) + { + ; + } + sc->CTL = SC_CTL_SCEN_Msk | SC_CTL_TMRSEL_Msk | u32Reg; +} + +/** + * @brief This function reset specified smartcard module to its default state for activate smartcard + * @param[in] sc Base address of smartcard module + * @return None + */ +void SC_ResetReader(SC_T *sc) +{ + uint32_t u32Intf; + + if (sc == SC0) + { + u32Intf = 0UL; + } + else + { + u32Intf = 1UL; + } + + /* Reset FIFO, enable auto de-activation while card removal */ + sc->ALTCTL |= (SC_ALTCTL_TXRST_Msk | SC_ALTCTL_RXRST_Msk | SC_ALTCTL_ADACEN_Msk); + /* Set Rx trigger level to 1 character, longest card detect debounce period, disable error retry (EMV ATR does not use error retry) */ + while (sc->CTL & SC_CTL_SYNC_Msk) + { + ; + } + sc->CTL &= ~(SC_CTL_RXTRGLV_Msk | + SC_CTL_CDDBSEL_Msk | + SC_CTL_TXRTY_Msk | + SC_CTL_TXRTYEN_Msk | + SC_CTL_RXRTY_Msk | + SC_CTL_RXRTYEN_Msk); + while (sc->CTL & SC_CTL_SYNC_Msk) + { + ; + } + /* Enable auto convention, and all three smartcard internal timers */ + sc->CTL |= SC_CTL_AUTOCEN_Msk | SC_CTL_TMRSEL_Msk; + /* Disable Rx timeout */ + sc->RXTOUT = 0UL; + /* 372 clocks per ETU by default */ + sc->ETUCTL = 371UL; + + + /* Enable necessary interrupt for smartcard operation */ + if (u32CardStateIgnore[u32Intf]) /* Do not enable card detect interrupt if card present state ignore */ + { + sc->INTEN = (SC_INTEN_RDAIEN_Msk | + SC_INTEN_TERRIEN_Msk | + SC_INTEN_TMR0IEN_Msk | + SC_INTEN_TMR1IEN_Msk | + SC_INTEN_TMR2IEN_Msk | + SC_INTEN_BGTIEN_Msk | + SC_INTEN_ACERRIEN_Msk); + } + else + { + sc->INTEN = (SC_INTEN_RDAIEN_Msk | + SC_INTEN_TERRIEN_Msk | + SC_INTEN_TMR0IEN_Msk | + SC_INTEN_TMR1IEN_Msk | + SC_INTEN_TMR2IEN_Msk | + SC_INTEN_BGTIEN_Msk | + SC_INTEN_CDIEN_Msk | + SC_INTEN_ACERRIEN_Msk); + } + return; +} + +/** + * @brief This function block guard time (BGT) of specified smartcard module + * @param[in] sc Base address of smartcard module + * @param[in] u32BGT Block guard time using ETU as unit, valid range are between 1 ~ 32 + * @return None + */ +void SC_SetBlockGuardTime(SC_T *sc, uint32_t u32BGT) +{ + sc->CTL = (sc->CTL & ~SC_CTL_BGT_Msk) | ((u32BGT - 1UL) << SC_CTL_BGT_Pos); +} + +/** + * @brief This function character guard time (CGT) of specified smartcard module + * @param[in] sc Base address of smartcard module + * @param[in] u32CGT Character guard time using ETU as unit, valid range are between 11 ~ 267 + * @return None + */ +void SC_SetCharGuardTime(SC_T *sc, uint32_t u32CGT) +{ + u32CGT -= sc->CTL & SC_CTL_NSB_Msk ? 11UL : 12UL; + sc->EGT = u32CGT; +} + +/** + * @brief This function stop all smartcard timer of specified smartcard module + * @param[in] sc Base address of smartcard module + * @return None + * @note This function stop the timers within smartcard module, \b not timer module + */ +void SC_StopAllTimer(SC_T *sc) +{ + while (sc->ALTCTL & SC_ALTCTL_SYNC_Msk) + { + ; + } + sc->ALTCTL &= ~(SC_ALTCTL_CNTEN0_Msk | SC_ALTCTL_CNTEN1_Msk | SC_ALTCTL_CNTEN2_Msk); +} + +/** + * @brief This function configure and start a smartcard timer of specified smartcard module + * @param[in] sc Base address of smartcard module + * @param[in] u32TimerNum Timer to start. Valid values are 0, 1, 2. + * @param[in] u32Mode Timer operating mode, valid values are: + * - \ref SC_TMR_MODE_0 + * - \ref SC_TMR_MODE_1 + * - \ref SC_TMR_MODE_2 + * - \ref SC_TMR_MODE_3 + * - \ref SC_TMR_MODE_4 + * - \ref SC_TMR_MODE_5 + * - \ref SC_TMR_MODE_6 + * - \ref SC_TMR_MODE_7 + * - \ref SC_TMR_MODE_8 + * - \ref SC_TMR_MODE_F + * @param[in] u32ETUCount Timer timeout duration, ETU based. For timer 0, valid range are between 1~0x1000000ETUs. + * For timer 1 and timer 2, valid range are between 1 ~ 0x100 ETUs + * @return None + * @note This function start the timer within smartcard module, \b not timer module + * @note Depend on the timer operating mode, timer may not start counting immediately + */ +void SC_StartTimer(SC_T *sc, uint32_t u32TimerNum, uint32_t u32Mode, uint32_t u32ETUCount) +{ + uint32_t reg = u32Mode | (SC_TMRCTL0_CNT_Msk & (u32ETUCount - 1UL)); + while (sc->ALTCTL & SC_ALTCTL_SYNC_Msk) + { + ; + } + if (u32TimerNum == 0UL) + { + while (sc->TMRCTL0 & SC_TMRCTL0_SYNC_Msk) + { + ; + } + sc->TMRCTL0 = reg; + sc->ALTCTL |= SC_ALTCTL_CNTEN0_Msk; + } + else if (u32TimerNum == 1UL) + { + while (sc->TMRCTL1 & SC_TMRCTL1_SYNC_Msk) + { + ; + } + sc->TMRCTL1 = reg; + sc->ALTCTL |= SC_ALTCTL_CNTEN1_Msk; + } + else /* timer 2 */ + { + while (sc->TMRCTL2 & SC_TMRCTL2_SYNC_Msk) + { + ; + } + sc->TMRCTL2 = reg; + sc->ALTCTL |= SC_ALTCTL_CNTEN2_Msk; + } +} + +/** + * @brief This function stop a smartcard timer of specified smartcard module + * @param[in] sc Base address of smartcard module + * @param[in] u32TimerNum Timer to stop. Valid values are 0, 1, 2. + * @return None + * @note This function stop the timer within smartcard module, \b not timer module + */ +void SC_StopTimer(SC_T *sc, uint32_t u32TimerNum) +{ + while (sc->ALTCTL & SC_ALTCTL_SYNC_Msk) + { + ; + } + if (u32TimerNum == 0UL) + { + sc->ALTCTL &= ~SC_ALTCTL_CNTEN0_Msk; + } + else if (u32TimerNum == 1UL) + { + sc->ALTCTL &= ~SC_ALTCTL_CNTEN1_Msk; + } + else /* timer 2 */ + { + sc->ALTCTL &= ~SC_ALTCTL_CNTEN2_Msk; + } +} + +/** + * @brief This function gets smartcard clock frequency. + * @param[in] sc Base address of smartcard module + * @return Smartcard frequency in kHz + */ +uint32_t SC_GetInterfaceClock(SC_T *sc) +{ + uint32_t u32ClkSrc, u32Num, u32Clk; + + if (sc == SC0) + { + u32Num = 0UL; + } + else + { + u32Num = 1UL; + } + + u32ClkSrc = CLK->CLKSEL4 >> (u32Num + CLK_CLKSEL4_SC0SEL_Pos); + + /* Get smartcard module clock */ + if (u32ClkSrc == 0UL) + { + u32Clk = __HXT; + } + else + { + u32Clk = CLK_GetPCLK3Freq(); + } + + u32Clk /= (((CLK->CLKDIV1 >> (4UL * u32Num)) & CLK_CLKDIV1_SC0DIV_Msk) + 1UL) * 1000UL;; + + return u32Clk; +} + +/*@}*/ /* end of group SC_EXPORTED_FUNCTIONS */ + +/*@}*/ /* end of group SC_Driver */ + +/*@}*/ /* end of group Standard_Driver */ + diff --git a/bsp/nuvoton/libraries/ma35/StdDriver/src/nu_scuart.c b/bsp/nuvoton/libraries/ma35/StdDriver/src/nu_scuart.c new file mode 100644 index 0000000000..7af435253c --- /dev/null +++ b/bsp/nuvoton/libraries/ma35/StdDriver/src/nu_scuart.c @@ -0,0 +1,222 @@ +/**************************************************************************//** + * @file scuart.c + * @brief Smartcard UART mode (SCUART) driver source file + * + * SPDX-License-Identifier: Apache-2.0 + * @copyright (C) 2020 Nuvoton Technology Corp. All rights reserved. + *****************************************************************************/ +#include "NuMicro.h" + +static uint32_t SCUART_GetClock(SC_T *sc); + +/** @addtogroup Standard_Driver Standard Driver + @{ +*/ + +/** @addtogroup SCUART_Driver SCUART Driver + @{ +*/ + + +/** @addtogroup SCUART_EXPORTED_FUNCTIONS SCUART Exported Functions + @{ +*/ + +/** + * @brief The function is used to disable smartcard interface UART mode. + * @param sc The base address of smartcard module. + * @return None + */ +void SCUART_Close(SC_T *sc) +{ + sc->INTEN = 0UL; + sc->UARTCTL = 0UL; + sc->CTL = 0UL; + +} +/** @cond HIDDEN_SYMBOLS */ +/** + * @brief This function returns module clock of specified SC interface + * @param[in] sc The base address of smartcard module. + * @return Module clock of specified SC interface + */ +static uint32_t SCUART_GetClock(SC_T *sc) +{ + uint32_t u32ClkSrc, u32Num, u32Clk; + + if (sc == SC0) + { + u32Num = 0UL; + } + else + { + u32Num = 1UL; + } + + u32ClkSrc = CLK->CLKSEL4 >> (u32Num + CLK_CLKSEL4_SC0SEL_Msk); + + /* Get smartcard module clock */ + if (u32ClkSrc == 0UL) + { + u32Clk = __HXT; + } + else + { + u32Clk = CLK_GetPCLK3Freq(); + } + + + u32Clk /= (((CLK->CLKDIV1 >> (4UL * u32Num)) & CLK_CLKDIV1_SC0DIV_Msk) + 1UL); + + + return u32Clk; +} + +/** @endcond HIDDEN_SYMBOLS */ + +/** + * @brief This function use to enable smartcard module UART mode and set baudrate. + * @param[in] sc The base address of smartcard module. + * @param[in] u32baudrate Target baudrate of smartcard module. + * @return Actual baudrate of smartcard mode + * @details This function configures character width to 8 bits, 1 stop bit, and no parity. + * And can use \ref SCUART_SetLineConfig function to update these settings + * The baudrate clock source comes from SC_CLK/SC_DIV, where SC_CLK is controlled + * by SCxSEL in CLKSEL3 register, SC_DIV is controlled by SCxDIV in CLKDIV1 + * register. Since the baudrate divider is 12-bit wide and must be larger than 4, + * (clock source / baudrate) must be larger or equal to 5 and smaller or equal to + * 4096. Otherwise this function cannot configure SCUART to work with target baudrate. + */ +uint32_t SCUART_Open(SC_T *sc, uint32_t u32baudrate) +{ + uint32_t u32Clk = SCUART_GetClock(sc), u32Div; + + /* Calculate divider for target baudrate */ + u32Div = (u32Clk + (u32baudrate >> 1) - 1UL) / u32baudrate - 1UL; + + /* Enable smartcard interface and stop bit = 1 */ + sc->CTL = SC_CTL_SCEN_Msk | SC_CTL_NSB_Msk; + /* Enable UART mode, disable parity and 8 bit per character */ + sc->UARTCTL = SCUART_CHAR_LEN_8 | SCUART_PARITY_NONE | SC_UARTCTL_UARTEN_Msk; + sc->ETUCTL = u32Div; + + return (u32Clk / (u32Div + 1UL)); +} + +/** + * @brief The function is used to read Rx data from RX FIFO. + * @param[in] sc The base address of smartcard module. + * @param[in] pu8RxBuf The buffer to store receive the data + * @param[in] u32ReadBytes Target number of characters to receive + * @return Actual character number reads to buffer + * @note This function does not block and return immediately if there's no data available + */ +uint32_t SCUART_Read(SC_T *sc, uint8_t pu8RxBuf[], uint32_t u32ReadBytes) +{ + uint32_t u32Count; + + for (u32Count = 0UL; u32Count < u32ReadBytes; u32Count++) + { + if (SCUART_GET_RX_EMPTY(sc)) /* no data available */ + { + break; + } + pu8RxBuf[u32Count] = (uint8_t)SCUART_READ(sc); /* get data from FIFO */ + } + + return u32Count; +} + +/** + * @brief This function use to configure smartcard UART mode line setting. + * @param[in] sc The base address of smartcard module. + * @param[in] u32Baudrate Target baudrate of smartcard module. If this value is 0, UART baudrate will not change. + * @param[in] u32DataWidth The data length, could be + * - \ref SCUART_CHAR_LEN_5 + * - \ref SCUART_CHAR_LEN_6 + * - \ref SCUART_CHAR_LEN_7 + * - \ref SCUART_CHAR_LEN_8 + * @param[in] u32Parity The parity setting, could be + * - \ref SCUART_PARITY_NONE + * - \ref SCUART_PARITY_ODD + * - \ref SCUART_PARITY_EVEN + * @param[in] u32StopBits The stop bit length, could be + * - \ref SCUART_STOP_BIT_1 + * - \ref SCUART_STOP_BIT_2 + * @return Actual baudrate of smartcard + * @details The baudrate clock source comes from SC_CLK/SC_DIV, where SC_CLK is controlled + * by SCxSEL in CLKSEL3 register, SC_DIV is controlled by SCxDIV in CLKDIV1 + * register. Since the baudrate divider is 12-bit wide and must be larger than 4, + * (clock source / baudrate) must be larger or equal to 5 and smaller or equal to + * 4096. Otherwise this function cannot configure SCUART to work with target baudrate. + */ +uint32_t SCUART_SetLineConfig(SC_T *sc, uint32_t u32Baudrate, uint32_t u32DataWidth, uint32_t u32Parity, uint32_t u32StopBits) +{ + + uint32_t u32Clk = SCUART_GetClock(sc), u32Div; + + if (u32Baudrate == 0UL) /* keep original baudrate setting */ + { + u32Div = sc->ETUCTL & SC_ETUCTL_ETURDIV_Msk; + } + else + { + /* Calculate divider for target baudrate */ + u32Div = (u32Clk + (u32Baudrate >> 1) - 1UL) / u32Baudrate - 1UL; + sc->ETUCTL = u32Div; + } + /* Set stop bit */ + sc->CTL = u32StopBits | SC_CTL_SCEN_Msk; + /* Set character width and parity */ + sc->UARTCTL = u32Parity | u32DataWidth | SC_UARTCTL_UARTEN_Msk; + + return (u32Clk / (u32Div + 1UL)); +} + +/** + * @brief This function use to set receive timeout count. + * @param[in] sc The base address of smartcard module. + * @param[in] u32TOC Rx timeout counter, using baudrate as counter unit. Valid range are 0~0x1FF, + * set this value to 0 will disable timeout counter + * @return None + * @details The time-out counter resets and starts counting whenever the RX buffer received a + * new data word. Once the counter decrease to 1 and no new data is received or CPU + * does not read any data from FIFO, a receiver time-out interrupt will be generated. + */ +void SCUART_SetTimeoutCnt(SC_T *sc, uint32_t u32TOC) +{ + sc->RXTOUT = u32TOC; +} + + +/** + * @brief This function is to write data into transmit FIFO to send data out. + * @param[in] sc The base address of smartcard module. + * @param[in] pu8TxBuf The buffer containing data to send to transmit FIFO. + * @param[in] u32WriteBytes Number of data to send. + * @return None + * @note This function blocks until all data write into FIFO + */ +void SCUART_Write(SC_T *sc, uint8_t pu8TxBuf[], uint32_t u32WriteBytes) +{ + uint32_t u32Count; + + for (u32Count = 0UL; u32Count != u32WriteBytes; u32Count++) + { + /* Wait 'til FIFO not full */ + while (SCUART_GET_TX_FULL(sc)) + { + ; + } + /* Write 1 byte to FIFO */ + sc->DAT = pu8TxBuf[u32Count]; + } +} + + +/*@}*/ /* end of group SCUART_EXPORTED_FUNCTIONS */ + +/*@}*/ /* end of group SCUART_Driver */ + +/*@}*/ /* end of group Standard_Driver */ + diff --git a/bsp/nuvoton/libraries/ma35/StdDriver/src/nu_sdh.c b/bsp/nuvoton/libraries/ma35/StdDriver/src/nu_sdh.c new file mode 100644 index 0000000000..a7f9a9dfef --- /dev/null +++ b/bsp/nuvoton/libraries/ma35/StdDriver/src/nu_sdh.c @@ -0,0 +1,276 @@ +/**************************************************************************//** +* @file nu_sdh.c +* @brief SDH driver source file +* +* SPDX-License-Identifier: Apache-2.0 +* @copyright (C) 2020 Nuvoton Technology Corp. All rights reserved. +*****************************************************************************/ +#include "NuMicro.h" +#include + +/** @addtogroup Standard_Driver Standard Driver +@{ +*/ + +/** @addtogroup SDH_Driver SDH Driver +@{ +*/ + +/** @addtogroup SDH_EXPORTED_FUNCTIONS SDH Exported Functions +@{ +*/ + +#define SDH_DBG +#if defined(SDH_DBG) + extern int rt_kprintf(const char *fmt, ...); + #define SDH_DBG_PRINT rt_kprintf + extern void rt_hw_us_delay(uint32_t us); + #define DelayMicrosecond rt_hw_us_delay + +#else + #define SDH_DBG_PRINT(...) + #define DelayMicrosecond SDH_Delay +#endif + +/* Print out register information: Name, Offset, Current value, Reset value, match flag. */ +#define DUMP_REG(BASE, NAME, DEFAULT) SDH_DBG_PRINT("| %-24s | 0x%04x | 0x%08x | 0x%08x | %-6s |\n", #NAME, (uint32_t)&BASE->NAME - (uint32_t)BASE, BASE->NAME, DEFAULT, ((BASE->NAME != DEFAULT) ? " N ":" Y ") ) + +#define PACK_MMC_CMD(CMD, IDX, ARG, RESP) ( CMD.cmdidx=IDX, CMD.cmdarg=ARG, CMD.resp_type=RESP ) + +#if !defined(SDH_DBG) +static void SDH_Delay(uint32_t u32LoopTime) +{ + volatile uint32_t i = 0x2000 * u32LoopTime; + for (; i > 0; i--); +} +#endif + +void SDH_DumpReg(SDH_T *sdh) +{ + + SDH_DBG_PRINT("========================================================================\n"); + SDH_DBG_PRINT("SDH_T(0x%08x): %d\n", sdh, sizeof(SDH_T)); + SDH_DBG_PRINT("========================================================================\n"); + SDH_DBG_PRINT("| %-24s | %-6s | %-10s | %-10s | %-6s |\n", "REG NAME", "OFFSET", "CURRENT", "DEFAULT", "MATCH?"); + SDH_DBG_PRINT("========================================================================\n"); + DUMP_REG(sdh, SDMASA, 0x0); + DUMP_REG(sdh, BLOCKSIZE, 0x0); + DUMP_REG(sdh, BLOCKCOUNT, 0x0); + DUMP_REG(sdh, ARGUMENT, 0x0); + DUMP_REG(sdh, XFER_MODE, 0x0); + DUMP_REG(sdh, CMD, 0x0); + DUMP_REG(sdh, RESP01, 0x0); + DUMP_REG(sdh, RESP23, 0x0); + DUMP_REG(sdh, RESP45, 0x0); + DUMP_REG(sdh, RESP67, 0x0); + DUMP_REG(sdh, BUF_DATA, 0x0); + DUMP_REG(sdh, PSTATE, 0x0); + DUMP_REG(sdh, HOST_CTRL1, 0x0); + DUMP_REG(sdh, PWR_CTRL, 0x0); + + DUMP_REG(sdh, BGAP_CTRL, 0x0); + DUMP_REG(sdh, WUP_CTRL, 0x0); + DUMP_REG(sdh, CLK_CTRL, 0x0); + DUMP_REG(sdh, TOUT_CTRL, 0x0); + DUMP_REG(sdh, SW_RST, 0x0); + DUMP_REG(sdh, NORMAL_INT_STAT, 0x0); + DUMP_REG(sdh, ERROR_INT_STAT, 0x0); + DUMP_REG(sdh, NORMAL_INT_STAT_EN, 0x0); + DUMP_REG(sdh, ERROR_INT_STAT_EN, 0x0); + DUMP_REG(sdh, NORMAL_INT_SIGNAL_EN, 0x0); + + DUMP_REG(sdh, ERROR_INT_SIGNAL_EN, 0x0); + DUMP_REG(sdh, AUTO_CMD_STAT, 0x0); + DUMP_REG(sdh, HOST_CTRL2, 0x0); + DUMP_REG(sdh, CAPABILITIES1, 0x276EC898); + DUMP_REG(sdh, CAPABILITIES2, 0x08008077); + DUMP_REG(sdh, CURR_CAPABILITIES1, 0x0); + DUMP_REG(sdh, CURR_CAPABILITIES2, 0x0); + DUMP_REG(sdh, FORCE_AUTO_CMD_STAT, 0x0); + DUMP_REG(sdh, FORCE_ERROR_INT_STAT, 0x0); + DUMP_REG(sdh, ADMA_ERR_STAT, 0x0); + DUMP_REG(sdh, ADMA_SA_LOW, 0x0); + DUMP_REG(sdh, PRESET_INIT, 0x0); + DUMP_REG(sdh, PRESET_DS, 0x0); + DUMP_REG(sdh, PRESET_HS, 0x0); + DUMP_REG(sdh, PRESET_SDR12, 0x0); + DUMP_REG(sdh, PRESET_SDR25, 0x0); + DUMP_REG(sdh, PRESET_SDR50, 0x0); + DUMP_REG(sdh, PRESET_SDR104, 0x0); + DUMP_REG(sdh, PRESET_DDR50, 0x0); + DUMP_REG(sdh, PRESET_UHS2, 0x0); + DUMP_REG(sdh, P_EMBEDDED_CNTRL, 0x0F6C); + DUMP_REG(sdh, P_VENDOR_SPECIFIC_AREA, 0x0500); + DUMP_REG(sdh, P_VENDOR2_SPECIFIC_AREA, 0x0180); + DUMP_REG(sdh, SLOT_INTR_STATUS, 0x0000); + DUMP_REG(sdh, HOST_CNTRL_VERS, 0x0005); + DUMP_REG(sdh, EMBEDDED_CTRL, 0x00000000); + DUMP_REG(sdh, MSHC_VER_ID, 0x3138302A); + DUMP_REG(sdh, MSHC_VER_TYPE, 0x67612A2A); + DUMP_REG(sdh, MSHC_CTRL, 0x01); + DUMP_REG(sdh, MBIU_CTRL, 0x0F); + DUMP_REG(sdh, EMMC_CTRL, 0x000C); + DUMP_REG(sdh, BOOT_CTRL, 0x0000); + + DUMP_REG(sdh, AT_CTRL, 0x03000005); + DUMP_REG(sdh, AT_STAT, 0x00000006); + DUMP_REG(sdh, CQCAP, 0x000030C8); + SDH_DBG_PRINT("========================================================================\n"); +} + +void SDH_Reset(SDH_T *sdh, uint8_t u8Mask) +{ + /* Wait max 100 ms */ + unsigned int timeout = 100; + + sdh->SW_RST |= u8Mask; + while (sdh->SW_RST & u8Mask) + { + if (timeout == 0) + { + SDH_DBG_PRINT("SD Reset fail\n"); + return; + } + timeout--; + DelayMicrosecond(1000); + } +} + +void SDH_SetPower(SDH_T *sdh, uint32_t u32OnOff) +{ + if (u32OnOff) + { + /* Power on VDD1 */ + sdh->S_PWR_CTRL.SD_BUS_PWR_VDD1 = 1; + + /* Set 3.3v for EMMC, SD and */ + sdh->S_PWR_CTRL.SD_BUS_VOL_VDD1 = 7; + } + else + { + /* Power off VDD1 */ + sdh->S_PWR_CTRL.SD_BUS_PWR_VDD1 = 0; + + /* Set 0v for EMMC, SD and */ + sdh->S_PWR_CTRL.SD_BUS_VOL_VDD1 = 0; + } +} + +uint32_t SDH_SetClock(SDH_T *sdh, uint32_t u32SrcFreqInHz, uint32_t u32ExceptedFreqInHz) +{ + uint32_t timeout; + uint32_t div; + + if (u32ExceptedFreqInHz == 0) + goto exit_SDH_SetClock; + + /* Wait max 20 ms */ + timeout = 200; + while (sdh->PSTATE & 0x3) //(SDH_CMD_INHIBIT | SDH_DATA_INHIBIT)) + { + if (timeout == 0) + { + SDH_DBG_PRINT("Timeout to wait cmd & data inhibit\n"); + goto exit_SDH_SetClock; + } + timeout--; + DelayMicrosecond(100); + } + /* Shutdown clocks. */ + sdh->CLK_CTRL = 0; + DelayMicrosecond(1000); + + div = (u32SrcFreqInHz / 2) / u32ExceptedFreqInHz; + if (div > 0) + { + while ((u32SrcFreqInHz / (2 * div)) > u32ExceptedFreqInHz) + { + div++; + } + } + + sdh->S_CLK_CTRL.FREQ_SEL = div & 0xff; + sdh->S_CLK_CTRL.UPPER_FREQ_SEL = (div >> 8) & 0x3; + + sdh->S_CLK_CTRL.INTERNAL_CLK_EN = 1; + + /* Wait stable */ + /* Wait max 20 ms */ + timeout = 200; + while (!sdh->S_CLK_CTRL.INTERNAL_CLK_STABLE) + { + if (timeout == 0) + { + SDH_DBG_PRINT("Timeout to wait CLK stable.\n"); + goto exit_SDH_SetClock; + } + timeout--; + DelayMicrosecond(100); + } + + /* Enable SD CLK */ + sdh->S_CLK_CTRL.SD_CLK_EN = 1; + + return (div == 0) ? u32SrcFreqInHz : u32SrcFreqInHz / (2 * div); + +exit_SDH_SetClock: + + sdh->CLK_CTRL = 0; + + return 0; +} + +#define SDH_CMD_MAX_TIMEOUT 3200 +#define SDH_CMD_DEFAULT_TIMEOUT 100 +#define SDH_MAX_DIV_SPEC_300 2046 + +int SD_GetBusStatus(SDH_T *sdh, uint32_t mask) +{ + volatile unsigned int time = 0; + volatile unsigned int cmd_timeout = SDH_CMD_DEFAULT_TIMEOUT; + + while (sdh->PSTATE & mask) + { + if (time >= cmd_timeout) + { + if (2 * cmd_timeout <= SDH_CMD_MAX_TIMEOUT) + { + cmd_timeout += cmd_timeout; + } + else + { + return -1; + } + } + DelayMicrosecond(1000); + time++; + } + return 0; +} + +int SDH_SetBusWidth(SDH_T *sdh, uint32_t u32BusWidth) +{ + switch (u32BusWidth) + { + case 1: + sdh->S_HOST_CTRL1.DAT_XFER_WIDTH = 0; + sdh->S_HOST_CTRL1.EXT_DAT_XFER = 0; + break; + case 4: + sdh->S_HOST_CTRL1.DAT_XFER_WIDTH = 1; + sdh->S_HOST_CTRL1.EXT_DAT_XFER = 0; + break; + case 8: + sdh->S_HOST_CTRL1.DAT_XFER_WIDTH = 1; + sdh->S_HOST_CTRL1.EXT_DAT_XFER = 1; + break; + } + return 0; +} + +/*@}*/ /* end of group SDH_EXPORTED_FUNCTIONS */ + +/*@}*/ /* end of group SDH_Driver */ + +/*@}*/ /* end of group Standard_Driver */ + diff --git a/bsp/nuvoton/libraries/ma35/StdDriver/src/nu_spi.c b/bsp/nuvoton/libraries/ma35/StdDriver/src/nu_spi.c new file mode 100644 index 0000000000..e4bc1b397c --- /dev/null +++ b/bsp/nuvoton/libraries/ma35/StdDriver/src/nu_spi.c @@ -0,0 +1,1313 @@ +/**************************************************************************//** + * @file spi.c + * @brief SPI driver source file + * + * SPDX-License-Identifier: Apache-2.0 + * @copyright (C) 2020 Nuvoton Technology Corp. All rights reserved. + *****************************************************************************/ +#include "NuMicro.h" + +/** @addtogroup Standard_Driver Standard Driver + @{ +*/ + +/** @addtogroup SPI_Driver SPI Driver + @{ +*/ + + +/** @addtogroup SPI_EXPORTED_FUNCTIONS SPI Exported Functions + @{ +*/ +static uint32_t SPII2S_GetSourceClockFreq(SPI_T *i2s); + +/** + * @brief This function make SPI module be ready to transfer. + * @param[in] spi The pointer of the specified SPI module. + * @param[in] u32MasterSlave Decides the SPI module is operating in master mode or in slave mode. (SPI_SLAVE, SPI_MASTER) + * @param[in] u32SPIMode Decides the transfer timing. (SPI_MODE_0, SPI_MODE_1, SPI_MODE_2, SPI_MODE_3) + * @param[in] u32DataWidth Decides the data width of a SPI transaction. + * @param[in] u32BusClock The expected frequency of SPI bus clock in Hz. + * @return Actual frequency of SPI peripheral clock. + * @details By default, the SPI transfer sequence is MSB first, the slave selection signal is active low and the automatic + * slave selection function is disabled. + * In Slave mode, the u32BusClock shall be NULL and the SPI clock divider setting will be 0. + * The actual clock rate may be different from the target SPI clock rate. + * For example, if the SPI source clock rate is 12 MHz and the target SPI bus clock rate is 7 MHz, the + * actual SPI clock rate will be 6MHz. + * @note If u32BusClock = 0, DIVIDER setting will be set to the maximum value. + * @note If u32BusClock >= system clock frequency, SPI peripheral clock source will be set to APB clock and DIVIDER will be set to 0. + * @note If u32BusClock >= SPI peripheral clock source, DIVIDER will be set to 0. + * @note In slave mode, the SPI peripheral clock rate will be equal to APB clock rate. + */ +uint32_t SPI_Open(SPI_T *spi, + uint32_t u32MasterSlave, + uint32_t u32SPIMode, + uint32_t u32DataWidth, + uint32_t u32BusClock) +{ + uint32_t u32ClkSrc = 0U, u32Div, u32HCLKFreq, u32RetValue = 0U; + + /* Disable I2S mode */ + spi->I2SCTL &= ~SPI_I2SCTL_I2SEN_Msk; + + if (u32DataWidth == 32U) + { + u32DataWidth = 0U; + } + + /* Get system clock frequency */ + u32HCLKFreq = CLK_GetSYSCLK0Freq(); + + if (u32MasterSlave == SPI_MASTER) + { + /* Default setting: slave selection signal is active low; disable automatic slave selection function. */ + spi->SSCTL = SPI_SS_ACTIVE_LOW; + + /* Default setting: MSB first, disable unit transfer interrupt, SP_CYCLE = 0. */ + spi->CTL = u32MasterSlave | (u32DataWidth << SPI_CTL_DWIDTH_Pos) | (u32SPIMode) | SPI_CTL_SPIEN_Msk; + + if (u32BusClock >= u32HCLKFreq) + { + /* Select PCLK as the clock source of SPI */ + if (spi == SPI0) + { + CLK->CLKSEL4 = (CLK->CLKSEL4 & (~CLK_CLKSEL4_SPI0SEL_Msk)) | CLK_CLKSEL4_SPI0SEL_PCLK1; + } + else if (spi == SPI1) + { + CLK->CLKSEL4 = (CLK->CLKSEL4 & (~CLK_CLKSEL4_SPI1SEL_Msk)) | CLK_CLKSEL4_SPI1SEL_PCLK2; + } + else if (spi == SPI2) + { + CLK->CLKSEL4 = (CLK->CLKSEL4 & (~CLK_CLKSEL4_SPI2SEL_Msk)) | CLK_CLKSEL4_SPI2SEL_PCLK1; + } + else + { + CLK->CLKSEL4 = (CLK->CLKSEL4 & (~CLK_CLKSEL4_SPI3SEL_Msk)) | CLK_CLKSEL4_SPI3SEL_PCLK2; + } + } + + /* Check clock source of SPI */ + if (spi == SPI0) + { + if ((CLK->CLKSEL4 & CLK_CLKSEL4_SPI0SEL_Msk) == CLK_CLKSEL4_SPI0SEL_APLL) + { + u32ClkSrc = CLK_GetPLLClockFreq(APLL); /* Clock source is APLL */ + } + else if ((CLK->CLKSEL4 & CLK_CLKSEL4_SPI0SEL_Msk) == CLK_CLKSEL4_SPI0SEL_PCLK1) + { + /* Clock source is PCLK1 */ + u32ClkSrc = CLK_GetPCLK1Freq(); + } + } + else if (spi == SPI1) + { + if ((CLK->CLKSEL4 & CLK_CLKSEL4_SPI1SEL_Msk) == CLK_CLKSEL4_SPI1SEL_APLL) + { + u32ClkSrc = CLK_GetPLLClockFreq(APLL); /* Clock source is APLL */ + } + else if ((CLK->CLKSEL4 & CLK_CLKSEL4_SPI1SEL_Msk) == CLK_CLKSEL4_SPI1SEL_PCLK2) + { + /* Clock source is PCLK2 */ + u32ClkSrc = CLK_GetPCLK2Freq(); + } + } + else if (spi == SPI2) + { + if ((CLK->CLKSEL4 & CLK_CLKSEL4_SPI2SEL_Msk) == CLK_CLKSEL4_SPI2SEL_APLL) + { + u32ClkSrc = CLK_GetPLLClockFreq(APLL); /* Clock source is APLL */ + } + else if ((CLK->CLKSEL4 & CLK_CLKSEL4_SPI2SEL_Msk) == CLK_CLKSEL4_SPI2SEL_PCLK1) + { + u32ClkSrc = CLK_GetPCLK1Freq(); + } + } + else + { + if ((CLK->CLKSEL4 & CLK_CLKSEL4_SPI3SEL_Msk) == CLK_CLKSEL4_SPI3SEL_APLL) + { + u32ClkSrc = CLK_GetPLLClockFreq(APLL); /* Clock source is APLL */ + } + else if ((CLK->CLKSEL4 & CLK_CLKSEL4_SPI3SEL_Msk) == CLK_CLKSEL4_SPI3SEL_PCLK2) + { + /* Clock source is PCLK2 */ + u32ClkSrc = CLK_GetPCLK2Freq(); + } + } + + if (u32BusClock >= u32HCLKFreq) + { + /* Set DIVIDER = 0 */ + spi->CLKDIV = 0U; + /* Return master peripheral clock rate */ + u32RetValue = u32ClkSrc; + } + else if (u32BusClock >= u32ClkSrc) + { + /* Set DIVIDER = 0 */ + spi->CLKDIV = 0U; + /* Return master peripheral clock rate */ + u32RetValue = u32ClkSrc; + } + else if (u32BusClock == 0U) + { + /* Set DIVIDER to the maximum value 0xFF. f_spi = f_spi_clk_src / (DIVIDER + 1) */ + spi->CLKDIV |= SPI_CLKDIV_DIVIDER_Msk; + /* Return master peripheral clock rate */ + u32RetValue = (u32ClkSrc / (0xFFU + 1U)); + } + else + { + u32Div = (((u32ClkSrc * 10U) / u32BusClock + 5U) / 10U) - 1U; /* Round to the nearest integer */ + if (u32Div > 0xFFU) + { + u32Div = 0xFFU; + spi->CLKDIV |= SPI_CLKDIV_DIVIDER_Msk; + /* Return master peripheral clock rate */ + u32RetValue = (u32ClkSrc / (0xFFU + 1U)); + } + else + { + spi->CLKDIV = (spi->CLKDIV & (~SPI_CLKDIV_DIVIDER_Msk)) | (u32Div << SPI_CLKDIV_DIVIDER_Pos); + /* Return master peripheral clock rate */ + u32RetValue = (u32ClkSrc / (u32Div + 1U)); + } + } + } + else /* For slave mode, force the SPI peripheral clock rate to equal APB clock rate. */ + { + /* Default setting: slave selection signal is low level active. */ + spi->SSCTL = SPI_SS_ACTIVE_LOW; + + /* Default setting: MSB first, disable unit transfer interrupt, SP_CYCLE = 0. */ + spi->CTL = u32MasterSlave | (u32DataWidth << SPI_CTL_DWIDTH_Pos) | (u32SPIMode) | SPI_CTL_SPIEN_Msk; + + /* Set DIVIDER = 0 */ + spi->CLKDIV = 0U; + + /* Select PCLK as the clock source of SPI */ + if (spi == SPI0) + { + CLK->CLKSEL4 = (CLK->CLKSEL4 & (~CLK_CLKSEL4_SPI0SEL_Msk)) | CLK_CLKSEL4_SPI0SEL_PCLK1; + /* Return slave peripheral clock rate */ + u32RetValue = CLK_GetPCLK1Freq(); + } + else if (spi == SPI1) + { + CLK->CLKSEL4 = (CLK->CLKSEL4 & (~CLK_CLKSEL4_SPI1SEL_Msk)) | CLK_CLKSEL4_SPI1SEL_PCLK2; + /* Return slave peripheral clock rate */ + u32RetValue = CLK_GetPCLK2Freq(); + } + else if (spi == SPI2) + { + CLK->CLKSEL4 = (CLK->CLKSEL4 & (~CLK_CLKSEL4_SPI2SEL_Msk)) | CLK_CLKSEL4_SPI2SEL_PCLK1; + /* Return slave peripheral clock rate */ + u32RetValue = CLK_GetPCLK1Freq(); + } + else + { + CLK->CLKSEL4 = (CLK->CLKSEL4 & (~CLK_CLKSEL4_SPI3SEL_Msk)) | CLK_CLKSEL4_SPI3SEL_PCLK2; + /* Return slave peripheral clock rate */ + u32RetValue = CLK_GetPCLK2Freq(); + } + } + + return u32RetValue; +} + +/** + * @brief Disable SPI controller. + * @param[in] spi The pointer of the specified SPI module. + * @return None + * @details This function will reset SPI controller. + */ +void SPI_Close(SPI_T *spi) +{ + if (spi == SPI0) + { + /* Reset SPI */ + SYS->IPRST1 |= SYS_IPRST1_SPI0RST_Msk; + SYS->IPRST1 &= ~SYS_IPRST1_SPI0RST_Msk; + } + else if (spi == SPI1) + { + /* Reset SPI */ + SYS->IPRST1 |= SYS_IPRST1_SPI1RST_Msk; + SYS->IPRST1 &= ~SYS_IPRST1_SPI1RST_Msk; + } + else if (spi == SPI2) + { + /* Reset SPI */ + SYS->IPRST1 |= SYS_IPRST1_SPI2RST_Msk; + SYS->IPRST1 &= ~SYS_IPRST1_SPI2RST_Msk; + } + else + { + /* Reset SPI */ + SYS->IPRST2 |= SYS_IPRST2_SPI3RST_Msk; + SYS->IPRST2 &= ~SYS_IPRST2_SPI3RST_Msk; + } +} + +/** + * @brief Clear RX FIFO buffer. + * @param[in] spi The pointer of the specified SPI module. + * @return None + * @details This function will clear SPI RX FIFO buffer. The RXEMPTY (SPI_STATUS[8]) will be set to 1. + */ +void SPI_ClearRxFIFO(SPI_T *spi) +{ + spi->FIFOCTL |= SPI_FIFOCTL_RXFBCLR_Msk; +} + +/** + * @brief Clear TX FIFO buffer. + * @param[in] spi The pointer of the specified SPI module. + * @return None + * @details This function will clear SPI TX FIFO buffer. The TXEMPTY (SPI_STATUS[16]) will be set to 1. + * @note The TX shift register will not be cleared. + */ +void SPI_ClearTxFIFO(SPI_T *spi) +{ + spi->FIFOCTL |= SPI_FIFOCTL_TXFBCLR_Msk; +} + +/** + * @brief Disable the automatic slave selection function. + * @param[in] spi The pointer of the specified SPI module. + * @return None + * @details This function will disable the automatic slave selection function and set slave selection signal to inactive state. + */ +void SPI_DisableAutoSS(SPI_T *spi) +{ + spi->SSCTL &= ~(SPI_SSCTL_AUTOSS_Msk | SPI_SSCTL_SS_Msk); +} + +/** + * @brief Enable the automatic slave selection function. + * @param[in] spi The pointer of the specified SPI module. + * @param[in] u32SSPinMask Specifies slave selection pins. (SPI_SS) + * @param[in] u32ActiveLevel Specifies the active level of slave selection signal. (SPI_SS_ACTIVE_HIGH, SPI_SS_ACTIVE_LOW) + * @return None + * @details This function will enable the automatic slave selection function. Only available in Master mode. + * The slave selection pin and the active level will be set in this function. + */ +void SPI_EnableAutoSS(SPI_T *spi, uint32_t u32SSPinMask, uint32_t u32ActiveLevel) +{ + spi->SSCTL = (spi->SSCTL & (~(SPI_SSCTL_AUTOSS_Msk | SPI_SSCTL_SSACTPOL_Msk | SPI_SSCTL_SS_Msk))) | (u32SSPinMask | u32ActiveLevel | SPI_SSCTL_AUTOSS_Msk); +} + +/** + * @brief Set the SPI bus clock. + * @param[in] spi The pointer of the specified SPI module. + * @param[in] u32BusClock The expected frequency of SPI bus clock in Hz. + * @return Actual frequency of SPI bus clock. + * @details This function is only available in Master mode. The actual clock rate may be different from the target SPI bus clock rate. + * For example, if the SPI source clock rate is 12 MHz and the target SPI bus clock rate is 7 MHz, the actual SPI bus clock + * rate will be 6 MHz. + * @note If u32BusClock = 0, DIVIDER setting will be set to the maximum value. + * @note If u32BusClock >= system clock frequency, SPI peripheral clock source will be set to APB clock and DIVIDER will be set to 0. + * @note If u32BusClock >= SPI peripheral clock source, DIVIDER will be set to 0. + */ +uint32_t SPI_SetBusClock(SPI_T *spi, uint32_t u32BusClock) +{ + uint32_t u32ClkSrc = 0, u32HCLKFreq; + uint32_t u32Div, u32RetValue; + + /* Get system clock frequency */ + u32HCLKFreq = CLK_GetSYSCLK0Freq(); + + if (u32BusClock >= u32HCLKFreq) + { + /* Select PCLK as the clock source of SPI */ + if (spi == SPI0) + CLK->CLKSEL4 = (CLK->CLKSEL4 & (~CLK_CLKSEL4_SPI0SEL_Msk)) | CLK_CLKSEL4_SPI0SEL_PCLK1; + else if (spi == SPI1) + CLK->CLKSEL4 = (CLK->CLKSEL4 & (~CLK_CLKSEL4_SPI1SEL_Msk)) | CLK_CLKSEL4_SPI1SEL_PCLK2; + else if (spi == SPI2) + CLK->CLKSEL4 = (CLK->CLKSEL4 & (~CLK_CLKSEL4_SPI2SEL_Msk)) | CLK_CLKSEL4_SPI2SEL_PCLK1; + else + CLK->CLKSEL4 = (CLK->CLKSEL4 & (~CLK_CLKSEL4_SPI3SEL_Msk)) | CLK_CLKSEL4_SPI3SEL_PCLK2; + } + + /* Check clock source of SPI */ + if (spi == SPI0) + { + if ((CLK->CLKSEL4 & CLK_CLKSEL4_SPI0SEL_Msk) == CLK_CLKSEL4_SPI0SEL_APLL) + { + u32ClkSrc = CLK_GetPLLClockFreq(APLL); /* Clock source is APLL */ + } + else if ((CLK->CLKSEL4 & CLK_CLKSEL4_SPI0SEL_Msk) == CLK_CLKSEL4_SPI0SEL_PCLK1) + { + /* Clock source is PCLK1 */ + u32ClkSrc = CLK_GetPCLK1Freq(); + } + } + else if (spi == SPI1) + { + if ((CLK->CLKSEL4 & CLK_CLKSEL4_SPI1SEL_Msk) == CLK_CLKSEL4_SPI1SEL_APLL) + { + u32ClkSrc = CLK_GetPLLClockFreq(APLL); /* Clock source is APLL */ + } + else if ((CLK->CLKSEL4 & CLK_CLKSEL4_SPI1SEL_Msk) == CLK_CLKSEL4_SPI1SEL_PCLK2) + { + /* Clock source is PCLK2 */ + u32ClkSrc = CLK_GetPCLK2Freq(); + } + } + else if (spi == SPI2) + { + if ((CLK->CLKSEL4 & CLK_CLKSEL4_SPI2SEL_Msk) == CLK_CLKSEL4_SPI2SEL_APLL) + { + u32ClkSrc = CLK_GetPLLClockFreq(APLL); /* Clock source is APLL */ + } + else if ((CLK->CLKSEL4 & CLK_CLKSEL4_SPI2SEL_Msk) == CLK_CLKSEL4_SPI2SEL_PCLK1) + { + /* Clock source is PCLK1 */ + u32ClkSrc = CLK_GetPCLK1Freq(); + } + } + else + { + if ((CLK->CLKSEL4 & CLK_CLKSEL4_SPI3SEL_Msk) == CLK_CLKSEL4_SPI3SEL_APLL) + { + u32ClkSrc = CLK_GetPLLClockFreq(APLL); /* Clock source is APLL */ + } + else if ((CLK->CLKSEL4 & CLK_CLKSEL4_SPI3SEL_Msk) == CLK_CLKSEL4_SPI3SEL_PCLK2) + { + /* Clock source is PCLK2 */ + u32ClkSrc = CLK_GetPCLK2Freq(); + } + } + + if (u32BusClock >= u32HCLKFreq) + { + /* Set DIVIDER = 0 */ + spi->CLKDIV = 0U; + /* Return master peripheral clock rate */ + u32RetValue = u32ClkSrc; + } + else if (u32BusClock >= u32ClkSrc) + { + /* Set DIVIDER = 0 */ + spi->CLKDIV = 0U; + /* Return master peripheral clock rate */ + u32RetValue = u32ClkSrc; + } + else if (u32BusClock == 0U) + { + /* Set DIVIDER to the maximum value 0xFF. f_spi = f_spi_clk_src / (DIVIDER + 1) */ + spi->CLKDIV |= SPI_CLKDIV_DIVIDER_Msk; + /* Return master peripheral clock rate */ + u32RetValue = (u32ClkSrc / (0xFFU + 1U)); + } + else + { + u32Div = (((u32ClkSrc * 10U) / u32BusClock + 5U) / 10U) - 1U; /* Round to the nearest integer */ + if (u32Div > 0x1FFU) + { + u32Div = 0x1FFU; + spi->CLKDIV |= SPI_CLKDIV_DIVIDER_Msk; + /* Return master peripheral clock rate */ + u32RetValue = (u32ClkSrc / (0xFFU + 1U)); + } + else + { + spi->CLKDIV = (spi->CLKDIV & (~SPI_CLKDIV_DIVIDER_Msk)) | (u32Div << SPI_CLKDIV_DIVIDER_Pos); + /* Return master peripheral clock rate */ + u32RetValue = (u32ClkSrc / (u32Div + 1U)); + } + } + + return u32RetValue; +} + +/** + * @brief Configure FIFO threshold setting. + * @param[in] spi The pointer of the specified SPI module. + * @param[in] u32TxThreshold Decides the TX FIFO threshold. It could be 0 ~ 3. If data width is 8~16 bits, it could be 0 ~ 7. + * @param[in] u32RxThreshold Decides the RX FIFO threshold. It could be 0 ~ 3. If data width is 8~16 bits, it could be 0 ~ 7. + * @return None + * @details Set TX FIFO threshold and RX FIFO threshold configurations. + */ +void SPI_SetFIFO(SPI_T *spi, uint32_t u32TxThreshold, uint32_t u32RxThreshold) +{ + spi->FIFOCTL = (spi->FIFOCTL & ~(SPI_FIFOCTL_TXTH_Msk | SPI_FIFOCTL_RXTH_Msk)) | + (u32TxThreshold << SPI_FIFOCTL_TXTH_Pos) | + (u32RxThreshold << SPI_FIFOCTL_RXTH_Pos); +} + +/** + * @brief Get the actual frequency of SPI bus clock. Only available in Master mode. + * @param[in] spi The pointer of the specified SPI module. + * @return Actual SPI bus clock frequency in Hz. + * @details This function will calculate the actual SPI bus clock rate according to the SPInSEL and DIVIDER settings. Only available in Master mode. + */ +uint32_t SPI_GetBusClock(SPI_T *spi) +{ + uint32_t u32Div; + uint32_t u32ClkSrc = 0; + + /* Get DIVIDER setting */ + u32Div = (spi->CLKDIV & SPI_CLKDIV_DIVIDER_Msk) >> SPI_CLKDIV_DIVIDER_Pos; + + /* Check clock source of SPI */ + if (spi == SPI0) + { + if ((CLK->CLKSEL4 & CLK_CLKSEL4_SPI0SEL_Msk) == CLK_CLKSEL4_SPI0SEL_APLL) + { + u32ClkSrc = CLK_GetPLLClockFreq(APLL); /* Clock source is APLL */ + } + else if ((CLK->CLKSEL4 & CLK_CLKSEL4_SPI0SEL_Msk) == CLK_CLKSEL4_SPI0SEL_PCLK1) + { + /* Clock source is PCLK1 */ + u32ClkSrc = CLK_GetPCLK1Freq(); + } + } + else if (spi == SPI1) + { + if ((CLK->CLKSEL4 & CLK_CLKSEL4_SPI1SEL_Msk) == CLK_CLKSEL4_SPI1SEL_APLL) + { + u32ClkSrc = CLK_GetPLLClockFreq(APLL); /* Clock source is APLL */ + } + else if ((CLK->CLKSEL4 & CLK_CLKSEL4_SPI1SEL_Msk) == CLK_CLKSEL4_SPI1SEL_PCLK2) + { + /* Clock source is PCLK2 */ + u32ClkSrc = CLK_GetPCLK2Freq(); + } + } + else if (spi == SPI2) + { + if ((CLK->CLKSEL4 & CLK_CLKSEL4_SPI2SEL_Msk) == CLK_CLKSEL4_SPI2SEL_APLL) + { + u32ClkSrc = CLK_GetPLLClockFreq(APLL); /* Clock source is APLL */ + } + else if ((CLK->CLKSEL4 & CLK_CLKSEL4_SPI2SEL_Msk) == CLK_CLKSEL4_SPI2SEL_PCLK1) + { + /* Clock source is PCLK1 */ + u32ClkSrc = CLK_GetPCLK1Freq(); + } + } + else + { + if ((CLK->CLKSEL4 & CLK_CLKSEL4_SPI3SEL_Msk) == CLK_CLKSEL4_SPI3SEL_APLL) + { + u32ClkSrc = CLK_GetPLLClockFreq(APLL); /* Clock source is APLL */ + } + else if ((CLK->CLKSEL4 & CLK_CLKSEL4_SPI3SEL_Msk) == CLK_CLKSEL4_SPI3SEL_PCLK2) + { + /* Clock source is PCLK2 */ + u32ClkSrc = CLK_GetPCLK2Freq(); + } + } + + /* Return SPI bus clock rate */ + return (u32ClkSrc / (u32Div + 1U)); +} + +/** + * @brief Enable interrupt function. + * @param[in] spi The pointer of the specified SPI module. + * @param[in] u32Mask The combination of all related interrupt enable bits. + * Each bit corresponds to a interrupt enable bit. + * This parameter decides which interrupts will be enabled. It is combination of: + * - \ref SPI_UNIT_INT_MASK + * - \ref SPI_SSACT_INT_MASK + * - \ref SPI_SSINACT_INT_MASK + * - \ref SPI_SLVUR_INT_MASK + * - \ref SPI_SLVBE_INT_MASK + * - \ref SPI_TXUF_INT_MASK + * - \ref SPI_FIFO_TXTH_INT_MASK + * - \ref SPI_FIFO_RXTH_INT_MASK + * - \ref SPI_FIFO_RXOV_INT_MASK + * - \ref SPI_FIFO_RXTO_INT_MASK + * + * @return None + * @details Enable SPI related interrupts specified by u32Mask parameter. + */ +void SPI_EnableInt(SPI_T *spi, uint32_t u32Mask) +{ + /* Enable unit transfer interrupt flag */ + if ((u32Mask & SPI_UNIT_INT_MASK) == SPI_UNIT_INT_MASK) + { + spi->CTL |= SPI_CTL_UNITIEN_Msk; + } + + /* Enable slave selection signal active interrupt flag */ + if ((u32Mask & SPI_SSACT_INT_MASK) == SPI_SSACT_INT_MASK) + { + spi->SSCTL |= SPI_SSCTL_SSACTIEN_Msk; + } + + /* Enable slave selection signal inactive interrupt flag */ + if ((u32Mask & SPI_SSINACT_INT_MASK) == SPI_SSINACT_INT_MASK) + { + spi->SSCTL |= SPI_SSCTL_SSINAIEN_Msk; + } + + /* Enable slave TX under run interrupt flag */ + if ((u32Mask & SPI_SLVUR_INT_MASK) == SPI_SLVUR_INT_MASK) + { + spi->SSCTL |= SPI_SSCTL_SLVURIEN_Msk; + } + + /* Enable slave bit count error interrupt flag */ + if ((u32Mask & SPI_SLVBE_INT_MASK) == SPI_SLVBE_INT_MASK) + { + spi->SSCTL |= SPI_SSCTL_SLVBEIEN_Msk; + } + + /* Enable slave TX underflow interrupt flag */ + if ((u32Mask & SPI_TXUF_INT_MASK) == SPI_TXUF_INT_MASK) + { + spi->FIFOCTL |= SPI_FIFOCTL_TXUFIEN_Msk; + } + + /* Enable TX threshold interrupt flag */ + if ((u32Mask & SPI_FIFO_TXTH_INT_MASK) == SPI_FIFO_TXTH_INT_MASK) + { + spi->FIFOCTL |= SPI_FIFOCTL_TXTHIEN_Msk; + } + + /* Enable RX threshold interrupt flag */ + if ((u32Mask & SPI_FIFO_RXTH_INT_MASK) == SPI_FIFO_RXTH_INT_MASK) + { + spi->FIFOCTL |= SPI_FIFOCTL_RXTHIEN_Msk; + } + + /* Enable RX overrun interrupt flag */ + if ((u32Mask & SPI_FIFO_RXOV_INT_MASK) == SPI_FIFO_RXOV_INT_MASK) + { + spi->FIFOCTL |= SPI_FIFOCTL_RXOVIEN_Msk; + } + + /* Enable RX time-out interrupt flag */ + if ((u32Mask & SPI_FIFO_RXTO_INT_MASK) == SPI_FIFO_RXTO_INT_MASK) + { + spi->FIFOCTL |= SPI_FIFOCTL_RXTOIEN_Msk; + } +} + +/** + * @brief Disable interrupt function. + * @param[in] spi The pointer of the specified SPI module. + * @param[in] u32Mask The combination of all related interrupt enable bits. + * Each bit corresponds to a interrupt bit. + * This parameter decides which interrupts will be disabled. It is combination of: + * - \ref SPI_UNIT_INT_MASK + * - \ref SPI_SSACT_INT_MASK + * - \ref SPI_SSINACT_INT_MASK + * - \ref SPI_SLVUR_INT_MASK + * - \ref SPI_SLVBE_INT_MASK + * - \ref SPI_TXUF_INT_MASK + * - \ref SPI_FIFO_TXTH_INT_MASK + * - \ref SPI_FIFO_RXTH_INT_MASK + * - \ref SPI_FIFO_RXOV_INT_MASK + * - \ref SPI_FIFO_RXTO_INT_MASK + * + * @return None + * @details Disable SPI related interrupts specified by u32Mask parameter. + */ +void SPI_DisableInt(SPI_T *spi, uint32_t u32Mask) +{ + /* Disable unit transfer interrupt flag */ + if ((u32Mask & SPI_UNIT_INT_MASK) == SPI_UNIT_INT_MASK) + { + spi->CTL &= ~SPI_CTL_UNITIEN_Msk; + } + + /* Disable slave selection signal active interrupt flag */ + if ((u32Mask & SPI_SSACT_INT_MASK) == SPI_SSACT_INT_MASK) + { + spi->SSCTL &= ~SPI_SSCTL_SSACTIEN_Msk; + } + + /* Disable slave selection signal inactive interrupt flag */ + if ((u32Mask & SPI_SSINACT_INT_MASK) == SPI_SSINACT_INT_MASK) + { + spi->SSCTL &= ~SPI_SSCTL_SSINAIEN_Msk; + } + + /* Disable slave TX under run interrupt flag */ + if ((u32Mask & SPI_SLVUR_INT_MASK) == SPI_SLVUR_INT_MASK) + { + spi->SSCTL &= ~SPI_SSCTL_SLVURIEN_Msk; + } + + /* Disable slave bit count error interrupt flag */ + if ((u32Mask & SPI_SLVBE_INT_MASK) == SPI_SLVBE_INT_MASK) + { + spi->SSCTL &= ~SPI_SSCTL_SLVBEIEN_Msk; + } + + /* Disable slave TX underflow interrupt flag */ + if ((u32Mask & SPI_TXUF_INT_MASK) == SPI_TXUF_INT_MASK) + { + spi->FIFOCTL &= ~SPI_FIFOCTL_TXUFIEN_Msk; + } + + /* Disable TX threshold interrupt flag */ + if ((u32Mask & SPI_FIFO_TXTH_INT_MASK) == SPI_FIFO_TXTH_INT_MASK) + { + spi->FIFOCTL &= ~SPI_FIFOCTL_TXTHIEN_Msk; + } + + /* Disable RX threshold interrupt flag */ + if ((u32Mask & SPI_FIFO_RXTH_INT_MASK) == SPI_FIFO_RXTH_INT_MASK) + { + spi->FIFOCTL &= ~SPI_FIFOCTL_RXTHIEN_Msk; + } + + /* Disable RX overrun interrupt flag */ + if ((u32Mask & SPI_FIFO_RXOV_INT_MASK) == SPI_FIFO_RXOV_INT_MASK) + { + spi->FIFOCTL &= ~SPI_FIFOCTL_RXOVIEN_Msk; + } + + /* Disable RX time-out interrupt flag */ + if ((u32Mask & SPI_FIFO_RXTO_INT_MASK) == SPI_FIFO_RXTO_INT_MASK) + { + spi->FIFOCTL &= ~SPI_FIFOCTL_RXTOIEN_Msk; + } +} + +/** + * @brief Get interrupt flag. + * @param[in] spi The pointer of the specified SPI module. + * @param[in] u32Mask The combination of all related interrupt sources. + * Each bit corresponds to a interrupt source. + * This parameter decides which interrupt flags will be read. It is combination of: + * - \ref SPI_UNIT_INT_MASK + * - \ref SPI_SSACT_INT_MASK + * - \ref SPI_SSINACT_INT_MASK + * - \ref SPI_SLVUR_INT_MASK + * - \ref SPI_SLVBE_INT_MASK + * - \ref SPI_TXUF_INT_MASK + * - \ref SPI_FIFO_TXTH_INT_MASK + * - \ref SPI_FIFO_RXTH_INT_MASK + * - \ref SPI_FIFO_RXOV_INT_MASK + * - \ref SPI_FIFO_RXTO_INT_MASK + * + * @return Interrupt flags of selected sources. + * @details Get SPI related interrupt flags specified by u32Mask parameter. + */ +uint32_t SPI_GetIntFlag(SPI_T *spi, uint32_t u32Mask) +{ + uint32_t u32IntFlag = 0U, u32TmpVal; + + u32TmpVal = spi->STATUS & SPI_STATUS_UNITIF_Msk; + /* Check unit transfer interrupt flag */ + if ((u32Mask & SPI_UNIT_INT_MASK) && (u32TmpVal)) + { + u32IntFlag |= SPI_UNIT_INT_MASK; + } + + u32TmpVal = spi->STATUS & SPI_STATUS_SSACTIF_Msk; + /* Check slave selection signal active interrupt flag */ + if ((u32Mask & SPI_SSACT_INT_MASK) && (u32TmpVal)) + { + u32IntFlag |= SPI_SSACT_INT_MASK; + } + + u32TmpVal = spi->STATUS & SPI_STATUS_SSINAIF_Msk; + /* Check slave selection signal inactive interrupt flag */ + if ((u32Mask & SPI_SSINACT_INT_MASK) && (u32TmpVal)) + { + u32IntFlag |= SPI_SSINACT_INT_MASK; + } + + u32TmpVal = spi->STATUS & SPI_STATUS_SLVURIF_Msk; + /* Check slave TX under run interrupt flag */ + if ((u32Mask & SPI_SLVUR_INT_MASK) && (u32TmpVal)) + { + u32IntFlag |= SPI_SLVUR_INT_MASK; + } + + u32TmpVal = spi->STATUS & SPI_STATUS_SLVBEIF_Msk; + /* Check slave bit count error interrupt flag */ + if ((u32Mask & SPI_SLVBE_INT_MASK) && (u32TmpVal)) + { + u32IntFlag |= SPI_SLVBE_INT_MASK; + } + + u32TmpVal = spi->STATUS & SPI_STATUS_TXUFIF_Msk; + /* Check slave TX underflow interrupt flag */ + if ((u32Mask & SPI_TXUF_INT_MASK) && (u32TmpVal)) + { + u32IntFlag |= SPI_TXUF_INT_MASK; + } + + u32TmpVal = spi->STATUS & SPI_STATUS_TXTHIF_Msk; + /* Check TX threshold interrupt flag */ + if ((u32Mask & SPI_FIFO_TXTH_INT_MASK) && (u32TmpVal)) + { + u32IntFlag |= SPI_FIFO_TXTH_INT_MASK; + } + + u32TmpVal = spi->STATUS & SPI_STATUS_RXTHIF_Msk; + /* Check RX threshold interrupt flag */ + if ((u32Mask & SPI_FIFO_RXTH_INT_MASK) && (u32TmpVal)) + { + u32IntFlag |= SPI_FIFO_RXTH_INT_MASK; + } + + u32TmpVal = spi->STATUS & SPI_STATUS_RXOVIF_Msk; + /* Check RX overrun interrupt flag */ + if ((u32Mask & SPI_FIFO_RXOV_INT_MASK) && (u32TmpVal)) + { + u32IntFlag |= SPI_FIFO_RXOV_INT_MASK; + } + + u32TmpVal = spi->STATUS & SPI_STATUS_RXTOIF_Msk; + /* Check RX time-out interrupt flag */ + if ((u32Mask & SPI_FIFO_RXTO_INT_MASK) && (u32TmpVal)) + { + u32IntFlag |= SPI_FIFO_RXTO_INT_MASK; + } + + return u32IntFlag; +} + +/** + * @brief Clear interrupt flag. + * @param[in] spi The pointer of the specified SPI module. + * @param[in] u32Mask The combination of all related interrupt sources. + * Each bit corresponds to a interrupt source. + * This parameter decides which interrupt flags will be cleared. It could be the combination of: + * - \ref SPI_UNIT_INT_MASK + * - \ref SPI_SSACT_INT_MASK + * - \ref SPI_SSINACT_INT_MASK + * - \ref SPI_SLVUR_INT_MASK + * - \ref SPI_SLVBE_INT_MASK + * - \ref SPI_TXUF_INT_MASK + * - \ref SPI_FIFO_RXOV_INT_MASK + * - \ref SPI_FIFO_RXTO_INT_MASK + * + * @return None + * @details Clear SPI related interrupt flags specified by u32Mask parameter. + */ +void SPI_ClearIntFlag(SPI_T *spi, uint32_t u32Mask) +{ + if (u32Mask & SPI_UNIT_INT_MASK) + { + spi->STATUS = SPI_STATUS_UNITIF_Msk; /* Clear unit transfer interrupt flag */ + } + + if (u32Mask & SPI_SSACT_INT_MASK) + { + spi->STATUS = SPI_STATUS_SSACTIF_Msk; /* Clear slave selection signal active interrupt flag */ + } + + if (u32Mask & SPI_SSINACT_INT_MASK) + { + spi->STATUS = SPI_STATUS_SSINAIF_Msk; /* Clear slave selection signal inactive interrupt flag */ + } + + if (u32Mask & SPI_SLVUR_INT_MASK) + { + spi->STATUS = SPI_STATUS_SLVURIF_Msk; /* Clear slave TX under run interrupt flag */ + } + + if (u32Mask & SPI_SLVBE_INT_MASK) + { + spi->STATUS = SPI_STATUS_SLVBEIF_Msk; /* Clear slave bit count error interrupt flag */ + } + + if (u32Mask & SPI_TXUF_INT_MASK) + { + spi->STATUS = SPI_STATUS_TXUFIF_Msk; /* Clear slave TX underflow interrupt flag */ + } + + if (u32Mask & SPI_FIFO_RXOV_INT_MASK) + { + spi->STATUS = SPI_STATUS_RXOVIF_Msk; /* Clear RX overrun interrupt flag */ + } + + if (u32Mask & SPI_FIFO_RXTO_INT_MASK) + { + spi->STATUS = SPI_STATUS_RXTOIF_Msk; /* Clear RX time-out interrupt flag */ + } +} + +/** + * @brief Get SPI status. + * @param[in] spi The pointer of the specified SPI module. + * @param[in] u32Mask The combination of all related sources. + * Each bit corresponds to a source. + * This parameter decides which flags will be read. It is combination of: + * - \ref SPI_BUSY_MASK + * - \ref SPI_RX_EMPTY_MASK + * - \ref SPI_RX_FULL_MASK + * - \ref SPI_TX_EMPTY_MASK + * - \ref SPI_TX_FULL_MASK + * - \ref SPI_TXRX_RESET_MASK + * - \ref SPI_SPIEN_STS_MASK + * - \ref SPI_SSLINE_STS_MASK + * + * @return Flags of selected sources. + * @details Get SPI related status specified by u32Mask parameter. + */ +uint32_t SPI_GetStatus(SPI_T *spi, uint32_t u32Mask) +{ + uint32_t u32Flag = 0U, u32TmpValue; + + u32TmpValue = spi->STATUS & SPI_STATUS_BUSY_Msk; + /* Check busy status */ + if ((u32Mask & SPI_BUSY_MASK) && (u32TmpValue)) + { + u32Flag |= SPI_BUSY_MASK; + } + + u32TmpValue = spi->STATUS & SPI_STATUS_RXEMPTY_Msk; + /* Check RX empty flag */ + if ((u32Mask & SPI_RX_EMPTY_MASK) && (u32TmpValue)) + { + u32Flag |= SPI_RX_EMPTY_MASK; + } + + u32TmpValue = spi->STATUS & SPI_STATUS_RXFULL_Msk; + /* Check RX full flag */ + if ((u32Mask & SPI_RX_FULL_MASK) && (u32TmpValue)) + { + u32Flag |= SPI_RX_FULL_MASK; + } + + u32TmpValue = spi->STATUS & SPI_STATUS_TXEMPTY_Msk; + /* Check TX empty flag */ + if ((u32Mask & SPI_TX_EMPTY_MASK) && (u32TmpValue)) + { + u32Flag |= SPI_TX_EMPTY_MASK; + } + + u32TmpValue = spi->STATUS & SPI_STATUS_TXFULL_Msk; + /* Check TX full flag */ + if ((u32Mask & SPI_TX_FULL_MASK) && (u32TmpValue)) + { + u32Flag |= SPI_TX_FULL_MASK; + } + + u32TmpValue = spi->STATUS & SPI_STATUS_TXRXRST_Msk; + /* Check TX/RX reset flag */ + if ((u32Mask & SPI_TXRX_RESET_MASK) && (u32TmpValue)) + { + u32Flag |= SPI_TXRX_RESET_MASK; + } + + u32TmpValue = spi->STATUS & SPI_STATUS_SPIENSTS_Msk; + /* Check SPIEN flag */ + if ((u32Mask & SPI_SPIEN_STS_MASK) && (u32TmpValue)) + { + u32Flag |= SPI_SPIEN_STS_MASK; + } + + u32TmpValue = spi->STATUS & SPI_STATUS_SSLINE_Msk; + /* Check SPIx_SS line status */ + if ((u32Mask & SPI_SSLINE_STS_MASK) && (u32TmpValue)) + { + u32Flag |= SPI_SSLINE_STS_MASK; + } + + return u32Flag; +} + + +/** + * @brief This function is used to get I2S source clock frequency. + * @param[in] i2s The pointer of the specified I2S module. + * @return I2S source clock frequency (Hz). + * @details Return the source clock frequency according to the setting of SPI0SEL (CLKSEL2[27:26]). + */ +static uint32_t SPII2S_GetSourceClockFreq(SPI_T *i2s) +{ + uint32_t u32Freq = 0; + + if (i2s == SPI0) + { + if ((CLK->CLKSEL4 & CLK_CLKSEL4_SPI0SEL_Msk) == CLK_CLKSEL4_SPI0SEL_APLL) + { + u32Freq = CLK_GetPLLClockFreq(APLL); /* Clock source is APLL */ + } + else if ((CLK->CLKSEL4 & CLK_CLKSEL4_SPI0SEL_Msk) == CLK_CLKSEL4_SPI0SEL_PCLK1) + { + /* Clock source is PCLK1 */ + u32Freq = CLK_GetPCLK1Freq(); + } + } + else if (i2s == SPI1) + { + if ((CLK->CLKSEL4 & CLK_CLKSEL4_SPI1SEL_Msk) == CLK_CLKSEL4_SPI1SEL_APLL) + { + u32Freq = CLK_GetPLLClockFreq(APLL); /* Clock source is APLL */ + } + else if ((CLK->CLKSEL4 & CLK_CLKSEL4_SPI1SEL_Msk) == CLK_CLKSEL4_SPI1SEL_PCLK2) + { + /* Clock source is PCLK2 */ + u32Freq = CLK_GetPCLK2Freq(); + } + } + else if (i2s == SPI2) + { + if ((CLK->CLKSEL4 & CLK_CLKSEL4_SPI2SEL_Msk) == CLK_CLKSEL4_SPI2SEL_APLL) + { + u32Freq = CLK_GetPLLClockFreq(APLL); /* Clock source is APLL */ + } + else if ((CLK->CLKSEL4 & CLK_CLKSEL4_SPI2SEL_Msk) == CLK_CLKSEL4_SPI2SEL_PCLK1) + { + /* Clock source is PCLK1 */ + u32Freq = CLK_GetPCLK1Freq(); + } + } + else + { + if ((CLK->CLKSEL4 & CLK_CLKSEL4_SPI3SEL_Msk) == CLK_CLKSEL4_SPI3SEL_APLL) + { + u32Freq = CLK_GetPLLClockFreq(APLL); /* Clock source is APLL */ + } + else if ((CLK->CLKSEL4 & CLK_CLKSEL4_SPI3SEL_Msk) == CLK_CLKSEL4_SPI3SEL_PCLK2) + { + /* Clock source is PCLK2 */ + u32Freq = CLK_GetPCLK2Freq(); + } + } + + return u32Freq; +} + +/** + * @brief This function configures some parameters of I2S interface for general purpose use. + * @param[in] i2s The pointer of the specified I2S module. + * @param[in] u32MasterSlave I2S operation mode. Valid values are listed below. + * - \ref SPII2S_MODE_MASTER + * - \ref SPII2S_MODE_SLAVE + * @param[in] u32SampleRate Sample rate + * @param[in] u32WordWidth Data length. Valid values are listed below. + * - \ref SPII2S_DATABIT_8 + * - \ref SPII2S_DATABIT_16 + * - \ref SPII2S_DATABIT_24 + * - \ref SPII2S_DATABIT_32 + * @param[in] u32Channels Audio format. Valid values are listed below. + * - \ref SPII2S_MONO + * - \ref SPII2S_STEREO + * @param[in] u32DataFormat Data format. Valid values are listed below. + * - \ref SPII2S_FORMAT_I2S + * - \ref SPII2S_FORMAT_MSB + * - \ref SPII2S_FORMAT_PCMA + * - \ref SPII2S_FORMAT_PCMB + * @return Real sample rate of master mode or peripheral clock rate of slave mode. + * @details This function will reset SPI/I2S controller and configure I2S controller according to the input parameters. + * Set TX FIFO threshold to 2 and RX FIFO threshold to 1. Both the TX and RX functions will be enabled. + * The actual sample rate may be different from the target sample rate. The real sample rate will be returned for reference. + * @note In slave mode, the SPI peripheral clock rate will be equal to APB clock rate. + */ +uint32_t SPII2S_Open(SPI_T *i2s, uint32_t u32MasterSlave, uint32_t u32SampleRate, uint32_t u32WordWidth, uint32_t u32Channels, uint32_t u32DataFormat) +{ + uint32_t u32Divider; + uint32_t u32BitRate, u32SrcClk, u32RetValue; + + /* Reset SPI/I2S */ + if (i2s == SPI0) + { + SYS->IPRST1 |= SYS_IPRST1_SPI0RST_Msk; + SYS->IPRST1 &= ~SYS_IPRST1_SPI0RST_Msk; + } + else if (i2s == SPI1) + { + SYS->IPRST1 |= SYS_IPRST1_SPI1RST_Msk; + SYS->IPRST1 &= ~SYS_IPRST1_SPI1RST_Msk; + } + else if (i2s == SPI2) + { + SYS->IPRST1 |= SYS_IPRST1_SPI2RST_Msk; + SYS->IPRST1 &= ~SYS_IPRST1_SPI2RST_Msk; + } + else + { + SYS->IPRST2 |= SYS_IPRST2_SPI3RST_Msk; + SYS->IPRST2 &= ~SYS_IPRST2_SPI3RST_Msk; + } + + /* Configure I2S controller */ + i2s->I2SCTL = u32MasterSlave | u32WordWidth | u32Channels | u32DataFormat; + /* Set TX FIFO threshold to 2 and RX FIFO threshold to 1 */ + SPI_SetFIFO(i2s, 2, 1); + + if (u32MasterSlave == SPI_MASTER) + { + /* Get the source clock rate */ + u32SrcClk = SPII2S_GetSourceClockFreq(i2s); + + /* Calculate the bit clock rate */ + u32BitRate = u32SampleRate * ((u32WordWidth >> SPI_I2SCTL_WDWIDTH_Pos) + 1U) * 16U; + u32Divider = ((u32SrcClk / u32BitRate) >> 1U) - 1U; + //u32Divider = ((((u32SrcClk * 10UL / u32BitRate) >> 1U) + 5UL) / 10UL) - 1U; + /* Set BCLKDIV setting */ + i2s->I2SCLK = (i2s->I2SCLK & ~SPI_I2SCLK_BCLKDIV_Msk) | (u32Divider << SPI_I2SCLK_BCLKDIV_Pos); + + /* Calculate bit clock rate */ + u32BitRate = u32SrcClk / ((u32Divider + 1U) * 2U); + /* Calculate real sample rate */ + u32SampleRate = u32BitRate / (((u32WordWidth >> SPI_I2SCTL_WDWIDTH_Pos) + 1U) * 16U); + + /* Enable TX function, RX function and I2S mode. */ + i2s->I2SCTL |= (SPI_I2SCTL_RXEN_Msk | SPI_I2SCTL_TXEN_Msk | SPI_I2SCTL_I2SEN_Msk); + + /* Return the real sample rate */ + u32RetValue = u32SampleRate; + } + else + { + /* Set BCLKDIV = 0 */ + i2s->I2SCLK &= ~SPI_I2SCLK_BCLKDIV_Msk; + + if (i2s == SPI0) + { + /* Set the peripheral clock rate to equal APB clock rate */ + CLK->CLKSEL4 = (CLK->CLKSEL4 & (~CLK_CLKSEL4_SPI0SEL_Msk)) | CLK_CLKSEL4_SPI0SEL_PCLK1; + /* Enable TX function, RX function and I2S mode. */ + i2s->I2SCTL |= (SPI_I2SCTL_RXEN_Msk | SPI_I2SCTL_TXEN_Msk | SPI_I2SCTL_I2SEN_Msk); + /* Return slave peripheral clock rate */ + u32RetValue = CLK_GetPCLK1Freq(); + } + else if (i2s == SPI1) + { + /* Set the peripheral clock rate to equal APB clock rate */ + CLK->CLKSEL4 = (CLK->CLKSEL4 & (~CLK_CLKSEL4_SPI1SEL_Msk)) | CLK_CLKSEL4_SPI1SEL_PCLK2; + /* Enable TX function, RX function and I2S mode. */ + i2s->I2SCTL |= (SPI_I2SCTL_RXEN_Msk | SPI_I2SCTL_TXEN_Msk | SPI_I2SCTL_I2SEN_Msk); + /* Return slave peripheral clock rate */ + u32RetValue = CLK_GetPCLK2Freq(); + } + else if (i2s == SPI2) + { + /* Set the peripheral clock rate to equal APB clock rate */ + CLK->CLKSEL4 = (CLK->CLKSEL4 & (~CLK_CLKSEL4_SPI2SEL_Msk)) | CLK_CLKSEL4_SPI2SEL_PCLK1; + /* Enable TX function, RX function and I2S mode. */ + i2s->I2SCTL |= (SPI_I2SCTL_RXEN_Msk | SPI_I2SCTL_TXEN_Msk | SPI_I2SCTL_I2SEN_Msk); + /* Return slave peripheral clock rate */ + u32RetValue = CLK_GetPCLK1Freq(); + } + else + { + /* Set the peripheral clock rate to equal APB clock rate */ + CLK->CLKSEL4 = (CLK->CLKSEL4 & (~CLK_CLKSEL4_SPI3SEL_Msk)) | CLK_CLKSEL4_SPI3SEL_PCLK2; + /* Enable TX function, RX function and I2S mode. */ + i2s->I2SCTL |= (SPI_I2SCTL_RXEN_Msk | SPI_I2SCTL_TXEN_Msk | SPI_I2SCTL_I2SEN_Msk); + /* Return slave peripheral clock rate */ + u32RetValue = CLK_GetPCLK2Freq(); + } + } + + return u32RetValue; +} + +/** + * @brief Disable I2S function. + * @param[in] i2s The pointer of the specified I2S module. + * @return None + * @details Disable I2S function. + */ +void SPII2S_Close(SPI_T *i2s) +{ + i2s->I2SCTL &= ~SPI_I2SCTL_I2SEN_Msk; +} + +/** + * @brief Enable interrupt function. + * @param[in] i2s The pointer of the specified I2S module. + * @param[in] u32Mask The combination of all related interrupt enable bits. + * Each bit corresponds to a interrupt source. Valid values are listed below. + * - \ref SPII2S_FIFO_TXTH_INT_MASK + * - \ref SPII2S_FIFO_RXTH_INT_MASK + * - \ref SPII2S_FIFO_RXOV_INT_MASK + * - \ref SPII2S_FIFO_RXTO_INT_MASK + * - \ref SPII2S_TXUF_INT_MASK + * - \ref SPII2S_RIGHT_ZC_INT_MASK + * - \ref SPII2S_LEFT_ZC_INT_MASK + * @return None + * @details This function enables the interrupt according to the u32Mask parameter. + */ +void SPII2S_EnableInt(SPI_T *i2s, uint32_t u32Mask) +{ + /* Enable TX threshold interrupt flag */ + if ((u32Mask & SPII2S_FIFO_TXTH_INT_MASK) == SPII2S_FIFO_TXTH_INT_MASK) + { + i2s->FIFOCTL |= SPI_FIFOCTL_TXTHIEN_Msk; + } + + /* Enable RX threshold interrupt flag */ + if ((u32Mask & SPII2S_FIFO_RXTH_INT_MASK) == SPII2S_FIFO_RXTH_INT_MASK) + { + i2s->FIFOCTL |= SPI_FIFOCTL_RXTHIEN_Msk; + } + + /* Enable RX overrun interrupt flag */ + if ((u32Mask & SPII2S_FIFO_RXOV_INT_MASK) == SPII2S_FIFO_RXOV_INT_MASK) + { + i2s->FIFOCTL |= SPI_FIFOCTL_RXOVIEN_Msk; + } + + /* Enable RX time-out interrupt flag */ + if ((u32Mask & SPII2S_FIFO_RXTO_INT_MASK) == SPII2S_FIFO_RXTO_INT_MASK) + { + i2s->FIFOCTL |= SPI_FIFOCTL_RXTOIEN_Msk; + } + + /* Enable TX underflow interrupt flag */ + if ((u32Mask & SPII2S_TXUF_INT_MASK) == SPII2S_TXUF_INT_MASK) + { + i2s->FIFOCTL |= SPI_FIFOCTL_TXUFIEN_Msk; + } + + /* Enable right channel zero cross interrupt flag */ + if ((u32Mask & SPII2S_RIGHT_ZC_INT_MASK) == SPII2S_RIGHT_ZC_INT_MASK) + { + i2s->I2SCTL |= SPI_I2SCTL_RZCIEN_Msk; + } + + /* Enable left channel zero cross interrupt flag */ + if ((u32Mask & SPII2S_LEFT_ZC_INT_MASK) == SPII2S_LEFT_ZC_INT_MASK) + { + i2s->I2SCTL |= SPI_I2SCTL_LZCIEN_Msk; + } +} + +/** + * @brief Disable interrupt function. + * @param[in] i2s The pointer of the specified I2S module. + * @param[in] u32Mask The combination of all related interrupt enable bits. + * Each bit corresponds to a interrupt source. Valid values are listed below. + * - \ref SPII2S_FIFO_TXTH_INT_MASK + * - \ref SPII2S_FIFO_RXTH_INT_MASK + * - \ref SPII2S_FIFO_RXOV_INT_MASK + * - \ref SPII2S_FIFO_RXTO_INT_MASK + * - \ref SPII2S_TXUF_INT_MASK + * - \ref SPII2S_RIGHT_ZC_INT_MASK + * - \ref SPII2S_LEFT_ZC_INT_MASK + * @return None + * @details This function disables the interrupt according to the u32Mask parameter. + */ +void SPII2S_DisableInt(SPI_T *i2s, uint32_t u32Mask) +{ + /* Disable TX threshold interrupt flag */ + if ((u32Mask & SPII2S_FIFO_TXTH_INT_MASK) == SPII2S_FIFO_TXTH_INT_MASK) + { + i2s->FIFOCTL &= ~SPI_FIFOCTL_TXTHIEN_Msk; + } + + /* Disable RX threshold interrupt flag */ + if ((u32Mask & SPII2S_FIFO_RXTH_INT_MASK) == SPII2S_FIFO_RXTH_INT_MASK) + { + i2s->FIFOCTL &= ~SPI_FIFOCTL_RXTHIEN_Msk; + } + + /* Disable RX overrun interrupt flag */ + if ((u32Mask & SPII2S_FIFO_RXOV_INT_MASK) == SPII2S_FIFO_RXOV_INT_MASK) + { + i2s->FIFOCTL &= ~SPI_FIFOCTL_RXOVIEN_Msk; + } + + /* Disable RX time-out interrupt flag */ + if ((u32Mask & SPII2S_FIFO_RXTO_INT_MASK) == SPII2S_FIFO_RXTO_INT_MASK) + { + i2s->FIFOCTL &= ~SPI_FIFOCTL_RXTOIEN_Msk; + } + + /* Disable TX underflow interrupt flag */ + if ((u32Mask & SPII2S_TXUF_INT_MASK) == SPII2S_TXUF_INT_MASK) + { + i2s->FIFOCTL &= ~SPI_FIFOCTL_TXUFIEN_Msk; + } + + /* Disable right channel zero cross interrupt flag */ + if ((u32Mask & SPII2S_RIGHT_ZC_INT_MASK) == SPII2S_RIGHT_ZC_INT_MASK) + { + i2s->I2SCTL &= ~SPI_I2SCTL_RZCIEN_Msk; + } + + /* Disable left channel zero cross interrupt flag */ + if ((u32Mask & SPII2S_LEFT_ZC_INT_MASK) == SPII2S_LEFT_ZC_INT_MASK) + { + i2s->I2SCTL &= ~SPI_I2SCTL_LZCIEN_Msk; + } +} + +/** + * @brief Enable master clock (MCLK). + * @param[in] i2s The pointer of the specified I2S module. + * @param[in] u32BusClock The target MCLK clock rate. + * @return Actual MCLK clock rate + * @details Set the master clock rate according to u32BusClock parameter and enable master clock output. + * The actual master clock rate may be different from the target master clock rate. The real master clock rate will be returned for reference. + */ +uint32_t SPII2S_EnableMCLK(SPI_T *i2s, uint32_t u32BusClock) +{ + uint32_t u32Divider; + uint32_t u32SrcClk, u32RetValue; + + u32SrcClk = SPII2S_GetSourceClockFreq(i2s); + if (u32BusClock == u32SrcClk) + { + u32Divider = 0U; + } + else + { + u32Divider = (u32SrcClk / u32BusClock) >> 1U; + /* MCLKDIV is a 6-bit width configuration. The maximum value is 0x3F. */ + if (u32Divider > 0x3FU) + { + u32Divider = 0x3FU; + } + } + + /* Write u32Divider to MCLKDIV (SPI_I2SCLK[5:0]) */ + i2s->I2SCLK = (i2s->I2SCLK & ~SPI_I2SCLK_MCLKDIV_Msk) | (u32Divider << SPI_I2SCLK_MCLKDIV_Pos); + + /* Enable MCLK output */ + i2s->I2SCTL |= SPI_I2SCTL_MCLKEN_Msk; + + if (u32Divider == 0U) + { + u32RetValue = u32SrcClk; /* If MCLKDIV=0, master clock rate is equal to the source clock rate. */ + } + else + { + u32RetValue = ((u32SrcClk >> 1U) / u32Divider); /* If MCLKDIV>0, master clock rate = source clock rate / (MCLKDIV * 2) */ + } + + return u32RetValue; +} + +/** + * @brief Disable master clock (MCLK). + * @param[in] i2s The pointer of the specified I2S module. + * @return None + * @details Clear MCLKEN bit of SPI_I2SCTL register to disable master clock output. + */ +void SPII2S_DisableMCLK(SPI_T *i2s) +{ + i2s->I2SCTL &= ~SPI_I2SCTL_MCLKEN_Msk; +} + +/** + * @brief Configure FIFO threshold setting. + * @param[in] i2s The pointer of the specified I2S module. + * @param[in] u32TxThreshold Decides the TX FIFO threshold. It could be 0 ~ 3. + * @param[in] u32RxThreshold Decides the RX FIFO threshold. It could be 0 ~ 3. + * @return None + * @details Set TX FIFO threshold and RX FIFO threshold configurations. + */ +void SPII2S_SetFIFO(SPI_T *i2s, uint32_t u32TxThreshold, uint32_t u32RxThreshold) +{ + i2s->FIFOCTL = (i2s->FIFOCTL & ~(SPI_FIFOCTL_TXTH_Msk | SPI_FIFOCTL_RXTH_Msk)) | + (u32TxThreshold << SPI_FIFOCTL_TXTH_Pos) | + (u32RxThreshold << SPI_FIFOCTL_RXTH_Pos); +} + +/*@}*/ /* end of group SPI_EXPORTED_FUNCTIONS */ + +/*@}*/ /* end of group SPI_Driver */ + +/*@}*/ /* end of group Standard_Driver */ + diff --git a/bsp/nuvoton/libraries/ma35/StdDriver/src/nu_ssmcc.c b/bsp/nuvoton/libraries/ma35/StdDriver/src/nu_ssmcc.c new file mode 100644 index 0000000000..cb9e0e8cad --- /dev/null +++ b/bsp/nuvoton/libraries/ma35/StdDriver/src/nu_ssmcc.c @@ -0,0 +1,133 @@ +/**************************************************************************//** + * @file ssmcc.c + * @brief SSMCC driver source file + * + * SPDX-License-Identifier: Apache-2.0 + * @copyright (C) 2020 Nuvoton Technology Corp. All rights reserved. +*****************************************************************************/ +#include "NuMicro.h" + + +/** @addtogroup Standard_Driver Standard Driver + @{ +*/ + +/** @addtogroup SSMCC_Driver SSMCC Driver + @{ +*/ + +/** @addtogroup SSMCC_EXPORTED_FUNCTIONS SSMCC Exported Functions + @{ +*/ + +/** + * @brief Set TZC Region0. + * @param[in] u32Attr is security attribute for all region 0. + * @return none + * @details + * SSMCC::TZC0:Ch0 CA35, AXI-AP + * SSMCC::TZC0:Ch1 GFX, VC8000 + * SSMCC::TZC0:Ch2 DCUltra + * SSMCC::TZC0:Ch3 GMAC0, GMAC1 + * SSMCC::TZC2:Ch0 CCAP0, CCAP1 + * SSMCC::TZC2:Ch1 CM4 + * PDMA0, PDMA1, PDMA2, PDMA3 + * SDH0, SDH1 + * HSUSBH0, HSUSBH1, USBH0, USBH1, USBH2 + * HSUSBD, NFI + * SSMCC::TZC2:Ch2 CRYPTO + * \hideinitializer + */ +#define TZC0_CH_NUM 4 +#define TZC2_CH_NUM 3 + +void SSMCC_SetRegion0(uint32_t u32Attr) +{ + /* Enable SSMCC clock */ + CLK->APBCLK2 |= CLK_APBCLK2_SSMCCEN_Msk; + + /* Enable IP clocks on channels. */ + CLK->CLKSEL0 |= CLK_CLKSEL0_SYSCK0SEL_SYSPLL; + + CLK->SYSCLK0 |= (CLK_SYSCLK0_CCAP1EN_Msk | + CLK_SYSCLK0_CCAP0EN_Msk | + CLK_SYSCLK0_GMAC1EN_Msk | + CLK_SYSCLK0_GMAC0EN_Msk | + CLK_SYSCLK0_DCUEN_Msk | + CLK_SYSCLK0_VDECEN_Msk | + CLK_SYSCLK0_GFXEN_Msk | + CLK_SYSCLK0_HUSBH1EN_Msk | + CLK_SYSCLK0_HUSBH0EN_Msk | + CLK_SYSCLK0_USBHEN_Msk | + CLK_SYSCLK0_USBDEN_Msk | + CLK_SYSCLK0_NANDEN_Msk | + CLK_SYSCLK0_SDH1EN_Msk | + CLK_SYSCLK0_SDH0EN_Msk); + + /* Set region 0 secure attribute */ + TZC0->REGION[SSMCC_REGION_0].ATTRIBUTES = u32Attr & (TZC_REGION_ATTRIBUTES_s_rd_en_Msk | TZC_REGION_ATTRIBUTES_s_wr_en_Msk); + TZC0->GATE_KEEPER = (1 << TZC0_CH_NUM) - 1; /* CH[0, 1, 2, 3] used, filter mask is 0xF */ + TZC2->REGION[SSMCC_REGION_0].ATTRIBUTES = u32Attr & (TZC_REGION_ATTRIBUTES_s_rd_en_Msk | TZC_REGION_ATTRIBUTES_s_wr_en_Msk); + TZC2->GATE_KEEPER = (1 << TZC2_CH_NUM) - 1; /* CH[0, 1, 2] used, filter mask is 0x7 */ + + while (1) + { + if (((TZC0->GATE_KEEPER & TZC_GATE_KEEPER_open_status_Msk) == (((1 << TZC0_CH_NUM) - 1) << TZC_GATE_KEEPER_open_status_Pos)) + && ((TZC2->GATE_KEEPER & TZC_GATE_KEEPER_open_status_Msk) == (((1 << TZC2_CH_NUM) - 1) << TZC_GATE_KEEPER_open_status_Pos))) + { + break; + } + } + + /* set region 0 non-secure attribute */ + TZC0->REGION[SSMCC_REGION_0].ID_ACCESS = u32Attr & 0x00010001; + TZC2->REGION[SSMCC_REGION_0].ID_ACCESS = u32Attr & 0x00030003; + + CLK->SYSCLK0 &= ~(CLK_SYSCLK0_CCAP1EN_Msk | + CLK_SYSCLK0_CCAP0EN_Msk | + CLK_SYSCLK0_GMAC1EN_Msk | + CLK_SYSCLK0_GMAC0EN_Msk | + CLK_SYSCLK0_DCUEN_Msk | + CLK_SYSCLK0_VDECEN_Msk | + CLK_SYSCLK0_GFXEN_Msk | + CLK_SYSCLK0_HUSBH1EN_Msk | + CLK_SYSCLK0_HUSBH0EN_Msk | + CLK_SYSCLK0_USBHEN_Msk | + CLK_SYSCLK0_USBDEN_Msk | + CLK_SYSCLK0_NANDEN_Msk | + CLK_SYSCLK0_SDH1EN_Msk | + CLK_SYSCLK0_SDH0EN_Msk); + + //CLK->CLKSEL0 &= ~CLK_CLKSEL0_SYSCK0SEL_Msk; +} + +/** + * @brief Set TZC Regions. + * @param[in] psParam is structure pointer of SSMCC parameter. + * @return none + * @details + * \hideinitializer + */ +void SSMCC_SetRegion(SSMCC_PARAM_T *psParam) +{ + if (psParam && + psParam->region_no != SSMCC_REGION_0) + { + TZC0->REGION[psParam->region_no].BASE_LOW = psParam->base_address; + TZC0->REGION[psParam->region_no].TOP_LOW = psParam->base_address + psParam->size - 1; + TZC0->REGION[psParam->region_no].ATTRIBUTES = ((1 << TZC0_CH_NUM) - 1) | (psParam->attribute & (TZC_REGION_ATTRIBUTES_s_rd_en_Msk | TZC_REGION_ATTRIBUTES_s_wr_en_Msk)); + TZC0->REGION[psParam->region_no].ID_ACCESS = psParam->attribute & 0x00010001; + + TZC2->REGION[psParam->region_no].BASE_LOW = psParam->base_address; + TZC2->REGION[psParam->region_no].TOP_LOW = psParam->base_address + psParam->size - 1; + TZC2->REGION[psParam->region_no].ATTRIBUTES = ((1 << TZC2_CH_NUM) - 1) | (psParam->attribute & (TZC_REGION_ATTRIBUTES_s_rd_en_Msk | TZC_REGION_ATTRIBUTES_s_wr_en_Msk)); + TZC2->REGION[psParam->region_no].ID_ACCESS = psParam->attribute & 0x00030003; + } +} + +/*@}*/ /* end of group SSMCC_EXPORTED_FUNCTIONS */ + +/*@}*/ /* end of group SSMCC_Driver */ + +/*@}*/ /* end of group Standard_Driver */ + diff --git a/bsp/nuvoton/libraries/ma35/StdDriver/src/nu_sspcc.c b/bsp/nuvoton/libraries/ma35/StdDriver/src/nu_sspcc.c new file mode 100644 index 0000000000..d72def46d5 --- /dev/null +++ b/bsp/nuvoton/libraries/ma35/StdDriver/src/nu_sspcc.c @@ -0,0 +1,106 @@ +/**************************************************************************//** + * @file sspcc.c + * @brief SSPCC driver source file + * + * SPDX-License-Identifier: Apache-2.0 + * @copyright (C) 2020 Nuvoton Technology Corp. All rights reserved. + *****************************************************************************/ + +#include "NuMicro.h" + +/** @addtogroup Standard_Driver Standard Driver + @{ +*/ + +/** @addtogroup SSPCC_Driver SSPCC Driver + @{ +*/ + +/** @addtogroup SSPCC_EXPORTED_FUNCTIONS SSPCC Exported Functions + @{ +*/ + +/** + * @brief Set Peripheral Realm + * + * @param[in] u32Perip SSPCC Peripheral ID. + * @param[in] u32Realm Security set(Realm). It could be \n + * SSPCC_SSET_TZS, SSPCC_SSET_TZNS, SSPCC_SSET_SUBM. + * + * @return None + * + * @details This function is used to set specified realm. + */ +void SSPCC_SetRealm(uint32_t u32Perip, uint32_t u32Realm) +{ + vu32 *pu32SSet = (vu32 *)(SSPCC_BASE + (u32Perip >> SSPCC_REG_Pos)); + uint32_t u32Pos = u32Perip & SSPCC_PS_Msk; + + *pu32SSet = (*pu32SSet & ~(SSPCC_SSET_Msk << u32Pos)) | (u32Realm << u32Pos); +} + +/** + * @brief Get Peripheral Realm + * + * @param[in] u32Perip SSPCC Peripheral ID. + * @param[out] u32Realm Security set(Realm). It could be \n + * SSPCC_SSET_TZS, SSPCC_SSET_TZNS, SSPCC_SSET_SUBM. + * + * @return None + * + * @details This function is used to get specified realm. + */ +uint32_t SSPCC_GetRealm(uint32_t u32Perip) +{ + vu32 *pu32SSet = (vu32 *)(SSPCC_BASE + (u32Perip >> SSPCC_REG_Pos)); + uint32_t u32Pos = u32Perip & SSPCC_PS_Msk; + + return (*pu32SSet & (SSPCC_SSET_Msk << u32Pos)) >> u32Pos; +} + +/** + * @brief Set Pin Realm + * + * @param[in] u32PortBA GPIO port. It could be GPIOA_BASE, GPIOB_BASE, ..., GPIOM_BASE and GPION_BASE. + * @param[in] u32Pin It could be 0 ~ 15 for PA, PB, ..., PM and PN GPIO ports. + * @param[in] u32Realm realm. It could be \n + * SSPCC_SSET_TZS, SSPCC_SSET_TZNS, SSPCC_SSET_SUBM. + * + * @return None + * + * @details This function is used to set specified IO realm. + */ +void SSPCC_SetRealm_GPIO(uint32_t u32PortBA, uint32_t u32Pin, uint32_t u32Realm) +{ + uint32_t u32PortIdx = (u32PortBA - GPIO_BASE) / 0x40; + vu32 *avu32IOSecuritySet = (vu32 *)&SSPCC->IOASSET; + + avu32IOSecuritySet[u32PortIdx] = (avu32IOSecuritySet[u32PortIdx] & ~(SSPCC_SSET_Msk << (u32Pin << 1))) | (u32Realm << (u32Pin << 1)); +} + +/** + * @brief Get Pin Realm + * + * @param[in] u32PortBA GPIO port. It could be GPIOA_BASE, GPIOB_BASE, ..., GPIOM_BASE and GPION_BASE. + * @param[in] u32Pin It could be 0 ~ 15 for PA, PB, ..., PM and PN GPIO ports. + * + * @return It could be \n + * SSPCC_SSET_TZS, SSPCC_SSET_TZNS, SSPCC_SSET_SUBM. + * + * @details This function is used to set specified IO realm. + */ +uint32_t SSPCC_GetRealm_GPIO(uint32_t u32PortBA, uint32_t u32Pin) +{ + uint32_t u32PortIdx = (u32PortBA - GPIO_BASE) / 0x40; + vu32 *avu32IOSecuritySet = (vu32 *)&SSPCC->IOASSET; + uint32_t u32Ret = avu32IOSecuritySet[u32PortIdx] & (SSPCC_SSET_Msk << (u32Pin << 1)); + + return u32Ret >> (u32Pin << 1); +} + +/*@}*/ /* end of group SSPCC_EXPORTED_FUNCTIONS */ + +/*@}*/ /* end of group SSPCC_Driver */ + +/*@}*/ /* end of group Standard_Driver */ + diff --git a/bsp/nuvoton/libraries/ma35/StdDriver/src/nu_sys.c b/bsp/nuvoton/libraries/ma35/StdDriver/src/nu_sys.c new file mode 100644 index 0000000000..98a23a2757 --- /dev/null +++ b/bsp/nuvoton/libraries/ma35/StdDriver/src/nu_sys.c @@ -0,0 +1,149 @@ +/**************************************************************************//** + * @file sys.c + * @brief SYS driver source file + * + * SPDX-License-Identifier: Apache-2.0 + * @copyright (C) 2020 Nuvoton Technology Corp. All rights reserved. + *****************************************************************************/ + +#include "NuMicro.h" + +#ifdef __cplusplus +extern "C" +{ +#endif + +/** @addtogroup Standard_Driver Standard Driver + @{ +*/ + +/** @addtogroup SYS_Driver SYS Driver + @{ +*/ + + +/** @addtogroup SYS_EXPORTED_FUNCTIONS SYS Exported Functions + @{ +*/ + +/** + * @brief Reset selected module + * @param[in] u32ModuleIndex is module index. Including : + * - \ref PDMA0_RST + * - \ref PDMA1_RST + * - \ref PDMA2_RST + * - \ref PDMA3_RST + * - \ref DISPC_RST + * - \ref VCAP0_RST + * - \ref VCAP1_RST + * - \ref GFX_RST + * - \ref VDEC_RST + * - \ref WRHO0_RST + * - \ref WRHO1_RST + * - \ref GMAC0_RST + * - \ref GMAC1_RST + * - \ref HWSEM_RST + * - \ref EBI_RST + * - \ref HSUSBH0_RST + * - \ref HSUSBH1_RST + * - \ref HSUSBD_RST + * - \ref USBHL_RST + * - \ref SDH0_RST + * - \ref SDH1_RST + * - \ref NAND_RST + * - \ref GPIO_RST + * - \ref MCTLP_RST + * - \ref MCTLC_RST + * - \ref DDRPUB_RST + * - \ref TMR0_RST + * - \ref TMR1_RST + * - \ref TMR2_RST + * - \ref TMR3_RST + * - \ref I2C0_RST + * - \ref I2C1_RST + * - \ref I2C2_RST + * - \ref I2C3_RST + * - \ref QSPI0_RST + * - \ref SPI0_RST + * - \ref SPI1_RST + * - \ref SPI2_RST + * - \ref UART0_RST + * - \ref UART1_RST + * - \ref UART2_RST + * - \ref UART3_RST + * - \ref UART4_RST + * - \ref UART5_RST + * - \ref UART6_RST + * - \ref UART7_RST + * - \ref MCAN0_RST + * - \ref MCAN1_RST + * - \ref EADC0_RST + * - \ref I2S0_RST + * - \ref SC0_RST + * - \ref SC1_RST + * - \ref QSPI1_RST + * - \ref SPI3_RST + * - \ref EPWM0_RST + * - \ref EPWM1_RST + * - \ref QEI0_RST + * - \ref QEI1_RST + * - \ref ECAP0_RST + * - \ref ECAP1_RST + * - \ref MCAN2_RST + * - \ref ADC0_RST + * - \ref TMR4_RST + * - \ref TMR5_RST + * - \ref TMR6_RST + * - \ref TMR7_RST + * - \ref TMR8_RST + * - \ref TMR9_RST + * - \ref TMR10_RST + * - \ref TMR11_RST + * - \ref UART8_RST + * - \ref UART9_RST + * - \ref UART10_RST + * - \ref UART11_RST + * - \ref UART12_RST + * - \ref UART13_RST + * - \ref UART14_RST + * - \ref UART15_RST + * - \ref UART16_RST + * - \ref I2S1_RST + * - \ref I2C4_RST + * - \ref I2C5_RST + * - \ref EPWM2_RST + * - \ref ECAP2_RST + * - \ref QEI2_RST + * - \ref MCAN3_RST + * - \ref KPI_RST + * - \ref GIC_RST + * - \ref SSMCC_RST + * - \ref SSPCC_RST + * @return None + * @details This function reset selected module. + */ +void SYS_ResetModule(uint32_t u32ModuleIndex) +{ + uint32_t u32tmpVal = 0UL, u32tmpAddr = 0UL; + + /* Generate reset signal to the corresponding module */ + u32tmpVal = (1UL << (u32ModuleIndex & 0x00ffffffUL)); + u32tmpAddr = (vu32)&SYS->IPRST0 + ((u32ModuleIndex >> 24UL)); + *(vu32 *)u32tmpAddr |= u32tmpVal; + + /* Release corresponding module from reset state */ + u32tmpVal = ~(1UL << (u32ModuleIndex & 0x00ffffffUL)); + *(vu32 *)u32tmpAddr &= u32tmpVal; +} + + +/*@}*/ /* end of group SYS_EXPORTED_FUNCTIONS */ + +/*@}*/ /* end of group SYS_Driver */ + +/*@}*/ /* end of group Standard_Driver */ + +#ifdef __cplusplus +} +#endif + diff --git a/bsp/nuvoton/libraries/ma35/StdDriver/src/nu_timer.c b/bsp/nuvoton/libraries/ma35/StdDriver/src/nu_timer.c new file mode 100644 index 0000000000..d933ec6587 --- /dev/null +++ b/bsp/nuvoton/libraries/ma35/StdDriver/src/nu_timer.c @@ -0,0 +1,396 @@ +/**************************************************************************//** + * @file timer.c + * @brief Timer Controller(Timer) driver source file + * + * SPDX-License-Identifier: Apache-2.0 + * @copyright (C) 2020 Nuvoton Technology Corp. All rights reserved. +*****************************************************************************/ +#include "NuMicro.h" + + +/** @addtogroup Standard_Driver Standard Driver + @{ +*/ + +/** @addtogroup TIMER_Driver TIMER Driver + @{ +*/ + +/** @addtogroup TIMER_EXPORTED_FUNCTIONS TIMER Exported Functions + @{ +*/ + +/** + * @brief Open Timer with Operate Mode and Frequency + * + * @param[in] timer The pointer of the specified Timer module. It could be TIMER2 ~ TIMER11. + * @param[in] u32Mode Operation mode. Possible options are + * - \ref TIMER_ONESHOT_MODE + * - \ref TIMER_PERIODIC_MODE + * - \ref TIMER_TOGGLE_MODE + * - \ref TIMER_CONTINUOUS_MODE + * @param[in] u32Freq Target working frequency + * + * @return Real timer working frequency + * + * @details This API is used to configure timer to operate in specified mode and frequency. + * If timer cannot work in target frequency, a closest frequency will be chose and returned. + * @note After calling this API, Timer is \b NOT running yet. But could start timer running be calling + * \ref TIMER_Start macro or program registers directly. + */ +uint32_t TIMER_Open(TIMER_T *timer, uint32_t u32Mode, uint32_t u32Freq) +{ + uint32_t u32Clk = TIMER_GetModuleClock(timer); + uint32_t u32Cmpr = 0UL, u32Prescale = 0UL; + + /* Fastest possible timer working freq is (u32Clk / 2). While cmpr = 2, prescaler = 0. */ + if (u32Freq > (u32Clk / 2UL)) + { + u32Cmpr = 2UL; + } + else + { + u32Cmpr = u32Clk / u32Freq; + u32Prescale = (u32Cmpr >> 24); /* for 24 bits CMPDAT */ + + if (u32Prescale > 0UL) + u32Cmpr = u32Cmpr / (u32Prescale + 1UL); + } + + timer->CTL = u32Mode | u32Prescale; + timer->CMP = u32Cmpr; + + return (u32Clk / (u32Cmpr * (u32Prescale + 1UL))); +} + +/** + * @brief Stop Timer Counting + * + * @param[in] timer The pointer of the specified Timer module. It could be TIMER2 ~ TIMER11. + * + * @return None + * + * @details This API stops timer counting and disable all timer interrupt function. + */ +void TIMER_Close(TIMER_T *timer) +{ + timer->CTL = 0UL; + timer->EXTCTL = 0UL; +} + +/** + * @brief Create a specify Delay Time + * + * @param[in] timer The pointer of the specified Timer module. It could be TIMER2 ~ TIMER11. + * @param[in] u32Usec Delay period in micro seconds. Valid values are between 100~1000000 (100 micro second ~ 1 second). + * + * @return None + * + * @details This API is used to create a delay loop for u32usec micro seconds by using timer one-shot mode. + * @note This API overwrites the register setting of the timer used to count the delay time. + * @note This API use polling mode. So there is no need to enable interrupt for the timer module used to generate delay. + */ +void TIMER_Delay(TIMER_T *timer, uint32_t u32Usec) +{ +#if 0 + uint32_t u32Clk = TIMER_GetModuleClock(timer); + uint32_t u32Prescale = 0UL, delay = (SystemCoreClock / u32Clk) + 1UL; + uint32_t u32Cmpr, u32NsecPerTick; + + /* Clear current timer configuration */ + timer->CTL = 0UL; + timer->EXTCTL = 0UL; + + if (u32Clk <= 1000000UL) /* min delay is 1000 us if timer clock source is <= 1 MHz */ + { + if (u32Usec < 1000UL) + { + u32Usec = 1000UL; + } + + if (u32Usec > 1000000UL) + { + u32Usec = 1000000UL; + } + } + else + { + if (u32Usec < 100UL) + { + u32Usec = 100UL; + } + + if (u32Usec > 1000000UL) + { + u32Usec = 1000000UL; + } + } + + if (u32Clk <= 1000000UL) + { + u32Prescale = 0UL; + u32NsecPerTick = 1000000000UL / u32Clk; + u32Cmpr = (u32Usec * 1000UL) / u32NsecPerTick; + } + else + { + u32Cmpr = u32Usec * (u32Clk / 1000000UL); + u32Prescale = (u32Cmpr >> 24); /* for 24 bits CMPDAT */ + + if (u32Prescale > 0UL) + u32Cmpr = u32Cmpr / (u32Prescale + 1UL); + } + + timer->CMP = u32Cmpr; + timer->CTL = TIMER_CTL_CNTEN_Msk | TIMER_ONESHOT_MODE | u32Prescale; + + /* When system clock is faster than timer clock, it is possible timer active bit cannot set in time while we check it. + And the while loop below return immediately, so put a tiny delay here allowing timer start counting and raise active flag. */ + for (; delay > 0UL; delay--) + { + __NOP(); + } + + while (timer->CTL & TIMER_CTL_ACTSTS_Msk) + { + ; + } +#endif +} + +/** + * @brief Enable Timer Capture Function + * + * @param[in] timer The pointer of the specified Timer module. It could be TIMER2 ~ TIMER11. + * @param[in] u32CapMode Timer capture mode. Could be + * - \ref TIMER_CAPTURE_FREE_COUNTING_MODE + * - \ref TIMER_CAPTURE_COUNTER_RESET_MODE + * @param[in] u32Edge Timer capture trigger edge. Possible values are + * - \ref TIMER_CAPTURE_EVENT_FALLING + * - \ref TIMER_CAPTURE_EVENT_RISING + * - \ref TIMER_CAPTURE_EVENT_FALLING_RISING + * - \ref TIMER_CAPTURE_EVENT_RISING_FALLING + * + * @return None + * + * @details This API is used to enable timer capture function with specify capture trigger edge \n + * to get current counter value or reset counter value to 0. + * @note Timer frequency should be configured separately by using \ref TIMER_Open API, or program registers directly. + */ +void TIMER_EnableCapture(TIMER_T *timer, uint32_t u32CapMode, uint32_t u32Edge) +{ + timer->EXTCTL = (timer->EXTCTL & ~(TIMER_EXTCTL_CAPFUNCS_Msk | TIMER_EXTCTL_CAPEDGE_Msk)) | + u32CapMode | u32Edge | TIMER_EXTCTL_CAPEN_Msk; +} + +/** + * @brief Disable Timer Capture Function + * + * @param[in] timer The pointer of the specified Timer module. It could be TIMER0, TIMER1, TIMER2, TIMER3. + * + * @return None + * + * @details This API is used to disable the timer capture function. + */ +void TIMER_DisableCapture(TIMER_T *timer) +{ + timer->EXTCTL &= ~TIMER_EXTCTL_CAPEN_Msk; +} + +/** + * @brief Enable Timer Counter Function + * + * @param[in] timer The pointer of the specified Timer module. It could be TIMER2 ~ TIMER11. + * @param[in] u32Edge Detection edge of counter pin. Could be ether + * - \ref TIMER_COUNTER_EVENT_FALLING, or + * - \ref TIMER_COUNTER_EVENT_RISING + * + * @return None + * + * @details This function is used to enable the timer counter function with specify detection edge. + * @note Timer compare value should be configured separately by using \ref TIMER_SET_CMP_VALUE macro or program registers directly. + * @note While using event counter function, \ref TIMER_TOGGLE_MODE cannot set as timer operation mode. + */ +void TIMER_EnableEventCounter(TIMER_T *timer, uint32_t u32Edge) +{ + timer->EXTCTL = (timer->EXTCTL & ~TIMER_EXTCTL_CNTPHASE_Msk) | u32Edge; + timer->CTL |= TIMER_CTL_EXTCNTEN_Msk; +} + +/** + * @brief Disable Timer Counter Function + * + * @param[in] timer The pointer of the specified Timer module. It could be TIMER2 ~ TIMER11. + * + * @return None + * + * @details This API is used to disable the timer event counter function. + */ +void TIMER_DisableEventCounter(TIMER_T *timer) +{ + timer->CTL &= ~TIMER_CTL_EXTCNTEN_Msk; +} + +/** + * @brief Get Timer Clock Frequency + * + * @param[in] timer The pointer of the specified Timer module. It could be TIMER2 ~ TIMER11. + * + * @return Timer clock frequency + * + * @details This API is used to get the timer clock frequency. + * @note This API cannot return correct clock rate if timer source is from external clock input. + */ +uint32_t TIMER_GetModuleClock(TIMER_T *timer) +{ + uint32_t u32Src, u32Clk; + const uint32_t au32Clk[] = {__HXT, __LXT, 0UL, 0UL, 0UL, __LIRC, 0UL, __HIRC}; + + if (timer == TIMER0) + { + u32Src = (CLK->CLKSEL1 & CLK_CLKSEL1_TMR0SEL_Msk) >> CLK_CLKSEL1_TMR0SEL_Pos; + } + else if (timer == TIMER1) + { + u32Src = (CLK->CLKSEL1 & CLK_CLKSEL1_TMR1SEL_Msk) >> CLK_CLKSEL1_TMR1SEL_Pos; + } + else if (timer == TIMER2) + { + u32Src = (CLK->CLKSEL1 & CLK_CLKSEL1_TMR2SEL_Msk) >> CLK_CLKSEL1_TMR2SEL_Pos; + } + else if (timer == TIMER3) + { + u32Src = (CLK->CLKSEL1 & CLK_CLKSEL1_TMR3SEL_Msk) >> CLK_CLKSEL1_TMR3SEL_Pos; + } + else if (timer == TIMER4) + { + u32Src = (CLK->CLKSEL1 & CLK_CLKSEL1_TMR4SEL_Msk) >> CLK_CLKSEL1_TMR4SEL_Pos; + } + else if (timer == TIMER5) + { + u32Src = (CLK->CLKSEL1 & CLK_CLKSEL1_TMR5SEL_Msk) >> CLK_CLKSEL1_TMR5SEL_Pos; + } + else if (timer == TIMER6) + { + u32Src = (CLK->CLKSEL1 & CLK_CLKSEL1_TMR6SEL_Msk) >> CLK_CLKSEL1_TMR6SEL_Pos; + } + else if (timer == TIMER7) + { + u32Src = (CLK->CLKSEL1 & CLK_CLKSEL1_TMR7SEL_Msk) >> CLK_CLKSEL1_TMR7SEL_Pos; + } + else if (timer == TIMER8) + { + u32Src = (CLK->CLKSEL2 & CLK_CLKSEL2_TMR8SEL_Msk) >> CLK_CLKSEL2_TMR8SEL_Pos; + } + else if (timer == TIMER9) + { + u32Src = (CLK->CLKSEL2 & CLK_CLKSEL2_TMR9SEL_Msk) >> CLK_CLKSEL2_TMR9SEL_Pos; + } + else if (timer == TIMER10) + { + u32Src = (CLK->CLKSEL2 & CLK_CLKSEL2_TMR10SEL_Msk) >> CLK_CLKSEL2_TMR10SEL_Pos; + } + else /* Timer 11 */ + { + u32Src = (CLK->CLKSEL2 & CLK_CLKSEL2_TMR11SEL_Msk) >> CLK_CLKSEL2_TMR11SEL_Pos; + } + + if (u32Src == 2UL) + { + u32Clk = CLK_GetSYSCLK1Freq(); + } + else + { + u32Clk = au32Clk[u32Src]; + } + + return u32Clk; +} + + + +/** + * @brief This function is used to enable the Timer frequency counter function + * @param[in] timer The base address of Timer module. Can be \ref TIMER2 or \ref TIMER4 + * @param[in] u32DropCount This parameter has no effect + * @param[in] u32Timeout This parameter has no effect + * @param[in] u32EnableInt Enable interrupt assertion after capture complete or not. Valid values are TRUE and FALSE + * @return None + * @details This function is used to calculate input event frequency. After enable + * this function, a pair of timers, TIMER2 and TIMER3, or TIMER4 and TIMER5 + * will be configured for this function. The mode used to calculate input + * event frequency is mentioned as "Inter Timer Trigger Mode" in Technical + * Reference Manual + */ +void TIMER_EnableFreqCounter(TIMER_T *timer, + uint32_t u32DropCount, + uint32_t u32Timeout, + uint32_t u32EnableInt) +{ + TIMER_T *t = NULL; /* store the timer base to configure compare value */ + + if (timer == TIMER0) + t = TIMER1; + else if (timer == TIMER2) + t = TIMER3; + else if (timer == TIMER4) + t = TIMER5; + else if (timer == TIMER6) + t = TIMER7; + else if (timer == TIMER8) + t = TIMER9; + else if (timer == TIMER10) + t = TIMER11; + else // Select error + return; + + t->CMP = 0xFFFFFFUL; + t->EXTCTL = u32EnableInt ? TIMER_EXTCTL_CAPIEN_Msk : 0UL; + timer->CTL = TIMER_CTL_INTRGEN_Msk | TIMER_CTL_CNTEN_Msk; + + return; +} +/** + * @brief This function is used to disable the Timer frequency counter function. + * @param[in] timer The base address of Timer module + * @return None + */ +void TIMER_DisableFreqCounter(TIMER_T *timer) +{ + timer->CTL &= ~TIMER_CTL_INTRGEN_Msk; +} + + +/** + * @brief This function is used to select the interrupt source used to trigger other modules. + * @param[in] timer The base address of Timer module + * @param[in] u32Src Selects the interrupt source to trigger other modules. Could be: + * - \ref TIMER_TRGSRC_TIMEOUT_EVENT + * - \ref TIMER_TRGSRC_CAPTURE_EVENT + * @return None + */ +void TIMER_SetTriggerSource(TIMER_T *timer, uint32_t u32Src) +{ + timer->TRGCTL = (timer->TRGCTL & ~TIMER_TRGCTL_TRGSSEL_Msk) | u32Src; +} + +/** + * @brief This function is used to set modules trigger by timer interrupt + * @param[in] timer The base address of Timer module + * @param[in] u32Mask The mask of modules (EPWM, EADC, DAC and PDMA) trigger by timer. Is the combination of + * - \ref TIMER_TRG_TO_EPWM, + * - \ref TIMER_TRG_TO_EADC, and + * - \ref TIMER_TRG_TO_PDMA + * @return None + */ +void TIMER_SetTriggerTarget(TIMER_T *timer, uint32_t u32Mask) +{ + timer->TRGCTL = (timer->TRGCTL & ~(TIMER_TRGCTL_TRGPWM_Msk | TIMER_TRGCTL_TRGEADC_Msk | TIMER_TRGCTL_TRGPDMA_Msk)) | u32Mask; +} + +/*@}*/ /* end of group TIMER_EXPORTED_FUNCTIONS */ + +/*@}*/ /* end of group TIMER_Driver */ + +/*@}*/ /* end of group Standard_Driver */ + diff --git a/bsp/nuvoton/libraries/ma35/StdDriver/src/nu_timer_pwm.c b/bsp/nuvoton/libraries/ma35/StdDriver/src/nu_timer_pwm.c new file mode 100644 index 0000000000..9118564109 --- /dev/null +++ b/bsp/nuvoton/libraries/ma35/StdDriver/src/nu_timer_pwm.c @@ -0,0 +1,437 @@ +/**************************************************************************//** + * @file timer_pwm.c + * @brief Timer PWM Controller(Timer PWM) driver source file + * + * SPDX-License-Identifier: Apache-2.0 + * @copyright (C) 2020 Nuvoton Technology Corp. All rights reserved. + *****************************************************************************/ +#include "NuMicro.h" + + +/** @addtogroup Standard_Driver Standard Driver + @{ +*/ + +/** @addtogroup TIMER_PWM_Driver TIMER PWM Driver + @{ +*/ + +/** @addtogroup TIMER_PWM_EXPORTED_FUNCTIONS TIMER PWM Exported Functions + @{ +*/ + +/** + * @brief Set PWM Counter Clock Source + * + * @param[in] timer The pointer of the specified Timer module. It could be TIMER2 ~ TIMER11. + * @param[in] u32CntClkSrc PWM counter clock source, could be one of following source + * - \ref TPWM_CNTR_CLKSRC_TMR_CLK + * - \ref TPWM_CNTR_CLKSRC_TIMER2_INT + * - \ref TPWM_CNTR_CLKSRC_TIMER3_INT + * - \ref TPWM_CNTR_CLKSRC_TIMER4_INT + * - \ref TPWM_CNTR_CLKSRC_TIMER5_INT + * + * @return None + * + * @details This function is used to set PWM counter clock source. + */ +void TPWM_SetCounterClockSource(TIMER_T *timer, uint32_t u32CntClkSrc) +{ + (timer)->PWMCLKSRC = ((timer)->PWMCLKSRC & ~TIMER_PWMCLKSRC_CLKSRC_Msk) | u32CntClkSrc; +} + +/** + * @brief Configure PWM Output Frequency and Duty Cycle + * + * @param[in] timer The pointer of the specified Timer module. It could be TIMER2 ~ TIMER11. + * @param[in] u32Frequency Target generator frequency. + * @param[in] u32DutyCycle Target generator duty cycle percentage. Valid range are between 0~100. 10 means 10%, 20 means 20%... + * + * @return Nearest frequency clock in nano second + * + * @details This API is used to configure PWM output frequency and duty cycle in up count type and auto-reload operation mode. + * @note This API is only available if Timer PWM counter clock source is from TMRx_CLK. + */ +uint32_t TPWM_ConfigOutputFreqAndDuty(TIMER_T *timer, uint32_t u32Frequency, uint32_t u32DutyCycle) +{ + uint32_t u32PWMClockFreq, u32TargetFreq; + uint32_t u32Prescaler = 0x1000UL, u32Period, u32CMP; + + u32PWMClockFreq = CLK_GetSYSCLK1Freq(); + + /* Calculate u16PERIOD and u16PSC */ + for (u32Prescaler = 1UL; u32Prescaler <= 0x1000UL; u32Prescaler++) + { + u32Period = (u32PWMClockFreq / u32Prescaler) / u32Frequency; + + /* If target u32Period is larger than 0x10000, need to use a larger prescaler */ + if (u32Period <= 0x10000UL) + { + break; + } + } + + /* Store return value here 'cos we're gonna change u32Prescaler & u32Period to the real value to fill into register */ + u32TargetFreq = (u32PWMClockFreq / u32Prescaler) / u32Period; + + /* Set PWM to up count type */ + timer->PWMCTL = (timer->PWMCTL & ~TIMER_PWMCTL_CNTTYPE_Msk) | (TPWM_UP_COUNT << TIMER_PWMCTL_CNTTYPE_Pos); + + /* Set PWM to auto-reload mode */ + timer->PWMCTL = (timer->PWMCTL & ~TIMER_PWMCTL_CNTMODE_Msk) | TPWM_AUTO_RELOAD_MODE; + + /* Convert to real register value */ + TPWM_SET_PRESCALER(timer, (u32Prescaler - 1UL)); + + TPWM_SET_PERIOD(timer, (u32Period - 1UL)); + + if (u32DutyCycle) + { + u32CMP = (u32DutyCycle * u32Period) / 100UL; + } + else + { + u32CMP = 0UL; + } + + TPWM_SET_CMPDAT(timer, u32CMP); + + return (u32TargetFreq); +} + +/** + * @brief Enable Dead-Time Function + * + * @param[in] timer The pointer of the specified Timer module. It could be TIMER2 ~ TIMER11. + * @param[in] u32DTCount Dead-Time duration in PWM clock count, valid values are between 0x0~0xFFF, but 0x0 means there is no Dead-Time insertion. + * + * @return None + * + * @details This function is used to enable Dead-Time function and counter source is the same as Timer PWM clock source. + * @note The register write-protection function should be disabled before using this function. + */ +void TPWM_EnableDeadTime(TIMER_T *timer, uint32_t u32DTCount) +{ + timer->PWMDTCTL = TIMER_PWMDTCTL_DTEN_Msk | u32DTCount; +} + +/** + * @brief Enable Dead-Time Function + * + * @param[in] timer The pointer of the specified Timer module. It could be TIMER2 ~ TIMER11. + * @param[in] u32DTCount Dead-Time duration in PWM clock count, valid values are between 0x0~0xFFF, but 0x0 means there is no Dead-Time insertion. + * + * @return None + * + * @details This function is used to enable Dead-Time function and counter source is the Timer PWM clock source with prescale. + * @note The register write-protection function should be disabled before using this function. + */ +void TPWM_EnableDeadTimeWithPrescale(TIMER_T *timer, uint32_t u32DTCount) +{ + timer->PWMDTCTL = TIMER_PWMDTCTL_DTCKSEL_Msk | TIMER_PWMDTCTL_DTEN_Msk | u32DTCount; +} + +/** + * @brief Disable Dead-Time Function + * + * @param[in] timer The pointer of the specified Timer module. It could be TIMER2 ~ TIMER11. + * + * @return None + * + * @details This function is used to enable Dead-time of selected channel. + * @note The register write-protection function should be disabled before using this function. + */ +void TPWM_DisableDeadTime(TIMER_T *timer) +{ + timer->PWMDTCTL = 0x0UL; +} + +/** + * @brief Enable PWM Counter + * + * @param[in] timer The pointer of the specified Timer module. It could be TIMER2 ~ TIMER11. + * + * @return None + * + * @details This function is used to enable PWM generator and start counter counting. + */ +void TPWM_EnableCounter(TIMER_T *timer) +{ + timer->PWMCTL |= TIMER_PWMCTL_CNTEN_Msk; +} + +/** + * @brief Disable PWM Generator + * + * @param[in] timer The pointer of the specified Timer module. It could be TIMER2 ~ TIMER11. + * + * @return None + * + * @details This function is used to disable PWM counter immediately by clear CNTEN (TIMERx_PWMCTL[0]) bit. + */ +void TPWM_DisableCounter(TIMER_T *timer) +{ + timer->PWMCTL &= ~TIMER_PWMCTL_CNTEN_Msk; +} + +/** + * @brief Enable Trigger ADC + * + * @param[in] timer The pointer of the specified Timer module. It could be TIMER2 ~ TIMER11. + * @param[in] u32Condition The condition to trigger ADC. It could be one of following conditions: + * - \ref TPWM_TRIGGER_ADC_AT_ZERO_POINT + * - \ref TPWM_TRIGGER_ADC_AT_PERIOD_POINT + * - \ref TPWM_TRIGGER_ADC_AT_ZERO_OR_PERIOD_POINT + * - \ref TPWM_TRIGGER_ADC_AT_COMPARE_UP_COUNT_POINT + * - \ref TPWM_TRIGGER_ADC_AT_COMPARE_DOWN_COUNT_POINT + * + * @return None + * + * @details This function is used to enable specified counter compare event to trigger ADC. + */ +void TPWM_EnableTriggerADC(TIMER_T *timer, uint32_t u32Condition) +{ + timer->PWMEADCTS = TIMER_PWMEADCTS_TRGEN_Msk | u32Condition; +} + +/** + * @brief Disable Trigger ADC + * + * @param[in] timer The pointer of the specified Timer module. It could be TIMER2 ~ TIMER11. + * + * @return None + * + * @details This function is used to disable counter compare event to trigger ADC. + */ +void TPWM_DisableTriggerADC(TIMER_T *timer) +{ + timer->PWMEADCTS = 0x0UL; +} + +/** + * @brief Enable Fault Brake Function + * + * @param[in] timer The pointer of the specified Timer module. It could be TIMER2 ~ TIMER11. + * @param[in] u32CH0Level PWMx_CH0 output level while fault brake event occurs. Valid value is one of following setting + * - \ref TPWM_OUTPUT_TOGGLE + * - \ref TPWM_OUTPUT_NOTHING + * - \ref TPWM_OUTPUT_LOW + * - \ref TPWM_OUTPUT_HIGH + * @param[in] u32CH1Level PWMx_CH1 output level while fault brake event occurs. Valid value is one of following setting + * - \ref TPWM_OUTPUT_TOGGLE + * - \ref TPWM_OUTPUT_NOTHING + * - \ref TPWM_OUTPUT_LOW + * - \ref TPWM_OUTPUT_HIGH + * @param[in] u32BrakeSource Fault brake source, combination of following source + * - \ref TPWM_BRAKE_SOURCE_EDGE_ACMP0 + * - \ref TPWM_BRAKE_SOURCE_EDGE_ACMP1 + * - \ref TPWM_BRAKE_SOURCE_EDGE_BKPIN + * - \ref TPWM_BRAKE_SOURCE_EDGE_SYS_CSS + * - \ref TPWM_BRAKE_SOURCE_EDGE_SYS_BOD + * - \ref TPWM_BRAKE_SOURCE_EDGE_SYS_COR + * - \ref TPWM_BRAKE_SOURCE_EDGE_SYS_RAM + * - \ref TPWM_BRAKE_SOURCE_LEVEL_ACMP0 + * - \ref TPWM_BRAKE_SOURCE_LEVEL_ACMP1 + * - \ref TPWM_BRAKE_SOURCE_LEVEL_BKPIN + * - \ref TPWM_BRAKE_SOURCE_LEVEL_SYS_CSS + * - \ref TPWM_BRAKE_SOURCE_LEVEL_SYS_BOD + * - \ref TPWM_BRAKE_SOURCE_LEVEL_SYS_COR + * - \ref TPWM_BRAKE_SOURCE_LEVEL_SYS_RAM + * + * @return None + * + * @details This function is used to enable fault brake function. + * @note The register write-protection function should be disabled before using this function. + */ +void TPWM_EnableFaultBrake(TIMER_T *timer, uint32_t u32CH0Level, uint32_t u32CH1Level, uint32_t u32BrakeSource) +{ + timer->PWMFAILBRK |= ((u32BrakeSource >> 16) & 0xFUL); + timer->PWMBRKCTL = (timer->PWMBRKCTL & ~(TIMER_PWMBRKCTL_BRKAEVEN_Msk | TIMER_PWMBRKCTL_BRKAODD_Msk)) | + (u32BrakeSource & 0xFFFFUL) | (u32CH0Level << TIMER_PWMBRKCTL_BRKAEVEN_Pos) | (u32CH1Level << TIMER_PWMBRKCTL_BRKAODD_Pos); +} + +/** + * @brief Enable Fault Brake Interrupt + * + * @param[in] timer The pointer of the specified Timer module. It could be TIMER2 ~ TIMER11. + * @param[in] u32IntSource Interrupt source, could be one of following source + * - \ref TPWM_BRAKE_EDGE + * - \ref TPWM_BRAKE_LEVEL + * + * @return None + * + * @details This function is used to enable fault brake interrupt. + * @note The register write-protection function should be disabled before using this function. + */ +void TPWM_EnableFaultBrakeInt(TIMER_T *timer, uint32_t u32IntSource) +{ + timer->PWMINTEN1 |= u32IntSource; +} + +/** + * @brief Disable Fault Brake Interrupt + * + * @param[in] timer The pointer of the specified Timer module. It could be TIMER2 ~ TIMER11. + * @param[in] u32IntSource Interrupt source, could be one of following source + * - \ref TPWM_BRAKE_EDGE + * - \ref TPWM_BRAKE_LEVEL + * + * @return None + * + * @details This function is used to disable fault brake interrupt. + * @note The register write-protection function should be disabled before using this function. + */ +void TPWM_DisableFaultBrakeInt(TIMER_T *timer, uint32_t u32IntSource) +{ + timer->PWMINTEN1 &= ~u32IntSource; +} + +/** + * @brief Indicate Fault Brake Interrupt Flag + * + * @param[in] timer The pointer of the specified Timer module. It could be TIMER2 ~ TIMER11. + * @param[in] u32IntSource Interrupt source, could be one of following source + * - \ref TPWM_BRAKE_EDGE + * - \ref TPWM_BRAKE_LEVEL + * + * @return Fault brake interrupt flag of specified source + * @retval 0 Fault brake interrupt did not occurred + * @retval 1 Fault brake interrupt occurred + * + * @details This function is used to indicate fault brake interrupt flag occurred or not of selected source. + */ +uint32_t TPWM_GetFaultBrakeIntFlag(TIMER_T *timer, uint32_t u32IntSource) +{ + return ((timer->PWMINTSTS1 & (0x3UL << u32IntSource)) ? 1UL : 0UL); +} + +/** + * @brief Clear Fault Brake Interrupt Flags + * + * @param[in] timer The pointer of the specified Timer module. It could be TIMER2 ~ TIMER11. + * @param[in] u32IntSource Interrupt source, could be one of following source + * - \ref TPWM_BRAKE_EDGE + * - \ref TPWM_BRAKE_LEVEL + * + * @return None + * + * @details This function is used to clear fault brake interrupt flags of selected source. + * @note The register write-protection function should be disabled before using this function. + */ +void TPWM_ClearFaultBrakeIntFlag(TIMER_T *timer, uint32_t u32IntSource) +{ + timer->PWMINTSTS1 = (0x3UL << u32IntSource); +} + +/** + * @brief Enable load mode of selected channel + * + * @param[in] timer The pointer of the specified Timer module. It could be TIMER2 ~ TIMER11. + * @param[in] u32LoadMode Timer PWM counter loading mode, could be one of following mode + * - \ref TPWM_LOAD_MODE_PERIOD + * - \ref TPWM_LOAD_MODE_IMMEDIATE + * - \ref TPWM_LOAD_MODE_CENTER + * + * @return None + * + * @details This function is used to enable load mode of selected channel. + * @note The default loading mode is period loading mode. + */ +void TPWM_SetLoadMode(TIMER_T *timer, uint32_t u32LoadMode) +{ + timer->PWMCTL = (timer->PWMCTL & ~(TIMER_PWMCTL_IMMLDEN_Msk | TIMER_PWMCTL_CTRLD_Msk)) | u32LoadMode; +} + +/** + * @brief Enable brake pin noise filter function + * + * @param[in] timer The pointer of the specified Timer module. It could be TIMER2 ~ TIMER11. + * @param[in] u32BrakePinSrc The external brake pin source, could be one of following source + * - \ref TPWM_TM_BRAKE0 + * - \ref TPWM_TM_BRAKE1 + * - \ref TPWM_TM_BRAKE2 + * - \ref TPWM_TM_BRAKE3 + * @param[in] u32DebounceCnt This value controls the real debounce sample time. + * The target debounce sample time is (debounce sample clock period) * (u32DebounceCnt). + * @param[in] u32ClkSrcSel Brake pin detector debounce clock source, could be one of following source + * - \ref TPWM_BKP_DBCLK_PCLK_DIV_1 + * - \ref TPWM_BKP_DBCLK_PCLK_DIV_2 + * - \ref TPWM_BKP_DBCLK_PCLK_DIV_4 + * - \ref TPWM_BKP_DBCLK_PCLK_DIV_8 + * - \ref TPWM_BKP_DBCLK_PCLK_DIV_16 + * - \ref TPWM_BKP_DBCLK_PCLK_DIV_32 + * - \ref TPWM_BKP_DBCLK_PCLK_DIV_64 + * - \ref TPWM_BKP_DBCLK_PCLK_DIV_128 + * + * @return None + * + * @details This function is used to enable external brake pin detector noise filter function. + */ +void TPWM_EnableBrakePinDebounce(TIMER_T *timer, uint32_t u32BrakePinSrc, uint32_t u32DebounceCnt, uint32_t u32ClkSrcSel) +{ + timer->PWMBNF = (timer->PWMBNF & ~(TIMER_PWMBNF_BKPINSRC_Msk | TIMER_PWMBNF_BRKFCNT_Msk | TIMER_PWMBNF_BRKNFSEL_Msk)) | + (u32BrakePinSrc << TIMER_PWMBNF_BKPINSRC_Pos) | + (u32DebounceCnt << TIMER_PWMBNF_BRKFCNT_Pos) | + (u32ClkSrcSel << TIMER_PWMBNF_BRKNFSEL_Pos) | TIMER_PWMBNF_BRKNFEN_Msk; +} + +/** + * @brief Disable brake pin noise filter function + * + * @param[in] timer The pointer of the specified Timer module. It could be TIMER2 ~ TIMER11. + * + * @return None + * + * @details This function is used to disable external brake pin detector noise filter function. + */ +void TPWM_DisableBrakePinDebounce(TIMER_T *timer) +{ + timer->PWMBNF &= ~TIMER_PWMBNF_BRKNFEN_Msk; +} + + +/** + * @brief Enable brake pin inverse function + * @param[in] timer The pointer of the specified Timer module. It could be TIMER2 ~ TIMER11. + * @return None + * @details This function is used to enable PWM brake pin inverse function. + */ +void TPWM_EnableBrakePinInverse(TIMER_T *timer) +{ + timer->PWMBNF |= TIMER_PWMBNF_BRKPINV_Msk; +} + +/** + * @brief Disable brake pin inverse function + * @param[in] timer The pointer of the specified Timer module. It could be TIMER2 ~ TIMER11. + * @return None + * @details This function is used to disable PWM brake pin inverse function. + */ +void TPWM_DisableBrakePinInverse(TIMER_T *timer) +{ + timer->PWMBNF &= ~TIMER_PWMBNF_BRKPINV_Msk; +} + +/** + * @brief Set brake pin source + * @param[in] timer The pointer of the specified Timer module. It could be TIMER2 ~ TIMER11. + * @param[in] u32BrakePinNum Brake pin selection. One of the following: + * - \ref TPWM_TM_BRAKE0 + * - \ref TPWM_TM_BRAKE1 + * - \ref TPWM_TM_BRAKE2 + * - \ref TPWM_TM_BRAKE3 + * @return None + * @details This function is used to set PWM brake pin source. + */ +void TPWM_SetBrakePinSource(TIMER_T *timer, uint32_t u32BrakePinNum) +{ + timer->PWMBNF = (((timer)->PWMBNF & ~TIMER_PWMBNF_BKPINSRC_Msk) | (u32BrakePinNum << TIMER_PWMBNF_BKPINSRC_Pos)); +} + + +/*@}*/ /* end of group TIMER_PWM_EXPORTED_FUNCTIONS */ + +/*@}*/ /* end of group TIMER_PWM_Driver */ + +/*@}*/ /* end of group Standard_Driver */ + diff --git a/bsp/nuvoton/libraries/ma35/StdDriver/src/nu_uart.c b/bsp/nuvoton/libraries/ma35/StdDriver/src/nu_uart.c new file mode 100644 index 0000000000..4b4a8a43f0 --- /dev/null +++ b/bsp/nuvoton/libraries/ma35/StdDriver/src/nu_uart.c @@ -0,0 +1,545 @@ +/**************************************************************************//** + * @file uart.c + * @brief UART driver source file + * + * SPDX-License-Identifier: Apache-2.0 + * @copyright (C) 2020 Nuvoton Technology Corp. All rights reserved. + *****************************************************************************/ + +#include +#include "NuMicro.h" + +/** @addtogroup Standard_Driver Standard Driver + @{ +*/ + +/** @addtogroup UART_Driver UART Driver + @{ +*/ + +/** @addtogroup UART_EXPORTED_FUNCTIONS UART Exported Functions + @{ +*/ + +static void UART_GetSrcClkSetting(UART_T *uart, uint32_t *pu32ClkSrcFreq, uint32_t *pu32ClkDivNum); + +/** + * @brief This function make UART module be ready to transfer. + * @param[in] pu32ClkSrcFreq will return UART source clock frequency(In HZ). + * @param[in] pu32ClkSrcFreq will return UART source clock frequency(In HZ). + * @param[in] pu32ClkDivNum will return UART source clock divider. + * @return None. + * @details + * 0: HXT + * 1: SYSCLK1 + * 2: LXT + * 3: HIRC + * @note If u32BusClock = 0, DIVIDER setting will be set to the maximum value. + */ + +static void UART_GetSrcClkSetting(UART_T *uart, uint32_t *pu32ClkSrcFreq, uint32_t *pu32ClkDivNum) +{ + uint32_t u32UartClkSrcSel = 0u, u32UartClkDivNum = 0u; + uint32_t u32SrcClkFreq = 0u; + uint32_t u32UartPort; + + if (uart == (UART_T *)UART16) + { + u32UartPort = 16; + } + else + { + u32UartPort = ((uint32_t)uart & 0xf0000) >> 16; + } + + if (u32UartPort < 8) + { + u32UartClkSrcSel = ((CLK->CLKSEL2 >> (16 + u32UartPort * 2)) & 0x3ul); + + if (u32UartPort < 4) + { + u32UartClkDivNum = ((CLK->CLKDIV1 >> ((u32UartPort + 4) * 4)) & 0xful); + } + else + { + u32UartClkDivNum = ((CLK->CLKDIV2 >> ((u32UartPort - 4) * 4)) & 0xful); + } + } + else if (u32UartPort <= 16) + { + u32UartClkSrcSel = ((CLK->CLKSEL3 >> ((u32UartPort - 8) * 2)) & 0x3ul); + + if (u32UartPort < 12) + { + u32UartClkDivNum = ((CLK->CLKDIV2 >> ((u32UartPort - 4) * 4)) & 0xful); + } + else + { + u32UartClkDivNum = ((CLK->CLKDIV3 >> ((u32UartPort - 12) * 4)) & 0xful); + } + } + + /* Get PLL clock frequency if UART clock source selection is PLL */ + switch (u32UartClkSrcSel) + { + case 0u: + u32SrcClkFreq = __HXT; + break; + case 1u: + u32SrcClkFreq = CLK_GetSYSCLK1Freq(); //TODO + break; + default: + u32SrcClkFreq = 0; + break; + } + + if (pu32ClkSrcFreq) + *pu32ClkSrcFreq = u32SrcClkFreq; + + if (pu32ClkDivNum) + *pu32ClkDivNum = u32UartClkDivNum; +} + +/** + * @brief Clear UART specified interrupt flag + * + * @param[in] uart The pointer of the specified UART module. + * @param[in] u32InterruptFlag The specified interrupt of UART module. + * - \ref UART_INTSTS_WKIF_Msk : Wake-up interrupt + * - \ref UART_INTSTS_BUFEINT_Msk : Buffer Error interrupt + * - \ref UART_INTSTS_MODEMINT_Msk : Modem Status interrupt + * - \ref UART_INTSTS_RLSINT_Msk : Receive Line Status interrupt + * + * @return None + * + * @details The function is used to clear UART specified interrupt flag. + */ + +void UART_ClearIntFlag(UART_T *uart, uint32_t u32InterruptFlag) +{ + + if (u32InterruptFlag & UART_INTSTS_RLSINT_Msk) /* Clear Receive Line Status Interrupt */ + { + uart->FIFOSTS = UART_FIFOSTS_BIF_Msk | UART_FIFOSTS_FEF_Msk | UART_FIFOSTS_PEF_Msk; + uart->FIFOSTS = UART_FIFOSTS_ADDRDETF_Msk; + } + + if (u32InterruptFlag & UART_INTSTS_MODEMINT_Msk) /* Clear Modem Status Interrupt */ + { + uart->MODEMSTS |= UART_MODEMSTS_CTSDETF_Msk; + } + else + { + } + + if (u32InterruptFlag & UART_INTSTS_BUFEINT_Msk) /* Clear Buffer Error Interrupt */ + { + uart->FIFOSTS = UART_FIFOSTS_RXOVIF_Msk | UART_FIFOSTS_TXOVIF_Msk; + } + + if (u32InterruptFlag & UART_INTSTS_WKINT_Msk) /* Clear Wake-up Interrupt */ + { + uart->WKSTS = UART_WKSTS_CTSWKF_Msk | UART_WKSTS_DATWKF_Msk | + UART_WKSTS_RFRTWKF_Msk | UART_WKSTS_RS485WKF_Msk | + UART_WKSTS_TOUTWKF_Msk; + } + +} + + +/** + * @brief Disable UART interrupt + * + * @param[in] uart The pointer of the specified UART module. + * + * @return None + * + * @details The function is used to disable UART interrupt. + */ +void UART_Close(UART_T *uart) +{ + uart->INTEN = 0ul; +} + + +/** + * @brief Disable UART auto flow control function + * + * @param[in] uart The pointer of the specified UART module. + * + * @return None + * + * @details The function is used to disable UART auto flow control. + */ +void UART_DisableFlowCtrl(UART_T *uart) +{ + uart->INTEN &= ~(UART_INTEN_ATORTSEN_Msk | UART_INTEN_ATOCTSEN_Msk); +} + + +/** + * @brief Disable UART specified interrupt + * + * @param[in] uart The pointer of the specified UART module. + * @param[in] u32InterruptFlag The specified interrupt of UART module. + * - \ref UART_INTEN_WKIEN_Msk : Wake-up interrupt + * - \ref UART_INTEN_BUFEIEN_Msk : Buffer Error interrupt + * - \ref UART_INTEN_RXTOIEN_Msk : Rx time-out interrupt + * - \ref UART_INTEN_MODEMIEN_Msk : Modem status interrupt + * - \ref UART_INTEN_RLSIEN_Msk : Receive Line status interrupt + * - \ref UART_INTEN_THREIEN_Msk : Tx empty interrupt + * - \ref UART_INTEN_RDAIEN_Msk : Rx ready interrupt * + * + * @return None + * + * @details The function is used to disable UART specified interrupt and disable NVIC UART IRQ. + */ +void UART_DisableInt(UART_T *uart, uint32_t u32InterruptFlag) +{ + /* Disable UART specified interrupt */ + UART_DISABLE_INT(uart, u32InterruptFlag); +} + + +/** + * @brief Enable UART auto flow control function + * + * @param[in] uart The pointer of the specified UART module. + * + * @return None + * + * @details The function is used to Enable UART auto flow control. + */ +void UART_EnableFlowCtrl(UART_T *uart) +{ + /* Set RTS pin output is low level active */ + uart->MODEM |= UART_MODEM_RTSACTLV_Msk; + + /* Set CTS pin input is low level active */ + uart->MODEMSTS |= UART_MODEMSTS_CTSACTLV_Msk; + + /* Set RTS and CTS auto flow control enable */ + uart->INTEN |= UART_INTEN_ATORTSEN_Msk | UART_INTEN_ATOCTSEN_Msk; +} + + +/** + * @brief The function is used to enable UART specified interrupt and enable NVIC UART IRQ. + * + * @param[in] uart The pointer of the specified UART module. + * @param[in] u32InterruptFlag The specified interrupt of UART module: + * - \ref UART_INTEN_WKIEN_Msk : Wake-up interrupt + * - \ref UART_INTEN_BUFEIEN_Msk : Buffer Error interrupt + * - \ref UART_INTEN_RXTOIEN_Msk : Rx time-out interrupt + * - \ref UART_INTEN_MODEMIEN_Msk : Modem status interrupt + * - \ref UART_INTEN_RLSIEN_Msk : Receive Line status interrupt + * - \ref UART_INTEN_THREIEN_Msk : Tx empty interrupt + * - \ref UART_INTEN_RDAIEN_Msk : Rx ready interrupt * + * + * @return None + * + * @details The function is used to enable UART specified interrupt and enable NVIC UART IRQ. + */ +void UART_EnableInt(UART_T *uart, uint32_t u32InterruptFlag) +{ + /* Enable UART specified interrupt */ + UART_ENABLE_INT(uart, u32InterruptFlag); +} + + +/** + * @brief Open and set UART function + * + * @param[in] uart The pointer of the specified UART module. + * @param[in] u32baudrate The baudrate of UART module. + * + * @return None + * + * @details This function use to enable UART function and set baud-rate. + */ +void UART_Open(UART_T *uart, uint32_t u32baudrate) +{ + uint32_t u32UartSrcClkFreq = 0ul, u32UartClkDivNum = 0ul; + uint32_t u32Baud_Div = 0ul; + + /* Select UART function */ + uart->FUNCSEL = UART_FUNCSEL_UART; + + /* Set UART line configuration */ + uart->LINE = UART_WORD_LEN_8 | UART_PARITY_NONE | UART_STOP_BIT_1; + + /* Set UART Rx and RTS trigger level */ + uart->FIFO &= ~(UART_FIFO_RFITL_Msk | UART_FIFO_RTSTRGLV_Msk); + + /* Get Source clock frequency and its divider of curret setting */ + UART_GetSrcClkSetting(uart, &u32UartSrcClkFreq, &u32UartClkDivNum); + + /* Set UART baud rate */ + if (u32baudrate != 0ul) + { + u32Baud_Div = UART_BAUD_MODE2_DIVIDER(u32UartSrcClkFreq / (u32UartClkDivNum + 1ul), u32baudrate); + + if (u32Baud_Div > 0xFFFFul) + { + uart->BAUD = (UART_BAUD_MODE0 | UART_BAUD_MODE0_DIVIDER(u32UartSrcClkFreq / (u32UartClkDivNum + 1ul), u32baudrate)); + } + else + { + uart->BAUD = (UART_BAUD_MODE2 | u32Baud_Div); + } + } +} + + +/** + * @brief Read UART data + * + * @param[in] uart The pointer of the specified UART module. + * @param[in] pu8RxBuf The buffer to receive the data of receive FIFO. + * @param[in] u32ReadBytes The the read bytes number of data. + * + * @return u32Count Receive byte count + * + * @details The function is used to read Rx data from RX FIFO and the data will be stored in pu8RxBuf. + */ +uint32_t UART_Read(UART_T *uart, uint8_t pu8RxBuf[], uint32_t u32ReadBytes) +{ + uint32_t u32Count, u32delayno; + uint32_t u32Exit = 0ul; + + for (u32Count = 0ul; u32Count < u32ReadBytes; u32Count++) + { + u32delayno = 0ul; + + while (uart->FIFOSTS & UART_FIFOSTS_RXEMPTY_Msk) /* Check RX empty => failed */ + { + u32delayno++; + if (u32delayno >= 0x40000000ul) + { + u32Exit = 1ul; + break; + } + else + { + } + } + + if (u32Exit == 1ul) + { + break; + } + else + { + pu8RxBuf[u32Count] = (uint8_t)uart->DAT; /* Get Data from UART RX */ + } + } + + return u32Count; + +} + + +/** + * @brief Set UART line configuration + * + * @param[in] uart The pointer of the specified UART module. + * @param[in] u32baudrate The register value of baudrate of UART module. + * If u32baudrate = 0, UART baudrate will not change. + * @param[in] u32data_width The data length of UART module. + * - \ref UART_WORD_LEN_5 + * - \ref UART_WORD_LEN_6 + * - \ref UART_WORD_LEN_7 + * - \ref UART_WORD_LEN_8 + * @param[in] u32parity The parity setting (none/odd/even/mark/space) of UART module. + * - \ref UART_PARITY_NONE + * - \ref UART_PARITY_ODD + * - \ref UART_PARITY_EVEN + * - \ref UART_PARITY_MARK + * - \ref UART_PARITY_SPACE + * @param[in] u32stop_bits The stop bit length (1/1.5/2 bit) of UART module. + * - \ref UART_STOP_BIT_1 + * - \ref UART_STOP_BIT_1_5 + * - \ref UART_STOP_BIT_2 + * + * @return None + * + * @details This function use to config UART line setting. + */ +void UART_SetLineConfig(UART_T *uart, uint32_t u32baudrate, uint32_t u32data_width, uint32_t u32parity, uint32_t u32stop_bits) +{ + uint32_t u32UartSrcClkFreq = 0ul, u32UartClkDivNum = 0ul; + uint32_t u32Baud_Div = 0ul; + + /* Get Source clock frequency and its divider of curret setting */ + UART_GetSrcClkSetting(uart, &u32UartSrcClkFreq, &u32UartClkDivNum); + + /* Set UART baud rate */ + if (u32baudrate != 0ul) + { + u32Baud_Div = UART_BAUD_MODE2_DIVIDER(u32UartSrcClkFreq / (u32UartClkDivNum + 1ul), u32baudrate); + + if (u32Baud_Div > 0xFFFFul) + { + uart->BAUD = (UART_BAUD_MODE0 | UART_BAUD_MODE0_DIVIDER(u32UartSrcClkFreq / (u32UartClkDivNum + 1ul), u32baudrate)); + } + else + { + uart->BAUD = (UART_BAUD_MODE2 | u32Baud_Div); + } + } + + /* Set UART line configuration */ + uart->LINE = u32data_width | u32parity | u32stop_bits; +} + + +/** + * @brief Set Rx timeout count + * + * @param[in] uart The pointer of the specified UART module. + * @param[in] u32TOC Rx timeout counter. + * + * @return None + * + * @details This function use to set Rx timeout count. + */ +void UART_SetTimeoutCnt(UART_T *uart, uint32_t u32TOC) +{ + /* Set time-out interrupt comparator */ + uart->TOUT = (uart->TOUT & ~UART_TOUT_TOIC_Msk) | (u32TOC); + + /* Set time-out counter enable */ + uart->INTEN |= UART_INTEN_TOCNTEN_Msk; +} + + +/** + * @brief Select and configure IrDA function + * + * @param[in] uart The pointer of the specified UART module. + * @param[in] u32Buadrate The baudrate of UART module. + * @param[in] u32Direction The direction of UART module in IrDA mode: + * - \ref UART_IRDA_TXEN + * - \ref UART_IRDA_RXEN + * + * @return None + * + * @details The function is used to configure IrDA relative settings. It consists of TX or RX mode and baudrate. + */ +void UART_SelectIrDAMode(UART_T *uart, uint32_t u32Buadrate, uint32_t u32Direction) +{ + uint32_t u32UartSrcClkFreq = 0ul, u32UartClkDivNum = 0ul; + uint32_t u32Baud_Div; + + /* Select IrDA function mode */ + uart->FUNCSEL = UART_FUNCSEL_IrDA; + + /* Get Source clock frequency and its divider of curret setting */ + UART_GetSrcClkSetting(uart, &u32UartSrcClkFreq, &u32UartClkDivNum); + + /* Set UART IrDA baud rate in mode 0 */ + if (u32Buadrate != 0ul) + { + u32Baud_Div = UART_BAUD_MODE0_DIVIDER(u32UartSrcClkFreq / (u32UartClkDivNum + 1ul), u32Buadrate); + + if (u32Baud_Div < 0xFFFFul) + { + uart->BAUD = (UART_BAUD_MODE0 | u32Baud_Div); + } + else + { + } + } + + /* Configure IrDA relative settings */ + if (u32Direction == UART_IRDA_RXEN) + { + uart->IRDA |= UART_IRDA_RXINV_Msk; /*Rx signal is inverse*/ + uart->IRDA &= ~UART_IRDA_TXEN_Msk; + } + else + { + uart->IRDA &= ~UART_IRDA_TXINV_Msk; /*Tx signal is not inverse*/ + uart->IRDA |= UART_IRDA_TXEN_Msk; + } + +} + + +/** + * @brief Select and configure RS485 function + * + * @param[in] uart The pointer of the specified UART module. + * @param[in] u32Mode The operation mode(NMM/AUD/AAD). + * - \ref UART_ALTCTL_RS485NMM_Msk + * - \ref UART_ALTCTL_RS485AUD_Msk + * - \ref UART_ALTCTL_RS485AAD_Msk + * @param[in] u32Addr The RS485 address. + * + * @return None + * + * @details The function is used to set RS485 relative setting. + */ +void UART_SelectRS485Mode(UART_T *uart, uint32_t u32Mode, uint32_t u32Addr) +{ + /* Select UART RS485 function mode */ + uart->FUNCSEL = UART_FUNCSEL_RS485; + + /* Set RS585 configuration */ + uart->ALTCTL &= ~(UART_ALTCTL_RS485NMM_Msk | UART_ALTCTL_RS485AUD_Msk | UART_ALTCTL_RS485AAD_Msk | UART_ALTCTL_ADDRMV_Msk); + uart->ALTCTL |= (u32Mode | (u32Addr << UART_ALTCTL_ADDRMV_Pos)); +} + + +/** + * @brief Write UART data + * + * @param[in] uart The pointer of the specified UART module. + * @param[in] pu8TxBuf The buffer to send the data to UART transmission FIFO. + * @param[out] u32WriteBytes The byte number of data. + * + * @return u32Count transfer byte count + * + * @details The function is to write data into TX buffer to transmit data by UART. + */ +uint32_t UART_Write(UART_T *uart, uint8_t pu8TxBuf[], uint32_t u32WriteBytes) +{ + uint32_t u32Count, u32delayno; + uint32_t u32Exit = 0ul; + + for (u32Count = 0ul; u32Count != u32WriteBytes; u32Count++) + { + u32delayno = 0ul; + while (uart->FIFOSTS & UART_FIFOSTS_TXFULL_Msk) /* Check Tx Full */ + { + u32delayno++; + if (u32delayno >= 0x40000000ul) + { + u32Exit = 1ul; + break; + } + else + { + } + } + + if (u32Exit == 1ul) + { + break; + } + else + { + uart->DAT = pu8TxBuf[u32Count]; /* Send UART Data from buffer */ + } + } + + return u32Count; +} + + +/*@}*/ /* end of group UART_EXPORTED_FUNCTIONS */ + +/*@}*/ /* end of group UART_Driver */ + +/*@}*/ /* end of group Standard_Driver */ + diff --git a/bsp/nuvoton/libraries/ma35/StdDriver/src/nu_wdt.c b/bsp/nuvoton/libraries/ma35/StdDriver/src/nu_wdt.c new file mode 100644 index 0000000000..71a8efc2d2 --- /dev/null +++ b/bsp/nuvoton/libraries/ma35/StdDriver/src/nu_wdt.c @@ -0,0 +1,68 @@ +/**************************************************************************//** + * @file wdt.c + * @brief WDT driver source file + * + * SPDX-License-Identifier: Apache-2.0 + * @copyright (C) 2020 Nuvoton Technology Corp. All rights reserved. +*****************************************************************************/ +#include "NuMicro.h" + + +/** @addtogroup Standard_Driver Standard Driver + @{ +*/ + +/** @addtogroup WDT_Driver WDT Driver + @{ +*/ + +/** @addtogroup WDT_EXPORTED_FUNCTIONS WDT Exported Functions + @{ +*/ + +/** + * @brief Initialize WDT and start counting + * @param[in] wdt WDT instance. + * @param[in] u32TimeoutInterval Time-out interval period of WDT module. Valid values are: + * - \ref WDT_TIMEOUT_2POW4 + * - \ref WDT_TIMEOUT_2POW6 + * - \ref WDT_TIMEOUT_2POW8 + * - \ref WDT_TIMEOUT_2POW10 + * - \ref WDT_TIMEOUT_2POW12 + * - \ref WDT_TIMEOUT_2POW14 + * - \ref WDT_TIMEOUT_2POW16 + * - \ref WDT_TIMEOUT_2POW18 + * @param[in] u32ResetDelay Configure WDT time-out reset delay period. Valid values are: + * - \ref WDT_RESET_DELAY_1026CLK + * - \ref WDT_RESET_DELAY_130CLK + * - \ref WDT_RESET_DELAY_18CLK + * - \ref WDT_RESET_DELAY_3CLK + * @param[in] u32EnableReset Enable WDT time-out reset system function. Valid values are TRUE and FALSE. + * @param[in] u32EnableWakeup Enable WDT time-out wake-up system function. Valid values are TRUE and FALSE. + * + * @return None + * + * @details This function makes WDT module start counting with different time-out interval, reset delay period and choose to \n + * enable or disable WDT time-out reset system or wake-up system. + * @note Please make sure that Register Write-Protection Function has been disabled before using this function. + */ +void WDT_Open(WDT_T *wdt, + uint32_t u32TimeoutInterval, + uint32_t u32ResetDelay, + uint32_t u32EnableReset, + uint32_t u32EnableWakeup) +{ + wdt->ALTCTL = u32ResetDelay; + + wdt->CTL = u32TimeoutInterval | WDT_CTL_WDTEN_Msk | + (u32EnableReset << WDT_CTL_RSTEN_Pos) | + (u32EnableWakeup << WDT_CTL_WKEN_Pos); + return; +} + +/*@}*/ /* end of group WDT_EXPORTED_FUNCTIONS */ + +/*@}*/ /* end of group WDT_Driver */ + +/*@}*/ /* end of group Standard_Driver */ + diff --git a/bsp/nuvoton/libraries/ma35/StdDriver/src/nu_whc.c b/bsp/nuvoton/libraries/ma35/StdDriver/src/nu_whc.c new file mode 100644 index 0000000000..3065fb8ff2 --- /dev/null +++ b/bsp/nuvoton/libraries/ma35/StdDriver/src/nu_whc.c @@ -0,0 +1,100 @@ +/**************************************************************************//** + * @file whc.c + * @brief WHC driver source file + * + * SPDX-License-Identifier: Apache-2.0 + * @copyright (C) 2020 Nuvoton Technology Corp. All rights reserved. + *****************************************************************************/ +#include "NuMicro.h" + +/** @addtogroup Standard_Driver Standard Driver + @{ +*/ + +/** @addtogroup WHC_Driver WHC Driver + @{ +*/ + +/** @addtogroup WHC_EXPORTED_FUNCTIONS WHC Exported Functions + @{ +*/ + +/** + * @brief Send message through a wormhole channel + * @param[in] whc The pointer of the specified WHC module. + * @param[in] u32Ch WHC channel, valid channel numbers are 0~3 + * @param[in] pu32TxBuf The buffer holds the data to send + * @retval 0 Success + * @retval -1 Failed. Channel is busy, previous message hasn't been read yet. + */ +int WHC_Send(WHC_T *whc, uint32_t u32Ch, uint32_t *pu32TxBuf) +{ + int i; + + if (whc->TXSTS & (1ul << u32Ch)) + { + for (i = 0; i < WHC_BUFFER_LEN; i++) + whc->TMDAT[u32Ch][i] = *pu32TxBuf++; + whc->TXCTL = (1ul << u32Ch); + } + else + { + return -1; + + } + return 0; +} + +/** + * @brief Receive message from a wormhole channel + * @param[in] whc The pointer of the specified WHC module. + * @param[in] u32Ch WHC channel, valid channel numbers are 0~3 + * @param[out] pu32RxBuf The buffer to hold the receive data + * @retval 0 Success + * @retval -1 Failed. Channel is empty and no message is available for read. + * @Note This function send an ACK signal after receive complete + */ +int WHC_Recv(WHC_T *whc, uint32_t u32Ch, uint32_t *pu32RxBuf) +{ + int i; + + if (whc->RXSTS & (1ul << u32Ch)) + { + for (i = 0; i < WHC_BUFFER_LEN; i++) + *pu32RxBuf++ = whc->RMDAT[u32Ch][i]; + whc->RXCTL = (1ul << u32Ch); + } + else + { + return -1; + + } + return 0; +} + +/** + * @brief Get counter part status + * @param[in] whc The pointer of the specified WHC module. + * @param[in] u32Core Core number, valid channel numbers are 0~1 + * @retval \ref WHC_RUN_MODE + * @retval \ref WHC_POFF_MODE + * @retval \ref WHC_PD_MODE + */ +int WHC_GetCPSts(WHC_T *whc, uint32_t u32Core) +{ + if (u32Core == 0) + { + return (whc->CPSTS & WHC_CPSTS_OPMODE0_Msk) >> WHC_CPSTS_OPMODE0_Pos; + } + else + { + return (whc->CPSTS & WHC_CPSTS_OPMODE1_Msk) >> WHC_CPSTS_OPMODE1_Pos; + } +} + +/*@}*/ /* end of group WHC_EXPORTED_FUNCTIONS */ + +/*@}*/ /* end of group WHC_Driver */ + +/*@}*/ /* end of group Standard_Driver */ + diff --git a/bsp/nuvoton/libraries/ma35/StdDriver/src/nu_wwdt.c b/bsp/nuvoton/libraries/ma35/StdDriver/src/nu_wwdt.c new file mode 100644 index 0000000000..aa0903b506 --- /dev/null +++ b/bsp/nuvoton/libraries/ma35/StdDriver/src/nu_wwdt.c @@ -0,0 +1,67 @@ +/**************************************************************************//** + * @file wwdt.c + * @brief WWDT driver source file + * + * SPDX-License-Identifier: Apache-2.0 + * @copyright (C) 2020 Nuvoton Technology Corp. All rights reserved. +*****************************************************************************/ +#include "NuMicro.h" + + +/** @addtogroup Standard_Driver Standard Driver + @{ +*/ + +/** @addtogroup WWDT_Driver WWDT Driver + @{ +*/ + +/** @addtogroup WWDT_EXPORTED_FUNCTIONS WWDT Exported Functions + @{ +*/ + +/** + * @brief Open WWDT and start counting + * + * @param[in] u32PreScale Pre-scale setting of WWDT counter. Valid values are: + * - \ref WWDT_PRESCALER_1 + * - \ref WWDT_PRESCALER_2 + * - \ref WWDT_PRESCALER_4 + * - \ref WWDT_PRESCALER_8 + * - \ref WWDT_PRESCALER_16 + * - \ref WWDT_PRESCALER_32 + * - \ref WWDT_PRESCALER_64 + * - \ref WWDT_PRESCALER_128 + * - \ref WWDT_PRESCALER_192 + * - \ref WWDT_PRESCALER_256 + * - \ref WWDT_PRESCALER_384 + * - \ref WWDT_PRESCALER_512 + * - \ref WWDT_PRESCALER_768 + * - \ref WWDT_PRESCALER_1024 + * - \ref WWDT_PRESCALER_1536 + * - \ref WWDT_PRESCALER_2048 + * @param[in] u32CmpValue Setting the window compared value. Valid values are between 0x0 to 0x3F. + * @param[in] u32EnableInt Enable WWDT time-out interrupt function. Valid values are TRUE and FALSE. + * + * @return None + * + * @details This function makes WWDT module start counting with different counter period by pre-scale setting and compared window value. + * @note This WWDT_CTL register can be write only one time after chip is powered on or reset. + */ +void WWDT_Open(uint32_t u32PreScale, + uint32_t u32CmpValue, + uint32_t u32EnableInt) +{ + WWDT2->CTL = u32PreScale | + (u32CmpValue << WWDT_CTL_CMPDAT_Pos) | + ((u32EnableInt == TRUE) ? WWDT_CTL_INTEN_Msk : 0U) | + WWDT_CTL_WWDTEN_Msk; + return; +} + +/*@}*/ /* end of group WWDT_EXPORTED_FUNCTIONS */ + +/*@}*/ /* end of group WWDT_Driver */ + +/*@}*/ /* end of group Standard_Driver */ + diff --git a/bsp/nuvoton/libraries/ma35/UsbHostLib/SConscript b/bsp/nuvoton/libraries/ma35/UsbHostLib/SConscript new file mode 100644 index 0000000000..e7e5dcfbb9 --- /dev/null +++ b/bsp/nuvoton/libraries/ma35/UsbHostLib/SConscript @@ -0,0 +1,12 @@ +# RT-Thread building script for component + +from building import * + +cwd = GetCurrentDir() +group = [] +if GetDepend('BSP_USING_USBH'): + src = Glob('*src/*.c') + Glob('src/*.cpp') + CPPPATH = [cwd + '/inc'] + group = DefineGroup('ma35d1_usbhostlib', src, depend = [''], CPPPATH = CPPPATH) + +Return('group') diff --git a/bsp/nuvoton/libraries/ma35/UsbHostLib/inc/config.h b/bsp/nuvoton/libraries/ma35/UsbHostLib/inc/config.h new file mode 100644 index 0000000000..892cbbb32b --- /dev/null +++ b/bsp/nuvoton/libraries/ma35/UsbHostLib/inc/config.h @@ -0,0 +1,142 @@ +/**************************************************************************//** + * @file config.h + * @version V1.00 + * @brief This header file defines the configuration of USB Host library. + * @note + * SPDX-License-Identifier: Apache-2.0 + * Copyright (C) 2018 Nuvoton Technology Corp. All rights reserved. + *****************************************************************************/ + +#ifndef _USBH_CONFIG_H_ +#define _USBH_CONFIG_H_ + + +/// @cond HIDDEN_SYMBOLS + +#include +#include "NuMicro.h" +#include "nu_sys.h" +#include "drv_sys.h" + + +/*----------------------------------------------------------------------------------------*/ +/* Hardware settings */ +/*----------------------------------------------------------------------------------------*/ +#define HCLK_MHZ 700 /* used for loop-delay. must be larger than + true HCLK clock MHz */ + +#define NON_CACHE_MASK (0xC0000000) + +static __inline void ENABLE_OHCI_IRQ(void) +{ + rt_hw_interrupt_umask(USBH0_IRQn); + rt_hw_interrupt_umask(USBH1_IRQn); +} +static __inline void DISABLE_OHCI_IRQ(void) +{ + rt_hw_interrupt_mask(USBH0_IRQn); + rt_hw_interrupt_mask(USBH1_IRQn); +} +static __inline void ENABLE_EHCI_IRQ(void) +{ + rt_hw_interrupt_umask(HSUSBH0_IRQn); + rt_hw_interrupt_umask(HSUSBH1_IRQn); +} +static __inline void DISABLE_EHCI_IRQ(void) +{ + rt_hw_interrupt_mask(HSUSBH0_IRQn); + rt_hw_interrupt_mask(HSUSBH1_IRQn); +} + + +#if defined(BSP_USING_HSUSBH0) + #define ENABLE_EHCI0 + #define ENABLE_OHCI0 +#endif + +#if defined(BSP_USING_HSUSBH1) + #define ENABLE_EHCI1 + #define ENABLE_OHCI1 +#endif + +#define EHCI_PORT_CNT 1 /* Number of EHCI roothub ports */ +#define OHCI_PORT_CNT 1 /* Number of OHCI roothub ports */ +#define OHCI_PER_PORT_POWER /* OHCI root hub per port powered */ + +#define OHCI_ISO_DELAY 4 /* preserved number frames while scheduling + OHCI isochronous transfer */ + +#define EHCI_ISO_DELAY 2 /* preserved number of frames while + scheduling EHCI isochronous transfer */ + +#define EHCI_ISO_RCLM_RANGE 32 /* When inspecting activated iTD/siTD, + unconditionally reclaim iTD/isTD scheduled + in just elapsed EHCI_ISO_RCLM_RANGE ms. */ + +#define MAX_DESC_BUFF_SIZE 4096 /* To hold the configuration descriptor, USB + core will allocate a buffer with this size + for each connected device. USB core does + not release it until device disconnected. */ + +/*----------------------------------------------------------------------------------------*/ +/* Memory allocation settings */ +/*----------------------------------------------------------------------------------------*/ + +#define STATIC_MEMORY_ALLOC 0 /* pre-allocate static memory blocks. No dynamic memory aloocation. + But the maximum number of connected devices and transfers are + limited. */ + +#define MAX_UDEV_DRIVER 8 /*!< Maximum number of registered drivers */ +#define MAX_ALT_PER_IFACE 8 /*!< maximum number of alternative interfaces per interface */ +#define MAX_EP_PER_IFACE 6 /*!< maximum number of endpoints per interface */ +#define MAX_HUB_DEVICE 8 /*!< Maximum number of hub devices */ + +/* Host controller hardware transfer descriptors memory pool. ED/TD/ITD of OHCI and QH/QTD of EHCI + are all allocated from this pool. Allocated unit size is determined by MEM_POOL_UNIT_SIZE. + May allocate one or more units depend on hardware descriptor type. */ + +#define MEM_POOL_UNIT_SIZE 64 /*!< A fixed hard coding setting. Do not change it! */ +#define MEM_POOL_UNIT_NUM 256 /*!< Increase this or heap size if memory allocate failed. */ + +/*----------------------------------------------------------------------------------------*/ +/* Re-defined staff for various compiler */ +/*----------------------------------------------------------------------------------------*/ +#ifdef __ICCARM__ + #define __inline inline +#endif + + +/*----------------------------------------------------------------------------------------*/ +/* Debug settings */ +/*----------------------------------------------------------------------------------------*/ +//#define ENABLE_ERROR_MSG /* enable debug messages */ +//#define ENABLE_DEBUG_MSG /* enable debug messages */ +//#define ENABLE_VERBOSE_DEBUG /* verbos debug messages */ +//#define DUMP_DESCRIPTOR /* dump descriptors */ + +#ifdef ENABLE_ERROR_MSG + #define USB_error rt_kprintf +#else + #define USB_error(...) +#endif + +#ifdef ENABLE_DEBUG_MSG + #define USB_debug rt_kprintf + #ifdef ENABLE_VERBOSE_DEBUG + #define USB_vdebug rt_kprintf + #else + #define USB_vdebug(...) + #endif +#else + #define USB_debug(...) + #define USB_vdebug(...) +#endif +#define ptr_to_u32(x) ((uint32_t)(x)) + + +/// @endcond HIDDEN_SYMBOLS + +#endif /* _USBH_CONFIG_H_ */ + +/*** (C) COPYRIGHT 2018 Nuvoton Technology Corp. ***/ + diff --git a/bsp/nuvoton/libraries/ma35/UsbHostLib/inc/ehci.h b/bsp/nuvoton/libraries/ma35/UsbHostLib/inc/ehci.h new file mode 100644 index 0000000000..a5dbe01a11 --- /dev/null +++ b/bsp/nuvoton/libraries/ma35/UsbHostLib/inc/ehci.h @@ -0,0 +1,277 @@ +/**************************************************************************//** + * @file ehci.h + * @version V1.00 + * @brief USB EHCI host controller driver header file. + * @note + * SPDX-License-Identifier: Apache-2.0 + * Copyright (C) 2017 Nuvoton Technology Corp. All rights reserved. + *****************************************************************************/ + +#ifndef _USBH_EHCI_H_ +#define _USBH_EHCI_H_ + +/// @cond HIDDEN_SYMBOLS + +struct utr_t; +struct udev_t; +struct qh_t; +struct iso_ep_t; +struct ep_info_t; + +/*----------------------------------------------------------------------------------------*/ +/* Periodic Frame List Size (256, 512, or 1024) */ +/*----------------------------------------------------------------------------------------*/ +#define FL_SIZE 1024 /* frame list size can be 256, 512, or 1024 */ +#define NUM_IQH 11 /* depends on FL_SIZE, 256:9, 512:10, 1024:11 */ + + +/*----------------------------------------------------------------------------------------*/ +/* Interrupt Threshold Control (1, 2, 4, 6, .. 64) */ +/*----------------------------------------------------------------------------------------*/ +#define UCMDR_INT_THR_CTRL (0x1< of QH */ +} qTD_T; + + +#define QTD_LIST_END 0x1 /* Indicate the terminate of qTD list. */ +#define QTD_PTR(x) ((qTD_T *)((uint32_t)(x) & ~0x1F)) + +/* + * Status: qTD Token[7:0] + */ +#define QTD_STS_PS_OUT (0<<0) /* directs the HC to issue an OUT PID */ +#define QTD_STS_PS_PING (1<<0) /* directs the HC to issue an PING PID */ +#define QTD_STS_SPLIT_STRAT (0<<1) /* directs the HC to issue an Start split */ +#define QTD_STS_SPLIT_COMPLETE (1<<1) /* directs the HC to issue an Complete split */ +#define QTD_STS_MISS_MF (1<<2) /* miss a required complete-split transaction */ +#define QTD_STS_XactErr (1<<3) /* Transaction Error occurred */ +#define QTD_STS_BABBLE (1<<4) /* Babble Detected */ +#define QTD_STS_DATA_BUFF_ERR (1<<5) /* Data Buffer Error */ +#define QTD_STS_HALT (1<<6) /* Halted */ +#define QTD_STS_ACTIVE (1<<7) /* Active */ + +/* + * PID: qTD Token[9:8] + */ +#define QTD_PID_Msk (0x3<<8) +#define QTD_PID_OUT (0<<8) /* generates token (E1H) */ +#define QTD_PID_IN (1<<8) /* generates token (69H) */ +#define QTD_PID_SETUP (2<<8) /* generates token (2DH) */ + +#define QTD_ERR_COUNTER (3<<10) /* Token[11:10] */ +#define QTD_IOC (1<<15) /* Token[15] - Interrupt On Complete */ +#define QTD_TODO_LEN_Pos 16 /* Token[31:16] - Total Bytes to Transfer */ +#define QTD_TODO_LEN(x) (((x)>>16) & 0x7FFF) +#define QTD_DT (1UL<<31) /* Token[31] - Data Toggle */ + +/*----------------------------------------------------------------------------------------*/ +/* Queue Head (QH) */ +/*----------------------------------------------------------------------------------------*/ +typedef struct qh_t +{ + /* OHCI spec. Endpoint descriptor */ + uint32_t HLink; /* Queue Head Horizontal Link Pointer */ + uint32_t Chrst; /* Endpoint Characteristics: QH DWord 1 */ + uint32_t Cap; /* Endpoint Capabilities: QH DWord 2 */ + uint32_t Curr_qTD; /* Current qTD Pointer */ + /* + * The followings are qTD Transfer Overlay + */ + uint32_t OL_Next_qTD; /* Next qTD Pointer */ + uint32_t OL_Alt_Next_qTD; /* Alternate Next qTD Pointer */ + uint32_t OL_Token; /* qTD Token */ + uint32_t OL_Bptr[5]; /* qTD Buffer Page Pointer List */ + /* + * The following members are used by USB Host libary. + */ + qTD_T *qtd_list; /* currently linked qTD transfers */ + qTD_T *done_list; /* currently linked qTD transfers */ + struct qh_t *next; /* point to the next QH in remove list */ +} QH_T; + +/* HLink[0] T field of "Queue Head Horizontal Link Pointer" */ +#define QH_HLNK_END 0x1 + +/* + * HLink[2:1] Typ field of "Queue Head Horizontal Link Pointer" + */ +#define QH_HLNK_ITD(x) (((uint32_t)(x) & ~0x1F) | 0x0) +#define QH_HLNK_QH(x) (((uint32_t)(x) & ~0x1F) | 0x2) +#define QH_HLNK_SITD(x) (((uint32_t)(x) & ~0x1F) | 0x4) +#define QH_HLNK_FSTN(x) (((uint32_t)(x) & ~0x1F) | 0x6) +#define QH_PTR(x) ((QH_T *)((uint32_t)(x) & ~0x1F)) + +/* + * Bit fields of "Endpoint Characteristics" + */ +#define QH_NAK_RL (4L<<28) /* Chrst[31:28] - NAK Count Reload */ +#define QH_CTRL_EP_FLAG (1<<27) /* Chrst[27] - Control Endpoint Flag */ +#define QH_RCLM_LIST_HEAD (1<<15) /* Chrst[15] - Head of Reclamation List Flag */ +#define QH_DTC (1<<14) /* Chrst[14] - Data Toggle Control */ +#define QH_EPS_FULL (0<<12) /* Chrst[13:12] - Endpoint Speed (Full) */ +#define QH_EPS_LOW (1<<12) /* Chrst[13:12] - Endpoint Speed (Low) */ +#define QH_EPS_HIGH (2<<12) /* Chrst[13:12] - Endpoint Speed (High) */ +#define QH_I_NEXT (1<<7) /* Chrst[7] - Inactivate on Next Transaction */ + +/* + * Bit fields of "Endpoint Capabilities" + */ +#define QH_MULT_Pos 30 /* Cap[31:30] - High-Bandwidth Pipe Multiplier */ +#define QH_HUB_PORT_Pos 23 /* Cap[29:23] - Hub Port Number */ +#define QH_HUB_ADDR_Pos 16 /* Cap[22:16] - Hub Addr */ +#define QH_C_MASK_Msk 0xFF00 /* Cap[15:8] - uFrame C-mask */ +#define QH_S_MASK_Msk 0x00FF /* Cap[7:0] - uFrame S-mask */ + + +/*----------------------------------------------------------------------------------------*/ +/* Isochronous (High-Speed) Transfer Descriptor (iTD) */ +/*----------------------------------------------------------------------------------------*/ +typedef struct itd_t +{ + uint32_t Next_Link; /* Next Link Pointer */ + uint32_t Transaction[8]; /* Transaction Status and Control */ + uint32_t Bptr[7]; /* Buffer Page Pointer List */ + /* + * The following members are used by USB Host libary. + */ + struct iso_ep_t *iso_ep; /* associated isochronous information block */ + struct utr_t *utr; /* associated UTR */ + uint32_t buff_base; /* buffer base address */ + uint8_t fidx; /* iTD's first index to UTR iso frames */ + uint8_t trans_mask; /* mask of activated transactions in iTD */ + uint32_t sched_frnidx; /* scheduled frame index */ + struct itd_t *next; /* used by software to maintain iTD list */ +} iTD_T; + +/* + * Next_Link[2:1] Typ field of "Next Schedule Element Pointer" Typ field + */ +#define ITD_HLNK_ITD(x) (((uint32_t)(x) & ~0x1F) | 0x0) +#define ITD_HLNK_QH(x) (((uint32_t)(x) & ~0x1F) | 0x2) +#define ITD_HLNK_SITD(x) (((uint32_t)(x) & ~0x1F) | 0x4) +#define ITD_HLNK_FSTN(x) (((uint32_t)(x) & ~0x1F) | 0x6) +#define ITD_PTR(x) ((iTD_T *)((uint32_t)(x) & ~0x1F)) + +/* + * Transaction[8] + */ +#define ITD_STATUS(x) (((x)>>28)&0xF) +#define ITD_STATUS_ACTIVE (0x80000000UL) /* Active */ +#define ITD_STATUS_BUFF_ERR (0x40000000UL) /* Data Buffer Error */ +#define ITD_STATUS_BABBLE (0x20000000UL) /* Babble Detected */ +#define ITD_STATUS_XACT_ERR (0x10000000UL) /* Transcation Error */ + +#define ITD_XLEN_Pos 16 +#define ITD_XFER_LEN(x) (((x)>>16)&0xFFF) +#define ITD_IOC (1<<15) +#define ITD_PG_Pos 12 +#define ITD_XFER_OFF_Msk 0xFFF + +/* + * Bptr[7] + */ +#define ITD_BUFF_PAGE_Pos 12 +/* Bptr[0] */ +#define ITD_EP_NUM_Pos 8 +#define ITD_EP_NUM(itd) (((itd)->Bptr[0]>>8)&0xF) +#define ITD_DEV_ADDR_Pos 0 +#define ITD_DEV_ADDR(itd) ((itd)->Bptr[0]&0x7F) +/* Bptr[1] */ +#define ITD_DIR_IN (1<<11) +#define ITD_DIR_OUT (0<<11) +#define ITD_MAX_PKTSZ_Pos 0 +#define ITD_MAX_PKTSZ(itd) ((itd)->Bptr[1]&0x7FF) + +/*----------------------------------------------------------------------------------------*/ +/* Split Isochronous (Full-Speed) Transfer Descriptor (siTD) */ +/*----------------------------------------------------------------------------------------*/ +typedef struct sitd_t +{ + uint32_t Next_Link; /* Next Link Pointer */ + uint32_t Chrst; /* Endpoint and Transaction Translator Characteristics */ + uint32_t Sched; /* Micro-frame Schedule Control */ + uint32_t StsCtrl; /* siTD Transfer Status and Control */ + uint32_t Bptr[2]; /* Buffer Page Pointer List */ + uint32_t BackLink; /* siTD Back Link Pointer */ + /* + * The following members are used by USB Host libary. + */ + struct iso_ep_t *iso_ep; /* associated isochronous information block */ + struct utr_t *utr; /* associated UTR */ + uint8_t fidx; /* iTD's first index to UTR iso frames */ + uint32_t sched_frnidx; /* scheduled frame index */ + struct sitd_t *next; /* used by software to maintain siTD list */ +} siTD_T; + +#define SITD_LIST_END 0x1 /* Indicate the terminate of siTD list. */ + +#define SITD_XFER_IO_Msk (1UL<<31) +#define SITD_XFER_IN (1UL<<31) +#define SITD_XFER_OUT (0UL<<31) + +#define SITD_PORT_NUM_Pos 24 +#define SITD_HUB_ADDR_Pos 16 +#define SITD_EP_NUM_Pos 8 +#define SITD_DEV_ADDR_Pos 0 + +#define SITD_IOC (1UL<<31) +#define SITD_XFER_CNT_Pos 16 +#define SITD_XFER_CNT_Msk (0x3FF<>28) & 0x0F) +#define TD_CC_SET(td, cc) (td) = ((td) & 0x0FFFFFFF) | (((cc) & 0x0F) << 28) +#define TD_T_DATA0 0x02000000 +#define TD_T_DATA1 0x03000000 +#define TD_R 0x00040000 +#define TD_DP 0x00180000 +#define TD_DP_IN 0x00100000 +#define TD_DP_OUT 0x00080000 +#define MAXPSW 8 +/* steel TD reserved bits to keep driver data */ +#define TD_TYPE_Msk (0x3<<16) +#define TD_TYPE_CTRL (0x0<<16) +#define TD_TYPE_BULK (0x1<<16) +#define TD_TYPE_INT (0x2<<16) +#define TD_TYPE_ISO (0x3<<16) +#define TD_CTRL_Msk (0x7<<15) +#define TD_CTRL_DATA (1<<15) + + +/* + * The HCCA (Host Controller Communications Area) is a 256 byte + * structure defined in the OHCI spec. that the host controller is + * told the base address of. It must be 256-byte aligned. + */ +typedef struct +{ + uint32_t int_table[32]; /* Interrupt ED table */ + uint16_t frame_no; /* current frame number */ + uint16_t pad1; /* set to 0 on each frame_no change */ + uint32_t done_head; /* info returned for an interrupt */ + uint8_t reserved_for_hc[116]; +} HCCA_T; + + +/// @endcond + +#endif /* _USBH_OHCI_H_ */ diff --git a/bsp/nuvoton/libraries/ma35/UsbHostLib/inc/usb.h b/bsp/nuvoton/libraries/ma35/UsbHostLib/inc/usb.h new file mode 100644 index 0000000000..ce223e6c6f --- /dev/null +++ b/bsp/nuvoton/libraries/ma35/UsbHostLib/inc/usb.h @@ -0,0 +1,386 @@ +/**************************************************************************//** + * @file usb.h + * @version V1.00 + * @brief USB Host library header file. + * @note + * SPDX-License-Identifier: Apache-2.0 + * Copyright (C) 2017 Nuvoton Technology Corp. All rights reserved. + *****************************************************************************/ + +#ifndef _USBH_H_ +#define _USBH_H_ + +#include "config.h" +#include "usbh_lib.h" +#include "ehci.h" +#include "ohci.h" + +/// @cond HIDDEN_SYMBOLS + +struct utr_t; +struct udev_t; +struct hub_dev_t; +struct iface_t; +struct ep_info_t; + +/*----------------------------------------------------------------------------------*/ +/* USB device request setup packet */ +/*----------------------------------------------------------------------------------*/ +typedef struct __attribute__((__packed__)) +{ + uint8_t bmRequestType; + uint8_t bRequest; + uint16_t wValue; + uint16_t wIndex; + uint16_t wLength; +} +DEV_REQ_T; + +/* + * bmRequestType[7] - Data transfer direction + */ +#define REQ_TYPE_OUT 0x00 +#define REQ_TYPE_IN 0x80 +/* + * bmRequestType[6:5] - Type + */ +#define REQ_TYPE_STD_DEV 0x00 +#define REQ_TYPE_CLASS_DEV 0x20 +#define REQ_TYPE_VENDOR_DEV 0x40 +/* + * bmRequestType[4:0] - Recipient + */ +#define REQ_TYPE_TO_DEV 0x00 +#define REQ_TYPE_TO_IFACE 0x01 +#define REQ_TYPE_TO_EP 0x02 +#define REQ_TYPE_TO_OTHER 0x03 +/* + * Standard Requests + */ +#define USB_REQ_GET_STATUS 0x00 +#define USB_REQ_CLEAR_FEATURE 0x01 +#define USB_REQ_SET_FEATURE 0x03 +#define USB_REQ_SET_ADDRESS 0x05 +#define USB_REQ_GET_DESCRIPTOR 0x06 +#define USB_REQ_SET_CONFIGURATION 0x09 +#define USB_REQ_SET_INTERFACE 0x0B +/* + * Descriptor Types + */ +#define USB_DT_STANDARD 0x00 +#define USB_DT_CLASS 0x20 +#define USB_DT_VENDOR 0x40 + +#define USB_DT_DEVICE 0x01 +#define USB_DT_CONFIGURATION 0x02 +#define USB_DT_STRING 0x03 +#define USB_DT_INTERFACE 0x04 +#define USB_DT_ENDPOINT 0x05 +#define USB_DT_DEVICE_QUALIFIER 0x06 +#define USB_DT_OTHER_SPEED_CONF 0x07 +#define USB_DT_IFACE_POWER 0x08 + + + +/*----------------------------------------------------------------------------------*/ +/* USB standard descriptors */ +/*----------------------------------------------------------------------------------*/ + +/* Descriptor header */ +typedef struct __attribute__((__packed__)) +{ + uint8_t bLength; + uint8_t bDescriptorType; +} +DESC_HDR_T; + +/*----------------------------------------------------------------------------------*/ +/* USB device descriptor */ +/*----------------------------------------------------------------------------------*/ +typedef struct __attribute__((__packed__)) /*!< device descriptor structure */ +{ + uint8_t bLength; /*!< Length of device descriptor */ + uint8_t bDescriptorType; /*!< Device descriptor type */ + uint16_t bcdUSB; /*!< USB version number */ + uint8_t bDeviceClass; /*!< Device class code */ + uint8_t bDeviceSubClass; /*!< Device subclass code */ + uint8_t bDeviceProtocol; /*!< Device protocol code */ + uint8_t bMaxPacketSize0; /*!< Maximum packet size of control endpoint*/ + uint16_t idVendor; /*!< Vendor ID */ + uint16_t idProduct; /*!< Product ID */ + uint16_t bcdDevice; /*!< Device ID */ + uint8_t iManufacturer; /*!< Manufacture description string ID */ + uint8_t iProduct; /*!< Product description string ID */ + uint8_t iSerialNumber; /*!< Serial number description string ID */ + uint8_t bNumConfigurations; /*!< Total number of configurations */ +} +DESC_DEV_T; /*!< device descriptor structure */ + +/* + * Configuration Descriptor + */ +typedef struct __attribute__((__packed__)) usb_config_descriptor /*!< Configuration descriptor structure */ +{ + uint8_t bLength; /*!< Length of configuration descriptor */ + uint8_t bDescriptorType; /*!< Descriptor type */ + uint16_t wTotalLength; /*!< Total length of this configuration */ + uint8_t bNumInterfaces; /*!< Total number of interfaces */ + uint8_t bConfigurationValue; /*!< Configuration descriptor number */ + uint8_t iConfiguration; /*!< String descriptor ID */ + uint8_t bmAttributes; /*!< Configuration characteristics */ + uint8_t MaxPower; /*!< Maximum power consumption */ +} DESC_CONF_T; /*!< Configuration descriptor structure */ + +/* + * Interface Descriptor + */ +typedef struct __attribute__((__packed__))usb_interface_descriptor /*!< Interface descriptor structure */ +{ + uint8_t bLength; /*!< Length of interface descriptor */ + uint8_t bDescriptorType; /*!< Descriptor type */ + uint8_t bInterfaceNumber; /*!< Interface number */ + uint8_t bAlternateSetting; /*!< Alternate setting number */ + uint8_t bNumEndpoints; /*!< Number of endpoints */ + uint8_t bInterfaceClass; /*!< Interface class code */ + uint8_t bInterfaceSubClass; /*!< Interface subclass code */ + uint8_t bInterfaceProtocol; /*!< Interface protocol code */ + uint8_t iInterface; /*!< Interface ID */ +} DESC_IF_T; /*!< Interface descriptor structure */ + +/* + * Endpoint Descriptor + */ +typedef struct __attribute__((__packed__)) usb_endpoint_descriptor /*!< Endpoint descriptor structure */ +{ + uint8_t bLength; /*!< Length of endpoint descriptor */ + uint8_t bDescriptorType; /*!< Descriptor type */ + uint8_t bEndpointAddress; /*!< Endpoint address */ + uint8_t bmAttributes; /*!< Endpoint attribute */ + uint16_t wMaxPacketSize; /*!< Maximum packet size */ + uint8_t bInterval; /*!< Synchronous transfer interval */ + uint8_t bRefresh; /*!< Refresh */ + uint8_t bSynchAddress; /*!< Sync address */ +} DESC_EP_T; /*!< Endpoint descriptor structure */ + +/* + * Endpoint descriptor bEndpointAddress[7] - direction + */ +#define EP_ADDR_DIR_MASK 0x80 +#define EP_ADDR_DIR_IN 0x80 +#define EP_ADDR_DIR_OUT 0x00 + +/* + * Endpoint descriptor bmAttributes[1:0] - transfer type + */ +#define EP_ATTR_TT_MASK 0x03 +#define EP_ATTR_TT_CTRL 0x00 +#define EP_ATTR_TT_ISO 0x01 +#define EP_ATTR_TT_BULK 0x02 +#define EP_ATTR_TT_INT 0x03 + + +/*----------------------------------------------------------------------------------*/ +/* USB Host controller driver */ +/*----------------------------------------------------------------------------------*/ +typedef struct +{ + int (*init)(void); + void (*shutdown)(void); + void (*suspend)(void); + void (*resume)(void); + int (*ctrl_xfer)(struct utr_t *utr); + int (*bulk_xfer)(struct utr_t *utr); + int (*int_xfer)(struct utr_t *utr); + int (*iso_xfer)(struct utr_t *utr); + int (*quit_xfer)(struct utr_t *utr, struct ep_info_t *ep); + + /* root hub support */ + int (*rthub_port_reset)(int port); + int (*rthub_polling)(void); + void *hc_data; +} HC_DRV_T; + + +/*----------------------------------------------------------------------------------*/ +/* USB device driver */ +/*----------------------------------------------------------------------------------*/ +typedef struct +{ + int (*probe)(struct iface_t *iface); + void (*disconnect)(struct iface_t *iface); + void (*suspend)(struct iface_t *iface); + void (*resume)(struct iface_t *iface); +} UDEV_DRV_T; + + +/*----------------------------------------------------------------------------------*/ +/* USB device */ +/*----------------------------------------------------------------------------------*/ + +typedef enum +{ + SPEED_LOW, + SPEED_FULL, + SPEED_HIGH +} SPEED_E; + +typedef struct ep_info_t +{ + uint8_t bEndpointAddress; + uint8_t bmAttributes; + uint8_t bInterval; + uint8_t bToggle; + uint16_t wMaxPacketSize; + void *hw_pipe; /*!< point to the HC assocaied endpoint \hideinitializer */ +} EP_INFO_T; + +typedef struct udev_t +{ + DESC_DEV_T descriptor; /*!< Device descriptor. \hideinitializer */ + struct hub_dev_t *parent; /*!< parent hub device \hideinitializer */ + uint8_t port_num; /*!< The hub port this device connected on \hideinitializer */ + uint8_t dev_num; /*!< device number \hideinitializer */ + int8_t cur_conf; /*!< Currentll selected configuration \hideinitializer */ + SPEED_E speed; /*!< device speed (low/full/high) \hideinitializer */ + /* + * The followings are lightweight USB stack internal used . + */ + uint8_t *cfd_buff; /*!< Configuration descriptor buffer. \hideinitializer */ + EP_INFO_T ep0; /*!< Endpoint 0 \hideinitializer */ + HC_DRV_T *hc_driver; /*!< host controller driver \hideinitializer */ + struct iface_t *iface_list; /*!< Working interface list \hideinitializer */ + struct udev_t *next; /*!< link for global usb device list \hideinitializer */ +} UDEV_T; + +typedef struct alt_iface_t +{ + DESC_IF_T *ifd; /*!< point to the location of this alternative interface descriptor in UDEV_T->cfd_buff */ + EP_INFO_T ep[MAX_EP_PER_IFACE]; /*!< endpoints of this alternative interface */ +} ALT_IFACE_T; + +typedef struct iface_t +{ + UDEV_T *udev; /*!< USB device \hideinitializer */ + uint8_t if_num; /*!< Interface number \hideinitializer */ + uint8_t num_alt; /*!< Number of alternative interface \hideinitializer */ + ALT_IFACE_T *aif; /*!< Point to the active alternative interface */ + ALT_IFACE_T alt[MAX_ALT_PER_IFACE]; /*!< List of alternative interface \hideinitializer */ + UDEV_DRV_T *driver; /*!< Interface associated driver \hideinitializer */ + void *context; /*!< Reference to device context \hideinitializer */ + struct iface_t *next; /*!< Point to next interface of the same device. Started from UDEV_T->iface_list \hideinitializer */ +} IFACE_T; + + +/*----------------------------------------------------------------------------------*/ +/* URB (USB Request Block) */ +/*----------------------------------------------------------------------------------*/ + +#define IF_PER_UTR 8 /* number of frames per UTR isochronous transfer (DO NOT modify it!) */ + +typedef void (*FUNC_UTR_T)(struct utr_t *); + +typedef struct utr_t +{ + UDEV_T *udev; /*!< point to associated USB device \hideinitializer */ + DEV_REQ_T setup; /*!< buffer for setup packet \hideinitializer */ + EP_INFO_T *ep; /*!< associated endpoint \hideinitializer */ + uint8_t *buff; /*!< transfer buffer \hideinitializer */ + uint8_t bIsTransferDone; /*!< tansfer done? \hideinitializer */ + uint32_t data_len; /*!< length of data to be transferred \hideinitializer */ + uint32_t xfer_len; /*!< length of transferred data \hideinitializer */ + uint8_t bIsoNewSched; /*!< New schedule isochronous transfer \hideinitializer */ + uint16_t iso_sf; /*!< Isochronous start frame number \hideinitializer */ + uint16_t iso_xlen[IF_PER_UTR]; /*!< transfer length of isochronous frames \hideinitializer */ + uint8_t *iso_buff[IF_PER_UTR]; /*!< transfer buffer address of isochronous frames \hideinitializer */ + int iso_status[IF_PER_UTR]; /*!< transfer status of isochronous frames \hideinitializer */ + int td_cnt; /*!< number of transfer descriptors \hideinitializer */ + int status; /*!< return status \hideinitializer */ + int interval; /*!< interrupt/isochronous interval \hideinitializer */ + void *context; /*!< point to deivce proprietary data area \hideinitializer */ + FUNC_UTR_T func; /*!< tansfer done call-back function \hideinitializer */ + struct utr_t *next; /* point to the next UTR of the same endpoint. \hideinitializer */ +} UTR_T; + + +/*----------------------------------------------------------------------------------*/ +/* Global variables */ +/*----------------------------------------------------------------------------------*/ +extern USBH_T *_ohci0, *_ohci1, *_ohci2; +extern HSUSBH_T *_ehci0, *_ehci1; + +extern HC_DRV_T ohci0_driver, ohci1_driver, ohci2_driver; +extern HC_DRV_T ehci0_driver, ehci1_driver; + +extern UDEV_T *g_udev_list; + +/*----------------------------------------------------------------------------------*/ +/* USB stack exported functions */ +/*----------------------------------------------------------------------------------*/ +extern void usbh_delay_ms(int msec); + +extern void usbh_dump_buff_bytes(uint8_t *buff, int nSize); +extern void usbh_dump_interface_descriptor(DESC_IF_T *if_desc); +extern void usbh_dump_endpoint_descriptor(DESC_EP_T *ep_desc); +extern void usbh_dump_iface(IFACE_T *iface); +extern void usbh_dump_ep_info(EP_INFO_T *ep); + +/* + * Memory management functions + */ +extern void USB_InitializeMemoryPool(void); +extern void *USB_malloc(int wanted_size, int boundary); +extern void USB_free(void *); +extern int USB_available_memory(void); +extern int USB_allocated_memory(void); +extern void usbh_memory_init(void); +extern uint32_t usbh_memory_used(void); +extern void *usbh_alloc_mem(int size); +extern void usbh_free_mem(void *p, int size); +extern int alloc_dev_address(void); +extern void free_dev_address(int dev_addr); +extern UDEV_T *alloc_device(void); +extern void free_device(UDEV_T *udev); +extern UTR_T *alloc_utr(UDEV_T *udev); +extern void free_utr(UTR_T *utr); +extern ED_T *alloc_ohci_ED(void); +extern void free_ohci_ED(ED_T *ed); +extern TD_T *alloc_ohci_TD(UTR_T *utr); +extern void free_ohci_TD(TD_T *td); +extern QH_T *alloc_ehci_QH(void); +extern void free_ehci_QH(QH_T *qh); +extern qTD_T *alloc_ehci_qTD(UTR_T *utr); +extern void free_ehci_qTD(qTD_T *qtd); +extern iTD_T *alloc_ehci_iTD(void); +extern void free_ehci_iTD(iTD_T *itd); +extern siTD_T *alloc_ehci_siTD(void); +extern void free_ehci_siTD(siTD_T *sitd); + + +extern void usbh_hub_init(void); +extern int usbh_connect_device(UDEV_T *); +extern void usbh_disconnect_device(UDEV_T *); +extern int usbh_register_driver(UDEV_DRV_T *driver); +extern EP_INFO_T *usbh_iface_find_ep(IFACE_T *iface, uint8_t ep_addr, uint8_t dir_type); +extern int usbh_reset_device(UDEV_T *); +extern int usbh_reset_port(UDEV_T *); + +/* + * USB Standard Request functions + */ +extern int usbh_get_device_descriptor(UDEV_T *udev, DESC_DEV_T *desc_buff); +extern int usbh_get_config_descriptor(UDEV_T *udev, uint8_t *desc_buff, int buff_len); +extern int usbh_set_configuration(UDEV_T *udev, uint8_t conf_val); +extern int usbh_set_interface(IFACE_T *iface, uint16_t alt_setting); +extern int usbh_clear_halt(UDEV_T *udev, uint16_t ep_addr); + +extern int usbh_ctrl_xfer(UDEV_T *udev, uint8_t bmRequestType, uint8_t bRequest, uint16_t wValue, uint16_t wIndex, uint16_t wLength, uint8_t *buff, uint32_t *xfer_len, uint32_t timeout); +extern int usbh_bulk_xfer(UTR_T *utr); +extern int usbh_int_xfer(UTR_T *utr); +extern int usbh_iso_xfer(UTR_T *utr); +extern int usbh_quit_utr(UTR_T *utr); +extern int usbh_quit_xfer(UDEV_T *udev, EP_INFO_T *ep); + + +/// @endcond HIDDEN_SYMBOLS + +#endif /* _USBH_H_ */ diff --git a/bsp/nuvoton/libraries/ma35/UsbHostLib/inc/usbh_lib.h b/bsp/nuvoton/libraries/ma35/UsbHostLib/inc/usbh_lib.h new file mode 100644 index 0000000000..90eb8c3de3 --- /dev/null +++ b/bsp/nuvoton/libraries/ma35/UsbHostLib/inc/usbh_lib.h @@ -0,0 +1,189 @@ +/**************************************************************************//** + * @file usbh_lib.h + * @version V1.10 + * @brief USB Host library exported header file. + * + * @note + * SPDX-License-Identifier: Apache-2.0 + * Copyright (C) 2017 Nuvoton Technology Corp. All rights reserved. + ******************************************************************************/ +#ifndef _USBH_LIB_H_ +#define _USBH_LIB_H_ + +#include "NuMicro.h" + +#include "usb.h" + + +#ifdef __cplusplus +extern "C" +{ +#endif + +/** @addtogroup LIBRARY Library + @{ +*/ + +/** @addtogroup USBH_Library USB Host Library + @{ +*/ + +/** @addtogroup USBH_EXPORTED_CONSTANTS USB Host Exported Constants + @{ +*/ + +#define USBH_OK 0 /*!< No error. */ +#define USBH_ERR_MEMORY_OUT -10 /*!< Out of memory. */ +#define USBH_ERR_IF_ALT_LIMIT -11 /*!< Number of alternative interface > MAX_ALT_PER_IFACE */ +#define USBH_ERR_IF_EP_LIMIT -15 /*!< Number of endpoints > MAX_EP_PER_IFACE */ +#define USBH_ERR_NOT_SUPPORTED -101 /*!< Device/Class/Transfer not supported */ +#define USBH_ERR_NOT_MATCHED -103 /*!< Not macthed */ +#define USBH_ERR_NOT_EXPECTED -104 /*!< Unknown or unexpected */ +#define USBH_ERR_INVALID_PARAM -105 /*!< Invalid parameter */ +#define USBH_ERR_NOT_FOUND -106 /*!< Device or interface not found */ +#define USBH_ERR_EP_NOT_FOUND -107 /*!< Endpoint not found */ +#define USBH_ERR_DESCRIPTOR -137 /*!< Failed to parse USB descriptors */ +#define USBH_ERR_SET_DEV_ADDR -139 /*!< Failed to set device address */ +#define USBH_ERR_SET_CONFIG -151 /*!< Failed to set device configuration */ + +#define USBH_ERR_TRANSFER -201 /*!< USB transfer error */ +#define USBH_ERR_TIMEOUT -203 /*!< USB transfer time-out */ +#define USBH_ERR_ABORT -205 /*!< USB transfer aborted due to disconnect or reset */ +#define USBH_ERR_PORT_RESET -255 /*!< Hub port reset failed */ +#define USBH_ERR_SCH_OVERRUN -257 /*!< USB isochronous schedule overrun */ +#define USBH_ERR_DISCONNECTED -259 /*!< USB device was disconnected */ + +#define USBH_ERR_TRANSACTION -271 /*!< USB transaction timeout, CRC, Bad PID, etc. */ +#define USBH_ERR_BABBLE_DETECTED -272 /*!< A 'babble' is detected during the transaction */ +#define USBH_ERR_DATA_BUFF -274 /*!< Data buffer overrun or underrun */ + +#define USBH_ERR_CC_NO_ERR -280 /*!< OHCI CC code - no error */ +#define USBH_ERR_CRC -281 /*!< USB trasfer CRC error */ +#define USBH_ERR_BIT_STUFF -282 /*!< USB transfer bit stuffing error */ +#define USBH_ERR_DATA_TOGGLE -283 /*!< USB trasfer data toggle error */ +#define USBH_ERR_STALL -284 /*!< USB trasfer STALL error */ +#define USBH_ERR_DEV_NO_RESP -285 /*!< USB trasfer device no response error */ +#define USBH_ERR_PID_CHECK -286 /*!< USB trasfer PID check failure */ +#define USBH_ERR_UNEXPECT_PID -287 /*!< USB trasfer unexpected PID error */ +#define USBH_ERR_DATA_OVERRUN -288 /*!< USB trasfer data overrun error */ +#define USBH_ERR_DATA_UNDERRUN -289 /*!< USB trasfer data underrun error */ +#define USBH_ERR_BUFF_OVERRUN -292 /*!< USB trasfer buffer overrun error */ +#define USBH_ERR_BUFF_UNDERRUN -293 /*!< USB trasfer buffer underrun error */ +#define USBH_ERR_NOT_ACCESS0 -294 /*!< USB trasfer not accessed error */ +#define USBH_ERR_NOT_ACCESS1 -295 /*!< USB trasfer not accessed error */ + +#define USBH_ERR_OHCI_INIT -301 /*!< Failed to initialize OHIC controller. */ +#define USBH_ERR_OHCI_EP_BUSY -303 /*!< The endpoint is under transfer. */ + +#define USBH_ERR_EHCI_INIT -501 /*!< Failed to initialize EHCI controller. */ +#define USBH_ERR_EHCI_QH_BUSY -503 /*!< the Queue Head is busy. */ + +#define UMAS_OK 0 /*!< No error. */ +#define UMAS_ERR_NO_DEVICE -1031 /*!< No Mass Stroage Device found. */ +#define UMAS_ERR_IO -1033 /*!< Device read/write failed. */ +#define UMAS_ERR_INIT_DEVICE -1035 /*!< failed to init MSC device */ +#define UMAS_ERR_CMD_STATUS -1037 /*!< SCSI command status failed */ +#define UMAS_ERR_IVALID_PARM -1038 /*!< Invalid parameter. */ +#define UMAS_ERR_DRIVE_NOT_FOUND -1039 /*!< drive not found */ + +#define HID_RET_OK 0 /*!< Return with no errors. */ +#define HID_RET_DEV_NOT_FOUND -1081 /*!< HID device not found or removed. */ +#define HID_RET_IO_ERR -1082 /*!< USB transfer failed. */ +#define HID_RET_INVALID_PARAMETER -1083 /*!< Invalid parameter. */ +#define HID_RET_OUT_OF_MEMORY -1084 /*!< Out of memory. */ +#define HID_RET_NOT_SUPPORTED -1085 /*!< Function not supported. */ +#define HID_RET_EP_NOT_FOUND -1086 /*!< Endpoint not found. */ +#define HID_RET_PARSING -1087 /*!< Failed to parse HID descriptor */ +#define HID_RET_XFER_IS_RUNNING -1089 /*!< The transfer has been enabled. */ +#define HID_RET_REPORT_NOT_FOUND -1090 /*!< The transfer has been enabled. */ + +#define UAC_RET_OK 0 /*!< Return with no errors. */ +#define UAC_RET_DEV_NOT_FOUND -2001 /*!< Audio Class device not found or removed. */ +#define UAC_RET_FUNC_NOT_FOUND -2002 /*!< Audio device has no this function. */ +#define UAC_RET_IO_ERR -2003 /*!< USB transfer failed. */ +#define UAC_RET_DATA_LEN -2004 /*!< Unexpected transfer length */ +#define UAC_RET_INVALID -2005 /*!< Invalid parameter or usage. */ +#define UAC_RET_OUT_OF_MEMORY -2007 /*!< Out of memory. */ +#define UAC_RET_DRV_NOT_SUPPORTED -2009 /*!< Function not supported by this UAC driver. */ +#define UAC_RET_DEV_NOT_SUPPORTED -2011 /*!< Function not supported by the UAC device. */ +#define UAC_RET_PARSER -2013 /*!< Failed to parse UAC descriptor */ +#define UAC_RET_IS_STREAMING -2015 /*!< Audio pipe is on streaming. */ + + +/*@}*/ /* end of group USBH_EXPORTED_CONSTANTS */ + + +/** @addtogroup USBH_EXPORTED_TYPEDEF USB Host Typedef + @{ +*/ +struct udev_t; +typedef void (CONN_FUNC)(struct udev_t *udev, int param); + +struct line_coding_t; +struct cdc_dev_t; +typedef void (CDC_CB_FUNC)(struct cdc_dev_t *cdev, uint8_t *rdata, int data_len); + +struct usbhid_dev; +typedef void (HID_IR_FUNC)(struct usbhid_dev *hdev, uint16_t ep_addr, int status, uint8_t *rdata, uint32_t data_len); /*!< interrupt in callback function \hideinitializer */ +typedef void (HID_IW_FUNC)(struct usbhid_dev *hdev, uint16_t ep_addr, int status, uint8_t *wbuff, uint32_t *data_len); /*!< interrupt out callback function \hideinitializer */ + +struct uac_dev_t; +typedef int (UAC_CB_FUNC)(struct uac_dev_t *dev, uint8_t *data, int len); /*!< audio in callback function \hideinitializer */ + +/*@}*/ /* end of group USBH_EXPORTED_STRUCT */ + + + +/** @addtogroup USBH_EXPORTED_FUNCTIONS USB Host Exported Functions + @{ +*/ + +/*------------------------------------------------------------------*/ +/* */ +/* USB Core Library APIs */ +/* */ +/*------------------------------------------------------------------*/ +extern void usbh_core_init(void); +extern int usbh_polling_root_hubs(void); +extern void usbh_install_conn_callback(CONN_FUNC *conn_func, CONN_FUNC *disconn_func); +extern void usbh_suspend(void); +extern void usbh_resume(void); +extern struct udev_t *usbh_find_device(char *hub_id, int port); + +/** + * @brief A function return current tick count. + * @return Current tick. + * @details User application must provide this function to return current tick. + * The tick should increase by 1 for every 10 ms. + */ +extern uint32_t usbh_get_ticks(void); /* This function must be provided by user application. */ +extern uint32_t usbh_tick_from_millisecond(uint32_t msec); /* This function must be provided by user application. */ + + +/// @cond HIDDEN_SYMBOLS + +//extern void dump_ohci_regs(void); +//extern void dump_ehci_regs(void); +//extern void dump_ohci_ports(void); +//extern void dump_ehci_ports(void); +//extern uint32_t usbh_memory_used(void); + +/// @endcond HIDDEN_SYMBOLS + + +/*@}*/ /* end of group USBH_EXPORTED_FUNCTIONS */ + +/*@}*/ /* end of group USBH_Library */ + +/*@}*/ /* end of group LIBRARY */ + +#ifdef __cplusplus +} +#endif + +#endif /* _USBH_LIB_H_ */ + +/*** (C) COPYRIGHT 2017 Nuvoton Technology Corp. ***/ + + + diff --git a/bsp/nuvoton/libraries/ma35/UsbHostLib/src/_ehci.c_ b/bsp/nuvoton/libraries/ma35/UsbHostLib/src/_ehci.c_ new file mode 100644 index 0000000000..958844b806 --- /dev/null +++ b/bsp/nuvoton/libraries/ma35/UsbHostLib/src/_ehci.c_ @@ -0,0 +1,1264 @@ +/**************************************************************************//** + * @file ehci.c + * @version V1.10 + * @brief USB Host library EHCI (USB 2.0) host controller driver. + * + * @note + * SPDX-License-Identifier: Apache-2.0 + * Copyright (C) 2017 Nuvoton Technology Corp. All rights reserved. +*****************************************************************************/ + + +/// @cond HIDDEN_SYMBOLS + +static QH_T *_H_qh; /* head of reclamation list */ +static qTD_T *_ghost_qtd; /* used as a terminator qTD */ +static QH_T *qh_remove_list; + +static uint32_t _PFList_mem[FL_SIZE] __attribute__((aligned(4096))); /* Periodic frame list */ + +static uint32_t *_PFList; + +static QH_T *_Iqh[NUM_IQH]; + +static int ehci_quit_iso_xfer(UTR_T *utr, EP_INFO_T *ep); +static void scan_isochronous_list(void); + + +#ifdef ENABLE_ERROR_MSG +static void dump_ehci_regs(void) +{ + USB_debug("Dump HSUSBH(0x%x) registers:\n", ptr_to_u32(&_ehci->EHCVNR)); + USB_debug(" EHCVNR = 0x%x\n", _ehci->EHCVNR); + USB_debug(" EHCSPR = 0x%x\n", _ehci->EHCSPR); + USB_debug(" EHCCPR = 0x%x\n", _ehci->EHCCPR); + USB_debug(" UCMDR = 0x%x\n", _ehci->UCMDR); + USB_debug(" USTSR = 0x%x\n", _ehci->USTSR); + USB_debug(" UIENR = 0x%x\n", _ehci->UIENR); + USB_debug(" UFINDR = 0x%x\n", _ehci->UFINDR); + USB_debug(" UPFLBAR = 0x%x\n", _ehci->UPFLBAR); + USB_debug(" UCALAR = 0x%x\n", _ehci->UCALAR); + USB_debug(" UCFGR = 0x%x\n", _ehci->UCFGR); + USB_debug(" UPSCR0 = 0x%x\n", _ehci->UPSCR); +// USB_debug(" PHYCTL0 = 0x%x\n", _ehci->USBPCR0); +// USB_debug(" PHYCTL1 = 0x%x\n", _ehci->USBPCR1); +} + +static void dump_ehci_ports() +{ + USB_debug("_ehci port0=0x%x\n", _ehci->UPSCR); +} + +static void dump_ehci_qtd(qTD_T *qtd) +{ + USB_debug(" [qTD] - 0x%08x\n", (int)qtd); + USB_debug(" 0x%08x (Next qtd Pointer)\n", qtd->Next_qTD); + USB_debug(" 0x%08x (Alternate Next qtd Pointer)\n", qtd->Alt_Next_qTD); + USB_debug(" 0x%08x (qtd Token) PID: %s, Bytes: %d, IOC: %d\n", qtd->Token, (((qtd->Token >> 8) & 0x3) == 0) ? "OUT" : ((((qtd->Token >> 8) & 0x3) == 1) ? "IN" : "SETUP"), (qtd->Token >> 16) & 0x7FFF, (qtd->Token >> 15) & 0x1); + USB_debug(" 0x%08x (Buffer Pointer (page 0))\n", qtd->Bptr[0]); + //USB_debug(" 0x%08x (Buffer Pointer (page 1))\n", qtd->Bptr[1]); + //USB_debug(" 0x%08x (Buffer Pointer (page 2))\n", qtd->Bptr[2]); + //USB_debug(" 0x%08x (Buffer Pointer (page 3))\n", qtd->Bptr[3]); + //USB_debug(" 0x%08x (Buffer Pointer (page 4))\n", qtd->Bptr[4]); + USB_debug("\n"); +} + +static void dump_ehci_asynclist(void) +{ + QH_T *qh = _H_qh; + qTD_T *qtd; + + USB_debug(">>> Dump EHCI Asynchronous List <<<\n"); + do + { + USB_debug("[QH] - 0x%08x\n", (int)qh); + USB_debug(" 0x%08x (Queue Head Horizontal Link Pointer, Queue Head DWord 0)\n", qh->HLink); + USB_debug(" 0x%08x (Endpoint Characteristics) DevAddr: %d, EP: 0x%x, PktSz: %d, Speed: %s\n", qh->Chrst, (qh->Chrst & 0x7F), ((qh->Chrst >> 8) & 0xF), ((qh->Chrst >> 16) & 0x7FF), ((qh->Chrst >> 12) & 0x3 == 0) ? "Full" : (((qh->Chrst >> 12) & 0x3 == 1) ? "Low" : "High")); + USB_debug(" 0x%08x (Endpoint Capabilities: Queue Head DWord 2)\n", qh->Cap); + USB_debug(" 0x%08x (Current qtd Pointer)\n", qh->Curr_qTD); + USB_debug(" --- Overlay Area ---\n"); + USB_debug(" 0x%08x (Next qtd Pointer)\n", qh->OL_Next_qTD); + USB_debug(" 0x%08x (Alternate Next qtd Pointer)\n", qh->OL_Alt_Next_qTD); + USB_debug(" 0x%08x (qtd Token)\n", qh->OL_Token); + USB_debug(" 0x%08x (Buffer Pointer (page 0))\n", qh->OL_Bptr[0]); + USB_debug("\n"); + + qtd = QTD_PTR(qh->Curr_qTD); + while (qtd != NULL) + { + dump_ehci_qtd(qtd); + qtd = QTD_PTR(qtd->Next_qTD); + } + qh = QH_PTR(qh->HLink); + } + while (qh != _H_qh); +} + +static void dump_ehci_asynclist_simple(void) +{ + QH_T *qh = _H_qh; + + USB_debug(">>> EHCI Asynchronous List <<<\n"); + USB_debug("[QH] => "); + do + { + USB_debug("0x%08x ", (int)qh); + qh = QH_PTR(qh->HLink); + } + while (qh != _H_qh); + USB_debug("\n"); +} + +static void dump_ehci_period_frame_list_simple(void) +{ + QH_T *qh = _Iqh[NUM_IQH - 1]; + + USB_debug(">>> EHCI period frame list simple <<<\n"); + USB_debug("[FList] => "); + do + { + USB_debug("0x%08x ", (int)qh); + qh = QH_PTR(qh->HLink); + } + while (qh != NULL); + USB_debug("\n"); +} + +static void dump_ehci_period_frame_list() +{ + int i; + QH_T *qh; + + for (i = 0; i < FL_SIZE; i++) + { + USB_debug("!%02d: ", i); + qh = QH_PTR(_PFList[i]);; + while (qh != NULL) + { + // USB_debug("0x%x (0x%x) => ", (int)qh, qh->HLink); + USB_debug("0x%x => ", (int)qh); + qh = QH_PTR(qh->HLink); + } + USB_debug("0\n"); + } +} + +#endif /* ENABLE_ERROR_MSG */ + +static void init_periodic_frame_list() +{ + QH_T *qh_p; + int i, idx, interval; + + _PFList = (uint32_t *)((uint32_t)_PFList_mem | NON_CACHE_MASK); + memset(_PFList, 0, sizeof(_PFList_mem)); + + iso_ep_list = NULL; + + for (i = NUM_IQH - 1; i >= 0; i--) /* interval = i^2 */ + { + _Iqh[i] = alloc_ehci_QH(); + + _Iqh[i]->HLink = QH_HLNK_END; + _Iqh[i]->Curr_qTD = (uint32_t)_ghost_qtd; + _Iqh[i]->OL_Next_qTD = QTD_LIST_END; + _Iqh[i]->OL_Alt_Next_qTD = (uint32_t)_ghost_qtd; + _Iqh[i]->OL_Token = QTD_STS_HALT; + + interval = 0x1 << i; + + for (idx = interval - 1; idx < FL_SIZE; idx += interval) + { + if (_PFList[idx] == 0) /* is empty list, insert directly */ + { + _PFList[idx] = QH_HLNK_QH(_Iqh[i]); + } + else + { + qh_p = QH_PTR(_PFList[idx]); + + while (1) + { + if (qh_p == _Iqh[i]) + break; /* already chained by previous visit */ + + if (qh_p->HLink == QH_HLNK_END) /* reach end of list? */ + { + qh_p->HLink = QH_HLNK_QH(_Iqh[i]); + break; + } + qh_p = QH_PTR(qh_p->HLink); + } + } + } + } +} + +static QH_T *get_int_tree_head_node(int interval) +{ + int i; + + interval /= 8; /* each frame list entry for 8 micro-frame */ + + for (i = 0; i < NUM_IQH - 1; i++) + { + interval >>= 1; + if (interval == 0) + return _Iqh[i]; + } + return _Iqh[NUM_IQH - 1]; +} + +static int make_int_s_mask(int bInterval) +{ + int order, interval; + + interval = 1; + while (bInterval > 1) + { + interval *= 2; + bInterval--; + } + + if (interval < 2) + return 0xFF; /* interval 1 */ + if (interval < 4) + return 0x55; /* interval 2 */ + if (interval < 8) + return 0x22; /* interval 4 */ + for (order = 0; (interval > 1); order++) + { + interval >>= 1; + } + return (0x1 << (order % 8)); +} + +static int ehci_init(void) +{ + int timeout = 250 * 1000; /* EHCI reset time-out 250 ms */ + + /*------------------------------------------------------------------------------------*/ + /* Reset EHCI host controller */ + /*------------------------------------------------------------------------------------*/ + _ehci->UCMDR = HSUSBH_UCMDR_HCRST_Msk; + while ((_ehci->UCMDR & HSUSBH_UCMDR_HCRST_Msk) && (timeout > 0)) + { + usbh_delay_ms(1); + timeout -= 1000; + } + if (_ehci->UCMDR & HSUSBH_UCMDR_HCRST_Msk) + return USBH_ERR_EHCI_INIT; + + _ehci->UCMDR = UCMDR_INT_THR_CTRL | HSUSBH_UCMDR_RUN_Msk; + + _ghost_qtd = alloc_ehci_qTD(NULL); + _ghost_qtd->Token = 0x11197B7F; //QTD_STS_HALT; visit_qtd() will not remove a qTD with this mark. It represents a qhost qTD. + + /*------------------------------------------------------------------------------------*/ + /* Initialize asynchronous list */ + /*------------------------------------------------------------------------------------*/ + qh_remove_list = NULL; + + /* Create the QH list head with H-bit 1 */ + _H_qh = alloc_ehci_QH(); + _H_qh->HLink = QH_HLNK_QH(_H_qh); /* circular link to itself, the only one QH */ + _H_qh->Chrst = QH_RCLM_LIST_HEAD; /* it's the head of reclamation list */ + _H_qh->Curr_qTD = (uint32_t)_ghost_qtd; + _H_qh->OL_Next_qTD = QTD_LIST_END; + _H_qh->OL_Alt_Next_qTD = (uint32_t)_ghost_qtd; + _H_qh->OL_Token = QTD_STS_HALT; + _ehci->UCALAR = (uint32_t)_H_qh; + + /*------------------------------------------------------------------------------------*/ + /* Initialize periodic list */ + /*------------------------------------------------------------------------------------*/ + if (FL_SIZE == 256) + _ehci->UCMDR |= (0x2 << HSUSBH_UCMDR_FLSZ_Pos); + else if (FL_SIZE == 512) + _ehci->UCMDR |= (0x1 << HSUSBH_UCMDR_FLSZ_Pos); + else if (FL_SIZE == 1024) + _ehci->UCMDR |= (0x0 << HSUSBH_UCMDR_FLSZ_Pos); + else + return USBH_ERR_EHCI_INIT; /* Invalid FL_SIZE setting! */ + + /*------------------------------------------------------------------------------------*/ + /* start run */ + /*------------------------------------------------------------------------------------*/ + + _ehci->UCFGR = 0x1; /* enable port routing to EHCI */ + _ehci->UIENR = HSUSBH_UIENR_USBIEN_Msk | HSUSBH_UIENR_UERRIEN_Msk | HSUSBH_UIENR_HSERREN_Msk | HSUSBH_UIENR_IAAEN_Msk; + + usbh_delay_ms(1); /* delay 1 ms */ + + _ehci->UPSCR[0] = HSUSBH_UPSCR_PP_Msk; /* enable port 1 port power */ + //_ehci->UPSCR[0] = HSUSBH_UPSCR_PP_Msk | HSUSBH_UPSCR_PO_Msk; /* set port owner to OHCI */ + + init_periodic_frame_list(); + + _ehci->UPFLBAR = (uint32_t)_PFList; + usbh_delay_ms(10); /* delay 10 ms */ + + return 0; +} + +static void ehci_suspend(void) +{ + if (_ehci->UPSCR[0] & 0x1) + _ehci->UPSCR[0] |= HSUSBH_UPSCR_SUSPEND_Msk; +} + +static void ehci_resume(void) +{ + if (_ehci->UPSCR[0] & 0x1) + _ehci->UPSCR[0] = (_ehci->UPSCR[0] & ~HSUSBH_UPSCR_SUSPEND_Msk) | HSUSBH_UPSCR_FPR_Msk; +} + +static void ehci_shutdown(void) +{ + ehci_suspend(); +} + +static void move_qh_to_remove_list(QH_T *qh) +{ + QH_T *q; + + // USB_debug("move_qh_to_remove_list - 0x%x (0x%x)\n", (int)qh, qh->Chrst); + + /* check if this ED found in ed_remove_list */ + q = qh_remove_list; + while (q) + { + if (q == qh) /* This QH found in qh_remove_list. */ + { + return; /* Do nothing, return... */ + } + q = q->next; + } + + DISABLE_EHCI_IRQ(); + + /*------------------------------------------------------------------------------------*/ + /* Search asynchronous frame list and remove qh if found in list. */ + /*------------------------------------------------------------------------------------*/ + q = _H_qh; /* find and remove it from asynchronous list */ + while (QH_PTR(q->HLink) != _H_qh) + { + if (QH_PTR(q->HLink) == qh) + { + /* q's next QH is qh, found... */ + q->HLink = qh->HLink; /* remove qh from list */ + + qh->next = qh_remove_list; /* add qh to qh_remove_list */ + qh_remove_list = qh; + _ehci->UCMDR |= HSUSBH_UCMDR_IAAD_Msk; /* trigger IAA interrupt */ + ENABLE_EHCI_IRQ(); + return; /* done */ + } + q = QH_PTR(q->HLink); /* advance to next QH in asynchronous list */ + } + + /*------------------------------------------------------------------------------------*/ + /* Search periodic frame list and remove qh if found in list. */ + /*------------------------------------------------------------------------------------*/ + q = _Iqh[NUM_IQH - 1]; + while (q->HLink != QH_HLNK_END) + { + if (QH_PTR(q->HLink) == qh) + { + /* q's next QH is qh, found... */ + q->HLink = qh->HLink; /* remove qh from list */ + + qh->next = qh_remove_list; /* add qh to qh_remove_list */ + qh_remove_list = qh; + _ehci->UCMDR |= HSUSBH_UCMDR_IAAD_Msk; /* trigger IAA interrupt */ + ENABLE_EHCI_IRQ(); + return; /* done */ + } + q = QH_PTR(q->HLink); /* advance to next QH in asynchronous list */ + } + ENABLE_EHCI_IRQ(); +} + +static void append_to_qtd_list_of_QH(QH_T *qh, qTD_T *qtd) +{ + qTD_T *q; + + if (qh->qtd_list == NULL) + { + qh->qtd_list = qtd; + } + else + { + q = qh->qtd_list; + while (q->next != NULL) + { + q = q->next; + } + q->next = qtd; + } +} + +/* + * If ep==NULL, it's a control endpoint QH. + */ +static void write_qh(UDEV_T *udev, EP_INFO_T *ep, QH_T *qh) +{ + uint32_t chrst, cap; + + /*------------------------------------------------------------------------------------*/ + /* Write QH DWord 1 - Endpoint Characteristics */ + /*------------------------------------------------------------------------------------*/ + if (ep == NULL) /* is control endpoint? */ + { + if (udev->descriptor.bMaxPacketSize0 == 0) + { + if (udev->speed == SPEED_LOW) /* give a default maximum packet size */ + udev->descriptor.bMaxPacketSize0 = 8; + else + udev->descriptor.bMaxPacketSize0 = 64; + } + chrst = QH_DTC | QH_NAK_RL | (udev->descriptor.bMaxPacketSize0 << 16); + if (udev->speed != SPEED_HIGH) + chrst |= QH_CTRL_EP_FLAG; /* non-high-speed control endpoint */ + } + else /* not a control endpoint */ + { + chrst = QH_NAK_RL | (ep->wMaxPacketSize << 16); + chrst |= ((ep->bEndpointAddress & 0xf) << 8); /* Endpoint Address */ + } + + if (udev->speed == SPEED_LOW) + chrst |= QH_EPS_LOW; + else if (udev->speed == SPEED_FULL) + chrst |= QH_EPS_FULL; + else + chrst |= QH_EPS_HIGH; + + chrst |= udev->dev_num; + + qh->Chrst = chrst; + + /*------------------------------------------------------------------------------------*/ + /* Write QH DWord 2 - Endpoint Capabilities */ + /*------------------------------------------------------------------------------------*/ + if (udev->speed == SPEED_HIGH) + { + cap = 0x40000000; + } + else + { + /* + * Backtrace device tree until the USB 2.0 hub found + */ + HUB_DEV_T *hub; + int port_num; + + port_num = udev->port_num; + hub = udev->parent; + + while ((hub != NULL) && (hub->iface->udev->speed != SPEED_HIGH)) + { + port_num = hub->iface->udev->port_num; + hub = hub->iface->udev->parent; + } + + cap = (port_num << QH_HUB_PORT_Pos) | + (hub->iface->udev->dev_num << QH_HUB_ADDR_Pos); + } + + qh->Cap = cap; +} + +static void write_qtd_bptr(qTD_T *qtd, uint32_t buff_addr, int xfer_len) +{ + int i; + + qtd->xfer_len = xfer_len; + qtd->Bptr[0] = buff_addr; + + buff_addr = (buff_addr + 0x1000) & ~0xFFF; + + for (i = 1; i < 5; i++) + { + qtd->Bptr[i] = buff_addr; + buff_addr += 0x1000; + } +} + +static int ehci_ctrl_xfer(UTR_T *utr) +{ + UDEV_T *udev; + QH_T *qh; + qTD_T *qtd_setup, *qtd_data, *qtd_status; + uint32_t token; + int is_new_qh = 0; + + udev = utr->udev; + + if (utr->data_len > 0) + { + if (((uint32_t)utr->buff + utr->data_len) > (((uint32_t)utr->buff & ~0xFFF) + 0x5000)) + return USBH_ERR_BUFF_OVERRUN; + } + + /*------------------------------------------------------------------------------------*/ + /* Allocate and link QH */ + /*------------------------------------------------------------------------------------*/ + if (udev->ep0.hw_pipe != NULL) + { + qh = (QH_T *)udev->ep0.hw_pipe; + if (qh->qtd_list) + return USBH_ERR_EHCI_QH_BUSY; + } + else + { + qh = alloc_ehci_QH(); + if (qh == NULL) + return USBH_ERR_MEMORY_OUT; + + udev->ep0.hw_pipe = (void *)qh; /* driver can find QH from EP */ + is_new_qh = 1; + } + write_qh(udev, NULL, qh); + utr->ep = &udev->ep0; /* driver can find EP from UTR */ + + /*------------------------------------------------------------------------------------*/ + /* Allocate qTDs */ + /*------------------------------------------------------------------------------------*/ + qtd_setup = alloc_ehci_qTD(utr); /* allocate qTD for SETUP */ + + if (utr->data_len > 0) + qtd_data = alloc_ehci_qTD(utr); /* allocate qTD for DATA */ + else + qtd_data = NULL; + + qtd_status = alloc_ehci_qTD(utr); /* allocate qTD for USTSR */ + + if (qtd_status == NULL) /* out of memory? */ + { + if (qtd_setup) + free_ehci_qTD(qtd_setup); /* free memory */ + if (qtd_data) + free_ehci_qTD(qtd_data); /* free memory */ + return USBH_ERR_MEMORY_OUT; /* out of memory */ + } + + //USB_debug("qh=0x%x, qtd_setup=0x%x, qtd_data=0x%x, qtd_status=0x%x\n", (int)qh, (int)qtd_setup, (int)qtd_data, (int)qtd_status); + + /*------------------------------------------------------------------------------------*/ + /* prepare SETUP stage qTD */ + /*------------------------------------------------------------------------------------*/ + qtd_setup->qh = qh; + //qtd_setup->utr = utr; + write_qtd_bptr(qtd_setup, (uint32_t)&utr->setup, 8); + append_to_qtd_list_of_QH(qh, qtd_setup); + qtd_setup->Token = (8 << 16) | QTD_ERR_COUNTER | QTD_PID_SETUP | QTD_STS_ACTIVE; + + /*------------------------------------------------------------------------------------*/ + /* prepare DATA stage qTD */ + /*------------------------------------------------------------------------------------*/ + if (utr->data_len > 0) + { + qtd_setup->Next_qTD = (uint32_t)qtd_data; + qtd_data->Next_qTD = (uint32_t)qtd_status; + + if ((utr->setup.bmRequestType & 0x80) == REQ_TYPE_OUT) + token = QTD_ERR_COUNTER | QTD_PID_OUT | QTD_STS_ACTIVE; + else + token = QTD_ERR_COUNTER | QTD_PID_IN | QTD_STS_ACTIVE; + + qtd_data->qh = qh; + //qtd_data->utr = utr; + write_qtd_bptr(qtd_data, (uint32_t)utr->buff, utr->data_len); + append_to_qtd_list_of_QH(qh, qtd_data); + qtd_data->Token = QTD_DT | (utr->data_len << 16) | token; + } + else + { + qtd_setup->Next_qTD = (uint32_t)qtd_status; + } + + /*------------------------------------------------------------------------------------*/ + /* prepare USTSR stage qTD */ + /*------------------------------------------------------------------------------------*/ + qtd_status->Next_qTD = (uint32_t)_ghost_qtd; + qtd_status->Alt_Next_qTD = QTD_LIST_END; + + if ((utr->setup.bmRequestType & 0x80) == REQ_TYPE_OUT) + token = QTD_ERR_COUNTER | QTD_PID_IN | QTD_STS_ACTIVE; + else + token = QTD_ERR_COUNTER | QTD_PID_OUT | QTD_STS_ACTIVE; + + qtd_status->qh = qh; + //qtd_status->utr = utr; + append_to_qtd_list_of_QH(qh, qtd_status); + qtd_status->Token = QTD_DT | QTD_IOC | token; + + /*------------------------------------------------------------------------------------*/ + /* Update QH overlay */ + /*------------------------------------------------------------------------------------*/ + qh->Curr_qTD = 0; + qh->OL_Next_qTD = (uint32_t)qtd_setup; + qh->OL_Alt_Next_qTD = QTD_LIST_END; + qh->OL_Token = 0; + + /*------------------------------------------------------------------------------------*/ + /* Link QH and start asynchronous transfer */ + /*------------------------------------------------------------------------------------*/ + if (is_new_qh) + { + qh->HLink = _H_qh->HLink; + _H_qh->HLink = QH_HLNK_QH(qh); + } + + /* Start transfer */ + _ehci->UCMDR |= HSUSBH_UCMDR_ASEN_Msk; /* start asynchronous transfer */ + return 0; +} + +static int ehci_bulk_xfer(UTR_T *utr) +{ + UDEV_T *udev; + EP_INFO_T *ep = utr->ep; + QH_T *qh; + qTD_T *qtd, *qtd_pre; + uint32_t data_len, xfer_len; + uint8_t *buff; + uint32_t token; + int is_new_qh = 0; + + //USB_debug("Bulk XFER =>\n"); + // dump_ehci_asynclist_simple(); + + udev = utr->udev; + + if (ep->hw_pipe != NULL) + { + qh = (QH_T *)ep->hw_pipe ; + if (qh->qtd_list) + { + return USBH_ERR_EHCI_QH_BUSY; + } + } + else + { + qh = alloc_ehci_QH(); + if (qh == NULL) + return USBH_ERR_MEMORY_OUT; + is_new_qh = 1; + write_qh(udev, ep, qh); + ep->hw_pipe = (void *)qh; /* associate QH with endpoint */ + } + + /*------------------------------------------------------------------------------------*/ + /* Prepare qTDs */ + /*------------------------------------------------------------------------------------*/ + data_len = utr->data_len; + buff = utr->buff; + qtd_pre = NULL; + + while (data_len > 0) + { + qtd = alloc_ehci_qTD(utr); + if (qtd == NULL) /* failed to allocate a qTD */ + { + qtd = qh->qtd_list; + while (qtd != NULL) + { + qtd_pre = qtd; + qtd = qtd->next; + free_ehci_qTD(qtd_pre); + } + if (is_new_qh) + { + free_ehci_QH(qh); + ep->hw_pipe = NULL; + } + return USBH_ERR_MEMORY_OUT; + } + + if ((ep->bEndpointAddress & EP_ADDR_DIR_MASK) == EP_ADDR_DIR_OUT) + token = QTD_ERR_COUNTER | QTD_PID_OUT | QTD_STS_ACTIVE; + else + token = QTD_ERR_COUNTER | QTD_PID_IN | QTD_STS_ACTIVE; + + if (data_len > 0x4000) /* force maximum x'fer length 16K per qTD */ + xfer_len = 0x4000; + else + xfer_len = data_len; /* remaining data length < 4K */ + + qtd->qh = qh; + qtd->Next_qTD = (uint32_t)_ghost_qtd; + qtd->Alt_Next_qTD = QTD_LIST_END; //(uint32_t)_ghost_qtd; + write_qtd_bptr(qtd, (uint32_t)buff, xfer_len); + append_to_qtd_list_of_QH(qh, qtd); + qtd->Token = (xfer_len << 16) | token; + + buff += xfer_len; /* advanced buffer pointer */ + data_len -= xfer_len; + + if (data_len == 0) /* is this the latest qTD? */ + { + qtd->Token |= QTD_IOC; /* ask to raise an interrupt on the last qTD */ + qtd->Next_qTD = (uint32_t)_ghost_qtd; /* qTD list end */ + } + + if (qtd_pre != NULL) + qtd_pre->Next_qTD = (uint32_t)qtd; + qtd_pre = qtd; + } + + //USB_debug("utr=0x%x, qh=0x%x, qtd=0x%x\n", (int)utr, (int)qh, (int)qh->qtd_list); + + qtd = qh->qtd_list; + + qh->OL_Next_qTD = (uint32_t)qtd; + + /*------------------------------------------------------------------------------------*/ + /* Link QH and start asynchronous transfer */ + /*------------------------------------------------------------------------------------*/ + if (is_new_qh) + { + memcpy(&(qh->OL_Bptr[0]), &(qtd->Bptr[0]), 20); + qh->Curr_qTD = (uint32_t)qtd; + + qh->OL_Token = 0; //qtd->Token; + + if (utr->ep->bToggle) + qh->OL_Token |= QTD_DT; + + qh->HLink = _H_qh->HLink; + _H_qh->HLink = QH_HLNK_QH(qh); + } + + /* Start transfer */ + _ehci->UCMDR |= HSUSBH_UCMDR_ASEN_Msk; /* start asynchronous transfer */ + + return 0; +} + +static int ehci_int_xfer(UTR_T *utr) +{ + UDEV_T *udev = utr->udev; + EP_INFO_T *ep = utr->ep; + QH_T *qh, *iqh; + qTD_T *qtd; + uint32_t token; + int8_t is_new_qh = 0; + + if (ep->hw_pipe != NULL) + { + qh = (QH_T *)ep->hw_pipe ; + if (qh->qtd_list) + return USBH_ERR_EHCI_QH_BUSY; + } + else + { + qh = alloc_ehci_QH(); + if (qh == NULL) + return USBH_ERR_MEMORY_OUT; + is_new_qh = 1; + write_qh(udev, ep, qh); + qh->Chrst &= ~0xF0000000; + + if (udev->speed == SPEED_HIGH) + { + qh->Cap = (0x1 << QH_MULT_Pos) | (qh->Cap & 0xff) | make_int_s_mask(ep->bInterval); + } + else + { + qh->Cap = (0x1 << QH_MULT_Pos) | (qh->Cap & ~(QH_C_MASK_Msk | QH_S_MASK_Msk)) | 0x7802; + } + ep->hw_pipe = (void *)qh; /* associate QH with endpoint */ + } + + /*------------------------------------------------------------------------------------*/ + /* Prepare qTD */ + /*------------------------------------------------------------------------------------*/ + qtd = alloc_ehci_qTD(utr); + if (qtd == NULL) /* failed to allocate a qTD */ + { + if (is_new_qh) + { + free_ehci_QH(qh); + ep->hw_pipe = NULL; + } + return USBH_ERR_MEMORY_OUT; + } + + if ((ep->bEndpointAddress & EP_ADDR_DIR_MASK) == EP_ADDR_DIR_OUT) + token = QTD_ERR_COUNTER | QTD_PID_OUT | QTD_STS_ACTIVE; + else + token = QTD_ERR_COUNTER | QTD_PID_IN | QTD_STS_ACTIVE; + + qtd->qh = qh; + qtd->Next_qTD = QTD_LIST_END; //(uint32_t)_ghost_qtd; + qtd->Alt_Next_qTD = QTD_LIST_END; //(uint32_t)_ghost_qtd; + write_qtd_bptr(qtd, (uint32_t)utr->buff, utr->data_len); + append_to_qtd_list_of_QH(qh, qtd); + qtd->Token = QTD_IOC | (utr->data_len << 16) | token; + + DISABLE_EHCI_IRQ(); + + USB_debug("ehci_int_xfer - qh: 0x%x, 0x%x, 0x%x, qtd: 0x%x\n", (int)qh, (int)qh->Chrst, (int)qh->Cap, (int)qtd); + + qh->OL_Next_qTD = (uint32_t)qtd; + + if (is_new_qh) + { + memcpy(&(qh->OL_Bptr[0]), &(qtd->Bptr[0]), 20); + qh->Curr_qTD = (uint32_t)qtd; + qh->OL_Token = qtd->Token; + + if (udev->speed == SPEED_HIGH) /* get head node of this interval */ + iqh = get_int_tree_head_node(ep->bInterval); + else + iqh = get_int_tree_head_node(ep->bInterval * 8); + qh->HLink = iqh->HLink; /* Add to list of the same interval */ + iqh->HLink = QH_HLNK_QH(qh); + } + + ENABLE_EHCI_IRQ(); + + _ehci->UCMDR |= HSUSBH_UCMDR_PSEN_Msk; /* periodic list enable */ + return 0; +} + +/* + * Quit current trasnfer via UTR or hardware EP. + */ +static int ehci_quit_xfer(UTR_T *utr, EP_INFO_T *ep) +{ + QH_T *qh; + + // USB_debug("ehci_quit_xfer - utr: 0x%x, ep: 0x%x\n", (int)utr, (int)ep); + + DISABLE_EHCI_IRQ(); + if (ehci_quit_iso_xfer(utr, ep) == 0) + { + ENABLE_EHCI_IRQ(); + return 0; + } + ENABLE_EHCI_IRQ(); + + if (utr != NULL) + { + if (utr->ep == NULL) + return USBH_ERR_NOT_FOUND; + + qh = (QH_T *)(utr->ep->hw_pipe); + + if (!qh) + return USBH_ERR_NOT_FOUND; + + /* add the QH to remove list, it will be removed on the next IAAD interrupt */ + move_qh_to_remove_list(qh); + utr->ep->hw_pipe = NULL; + } + + if ((ep != NULL) && (ep->hw_pipe != NULL)) + { + qh = (QH_T *)(ep->hw_pipe); + /* add the QH to remove list, it will be removed on the next IAAD interrupt */ + move_qh_to_remove_list(qh); + ep->hw_pipe = NULL; + } + usbh_delay_ms(2); + + return 0; +} + +static int visit_qtd(qTD_T *qtd) +{ + if ((qtd->Token == 0x11197B7F) || (qtd->Token == 0x1197B7F)) + return 0; /* A Dummy qTD or qTD on writing, don't touch it. */ + + // USB_debug("Visit qtd 0x%x - 0x%x\n", (int)qtd, qtd->Token); + + if ((qtd->Token & QTD_STS_ACTIVE) == 0) + { + if (qtd->Token & (QTD_STS_HALT | QTD_STS_DATA_BUFF_ERR | QTD_STS_BABBLE | QTD_STS_XactErr | QTD_STS_MISS_MF)) + { + USB_error("qTD 0x%x error token=0x%x! 0x%x\n", (int)qtd, qtd->Token, qtd->Bptr[0]); + if (qtd->utr->status == 0) + qtd->utr->status = USBH_ERR_TRANSACTION; + } + else + { + if ((qtd->Token & QTD_PID_Msk) != QTD_PID_SETUP) + { + qtd->utr->xfer_len += qtd->xfer_len - QTD_TODO_LEN(qtd->Token); + // USB_debug("0x%x utr->xfer_len += %d\n", qtd->Token, qtd->xfer_len - QTD_TODO_LEN(qtd->Token)); + } + } + return 1; + } + return 0; +} + +static void scan_asynchronous_list() +{ + QH_T *qh, *qh_tmp; + qTD_T *q_pre, *qtd, *qtd_tmp; + UTR_T *utr; + + q_pre = NULL; + qh = QH_PTR(_H_qh->HLink); + while (qh != _H_qh) + { + // USB_debug("Scan qh=0x%x, 0x%x\n", (int)qh, qh->OL_Token); + + utr = NULL; + qtd = qh->qtd_list; + while (qtd != NULL) + { + if (visit_qtd(qtd)) /* if TRUE, reclaim this qtd */ + { + /* qTD is completed, will remove it */ + utr = qtd->utr; + if (qtd == qh->qtd_list) + qh->qtd_list = qtd->next; /* unlink the qTD from qtd_list */ + else + q_pre->next = qtd->next; /* unlink the qTD from qtd_list */ + + qtd_tmp = qtd; /* remember this qTD for freeing later */ + qtd = qtd->next; /* advance to the next qTD */ + + qtd_tmp->next = qh->done_list; /* push this qTD to QH's done list */ + qh->done_list = qtd_tmp; + } + else + { + q_pre = qtd; /* remember this qTD as a preceder */ + qtd = qtd->next; /* advance to next qTD */ + } + } + + qh_tmp = qh; + qh = QH_PTR(qh->HLink); /* advance to the next QH */ + + /* If all TDs are done, call-back to requester and then remove this QH. */ + if ((qh_tmp->qtd_list == NULL) && utr) + { + // printf("T %d [%d]\n", (qh_tmp->Chrst>>8)&0xf, (qh_tmp->OL_Token&QTD_DT) ? 1 : 0); + if (qh_tmp->OL_Token & QTD_DT) + utr->ep->bToggle = 1; + else + utr->ep->bToggle = 0; + + utr->bIsTransferDone = 1; + if (utr->func) + utr->func(utr); + + _ehci->UCMDR |= HSUSBH_UCMDR_IAAD_Msk; /* trigger IAA to reclaim done_list */ + } + } +} + +static void scan_periodic_frame_list() +{ + QH_T *qh; + qTD_T *qtd; + UTR_T *utr; + + /*------------------------------------------------------------------------------------*/ + /* Scan interrupt frame list */ + /*------------------------------------------------------------------------------------*/ + qh = _Iqh[NUM_IQH - 1]; + while (qh != NULL) + { + qtd = qh->qtd_list; /* There's only one qTD in list at most. */ + + if (qtd == NULL) + { + /* empty QH */ + qh = QH_PTR(qh->HLink); /* advance to the next QH */ + continue; + } + + if (visit_qtd(qtd)) /* if TRUE, reclaim this qtd */ + { + qtd->next = qh->done_list; /* push qTD into the done list */ + qh->done_list = qtd; + qh->qtd_list = NULL; /* qtd_list becomes empty */ + } + + qtd = qh->done_list; + + /* If all TDs are done, call-back to requester and then remove this QH. */ + if ((qtd != NULL) && (qh->qtd_list == NULL)) + { + utr = qtd->utr; + + if (qh->OL_Token & QTD_DT) + utr->ep->bToggle = 1; + else + utr->ep->bToggle = 0; + + utr->bIsTransferDone = 1; + if (utr->func) + utr->func(utr); + + _ehci->UCMDR |= HSUSBH_UCMDR_IAAD_Msk; /* trigger IAA to reclaim done_list */ + } + + qh = QH_PTR(qh->HLink); /* advance to the next QH */ + } + + /*------------------------------------------------------------------------------------*/ + /* Scan isochronous frame list */ + /*------------------------------------------------------------------------------------*/ + + scan_isochronous_list(); +} + +static void iaad_remove_qh() +{ + QH_T *qh; + qTD_T *qtd; + UTR_T *utr; + + /*------------------------------------------------------------------------------------*/ + /* Remove all QHs in qh_remove_list... */ + /*------------------------------------------------------------------------------------*/ + while (qh_remove_list != NULL) + { + qh = qh_remove_list; + qh_remove_list = qh->next; + + // USB_debug("iaad_remove_qh - remove QH 0x%x\n", (int)qh); + + while (qh->done_list) /* we can free the qTDs now */ + { + qtd = qh->done_list; + qh->done_list = qtd->next; + free_ehci_qTD(qtd); + } + + if (qh->qtd_list != NULL) /* still have incomplete qTDs? */ + { + utr = qh->qtd_list->utr; + while (qh->qtd_list) + { + qtd = qh->qtd_list; + qh->qtd_list = qtd->next; + free_ehci_qTD(qtd); + } + utr->status = USBH_ERR_ABORT; + utr->bIsTransferDone = 1; + if (utr->func) + utr->func(utr); /* call back */ + } + free_ehci_QH(qh); /* free the QH */ + } + + /*------------------------------------------------------------------------------------*/ + /* Free all qTD in done_list of each asynchronous QH */ + /*------------------------------------------------------------------------------------*/ + qh = QH_PTR(_H_qh->HLink); + while (qh != _H_qh) + { + while (qh->done_list) /* we can free the qTDs now */ + { + qtd = qh->done_list; + qh->done_list = qtd->next; + free_ehci_qTD(qtd); + } + qh = QH_PTR(qh->HLink); /* advance to the next QH */ + } + + /*------------------------------------------------------------------------------------*/ + /* Free all qTD in done_list of each QH of periodic frame list */ + /*------------------------------------------------------------------------------------*/ + qh = _Iqh[NUM_IQH - 1]; + while (qh != NULL) + { + while (qh->done_list) /* we can free the qTDs now */ + { + qtd = qh->done_list; + qh->done_list = qtd->next; + free_ehci_qTD(qtd); + } + qh = QH_PTR(qh->HLink); /* advance to the next QH */ + } +} + +//static irqreturn_t ehci_irq (struct usb_hcd *hcd) +void EHCI_IRQHandler(int vector, void *param) +{ + uint32_t intsts; + + intsts = _ehci->USTSR; + _ehci->USTSR = intsts; /* clear interrupt status */ + + //rt_kprintf("[%s]ehci int_sts = 0x%x\n", __func__, intsts); + + if (intsts & HSUSBH_USTSR_UERRINT_Msk) + { + USB_error("Transfer error!\n"); + } + + if (intsts & HSUSBH_USTSR_USBINT_Msk) + { + /* some transfers completed, travel asynchronous */ + /* and periodic lists to find and reclaim them. */ + scan_asynchronous_list(); + + scan_periodic_frame_list(); + } + + if (intsts & HSUSBH_USTSR_IAA_Msk) + { + iaad_remove_qh(); + } +} + +static UDEV_T *ehci_find_device_by_port(int port) +{ + UDEV_T *udev; + + udev = g_udev_list; + while (udev != NULL) + { + if ((udev->parent == NULL) && (udev->port_num == port) && (udev->speed == SPEED_HIGH)) + return udev; + udev = udev->next; + } + return NULL; +} + +static int ehci_rh_port_reset(int port) +{ + int retry; + int reset_time; + uint32_t t0; + + reset_time = usbh_tick_from_millisecond(PORT_RESET_TIME_MS); + + for (retry = 0; retry < PORT_RESET_RETRY; retry++) + { + _ehci->UPSCR[port] = (_ehci->UPSCR[port] | HSUSBH_UPSCR_PRST_Msk) & ~HSUSBH_UPSCR_PE_Msk; + + t0 = usbh_get_ticks(); + while (usbh_get_ticks() - t0 < (reset_time) + 1) ; /* wait at least 50 ms */ + + _ehci->UPSCR[port] &= ~HSUSBH_UPSCR_PRST_Msk; + + t0 = usbh_get_ticks(); + while (usbh_get_ticks() - t0 < (reset_time) + 1) + { + if (!(_ehci->UPSCR[port] & HSUSBH_UPSCR_CCS_Msk) || + ((_ehci->UPSCR[port] & (HSUSBH_UPSCR_CCS_Msk | HSUSBH_UPSCR_PE_Msk)) == (HSUSBH_UPSCR_CCS_Msk | HSUSBH_UPSCR_PE_Msk))) + goto port_reset_done; + } + reset_time += PORT_RESET_RETRY_INC_MS; + } + + USB_debug("EHCI port %d - port reset failed!\n", port + 1); + return USBH_ERR_PORT_RESET; + +port_reset_done: + if ((_ehci->UPSCR[port] & HSUSBH_UPSCR_CCS_Msk) == 0) /* check again if device disconnected */ + { + _ehci->UPSCR[port] |= HSUSBH_UPSCR_CSC_Msk; /* clear CSC */ + return USBH_ERR_DISCONNECTED; + } + _ehci->UPSCR[port] |= HSUSBH_UPSCR_PEC_Msk; /* clear port enable change status */ + return USBH_OK; /* port reset success */ +} + +static int ehci_rh_polling(void) +{ + UDEV_T *udev; + int ret, change = 0; + int port; + int connect_status, t0, debounce_tick; + + for (port = 0; port < EHCI_PORT_CNT; port++) + { + if (!(_ehci->UPSCR[port] & HSUSBH_UPSCR_CSC_Msk)) + continue; + + change = 1; + rt_kprintf("EHCI port%d status change: 0x%x\n", port + 1, _ehci->UPSCR[port]); + + /*--------------------------------------------------------------------------------*/ + /* Disconnect the devices attached to this port. */ + /*--------------------------------------------------------------------------------*/ + while (1) + { + udev = ehci_find_device_by_port(port + 1); + if (udev == NULL) + break; + usbh_disconnect_device(udev); + } + + /*--------------------------------------------------------------------------------*/ + /* Port de-bounce */ + /*--------------------------------------------------------------------------------*/ + t0 = usbh_get_ticks(); + debounce_tick = usbh_tick_from_millisecond(HUB_DEBOUNCE_TIME); + connect_status = _ehci->UPSCR[port] & HSUSBH_UPSCR_CCS_Msk; + while (usbh_get_ticks() - t0 < debounce_tick) + { + if (connect_status != (_ehci->UPSCR[port] & HSUSBH_UPSCR_CCS_Msk)) + { + /* reset stable time counting */ + t0 = usbh_get_ticks(); + connect_status = _ehci->UPSCR[port] & HSUSBH_UPSCR_CCS_Msk; + } + } + + _ehci->UPSCR[port] |= HSUSBH_UPSCR_CSC_Msk; /* clear connect status change bit */ + + if (connect_status == HSUSBH_UPSCR_CCS_Msk) + { + /*----------------------------------------------------------------------------*/ + /* A new device connected. */ + /*----------------------------------------------------------------------------*/ + if (ehci_rh_port_reset(port) != USBH_OK) + { + /* port reset failed, maybe an USB 1.1 device */ + _ehci->UPSCR[port] |= HSUSBH_UPSCR_PO_Msk; /* change port owner to OHCI */ + _ehci->UPSCR[port] |= HSUSBH_UPSCR_CSC_Msk; /* clear all status change bits */ + return 0; + } + + /* + * Port reset success. Start to enumerate this new device. + */ + udev = alloc_device(); + if (udev == NULL) + return 0; /* out-of-memory, do nothing... */ + + udev->parent = NULL; + udev->port_num = port + 1; + udev->speed = SPEED_HIGH; + udev->hc_driver = &ehci_driver; + + ret = usbh_connect_device(udev); + if (ret < 0) + { + USB_error("connect_device error! [%d]\n", ret); + free_device(udev); + } + } + else + { + /* Device disconnected */ + while (1) + { + udev = ehci_find_device_by_port(port + 1); + if (udev == NULL) + break; + usbh_disconnect_device(udev); + } + } + } + return change; +} + + +/// @endcond HIDDEN_SYMBOLS + +/*** (C) COPYRIGHT 2017 Nuvoton Technology Corp. ***/ diff --git a/bsp/nuvoton/libraries/ma35/UsbHostLib/src/_ehci_iso.c_ b/bsp/nuvoton/libraries/ma35/UsbHostLib/src/_ehci_iso.c_ new file mode 100644 index 0000000000..148132adf3 --- /dev/null +++ b/bsp/nuvoton/libraries/ma35/UsbHostLib/src/_ehci_iso.c_ @@ -0,0 +1,902 @@ +/**************************************************************************//** + * @file ehci_iso.c + * @version V1.10 + * @brief USB EHCI isochronous transfer driver. + * + * @note + * SPDX-License-Identifier: Apache-2.0 + * Copyright (C) 2017 Nuvoton Technology Corp. All rights reserved. +*****************************************************************************/ + +/// @cond HIDDEN_SYMBOLS + +//static uint32_t g_flr_cnt; /* frame list rollover counter */ + +static const uint16_t sitd_OUT_Smask [] = { 0x01, 0x03, 0x07, 0x0f, 0x1f, 0x3f }; + +static int ehci_iso_split_xfer(UTR_T *utr, ISO_EP_T *iso_ep); + +/* + * Inspect the iTD can be reclaimed or not. If yes, collect the transaction results. + * Return: 1 - reclaimed + * 0 - not completed + */ +static int review_itd(iTD_T *itd) +{ + UTR_T *utr; + uint32_t frnidx = itd->sched_frnidx; + uint32_t now_frame = (_ehci->UFINDR >> 3) & 0x3FF; + int i, fidx; + + // printf("R - %d %d, 0x%x\n", now_frame, frnidx, itd->Transaction[0]); + + if (now_frame == frnidx) + { + for (i = 0; i < 8; i++) + { + if (itd->Transaction[i] & ITD_STATUS_ACTIVE) + return 0; /* have any not completed frames */ + } + } + else if (now_frame > frnidx) + { + if ((now_frame - frnidx) > EHCI_ISO_RCLM_RANGE) + return 0; /* don't touch it */ + } + else + { + if (now_frame + FL_SIZE - frnidx > EHCI_ISO_RCLM_RANGE) + return 0; /* don't touch it */ + } + + /* + * Reclaim this iTD + */ + utr = itd->utr; + fidx = itd->fidx; + for (i = 0; i < 8; i++) + { + if (!(itd->trans_mask & (0x1 << i))) + continue; /* not scheduled micro-frame */ + + if (ITD_STATUS(itd->Transaction[i])) + { + if (itd->Transaction[i] & ITD_STATUS_ACTIVE) + { + utr->iso_status[fidx] = USBH_ERR_NOT_ACCESS0; + utr->status = USBH_ERR_NOT_ACCESS0; + } + else if (itd->Transaction[i] & ITD_STATUS_BABBLE) + { + utr->iso_status[fidx] = USBH_ERR_BABBLE_DETECTED; + utr->status = USBH_ERR_TRANSFER; + } + else if (itd->Transaction[i] & ITD_STATUS_BUFF_ERR) + { + utr->iso_status[fidx] = USBH_ERR_DATA_BUFF; + utr->status = USBH_ERR_TRANSFER; + } + else + { + utr->iso_status[fidx] = USBH_ERR_TRANSACTION; + utr->status = USBH_ERR_TRANSFER; + } + } + else + { + utr->iso_status[fidx] = 0; + utr->iso_xlen[fidx] = ITD_XFER_LEN(itd->Transaction[i]); + } + fidx++; + } + utr->td_cnt--; + + if (utr->td_cnt == 0) /* All iTD of this UTR done */ + { + utr->bIsTransferDone = 1; + if (utr->func) + utr->func(utr); + } + + return 1; /* to be reclaimed */ +} + +/* + * Inspect the siTD can be reclaimed or not. If yes, collect the transaction results. + * Return: 1 - reclaimed + * 0 - not completed + */ +static int review_sitd(siTD_T *sitd) +{ + UTR_T *utr; + uint32_t frnidx = sitd->sched_frnidx; + uint32_t now_frame = (_ehci->UFINDR >> 3) & 0x3FF; + int fidx; + uint32_t TotalBytesToTransfer; + + if (now_frame == frnidx) + { + if (SITD_STATUS(sitd->StsCtrl) == SITD_STATUS_ACTIVE) + return 0; + } + else if (now_frame > frnidx) + { + if ((now_frame - frnidx) > EHCI_ISO_RCLM_RANGE) + return 0; /* don't touch it */ + } + else + { + if (now_frame + FL_SIZE - frnidx > EHCI_ISO_RCLM_RANGE) + return 0; /* don't touch it */ + } + + /* + * Reclaim this siTD + */ + utr = sitd->utr; + fidx = sitd->fidx; + + if (SITD_STATUS(sitd->StsCtrl)) + { + if (sitd->StsCtrl & SITD_STATUS_ACTIVE) + { + utr->iso_status[fidx] = USBH_ERR_NOT_ACCESS0; + } + else if (sitd->StsCtrl & SITD_BABBLE_DETECTED) + { + utr->iso_status[fidx] = USBH_ERR_BABBLE_DETECTED; + utr->status = USBH_ERR_TRANSFER; + } + else if (sitd->StsCtrl & SITD_STATUS_BUFF_ERR) + { + utr->iso_status[fidx] = USBH_ERR_DATA_BUFF; + utr->status = USBH_ERR_TRANSFER; + } + else + { + utr->iso_status[fidx] = USBH_ERR_TRANSACTION; + utr->status = USBH_ERR_TRANSFER; + } + } + else + { + TotalBytesToTransfer = (sitd->StsCtrl & SITD_XFER_CNT_Msk) >> SITD_XFER_CNT_Pos; + utr->iso_xlen[fidx] = utr->iso_xlen[fidx] - TotalBytesToTransfer; + utr->iso_status[fidx] = 0; + } + utr->td_cnt--; + + if (utr->td_cnt == 0) /* All iTD of this UTR done */ + { + utr->bIsTransferDone = 1; + if (utr->func) + utr->func(utr); + } + return 1; /* to be reclaimed */ +} + +/* + * Some iTD/siTD may be scheduled but not serviced due to time missed. + * This function scan several earlier frames and drop unserviced iTD/siTD if found. + */ +static void scan_isochronous_list(void) +{ + ISO_EP_T *iso_ep = iso_ep_list; + iTD_T *itd, *itd_pre, *p; + siTD_T *sitd, *sitd_pre, *sp; + uint32_t frnidx; + + DISABLE_EHCI_IRQ(); + + while (iso_ep != NULL) /* Search all activated iso endpoints */ + { + /*--------------------------------------------------------------------------------*/ + /* Scan all iTDs */ + /*--------------------------------------------------------------------------------*/ + itd = iso_ep->itd_list; /* get the first iTD from iso_ep's iTD list */ + itd_pre = NULL; + while (itd != NULL) /* traverse all iTDs of itd list */ + { + if (review_itd(itd)) /* inspect and reclaim iTD */ + { + /*------------------------------------------------------------------------*/ + /* Remove this iTD from period frame list */ + /*------------------------------------------------------------------------*/ + frnidx = itd->sched_frnidx; + if (_PFList[frnidx] == ITD_HLNK_ITD(itd)) + { + /* is the first entry, just change to next */ + _PFList[frnidx] = itd->Next_Link; + } + else + { + p = ITD_PTR(_PFList[frnidx]); /* find the preceding iTD */ + while ((ITD_PTR(p->Next_Link) != itd) && (p != NULL)) + { + p = ITD_PTR(p->Next_Link); + } + + if (p == NULL) /* link list out of control! */ + { + USB_error("An iTD lost refernece to periodic frame list! 0x%x -> %d\n", (int)itd, frnidx); + } + else /* remove iTD from list */ + { + p->Next_Link = itd->Next_Link; + } + } + + /*------------------------------------------------------------------------*/ + /* Remove this iTD from iso_ep's iTD list */ + /*------------------------------------------------------------------------*/ + if (itd_pre == NULL) + { + iso_ep->itd_list = itd->next; + } + else + { + itd_pre->next = itd->next; + } + p = itd->next; + free_ehci_iTD(itd); + itd = p; + } + else + { + itd_pre = itd; + itd = itd->next; /* traverse to the next iTD of iTD list */ + } + } + + /*--------------------------------------------------------------------------------*/ + /* Scan all siTDs */ + /*--------------------------------------------------------------------------------*/ + sitd = iso_ep->sitd_list; /* get the first siTD from iso_ep's siTD list */ + sitd_pre = NULL; + while (sitd != NULL) /* traverse all siTDs of sitd list */ + { + if (review_sitd(sitd)) /* inspect and reclaim siTD */ + { + /*------------------------------------------------------------------------*/ + /* Remove this siTD from period frame list */ + /*------------------------------------------------------------------------*/ + frnidx = sitd->sched_frnidx; + if (_PFList[frnidx] == SITD_HLNK_SITD(sitd)) + { + /* is the first entry, just change to next */ + _PFList[frnidx] = sitd->Next_Link; + } + else + { + sp = SITD_PTR(_PFList[frnidx]); /* find the preceding siTD */ + while ((SITD_PTR(sp->Next_Link) != sitd) && (sp != NULL)) + { + sp = SITD_PTR(sp->Next_Link); + } + + if (sp == NULL) /* link list out of control! */ + { + USB_error("An siTD lost reference to periodic frame list! 0x%x -> %d\n", (int)sitd, frnidx); + } + else /* remove iTD from list */ + { + sp->Next_Link = sitd->Next_Link; + } + } + + /*------------------------------------------------------------------------*/ + /* Remove this siTD from iso_ep's siTD list */ + /*------------------------------------------------------------------------*/ + if (sitd_pre == NULL) + { + iso_ep->sitd_list = sitd->next; + } + else + { + sitd_pre->next = sitd->next; + } + sp = sitd->next; + free_ehci_siTD(sitd); + sitd = sp; + } + else + { + sitd_pre = sitd; + sitd = sitd->next; /* traverse to the next siTD of siTD list */ + } + } + + iso_ep = iso_ep->next; + } + + ENABLE_EHCI_IRQ(); +} + + +static void write_itd_info(UTR_T *utr, iTD_T *itd) +{ + UDEV_T *udev = utr->udev; + EP_INFO_T *ep = utr->ep; /* reference to isochronous endpoint */ + uint32_t buff_page_addr; + int i; + + buff_page_addr = itd->buff_base & 0xFFFFF000; /* 4K page */ + + for (i = 0; i < 7; i++) + { + itd->Bptr[i] = buff_page_addr + (0x1000 * i); + } + /* EndPtr R Device Address */ + itd->Bptr[0] |= (udev->dev_num) | ((ep->bEndpointAddress & 0xF) << ITD_EP_NUM_Pos); + itd->Bptr[1] |= ep->wMaxPacketSize; /* Maximum Packet Size */ + + if ((ep->bEndpointAddress & EP_ADDR_DIR_MASK) == EP_ADDR_DIR_IN) /* I/O */ + itd->Bptr[1] |= ITD_DIR_IN; + else + itd->Bptr[1] |= ITD_DIR_OUT; + + itd->Bptr[2] |= (ep->wMaxPacketSize + 1023) / 1024; /* Mult */ +} + +static void write_itd_micro_frame(UTR_T *utr, int fidx, iTD_T *itd, int mf) +{ + uint32_t buff_addr; + + buff_addr = (uint32_t)(utr->iso_buff[fidx]); /* xfer buffer start address of this frame */ + + itd->Transaction[mf] = ITD_STATUS_ACTIVE | /* Status */ + ((utr->iso_xlen[fidx] & 0xFFF) << ITD_XLEN_Pos) | /* Transaction Length */ + ((buff_addr & 0xFFFFF000) - (itd->buff_base & 0xFFFFF000)) | /* PG */ + (buff_addr & 0xFFF); /* Transaction offset */ +} + + +static void remove_iso_ep_from_list(ISO_EP_T *iso_ep) +{ + ISO_EP_T *p; + + if (iso_ep_list == iso_ep) + { + iso_ep_list = iso_ep->next; /* it's the first entry, remove it */ + return; + } + + p = iso_ep_list; /* find the previous entry of iso_ep */ + while (p->next != NULL) + { + if (p->next == iso_ep) + { + break; + } + p = p->next; + } + + if (p->next == NULL) + { + return; /* not found */ + } + p->next = iso_ep->next; /* remove iso_ep from list */ +} + + +static __inline void add_itd_to_iso_ep(ISO_EP_T *iso_ep, iTD_T *itd) +{ + iTD_T *p; + + itd->next = NULL; + + if (iso_ep->itd_list == NULL) + { + iso_ep->itd_list = itd; + return; + } + + /* + * Find the tail entry of iso_ep->itd_list + */ + p = iso_ep->itd_list; + while (p->next != NULL) + { + p = p->next; + } + p->next = itd; +} + +static int ehci_iso_xfer(UTR_T *utr) +{ + EP_INFO_T *ep = utr->ep; /* reference to isochronous endpoint */ + ISO_EP_T *iso_ep; /* software iso endpoint descriptor */ + iTD_T *itd, *itd_next, *itd_list = NULL; + int i, itd_cnt; + int trans_mask; /* bit mask of used xfer in an iTD */ + int fidx; /* index to the 8 iso frames of UTR */ + int interval; /* frame interval of iTD */ + + if (ep->hw_pipe != NULL) + { + iso_ep = (ISO_EP_T *)ep->hw_pipe; /* get reference of the isochronous endpoint */ + + if (utr->bIsoNewSched) + iso_ep->next_frame = (((_ehci->UFINDR + (EHCI_ISO_DELAY * 8)) & HSUSBH_UFINDR_FI_Msk) >> 3) & 0x3FF; + } + else + { + /* first time transfer of this iso endpoint */ + iso_ep = usbh_alloc_mem(sizeof(*iso_ep)); + if (iso_ep == NULL) + return USBH_ERR_MEMORY_OUT; + + memset(iso_ep, 0, sizeof(*iso_ep)); + iso_ep->ep = ep; + iso_ep->next_frame = (((_ehci->UFINDR + (EHCI_ISO_DELAY * 8)) & HSUSBH_UFINDR_FI_Msk) >> 3) & 0x3FF; + + ep->hw_pipe = iso_ep; + + /* + * Add this iso_ep into iso_ep_list + */ + DISABLE_EHCI_IRQ(); + iso_ep->next = iso_ep_list; + iso_ep_list = iso_ep; + ENABLE_EHCI_IRQ(); + } + + if (utr->udev->speed == SPEED_FULL) + return ehci_iso_split_xfer(utr, iso_ep); + + /*------------------------------------------------------------------------------------*/ + /* Allocate iTDs */ + /*------------------------------------------------------------------------------------*/ + + if (ep->bInterval < 2) /* transfer interval is 1 micro-frame */ + { + trans_mask = 0xFF; + itd_cnt = 1; /* required 1 iTD for one UTR */ + interval = 1; /* iTD frame interval of this endpoint */ + } + else if (ep->bInterval < 4) /* transfer interval is 2 micro-frames */ + { + trans_mask = 0x55; + itd_cnt = 2; /* required 2 iTDs for one UTR */ + interval = 1; /* iTD frame interval of this endpoint */ + } + else if (ep->bInterval < 8) /* transfer interval is 4 micro-frames */ + { + trans_mask = 0x44; + itd_cnt = 4; /* required 4 iTDs for one UTR */ + interval = 1; /* iTD frame interval of this endpoint */ + } + else if (ep->bInterval < 16) /* transfer interval is 8 micro-frames */ + { + trans_mask = 0x08; /* there's 1 transfer in one iTD */ + itd_cnt = 8; /* required 8 iTDs for one UTR */ + interval = 1; /* iTD frame interval of this endpoint */ + } + else if (ep->bInterval < 32) /* transfer interval is 16 micro-frames */ + { + trans_mask = 0x10; /* there's 1 transfer in one iTD */ + itd_cnt = 8; /* required 8 iTDs for one UTR */ + interval = 2; /* iTD frame interval of this endpoint */ + } + else if (ep->bInterval < 64) /* transfer interval is 32 micro-frames */ + { + trans_mask = 0x02; /* there's 1 transfer in one iTD */ + itd_cnt = 8; /* required 8 iTDs for one UTR */ + interval = 4; /* iTD frame interval of this endpoint */ + } + else /* transfer interval is 64 micro-frames */ + { + trans_mask = 0x04; /* there's 1 transfer in one iTD */ + itd_cnt = 8; /* required 8 iTDs for one UTR */ + interval = 8; /* iTD frame interval of this endpoint */ + } + + for (i = 0; i < itd_cnt; i++) /* allocate all iTDs required by UTR */ + { + itd = alloc_ehci_iTD(); + if (itd == NULL) + goto malloc_failed; + + if (itd_list == NULL) /* link all iTDs */ + { + itd_list = itd; + } + else + { + itd->next = itd_list; + itd_list = itd; + } + } + + utr->td_cnt = itd_cnt; + + /*------------------------------------------------------------------------------------*/ + /* Fill and link all iTDs */ + /*------------------------------------------------------------------------------------*/ + + utr->iso_sf = iso_ep->next_frame; + fidx = 0; /* index to UTR iso frmes (total IF_PER_UTR) */ + + for (itd = itd_list; (itd != NULL);) + { + if (fidx >= IF_PER_UTR) /* unlikely */ + { + USB_error("EHCI driver ITD bug!?\n"); + goto malloc_failed; + } + + itd->utr = utr; + itd->fidx = fidx; /* index to UTR's n'th IF_PER_UTR frame */ + itd->buff_base = (uint32_t)(utr->iso_buff[fidx]); /* iTD buffer base is buffer of the first UTR iso frame serviced by this iTD */ + itd->trans_mask = trans_mask; + + write_itd_info(utr, itd); + + for (i = 0; i < 8; i++) /* settle xfer into micro-frames */ + { + if (!(trans_mask & (0x1 << i))) + { + itd->Transaction[i] = 0; /* not accesed */ + continue; /* not scheduled micro-frame */ + } + + write_itd_micro_frame(utr, fidx, itd, i); + + fidx++; /* preceed to next UTR iso frame */ + + if (fidx == IF_PER_UTR) /* is the last scheduled micro-frame? */ + { + /* raise interrupt on completed */ + itd->Transaction[i] |= ITD_IOC; + break; + } + } + + itd_next = itd->next; /* remember the next itd */ + + // USB_debug("Link iTD 0x%x, %d\n", (int)itd, iso_ep->next_frame); + /* + * Link iTD to period frame list + */ + DISABLE_EHCI_IRQ(); + itd->sched_frnidx = iso_ep->next_frame; /* remember it for reclamation scan */ + add_itd_to_iso_ep(iso_ep, itd); /* add to software itd list */ + itd->Next_Link = _PFList[itd->sched_frnidx]; /* keep the next link */ + _PFList[itd->sched_frnidx] = ITD_HLNK_ITD(itd); + iso_ep->next_frame = (iso_ep->next_frame + interval) % FL_SIZE; + ENABLE_EHCI_IRQ(); + + itd = itd_next; + } + + _ehci->UCMDR |= HSUSBH_UCMDR_PSEN_Msk; /* periodic list enable */ + return 0; + +malloc_failed: + + while (itd_list != NULL) + { + itd = itd_list; + itd_list = itd->next; + free_ehci_iTD(itd); + } + return USBH_ERR_MEMORY_OUT; +} + +static __inline void add_sitd_to_iso_ep(ISO_EP_T *iso_ep, siTD_T *sitd) +{ + siTD_T *p; + + sitd->next = NULL; + + if (iso_ep->sitd_list == NULL) + { + iso_ep->sitd_list = sitd; + return; + } + + /* + * Find the tail entry of iso_ep->itd_list + */ + p = iso_ep->sitd_list; + while (p->next != NULL) + { + p = p->next; + } + p->next = sitd; +} + +static void write_sitd_info(UTR_T *utr, siTD_T *sitd) +{ + UDEV_T *udev = utr->udev; + EP_INFO_T *ep = utr->ep; /* reference to isochronous endpoint */ + uint32_t buff_page_addr; + int xlen = utr->iso_xlen[sitd->fidx]; + int scnt; + + sitd->Chrst = (udev->port_num << SITD_PORT_NUM_Pos) | + (udev->parent->iface->udev->dev_num << SITD_HUB_ADDR_Pos) | + ((ep->bEndpointAddress & 0xF) << SITD_EP_NUM_Pos) | + (udev->dev_num << SITD_DEV_ADDR_Pos); + + buff_page_addr = ((uint32_t)utr->iso_buff[sitd->fidx]) & 0xFFFFF000; + sitd->Bptr[0] = (uint32_t)(utr->iso_buff[sitd->fidx]); + sitd->Bptr[1] = buff_page_addr + 0x1000; + + scnt = (xlen + 187) / 188; + + if ((ep->bEndpointAddress & EP_ADDR_DIR_MASK) == EP_ADDR_DIR_IN) /* I/O */ + { + sitd->Chrst |= SITD_XFER_IN; + sitd->Sched = (1 << (scnt + 2)) - 1; + sitd->Sched = (sitd->Sched << 10) | 0x1; + //sitd->Sched <<= 1; + } + else + { + sitd->Chrst |= SITD_XFER_OUT; + sitd->Sched = sitd_OUT_Smask[scnt - 1]; + if (scnt > 1) + { + sitd->Bptr[1] |= (0x1 << 3); /* Transaction position (TP) 01b: Begin */ + } + sitd->Bptr[1] |= scnt; /* Transaction count (T-Count) */ + } + + if (sitd->fidx == IF_PER_UTR) + { + sitd->Sched |= SITD_IOC; + } + + sitd->StsCtrl = (xlen << SITD_XFER_CNT_Pos) | SITD_STATUS_ACTIVE; + + sitd->BackLink = SITD_LIST_END; +} + + +static void ehci_sitd_adjust_schedule(siTD_T *sitd) +{ + siTD_T *hlink = (siTD_T *)_PFList[sitd->sched_frnidx]; + uint32_t uframe_mask = 0x00; + + while (hlink && !HLINK_IS_TERMINATED(hlink) && HLINK_IS_SITD(hlink)) + { + hlink = SITD_PTR(hlink); + if (hlink != sitd) + { + if ((hlink->Chrst & SITD_XFER_IO_Msk) == SITD_XFER_IN) + { + uframe_mask |= (hlink->Sched & 0xFF); /* mark micro-frames used by IN S-mask */ + uframe_mask |= ((hlink->Sched >> 8) & 0xFF); /* mark micro-frames used by IN C-mask */ + } + else + { + uframe_mask |= (hlink->Sched & 0xFF); /* mark micro-frames used by OUT S-mask */ + } + } + hlink = SITD_PTR(hlink->Next_Link); + } + + uframe_mask = uframe_mask | (uframe_mask << 8); /* mark both S-mask and C-mask */ + + if (uframe_mask) + { + /* + * Shift afterward one micro-frame until no conflicts. + */ + while (1) + { + if (sitd->Sched & uframe_mask) + { + sitd->Sched = (sitd->Sched & 0xFFFF0000) | ((sitd->Sched << 1) & 0xFFFF); + } + else + { + break; /* no conflit, done. */ + } + } + } +} + + +static int ehci_iso_split_xfer(UTR_T *utr, ISO_EP_T *iso_ep) +{ + EP_INFO_T *ep = utr->ep; /* reference to isochronous endpoint */ + siTD_T *sitd, *sitd_next, *sitd_list = NULL; + int i; + int fidx; /* index to the 8 iso frames of UTR */ + + if (utr->udev->parent == NULL) + { + USB_error("siso xfer - parent lost!\n"); + return USBH_ERR_INVALID_PARAM; + } + + /*------------------------------------------------------------------------------------*/ + /* Allocate siTDs */ + /*------------------------------------------------------------------------------------*/ + for (i = 0; i < IF_PER_UTR; i++) /* allocate all siTDs required by UTR */ + { + sitd = alloc_ehci_siTD(); + if (sitd == NULL) + goto malloc_failed; + + if (sitd_list == NULL) /* link all siTDs */ + { + sitd_list = sitd; + } + else + { + sitd->next = sitd_list; + sitd_list = sitd; + } + } + + utr->td_cnt = IF_PER_UTR; + + /*------------------------------------------------------------------------------------*/ + /* Fill and link all siTDs */ + /*------------------------------------------------------------------------------------*/ + + utr->iso_sf = iso_ep->next_frame; + fidx = 0; /* index to UTR iso frmes (total IF_PER_UTR) */ + + for (sitd = sitd_list; (sitd != NULL); fidx++) + { + if (fidx >= IF_PER_UTR) /* unlikely */ + { + USB_error("EHCI driver siTD bug!?\n"); + goto malloc_failed; + } + + sitd->utr = utr; + sitd->fidx = fidx; /* index to UTR's n'th IF_PER_UTR frame */ + + write_sitd_info(utr, sitd); + + sitd_next = sitd->next; /* remember the next itd */ + + // USB_debug("Link iTD 0x%x, %d\n", (int)itd, iso_ep->next_frame); + /* + * Link iTD to period frame list + */ + sitd->sched_frnidx = iso_ep->next_frame; /* remember it for reclamation scan */ + DISABLE_EHCI_IRQ(); + ehci_sitd_adjust_schedule(sitd); + add_sitd_to_iso_ep(iso_ep, sitd); /* add to software itd list */ + sitd->Next_Link = _PFList[sitd->sched_frnidx];/* keep the next link */ + _PFList[sitd->sched_frnidx] = SITD_HLNK_SITD(sitd); + iso_ep->next_frame = (iso_ep->next_frame + ep->bInterval) % FL_SIZE; + ENABLE_EHCI_IRQ(); + + sitd = sitd_next; + } + + _ehci->UCMDR |= HSUSBH_UCMDR_PSEN_Msk; /* periodic list enable */ + return 0; + +malloc_failed: + + while (sitd_list != NULL) + { + sitd = sitd_list; + sitd_list = sitd->next; + free_ehci_siTD(sitd); + } + return USBH_ERR_MEMORY_OUT; +} + +/* + * If it's an isochronous endpoint, quit current transfer via UTR or hardware EP. + */ +static int ehci_quit_iso_xfer(UTR_T *utr, EP_INFO_T *ep) +{ + ISO_EP_T *iso_ep; + iTD_T *itd, *itd_next, *p; + uint32_t frnidx; + uint32_t now_frame; + + if (ep == NULL) + { + if (utr == NULL) + return USBH_ERR_NOT_FOUND; + + if (utr->ep == NULL) + return USBH_ERR_NOT_FOUND; + + ep = utr->ep; + } + + if ((ep->bmAttributes & EP_ATTR_TT_MASK) != EP_ATTR_TT_ISO) + return USBH_ERR_NOT_FOUND; /* not isochronous endpoint */ + + /*------------------------------------------------------------------------------------*/ + /* It's an iso endpoint. Remove it as required. */ + /*------------------------------------------------------------------------------------*/ + iso_ep = iso_ep_list; + while (iso_ep != NULL) /* Search all activated iso endpoints */ + { + if (iso_ep->ep == ep) + break; + iso_ep = iso_ep->next; + } + if (iso_ep == NULL) + return 0; /* should have been removed */ + + itd = iso_ep->itd_list; /* get the first iTD from iso_ep's iTD list */ + + while (itd != NULL) /* traverse all iTDs of itd list */ + { + itd_next = itd->next; /* remember the next iTD */ + utr = itd->utr; + + /*--------------------------------------------------------------------------------*/ + /* Remove this iTD from period frame list */ + /*--------------------------------------------------------------------------------*/ + frnidx = itd->sched_frnidx; + + /* + * Prevent to race with Host Controller. If the iTD to be removed is located in + * current or next frame, wait until HC passed through it. + */ + while (1) + { + now_frame = (_ehci->UFINDR >> 3) & 0x3FF; + if ((now_frame == frnidx) || (((now_frame + 1) % 1024) == frnidx)) + continue; + break; + } + + if (_PFList[frnidx] == ITD_HLNK_ITD(itd)) + { + /* is the first entry, just change to next */ + _PFList[frnidx] = itd->Next_Link; + } + else + { + p = ITD_PTR(_PFList[frnidx]); /* find the preceding iTD */ + while ((ITD_PTR(p->Next_Link) != itd) && (p != NULL)) + { + p = ITD_PTR(p->Next_Link); + } + + if (p == NULL) /* link list out of control! */ + { + USB_error("ehci_quit_iso_xfer - An iTD lost reference to periodic frame list! 0x%x on %d\n", (int)itd, frnidx); + } + else /* remove iTD from list */ + { + p->Next_Link = itd->Next_Link; + } + } + + utr->td_cnt--; + + if (utr->td_cnt == 0) /* All iTD of this UTR done */ + { + utr->bIsTransferDone = 1; + if (utr->func) + utr->func(utr); + utr->status = USBH_ERR_ABORT; + } + free_ehci_iTD(itd); + itd = itd_next; + } + + /* + * Remove iso_ep from iso_ep_list + */ + remove_iso_ep_from_list(iso_ep); + usbh_free_mem(iso_ep, sizeof(*iso_ep)); /* free this iso_ep */ + ep->hw_pipe = NULL; + + if (iso_ep_list == NULL) + _ehci->UCMDR &= ~HSUSBH_UCMDR_PSEN_Msk; + + return 0; +} + + +/// @endcond HIDDEN_SYMBOLS + +/*** (C) COPYRIGHT 2017 Nuvoton Technology Corp. ***/ diff --git a/bsp/nuvoton/libraries/ma35/UsbHostLib/src/_ohci.c_ b/bsp/nuvoton/libraries/ma35/UsbHostLib/src/_ohci.c_ new file mode 100644 index 0000000000..a551648248 --- /dev/null +++ b/bsp/nuvoton/libraries/ma35/UsbHostLib/src/_ohci.c_ @@ -0,0 +1,1283 @@ +/**************************************************************************//** + * @file ohci.c + * @version V1.10 + * @brief USB Host library OHCI (USB 1.1) host controller driver. + * + * @copyright (C) 2017 Nuvoton Technology Corp. All rights reserved. +*****************************************************************************/ + +/// @cond HIDDEN_SYMBOLS + +//#define TD_debug rt_kprintf +#define TD_debug(...) + +//#define ED_debug rt_kprintf +#define ED_debug(...) + + +#define PORT_CNT (_ohci->HcRhDescriptorA & 0xf) + +static uint8_t _hcca_mem[256] __attribute__((aligned(256))); + +static HCCA_T *_hcca; + +static ED_T *_Ied[6]; + + +static ED_T *ed_remove_list; + +#ifdef ENABLE_DEBUG_MSG +static void dump_ohci_regs(void); +#endif + +static void add_to_ED_remove_list(ED_T *ed) +{ + ED_T *p; + + ED_debug("add_to_ED_remove_list - 0x%x (0x%x)\n", (int)ed, ed->Info); + DISABLE_OHCI_IRQ(); + + /* check if this ED found in ed_remove_list */ + p = ed_remove_list; + while (p) + { + if (p == ed) + { + ENABLE_OHCI_IRQ(); /* This ED found in ed_remove_list */ + return; /* do nothing */ + } + p = p->next; + } + + ed->Info |= ED_SKIP; /* ask OHCI controller skip this ED */ + ed->next = ed_remove_list; + ed_remove_list = ed; /* insert to the head of ed_remove_list */ + ENABLE_OHCI_IRQ(); + _ohci->HcInterruptStatus = USBH_HcInterruptStatus_SF_Msk; + _ohci->HcInterruptEnable |= USBH_HcInterruptEnable_SF_Msk; + usbh_delay_ms(2); /* Full speed wait 2 ms is enough */ +} + +static int ohci_reset(void) +{ + /* Disable HC interrupts */ + _ohci->HcInterruptDisable = USBH_HcInterruptDisable_MIE_Msk; + + /* HC Reset requires max 10 ms delay */ + _ohci->HcControl = 0; + _ohci->HcCommandStatus = USBH_HcCommandStatus_HCR_Msk; + + usbh_delay_ms(10); + + /* Check if OHCI reset completed? */ + if ((_ohci->HcCommandStatus & USBH_HcCommandStatus_HCR_Msk) != 0) + { + USB_error("Error! - USB OHCI reset timed out!\n"); + return -1; + } + + _ohci->HcRhStatus = USBH_HcRhStatus_OCI_Msk | USBH_HcRhStatus_LPS_Msk; + + _ohci->HcControl = HCFS_RESET; + + usbh_delay_ms(10); + + /* Check if OHCI reset completed? */ + if ((_ohci->HcCommandStatus & USBH_HcCommandStatus_HCR_Msk) != 0) + { + USB_error("Error! - USB HC reset timed out!\n"); + return -1; + } + + return 0; +} + +static void init_hcca_int_table() +{ + ED_T *ed_p; + int i, idx, interval; + + memset(_hcca->int_table, 0, sizeof(_hcca->int_table)); + + for (i = 5; i >= 0; i--) /* interval = i^2 */ + { + _Ied[i] = alloc_ohci_ED(); + _Ied[i]->Info = ED_SKIP; + + interval = 0x1 << i; + + for (idx = interval - 1; idx < 32; idx += interval) + { + if (_hcca->int_table[idx] == 0) /* is empty list, insert directly */ + { + _hcca->int_table[idx] = (uint32_t)_Ied[i]; + } + else + { + ed_p = (ED_T *)_hcca->int_table[idx]; + + while (1) + { + if (ed_p == _Ied[i]) + break; /* already chained by previous visit */ + + if (ed_p->NextED == 0) /* reach end of list? */ + { + ed_p->NextED = (uint32_t)_Ied[i]; + break; + } + ed_p = (ED_T *)ed_p->NextED; + } + } + } + } +} + +static ED_T *get_int_tree_head_node(int interval) +{ + int i; + + for (i = 0; i < 5; i++) + { + interval >>= 1; + if (interval == 0) + return _Ied[i]; + } + return _Ied[5]; /* for interval >= 32 */ +} + +static int get_ohci_interval(int interval) +{ + int i, bInterval = 1; + + for (i = 0; i < 5; i++) + { + interval >>= 1; + if (interval == 0) + return bInterval; + bInterval *= 2; + } + return 32; /* for interval >= 32 */ +} + + +static int ohci_init(void) +{ + uint32_t fminterval; + volatile int i; + + _hcca = (HCCA_T *)((uint32_t)_hcca_mem | NON_CACHE_MASK); + + if (ohci_reset() < 0) + return -1; + + ed_remove_list = NULL; + + init_hcca_int_table(); + + /* Tell the controller where the control and bulk lists are + * The lists are empty now. */ + _ohci->HcControlHeadED = 0; /* control ED list head */ + _ohci->HcBulkHeadED = 0; /* bulk ED list head */ + + _ohci->HcHCCA = (uint32_t)_hcca; /* HCCA area */ + + /* periodic start 90% of frame interval */ + fminterval = 0x2edf; /* 11,999 */ + _ohci->HcPeriodicStart = (fminterval * 9) / 10; + + /* set FSLargestDataPacket, 10,104 for 0x2edf frame interval */ + fminterval |= ((((fminterval - 210) * 6) / 7) << 16); + _ohci->HcFmInterval = fminterval; + + _ohci->HcLSThreshold = 0x628; + + /* start controller operations */ + _ohci->HcControl = HCFS_OPER | (0x3 << USBH_HcControl_CBSR_Pos); + + if (_ohci->HcRhDescriptorA & USBH_HcRhDescriptorA_PSM_Msk) + { + /* is per-port powered */ + if (PORT_CNT == 1) + _ohci->HcRhDescriptorB = 0x20000; + else + _ohci->HcRhDescriptorB = 0x7E0000; + for (i = 0; i < PORT_CNT; i++) + _ohci->HcRhPortStatus[i] = USBH_HcRhPortStatus_PPS_Msk; + } + else + { + /* is global port powered */ + _ohci->HcRhDescriptorA = (_ohci->HcRhDescriptorA | (1<<9)) & ~USBH_HcRhDescriptorA_PSM_Msk; + _ohci->HcRhStatus = USBH_HcRhStatus_LPSC_Msk; + } + + _ohci->HcInterruptEnable = USBH_HcInterruptEnable_MIE_Msk | USBH_HcInterruptEnable_WDH_Msk | USBH_HcInterruptEnable_SF_Msk; + + /* POTPGT delay is bits 24-31, in 20 ms units. */ + usbh_delay_ms(20); + return 0; +} + +static void ohci_suspend(void) +{ + int i; + + /* set port suspend if connected */ + for (i = 0; i < PORT_CNT; i++) + { + if (_ohci->HcRhPortStatus[i] & 0x1) + _ohci->HcRhPortStatus[i] = 0x4; + } + + /* enable Device Remote Wakeup */ + _ohci->HcRhStatus |= USBH_HcRhStatus_DRWE_Msk; + + /* enable USBH RHSC interrupt for system wakeup */ + _ohci->HcInterruptEnable |= USBH_HcInterruptEnable_RHSC_Msk | USBH_HcInterruptEnable_RD_Msk; + + /* set Host Controller enter suspend state */ + _ohci->HcControl = (_ohci->HcControl & ~USBH_HcControl_HCFS_Msk) | (3 << USBH_HcControl_HCFS_Pos); +} + +static void ohci_resume(void) +{ + int i; + + _ohci->HcControl = (_ohci->HcControl & ~USBH_HcControl_HCFS_Msk) | (1 << USBH_HcControl_HCFS_Pos); + _ohci->HcControl = (_ohci->HcControl & ~USBH_HcControl_HCFS_Msk) | (2 << USBH_HcControl_HCFS_Pos); + + for (i = 0; i < PORT_CNT; i++) + { + if (_ohci->HcRhPortStatus[i] & 0x4) + _ohci->HcRhPortStatus[i] = 0x8; + } +} + +static void ohci_shutdown(void) +{ + ohci_suspend(); + // NVIC_DisableIRQ(USBH_IRQn); +#ifndef OHCI_PER_PORT_POWER + _ohci->HcRhStatus = USBH_HcRhStatus_LPS_Msk; +#endif +} + + +/* + * Quit current trasnfer via UTR or hardware EP. + */ +static int ohci_quit_xfer(UTR_T *utr, EP_INFO_T *ep) +{ + ED_T *ed; + + if (utr != NULL) + { + if (utr->ep == NULL) + return USBH_ERR_NOT_FOUND; + + ed = (ED_T *)(utr->ep->hw_pipe); + + if (!ed) + return USBH_ERR_NOT_FOUND; + + /* add the endpoint to remove list, it will be removed on the next start of frame */ + add_to_ED_remove_list(ed); + utr->ep->hw_pipe = NULL; + } + + if ((ep != NULL) && (ep->hw_pipe != NULL)) + { + ed = (ED_T *)(ep->hw_pipe); + /* add the endpoint to remove list, it will be removed on the next start of frame */ + add_to_ED_remove_list(ed); + ep->hw_pipe = NULL; + } + + return 0; +} + +static uint32_t ed_make_info(UDEV_T *udev, EP_INFO_T *ep) +{ + uint32_t info; + + if (ep == NULL) /* is a control endpoint */ + { + /* control endpoint direction is from TD */ + if (udev->descriptor.bMaxPacketSize0 == 0) /* is 0 if device descriptor still not obtained. */ + { + if (udev->speed == SPEED_LOW) /* give a default maximum packet size */ + udev->descriptor.bMaxPacketSize0 = 8; + else + udev->descriptor.bMaxPacketSize0 = 64; + } + info = (udev->descriptor.bMaxPacketSize0 << 16) /* Control endpoint Maximum Packet Size from device descriptor */ + | ED_DIR_BY_TD /* Direction (Get direction From TD) */ + | ED_FORMAT_GENERAL /* General format */ + | (0 << ED_CTRL_EN_Pos); /* Endpoint address 0 */ + } + else /* Other endpoint direction is from endpoint descriptor */ + { + info = (ep->wMaxPacketSize << 16); /* Maximum Packet Size from endpoint */ + + info |= ((ep->bEndpointAddress & 0xf) << ED_CTRL_EN_Pos); /* Endpoint Number */ + + if ((ep->bEndpointAddress & EP_ADDR_DIR_MASK) == EP_ADDR_DIR_IN) + info |= ED_DIR_IN; + else + info |= ED_DIR_OUT; + + if ((ep->bmAttributes & EP_ATTR_TT_MASK) == EP_ATTR_TT_ISO) + info |= ED_FORMAT_ISO; + else + info |= ED_FORMAT_GENERAL; + } + + info |= ((udev->speed == SPEED_LOW) ? ED_SPEED_LOW : ED_SPEED_FULL); /* Speed */ + info |= (udev->dev_num); /* Function Address */ + + return info; +} + +static void write_td(TD_T *td, uint32_t info, uint8_t *buff, uint32_t data_len) +{ + uint32_t baddr = ptr_to_u32(buff); + + td->Info = info; + td->CBP = (((baddr == 0) || !data_len) ? 0 : baddr); + td->BE = (((baddr == 0) || !data_len) ? 0 : baddr + data_len - 1); + td->buff_start = td->CBP; + // TD_debug("TD [0x%x]: 0x%x, 0x%x, 0x%x\n", (int)td, td->Info, td->CBP, td->BE); +} + +static int ohci_ctrl_xfer(UTR_T *utr) +{ + UDEV_T *udev; + ED_T *ed; + TD_T *td_setup, *td_data, *td_status; + uint32_t info; + + udev = utr->udev; + + /*------------------------------------------------------------------------------------*/ + /* Allocate ED and TDs */ + /*------------------------------------------------------------------------------------*/ + td_setup = alloc_ohci_TD(utr); + + if (utr->data_len > 0) + td_data = alloc_ohci_TD(utr); + else + td_data = NULL; + + td_status = alloc_ohci_TD(utr); + + if (td_status == NULL) + { + free_ohci_TD(td_setup); + if (utr->data_len > 0) + free_ohci_TD(td_data); + return USBH_ERR_MEMORY_OUT; + } + + /* Check if there's any transfer pending on this endpoint... */ + if (udev->ep0.hw_pipe == NULL) + { + ed = alloc_ohci_ED(); + if (ed == NULL) + { + free_ohci_TD(td_setup); + free_ohci_TD(td_status); + if (utr->data_len > 0) + free_ohci_TD(td_data); + return USBH_ERR_MEMORY_OUT; + } + } + else + ed = (ED_T *)udev->ep0.hw_pipe; + + /*------------------------------------------------------------------------------------*/ + /* prepare SETUP stage TD */ + /*------------------------------------------------------------------------------------*/ + info = TD_CC | TD_T_DATA0 | TD_TYPE_CTRL; + write_td(td_setup, info, (uint8_t *)&utr->setup, 8); + td_setup->ed = ed; + + /*------------------------------------------------------------------------------------*/ + /* prepare DATA stage TD */ + /*------------------------------------------------------------------------------------*/ + if (utr->data_len > 0) + { + if ((utr->setup.bmRequestType & 0x80) == REQ_TYPE_OUT) + info = (TD_CC | TD_R | TD_DP_OUT | TD_T_DATA1 | TD_TYPE_CTRL | TD_CTRL_DATA); + else + info = (TD_CC | TD_R | TD_DP_IN | TD_T_DATA1 | TD_TYPE_CTRL | TD_CTRL_DATA); + + write_td(td_data, info, utr->buff, utr->data_len); + td_data->ed = ed; + td_setup->NextTD = ptr_to_u32(td_data); + td_setup->next = td_data; + td_data->NextTD = ptr_to_u32(td_status); + td_data->next = td_status; + } + else + { + td_setup->NextTD = ptr_to_u32(td_status); + td_setup->next = td_status; + } + + /*------------------------------------------------------------------------------------*/ + /* prepare STATUS stage TD */ + /*------------------------------------------------------------------------------------*/ + ed->Info = ed_make_info(udev, NULL); + if ((utr->setup.bmRequestType & 0x80) == REQ_TYPE_OUT) + info = (TD_CC | TD_DP_IN | TD_T_DATA1 | TD_TYPE_CTRL); + else + info = (TD_CC | TD_DP_OUT | TD_T_DATA1 | TD_TYPE_CTRL); + + write_td(td_status, info, NULL, 0); + td_status->ed = ed; + td_status->NextTD = 0; + td_status->next = 0; + + /*------------------------------------------------------------------------------------*/ + /* prepare ED */ + /*------------------------------------------------------------------------------------*/ + ed->TailP = 0; + ed->HeadP = ptr_to_u32(td_setup); + ed->Info = ed_make_info(udev, NULL); + ed->NextED = 0; + + //TD_debug("TD SETUP [0x%x]: 0x%x, 0x%x, 0x%x, 0x%x\n", (int)td_setup, td_setup->Info, td_setup->CBP, td_setup->BE, td_setup->NextTD); + //if (td_data) + // TD_debug("TD DATA [0x%x]: 0x%x, 0x%x, 0x%x, 0x%x\n", (int)td_data, td_data->Info, td_data->CBP, td_data->BE, td_data->NextTD); + //TD_debug("TD STATUS [0x%x]: 0x%x, 0x%x, 0x%x, 0x%x\n", (int)td_status, td_status->Info, td_status->CBP, td_status->BE, td_status->NextTD); + ED_debug("Xfer ED 0x%x: 0x%x 0x%x 0x%x 0x%x\n", ptr_to_u32(ed), ed->Info, ed->TailP, ed->HeadP, ed->NextED); + + if (utr->data_len > 0) + utr->td_cnt = 3; + else + utr->td_cnt = 2; + + utr->ep = &udev->ep0; /* driver can find EP from UTR */ + udev->ep0.hw_pipe = (void *)ed; /* driver can find ED from EP */ + + /*------------------------------------------------------------------------------------*/ + /* Start transfer */ + /*------------------------------------------------------------------------------------*/ + DISABLE_OHCI_IRQ(); + _ohci->HcControlHeadED = ptr_to_u32(ed); /* Link ED to OHCI */ + _ohci->HcControl |= USBH_HcControl_CLE_Msk; /* enable control list */ + ENABLE_OHCI_IRQ(); + _ohci->HcCommandStatus = USBH_HcCommandStatus_CLF_Msk; /* start Control list */ + + return 0; +} + +static int ohci_bulk_xfer(UTR_T *utr) +{ + UDEV_T *udev = utr->udev; + EP_INFO_T *ep = utr->ep; + ED_T *ed; + TD_T *td, *td_p, *td_list = NULL; + uint32_t info; + uint32_t data_len, xfer_len; + int8_t bIsNewED = 0; + uint8_t *buff; + + /*------------------------------------------------------------------------------------*/ + /* Check if there's uncompleted transfer on this endpoint... */ + /* Prepare ED */ + /*------------------------------------------------------------------------------------*/ + info = ed_make_info(udev, ep); + + /* Check if there's any transfer pending on this endpoint... */ + ed = (ED_T *)_ohci->HcBulkHeadED; /* get the head of bulk endpoint list */ + while (ed != NULL) + { + if (ed->Info == info) /* have transfer of this EP not completed? */ + { + if ((ed->HeadP & 0xFFFFFFF0) != (ed->TailP & 0xFFFFFFF0)) + return USBH_ERR_OHCI_EP_BUSY; /* endpoint is busy */ + else + break; /* ED already there... */ + } + ed = (ED_T *)ed->NextED; + } + + if (ed == NULL) + { + bIsNewED = 1; + ed = alloc_ohci_ED(); /* allocate an Endpoint Descriptor */ + if (ed == NULL) + return USBH_ERR_MEMORY_OUT; + ed->Info = info; + ed->HeadP = 0; + ED_debug("Link BULK ED 0x%x: 0x%x 0x%x 0x%x 0x%x\n", (int)ed, ed->Info, ed->TailP, ed->HeadP, ed->NextED); + } + + ep->hw_pipe = (void *)ed; + + /*------------------------------------------------------------------------------------*/ + /* Prepare TDs */ + /*------------------------------------------------------------------------------------*/ + utr->td_cnt = 0; + data_len = utr->data_len; + buff = utr->buff; + + do + { + if ((ep->bEndpointAddress & EP_ADDR_DIR_MASK) == EP_ADDR_DIR_OUT) + info = (TD_CC | TD_R | TD_DP_OUT | TD_TYPE_BULK); + else + info = (TD_CC | TD_R | TD_DP_IN | TD_TYPE_BULK); + + info &= ~(1 << 25); /* Data toggle from ED toggleCarry bit */ + + if (data_len > 4096) /* maximum transfer length is 4K for each TD */ + xfer_len = 4096; + else + xfer_len = data_len; /* remaining data length < 4K */ + + td = alloc_ohci_TD(utr); /* allocate a TD */ + if (td == NULL) + goto mem_out; + /* fill this TD */ + write_td(td, info, buff, xfer_len); + td->ed = ed; + + utr->td_cnt++; /* increase TD count, for recalim counter */ + + buff += xfer_len; /* advanced buffer pointer */ + data_len -= xfer_len; + + /* chain to end of TD list */ + if (td_list == NULL) + { + td_list = td; + } + else + { + td_p = td_list; + while (td_p->NextTD != 0) + td_p = (TD_T *)td_p->NextTD; + td_p->NextTD = (uint32_t)td; + } + + } + while (data_len > 0); + + /*------------------------------------------------------------------------------------*/ + /* Start transfer */ + /*------------------------------------------------------------------------------------*/ + utr->status = 0; + DISABLE_OHCI_IRQ(); + ed->HeadP = (ed->HeadP & 0x2) | ptr_to_u32(td_list); /* keep toggleCarry bit */ + if (bIsNewED) + { + ed->HeadP = ptr_to_u32(td_list); + /* Link ED to OHCI Bulk List */ + ed->NextED = _ohci->HcBulkHeadED; + _ohci->HcBulkHeadED = ptr_to_u32(ed); + } + ENABLE_OHCI_IRQ(); + _ohci->HcControl |= USBH_HcControl_BLE_Msk; /* enable bulk list */ + _ohci->HcCommandStatus = USBH_HcCommandStatus_BLF_Msk; /* start bulk list */ + + return 0; + +mem_out: + while (td_list != NULL) + { + td = td_list; + td_list = (TD_T *)td_list->NextTD; + free_ohci_TD(td); + } + free_ohci_ED(ed); + return USBH_ERR_MEMORY_OUT; +} + +static int ohci_int_xfer(UTR_T *utr) +{ + UDEV_T *udev = utr->udev; + EP_INFO_T *ep = utr->ep; + ED_T *ed, *ied; + TD_T *td, *td_new; + uint32_t info; + int8_t bIsNewED = 0; + + if (utr->data_len > 64) /* USB 1.1 interrupt transfer maximum packet size is 64 */ + return USBH_ERR_INVALID_PARAM; + + td_new = alloc_ohci_TD(utr); /* allocate a TD for dummy TD */ + if (td_new == NULL) + return USBH_ERR_MEMORY_OUT; + + ied = get_int_tree_head_node(ep->bInterval); /* get head node of this interval */ + + /*------------------------------------------------------------------------------------*/ + /* Find if this ED was already in the list */ + /*------------------------------------------------------------------------------------*/ + info = ed_make_info(udev, ep); + ed = ied; + while (ed != NULL) + { + if (ed->Info == info) + break; /* Endpoint found */ + ed = (ED_T *)ed->NextED; + } + + if (ed == NULL) /* ED not found, create it */ + { + bIsNewED = 1; + ed = alloc_ohci_ED(); /* allocate an Endpoint Descriptor */ + if (ed == NULL) + return USBH_ERR_MEMORY_OUT; + ed->Info = info; + ed->HeadP = 0; + ed->bInterval = ep->bInterval; + + td = alloc_ohci_TD(NULL); /* allocate the initial dummy TD for ED */ + if (td == NULL) + { + free_ohci_ED(ed); + free_ohci_TD(td_new); + return USBH_ERR_MEMORY_OUT; + } + ed->HeadP = ptr_to_u32(td); /* Let both HeadP and TailP point to dummy TD */ + ed->TailP = ed->HeadP; + } + else + { + td = (TD_T *)(ed->TailP & ~0xf); /* TailP always point to the dummy TD */ + } + ep->hw_pipe = (void *)ed; + + /*------------------------------------------------------------------------------------*/ + /* Prepare TD */ + /*------------------------------------------------------------------------------------*/ + if ((ep->bEndpointAddress & EP_ADDR_DIR_MASK) == EP_ADDR_DIR_OUT) + info = (TD_CC | TD_R | TD_DP_OUT | TD_TYPE_INT); + else + info = (TD_CC | TD_R | TD_DP_IN | TD_TYPE_INT); + + /* Keep data toggle */ + info = (info & ~(1 << 25)) | (td->Info & (1 << 25)); + + /* fill this TD */ + write_td(td, info, utr->buff, utr->data_len); + td->ed = ed; + td->NextTD = ptr_to_u32(td_new); + td->utr = utr; + utr->td_cnt = 1; /* increase TD count, for recalim counter */ + utr->status = 0; + + /*------------------------------------------------------------------------------------*/ + /* Hook ED and TD list to HCCA interrupt table */ + /*------------------------------------------------------------------------------------*/ + DISABLE_OHCI_IRQ(); + + ed->TailP = ptr_to_u32(td_new); + if (bIsNewED) + { + /* Add to list of the same interval */ + ed->NextED = ied->NextED; + ied->NextED = ptr_to_u32(ed); + } + + ENABLE_OHCI_IRQ(); + + //printf("Link INT ED 0x%x: 0x%x 0x%x 0x%x 0x%x\n", (int)ed, ed->Info, ed->TailP, ed->HeadP, ed->NextED); + + _ohci->HcControl |= USBH_HcControl_PLE_Msk; /* periodic list enable */ + return 0; +} + +static int ohci_iso_xfer(UTR_T *utr) +{ + UDEV_T *udev = utr->udev; + EP_INFO_T *ep = utr->ep; + ED_T *ed, *ied; + TD_T *td, *td_list, *last_td; + int i; + uint32_t info; + uint32_t buff_addr; + int8_t bIsNewED = 0; + + ied = get_int_tree_head_node(ep->bInterval); /* get head node of this interval */ + + /*------------------------------------------------------------------------------------*/ + /* Find if this ED was already in the list */ + /*------------------------------------------------------------------------------------*/ + info = ed_make_info(udev, ep); + ed = ied; + while (ed != NULL) + { + if (ed->Info == info) + break; /* Endpoint found */ + ed = (ED_T *)ed->NextED; + } + + if (ed == NULL) /* ED not found, create it */ + { + bIsNewED = 1; + ed = alloc_ohci_ED(); /* allocate an Endpoint Descriptor */ + if (ed == NULL) + return USBH_ERR_MEMORY_OUT; + ed->Info = info; + ed->HeadP = 0; + ed->bInterval = ep->bInterval; + } + else + + ep->hw_pipe = (void *)ed; + + /*------------------------------------------------------------------------------------*/ + /* Prepare TDs */ + /*------------------------------------------------------------------------------------*/ + if (utr->bIsoNewSched) /* Is the starting of isochronous streaming? */ + ed->next_sf = _hcca->frame_no + OHCI_ISO_DELAY; + + utr->td_cnt = 0; + utr->iso_sf = ed->next_sf; + + last_td = NULL; + td_list = NULL; + + for (i = 0; i < IF_PER_UTR; i++) + { + utr->iso_status[i] = USBH_ERR_NOT_ACCESS1; + + td = alloc_ohci_TD(utr); /* allocate a TD */ + if (td == NULL) + goto mem_out; + /* fill this TD */ + buff_addr = ptr_to_u32(utr->iso_buff[i]); + td->Info = (TD_CC | TD_TYPE_ISO) | ed->next_sf; + ed->next_sf += get_ohci_interval(ed->bInterval); + td->CBP = buff_addr & ~0xFFF; + td->BE = buff_addr + utr->iso_xlen[i] - 1; + td->PSW[0] = 0xE000 | (buff_addr & 0xFFF); + + td->ed = ed; + utr->td_cnt++; /* increase TD count, for recalim counter */ + + /* chain to end of TD list */ + if (td_list == NULL) + td_list = td; + else + last_td->NextTD = ptr_to_u32(td); + + last_td = td; + }; + + /*------------------------------------------------------------------------------------*/ + /* Hook ED and TD list to HCCA interrupt table */ + /*------------------------------------------------------------------------------------*/ + utr->status = 0; + DISABLE_OHCI_IRQ(); + + if ((ed->HeadP & ~0x3) == 0) + ed->HeadP = (ed->HeadP & 0x2) | ptr_to_u32(td_list); /* keep toggleCarry bit */ + else + { + /* find the tail of TDs under this ED */ + td = (TD_T *)(ed->HeadP & ~0x3); + while (td->NextTD != 0) + { + td = (TD_T *)td->NextTD; + } + td->NextTD = (uint32_t)td_list; + } + + if (bIsNewED) + { + /* Add to list of the same interval */ + ed->NextED = ied->NextED; + ied->NextED = ptr_to_u32(ed); + } + + ENABLE_OHCI_IRQ(); + ED_debug("Link ISO ED 0x%x: 0x%x 0x%x 0x%x 0x%x\n", (int)ed, ed->Info, ed->TailP, ed->HeadP, ed->NextED); + _ohci->HcControl |= USBH_HcControl_PLE_Msk | USBH_HcControl_IE_Msk; /* enable periodic list and isochronous transfer */ + + return 0; + +mem_out: + while (td_list != NULL) + { + td = td_list; + td_list = (TD_T *)td_list->NextTD; + free_ohci_TD(td); + } + free_ohci_ED(ed); + return USBH_ERR_MEMORY_OUT; +} + +static UDEV_T * ohci_find_device_by_port(int port) +{ + UDEV_T *udev; + + udev = g_udev_list; + while (udev != NULL) + { + if ((udev->parent == NULL) && (udev->port_num == port) && + ((udev->speed == SPEED_LOW) || (udev->speed == SPEED_FULL))) + return udev; + udev = udev->next; + } + return NULL; +} + +static int ohci_rh_port_reset(int port) +{ + int retry; + int reset_time; + uint32_t t0; + + reset_time = usbh_tick_from_millisecond(PORT_RESET_TIME_MS); + + for (retry = 0; retry < PORT_RESET_RETRY; retry++) + { + _ohci->HcRhPortStatus[port] = USBH_HcRhPortStatus_PRS_Msk; + + t0 = usbh_get_ticks(); + while (usbh_get_ticks() - t0 < (reset_time) + 1) + { + /* + * If device is disconnected or port enabled, we can stop port reset. + */ + if (((_ohci->HcRhPortStatus[port] & USBH_HcRhPortStatus_CCS_Msk) == 0) || + ((_ohci->HcRhPortStatus[port] & (USBH_HcRhPortStatus_PES_Msk | USBH_HcRhPortStatus_CCS_Msk)) == (USBH_HcRhPortStatus_PES_Msk | USBH_HcRhPortStatus_CCS_Msk))) + goto port_reset_done; + } + reset_time += PORT_RESET_RETRY_INC_MS; + } + + USB_debug("OHCI port %d - port reset failed!\n", port + 1); + return USBH_ERR_PORT_RESET; + +port_reset_done: + if ((_ohci->HcRhPortStatus[port] & USBH_HcRhPortStatus_CCS_Msk) == 0) /* check again if device disconnected */ + { + _ohci->HcRhPortStatus[port] = USBH_HcRhPortStatus_CSC_Msk; /* clear CSC */ + return USBH_ERR_DISCONNECTED; + } + return USBH_OK; /* port reset success */ +} + +static int ohci_rh_polling(void) +{ + int i, change = 0; + UDEV_T *udev; + int ret; + + for (i = 0; i < OHCI_PORT_CNT; i++) + { + /* clear unwanted port change status */ + _ohci->HcRhPortStatus[i] = USBH_HcRhPortStatus_OCIC_Msk | USBH_HcRhPortStatus_PRSC_Msk | + USBH_HcRhPortStatus_PSSC_Msk | USBH_HcRhPortStatus_PESC_Msk; + + if ((_ohci->HcRhPortStatus[i] & USBH_HcRhPortStatus_CSC_Msk) == 0) + continue; + rt_kprintf("OHCI port%d status change: 0x%x\n", i + 1, _ohci->HcRhPortStatus[i]); + + /*--------------------------------------------------------------------------------*/ + /* connect status change */ + /*--------------------------------------------------------------------------------*/ + + _ohci->HcRhPortStatus[i] = USBH_HcRhPortStatus_CSC_Msk; /* clear CSC */ + + if (_ohci->HcRhPortStatus[i] & USBH_HcRhPortStatus_CCS_Msk) + { + /*----------------------------------------------------------------------------*/ + /* First of all, check if there's any previously connected device. */ + /*----------------------------------------------------------------------------*/ + while (1) + { + udev = ohci_find_device_by_port(i + 1); + if (udev == NULL) + break; + usbh_disconnect_device(udev); + } + + rt_kprintf("OHCI connect device.\n"); + + if (ohci_rh_port_reset(i) != USBH_OK) + continue; + + /* + * Port reset success... + */ + udev = alloc_device(); + if (udev == NULL) + continue; + + udev->parent = NULL; + udev->port_num = i + 1; + if (_ohci->HcRhPortStatus[i] & USBH_HcRhPortStatus_LSDA_Msk) + udev->speed = SPEED_LOW; + else + udev->speed = SPEED_FULL; + udev->hc_driver = &ohci_driver; + + ret = usbh_connect_device(udev); + if (ret < 0) + { + USB_error("connect_device error! [%d]\n", ret); + free_device(udev); + } + + change = 1; + } + else + { + /* + * Device disconnected + */ + rt_kprintf("OHCI disconnect device.\n"); + while (1) + { + udev = ohci_find_device_by_port(i + 1); + if (udev == NULL) + break; + usbh_disconnect_device(udev); + } + change = 1; + } + } + return change; +} + +static void td_done(TD_T *td) +{ + UTR_T *utr = td->utr; + uint32_t info; + int cc; + + info = td->Info; + + TD_debug("td_done: 0x%x, 0x%x, 0x%x, 0x%x, 0x%x\n", (int)td, td->Info, td->CBP, td->NextTD, td->BE); + + /* ISO ... drivers see per-TD length/status */ + if ((info & TD_TYPE_Msk) == TD_TYPE_ISO) + { + uint16_t sf; + int idx; + + sf = info & 0xFFFF; + idx = ((sf + 0x10000 - utr->iso_sf) & 0xFFFF) / get_ohci_interval(td->ed->bInterval); + if (idx >= IF_PER_UTR) + { + USB_error("ISO invalid index!! %d, %d\n", sf, utr->iso_sf); + goto td_out; + } + + cc = (td->PSW[0] >> 12) & 0xF; + if (cc == 0xF) /* this frame was not transferred */ + { + USB_debug("ISO F %d N/A!\n", sf); + utr->iso_status[idx] = USBH_ERR_SCH_OVERRUN; + goto td_out; + } + if ((cc != 0) && (cc != CC_DATA_UNDERRUN)) + { + utr->iso_status[idx] = USBH_ERR_CC_NO_ERR - cc; + goto td_out; + } + utr->iso_status[idx] = 0; + utr->iso_xlen[idx] = td->PSW[0] & 0x7FF; + } + else + { + cc = TD_CC_GET(info); + + /* short packet is fine */ + if ((cc != CC_NOERROR) && (cc != CC_DATA_UNDERRUN)) + { + USB_error("TD error, CC = 0x%x\n", cc); + if (cc == CC_STALL) + utr->status = USBH_ERR_STALL; + else + utr->status = USBH_ERR_TRANSFER; + } + + switch (info & TD_TYPE_Msk) + { + case TD_TYPE_CTRL: + if (info & TD_CTRL_DATA) + { + if (td->CBP == 0) + utr->xfer_len += td->BE - td->buff_start + 1; + else + utr->xfer_len += td->CBP - td->buff_start; + } + break; + + case TD_TYPE_BULK: + case TD_TYPE_INT: + if (td->CBP == 0) + utr->xfer_len += td->BE - td->buff_start + 1; + else + utr->xfer_len += td->CBP - td->buff_start; + break; + } + } + +td_out: + + utr->td_cnt--; + + /* If all TDs are done, call-back to requester. */ + if (utr->td_cnt == 0) + { + utr->bIsTransferDone = 1; + if (utr->func) + utr->func(utr); + } +} + +/* in IRQ context */ +static void remove_ed() +{ + ED_T *ed, *ed_p, *ied; + TD_T *td, *td_next; + UTR_T *utr; + int found; + + while (ed_remove_list != NULL) + { + ED_debug("Remove ED: 0x%x, %d\n", (int)ed_remove_list, ed_remove_list->bInterval); + ed_p = ed_remove_list; + found = 0; + + /*--------------------------------------------------------------------------------*/ + /* Remove endpoint from Control List if found */ + /*--------------------------------------------------------------------------------*/ + if ((ed_p->Info & ED_EP_ADDR_Msk) == 0) + { + if (_ohci->HcControlHeadED == ptr_to_u32(ed_p)) + { + _ohci->HcControlHeadED = ed_p->NextED; + found = 1; + } + else + { + ed = (ED_T *)_ohci->HcControlHeadED; + while (ed != NULL) + { + if (ed->NextED == ptr_to_u32(ed_p)) + { + ed->NextED = ed_p->NextED; + found = 1; + } + ed = (ED_T *)ed->NextED; + } + } + } + + /*--------------------------------------------------------------------------------*/ + /* Remove INT or ISO endpoint from HCCA interrupt table */ + /*--------------------------------------------------------------------------------*/ + else if (ed_p->bInterval > 0) + { + ied = get_int_tree_head_node(ed_p->bInterval); + + ed = ied; + while (ed != NULL) + { + if (ed->NextED == ptr_to_u32(ed_p)) + { + ed->NextED = ed_p->NextED; + found = 1; + break; + } + ed = (ED_T *)ed->NextED; + } + } + + /*--------------------------------------------------------------------------------*/ + /* Remove endpoint from Bulk List if found */ + /*--------------------------------------------------------------------------------*/ + else + { + if (_ohci->HcBulkHeadED == ptr_to_u32(ed_p)) + { + ed = (ED_T *)ed_p; + _ohci->HcBulkHeadED = ed_p->NextED; + found = 1; + } + else + { + ed = (ED_T *)_ohci->HcBulkHeadED; + while (ed != NULL) + { + if (ed->NextED == ptr_to_u32(ed_p)) + { + ed->NextED = ed_p->NextED; + found = 1; + } + ed = (ED_T *)ed->NextED; + } + } + } + + /*--------------------------------------------------------------------------------*/ + /* Remove and free all TDs under this endpoint */ + /*--------------------------------------------------------------------------------*/ + if (found) + { + td = (TD_T *)(ed_p->HeadP & ~0x3); + if (td != NULL) + { + while (td != NULL) + { + utr = td->utr; + td_next = (TD_T *)td->NextTD; + free_ohci_TD(td); + td = td_next; + + utr->td_cnt--; + if (utr->td_cnt == 0) + { + utr->status = USBH_ERR_ABORT; + utr->bIsTransferDone = 1; + if (utr->func) + utr->func(utr); + } + } + } + } + + /* + * Done. Remove this ED from [ed_remove_list] and free it. + */ + ed_remove_list = ed_p->next; + free_ohci_ED(ed_p); + } +} + + +//static irqreturn_t ohci_irq (struct usb_hcd *hcd) +void OHCI_IRQHandler(int vector, void *param) +{ + TD_T *td, *td_prev, *td_next; + uint32_t int_sts; + + int_sts = _ohci->HcInterruptStatus; + + //rt_kprintf("[%s]ohci int_sts = 0x%x\n", __func__, int_sts); + + if ((_ohci->HcInterruptEnable & USBH_HcInterruptEnable_SF_Msk) && + (int_sts & USBH_HcInterruptStatus_SF_Msk)) + { + int_sts &= ~USBH_HcInterruptStatus_SF_Msk; + + _ohci->HcInterruptDisable = USBH_HcInterruptDisable_SF_Msk; + remove_ed(); + _ohci->HcInterruptStatus = USBH_HcInterruptStatus_SF_Msk; + } + + if (int_sts & USBH_HcInterruptStatus_WDH_Msk) + { + int_sts &= ~USBH_HcInterruptStatus_WDH_Msk; + /* + * reverse done list + */ + td = (TD_T *)(_hcca->done_head & TD_ADDR_MASK); + _hcca->done_head = 0; + td_prev = NULL; + _ohci->HcInterruptStatus = USBH_HcInterruptStatus_WDH_Msk; + + while (td != NULL) + { + //TD_debug("Done list TD 0x%x => 0x%x\n", (int)td, (int)td->NextTD); + td_next = (TD_T *)(td->NextTD & TD_ADDR_MASK); + td->NextTD = ptr_to_u32(td_prev); + td_prev = td; + td = td_next; + } + td = td_prev; /* first TD of the reversed done list */ + + /* + * reclaim TDs + */ + while (td != NULL) + { + TD_debug("Reclaim TD 0x%x, next 0x%x\n", (int)td, td->NextTD); + td_next = (TD_T *)td->NextTD; + td_done(td); + free_ohci_TD(td); + td = td_next; + } + } + + if (int_sts & USBH_HcInterruptStatus_RHSC_Msk) + { + _ohci->HcInterruptDisable = USBH_HcInterruptDisable_RHSC_Msk; + } + + _ohci->HcInterruptStatus = int_sts; +} + +#ifdef ENABLE_DEBUG_MSG + +static void dump_ohci_int_table() +{ + int i; + ED_T *ed; + + for (i = 0; i < 32; i++) +// for (i = 0; i < 1; i++) + + { + USB_debug("%02d: ", i); + + ed = (ED_T *)_hcca->int_table[i]; + + while (ed != NULL) + { + USB_debug("0x%x (0x%x) => ", ptr_to_u32(ed), ed->HeadP); + ed = (ED_T *)ed->NextED; + } + rt_kprintf("0\n"); + } +} + +static void dump_ohci_regs() +{ + USB_debug("Dump OCHI registers: [0x%x]\n", ptr_to_u32(&_ohci->HcRevision)); + USB_debug(" HcRevision = 0x%x\n", _ohci->HcRevision); + USB_debug(" HcControl = 0x%x\n", _ohci->HcControl); + USB_debug(" HcCommandStatus = 0x%x\n", _ohci->HcCommandStatus); + USB_debug(" HcInterruptStatus = 0x%x\n", _ohci->HcInterruptStatus); + USB_debug(" HcInterruptEnable = 0x%x\n", _ohci->HcInterruptEnable); + USB_debug(" HcInterruptDisable = 0x%x\n", _ohci->HcInterruptDisable); + USB_debug(" HcHCCA = 0x%x\n", _ohci->HcHCCA); + USB_debug(" HcPeriodCurrentED = 0x%x\n", _ohci->HcPeriodCurrentED); + USB_debug(" HcControlHeadED = 0x%x\n", _ohci->HcControlHeadED); + USB_debug(" HcControlCurrentED = 0x%x\n", _ohci->HcControlCurrentED); + USB_debug(" HcBulkHeadED = 0x%x\n", _ohci->HcBulkHeadED); + USB_debug(" HcBulkCurrentED = 0x%x\n", _ohci->HcBulkCurrentED); + USB_debug(" HcDoneHead = 0x%x\n", _ohci->HcDoneHead); + USB_debug(" HcFmInterval = 0x%x\n", _ohci->HcFmInterval); + USB_debug(" HcFmRemaining = 0x%x\n", _ohci->HcFmRemaining); + USB_debug(" HcFmNumber = 0x%x\n", _ohci->HcFmNumber); + USB_debug(" HcPeriodicStart = 0x%x\n", _ohci->HcPeriodicStart); + USB_debug(" HcLSThreshold = 0x%x\n", _ohci->HcLSThreshold); + USB_debug(" HcRhDescriptorA = 0x%x\n", _ohci->HcRhDescriptorA); + USB_debug(" HcRhDescriptorB = 0x%x\n", _ohci->HcRhDescriptorB); + USB_debug(" HcRhStatus = 0x%x\n", _ohci->HcRhStatus); + USB_debug(" HcRhPortStatus0 = 0x%x\n", _ohci->HcRhPortStatus[0]); + USB_debug(" HcPhyControl = 0x%x\n", _ohci->HcPhyControl); +} + +static void dump_ohci_ports() +{ + USB_debug("_ohci port0=0x%x\n", _ohci->HcRhPortStatus[0]); +} + +#endif // ENABLE_DEBUG_MSG + +/// @endcond HIDDEN_SYMBOLS + +/*** (C) COPYRIGHT 2017 Nuvoton Technology Corp. ***/ diff --git a/bsp/nuvoton/libraries/ma35/UsbHostLib/src/ehci_0.c b/bsp/nuvoton/libraries/ma35/UsbHostLib/src/ehci_0.c new file mode 100644 index 0000000000..ffb1afe021 --- /dev/null +++ b/bsp/nuvoton/libraries/ma35/UsbHostLib/src/ehci_0.c @@ -0,0 +1,43 @@ +/**************************************************************************//** + * @file ehci_0.c + * @version V1.10 + * @brief USB Host library EHCI (USB 2.0) host controller driver. + * + * @copyright (C) 2017 Nuvoton Technology Corp. All rights reserved. +*****************************************************************************/ + +#include +#include +#include + +#include "usb.h" +#include "hub.h" +#include "ehci.h" + +#define _ehci _ehci0 +#define ehci_driver ehci0_driver + +#define EHCI_IRQHandler EHCI0_IRQHandler + +//static uint16_t port_mask = 0x0001; +static ISO_EP_T *iso_ep_list; /* list of activated isochronous pipes */ + +#include "_ehci.c_" +#include "_ehci_iso.c_" + +HC_DRV_T ehci0_driver = +{ + ehci_init, /* init */ + ehci_shutdown, /* shutdown */ + ehci_suspend, /* suspend */ + ehci_resume, /* resume */ + ehci_ctrl_xfer, /* ctrl_xfer */ + ehci_bulk_xfer, /* bulk_xfer */ + ehci_int_xfer, /* int_xfer */ + ehci_iso_xfer, /* iso_xfer */ + ehci_quit_xfer, /* quit_xfer */ + ehci_rh_port_reset, /* rthub_port_reset */ + ehci_rh_polling, /* rthub_polling */ +}; + + diff --git a/bsp/nuvoton/libraries/ma35/UsbHostLib/src/ehci_1.c b/bsp/nuvoton/libraries/ma35/UsbHostLib/src/ehci_1.c new file mode 100644 index 0000000000..bd6343d903 --- /dev/null +++ b/bsp/nuvoton/libraries/ma35/UsbHostLib/src/ehci_1.c @@ -0,0 +1,43 @@ +/**************************************************************************//** + * @file ehci_0.c + * @version V1.10 + * @brief USB Host library EHCI (USB 2.0) host controller driver. + * + * @copyright (C) 2017 Nuvoton Technology Corp. All rights reserved. +*****************************************************************************/ + +#include +#include +#include + +#include "usb.h" +#include "hub.h" +#include "ehci.h" + +#define _ehci _ehci1 +#define ehci_driver ehci1_driver + +#define EHCI_IRQHandler EHCI1_IRQHandler + +//static uint16_t port_mask = 0x0002; +static ISO_EP_T *iso_ep_list; /* list of activated isochronous pipes */ + +#include "_ehci.c_" +#include "_ehci_iso.c_" + +HC_DRV_T ehci1_driver = +{ + ehci_init, /* init */ + ehci_shutdown, /* shutdown */ + ehci_suspend, /* suspend */ + ehci_resume, /* resume */ + ehci_ctrl_xfer, /* ctrl_xfer */ + ehci_bulk_xfer, /* bulk_xfer */ + ehci_int_xfer, /* int_xfer */ + ehci_iso_xfer, /* iso_xfer */ + ehci_quit_xfer, /* quit_xfer */ + ehci_rh_port_reset, /* rthub_port_reset */ + ehci_rh_polling, /* rthub_polling */ +}; + + diff --git a/bsp/nuvoton/libraries/ma35/UsbHostLib/src/mem_alloc.c b/bsp/nuvoton/libraries/ma35/UsbHostLib/src/mem_alloc.c new file mode 100644 index 0000000000..75a7b60e38 --- /dev/null +++ b/bsp/nuvoton/libraries/ma35/UsbHostLib/src/mem_alloc.c @@ -0,0 +1,538 @@ +/**************************************************************************//** + * @file mem_alloc.c + * @version V1.10 + * @brief USB host library memory allocation functions. + * + * @note + * SPDX-License-Identifier: Apache-2.0 + * Copyright (C) 2018 Nuvoton Technology Corp. All rights reserved. +*****************************************************************************/ + +#include +#include +#include + +#include "usb.h" + + +/// @cond HIDDEN_SYMBOLS + +//#define MEM_DEBUG + +#ifdef MEM_DEBUG + #define mem_debug rt_kprintf +#else + #define mem_debug(...) +#endif + +#ifdef __ICCARM__ + #pragma data_alignment=1024 + uint8_t _mem_pool_buff[MEM_POOL_UNIT_NUM][MEM_POOL_UNIT_SIZE]; +#else + uint8_t _mem_pool_buff[MEM_POOL_UNIT_NUM][MEM_POOL_UNIT_SIZE] __attribute__((aligned(1024))); +#endif + +static uint8_t *_mem_pool[MEM_POOL_UNIT_NUM]; +static uint8_t _unit_used[MEM_POOL_UNIT_NUM]; + +static volatile int _usbh_mem_used; +static volatile int _usbh_max_mem_used; +static volatile int _mem_pool_used; + + +UDEV_T *g_udev_list; + +uint8_t _dev_addr_pool[128]; +static volatile int _device_addr; + +static int _sidx = 0;; + +/*--------------------------------------------------------------------------*/ +/* Memory alloc/free recording */ +/*--------------------------------------------------------------------------*/ + +void usbh_memory_init(void) +{ + int i; + + if (sizeof(TD_T) > MEM_POOL_UNIT_SIZE) + { + USB_error("TD_T - MEM_POOL_UNIT_SIZE too small!\n"); + while (1); + } + + if (sizeof(ED_T) > MEM_POOL_UNIT_SIZE) + { + USB_error("ED_T - MEM_POOL_UNIT_SIZE too small!\n"); + while (1); + } + + for (i = 0; i < MEM_POOL_UNIT_NUM; i++) + { + _unit_used[i] = 0; + _mem_pool[i] = (uint8_t *)((uint32_t)&_mem_pool_buff[i] | NON_CACHE_MASK); + } + + _usbh_mem_used = 0L; + _usbh_max_mem_used = 0L; + + _mem_pool_used = 0; + _sidx = 0; + + g_udev_list = NULL; + + memset(_dev_addr_pool, 0, sizeof(_dev_addr_pool)); + _device_addr = 1; + + USB_InitializeMemoryPool(); +} + +uint32_t usbh_memory_used(void) +{ + mem_debug("USB static memory: %d/%d, heap used: %d\n", _mem_pool_used, MEM_POOL_UNIT_NUM, _usbh_mem_used); + return _usbh_mem_used; +} + +static void memory_counter(int size) +{ + _usbh_mem_used += size; + if (_usbh_mem_used > _usbh_max_mem_used) + _usbh_max_mem_used = _usbh_mem_used; +} + +void *usbh_alloc_mem(int size) +{ + void *p; + + p = USB_malloc(size, 16); + if (p == NULL) + { + USB_error("usbh_alloc_mem failed! %d\n", size); + return NULL; + } + + memset(p, 0, size); + memory_counter(size); + return p; +} + +void usbh_free_mem(void *p, int size) +{ + USB_free(p); + memory_counter(0 - size); +} + + +/*--------------------------------------------------------------------------*/ +/* USB device allocate/free */ +/*--------------------------------------------------------------------------*/ + +UDEV_T *alloc_device(void) +{ + UDEV_T *udev; + + udev = (UDEV_T *)USB_malloc(sizeof(*udev), 16); + if (udev == NULL) + { + USB_error("alloc_device failed!\n"); + return NULL; + } + + memset(udev, 0, sizeof(*udev)); + memory_counter(sizeof(*udev)); + udev->cur_conf = -1; /* must! used to identify the first SET CONFIGURATION */ + udev->next = g_udev_list; /* chain to global device list */ + g_udev_list = udev; + return udev; +} + +void free_device(UDEV_T *udev) +{ + UDEV_T *d; + + if (udev == NULL) + return; + + if (udev->cfd_buff != NULL) + usbh_free_mem(udev->cfd_buff, MAX_DESC_BUFF_SIZE); + + /* + * Remove it from the global device list + */ + if (g_udev_list == udev) + { + g_udev_list = g_udev_list->next; + } + else + { + d = g_udev_list; + while (d != NULL) + { + if (d->next == udev) + { + d->next = udev->next; + break; + } + d = d->next; + } + } + USB_free(udev); + memory_counter(-sizeof(*udev)); +} + +int alloc_dev_address(void) +{ + _device_addr++; + + if (_device_addr >= 128) + _device_addr = 1; + + while (1) + { + if (_dev_addr_pool[_device_addr] == 0) + { + _dev_addr_pool[_device_addr] = 1; + return _device_addr; + } + _device_addr++; + if (_device_addr >= 128) + _device_addr = 1; + } +} + +void free_dev_address(int dev_addr) +{ + if (dev_addr < 128) + _dev_addr_pool[dev_addr] = 0; +} + +/*--------------------------------------------------------------------------*/ +/* UTR (USB Transfer Request) allocate/free */ +/*--------------------------------------------------------------------------*/ + +UTR_T *alloc_utr(UDEV_T *udev) +{ +#if 0 + UTR_T *utr, *utr_noncache; + + utr = (UTR_T *)USB_malloc(sizeof(*utr), 16); + if (utr == NULL) + { + USB_error("alloc_utr failed!\n"); + return NULL; + } + + utr_noncache = (UTR_T *)((uint32_t)utr | NONCACHEABLE); + + memory_counter(sizeof(*utr)); + memset(utr_noncache, 0, sizeof(*utr)); + utr_noncache->udev = udev; + mem_debug("[ALLOC] [UTR] - 0x%x\n", (int)utr_noncache); + return utr_noncache; +#else + UTR_T *utr; + + utr = (UTR_T *)USB_malloc(sizeof(*utr), 16); + if (utr == NULL) + { + USB_error("alloc_utr failed!\n"); + return NULL; + } + + memory_counter(sizeof(*utr)); + memset(utr, 0, sizeof(*utr)); + utr->udev = udev; + mem_debug("[ALLOC] [UTR] - 0x%x\n", (int)utr_noncache); + return utr; +#endif +} + +void free_utr(UTR_T *utr) +{ + if (utr == NULL) + return; + + mem_debug("[FREE] [UTR] - 0x%x\n", (int)utr); + +#if 0 + if ((uint32_t)utr & NONCACHEABLE) + utr = (UTR_T *)((uint32_t)utr & ~NONCACHEABLE); +#endif + + USB_free(utr); + memory_counter(0 - (int)sizeof(*utr)); +} + +/*--------------------------------------------------------------------------*/ +/* OHCI ED allocate/free */ +/*--------------------------------------------------------------------------*/ + +ED_T *alloc_ohci_ED(void) +{ + int i; + ED_T *ed; + + for (i = 0; i < MEM_POOL_UNIT_NUM; i++) + { + if (_unit_used[i] == 0) + { + _unit_used[i] = 1; + _mem_pool_used++; + ed = (ED_T *)_mem_pool[i]; + memset(ed, 0, sizeof(*ed)); + mem_debug("[ALLOC] [ED] - 0x%x\n", (int)ed); + return ed; + } + } + USB_error("alloc_ohci_ED failed!\n"); + return NULL; +} + +void free_ohci_ED(ED_T *ed) +{ + int i; + + for (i = 0; i < MEM_POOL_UNIT_NUM; i++) + { + if ((uint32_t)_mem_pool[i] == (uint32_t)ed) + { + mem_debug("[FREE] [ED] - 0x%x\n", (int)ed); + _unit_used[i] = 0; + _mem_pool_used--; + return; + } + } + USB_debug("free_ohci_ED - not found! (ignored in case of multiple UTR)\n"); +} + +/*--------------------------------------------------------------------------*/ +/* OHCI TD allocate/free */ +/*--------------------------------------------------------------------------*/ +TD_T *alloc_ohci_TD(UTR_T *utr) +{ + int i; + TD_T *td; + + for (i = 0; i < MEM_POOL_UNIT_NUM; i++) + { + if (_unit_used[i] == 0) + { + _unit_used[i] = 1; + _mem_pool_used++; + td = (TD_T *)_mem_pool[i]; + + memset(td, 0, sizeof(*td)); + td->utr = utr; + mem_debug("[ALLOC] [TD] - 0x%x\n", (int)td); + return td; + } + } + USB_error("alloc_ohci_TD failed!\n"); + return NULL; +} + +void free_ohci_TD(TD_T *td) +{ + int i; + + for (i = 0; i < MEM_POOL_UNIT_NUM; i++) + { + if ((uint32_t)_mem_pool[i] == (uint32_t)td) + { + mem_debug("[FREE] [TD] - 0x%x\n", (int)td); + _unit_used[i] = 0; + _mem_pool_used--; + return; + } + } + USB_error("free_ohci_TD - not found!\n"); +} + +/*--------------------------------------------------------------------------*/ +/* EHCI QH allocate/free */ +/*--------------------------------------------------------------------------*/ +QH_T *alloc_ehci_QH(void) +{ + int i; + QH_T *qh = NULL; + + for (i = (_sidx + 1) % MEM_POOL_UNIT_NUM; i != _sidx; i = (i + 1) % MEM_POOL_UNIT_NUM) + { + if (_unit_used[i] == 0) + { + _unit_used[i] = 1; + _sidx = i; + _mem_pool_used++; + qh = (QH_T *)_mem_pool[i]; + memset(qh, 0, sizeof(*qh)); + mem_debug("[ALLOC] [QH] - 0x%x\n", (int)qh); + break; + } + } + if (qh == NULL) + { + USB_error("alloc_ehci_QH failed!\n"); + return NULL; + } + qh->Curr_qTD = QTD_LIST_END; + qh->OL_Next_qTD = QTD_LIST_END; + qh->OL_Alt_Next_qTD = QTD_LIST_END; + qh->OL_Token = QTD_STS_HALT; + return qh; +} + +void free_ehci_QH(QH_T *qh) +{ + int i; + + for (i = 0; i < MEM_POOL_UNIT_NUM; i++) + { + if ((uint32_t)_mem_pool[i] == (uint32_t)qh) + { + mem_debug("[FREE] [QH] - 0x%x\n", (int)qh); + _unit_used[i] = 0; + _mem_pool_used--; + return; + } + } + USB_debug("free_ehci_QH - not found! (ignored in case of multiple UTR)\n"); +} + +/*--------------------------------------------------------------------------*/ +/* EHCI qTD allocate/free */ +/*--------------------------------------------------------------------------*/ +qTD_T *alloc_ehci_qTD(UTR_T *utr) +{ + int i; + qTD_T *qtd; + + for (i = (_sidx + 1) % MEM_POOL_UNIT_NUM; i != _sidx; i = (i + 1) % MEM_POOL_UNIT_NUM) + { + if (_unit_used[i] == 0) + { + _unit_used[i] = 1; + _sidx = i; + _mem_pool_used++; + qtd = (qTD_T *)_mem_pool[i]; + + memset(qtd, 0, sizeof(*qtd)); + qtd->Next_qTD = QTD_LIST_END; + qtd->Alt_Next_qTD = QTD_LIST_END; + qtd->Token = 0x1197B7F; // QTD_STS_HALT; visit_qtd() will not remove a qTD with this mark. It means the qTD still not ready for transfer. + qtd->utr = utr; + mem_debug("[ALLOC] [qTD] - 0x%x\n", (int)qtd); + return qtd; + } + } + USB_error("alloc_ehci_qTD failed!\n"); + return NULL; +} + +void free_ehci_qTD(qTD_T *qtd) +{ + int i; + + for (i = 0; i < MEM_POOL_UNIT_NUM; i++) + { + if ((uint32_t)_mem_pool[i] == (uint32_t)qtd) + { + mem_debug("[FREE] [qTD] - 0x%x\n", (int)qtd); + _unit_used[i] = 0; + _mem_pool_used--; + return; + } + } + USB_error("free_ehci_qTD 0x%x - not found!\n", (int)qtd); +} + +/*--------------------------------------------------------------------------*/ +/* EHCI iTD allocate/free */ +/*--------------------------------------------------------------------------*/ +iTD_T *alloc_ehci_iTD(void) +{ + int i; + iTD_T *itd; + + for (i = (_sidx + 1) % MEM_POOL_UNIT_NUM; i != _sidx; i = (i + 1) % MEM_POOL_UNIT_NUM) + { + if (i + 2 >= MEM_POOL_UNIT_NUM) + continue; + + if ((_unit_used[i] == 0) && (_unit_used[i + 1] == 0)) + { + _unit_used[i] = _unit_used[i + 1] = 1; + _sidx = i + 1; + _mem_pool_used += 2; + itd = (iTD_T *)_mem_pool[i]; + memset(itd, 0, sizeof(*itd)); + mem_debug("[ALLOC] [iTD] - 0x%x\n", (int)itd); + return itd; + } + } + USB_error("alloc_ehci_iTD failed!\n"); + return NULL; +} + +void free_ehci_iTD(iTD_T *itd) +{ + int i; + + for (i = 0; i + 1 < MEM_POOL_UNIT_NUM; i++) + { + if ((uint32_t)_mem_pool[i] == (uint32_t)itd) + { + mem_debug("[FREE] [iTD] - 0x%x\n", (int)itd); + _unit_used[i] = _unit_used[i + 1] = 0; + _mem_pool_used -= 2; + return; + } + } + USB_error("free_ehci_iTD 0x%x - not found!\n", (int)itd); +} + +/*--------------------------------------------------------------------------*/ +/* EHCI iTD allocate/free */ +/*--------------------------------------------------------------------------*/ +siTD_T *alloc_ehci_siTD(void) +{ + int i; + siTD_T *sitd; + + for (i = (_sidx + 1) % MEM_POOL_UNIT_NUM; i != _sidx; i = (i + 1) % MEM_POOL_UNIT_NUM) + { + if (_unit_used[i] == 0) + { + _unit_used[i] = 1; + _sidx = i; + _mem_pool_used ++; + sitd = (siTD_T *)_mem_pool[i]; + memset(sitd, 0, sizeof(*sitd)); + mem_debug("[ALLOC] [siTD] - 0x%x\n", (int)sitd); + return sitd; + } + } + USB_error("alloc_ehci_siTD failed!\n"); + return NULL; +} + +void free_ehci_siTD(siTD_T *sitd) +{ + int i; + + for (i = 0; i < MEM_POOL_UNIT_NUM; i++) + { + if ((uint32_t)_mem_pool[i] == (uint32_t)sitd) + { + mem_debug("[FREE] [siTD] - 0x%x\n", (int)sitd); + _unit_used[i] = 0; + _mem_pool_used--; + return; + } + } + USB_error("free_ehci_siTD 0x%x - not found!\n", (int)sitd); +} + +/// @endcond HIDDEN_SYMBOLS + +/*** (C) COPYRIGHT 2018 Nuvoton Technology Corp. ***/ + diff --git a/bsp/nuvoton/libraries/ma35/UsbHostLib/src/ohci_0.c b/bsp/nuvoton/libraries/ma35/UsbHostLib/src/ohci_0.c new file mode 100644 index 0000000000..40875bb99d --- /dev/null +++ b/bsp/nuvoton/libraries/ma35/UsbHostLib/src/ohci_0.c @@ -0,0 +1,41 @@ +/**************************************************************************//** + * @file ohci.c + * @version V1.10 + * @brief USB Host library OHCI (USB 1.1) host controller driver. + * + * @copyright (C) 2017 Nuvoton Technology Corp. All rights reserved. +*****************************************************************************/ + +#include +#include +#include + +#include "usb.h" +#include "hub.h" +#include "ohci.h" + +/// @cond HIDDEN_SYMBOLS + +#define _ohci _ohci0 +#define ohci_driver ohci0_driver + +#define OHCI_IRQHandler OHCI0_IRQHandler + +#include "_ohci.c_" + +HC_DRV_T ohci0_driver = +{ + ohci_init, /* init */ + ohci_shutdown, /* shutdown */ + ohci_suspend, /* suspend */ + ohci_resume, /* resume */ + ohci_ctrl_xfer, /* ctrl_xfer */ + ohci_bulk_xfer, /* bulk_xfer */ + ohci_int_xfer, /* int_xfer */ + ohci_iso_xfer, /* iso_xfer */ + ohci_quit_xfer, /* quit_xfer */ + ohci_rh_port_reset, /* rthub_port_reset */ + ohci_rh_polling, /* rthub_polling */ +}; + + diff --git a/bsp/nuvoton/libraries/ma35/UsbHostLib/src/ohci_1.c b/bsp/nuvoton/libraries/ma35/UsbHostLib/src/ohci_1.c new file mode 100644 index 0000000000..2dfb1d08ad --- /dev/null +++ b/bsp/nuvoton/libraries/ma35/UsbHostLib/src/ohci_1.c @@ -0,0 +1,41 @@ +/**************************************************************************//** + * @file ohci.c + * @version V1.10 + * @brief USB Host library OHCI (USB 1.1) host controller driver. + * + * @copyright (C) 2017 Nuvoton Technology Corp. All rights reserved. +*****************************************************************************/ + +#include +#include +#include + +#include "usb.h" +#include "hub.h" +#include "ohci.h" + +/// @cond HIDDEN_SYMBOLS + +#define _ohci _ohci1 +#define ohci_driver ohci1_driver + +#define OHCI_IRQHandler OHCI1_IRQHandler + +#include "_ohci.c_" + +HC_DRV_T ohci1_driver = +{ + ohci_init, /* init */ + ohci_shutdown, /* shutdown */ + ohci_suspend, /* suspend */ + ohci_resume, /* resume */ + ohci_ctrl_xfer, /* ctrl_xfer */ + ohci_bulk_xfer, /* bulk_xfer */ + ohci_int_xfer, /* int_xfer */ + ohci_iso_xfer, /* iso_xfer */ + ohci_quit_xfer, /* quit_xfer */ + ohci_rh_port_reset, /* rthub_port_reset */ + ohci_rh_polling, /* rthub_polling */ +}; + + diff --git a/bsp/nuvoton/libraries/ma35/UsbHostLib/src/support.c b/bsp/nuvoton/libraries/ma35/UsbHostLib/src/support.c new file mode 100644 index 0000000000..7338f41ab7 --- /dev/null +++ b/bsp/nuvoton/libraries/ma35/UsbHostLib/src/support.c @@ -0,0 +1,274 @@ +/**************************************************************************//** + * @file support.c + * @version V1.10 + * $Revision: 11 $ + * $Date: 14/10/03 1:54p $ + * @brief Functions to support USB host driver. + * + * @note + * SPDX-License-Identifier: Apache-2.0 + * Copyright (C) 2018 Nuvoton Technology Corp. All rights reserved. +*****************************************************************************/ + +#include +#include +#include + +#include "usb.h" + +/// @cond HIDDEN_SYMBOLS + + +#define USB_MEMORY_POOL_SIZE (32*1024) +#define USB_MEM_BLOCK_SIZE 128 + +#define BOUNDARY_WORD 4 + + +static uint32_t _FreeMemorySize; +uint32_t _AllocatedMemorySize; + + +#define USB_MEM_ALLOC_MAGIC 0x19685788 /* magic number in leading block */ + +typedef struct USB_mhdr +{ + uint32_t flag; /* 0:free, 1:allocated, 0x3:first block */ + uint32_t bcnt; /* if allocated, the block count of allocated memory block */ + uint32_t magic; + uint32_t reserved; +} USB_MHDR_T; + +uint8_t _USBMemoryPool[USB_MEMORY_POOL_SIZE] __attribute__((aligned(USB_MEM_BLOCK_SIZE))); + + +static USB_MHDR_T *_pCurrent; +uint32_t *_USB_pCurrent = (uint32_t *) &_pCurrent; + +static uint32_t _MemoryPoolBase, _MemoryPoolEnd; + + +void USB_InitializeMemoryPool() +{ + _MemoryPoolBase = (uint32_t)&_USBMemoryPool[0] | NON_CACHE_MASK; + _MemoryPoolEnd = _MemoryPoolBase + USB_MEMORY_POOL_SIZE; + _FreeMemorySize = _MemoryPoolEnd - _MemoryPoolBase; + _AllocatedMemorySize = 0; + _pCurrent = (USB_MHDR_T *)_MemoryPoolBase; + memset((char *)_MemoryPoolBase, 0, _FreeMemorySize); +} + + +int USB_available_memory() +{ + return _FreeMemorySize; +} + + +int USB_allocated_memory() +{ + return _AllocatedMemorySize; +} + + +void *USB_malloc(int wanted_size, int boundary) +{ + USB_MHDR_T *pPrimitivePos = _pCurrent; + USB_MHDR_T *pFound; + int found_size = -1; + int i, block_count; + int wrap = 0; + void *pvBuf = NULL; + rt_base_t level; + + level = rt_hw_interrupt_disable(); + + if (wanted_size >= _FreeMemorySize) + { + rt_kprintf("USB_malloc - want=%d, free=%d\n", wanted_size, _FreeMemorySize); + goto exit_USB_malloc; + } + + + if ((uint32_t)_pCurrent >= _MemoryPoolEnd) + _pCurrent = (USB_MHDR_T *)_MemoryPoolBase; /* wrapped */ + + do + { + if (_pCurrent->flag) /* is not a free block */ + { + if (_pCurrent->magic != USB_MEM_ALLOC_MAGIC) + { + rt_kprintf("\nUSB_malloc - incorrect magic number! C:%x F:%x, wanted:%d, Base:0x%x, End:0x%x\n", (uint32_t)_pCurrent, _FreeMemorySize, wanted_size, (uint32_t)_MemoryPoolBase, (uint32_t)_MemoryPoolEnd); + goto exit_USB_malloc; + } + + if (_pCurrent->flag == 0x3) + _pCurrent = (USB_MHDR_T *)((uint32_t)_pCurrent + _pCurrent->bcnt * USB_MEM_BLOCK_SIZE); + else + { + rt_kprintf("USB_malloc warning - not the first block!\n"); + _pCurrent = (USB_MHDR_T *)((uint32_t)_pCurrent + USB_MEM_BLOCK_SIZE); + } + + if ((uint32_t)_pCurrent > _MemoryPoolEnd) + rt_kprintf("USB_malloc - behind limit!!\n"); + + if ((uint32_t)_pCurrent == _MemoryPoolEnd) + { + //rt_kprintf("USB_alloc - warp!!\n"); + wrap = 1; + _pCurrent = (USB_MHDR_T *)_MemoryPoolBase; /* wrapped */ + } + + found_size = -1; /* reset the accumlator */ + } + else /* is a free block */ + { + if (found_size == -1) /* the leading block */ + { + pFound = _pCurrent; + block_count = 1; + + if (boundary > BOUNDARY_WORD) + found_size = 0; /* not use the data area of the leading block */ + else + found_size = USB_MEM_BLOCK_SIZE - sizeof(USB_MHDR_T); + + /* check boundary - + * If boundary > BOUNDARY_WORD, the start of next block should + * be the beginning address of allocated memory. Thus, we check + * the boundary of the next block. The leading block will be + * used as a header only. + */ + if ((boundary > BOUNDARY_WORD) && + ((((uint32_t)_pCurrent) + USB_MEM_BLOCK_SIZE >= _MemoryPoolEnd) || + ((((uint32_t)_pCurrent) + USB_MEM_BLOCK_SIZE) % boundary != 0))) + found_size = -1; /* violate boundary, reset the accumlator */ + } + else /* not the leading block */ + { + found_size += USB_MEM_BLOCK_SIZE; + block_count++; + } + + if (found_size >= wanted_size) + { + pFound->bcnt = block_count; + pFound->magic = USB_MEM_ALLOC_MAGIC; + _FreeMemorySize -= block_count * USB_MEM_BLOCK_SIZE; + _AllocatedMemorySize += block_count * USB_MEM_BLOCK_SIZE; + _pCurrent = pFound; + for (i = 0; i < block_count; i++) + { + _pCurrent->flag = 1; /* allocate block */ + _pCurrent = (USB_MHDR_T *)((uint32_t)_pCurrent + USB_MEM_BLOCK_SIZE); + } + pFound->flag = 0x3; + + if (boundary > BOUNDARY_WORD) + { + pvBuf = (void *)((uint32_t)pFound + USB_MEM_BLOCK_SIZE); + goto exit_USB_malloc; + } + else + { + //USB_debug("USB_malloc(%d,%d):%x\tsize:%d, C:0x%x, %d\n", wanted_size, boundary, (uint32_t)pFound + sizeof(USB_MHDR_T), block_count * USB_MEM_BLOCK_SIZE, _pCurrent, block_count); + pvBuf = (void *)((uint32_t)pFound + sizeof(USB_MHDR_T)); + goto exit_USB_malloc; + } + } + + /* advance to the next block */ + _pCurrent = (USB_MHDR_T *)((uint32_t)_pCurrent + USB_MEM_BLOCK_SIZE); + if ((uint32_t)_pCurrent >= _MemoryPoolEnd) + { + wrap = 1; + _pCurrent = (USB_MHDR_T *)_MemoryPoolBase; /* wrapped */ + found_size = -1; /* reset accumlator */ + } + } + } + while ((wrap == 0) || (_pCurrent < pPrimitivePos)); + + rt_kprintf("USB_malloc - No free memory!\n"); + +exit_USB_malloc: + + rt_hw_interrupt_enable(level); + + return pvBuf; +} + + +void USB_free(void *alloc_addr) +{ + USB_MHDR_T *pMblk; + uint32_t addr = (uint32_t)alloc_addr; + int i, count; + rt_base_t level; + + //rt_kprintf("USB_free: 0x%x\n", (int)alloc_addr); + + level = rt_hw_interrupt_disable(); + + if ((addr < _MemoryPoolBase) || (addr >= _MemoryPoolEnd)) + { + if (addr) + { + rt_kprintf("[%s]Wrong!!\n", __func__); + } + goto Exit_USB_free; + } + + //rt_kprintf("USB_free:%x\n", (int32_t)addr+USB_MEM_BLOCK_SIZE); + + /* get the leading block address */ + if (addr % USB_MEM_BLOCK_SIZE == 0) + addr -= USB_MEM_BLOCK_SIZE; + else + addr -= sizeof(USB_MHDR_T); + + if (addr % USB_MEM_BLOCK_SIZE != 0) + { + rt_kprintf("USB_free fatal error on address: %x!!\n", (uint32_t)alloc_addr); + goto Exit_USB_free; + } + + pMblk = (USB_MHDR_T *)addr; + if (pMblk->flag == 0) + { + rt_kprintf("USB_free(), warning - try to free a free block: %x\n", (uint32_t)alloc_addr); + goto Exit_USB_free; + } + if (pMblk->magic != USB_MEM_ALLOC_MAGIC) + { + rt_kprintf("USB_free(), warning - try to free an unknow block at address:%x.\n", addr); + goto Exit_USB_free; + } + + //_pCurrent = pMblk; + + //rt_kprintf("+ 0x%x, %d\n", (int)pMblk, pMblk->bcnt); + + count = pMblk->bcnt; + for (i = 0; i < count; i++) + { + pMblk->flag = 0; /* release block */ + pMblk = (USB_MHDR_T *)((uint32_t)pMblk + USB_MEM_BLOCK_SIZE); + } + + _FreeMemorySize += count * USB_MEM_BLOCK_SIZE; + _AllocatedMemorySize -= count * USB_MEM_BLOCK_SIZE; + + +Exit_USB_free: + + rt_hw_interrupt_enable(level); + + return; +} + + +/// @endcond HIDDEN_SYMBOLS + diff --git a/bsp/nuvoton/libraries/ma35/UsbHostLib/src/usb_core.c b/bsp/nuvoton/libraries/ma35/UsbHostLib/src/usb_core.c new file mode 100644 index 0000000000..bd85008f9c --- /dev/null +++ b/bsp/nuvoton/libraries/ma35/UsbHostLib/src/usb_core.c @@ -0,0 +1,335 @@ +/**************************************************************************//** + * @file usb_core.c + * @version V1.10 + * @brief USB Host library core. + * + * @note + * SPDX-License-Identifier: Apache-2.0 + * Copyright (C) 2018 Nuvoton Technology Corp. All rights reserved. +*****************************************************************************/ + +#include +#include +#include + +#include "usb.h" +#include "hub.h" + + +/// @cond HIDDEN_SYMBOLS + +USBH_T *_ohci0, *_ohci1; +HSUSBH_T *_ehci0, *_ehci1; + +int _IsInUsbInterrupt = 0; + +static UDEV_DRV_T *_drivers[MAX_UDEV_DRIVER]; + +static CONN_FUNC *g_conn_func, *g_disconn_func; + +extern void OHCI0_IRQHandler(int vector, void *param); +extern void OHCI1_IRQHandler(int vector, void *param); +extern void EHCI0_IRQHandler(int vector, void *param); +extern void EHCI1_IRQHandler(int vector, void *param); + + +/// @endcond HIDDEN_SYMBOLS + + +/** + * @brief Initialize MA35D1 USB Host controller and USB stack. + * + * @return None. + */ +void usbh_core_init() +{ + _ehci0 = (HSUSBH_T *)HSUSBH0_BASE; + _ohci0 = (USBH_T *)USBH0_BASE; + _ehci1 = (HSUSBH_T *)HSUSBH1_BASE; + _ohci1 = (USBH_T *)USBH1_BASE; + + memset(_drivers, 0, sizeof(_drivers)); + + g_conn_func = NULL; + g_disconn_func = NULL; + +// usbh_hub_init(); + usbh_memory_init(); + +#ifdef ENABLE_OHCI0 + rt_hw_interrupt_install(USBH0_IRQn, OHCI0_IRQHandler, NULL, "ohci0"); + rt_hw_interrupt_umask(USBH0_IRQn); + ohci0_driver.init(); + rt_kprintf("OHCI0 init done.\n"); +#endif + +#ifdef ENABLE_EHCI0 + rt_hw_interrupt_install(HSUSBH0_IRQn, EHCI0_IRQHandler, NULL, "ehci0"); + rt_hw_interrupt_umask(HSUSBH0_IRQn); + ehci0_driver.init(); + rt_kprintf("EHCI0 init done.\n"); +#endif + +#ifdef ENABLE_OHCI1 + rt_hw_interrupt_install(USBH1_IRQn, OHCI1_IRQHandler, NULL, "ohci1"); + rt_hw_interrupt_umask(USBH1_IRQn); + ohci1_driver.init(); + rt_kprintf("OHCI1 init done.\n"); +#endif + +#ifdef ENABLE_EHCI1 + rt_hw_interrupt_install(HSUSBH1_IRQn, EHCI1_IRQHandler, NULL, "ehci1"); + rt_hw_interrupt_umask(HSUSBH1_IRQn); + ehci1_driver.init(); + rt_kprintf("EHCI1 init done.\n"); +#endif +} + + + + +/** + * @brief Let USB stack polls all root hubs. If there's any hub port + * change found, USB stack will manage the hub events in this function call. + * In this function, USB stack enumerates newly connected devices and remove staff + * of disconnected devices. User's application should periodically invoke this + * function. + * @return There's hub port change or not. + * @retval 0 No any hub port status changes found. + * @retval 1 There's hub port status changes. + */ +int usbh_polling_root_hubs(void) +{ + int ret, change = 0; + +#ifdef ENABLE_EHCI0 + do + { + ret = ehci0_driver.rthub_polling(); + if (ret) + change = 1; + } + while (ret == 1); + // scan_isochronous_list(); +#endif + +#ifdef ENABLE_EHCI1 + do + { + ret = ehci1_driver.rthub_polling(); + if (ret) + change = 1; + } + while (ret == 1); + // scan_isochronous_list(); +#endif + +#ifdef ENABLE_OHCI0 + do + { + ret = ohci0_driver.rthub_polling(); + if (ret) + change = 1; + } + while (ret == 1); +#endif + +#ifdef ENABLE_OHCI1 + do + { + ret = ohci1_driver.rthub_polling(); + if (ret) + change = 1; + } + while (ret == 1); +#endif + + return change; +} + +/** + * @brief Force to quit an endpoint transfer. + * @param[in] udev The USB device. + * @param[in] ep The endpoint to be quit. + * @retval 0 Transfer success + * @retval < 0 Failed. Refer to error code definitions. + */ +int usbh_quit_xfer(UDEV_T *udev, EP_INFO_T *ep) +{ + return udev->hc_driver->quit_xfer(NULL, ep); +} + + +int usbh_connect_device(UDEV_T *udev) +{ + usbh_delay_ms(100); /* initially, give 100 ms delay */ + + if (g_conn_func) + g_conn_func(udev, 0); + + return 0; +} + + +void usbh_disconnect_device(UDEV_T *udev) +{ + USB_debug("disconnect device...\n"); + + if (g_disconn_func) + g_disconn_func(udev, 0); + + +#if 1 //CHECK: Maybe create a new API to quit_xfer and free udev for application + usbh_quit_xfer(udev, &(udev->ep0)); /* Quit control transfer if hw_pipe is not NULL. */ + + /* remove device from global device list */ +// free_dev_address(udev->dev_num); + free_device(udev); + +// usbh_memory_used(); +#endif +} + +/** + * @brief Install device connect and disconnect callback function. + * + * @param[in] conn_func Device connect callback function. + * @param[in] disconn_func Device disconnect callback function. + * @return None. + */ +void usbh_install_conn_callback(CONN_FUNC *conn_func, CONN_FUNC *disconn_func) +{ + g_conn_func = conn_func; + g_disconn_func = disconn_func; +} + +int usbh_reset_port(UDEV_T *udev) +{ + if (udev->parent == NULL) + { + if (udev->hc_driver) + return udev->hc_driver->rthub_port_reset(udev->port_num - 1); + else + return USBH_ERR_NOT_FOUND; + } + else + { + return udev->parent->port_reset(udev->parent, udev->port_num); + } +} + + +/** + * @brief Force to quit an UTR transfer. + * @param[in] utr The UTR transfer to be quit. + * @retval 0 Transfer success + * @retval < 0 Failed. Refer to error code definitions. + */ +int usbh_quit_utr(UTR_T *utr) +{ + if (!utr || !utr->udev) + return USBH_ERR_NOT_FOUND; + + return utr->udev->hc_driver->quit_xfer(utr, NULL); +} + + +/** + * @brief Execute an USB request in control transfer. This function returns after the request + * was done or aborted. + * @param[in] udev The target USB device. + * @param[in] bmRequestType Characteristics of request + * @param[in] bRequest Specific request + * @param[in] wValue Word-sized field that varies according to request + * @param[in] wIndex Word-sized field that varies according to request + * @param[in] wLength Number of bytes to transfer if there is a Data stage + * @param[in] buff Data buffer used in data stage + * @param[out] xfer_len Transmitted/received length of data + * @param[in] timeout Time-out limit (in 10ms - timer tick) of this transfer + * @retval 0 Transfer success + * @retval < 0 Transfer failed. Refer to error code definitions. + */ +int usbh_ctrl_xfer(UDEV_T *udev, uint8_t bmRequestType, uint8_t bRequest, uint16_t wValue, uint16_t wIndex, + uint16_t wLength, uint8_t *buff, uint32_t *xfer_len, uint32_t timeout) +{ + UTR_T *utr; + uint32_t t0, timeout_tick; + int status; + + *xfer_len = 0; + + //if (check_device(udev)) + // return USBH_ERR_INVALID_PARAM; + + utr = alloc_utr(udev); + if (utr == NULL) + return USBH_ERR_MEMORY_OUT; + + utr->setup.bmRequestType = bmRequestType; + utr->setup.bRequest = bRequest; + utr->setup.wValue = wValue; + utr->setup.wIndex = wIndex; + utr->setup.wLength = wLength; + + utr->buff = buff; + utr->data_len = wLength; + utr->bIsTransferDone = 0; + status = udev->hc_driver->ctrl_xfer(utr); + if (status < 0) + { + udev->ep0.hw_pipe = NULL; + free_utr(utr); + return status; + } + + timeout_tick = usbh_tick_from_millisecond(timeout); + t0 = usbh_get_ticks(); + while (utr->bIsTransferDone == 0) + { + if (usbh_get_ticks() - t0 > timeout_tick) + { + usbh_quit_utr(utr); + free_utr(utr); + udev->ep0.hw_pipe = NULL; + return USBH_ERR_TIMEOUT; + } + } + + status = utr->status; + + if (status == 0) + { + *xfer_len = utr->xfer_len; + } + free_utr(utr); + + return status; +} + +/** + * @brief Execute a bulk transfer request. This function will return immediately after + * issued the bulk transfer. USB stack will later call back utr->func() once the bulk + * transfer was done or aborted. + * @param[in] utr The bulk transfer request. + * @retval 0 Transfer success + * @retval < 0 Failed. Refer to error code definitions. + */ +int usbh_bulk_xfer(UTR_T *utr) +{ + return utr->udev->hc_driver->bulk_xfer(utr); +} + +/** + * @brief Execute an interrupt transfer request. This function will return immediately after + * issued the interrupt transfer. USB stack will later call back utr->func() once the + * interrupt transfer was done or aborted. + * @param[in] utr The interrupt transfer request. + * @retval 0 Transfer success + * @retval < 0 Failed. Refer to error code definitions. + */ +int usbh_int_xfer(UTR_T *utr) +{ + return utr->udev->hc_driver->int_xfer(utr); +} + + diff --git a/bsp/nuvoton/libraries/ma35/libcpu/SConscript b/bsp/nuvoton/libraries/ma35/libcpu/SConscript new file mode 100644 index 0000000000..6092707e6d --- /dev/null +++ b/bsp/nuvoton/libraries/ma35/libcpu/SConscript @@ -0,0 +1,15 @@ +# RT-Thread building script for bridge + +import os +from building import * + +Import('rtconfig') + +cwd = GetCurrentDir() +group = [] +list = os.listdir(cwd) + +if rtconfig.ARCH in list: + group = group + SConscript(os.path.join(rtconfig.ARCH, 'SConscript')) + +Return('group') diff --git a/bsp/nuvoton/libraries/ma35/libcpu/aarch64/SConscript b/bsp/nuvoton/libraries/ma35/libcpu/aarch64/SConscript new file mode 100644 index 0000000000..0b74223c6f --- /dev/null +++ b/bsp/nuvoton/libraries/ma35/libcpu/aarch64/SConscript @@ -0,0 +1,13 @@ +# RT-Thread building script for component + +from building import * + +Import('rtconfig') + +cwd = GetCurrentDir() +src = Glob('*.c') + Glob('*.cpp') + Glob('*.S') +CPPPATH = [cwd] + +group = DefineGroup('CPU', src, depend = [''], CPPPATH = CPPPATH) + +Return('group') diff --git a/bsp/nuvoton/libraries/ma35/libcpu/aarch64/armv8.h b/bsp/nuvoton/libraries/ma35/libcpu/aarch64/armv8.h new file mode 100644 index 0000000000..1e74ced48e --- /dev/null +++ b/bsp/nuvoton/libraries/ma35/libcpu/aarch64/armv8.h @@ -0,0 +1,63 @@ +/* + * Copyright (c) 2006-2022, RT-Thread Development Team + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + * 2011-09-15 Bernard first version + */ + +#ifndef __ARMV8_H__ +#define __ARMV8_H__ + +/* the exception stack without VFP registers */ +struct rt_hw_exp_stack +{ + unsigned long long pc; + unsigned long long spsr; + unsigned long long x30; + unsigned long long xz; + unsigned long long x28; + unsigned long long x29; + unsigned long long x26; + unsigned long long x27; + unsigned long long x24; + unsigned long long x25; + unsigned long long x22; + unsigned long long x23; + unsigned long long x20; + unsigned long long x21; + unsigned long long x18; + unsigned long long x19; + unsigned long long x16; + unsigned long long x17; + unsigned long long x14; + unsigned long long x15; + unsigned long long x12; + unsigned long long x13; + unsigned long long x10; + unsigned long long x11; + unsigned long long x8; + unsigned long long x9; + unsigned long long x6; + unsigned long long x7; + unsigned long long x4; + unsigned long long x5; + unsigned long long x2; + unsigned long long x3; + unsigned long long x0; + unsigned long long x1; +}; + +#define SP_ELx ( ( unsigned long long ) 0x01 ) +#define SP_EL0 ( ( unsigned long long ) 0x00 ) +#define PSTATE_EL1 ( ( unsigned long long ) 0x04 ) +#define PSTATE_EL2 ( ( unsigned long long ) 0x08 ) +#define PSTATE_EL3 ( ( unsigned long long ) 0x0c ) + +rt_ubase_t rt_hw_get_current_el(void); +void rt_hw_set_elx_env(void); +void rt_hw_set_current_vbar(rt_ubase_t addr); + +#endif diff --git a/bsp/nuvoton/libraries/ma35/libcpu/aarch64/cache.S b/bsp/nuvoton/libraries/ma35/libcpu/aarch64/cache.S new file mode 100644 index 0000000000..7f295a2b02 --- /dev/null +++ b/bsp/nuvoton/libraries/ma35/libcpu/aarch64/cache.S @@ -0,0 +1,151 @@ +/* + * Copyright (c) 2006-2020, RT-Thread Development Team + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + * 2020-03-17 bigmagic first version + */ + +/* + * void __asm_dcache_level(level) + * + * flush or invalidate one level cache. + * + * x0: cache level + * x1: 0 clean & invalidate, 1 invalidate only + * x2~x9: clobbered + */ +.globl __asm_dcache_level +__asm_dcache_level: + lsl x12, x0, #1 + msr csselr_el1, x12 /* select cache level */ + isb /* sync change of cssidr_el1 */ + mrs x6, ccsidr_el1 /* read the new cssidr_el1 */ + and x2, x6, #7 /* x2 <- log2(cache line size)-4 */ + add x2, x2, #4 /* x2 <- log2(cache line size) */ + mov x3, #0x3ff + and x3, x3, x6, lsr #3 /* x3 <- max number of #ways */ + clz w5, w3 /* bit position of #ways */ + mov x4, #0x7fff + and x4, x4, x6, lsr #13 /* x4 <- max number of #sets */ + /* x12 <- cache level << 1 */ + /* x2 <- line length offset */ + /* x3 <- number of cache ways - 1 */ + /* x4 <- number of cache sets - 1 */ + /* x5 <- bit position of #ways */ + +loop_set: + mov x6, x3 /* x6 <- working copy of #ways */ +loop_way: + lsl x7, x6, x5 + orr x9, x12, x7 /* map way and level to cisw value */ + lsl x7, x4, x2 + orr x9, x9, x7 /* map set number to cisw value */ + tbz w1, #0, 1f + dc isw, x9 + b 2f +1: dc cisw, x9 /* clean & invalidate by set/way */ +2: subs x6, x6, #1 /* decrement the way */ + b.ge loop_way + subs x4, x4, #1 /* decrement the set */ + b.ge loop_set + + ret + +/* + * void __asm_flush_dcache_all(int invalidate_only) + * + * x0: 0 clean & invalidate, 1 invalidate only + * + * flush or invalidate all data cache by SET/WAY. + */ +.globl __asm_dcache_all +__asm_dcache_all: + mov x1, x0 + dsb sy + mrs x10, clidr_el1 /* read clidr_el1 */ + lsr x11, x10, #24 + and x11, x11, #0x7 /* x11 <- loc */ + cbz x11, finished /* if loc is 0, exit */ + mov x15, lr + mov x0, #0 /* start flush at cache level 0 */ + /* x0 <- cache level */ + /* x10 <- clidr_el1 */ + /* x11 <- loc */ + /* x15 <- return address */ + +loop_level: + lsl x12, x0, #1 + add x12, x12, x0 /* x0 <- tripled cache level */ + lsr x12, x10, x12 + and x12, x12, #7 /* x12 <- cache type */ + cmp x12, #2 + b.lt skip /* skip if no cache or icache */ + bl __asm_dcache_level /* x1 = 0 flush, 1 invalidate */ +skip: + add x0, x0, #1 /* increment cache level */ + cmp x11, x0 + b.gt loop_level + + mov x0, #0 + msr csselr_el1, x0 /* restore csselr_el1 */ + dsb sy + isb + mov lr, x15 + +finished: + ret + +.globl __asm_flush_dcache_all +__asm_flush_dcache_all: + mov x0, #0 + b __asm_dcache_all + +.globl __asm_invalidate_dcache_all +__asm_invalidate_dcache_all: + mov x0, #0x1 + b __asm_dcache_all + +/* + * void __asm_flush_dcache_range(start, end) + * + * clean & invalidate data cache in the range + * + * x0: start address + * x1: end address + */ +.globl __asm_flush_dcache_range +__asm_flush_dcache_range: + mrs x3, ctr_el0 + lsr x3, x3, #16 + and x3, x3, #0xf + mov x2, #4 + lsl x2, x2, x3 /* cache line size */ + + /* x2 <- minimal cache line size in cache system */ + sub x3, x2, #1 + bic x0, x0, x3 +1: dc civac, x0 /* clean & invalidate data or unified cache */ + add x0, x0, x2 + cmp x0, x1 + b.lo 1b + dsb sy + ret + +/* + * void __asm_invalidate_icache_all(void) + * + * invalidate all tlb entries. + */ +.globl __asm_invalidate_icache_all +__asm_invalidate_icache_all: + ic ialluis + isb sy + ret + +.globl __asm_flush_l3_cache +__asm_flush_l3_cache: + mov x0, #0 /* return status as success */ + ret \ No newline at end of file diff --git a/bsp/nuvoton/libraries/ma35/libcpu/aarch64/context_gcc.S b/bsp/nuvoton/libraries/ma35/libcpu/aarch64/context_gcc.S new file mode 100644 index 0000000000..f58ea1b15d --- /dev/null +++ b/bsp/nuvoton/libraries/ma35/libcpu/aarch64/context_gcc.S @@ -0,0 +1,312 @@ +/* + * Copyright (c) 2006-2020, RT-Thread Development Team + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + * 2018-10-06 ZhaoXiaowei the first version + */ + +.macro SAVE_CONTEXT + + /* Switch to use the EL0 stack pointer. */ + MSR SPSEL, #0 + + /* Save the entire context. */ + STP X0, X1, [SP, #-0x10]! + STP X2, X3, [SP, #-0x10]! + STP X4, X5, [SP, #-0x10]! + STP X6, X7, [SP, #-0x10]! + STP X8, X9, [SP, #-0x10]! + STP X10, X11, [SP, #-0x10]! + STP X12, X13, [SP, #-0x10]! + STP X14, X15, [SP, #-0x10]! + STP X16, X17, [SP, #-0x10]! + STP X18, X19, [SP, #-0x10]! + STP X20, X21, [SP, #-0x10]! + STP X22, X23, [SP, #-0x10]! + STP X24, X25, [SP, #-0x10]! + STP X26, X27, [SP, #-0x10]! + STP X28, X29, [SP, #-0x10]! + STP X30, XZR, [SP, #-0x10]! + + MRS X0, CurrentEL + CMP X0, 0xc + B.EQ 3f + CMP X0, 0x8 + B.EQ 2f + CMP X0, 0x4 + B.EQ 1f + B . +3: + MRS X3, SPSR_EL3 + /* Save the ELR. */ + MRS X2, ELR_EL3 + B 0f +2: + MRS X3, SPSR_EL2 + /* Save the ELR. */ + MRS X2, ELR_EL2 + B 0f +1: + MRS X3, SPSR_EL1 + MRS X2, ELR_EL1 + B 0f +0: + + STP X2, X3, [SP, #-0x10]! + + MOV X0, SP /* Move SP into X0 for saving. */ + + /* Switch to use the ELx stack pointer. */ + MSR SPSEL, #1 + + .endm + +.macro SAVE_CONTEXT_T + + /* Switch to use the EL0 stack pointer. */ + MSR SPSEL, #0 + + /* Save the entire context. */ + STP X0, X1, [SP, #-0x10]! + STP X2, X3, [SP, #-0x10]! + STP X4, X5, [SP, #-0x10]! + STP X6, X7, [SP, #-0x10]! + STP X8, X9, [SP, #-0x10]! + STP X10, X11, [SP, #-0x10]! + STP X12, X13, [SP, #-0x10]! + STP X14, X15, [SP, #-0x10]! + STP X16, X17, [SP, #-0x10]! + STP X18, X19, [SP, #-0x10]! + STP X20, X21, [SP, #-0x10]! + STP X22, X23, [SP, #-0x10]! + STP X24, X25, [SP, #-0x10]! + STP X26, X27, [SP, #-0x10]! + STP X28, X29, [SP, #-0x10]! + STP X30, XZR, [SP, #-0x10]! + + MRS X0, CurrentEL + CMP X0, 0xc + B.EQ 3f + CMP X0, 0x8 + B.EQ 2f + CMP X0, 0x4 + B.EQ 1f + B . +3: + MRS X3, SPSR_EL3 + MOV X2, X30 + B 0f +2: + MRS X3, SPSR_EL2 + MOV X2, X30 + B 0f +1: + MRS X3, SPSR_EL1 + MOV X2, X30 + B 0f +0: + + STP X2, X3, [SP, #-0x10]! + + MOV X0, SP /* Move SP into X0 for saving. */ + + /* Switch to use the ELx stack pointer. */ + MSR SPSEL, #1 + + .endm + +.macro RESTORE_CONTEXT + + /* Switch to use the EL0 stack pointer. */ + MSR SPSEL, #0 + + /* Set the SP to point to the stack of the task being restored. */ + MOV SP, X0 + + LDP X2, X3, [SP], #0x10 /* SPSR and ELR. */ + + MRS X0, CurrentEL + CMP X0, 0xc + B.EQ 3f + CMP X0, 0x8 + B.EQ 2f + CMP X0, 0x4 + B.EQ 1f + B . +3: + MSR SPSR_EL3, X3 + MSR ELR_EL3, X2 + B 0f +2: + MSR SPSR_EL2, X3 + MSR ELR_EL2, X2 + B 0f +1: + MSR SPSR_EL1, X3 + MSR ELR_EL1, X2 + B 0f +0: + + LDP X30, XZR, [SP], #0x10 + LDP X28, X29, [SP], #0x10 + LDP X26, X27, [SP], #0x10 + LDP X24, X25, [SP], #0x10 + LDP X22, X23, [SP], #0x10 + LDP X20, X21, [SP], #0x10 + LDP X18, X19, [SP], #0x10 + LDP X16, X17, [SP], #0x10 + LDP X14, X15, [SP], #0x10 + LDP X12, X13, [SP], #0x10 + LDP X10, X11, [SP], #0x10 + LDP X8, X9, [SP], #0x10 + LDP X6, X7, [SP], #0x10 + LDP X4, X5, [SP], #0x10 + LDP X2, X3, [SP], #0x10 + LDP X0, X1, [SP], #0x10 + + /* Switch to use the ELx stack pointer. _RB_ Might not be required. */ + MSR SPSEL, #1 + + ERET + + .endm + +.text +/* + * rt_base_t rt_hw_interrupt_disable(); + */ +.globl rt_hw_interrupt_disable +rt_hw_interrupt_disable: + MRS X0, DAIF + MSR DAIFSet, #3 + DSB SY + RET + +/* + * void rt_hw_interrupt_enable(rt_base_t level); + */ +.globl rt_hw_interrupt_enable +rt_hw_interrupt_enable: + DSB SY + MOV X1, #0xC0 + ANDS X0, X0, X1 + B.NE rt_hw_interrupt_enable_exit + MSR DAIFClr, #3 +rt_hw_interrupt_enable_exit: + RET + +/* + * void rt_hw_context_switch_to(rt_ubase_t to); + * r0 --> to + */ +.globl rt_hw_context_switch_to +rt_hw_context_switch_to: + LDR X0, [X0] + RESTORE_CONTEXT + +.text +/* + * void rt_hw_context_switch(rt_ubase_t from, rt_ubase_t to); + * r0 --> from + * r1 --> to + */ +.globl rt_hw_context_switch +rt_hw_context_switch: + + MOV X8,X0 + MOV X9,X1 + + SAVE_CONTEXT_T + + STR X0, [X8] // store sp in preempted tasks TCB + LDR X0, [X9] // get new task stack pointer + + RESTORE_CONTEXT + +/* + * void rt_hw_context_switch_interrupt(rt_ubase_t from, rt_ubase_t to); + */ +.globl rt_thread_switch_interrupt_flag +.globl rt_interrupt_from_thread +.globl rt_interrupt_to_thread +.globl rt_hw_context_switch_interrupt +rt_hw_context_switch_interrupt: + ADR X2, rt_thread_switch_interrupt_flag + LDR X3, [X2] + CMP X3, #1 + B.EQ _reswitch + ADR X4, rt_interrupt_from_thread // set rt_interrupt_from_thread + MOV X3, #1 // set rt_thread_switch_interrupt_flag to 1 + STR X0, [X4] + STR X3, [X2] +_reswitch: + ADR X2, rt_interrupt_to_thread // set rt_interrupt_to_thread + STR X1, [X2] + RET + +.text + +// -- Exception handlers ---------------------------------- + + .align 8 +.globl vector_fiq +vector_fiq: + SAVE_CONTEXT + STP X0, X1, [SP, #-0x10]! + BL rt_hw_trap_fiq + LDP X0, X1, [SP], #0x10 + RESTORE_CONTEXT + +.globl rt_interrupt_enter +.globl rt_interrupt_leave +.globl rt_thread_switch_interrupt_flag +.globl rt_interrupt_from_thread +.globl rt_interrupt_to_thread + + +// ------------------------------------------------------------------- + + .align 8 +.globl vector_irq +vector_irq: + SAVE_CONTEXT + STP X0, X1, [SP, #-0x10]! + + BL rt_interrupt_enter + BL rt_hw_trap_irq + BL rt_interrupt_leave + + LDP X0, X1, [SP], #0x10 + + // if rt_thread_switch_interrupt_flag set, jump to + // rt_hw_context_switch_interrupt_do and don't return + ADR X1, rt_thread_switch_interrupt_flag + LDR X2, [X1] + CMP X2, #1 + B.NE vector_irq_exit + + MOV X2, #0 // clear flag + STR X2, [X1] + + ADR X3, rt_interrupt_from_thread + LDR X4, [X3] + STR x0, [X4] // store sp in preempted tasks's TCB + + ADR x3, rt_interrupt_to_thread + LDR X4, [X3] + LDR x0, [X4] // get new task's stack pointer + +vector_irq_exit: + RESTORE_CONTEXT + +// ------------------------------------------------- + + .align 8 + .globl vector_error +vector_error: + SAVE_CONTEXT + BL rt_hw_trap_error + B . diff --git a/bsp/nuvoton/libraries/ma35/libcpu/aarch64/cp15.h b/bsp/nuvoton/libraries/ma35/libcpu/aarch64/cp15.h new file mode 100644 index 0000000000..7c64f23c9e --- /dev/null +++ b/bsp/nuvoton/libraries/ma35/libcpu/aarch64/cp15.h @@ -0,0 +1,68 @@ +/* + * Copyright (c) 2006-2022, RT-Thread Development Team + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + * 2011-09-15 Bernard first version + */ + +#ifndef __CP15_H__ +#define __CP15_H__ + +#ifndef __STATIC_FORCEINLINE + #define __STATIC_FORCEINLINE __attribute__((always_inline)) static inline +#endif + +#define __WFI() __asm__ volatile ("wfi":::"memory") + +#define __WFE() __asm__ volatile ("wfe":::"memory") + +#define __SEV() __asm__ volatile ("sev") + +/** + \brief Instruction Synchronization Barrier + \details Instruction Synchronization Barrier flushes the pipeline in the processor, + so that all instructions following the ISB are fetched from cache or + memory, after the instruction has been completed. + */ +__STATIC_FORCEINLINE void __ISB(void) +{ + __asm__ volatile("isb 0xF":::"memory"); +} + +/** + \brief Data Synchronization Barrier + \details Acts as a special kind of Data Memory Barrier. + It completes when all explicit memory accesses before this instruction complete. + */ +__STATIC_FORCEINLINE void __DSB(void) +{ + __asm__ volatile("dsb 0xF":::"memory"); +} + +/** + \brief Data Memory Barrier + \details Ensures the apparent order of the explicit memory operations before + and after the instruction, without ensuring their completion. + */ +__STATIC_FORCEINLINE void __DMB(void) +{ + __asm__ volatile("dmb 0xF":::"memory"); +} + +unsigned long rt_cpu_get_smp_id(void); + +void rt_cpu_mmu_disable(void); +void rt_cpu_mmu_enable(void); +void rt_cpu_tlb_set(volatile unsigned long *); + +void rt_cpu_dcache_clean_flush(void); +void rt_cpu_icache_flush(void); + +void rt_cpu_vector_set_base(rt_ubase_t addr); +void rt_hw_mmu_init(void); +void rt_hw_vector_init(void); + +#endif diff --git a/bsp/nuvoton/libraries/ma35/libcpu/aarch64/cpu.c b/bsp/nuvoton/libraries/ma35/libcpu/aarch64/cpu.c new file mode 100644 index 0000000000..3f4fe52b46 --- /dev/null +++ b/bsp/nuvoton/libraries/ma35/libcpu/aarch64/cpu.c @@ -0,0 +1,108 @@ +/* + * Copyright (c) 2006-2022, RT-Thread Development Team + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + * 2011-09-15 Bernard first version + * 2019-07-28 zdzn add smp support + */ + +#include +#include +#include +#include "cp15.h" + +int rt_hw_cpu_id(void) +{ + int cpu_id; + rt_base_t value; + + __asm__ volatile( + "mrs %0, mpidr_el1" + :"=r"(value) + ); + cpu_id = value & 0xf; + return cpu_id; +}; + +#ifdef RT_USING_SMP +void rt_hw_spin_lock_init(rt_hw_spinlock_t *lock) +{ + lock->slock = 0; +} + +void rt_hw_spin_lock(rt_hw_spinlock_t *lock) +{ + unsigned long tmp; + unsigned long newval; + rt_hw_spinlock_t lockval; + + __asm__ __volatile__( + " prfm pstl1strm, %3\n" + "1: ldaxr %w0, %3\n" + " add %w1, %w0, %w5\n" + " stxr %w2, %w1, %3\n" + " cbnz %w2, 1b\n" + /* Did we get the lock? */ + " eor %w1, %w0, %w0, ror #16\n" + " cbz %w1, 3f\n" + " sevl\n" + "2: wfe\n" + " ldaxrh %w2, %4\n" + " eor %w1, %w2, %w0, lsr #16\n" + " cbnz %w1, 2b\n" + "3:" + : "=&r"(lockval), "=&r"(newval), "=&r"(tmp), "+Q"(*lock) + : "Q"(lock->slock), "I"(1 << 16) + : "memory"); + + +} + +void rt_hw_spin_unlock(rt_hw_spinlock_t *lock) +{ + __DMB(); + lock->tickets.owner++; + __DSB(); + __SEV(); +} +#endif /*RT_USING_SMP*/ + +/** + * @addtogroup ARM CPU + */ +/*@{*/ + +/** shutdown CPU */ +RT_WEAK void rt_hw_cpu_shutdown() +{ + rt_uint32_t level; + rt_kprintf("shutdown...\n"); + + level = rt_hw_interrupt_disable(); + while (level) + { + RT_ASSERT(0); + } +} + +#ifdef RT_USING_CPU_FFS +/** + * This function finds the first bit set (beginning with the least significant bit) + * in value and return the index of that bit. + * + * Bits are numbered starting at 1 (the least significant bit). A return value of + * zero from any of these functions means that the argument was zero. + * + * @return return the index of the first bit set. If value is 0, then this function + * shall return 0. + */ +int __rt_ffs(int value) +{ + return __builtin_ffs(value); +} +#endif + +/*@}*/ diff --git a/bsp/nuvoton/libraries/ma35/libcpu/aarch64/cpu_gcc.S b/bsp/nuvoton/libraries/ma35/libcpu/aarch64/cpu_gcc.S new file mode 100644 index 0000000000..b8c8b8768c --- /dev/null +++ b/bsp/nuvoton/libraries/ma35/libcpu/aarch64/cpu_gcc.S @@ -0,0 +1,82 @@ +/* + * Copyright (c) 2006-2020, RT-Thread Development Team + * + * SPDX-License-Identifier: Apache-2.0 + * + * Date Author Notes + * 2018-10-06 ZhaoXiaowei the first version + */ + +.text +.globl rt_hw_get_current_el +rt_hw_get_current_el: + MRS X0, CurrentEL + CMP X0, 0xc + B.EQ 3f + CMP X0, 0x8 + B.EQ 2f + CMP X0, 0x4 + B.EQ 1f + + LDR X0, =0 + B 0f +3: + LDR X0, =3 + B 0f +2: + LDR X0, =2 + B 0f +1: + LDR X0, =1 + B 0f +0: + RET + + +.globl rt_hw_set_current_vbar +rt_hw_set_current_vbar: + MRS X1, CurrentEL + CMP X1, 0xc + B.EQ 3f + CMP X1, 0x8 + B.EQ 2f + CMP X1, 0x4 + B.EQ 1f + B 0f +3: + MSR VBAR_EL3,X0 + B 0f +2: + MSR VBAR_EL2,X0 + B 0f +1: + MSR VBAR_EL1,X0 + B 0f +0: + RET + + +.globl rt_hw_set_elx_env +rt_hw_set_elx_env: + MRS X1, CurrentEL + CMP X1, 0xc + B.EQ 3f + CMP X1, 0x8 + B.EQ 2f + CMP X1, 0x4 + B.EQ 1f + B 0f +3: + MRS X0, SCR_EL3 + ORR X0, X0, #0xF /* SCR_EL3.NS|IRQ|FIQ|EA */ + MSR SCR_EL3, X0 + B 0f +2: + MRS X0, HCR_EL2 + ORR X0, X0, #0x38 + MSR HCR_EL2, X0 + B 0f +1: + B 0f +0: + RET diff --git a/bsp/nuvoton/libraries/ma35/libcpu/aarch64/entry_point.S b/bsp/nuvoton/libraries/ma35/libcpu/aarch64/entry_point.S new file mode 100644 index 0000000000..2212d07511 --- /dev/null +++ b/bsp/nuvoton/libraries/ma35/libcpu/aarch64/entry_point.S @@ -0,0 +1,212 @@ +/* + * Copyright (c) 2006-2020, RT-Thread Development Team + * + * SPDX-License-Identifier: Apache-2.0 + * + * Date Author Notes + * 2021-06-29 Wayne the first version + */ + +/* GICv2 - Distributor Registers */ +#define GICD_CTLR 0x0000 +#define GICD_TYPER 0x0004 +#define GICD_IIDR 0x0008 +#define GICD_STATUSR 0x0010 +#define GICD_SETSPI_NSR 0x0040 +#define GICD_CLRSPI_NSR 0x0048 +#define GICD_SETSPI_SR 0x0050 +#define GICD_CLRSPI_SR 0x0058 +#define GICD_SEIR 0x0068 +#define GICD_IGROUPRn 0x0080 +#define GICD_ISENABLERn 0x0100 +#define GICD_ICENABLERn 0x0180 +#define GICD_ISPENDRn 0x0200 +#define GICD_ICPENDRn 0x0280 +#define GICD_ISACTIVERn 0x0300 +#define GICD_ICACTIVERn 0x0380 +#define GICD_IPRIORITYRn 0x0400 +#define GICD_ITARGETSRn 0x0800 +#define GICD_ICFGR 0x0c00 +#define GICD_IGROUPMODRn 0x0d00 +#define GICD_NSACRn 0x0e00 +#define GICD_SGIR 0x0f00 +#define GICD_CPENDSGIRn 0x0f10 +#define GICD_SPENDSGIRn 0x0f20 +#define GICD_IROUTERn 0x6000 + +/* GICv2 - CPU Interface Memory Mapped Registers */ +#define GICC_CTLR 0x0000 +#define GICC_PMR 0x0004 +#define GICC_BPR 0x0008 +#define GICC_IAR 0x000C +#define GICC_EOIR 0x0010 +#define GICC_RPR 0x0014 +#define GICC_HPPIR 0x0018 +#define GICC_ABPR 0x001c +#define GICC_AIAR 0x0020 +#define GICC_AEOIR 0x0024 +#define GICC_AHPPIR 0x0028 +#define GICC_APRn 0x00d0 +#define GICC_NSAPRn 0x00e0 +#define GICC_IIDR 0x00fc +#define GICC_DIR 0x1000 + +.section ".text.entrypoint" +.global _start + +_start: + /*=============================================================*/ + /* Read CPU id */ + /* Primary core(id=0): Help Secondary core leaving. */ + /* Secondary core(id>0): Notice 'Ready' to Primary core. */ + /*=============================================================*/ + /* MPIDR_EL1: Multi-Processor Affinity Register */ + mrs x1, mpidr_el1 + and x1, x1, #3 + cbz x1, .L__cpu_0 + +.L__current_cpu_idle: + /*=============================================================*/ + /* Secondary CPUs */ + /*=============================================================*/ + wfe + b .L__current_cpu_idle + +.L__cpu_0: + + /*=============================================================*/ + /* Initialize Gtimer. Set frequency to 12MHz. */ + /*=============================================================*/ + mov x0, #0x1B00 + movk x0, #0xB7, LSL #16 + msr CNTFRQ_EL0, x0 + + /*=============================================================*/ + /* Enable GICv2. */ + /* Assign all IRQs to secure group. */ + /*=============================================================*/ + /* Route to secure Group */ + mov x0, #0x1000 + movk x0, #0x5080, LSL #16 + mov w9, #0x3 + str w9, [x0, GICD_CTLR] + ldr w9, [x0, GICD_TYPER] + and w10, w9, #0x1f + cbz w10, 1f + add x11, x0, GICD_IGROUPRn + mov w9, #0 + str w9, [x11], #0x04 +0: str w9, [x11], #0x04 + sub w10, w10, #0x1 + cbnz w10, 0b + + mov x1, #0x2000 + movk x1, #0x5080, LSL #16 + mov w0, #3 + str w0, [x1] + + mov w0, #1 << 7 + str w0, [x1, #4] +1: + mov x0, #0x1000 + movk x0, #0x5080, LSL #16 + mov x1, #0x2000 + movk x1, #0x5080, LSL #16 + + mov w9, #0 + str w9, [x0, GICD_IGROUPRn] + mov w9, #0x1 + str w9, [x0, GICD_ISENABLERn] + + mov w9, #0x1e7 + str w9, [x1, GICC_CTLR] + + mov w9, #0x1 << 7 + str w9, [x1, GICC_PMR] + + /*=============================================================*/ + /* Enable the SMP bit. */ + /*=============================================================*/ + mrs x0, S3_1_C15_C2_1 + orr x0, x0, #(1<<6) + msr S3_1_C15_C2_1, x0 + + /*=============================================================*/ + /* Enable FP/SIMD at EL1 */ + /*=============================================================*/ + mov x0, #(3 << 20) + msr cpacr_el1, x0 /* Enable FP/SIMD at EL1 */ + + /*=============================================================*/ + /* Initialize sctlr_el1 */ + /*=============================================================*/ + mov x0, xzr + orr x0, x0, #(1 << 29) /* Enable LSMAOE at EL1 */ + orr x0, x0, #(1 << 28) /* Enable nTLSMD at EL1 */ + orr x0, x0, #(1 << 23) /* Enable SPAN at EL1 */ + orr x0, x0, #(1 << 22) /* Enable EIS at EL1 */ + orr x0, x0, #(1 << 20) /* Enable TSCXT at EL1 */ + orr x0, x0, #(1 << 11) /* Enable EOS at EL1 */ + msr sctlr_el1, x0 + + /*=============================================================*/ + /* Initialize scr_el3 */ + /*=============================================================*/ + mov x0, xzr + orr x0, x0, #(1 << 10) /* Enable AARCH64 */ + orr x0, x0, #(1 << 9) /* Enable SIF */ + orr x0, x0, #(1 << 8) /* Enable HCE */ + orr x0, x0, #(1 << 7) /* Enable SMD */ + orr x0, x0, #(1 << 5) /* RES1[5:4] */ + orr x0, x0, #(1 << 4) + /* Disable FIQ routing */ + /* Disable IRQ routing */ + /* Disable NS */ + msr scr_el3, x0 + + /*=============================================================*/ + /* Initialize spsr_el3 */ + /*=============================================================*/ + mov x0, xzr + mov x0, #0b00101 /* AARCH64_EL1 */ + orr x0, x0, #(1 << 8) /* Enable SError and External Abort. */ + orr x0, x0, #(1 << 7) /* IRQ interrupt Process state mask. */ + orr x0, x0, #(1 << 6) /* FIQ interrupt Process state mask. */ + msr spsr_el3, x0 + + /*=============================================================*/ + /* Initialize elr_el3 */ + /* Jump to Secure EL1 from EL3. */ + /*=============================================================*/ + adr x0, .aarch64_code /* Exception return to aarch64_code */ + msr elr_el3, x0 + eret + +.aarch64_code: + ldr x1, =_start + mov sp, x1 + + /*=============================================================*/ + /* clear bbs */ + /*=============================================================*/ + ldr x1, =__bss_start + ldr w2, =__bss_size + +.L__clean_bss_loop: + cbz w2, .L__jump_to_entry + str xzr, [x1], #8 + sub w2, w2, #1 + cbnz w2, .L__clean_bss_loop + + /*=============================================================*/ + /* jump to C code */ + /*=============================================================*/ +.L__jump_to_entry: + + bl entry + + /*=============================================================*/ + /* for failsafe, halt this core too */ + /*=============================================================*/ + + b .L__current_cpu_idle diff --git a/bsp/nuvoton/libraries/ma35/libcpu/aarch64/gic.c b/bsp/nuvoton/libraries/ma35/libcpu/aarch64/gic.c new file mode 100644 index 0000000000..3559969042 --- /dev/null +++ b/bsp/nuvoton/libraries/ma35/libcpu/aarch64/gic.c @@ -0,0 +1,491 @@ +/* + * Copyright (c) 2006-2022, RT-Thread Development Team + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + * 2013-07-20 Bernard first version + * 2014-04-03 Grissiom many enhancements + * 2018-11-22 Jesven add rt_hw_ipi_send() + * add rt_hw_ipi_handler_install() + */ + +#include +#include + +#include "gic.h" +#include "cp15.h" + +struct arm_gic +{ + rt_uint32_t offset; /* the first interrupt index in the vector table */ + + rt_uint32_t dist_hw_base; /* the base address of the gic distributor */ + rt_uint32_t cpu_hw_base; /* the base addrees of the gic cpu interface */ +}; + +/* 'ARM_GIC_MAX_NR' is the number of cores */ +static struct arm_gic _gic_table[ARM_GIC_MAX_NR]; + +/** Macro to access the Generic Interrupt Controller Interface (GICC) +*/ +#define GIC_CPU_CTRL(hw_base) __REG32((hw_base) + 0x00U) +#define GIC_CPU_PRIMASK(hw_base) __REG32((hw_base) + 0x04U) +#define GIC_CPU_BINPOINT(hw_base) __REG32((hw_base) + 0x08U) +#define GIC_CPU_INTACK(hw_base) __REG32((hw_base) + 0x0cU) +#define GIC_CPU_EOI(hw_base) __REG32((hw_base) + 0x10U) +#define GIC_CPU_RUNNINGPRI(hw_base) __REG32((hw_base) + 0x14U) +#define GIC_CPU_HIGHPRI(hw_base) __REG32((hw_base) + 0x18U) +#define GIC_CPU_IIDR(hw_base) __REG32((hw_base) + 0xFCU) + +/** Macro to access the Generic Interrupt Controller Distributor (GICD) +*/ +#define GIC_DIST_CTRL(hw_base) __REG32((hw_base) + 0x000U) +#define GIC_DIST_TYPE(hw_base) __REG32((hw_base) + 0x004U) +#define GIC_DIST_IGROUP(hw_base, n) __REG32((hw_base) + 0x080U + ((n)/32U) * 4U) +#define GIC_DIST_ENABLE_SET(hw_base, n) __REG32((hw_base) + 0x100U + ((n)/32U) * 4U) +#define GIC_DIST_ENABLE_CLEAR(hw_base, n) __REG32((hw_base) + 0x180U + ((n)/32U) * 4U) +#define GIC_DIST_PENDING_SET(hw_base, n) __REG32((hw_base) + 0x200U + ((n)/32U) * 4U) +#define GIC_DIST_PENDING_CLEAR(hw_base, n) __REG32((hw_base) + 0x280U + ((n)/32U) * 4U) +#define GIC_DIST_ACTIVE_SET(hw_base, n) __REG32((hw_base) + 0x300U + ((n)/32U) * 4U) +#define GIC_DIST_ACTIVE_CLEAR(hw_base, n) __REG32((hw_base) + 0x380U + ((n)/32U) * 4U) +#define GIC_DIST_PRI(hw_base, n) __REG32((hw_base) + 0x400U + ((n)/4U) * 4U) +#define GIC_DIST_TARGET(hw_base, n) __REG32((hw_base) + 0x800U + ((n)/4U) * 4U) +#define GIC_DIST_CONFIG(hw_base, n) __REG32((hw_base) + 0xc00U + ((n)/16U) * 4U) +#define GIC_DIST_SOFTINT(hw_base) __REG32((hw_base) + 0xf00U) +#define GIC_DIST_CPENDSGI(hw_base, n) __REG32((hw_base) + 0xf10U + ((n)/4U) * 4U) +#define GIC_DIST_SPENDSGI(hw_base, n) __REG32((hw_base) + 0xf20U + ((n)/4U) * 4U) +#define GIC_DIST_ICPIDR2(hw_base) __REG32((hw_base) + 0xfe8U) + +static unsigned int _gic_max_irq; + +int arm_gic_get_active_irq(rt_uint32_t index) +{ + int irq; + + RT_ASSERT(index < ARM_GIC_MAX_NR); + + irq = GIC_CPU_INTACK(_gic_table[index].cpu_hw_base); + irq += _gic_table[index].offset; + return irq; +} + +void arm_gic_ack(rt_uint32_t index, int irq) +{ + rt_uint32_t mask = 1U << (irq % 32U); + + RT_ASSERT(index < ARM_GIC_MAX_NR); + + irq = irq - _gic_table[index].offset; + RT_ASSERT(irq >= 0U); + + GIC_DIST_PENDING_CLEAR(_gic_table[index].dist_hw_base, irq) = mask; + GIC_CPU_EOI(_gic_table[index].cpu_hw_base) = irq; +} + +void arm_gic_mask(rt_uint32_t index, int irq) +{ + rt_uint32_t mask = 1U << (irq % 32U); + + RT_ASSERT(index < ARM_GIC_MAX_NR); + + irq = irq - _gic_table[index].offset; + RT_ASSERT(irq >= 0U); + + GIC_DIST_ENABLE_CLEAR(_gic_table[index].dist_hw_base, irq) = mask; +} + +void arm_gic_umask(rt_uint32_t index, int irq) +{ + rt_uint32_t mask = 1U << (irq % 32U); + + RT_ASSERT(index < ARM_GIC_MAX_NR); + + irq = irq - _gic_table[index].offset; + RT_ASSERT(irq >= 0U); + + GIC_DIST_ENABLE_SET(_gic_table[index].dist_hw_base, irq) = mask; +} + +rt_uint32_t arm_gic_get_pending_irq(rt_uint32_t index, int irq) +{ + rt_uint32_t pend; + + RT_ASSERT(index < ARM_GIC_MAX_NR); + + irq = irq - _gic_table[index].offset; + RT_ASSERT(irq >= 0U); + + if (irq >= 16U) + { + pend = (GIC_DIST_PENDING_SET(_gic_table[index].dist_hw_base, irq) >> (irq % 32U)) & 0x1UL; + } + else + { + /* INTID 0-15 Software Generated Interrupt */ + pend = (GIC_DIST_SPENDSGI(_gic_table[index].dist_hw_base, irq) >> ((irq % 4U) * 8U)) & 0xFFUL; + /* No CPU identification offered */ + if (pend != 0U) + { + pend = 1U; + } + else + { + pend = 0U; + } + } + + return (pend); +} + +void arm_gic_set_pending_irq(rt_uint32_t index, int irq) +{ + RT_ASSERT(index < ARM_GIC_MAX_NR); + + irq = irq - _gic_table[index].offset; + RT_ASSERT(irq >= 0U); + + if (irq >= 16U) + { + GIC_DIST_PENDING_SET(_gic_table[index].dist_hw_base, irq) = 1U << (irq % 32U); + } + else + { + /* INTID 0-15 Software Generated Interrupt */ + /* Forward the interrupt to the CPU interface that requested it */ + GIC_DIST_SOFTINT(_gic_table[index].dist_hw_base) = (irq | 0x02000000U); + } +} + +void arm_gic_clear_pending_irq(rt_uint32_t index, int irq) +{ + rt_uint32_t mask; + + RT_ASSERT(index < ARM_GIC_MAX_NR); + + irq = irq - _gic_table[index].offset; + RT_ASSERT(irq >= 0U); + + if (irq >= 16U) + { + mask = 1U << (irq % 32U); + GIC_DIST_PENDING_CLEAR(_gic_table[index].dist_hw_base, irq) = mask; + } + else + { + mask = 1U << ((irq % 4U) * 8U); + GIC_DIST_CPENDSGI(_gic_table[index].dist_hw_base, irq) = mask; + } +} + +void arm_gic_set_configuration(rt_uint32_t index, int irq, uint32_t config) +{ + rt_uint32_t icfgr; + rt_uint32_t shift; + + RT_ASSERT(index < ARM_GIC_MAX_NR); + + irq = irq - _gic_table[index].offset; + RT_ASSERT(irq >= 0U); + + icfgr = GIC_DIST_CONFIG(_gic_table[index].dist_hw_base, irq); + shift = (irq % 16U) << 1U; + + icfgr &= (~(3U << shift)); + icfgr |= (config << shift); + + GIC_DIST_CONFIG(_gic_table[index].dist_hw_base, irq) = icfgr; +} + +rt_uint32_t arm_gic_get_configuration(rt_uint32_t index, int irq) +{ + RT_ASSERT(index < ARM_GIC_MAX_NR); + + irq = irq - _gic_table[index].offset; + RT_ASSERT(irq >= 0U); + + return (GIC_DIST_CONFIG(_gic_table[index].dist_hw_base, irq) >> ((irq % 16U) >> 1U)); +} + +void arm_gic_clear_active(rt_uint32_t index, int irq) +{ + rt_uint32_t mask = 1U << (irq % 32U); + + RT_ASSERT(index < ARM_GIC_MAX_NR); + + irq = irq - _gic_table[index].offset; + RT_ASSERT(irq >= 0U); + + GIC_DIST_ACTIVE_CLEAR(_gic_table[index].dist_hw_base, irq) = mask; +} + +/* Set up the cpu mask for the specific interrupt */ +void arm_gic_set_cpu(rt_uint32_t index, int irq, unsigned int cpumask) +{ + rt_uint32_t old_tgt; + + RT_ASSERT(index < ARM_GIC_MAX_NR); + + irq = irq - _gic_table[index].offset; + RT_ASSERT(irq >= 0U); + + old_tgt = GIC_DIST_TARGET(_gic_table[index].dist_hw_base, irq); + + old_tgt &= ~(0x0FFUL << ((irq % 4U) * 8U)); + old_tgt |= cpumask << ((irq % 4U) * 8U); + + GIC_DIST_TARGET(_gic_table[index].dist_hw_base, irq) = old_tgt; +} + +rt_uint32_t arm_gic_get_target_cpu(rt_uint32_t index, int irq) +{ + RT_ASSERT(index < ARM_GIC_MAX_NR); + + irq = irq - _gic_table[index].offset; + RT_ASSERT(irq >= 0U); + + return (GIC_DIST_TARGET(_gic_table[index].dist_hw_base, irq) >> ((irq % 4U) * 8U)) & 0xFFUL; +} + +void arm_gic_set_priority(rt_uint32_t index, int irq, rt_uint32_t priority) +{ + rt_uint32_t mask; + + RT_ASSERT(index < ARM_GIC_MAX_NR); + + irq = irq - _gic_table[index].offset; + RT_ASSERT(irq >= 0U); + + mask = GIC_DIST_PRI(_gic_table[index].dist_hw_base, irq); + mask &= ~(0xFFUL << ((irq % 4U) * 8U)); + mask |= ((priority & 0xFFUL) << ((irq % 4U) * 8U)); + GIC_DIST_PRI(_gic_table[index].dist_hw_base, irq) = mask; +} + +rt_uint32_t arm_gic_get_priority(rt_uint32_t index, int irq) +{ + RT_ASSERT(index < ARM_GIC_MAX_NR); + + irq = irq - _gic_table[index].offset; + RT_ASSERT(irq >= 0U); + + return (GIC_DIST_PRI(_gic_table[index].dist_hw_base, irq) >> ((irq % 4U) * 8U)) & 0xFFUL; +} + +void arm_gic_set_interface_prior_mask(rt_uint32_t index, rt_uint32_t priority) +{ + RT_ASSERT(index < ARM_GIC_MAX_NR); + + /* set priority mask */ + GIC_CPU_PRIMASK(_gic_table[index].cpu_hw_base) = priority & 0xFFUL; +} + +rt_uint32_t arm_gic_get_interface_prior_mask(rt_uint32_t index) +{ + RT_ASSERT(index < ARM_GIC_MAX_NR); + + return GIC_CPU_PRIMASK(_gic_table[index].cpu_hw_base); +} + +void arm_gic_set_binary_point(rt_uint32_t index, rt_uint32_t binary_point) +{ + GIC_CPU_BINPOINT(_gic_table[index].cpu_hw_base) = binary_point & 0x7U; +} + +rt_uint32_t arm_gic_get_binary_point(rt_uint32_t index) +{ + return GIC_CPU_BINPOINT(_gic_table[index].cpu_hw_base); +} + +rt_uint32_t arm_gic_get_irq_status(rt_uint32_t index, int irq) +{ + rt_uint32_t pending; + rt_uint32_t active; + + RT_ASSERT(index < ARM_GIC_MAX_NR); + + irq = irq - _gic_table[index].offset; + RT_ASSERT(irq >= 0U); + + active = (GIC_DIST_ACTIVE_SET(_gic_table[index].dist_hw_base, irq) >> (irq % 32U)) & 0x1UL; + pending = (GIC_DIST_PENDING_SET(_gic_table[index].dist_hw_base, irq) >> (irq % 32U)) & 0x1UL; + + return ((active << 1U) | pending); +} + +void arm_gic_send_sgi(rt_uint32_t index, int irq, rt_uint32_t target_list, rt_uint32_t filter_list) +{ + RT_ASSERT(index < ARM_GIC_MAX_NR); + + irq = irq - _gic_table[index].offset; + RT_ASSERT(irq >= 0U); + + GIC_DIST_SOFTINT(_gic_table[index].dist_hw_base) = ((filter_list & 0x3U) << 24U) | ((target_list & 0xFFUL) << 16U) | (irq & 0x0FUL); +} + +rt_uint32_t arm_gic_get_high_pending_irq(rt_uint32_t index) +{ + RT_ASSERT(index < ARM_GIC_MAX_NR); + + return GIC_CPU_HIGHPRI(_gic_table[index].cpu_hw_base); +} + +rt_uint32_t arm_gic_get_interface_id(rt_uint32_t index) +{ + RT_ASSERT(index < ARM_GIC_MAX_NR); + + return GIC_CPU_IIDR(_gic_table[index].cpu_hw_base); +} + +void arm_gic_set_group(rt_uint32_t index, int irq, rt_uint32_t group) +{ + uint32_t igroupr; + uint32_t shift; + + RT_ASSERT(index < ARM_GIC_MAX_NR); + RT_ASSERT(group <= 1U); + + irq = irq - _gic_table[index].offset; + RT_ASSERT(irq >= 0U); + + igroupr = GIC_DIST_IGROUP(_gic_table[index].dist_hw_base, irq); + shift = (irq % 32U); + igroupr &= (~(1U << shift)); + igroupr |= ((group & 0x1U) << shift); + + GIC_DIST_IGROUP(_gic_table[index].dist_hw_base, irq) = igroupr; +} + +rt_uint32_t arm_gic_get_group(rt_uint32_t index, int irq) +{ + RT_ASSERT(index < ARM_GIC_MAX_NR); + + irq = irq - _gic_table[index].offset; + RT_ASSERT(irq >= 0U); + + return (GIC_DIST_IGROUP(_gic_table[index].dist_hw_base, irq) >> (irq % 32U)) & 0x1UL; +} + +int arm_gic_dist_init(rt_uint32_t index, rt_uint32_t dist_base, int irq_start) +{ + unsigned int gic_type, i; + rt_uint32_t cpumask = 1U << 0U; + + RT_ASSERT(index < ARM_GIC_MAX_NR); + + _gic_table[index].dist_hw_base = dist_base; + _gic_table[index].offset = irq_start; + + /* Find out how many interrupts are supported. */ + gic_type = GIC_DIST_TYPE(dist_base); + _gic_max_irq = ((gic_type & 0x1fU) + 1U) * 32U; + + /* + * The GIC only supports up to 1020 interrupt sources. + * Limit this to either the architected maximum, or the + * platform maximum. + */ + if (_gic_max_irq > 1020U) + _gic_max_irq = 1020U; + if (_gic_max_irq > ARM_GIC_NR_IRQS) /* the platform maximum interrupts */ + _gic_max_irq = ARM_GIC_NR_IRQS; + + cpumask |= cpumask << 8U; + cpumask |= cpumask << 16U; + cpumask |= cpumask << 24U; + + GIC_DIST_CTRL(dist_base) = 0x0U; + + /* Set all global interrupts to be level triggered, active low. */ + for (i = 32U; i < _gic_max_irq; i += 16U) + GIC_DIST_CONFIG(dist_base, i) = 0x0U; + + /* Set all global interrupts to this CPU only. */ + for (i = 32U; i < _gic_max_irq; i += 4U) + GIC_DIST_TARGET(dist_base, i) = cpumask; + + /* Set priority on all interrupts. */ + for (i = 0U; i < _gic_max_irq; i += 4U) + GIC_DIST_PRI(dist_base, i) = 0xa0a0a0a0U; + + /* Disable all interrupts. */ + for (i = 0U; i < _gic_max_irq; i += 32U) + GIC_DIST_ENABLE_CLEAR(dist_base, i) = 0xffffffffU; + + /* Important: Below setting need be done in Secure world. */ + for (i = 0U; i < _gic_max_irq; i += 32U) + GIC_DIST_IGROUP(dist_base, i) = 0U; + + /* Enable group0 interrupt forwarding. */ + GIC_DIST_CTRL(dist_base) = 0x01U; + + return 0; +} + +int arm_gic_cpu_init(rt_uint32_t index, rt_uint32_t cpu_base) +{ + RT_ASSERT(index < ARM_GIC_MAX_NR); + + _gic_table[index].cpu_hw_base = cpu_base; + + GIC_CPU_PRIMASK(cpu_base) = 0xf0U; + GIC_CPU_BINPOINT(cpu_base) = 0x7U; + /* Enable CPU interrupt */ + GIC_CPU_CTRL(cpu_base) = 0x01U; + + return 0; +} + +void arm_gic_dump_type(rt_uint32_t index) +{ + unsigned int gic_type; + + gic_type = GIC_DIST_TYPE(_gic_table[index].dist_hw_base); + rt_kprintf("GICv%d on %p, max IRQs: %d, %s security extension(%08x)\n", + (GIC_DIST_ICPIDR2(_gic_table[index].dist_hw_base) >> 4U) & 0xfUL, + _gic_table[index].dist_hw_base, + _gic_max_irq, + gic_type & (1U << 10U) ? "has" : "no", + gic_type); +} + +void arm_gic_dump(rt_uint32_t index) +{ + unsigned int i, k; + + k = GIC_CPU_HIGHPRI(_gic_table[index].cpu_hw_base); + rt_kprintf("--- high pending priority: %d(%08x)\n", k, k); + rt_kprintf("--- hw mask ---\n"); + for (i = 0U; i < _gic_max_irq / 32U; i++) + { + rt_kprintf("0x%08x, ", + GIC_DIST_ENABLE_SET(_gic_table[index].dist_hw_base, + i * 32U)); + } + rt_kprintf("\n--- hw pending ---\n"); + for (i = 0U; i < _gic_max_irq / 32U; i++) + { + rt_kprintf("0x%08x, ", + GIC_DIST_PENDING_SET(_gic_table[index].dist_hw_base, + i * 32U)); + } + rt_kprintf("\n--- hw active ---\n"); + for (i = 0U; i < _gic_max_irq / 32U; i++) + { + rt_kprintf("0x%08x, ", + GIC_DIST_ACTIVE_SET(_gic_table[index].dist_hw_base, + i * 32U)); + } + rt_kprintf("\n"); +} + +long gic_dump(void) +{ + arm_gic_dump_type(0); + arm_gic_dump(0); + + return 0; +} +MSH_CMD_EXPORT(gic_dump, show gic status); + diff --git a/bsp/nuvoton/libraries/ma35/libcpu/aarch64/gic.h b/bsp/nuvoton/libraries/ma35/libcpu/aarch64/gic.h new file mode 100644 index 0000000000..c896442f8b --- /dev/null +++ b/bsp/nuvoton/libraries/ma35/libcpu/aarch64/gic.h @@ -0,0 +1,62 @@ +/* + * Copyright (c) 2006-2022, RT-Thread Development Team + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + * 2013-07-20 Bernard first version + */ + +#ifndef __GIC_H__ +#define __GIC_H__ + +#include +#include + +int arm_gic_get_active_irq(rt_uint32_t index); +void arm_gic_ack(rt_uint32_t index, int irq); + +void arm_gic_mask(rt_uint32_t index, int irq); +void arm_gic_umask(rt_uint32_t index, int irq); + +rt_uint32_t arm_gic_get_pending_irq(rt_uint32_t index, int irq); +void arm_gic_set_pending_irq(rt_uint32_t index, int irq); +void arm_gic_clear_pending_irq(rt_uint32_t index, int irq); + +void arm_gic_set_configuration(rt_uint32_t index, int irq, uint32_t config); +rt_uint32_t arm_gic_get_configuration(rt_uint32_t index, int irq); + +void arm_gic_clear_active(rt_uint32_t index, int irq); + +void arm_gic_set_cpu(rt_uint32_t index, int irq, unsigned int cpumask); +rt_uint32_t arm_gic_get_target_cpu(rt_uint32_t index, int irq); + +void arm_gic_set_priority(rt_uint32_t index, int irq, rt_uint32_t priority); +rt_uint32_t arm_gic_get_priority(rt_uint32_t index, int irq); + +void arm_gic_set_interface_prior_mask(rt_uint32_t index, rt_uint32_t priority); +rt_uint32_t arm_gic_get_interface_prior_mask(rt_uint32_t index); + +void arm_gic_set_binary_point(rt_uint32_t index, rt_uint32_t binary_point); +rt_uint32_t arm_gic_get_binary_point(rt_uint32_t index); + +rt_uint32_t arm_gic_get_irq_status(rt_uint32_t index, int irq); + +void arm_gic_send_sgi(rt_uint32_t index, int irq, rt_uint32_t target_list, rt_uint32_t filter_list); + +rt_uint32_t arm_gic_get_high_pending_irq(rt_uint32_t index); + +rt_uint32_t arm_gic_get_interface_id(rt_uint32_t index); + +void arm_gic_set_group(rt_uint32_t index, int irq, rt_uint32_t group); +rt_uint32_t arm_gic_get_group(rt_uint32_t index, int irq); + +int arm_gic_dist_init(rt_uint32_t index, rt_uint32_t dist_base, int irq_start); +int arm_gic_cpu_init(rt_uint32_t index, rt_uint32_t cpu_base); + +void arm_gic_dump_type(rt_uint32_t index); +void arm_gic_dump(rt_uint32_t index); + +#endif + diff --git a/bsp/nuvoton/libraries/ma35/libcpu/aarch64/gtimer.S b/bsp/nuvoton/libraries/ma35/libcpu/aarch64/gtimer.S new file mode 100644 index 0000000000..ed18ae8d41 --- /dev/null +++ b/bsp/nuvoton/libraries/ma35/libcpu/aarch64/gtimer.S @@ -0,0 +1,44 @@ +#include "rtconfig.h" + +/* + *enable gtimer + */ +.globl gtimer_set_control +gtimer_set_control: + MSR CNTP_CTL_EL0, X0 + RET + +/* + *set gtimer CNTP_TVAL_EL0 value + */ + +.globl gtimer_set_load_value +gtimer_set_load_value: + MSR CNTP_TVAL_EL0,X0 + RET + +/* + *get gtimer CNTP_TVAL_EL0 value + */ +.globl rt_hw_get_gtimer_val +rt_hw_get_gtimer_val: + MRS X0,CNTP_TVAL_EL0 + RET + +.globl gtimer_get_current_value +gtimer_get_current_value: + MRS X0,CNTP_TVAL_EL0 + RET + +.globl rt_hw_get_cntpct_val +rt_hw_get_cntpct_val: + MRS X0, CNTPCT_EL0 + RET + +/* + *get gtimer frq value + */ +.globl gtimer_get_counter_frequency +gtimer_get_counter_frequency: + MRS X0,CNTFRQ_EL0 + RET diff --git a/bsp/nuvoton/libraries/ma35/libcpu/aarch64/gtimer.h b/bsp/nuvoton/libraries/ma35/libcpu/aarch64/gtimer.h new file mode 100644 index 0000000000..2e1f33df50 --- /dev/null +++ b/bsp/nuvoton/libraries/ma35/libcpu/aarch64/gtimer.h @@ -0,0 +1,27 @@ +/* + * Copyright (c) 2006-2022, RT-Thread Development Team + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + * 2021-03-30 huijie.feng first version + */ + +#ifndef __GTIMER_H__ +#define __GTIMER_H__ + +#include + +void gtimer_set_counter_frequency(rt_uint32_t value); +rt_uint32_t gtimer_get_counter_frequency(void); +void gtimer_set_load_value(rt_uint32_t value); +rt_uint32_t gtimer_get_current_value(void); +rt_uint64_t gtimer_get_current_physical_value(void); +void gtimer_set_physical_compare_value(rt_uint64_t value); +rt_uint64_t gtimer_get_physical_compare_value(void); +void gtimer_set_control(rt_uint32_t value); +rt_uint32_t gtimer_get_control(void); + +#endif + diff --git a/bsp/nuvoton/libraries/ma35/libcpu/aarch64/interrupt.c b/bsp/nuvoton/libraries/ma35/libcpu/aarch64/interrupt.c new file mode 100644 index 0000000000..756fea0d09 --- /dev/null +++ b/bsp/nuvoton/libraries/ma35/libcpu/aarch64/interrupt.c @@ -0,0 +1,285 @@ +/* + * Copyright (c) 2006-2022, RT-Thread Development Team + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + * 2020-04-16 bigmagic first version + */ + +#include +#include +#include +#include +#include + +#define MAX_HANDLERS 256 +#define GIC_ACK_INTID_MASK 0x000003ff + +#ifdef RT_USING_SMP + #define rt_interrupt_nest rt_cpu_self()->irq_nest +#else + extern volatile rt_uint8_t rt_interrupt_nest; +#endif + +/* exception and interrupt handler table */ +struct rt_irq_desc isr_table[MAX_HANDLERS]; + +#ifndef RT_USING_SMP + /* Those varibles will be accessed in ISR, so we need to share them. */ + rt_ubase_t rt_interrupt_from_thread; + rt_ubase_t rt_interrupt_to_thread; + rt_ubase_t rt_thread_switch_interrupt_flag; +#endif + +extern int system_vectors; + +void rt_hw_vector_init(void) +{ + rt_hw_set_current_vbar((rt_ubase_t)&system_vectors); // cpu_gcc.S +} + +/** + * This function will initialize hardware interrupt + */ +void rt_hw_interrupt_init(void) +{ + rt_uint32_t gic_cpu_base; + rt_uint32_t gic_dist_base; + rt_uint32_t gic_irq_start; + + /* initialize vector table */ + rt_hw_vector_init(); + + /* initialize exceptions table */ + rt_memset(isr_table, 0x00, sizeof(isr_table)); + /* initialize ARM GIC */ + gic_dist_base = GIC_DISTRIBUTOR_BASE; + gic_cpu_base = GIC_INTERFACE_BASE; + gic_irq_start = GIC_IRQ_START; + + arm_gic_dist_init(0, gic_dist_base, gic_irq_start); + arm_gic_cpu_init(0, gic_cpu_base); +} + +/** + * This function will mask a interrupt. + * @param vector the interrupt number + */ +void rt_hw_interrupt_mask(int vector) +{ + arm_gic_mask(0, vector); +} + +/** + * This function will un-mask a interrupt. + * @param vector the interrupt number + */ +void rt_hw_interrupt_umask(int vector) +{ + arm_gic_umask(0, vector); +} + +/** + * This function returns the active interrupt number. + * @param none + */ +int rt_hw_interrupt_get_irq(void) +{ + return arm_gic_get_active_irq(0); +} + +/** + * This function acknowledges the interrupt. + * @param vector the interrupt number + */ +void rt_hw_interrupt_ack(int vector) +{ + arm_gic_ack(0, vector); +} + +/** + * This function set interrupt CPU targets. + * @param vector: the interrupt number + * cpu_mask: target cpus mask, one bit for one core + */ +void rt_hw_interrupt_set_target_cpus(int vector, unsigned int cpu_mask) +{ + arm_gic_set_cpu(0, vector, cpu_mask); +} + +/** + * This function get interrupt CPU targets. + * @param vector: the interrupt number + * @return target cpus mask, one bit for one core + */ +unsigned int rt_hw_interrupt_get_target_cpus(int vector) +{ + return arm_gic_get_target_cpu(0, vector); +} + +/** + * This function set interrupt triger mode. + * @param vector: the interrupt number + * mode: interrupt triger mode; 0: level triger, 1: edge triger + */ +void rt_hw_interrupt_set_triger_mode(int vector, unsigned int mode) +{ + arm_gic_set_configuration(0, vector, mode); +} + +/** + * This function get interrupt triger mode. + * @param vector: the interrupt number + * @return interrupt triger mode; 0: level triger, 1: edge triger + */ +unsigned int rt_hw_interrupt_get_triger_mode(int vector) +{ + return arm_gic_get_configuration(0, vector); +} + +/** + * This function set interrupt pending flag. + * @param vector: the interrupt number + */ +void rt_hw_interrupt_set_pending(int vector) +{ + arm_gic_set_pending_irq(0, vector); +} + +/** + * This function get interrupt pending flag. + * @param vector: the interrupt number + * @return interrupt pending flag, 0: not pending; 1: pending + */ +unsigned int rt_hw_interrupt_get_pending(int vector) +{ + return arm_gic_get_pending_irq(0, vector); +} + +/** + * This function clear interrupt pending flag. + * @param vector: the interrupt number + */ +void rt_hw_interrupt_clear_pending(int vector) +{ + arm_gic_clear_pending_irq(0, vector); +} + +/** + * This function set interrupt priority value. + * @param vector: the interrupt number + * priority: the priority of interrupt to set + */ +void rt_hw_interrupt_set_priority(int vector, unsigned int priority) +{ + arm_gic_set_priority(0, vector, priority); +} + +/** + * This function get interrupt priority. + * @param vector: the interrupt number + * @return interrupt priority value + */ +unsigned int rt_hw_interrupt_get_priority(int vector) +{ + return arm_gic_get_priority(0, vector); +} + +/** + * This function set priority masking threshold. + * @param priority: priority masking threshold + */ +void rt_hw_interrupt_set_priority_mask(unsigned int priority) +{ + arm_gic_set_interface_prior_mask(0, priority); +} + +/** + * This function get priority masking threshold. + * @param none + * @return priority masking threshold + */ +unsigned int rt_hw_interrupt_get_priority_mask(void) +{ + return arm_gic_get_interface_prior_mask(0); +} + +/** + * This function set priority grouping field split point. + * @param bits: priority grouping field split point + * @return 0: success; -1: failed + */ +int rt_hw_interrupt_set_prior_group_bits(unsigned int bits) +{ + int status; + + if (bits < 8) + { + arm_gic_set_binary_point(0, (7 - bits)); + status = 0; + } + else + { + status = -1; + } + + return (status); +} + +/** + * This function get priority grouping field split point. + * @param none + * @return priority grouping field split point + */ +unsigned int rt_hw_interrupt_get_prior_group_bits(void) +{ + unsigned int bp; + + bp = arm_gic_get_binary_point(0) & 0x07; + + return (7 - bp); +} + +/** + * This function will install a interrupt service routine to a interrupt. + * @param vector the interrupt number + * @param new_handler the interrupt service routine to be installed + * @param old_handler the old interrupt service routine + */ +rt_isr_handler_t rt_hw_interrupt_install(int vector, rt_isr_handler_t handler, + void *param, const char *name) +{ + rt_isr_handler_t old_handler = RT_NULL; + + if (vector < MAX_HANDLERS) + { + old_handler = isr_table[vector].handler; + + if (handler != RT_NULL) + { +#ifdef RT_USING_INTERRUPT_INFO + rt_strncpy(isr_table[vector].name, name, RT_NAME_MAX); +#endif /* RT_USING_INTERRUPT_INFO */ + isr_table[vector].handler = handler; + isr_table[vector].param = param; + } + } + + return old_handler; +} + +#ifdef RT_USING_SMP +void rt_hw_ipi_send(int ipi_vector, unsigned int cpu_mask) +{ + arm_gic_send_sgi(0, ipi_vector, cpu_mask, 0); +} + +void rt_hw_ipi_handler_install(int ipi_vector, rt_isr_handler_t ipi_isr_handler) +{ + /* note: ipi_vector maybe different with irq_vector */ + rt_hw_interrupt_install(ipi_vector, ipi_isr_handler, 0, "IPI_HANDLER"); +} +#endif + diff --git a/bsp/nuvoton/libraries/ma35/libcpu/aarch64/interrupt.h b/bsp/nuvoton/libraries/ma35/libcpu/aarch64/interrupt.h new file mode 100644 index 0000000000..27c62ad285 --- /dev/null +++ b/bsp/nuvoton/libraries/ma35/libcpu/aarch64/interrupt.h @@ -0,0 +1,55 @@ +/* + * Copyright (c) 2006-2022, RT-Thread Development Team + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + * 2020-04-16 bigmagic first version + */ + +#ifndef __INTERRUPT_H__ +#define __INTERRUPT_H__ + +#include +#include + +#define INT_IRQ 0x00 +#define INT_FIQ 0x01 + +void rt_hw_interrupt_init(void); +void rt_hw_interrupt_mask(int vector); +void rt_hw_interrupt_umask(int vector); + +int rt_hw_interrupt_get_irq(void); +void rt_hw_interrupt_ack(int vector); + +void rt_hw_interrupt_set_target_cpus(int vector, unsigned int cpu_mask); +unsigned int rt_hw_interrupt_get_target_cpus(int vector); + +void rt_hw_interrupt_set_triger_mode(int vector, unsigned int mode); +unsigned int rt_hw_interrupt_get_triger_mode(int vector); + +void rt_hw_interrupt_set_pending(int vector); +unsigned int rt_hw_interrupt_get_pending(int vector); +void rt_hw_interrupt_clear_pending(int vector); + +void rt_hw_interrupt_set_priority(int vector, unsigned int priority); +unsigned int rt_hw_interrupt_get_priority(int vector); + +void rt_hw_interrupt_set_priority_mask(unsigned int priority); +unsigned int rt_hw_interrupt_get_priority_mask(void); + +int rt_hw_interrupt_set_prior_group_bits(unsigned int bits); +unsigned int rt_hw_interrupt_get_prior_group_bits(void); + +rt_isr_handler_t rt_hw_interrupt_install(int vector, rt_isr_handler_t handler, + void *param, const char *name); + +#ifdef RT_USING_SMP + void rt_hw_ipi_send(int ipi_vector, unsigned int cpu_mask); + void rt_hw_ipi_handler_install(int ipi_vector, rt_isr_handler_t ipi_isr_handler); +#endif + +#endif + diff --git a/bsp/nuvoton/libraries/ma35/libcpu/aarch64/mmu.c b/bsp/nuvoton/libraries/ma35/libcpu/aarch64/mmu.c new file mode 100644 index 0000000000..3ce9ab2641 --- /dev/null +++ b/bsp/nuvoton/libraries/ma35/libcpu/aarch64/mmu.c @@ -0,0 +1,371 @@ +/* + * Copyright (c) 2006-2022, RT-Thread Development Team + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + * 2020-02-20 bigmagic first version + * 2021-06-25 Wayne Support EL3 + */ +#include +#include +#include + +#define TTBR_CNP 1 + +typedef unsigned long int uint64_t; + +static unsigned long main_tbl[512 * 20] __attribute__((aligned(4096))); + +#define IS_ALIGNED(x, a) (((x) & ((typeof(x))(a) - 1)) == 0) + +#define PMD_TYPE_SECT (1 << 0) + +#define PMD_TYPE_TABLE (3 << 0) + +#define PTE_TYPE_PAGE (3 << 0) + +#define BITS_PER_VA 39 + +/* Granule size of 4KB is being used */ +#define GRANULE_SIZE_SHIFT 12 +#define GRANULE_SIZE (1 << GRANULE_SIZE_SHIFT) +#define XLAT_ADDR_MASK ((1UL << BITS_PER_VA) - GRANULE_SIZE) + +#define PMD_TYPE_MASK (3 << 0) + +int free_idx = 1; + +void __asm_invalidate_icache_all(void); +void __asm_flush_dcache_all(void); +int __asm_flush_l3_cache(void); +void __asm_flush_dcache_range(unsigned long long start, unsigned long long end); +void __asm_invalidate_dcache_all(void); +void __asm_invalidate_icache_all(void); + +static void nonmmu_memset(char *dst, char v, size_t len) +{ + while (len--) + { + *dst++ = v; + } +} + +static unsigned long __page_off = 0; +static unsigned long get_free_page(void) +{ + __page_off += 512; + return (unsigned long)(main_tbl + __page_off); +} + + +static inline unsigned int get_sctlr(void) +{ + unsigned int val; + asm volatile("mrs %0, sctlr_el1" : "=r"(val) : : "cc"); + return val; +} + +static inline void set_sctlr(unsigned int val) +{ + asm volatile("msr sctlr_el1, %0" : : "r"(val) : "cc"); + asm volatile("isb"); +} + +void mmu_init(void) +{ + unsigned long val64; + unsigned long val32; + + val64 = 0x007f6eUL; + __asm__ volatile("msr MAIR_EL1, %0\n dsb sy\n"::"r"(val64)); + __asm__ volatile("mrs %0, MAIR_EL1\n dsb sy\n":"=r"(val64)); + + //TCR_EL1 + val32 = (16UL << 0)//48bit + | (0x0UL << 6) + | (0x0UL << 7) + | (0x3UL << 8) + | (0x3UL << 10)//Inner Shareable + | (0x2UL << 12) + | (0x0UL << 14)//4K + | (0x0UL << 16) + | (0x0UL << 22) + | (0x1UL << 23) + | (0x2UL << 30) + | (0x1UL << 32) + | (0x0UL << 35) + | (0x0UL << 36) + | (0x0UL << 37) + | (0x0UL << 38); + __asm__ volatile("msr TCR_EL1, %0\n"::"r"(val32)); + __asm__ volatile("mrs %0, TCR_EL1\n":"=r"(val32)); + + __asm__ volatile("msr TTBR0_EL1, %0\n dsb sy\n"::"r"(main_tbl)); + __asm__ volatile("mrs %0, TTBR0_EL1\n dsb sy\n":"=r"(val64)); + + nonmmu_memset((char *)main_tbl, 0, 4096); +} + +void mmu_enable(void) +{ + unsigned long val64; + unsigned long val32; + + __asm__ volatile("mrs %0, SCTLR_EL1\n":"=r"(val64)); + val64 &= ~0x1000; //disable I + __asm__ volatile("dmb sy\n msr SCTLR_EL1, %0\n isb sy\n"::"r"(val64)); + + __asm__ volatile("IC IALLUIS\n dsb sy\n isb sy\n"); + __asm__ volatile("tlbi vmalle1\n dsb sy\n isb sy\n"); + + //SCTLR_EL1, turn on mmu + __asm__ volatile("mrs %0, SCTLR_EL1\n":"=r"(val32)); + val32 |= 0x1005; //enable mmu, I C M + __asm__ volatile("dmb sy\n msr SCTLR_EL1, %0\nisb sy\n"::"r"(val32)); + rt_hw_icache_enable(); + rt_hw_dcache_enable(); + +} + +static int map_single_page_2M(unsigned long *lv0_tbl, unsigned long va, unsigned long pa, unsigned long attr) +{ + int level; + unsigned long *cur_lv_tbl = lv0_tbl; + unsigned long page; + unsigned long off; + int level_shift = 39; + + if (va & (0x200000UL - 1)) + { + return MMU_MAP_ERROR_VANOTALIGN; + } + if (pa & (0x200000UL - 1)) + { + return MMU_MAP_ERROR_PANOTALIGN; + } + for (level = 0; level < 2; level++) + { + off = (va >> level_shift); + off &= MMU_LEVEL_MASK; + if ((cur_lv_tbl[off] & 1) == 0) + { + page = get_free_page(); + if (!page) + { + return MMU_MAP_ERROR_NOPAGE; + } + nonmmu_memset((char *)page, 0, 4096); + cur_lv_tbl[off] = page | 0x3UL; + } + page = cur_lv_tbl[off]; + if (!(page & 0x2)) + { + //is block! error! + return MMU_MAP_ERROR_CONFLICT; + } + cur_lv_tbl = (unsigned long *)(page & 0x0000fffffffff000UL); + level_shift -= 9; + } + attr &= 0xfff0000000000ffcUL; + pa |= (attr | 0x1UL); //block + off = (va >> 21); + off &= MMU_LEVEL_MASK; + cur_lv_tbl[off] = pa; + return 0; +} + +int armv8_map_2M(unsigned long va, unsigned long pa, int count, unsigned long attr) +{ + int i; + int ret; + + if (va & (0x200000 - 1)) + { + return -1; + } + if (pa & (0x200000 - 1)) + { + return -1; + } + for (i = 0; i < count; i++) + { + ret = map_single_page_2M((unsigned long *)main_tbl, va, pa, attr); + va += 0x200000; + pa += 0x200000; + if (ret != 0) + { + return ret; + } + } + return 0; +} + +static void set_table(uint64_t *pt, uint64_t *table_addr) +{ + uint64_t val; + val = (0x3UL | (uint64_t)table_addr); + *pt = val; +} + +static uint64_t *create_table(void) +{ + uint64_t *new_table = (uint64_t *)((unsigned char *)&main_tbl[0] + free_idx * 4096); //+ free_idx * GRANULE_SIZE; + /* Mark all entries as invalid */ + nonmmu_memset((char *)new_table, 0, 4096); + free_idx++; + return new_table; +} + +static int pte_type(uint64_t *pte) +{ + return *pte & PMD_TYPE_MASK; +} + +static int level2shift(int level) +{ + /* Page is 12 bits wide, every level translates 9 bits */ + return (12 + 9 * (3 - level)); +} + +static uint64_t *get_level_table(uint64_t *pte) +{ + uint64_t *table = (uint64_t *)(*pte & XLAT_ADDR_MASK); + + if (pte_type(pte) != PMD_TYPE_TABLE) + { + table = create_table(); + set_table(pte, table); + } + return table; +} + +static void map_region(uint64_t virt, uint64_t phys, uint64_t size, uint64_t attr) +{ + uint64_t block_size = 0; + uint64_t block_shift = 0; + uint64_t *pte; + uint64_t idx = 0; + uint64_t addr = 0; + uint64_t *table = 0; + int level = 0; + + addr = virt; + while (size) + { + table = &main_tbl[0]; + for (level = 0; level < 4; level++) + { + block_shift = level2shift(level); + idx = addr >> block_shift; + idx = idx % 512; + block_size = (uint64_t)(1L << block_shift); + pte = table + idx; + + if (size >= block_size && IS_ALIGNED(addr, block_size)) + { + attr &= 0xfff0000000000ffcUL; + if (level != 3) + { + *pte = phys | (attr | 0x1UL); + } + else + { + *pte = phys | (attr | 0x3UL); + } + addr += block_size; + phys += block_size; + size -= block_size; + break; + } + table = get_level_table(pte); + } + } +} + +void armv8_map(unsigned long va, unsigned long pa, unsigned long size, unsigned long attr) +{ + map_region(va, pa, size, attr); +} + +void rt_hw_dcache_enable(void) +{ + if (!(get_sctlr() & CR_M)) + { + rt_kprintf("please init mmu!\n"); + } + else + { + set_sctlr(get_sctlr() | CR_C); + } +} + +void rt_hw_dcache_flush_all(void) +{ + int ret; + + __asm_flush_dcache_all(); + ret = __asm_flush_l3_cache(); + if (ret) + { + rt_kprintf("flushing dcache returns 0x%x\n", ret); + } + else + { + rt_kprintf("flushing dcache successfully.\n"); + } +} + +void rt_hw_dcache_flush_range(unsigned long start_addr, unsigned long size) +{ + __asm_flush_dcache_range(start_addr, start_addr + size); +} + +void rt_hw_dcache_invalidate_range(unsigned long start_addr, unsigned long size) +{ + __asm_flush_dcache_range(start_addr, start_addr + size); +} + +void rt_hw_cpu_dcache_clean_inv(unsigned long start_addr, unsigned long size) +{ + __asm_flush_dcache_range(start_addr, start_addr + size); +} + +void rt_hw_cpu_dcache_invalidate(void *start_addr, int size) +{ + rt_hw_dcache_invalidate_range((unsigned long)start_addr, (unsigned long)size); +} + +void rt_hw_dcache_invalidate_all(void) +{ + __asm_invalidate_dcache_all(); +} + +void rt_hw_dcache_disable(void) +{ + /* if cache isn't enabled no need to disable */ + if (!(get_sctlr() & CR_C)) + { + rt_kprintf("need enable cache!\n"); + return; + } + set_sctlr(get_sctlr() & ~CR_C); +} + +//icache +void rt_hw_icache_enable(void) +{ + __asm_invalidate_icache_all(); + set_sctlr(get_sctlr() | CR_I); +} + +void rt_hw_icache_invalidate_all(void) +{ + __asm_invalidate_icache_all(); +} + +void rt_hw_icache_disable(void) +{ + set_sctlr(get_sctlr() & ~CR_I); +} diff --git a/bsp/nuvoton/libraries/ma35/libcpu/aarch64/mmu.h b/bsp/nuvoton/libraries/ma35/libcpu/aarch64/mmu.h new file mode 100644 index 0000000000..8295116c08 --- /dev/null +++ b/bsp/nuvoton/libraries/ma35/libcpu/aarch64/mmu.h @@ -0,0 +1,78 @@ +/* + * Copyright (c) 2006-2022, RT-Thread Development Team + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + * 2020-02-20 bigmagic first version + */ + +#ifndef __MMU_H__ +#define __MMU_H__ + +/* + * CR1 bits (CP#15 CR1) + */ +#define CR_M (1 << 0) /* MMU enable */ +#define CR_A (1 << 1) /* Alignment abort enable */ +#define CR_C (1 << 2) /* Dcache enable */ +#define CR_W (1 << 3) /* Write buffer enable */ +#define CR_P (1 << 4) /* 32-bit exception handler */ +#define CR_D (1 << 5) /* 32-bit data address range */ +#define CR_L (1 << 6) /* Implementation defined */ +#define CR_B (1 << 7) /* Big endian */ +#define CR_S (1 << 8) /* System MMU protection */ +#define CR_R (1 << 9) /* ROM MMU protection */ +#define CR_F (1 << 10) /* Implementation defined */ +#define CR_Z (1 << 11) /* Implementation defined */ +#define CR_I (1 << 12) /* Icache enable */ +#define CR_V (1 << 13) /* Vectors relocated to 0xffff0000 */ +#define CR_RR (1 << 14) /* Round Robin cache replacement */ +#define CR_L4 (1 << 15) /* LDR pc can set T bit */ +#define CR_DT (1 << 16) +#define CR_IT (1 << 18) +#define CR_ST (1 << 19) +#define CR_FI (1 << 21) /* Fast interrupt (lower latency mode) */ +#define CR_U (1 << 22) /* Unaligned access operation */ +#define CR_XP (1 << 23) /* Extended page tables */ +#define CR_VE (1 << 24) /* Vectored interrupts */ +#define CR_EE (1 << 25) /* Exception (Big) Endian */ +#define CR_TRE (1 << 28) /* TEX remap enable */ +#define CR_AFE (1 << 29) /* Access flag enable */ +#define CR_TE (1 << 30) /* Thumb exception enable */ + +#define MMU_LEVEL_MASK 0x1ffUL +#define MMU_MAP_ERROR_VANOTALIGN -1 +#define MMU_MAP_ERROR_PANOTALIGN -2 +#define MMU_MAP_ERROR_NOPAGE -3 +#define MMU_MAP_ERROR_CONFLICT -4 + +#define MEM_ATTR_MEMORY ((0x1UL << 10) | (0x2UL << 8) | (0x0UL << 6) | (0x1UL << 2)) +#define MEM_ATTR_IO ((0x1UL << 10) | (0x2UL << 8) | (0x0UL << 6) | (0x2UL << 2)) + +#define BUS_ADDRESS(phys) (((phys) & ~0xC0000000) | 0xC0000000) + +void mmu_init(void); + +void mmu_enable(void); + +int armv8_map_2M(unsigned long va, unsigned long pa, int count, unsigned long attr); + +void armv8_map(unsigned long va, unsigned long pa, unsigned long size, unsigned long attr); + +//dcache +void rt_hw_dcache_enable(void); +void rt_hw_dcache_flush_all(void); +void rt_hw_dcache_flush_range(unsigned long start_addr, unsigned long size); +void rt_hw_dcache_invalidate_range(unsigned long start_addr, unsigned long size); +void rt_hw_dcache_invalidate_all(void); +void rt_hw_dcache_disable(void); + +//icache +void rt_hw_icache_enable(void); +void rt_hw_icache_invalidate_all(void); +void rt_hw_icache_disable(void); + + +#endif /*__MMU_H__*/ diff --git a/bsp/nuvoton/libraries/ma35/libcpu/aarch64/secondary_cpu.c b/bsp/nuvoton/libraries/ma35/libcpu/aarch64/secondary_cpu.c new file mode 100644 index 0000000000..bb1ab62974 --- /dev/null +++ b/bsp/nuvoton/libraries/ma35/libcpu/aarch64/secondary_cpu.c @@ -0,0 +1,71 @@ +/* + * Copyright (c) 2006-2022, RT-Thread Development Team + * + * SPDX-License-Identifier: Apache-2.0 + * + * Date Author Notes + * 2021-06-17 Wayne the first version + */ + +#include +#include "board.h" +#include "gic.h" +#include "cp15.h" + +#ifdef RT_USING_SMP +#include "interrupt.h" + +extern int rt_hw_timer_init(void); +extern void secondary_cpu_start(void); + +/* + For core-1, core-2 and core-3. +*/ +void rt_hw_secondary_cpu_up(void) +{ + rt_uint32_t cpu_mask = 2; + rt_int32_t i; + + rt_cpu_dcache_clean_flush(); + rt_cpu_icache_flush(); + + rt_kprintf("rt_hw_secondary_cpu_up is processing \r\n"); + for (i = 1; i < RT_CPUS_NR, i != 4; i++) + { + rt_kprintf("Boot Core-%d\n", i); + //FPsci_CpuOn(1 << i, (rt_uint32_t)secondary_cpu_start); + cpu_mask <<= 1; + __SEV(); + __DSB(); + __ISB(); + + __DSB(); + rt_hw_ipi_send(RT_SCHEDULE_IPI, cpu_mask); + } +} + +void secondary_cpu_c_start(void) +{ + uint32_t id = rt_hw_cpu_id(); + rt_kprintf("cpu = 0x%08x\n", id); + + rt_hw_timer_init(); + + /* initialize vector table */ + rt_hw_vector_init(); + + rt_hw_spin_lock(&_cpus_lock); + + rt_hw_interrupt_set_priority(RT_SCHEDULE_IPI, 16); + rt_hw_interrupt_umask(RT_SCHEDULE_IPI); + + rt_system_scheduler_start(); +} + +void rt_hw_secondary_cpu_idle_exec(void) +{ + asm volatile("wfe" :: + : "memory", "cc"); +} + +#endif diff --git a/bsp/nuvoton/libraries/ma35/libcpu/aarch64/stack.c b/bsp/nuvoton/libraries/ma35/libcpu/aarch64/stack.c new file mode 100644 index 0000000000..5f41d391b4 --- /dev/null +++ b/bsp/nuvoton/libraries/ma35/libcpu/aarch64/stack.c @@ -0,0 +1,90 @@ +/* + * Copyright (c) 2006-2022, RT-Thread Development Team + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + * 2011-09-23 Bernard the first version + * 2011-10-05 Bernard add thumb mode + */ +#include +#include + +#include + +#define INITIAL_SPSR_EL3 (PSTATE_EL3 | SP_EL0) +#define INITIAL_SPSR_EL2 (PSTATE_EL2 | SP_EL0) +#define INITIAL_SPSR_EL1 (PSTATE_EL1 | SP_EL0) + +/** + * This function will initialize thread stack + * + * @param tentry the entry of thread + * @param parameter the parameter of entry + * @param stack_addr the beginning stack address + * @param texit the function will be called when thread exit + * + * @return stack address + */ +rt_uint8_t *rt_hw_stack_init(void *tentry, void *parameter, + rt_uint8_t *stack_addr, void *texit) +{ + rt_ubase_t *stk; + rt_ubase_t current_el; + + stk = (rt_ubase_t *)stack_addr; + + *(--stk) = (rt_ubase_t) 11; /* X1 */ + *(--stk) = (rt_ubase_t) parameter; /* X0 */ + *(--stk) = (rt_ubase_t) 33; /* X3 */ + *(--stk) = (rt_ubase_t) 22; /* X2 */ + *(--stk) = (rt_ubase_t) 55; /* X5 */ + *(--stk) = (rt_ubase_t) 44; /* X4 */ + *(--stk) = (rt_ubase_t) 77; /* X7 */ + *(--stk) = (rt_ubase_t) 66; /* X6 */ + *(--stk) = (rt_ubase_t) 99; /* X9 */ + *(--stk) = (rt_ubase_t) 88; /* X8 */ + *(--stk) = (rt_ubase_t) 11; /* X11 */ + *(--stk) = (rt_ubase_t) 10; /* X10 */ + *(--stk) = (rt_ubase_t) 13; /* X13 */ + *(--stk) = (rt_ubase_t) 12; /* X12 */ + *(--stk) = (rt_ubase_t) 15; /* X15 */ + *(--stk) = (rt_ubase_t) 14; /* X14 */ + *(--stk) = (rt_ubase_t) 17; /* X17 */ + *(--stk) = (rt_ubase_t) 16; /* X16 */ + *(--stk) = (rt_ubase_t) 19; /* X19 */ + *(--stk) = (rt_ubase_t) 18; /* X18 */ + *(--stk) = (rt_ubase_t) 21; /* X21 */ + *(--stk) = (rt_ubase_t) 20; /* X20 */ + *(--stk) = (rt_ubase_t) 23; /* X23 */ + *(--stk) = (rt_ubase_t) 22; /* X22 */ + *(--stk) = (rt_ubase_t) 25; /* X25 */ + *(--stk) = (rt_ubase_t) 24; /* X24 */ + *(--stk) = (rt_ubase_t) 27; /* X27 */ + *(--stk) = (rt_ubase_t) 26; /* X26 */ + *(--stk) = (rt_ubase_t) 29; /* X29 */ + *(--stk) = (rt_ubase_t) 28; /* X28 */ + *(--stk) = (rt_ubase_t) 0; /* XZR - has no effect, used so there are an even number of registers. */ + *(--stk) = (rt_ubase_t) texit; /* X30 - procedure call link register. */ + + current_el = rt_hw_get_current_el(); + + if (current_el == 3) + { + *(--stk) = INITIAL_SPSR_EL3; + } + else if (current_el == 2) + { + *(--stk) = INITIAL_SPSR_EL2; + } + else + { + *(--stk) = INITIAL_SPSR_EL1; + } + + *(--stk) = (rt_ubase_t) tentry; /* Exception return address. */ + + /* return task's current stack address */ + return (rt_uint8_t *)stk; +} diff --git a/bsp/nuvoton/libraries/ma35/libcpu/aarch64/trap.c b/bsp/nuvoton/libraries/ma35/libcpu/aarch64/trap.c new file mode 100644 index 0000000000..a4f837c05d --- /dev/null +++ b/bsp/nuvoton/libraries/ma35/libcpu/aarch64/trap.c @@ -0,0 +1,114 @@ +/* + * Copyright (c) 2006-2022, RT-Thread Development Team + * + * SPDX-License-Identifier: Apache-2.0 + * + * Date Author Notes + * 2018-10-06 ZhaoXiaowei the first version + */ + +#include +#include + +#include "interrupt.h" +#include "armv8.h" + +extern struct rt_thread *rt_current_thread; +#ifdef RT_USING_FINSH + extern long list_thread(void); +#endif + +/** + * this function will show registers of CPU + * + * @param regs the registers point + */ +void rt_hw_show_register(struct rt_hw_exp_stack *regs) +{ + rt_kprintf("Execption:\n"); + rt_kprintf("r00:0x%16.16lx r01:0x%16.16lx r02:0x%16.16lx r03:0x%16.16lx\n", regs->x0, regs->x1, regs->x2, regs->x3); + rt_kprintf("r04:0x%16.16lx r05:0x%16.16lx r06:0x%16.16lx r07:0x%16.16lx\n", regs->x4, regs->x5, regs->x6, regs->x7); + rt_kprintf("r08:0x%16.16lx r09:0x%16.16lx r10:0x%16.16lx r11:0x%16.16lx\n", regs->x8, regs->x9, regs->x10, regs->x11); + rt_kprintf("r12:0x%16.16lx r13:0x%16.16lx r14:0x%16.16lx r15:0x%16.16lx\n", regs->x12, regs->x13, regs->x14, regs->x15); + rt_kprintf("r16:0x%16.16lx r17:0x%16.16lx r18:0x%16.16lx r19:0x%16.16lx\n", regs->x16, regs->x17, regs->x18, regs->x19); + rt_kprintf("r20:0x%16.16lx r21:0x%16.16lx r22:0x%16.16lx r23:0x%16.16lx\n", regs->x20, regs->x21, regs->x22, regs->x23); + rt_kprintf("r24:0x%16.16lx r25:0x%16.16lx r26:0x%16.16lx r27:0x%16.16lx\n", regs->x24, regs->x25, regs->x26, regs->x27); + rt_kprintf("r28:0x%16.16lx r29:0x%16.16lx r30:0x%16.16lx\n", regs->x28, regs->x29, regs->x30); + rt_kprintf("spsr:0x%16.16lx\n", regs->spsr); + rt_kprintf("return pc:0x%16.16lx\n", regs->pc); +} + +/** + * When comes across an instruction which it cannot handle, + * it takes the undefined instruction trap. + * + * @param regs system registers + * + * @note never invoke this function in application + */ +void rt_hw_trap_error(struct rt_hw_exp_stack *regs) +{ + rt_kprintf("error exception:\n"); + rt_hw_show_register(regs); +#ifdef RT_USING_FINSH + list_thread(); +#endif + rt_hw_cpu_shutdown(); +} + +#define GIC_ACK_INTID_MASK 0x000003ff + + +void rt_hw_trap_irq(void) +{ + void *param; + int ir; + rt_isr_handler_t isr_func; + extern struct rt_irq_desc isr_table[]; + + ir = rt_hw_interrupt_get_irq(); + if (ir == 1023) + { + /* Spurious interrupt */ + return; + } + + /* get interrupt service routine */ + isr_func = isr_table[ir].handler; +#ifdef RT_USING_INTERRUPT_INFO + isr_table[ir].counter++; +#endif + if (isr_func) + { + /* Interrupt for myself. */ + param = isr_table[ir].param; + /* turn to interrupt service routine */ + isr_func(ir, param); + } + + /* end of interrupt */ + rt_hw_interrupt_ack(ir); +} + +void rt_hw_trap_fiq(void) +{ + void *param; + int ir; + rt_isr_handler_t isr_func; + extern struct rt_irq_desc isr_table[]; + + ir = rt_hw_interrupt_get_irq(); + + /* get interrupt service routine */ + isr_func = isr_table[ir].handler; + if (isr_func) + { + param = isr_table[ir].param; + + /* turn to interrupt service routine */ + isr_func(ir, param); + } + + /* end of interrupt */ + rt_hw_interrupt_ack(ir); +} diff --git a/bsp/nuvoton/libraries/ma35/libcpu/aarch64/vector_gcc.S b/bsp/nuvoton/libraries/ma35/libcpu/aarch64/vector_gcc.S new file mode 100644 index 0000000000..fc88cce7f8 --- /dev/null +++ b/bsp/nuvoton/libraries/ma35/libcpu/aarch64/vector_gcc.S @@ -0,0 +1,61 @@ +/* + * Copyright (c) 2006-2020, RT-Thread Development Team + * + * SPDX-License-Identifier: Apache-2.0 + * + * Date Author Notes + * 2018-10-06 ZhaoXiaowei the first version + */ + +.text + +.globl system_vectors +.globl vector_error +.globl vector_irq +.globl vector_fiq + +system_vectors: +.align 11 + .set VBAR, system_vectors + .org VBAR + // Exception from CurrentEL (EL1) with SP_EL0 (SPSEL=1) + .org (VBAR + 0x00 + 0) + B vector_error // Synchronous + .org (VBAR + 0x80 + 0) + B vector_irq // IRQ/vIRQ + .org (VBAR + 0x100 + 0) + B vector_fiq // FIQ/vFIQ + .org (VBAR + 0x180 + 0) + B vector_error // Error/vError + + // Exception from CurrentEL (EL1) with SP_ELn + .org (VBAR + 0x200 + 0) + B vector_error // Synchronous + .org (VBAR + 0x280 + 0) + B vector_irq // IRQ/vIRQ + .org (VBAR + 0x300 + 0) + B vector_fiq // FIQ/vFIQ + .org (VBAR + 0x380 + 0) + B vector_error + + // Exception from lower EL, aarch64 + .org (VBAR + 0x400 + 0) + B vector_error + .org (VBAR + 0x480 + 0) + B vector_error + .org (VBAR + 0x500 + 0) + B vector_error + .org (VBAR + 0x580 + 0) + B vector_error + + // Exception from lower EL, aarch32 + .org (VBAR + 0x600 + 0) + B vector_error + .org (VBAR + 0x680 + 0) + B vector_error + .org (VBAR + 0x700 + 0) + B vector_error + .org (VBAR + 0x780 + 0) + B vector_error + .org (VBAR + 0x800 + 0) + B vector_error diff --git a/bsp/nuvoton/libraries/ma35/libcpu/arm/SConscript b/bsp/nuvoton/libraries/ma35/libcpu/arm/SConscript new file mode 100644 index 0000000000..0bf1ca703a --- /dev/null +++ b/bsp/nuvoton/libraries/ma35/libcpu/arm/SConscript @@ -0,0 +1,17 @@ +# RT-Thread building script for bridge + +import os +from building import * + +Import('rtconfig') + +cwd = GetCurrentDir() +list = os.listdir(cwd) + +group = [] + +# cpu porting code files +if rtconfig.CPU in list: + group = group + SConscript(os.path.join(rtconfig.CPU, 'SConscript')) + +Return('group') diff --git a/bsp/nuvoton/libraries/ma35/libcpu/arm/cortex-a/SConscript b/bsp/nuvoton/libraries/ma35/libcpu/arm/cortex-a/SConscript new file mode 100644 index 0000000000..337a027276 --- /dev/null +++ b/bsp/nuvoton/libraries/ma35/libcpu/arm/cortex-a/SConscript @@ -0,0 +1,14 @@ +# RT-Thread building script for component + +Import('RTT_ROOT') +from building import * + +cwd = GetCurrentDir() +src = Glob('*.c') + Glob('*.cpp') +CPPPATH = [cwd] +group = [] + +# USB driver constrain +group = DefineGroup('CPU', src, depend = [''], CPPPATH = CPPPATH) + +Return('group') diff --git a/bsp/nuvoton/libraries/ma35/libcpu/arm/cortex-a/gtimer.c b/bsp/nuvoton/libraries/ma35/libcpu/arm/cortex-a/gtimer.c new file mode 100644 index 0000000000..149230a00e --- /dev/null +++ b/bsp/nuvoton/libraries/ma35/libcpu/arm/cortex-a/gtimer.c @@ -0,0 +1,179 @@ +/* + * Copyright (c) 2006-2022, RT-Thread Development Team + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + * 2021-03-30 huijie.feng first version + */ + +#include "cp15.h" +#include + +/** Set CNTFRQ + * This function assigns the given value to PL1 Physical Timer Counter Frequency Register (CNTFRQ). + * @param value: CNTFRQ Register value to set + */ +static inline void __set_cntfrq(rt_uint32_t value) +{ + __set_cp(15, 0, value, 14, 0, 0); +} + +/** Get CNTFRQ + * This function returns the value of the PL1 Physical Timer Counter Frequency Register (CNTFRQ). + * return CNTFRQ Register value + */ +static inline rt_uint32_t __get_cntfrq(void) +{ + rt_uint32_t result; + __get_cp(15, 0, result, 14, 0, 0); + return result; +} + +/** Set CNTP_TVAL + * This function assigns the given value to PL1 Physical Timer Value Register (CNTP_TVAL). + * param value: CNTP_TVAL Register value to set + */ +static inline void __set_cntp_tval(rt_uint32_t value) +{ + __set_cp(15, 0, value, 14, 2, 0); +} + +/** Get CNTP_TVAL + * This function returns the value of the PL1 Physical Timer Value Register (CNTP_TVAL). + * return CNTP_TVAL Register value + */ +static inline rt_uint32_t __get_cntp_tval(void) +{ + rt_uint32_t result; + __get_cp(15, 0, result, 14, 2, 0); + return result; +} + +/** Get CNTPCT + * This function returns the value of the 64 bits PL1 Physical Count Register (CNTPCT). + * return CNTPCT Register value + */ +static inline rt_uint64_t __get_cntpct(void) +{ + rt_uint64_t result; + __get_cp64(15, 0, result, 14); + return result; +} + +/** Set CNTP_CVAL + * This function assigns the given value to 64bits PL1 Physical Timer CompareValue Register (CNTP_CVAL). + * param value: CNTP_CVAL Register value to set +*/ +static inline void __set_cntp_cval(rt_uint64_t value) +{ + __set_cp64(15, 2, value, 14); +} + +/** Get CNTP_CVAL + * This function returns the value of the 64 bits PL1 Physical Timer CompareValue Register (CNTP_CVAL). + * return CNTP_CVAL Register value + */ +static inline rt_uint64_t __get_cntp_cval(void) +{ + rt_uint64_t result; + __get_cp64(15, 2, result, 14); + return result; +} + +/** Set CNTP_CTL + * This function assigns the given value to PL1 Physical Timer Control Register (CNTP_CTL). + * param value: CNTP_CTL Register value to set + */ +static inline void __set_cntp_ctl(rt_uint32_t value) +{ + __set_cp(15, 0, value, 14, 2, 1); +} + +/** Get CNTP_CTL register + * return CNTP_CTL Register value + */ +static inline rt_uint32_t __get_cntp_ctl(void) +{ + rt_uint32_t result; + __get_cp(15, 0, result, 14, 2, 1); + return result; +} + +/** Configures the frequency the timer shall run at. + * param value The timer frequency in Hz. + */ +void gtimer_set_counter_frequency(rt_uint32_t value) +{ + __set_cntfrq(value); + __asm__ volatile("isb 0xF":::"memory"); +} + +/** Get the frequency the timer shall run at. + * return timer frequency in Hz. + */ +rt_uint32_t gtimer_get_counter_frequency(void) +{ + return (__get_cntfrq()); +} + +/** Sets the reset value of the timer. + * param value: The value the timer is loaded with. + */ +void gtimer_set_load_value(rt_uint32_t value) +{ + __set_cntp_tval(value); + __asm__ volatile("isb 0xF":::"memory"); +} + +/** Get the current counter value. + * return Current counter value. + */ +rt_uint32_t gtimer_get_current_value(void) +{ + return (__get_cntp_tval()); +} + +/** Get the current physical counter value. + * return Current physical counter value. + */ +rt_uint64_t gtimer_get_current_physical_value(void) +{ + return (__get_cntpct()); +} + +/** Set the physical compare value. + * param value: New physical timer compare value. + */ +void gtimer_set_physical_compare_value(rt_uint64_t value) +{ + __set_cntp_cval(value); + __asm__ volatile("isb 0xF":::"memory"); +} + +/** Get the physical compare value. + * return Physical compare value. + */ +rt_uint64_t gtimer_get_physical_compare_value(void) +{ + return (__get_cntp_cval()); +} + +/** Configure the timer by setting the control value. + * param value: New timer control value. + */ +void gtimer_set_control(rt_uint32_t value) +{ + __set_cntp_ctl(value); + __asm__ volatile("isb 0xF":::"memory"); +} + +/** Get the control value. + * return Control value. + */ +rt_uint32_t gtimer_get_control(void) +{ + return (__get_cntp_ctl()); +} + diff --git a/bsp/nuvoton/libraries/ma35/libcpu/arm/cortex-a/gtimer.h b/bsp/nuvoton/libraries/ma35/libcpu/arm/cortex-a/gtimer.h new file mode 100644 index 0000000000..2e1f33df50 --- /dev/null +++ b/bsp/nuvoton/libraries/ma35/libcpu/arm/cortex-a/gtimer.h @@ -0,0 +1,27 @@ +/* + * Copyright (c) 2006-2022, RT-Thread Development Team + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + * 2021-03-30 huijie.feng first version + */ + +#ifndef __GTIMER_H__ +#define __GTIMER_H__ + +#include + +void gtimer_set_counter_frequency(rt_uint32_t value); +rt_uint32_t gtimer_get_counter_frequency(void); +void gtimer_set_load_value(rt_uint32_t value); +rt_uint32_t gtimer_get_current_value(void); +rt_uint64_t gtimer_get_current_physical_value(void); +void gtimer_set_physical_compare_value(rt_uint64_t value); +rt_uint64_t gtimer_get_physical_compare_value(void); +void gtimer_set_control(rt_uint32_t value); +rt_uint32_t gtimer_get_control(void); + +#endif + diff --git a/bsp/nuvoton/libraries/ma35/libcpu/arm/cortex-a/pmu.c b/bsp/nuvoton/libraries/ma35/libcpu/arm/cortex-a/pmu.c new file mode 100644 index 0000000000..0f1975dfc0 --- /dev/null +++ b/bsp/nuvoton/libraries/ma35/libcpu/arm/cortex-a/pmu.c @@ -0,0 +1,20 @@ +/* + * Copyright (c) 2006-2022, RT-Thread Development Team + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + */ +#include +#include "pmu.h" + +void rt_hw_pmu_dump_feature(void) +{ + unsigned long reg; + + reg = rt_hw_pmu_get_control(); + rt_kprintf("ARM PMU Implementor: %c, ID code: %02x, %d counters\n", + reg >> 24, (reg >> 16) & 0xff, (reg >> 11) & 0x1f); + RT_ASSERT(ARM_PMU_CNTER_NR == ((reg >> 11) & 0x1f)); +} diff --git a/bsp/nuvoton/libraries/ma35/libcpu/arm/cortex-a/pmu.h b/bsp/nuvoton/libraries/ma35/libcpu/arm/cortex-a/pmu.h new file mode 100644 index 0000000000..f8dcf1d584 --- /dev/null +++ b/bsp/nuvoton/libraries/ma35/libcpu/arm/cortex-a/pmu.h @@ -0,0 +1,160 @@ +/* + * Copyright (c) 2006-2022, RT-Thread Development Team + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + */ +#ifndef __PMU_H__ +#define __PMU_H__ + +#include "board.h" + +/* Number of counters */ +#define ARM_PMU_CNTER_NR 4 + +enum rt_hw_pmu_event_type +{ + ARM_PMU_EVENT_PMNC_SW_INCR = 0x00, + ARM_PMU_EVENT_L1_ICACHE_REFILL = 0x01, + ARM_PMU_EVENT_ITLB_REFILL = 0x02, + ARM_PMU_EVENT_L1_DCACHE_REFILL = 0x03, + ARM_PMU_EVENT_L1_DCACHE_ACCESS = 0x04, + ARM_PMU_EVENT_DTLB_REFILL = 0x05, + ARM_PMU_EVENT_MEM_READ = 0x06, + ARM_PMU_EVENT_MEM_WRITE = 0x07, + ARM_PMU_EVENT_INSTR_EXECUTED = 0x08, + ARM_PMU_EVENT_EXC_TAKEN = 0x09, + ARM_PMU_EVENT_EXC_EXECUTED = 0x0A, + ARM_PMU_EVENT_CID_WRITE = 0x0B, +}; + +/* Enable bit */ +#define ARM_PMU_PMCR_E (0x01 << 0) +/* Event counter reset */ +#define ARM_PMU_PMCR_P (0x01 << 1) +/* Cycle counter reset */ +#define ARM_PMU_PMCR_C (0x01 << 2) +/* Cycle counter divider */ +#define ARM_PMU_PMCR_D (0x01 << 3) + +#ifdef __GNUC__ +rt_inline void rt_hw_pmu_enable_cnt(int divide64) +{ + unsigned long pmcr; + unsigned long pmcntenset; + + asm volatile("mrc p15, 0, %0, c9, c12, 0" : "=r"(pmcr)); + pmcr |= ARM_PMU_PMCR_E | ARM_PMU_PMCR_P | ARM_PMU_PMCR_C; + if (divide64) + pmcr |= ARM_PMU_PMCR_D; + else + pmcr &= ~ARM_PMU_PMCR_D; + asm volatile("mcr p15, 0, %0, c9, c12, 0" :: "r"(pmcr)); + + /* enable all the counters */ + pmcntenset = ~0; + asm volatile("mcr p15, 0, %0, c9, c12, 1" :: "r"(pmcntenset)); + /* clear overflows(just in case) */ + asm volatile("mcr p15, 0, %0, c9, c12, 3" :: "r"(pmcntenset)); +} + +rt_inline unsigned long rt_hw_pmu_get_control(void) +{ + unsigned long pmcr; + asm("mrc p15, 0, %0, c9, c12, 0" : "=r"(pmcr)); + return pmcr; +} + +rt_inline unsigned long rt_hw_pmu_get_ceid(void) +{ + unsigned long reg; + /* only PMCEID0 is supported, PMCEID1 is RAZ. */ + asm("mrc p15, 0, %0, c9, c12, 6" : "=r"(reg)); + return reg; +} + +rt_inline unsigned long rt_hw_pmu_get_cnten(void) +{ + unsigned long pmcnt; + asm("mrc p15, 0, %0, c9, c12, 1" : "=r"(pmcnt)); + return pmcnt; +} + +rt_inline void rt_hw_pmu_reset_cycle(void) +{ + unsigned long pmcr; + + asm volatile("mrc p15, 0, %0, c9, c12, 0" : "=r"(pmcr)); + pmcr |= ARM_PMU_PMCR_C; + asm volatile("mcr p15, 0, %0, c9, c12, 0" :: "r"(pmcr)); + asm volatile("isb"); +} + +rt_inline void rt_hw_pmu_reset_event(void) +{ + unsigned long pmcr; + + asm volatile("mrc p15, 0, %0, c9, c12, 0" : "=r"(pmcr)); + pmcr |= ARM_PMU_PMCR_P; + asm volatile("mcr p15, 0, %0, c9, c12, 0" :: "r"(pmcr)); + asm volatile("isb"); +} + +rt_inline unsigned long rt_hw_pmu_get_cycle(void) +{ + unsigned long cyc; + asm volatile("isb"); + asm volatile("mrc p15, 0, %0, c9, c13, 0" : "=r"(cyc)); + return cyc; +} + +rt_inline void rt_hw_pmu_select_counter(int idx) +{ + RT_ASSERT(idx < ARM_PMU_CNTER_NR); + + asm volatile("mcr p15, 0, %0, c9, c12, 5" : : "r"(idx)); + /* Linux add an isb here, don't know why here. */ + asm volatile("isb"); +} + +rt_inline void rt_hw_pmu_select_event(int idx, + enum rt_hw_pmu_event_type eve) +{ + RT_ASSERT(idx < ARM_PMU_CNTER_NR); + + rt_hw_pmu_select_counter(idx); + asm volatile("mcr p15, 0, %0, c9, c13, 1" : : "r"(eve)); +} + +rt_inline unsigned long rt_hw_pmu_read_counter(int idx) +{ + unsigned long reg; + + rt_hw_pmu_select_counter(idx); + asm volatile("isb"); + asm volatile("mrc p15, 0, %0, c9, c13, 2" : "=r"(reg)); + return reg; +} + +rt_inline unsigned long rt_hw_pmu_get_ovsr(void) +{ + unsigned long reg; + asm volatile("isb"); + asm("mrc p15, 0, %0, c9, c12, 3" : "=r"(reg)); + return reg; +} + +rt_inline void rt_hw_pmu_clear_ovsr(unsigned long reg) +{ + asm("mcr p15, 0, %0, c9, c12, 3" : : "r"(reg)); + asm volatile("isb"); +} + +#endif + +void rt_hw_pmu_dump_feature(void); + +#endif /* end of include guard: __PMU_H__ */ + diff --git a/bsp/nuvoton/libraries/ma35/libcpu/arm/cortex-m4/SConscript b/bsp/nuvoton/libraries/ma35/libcpu/arm/cortex-m4/SConscript new file mode 100644 index 0000000000..337a027276 --- /dev/null +++ b/bsp/nuvoton/libraries/ma35/libcpu/arm/cortex-m4/SConscript @@ -0,0 +1,14 @@ +# RT-Thread building script for component + +Import('RTT_ROOT') +from building import * + +cwd = GetCurrentDir() +src = Glob('*.c') + Glob('*.cpp') +CPPPATH = [cwd] +group = [] + +# USB driver constrain +group = DefineGroup('CPU', src, depend = [''], CPPPATH = CPPPATH) + +Return('group') diff --git a/bsp/nuvoton/libraries/ma35/libcpu/arm/cortex-m4/interrupt.c b/bsp/nuvoton/libraries/ma35/libcpu/arm/cortex-m4/interrupt.c new file mode 100644 index 0000000000..38ee902044 --- /dev/null +++ b/bsp/nuvoton/libraries/ma35/libcpu/arm/cortex-m4/interrupt.c @@ -0,0 +1,156 @@ +/**************************************************************************//** +* +* @copyright (C) 2020 Nuvoton Technology Corp. All rights reserved. +* +* SPDX-License-Identifier: Apache-2.0 +* +* Change Logs: +* Date Author Notes +* 2021-07-19 Wayne First version +* +******************************************************************************/ + +#include +#include "interrupt.h" + +#define NVIC_INT_OFFSET (16) +#define SYS_MAX_INT_SOURCE (IRQn_Max) + +static struct rt_irq_desc irq_desc[SYS_MAX_INT_SOURCE] = {0}; + +void rt_hw_interrupt_dummy_handler(int vector, void *param) +{ + rt_kprintf("Unhandled interrupt %d occurred!!!\n", vector); + + RT_ASSERT(0); +} + +static uint32_t rt_hw_interrupt_current_irq(void) +{ + return ((SCB->ICSR & SCB_ICSR_VECTACTIVE_Msk) >> SCB_ICSR_VECTACTIVE_Pos); +} + +void ISR_Trapper(void) +{ + int irq; + + /* Enter interrupt */ + rt_interrupt_enter(); + + /* Get irq number */ + irq = rt_hw_interrupt_current_irq(); + if (irq >= SYS_MAX_INT_SOURCE) + { + rt_kprintf("Over interrupt range - %d!!!\n", irq); + goto exit_rt_interrupt_trap; + } + else if (irq_desc[irq].handler == RT_NULL) + { + rt_kprintf("Unhandled interrupt %d occurred!!!\n", irq); + goto exit_rt_interrupt_trap; + } + else + { + void *param; + rt_isr_handler_t isr_func; + + /* get interrupt service routine */ + isr_func = irq_desc[irq].handler; + param = irq_desc[irq].param; + + /* turn to interrupt service routine */ + isr_func(irq, param); + } + +#ifdef RT_USING_INTERRUPT_INFO + irq_desc[irq].counter ++; +#endif + +exit_rt_interrupt_trap: + + /* Enter interrupt */ + rt_interrupt_leave(); +} + +void rt_hw_interrupt_init(void) +{ + int i; + vu32 *vpu32Vector; + + /* Enter interrupt */ + rt_interrupt_enter(); + + /* Replace user-handler in RAM to ISR_Trapper */ + vpu32Vector = (vu32 *)SCB->VTOR; + for (i = NVIC_INT_OFFSET; i < IRQn_Max; i++) + { + vpu32Vector[i] = (uint32_t)ISR_Trapper; + } + + /* Initial all interrupt handler */ + for (i = 0; i < SYS_MAX_INT_SOURCE; i++) + { + rt_hw_interrupt_install(i, RT_NULL, RT_NULL, (char *)"dummy"); + rt_hw_interrupt_mask(i); + } + + NVIC_SetPriorityGrouping(7); + + /* Enter interrupt */ + rt_interrupt_leave(); +} + +rt_isr_handler_t rt_hw_interrupt_install(int vector, rt_isr_handler_t handler, void *param, const char *name) +{ + rt_isr_handler_t old_handler = RT_NULL; + + if (vector > SYS_MAX_INT_SOURCE) + return RT_NULL; + + /* Set default priority IRQ_LEVEL_7 */ + //rt_hw_interrupt_set_priority(vector, IRQ_LEVEL_7); + + old_handler = irq_desc[vector + NVIC_INT_OFFSET].handler; + if (handler != RT_NULL) + { + irq_desc[vector + NVIC_INT_OFFSET].handler = (rt_isr_handler_t)handler; + irq_desc[vector + NVIC_INT_OFFSET].param = param; +#ifdef RT_USING_INTERRUPT_INFO + rt_snprintf(irq_desc[vector + NVIC_INT_OFFSET].name, RT_NAME_MAX - 1, "%s", name); + irq_desc[vector + NVIC_INT_OFFSET].counter = 0; +#endif + } + + return old_handler; +} + +/* Disable interrupt */ +void rt_hw_interrupt_mask(int vector) +{ + NVIC_DisableIRQ((IRQn_Type)vector); + NVIC_ClearPendingIRQ((IRQn_Type)vector); +} + +/* Enable interrupt */ +void rt_hw_interrupt_umask(int vector) +{ + NVIC_EnableIRQ((IRQn_Type)vector); +} + +#ifdef RT_USING_INTERRUPT_INFO +int list_interrupt(int argc, char **argv) +{ + int i; + + for (i = 0; i <= SYS_MAX_INT_SOURCE; i++) + { + if (irq_desc[i].handler != rt_hw_interrupt_dummy_handler) + { + rt_kprintf("[%d] %s: %d\n", i, irq_desc[i].name, irq_desc[i].counter); + } + } + + return 0; +} +MSH_CMD_EXPORT(list_interrupt, list registered interrupts); +#endif diff --git a/bsp/nuvoton/libraries/ma35/libcpu/arm/cortex-m4/interrupt.h b/bsp/nuvoton/libraries/ma35/libcpu/arm/cortex-m4/interrupt.h new file mode 100644 index 0000000000..ff8ca32cba --- /dev/null +++ b/bsp/nuvoton/libraries/ma35/libcpu/arm/cortex-m4/interrupt.h @@ -0,0 +1,27 @@ +/* + * Copyright (c) 2006-2022, RT-Thread Development Team + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + * 2021-07-16 Wayne First version + */ + +#ifndef __INTERRUPT_H__ +#define __INTERRUPT_H__ + +#include +#include + +#define INT_IRQ 0x00 +#define INT_FIQ 0x01 + +void rt_hw_interrupt_init(void); +void rt_hw_interrupt_mask(int vector); +void rt_hw_interrupt_umask(int vector); +rt_isr_handler_t rt_hw_interrupt_install(int vector, rt_isr_handler_t handler, + void *param, const char *name); + +#endif + diff --git a/bsp/nuvoton/libraries/ma35/rtt_port/Kconfig b/bsp/nuvoton/libraries/ma35/rtt_port/Kconfig new file mode 100644 index 0000000000..035e80155e --- /dev/null +++ b/bsp/nuvoton/libraries/ma35/rtt_port/Kconfig @@ -0,0 +1,1119 @@ + config SOC_SERIES_MA35D1 + bool + select SOC_FAMILY_NUMICRO + select RT_USING_COMPONENTS_INIT + select RT_USING_USER_MAIN + default y + + config USE_MA35D1_AARCH32 + bool + select ARCH_ARM_CORTEX_A + select RT_USING_GIC_V2 + select RT_USING_FPU + select ARCH_ARMV8 + select RT_SMP_AUTO_BOOT + + config USE_MA35D1_AARCH64 + bool + select ARCH_ARMV8 + + config USE_MA35D1_SUBM + bool + select ARCH_ARM_CORTEX_M4 + + config RT_USING_FPU + bool + + config BSP_USE_STDDRIVER_SOURCE + bool "Build StdDriver source" + default n + + menuconfig BSP_USING_PDMA + bool "Enable Peripheral Direct Memory Access Controller(PDMA)" + default y + + if BSP_USING_PDMA + config BSP_USING_PDMA0 + bool "Enable PDMA0" + depends on !USE_MA35D1_SUBM + + config BSP_USING_PDMA1 + bool "Enable PDMA1" + depends on !USE_MA35D1_SUBM + + config BSP_USING_PDMA2 + bool "Enable PDMA2" + + config BSP_USING_PDMA3 + bool "Enable PDMA3" + + config NU_PDMA_MEMFUN_ACTOR_MAX + int "Specify maximum mem actor for memfun" + range 1 4 + default 2 + endif + + config BSP_USING_GPIO + bool "Enable General Purpose I/O(GPIO)" + select RT_USING_PIN + default y + + menuconfig BSP_USING_GMAC + bool "Enable Ethernet Gigabit MAC Controller(GMAC)" + select RT_USING_LWIP + select RT_USING_NETDEV + depends on !USE_MA35D1_SUBM + + if BSP_USING_GMAC + config BSP_USING_GMAC0 + bool "Enable GMAC0" + + config BSP_USING_GMAC1 + bool "Enable GMAC1" + endif + + menuconfig BSP_USING_RTC + bool "Enable Real Time Clock(RTC)" + select RT_USING_RTC + + config NU_RTC_SUPPORT_IO_RW + bool "Support device RW entry" + depends on BSP_USING_RTC && RT_USING_RTC + + config NU_RTC_SUPPORT_MSH_CMD + bool "Support module shell command" + depends on BSP_USING_RTC && RT_USING_RTC + + menuconfig BSP_USING_ADC + bool "Enable Analog-to-Digital Converter(ADC)" + select RT_USING_ADC + depends on !USE_MA35D1_SUBM + + if BSP_USING_ADC + config BSP_USING_ADC_TOUCH + bool "Enable ADC Touching function" + select RT_USING_TOUCH + default y + endif + + menuconfig BSP_USING_CCAP + bool "Enable Camera Capture Interface Controller(CCAP)" + select RT_USING_PIN + depends on !USE_MA35D1_SUBM + + if BSP_USING_CCAP + config BSP_USING_CCAP0 + bool "Enable CCAP0" + config BSP_USING_CCAP1 + bool "Enable CCAP1" + endif + menuconfig BSP_USING_EADC + bool "Enable Enhanced Analog-to-Digital Converter(EADC)" + select RT_USING_ADC + + if BSP_USING_EADC + config BSP_USING_EADC0 + bool "Enable EADC0" + endif + + menuconfig BSP_USING_TMR + bool "Enable Timer Controller(TIMER)" + + if BSP_USING_TMR + + config BSP_USING_TIMER + bool + + config BSP_USING_TPWM + bool + + config BSP_USING_TMR0 + bool "Enable TIMER0" + depends on BSP_USING_TMR && !USE_MA35D1_SUBM + + if BSP_USING_TMR0 + choice + prompt "Select TIMER0 function mode" + + config BSP_USING_TIMER0 + select BSP_USING_TIMER + select RT_USING_HWTIMER + bool "Timer" + help + Choose this option if you need TIMER function mode. + + config BSP_USING_TPWM0 + select BSP_USING_TPWM + select RT_USING_PWM + bool "Timer PWM" + help + Choose this option if you need Timer PWM function mode. + + endchoice + endif + + config BSP_USING_TMR1 + bool "Enable TIMER1" + depends on BSP_USING_TMR && !USE_MA35D1_SUBM + + if BSP_USING_TMR1 + choice + prompt "Select TIMER1 function mode" + + config BSP_USING_TIMER1 + select BSP_USING_TIMER + select RT_USING_HWTIMER + bool "Timer" + help + Choose this option if you need TIMER function mode. + + config BSP_USING_TPWM1 + select BSP_USING_TPWM + select RT_USING_PWM + bool "Timer PWM" + help + Choose this option if you need Timer PWM function mode. + endchoice + endif + + config BSP_USING_TMR2 + bool "Enable TIMER2" + depends on BSP_USING_TMR + + if BSP_USING_TMR2 + choice + prompt "Select TIMER2 function mode" + + config BSP_USING_TIMER2 + select BSP_USING_TIMER + select RT_USING_HWTIMER + bool "Timer" + help + Choose this option if you need TIMER function mode. + + config BSP_USING_TPWM2 + select BSP_USING_TPWM + select RT_USING_PWM + bool "Timer PWM" + help + Choose this option if you need Timer PWM function mode. + endchoice + endif + + config BSP_USING_TMR3 + bool "Enable TIMER3" + depends on BSP_USING_TMR + + if BSP_USING_TMR3 + choice + prompt "Select TIMER3 function mode" + + config BSP_USING_TIMER3 + select BSP_USING_TIMER + select RT_USING_HWTIMER + bool "Timer" + help + Choose this option if you need TIMER function mode. + + config BSP_USING_TPWM3 + select BSP_USING_TPWM + select RT_USING_PWM + bool "Timer PWM" + help + Choose this option if you need Timer PWM function mode. + endchoice + endif + + config BSP_USING_TMR4 + bool "Enable TIMER4" + depends on BSP_USING_TMR + + if BSP_USING_TMR4 + choice + prompt "Select TIMER4 function mode" + + config BSP_USING_TIMER4 + select BSP_USING_TIMER + select RT_USING_HWTIMER + bool "Timer" + help + Choose this option if you need TIMER function mode. + + config BSP_USING_TPWM4 + select BSP_USING_TPWM + select RT_USING_PWM + bool "Timer PWM" + help + Choose this option if you need Timer PWM function mode. + + endchoice + endif + + config BSP_USING_TMR5 + bool "Enable TIMER5" + depends on BSP_USING_TMR + + if BSP_USING_TMR5 + choice + prompt "Select TIMER5 function mode" + + config BSP_USING_TIMER5 + select BSP_USING_TIMER + select RT_USING_HWTIMER + bool "Timer" + help + Choose this option if you need TIMER function mode. + + config BSP_USING_TPWM5 + select BSP_USING_TPWM + select RT_USING_PWM + bool "Timer PWM" + help + Choose this option if you need Timer PWM function mode. + + endchoice + endif + + config BSP_USING_TMR6 + bool "Enable TIMER6" + depends on BSP_USING_TMR + + if BSP_USING_TMR6 + choice + prompt "Select TIMER6 function mode" + + config BSP_USING_TIMER6 + select BSP_USING_TIMER + select RT_USING_HWTIMER + bool "Timer" + help + Choose this option if you need TIMER function mode. + + config BSP_USING_TPWM6 + select BSP_USING_TPWM + select RT_USING_PWM + bool "Timer PWM" + help + Choose this option if you need Timer PWM function mode. + + endchoice + endif + + + config BSP_USING_TMR7 + bool "Enable TIMER7" + depends on BSP_USING_TMR + + if BSP_USING_TMR7 + choice + prompt "Select TIMER7 function mode" + + config BSP_USING_TIMER7 + select BSP_USING_TIMER + select RT_USING_HWTIMER + bool "Timer" + help + Choose this option if you need TIMER function mode. + + config BSP_USING_TPWM7 + select BSP_USING_TPWM + select RT_USING_PWM + bool "Timer PWM" + help + Choose this option if you need Timer PWM function mode. + + endchoice + endif + + config BSP_USING_TMR8 + bool "Enable TIMER8" + depends on BSP_USING_TMR + + if BSP_USING_TMR8 + choice + prompt "Select TIMER8 function mode" + + config BSP_USING_TIMER8 + select BSP_USING_TIMER + select RT_USING_HWTIMER + bool "Timer" + help + Choose this option if you need TIMER function mode. + + config BSP_USING_TPWM8 + select BSP_USING_TPWM + select RT_USING_PWM + bool "Timer PWM" + help + Choose this option if you need Timer PWM function mode. + + endchoice + endif + + config BSP_USING_TMR9 + bool "Enable TIMER9" + depends on BSP_USING_TMR + + if BSP_USING_TMR9 + choice + prompt "Select TIMER9 function mode" + + config BSP_USING_TIMER9 + select BSP_USING_TIMER + select RT_USING_HWTIMER + bool "Timer" + help + Choose this option if you need TIMER function mode. + + config BSP_USING_TPWM9 + select BSP_USING_TPWM + select RT_USING_PWM + bool "Timer PWM" + help + Choose this option if you need Timer PWM function mode. + + endchoice + endif + + config BSP_USING_TMR10 + bool "Enable TIMER10" + depends on BSP_USING_TMR + + if BSP_USING_TMR10 + choice + prompt "Select TIMER10 function mode" + + config BSP_USING_TIMER10 + select BSP_USING_TIMER + select RT_USING_HWTIMER + bool "Timer" + help + Choose this option if you need TIMER function mode. + + config BSP_USING_TPWM10 + select BSP_USING_TPWM + select RT_USING_PWM + bool "Timer PWM" + help + Choose this option if you need Timer PWM function mode. + + endchoice + endif + + config BSP_USING_TMR11 + bool "Enable TIMER11" + depends on BSP_USING_TMR + + if BSP_USING_TMR11 + choice + prompt "Select TIMER11 function mode" + + config BSP_USING_TIMER11 + select BSP_USING_TIMER + select RT_USING_HWTIMER + bool "Timer" + help + Choose this option if you need TIMER function mode. + + config BSP_USING_TPWM11 + select BSP_USING_TPWM + select RT_USING_PWM + bool "Timer PWM" + help + Choose this option if you need Timer PWM function mode. + + endchoice + endif + + endif + + menuconfig BSP_USING_UART + bool "Enable Universal Asynchronous Receiver/Transmitters(UART)" + select RT_USING_SERIAL + + if BSP_USING_UART + config BSP_USING_UART0 + bool "Enable UART0" + depends on !USE_MA35D1_SUBM + + config BSP_USING_UART0_TX_DMA + bool "Enable UART0 TX DMA" + depends on BSP_USING_UART0 && RT_SERIAL_USING_DMA + + config BSP_USING_UART0_RX_DMA + bool "Enable UART0 RX DMA" + depends on BSP_USING_UART0 && RT_SERIAL_USING_DMA + + config BSP_USING_UART1 + bool "Enable UART1" + + config BSP_USING_UART1_TX_DMA + bool "Enable UART1 TX DMA" + depends on BSP_USING_UART1 && RT_SERIAL_USING_DMA + + config BSP_USING_UART1_RX_DMA + bool "Enable UART1 RX DMA" + depends on BSP_USING_UART1 && RT_SERIAL_USING_DMA + + config BSP_USING_UART2 + bool "Enable UART2" + + config BSP_USING_UART2_TX_DMA + bool "Enable UART2 TX DMA" + depends on BSP_USING_UART2 && RT_SERIAL_USING_DMA + + config BSP_USING_UART2_RX_DMA + bool "Enable UART2 RX DMA" + depends on BSP_USING_UART2 && RT_SERIAL_USING_DMA + + config BSP_USING_UART3 + bool "Enable UART3" + + config BSP_USING_UART3_TX_DMA + bool "Enable UART3 TX DMA" + depends on BSP_USING_UART3 && RT_SERIAL_USING_DMA + + config BSP_USING_UART3_RX_DMA + bool "Enable UART3 RX DMA" + depends on BSP_USING_UART3 && RT_SERIAL_USING_DMA + + config BSP_USING_UART4 + bool "Enable UART4" + + config BSP_USING_UART4_TX_DMA + bool "Enable UART4 TX DMA" + depends on BSP_USING_UART4 && RT_SERIAL_USING_DMA + + config BSP_USING_UART4_RX_DMA + bool "Enable UART4 RX DMA" + depends on BSP_USING_UART4 && RT_SERIAL_USING_DMA + + config BSP_USING_UART5 + bool "Enable UART5" + + config BSP_USING_UART5_TX_DMA + bool "Enable UART5 TX DMA" + depends on BSP_USING_UART5 && RT_SERIAL_USING_DMA + + config BSP_USING_UART5_RX_DMA + bool "Enable UART5 RX DMA" + depends on BSP_USING_UART5 && RT_SERIAL_USING_DMA + + config BSP_USING_UART6 + bool "Enable UART6" + + config BSP_USING_UART6_TX_DMA + bool "Enable UART6 TX DMA" + depends on BSP_USING_UART6 && RT_SERIAL_USING_DMA + + config BSP_USING_UART6_RX_DMA + bool "Enable UART6 RX DMA" + depends on BSP_USING_UART6 && RT_SERIAL_USING_DMA + + config BSP_USING_UART7 + bool "Enable UART7" + + config BSP_USING_UART7_TX_DMA + bool "Enable UART7 TX DMA" + depends on BSP_USING_UART7 && RT_SERIAL_USING_DMA + + config BSP_USING_UART7_RX_DMA + bool "Enable UART7 RX DMA" + depends on BSP_USING_UART7 && RT_SERIAL_USING_DMA + + config BSP_USING_UART8 + bool "Enable UART8" + + config BSP_USING_UART8_TX_DMA + bool "Enable UART8 TX DMA" + depends on BSP_USING_UART8 && RT_SERIAL_USING_DMA + + config BSP_USING_UART8_RX_DMA + bool "Enable UART8 RX DMA" + depends on BSP_USING_UART8 && RT_SERIAL_USING_DMA + + config BSP_USING_UART9 + bool "Enable UART9" + + config BSP_USING_UART9_TX_DMA + bool "Enable UART9 TX DMA" + depends on BSP_USING_UART9 && RT_SERIAL_USING_DMA + + config BSP_USING_UART9_RX_DMA + bool "Enable UART9 RX DMA" + depends on BSP_USING_UART9 && RT_SERIAL_USING_DMA + + config BSP_USING_UART10 + bool "Enable UART10" + + config BSP_USING_UART10_TX_DMA + bool "Enable UART10 TX DMA" + depends on BSP_USING_UART10 && RT_SERIAL_USING_DMA + + config BSP_USING_UART10_RX_DMA + bool "Enable UART10 RX DMA" + depends on BSP_USING_UART10 && RT_SERIAL_USING_DMA + + config BSP_USING_UART11 + bool "Enable UART11" + + config BSP_USING_UART11_TX_DMA + bool "Enable UART11 TX DMA" + depends on BSP_USING_UART11 && RT_SERIAL_USING_DMA + + config BSP_USING_UART11_RX_DMA + bool "Enable UART11 RX DMA" + depends on BSP_USING_UART11 && RT_SERIAL_USING_DMA + + config BSP_USING_UART12 + bool "Enable UART12" + + config BSP_USING_UART12_TX_DMA + bool "Enable UART12 TX DMA" + depends on BSP_USING_UART12 && RT_SERIAL_USING_DMA + + config BSP_USING_UART12_RX_DMA + bool "Enable UART12 RX DMA" + depends on BSP_USING_UART12 && RT_SERIAL_USING_DMA + + config BSP_USING_UART13 + bool "Enable UART13" + + config BSP_USING_UART13_TX_DMA + bool "Enable UART13 TX DMA" + depends on BSP_USING_UART13 && RT_SERIAL_USING_DMA + + config BSP_USING_UART13_RX_DMA + bool "Enable UART13 RX DMA" + depends on BSP_USING_UART13 && RT_SERIAL_USING_DMA + + config BSP_USING_UART14 + bool "Enable UART14" + + config BSP_USING_UART14_TX_DMA + bool "Enable UART14 TX DMA" + depends on BSP_USING_UART14 && RT_SERIAL_USING_DMA + + config BSP_USING_UART14_RX_DMA + bool "Enable UART14 RX DMA" + depends on BSP_USING_UART14 && RT_SERIAL_USING_DMA + + config BSP_USING_UART15 + bool "Enable UART15" + + config BSP_USING_UART15_TX_DMA + bool "Enable UART15 TX DMA" + depends on BSP_USING_UART15 && RT_SERIAL_USING_DMA + + config BSP_USING_UART15_RX_DMA + bool "Enable UART15 RX DMA" + depends on BSP_USING_UART15 && RT_SERIAL_USING_DMA + + config BSP_USING_UART16 + bool "Enable UART16" + + config BSP_USING_UART16_TX_DMA + bool "Enable UART16 TX DMA" + depends on BSP_USING_UART16 && RT_SERIAL_USING_DMA + + config BSP_USING_UART16_RX_DMA + bool "Enable UART16 RX DMA" + depends on BSP_USING_UART16 && RT_SERIAL_USING_DMA + + endif + + menuconfig BSP_USING_I2C + bool "Enable I2C Serial Interface Controller(I2C)" + select RT_USING_I2C + + if BSP_USING_I2C + config BSP_USING_I2C0 + bool "Enable I2C0" + + config BSP_USING_I2C1 + bool "Enable I2C1" + + config BSP_USING_I2C2 + bool "Enable I2C2" + + config BSP_USING_I2C3 + bool "Enable I2C3" + + config BSP_USING_I2C4 + bool "Enable I2C4" + + config BSP_USING_I2C5 + bool "Enable I2C5" + + endif + + menuconfig BSP_USING_SDH + bool "Enable Secure Digital Host Controller(SDH)" + select RT_USING_DFS + select RT_USING_SDIO + depends on !USE_MA35D1_SUBM + + if BSP_USING_SDH + config BSP_USING_SDH0 + bool "Enable SDH0" + + config BSP_USING_SDH1 + bool "Enable SDH1" + endif + + menuconfig BSP_USING_CANFD + bool "Enable CAN with Flexible Data-rate(CAN FD)" + select RT_USING_CAN + + if BSP_USING_CANFD + config BSP_USING_CANFD0 + bool "Enable CANFD0" + + config BSP_USING_CANFD1 + bool "Enable CANFD1" + + config BSP_USING_CANFD2 + bool "Enable CANFD2" + + config BSP_USING_CANFD3 + bool "Enable CANFD3" + endif + + menuconfig BSP_USING_EPWM + bool "Enable EPWM Generator and Capture Timer(EPWM)" + + if BSP_USING_EPWM + + config BSP_USING_EPWM0 + bool "Enable EPWM0" + depends on BSP_USING_EPWM && !USE_MA35D1_SUBM + + config BSP_USING_EPWM_CAPTURE + bool + + if BSP_USING_EPWM0 + choice + prompt "Select EPWM0 function mode" + config BSP_USING_EPWM0_PWM + select RT_USING_PWM + bool "EPWM0 PWM" + help + Choose this option if you need PWM function mode. + + config BSP_USING_EPWM0_CAPTURE + select RT_USING_INPUT_CAPTURE + select BSP_USING_EPWM_CAPTURE + bool "EPWM0 CAPTURE" + help + Choose this option if you need PWM capture function mode. + endchoice + endif + + config BSP_USING_EPWM1 + bool "Enable EPWM1" + depends on BSP_USING_EPWM && !USE_MA35D1_SUBM + + if BSP_USING_EPWM1 + choice + prompt "Select EPWM1 function mode" + config BSP_USING_EPWM1_PWM + select RT_USING_PWM + bool "EPWM1 PWM" + help + Choose this option if you need PWM function mode. + + config BSP_USING_EPWM1_CAPTURE + select RT_USING_INPUT_CAPTURE + select BSP_USING_EPWM_CAPTURE + bool "EPWM1 CAPTURE" + help + Choose this option if you need PWM capture function mode. + endchoice + endif + + config BSP_USING_EPWM2 + bool "Enable EPWM2" + depends on BSP_USING_EPWM && !USE_MA35D1_SUBM + + if BSP_USING_EPWM2 + choice + prompt "Select EPWM2 function mode" + config BSP_USING_EPWM2_PWM + select RT_USING_PWM + bool "EPWM2 PWM" + help + Choose this option if you need PWM function mode. + + config BSP_USING_EPWM2_CAPTURE + select RT_USING_INPUT_CAPTURE + select BSP_USING_EPWM_CAPTURE + bool "EPWM2 CAPTURE" + help + Choose this option if you need PWM capture function mode. + endchoice + endif + + endif + + menuconfig BSP_USING_SPI + bool "Enable Serial Peripheral Interface(SPI)" + select RT_USING_SPI + + if BSP_USING_SPI + config BSP_USING_SPI_PDMA + bool + default n + + config BSP_USING_SPII2S + bool + + choice + prompt "Select SPI0 function mode" + config BSP_USING_SPI0_NONE + bool "NONE" + help + Choose this option if you need not SPI0. + + config BSP_USING_SPI0 + bool "Enable SPI0" + help + Choose this option if you need SPI function mode. + + config BSP_USING_SPII2S0 + select RT_USING_AUDIO + select BSP_USING_SPII2S + bool "Enable SPII2S0" + help + Choose this option if you need SPII2S function mode. + + endchoice + + if BSP_USING_SPI0 + config BSP_USING_SPI0_PDMA + bool "Enable PDMA for SPI0" + select BSP_USING_SPI_PDMA + depends on BSP_USING_SPI0 + endif + + choice + prompt "Select SPI1 function mode" + config BSP_USING_SPI1_NONE + bool "NONE" + help + Choose this option if you need not SPI1. + + config BSP_USING_SPI1 + bool "Enable SPI1" + help + Choose this option if you need SPI function mode. + + config BSP_USING_SPII2S1 + select RT_USING_AUDIO + select BSP_USING_SPII2S + bool "Enable SPII2S1" + help + Choose this option if you need SPII2S function mode. + + endchoice + + if BSP_USING_SPI1 + config BSP_USING_SPI1_PDMA + bool "Enable PDMA for SPI1" + select BSP_USING_SPI_PDMA + depends on BSP_USING_SPI1 + endif + + choice + prompt "Select SPI2 function mode" + config BSP_USING_SPI2_NONE + bool "NONE" + help + Choose this option if you need not SPI2. + + config BSP_USING_SPI2 + bool "Enable SPI2" + help + Choose this option if you need SPI function mode. + + config BSP_USING_SPII2S2 + select RT_USING_AUDIO + select BSP_USING_SPII2S + bool "Enable SPII2S2" + help + Choose this option if you need SPII2S function mode. + + endchoice + + if BSP_USING_SPI2 + config BSP_USING_SPI1_PDMA + bool "Enable PDMA for SPI2" + select BSP_USING_SPI_PDMA + depends on BSP_USING_SPI2 + endif + + choice + prompt "Select SPI3 function mode" + config BSP_USING_SPI3_NONE + bool "NONE" + help + Choose this option if you need not SPI3. + + config BSP_USING_SPI3 + bool "Enable SPI3" + help + Choose this option if you need SPI function mode. + + config BSP_USING_SPII2S3 + select RT_USING_AUDIO + select BSP_USING_SPII2S + bool "Enable SPII2S3" + help + Choose this option if you need SPII2S function mode. + + endchoice + + if BSP_USING_SPI3 + config BSP_USING_SPI3_PDMA + bool "Enable PDMA for SPI3" + select BSP_USING_SPI_PDMA + depends on BSP_USING_SPI3 + endif + + endif + + menuconfig BSP_USING_I2S + bool "Enable I2S Controller(I2S)" + select RT_USING_AUDIO + + if BSP_USING_I2S + config BSP_USING_I2S0 + bool "Enable I2S0" + + config BSP_USING_I2S1 + bool "Enable I2S1" + + config NU_I2S_DMA_FIFO_SIZE + int "DMA Buffer size of capture and playback" + range 2048 4096 + default 2048 + endif + + menuconfig BSP_USING_QSPI + bool "Enable Quad Serial Peripheral Interface(QSPI)" + select RT_USING_SPI + select RT_USING_QSPI + select BSP_USING_SPI + + if BSP_USING_QSPI + + config BSP_USING_QSPI_PDMA + bool + select BSP_USING_SPI_PDMA + default n + + config BSP_USING_QSPI0 + bool "Enable QSPI0" + + config BSP_USING_QSPI0_PDMA + bool "Enable PDMA for QSPI0" + select BSP_USING_QSPI_PDMA + depends on BSP_USING_QSPI0 + + config BSP_USING_QSPI1 + bool "Enable QSPI1" + + config BSP_USING_QSPI1_PDMA + bool "Enable PDMA for QSPI1" + select BSP_USING_QSPI_PDMA + depends on BSP_USING_QSPI1 + + endif + + menuconfig BSP_USING_SCUART + bool "Enable Smart Card Host Interface - UART(SCUART)" + + if BSP_USING_SCUART + config BSP_USING_SCUART0 + bool "Enable SCUART0" + + config BSP_USING_SCUART1 + bool "Enable SCUART1" + + endif + + menuconfig BSP_USING_ECAP + bool "Enable Enhanced Input Capture Timer(ECAP)" + select RT_USING_INPUT_CAPTURE + + if BSP_USING_ECAP + + config BSP_USING_ECAP0 + select RT_USING_INPUT_CAPTURE + bool "Enable ECAP0" + help + Choose this option if you need ECAP0. + + config BSP_USING_ECAP1 + select RT_USING_INPUT_CAPTURE + bool "Enable ECAP1" + help + Choose this option if you need ECAP1. + + config BSP_USING_ECAP2 + select RT_USING_INPUT_CAPTURE + bool "Enable ECAP2" + help + Choose this option if you need ECAP2. + + endif + + menuconfig BSP_USING_QEI + bool "Enable Quadrature Encoder Interface(QEI)" + + if BSP_USING_QEI + config BSP_USING_QEI0 + bool "Enable QEI0" + select RT_USING_PULSE_ENCODER + + config BSP_USING_QEI1 + bool "Enable QEI1" + select RT_USING_PULSE_ENCODER + + config BSP_USING_QEI2 + bool "Enable QEI2" + select RT_USING_PULSE_ENCODER + + endif + + menuconfig BSP_USING_SOFT_I2C + bool "Enable SOFT I2C" + + if BSP_USING_SOFT_I2C + config BSP_USING_SOFT_I2C0 + bool "Enable SOFT I2C0" + select RT_USING_I2C + select RT_USING_I2C_BITOPS + default n + + if BSP_USING_SOFT_I2C0 + config BSP_SOFT_I2C0_SCL_PIN + hex "Specify the pin index of SCL of SOFT I2C0" + range 0 0xDF + default 0x19 + + config BSP_SOFT_I2C0_SDA_PIN + hex "Specify the pin index of SDA of SOFT I2C0" + range 0 0xDF + default 0x18 + endif + + config BSP_USING_SOFT_I2C1 + bool "Enable SOFT I2C1" + select RT_USING_I2C + select RT_USING_I2C_BITOPS + default n + + if BSP_USING_SOFT_I2C1 + config BSP_SOFT_I2C1_SCL_PIN + hex "Specify the pin index of SCL of SOFT I2C1" + range 0 0xDF + default 0x0B + + config BSP_SOFT_I2C1_SDA_PIN + hex "Specify the pin index of SDA of SOFT I2C1" + range 0 0xDF + default 0x0A + endif + endif + + config BSP_USING_DISP + bool "Enable Display" + depends on !USE_MA35D1_SUBM + default y + + if BSP_USING_DISP + choice + prompt "Select Supported LCM panel" + default LCM_USING_FW070TFT_WSVGA + config LCM_USING_FW070TFT_WSVGA + bool "eDispLcd_1024x600(1024x600-RGB888)" + + config LCM_USING_FW070TFT_WVGA + bool "eDispLcd_800x480(800x480-RGB888)" + + config LCM_USING_FHD + bool "eDispLcd_1920x1080(1920x1080-RGB888)" + endchoice + + config DISP_USING_LCD_IDX + int + default 0 if LCM_USING_FW070TFT_WSVGA + default 1 if LCM_USING_FW070TFT_WVGA + default 2 if LCM_USING_FHD + + config BSP_LCD_BPP + int + default 32 if LCM_USING_FW070TFT_WSVGA + default 32 if LCM_USING_FW070TFT_WVGA + default 32 if LCM_USING_FHD + + config BSP_LCD_WIDTH + int + default 1024 if LCM_USING_FW070TFT_WSVGA + default 800 if LCM_USING_FW070TFT_WVGA + default 1920 if LCM_USING_FHD + + config BSP_LCD_HEIGHT + int + default 600 if LCM_USING_FW070TFT_WSVGA + default 480 if LCM_USING_FW070TFT_WVGA + default 1080 if LCM_USING_FHD + + config DISP_USING_OVERLAY + bool "Enable Overlay layer" + default n + endif + + config BSP_USING_WDT + bool "Enable Watchdog Timer(WDT)" + select RT_USING_WDT + default y + + if BSP_USING_WDT + config BSP_USING_WDT0 + bool "Enable WDT0" + select RT_USING_WATCHDOG + depends on !USE_MA35D1_SUBM + default n + + config BSP_USING_WDT1 + bool "Enable WDT1" + select RT_USING_WATCHDOG + depends on !USE_MA35D1_SUBM + default n + + config BSP_USING_WDT2 + bool "Enable WDT2" + select RT_USING_WATCHDOG + default n + endif + + config BSP_USING_EBI + bool "Enable External Bus Interface(EBI)" + default n + + config BSP_USING_USBH + bool "Enable USB Host Controller(USBH)" + select RT_USING_USB_HOST + select RT_USBH_MSTORAGE + depends on !USE_MA35D1_SUBM + + if BSP_USING_USBH + config BSP_USING_HSUSBH0 + bool "Enable HSUSBH0" + default y + + config BSP_USING_HSUSBH1 + bool "Enable HSUSBH1" + default y + endif diff --git a/bsp/nuvoton/libraries/ma35/rtt_port/SConscript b/bsp/nuvoton/libraries/ma35/rtt_port/SConscript new file mode 100644 index 0000000000..8e375e6708 --- /dev/null +++ b/bsp/nuvoton/libraries/ma35/rtt_port/SConscript @@ -0,0 +1,21 @@ +# RT-Thread building script for component + +import os +Import('RTT_ROOT') +from building import * + +cwd = GetCurrentDir() +objs = [] +list = os.listdir(cwd) +src = Glob('*.c') + Glob('*.cpp') +CPPPATH = [cwd] +group = DefineGroup('Drivers', src, depend = [''], CPPPATH = CPPPATH) + +for d in list: + path = os.path.join(cwd, d) + if os.path.isfile(os.path.join(path, 'SConscript')): + objs = objs + SConscript(os.path.join(d, 'SConscript')) + +objs += group + +Return('objs') diff --git a/bsp/nuvoton/libraries/ma35/rtt_port/drv_adc.c b/bsp/nuvoton/libraries/ma35/rtt_port/drv_adc.c new file mode 100644 index 0000000000..1156803603 --- /dev/null +++ b/bsp/nuvoton/libraries/ma35/rtt_port/drv_adc.c @@ -0,0 +1,615 @@ +/**************************************************************************//** +* @copyright (C) 2020 Nuvoton Technology Corp. All rights reserved. +* +* SPDX-License-Identifier: Apache-2.0 +* +* Change Logs: +* Date Author Notes +* 2020-12-12 Wayne First version +* +******************************************************************************/ + +#include + +#if defined(BSP_USING_ADC) + +#include +#include "NuMicro.h" +#include "drv_sys.h" +#include "nu_bitutil.h" +#include "drv_adc.h" + +/* Private define ---------------------------------------------------------------*/ +#define DEF_ADC_TOUCH_SMPL_TICK 20 +#define TOUCH_MQ_LENGTH 64 + +/* Private Typedef --------------------------------------------------------------*/ +struct nu_adc +{ + struct rt_adc_device dev; + char *name; + ADC_T *base; + uint32_t bReset; + IRQn_Type irqn; + uint32_t rstidx; + uint32_t modid; + uint32_t chn_mask; + rt_sem_t m_psSem; + +#if defined(BSP_USING_ADC_TOUCH) + rt_touch_t psRtTouch; + rt_timer_t psRtTouchMenuTimer; + rt_mq_t m_pmqTouchXYZ; +#endif + + nu_adc_cb m_isr[eAdc_ISR_CNT]; + nu_adc_cb m_wkisr[eAdc_WKISR_CNT]; +}; +typedef struct nu_adc *nu_adc_t; + +#if defined(BSP_USING_ADC_TOUCH) +struct nu_adc_touch_data +{ + uint32_t u32X; + uint32_t u32Y; + uint32_t u32Z0; + uint32_t u32Z1; +}; +typedef struct nu_adc_touch_data *nu_adc_touch_data_t; +#endif + +/* Private functions ------------------------------------------------------------*/ +static rt_err_t nu_adc_enabled(struct rt_adc_device *device, rt_uint32_t channel, rt_bool_t enabled); +static rt_err_t nu_adc_convert(struct rt_adc_device *device, rt_uint32_t channel, rt_uint32_t *value); +static rt_err_t _nu_adc_control(rt_device_t dev, int cmd, void *args); + +/* Public functions ------------------------------------------------------------*/ +int rt_hw_adc_init(void); + +/* Private variables ------------------------------------------------------------*/ + +static struct nu_adc g_sNuADC = +{ + .name = "adc", + .base = ADC0, + .bReset = 1, + .irqn = ADC0_IRQn, + .rstidx = ADC0_RST, + .modid = ADC_MODULE, + .chn_mask = 0 +}; + +static void nu_adc_isr(int vector, void *param) +{ + volatile rt_int32_t isr, wkisr; + nu_adc_t psNuAdc = (nu_adc_t)param; + rt_int32_t irqidx; + ADC_T *adc = psNuAdc->base; + + //rt_kprintf("[%s %d] CTL: %08x CONF:%08x IER:%08x ISR:%08x\n", __func__, __LINE__, adc->CTL, adc->CONF, adc->IER, adc->ISR); + + isr = adc->ISR; + wkisr = adc->WKISR; + + adc->ISR = isr; + + while ((irqidx = nu_ctz(isr)) < eAdc_ISR_CNT) + { + uint32_t u32IsrBitMask = 1 << irqidx ; + + if (psNuAdc->m_isr[irqidx].cbfunc != RT_NULL) + { + // rt_kprintf("[%s] %d %x\n", __func__, irqidx, psNuAdc->m_isr[irqidx].cbfunc); + psNuAdc->m_isr[irqidx].cbfunc(isr, psNuAdc->m_isr[irqidx].private_data); + } + + /* Clear sent bit */ + isr &= ~(u32IsrBitMask); + } //while + + while ((irqidx = nu_ctz(wkisr)) < eAdc_WKISR_CNT) + { + uint32_t u32IsrBitMask = 1 << irqidx ; + + if (psNuAdc->m_wkisr[irqidx].cbfunc != RT_NULL) + { + psNuAdc->m_wkisr[irqidx].cbfunc(wkisr, psNuAdc->m_wkisr[irqidx].private_data); + } + + wkisr &= ~(u32IsrBitMask); + } //while +} + +static rt_err_t _nu_adc_init(rt_device_t dev) +{ + nu_adc_t psNuAdc = (nu_adc_t)dev; + + /* ADC Engine Clock is set to freq Khz */ + CLK_SetModuleClock(psNuAdc->modid, 0, CLK_CLKDIV4_ADC(180)); // Set ADC clock rate to 9MHz + + /* Install interrupt service routine */ + rt_hw_interrupt_install(psNuAdc->irqn, nu_adc_isr, (void *)psNuAdc, psNuAdc->name); + + return RT_EOK; +} + +#define ADC_TOUCH_Z0_ACTIVE 20 +static int32_t AdcMenuStartCallback(uint32_t status, uint32_t userData) +{ + nu_adc_t psNuAdc = (nu_adc_t)userData; + +#if defined(BSP_USING_ADC_TOUCH) + ADC_T *adc = psNuAdc->base; + static struct nu_adc_touch_data point; + static rt_bool_t bDrop = RT_FALSE; + static uint32_t u32LastZ0 = 0xffffu; + + if (psNuAdc->psRtTouch != RT_NULL) + { + point.u32X = ADC_GET_CONVERSION_XDATA(adc); + point.u32Y = ADC_GET_CONVERSION_YDATA(adc); + + point.u32Z0 = ADC_GET_CONVERSION_Z1DATA(adc); + point.u32Z1 = ADC_GET_CONVERSION_Z2DATA(adc); + + //rt_kprintf("x=%d y=%d z0=%d z1=%d\n", point.u32X, point.u32Y, point.u32Z0, point.u32Z1); + /* Trigger next or not. */ + if (point.u32Z0 < ADC_TOUCH_Z0_ACTIVE) + { + /* Stop sampling procedure. */ + rt_timer_stop(g_sNuADC.psRtTouchMenuTimer); + + /* Re-start pendown detection */ + nu_adc_touch_detect(RT_TRUE); + + psNuAdc->bReset = 1; + + point.u32Z0 = point.u32Z1 = 0; + + bDrop = RT_TRUE; + } + else + { + bDrop = RT_FALSE; + } + + /* Notify upper layer. */ + if ((!bDrop || (u32LastZ0 > ADC_TOUCH_Z0_ACTIVE)) && rt_mq_send(psNuAdc->m_pmqTouchXYZ, (const void *)&point, sizeof(struct nu_adc_touch_data)) == RT_EOK) + { + rt_hw_touch_isr(psNuAdc->psRtTouch); + } + + u32LastZ0 = point.u32Z0; + } + else +#endif + { + rt_err_t result = rt_sem_release(psNuAdc->m_psSem); + RT_ASSERT(result == RT_EOK); + } + + return 0; +} + +#if defined(BSP_USING_ADC_TOUCH) + +static void nu_adc_touch_antiglitch(ADC_T *adc) +{ + int count = 10; + do + { + rt_hw_us_delay(1000); // 1ms + ADC_CLR_INT_FLAG(adc, adc->ISR); + if (adc->ISR == 0) + break; + } + while (count-- > 0); +} + +void nu_adc_touch_detect(rt_bool_t bStartDetect) +{ + nu_adc_t psNuAdc = (nu_adc_t)&g_sNuADC; + ADC_T *adc = psNuAdc->base; + + /* Disable interrupt */ + rt_hw_interrupt_mask(psNuAdc->irqn); + + ADC_POWER_DOWN(adc); + + /* Disable interrupt */ + ADC_DISABLE_INT(adc, ADC_IER_PEDEIEN_Msk | ADC_IER_MIEN_Msk); + nu_adc_touch_antiglitch(adc); + + if (bStartDetect == RT_TRUE) + { + /* Switch to PenDown detection mode */ + ADC_DETECT_PD_MODE(adc); + nu_adc_touch_antiglitch(adc); + + /* Enable interrupt */ + ADC_ENABLE_INT(adc, ADC_IER_PEDEIEN_Msk); + } + else + { + /* Switch to XY coordination converting mode */ + ADC_CONVERT_XY_MODE(adc); + nu_adc_touch_antiglitch(adc); + + /* Enable interrupt */ + ADC_ENABLE_INT(adc, ADC_IER_MIEN_Msk); + } + + ADC_POWER_ON(adc); + + /* Enable interrupt */ + rt_hw_interrupt_umask(psNuAdc->irqn); +} + +static int32_t PenDownCallback(uint32_t status, uint32_t userData) +{ + nu_adc_t psNuAdc = (nu_adc_t)userData; + return rt_timer_start(psNuAdc->psRtTouchMenuTimer); +} + +int32_t nu_adc_touch_read_xyz(uint32_t *bufX, uint32_t *bufY, uint32_t *bufZ0, uint32_t *bufZ1, int32_t dataCnt) +{ + int i; + struct nu_adc_touch_data value; + + for (i = 0 ; i < dataCnt; i++) + { + if (rt_mq_recv(g_sNuADC.m_pmqTouchXYZ, (void *)&value, sizeof(struct nu_adc_touch_data), 0) == -RT_ETIMEOUT) + break; + + bufX[i] = value.u32X; + bufY[i] = value.u32Y; + bufZ0[i] = value.u32Z0; + bufZ1[i] = value.u32Z1; + } + return i; +} + +rt_err_t nu_adc_touch_enable(rt_touch_t psRtTouch) +{ + nu_adc_t psNuAdc = (nu_adc_t)&g_sNuADC; + nu_adc_cb sNuAdcCb; + ADC_T *adc = psNuAdc->base; + + adc->CONF = 0x0; + + rt_adc_enable((rt_adc_device_t)psNuAdc, 4); //Channel number 4 + rt_adc_enable((rt_adc_device_t)psNuAdc, 5); //Channel number 5 + rt_adc_enable((rt_adc_device_t)psNuAdc, 6); //Channel number 6 + rt_adc_enable((rt_adc_device_t)psNuAdc, 7); //Channel number 7 + + /* Register touch device. */ + psNuAdc->psRtTouch = psRtTouch; + + /* Register PenDown callback. */ + sNuAdcCb.cbfunc = PenDownCallback; + sNuAdcCb.private_data = (rt_uint32_t)psNuAdc; + rt_memcpy(&psNuAdc->m_isr[eAdc_PEDEF], &sNuAdcCb, sizeof(nu_adc_cb)); + + nu_adc_touch_detect(RT_TRUE); + + return RT_EOK; +} + +rt_err_t nu_adc_touch_disable(void) +{ + nu_adc_t psNuAdc = (nu_adc_t)&g_sNuADC; + + nu_adc_touch_detect(RT_FALSE); + + _nu_adc_control((rt_device_t)psNuAdc, T_OFF, RT_NULL); + _nu_adc_control((rt_device_t)psNuAdc, Z_OFF, RT_NULL); + _nu_adc_control((rt_device_t)psNuAdc, PEDEF_OFF, RT_NULL); + + rt_adc_disable((rt_adc_device_t)psNuAdc, 4); //Channel number 4 + rt_adc_disable((rt_adc_device_t)psNuAdc, 5); //Channel number 5 + rt_adc_disable((rt_adc_device_t)psNuAdc, 6); //Channel number 6 + rt_adc_disable((rt_adc_device_t)psNuAdc, 7); //Channel number 7 + + return RT_EOK; +} + +static void nu_adc_touch_smpl(void *p) +{ + nu_adc_t psNuAdc = (nu_adc_t)p; + if (psNuAdc->bReset) + { + psNuAdc->bReset = 0; + nu_adc_touch_detect(RT_FALSE); + } + + /* Start conversion */ + ADC_START_CONV(psNuAdc->base); +} +#endif + +static rt_err_t _nu_adc_control(rt_device_t dev, int cmd, void *args) +{ + rt_err_t ret = RT_EINVAL ; + nu_adc_t psNuAdc = (nu_adc_t)dev; + ADC_T *adc = psNuAdc->base; + + nu_adc_cb_t psAdcCb = (nu_adc_cb_t)args; + + switch (cmd) + { + case START_MST: /* Menu Start Conversion */ + { + /* Enable interrupt */ + ADC_ENABLE_INT(adc, ADC_IER_MIEN_Msk); + + /* Start conversion */ + ADC_START_CONV(adc); + + /* Wait it done */ + ret = rt_sem_take(psNuAdc->m_psSem, RT_WAITING_FOREVER); + RT_ASSERT(ret == RT_EOK); + + /* Get data: valid data is 12-bit */ + if (args != RT_NULL) + *((uint32_t *)args) = ADC_GET_CONVERSION_DATA(adc, 0); + } + break; + + case WKT_ON: /* Enable Touch Wake Up */ + { + if (psAdcCb) + { + rt_memcpy(&psNuAdc->m_wkisr[eAdc_WPEDEF], psAdcCb, sizeof(nu_adc_cb)); + } + adc->CTL |= ADC_CTL_WKTEN_Msk; + adc->IER |= ADC_IER_WKTIEN_Msk; + + //TODO outpw(REG_SYS_WKUPSER, inpw(REG_SYS_WKUPSER) | (1 << 26)); + } + break; + + case WKT_OFF: /* Disable Touch Wake Up */ + { + adc->CTL &= ~ADC_CTL_WKTEN_Msk; + adc->IER &= ~ADC_IER_WKTIEN_Msk; + + //TODO outpw(REG_SYS_WKUPSER, inpw(REG_SYS_WKUPSER) & ~(1 << 26)); + } + break; + + case SWITCH_5WIRE_ON: /* Wire Mode Switch to 5-Wire */ + { + adc->CTL |= ADC_CTL_WMSWCH_Msk; + } + break; + + case SWITCH_5WIRE_OFF: /* Wire Mode Switch to 4-Wire */ + { + adc->CTL &= ~ADC_CTL_WMSWCH_Msk; + } + break; + + case T_ON: /* Enable Touch detection function */ + { + adc->CONF |= ADC_CONF_TEN_Msk; + } + break; + + case T_OFF: /* Disable Touch detection function */ + { + adc->CONF &= ~ADC_CONF_TEN_Msk; + } + break; + + case TAVG_ON: /* Enable Touch Mean average for X and Y function */ + { + adc->CONF |= ADC_CONF_TMAVDIS_Msk; + } + break; + + case TAVG_OFF: /* Disable Touch Mean average for X and Y function */ + { + adc->CONF &= ~ADC_CONF_TMAVDIS_Msk; + } + break; + + case Z_ON: /* Enable Press measure function */ + { + adc->CONF |= ADC_CONF_ZEN_Msk; + } + break; + + case Z_OFF: /* Disable Press measure function */ + { + adc->CONF &= ~ADC_CONF_ZEN_Msk; +#if defined(BSP_USING_ADC_TOUCH) + rt_mq_control(psNuAdc->m_pmqTouchXYZ, RT_IPC_CMD_RESET, RT_NULL); +#endif + } + break; + + case TZAVG_ON: /* Enable Pressure Mean average for Z1 and Z2 function */ + { + adc->CONF |= ADC_CONF_ZMAVDIS_Msk; + } + break; + + case TZAVG_OFF: /* Disable Pressure Mean average for Z1 and Z2 function */ + { + adc->CONF &= ~ADC_CONF_ZMAVDIS_Msk; + } + break; + + case NAC_ON: /* Enable Normal AD Conversion */ + { + adc->CONF |= (ADC_CONF_NACEN_Msk | ADC_CONF_REFSEL_AVDD33); + } + break; + + case NAC_OFF: /* Disable Normal AD Conversion */ + { + adc->CONF &= ~ADC_CONF_NACEN_Msk; + } + break; + + case SWITCH_CH: + { + int chn = (int)args; + if (chn >= ADC_CH_NUM) + { + return -ret; + } + adc->CONF &= ~ADC_CONF_CHSEL_Msk; + adc->CONF |= (chn << ADC_CONF_CHSEL_Pos); + } + break; + + default: + return -(ret); + } + + return RT_EOK; +} + +static rt_err_t _nu_adc_open(rt_device_t dev, rt_uint16_t oflag) +{ + nu_adc_t psNuAdc = (nu_adc_t)dev; + ADC_T *adc = psNuAdc->base; + + /* Enable ADC engine clock */ + CLK_EnableModuleClock(psNuAdc->modid); + + /* Reset the ADC IP */ + SYS_ResetModule(psNuAdc->modid); + + /* Enable ADC Power */ + ADC_POWER_ON(adc); + + /* Enable ADC to high speed mode */ + adc->CONF |= ADC_CONF_SPEED_Msk; + + /* Enable interrupt */ + rt_hw_interrupt_umask(psNuAdc->irqn); + + /* Enable Normal AD Conversion */ + _nu_adc_control(dev, NAC_ON, RT_NULL); + + return RT_EOK; +} + +static rt_err_t _nu_adc_close(rt_device_t dev) +{ + nu_adc_t psNuAdc = (nu_adc_t)dev; + ADC_T *adc = psNuAdc->base; + + /* Disable Normal AD Conversion */ + _nu_adc_control(dev, NAC_OFF, RT_NULL); + + /* Disable interrupt */ + rt_hw_interrupt_mask(psNuAdc->irqn); + + /* Disable ADC Power */ + ADC_POWER_DOWN(adc); + + /* Disable ADC engine clock */ + CLK_DisableModuleClock(psNuAdc->modid); + + return RT_EOK; +} + +static const struct rt_adc_ops nu_adc_ops = +{ + nu_adc_enabled, + nu_adc_convert, +}; + +/* nu_adc_enabled - Enable ADC clock and wait for ready */ +static rt_err_t nu_adc_enabled(struct rt_adc_device *device, rt_uint32_t channel, rt_bool_t enabled) +{ + nu_adc_t psNuADC = (nu_adc_t)device; + RT_ASSERT(device); + + if (channel >= ADC_CH_NUM) + return -(RT_EINVAL); + + if (enabled) + { + psNuADC->chn_mask |= (1 << channel); + } + else + { + psNuADC->chn_mask &= ~(1 << channel); + } + + if (psNuADC->chn_mask > 0 && ((rt_device_t)device)->ref_count == 0) + { + _nu_adc_open((rt_device_t)device, 0); + ((rt_device_t)device)->ref_count = 1; + } + else if ((psNuADC->chn_mask == 0) && ((rt_device_t)device)->ref_count == 1) + { + _nu_adc_close((rt_device_t)device); + ((rt_device_t)device)->ref_count = 0; + } + return RT_EOK; +} + +static rt_err_t nu_adc_convert(struct rt_adc_device *device, rt_uint32_t channel, rt_uint32_t *value) +{ + rt_err_t ret = RT_EOK; + + RT_ASSERT(device); + RT_ASSERT(value); + + if (channel >= ADC_CH_NUM) + { + ret = RT_EINVAL; + goto exit_nu_adc_convert; + } + else if ((ret = _nu_adc_control((rt_device_t)device, SWITCH_CH, (void *)channel)) != RT_EOK) + { + goto exit_nu_adc_convert; + } + else if ((ret = _nu_adc_control((rt_device_t)device, START_MST, (void *)value)) != RT_EOK) + { + goto exit_nu_adc_convert; + } + +exit_nu_adc_convert: + + return (-ret) ; +} + +int rt_hw_adc_init(void) +{ + rt_err_t result = RT_ERROR; + rt_device_t psDev = &g_sNuADC.dev.parent; + + result = rt_hw_adc_register(&g_sNuADC.dev, g_sNuADC.name, &nu_adc_ops, &g_sNuADC); + RT_ASSERT(result == RT_EOK); + + result = _nu_adc_init(psDev); + RT_ASSERT(result == RT_EOK); + + g_sNuADC.m_psSem = rt_sem_create("adc_mst_sem", 0, RT_IPC_FLAG_FIFO); + RT_ASSERT(g_sNuADC.m_psSem); + +#if defined(BSP_USING_ADC_TOUCH) + g_sNuADC.m_pmqTouchXYZ = rt_mq_create("ADC_TOUCH_XYZ", sizeof(struct nu_adc_touch_data), TOUCH_MQ_LENGTH, RT_IPC_FLAG_FIFO); + RT_ASSERT(g_sNuADC.m_pmqTouchXYZ); + + g_sNuADC.psRtTouchMenuTimer = rt_timer_create("TOUCH_SMPL_TIMER", nu_adc_touch_smpl, (void *)&g_sNuADC, DEF_ADC_TOUCH_SMPL_TICK, RT_TIMER_FLAG_PERIODIC); + RT_ASSERT(g_sNuADC.psRtTouchMenuTimer); +#endif + + rt_memset(&g_sNuADC.m_isr, 0, sizeof(g_sNuADC.m_isr)); + rt_memset(&g_sNuADC.m_wkisr, 0, sizeof(g_sNuADC.m_wkisr)); + + g_sNuADC.m_isr[eAdc_MF].cbfunc = AdcMenuStartCallback; + g_sNuADC.m_isr[eAdc_MF].private_data = (uint32_t)&g_sNuADC; + + return (int)result; +} +INIT_BOARD_EXPORT(rt_hw_adc_init); + +#endif //#if defined(BSP_USING_ADC) diff --git a/bsp/nuvoton/libraries/ma35/rtt_port/drv_adc.h b/bsp/nuvoton/libraries/ma35/rtt_port/drv_adc.h new file mode 100644 index 0000000000..1ccba61d18 --- /dev/null +++ b/bsp/nuvoton/libraries/ma35/rtt_port/drv_adc.h @@ -0,0 +1,63 @@ +/**************************************************************************//** +* +* @copyright (C) 2020 Nuvoton Technology Corp. All rights reserved. +* +* SPDX-License-Identifier: Apache-2.0 +* +* Change Logs: +* Date Author Notes +* 2021-4-7 Wayne First version +* +******************************************************************************/ + +#ifndef __DRV_ADC_H__ +#define __DRV_ADC_H__ + +#include +#include "nu_adc.h" + +#if defined(BSP_USING_ADC_TOUCH) + #include "touch.h" +#endif + +typedef enum +{ + eAdc_MF, //0 + eAdc_KPEF, //1 + eAdc_PEDEF, //2 + eAdc_KPUEF, //3 + eAdc_PEUEF, //4 + eAdc_TF = 8, //8 + eAdc_ZF, //9 + eAdc_NACF, //10 + eAdc_VBF, //11 + eAdc_KPCF, //12 + eAdc_SELFTF, //13 + eAdc_INTKP = 16, //16 + eAdc_INTTC, //17 + eAdc_ISR_CNT //18 +} E_ADC_ISR_EVENT; + +typedef enum +{ + eAdc_WKPEF, + eAdc_WPEDEF, + eAdc_WKISR_CNT +} E_ADC_WKISR_EVENT; + +typedef struct +{ + ADC_CALLBACK cbfunc; + uint32_t private_data; +} nu_adc_cb; + +typedef nu_adc_cb *nu_adc_cb_t; + +#if defined(BSP_USING_ADC_TOUCH) + void nu_adc_touch_detect(rt_bool_t bStartDetect); + int32_t nu_adc_touch_read_xyz(uint32_t *bufX, uint32_t *bufY, uint32_t *bufZ0, uint32_t *bufZ1, int32_t dataCnt); + rt_err_t nu_adc_touch_enable(rt_touch_t psRtTouch); + rt_err_t nu_adc_touch_disable(void); +#endif + +#endif /* __DRV_ADC_H__ */ diff --git a/bsp/nuvoton/libraries/ma35/rtt_port/drv_canfd.c b/bsp/nuvoton/libraries/ma35/rtt_port/drv_canfd.c new file mode 100644 index 0000000000..a8a2914b77 --- /dev/null +++ b/bsp/nuvoton/libraries/ma35/rtt_port/drv_canfd.c @@ -0,0 +1,660 @@ +/**************************************************************************//** +* +* @copyright (C) 2020 Nuvoton Technology Corp. All rights reserved. +* +* SPDX-License-Identifier: Apache-2.0 +* +* Change Logs: +* Date Author Notes +* 2022-4-27 Wayne First version +* +******************************************************************************/ + +#include + +#if defined(BSP_USING_CANFD) + +#include +#include + +#include "drv_sys.h" +#include "drv_common.h" +#include "nu_bitutil.h" + +#define LOG_TAG "drv.canfd" +#undef DBG_ENABLE +#define DBG_SECTION_NAME LOG_TAG +#define DBG_LEVEL LOG_LVL_ERROR +#define DBG_COLOR +#include + +/* Private Define ---------------------------------------------------------------*/ +#define IS_CAN_STDID(STDID) ((STDID) <= 0x7FFU) +#define IS_CAN_EXTID(EXTID) ((EXTID) <= 0x1FFFFFFFU) +#define IS_CAN_DLC(DLC) ((DLC) <= 8U) + +/* Default config for serial_configure structure */ +#define NU_CANFD_CONFIG_DEFAULT \ +{ \ + CAN1MBaud, /* 1M bits/s */ \ + RT_CANMSG_BOX_SZ, /* message box max size */ \ + RT_CANSND_BOX_NUM, /* message box number */ \ + RT_CAN_MODE_NORMAL, /* Normal mode */ \ + 0, /* privmode */ \ + 0, /* reserved */ \ + 100, /* Timeout Tick */ \ +} + +enum +{ + CANFD_START = -1, +#if defined(BSP_USING_CANFD0) + CANFD0_IDX, +#endif +#if defined(BSP_USING_CANFD1) + CANFD1_IDX, +#endif +#if defined(BSP_USING_CANFD2) + CANFD2_IDX, +#endif +#if defined(BSP_USING_CANFD3) + CANFD3_IDX, +#endif + CANFD_CNT +}; + +/* Private Typedef --------------------------------------------------------------*/ +struct nu_canfd +{ + struct rt_can_device dev; + char *name; + CANFD_T *base; + uint32_t rstidx; + IRQn_Type irqn0; + IRQn_Type irqn1; + uint32_t int_flag; + CANFD_FD_T sCANFD_Config; +}; +typedef struct nu_canfd *nu_canfd_t; + +/* Private functions ------------------------------------------------------------*/ +static rt_err_t nu_canfd_configure(struct rt_can_device *can, struct can_configure *cfg); +static rt_err_t nu_canfd_control(struct rt_can_device *can, int cmd, void *arg); +static int nu_canfd_sendmsg(struct rt_can_device *can, const void *buf, rt_uint32_t boxno); +static int nu_canfd_recvmsg(struct rt_can_device *can, void *buf, rt_uint32_t boxno); + +static struct nu_canfd nu_canfd_arr[] = +{ +#if defined(BSP_USING_CANFD0) + { + .name = "canfd0", + .base = CANFD0, + .rstidx = CANFD0_RST, + .irqn0 = CANFD00_IRQn, + .irqn1 = CANFD01_IRQn, + }, +#endif +#if defined(BSP_USING_CANFD1) + { + .name = "canfd1", + .base = CANFD1, + .rstidx = CANFD1_RST, + .irqn0 = CANFD10_IRQn, + .irqn1 = CANFD11_IRQn, + }, +#endif +#if defined(BSP_USING_CANFD2) + { + .name = "canfd2", + .base = CANFD2, + .rstidx = CANFD2_RST, + .irqn0 = CANFD20_IRQn, + .irqn1 = CANFD21_IRQn, + }, +#endif +#if defined(BSP_USING_CANFD3) + { + .name = "canfd3", + .base = CANFD3, + .rstidx = CANFD3_RST, + .irqn0 = CANFD30_IRQn, + .irqn1 = CANFD31_IRQn, + }, +#endif +}; /* struct nu_can */ + +/* Public functions ------------------------------------------------------------*/ + +/* Private variables ------------------------------------------------------------*/ +static const struct rt_can_ops nu_canfd_ops = +{ + .configure = nu_canfd_configure, + .control = nu_canfd_control, + .sendmsg = nu_canfd_sendmsg, + .recvmsg = nu_canfd_recvmsg, +}; + +static const struct can_configure nu_canfd_default_config = NU_CANFD_CONFIG_DEFAULT; + +/* Interrupt Handle Function ----------------------------------------------------*/ + +/* Private Variables ------------------------------------------------------------*/ +const char *szIR[] = +{ + "CANFD_IR_RF0N - Rx FIFO 0 New Message", + "CANFD_IR_RF0W - Rx FIFO 0 Watermark Reached", + "CANFD_IR_RF0F - Rx FIFO 0 Full", + "CANFD_IR_RF0L - Rx FIFO 0 Message Lost", + "CANFD_IR_RF1N - Rx FIFO 1 New Message", + "CANFD_IR_RF1W - Rx FIFO 1 Watermark Reached", + "CANFD_IR_RF1F - Rx FIFO 1 Full", + "CANFD_IR_RF1L - Rx FIFO 1 Message Lost", + "CANFD_IR_HPM - High Priority Message", + "CANFD_IR_TC - Transmission Completed", + "CANFD_IR_TCF - Transmission Cancellation Finished", + "CANFD_IR_TFE - Tx FIFO Empty", + "CANFD_IR_TEFN - Tx Event FIFO New Entry", + "CANFD_IR_TEFW - Tx Event FIFO Watermark Reached", + "CANFD_IR_TEFF - Tx Event FIFO Full", + "CANFD_IR_TEFL - Tx Event FIFO Event Lost", + "CANFD_IR_TSW - Timestamp Wraparound", + "CANFD_IR_MRAF - Message RAM Access Failure", + "CANFD_IR_TOO - Timeout Occurred", + "CANFD_IR_DRX - Message stored to Dedicated Rx Buffer", + "BIT20", + "BIT21", + "CANFD_IR_ELO - Error Logging Overflow", + "CANFD_IR_EP - Error Passive", + "CANFD_IR_EW - Warning Status", + "CANFD_IR_BO - Bus_Off Status", + "CANFD_IR_WDI - Watchdog", + "CANFD_IR_PEA - Protocol Error in Arbitration Phase", + "CANFD_IR_PED - Protocol Error in Data Phase", + "CANFD_IR_ARA - Access to Reserved Address", + "BIT30", + "BIT31" +}; + +static void dump_interrupt_event(uint32_t u32Status) +{ + uint32_t idx; + while ((idx = nu_ctz(u32Status)) < 32) // Count Trailing Zeros ==> Find First One + { + LOG_D("[%s]", szIR[idx]); + u32Status &= ~(1 << idx); + } +} + +static void nu_canfd_isr(int vector, void *param) +{ + /* Get base address of canfd register */ + nu_canfd_t psNuCANFD = (nu_canfd_t)param; + + /* Get base address of CAN register */ + CANFD_T *base = psNuCANFD->base; + + /* Get interrupt status */ + uint32_t u32Status = base->IR; + CANFD_ClearStatusFlag(base, u32Status); + + /* Dump IR event */ + dump_interrupt_event(u32Status); + + /* Check Status Interrupt Flag (Error status Int and Status change Int) */ + /**************************/ + /* Status Change interrupt*/ + /**************************/ + + if (u32Status & CANFD_IR_TC_Msk) + { + if (psNuCANFD->int_flag & RT_DEVICE_FLAG_INT_TX) + { + rt_hw_can_isr(&psNuCANFD->dev, RT_CAN_EVENT_TX_DONE); + } + } + + if (u32Status & (CANFD_IR_RF0N_Msk | CANFD_IR_RF1N_Msk)) + { + if (psNuCANFD->int_flag & RT_DEVICE_FLAG_INT_RX) + { + rt_hw_can_isr(&psNuCANFD->dev, RT_CAN_EVENT_RX_IND); + } + } + + if (u32Status & (CANFD_IR_RF0L_Msk | CANFD_IR_RF1L_Msk)) + { + rt_hw_can_isr(&psNuCANFD->dev, RT_CAN_EVENT_RXOF_IND); + } + + if (u32Status & (CANFD_IR_TEFF_Msk | CANFD_IR_TOO_Msk)) + { + rt_hw_can_isr(&psNuCANFD->dev, RT_CAN_EVENT_TX_FAIL); + } + + /**************************/ + /* Error Status interrupt */ + /**************************/ + if (u32Status & CANFD_IR_EW_Msk) + { + LOG_E("[%s]EWARN", psNuCANFD->name) ; + } + + if (u32Status & CANFD_IR_BO_Msk) + { + LOG_E("[%s]BUSOFF", psNuCANFD->name) ; + + /* To release busoff pin */ + } + + if (u32Status & CANFD_IR_PED_Msk) + { + LOG_E("[%s] LEC: %03x\n", psNuCANFD->name, base->PSR & CANFD_PSR_LEC_Msk) ; + } +} + +static void nu_canfd_ie(nu_canfd_t psNuCANFD) +{ + uint32_t u32CanFDIE = CANFD_IE_BOE_Msk; + + if (psNuCANFD->int_flag & (RT_DEVICE_FLAG_INT_RX)) + { + /* Rx FIFO 0 New Message Interrupt */ + u32CanFDIE |= (CANFD_IE_RF0NE_Msk | CANFD_IE_RF1NE_Msk); + } + + if (psNuCANFD->int_flag & (RT_DEVICE_FLAG_INT_TX)) + { + /* Transmission Completed Interrupt */ + /* Timeout Occurred Interrupt */ + u32CanFDIE |= (CANFD_IE_TCE_Msk | CANFD_IE_TEFNE_Msk); + } + + if (psNuCANFD->int_flag & RT_DEVICE_CAN_INT_ERR) + { + /* Bus_Off Status Interrupt */ + /* Warning Status Interrupt */ + /* Error Passive Interrupt */ + /* Error Logging Overflow Interrupt */ + /* Protocol Error in Data Phase interrupt Indicator */ + u32CanFDIE |= (CANFD_IE_EPE_Msk | CANFD_IE_EWE_Msk | CANFD_IE_ELOE_Msk | CANFD_IE_TOOE_Msk | CANFD_IR_PED_Msk); + } + + //u32CanFDIE = 0xffffffff; + + CANFD_EnableInt(psNuCANFD->base, u32CanFDIE, 0, + (psNuCANFD->int_flag & (RT_DEVICE_FLAG_INT_TX)) ? CANFD_TXBTIE_TIEn_Msk : 0, + (psNuCANFD->int_flag & (RT_DEVICE_FLAG_INT_TX)) ? CANFD_TXBCIE_CFIEn_Msk : 0); +} + +static rt_err_t nu_canfd_configure(struct rt_can_device *can, struct can_configure *cfg) +{ + nu_canfd_t psNuCANFD = (nu_canfd_t)can; + CANFD_FD_T *psCANFDConf; + + RT_ASSERT(can); + RT_ASSERT(cfg); + + psCANFDConf = &psNuCANFD->sCANFD_Config; + + /* Get base address of CAN register */ + CANFD_T *base = psNuCANFD->base; + + CANFD_GetDefaultConfig(psCANFDConf, CANFD_OP_CAN_MODE); + + LOG_I("Message Ram Size: %d @%08x ~ %08x", psCANFDConf->u32MRamSize, CANFD_SRAM_BASE_ADDR(base), psCANFDConf->u32MRamSize + CANFD_SRAM_BASE_ADDR(base)); + LOG_I("SIDFC: %d @%08x Size:%d", psCANFDConf->sElemSize.u32SIDFC, CANFD_SRAM_BASE_ADDR(base) + psCANFDConf->sMRamStartAddr.u32SIDFC_FLSSA, psCANFDConf->sElemSize.u32SIDFC * sizeof(CANFD_STD_FILTER_T)); + LOG_I("XIDFC: %d @%08x Size:%d", psCANFDConf->sElemSize.u32XIDFC, CANFD_SRAM_BASE_ADDR(base) + psCANFDConf->sMRamStartAddr.u32XIDFC_FLESA, psCANFDConf->sElemSize.u32XIDFC * sizeof(CANFD_EXT_FILTER_T)); + LOG_I("RxFifo0: %d @%08x Size:%d", psCANFDConf->sElemSize.u32RxFifo0, CANFD_SRAM_BASE_ADDR(base) + psCANFDConf->sMRamStartAddr.u32RXF0C_F0SA, psCANFDConf->sElemSize.u32RxFifo0 * sizeof(CANFD_BUF_T)); + LOG_I("RxFifo1: %d @%08x Size:%d", psCANFDConf->sElemSize.u32RxFifo1, CANFD_SRAM_BASE_ADDR(base) + psCANFDConf->sMRamStartAddr.u32RXF1C_F1SA, psCANFDConf->sElemSize.u32RxFifo1 * sizeof(CANFD_BUF_T)); + LOG_I("RxBuf: %d @%08x Size:%d", psCANFDConf->sElemSize.u32RxBuf, CANFD_SRAM_BASE_ADDR(base) + psCANFDConf->sMRamStartAddr.u32RXBC_RBSA, psCANFDConf->sElemSize.u32RxBuf * sizeof(CANFD_BUF_T)); + LOG_I("TxEventFifo: %d @%08x Size:%d", psCANFDConf->sElemSize.u32TxEventFifo, CANFD_SRAM_BASE_ADDR(base) + psCANFDConf->sMRamStartAddr.u32TXEFC_EFSA, psCANFDConf->sElemSize.u32TxEventFifo * sizeof(CANFD_EXT_FILTER_T)); + LOG_I("TxBuf: %d @%08x Size:%d", psCANFDConf->sElemSize.u32TxBuf, CANFD_SRAM_BASE_ADDR(base) + psCANFDConf->sMRamStartAddr.u32TXBC_TBSA, psCANFDConf->sElemSize.u32TxBuf * sizeof(CANFD_BUF_T)); + + psCANFDConf->sBtConfig.sNormBitRate.u32BitRate = cfg->baud_rate; + psCANFDConf->sBtConfig.sDataBitRate.u32BitRate = 0; + + LOG_I("CAN Baud rate: %d bps", cfg->baud_rate); + + switch (cfg->mode) + { + case RT_CAN_MODE_NORMAL: // Normal + psCANFDConf->sBtConfig.evTestMode = eCANFD_NORMAL; + break; + + case RT_CAN_MODE_LISTEN: // Bus monitor Mode, can't start a transmission + psCANFDConf->sBtConfig.evTestMode = eCANFD_BUS_MONITOR; + break; + + case RT_CAN_MODE_LOOPBACK: // Test - Internal loopback + psCANFDConf->sBtConfig.evTestMode = eCANFD_LOOPBACK_INTERNAL; + break; + + case RT_CAN_MODE_LOOPBACKANLISTEN: + default: + rt_kprintf("Unsupported Operating mode\n"); + goto exit_nu_canfd_configure; + } + + /*Set the CAN Bit Rate and Operating mode*/ + CANFD_Open(base, psCANFDConf); + + /* Set FIFO policy */ +#if defined(RT_CAN_USING_HDR) + /* Whitelist filtering */ + CANFD_SetGFC(base, eCANFD_REJ_NON_MATCH_FRM, eCANFD_REJ_NON_MATCH_FRM, 0, 0); +#else + /* Blacklist filtering. */ + CANFD_SetGFC(base, eCANFD_ACC_NON_MATCH_FRM_RX_FIFO0, eCANFD_ACC_NON_MATCH_FRM_RX_FIFO0, 0, 0); +#endif + + /* Enable interrupt */ + nu_canfd_ie(psNuCANFD); + + //LOG_HEX("canfd", 16, (void *)base, sizeof(CANFD_T)); + + /* Lock protected registers & Run */ + CANFD_RunToNormal(base, TRUE); + + return RT_EOK; + +exit_nu_canfd_configure: + + CANFD_Close(base); + + return -(RT_ERROR); +} + +static rt_err_t nu_canfd_control(struct rt_can_device *can, int cmd, void *arg) +{ + rt_uint32_t argval = (rt_uint32_t)arg; + nu_canfd_t psNuCANFD = (nu_canfd_t)can; + + RT_ASSERT(can); + + switch (cmd) + { + case RT_DEVICE_CTRL_SET_INT: + psNuCANFD->int_flag |= argval; + return nu_canfd_configure(can, &can->config); + + case RT_DEVICE_CTRL_CLR_INT: + psNuCANFD->int_flag &= ~argval; + return nu_canfd_configure(can, &can->config); + +#if defined(RT_CAN_USING_HDR) + case RT_CAN_CMD_SET_FILTER: + { + struct rt_can_filter_config *filter_cfg = (struct rt_can_filter_config *)arg; + + RT_ASSERT(filter_cfg); + + for (int i = 0; i < filter_cfg->count; i++) + { + uint32_t u32FEC = (filter_cfg->items[i].mode == RT_CAN_MODE_PRIV) ? eCANFD_FLTR_ELEM_SET_PRI_STO_FIFO0 : eCANFD_FLTR_ELEM_STO_FIFO0; + + /* Set the filter rule */ + if (filter_cfg->items[i].ide == RT_CAN_STDID) + { + /* for 11-bit */ + CANFD_STD_FILTER_T sStdFilter; + + if (i >= CANFD_MAX_11_BIT_FTR_ELEMS) // Check filter entry limitation + return -(RT_ERROR); + + sStdFilter.SFID2 = filter_cfg->items[i].mask; /*!items[i].id; /*!base, i, sStdFilter.VALUE); + } + else + { + /* for 29-bit */ + CANFD_EXT_FILTER_T sXidFilter; + + if (i >= CANFD_MAX_29_BIT_FTR_ELEMS) // Check filter entry limitation + return -(RT_ERROR); + + sXidFilter.EFID1 = filter_cfg->items[i].mask; /*!items[i].id; /*!base, i, sXidFilter.LOWVALUE, sXidFilter.HIGHVALUE); + } + + } //for (int i = 0; i < filter_cfg->count; i++) + } + break; +#endif + + case RT_CAN_CMD_SET_MODE: + if ((argval == RT_CAN_MODE_NORMAL) || + (argval == RT_CAN_MODE_LISTEN) || + (argval == RT_CAN_MODE_LOOPBACK) || + (argval == RT_CAN_MODE_LOOPBACKANLISTEN)) + { + if (argval != can->config.mode) + { + can->config.mode = argval; + return nu_canfd_configure(can, &can->config); + } + } + else + { + return -(RT_ERROR); + } + break; + + case RT_CAN_CMD_SET_BAUD: + { + if ((argval == CAN1MBaud) || + (argval == CAN800kBaud) || + (argval == CAN500kBaud) || + (argval == CAN250kBaud) || + (argval == CAN125kBaud) || + (argval == CAN100kBaud) || + (argval == CAN50kBaud) || + (argval == CAN20kBaud) || + (argval == CAN10kBaud)) + { + if (argval != can->config.baud_rate) + { + can->config.baud_rate = argval; + return nu_canfd_configure(can, &can->config); + } + } + else + { + return -(RT_ERROR); + } + } + break; + + case RT_CAN_CMD_SET_PRIV: + if (argval != RT_CAN_MODE_PRIV && + argval != RT_CAN_MODE_NOPRIV) + { + return -(RT_ERROR); + } + if (argval != can->config.privmode) + { + can->config.privmode = argval; + return nu_canfd_configure(can, &can->config); + } + break; + + case RT_CAN_CMD_GET_STATUS: + { + rt_uint32_t u32ErrCounter = psNuCANFD->base->ECR; + rt_uint32_t u32ProtocolStatus = psNuCANFD->base->PSR; + + RT_ASSERT(arg); + + /*Receive Error Counter, return value is with Receive Error Passive.*/ + can->status.rcverrcnt = ((u32ErrCounter & CANFD_ECR_REC_Msk) >> CANFD_ECR_REC_Pos); + + /*Transmit Error Counter*/ + can->status.snderrcnt = ((u32ErrCounter & CANFD_ECR_TEC_Msk) >> CANFD_ECR_TEC_Pos); + + /*Last Error Type*/ + can->status.lasterrtype = ((u32ProtocolStatus & CANFD_PSR_LEC_Msk) >> CANFD_PSR_LEC_Pos); + + /*Status error code*/ + can->status.errcode = (u32ProtocolStatus & CANFD_PSR_EW_Msk) ? 1 : + (u32ProtocolStatus & CANFD_PSR_EP_Msk) ? 2 : + (u32ProtocolStatus & CANFD_PSR_BO_Msk) ? 3 : + 0; + + rt_memcpy(arg, &can->status, sizeof(struct rt_can_status)); + } + break; + + default: + return -(RT_EINVAL); + + } + + return RT_EOK; +} + +static int nu_canfd_sendmsg(struct rt_can_device *can, const void *buf, rt_uint32_t boxno) +{ + CANFD_FD_MSG_T sTxMsg; + struct rt_can_msg *pmsg; + nu_canfd_t psNuCANFD = (nu_canfd_t)can; + + RT_ASSERT(can); + RT_ASSERT(buf); + + pmsg = (struct rt_can_msg *) buf; + + if (pmsg->ide == RT_CAN_STDID && IS_CAN_STDID(pmsg->id)) + { + /* Standard ID (11 bits)*/ + sTxMsg.u32Id = pmsg->id; + sTxMsg.eIdType = eCANFD_SID; + } + else if (pmsg->ide == RT_CAN_EXTID && IS_CAN_EXTID(pmsg->id)) + { + /* Extended ID (29 bits)*/ + sTxMsg.u32Id = pmsg->id; + sTxMsg.eIdType = eCANFD_XID; + } + else + { + goto exit_nu_canfd_sendmsg; + } + + sTxMsg.bBitRateSwitch = 0; + + if (pmsg->rtr == RT_CAN_DTR) + { + /* Data frame */ + sTxMsg.eFrmType = eCANFD_DATA_FRM; + } + else if (pmsg->rtr == RT_CAN_RTR) + { + /* Remote frame */ + sTxMsg.eFrmType = eCANFD_REMOTE_FRM; + } + else + { + goto exit_nu_canfd_sendmsg; + } + + /* Check the parameters */ + if (IS_CAN_DLC(pmsg->len)) + { + sTxMsg.u32DLC = pmsg->len; + } + else + { + goto exit_nu_canfd_sendmsg; + } + + if (pmsg->len > 0) + { + rt_memcpy(&sTxMsg.au8Data[0], pmsg->data, pmsg->len); + } + + if (!CANFD_TransmitTxMsg(psNuCANFD->base, 0, &sTxMsg)) + { + goto exit_nu_canfd_sendmsg; + } + + return RT_EOK; + +exit_nu_canfd_sendmsg: + + return -(RT_ERROR); +} + +static int nu_canfd_recvmsg(struct rt_can_device *can, void *buf, rt_uint32_t boxno) +{ + CANFD_FD_MSG_T sRxMsg; + struct rt_can_msg *pmsg; + nu_canfd_t psNuCANFD = (nu_canfd_t)can; + + RT_ASSERT(can); + RT_ASSERT(buf); + + pmsg = (struct rt_can_msg *) buf; + + /* get data */ + if (CANFD_ReadRxFifoMsg(psNuCANFD->base, 0, &sRxMsg) == FALSE) + { + rt_kprintf("No available RX Msg.\n"); + return -(RT_ERROR); + } + +#ifdef RT_CAN_USING_HDR + /* Hardware filter messages are valid */ + pmsg->hdr = boxno; + can->hdr[pmsg->hdr].connected = 1; +#endif + + pmsg->ide = (sRxMsg.eIdType == eCANFD_SID) ? RT_CAN_STDID : RT_CAN_EXTID; + pmsg->rtr = (sRxMsg.eFrmType == eCANFD_DATA_FRM) ? RT_CAN_DTR : RT_CAN_RTR; + pmsg->id = sRxMsg.u32Id; + pmsg->len = sRxMsg.u32DLC; + + if (pmsg->len > 0) + rt_memcpy(&pmsg->data[0], &sRxMsg.au8Data[0], pmsg->len); + + return RT_EOK; +} + +/** + * Hardware CAN Initialization + */ +static int rt_hw_canfd_init(void) +{ + int i; + rt_err_t ret = RT_EOK; + + for (i = (CANFD_START + 1); i < CANFD_CNT; i++) + { + nu_canfd_arr[i].dev.config = nu_canfd_default_config; + +#ifdef RT_CAN_USING_HDR + nu_canfd_arr[i].dev.config.maxhdr = RT_CANMSG_BOX_SZ; +#endif + /* Register can device */ + ret = rt_hw_can_register(&nu_canfd_arr[i].dev, nu_canfd_arr[i].name, &nu_canfd_ops, NULL); + RT_ASSERT(ret == RT_EOK); + + /* Register ISR. */ + rt_hw_interrupt_install(nu_canfd_arr[i].irqn0, nu_canfd_isr, &nu_canfd_arr[i], nu_canfd_arr[i].name); + rt_hw_interrupt_install(nu_canfd_arr[i].irqn1, nu_canfd_isr, &nu_canfd_arr[i], nu_canfd_arr[i].name); + + /* Unmask interrupt. */ + rt_hw_interrupt_umask(nu_canfd_arr[i].irqn0); + rt_hw_interrupt_umask(nu_canfd_arr[i].irqn1); + } + + return (int)ret; +} +INIT_DEVICE_EXPORT(rt_hw_canfd_init); +#endif //#if defined(BSP_USING_CANFD) diff --git a/bsp/nuvoton/libraries/ma35/rtt_port/drv_ccap.c b/bsp/nuvoton/libraries/ma35/rtt_port/drv_ccap.c new file mode 100644 index 0000000000..1c9292baf2 --- /dev/null +++ b/bsp/nuvoton/libraries/ma35/rtt_port/drv_ccap.c @@ -0,0 +1,489 @@ +/**************************************************************************//** +* +* @copyright (C) 2019 Nuvoton Technology Corp. All rights reserved. +* +* SPDX-License-Identifier: Apache-2.0 +* +* Change Logs: +* Date Author Notes +* 2022-8-16 Wayne First version +* +******************************************************************************/ + +#include + +#if defined(BSP_USING_CCAP) + +#include +#include "NuMicro.h" +#include "ccap_sensor.h" +#include "drv_ccap.h" + +#define LOG_TAG "drv.ccap" +#define DBG_ENABLE +#define DBG_SECTION_NAME LOG_TAG +#define DBG_LEVEL LOG_LVL_INFO +#define DBG_COLOR +#include + + +/* Private Typedef --------------------------------------------------------------*/ + +enum +{ + CCAP_START = -1, +#if defined(BSP_USING_CCAP0) + CCAP0_IDX, +#endif +#if defined(BSP_USING_CCAP1) + CCAP1_IDX, +#endif + CCAP_CNT +}; + +struct nu_ccap +{ + struct rt_device device; + char *name; + CCAP_T *base; + uint32_t rstidx; + uint32_t modid_ccap; + IRQn_Type irqn; + + ccap_config sConfig; +}; +typedef struct nu_ccap *nu_ccap_t; + +static struct nu_ccap nu_ccap_arr [] = +{ +#if defined(BSP_USING_CCAP0) + { + .name = "ccap0", + .base = CCAP0, + .rstidx = CCAP0_RST, + .modid_ccap = CCAP0_MODULE, + .irqn = CCAP0_IRQn, + }, +#endif +#if defined(BSP_USING_CCAP1) + { + .name = "ccap1", + .base = CCAP1, + .rstidx = CCAP1_RST, + .modid_ccap = CCAP1_MODULE, + .irqn = CCAP1_IRQn, + }, +#endif +}; + +static void nu_ccap_isr(int vector, void *param) +{ + nu_ccap_t ccap = (nu_ccap_t)param; + CCAP_T *base = ccap->base; + uint32_t u32CapInt, u32EvtMsk; + + u32CapInt = base->INT; + u32EvtMsk = 0; + + if ((u32CapInt & (CCAP_INT_VIEN_Msk | CCAP_INT_VINTF_Msk)) == (CCAP_INT_VIEN_Msk | CCAP_INT_VINTF_Msk)) + { + base->INT |= CCAP_INT_VINTF_Msk; /* Clear Frame end interrupt */ + u32EvtMsk |= NU_CCAP_FRAME_END; + } + + if ((u32CapInt & (CCAP_INT_ADDRMIEN_Msk | CCAP_INT_ADDRMINTF_Msk)) == (CCAP_INT_ADDRMIEN_Msk | CCAP_INT_ADDRMINTF_Msk)) + { + base->INT |= CCAP_INT_ADDRMINTF_Msk; /* Clear Address match interrupt */ + u32EvtMsk |= NU_CCAP_ADDRESS_MATCH; + } + + if ((u32CapInt & (CCAP_INT_MEIEN_Msk | CCAP_INT_MEINTF_Msk)) == (CCAP_INT_MEIEN_Msk | CCAP_INT_MEINTF_Msk)) + { + base->INT |= CCAP_INT_MEINTF_Msk; /* Clear Memory error interrupt */ + u32EvtMsk |= NU_CCAP_MEMORY_ERROR; + } + + /* Invoke callback */ + if (ccap->device.rx_indicate != RT_NULL) + ccap->device.rx_indicate(&ccap->device, 1); + + if (ccap->sConfig.pfnEvHndler && u32EvtMsk) + ccap->sConfig.pfnEvHndler(ccap->sConfig.pvData, u32EvtMsk); + + base->CTL = base->CTL | CCAP_CTL_UPDATE; +} + +/* common device interface */ +static rt_err_t ccap_init(rt_device_t dev) +{ + return RT_EOK; +} + +static void ccap_sensor_setfreq(nu_ccap_t psNuCcap, uint32_t u32SensorFreq) +{ + uint32_t u32RegLockLevel = SYS_IsRegLocked(); + + /* Unlock protected registers */ + if (u32RegLockLevel) + SYS_UnlockReg(); + + if (u32SensorFreq > 0) + { + int32_t i32Div; + + /* Specified sensor clock */ + i32Div = CLK_GetPLLClockFreq(SYSPLL) / u32SensorFreq; + + if (i32Div == 0) + i32Div = 1; + + CLK_EnableModuleClock(psNuCcap->modid_ccap); + if (psNuCcap->base == CCAP0) + CLK_SetModuleClock(psNuCcap->modid_ccap, CLK_CLKSEL0_CCAP0SEL_SYSPLL, CLK_CLKDIV1_CCAP0(i32Div)); + else if (psNuCcap->base == CCAP1) + CLK_SetModuleClock(psNuCcap->modid_ccap, CLK_CLKSEL0_CCAP1SEL_SYSPLL, CLK_CLKDIV1_CCAP1(i32Div)); + else + return; + + LOG_I("CCAP Engine clock:%d", CLK_GetPLLClockFreq(SYSPLL)); + LOG_I("CCAP Sensor preferred clock %d, divider:%d", u32SensorFreq, i32Div); + LOG_I("CCAP Sensor actully clock:%d", CLK_GetPLLClockFreq(SYSPLL) / i32Div); + } + else + { + CLK_DisableModuleClock(psNuCcap->modid_ccap); + } + + /* Lock protected registers */ + if (u32RegLockLevel) + SYS_LockReg(); +} + +static rt_err_t ccap_pipe_configure(nu_ccap_t psNuCcap, ccap_view_info_t psViewInfo) +{ + sensor_mode_info_t psSensorModeInfo = (sensor_mode_info_t)psViewInfo; + ccap_config_t psCcapConf = &psNuCcap->sConfig; + uint32_t u32PipeEnabling = 0; + struct rt_device_rect_info *psRectCropping = &psCcapConf->sRectCropping; + + /* Set Cropping Window Vertical/Horizontal Starting Address and Cropping Window Size */ + CCAP_SetCroppingWindow(psNuCcap->base, psRectCropping->y, psRectCropping->x, psRectCropping->height, psRectCropping->width); + + if (psCcapConf->sPipeInfo_Packet.pu8FarmAddr) + { + uint32_t u32WM, u32WN, u32HM, u32HN; + + /* Set System Memory Packet Base Address Register */ + CCAP_SetPacketBuf(psNuCcap->base, (uint32_t)psCcapConf->sPipeInfo_Packet.pu8FarmAddr); + + u32WM = u32WN = u32HM = u32HN = 0; + /* Set Packet Scaling Vertical/Horizontal Factor Register */ + if (psCcapConf->sPipeInfo_Packet.u32Height < psRectCropping->height) + { + u32HN = psCcapConf->sPipeInfo_Packet.u32Height; + u32HM = psRectCropping->height; + } + + if (psCcapConf->sPipeInfo_Packet.u32Width < psRectCropping->width) + { + u32WN = psCcapConf->sPipeInfo_Packet.u32Width; + u32WM = psRectCropping->width; + } + + CCAP_SetPacketScaling(psNuCcap->base, + u32HN, + u32HM, + u32WN, + u32WM); + + /* Set Packet Frame Output Pixel Stride Width */ + CCAP_SetPacketStride(psNuCcap->base, psCcapConf->u32Stride_Packet); + + u32PipeEnabling |= CCAP_CTL_PKTEN; + } + + if (psCcapConf->sPipeInfo_Planar.pu8FarmAddr) + { + uint32_t u32Offset = 0; + uint32_t u32WM, u32WN, u32HM, u32HN; + uint32_t u32Div = 0; + + if (psCcapConf->sPipeInfo_Planar.u32PixFmt == CCAP_PAR_PLNFMT_YUV422) + { + /* U/V farm size equals Y/2 farm size */ + u32Div = 2; + } + else if (psCcapConf->sPipeInfo_Planar.u32PixFmt == CCAP_PAR_PLNFMT_YUV420) + { + /* U/V farm size equals Y/4 farm size */ + u32Div = 4; + } + else + { + goto fail_ccap_pipe_configure; + } + + /* Set System Memory Planar Y Base Address Register */ + CCAP_SetPlanarYBuf(psNuCcap->base, (uint32_t)psCcapConf->sPipeInfo_Planar.pu8FarmAddr + u32Offset); + + u32Offset = psCcapConf->sPipeInfo_Planar.u32Height * psCcapConf->sPipeInfo_Planar.u32Width; + + /* Set System Memory Planar U Base Address Register */ + CCAP_SetPlanarUBuf(psNuCcap->base, (uint32_t)psCcapConf->sPipeInfo_Planar.pu8FarmAddr + u32Offset); + + u32Offset += ((psCcapConf->sPipeInfo_Planar.u32Height * psCcapConf->sPipeInfo_Planar.u32Width) / u32Div); + + /* Set System Memory Planar V Base Address Register */ + CCAP_SetPlanarVBuf(psNuCcap->base, (uint32_t)psCcapConf->sPipeInfo_Planar.pu8FarmAddr + u32Offset); + + u32WM = u32WN = u32HM = u32HN = 0; + /* Set Planar Scaling Vertical/Horizontal Factor Register */ + if (psCcapConf->sPipeInfo_Planar.u32Height < psRectCropping->height) + { + u32HN = psCcapConf->sPipeInfo_Planar.u32Height; + u32HM = psRectCropping->height; + } + + if (psCcapConf->sPipeInfo_Planar.u32Width < psRectCropping->width) + { + u32WN = psCcapConf->sPipeInfo_Planar.u32Width; + u32WM = psRectCropping->width; + } + + /* Set Planar Scaling Vertical/Horizontal Factor Register */ + CCAP_SetPlanarScaling(psNuCcap->base, + u32HN, + u32HM, + u32WN, + u32WM); + + /* Set Planar Frame Output Pixel Stride Width */ + CCAP_SetPlanarStride(psNuCcap->base, psCcapConf->u32Stride_Planar); + + u32PipeEnabling |= CCAP_CTL_PLNEN; + } + + /* Set Vsync polarity, Hsync polarity, pixel clock polarity, Sensor Format and Order */ + CCAP_Open(psNuCcap->base, + psSensorModeInfo->u32Polarity | + psViewInfo->u32PixFmt | + psCcapConf->sPipeInfo_Packet.u32PixFmt | + psCcapConf->sPipeInfo_Planar.u32PixFmt, + u32PipeEnabling); + + return RT_EOK; + +fail_ccap_pipe_configure: + + return -RT_ERROR; +} + +static rt_err_t ccap_open(rt_device_t dev, rt_uint16_t oflag) +{ + nu_ccap_t psNuCcap = (nu_ccap_t)dev; + + uint32_t u32RegLockLevel = SYS_IsRegLocked(); + + /* Unlock protected registers */ + if (u32RegLockLevel) + SYS_UnlockReg(); + + /* Enable clock */ + ccap_sensor_setfreq(psNuCcap, 24000000); + + /* Reset IP */ + SYS_ResetModule(psNuCcap->rstidx); + + /* Lock protected registers */ + if (u32RegLockLevel) + SYS_LockReg(); + + /* Unmask External CCAP Interrupt */ + rt_hw_interrupt_umask(psNuCcap->irqn); + + return RT_EOK; +} + +static rt_err_t ccap_close(rt_device_t dev) +{ + nu_ccap_t psNuCcap = (nu_ccap_t)dev; + + /* Stop capture engine */ + CCAP_Stop(psNuCcap->base, FALSE); + + /* Disable CCAP Interrupt */ + CCAP_DisableInt(psNuCcap->base, CCAP_INT_VIEN_Msk); + + /* Mask External CCAP Interrupt */ + rt_hw_interrupt_mask(psNuCcap->irqn); + + /* Disable clock */ + ccap_sensor_setfreq(psNuCcap, 0); + + return RT_EOK; +} + +static rt_err_t ccap_control(rt_device_t dev, int cmd, void *args) +{ + nu_ccap_t psNuCcap = (nu_ccap_t)dev; + rt_err_t ret = -RT_ERROR; + + if (psNuCcap == RT_NULL) + goto exit_ccap_control; + + switch (cmd) + { + case CCAP_CMD_CONFIG: + { + ccap_config *psCcapConf = (ccap_config *)args; + if (args == RT_NULL) + goto exit_ccap_control; + + rt_memcpy(&psNuCcap->sConfig, psCcapConf, sizeof(ccap_config)); + } + break; + + case CCAP_CMD_START_CAPTURE: + + /* Enable CCAP Interrupt */ + CCAP_EnableInt(psNuCcap->base, CCAP_INT_VIEN_Msk); + + /* Start capture engine */ + CCAP_Start(psNuCcap->base); + + break; + + case CCAP_CMD_STOP_CAPTURE: + + /* Disable CCAP Interrupt */ + CCAP_DisableInt(psNuCcap->base, CCAP_INT_VIEN_Msk); + + /* Stop capture engine */ + CCAP_Stop(psNuCcap->base, FALSE); + + break; + + case CCAP_CMD_SET_SENCLK: + { + rt_uint32_t u32SenClk; + + RT_ASSERT(args); + + u32SenClk = *((rt_uint32_t *)args); + if (u32SenClk > 0) + ccap_sensor_setfreq(psNuCcap, u32SenClk); + } + break; + + case CCAP_CMD_SET_PIPES: + { + ccap_view_info_t psViewInfo; + + RT_ASSERT(args); + psViewInfo = (ccap_view_info_t)args; + + ret = ccap_pipe_configure(psNuCcap, psViewInfo); + } + break; + + case CCAP_CMD_SET_OPMODE: + { + RT_ASSERT(args); + int i32IsOneSutterMode = *((int *)args); + + /* Set shutter or continuous mode */ + CCAP_SET_CTL(psNuCcap->base, (i32IsOneSutterMode > 0) ? CCAP_CTL_SHUTTER_Msk : 0); + } + break; + + case CCAP_CMD_SET_BASEADDR: + { + uint32_t u32Offset = 0; + ccap_config_t psCcapConf; + + RT_ASSERT(args); + psCcapConf = (ccap_config_t)args; + + /* Set System Memory Packet Base Address Register */ + CCAP_SetPacketBuf(psNuCcap->base, (uint32_t)psCcapConf->sPipeInfo_Packet.pu8FarmAddr); + + /* Set System Memory Planar Y Base Address Register */ + CCAP_SetPlanarYBuf(psNuCcap->base, (uint32_t)psCcapConf->sPipeInfo_Planar.pu8FarmAddr + u32Offset); + u32Offset = psCcapConf->sPipeInfo_Planar.u32Height * psCcapConf->sPipeInfo_Planar.u32Width; + /* Set System Memory Planar U Base Address Register */ + CCAP_SetPlanarUBuf(psNuCcap->base, (uint32_t)psCcapConf->sPipeInfo_Planar.pu8FarmAddr + u32Offset); + u32Offset += ((psCcapConf->sPipeInfo_Planar.u32Height * psCcapConf->sPipeInfo_Planar.u32Width) / 2); + /* Set System Memory Planar V Base Address Register */ + CCAP_SetPlanarVBuf(psNuCcap->base, (uint32_t)psCcapConf->sPipeInfo_Planar.pu8FarmAddr + u32Offset); + } + break; + + default: + return -RT_ENOSYS; + } + + ret = RT_EOK; + +exit_ccap_control: + + return ret; +} + +#ifdef RT_USING_DEVICE_OPS +static struct rt_device_ops ccap_ops = +{ + .init = ccap_init, + .open = ccap_open, + .close = ccap_close, + .read = RT_NULL, + .write = RT_NULL, + .control = ccap_control, +}; +#endif + +static rt_err_t ccap_register(struct rt_device *device, const char *name, void *user_data) +{ + RT_ASSERT(device); + + device->type = RT_Device_Class_Miscellaneous; + device->rx_indicate = RT_NULL; + device->tx_complete = RT_NULL; + +#ifdef RT_USING_DEVICE_OPS + device->ops = &inputcapture_ops; +#else + device->init = ccap_init; + device->open = ccap_open; + device->close = ccap_close; + device->read = RT_NULL; + device->write = RT_NULL; + device->control = ccap_control; +#endif + device->user_data = user_data; + + return rt_device_register(device, name, RT_DEVICE_FLAG_RDONLY | RT_DEVICE_FLAG_STANDALONE); +} + +/** + * Hardware CCAP Initialization + */ +int rt_hw_ccap_init(void) +{ + int i; + rt_err_t ret = RT_EOK; + + for (i = (CCAP_START + 1); i < CCAP_CNT; i++) + { + rt_memset(&nu_ccap_arr[i].sConfig, 0, sizeof(ccap_config)); + + rt_hw_interrupt_install(nu_ccap_arr[i].irqn, nu_ccap_isr, &nu_ccap_arr[i], nu_ccap_arr[i].name); + + ret = ccap_register(&nu_ccap_arr[i].device, nu_ccap_arr[i].name, NULL); + RT_ASSERT(ret == RT_EOK); + } + + return ret; +} +INIT_DEVICE_EXPORT(rt_hw_ccap_init); + +#endif diff --git a/bsp/nuvoton/libraries/ma35/rtt_port/drv_ccap.h b/bsp/nuvoton/libraries/ma35/rtt_port/drv_ccap.h new file mode 100644 index 0000000000..711971421f --- /dev/null +++ b/bsp/nuvoton/libraries/ma35/rtt_port/drv_ccap.h @@ -0,0 +1,49 @@ +/**************************************************************************//** +* +* @copyright (C) 2019 Nuvoton Technology Corp. All rights reserved. +* +* SPDX-License-Identifier: Apache-2.0 +* +* Change Logs: +* Date Author Notes +* 2022-8-16 Wayne First version +* +******************************************************************************/ + +#ifndef __DRV_CCAP_H__ +#define __DRV_CCAP_H__ + +#include "ccap_sensor.h" + +#define NU_CCAP_FRAME_END (1<<0) +#define NU_CCAP_ADDRESS_MATCH (1<<1) +#define NU_CCAP_MEMORY_ERROR (1<<2) +#define NU_CCAP_MOTION_DETECT (1<<3) + +typedef void (*nu_ccap_event_handler_t)(void *pvData, uint32_t u32EvtMask); + +typedef enum +{ + CCAP_CMD_CONFIG, + CCAP_CMD_START_CAPTURE, + CCAP_CMD_STOP_CAPTURE, + CCAP_CMD_SET_SENCLK, + CCAP_CMD_SET_PIPES, + CCAP_CMD_SET_OPMODE, + CCAP_CMD_SET_BASEADDR, +} ccap_cmd; + +typedef struct +{ + struct rt_device_rect_info sRectCropping; + ccap_view_info sPipeInfo_Packet; + ccap_view_info sPipeInfo_Planar; + uint32_t u32Stride_Packet; + uint32_t u32Stride_Planar; + + nu_ccap_event_handler_t pfnEvHndler; // Callback function in ISR + void *pvData; // For ISR callback argument. +} ccap_config; +typedef ccap_config *ccap_config_t; + +#endif //__DRV_CCAP_H__ diff --git a/bsp/nuvoton/libraries/ma35/rtt_port/drv_common.c b/bsp/nuvoton/libraries/ma35/rtt_port/drv_common.c new file mode 100644 index 0000000000..75bee5bd6c --- /dev/null +++ b/bsp/nuvoton/libraries/ma35/rtt_port/drv_common.c @@ -0,0 +1,437 @@ +/**************************************************************************//** +* +* @copyright (C) 2020 Nuvoton Technology Corp. All rights reserved. +* +* SPDX-License-Identifier: Apache-2.0 +* +* Change Logs: +* Date Author Notes +* 2021-07-14 Wayne First version +* +******************************************************************************/ + +#include +#include +#include + +#include "drv_common.h" +#include "board.h" +#include "drv_uart.h" + +#define LOG_TAG "drv.common" +#undef DBG_ENABLE +#define DBG_SECTION_NAME LOG_TAG +#define DBG_LEVEL LOG_LVL_DBG +#define DBG_COLOR +#include + +#if defined(USE_MA35D1_AARCH32) +#define NORMAL_MEM_UNCACHED (SHARED|AP_RW|DOMAIN0|STRONGORDER|DESC_SEC) + +/* +MMU TLB setting: +0xFFFFFFFF ---------------------------- + | 1GB DDR(non-cacheable) | +0xC0000000 ---------------------------- + | 1GB DDR(cacheable) | +0x80000000 ---------------------------- + | DEVICE_MEM | + | | +0x00000000 ---------------------------- +*/ +struct mem_desc platform_mem_desc[] = +{ + {0x00000000, 0x7FFFFFFF, 0x00000000, DEVICE_MEM}, // Peripherals + {0x80000000, DDR_LIMIT_SIZE - 1, 0x80000000, NORMAL_MEM}, // 1GB DDR, cacheable + {0xC0000000, 0xFFFFFFFF, 0x80000000, NORMAL_MEM_UNCACHED} // 1GB DDR, non-cacheable +}; +const rt_uint32_t platform_mem_desc_size = sizeof(platform_mem_desc) / sizeof(platform_mem_desc[0]); +#endif + +static void nu_mmu_initialize(void) +{ +#if defined(USE_MA35D1_AARCH64) + mmu_init(); + /* device memory 0x0000_0000 - 0x3FFF_FFFF */ + armv8_map(0x00000000, 0x00000000, 0x40000000, MEM_ATTR_IO); + /* device memory 0x4000_0000 - 0x7FFF_FFFF */ + armv8_map(0x40000000, 0x40000000, 0x40000000, MEM_ATTR_IO); + /* system memory 0x8000_0000 - 0xFFFF_FFFF */ + armv8_map(0x80000000, 0x80000000, 0x80000000, MEM_ATTR_MEMORY); + mmu_enable(); +#endif +} + +#if !defined(USE_MA35D1_SUBM) + +volatile uint32_t secondary_cpu_entry __attribute__((aligned(32))) = 0; +static rt_uint32_t timerStep; +void rt_hw_systick_isr(int vector, void *parameter) +{ + gtimer_set_load_value(timerStep); + rt_tick_increase(); +} + +int rt_hw_systick_init(void) +{ + rt_hw_interrupt_install(NonSecPhysicalTimer_IRQn, rt_hw_systick_isr, RT_NULL, "systick"); + rt_hw_interrupt_umask(NonSecPhysicalTimer_IRQn); + timerStep = gtimer_get_counter_frequency(); + timerStep /= RT_TICK_PER_SECOND; + gtimer_set_load_value(timerStep); + gtimer_set_control(1); + return 0; +} + +void nu_sspcc_init(void) +{ + int i, j; + + CLK->APBCLK2 |= CLK_APBCLK2_SSPCCEN_Msk; + /* Set all GPIO security set to TZNS. */ + for (i = 0; i < 16; i++) + { + for (j = 0; j < 14; j++) + { + SSPCC_SetRealm_GPIO(GPIO_BASE + (j * 0x40), i, SSPCC_SSET_TZNS); + } + } +} + +void nu_ssmcc_init(void) +{ + CLK->APBCLK2 |= CLK_APBCLK2_SSMCCEN_Msk; + + /* set region 0 to secure region, non-secure and m4 all can access */ + SSMCC_SetRegion0(SSMCC_SECURE_READ | SSMCC_SECURE_WRITE | SSMCC_NONSECURE_READ | SSMCC_NONSECURE_WRITE | SSMCC_M4NS_READ | SSMCC_M4NS_WRITE); +} + +void nu_ddr_init(void) +{ + UMCTL2->PCTRL_0 = UMCTL2_PCTRL_0_port_en_Msk; //[0x0490] + UMCTL2->PCTRL_1 = UMCTL2_PCTRL_1_port_en_Msk; //[0x0540] + UMCTL2->PCTRL_2 = UMCTL2_PCTRL_2_port_en_Msk; //[0x05f0] + UMCTL2->PCTRL_3 = UMCTL2_PCTRL_3_port_en_Msk; //[0x06a0] + + UMCTL2->PCTRL_4 = UMCTL2_PCTRL_4_port_en_Msk; //[0x0750] + UMCTL2->PCTRL_5 = UMCTL2_PCTRL_5_port_en_Msk; //[0x0800] + UMCTL2->PCTRL_6 = UMCTL2_PCTRL_6_port_en_Msk; //[0x08b0] + UMCTL2->PCTRL_7 = UMCTL2_PCTRL_7_port_en_Msk; //[0x0960] +} + +void rt_hw_us_delay(rt_uint32_t us) +{ + rt_uint32_t ticks; + volatile rt_uint32_t told, tnow, tcnt = 0; + rt_uint32_t cmp = timerStep; // 12000 count / 1ms + + ticks = us * (cmp / 1000); // us * 12(count/1us) + told = gtimer_get_current_value(); + + while (1) + { + /* Timer counter is increment. */ + tnow = gtimer_get_current_value(); + if (tnow != told) + { + /* 0 -- now === old -------- cmp */ + if (tnow < told) + { + tcnt += (told - tnow); + } + else + { + /* 0 == old --- new ======== cmp */ + tcnt += (cmp - tnow + told); + } + told = tnow; + + /* Timeout */ + if (tcnt >= ticks) + { + break; + } + } + __NOP(); + } +} /* rt_hw_us_delay */ + +#else + +void SysTick_Handler(void) +{ + /* enter interrupt */ + rt_interrupt_enter(); + + rt_tick_increase(); + + /* leave interrupt */ + rt_interrupt_leave(); +} + +int rt_hw_systick_init(void) +{ + /* User can use SystemCoreClockUpdate() to calculate SystemCoreClock. */ + SystemCoreClockUpdate(); + + /* Configure SysTick */ + SysTick_Config(SystemCoreClock / RT_TICK_PER_SECOND); + + + return 0; +} + +/** + * The time delay function. + * + * @param microseconds. + */ +void rt_hw_us_delay(rt_uint32_t us) +{ + rt_uint32_t ticks; + rt_uint32_t told, tnow, tcnt = 0; + rt_uint32_t reload = SysTick->LOAD; + + ticks = us * reload / (1000000 / RT_TICK_PER_SECOND); + told = SysTick->VAL; + while (1) + { + tnow = SysTick->VAL; + if (tnow != told) + { + if (tnow < told) + { + tcnt += told - tnow; + } + else + { + tcnt += reload - tnow + told; + } + told = tnow; + if (tcnt >= ticks) + { + break; + } + } + } +} + +#endif + + +void devmem(int argc, char *argv[]) +{ + volatile unsigned int u32Addr; + unsigned int value = 0, mode = 0; + + if (argc < 2 || argc > 3) + { + goto exit_devmem; + } + + if (argc == 3) + { + if (sscanf(argv[2], "0x%x", &value) != 1) + goto exit_devmem; + mode = 1; //Write + } + + if (sscanf(argv[1], "0x%x", &u32Addr) != 1) + goto exit_devmem; + else if (u32Addr & (4 - 1)) + goto exit_devmem; + + if (mode) + { + *((volatile uint32_t *)u32Addr) = value; + } + rt_kprintf("0x%08x\n", *((volatile uint32_t *)u32Addr)); + + return; +exit_devmem: + rt_kprintf("Read: devmem \n"); + rt_kprintf("Write: devmem \n"); + return; +} +MSH_CMD_EXPORT(devmem, dump device registers); + +void devmem2(int argc, char *argv[]) +{ + volatile unsigned int u32Addr; + unsigned int value = 0, word_count = 1; + + if (argc < 2 || argc > 3) + { + goto exit_devmem; + } + + if (argc == 3) + { + if (sscanf(argv[2], "%d", &value) != 1) + goto exit_devmem; + word_count = value; + } + + if (sscanf(argv[1], "0x%x", &u32Addr) != 1) + goto exit_devmem; + else if (u32Addr & (4 - 1)) + goto exit_devmem; + + if (word_count > 0) + { + LOG_HEX("devmem", 16, (void *)u32Addr, word_count * sizeof(rt_base_t)); + } + + return; +exit_devmem: + rt_kprintf("devmem2: \n"); + return; +} +MSH_CMD_EXPORT(devmem2, dump device registers); + +void idle_wfi(void) +{ +#if defined(USE_MA35D1_SUBM) + __WFI(); +#else + asm volatile("wfi"); +#endif +} + +extern void nu_clock_dump(void); +extern void nu_clock_raise(void); + +RT_WEAK void nutool_pincfg_init(void) +{ + +} + +/** + * This function will initial board. + */ +RT_WEAK void rt_hw_board_init(void) +{ + /* Unlock protected registers */ + SYS_UnlockReg(); + +#if !defined(USE_MA35D1_SUBM) + /* initialize SSPCC */ + nu_sspcc_init(); + + /* initialize SSMCC */ + nu_ssmcc_init(); + + /* initialize UMCTL2 */ + nu_ddr_init(); + +#endif + + /* initialize base clock */ + nu_clock_init(); + + + /* initialize peripheral pin function */ + nutool_pincfg_init(); + + /* initialize hardware interrupt */ + rt_hw_interrupt_init(); + + /* initialize MMU */ + nu_mmu_initialize(); + +#if defined(RT_USING_HEAP) + rt_system_heap_init((void *)BOARD_HEAP_START, (void *)BOARD_HEAP_END); +#endif + + /* initialize uart */ + rt_hw_uart_init(); + +#if defined(RT_USING_CONSOLE) + rt_console_set_device(RT_CONSOLE_DEVICE_NAME); +#endif + +#if !defined(USE_MA35D1_SUBM) +#if !defined(USE_MA35D1_AARCH64) + //TOFIX + nu_clock_raise(); +#endif + nu_clock_dump(); +#endif + +#if defined(RT_USING_HEAP) + /* Dump heap information */ + rt_kprintf("Heap: Begin@%08x, END@%08x, SIZE: %d KiB\n", BOARD_HEAP_START, BOARD_HEAP_END, ((rt_uint32_t)BOARD_HEAP_END - (rt_uint32_t)BOARD_HEAP_START) / 1024); +#endif + + /* initialize systick */ + rt_hw_systick_init(); + rt_thread_idle_sethook(idle_wfi); + +#if defined(RT_USING_COMPONENTS_INIT) + rt_components_board_init(); +#endif + +#if defined(RT_USING_SMP) + /* install IPI handle */ + rt_hw_interrupt_set_priority(RT_SCHEDULE_IPI, 16); + rt_hw_ipi_handler_install(RT_SCHEDULE_IPI, rt_scheduler_ipi_handler); + rt_hw_interrupt_umask(RT_SCHEDULE_IPI); +#endif + +} + +#if defined(RT_USING_SMP) + +extern void secondary_cpu_start(void); +void set_secondary_cpu_boot_address(void) +{ + secondary_cpu_entry = (uint32_t)&secondary_cpu_start; + rt_kprintf("Wake up cpu-1 goto -> 0x%08x\n", secondary_cpu_entry); +} + +void rt_hw_secondary_cpu_up(void) +{ + rt_uint32_t i; + rt_uint32_t cpu_mask; + + rt_kprintf("rt_hw_secondary_cpu_up is processing \r\n"); + + set_secondary_cpu_boot_address(); + + /* Flush to memory */ + rt_cpu_dcache_clean_flush(); + + for (i = 1; i < RT_CPUS_NR; i++) + { + rt_kprintf("Bring up cpu-%d\r\n", i); + cpu_mask = 1 << i; + __asm__ volatile("dsb" :: + : "memory"); + __asm__ volatile("isb" :: + : "memory"); + __asm__ volatile("sev"); + rt_hw_ipi_send(RT_SCHEDULE_IPI, cpu_mask); + } +} + +void secondary_cpu_c_start(void) +{ + rt_kprintf("[%s] cpu-%d\r\n", __func__, rt_hw_cpu_id()); + + rt_hw_vector_init(); + + rt_hw_spin_lock(&_cpus_lock); + + arm_gic_cpu_init(0, platform_get_gic_cpu_base()); + rt_hw_systick_init(); + + rt_system_scheduler_start(); +} + +void rt_hw_secondary_cpu_idle_exec(void) +{ + asm volatile("wfe" :: + : "memory", "cc"); +} + +#endif diff --git a/bsp/nuvoton/libraries/ma35/rtt_port/drv_common.h b/bsp/nuvoton/libraries/ma35/rtt_port/drv_common.h new file mode 100644 index 0000000000..fc0e3ee187 --- /dev/null +++ b/bsp/nuvoton/libraries/ma35/rtt_port/drv_common.h @@ -0,0 +1,83 @@ +/**************************************************************************//** +* +* @copyright (C) 2020 Nuvoton Technology Corp. All rights reserved. +* +* SPDX-License-Identifier: Apache-2.0 +* +* Change Logs: +* Date Author Notes +* 2020-12-12 Wayne First version +* +******************************************************************************/ + +#ifndef __DRV_COMMON_H__ +#define __DRV_COMMON_H__ + +#include +#include "NuMicro.h" +#include "interrupt.h" + +#if !defined(USE_MA35D1_SUBM) + +#include "gic.h" +#include "mmu.h" +#include "cp15.h" +#include "gtimer.h" + +#define __REG32(x) (*((volatile unsigned int*)((rt_ubase_t)x))) + +#define GIC_ACK_INTID_MASK 0x000003ff +#define ARM_GIC_NR_IRQS 256 +#define MAX_HANDLERS ARM_GIC_NR_IRQS +#define ARM_GIC_MAX_NR 1 +#define GIC_IRQ_START 0 + +#define DDR_LIMIT_SIZE 0xC0000000u +#define UNCACHEABLE 0x40000000u + +#define SSPCC_SET_REALM(IP, REALM) \ + do { \ + rt_kprintf("Set %s realm to %s(%d)\n", #IP, #REALM, REALM); \ + SSPCC_SetRealm(IP, REALM); \ + rt_kprintf("Get %s realm is %d ....%s\n", #IP, SSPCC_GetRealm(IP), (SSPCC_GetRealm(IP)==REALM)?"Success":"Failure"); \ + } while(0) + +#define SSPCC_SET_GPIO_REALM(PORT, PIN, REALM) \ + do { \ + rt_kprintf("Set %s%s realm to %s(%d)\n", #PORT, #PIN, #REALM, REALM); \ + SSPCC_SetRealm_GPIO((uint32_t)PORT, PIN, REALM); \ + rt_kprintf("Get %s%s realm is %d ....%s\n", #PORT, #PIN, SSPCC_GetRealm_GPIO((uint32_t)PORT, PIN), (SSPCC_GetRealm_GPIO((uint32_t)PORT, PIN)==REALM)?"Success":"Failure"); \ + } while(0) + + +/* the basic constants needed by gic */ +rt_inline rt_uint32_t platform_get_gic_dist_base(void) +{ + return GIC_DISTRIBUTOR_BASE; +} + +rt_inline rt_uint32_t platform_get_gic_cpu_base(void) +{ + return GIC_INTERFACE_BASE; +} + +rt_inline rt_uint32_t nu_cpu_dcache_line_size(void) +{ + rt_uint32_t ctr = 0; +#if defined(USE_MA35D1_AARCH32) + asm volatile("mrc p15, 0, %0, c0, c0, 1" : "=r"(ctr)); +#elif defined(USE_MA35D1_AARCH64) + asm volatile("mrs %0, ctr_el0" : "=r"(ctr)); +#endif + return 4 << ((ctr >> 16) & 0xF); +} +extern void rt_hw_cpu_dcache_clean(void *addr, int size); +extern void rt_hw_cpu_dcache_clean_inv(void *addr, int size); +extern void rt_hw_cpu_dcache_invalidate(void *addr, int size); +#else +#define UNCACHEABLE 0 +#endif + +void nu_clock_init(void); + +#endif /* __DRV_COMMON_H__ */ diff --git a/bsp/nuvoton/libraries/ma35/rtt_port/drv_disp.c b/bsp/nuvoton/libraries/ma35/rtt_port/drv_disp.c new file mode 100644 index 0000000000..2319257273 --- /dev/null +++ b/bsp/nuvoton/libraries/ma35/rtt_port/drv_disp.c @@ -0,0 +1,450 @@ +/**************************************************************************//** +* +* @copyright (C) 2020 Nuvoton Technology Corp. All rights reserved. +* +* SPDX-License-Identifier: Apache-2.0 +* +* Change Logs: +* Date Author Notes +* 2021-8-11 Wayne First version +* +******************************************************************************/ + +#include + +#if defined(BSP_USING_DISP) + +#include +#include +#include +#include "NuMicro.h" +#include +#include +#include +#include + +#if !defined(DISP_USING_LCD_IDX) + #define DISP_USING_LCD_IDX eDispLcd_1024x600 +#endif + +#if !defined(BSP_LCD_BPP) + #define BSP_LCD_BPP 32 +#endif + +#if !defined(DISP_USING_OVERLAY) + #define DISP_USING_OVERLAY +#endif + +#define DEF_VPOST_BUFFER_NUMBER 3 + +/* Private typedef --------------------------------------------------------------*/ +struct nu_disp +{ + struct rt_device dev; + char *name; + E_DISP_LAYER layer; + uint32_t last_commit; + uint32_t ref_count; + struct rt_device_graphic_info info; + rt_uint8_t *pu8FBDMABuf; +}; +typedef struct nu_disp *nu_disp_t; + +static volatile uint32_t g_u32VSyncBlank = 0; +static struct rt_completion vsync_wq; + +static struct nu_disp nu_fbdev[eLayer_Cnt] = +{ + { + .name = "lcd", + .layer = eLayer_Video, + .ref_count = 0, + } +#if defined(DISP_USING_OVERLAY) + , { + .name = "overlay", + .layer = eLayer_Overlay, + .ref_count = 0, + } +#endif +}; + +RT_WEAK void nu_lcd_backlight_on(void) { } + +RT_WEAK void nu_lcd_backlight_off(void) { } + +static void nu_disp_isr(int vector, void *param) +{ + /* Get DISP INTSTS */ + if (DISP_GET_INTSTS()) + { + g_u32VSyncBlank++; + rt_completion_done(&vsync_wq); + } +} + +static rt_err_t disp_layer_open(rt_device_t dev, rt_uint16_t oflag) +{ + nu_disp_t psDisp = (nu_disp_t)dev; + RT_ASSERT(psDisp != RT_NULL); + + psDisp->ref_count++; + +#if defined(DISP_USING_OVERLAY) + if (psDisp->layer == eLayer_Overlay) // Depend on video layer + { + nu_fbdev[eLayer_Video].ref_count++; + } +#endif + + if (nu_fbdev[eLayer_Video].ref_count == 1) + { + DISP_SetTransparencyMode(eLayer_Video, eMASK); + DISP_ENABLE_INT(); + DISP_Trigger(eLayer_Video, 1); + } + +#if defined(DISP_USING_OVERLAY) + if (nu_fbdev[eLayer_Overlay].ref_count == 1) + { + DISP_SetTransparencyMode(eLayer_Overlay, eOPAQUE); + DISP_Trigger(eLayer_Overlay, 1); + } +#endif + + return RT_EOK; +} + +static rt_err_t disp_layer_close(rt_device_t dev) +{ + nu_disp_t psDisp = (nu_disp_t)dev; + RT_ASSERT(psDisp != RT_NULL); + + psDisp->ref_count--; + +#if defined(DISP_USING_OVERLAY) + if (psDisp->layer == eLayer_Overlay) // Depend on video layer + { + nu_fbdev[eLayer_Video].ref_count--; + } + + if (nu_fbdev[eLayer_Overlay].ref_count == 0) + { + DISP_Trigger(eLayer_Overlay, 0); + } +#endif + + if (nu_fbdev[eLayer_Video].ref_count == 0) + { + DISP_DISABLE_INT(); + DISP_Trigger(eLayer_Video, 0); + } + + return RT_EOK; +} + +static rt_err_t disp_layer_control(rt_device_t dev, int cmd, void *args) +{ + nu_disp_t psDisp = (nu_disp_t)dev; + RT_ASSERT(psDisp != RT_NULL); + + switch (cmd) + { + case RTGRAPHIC_CTRL_POWERON: + { + nu_lcd_backlight_on(); + } + break; + + case RTGRAPHIC_CTRL_POWEROFF: + { + nu_lcd_backlight_off(); + } + break; + + case RTGRAPHIC_CTRL_GET_INFO: + { + struct rt_device_graphic_info *info = (struct rt_device_graphic_info *) args; + RT_ASSERT(info != RT_NULL); + rt_memcpy(args, (void *)&psDisp->info, sizeof(struct rt_device_graphic_info)); + } + break; + + case RTGRAPHIC_CTRL_SET_MODE: + { + int pixfmt, bpp; + E_FB_FMT eFBFmt; + + RT_ASSERT(args); + pixfmt = *((int *)args); + + switch (pixfmt) + { + case RTGRAPHIC_PIXEL_FORMAT_RGB565: + eFBFmt = eFBFmt_R5G6B5; + bpp = 16; + break; + case RTGRAPHIC_PIXEL_FORMAT_ARGB888: + eFBFmt = eFBFmt_A8R8G8B8; + bpp = 32; + break; + case RTGRAPHIC_PIXEL_FORMAT_MONO: + case RTGRAPHIC_PIXEL_FORMAT_GRAY4: + case RTGRAPHIC_PIXEL_FORMAT_GRAY16: + case RTGRAPHIC_PIXEL_FORMAT_RGB332: + case RTGRAPHIC_PIXEL_FORMAT_RGB444: + case RTGRAPHIC_PIXEL_FORMAT_BGR565: + case RTGRAPHIC_PIXEL_FORMAT_RGB666: + case RTGRAPHIC_PIXEL_FORMAT_RGB888: + case RTGRAPHIC_PIXEL_FORMAT_BGR888: + case RTGRAPHIC_PIXEL_FORMAT_ABGR888: + case RTGRAPHIC_PIXEL_FORMAT_RESERVED: + default: + return -RT_ERROR; + } + psDisp->info.bits_per_pixel = bpp; + psDisp->info.pixel_format = pixfmt; + psDisp->info.pitch = psDisp->info.width * (bpp >> 3U); + + /* Initial LCD */ + DISP_SetFBFmt(psDisp->layer, eFBFmt, psDisp->info.pitch); + + + } + break; + + case RTGRAPHIC_CTRL_GET_MODE: + { + RT_ASSERT(args); + *((int *)args) = psDisp->info.pixel_format; + } + break; + + case RTGRAPHIC_CTRL_PAN_DISPLAY: + { + if (args != RT_NULL) + { + uint32_t u32BufPtr = (uint32_t)args; + psDisp->last_commit = g_u32VSyncBlank; + + /* Pan display */ + return (DISP_SetFBAddr(psDisp->layer, u32BufPtr) == 0) ? RT_EOK : -RT_ERROR; + } + else + return -RT_ERROR; + } + break; + + case RTGRAPHIC_CTRL_WAIT_VSYNC: + { + if (args != RT_NULL) + psDisp->last_commit = g_u32VSyncBlank + 1; + + if (psDisp->last_commit >= g_u32VSyncBlank) + { + rt_completion_init(&vsync_wq); + rt_completion_wait(&vsync_wq, RT_TICK_PER_SECOND / 60); + } + } + break; + + default: + return -RT_ERROR; + } + + return RT_EOK; +} + +static rt_err_t disp_layer_init(rt_device_t dev) +{ + nu_disp_t psDisp = (nu_disp_t)dev; + RT_ASSERT(psDisp != RT_NULL); + + rt_completion_init(&vsync_wq); + return RT_EOK; +} + +int rt_hw_disp_init(void) +{ + int i; + rt_err_t ret; + + /* Get LCD panel instance by ID. */ + const DISP_LCD_INFO *psDispLcdInstance = DISP_GetLCDInst(DISP_USING_LCD_IDX); + RT_ASSERT(psDispLcdInstance != RT_NULL); + + /* Initial LCD */ + DISP_LCDInit(psDispLcdInstance); + + for (i = eLayer_Video; +#if defined(DISP_USING_OVERLAY) + i < eLayer_Cnt; +#else + i < eLayer_Overlay; +#endif + i++) + { + E_FB_FMT eFbFmt; + nu_disp_t psDisp = &nu_fbdev[i]; + rt_memset((void *)&psDisp->info, 0, sizeof(struct rt_device_graphic_info)); + + /* Register Disp device information */ + psDisp->info.bits_per_pixel = BSP_LCD_BPP; + psDisp->info.pixel_format = (BSP_LCD_BPP == 32) ? RTGRAPHIC_PIXEL_FORMAT_ARGB888 : RTGRAPHIC_PIXEL_FORMAT_RGB565; + psDisp->info.pitch = psDispLcdInstance->u32ResolutionWidth * (BSP_LCD_BPP / 8); + psDisp->info.width = psDispLcdInstance->u32ResolutionWidth; + psDisp->info.height = psDispLcdInstance->u32ResolutionHeight; + + /* Get pointer of video frame buffer */ + rt_uint8_t *pu8FBDMABuf = rt_malloc_align(psDisp->info.pitch * psDisp->info.height * DEF_VPOST_BUFFER_NUMBER, 128); + if (pu8FBDMABuf == NULL) + { + rt_kprintf("Fail to get VRAM buffer for %s layer.\n", psDisp->name); + RT_ASSERT(0); + } + else + { + /* Register non-cacheable DMA address to upper layer. */ + psDisp->info.framebuffer = (rt_uint8_t *)((uint32_t)pu8FBDMABuf | UNCACHEABLE); + + uint32_t u32FBSize = psDisp->info.pitch * psDispLcdInstance->u32ResolutionHeight; + psDisp->info.smem_len = u32FBSize * DEF_VPOST_BUFFER_NUMBER; + rt_memset(psDisp->info.framebuffer, 0, psDisp->info.smem_len); + } + + eFbFmt = (psDisp->info.pixel_format == RTGRAPHIC_PIXEL_FORMAT_ARGB888) ? eFBFmt_A8R8G8B8 : eFBFmt_R5G6B5 ; + ret = (rt_err_t)DISP_SetFBConfig(i, eFbFmt, psDisp->info.width, psDisp->info.height, (uint32_t)pu8FBDMABuf); + RT_ASSERT(ret == RT_EOK); + psDisp->pu8FBDMABuf = pu8FBDMABuf; + + /* Register member functions of lcd device */ + psDisp->dev.type = RT_Device_Class_Graphic; + psDisp->dev.init = disp_layer_init; + psDisp->dev.open = disp_layer_open; + psDisp->dev.close = disp_layer_close; + psDisp->dev.control = disp_layer_control; + + /* register graphic device driver */ + ret = rt_device_register(&psDisp->dev, psDisp->name, RT_DEVICE_FLAG_RDWR); + RT_ASSERT(ret == RT_EOK); + + rt_kprintf("%s's fbdev video memory at 0x%08x.\n", psDisp->name, psDisp->info.framebuffer); + } + + /* Register ISR */ + rt_hw_interrupt_install(DISP_IRQn, nu_disp_isr, RT_NULL, "DISP"); + + /* Enable interrupt. */ + rt_hw_interrupt_umask(DISP_IRQn); + + return (int)ret; +} +INIT_DEVICE_EXPORT(rt_hw_disp_init); + +static void lcd_show_video_layer(void) +{ + rt_device_open(&nu_fbdev[eLayer_Video].dev, RT_DEVICE_FLAG_RDWR); +} +MSH_CMD_EXPORT(lcd_show_video_layer, show video layer); + +static void lcd_hide_video_layer(void) +{ + rt_device_close(&nu_fbdev[eLayer_Video].dev); +} +MSH_CMD_EXPORT(lcd_hide_video_layer, hide video layer); + +#if defined(DISP_USING_OVERLAY) + +int nu_overlay_set_colkey(uint32_t u32Low, uint32_t u32High) +{ + DISP_SetColorKeyValue(u32Low, u32High); + DISP_SetTransparencyMode(eLayer_Overlay, eKEY); + return 0; +} +RTM_EXPORT(nu_overlay_set_colkey); + +/* Support "lcd_set_overlay_colkey" command line in msh mode */ +static rt_err_t lcd_set_overlay_colkey(int argc, char **argv) +{ + unsigned int index, len, arg[2]; + + rt_memset(arg, 0, sizeof(arg)); + len = (argc >= 3) ? 3 : argc; + + for (index = 0; index < (len - 1); index ++) + { + if (sscanf(argv[index + 1], "%x", &arg[index]) != 1) + return -1; + } + rt_kprintf("colkeylow:0x%08x colkeyhigh:0x%08x\n", arg[0], arg[1]); + nu_overlay_set_colkey(arg[0], arg[1]); + + return 0; +} +MSH_CMD_EXPORT(lcd_set_overlay_colkey, e.g: lcd_set_overlay_colkey colkeylow colkeyhigh); + +static void lcd_show_overlay_layer(void) +{ + rt_device_open(&nu_fbdev[eLayer_Overlay].dev, RT_DEVICE_FLAG_RDWR); +} + +static void lcd_hide_overlay_layer(void) +{ + rt_device_close(&nu_fbdev[eLayer_Overlay].dev); +} +MSH_CMD_EXPORT(lcd_show_overlay_layer, show overlay layer); +MSH_CMD_EXPORT(lcd_hide_overlay_layer, hide overlay layer); + +static void lcd_fill_layer_color(void) +{ + nu_disp_t psDispLayer; + int idx; + for (idx = eLayer_Overlay; //eLayer_Video; +#if defined(DISP_USING_OVERLAY) + idx < eLayer_Cnt; +#else + idx < eLayer_Overlay; +#endif + idx++) + { + psDispLayer = &nu_fbdev[idx]; + if (psDispLayer->info.framebuffer != RT_NULL) + { + int i; + uint32_t fill_num = psDispLayer->info.height * psDispLayer->info.width; + uint32_t *fbmem_start = (uint32_t *)psDispLayer->info.framebuffer; + uint32_t color = (0x3F << 24) | (rand() % 0x1000000) ; + rt_kprintf("fill color=0x%08x on %s layer\n", color, psDispLayer->name); + for (i = 0; i < fill_num; i++) + { + rt_memcpy((void *)&fbmem_start[i], &color, (psDispLayer->info.bits_per_pixel / 8)); + } + } + } +} +MSH_CMD_EXPORT(lcd_fill_layer_color, fill random color on overlay layer); + +static rt_err_t lcd_set_alphablend_opmode(int argc, char **argv) +{ + unsigned int index, len, arg[1]; + + rt_memset(arg, 0, sizeof(arg)); + len = (argc >= 2) ? 2 : argc; + + for (index = 0; index < (len - 1); index ++) + { + if (sscanf(argv[index + 1], "%x", &arg[index]) != 1) + return -1; + } + + rt_kprintf("opmode:0x%08x\n", arg[0]); + + if (arg[0] <= DC_BLEND_MODE_SRC_OUT) + DISP_SetBlendOpMode(arg[0], eGloAM_NORMAL, eGloAM_NORMAL); + + return 0; +} +MSH_CMD_EXPORT(lcd_set_alphablend_opmode, Set alpha blending opmode); +#endif + +#endif /* if defined(BSP_USING_DISP) */ diff --git a/bsp/nuvoton/libraries/ma35/rtt_port/drv_eadc.c b/bsp/nuvoton/libraries/ma35/rtt_port/drv_eadc.c new file mode 100644 index 0000000000..f022392aa0 --- /dev/null +++ b/bsp/nuvoton/libraries/ma35/rtt_port/drv_eadc.c @@ -0,0 +1,154 @@ +/**************************************************************************//** +* @copyright (C) 2020 Nuvoton Technology Corp. All rights reserved. +* +* SPDX-License-Identifier: Apache-2.0 +* +* Change Logs: +* Date Author Notes +* 2021-9-23 Wayne First version +* +******************************************************************************/ + +#include + +#if defined(BSP_USING_EADC) + +#include +#include "NuMicro.h" + +/* Private define ---------------------------------------------------------------*/ +#define DEF_EADC_MAX_CHANNEL_NUM 8 + +enum +{ + EADC_START = -1, +#if defined(BSP_USING_EADC0) + EADC0_IDX, +#endif + EADC_CNT +}; + +/* Private Typedef --------------------------------------------------------------*/ +struct nu_eadc +{ + struct rt_adc_device parent; + char *name; + EADC_T *base; + uint32_t rstidx; + uint32_t modid; + uint32_t chnmask; +}; +typedef struct nu_eadc *nu_eadc_t; + +/* Private functions ------------------------------------------------------------*/ +static rt_err_t nu_eadc_enabled(struct rt_adc_device *device, rt_uint32_t channel, rt_bool_t enabled); +static rt_err_t nu_get_eadc_value(struct rt_adc_device *device, rt_uint32_t channel, rt_uint32_t *value); +static rt_err_t nu_get_eadc_value(struct rt_adc_device *device, rt_uint32_t channel, rt_uint32_t *value); + +/* Public functions ------------------------------------------------------------*/ +int rt_hw_eadc_init(void); + +/* Private variables ------------------------------------------------------------*/ + +static struct nu_eadc nu_eadc_arr [] = +{ +#if defined(BSP_USING_EADC0) + { .name = "eadc0", .base = EADC0, .rstidx = EADC0_RST, .modid = EADC0_MODULE, .chnmask = 0 }, +#endif +}; + +static const struct rt_adc_ops nu_adc_ops = +{ + nu_eadc_enabled, + nu_get_eadc_value, +}; +typedef struct rt_adc_ops *rt_adc_ops_t; + + +/* nu_adc_enabled - Enable ADC clock and wait for ready */ +static rt_err_t nu_eadc_enabled(struct rt_adc_device *device, rt_uint32_t channel, rt_bool_t enabled) +{ + nu_eadc_t psNuEadc = (nu_eadc_t)device; + RT_ASSERT(device != RT_NULL); + + if (channel >= DEF_EADC_MAX_CHANNEL_NUM) + return -(RT_EINVAL); + + if (enabled) + { + if (psNuEadc->chnmask == 0) + { + /* Invoke Open function at first call. */ + EADC_Open(psNuEadc->base, EADC_CTL_DIFFEN_SINGLE_END); + } + psNuEadc->chnmask |= (1 << channel); + } + else + { + psNuEadc->chnmask &= ~(1 << channel); + + if (psNuEadc->chnmask == 0) + { + /* Invoke Open function at last call. */ + EADC_Close(psNuEadc->base); + } + } + + return RT_EOK; +} + +static rt_err_t nu_get_eadc_value(struct rt_adc_device *device, rt_uint32_t channel, rt_uint32_t *value) +{ + nu_eadc_t psNuEadc = (nu_eadc_t)device; + + RT_ASSERT(device != RT_NULL); + RT_ASSERT(value != RT_NULL); + + if (channel >= DEF_EADC_MAX_CHANNEL_NUM) + { + *value = 0xFFFFFFFF; + return -(RT_EINVAL); + } + + if ((psNuEadc->chnmask & (1 << channel)) == 0) + { + *value = 0xFFFFFFFF; + return -(RT_EBUSY); + } + + EADC_ConfigSampleModule(psNuEadc->base, 0, EADC_SOFTWARE_TRIGGER, channel); + + EADC_CLR_INT_FLAG(psNuEadc->base, EADC_STATUS2_ADIF0_Msk); + + EADC_ENABLE_INT(psNuEadc->base, BIT0); + + EADC_ENABLE_SAMPLE_MODULE_INT(psNuEadc->base, 0, BIT0); + + EADC_START_CONV(psNuEadc->base, BIT0); + + while (EADC_GET_INT_FLAG(psNuEadc->base, BIT0) == 0); + + *value = EADC_GET_CONV_DATA(psNuEadc->base, 0); + + return RT_EOK; +} + +int rt_hw_eadc_init(void) +{ + int i; + rt_err_t ret = RT_EOK; + + for (i = (EADC_START + 1); i < EADC_CNT; i++) + { + CLK_EnableModuleClock(nu_eadc_arr[i].modid); + SYS_ResetModule(nu_eadc_arr[i].rstidx); + + ret = rt_hw_adc_register(&nu_eadc_arr[i].parent, nu_eadc_arr[i].name, &nu_adc_ops, &nu_eadc_arr[i]); + RT_ASSERT(ret == RT_EOK); + } + + return (int)ret; +} +INIT_BOARD_EXPORT(rt_hw_eadc_init); + +#endif //#if defined(BSP_USING_EADC) diff --git a/bsp/nuvoton/libraries/ma35/rtt_port/drv_ecap.c b/bsp/nuvoton/libraries/ma35/rtt_port/drv_ecap.c new file mode 100644 index 0000000000..c5729cadc4 --- /dev/null +++ b/bsp/nuvoton/libraries/ma35/rtt_port/drv_ecap.c @@ -0,0 +1,287 @@ +/**************************************************************************//** +* +* @copyright (C) 2020 Nuvoton Technology Corp. All rights reserved. +* +* SPDX-License-Identifier: Apache-2.0 +* +* Change Logs: +* Date Author Notes +* 2021-10-7 Wayne First version +* +******************************************************************************/ +#include + +#if defined(BSP_USING_ECAP) + +#include +#include "drv_sys.h" +#include "drv_common.h" +#include "nu_bitutil.h" + +#define ECAP_CHANNEL_NUM 0x3 +#define ECAP_CHANNEL_MSK ((1<CTL1 = ((ecap)->CTL1 & ECAP_CTL1_CLKSEL_Msk)>>ECAP_CTL1_CLKSEL_Pos) + +/* Public functions -------------------------------------------------------------*/ + + +/* Private variables ------------------------------------------------------------*/ +static struct nu_ecap nu_ecap_arr [] = +{ +#if defined(BSP_USING_ECAP0) + { .base = ECAP0, .name = "ecap0i0", .irqn = ECAP0_IRQn, .rstidx = ECAP0_RST, .modid = ECAP0_MODULE }, + { .base = ECAP0, .name = "ecap0i1", .irqn = ECAP0_IRQn, .rstidx = ECAP0_RST, .modid = ECAP0_MODULE }, + { .base = ECAP0, .name = "ecap0i2", .irqn = ECAP0_IRQn, .rstidx = ECAP0_RST, .modid = ECAP0_MODULE }, +#endif +#if defined(BSP_USING_ECAP1) + { .base = ECAP1, .name = "ecap1i0", .irqn = ECAP1_IRQn, .rstidx = ECAP1_RST, .modid = ECAP1_MODULE }, + { .base = ECAP1, .name = "ecap1i1", .irqn = ECAP1_IRQn, .rstidx = ECAP1_RST, .modid = ECAP1_MODULE }, + { .base = ECAP1, .name = "ecap1i2", .irqn = ECAP1_IRQn, .rstidx = ECAP1_RST, .modid = ECAP1_MODULE }, +#endif +#if defined(BSP_USING_ECAP2) + { .base = ECAP2, .name = "ecap2i0", .irqn = ECAP2_IRQn, .rstidx = ECAP1_RST, .modid = ECAP2_MODULE }, + { .base = ECAP2, .name = "ecap2i1", .irqn = ECAP2_IRQn, .rstidx = ECAP1_RST, .modid = ECAP2_MODULE }, + { .base = ECAP2, .name = "ecap2i2", .irqn = ECAP2_IRQn, .rstidx = ECAP1_RST, .modid = ECAP2_MODULE }, +#endif +}; + +static struct rt_inputcapture_ops nu_ecap_ops = +{ + .init = nu_ecap_init, + .open = nu_ecap_open, + .close = nu_ecap_close, + .get_pulsewidth = nu_ecap_get_pulsewidth, +}; + +/* Functions define ------------------------------------------------------------*/ +static void nu_ecap_isr(int vector, void *param) +{ + /* Get base address of uart register */ + rt_int32_t irqindex; + nu_ecap_t psNuEcap = (nu_ecap_t)param; + ECAP_T *base = psNuEcap->base; + + /* Get input Capture status */ + uint32_t u32Status = ECAP_GET_INT_STATUS(base); + uint32_t u32ChStatus = u32Status & ECAP_CHANNEL_MSK; + + /* Check input capture channel flag */ + /* Find index of pin is attached in pool. */ + while ((irqindex = nu_ctz(u32ChStatus)) < ECAP_CHANNEL_NUM) // Count Trailing Zeros ==> Find First One + { + if (u32Status & (ECAP_STATUS_CAPTF0_Msk << (psNuEcap->u8Channel))) + { + /* Clear input capture channel flag */ + ECAP_CLR_CAPTURE_FLAG(base, ECAP_STATUS_CAPTF0_Msk << (psNuEcap->u8Channel)); + + psNuEcap->input_data_level = NU_ECAP_GET_LEVEL(u32Status, psNuEcap->u8Channel); + + psNuEcap->u32CurrentCnt = ECAP_GET_CNT_HOLD_VALUE(base, psNuEcap->u8Channel); + + rt_hw_inputcapture_isr(&psNuEcap->parent, psNuEcap->input_data_level); + } + } +} + +static rt_err_t nu_ecap_get_pulsewidth(struct rt_inputcapture_device *inputcapture, rt_uint32_t *pulsewidth_us) +{ + rt_err_t ret = RT_EOK; + float fTempCnt; + nu_ecap_t psNuEcap = (nu_ecap_t) inputcapture; + + RT_ASSERT(inputcapture != RT_NULL); + + if (psNuEcap->bfirstData) + { + psNuEcap->bfirstData = RT_FALSE; + ret = RT_ERROR; + + return -(ret); + } + + if (psNuEcap->u32CurrentCnt > psNuEcap->u32LastCnt) + fTempCnt = psNuEcap->u32CurrentCnt - psNuEcap->u32LastCnt; + else /* Overrun case */ + fTempCnt = psNuEcap->u32CurrentCnt + ((0x1000000 - psNuEcap->u32LastCnt) + 1); + + *pulsewidth_us = (int)(fTempCnt * psNuEcap->fUsPerTick); + + psNuEcap->u32LastCnt = psNuEcap->u32CurrentCnt; + + return -(ret); +} + +static float get_ecap_tick_time_us(nu_ecap_t psNuEcap) +{ + uint8_t u8ClockDivider[8] = { 1, 4, 16, 32, 64, 96, 112, 128}; + + if (psNuEcap->base == ECAP0) + return ((float)1000000 / ((float)CLK_GetPCLK2Freq() / u8ClockDivider[(psNuEcap->base->CTL1 & ECAP_CTL1_CLKSEL_Msk) >> ECAP_CTL1_CLKSEL_Pos])); + else + return ((float)1000000 / ((float)CLK_GetPCLK1Freq() / u8ClockDivider[(psNuEcap->base->CTL1 & ECAP_CTL1_CLKSEL_Msk) >> ECAP_CTL1_CLKSEL_Pos])); +} + +static rt_err_t nu_ecap_init(struct rt_inputcapture_device *inputcapture) +{ + return RT_EOK; +} + +static rt_err_t nu_ecap_open(struct rt_inputcapture_device *inputcapture) +{ + rt_err_t ret = RT_EOK; + nu_ecap_t psNuEcap = (nu_ecap_t) inputcapture; + + RT_ASSERT(inputcapture != RT_NULL); + + psNuEcap->fUsPerTick = get_ecap_tick_time_us(psNuEcap); + + /* Enable ECAP Input Channel */ + ECAP_ENABLE_INPUT_CHANNEL(psNuEcap->base, 0x1 << (ECAP_CTL0_IC0EN_Pos + psNuEcap->u8Channel)); + + /* Input Channel interrupt enabled */ + ECAP_EnableINT(psNuEcap->base, 0x1 << (ECAP_CTL0_CAPIEN0_Pos + psNuEcap->u8Channel)); + + /* Enable interrupt. */ + if ((psNuEcap->base->CTL0 & (ECAP_CHANNEL_MSK << ECAP_CTL0_CAPIEN0_Pos)) != 0U) + rt_hw_interrupt_umask(psNuEcap->irqn); + + /* ECAP_CNT starts up-counting */ + ECAP_CNT_START(psNuEcap->base); + + return ret; +} + +static rt_err_t nu_ecap_close(struct rt_inputcapture_device *inputcapture) +{ + rt_err_t ret = RT_EOK; + + nu_ecap_t psNuEcap = (nu_ecap_t) inputcapture; + + RT_ASSERT(inputcapture != RT_NULL); + + /* Input Channel interrupt disabled */ + ECAP_DisableINT(psNuEcap->base, 0x1 << (ECAP_CTL0_CAPIEN0_Pos + psNuEcap->u8Channel)); + + /* Disable interrupt. */ + if ((psNuEcap->base->CTL0 & (ECAP_CHANNEL_MSK << ECAP_CTL0_CAPIEN0_Pos)) == 0U) + rt_hw_interrupt_mask(psNuEcap->irqn); + + /* Disable ECAP Input Channel */ + ECAP_DISABLE_INPUT_CHANNEL(psNuEcap->base, 0x1 << (ECAP_CTL0_IC0EN_Pos + psNuEcap->u8Channel)); + + /* Clear input capture channel flag */ + ECAP_CLR_CAPTURE_FLAG(psNuEcap->base, 0x1 << (ECAP_STATUS_CAPTF0_Pos + psNuEcap->u8Channel)); + + return ret; +} + +static void nu_ecap_channel_init(ECAP_T *base) +{ + /* Enable ECAP */ + ECAP_Open(base, ECAP_DISABLE_COMPARE); + + ECAP_SEL_TIMER_CLK_DIV(base, ECAP_CLK_DIV); + + /* Select Reload function */ + ECAP_SET_CNT_CLEAR_EVENT(base, ECAP_CTL1_OVRLDEN_Msk); + + /* Enable ECAP source IC */ + ECAP_SEL_INPUT_SRC(base, ECAP_IC0, ECAP_CAP_INPUT_SRC_FROM_IC); + ECAP_SEL_INPUT_SRC(base, ECAP_IC1, ECAP_CAP_INPUT_SRC_FROM_IC); + ECAP_SEL_INPUT_SRC(base, ECAP_IC2, ECAP_CAP_INPUT_SRC_FROM_IC); + + /* Select IC detect rising edge */ + ECAP_SEL_CAPTURE_EDGE(base, ECAP_IC0, ECAP_RISING_FALLING_EDGE); + ECAP_SEL_CAPTURE_EDGE(base, ECAP_IC1, ECAP_RISING_FALLING_EDGE); + ECAP_SEL_CAPTURE_EDGE(base, ECAP_IC2, ECAP_RISING_FALLING_EDGE); +} + +/* Init and register ecap capture */ +static int rt_hw_ecap_init(void) +{ + int i; + rt_err_t ret = RT_EOK; + + for (i = (ECAP_START + 1); i < ECAP_CNT; i++) + { + nu_ecap_t psNuEcap = &nu_ecap_arr[i]; + + psNuEcap->u8Channel = i % ECAP_CHANNEL_NUM; + psNuEcap->bfirstData = RT_TRUE; + psNuEcap->u32CurrentCnt = 0; + psNuEcap->u32LastCnt = 0; + psNuEcap->parent.ops = &nu_ecap_ops; + + if ((psNuEcap->u8Channel % ECAP_CHANNEL_NUM) == 0) + { + /* register ecap module */ + CLK_EnableModuleClock(psNuEcap->modid); + SYS_ResetModule(psNuEcap->rstidx); + + nu_ecap_channel_init(psNuEcap->base); + + /* register isr */ + rt_hw_interrupt_install(psNuEcap->irqn, nu_ecap_isr, psNuEcap, psNuEcap->name); + } + + /* register inputcapture device */ + ret = rt_device_inputcapture_register(&psNuEcap->parent, psNuEcap->name, psNuEcap); + RT_ASSERT(ret == RT_EOK); + } + + return 0; +} +INIT_DEVICE_EXPORT(rt_hw_ecap_init); + +#endif //#if defined(BSP_USING_ECAP) diff --git a/bsp/nuvoton/libraries/ma35/rtt_port/drv_epwm.c b/bsp/nuvoton/libraries/ma35/rtt_port/drv_epwm.c new file mode 100644 index 0000000000..40fb503e83 --- /dev/null +++ b/bsp/nuvoton/libraries/ma35/rtt_port/drv_epwm.c @@ -0,0 +1,210 @@ +/**************************************************************************//** +* +* @copyright (C) 2020 Nuvoton Technology Corp. All rights reserved. +* +* SPDX-License-Identifier: Apache-2.0 +* +* Change Logs: +* Date Author Notes +* 2021-9-22 Wayne First version +* +******************************************************************************/ + +#include + +#if (defined(BSP_USING_EPWM) && defined(RT_USING_PWM)) + +#define LOG_TAG "drv.epwm" +#define DBG_ENABLE +#define DBG_SECTION_NAME LOG_TAG +#define DBG_LEVEL DBG_INFO +#define DBG_COLOR +#include + +#include +#include +#include "NuMicro.h" + +enum +{ + EPWM_START = -1, +#if defined(BSP_USING_EPWM0_PWM) + EPWM0_IDX, +#endif +#if defined(BSP_USING_EPWM1_PWM) + EPWM1_IDX, +#endif +#if defined(BSP_USING_EPWM2_PWM) + EPWM2_IDX, +#endif + EPWM_CNT +}; + +struct nu_epwm +{ + struct rt_device_pwm dev; + char *name; + EPWM_T *base; + uint32_t rstidx; + uint32_t modid; +}; + +typedef struct nu_epwm *nu_epwm_t; + +static struct nu_epwm nu_epwm_arr [] = +{ +#if defined(BSP_USING_EPWM0_PWM) + { .name = "epwm0", .base = EPWM0, .rstidx = EPWM0_RST, .modid = EPWM0_MODULE }, +#endif + +#if defined(BSP_USING_EPWM1_PWM) + { .name = "epwm1", .base = EPWM1, .rstidx = EPWM1_RST, .modid = EPWM1_MODULE }, +#endif + +#if defined(BSP_USING_EPWM2_PWM) + { .name = "epwm2", .base = EPWM2, .rstidx = EPWM2_RST, .modid = EPWM2_MODULE }, +#endif + +}; /* epwm nu_epwm */ + +static rt_err_t nu_epwm_control(struct rt_device_pwm *device, int cmd, void *arg); + +static struct rt_pwm_ops nu_epwm_ops = +{ + .control = nu_epwm_control +}; + +static rt_err_t nu_epwm_enable(struct rt_device_pwm *device, struct rt_pwm_configuration *configuration, rt_bool_t enable) +{ + rt_err_t result = RT_EOK; + + EPWM_T *pwm_base = ((nu_epwm_t)device)->base; + rt_uint32_t pwm_channel = ((struct rt_pwm_configuration *)configuration)->channel; + + if (enable == RT_TRUE) + { + EPWM_EnableOutput(pwm_base, 1 << pwm_channel); + EPWM_Start(pwm_base, 1 << pwm_channel); + } + else + { + EPWM_DisableOutput(pwm_base, 1 << pwm_channel); + EPWM_ForceStop(pwm_base, 1 << pwm_channel); + } + + return result; +} + +static rt_err_t nu_epwm_set(struct rt_device_pwm *device, struct rt_pwm_configuration *configuration) +{ + if ((((struct rt_pwm_configuration *)configuration)->period) <= 0) + return -(RT_ERROR); + + rt_uint8_t pwm_channel_pair; + rt_uint32_t pwm_freq, pwm_dutycycle ; + EPWM_T *pwm_base = ((nu_epwm_t)device)->base; + rt_uint8_t pwm_channel = ((struct rt_pwm_configuration *)configuration)->channel; + rt_uint32_t pwm_period = ((struct rt_pwm_configuration *)configuration)->period; + rt_uint32_t pwm_pulse = ((struct rt_pwm_configuration *)configuration)->pulse; + rt_uint32_t pre_pwm_prescaler = EPWM_GET_PRESCALER(pwm_base, pwm_channel); + + if ((pwm_channel % 2) == 0) + pwm_channel_pair = pwm_channel + 1; + else + pwm_channel_pair = pwm_channel - 1; + + pwm_freq = (uint64_t)1000000000 / pwm_period; + pwm_dutycycle = (pwm_pulse * 100) / pwm_period; + + EPWM_ConfigOutputChannel(pwm_base, pwm_channel, pwm_freq, pwm_dutycycle) ; + + if ((pre_pwm_prescaler != 0) || (EPWM_GET_CNR(pwm_base, pwm_channel_pair) != 0) || (EPWM_GET_CMR(pwm_base, pwm_channel_pair) != 0)) + { + if (pre_pwm_prescaler < EPWM_GET_PRESCALER(pwm_base, pwm_channel)) + { + EPWM_SET_CNR(pwm_base, pwm_channel_pair, ((EPWM_GET_CNR(pwm_base, pwm_channel_pair) + 1) * (pre_pwm_prescaler + 1)) / (EPWM_GET_PRESCALER(pwm_base, pwm_channel) + 1)); + EPWM_SET_CMR(pwm_base, pwm_channel_pair, (EPWM_GET_CMR(pwm_base, pwm_channel_pair) * (pre_pwm_prescaler + 1)) / (EPWM_GET_PRESCALER(pwm_base, pwm_channel) + 1)); + } + else if (pre_pwm_prescaler > EPWM_GET_PRESCALER(pwm_base, pwm_channel)) + { + EPWM_SET_CNR(pwm_base, pwm_channel, ((EPWM_GET_CNR(pwm_base, pwm_channel) + 1) * (EPWM_GET_PRESCALER(pwm_base, pwm_channel) + 1)) / (pre_pwm_prescaler + 1)); + EPWM_SET_CMR(pwm_base, pwm_channel, (EPWM_GET_CMR(pwm_base, pwm_channel) * (EPWM_GET_PRESCALER(pwm_base, pwm_channel) + 1)) / (pre_pwm_prescaler + 1)); + } + } + return RT_EOK; +} + +static rt_uint32_t nu_epwm_clksr(struct rt_device_pwm *device) +{ + return CLK_GetPCLK0Freq(); //Both PCLK0 && PCLK1 are the same. +} + +static rt_err_t nu_epwm_get(struct rt_device_pwm *device, struct rt_pwm_configuration *configuration) +{ + rt_uint32_t pwm_real_period, pwm_real_duty, time_tick, u32EPWMClockSrc ; + + EPWM_T *pwm_base = ((nu_epwm_t)device)->base; + rt_uint32_t pwm_channel = ((struct rt_pwm_configuration *)configuration)->channel; + rt_uint32_t pwm_prescale = EPWM_GET_PRESCALER(pwm_base, pwm_channel); + rt_uint32_t pwm_period = EPWM_GET_CNR(pwm_base, pwm_channel); + rt_uint32_t pwm_pulse = EPWM_GET_CMR(pwm_base, pwm_channel); + + u32EPWMClockSrc = nu_epwm_clksr(device); + time_tick = (uint64_t)1000000000000 / u32EPWMClockSrc; + + pwm_real_period = (((pwm_prescale + 1) * (pwm_period + 1)) * time_tick) / 1000; + pwm_real_duty = (((pwm_prescale + 1) * pwm_pulse * time_tick)) / 1000; + ((struct rt_pwm_configuration *)configuration)->period = pwm_real_period; + ((struct rt_pwm_configuration *)configuration)->pulse = pwm_real_duty; + + LOG_I("%s %d %d %d\n", ((nu_epwm_t)device)->name, configuration->channel, configuration->period, configuration->pulse); + + return RT_EOK; +} + +static rt_err_t nu_epwm_control(struct rt_device_pwm *device, int cmd, void *arg) +{ + struct rt_pwm_configuration *configuration = (struct rt_pwm_configuration *)arg; + + RT_ASSERT(device != RT_NULL); + RT_ASSERT(configuration != RT_NULL); + + if (((((struct rt_pwm_configuration *)configuration)->channel) + 1) > EPWM_CHANNEL_NUM) + return -(RT_ERROR); + + switch (cmd) + { + case PWM_CMD_ENABLE: + return nu_epwm_enable(device, configuration, RT_TRUE); + case PWM_CMD_DISABLE: + return nu_epwm_enable(device, configuration, RT_FALSE); + case PWM_CMD_SET: + return nu_epwm_set(device, configuration); + case PWM_CMD_GET: + return nu_epwm_get(device, configuration); + } + return -(RT_EINVAL); +} + +int rt_hw_epwm_init(void) +{ + rt_err_t ret; + int i; + + for (i = (EPWM_START + 1); i < EPWM_CNT; i++) + { + + CLK_EnableModuleClock(nu_epwm_arr[i].modid); + + SYS_ResetModule(nu_epwm_arr[i].rstidx); + + ret = rt_device_pwm_register(&nu_epwm_arr[i].dev, nu_epwm_arr[i].name, &nu_epwm_ops, &nu_epwm_arr[i]); + RT_ASSERT(ret == RT_EOK); + } + + return 0; +} + +INIT_DEVICE_EXPORT(rt_hw_epwm_init); + +#endif diff --git a/bsp/nuvoton/libraries/ma35/rtt_port/drv_epwm_capture.c b/bsp/nuvoton/libraries/ma35/rtt_port/drv_epwm_capture.c new file mode 100644 index 0000000000..4e97fe5e03 --- /dev/null +++ b/bsp/nuvoton/libraries/ma35/rtt_port/drv_epwm_capture.c @@ -0,0 +1,289 @@ +/**************************************************************************//** +* +* @copyright (C) 2020 Nuvoton Technology Corp. All rights reserved. +* +* SPDX-License-Identifier: Apache-2.0 +* +* Change Logs: +* Date Author Notes +* 2021-10-19 Wayne First version +* +******************************************************************************/ +#include + +#if defined(BSP_USING_EPWM_CAPTURE) + +#include +#include "drv_sys.h" +#include "drv_common.h" + +/* Private typedef --------------------------------------------------------------*/ +enum +{ + EPWM_START = -1, +#if defined(BSP_USING_EPWM0_CAPTURE) + EPWM0I0_IDX, + EPWM0I1_IDX, + EPWM0I2_IDX, + EPWM0I3_IDX, + EPWM0I4_IDX, + EPWM0I5_IDX, +#endif +#if defined(BSP_USING_EPWM1_CAPTURE) + EPWM1I0_IDX, + EPWM1I1_IDX, + EPWM1I2_IDX, + EPWM1I3_IDX, + EPWM1I4_IDX, + EPWM1I5_IDX, +#endif +#if defined(BSP_USING_EPWM2_CAPTURE) + EPWM2I0_IDX, + EPWM2I1_IDX, + EPWM2I2_IDX, + EPWM2I3_IDX, + EPWM2I4_IDX, + EPWM2I5_IDX, +#endif + EPWM_CNT +}; + +struct nu_epwmcap +{ + struct rt_inputcapture_device parent; + EPWM_T *base; + char *name; + IRQn_Type irqn; + uint32_t rstidx; + uint32_t modid; + + uint8_t u8Channel; + uint32_t u32CurrentRisingCnt; + uint32_t u32CurrentFallingCnt; + rt_bool_t input_data_level; +}; +typedef struct nu_epwmcap *nu_epwmcap_t; + +/* Private functions ------------------------------------------------------------*/ +static rt_err_t nu_epwmcap_init(struct rt_inputcapture_device *inputcapture); +static rt_err_t nu_epwmcap_open(struct rt_inputcapture_device *inputcapture); +static rt_err_t nu_epwmcap_close(struct rt_inputcapture_device *inputcapture); +static rt_err_t nu_epwmcap_get_pulsewidth(struct rt_inputcapture_device *inputcapture, rt_uint32_t *pulsewidth_us); + +/* Public functions -------------------------------------------------------------*/ + + +/* Private variables ------------------------------------------------------------*/ +static struct nu_epwmcap nu_epwmcap_arr [] = +{ +#if defined(BSP_USING_EPWM0_CAPTURE) + { .base = EPWM0, .name = "epwm0i0", .irqn = EPWM0P0_IRQn, .rstidx = EPWM0_RST, .modid = EPWM0_MODULE }, + { .base = EPWM0, .name = "epwm0i1", .irqn = EPWM0P0_IRQn, .rstidx = EPWM0_RST, .modid = EPWM0_MODULE }, + { .base = EPWM0, .name = "epwm0i2", .irqn = EPWM0P1_IRQn, .rstidx = EPWM0_RST, .modid = EPWM0_MODULE }, + { .base = EPWM0, .name = "epwm0i3", .irqn = EPWM0P1_IRQn, .rstidx = EPWM0_RST, .modid = EPWM0_MODULE }, + { .base = EPWM0, .name = "epwm0i4", .irqn = EPWM0P2_IRQn, .rstidx = EPWM0_RST, .modid = EPWM0_MODULE }, + { .base = EPWM0, .name = "epwm0i5", .irqn = EPWM0P2_IRQn, .rstidx = EPWM0_RST, .modid = EPWM0_MODULE }, +#endif +#if defined(BSP_USING_EPWM1_CAPTURE) + { .base = EPWM1, .name = "epwm1i0", .irqn = EPWM1P0_IRQn, .rstidx = EPWM1_RST, .modid = EPWM1_MODULE }, + { .base = EPWM1, .name = "epwm1i1", .irqn = EPWM1P0_IRQn, .rstidx = EPWM1_RST, .modid = EPWM1_MODULE }, + { .base = EPWM1, .name = "epwm1i2", .irqn = EPWM1P1_IRQn, .rstidx = EPWM1_RST, .modid = EPWM1_MODULE }, + { .base = EPWM1, .name = "epwm1i3", .irqn = EPWM1P1_IRQn, .rstidx = EPWM1_RST, .modid = EPWM1_MODULE }, + { .base = EPWM1, .name = "epwm1i4", .irqn = EPWM1P2_IRQn, .rstidx = EPWM1_RST, .modid = EPWM1_MODULE }, + { .base = EPWM1, .name = "epwm1i5", .irqn = EPWM1P2_IRQn, .rstidx = EPWM1_RST, .modid = EPWM1_MODULE }, +#endif +#if defined(BSP_USING_EPWM2_CAPTURE) + { .base = EPWM2, .name = "epwm2i0", .irqn = EPWM2P0_IRQn, .rstidx = EPWM2_RST, .modid = EPWM2_MODULE }, + { .base = EPWM2, .name = "epwm2i1", .irqn = EPWM2P0_IRQn, .rstidx = EPWM2_RST, .modid = EPWM2_MODULE }, + { .base = EPWM2, .name = "epwm2i2", .irqn = EPWM2P1_IRQn, .rstidx = EPWM2_RST, .modid = EPWM2_MODULE }, + { .base = EPWM2, .name = "epwm2i3", .irqn = EPWM2P1_IRQn, .rstidx = EPWM2_RST, .modid = EPWM2_MODULE }, + { .base = EPWM2, .name = "epwm2i4", .irqn = EPWM2P2_IRQn, .rstidx = EPWM2_RST, .modid = EPWM2_MODULE }, + { .base = EPWM2, .name = "epwm2i5", .irqn = EPWM2P2_IRQn, .rstidx = EPWM2_RST, .modid = EPWM2_MODULE }, +#endif +}; + +static struct rt_inputcapture_ops nu_epwmcap_ops = +{ + .init = nu_epwmcap_init, + .open = nu_epwmcap_open, + .close = nu_epwmcap_close, + .get_pulsewidth = nu_epwmcap_get_pulsewidth, +}; + +/* Functions define ------------------------------------------------------------*/ +static rt_err_t CalPulseWidth(nu_epwmcap_t psNuEpwmCap) +{ + rt_bool_t bWrapAroundFlag = RT_FALSE; + + /* Check rising/falling capture counter is overflow or not */ + if (EPWM_GetWrapAroundFlag(psNuEpwmCap->base, psNuEpwmCap->u8Channel)) + { + EPWM_ClearWrapAroundFlag(psNuEpwmCap->base, psNuEpwmCap->u8Channel); + bWrapAroundFlag = RT_TRUE; + } + + /* Read the capture counter value if falling/rising edge */ + if (EPWM_GetCaptureIntFlag(psNuEpwmCap->base, psNuEpwmCap->u8Channel) == 1)//Rising edge + { + EPWM_ClearCaptureIntFlag(psNuEpwmCap->base, psNuEpwmCap->u8Channel, EPWM_CAPTURE_INT_RISING_LATCH); + + if (bWrapAroundFlag) + { + psNuEpwmCap->u32CurrentRisingCnt = 0x10000; + } + psNuEpwmCap->u32CurrentRisingCnt += EPWM_GET_CAPTURE_RISING_DATA(psNuEpwmCap->base, psNuEpwmCap->u8Channel); + } + else if (EPWM_GetCaptureIntFlag(psNuEpwmCap->base, psNuEpwmCap->u8Channel) == 2)//Falling edge + { + EPWM_ClearCaptureIntFlag(psNuEpwmCap->base, psNuEpwmCap->u8Channel, EPWM_CAPTURE_INT_FALLING_LATCH); + + if (bWrapAroundFlag) + { + psNuEpwmCap->u32CurrentFallingCnt = 0x10000; + } + psNuEpwmCap->u32CurrentFallingCnt += EPWM_GET_CAPTURE_FALLING_DATA(psNuEpwmCap->base, psNuEpwmCap->u8Channel); + } + else //Rising & Falling edge + { + EPWM_ClearCaptureIntFlag(psNuEpwmCap->base, psNuEpwmCap->u8Channel, EPWM_CAPTURE_INT_RISING_LATCH); + EPWM_ClearCaptureIntFlag(psNuEpwmCap->base, psNuEpwmCap->u8Channel, EPWM_CAPTURE_INT_FALLING_LATCH); + + return -(RT_ERROR); + } + + return RT_EOK; +} + +static void nu_epwmcap_isr(int vector, void *param) +{ + nu_epwmcap_t psNuEpwmCap = (nu_epwmcap_t)param; + + if (EPWM_GetCaptureIntFlag(psNuEpwmCap->base, psNuEpwmCap->u8Channel) != 0) + { + /* Calculate pulse width */ + if (CalPulseWidth(psNuEpwmCap) == RT_EOK) + { + rt_hw_inputcapture_isr(&psNuEpwmCap->parent, psNuEpwmCap->input_data_level); + } + } +} + +static rt_err_t nu_epwmcap_get_pulsewidth(struct rt_inputcapture_device *inputcapture, rt_uint32_t *pulsewidth_us) +{ + rt_err_t ret = RT_EOK; + nu_epwmcap_t psNuEpwmCap = (nu_epwmcap_t)inputcapture; + + RT_ASSERT(psNuEpwmCap != RT_NULL); + + if (psNuEpwmCap->u32CurrentFallingCnt) + { + *pulsewidth_us = psNuEpwmCap->u32CurrentFallingCnt; + psNuEpwmCap->input_data_level = RT_FALSE; + psNuEpwmCap->u32CurrentFallingCnt = 0; + } + else if (psNuEpwmCap->u32CurrentRisingCnt) + { + *pulsewidth_us = psNuEpwmCap->u32CurrentRisingCnt; + psNuEpwmCap->input_data_level = RT_TRUE; + psNuEpwmCap->u32CurrentRisingCnt = 0; + } + else + { + ret = RT_ERROR; + } + return -(ret); +} + +static rt_err_t nu_epwmcap_init(struct rt_inputcapture_device *inputcapture) +{ + return RT_EOK; +} + +static rt_err_t nu_epwmcap_open(struct rt_inputcapture_device *inputcapture) +{ + rt_err_t ret = RT_EOK; + nu_epwmcap_t psNuEpwmCap = (nu_epwmcap_t) inputcapture; + + RT_ASSERT(psNuEpwmCap != RT_NULL); + + /* Set capture time as 1000 nanosecond */ + EPWM_ConfigCaptureChannel(psNuEpwmCap->base, psNuEpwmCap->u8Channel, 1000, 0); + + /* Enable capture rising/falling edge interrupt */ + EPWM_EnableCaptureInt(psNuEpwmCap->base, psNuEpwmCap->u8Channel, EPWM_CAPTURE_INT_FALLING_LATCH | EPWM_CAPTURE_INT_RISING_LATCH); + + /* Enable Capture Function for EPWM */ + EPWM_EnableCapture(psNuEpwmCap->base, 0x1 << psNuEpwmCap->u8Channel); + + /* Enable rising/falling capture reload */ + psNuEpwmCap->base->CAPCTL |= (0x1 << (EPWM_CAPCTL_RCRLDEN0_Pos + psNuEpwmCap->u8Channel)) + | (0x1 << (EPWM_CAPCTL_FCRLDEN0_Pos + psNuEpwmCap->u8Channel)); + + /* Set counter type as down count */ + EPWM_SET_ALIGNED_TYPE(psNuEpwmCap->base, 0x1 << psNuEpwmCap->u8Channel, EPWM_UP_COUNTER); + + /* Enable EPWM Timer */ + EPWM_Start(psNuEpwmCap->base, 0x1 << psNuEpwmCap->u8Channel); + + /* Enable EPWMxPx interrupt. */ + rt_hw_interrupt_umask(psNuEpwmCap->irqn); + + return ret; +} + +static rt_err_t nu_epwmcap_close(struct rt_inputcapture_device *inputcapture) +{ + rt_err_t ret = RT_EOK; + + nu_epwmcap_t psNuEpwmCap = (nu_epwmcap_t) inputcapture; + + RT_ASSERT(psNuEpwmCap != RT_NULL); + + /* Disable capture rising/falling edge interrupt */ + EPWM_DisableCaptureInt(psNuEpwmCap->base, psNuEpwmCap->u8Channel, EPWM_CAPTURE_INT_FALLING_LATCH | EPWM_CAPTURE_INT_RISING_LATCH); + + /* Stop EPWM Timer */ + EPWM_ForceStop(psNuEpwmCap->base, 0x1 << psNuEpwmCap->u8Channel); + + /* Disable EPWMxPx interrupt */ + if ((psNuEpwmCap->base->CNTEN & (0x3 << (psNuEpwmCap->u8Channel / 2 * 2))) == 0u) + rt_hw_interrupt_mask(psNuEpwmCap->irqn); + + return ret; +} + +/* Init and register epwm capture */ +int rt_hw_epwmcap_init(void) +{ + int i; + rt_err_t ret = RT_EOK; + + for (i = (EPWM_START + 1); i < EPWM_CNT; i++) + { + nu_epwmcap_t psNuEpwmCap = &nu_epwmcap_arr[i]; + + psNuEpwmCap->u8Channel = i % EPWM_CHANNEL_NUM; + psNuEpwmCap->u32CurrentRisingCnt = 0; + psNuEpwmCap->u32CurrentFallingCnt = 0; + psNuEpwmCap->parent.ops = &nu_epwmcap_ops; + + if ((psNuEpwmCap->u8Channel % EPWM_CHANNEL_NUM) == 0) + { + /* Enable epwm module */ + CLK_EnableModuleClock(psNuEpwmCap->modid); + SYS_ResetModule(psNuEpwmCap->rstidx); + + /* register isr */ + rt_hw_interrupt_install(psNuEpwmCap->irqn, nu_epwmcap_isr, psNuEpwmCap, psNuEpwmCap->name); + } + + /* register inputcapture device */ + ret = rt_device_inputcapture_register(&psNuEpwmCap->parent, psNuEpwmCap->name, psNuEpwmCap); + RT_ASSERT(ret == RT_EOK); + } + + return 0; +} +INIT_DEVICE_EXPORT(rt_hw_epwmcap_init); + +#endif //#if defined(BSP_USING_EPWM_CAPTURE) diff --git a/bsp/nuvoton/libraries/ma35/rtt_port/drv_gpio.c b/bsp/nuvoton/libraries/ma35/rtt_port/drv_gpio.c new file mode 100644 index 0000000000..0a7a75ee9b --- /dev/null +++ b/bsp/nuvoton/libraries/ma35/rtt_port/drv_gpio.c @@ -0,0 +1,341 @@ +/**************************************************************************//** +* +* @copyright (C) 2020 Nuvoton Technology Corp. All rights reserved. +* +* SPDX-License-Identifier: Apache-2.0 +* +* Change Logs: +* Date Author Notes +* 2021-07-23 Wayne First version +* +******************************************************************************/ + +#include + +#if (defined(BSP_USING_GPIO) && defined(RT_USING_PIN)) + +#include +#include +#include "drv_common.h" +#include +#include "nu_bitutil.h" +#include "stdlib.h" + +/* Private define ---------------------------------------------------------------*/ + +#define PORT_OFFSET 0x40 +#define IRQ_MAX_NUM 16 //Max support 32 + +/* Private functions ------------------------------------------------------------*/ + +static void nu_gpio_mode(struct rt_device *device, rt_base_t pin, rt_base_t mode); +static void nu_gpio_write(struct rt_device *device, rt_base_t pin, rt_base_t value); +static int nu_gpio_read(struct rt_device *device, rt_base_t pin); +static rt_err_t nu_gpio_attach_irq(struct rt_device *device, rt_int32_t pin, rt_uint32_t mode, void (*hdr)(void *args), void *args); +static rt_err_t nu_gpio_detach_irq(struct rt_device *device, rt_int32_t pin); +static rt_err_t nu_gpio_irq_enable(struct rt_device *device, rt_base_t pin, rt_uint32_t enabled); +static rt_base_t nu_gpio_pin_get(const char *name); + +/* Private variables ------------------------------------------------------------*/ +static struct rt_pin_irq_hdr pin_irq_hdr_tab[IRQ_MAX_NUM]; +static struct rt_pin_ops nu_gpio_ops = +{ + nu_gpio_mode, + nu_gpio_write, + nu_gpio_read, + nu_gpio_attach_irq, + nu_gpio_detach_irq, + nu_gpio_irq_enable, + nu_gpio_pin_get, +}; + +static IRQn_Type au32GPIRQ[NU_PORT_CNT] = {GPA_IRQn, GPB_IRQn, GPC_IRQn, GPD_IRQn, GPE_IRQn, GPF_IRQn, GPG_IRQn, GPH_IRQn, GPI_IRQn, GPJ_IRQn, GPK_IRQn, GPL_IRQn, GPM_IRQn, GPN_IRQn}; + +static rt_uint32_t g_u32PinIrqMask = 0x0; + +/* Functions define ------------------------------------------------------------*/ + +static rt_err_t nu_port_check(rt_int32_t pin) +{ + if (NU_GET_PORT(pin) >= NU_PORT_CNT) + return -(RT_ERROR); + + return RT_EOK; +} + +static rt_int32_t nu_find_irqindex(rt_uint32_t pin_index) +{ + rt_int32_t irqindex; + rt_int32_t u32PinIrqStatus = g_u32PinIrqMask; + + // Find index of pin is attached in pool. + while ((irqindex = nu_ctz(u32PinIrqStatus)) < IRQ_MAX_NUM) // Count Trailing Zeros ==> Find First One + { + if (pin_irq_hdr_tab[irqindex].pin == pin_index) + return irqindex; + + u32PinIrqStatus &= ~(1 << irqindex); + } + + return -(RT_ERROR); +} + +static void pin_irq_hdr(rt_uint32_t irq_status, rt_uint32_t port_index) +{ + rt_int32_t irqindex, i; + rt_int32_t pinindex = port_index * GPIO_PIN_MAX ; + + while ((i = nu_ctz(irq_status)) < GPIO_PIN_MAX)// Count Trailing Zeros ==> Find First One + { + int pin_mask = (1 << i); + irqindex = nu_find_irqindex(pinindex + i); + if (irqindex != -(RT_ERROR)) + { + if (pin_irq_hdr_tab[irqindex].hdr) + { + pin_irq_hdr_tab[irqindex].hdr(pin_irq_hdr_tab[irqindex].args); + } + } + // Clear the served bit. + irq_status &= ~pin_mask; + } +} + +static rt_base_t nu_gpio_pin_get(const char *name) +{ + /* Get pin number by name,such as PA.0, PF12 */ + if ((name[2] == '\0') || ((name[2] == '.') && (name[3] == '\0'))) + return -(RT_EINVAL); + + long number; + + if ((name[2] == '.')) + number = atol(&name[3]); + else + number = atol(&name[2]); + + if (number > 15) + return -(RT_EINVAL); + + if (name[1] >= 'A' && name[1] <= 'N') + return ((name[1] - 'A') * 0x10) + number; + + if (name[1] >= 'a' && name[1] <= 'n') + return ((name[1] - 'a') * 0x10) + number; + + return -(RT_EINVAL); +} + +static void nu_gpio_mode(struct rt_device *device, rt_base_t pin, rt_base_t mode) +{ + GPIO_T *PORT; + + if (nu_port_check(pin)) + return; + + PORT = (GPIO_T *)(GPIOA_BASE + (NU_GET_PORT(pin) * PORT_OFFSET)); + + if (mode == PIN_MODE_INPUT_PULLUP) + { + GPIO_SetMode(PORT, NU_GET_PIN_MASK(NU_GET_PINS(pin)), GPIO_MODE_INPUT); + GPIO_SetPullCtl(PORT, NU_GET_PIN_MASK(NU_GET_PINS(pin)), GPIO_PUSEL_PULL_UP); + } + else if (mode == PIN_MODE_INPUT_PULLDOWN) + { + GPIO_SetMode(PORT, NU_GET_PIN_MASK(NU_GET_PINS(pin)), GPIO_MODE_INPUT); + GPIO_SetPullCtl(PORT, NU_GET_PIN_MASK(NU_GET_PINS(pin)), GPIO_PUSEL_PULL_DOWN); + } + else if (mode == PIN_MODE_OUTPUT) + { + GPIO_SetMode(PORT, NU_GET_PIN_MASK(NU_GET_PINS(pin)), GPIO_MODE_OUTPUT); + } + else if (mode == PIN_MODE_INPUT) + { + GPIO_SetMode(PORT, NU_GET_PIN_MASK(NU_GET_PINS(pin)), GPIO_MODE_INPUT); + GPIO_SetPullCtl(PORT, NU_GET_PIN_MASK(NU_GET_PINS(pin)), GPIO_PUSEL_DISABLE); + } + else if (mode == PIN_MODE_OUTPUT_OD) + { + GPIO_SetMode(PORT, NU_GET_PIN_MASK(NU_GET_PINS(pin)), GPIO_MODE_OPEN_DRAIN); + GPIO_SetPullCtl(PORT, NU_GET_PIN_MASK(NU_GET_PINS(pin)), GPIO_PUSEL_DISABLE); + } +} + +static void nu_gpio_write(struct rt_device *device, rt_base_t pin, rt_base_t value) +{ + if (nu_port_check(pin)) + return; + + GPIO_PIN_DATA(NU_GET_PORT(pin), NU_GET_PINS(pin)) = value; +} + +static int nu_gpio_read(struct rt_device *device, rt_base_t pin) +{ + if (nu_port_check(pin)) + return PIN_LOW; + + return GPIO_PIN_DATA(NU_GET_PORT(pin), NU_GET_PINS(pin)); +} + +static rt_err_t nu_gpio_attach_irq(struct rt_device *device, rt_int32_t pin, rt_uint32_t mode, void (*hdr)(void *args), void *args) +{ + rt_base_t level; + rt_int32_t irqindex; + + if (nu_port_check(pin)) + return -(RT_ERROR); + + level = rt_hw_interrupt_disable(); + + // Find index of pin is attached in pool. + if ((irqindex = nu_find_irqindex(pin)) >= 0) + goto exit_nu_gpio_attach_irq; + + // Find available index of pin in pool. + if ((irqindex = nu_cto(g_u32PinIrqMask)) < IRQ_MAX_NUM) // Count Trailing Ones ==> Find First Zero + goto exit_nu_gpio_attach_irq; + + rt_hw_interrupt_enable(level); + + return -(RT_EBUSY); + +exit_nu_gpio_attach_irq: + + pin_irq_hdr_tab[irqindex].pin = pin; + pin_irq_hdr_tab[irqindex].hdr = hdr; + pin_irq_hdr_tab[irqindex].mode = mode; + pin_irq_hdr_tab[irqindex].args = args; + + g_u32PinIrqMask |= (1 << irqindex); + rt_hw_interrupt_enable(level); + + return RT_EOK; +} + +static rt_err_t nu_gpio_detach_irq(struct rt_device *device, rt_int32_t pin) +{ + rt_base_t level; + rt_int32_t irqindex; + rt_int32_t u32PinIrqStatus; + + if (nu_port_check(pin)) + return -(RT_ERROR); + + level = rt_hw_interrupt_disable(); + + u32PinIrqStatus = g_u32PinIrqMask; + + // Find index of pin is attached in pool. + while ((irqindex = nu_ctz(u32PinIrqStatus)) < IRQ_MAX_NUM)// Count Trailing Zeros ==> Find First One + { + if (pin_irq_hdr_tab[irqindex].pin == pin) + { + pin_irq_hdr_tab[irqindex].pin = PIN_IRQ_PIN_NONE; + pin_irq_hdr_tab[irqindex].hdr = RT_NULL; + pin_irq_hdr_tab[irqindex].mode = PIN_IRQ_MODE_RISING; + pin_irq_hdr_tab[irqindex].args = RT_NULL; + g_u32PinIrqMask &= ~(1 << irqindex); + break; + } + u32PinIrqStatus &= ~(1 << irqindex); + } + + rt_hw_interrupt_enable(level); + return RT_EOK; +} + +static void nu_gpio_isr(int vector, void *param) +{ + rt_uint32_t int_status; + GPIO_T *PORT = (GPIO_T *)param; + rt_uint32_t port_idx = ((rt_uint32_t)PORT - GPIOA_BASE) / PORT_OFFSET ; + + int_status = PORT->INTSRC; + pin_irq_hdr(int_status, port_idx); + PORT->INTSRC = int_status; +} + +static rt_err_t nu_gpio_irq_enable(struct rt_device *device, rt_base_t pin, rt_uint32_t enabled) +{ + GPIO_T *PORT; + rt_base_t level; + uint32_t u32IntAttribs; + rt_int32_t irqindex; + rt_err_t ret = RT_EOK; + IRQn_Type irqn; + + if (nu_port_check(pin)) + return -(RT_ERROR); + + level = rt_hw_interrupt_disable(); + + irqindex = nu_find_irqindex(pin); + if (irqindex == -(RT_ERROR)) + { + ret = RT_ERROR; + goto exit_nu_gpio_irq_enable; + } + + PORT = (GPIO_T *)(GPIOA_BASE + (NU_GET_PORT(pin) * PORT_OFFSET)); + + irqn = au32GPIRQ[NU_GET_PORT(pin)]; + + if (enabled == PIN_IRQ_ENABLE) + { + if (pin_irq_hdr_tab[irqindex].mode == PIN_IRQ_MODE_RISING) + u32IntAttribs = GPIO_INT_RISING; + else if (pin_irq_hdr_tab[irqindex].mode == PIN_IRQ_MODE_FALLING) + u32IntAttribs = GPIO_INT_FALLING; + else if (pin_irq_hdr_tab[irqindex].mode == PIN_IRQ_MODE_RISING_FALLING) + u32IntAttribs = GPIO_INT_BOTH_EDGE; + else if (pin_irq_hdr_tab[irqindex].mode == PIN_IRQ_MODE_HIGH_LEVEL) + u32IntAttribs = GPIO_INT_HIGH; + else if (pin_irq_hdr_tab[irqindex].mode == PIN_IRQ_MODE_LOW_LEVEL) + u32IntAttribs = GPIO_INT_LOW; + else + goto exit_nu_gpio_irq_enable; + + GPIO_EnableInt(PORT, NU_GET_PINS(pin), u32IntAttribs); + + rt_hw_interrupt_umask(irqn); + + } + else + { + GPIO_DisableInt(PORT, NU_GET_PINS(pin)); + rt_hw_interrupt_mask(irqn); + } + +exit_nu_gpio_irq_enable: + + rt_hw_interrupt_enable(level); + return -(ret); +} + +int rt_hw_gpio_init(void) +{ + char szTmp[16]; + int i; + rt_int32_t irqindex; + + for (irqindex = 0; irqindex < IRQ_MAX_NUM ; irqindex++) + { + pin_irq_hdr_tab[irqindex].pin = PIN_IRQ_PIN_NONE; + pin_irq_hdr_tab[irqindex].hdr = RT_NULL; + pin_irq_hdr_tab[irqindex].mode = PIN_IRQ_MODE_RISING; + pin_irq_hdr_tab[irqindex].args = RT_NULL; + } + + for (i = 0; i < NU_PORT_CNT ; i++) + { + IRQn_Type irqn = au32GPIRQ[i]; + rt_snprintf(szTmp, sizeof(szTmp), "gpio-%d", i); + rt_hw_interrupt_install(irqn, nu_gpio_isr, (void *)(GPIOA_BASE + (i * PORT_OFFSET)), szTmp); + } + + return rt_device_pin_register("gpio", &nu_gpio_ops, RT_NULL); +} + +INIT_BOARD_EXPORT(rt_hw_gpio_init); + +#endif //#if (defined(BSP_USING_GPIO) && defined(RT_USING_PIN)) diff --git a/bsp/nuvoton/libraries/ma35/rtt_port/drv_gpio.h b/bsp/nuvoton/libraries/ma35/rtt_port/drv_gpio.h new file mode 100644 index 0000000000..6807ac408c --- /dev/null +++ b/bsp/nuvoton/libraries/ma35/rtt_port/drv_gpio.h @@ -0,0 +1,40 @@ +/**************************************************************************//** +* +* @copyright (C) 2020 Nuvoton Technology Corp. All rights reserved. +* +* SPDX-License-Identifier: Apache-2.0 +* +* Change Logs: +* Date Author Notes +* 2021-8-17 Wayne First version +* +******************************************************************************/ + +#ifndef __DRV_GPIO_H__ +#define __DRV_GPIO_H__ + +typedef enum +{ + NU_PA, + NU_PB, + NU_PC, + NU_PD, + NU_PE, + NU_PF, + NU_PG, + NU_PH, + NU_PI, + NU_PJ, + NU_PK, + NU_PL, + NU_PM, + NU_PN, + NU_PORT_CNT, +} nu_gpio_port; + +#define NU_GET_PININDEX(port, pin) (((port)<<4) + (pin)) +#define NU_GET_PINS(rt_pin_index) ((rt_pin_index) & 0x0000000F) +#define NU_GET_PORT(rt_pin_index) (((rt_pin_index)>>4) & 0x0000000F) +#define NU_GET_PIN_MASK(nu_gpio_pin) (1 << (nu_gpio_pin)) + +#endif //__DRV_GPIO_H__ diff --git a/bsp/nuvoton/libraries/ma35/rtt_port/drv_i2c.c b/bsp/nuvoton/libraries/ma35/rtt_port/drv_i2c.c new file mode 100644 index 0000000000..c4f9781681 --- /dev/null +++ b/bsp/nuvoton/libraries/ma35/rtt_port/drv_i2c.c @@ -0,0 +1,409 @@ +/**************************************************************************//** +* +* @copyright (C) 2020 Nuvoton Technology Corp. All rights reserved. +* +* SPDX-License-Identifier: Apache-2.0 +* +* Change Logs: +* Date Author Notes +* 2020-11-11 Wayne First version +******************************************************************************/ + + +#include + +#if defined( BSP_USING_I2C) + +#include +#include "NuMicro.h" +#include +#include + +/* Private define ---------------------------------------------------------------*/ +#define LOG_TAG "drv.i2c" +#define DBG_ENABLE +#define DBG_SECTION_NAME LOG_TAG +#define DBG_LEVEL DBG_INFO +#define DBG_COLOR +#include + +enum +{ + I2C_START = -1, +#if defined(BSP_USING_I2C0) + I2C0_IDX, +#endif +#if defined(BSP_USING_I2C1) + I2C1_IDX, +#endif +#if defined(BSP_USING_I2C2) + I2C2_IDX, +#endif +#if defined(BSP_USING_I2C3) + I2C3_IDX, +#endif +#if defined(BSP_USING_I2C4) + I2C4_IDX, +#endif +#if defined(BSP_USING_I2C5) + I2C5_IDX, +#endif + I2C_CNT +}; + +/* Private typedef --------------------------------------------------------------*/ +typedef struct _nu_i2c_bus +{ + struct rt_i2c_bus_device parent; + I2C_T *I2C; + struct rt_i2c_msg *msg; + char *device_name; +} nu_i2c_bus_t; + +/* Private variables ------------------------------------------------------------*/ + + +static nu_i2c_bus_t nu_i2c_arr [ ] = +{ +#if defined(BSP_USING_I2C0) + { + .I2C = I2C0, .device_name = "i2c0", + }, +#endif +#if defined(BSP_USING_I2C1) + { + .I2C = I2C1, .device_name = "i2c1", + }, +#endif +#if defined(BSP_USING_I2C2) + { + .I2C = I2C2, .device_name = "i2c2", + }, +#endif +#if defined(BSP_USING_I2C3) + { + .I2C = I2C3, .device_name = "i2c3", + }, +#endif +#if defined(BSP_USING_I2C4) + { + .I2C = I2C4, .device_name = "i2c4", + }, +#endif +#if defined(BSP_USING_I2C5) + { + .I2C = I2C5, .device_name = "i2c5", + }, +#endif +}; + +/* Private functions ------------------------------------------------------------*/ +#if defined(BSP_USING_I2C) +static rt_size_t nu_i2c_mst_xfer(struct rt_i2c_bus_device *bus, + struct rt_i2c_msg msgs[], + rt_uint32_t num); +static rt_err_t nu_i2c_bus_control(struct rt_i2c_bus_device *bus, + rt_uint32_t u32Cmd, + rt_uint32_t u32Value); + +static const struct rt_i2c_bus_device_ops nu_i2c_ops = +{ + .master_xfer = nu_i2c_mst_xfer, + .slave_xfer = NULL, + .i2c_bus_control = nu_i2c_bus_control +}; + +static rt_err_t nu_i2c_bus_control(struct rt_i2c_bus_device *bus, rt_uint32_t u32Cmd, rt_uint32_t u32Value) +{ + nu_i2c_bus_t *nu_i2c; + + RT_ASSERT(bus != RT_NULL); + nu_i2c = (nu_i2c_bus_t *) bus; + + switch (u32Cmd) + { + case RT_I2C_DEV_CTRL_CLK: + I2C_SetBusClockFreq(nu_i2c->I2C, u32Value); + break; + default: + return -RT_EIO; + } + + return RT_EOK; +} + +static inline rt_err_t nu_i2c_wait_ready_with_timeout(nu_i2c_bus_t *bus) +{ + rt_tick_t start = rt_tick_get(); + while (!(bus->I2C->CTL0 & I2C_CTL0_SI_Msk)) + { + if ((rt_tick_get() - start) > bus->parent.timeout) + { + LOG_E("\ni2c: timeout!\n"); + return -RT_ETIMEOUT; + } + } + + return RT_EOK; +} + +static inline rt_err_t nu_i2c_send_data(nu_i2c_bus_t *nu_i2c, rt_uint8_t data) +{ + I2C_SET_DATA(nu_i2c->I2C, data); + I2C_SET_CONTROL_REG(nu_i2c->I2C, I2C_CTL_SI); + return nu_i2c_wait_ready_with_timeout(nu_i2c); +} + +static rt_err_t nu_i2c_send_address(nu_i2c_bus_t *nu_i2c, + struct rt_i2c_msg *msg) +{ + rt_uint16_t flags = msg->flags; + rt_uint16_t ignore_nack = msg->flags & RT_I2C_IGNORE_NACK; + rt_uint8_t addr1, addr2; + rt_err_t ret; + + + if (flags & RT_I2C_ADDR_10BIT) + { + nu_i2c->I2C->CTL1 |= I2C_CTL1_ADDR10EN_Msk; + addr1 = 0xf0 | ((msg->addr >> 7) & 0x06); + addr2 = msg->addr & 0xff; + + LOG_D("address1: %d, address2: %d\n", addr1, addr2); + + ret = nu_i2c_send_data(nu_i2c, addr1); + if (ret != RT_EOK) /* for timeout condition */ + return -RT_EIO; + + if ((I2C_GET_STATUS(nu_i2c->I2C) != NU_I2C_MASTER_STATUS_TRANSMIT_ADDRESS_ACK) && !ignore_nack) + { + LOG_E("NACK: sending first address failed\n"); + + return -RT_EIO; + } + + ret = nu_i2c_send_data(nu_i2c, addr2); + if (ret != RT_EOK) /* for timeout condition */ + return -RT_EIO; + + if ((I2C_GET_STATUS(nu_i2c->I2C) != NU_I2C_MASTER_STATUS_TRANSMIT_ADDRESS_ACK) && !ignore_nack) + { + LOG_E("NACK: sending second address failed\n"); + + return -RT_EIO; + } + + if (flags & RT_I2C_RD) + { + LOG_D("send repeated START signal\n"); + + I2C_SET_CONTROL_REG(nu_i2c->I2C, I2C_CTL_STA_SI); + ret = nu_i2c_wait_ready_with_timeout(nu_i2c); + if (ret != RT_EOK) /* for timeout condition */ + return -RT_EIO; + + if ((I2C_GET_STATUS(nu_i2c->I2C) != NU_I2C_MASTER_STATUS_REPEAT_START) && !ignore_nack) + { + //LOG_E("sending repeated START failed\n"); + + return -RT_EIO; + } + + addr1 |= 0x01; + + ret = nu_i2c_send_data(nu_i2c, addr1); + if (ret != RT_EOK) /* for timeout condition */ + return -RT_EIO; + + if ((I2C_GET_STATUS(nu_i2c->I2C) != NU_I2C_MASTER_STATUS_RECEIVE_ADDRESS_ACK) && !ignore_nack) + { + LOG_E("NACK: sending read address failed\n"); + + return -RT_EIO; + } + } + } + else + { + /* 7-bit addr */ + addr1 = msg->addr << 1; + if (flags & RT_I2C_RD) + addr1 |= 1; + + /* Send device address */ + ret = nu_i2c_send_data(nu_i2c, addr1); /* Send Address */ + if (ret != RT_EOK) /* for timeout condition */ + return -RT_EIO; + + if ((I2C_GET_STATUS(nu_i2c->I2C) + != ((flags & RT_I2C_RD) ? NU_I2C_MASTER_STATUS_RECEIVE_ADDRESS_ACK : NU_I2C_MASTER_STATUS_TRANSMIT_ADDRESS_ACK)) + && !ignore_nack) + { + LOG_E("sending address failed\n"); + return -RT_EIO; + } + } + + return RT_EOK; +} + +static rt_size_t nu_i2c_mst_xfer(struct rt_i2c_bus_device *bus, + struct rt_i2c_msg msgs[], + rt_uint32_t num) +{ + struct rt_i2c_msg *msg; + nu_i2c_bus_t *nu_i2c; + rt_size_t i; + rt_uint32_t cnt_data; + rt_uint16_t ignore_nack; + rt_err_t ret; + + RT_ASSERT(bus != RT_NULL); + nu_i2c = (nu_i2c_bus_t *) bus; + + nu_i2c->msg = msgs; + + nu_i2c->I2C->CTL0 |= I2C_CTL0_STA_Msk | I2C_CTL0_SI_Msk; + ret = nu_i2c_wait_ready_with_timeout(nu_i2c); + if (ret != RT_EOK) /* for timeout condition */ + { + rt_set_errno(-RT_ETIMEOUT); + return 0; + } + if (I2C_GET_STATUS(nu_i2c->I2C) != NU_I2C_MASTER_STATUS_START) + { + i = 0; + LOG_E("Send START Failed"); + return i; + } + + for (i = 0; i < num; i++) + { + msg = &msgs[i]; + ignore_nack = msg->flags & RT_I2C_IGNORE_NACK; + + if (!(msg->flags & RT_I2C_NO_START)) + { + if (i) + { + I2C_SET_CONTROL_REG(nu_i2c->I2C, I2C_CTL_STA_SI); + ret = nu_i2c_wait_ready_with_timeout(nu_i2c); + if (ret != RT_EOK) /* for timeout condition */ + break; + + if (I2C_GET_STATUS(nu_i2c->I2C) != NU_I2C_MASTER_STATUS_REPEAT_START) + { + i = 0; + //LOG_E("Send repeat START Fail"); + break; + } + } + + if ((RT_EOK != nu_i2c_send_address(nu_i2c, msg)) + && !ignore_nack) + { + i = 0; + LOG_E("Send Address Fail"); + break; + } + } + + + if (nu_i2c->msg[i].flags & RT_I2C_RD) /* Receive Bytes */ + { + rt_uint32_t do_rd_nack = (i == (num - 1)); + for (cnt_data = 0 ; cnt_data < (nu_i2c->msg[i].len) ; cnt_data++) + { + do_rd_nack += (cnt_data == (nu_i2c->msg[i].len - 1)); /* NACK after last byte for hardware setting */ + if (do_rd_nack == 2) + { + I2C_SET_CONTROL_REG(nu_i2c->I2C, I2C_CTL_SI); + } + else + { + I2C_SET_CONTROL_REG(nu_i2c->I2C, I2C_CTL_SI_AA); + } + + ret = nu_i2c_wait_ready_with_timeout(nu_i2c); + if (ret != RT_EOK) /* for timeout condition */ + break; + + if (nu_i2c->I2C->CTL0 & I2C_CTL_AA) + { + if (I2C_GET_STATUS(nu_i2c->I2C) != NU_I2C_MASTER_STATUS_RECEIVE_DATA_ACK) + { + i = 0; + break; + } + } + else + { + if (I2C_GET_STATUS(nu_i2c->I2C) != NU_I2C_MASTER_STATUS_RECEIVE_DATA_NACK) + { + i = 0; + break; + } + } + + nu_i2c->msg[i].buf[cnt_data] = nu_i2c->I2C->DAT; + } + } + else /* Send Bytes */ + { + for (cnt_data = 0 ; cnt_data < (nu_i2c->msg[i].len) ; cnt_data++) + { + /* Send register number and MSB of data */ + ret = nu_i2c_send_data(nu_i2c, (uint8_t)(nu_i2c->msg[i].buf[cnt_data])); + if (ret != RT_EOK) /* for timeout condition */ + break; + + if (I2C_GET_STATUS(nu_i2c->I2C) != NU_I2C_MASTER_STATUS_TRANSMIT_DATA_ACK + && !ignore_nack + ) /* Send aata and get Ack */ + { + i = 0; + break; + } + } + } + } + + I2C_STOP(nu_i2c->I2C); + + RT_ASSERT(I2C_GET_STATUS(nu_i2c->I2C) == NU_I2C_MASTER_STATUS_BUS_RELEASED); + if (I2C_GET_STATUS(nu_i2c->I2C) != NU_I2C_MASTER_STATUS_BUS_RELEASED) + { + i = 0; + } + + nu_i2c->msg = RT_NULL; + nu_i2c->I2C->CTL1 = 0; /*clear all sub modes like 10 bit mode*/ + return i; +} +#endif + +/* Public functions -------------------------------------------------------------*/ +int rt_hw_i2c_init(void) +{ + int i; + rt_err_t ret = RT_EOK; + + for (i = (I2C_START + 1); i < I2C_CNT; i++) + { + /* Reset and initial IP engine. */ + I2C_Close(nu_i2c_arr[i].I2C); + I2C_Open(nu_i2c_arr[i].I2C, 100000); + + nu_i2c_arr[i].parent.ops = &nu_i2c_ops; + + ret = rt_i2c_bus_device_register(&nu_i2c_arr[i].parent, nu_i2c_arr[i].device_name); + RT_ASSERT(RT_EOK == ret); + } + + return 0; +} + +INIT_DEVICE_EXPORT(rt_hw_i2c_init); + +#endif /* BSP_USING_I2C */ + diff --git a/bsp/nuvoton/libraries/ma35/rtt_port/drv_i2c.h b/bsp/nuvoton/libraries/ma35/rtt_port/drv_i2c.h new file mode 100644 index 0000000000..6a314fa0b9 --- /dev/null +++ b/bsp/nuvoton/libraries/ma35/rtt_port/drv_i2c.h @@ -0,0 +1,36 @@ +/**************************************************************************//** +* +* @copyright (C) 2020 Nuvoton Technology Corp. All rights reserved. +* +* SPDX-License-Identifier: Apache-2.0 +* +* Change Logs: +* Date Author Notes +* 2020-11-11 Wayne First version +* +******************************************************************************/ + +#ifndef __DRV_I2C_H__ +#define __DRV_I2C_H__ + +#define NU_I2C_MASTER_STATUS_START 0x08UL +#define NU_I2C_MASTER_STATUS_REPEAT_START 0x10UL +#define NU_I2C_MASTER_STATUS_TRANSMIT_ADDRESS_ACK 0x18UL +#define NU_I2C_MASTER_STATUS_TRANSMIT_ADDRESS_NACK 0x20UL +#define NU_I2C_MASTER_STATUS_TRANSMIT_DATA_ACK 0x28UL +#define NU_I2C_MASTER_STATUS_TRANSMIT_DATA_NACK 0x30UL +#define NU_I2C_MASTER_STATUS_ARBITRATION_LOST 0x38UL +#define NU_I2C_MASTER_STATUS_RECEIVE_ADDRESS_ACK 0x40UL +#define NU_I2C_MASTER_STATUS_RECEIVE_ADDRESS_NACK 0x48UL +#define NU_I2C_MASTER_STATUS_RECEIVE_DATA_ACK 0x50UL +#define NU_I2C_MASTER_STATUS_RECEIVE_DATA_NACK 0x58UL +#define NU_I2C_MASTER_STATUS_BUS_ERROR 0x00UL +#define NU_I2C_MASTER_STATUS_BUS_RELEASED 0xF8UL + +#define NU_I2C_SLAVE_STATUS_TRANSMIT_REPEAT_START_OR_STOP 0xA0UL +#define NU_I2C_SLAVE_STATUS_TRANSMIT_ADDRESS_ACK 0xA8UL +#define NU_I2C_SLAVE_STATUS_TRANSMIT_DATA_NACK 0xC0UL +#define NU_I2C_SLAVE_STATUS_RECEIVE_ADDRESS_ACK 0x60UL +#define NU_I2C_SLAVE_STATUS_RECEIVE_DATA_ACK 0x80UL + +#endif /* __DRV_I2C_H__ */ diff --git a/bsp/nuvoton/libraries/ma35/rtt_port/drv_i2s.c b/bsp/nuvoton/libraries/ma35/rtt_port/drv_i2s.c new file mode 100644 index 0000000000..0bcb5b88cb --- /dev/null +++ b/bsp/nuvoton/libraries/ma35/rtt_port/drv_i2s.c @@ -0,0 +1,637 @@ +/**************************************************************************//** +* +* @copyright (C) 2020 Nuvoton Technology Corp. All rights reserved. +* +* SPDX-License-Identifier: Apache-2.0 +* +* Change Logs: +* Date Author Notes +* 2020-2-7 Wayne Lin First version +* +******************************************************************************/ + +#include + +#if defined(BSP_USING_I2S) + +#include +#include "drv_pdma.h" +#include "drv_i2s.h" +#include "drv_common.h" + +/* Private define ---------------------------------------------------------------*/ +#define DBG_ENABLE +#define DBG_LEVEL DBG_LOG +#define DBG_SECTION_NAME "i2s" +#define DBG_COLOR +#include + +enum +{ + I2S_START = -1, +#if defined(BSP_USING_I2S0) + I2S0_IDX, +#endif +#if defined(BSP_USING_I2S1) + I2S1_IDX, +#endif + I2S_CNT +}; + +/* Private functions ------------------------------------------------------------*/ +static rt_err_t nu_i2s_getcaps(struct rt_audio_device *audio, struct rt_audio_caps *caps); +static rt_err_t nu_i2s_configure(struct rt_audio_device *audio, struct rt_audio_caps *caps); +static rt_err_t nu_i2s_init(struct rt_audio_device *audio); +static rt_err_t nu_i2s_start(struct rt_audio_device *audio, int stream); +static rt_err_t nu_i2s_stop(struct rt_audio_device *audio, int stream); +static void nu_i2s_buffer_info(struct rt_audio_device *audio, struct rt_audio_buf_info *info); +/* Public functions -------------------------------------------------------------*/ +rt_err_t nu_i2s_acodec_register(nu_acodec_ops_t); + +/* Private variables ------------------------------------------------------------*/ +static struct nu_i2s nu_i2s_arr[] = +{ +#if defined(BSP_USING_I2S0) + { + .name = "sound0", + .i2s_base = I2S0, + .i2s_rst = I2S0_RST, + .i2s_dais = { + [NU_I2S_DAI_PLAYBACK] = { + .pdma_perp = PDMA_I2S0_TX, + }, + [NU_I2S_DAI_CAPTURE] = { + .pdma_perp = PDMA_I2S0_RX, + } + } + }, +#endif +#if defined(BSP_USING_I2S1) + { + .name = "sound1", + .i2s_base = I2S1, + .i2s_rst = I2S1_RST, + .i2s_dais = { + [NU_I2S_DAI_PLAYBACK] = { + .pdma_perp = PDMA_I2S1_TX, + }, + [NU_I2S_DAI_CAPTURE] = { + .pdma_perp = PDMA_I2S1_RX, + } + } + }, +#endif +}; + +static void nu_pdma_i2s_rx_cb(void *pvUserData, uint32_t u32EventFilter) +{ + nu_i2s_t psNuI2s = (nu_i2s_t)pvUserData; + nu_i2s_dai_t psNuI2sDai; + + RT_ASSERT(psNuI2s != RT_NULL); + psNuI2sDai = &psNuI2s->i2s_dais[NU_I2S_DAI_CAPTURE]; + + if (u32EventFilter & NU_PDMA_EVENT_TRANSFER_DONE) + { + /* Report uncacheable memory address to upper layer. */ + rt_uint8_t *pbuf_old = (rt_uint8_t *)((uint32_t)&psNuI2sDai->fifo[psNuI2sDai->fifo_block_idx * NU_I2S_DMA_BUF_BLOCK_SIZE] | UNCACHEABLE) ; + psNuI2sDai->fifo_block_idx = (psNuI2sDai->fifo_block_idx + 1) % NU_I2S_DMA_BUF_BLOCK_NUMBER; + + /* Report upper layer. */ + rt_audio_rx_done(&psNuI2s->audio, pbuf_old, NU_I2S_DMA_BUF_BLOCK_SIZE); + } +} + +static void nu_pdma_i2s_tx_cb(void *pvUserData, uint32_t u32EventFilter) +{ + nu_i2s_t psNuI2s = (nu_i2s_t)pvUserData; + nu_i2s_dai_t psNuI2sDai; + + RT_ASSERT(psNuI2s != RT_NULL); + psNuI2sDai = &psNuI2s->i2s_dais[NU_I2S_DAI_PLAYBACK]; + + if (u32EventFilter & NU_PDMA_EVENT_TRANSFER_DONE) + { + rt_audio_tx_complete(&psNuI2s->audio); + psNuI2sDai->fifo_block_idx = (psNuI2sDai->fifo_block_idx + 1) % NU_I2S_DMA_BUF_BLOCK_NUMBER; + } +} + +static rt_err_t nu_i2s_pdma_sc_config(nu_i2s_t psNuI2s, E_NU_I2S_DAI dai) +{ + rt_err_t result = RT_EOK; + I2S_T *i2s_base; + nu_i2s_dai_t psNuI2sDai; + int i; + uint32_t u32Src, u32Dst; + nu_pdma_cb_handler_t pfm_pdma_cb; + struct nu_pdma_chn_cb sChnCB; + + RT_ASSERT(psNuI2s != RT_NULL); + + /* Get base address of i2s register */ + i2s_base = psNuI2s->i2s_base; + psNuI2sDai = &psNuI2s->i2s_dais[dai]; + + switch ((int)dai) + { + case NU_I2S_DAI_PLAYBACK: + pfm_pdma_cb = nu_pdma_i2s_tx_cb; + u32Src = (uint32_t)&psNuI2sDai->fifo[0]; + u32Dst = (uint32_t)&i2s_base->TXFIFO; + break; + + case NU_I2S_DAI_CAPTURE: + pfm_pdma_cb = nu_pdma_i2s_rx_cb; + u32Src = (uint32_t)&i2s_base->RXFIFO; + u32Dst = (uint32_t)&psNuI2sDai->fifo[0]; + break; + + default: + return -RT_EINVAL; + } + /* Register ISR callback function */ + sChnCB.m_eCBType = eCBType_Event; + sChnCB.m_pfnCBHandler = pfm_pdma_cb; + sChnCB.m_pvUserData = (void *)psNuI2s; + + nu_pdma_filtering_set(psNuI2sDai->pdma_chanid, NU_PDMA_EVENT_TRANSFER_DONE); + result = nu_pdma_callback_register(psNuI2sDai->pdma_chanid, &sChnCB); + + RT_ASSERT(result == RT_EOK); + + for (i = 0; i < NU_I2S_DMA_BUF_BLOCK_NUMBER; i++) + { + /* Setup dma descriptor entry */ + result = nu_pdma_desc_setup(psNuI2sDai->pdma_chanid, // Channel ID + psNuI2sDai->pdma_descs[i], // this descriptor + 32, // 32-bits + (dai == NU_I2S_DAI_PLAYBACK) ? u32Src + (i * NU_I2S_DMA_BUF_BLOCK_SIZE) : u32Src, //Memory or RXFIFO + (dai == NU_I2S_DAI_PLAYBACK) ? u32Dst : u32Dst + (i * NU_I2S_DMA_BUF_BLOCK_SIZE), //TXFIFO or Memory + (int32_t)NU_I2S_DMA_BUF_BLOCK_SIZE / 4, // Transfer count + psNuI2sDai->pdma_descs[(i + 1) % NU_I2S_DMA_BUF_BLOCK_NUMBER], // Next descriptor + 0); // Interrupt assert when every SG-table done. + RT_ASSERT(result == RT_EOK); + } + + /* Assign head descriptor */ + result = nu_pdma_sg_transfer(psNuI2sDai->pdma_chanid, psNuI2sDai->pdma_descs[0], 0); + RT_ASSERT(result == RT_EOK); + + return result; +} + +static rt_bool_t nu_i2s_capacity_check(struct rt_audio_configure *pconfig) +{ + switch (pconfig->samplebits) + { + case 8: + case 16: + /* case 24: PDMA constrain */ + case 32: + break; + default: + goto exit_nu_i2s_capacity_check; + } + + switch (pconfig->channels) + { + case 1: + case 2: + break; + default: + goto exit_nu_i2s_capacity_check; + } + + return RT_TRUE; + +exit_nu_i2s_capacity_check: + + return RT_FALSE; +} + +static rt_err_t nu_i2s_dai_setup(nu_i2s_t psNuI2s, struct rt_audio_configure *pconfig) +{ + rt_err_t result = RT_EOK; + nu_acodec_ops_t pNuACodecOps = RT_NULL; + RT_ASSERT(psNuI2s->AcodecOps != RT_NULL); + pNuACodecOps = psNuI2s->AcodecOps; + rt_uint32_t real_samplerate; + + /* Open I2S */ + if (nu_i2s_capacity_check(pconfig) == RT_TRUE) + { + /* Reset audio codec */ + if (pNuACodecOps->nu_acodec_reset) + result = pNuACodecOps->nu_acodec_reset(); + + if (result != RT_EOK) + goto exit_nu_i2s_dai_setup; + + /* Setup audio codec */ + if (pNuACodecOps->nu_acodec_init) + result = pNuACodecOps->nu_acodec_init(); + + if (!pNuACodecOps->nu_acodec_init || result != RT_EOK) + goto exit_nu_i2s_dai_setup; + + /* Setup acodec samplerate/samplebit/channel */ + if (pNuACodecOps->nu_acodec_dsp_control) + result = pNuACodecOps->nu_acodec_dsp_control(pconfig); + + if (!pNuACodecOps->nu_acodec_dsp_control || result != RT_EOK) + goto exit_nu_i2s_dai_setup; + + real_samplerate = I2S_Open(psNuI2s->i2s_base, + (psNuI2s->AcodecOps->role == NU_ACODEC_ROLE_MASTER) ? I2S_MODE_SLAVE : I2S_MODE_MASTER, + pconfig->samplerate, + (((pconfig->samplebits / 8) - 1) << I2S_CTL0_DATWIDTH_Pos), + (pconfig->channels == 1) ? I2S_ENABLE_MONO : I2S_DISABLE_MONO, + I2S_FORMAT_I2S); + LOG_I("Open I2S."); + + /* Open I2S0 interface and set to slave mode, stereo channel, I2S format */ + if (pconfig->samplerate != real_samplerate) + { + LOG_W("Real sample rate: %d Hz != preferred sample rate: %d Hz\n", real_samplerate, pconfig->samplerate); + } + + /* Set MCLK and enable MCLK */ + /* The target MCLK is related to audio codec setting. */ + I2S_EnableMCLK(psNuI2s->i2s_base, 12000000); + + /* Set unmute */ + if (pNuACodecOps->nu_acodec_mixer_control) + pNuACodecOps->nu_acodec_mixer_control(AUDIO_MIXER_MUTE, RT_FALSE); + } + else + result = -RT_EINVAL; + +exit_nu_i2s_dai_setup: + + return result; +} + +static rt_err_t nu_i2s_getcaps(struct rt_audio_device *audio, struct rt_audio_caps *caps) +{ + rt_err_t result = RT_EOK; + nu_i2s_t psNuI2s; + nu_acodec_ops_t pNuACodecOps = RT_NULL; + + RT_ASSERT(audio != RT_NULL); + RT_ASSERT(caps != RT_NULL); + + psNuI2s = (nu_i2s_t)audio; + + RT_ASSERT(psNuI2s->AcodecOps != RT_NULL); + + pNuACodecOps = psNuI2s->AcodecOps; + + switch (caps->main_type) + { + case AUDIO_TYPE_QUERY: + switch (caps->sub_type) + { + case AUDIO_TYPE_QUERY: + caps->udata.mask = AUDIO_TYPE_INPUT | AUDIO_TYPE_OUTPUT | AUDIO_TYPE_MIXER; + break; + default: + result = -RT_ERROR; + break; + } // switch (caps->sub_type) + break; + + case AUDIO_TYPE_MIXER: + + if (pNuACodecOps->nu_acodec_mixer_query) + { + switch (caps->sub_type) + { + case AUDIO_MIXER_QUERY: + return pNuACodecOps->nu_acodec_mixer_query(AUDIO_MIXER_QUERY, &caps->udata.mask); + + default: + return pNuACodecOps->nu_acodec_mixer_query(caps->sub_type, (rt_uint32_t *)&caps->udata.value); + } // switch (caps->sub_type) + + } // if (pNuACodecOps->nu_acodec_mixer_query) + + result = -RT_ERROR; + break; + + case AUDIO_TYPE_INPUT: + case AUDIO_TYPE_OUTPUT: + + switch (caps->sub_type) + { + case AUDIO_DSP_PARAM: + caps->udata.config.channels = psNuI2s->config.channels; + caps->udata.config.samplebits = psNuI2s->config.samplebits; + caps->udata.config.samplerate = psNuI2s->config.samplerate; + break; + case AUDIO_DSP_SAMPLERATE: + caps->udata.config.samplerate = psNuI2s->config.samplerate; + break; + case AUDIO_DSP_CHANNELS: + caps->udata.config.channels = psNuI2s->config.channels; + break; + case AUDIO_DSP_SAMPLEBITS: + caps->udata.config.samplebits = psNuI2s->config.samplebits; + break; + default: + result = -RT_ERROR; + break; + } // switch (caps->sub_type) + break; + + default: + result = -RT_ERROR; + break; + + } // switch (caps->main_type) + + return result; +} + +static rt_err_t nu_i2s_configure(struct rt_audio_device *audio, struct rt_audio_caps *caps) +{ + rt_err_t result = RT_EOK; + nu_i2s_t psNuI2s; + nu_acodec_ops_t pNuACodecOps = RT_NULL; + int stream = -1; + + RT_ASSERT(audio != RT_NULL); + RT_ASSERT(caps != RT_NULL); + + psNuI2s = (nu_i2s_t)audio; + + RT_ASSERT(psNuI2s->AcodecOps != RT_NULL); + pNuACodecOps = psNuI2s->AcodecOps; + + switch (caps->main_type) + { + case AUDIO_TYPE_MIXER: + if (psNuI2s->AcodecOps->nu_acodec_mixer_control) + psNuI2s->AcodecOps->nu_acodec_mixer_control(caps->sub_type, caps->udata.value); + break; + + + case AUDIO_TYPE_INPUT: + stream = AUDIO_STREAM_RECORD; + case AUDIO_TYPE_OUTPUT: + { + rt_bool_t bNeedReset = RT_FALSE; + + if (stream < 0) + stream = AUDIO_STREAM_REPLAY; + + switch (caps->sub_type) + { + case AUDIO_DSP_PARAM: + if (rt_memcmp(&psNuI2s->config, &caps->udata.config, sizeof(struct rt_audio_configure)) != 0) + { + rt_memcpy(&psNuI2s->config, &caps->udata.config, sizeof(struct rt_audio_configure)); + bNeedReset = RT_TRUE; + } + break; + case AUDIO_DSP_SAMPLEBITS: + if (psNuI2s->config.samplerate != caps->udata.config.samplebits) + { + psNuI2s->config.samplerate = caps->udata.config.samplebits; + bNeedReset = RT_TRUE; + } + break; + case AUDIO_DSP_CHANNELS: + if (psNuI2s->config.channels != caps->udata.config.channels) + { + pNuACodecOps->config.channels = caps->udata.config.channels; + bNeedReset = RT_TRUE; + } + break; + case AUDIO_DSP_SAMPLERATE: + if (psNuI2s->config.samplerate != caps->udata.config.samplerate) + { + psNuI2s->config.samplerate = caps->udata.config.samplerate; + bNeedReset = RT_TRUE; + } + break; + default: + result = -RT_ERROR; + break; + } // switch (caps->sub_type) + + if (bNeedReset) + { + return nu_i2s_start(audio, stream); + } + } + break; + default: + result = -RT_ERROR; + break; + } // switch (caps->main_type) + + return result; +} + +static rt_err_t nu_i2s_init(struct rt_audio_device *audio) +{ + rt_err_t result = RT_EOK; + nu_i2s_t psNuI2s; + + RT_ASSERT(audio != RT_NULL); + + psNuI2s = (nu_i2s_t)audio; + + /* Reset this module */ + SYS_ResetModule(psNuI2s->i2s_rst); + + return -(result); +} + +static rt_err_t nu_i2s_start(struct rt_audio_device *audio, int stream) +{ + nu_i2s_t psNuI2s; + + RT_ASSERT(audio != RT_NULL); + + psNuI2s = (nu_i2s_t)audio; + + /* Restart all: I2S and codec. */ + nu_i2s_stop(audio, stream); + if (nu_i2s_dai_setup(psNuI2s, &psNuI2s->config) != RT_EOK) + return -RT_ERROR; + + switch (stream) + { + case AUDIO_STREAM_REPLAY: + { + nu_i2s_pdma_sc_config(psNuI2s, NU_I2S_DAI_PLAYBACK); + + /* Start TX DMA */ + I2S_ENABLE_TXDMA(psNuI2s->i2s_base); + + /* Enable I2S Tx function */ + I2S_ENABLE_TX(psNuI2s->i2s_base); + + LOG_I("Start replay."); + } + break; + + case AUDIO_STREAM_RECORD: + { + nu_i2s_pdma_sc_config(psNuI2s, NU_I2S_DAI_CAPTURE); + + /* Start RX DMA */ + I2S_ENABLE_RXDMA(psNuI2s->i2s_base); + + /* Enable I2S Rx function */ + I2S_ENABLE_RX(psNuI2s->i2s_base); + + LOG_I("Start record."); + } + break; + + default: + return -RT_ERROR; + } + + return RT_EOK; +} + +static rt_err_t nu_i2s_stop(struct rt_audio_device *audio, int stream) +{ + nu_i2s_t psNuI2s; + nu_i2s_dai_t psNuI2sDai = RT_NULL; + + RT_ASSERT(audio != RT_NULL); + + psNuI2s = (nu_i2s_t)audio; + + switch (stream) + { + case AUDIO_STREAM_REPLAY: + psNuI2sDai = &psNuI2s->i2s_dais[NU_I2S_DAI_PLAYBACK]; + + // Disable TX + I2S_DISABLE_TXDMA(psNuI2s->i2s_base); + I2S_DISABLE_TX(psNuI2s->i2s_base); + + LOG_I("Stop replay."); + break; + + case AUDIO_STREAM_RECORD: + psNuI2sDai = &psNuI2s->i2s_dais[NU_I2S_DAI_CAPTURE]; + + // Disable RX + I2S_DISABLE_RXDMA(psNuI2s->i2s_base); + I2S_DISABLE_RX(psNuI2s->i2s_base); + + LOG_I("Stop record."); + break; + + default: + return -RT_EINVAL; + } + + /* Stop DMA transfer. */ + nu_pdma_channel_terminate(psNuI2sDai->pdma_chanid); + + /* Close I2S */ + if (!(psNuI2s->i2s_base->CTL0 & (I2S_CTL0_TXEN_Msk | I2S_CTL0_RXEN_Msk))) + { + I2S_DisableMCLK(psNuI2s->i2s_base); + I2S_Close(psNuI2s->i2s_base); + LOG_I("Close I2S."); + } + + /* Silence */ + rt_memset((void *)psNuI2sDai->fifo, 0, NU_I2S_DMA_FIFO_SIZE); + psNuI2sDai->fifo_block_idx = 0; + + return RT_EOK; +} + +static void nu_i2s_buffer_info(struct rt_audio_device *audio, struct rt_audio_buf_info *info) +{ + nu_i2s_t psNuI2s; + + RT_ASSERT(audio != RT_NULL); + RT_ASSERT(info != RT_NULL); + + psNuI2s = (nu_i2s_t)audio; + + /* Report uncacheable memory address to upper layer. */ + info->buffer = (rt_uint8_t *)((uint32_t)psNuI2s->i2s_dais[NU_I2S_DAI_PLAYBACK].fifo | UNCACHEABLE); + info->total_size = NU_I2S_DMA_FIFO_SIZE; + info->block_size = NU_I2S_DMA_BUF_BLOCK_SIZE; + info->block_count = NU_I2S_DMA_BUF_BLOCK_NUMBER; + + //rt_kprintf("info->buffer=%08x\n", (uint32_t)info->buffer); + //rt_kprintf("info->total_size=%d\n", (uint32_t)info->total_size); + //rt_kprintf("info->block_size=%d\n", (uint32_t)info->block_size); + //rt_kprintf("info->block_count=%d\n", (uint32_t)info->block_count); + + return; +} + +static struct rt_audio_ops nu_i2s_audio_ops = +{ + .getcaps = nu_i2s_getcaps, + .configure = nu_i2s_configure, + + .init = nu_i2s_init, + .start = nu_i2s_start, + .stop = nu_i2s_stop, + .transmit = RT_NULL, + .buffer_info = nu_i2s_buffer_info +}; + +static rt_err_t nu_hw_i2s_pdma_allocate(nu_i2s_dai_t psNuI2sDai) +{ + /* Allocate I2S nu_dma channel */ + if ((psNuI2sDai->pdma_chanid = nu_pdma_channel_allocate(psNuI2sDai->pdma_perp)) < 0) + { + goto nu_hw_i2s_pdma_allocate; + } + + return RT_EOK; + +nu_hw_i2s_pdma_allocate: + + return -(RT_ERROR); +} + +int rt_hw_i2s_init(void) +{ + int i, j; + nu_i2s_dai_t psNuI2sDai; + + for (j = (I2S_START + 1); j < I2S_CNT; j++) + { + for (i = 0; i < NU_I2S_DAI_CNT; i++) + { + uint8_t *pu8ptr = rt_malloc_align(NU_I2S_DMA_FIFO_SIZE, 64); + psNuI2sDai = &nu_i2s_arr[j].i2s_dais[i]; + psNuI2sDai->fifo = pu8ptr; + rt_memset(pu8ptr, 0, NU_I2S_DMA_FIFO_SIZE); + RT_ASSERT(psNuI2sDai->fifo != RT_NULL); + rt_kprintf("psNuI2sDai->fifo=%08x\n", (uint32_t)psNuI2sDai->fifo); + + psNuI2sDai->pdma_chanid = -1; + psNuI2sDai->fifo_block_idx = 0; + RT_ASSERT(nu_hw_i2s_pdma_allocate(psNuI2sDai) == RT_EOK); + + RT_ASSERT(nu_pdma_sgtbls_allocate(&psNuI2sDai->pdma_descs[0], NU_I2S_DMA_BUF_BLOCK_NUMBER) == RT_EOK); + } + + /* Register ops of audio device */ + nu_i2s_arr[j].audio.ops = &nu_i2s_audio_ops; + + /* Register device, RW: it is with replay and record functions. */ + rt_audio_register(&nu_i2s_arr[j].audio, nu_i2s_arr[j].name, RT_DEVICE_FLAG_RDWR, &nu_i2s_arr[j]); + } + return RT_EOK; +} +INIT_DEVICE_EXPORT(rt_hw_i2s_init); +#endif //#if defined(BSP_USING_I2S) diff --git a/bsp/nuvoton/libraries/ma35/rtt_port/drv_i2s.h b/bsp/nuvoton/libraries/ma35/rtt_port/drv_i2s.h new file mode 100644 index 0000000000..9ee00646b8 --- /dev/null +++ b/bsp/nuvoton/libraries/ma35/rtt_port/drv_i2s.h @@ -0,0 +1,96 @@ +/**************************************************************************//** +* +* @copyright (C) 2020 Nuvoton Technology Corp. All rights reserved. +* +* SPDX-License-Identifier: Apache-2.0 +* +* Change Logs: +* Date Author Notes +* 2020-2-7 Wayne First version +* +******************************************************************************/ + +#ifndef __DRV_I2S_H__ +#define __DRV_I2S_H__ + +#include +#include "NuMicro.h" +#include + +#if !defined(NU_I2S_DMA_FIFO_SIZE) + #define NU_I2S_DMA_FIFO_SIZE (2048) +#endif + +#if !defined(NU_I2S_DMA_BUF_BLOCK_NUMBER) + #define NU_I2S_DMA_BUF_BLOCK_NUMBER (2) +#endif + +#if ( (NU_I2S_DMA_FIFO_SIZE % NU_I2S_DMA_BUF_BLOCK_NUMBER) != 0 ) + #error "Please give an aligned definition" +#endif +#if ( NU_I2S_DMA_FIFO_SIZE < 2048 ) + #warning "DMA FIFO too small, miss voice?" +#endif + +#define NU_I2S_DMA_BUF_BLOCK_SIZE (NU_I2S_DMA_FIFO_SIZE/NU_I2S_DMA_BUF_BLOCK_NUMBER) + +typedef enum +{ + NU_I2S_DAI_PLAYBACK, + NU_I2S_DAI_CAPTURE, + NU_I2S_DAI_CNT +} E_NU_I2S_DAI; + +typedef enum +{ + NU_ACODEC_ROLE_MASTER, + NU_ACODEC_ROLE_SLAVE, +} E_NU_ACODEC_ROLE; + +typedef struct +{ + char *name; + + E_NU_ACODEC_ROLE role; + + struct rt_audio_configure config; + + rt_err_t (*nu_acodec_init)(void); + + rt_err_t (*nu_acodec_reset)(void); + + rt_err_t (*nu_acodec_dsp_control)(struct rt_audio_configure *config); + + rt_err_t (*nu_acodec_mixer_control)(rt_uint32_t ui32Item, rt_uint32_t ui32Value); + + rt_err_t (*nu_acodec_mixer_query)(rt_uint32_t ui32Item, rt_uint32_t *ui32Value); + +} nu_acodec_ops; + +typedef nu_acodec_ops *nu_acodec_ops_t; + +struct nu_i2s_dai +{ + int16_t pdma_perp; + int8_t pdma_chanid; + rt_uint8_t *fifo; + int16_t fifo_block_idx; + nu_pdma_desc_t pdma_descs[NU_I2S_DMA_BUF_BLOCK_NUMBER]; +}; +typedef struct nu_i2s_dai *nu_i2s_dai_t; + +struct nu_i2s +{ + struct rt_audio_device audio; + struct rt_audio_configure config; + + char *name; + I2S_T *i2s_base; + uint32_t i2s_rst; + + struct nu_i2s_dai i2s_dais[NU_I2S_DAI_CNT]; + nu_acodec_ops_t AcodecOps; +}; +typedef struct nu_i2s *nu_i2s_t; + +#endif // __DRV_I2S_H___ diff --git a/bsp/nuvoton/libraries/ma35/rtt_port/drv_pdma.c b/bsp/nuvoton/libraries/ma35/rtt_port/drv_pdma.c new file mode 100644 index 0000000000..1c015ef704 --- /dev/null +++ b/bsp/nuvoton/libraries/ma35/rtt_port/drv_pdma.c @@ -0,0 +1,1265 @@ +/**************************************************************************//** +* +* @copyright (C) 2020 Nuvoton Technology Corp. All rights reserved. +* +* SPDX-License-Identifier: Apache-2.0 +* +* Change Logs: +* Date Author Notes +* 2021-7-15 Wayne First version +* +******************************************************************************/ + +#include + +#if defined(BSP_USING_PDMA) + +#include +#include +#include +#include +#include "drv_sys.h" + +/* Private define ---------------------------------------------------------------*/ +// RT_DEV_NAME_PREFIX pdma + +#ifndef NU_PDMA_MEMFUN_ACTOR_MAX + #define NU_PDMA_MEMFUN_ACTOR_MAX (4) +#endif + +/* To select the first PDMA base */ +#if !defined(USE_MA35D1_SUBM) + #define DEF_PDMA_BASE_START PDMA0_BASE +#else + #define DEF_PDMA_BASE_START PDMA2_BASE +#endif + +enum +{ + PDMA_START = -1, +#if defined(BSP_USING_PDMA0) + PDMA0_IDX, +#endif +#if defined(BSP_USING_PDMA1) + PDMA1_IDX, +#endif +#if defined(BSP_USING_PDMA2) + PDMA2_IDX, +#endif +#if defined(BSP_USING_PDMA3) + PDMA3_IDX, +#endif + PDMA_CNT +}; + +#define NU_PDMA_SG_TBL_MAXSIZE (NU_PDMA_SG_LIMITED_DISTANCE/sizeof(DSCT_T)) + +#define NU_PDMA_CH_MAX (PDMA_CNT*PDMA_CH_MAX) /* Specify maximum channels of PDMA */ +#define NU_PDMA_CH_Pos (0) /* Specify first channel number of PDMA */ +#define NU_PDMA_CH_Msk (PDMA_CH_Msk << NU_PDMA_CH_Pos) +#define NU_PDMA_GET_BASE(ch) (PDMA_T *)((((ch)/PDMA_CH_MAX)*0x10000UL) + DEF_PDMA_BASE_START) +#define NU_PDMA_GET_MOD_IDX(ch) ((ch)/PDMA_CH_MAX) +#define NU_PDMA_GET_MOD_CHIDX(ch) ((ch)%PDMA_CH_MAX) + +/* Private typedef --------------------------------------------------------------*/ +struct nu_pdma_periph_ctl +{ + uint32_t m_u32Peripheral; + nu_pdma_memctrl_t m_eMemCtl; +}; +typedef struct nu_pdma_periph_ctl nu_pdma_periph_ctl_t; + +struct nu_pdma_chn +{ + struct nu_pdma_chn_cb m_sCB_Event; + struct nu_pdma_chn_cb m_sCB_Trigger; + struct nu_pdma_chn_cb m_sCB_Disable; + + nu_pdma_desc_t *m_ppsSgtbl; + uint32_t m_u32WantedSGTblNum; + + uint32_t m_u32EventFilter; + uint32_t m_u32IdleTimeout_us; + nu_pdma_periph_ctl_t m_spPeripCtl; +}; +typedef struct nu_pdma_chn nu_pdma_chn_t; + +struct nu_pdma_memfun_actor +{ + int m_i32ChannID; + uint32_t m_u32Result; + rt_sem_t m_psSemMemFun; +} ; +typedef struct nu_pdma_memfun_actor *nu_pdma_memfun_actor_t; + +/* Private functions ------------------------------------------------------------*/ +static int nu_pdma_peripheral_set(uint32_t u32PeriphType); +static void nu_pdma_init(void); +static void nu_pdma_channel_enable(int i32ChannID); +static void nu_pdma_channel_disable(int i32ChannID); +static void nu_pdma_channel_reset(int i32ChannID); +static rt_err_t nu_pdma_timeout_set(int i32ChannID, int i32Timeout_us); +static void nu_pdma_periph_ctrl_fill(int i32ChannID, int i32CtlPoolIdx); +static rt_size_t nu_pdma_memfun(void *dest, void *src, uint32_t u32DataWidth, unsigned int u32TransferCnt, nu_pdma_memctrl_t eMemCtl); +static void nu_pdma_memfun_cb(void *pvUserData, uint32_t u32Events); +static void nu_pdma_memfun_actor_init(void); +static int nu_pdma_memfun_employ(void); +static int nu_pdma_non_transfer_count_get(int32_t i32ChannID); + +/* Public functions -------------------------------------------------------------*/ + + +/* Private variables ------------------------------------------------------------*/ +static volatile int nu_pdma_inited = 0; +static volatile uint32_t nu_pdma_chn_mask_arr[PDMA_CNT] = {0}; +static nu_pdma_chn_t nu_pdma_chn_arr[NU_PDMA_CH_MAX]; +static volatile uint32_t nu_pdma_memfun_actor_mask = 0; +static volatile uint32_t nu_pdma_memfun_actor_maxnum = 0; +static rt_sem_t nu_pdma_memfun_actor_pool_sem = RT_NULL; +static rt_mutex_t nu_pdma_memfun_actor_pool_lock = RT_NULL; +static void nu_pdma_isr(int vector, void *pvdata); + +const static struct nu_module nu_pdma_arr[] = +{ +#if defined(BSP_USING_PDMA0) + { + .name = "pdma0", + .m_pvBase = (void *)PDMA0, + .u32RstId = PDMA0_RST, + .eIRQn = PDMA0_IRQn + }, +#endif +#if defined(BSP_USING_PDMA1) + { + .name = "pdma1", + .m_pvBase = (void *)PDMA1, + .u32RstId = PDMA1_RST, + .eIRQn = PDMA1_IRQn + }, +#endif +#if defined(BSP_USING_PDMA2) + { + .name = "pdma2", + .m_pvBase = (void *)PDMA2, + .u32RstId = PDMA2_RST, + .eIRQn = PDMA2_IRQn + }, +#endif +#if defined(BSP_USING_PDMA3) + { + .name = "pdma3", + .m_pvBase = (void *)PDMA3, + .u32RstId = PDMA3_RST, + .eIRQn = PDMA3_IRQn + } +#endif +}; + +static const nu_pdma_periph_ctl_t g_nu_pdma_peripheral_ctl_pool[ ] = +{ + // M2M + { PDMA_MEM, eMemCtl_SrcInc_DstInc }, + + // M2P + { PDMA_UART0_TX, eMemCtl_SrcInc_DstFix }, + { PDMA_UART1_TX, eMemCtl_SrcInc_DstFix }, + { PDMA_UART2_TX, eMemCtl_SrcInc_DstFix }, + { PDMA_UART3_TX, eMemCtl_SrcInc_DstFix }, + { PDMA_UART4_TX, eMemCtl_SrcInc_DstFix }, + { PDMA_UART5_TX, eMemCtl_SrcInc_DstFix }, + { PDMA_UART6_TX, eMemCtl_SrcInc_DstFix }, + { PDMA_UART7_TX, eMemCtl_SrcInc_DstFix }, + { PDMA_UART8_TX, eMemCtl_SrcInc_DstFix }, + { PDMA_UART9_TX, eMemCtl_SrcInc_DstFix }, + { PDMA_UART10_TX, eMemCtl_SrcInc_DstFix }, + { PDMA_UART11_TX, eMemCtl_SrcInc_DstFix }, + { PDMA_UART12_TX, eMemCtl_SrcInc_DstFix }, + { PDMA_UART13_TX, eMemCtl_SrcInc_DstFix }, + { PDMA_UART14_TX, eMemCtl_SrcInc_DstFix }, + { PDMA_UART15_TX, eMemCtl_SrcInc_DstFix }, + { PDMA_UART16_TX, eMemCtl_SrcInc_DstFix }, + + { PDMA_QSPI0_TX, eMemCtl_SrcInc_DstFix }, + { PDMA_QSPI1_TX, eMemCtl_SrcInc_DstFix }, + + { PDMA_SPI0_TX, eMemCtl_SrcInc_DstFix }, + { PDMA_SPI1_TX, eMemCtl_SrcInc_DstFix }, + { PDMA_SPI2_TX, eMemCtl_SrcInc_DstFix }, + { PDMA_SPI3_TX, eMemCtl_SrcInc_DstFix }, + + { PDMA_I2C0_TX, eMemCtl_SrcInc_DstFix }, + { PDMA_I2C1_TX, eMemCtl_SrcInc_DstFix }, + { PDMA_I2C2_TX, eMemCtl_SrcInc_DstFix }, + { PDMA_I2C3_TX, eMemCtl_SrcInc_DstFix }, + { PDMA_I2C4_TX, eMemCtl_SrcInc_DstFix }, + { PDMA_I2C5_TX, eMemCtl_SrcInc_DstFix }, + + { PDMA_I2S0_TX, eMemCtl_SrcInc_DstFix }, + { PDMA_I2S1_TX, eMemCtl_SrcInc_DstFix }, + + // P2M + { PDMA_UART0_RX, eMemCtl_SrcFix_DstInc }, + { PDMA_UART1_RX, eMemCtl_SrcFix_DstInc }, + { PDMA_UART2_RX, eMemCtl_SrcFix_DstInc }, + { PDMA_UART3_RX, eMemCtl_SrcFix_DstInc }, + { PDMA_UART4_RX, eMemCtl_SrcFix_DstInc }, + { PDMA_UART5_RX, eMemCtl_SrcFix_DstInc }, + { PDMA_UART6_RX, eMemCtl_SrcFix_DstInc }, + { PDMA_UART7_RX, eMemCtl_SrcFix_DstInc }, + { PDMA_UART8_RX, eMemCtl_SrcFix_DstInc }, + { PDMA_UART9_RX, eMemCtl_SrcFix_DstInc }, + { PDMA_UART10_RX, eMemCtl_SrcFix_DstInc }, + { PDMA_UART11_RX, eMemCtl_SrcFix_DstInc }, + { PDMA_UART12_RX, eMemCtl_SrcFix_DstInc }, + { PDMA_UART13_RX, eMemCtl_SrcFix_DstInc }, + { PDMA_UART14_RX, eMemCtl_SrcFix_DstInc }, + { PDMA_UART15_RX, eMemCtl_SrcFix_DstInc }, + { PDMA_UART16_RX, eMemCtl_SrcFix_DstInc }, + + { PDMA_QSPI0_RX, eMemCtl_SrcFix_DstInc }, + { PDMA_QSPI1_RX, eMemCtl_SrcFix_DstInc }, + + { PDMA_SPI0_RX, eMemCtl_SrcFix_DstInc }, + { PDMA_SPI1_RX, eMemCtl_SrcFix_DstInc }, + { PDMA_SPI2_RX, eMemCtl_SrcFix_DstInc }, + { PDMA_SPI3_RX, eMemCtl_SrcFix_DstInc }, + + { PDMA_I2C0_RX, eMemCtl_SrcFix_DstInc }, + { PDMA_I2C1_RX, eMemCtl_SrcFix_DstInc }, + { PDMA_I2C2_RX, eMemCtl_SrcFix_DstInc }, + { PDMA_I2C3_RX, eMemCtl_SrcFix_DstInc }, + { PDMA_I2C4_RX, eMemCtl_SrcFix_DstInc }, + { PDMA_I2C5_RX, eMemCtl_SrcFix_DstInc }, + + { PDMA_I2S0_RX, eMemCtl_SrcFix_DstInc }, + { PDMA_I2S1_RX, eMemCtl_SrcFix_DstInc }, + +}; +#define NU_PERIPHERAL_SIZE ( sizeof(g_nu_pdma_peripheral_ctl_pool) / sizeof(g_nu_pdma_peripheral_ctl_pool[0]) ) + +static struct nu_pdma_memfun_actor nu_pdma_memfun_actor_arr[NU_PDMA_MEMFUN_ACTOR_MAX]; + +static int nu_pdma_check_is_nonallocated(uint32_t u32ChnId) +{ + uint32_t mod_idx = NU_PDMA_GET_MOD_IDX(u32ChnId); + RT_ASSERT(mod_idx < PDMA_CNT); + return !(nu_pdma_chn_mask_arr[mod_idx] & (1 << NU_PDMA_GET_MOD_CHIDX(u32ChnId))); +} + +static int nu_pdma_peripheral_set(uint32_t u32PeriphType) +{ + int idx = 0; + + while (idx < NU_PERIPHERAL_SIZE) + { + if (g_nu_pdma_peripheral_ctl_pool[idx].m_u32Peripheral == u32PeriphType) + return idx; + idx++; + } + + // Not such peripheral + return -1; +} + +static void nu_pdma_periph_ctrl_fill(int i32ChannID, int i32CtlPoolIdx) +{ + nu_pdma_chn_t *psPdmaChann = &nu_pdma_chn_arr[i32ChannID - NU_PDMA_CH_Pos]; + psPdmaChann->m_spPeripCtl.m_u32Peripheral = g_nu_pdma_peripheral_ctl_pool[i32CtlPoolIdx].m_u32Peripheral; + psPdmaChann->m_spPeripCtl.m_eMemCtl = g_nu_pdma_peripheral_ctl_pool[i32CtlPoolIdx].m_eMemCtl; +} + +/** + * Hardware PDMA Initialization + */ +static void nu_pdma_init(void) +{ + int i; + + if (nu_pdma_inited) + return; + + rt_memset(nu_pdma_chn_arr, 0x00, NU_PDMA_CH_MAX * sizeof(nu_pdma_chn_t)); + + for (i = (PDMA_START + 1); i < PDMA_CNT; i++) + { + nu_pdma_chn_mask_arr[i] = ~(NU_PDMA_CH_Msk); + + nu_sys_ip_reset(nu_pdma_arr[i].u32RstId); + + /* Initialize PDMA setting */ + PDMA_Open((PDMA_T *)nu_pdma_arr[i].m_pvBase, PDMA_CH_Msk); + + PDMA_Close((PDMA_T *)nu_pdma_arr[i].m_pvBase); + + /* Register PDMA ISR */ + rt_hw_interrupt_install(nu_pdma_arr[i].eIRQn, nu_pdma_isr, nu_pdma_arr[i].m_pvBase, nu_pdma_arr[i].name); + rt_hw_interrupt_umask(nu_pdma_arr[i].eIRQn); + } + + nu_pdma_inited = 1; +} + +static inline void nu_pdma_channel_enable(int i32ChannID) +{ + PDMA_T *PDMA = NU_PDMA_GET_BASE(i32ChannID); + int u32ModChannId = NU_PDMA_GET_MOD_CHIDX(i32ChannID); + + /* Clean descriptor table control register. */ + PDMA->DSCT[u32ModChannId].CTL = 0UL; + + /* Enable the channel */ + PDMA->CHCTL |= (1 << u32ModChannId); +} + +static inline void nu_pdma_channel_disable(int i32ChannID) +{ + PDMA_T *PDMA = NU_PDMA_GET_BASE(i32ChannID); + PDMA->CHCTL &= ~(1 << NU_PDMA_GET_MOD_CHIDX(i32ChannID)); +} + +static inline void nu_pdma_channel_reset(int i32ChannID) +{ + PDMA_T *PDMA = NU_PDMA_GET_BASE(i32ChannID); + int u32ModChannId = NU_PDMA_GET_MOD_CHIDX(i32ChannID); + + PDMA->CHRST = (1 << u32ModChannId); + + /* Wait for cleared channel CHCTL. */ + while ((PDMA->CHCTL & (1 << u32ModChannId))); +} + +void nu_pdma_channel_terminate(int i32ChannID) +{ + if (nu_pdma_check_is_nonallocated(i32ChannID)) + goto exit_pdma_channel_terminate; + + /* Reset specified channel. */ + nu_pdma_channel_reset(i32ChannID); + + /* Enable specified channel after reset. */ + nu_pdma_channel_enable(i32ChannID); + +exit_pdma_channel_terminate: + + return; +} + +static rt_err_t nu_pdma_timeout_set(int i32ChannID, int i32Timeout_us) +{ + rt_err_t ret = RT_EINVAL; + PDMA_T *PDMA = NULL; + uint32_t u32ModChannId; + + if (nu_pdma_check_is_nonallocated(i32ChannID)) + goto exit_nu_pdma_timeout_set; + + PDMA = NU_PDMA_GET_BASE(i32ChannID); + + u32ModChannId = NU_PDMA_GET_MOD_CHIDX(i32ChannID); + + nu_pdma_chn_arr[i32ChannID - NU_PDMA_CH_Pos].m_u32IdleTimeout_us = i32Timeout_us; + + if (i32Timeout_us) + { + uint32_t u32ToClk_Max = 1000000ul / (CLK_GetSYSCLK1Freq() / (1 << 8)); + uint32_t u32Divider = (i32Timeout_us / u32ToClk_Max) / (1 << 16); + uint32_t u32TOutCnt = (i32Timeout_us / u32ToClk_Max) % (1 << 16); + + PDMA_DisableTimeout(PDMA, 1 << u32ModChannId); + PDMA_EnableInt(PDMA, u32ModChannId, PDMA_INT_TIMEOUT); // Interrupt type + + if (u32Divider > 7) + { + u32Divider = 7; + u32TOutCnt = (1 << 16) - 1; + } + + if (u32ModChannId < 8) + PDMA->TOUTPSC = (PDMA->TOUTPSC & ~(0x7ul << (PDMA_TOUTPSC_TOUTPSC1_Pos * u32ModChannId))) | (u32Divider << (PDMA_TOUTPSC_TOUTPSC1_Pos * u32ModChannId)); + else + PDMA->TOUTPSC1 = (PDMA->TOUTPSC1 & ~(0x7ul << (PDMA_TOUTPSC_TOUTPSC1_Pos * u32ModChannId))) | (u32Divider << (PDMA_TOUTPSC_TOUTPSC1_Pos * u32ModChannId)); + + //rt_kprintf("[%d]HCLK=%d, u32Divider=%d, u32TOutCnt=%d\n", i32Timeout_us, CLK_GetSYSCLK1Freq(), u32Divider, u32TOutCnt ); + + PDMA_SetTimeOut(PDMA, u32ModChannId, 1, u32TOutCnt); + + ret = RT_EOK; + } + else + { + PDMA_DisableInt(PDMA, u32ModChannId, PDMA_INT_TIMEOUT); // Interrupt type + PDMA_DisableTimeout(PDMA, 1 << u32ModChannId); + } + +exit_nu_pdma_timeout_set: + + return -(ret); +} + +int nu_pdma_channel_allocate(int32_t i32PeripType) +{ + int ChnId, i32PeripCtlIdx, j; + + nu_pdma_init(); + + if ((i32PeripCtlIdx = nu_pdma_peripheral_set(i32PeripType)) < 0) + goto exit_nu_pdma_channel_allocate; + + for (j = (PDMA_START + 1); j < PDMA_CNT; j++) + { + /* Find the position of first '0' in nu_pdma_chn_mask_arr[j]. */ + ChnId = nu_cto(nu_pdma_chn_mask_arr[j]); + if (ChnId < PDMA_CH_MAX) + { + nu_pdma_chn_mask_arr[j] |= (1 << ChnId); + ChnId += (j * PDMA_CH_MAX); + rt_memset(nu_pdma_chn_arr + ChnId - NU_PDMA_CH_Pos, 0x00, sizeof(nu_pdma_chn_t)); + + /* Set idx number of g_nu_pdma_peripheral_ctl_pool */ + nu_pdma_periph_ctrl_fill(ChnId, i32PeripCtlIdx); + + /* Reset channel */ + nu_pdma_channel_terminate(ChnId); + + return ChnId; + } + } + +exit_nu_pdma_channel_allocate: + // No channel available + return -(RT_ERROR); +} + +rt_err_t nu_pdma_channel_free(int i32ChannID) +{ + rt_err_t ret = RT_EINVAL; + + if (! nu_pdma_inited) + goto exit_nu_pdma_channel_free; + + if (nu_pdma_check_is_nonallocated(i32ChannID)) + goto exit_nu_pdma_channel_free; + + if ((i32ChannID < NU_PDMA_CH_MAX) && (i32ChannID >= NU_PDMA_CH_Pos)) + { + nu_pdma_chn_mask_arr[NU_PDMA_GET_MOD_IDX(i32ChannID)] &= ~(1 << NU_PDMA_GET_MOD_CHIDX(i32ChannID)); + nu_pdma_channel_disable(i32ChannID); + ret = RT_EOK; + } +exit_nu_pdma_channel_free: + + return -(ret); +} + +rt_err_t nu_pdma_filtering_set(int i32ChannID, uint32_t u32EventFilter) +{ + rt_err_t ret = RT_EINVAL; + if (nu_pdma_check_is_nonallocated(i32ChannID)) + goto exit_nu_pdma_filtering_set; + + nu_pdma_chn_arr[i32ChannID - NU_PDMA_CH_Pos].m_u32EventFilter = u32EventFilter; + + ret = RT_EOK; + +exit_nu_pdma_filtering_set: + + return -(ret) ; +} + +uint32_t nu_pdma_filtering_get(int i32ChannID) +{ + if (nu_pdma_check_is_nonallocated(i32ChannID)) + goto exit_nu_pdma_filtering_get; + + return nu_pdma_chn_arr[i32ChannID - NU_PDMA_CH_Pos].m_u32EventFilter; + +exit_nu_pdma_filtering_get: + + return 0; +} + +rt_err_t nu_pdma_callback_register(int i32ChannID, nu_pdma_chn_cb_t psChnCb) +{ + rt_err_t ret = RT_EINVAL; + nu_pdma_chn_cb_t psChnCb_Current = RT_NULL; + + RT_ASSERT(psChnCb != RT_NULL); + + if (nu_pdma_check_is_nonallocated(i32ChannID)) + goto exit_nu_pdma_callback_register; + + switch (psChnCb->m_eCBType) + { + case eCBType_Event: + psChnCb_Current = &nu_pdma_chn_arr[i32ChannID - NU_PDMA_CH_Pos].m_sCB_Event; + break; + case eCBType_Trigger: + psChnCb_Current = &nu_pdma_chn_arr[i32ChannID - NU_PDMA_CH_Pos].m_sCB_Trigger; + break; + case eCBType_Disable: + psChnCb_Current = &nu_pdma_chn_arr[i32ChannID - NU_PDMA_CH_Pos].m_sCB_Disable; + break; + default: + goto exit_nu_pdma_callback_register; + } + + psChnCb_Current->m_pfnCBHandler = psChnCb->m_pfnCBHandler; + psChnCb_Current->m_pvUserData = psChnCb->m_pvUserData; + + ret = RT_EOK; + +exit_nu_pdma_callback_register: + + return -(ret) ; +} + +nu_pdma_cb_handler_t nu_pdma_callback_hijack(int i32ChannID, nu_pdma_cbtype_t eCBType, nu_pdma_chn_cb_t psChnCb_Hijack) +{ + nu_pdma_chn_cb_t psChnCb_Current = RT_NULL; + struct nu_pdma_chn_cb sChnCB_Tmp; + + RT_ASSERT(psChnCb_Hijack != NULL); + + sChnCB_Tmp.m_pfnCBHandler = RT_NULL; + + if (nu_pdma_check_is_nonallocated(i32ChannID)) + goto exit_nu_pdma_callback_hijack; + + switch (eCBType) + { + case eCBType_Event: + psChnCb_Current = &nu_pdma_chn_arr[i32ChannID - NU_PDMA_CH_Pos].m_sCB_Event; + break; + case eCBType_Trigger: + psChnCb_Current = &nu_pdma_chn_arr[i32ChannID - NU_PDMA_CH_Pos].m_sCB_Trigger; + break; + case eCBType_Disable: + psChnCb_Current = &nu_pdma_chn_arr[i32ChannID - NU_PDMA_CH_Pos].m_sCB_Disable; + break; + default: + goto exit_nu_pdma_callback_hijack; + } + + /* Backup */ + sChnCB_Tmp.m_pfnCBHandler = psChnCb_Current->m_pfnCBHandler; + sChnCB_Tmp.m_pvUserData = psChnCb_Current->m_pvUserData; + + /* Update */ + psChnCb_Current->m_pfnCBHandler = psChnCb_Hijack->m_pfnCBHandler; + psChnCb_Current->m_pvUserData = psChnCb_Hijack->m_pvUserData; + + /* Restore */ + psChnCb_Hijack->m_pfnCBHandler = sChnCB_Tmp.m_pfnCBHandler; + psChnCb_Hijack->m_pvUserData = sChnCB_Tmp.m_pvUserData; + +exit_nu_pdma_callback_hijack: + + return sChnCB_Tmp.m_pfnCBHandler; +} + +static int nu_pdma_non_transfer_count_get(int32_t i32ChannID) +{ + PDMA_T *PDMA = NU_PDMA_GET_BASE(i32ChannID); + return ((PDMA->DSCT[NU_PDMA_GET_MOD_CHIDX(i32ChannID)].CTL & PDMA_DSCT_CTL_TXCNT_Msk) >> PDMA_DSCT_CTL_TXCNT_Pos) + 1; +} + +int nu_pdma_transferred_byte_get(int32_t i32ChannID, int32_t i32TriggerByteLen) +{ + int i32BitWidth = 0; + int cur_txcnt = 0; + PDMA_T *PDMA; + + if (nu_pdma_check_is_nonallocated(i32ChannID)) + goto exit_nu_pdma_transferred_byte_get; + + PDMA = NU_PDMA_GET_BASE(i32ChannID); + + if ((PDMA->DSCT[NU_PDMA_GET_MOD_CHIDX(i32ChannID)].CTL & PDMA_DSCT_CTL_OPMODE_Msk) != PDMA_OP_SCATTER) + { + i32BitWidth = PDMA->DSCT[NU_PDMA_GET_MOD_CHIDX(i32ChannID)].CTL & PDMA_DSCT_CTL_TXWIDTH_Msk; + i32BitWidth = (i32BitWidth == PDMA_WIDTH_8) ? 1 : (i32BitWidth == PDMA_WIDTH_16) ? 2 : (i32BitWidth == PDMA_WIDTH_32) ? 4 : 0; + + cur_txcnt = nu_pdma_non_transfer_count_get(i32ChannID); + + // rt_kprintf("\n[%s] %d %d %02x\n", __func__, i32ChannID, cur_txcnt, (PDMA->DSCT[NU_PDMA_GET_MOD_CHIDX(i32ChannID)].CTL & PDMA_DSCT_CTL_OPMODE_Msk) ); + + return (i32TriggerByteLen - (cur_txcnt) * i32BitWidth); + } + + // rt_kprintf("\n@@@@ %d %02x @@@@\n", i32ChannID, PDMA->DSCT[NU_PDMA_GET_MOD_CHIDX(i32ChannID)].CTL & PDMA_DSCT_CTL_OPMODE_Msk); + + return 0; + +exit_nu_pdma_transferred_byte_get: + + return -1; +} + +nu_pdma_memctrl_t nu_pdma_channel_memctrl_get(int i32ChannID) +{ + nu_pdma_memctrl_t eMemCtrl = eMemCtl_Undefined; + + if (nu_pdma_check_is_nonallocated(i32ChannID)) + goto exit_nu_pdma_channel_memctrl_get; + + eMemCtrl = nu_pdma_chn_arr[i32ChannID - NU_PDMA_CH_Pos].m_spPeripCtl.m_eMemCtl; + +exit_nu_pdma_channel_memctrl_get: + + return eMemCtrl; +} + +rt_err_t nu_pdma_channel_memctrl_set(int i32ChannID, nu_pdma_memctrl_t eMemCtrl) +{ + rt_err_t ret = RT_EINVAL; + nu_pdma_chn_t *psPdmaChann = &nu_pdma_chn_arr[i32ChannID - NU_PDMA_CH_Pos]; + + if (nu_pdma_check_is_nonallocated(i32ChannID)) + goto exit_nu_pdma_channel_memctrl_set; + else if ((eMemCtrl < eMemCtl_SrcFix_DstFix) || (eMemCtrl > eMemCtl_SrcInc_DstInc)) + goto exit_nu_pdma_channel_memctrl_set; + + /* PDMA_MEM/SAR_FIX/BURST mode is not supported. */ + if ((psPdmaChann->m_spPeripCtl.m_u32Peripheral == PDMA_MEM) && + ((eMemCtrl == eMemCtl_SrcFix_DstInc) || (eMemCtrl == eMemCtl_SrcFix_DstFix))) + goto exit_nu_pdma_channel_memctrl_set; + + nu_pdma_chn_arr[i32ChannID - NU_PDMA_CH_Pos].m_spPeripCtl.m_eMemCtl = eMemCtrl; + + ret = RT_EOK; + +exit_nu_pdma_channel_memctrl_set: + + return -(ret); +} + +static void nu_pdma_channel_memctrl_fill(nu_pdma_memctrl_t eMemCtl, uint32_t *pu32SrcCtl, uint32_t *pu32DstCtl) +{ + switch ((int)eMemCtl) + { + case eMemCtl_SrcFix_DstFix: + *pu32SrcCtl = PDMA_SAR_FIX; + *pu32DstCtl = PDMA_DAR_FIX; + break; + case eMemCtl_SrcFix_DstInc: + *pu32SrcCtl = PDMA_SAR_FIX; + *pu32DstCtl = PDMA_DAR_INC; + break; + case eMemCtl_SrcInc_DstFix: + *pu32SrcCtl = PDMA_SAR_INC; + *pu32DstCtl = PDMA_DAR_FIX; + break; + case eMemCtl_SrcInc_DstInc: + *pu32SrcCtl = PDMA_SAR_INC; + *pu32DstCtl = PDMA_DAR_INC; + break; + default: + break; + } +} + +/* This is for Scatter-gather DMA. */ +rt_err_t nu_pdma_desc_setup(int i32ChannID, nu_pdma_desc_t dma_desc, uint32_t u32DataWidth, uint32_t u32AddrSrc, + uint32_t u32AddrDst, int32_t i32TransferCnt, nu_pdma_desc_t next, uint32_t u32BeSilent) +{ + nu_pdma_periph_ctl_t *psPeriphCtl = NULL; + + uint32_t u32SrcCtl = 0; + uint32_t u32DstCtl = 0; + + rt_err_t ret = RT_EINVAL; + + if (!dma_desc) + goto exit_nu_pdma_desc_setup; + else if (nu_pdma_check_is_nonallocated(i32ChannID)) + goto exit_nu_pdma_desc_setup; + else if (!(u32DataWidth == 8 || u32DataWidth == 16 || u32DataWidth == 32)) + goto exit_nu_pdma_desc_setup; + else if ((u32AddrSrc % (u32DataWidth / 8)) || (u32AddrDst % (u32DataWidth / 8))) + goto exit_nu_pdma_desc_setup; + else if (i32TransferCnt > NU_PDMA_MAX_TXCNT) + goto exit_nu_pdma_desc_setup; + + psPeriphCtl = &nu_pdma_chn_arr[i32ChannID - NU_PDMA_CH_Pos].m_spPeripCtl; + + nu_pdma_channel_memctrl_fill(psPeriphCtl->m_eMemCtl, &u32SrcCtl, &u32DstCtl); + + dma_desc->CTL = ((i32TransferCnt - 1) << PDMA_DSCT_CTL_TXCNT_Pos) | + ((u32DataWidth == 8) ? PDMA_WIDTH_8 : (u32DataWidth == 16) ? PDMA_WIDTH_16 : PDMA_WIDTH_32) | + u32SrcCtl | + u32DstCtl | + PDMA_OP_BASIC; + + dma_desc->SA = u32AddrSrc; + dma_desc->DA = u32AddrDst; + dma_desc->NEXT = 0; /* Terminating node by default. */ + + if (psPeriphCtl->m_u32Peripheral == PDMA_MEM) + { + /* For M2M transfer */ + dma_desc->CTL |= (PDMA_REQ_BURST | PDMA_BURST_32); + } + else + { + /* For P2M and M2P transfer */ + dma_desc->CTL |= (PDMA_REQ_SINGLE); + } + + if (next) + { + /* Link to Next and modify to scatter-gather DMA mode. */ + dma_desc->CTL = (dma_desc->CTL & ~PDMA_DSCT_CTL_OPMODE_Msk) | PDMA_OP_SCATTER; + dma_desc->NEXT = (uint32_t)next; + + } + + /* Be silent */ + if (u32BeSilent) + dma_desc->CTL |= PDMA_DSCT_CTL_TBINTDIS_Msk; + + ret = RT_EOK; + +exit_nu_pdma_desc_setup: + + return -(ret); +} + +rt_err_t nu_pdma_sgtbls_allocate(nu_pdma_desc_t *ppsSgtbls, int num) +{ + int i; + nu_pdma_desc_t psSgTblHead; + + RT_ASSERT(ppsSgtbls != NULL); + RT_ASSERT(num > 0); + + psSgTblHead = (nu_pdma_desc_t) rt_malloc_align(RT_ALIGN(sizeof(DSCT_T) * num, 64), 64); + RT_ASSERT(psSgTblHead != RT_NULL); + + rt_memset((void *)psSgTblHead, 0, sizeof(DSCT_T) * num); + + for (i = 0; i < num; i++) + ppsSgtbls[i] = &psSgTblHead[i]; + + return RT_EOK; +} + +void nu_pdma_sgtbls_free(nu_pdma_desc_t *ppsSgtbls, int num) +{ + nu_pdma_desc_t psSgTblHead; + + RT_ASSERT(ppsSgtbls != NULL); + psSgTblHead = *ppsSgtbls; + RT_ASSERT(psSgTblHead != NULL); + + rt_free_align(psSgTblHead); +} + +static void _nu_pdma_transfer(int i32ChannID, uint32_t u32Peripheral, nu_pdma_desc_t head, uint32_t u32IdleTimeout_us) +{ + PDMA_T *PDMA = NU_PDMA_GET_BASE(i32ChannID); + nu_pdma_chn_t *psPdmaChann = &nu_pdma_chn_arr[i32ChannID - NU_PDMA_CH_Pos]; + +#if !defined(USE_MA35D1_SUBM) + /* Writeback data in dcache to memory before transferring. */ + { + static uint32_t bNonCacheAlignedWarning = 1; + nu_pdma_desc_t next = head; + int CACHE_LINE_SIZE = nu_cpu_dcache_line_size(); + while (next != RT_NULL) + { + uint32_t u32TxCnt = ((next->CTL & PDMA_DSCT_CTL_TXCNT_Msk) >> PDMA_DSCT_CTL_TXCNT_Pos) + 1; + uint32_t u32DataWidth = (1 << ((next->CTL & PDMA_DSCT_CTL_TXWIDTH_Msk) >> PDMA_DSCT_CTL_TXWIDTH_Pos)); + uint32_t u32SrcCtl = (next->CTL & PDMA_DSCT_CTL_SAINC_Msk); + uint32_t u32DstCtl = (next->CTL & PDMA_DSCT_CTL_DAINC_Msk); + uint32_t u32FlushLen = u32TxCnt * u32DataWidth; + +#if 0 + rt_kprintf("[%s] i32ChannID=%d\n", __func__, i32ChannID); + rt_kprintf("[%s] PDMA=0x%08x\n", __func__, (uint32_t)PDMA); + rt_kprintf("[%s] u32TxCnt=%d\n", __func__, u32TxCnt); + rt_kprintf("[%s] u32DataWidth=%d\n", __func__, u32DataWidth); + rt_kprintf("[%s] u32SrcCtl=0x%08x\n", __func__, u32SrcCtl); + rt_kprintf("[%s] u32DstCtl=0x%08x\n", __func__, u32DstCtl); + rt_kprintf("[%s] u32FlushLen=%d\n", __func__, u32FlushLen); +#endif + + /* Flush Src buffer into memory. */ + if ((u32SrcCtl == PDMA_SAR_INC)) // for M2P, M2M + rt_hw_cpu_dcache_clean_inv((void *)next->SA, u32FlushLen); + + /* Flush Dst buffer into memory. */ + if ((u32DstCtl == PDMA_DAR_INC)) // for P2M, M2M + rt_hw_cpu_dcache_clean_inv((void *)next->DA, u32FlushLen); + + /* Flush descriptor into memory */ + rt_hw_cpu_dcache_clean_inv((void *)next, sizeof(DSCT_T)); + + if (bNonCacheAlignedWarning) + { + if ((u32FlushLen & (CACHE_LINE_SIZE - 1)) || + (next->SA & (CACHE_LINE_SIZE - 1)) || + (next->DA & (CACHE_LINE_SIZE - 1)) || + ((rt_uint32_t)next & (CACHE_LINE_SIZE - 1))) + { + /* + Race-condition avoidance between DMA-transferring and DCache write-back: + Source, destination, DMA descriptor address and length should be aligned at len(CACHE_LINE_SIZE) + */ + bNonCacheAlignedWarning = 0; + rt_kprintf("[PDMA-W]\n"); + } + } + + next = (nu_pdma_desc_t)next->NEXT; + + if (next == head) break; + } + } +#endif + + PDMA_DisableTimeout(PDMA, 1 << NU_PDMA_GET_MOD_CHIDX(i32ChannID)); + + PDMA_EnableInt(PDMA, NU_PDMA_GET_MOD_CHIDX(i32ChannID), PDMA_INT_TRANS_DONE); + + nu_pdma_timeout_set(i32ChannID, u32IdleTimeout_us); + + /* Set scatter-gather mode and head */ + /* Take care the head structure, you should make sure cache-coherence. */ + PDMA_SetTransferMode(PDMA, + NU_PDMA_GET_MOD_CHIDX(i32ChannID), + u32Peripheral, + (head->NEXT != 0) ? 1 : 0, + (uint32_t)head); + + /* If peripheral is M2M, trigger it. */ + if (u32Peripheral == PDMA_MEM) + { + PDMA_Trigger(PDMA, NU_PDMA_GET_MOD_CHIDX(i32ChannID)); + } + else if (psPdmaChann->m_sCB_Trigger.m_pfnCBHandler) + { + psPdmaChann->m_sCB_Trigger.m_pfnCBHandler(psPdmaChann->m_sCB_Trigger.m_pvUserData, psPdmaChann->m_sCB_Trigger.m_u32Reserved); + } +} + +static void _nu_pdma_free_sgtbls(nu_pdma_chn_t *psPdmaChann) +{ + if (psPdmaChann->m_ppsSgtbl) + { + nu_pdma_sgtbls_free(psPdmaChann->m_ppsSgtbl, psPdmaChann->m_u32WantedSGTblNum); + rt_free_align((void *)psPdmaChann->m_ppsSgtbl); + psPdmaChann->m_ppsSgtbl = RT_NULL; + psPdmaChann->m_u32WantedSGTblNum = 0; + } +} + +static rt_err_t _nu_pdma_transfer_chain(int i32ChannID, uint32_t u32DataWidth, uint32_t u32AddrSrc, uint32_t u32AddrDst, uint32_t u32TransferCnt, uint32_t u32IdleTimeout_us) +{ + int i = 0; + rt_err_t ret = RT_ERROR; + nu_pdma_periph_ctl_t *psPeriphCtl = NULL; + nu_pdma_chn_t *psPdmaChann = &nu_pdma_chn_arr[i32ChannID - NU_PDMA_CH_Pos]; + + nu_pdma_memctrl_t eMemCtl = nu_pdma_channel_memctrl_get(i32ChannID); + + rt_uint32_t u32Offset = 0; + rt_uint32_t u32TxCnt = 0; + + psPeriphCtl = &psPdmaChann->m_spPeripCtl; + + if (psPdmaChann->m_u32WantedSGTblNum != (u32TransferCnt / NU_PDMA_MAX_TXCNT + 1)) + { + if (psPdmaChann->m_u32WantedSGTblNum > 0) + _nu_pdma_free_sgtbls(psPdmaChann); + + psPdmaChann->m_u32WantedSGTblNum = u32TransferCnt / NU_PDMA_MAX_TXCNT + 1; + + psPdmaChann->m_ppsSgtbl = (nu_pdma_desc_t *)rt_malloc_align(sizeof(nu_pdma_desc_t) * psPdmaChann->m_u32WantedSGTblNum, 4); + if (!psPdmaChann->m_ppsSgtbl) + goto exit__nu_pdma_transfer_chain; + + ret = nu_pdma_sgtbls_allocate(psPdmaChann->m_ppsSgtbl, psPdmaChann->m_u32WantedSGTblNum); + if (ret != RT_EOK) + goto exit__nu_pdma_transfer_chain; + } + + for (i = 0; i < psPdmaChann->m_u32WantedSGTblNum; i++) + { + u32TxCnt = (u32TransferCnt > NU_PDMA_MAX_TXCNT) ? NU_PDMA_MAX_TXCNT : u32TransferCnt; + + ret = nu_pdma_desc_setup(i32ChannID, + psPdmaChann->m_ppsSgtbl[i], + u32DataWidth, + (eMemCtl & 0x2ul) ? u32AddrSrc + u32Offset : u32AddrSrc, /* Src address is Inc or not. */ + (eMemCtl & 0x1ul) ? u32AddrDst + u32Offset : u32AddrDst, /* Dst address is Inc or not. */ + u32TxCnt, + ((i + 1) == psPdmaChann->m_u32WantedSGTblNum) ? RT_NULL : psPdmaChann->m_ppsSgtbl[i + 1], + ((i + 1) == psPdmaChann->m_u32WantedSGTblNum) ? 0 : 1); // Silent, w/o TD interrupt + + if (ret != RT_EOK) + goto exit__nu_pdma_transfer_chain; + + u32TransferCnt -= u32TxCnt; + u32Offset += (u32TxCnt * u32DataWidth / 8); + } + + _nu_pdma_transfer(i32ChannID, psPeriphCtl->m_u32Peripheral, psPdmaChann->m_ppsSgtbl[0], u32IdleTimeout_us); + + ret = RT_EOK; + + return ret; + +exit__nu_pdma_transfer_chain: + + _nu_pdma_free_sgtbls(psPdmaChann); + + return -(ret); +} + +rt_err_t nu_pdma_transfer(int i32ChannID, uint32_t u32DataWidth, uint32_t u32AddrSrc, uint32_t u32AddrDst, uint32_t u32TransferCnt, uint32_t u32IdleTimeout_us) +{ + rt_err_t ret = RT_EINVAL; + PDMA_T *PDMA = NU_PDMA_GET_BASE(i32ChannID); + nu_pdma_desc_t head; + nu_pdma_chn_t *psPdmaChann; + + nu_pdma_periph_ctl_t *psPeriphCtl = NULL; + + if (nu_pdma_check_is_nonallocated(i32ChannID)) + goto exit_nu_pdma_transfer; + else if (!u32TransferCnt) + goto exit_nu_pdma_transfer; + else if (u32TransferCnt > NU_PDMA_MAX_TXCNT) + return _nu_pdma_transfer_chain(i32ChannID, u32DataWidth, u32AddrSrc, u32AddrDst, u32TransferCnt, u32IdleTimeout_us); + + psPdmaChann = &nu_pdma_chn_arr[i32ChannID - NU_PDMA_CH_Pos]; + psPeriphCtl = &psPdmaChann->m_spPeripCtl; + + head = &PDMA->DSCT[NU_PDMA_GET_MOD_CHIDX(i32ChannID)]; + + ret = nu_pdma_desc_setup(i32ChannID, + head, + u32DataWidth, + u32AddrSrc, + u32AddrDst, + u32TransferCnt, + RT_NULL, + 0); + if (ret != RT_EOK) + goto exit_nu_pdma_transfer; + + _nu_pdma_transfer(i32ChannID, psPeriphCtl->m_u32Peripheral, head, u32IdleTimeout_us); + + ret = RT_EOK; + +exit_nu_pdma_transfer: + + return -(ret); +} + +rt_err_t nu_pdma_sg_transfer(int i32ChannID, nu_pdma_desc_t head, uint32_t u32IdleTimeout_us) +{ + rt_err_t ret = RT_EINVAL; + nu_pdma_periph_ctl_t *psPeriphCtl = NULL; + + if (!head) + goto exit_nu_pdma_sg_transfer; + else if (nu_pdma_check_is_nonallocated(i32ChannID)) + goto exit_nu_pdma_sg_transfer; + + psPeriphCtl = &nu_pdma_chn_arr[i32ChannID - NU_PDMA_CH_Pos].m_spPeripCtl; + + _nu_pdma_transfer(i32ChannID, psPeriphCtl->m_u32Peripheral, head, u32IdleTimeout_us); + + ret = RT_EOK; + +exit_nu_pdma_sg_transfer: + + return -(ret); +} + +static void nu_pdma_isr(int vector, void *pvdata) +{ + int i; + PDMA_T *PDMA = (void *)pvdata; + + uint32_t intsts = PDMA_GET_INT_STATUS(PDMA); + uint32_t abtsts = PDMA_GET_ABORT_STS(PDMA); + uint32_t tdsts = PDMA_GET_TD_STS(PDMA); + uint32_t unalignsts = PDMA_GET_ALIGN_STS(PDMA); + uint32_t reqto = intsts & PDMA_INTSTS_REQTOFn_Msk; + uint32_t reqto_ch = (reqto >> PDMA_INTSTS_REQTOFn_Pos); + + int allch_sts = (reqto_ch | tdsts | abtsts | unalignsts); + + // Abort + if (intsts & PDMA_INTSTS_ABTIF_Msk) + { + // Clear all Abort flags + PDMA_CLR_ABORT_FLAG(PDMA, abtsts); + } + + // Transfer done + if (intsts & PDMA_INTSTS_TDIF_Msk) + { + // Clear all transfer done flags + PDMA_CLR_TD_FLAG(PDMA, tdsts); + } + + // Unaligned + if (intsts & PDMA_INTSTS_ALIGNF_Msk) + { + // Clear all Unaligned flags + PDMA_CLR_ALIGN_FLAG(PDMA, unalignsts); + } + + // Timeout + if (reqto) + { + // Clear all Timeout flags + PDMA->INTSTS = reqto; + } + + // Find the position of first '1' in allch_sts. + while ((i = nu_ctz(allch_sts)) < PDMA_CH_MAX) + { + int module_id = ((uint32_t)PDMA - DEF_PDMA_BASE_START) / 0x10000UL; + int j = i + (module_id * PDMA_CH_MAX); + int ch_mask = (1 << i); + + if (nu_pdma_chn_mask_arr[module_id] & ch_mask) + { + int ch_event = 0; + nu_pdma_chn_t *dma_chn = nu_pdma_chn_arr + j - NU_PDMA_CH_Pos; + + if (dma_chn->m_sCB_Event.m_pfnCBHandler) + { + if (abtsts & ch_mask) + { + ch_event |= NU_PDMA_EVENT_ABORT; + } + + if (tdsts & ch_mask) + { + ch_event |= NU_PDMA_EVENT_TRANSFER_DONE; + } + + if (unalignsts & ch_mask) + { + ch_event |= NU_PDMA_EVENT_ALIGNMENT; + } + + if (reqto_ch & ch_mask) + { + PDMA_DisableTimeout(PDMA, ch_mask); + ch_event |= NU_PDMA_EVENT_TIMEOUT; + } + + if (dma_chn->m_sCB_Disable.m_pfnCBHandler) + dma_chn->m_sCB_Disable.m_pfnCBHandler(dma_chn->m_sCB_Disable.m_pvUserData, dma_chn->m_sCB_Disable.m_u32Reserved); + + if ((dma_chn->m_u32EventFilter & ch_event) && dma_chn->m_sCB_Event.m_pfnCBHandler) + dma_chn->m_sCB_Event.m_pfnCBHandler(dma_chn->m_sCB_Event.m_pvUserData, ch_event); + + if (reqto_ch & ch_mask) + nu_pdma_timeout_set(j, nu_pdma_chn_arr[j - NU_PDMA_CH_Pos].m_u32IdleTimeout_us); + + }//if(dma_chn->handler) + + } //if (nu_pdma_chn_mask & ch_mask) + + // Clear the served bit. + allch_sts &= ~ch_mask; + + } //while +} + +static void nu_pdma_memfun_actor_init(void) +{ + int i = 0 ; + nu_pdma_init(); + for (i = 0; i < NU_PDMA_MEMFUN_ACTOR_MAX; i++) + { + rt_memset(&nu_pdma_memfun_actor_arr[i], 0, sizeof(struct nu_pdma_memfun_actor)); + if (-(RT_ERROR) != (nu_pdma_memfun_actor_arr[i].m_i32ChannID = nu_pdma_channel_allocate(PDMA_MEM))) + { + nu_pdma_memfun_actor_arr[i].m_psSemMemFun = rt_sem_create("memactor_sem", 0, RT_IPC_FLAG_FIFO); + RT_ASSERT(nu_pdma_memfun_actor_arr[i].m_psSemMemFun != RT_NULL); + } + else + break; + } + if (i) + { + nu_pdma_memfun_actor_maxnum = i; + nu_pdma_memfun_actor_mask = ~(((1 << i) - 1)); + + nu_pdma_memfun_actor_pool_sem = rt_sem_create("mempool_sem", nu_pdma_memfun_actor_maxnum, RT_IPC_FLAG_FIFO); + RT_ASSERT(nu_pdma_memfun_actor_pool_sem != RT_NULL); + + nu_pdma_memfun_actor_pool_lock = rt_mutex_create("mempool_lock", RT_IPC_FLAG_PRIO); + RT_ASSERT(nu_pdma_memfun_actor_pool_lock != RT_NULL); + } +} + +static void nu_pdma_memfun_cb(void *pvUserData, uint32_t u32Events) +{ + rt_err_t result = RT_EOK; + + nu_pdma_memfun_actor_t psMemFunActor = (nu_pdma_memfun_actor_t)pvUserData; + psMemFunActor->m_u32Result = u32Events; + + result = rt_sem_release(psMemFunActor->m_psSemMemFun); + RT_ASSERT(result == RT_EOK); +} + +static int nu_pdma_memfun_employ(void) +{ + int idx = -1 ; + rt_err_t result = RT_EOK; + + /* Headhunter */ + if (nu_pdma_memfun_actor_pool_sem && + ((result = rt_sem_take(nu_pdma_memfun_actor_pool_sem, RT_WAITING_FOREVER)) == RT_EOK)) + { + RT_ASSERT(result == RT_EOK); + + result = rt_mutex_take(nu_pdma_memfun_actor_pool_lock, RT_WAITING_FOREVER); + RT_ASSERT(result == RT_EOK); + + /* Find the position of first '0' in nu_pdma_memfun_actor_mask. */ + idx = nu_cto(nu_pdma_memfun_actor_mask); + if (idx != 32) + { + nu_pdma_memfun_actor_mask |= (1 << idx); + } + else + { + idx = -1; + } + result = rt_mutex_release(nu_pdma_memfun_actor_pool_lock); + RT_ASSERT(result == RT_EOK); + } + + return idx; +} + +static rt_size_t nu_pdma_memfun(void *dest, void *src, uint32_t u32DataWidth, unsigned int u32TransferCnt, nu_pdma_memctrl_t eMemCtl) +{ + nu_pdma_memfun_actor_t psMemFunActor = NULL; + struct nu_pdma_chn_cb sChnCB; + rt_err_t result = RT_ERROR; + + int idx; + rt_size_t ret = 0; + + /* Employ actor */ + while ((idx = nu_pdma_memfun_employ()) < 0); + + psMemFunActor = &nu_pdma_memfun_actor_arr[idx]; + + /* Set PDMA memory control to eMemCtl. */ + nu_pdma_channel_memctrl_set(psMemFunActor->m_i32ChannID, eMemCtl); + + /* Register ISR callback function */ + sChnCB.m_eCBType = eCBType_Event; + sChnCB.m_pfnCBHandler = nu_pdma_memfun_cb; + sChnCB.m_pvUserData = (void *)psMemFunActor; + + nu_pdma_filtering_set(psMemFunActor->m_i32ChannID, NU_PDMA_EVENT_ABORT | NU_PDMA_EVENT_TRANSFER_DONE); + nu_pdma_callback_register(psMemFunActor->m_i32ChannID, &sChnCB); + + psMemFunActor->m_u32Result = 0; + + /* Trigger it */ + nu_pdma_transfer(psMemFunActor->m_i32ChannID, + u32DataWidth, + (uint32_t)src, + (uint32_t)dest, + u32TransferCnt, + 0); + + /* Wait it done. */ + result = rt_sem_take(psMemFunActor->m_psSemMemFun, RT_WAITING_FOREVER); + RT_ASSERT(result == RT_EOK); + + /* Give result if get NU_PDMA_EVENT_TRANSFER_DONE.*/ + if (psMemFunActor->m_u32Result & NU_PDMA_EVENT_TRANSFER_DONE) + { + ret += u32TransferCnt; + } + else + { + ret += (u32TransferCnt - nu_pdma_non_transfer_count_get(psMemFunActor->m_i32ChannID)); + } + + /* Terminate it if get ABORT event */ + if (psMemFunActor->m_u32Result & NU_PDMA_EVENT_ABORT) + { + nu_pdma_channel_terminate(psMemFunActor->m_i32ChannID); + } + + result = rt_mutex_take(nu_pdma_memfun_actor_pool_lock, RT_WAITING_FOREVER); + RT_ASSERT(result == RT_EOK); + + nu_pdma_memfun_actor_mask &= ~(1 << idx); + + result = rt_mutex_release(nu_pdma_memfun_actor_pool_lock); + RT_ASSERT(result == RT_EOK); + + /* Fire actor */ + result = rt_sem_release(nu_pdma_memfun_actor_pool_sem); + RT_ASSERT(result == RT_EOK); + + return ret; +} + +rt_size_t nu_pdma_mempush(void *dest, void *src, uint32_t data_width, unsigned int transfer_count) +{ + if (data_width == 8 || data_width == 16 || data_width == 32) + return nu_pdma_memfun(dest, src, data_width, transfer_count, eMemCtl_SrcInc_DstFix); + return 0; +} + +void *nu_pdma_memcpy(void *dest, void *src, unsigned int count) +{ + int i = 0; + uint32_t u32Offset = 0; + uint32_t u32Remaining = count; + + for (i = 4; (i > 0) && (u32Remaining > 0) ; i >>= 1) + { + uint32_t u32src = (uint32_t)src + u32Offset; + uint32_t u32dest = (uint32_t)dest + u32Offset; + + if (((u32src % i) == (u32dest % i)) && + ((u32src % i) == 0) && + (RT_ALIGN_DOWN(u32Remaining, i) >= i)) + { + uint32_t u32TXCnt = u32Remaining / i; + if (u32TXCnt != nu_pdma_memfun((void *)u32dest, (void *)u32src, i * 8, u32TXCnt, eMemCtl_SrcInc_DstInc)) + goto exit_nu_pdma_memcpy; + + u32Offset += (u32TXCnt * i); + u32Remaining -= (u32TXCnt * i); + } + } + + if (count == u32Offset) + return dest; + +exit_nu_pdma_memcpy: + + return NULL; +} + +/** + * PDMA memfun actor initialization + */ +int rt_hw_pdma_memfun_init(void) +{ + nu_pdma_memfun_actor_init(); + return 0; +} +INIT_DEVICE_EXPORT(rt_hw_pdma_memfun_init); +#endif // #if defined(BSP_USING_PDMA) diff --git a/bsp/nuvoton/libraries/ma35/rtt_port/drv_pdma.h b/bsp/nuvoton/libraries/ma35/rtt_port/drv_pdma.h new file mode 100644 index 0000000000..1267dcb9fa --- /dev/null +++ b/bsp/nuvoton/libraries/ma35/rtt_port/drv_pdma.h @@ -0,0 +1,87 @@ +/**************************************************************************//** +* +* @copyright (C) 2020 Nuvoton Technology Corp. All rights reserved. +* +* SPDX-License-Identifier: Apache-2.0 +* +* Change Logs: +* Date Author Notes +* 2020-2-7 Wayne First version +* +******************************************************************************/ + +#ifndef __DRV_PDMA_H__ +#define __DRV_PDMA_H__ + +#include +#include +#include "NuMicro.h" +#include + +#define NU_PDMA_CAP_NONE (0 << 0) + +#define NU_PDMA_EVENT_ABORT (1 << 0) +#define NU_PDMA_EVENT_TRANSFER_DONE (1 << 1) +#define NU_PDMA_EVENT_ALIGNMENT (1 << 2) +#define NU_PDMA_EVENT_TIMEOUT (1 << 3) +#define NU_PDMA_EVENT_ALL (NU_PDMA_EVENT_ABORT | NU_PDMA_EVENT_TRANSFER_DONE | NU_PDMA_EVENT_TIMEOUT) +#define NU_PDMA_EVENT_MASK NU_PDMA_EVENT_ALL +#define NU_PDMA_UNUSED (-1) + +#define NU_PDMA_SG_LIMITED_DISTANCE (BOARD_SDRAM_SIZE) +#define NU_PDMA_MAX_TXCNT ((PDMA_DSCT_CTL_TXCNT_Msk>>PDMA_DSCT_CTL_TXCNT_Pos) + 1) + +typedef enum +{ + eMemCtl_SrcFix_DstFix, + eMemCtl_SrcFix_DstInc, + eMemCtl_SrcInc_DstFix, + eMemCtl_SrcInc_DstInc, + eMemCtl_Undefined = (-1) +} nu_pdma_memctrl_t; + +typedef DSCT_T *nu_pdma_desc_t; + +typedef void (*nu_pdma_cb_handler_t)(void *, uint32_t); + +typedef enum +{ + eCBType_Event, + eCBType_Trigger, + eCBType_Disable, + eCBType_Undefined = (-1) +} nu_pdma_cbtype_t; + +struct nu_pdma_chn_cb +{ + nu_pdma_cbtype_t m_eCBType; + nu_pdma_cb_handler_t m_pfnCBHandler; + void *m_pvUserData; + uint32_t m_u32Reserved; +}; +typedef struct nu_pdma_chn_cb *nu_pdma_chn_cb_t; + +int nu_pdma_channel_allocate(int32_t i32PeripType); +rt_err_t nu_pdma_channel_free(int i32ChannID); +rt_err_t nu_pdma_callback_register(int i32ChannID, nu_pdma_chn_cb_t psChnCb); +rt_err_t nu_pdma_transfer(int i32ChannID, uint32_t u32DataWidth, uint32_t u32AddrSrc, uint32_t u32AddrDst, uint32_t i32TransferCnt, uint32_t u32IdleTimeout_us); +int nu_pdma_transferred_byte_get(int32_t i32ChannID, int32_t i32TriggerByteLen); +void nu_pdma_channel_terminate(int i32ChannID); +nu_pdma_memctrl_t nu_pdma_channel_memctrl_get(int i32ChannID); +rt_err_t nu_pdma_channel_memctrl_set(int i32ChannID, nu_pdma_memctrl_t eMemCtrl); + +nu_pdma_cb_handler_t nu_pdma_callback_hijack(int i32ChannID, nu_pdma_cbtype_t eCBType, nu_pdma_chn_cb_t psChnCb_Hijack); +rt_err_t nu_pdma_filtering_set(int i32ChannID, uint32_t u32EventFilter); +uint32_t nu_pdma_filtering_get(int i32ChannID); + +// For scatter-gather DMA +rt_err_t nu_pdma_desc_setup(int i32ChannID, nu_pdma_desc_t dma_desc, uint32_t u32DataWidth, uint32_t u32AddrSrc, uint32_t u32AddrDst, int32_t TransferCnt, nu_pdma_desc_t next, uint32_t u32BeSilent); +rt_err_t nu_pdma_sg_transfer(int i32ChannID, nu_pdma_desc_t head, uint32_t u32IdleTimeout_us); +rt_err_t nu_pdma_sgtbls_allocate(nu_pdma_desc_t *ppsSgtbls, int num); +void nu_pdma_sgtbls_free(nu_pdma_desc_t *ppsSgtbls, int num); + +// For memory actor +void *nu_pdma_memcpy(void *dest, void *src, unsigned int count); +rt_size_t nu_pdma_mempush(void *dest, void *src, uint32_t data_width, unsigned int transfer_count); + +#endif // __DRV_PDMA_H___ diff --git a/bsp/nuvoton/libraries/ma35/rtt_port/drv_qei.c b/bsp/nuvoton/libraries/ma35/rtt_port/drv_qei.c new file mode 100644 index 0000000000..023c70ac9a --- /dev/null +++ b/bsp/nuvoton/libraries/ma35/rtt_port/drv_qei.c @@ -0,0 +1,298 @@ +/**************************************************************************//** +* +* @copyright (C) 2020 Nuvoton Technology Corp. All rights reserved. +* +* SPDX-License-Identifier: Apache-2.0 +* +* Change Logs: +* Date Author Notes +* 2021-10-21 Wayne First version +* +******************************************************************************/ + +#include + +#if defined(BSP_USING_QEI) + +#include +#include "drv_sys.h" +#include "drv_common.h" + +/* Private define ---------------------------------------------------------------*/ +enum +{ + QEI_START = -1, +#if defined(BSP_USING_QEI0) + QEI0_START, +#endif +#if defined(BSP_USING_QEI1) + QEI1_START, +#endif +#if defined(BSP_USING_QEI2) + QEI2_START, +#endif + QEI_CNT +}; + +/* Private typedef --------------------------------------------------------------*/ +struct nu_qei +{ + struct rt_pulse_encoder_device dev; + char *name; + QEI_T *base; + IRQn_Type irqn; + uint32_t rstidx; + uint32_t modid; + + rt_uint32_t max_cntval; + rt_uint32_t cmp_val; + rt_uint8_t qei_flag; +}; +typedef struct nu_qei *nu_qei_t; + +/* Private functions ------------------------------------------------------------*/ +static rt_uint32_t nu_qei_type(struct rt_pulse_encoder_device *pulse_encoder); +static rt_err_t nu_qei_init(struct rt_pulse_encoder_device *pulse_encoder); +static rt_int32_t nu_qei_get_count(struct rt_pulse_encoder_device *pulse_encoder); +static rt_err_t nu_qei_clear_count(struct rt_pulse_encoder_device *pulse_encoder); +static rt_err_t nu_qei_control(struct rt_pulse_encoder_device *pulse_encoder, rt_uint32_t cmd, void *args); + +/* Public functions -------------------------------------------------------------*/ +rt_int32_t nu_qei_get_maxval(struct rt_pulse_encoder_device *pulse_encoder); +rt_int32_t nu_qei_get_cmpval(struct rt_pulse_encoder_device *pulse_encoder); +rt_int32_t nu_qei_get_type(struct rt_pulse_encoder_device *pulse_encoder); +void nu_qei_set_maxval_type(struct rt_pulse_encoder_device *pulse_encoder, rt_uint32_t u32val, rt_uint8_t u8type); +void nu_qei_set_cmpval(struct rt_pulse_encoder_device *pulse_encoder, rt_uint32_t u32val); + +/* Private variables ------------------------------------------------------------*/ +static struct nu_qei nu_qei_arr [] = +{ +#if defined(BSP_USING_QEI0) + { + .name = "qei0", + .base = QEI0, + .irqn = QEI0_IRQn, + .rstidx = QEI0_RST, + .modid = QEI0_MODULE, + + .max_cntval = 1000, + .cmp_val = 100, + }, +#endif + +#if defined(BSP_USING_QEI1) + { + .name = "qei1", + .base = QEI1, + .irqn = QEI1_IRQn, + .rstidx = QEI1_RST, + .modid = QEI1_MODULE, + + .max_cntval = 1000, + .cmp_val = 100, + }, +#endif + +#if defined(BSP_USING_QEI2) + { + .name = "qei2", + .base = QEI2, + .irqn = QEI2_IRQn, + .rstidx = QEI2_RST, + .modid = QEI2_MODULE, + + .max_cntval = 1000, + .cmp_val = 100, + }, +#endif +}; + +static const struct rt_pulse_encoder_ops nu_qei_ops = +{ + .init = nu_qei_init, + .get_count = nu_qei_get_count, + .clear_count = nu_qei_clear_count, + .control = nu_qei_control, +}; + +/* Public variables -------------------------------------------------------------*/ +static rt_uint32_t nu_qei_type(struct rt_pulse_encoder_device *pulse_encoder) +{ + rt_uint32_t u32type; + nu_qei_t psNuQei = (nu_qei_t)pulse_encoder; + + RT_ASSERT(pulse_encoder != RT_NULL); + + switch (pulse_encoder->type) + { + case SINGLE_PHASE_PULSE_ENCODER: + u32type = (psNuQei->cmp_val) ? QEI_CTL_X2_COMPARE_COUNTING_MODE : QEI_CTL_X2_FREE_COUNTING_MODE; + break; + + case UNKNOWN_PULSE_ENCODER_TYPE: + case AB_PHASE_PULSE_ENCODER: + default: + u32type = (psNuQei->cmp_val) ? QEI_CTL_X4_COMPARE_COUNTING_MODE : QEI_CTL_X4_FREE_COUNTING_MODE; + break; + } + + return u32type; +} + +void nu_qei_set_cmpval(struct rt_pulse_encoder_device *pulse_encoder, rt_uint32_t u32val) +{ + nu_qei_t psNuQei = (nu_qei_t)pulse_encoder; + + RT_ASSERT(pulse_encoder != RT_NULL); + + QEI_SET_CNT_CMP(psNuQei->base, u32val); + if (u32val > 0) + { + QEI_EnableInt(psNuQei->base, QEI_CTL_CMPIEN_Msk); + QEI_ENABLE_CNT_CMP(psNuQei->base); + rt_hw_interrupt_umask(psNuQei->irqn); + } + else + { + QEI_DisableInt(psNuQei->base, QEI_CTL_CMPIEN_Msk); + QEI_DISABLE_CNT_CMP(psNuQei->base); + rt_hw_interrupt_mask(psNuQei->irqn); + } +} + +static rt_err_t nu_qei_init(struct rt_pulse_encoder_device *pulse_encoder) +{ + nu_qei_t psNuQei = (nu_qei_t)pulse_encoder; + + RT_ASSERT(pulse_encoder != RT_NULL); + + /* enable noise filter */ + QEI_ENABLE_NOISE_FILTER(psNuQei->base, QEI_CTL_NFCLKSEL_DIV2); + + /* set compare value and interrupt */ + nu_qei_set_cmpval(pulse_encoder, psNuQei->cmp_val); + + /* set qei mode */ + QEI_Open(psNuQei->base, nu_qei_type(pulse_encoder), psNuQei->max_cntval); + + return RT_EOK; +} + +static rt_int32_t nu_qei_get_count(struct rt_pulse_encoder_device *pulse_encoder) +{ + nu_qei_t psNuQei = (nu_qei_t)pulse_encoder; + RT_ASSERT(pulse_encoder != RT_NULL); + return (rt_int32_t)QEI_GET_CNT_VALUE(psNuQei->base); +} + +static rt_err_t nu_qei_clear_count(struct rt_pulse_encoder_device *pulse_encoder) +{ + nu_qei_t psNuQei = (nu_qei_t)pulse_encoder; + RT_ASSERT(pulse_encoder != RT_NULL); + + QEI_Stop(psNuQei->base); + QEI_SET_CNT_VALUE(psNuQei->base, 0); + QEI_Start(psNuQei->base); + + return RT_EOK; +} + +static rt_err_t nu_qei_control(struct rt_pulse_encoder_device *pulse_encoder, rt_uint32_t cmd, void *args) +{ + rt_err_t result = RT_EOK; + nu_qei_t psNuQei = (nu_qei_t)pulse_encoder; + + RT_ASSERT(pulse_encoder != RT_NULL); + + switch (cmd) + { + case PULSE_ENCODER_CMD_ENABLE: + /* set compare value and interrupt */ + QEI_Start(psNuQei->base); + nu_qei_set_cmpval(pulse_encoder, psNuQei->cmp_val); + break; + case PULSE_ENCODER_CMD_DISABLE: + QEI_Stop(psNuQei->base); + nu_qei_set_cmpval(pulse_encoder, 0); + break; + default: + result = -RT_ENOSYS; + break; + } + + return result; +} + +static void nu_qei_isr(int vector, void *param) +{ + nu_qei_t psNuQei = (nu_qei_t)param; + + if (QEI_GET_INT_FLAG(psNuQei->base, QEI_STATUS_CMPF_Msk)) + { + QEI_CLR_INT_FLAG(psNuQei->base, QEI_STATUS_CMPF_Msk); + rt_kprintf("%s: CMP flag rising\n", psNuQei->name) ; + } +} + +rt_int32_t nu_qei_get_maxval(struct rt_pulse_encoder_device *pulse_encoder) +{ + nu_qei_t psNuQei = (nu_qei_t)pulse_encoder; + RT_ASSERT(pulse_encoder != RT_NULL); + + return psNuQei->max_cntval; +} + +rt_int32_t nu_qei_get_cmpval(struct rt_pulse_encoder_device *pulse_encoder) +{ + nu_qei_t psNuQei = (nu_qei_t)pulse_encoder; + RT_ASSERT(pulse_encoder != RT_NULL); + + return psNuQei->cmp_val; +} + +rt_int32_t nu_qei_get_type(struct rt_pulse_encoder_device *pulse_encoder) +{ + RT_ASSERT(pulse_encoder != RT_NULL); + return nu_qei_type(pulse_encoder); +} + +void nu_qei_set_maxval_type(struct rt_pulse_encoder_device *pulse_encoder, rt_uint32_t u32val, enum rt_pulse_encoder_type eType) +{ + nu_qei_t psNuQei = (nu_qei_t)pulse_encoder; + + RT_ASSERT(pulse_encoder != RT_NULL); + RT_ASSERT(eType <= AB_PHASE_PULSE_ENCODER); + + psNuQei->dev.type = eType; + psNuQei->max_cntval = u32val; + QEI_Open(psNuQei->base, nu_qei_type(&psNuQei->dev), u32val); +} + +int rt_hw_qei_init(void) +{ + int i; + rt_err_t result = RT_EOK; + + for (i = (QEI_START + 1); i < QEI_CNT; i++) + { + nu_qei_t psNuQei = &nu_qei_arr[i]; + + psNuQei->dev.type = AB_PHASE_PULSE_ENCODER; + psNuQei->dev.ops = &nu_qei_ops; + + /* Enable QEI module */ + CLK_EnableModuleClock(psNuQei->modid); + SYS_ResetModule(psNuQei->rstidx); + + /* register isr */ + rt_hw_interrupt_install(psNuQei->irqn, nu_qei_isr, psNuQei, psNuQei->name); + + result = rt_device_pulse_encoder_register((struct rt_pulse_encoder_device *)&nu_qei_arr[i].dev, nu_qei_arr[i].name, RT_NULL); + RT_ASSERT(result == RT_EOK); + } + + return (int)result; +} +INIT_APP_EXPORT(rt_hw_qei_init); + +#endif /* BSP_USING_QEI */ diff --git a/bsp/nuvoton/libraries/ma35/rtt_port/drv_qei.h b/bsp/nuvoton/libraries/ma35/rtt_port/drv_qei.h new file mode 100644 index 0000000000..94bfb558c7 --- /dev/null +++ b/bsp/nuvoton/libraries/ma35/rtt_port/drv_qei.h @@ -0,0 +1,29 @@ +/**************************************************************************//** +* +* @copyright (C) 2020 Nuvoton Technology Corp. All rights reserved. +* +* SPDX-License-Identifier: Apache-2.0 +* +* Change Logs: +* Date Author Notes +* 2021-10-21 Wayne First version +* +* Tips: +* QEI compare interrupt flag *(pulse_encoder->user_data): If compare value is +* not null, after execute device init, compare interrupt will be enabled automatic. +* When the interrupt occur, interrupt flag will be set 1. +* +******************************************************************************/ + +#ifndef __DRV_QEI_H__ +#define __DRV_QEI_H__ + +#include + +rt_int32_t nu_qei_get_maxval(struct rt_pulse_encoder_device *pulse_encoder); +rt_int32_t nu_qei_get_cmpval(struct rt_pulse_encoder_device *pulse_encoder); +rt_int32_t nu_qei_get_type(struct rt_pulse_encoder_device *pulse_encoder); +void nu_qei_set_maxval_type(struct rt_pulse_encoder_device *pulse_encoder, rt_uint32_t u32val, enum rt_pulse_encoder_type eType); +void nu_qei_set_cmpval(struct rt_pulse_encoder_device *pulse_encoder, rt_uint32_t u32val); + +#endif // __DRV_QEI_H___ diff --git a/bsp/nuvoton/libraries/ma35/rtt_port/drv_qspi.c b/bsp/nuvoton/libraries/ma35/rtt_port/drv_qspi.c new file mode 100644 index 0000000000..a81632284e --- /dev/null +++ b/bsp/nuvoton/libraries/ma35/rtt_port/drv_qspi.c @@ -0,0 +1,442 @@ +/**************************************************************************//** +* +* @copyright (C) 2020 Nuvoton Technology Corp. All rights reserved. +* +* SPDX-License-Identifier: Apache-2.0 +* +* Change Logs: +* Date Author Notes +* 2020-11-11 Wayne First version +* +******************************************************************************/ +#include + +#if defined(BSP_USING_QSPI) + +#define LOG_TAG "drv.qspi" +#define DBG_ENABLE +#define DBG_SECTION_NAME LOG_TAG +#define DBG_LEVEL DBG_INFO +#define DBG_COLOR +#include + +#include +#include + +#include + +/* Private define ---------------------------------------------------------------*/ +enum +{ + QSPI_START = -1, +#if defined(BSP_USING_QSPI0) + QSPI0_IDX, +#endif +#if defined(BSP_USING_QSPI1) + QSPI1_IDX, +#endif + QSPI_CNT +}; + +/* Private typedef --------------------------------------------------------------*/ + +/* Private functions ------------------------------------------------------------*/ +static rt_err_t nu_qspi_bus_configure(struct rt_spi_device *device, struct rt_spi_configuration *configuration); +static rt_uint32_t nu_qspi_bus_xfer(struct rt_spi_device *device, struct rt_spi_message *message); +static int nu_qspi_register_bus(struct nu_spi *qspi_bus, const char *name); + +/* Public functions -------------------------------------------------------------*/ + +/* Private variables ------------------------------------------------------------*/ +static struct rt_spi_ops nu_qspi_poll_ops = +{ + .configure = nu_qspi_bus_configure, + .xfer = nu_qspi_bus_xfer, +}; + +static struct nu_spi nu_qspi_arr [] = +{ +#if defined(BSP_USING_QSPI0) + { + .name = "qspi0", + .spi_base = (SPI_T *)QSPI0, + .rstidx = QSPI0_RST, +#if defined(BSP_USING_SPI_PDMA) +#if defined(BSP_USING_QSPI0_PDMA) + .pdma_perp_tx = PDMA_QSPI0_TX, + .pdma_perp_rx = PDMA_QSPI0_RX, +#else + .pdma_perp_tx = NU_PDMA_UNUSED, + .pdma_perp_rx = NU_PDMA_UNUSED, +#endif +#endif + }, +#endif +#if defined(BSP_USING_QSPI1) + { + .name = "qspi1", + .spi_base = (SPI_T *)QSPI1, + .rstidx = QSPI1_RST, +#if defined(BSP_USING_SPI_PDMA) +#if defined(BSP_USING_QSPI1_PDMA) + .pdma_perp_tx = PDMA_QSPI1_TX, + .pdma_perp_rx = PDMA_QSPI1_RX, +#else + .pdma_perp_tx = NU_PDMA_UNUSED, + .pdma_perp_rx = NU_PDMA_UNUSED, +#endif +#endif + }, +#endif +}; /* qspi nu_qspi */ + +static rt_err_t nu_qspi_bus_configure(struct rt_spi_device *device, + struct rt_spi_configuration *configuration) +{ + struct nu_spi *spi_bus; + rt_uint32_t u32SPIMode; + rt_err_t ret = RT_EOK; + + RT_ASSERT(device != RT_NULL); + RT_ASSERT(configuration != RT_NULL); + + spi_bus = (struct nu_spi *) device->bus; + + /* Check mode */ + switch (configuration->mode & RT_SPI_MODE_3) + { + case RT_SPI_MODE_0: + u32SPIMode = SPI_MODE_0; + break; + case RT_SPI_MODE_1: + u32SPIMode = SPI_MODE_1; + break; + case RT_SPI_MODE_2: + u32SPIMode = SPI_MODE_2; + break; + case RT_SPI_MODE_3: + u32SPIMode = SPI_MODE_3; + break; + default: + ret = RT_EIO; + goto exit_nu_qspi_bus_configure; + } + + /* Check data width */ + if (!(configuration->data_width == 8 || + configuration->data_width == 16 || + configuration->data_width == 24 || + configuration->data_width == 32)) + { + ret = RT_EINVAL; + goto exit_nu_qspi_bus_configure; + } + + /* Need to initialize new configuration? */ + if (rt_memcmp(configuration, &spi_bus->configuration, sizeof(struct rt_spi_configuration)) != 0) + { + uint32_t u32ActualClk; + rt_memcpy(&spi_bus->configuration, configuration, sizeof(struct rt_spi_configuration)); + + u32ActualClk = QSPI_Open((QSPI_T *)spi_bus->spi_base, SPI_MASTER, u32SPIMode, configuration->data_width, configuration->max_hz); + LOG_I("[%s] Preferred clock:%d, Actually:%d", spi_bus->name, configuration->max_hz, u32ActualClk); + + if (configuration->mode & RT_SPI_CS_HIGH) + { + /* Set CS pin to LOW */ + SPI_SET_SS_LOW(spi_bus->spi_base); + } + else + { + /* Set CS pin to HIGH */ + SPI_SET_SS_HIGH(spi_bus->spi_base); + } + + if (configuration->mode & RT_SPI_MSB) + { + /* Set sequence to MSB first */ + SPI_SET_MSB_FIRST(spi_bus->spi_base); + } + else + { + /* Set sequence to LSB first */ + SPI_SET_LSB_FIRST(spi_bus->spi_base); + } + } + + /* Clear SPI RX FIFO */ + nu_spi_drain_rxfifo(spi_bus->spi_base); + +exit_nu_qspi_bus_configure: + + return -(ret); +} + +static int nu_qspi_mode_config(struct nu_spi *qspi_bus, rt_uint8_t *tx, rt_uint8_t *rx, int qspi_lines) +{ + QSPI_T *qspi_base = (QSPI_T *)qspi_bus->spi_base; + if (qspi_lines > 1) + { + if (tx) + { + switch (qspi_lines) + { + case 2: + QSPI_ENABLE_DUAL_OUTPUT_MODE(qspi_base); + break; + case 4: + QSPI_ENABLE_QUAD_OUTPUT_MODE(qspi_base); + break; + default: + LOG_E("Data line is not supported.\n"); + break; + } + } + else + { + switch (qspi_lines) + { + case 2: + QSPI_ENABLE_DUAL_INPUT_MODE(qspi_base); + break; + case 4: + QSPI_ENABLE_QUAD_INPUT_MODE(qspi_base); + break; + default: + LOG_E("Data line is not supported.\n"); + break; + } + } + } + else + { + QSPI_DISABLE_DUAL_MODE(qspi_base); + QSPI_DISABLE_QUAD_MODE(qspi_base); + } + return qspi_lines; +} + +static rt_uint32_t nu_qspi_bus_xfer(struct rt_spi_device *device, struct rt_spi_message *message) +{ + struct nu_spi *qspi_bus; + struct rt_qspi_configuration *qspi_configuration; + struct rt_qspi_message *qspi_message; + rt_uint8_t u8last = 1; + + rt_uint8_t bytes_per_word; + QSPI_T *qspi_base; + rt_uint32_t u32len = 0; + + RT_ASSERT(device != RT_NULL); + RT_ASSERT(message != RT_NULL); + + qspi_bus = (struct nu_spi *) device->bus; + qspi_base = (QSPI_T *)qspi_bus->spi_base; + qspi_configuration = &qspi_bus->configuration; + + bytes_per_word = qspi_configuration->parent.data_width / 8; + + if (message->cs_take && !(qspi_configuration->parent.mode & RT_SPI_NO_CS)) + { + if (qspi_configuration->parent.mode & RT_SPI_CS_HIGH) + { + QSPI_SET_SS_HIGH(qspi_base); + } + else + { + QSPI_SET_SS_LOW(qspi_base); + } + } + + qspi_message = (struct rt_qspi_message *)message; + + /* Command + Address + Dummy + Data */ + /* Command stage */ + if (qspi_message->instruction.content != 0) + { + u8last = nu_qspi_mode_config(qspi_bus, (rt_uint8_t *) &qspi_message->instruction.content, RT_NULL, qspi_message->instruction.qspi_lines); + nu_spi_transfer((struct nu_spi *)qspi_bus, + (rt_uint8_t *) &qspi_message->instruction.content, + RT_NULL, + 1, + 1); + } + + /* Address stage */ + if (qspi_message->address.size > 0) + { + rt_uint32_t u32ReversedAddr = 0; + rt_uint32_t u32AddrNumOfByte = qspi_message->address.size / 8; + switch (u32AddrNumOfByte) + { + case 1: + u32ReversedAddr = (qspi_message->address.content & 0xff); + break; + case 2: + nu_set16_be((rt_uint8_t *)&u32ReversedAddr, qspi_message->address.content); + break; + case 3: + nu_set24_be((rt_uint8_t *)&u32ReversedAddr, qspi_message->address.content); + break; + case 4: + nu_set32_be((rt_uint8_t *)&u32ReversedAddr, qspi_message->address.content); + break; + default: + RT_ASSERT(0); + break; + } + u8last = nu_qspi_mode_config(qspi_bus, (rt_uint8_t *)&u32ReversedAddr, RT_NULL, qspi_message->address.qspi_lines); + nu_spi_transfer((struct nu_spi *)qspi_bus, + (rt_uint8_t *) &u32ReversedAddr, + RT_NULL, + u32AddrNumOfByte, + 1); + } + + /* alternate_bytes stage */ + if ((qspi_message->alternate_bytes.size > 0) && (qspi_message->alternate_bytes.size <= 4)) + { + rt_uint32_t u32AlternateByte = 0; + rt_uint32_t u32NumOfByte = qspi_message->alternate_bytes.size / 8; + switch (u32NumOfByte) + { + case 1: + u32AlternateByte = (qspi_message->alternate_bytes.content & 0xff); + break; + case 2: + nu_set16_be((rt_uint8_t *)&u32AlternateByte, qspi_message->alternate_bytes.content); + break; + case 3: + nu_set24_be((rt_uint8_t *)&u32AlternateByte, qspi_message->alternate_bytes.content); + break; + case 4: + nu_set32_be((rt_uint8_t *)&u32AlternateByte, qspi_message->alternate_bytes.content); + break; + default: + RT_ASSERT(0); + break; + } + u8last = nu_qspi_mode_config(qspi_bus, (rt_uint8_t *)&u32AlternateByte, RT_NULL, qspi_message->alternate_bytes.qspi_lines); + nu_spi_transfer((struct nu_spi *)qspi_bus, + (rt_uint8_t *) &u32AlternateByte, + RT_NULL, + u32NumOfByte, + 1); + } + + /* Dummy_cycles stage */ + if (qspi_message->dummy_cycles > 0) + { + qspi_bus->dummy = 0x00; + + u8last = nu_qspi_mode_config(qspi_bus, (rt_uint8_t *) &qspi_bus->dummy, RT_NULL, u8last); + nu_spi_transfer((struct nu_spi *)qspi_bus, + (rt_uint8_t *) &qspi_bus->dummy, + RT_NULL, + qspi_message->dummy_cycles / (8 / u8last), + 1); + } + + if (message->length > 0) + { + /* Data stage */ + nu_qspi_mode_config(qspi_bus, (rt_uint8_t *) message->send_buf, (rt_uint8_t *) message->recv_buf, qspi_message->qspi_data_lines); + nu_spi_transfer((struct nu_spi *)qspi_bus, + (rt_uint8_t *) message->send_buf, + (rt_uint8_t *) message->recv_buf, + message->length, + bytes_per_word); + u32len = message->length; + } + else + { + u32len = 1; + } + + if (message->cs_release && !(qspi_configuration->parent.mode & RT_SPI_NO_CS)) + { + if (qspi_configuration->parent.mode & RT_SPI_CS_HIGH) + { + QSPI_SET_SS_LOW(qspi_base); + } + else + { + QSPI_SET_SS_HIGH(qspi_base); + } + } + + return u32len; +} + +static int nu_qspi_register_bus(struct nu_spi *qspi_bus, const char *name) +{ + return rt_qspi_bus_register(&qspi_bus->dev, name, &nu_qspi_poll_ops); +} + +/** + * Hardware SPI Initial + */ +static int rt_hw_qspi_init(void) +{ + rt_uint8_t i; + + for (i = (QSPI_START + 1); i < QSPI_CNT; i++) + { + nu_sys_ip_reset(nu_qspi_arr[i].rstidx); + + nu_qspi_register_bus(&nu_qspi_arr[i], nu_qspi_arr[i].name); +#if defined(BSP_USING_SPI_PDMA) + nu_qspi_arr[i].pdma_chanid_tx = -1; + nu_qspi_arr[i].pdma_chanid_rx = -1; +#endif +#if defined(BSP_USING_QSPI_PDMA) + if ((nu_qspi_arr[i].pdma_perp_tx != NU_PDMA_UNUSED) && (nu_qspi_arr[i].pdma_perp_rx != NU_PDMA_UNUSED)) + { + if (nu_hw_spi_pdma_allocate(&nu_qspi_arr[i]) != RT_EOK) + { + LOG_E("Failed to allocate DMA channels for %s. We will use poll-mode for this bus.\n", nu_qspi_arr[i].name); + } + } +#endif + } + + return 0; +} +INIT_DEVICE_EXPORT(rt_hw_qspi_init); + +rt_err_t nu_qspi_bus_attach_device(const char *bus_name, const char *device_name, rt_uint8_t data_line_width, void (*enter_qspi_mode)(), void (*exit_qspi_mode)()) +{ + struct rt_qspi_device *qspi_device = RT_NULL; + rt_err_t result = RT_EOK; + + RT_ASSERT(bus_name != RT_NULL); + RT_ASSERT(device_name != RT_NULL); + RT_ASSERT(data_line_width == 1 || data_line_width == 2 || data_line_width == 4); + + qspi_device = (struct rt_qspi_device *)rt_malloc(sizeof(struct rt_qspi_device)); + if (qspi_device == RT_NULL) + { + LOG_E("no memory, qspi bus attach device failed!\n"); + result = -RT_ENOMEM; + goto __exit; + } + + qspi_device->enter_qspi_mode = enter_qspi_mode; + qspi_device->exit_qspi_mode = exit_qspi_mode; + qspi_device->config.qspi_dl_width = data_line_width; + + result = rt_spi_bus_attach_device(&qspi_device->parent, device_name, bus_name, RT_NULL); + +__exit: + if (result != RT_EOK) + { + if (qspi_device) + { + rt_free(qspi_device); + } + } + + return result; +} + +#endif //#if defined(BSP_USING_QSPI) diff --git a/bsp/nuvoton/libraries/ma35/rtt_port/drv_qspi.h b/bsp/nuvoton/libraries/ma35/rtt_port/drv_qspi.h new file mode 100644 index 0000000000..87be3e6e42 --- /dev/null +++ b/bsp/nuvoton/libraries/ma35/rtt_port/drv_qspi.h @@ -0,0 +1,20 @@ +/**************************************************************************//** +* +* @copyright (C) 2020 Nuvoton Technology Corp. All rights reserved. +* +* SPDX-License-Identifier: Apache-2.0 +* +* Change Logs: +* Date Author Notes +* 2020-2-7 Wayne First version +* +******************************************************************************/ + +#ifndef __DRV_QSPI_H__ +#define __DRV_QSPI_H__ + +#include + +rt_err_t nu_qspi_bus_attach_device(const char *bus_name, const char *device_name, rt_uint8_t data_line_width, void (*enter_qspi_mode)(), void (*exit_qspi_mode)()); + +#endif // __DRV_QSPI_H___ diff --git a/bsp/nuvoton/libraries/ma35/rtt_port/drv_rtc.c b/bsp/nuvoton/libraries/ma35/rtt_port/drv_rtc.c new file mode 100644 index 0000000000..e960ae63b2 --- /dev/null +++ b/bsp/nuvoton/libraries/ma35/rtt_port/drv_rtc.c @@ -0,0 +1,371 @@ +/**************************************************************************//** +* +* @copyright (C) 2020 Nuvoton Technology Corp. All rights reserved. +* +* SPDX-License-Identifier: Apache-2.0 +* +* Change Logs: +* Date Author Notes +* 2021-09-27 Wayne First version +* +******************************************************************************/ +#include + +#if defined(BSP_USING_RTC) + +#include +#include +#include "NuMicro.h" +#include "drv_sys.h" +#include "drv_common.h" + +/* Private define ---------------------------------------------------------------*/ + +/* convert the real year and month value to the format of struct tm. */ +#define CONV_TO_TM_YEAR(year) ((year) - 1900) +#define CONV_TO_TM_MON(mon) ((mon) - 1) + +/* convert the tm_year and tm_mon from struct tm to the real value. */ +#define CONV_FROM_TM_YEAR(tm_year) ((tm_year) + 1900) +#define CONV_FROM_TM_MON(tm_mon) ((tm_mon) + 1) + +/* rtc date upper bound reaches the year of 2099. */ +#define RTC_TM_UPPER_BOUND \ +{ .tm_year = CONV_TO_TM_YEAR(2038), \ + .tm_mon = CONV_TO_TM_MON(1), \ + .tm_mday = 19, \ + .tm_hour = 3, \ + .tm_min = 14, \ + .tm_sec = 07, \ +} + +/* rtc date lower bound reaches the year of 2000. */ +#define RTC_TM_LOWER_BOUND \ +{ .tm_year = CONV_TO_TM_YEAR(2000), \ + .tm_mon = CONV_TO_TM_MON(1), \ + .tm_mday = 1, \ + .tm_hour = 0, \ + .tm_min = 0, \ + .tm_sec = 0, \ +} + +/* Private typedef --------------------------------------------------------------*/ + +/* Private functions ------------------------------------------------------------*/ +static rt_err_t nu_rtc_control(rt_device_t dev, int cmd, void *args); + +#if defined (NU_RTC_SUPPORT_IO_RW) + static rt_size_t nu_rtc_read(rt_device_t dev, rt_off_t pos, void *buffer, rt_size_t size); + static rt_size_t nu_rtc_write(rt_device_t dev, rt_off_t pos, const void *buffer, rt_size_t size); +#endif + +static rt_err_t nu_rtc_is_date_valid(const time_t t); +static rt_err_t nu_rtc_init(void); + +#if defined(RT_USING_ALARM) + static void nu_rtc_alarm_reset(void); + static void nu_rtc_isr(int vector, void *param); +#endif + +/* Public functions -------------------------------------------------------------*/ +#if defined (NU_RTC_SUPPORT_MSH_CMD) + extern rt_err_t set_date(rt_uint32_t year, rt_uint32_t month, rt_uint32_t day); + extern rt_err_t set_time(rt_uint32_t hour, rt_uint32_t minute, rt_uint32_t second); +#endif + +/* Private variables ------------------------------------------------------------*/ +static struct rt_device device_rtc; + +static rt_err_t nu_rtc_init(void) +{ + /* hw rtc initialise */ + CLK_EnableModuleClock(RTC_MODULE); + if (RTC_Open(NULL) < 0) + { + rt_kprintf("*** RTC initialization is failure. Is LXT clock ready?\n"); + rt_kprintf("*** Please also press RTC Wakeup button before pressing Reset button.\n"); + return -RT_ERROR; + } + RTC_DisableInt(RTC_INTEN_ALMIEN_Msk | RTC_INTEN_TICKIEN_Msk | + RTC_INTEN_TAMP0IEN_Msk | RTC_INTEN_TAMP1IEN_Msk); + +#if defined(RT_USING_ALARM) + + nu_rtc_alarm_reset(); + RTC_EnableInt(RTC_INTEN_ALMIEN_Msk); + + rt_hw_interrupt_install(RTC_IRQn, nu_rtc_isr, &device_rtc, "rtc"); + rt_hw_interrupt_umask(RTC_IRQn); + +#endif + + return RT_EOK; +} + + +#if defined(RT_USING_ALARM) +/* Reset alarm settings to avoid the unwanted values remain in rtc registers. */ +static void nu_rtc_alarm_reset(void) +{ + S_RTC_TIME_DATA_T alarm; + + /* Reset alarm time and calendar. */ + alarm.u32Year = RTC_YEAR2000; + alarm.u32Month = 0; + alarm.u32Day = 0; + alarm.u32Hour = 0; + alarm.u32Minute = 0; + alarm.u32Second = 0; + alarm.u32TimeScale = RTC_CLOCK_24; + + RTC_SetAlarmDateAndTime(&alarm); + + /* Reset alarm time mask and calendar mask. */ + RTC_SetAlarmDateMask(0, 0, 0, 0, 0, 0); + RTC_SetAlarmTimeMask(0, 0, 0, 0, 0, 0); + + /* Clear alarm flag for safe */ + RTC_CLEAR_ALARM_INT_FLAG(); +} +#endif + + +/* rtc device driver initialise. */ +int rt_hw_rtc_init(void) +{ + rt_err_t ret; + + ret = nu_rtc_init(); + if (ret != RT_EOK) + { + return -1; + } + + /* register rtc device IO operations */ + device_rtc.type = RT_Device_Class_RTC; + device_rtc.init = NULL; + device_rtc.open = NULL; + device_rtc.close = NULL; + device_rtc.control = nu_rtc_control; + +#if defined (NU_RTC_SUPPORT_IO_RW) + device_rtc.read = nu_rtc_read; + device_rtc.write = nu_rtc_write; +#else + device_rtc.read = NULL; + device_rtc.write = NULL; +#endif + + device_rtc.user_data = RT_NULL; + device_rtc.rx_indicate = RT_NULL; + device_rtc.tx_complete = RT_NULL; + + ret = rt_device_register(&device_rtc, "rtc", RT_DEVICE_FLAG_RDWR); + + return (int)ret; +} +INIT_BOARD_EXPORT(rt_hw_rtc_init); + + +#if defined (NU_RTC_SUPPORT_IO_RW) +/* Register rt-thread device.read() entry. */ +static rt_size_t nu_rtc_read(rt_device_t dev, rt_off_t pos, void *buffer, rt_size_t size) +{ + (void) pos; + nu_rtc_control(dev, RT_DEVICE_CTRL_RTC_GET_TIME, buffer); + + return size; +} +#endif + + +#if defined (NU_RTC_SUPPORT_IO_RW) +/* Register rt-thread device.write() entry. */ +static rt_size_t nu_rtc_write(rt_device_t dev, rt_off_t pos, const void *buffer, rt_size_t size) +{ + (void) pos; + nu_rtc_control(dev, RT_DEVICE_CTRL_RTC_SET_TIME, (void *)buffer); + + return size; +} +#endif + + +static rt_err_t nu_rtc_is_date_valid(const time_t t) +{ + static struct tm tm_upper = RTC_TM_UPPER_BOUND; + static struct tm tm_lower = RTC_TM_LOWER_BOUND; + static time_t t_upper, t_lower; + static rt_bool_t initialised = RT_FALSE; + + if (!initialised) + { + t_upper = timegm((struct tm *)&tm_upper); + t_lower = timegm((struct tm *)&tm_lower); + initialised = RT_TRUE; + } + + /* check the date is supported by rtc. */ + if ((t > t_upper) || (t < t_lower)) + return -(RT_EINVAL); + + return RT_EOK; +} + + +/* Register rt-thread device.control() entry. */ +static rt_err_t nu_rtc_control(rt_device_t dev, int cmd, void *args) +{ + struct tm tm_out, tm_in; + time_t *time; + S_RTC_TIME_DATA_T hw_time; + +#if defined(RT_USING_ALARM) + + struct rt_rtc_wkalarm *wkalarm; + S_RTC_TIME_DATA_T hw_alarm; +#endif + + if ((dev == NULL) || (args == NULL)) + return -(RT_EINVAL); + + switch (cmd) + { + case RT_DEVICE_CTRL_RTC_GET_TIME: + + time = (time_t *)args; + RTC_GetDateAndTime(&hw_time); + + tm_out.tm_year = CONV_TO_TM_YEAR(hw_time.u32Year); + tm_out.tm_mon = CONV_TO_TM_MON(hw_time.u32Month); + tm_out.tm_mday = hw_time.u32Day; + tm_out.tm_hour = hw_time.u32Hour; + tm_out.tm_min = hw_time.u32Minute; + tm_out.tm_sec = hw_time.u32Second; + *time = timegm(&tm_out); + break; + + case RT_DEVICE_CTRL_RTC_SET_TIME: + + time = (time_t *) args; + + if (nu_rtc_is_date_valid(*time) != RT_EOK) + return -(RT_ERROR); + + gmtime_r(time, &tm_in); + hw_time.u32Year = CONV_FROM_TM_YEAR(tm_in.tm_year); + hw_time.u32Month = CONV_FROM_TM_MON(tm_in.tm_mon); + hw_time.u32Day = tm_in.tm_mday; + hw_time.u32Hour = tm_in.tm_hour; + hw_time.u32Minute = tm_in.tm_min; + hw_time.u32Second = tm_in.tm_sec; + hw_time.u32TimeScale = RTC_CLOCK_24; + hw_time.u32AmPm = 0; + + RTC_SetDateAndTime(&hw_time); + break; + +#if defined(RT_USING_ALARM) + case RT_DEVICE_CTRL_RTC_GET_ALARM: + + wkalarm = (struct rt_rtc_wkalarm *) args; + RTC_GetAlarmDateAndTime(&hw_alarm); + + wkalarm->tm_hour = hw_alarm.u32Hour; + wkalarm->tm_min = hw_alarm.u32Minute; + wkalarm->tm_sec = hw_alarm.u32Second; + break; + + case RT_DEVICE_CTRL_RTC_SET_ALARM: + + wkalarm = (struct rt_rtc_wkalarm *) args; + hw_alarm.u32Hour = wkalarm->tm_hour; + hw_alarm.u32Minute = wkalarm->tm_min; + hw_alarm.u32Second = wkalarm->tm_sec; + + RTC_SetAlarmDateMask(1, 1, 1, 1, 1, 1); + RTC_SetAlarmDateAndTime(&hw_alarm); + break; + + default: + return -(RT_EINVAL); +#endif + } + + return RT_EOK; +} + + +#if defined (NU_RTC_SUPPORT_MSH_CMD) + +/* Support "rtc_det_date" command line in msh mode */ +static rt_err_t msh_rtc_set_date(int argc, char **argv) +{ + rt_uint32_t index, len, arg[3]; + + rt_memset(arg, 0, sizeof(arg)); + len = (argc >= 4) ? 4 : argc; + + /* The date information stored in argv is represented by the following order : + argv[0,1,2,3] = [cmd, year, month, day] */ + for (index = 0; index < (len - 1); index ++) + { + arg[index] = atol(argv[index + 1]); + } + + return set_date(arg[0], arg[1], arg[2]); +} +MSH_CMD_EXPORT_ALIAS(msh_rtc_set_date, rtc_set_date, e.g: rtc_set_date 2020 1 20); +#endif + + +#if defined (NU_RTC_SUPPORT_MSH_CMD) + +/* Support "rtc_det_time" command line in msh mode */ +static rt_err_t msh_rtc_set_time(int argc, char **argv) +{ + rt_uint32_t index, len, arg[3]; + + rt_memset(arg, 0, sizeof(arg)); + len = (argc >= 4) ? 4 : argc; + + /* The time information stored in argv is represented by the following order : + argv[0,1,2,3] = [cmd, hour, minute, second] */ + for (index = 0; index < (len - 1); index ++) + { + arg[index] = atol(argv[index + 1]); + } + + return set_time(arg[0], arg[1], arg[2]); +} +MSH_CMD_EXPORT_ALIAS(msh_rtc_set_time, rtc_set_time, e.g: rtc_set_time 18 30 00); +#endif + +#if defined(RT_USING_ALARM) +/* rtc interrupt entry */ +static void nu_rtc_isr(int vector, void *param) +{ + rt_interrupt_enter(); + + if (RTC_GET_TICK_INT_FLAG()) + { + RTC_CLEAR_TICK_INT_FLAG(); + } + +#if defined(RT_USING_ALARM) + + if (RTC_GET_ALARM_INT_FLAG()) + { + RTC_CLEAR_ALARM_INT_FLAG(); + + /* Send an alarm event to notify rt-thread alarm service. */ + rt_alarm_update(&device_rtc, (rt_uint32_t)NULL); + } +#endif + + rt_interrupt_leave(); +} +#endif + +#endif /* BSP_USING_RTC */ + diff --git a/bsp/nuvoton/libraries/ma35/rtt_port/drv_rtp.c b/bsp/nuvoton/libraries/ma35/rtt_port/drv_rtp.c new file mode 100644 index 0000000000..08ed8e0513 --- /dev/null +++ b/bsp/nuvoton/libraries/ma35/rtt_port/drv_rtp.c @@ -0,0 +1,250 @@ +/**************************************************************************//** +* @copyright (C) 2020 Nuvoton Technology Corp. All rights reserved. +* +* SPDX-License-Identifier: Apache-2.0 +* +* Change Logs: +* Date Author Notes +* 2022-9-27 Wayne First version +* +******************************************************************************/ + +#include + +#if !defined(USE_MA35D1_SUBM) + +#define LOG_TAG "drv.rtp" +#undef DBG_ENABLE +#define DBG_SECTION_NAME LOG_TAG +#define DBG_LEVEL LOG_LVL_DBG +#define DBG_COLOR +#include + +#include +#include "drv_sys.h" +#include +#include +#include +#include +#include + +#define RTP_USING_AT_STARTUP + +/* Link to rtthread.bin in ma35-rtp folder. */ +#define PATH_RTP_INCBIN "..//ma35-rtp//rtthread.bin" + +#define READ_BLOCK_SIZE 128 +#define REGION_ADDR_SRAM0 0x24000000 +#define REGION_ADDR_DDR (0x80020000|UNCACHEABLE) +#define REGION_MAXSIZE_SRAM0 (128*1024) +#define REGION_MAXSIZE_DDR (4*1024*1024-REGION_MAXSIZE_SRAM0) +#define REGION_MAXSIZE_LIMIT (REGION_MAXSIZE_SRAM0+REGION_MAXSIZE_DDR) + +#if !defined(PATH_RTP_FW_FILE) + #define PATH_RTP_FW_FILE "/mnt/sd1p0/rtp.bin" +#endif + +#if defined(RTP_USING_AT_STARTUP) + +#define STR2(x) #x +#define STR(x) STR2(x) + +#define INCBIN(name, file) \ + __asm__(".section .rodata\n" \ + ".global incbin_" STR(name) "_start\n" \ + ".balign 16\n" \ + "incbin_" STR(name) "_start:\n" \ + ".incbin \"" file "\"\n" \ + \ + ".global incbin_" STR(name) "_end\n" \ + ".balign 1\n" \ + "incbin_" STR(name) "_end:\n" \ + ".byte 0\n" \ + ); \ + extern const __attribute__((aligned(16))) void* incbin_ ## name ## _start; \ + extern const void* incbin_ ## name ## _end; \ + +INCBIN(rtp, PATH_RTP_INCBIN); + +static int nu_rtp_load_from_memory(void *pvBuf, int len) +{ + int remaining; + + if (!pvBuf || !len) + goto exit_nu_rtp_load_from_memory; + + /* Limit memory usage to 4MB. */ + if (len > REGION_MAXSIZE_LIMIT) + goto exit_nu_rtp_load_from_memory; + + remaining = len; + + /* Copy to SRAM0 */ + if (remaining > REGION_MAXSIZE_SRAM0) + { + rt_memcpy((void *)REGION_ADDR_SRAM0, pvBuf, REGION_MAXSIZE_SRAM0); + remaining -= REGION_MAXSIZE_SRAM0; + } + else + { + rt_memcpy((void *)REGION_ADDR_SRAM0, pvBuf, remaining); + remaining -= remaining; + } + + /* Copy to non-cacheable DDR memory if the size over 128KB. */ + if (remaining > 0) + { + rt_memcpy((void *)REGION_ADDR_DDR, (pvBuf + REGION_MAXSIZE_SRAM0), remaining); + remaining -= remaining; + } + + return 0; + +exit_nu_rtp_load_from_memory: + + return -1; +} +#endif + +RT_WEAK void nu_rtp_sspcc_setup(void) +{ + SSPCC_SET_REALM(SSPCC_UART16, SSPCC_SSET_SUBM); + + SSPCC_SET_GPIO_REALM(PK, 0, SSPCC_SSET_SUBM); + SSPCC_SET_GPIO_REALM(PK, 1, SSPCC_SSET_SUBM); + SSPCC_SET_GPIO_REALM(PK, 2, SSPCC_SSET_SUBM); + SSPCC_SET_GPIO_REALM(PK, 3, SSPCC_SSET_SUBM); +} + +static void nu_rtp_init(void) +{ + /* Enable WDT1/WDT2 reset */ + SYS->MISCRFCR |= SYS_MISCRFCR_WDT1RSTAEN_Msk | SYS_MISCRFCR_WDT2RSTAEN_Msk | SYS_MISCRFCR_WDT1RSTMEN_Msk; + + /* Enable M4 I/D cache */ + SYS->MISCFCR0 |= (SYS_MISCFCR0_RTPICACHEN_Msk | SYS_MISCFCR0_RTPDCACHEN_Msk | SYS_MISCFCR0_RTPDRMAEN_Msk); + + nu_rtp_sspcc_setup(); +} + +void nu_rtp_start(void) +{ + /* Enable RTP clock */ + CLK_EnableModuleClock(RTP_MODULE); + + /* Disable M4 Core reset*/ + SYS->IPRST0 &= ~SYS_IPRST0_CM4RST_Msk; +} +MSH_CMD_EXPORT(nu_rtp_start, start rtp); + +void nu_rtp_stop(void) +{ + /* Enable M4 Core reset*/ + SYS->IPRST0 |= SYS_IPRST0_CM4RST_Msk; + + /* Disable RTP clock */ + CLK_DisableModuleClock(RTP_MODULE); +} +MSH_CMD_EXPORT(nu_rtp_stop, stop rtp); + + +#if defined(RT_USING_DFS) +static int nu_rtp_load_from_file(char *szAbsFilePath) +{ + int fd, ret = -1; + char *buff_ptr = RT_NULL; + rt_size_t offset = 0; + + fd = open(szAbsFilePath, O_RDONLY); + if (fd < 0) + { + LOG_E("Could not open %s for rtp loading.", szAbsFilePath); + goto exit_nu_rtp_load_from_file; + } + + while (1) + { + int length; + + if (offset < REGION_MAXSIZE_SRAM0) + { + buff_ptr = (char *)(REGION_ADDR_SRAM0 + offset); + } + else + { + buff_ptr = (char *)(REGION_ADDR_DDR + offset - REGION_MAXSIZE_SRAM0); + } + + /* Limit memory usage to 4MB. */ + if ((offset + READ_BLOCK_SIZE) >= REGION_MAXSIZE_SRAM0) + goto exit_nu_rtp_load_from_file; + + length = read(fd, buff_ptr, READ_BLOCK_SIZE); + + if (length <= 0) break; + offset += length; + + //rt_kprintf("readed (%d/%d) to %08x\n", length, offset, buff_ptr); + } + + ret = 0; + +exit_nu_rtp_load_from_file: + + if (fd >= 0) + close(fd); + + return ret; +} + +int nu_rtp_load_run(int argc, char *argv[]) +{ + char *szFilePath = RT_NULL; + + if (argc == 1) + { + szFilePath = PATH_RTP_FW_FILE; + } + else if (argc == 2) + { + szFilePath = argv[1]; + } + + nu_rtp_stop(); + nu_rtp_init(); + + if (!szFilePath || nu_rtp_load_from_file(szFilePath) < 0) + return -1; + + rt_kprintf("Loaded %s, then run...\n", szFilePath); + + nu_rtp_start(); + + return 0; +} +MSH_CMD_EXPORT(nu_rtp_load_run, load rtp code then run); +#endif + +int rt_hw_rtp_init(void) +{ + int fw_size; + + fw_size = (int)((char *)&incbin_rtp_end - (char *)&incbin_rtp_start); + rt_kprintf("INCBIN RTP Start = %p\n", &incbin_rtp_start); + rt_kprintf("INCBIN RTP Size = %p\n", fw_size); + + /* Enable RTP and reset M4 reset */ + nu_rtp_init(); + +#if defined(RTP_USING_AT_STARTUP) + nu_rtp_stop(); + nu_rtp_load_from_memory(&incbin_rtp_start, fw_size); +#endif + + nu_rtp_start(); + + return 0; +} +INIT_BOARD_EXPORT(rt_hw_rtp_init); + +#endif //#if defined(USE_MA35D1_SUBM) diff --git a/bsp/nuvoton/libraries/ma35/rtt_port/drv_scuart.c b/bsp/nuvoton/libraries/ma35/rtt_port/drv_scuart.c new file mode 100644 index 0000000000..a0541c360c --- /dev/null +++ b/bsp/nuvoton/libraries/ma35/rtt_port/drv_scuart.c @@ -0,0 +1,323 @@ +/**************************************************************************//** + * + * @copyright (C) 2020 Nuvoton Technology Corp. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + * 2021-9-27 Wayne First version + * + ******************************************************************************/ + +#include + +#if defined(BSP_USING_SCUART) + +#include "NuMicro.h" +#include +#include +#include + +/* Private definition + * ---------------------------------------------------------------*/ +#define LOG_TAG "drv.scuart" +#define DBG_ENABLE +#define DBG_SECTION_NAME "drv.scuart" +#define DBG_LEVEL DBG_ERROR +#define DBG_COLOR +#include + +enum +{ + SCUART_START = -1, +#if defined(BSP_USING_SCUART0) + SCUART0_IDX, +#endif +#if defined(BSP_USING_SCUART1) + SCUART1_IDX, +#endif + SCUART_CNT +}; + +/* Private typedef + * --------------------------------------------------------------*/ +struct nu_scuart +{ + rt_serial_t dev; + char *name; + SC_T *base; + IRQn_Type irqn; + uint32_t rstidx; + uint32_t modid; +}; +typedef struct nu_scuart *nu_scuart_t; + +/* Private functions + * ------------------------------------------------------------*/ +static rt_err_t nu_scuart_configure(struct rt_serial_device *serial, + struct serial_configure *cfg); +static rt_err_t nu_scuart_control(struct rt_serial_device *serial, int cmd, + void *arg); +static int nu_scuart_send(struct rt_serial_device *serial, char c); +static int nu_scuart_receive(struct rt_serial_device *serial); +static void nu_scuart_isr(int vector, void *param); + +static const struct rt_uart_ops nu_scuart_ops = +{ + .configure = nu_scuart_configure, + .control = nu_scuart_control, + .putc = nu_scuart_send, + .getc = nu_scuart_receive, + .dma_transmit = RT_NULL /* not support DMA mode */ +}; + +static const struct serial_configure nu_scuart_default_config = + RT_SERIAL_CONFIG_DEFAULT; + +static struct nu_scuart nu_scuart_arr[] = +{ +#if defined(BSP_USING_SCUART0) + { + .name = "scuart0", .base = SC0, .irqn = SC0_IRQn, .rstidx = SC0_RST, .modid = SC0_MODULE, + }, +#endif +#if defined(BSP_USING_SCUART1) + { + .name = "scuart1", .base = SC1, .irqn = SC1_IRQn, .rstidx = SC1_RST, .modid = SC1_MODULE, + }, +#endif +}; /* scuart nu_scuart */ + +/** + * All SCUART interrupt service routine + */ +static void nu_scuart_isr(int vector, void *param) +{ + nu_scuart_t psNuSCUart = (nu_scuart_t)param; + + /* Handle RX event */ + if (SCUART_GET_INT_FLAG(psNuSCUart->base, SC_INTSTS_RXTOIF_Msk) || + SCUART_GET_INT_FLAG(psNuSCUart->base, SC_INTSTS_RDAIF_Msk)) + { + rt_hw_serial_isr(&psNuSCUart->dev, RT_SERIAL_EVENT_RX_IND); + + // RDA is the only interrupt enabled in this driver, this status bit + // automatically cleared after Rx FIFO empty. So no need to clear interrupt + // status here. + SCUART_CLR_INT_FLAG(psNuSCUart->base, SC_INTSTS_RXTOIF_Msk); + } +} + +/** + * Configure scuart port + */ +static rt_err_t nu_scuart_configure(struct rt_serial_device *serial, + struct serial_configure *cfg) +{ + rt_err_t ret = RT_EOK; + uint32_t scuart_word_len = 0; + uint32_t scuart_stop_bit = 0; + uint32_t scuart_parity = 0; + nu_scuart_t psNuSCUart = (nu_scuart_t)serial; + RT_ASSERT(psNuSCUart); + + /* Check baud rate */ + RT_ASSERT(cfg->baud_rate); + + /* Check word len */ + switch (cfg->data_bits) + { + case DATA_BITS_5: + scuart_word_len = SCUART_CHAR_LEN_5; + break; + + case DATA_BITS_6: + scuart_word_len = SCUART_CHAR_LEN_6; + break; + + case DATA_BITS_7: + scuart_word_len = SCUART_CHAR_LEN_7; + break; + + case DATA_BITS_8: + scuart_word_len = SCUART_CHAR_LEN_8; + break; + + default: + LOG_E("Unsupported data length"); + ret = RT_EINVAL; + goto exit_nu_scuart_configure; + } + + /* Check stop bit */ + switch (cfg->stop_bits) + { + case STOP_BITS_1: + scuart_stop_bit = SCUART_STOP_BIT_1; + break; + + case STOP_BITS_2: + scuart_stop_bit = SCUART_STOP_BIT_2; + break; + + default: + LOG_E("Unsupported stop bit"); + ret = RT_EINVAL; + goto exit_nu_scuart_configure; + } + + /* Check parity */ + switch (cfg->parity) + { + case PARITY_NONE: + scuart_parity = SCUART_PARITY_NONE; + break; + + case PARITY_ODD: + scuart_parity = SCUART_PARITY_ODD; + break; + + case PARITY_EVEN: + scuart_parity = SCUART_PARITY_EVEN; + break; + + default: + LOG_E("Unsupported parity"); + ret = RT_EINVAL; + goto exit_nu_scuart_configure; + } + + nu_sys_ip_reset(psNuSCUart->rstidx); + + /* Open SCUART and set SCUART baud rate */ + SCUART_Open(psNuSCUart->base, cfg->baud_rate); + + /* Set line configuration. */ + SCUART_SetLineConfig(psNuSCUart->base, 0, scuart_word_len, scuart_parity, + scuart_stop_bit); + + /* Enable interrupt. */ + rt_hw_interrupt_umask(psNuSCUart->irqn); + +exit_nu_scuart_configure: + + if (ret != RT_EOK) + SCUART_Close(psNuSCUart->base); + + return -(ret); +} + +/** + * SCUART interrupt control + */ +static rt_err_t nu_scuart_control(struct rt_serial_device *serial, int cmd, + void *arg) +{ + rt_err_t result = RT_EOK; + rt_uint32_t flag; + rt_ubase_t ctrl_arg = (rt_ubase_t)arg; + nu_scuart_t psNuSCUart = (nu_scuart_t)serial; + RT_ASSERT(psNuSCUart); + + switch (cmd) + { + case RT_DEVICE_CTRL_CLR_INT: + + if (ctrl_arg == RT_DEVICE_FLAG_INT_RX) /* Disable INT-RX */ + { + flag = SC_INTEN_RDAIEN_Msk | SC_INTEN_RXTOIEN_Msk; + SCUART_DISABLE_INT(psNuSCUart->base, flag); + } + break; + + case RT_DEVICE_CTRL_SET_INT: + + if (ctrl_arg == RT_DEVICE_FLAG_INT_RX) /* Enable INT-RX */ + { + flag = SC_INTEN_RDAIEN_Msk | SC_INTEN_RXTOIEN_Msk; + SCUART_ENABLE_INT(psNuSCUart->base, flag); + } + break; + + case RT_DEVICE_CTRL_CLOSE: + + /* Disable interrupt. */ + rt_hw_interrupt_mask(psNuSCUart->irqn); + + /* Close SCUART port */ + SCUART_Close(psNuSCUart->base); + + break; + + default: + + result = -RT_EINVAL; + break; + } + return result; +} + +/** + * SCUART put char + */ +static int nu_scuart_send(struct rt_serial_device *serial, char c) +{ + nu_scuart_t psNuSCUart = (nu_scuart_t)serial; + RT_ASSERT(psNuSCUart); + + /* Waiting if TX-FIFO is full. */ + while (SCUART_IS_TX_FULL(psNuSCUart->base)) ; + + /* Put char into TX-FIFO */ + SCUART_WRITE(psNuSCUart->base, c); + + return 1; +} + +/** + * SCUART get char + */ +static int nu_scuart_receive(struct rt_serial_device *serial) +{ + nu_scuart_t psNuSCUart = (nu_scuart_t)serial; + RT_ASSERT(psNuSCUart); + + /* Return failure if RX-FIFO is empty. */ + if (SCUART_GET_RX_EMPTY(psNuSCUart->base)) + { + return -1; + } + + /* Get char from RX-FIFO */ + return SCUART_READ(psNuSCUart->base); +} + +/** + * Hardware SCUART Initialization + */ +static int rt_hw_scuart_init(void) +{ + int i; + rt_uint32_t flag; + rt_err_t ret = RT_EOK; + + for (i = (SCUART_START + 1); i < SCUART_CNT; i++) + { + flag = RT_DEVICE_FLAG_RDWR | RT_DEVICE_FLAG_INT_RX; + + nu_scuart_arr[i].dev.ops = &nu_scuart_ops; + nu_scuart_arr[i].dev.config = nu_scuart_default_config; + + SYS_ResetModule(nu_scuart_arr[i].rstidx); + + rt_hw_interrupt_install(nu_scuart_arr[i].irqn, nu_scuart_isr, &nu_scuart_arr[i], nu_scuart_arr[i].name); + + ret = rt_hw_serial_register(&nu_scuart_arr[i].dev, nu_scuart_arr[i].name, flag, NULL); + RT_ASSERT(ret == RT_EOK); + } + + return (int)ret; +} +INIT_DEVICE_EXPORT(rt_hw_scuart_init); +#endif //#if defined(BSP_USING_SCUART) diff --git a/bsp/nuvoton/libraries/ma35/rtt_port/drv_sdio.c b/bsp/nuvoton/libraries/ma35/rtt_port/drv_sdio.c new file mode 100644 index 0000000000..503c591c87 --- /dev/null +++ b/bsp/nuvoton/libraries/ma35/rtt_port/drv_sdio.c @@ -0,0 +1,1061 @@ +/**************************************************************************//** +* +* @copyright (C) 2020 Nuvoton Technology Corp. All rights reserved. +* +* SPDX-License-Identifier: Apache-2.0 +* +* Change Logs: +* Date Author Notes +* 2021-11-19 Wayne First version +* +******************************************************************************/ + +#include "rtconfig.h" + +#if defined(BSP_USING_SDH) + +#include +#include +#include + +#include "NuMicro.h" +#include "drv_common.h" + +#define LOG_TAG "drv.sdio" +#undef DBG_ENABLE +#define DBG_SECTION_NAME LOG_TAG +#define DBG_LEVEL LOG_LVL_INFO +#define DBG_COLOR +#include + +#define SDH_ALIGN_LEN 64 +#define SDH_BUFF_SIZE (512*1024) + +enum +{ + SDH_START = -1, +#if defined(BSP_USING_SDH0) + SDH0_IDX, +#endif +#if defined(BSP_USING_SDH1) + SDH1_IDX, +#endif + SDH_CNT +}; + +struct nu_sdh +{ + struct rt_mmcsd_host *host; + char *name; + SDH_T *base; + IRQn_Type irqn; + uint32_t rstidx; + uint32_t modid; + uint8_t *cachebuf; + + struct rt_event event; +}; +typedef struct nu_sdh *nu_sdh_t; + +/* Private variables ------------------------------------------------------------*/ +#if defined(BSP_USING_SDH0) + ALIGN(SDH_ALIGN_LEN) + static uint8_t g_au8CacheBuf_SDH0[SDH_BUFF_SIZE]; +#endif + +#if defined(BSP_USING_SDH1) + ALIGN(SDH_ALIGN_LEN) + static uint8_t g_au8CacheBuf_SDH1[SDH_BUFF_SIZE]; +#endif + +static struct nu_sdh nu_sdh_arr [] = +{ +#if defined(BSP_USING_SDH0) + { + .name = "sdh0", + .base = SDH0, + .irqn = SDH0_IRQn, + .rstidx = SDH0_RST, + .modid = SDH0_MODULE, + .cachebuf = g_au8CacheBuf_SDH0, + }, +#endif +#if defined(BSP_USING_SDH1) + { + .name = "sdh1", + .base = SDH1, + .irqn = SDH1_IRQn, + .rstidx = SDH1_RST, + .modid = SDH1_MODULE, + .cachebuf = g_au8CacheBuf_SDH1, + }, +#endif +}; /* struct nu_sdh nu_sdh_arr [] */ + +static uint32_t nu_sdh_get_cmd_resptype(uint32_t rt_resp_type) +{ + uint32_t nu_resptype = 0; + switch (rt_resp_type) + { + case RESP_NONE: + nu_resptype = MMC_RSP_NONE; + break; + case RESP_R1: + nu_resptype = MMC_RSP_R1; + break; + case RESP_R1B: + nu_resptype = MMC_RSP_R1b; + break; + case RESP_R2: + nu_resptype = MMC_RSP_R2; + break; + case RESP_R3: + nu_resptype = MMC_RSP_R3; + break; + case RESP_R4: + nu_resptype = MMC_RSP_R4; + break; + case RESP_R6: + nu_resptype = MMC_RSP_R6; + break; + case RESP_R7: + nu_resptype = MMC_RSP_R7; + break; + case RESP_R5: + nu_resptype = MMC_RSP_R5; + break; + default: + nu_resptype = 0xffffffff; + } + return nu_resptype ; +} + +static void nu_sdh_send_commanddone(SDH_T *sdh, struct mmc_cmd *cmd) +{ + if (cmd->resp_type & MMC_RSP_136) + { + /* CRC is stripped so we need to do some shifting. */ + cmd->response[0] = (sdh->RESP67 << 8) | sdh->S_RESP45.B3; + cmd->response[1] = (sdh->RESP45 << 8) | sdh->S_RESP23.B3; + cmd->response[2] = (sdh->RESP23 << 8) | sdh->S_RESP01.B3; + cmd->response[3] = (sdh->RESP01 << 8); + } + else + { + cmd->response[0] = sdh->RESP01; + cmd->response[1] = cmd->response[2] = cmd->response[3] = 0; + } +} + +static int nu_sdh_xfer_data(SDH_T *sdh, struct mmc_data *data) +{ + uint32_t start_addr, timeout; + + if (data->flags & DATA_DIR_READ) + { + start_addr = (uint32_t)data->dest; + } + else + { + start_addr = (uint32_t)data->src; + } + + timeout = 1000000; + + while (!sdh->S_NORMAL_INT_STAT.XFER_COMPLETE) /* SDHCI_INT_DATA_END? */ + { + if (sdh->S_NORMAL_INT_STAT.ERR_INTERRUPT == 1) + return -1; + + if (sdh->S_NORMAL_INT_STAT.DMA_INTERRUPT) /* SDHCI_INT_DMA_END */ + { + sdh->S_NORMAL_INT_STAT.DMA_INTERRUPT = 1; /* Clear SDHCI_INT_DMA_END */ + + start_addr &= ~(SDH_BLOCK_SIZE * 1024 - 1); + start_addr += SDH_BLOCK_SIZE * 1024; + + sdh->SDMASA = start_addr; + } + if (timeout-- > 0) + rt_hw_us_delay(10); + else + return -2; + } + + return 0; +} + +static void nu_sdh_list_errors(SDH_T *sdh) +{ + if (sdh->S_NORMAL_INT_STAT.ERR_INTERRUPT) + { + LOG_D("Error List:"); + if (sdh->S_ERROR_INT_STAT.CMD_TOUT_ERR) + LOG_D("\tCMD_TOUT_ERR."); + if (sdh->S_ERROR_INT_STAT.CMD_CRC_ERR) + LOG_D("\tCMD_CRC_ERR."); + if (sdh->S_ERROR_INT_STAT.CMD_END_BIT_ERR) + LOG_D("\tCMD_END_BIT_ERR."); + if (sdh->S_ERROR_INT_STAT.CMD_IDX_ERR) + LOG_D("\tCMD_IDX_ERR."); + if (sdh->S_ERROR_INT_STAT.DATA_TOUT_ERR) + LOG_D("\tDATA_TOUT_ERR."); + if (sdh->S_ERROR_INT_STAT.DATA_CRC_ERR) + LOG_D("\tDATA_CRC_ERR."); + if (sdh->S_ERROR_INT_STAT.DATA_END_BIT_ERR) + LOG_D("\tDATA_END_BIT_ERR."); + if (sdh->S_ERROR_INT_STAT.CUR_LMT_ERR) + LOG_D("\tCUR_LMT_ERR."); + + if (sdh->S_ERROR_INT_STAT.AUTO_CMD_ERR) + LOG_D("\tAUTO_CMD_ERR."); + if (sdh->S_ERROR_INT_STAT.ADMA_ERR) + LOG_D("\tADMA_ERR."); + if (sdh->S_ERROR_INT_STAT.TUNING_ERR) + LOG_D("\tTUNING_ERR."); + if (sdh->S_ERROR_INT_STAT.RESP_ERR) + LOG_D("\tRESP_ERR."); + if (sdh->S_ERROR_INT_STAT.BOOT_ACK_ERR) + LOG_D("\tBOOT_ACK_ERR."); + if (sdh->S_ERROR_INT_STAT.VENDOR_ERR1) + LOG_D("\tVENDOR_ERR1."); + if (sdh->S_ERROR_INT_STAT.VENDOR_ERR2) + LOG_D("\tVENDOR_ERR2."); + if (sdh->S_ERROR_INT_STAT.VENDOR_ERR3) + LOG_D("\tVENDOR_ERR3."); + } +} + +/** + * @brief This function send command. + * @param sdio rthw_sdio + * @param pkg sdio package + * @retval None + */ +static int nu_sdh_send_command(SDH_T *sdh, struct mmc_cmd *cmd, struct mmc_data *data) +{ + int ret; + uint32_t mask, flags, mode; + volatile unsigned int time = 0; + volatile unsigned int cmd_timeout, stat; + + LOG_D("[CMD:%d ARG:0x%08x] RESP_TYPE:0x%08x rw:%c addr:0x%08x len:%d blksize:%d", + cmd->cmdidx, + cmd->cmdarg, + cmd->resp_type, + data ? (data->flags & DATA_DIR_WRITE ? 'w' : 'r') : '-', + data ? data->src : 0, + data ? data->blocks * data->blocksize : 0, + data ? data->blocksize : 0); + + mask = 0x3; /* SDH_CMD_INHIBIT | SDH_DATA_INHIBIT */ + if (cmd->cmdidx == MMC_CMD_STOP_TRANSMISSION) + mask &= ~0x2; /* SDH_DATA_INHIBIT */ + + ret = SD_GetBusStatus(sdh, mask); + if (ret) + { + LOG_E("ERROR: Busy %d\n", ret); + ret = __LINE__; + goto exit_nu_sdh_send_command; + } + + /* SDHCI_INT_ALL_MASK */ + sdh->NORMAL_INT_STAT = 0xFFFF; + sdh->ERROR_INT_STAT = 0xFFFF; + + mask = 0x1; /* SDHCI_INT_RESPONSE */ + + if (!(cmd->resp_type & MMC_RSP_PRESENT)) + flags = SDH_CMD_RESP_NONE; + else if (cmd->resp_type & MMC_RSP_136) + flags = SDH_CMD_RESP_LONG; + else if (cmd->resp_type & MMC_RSP_BUSY) + { + flags = SDH_CMD_RESP_SHORT_BUSY; + if (data) + mask |= 0x2; /* SDHCI_INT_DATA_END */ + } + else + flags = SDH_CMD_RESP_SHORT; + + if (cmd->resp_type & MMC_RSP_CRC) + flags |= SDH_CMD_CRC; + + if (cmd->resp_type & MMC_RSP_OPCODE) + flags |= SDH_CMD_INDEX; + + /* Set Transfer mode regarding to data flag */ + if (data) + { + flags |= SDH_CMD_DATA; + + sdh->S_TOUT_CTRL.TOUT_CNT = 0xE; + + mode = 0x2; /* SDHCI_TRNS_BLK_CNT_EN */ + if (data->blocks > 1) + mode |= 0x20; /* SDHCI_TRNS_MULTI */ + + if (data->flags & DATA_DIR_READ) + { + mode |= 0x10; /* SDHCI_TRNS_READ */ + sdh->SDMASA = (uint32_t)data->dest; + } + else + { + sdh->SDMASA = (uint32_t)data->src; + } + + mode |= 0x1; + sdh->S_HOST_CTRL1.DMA_SEL = 0; //SDMA is selected + + /* 512 Kbytes SDMA Buffer Boundary */ + sdh->S_BLOCKSIZE.SDMA_BUF_BDARY = 0x7; + + /* Set Block Size */ + sdh->S_BLOCKSIZE.XFER_BLOCK_SIZE = data->blocksize; + + /* Set Block count */ + sdh->S_BLOCKCOUNT.BLOCK_CNT = data->blocks; + + /* Set transfer mode */ + sdh->XFER_MODE = mode; + } + else if (cmd->resp_type & MMC_RSP_BUSY) + { + sdh->S_TOUT_CTRL.TOUT_CNT = 0xE; + } + + sdh->ARGUMENT = cmd->cmdarg; + sdh->CMD = ((cmd->cmdidx & 0xff) << 8) | (flags & 0xff); + + cmd_timeout = 10000000; + time = 0; + do + { + stat = sdh->NORMAL_INT_STAT; + if (stat & 0x8000) /* SDHCI_INT_ERROR */ + break; + + if (time > cmd_timeout) + { + ret = __LINE__; + LOG_E("[%s %d] timeout stat=%04x, mask=%04x", __func__, __LINE__, stat, mask); + goto exit_nu_sdh_send_command; + } + time++; + } + while ((stat & mask) != mask); + + if ((stat & (0x8000 | mask)) == mask) + { + //LOG_D("[%s %d] Done. cmdid=%d restore", __func__, __LINE__, cmd->cmdidx); + + nu_sdh_send_commanddone(sdh, cmd); + nu_sdh_list_errors(sdh); + + /* Send data */ + if (data) + { + ret = nu_sdh_xfer_data(sdh, data); + } + stat = sdh->ERROR_INT_STAT; + + sdh->NORMAL_INT_STAT = mask; + ret = 0; + } + else + { + //LOG_E("[%s %d] Error. cmdid=%d not restored %08x %08x", __func__, __LINE__, cmd->cmdidx, stat, mask); + ret = __LINE__; + + nu_sdh_list_errors(sdh); + goto exit_nu_sdh_send_command; + } + + /* SDHCI_INT_ALL_MASK */ + sdh->NORMAL_INT_STAT = 0xFFFF; + sdh->ERROR_INT_STAT = 0xFFFF; + + if (ret) + { + LOG_E("[%s %d] ret=%d cmd->cmdidx=%d, error=0x%x", __func__, __LINE__, ret, cmd->cmdidx, stat); + ret = __LINE__; + goto exit_nu_sdh_send_command; + } + + return 0; + +exit_nu_sdh_send_command: + + SDH_Reset(sdh, SDH_RESET_CMD); + SDH_Reset(sdh, SDH_RESET_DATA); + + //LOG_E("[%s %d] cmdid=%d error line=%d", __func__, __LINE__, cmd->cmdidx, ret); + + return ret; +} + + +/** + * @brief This function send sdio request. + * @param host rt_mmcsd_host + * @param req request + * @retval None + */ +static void nu_sdh_request(struct rt_mmcsd_host *host, struct rt_mmcsd_req *req) +{ + nu_sdh_t sdh = (nu_sdh_t)host->private_data; + + RT_ASSERT(host); + RT_ASSERT(req); + + if (host->card) + { + if (host->card->card_type == CARD_TYPE_MMC) + { + sdh->base->S_EMMC_CTRL.CARD_IS_EMMC = 1; + sdh->base->S_EMMC_CTRL.DISABLE_DATA_CRC_CHK = 1; + } + else + { + sdh->base->S_EMMC_CTRL.CARD_IS_EMMC = 0; + sdh->base->S_EMMC_CTRL.DISABLE_DATA_CRC_CHK = 0; + } + } + + if (req->cmd != RT_NULL) + { + struct mmc_cmd cmd; + + LOG_D("[%s%s%s%s%s]REQ: CMD:%d ARG:0x%08x RESP_TYPE:0x%08x, 0x%08x", + (host->card == RT_NULL) ? "Unknown" : "", + (host->card) && (host->card->card_type == CARD_TYPE_MMC) ? "MMC" : "", + (host->card) && (host->card->card_type == CARD_TYPE_SD) ? "SD" : "", + (host->card) && (host->card->card_type == CARD_TYPE_SDIO) ? "SDIO" : "", + (host->card) && (host->card->card_type == CARD_TYPE_SDIO_COMBO) ? "SDIO_COMBO" : "", + req->cmd->cmd_code, + req->cmd->arg, + resp_type(req->cmd), + nu_sdh_get_cmd_resptype(resp_type(req->cmd))); + + rt_memset(&cmd, 0, sizeof(struct mmc_cmd)); + + cmd.cmdidx = req->cmd->cmd_code; + cmd.cmdarg = req->cmd->arg; + cmd.resp_type = nu_sdh_get_cmd_resptype(resp_type(req->cmd)); + + if (req->data != RT_NULL) + { + struct mmc_data data; + rt_uint32_t size; + rt_int32_t IsNonaligned = 0; + + + LOG_D("[%s]REQ: BUF:%08x FLAGS:0x%08x BLKSIZE:%d, BLKCOUNT:%d", + sdh->name, + req->data->buf, + req->data->flags, + req->data->blksize, + req->data->blks); + + rt_memset(&data, 0, sizeof(struct mmc_data)); + + data.dest = (char *)req->data->buf; + data.flags = req->data->flags; + data.blocksize = req->data->blksize; + data.blocks = req->data->blks; + + size = data.blocksize * data.blocks; + + RT_ASSERT(size <= SDH_BUFF_SIZE); + + IsNonaligned = (((rt_uint32_t)data.dest & (SDH_ALIGN_LEN - 1)) > 0) ? 1 : 0; + if (IsNonaligned) + { + data.dest = (char *)sdh->cachebuf; + if (data.flags & DATA_DIR_WRITE) + { + LOG_D("Un-aligned, prepare into cache buf(%d)", size); + rt_memcpy(data.dest, req->data->buf, size); + } + } + + rt_hw_cpu_dcache_clean_inv((void *)data.dest, size); + req->cmd->err = nu_sdh_send_command(sdh->base, &cmd, &data); + rt_hw_cpu_dcache_invalidate((void *)data.dest, size); + + if (!req->cmd->err && IsNonaligned) + { + if (data.flags & DATA_DIR_READ) + { + LOG_D("Un-aligned, restore from cache buf(%d)", size); + rt_memcpy(req->data->buf, data.dest, size); + } + } + LOG_HEX("data.dest", 16, (void *)data.dest, size); + + } + else + { + req->cmd->err = nu_sdh_send_command(sdh->base, &cmd, NULL); + } + + /* Report response words */ + req->cmd->resp[3] = cmd.response[3]; + req->cmd->resp[2] = cmd.response[2]; + req->cmd->resp[1] = cmd.response[1]; + req->cmd->resp[0] = cmd.response[0]; + + LOG_HEX("req->cmd->resp", 16, (void *)&req->cmd->resp[0], 16); + + } + + if (req->stop != RT_NULL) + { + struct mmc_cmd stop; + rt_memset(&stop, 0, sizeof(struct mmc_cmd)); + + stop.cmdidx = req->stop->cmd_code; + stop.cmdarg = req->stop->arg; + stop.resp_type = nu_sdh_get_cmd_resptype(resp_type(req->stop)); + + req->stop->err = nu_sdh_send_command(sdh->base, &stop, NULL); + + /* Report response words */ + req->stop->resp[3] = stop.response[3]; + req->stop->resp[2] = stop.response[2]; + req->stop->resp[1] = stop.response[1]; + req->stop->resp[0] = stop.response[0]; + + LOG_HEX("req->stop->resp", 16, (void *)&req->stop->resp[0], 16); + + } + + mmcsd_req_complete(host); +} + +/** + * @brief This function config sdio. + * @param host rt_mmcsd_host + * @param io_cfg rt_mmcsd_io_cfg + * @retval None + */ +static void nu_sdh_iocfg(struct rt_mmcsd_host *host, struct rt_mmcsd_io_cfg *io_cfg) +{ + nu_sdh_t NuSdh; + rt_uint32_t clk = io_cfg->clock; + SDH_T *sdh; + + RT_ASSERT(host); + RT_ASSERT(io_cfg); + + NuSdh = (nu_sdh_t)host->private_data; + sdh = NuSdh->base; + + LOG_D("[%s]clk:%d width:%s%s%s power:%s%s%s", + NuSdh->name, + clk, + io_cfg->bus_width == MMCSD_BUS_WIDTH_8 ? "8" : "", + io_cfg->bus_width == MMCSD_BUS_WIDTH_4 ? "4" : "", + io_cfg->bus_width == MMCSD_BUS_WIDTH_1 ? "1" : "", + io_cfg->power_mode == MMCSD_POWER_OFF ? "OFF" : "", + io_cfg->power_mode == MMCSD_POWER_UP ? "UP" : "", + io_cfg->power_mode == MMCSD_POWER_ON ? "ON" : ""); + + /* Bus width */ + switch (io_cfg->bus_width) + { + case MMCSD_BUS_WIDTH_1: + case MMCSD_BUS_WIDTH_4: + case MMCSD_BUS_WIDTH_8: + SDH_SetBusWidth(sdh, 1 << io_cfg->bus_width); + break; + default: + break; + } + + /* Power */ + switch (io_cfg->power_mode) + { + case MMCSD_POWER_UP: + case MMCSD_POWER_ON: + SDH_SetPower(sdh, 1); + break; + + case MMCSD_POWER_OFF: + SDH_SetPower(sdh, 0); + break; + default: + break; + } + + /* Clock */ + if (clk > host->freq_max) + clk = host->freq_max; + + if (clk < host->freq_min) + clk = host->freq_min; + + if (clk) + { + uint32_t u32SrcFreqInHz = 0, u32ModRealFreqInHz; + uint32_t u32ModSrcIdx = CLK_GetModuleClockSource(NuSdh->modid); + + switch (u32ModSrcIdx) + { + case 0: // From SYSPLL + u32SrcFreqInHz = CLK_GetPLLClockFreq(SYSPLL); + break; + default: // From APLL + u32SrcFreqInHz = CLK_GetPLLClockFreq(APLL); + break; + } + + u32ModRealFreqInHz = SDH_SetClock(sdh, u32SrcFreqInHz, clk); + u32ModRealFreqInHz = u32ModRealFreqInHz; //Avoid warning + + LOG_D("[%s] SrcClock: %d kHz, ExceptedFreq: %d kHz, RealFreq: %d kHz", NuSdh->name, u32SrcFreqInHz / 1000, clk / 1000, u32ModRealFreqInHz / 1000); + } + +} + +/** + * @brief This function detect sdcard. + * @param host rt_mmcsd_host + * @retval 0x01 + */ +static rt_int32_t nu_sdh_card_detect(struct rt_mmcsd_host *host) +{ + LOG_D("try to detect device"); + return 0x01; +} + +/** + * @brief This function interrupt process function. + * @param host rt_mmcsd_host + * @retval None + */ +static void nu_sdh_isr(int vector, void *param) +{ + nu_sdh_t sdh = (nu_sdh_t)param; + struct rt_mmcsd_host *host = sdh->host; + SDH_T *base = sdh->base; + volatile unsigned int isr = base->NORMAL_INT_STAT; + + /* We just catch card detection here. */ + if (isr & 0xc0) + { + /* ready to change */ + mmcsd_change(host); + base->NORMAL_INT_STAT = 0xC0; + } +} + +/** + * @brief This function update sdh interrupt. + * @param host rt_mmcsd_host + * @param enable + * @retval None + */ +void nu_sdh_irq_update(struct rt_mmcsd_host *host, rt_int32_t enable) +{ + nu_sdh_t sdh = (nu_sdh_t)host->private_data; + SDH_T *sdh_base = sdh->base; + + if (enable) + { + LOG_D("Enable %s irq", sdh->name); + + /* Enable only interrupts served by the SD controller */ + /* sdh_base->NORMAL_INT_STAT_EN = 0x00FB; */ + sdh_base->S_NORMAL_INT_STAT_EN.CMD_COMPLETE_STAT_EN = 1; + sdh_base->S_NORMAL_INT_STAT_EN.XFER_COMPLETE_STAT_EN = 1; + sdh_base->S_NORMAL_INT_STAT_EN.DMA_INTERRUPT_STAT_EN = 1; + + sdh_base->S_NORMAL_INT_STAT_EN.BUF_WR_READY_STAT_EN = 1; + sdh_base->S_NORMAL_INT_STAT_EN.BUF_RD_READY_STAT_EN = 1; + sdh_base->S_NORMAL_INT_STAT_EN.CARD_INSERTION_STAT_EN = 1; + sdh_base->S_NORMAL_INT_STAT_EN.CARD_REMOVAL_STAT_EN = 1; + + /* sdh_base->ERROR_INT_STAT_EN = 0x0271; */ + sdh_base->S_ERROR_INT_STAT_EN.CMD_TOUT_ERR_STAT_EN = 1; + sdh_base->S_ERROR_INT_STAT_EN.DATA_TOUT_ERR_STAT_EN = 1; + sdh_base->S_ERROR_INT_STAT_EN.DATA_CRC_ERR_STAT_EN = 1; + sdh_base->S_ERROR_INT_STAT_EN.DATA_END_BIT_ERR_STAT_EN = 1; + sdh_base->S_ERROR_INT_STAT_EN.ADMA_ERR_STAT_EN = 1; + + /* Mask all interrupt sources */ + /* sdh_base->NORMAL_INT_SIGNAL_EN = 0xC0; */ + sdh_base->S_NORMAL_INT_SIGNAL_EN.CARD_INSERTION_SIGNAL_EN = 1; + sdh_base->S_NORMAL_INT_SIGNAL_EN.CARD_REMOVAL_SIGNAL_EN = 1; + + sdh_base->ERROR_INT_SIGNAL_EN = 0; + + //sdh_base->NORMAL_INT_STAT_EN = 0x7FFF; + //sdh_base->ERROR_INT_STAT_EN = 0xFFFF; + //sdh_base->NORMAL_INT_SIGNAL_EN=0x7FFF; + //sdh_base->ERROR_INT_SIGNAL_EN=0xFFFF; + } + else + { + LOG_D("Disable %s irq", sdh->name); + + sdh_base->NORMAL_INT_STAT_EN = 0x0; + sdh_base->ERROR_INT_STAT_EN = 0x0; + sdh_base->NORMAL_INT_SIGNAL_EN = 0x0; + sdh_base->ERROR_INT_SIGNAL_EN = 0x0; + } +} + +static const struct rt_mmcsd_host_ops ops = +{ + nu_sdh_request, + nu_sdh_iocfg, + nu_sdh_card_detect, + nu_sdh_irq_update, +}; + +/** + * @brief This function create mmcsd host. + * @param sdh nu_sdh_t + * @retval nuvton + */ +void nu_sdh_host_initial(nu_sdh_t sdh) +{ + struct rt_mmcsd_host *host; + rt_err_t ret = RT_EOK; + + host = mmcsd_alloc_host(); + RT_ASSERT(host != RT_NULL); + + ret = rt_event_init(&sdh->event, "sdh_event", RT_IPC_FLAG_FIFO); + RT_ASSERT(ret == RT_EOK); + + /* Reset sdh at first. */ + SDH_Reset(sdh->base, SDH_RESET_ALL); + + /* set host default attributes */ + host->ops = &ops; + host->freq_min = 200 * 1000; + host->freq_max = 50 * 1000 * 1000; + host->valid_ocr = VDD_30_31 | VDD_31_32 | VDD_32_33 | VDD_33_34; // | VDD_165_195; + + host->flags = MMCSD_BUSWIDTH_4 | MMCSD_MUTBLKWRITE | MMCSD_SUP_SDIO_IRQ | MMCSD_SUP_HIGHSPEED; + + host->max_seg_size = SDH_BUFF_SIZE; + host->max_dma_segs = 1; + host->max_blk_size = SDH_BLOCK_SIZE; + host->max_blk_count = (SDH_BUFF_SIZE / SDH_BLOCK_SIZE); + + /* link up host and sdio */ + host->private_data = sdh; + sdh->host = host; + + /* Set initial state: high speed */ + sdh->base->S_HOST_CTRL1.HIGH_SPEED_EN = 1; + + /* Set SDR50 mode */ + sdh->base->S_HOST_CTRL2.UHS_MODE_SEL = 2; + + /* Install ISR. */ + rt_hw_interrupt_install(sdh->irqn, nu_sdh_isr, (void *)sdh, sdh->name); + rt_hw_interrupt_umask(sdh->irqn); + + /* Enable interrupt. */ + nu_sdh_irq_update(host, 1); + + /* ready to change */ + mmcsd_change(host); +} + +void nu_sd_attach(void) +{ + int i; + /* ready to change */ + for (i = (SDH_START + 1); i < SDH_CNT; i++) + { + if (nu_sdh_arr[i].host) + mmcsd_change(nu_sdh_arr[i].host); + } +} +MSH_CMD_EXPORT(nu_sd_attach, attach card); + +void nu_sd_regdump(void) +{ + int i; + /* ready to change */ + for (i = (SDH_START + 1); i < SDH_CNT; i++) + { + if (nu_sdh_arr[i].host) + SDH_DumpReg(nu_sdh_arr[i].base); + } +} +MSH_CMD_EXPORT(nu_sd_regdump, dump sdh registers); + +static int rt_hw_sdh_init(void) +{ + int i; + + for (i = (SDH_START + 1); i < SDH_CNT; i++) + { + CLK_EnableModuleClock(nu_sdh_arr[i].modid); + SYS_ResetModule(nu_sdh_arr[i].rstidx); + + nu_sdh_host_initial(&nu_sdh_arr[i]); + } + + return 0; +} +INIT_DEVICE_EXPORT(rt_hw_sdh_init); + +/* A simple MBR writer. */ +struct mbr +{ + uint8_t code[440]; + union + { + uint32_t disk_signature; + struct + { + uint32_t disk_signature_B0: 8; + uint32_t disk_signature_B1: 8; + uint32_t disk_signature_B2: 8; + uint32_t disk_signature_B3: 8; + } s_disk_signature; + }; + uint16_t unused; + struct mbr_partition + { + uint8_t status; + + uint8_t first_cylinder; + uint8_t first_head; + uint8_t first_sector; + + uint8_t partition_type; + + uint8_t last_cylinder; + uint8_t last_head; + uint8_t last_sector; + + union + { + uint32_t first_sector_lba; + struct + { + uint32_t first_sector_lba_B0: 8; + uint32_t first_sector_lba_B1: 8; + uint32_t first_sector_lba_B2: 8; + uint32_t first_sector_lba_B3: 8; + } s_first_sector_lba; + }; + + union + { + uint32_t sectors ; + struct + { + uint32_t sectors_B0: 8; + uint32_t sectors_B1: 8; + uint32_t sectors_B2: 8; + uint32_t sectors_B3: 8; + } s_sectors; + }; + + } partition[4]; + + uint16_t mbr_signature; + +} __attribute__((packed)); + +#define MBR_SIGNATURE 0xAA55 +#define MBR_STATUS_BOOTABLE 0x80 + +#define le2(a, o) ((a)[o] << 0 | (a)[(o)+1] << 8) +#define le4(a, o) (le2(a,o) | (a)[(o)+2] << 16 | (a)[(o)+3] << 24) + +static int nu_sd_mbr_read(const char *devname) +{ + rt_device_t mmc_device = RT_NULL; + rt_err_t ret; + struct rt_device_blk_geometry geo = {0}; + struct mbr *psMbr = RT_NULL; + + if ((mmc_device = rt_device_find(devname)) == RT_NULL) + { + LOG_E("find device %s failed!\n", devname); + goto fail_nu_sd_mbr_read; + } + + if (rt_device_open(mmc_device, RT_DEVICE_OFLAG_RDWR) != RT_EOK) + { + LOG_E("open device %s failed!\n", devname); + mmc_device = RT_NULL; + goto fail_nu_sd_mbr_read; + } + + if (rt_device_control(mmc_device, RT_DEVICE_CTRL_BLK_GETGEOME, &geo) != RT_EOK) + { + LOG_E("control device %s failed!\n", devname); + goto fail_nu_sd_mbr_read; + } + + LOG_I("device information:\n"); + LOG_I("sector size : %d byte\n", geo.bytes_per_sector); + LOG_I("sector count : %d \n", geo.sector_count); + LOG_I("block size : %d byte\n", geo.block_size); + LOG_I("MBR size : %d byte\n", sizeof(struct mbr)); + + psMbr = rt_malloc(sizeof(struct mbr)); + if (psMbr == RT_NULL) + { + LOG_E("no memory for mbr buffer!\n"); + goto fail_nu_sd_mbr_read; + } + rt_memset(psMbr, 0, sizeof(struct mbr)); + + ret = rt_device_read(mmc_device, 0, psMbr, 1); + if (ret != 1) + { + LOG_E("read device %s %d failed!\n", devname, ret); + goto fail_nu_sd_mbr_read; + } + + LOG_I("disk_signature = %08x\n", psMbr->disk_signature); + LOG_I("unused = %02x\n", psMbr->unused); + for (int i = 0; i < 4; i++) + { + LOG_I("[%d] status = %02x\n", i, psMbr->partition[i].status); + LOG_I("[%d] first_cylinder = %d\n", i, psMbr->partition[i].first_cylinder); + LOG_I("[%d] first_head = %d\n", i, psMbr->partition[i].first_head); + LOG_I("[%d] first_sector = %d\n", i, psMbr->partition[i].first_sector); + LOG_I("[%d] partition_type = %02x\n", i, psMbr->partition[i].partition_type); + LOG_I("[%d] last_cylinder = %d\n", i, psMbr->partition[i].last_cylinder); + LOG_I("[%d] last_head = %d\n", i, psMbr->partition[i].last_head); + LOG_I("[%d] last_sector = %d\n", i, psMbr->partition[i].last_sector); + LOG_I("[%d] first_sector_lba = %u\n", i, psMbr->partition[i].first_sector_lba); + LOG_I("[%d] sectors = %u\n", i, psMbr->partition[i].sectors); + } + + LOG_I("signature = %02x\n", psMbr->mbr_signature); + + rt_free(psMbr); + + rt_device_close(mmc_device); + + return 0; + +fail_nu_sd_mbr_read: + + if (psMbr != RT_NULL) + rt_free(psMbr); + + if (mmc_device != RT_NULL) + rt_device_close(mmc_device); + + return -1; +} + + +int nu_sd_mbr_dump(int argc, char *argv[]) +{ +// argc=1: string, mmcblk device name. + if (argc != 2) + return -1; + return nu_sd_mbr_read(argv[1]); +} +MSH_CMD_EXPORT(nu_sd_mbr_dump, dump sd card device); + +static int nu_sd_mbr_write(const char *devname, int32_t u32Sectors) +{ + rt_device_t mmc_device = RT_NULL; + rt_err_t ret; + struct rt_device_blk_geometry geo; + struct mbr *psMbr = RT_NULL; + + if ((mmc_device = rt_device_find(devname)) == RT_NULL) + { + LOG_E("find device %s failed!\n", devname); + goto fail_nu_sd_mbr_write; + } + + if (rt_device_open(mmc_device, RT_DEVICE_OFLAG_RDWR) != RT_EOK) + { + mmc_device = RT_NULL; + LOG_E("open device %s failed!\n", devname); + goto fail_nu_sd_mbr_write; + } + + rt_memset(&geo, 0, sizeof(geo)); + ret = rt_device_control(mmc_device, RT_DEVICE_CTRL_BLK_GETGEOME, &geo); + if (ret != RT_EOK) + { + LOG_E("control device %s failed!\n", devname); + goto fail_nu_sd_mbr_write; + } + LOG_I("device information:\n"); + LOG_I("sector size : %d byte\n", geo.bytes_per_sector); + LOG_I("sector count : %d \n", geo.sector_count); + LOG_I("block size : %d byte\n", geo.block_size); + + if (u32Sectors >= geo.sector_count) + { + LOG_E("no enough sectors for reserved. %s failed!\n", devname); + goto fail_nu_sd_mbr_write; + } + + psMbr = rt_malloc(sizeof(struct mbr)); + if (psMbr == RT_NULL) + { + LOG_E("no memory for mbr buffer!\n"); + goto fail_nu_sd_mbr_write; + } + rt_memset(psMbr, 0, sizeof(struct mbr)); + + psMbr->disk_signature = 0xa8e7d068; + psMbr->mbr_signature = MBR_SIGNATURE; + + psMbr->partition[0].status = 0; + + //psMbr->partition[0].first_cylinder = 0x00; + //psMbr->partition[0].first_head = 0x21; + //psMbr->partition[0].first_sector = 0x21; + psMbr->partition[0].partition_type = 0x0C; + //psMbr->partition[0].last_head = 0xFE; + //psMbr->partition[0].last_sector = 0x3F; + //psMbr->partition[0].last_cylinder = 0xFF; + psMbr->partition[0].first_sector_lba = u32Sectors; + psMbr->partition[0].sectors = geo.sector_count - u32Sectors; + + ret = rt_device_write(mmc_device, 0, psMbr, 1); + if (ret != 1) + { + LOG_E("write device %s %d failed!\n", devname, ret); + goto fail_nu_sd_mbr_write; + } + +fail_nu_sd_mbr_write: + + if (psMbr != RT_NULL) + rt_free(psMbr); + + if (mmc_device) + rt_device_close(mmc_device); + + return -1; +} + +int nu_sd_mbr_layout(int argc, char *argv[]) +{ +// argc=1: string, mmcblk device name. +// argc=2: Reserved sectors for bootable code and remains sectors are for elm mounting. + + if (argc != 3) + return -1; + + return nu_sd_mbr_write((const char *)argv[1], atoi(argv[2])); +} +MSH_CMD_EXPORT(nu_sd_mbr_layout, layout sd device); + +#endif diff --git a/bsp/nuvoton/libraries/ma35/rtt_port/drv_softi2c.c b/bsp/nuvoton/libraries/ma35/rtt_port/drv_softi2c.c new file mode 100644 index 0000000000..69462bfa39 --- /dev/null +++ b/bsp/nuvoton/libraries/ma35/rtt_port/drv_softi2c.c @@ -0,0 +1,232 @@ +/**************************************************************************//** +* +* @copyright (C) 2020 Nuvoton Technology Corp. All rights reserved. +* +* SPDX-License-Identifier: Apache-2.0 +* +* Change Logs: +* Date Author Notes +* 2021-9-6 Wayne First version +* +******************************************************************************/ + +#include + +#if (defined(BSP_USING_SOFT_I2C) && defined(RT_USING_I2C_BITOPS) && defined(RT_USING_I2C) && defined(RT_USING_PIN)) + +#include +#include +#include +#include "NuMicro.h" + +/* Private define ---------------------------------------------------------------*/ +#define LOG_TAG "drv.softi2c" +#define DBG_ENABLE +#define DBG_SECTION_NAME LOG_TAG +#define DBG_LEVEL DBG_INFO +#include + +#ifdef BSP_USING_SOFT_I2C0 +#define NU_SOFT_I2C0_BUS_CONFIG \ + { \ + .scl = BSP_SOFT_I2C0_SCL_PIN, \ + .sda = BSP_SOFT_I2C0_SDA_PIN, \ + .bus_name = "softi2c0", \ + } +#endif + +#ifdef BSP_USING_SOFT_I2C1 +#define NU_SOFT_I2C1_BUS_CONFIG \ + { \ + .scl = BSP_SOFT_I2C1_SCL_PIN, \ + .sda = BSP_SOFT_I2C1_SDA_PIN, \ + .bus_name = "softi2c1", \ + } +#endif + +#if (!defined(BSP_USING_SOFT_I2C0) && !defined(BSP_USING_SOFT_I2C1)) + #error "Please define at least one BSP_USING_SOFT_I2Cx" + /* this driver can be disabled at menuconfig ? RT-Thread Components ? Device Drivers */ +#endif + +/* Private typedef --------------------------------------------------------------*/ +/* soft i2c config class */ +struct nu_soft_i2c_config +{ + rt_uint8_t scl; + rt_uint8_t sda; + const char *bus_name; +}; +/* soft i2c driver class */ +struct nu_soft_i2c +{ + struct rt_i2c_bit_ops ops; + struct rt_i2c_bus_device soft_i2c_bus; +}; + +/* Private functions ------------------------------------------------------------*/ +static void nu_soft_i2c_udelay(rt_uint32_t us); +static void nu_soft_i2c_set_sda(void *data, rt_int32_t state); +static void nu_soft_i2c_set_scl(void *data, rt_int32_t state); +static rt_int32_t nu_soft_i2c_get_sda(void *data); +static rt_int32_t nu_soft_i2c_get_scl(void *data); + +/* Private variables ------------------------------------------------------------*/ +static const struct nu_soft_i2c_config nu_soft_i2c_cfg[] = +{ +#ifdef BSP_USING_SOFT_I2C0 + NU_SOFT_I2C0_BUS_CONFIG, +#endif +#ifdef BSP_USING_SOFT_I2C1 + NU_SOFT_I2C1_BUS_CONFIG, +#endif +}; + +static struct nu_soft_i2c nu_soft_i2c_obj[sizeof(nu_soft_i2c_cfg) / sizeof(nu_soft_i2c_cfg[0])]; + +static const struct rt_i2c_bit_ops nu_soft_i2c_bit_ops = +{ + .data = RT_NULL, + .set_sda = nu_soft_i2c_set_sda, + .set_scl = nu_soft_i2c_set_scl, + .get_sda = nu_soft_i2c_get_sda, + .get_scl = nu_soft_i2c_get_scl, + .udelay = nu_soft_i2c_udelay, + .delay_us = 1, + .timeout = 100 +}; + +/* Functions define ------------------------------------------------------------*/ + +/** + * The time delay function. + * + * @param microseconds. + */ +static void nu_soft_i2c_udelay(rt_uint32_t us) +{ + rt_hw_us_delay(us); +} + +/** + * This function initializes the soft i2c pin. + * + * @param soft i2c config class. + */ +static void nu_soft_i2c_gpio_init(const struct nu_soft_i2c_config *cfg) +{ + rt_pin_mode(cfg->scl, PIN_MODE_OUTPUT_OD); + rt_pin_mode(cfg->sda, PIN_MODE_OUTPUT_OD); + + rt_pin_write(cfg->scl, PIN_HIGH); + rt_pin_write(cfg->sda, PIN_HIGH); +} + +/** + * if i2c is locked, this function will unlock it + * + * @param soft i2c config class + * + * @return RT_EOK indicates successful unlock. + */ +static rt_err_t nu_soft_i2c_bus_unlock(const struct nu_soft_i2c_config *cfg) +{ + rt_int32_t i = 0; + + if (PIN_LOW == rt_pin_read(cfg->sda)) + { + while (i++ < 9) + { + rt_pin_write(cfg->scl, PIN_HIGH); + nu_soft_i2c_udelay(100); + rt_pin_write(cfg->scl, PIN_LOW); + nu_soft_i2c_udelay(100); + } + } + if (PIN_LOW == rt_pin_read(cfg->sda)) + { + return -RT_ERROR; + } + + return RT_EOK; +} + +/** + * This function sets the sda pin. + * + * @param soft i2c config class. + * @param The sda pin state. + */ +static void nu_soft_i2c_set_sda(void *data, rt_int32_t state) +{ + struct nu_soft_i2c_config *cfg = (struct nu_soft_i2c_config *)data; + + rt_pin_write(cfg->sda, state ? PIN_HIGH : PIN_LOW); +} + +/** + * This function sets the scl pin. + * + * @param soft i2c config class. + * @param The scl pin state. + */ +static void nu_soft_i2c_set_scl(void *data, rt_int32_t state) +{ + struct nu_soft_i2c_config *cfg = (struct nu_soft_i2c_config *)data; + + rt_pin_write(cfg->scl, state ? PIN_HIGH : PIN_LOW); +} + +/** + * This function gets the sda pin state. + * + * @param The sda pin state. + */ +static rt_int32_t nu_soft_i2c_get_sda(void *data) +{ + struct nu_soft_i2c_config *cfg = (struct nu_soft_i2c_config *)data; + + return rt_pin_read(cfg->sda); +} + +/** + * This function gets the scl pin state. + * + * @param The scl pin state. + */ +static rt_int32_t nu_soft_i2c_get_scl(void *data) +{ + struct nu_soft_i2c_config *cfg = (struct nu_soft_i2c_config *)data; + + return rt_pin_read(cfg->scl); +} + +/* Soft I2C initialization function */ +int rt_soft_i2c_init(void) +{ + rt_size_t obj_num = sizeof(nu_soft_i2c_obj) / sizeof(struct nu_soft_i2c); + rt_err_t result; + + for (int i = 0; i < obj_num; i++) + { + nu_soft_i2c_obj[i].ops = nu_soft_i2c_bit_ops; + nu_soft_i2c_obj[i].ops.data = (void *)&nu_soft_i2c_cfg[i]; + nu_soft_i2c_obj[i].soft_i2c_bus.priv = &nu_soft_i2c_obj[i].ops; + nu_soft_i2c_gpio_init(&nu_soft_i2c_cfg[i]); + + result = rt_i2c_bit_add_bus(&nu_soft_i2c_obj[i].soft_i2c_bus, nu_soft_i2c_cfg[i].bus_name); + RT_ASSERT(result == RT_EOK); + + nu_soft_i2c_bus_unlock(&nu_soft_i2c_cfg[i]); + + LOG_D("software simulation %s init done, pin scl: %d, pin sda %d", + nu_soft_i2c_cfg[i].bus_name, + nu_soft_i2c_cfg[i].scl, + nu_soft_i2c_cfg[i].sda); + } + + return 0; +} +INIT_DEVICE_EXPORT(rt_soft_i2c_init); + +#endif //#if (defined(BSP_USING_SOFT_I2C) && defined(RT_USING_I2C_BITOPS) && defined(RT_USING_I2C) && defined(RT_USING_PIN)) diff --git a/bsp/nuvoton/libraries/ma35/rtt_port/drv_spi.c b/bsp/nuvoton/libraries/ma35/rtt_port/drv_spi.c new file mode 100644 index 0000000000..e8d2a69c9d --- /dev/null +++ b/bsp/nuvoton/libraries/ma35/rtt_port/drv_spi.c @@ -0,0 +1,726 @@ +/**************************************************************************//** +* +* @copyright (C) 2020 Nuvoton Technology Corp. All rights reserved. +* +* SPDX-License-Identifier: Apache-2.0 +* +* Change Logs: +* Date Author Notes +* 2020-11-11 Wayne First version +* +******************************************************************************/ +#include + +#if defined(BSP_USING_SPI) + +#define LOG_TAG "drv.spi" +#define DBG_ENABLE +#define DBG_SECTION_NAME LOG_TAG +#define DBG_LEVEL DBG_INFO +#define DBG_COLOR +#include + +#include +#include +#include + +#include + + +/* Private define ---------------------------------------------------------------*/ + +#ifndef NU_SPI_USE_PDMA_MIN_THRESHOLD + #define NU_SPI_USE_PDMA_MIN_THRESHOLD (128) +#endif + +enum +{ + SPI_START = -1, +#if defined(BSP_USING_SPI0) + SPI0_IDX, +#endif +#if defined(BSP_USING_SPI1) + SPI1_IDX, +#endif +#if defined(BSP_USING_SPI2) + SPI2_IDX, +#endif +#if defined(BSP_USING_SPI3) + SPI3_IDX, +#endif + SPI_CNT +}; + +/* Private typedef --------------------------------------------------------------*/ + +/* Private functions ------------------------------------------------------------*/ +static void nu_spi_transmission_with_poll(struct nu_spi *spi_bus, + uint8_t *send_addr, uint8_t *recv_addr, int length, uint8_t bytes_per_word); +static int nu_spi_register_bus(struct nu_spi *spi_bus, const char *name); +static rt_uint32_t nu_spi_bus_xfer(struct rt_spi_device *device, struct rt_spi_message *message); +static rt_err_t nu_spi_bus_configure(struct rt_spi_device *device, struct rt_spi_configuration *configuration); + +#if defined(BSP_USING_SPI_PDMA) + static void nu_pdma_spi_rx_cb_event(void *pvUserData, uint32_t u32EventFilter); + static rt_err_t nu_pdma_spi_rx_config(struct nu_spi *spi_bus, uint8_t *pu8Buf, int32_t i32RcvLen, uint8_t bytes_per_word); + static rt_err_t nu_pdma_spi_tx_config(struct nu_spi *spi_bus, const uint8_t *pu8Buf, int32_t i32SndLen, uint8_t bytes_per_word); + static rt_size_t nu_spi_pdma_transmit(struct nu_spi *spi_bus, const uint8_t *send_addr, uint8_t *recv_addr, int length, uint8_t bytes_per_word); +#endif +/* Public functions -------------------------------------------------------------*/ +void nu_spi_transfer(struct nu_spi *spi_bus, uint8_t *tx, uint8_t *rx, int length, uint8_t bytes_per_word); +void nu_spi_drain_rxfifo(SPI_T *spi_base); + +/* Private variables ------------------------------------------------------------*/ +static struct rt_spi_ops nu_spi_poll_ops = +{ + .configure = nu_spi_bus_configure, + .xfer = nu_spi_bus_xfer, +}; + +static struct nu_spi nu_spi_arr [] = +{ +#if defined(BSP_USING_SPI0) + { + .name = "spi0", + .spi_base = SPI0, + .rstidx = SPI0_RST, +#if defined(BSP_USING_SPI_PDMA) +#if defined(BSP_USING_SPI0_PDMA) + .pdma_perp_tx = PDMA_SPI0_TX, + .pdma_perp_rx = PDMA_SPI0_RX, +#else + .pdma_perp_tx = NU_PDMA_UNUSED, + .pdma_perp_rx = NU_PDMA_UNUSED, +#endif +#endif + }, +#endif +#if defined(BSP_USING_SPI1) + { + .name = "spi1", + .spi_base = SPI1, + .rstidx = SPI1_RST, +#if defined(BSP_USING_SPI_PDMA) +#if defined(BSP_USING_SPI1_PDMA) + .pdma_perp_tx = PDMA_SPI1_TX, + .pdma_perp_rx = PDMA_SPI1_RX, +#else + .pdma_perp_tx = NU_PDMA_UNUSED, + .pdma_perp_rx = NU_PDMA_UNUSED, +#endif +#endif + }, +#endif +#if defined(BSP_USING_SPI2) + { + .name = "spi2", + .spi_base = SPI2, + .rstidx = SPI2_RST, +#if defined(BSP_USING_SPI_PDMA) +#if defined(BSP_USING_SPI2_PDMA) + .pdma_perp_tx = PDMA_SPI2_TX, + .pdma_perp_rx = PDMA_SPI2_RX, +#else + .pdma_perp_tx = NU_PDMA_UNUSED, + .pdma_perp_rx = NU_PDMA_UNUSED, +#endif +#endif + }, +#endif +#if defined(BSP_USING_SPI3) + { + .name = "spi3", + .spi_base = SPI3, + .rstidx = SPI3_RST, +#if defined(BSP_USING_SPI_PDMA) +#if defined(BSP_USING_SPI3_PDMA) + .pdma_perp_tx = PDMA_SPI3_TX, + .pdma_perp_rx = PDMA_SPI3_RX, +#else + .pdma_perp_tx = NU_PDMA_UNUSED, + .pdma_perp_rx = NU_PDMA_UNUSED, +#endif +#endif + }, +#endif +}; /* spi nu_spi */ + +static rt_err_t nu_spi_bus_configure(struct rt_spi_device *device, + struct rt_spi_configuration *configuration) +{ + struct nu_spi *spi_bus; + uint32_t u32SPIMode; + rt_err_t ret = RT_EOK; + void *pvUserData; + + RT_ASSERT(device != RT_NULL); + RT_ASSERT(configuration != RT_NULL); + + spi_bus = (struct nu_spi *) device->bus; + pvUserData = device->parent.user_data; + + /* Check mode */ + switch (configuration->mode & RT_SPI_MODE_3) + { + case RT_SPI_MODE_0: + u32SPIMode = SPI_MODE_0; + break; + case RT_SPI_MODE_1: + u32SPIMode = SPI_MODE_1; + break; + case RT_SPI_MODE_2: + u32SPIMode = SPI_MODE_2; + break; + case RT_SPI_MODE_3: + u32SPIMode = SPI_MODE_3; + break; + default: + ret = RT_EIO; + goto exit_nu_spi_bus_configure; + } + + /* Check data width */ + if (!(configuration->data_width == 8 || + configuration->data_width == 16 || + configuration->data_width == 24 || + configuration->data_width == 32)) + { + ret = RT_EINVAL; + goto exit_nu_spi_bus_configure; + } + + /* Need to initialize new configuration? */ + if (rt_memcmp(configuration, &spi_bus->configuration, sizeof(*configuration)) != 0) + { + rt_memcpy(&spi_bus->configuration, configuration, sizeof(*configuration)); + + SPI_Open(spi_bus->spi_base, SPI_MASTER, u32SPIMode, configuration->data_width, configuration->max_hz); + + if (configuration->mode & RT_SPI_CS_HIGH) + { + /* Set CS pin to LOW */ + if (pvUserData != RT_NULL) + { + // set to LOW */ + rt_pin_write(*((rt_base_t *)pvUserData), PIN_LOW); + } + else + { + SPI_SET_SS_LOW(spi_bus->spi_base); + } + } + else + { + /* Set CS pin to HIGH */ + if (pvUserData != RT_NULL) + { + // set to HIGH */ + rt_pin_write(*((rt_base_t *)pvUserData), PIN_HIGH); + } + else + { + /* Set CS pin to HIGH */ + SPI_SET_SS_HIGH(spi_bus->spi_base); + } + } + + if (configuration->mode & RT_SPI_MSB) + { + /* Set sequence to MSB first */ + SPI_SET_MSB_FIRST(spi_bus->spi_base); + } + else + { + /* Set sequence to LSB first */ + SPI_SET_LSB_FIRST(spi_bus->spi_base); + } + } + + /* Clear SPI RX FIFO */ + nu_spi_drain_rxfifo(spi_bus->spi_base); + +exit_nu_spi_bus_configure: + + return -(ret); +} + +#if defined(BSP_USING_SPI_PDMA) +static void nu_pdma_spi_rx_cb_event(void *pvUserData, uint32_t u32EventFilter) +{ + rt_err_t result = RT_EOK; + struct nu_spi *spi_bus = (struct nu_spi *)pvUserData; + + RT_ASSERT(spi_bus != RT_NULL); + + result = rt_sem_release(spi_bus->m_psSemBus); + RT_ASSERT(result == RT_EOK); +} + +static void nu_pdma_spi_tx_cb_trigger(void *pvUserData, uint32_t u32UserData) +{ + /* Get base address of spi register */ + SPI_T *spi_base = (SPI_T *)pvUserData; + + /* Trigger TX/RX PDMA transfer. */ + SPI_TRIGGER_TX_RX_PDMA(spi_base); +} + +static void nu_pdma_spi_rx_cb_disable(void *pvUserData, uint32_t u32UserData) +{ + /* Get base address of spi register */ + SPI_T *spi_base = (SPI_T *)pvUserData; + + /* Stop TX/RX DMA transfer. */ + SPI_DISABLE_TX_RX_PDMA(spi_base); +} + +static rt_err_t nu_pdma_spi_rx_config(struct nu_spi *spi_bus, uint8_t *pu8Buf, int32_t i32RcvLen, uint8_t bytes_per_word) +{ + struct nu_pdma_chn_cb sChnCB; + + rt_err_t result = RT_EOK; + rt_uint8_t *dst_addr = NULL; + nu_pdma_memctrl_t memctrl = eMemCtl_Undefined; + + /* Get base address of spi register */ + SPI_T *spi_base = spi_bus->spi_base; + + rt_uint8_t spi_pdma_rx_chid = spi_bus->pdma_chanid_rx; + + nu_pdma_filtering_set(spi_pdma_rx_chid, NU_PDMA_EVENT_TRANSFER_DONE); + + /* Register ISR callback function */ + sChnCB.m_eCBType = eCBType_Event; + sChnCB.m_pfnCBHandler = nu_pdma_spi_rx_cb_event; + sChnCB.m_pvUserData = (void *)spi_bus; + result = nu_pdma_callback_register(spi_pdma_rx_chid, &sChnCB); + if (result != RT_EOK) + { + goto exit_nu_pdma_spi_rx_config; + } + + /* Register Disable engine dma trigger callback function */ + sChnCB.m_eCBType = eCBType_Disable; + sChnCB.m_pfnCBHandler = nu_pdma_spi_rx_cb_disable; + sChnCB.m_pvUserData = (void *)spi_base; + result = nu_pdma_callback_register(spi_pdma_rx_chid, &sChnCB); + if (result != RT_EOK) + { + goto exit_nu_pdma_spi_rx_config; + } + + if (pu8Buf == RT_NULL) + { + memctrl = eMemCtl_SrcFix_DstFix; + dst_addr = (rt_uint8_t *) &spi_bus->dummy; + } + else + { + memctrl = eMemCtl_SrcFix_DstInc; + dst_addr = pu8Buf; + } + + result = nu_pdma_channel_memctrl_set(spi_pdma_rx_chid, memctrl); + if (result != RT_EOK) + { + goto exit_nu_pdma_spi_rx_config; + } + + result = nu_pdma_transfer(spi_pdma_rx_chid, + bytes_per_word * 8, + (uint32_t)&spi_base->RX, + (uint32_t)dst_addr, + i32RcvLen / bytes_per_word, + 0); +exit_nu_pdma_spi_rx_config: + + return result; +} + +static rt_err_t nu_pdma_spi_tx_config(struct nu_spi *spi_bus, const uint8_t *pu8Buf, int32_t i32SndLen, uint8_t bytes_per_word) +{ + struct nu_pdma_chn_cb sChnCB; + + rt_err_t result = RT_EOK; + rt_uint8_t *src_addr = NULL; + nu_pdma_memctrl_t memctrl = eMemCtl_Undefined; + + /* Get base address of spi register */ + SPI_T *spi_base = spi_bus->spi_base; + + rt_uint8_t spi_pdma_tx_chid = spi_bus->pdma_chanid_tx; + + if (pu8Buf == RT_NULL) + { + spi_bus->dummy = 0; + memctrl = eMemCtl_SrcFix_DstFix; + src_addr = (rt_uint8_t *)&spi_bus->dummy; + } + else + { + memctrl = eMemCtl_SrcInc_DstFix; + src_addr = (rt_uint8_t *)pu8Buf; + } + + /* Register Disable engine dma trigger callback function */ + sChnCB.m_eCBType = eCBType_Trigger; + sChnCB.m_pfnCBHandler = nu_pdma_spi_tx_cb_trigger; + sChnCB.m_pvUserData = (void *)spi_base; + result = nu_pdma_callback_register(spi_pdma_tx_chid, &sChnCB); + if (result != RT_EOK) + { + goto exit_nu_pdma_spi_tx_config; + } + + result = nu_pdma_channel_memctrl_set(spi_pdma_tx_chid, memctrl); + if (result != RT_EOK) + { + goto exit_nu_pdma_spi_tx_config; + } + + result = nu_pdma_transfer(spi_pdma_tx_chid, + bytes_per_word * 8, + (uint32_t)src_addr, + (uint32_t)&spi_base->TX, + i32SndLen / bytes_per_word, + 0); +exit_nu_pdma_spi_tx_config: + + return result; +} + + +/** + * SPI PDMA transfer + */ +static rt_size_t nu_spi_pdma_transmit(struct nu_spi *spi_bus, const uint8_t *send_addr, uint8_t *recv_addr, int length, uint8_t bytes_per_word) +{ + rt_err_t result = RT_EOK; + + result = nu_pdma_spi_rx_config(spi_bus, recv_addr, length, bytes_per_word); + RT_ASSERT(result == RT_EOK); + + result = nu_pdma_spi_tx_config(spi_bus, send_addr, length, bytes_per_word); + RT_ASSERT(result == RT_EOK); + + /* Wait RX-PDMA transfer done */ + result = rt_sem_take(spi_bus->m_psSemBus, RT_WAITING_FOREVER); + RT_ASSERT(result == RT_EOK); + + return length; +} + +rt_err_t nu_hw_spi_pdma_allocate(struct nu_spi *spi_bus) +{ + /* Allocate SPI_TX nu_dma channel */ + if ((spi_bus->pdma_chanid_tx = nu_pdma_channel_allocate(spi_bus->pdma_perp_tx)) < 0) + { + goto exit_nu_hw_spi_pdma_allocate; + } + /* Allocate SPI_RX nu_dma channel */ + else if ((spi_bus->pdma_chanid_rx = nu_pdma_channel_allocate(spi_bus->pdma_perp_rx)) < 0) + { + nu_pdma_channel_free(spi_bus->pdma_chanid_tx); + goto exit_nu_hw_spi_pdma_allocate; + } + + spi_bus->m_psSemBus = rt_sem_create("spibus_sem", 0, RT_IPC_FLAG_FIFO); + RT_ASSERT(spi_bus->m_psSemBus != RT_NULL); + + return RT_EOK; + +exit_nu_hw_spi_pdma_allocate: + + return -(RT_ERROR); +} +#endif /* #if defined(BSP_USING_SPI_PDMA) */ + +void nu_spi_drain_rxfifo(SPI_T *spi_base) +{ + while (SPI_IS_BUSY(spi_base)); + + // Drain SPI RX FIFO, make sure RX FIFO is empty + while (!SPI_GET_RX_FIFO_EMPTY_FLAG(spi_base)) + { + SPI_ClearRxFIFO(spi_base); + } +} + +static int nu_spi_read(SPI_T *spi_base, uint8_t *recv_addr, uint8_t bytes_per_word) +{ + int size = 0; + + // Read RX data + if (!SPI_GET_RX_FIFO_EMPTY_FLAG(spi_base)) + { + uint32_t val; + // Read data from SPI RX FIFO + switch (bytes_per_word) + { + case 4: + val = SPI_READ_RX(spi_base); + nu_set32_le(recv_addr, val); + break; + case 3: + val = SPI_READ_RX(spi_base); + nu_set24_le(recv_addr, val); + break; + case 2: + val = SPI_READ_RX(spi_base); + nu_set16_le(recv_addr, val); + break; + case 1: + *recv_addr = SPI_READ_RX(spi_base); + break; + default: + LOG_E("Data length is not supported.\n"); + break; + } + size = bytes_per_word; + } + return size; +} + +static int nu_spi_write(SPI_T *spi_base, const uint8_t *send_addr, uint8_t bytes_per_word) +{ + // Wait SPI TX send data + while (SPI_GET_TX_FIFO_FULL_FLAG(spi_base)); + + // Input data to SPI TX + switch (bytes_per_word) + { + case 4: + SPI_WRITE_TX(spi_base, nu_get32_le(send_addr)); + break; + case 3: + SPI_WRITE_TX(spi_base, nu_get24_le(send_addr)); + break; + case 2: + SPI_WRITE_TX(spi_base, nu_get16_le(send_addr)); + break; + case 1: + SPI_WRITE_TX(spi_base, *((uint8_t *)send_addr)); + break; + default: + LOG_E("Data length is not supported.\n"); + break; + } + + return bytes_per_word; +} + +/** + * @brief SPI bus polling + * @param dev : The pointer of the specified SPI module. + * @param send_addr : Source address + * @param recv_addr : Destination address + * @param length : Data length + */ +static void nu_spi_transmission_with_poll(struct nu_spi *spi_bus, + uint8_t *send_addr, uint8_t *recv_addr, int length, uint8_t bytes_per_word) +{ + SPI_T *spi_base = spi_bus->spi_base; + + // Write-only + if ((send_addr != RT_NULL) && (recv_addr == RT_NULL)) + { + while (length > 0) + { + send_addr += nu_spi_write(spi_base, send_addr, bytes_per_word); + length -= bytes_per_word; + } + } // if (send_addr != RT_NULL && recv_addr == RT_NULL) + // Read-only + else if ((send_addr == RT_NULL) && (recv_addr != RT_NULL)) + { + spi_bus->dummy = 0; + while (length > 0) + { + /* Input data to SPI TX FIFO */ + length -= nu_spi_write(spi_base, (const uint8_t *)&spi_bus->dummy, bytes_per_word); + + /* Read data from RX FIFO */ + recv_addr += nu_spi_read(spi_base, recv_addr, bytes_per_word); + } + } // else if (send_addr == RT_NULL && recv_addr != RT_NULL) + // Read&Write + else + { + while (length > 0) + { + /* Input data to SPI TX FIFO */ + send_addr += nu_spi_write(spi_base, send_addr, bytes_per_word); + length -= bytes_per_word; + + /* Read data from RX FIFO */ + recv_addr += nu_spi_read(spi_base, recv_addr, bytes_per_word); + } + } // else + + /* Wait RX or drain RX-FIFO */ + if (recv_addr) + { + // Wait SPI transmission done + while (SPI_IS_BUSY(spi_base)) + { + while (!SPI_GET_RX_FIFO_EMPTY_FLAG(spi_base)) + { + recv_addr += nu_spi_read(spi_base, recv_addr, bytes_per_word); + } + } + + while (!SPI_GET_RX_FIFO_EMPTY_FLAG(spi_base)) + { + recv_addr += nu_spi_read(spi_base, recv_addr, bytes_per_word); + } + } + else + { + /* Clear SPI RX FIFO */ + nu_spi_drain_rxfifo(spi_base); + } +} + +void nu_spi_transfer(struct nu_spi *spi_bus, uint8_t *tx, uint8_t *rx, int length, uint8_t bytes_per_word) +{ + RT_ASSERT(spi_bus != RT_NULL); + +#if defined(BSP_USING_SPI_PDMA) + /* DMA transfer constrains */ + if ((spi_bus->pdma_chanid_rx >= 0) && + !((uint32_t)tx % bytes_per_word) && + !((uint32_t)rx % bytes_per_word) && + (bytes_per_word != 3) && + (length >= NU_SPI_USE_PDMA_MIN_THRESHOLD)) + nu_spi_pdma_transmit(spi_bus, tx, rx, length, bytes_per_word); + else + nu_spi_transmission_with_poll(spi_bus, tx, rx, length, bytes_per_word); +#else + nu_spi_transmission_with_poll(spi_bus, tx, rx, length, bytes_per_word); +#endif +} + +static rt_uint32_t nu_spi_bus_xfer(struct rt_spi_device *device, struct rt_spi_message *message) +{ + struct nu_spi *spi_bus; + struct rt_spi_configuration *configuration; + uint8_t bytes_per_word; + void *pvUserData; + + RT_ASSERT(device != RT_NULL); + RT_ASSERT(device->bus != RT_NULL); + RT_ASSERT(message != RT_NULL); + + spi_bus = (struct nu_spi *) device->bus; + configuration = (struct rt_spi_configuration *)&spi_bus->configuration; + bytes_per_word = configuration->data_width / 8; + pvUserData = device->parent.user_data; + + if ((message->length % bytes_per_word) != 0) + { + /* Say bye. */ + LOG_E("%s: error payload length(%d%%%d != 0).\n", spi_bus->name, message->length, bytes_per_word); + return 0; + } + + if (message->length > 0) + { + if (message->cs_take && !(configuration->mode & RT_SPI_NO_CS)) + { + if (pvUserData != RT_NULL) + { + if (configuration->mode & RT_SPI_CS_HIGH) + { + // set to HIGH */ + rt_pin_write(*((rt_base_t *)pvUserData), PIN_HIGH); + } + else + { + // set to LOW */ + rt_pin_write(*((rt_base_t *)pvUserData), PIN_LOW); + } + } + else + { + if (configuration->mode & RT_SPI_CS_HIGH) + { + SPI_SET_SS_HIGH(spi_bus->spi_base); + } + else + { + SPI_SET_SS_LOW(spi_bus->spi_base); + } + } + } + + nu_spi_transfer(spi_bus, (uint8_t *)message->send_buf, (uint8_t *)message->recv_buf, message->length, bytes_per_word); + + if (message->cs_release && !(configuration->mode & RT_SPI_NO_CS)) + { + if (pvUserData != RT_NULL) + { + if (configuration->mode & RT_SPI_CS_HIGH) + { + // set to LOW */ + rt_pin_write(*((rt_base_t *)pvUserData), PIN_LOW); + } + else + { + // set to HIGH */ + rt_pin_write(*((rt_base_t *)pvUserData), PIN_HIGH); + } + } + else + { + if (configuration->mode & RT_SPI_CS_HIGH) + { + SPI_SET_SS_LOW(spi_bus->spi_base); + } + else + { + SPI_SET_SS_HIGH(spi_bus->spi_base); + } + } + } + + } + + return message->length; +} + +static int nu_spi_register_bus(struct nu_spi *spi_bus, const char *name) +{ + return rt_spi_bus_register(&spi_bus->dev, name, &nu_spi_poll_ops); +} + +/** + * Hardware SPI Initial + */ +static int rt_hw_spi_init(void) +{ + int i; + + for (i = (SPI_START + 1); i < SPI_CNT; i++) + { + nu_sys_ip_reset(nu_spi_arr[i].rstidx); + + nu_spi_register_bus(&nu_spi_arr[i], nu_spi_arr[i].name); +#if defined(BSP_USING_SPI_PDMA) + nu_spi_arr[i].pdma_chanid_tx = -1; + nu_spi_arr[i].pdma_chanid_rx = -1; + if ((nu_spi_arr[i].pdma_perp_tx != NU_PDMA_UNUSED) && (nu_spi_arr[i].pdma_perp_rx != NU_PDMA_UNUSED)) + { + if (nu_hw_spi_pdma_allocate(&nu_spi_arr[i]) != RT_EOK) + { + LOG_W("Failed to allocate DMA channels for %s. We will use poll-mode for this bus.\n", nu_spi_arr[i].name); + } + } +#endif + } + + return 0; +} + +INIT_DEVICE_EXPORT(rt_hw_spi_init); + +#endif //#if defined(BSP_USING_SPI) diff --git a/bsp/nuvoton/libraries/ma35/rtt_port/drv_spi.h b/bsp/nuvoton/libraries/ma35/rtt_port/drv_spi.h new file mode 100644 index 0000000000..6195009d00 --- /dev/null +++ b/bsp/nuvoton/libraries/ma35/rtt_port/drv_spi.h @@ -0,0 +1,53 @@ +/**************************************************************************//** +* +* @copyright (C) 2020 Nuvoton Technology Corp. All rights reserved. +* +* SPDX-License-Identifier: Apache-2.0 +* +* Change Logs: +* Date Author Notes +* 2020-2-7 Wayne First version +* +******************************************************************************/ + +#ifndef __DRV_SPI_H__ +#define __DRV_SPI_H__ + +#include + +#include +#include "NuMicro.h" +#include +#include + +#if defined(BSP_USING_SPI_PDMA) + #include +#endif + +struct nu_spi +{ + struct rt_spi_bus dev; + char *name; + SPI_T *spi_base; + uint32_t rstidx; + uint32_t dummy; +#if defined(BSP_USING_SPI_PDMA) + int16_t pdma_perp_tx; + int8_t pdma_chanid_tx; + int16_t pdma_perp_rx; + int8_t pdma_chanid_rx; + rt_sem_t m_psSemBus; +#endif + struct rt_qspi_configuration configuration; +}; + +typedef struct nu_spi *nu_spi_t; + +void nu_spi_drain_rxfifo(SPI_T *spi_base); +void nu_spi_transfer(struct nu_spi *spi_bus, uint8_t *tx, uint8_t *rx, int length, uint8_t bytes_per_word); + +#if defined(BSP_USING_SPI_PDMA) + rt_err_t nu_hw_spi_pdma_allocate(struct nu_spi *spi_bus); +#endif + +#endif // __DRV_SPI_H___ diff --git a/bsp/nuvoton/libraries/ma35/rtt_port/drv_spii2s.c b/bsp/nuvoton/libraries/ma35/rtt_port/drv_spii2s.c new file mode 100644 index 0000000000..16e11e5b05 --- /dev/null +++ b/bsp/nuvoton/libraries/ma35/rtt_port/drv_spii2s.c @@ -0,0 +1,652 @@ +/**************************************************************************//** +* +* @copyright (C) 2020 Nuvoton Technology Corp. All rights reserved. +* +* SPDX-License-Identifier: Apache-2.0 +* +* Change Logs: +* Date Author Notes +* 2020-5-29 Wayne First version +* +******************************************************************************/ + +#include + +#if defined(BSP_USING_SPII2S) + +#include +#include +#include + +/* Private define ---------------------------------------------------------------*/ +#define DBG_ENABLE +#define DBG_LEVEL DBG_LOG +#define DBG_SECTION_NAME "spii2s" +#define DBG_COLOR +#include + +enum +{ + SPII2S_START = -1, +#if defined(BSP_USING_SPII2S0) + SPII2S0_IDX, +#endif +#if defined(BSP_USING_SPII2S1) + SPII2S1_IDX, +#endif +#if defined(BSP_USING_SPII2S2) + SPII2S2_IDX, +#endif +#if defined(BSP_USING_SPII2S3) + SPII2S3_IDX, +#endif + SPII2S_CNT +}; + +/* Private functions ------------------------------------------------------------*/ +static rt_err_t nu_spii2s_getcaps(struct rt_audio_device *audio, struct rt_audio_caps *caps); +static rt_err_t nu_spii2s_configure(struct rt_audio_device *audio, struct rt_audio_caps *caps); +static rt_err_t nu_spii2s_init(struct rt_audio_device *audio); +static rt_err_t nu_spii2s_start(struct rt_audio_device *audio, int stream); +static rt_err_t nu_spii2s_stop(struct rt_audio_device *audio, int stream); +static void nu_spii2s_buffer_info(struct rt_audio_device *audio, struct rt_audio_buf_info *info); +/* Public functions -------------------------------------------------------------*/ +rt_err_t nu_spii2s_acodec_register(struct rt_audio_device *audio, nu_acodec_ops_t); + +/* Private variables ------------------------------------------------------------*/ +static struct nu_i2s g_nu_spii2s_arr [] = +{ +#if defined(BSP_USING_SPII2S0) + { + .name = "spii2s0", + .i2s_base = (I2S_T *)SPI0, //Avoid warning + .i2s_rst = SPI0_RST, + .i2s_dais = { + [NU_I2S_DAI_PLAYBACK] = { + .pdma_perp = PDMA_SPI0_TX, + }, + [NU_I2S_DAI_CAPTURE] = { + .pdma_perp = PDMA_SPI0_RX, + } + } + }, +#endif +#if defined(BSP_USING_SPII2S1) + { + .name = "spii2s1", + .i2s_base = (I2S_T *)SPI1, //Avoid warning + .i2s_rst = SPI1_RST, + .i2s_dais = { + [NU_I2S_DAI_PLAYBACK] = { + .pdma_perp = PDMA_SPI1_TX, + }, + [NU_I2S_DAI_CAPTURE] = { + .pdma_perp = PDMA_SPI1_RX, + } + } + }, +#endif +#if defined(BSP_USING_SPII2S2) + { + .name = "spii2s2", + .i2s_base = (I2S_T *)SPI2, //Avoid warning + .i2s_rst = SPI2_RST, + .i2s_dais = { + [NU_I2S_DAI_PLAYBACK] = { + .pdma_perp = PDMA_SPI2_TX, + }, + [NU_I2S_DAI_CAPTURE] = { + .pdma_perp = PDMA_SPI2_RX, + } + } + }, +#endif +#if defined(BSP_USING_SPII2S3) + { + .name = "spii2s3", + .i2s_base = (I2S_T *)SPI3, //Avoid warning + .i2s_rst = SPI3_RST, + .i2s_dais = { + [NU_I2S_DAI_PLAYBACK] = { + .pdma_perp = PDMA_SPI3_TX, + }, + [NU_I2S_DAI_CAPTURE] = { + .pdma_perp = PDMA_SPI3_RX, + } + } + }, +#endif +}; + +static void nu_pdma_spii2s_rx_cb(void *pvUserData, uint32_t u32EventFilter) +{ + nu_i2s_t psNuSPII2s = (nu_i2s_t)pvUserData; + nu_i2s_dai_t psNuSPII2sDai; + + RT_ASSERT(psNuSPII2s != RT_NULL); + psNuSPII2sDai = &psNuSPII2s->i2s_dais[NU_I2S_DAI_CAPTURE]; + + if (u32EventFilter & NU_PDMA_EVENT_TRANSFER_DONE) + { + // Report a buffer ready. + rt_uint8_t *pbuf_old = &psNuSPII2sDai->fifo[psNuSPII2sDai->fifo_block_idx * NU_I2S_DMA_BUF_BLOCK_SIZE] ; + psNuSPII2sDai->fifo_block_idx = (psNuSPII2sDai->fifo_block_idx + 1) % NU_I2S_DMA_BUF_BLOCK_NUMBER; + + /* Report upper layer. */ + rt_audio_rx_done(&psNuSPII2s->audio, pbuf_old, NU_I2S_DMA_BUF_BLOCK_SIZE); + } +} + +static void nu_pdma_spii2s_tx_cb(void *pvUserData, uint32_t u32EventFilter) +{ + nu_i2s_t psNuSPII2s = (nu_i2s_t)pvUserData; + nu_i2s_dai_t psNuSPII2sDai; + + RT_ASSERT(psNuSPII2s != RT_NULL); + psNuSPII2sDai = &psNuSPII2s->i2s_dais[NU_I2S_DAI_PLAYBACK]; + + if (u32EventFilter & NU_PDMA_EVENT_TRANSFER_DONE) + { + rt_audio_tx_complete(&psNuSPII2s->audio); + psNuSPII2sDai->fifo_block_idx = (psNuSPII2sDai->fifo_block_idx + 1) % NU_I2S_DMA_BUF_BLOCK_NUMBER; + } +} + +static rt_err_t nu_spii2s_pdma_sc_config(nu_i2s_t psNuSPII2s, E_NU_I2S_DAI dai) +{ + rt_err_t result = RT_EOK; + SPI_T *spii2s_base; + nu_i2s_dai_t psNuSPII2sDai; + int i; + uint32_t u32Src, u32Dst; + nu_pdma_cb_handler_t pfm_pdma_cb; + struct nu_pdma_chn_cb sChnCB; + + RT_ASSERT(psNuSPII2s != RT_NULL); + + /* Get base address of spii2s register */ + spii2s_base = (SPI_T *)psNuSPII2s->i2s_base; + psNuSPII2sDai = &psNuSPII2s->i2s_dais[dai]; + + switch ((int)dai) + { + case NU_I2S_DAI_PLAYBACK: + pfm_pdma_cb = nu_pdma_spii2s_tx_cb; + u32Src = (uint32_t)&psNuSPII2sDai->fifo[0]; + u32Dst = (uint32_t)&spii2s_base->TX; + break; + + case NU_I2S_DAI_CAPTURE: + pfm_pdma_cb = nu_pdma_spii2s_rx_cb; + u32Src = (uint32_t)&spii2s_base->RX; + u32Dst = (uint32_t)&psNuSPII2sDai->fifo[0]; + break; + + default: + return -RT_EINVAL; + } + /* Register ISR callback function */ + sChnCB.m_eCBType = eCBType_Event; + sChnCB.m_pfnCBHandler = pfm_pdma_cb; + sChnCB.m_pvUserData = (void *)psNuSPII2s; + + nu_pdma_filtering_set(psNuSPII2sDai->pdma_chanid, NU_PDMA_EVENT_TRANSFER_DONE); + result = nu_pdma_callback_register(psNuSPII2sDai->pdma_chanid, &sChnCB); + RT_ASSERT(result == RT_EOK); + + for (i = 0; i < NU_I2S_DMA_BUF_BLOCK_NUMBER; i++) + { + /* Setup dma descriptor entry */ + result = nu_pdma_desc_setup(psNuSPII2sDai->pdma_chanid, // Channel ID + psNuSPII2sDai->pdma_descs[i], // this descriptor + 32, // 32-bits + (dai == NU_I2S_DAI_PLAYBACK) ? u32Src + (i * NU_I2S_DMA_BUF_BLOCK_SIZE) : u32Src, //Memory or RXFIFO + (dai == NU_I2S_DAI_PLAYBACK) ? u32Dst : u32Dst + (i * NU_I2S_DMA_BUF_BLOCK_SIZE), //TXFIFO or Memory + (int32_t)NU_I2S_DMA_BUF_BLOCK_SIZE / 4, // Transfer count + psNuSPII2sDai->pdma_descs[(i + 1) % NU_I2S_DMA_BUF_BLOCK_NUMBER], // Next descriptor + 0); // Interrupt assert when every SG-table done. + RT_ASSERT(result == RT_EOK); + } + + /* Assign head descriptor */ + result = nu_pdma_sg_transfer(psNuSPII2sDai->pdma_chanid, psNuSPII2sDai->pdma_descs[0], 0); + RT_ASSERT(result == RT_EOK); + + return result; +} + +static rt_bool_t nu_spii2s_capacity_check(struct rt_audio_configure *pconfig) +{ + switch (pconfig->samplebits) + { + case 8: + case 16: + /* case 24: PDMA constrain */ + case 32: + break; + default: + goto exit_nu_spii2s_capacity_check; + } + + switch (pconfig->channels) + { + case 1: + case 2: + break; + default: + goto exit_nu_spii2s_capacity_check; + } + + return RT_TRUE; + +exit_nu_spii2s_capacity_check: + + return RT_FALSE; +} + +static rt_err_t nu_spii2s_dai_setup(nu_i2s_t psNuSPII2s, struct rt_audio_configure *pconfig) +{ + rt_err_t result = RT_EOK; + nu_acodec_ops_t pNuACodecOps; + SPI_T *spii2s_base = (SPI_T *)psNuSPII2s->i2s_base; + + RT_ASSERT(psNuSPII2s->AcodecOps != RT_NULL); + pNuACodecOps = psNuSPII2s->AcodecOps; + + /* Open SPII2S */ + if (nu_spii2s_capacity_check(pconfig) == RT_TRUE) + { + /* Reset audio codec */ + if (pNuACodecOps->nu_acodec_reset) + result = pNuACodecOps->nu_acodec_reset(); + + if (result != RT_EOK) + goto exit_nu_spii2s_dai_setup; + + /* Setup audio codec */ + if (pNuACodecOps->nu_acodec_init) + result = pNuACodecOps->nu_acodec_init(); + + if (!pNuACodecOps->nu_acodec_init || result != RT_EOK) + goto exit_nu_spii2s_dai_setup; + + /* Setup acodec samplerate/samplebit/channel */ + if (pNuACodecOps->nu_acodec_dsp_control) + result = pNuACodecOps->nu_acodec_dsp_control(pconfig); + + if (!pNuACodecOps->nu_acodec_dsp_control || result != RT_EOK) + goto exit_nu_spii2s_dai_setup; + + SPII2S_Open(spii2s_base, + (psNuSPII2s->AcodecOps->role == NU_ACODEC_ROLE_MASTER) ? SPII2S_MODE_SLAVE : SPII2S_MODE_MASTER, + pconfig->samplerate, + (((pconfig->samplebits / 8) - 1) << SPI_I2SCTL_WDWIDTH_Pos), + (pconfig->channels == 1) ? SPII2S_MONO : SPII2S_STEREO, + SPII2S_FORMAT_I2S); + LOG_I("Open SPII2S."); + + /* Set MCLK and enable MCLK */ + /* The target MCLK is related to audio codec setting. */ + SPII2S_EnableMCLK(spii2s_base, 12000000); + + /* Set un-mute */ + if (pNuACodecOps->nu_acodec_mixer_control) + pNuACodecOps->nu_acodec_mixer_control(AUDIO_MIXER_MUTE, RT_FALSE); + } + else + result = -RT_EINVAL; + +exit_nu_spii2s_dai_setup: + + return result; +} + +static rt_err_t nu_spii2s_getcaps(struct rt_audio_device *audio, struct rt_audio_caps *caps) +{ + rt_err_t result = RT_EOK; + nu_i2s_t psNuSPII2s = (nu_i2s_t)audio; + nu_acodec_ops_t pNuACodecOps; + + RT_ASSERT(audio != RT_NULL); + RT_ASSERT(caps != RT_NULL); + RT_ASSERT(psNuSPII2s->AcodecOps != RT_NULL); + + pNuACodecOps = psNuSPII2s->AcodecOps; + + switch (caps->main_type) + { + case AUDIO_TYPE_QUERY: + switch (caps->sub_type) + { + case AUDIO_TYPE_QUERY: + caps->udata.mask = AUDIO_TYPE_INPUT | AUDIO_TYPE_OUTPUT | AUDIO_TYPE_MIXER; + break; + default: + result = -RT_ERROR; + break; + } // switch (caps->sub_type) + break; + + case AUDIO_TYPE_MIXER: + + if (pNuACodecOps->nu_acodec_mixer_query) + { + switch (caps->sub_type) + { + case AUDIO_MIXER_QUERY: + return pNuACodecOps->nu_acodec_mixer_query(AUDIO_MIXER_QUERY, &caps->udata.mask); + + default: + return pNuACodecOps->nu_acodec_mixer_query(caps->sub_type, (rt_uint32_t *)&caps->udata.value); + } // switch (caps->sub_type) + + } // if (pNuACodecOps->nu_acodec_mixer_query) + + result = -RT_ERROR; + break; + + case AUDIO_TYPE_INPUT: + case AUDIO_TYPE_OUTPUT: + + switch (caps->sub_type) + { + case AUDIO_DSP_PARAM: + caps->udata.config.channels = psNuSPII2s->config.channels; + caps->udata.config.samplebits = psNuSPII2s->config.samplebits; + caps->udata.config.samplerate = psNuSPII2s->config.samplerate; + break; + case AUDIO_DSP_SAMPLERATE: + caps->udata.config.samplerate = psNuSPII2s->config.samplerate; + break; + case AUDIO_DSP_CHANNELS: + caps->udata.config.channels = psNuSPII2s->config.channels; + break; + case AUDIO_DSP_SAMPLEBITS: + caps->udata.config.samplebits = psNuSPII2s->config.samplebits; + break; + default: + result = -RT_ERROR; + break; + } // switch (caps->sub_type) + break; + + default: + result = -RT_ERROR; + break; + + } // switch (caps->main_type) + + return result; +} + +static rt_err_t nu_spii2s_configure(struct rt_audio_device *audio, struct rt_audio_caps *caps) +{ + rt_err_t result = RT_EOK; + nu_i2s_t psNuSPII2s = (nu_i2s_t)audio; + nu_acodec_ops_t pNuACodecOps; + int stream = -1; + + RT_ASSERT(audio != RT_NULL); + RT_ASSERT(caps != RT_NULL); + RT_ASSERT(psNuSPII2s->AcodecOps != RT_NULL); + + pNuACodecOps = psNuSPII2s->AcodecOps; + + switch (caps->main_type) + { + case AUDIO_TYPE_MIXER: + if (psNuSPII2s->AcodecOps->nu_acodec_mixer_control) + psNuSPII2s->AcodecOps->nu_acodec_mixer_control(caps->sub_type, caps->udata.value); + break; + + case AUDIO_TYPE_INPUT: + stream = AUDIO_STREAM_RECORD; + case AUDIO_TYPE_OUTPUT: + { + rt_bool_t bNeedReset = RT_FALSE; + + if (stream < 0) + stream = AUDIO_STREAM_REPLAY; + + switch (caps->sub_type) + { + case AUDIO_DSP_PARAM: + if (rt_memcmp(&psNuSPII2s->config, &caps->udata.config, sizeof(struct rt_audio_configure)) != 0) + { + rt_memcpy(&psNuSPII2s->config, &caps->udata.config, sizeof(struct rt_audio_configure)); + bNeedReset = RT_TRUE; + } + break; + case AUDIO_DSP_SAMPLEBITS: + if (psNuSPII2s->config.samplerate != caps->udata.config.samplebits) + { + psNuSPII2s->config.samplerate = caps->udata.config.samplebits; + bNeedReset = RT_TRUE; + } + break; + case AUDIO_DSP_CHANNELS: + if (psNuSPII2s->config.channels != caps->udata.config.channels) + { + pNuACodecOps->config.channels = caps->udata.config.channels; + bNeedReset = RT_TRUE; + } + break; + case AUDIO_DSP_SAMPLERATE: + if (psNuSPII2s->config.samplerate != caps->udata.config.samplerate) + { + psNuSPII2s->config.samplerate = caps->udata.config.samplerate; + bNeedReset = RT_TRUE; + } + break; + default: + result = -RT_ERROR; + break; + } // switch (caps->sub_type) + + if (bNeedReset) + { + return nu_spii2s_start(audio, stream); + } + } + break; + + default: + result = -RT_ERROR; + break; + } // switch (caps->main_type) + + return result; +} + +static rt_err_t nu_spii2s_init(struct rt_audio_device *audio) +{ + rt_err_t result = RT_EOK; + nu_i2s_t psNuSPII2s = (nu_i2s_t)audio; + + RT_ASSERT(audio != RT_NULL); + + /* Reset this module */ + SYS_ResetModule(psNuSPII2s->i2s_rst); + + return -(result); +} + +static rt_err_t nu_spii2s_start(struct rt_audio_device *audio, int stream) +{ + nu_i2s_t psNuSPII2s = (nu_i2s_t)audio; + SPI_T *spii2s_base; + + RT_ASSERT(audio != RT_NULL); + + spii2s_base = (SPI_T *)psNuSPII2s->i2s_base; + + /* Restart all: SPII2S and codec. */ + nu_spii2s_stop(audio, stream); + if (nu_spii2s_dai_setup(psNuSPII2s, &psNuSPII2s->config) != RT_EOK) + return -RT_ERROR; + + switch (stream) + { + case AUDIO_STREAM_REPLAY: + { + nu_spii2s_pdma_sc_config(psNuSPII2s, NU_I2S_DAI_PLAYBACK); + + /* Start TX DMA */ + SPII2S_ENABLE_TXDMA(spii2s_base); + + /* Enable I2S Tx function */ + SPII2S_ENABLE_TX(spii2s_base); + + LOG_I("Start replay."); + } + break; + + case AUDIO_STREAM_RECORD: + { + nu_spii2s_pdma_sc_config(psNuSPII2s, NU_I2S_DAI_CAPTURE); + + /* Start RX DMA */ + SPII2S_ENABLE_RXDMA(spii2s_base); + + /* Enable I2S Rx function */ + SPII2S_ENABLE_RX(spii2s_base); + + LOG_I("Start record."); + } + break; + default: + return -RT_ERROR; + } + + return RT_EOK; +} + +static rt_err_t nu_spii2s_stop(struct rt_audio_device *audio, int stream) +{ + nu_i2s_t psNuSPII2s = (nu_i2s_t)audio; + nu_i2s_dai_t psNuSPII2sDai = RT_NULL; + SPI_T *spii2s_base; + + RT_ASSERT(audio != RT_NULL); + + spii2s_base = (SPI_T *)psNuSPII2s->i2s_base; + + switch (stream) + { + case AUDIO_STREAM_REPLAY: + psNuSPII2sDai = &psNuSPII2s->i2s_dais[NU_I2S_DAI_PLAYBACK]; + + // Disable TX + SPII2S_DISABLE_TXDMA(spii2s_base); + SPII2S_DISABLE_TX(spii2s_base); + + LOG_I("Stop replay."); + break; + + case AUDIO_STREAM_RECORD: + psNuSPII2sDai = &psNuSPII2s->i2s_dais[NU_I2S_DAI_CAPTURE]; + + // Disable RX + SPII2S_DISABLE_RXDMA(spii2s_base); + SPII2S_DISABLE_RX(spii2s_base); + + LOG_I("Stop record."); + break; + + default: + return -RT_EINVAL; + } + + /* Stop DMA transfer. */ + nu_pdma_channel_terminate(psNuSPII2sDai->pdma_chanid); + + /* Close SPII2S */ + if (!(spii2s_base->I2SCTL & (SPI_I2SCTL_TXEN_Msk | SPI_I2SCTL_RXEN_Msk))) + { + SPII2S_DisableMCLK(spii2s_base); + SPII2S_Close(spii2s_base); + LOG_I("Close SPII2S."); + } + + /* Silence */ + rt_memset((void *)psNuSPII2sDai->fifo, 0, NU_I2S_DMA_FIFO_SIZE); + psNuSPII2sDai->fifo_block_idx = 0; + + return RT_EOK; +} + +static void nu_spii2s_buffer_info(struct rt_audio_device *audio, struct rt_audio_buf_info *info) +{ + nu_i2s_t psNuSPII2s = (nu_i2s_t)audio; + + RT_ASSERT(audio != RT_NULL); + RT_ASSERT(info != RT_NULL); + + info->buffer = (rt_uint8_t *)psNuSPII2s->i2s_dais[NU_I2S_DAI_PLAYBACK].fifo ; + info->total_size = NU_I2S_DMA_FIFO_SIZE; + info->block_size = NU_I2S_DMA_BUF_BLOCK_SIZE; + info->block_count = NU_I2S_DMA_BUF_BLOCK_NUMBER; + + return; +} + +static struct rt_audio_ops nu_spii2s_audio_ops = +{ + .getcaps = nu_spii2s_getcaps, + .configure = nu_spii2s_configure, + + .init = nu_spii2s_init, + .start = nu_spii2s_start, + .stop = nu_spii2s_stop, + .transmit = RT_NULL, + .buffer_info = nu_spii2s_buffer_info +}; + +static rt_err_t nu_hw_spii2s_pdma_allocate(nu_i2s_dai_t psNuSPII2sDai) +{ + /* Allocate I2S nu_dma channel */ + if ((psNuSPII2sDai->pdma_chanid = nu_pdma_channel_allocate(psNuSPII2sDai->pdma_perp)) < 0) + { + goto nu_hw_spii2s_pdma_allocate; + } + + return RT_EOK; + +nu_hw_spii2s_pdma_allocate: + + return -(RT_ERROR); +} + +int rt_hw_spii2s_init(void) +{ + int j = 0; + nu_i2s_dai_t psNuSPII2sDai; + + for (j = (SPII2S_START + 1); j < SPII2S_CNT; j++) + { + int i = 0; + for (i = 0; i < NU_I2S_DAI_CNT; i++) + { + uint8_t *pu8ptr = rt_malloc(NU_I2S_DMA_FIFO_SIZE); + psNuSPII2sDai = &g_nu_spii2s_arr[j].i2s_dais[i]; + psNuSPII2sDai->fifo = pu8ptr; + rt_memset(pu8ptr, 0, NU_I2S_DMA_FIFO_SIZE); + RT_ASSERT(psNuSPII2sDai->fifo != RT_NULL); + + psNuSPII2sDai->pdma_chanid = -1; + psNuSPII2sDai->fifo_block_idx = 0; + RT_ASSERT(nu_hw_spii2s_pdma_allocate(psNuSPII2sDai) == RT_EOK); + RT_ASSERT(nu_pdma_sgtbls_allocate(&psNuSPII2sDai->pdma_descs[0], NU_I2S_DMA_BUF_BLOCK_NUMBER) == RT_EOK); + } + + /* Register ops of audio device */ + g_nu_spii2s_arr[j].audio.ops = &nu_spii2s_audio_ops; + + /* Register device, RW: it is with replay and record functions. */ + rt_audio_register(&g_nu_spii2s_arr[j].audio, g_nu_spii2s_arr[j].name, RT_DEVICE_FLAG_RDWR, &g_nu_spii2s_arr[j]); + } + + return RT_EOK; +} +INIT_DEVICE_EXPORT(rt_hw_spii2s_init); +#endif //#if defined(BSP_USING_SPII2S) diff --git a/bsp/nuvoton/libraries/ma35/rtt_port/drv_sys.c b/bsp/nuvoton/libraries/ma35/rtt_port/drv_sys.c new file mode 100644 index 0000000000..cbf15c750e --- /dev/null +++ b/bsp/nuvoton/libraries/ma35/rtt_port/drv_sys.c @@ -0,0 +1,269 @@ +/**************************************************************************//** +* +* @copyright (C) 2020 Nuvoton Technology Corp. All rights reserved. +* +* SPDX-License-Identifier: Apache-2.0 +* +* Change Logs: +* Date Author Notes +* 2020-11-11 Wayne First version +* +******************************************************************************/ + +#include +#include +#include "drv_sys.h" +#include + +#define DEF_RAISING_CPU_FREQUENCY +//Dont enable #define DEF_RAISING_CPU_VOLTAGE + +void machine_shutdown(void) +{ + rt_kprintf("machine_shutdown...\n"); + rt_hw_interrupt_disable(); + + /* Unlock */ + SYS_UnlockReg(); + + while (1); +} + +void machine_reset(void) +{ + rt_kprintf("machine_reset...\n"); + rt_hw_interrupt_disable(); + + /* Unlock */ + SYS_UnlockReg(); + + SYS->IPRST0 = SYS_IPRST0_CHIPRST_Msk; + SYS->IPRST0 = 0; + while (1); +} + +int reboot(int argc, char **argv) +{ + machine_reset(); + return 0; +} +MSH_CMD_EXPORT(reboot, Reboot System); + + +void nu_sys_ip_reset(uint32_t u32ModuleIndex) +{ + SYS_ResetModule(u32ModuleIndex); +} + +E_SYS_USB0_ID nu_sys_usb0_role(void) +{ +#if 0 + /* Check Role on USB0 dual-role port. */ + /* + [17] USB0_IDS + USB0_ID Status + 0 = USB port 0 used as a USB device port. + 1 = USB port 0 used as a USB host port. + */ + return ((inpw(REG_SYS_MISCISR) & (1 << 17)) > 0) ? USB0_ID_HOST : USB0_ID_DEVICE; +#else + return USB0_ID_DEVICE; +#endif +} + +void nu_sys_check_register(S_NU_REG *psNuReg) +{ + if (psNuReg == RT_NULL) + return; + + while (psNuReg->vu32RegAddr != 0) + { + vu32 vc32RegValue = *((vu32 *)psNuReg->vu32RegAddr); + vu32 vc32BMValue = vc32RegValue & psNuReg->vu32BitMask; + rt_kprintf("[%3s] %32s(0x%08x) %24s(0x%08x): 0x%08x(AndBitMask:0x%08x)\n", + (psNuReg->vu32Value == vc32BMValue) ? "Ok" : "!OK", + psNuReg->szVName, + psNuReg->vu32Value, + psNuReg->szRegName, + psNuReg->vu32RegAddr, + vc32RegValue, + vc32BMValue); + psNuReg++; + } +} + +static int nu_tempsen_init() +{ + SYS->TSENSRFCR &= ~SYS_TSENSRFCR_PD_Msk; // Disable power down, don't wait, takes double conv time (350ms * 2) + return 0; +} + +static int nu_tempsen_get_value() +{ + char sztmp[32]; + double temp; + static rt_tick_t _old_tick = 0; + static int32_t count = 0; + + _old_tick = rt_tick_get(); + + // Wait valid bit set + while ((SYS->TSENSRFCR & SYS_TSENSRFCR_DATAVALID_Msk) == 0) + { + // 700 ms after clear pd bit. other conversion takes 350 ms + if (rt_tick_get() > (500 + _old_tick)) + { + return -1; + } + } + + if (++count == 8) + { + count = 0; + temp = (double)((SYS->TSENSRFCR & 0x0FFF0000) >> 16) * 274.3531 / 4096.0 - 93.3332; + snprintf(sztmp, sizeof(sztmp), "Temperature: %.1f\n", temp); + rt_kprintf("%s", sztmp); + } + + // Clear Valid bit + SYS->TSENSRFCR = SYS_TSENSRFCR_DATAVALID_Msk; + + return 0; +} + +void nu_tempsen_hook(void) +{ + nu_tempsen_get_value(); +} + +static int nu_tempsen_go(void) +{ + rt_err_t err = rt_thread_idle_sethook(nu_tempsen_hook); + + if (err != RT_EOK) + { + rt_kprintf("set %s idle hook failed!\n", __func__); + return -1; + } + + nu_tempsen_init(); + + return 0; +} +//INIT_APP_EXPORT(nu_tempsen_go); +MSH_CMD_EXPORT(nu_tempsen_go, go tempsen); + +void nu_clock_dump(void) +{ + rt_kprintf("HXT: %d Hz\n", CLK_GetHXTFreq()); + rt_kprintf("LXT: %d Hz\n", CLK_GetLXTFreq()); + rt_kprintf("CAPLL: %d Hz(OpMode=%d)\n", CLK_GetPLLClockFreq(CAPLL), CLK_GetPLLOpMode(CAPLL)); + rt_kprintf("DDRPLL: %d Hz(OpMode=%d)\n", CLK_GetPLLClockFreq(DDRPLL), CLK_GetPLLOpMode(DDRPLL)); + rt_kprintf("APLL: %d Hz(OpMode=%d)\n", CLK_GetPLLClockFreq(APLL), CLK_GetPLLOpMode(APLL)); + rt_kprintf("EPLL: %d Hz(OpMode=%d)\n", CLK_GetPLLClockFreq(EPLL), CLK_GetPLLOpMode(EPLL)); + rt_kprintf("VPLL: %d Hz(OpMode=%d)\n", CLK_GetPLLClockFreq(VPLL), CLK_GetPLLOpMode(VPLL)); + + rt_kprintf("M4-CPU: %d Hz\n", CLK_GetCPUFreq()); + + rt_kprintf("SYSCLK0: %d Hz\n", CLK_GetSYSCLK0Freq()); + rt_kprintf("SYSCLK1: %d Hz\n", CLK_GetSYSCLK1Freq()); + rt_kprintf("HCLK0: %d Hz\n", CLK_GetHCLK0Freq()); + rt_kprintf("HCLK1: %d Hz\n", CLK_GetHCLK1Freq()); + rt_kprintf("HCLK2: %d Hz\n", CLK_GetHCLK2Freq()); + rt_kprintf("HCLK3: %d Hz\n", CLK_GetHCLK3Freq()); + rt_kprintf("PCLK0: %d Hz\n", CLK_GetPCLK0Freq()); + rt_kprintf("PCLK1: %d Hz\n", CLK_GetPCLK1Freq()); + rt_kprintf("PCLK2: %d Hz\n", CLK_GetPCLK2Freq()); + rt_kprintf("PCLK3: %d Hz\n", CLK_GetPCLK3Freq()); + rt_kprintf("PCLK4: %d Hz\n", CLK_GetPCLK4Freq()); +} + +const char *szClockName [] = +{ + "HXT", + "LXT", + "N/A", + "LIRC", + "HIRC", + "N/A", + "CAPLL", + "N/A", + "DDRPLL", + "EPLL", + "APLL", + "VPLL" +}; +#define CLOCKNAME_SIZE (sizeof(szClockName)/sizeof(char*)) + +void nu_clock_isready(void) +{ + uint32_t u32IsReady, i; + for (i = 0; i < CLOCKNAME_SIZE; i++) + { + if (i == 5 || i == 7 || i == 2) continue; + u32IsReady = CLK_WaitClockReady(1 << i); + rt_kprintf("%s: %s\n", szClockName[i], (u32IsReady == 1) ? "[Stable]" : "[Unstable]"); + } +} + +extern uint32_t ma35d1_set_cpu_voltage(uint32_t sys_clk, uint32_t u32Vol); +void nu_clock_raise(void) +{ + uint32_t u32PllRefClk; + + /* Unlock protected registers */ + SYS_UnlockReg(); + + /* Enable HXT, LXT */ + CLK->PWRCTL |= (CLK_PWRCTL_HXTEN_Msk | CLK_PWRCTL_HIRCEN_Msk); + if (CLK->STATUS & CLK_STATUS_HXTSTB_Msk) // Check Ready + { + u32PllRefClk = __HXT; + } + else if (CLK->STATUS & CLK_STATUS_HIRCSTB_Msk) // Check Ready + { + u32PllRefClk = __HIRC; // HXT_CHECK_FAIL + } + else + { + return; + } + + CLK_SetPLLFreq(VPLL, PLL_OPMODE_INTEGER, u32PllRefClk, 102000000ul); + CLK_SetPLLFreq(APLL, PLL_OPMODE_INTEGER, u32PllRefClk, 160000000ul); + CLK_SetPLLFreq(EPLL, PLL_OPMODE_INTEGER, u32PllRefClk, 500000000ul); + + /* Waiting clock ready */ + CLK_WaitClockReady(CLK_STATUS_VPLLSTB_Msk | CLK_STATUS_APLLSTB_Msk | CLK_STATUS_EPLLSTB_Msk); + +#if defined(DEF_RAISING_CPU_FREQUENCY) + /* Switch clock source of CA35 to DDRPLL before raising CA-PLL */ + CLK->CLKSEL0 = (CLK->CLKSEL0 & (~CLK_CLKSEL0_CA35CKSEL_Msk)) | CLK_CLKSEL0_CA35CKSEL_DDRPLL; +#if defined(DEF_RAISING_CPU_VOLTAGE) + if (ma35d1_set_cpu_voltage(CLK_GetPLLClockFreq(SYSPLL), 0x68)) + { + CLK_SetPLLFreq(CAPLL, PLL_OPMODE_INTEGER, u32PllRefClk, 1000000000ul); + } + else +#endif + { + ma35d1_set_cpu_voltage(CLK_GetPLLClockFreq(SYSPLL), 0x5F); + CLK_SetPLLFreq(CAPLL, PLL_OPMODE_INTEGER, u32PllRefClk, 800000000ul); + } + + /* Waiting clock ready */ + CLK_WaitClockReady(CLK_STATUS_CAPLLSTB_Msk); + + /* Switch clock source of CA35 to CA-PLL after raising */ + CLK->CLKSEL0 = (CLK->CLKSEL0 & (~CLK_CLKSEL0_CA35CKSEL_Msk)) | CLK_CLKSEL0_CA35CKSEL_CAPLL; +#endif + +} + +#ifdef FINSH_USING_MSH + MSH_CMD_EXPORT(nu_clock_dump, Dump all clocks); + MSH_CMD_EXPORT(nu_clock_raise, Raise clock); + MSH_CMD_EXPORT(nu_clock_isready, Check PLL clocks); +#endif + + diff --git a/bsp/nuvoton/libraries/ma35/rtt_port/drv_sys.h b/bsp/nuvoton/libraries/ma35/rtt_port/drv_sys.h new file mode 100644 index 0000000000..63b47fded8 --- /dev/null +++ b/bsp/nuvoton/libraries/ma35/rtt_port/drv_sys.h @@ -0,0 +1,95 @@ +#ifndef __DRV_SYS_H__ +#define __DRV_SYS_H__ + +#include +#include "drv_common.h" +#include "NuMicro.h" + +typedef enum +{ + USB0_ID_DEVICE, + USB0_ID_HOST, + USB0_ID_CNT +} E_SYS_USB0_ID; + +struct nu_module +{ + char *name; + void *m_pvBase; + uint32_t u32RstId; + IRQn_Type eIRQn; +} ; +typedef struct nu_module *nu_module_t; + +typedef struct +{ + vu32 vu32RegAddr; + char *szRegName; + vu32 vu32BitMask; + char *szBMName; + vu32 vu32Value; + char *szVName; +} S_NU_REG; + +#define SYS_GPA_MFPL (SYS_BASE + 0x0080U) +#define SYS_GPA_MFPH (SYS_BASE + 0x0084U) +#define SYS_GPB_MFPL (SYS_BASE + 0x0088U) +#define SYS_GPB_MFPH (SYS_BASE + 0x008CU) +#define SYS_GPC_MFPL (SYS_BASE + 0x0090U) +#define SYS_GPC_MFPH (SYS_BASE + 0x0094U) +#define SYS_GPD_MFPL (SYS_BASE + 0x0098U) +#define SYS_GPD_MFPH (SYS_BASE + 0x009CU) +#define SYS_GPE_MFPL (SYS_BASE + 0x00A0U) +#define SYS_GPE_MFPH (SYS_BASE + 0x00A4U) +#define SYS_GPF_MFPL (SYS_BASE + 0x00A8U) +#define SYS_GPF_MFPH (SYS_BASE + 0x00ACU) +#define SYS_GPG_MFPL (SYS_BASE + 0x00B0U) +#define SYS_GPG_MFPH (SYS_BASE + 0x00B4U) +#define SYS_GPH_MFPL (SYS_BASE + 0x00B8U) +#define SYS_GPH_MFPH (SYS_BASE + 0x00BCU) +#define SYS_GPI_MFPL (SYS_BASE + 0x00C0U) +#define SYS_GPI_MFPH (SYS_BASE + 0x00C4U) +#define SYS_GPJ_MFPL (SYS_BASE + 0x00C8U) +#define SYS_GPJ_MFPH (SYS_BASE + 0x00CCU) +#define SYS_GPK_MFPL (SYS_BASE + 0x00D0U) +#define SYS_GPK_MFPH (SYS_BASE + 0x00D4U) +#define SYS_GPL_MFPL (SYS_BASE + 0x00D8U) +#define SYS_GPL_MFPH (SYS_BASE + 0x00DCU) +#define SYS_GPM_MFPL (SYS_BASE + 0x00E0U) +#define SYS_GPM_MFPH (SYS_BASE + 0x00E4U) +#define SYS_GPN_MFPL (SYS_BASE + 0x00E8U) +#define SYS_GPN_MFPH (SYS_BASE + 0x00ECU) + +#define SYS_USBPMISCR (SYS_BASE + 0x0060U) +#define SYS_USBP0PCR (SYS_BASE + 0x0064U) +#define SYS_USBP1PCR (SYS_BASE + 0x0068U) + +#define CLK_PWRCTL (CLK_BASE + 0x0000U) +#define CLK_SYSCLK0 (CLK_BASE + 0x0004U) +#define CLK_SYSCLK1 (CLK_BASE + 0x0008U) +#define CLK_APBCLK0 (CLK_BASE + 0x000CU) +#define CLK_APBCLK1 (CLK_BASE + 0x0010U) +#define CLK_APBCLK2 (CLK_BASE + 0x0014U) +#define CLK_CLKSEL0 (CLK_BASE + 0x0018U) +#define CLK_CLKSEL1 (CLK_BASE + 0x001CU) +#define CLK_CLKSEL2 (CLK_BASE + 0x0020U) +#define CLK_CLKSEL3 (CLK_BASE + 0x0024U) +#define CLK_CLKSEL4 (CLK_BASE + 0x0028U) + +#define CLK_CLKDIV0 (CLK_BASE + 0x002CU) +#define CLK_CLKDIV1 (CLK_BASE + 0x0030U) +#define CLK_CLKDIV2 (CLK_BASE + 0x0034U) +#define CLK_CLKDIV3 (CLK_BASE + 0x0038U) +#define CLK_CLKDIV4 (CLK_BASE + 0x003CU) +#define CLK_CLKOCTL (CLK_BASE + 0x0040U) + +#define NUREG_EXPORT(vu32RegAddr, vu32BitMask, vu32Value) { vu32RegAddr, #vu32RegAddr, vu32BitMask, #vu32BitMask, vu32Value, #vu32Value } + +void nu_clock_base_init(void); +void nu_sys_ip_reset(uint32_t u32ModuleIndex); +void nu_sys_ipclk_enable(uint32_t eIPClkIdx); +void nu_sys_ipclk_disable(uint32_t eIPClkIdx); +E_SYS_USB0_ID nu_sys_usb0_role(void); +void nu_sys_check_register(S_NU_REG *psNuReg); + +#endif diff --git a/bsp/nuvoton/libraries/ma35/rtt_port/drv_sys_i2c0.c b/bsp/nuvoton/libraries/ma35/rtt_port/drv_sys_i2c0.c new file mode 100644 index 0000000000..9871daf6fb --- /dev/null +++ b/bsp/nuvoton/libraries/ma35/rtt_port/drv_sys_i2c0.c @@ -0,0 +1,303 @@ +/**************************************************************************//** +* +* @copyright (C) 2020 Nuvoton Technology Corp. All rights reserved. +* +* SPDX-License-Identifier: Apache-2.0 +* +* Change Logs: +* Date Author Notes +* 2020-11-11 Wayne First version +* +******************************************************************************/ + +#include +#include "NuMicro.h" + +#define ERROR rt_kprintf +#define RETRY_COUNT 3 +/*---------------------------------------------------------------------------------------------------------*/ +/* Global variables */ +/*---------------------------------------------------------------------------------------------------------*/ +static uint8_t g_u8DeviceAddr = 0xB0; +static uint8_t g_uPageNum; +static uint8_t g_u8RegAddr; +static uint8_t g_u8WriteData; + +static volatile uint8_t g_u8RxData; +static volatile uint8_t g_u8DataLen; +static volatile uint8_t g_u8EndFlag = 0; + +static void I2C0_MasterRx(uint32_t u32Status) +{ + if (u32Status == 0x08) + { + /* START has been transmitted and prepare SLA+W */ + I2C0->DAT = g_u8DeviceAddr | (g_uPageNum << 1); + I2C0->CTL0 = (I2C0->CTL0 & ~0x3c) | I2C_CTL_SI; + } + else if (u32Status == 0x18) + { + /* SLA+W has been transmitted and ACK has been received */ + I2C0->DAT = g_u8RegAddr; + I2C0->CTL0 = (I2C0->CTL0 & ~0x3c) | I2C_CTL_SI; + } + else if (u32Status == 0x20) + { + /* SLA+W has been transmitted and NACK has been received */ + I2C0->CTL0 = (I2C0->CTL0 & ~0x3c) | (I2C_CTL_STA | I2C_CTL_STO | I2C_CTL_SI); + } + else if (u32Status == 0x28) + { + /* DATA has been transmitted and ACK has been received */ + I2C0->CTL0 = (I2C0->CTL0 & ~0x3c) | (I2C_CTL_STA | I2C_CTL_SI); // repeat start + } + else if (u32Status == 0x10) + { + /* Repeat START has been transmitted and prepare SLA+R */ + I2C0->DAT = (g_u8DeviceAddr | (g_uPageNum << 1)) | 0x01; + I2C0->CTL0 = (I2C0->CTL0 & ~0x3c) | I2C_CTL_SI; + } + else if (u32Status == 0x40) + { + /* SLA+R has been transmitted and ACK has been received */ + I2C0->CTL0 = (I2C0->CTL0 & ~0x3c) | I2C_CTL_SI; + } + else if (u32Status == 0x58) + { + /* DATA has been received and NACK has been returned */ + g_u8RxData = I2C0->DAT; + I2C0->CTL0 = (I2C0->CTL0 & ~0x3c) | (I2C_CTL_STO | I2C_CTL_SI); + g_u8EndFlag = 1; + } + else + { + ERROR("Status 0x%x is NOT processed\n", u32Status); + } +} + +static void I2C0_MasterTx(uint32_t u32Status) +{ + if (u32Status == 0x08) + { + /* START has been transmitted */ + I2C0->DAT = g_u8DeviceAddr | (g_uPageNum << 1); /* Write SLA+W to Register I2CDAT */ + I2C0->CTL0 = (I2C0->CTL0 & ~0x3c) | I2C_CTL_SI; + } + else if (u32Status == 0x18) + { + /* SLA+W has been transmitted and ACK has been received */ + I2C0->DAT = g_u8RegAddr; + I2C0->CTL0 = (I2C0->CTL0 & ~0x3c) | I2C_CTL_SI; + } + else if (u32Status == 0x20) + { + /* SLA+W has been transmitted and NACK has been received */ + I2C0->CTL0 = (I2C0->CTL0 & ~0x3c) | (I2C_CTL_STA | I2C_CTL_STO | I2C_CTL_SI); + } + else if (u32Status == 0x28) + { + /* DATA has been transmitted and ACK has been received */ + if ((g_u8DataLen == 0) && (g_u8EndFlag == 0)) + { + I2C0->DAT = g_u8WriteData; + I2C0->CTL0 = (I2C0->CTL0 & ~0x3c) | I2C_CTL_SI; + g_u8DataLen++; + } + else + { + g_u8DataLen = 0; + I2C0->CTL0 = (I2C0->CTL0 & ~0x3c) | (I2C_CTL_STO | I2C_CTL_SI); + g_u8EndFlag = 1; + } + } + else + { + ERROR("Status 0x%x is NOT processed\n", u32Status); + } +} + +static uint32_t ma35d1_write_i2c_data(uint32_t u32Addr, uint32_t u32Data) +{ + uint32_t I2C_TIME_OUT_COUNT = 0x20000; + uint32_t u32Status; + uint32_t u32time_out = 0; + + g_uPageNum = 0; + if (g_uPageNum == 0xff) + { + ERROR("\n address error !!\n"); + return 0; + } + + g_u8RegAddr = u32Addr; + g_u8WriteData = u32Data; + g_u8EndFlag = 0x0; + + I2C0->CTL0 = (I2C0->CTL0 & ~0x3c) | I2C_CTL_STA; + + while (1) + { + if (I2C0->CTL0 & I2C_CTL_SI) + { + u32time_out = 0; + u32Status = I2C0->STATUS0; + I2C0_MasterTx(u32Status); + } + + if (g_u8EndFlag) + { + break; + } + u32time_out++; + if (u32time_out > I2C_TIME_OUT_COUNT) + { + ERROR("i2c Write Time Out!\n"); + return 0; // error + } + } + return 1; +} + +static uint32_t ma35d1_read_i2c_data(uint32_t u32Addr, uint32_t *pu32Data) +{ + uint32_t I2C_TIME_OUT_COUNT = 0x200000; + uint32_t u32Status; + uint32_t u32time_out = 0; + + g_uPageNum = 0; + if (g_uPageNum == 0xff) + { + ERROR("\n address error !!\n"); + return 0; + } + + g_u8RegAddr = u32Addr; + g_u8EndFlag = 0x0; + + I2C0->CTL0 = (I2C0->CTL0 & ~0x3c) | I2C_CTL_STA; + + while (1) + { + if (I2C0->CTL0 & I2C_CTL_SI) + { + u32time_out = 0; + u32Status = I2C0->STATUS0; + I2C0_MasterRx(u32Status); + } + + if (g_u8EndFlag) + { + break; + } + + u32time_out++; + if (u32time_out > I2C_TIME_OUT_COUNT) + { + ERROR("i2c Read Time Out!\n"); + return 1; // error + } + } + + *pu32Data = g_u8RxData; + return 2; +} + +static uint32_t ma35d1_read_pmic_data(uint32_t u32Addr, uint32_t *pu32Data) +{ + uint32_t j = RETRY_COUNT; + + while (j-- > 0) + { + if (ma35d1_read_i2c_data(u32Addr, pu32Data) == 2) + { + break; + } + } + + if (j <= 0) + { + ERROR("\n READ ERROR! \n"); + return 0; + } + + return 1; +} + +static uint32_t ma35d1_write_pmic_data(uint32_t u32Addr, uint32_t u32Data) +{ + uint32_t j = RETRY_COUNT; + + while (j-- > 0) + { + if (ma35d1_write_i2c_data(u32Addr, u32Data) == 1) + { + break; + } + } + + if (j <= 0) + { + ERROR("\n WRITE ERROR [%d]! \n", j); + return 0; + } + + return 1; +} + +static void ma35d1_i2c0_init(uint32_t sys_clk) +{ + unsigned long clk_rate; + uint32_t u32Div, speed; + + outpw((void *)0x40460208, inpw((void *)0x40460208) | (0x3fff << 16)); // enable GPIO clock + outpw((void *)0x40460210, inpw((void *)0x40460210) | (0x1 << 0)); // I2C0 CLK + + outpw(0x40460098, ((inpw(0x40460098) & ~0x0f000000) | (0x6 << 24))); // PD.6 I2C0_SDA + outpw(0x40460098, ((inpw(0x40460098) & ~0xf0000000) | (0x6 << 28))); // PD.7 I2C0_CLK + outpw(0x400400F0, 0x5 << 12); // pull high + + /* i2c_clk = 100KHz */ + clk_rate = sys_clk; + speed = 100 * 1000; + + /* assume speed above 1000 are Hz-specified */ + if (speed > 1000) speed = speed / 1000; + if (speed > 400) speed = 400; + + u32Div = (uint32_t)(((clk_rate * 10U) / (speed * 4U) + 5U) / 10U - 1U); + + I2C0->CLKDIV = u32Div; + I2C0->CTL0 = I2C0->CTL0 | I2C_CTL0_I2CEN_Msk; /* i2c enable */ +} + +uint32_t ma35d1_set_cpu_voltage(uint32_t sys_clk, uint32_t u32Vol) +{ + /* + RegValue = (Voltage - 0.3) / 0.01 + RegValue(hex) Voltage(v) + 0x5B 1.22 + 0x5C 1.23 + 0x5D 1.24 + 0x5F 1.25 + 0x60 1.26 + 0x61 1.27 + 0x62 1.28 + 0x63 1.29 + 0x64 1.30 + 0x65 1.31 + 0x66 1.32 + 0x67 1.33 + 0x68 1.34 + 0x69 1.35 + */ + uint32_t u32Data = 0; + + if ((u32Vol < 0x59) || (u32Vol > 0x68)) + return 0; + + ma35d1_i2c0_init(sys_clk); + ma35d1_write_pmic_data(0xA4, u32Vol); + ma35d1_read_pmic_data(0xA4, &u32Data); + + return (u32Data == u32Vol); +} diff --git a/bsp/nuvoton/libraries/ma35/rtt_port/drv_timer.c b/bsp/nuvoton/libraries/ma35/rtt_port/drv_timer.c new file mode 100644 index 0000000000..5b98e49718 --- /dev/null +++ b/bsp/nuvoton/libraries/ma35/rtt_port/drv_timer.c @@ -0,0 +1,307 @@ +/**************************************************************************//** +* +* @copyright (C) 2020 Nuvoton Technology Corp. All rights reserved. +* +* SPDX-License-Identifier: Apache-2.0 +* +* Change Logs: +* Date Author Notes +* 2021-9-17 Wayne First version +* +******************************************************************************/ + +#include + +#if defined(BSP_USING_TIMER) && defined(RT_USING_HWTIMER) + +#include +#include "NuMicro.h" +#include + +/* Private define ---------------------------------------------------------------*/ +#define NU_TIMER_DEVICE(timer) (nu_timer_t)(timer) + +enum +{ + TIMER_START = -1, +#if defined(BSP_USING_TIMER0) + TIMER0_IDX, +#endif +#if defined(BSP_USING_TIMER1) + TIMER1_IDX, +#endif +#if defined(BSP_USING_TIMER2) + TIMER2_IDX, +#endif +#if defined(BSP_USING_TIMER3) + TIMER3_IDX, +#endif +#if defined(BSP_USING_TIMER4) + TIMER4_IDX, +#endif +#if defined(BSP_USING_TIMER5) + TIMER5_IDX, +#endif +#if defined(BSP_USING_TIMER6) + TIMER6_IDX, +#endif +#if defined(BSP_USING_TIMER7) + TIMER7_IDX, +#endif +#if defined(BSP_USING_TIMER8) + TIMER8_IDX, +#endif +#if defined(BSP_USING_TIMER9) + TIMER9_IDX, +#endif +#if defined(BSP_USING_TIMER10) + TIMER10_IDX, +#endif +#if defined(BSP_USING_TIMER11) + TIMER11_IDX, +#endif + TIMER_CNT +}; + +/* Private typedef --------------------------------------------------------------*/ +struct nu_timer +{ + rt_hwtimer_t parent; + char *name; + TIMER_T *base; + IRQn_Type irqn; + uint32_t rstidx; + uint32_t modid; +}; +typedef struct nu_timer *nu_timer_t; + +/* Private functions ------------------------------------------------------------*/ +static void nu_timer_init(rt_hwtimer_t *timer, rt_uint32_t state); +static rt_err_t nu_timer_start(rt_hwtimer_t *timer, rt_uint32_t cnt, rt_hwtimer_mode_t opmode); +static void nu_timer_stop(rt_hwtimer_t *timer); +static rt_uint32_t nu_timer_count_get(rt_hwtimer_t *timer); +static rt_err_t nu_timer_control(rt_hwtimer_t *timer, rt_uint32_t cmd, void *args); + +/* Public functions -------------------------------------------------------------*/ + + +/* Private variables ------------------------------------------------------------*/ +static struct nu_timer nu_timer_arr [] = +{ +#if defined(BSP_USING_TIMER0) + { .name = "timer0", .base = TIMER0, .irqn = TMR0_IRQn, .rstidx = TMR0_RST, .modid = TMR0_MODULE }, +#endif +#if defined(BSP_USING_TIMER1) + { .name = "timer1", .base = TIMER1, .irqn = TMR1_IRQn, .rstidx = TMR1_RST, .modid = TMR1_MODULE }, +#endif +#if defined(BSP_USING_TIMER2) + { .name = "timer2", .base = TIMER2, .irqn = TMR2_IRQn, .rstidx = TMR2_RST, .modid = TMR2_MODULE }, +#endif +#if defined(BSP_USING_TIMER3) + { .name = "timer3", .base = TIMER3, .irqn = TMR3_IRQn, .rstidx = TMR3_RST, .modid = TMR3_MODULE }, +#endif +#if defined(BSP_USING_TIMER4) + { .name = "timer4", .base = TIMER4, .irqn = TMR4_IRQn, .rstidx = TMR4_RST, .modid = TMR4_MODULE }, +#endif +#if defined(BSP_USING_TIMER5) + { .name = "timer5", .base = TIMER5, .irqn = TMR5_IRQn, .rstidx = TMR5_RST, .modid = TMR5_MODULE }, +#endif +#if defined(BSP_USING_TIMER6) + { .name = "timer6", .base = TIMER6, .irqn = TMR6_IRQn, .rstidx = TMR6_RST, .modid = TMR6_MODULE }, +#endif +#if defined(BSP_USING_TIMER7) + { .name = "timer7", .base = TIMER7, .irqn = TMR7_IRQn, .rstidx = TMR7_RST, .modid = TMR7_MODULE }, +#endif +#if defined(BSP_USING_TIMER8) + { .name = "timer8", .base = TIMER8, .irqn = TMR8_IRQn, .rstidx = TMR8_RST, .modid = TMR8_MODULE }, +#endif +#if defined(BSP_USING_TIMER9) + { .name = "timer9", .base = TIMER9, .irqn = TMR9_IRQn, .rstidx = TMR9_RST, .modid = TMR9_MODULE }, +#endif +#if defined(BSP_USING_TIMER10) + { .name = "timer10", .base = TIMER10, .irqn = TMR10_IRQn, .rstidx = TMR10_RST, .modid = TMR10_MODULE }, +#endif +#if defined(BSP_USING_TIMER11) + { .name = "timer11", .base = TIMER11, .irqn = TMR11_IRQn, .rstidx = TMR11_RST, .modid = TMR11_MODULE }, +#endif +}; + +static struct rt_hwtimer_info nu_timer_info = +{ + __HXT, /* maximum count frequency */ + (__HXT / 256), /* minimum count frequency */ + 0xFFFFFF, /* the maximum counter value */ + HWTIMER_CNTMODE_UP, /* Increment or Decreasing count mode */ +}; + +static struct rt_hwtimer_ops nu_timer_ops = +{ + nu_timer_init, + nu_timer_start, + nu_timer_stop, + nu_timer_count_get, + nu_timer_control +}; + +/* Functions define ------------------------------------------------------------*/ +static void nu_timer_init(rt_hwtimer_t *timer, rt_uint32_t state) +{ + nu_timer_t psNuTmr = NU_TIMER_DEVICE(timer); + RT_ASSERT(psNuTmr != RT_NULL); + + if (1 == state) + { + uint32_t timer_clk; + struct rt_hwtimer_info *info = &nu_timer_info; + + timer_clk = TIMER_GetModuleClock(psNuTmr->base); + info->maxfreq = timer_clk; + info->minfreq = timer_clk / 256; + TIMER_Open(psNuTmr->base, TIMER_ONESHOT_MODE, 1); + TIMER_EnableInt(psNuTmr->base); + rt_hw_interrupt_umask(psNuTmr->irqn); + } + else + { + rt_hw_interrupt_mask(psNuTmr->irqn); + TIMER_DisableInt(psNuTmr->base); + TIMER_Close(psNuTmr->base); + } +} + +static rt_err_t nu_timer_start(rt_hwtimer_t *timer, rt_uint32_t cnt, rt_hwtimer_mode_t opmode) +{ + rt_err_t ret = RT_EINVAL; + rt_uint32_t u32OpMode; + + nu_timer_t psNuTmr = NU_TIMER_DEVICE(timer); + RT_ASSERT(psNuTmr != RT_NULL); + + if (cnt <= 1 || cnt > 0xFFFFFF) + { + goto exit_nu_timer_start; + } + + switch (opmode) + { + case HWTIMER_MODE_PERIOD: + u32OpMode = TIMER_PERIODIC_MODE; + break; + + case HWTIMER_MODE_ONESHOT: + u32OpMode = TIMER_ONESHOT_MODE; + break; + + default: + goto exit_nu_timer_start; + } + + TIMER_SET_CMP_VALUE(psNuTmr->base, cnt); + TIMER_SET_OPMODE(psNuTmr->base, u32OpMode); + TIMER_EnableInt(psNuTmr->base); + rt_hw_interrupt_umask(psNuTmr->irqn); + + TIMER_Start(psNuTmr->base); + + ret = RT_EOK; + +exit_nu_timer_start: + + return -(ret); +} + +static void nu_timer_stop(rt_hwtimer_t *timer) +{ + nu_timer_t psNuTmr = NU_TIMER_DEVICE(timer); + RT_ASSERT(psNuTmr != RT_NULL); + + rt_hw_interrupt_mask(psNuTmr->irqn); + TIMER_DisableInt(psNuTmr->base); + TIMER_Stop(psNuTmr->base); + TIMER_ResetCounter(psNuTmr->base); +} + +static rt_uint32_t nu_timer_count_get(rt_hwtimer_t *timer) +{ + nu_timer_t psNuTmr = NU_TIMER_DEVICE(timer); + RT_ASSERT(psNuTmr != RT_NULL); + + return TIMER_GetCounter(psNuTmr->base); +} + +static rt_err_t nu_timer_control(rt_hwtimer_t *timer, rt_uint32_t cmd, void *args) +{ + rt_err_t ret = RT_EOK; + nu_timer_t psNuTmr = NU_TIMER_DEVICE(timer); + RT_ASSERT(psNuTmr != RT_NULL); + + switch (cmd) + { + case HWTIMER_CTRL_FREQ_SET: + { + uint32_t clk; + uint32_t pre; + + clk = TIMER_GetModuleClock(psNuTmr->base); + pre = clk / *((uint32_t *)args) - 1; + TIMER_SET_PRESCALE_VALUE(psNuTmr->base, pre); + *((uint32_t *)args) = clk / (pre + 1) ; + } + break; + + case HWTIMER_CTRL_STOP: + TIMER_Stop(psNuTmr->base); + break; + + default: + ret = RT_EINVAL; + break; + } + + return -(ret); +} + +/** + * All UART interrupt service routine + */ +static void nu_timer_isr(int vector, void *param) +{ + nu_timer_t psNuTmr = NU_TIMER_DEVICE(param); + RT_ASSERT(psNuTmr != RT_NULL); + + if (TIMER_GetIntFlag(psNuTmr->base)) + { + TIMER_ClearIntFlag(psNuTmr->base); + rt_device_hwtimer_isr(&psNuTmr->parent); + } +} + +int rt_hw_timer_init(void) +{ + int i; + rt_err_t ret = RT_EOK; + for (i = (TIMER_START + 1); i < TIMER_CNT; i++) + { + CLK_EnableModuleClock(nu_timer_arr[i].modid); + + SYS_ResetModule(nu_timer_arr[i].rstidx); + + /* Register Timer information. */ + nu_timer_arr[i].parent.info = &nu_timer_info; + + /* Register Timer operation. */ + nu_timer_arr[i].parent.ops = &nu_timer_ops; + + /* Register Timer interrupt service routine. */ + rt_hw_interrupt_install(nu_timer_arr[i].irqn, nu_timer_isr, &nu_timer_arr[i], nu_timer_arr[i].name); + + /* Register RT hwtimer device. */ + ret = rt_device_hwtimer_register(&nu_timer_arr[i].parent, nu_timer_arr[i].name, &nu_timer_arr[i]); + RT_ASSERT(ret == RT_EOK); + } + return 0; +} + +INIT_BOARD_EXPORT(rt_hw_timer_init); + +#endif //#if defined(BSP_USING_TIMER) && defined(RT_USING_HWTIMER) diff --git a/bsp/nuvoton/libraries/ma35/rtt_port/drv_tpwm.c b/bsp/nuvoton/libraries/ma35/rtt_port/drv_tpwm.c new file mode 100644 index 0000000000..7cf2c4ae22 --- /dev/null +++ b/bsp/nuvoton/libraries/ma35/rtt_port/drv_tpwm.c @@ -0,0 +1,265 @@ +/**************************************************************************//** +* +* @copyright (C) 2020 Nuvoton Technology Corp. All rights reserved. +* +* SPDX-License-Identifier: Apache-2.0 +* +* Change Logs: +* Date Author Notes +* 2021-9-22 Wayne First version +* +* Note: 2 channels of a tpwm have the same output. +******************************************************************************/ + +#include + +#if (defined(BSP_USING_TPWM) && defined(RT_USING_PWM)) + +#define LOG_TAG "drv.tpwm" +#define DBG_ENABLE +#define DBG_SECTION_NAME LOG_TAG +#define DBG_LEVEL DBG_INFO +#define TPWM_CHANNEL_NUM 2 +#include + +#include +#include "NuMicro.h" +#include + +/* Private define ---------------------------------------------------------------*/ +#define NU_TPWM_DEVICE(tpwm) (nu_tpwm_t)(tpwm) + +enum +{ + TPWM_START = -1, +#if defined(BSP_USING_TPWM0) + TPWM0_IDX, +#endif +#if defined(BSP_USING_TPWM1) + TPWM1_IDX, +#endif +#if defined(BSP_USING_TPWM2) + TPWM2_IDX, +#endif +#if defined(BSP_USING_TPWM3) + TPWM3_IDX, +#endif +#if defined(BSP_USING_TPWM4) + TPWM4_IDX, +#endif +#if defined(BSP_USING_TPWM5) + TPWM5_IDX, +#endif +#if defined(BSP_USING_TPWM6) + TPWM6_IDX, +#endif +#if defined(BSP_USING_TPWM7) + TPWM7_IDX, +#endif +#if defined(BSP_USING_TPWM8) + TPWM8_IDX, +#endif +#if defined(BSP_USING_TPWM9) + TPWM9_IDX, +#endif +#if defined(BSP_USING_TPWM10) + TPWM10_IDX, +#endif +#if defined(BSP_USING_TPWM11) + TPWM11_IDX, +#endif + TPWM_CNT +}; + +/* Private typedef --------------------------------------------------------------*/ +struct nu_tpwm +{ + struct rt_device_pwm tpwm_dev; + char *name; + TIMER_T *base; + uint32_t rstidx; + uint32_t modid; + rt_uint32_t channel_mask; //TPWM_CH0 | TPWM_CH1 +} ; + +typedef struct nu_tpwm *nu_tpwm_t; + +/* Private functions ------------------------------------------------------------*/ +static rt_err_t nu_tpwm_enable(struct rt_device_pwm *tpwm_dev, struct rt_pwm_configuration *tpwm_config, rt_bool_t enable); +static rt_err_t nu_tpwm_set(struct rt_device_pwm *tpwm_dev, struct rt_pwm_configuration *tpwm_config); +static rt_err_t nu_tpwm_get(struct rt_device_pwm *tpwm_dev, struct rt_pwm_configuration *tpwm_config); +static rt_err_t nu_tpwm_control(struct rt_device_pwm *tpwm_dev, int cmd, void *arg); + +/* Private variables ------------------------------------------------------------*/ +static struct nu_tpwm nu_tpwm_arr [] = +{ +#if defined(BSP_USING_TPWM0) + { .name = "tpwm0", .base = TIMER0, .rstidx = TMR0_RST, .modid = TMR0_MODULE }, +#endif +#if defined(BSP_USING_TPWM1) + { .name = "tpwm1", .base = TIMER1, .rstidx = TMR1_RST, .modid = TMR1_MODULE }, +#endif +#if defined(BSP_USING_TPWM2) + { .name = "tpwm2", .base = TIMER2, .rstidx = TMR2_RST, .modid = TMR2_MODULE }, +#endif +#if defined(BSP_USING_TPWM3) + { .name = "tpwm3", .base = TIMER3, .rstidx = TMR3_RST, .modid = TMR3_MODULE }, +#endif +#if defined(BSP_USING_TPWM4) + { .name = "tpwm4", .base = TIMER4, .rstidx = TMR4_RST, .modid = TMR4_MODULE }, +#endif +#if defined(BSP_USING_TPWM5) + { .name = "tpwm5", .base = TIMER5, .rstidx = TMR5_RST, .modid = TMR5_MODULE }, +#endif +#if defined(BSP_USING_TPWM6) + { .name = "tpwm6", .base = TIMER6, .rstidx = TMR6_RST, .modid = TMR6_MODULE }, +#endif +#if defined(BSP_USING_TPWM7) + { .name = "tpwm7", .base = TIMER7, .rstidx = TMR7_RST, .modid = TMR7_MODULE }, +#endif +#if defined(BSP_USING_TPWM8) + { .name = "tpwm8", .base = TIMER8, .rstidx = TMR8_RST, .modid = TMR8_MODULE }, +#endif +#if defined(BSP_USING_TPWM9) + { .name = "tpwm9", .base = TIMER9, .rstidx = TMR9_RST, .modid = TMR9_MODULE }, +#endif +#if defined(BSP_USING_TPWM10) + { .name = "tpwm10", .base = TIMER10, .rstidx = TMR10_RST, .modid = TMR10_MODULE }, +#endif +#if defined(BSP_USING_TPWM11) + { .name = "tpwm11", .base = TIMER11, .rstidx = TMR11_RST, .modid = TMR11_MODULE }, +#endif +}; + +static struct rt_pwm_ops nu_tpwm_ops = +{ + nu_tpwm_control +}; + +/* Functions define ------------------------------------------------------------*/ +static rt_err_t nu_tpwm_enable(struct rt_device_pwm *tpwm_dev, struct rt_pwm_configuration *tpwm_config, rt_bool_t enable) +{ + rt_err_t result = RT_EOK; + rt_uint32_t tpwm_channel = tpwm_config->channel; + nu_tpwm_t psNuTPWM = NU_TPWM_DEVICE(tpwm_dev->parent.user_data); + + if (enable == RT_TRUE) + { + if (psNuTPWM->channel_mask == 0) + { + TPWM_START_COUNTER(psNuTPWM->base); + } + psNuTPWM->channel_mask |= (1 << tpwm_channel); + TPWM_ENABLE_OUTPUT(psNuTPWM->base, psNuTPWM->channel_mask); + } + else + { + psNuTPWM->channel_mask &= ~(1 << tpwm_channel); + TPWM_ENABLE_OUTPUT(psNuTPWM->base, psNuTPWM->channel_mask); + if (psNuTPWM->channel_mask == 0) + { + TPWM_STOP_COUNTER(psNuTPWM->base); + } + } + + return result; +} + +static rt_err_t nu_tpwm_set(struct rt_device_pwm *tpwm_dev, struct rt_pwm_configuration *tpwm_config) +{ + if (tpwm_config->period <= 0) + return -(RT_ERROR); + + rt_uint32_t tpwm_freq, tpwm_dutycycle ; + rt_uint32_t tpwm_period = tpwm_config->period; + rt_uint32_t tpwm_pulse = tpwm_config->pulse; + nu_tpwm_t psNuTPWM = NU_TPWM_DEVICE(tpwm_dev->parent.user_data); + + //rt_uint32_t pre_tpwm_prescaler = TPWM_GET_PRESCALER(psNuTPWM->base); + + tpwm_freq = 1000000000 / tpwm_period; + tpwm_dutycycle = (tpwm_pulse * 100) / tpwm_period; + + TPWM_ConfigOutputFreqAndDuty(psNuTPWM->base, tpwm_freq, tpwm_dutycycle) ; + + return RT_EOK; +} + +static rt_err_t nu_tpwm_get(struct rt_device_pwm *tpwm_dev, struct rt_pwm_configuration *tpwm_config) +{ + rt_uint32_t tpwm_real_period, tpwm_real_duty, time_tick, u32TPWMClockFreq ; + + nu_tpwm_t psNuTPWM = NU_TPWM_DEVICE(tpwm_dev->parent.user_data); + rt_uint32_t tpwm_prescale = TPWM_GET_PRESCALER(psNuTPWM->base); + rt_uint32_t tpwm_period = TPWM_GET_PERIOD(psNuTPWM->base); + rt_uint32_t tpwm_pulse = TPWM_GET_CMPDAT(psNuTPWM->base); + + u32TPWMClockFreq = TIMER_GetModuleClock(psNuTPWM->base); + time_tick = (uint64_t)1000000000000 / u32TPWMClockFreq; + + LOG_I("%s reg--> %d %d %d %d %d\n", psNuTPWM->name, tpwm_prescale, tpwm_period, tpwm_pulse, u32TPWMClockFreq, time_tick); + + tpwm_real_period = (((tpwm_prescale + 1) * (tpwm_period + 1)) * time_tick) / 1000; + tpwm_real_duty = (((tpwm_prescale + 1) * tpwm_pulse * time_tick)) / 1000; + tpwm_config->period = tpwm_real_period; + tpwm_config->pulse = tpwm_real_duty; + + LOG_I("%s %d %d %d\n", psNuTPWM->name, tpwm_config->channel, tpwm_config->period, tpwm_config->pulse); + + return RT_EOK; +} + +static rt_err_t nu_tpwm_control(struct rt_device_pwm *tpwm_dev, int cmd, void *arg) +{ + struct rt_pwm_configuration *tpwm_config = (struct rt_pwm_configuration *)arg; + + RT_ASSERT(tpwm_dev != RT_NULL); + RT_ASSERT(tpwm_config != RT_NULL); + + nu_tpwm_t psNuTPWM = NU_TPWM_DEVICE(tpwm_dev->parent.user_data); + RT_ASSERT(psNuTPWM != RT_NULL); + RT_ASSERT(psNuTPWM->base != RT_NULL); + + if ((tpwm_config->channel + 1) > TPWM_CHANNEL_NUM) + return -(RT_ERROR); + + switch (cmd) + { + case PWM_CMD_ENABLE: + return nu_tpwm_enable(tpwm_dev, tpwm_config, RT_TRUE); + case PWM_CMD_DISABLE: + return nu_tpwm_enable(tpwm_dev, tpwm_config, RT_FALSE); + case PWM_CMD_SET: + return nu_tpwm_set(tpwm_dev, tpwm_config); + case PWM_CMD_GET: + return nu_tpwm_get(tpwm_dev, tpwm_config); + default: + break; + } + return -(RT_EINVAL); +} + +int rt_hw_tpwm_init(void) +{ + int i; + rt_err_t ret = RT_EOK; + for (i = (TPWM_START + 1); i < TPWM_CNT; i++) + { + nu_tpwm_arr[i].channel_mask = 0; + + CLK_EnableModuleClock(nu_tpwm_arr[i].modid); + + SYS_ResetModule(nu_tpwm_arr[i].rstidx); + + TPWM_ENABLE_PWM_MODE(nu_tpwm_arr[i].base); + + /* Register RT PWM device. */ + ret = rt_device_pwm_register(&nu_tpwm_arr[i].tpwm_dev, nu_tpwm_arr[i].name, &nu_tpwm_ops, &nu_tpwm_arr[i]); + RT_ASSERT(ret == RT_EOK); + } + return 0; +} + +INIT_DEVICE_EXPORT(rt_hw_tpwm_init); + +#endif //#if (defined(BSP_USING_TPWM) && defined(RT_USING_PWM)) diff --git a/bsp/nuvoton/libraries/ma35/rtt_port/drv_uart.c b/bsp/nuvoton/libraries/ma35/rtt_port/drv_uart.c new file mode 100644 index 0000000000..ce80525109 --- /dev/null +++ b/bsp/nuvoton/libraries/ma35/rtt_port/drv_uart.c @@ -0,0 +1,1071 @@ +/**************************************************************************//** +* +* @copyright (C) 2020 Nuvoton Technology Corp. All rights reserved. +* +* SPDX-License-Identifier: Apache-2.0 +* +* Change Logs: +* Date Author Notes +* 2020-12-12 Wayne First version +* +******************************************************************************/ + +#include + +#if defined(BSP_USING_UART) + +#include +#include "drv_uart.h" +#include "drv_sys.h" +#include "drv_common.h" + +#if defined(RT_SERIAL_USING_DMA) + #include +#endif + +/* Private define ---------------------------------------------------------------*/ +enum +{ + UART_START = -1, +#if defined(BSP_USING_UART0) + UART0_IDX, +#endif +#if defined(BSP_USING_UART1) + UART1_IDX, +#endif +#if defined(BSP_USING_UART2) + UART2_IDX, +#endif +#if defined(BSP_USING_UART3) + UART3_IDX, +#endif +#if defined(BSP_USING_UART4) + UART4_IDX, +#endif +#if defined(BSP_USING_UART5) + UART5_IDX, +#endif +#if defined(BSP_USING_UART6) + UART6_IDX, +#endif +#if defined(BSP_USING_UART7) + UART7_IDX, +#endif +#if defined(BSP_USING_UART8) + UART8_IDX, +#endif +#if defined(BSP_USING_UART9) + UART9_IDX, +#endif +#if defined(BSP_USING_UART10) + UART10_IDX, +#endif +#if defined(BSP_USING_UART11) + UART11_IDX, +#endif +#if defined(BSP_USING_UART12) + UART12_IDX, +#endif +#if defined(BSP_USING_UART13) + UART13_IDX, +#endif +#if defined(BSP_USING_UART14) + UART14_IDX, +#endif +#if defined(BSP_USING_UART15) + UART15_IDX, +#endif +#if defined(BSP_USING_UART16) + UART16_IDX, +#endif + UART_CNT +}; + +/* Private typedef --------------------------------------------------------------*/ +struct nu_uart +{ + rt_serial_t dev; + char *name; + UART_T *uart_base; + IRQn_Type irqn; + uint32_t rstidx; + +#if defined(RT_SERIAL_USING_DMA) + uint32_t dma_flag; + int16_t pdma_perp_tx; + int8_t pdma_chanid_tx; + + int16_t pdma_perp_rx; + int8_t pdma_chanid_rx; + int32_t rx_write_offset; + int32_t rxdma_trigger_len; + + nu_pdma_desc_t pdma_rx_desc; +#endif + +}; +typedef struct nu_uart *nu_uart_t; + +/* Private functions ------------------------------------------------------------*/ +static rt_err_t nu_uart_configure(struct rt_serial_device *serial, struct serial_configure *cfg); +static rt_err_t nu_uart_control(struct rt_serial_device *serial, int cmd, void *arg); +static int nu_uart_send(struct rt_serial_device *serial, char c); +static int nu_uart_receive(struct rt_serial_device *serial); + +#if defined(RT_SERIAL_USING_DMA) + static rt_size_t nu_uart_dma_transmit(struct rt_serial_device *serial, rt_uint8_t *buf, rt_size_t size, int direction); + static void nu_pdma_uart_rx_cb(void *pvOwner, uint32_t u32Events); + static void nu_pdma_uart_tx_cb(void *pvOwner, uint32_t u32Events); +#endif + +/* Public functions ------------------------------------------------------------*/ + +/* Private variables ------------------------------------------------------------*/ + +static const struct rt_uart_ops nu_uart_ops = +{ + .configure = nu_uart_configure, + .control = nu_uart_control, + .putc = nu_uart_send, + .getc = nu_uart_receive, +#if defined(RT_SERIAL_USING_DMA) + .dma_transmit = nu_uart_dma_transmit +#else + .dma_transmit = RT_NULL +#endif +}; + +static const struct serial_configure nu_uart_default_config = + RT_SERIAL_CONFIG_DEFAULT; + +static struct nu_uart nu_uart_arr [] = +{ +#if defined(BSP_USING_UART0) + { + .name = "uart0", + .uart_base = UART0, + .irqn = UART0_IRQn, + .rstidx = UART0_RST, + +#if defined(RT_SERIAL_USING_DMA) +#if defined(BSP_USING_UART0_TX_DMA) + .pdma_perp_tx = PDMA_UART0_TX, +#else + .pdma_perp_tx = NU_PDMA_UNUSED, +#endif +#if defined(BSP_USING_UART0_RX_DMA) + .pdma_perp_rx = PDMA_UART0_RX, + .rx_write_offset = 0, +#else + .pdma_perp_rx = NU_PDMA_UNUSED, +#endif +#endif + }, +#endif + +#if defined(BSP_USING_UART1) + { + .name = "uart1", + .uart_base = UART1, + .irqn = UART1_IRQn, + .rstidx = UART1_RST, + +#if defined(RT_SERIAL_USING_DMA) +#if defined(BSP_USING_UART1_TX_DMA) + .pdma_perp_tx = PDMA_UART1_TX, +#else + .pdma_perp_tx = NU_PDMA_UNUSED, +#endif +#if defined(BSP_USING_UART1_RX_DMA) + .pdma_perp_rx = PDMA_UART1_RX, + .rx_write_offset = 0, +#else + .pdma_perp_rx = NU_PDMA_UNUSED, +#endif +#endif + }, +#endif + +#if defined(BSP_USING_UART2) + { + .name = "uart2", + .uart_base = UART2, + .irqn = UART2_IRQn, + .rstidx = UART2_RST, + +#if defined(RT_SERIAL_USING_DMA) +#if defined(BSP_USING_UART2_TX_DMA) + .pdma_perp_tx = PDMA_UART2_TX, +#else + .pdma_perp_tx = NU_PDMA_UNUSED, +#endif +#if defined(BSP_USING_UART2_RX_DMA) + .pdma_perp_rx = PDMA_UART2_RX, + .rx_write_offset = 0, +#else + .pdma_perp_rx = NU_PDMA_UNUSED, +#endif +#endif + }, +#endif + +#if defined(BSP_USING_UART3) + { + .name = "uart3", + .uart_base = UART3, + .irqn = UART3_IRQn, + .rstidx = UART3_RST, + +#if defined(RT_SERIAL_USING_DMA) +#if defined(BSP_USING_UART3_TX_DMA) + .pdma_perp_tx = PDMA_UART3_TX, +#else + .pdma_perp_tx = NU_PDMA_UNUSED, +#endif +#if defined(BSP_USING_UART3_RX_DMA) + .pdma_perp_rx = PDMA_UART3_RX, + .rx_write_offset = 0, +#else + .pdma_perp_rx = NU_PDMA_UNUSED, +#endif +#endif + }, +#endif + +#if defined(BSP_USING_UART4) + { + .name = "uart4", + .uart_base = UART4, + .irqn = UART4_IRQn, + .rstidx = UART4_RST, + +#if defined(RT_SERIAL_USING_DMA) +#if defined(BSP_USING_UART4_TX_DMA) + .pdma_perp_tx = PDMA_UART4_TX, +#else + .pdma_perp_tx = NU_PDMA_UNUSED, +#endif +#if defined(BSP_USING_UART4_RX_DMA) + .pdma_perp_rx = PDMA_UART4_RX, + .rx_write_offset = 0, +#else + .pdma_perp_rx = NU_PDMA_UNUSED, +#endif +#endif + }, +#endif + +#if defined(BSP_USING_UART5) + { + .name = "uart5", + .uart_base = UART5, + .irqn = UART5_IRQn, + .rstidx = UART5_RST, + +#if defined(RT_SERIAL_USING_DMA) +#if defined(BSP_USING_UART5_TX_DMA) + .pdma_perp_tx = PDMA_UART5_TX, +#else + .pdma_perp_tx = NU_PDMA_UNUSED, +#endif +#if defined(BSP_USING_UART5_RX_DMA) + .pdma_perp_rx = PDMA_UART5_RX, + .rx_write_offset = 0, +#else + .pdma_perp_rx = NU_PDMA_UNUSED, +#endif +#endif + }, +#endif + +#if defined(BSP_USING_UART6) + { + .name = "uart6", + .uart_base = UART6, + .irqn = UART6_IRQn, + .rstidx = UART6_RST, + +#if defined(RT_SERIAL_USING_DMA) +#if defined(BSP_USING_UART6_TX_DMA) + .pdma_perp_tx = PDMA_UART6_TX, +#else + .pdma_perp_tx = NU_PDMA_UNUSED, +#endif +#if defined(BSP_USING_UART6_RX_DMA) + .pdma_perp_rx = PDMA_UART6_RX, + .rx_write_offset = 0, +#else + .pdma_perp_rx = NU_PDMA_UNUSED, +#endif +#endif + }, +#endif + +#if defined(BSP_USING_UART7) + { + .name = "uart7", + .uart_base = UART7, + .irqn = UART7_IRQn, + .rstidx = UART7_RST, + +#if defined(RT_SERIAL_USING_DMA) +#if defined(BSP_USING_UART7_TX_DMA) + .pdma_perp_tx = PDMA_UART7_TX, +#else + .pdma_perp_tx = NU_PDMA_UNUSED, +#endif +#if defined(BSP_USING_UART7_RX_DMA) + .pdma_perp_rx = PDMA_UART7_RX, + .rx_write_offset = 0, +#else + .pdma_perp_rx = NU_PDMA_UNUSED, +#endif +#endif + }, +#endif + +#if defined(BSP_USING_UART8) + { + .name = "uart8", + .uart_base = UART8, + .irqn = UART8_IRQn, + .rstidx = UART8_RST, + +#if defined(RT_SERIAL_USING_DMA) +#if defined(BSP_USING_UART8_TX_DMA) + .pdma_perp_tx = PDMA_UART8_TX, +#else + .pdma_perp_tx = NU_PDMA_UNUSED, +#endif +#if defined(BSP_USING_UART8_RX_DMA) + .pdma_perp_rx = PDMA_UART8_RX, + .rx_write_offset = 0, +#else + .pdma_perp_rx = NU_PDMA_UNUSED, +#endif +#endif + }, +#endif + +#if defined(BSP_USING_UART9) + { + .name = "uart9", + .uart_base = UART9, + .irqn = UART9_IRQn, + .rstidx = UART9_RST, + +#if defined(RT_SERIAL_USING_DMA) +#if defined(BSP_USING_UART9_TX_DMA) + .pdma_perp_tx = PDMA_UART9_TX, +#else + .pdma_perp_tx = NU_PDMA_UNUSED, +#endif +#if defined(BSP_USING_UART9_RX_DMA) + .pdma_perp_rx = PDMA_UART9_RX, + .rx_write_offset = 0, +#else + .pdma_perp_rx = NU_PDMA_UNUSED, +#endif +#endif + }, +#endif + +#if defined(BSP_USING_UART10) + { + .name = "uart10", + .uart_base = UART10, + .irqn = UART10_IRQn, + .rstidx = UART10_RST, + +#if defined(RT_SERIAL_USING_DMA) +#if defined(BSP_USING_UART10_TX_DMA) + .pdma_perp_tx = PDMA_UART10_TX, +#else + .pdma_perp_tx = NU_PDMA_UNUSED, +#endif +#if defined(BSP_USING_UART10_RX_DMA) + .pdma_perp_rx = PDMA_UART10_RX, + .rx_write_offset = 0, +#else + .pdma_perp_rx = NU_PDMA_UNUSED, +#endif +#endif + }, +#endif + +#if defined(BSP_USING_UART11) + { + .name = "uart11", + .uart_base = UART11, + .irqn = UART11_IRQn, + .rstidx = UART11_RST, + +#if defined(RT_SERIAL_USING_DMA) +#if defined(BSP_USING_UART11_TX_DMA) + .pdma_perp_tx = PDMA_UART11_TX, +#else + .pdma_perp_tx = NU_PDMA_UNUSED, +#endif +#if defined(BSP_USING_UART11_RX_DMA) + .pdma_perp_rx = PDMA_UART11_RX, + .rx_write_offset = 0, +#else + .pdma_perp_rx = NU_PDMA_UNUSED, +#endif +#endif + }, +#endif + +#if defined(BSP_USING_UART12) + { + .name = "uart12", + .uart_base = UART12, + .irqn = UART12_IRQn, + .rstidx = UART12_RST, + +#if defined(RT_SERIAL_USING_DMA) +#if defined(BSP_USING_UART12_TX_DMA) + .pdma_perp_tx = PDMA_UART12_TX, +#else + .pdma_perp_tx = NU_PDMA_UNUSED, +#endif +#if defined(BSP_USING_UART12_RX_DMA) + .pdma_perp_rx = PDMA_UART12_RX, + .rx_write_offset = 0, +#else + .pdma_perp_rx = NU_PDMA_UNUSED, +#endif +#endif + }, +#endif + +#if defined(BSP_USING_UART13) + { + .name = "uart13", + .uart_base = UART13, + .irqn = UART13_IRQn, + .rstidx = UART13_RST, + +#if defined(RT_SERIAL_USING_DMA) +#if defined(BSP_USING_UART13_TX_DMA) + .pdma_perp_tx = PDMA_UART13_TX, +#else + .pdma_perp_tx = NU_PDMA_UNUSED, +#endif +#if defined(BSP_USING_UART13_RX_DMA) + .pdma_perp_rx = PDMA_UART13_RX, + .rx_write_offset = 0, +#else + .pdma_perp_rx = NU_PDMA_UNUSED, +#endif +#endif + }, +#endif + +#if defined(BSP_USING_UART14) + { + .name = "uart14", + .uart_base = UART14, + .irqn = UART14_IRQn, + .rstidx = UART14_RST, + +#if defined(RT_SERIAL_USING_DMA) +#if defined(BSP_USING_UART14_TX_DMA) + .pdma_perp_tx = PDMA_UART14_TX, +#else + .pdma_perp_tx = NU_PDMA_UNUSED, +#endif +#if defined(BSP_USING_UART14_RX_DMA) + .pdma_perp_rx = PDMA_UART14_RX, + .rx_write_offset = 0, +#else + .pdma_perp_rx = NU_PDMA_UNUSED, +#endif +#endif + }, +#endif + +#if defined(BSP_USING_UART15) + { + .name = "uart15", + .uart_base = UART15, + .irqn = UART15_IRQn, + .rstidx = UART15_RST, + +#if defined(RT_SERIAL_USING_DMA) +#if defined(BSP_USING_UART15_TX_DMA) + .pdma_perp_tx = PDMA_UART15_TX, +#else + .pdma_perp_tx = NU_PDMA_UNUSED, +#endif +#if defined(BSP_USING_UART15_RX_DMA) + .pdma_perp_rx = PDMA_UART15_RX, + .rx_write_offset = 0, +#else + .pdma_perp_rx = NU_PDMA_UNUSED, +#endif +#endif + }, +#endif + +#if defined(BSP_USING_UART16) + { + .name = "uart16", + .uart_base = UART16, + .irqn = UART16_IRQn, + .rstidx = UART16_RST, + +#if defined(RT_SERIAL_USING_DMA) +#if defined(BSP_USING_UART16_TX_DMA) + .pdma_perp_tx = PDMA_UART16_TX, +#else + .pdma_perp_tx = NU_PDMA_UNUSED, +#endif +#if defined(BSP_USING_UART16_RX_DMA) + .pdma_perp_rx = PDMA_UART16_RX, + .rx_write_offset = 0, +#else + .pdma_perp_rx = NU_PDMA_UNUSED, +#endif +#endif + }, +#endif + +}; /* uart nu_uart */ + +/** + * All UART interrupt service routine + */ +static void nu_uart_isr(int vector, void *param) +{ + /* Get base address of uart register */ + nu_uart_t serial = (nu_uart_t)param; + UART_T *uart_base = serial->uart_base; + + /* Get interrupt event */ + uint32_t u32IntSts = uart_base->INTSTS; + uint32_t u32FIFOSts = uart_base->FIFOSTS; + +#if defined(RT_SERIAL_USING_DMA) + if (u32IntSts & UART_INTSTS_PRLSIF_Msk) + { + /* Drain RX FIFO to remove remain FEF frames in FIFO. */ + uart_base->FIFO |= UART_FIFO_RXRST_Msk; + uart_base->FIFOSTS |= (UART_FIFOSTS_BIF_Msk | UART_FIFOSTS_FEF_Msk | UART_FIFOSTS_PEF_Msk); + return; + } +#endif + + /* Handle RX event */ + if (u32IntSts & (UART_INTSTS_RDAINT_Msk | UART_INTSTS_RXTOINT_Msk)) + { + rt_hw_serial_isr(&serial->dev, RT_SERIAL_EVENT_RX_IND); + } + uart_base->INTSTS = u32IntSts; + uart_base->FIFOSTS = u32FIFOSts; +} + +/** + * Set RS-485 AUD mode + */ +void nu_uart_set_rs485aud(struct rt_serial_device *serial, rt_bool_t bRTSActiveLowLevel) +{ + UART_T *uart_base; + RT_ASSERT(serial); + + /* Get base address of uart register */ + uart_base = ((nu_uart_t)serial)->uart_base; + + /* Set RTS as RS-485 phy direction controlling ping. */ + UART_SelectRS485Mode(uart_base, UART_ALTCTL_RS485AUD_Msk, 0); + + if (bRTSActiveLowLevel) + { + /* Set direction pin as active-low. */ + uart_base->MODEM |= UART_MODEM_RTSACTLV_Msk; + } + else + { + /* Set direction pin as active-high. */ + uart_base->MODEM &= ~UART_MODEM_RTSACTLV_Msk; + } + + rt_kprintf("Set %s to RS-485 AUD function mode. ActiveLowLevel-%s\n", ((nu_uart_t)serial)->name, bRTSActiveLowLevel ? "YES" : "NO"); +} + +/** + * Configure uart port + */ +static rt_err_t nu_uart_configure(struct rt_serial_device *serial, struct serial_configure *cfg) +{ + rt_err_t ret = RT_EOK; + uint32_t uart_word_len = 0; + uint32_t uart_stop_bit = 0; + uint32_t uart_parity = 0; + + RT_ASSERT(serial); + RT_ASSERT(cfg); + + /* Check baudrate */ + RT_ASSERT(cfg->baud_rate != 0); + + /* Get base address of uart register */ + UART_T *uart_base = ((nu_uart_t)serial)->uart_base; + + /* Check word len */ + switch (cfg->data_bits) + { + case DATA_BITS_5: + uart_word_len = UART_WORD_LEN_5; + break; + + case DATA_BITS_6: + uart_word_len = UART_WORD_LEN_6; + break; + + case DATA_BITS_7: + uart_word_len = UART_WORD_LEN_7; + break; + + case DATA_BITS_8: + uart_word_len = UART_WORD_LEN_8; + break; + + default: + rt_kprintf("Unsupported data length\n"); + ret = RT_EINVAL; + goto exit_nu_uart_configure; + } + + /* Check stop bit */ + switch (cfg->stop_bits) + { + case STOP_BITS_1: + uart_stop_bit = UART_STOP_BIT_1; + break; + + case STOP_BITS_2: + uart_stop_bit = UART_STOP_BIT_2; + break; + + default: + rt_kprintf("Unsupported stop bit\n"); + ret = RT_EINVAL; + goto exit_nu_uart_configure; + } + + /* Check parity */ + switch (cfg->parity) + { + case PARITY_NONE: + uart_parity = UART_PARITY_NONE; + break; + + case PARITY_ODD: + uart_parity = UART_PARITY_ODD; + break; + + case PARITY_EVEN: + uart_parity = UART_PARITY_EVEN; + break; + + default: + rt_kprintf("Unsupported parity\n"); + ret = RT_EINVAL; + goto exit_nu_uart_configure; + } + + /* Reset this module */ + nu_sys_ip_reset(((nu_uart_t)serial)->rstidx); + + /* Open Uart and set UART Baudrate */ + UART_Open(uart_base, cfg->baud_rate); + + /* Set line configuration. */ + UART_SetLineConfig(uart_base, 0, uart_word_len, uart_parity, uart_stop_bit); + + /* Enable interrupt. */ + rt_hw_interrupt_umask(((nu_uart_t)serial)->irqn); + +exit_nu_uart_configure: + + if (ret != RT_EOK) + UART_Close(uart_base); + + return -(ret); +} + +#if defined(RT_SERIAL_USING_DMA) +static rt_err_t nu_pdma_uart_rx_config(struct rt_serial_device *serial, uint8_t *pu8Buf, int32_t i32TriggerLen) +{ + rt_err_t result = RT_EOK; + struct nu_pdma_chn_cb sChnCB; + nu_uart_t psNuUart = (nu_uart_t)serial; + + /* Get base address of uart register */ + UART_T *uart_base = psNuUart->uart_base; + + /* Register ISR callback function */ + sChnCB.m_eCBType = eCBType_Event; + sChnCB.m_pfnCBHandler = nu_pdma_uart_rx_cb; + sChnCB.m_pvUserData = (void *)serial; + + nu_pdma_filtering_set(psNuUart->pdma_chanid_rx, NU_PDMA_EVENT_TRANSFER_DONE | NU_PDMA_EVENT_TIMEOUT); + result = nu_pdma_callback_register(psNuUart->pdma_chanid_rx, &sChnCB); + + if (result != RT_EOK) + { + goto exit_nu_pdma_uart_rx_config; + } + + if (serial->config.bufsz == 0) + { + result = nu_pdma_transfer(((nu_uart_t)serial)->pdma_chanid_rx, + 8, + (uint32_t)uart_base, + (uint32_t)pu8Buf, + i32TriggerLen, + 1000); //Idle-timeout, 1ms + if (result != RT_EOK) + { + goto exit_nu_pdma_uart_rx_config; + } + } + else + { + /* For Serial RX FIFO - Single buffer recycle SG trigger */ + /* Link to next */ + nu_pdma_desc_t next = psNuUart->pdma_rx_desc; + + result = nu_pdma_desc_setup(psNuUart->pdma_chanid_rx, + psNuUart->pdma_rx_desc, + 8, + (uint32_t)uart_base, + (uint32_t)pu8Buf, + i32TriggerLen, + next, + 0); + if (result != RT_EOK) + { + goto exit_nu_pdma_uart_rx_config; + } + + /* Assign head descriptor & go */ + result = nu_pdma_sg_transfer(psNuUart->pdma_chanid_rx, psNuUart->pdma_rx_desc, 1000); + if (result != RT_EOK) + { + goto exit_nu_pdma_uart_rx_config; + } + } + + /* Enable Receive Line interrupt & Start DMA RX transfer. */ + UART_ENABLE_INT(uart_base, UART_INTEN_RLSIEN_Msk | UART_INTEN_RXPDMAEN_Msk); + +exit_nu_pdma_uart_rx_config: + + return result; +} + +static void nu_pdma_uart_rx_cb(void *pvOwner, uint32_t u32Events) +{ + rt_size_t recv_len = 0; + rt_size_t transferred_rxbyte = 0; + struct rt_serial_device *serial = (struct rt_serial_device *)pvOwner; + nu_uart_t puart = (nu_uart_t)serial; + RT_ASSERT(serial); + + /* Get base address of uart register */ + UART_T *uart_base = puart->uart_base; + + transferred_rxbyte = nu_pdma_transferred_byte_get(puart->pdma_chanid_rx, puart->rxdma_trigger_len); + if (u32Events & (NU_PDMA_EVENT_TRANSFER_DONE | NU_PDMA_EVENT_TIMEOUT)) + { + if (u32Events & NU_PDMA_EVENT_TRANSFER_DONE) + { + transferred_rxbyte = puart->rxdma_trigger_len; + } + else if ((u32Events & NU_PDMA_EVENT_TIMEOUT) && !UART_GET_RX_EMPTY(uart_base)) + { + return; + } + + recv_len = transferred_rxbyte - puart->rx_write_offset; + + if (recv_len > 0) + { +#if !defined(USE_MA35D1_SUBM) + struct rt_serial_rx_fifo *rx_fifo = (struct rt_serial_rx_fifo *)serial->serial_rx; + rt_hw_cpu_dcache_invalidate((void *)&rx_fifo->buffer[puart->rx_write_offset], recv_len); +#endif + puart->rx_write_offset = transferred_rxbyte % puart->rxdma_trigger_len; + } + } + + if ((serial->config.bufsz == 0) && (u32Events & NU_PDMA_EVENT_TRANSFER_DONE)) + { + recv_len = puart->rxdma_trigger_len; + } + + if (recv_len > 0) + { + rt_hw_serial_isr(&puart->dev, RT_SERIAL_EVENT_RX_DMADONE | (recv_len << 8)); + } +} + +static rt_err_t nu_pdma_uart_tx_config(struct rt_serial_device *serial) +{ + struct nu_pdma_chn_cb sChnCB; + RT_ASSERT(serial); + + /* Register ISR callback function */ + sChnCB.m_eCBType = eCBType_Event; + sChnCB.m_pfnCBHandler = nu_pdma_uart_tx_cb; + sChnCB.m_pvUserData = (void *)serial; + + nu_pdma_filtering_set(((nu_uart_t)serial)->pdma_chanid_tx, NU_PDMA_EVENT_TRANSFER_DONE); + return nu_pdma_callback_register(((nu_uart_t)serial)->pdma_chanid_tx, &sChnCB); +} + +static void nu_pdma_uart_tx_cb(void *pvOwner, uint32_t u32Events) +{ + nu_uart_t puart = (nu_uart_t)pvOwner; + + RT_ASSERT(puart); + + UART_DISABLE_INT(puart->uart_base, UART_INTEN_TXPDMAEN_Msk);// Stop DMA TX transfer + + if (u32Events & NU_PDMA_EVENT_TRANSFER_DONE) + { + rt_hw_serial_isr(&puart->dev, RT_SERIAL_EVENT_TX_DMADONE); + } +} + +/** + * Uart DMA transfer + */ +static rt_size_t nu_uart_dma_transmit(struct rt_serial_device *serial, rt_uint8_t *buf, rt_size_t size, int direction) +{ + rt_err_t result = RT_EOK; + nu_uart_t psNuUart = (nu_uart_t)serial; + + RT_ASSERT(serial); + RT_ASSERT(buf); + + /* Get base address of uart register */ + UART_T *uart_base = psNuUart->uart_base; + if (direction == RT_SERIAL_DMA_TX) + { + result = nu_pdma_transfer(psNuUart->pdma_chanid_tx, + 8, + (uint32_t)buf, + (uint32_t)uart_base, + size, + 0); // wait-forever + // Start DMA TX transfer + UART_ENABLE_INT(uart_base, UART_INTEN_TXPDMAEN_Msk); + } + else if (direction == RT_SERIAL_DMA_RX) + { + UART_DISABLE_INT(uart_base, UART_INTEN_RLSIEN_Msk | UART_INTEN_RXPDMAEN_Msk); + + // If config.bufsz = 0, serial will trigger once. + psNuUart->rxdma_trigger_len = size; + psNuUart->rx_write_offset = 0; + result = nu_pdma_uart_rx_config(serial, buf, size); + } + else + { + result = RT_ERROR; + } + + return result; +} + +static int nu_hw_uart_dma_allocate(nu_uart_t pusrt) +{ + RT_ASSERT(pusrt); + + /* Allocate UART_TX nu_dma channel */ + if (pusrt->pdma_perp_tx != NU_PDMA_UNUSED) + { + pusrt->pdma_chanid_tx = nu_pdma_channel_allocate(pusrt->pdma_perp_tx); + if (pusrt->pdma_chanid_tx >= 0) + { + pusrt->dma_flag |= RT_DEVICE_FLAG_DMA_TX; + } + } + + /* Allocate UART_RX nu_dma channel */ + if (pusrt->pdma_perp_rx != NU_PDMA_UNUSED) + { + pusrt->pdma_chanid_rx = nu_pdma_channel_allocate(pusrt->pdma_perp_rx); + if (pusrt->pdma_chanid_rx >= 0) + { + rt_err_t ret = RT_EOK; + pusrt->dma_flag |= RT_DEVICE_FLAG_DMA_RX; + ret = nu_pdma_sgtbls_allocate(&pusrt->pdma_rx_desc, 1); + RT_ASSERT(ret == RT_EOK); + } + } + + return RT_EOK; +} +#endif + +/** + * Uart interrupt control + */ +static rt_err_t nu_uart_control(struct rt_serial_device *serial, int cmd, void *arg) +{ + nu_uart_t psNuUart = (nu_uart_t)serial; + rt_err_t result = RT_EOK; + rt_ubase_t ctrl_arg = (rt_ubase_t)arg; + + RT_ASSERT(serial); + + /* Get base address of uart register */ + UART_T *uart_base = psNuUart->uart_base; + + switch (cmd) + { + case RT_DEVICE_CTRL_CLR_INT: + if (ctrl_arg == RT_DEVICE_FLAG_INT_RX) /* Disable INT-RX */ + { + UART_DISABLE_INT(uart_base, UART_INTEN_RDAIEN_Msk | UART_INTEN_RXTOIEN_Msk | UART_INTEN_TOCNTEN_Msk); + } + else if (ctrl_arg == RT_DEVICE_FLAG_DMA_RX) /* Disable DMA-RX */ + { + /* Disable Receive Line interrupt & Stop DMA RX transfer. */ +#if defined(RT_SERIAL_USING_DMA) + if (psNuUart->dma_flag & RT_DEVICE_FLAG_DMA_RX) + { + nu_pdma_channel_terminate(psNuUart->pdma_chanid_rx); + } + UART_DISABLE_INT(uart_base, UART_INTEN_RLSIEN_Msk | UART_INTEN_RXPDMAEN_Msk); +#endif + } + break; + + case RT_DEVICE_CTRL_SET_INT: + if (ctrl_arg == RT_DEVICE_FLAG_INT_RX) /* Enable INT-RX */ + { + UART_ENABLE_INT(uart_base, UART_INTEN_RDAIEN_Msk | UART_INTEN_RXTOIEN_Msk | UART_INTEN_TOCNTEN_Msk); + } + break; + +#if defined(RT_SERIAL_USING_DMA) + case RT_DEVICE_CTRL_CONFIG: + if (ctrl_arg == RT_DEVICE_FLAG_DMA_RX) /* Configure and trigger DMA-RX */ + { + struct rt_serial_rx_fifo *rx_fifo = (struct rt_serial_rx_fifo *)serial->serial_rx; + psNuUart->rxdma_trigger_len = serial->config.bufsz; + psNuUart->rx_write_offset = 0; + + result = nu_pdma_uart_rx_config(serial, &rx_fifo->buffer[0], psNuUart->rxdma_trigger_len); // Config & trigger + } + else if (ctrl_arg == RT_DEVICE_FLAG_DMA_TX) /* Configure DMA-TX */ + { + result = nu_pdma_uart_tx_config(serial); + } + break; +#endif + + case RT_DEVICE_CTRL_CLOSE: + /* Disable interrupt. */ + rt_hw_interrupt_mask(psNuUart->irqn); + +#if defined(RT_SERIAL_USING_DMA) + UART_DISABLE_INT(uart_base, UART_INTEN_RLSIEN_Msk | UART_INTEN_RXPDMAEN_Msk); + UART_DISABLE_INT(uart_base, UART_INTEN_TXPDMAEN_Msk); + + if (psNuUart->dma_flag != 0) + { + nu_pdma_channel_terminate(psNuUart->pdma_chanid_tx); + nu_pdma_channel_terminate(psNuUart->pdma_chanid_rx); + } +#endif + + /* Close UART port */ + UART_Close(uart_base); + + break; + + default: + result = -RT_EINVAL; + break; + + } + return result; +} + +/** + * Uart put char + */ +static int nu_uart_send(struct rt_serial_device *serial, char c) +{ + RT_ASSERT(serial); + + /* Get base address of uart register */ + UART_T *uart_base = ((nu_uart_t)serial)->uart_base; + + /* Waiting if TX-FIFO is full. */ + while (UART_IS_TX_FULL(uart_base)); + + /* Put char into TX-FIFO */ + UART_WRITE(uart_base, c); + + return 1; +} + +/** + * Uart get char + */ +static int nu_uart_receive(struct rt_serial_device *serial) +{ + RT_ASSERT(serial); + + /* Get base address of uart register */ + UART_T *uart_base = ((nu_uart_t)serial)->uart_base; + + /* Return failure if RX-FIFO is empty. */ + if (UART_GET_RX_EMPTY(uart_base)) + { + return -1; + } + + /* Get char from RX-FIFO */ + return UART_READ(uart_base); +} + +/** + * Hardware UART Initialization + */ +rt_err_t rt_hw_uart_init(void) +{ + int i; + rt_uint32_t flag; + rt_err_t ret = RT_EOK; + + for (i = (UART_START + 1); i < UART_CNT; i++) + { + flag = RT_DEVICE_FLAG_RDWR | RT_DEVICE_FLAG_INT_RX; + + nu_uart_arr[i].dev.ops = &nu_uart_ops; + nu_uart_arr[i].dev.config = nu_uart_default_config; + +#if defined(RT_SERIAL_USING_DMA) + nu_uart_arr[i].dma_flag = 0; + nu_hw_uart_dma_allocate(&nu_uart_arr[i]); + flag |= nu_uart_arr[i].dma_flag; +#endif + + rt_hw_interrupt_install(nu_uart_arr[i].irqn, nu_uart_isr, &nu_uart_arr[i], nu_uart_arr[i].name); + + ret = rt_hw_serial_register(&nu_uart_arr[i].dev, nu_uart_arr[i].name, flag, NULL); + RT_ASSERT(ret == RT_EOK); + } + + return ret; +} + +#endif //#if defined(BSP_USING_UART) diff --git a/bsp/nuvoton/libraries/ma35/rtt_port/drv_uart.h b/bsp/nuvoton/libraries/ma35/rtt_port/drv_uart.h new file mode 100644 index 0000000000..3dd14c0d8d --- /dev/null +++ b/bsp/nuvoton/libraries/ma35/rtt_port/drv_uart.h @@ -0,0 +1,22 @@ +/**************************************************************************//** +* +* @copyright (C) 2020 Nuvoton Technology Corp. All rights reserved. +* +* SPDX-License-Identifier: Apache-2.0 +* +* Change Logs: +* Date Author Notes +* 2020-2-7 Wayne First version +* +******************************************************************************/ + +#ifndef __DRV_UART_H__ +#define __DRV_UART_H__ + +#include +#include "board.h" + +rt_err_t rt_hw_uart_init(void); +void nu_uart_set_rs485aud(struct rt_serial_device *serial, rt_bool_t bRTSActiveLowLevel); + +#endif /* __DRV_UART_H__ */ diff --git a/bsp/nuvoton/libraries/ma35/rtt_port/drv_usbhost.c b/bsp/nuvoton/libraries/ma35/rtt_port/drv_usbhost.c new file mode 100644 index 0000000000..2707f1c4dc --- /dev/null +++ b/bsp/nuvoton/libraries/ma35/rtt_port/drv_usbhost.c @@ -0,0 +1,950 @@ +/**************************************************************************//** +* +* @copyright (C) 2020 Nuvoton Technology Corp. All rights reserved. +* +* SPDX-License-Identifier: Apache-2.0 +* +* Change Logs: +* Date Author Notes +* 2021-11-5 Wayne First version +* +******************************************************************************/ +#include + +#if defined(BSP_USING_USBH) + +#include +#include +#include "NuMicro.h" + +#include "usb.h" +#include "usbh_lib.h" + +#define LOG_TAG "drv.usbhost" +#define DBG_ENABLE +#define DBG_SECTION_NAME LOG_TAG +#define DBG_LEVEL LOG_LVL_DBG +#define DBG_COLOR +#include + +#if !defined(NU_USBHOST_HUB_POLLING_INTERVAL) + #define NU_USBHOST_HUB_POLLING_INTERVAL (100) +#endif + +#define NU_MAX_USBH_PORT (2+1) // 2* USB2.0 + 1*USB1.2 ports +#define NU_MAX_USBH_PIPE 16 +#define NU_USBH_THREAD_STACK_SIZE 2048 + +#define NU_MAX_USBH_HUB_PORT_DEV USB_HUB_PORT_NUM + +#define NU_USBHOST_HUB_POLLING_LOCK +#if defined(NU_USBHOST_HUB_POLLING_LOCK) +#define NU_USBHOST_MUTEX_INIT() { \ + s_sUSBHDev.lock = rt_mutex_create("usbhost_lock", RT_IPC_FLAG_PRIO); \ + RT_ASSERT(s_sUSBHDev.lock != RT_NULL); \ + } + +#define NU_USBHOST_LOCK() { \ + rt_err_t result = rt_mutex_take(s_sUSBHDev.lock, RT_WAITING_FOREVER); \ + RT_ASSERT(result == RT_EOK); \ + } + +#define NU_USBHOST_UNLOCK() { \ + rt_err_t result = rt_mutex_release(s_sUSBHDev.lock); \ + RT_ASSERT(result == RT_EOK); \ + } +#else +#define NU_USBHOST_MUTEX_INIT() +#define NU_USBHOST_LOCK() +#define NU_USBHOST_UNLOCK() +#endif + +/* Private typedef --------------------------------------------------------------*/ +typedef struct nu_port_dev +{ + rt_bool_t bRHParent; + UDEV_T *pUDev; + EP_INFO_T *apsEPInfo[NU_MAX_USBH_PIPE]; + struct urequest asSetupReq[NU_MAX_USBH_PIPE]; + uint32_t u32SentLength[NU_MAX_USBH_PIPE]; + struct rt_completion utr_completion; + int port_num; + rt_bool_t bEnumDone; + void *asPipePktBuf[NU_MAX_USBH_PIPE]; +} S_NU_PORT_DEV; + + +typedef struct nu_port_ctrl +{ + S_NU_PORT_DEV sRHPortDev; + S_NU_PORT_DEV asHubPortDev[NU_MAX_USBH_HUB_PORT_DEV]; +} S_NU_RH_PORT_CTRL; + + +struct nu_usbh_dev +{ + struct uhcd uhcd; + rt_thread_t polling_thread; + rt_mutex_t lock; + S_NU_RH_PORT_CTRL asPortCtrl[NU_MAX_USBH_PORT]; +}; + +/* Private variables ------------------------------------------------------------*/ +static struct nu_usbh_dev s_sUSBHDev; + +static S_NU_RH_PORT_CTRL * +GetRHPortControlFromPipe( + upipe_t pipe) +{ + uinst_t inst; + int port; + + if (!pipe || + !pipe->inst || + !pipe->inst->parent_hub) + return RT_NULL; + + if (pipe->inst->parent_hub->is_roothub) + { + //case: device ---> root hub + inst = pipe->inst; + port = inst->port; + } + else + { + //case: device ---> hub ---> root hub + inst = pipe->inst->parent_hub->self; + port = inst->port; + } + + if (port > NU_MAX_USBH_PORT) + { + RT_DEBUG_LOG(RT_DEBUG_USB, ("nu_open_pipe ERROR: port index over NU_MAX_USBH_PORT\n")); + return RT_NULL; + } + + return &s_sUSBHDev.asPortCtrl[port - 1];; +} + +static S_NU_PORT_DEV * +GetPortDevFromPipe( + upipe_t pipe) +{ + S_NU_RH_PORT_CTRL *psRHPortCtrl = GetRHPortControlFromPipe(pipe); + int i; + + if (psRHPortCtrl == RT_NULL) + return RT_NULL; + + if (pipe->inst->parent_hub->is_roothub) + { + //case: device ---> root hub + return &psRHPortCtrl->sRHPortDev; + } + + //case: device ---> hub ---> root hub + for (i = 0 ; i < NU_MAX_USBH_HUB_PORT_DEV; i ++) + { + if (psRHPortCtrl->asHubPortDev[i].port_num == pipe->inst->port) + break; + } + + if (i >= NU_MAX_USBH_HUB_PORT_DEV) + return RT_NULL; + + return &psRHPortCtrl->asHubPortDev[i]; +} + +static rt_err_t nu_reset_port(rt_uint8_t port) +{ + S_NU_RH_PORT_CTRL *psPortCtrl; + + if (port > NU_MAX_USBH_PORT) + { + RT_DEBUG_LOG(RT_DEBUG_USB, ("%s ERROR: port index over NU_MAX_USBH_PORT\n", __func__)); + return RT_EIO; + } + + psPortCtrl = &s_sUSBHDev.asPortCtrl[port - 1]; + if (psPortCtrl->sRHPortDev.pUDev == NULL) + { + RT_DEBUG_LOG(RT_DEBUG_USB, ("%s ERROR: udev not found\n", __func__)); + return RT_EIO; + } + + usbh_reset_port(psPortCtrl->sRHPortDev.pUDev); + + return RT_EOK; +} + +static EP_INFO_T *GetFreePipe( + S_NU_RH_PORT_CTRL *psPortCtrl, + S_NU_PORT_DEV *psPortDev, + rt_uint8_t *pu8PipeIndex) +{ + if (psPortCtrl != NULL) + { + int i; + /* Find free Pipe */ + for (i = 0; i < NU_MAX_USBH_PIPE; i ++) + { + if (psPortDev->apsEPInfo[i] == NULL) + break; + } + + if (i < NU_MAX_USBH_PIPE) + { + EP_INFO_T *psEPInfo = rt_malloc(sizeof(EP_INFO_T)); + if (psEPInfo != RT_NULL) + { + psPortDev->apsEPInfo[i] = psEPInfo; + *pu8PipeIndex = i; + return psEPInfo; + } + } + } + return RT_NULL; +} + +static void FreePipe( + S_NU_RH_PORT_CTRL *psPortCtrl, + S_NU_PORT_DEV *psPortDev, + rt_uint8_t u8PipeIndex) +{ + if ((psPortCtrl != RT_NULL) && + (u8PipeIndex < NU_MAX_USBH_PIPE) && + (psPortDev->apsEPInfo[u8PipeIndex] != RT_NULL)) + { + rt_free(psPortDev->apsEPInfo[u8PipeIndex]); + psPortDev->apsEPInfo[u8PipeIndex] = RT_NULL; + } +} + +static S_NU_PORT_DEV * +AllocateNewUDev( + S_NU_RH_PORT_CTRL *psRHPortCtrl) +{ + if (psRHPortCtrl != RT_NULL) + { + int i; + /* Find free Dev */ + for (i = 0 ; i < NU_MAX_USBH_HUB_PORT_DEV; i ++) + { + if (psRHPortCtrl->asHubPortDev[i].pUDev == NULL) + break; + } + + if (i < NU_MAX_USBH_HUB_PORT_DEV) + { + psRHPortCtrl->asHubPortDev[i].pUDev = alloc_device(); + if (psRHPortCtrl->asHubPortDev[i].pUDev == NULL) + { + return RT_NULL; + } + else + { + return &psRHPortCtrl->asHubPortDev[i]; + } + } + } + return RT_NULL; +} + +static rt_err_t nu_open_pipe(upipe_t pipe) +{ + S_NU_RH_PORT_CTRL *psPortCtrl; + S_NU_PORT_DEV *psPortDev; + + psPortCtrl = GetRHPortControlFromPipe(pipe); + if (psPortCtrl == RT_NULL) + { + RT_DEBUG_LOG(RT_DEBUG_USB, ("%s ERROR: RHPort not found\n", __func__)); + goto exit_nu_open_pipe; + } + + if (psPortCtrl->sRHPortDev.pUDev == NULL) + { + RT_DEBUG_LOG(RT_DEBUG_USB, ("%s ERROR: udev not found\n", __func__)); + goto exit_nu_open_pipe; + } + + psPortDev = GetPortDevFromPipe(pipe); + + if ((psPortDev == NULL) || (psPortDev->pUDev == NULL)) + { + //allocate new dev for hub device + psPortDev = AllocateNewUDev(psPortCtrl); + + if (psPortDev == RT_NULL) + { + RT_DEBUG_LOG(RT_DEBUG_USB, ("nu_open_pipe ERROR: udev allocate failed\n")); + goto exit_nu_open_pipe; + } + + if (pipe->inst->speed) + { + psPortDev->pUDev->speed = SPEED_FULL; + } + else + { + psPortDev->pUDev->speed = SPEED_HIGH; + } + + psPortDev->pUDev->parent = NULL; + psPortDev->pUDev->hc_driver = psPortCtrl->sRHPortDev.pUDev->hc_driver; + psPortDev->port_num = pipe->inst->port; + psPortDev->pUDev->port_num = pipe->inst->port; + psPortDev->bEnumDone = FALSE; + } + + //For ep0 control transfer + if ((pipe->ep.bEndpointAddress & 0x7F) == 0) + { + pipe->pipe_index = 0; + } + else + { + int pksz; + EP_INFO_T *psEPInfo = GetFreePipe(psPortCtrl, psPortDev, &pipe->pipe_index); + if (psEPInfo == RT_NULL) + { + RT_DEBUG_LOG(RT_DEBUG_USB, ("%s ERROR: get free pipe failed\n", __func__)); + goto exit_nu_open_pipe; + } + + psEPInfo->bEndpointAddress = pipe->ep.bEndpointAddress; + psEPInfo->bmAttributes = pipe->ep.bmAttributes; + + pksz = pipe->ep.wMaxPacketSize; + pksz = (pksz & 0x07ff) * (1 + ((pksz >> 11) & 3)); + psEPInfo->wMaxPacketSize = pksz; + + psEPInfo->bInterval = pipe->ep.bInterval; + psEPInfo->hw_pipe = NULL; + psEPInfo->bToggle = 0; + } + + if (!psPortDev->asPipePktBuf[pipe->pipe_index]) + { + psPortDev->asPipePktBuf[pipe->pipe_index] = rt_malloc_align(512ul, nu_cpu_dcache_line_size()); + RT_ASSERT(psPortDev->asPipePktBuf[pipe->pipe_index] != RT_NULL); + } + + return RT_EOK; + +exit_nu_open_pipe: + + return -RT_ERROR; +} + +static rt_err_t nu_close_pipe(upipe_t pipe) +{ + S_NU_RH_PORT_CTRL *psPortCtrl; + S_NU_PORT_DEV *psPortDev; + + psPortCtrl = GetRHPortControlFromPipe(pipe); + if (psPortCtrl == RT_NULL) + { + return RT_EIO; + } + + psPortDev = GetPortDevFromPipe(pipe); + + //For ep0 control transfer + if ((pipe->ep.bEndpointAddress & 0x7F) == 0) + { + if ((psPortDev) && (psPortDev->bRHParent == FALSE) && (psPortDev->bEnumDone == TRUE)) + { + if (psPortDev->pUDev) + { + int i; + for (i = 0; i < NU_MAX_USBH_PIPE; i++) + { + if (psPortDev->apsEPInfo[i] != NULL) + { + usbh_quit_xfer(psPortDev->pUDev, psPortDev->apsEPInfo[i]); + } + } + + free_device(psPortDev->pUDev); + psPortDev->pUDev = NULL; + } + } + } + + if (psPortDev != NULL) + { + if (psPortDev->asPipePktBuf[pipe->pipe_index]) + { + rt_free_align(psPortDev->asPipePktBuf[pipe->pipe_index]); + psPortDev->asPipePktBuf[pipe->pipe_index] = RT_NULL; + } + + FreePipe(psPortCtrl, psPortDev, pipe->pipe_index); + } + return RT_EOK; +} + +static int nu_ctrl_xfer( + S_NU_PORT_DEV *psPortDev, + struct urequest *psSetup, + void *buffer, + int timeouts) +{ + uint32_t xfer_len = 0; + int ret; + + ret = usbh_ctrl_xfer(psPortDev->pUDev, psSetup->request_type, psSetup->bRequest, psSetup->wValue, psSetup->wIndex, psSetup->wLength, buffer, &xfer_len, timeouts * 10); + if (ret < 0) + { + RT_DEBUG_LOG(RT_DEBUG_USB, ("nu_ctrl_xfer ERROR: xfer failed %d\n", ret)); + return ret; + } + + if (xfer_len != psSetup->wLength) + { + RT_DEBUG_LOG(RT_DEBUG_USB, ("nu_ctrl_xfer ERROR: xfer length %d %d\n", psSetup->wLength, xfer_len)); + } + + if ((psSetup->bRequest == USB_REQ_SET_ADDRESS) && ((psSetup->request_type & 0x60) == REQ_TYPE_STD_DEV)) + psPortDev->pUDev->dev_num = psSetup->wValue; + + if ((psSetup->bRequest == USB_REQ_SET_CONFIGURATION) && ((psSetup->request_type & 0x60) == REQ_TYPE_STD_DEV)) + { + psPortDev->pUDev->cur_conf = psSetup->wValue; + psPortDev->bEnumDone = TRUE; + } + + return xfer_len; +} + +static int nu_bulk_xfer( + S_NU_PORT_DEV *psPortDev, + UTR_T *psUTR, + int timeouts) +{ + int ret = usbh_bulk_xfer(psUTR); + if (ret < 0) + return ret; + + //wait transfer done + if (rt_completion_wait(&(psPortDev->utr_completion), timeouts) < 0) + { + rt_kprintf("Request Timeout in %d ms!! (bulk_xfer)\n", timeouts); + + rt_kprintf("psUTR->buff: %08x\n", psUTR->buff); + rt_kprintf("psUTR->data_len: %d\n", psUTR->data_len); + rt_kprintf("psUTR->xfer_len: %d\n", psUTR->xfer_len); + rt_kprintf("psUTR->ep: %08x\n", psUTR->ep); + rt_kprintf("psUTR->bIsTransferDone: %08x\n", psUTR->bIsTransferDone); + rt_kprintf("psUTR->status: %08x\n", psUTR->status); + rt_kprintf("psUTR->td_cnt: %08x\n", psUTR->td_cnt); + + return -1; + } + return 0; +} + +static int nu_int_xfer( + upipe_t pipe, + S_NU_PORT_DEV *psPortDev, + UTR_T *psUTR, + int timeouts) +{ + int ret; + + while (1) + { + ret = usbh_int_xfer(psUTR); + if (ret < 0) + return ret; + + if (rt_completion_wait(&(psPortDev->utr_completion), timeouts) != 0) + { + RT_DEBUG_LOG(RT_DEBUG_USB, ("Request %08x Timeout in %d ms!!\n", psUTR, timeouts)); + usbh_quit_utr(psUTR); + + rt_completion_init(&(psPortDev->utr_completion)); + rt_thread_mdelay(1); + } + else + { + + RT_DEBUG_LOG(RT_DEBUG_USB, ("Transferring done %08x\n", psUTR)); + usbh_quit_utr(psUTR); + break; + } + } + + return 0; +} + +static void xfer_done_cb(UTR_T *psUTR) +{ + S_NU_PORT_DEV *psPortDev = (S_NU_PORT_DEV *)psUTR->context; + + //transfer done, signal utr_completion + rt_completion_done(&(psPortDev->utr_completion)); +} + +static int nu_pipe_xfer(upipe_t pipe, rt_uint8_t token, void *buffer, int nbytes, int timeouts) +{ + S_NU_RH_PORT_CTRL *psPortCtrl; + S_NU_PORT_DEV *psPortDev; + UTR_T *psUTR = NULL; + int i32XferLen = -1; + + void *buffer_nonch = buffer; + + NU_USBHOST_LOCK(); + + psPortCtrl = GetRHPortControlFromPipe(pipe); + if (psPortCtrl == RT_NULL) + { + goto exit_nu_pipe_xfer; + } + + psPortDev = GetPortDevFromPipe(pipe); + if (psPortDev->pUDev == NULL) + { + RT_DEBUG_LOG(RT_DEBUG_USB, ("nu_pipe_xfer ERROR: udev not found\n")); + goto exit_nu_pipe_xfer; + } + + if (buffer_nonch && nbytes) + { + buffer_nonch = psPortDev->asPipePktBuf[pipe->pipe_index]; + if ((pipe->ep.bEndpointAddress & USB_DIR_MASK) == USB_DIR_OUT) + { + rt_memcpy(buffer_nonch, buffer, nbytes); + rt_hw_cpu_dcache_clean_inv((void *)buffer_nonch, nbytes); + } + } + + //ctrl xfer + if (pipe->ep.bmAttributes == USB_EP_ATTR_CONTROL) + { + int ret; + + if (token == USBH_PID_SETUP) + { + struct urequest *psSetup = (struct urequest *)buffer_nonch; + RT_ASSERT(buffer_nonch != RT_NULL); + psPortCtrl->asHubPortDev->u32SentLength[pipe->pipe_index] = 0; + + /* Read data from USB device. */ + if (psSetup->request_type & USB_REQ_TYPE_DIR_IN) + { + //Store setup request + rt_memcpy(&psPortCtrl->asHubPortDev->asSetupReq[pipe->pipe_index], psSetup, sizeof(struct urequest)); + } + else + { + /* Write data to USB device. */ + //Trigger USBHostLib Ctrl_Xfer + ret = nu_ctrl_xfer(psPortDev, psSetup, NULL, timeouts); + if (ret != psSetup->wLength) + goto exit_nu_pipe_xfer; + } + } + else + { + //token == USBH_PID_DATA + if (buffer_nonch && ((pipe->ep.bEndpointAddress & USB_DIR_MASK) == USB_DIR_IN)) + { + struct urequest *psSetup = &psPortCtrl->asHubPortDev->asSetupReq[pipe->pipe_index]; + + /* Read data from USB device. */ + //Trigger USBHostLib Ctril_Xfer + /* + * Workaround: HCD driver can readback all bytes of setup.wLength, but not support single packet transferring. + */ + if (psPortCtrl->asHubPortDev->u32SentLength[pipe->pipe_index] == 0) + { + ret = nu_ctrl_xfer(psPortDev, psSetup, buffer_nonch, timeouts); + psPortCtrl->asHubPortDev->u32SentLength[pipe->pipe_index] = ret; + if (ret > 0) + { + rt_hw_cpu_dcache_invalidate((void *)buffer_nonch, ret); + rt_memcpy(buffer, buffer_nonch, ret); + } + } + else + { + if (psPortCtrl->asHubPortDev->u32SentLength[pipe->pipe_index] < nbytes) + { + ret = 0; + } + else + { + psPortCtrl->asHubPortDev->u32SentLength[pipe->pipe_index] -= nbytes; + ret = nbytes; + } + } + if (ret <= 0) + goto exit_nu_pipe_xfer; + } + else + { + RT_DEBUG_LOG(RT_DEBUG_USB, ("%d == USBH_PID_DATA, nil buf-%d \n", token, nbytes)); + } + + } //else + i32XferLen = nbytes; + goto exit_nu_pipe_xfer2; + } // if ( pipe->ep.bmAttributes == USB_EP_ATTR_CONTROL ) + else + { + + psUTR = alloc_utr(psPortDev->pUDev); + + if (!psUTR) + { + RT_DEBUG_LOG(RT_DEBUG_USB, ("nu_pipe_xfer ERROR: unable alloc UTR\n")); + goto exit_nu_pipe_xfer; + } + + psUTR->ep = psPortDev->apsEPInfo[pipe->pipe_index]; + psUTR->buff = buffer_nonch; + psUTR->data_len = nbytes; + psUTR->xfer_len = 0; + psUTR->func = xfer_done_cb; + psUTR->context = psPortDev; + psUTR->bIsTransferDone = 0; + psUTR->status = 0; + + //others xfer + rt_completion_init(&(psPortDev->utr_completion)); + + if (pipe->ep.bmAttributes == USB_EP_ATTR_BULK) + { + if (nu_bulk_xfer(psPortDev, psUTR, timeouts) < 0) + { + RT_DEBUG_LOG(RT_DEBUG_USB, ("nu_pipe_xfer ERROR: bulk transfer failed\n")); + goto failreport_nu_pipe_xfer; + } + } + else if (pipe->ep.bmAttributes == USB_EP_ATTR_INT) + { + if (nu_int_xfer(pipe, psPortDev, psUTR, timeouts) < 0) + { + RT_DEBUG_LOG(RT_DEBUG_USB, ("nu_pipe_xfer ERROR: int transfer failed\n")); + //goto exit_nu_pipe_xfer; + } + else + { + i32XferLen = nbytes; + } + goto exit_nu_pipe_xfer; + } + else if (pipe->ep.bmAttributes == USB_EP_ATTR_ISOC) + { + //TODO: ISO transfer + RT_DEBUG_LOG(RT_DEBUG_USB, ("nu_pipe_xfer ERROR: isoc transfer not support\n")); + goto exit_nu_pipe_xfer; + } + + } //else + +failreport_nu_pipe_xfer: + + if (psUTR->bIsTransferDone == 0) + { + //Timeout + RT_DEBUG_LOG(RT_DEBUG_USB, ("nu_pipe_xfer ERROR: timeout\n")); + pipe->status = UPIPE_STATUS_ERROR; + usbh_quit_utr(psUTR); + } + else + { + // Transfer Done. Get status + if (psUTR->status == 0) + { + pipe->status = UPIPE_STATUS_OK; + } + else if (psUTR->status == USBH_ERR_STALL) + { + pipe->status = UPIPE_STATUS_STALL; + } + else + { + pipe->status = UPIPE_STATUS_ERROR; + } + } + + i32XferLen = psUTR->xfer_len; + +exit_nu_pipe_xfer: + + //Call callback + if (pipe->callback != RT_NULL) + { + pipe->callback(pipe); + } + + if (psUTR) + free_utr(psUTR); + + if ((nbytes) && + (buffer_nonch != buffer)) + { + if ((pipe->ep.bEndpointAddress & USB_DIR_MASK) == USB_DIR_IN) + { + rt_hw_cpu_dcache_invalidate((void *)buffer_nonch, nbytes); + rt_memcpy(buffer, buffer_nonch, nbytes); + } + } + +exit_nu_pipe_xfer2: + + NU_USBHOST_UNLOCK(); + + return i32XferLen; +} + +/* Polling USB root hub status task */ +static void nu_usbh_rh_thread_entry(void *parameter) +{ + while (1) + { + NU_USBHOST_LOCK(); + usbh_polling_root_hubs(); + NU_USBHOST_UNLOCK(); + + rt_thread_mdelay(NU_USBHOST_HUB_POLLING_INTERVAL); + } +} + +static void nu_hcd_connect_callback( + struct udev_t *udev, + int param) +{ + int i; + int port_index; + S_NU_RH_PORT_CTRL *psPortCtrl; + + for (i = 0; i < NU_MAX_USBH_PORT; i++) + { + psPortCtrl = &s_sUSBHDev.asPortCtrl[i]; + if (psPortCtrl->sRHPortDev.pUDev == NULL) + break; + } + + if (i >= NU_MAX_USBH_PORT) + { + RT_DEBUG_LOG(RT_DEBUG_USB, ("ERROR: port connect slot is full\n")); + return; + } + + port_index = i + 1; + psPortCtrl->sRHPortDev.pUDev = udev; + psPortCtrl->sRHPortDev.bRHParent = TRUE; + + RT_DEBUG_LOG(RT_DEBUG_USB, ("usb connected\n")); + + if (udev->speed == SPEED_HIGH) + rt_usbh_root_hub_connect_handler(&s_sUSBHDev.uhcd, port_index, RT_TRUE); + else + rt_usbh_root_hub_connect_handler(&s_sUSBHDev.uhcd, port_index, RT_FALSE); +} + +static void nu_hcd_disconnect_callback( + struct udev_t *udev, + int param) +{ + int i; + int port_index; + S_NU_RH_PORT_CTRL *psPortCtrl; + + for (i = 0; i < NU_MAX_USBH_PORT; i++) + { + psPortCtrl = &s_sUSBHDev.asPortCtrl[i]; + if (psPortCtrl->sRHPortDev.pUDev == udev) + break; + } + + if (i >= NU_MAX_USBH_PORT) + { + RT_DEBUG_LOG(RT_DEBUG_USB, ("ERROR: udev not found\n")); + return; + } + + port_index = i + 1; + + for (i = 0; i < NU_MAX_USBH_PIPE; i++) + { + if (psPortCtrl->sRHPortDev.apsEPInfo[i] != NULL) + { + usbh_quit_xfer(psPortCtrl->sRHPortDev.pUDev, psPortCtrl->sRHPortDev.apsEPInfo[i]); + } + } + + psPortCtrl->sRHPortDev.pUDev = NULL; + + RT_DEBUG_LOG(RT_DEBUG_USB, ("usb disconnect\n")); + + rt_usbh_root_hub_disconnect_handler(&s_sUSBHDev.uhcd, port_index); +} + + +/* USB host operations -----------------------------------------------------------*/ +static struct uhcd_ops nu_uhcd_ops = +{ + nu_reset_port, + nu_pipe_xfer, + nu_open_pipe, + nu_close_pipe, +}; + +static rt_err_t nu_hcd_init(rt_device_t device) +{ + struct nu_usbh_dev *pNuUSBHDev = (struct nu_usbh_dev *)device; + + usbh_core_init(); + + //install connect/disconnect callback + usbh_install_conn_callback(nu_hcd_connect_callback, nu_hcd_disconnect_callback); + + //create thread for polling usbh port status + /* create usb hub thread */ + pNuUSBHDev->polling_thread = rt_thread_create("usbh_drv", nu_usbh_rh_thread_entry, RT_NULL, + NU_USBH_THREAD_STACK_SIZE, 8, 20); + RT_ASSERT(pNuUSBHDev->polling_thread != RT_NULL); + + /* startup usb host thread */ + rt_thread_startup(pNuUSBHDev->polling_thread); + + return RT_EOK; +} + +/* global function for USB host library -----------------------------*/ +uint32_t usbh_get_ticks(void) +{ + return rt_tick_get(); +} + +void usbh_delay_ms(int msec) +{ + rt_thread_mdelay(msec); +} + +uint32_t usbh_tick_from_millisecond(uint32_t msec) +{ + return rt_tick_from_millisecond(msec); +} + +#if defined(RT_USING_PM) + +/* device pm suspend() entry. */ +static int usbhost_pm_suspend(const struct rt_device *device, rt_uint8_t mode) +{ + rt_err_t result; + + struct nu_usbh_dev *pNuUSBHDev = (struct nu_usbh_dev *)device; + + RT_ASSERT(pNuUSBHDev != RT_NULL); + switch (mode) + { + case PM_SLEEP_MODE_LIGHT: + case PM_SLEEP_MODE_DEEP: + + pNuUSBHDev->polling_thread->stat = RT_THREAD_READY; + result = rt_thread_suspend(pNuUSBHDev->polling_thread); + RT_ASSERT(result == RT_EOK); + + break; + + default: + break; + } + + return (int)RT_EOK; +} + +/* device pm resume() entry. */ +static void usbhost_pm_resume(const struct rt_device *device, rt_uint8_t mode) +{ + rt_err_t result; + struct nu_usbh_dev *pNuUSBHDev = (struct nu_usbh_dev *)device; + RT_ASSERT(pNuUSBHDev != RT_NULL); + + switch (mode) + { + case PM_SLEEP_MODE_LIGHT: + case PM_SLEEP_MODE_DEEP: + result = rt_thread_resume(pNuUSBHDev->polling_thread); + RT_ASSERT(result == RT_EOK); + break; + + default: + break; + } +} + +static struct rt_device_pm_ops device_pm_ops = +{ + .suspend = usbhost_pm_suspend, + .resume = usbhost_pm_resume, + .frequency_change = RT_NULL +}; +#endif + +int nu_usbh_register(void) +{ + rt_err_t res; + uhcd_t psUHCD; + + psUHCD = (uhcd_t)&s_sUSBHDev.uhcd; + + psUHCD->parent.type = RT_Device_Class_USBHost; + psUHCD->parent.init = nu_hcd_init; + psUHCD->parent.user_data = &s_sUSBHDev; + + psUHCD->ops = &nu_uhcd_ops; + psUHCD->num_ports = NU_MAX_USBH_PORT; + +#if defined(BSP_USING_HSUSBH0) + CLK_EnableModuleClock(HUSBH0_MODULE); + SYS_ResetModule(HSUSBH0_RST); +#endif + +#if defined(BSP_USING_HSUSBH1) + CLK_EnableModuleClock(HUSBH1_MODULE); + SYS_ResetModule(HSUSBH1_RST); +#endif + + /* set UHOVRCURH(SYS_MISCFCR0[12]) 1 => USBH Host over-current detect is high-active */ + /* 0 => USBH Host over-current detect is low-active */ + //SYS->MISCFCR0 |= SYS_MISCFCR0_UHOVRCURH_Msk; + SYS->MISCFCR0 &= ~SYS_MISCFCR0_UHOVRCURH_Msk; + +#if defined(BSP_USING_HSUSBH0) + /* Clock engine clock Configuration */ + SYS->USBPMISCR &= ~(SYS_USBPMISCR_PHY0POR_Msk | SYS_USBPMISCR_PHY0COMN_Msk); + SYS->USBPMISCR |= SYS_USBPMISCR_PHY0SUSPEND_Msk; +#endif + +#if defined(BSP_USING_HSUSBH1) + /* Clock engine clock Configuration */ + SYS->USBPMISCR &= ~(SYS_USBPMISCR_PHY1POR_Msk | SYS_USBPMISCR_PHY1COMN_Msk); + SYS->USBPMISCR |= SYS_USBPMISCR_PHY1SUSPEND_Msk; +#endif + + NU_USBHOST_MUTEX_INIT(); + + res = rt_device_register(&psUHCD->parent, "usbh", RT_DEVICE_FLAG_DEACTIVATE); + RT_ASSERT(res == RT_EOK); + + /*initialize the usb host function */ + res = rt_usb_host_init("usbh"); + RT_ASSERT(res == RT_EOK); + +#if defined(RT_USING_PM) + rt_pm_device_register(&psUHCD->parent, &device_pm_ops); +#endif + + return 0; +} +INIT_APP_EXPORT(nu_usbh_register); + +#endif diff --git a/bsp/nuvoton/libraries/ma35/rtt_port/drv_wdt.c b/bsp/nuvoton/libraries/ma35/rtt_port/drv_wdt.c new file mode 100644 index 0000000000..cbacf45e9c --- /dev/null +++ b/bsp/nuvoton/libraries/ma35/rtt_port/drv_wdt.c @@ -0,0 +1,372 @@ +/**************************************************************************//** +* +* @copyright (C) 2020 Nuvoton Technology Corp. All rights reserved. +* +* SPDX-License-Identifier: Apache-2.0 +* +* Change Logs: +* Date Author Notes +* 2020-3-25 Wayne First version +* +******************************************************************************/ + +#include + +#if defined(BSP_USING_WDT) + +#include +#include +#include "NuMicro.h" + +#define LOG_TAG "drv.wdt" +#define DBG_SECTION_NAME LOG_TAG +#define DBG_LEVEL LOG_LVL_ERROR +#define DBG_COLOR +#include + +/* Private define ---------------------------------------------------------------*/ +enum +{ + WDT_START = -1, +#if defined(BSP_USING_WDT0) + WDT0_IDX, +#endif +#if defined(BSP_USING_WDT1) + WDT1_IDX, +#endif +#if defined(BSP_USING_WDT2) + WDT2_IDX, +#endif + WDT_CNT +}; + +/* Pick a suitable wdt timeout interval, it is a trade-off between the + consideration of timeout accuracy and the system performance. The MIN_CYCLES + parameter is a numerical value of the toutsel setting, and it must be set to + a correct one which matches to the literal meaning of MIN_TOUTSEL. */ +#define MIN_TOUTSEL (WDT_TIMEOUT_2POW10) +#define MIN_CYCLES (1024) + + +/* Macros to convert the value between the timeout interval and the soft time iterations. */ +#define ROUND_TO_INTEGER(value) ((int)(((value) * 10 + 5) / 10)) +#define CONV_SEC_TO_IT(hz, secs) (ROUND_TO_INTEGER((float)((secs) * (hz)) / (float)(MIN_CYCLES))) +#define CONV_IT_TO_SEC(hz, iterations) (ROUND_TO_INTEGER((float)((iterations) * (MIN_CYCLES)) / (float)(hz))) + + +/* Private typedef --------------------------------------------------------------*/ +struct soft_time_handle +{ + int clock_hz; + int wanted_sec; + int report_sec; + int left_iterations; + int full_iterations; + rt_bool_t expired; + rt_bool_t feed_dog; +}; +typedef volatile struct soft_time_handle soft_time_handle_t; + +struct nu_wdt +{ + struct rt_watchdog_device parent; + char *name; + WDT_T *base; + IRQn_Type irqn; + uint32_t modid; + struct soft_time_handle soft_time; +}; +typedef struct nu_wdt *nu_wdt_t; + +/* Private functions ------------------------------------------------------------*/ +static rt_err_t nu_wdt_init(rt_watchdog_t *dev); +static rt_err_t nu_wdt_control(rt_watchdog_t *dev, int cmd, void *args); +static uint32_t nu_wdt_get_module_clock(nu_wdt_t); +static uint32_t nu_wdt_get_working_hz(nu_wdt_t); +static void soft_time_init(soft_time_handle_t *const soft_time); +static void soft_time_setup(uint32_t wanted_sec, uint32_t hz, soft_time_handle_t *const soft_time); +static void soft_time_feed_dog(soft_time_handle_t *const soft_time); +static void nu_wdt_isr(int vector, void *param); +/* Public functions -------------------------------------------------------------*/ + +/* Private variables ------------------------------------------------------------*/ +static struct nu_wdt nu_wdt_arr [] = +{ +#if defined(BSP_USING_WDT0) + { .name = "wdt0", .base = WDT0, .irqn = WDT0_IRQn, .modid = WDT0_MODULE }, +#endif +#if defined(BSP_USING_WDT1) + { .name = "wdt1", .base = WDT1, .irqn = WDT1_IRQn, .modid = WDT1_MODULE }, +#endif +#if defined(BSP_USING_WDT2) + { .name = "wdt2", .base = WDT2, .irqn = WDT2_IRQn, .modid = WDT2_MODULE }, +#endif +}; + +static struct rt_watchdog_ops ops_wdt = +{ + .init = nu_wdt_init, + .control = nu_wdt_control, +}; + + +/* wdt device driver initialize. */ +int rt_hw_wdt_init(void) +{ + int i; + rt_err_t ret = RT_EOK; + + for (i = (WDT_START + 1); i < WDT_CNT; i++) + { + nu_wdt_t psNuWdt = &nu_wdt_arr[i]; + + if (WDT_GET_RESET_FLAG(psNuWdt->base)) + { + LOG_W("%s: System re-boots from watchdog timer reset.\n", psNuWdt->name); + WDT_CLEAR_RESET_FLAG(psNuWdt->base); + } + + psNuWdt->parent.ops = &ops_wdt; + ret = rt_hw_watchdog_register(&psNuWdt->parent, psNuWdt->name, RT_DEVICE_FLAG_RDWR, psNuWdt); + RT_ASSERT(ret == RT_EOK); + + rt_hw_interrupt_install(psNuWdt->irqn, nu_wdt_isr, psNuWdt, psNuWdt->name); + rt_hw_interrupt_umask(psNuWdt->irqn); + } + + return (int)ret; +} +INIT_BOARD_EXPORT(rt_hw_wdt_init); + + +/* Register rt-thread device.init() entry. */ +static rt_err_t nu_wdt_init(rt_watchdog_t *dev) +{ + nu_wdt_t psNuWdt = (nu_wdt_t)dev; + RT_ASSERT(dev != RT_NULL); + + soft_time_init(&psNuWdt->soft_time); + + return RT_EOK; +} + + +static uint32_t nu_wdt_get_module_clock(nu_wdt_t psNuWdt) +{ + uint32_t ret = 0; + switch (psNuWdt->modid) + { + case WDT0_MODULE: + case WDT1_MODULE: + case WDT2_MODULE: + ret = CLK_GetModuleClockSource(psNuWdt->modid); + break; + + default: + break; + } + + return ret; +} + + +static uint32_t nu_wdt_get_working_hz(nu_wdt_t psNuWdt) +{ + uint32_t src_clk, hz = 0; + + src_clk = nu_wdt_get_module_clock(psNuWdt); + + switch (src_clk) + { + case 1: /* CLK_CLKSEL3_WDT0SEL_LXT */ + hz = __LXT; + break; + + case 2: /* CLK_CLKSEL3_WDT0SEL_PCLK3_DIV4096 */ + hz = CLK_GetPCLK3Freq() / 4096; + break; + + case 3: /* CLK_CLKSEL3_WDT0SEL_LIRC */ + hz = __LIRC; + break; + + default: + break; + } + + LOG_D("[%s] modid=%x src_clk=%d src_hz=%d\n", psNuWdt->name, psNuWdt->modid, src_clk, hz); + + return hz; +} + + +static void soft_time_init(soft_time_handle_t *const soft_time) +{ + rt_memset((void *)soft_time, 0, sizeof(struct soft_time_handle)); + +} + + +static void soft_time_setup(uint32_t wanted_sec, uint32_t hz, soft_time_handle_t *const soft_time) +{ + rt_base_t level; + + level = rt_hw_interrupt_disable(); + + soft_time->expired = RT_FALSE; + soft_time->feed_dog = RT_FALSE; + soft_time->wanted_sec = wanted_sec; + soft_time->full_iterations = CONV_SEC_TO_IT(hz, wanted_sec); + soft_time->left_iterations = soft_time->full_iterations; + soft_time->report_sec = CONV_IT_TO_SEC(hz, soft_time->full_iterations); + soft_time->clock_hz = hz; + + rt_hw_interrupt_enable(level); + + LOG_D("wanted_sec=%d\n", soft_time->wanted_sec); + LOG_D("full_iterations=%d\n", soft_time->full_iterations); + LOG_D("left_iterations=%d\n", soft_time->left_iterations); + LOG_D("report_sec=%d\n", soft_time->report_sec); + LOG_D("clock_hz=%d\n", soft_time->clock_hz); + +} + + +static void soft_time_feed_dog(soft_time_handle_t *const soft_time) +{ + soft_time->feed_dog = RT_TRUE; +} + + +/* Register rt-thread device.control() entry. */ +static rt_err_t nu_wdt_control(rt_watchdog_t *dev, int cmd, void *args) +{ + uint32_t wanted_sec, hz; + rt_err_t ret = RT_EOK; + + nu_wdt_t psNuWdt = (nu_wdt_t)dev; + RT_ASSERT(dev); + + //SYS_UnlockReg(); + + hz = nu_wdt_get_working_hz(psNuWdt); + + switch (cmd) + { + case RT_DEVICE_CTRL_WDT_GET_TIMEOUT: + + if (args == RT_NULL) + { + ret = RT_EINVAL; + break; + } + + *((uint32_t *)args) = psNuWdt->soft_time.report_sec; + LOG_D("[GET]report_sec=%d\n", psNuWdt->soft_time.report_sec); + break; + + case RT_DEVICE_CTRL_WDT_SET_TIMEOUT: + + if (args == RT_NULL) + { + ret = RT_EINVAL; + break; + } + + wanted_sec = *((uint32_t *)args); + + if (wanted_sec == 0) + { + ret = RT_EINVAL; + break; + } + + soft_time_setup(wanted_sec, hz, &psNuWdt->soft_time); + LOG_D("[SET]report_sec=%d\n", psNuWdt->soft_time.report_sec); + break; + + case RT_DEVICE_CTRL_WDT_GET_TIMELEFT: + + if (args == RT_NULL) + { + ret = RT_EINVAL; + break; + } + + *((uint32_t *)args) = CONV_IT_TO_SEC(hz, psNuWdt->soft_time.left_iterations); + break; + + case RT_DEVICE_CTRL_WDT_KEEPALIVE: + + /* Make a mark that the application has fed the watchdog. */ + soft_time_feed_dog(&psNuWdt->soft_time); + break; + + case RT_DEVICE_CTRL_WDT_START: + + WDT_RESET_COUNTER(psNuWdt->base); + WDT_Open(psNuWdt->base, MIN_TOUTSEL, WDT_RESET_DELAY_1026CLK, TRUE, TRUE); + WDT_EnableInt(psNuWdt->base); + break; + + case RT_DEVICE_CTRL_WDT_STOP: + + WDT_Close(psNuWdt->base); + break; + + default: + ret = RT_ERROR; + } + + //SYS_LockReg(); + + return -(ret); +} + + +/* wdt interrupt entry */ +static void nu_wdt_isr(int vector, void *param) +{ + nu_wdt_t psNuWdt = (nu_wdt_t)param; + RT_ASSERT(param != RT_NULL); + + /* Clear wdt interrupt flag */ + if (WDT_GET_TIMEOUT_INT_FLAG(psNuWdt->base)) + { + WDT_CLEAR_TIMEOUT_INT_FLAG(psNuWdt->base); + } + + /* Clear wdt wakeup flag */ + if (WDT_GET_TIMEOUT_WAKEUP_FLAG(psNuWdt->base)) + { + WDT_CLEAR_TIMEOUT_WAKEUP_FLAG(psNuWdt->base); + } + + /* The soft time has not reached the configured timeout yet. Clear the wdt counter + any way to prevent the system from hardware wdt reset. */ + if (psNuWdt->soft_time.left_iterations-- > 0) + { + WDT_RESET_COUNTER(psNuWdt->base); + } + + /* The soft time reaches the configured timeout boundary. Clear the wdt + counter if he application has fed the dog at least once until now. */ + else + { + if ((psNuWdt->soft_time.feed_dog) && (!psNuWdt->soft_time.expired)) + { + WDT_RESET_COUNTER(psNuWdt->base); + psNuWdt->soft_time.feed_dog = RT_FALSE; + psNuWdt->soft_time.left_iterations = psNuWdt->soft_time.full_iterations; + } + else + { + /* Application does not feed the dog in time. */ + psNuWdt->soft_time.expired = RT_TRUE; + } + } +} + +#endif /* BSP_USING_WDT */ + + diff --git a/bsp/nuvoton/libraries/ma35/rtt_port/gmac/SConscript b/bsp/nuvoton/libraries/ma35/rtt_port/gmac/SConscript new file mode 100644 index 0000000000..21d7483ac6 --- /dev/null +++ b/bsp/nuvoton/libraries/ma35/rtt_port/gmac/SConscript @@ -0,0 +1,13 @@ +Import('RTT_ROOT') +from building import * + +cwd = GetCurrentDir() +src = Glob('*.c') +group = [] + +CPPPATH = [cwd] + +if GetDepend('BSP_USING_GMAC'): + group = DefineGroup('Drivers', src, depend = [''], CPPPATH = CPPPATH) + +Return('group') diff --git a/bsp/nuvoton/libraries/ma35/rtt_port/gmac/drv_gmac.c b/bsp/nuvoton/libraries/ma35/rtt_port/gmac/drv_gmac.c new file mode 100644 index 0000000000..9a7ee9ed8a --- /dev/null +++ b/bsp/nuvoton/libraries/ma35/rtt_port/gmac/drv_gmac.c @@ -0,0 +1,801 @@ +/**************************************************************************//** +* +* @copyright (C) 2020 Nuvoton Technology Corp. All rights reserved. +* +* SPDX-License-Identifier: Apache-2.0 +* +* Change Logs: +* Date Author Notes +* 2021-07-23 Wayne First version +* +******************************************************************************/ + +#include "rtconfig.h" + +#if defined(BSP_USING_GMAC) + +#include "drv_common.h" +#include "drv_sys.h" +#include +#include +#include +#include +#include +#include +#include "lwipopts.h" + +#include "synopGMAC_Host.h" + +#define DBG_ENABLE +//#undef DBG_ENABLE +#define DBG_LEVEL LOG_LVL_INFO +#define DBG_SECTION_NAME "drv_gmac" +#define DBG_COLOR +#include + +/* Private define ---------------------------------------------------------------*/ + +//#define NU_GMAC_DEBUG +#if defined(NU_GMAC_DEBUG) + //#define NU_GMAC_RX_DUMP + //#define NU_GMAC_TX_DUMP + #define NU_GMAC_TRACE rt_kprintf +#else + #define NU_GMAC_TRACE(...) +#endif + +enum +{ + GMAC_START = -1, +#if defined(BSP_USING_GMAC0) + GMAC0_IDX, +#endif +#if defined(BSP_USING_GMAC1) + GMAC1_IDX, +#endif + GMAC_CNT +}; + +#define invalidate_cpu_cache(addr, len) rt_hw_cpu_dcache_invalidate(addr, len) + +/* Private typedef --------------------------------------------------------------*/ + +struct nu_gmac_lwip_pbuf +{ + struct pbuf_custom p; // lwip pbuf + PKT_FRAME_T *psPktFrameDataBuf; // gmac descriptor + synopGMACdevice *gmacdev; + const struct memp_desc *pool; +}; + +typedef struct nu_gmac_lwip_pbuf *nu_gmac_lwip_pbuf_t; + +struct nu_gmac +{ + struct eth_device eth; + char *name; + GMAC_T *base; + IRQn_Type irqn; + rt_timer_t link_timer; + rt_uint8_t mac_addr[8]; + synopGMACNetworkAdapter *adapter; + const struct memp_desc *memp_rx_pool; +}; +typedef struct nu_gmac *nu_gmac_t; + +/* Private variables ------------------------------------------------------------*/ +#if defined(BSP_USING_GMAC0) + LWIP_MEMPOOL_DECLARE(gmac0_rx, RECEIVE_DESC_SIZE, sizeof(struct nu_gmac_lwip_pbuf), "GMAC0 RX PBUF pool"); +#endif + +#if defined(BSP_USING_GMAC1) + LWIP_MEMPOOL_DECLARE(gmac1_rx, RECEIVE_DESC_SIZE, sizeof(struct nu_gmac_lwip_pbuf), "GMAC1 RX PBUF pool"); +#endif + +static struct nu_gmac nu_gmac_arr[] = +{ +#if defined(BSP_USING_GMAC0) + { + .name = "e0", + .base = GMAC0, + .irqn = GMAC0RX_IRQn, + .memp_rx_pool = &memp_gmac0_rx + }, +#endif +#if defined(BSP_USING_GMAC1) + { + .name = "e1", + .base = GMAC1, + .irqn = GMAC1RX_IRQn, + .memp_rx_pool = &memp_gmac1_rx + }, +#endif +}; + +void nu_gmac_pkt_dump(const char *msg, const struct pbuf *p) +{ + rt_uint32_t i; + rt_uint8_t *ptr = p->payload; + + NU_GMAC_TRACE("%s %d byte\n", msg, p->tot_len); + + for (i = 0; i < p->tot_len; i++) + { + if ((i % 8) == 0) + { + NU_GMAC_TRACE(" "); + } + if ((i % 16) == 0) + { + NU_GMAC_TRACE("\r\n"); + } + NU_GMAC_TRACE("%02x ", *ptr); + ptr++; + } + NU_GMAC_TRACE("\n\n"); +} + +static int nu_gmac_mdio_read(void *adapter, int addr, int reg) +{ + synopGMACdevice *gmacdev = ((synopGMACNetworkAdapter *)adapter)->m_gmacdev; + u16 data; + synopGMAC_read_phy_reg(gmacdev->MacBase, addr, reg, &data); + return data; +} + +static void nu_gmac_mdio_write(void *adapter, int addr, int reg, int data) +{ + synopGMACdevice *gmacdev = ((synopGMACNetworkAdapter *)adapter)->m_gmacdev; + synopGMAC_write_phy_reg(gmacdev->MacBase, addr, reg, data); +} + +s32 synopGMAC_check_phy_init(synopGMACNetworkAdapter *adapter) +{ + struct ethtool_cmd cmd; + synopGMACdevice *gmacdev = adapter->m_gmacdev; + + if (!mii_link_ok(&adapter->m_mii)) + { + gmacdev->DuplexMode = FULLDUPLEX; + gmacdev->Speed = SPEED100; + return 0; + } + else + { + mii_ethtool_gset(&adapter->m_mii, &cmd); + gmacdev->DuplexMode = (cmd.duplex == DUPLEX_FULL) ? FULLDUPLEX : HALFDUPLEX ; + if (cmd.speed == SPEED_1000) + gmacdev->Speed = SPEED1000; + else if (cmd.speed == SPEED_100) + gmacdev->Speed = SPEED100; + else + gmacdev->Speed = SPEED10; + } + + return gmacdev->Speed | (gmacdev->DuplexMode << 4); +} + +static void nu_gmac_isr(int irqno, void *param) +{ + nu_gmac_t psNuGMAC = (nu_gmac_t)param; + + synopGMACNetworkAdapter *adapter = psNuGMAC->adapter; + synopGMACdevice *gmacdev = (synopGMACdevice *)adapter->m_gmacdev; + + u32 interrupt, dma_status_reg; + s32 status; + u32 u32GmacIntSts; + u32 u32GmacDmaIE = DmaIntEnable; + + // Check GMAC interrupt + u32GmacIntSts = synopGMACReadReg(gmacdev->MacBase, GmacInterruptStatus); + if (u32GmacIntSts & GmacTSIntSts) + { + gmacdev->synopGMACNetStats.ts_int = 1; + status = synopGMACReadReg(gmacdev->MacBase, GmacTSStatus); + if (!(status & (1 << 1))) + LOG_I("TS alarm flag not set??"); + else + LOG_I("TS alarm!\n"); + } + + synopGMACWriteReg(gmacdev->MacBase, GmacInterruptStatus, u32GmacIntSts); + + dma_status_reg = synopGMACReadReg(gmacdev->DmaBase, DmaStatus); + if (dma_status_reg == 0) + { + //LOG_I("dma_status ==0 \n"); + return; + } + + if (dma_status_reg & GmacPmtIntr) + { + //LOG_D("%s:: Interrupt due to PMT module\n", psNuGMAC->name); + synopGMAC_powerup_mac(gmacdev); + } + + if (dma_status_reg & GmacLineIntfIntr) + { + LOG_I("%s: GMAC status reg is %08x mask is %08x\n", + psNuGMAC->name, + synopGMACReadReg(gmacdev->MacBase, GmacInterruptStatus), + synopGMACReadReg(gmacdev->MacBase, GmacInterruptMask)); + + if (synopGMACReadReg(gmacdev->MacBase, GmacInterruptStatus) & GmacRgmiiIntSts) + { + LOG_D("%s: GMAC RGMII status is %08x\n", + psNuGMAC->name, + synopGMACReadReg(gmacdev->MacBase, GmacRgmiiCtrlSts)); + synopGMACReadReg(gmacdev->MacBase, GmacRgmiiCtrlSts); + } + } + + /* DMA status */ + interrupt = synopGMAC_get_interrupt_type(gmacdev); + LOG_D("%s: 0x%08x@%08x\n", psNuGMAC->name, interrupt, DmaStatus); + + if (interrupt & synopGMACDmaError) + { + LOG_E("%s::Fatal Bus Error Inetrrupt Seen\n", psNuGMAC->name); + synopGMAC_disable_dma_tx(gmacdev); + synopGMAC_disable_dma_rx(gmacdev); + + synopGMAC_take_desc_ownership_tx(gmacdev); + synopGMAC_take_desc_ownership_rx(gmacdev); + + synopGMAC_init_tx_rx_desc_queue(gmacdev); + + synopGMAC_reset(gmacdev); + + synopGMAC_set_mac_addr(gmacdev, GmacAddr0High, GmacAddr0Low, &psNuGMAC->mac_addr[0]); + synopGMAC_dma_bus_mode_init(gmacdev, DmaBurstLength32 | DmaDescriptorSkip0/*DmaDescriptorSkip2*/ | DmaDescriptor8Words); + synopGMAC_dma_control_init(gmacdev, DmaStoreAndForward | DmaTxSecondFrame | DmaRxThreshCtrl128); + synopGMAC_init_rx_desc_base(gmacdev); + synopGMAC_init_tx_desc_base(gmacdev); + synopGMAC_mac_init(gmacdev); + synopGMAC_enable_dma_rx(gmacdev); + synopGMAC_enable_dma_tx(gmacdev); + + } + + if ((interrupt & synopGMACDmaRxNormal) || + (interrupt & synopGMACDmaRxAbnormal)) + { + if (interrupt & synopGMACDmaRxNormal) + { + LOG_D("%s:: Rx Normal \n", psNuGMAC->name); + u32GmacDmaIE &= ~DmaIntRxNormMask; + + } + if (interrupt & synopGMACDmaRxAbnormal) + { + LOG_E("%s::Abnormal Rx Interrupt Seen %08x\n", psNuGMAC->name, dma_status_reg); + + if (gmacdev->GMAC_Power_down == 0) + { + gmacdev->synopGMACNetStats.rx_over_errors++; + u32GmacDmaIE &= ~DmaIntRxAbnMask; + //synopGMAC_resume_dma_rx(gmacdev); + } + } + eth_device_ready(&psNuGMAC->eth); + } + + if (interrupt & synopGMACDmaRxStopped) + { + LOG_E("%s::Receiver stopped seeing Rx interrupts\n", psNuGMAC->name); //Receiver gone in to stopped state + if (gmacdev->GMAC_Power_down == 0) // If Mac is not in powerdown + { + gmacdev->synopGMACNetStats.rx_over_errors++; + synopGMAC_enable_dma_rx(gmacdev); + } + } + + if (interrupt & synopGMACDmaTxNormal) + { + LOG_D("%s::Finished Normal Transmission \n", psNuGMAC->name); + synop_handle_transmit_over(gmacdev);//Do whatever you want after the transmission is over + } + + if (interrupt & synopGMACDmaTxAbnormal) + { + LOG_E("%s::Abnormal Tx Interrupt Seen\n", psNuGMAC->name); + if (gmacdev->GMAC_Power_down == 0) // If Mac is not in powerdown + { + synop_handle_transmit_over(gmacdev); + } + } + + if (interrupt & synopGMACDmaTxStopped) + { + LOG_E("%s::Transmitter stopped sending the packets\n", psNuGMAC->name); + if (gmacdev->GMAC_Power_down == 0) // If Mac is not in powerdown + { + synopGMAC_disable_dma_tx(gmacdev); + synopGMAC_take_desc_ownership_tx(gmacdev); + synopGMAC_enable_dma_tx(gmacdev); + LOG_I("%s::Transmission Resumed\n", psNuGMAC->name); + } + } + + /* Enable the interrupt before returning from ISR*/ + synopGMAC_enable_interrupt(gmacdev, u32GmacDmaIE); +} + +void nu_gmac_link_monitor(void *pvData) +{ + nu_gmac_t psNuGMAC = (nu_gmac_t)pvData; + + synopGMACNetworkAdapter *adapter = psNuGMAC->adapter; + synopGMACdevice *gmacdev = adapter->m_gmacdev; + if (!mii_link_ok(&adapter->m_mii)) + { + if (gmacdev->LinkState) + { + eth_device_linkchange(&psNuGMAC->eth, RT_FALSE); + LOG_I("%s: No Link", psNuGMAC->name); + } + gmacdev->DuplexMode = 0; + gmacdev->Speed = 0; + gmacdev->LoopBackMode = 0; + gmacdev->LinkState = 0; + } + else + { + s32 data, speed; + data = synopGMAC_check_phy_init(adapter); + if (gmacdev->LinkState != data) + { + speed = data & 0x0f; + gmacdev->LinkState = data; + synopGMAC_mac_init(gmacdev); + synopGMAC_set_mode(gmacdev, speed); + eth_device_linkchange(&psNuGMAC->eth, RT_TRUE); + LOG_I("%s: Link is up in %s %s mode", psNuGMAC->name, \ + (speed == SPEED1000) ? "1000M" : (speed == SPEED100) ? "100M" : (speed == SPEED10) ? "10M" : "", + (gmacdev->DuplexMode == FULLDUPLEX) ? "FULL DUPLEX" : "HALF DUPLEX"); + } + } + NU_GMAC_TRACE("%s: Interrupt enable: %08x, status:%08x\n", psNuGMAC->name, synopGMAC_get_ie(gmacdev), synopGMACReadReg(gmacdev->DmaBase, DmaStatus)); + NU_GMAC_TRACE("%s: op:%08x\n", psNuGMAC->name, synopGMACReadReg(gmacdev->DmaBase, DmaControl)); + NU_GMAC_TRACE("%s: debug:%08x\n", psNuGMAC->name, synopGMACReadReg(gmacdev->MacBase, GmacDebug)); +} + +static void nu_memmgr_init(GMAC_MEMMGR_T *psMemMgr) +{ + psMemMgr->u32TxDescSize = TRANSMIT_DESC_SIZE; + psMemMgr->u32RxDescSize = RECEIVE_DESC_SIZE; + + psMemMgr->psTXDescs = (DmaDesc *) rt_malloc_align(sizeof(DmaDesc) * psMemMgr->u32TxDescSize, nu_cpu_dcache_line_size()); + RT_ASSERT(psMemMgr->psTXDescs); + LOG_D("[%s] First TXDescAddr= %08x", __func__, psMemMgr->psTXDescs); + + psMemMgr->psRXDescs = (DmaDesc *) rt_malloc_align(sizeof(DmaDesc) * psMemMgr->u32RxDescSize, nu_cpu_dcache_line_size()); + RT_ASSERT(psMemMgr->psRXDescs); + LOG_D("[%s] First RXDescAddr= %08x", __func__, psMemMgr->psRXDescs); + + psMemMgr->psTXFrames = (PKT_FRAME_T *) rt_malloc_align(sizeof(PKT_FRAME_T) * psMemMgr->u32TxDescSize, nu_cpu_dcache_line_size()); + RT_ASSERT(psMemMgr->psTXFrames); + LOG_D("[%s] First TXFrameAddr= %08x", __func__, psMemMgr->psTXFrames); + + psMemMgr->psRXFrames = (PKT_FRAME_T *) rt_malloc_align(sizeof(PKT_FRAME_T) * psMemMgr->u32RxDescSize, nu_cpu_dcache_line_size()); + RT_ASSERT(psMemMgr->psRXFrames); + LOG_D("[%s] First RXFrameAddr= %08x", __func__, psMemMgr->psRXFrames); +} + +static void nu_mii_init(synopGMACNetworkAdapter *adapter) +{ + /* MII setup */ + adapter->m_mii.phy_id_mask = 0x1F; + adapter->m_mii.reg_num_mask = 0x1F; + adapter->m_mii.adapter = (void *)adapter; + adapter->m_mii.mdio_read = nu_gmac_mdio_read; + adapter->m_mii.mdio_write = nu_gmac_mdio_write; + adapter->m_mii.phy_id = adapter->m_gmacdev->PhyBase; + adapter->m_mii.supports_gmii = mii_check_gmii_support(&adapter->m_mii); +} + +static rt_err_t nu_gmac_init(rt_device_t device) +{ + rt_err_t ret; + s32 status = 0; + char szTmp[32]; + int count; + + nu_gmac_t psNuGMAC = (nu_gmac_t)device; + RT_ASSERT(psNuGMAC); + + synopGMACNetworkAdapter *adapter = psNuGMAC->adapter; + synopGMACdevice *gmacdev = (synopGMACdevice *)adapter->m_gmacdev; + GMAC_MEMMGR_T *psgmacmemmgr = (GMAC_MEMMGR_T *)adapter->m_gmacmemmgr; + + RT_ASSERT(gmacdev); + RT_ASSERT(psgmacmemmgr); + + LOG_D("[%s] Init %s", __func__, psNuGMAC->name); + + synopGMAC_attach(gmacdev, ((uint32_t)psNuGMAC->base + MACBASE), ((uint32_t)psNuGMAC->base + DMABASE), DEFAULT_PHY_BASE, &psNuGMAC->mac_addr[0]); + nu_mii_init(adapter); + + /* Reset to make RGMII/RMII setting take affect. */ + synopGMAC_reset(gmacdev); + synopGMAC_read_version(gmacdev); + LOG_I("%s: HW version is %08x", psNuGMAC->name, gmacdev->Version); + + /*Check for Phy initialization*/ + synopGMAC_set_mdc_clk_div(gmacdev, GmiiCsrClk2); + gmacdev->ClockDivMdc = synopGMAC_get_mdc_clk_div(gmacdev); + status = synopGMAC_check_phy_init(adapter); + + /*Set up the tx and rx descriptor queue/ring*/ + LOG_D("tx desc_queue"); + synopGMAC_setup_tx_desc_queue(gmacdev, &psgmacmemmgr->psTXDescs[0], TRANSMIT_DESC_SIZE, RINGMODE); + synopGMAC_init_tx_desc_base(gmacdev); + LOG_D("DmaTxBaseAddr = %08x\n", synopGMACReadReg(gmacdev->DmaBase, DmaTxBaseAddr)); + + LOG_D("rx desc_queue"); + synopGMAC_setup_rx_desc_queue(gmacdev, &psgmacmemmgr->psRXDescs[0], RECEIVE_DESC_SIZE, RINGMODE); + synopGMAC_init_rx_desc_base(gmacdev); + LOG_D("DmaRxBaseAddr = %08x", synopGMACReadReg(gmacdev->DmaBase, DmaRxBaseAddr)); + + /*Initialize the dma interface*/ + synopGMAC_dma_bus_mode_init(gmacdev, DmaBurstLength32 | DmaDescriptorSkip0/*DmaDescriptorSkip2*/ | DmaDescriptor8Words); + synopGMAC_dma_control_init(gmacdev, DmaStoreAndForward | DmaTxSecondFrame | DmaRxThreshCtrl128); + + /*Initialize the mac interface*/ + gmacdev->Speed = SPEED1000; + gmacdev->DuplexMode = FULLDUPLEX; + synopGMAC_mac_init(gmacdev); + //synopGMAC_promisc_enable(gmacdev); + + synopGMAC_pause_control(gmacdev); // This enables the pause control in Full duplex mode of operation + +#if defined(RT_LWIP_USING_HW_CHECKSUM) + /*IPC Checksum offloading is enabled for this driver. Should only be used if Full Ip checksumm offload engine is configured in the hardware*/ + synopGMAC_enable_rx_chksum_offload(gmacdev); //Enable the offload engine in the receive path + synopGMAC_rx_tcpip_chksum_drop_enable(gmacdev); // This is default configuration, DMA drops the packets if error in encapsulated ethernet payload +#endif + + /* Set all RX frame buffers. */ + count = 0; + do + { + LOG_D("[%s] Set %d pkt frame buffer address - 0x%08x, size=%d", __func__, count, (u32)(&psgmacmemmgr->psRXFrames[count]), PKT_FRAME_BUF_SIZE); + status = synopGMAC_set_rx_qptr(gmacdev, (u32)(&psgmacmemmgr->psRXFrames[count]), PKT_FRAME_BUF_SIZE, 0); + if (status < 0) + { + LOG_E("status < 0!!"); + break; + } + count++; + } + while (count < RECEIVE_DESC_SIZE); + + synopGMAC_clear_interrupt(gmacdev); + + synopGMAC_disable_interrupt_all(gmacdev); + synopGMAC_enable_interrupt(gmacdev, DmaIntEnable); + LOG_D("%s: Interrupt enable: %08x", psNuGMAC->name, synopGMAC_get_ie(gmacdev)); + + synopGMAC_enable_dma_rx(gmacdev); + synopGMAC_enable_dma_tx(gmacdev); + + synopGMAC_set_mac_addr(gmacdev, GmacAddr0High, GmacAddr0Low, &psNuGMAC->mac_addr[0]); + + LOG_D("Create %s link monitor timer.", psNuGMAC->name); + /* Create timer to monitor link status. */ + psNuGMAC->link_timer = rt_timer_create("link_timer", + nu_gmac_link_monitor, + (void *)psNuGMAC, + RT_TICK_PER_SECOND, + RT_TIMER_FLAG_PERIODIC); + RT_ASSERT(psNuGMAC->link_timer); + + ret = rt_timer_start(psNuGMAC->link_timer); + RT_ASSERT(ret == RT_EOK); + + /* Install ISR */ + LOG_D("[%s] Install %s ISR.", __func__, psNuGMAC->name); + rt_snprintf(szTmp, sizeof(szTmp), "%s_rx", psNuGMAC->name); + rt_hw_interrupt_install(psNuGMAC->irqn, nu_gmac_isr, (void *)psNuGMAC, szTmp); + rt_hw_interrupt_umask(psNuGMAC->irqn); + + LOG_D("[%s] Init %s done", __func__, psNuGMAC->name); + + return RT_EOK; +} + +static rt_err_t nu_gmac_open(rt_device_t dev, rt_uint16_t oflag) +{ + return RT_EOK; +} + +static rt_err_t nu_gmac_close(rt_device_t dev) +{ + return RT_EOK; +} + +static rt_size_t nu_gmac_read(rt_device_t dev, rt_off_t pos, void *buffer, rt_size_t size) +{ + rt_set_errno(-RT_ENOSYS); + return 0; +} + +static rt_size_t nu_gmac_write(rt_device_t dev, rt_off_t pos, const void *buffer, rt_size_t size) +{ + rt_set_errno(-RT_ENOSYS); + return 0; +} + +static rt_err_t nu_gmac_control(rt_device_t device, int cmd, void *args) +{ + nu_gmac_t psNuGMAC = (nu_gmac_t)device; + RT_ASSERT(device); + + switch (cmd) + { + case NIOCTL_GADDR: + if (args) rt_memcpy(args, &psNuGMAC->mac_addr[0], 6); + else return -RT_ERROR; + break; + + default : + break; + } + + return RT_EOK; +} + +rt_err_t nu_gmac_tx(rt_device_t device, struct pbuf *p) +{ + rt_err_t ret = -RT_ERROR; + s32 status; + + nu_gmac_t psNuGMAC = (nu_gmac_t)device; + synopGMACNetworkAdapter *adapter; + synopGMACdevice *gmacdev; + GMAC_MEMMGR_T *psgmacmemmgr; + + RT_ASSERT(device); + + adapter = (synopGMACNetworkAdapter *) psNuGMAC->adapter; + RT_ASSERT(adapter); + + gmacdev = (synopGMACdevice *) adapter->m_gmacdev; + RT_ASSERT(gmacdev); + + psgmacmemmgr = (GMAC_MEMMGR_T *)adapter->m_gmacmemmgr; + RT_ASSERT(psgmacmemmgr); + + if (!synopGMAC_is_desc_owned_by_dma(gmacdev->TxNextDesc)) + { + u32 offload_needed; +#if defined(RT_LWIP_USING_HW_CHECKSUM) + offload_needed = 1; +#else + offload_needed = 0; +#endif + u32 index = gmacdev->TxNext; + u8 *pu8PktData = (u8 *)((u32)&psgmacmemmgr->psTXFrames[index] | UNCACHEABLE); + struct pbuf *q; + rt_uint32_t offset = 0; + + LOG_D("%s: Transmitting data(%08x-%d).\n", psNuGMAC->name, (u32)&psgmacmemmgr->psTXFrames[index], p->tot_len); + + /* Copy to TX data buffer. */ + for (q = p; q != NULL; q = q->next) + { + rt_uint8_t *ptr = q->payload; + rt_uint32_t len = q->len; + rt_memcpy(&pu8PktData[offset], ptr, len); + offset += len; + } + + status = synopGMAC_xmit_frames(gmacdev, (u8 *)&psgmacmemmgr->psTXFrames[index], offset, offload_needed, 0); + if (status != 0) + { + LOG_E("%s No More Free Tx skb\n", __func__); + ret = -RT_ERROR; + goto exit_nu_gmac_tx; + } + } + else + { + LOG_E("No avaialbe TX descriptor.\n"); + ret = -RT_ERROR; + goto exit_nu_gmac_tx; + } + + ret = RT_EOK; + +exit_nu_gmac_tx: + + return ret; +} + +void nu_gmac_pbuf_free(struct pbuf *p) +{ + nu_gmac_lwip_pbuf_t my_buf = (nu_gmac_lwip_pbuf_t)p; + s32 status; + + SYS_ARCH_DECL_PROTECT(old_level); + SYS_ARCH_PROTECT(old_level); + status = synopGMAC_set_rx_qptr(my_buf->gmacdev, (u32)my_buf->psPktFrameDataBuf, PKT_FRAME_BUF_SIZE, 0); + if (status < 0) + { + LOG_E("synopGMAC_set_rx_qptr: status < 0!!\n"); + } + memp_free_pool(my_buf->pool, my_buf); + SYS_ARCH_UNPROTECT(old_level); +} + +struct pbuf *nu_gmac_rx(rt_device_t device) +{ + nu_gmac_t psNuGMAC = (nu_gmac_t)device; + synopGMACNetworkAdapter *adapter; + synopGMACdevice *gmacdev; + struct pbuf *pbuf = RT_NULL; + PKT_FRAME_T *psPktFrame; + s32 s32PktLen; + + RT_ASSERT(device); + + adapter = psNuGMAC->adapter; + RT_ASSERT(adapter); + + gmacdev = (synopGMACdevice *) adapter->m_gmacdev; + RT_ASSERT(gmacdev); + + if ((s32PktLen = synop_handle_received_data(gmacdev, &psPktFrame)) > 0) + { + nu_gmac_lwip_pbuf_t my_pbuf = (nu_gmac_lwip_pbuf_t)memp_malloc_pool(psNuGMAC->memp_rx_pool); + if (my_pbuf != RT_NULL) + { + my_pbuf->p.custom_free_function = nu_gmac_pbuf_free; + my_pbuf->psPktFrameDataBuf = psPktFrame; + my_pbuf->gmacdev = gmacdev; + my_pbuf->pool = psNuGMAC->memp_rx_pool; + + invalidate_cpu_cache(psPktFrame, s32PktLen); + pbuf = pbuf_alloced_custom(PBUF_RAW, + s32PktLen, + PBUF_REF, + &my_pbuf->p, + psPktFrame, + PKT_FRAME_BUF_SIZE); + if (pbuf == RT_NULL) + LOG_E("%s: failed to alloted %08x\n", psNuGMAC->name, pbuf); + } + else + { + LOG_E("LWIP_MEMPOOL_ALLOC < 0!!\n"); + } + } + else + { + //rt_kprintf("%s : fail to receive data.\n", psNuGMAC->name); + synopGMAC_enable_interrupt(gmacdev, DmaIntEnable); + goto exit_nu_gmac_rx; + } + +exit_nu_gmac_rx: + + return pbuf; +} + +static void nu_gmac_assign_macaddr(nu_gmac_t psNuGMAC) +{ + static rt_uint32_t value = 0x94539452; + + /* Assign MAC address */ + psNuGMAC->mac_addr[0] = 0x82; + psNuGMAC->mac_addr[1] = 0x06; + psNuGMAC->mac_addr[2] = 0x21; + psNuGMAC->mac_addr[3] = (value >> 16) & 0xff; + psNuGMAC->mac_addr[4] = (value >> 8) & 0xff; + psNuGMAC->mac_addr[5] = (value) & 0xff; + + LOG_I("MAC address: %02X:%02X:%02X:%02X:%02X:%02X\n", \ + psNuGMAC->mac_addr[0], \ + psNuGMAC->mac_addr[1], \ + psNuGMAC->mac_addr[2], \ + psNuGMAC->mac_addr[3], \ + psNuGMAC->mac_addr[4], \ + psNuGMAC->mac_addr[5]); + value++; +} + +int32_t nu_gmac_adapter_init(nu_gmac_t psNuGMAC) +{ + synopGMACNetworkAdapter *adapter; + + RT_ASSERT(psNuGMAC); + + /* Allocate net adapter */ + adapter = (synopGMACNetworkAdapter *)rt_malloc_align(sizeof(synopGMACNetworkAdapter), nu_cpu_dcache_line_size()); + RT_ASSERT(adapter); + rt_memset((void *)adapter, 0, sizeof(synopGMACNetworkAdapter)); + + /* Allocate device */ + adapter->m_gmacdev = (synopGMACdevice *) rt_malloc_align(sizeof(synopGMACdevice), nu_cpu_dcache_line_size()); + RT_ASSERT(adapter->m_gmacdev); + rt_memset((char *)adapter->m_gmacdev, 0, sizeof(synopGMACdevice)); + + /* Allocate memory management */ + adapter->m_gmacmemmgr = (GMAC_MEMMGR_T *) rt_malloc_align(sizeof(GMAC_MEMMGR_T), nu_cpu_dcache_line_size()); + RT_ASSERT(adapter->m_gmacmemmgr); + nu_memmgr_init(adapter->m_gmacmemmgr); + + /* Store adapter to priv */ + psNuGMAC->adapter = adapter; + + return 0; +} + +int rt_hw_gmac_init(void) +{ + int i; + rt_err_t ret = RT_EOK; + + for (i = (GMAC_START + 1); i < GMAC_CNT; i++) + { + nu_gmac_t psNuGMAC = (nu_gmac_t)&nu_gmac_arr[i]; + + /* Register member functions */ + psNuGMAC->eth.parent.type = RT_Device_Class_NetIf; + psNuGMAC->eth.parent.init = nu_gmac_init; + psNuGMAC->eth.parent.open = nu_gmac_open; + psNuGMAC->eth.parent.close = nu_gmac_close; + psNuGMAC->eth.parent.read = nu_gmac_read; + psNuGMAC->eth.parent.write = nu_gmac_write; + psNuGMAC->eth.parent.control = nu_gmac_control; + psNuGMAC->eth.parent.user_data = psNuGMAC; + psNuGMAC->eth.eth_rx = nu_gmac_rx; + psNuGMAC->eth.eth_tx = nu_gmac_tx; + + /* Set MAC address */ + nu_gmac_assign_macaddr(psNuGMAC); + + /* Initial GMAC adapter */ + nu_gmac_adapter_init(psNuGMAC); + + /* Initial zero_copy rx pool */ + memp_init_pool(psNuGMAC->memp_rx_pool); + + /* Register eth device */ + ret = eth_device_init(&psNuGMAC->eth, psNuGMAC->name); + RT_ASSERT(ret == RT_EOK); + } + + + return 0; +} +INIT_APP_EXPORT(rt_hw_gmac_init); + +#if 0 +/* + Remeber src += lwipiperf_SRCS in components\net\lwip-*\SConscript +*/ +#include "lwip/apps/lwiperf.h" + +static void +lwiperf_report(void *arg, enum lwiperf_report_type report_type, + const ip_addr_t *local_addr, u16_t local_port, const ip_addr_t *remote_addr, u16_t remote_port, + u32_t bytes_transferred, u32_t ms_duration, u32_t bandwidth_kbitpsec) +{ + LWIP_UNUSED_ARG(arg); + LWIP_UNUSED_ARG(local_addr); + LWIP_UNUSED_ARG(local_port); + + rt_kprintf("IPERF report: type=%d, remote: %s:%d, total bytes: %"U32_F", duration in ms: %"U32_F", kbits/s: %"U32_F"\n", + (int)report_type, ipaddr_ntoa(remote_addr), (int)remote_port, bytes_transferred, ms_duration, bandwidth_kbitpsec); +} + +void lwiperf_example_init(void) +{ + lwiperf_start_tcp_server_default(lwiperf_report, NULL); +} +MSH_CMD_EXPORT(lwiperf_example_init, start lwip tcp server); +#endif + +#endif /* if defined(BSP_USING_GMAC) */ diff --git a/bsp/nuvoton/libraries/ma35/rtt_port/gmac/mii.c b/bsp/nuvoton/libraries/ma35/rtt_port/gmac/mii.c new file mode 100644 index 0000000000..904a5250e9 --- /dev/null +++ b/bsp/nuvoton/libraries/ma35/rtt_port/gmac/mii.c @@ -0,0 +1,144 @@ +/**************************************************************************//** +* +* @copyright (C) 2020 Nuvoton Technology Corp. All rights reserved. +* +* SPDX-License-Identifier: Apache-2.0 +* +* Change Logs: +* Date Author Notes +* 2021-07-23 Wayne First version +* +******************************************************************************/ + +#include "mii.h" + +unsigned int mii_nway_result(unsigned int negotiated) +{ + unsigned int ret; + + if (negotiated & LPA_100FULL) + ret = LPA_100FULL; + else if (negotiated & LPA_100BASE4) + ret = LPA_100BASE4; + else if (negotiated & LPA_100HALF) + ret = LPA_100HALF; + else if (negotiated & LPA_10FULL) + ret = LPA_10FULL; + else + ret = LPA_10HALF; + + return ret; +} + +int mii_check_gmii_support(struct mii_if_info *mii) +{ + int reg; + + reg = mii->mdio_read(mii->adapter, mii->phy_id, MII_BMSR); + if (reg & BMSR_ESTATEN) + { + reg = mii->mdio_read(mii->adapter, mii->phy_id, MII_ESTATUS); + if (reg & (ESTATUS_1000_TFULL | ESTATUS_1000_THALF)) + return 1; + } + + return 0; +} + +int mii_ethtool_gset(struct mii_if_info *mii, struct ethtool_cmd *ecmd) +{ + void *adapter = mii->adapter; + u32 advert, bmcr, lpa, nego; + u32 advert2 = 0, bmcr2 = 0, lpa2 = 0; + + ecmd->supported = + (SUPPORTED_10baseT_Half | SUPPORTED_10baseT_Full | + SUPPORTED_100baseT_Half | SUPPORTED_100baseT_Full | + SUPPORTED_Autoneg | SUPPORTED_TP | SUPPORTED_MII); + if (mii->supports_gmii) + ecmd->supported |= SUPPORTED_1000baseT_Half | + SUPPORTED_1000baseT_Full; + + /* only supports twisted-pair */ + ecmd->port = PORT_MII; + + /* only supports internal transceiver */ + ecmd->transceiver = XCVR_INTERNAL; + + /* this isn't fully supported at higher layers */ + ecmd->phy_address = mii->phy_id; + + ecmd->advertising = ADVERTISED_TP | ADVERTISED_MII; + advert = mii->mdio_read(adapter, mii->phy_id, MII_ADVERTISE); + if (mii->supports_gmii) + advert2 = mii->mdio_read(adapter, mii->phy_id, MII_CTRL1000); + + if (advert & ADVERTISE_10HALF) + ecmd->advertising |= ADVERTISED_10baseT_Half; + if (advert & ADVERTISE_10FULL) + ecmd->advertising |= ADVERTISED_10baseT_Full; + if (advert & ADVERTISE_100HALF) + ecmd->advertising |= ADVERTISED_100baseT_Half; + if (advert & ADVERTISE_100FULL) + ecmd->advertising |= ADVERTISED_100baseT_Full; + if (advert2 & ADVERTISE_1000HALF) + ecmd->advertising |= ADVERTISED_1000baseT_Half; + if (advert2 & ADVERTISE_1000FULL) + ecmd->advertising |= ADVERTISED_1000baseT_Full; + + bmcr = mii->mdio_read(adapter, mii->phy_id, MII_BMCR); + lpa = mii->mdio_read(adapter, mii->phy_id, MII_LPA); + if (mii->supports_gmii) + { + bmcr2 = mii->mdio_read(adapter, mii->phy_id, MII_CTRL1000); + lpa2 = mii->mdio_read(adapter, mii->phy_id, MII_STAT1000); + } + if (bmcr & BMCR_ANENABLE) + { + ecmd->advertising |= ADVERTISED_Autoneg; + ecmd->autoneg = AUTONEG_ENABLE; + + nego = mii_nway_result(advert & lpa); + if ((bmcr2 & (ADVERTISE_1000HALF | ADVERTISE_1000FULL)) & + (lpa2 >> 2)) + ecmd->speed = SPEED_1000; + else if (nego == LPA_100FULL || nego == LPA_100HALF) + ecmd->speed = SPEED_100; + else + ecmd->speed = SPEED_10; + if ((lpa2 & LPA_1000FULL) || nego == LPA_100FULL || + nego == LPA_10FULL) + { + ecmd->duplex = DUPLEX_FULL; + mii->full_duplex = 1; + } + else + { + ecmd->duplex = DUPLEX_HALF; + mii->full_duplex = 0; + } + } + else + { + ecmd->autoneg = AUTONEG_DISABLE; + + ecmd->speed = ((bmcr & BMCR_SPEED1000 && + (bmcr & BMCR_SPEED100) == 0) ? SPEED_1000 : + (bmcr & BMCR_SPEED100) ? SPEED_100 : SPEED_10); + ecmd->duplex = (bmcr & BMCR_FULLDPLX) ? DUPLEX_FULL : DUPLEX_HALF; + } + + /* ignore maxtxpkt, maxrxpkt for now */ + + return 0; +} + +int mii_link_ok(struct mii_if_info *mii) +{ + /* first, a dummy read, needed to latch some MII phys */ + mii->mdio_read(mii->adapter, mii->phy_id, MII_BMSR); + if (mii->mdio_read(mii->adapter, mii->phy_id, MII_BMSR) & BMSR_LSTATUS) + return 1; + return 0; +} + diff --git a/bsp/nuvoton/libraries/ma35/rtt_port/gmac/mii.h b/bsp/nuvoton/libraries/ma35/rtt_port/gmac/mii.h new file mode 100644 index 0000000000..58b6af21a7 --- /dev/null +++ b/bsp/nuvoton/libraries/ma35/rtt_port/gmac/mii.h @@ -0,0 +1,233 @@ +/* + * Copyright (c) 2006-2022, RT-Thread Development Team + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + * 2017-08-24 chinesebear first version + */ + +#ifndef __MII_H__ +#define __MII_H__ + +#include "synopGMAC_types.h" + +#define MII_BMCR 0x00 /* Basic mode control register */ +#define MII_BMSR 0x01 /* Basic mode status register */ +#define MII_PHYSID1 0x02 /* PHYS ID 1 */ +#define MII_PHYSID2 0x03 /* PHYS ID 2 */ +#define MII_ADVERTISE 0x04 /* Advertisement control reg */ +#define MII_LPA 0x05 /* Link partner ability reg */ +#define MII_EXPANSION 0x06 /* Expansion register */ +#define MII_CTRL1000 0x09 /* 1000BASE-T control */ +#define MII_STAT1000 0x0a /* 1000BASE-T status */ +#define MII_ESTATUS 0x0f /* Extended Status */ +#define MII_DCOUNTER 0x12 /* Disconnect counter */ +#define MII_FCSCOUNTER 0x13 /* False carrier counter */ +#define MII_NWAYTEST 0x14 /* N-way auto-neg test reg */ +#define MII_RERRCOUNTER 0x15 /* Receive error counter */ +#define MII_SREVISION 0x16 /* Silicon revision */ +#define MII_RESV1 0x17 /* Reserved... */ +#define MII_LBRERROR 0x18 /* Lpback, rx, bypass error */ +#define MII_PHYADDR 0x19 /* PHY address */ +#define MII_RESV2 0x1a /* Reserved... */ +#define MII_TPISTATUS 0x1b /* TPI status for 10mbps */ +#define MII_NCONFIG 0x1c /* Network interface config */ + +/* Basic mode control register. */ +#define BMCR_RESV 0x003f /* Unused... */ +#define BMCR_SPEED1000 0x0040 /* MSB of Speed (1000) */ +#define BMCR_CTST 0x0080 /* Collision test */ +#define BMCR_FULLDPLX 0x0100 /* Full duplex */ +#define BMCR_ANRESTART 0x0200 /* Auto negotiation restart */ +#define BMCR_ISOLATE 0x0400 /* Disconnect DP83840 from MII */ +#define BMCR_PDOWN 0x0800 /* Powerdown the DP83840 */ +#define BMCR_ANENABLE 0x1000 /* Enable auto negotiation */ +#define BMCR_SPEED100 0x2000 /* Select 100Mbps */ +#define BMCR_LOOPBACK 0x4000 /* TXD loopback bits */ +#define BMCR_RESET 0x8000 /* Reset the DP83840 */ + +/* Basic mode status register. */ +#define BMSR_ERCAP 0x0001 /* Ext-reg capability */ +#define BMSR_JCD 0x0002 /* Jabber detected */ +#define BMSR_LSTATUS 0x0004 /* Link status */ +#define BMSR_ANEGCAPABLE 0x0008 /* Able to do auto-negotiation */ +#define BMSR_RFAULT 0x0010 /* Remote fault detected */ +#define BMSR_ANEGCOMPLETE 0x0020 /* Auto-negotiation complete */ +#define BMSR_RESV 0x00c0 /* Unused... */ +#define BMSR_ESTATEN 0x0100 /* Extended Status in R15 */ +#define BMSR_100FULL2 0x0200 /* Can do 100BASE-T2 HDX */ +#define BMSR_100HALF2 0x0400 /* Can do 100BASE-T2 FDX */ +#define BMSR_10HALF 0x0800 /* Can do 10mbps, half-duplex */ +#define BMSR_10FULL 0x1000 /* Can do 10mbps, full-duplex */ +#define BMSR_100HALF 0x2000 /* Can do 100mbps, half-duplex */ +#define BMSR_100FULL 0x4000 /* Can do 100mbps, full-duplex */ +#define BMSR_100BASE4 0x8000 /* Can do 100mbps, 4k packets */ + +/* Advertisement control register. */ +#define ADVERTISE_SLCT 0x001f /* Selector bits */ +#define ADVERTISE_CSMA 0x0001 /* Only selector supported */ +#define ADVERTISE_10HALF 0x0020 /* Try for 10mbps half-duplex */ +#define ADVERTISE_1000XFULL 0x0020 /* Try for 1000BASE-X full-duplex */ +#define ADVERTISE_10FULL 0x0040 /* Try for 10mbps full-duplex */ +#define ADVERTISE_1000XHALF 0x0040 /* Try for 1000BASE-X half-duplex */ +#define ADVERTISE_100HALF 0x0080 /* Try for 100mbps half-duplex */ +#define ADVERTISE_1000XPAUSE 0x0080 /* Try for 1000BASE-X pause */ +#define ADVERTISE_100FULL 0x0100 /* Try for 100mbps full-duplex */ +#define ADVERTISE_1000XPSE_ASYM 0x0100 /* Try for 1000BASE-X asym pause */ +#define ADVERTISE_100BASE4 0x0200 /* Try for 100mbps 4k packets */ +#define ADVERTISE_PAUSE_CAP 0x0400 /* Try for pause */ +#define ADVERTISE_PAUSE_ASYM 0x0800 /* Try for asymetric pause */ +#define ADVERTISE_RESV 0x1000 /* Unused... */ +#define ADVERTISE_RFAULT 0x2000 /* Say we can detect faults */ +#define ADVERTISE_LPACK 0x4000 /* Ack link partners response */ +#define ADVERTISE_NPAGE 0x8000 /* Next page bit */ + +#define ADVERTISE_FULL (ADVERTISE_100FULL | ADVERTISE_10FULL | ADVERTISE_CSMA) +#define ADVERTISE_ALL (ADVERTISE_10HALF | ADVERTISE_10FULL | ADVERTISE_100HALF | ADVERTISE_100FULL) + +/* Indicates what features are advertised by the interface. */ +#define ADVERTISED_10baseT_Half (1 << 0) +#define ADVERTISED_10baseT_Full (1 << 1) +#define ADVERTISED_100baseT_Half (1 << 2) +#define ADVERTISED_100baseT_Full (1 << 3) +#define ADVERTISED_1000baseT_Half (1 << 4) +#define ADVERTISED_1000baseT_Full (1 << 5) +#define ADVERTISED_Autoneg (1 << 6) +#define ADVERTISED_TP (1 << 7) +#define ADVERTISED_AUI (1 << 8) +#define ADVERTISED_MII (1 << 9) +#define ADVERTISED_FIBRE (1 << 10) +#define ADVERTISED_BNC (1 << 11) +#define ADVERTISED_10000baseT_Full (1 << 12) +#define ADVERTISED_Pause (1 << 13) +#define ADVERTISED_Asym_Pause (1 << 14) + +/* Link partner ability register. */ +#define LPA_SLCT 0x001f /* Same as advertise selector */ +#define LPA_10HALF 0x0020 /* Can do 10mbps half-duplex */ +#define LPA_1000XFULL 0x0020 /* Can do 1000BASE-X full-duplex */ +#define LPA_10FULL 0x0040 /* Can do 10mbps full-duplex */ +#define LPA_1000XHALF 0x0040 /* Can do 1000BASE-X half-duplex */ +#define LPA_100HALF 0x0080 /* Can do 100mbps half-duplex */ +#define LPA_1000XPAUSE 0x0080 /* Can do 1000BASE-X pause */ +#define LPA_100FULL 0x0100 /* Can do 100mbps full-duplex */ +#define LPA_1000XPAUSE_ASYM 0x0100 /* Can do 1000BASE-X pause asym*/ +#define LPA_100BASE4 0x0200 /* Can do 100mbps 4k packets */ +#define LPA_PAUSE_CAP 0x0400 /* Can pause */ +#define LPA_PAUSE_ASYM 0x0800 /* Can pause asymetrically */ +#define LPA_RESV 0x1000 /* Unused... */ +#define LPA_RFAULT 0x2000 /* Link partner faulted */ +#define LPA_LPACK 0x4000 /* Link partner acked us */ +#define LPA_NPAGE 0x8000 /* Next page bit */ + +#define LPA_DUPLEX (LPA_10FULL | LPA_100FULL) +#define LPA_100 (LPA_100FULL | LPA_100HALF | LPA_100BASE4) + +/* Expansion register for auto-negotiation. */ +#define EXPANSION_NWAY 0x0001 /* Can do N-way auto-nego */ +#define EXPANSION_LCWP 0x0002 /* Got new RX page code word */ +#define EXPANSION_ENABLENPAGE 0x0004 /* This enables npage words */ +#define EXPANSION_NPCAPABLE 0x0008 /* Link partner supports npage */ +#define EXPANSION_MFAULTS 0x0010 /* Multiple faults detected */ +#define EXPANSION_RESV 0xffe0 /* Unused... */ + +#define ESTATUS_1000_TFULL 0x2000 /* Can do 1000BT Full */ +#define ESTATUS_1000_THALF 0x1000 /* Can do 1000BT Half */ + +/* N-way test register. */ +#define NWAYTEST_RESV1 0x00ff /* Unused... */ +#define NWAYTEST_LOOPBACK 0x0100 /* Enable loopback for N-way */ +#define NWAYTEST_RESV2 0xfe00 /* Unused... */ + +/* 1000BASE-T Control register */ +#define ADVERTISE_1000FULL 0x0200 /* Advertise 1000BASE-T full duplex */ +#define ADVERTISE_1000HALF 0x0100 /* Advertise 1000BASE-T half duplex */ + +/* 1000BASE-T Status register */ +#define LPA_1000LOCALRXOK 0x2000 /* Link partner local receiver status */ +#define LPA_1000REMRXOK 0x1000 /* Link partner remote receiver status */ +#define LPA_1000FULL 0x0800 /* Link partner 1000BASE-T full duplex */ + +#define SUPPORTED_10baseT_Half (1 << 0) +#define SUPPORTED_10baseT_Full (1 << 1) +#define SUPPORTED_100baseT_Half (1 << 2) +#define SUPPORTED_100baseT_Full (1 << 3) +#define SUPPORTED_1000baseT_Half (1 << 4) +#define SUPPORTED_1000baseT_Full (1 << 5) +#define SUPPORTED_Autoneg (1 << 6) +#define SUPPORTED_TP (1 << 7) +#define SUPPORTED_AUI (1 << 8) +#define SUPPORTED_MII (1 << 9) +#define SUPPORTED_FIBRE (1 << 10) +#define SUPPORTED_BNC (1 << 11) +#define SUPPORTED_10000baseT_Full (1 << 12) +#define SUPPORTED_Pause (1 << 13) +#define SUPPORTED_Asym_Pause (1 << 14) + + +/* Which connector port. */ +#define PORT_TP 0x00 +#define PORT_AUI 0x01 +#define PORT_MII 0x02 +#define PORT_FIBRE 0x03 +#define PORT_BNC 0x04 + +/* Which transceiver to use. */ +#define XCVR_INTERNAL 0x00 +#define XCVR_EXTERNAL 0x01 +#define XCVR_DUMMY1 0x02 +#define XCVR_DUMMY2 0x03 +#define XCVR_DUMMY3 0x04 + +#define AUTONEG_DISABLE 0x00 +#define AUTONEG_ENABLE 0x01 + + +#define SPEED_10 10 +#define SPEED_100 100 +#define SPEED_1000 1000 +#define SPEED_2500 2500 +#define SPEED_10000 10000 + +#define DUPLEX_HALF 0x00 +#define DUPLEX_FULL 0x01 + +struct ethtool_cmd +{ + u32 cmd; + u32 supported; /* Features this interface supports */ + u32 advertising; /* Features this interface advertises */ + u16 speed; /* The forced speed, 10Mb, 100Mb, gigabit */ + u8 duplex; /* Duplex, half or full */ + u8 port; /* Which connector port */ + u8 phy_address; + u8 transceiver; /* Which transceiver to use */ + u8 autoneg; /* Enable or disable autonegotiation */ + u32 maxtxpkt; /* Tx pkts before generating tx int */ + u32 maxrxpkt; /* Rx pkts before generating rx int */ + u32 reserved[4]; +}; + +struct mii_if_info +{ + int phy_id; + int advertising; + int phy_id_mask; + int reg_num_mask; + + unsigned int full_duplex : 1; /* is full duplex? */ + unsigned int force_media : 1; /* is autoneg. disabled? */ + unsigned int supports_gmii : 1; /* are GMII registers supported? */ + + void *adapter; + int (*mdio_read)(void *adapter, int phy_id, int location); + void (*mdio_write)(void *adapter, int phy_id, int location, int val); +}; + +unsigned int mii_nway_result(unsigned int negotiated); +int mii_check_gmii_support(struct mii_if_info *mii); +int mii_ethtool_gset(struct mii_if_info *mii, struct ethtool_cmd *ecmd); +int mii_link_ok(struct mii_if_info *mii); +#endif diff --git a/bsp/nuvoton/libraries/ma35/rtt_port/gmac/synopGMAC_Dev.c b/bsp/nuvoton/libraries/ma35/rtt_port/gmac/synopGMAC_Dev.c new file mode 100644 index 0000000000..52e6c6ede9 --- /dev/null +++ b/bsp/nuvoton/libraries/ma35/rtt_port/gmac/synopGMAC_Dev.c @@ -0,0 +1,2961 @@ +/* =================================================================================== + * Copyright (c) <2009> Synopsys, Inc. + * + * Permission is hereby granted, free of charge, to any person obtaining a copy of + * this software annotated with this license and associated documentation files + * (the "Software"), to deal in the Software without restriction, including without + * limitation the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the Software is + * furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in all + * copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, + * INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS FOR A + * PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT + * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION + * OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE + * OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + * + * =================================================================================== */ + +/** \file + * This file defines the synopsys GMAC device dependent functions. + * Most of the operations on the GMAC device are available in this file. + * Functions for initiliasing and accessing MAC/DMA/PHY registers and the DMA descriptors + * are encapsulated in this file. The functions are platform/host/OS independent. + * These functions in turn use the low level device dependent (HAL) functions to + * access the register space. + * \internal + * ------------------------REVISION HISTORY--------------------------------- + * Synopsys 01/Aug/2007 Created + */ + +#include "synopGMAC_Dev.h" +#include "synopGMAC_network_interface.h" + +/** + * Function to set the MDC clock for mdio transactiona + * + * @param[in] pointer to device structure. + * @param[in] clk divider value. + * \return Reuturns 0 on success else return the error value. + */ +s32 synopGMAC_set_mdc_clk_div(synopGMACdevice *gmacdev, u32 clk_div_val) +{ + u32 orig_data; + orig_data = synopGMACReadReg(gmacdev->MacBase, GmacGmiiAddr); //set the mdc clock to the user defined value + orig_data &= (~ GmiiCsrClkMask); + orig_data |= clk_div_val; + synopGMACWriteReg(gmacdev->MacBase, GmacGmiiAddr, orig_data); + return 0; +} + +/** + * Returns the current MDC divider value programmed in the ip. + * + * @param[in] pointer to device structure. + * @param[in] clk divider value. + * \return Returns the MDC divider value read. + */ +u32 synopGMAC_get_mdc_clk_div(synopGMACdevice *gmacdev) +{ + u32 data; + data = synopGMACReadReg(gmacdev->MacBase, GmacGmiiAddr); + data &= GmiiCsrClkMask; + return data; +} + + +/** + * Function to read the Phy register. The access to phy register + * is a slow process as the data is moved accross MDI/MDO interface + * @param[in] pointer to Register Base (It is the mac base in our case) . + * @param[in] PhyBase register is the index of one of supported 32 PHY devices. + * @param[in] Register offset is the index of one of the 32 phy register. + * @param[out] u16 data read from the respective phy register (only valid iff return value is 0). + * \return Returns 0 on success else return the error status. + */ +s32 synopGMAC_read_phy_reg(u32 RegBase, u32 PhyBase, u32 RegOffset, u16 *data) +{ + u32 addr; + u32 loop_variable; + addr = ((PhyBase << GmiiDevShift) & GmiiDevMask) | ((RegOffset << GmiiRegShift) & GmiiRegMask); + addr = addr | GmiiBusy ; //Gmii busy bit + synopGMACWriteReg(RegBase, GmacGmiiAddr, addr); //write the address from where the data to be read in GmiiGmiiAddr register of synopGMAC ip + + for (loop_variable = 0; loop_variable < DEFAULT_LOOP_VARIABLE; loop_variable++) //Wait till the busy bit gets cleared with in a certain amount of time + { + if (!(synopGMACReadReg(RegBase, GmacGmiiAddr) & GmiiBusy)) + { + break; + } + plat_delay(DEFAULT_DELAY_VARIABLE); + } + if (loop_variable < DEFAULT_LOOP_VARIABLE) + * data = (u16)(synopGMACReadReg(RegBase, GmacGmiiData) & 0xFFFF); + else + { + TR("Error::: PHY not responding Busy bit didnot get cleared !!!!!!\n"); + return -ESYNOPGMACPHYERR; + } + return 0; +} + +/** + * Function to write to the Phy register. The access to phy register + * is a slow process as the data is moved accross MDI/MDO interface + * @param[in] pointer to Register Base (It is the mac base in our case) . + * @param[in] PhyBase register is the index of one of supported 32 PHY devices. + * @param[in] Register offset is the index of one of the 32 phy register. + * @param[in] data to be written to the respective phy register. + * \return Returns 0 on success else return the error status. + */ +s32 synopGMAC_write_phy_reg(u32 RegBase, u32 PhyBase, u32 RegOffset, u16 data) +{ + u32 addr; + u32 loop_variable; + + synopGMACWriteReg(RegBase, GmacGmiiData, data); // write the data in to GmacGmiiData register of synopGMAC ip + + addr = ((PhyBase << GmiiDevShift) & GmiiDevMask) | ((RegOffset << GmiiRegShift) & GmiiRegMask) | GmiiWrite; + + addr = addr | GmiiBusy ; //set Gmii clk to 20-35 Mhz and Gmii busy bit + + synopGMACWriteReg(RegBase, GmacGmiiAddr, addr); + for (loop_variable = 0; loop_variable < DEFAULT_LOOP_VARIABLE; loop_variable++) + { + if (!(synopGMACReadReg(RegBase, GmacGmiiAddr) & GmiiBusy)) + { + break; + } + plat_delay(DEFAULT_DELAY_VARIABLE); + } + + if (loop_variable < DEFAULT_LOOP_VARIABLE) + { + return 0; + } + else + { + TR("Error::: PHY not responding Busy bit didnot get cleared !!!!!!\n"); + return -ESYNOPGMACPHYERR; + } +} + +/** + * Function to configure the phy in loopback mode. + * + * @param[in] pointer to synopGMACdevice. + * @param[in] enable or disable the loopback. + * \return 0 on success else return the error status. + * \note Don't get confused with mac loop-back synopGMAC_loopback_on(synopGMACdevice *) + * and synopGMAC_loopback_off(synopGMACdevice *) functions. + */ +s32 synopGMAC_phy_loopback(synopGMACdevice *gmacdev, bool loopback) +{ + s32 status = 0; +#ifndef EMULATION + if (loopback) + status = synopGMAC_write_phy_reg(gmacdev->MacBase, gmacdev->PhyBase, PHY_CONTROL_REG, Mii_Loopback); + else + status = synopGMAC_write_phy_reg(gmacdev->MacBase, gmacdev->PhyBase, PHY_CONTROL_REG, Mii_NoLoopback); +#endif + return status; +} + + + +/** + * Function to read the GMAC IP Version and populates the same in device data structure. + * @param[in] pointer to synopGMACdevice. + * \return Always return 0. + */ + +s32 synopGMAC_read_version(synopGMACdevice *gmacdev) +{ + u32 data = 0; + data = synopGMACReadReg(gmacdev->MacBase, GmacVersion); + gmacdev->Version = data; + TR("The data read from %08x is %08x\n", (gmacdev->MacBase + GmacVersion), data); + return 0; +} + + +/** + * Function to reset the GMAC core. + * This reests the DMA and GMAC core. After reset all the registers holds their respective reset value + * @param[in] pointer to synopGMACdevice. + * \return 0 on success else return the error status. + */ + +s32 synopGMAC_reset(synopGMACdevice *gmacdev) +{ + u32 data = 0; + synopGMACWriteReg(gmacdev->DmaBase, DmaBusMode, DmaResetOn); + plat_delay(DEFAULT_LOOP_VARIABLE); + + do + { + data = synopGMACReadReg(gmacdev->DmaBase, DmaBusMode); + } + while (data & 1); + + TR("DATA after Reset = %08x\n", data); + + return 0; +} + +s32 synopGMAC_reset_nocheck(synopGMACdevice *gmacdev) +{ + synopGMACWriteReg(gmacdev->DmaBase, DmaBusMode, DmaResetOn); + plat_delay(DEFAULT_LOOP_VARIABLE); + return 0; +} + +/** + * Function to program DMA bus mode register. + * + * The Bus Mode register is programmed with the value given. The bits to be set are + * bit wise or'ed and sent as the second argument to this function. + * @param[in] pointer to synopGMACdevice. + * @param[in] the data to be programmed. + * \return 0 on success else return the error status. + */ +s32 synopGMAC_dma_bus_mode_init(synopGMACdevice *gmacdev, u32 init_value) +{ + synopGMACWriteReg(gmacdev->DmaBase, DmaBusMode, init_value); + return 0; + +} + +/** + * Function to program DMA Control register. + * + * The Dma Control register is programmed with the value given. The bits to be set are + * bit wise or'ed and sent as the second argument to this function. + * @param[in] pointer to synopGMACdevice. + * @param[in] the data to be programmed. + * \return 0 on success else return the error status. + */ +s32 synopGMAC_dma_control_init(synopGMACdevice *gmacdev, u32 init_value) +{ + synopGMACWriteReg(gmacdev->DmaBase, DmaControl, init_value); + return 0; +} + + +/*Gmac configuration functions*/ + +/** + * Enable the watchdog timer on the receiver. + * When enabled, Gmac enables Watchdog timer, and GMAC allows no more than + * 2048 bytes of data (10,240 if Jumbo frame enabled). + * @param[in] pointer to synopGMACdevice. + * \return returns void. + */ +void synopGMAC_wd_enable(synopGMACdevice *gmacdev) +{ + synopGMACClearBits(gmacdev->MacBase, GmacConfig, GmacWatchdog); + return; +} +/** + * Disable the watchdog timer on the receiver. + * When disabled, Gmac disabled watchdog timer, and can receive frames up to + * 16,384 bytes. + * @param[in] pointer to synopGMACdevice. + * \return returns void. + */ +void synopGMAC_wd_disable(synopGMACdevice *gmacdev) +{ + synopGMACSetBits(gmacdev->MacBase, GmacConfig, GmacWatchdog); + return; +} + +/** + * Enables the Jabber frame support. + * When enabled, GMAC disabled the jabber timer, and can transfer 16,384 byte frames. + * @param[in] pointer to synopGMACdevice. + * \return returns void. + */ +void synopGMAC_jab_enable(synopGMACdevice *gmacdev) +{ + synopGMACSetBits(gmacdev->MacBase, GmacConfig, GmacJabber); + return; +} +/** + * Disables the Jabber frame support. + * When disabled, GMAC enables jabber timer. It cuts of transmitter if application + * sends more than 2048 bytes of data (10240 if Jumbo frame enabled). + * @param[in] pointer to synopGMACdevice. + * \return returns void. + */ +void synopGMAC_jab_disable(synopGMACdevice *gmacdev) +{ + synopGMACClearBits(gmacdev->MacBase, GmacConfig, GmacJabber); + return; +} + +/** + * Enables Frame bursting (Only in Half Duplex Mode). + * When enabled, GMAC allows frame bursting in GMII Half Duplex mode. + * Reserved in 10/100 and Full-Duplex configurations. + * @param[in] pointer to synopGMACdevice. + * \return returns void. + */ +void synopGMAC_frame_burst_enable(synopGMACdevice *gmacdev) +{ + synopGMACSetBits(gmacdev->MacBase, GmacConfig, GmacFrameBurst); + return; +} +/** + * Disables Frame bursting. + * When Disabled, frame bursting is not supported. + * @param[in] pointer to synopGMACdevice. + * \return returns void. + */ +void synopGMAC_frame_burst_disable(synopGMACdevice *gmacdev) +{ + synopGMACClearBits(gmacdev->MacBase, GmacConfig, GmacFrameBurst); + return; +} + +/** + * Enable Jumbo frame support. + * When Enabled GMAC supports jumbo frames of 9018/9022(VLAN tagged). + * Giant frame error is not reported in receive frame status. + * @param[in] pointer to synopGMACdevice. + * \return returns void. + */ +void synopGMAC_jumbo_frame_enable(synopGMACdevice *gmacdev) +{ + synopGMACSetBits(gmacdev->MacBase, GmacConfig, GmacJumboFrame); + return; +} +/** + * Disable Jumbo frame support. + * When Disabled GMAC does not supports jumbo frames. + * Giant frame error is reported in receive frame status. + * @param[in] pointer to synopGMACdevice. + * \return returns void. + */ +void synopGMAC_jumbo_frame_disable(synopGMACdevice *gmacdev) +{ + synopGMACClearBits(gmacdev->MacBase, GmacConfig, GmacJumboFrame); + return; +} + +/** + * Disable Carrier sense. + * When Disabled GMAC ignores CRS signal during frame transmission + * in half duplex mode. + * @param[in] pointer to synopGMACdevice. + * \return void. + */ + +void synopGMAC_disable_crs(synopGMACdevice *gmacdev) +{ + synopGMACSetBits(gmacdev->MacBase, GmacConfig, GmacDisableCrs); + return; +} + + + +/** + * Selects the GMII port. + * When called GMII (1000Mbps) port is selected (programmable only in 10/100/1000 Mbps configuration). + * @param[in] pointer to synopGMACdevice. + * \return returns void. + */ +void synopGMAC_select_gmii(synopGMACdevice *gmacdev) +{ + synopGMACClearBits(gmacdev->MacBase, GmacConfig, GmacMiiGmii); + return; +} +/** + * Selects the MII port. + * When called MII (10/100Mbps) port is selected (programmable only in 10/100/1000 Mbps configuration). + * @param[in] pointer to synopGMACdevice. + * \return returns void. + */ +void synopGMAC_select_mii(synopGMACdevice *gmacdev) +{ + synopGMACSetBits(gmacdev->MacBase, GmacConfig, GmacMiiGmii); + return; +} + +/** + * Enables Receive Own bit (Only in Half Duplex Mode). + * When enaled GMAC receives all the packets given by phy while transmitting. + * @param[in] pointer to synopGMACdevice. + * \return returns void. + */ +void synopGMAC_rx_own_enable(synopGMACdevice *gmacdev) +{ + synopGMACClearBits(gmacdev->MacBase, GmacConfig, GmacRxOwn); + return; +} +/** + * Disables Receive Own bit (Only in Half Duplex Mode). + * When enaled GMAC disables the reception of frames when gmii_txen_o is asserted. + * @param[in] pointer to synopGMACdevice. + * \return returns void. + */ +void synopGMAC_rx_own_disable(synopGMACdevice *gmacdev) +{ + synopGMACSetBits(gmacdev->MacBase, GmacConfig, GmacRxOwn); + return; +} + +/** + * Sets the GMAC in loopback mode. + * When on GMAC operates in loop-back mode at GMII/MII. + * @param[in] pointer to synopGMACdevice. + * \return returns void. + * \note (G)MII Receive clock is required for loopback to work properly, as transmit clock is + * not looped back internally. + */ +void synopGMAC_loopback_on(synopGMACdevice *gmacdev) +{ + synopGMACSetBits(gmacdev->MacBase, GmacConfig, GmacLoopback); + return; +} +/** + * Sets the GMAC in Normal mode. + * @param[in] pointer to synopGMACdevice. + * \return returns void. + */ +void synopGMAC_loopback_off(synopGMACdevice *gmacdev) +{ + synopGMACClearBits(gmacdev->MacBase, GmacConfig, GmacLoopback); + return; +} + +/** + * Sets the GMAC core in Full-Duplex mode. + * @param[in] pointer to synopGMACdevice. + * \return returns void. + */ +void synopGMAC_set_full_duplex(synopGMACdevice *gmacdev) +{ + synopGMACSetBits(gmacdev->MacBase, GmacConfig, GmacDuplex); + return; +} +/** + * Sets the GMAC core in Half-Duplex mode. + * @param[in] pointer to synopGMACdevice. + * \return returns void. + */ +void synopGMAC_set_half_duplex(synopGMACdevice *gmacdev) +{ + synopGMACClearBits(gmacdev->MacBase, GmacConfig, GmacDuplex); + return; +} + +/** + * GMAC tries retransmission (Only in Half Duplex mode). + * If collision occurs on the GMII/MII, GMAC attempt retries based on the + * back off limit configured. + * @param[in] pointer to synopGMACdevice. + * \return returns void. + * \note This function is tightly coupled with synopGMAC_back_off_limit(synopGMACdev *, u32). + */ +void synopGMAC_retry_enable(synopGMACdevice *gmacdev) +{ + synopGMACClearBits(gmacdev->MacBase, GmacConfig, GmacRetry); + return; +} +/** + * GMAC tries only one transmission (Only in Half Duplex mode). + * If collision occurs on the GMII/MII, GMAC will ignore the current frami + * transmission and report a frame abort with excessive collision in tranmit frame status. + * @param[in] pointer to synopGMACdevice. + * \return returns void. + */ +void synopGMAC_retry_disable(synopGMACdevice *gmacdev) +{ + synopGMACSetBits(gmacdev->MacBase, GmacConfig, GmacRetry); + return; +} + +/** + * GMAC strips the Pad/FCS field of incoming frames. + * This is true only if the length field value is less than or equal to + * 1500 bytes. All received frames with length field greater than or equal to + * 1501 bytes are passed to the application without stripping the Pad/FCS field. + * @param[in] pointer to synopGMACdevice. + * \return returns void. + */ +void synopGMAC_pad_crc_strip_enable(synopGMACdevice *gmacdev) +{ + synopGMACSetBits(gmacdev->MacBase, GmacConfig, GmacPadCrcStrip); + return; +} +/** + * GMAC doesnot strips the Pad/FCS field of incoming frames. + * GMAC will pass all the incoming frames to Host unmodified. + * @param[in] pointer to synopGMACdevice. + * \return returns void. + */ +void synopGMAC_pad_crc_strip_disable(synopGMACdevice *gmacdev) +{ + u32 status; + synopGMACClearBits(gmacdev->MacBase, GmacConfig, GmacPadCrcStrip); + status = synopGMACReadReg(gmacdev->MacBase, GmacConfig); + if ((status & GmacPadCrcStrip)) + { + TR("strips status : %u\n", status & GmacPadCrcStrip); + } + return; +} +/** + * GMAC programmed with the back off limit value. + * @param[in] pointer to synopGMACdevice. + * \return returns void. + * \note This function is tightly coupled with synopGMAC_retry_enable(synopGMACdevice * gmacdev) + */ +void synopGMAC_back_off_limit(synopGMACdevice *gmacdev, u32 value) +{ + u32 data; + data = synopGMACReadReg(gmacdev->MacBase, GmacConfig); + data &= (~GmacBackoffLimit); + data |= value; + synopGMACWriteReg(gmacdev->MacBase, GmacConfig, data); + return; +} + +/** + * Enables the Deferral check in GMAC (Only in Half Duplex mode) + * GMAC issues a Frame Abort Status, along with the excessive deferral error bit set in the + * transmit frame status when transmit state machine is deferred for more than + * - 24,288 bit times in 10/100Mbps mode + * - 155,680 bit times in 1000Mbps mode or Jumbo frame mode in 10/100Mbps operation. + * @param[in] pointer to synopGMACdevice. + * \return returns void. + * \note Deferral begins when transmitter is ready to transmit, but is prevented because of + * an active CRS (carrier sense) + */ +void synopGMAC_deferral_check_enable(synopGMACdevice *gmacdev) +{ + synopGMACSetBits(gmacdev->MacBase, GmacConfig, GmacDeferralCheck); + return; +} +/** + * Disables the Deferral check in GMAC (Only in Half Duplex mode). + * GMAC defers until the CRS signal goes inactive. + * @param[in] pointer to synopGMACdevice. + * \return returns void. + */ +void synopGMAC_deferral_check_disable(synopGMACdevice *gmacdev) +{ + synopGMACClearBits(gmacdev->MacBase, GmacConfig, GmacDeferralCheck); + return; +} +/** + * Enable the reception of frames on GMII/MII. + * @param[in] pointer to synopGMACdevice. + * \return returns void. + */ +void synopGMAC_rx_enable(synopGMACdevice *gmacdev) +{ + synopGMACSetBits(gmacdev->MacBase, GmacConfig, GmacRx); + return; +} +/** + * Disable the reception of frames on GMII/MII. + * GMAC receive state machine is disabled after completion of reception of current frame. + * @param[in] pointer to synopGMACdevice. + * \return returns void. + */ +void synopGMAC_rx_disable(synopGMACdevice *gmacdev) +{ + synopGMACClearBits(gmacdev->MacBase, GmacConfig, GmacRx); + return; +} +/** + * Enable the transmission of frames on GMII/MII. + * @param[in] pointer to synopGMACdevice. + * \return returns void. + */ +void synopGMAC_tx_enable(synopGMACdevice *gmacdev) +{ + synopGMACSetBits(gmacdev->MacBase, GmacConfig, GmacTx); + return; +} +/** + * Disable the transmission of frames on GMII/MII. + * GMAC transmit state machine is disabled after completion of transmission of current frame. + * @param[in] pointer to synopGMACdevice. + * \return returns void. + */ +void synopGMAC_tx_disable(synopGMACdevice *gmacdev) +{ + synopGMACClearBits(gmacdev->MacBase, GmacConfig, GmacTx); + return; +} + + +/*Receive frame filter configuration functions*/ + +/** + * Enables reception of all the frames to application. + * GMAC passes all the frames received to application irrespective of whether they + * pass SA/DA address filtering or not. + * @param[in] pointer to synopGMACdevice. + * \return returns void. + */ +void synopGMAC_frame_filter_enable(synopGMACdevice *gmacdev) +{ + synopGMACClearBits(gmacdev->MacBase, GmacFrameFilter, GmacFilter); + return; +} +/** + * Disables reception of all the frames to application. + * GMAC passes only those received frames to application which + * pass SA/DA address filtering. + * @param[in] pointer to synopGMACdevice. + * \return void. + */ +void synopGMAC_frame_filter_disable(synopGMACdevice *gmacdev) +{ + synopGMACSetBits(gmacdev->MacBase, GmacFrameFilter, GmacFilter); + return; +} + +/** + * Populates the Hash High register with the data supplied. + * This function is called when the Hash filtering is to be enabled. + * @param[in] pointer to synopGMACdevice. + * @param[in] data to be written to hash table high register. + * \return void. + */ +void synopGMAC_write_hash_table_high(synopGMACdevice *gmacdev, u32 data) +{ + synopGMACWriteReg(gmacdev->MacBase, GmacHashHigh, data); + return; +} + +/** + * Populates the Hash Low register with the data supplied. + * This function is called when the Hash filtering is to be enabled. + * @param[in] pointer to synopGMACdevice. + * @param[in] data to be written to hash table low register. + * \return void. + */ +void synopGMAC_write_hash_table_low(synopGMACdevice *gmacdev, u32 data) +{ + synopGMACWriteReg(gmacdev->MacBase, GmacHashLow, data); + return; +} + +/** + * Enables Hash or Perfect filter (only if Hash filter is enabled in H/W). + * Only frames matching either perfect filtering or Hash Filtering as per HMC and HUC + * configuration are sent to application. + * @param[in] pointer to synopGMACdevice. + * \return void. + */ +void synopGMAC_hash_perfect_filter_enable(synopGMACdevice *gmacdev) +{ + synopGMACSetBits(gmacdev->MacBase, GmacFrameFilter, GmacHashPerfectFilter); + return; +} + +/** + * Enables only Hash(only if Hash filter is enabled in H/W). + * Only frames matching Hash Filtering as per HMC and HUC + * configuration are sent to application. + * @param[in] pointer to synopGMACdevice. + * \return void. + */ +void synopGMAC_Hash_filter_only_enable(synopGMACdevice *gmacdev) +{ + synopGMACSetBits(gmacdev->MacBase, GmacFrameFilter, GmacHashPerfectFilter); + return; +} + +/** + * Enables Source address filtering. + * When enabled source address filtering is performed. Only frames matching SA filtering are passed to application with + * SAMatch bit of RxStatus is set. GMAC drops failed frames. + * @param[in] pointer to synopGMACdevice. + * \return void. + * \note This function is overriden by synopGMAC_frame_filter_disable(synopGMACdevice *) + */ +void synopGMAC_src_addr_filter_enable(synopGMACdevice *gmacdev) +{ + synopGMACSetBits(gmacdev->MacBase, GmacFrameFilter, GmacSrcAddrFilter); + return; +} +/** + * Disables Source address filtering. + * When disabled GMAC forwards the received frames with updated SAMatch bit in RxStatus. + * @param[in] pointer to synopGMACdevice. + * \return void. + */ +void synopGMAC_src_addr_filter_disable(synopGMACdevice *gmacdev) +{ + synopGMACClearBits(gmacdev->MacBase, GmacFrameFilter, GmacSrcAddrFilter); + return; +} +/** + * Enables Inverse Destination address filtering. + * @param[in] pointer to synopGMACdevice. + * \return void. + */ +void synopGMAC_dst_addr_filter_inverse(synopGMACdevice *gmacdev) +{ + synopGMACSetBits(gmacdev->MacBase, GmacFrameFilter, GmacDestAddrFilterNor); + return; +} +/** + * Enables the normal Destination address filtering. + * @param[in] pointer to synopGMACdevice. + * \return void. + */ +void synopGMAC_dst_addr_filter_normal(synopGMACdevice *gmacdev) +{ + synopGMACClearBits(gmacdev->MacBase, GmacFrameFilter, GmacDestAddrFilterNor); + return; +} + +/** + * Enables forwarding of control frames. + * When set forwards all the control frames (incl. unicast and multicast PAUSE frames). + * @param[in] pointer to synopGMACdevice. + * \return void. + * \note Depends on RFE of FlowControlRegister[2] + */ +void synopGMAC_set_pass_control(synopGMACdevice *gmacdev, u32 passcontrol) +{ + u32 data; + data = synopGMACReadReg(gmacdev->MacBase, GmacFrameFilter); + data &= (~GmacPassControl); + data |= passcontrol; + synopGMACWriteReg(gmacdev->MacBase, GmacFrameFilter, data); + return; +} + +/** + * Enables Broadcast frames. + * When enabled Address filtering module passes all incoming broadcast frames. + * @param[in] pointer to synopGMACdevice. + * \return void. + */ +void synopGMAC_broadcast_enable(synopGMACdevice *gmacdev) +{ + synopGMACClearBits(gmacdev->MacBase, GmacFrameFilter, GmacBroadcast); + return; +} + +/** + * Disable Broadcast frames. + * When disabled Address filtering module filters all incoming broadcast frames. + * @param[in] pointer to synopGMACdevice. + * \return void. + */ +void synopGMAC_broadcast_disable(synopGMACdevice *gmacdev) +{ + synopGMACSetBits(gmacdev->MacBase, GmacFrameFilter, GmacBroadcast); + return; +} + +/** + * Enables Multicast frames. + * When enabled all multicast frames are passed. + * @param[in] pointer to synopGMACdevice. + * \return void. + */ +void synopGMAC_multicast_enable(synopGMACdevice *gmacdev) +{ + synopGMACSetBits(gmacdev->MacBase, GmacFrameFilter, GmacMulticastFilter); + return; +} +/** + * Disable Multicast frames. + * When disabled multicast frame filtering depends on HMC bit. + * @param[in] pointer to synopGMACdevice. + * \return void. + */ +void synopGMAC_multicast_disable(synopGMACdevice *gmacdev) +{ + synopGMACClearBits(gmacdev->MacBase, GmacFrameFilter, GmacMulticastFilter); + return; +} + +/** + * Enables multicast hash filtering. + * When enabled GMAC performs teh destination address filtering according to the hash table. + * @param[in] pointer to synopGMACdevice. + * \return void. + */ +void synopGMAC_multicast_hash_filter_enable(synopGMACdevice *gmacdev) +{ + synopGMACSetBits(gmacdev->MacBase, GmacFrameFilter, GmacMcastHashFilter); + return; +} +/** + * Disables multicast hash filtering. + * When disabled GMAC performs perfect destination address filtering for multicast frames, it compares + * DA field with the value programmed in DA register. + * @param[in] pointer to synopGMACdevice. + * \return void. + */ +void synopGMAC_multicast_hash_filter_disable(synopGMACdevice *gmacdev) +{ + synopGMACClearBits(gmacdev->MacBase, GmacFrameFilter, GmacMcastHashFilter); + return; +} + +/** + * Enables promiscous mode. + * When enabled Address filter modules pass all incoming frames regardless of their Destination + * and source addresses. + * @param[in] pointer to synopGMACdevice. + * \return void. + */ +void synopGMAC_promisc_enable(synopGMACdevice *gmacdev) +{ + synopGMACSetBits(gmacdev->MacBase, GmacFrameFilter, GmacPromiscuousMode); + return; +} +/** + * Clears promiscous mode. + * When called the GMAC falls back to normal operation from promiscous mode. + * @param[in] pointer to synopGMACdevice. + * \return void. + */ +void synopGMAC_promisc_disable(synopGMACdevice *gmacdev) +{ + synopGMACClearBits(gmacdev->MacBase, GmacFrameFilter, GmacPromiscuousMode); + return; +} + + +/** + * Enables unicast hash filtering. + * When enabled GMAC performs the destination address filtering of unicast frames according to the hash table. + * @param[in] pointer to synopGMACdevice. + * \return void. + */ +void synopGMAC_unicast_hash_filter_enable(synopGMACdevice *gmacdev) +{ + synopGMACSetBits(gmacdev->MacBase, GmacFrameFilter, GmacUcastHashFilter); + return; +} +/** + * Disables multicast hash filtering. + * When disabled GMAC performs perfect destination address filtering for unicast frames, it compares + * DA field with the value programmed in DA register. + * @param[in] pointer to synopGMACdevice. + * \return void. + */ +void synopGMAC_unicast_hash_filter_disable(synopGMACdevice *gmacdev) +{ + synopGMACClearBits(gmacdev->MacBase, GmacFrameFilter, GmacUcastHashFilter); + return; +} + +/*Flow control configuration functions*/ + +/** + * Enables detection of pause frames with stations unicast address. + * When enabled GMAC detects the pause frames with stations unicast address in addition to the + * detection of pause frames with unique multicast address. + * @param[in] pointer to synopGMACdevice. + * \return void. + */ +void synopGMAC_unicast_pause_frame_detect_enable(synopGMACdevice *gmacdev) +{ + synopGMACSetBits(gmacdev->MacBase, GmacFlowControl, GmacUnicastPauseFrame); + return; +} +/** + * Disables detection of pause frames with stations unicast address. + * When disabled GMAC only detects with the unique multicast address (802.3x). + * @param[in] pointer to synopGMACdevice. + * \return void. + */ +void synopGMAC_unicast_pause_frame_detect_disable(synopGMACdevice *gmacdev) +{ + synopGMACClearBits(gmacdev->MacBase, GmacFlowControl, GmacUnicastPauseFrame); + return; +} +/** + * Rx flow control enable. + * When Enabled GMAC will decode the rx pause frame and disable the tx for a specified time. + * @param[in] pointer to synopGMACdevice. + * \return void. + */ +void synopGMAC_rx_flow_control_enable(synopGMACdevice *gmacdev) +{ + synopGMACSetBits(gmacdev->MacBase, GmacFlowControl, GmacRxFlowControl); + return; +} +/** + * Rx flow control disable. + * When disabled GMAC will not decode pause frame. + * @param[in] pointer to synopGMACdevice. + * \return void. + */ +void synopGMAC_rx_flow_control_disable(synopGMACdevice *gmacdev) +{ + synopGMACClearBits(gmacdev->MacBase, GmacFlowControl, GmacRxFlowControl); + return; +} +/** + * Tx flow control enable. + * When Enabled + * - In full duplex GMAC enables flow control operation to transmit pause frames. + * - In Half duplex GMAC enables the back pressure operation + * @param[in] pointer to synopGMACdevice. + * \return void. + */ +void synopGMAC_tx_flow_control_enable(synopGMACdevice *gmacdev) +{ + synopGMACSetBits(gmacdev->MacBase, GmacFlowControl, GmacTxFlowControl); + return; +} + +/** + * Tx flow control disable. + * When Disabled + * - In full duplex GMAC will not transmit any pause frames. + * - In Half duplex GMAC disables the back pressure feature. + * @param[in] pointer to synopGMACdevice. + * \return void. + */ +void synopGMAC_tx_flow_control_disable(synopGMACdevice *gmacdev) +{ + synopGMACClearBits(gmacdev->MacBase, GmacFlowControl, GmacTxFlowControl); + return; +} + +/** + * Initiate Flowcontrol operation. + * When Set + * - In full duplex GMAC initiates pause control frame. + * - In Half duplex GMAC initiates back pressure function. + * @param[in] pointer to synopGMACdevice. + * \return void. + */ +void synopGMAC_tx_activate_flow_control(synopGMACdevice *gmacdev) +{ + //In case of full duplex check for this bit to b'0. if it is read as b'1 indicates that + //control frame transmission is in progress. + if (gmacdev->Speed == FULLDUPLEX) + { + if (!synopGMACCheckBits(gmacdev->MacBase, GmacFlowControl, GmacFlowControlBackPressure)) + synopGMACSetBits(gmacdev->MacBase, GmacFlowControl, GmacFlowControlBackPressure); + } + else //if half duplex mode + { + + synopGMACSetBits(gmacdev->MacBase, GmacFlowControl, GmacFlowControlBackPressure); + } + + return; +} + +/** + * stops Flowcontrol operation. + * @param[in] pointer to synopGMACdevice. + * \return void. + */ +void synopGMAC_tx_deactivate_flow_control(synopGMACdevice *gmacdev) +{ + //In full duplex this bit is automatically cleared after transmitting a pause control frame. + if (gmacdev->Speed == HALFDUPLEX) + { + synopGMACSetBits(gmacdev->MacBase, GmacFlowControl, GmacFlowControlBackPressure); + } + return; +} + +/** + * This enables the pause frame generation after programming the appropriate registers. + * presently activation is set at 3k and deactivation set at 4k. These may have to tweaked + * if found any issues + * @param[in] pointer to synopGMACdevice. + * \return void. + */ +void synopGMAC_pause_control(synopGMACdevice *gmacdev) +{ + u32 omr_reg; + u32 mac_flow_control_reg; + omr_reg = synopGMACReadReg(gmacdev->DmaBase, DmaControl); + omr_reg |= DmaRxFlowCtrlAct4K | DmaRxFlowCtrlDeact5K | DmaEnHwFlowCtrl; + synopGMACWriteReg(gmacdev->DmaBase, DmaControl, omr_reg); + + mac_flow_control_reg = synopGMACReadReg(gmacdev->MacBase, GmacFlowControl); + mac_flow_control_reg |= GmacRxFlowControl | GmacTxFlowControl | 0xFFFF0000; + synopGMACWriteReg(gmacdev->MacBase, GmacFlowControl, mac_flow_control_reg); + + return; + +} + +/** + * Example mac initialization sequence. + * This function calls the initialization routines to initialize the GMAC register. + * One can change the functions invoked here to have different configuration as per the requirement + * @param[in] pointer to synopGMACdevice. + * \return Returns 0 on success. + */ +s32 synopGMAC_mac_init(synopGMACdevice *gmacdev) +{ + u32 PHYreg; + + if (gmacdev->DuplexMode == FULLDUPLEX) + { + synopGMAC_wd_enable(gmacdev); + synopGMAC_jab_enable(gmacdev); + synopGMAC_frame_burst_enable(gmacdev); + synopGMAC_jumbo_frame_disable(gmacdev); + synopGMAC_rx_own_enable(gmacdev); + synopGMAC_loopback_off(gmacdev); + synopGMAC_set_full_duplex(gmacdev); + synopGMAC_retry_enable(gmacdev); + synopGMAC_pad_crc_strip_disable(gmacdev); + synopGMAC_back_off_limit(gmacdev, GmacBackoffLimit0); + synopGMAC_deferral_check_disable(gmacdev); + + + if (gmacdev->Speed == SPEED1000) + synopGMAC_select_gmii(gmacdev); + else + synopGMAC_select_mii(gmacdev); + + // Cannot enable tx/rx while changing Speed/mode. + synopGMAC_tx_enable(gmacdev); + synopGMAC_rx_enable(gmacdev); + /*Frame Filter Configuration*/ + synopGMAC_frame_filter_enable(gmacdev); + synopGMAC_set_pass_control(gmacdev, GmacPassControl0); + synopGMAC_broadcast_enable(gmacdev); + synopGMAC_src_addr_filter_disable(gmacdev); + synopGMAC_multicast_disable(gmacdev); + synopGMAC_dst_addr_filter_normal(gmacdev); + synopGMAC_multicast_hash_filter_disable(gmacdev); + synopGMAC_promisc_disable(gmacdev); + synopGMAC_unicast_hash_filter_disable(gmacdev); + + /*Flow Control Configuration*/ + synopGMAC_unicast_pause_frame_detect_disable(gmacdev); + synopGMAC_rx_flow_control_enable(gmacdev); + synopGMAC_tx_flow_control_enable(gmacdev); + } + else //for Half Duplex configuration + { + + synopGMAC_wd_enable(gmacdev); + synopGMAC_jab_enable(gmacdev); + synopGMAC_frame_burst_enable(gmacdev); + synopGMAC_jumbo_frame_disable(gmacdev); + synopGMAC_rx_own_enable(gmacdev); + synopGMAC_loopback_off(gmacdev); + synopGMAC_set_half_duplex(gmacdev); + synopGMAC_retry_enable(gmacdev); + synopGMAC_pad_crc_strip_disable(gmacdev); + synopGMAC_back_off_limit(gmacdev, GmacBackoffLimit0); + synopGMAC_deferral_check_disable(gmacdev); + + + if (gmacdev->Speed == SPEED1000) + synopGMAC_select_gmii(gmacdev); + else + synopGMAC_select_mii(gmacdev); + + synopGMAC_tx_enable(gmacdev); + synopGMAC_rx_enable(gmacdev); + /*Frame Filter Configuration*/ + synopGMAC_frame_filter_enable(gmacdev); + synopGMAC_set_pass_control(gmacdev, GmacPassControl0); + synopGMAC_broadcast_enable(gmacdev); + synopGMAC_src_addr_filter_disable(gmacdev); + synopGMAC_multicast_disable(gmacdev); + synopGMAC_dst_addr_filter_normal(gmacdev); + synopGMAC_multicast_hash_filter_disable(gmacdev); + synopGMAC_promisc_disable(gmacdev); + synopGMAC_unicast_hash_filter_disable(gmacdev); + + /*Flow Control Configuration*/ + synopGMAC_unicast_pause_frame_detect_disable(gmacdev); + synopGMAC_rx_flow_control_disable(gmacdev); + synopGMAC_tx_flow_control_disable(gmacdev); + + /*To set PHY register to enable CRS on Transmit*/ + synopGMACWriteReg(gmacdev->MacBase, GmacGmiiAddr, GmiiBusy | 0x00000408); + PHYreg = synopGMACReadReg(gmacdev->MacBase, GmacGmiiData); + synopGMACWriteReg(gmacdev->MacBase, GmacGmiiData, PHYreg | 0x00000800); + synopGMACWriteReg(gmacdev->MacBase, GmacGmiiAddr, GmiiBusy | 0x0000040a); + } + return 0; +} + +/** + * Sets the Mac address in to GMAC register. + * This function sets the MAC address to the MAC register in question. + * @param[in] pointer to synopGMACdevice to populate mac dma and phy addresses. + * @param[in] Register offset for Mac address high + * @param[in] Register offset for Mac address low + * @param[in] buffer containing mac address to be programmed. + * \return 0 upon success. Error code upon failure. + */ +s32 synopGMAC_set_mac_addr(synopGMACdevice *gmacdev, u32 MacHigh, u32 MacLow, u8 *MacAddr) +{ + u32 data; + + data = (MacAddr[5] << 8) | MacAddr[4]; + synopGMACWriteReg(gmacdev->MacBase, MacHigh, data); + data = (MacAddr[3] << 24) | (MacAddr[2] << 16) | (MacAddr[1] << 8) | MacAddr[0] ; + synopGMACWriteReg(gmacdev->MacBase, MacLow, data); + + return 0; +} + + +/** + * Get the Mac address in to the address specified. + * The mac register contents are read and written to buffer passed. + * @param[in] pointer to synopGMACdevice to populate mac dma and phy addresses. + * @param[in] Register offset for Mac address high + * @param[in] Register offset for Mac address low + * @param[out] buffer containing the device mac address. + * \return 0 upon success. Error code upon failure. + */ +s32 synopGMAC_get_mac_addr(synopGMACdevice *gmacdev, u32 MacHigh, u32 MacLow, u8 *MacAddr) +{ + u32 data; + + data = synopGMACReadReg(gmacdev->MacBase, MacHigh); + MacAddr[5] = (data >> 8) & 0xff; + MacAddr[4] = (data) & 0xff; + + data = synopGMACReadReg(gmacdev->MacBase, MacLow); + MacAddr[3] = (data >> 24) & 0xff; + MacAddr[2] = (data >> 16) & 0xff; + MacAddr[1] = (data >> 8) & 0xff; + MacAddr[0] = (data) & 0xff; + + return 0; +} +/** + * Attaches the synopGMAC device structure to the hardware. + * Device structure is populated with MAC/DMA and PHY base addresses. + * @param[in] pointer to synopGMACdevice to populate mac dma and phy addresses. + * @param[in] GMAC IP mac base address. + * @param[in] GMAC IP dma base address. + * @param[in] GMAC IP phy base address. + * \return 0 upon success. Error code upon failure. + * \note This is important function. No kernel api provided by Synopsys + */ +static s32 synopGMAC_scan_phyid(synopGMACdevice *gmacdev, u32 phyBase) +{ + int i, j; + u16 data; + + for (i = phyBase, j = 0; j < 32; i = (i + 1) & 0x1f, j++) + { + synopGMAC_read_phy_reg(gmacdev->MacBase, i, 2, &data); + if (data != 0 && data != 0xffff) break; + synopGMAC_read_phy_reg(gmacdev->MacBase, i, 3, &data); + if (data != 0 && data != 0xffff) break; + } + if (j == 32) + { + j = -1; + } + return j; +} + +s32 synopGMAC_attach(synopGMACdevice *gmacdev, u32 macBase, u32 dmaBase, u32 phyBase, u8 *mac_addr) +{ + /*Make sure the Device data strucure is cleared before we proceed further*/ + rt_memset((void *) gmacdev, 0, sizeof(synopGMACdevice)); + + /*Populate the mac and dma base addresses*/ + gmacdev->MacBase = macBase; + gmacdev->DmaBase = dmaBase; + gmacdev->PhyBase = phyBase; + + /* Program/flash in the station/IP's Mac address */ + //synopGMAC_set_mac_addr(gmacdev, GmacAddr0High, GmacAddr0Low, mac_addr); + + if (synopGMAC_scan_phyid(gmacdev, phyBase) < 0) + { + return -1; + } + + return 0; +} + + +/** + * Initialize the rx descriptors for ring or chain mode operation. + * - Status field is initialized to 0. + * - EndOfRing set for the last descriptor. + * - buffer1 and buffer2 set to 0 for ring mode of operation. (note) + * - data1 and data2 set to 0. (note) + * @param[in] pointer to DmaDesc structure. + * @param[in] whether end of ring + * \return void. + * \note Initialization of the buffer1, buffer2, data1,data2 and status are not done here. This only initializes whether one wants to use this descriptor + * in chain mode or ring mode. For chain mode of operation the buffer2 and data2 are programmed before calling this function. + */ +void synopGMAC_rx_desc_init_ring(DmaDesc *desc, bool last_ring_desc) +{ + desc->status = 0; + desc->length = last_ring_desc ? RxDescEndOfRing : 0; + desc->buffer1 = 0; + desc->buffer2 = 0; + //desc->data1 = 0; + //desc->data2 = 0; + return; +} +/** + * Initialize the tx descriptors for ring or chain mode operation. + * - Status field is initialized to 0. + * - EndOfRing set for the last descriptor. + * - buffer1 and buffer2 set to 0 for ring mode of operation. (note) + * - data1 and data2 set to 0. (note) + * @param[in] pointer to DmaDesc structure. + * @param[in] whether end of ring + * \return void. + * \note Initialization of the buffer1, buffer2, data1,data2 and status are not done here. This only initializes whether one wants to use this descriptor + * in chain mode or ring mode. For chain mode of operation the buffer2 and data2 are programmed before calling this function. + */ +void synopGMAC_tx_desc_init_ring(DmaDesc *desc, bool last_ring_desc) +{ + + desc->status = last_ring_desc ? TxDescEndOfRing : 0; + desc->length = 0; + + desc->buffer1 = 0; + desc->buffer2 = 0; + //desc->data1 = 0; + //desc->data2 = 0; + + return; +} + +s32 synopGMAC_init_tx_rx_desc_queue(synopGMACdevice *gmacdev) +{ + s32 i; + for (i = 0; i < gmacdev -> TxDescCount; i++) + { + synopGMAC_tx_desc_init_ring(gmacdev->TxDesc + i, i == gmacdev->TxDescCount - 1); + } + TR("At line %d\n", __LINE__); + for (i = 0; i < gmacdev -> RxDescCount; i++) + { + synopGMAC_rx_desc_init_ring(gmacdev->RxDesc + i, i == gmacdev->RxDescCount - 1); + } + + gmacdev->TxNext = 0; + gmacdev->TxBusy = 0; + gmacdev->RxNext = 0; + gmacdev->RxBusy = 0; + + return 0; +} + +/** + * Programs the DmaRxBaseAddress with the Rx descriptor base address. + * Rx Descriptor's base address is available in the gmacdev structure. This function progrms the + * Dma Rx Base address with the starting address of the descriptor ring or chain. + * @param[in] pointer to synopGMACdevice. + * \return returns void. + */ +void synopGMAC_init_rx_desc_base(synopGMACdevice *gmacdev) +{ + synopGMACWriteReg(gmacdev->DmaBase, DmaRxBaseAddr, (u32)gmacdev->RxDescDma); + return; +} + +/** + * Programs the DmaTxBaseAddress with the Tx descriptor base address. + * Tx Descriptor's base address is available in the gmacdev structure. This function progrms the + * Dma Tx Base address with the starting address of the descriptor ring or chain. + * @param[in] pointer to synopGMACdevice. + * \return returns void. + */ +void synopGMAC_init_tx_desc_base(synopGMACdevice *gmacdev) +{ + synopGMACWriteReg(gmacdev->DmaBase, DmaTxBaseAddr, (u32)gmacdev->TxDescDma); + return; +} + + +/** + * Checks whether the descriptor is owned by DMA. + * If descriptor is owned by DMA then the OWN bit is set to 1. This API is same for both ring and chain mode. + * @param[in] pointer to DmaDesc structure. + * \return returns true if Dma owns descriptor and false if not. + */ +bool synopGMAC_is_desc_owned_by_dma(DmaDesc *desc) +{ + return ((desc->status & DescOwnByDma) == DescOwnByDma); +} + +/** + * returns the byte length of received frame including CRC. + * This returns the no of bytes received in the received ethernet frame including CRC(FCS). + * @param[in] pointer to DmaDesc structure. + * \return returns the length of received frame lengths in bytes. + */ +u32 synopGMAC_get_rx_desc_frame_length(u32 status) +{ + return ((status & DescFrameLengthMask) >> DescFrameLengthShift); +} + +/** + * Checks whether the descriptor is valid + * if no errors such as CRC/Receive Error/Watchdog Timeout/Late collision/Giant Frame/Overflow/Descriptor + * error the descritpor is said to be a valid descriptor. + * @param[in] pointer to DmaDesc structure. + * \return True if desc valid. false if error. + */ +bool synopGMAC_is_desc_valid(u32 status) +{ + return ((status & DescError) == 0); +} + +/** + * Checks whether the descriptor is empty. + * If the buffer1 and buffer2 lengths are zero in ring mode descriptor is empty. + * In chain mode buffer2 length is 0 but buffer2 itself contains the next descriptor address. + * @param[in] pointer to DmaDesc structure. + * \return returns true if descriptor is empty, false if not empty. + */ +bool synopGMAC_is_desc_empty(DmaDesc *desc) +{ + //if both the buffer1 length and buffer2 length are zero desc is empty + return (((desc->length & DescSize1Mask) == 0) && ((desc->length & DescSize2Mask) == 0)); +} + + +/** + * Checks whether the rx descriptor is valid. + * if rx descripor is not in error and complete frame is available in the same descriptor + * @param[in] pointer to DmaDesc structure. + * \return returns true if no error and first and last desc bits are set, otherwise it returns false. + */ +bool synopGMAC_is_rx_desc_valid(u32 status) +{ + return ((status & DescError) == 0) && ((status & DescRxFirst) == DescRxFirst) && ((status & DescRxLast) == DescRxLast); +} + +/** + * Checks whether the tx is aborted due to collisions. + * @param[in] pointer to DmaDesc structure. + * \return returns true if collisions, else returns false. + */ +bool synopGMAC_is_tx_aborted(u32 status) +{ + return (((status & DescTxLateCollision) == DescTxLateCollision) | ((status & DescTxExcCollisions) == DescTxExcCollisions)); + +} + +/** + * Checks whether the tx carrier error. + * @param[in] pointer to DmaDesc structure. + * \return returns true if carrier error occured, else returns falser. + */ +bool synopGMAC_is_tx_carrier_error(u32 status) +{ + return (((status & DescTxLostCarrier) == DescTxLostCarrier) | ((status & DescTxNoCarrier) == DescTxNoCarrier)); +} + + +/** + * Gives the transmission collision count. + * returns the transmission collision count indicating number of collisions occured before the frame was transmitted. + * Make sure to check excessive collision didnot happen to ensure the count is valid. + * @param[in] pointer to DmaDesc structure. + * \return returns the count value of collision. + */ +u32 synopGMAC_get_tx_collision_count(u32 status) +{ + return ((status & DescTxCollMask) >> DescTxCollShift); +} +u32 synopGMAC_is_exc_tx_collisions(u32 status) +{ + return ((status & DescTxExcCollisions) == DescTxExcCollisions); +} + + +/** + * Check for damaged frame due to overflow or collision. + * Retruns true if rx frame was damaged due to buffer overflow in MTL or late collision in half duplex mode. + * @param[in] pointer to DmaDesc structure. + * \return returns true if error else returns false. + */ +bool synopGMAC_is_rx_frame_damaged(u32 status) +{ +//bool synopGMAC_dma_rx_collisions(u32 status) + return (((status & DescRxDamaged) == DescRxDamaged) | ((status & DescRxCollision) == DescRxCollision)); +} + +/** + * Check for damaged frame due to collision. + * Retruns true if rx frame was damaged due to late collision in half duplex mode. + * @param[in] pointer to DmaDesc structure. + * \return returns true if error else returns false. + */ +bool synopGMAC_is_rx_frame_collision(u32 status) +{ +//bool synopGMAC_dma_rx_collisions(u32 status) + return ((status & DescRxCollision) == DescRxCollision); +} + +/** + * Check for receive CRC error. + * Retruns true if rx frame CRC error occured. + * @param[in] pointer to DmaDesc structure. + * \return returns true if error else returns false. + */ +bool synopGMAC_is_rx_crc(u32 status) +{ +//u32 synopGMAC_dma_rx_crc(u32 status) + return ((status & DescRxCrc) == DescRxCrc); +} + +/** + * Indicates rx frame has non integer multiple of bytes. (odd nibbles). + * Retruns true if dribbling error in rx frame. + * @param[in] pointer to DmaDesc structure. + * \return returns true if error else returns false. + */ +bool synopGMAC_is_frame_dribbling_errors(u32 status) +{ +//u32 synopGMAC_dma_rx_frame_errors(u32 status) + return ((status & DescRxDribbling) == DescRxDribbling); +} + +/** + * Indicates error in rx frame length. + * Retruns true if received frame length doesnot match with the length field + * @param[in] pointer to DmaDesc structure. + * \return returns true if error else returns false. + */ +bool synopGMAC_is_rx_frame_length_errors(u32 status) +{ +//u32 synopGMAC_dma_rx_length_errors(u32 status) + return ((status & DescRxLengthError) == DescRxLengthError); +} + +/** + * Checks whether this rx descriptor is last rx descriptor. + * This returns true if it is last descriptor either in ring mode or in chain mode. + * @param[in] pointer to devic structure. + * @param[in] pointer to DmaDesc structure. + * \return returns true if it is last descriptor, false if not. + * \note This function should not be called before initializing the descriptor using synopGMAC_desc_init(). + */ +bool synopGMAC_is_last_rx_desc(synopGMACdevice *gmacdev, DmaDesc *desc) +{ +//bool synopGMAC_is_last_desc(DmaDesc *desc) + return (((desc->length & RxDescEndOfRing) == RxDescEndOfRing) /*|| ((u32)((u64)gmacdev->RxDesc & 0xFFFFFFFF) == desc->data2)*/); +} + +/** + * Checks whether this tx descriptor is last tx descriptor. + * This returns true if it is last descriptor either in ring mode or in chain mode. + * @param[in] pointer to devic structure. + * @param[in] pointer to DmaDesc structure. + * \return returns true if it is last descriptor, false if not. + * \note This function should not be called before initializing the descriptor using synopGMAC_desc_init(). + */ +bool synopGMAC_is_last_tx_desc(synopGMACdevice *gmacdev, DmaDesc *desc) +{ +//bool synopGMAC_is_last_desc(DmaDesc *desc) + + return (((desc->status & TxDescEndOfRing) == TxDescEndOfRing) /*|| ((u32)((u64)gmacdev->TxDesc & 0xFFFFFFFF) == desc->data2)*/); + +} + + +/** + * This function is defined two times. Once when the code is compiled for ENHANCED DESCRIPTOR SUPPORT and Once for Normal descriptor + * Get the index and address of Tx desc. + * This api is same for both ring mode and chain mode. + * This function tracks the tx descriptor the DMA just closed after the transmission of data from this descriptor is + * over. This returns the descriptor fields to the caller. + * @param[in] pointer to synopGMACdevice. + * @param[out] status field of the descriptor. + * @param[out] Dma-able buffer1 pointer. + * @param[out] length of buffer1 (Max is 2048). + * @param[out] virtual pointer for buffer1. + * @param[out] u32 data indicating whether the descriptor is in ring mode or chain mode. + * \return returns present tx descriptor index on success. Negative value if error. + */ +s32 synopGMAC_get_tx_qptr(synopGMACdevice *gmacdev, u32 *Status, u32 *Buffer1, u32 *Length1, u32 *Data1, u32 *Ext_Status, u32 *Time_Stamp_High, u32 *Time_Stamp_Low) +{ + u32 txover = gmacdev->TxBusy; +#ifdef CACHE_ON + DmaDesc *txdesc = (DmaDesc *)((u32)(gmacdev->TxBusyDesc) | UNCACHEABLE); +#else + DmaDesc *txdesc = gmacdev->TxBusyDesc; +#endif + if (synopGMAC_is_desc_owned_by_dma(txdesc)) + return -1; + if (synopGMAC_is_desc_empty(txdesc)) + return -1; + + (gmacdev->BusyTxDesc)--; //busy tx descriptor is reduced by one as it will be handed over to Processor now + + if (Status != 0) + *Status = txdesc->status; + + if (Ext_Status != 0) + *Ext_Status = txdesc->extstatus; + if (Time_Stamp_High != 0) + *Time_Stamp_High = txdesc->timestamphigh; + if (Time_Stamp_Low != 0) + *Time_Stamp_Low = txdesc->timestamplow; + + if (Buffer1 != 0) + *Buffer1 = txdesc->buffer1; + if (Length1 != 0) + *Length1 = (txdesc->length & DescSize1Mask) >> DescSize1Shift; + //if(Data1 != 0) + // *Data1 = txdesc->data1; + + + gmacdev->TxBusy = synopGMAC_is_last_tx_desc(gmacdev, txdesc) ? 0 : txover + 1; + + if (1 /* ring mode */) + { + gmacdev->TxBusyDesc = synopGMAC_is_last_tx_desc(gmacdev, txdesc) ? gmacdev->TxDesc : (txdesc + 1); + synopGMAC_tx_desc_init_ring(txdesc, synopGMAC_is_last_tx_desc(gmacdev, txdesc)); + } +// TR("%02d %08x %08x %08x %08x %08x %08x %08x\n", txover, (u32)txdesc, txdesc->status, txdesc->length, txdesc->buffer1, txdesc->buffer2, txdesc->data1, txdesc->data2); + TR("%02d %08x %08x %08x %08x %08x\n", txover, (u32)txdesc, txdesc->status, txdesc->length, txdesc->buffer1, txdesc->buffer2); + + return txover; +} + +DmaDesc *prevtx; +void synopGMAC_set_crc_replacement(synopGMACdevice *gmacdev) +{ +#ifdef CACHE_ON + DmaDesc *txdesc = (DmaDesc *)((u32)(gmacdev->TxNextDesc) | UNCACHEABLE); +#else + DmaDesc *txdesc = gmacdev->TxNextDesc; +#endif + txdesc->status |= DescTxDisableCrc | DescTxCrcReplacement; + + prevtx = txdesc; +} + +void synopGMAC_clr_crc_replacement(synopGMACdevice *gmacdev) +{ + prevtx->status &= ~(DescTxDisableCrc | DescTxCrcReplacement); + prevtx = NULL; +} + +/** + * Populate the tx desc structure with the buffer address. + * Once the driver has a packet ready to be transmitted, this function is called with the + * valid dma-able buffer addresses and their lengths. This function populates the descriptor + * and make the DMA the owner for the descriptor. This function also controls whetther Checksum + * offloading to be done in hardware or not. + * This api is same for both ring mode and chain mode. + * @param[in] pointer to synopGMACdevice. + * @param[in] Dma-able buffer1 pointer. + * @param[in] length of buffer1 (Max is 2048). + * @param[in] virtual pointer for buffer1. + + * @param[in] u32 data indicating whether the descriptor is in ring mode or chain mode. + * @param[in] u32 indicating whether the checksum offloading in HW/SW. + * \return returns present tx descriptor index on success. Negative value if error. + */ +s32 synopGMAC_set_tx_qptr(synopGMACdevice *gmacdev, u32 Buffer1, u32 Length1, u32 Data1, u32 offload_needed, u32 ts) +{ + u32 txnext = gmacdev->TxNext; +#ifdef CACHE_ON + DmaDesc *txdesc = (DmaDesc *)((u32)(gmacdev->TxNextDesc) | UNCACHEABLE); +#else + DmaDesc *txdesc = gmacdev->TxNextDesc; +#endif + if (!synopGMAC_is_desc_empty(txdesc)) + return -1; + + (gmacdev->BusyTxDesc)++; //busy tx descriptor is incremented by one as it will be handed over to DMA + + txdesc->length |= ((Length1 << DescSize1Shift) & DescSize1Mask); + + txdesc->status |= (DescTxFirst | DescTxLast | DescTxIntEnable | (ts == 1 ? DescTxTSEnable : 0)); //ENH_DESC // FIXME: Need to set DescTxTSEnable? + + txdesc->buffer1 = Buffer1; + //txdesc->data1 = Data1; + + if (offload_needed) + { + /* + Make sure that the OS you are running supports the IP and TCP checkusm offloaidng, + before calling any of the functions given below. + */ + + //TODO: + synopGMAC_tx_checksum_offload_ipv4hdr(gmacdev, txdesc); + synopGMAC_tx_checksum_offload_tcponly(gmacdev, txdesc); + synopGMAC_tx_checksum_offload_tcp_pseudo(gmacdev, txdesc); + } + else + { + synopGMAC_tx_checksum_offload_bypass(gmacdev, txdesc); + } + + txdesc->status |= DescOwnByDma;//ENH_DESC + + gmacdev->TxNext = synopGMAC_is_last_tx_desc(gmacdev, txdesc) ? 0 : txnext + 1; + gmacdev->TxNextDesc = synopGMAC_is_last_tx_desc(gmacdev, txdesc) ? gmacdev->TxDesc : (txdesc + 1); + + TR("(set)%02d %08x %08x %08x %08x %08x\n", txnext, (u32)txdesc, txdesc->status, txdesc->length, txdesc->buffer1, txdesc->buffer2); + //rt_kprintf("(set)%02d %08x %08x %08x %08x %08x\n", txnext, (u32)txdesc, txdesc->status, txdesc->length, txdesc->buffer1, txdesc->buffer2); + return txnext; +} + +/** + * Prepares the descriptor to receive packets. + * The descriptor is allocated with the valid buffer addresses (sk_buff address) and the length fields + * and handed over to DMA by setting the ownership. After successful return from this function the + * descriptor is added to the receive descriptor pool/queue. + * This api is same for both ring mode and chain mode. + * @param[in] pointer to synopGMACdevice. + * @param[in] Dma-able buffer1 pointer. + * @param[in] length of buffer1 (Max is 2048). + * @param[in] Dma-able buffer2 pointer. + * @param[in] length of buffer2 (Max is 2048). + * @param[in] u32 data indicating whether the descriptor is in ring mode or chain mode. + * \return returns present rx descriptor index on success. Negative value if error. + */ +s32 synopGMAC_set_rx_qptr(synopGMACdevice *gmacdev, u32 Buffer1, u32 Length1, u32 Data1) +{ + u32 rxnext = gmacdev->RxNext; +#ifdef CACHE_ON + DmaDesc *rxdesc = (DmaDesc *)((u32)(gmacdev->RxNextDesc) | UNCACHEABLE); +#else + DmaDesc *rxdesc = gmacdev->RxNextDesc; +#endif + if (!synopGMAC_is_desc_empty(rxdesc)) + { + return -1; + } + + rxdesc->length |= ((Length1 << DescSize1Shift) & DescSize1Mask); + + rxdesc->buffer1 = Buffer1; + //rxdesc->data1 = Data1; + + rxdesc->extstatus = 0; + rxdesc->reserved1 = 0; + rxdesc->timestamplow = 0; + rxdesc->timestamphigh = 0; + + rxdesc->buffer2 = 0; + //rxdesc->data2 = 0; + + if ((rxnext % MODULO_INTERRUPT) != 0) + rxdesc->length |= RxDisIntCompl; + + rxdesc->status = DescOwnByDma; + + gmacdev->RxNext = synopGMAC_is_last_rx_desc(gmacdev, rxdesc) ? 0 : rxnext + 1; + gmacdev->RxNextDesc = synopGMAC_is_last_rx_desc(gmacdev, rxdesc) ? gmacdev->RxDesc : (rxdesc + 1); + +// TR("%02d %08x %08x %08x %08x %08x %08x %08x\n", rxnext, (u32)rxdesc, rxdesc->status, rxdesc->length, rxdesc->buffer1, rxdesc->buffer2, rxdesc->data1, rxdesc->data2); + TR("%02d %08x %08x %08x %08x %08x\n", rxnext, (u32)rxdesc, rxdesc->status, rxdesc->length, rxdesc->buffer1, rxdesc->buffer2); + + (gmacdev->BusyRxDesc)++; //One descriptor will be given to Hardware. So busy count incremented by one + return rxnext; +} + + +/** + * This function is defined two times. Once when the code is compiled for ENHANCED DESCRIPTOR SUPPORT and Once for Normal descriptor + * Get back the descriptor from DMA after data has been received. + * When the DMA indicates that the data is received (interrupt is generated), this function should be + * called to get the descriptor and hence the data buffers received. With successful return from this + * function caller gets the descriptor fields for processing. check the parameters to understand the + * fields returned.` + * @param[in] pointer to synopGMACdevice. + * @param[out] pointer to hold the status of DMA. + * @param[out] Dma-able buffer1 pointer. + * @param[out] pointer to hold length of buffer1 (Max is 2048). + * @param[out] virtual pointer for buffer1. + * \return returns present rx descriptor index on success. Negative value if error. + */ + +s32 synopGMAC_get_rx_qptr(synopGMACdevice *gmacdev, u32 *Status, u32 *Buffer1, u32 *Length1, u32 *Data1, + u32 *Ext_Status, u32 *Time_Stamp_High, u32 *Time_Stamp_Low) +{ + u32 rxnext = gmacdev->RxBusy; // index of descriptor the DMA just completed. May be useful when data + //is spread over multiple buffers/descriptors +#ifdef CACHE_ON + DmaDesc *rxdesc = (DmaDesc *)((u32)(gmacdev->RxBusyDesc) | UNCACHEABLE); +#else + DmaDesc *rxdesc = gmacdev->RxBusyDesc; +#endif + if (synopGMAC_is_desc_owned_by_dma(rxdesc)) + return -1; + + if (synopGMAC_is_desc_empty(rxdesc)) + return -1; + + if (Status != 0) + *Status = rxdesc->status;// send the status of this descriptor + + if (Ext_Status != 0) + *Ext_Status = rxdesc->extstatus; + + if (Time_Stamp_High != 0) + *Time_Stamp_High = rxdesc->timestamphigh; + + if (Time_Stamp_Low != 0) + *Time_Stamp_Low = rxdesc->timestamplow; + + if (Length1 != 0) + *Length1 = (rxdesc->length & DescSize1Mask) >> DescSize1Shift; + + if (Buffer1 != 0) + *Buffer1 = rxdesc->buffer1; + + //if(Data1 != 0) + // *Data1 = rxdesc->data1; + + gmacdev->RxBusy = synopGMAC_is_last_rx_desc(gmacdev, rxdesc) ? 0 : rxnext + 1; + + /* Ring */ + gmacdev->RxBusyDesc = synopGMAC_is_last_rx_desc(gmacdev, rxdesc) ? gmacdev->RxDesc : (rxdesc + 1); + + /* Wayne's modification */ + synopGMAC_rx_desc_init_ring(rxdesc, synopGMAC_is_last_rx_desc(gmacdev, rxdesc)); + // why init here.... should change onwer to DMA --ya + //rxdesc->status = DescOwnByDma; + //rxdesc->extstatus = 0; + //rxdesc->reserved1 = 0; + //rxdesc->timestamplow = 0; + //rxdesc->timestamphigh = 0; + TR("%02d %08x %08x %08x %08x %08x\n", rxnext, (u32)rxdesc, rxdesc->status, rxdesc->length, rxdesc->buffer1, rxdesc->buffer2); + + TR("%02d %08x %08x %08x %08x %08x\n", rxnext, (u32)rxdesc, rxdesc->status, rxdesc->length, rxdesc->buffer1, rxdesc->buffer2); + (gmacdev->BusyRxDesc)--; //busy tx descriptor is reduced by one as it will be handed over to Processor now + return (rxnext); + +} + + +/** + * Clears all the pending interrupts. + * If the Dma status register is read then all the interrupts gets cleared + * @param[in] pointer to synopGMACdevice. + * \return returns void. + */ +void synopGMAC_clear_interrupt(synopGMACdevice *gmacdev) +{ + u32 data; + data = synopGMACReadReg(gmacdev->DmaBase, DmaStatus); + synopGMACWriteReg(gmacdev->DmaBase, DmaStatus, data); +} + +/** + * Returns the all unmasked interrupt status after reading the DmaStatus register. + * @param[in] pointer to synopGMACdevice. + * \return 0 upon success. Error code upon failure. + */ +u32 synopGMAC_get_interrupt_type(synopGMACdevice *gmacdev) +{ + u32 data; + u32 interrupts = 0; + data = synopGMACReadReg(gmacdev->DmaBase, DmaStatus); + synopGMACWriteReg(gmacdev->DmaBase, DmaStatus, data); //This is the appropriate location to clear the interrupts + //TR("DMA status reg is %08x\n", data); + if (data & DmaIntErrorMask) interrupts |= synopGMACDmaError; + if (data & DmaIntRxNormMask) interrupts |= synopGMACDmaRxNormal; + if (data & DmaIntRxAbnMask) interrupts |= synopGMACDmaRxAbnormal; + if (data & DmaIntRxStoppedMask) interrupts |= synopGMACDmaRxStopped; + if (data & DmaIntTxNormMask) interrupts |= synopGMACDmaTxNormal; + if (data & DmaIntTxAbnMask) interrupts |= synopGMACDmaTxAbnormal; + if (data & DmaIntTxStoppedMask) interrupts |= synopGMACDmaTxStopped; + + return interrupts; +} + + +/** + * Enable all the interrupts. + * Enables the DMA interrupt as specified by the bit mask. + * @param[in] pointer to synopGMACdevice. + * @param[in] bit mask of interrupts to be enabled. + * \return returns void. + */ +void synopGMAC_enable_interrupt(synopGMACdevice *gmacdev, u32 interrupts) +{ + synopGMACWriteReg(gmacdev->DmaBase, DmaInterrupt, interrupts); + return; +} + +void synopGMAC_get_ie(synopGMACdevice *gmacdev) +{ + synopGMACReadReg(gmacdev->DmaBase, DmaInterrupt); + return; +} + +/** + * Disable all the interrupts. + * Disables all DMA interrupts. + * @param[in] pointer to synopGMACdevice. + * \return returns void. + * \note This function disabled all the interrupts, if you want to disable a particular interrupt then + * use synopGMAC_disable_interrupt(). + */ +void synopGMAC_disable_interrupt_all(synopGMACdevice *gmacdev) +{ + synopGMACWriteReg(gmacdev->DmaBase, DmaInterrupt, DmaIntDisable); + return; +} + +/** + * Disable interrupt according to the bitfield supplied. + * Disables only those interrupts specified in the bit mask in second argument. + * @param[in] pointer to synopGMACdevice. + * @param[in] bit mask for interrupts to be disabled. + * \return returns void. + */ +void synopGMAC_disable_interrupt(synopGMACdevice *gmacdev, u32 interrupts) +{ + synopGMACClearBits(gmacdev->DmaBase, DmaInterrupt, interrupts); + return; +} +/** + * Enable the DMA Reception. + * @param[in] pointer to synopGMACdevice. + * \return returns void. + */ +void synopGMAC_enable_dma_rx(synopGMACdevice *gmacdev) +{ +// synopGMACSetBits(gmacdev->DmaBase, DmaControl, DmaRxStart); + u32 data; + data = synopGMACReadReg(gmacdev->DmaBase, DmaControl); + data |= DmaRxStart; + synopGMACWriteReg(gmacdev->DmaBase, DmaControl, data); + +} + +/** + * Enable the DMA Transmission. + * @param[in] pointer to synopGMACdevice. + * \return returns void. + */ +void synopGMAC_enable_dma_tx(synopGMACdevice *gmacdev) +{ +// synopGMACSetBits(gmacdev->DmaBase, DmaControl, DmaTxStart); + u32 data; + data = synopGMACReadReg(gmacdev->DmaBase, DmaControl); + data |= DmaTxStart; + synopGMACWriteReg(gmacdev->DmaBase, DmaControl, data); + +} + +void synopGMAC_enable_under_size_pkt(synopGMACdevice *gmacdev) +{ + u32 data; + data = synopGMACReadReg(gmacdev->DmaBase, DmaControl); + data |= DmaFwdUnderSzFrames; + synopGMACWriteReg(gmacdev->DmaBase, DmaControl, data); + +} + +void synopGMAC_disable_under_size_pkt(synopGMACdevice *gmacdev) +{ + u32 data; + data = synopGMACReadReg(gmacdev->DmaBase, DmaControl); + data &= ~DmaFwdUnderSzFrames; + synopGMACWriteReg(gmacdev->DmaBase, DmaControl, data); + +} + +void synopGMAC_enable_crc_err_pkt(synopGMACdevice *gmacdev) +{ + u32 data; + data = synopGMACReadReg(gmacdev->DmaBase, DmaControl); + data |= DmaFwdErrorFrames; + synopGMACWriteReg(gmacdev->DmaBase, DmaControl, data); + +} + +void synopGMAC_disable_crc_err_pkt(synopGMACdevice *gmacdev) +{ + u32 data; + data = synopGMACReadReg(gmacdev->DmaBase, DmaControl); + data &= ~DmaFwdErrorFrames; + synopGMACWriteReg(gmacdev->DmaBase, DmaControl, data); + +} + + +/** + * Resumes the DMA Transmission. + * the DmaTxPollDemand is written. (the data writeen could be anything). + * This forces the DMA to resume transmission. + * @param[in] pointer to synopGMACdevice. + * \return returns void. + */ +void synopGMAC_resume_dma_tx(synopGMACdevice *gmacdev) +{ + synopGMACWriteReg(gmacdev->DmaBase, DmaTxPollDemand, 0); + +} +/** + * Resumes the DMA Reception. + * the DmaRxPollDemand is written. (the data writeen could be anything). + * This forces the DMA to resume reception. + * @param[in] pointer to synopGMACdevice. + * \return returns void. + */ +void synopGMAC_resume_dma_rx(synopGMACdevice *gmacdev) +{ + synopGMACWriteReg(gmacdev->DmaBase, DmaRxPollDemand, 0); + +} +/** + * Take ownership of this Descriptor. + * The function is same for both the ring mode and the chain mode DMA structures. + * @param[in] pointer to synopGMACdevice. + * \return returns void. + */ +void synopGMAC_take_desc_ownership(DmaDesc *desc) +{ + if (desc) + { + desc->status &= ~DescOwnByDma; //Clear the DMA own bit +// desc->status |= DescError; // Set the error to indicate this descriptor is bad + } +} + +/** + * Take ownership of all the rx Descriptors. + * This function is called when there is fatal error in DMA transmission. + * When called it takes the ownership of all the rx descriptor in rx descriptor pool/queue from DMA. + * The function is same for both the ring mode and the chain mode DMA structures. + * @param[in] pointer to synopGMACdevice. + * \return returns void. + * \note Make sure to disable the transmission before calling this function, otherwise may result in racing situation. + */ +void synopGMAC_take_desc_ownership_rx(synopGMACdevice *gmacdev) +{ + s32 i; + DmaDesc *desc; + desc = gmacdev->RxDesc; + for (i = 0; i < gmacdev->RxDescCount; i++) + { + synopGMAC_take_desc_ownership(desc + i); + } +} + +/** + * Take ownership of all the rx Descriptors. + * This function is called when there is fatal error in DMA transmission. + * When called it takes the ownership of all the tx descriptor in tx descriptor pool/queue from DMA. + * The function is same for both the ring mode and the chain mode DMA structures. + * @param[in] pointer to synopGMACdevice. + * \return returns void. + * \note Make sure to disable the transmission before calling this function, otherwise may result in racing situation. + */ +void synopGMAC_take_desc_ownership_tx(synopGMACdevice *gmacdev) +{ + s32 i; + DmaDesc *desc; + desc = gmacdev->TxDesc; + for (i = 0; i < gmacdev->TxDescCount; i++) + { + synopGMAC_take_desc_ownership(desc + i); + } + +} + +/** + * Disable the DMA for Transmission. + * @param[in] pointer to synopGMACdevice. + * \return returns void. + */ + +void synopGMAC_disable_dma_tx(synopGMACdevice *gmacdev) +{ +// synopGMACClearBits(gmacdev->DmaBase, DmaControl, DmaTxStart); + u32 data; + data = synopGMACReadReg(gmacdev->DmaBase, DmaControl); + data &= (~DmaTxStart); + synopGMACWriteReg(gmacdev->DmaBase, DmaControl, data); +} +/** + * Disable the DMA for Reception. + * @param[in] pointer to synopGMACdevice. + * \return returns void. + */ +void synopGMAC_disable_dma_rx(synopGMACdevice *gmacdev) +{ +// synopGMACClearBits(gmacdev->DmaBase, DmaControl, DmaRxStart); + u32 data; + data = synopGMACReadReg(gmacdev->DmaBase, DmaControl); + data &= (~DmaRxStart); + synopGMACWriteReg(gmacdev->DmaBase, DmaControl, data); +} + + + +/*******************PMT APIs***************************************/ + + + + +/** + * Enables the assertion of PMT interrupt. + * This enables the assertion of PMT interrupt due to Magic Pkt or Wakeup frame + * reception. + * @param[in] pointer to synopGMACdevice. + * \return returns void. + */ +void synopGMAC_pmt_int_enable(synopGMACdevice *gmacdev) +{ + synopGMACClearBits(gmacdev->MacBase, GmacInterruptMask, GmacPmtIntMask); + return; +} +/** + * Disables the assertion of PMT interrupt. + * This disables the assertion of PMT interrupt due to Magic Pkt or Wakeup frame + * reception. + * @param[in] pointer to synopGMACdevice. + * \return returns void. + */ +void synopGMAC_pmt_int_disable(synopGMACdevice *gmacdev) +{ + synopGMACSetBits(gmacdev->MacBase, GmacInterruptMask, GmacPmtIntMask); + return; +} +/** + * Enables the power down mode of GMAC. + * This function puts the Gmac in power down mode. + * @param[in] pointer to synopGMACdevice. + * \return returns void. + */ +void synopGMAC_power_down_enable(synopGMACdevice *gmacdev) +{ + synopGMACSetBits(gmacdev->MacBase, GmacPmtCtrlStatus, GmacPmtPowerDown); + return; +} +/** + * Disables the powerd down setting of GMAC. + * If the driver wants to bring up the GMAC from powerdown mode, even though the magic packet or the + * wake up frames received from the network, this function should be called. + * @param[in] pointer to synopGMACdevice. + * \return returns void. + */ +void synopGMAC_power_down_disable(synopGMACdevice *gmacdev) +{ + synopGMACClearBits(gmacdev->MacBase, GmacPmtCtrlStatus, GmacPmtPowerDown); + return; +} +/** + * Enables the pmt interrupt generation in powerdown mode. + * @param[in] pointer to synopGMACdevice. + * \return returns void. + */ +void synopGMAC_enable_pmt_interrupt(synopGMACdevice *gmacdev) +{ + synopGMACClearBits(gmacdev->MacBase, GmacInterruptMask, GmacPmtIntMask); +} +/** + * Disables the pmt interrupt generation in powerdown mode. + * @param[in] pointer to synopGMACdevice. + * \return returns void. + */ +void synopGMAC_disable_pmt_interrupt(synopGMACdevice *gmacdev) +{ + synopGMACSetBits(gmacdev->MacBase, GmacInterruptMask, GmacPmtIntMask); +} +/** + * Enables GMAC to look for Magic packet. + * @param[in] pointer to synopGMACdevice. + * \return returns void. + */ +void synopGMAC_magic_packet_enable(synopGMACdevice *gmacdev) +{ + synopGMACSetBits(gmacdev->MacBase, GmacPmtCtrlStatus, GmacPmtMagicPktEnable); + return; +} + +void synopGMAC_magic_packet_disable(synopGMACdevice *gmacdev) +{ + synopGMACClearBits(gmacdev->MacBase, GmacPmtCtrlStatus, GmacPmtMagicPktEnable); + return; +} + +/** + * Enables GMAC to look for wake up frame. + * Wake up frame is defined by the user. + * @param[in] pointer to synopGMACdevice. + * \return returns void. + */ +void synopGMAC_wakeup_frame_enable(synopGMACdevice *gmacdev) +{ + synopGMACSetBits(gmacdev->MacBase, GmacPmtCtrlStatus, GmacPmtWakeupFrameEnable); + return; +} + +/** + * Enables wake-up frame filter to handle unicast packets. + * @param[in] pointer to synopGMACdevice. + * \return returns void. + */ +void synopGMAC_pmt_unicast_enable(synopGMACdevice *gmacdev) +{ + synopGMACSetBits(gmacdev->MacBase, GmacPmtCtrlStatus, GmacPmtGlobalUnicast); + return; +} +/** + * Checks whether the packet received is a magic packet?. + * @param[in] pointer to synopGMACdevice. + * \return returns True if magic packet received else returns false. + */ +bool synopGMAC_is_magic_packet_received(synopGMACdevice *gmacdev) +{ + u32 data; + data = synopGMACReadReg(gmacdev->MacBase, GmacPmtCtrlStatus); + return ((data & GmacPmtMagicPktReceived) == GmacPmtMagicPktReceived); +} +/** + * Checks whether the packet received is a wakeup frame?. + * @param[in] pointer to synopGMACdevice. + * \return returns true if wakeup frame received else returns false. + */ +bool synopGMAC_is_wakeup_frame_received(synopGMACdevice *gmacdev) +{ + u32 data; + data = synopGMACReadReg(gmacdev->MacBase, GmacPmtCtrlStatus); + return ((data & GmacPmtWakeupFrameReceived) == GmacPmtWakeupFrameReceived); +} + +/** + * Populates the remote wakeup frame registers. + * Consecutive 8 writes to GmacWakeupAddr writes the wakeup frame filter registers. + * Before commensing a new write, frame filter pointer is reset to 0x0000. + * A small delay is introduced to allow frame filter pointer reset operation. + * @param[in] pointer to synopGMACdevice. + * @param[in] pointer to frame filter contents array. + * \return returns void. + */ +#if 0 +void synopGMAC_write_wakeup_frame_register(synopGMACdevice *gmacdev, u32 *filter_contents) +{ + s32 i; + synopGMACSetBits(gmacdev->MacBase, GmacPmtCtrlStatus, GmacPmtFrmFilterPtrReset); + plat_delay(10); + for (i = 0; i < WAKEUP_REG_LENGTH; i++) + synopGMACWriteReg(gmacdev->MacBase, GmacWakeupAddr, *(filter_contents + i)); + return; + +} +#endif +/*******************PMT APIs***************************************/ + +/*******************Ip checksum offloading APIs***************************************/ + +/** + * Enables the ip checksum offloading in receive path. + * When set GMAC calculates 16 bit 1's complement of all received ethernet frame payload. + * It also checks IPv4 Header checksum is correct. GMAC core appends the 16 bit checksum calculated + * for payload of IP datagram and appends it to Ethernet frame transferred to the application. + * @param[in] pointer to synopGMACdevice. + * \return returns void. + */ +void synopGMAC_enable_rx_chksum_offload(synopGMACdevice *gmacdev) +{ + synopGMACSetBits(gmacdev->MacBase, GmacConfig, GmacRxIpcOffload); + return; +} +/** + * Disable the ip checksum offloading in receive path. + * Ip checksum offloading is disabled in the receive path. + * @param[in] pointer to synopGMACdevice. + * \return returns void. + */ +void synopGMAC_disable_rx_chksum_offload(synopGMACdevice *gmacdev) +{ + synopGMACClearBits(gmacdev->MacBase, GmacConfig, GmacRxIpcOffload); +} +/** + * Instruct the DMA to drop the packets fails tcp ip checksum. + * This is to instruct the receive DMA engine to drop the recevied packet if they + * fails the tcp/ip checksum in hardware. Valid only when full checksum offloading is enabled(type-2). + * @param[in] pointer to synopGMACdevice. + * \return returns void. + */ +void synopGMAC_rx_tcpip_chksum_drop_enable(synopGMACdevice *gmacdev) +{ + synopGMACClearBits(gmacdev->DmaBase, DmaControl, DmaDisableDropTcpCs); + return; +} +/** + * Instruct the DMA not to drop the packets even if it fails tcp ip checksum. + * This is to instruct the receive DMA engine to allow the packets even if recevied packet + * fails the tcp/ip checksum in hardware. Valid only when full checksum offloading is enabled(type-2). + * @param[in] pointer to synopGMACdevice. + * \return returns void. + */ +void synopGMAC_rx_tcpip_chksum_drop_disable(synopGMACdevice *gmacdev) +{ + synopGMACSetBits(gmacdev->DmaBase, DmaControl, DmaDisableDropTcpCs); + return; +} + +/** + * When the Enhanced Descriptor is enabled then the bit 0 of RDES0 indicates whether the + * Extended Status is available (RDES4). Time Stamp feature and the Checksum Offload Engine2 + * makes use of this extended status to provide the status of the received packet. + * @param[in] pointer to synopGMACdevice + * \return returns TRUE or FALSE + */ + + +/** + * This function indicates whether extended status is available in the RDES0. + * Any function which accesses the fields of extended status register must ensure a check on this has been made + * This is valid only for Enhanced Descriptor. + * @param[in] pointer to synopGMACdevice. + * @param[in] u32 status field of the corresponding descriptor. + * \return returns TRUE or FALSE. + */ +bool synopGMAC_is_ext_status(synopGMACdevice *gmacdev, u32 status) // extended status present indicates that the RDES4 need to be probed +{ + return ((status & DescRxEXTsts) != 0); // if extstatus set then it returns 1 +} +/** + * This function returns true if the IP header checksum bit is set in the extended status. + * Valid only when enhaced status available is set in RDES0 bit 0. + * This is valid only for Enhanced Descriptor. + * @param[in] pointer to synopGMACdevice. + * @param[in] u32 status field of the corresponding descriptor. + * \return returns TRUE or FALSE. + */ +bool synopGMAC_ES_is_IP_header_error(synopGMACdevice *gmacdev, u32 ext_status) // IP header (IPV4) checksum error +{ + return ((ext_status & DescRxIpHeaderError) != 0); // if IPV4 header error return 1 +} +/** + * This function returns true if the Checksum is bypassed in the hardware. + * Valid only when enhaced status available is set in RDES0 bit 0. + * This is valid only for Enhanced Descriptor. + * @param[in] pointer to synopGMACdevice. + * @param[in] u32 status field of the corresponding descriptor. + * \return returns TRUE or FALSE. + */ +bool synopGMAC_ES_is_rx_checksum_bypassed(synopGMACdevice *gmacdev, u32 ext_status) // Hardware engine bypassed the checksum computation/checking +{ + return ((ext_status & DescRxChkSumBypass) != 0); // if checksum offloading bypassed return 1 +} +/** + * This function returns true if payload checksum error is set in the extended status. + * Valid only when enhaced status available is set in RDES0 bit 0. + * This is valid only for Enhanced Descriptor. + * @param[in] pointer to synopGMACdevice. + * @param[in] u32 status field of the corresponding descriptor. + * \return returns TRUE or FALSE. + */ +bool synopGMAC_ES_is_IP_payload_error(synopGMACdevice *gmacdev, u32 ext_status) // IP payload checksum is in error (UDP/TCP/ICMP checksum error) +{ + return ((ext_status & DescRxIpPayloadError) != 0); // if IP payload error return 1 +} + + + + +/** + * Decodes the Rx Descriptor status to various checksum error conditions. + * @param[in] pointer to synopGMACdevice. + * @param[in] u32 status field of the corresponding descriptor. + * \return returns decoded enum (u32) indicating the status. + */ +u32 synopGMAC_is_rx_checksum_error(synopGMACdevice *gmacdev, u32 status) +{ + if (((status & DescRxChkBit5) == 0) && ((status & DescRxChkBit7) == 0) && ((status & DescRxChkBit0) == 0)) + return RxLenLT600; + else if (((status & DescRxChkBit5) == 0) && ((status & DescRxChkBit7) == 0) && ((status & DescRxChkBit0) != 0)) + return RxIpHdrPayLoadChkBypass; + else if (((status & DescRxChkBit5) == 0) && ((status & DescRxChkBit7) != 0) && ((status & DescRxChkBit0) != 0)) + return RxChkBypass; + else if (((status & DescRxChkBit5) != 0) && ((status & DescRxChkBit7) == 0) && ((status & DescRxChkBit0) == 0)) + return RxNoChkError; + else if (((status & DescRxChkBit5) != 0) && ((status & DescRxChkBit7) == 0) && ((status & DescRxChkBit0) != 0)) + return RxPayLoadChkError; + else if (((status & DescRxChkBit5) != 0) && ((status & DescRxChkBit7) != 0) && ((status & DescRxChkBit0) == 0)) + return RxIpHdrChkError; + else if (((status & DescRxChkBit5) != 0) && ((status & DescRxChkBit7) != 0) && ((status & DescRxChkBit0) != 0)) + return RxIpHdrPayLoadChkError; + else + return RxIpHdrPayLoadRes; +} +/** + * Checks if any Ipv4 header checksum error in the frame just transmitted. + * This serves as indication that error occureed in the IPv4 header checksum insertion. + * The sent out frame doesnot carry any ipv4 header checksum inserted by the hardware. + * @param[in] pointer to synopGMACdevice. + * @param[in] u32 status field of the corresponding descriptor. + * \return returns true if error in ipv4 header checksum, else returns false. + */ +bool synopGMAC_is_tx_ipv4header_checksum_error(synopGMACdevice *gmacdev, u32 status) +{ + return ((status & DescTxIpv4ChkError) == DescTxIpv4ChkError); +} + + +/** + * Checks if any payload checksum error in the frame just transmitted. + * This serves as indication that error occureed in the payload checksum insertion. + * The sent out frame doesnot carry any payload checksum inserted by the hardware. + * @param[in] pointer to synopGMACdevice. + * @param[in] u32 status field of the corresponding descriptor. + * \return returns true if error in ipv4 header checksum, else returns false. + */ +bool synopGMAC_is_tx_payload_checksum_error(synopGMACdevice *gmacdev, u32 status) +{ + return ((status & DescTxPayChkError) == DescTxPayChkError); +} +/** + * The check summ offload engine is bypassed in the tx path. + * Checksum is not computed in the Hardware. + * @param[in] pointer to synopGMACdevice. + * @param[in] Pointer to tx descriptor for which ointer to synopGMACdevice. + * \return returns void. + */ +void synopGMAC_tx_checksum_offload_bypass(synopGMACdevice *gmacdev, DmaDesc *desc) +{ + desc->status = (desc->status & (~DescTxCisMask));//ENH_DESC + + +} +/** + * The check summ offload engine is enabled to do only IPV4 header checksum. + * IPV4 header Checksum is computed in the Hardware. + * @param[in] pointer to synopGMACdevice. + * @param[in] Pointer to tx descriptor for which ointer to synopGMACdevice. + * \return returns void. + */ +void synopGMAC_tx_checksum_offload_ipv4hdr(synopGMACdevice *gmacdev, DmaDesc *desc) +{ + + desc->status = ((desc->status & (~DescTxCisMask)) | DescTxCisIpv4HdrCs);//ENH_DESC + + +} + +/** + * The check summ offload engine is enabled to do TCPIP checsum assuming Pseudo header is available. + * Hardware computes the tcp ip checksum assuming pseudo header checksum is computed in software. + * Ipv4 header checksum is also inserted. + * @param[in] pointer to synopGMACdevice. + * @param[in] Pointer to tx descriptor for which ointer to synopGMACdevice. + * \return returns void. + */ +void synopGMAC_tx_checksum_offload_tcponly(synopGMACdevice *gmacdev, DmaDesc *desc) +{ + + desc->status = ((desc->status & (~DescTxCisMask)) | DescTxCisTcpOnlyCs);//ENH_DESC + + +} +/** + * The check summ offload engine is enabled to do complete checksum computation. + * Hardware computes the tcp ip checksum including the pseudo header checksum. + * Here the tcp payload checksum field should be set to 0000. + * Ipv4 header checksum is also inserted. + * @param[in] pointer to synopGMACdevice. + * @param[in] Pointer to tx descriptor for which ointer to synopGMACdevice. + * \return returns void. + */ +void synopGMAC_tx_checksum_offload_tcp_pseudo(synopGMACdevice *gmacdev, DmaDesc *desc) +{ + + desc->status = ((desc->status & (~DescTxCisMask)) | DescTxCisTcpPseudoCs); + + +} +/*******************Ip checksum offloading APIs***************************************/ + + + + + +/*******************IEEE 1588 Timestamping API***************************************/ + + +/* + * At this time the driver supports the IEEE time stamping feature when the Enhanced Descriptors are enabled. + * For normal descriptor and the IEEE time stamp (version 1), driver support is not proviced + * Please make sure you have enabled the Advanced timestamp feature in the hardware and the driver should + * be compiled with the ADV_TME_STAMP feature. + * Some of the APIs provided here may not be valid for all configurations. Please make sure you call the + * API with due care. + */ + +/** + * This function enables the timestamping. This enables the timestamping for transmit and receive frames. + * When disabled timestamp is not added to tx and receive frames and timestamp generator is suspended. + * @param[in] pointer to synopGMACdevice + * \return returns void + */ +void synopGMAC_TS_enable(synopGMACdevice *gmacdev) +{ + synopGMACSetBits(gmacdev->MacBase, GmacTSControl, GmacTSENA); + return; +} +/** + * This function disables the timestamping. + * When disabled timestamp is not added to tx and receive frames and timestamp generator is suspended. + * @param[in] pointer to synopGMACdevice + * \return returns void + */ +void synopGMAC_TS_disable(synopGMACdevice *gmacdev) +{ + synopGMACClearBits(gmacdev->MacBase, GmacTSControl, GmacTSENA); + return; +} + + +/** + * Enable the interrupt to get timestamping interrupt. + * This enables the host to get the interrupt when (1) system time is greater or equal to the + * target time high and low register or (2) there is a overflow in th esecond register. + * @param[in] pointer to synopGMACdevice + * \return returns void + */ +void synopGMAC_TS_int_enable(synopGMACdevice *gmacdev) +{ + //synopGMACClearBits(gmacdev->MacBase,GmacInterruptMask,GmacTSIntMask); + synopGMACSetBits(gmacdev->MacBase, GmacTSControl, GmacTSTRIG); + return; +} + +/** + * Disable the interrupt to get timestamping interrupt. + * @param[in] pointer to synopGMACdevice + * \return returns void + */ +void synopGMAC_TS_int_disable(synopGMACdevice *gmacdev) +{ + //synopGMACSetBits(gmacdev->MacBase,GmacInterruptMask,GmacTSIntMask); + synopGMACClearBits(gmacdev->MacBase, GmacTSControl, GmacTSTRIG); + return; +} + +/** + * Enable MAC address for PTP frame filtering. + * When enabled, uses MAC address (apart from MAC address 0) to filter the PTP frames when + * PTP is sent directly over Ethernet. + * @param[in] pointer to synopGMACdevice + * \return returns void + */ +void synopGMAC_TS_mac_addr_filt_enable(synopGMACdevice *gmacdev) +{ + synopGMACSetBits(gmacdev->MacBase, GmacTSControl, GmacTSENMACADDR); + return; +} + +/** + * Disables MAC address for PTP frame filtering. + * @param[in] pointer to synopGMACdevice + * \return returns void + */ +void synopGMAC_TS_mac_addr_filt_disable(synopGMACdevice *gmacdev) +{ + synopGMACClearBits(gmacdev->MacBase, GmacTSControl, GmacTSENMACADDR); + return; +} + + +/** + * Selet the type of clock mode for PTP. + * Please note to use one of the follwoing as the clk_type argument. + * GmacTSOrdClk = 0x00000000, 00=> Ordinary clock + * GmacTSBouClk = 0x00010000, 01=> Boundary clock + * GmacTSEtoEClk = 0x00020000, 10=> End-to-End transparent clock + * GmacTSPtoPClk = 0x00030000, 11=> P-to-P transparent clock + * @param[in] pointer to synopGMACdevice + * @param[in] u32 value representing one of the above clk value + * \return returns void + */ +void synopGMAC_TS_set_clk_type(synopGMACdevice *gmacdev, u32 clk_type) +{ + u32 clkval; + clkval = synopGMACReadReg(gmacdev->MacBase, GmacTSControl); //set the mdc clock to the user defined value + clkval = (clkval & ~GmacTSCLKTYPE) | clk_type; + synopGMACWriteReg(gmacdev->MacBase, GmacTSControl, clkval); + return; +} + +/** + * Enable Snapshot for messages relevant to Master. + * When enabled, snapshot is taken for messages relevant to master mode only, else snapshot is taken for messages relevant + * to slave node. + * Valid only for Ordinary clock and Boundary clock + * Reserved when "Advanced Time Stamp" is not selected + * @param[in] pointer to synopGMACdevice + * \return returns void + */ +void synopGMAC_TS_master_enable(synopGMACdevice *gmacdev) +{ + synopGMACSetBits(gmacdev->MacBase, GmacTSControl, GmacTSMSTRENA); + return; +} +/** + * Disable Snapshot for messages relevant to Master. + * When disabled, snapshot is taken for messages relevant + * to slave node. + * Valid only for Ordinary clock and Boundary clock + * Reserved when "Advanced Time Stamp" is not selected + * @param[in] pointer to synopGMACdevice + * \return returns void + */ +void synopGMAC_TS_master_disable(synopGMACdevice *gmacdev) +{ + synopGMACClearBits(gmacdev->MacBase, GmacTSControl, GmacTSMSTRENA); + return; +} +/** + * Enable Snapshot for Event messages. + * When enabled, snapshot is taken for event messages only (SYNC, Delay_Req, Pdelay_Req or Pdelay_Resp) + * When disabled, snapshot is taken for all messages except Announce, Management and Signaling. + * Reserved when "Advanced Time Stamp" is not selected + * @param[in] pointer to synopGMACdevice + * \return returns void + */ +void synopGMAC_TS_event_enable(synopGMACdevice *gmacdev) +{ + synopGMACSetBits(gmacdev->MacBase, GmacTSControl, GmacTSEVNTENA); + return; +} +/** + * Disable Snapshot for Event messages. + * When disabled, snapshot is taken for all messages except Announce, Management and Signaling. + * Reserved when "Advanced Time Stamp" is not selected + * @param[in] pointer to synopGMACdevice + * \return returns void + */ +void synopGMAC_TS_event_disable(synopGMACdevice *gmacdev) +{ + synopGMACClearBits(gmacdev->MacBase, GmacTSControl, GmacTSEVNTENA); + return; +} + +/** + * Enable time stamp snapshot for IPV4 frames. + * When enabled, time stamp snapshot is taken for IPV4 frames + * Reserved when "Advanced Time Stamp" is not selected + * @param[in] pointer to synopGMACdevice + * \return returns void + */ +void synopGMAC_TS_IPV4_enable(synopGMACdevice *gmacdev) +{ + synopGMACSetBits(gmacdev->MacBase, GmacTSControl, GmacTSIPV4ENA); + return; +} +/** + * Disable time stamp snapshot for IPV4 frames. + * When disabled, time stamp snapshot is not taken for IPV4 frames + * Reserved when "Advanced Time Stamp" is not selected + * @param[in] pointer to synopGMACdevice + * \return returns void + */ +void synopGMAC_TS_IPV4_disable(synopGMACdevice *gmacdev) +{ + synopGMACClearBits(gmacdev->MacBase, GmacTSControl, GmacTSIPV4ENA); + return; +} // Only for "Advanced Time Stamp" +/** + * Enable time stamp snapshot for IPV6 frames. + * When enabled, time stamp snapshot is taken for IPV6 frames + * Reserved when "Advanced Time Stamp" is not selected + * @param[in] pointer to synopGMACdevice + * \return returns void + */ +void synopGMAC_TS_IPV6_enable(synopGMACdevice *gmacdev) +{ + synopGMACSetBits(gmacdev->MacBase, GmacTSControl, GmacTSIPV6ENA); + return; +} +/** + * Disable time stamp snapshot for IPV6 frames. + * When disabled, time stamp snapshot is not taken for IPV6 frames + * Reserved when "Advanced Time Stamp" is not selected + * @param[in] pointer to synopGMACdevice + * \return returns void + */ +void synopGMAC_TS_IPV6_disable(synopGMACdevice *gmacdev) +{ + synopGMACClearBits(gmacdev->MacBase, GmacTSControl, GmacTSIPV6ENA); + return; +} + +/** + * Enable time stamp snapshot for PTP over Ethernet frames. + * When enabled, time stamp snapshot is taken for PTP over Ethernet frames + * Reserved when "Advanced Time Stamp" is not selected + * @param[in] pointer to synopGMACdevice + * \return returns void + */ +void synopGMAC_TS_ptp_over_ethernet_enable(synopGMACdevice *gmacdev) +{ + synopGMACSetBits(gmacdev->MacBase, GmacTSControl, GmacTSIPENA); + return; +} +/** + * Disable time stamp snapshot for PTP over Ethernet frames. + * When disabled, time stamp snapshot is not taken for PTP over Ethernet frames + * Reserved when "Advanced Time Stamp" is not selected + * @param[in] pointer to synopGMACdevice + * \return returns void + */ +void synopGMAC_TS_ptp_over_ethernet_disable(synopGMACdevice *gmacdev) +{ + synopGMACClearBits(gmacdev->MacBase, GmacTSControl, GmacTSIPENA); + return; +} + + +/** + * Snoop PTP packet for version 2 format + * When set the PTP packets are snooped using the version 2 format. + * @param[in] pointer to synopGMACdevice + * \return returns void + */ +void synopGMAC_TS_pkt_snoop_ver2(synopGMACdevice *gmacdev) +{ + synopGMACSetBits(gmacdev->MacBase, GmacTSControl, GmacTSVER2ENA); + return; +} +/** + * Snoop PTP packet for version 2 format + * When set the PTP packets are snooped using the version 2 format. + * @param[in] pointer to synopGMACdevice + * \return returns void + */ +void synopGMAC_TS_pkt_snoop_ver1(synopGMACdevice *gmacdev) +{ + synopGMACClearBits(gmacdev->MacBase, GmacTSControl, GmacTSVER2ENA); + return; +} + +/** + * Timestamp digital rollover + * When set the timestamp low register rolls over after 0x3B9A_C9FF value. + * @param[in] pointer to synopGMACdevice + * \return returns void + */ +void synopGMAC_TS_digital_rollover_enable(synopGMACdevice *gmacdev) +{ + synopGMACSetBits(gmacdev->MacBase, GmacTSControl, GmacTSCTRLSSR); + return; +} +/** + * Timestamp binary rollover + * When set the timestamp low register rolls over after 0x7FFF_FFFF value. + * @param[in] pointer to synopGMACdevice + * \return returns void + */ +void synopGMAC_TS_binary_rollover_enable(synopGMACdevice *gmacdev) +{ + synopGMACClearBits(gmacdev->MacBase, GmacTSControl, GmacTSCTRLSSR); + return; +} +/** + * Enable Time Stamp for All frames + * When set the timestamp snap shot is enabled for all frames received by the core. + * Reserved when "Advanced Time Stamp" is not selected + * @param[in] pointer to synopGMACdevice + * \return returns void + */ +void synopGMAC_TS_all_frames_enable(synopGMACdevice *gmacdev) +{ + synopGMACSetBits(gmacdev->MacBase, GmacTSControl, GmacTSENALL); + return; +} +/** + * Disable Time Stamp for All frames + * When reset the timestamp snap shot is not enabled for all frames received by the core. + * Reserved when "Advanced Time Stamp" is not selected + * @param[in] pointer to synopGMACdevice + * \return returns void + */ +void synopGMAC_TS_all_frames_disable(synopGMACdevice *gmacdev) +{ + synopGMACClearBits(gmacdev->MacBase, GmacTSControl, GmacTSENALL); + return; +} +/** + * Addend Register Update + * This function loads the contents of Time stamp addend register with the supplied 32 value. + * This is reserved function when only coarse correction option is selected + * @param[in] pointer to synopGMACdevice + * @param[in] 32 bit addend value + * \return returns 0 for Success or else Failure + */ +s32 synopGMAC_TS_addend_update(synopGMACdevice *gmacdev, u32 addend_value) +{ + u32 loop_variable; + synopGMACWriteReg(gmacdev->MacBase, GmacTSAddend, addend_value); // Load the addend_value in to Addend register + for (loop_variable = 0; loop_variable < DEFAULT_LOOP_VARIABLE; loop_variable++) //Wait till the busy bit gets cleared with in a certain amount of time + { + if (!((synopGMACReadReg(gmacdev->MacBase, GmacTSControl)) & GmacTSADDREG)) // if it is cleared then break + { + break; + } + plat_delay(DEFAULT_DELAY_VARIABLE); + } + if (loop_variable < DEFAULT_LOOP_VARIABLE) + synopGMACSetBits(gmacdev->MacBase, GmacTSControl, GmacTSADDREG); + else + { + TR("Error::: The TSADDREG bit is not getting cleared !!!!!!\n"); + return -ESYNOPGMACPHYERR; + } + return 0; + +} +/** + * time stamp Update + * This function updates (adds/subtracts) with the value specified in the Timestamp High Update and + * Timestamp Low Update register. + * @param[in] pointer to synopGMACdevice + * @param[in] Timestamp High Update value + * @param[in] Timestamp Low Update value + * \return returns 0 for Success or else Failure + */ +s32 synopGMAC_TS_timestamp_update(synopGMACdevice *gmacdev, u32 high_value, u32 low_value) +{ + u32 loop_variable; + synopGMACWriteReg(gmacdev->MacBase, GmacTSHighUpdate, high_value); // Load the high value to Timestamp High register + synopGMACWriteReg(gmacdev->MacBase, GmacTSLowUpdate, low_value); // Load the high value to Timestamp High register + for (loop_variable = 0; loop_variable < DEFAULT_LOOP_VARIABLE; loop_variable++) //Wait till the busy bit gets cleared with in a certain amount of time + { + if (!((synopGMACReadReg(gmacdev->MacBase, GmacTSControl)) & GmacTSUPDT)) // if it is cleared then break + { + break; + } + plat_delay(DEFAULT_DELAY_VARIABLE); + } + if (loop_variable < DEFAULT_LOOP_VARIABLE) + synopGMACSetBits(gmacdev->MacBase, GmacTSControl, GmacTSUPDT); + else + { + TR("Error::: The TSADDREG bit is not getting cleared !!!!!!\n"); + return -ESYNOPGMACPHYERR; + } + return 0; +} + +/** + * time stamp Initialize + * This function Loads/Initializes h the value specified in the Timestamp High Update and + * Timestamp Low Update register. + * @param[in] pointer to synopGMACdevice + * @param[in] Timestamp High Load value + * @param[in] Timestamp Low Load value + * \return returns 0 for Success or else Failure + */ +s32 synopGMAC_TS_timestamp_init(synopGMACdevice *gmacdev, u32 high_value, u32 low_value) +{ + u32 loop_variable; + synopGMACWriteReg(gmacdev->MacBase, GmacTSHighUpdate, high_value); // Load the high value to Timestamp High register + synopGMACWriteReg(gmacdev->MacBase, GmacTSLowUpdate, low_value); // Load the high value to Timestamp High register + for (loop_variable = 0; loop_variable < DEFAULT_LOOP_VARIABLE; loop_variable++) //Wait till the busy bit gets cleared with in a certain amount of time + { + if (!((synopGMACReadReg(gmacdev->MacBase, GmacTSControl)) & GmacTSINT)) // if it is cleared then break + { + break; + } + plat_delay(DEFAULT_DELAY_VARIABLE); + } + if (loop_variable < DEFAULT_LOOP_VARIABLE) + synopGMACSetBits(gmacdev->MacBase, GmacTSControl, GmacTSINT); + else + { + TR("Error::: The TSADDREG bit is not getting cleared !!!!!!\n"); + return -ESYNOPGMACPHYERR; + } + return 0; +} + +/** + * Time Stamp Update Coarse + * When reset the timestamp update is done using coarse method. + * @param[in] pointer to synopGMACdevice + * \return returns void + */ +void synopGMAC_TS_coarse_update(synopGMACdevice *gmacdev) +{ + synopGMACClearBits(gmacdev->MacBase, GmacTSControl, GmacTSCFUPDT); + return; +} +/** + * Time Stamp Update Fine + * When reset the timestamp update is done using Fine method. + * @param[in] pointer to synopGMACdevice + * \return returns void + */ +void synopGMAC_TS_fine_update(synopGMACdevice *gmacdev) +{ + synopGMACSetBits(gmacdev->MacBase, GmacTSControl, GmacTSCFUPDT); + return; +} + +/** + * Load the Sub Second Increment value in to Sub Second increment register + * @param[in] pointer to synopGMACdevice + * \return returns void + */ +void synopGMAC_TS_subsecond_init(synopGMACdevice *gmacdev, u32 sub_sec_inc_value) +{ + synopGMACWriteReg(gmacdev->MacBase, GmacTSSubSecIncr, (sub_sec_inc_value & GmacSSINCMsk)); + return; +} +/** + * Reads the time stamp contents in to the respective pointers + * These registers are readonly. + * This function returns the 48 bit time stamp assuming Version 2 timestamp with higher word is selected. + * @param[in] pointer to synopGMACdevice + * @param[in] pointer to hold 16 higher bit second register contents + * @param[in] pointer to hold 32 bit second register contents + * @param[in] pointer to hold 32 bit subnanosecond register contents + * \return returns void + * \note Please note that since the atomic access to the timestamp registers is not possible, + * the contents read may be different from the actual time stamp. + */ +void synopGMAC_TS_read_timestamp(synopGMACdevice *gmacdev, u16 *higher_sec_val, u32 *sec_val, u32 *sub_sec_val) +{ + * higher_sec_val = (u16)(synopGMACReadReg(gmacdev->MacBase, GmacTSHighWord) & GmacTSHighWordMask); + * sec_val = synopGMACReadReg(gmacdev->MacBase, GmacTSHigh); + * sub_sec_val = synopGMACReadReg(gmacdev->MacBase, GmacTSLow); + return; +} +/** + * Loads the time stamp higher sec value from the value supplied + * @param[in] pointer to synopGMACdevice + * @param[in] 16 higher bit second register contents passed as 32 bit value + * \return returns void + */ +void synopGMAC_TS_load_timestamp_higher_val(synopGMACdevice *gmacdev, u32 higher_sec_val) +{ + synopGMACWriteReg(gmacdev->MacBase, GmacTSHighWord, (higher_sec_val & GmacTSHighWordMask)); + return; +} +/** + * Reads the time stamp higher sec value to respective pointers + * @param[in] pointer to synopGMACdevice + * @param[in] pointer to hold 16 higher bit second register contents + * \return returns void + */ +void synopGMAC_TS_read_timestamp_higher_val(synopGMACdevice *gmacdev, u16 *higher_sec_val) +{ + * higher_sec_val = (u16)(synopGMACReadReg(gmacdev->MacBase, GmacTSHighWord) & GmacTSHighWordMask); + return; +} +/** + * Load the Target time stamp registers + * This function Loads the target time stamp registers with the values proviced + * @param[in] pointer to synopGMACdevice + * @param[in] target Timestamp High value + * @param[in] target Timestamp Low value + * \return returns 0 for Success or else Failure + */ +void synopGMAC_TS_load_target_timestamp(synopGMACdevice *gmacdev, u32 sec_val, u32 sub_sec_val) +{ + synopGMACWriteReg(gmacdev->MacBase, GmacTSTargetTimeHigh, sec_val); + synopGMACWriteReg(gmacdev->MacBase, GmacTSTargetTimeLow, sub_sec_val); + return; +} +/** + * Reads the Target time stamp registers + * This function Loads the target time stamp registers with the values proviced + * @param[in] pointer to synopGMACdevice + * @param[in] pointer to hold target Timestamp High value + * @param[in] pointer to hold target Timestamp Low value + * \return returns 0 for Success or else Failure + */ +void synopGMAC_TS_read_target_timestamp(synopGMACdevice *gmacdev, u32 *sec_val, u32 *sub_sec_val) +{ + * sec_val = synopGMACReadReg(gmacdev->MacBase, GmacTSTargetTimeHigh); + * sub_sec_val = synopGMACReadReg(gmacdev->MacBase, GmacTSTargetTimeLow); + return; +} + +void synopGMAC_src_addr_insert_enable(synopGMACdevice *gmacdev) +{ + synopGMACClearBits(gmacdev->MacBase, GmacConfig, GmacSrcAddrInsRpl); + synopGMACSetBits(gmacdev->MacBase, GmacConfig, GmacSrcAddrIns); + +} +void synopGMAC_src_addr_insert_disable(synopGMACdevice *gmacdev) +{ + + synopGMACClearBits(gmacdev->MacBase, GmacConfig, GmacSrcAddrInsRpl); + +} +void synopGMAC_src_addr_replace_enable(synopGMACdevice *gmacdev) +{ + synopGMACClearBits(gmacdev->MacBase, GmacConfig, GmacSrcAddrInsRpl); + synopGMACSetBits(gmacdev->MacBase, GmacConfig, GmacSrcAddrRpl); + + +} +void synopGMAC_src_addr_replace_disable(synopGMACdevice *gmacdev) +{ + synopGMACClearBits(gmacdev->MacBase, GmacConfig, GmacSrcAddrInsRpl); + +} + + +void synopGMAC_svlan_insertion_enable(synopGMACdevice *gmacdev, u16 vlantag) +{ + + synopGMACWriteReg(gmacdev->MacBase, GmacVLANIncRep, GmacVLP | GmacSVLAN | GmacVLANIns | vlantag); + + +} + +void synopGMAC_cvlan_insertion_enable(synopGMACdevice *gmacdev, u16 vlantag) +{ + synopGMACWriteReg(gmacdev->MacBase, GmacVLANIncRep, GmacVLP | GmacCVLAN | GmacVLANIns | vlantag); + + +} + +void synopGMAC_svlan_replace_enable(synopGMACdevice *gmacdev, u16 vlantag) +{ + synopGMACWriteReg(gmacdev->MacBase, GmacVLANIncRep, GmacVLP | GmacSVLAN | GmacVLANRep | vlantag); + +} + +void synopGMAC_cvlan_replace_enable(synopGMACdevice *gmacdev, u16 vlantag) +{ + synopGMACWriteReg(gmacdev->MacBase, GmacVLANIncRep, GmacVLP | GmacCVLAN | GmacVLANRep | vlantag); + +} + +void synopGMAC_vlan_deletion_enable(synopGMACdevice *gmacdev) +{ + synopGMACWriteReg(gmacdev->MacBase, GmacVLANIncRep, GmacVLP | GmacVLANDel); + + +} + + +void synopGMAC_vlan_no_act_enable(synopGMACdevice *gmacdev) +{ + synopGMACClearBits(gmacdev->MacBase, GmacVLANIncRep, 0xFFFFFFFF); +} + + diff --git a/bsp/nuvoton/libraries/ma35/rtt_port/gmac/synopGMAC_Dev.h b/bsp/nuvoton/libraries/ma35/rtt_port/gmac/synopGMAC_Dev.h new file mode 100644 index 0000000000..b25b522d08 --- /dev/null +++ b/bsp/nuvoton/libraries/ma35/rtt_port/gmac/synopGMAC_Dev.h @@ -0,0 +1,1715 @@ +/* =================================================================================== + * Copyright (c) <2009> Synopsys, Inc. + * + * Permission is hereby granted, free of charge, to any person obtaining a copy of + * this software annotated with this license and associated documentation files + * (the "Software"), to deal in the Software without restriction, including without + * limitation the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the Software is + * furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in all + * copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, + * INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS FOR A + * PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT + * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION + * OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE + * OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + * + * =================================================================================== */ + +/**\file + * This file defines the function prototypes for the Synopsys GMAC device and the + * Marvell 88E1011/88E1011S integrated 10/100/1000 Gigabit Ethernet Transceiver. + * Since the phy register mapping are standardised, the phy register map and the + * bit definitions remain the same for other phy as well. + * This also defines some of the Ethernet related parmeters. + * \internal + * -----------------------------REVISION HISTORY------------------------------------ + * Synopsys 01/Aug/2007 Created + */ + + +#ifndef SYNOP_GMAC_DEV_H +#define SYNOP_GMAC_DEV_H 1 + + +#include "synopGMAC_plat.h" +#include "synopGMAC_types.h" + +/*SynopGMAC can support up to 32 phys*/ + +enum GMACPhyBase +{ + PHY0 = 0, //The device can support 32 phys, but we use first phy only + PHY1 = 1, + PHY31 = 31, +}; + +#define DEFAULT_PHY_BASE PHY0 //We use First Phy +#define MACBASE 0x0000 // The Mac Base address offset is 0x0000 +#define DMABASE 0x1000 // Dma base address starts with an offset 0x1000 + + +#define TRANSMIT_DESC_SIZE 512 //Tx Descriptors needed in the Descriptor pool/queue +#define RECEIVE_DESC_SIZE 1024 //Rx Descriptors needed in the Descriptor pool/queue + +#define ETHERNET_HEADER 14 //6 byte Dest addr, 6 byte Src addr, 2 byte length/type +#define ETHERNET_CRC 4 //Ethernet CRC +#define ETHERNET_EXTRA 2 //Only God knows about this????? +#define ETHERNET_PACKET_COPY 250 // Maximum length when received data is copied on to a new skb +#define ETHERNET_PACKET_EXTRA 18 // Preallocated length for the rx packets is MTU + ETHERNET_PACKET_EXTRA +#define VLAN_TAG 4 //optional 802.1q VLAN Tag +#define MIN_ETHERNET_PAYLOAD 46 //Minimum Ethernet payload size +#define MAX_ETHERNET_PAYLOAD 1500 //Maximum Ethernet payload size +#define JUMBO_FRAME_PAYLOAD 9000 //Jumbo frame payload size + +#define PKT_FRAME_BUF_SIZE 1536 //(ETHERNET_HEADER + ETHERNET_CRC + MAX_ETHERNET_PAYLOAD + VLAN_TAG)+alignment + +// This is the IP's phy address. This is unique address for every MAC in the universe +#define DEFAULT_MAC0_ADDRESS {0x00, 0x55, 0x7B, 0xB5, 0x7D, 0xF7} +#define DEFAULT_MAC1_ADDRESS {0x00, 0x55, 0x7B, 0xB5, 0x7D, 0xF8} +/* +DMA Descriptor Structure +The structure is common for both receive and transmit descriptors +The descriptor is of 4 words, but our structrue contains 6 words where +last two words are to hold the virtual address of the network buffer pointers +for driver's use +From the GMAC core release 3.50a onwards, the Enhanced Descriptor structure got changed. +The descriptor (both transmit and receive) are of 8 words each rather the 4 words of normal +descriptor structure. +Whenever IEEE 1588 Timestamping is enabled TX/RX DESC6 provides the lower 32 bits of Timestamp value and + TX/RX DESC7 provides the upper 32 bits of Timestamp value +In addition to this whenever extended status bit is set (RX DESC0 bit 0), RX DESC4 contains the extended status information +*/ + +#define MODULO_INTERRUPT 1 // if it is set to 1, interrupt is available for all the descriptors or else interrupt is available only for +// descriptor whose index%MODULO_INTERRUPT is zero +typedef struct DmaDescStruct +{ + u32 status; /* Status */ + u32 length; /* Buffer 1 and Buffer 2 length */ + u32 buffer1; /* Network Buffer 1 pointer (Dma-able) */ + u32 buffer2; /* Network Buffer 2 pointer or next descriptor pointer (Dma-able)in chain structure */ + /* This data below is used only by driver */ + u32 extstatus; /* Extended status of a Rx Descriptor */ + u32 reserved1; /* Reserved word */ + u32 timestamplow; /* Lower 32 bits of the 64 bit timestamp value */ + u32 timestamphigh; /* Higher 32 bits of the 64 bit timestamp value */ + //u32 data1; /* This holds virtual address of buffer1, not used by DMA */ + //u32 data2; /* This holds virtual address of buffer2, not used by DMA */ +} DmaDesc; + +enum DescMode +{ + RINGMODE = 0x00000001, + CHAINMODE = 0x00000002, +}; + +enum BufferMode +{ + SINGLEBUF = 0x00000001, + DUALBUF = 0x00000002, +}; + +/* synopGMAC device data */ + +struct net_device_stats +{ + u32 tx_bytes; + u32 tx_packets; + u32 tx_errors; + u32 tx_aborted_errors; + u32 tx_carrier_errors; + u32 tx_ip_header_errors; + u32 tx_ip_payload_errors; + u32 collisions; + u32 rx_bytes; + u32 rx_packets; + u32 rx_errors; + u32 rx_crc_errors; + u32 rx_frame_errors; + u32 rx_length_errors; + u32 rx_dropped; + u32 rx_over_errors; + u32 rx_ip_header_errors; + u32 rx_ip_payload_errors; + volatile u32 ts_int; +}; + +typedef struct synopGMACDeviceStruct +{ + u32 MacBase; /* base address of MAC registers */ + u32 DmaBase; /* base address of DMA registers */ + u32 PhyBase; /* PHY device address on MII interface */ + u32 Version; /* Gmac Revision version */ + + dma_addr_t TxDescDma; /* Dma-able address of first tx descriptor either in ring or chain mode, this is used by the GMAC device*/ + dma_addr_t RxDescDma; /* Dma-albe address of first rx descriptor either in ring or chain mode, this is used by the GMAC device*/ + DmaDesc *TxDesc; /* start address of TX descriptors ring or chain, this is used by the driver */ + DmaDesc *RxDesc; /* start address of RX descriptors ring or chain, this is used by the driver */ + + u32 BusyTxDesc; /* Number of Tx Descriptors owned by DMA at any given time*/ + u32 BusyRxDesc; /* Number of Rx Descriptors owned by DMA at any given time*/ + + u32 RxDescCount; /* number of rx descriptors in the tx descriptor queue/pool */ + u32 TxDescCount; /* number of tx descriptors in the rx descriptor queue/pool */ + + u32 TxBusy; /* index of the tx descriptor owned by DMA, is obtained by synopGMAC_get_tx_qptr() */ + u32 TxNext; /* index of the tx descriptor next available with driver, given to DMA by synopGMAC_set_tx_qptr() */ + u32 RxBusy; /* index of the rx descriptor owned by DMA, obtained by synopGMAC_get_rx_qptr() */ + u32 RxNext; /* index of the rx descriptor next available with driver, given to DMA by synopGMAC_set_rx_qptr() */ + + DmaDesc *TxBusyDesc; /* Tx Descriptor address corresponding to the index TxBusy */ + DmaDesc *TxNextDesc; /* Tx Descriptor address corresponding to the index TxNext */ + DmaDesc *RxBusyDesc; /* Rx Descriptor address corresponding to the index TxBusy */ + DmaDesc *RxNextDesc; /* Rx Descriptor address corresponding to the index RxNext */ + + struct net_device_stats synopGMACNetStats; + + /*Phy related stuff*/ + u32 ClockDivMdc; /* Clock divider value programmed in the hardware */ + /* The status of the link */ + u32 LinkState; /* Link status as reported by the Marvel Phy */ + u32 DuplexMode; /* Duplex mode of the Phy */ + u32 Speed; /* Speed of the Phy */ + u32 LoopBackMode; /* Loopback status of the Phy */ + + u32 tx_sec; + u32 tx_subsec; + u32 rx_sec; + u32 rx_subsec; + + u32 GMAC_Power_down; + +} synopGMACdevice; + + +/* Below is "88E1011/88E1011S Integrated 10/100/1000 Gigabit Ethernet Transceiver" + * Register and their layouts. This Phy has been used in the Dot Aster GMAC Phy daughter. + * Since the Phy register map is standard, this map hardly changes to a different Ppy + */ + +enum MiiRegisters +{ + PHY_CONTROL_REG = 0x0000, /*Control Register*/ + PHY_STATUS_REG = 0x0001, /*Status Register */ + PHY_ID_HI_REG = 0x0002, /*PHY Identifier High Register*/ + PHY_ID_LOW_REG = 0x0003, /*PHY Identifier High Register*/ + PHY_AN_ADV_REG = 0x0004, /*Auto-Negotiation Advertisement Register*/ + PHY_LNK_PART_ABl_REG = 0x0005, /*Link Partner Ability Register (Base Page)*/ + PHY_AN_EXP_REG = 0x0006, /*Auto-Negotiation Expansion Register*/ + PHY_AN_NXT_PAGE_TX_REG = 0x0007, /*Next Page Transmit Register*/ + PHY_LNK_PART_NXT_PAGE_REG = 0x0008, /*Link Partner Next Page Register*/ + PHY_1000BT_CTRL_REG = 0x0009, /*1000BASE-T Control Register*/ + PHY_1000BT_STATUS_REG = 0x000a, /*1000BASE-T Status Register*/ + PHY_SPECIFIC_CTRL_REG = 0x0010, /*Phy specific control register*/ + PHY_SPECIFIC_STATUS_REG = 0x0011, /*Phy specific status register*/ + PHY_INTERRUPT_ENABLE_REG = 0x0012, /*Phy interrupt enable register*/ + PHY_INTERRUPT_STATUS_REG = 0x0013, /*Phy interrupt status register*/ + PHY_EXT_PHY_SPC_CTRL = 0x0014, /*Extended Phy specific control*/ + PHY_RX_ERR_COUNTER = 0x0015, /*Receive Error Counter*/ + PHY_EXT_ADDR_CBL_DIAG = 0x0016, /*Extended address for cable diagnostic register*/ + PHY_LED_CONTROL = 0x0018, /*LED Control*/ + PHY_MAN_LED_OVERIDE = 0x0019, /*Manual LED override register*/ + PHY_EXT_PHY_SPC_CTRL2 = 0x001a, /*Extended Phy specific control 2*/ + PHY_EXT_PHY_SPC_STATUS = 0x001b, /*Extended Phy specific status*/ + PHY_CBL_DIAG_REG = 0x001c, /*Cable diagnostic registers*/ +}; + + +/* This is Control register layout. Control register is of 16 bit wide. +*/ + +enum Mii_GEN_CTRL +{ + /* Description bits R/W default value */ + Mii_reset = 0x8000, + Mii_Speed_10 = 0x0000, /* 10 Mbps 6:13 RW */ + Mii_Speed_100 = 0x2000, /* 100 Mbps 6:13 RW */ + Mii_Speed_1000 = 0x0040, /* 1000 Mbit/s 6:13 RW */ + + Mii_Duplex = 0x0100, /* Full Duplex mode 8 RW */ + + Mii_Manual_Master_Config = 0x0800, /* Manual Master Config 11 RW */ + + Mii_Loopback = 0x4000, /* Enable Loop back 14 RW */ + Mii_NoLoopback = 0x0000, /* Enable Loop back 14 RW */ +}; + +enum Mii_Phy_Status +{ + Mii_phy_status_speed_10 = 0x0000, + Mii_phy_status_speed_100 = 0x4000, + Mii_phy_status_speed_1000 = 0x8000, + + Mii_phy_status_full_duplex = 0x2000, + Mii_phy_status_half_duplex = 0x0000, + + Mii_phy_status_link_up = 0x0400, +}; +/* This is Status register layout. Status register is of 16 bit wide. +*/ +enum Mii_GEN_STATUS +{ + Mii_AutoNegCmplt = 0x0020, /* Autonegotiation completed 5 RW */ + Mii_Link = 0x0004, /* Link status 2 RW */ +}; + +enum Mii_Link_Status +{ + LINKDOWN = 0, + LINKUP = 1, +}; + +enum Mii_Duplex_Mode +{ + HALFDUPLEX = 1, + FULLDUPLEX = 2, +}; +enum Mii_Link_Speed +{ + SPEED10 = 1, + SPEED100 = 2, + SPEED1000 = 3, +}; + +enum Mii_Loop_Back +{ + NOLOOPBACK = 0, + LOOPBACK = 1, +}; + + + +/********************************************************** + * GMAC registers Map + * For Pci based system address is BARx + GmacRegisterBase + * For any other system translation is done accordingly + **********************************************************/ +enum GmacRegisters +{ + GmacConfig = 0x0000, /* Mac config Register */ + GmacFrameFilter = 0x0004, /* Mac frame filtering controls */ + GmacHashHigh = 0x0008, /* Multi-cast hash table high */ + GmacHashLow = 0x000C, /* Multi-cast hash table low */ + GmacGmiiAddr = 0x0010, /* GMII address Register(ext. Phy) */ + GmacGmiiData = 0x0014, /* GMII data Register(ext. Phy) */ + GmacFlowControl = 0x0018, /* Flow control Register */ + GmacVlan = 0x001C, /* VLAN tag Register (IEEE 802.1Q) */ + + GmacVersion = 0x0020, /* GMAC Core Version Register */ + GmacDebug = 0x0024, /* GMAC Debug Register */ + GmacWakeupAddr = 0x0028, /* GMAC wake-up frame filter adrress reg */ + GmacPmtCtrlStatus = 0x002C, /* PMT control and status register */ + + + GmacLPICtrlSts = 0x0030, /* LPI (low power idle) Control and Status Register */ + GmacLPITimerCtrl = 0x0034, /* LPI timer control register */ + + + GmacInterruptStatus = 0x0038, /* Mac Interrupt ststus register */ + GmacInterruptMask = 0x003C, /* Mac Interrupt Mask register */ + + GmacAddr0High = 0x0040, /* Mac address0 high Register */ + GmacAddr0Low = 0x0044, /* Mac address0 low Register */ + GmacAddr1High = 0x0048, /* Mac address1 high Register */ + GmacAddr1Low = 0x004C, /* Mac address1 low Register */ + GmacAddr2High = 0x0050, /* Mac address2 high Register */ + GmacAddr2Low = 0x0054, /* Mac address2 low Register */ + GmacAddr3High = 0x0058, /* Mac address3 high Register */ + GmacAddr3Low = 0x005C, /* Mac address3 low Register */ + GmacAddr4High = 0x0060, /* Mac address4 high Register */ + GmacAddr4Low = 0x0064, /* Mac address4 low Register */ + GmacAddr5High = 0x0068, /* Mac address5 high Register */ + GmacAddr5Low = 0x006C, /* Mac address5 low Register */ + GmacAddr6High = 0x0070, /* Mac address6 high Register */ + GmacAddr6Low = 0x0074, /* Mac address6 low Register */ + GmacAddr7High = 0x0078, /* Mac address7 high Register */ + GmacAddr7Low = 0x007C, /* Mac address7 low Register */ + GmacAddr8High = 0x0080, /* Mac address8 high Register */ + GmacAddr8Low = 0x0084, /* Mac address8 low Register */ + GmacAddr9High = 0x0088, /* Mac address9 high Register */ + GmacAddr9Low = 0x008C, /* Mac address9 low Register */ + GmacAddr10High = 0x0090, /* Mac address10 high Register */ + GmacAddr10Low = 0x0094, /* Mac address10 low Register */ + GmacAddr11High = 0x0098, /* Mac address11 high Register */ + GmacAddr11Low = 0x009C, /* Mac address11 low Register */ + GmacAddr12High = 0x00A0, /* Mac address12 high Register */ + GmacAddr12Low = 0x00A4, /* Mac address12 low Register */ + GmacAddr13High = 0x00A8, /* Mac address13 high Register */ + GmacAddr13Low = 0x00AC, /* Mac address13 low Register */ + GmacAddr14High = 0x00B0, /* Mac address14 high Register */ + GmacAddr14Low = 0x00B4, /* Mac address14 low Register */ + GmacAddr15High = 0x00B8, /* Mac address15 high Register */ + GmacAddr15Low = 0x00BC, /* Mac address15 low Register */ + GmacRgmiiCtrlSts = 0x00D8, /*SGMII_RGMII_SMII_Control_Status Register */ + GmacVLANIncRep = 0x0584, + /*Time Stamp Register Map*/ + GmacTSControl = 0x0700, /* Controls the Timestamp update logic : only when IEEE 1588 time stamping is enabled in corekit */ + + GmacTSSubSecIncr = 0x0704, /* 8 bit value by which sub second register is incremented : only when IEEE 1588 time stamping without external timestamp input */ + + GmacTSHigh = 0x0708, /* 32 bit seconds(MS) : only when IEEE 1588 time stamping without external timestamp input */ + GmacTSLow = 0x070C, /* 32 bit nano seconds(MS) : only when IEEE 1588 time stamping without external timestamp input */ + + GmacTSHighUpdate = 0x0710, /* 32 bit seconds(MS) to be written/added/subtracted : only when IEEE 1588 time stamping without external timestamp input */ + GmacTSLowUpdate = 0x0714, /* 32 bit nano seconds(MS) to be writeen/added/subtracted : only when IEEE 1588 time stamping without external timestamp input */ + + GmacTSAddend = 0x0718, /* Used by Software to readjust the clock frequency linearly : only when IEEE 1588 time stamping without external timestamp input */ + + GmacTSTargetTimeHigh = 0x071C, /* 32 bit seconds(MS) to be compared with system time : only when IEEE 1588 time stamping without external timestamp input */ + GmacTSTargetTimeLow = 0x0720, /* 32 bit nano seconds(MS) to be compared with system time : only when IEEE 1588 time stamping without external timestamp input */ + + GmacTSHighWord = 0x0724, /* Time Stamp Higher Word Register (Version 2 only); only lower 16 bits are valid */ + //GmacTSHighWordUpdate = 0x072C, /* Time Stamp Higher Word Update Register (Version 2 only); only lower 16 bits are valid */ + + GmacTSStatus = 0x0728, /* Time Stamp Status Register */ + GmacPPSCtrl = 0x072C, /* PPS Control Register */ + GmacPPSInt = 0x0760, /* PPS0 Interval Register */ + GmacPPSWidth = 0x0764, /* PPS0 Width Register */ +}; + +/********************************************************** + * GMAC Network interface registers + * This explains the Register's Layout + + * FES is Read only by default and is enabled only when Tx + * Config Parameter is enabled for RGMII/SGMII interface + * during CoreKit Config. + + * DM is Read only with value 1'b1 in Full duplex only Config + **********************************************************/ + +/* GmacConfig = 0x0000, Mac config Register Layout */ +enum GmacConfigReg +{ + /* Bit description Bits R/W Reset value */ + + GmacSrcAddrInsRpl = 0x70000000, + GmacSrcAddrIns = 0x20000000, + GmacSrcAddrRpl = 0x30000000, + GmacWatchdog = 0x00800000, + GmacWatchdogDisable = 0x00800000, /* (WD)Disable watchdog timer on Rx 23 RW */ + GmacWatchdogEnable = 0x00000000, /* Enable watchdog timer 0 */ + + GmacJabber = 0x00400000, + GmacJabberDisable = 0x00400000, /* (JD)Disable jabber timer on Tx 22 RW */ + GmacJabberEnable = 0x00000000, /* Enable jabber timer 0 */ + + GmacFrameBurst = 0x00200000, + GmacFrameBurstEnable = 0x00200000, /* (BE)Enable frame bursting during Tx 21 RW */ + GmacFrameBurstDisable = 0x00000000, /* Disable frame bursting 0 */ + + GmacJumboFrame = 0x00100000, + GmacJumboFrameEnable = 0x00100000, /* (JE)Enable jumbo frame for Tx 20 RW */ + GmacJumboFrameDisable = 0x00000000, /* Disable jumbo frame 0 */ + + GmacInterFrameGap7 = 0x000E0000, /* (IFG) Config7 - 40 bit times 19:17 RW */ + GmacInterFrameGap6 = 0x000C0000, /* (IFG) Config6 - 48 bit times */ + GmacInterFrameGap5 = 0x000A0000, /* (IFG) Config5 - 56 bit times */ + GmacInterFrameGap4 = 0x00080000, /* (IFG) Config4 - 64 bit times */ + GmacInterFrameGap3 = 0x00040000, /* (IFG) Config3 - 72 bit times */ + GmacInterFrameGap2 = 0x00020000, /* (IFG) Config2 - 80 bit times */ + GmacInterFrameGap1 = 0x00010000, /* (IFG) Config1 - 88 bit times */ + GmacInterFrameGap0 = 0x00000000, /* (IFG) Config0 - 96 bit times 000 */ + + GmacDisableCrs = 0x00010000, + GmacMiiGmii = 0x00008000, + GmacSelectMii = 0x00008000, /* (PS)Port Select-MII mode 15 RW */ + GmacSelectGmii = 0x00000000, /* GMII mode 0 */ + + GmacFESpeed100 = 0x00004000, /*(FES)Fast Ethernet speed 100Mbps 14 RW */ + GmacFESpeed10 = 0x00000000, /* 10Mbps 0 */ + + GmacRxOwn = 0x00002000, + GmacDisableRxOwn = 0x00002000, /* (DO)Disable receive own packets 13 RW */ + GmacEnableRxOwn = 0x00000000, /* Enable receive own packets 0 */ + + GmacLoopback = 0x00001000, + GmacLoopbackOn = 0x00001000, /* (LM)Loopback mode for GMII/MII 12 RW */ + GmacLoopbackOff = 0x00000000, /* Normal mode 0 */ + + GmacDuplex = 0x00000800, + GmacFullDuplex = 0x00000800, /* (DM)Full duplex mode 11 RW */ + GmacHalfDuplex = 0x00000000, /* Half duplex mode 0 */ + + GmacRxIpcOffload = 0x00000400, /*IPC checksum offload 10 RW 0 */ + + GmacRetry = 0x00000200, + GmacRetryDisable = 0x00000200, /* (DR)Disable Retry 9 RW */ + GmacRetryEnable = 0x00000000, /* Enable retransmission as per BL 0 */ + + GmacLinkUp = 0x00000100, /* (LUD)Link UP 8 RW */ + GmacLinkDown = 0x00000100, /* Link Down 0 */ + + GmacPadCrcStrip = 0x00000080, + GmacPadCrcStripEnable = 0x00000080, /* (ACS) Automatic Pad/Crc strip enable 7 RW */ + GmacPadCrcStripDisable = 0x00000000, /* Automatic Pad/Crc stripping disable 0 */ + + GmacBackoffLimit = 0x00000060, + GmacBackoffLimit3 = 0x00000060, /* (BL)Back-off limit in HD mode 6:5 RW */ + GmacBackoffLimit2 = 0x00000040, /* */ + GmacBackoffLimit1 = 0x00000020, /* */ + GmacBackoffLimit0 = 0x00000000, /* 00 */ + + GmacDeferralCheck = 0x00000010, + GmacDeferralCheckEnable = 0x00000010, /* (DC)Deferral check enable in HD mode 4 RW */ + GmacDeferralCheckDisable = 0x00000000, /* Deferral check disable 0 */ + + GmacTx = 0x00000008, + GmacTxEnable = 0x00000008, /* (TE)Transmitter enable 3 RW */ + GmacTxDisable = 0x00000000, /* Transmitter disable 0 */ + + GmacRx = 0x00000004, + GmacRxEnable = 0x00000004, /* (RE)Receiver enable 2 RW */ + GmacRxDisable = 0x00000000, /* Receiver disable 0 */ +}; + +/* GmacFrameFilter = 0x0004, Mac frame filtering controls Register Layout*/ +enum GmacFrameFilterReg +{ + GmacFilter = 0x80000000, + GmacFilterOff = 0x80000000, /* (RA)Receive all incoming packets 31 RW */ + GmacFilterOn = 0x00000000, /* Receive filtered packets only 0 */ + GmacVlanTagFilter = 0x00010000, /*VLAN tag filter enable 16 RW 0 */ + GmacHashPerfectFilter = 0x00000400, /*Hash or Perfect Filter enable 10 RW 0 */ + + GmacSrcAddrFilter = 0x00000200, + GmacSrcAddrFilterEnable = 0x00000200, /* (SAF)Source Address Filter enable 9 RW */ + GmacSrcAddrFilterDisable = 0x00000000, /* 0 */ + + GmacSrcInvaAddrFilter = 0x00000100, + GmacSrcInvAddrFilterEn = 0x00000100, /* (SAIF)Inv Src Addr Filter enable 8 RW */ + GmacSrcInvAddrFilterDis = 0x00000000, /* 0 */ + + GmacPassControl = 0x000000C0, + GmacPassControl3 = 0x000000C0, /* (PCS)Forwards ctrl frms that pass AF 7:6 RW */ + GmacPassControl2 = 0x00000080, /* Forwards all control frames */ + GmacPassControl1 = 0x00000040, /* Does not pass control frames */ + GmacPassControl0 = 0x00000000, /* Does not pass control frames 00 */ + + GmacBroadcast = 0x00000020, + GmacBroadcastDisable = 0x00000020, /* (DBF)Disable Rx of broadcast frames 5 RW */ + GmacBroadcastEnable = 0x00000000, /* Enable broadcast frames 0 */ + + GmacMulticastFilter = 0x00000010, + GmacMulticastFilterOff = 0x00000010, /* (PM) Pass all multicast packets 4 RW */ + GmacMulticastFilterOn = 0x00000000, /* Pass filtered multicast packets 0 */ + + GmacDestAddrFilter = 0x00000008, + GmacDestAddrFilterInv = 0x00000008, /* (DAIF)Inverse filtering for DA 3 RW */ + GmacDestAddrFilterNor = 0x00000000, /* Normal filtering for DA 0 */ + + GmacMcastHashFilter = 0x00000004, + GmacMcastHashFilterOn = 0x00000004, /* (HMC)perfom multicast hash filtering 2 RW */ + GmacMcastHashFilterOff = 0x00000000, /* perfect filtering only 0 */ + + GmacUcastHashFilter = 0x00000002, + GmacUcastHashFilterOn = 0x00000002, /* (HUC)Unicast Hash filtering only 1 RW */ + GmacUcastHashFilterOff = 0x00000000, /* perfect filtering only 0 */ + + GmacPromiscuousMode = 0x00000001, + GmacPromiscuousModeOn = 0x00000001, /* Receive all frames 0 RW */ + GmacPromiscuousModeOff = 0x00000000, /* Receive filtered packets only 0 */ +}; + + +/*GmacGmiiAddr = 0x0010, GMII address Register(ext. Phy) Layout */ +enum GmacGmiiAddrReg +{ + GmiiDevMask = 0x0000F800, /* (PA)GMII device address 15:11 RW 0x00 */ + GmiiDevShift = 11, + + GmiiRegMask = 0x000007C0, /* (GR)GMII register in selected Phy 10:6 RW 0x00 */ + GmiiRegShift = 6, + + GmiiCsrClkMask = 0x0000001C, /*CSR Clock bit Mask 4:2 */ + GmiiCsrClk5 = 0x00000014, /* (CR)CSR Clock Range 250-300 MHz 4:2 RW 000 */ + GmiiCsrClk4 = 0x00000010, /* 150-250 MHz */ + GmiiCsrClk3 = 0x0000000C, /* 35-60 MHz */ + GmiiCsrClk2 = 0x00000008, /* 20-35 MHz */ + GmiiCsrClk1 = 0x00000004, /* 100-150 MHz */ + GmiiCsrClk0 = 0x00000000, /* 60-100 MHz */ + + GmiiWrite = 0x00000002, /* (GW)Write to register 1 RW */ + GmiiRead = 0x00000000, /* Read from register 0 */ + + GmiiBusy = 0x00000001, /* (GB)GMII interface is busy 0 RW 0 */ +}; + +enum GmacVlanTagReg +{ + GmacEnableSVlan = 0x00040000, /* (ESVL) Enabe S-Vlan */ + GmacVlanInvMatch = 0x00020000, /* (VTIM) VLAN tag inverse match enable */ + GmacEnable12BitComp = 0x00010000, /* (ETV) Enable 12-bit VLAN tag comparision */ + GmacVlanTagMsk = 0x0000FFFF /* (VL) VLAN tag */ + +}; + + +enum GmacLPICtrlStsReg +{ + GmacLPITxAuto = 0x00080000, + GmacLPIPhyStsEn = 0x00040000, + GmacLPIPhySts = 0x00020000, + GmacLPIEn = 0x00010000, + GmacRxLPISts = 0x00000200, + GmacTxLPISts = 0x00000100, + GmacRxLPIExit = 0x00000008, + GmacRxLPIEnter = 0x00000004, + GmacTxLPIExit = 0x00000002, + GmacTxLPIEnter = 0x00000001, +}; + +enum GmacLPITimerCtrlReg +{ + GmacLPILinkStableTimerMsk = 0x03FF0000, + GmacLPITxWaitTimerMsk = 0x0000FFFF, +}; + + +/* GmacGmiiData = 0x0014, GMII data Register(ext. Phy) Layout */ +enum GmacGmiiDataReg +{ + GmiiDataMask = 0x0000FFFF, /* (GD)GMII Data 15:0 RW 0x0000 */ +}; + + +/*GmacFlowControl = 0x0018, Flow control Register Layout */ +enum GmacFlowControlReg +{ + GmacPauseTimeMask = 0xFFFF0000, /* (PT) PAUSE TIME field in the control frame 31:16 RW 0x0000 */ + GmacPauseTimeShift = 16, + + GmacPauseLowThresh = 0x00000030, + GmacPauseLowThresh3 = 0x00000030, /* (PLT)thresh for pause tmr 256 slot time 5:4 RW */ + GmacPauseLowThresh2 = 0x00000020, /* 144 slot time */ + GmacPauseLowThresh1 = 0x00000010, /* 28 slot time */ + GmacPauseLowThresh0 = 0x00000000, /* 4 slot time 000 */ + + GmacUnicastPauseFrame = 0x00000008, + GmacUnicastPauseFrameOn = 0x00000008, /* (UP)Detect pause frame with unicast addr. 3 RW */ + GmacUnicastPauseFrameOff = 0x00000000, /* Detect only pause frame with multicast addr. 0 */ + + GmacRxFlowControl = 0x00000004, + GmacRxFlowControlEnable = 0x00000004, /* (RFE)Enable Rx flow control 2 RW */ + GmacRxFlowControlDisable = 0x00000000, /* Disable Rx flow control 0 */ + + GmacTxFlowControl = 0x00000002, + GmacTxFlowControlEnable = 0x00000002, /* (TFE)Enable Tx flow control 1 RW */ + GmacTxFlowControlDisable = 0x00000000, /* Disable flow control 0 */ + + GmacFlowControlBackPressure = 0x00000001, + GmacSendPauseFrame = 0x00000001, /* (FCB/PBA)send pause frm/Apply back pressure 0 RW 0 */ +}; + + +enum GmacVLANIncRepReg +{ + GmacSVLAN = 0x00080000, + GmacCVLAN = 0x00000000, + GmacVLP = 0x00040000, + GmacVLANNoACT = 0x00000000, + GmacVLANDel = 0x00010000, + GmacVLANIns = 0x00020000, + GmacVLANRep = 0x00030000, + GmacVLANMsk = 0x0000FFFF + +}; + +/* GmacInterruptStatus = 0x0038, Mac Interrupt ststus register */ +enum GmacInterruptStatusBitDefinition +{ + GmacLPIIntSts = 0x00000400, /* set if int generated due to TS (Read Time Stamp Status Register to know details)*/ + GmacTSIntSts = 0x00000200, /* set if int generated due to TS (Read Time Stamp Status Register to know details)*/ + GmacMmcRxChksumOffload = 0x00000080, /* set if int generated in MMC RX CHECKSUM OFFLOAD int register */ + GmacMmcTxIntSts = 0x00000040, /* set if int generated in MMC TX Int register */ + GmacMmcRxIntSts = 0x00000020, /* set if int generated in MMC RX Int register */ + GmacMmcIntSts = 0x00000010, /* set if any of the above bit [7:5] is set */ + GmacPmtIntSts = 0x00000008, /* set whenver magic pkt/wake-on-lan frame is received */ + GmacPcsAnComplete = 0x00000004, /* set when AN is complete in TBI/RTBI/SGMIII phy interface */ + GmacPcsLnkStsChange = 0x00000002, /* set if any lnk status change in TBI/RTBI/SGMII interface */ + GmacRgmiiIntSts = 0x00000001, /* set if any change in lnk status of RGMII interface */ + +}; + +/* GmacInterruptMask = 0x003C, Mac Interrupt Mask register */ +enum GmacInterruptMaskBitDefinition +{ + GmacTSIntMask = 0x00000200, /* when set disables the time stamp interrupt generation */ + GmacPmtIntMask = 0x00000008, /* when set Disables the assertion of PMT interrupt */ + GmacPcsAnIntMask = 0x00000004, /* When set disables the assertion of PCS AN complete interrupt */ + GmacPcsLnkStsIntMask = 0x00000002, /* when set disables the assertion of PCS lnk status change interrupt */ + GmacRgmiiIntMask = 0x00000001, /* when set disables the assertion of RGMII int */ +}; + +/********************************************************** + * GMAC DMA registers + * For Pci based system address is BARx + GmaDmaBase + * For any other system translation is done accordingly + **********************************************************/ + +enum DmaRegisters +{ + DmaBusMode = 0x0000, /* CSR0 - Bus Mode Register */ + DmaTxPollDemand = 0x0004, /* CSR1 - Transmit Poll Demand Register */ + DmaRxPollDemand = 0x0008, /* CSR2 - Receive Poll Demand Register */ + DmaRxBaseAddr = 0x000C, /* CSR3 - Receive Descriptor list base address */ + DmaTxBaseAddr = 0x0010, /* CSR4 - Transmit Descriptor list base address */ + DmaStatus = 0x0014, /* CSR5 - Dma status Register */ + DmaControl = 0x0018, /* CSR6 - Dma Operation Mode Register */ + DmaInterrupt = 0x001C, /* CSR7 - Interrupt enable */ + DmaMissedFr = 0x0020, /* CSR8 - Missed Frame & Buffer overflow Counter */ + DmaTxCurrDesc = 0x0048, /* - Current host Tx Desc Register */ + DmaRxCurrDesc = 0x004C, /* - Current host Rx Desc Register */ + DmaTxCurrAddr = 0x0050, /* CSR20 - Current host transmit buffer address */ + DmaRxCurrAddr = 0x0054, /* CSR21 - Current host receive buffer address */ + + +}; + +/********************************************************** + * DMA Engine registers Layout + **********************************************************/ + +/*DmaBusMode = 0x0000, CSR0 - Bus Mode */ +enum DmaBusModeReg +{ + /* Bit description Bits R/W Reset value */ + + DmaFixedBurstEnable = 0x00010000, /* (FB)Fixed Burst SINGLE, INCR4, INCR8 or INCR16 16 RW */ + DmaFixedBurstDisable = 0x00000000, /* SINGLE, INCR 0 */ + + DmaTxPriorityRatio11 = 0x00000000, /* (PR)TX:RX DMA priority ratio 1:1 15:14 RW 00 */ + DmaTxPriorityRatio21 = 0x00004000, /* (PR)TX:RX DMA priority ratio 2:1 */ + DmaTxPriorityRatio31 = 0x00008000, /* (PR)TX:RX DMA priority ratio 3:1 */ + DmaTxPriorityRatio41 = 0x0000C000, /* (PR)TX:RX DMA priority ratio 4:1 */ + + DmaBurstLengthx8 = 0x01000000, /* When set mutiplies the PBL by 8 24 RW 0 */ + + DmaBurstLength256 = 0x01002000, /*(DmaBurstLengthx8 | DmaBurstLength32) = 256 [24]:13:8 */ + DmaBurstLength128 = 0x01001000, /*(DmaBurstLengthx8 | DmaBurstLength16) = 128 [24]:13:8 */ + DmaBurstLength64 = 0x01000800, /*(DmaBurstLengthx8 | DmaBurstLength8) = 64 [24]:13:8 */ + DmaBurstLength32 = 0x00002000, /* (PBL) programmable Dma burst length = 32 13:8 RW */ + DmaBurstLength16 = 0x00001000, /* Dma burst length = 16 */ + DmaBurstLength8 = 0x00000800, /* Dma burst length = 8 */ + DmaBurstLength4 = 0x00000400, /* Dma burst length = 4 */ + DmaBurstLength2 = 0x00000200, /* Dma burst length = 2 */ + DmaBurstLength1 = 0x00000100, /* Dma burst length = 1 */ + DmaBurstLength0 = 0x00000000, /* Dma burst length = 0 0x00 */ + + DmaDescriptor8Words = 0x00000080, /* Enh Descriptor works 1=> 8 word descriptor 7 0 */ + DmaDescriptor4Words = 0x00000000, /* Enh Descriptor works 0=> 4 word descriptor 7 0 */ + + DmaDescriptorSkip16 = 0x00000040, /* (DSL)Descriptor skip length (no.of dwords) 6:2 RW */ + DmaDescriptorSkip8 = 0x00000020, /* between two unchained descriptors */ + DmaDescriptorSkip4 = 0x00000010, /* */ + DmaDescriptorSkip2 = 0x00000008, /* */ + DmaDescriptorSkip1 = 0x00000004, /* */ + DmaDescriptorSkip0 = 0x00000000, /* 0x00 */ + + DmaArbitRr = 0x00000000, /* (DA) DMA RR arbitration 1 RW 0 */ + DmaArbitPr = 0x00000002, /* Rx has priority over Tx */ + + DmaResetOn = 0x00000001, /* (SWR)Software Reset DMA engine 0 RW */ + DmaResetOff = 0x00000000, /* 0 */ +}; + + +/*DmaStatus = 0x0014, CSR5 - Dma status Register */ +enum DmaStatusReg +{ + /*Bit 28 27 and 26 indicate whether the interrupt due to PMT GMACMMC or GMAC LINE Remaining bits are DMA interrupts*/ + + + GmacLPIIntr = 0x40000000, /* GMC LPI interrupt 31 RO 0 */ + + + GmacPmtIntr = 0x10000000, /* (GPI)Gmac subsystem interrupt 28 RO 0 */ + GmacMmcIntr = 0x08000000, /* (GMI)Gmac MMC subsystem interrupt 27 RO 0 */ + GmacLineIntfIntr = 0x04000000, /* Line interface interrupt 26 RO 0 */ + + DmaErrorBit2 = 0x02000000, /* (EB)Error bits 0-data buffer, 1-desc. access 25 RO 0 */ + DmaErrorBit1 = 0x01000000, /* (EB)Error bits 0-write trnsf, 1-read transfr 24 RO 0 */ + DmaErrorBit0 = 0x00800000, /* (EB)Error bits 0-Rx DMA, 1-Tx DMA 23 RO 0 */ + + DmaTxState = 0x00700000, /* (TS)Transmit process state 22:20 RO */ + DmaTxStopped = 0x00000000, /* Stopped - Reset or Stop Tx Command issued 000 */ + DmaTxFetching = 0x00100000, /* Running - fetching the Tx descriptor */ + DmaTxWaiting = 0x00200000, /* Running - waiting for status */ + DmaTxReading = 0x00300000, /* Running - reading the data from host memory */ + DmaTxSuspended = 0x00600000, /* Suspended - Tx Descriptor unavailabe */ + DmaTxClosing = 0x00700000, /* Running - closing Rx descriptor */ + + DmaRxState = 0x000E0000, /* (RS)Receive process state 19:17 RO */ + DmaRxStopped = 0x00000000, /* Stopped - Reset or Stop Rx Command issued 000 */ + DmaRxFetching = 0x00020000, /* Running - fetching the Rx descriptor */ + DmaRxWaiting = 0x00060000, /* Running - waiting for packet */ + DmaRxSuspended = 0x00080000, /* Suspended - Rx Descriptor unavailable */ + DmaRxClosing = 0x000A0000, /* Running - closing descriptor */ + DmaRxQueuing = 0x000E0000, /* Running - queuing the recieve frame into host memory */ + + DmaIntNormal = 0x00010000, /* (NIS)Normal interrupt summary 16 RW 0 */ + DmaIntAbnormal = 0x00008000, /* (AIS)Abnormal interrupt summary 15 RW 0 */ + + DmaIntEarlyRx = 0x00004000, /* Early receive interrupt (Normal) RW 0 */ + DmaIntBusError = 0x00002000, /* Fatal bus error (Abnormal) RW 0 */ + DmaIntEarlyTx = 0x00000400, /* Early transmit interrupt (Abnormal) RW 0 */ + DmaIntRxWdogTO = 0x00000200, /* Receive Watchdog Timeout (Abnormal) RW 0 */ + DmaIntRxStopped = 0x00000100, /* Receive process stopped (Abnormal) RW 0 */ + DmaIntRxNoBuffer = 0x00000080, /* Receive buffer unavailable (Abnormal) RW 0 */ + DmaIntRxCompleted = 0x00000040, /* Completion of frame reception (Normal) RW 0 */ + DmaIntTxUnderflow = 0x00000020, /* Transmit underflow (Abnormal) RW 0 */ + DmaIntRcvOverflow = 0x00000010, /* Receive Buffer overflow interrupt RW 0 */ + DmaIntTxJabberTO = 0x00000008, /* Transmit Jabber Timeout (Abnormal) RW 0 */ + DmaIntTxNoBuffer = 0x00000004, /* Transmit buffer unavailable (Normal) RW 0 */ + DmaIntTxStopped = 0x00000002, /* Transmit process stopped (Abnormal) RW 0 */ + DmaIntTxCompleted = 0x00000001, /* Transmit completed (Normal) RW 0 */ +}; + +/*DmaControl = 0x0018, CSR6 - Dma Operation Mode Register */ +enum DmaControlReg +{ + DmaDisableDropTcpCs = 0x04000000, /* (DT) Dis. drop. of tcp/ip CS error frames 26 RW 0 */ + + DmaStoreAndForward = 0x00200000, /* (SF)Store and forward 21 RW 0 */ + DmaFlushTxFifo = 0x00100000, /* (FTF)Tx FIFO controller is reset to default 20 RW 0 */ + + DmaTxThreshCtrl = 0x0001C000, /* (TTC)Controls thre Threh of MTL tx Fifo 16:14 RW */ + DmaTxThreshCtrl16 = 0x0001C000, /* (TTC)Controls thre Threh of MTL tx Fifo 16 16:14 RW */ + DmaTxThreshCtrl24 = 0x00018000, /* (TTC)Controls thre Threh of MTL tx Fifo 24 16:14 RW */ + DmaTxThreshCtrl32 = 0x00014000, /* (TTC)Controls thre Threh of MTL tx Fifo 32 16:14 RW */ + DmaTxThreshCtrl40 = 0x00010000, /* (TTC)Controls thre Threh of MTL tx Fifo 40 16:14 RW */ + DmaTxThreshCtrl256 = 0x0000c000, /* (TTC)Controls thre Threh of MTL tx Fifo 256 16:14 RW */ + DmaTxThreshCtrl192 = 0x00008000, /* (TTC)Controls thre Threh of MTL tx Fifo 192 16:14 RW */ + DmaTxThreshCtrl128 = 0x00004000, /* (TTC)Controls thre Threh of MTL tx Fifo 128 16:14 RW */ + DmaTxThreshCtrl64 = 0x00000000, /* (TTC)Controls thre Threh of MTL tx Fifo 64 16:14 RW 000 */ + + DmaTxStart = 0x00002000, /* (ST)Start/Stop transmission 13 RW 0 */ + + DmaRxFlowCtrlDeact = 0x00401800, /* (RFD)Rx flow control deact. threhold [22]:12:11 RW */ + DmaRxFlowCtrlDeact1K = 0x00000000, /* (RFD)Rx flow control deact. threhold (1kbytes) [22]:12:11 RW 00 */ + DmaRxFlowCtrlDeact2K = 0x00000800, /* (RFD)Rx flow control deact. threhold (2kbytes) [22]:12:11 RW */ + DmaRxFlowCtrlDeact3K = 0x00001000, /* (RFD)Rx flow control deact. threhold (3kbytes) [22]:12:11 RW */ + DmaRxFlowCtrlDeact4K = 0x00001800, /* (RFD)Rx flow control deact. threhold (4kbytes) [22]:12:11 RW */ + DmaRxFlowCtrlDeact5K = 0x00400000, /* (RFD)Rx flow control deact. threhold (4kbytes) [22]:12:11 RW */ + DmaRxFlowCtrlDeact6K = 0x00400800, /* (RFD)Rx flow control deact. threhold (4kbytes) [22]:12:11 RW */ + DmaRxFlowCtrlDeact7K = 0x00401000, /* (RFD)Rx flow control deact. threhold (4kbytes) [22]:12:11 RW */ + + DmaRxFlowCtrlAct = 0x00800600, /* (RFA)Rx flow control Act. threhold [23]:10:09 RW */ + DmaRxFlowCtrlAct1K = 0x00000000, /* (RFA)Rx flow control Act. threhold (1kbytes) [23]:10:09 RW 00 */ + DmaRxFlowCtrlAct2K = 0x00000200, /* (RFA)Rx flow control Act. threhold (2kbytes) [23]:10:09 RW */ + DmaRxFlowCtrlAct3K = 0x00000400, /* (RFA)Rx flow control Act. threhold (3kbytes) [23]:10:09 RW */ + DmaRxFlowCtrlAct4K = 0x00000300, /* (RFA)Rx flow control Act. threhold (4kbytes) [23]:10:09 RW */ + DmaRxFlowCtrlAct5K = 0x00800000, /* (RFA)Rx flow control Act. threhold (5kbytes) [23]:10:09 RW */ + DmaRxFlowCtrlAct6K = 0x00800200, /* (RFA)Rx flow control Act. threhold (6kbytes) [23]:10:09 RW */ + DmaRxFlowCtrlAct7K = 0x00800400, /* (RFA)Rx flow control Act. threhold (7kbytes) [23]:10:09 RW */ + + DmaRxThreshCtrl = 0x00000018, /* (RTC)Controls thre Threh of MTL rx Fifo 4:3 RW */ + DmaRxThreshCtrl64 = 0x00000000, /* (RTC)Controls thre Threh of MTL tx Fifo 64 4:3 RW */ + DmaRxThreshCtrl32 = 0x00000008, /* (RTC)Controls thre Threh of MTL tx Fifo 32 4:3 RW */ + DmaRxThreshCtrl96 = 0x00000010, /* (RTC)Controls thre Threh of MTL tx Fifo 96 4:3 RW */ + DmaRxThreshCtrl128 = 0x00000018, /* (RTC)Controls thre Threh of MTL tx Fifo 128 4:3 RW */ + + DmaEnHwFlowCtrl = 0x00000100, /* (EFC)Enable HW flow control 8 RW */ + DmaDisHwFlowCtrl = 0x00000000, /* Disable HW flow control 0 */ + + DmaFwdErrorFrames = 0x00000080, /* (FEF)Forward error frames 7 RW 0 */ + DmaFwdUnderSzFrames = 0x00000040, /* (FUF)Forward undersize frames 6 RW 0 */ + DmaTxSecondFrame = 0x00000004, /* (OSF)Operate on second frame 4 RW 0 */ + DmaRxStart = 0x00000002, /* (SR)Start/Stop reception 1 RW 0 */ +}; + + +/*DmaInterrupt = 0x001C, CSR7 - Interrupt enable Register Layout */ +enum DmaInterruptReg +{ + DmaIeNormal = DmaIntNormal, /* Normal interrupt enable RW 0 */ + DmaIeAbnormal = DmaIntAbnormal, /* Abnormal interrupt enable RW 0 */ + + DmaIeEarlyRx = DmaIntEarlyRx, /* Early receive interrupt enable RW 0 */ + DmaIeBusError = DmaIntBusError, /* Fatal bus error enable RW 0 */ + DmaIeEarlyTx = DmaIntEarlyTx, /* Early transmit interrupt enable RW 0 */ + DmaIeRxWdogTO = DmaIntRxWdogTO, /* Receive Watchdog Timeout enable RW 0 */ + DmaIeRxStopped = DmaIntRxStopped, /* Receive process stopped enable RW 0 */ + DmaIeRxNoBuffer = DmaIntRxNoBuffer, /* Receive buffer unavailable enable RW 0 */ + DmaIeRxCompleted = DmaIntRxCompleted, /* Completion of frame reception enable RW 0 */ + DmaIeTxUnderflow = DmaIntTxUnderflow, /* Transmit underflow enable RW 0 */ + + DmaIeRxOverflow = DmaIntRcvOverflow, /* Receive Buffer overflow interrupt RW 0 */ + DmaIeTxJabberTO = DmaIntTxJabberTO, /* Transmit Jabber Timeout enable RW 0 */ + DmaIeTxNoBuffer = DmaIntTxNoBuffer, /* Transmit buffer unavailable enable RW 0 */ + DmaIeTxStopped = DmaIntTxStopped, /* Transmit process stopped enable RW 0 */ + DmaIeTxCompleted = DmaIntTxCompleted, /* Transmit completed enable RW 0 */ +}; + + +/********************************************************** + * DMA Engine descriptors + **********************************************************/ + +/* +**********Enhanced Descritpor structure to support 8K buffer per buffer **************************** + +DmaRxBaseAddr = 0x000C, CSR3 - Receive Descriptor list base address +DmaRxBaseAddr is the pointer to the first Rx Descriptors. the Descriptor format in Little endian with a +32 bit Data bus is as shown below + +Similarly +DmaTxBaseAddr = 0x0010, CSR4 - Transmit Descriptor list base address +DmaTxBaseAddr is the pointer to the first Rx Descriptors. the Descriptor format in Little endian with a +32 bit Data bus is as shown below + -------------------------------------------------------------------------- + RDES0 |OWN (31)| Status | + -------------------------------------------------------------------------- + RDES1 | Ctrl | Res | Byte Count Buffer 2 | Ctrl | Res | Byte Count Buffer 1 | + -------------------------------------------------------------------------- + RDES2 | Buffer 1 Address | + -------------------------------------------------------------------------- + RDES3 | Buffer 2 Address / Next Descriptor Address | + -------------------------------------------------------------------------- + + -------------------------------------------------------------------------- + TDES0 |OWN (31)| Ctrl | Res | Ctrl | Res | Status | + -------------------------------------------------------------------------- + TDES1 | Res | Byte Count Buffer 2 | Res | Byte Count Buffer 1 | + -------------------------------------------------------------------------- + TDES2 | Buffer 1 Address | + -------------------------------------------------------------------------- + TDES3 | Buffer 2 Address / Next Descriptor Address | + -------------------------------------------------------------------------- + +*/ + +enum DmaDescriptorStatus /* status word of DMA descriptor */ +{ + + DescOwnByDma = 0x80000000, /* (OWN)Descriptor is owned by DMA engine 31 RW */ + + DescDAFilterFail = 0x40000000, /* (AFM)Rx - DA Filter Fail for the rx frame 30 */ + + DescFrameLengthMask = 0x3FFF0000, /* (FL)Receive descriptor frame length 29:16 */ + DescFrameLengthShift = 16, + + DescError = 0x00008000, /* (ES)Error summary bit - OR of the follo. bits: 15 */ + /* DE || OE || IPC || LC || RWT || RE || CE */ + DescRxTruncated = 0x00004000, /* (DE)Rx - no more descriptors for receive frame 14 */ + DescSAFilterFail = 0x00002000, /* (SAF)Rx - SA Filter Fail for the received frame 13 */ + DescRxLengthError = 0x00001000, /* (LE)Rx - frm size not matching with len field 12 */ + DescRxDamaged = 0x00000800, /* (OE)Rx - frm was damaged due to buffer overflow 11 */ + DescRxVLANTag = 0x00000400, /* (VLAN)Rx - received frame is a VLAN frame 10 */ + DescRxFirst = 0x00000200, /* (FS)Rx - first descriptor of the frame 9 */ + DescRxLast = 0x00000100, /* (LS)Rx - last descriptor of the frame 8 */ + DescRxLongFrame = 0x00000080, /* (Giant Frame)Rx - frame is longer than 1518/1522 7 */ + DescRxTSAvailable = 0x00000080, /* Share bit with (Giant Frame)Rx 7 */ + DescRxCollision = 0x00000040, /* (LC)Rx - late collision occurred during reception 6 */ + DescRxFrameEther = 0x00000020, /* (FT)Rx - Frame type - Ethernet, otherwise 802.3 5 */ + DescRxWatchdog = 0x00000010, /* (RWT)Rx - watchdog timer expired during reception 4 */ + DescRxMiiError = 0x00000008, /* (RE)Rx - error reported by MII interface 3 */ + DescRxDribbling = 0x00000004, /* (DE)Rx - frame contains non int multiple of 8 bits 2 */ + DescRxCrc = 0x00000002, /* (CE)Rx - CRC error 1 */ +// DescRxMacMatch = 0x00000001, /* (RX MAC Address) Rx mac address reg(1 to 15)match 0 */ + + DescRxEXTsts = 0x00000001, /* Extended Status Available (RDES4) 0 */ + + DescTxIntEnable = 0x40000000, /* (IC)Tx - interrupt on completion 30 */ + DescTxLast = 0x20000000, /* (LS)Tx - Last segment of the frame 29 */ + DescTxFirst = 0x10000000, /* (FS)Tx - First segment of the frame 28 */ + DescTxDisableCrc = 0x08000000, /* (DC)Tx - Add CRC disabled (first segment only) 27 */ + DescTxDisablePadd = 0x04000000, /* (DP)disable padding, added by - reyaz 26 */ + DescTxTSEnable = 0x02000000, /* (TTSE) Transmit Timestamp Enable 25 */ + DescTxCrcReplacement = 0x01000000, /* (CRCR) CRC Replacement Control 24 */ + DescTxCisMask = 0x00c00000, /* Tx checksum offloading control mask 23:22 */ + DescTxCisBypass = 0x00000000, /* Checksum bypass */ + DescTxCisIpv4HdrCs = 0x00400000, /* IPv4 header checksum */ + DescTxCisTcpOnlyCs = 0x00800000, /* TCP/UDP/ICMP checksum. Pseudo header checksum is assumed to be present */ + DescTxCisTcpPseudoCs = 0x00c00000, /* TCP/UDP/ICMP checksum fully in hardware including pseudo header */ + + TxDescEndOfRing = 0x00200000, /* (TER)End of descriptors ring 21 */ + TxDescChain = 0x00100000, /* (TCH)Second buffer address is chain address 20 */ + + DescRxChkBit0 = 0x00000001, /*() Rx - Rx Payload Checksum Error 0 */ + DescRxChkBit7 = 0x00000080, /* (IPC CS ERROR)Rx - Ipv4 header checksum error 7 */ + DescRxChkBit5 = 0x00000020, /* (FT)Rx - Frame type - Ethernet, otherwise 802.3 5 */ + + DescRxTSavail = 0x00000080, /* Time stamp available 7 */ + DescRxFrameType = 0x00000020, /* (FT)Rx - Frame type - Ethernet, otherwise 802.3 5 */ + DescTxTSStatus = 0x00020000, /* (TTSS) Transmit Timestamp Status 17 */ + DescTxIpv4ChkError = 0x00010000, /* (IHE) Tx Ip header error 16 */ + DescTxTimeout = 0x00004000, /* (JT)Tx - Transmit jabber timeout 14 */ + DescTxFrameFlushed = 0x00002000, /* (FF)Tx - DMA/MTL flushed the frame due to SW flush 13 */ + DescTxPayChkError = 0x00001000, /* (PCE) Tx Payload checksum Error 12 */ + DescTxLostCarrier = 0x00000800, /* (LC)Tx - carrier lost during tramsmission 11 */ + DescTxNoCarrier = 0x00000400, /* (NC)Tx - no carrier signal from the tranceiver 10 */ + DescTxLateCollision = 0x00000200, /* (LC)Tx - transmission aborted due to collision 9 */ + DescTxExcCollisions = 0x00000100, /* (EC)Tx - transmission aborted after 16 collisions 8 */ + DescTxVLANFrame = 0x00000080, /* (VF)Tx - VLAN-type frame 7 */ + + DescTxCollMask = 0x00000078, /* (CC)Tx - Collision count 6:3 */ + DescTxCollShift = 3, + + DescTxExcDeferral = 0x00000004, /* (ED)Tx - excessive deferral 2 */ + DescTxUnderflow = 0x00000002, /* (UF)Tx - late data arrival from the memory 1 */ + DescTxDeferred = 0x00000001, /* (DB)Tx - frame transmision deferred 0 */ + + /* + This explains the RDES1/TDES1 bits layout + -------------------------------------------------------------------- + RDES1/TDES1 | Control Bits | Byte Count Buffer 2 | Byte Count Buffer 1 | + -------------------------------------------------------------------- + + */ +// DmaDescriptorLength length word of DMA descriptor + + + RxDisIntCompl = 0x80000000, /* (Disable Rx int on completion) 31 */ + RxDescEndOfRing = 0x00008000, /* (TER)End of descriptors ring 15 */ + RxDescChain = 0x00004000, /* (TCH)Second buffer address is chain address 14 */ + + + DescSize2Mask = 0x1FFF0000, /* (TBS2) Buffer 2 size 28:16 */ + DescSize2Shift = 16, + DescSize1Mask = 0x00001FFF, /* (TBS1) Buffer 1 size 12:0 */ + DescSize1Shift = 0, + + + /* + This explains the RDES4 Extended Status bits layout + -------------------------------------------------------------------- + RDES4 | Extended Status | + -------------------------------------------------------------------- + */ + + DescRxPtpAvail = 0x00004000, /* PTP snapshot available 14 */ + DescRxPtpVer = 0x00002000, /* When set indicates IEEE1584 Version 2 (else Ver1) 13 */ + DescRxPtpFrameType = 0x00001000, /* PTP frame type Indicates PTP sent over ethernet 12 */ + DescRxPtpMessageType = 0x00000F00, /* Message Type 11:8 */ + DescRxPtpNo = 0x00000000, /* 0000 => No PTP message received */ + DescRxPtpSync = 0x00000100, /* 0001 => Sync (all clock types) received */ + DescRxPtpFollowUp = 0x00000200, /* 0010 => Follow_Up (all clock types) received */ + DescRxPtpDelayReq = 0x00000300, /* 0011 => Delay_Req (all clock types) received */ + DescRxPtpDelayResp = 0x00000400, /* 0100 => Delay_Resp (all clock types) received */ + DescRxPtpPdelayReq = 0x00000500, /* 0101 => Pdelay_Req (in P to P tras clk) or Announce in Ord and Bound clk */ + DescRxPtpPdelayResp = 0x00000600, /* 0110 => Pdealy_Resp(in P to P trans clk) or Management in Ord and Bound clk */ + DescRxPtpPdelayRespFP = 0x00000700, /* 0111 => Pdealy_Resp_Follow_Up (in P to P trans clk) or Signaling in Ord and Bound clk */ + DescRxPtpIPV6 = 0x00000080, /* Received Packet is in IPV6 Packet 7 */ + DescRxPtpIPV4 = 0x00000040, /* Received Packet is in IPV4 Packet 6 */ + + DescRxChkSumBypass = 0x00000020, /* When set indicates checksum offload engine 5 + is bypassed */ + DescRxIpPayloadError = 0x00000010, /* When set indicates 16bit IP payload CS is in error 4 */ + DescRxIpHeaderError = 0x00000008, /* When set indicates 16bit IPV4 header CS is in 3 + error or IP datagram version is not consistent + with Ethernet type value */ + DescRxIpPayloadType = 0x00000007, /* Indicate the type of payload encapsulated 2:0 + in IPdatagram processed by COE (Rx) */ + DescRxIpPayloadUnknown = 0x00000000, /* Unknown or didnot process IP payload */ + DescRxIpPayloadUDP = 0x00000001, /* UDP */ + DescRxIpPayloadTCP = 0x00000002, /* TCP */ + DescRxIpPayloadICMP = 0x00000003, /* ICMP */ + +}; + + +// Rx Descriptor COE type2 encoding +enum RxDescCOEEncode +{ + RxLenLT600 = 0, /* Bit(5:7:0)=>0 IEEE 802.3 type frame Length field is Lessthan 0x0600 */ + RxIpHdrPayLoadChkBypass = 1, /* Bit(5:7:0)=>1 Payload & Ip header checksum bypassed (unsuppported payload) */ + RxIpHdrPayLoadRes = 2, /* Bit(5:7:0)=>2 Reserved */ + RxChkBypass = 3, /* Bit(5:7:0)=>3 Neither IPv4 nor IPV6. So checksum bypassed */ + RxNoChkError = 4, /* Bit(5:7:0)=>4 No IPv4/IPv6 Checksum error detected */ + RxPayLoadChkError = 5, /* Bit(5:7:0)=>5 Payload checksum error detected for Ipv4/Ipv6 frames */ + RxIpHdrChkError = 6, /* Bit(5:7:0)=>6 Ip header checksum error detected for Ipv4 frames */ + RxIpHdrPayLoadChkError = 7, /* Bit(5:7:0)=>7 Payload & Ip header checksum error detected for Ipv4/Ipv6 frames */ +}; + +/********************************************************** + * DMA engine interrupt handling functions + **********************************************************/ + +enum synopGMACDmaIntEnum /* Intrerrupt types */ +{ + synopGMACDmaRxNormal = 0x01, /* normal receiver interrupt */ + synopGMACDmaRxAbnormal = 0x02, /* abnormal receiver interrupt */ + synopGMACDmaRxStopped = 0x04, /* receiver stopped */ + synopGMACDmaTxNormal = 0x08, /* normal transmitter interrupt */ + synopGMACDmaTxAbnormal = 0x10, /* abnormal transmitter interrupt */ + synopGMACDmaTxStopped = 0x20, /* transmitter stopped */ + synopGMACDmaError = 0x80, /* Dma engine error */ + +}; + + +/********************************************************** + * Initial register values + **********************************************************/ +enum InitialRegisters +{ + /* Full-duplex mode with perfect filter on */ + GmacConfigInitFdx1000 = GmacWatchdogEnable | GmacJabberEnable | GmacFrameBurstEnable | GmacJumboFrameDisable + | GmacSelectGmii | GmacEnableRxOwn | GmacLoopbackOff + | GmacFullDuplex | GmacRetryEnable | GmacPadCrcStripDisable + | GmacBackoffLimit0 | GmacDeferralCheckDisable | GmacTxEnable | GmacRxEnable, + + /* Full-duplex mode with perfect filter on */ + GmacConfigInitFdx110 = GmacWatchdogEnable | GmacJabberEnable | GmacFrameBurstEnable | GmacJumboFrameDisable + | GmacSelectMii | GmacEnableRxOwn | GmacLoopbackOff + | GmacFullDuplex | GmacRetryEnable | GmacPadCrcStripDisable + | GmacBackoffLimit0 | GmacDeferralCheckDisable | GmacTxEnable | GmacRxEnable, + + /* Full-duplex mode */ + // CHANGED: Pass control config, dest addr filter normal, added source address filter, multicast & unicast + // Hash filter. + /* = GmacFilterOff | GmacPassControlOff | GmacBroadcastEnable */ + GmacFrameFilterInitFdx = GmacFilterOn | GmacPassControl0 | GmacBroadcastEnable | GmacSrcAddrFilterDisable + | GmacMulticastFilterOn | GmacDestAddrFilterNor | GmacMcastHashFilterOff + | GmacPromiscuousModeOff | GmacUcastHashFilterOff, + + /* Full-duplex mode */ + GmacFlowControlInitFdx = GmacUnicastPauseFrameOff | GmacRxFlowControlEnable | GmacTxFlowControlEnable, + + /* Full-duplex mode */ + GmacGmiiAddrInitFdx = GmiiCsrClk2, + + + /* Half-duplex mode with perfect filter on */ + // CHANGED: Removed Endian configuration, added single bit config for PAD/CRC strip, + /*| GmacSelectMii | GmacLittleEndian | GmacDisableRxOwn | GmacLoopbackOff*/ + GmacConfigInitHdx1000 = GmacWatchdogEnable | GmacJabberEnable | GmacFrameBurstEnable | GmacJumboFrameDisable + | GmacSelectGmii | GmacDisableRxOwn | GmacLoopbackOff + | GmacHalfDuplex | GmacRetryEnable | GmacPadCrcStripDisable + | GmacBackoffLimit0 | GmacDeferralCheckDisable | GmacTxEnable | GmacRxEnable, + + /* Half-duplex mode with perfect filter on */ + GmacConfigInitHdx110 = GmacWatchdogEnable | GmacJabberEnable | GmacFrameBurstEnable | GmacJumboFrameDisable + | GmacSelectMii | GmacDisableRxOwn | GmacLoopbackOff + | GmacHalfDuplex | GmacRetryEnable | GmacPadCrcStripDisable + | GmacBackoffLimit0 | GmacDeferralCheckDisable | GmacTxEnable | GmacRxEnable, + + /* Half-duplex mode */ + GmacFrameFilterInitHdx = GmacFilterOn | GmacPassControl0 | GmacBroadcastEnable | GmacSrcAddrFilterDisable + | GmacMulticastFilterOn | GmacDestAddrFilterNor | GmacMcastHashFilterOff + | GmacUcastHashFilterOff | GmacPromiscuousModeOff, + + /* Half-duplex mode */ + GmacFlowControlInitHdx = GmacUnicastPauseFrameOff | GmacRxFlowControlDisable | GmacTxFlowControlDisable, + + /* Half-duplex mode */ + GmacGmiiAddrInitHdx = GmiiCsrClk2, + + + + /********************************************** + *DMA configurations + **********************************************/ + + DmaBusModeInit = DmaFixedBurstEnable | DmaBurstLength8 | DmaDescriptorSkip2 | DmaResetOff, +// DmaBusModeInit = DmaFixedBurstEnable | DmaBurstLength8 | DmaDescriptorSkip4 | DmaResetOff, + + /* 1000 Mb/s mode */ + DmaControlInit1000 = DmaStoreAndForward,// | DmaTxSecondFrame , + + /* 100 Mb/s mode */ + DmaControlInit100 = DmaStoreAndForward, + + /* 10 Mb/s mode */ + DmaControlInit10 = DmaStoreAndForward, + + /* Interrupt groups */ + DmaIntErrorMask = DmaIntBusError, /* Error */ + DmaIntRxAbnMask = DmaIntRxNoBuffer, /* receiver abnormal interrupt */ + DmaIntRxNormMask = DmaIntRxCompleted, /* receiver normal interrupt */ + DmaIntRxStoppedMask = DmaIntRxStopped, /* receiver stopped */ + DmaIntTxAbnMask = DmaIntTxUnderflow, /* transmitter abnormal interrupt */ + DmaIntTxNormMask = DmaIntTxCompleted, /* transmitter normal interrupt */ + DmaIntTxStoppedMask = DmaIntTxStopped, /* transmitter stopped */ + + DmaIntEnable = DmaIeNormal | DmaIeAbnormal | DmaIntErrorMask + | DmaIntRxAbnMask | DmaIntRxNormMask | DmaIntRxStoppedMask + | DmaIntTxAbnMask | DmaIntTxNormMask | DmaIntTxStoppedMask, + DmaIntDisable = 0, +}; + + +/********************************************************** + * Mac Management Counters (MMC) + **********************************************************/ + +enum MMC_ENABLE +{ + GmacMmcCntrl = 0x0100, /* mmc control for operating mode of MMC */ + GmacMmcIntrRx = 0x0104, /* maintains interrupts generated by rx counters */ + GmacMmcIntrTx = 0x0108, /* maintains interrupts generated by tx counters */ + GmacMmcIntrMaskRx = 0x010C, /* mask for interrupts generated from rx counters */ + GmacMmcIntrMaskTx = 0x0110, /* mask for interrupts generated from tx counters */ +}; +enum MMC_TX +{ + GmacMmcTxOctetCountGb = 0x0114, /*Bytes Tx excl. of preamble and retried bytes (Good or Bad) */ + GmacMmcTxFrameCountGb = 0x0118, /*Frames Tx excl. of retried frames (Good or Bad) */ + GmacMmcTxBcFramesG = 0x011C, /*Broadcast Frames Tx (Good) */ + GmacMmcTxMcFramesG = 0x0120, /*Multicast Frames Tx (Good) */ + + GmacMmcTx64OctetsGb = 0x0124, /*Tx with len 64 bytes excl. of pre and retried (Good or Bad) */ + GmacMmcTx65To127OctetsGb = 0x0128, /*Tx with len >64 bytes <=127 excl. of pre and retried (Good or Bad) */ + GmacMmcTx128To255OctetsGb = 0x012C, /*Tx with len >128 bytes <=255 excl. of pre and retried (Good or Bad) */ + GmacMmcTx256To511OctetsGb = 0x0130, /*Tx with len >256 bytes <=511 excl. of pre and retried (Good or Bad) */ + GmacMmcTx512To1023OctetsGb = 0x0134, /*Tx with len >512 bytes <=1023 excl. of pre and retried (Good or Bad) */ + GmacMmcTx1024ToMaxOctetsGb = 0x0138, /*Tx with len >1024 bytes <=MaxSize excl. of pre and retried (Good or Bad) */ + + GmacMmcTxUcFramesGb = 0x013C, /*Unicast Frames Tx (Good or Bad) */ + GmacMmcTxMcFramesGb = 0x0140, /*Multicast Frames Tx (Good and Bad) */ + GmacMmcTxBcFramesGb = 0x0144, /*Broadcast Frames Tx (Good and Bad) */ + GmacMmcTxUnderFlowError = 0x0148, /*Frames aborted due to Underflow error */ + GmacMmcTxSingleColG = 0x014C, /*Successfully Tx Frames after singel collision in Half duplex mode */ + GmacMmcTxMultiColG = 0x0150, /*Successfully Tx Frames after more than singel collision in Half duplex mode */ + GmacMmcTxDeferred = 0x0154, /*Successfully Tx Frames after a deferral in Half duplex mode */ + GmacMmcTxLateCol = 0x0158, /*Frames aborted due to late collision error */ + GmacMmcTxExessCol = 0x015C, /*Frames aborted due to excessive (16) collision errors */ + GmacMmcTxCarrierError = 0x0160, /*Frames aborted due to carrier sense error (No carrier or Loss of carrier) */ + GmacMmcTxOctetCountG = 0x0164, /*Bytes Tx excl. of preamble and retried bytes (Good) */ + GmacMmcTxFrameCountG = 0x0168, /*Frames Tx (Good) */ + GmacMmcTxExessDef = 0x016C, /*Frames aborted due to excessive deferral errors (deferred for more than 2 max-sized frame times)*/ + + GmacMmcTxPauseFrames = 0x0170, /*Number of good pause frames Tx. */ + GmacMmcTxVlanFramesG = 0x0174, /*Number of good Vlan frames Tx excl. retried frames */ +}; +enum MMC_RX +{ + GmacMmcRxFrameCountGb = 0x0180, /*Frames Rx (Good or Bad) */ + GmacMmcRxOctetCountGb = 0x0184, /*Bytes Rx excl. of preamble and retried bytes (Good or Bad) */ + GmacMmcRxOctetCountG = 0x0188, /*Bytes Rx excl. of preamble and retried bytes (Good) */ + GmacMmcRxBcFramesG = 0x018C, /*Broadcast Frames Rx (Good) */ + GmacMmcRxMcFramesG = 0x0190, /*Multicast Frames Rx (Good) */ + + GmacMmcRxCrcError = 0x0194, /*Number of frames received with CRC error */ + GmacMmcRxAlignError = 0x0198, /*Number of frames received with alignment (dribble) error. Only in 10/100mode */ + GmacMmcRxRuntError = 0x019C, /*Number of frames received with runt (<64 bytes and CRC error) error */ + GmacMmcRxJabberError = 0x01A0, /*Number of frames rx with jabber (>1518/1522 or >9018/9022 and CRC) */ + GmacMmcRxUnderSizeG = 0x01A4, /*Number of frames received with <64 bytes without any error */ + GmacMmcRxOverSizeG = 0x01A8, /*Number of frames received with >1518/1522 bytes without any error */ + + GmacMmcRx64OctetsGb = 0x01AC, /*Rx with len 64 bytes excl. of pre and retried (Good or Bad) */ + GmacMmcRx65To127OctetsGb = 0x01B0, /*Rx with len >64 bytes <=127 excl. of pre and retried (Good or Bad) */ + GmacMmcRx128To255OctetsGb = 0x01B4, /*Rx with len >128 bytes <=255 excl. of pre and retried (Good or Bad) */ + GmacMmcRx256To511OctetsGb = 0x01B8, /*Rx with len >256 bytes <=511 excl. of pre and retried (Good or Bad) */ + GmacMmcRx512To1023OctetsGb = 0x01BC, /*Rx with len >512 bytes <=1023 excl. of pre and retried (Good or Bad) */ + GmacMmcRx1024ToMaxOctetsGb = 0x01C0, /*Rx with len >1024 bytes <=MaxSize excl. of pre and retried (Good or Bad) */ + + GmacMmcRxUcFramesG = 0x01C4, /*Unicast Frames Rx (Good) */ + GmacMmcRxLengthError = 0x01C8, /*Number of frames received with Length type field != frame size */ + GmacMmcRxOutOfRangeType = 0x01CC, /*Number of frames received with length field != valid frame size */ + + GmacMmcRxPauseFrames = 0x01D0, /*Number of good pause frames Rx. */ + GmacMmcRxFifoOverFlow = 0x01D4, /*Number of missed rx frames due to FIFO overflow */ + GmacMmcRxVlanFramesGb = 0x01D8, /*Number of good Vlan frames Rx */ + + GmacMmcRxWatchdobError = 0x01DC, /*Number of frames rx with error due to watchdog timeout error */ +}; +enum MMC_IP_RELATED +{ + GmacMmcRxIpcIntrMask = 0x0200, /*Maintains the mask for interrupt generated from rx IPC statistic counters */ + GmacMmcRxIpcIntr = 0x0208, /*Maintains the interrupt that rx IPC statistic counters generate */ + + GmacMmcRxIpV4FramesG = 0x0210, /*Good IPV4 datagrams received */ + GmacMmcRxIpV4HdrErrFrames = 0x0214, /*Number of IPV4 datagrams received with header errors */ + GmacMmcRxIpV4NoPayFrames = 0x0218, /*Number of IPV4 datagrams received which didnot have TCP/UDP/ICMP payload */ + GmacMmcRxIpV4FragFrames = 0x021C, /*Number of IPV4 datagrams received with fragmentation */ + GmacMmcRxIpV4UdpChkDsblFrames = 0x0220, /*Number of IPV4 datagrams received that had a UDP payload checksum disabled */ + + GmacMmcRxIpV6FramesG = 0x0224, /*Good IPV6 datagrams received */ + GmacMmcRxIpV6HdrErrFrames = 0x0228, /*Number of IPV6 datagrams received with header errors */ + GmacMmcRxIpV6NoPayFrames = 0x022C, /*Number of IPV6 datagrams received which didnot have TCP/UDP/ICMP payload */ + + GmacMmcRxUdpFramesG = 0x0230, /*Number of good IP datagrams with good UDP payload */ + GmacMmcRxUdpErrorFrames = 0x0234, /*Number of good IP datagrams with UDP payload having checksum error */ + + GmacMmcRxTcpFramesG = 0x0238, /*Number of good IP datagrams with good TDP payload */ + GmacMmcRxTcpErrorFrames = 0x023C, /*Number of good IP datagrams with TCP payload having checksum error */ + + GmacMmcRxIcmpFramesG = 0x0240, /*Number of good IP datagrams with good Icmp payload */ + GmacMmcRxIcmpErrorFrames = 0x0244, /*Number of good IP datagrams with Icmp payload having checksum error */ + + GmacMmcRxIpV4OctetsG = 0x0250, /*Good IPV4 datagrams received excl. Ethernet hdr,FCS,Pad,Ip Pad bytes */ + GmacMmcRxIpV4HdrErrorOctets = 0x0254, /*Number of bytes in IPV4 datagram with header errors */ + GmacMmcRxIpV4NoPayOctets = 0x0258, /*Number of bytes in IPV4 datagram with no TCP/UDP/ICMP payload */ + GmacMmcRxIpV4FragOctets = 0x025C, /*Number of bytes received in fragmented IPV4 datagrams */ + GmacMmcRxIpV4UdpChkDsblOctets = 0x0260, /*Number of bytes received in UDP segment that had UDP checksum disabled */ + + GmacMmcRxIpV6OctetsG = 0x0264, /*Good IPV6 datagrams received excl. Ethernet hdr,FCS,Pad,Ip Pad bytes */ + GmacMmcRxIpV6HdrErrorOctets = 0x0268, /*Number of bytes in IPV6 datagram with header errors */ + GmacMmcRxIpV6NoPayOctets = 0x026C, /*Number of bytes in IPV6 datagram with no TCP/UDP/ICMP payload */ + + GmacMmcRxUdpOctetsG = 0x0270, /*Number of bytes in IP datagrams with good UDP payload */ + GmacMmcRxUdpErrorOctets = 0x0274, /*Number of bytes in IP datagrams with UDP payload having checksum error */ + + GmacMmcRxTcpOctetsG = 0x0278, /*Number of bytes in IP datagrams with good TDP payload */ + GmacMmcRxTcpErrorOctets = 0x027C, /*Number of bytes in IP datagrams with TCP payload having checksum error */ + + GmacMmcRxIcmpOctetsG = 0x0280, /*Number of bytes in IP datagrams with good Icmp payload */ + GmacMmcRxIcmpErrorOctets = 0x0284, /*Number of bytes in IP datagrams with Icmp payload having checksum error */ +}; + + +enum MMC_CNTRL_REG_BIT_DESCRIPTIONS +{ + GmacMmcCounterFreeze = 0x00000008, /* when set MMC counters freeze to current value */ + GmacMmcCounterResetOnRead = 0x00000004, /* when set MMC counters will be reset to 0 after read */ + GmacMmcCounterStopRollover = 0x00000002, /* when set counters will not rollover after max value */ + GmacMmcCounterReset = 0x00000001, /* when set all counters wil be reset (automatically cleared after 1 clk) */ + +}; + +enum MMC_RX_INTR_MASK_AND_STATUS_BIT_DESCRIPTIONS +{ + GmacMmcRxWDInt = 0x00800000, /* set when rxwatchdog error reaches half of max value */ + GmacMmcRxVlanInt = 0x00400000, /* set when GmacMmcRxVlanFramesGb counter reaches half of max value */ + GmacMmcRxFifoOverFlowInt = 0x00200000, /* set when GmacMmcRxFifoOverFlow counter reaches half of max value */ + GmacMmcRxPauseFrameInt = 0x00100000, /* set when GmacMmcRxPauseFrames counter reaches half of max value */ + GmacMmcRxOutOfRangeInt = 0x00080000, /* set when GmacMmcRxOutOfRangeType counter reaches half of max value */ + GmacMmcRxLengthErrorInt = 0x00040000, /* set when GmacMmcRxLengthError counter reaches half of max value */ + GmacMmcRxUcFramesInt = 0x00020000, /* set when GmacMmcRxUcFramesG counter reaches half of max value */ + GmacMmcRx1024OctInt = 0x00010000, /* set when GmacMmcRx1024ToMaxOctetsGb counter reaches half of max value */ + GmacMmcRx512OctInt = 0x00008000, /* set when GmacMmcRx512To1023OctetsGb counter reaches half of max value */ + GmacMmcRx256OctInt = 0x00004000, /* set when GmacMmcRx256To511OctetsGb counter reaches half of max value */ + GmacMmcRx128OctInt = 0x00002000, /* set when GmacMmcRx128To255OctetsGb counter reaches half of max value */ + GmacMmcRx65OctInt = 0x00001000, /* set when GmacMmcRx65To127OctetsG counter reaches half of max value */ + GmacMmcRx64OctInt = 0x00000800, /* set when GmacMmcRx64OctetsGb counter reaches half of max value */ + GmacMmcRxOverSizeInt = 0x00000400, /* set when GmacMmcRxOverSizeG counter reaches half of max value */ + GmacMmcRxUnderSizeInt = 0x00000200, /* set when GmacMmcRxUnderSizeG counter reaches half of max value */ + GmacMmcRxJabberErrorInt = 0x00000100, /* set when GmacMmcRxJabberError counter reaches half of max value */ + GmacMmcRxRuntErrorInt = 0x00000080, /* set when GmacMmcRxRuntError counter reaches half of max value */ + GmacMmcRxAlignErrorInt = 0x00000040, /* set when GmacMmcRxAlignError counter reaches half of max value */ + GmacMmcRxCrcErrorInt = 0x00000020, /* set when GmacMmcRxCrcError counter reaches half of max value */ + GmacMmcRxMcFramesInt = 0x00000010, /* set when GmacMmcRxMcFramesG counter reaches half of max value */ + GmacMmcRxBcFramesInt = 0x00000008, /* set when GmacMmcRxBcFramesG counter reaches half of max value */ + GmacMmcRxOctetGInt = 0x00000004, /* set when GmacMmcRxOctetCountG counter reaches half of max value */ + GmacMmcRxOctetGbInt = 0x00000002, /* set when GmacMmcRxOctetCountGb counter reaches half of max value */ + GmacMmcRxFrameInt = 0x00000001, /* set when GmacMmcRxFrameCountGb counter reaches half of max value */ +}; + +enum MMC_TX_INTR_MASK_AND_STATUS_BIT_DESCRIPTIONS +{ + + GmacMmcTxVlanInt = 0x01000000, /* set when GmacMmcTxVlanFramesG counter reaches half of max value */ + GmacMmcTxPauseFrameInt = 0x00800000, /* set when GmacMmcTxPauseFrames counter reaches half of max value */ + GmacMmcTxExessDefInt = 0x00400000, /* set when GmacMmcTxExessDef counter reaches half of max value */ + GmacMmcTxFrameInt = 0x00200000, /* set when GmacMmcTxFrameCount counter reaches half of max value */ + GmacMmcTxOctetInt = 0x00100000, /* set when GmacMmcTxOctetCountG counter reaches half of max value */ + GmacMmcTxCarrierErrorInt = 0x00080000, /* set when GmacMmcTxCarrierError counter reaches half of max value */ + GmacMmcTxExessColInt = 0x00040000, /* set when GmacMmcTxExessCol counter reaches half of max value */ + GmacMmcTxLateColInt = 0x00020000, /* set when GmacMmcTxLateCol counter reaches half of max value */ + GmacMmcTxDeferredInt = 0x00010000, /* set when GmacMmcTxDeferred counter reaches half of max value */ + GmacMmcTxMultiColInt = 0x00008000, /* set when GmacMmcTxMultiColG counter reaches half of max value */ + GmacMmcTxSingleCol = 0x00004000, /* set when GmacMmcTxSingleColG counter reaches half of max value */ + GmacMmcTxUnderFlowErrorInt = 0x00002000, /* set when GmacMmcTxUnderFlowError counter reaches half of max value */ + GmacMmcTxBcFramesGbInt = 0x00001000, /* set when GmacMmcTxBcFramesGb counter reaches half of max value */ + GmacMmcTxMcFramesGbInt = 0x00000800, /* set when GmacMmcTxMcFramesGb counter reaches half of max value */ + GmacMmcTxUcFramesInt = 0x00000400, /* set when GmacMmcTxUcFramesGb counter reaches half of max value */ + GmacMmcTx1024OctInt = 0x00000200, /* set when GmacMmcTx1024ToMaxOctetsGb counter reaches half of max value */ + GmacMmcTx512OctInt = 0x00000100, /* set when GmacMmcTx512To1023OctetsGb counter reaches half of max value */ + GmacMmcTx256OctInt = 0x00000080, /* set when GmacMmcTx256To511OctetsGb counter reaches half of max value */ + GmacMmcTx128OctInt = 0x00000040, /* set when GmacMmcTx128To255OctetsGb counter reaches half of max value */ + GmacMmcTx65OctInt = 0x00000020, /* set when GmacMmcTx65To127OctetsGb counter reaches half of max value */ + GmacMmcTx64OctInt = 0x00000010, /* set when GmacMmcTx64OctetsGb counter reaches half of max value */ + GmacMmcTxMcFramesInt = 0x00000008, /* set when GmacMmcTxMcFramesG counter reaches half of max value */ + GmacMmcTxBcFramesInt = 0x00000004, /* set when GmacMmcTxBcFramesG counter reaches half of max value */ + GmacMmcTxFrameGbInt = 0x00000002, /* set when GmacMmcTxFrameCountGb counter reaches half of max value */ + GmacMmcTxOctetGbInt = 0x00000001, /* set when GmacMmcTxOctetCountGb counter reaches half of max value */ + +}; + + +/********************************************************** + * Power Management (PMT) Block + **********************************************************/ + +/** + * PMT supports the reception of network (remote) wake-up frames and Magic packet frames. + * It generates interrupts for wake-up frames and Magic packets received by GMAC. + * PMT sits in Rx path and is enabled with remote wake-up frame enable and Magic packet enable. + * These enable are in PMT control and Status register and are programmed by apllication. + * + * When power down mode is enabled in PMT, all rx frames are dropped by the core. Core comes + * out of power down mode only when either Magic packe tor a Remote wake-up frame is received + * and the corresponding detection is enabled. + * + * Driver need not be modified to support this feature. Only Api to put the device in to power + * down mode is sufficient + */ + +#define WAKEUP_REG_LENGTH 8 /*This is the reg length for wake up register configuration*/ + +enum GmacPmtCtrlStatusBitDefinition +{ + GmacPmtFrmFilterPtrReset = 0x80000000, /* when set remote wake-up frame filter register pointer to 3'b000 */ + GmacPmtGlobalUnicast = 0x00000200, /* When set enables any unicast packet to be a wake-up frame */ + GmacPmtWakeupFrameReceived = 0x00000040, /* Wake up frame received */ + GmacPmtMagicPktReceived = 0x00000020, /* Magic Packet received */ + GmacPmtWakeupFrameEnable = 0x00000004, /* Wake-up frame enable */ + GmacPmtMagicPktEnable = 0x00000002, /* Magic packet enable */ + GmacPmtPowerDown = 0x00000001, /* Power Down */ +}; + + + + +/********************************************************** + * IEEE 1588-2008 Precision Time Protocol (PTP) Support + **********************************************************/ +enum PTPMessageType +{ + SYNC = 0x0, + Delay_Req = 0x1, + Pdelay_Req = 0x2, + Pdelay_Resp = 0x3, + Follow_up = 0x8, + Delay_Resp = 0x9, + Pdelay_Resp_Follow_Up = 0xA, + Announce = 0xB, + Signaling = 0xC, + Management = 0xD, +}; + + + +typedef struct TimeStampStruct +{ + u32 TSversion; /* PTP Version 1 or PTP version2 */ + u32 TSmessagetype; /* Message type associated with this time stamp */ + + u16 TShighest16; /* Highest 16 bit time stamp value, Valid onley when ADV_TIME_HIGH_WORD configured in corekit */ + u32 TSupper32; /* Most significant 32 bit time stamp value */ + u32 TSlower32; /* Least Significat 32 bit time stamp value */ + +} TimeStamp; + + +/** + * IEEE 1588-2008 is the optional module to support Ethernet frame time stamping. + * Sixty four (+16) bit time stamps are given in each frames transmit and receive status. + * The driver assumes the following + * 1. "IEEE 1588 Time Stamping" "TIME_STAMPING"is ENABLED in corekit + * 2. "IEEE 1588 External Time Stamp Input Enable" "EXT_TIME_STAMPING" is DISABLED in corekit + * 3. "IEEE 1588 Advanced Time Stamp support" "ADV_TIME_STAMPING" is ENABLED in corekit + * 4. "IEEE 1588 Higher Word Register Enable" "ADV_TIME_HIGH_WORD" is ENABLED in corekit + */ + +/* GmacTSControl = 0x0700, Controls the Timestamp update logic : only when IEEE 1588 time stamping is enabled in corekit */ +enum GmacTSControlReg +{ + GmacTSENMACADDR = 0x00040000, /* Enable Mac Addr for PTP filtering 18 RW 0 */ + + GmacTSCLKTYPE = 0x00030000, /* Select the type of clock node 17:16 RW 00 */ + /* + TSCLKTYPE TSMSTRENA TSEVNTENA Messages for wihich TS snapshot is taken + 00/01 X 0 SYNC, FOLLOW_UP, DELAY_REQ, DELAY_RESP + 00/01 1 0 DELAY_REQ + 00/01 0 1 SYNC + 10 NA 0 SYNC, FOLLOW_UP, DELAY_REQ, DELAY_RESP + 10 NA 1 SYNC, FOLLOW_UP + 11 NA 0 SYNC, FOLLOW_UP, DELAY_REQ, DELAY_RESP, PDELAY_REQ, PDELAY_RESP + 11 NA 1 SYNC, PDELAY_REQ, PDELAY_RESP + */ + GmacTSOrdClk = 0x00000000, /* 00=> Ordinary clock*/ + GmacTSBouClk = 0x00010000, /* 01=> Boundary clock*/ + GmacTSEtoEClk = 0x00020000, /* 10=> End-to-End transparent clock*/ + GmacTSPtoPClk = 0x00030000, /* 11=> P-to-P transparent clock*/ + + GmacTSMSTRENA = 0x00008000, /* Ena TS Snapshot for Master Messages 15 RW 0 */ + GmacTSEVNTENA = 0x00004000, /* Ena TS Snapshot for Event Messages 14 RW 0 */ + GmacTSIPV4ENA = 0x00002000, /* Ena TS snapshot for IPv4 13 RW 1 */ + GmacTSIPV6ENA = 0x00001000, /* Ena TS snapshot for IPv6 12 RW 0 */ + GmacTSIPENA = 0x00000800, /* Ena TS snapshot for PTP over E'net 11 RW 0 */ + GmacTSVER2ENA = 0x00000400, /* Ena PTP snooping for version 2 10 RW 0 */ + + GmacTSCTRLSSR = 0x00000200, /* Digital or Binary Rollover 9 RW 0 */ + + GmacTSENALL = 0x00000100, /* Enable TS fro all frames (Ver2 only) 8 RW 0 */ + + GmacTSADDREG = 0x00000020, /* Addend Register Update 5 RW_SC 0 */ + GmacTSUPDT = 0x00000008, /* Time Stamp Update 3 RW_SC 0 */ + GmacTSINT = 0x00000004, /* Time Atamp Initialize 2 RW_SC 0 */ + + GmacTSTRIG = 0x00000010, /* Time stamp interrupt Trigger Enable 4 RW_SC 0 */ + + GmacTSCFUPDT = 0x00000002, /* Time Stamp Fine/Coarse 1 RW 0 */ + GmacTSCUPDTCoarse = 0x00000000, /* 0=> Time Stamp update method is coarse */ + GmacTSCUPDTFine = 0x00000002, /* 1=> Time Stamp update method is fine */ + + GmacTSENA = 0x00000001, /* Time Stamp Enable 0 RW 0 */ +}; + + +/* GmacTSSubSecIncr = 0x0704, 8 bit value by which sub second register is incremented : only when IEEE 1588 time stamping without external timestamp input */ +enum GmacTSSubSecIncrReg +{ + GmacSSINCMsk = 0x000000FF, /* Only Lower 8 bits are valid bits 7:0 RW 00 */ +}; + +/* GmacTSLow = 0x070C, Indicates whether the timestamp low count is positive or negative; for Adv timestamp it is always zero */ +enum GmacTSSign +{ + GmacTSSign = 0x80000000, /* PSNT 31 RW 0 */ + GmacTSPositive = 0x00000000, + GmacTSNegative = 0x80000000, +}; + +/*GmacTargetTimeLow = 0x0718, 32 bit nano seconds(MS) to be compared with system time : only when IEEE 1588 time stamping without external timestamp input */ +enum GmacTSLowReg +{ + GmacTSDecThr = 0x3B9AC9FF, /*when TSCTRLSSR is set the max value for GmacTargetTimeLowReg and GmacTimeStampLow register is 0x3B9AC9FF at 1ns precision */ +}; + +/* GmacTSHighWord = 0x0724, Time Stamp Higher Word Register (Version 2 only); only lower 16 bits are valid */ +enum GmacTSHighWordReg +{ + GmacTSHighWordMask = 0x0000FFFF, /* Time Stamp Higher work register has only lower 16 bits valid */ +}; +/*GmacTSStatus = 0x0728, Time Stamp Status Register */ +enum GmacTSStatusReg +{ + GmacTSTargTimeReached = 0x00000002, /* Time Stamp Target Time Reached 1 RO 0 */ + GmacTSSecondsOverflow = 0x00000001, /* Time Stamp Seconds Overflow 0 RO 0 */ +}; + + +/********************************************************** + * Time stamp related functions + **********************************************************/ +void synopGMAC_TS_enable(synopGMACdevice *gmacdev); +void synopGMAC_TS_disable(synopGMACdevice *gmacdev); + +void synopGMAC_TS_int_enable(synopGMACdevice *gmacdev); +void synopGMAC_TS_int_disable(synopGMACdevice *gmacdev); + +void synopGMAC_TS_mac_addr_filt_enable(synopGMACdevice *gmacdev); +void synopGMAC_TS_mac_addr_filt_disable(synopGMACdevice *gmacdev); +void synopGMAC_TS_set_clk_type(synopGMACdevice *gmacdev, u32 clk_type); +void synopGMAC_TS_master_enable(synopGMACdevice *gmacdev); // Only for Ordinary clock and Boundary clock and "Advanced Time Stamp" +void synopGMAC_TS_master_disable(synopGMACdevice *gmacdev); // Only for Ordinary clock and Boundary clock and "Advanced Time Stamp" +void synopGMAC_TS_event_enable(synopGMACdevice *gmacdev); // Only for "Advanced Time Stamp" +void synopGMAC_TS_event_disable(synopGMACdevice *gmacdev); // Only for "Advanced Time Stamp" +void synopGMAC_TS_IPV4_enable(synopGMACdevice *gmacdev); // Only for "Advanced Time Stamp" +void synopGMAC_TS_IPV4_disable(synopGMACdevice *gmacdev); // Only for "Advanced Time Stamp" +void synopGMAC_TS_IPV6_enable(synopGMACdevice *gmacdev); // Only for "Advanced Time Stamp" +void synopGMAC_TS_IPV6_disable(synopGMACdevice *gmacdev); // Only for "Advanced Time Stamp" +void synopGMAC_TS_ptp_over_ethernet_enable(synopGMACdevice *gmacdev); // Only for "Advanced Time Stamp" +void synopGMAC_TS_ptp_over_ethernet_disable(synopGMACdevice *gmacdev); // Only for "Advanced Time Stamp" +void synopGMAC_TS_pkt_snoop_ver2(synopGMACdevice *gmacdev); // Only for "Advanced Time Stamp" +void synopGMAC_TS_pkt_snoop_ver1(synopGMACdevice *gmacdev); // Only for "Advanced Time Stamp" + +void synopGMAC_TS_digital_rollover_enable(synopGMACdevice *gmacdev); +void synopGMAC_TS_binary_rollover_enable(synopGMACdevice *gmacdev); +void synopGMAC_TS_all_frames_enable(synopGMACdevice *gmacdev); // Only for "Advanced Time Stamp" +void synopGMAC_TS_all_frames_disable(synopGMACdevice *gmacdev); // Only for "Advanced Time Stamp" + +s32 synopGMAC_TS_addend_update(synopGMACdevice *gmacdev, u32 addend_value); +s32 synopGMAC_TS_timestamp_update(synopGMACdevice *gmacdev, u32 high_value, u32 low_value); +s32 synopGMAC_TS_timestamp_init(synopGMACdevice *gmacdev, u32 high_value, u32 low_value); + +void synopGMAC_TS_coarse_update(synopGMACdevice *gmacdev); // Only if "fine correction" enabled +void synopGMAC_TS_fine_update(synopGMACdevice *gmacdev); // Only if "fine correction" enabled + +void synopGMAC_TS_subsecond_init(synopGMACdevice *gmacdev, u32 sub_sec_inc_val); // Update should happen making use of subsecond mask +void synopGMAC_TS_read_timestamp(synopGMACdevice *gmacdev, u16 *higher_sec_val, + u32 *sec_val, u32 *sub_sec_val); // Reads the timestamp low,high and higher(Ver2) registers in the the struct pointer; readonly contents +void synopGMAC_TS_load_target_timestamp(synopGMACdevice *gmacdev, u32 sec_val, u32 sub_sec_val); //Loads the timestamp target register with the values provided + +void synopGMAC_TS_load_timestamp_higher_val(synopGMACdevice *gmacdev, u32 higher_sec_val); +void synopGMAC_TS_read_timestamp_higher_val(synopGMACdevice *gmacdev, u16 *higher_sec_val); +void synopGMAC_TS_read_target_timestamp(synopGMACdevice *gmacdev, u32 *sec_val, u32 *sub_sec_val); //Read the target time stamp register contents + + +/********************************************************** + * Common functions + **********************************************************/ +s32 synopGMAC_set_mdc_clk_div(synopGMACdevice *gmacdev, u32 clk_div_val); +u32 synopGMAC_get_mdc_clk_div(synopGMACdevice *gmacdev); +s32 synopGMAC_read_phy_reg(u32 RegBase, u32 PhyBase, u32 RegOffset, u16 *data); +s32 synopGMAC_write_phy_reg(u32 RegBase, u32 PhyBase, u32 RegOffset, u16 data); +s32 synopGMAC_phy_loopback(synopGMACdevice *gmacdev, bool loopback); +s32 synopGMAC_read_version(synopGMACdevice *gmacdev) ; +s32 synopGMAC_reset(synopGMACdevice *gmacdev); +s32 synopGMAC_reset_nocheck(synopGMACdevice *gmacdev); +s32 synopGMAC_dma_bus_mode_init(synopGMACdevice *gmacdev, u32 init_value); +s32 synopGMAC_dma_control_init(synopGMACdevice *gmacdev, u32 init_value); +void synopGMAC_wd_enable(synopGMACdevice *gmacdev); +void synopGMAC_wd_disable(synopGMACdevice *gmacdev); +void synopGMAC_jab_enable(synopGMACdevice *gmacdev); +void synopGMAC_jab_disable(synopGMACdevice *gmacdev); +void synopGMAC_frame_burst_enable(synopGMACdevice *gmacdev); +void synopGMAC_frame_burst_disable(synopGMACdevice *gmacdev); +void synopGMAC_jumbo_frame_enable(synopGMACdevice *gmacdev); +void synopGMAC_jumbo_frame_disable(synopGMACdevice *gmacdev); +void synopGMAC_select_gmii(synopGMACdevice *gmacdev); +void synopGMAC_select_mii(synopGMACdevice *gmacdev); +void synopGMAC_rx_own_enable(synopGMACdevice *gmacdev); +void synopGMAC_rx_own_disable(synopGMACdevice *gmacdev); +void synopGMAC_loopback_on(synopGMACdevice *gmacdev); +void synopGMAC_loopback_off(synopGMACdevice *gmacdev); +void synopGMAC_set_full_duplex(synopGMACdevice *gmacdev); +void synopGMAC_set_half_duplex(synopGMACdevice *gmacdev); +void synopGMAC_retry_enable(synopGMACdevice *gmacdev); +void synopGMAC_retry_disable(synopGMACdevice *gmacdev); +void synopGMAC_pad_crc_strip_enable(synopGMACdevice *gmacdev); +void synopGMAC_pad_crc_strip_disable(synopGMACdevice *gmacdev); +void synopGMAC_back_off_limit(synopGMACdevice *gmacdev, u32 value); +void synopGMAC_deferral_check_enable(synopGMACdevice *gmacdev); +void synopGMAC_deferral_check_disable(synopGMACdevice *gmacdev); +void synopGMAC_rx_enable(synopGMACdevice *gmacdev); +void synopGMAC_rx_disable(synopGMACdevice *gmacdev); +void synopGMAC_tx_enable(synopGMACdevice *gmacdev); +void synopGMAC_tx_disable(synopGMACdevice *gmacdev); +void synopGMAC_frame_filter_enable(synopGMACdevice *gmacdev); +void synopGMAC_frame_filter_disable(synopGMACdevice *gmacdev); +void synopGMAC_write_hash_table_high(synopGMACdevice *gmacdev, u32 data); +void synopGMAC_write_hash_table_low(synopGMACdevice *gmacdev, u32 data); +void synopGMAC_hash_perfect_filter_enable(synopGMACdevice *gmacdev); +void synopGMAC_Hash_filter_only_enable(synopGMACdevice *gmacdev); +void synopGMAC_src_addr_filter_enable(synopGMACdevice *gmacdev); +void synopGMAC_src_addr_filter_disable(synopGMACdevice *gmacdev); +void synopGMAC_dst_addr_filter_inverse(synopGMACdevice *gmacdev); +void synopGMAC_dst_addr_filter_normal(synopGMACdevice *gmacdev); +void synopGMAC_set_pass_control(synopGMACdevice *gmacdev, u32 passcontrol); +void synopGMAC_broadcast_enable(synopGMACdevice *gmacdev); +void synopGMAC_broadcast_disable(synopGMACdevice *gmacdev); +void synopGMAC_multicast_enable(synopGMACdevice *gmacdev); +void synopGMAC_multicast_disable(synopGMACdevice *gmacdev); +void synopGMAC_multicast_hash_filter_enable(synopGMACdevice *gmacdev); +void synopGMAC_multicast_hash_filter_disable(synopGMACdevice *gmacdev); +void synopGMAC_promisc_enable(synopGMACdevice *gmacdev); +void synopGMAC_promisc_disable(synopGMACdevice *gmacdev); +void synopGMAC_unicast_hash_filter_enable(synopGMACdevice *gmacdev); +void synopGMAC_unicast_hash_filter_disable(synopGMACdevice *gmacdev); +void synopGMAC_unicast_pause_frame_detect_enable(synopGMACdevice *gmacdev); +void synopGMAC_unicast_pause_frame_detect_disable(synopGMACdevice *gmacdev); +void synopGMAC_rx_flow_control_enable(synopGMACdevice *gmacdev); +void synopGMAC_rx_flow_control_disable(synopGMACdevice *gmacdev); +void synopGMAC_tx_flow_control_enable(synopGMACdevice *gmacdev); +void synopGMAC_tx_flow_control_disable(synopGMACdevice *gmacdev); +void synopGMAC_tx_activate_flow_control(synopGMACdevice *gmacdev); +void synopGMAC_tx_deactivate_flow_control(synopGMACdevice *gmacdev); +void synopGMAC_pause_control(synopGMACdevice *gmacdev); +s32 synopGMAC_mac_init(synopGMACdevice *gmacdev); +//s32 synopGMAC_check_phy_init (synopGMACdevice * gmacdev); +s32 synopGMAC_set_mac_addr(synopGMACdevice *gmacdev, u32 MacHigh, u32 MacLow, u8 *MacAddr); +s32 synopGMAC_get_mac_addr(synopGMACdevice *gmacdev, u32 MacHigh, u32 MacLow, u8 *MacAddr); +s32 synopGMAC_attach(synopGMACdevice *gmacdev, u32 macBase, u32 dmaBase, u32 phyBase, u8 *mac_addr); +void synopGMAC_rx_desc_init_ring(DmaDesc *desc, bool last_ring_desc); +void synopGMAC_tx_desc_init_ring(DmaDesc *desc, bool last_ring_desc); +void synopGMAC_rx_desc_init_chain(DmaDesc *desc); +void synopGMAC_tx_desc_init_chain(DmaDesc *desc); +s32 synopGMAC_init_tx_rx_desc_queue(synopGMACdevice *gmacdev); +void synopGMAC_init_rx_desc_base(synopGMACdevice *gmacdev); +void synopGMAC_init_tx_desc_base(synopGMACdevice *gmacdev); +void synopGMAC_set_owner_dma(DmaDesc *desc); +void synopGMAC_set_desc_sof(DmaDesc *desc); +void synopGMAC_set_desc_eof(DmaDesc *desc); +bool synopGMAC_is_sof_in_rx_desc(DmaDesc *desc); +bool synopGMAC_is_eof_in_rx_desc(DmaDesc *desc); +bool synopGMAC_is_da_filter_failed(DmaDesc *desc); +bool synopGMAC_is_sa_filter_failed(DmaDesc *desc); +bool synopGMAC_is_desc_owned_by_dma(DmaDesc *desc); +u32 synopGMAC_get_rx_desc_frame_length(u32 status); +bool synopGMAC_is_desc_valid(u32 status); +bool synopGMAC_is_desc_empty(DmaDesc *desc); +bool synopGMAC_is_rx_desc_valid(u32 status); +bool synopGMAC_is_tx_aborted(u32 status); +bool synopGMAC_is_tx_carrier_error(u32 status); +u32 synopGMAC_get_tx_collision_count(u32 status); +u32 synopGMAC_is_exc_tx_collisions(u32 status); +bool synopGMAC_is_rx_frame_damaged(u32 status); +bool synopGMAC_is_rx_frame_collision(u32 status); +bool synopGMAC_is_rx_crc(u32 status); +bool synopGMAC_is_frame_dribbling_errors(u32 status); +bool synopGMAC_is_rx_frame_length_errors(u32 status); +bool synopGMAC_is_last_rx_desc(synopGMACdevice *gmacdev, DmaDesc *desc); +bool synopGMAC_is_last_tx_desc(synopGMACdevice *gmacdev, DmaDesc *desc); +bool synopGMAC_is_rx_desc_chained(DmaDesc *desc); +bool synopGMAC_is_tx_desc_chained(DmaDesc *desc); +void synopGMAC_get_desc_data(DmaDesc *desc, u32 *Status, u32 *Buffer1, u32 *Length1, u32 *Data1); + +s32 synopGMAC_get_tx_qptr(synopGMACdevice *gmacdev, u32 *Status, u32 *Buffer1, u32 *Length1, u32 *Data1, u32 *Ext_Status, u32 *Time_Stamp_High, u32 *Time_Stamp_low); + +s32 synopGMAC_set_tx_qptr(synopGMACdevice *gmacdev, u32 Buffer1, u32 Length1, u32 Data1, u32 offload_needed, u32 ts); +s32 synopGMAC_set_rx_qptr(synopGMACdevice *gmacdev, u32 Buffer1, u32 Length1, u32 Data1); + +s32 synopGMAC_get_rx_qptr(synopGMACdevice *gmacdev, u32 *Status, u32 *Buffer1, u32 *Length1, u32 *Data1, u32 *Ext_Status, u32 *Time_Stamp_High, u32 *Time_Stamp_low); + +void synopGMAC_clear_interrupt(synopGMACdevice *gmacdev); +u32 synopGMAC_get_interrupt_type(synopGMACdevice *gmacdev); +u32 synopGMAC_get_interrupt_mask(synopGMACdevice *gmacdev); +void synopGMAC_enable_interrupt(synopGMACdevice *gmacdev, u32 interrupts); +void synopGMAC_disable_interrupt_all(synopGMACdevice *gmacdev); +void synopGMAC_disable_interrupt(synopGMACdevice *gmacdev, u32 interrupts); +void synopGMAC_enable_dma_rx(synopGMACdevice *gmacdev); +void synopGMAC_enable_dma_tx(synopGMACdevice *gmacdev); +void synopGMAC_resume_dma_tx(synopGMACdevice *gmacdev); +void synopGMAC_resume_dma_rx(synopGMACdevice *gmacdev); +void synopGMAC_take_desc_ownership(DmaDesc *desc); +void synopGMAC_take_desc_ownership_rx(synopGMACdevice *gmacdev); +void synopGMAC_take_desc_ownership_tx(synopGMACdevice *gmacdev); +void synopGMAC_disable_dma_tx(synopGMACdevice *gmacdev); +void synopGMAC_disable_dma_rx(synopGMACdevice *gmacdev); +/******Following APIs are valid only for Enhanced Descriptor from 3.50a release onwards*******/ +bool synopGMAC_is_ext_status(synopGMACdevice *gmacdev, u32 status); +bool synopGMAC_ES_is_IP_header_error(synopGMACdevice *gmacdev, u32 ext_status); +bool synopGMAC_ES_is_rx_checksum_bypassed(synopGMACdevice *gmacdev, u32 ext_status); +bool synopGMAC_ES_is_IP_payload_error(synopGMACdevice *gmacdev, u32 ext_status); +/*******************PMT APIs***************************************/ +void synopGMAC_pmt_int_enable(synopGMACdevice *gmacdev); +void synopGMAC_pmt_int_disable(synopGMACdevice *gmacdev); +void synopGMAC_power_down_enable(synopGMACdevice *gmacdev); +void synopGMAC_power_down_disable(synopGMACdevice *gmacdev); +void synopGMAC_enable_pmt_interrupt(synopGMACdevice *gmacdev); +void synopGMAC_disable_pmt_interrupt(synopGMACdevice *gmacdev); +void synopGMAC_magic_packet_enable(synopGMACdevice *gmacdev); +void synopGMAC_magic_packet_disable(synopGMACdevice *gmacdev); +void synopGMAC_wakeup_frame_enable(synopGMACdevice *gmacdev); +void synopGMAC_pmt_unicast_enable(synopGMACdevice *gmacdev); +bool synopGMAC_is_magic_packet_received(synopGMACdevice *gmacdev); +bool synopGMAC_is_wakeup_frame_received(synopGMACdevice *gmacdev); +void synopGMAC_write_wakeup_frame_register(synopGMACdevice *gmacdev, u32 *filter_contents); + +/*******************Ip checksum offloading APIs***************************************/ +void synopGMAC_enable_rx_chksum_offload(synopGMACdevice *gmacdev); +void synopGMAC_disable_rx_chksum_offload(synopGMACdevice *gmacdev); +void synopGMAC_rx_tcpip_chksum_drop_enable(synopGMACdevice *gmacdev); +void synopGMAC_rx_tcpip_chksum_drop_disable(synopGMACdevice *gmacdev); +u32 synopGMAC_is_rx_checksum_error(synopGMACdevice *gmacdev, u32 status); +bool synopGMAC_is_tx_ipv4header_checksum_error(synopGMACdevice *gmacdev, u32 status); +bool synopGMAC_is_tx_payload_checksum_error(synopGMACdevice *gmacdev, u32 status); +void synopGMAC_tx_checksum_offload_bypass(synopGMACdevice *gmacdev, DmaDesc *desc); +void synopGMAC_tx_checksum_offload_ipv4hdr(synopGMACdevice *gmacdev, DmaDesc *desc); +void synopGMAC_tx_checksum_offload_tcponly(synopGMACdevice *gmacdev, DmaDesc *desc); +void synopGMAC_tx_checksum_offload_tcp_pseudo(synopGMACdevice *gmacdev, DmaDesc *desc); + + +// For testing --ya +void synopGMAC_src_addr_insert_enable(synopGMACdevice *gmacdev); +void synopGMAC_src_addr_insert_disable(synopGMACdevice *gmacdev); +void synopGMAC_src_addr_replace_enable(synopGMACdevice *gmacdev); +void synopGMAC_src_addr_replace_disable(synopGMACdevice *gmacdev); + +void synopGMAC_svlan_insertion_enable(synopGMACdevice *gmacdev, u16 vlantag); +void synopGMAC_cvlan_insertion_enable(synopGMACdevice *gmacdev, u16 vlantag); +void synopGMAC_svlan_replace_enable(synopGMACdevice *gmacdev, u16 vlantag); +void synopGMAC_cvlan_replace_enable(synopGMACdevice *gmacdev, u16 vlantag); +void synopGMAC_vlan_deletion_enable(synopGMACdevice *gmacdev); +void synopGMAC_vlan_no_act_enable(synopGMACdevice *gmacdev); + +void synopGMAC_set_crc_replacement(synopGMACdevice *gmacdev); +void synopGMAC_clr_crc_replacement(synopGMACdevice *gmacdev); + +void synopGMAC_enable_under_size_pkt(synopGMACdevice *gmacdev); +void synopGMAC_disable_under_size_pkt(synopGMACdevice *gmacdev); + +void synopGMAC_enable_crc_err_pkt(synopGMACdevice *gmacdev); +void synopGMAC_disable_crc_err_pkt(synopGMACdevice *gmacdev); + +#endif /* End of file */ diff --git a/bsp/nuvoton/libraries/ma35/rtt_port/gmac/synopGMAC_Host.h b/bsp/nuvoton/libraries/ma35/rtt_port/gmac/synopGMAC_Host.h new file mode 100644 index 0000000000..2290a3b317 --- /dev/null +++ b/bsp/nuvoton/libraries/ma35/rtt_port/gmac/synopGMAC_Host.h @@ -0,0 +1,38 @@ +/* + * Copyright (c) 2006-2022, RT-Thread Development Team + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + * 2017-08-24 chinesebear first version + */ + +#ifndef SYNOP_GMAC_HOST_H +#define SYNOP_GMAC_HOST_H 1 + +#include "synopGMAC_plat.h" +#include "synopGMAC_Dev.h" +#include "mii.h" +#include "synopGMAC_network_interface.h" + +typedef struct +{ + uint32_t u32TxDescSize; + uint32_t u32RxDescSize; + + DmaDesc *psRXDescs; + PKT_FRAME_T *psRXFrames; + DmaDesc *psTXDescs; + PKT_FRAME_T *psTXFrames; +} GMAC_MEMMGR_T; + +typedef struct +{ + /*Device Dependent Data structur*/ + synopGMACdevice *m_gmacdev; + GMAC_MEMMGR_T *m_gmacmemmgr; + struct mii_if_info m_mii; +} synopGMACNetworkAdapter; + +#endif diff --git a/bsp/nuvoton/libraries/ma35/rtt_port/gmac/synopGMAC_network_interface.c b/bsp/nuvoton/libraries/ma35/rtt_port/gmac/synopGMAC_network_interface.c new file mode 100644 index 0000000000..48dc0070e8 --- /dev/null +++ b/bsp/nuvoton/libraries/ma35/rtt_port/gmac/synopGMAC_network_interface.c @@ -0,0 +1,628 @@ +/* =================================================================================== + * Copyright (c) <2009> Synopsys, Inc. + * + * Permission is hereby granted, free of charge, to any person obtaining a copy of + * this software annotated with this license and associated documentation files + * (the "Software"), to deal in the Software without restriction, including without + * limitation the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the Software is + * furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in all + * copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, + * INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS FOR A + * PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT + * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION + * OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE + * OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + * + * =================================================================================== */ + + +/** \file + * This is the network dependent layer to handle network related functionality. + * This file is tightly coupled to neworking frame work of linux 2.6.xx kernel. + * The functionality carried out in this file should be treated as an example only + * if the underlying operating system is not Linux. + * + * \note Many of the functions other than the device specific functions + * changes for operating system other than Linux 2.6.xx + * \internal + *-----------------------------REVISION HISTORY----------------------------------- + * Synopsys 01/Aug/2007 Created + */ + +#include "NuMicro.h" +#include "synopGMAC_network_interface.h" + + +void synopGMAC_powerup_mac(synopGMACdevice *gmacdev) +{ + gmacdev->GMAC_Power_down = 0; // Let ISR know that MAC is out of power down now + if (synopGMAC_is_magic_packet_received(gmacdev)) + TR("GMAC wokeup due to Magic Pkt Received\n"); + if (synopGMAC_is_wakeup_frame_received(gmacdev)) + TR("GMAC wokeup due to Wakeup Frame Received\n"); + //Disable the assertion of PMT interrupt + synopGMAC_pmt_int_disable(gmacdev); + //Enable the mac and Dma rx and tx paths + synopGMAC_rx_enable(gmacdev); + synopGMAC_enable_dma_rx(gmacdev); + + synopGMAC_tx_enable(gmacdev); + synopGMAC_enable_dma_tx(gmacdev); + + return; +} + +void synopGMAC_powerdown_mac(synopGMACdevice *gmacdev) +{ + TR("Put the GMAC to power down mode..\n"); + + // Disable the Dma engines in tx path + gmacdev->GMAC_Power_down = 1; // Let ISR know that Mac is going to be in the power down mode + synopGMAC_disable_dma_tx(gmacdev); + plat_delay(DEFAULT_LOOP_VARIABLE); //allow any pending transmission to complete + // Disable the Mac for both tx and rx + synopGMAC_tx_disable(gmacdev); + synopGMAC_rx_disable(gmacdev); + plat_delay(DEFAULT_LOOP_VARIABLE); //Allow any pending buffer to be read by host + //Disable the Dma in rx path + synopGMAC_disable_dma_rx(gmacdev); + + //enable the power down mode + //synopGMAC_pmt_unicast_enable(gmacdev); + + //prepare the gmac for magic packet reception and wake up frame reception + synopGMAC_magic_packet_enable(gmacdev); + + //gate the application and transmit clock inputs to the code. This is not done in this driver :). + + //enable the Mac for reception + synopGMAC_rx_enable(gmacdev); + + //Enable the assertion of PMT interrupt + synopGMAC_pmt_int_enable(gmacdev); + + //enter the power down mode + synopGMAC_power_down_enable(gmacdev); + + return; +} + +#if 0 +void synopGMAC_powerdown_mac(synopGMACdevice *gmacdev) +{ + TR0("Put the GMAC to power down mode..\n"); + // Disable the Dma engines in tx path + GMAC_Power_down = 1; // Let ISR know that Mac is going to be in the power down mode + synopGMAC_disable_dma_tx(gmacdev); + plat_delay(DEFAULT_LOOP_VARIABLE); //allow any pending transmission to complete + // Disable the Mac for both tx and rx + synopGMAC_tx_disable(gmacdev); + synopGMAC_rx_disable(gmacdev); + plat_delay(DEFAULT_LOOP_VARIABLE); //Allow any pending buffer to be read by host + //Disable the Dma in rx path + synopGMAC_disable_dma_rx(gmacdev); + + //enable the power down mode + //synopGMAC_pmt_unicast_enable(gmacdev); + + //prepare the gmac for magic packet reception and wake up frame reception + synopGMAC_magic_packet_enable(gmacdev); + + //gate the application and transmit clock inputs to the code. This is not done in this driver :). + + //enable the Mac for reception + synopGMAC_rx_enable(gmacdev); + + //Enable the assertion of PMT interrupt + synopGMAC_pmt_int_enable(gmacdev); + //enter the power down mode + synopGMAC_power_down_enable(gmacdev); + return; +} + +void synopGMAC_powerup_mac(synopGMACdevice *gmacdev) +{ + GMAC_Power_down = 0; // Let ISR know that MAC is out of power down now + if (synopGMAC_is_magic_packet_received(gmacdev)) + TR("GMAC wokeup due to Magic Pkt Received\n"); + if (synopGMAC_is_wakeup_frame_received(gmacdev)) + TR("GMAC wokeup due to Wakeup Frame Received\n"); + //Disable the assertion of PMT interrupt + synopGMAC_pmt_int_disable(gmacdev); + //Enable the mac and Dma rx and tx paths + synopGMAC_rx_enable(gmacdev); + synopGMAC_enable_dma_rx(gmacdev); + + synopGMAC_tx_enable(gmacdev); + synopGMAC_enable_dma_tx(gmacdev); + return; +} +#endif + +/** + * This sets up the transmit Descriptor queue in ring or chain mode. + * This function is tightly coupled to the platform and operating system + * Device is interested only after the descriptors are setup. Therefore this function + * is not included in the device driver API. This function should be treated as an + * example code to design the descriptor structures for ring mode or chain mode. + * This function depends on the pcidev structure for allocation consistent dma-able memory in case of linux. + * This limitation is due to the fact that linux uses pci structure to allocate a dmable memory + * - Allocates the memory for the descriptors. + * - Initialize the Busy and Next descriptors indices to 0(Indicating first descriptor). + * - Initialize the Busy and Next descriptors to first descriptor address. + * - Initialize the last descriptor with the endof ring in case of ring mode. + * - Initialize the descriptors in chain mode. + * @param[in] pointer to synopGMACdevice. + * @param[in] pointer to pci_device structure. + * @param[in] number of descriptor expected in tx descriptor queue. + * @param[in] whether descriptors to be created in RING mode or CHAIN mode. + * \return 0 upon success. Error code upon failure. + * \note This function fails if allocation fails for required number of descriptors in Ring mode, but in chain mode + * function returns -ESYNOPGMACNOMEM in the process of descriptor chain creation. once returned from this function + * user should for gmacdev->TxDescCount to see how many descriptors are there in the chain. Should continue further + * only if the number of descriptors in the chain meets the requirements + */ + +s32 synopGMAC_setup_tx_desc_queue(synopGMACdevice *gmacdev, DmaDesc *first_desc, u32 no_of_desc, u32 desc_mode) +{ + s32 i; + + TR("Total size of memory required for Tx Descriptors in Ring Mode = 0x%08x\n", ((sizeof(DmaDesc) * no_of_desc))); + + gmacdev->TxDescCount = no_of_desc; + +#ifdef CACHE_ON + gmacdev->TxDesc = (DmaDesc *)((u32)first_desc | UNCACHEABLE) ; +#else + gmacdev->TxDesc = first_desc; +#endif + + gmacdev->TxDescDma = (dma_addr_t)first_desc; + + for (i = 0; i < gmacdev -> TxDescCount; i++) + { + synopGMAC_tx_desc_init_ring((DmaDesc *)gmacdev->TxDesc + i, i == gmacdev->TxDescCount - 1); + + TR("%02d %08x \n", i, (unsigned int)(gmacdev->TxDesc + i)); + TR("status: %08x\n", (unsigned int)((gmacdev->TxDesc + i))->status); + TR("length: %08x\n", (unsigned int)((gmacdev->TxDesc + i)->length)); + TR("buffer1: %08x\n", (unsigned int)((gmacdev->TxDesc + i)->buffer1)); + TR("buffer2: %08x\n", (unsigned int)((gmacdev->TxDesc + i)->buffer2)); + TR("extstatus: %08x\n", (unsigned int)((gmacdev->TxDesc + i)->extstatus)); + TR("reserved1: %08x\n", (unsigned int)((gmacdev->TxDesc + i)->reserved1)); + TR("timestamplow: %08x\n", (unsigned int)((gmacdev->TxDesc + i)->timestamplow)); + TR("timestamphigh: %08x\n", (unsigned int)((gmacdev->TxDesc + i)->timestamphigh)); +// TR("data1: %08x\n", (unsigned int)((gmacdev->TxDesc + i)->data1)); +// TR("data2: %08x\n", (unsigned int)((gmacdev->TxDesc + i)->data2)); + } + + gmacdev->TxNext = 0; + gmacdev->TxBusy = 0; + gmacdev->TxNextDesc = gmacdev->TxDesc; + gmacdev->TxBusyDesc = gmacdev->TxDesc; + gmacdev->BusyTxDesc = 0; + + return 0; +} + + +/** + * This sets up the receive Descriptor queue in ring or chain mode. + * This function is tightly coupled to the platform and operating system + * Device is interested only after the descriptors are setup. Therefore this function + * is not included in the device driver API. This function should be treated as an + * example code to design the descriptor structures in ring mode or chain mode. + * This function depends on the pcidev structure for allocation of consistent dma-able memory in case of linux. + * This limitation is due to the fact that linux uses pci structure to allocate a dmable memory + * - Allocates the memory for the descriptors. + * - Initialize the Busy and Next descriptors indices to 0(Indicating first descriptor). + * - Initialize the Busy and Next descriptors to first descriptor address. + * - Initialize the last descriptor with the endof ring in case of ring mode. + * - Initialize the descriptors in chain mode. + * @param[in] pointer to synopGMACdevice. + * @param[in] pointer to pci_device structure. + * @param[in] number of descriptor expected in rx descriptor queue. + * @param[in] whether descriptors to be created in RING mode or CHAIN mode. + * \return 0 upon success. Error code upon failure. + * \note This function fails if allocation fails for required number of descriptors in Ring mode, but in chain mode + * function returns -ESYNOPGMACNOMEM in the process of descriptor chain creation. once returned from this function + * user should for gmacdev->RxDescCount to see how many descriptors are there in the chain. Should continue further + * only if the number of descriptors in the chain meets the requirements + */ +s32 synopGMAC_setup_rx_desc_queue(synopGMACdevice *gmacdev, DmaDesc *first_desc, u32 no_of_desc, u32 desc_mode) +{ + s32 i; + + TR("total size of memory required for Rx Descriptors in Ring Mode = 0x%08x\n", ((sizeof(DmaDesc) * no_of_desc))); + + gmacdev->RxDescCount = no_of_desc; +#ifdef CACHE_ON + gmacdev->RxDesc = (DmaDesc *)((u32)first_desc | UNCACHEABLE) ; +#else + gmacdev->RxDesc = first_desc; +#endif + gmacdev->RxDescDma = (dma_addr_t)((u32)first_desc); + + for (i = 0; i < gmacdev -> RxDescCount; i++) + { + synopGMAC_rx_desc_init_ring((DmaDesc *)gmacdev->RxDesc + i, i == gmacdev->RxDescCount - 1); + TR("%02d %08x \n", i, (unsigned int)(gmacdev->RxDesc + i)); + } + + + gmacdev->RxNext = 0; + gmacdev->RxBusy = 0; + gmacdev->RxNextDesc = gmacdev->RxDesc; + gmacdev->RxBusyDesc = gmacdev->RxDesc; + + gmacdev->BusyRxDesc = 0; + + return 0; +} + +/** + * This gives up the receive Descriptor queue in ring or chain mode. + * This function is tightly coupled to the platform and operating system + * Once device's Dma is stopped the memory descriptor memory and the buffer memory deallocation, + * is completely handled by the operating system, this call is kept outside the device driver Api. + * This function should be treated as an example code to de-allocate the descriptor structures in ring mode or chain mode + * and network buffer deallocation. + * This function depends on the pcidev structure for dma-able memory deallocation for both descriptor memory and the + * network buffer memory under linux. + * The responsibility of this function is to + * - Free the network buffer memory if any. + * - Fee the memory allocated for the descriptors. + * @param[in] pointer to synopGMACdevice. + * @param[in] pointer to pci_device structure. + * @param[in] number of descriptor expected in rx descriptor queue. + * @param[in] whether descriptors to be created in RING mode or CHAIN mode. + * \return 0 upon success. Error code upon failure. + * \note No referece should be made to descriptors once this function is called. This function is invoked when the device is closed. + */ +void synopGMAC_giveup_rx_desc_queue(synopGMACdevice *gmacdev, u32 desc_mode) +{ + gmacdev->RxDesc = NULL; + gmacdev->RxDescDma = 0; + return; +} + +/** + * This gives up the transmit Descriptor queue in ring or chain mode. + * This function is tightly coupled to the platform and operating system + * Once device's Dma is stopped the memory descriptor memory and the buffer memory deallocation, + * is completely handled by the operating system, this call is kept outside the device driver Api. + * This function should be treated as an example code to de-allocate the descriptor structures in ring mode or chain mode + * and network buffer deallocation. + * This function depends on the pcidev structure for dma-able memory deallocation for both descriptor memory and the + * network buffer memory under linux. + * The responsibility of this function is to + * - Free the network buffer memory if any. + * - Fee the memory allocated for the descriptors. + * @param[in] pointer to synopGMACdevice. + * @param[in] pointer to pci_device structure. + * @param[in] number of descriptor expected in tx descriptor queue. + * @param[in] whether descriptors to be created in RING mode or CHAIN mode. + * \return 0 upon success. Error code upon failure. + * \note No reference should be made to descriptors once this function is called. This function is invoked when the device is closed. + */ +void synopGMAC_giveup_tx_desc_queue(synopGMACdevice *gmacdev, u32 desc_mode) +{ + + + gmacdev->TxDesc = NULL; + gmacdev->TxDescDma = 0; + return; +} + +void synopGMAC_set_speed(synopGMACdevice *gmacdev) +{ + switch (gmacdev->Speed) + { + case SPEED1000: + synopGMACClearBits(gmacdev->MacBase, GmacConfig, GmacMiiGmii); + break; + case SPEED100: + synopGMACSetBits(gmacdev->MacBase, GmacConfig, GmacMiiGmii); + synopGMACSetBits(gmacdev->MacBase, GmacConfig, GmacFESpeed100); + break; + case SPEED10: + synopGMACSetBits(gmacdev->MacBase, GmacConfig, GmacMiiGmii); + synopGMACClearBits(gmacdev->MacBase, GmacConfig, GmacFESpeed100); + default: + break; + } +} + +/** + * Function to transmit a given packet on the wire. + * Whenever Linux Kernel has a packet ready to be transmitted, this function is called. + * The function prepares a packet and prepares the descriptor and + * enables/resumes the transmission. + * @param[in] pointer to sk_buff structure. + * @param[in] pointer to net_device structure. + * \return Returns 0 on success and Error code on failure. + * \note structure sk_buff is used to hold packet in Linux networking stacks. + */ +s32 synopGMAC_xmit_frames(synopGMACdevice *gmacdev, u8 *pkt_data, u32 pkt_len, u32 offload_needed, u32 ts) +{ + s32 status = 0; + u32 dma_addr = (u32)pkt_data; + + /*Now we have skb ready and OS invoked this function. Lets make our DMA know about this*/ + status = synopGMAC_set_tx_qptr(gmacdev, dma_addr, pkt_len, dma_addr, offload_needed, ts); + if (status < 0) + { + TR0("%s No More Free Tx Descriptors\n", __FUNCTION__); + return -1; + } + + /*Now force the DMA to start transmission*/ + synopGMAC_resume_dma_tx(gmacdev); + + return 0; +} + + +/** + * Function to handle housekeeping after a packet is transmitted over the wire. + * After the transmission of a packet DMA generates corresponding interrupt + * (if it is enabled). It takes care of returning the sk_buff to the linux + * kernel, updating the networking statistics and tracking the descriptors. + * @param[in] pointer to net_device structure. + * \return void. + * \note This function runs in interrupt context + */ +void synop_handle_transmit_over(synopGMACdevice *gmacdev) +{ + s32 desc_index; + u32 data1; + u32 status; + u32 length1; + u32 dma_addr1; + + u32 ext_status; + //u16 time_stamp_higher; + u32 time_stamp_high; + u32 time_stamp_low; + + /*Handle the transmit Descriptors*/ + do + { + desc_index = synopGMAC_get_tx_qptr(gmacdev, &status, &dma_addr1, &length1, &data1, &ext_status, &time_stamp_high, &time_stamp_low); + //synopGMAC_TS_read_timestamp_higher_val(gmacdev, &time_stamp_higher); + + if (desc_index >= 0 /*&& data1 != 0*/) + { + TR("Finished Transmit at Tx Descriptor %d for buffer = %08x whose status is %08x \n", desc_index, dma_addr1, status); + + if (synopGMAC_is_tx_ipv4header_checksum_error(gmacdev, status)) + { + TR("Harware Failed to Insert IPV4 Header Checksum\n"); + gmacdev->synopGMACNetStats.tx_ip_header_errors++; + } + if (synopGMAC_is_tx_payload_checksum_error(gmacdev, status)) + { + TR("Harware Failed to Insert Payload Checksum\n"); + gmacdev->synopGMACNetStats.tx_ip_payload_errors++; + } + + if (synopGMAC_is_desc_valid(status)) + { + gmacdev->synopGMACNetStats.tx_bytes += length1; + gmacdev->synopGMACNetStats.tx_packets++; + if (status & DescTxTSStatus) + { + gmacdev->tx_sec = time_stamp_high; + gmacdev->tx_subsec = time_stamp_low; + } + else + { + gmacdev->tx_sec = 0; + gmacdev->tx_subsec = 0; + } + } + else + { + TR("Error in Status %08x\n", status); + gmacdev->synopGMACNetStats.tx_errors++; + gmacdev->synopGMACNetStats.tx_aborted_errors += synopGMAC_is_tx_aborted(status); + gmacdev->synopGMACNetStats.tx_carrier_errors += synopGMAC_is_tx_carrier_error(status); + } + } + gmacdev->synopGMACNetStats.collisions += synopGMAC_get_tx_collision_count(status); + } + while (desc_index >= 0); +} + +/** + * Function to Receive a packet from the interface. + * After Receiving a packet, DMA transfers the received packet to the system memory + * and generates corresponding interrupt (if it is enabled). This function prepares + * the sk_buff for received packet after removing the ethernet CRC, and hands it over + * to linux networking stack. + * - Updataes the networking interface statistics + * - Keeps track of the rx descriptors + * @param[in] pointer to net_device structure. + * \return void. + * \note This function runs in interrupt context. + */ +extern DmaDesc *prevtx; // for CRC test +s32 synop_handle_received_data(synopGMACdevice *gmacdev, PKT_FRAME_T **ppsPktFrame) +{ + u32 data1; + u32 len; + u32 status; + u32 dma_addr1; + + u32 ext_status; + //u16 time_stamp_higher; + u32 time_stamp_high; + u32 time_stamp_low; + + /* Handle the Receive Descriptors */ + if (synopGMAC_get_rx_qptr(gmacdev, &status, + &dma_addr1, NULL, &data1, + &ext_status, &time_stamp_high, &time_stamp_low) >= 0) + { + //synopGMAC_TS_read_timestamp_higher_val(gmacdev, &time_stamp_higher); + //TR("S:%08x ES:%08x DA1:%08x d1:%08x TSH:%08x TSL:%08x TSHW:%08x \n",status,ext_status,dma_addr1, data1,time_stamp_high,time_stamp_low,time_stamp_higher); + TR("S:%08x ES:%08x DA1:%08x d1:%08x TSH:%08x TSL:%08x\n", status, ext_status, dma_addr1, data1, time_stamp_high, time_stamp_low); + + TR("Received Data at Rx Descriptor for skb 0x%08x whose status is %08x\n", data1, status); + + if (synopGMAC_is_rx_desc_valid(status)) + { + // Always enter this loop. synopGMAC_is_rx_desc_valid() also report invalid descriptor + // if there's packet error generated by test code and drop it. But we need to execute ext_status + // check code to tell what's going on. --ya + + len = synopGMAC_get_rx_desc_frame_length(status) - 4; //Not interested in Ethernet CRC bytes + + + // Now lets check for the IPC offloading + /* Since we have enabled the checksum offloading in hardware, lets inform the kernel + not to perform the checksum computation on the incoming packet. Note that ip header + checksum will be computed by the kernel immaterial of what we inform. Similary TCP/UDP/ICMP + pseudo header checksum will be computed by the stack. What we can inform is not to perform + payload checksum. + When CHECKSUM_UNNECESSARY is set kernel bypasses the checksum computation. + */ + + TR("Checksum Offloading will be done now\n"); + + if (synopGMAC_is_ext_status(gmacdev, status)) // extended status present indicates that the RDES4 need to be probed + { + TR("Extended Status present\n"); + if (synopGMAC_ES_is_IP_header_error(gmacdev, ext_status)) // IP header (IPV4) checksum error + { + //Linux Kernel doesnot care for ipv4 header checksum. So we will simply proceed by printing a warning .... + TR("(EXTSTS)Error in IP header error\n"); + gmacdev->synopGMACNetStats.rx_ip_header_errors++; + } + if (synopGMAC_ES_is_rx_checksum_bypassed(gmacdev, ext_status)) // Hardware engine bypassed the checksum computation/checking + { + TR("(EXTSTS)Hardware bypassed checksum computation\n"); + } + if (synopGMAC_ES_is_IP_payload_error(gmacdev, ext_status)) // IP payload checksum is in error (UDP/TCP/ICMP checksum error) + { + TR("(EXTSTS) Error in EP payload\n"); + gmacdev->synopGMACNetStats.rx_ip_payload_errors++; + } + } + else // No extended status. So relevant information is available in the status itself + { + if (synopGMAC_is_rx_checksum_error(gmacdev, status) == RxNoChkError) + { + TR("Ip header and TCP/UDP payload checksum Bypassed \n"); + } + if (synopGMAC_is_rx_checksum_error(gmacdev, status) == RxIpHdrChkError) + { + //Linux Kernel doesnot care for ipv4 header checksum. So we will simply proceed by printing a warning .... + TR(" Error in 16bit IPV4 Header Checksum \n"); + gmacdev->synopGMACNetStats.rx_ip_header_errors++; + } + if (synopGMAC_is_rx_checksum_error(gmacdev, status) == RxLenLT600) + { + TR("IEEE 802.3 type frame with Length field Lesss than 0x0600 \n"); + } + if (synopGMAC_is_rx_checksum_error(gmacdev, status) == RxIpHdrPayLoadChkBypass) + { + TR("Ip header and TCP/UDP payload checksum Bypassed \n"); + } + if (synopGMAC_is_rx_checksum_error(gmacdev, status) == RxChkBypass) + { + TR("Ip header and TCP/UDP payload checksum Bypassed \n"); + } + if (synopGMAC_is_rx_checksum_error(gmacdev, status) == RxPayLoadChkError) + { + TR(" TCP/UDP payload checksum Error \n"); + gmacdev->synopGMACNetStats.rx_ip_payload_errors++; + } + if (synopGMAC_is_rx_checksum_error(gmacdev, status) == RxIpHdrPayLoadChkError) + { + //Linux Kernel doesnot care for ipv4 header checksum. So we will simply proceed by printing a warning .... + TR(" Both IP header and Payload Checksum Error \n"); + gmacdev->synopGMACNetStats.rx_ip_header_errors++; + gmacdev->synopGMACNetStats.rx_ip_payload_errors++; + } + } + *ppsPktFrame = (PKT_FRAME_T *)dma_addr1; +#if 0 +#ifdef CACHE_ON + memcpy((void *)pu8rb, (void *)((u32)dma_addr1 | UNCACHEABLE), len); +#else + memcpy((void *)pu8rb, (void *)((u32)dma_addr1), len); +#endif + if (prevtx != NULL) + { +#ifdef CACHE_ON + memcpy((void *)pu8rb + len, (void *)((u32)(dma_addr1 | UNCACHEABLE) + len), 4); +#else + memcpy((void *)pu8rb + len, (void *)((u32)dma_addr1 + len), 4); +#endif + } +// rb->rdy = 1; +// rb->len = len; +#endif + gmacdev->synopGMACNetStats.rx_packets++; + gmacdev->synopGMACNetStats.rx_bytes += len; + if (status & DescRxTSAvailable) + { + gmacdev->rx_sec = time_stamp_high; + gmacdev->rx_subsec = time_stamp_low; + } + else + { + gmacdev->rx_sec = 0; + gmacdev->rx_subsec = 0; + } + return len; + } // if ( synopGMAC_is_rx_desc_valid(status) ) + else + { + /*Now the present skb should be set free*/ + TR("s: %08x\n", status); + gmacdev->synopGMACNetStats.rx_errors++; + gmacdev->synopGMACNetStats.collisions += synopGMAC_is_rx_frame_collision(status); + gmacdev->synopGMACNetStats.rx_crc_errors += synopGMAC_is_rx_crc(status); + gmacdev->synopGMACNetStats.rx_frame_errors += synopGMAC_is_frame_dribbling_errors(status); + gmacdev->synopGMACNetStats.rx_length_errors += synopGMAC_is_rx_frame_length_errors(status); + } + + } // /*Handle the Receive Descriptors*/ + + return 0; +} + +// mode 0: 1000Mbps, 1: 100Mbps, 2: 10Mbps +void synopGMAC_set_mode(synopGMACdevice *gmacdev, int mode) +{ + // Must stop Tx/Rx before change speed/mode + synopGMAC_tx_disable(gmacdev); + synopGMAC_rx_disable(gmacdev); + switch (mode) + { + case SPEED1000: + synopGMACClearBits(gmacdev->MacBase, GmacConfig, GmacMiiGmii); + gmacdev->Speed = SPEED1000; + break; + case SPEED100: + synopGMACSetBits(gmacdev->MacBase, GmacConfig, GmacMiiGmii); + synopGMACSetBits(gmacdev->MacBase, GmacConfig, GmacFESpeed100); + gmacdev->Speed = SPEED100; + break; + case SPEED10: + synopGMACSetBits(gmacdev->MacBase, GmacConfig, GmacMiiGmii); + synopGMACClearBits(gmacdev->MacBase, GmacConfig, GmacFESpeed100); + gmacdev->Speed = SPEED10; + default: + break; + } + synopGMAC_tx_enable(gmacdev); + synopGMAC_rx_enable(gmacdev); +} diff --git a/bsp/nuvoton/libraries/ma35/rtt_port/gmac/synopGMAC_network_interface.h b/bsp/nuvoton/libraries/ma35/rtt_port/gmac/synopGMAC_network_interface.h new file mode 100644 index 0000000000..dad081209e --- /dev/null +++ b/bsp/nuvoton/libraries/ma35/rtt_port/gmac/synopGMAC_network_interface.h @@ -0,0 +1,54 @@ +/* =================================================================================== + * Copyright (c) <2009> Synopsys, Inc. + * + * Permission is hereby granted, free of charge, to any person obtaining a copy of + * this software annotated with this license and associated documentation files + * (the "Software"), to deal in the Software without restriction, including without + * limitation the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the Software is + * furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in all + * copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, + * INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS FOR A + * PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT + * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION + * OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE + * OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + * + * =================================================================================== */ + +/** \file + * Header file for the nework dependent functionality. + * The function prototype listed here are linux dependent. + * + * \internal + * ---------------------------REVISION HISTORY------------------- + * Synopsys 01/Aug/2007 Created + */ +#ifndef SYNOP_GMAC_NETWORK_INTERFACE_H +#define SYNOP_GMAC_NETWORK_INTERFACE_H 1 + +#include "synopGMAC_Dev.h" +#define TEST_RGMII +//#define TEST_RMII +#define CACHE_ON + +/** Tx/Rx buffer structure */ +typedef struct +{ + uint8_t au8Buf[PKT_FRAME_BUF_SIZE]; +} PKT_FRAME_T; + +s32 synopGMAC_setup_tx_desc_queue(synopGMACdevice *gmacdev, DmaDesc *first_desc, u32 no_of_desc, u32 desc_mode); +s32 synopGMAC_setup_rx_desc_queue(synopGMACdevice *gmacdev, DmaDesc *first_desc, u32 no_of_desc, u32 desc_mode); +s32 synopGMAC_xmit_frames(synopGMACdevice *gmacdev, u8 *pkt_data, u32 pkt_len, u32 offload_needed, u32 ts); +s32 synop_handle_received_data(synopGMACdevice *gmacdev, PKT_FRAME_T **ppsPktFrame); +void synop_handle_transmit_over(synopGMACdevice *gmacdev); +void synopGMAC_set_mode(synopGMACdevice *gmacdev, int mode); +void synopGMAC_powerup_mac(synopGMACdevice *gmacdev); +void synopGMAC_powerdown_mac(synopGMACdevice *gmacdev); + +#endif /* End of file */ diff --git a/bsp/nuvoton/libraries/ma35/rtt_port/gmac/synopGMAC_plat.c b/bsp/nuvoton/libraries/ma35/rtt_port/gmac/synopGMAC_plat.c new file mode 100644 index 0000000000..b483979c91 --- /dev/null +++ b/bsp/nuvoton/libraries/ma35/rtt_port/gmac/synopGMAC_plat.c @@ -0,0 +1,78 @@ +/* + * Copyright (c) 2006-2022, RT-Thread Development Team + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + * 2021-08-24 Wayne first version + */ + +#include "synopGMAC_plat.h" + +void plat_delay(u32 delay) +{ + volatile u32 loop = delay; + while (loop--); +} + +u32 synopGMACReadReg(u32 RegBase, u32 RegOffset) +{ + u32 addr = RegBase + RegOffset; + u32 data = *((volatile u32 *)addr); + +#if SYNOP_REG_DEBUG + TR("%s RegBase = 0x%08x RegOffset = 0x%08x RegData = 0x%08x\n", __FUNCTION__, (u32)RegBase, RegOffset, data); +#endif + + return data; +} + +void synopGMACWriteReg(u32 RegBase, u32 RegOffset, u32 RegData) +{ + u32 addr = RegBase + (u32)RegOffset; + +#if SYNOP_REG_DEBUG + TR("%s RegBase = 0x%08x RegOffset = 0x%08x RegData = 0x%08x\n", __FUNCTION__, (u32) RegBase, RegOffset, RegData); +#endif + + *((volatile u32 *)addr) = RegData; + + return; +} + +void synopGMACSetBits(u32 RegBase, u32 RegOffset, u32 BitPos) +{ + u32 data = synopGMACReadReg(RegBase, RegOffset) | BitPos; + + synopGMACWriteReg(RegBase, RegOffset, data); + +#if SYNOP_REG_DEBUG + TR("%s !!!!!!!!!!!!! RegOffset = 0x%08x RegData = 0x%08x\n", __FUNCTION__, RegOffset, data); +#endif + + return; +} + +void synopGMACClearBits(u32 RegBase, u32 RegOffset, u32 BitPos) +{ + u32 data = synopGMACReadReg(RegBase, RegOffset) & (~BitPos); + + synopGMACWriteReg(RegBase, RegOffset, data); + +#if SYNOP_REG_DEBUG + TR("%s !!!!!!!!!!!!! RegOffset = 0x%08x RegData = 0x%08x\n", __FUNCTION__, RegOffset, data); +#endif + + return; +} + +bool synopGMACCheckBits(u32 RegBase, u32 RegOffset, u32 BitPos) +{ + u32 data = synopGMACReadReg(RegBase, RegOffset) & BitPos; + + if (data) + return true; + else + return false; +} diff --git a/bsp/nuvoton/libraries/ma35/rtt_port/gmac/synopGMAC_plat.h b/bsp/nuvoton/libraries/ma35/rtt_port/gmac/synopGMAC_plat.h new file mode 100644 index 0000000000..cf0b85c5bb --- /dev/null +++ b/bsp/nuvoton/libraries/ma35/rtt_port/gmac/synopGMAC_plat.h @@ -0,0 +1,44 @@ +/* + * Copyright (c) 2006-2022, RT-Thread Development Team + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + * 2021-08-24 Wayne first version + */ + +#ifndef SYNOP_GMAC_PLAT_H +#define SYNOP_GMAC_PLAT_H 1 + +#include +#include "synopGMAC_types.h" +#include "drv_common.h" + +#define DEFAULT_DELAY_VARIABLE 10 +#define DEFAULT_LOOP_VARIABLE 1000 + +/* Error Codes */ +#define ESYNOPGMACNOERR 0 +#define ESYNOPGMACNOMEM 1 +#define ESYNOPGMACPHYERR 2 +#define ESYNOPGMACBUSY 3 + +#define TR0(fmt, args...) rt_kprintf("SynopGMAC: " fmt, ##args) + +//#define DEBUG +#ifdef DEBUG + #undef TR + #define TR(fmt, args...) rt_kprintf("SynopGMAC: " fmt, ##args) +#else + #define TR(fmt, args...) /* not debugging: nothing */ +#endif + +u32 synopGMACReadReg(u32 RegBase, u32 RegOffset); +void synopGMACWriteReg(u32 RegBase, u32 RegOffset, u32 RegData); +void synopGMACSetBits(u32 RegBase, u32 RegOffset, u32 BitPos); +void synopGMACClearBits(u32 RegBase, u32 RegOffset, u32 BitPos); +bool synopGMACCheckBits(u32 RegBase, u32 RegOffset, u32 BitPos); +void plat_delay(u32); + +#endif diff --git a/bsp/nuvoton/libraries/ma35/rtt_port/gmac/synopGMAC_types.h b/bsp/nuvoton/libraries/ma35/rtt_port/gmac/synopGMAC_types.h new file mode 100644 index 0000000000..9f8f081aa9 --- /dev/null +++ b/bsp/nuvoton/libraries/ma35/rtt_port/gmac/synopGMAC_types.h @@ -0,0 +1,31 @@ +/* + * Copyright (c) 2006-2022, RT-Thread Development Team + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + * 2017-08-24 chinesebear first version + */ + +#ifndef __TYPES__H +#define __TYPES__H + +typedef unsigned char uint8_t; +typedef unsigned long long u64; +typedef unsigned int u32; +typedef unsigned short u16; +typedef unsigned char u8; +typedef signed int s32; + +typedef int bool; +enum synopGMAC_boolean +{ + false = 0, + true = 1 +}; + +//typedef u32 dma_addr_t; +typedef u32 *dma_addr_t; + +#endif /*__TYPES__H*/ diff --git a/bsp/nuvoton/libraries/ma35/rtt_port/nu_clock_init.c b/bsp/nuvoton/libraries/ma35/rtt_port/nu_clock_init.c new file mode 100644 index 0000000000..228a704f7b --- /dev/null +++ b/bsp/nuvoton/libraries/ma35/rtt_port/nu_clock_init.c @@ -0,0 +1,398 @@ +/**************************************************************************//** +* +* @copyright (C) 2019 Nuvoton Technology Corp. All rights reserved. +* +* SPDX-License-Identifier: Apache-2.0 +* +* Change Logs: +* Date Author Notes +* 2021-6-1 Wayne First version +* +******************************************************************************/ + +#include "board.h" + +static void nu_clock_uart_init(void) +{ +#if defined(BSP_USING_UART0) + CLK_EnableModuleClock(UART0_MODULE); + CLK_SetModuleClock(UART0_MODULE, CLK_CLKSEL2_UART0SEL_HXT, CLK_CLKDIV1_UART0(1)); +#endif +#if defined(BSP_USING_UART1) + CLK_EnableModuleClock(UART1_MODULE); + CLK_SetModuleClock(UART1_MODULE, CLK_CLKSEL2_UART1SEL_HXT, CLK_CLKDIV1_UART1(1)); +#endif +#if defined(BSP_USING_UART2) + CLK_EnableModuleClock(UART2_MODULE); + CLK_SetModuleClock(UART2_MODULE, CLK_CLKSEL2_UART2SEL_HXT, CLK_CLKDIV1_UART2(1)); +#endif +#if defined(BSP_USING_UART3) + CLK_EnableModuleClock(UART3_MODULE); + CLK_SetModuleClock(UART3_MODULE, CLK_CLKSEL2_UART3SEL_HXT, CLK_CLKDIV1_UART3(1)); +#endif +#if defined(BSP_USING_UART4) + CLK_EnableModuleClock(UART4_MODULE); + CLK_SetModuleClock(UART4_MODULE, CLK_CLKSEL2_UART4SEL_HXT, CLK_CLKDIV1_UART4(1)); +#endif +#if defined(BSP_USING_UART5) + CLK_EnableModuleClock(UART5_MODULE); + CLK_SetModuleClock(UART5_MODULE, CLK_CLKSEL2_UART5SEL_HXT, CLK_CLKDIV1_UART5(1)); +#endif +#if defined(BSP_USING_UART6) + CLK_EnableModuleClock(UART6_MODULE); + CLK_SetModuleClock(UART6_MODULE, CLK_CLKSEL2_UART6SEL_HXT, CLK_CLKDIV1_UART6(1)); +#endif +#if defined(BSP_USING_UART7) + CLK_EnableModuleClock(UART7_MODULE); + CLK_SetModuleClock(UART7_MODULE, CLK_CLKSEL2_UART7SEL_HXT, CLK_CLKDIV1_UART7(1)); +#endif +#if defined(BSP_USING_UART8) + CLK_EnableModuleClock(UART8_MODULE); + CLK_SetModuleClock(UART8_MODULE, CLK_CLKSEL3_UART8SEL_HXT, CLK_CLKDIV1_UART8(1)); +#endif +#if defined(BSP_USING_UART9) + CLK_EnableModuleClock(UART9_MODULE); + CLK_SetModuleClock(UART9_MODULE, CLK_CLKSEL3_UART9SEL_HXT, CLK_CLKDIV2_UART9(1)); +#endif +#if defined(BSP_USING_UART10) + CLK_EnableModuleClock(UART10_MODULE); + CLK_SetModuleClock(UART10_MODULE, CLK_CLKSEL3_UART10SEL_HXT, CLK_CLKDIV2_UART10(1)); +#endif +#if defined(BSP_USING_UART11) + CLK_EnableModuleClock(UART11_MODULE); + CLK_SetModuleClock(UART11_MODULE, CLK_CLKSEL3_UART11SEL_HXT, CLK_CLKDIV2_UART11(1)); +#endif +#if defined(BSP_USING_UART12) + CLK_EnableModuleClock(UART12_MODULE); + CLK_SetModuleClock(UART12_MODULE, CLK_CLKSEL3_UART12SEL_HXT, CLK_CLKDIV3_UART12(1)); +#endif +#if defined(BSP_USING_UART13) + CLK_EnableModuleClock(UART13_MODULE); + CLK_SetModuleClock(UART13_MODULE, CLK_CLKSEL3_UART13SEL_HXT, CLK_CLKDIV3_UART13(1)); +#endif +#if defined(BSP_USING_UART14) + CLK_EnableModuleClock(UART14_MODULE); + CLK_SetModuleClock(UART14_MODULE, CLK_CLKSEL3_UART14SEL_HXT, CLK_CLKDIV3_UART14(1)); +#endif +#if defined(BSP_USING_UART15) + CLK_EnableModuleClock(UART15_MODULE); + CLK_SetModuleClock(UART15_MODULE, CLK_CLKSEL3_UART15SEL_HXT, CLK_CLKDIV3_UART15(1)); +#endif +#if defined(BSP_USING_UART16) + CLK_EnableModuleClock(UART16_MODULE); + CLK_SetModuleClock(UART16_MODULE, CLK_CLKSEL3_UART16SEL_HXT, CLK_CLKDIV3_UART16(1)); +#endif +} + +static void nu_clock_pdma_init(void) +{ +#if defined(BSP_USING_PDMA0) + CLK_EnableModuleClock(PDMA0_MODULE); +#endif +#if defined(BSP_USING_PDMA1) + CLK_EnableModuleClock(PDMA1_MODULE); +#endif +#if defined(BSP_USING_PDMA2) + CLK_EnableModuleClock(PDMA2_MODULE); +#endif +#if defined(BSP_USING_PDMA3) + CLK_EnableModuleClock(PDMA3_MODULE); +#endif +} + +static void nu_clock_gpio_init(void) +{ +#if defined(BSP_USING_GPIO) + CLK_EnableModuleClock(GPA_MODULE); + CLK_EnableModuleClock(GPB_MODULE); + CLK_EnableModuleClock(GPC_MODULE); + CLK_EnableModuleClock(GPD_MODULE); + CLK_EnableModuleClock(GPE_MODULE); + CLK_EnableModuleClock(GPF_MODULE); + CLK_EnableModuleClock(GPG_MODULE); + CLK_EnableModuleClock(GPH_MODULE); + CLK_EnableModuleClock(GPI_MODULE); + CLK_EnableModuleClock(GPJ_MODULE); + CLK_EnableModuleClock(GPK_MODULE); + CLK_EnableModuleClock(GPL_MODULE); + CLK_EnableModuleClock(GPM_MODULE); + CLK_EnableModuleClock(GPN_MODULE); +#endif +} + +static void nu_clock_qspi_init(void) +{ +#if defined(BSP_USING_QSPI0) + CLK_EnableModuleClock(QSPI0_MODULE); + CLK_SetModuleClock(QSPI0_MODULE, CLK_CLKSEL4_QSPI0SEL_PCLK0, MODULE_NoMsk); +#endif +#if defined(BSP_USING_QSPI1) + CLK_EnableModuleClock(QSPI1_MODULE); + CLK_SetModuleClock(QSPI1_MODULE, CLK_CLKSEL4_QSPI1SEL_PCLK0, MODULE_NoMsk); +#endif +} + +static void nu_clock_spi_init(void) +{ +#if defined(BSP_USING_SPI0) + CLK_EnableModuleClock(SPI0_MODULE); + CLK_SetModuleClock(SPI0_MODULE, CLK_CLKSEL4_SPI0SEL_PCLK1, MODULE_NoMsk); +#endif +#if defined(BSP_USING_SPI1) + CLK_EnableModuleClock(SPI1_MODULE); + CLK_SetModuleClock(SPI1_MODULE, CLK_CLKSEL4_SPI1SEL_PCLK2, MODULE_NoMsk); +#endif +#if defined(BSP_USING_SPI2) + CLK_EnableModuleClock(SPI2_MODULE); + CLK_SetModuleClock(SPI2_MODULE, CLK_CLKSEL4_SPI2SEL_PCLK1, MODULE_NoMsk); +#endif +#if defined(BSP_USING_SPI3) + CLK_EnableModuleClock(SPI3_MODULE); + CLK_SetModuleClock(SPI3_MODULE, CLK_CLKSEL4_SPI3SEL_PCLK2, MODULE_NoMsk); +#endif +} + +static void nu_clock_i2c_init(void) +{ +#if defined(BSP_USING_I2C0) + CLK_EnableModuleClock(I2C0_MODULE); +#endif +#if defined(BSP_USING_I2C1) + CLK_EnableModuleClock(I2C1_MODULE); +#endif +#if defined(BSP_USING_I2C2) + CLK_EnableModuleClock(I2C2_MODULE); +#endif +#if defined(BSP_USING_I2C3) + CLK_EnableModuleClock(I2C3_MODULE); +#endif +#if defined(BSP_USING_I2C4) + CLK_EnableModuleClock(I2C4_MODULE); +#endif +#if defined(BSP_USING_I2C5) + CLK_EnableModuleClock(I2C5_MODULE); +#endif +} + +static void nu_clock_epwm_init(void) +{ +#if defined(BSP_USING_EPWM0) + CLK_EnableModuleClock(EPWM0_MODULE); +#endif +#if defined(BSP_USING_EPWM1) + CLK_EnableModuleClock(EPWM1_MODULE); +#endif +#if defined(BSP_USING_EPWM2) + CLK_EnableModuleClock(EPWM2_MODULE); +#endif +} + +static void nu_clock_i2s_init(void) +{ +#if defined(BSP_USING_I2S0) + CLK_EnableModuleClock(I2S0_MODULE); + CLK_SetModuleClock(I2S0_MODULE, CLK_CLKSEL4_I2S0SEL_SYSCLK1_DIV2, MODULE_NoMsk); +#endif +#if defined(BSP_USING_I2S1) + CLK_EnableModuleClock(I2S1_MODULE); + CLK_SetModuleClock(I2S1_MODULE, CLK_CLKSEL4_I2S1SEL_SYSCLK1_DIV2, MODULE_NoMsk); +#endif +} + +void nu_clock_timer_init(void) +{ +#if defined(BSP_USING_TMR0) + CLK_EnableModuleClock(TMR0_MODULE); + CLK_SetModuleClock(TMR0_MODULE, CLK_CLKSEL1_TMR0SEL_HXT, MODULE_NoMsk); +#endif +#if defined(BSP_USING_TMR1) + CLK_EnableModuleClock(TMR1_MODULE); + CLK_SetModuleClock(TMR1_MODULE, CLK_CLKSEL1_TMR1SEL_HXT, MODULE_NoMsk); +#endif +#if defined(BSP_USING_TMR2) + CLK_EnableModuleClock(TMR2_MODULE); + CLK_SetModuleClock(TMR2_MODULE, CLK_CLKSEL1_TMR2SEL_HXT, MODULE_NoMsk); +#endif +#if defined(BSP_USING_TMR3) + CLK_EnableModuleClock(TMR3_MODULE); + CLK_SetModuleClock(TMR3_MODULE, CLK_CLKSEL1_TMR3SEL_HXT, MODULE_NoMsk); +#endif +#if defined(BSP_USING_TMR4) + CLK_EnableModuleClock(TMR4_MODULE); + CLK_SetModuleClock(TMR4_MODULE, CLK_CLKSEL1_TMR4SEL_HXT, MODULE_NoMsk); +#endif +#if defined(BSP_USING_TMR5) + CLK_EnableModuleClock(TMR5_MODULE); + CLK_SetModuleClock(TMR5_MODULE, CLK_CLKSEL1_TMR5SEL_HXT, MODULE_NoMsk); +#endif +#if defined(BSP_USING_TMR6) + CLK_EnableModuleClock(TMR6_MODULE); + CLK_SetModuleClock(TMR6_MODULE, CLK_CLKSEL1_TMR6SEL_HXT, MODULE_NoMsk); +#endif +#if defined(BSP_USING_TMR7) + CLK_EnableModuleClock(TMR7_MODULE); + CLK_SetModuleClock(TMR7_MODULE, CLK_CLKSEL1_TMR7SEL_HXT, MODULE_NoMsk); +#endif +#if defined(BSP_USING_TMR8) + CLK_EnableModuleClock(TMR8_MODULE); + CLK_SetModuleClock(TMR8_MODULE, CLK_CLKSEL2_TMR8SEL_HXT, MODULE_NoMsk); +#endif +#if defined(BSP_USING_TMR9) + CLK_EnableModuleClock(TMR9_MODULE); + CLK_SetModuleClock(TMR9_MODULE, CLK_CLKSEL2_TMR9SEL_HXT, MODULE_NoMsk); +#endif +#if defined(BSP_USING_TMR10) + CLK_EnableModuleClock(TMR10_MODULE); + CLK_SetModuleClock(TMR10_MODULE, CLK_CLKSEL2_TMR10SEL_HXT, MODULE_NoMsk); +#endif +#if defined(BSP_USING_TMR11) + CLK_EnableModuleClock(TMR11_MODULE); + CLK_SetModuleClock(TMR11_MODULE, CLK_CLKSEL2_TMR11SEL_HXT, MODULE_NoMsk); +#endif +} + +void nu_clock_wdt_init(void) +{ +#if defined(BSP_USING_WDT0) + CLK_EnableModuleClock(WDT0_MODULE); + CLK_SetModuleClock(WDT0_MODULE, CLK_CLKSEL3_WDT0SEL_PCLK3_DIV4096, MODULE_NoMsk); +#endif +#if defined(BSP_USING_WDT1) + CLK_EnableModuleClock(WDT1_MODULE); + CLK_SetModuleClock(WDT1_MODULE, CLK_CLKSEL3_WDT1SEL_PCLK3_DIV4096, MODULE_NoMsk); +#endif +#if defined(BSP_USING_WDT2) + CLK_EnableModuleClock(WDT2_MODULE); + CLK_SetModuleClock(WDT2_MODULE, CLK_CLKSEL3_WDT2SEL_PCLK3_DIV4096, MODULE_NoMsk); +#endif +} + +void nu_clock_canfd_init(void) +{ +#if defined(BSP_USING_CANFD0) + CLK_EnableModuleClock(CANFD0_MODULE); + CLK_SetModuleClock(CANFD0_MODULE, CLK_CLKSEL4_CANFD0SEL_APLL, CLK_CLKDIV0_CANFD0(1)); +#endif +#if defined(BSP_USING_CANFD1) + CLK_EnableModuleClock(CANFD1_MODULE); + CLK_SetModuleClock(CANFD1_MODULE, CLK_CLKSEL4_CANFD1SEL_APLL, CLK_CLKDIV0_CANFD1(1)); +#endif +#if defined(BSP_USING_CANFD2) + CLK_EnableModuleClock(CANFD2_MODULE); + CLK_SetModuleClock(CANFD2_MODULE, CLK_CLKSEL4_CANFD2SEL_APLL, CLK_CLKDIV0_CANFD2(1)); +#endif +#if defined(BSP_USING_CANFD3) + CLK_EnableModuleClock(CANFD3_MODULE); + CLK_SetModuleClock(CANFD3_MODULE, CLK_CLKSEL4_CANFD3SEL_APLL, CLK_CLKDIV0_CANFD3(1)); +#endif +} + +void nu_clock_sc_init(void) +{ +#if defined(BSP_USING_SCUART0) + CLK_EnableModuleClock(SC0_MODULE); + CLK_SetModuleClock(SC0_MODULE, CLK_CLKSEL4_SC0SEL_HXT, MODULE_NoMsk); +#endif +#if defined(BSP_USING_SCUART1) + CLK_EnableModuleClock(SC1_MODULE); + CLK_SetModuleClock(SC1_MODULE, CLK_CLKSEL4_SC1SEL_HXT, MODULE_NoMsk); +#endif +} + +void nu_clock_rtc_init(void) +{ +#if defined(BSP_USING_RTC) + CLK_EnableModuleClock(RTC_MODULE); +#endif +} + +#if !defined(USE_MA35D1_SUBM) + +static void nu_clock_usbd_init(void) +{ +} + +static void nu_clock_usbh_init(void) +{ +} + +static void nu_clock_gmac_init(void) +{ +#if defined(BSP_USING_GMAC0) + CLK_EnableModuleClock(GMAC0_MODULE); +#endif +#if defined(BSP_USING_GMAC1) + CLK_EnableModuleClock(GMAC1_MODULE); +#endif +} + +static void nu_clock_sdh_init(void) +{ +#if defined(BSP_USING_SDH0) + CLK_EnableModuleClock(SDH0_MODULE); +#endif +#if defined(BSP_USING_SDH1) + CLK_EnableModuleClock(SDH1_MODULE); +#endif +} + +static void nu_clock_disp_init(void) +{ +#if defined(BSP_USING_DISP) + CLK_EnableModuleClock(DCU_MODULE); + CLK_SetModuleClock(DCU_MODULE, CLK_CLKSEL0_DCUSEL_EPLL_DIV2, MODULE_NoMsk); + +// CLK_SetModuleClock(DCUP_MODULE, CLK_CLKSEL0_DCUPSEL_VPLL, MODULE_NoMsk); +#endif +} + +void nu_clock_base_init(void) +{ + /* Enable HXT, LXT */ + CLK->PWRCTL |= (CLK_PWRCTL_HXTEN_Msk | CLK_PWRCTL_HIRCEN_Msk | CLK_PWRCTL_LXTEN_Msk | CLK_PWRCTL_LIRCEN_Msk); + + /* Waiting clock ready */ + CLK_WaitClockReady(CLK_STATUS_HXTSTB_Msk); + + /* Waiting clock ready */ + CLK_WaitClockReady(CLK_STATUS_LXTSTB_Msk); + + /* Waiting clock ready */ + CLK_WaitClockReady(CLK_STATUS_HIRCSTB_Msk); + + /* Waiting clock ready */ + CLK_WaitClockReady(CLK_STATUS_LIRCSTB_Msk); +} +#endif + +void nu_clock_init(void) +{ +#if !defined(USE_MA35D1_SUBM) + nu_clock_base_init(); + + nu_clock_gmac_init(); + nu_clock_sdh_init(); + nu_clock_usbd_init(); + nu_clock_usbh_init(); + nu_clock_disp_init(); +#endif + + nu_clock_pdma_init(); + nu_clock_gpio_init(); + nu_clock_uart_init(); + nu_clock_qspi_init(); + nu_clock_spi_init(); + nu_clock_i2c_init(); + nu_clock_epwm_init(); + nu_clock_i2s_init(); + nu_clock_canfd_init(); + nu_clock_sc_init(); + nu_clock_timer_init(); + nu_clock_wdt_init(); + nu_clock_rtc_init(); +} + +void nu_clock_deinit(void) +{ + +} diff --git a/bsp/nuvoton/libraries/n9h30/rtt_port/drv_adc.c b/bsp/nuvoton/libraries/n9h30/rtt_port/drv_adc.c index 9d87e28f22..eea201ea69 100644 --- a/bsp/nuvoton/libraries/n9h30/rtt_port/drv_adc.c +++ b/bsp/nuvoton/libraries/n9h30/rtt_port/drv_adc.c @@ -84,7 +84,7 @@ static void nu_adc_isr(int vector, void *param) volatile rt_int32_t isr, wkisr; nu_adc_t psNuAdc = (nu_adc_t)param; rt_int32_t irqidx; - ADC_T* adc = psNuAdc->base; + ADC_T *adc = psNuAdc->base; //rt_kprintf("[%s %d] CTL: %08x CONF:%08x IER:%08x ISR:%08x\n", __func__, __LINE__, adc->CTL, adc->CONF, adc->IER, adc->ISR); @@ -142,7 +142,7 @@ static int32_t AdcMenuStartCallback(uint32_t status, uint32_t userData) nu_adc_t psNuAdc = (nu_adc_t)userData; #if defined(BSP_USING_ADC_TOUCH) - ADC_T* adc = psNuAdc->base; + ADC_T *adc = psNuAdc->base; static struct nu_adc_touch_data point; static rt_bool_t bDrop = RT_FALSE; static uint32_t u32LastZ0 = 0xffffu; @@ -194,21 +194,23 @@ static int32_t AdcMenuStartCallback(uint32_t status, uint32_t userData) #if defined(BSP_USING_ADC_TOUCH) -static void nu_adc_touch_antiglitch(ADC_T* adc) +static void nu_adc_touch_antiglitch(ADC_T *adc) { int count = 10; - do { + do + { rt_hw_us_delay(1000); // 1ms - ADC_CLR_INT_FLAG(adc, adc->ISR); - if ( adc->ISR == 0 ) + ADC_CLR_INT_FLAG(adc, adc->ISR); + if (adc->ISR == 0) break; - } while(count-- > 0); + } + while (count-- > 0); } void nu_adc_touch_detect(rt_bool_t bStartDetect) { nu_adc_t psNuAdc = (nu_adc_t)&g_sNuADC; - ADC_T* adc = psNuAdc->base; + ADC_T *adc = psNuAdc->base; /* Disable interrupt */ rt_hw_interrupt_mask(psNuAdc->irqn); @@ -217,13 +219,13 @@ void nu_adc_touch_detect(rt_bool_t bStartDetect) /* Disable interrupt */ ADC_DISABLE_INT(adc, ADC_IER_PEDEIEN_Msk | ADC_IER_MIEN_Msk); - nu_adc_touch_antiglitch(adc); + nu_adc_touch_antiglitch(adc); if (bStartDetect == RT_TRUE) { /* Switch to PenDown detection mode */ ADC_DETECT_PD_MODE(adc); - nu_adc_touch_antiglitch(adc); + nu_adc_touch_antiglitch(adc); /* Enable interrupt */ ADC_ENABLE_INT(adc, ADC_IER_PEDEIEN_Msk); @@ -232,7 +234,7 @@ void nu_adc_touch_detect(rt_bool_t bStartDetect) { /* Switch to XY coordination converting mode */ ADC_CONVERT_XY_MODE(adc); - nu_adc_touch_antiglitch(adc); + nu_adc_touch_antiglitch(adc); /* Enable interrupt */ ADC_ENABLE_INT(adc, ADC_IER_MIEN_Msk); @@ -272,7 +274,7 @@ rt_err_t nu_adc_touch_enable(rt_touch_t psRtTouch) { nu_adc_t psNuAdc = (nu_adc_t)&g_sNuADC; nu_adc_cb sNuAdcCb; - ADC_T* adc = psNuAdc->base; + ADC_T *adc = psNuAdc->base; adc->CONF = 0x0; @@ -315,7 +317,7 @@ rt_err_t nu_adc_touch_disable(void) static void nu_adc_touch_smpl(void *p) { nu_adc_t psNuAdc = (nu_adc_t)p; - if ( psNuAdc->bReset ) + if (psNuAdc->bReset) { psNuAdc->bReset = 0; nu_adc_touch_detect(RT_FALSE); @@ -330,7 +332,7 @@ static rt_err_t _nu_adc_control(rt_device_t dev, int cmd, void *args) { rt_err_t ret = RT_EINVAL ; nu_adc_t psNuAdc = (nu_adc_t)dev; - ADC_T* adc = psNuAdc->base; + ADC_T *adc = psNuAdc->base; nu_adc_cb_t psAdcCb = (nu_adc_cb_t)args; @@ -473,7 +475,7 @@ static rt_err_t _nu_adc_control(rt_device_t dev, int cmd, void *args) static rt_err_t _nu_adc_open(rt_device_t dev, rt_uint16_t oflag) { nu_adc_t psNuAdc = (nu_adc_t)dev; - ADC_T* adc = psNuAdc->base; + ADC_T *adc = psNuAdc->base; /* Enable ADC engine clock */ nu_sys_ipclk_enable(psNuAdc->clkidx); @@ -499,7 +501,7 @@ static rt_err_t _nu_adc_open(rt_device_t dev, rt_uint16_t oflag) static rt_err_t _nu_adc_close(rt_device_t dev) { nu_adc_t psNuAdc = (nu_adc_t)dev; - ADC_T* adc = psNuAdc->base; + ADC_T *adc = psNuAdc->base; /* Disable Normal AD Conversion */ _nu_adc_control(dev, NAC_OFF, RT_NULL); diff --git a/bsp/nuvoton/libraries/n9h30/rtt_port/drv_usbhost.c b/bsp/nuvoton/libraries/n9h30/rtt_port/drv_usbhost.c index 64e9dbf3ae..bb29de3ea0 100644 --- a/bsp/nuvoton/libraries/n9h30/rtt_port/drv_usbhost.c +++ b/bsp/nuvoton/libraries/n9h30/rtt_port/drv_usbhost.c @@ -20,6 +20,13 @@ #include "usb.h" #include "usbh_lib.h" +#define LOG_TAG "drv.usbhost" +#define DBG_ENABLE +#define DBG_SECTION_NAME LOG_TAG +#define DBG_LEVEL LOG_LVL_DBG +#define DBG_COLOR +#include + #if !defined(NU_USBHOST_HUB_POLLING_INTERVAL) #define NU_USBHOST_HUB_POLLING_INTERVAL (100) #endif @@ -30,6 +37,8 @@ #define NU_MAX_USBH_HUB_PORT_DEV USB_HUB_PORT_NUM +#define NU_USBHOST_HUB_POLLING_LOCK +#if defined(NU_USBHOST_HUB_POLLING_LOCK) #define NU_USBHOST_MUTEX_INIT() { \ s_sUSBHDev.lock = rt_mutex_create("usbhost_lock", RT_IPC_FLAG_PRIO); \ RT_ASSERT(s_sUSBHDev.lock != RT_NULL); \ @@ -44,6 +53,11 @@ rt_err_t result = rt_mutex_release(s_sUSBHDev.lock); \ RT_ASSERT(result == RT_EOK); \ } +#else +#define NU_USBHOST_MUTEX_INIT() +#define NU_USBHOST_LOCK() +#define NU_USBHOST_UNLOCK() +#endif /* Private typedef --------------------------------------------------------------*/ typedef struct nu_port_dev @@ -52,6 +66,7 @@ typedef struct nu_port_dev UDEV_T *pUDev; EP_INFO_T *apsEPInfo[NU_MAX_USBH_PIPE]; struct urequest asSetupReq[NU_MAX_USBH_PIPE]; + uint32_t u32SentLength[NU_MAX_USBH_PIPE]; struct rt_completion utr_completion; int port_num; rt_bool_t bEnumDone; @@ -91,6 +106,12 @@ GetRHPortControlFromPipe( { uinst_t inst; int port; + + if (!pipe || + !pipe->inst || + !pipe->inst->parent_hub) + return RT_NULL; + if (pipe->inst->parent_hub->is_roothub) { //case: device ---> root hub @@ -470,22 +491,30 @@ static int nu_int_xfer( int timeouts) { int ret; - int retry = 3; - while (retry > 0) + while (1) { ret = usbh_int_xfer(psUTR); - if (ret == 0) + if (ret < 0) + return ret; + + if (rt_completion_wait(&(psPortDev->utr_completion), timeouts) != 0) + { + RT_DEBUG_LOG(RT_DEBUG_USB, ("Request %08x Timeout in %d ms!!\n", psUTR, timeouts)); + usbh_quit_utr(psUTR); + + rt_completion_init(&(psPortDev->utr_completion)); + rt_thread_mdelay(1); + } + else + { + + RT_DEBUG_LOG(RT_DEBUG_USB, ("Transferring done %08x\n", psUTR)); + usbh_quit_utr(psUTR); break; - - RT_DEBUG_LOG(RT_DEBUG_USB, ("nu_int_xfer ERROR: failed to submit interrupt request\n")); - rt_thread_delay((pipe->ep.bInterval * RT_TICK_PER_SECOND / 1000) > 0 ? (pipe->ep.bInterval * RT_TICK_PER_SECOND / 1000) : 1); - retry --; + } } - if (ret < 0) - return ret; - return 0; } @@ -497,30 +526,6 @@ static void xfer_done_cb(UTR_T *psUTR) rt_completion_done(&(psPortDev->utr_completion)); } -static void int_xfer_done_cb(UTR_T *psUTR) -{ - upipe_t pipe = (upipe_t)psUTR->context; - - if (psUTR->status != 0) - { - RT_DEBUG_LOG(RT_DEBUG_USB, ("Interrupt xfer failed %d\n", psUTR->status)); - goto exit_int_xfer_done_cb; - } - - if (pipe->callback != RT_NULL) - { - struct uhost_msg msg; - msg.type = USB_MSG_CALLBACK; - msg.content.cb.function = pipe->callback; - msg.content.cb.context = pipe; - rt_usbh_event_signal(&s_sUSBHDev.uhcd, &msg); - } - -exit_int_xfer_done_cb: - - free_utr(psUTR); -} - static int nu_pipe_xfer(upipe_t pipe, rt_uint8_t token, void *buffer, int nbytes, int timeouts) { S_NU_RH_PORT_CTRL *psPortCtrl; @@ -565,6 +570,7 @@ static int nu_pipe_xfer(upipe_t pipe, rt_uint8_t token, void *buffer, int nbytes { struct urequest *psSetup = (struct urequest *)buffer_nonch; RT_ASSERT(buffer_nonch != RT_NULL); + psPortCtrl->asHubPortDev->u32SentLength[pipe->pipe_index] = 0; /* Read data from USB device. */ if (psSetup->request_type & USB_REQ_TYPE_DIR_IN) @@ -586,10 +592,35 @@ static int nu_pipe_xfer(upipe_t pipe, rt_uint8_t token, void *buffer, int nbytes //token == USBH_PID_DATA if (buffer_nonch && ((pipe->ep.bEndpointAddress & USB_DIR_MASK) == USB_DIR_IN)) { + struct urequest *psSetup = &psPortCtrl->asHubPortDev->asSetupReq[pipe->pipe_index]; + /* Read data from USB device. */ //Trigger USBHostLib Ctril_Xfer - ret = nu_ctrl_xfer(psPortDev, &psPortCtrl->asHubPortDev->asSetupReq[pipe->pipe_index], buffer_nonch, timeouts); - if (ret != nbytes) + /* + * Workaround: HCD driver can readback all bytes of setup.wLength, but not support single packet transferring. + */ + if (psPortCtrl->asHubPortDev->u32SentLength[pipe->pipe_index] == 0) + { + ret = nu_ctrl_xfer(psPortDev, psSetup, buffer_nonch, timeouts); + psPortCtrl->asHubPortDev->u32SentLength[pipe->pipe_index] = ret; + if (ret > 0) + { + rt_memcpy(buffer, buffer_nonch, ret); + } + } + else + { + if (psPortCtrl->asHubPortDev->u32SentLength[pipe->pipe_index] < nbytes) + { + ret = 0; + } + else + { + psPortCtrl->asHubPortDev->u32SentLength[pipe->pipe_index] -= nbytes; + ret = nbytes; + } + } + if (ret <= 0) goto exit_nu_pipe_xfer; } else @@ -599,7 +630,7 @@ static int nu_pipe_xfer(upipe_t pipe, rt_uint8_t token, void *buffer, int nbytes } //else i32XferLen = nbytes; - goto exit_nu_pipe_xfer; + goto exit_nu_pipe_xfer2; } // if ( pipe->ep.bmAttributes == USB_EP_ATTR_CONTROL ) else { @@ -634,9 +665,6 @@ static int nu_pipe_xfer(upipe_t pipe, rt_uint8_t token, void *buffer, int nbytes } else if (pipe->ep.bmAttributes == USB_EP_ATTR_INT) { - psUTR->func = int_xfer_done_cb; - psUTR->context = pipe; - if (nu_int_xfer(pipe, psPortDev, psUTR, timeouts) < 0) { RT_DEBUG_LOG(RT_DEBUG_USB, ("nu_pipe_xfer ERROR: int transfer failed\n")); @@ -646,7 +674,7 @@ static int nu_pipe_xfer(upipe_t pipe, rt_uint8_t token, void *buffer, int nbytes { i32XferLen = nbytes; } - goto exit2_nu_pipe_xfer; + goto exit_nu_pipe_xfer; } else if (pipe->ep.bmAttributes == USB_EP_ATTR_ISOC) { @@ -685,19 +713,17 @@ failreport_nu_pipe_xfer: i32XferLen = psUTR->xfer_len; +exit_nu_pipe_xfer: + //Call callback if (pipe->callback != RT_NULL) { pipe->callback(pipe); } -exit_nu_pipe_xfer: - if (psUTR) free_utr(psUTR); -exit2_nu_pipe_xfer: - #if defined(BSP_USING_MMU) if ((nbytes) && (buffer_nonch != buffer)) @@ -709,6 +735,8 @@ exit2_nu_pipe_xfer: } #endif +exit_nu_pipe_xfer2: + NU_USBHOST_UNLOCK(); return i32XferLen; @@ -951,6 +979,6 @@ int nu_usbh_register(void) return 0; } -INIT_DEVICE_EXPORT(nu_usbh_register); +INIT_APP_EXPORT(nu_usbh_register); #endif diff --git a/bsp/nuvoton/libraries/nu_packages/CCAP_Sensors/ccap_demo.c b/bsp/nuvoton/libraries/nu_packages/CCAP_Sensors/ccap_demo.c index b0e5823f54..41426d2f8f 100644 --- a/bsp/nuvoton/libraries/nu_packages/CCAP_Sensors/ccap_demo.c +++ b/bsp/nuvoton/libraries/nu_packages/CCAP_Sensors/ccap_demo.c @@ -124,7 +124,7 @@ static rt_device_t ccap_sensor_init(ccap_grabber_context_t psGrabberContext, cca psCcapConfig->sPipeInfo_Planar.u32Width = psLcdInfo->width / 2; psCcapConfig->sPipeInfo_Planar.u32Height = psLcdInfo->height / 2; psCcapConfig->sPipeInfo_Planar.pu8FarmAddr = rt_malloc_align(psCcapConfig->sPipeInfo_Planar.u32Height * psCcapConfig->sPipeInfo_Planar.u32Width * 2, 32); - psCcapConfig->sPipeInfo_Planar.u32PixFmt = CCAP_PAR_PLNFMT_YUV422; + psCcapConfig->sPipeInfo_Planar.u32PixFmt = CCAP_PAR_PLNFMT_YUV420; //CCAP_PAR_PLNFMT_YUV422; psCcapConfig->u32Stride_Planar = psCcapConfig->sPipeInfo_Planar.u32Width; if (psCcapConfig->sPipeInfo_Planar.pu8FarmAddr == RT_NULL) @@ -354,6 +354,7 @@ static void ccap_grabber(void *parameter) goto exit_ccap_grabber; } + /* Get LCD Info */ ret = rt_device_control(psDevLcd, RTGRAPHIC_CTRL_GET_INFO, &sGrabberContext.sLcdInfo); if (ret != RT_EOK) { @@ -361,10 +362,13 @@ static void ccap_grabber(void *parameter) goto exit_ccap_grabber; } + /* Check panel type */ if (rt_device_control(psDevLcd, RTGRAPHIC_CTRL_PAN_DISPLAY, (void *)sGrabberContext.sLcdInfo.framebuffer) == RT_EOK) { /* Sync-type LCD panel, will draw to VRAM directly. */ + int pixfmt = RTGRAPHIC_PIXEL_FORMAT_RGB565; bDrawDirect = RT_TRUE; + rt_device_control(psDevLcd, RTGRAPHIC_CTRL_SET_MODE, (void *)&pixfmt); } else { @@ -372,6 +376,13 @@ static void ccap_grabber(void *parameter) bDrawDirect = RT_FALSE; } + ret = rt_device_control(psDevLcd, RTGRAPHIC_CTRL_GET_INFO, &sGrabberContext.sLcdInfo); + if (ret != RT_EOK) + { + LOG_E("Can't get LCD info %s", psGrabberParam->devname_lcd); + goto exit_ccap_grabber; + } + LOG_I("LCD Type: %s-type", bDrawDirect ? "Sync" : "MPU"); LOG_I("LCD Width: %d", sGrabberContext.sLcdInfo.width); LOG_I("LCD Height: %d", sGrabberContext.sLcdInfo.height); @@ -431,19 +442,17 @@ static void ccap_grabber(void *parameter) rt_device_control(psDevLcd, RTGRAPHIC_CTRL_RECT_UPDATE, &sRectInfo); } - else + else if (!DEF_GRID_VIEW) { - int i32FBSize = sGrabberContext.sLcdInfo.width * sGrabberContext.sLcdInfo.height * (sGrabberContext.sLcdInfo.bits_per_pixel / 8); + int i32FBSize = sGrabberContext.sLcdInfo.width * sGrabberContext.sLcdInfo.height * (sGrabberContext.sLcdInfo.bits_per_pixel >> 3); int i32VRAMPiece = sGrabberContext.sLcdInfo.smem_len / i32FBSize; ccap_config sCcapConfig = {0}; - // Pan to next view by grab0 - if (!DEF_GRID_VIEW || !rt_strcmp(psGrabberParam->thread_name, "grab0")) - { - uint32_t u32BufPtr = (uint32_t)sGrabberContext.sCcapConfig.sPipeInfo_Packet.pu8FarmAddr - + (sGrabberContext.u32FrameEnd % i32VRAMPiece) * i32FBSize; - rt_device_control(psDevLcd, RTGRAPHIC_CTRL_PAN_DISPLAY, (void *)u32BufPtr); - } + uint32_t u32BufPtr = (uint32_t)sGrabberContext.sCcapConfig.sPipeInfo_Packet.pu8FarmAddr + + (sGrabberContext.u32FrameEnd % i32VRAMPiece) * i32FBSize; + + /* Pan to valid frame address. */ + rt_device_control(psDevLcd, RTGRAPHIC_CTRL_PAN_DISPLAY, (void *)u32BufPtr); sCcapConfig.sPipeInfo_Packet.pu8FarmAddr = sGrabberContext.sCcapConfig.sPipeInfo_Packet.pu8FarmAddr + ((sGrabberContext.u32FrameEnd + 1) % i32VRAMPiece) * i32FBSize ; @@ -473,7 +482,18 @@ static void ccap_grabber(void *parameter) if ((now - last) >= (DEF_DURATION * 1000)) { #if DEF_ENABLE_PLANAR_PIPE - ccap_save_planar_frame(psGrabberParam->thread_name, now, (const void *)sGrabberContext.sCcapConfig.sPipeInfo_Planar.pu8FarmAddr, sGrabberContext.sCcapConfig.sPipeInfo_Planar.u32Width * sGrabberContext.sCcapConfig.sPipeInfo_Planar.u32Height * 2); + { + uint32_t u32Factor = 0; + if (sGrabberContext.sCcapConfig.sPipeInfo_Planar.u32PixFmt == CCAP_PAR_PLNFMT_YUV420) + u32Factor = 3; + else if (sGrabberContext.sCcapConfig.sPipeInfo_Planar.u32PixFmt == CCAP_PAR_PLNFMT_YUV422) + u32Factor = 4; + + if (u32Factor > 0) + { + ccap_save_planar_frame(psGrabberParam->thread_name, now, (const void *)sGrabberContext.sCcapConfig.sPipeInfo_Planar.pu8FarmAddr, sGrabberContext.sCcapConfig.sPipeInfo_Planar.u32Width * sGrabberContext.sCcapConfig.sPipeInfo_Planar.u32Height * u32Factor / 2); + } + } #endif LOG_I("%s: %d FPS", psGrabberParam->devname_ccap, sGrabberContext.u32FrameEnd / DEF_DURATION); sGrabberContext.u32FrameEnd = 0; @@ -519,4 +539,4 @@ int ccap_demo(void) return 0; } MSH_CMD_EXPORT(ccap_demo, camera capture demo); -INIT_APP_EXPORT(ccap_demo); +//INIT_APP_EXPORT(ccap_demo); diff --git a/bsp/nuvoton/libraries/nu_packages/CCAP_Sensors/ccap_sensor.c b/bsp/nuvoton/libraries/nu_packages/CCAP_Sensors/ccap_sensor.c index 50d5d2f654..8b78514a09 100644 --- a/bsp/nuvoton/libraries/nu_packages/CCAP_Sensors/ccap_sensor.c +++ b/bsp/nuvoton/libraries/nu_packages/CCAP_Sensors/ccap_sensor.c @@ -333,26 +333,23 @@ rt_err_t ccap_sensor_register(struct rt_device *device, const char *name, void * return rt_device_register(device, name, RT_DEVICE_FLAG_RDONLY | RT_DEVICE_FLAG_STANDALONE); } -rt_err_t nu_ccap_sensor_create(ccap_sensor_io *psIo, ccap_sensor_id evSensorId) +rt_err_t nu_ccap_sensor_create(ccap_sensor_io *psIo, ccap_sensor_id evSensorId, const char *szName) { static int i32AllocatedSensorId = 0; - char szSensor[16]; rt_err_t ret = -RT_ERROR; ccap_sensor_dev_t pdev = RT_NULL; RT_ASSERT(psIo); RT_ASSERT((evSensorId >= 0) && (evSensorId < evCCAPSNR_CNT)); - rt_snprintf(szSensor, sizeof(szSensor), "sensor%d", i32AllocatedSensorId); - switch (evSensorId) { case evCCAPSNR_HM1055: - pdev = nu_create_hm1055(psIo, szSensor); + pdev = nu_create_hm1055(psIo, szName); break; case evCCAPSNR_ADV728X: - pdev = nu_create_adv728x(psIo, szSensor); + pdev = nu_create_adv728x(psIo, szName); break; default: diff --git a/bsp/nuvoton/libraries/nu_packages/CCAP_Sensors/ccap_sensor.h b/bsp/nuvoton/libraries/nu_packages/CCAP_Sensors/ccap_sensor.h index f7756ca7df..6fe5af24a3 100644 --- a/bsp/nuvoton/libraries/nu_packages/CCAP_Sensors/ccap_sensor.h +++ b/bsp/nuvoton/libraries/nu_packages/CCAP_Sensors/ccap_sensor.h @@ -94,8 +94,8 @@ typedef ccap_sensor_dev *ccap_sensor_dev_t; rt_err_t ccap_sensor_i2c_write(struct rt_i2c_bus_device *i2cdev, rt_uint16_t addr, rt_uint8_t *puBuf, int i32BufLen); rt_err_t ccap_sensor_i2c_read(struct rt_i2c_bus_device *i2cdev, rt_uint16_t addr, rt_uint8_t *puWBuf, int i32WBufLen, rt_uint8_t *puRBuf, int i32RBufLen); -rt_err_t nu_ccap_sensor_create(ccap_sensor_io *psIo, ccap_sensor_id evSensorId); rt_err_t ccap_sensor_register(struct rt_device *device, const char *name, void *user_data); +rt_err_t nu_ccap_sensor_create(ccap_sensor_io *psIo, ccap_sensor_id evSensorId, const char *szName); ccap_sensor_dev_t nu_create_hm1055(ccap_sensor_io *psIo, const char *szName); ccap_sensor_dev_t nu_create_adv728x(ccap_sensor_io *psIo, const char *szName); diff --git a/bsp/nuvoton/libraries/nuc980/rtt_port/drv_adc.c b/bsp/nuvoton/libraries/nuc980/rtt_port/drv_adc.c index 9d87e28f22..eea201ea69 100644 --- a/bsp/nuvoton/libraries/nuc980/rtt_port/drv_adc.c +++ b/bsp/nuvoton/libraries/nuc980/rtt_port/drv_adc.c @@ -84,7 +84,7 @@ static void nu_adc_isr(int vector, void *param) volatile rt_int32_t isr, wkisr; nu_adc_t psNuAdc = (nu_adc_t)param; rt_int32_t irqidx; - ADC_T* adc = psNuAdc->base; + ADC_T *adc = psNuAdc->base; //rt_kprintf("[%s %d] CTL: %08x CONF:%08x IER:%08x ISR:%08x\n", __func__, __LINE__, adc->CTL, adc->CONF, adc->IER, adc->ISR); @@ -142,7 +142,7 @@ static int32_t AdcMenuStartCallback(uint32_t status, uint32_t userData) nu_adc_t psNuAdc = (nu_adc_t)userData; #if defined(BSP_USING_ADC_TOUCH) - ADC_T* adc = psNuAdc->base; + ADC_T *adc = psNuAdc->base; static struct nu_adc_touch_data point; static rt_bool_t bDrop = RT_FALSE; static uint32_t u32LastZ0 = 0xffffu; @@ -194,21 +194,23 @@ static int32_t AdcMenuStartCallback(uint32_t status, uint32_t userData) #if defined(BSP_USING_ADC_TOUCH) -static void nu_adc_touch_antiglitch(ADC_T* adc) +static void nu_adc_touch_antiglitch(ADC_T *adc) { int count = 10; - do { + do + { rt_hw_us_delay(1000); // 1ms - ADC_CLR_INT_FLAG(adc, adc->ISR); - if ( adc->ISR == 0 ) + ADC_CLR_INT_FLAG(adc, adc->ISR); + if (adc->ISR == 0) break; - } while(count-- > 0); + } + while (count-- > 0); } void nu_adc_touch_detect(rt_bool_t bStartDetect) { nu_adc_t psNuAdc = (nu_adc_t)&g_sNuADC; - ADC_T* adc = psNuAdc->base; + ADC_T *adc = psNuAdc->base; /* Disable interrupt */ rt_hw_interrupt_mask(psNuAdc->irqn); @@ -217,13 +219,13 @@ void nu_adc_touch_detect(rt_bool_t bStartDetect) /* Disable interrupt */ ADC_DISABLE_INT(adc, ADC_IER_PEDEIEN_Msk | ADC_IER_MIEN_Msk); - nu_adc_touch_antiglitch(adc); + nu_adc_touch_antiglitch(adc); if (bStartDetect == RT_TRUE) { /* Switch to PenDown detection mode */ ADC_DETECT_PD_MODE(adc); - nu_adc_touch_antiglitch(adc); + nu_adc_touch_antiglitch(adc); /* Enable interrupt */ ADC_ENABLE_INT(adc, ADC_IER_PEDEIEN_Msk); @@ -232,7 +234,7 @@ void nu_adc_touch_detect(rt_bool_t bStartDetect) { /* Switch to XY coordination converting mode */ ADC_CONVERT_XY_MODE(adc); - nu_adc_touch_antiglitch(adc); + nu_adc_touch_antiglitch(adc); /* Enable interrupt */ ADC_ENABLE_INT(adc, ADC_IER_MIEN_Msk); @@ -272,7 +274,7 @@ rt_err_t nu_adc_touch_enable(rt_touch_t psRtTouch) { nu_adc_t psNuAdc = (nu_adc_t)&g_sNuADC; nu_adc_cb sNuAdcCb; - ADC_T* adc = psNuAdc->base; + ADC_T *adc = psNuAdc->base; adc->CONF = 0x0; @@ -315,7 +317,7 @@ rt_err_t nu_adc_touch_disable(void) static void nu_adc_touch_smpl(void *p) { nu_adc_t psNuAdc = (nu_adc_t)p; - if ( psNuAdc->bReset ) + if (psNuAdc->bReset) { psNuAdc->bReset = 0; nu_adc_touch_detect(RT_FALSE); @@ -330,7 +332,7 @@ static rt_err_t _nu_adc_control(rt_device_t dev, int cmd, void *args) { rt_err_t ret = RT_EINVAL ; nu_adc_t psNuAdc = (nu_adc_t)dev; - ADC_T* adc = psNuAdc->base; + ADC_T *adc = psNuAdc->base; nu_adc_cb_t psAdcCb = (nu_adc_cb_t)args; @@ -473,7 +475,7 @@ static rt_err_t _nu_adc_control(rt_device_t dev, int cmd, void *args) static rt_err_t _nu_adc_open(rt_device_t dev, rt_uint16_t oflag) { nu_adc_t psNuAdc = (nu_adc_t)dev; - ADC_T* adc = psNuAdc->base; + ADC_T *adc = psNuAdc->base; /* Enable ADC engine clock */ nu_sys_ipclk_enable(psNuAdc->clkidx); @@ -499,7 +501,7 @@ static rt_err_t _nu_adc_open(rt_device_t dev, rt_uint16_t oflag) static rt_err_t _nu_adc_close(rt_device_t dev) { nu_adc_t psNuAdc = (nu_adc_t)dev; - ADC_T* adc = psNuAdc->base; + ADC_T *adc = psNuAdc->base; /* Disable Normal AD Conversion */ _nu_adc_control(dev, NAC_OFF, RT_NULL); diff --git a/bsp/nuvoton/libraries/nuc980/rtt_port/drv_usbhost.c b/bsp/nuvoton/libraries/nuc980/rtt_port/drv_usbhost.c index 64e9dbf3ae..bb29de3ea0 100644 --- a/bsp/nuvoton/libraries/nuc980/rtt_port/drv_usbhost.c +++ b/bsp/nuvoton/libraries/nuc980/rtt_port/drv_usbhost.c @@ -20,6 +20,13 @@ #include "usb.h" #include "usbh_lib.h" +#define LOG_TAG "drv.usbhost" +#define DBG_ENABLE +#define DBG_SECTION_NAME LOG_TAG +#define DBG_LEVEL LOG_LVL_DBG +#define DBG_COLOR +#include + #if !defined(NU_USBHOST_HUB_POLLING_INTERVAL) #define NU_USBHOST_HUB_POLLING_INTERVAL (100) #endif @@ -30,6 +37,8 @@ #define NU_MAX_USBH_HUB_PORT_DEV USB_HUB_PORT_NUM +#define NU_USBHOST_HUB_POLLING_LOCK +#if defined(NU_USBHOST_HUB_POLLING_LOCK) #define NU_USBHOST_MUTEX_INIT() { \ s_sUSBHDev.lock = rt_mutex_create("usbhost_lock", RT_IPC_FLAG_PRIO); \ RT_ASSERT(s_sUSBHDev.lock != RT_NULL); \ @@ -44,6 +53,11 @@ rt_err_t result = rt_mutex_release(s_sUSBHDev.lock); \ RT_ASSERT(result == RT_EOK); \ } +#else +#define NU_USBHOST_MUTEX_INIT() +#define NU_USBHOST_LOCK() +#define NU_USBHOST_UNLOCK() +#endif /* Private typedef --------------------------------------------------------------*/ typedef struct nu_port_dev @@ -52,6 +66,7 @@ typedef struct nu_port_dev UDEV_T *pUDev; EP_INFO_T *apsEPInfo[NU_MAX_USBH_PIPE]; struct urequest asSetupReq[NU_MAX_USBH_PIPE]; + uint32_t u32SentLength[NU_MAX_USBH_PIPE]; struct rt_completion utr_completion; int port_num; rt_bool_t bEnumDone; @@ -91,6 +106,12 @@ GetRHPortControlFromPipe( { uinst_t inst; int port; + + if (!pipe || + !pipe->inst || + !pipe->inst->parent_hub) + return RT_NULL; + if (pipe->inst->parent_hub->is_roothub) { //case: device ---> root hub @@ -470,22 +491,30 @@ static int nu_int_xfer( int timeouts) { int ret; - int retry = 3; - while (retry > 0) + while (1) { ret = usbh_int_xfer(psUTR); - if (ret == 0) + if (ret < 0) + return ret; + + if (rt_completion_wait(&(psPortDev->utr_completion), timeouts) != 0) + { + RT_DEBUG_LOG(RT_DEBUG_USB, ("Request %08x Timeout in %d ms!!\n", psUTR, timeouts)); + usbh_quit_utr(psUTR); + + rt_completion_init(&(psPortDev->utr_completion)); + rt_thread_mdelay(1); + } + else + { + + RT_DEBUG_LOG(RT_DEBUG_USB, ("Transferring done %08x\n", psUTR)); + usbh_quit_utr(psUTR); break; - - RT_DEBUG_LOG(RT_DEBUG_USB, ("nu_int_xfer ERROR: failed to submit interrupt request\n")); - rt_thread_delay((pipe->ep.bInterval * RT_TICK_PER_SECOND / 1000) > 0 ? (pipe->ep.bInterval * RT_TICK_PER_SECOND / 1000) : 1); - retry --; + } } - if (ret < 0) - return ret; - return 0; } @@ -497,30 +526,6 @@ static void xfer_done_cb(UTR_T *psUTR) rt_completion_done(&(psPortDev->utr_completion)); } -static void int_xfer_done_cb(UTR_T *psUTR) -{ - upipe_t pipe = (upipe_t)psUTR->context; - - if (psUTR->status != 0) - { - RT_DEBUG_LOG(RT_DEBUG_USB, ("Interrupt xfer failed %d\n", psUTR->status)); - goto exit_int_xfer_done_cb; - } - - if (pipe->callback != RT_NULL) - { - struct uhost_msg msg; - msg.type = USB_MSG_CALLBACK; - msg.content.cb.function = pipe->callback; - msg.content.cb.context = pipe; - rt_usbh_event_signal(&s_sUSBHDev.uhcd, &msg); - } - -exit_int_xfer_done_cb: - - free_utr(psUTR); -} - static int nu_pipe_xfer(upipe_t pipe, rt_uint8_t token, void *buffer, int nbytes, int timeouts) { S_NU_RH_PORT_CTRL *psPortCtrl; @@ -565,6 +570,7 @@ static int nu_pipe_xfer(upipe_t pipe, rt_uint8_t token, void *buffer, int nbytes { struct urequest *psSetup = (struct urequest *)buffer_nonch; RT_ASSERT(buffer_nonch != RT_NULL); + psPortCtrl->asHubPortDev->u32SentLength[pipe->pipe_index] = 0; /* Read data from USB device. */ if (psSetup->request_type & USB_REQ_TYPE_DIR_IN) @@ -586,10 +592,35 @@ static int nu_pipe_xfer(upipe_t pipe, rt_uint8_t token, void *buffer, int nbytes //token == USBH_PID_DATA if (buffer_nonch && ((pipe->ep.bEndpointAddress & USB_DIR_MASK) == USB_DIR_IN)) { + struct urequest *psSetup = &psPortCtrl->asHubPortDev->asSetupReq[pipe->pipe_index]; + /* Read data from USB device. */ //Trigger USBHostLib Ctril_Xfer - ret = nu_ctrl_xfer(psPortDev, &psPortCtrl->asHubPortDev->asSetupReq[pipe->pipe_index], buffer_nonch, timeouts); - if (ret != nbytes) + /* + * Workaround: HCD driver can readback all bytes of setup.wLength, but not support single packet transferring. + */ + if (psPortCtrl->asHubPortDev->u32SentLength[pipe->pipe_index] == 0) + { + ret = nu_ctrl_xfer(psPortDev, psSetup, buffer_nonch, timeouts); + psPortCtrl->asHubPortDev->u32SentLength[pipe->pipe_index] = ret; + if (ret > 0) + { + rt_memcpy(buffer, buffer_nonch, ret); + } + } + else + { + if (psPortCtrl->asHubPortDev->u32SentLength[pipe->pipe_index] < nbytes) + { + ret = 0; + } + else + { + psPortCtrl->asHubPortDev->u32SentLength[pipe->pipe_index] -= nbytes; + ret = nbytes; + } + } + if (ret <= 0) goto exit_nu_pipe_xfer; } else @@ -599,7 +630,7 @@ static int nu_pipe_xfer(upipe_t pipe, rt_uint8_t token, void *buffer, int nbytes } //else i32XferLen = nbytes; - goto exit_nu_pipe_xfer; + goto exit_nu_pipe_xfer2; } // if ( pipe->ep.bmAttributes == USB_EP_ATTR_CONTROL ) else { @@ -634,9 +665,6 @@ static int nu_pipe_xfer(upipe_t pipe, rt_uint8_t token, void *buffer, int nbytes } else if (pipe->ep.bmAttributes == USB_EP_ATTR_INT) { - psUTR->func = int_xfer_done_cb; - psUTR->context = pipe; - if (nu_int_xfer(pipe, psPortDev, psUTR, timeouts) < 0) { RT_DEBUG_LOG(RT_DEBUG_USB, ("nu_pipe_xfer ERROR: int transfer failed\n")); @@ -646,7 +674,7 @@ static int nu_pipe_xfer(upipe_t pipe, rt_uint8_t token, void *buffer, int nbytes { i32XferLen = nbytes; } - goto exit2_nu_pipe_xfer; + goto exit_nu_pipe_xfer; } else if (pipe->ep.bmAttributes == USB_EP_ATTR_ISOC) { @@ -685,19 +713,17 @@ failreport_nu_pipe_xfer: i32XferLen = psUTR->xfer_len; +exit_nu_pipe_xfer: + //Call callback if (pipe->callback != RT_NULL) { pipe->callback(pipe); } -exit_nu_pipe_xfer: - if (psUTR) free_utr(psUTR); -exit2_nu_pipe_xfer: - #if defined(BSP_USING_MMU) if ((nbytes) && (buffer_nonch != buffer)) @@ -709,6 +735,8 @@ exit2_nu_pipe_xfer: } #endif +exit_nu_pipe_xfer2: + NU_USBHOST_UNLOCK(); return i32XferLen; @@ -951,6 +979,6 @@ int nu_usbh_register(void) return 0; } -INIT_DEVICE_EXPORT(nu_usbh_register); +INIT_APP_EXPORT(nu_usbh_register); #endif diff --git a/bsp/nuvoton/ma35-rtp/.config b/bsp/nuvoton/ma35-rtp/.config new file mode 100644 index 0000000000..24c4519665 --- /dev/null +++ b/bsp/nuvoton/ma35-rtp/.config @@ -0,0 +1,801 @@ +# +# Automatically generated file; DO NOT EDIT. +# RT-Thread Configuration +# +CONFIG_USE_MA35D1_SUBM=y + +# +# RT-Thread Kernel +# +CONFIG_RT_NAME_MAX=8 +# CONFIG_RT_USING_ARCH_DATA_TYPE is not set +# CONFIG_RT_USING_SMP is not set +CONFIG_RT_ALIGN_SIZE=4 +# CONFIG_RT_THREAD_PRIORITY_8 is not set +CONFIG_RT_THREAD_PRIORITY_32=y +# CONFIG_RT_THREAD_PRIORITY_256 is not set +CONFIG_RT_THREAD_PRIORITY_MAX=32 +CONFIG_RT_TICK_PER_SECOND=1000 +CONFIG_RT_USING_OVERFLOW_CHECK=y +CONFIG_RT_USING_HOOK=y +CONFIG_RT_HOOK_USING_FUNC_PTR=y +CONFIG_RT_USING_IDLE_HOOK=y +CONFIG_RT_IDLE_HOOK_LIST_SIZE=4 +CONFIG_IDLE_THREAD_STACK_SIZE=2048 +CONFIG_RT_USING_TIMER_SOFT=y +CONFIG_RT_TIMER_THREAD_PRIO=4 +CONFIG_RT_TIMER_THREAD_STACK_SIZE=2048 + +# +# kservice optimization +# +# CONFIG_RT_KSERVICE_USING_STDLIB is not set +# CONFIG_RT_KSERVICE_USING_TINY_SIZE is not set +# CONFIG_RT_USING_TINY_FFS is not set +# CONFIG_RT_KPRINTF_USING_LONGLONG is not set +CONFIG_RT_DEBUG=y +# CONFIG_RT_DEBUG_COLOR is not set +# CONFIG_RT_DEBUG_INIT_CONFIG is not set +# CONFIG_RT_DEBUG_THREAD_CONFIG is not set +# CONFIG_RT_DEBUG_SCHEDULER_CONFIG is not set +# CONFIG_RT_DEBUG_IPC_CONFIG is not set +# CONFIG_RT_DEBUG_TIMER_CONFIG is not set +# CONFIG_RT_DEBUG_IRQ_CONFIG is not set +# CONFIG_RT_DEBUG_MEM_CONFIG is not set +# CONFIG_RT_DEBUG_SLAB_CONFIG is not set +# CONFIG_RT_DEBUG_MEMHEAP_CONFIG is not set +# CONFIG_RT_DEBUG_MODULE_CONFIG is not set + +# +# Inter-Thread communication +# +CONFIG_RT_USING_SEMAPHORE=y +CONFIG_RT_USING_MUTEX=y +CONFIG_RT_USING_EVENT=y +CONFIG_RT_USING_MAILBOX=y +CONFIG_RT_USING_MESSAGEQUEUE=y +# CONFIG_RT_USING_SIGNALS is not set + +# +# Memory Management +# +CONFIG_RT_USING_MEMPOOL=y +CONFIG_RT_USING_SMALL_MEM=y +# CONFIG_RT_USING_SLAB is not set +# CONFIG_RT_USING_MEMHEAP is not set +CONFIG_RT_USING_SMALL_MEM_AS_HEAP=y +# CONFIG_RT_USING_MEMHEAP_AS_HEAP is not set +# CONFIG_RT_USING_SLAB_AS_HEAP is not set +# CONFIG_RT_USING_USERHEAP is not set +# CONFIG_RT_USING_NOHEAP is not set +# CONFIG_RT_USING_MEMTRACE is not set +# CONFIG_RT_USING_HEAP_ISR is not set +CONFIG_RT_USING_HEAP=y + +# +# Kernel Device Object +# +CONFIG_RT_USING_DEVICE=y +# CONFIG_RT_USING_DEVICE_OPS is not set +# CONFIG_RT_USING_INTERRUPT_INFO is not set +CONFIG_RT_USING_CONSOLE=y +CONFIG_RT_CONSOLEBUF_SIZE=256 +CONFIG_RT_CONSOLE_DEVICE_NAME="uart16" +CONFIG_RT_VER_NUM=0x50000 +CONFIG_ARCH_ARM=y +CONFIG_RT_USING_CPU_FFS=y +CONFIG_ARCH_ARM_CORTEX_M=y +CONFIG_ARCH_ARM_CORTEX_M4=y +# CONFIG_ARCH_CPU_STACK_GROWS_UPWARD is not set + +# +# RT-Thread Components +# +CONFIG_RT_USING_COMPONENTS_INIT=y +CONFIG_RT_USING_USER_MAIN=y +CONFIG_RT_MAIN_THREAD_STACK_SIZE=2048 +CONFIG_RT_MAIN_THREAD_PRIORITY=10 +# CONFIG_RT_USING_LEGACY is not set +CONFIG_RT_USING_MSH=y +CONFIG_RT_USING_FINSH=y +CONFIG_FINSH_USING_MSH=y +CONFIG_FINSH_THREAD_NAME="tshell" +CONFIG_FINSH_THREAD_PRIORITY=20 +CONFIG_FINSH_THREAD_STACK_SIZE=4096 +CONFIG_FINSH_USING_HISTORY=y +CONFIG_FINSH_HISTORY_LINES=5 +CONFIG_FINSH_USING_SYMTAB=y +CONFIG_FINSH_CMD_SIZE=80 +CONFIG_MSH_USING_BUILT_IN_COMMANDS=y +CONFIG_FINSH_USING_DESCRIPTION=y +# CONFIG_FINSH_ECHO_DISABLE_DEFAULT is not set +# CONFIG_FINSH_USING_AUTH is not set +CONFIG_FINSH_ARG_MAX=10 +# CONFIG_RT_USING_DFS is not set +# CONFIG_RT_USING_FAL is not set +# CONFIG_RT_USING_LWP is not set + +# +# Device Drivers +# +CONFIG_RT_USING_DEVICE_IPC=y +# CONFIG_RT_USING_SYSTEM_WORKQUEUE is not set +CONFIG_RT_USING_SERIAL=y +CONFIG_RT_USING_SERIAL_V1=y +# CONFIG_RT_USING_SERIAL_V2 is not set +# CONFIG_RT_SERIAL_USING_DMA is not set +CONFIG_RT_SERIAL_RB_BUFSZ=256 +# CONFIG_RT_USING_CAN is not set +# CONFIG_RT_USING_HWTIMER is not set +# CONFIG_RT_USING_CPUTIME is not set +# CONFIG_RT_USING_I2C is not set +# CONFIG_RT_USING_PHY is not set +CONFIG_RT_USING_PIN=y +# CONFIG_RT_USING_ADC is not set +# CONFIG_RT_USING_DAC is not set +# CONFIG_RT_USING_PWM is not set +# CONFIG_RT_USING_MTD_NOR is not set +# CONFIG_RT_USING_MTD_NAND is not set +# CONFIG_RT_USING_PM is not set +# CONFIG_RT_USING_RTC is not set +# CONFIG_RT_USING_SDIO is not set +# CONFIG_RT_USING_SPI is not set +# CONFIG_RT_USING_WDT is not set +# CONFIG_RT_USING_AUDIO is not set +# CONFIG_RT_USING_SENSOR is not set +# CONFIG_RT_USING_TOUCH is not set +# CONFIG_RT_USING_HWCRYPTO is not set +# CONFIG_RT_USING_PULSE_ENCODER is not set +# CONFIG_RT_USING_INPUT_CAPTURE is not set +# CONFIG_RT_USING_WIFI is not set + +# +# Using USB +# +# CONFIG_RT_USING_USB is not set +# CONFIG_RT_USING_USB_HOST is not set +# CONFIG_RT_USING_USB_DEVICE is not set + +# +# C/C++ and POSIX layer +# +CONFIG_RT_LIBC_DEFAULT_TIMEZONE=8 + +# +# POSIX (Portable Operating System Interface) layer +# +# CONFIG_RT_USING_POSIX_FS is not set +# CONFIG_RT_USING_POSIX_DELAY is not set +# CONFIG_RT_USING_POSIX_CLOCK is not set +# CONFIG_RT_USING_POSIX_TIMER is not set +# CONFIG_RT_USING_PTHREADS is not set +# CONFIG_RT_USING_MODULE is not set + +# +# Interprocess Communication (IPC) +# +# CONFIG_RT_USING_POSIX_PIPE is not set +# CONFIG_RT_USING_POSIX_MESSAGE_QUEUE is not set +# CONFIG_RT_USING_POSIX_MESSAGE_SEMAPHORE is not set + +# +# Socket is in the 'Network' category +# +# CONFIG_RT_USING_CPLUSPLUS is not set + +# +# Network +# +# CONFIG_RT_USING_SAL is not set +# CONFIG_RT_USING_NETDEV is not set +# CONFIG_RT_USING_LWIP is not set +# CONFIG_RT_USING_AT is not set + +# +# Utilities +# +# CONFIG_RT_USING_RYM is not set +CONFIG_RT_USING_ULOG=y +# CONFIG_ULOG_OUTPUT_LVL_A is not set +# CONFIG_ULOG_OUTPUT_LVL_E is not set +# CONFIG_ULOG_OUTPUT_LVL_W is not set +# CONFIG_ULOG_OUTPUT_LVL_I is not set +CONFIG_ULOG_OUTPUT_LVL_D=y +CONFIG_ULOG_OUTPUT_LVL=7 +CONFIG_ULOG_USING_ISR_LOG=y +CONFIG_ULOG_ASSERT_ENABLE=y +CONFIG_ULOG_LINE_BUF_SIZE=128 +# CONFIG_ULOG_USING_ASYNC_OUTPUT is not set + +# +# log format +# +# CONFIG_ULOG_OUTPUT_FLOAT is not set +CONFIG_ULOG_USING_COLOR=y +CONFIG_ULOG_OUTPUT_TIME=y +# CONFIG_ULOG_TIME_USING_TIMESTAMP is not set +CONFIG_ULOG_OUTPUT_LEVEL=y +CONFIG_ULOG_OUTPUT_TAG=y +# CONFIG_ULOG_OUTPUT_THREAD_NAME is not set +CONFIG_ULOG_BACKEND_USING_CONSOLE=y +# CONFIG_ULOG_BACKEND_USING_FILE is not set +# CONFIG_ULOG_USING_FILTER is not set +# CONFIG_ULOG_USING_SYSLOG is not set +CONFIG_RT_USING_UTEST=y +CONFIG_UTEST_THR_STACK_SIZE=4096 +CONFIG_UTEST_THR_PRIORITY=20 +# CONFIG_RT_USING_VAR_EXPORT is not set +# CONFIG_RT_USING_RT_LINK is not set +# CONFIG_RT_USING_VBUS is not set + +# +# RT-Thread Utestcases +# +CONFIG_RT_USING_UTESTCASES=y + +# +# Utest Self Testcase +# +CONFIG_UTEST_SELF_PASS_TC=y + +# +# Kernel Testcase +# +CONFIG_UTEST_SMALL_MEM_TC=y +# CONFIG_UTEST_IRQ_TC is not set +# CONFIG_UTEST_SEMAPHORE_TC is not set +# CONFIG_UTEST_EVENT_TC is not set +# CONFIG_UTEST_TIMER_TC is not set +# CONFIG_UTEST_MESSAGEQUEUE_TC is not set +# CONFIG_UTEST_SIGNAL_TC is not set +# CONFIG_UTEST_MUTEX_TC is not set +# CONFIG_UTEST_MAILBOX_TC is not set +# CONFIG_UTEST_THREAD_TC is not set + +# +# CPP11 Testcase +# +# CONFIG_UTEST_CPP11_THREAD_TC is not set + +# +# Utest Serial Testcase +# +# CONFIG_UTEST_SERIAL_TC is not set + +# +# RTT Posix Testcase +# +# CONFIG_RTT_POSIX_TESTCASE is not set + +# +# RT-Thread online packages +# + +# +# IoT - internet of things +# +# CONFIG_PKG_USING_LWIP is not set +# CONFIG_PKG_USING_LORAWAN_DRIVER is not set +# CONFIG_PKG_USING_PAHOMQTT is not set +# CONFIG_PKG_USING_UMQTT is not set +# CONFIG_PKG_USING_WEBCLIENT is not set +# CONFIG_PKG_USING_WEBNET is not set +# CONFIG_PKG_USING_MONGOOSE is not set +# CONFIG_PKG_USING_MYMQTT is not set +# CONFIG_PKG_USING_KAWAII_MQTT is not set +# CONFIG_PKG_USING_BC28_MQTT is not set +# CONFIG_PKG_USING_WEBTERMINAL is not set +# CONFIG_PKG_USING_LIBMODBUS is not set +# CONFIG_PKG_USING_FREEMODBUS is not set +# CONFIG_PKG_USING_NANOPB is not set + +# +# Wi-Fi +# + +# +# Marvell WiFi +# +# CONFIG_PKG_USING_WLANMARVELL is not set + +# +# Wiced WiFi +# +# CONFIG_PKG_USING_WLAN_WICED is not set +# CONFIG_PKG_USING_RW007 is not set +# CONFIG_PKG_USING_COAP is not set +# CONFIG_PKG_USING_NOPOLL is not set +# CONFIG_PKG_USING_NETUTILS is not set +# CONFIG_PKG_USING_CMUX is not set +# CONFIG_PKG_USING_PPP_DEVICE is not set +# CONFIG_PKG_USING_AT_DEVICE is not set +# CONFIG_PKG_USING_ATSRV_SOCKET is not set +# CONFIG_PKG_USING_WIZNET is not set +# CONFIG_PKG_USING_ZB_COORDINATOR is not set + +# +# IoT Cloud +# +# CONFIG_PKG_USING_ONENET is not set +# CONFIG_PKG_USING_GAGENT_CLOUD is not set +# CONFIG_PKG_USING_ALI_IOTKIT is not set +# CONFIG_PKG_USING_AZURE is not set +# CONFIG_PKG_USING_TENCENT_IOT_EXPLORER is not set +# CONFIG_PKG_USING_JIOT-C-SDK is not set +# CONFIG_PKG_USING_UCLOUD_IOT_SDK is not set +# CONFIG_PKG_USING_JOYLINK is not set +# CONFIG_PKG_USING_EZ_IOT_OS is not set +# CONFIG_PKG_USING_IOTSHARP_SDK is not set +# CONFIG_PKG_USING_NIMBLE is not set +# CONFIG_PKG_USING_LLSYNC_SDK_ADAPTER is not set +# CONFIG_PKG_USING_OTA_DOWNLOADER is not set +# CONFIG_PKG_USING_IPMSG is not set +# CONFIG_PKG_USING_LSSDP is not set +# CONFIG_PKG_USING_AIRKISS_OPEN is not set +# CONFIG_PKG_USING_LIBRWS is not set +# CONFIG_PKG_USING_TCPSERVER is not set +# CONFIG_PKG_USING_PROTOBUF_C is not set +# CONFIG_PKG_USING_DLT645 is not set +# CONFIG_PKG_USING_QXWZ is not set +# CONFIG_PKG_USING_SMTP_CLIENT is not set +# CONFIG_PKG_USING_ABUP_FOTA is not set +# CONFIG_PKG_USING_LIBCURL2RTT is not set +# CONFIG_PKG_USING_CAPNP is not set +# CONFIG_PKG_USING_AGILE_TELNET is not set +# CONFIG_PKG_USING_NMEALIB is not set +# CONFIG_PKG_USING_PDULIB is not set +# CONFIG_PKG_USING_BTSTACK is not set +# CONFIG_PKG_USING_LORAWAN_ED_STACK is not set +# CONFIG_PKG_USING_WAYZ_IOTKIT is not set +# CONFIG_PKG_USING_MAVLINK is not set +# CONFIG_PKG_USING_BSAL is not set +# CONFIG_PKG_USING_AGILE_MODBUS is not set +# CONFIG_PKG_USING_AGILE_FTP is not set +# CONFIG_PKG_USING_EMBEDDEDPROTO is not set +# CONFIG_PKG_USING_RT_LINK_HW is not set +# CONFIG_PKG_USING_LORA_PKT_FWD is not set +# CONFIG_PKG_USING_LORA_GW_DRIVER_LIB is not set +# CONFIG_PKG_USING_LORA_PKT_SNIFFER is not set +# CONFIG_PKG_USING_HM is not set +# CONFIG_PKG_USING_SMALL_MODBUS is not set +# CONFIG_PKG_USING_NET_SERVER is not set +# CONFIG_PKG_USING_ZFTP is not set + +# +# security packages +# +# CONFIG_PKG_USING_MBEDTLS is not set +# CONFIG_PKG_USING_LIBSODIUM is not set +# CONFIG_PKG_USING_LIBHYDROGEN is not set +# CONFIG_PKG_USING_TINYCRYPT is not set +# CONFIG_PKG_USING_TFM is not set +# CONFIG_PKG_USING_YD_CRYPTO is not set + +# +# language packages +# + +# +# JSON: JavaScript Object Notation, a lightweight data-interchange format +# +# CONFIG_PKG_USING_CJSON is not set +# CONFIG_PKG_USING_LJSON is not set +# CONFIG_PKG_USING_RT_CJSON_TOOLS is not set +# CONFIG_PKG_USING_RAPIDJSON is not set +# CONFIG_PKG_USING_JSMN is not set +# CONFIG_PKG_USING_AGILE_JSMN is not set +# CONFIG_PKG_USING_PARSON is not set + +# +# XML: Extensible Markup Language +# +# CONFIG_PKG_USING_SIMPLE_XML is not set +# CONFIG_PKG_USING_EZXML is not set +# CONFIG_PKG_USING_LUATOS_SOC is not set +# CONFIG_PKG_USING_LUA is not set +# CONFIG_PKG_USING_JERRYSCRIPT is not set +# CONFIG_PKG_USING_MICROPYTHON is not set +# CONFIG_PKG_USING_PIKASCRIPT is not set +# CONFIG_PKG_USING_RTT_RUST is not set + +# +# multimedia packages +# + +# +# LVGL: powerful and easy-to-use embedded GUI library +# +# CONFIG_PKG_USING_LVGL is not set +# CONFIG_PKG_USING_LITTLEVGL2RTT is not set +# CONFIG_PKG_USING_LV_MUSIC_DEMO is not set +# CONFIG_PKG_USING_GUI_GUIDER_DEMO is not set + +# +# u8g2: a monochrome graphic library +# +# CONFIG_PKG_USING_U8G2_OFFICIAL is not set +# CONFIG_PKG_USING_U8G2 is not set +# CONFIG_PKG_USING_OPENMV is not set +# CONFIG_PKG_USING_MUPDF is not set +# CONFIG_PKG_USING_STEMWIN is not set +# CONFIG_PKG_USING_WAVPLAYER is not set +# CONFIG_PKG_USING_TJPGD is not set +# CONFIG_PKG_USING_PDFGEN is not set +# CONFIG_PKG_USING_HELIX is not set +# CONFIG_PKG_USING_AZUREGUIX is not set +# CONFIG_PKG_USING_TOUCHGFX2RTT is not set +# CONFIG_PKG_USING_NUEMWIN is not set +# CONFIG_PKG_USING_MP3PLAYER is not set +# CONFIG_PKG_USING_TINYJPEG is not set +# CONFIG_PKG_USING_UGUI is not set + +# +# PainterEngine: A cross-platform graphics application framework written in C language +# +# CONFIG_PKG_USING_PAINTERENGINE is not set +# CONFIG_PKG_USING_PAINTERENGINE_AUX is not set +# CONFIG_PKG_USING_MCURSES is not set +# CONFIG_PKG_USING_TERMBOX is not set +# CONFIG_PKG_USING_VT100 is not set +# CONFIG_PKG_USING_QRCODE is not set +# CONFIG_PKG_USING_GUIENGINE is not set +# CONFIG_PKG_USING_PERSIMMON is not set + +# +# tools packages +# +# CONFIG_PKG_USING_CMBACKTRACE is not set +# CONFIG_PKG_USING_EASYFLASH is not set +# CONFIG_PKG_USING_EASYLOGGER is not set +# CONFIG_PKG_USING_SYSTEMVIEW is not set +# CONFIG_PKG_USING_SEGGER_RTT is not set +# CONFIG_PKG_USING_RDB is not set +# CONFIG_PKG_USING_ULOG_EASYFLASH is not set +# CONFIG_PKG_USING_ULOG_FILE is not set +# CONFIG_PKG_USING_LOGMGR is not set +# CONFIG_PKG_USING_ADBD is not set +# CONFIG_PKG_USING_COREMARK is not set +# CONFIG_PKG_USING_DHRYSTONE is not set +# CONFIG_PKG_USING_MEMORYPERF is not set +# CONFIG_PKG_USING_NR_MICRO_SHELL is not set +# CONFIG_PKG_USING_CHINESE_FONT_LIBRARY is not set +# CONFIG_PKG_USING_LUNAR_CALENDAR is not set +# CONFIG_PKG_USING_BS8116A is not set +# CONFIG_PKG_USING_GPS_RMC is not set +# CONFIG_PKG_USING_URLENCODE is not set +# CONFIG_PKG_USING_UMCN is not set +# CONFIG_PKG_USING_LWRB2RTT is not set +# CONFIG_PKG_USING_CPU_USAGE is not set +# CONFIG_PKG_USING_GBK2UTF8 is not set +# CONFIG_PKG_USING_VCONSOLE is not set +# CONFIG_PKG_USING_KDB is not set +# CONFIG_PKG_USING_WAMR is not set +# CONFIG_PKG_USING_MICRO_XRCE_DDS_CLIENT is not set +# CONFIG_PKG_USING_LWLOG is not set +# CONFIG_PKG_USING_ANV_TRACE is not set +# CONFIG_PKG_USING_ANV_MEMLEAK is not set +# CONFIG_PKG_USING_ANV_TESTSUIT is not set +# CONFIG_PKG_USING_ANV_BENCH is not set +# CONFIG_PKG_USING_DEVMEM is not set +# CONFIG_PKG_USING_REGEX is not set +# CONFIG_PKG_USING_MEM_SANDBOX is not set +# CONFIG_PKG_USING_SOLAR_TERMS is not set +# CONFIG_PKG_USING_GAN_ZHI is not set +# CONFIG_PKG_USING_FDT is not set +# CONFIG_PKG_USING_CBOX is not set +# CONFIG_PKG_USING_SNOWFLAKE is not set +# CONFIG_PKG_USING_HASH_MATCH is not set +# CONFIG_PKG_USING_FIRE_PID_CURVE is not set +# CONFIG_PKG_USING_ARMV7M_DWT_TOOL is not set + +# +# system packages +# + +# +# enhanced kernel services +# +# CONFIG_PKG_USING_RT_MEMCPY_CM is not set +# CONFIG_PKG_USING_RT_KPRINTF_THREADSAFE is not set +# CONFIG_PKG_USING_RT_VSNPRINTF_FULL is not set + +# +# acceleration: Assembly language or algorithmic acceleration packages +# +# CONFIG_PKG_USING_QFPLIB_M0_FULL is not set +# CONFIG_PKG_USING_QFPLIB_M0_TINY is not set +# CONFIG_PKG_USING_QFPLIB_M3 is not set + +# +# CMSIS: ARM Cortex-M Microcontroller Software Interface Standard +# +# CONFIG_PKG_USING_CMSIS_5 is not set +# CONFIG_PKG_USING_CMSIS_RTOS1 is not set +# CONFIG_PKG_USING_CMSIS_RTOS2 is not set + +# +# Micrium: Micrium software products porting for RT-Thread +# +# CONFIG_PKG_USING_UCOSIII_WRAPPER is not set +# CONFIG_PKG_USING_UCOSII_WRAPPER is not set +# CONFIG_PKG_USING_UC_CRC is not set +# CONFIG_PKG_USING_UC_CLK is not set +# CONFIG_PKG_USING_UC_COMMON is not set +# CONFIG_PKG_USING_UC_MODBUS is not set +# CONFIG_PKG_USING_RTDUINO is not set +# CONFIG_PKG_USING_FREERTOS_WRAPPER is not set +# CONFIG_PKG_USING_CAIRO is not set +# CONFIG_PKG_USING_PIXMAN is not set +# CONFIG_PKG_USING_PARTITION is not set +# CONFIG_PKG_USING_PERF_COUNTER is not set +# CONFIG_PKG_USING_FLASHDB is not set +# CONFIG_PKG_USING_SQLITE is not set +# CONFIG_PKG_USING_RTI is not set +# CONFIG_PKG_USING_DFS_YAFFS is not set +# CONFIG_PKG_USING_LITTLEFS is not set +# CONFIG_PKG_USING_DFS_JFFS2 is not set +# CONFIG_PKG_USING_DFS_UFFS is not set +# CONFIG_PKG_USING_LWEXT4 is not set +# CONFIG_PKG_USING_THREAD_POOL is not set +# CONFIG_PKG_USING_ROBOTS is not set +# CONFIG_PKG_USING_EV is not set +# CONFIG_PKG_USING_SYSWATCH is not set +# CONFIG_PKG_USING_SYS_LOAD_MONITOR is not set +# CONFIG_PKG_USING_PLCCORE is not set +# CONFIG_PKG_USING_RAMDISK is not set +# CONFIG_PKG_USING_MININI is not set +# CONFIG_PKG_USING_QBOOT is not set +# CONFIG_PKG_USING_PPOOL is not set +# CONFIG_PKG_USING_OPENAMP is not set +# CONFIG_PKG_USING_LPM is not set +# CONFIG_PKG_USING_TLSF is not set +# CONFIG_PKG_USING_EVENT_RECORDER is not set +# CONFIG_PKG_USING_ARM_2D is not set +# CONFIG_PKG_USING_MCUBOOT is not set +# CONFIG_PKG_USING_TINYUSB is not set +# CONFIG_PKG_USING_CHERRYUSB is not set +# CONFIG_PKG_USING_KMULTI_RTIMER is not set +# CONFIG_PKG_USING_TFDB is not set +# CONFIG_PKG_USING_QPC is not set + +# +# peripheral libraries and drivers +# +# CONFIG_PKG_USING_SENSORS_DRIVERS is not set +# CONFIG_PKG_USING_REALTEK_AMEBA is not set +# CONFIG_PKG_USING_SHT2X is not set +# CONFIG_PKG_USING_SHT3X is not set +# CONFIG_PKG_USING_ADT74XX is not set +# CONFIG_PKG_USING_AS7341 is not set +# CONFIG_PKG_USING_STM32_SDIO is not set +# CONFIG_PKG_USING_ESP_IDF is not set +# CONFIG_PKG_USING_ICM20608 is not set +# CONFIG_PKG_USING_BUTTON is not set +# CONFIG_PKG_USING_PCF8574 is not set +# CONFIG_PKG_USING_SX12XX is not set +# CONFIG_PKG_USING_SIGNAL_LED is not set +# CONFIG_PKG_USING_LEDBLINK is not set +# CONFIG_PKG_USING_LITTLED is not set +# CONFIG_PKG_USING_LKDGUI is not set +# CONFIG_PKG_USING_NRF5X_SDK is not set +# CONFIG_PKG_USING_NRFX is not set +# CONFIG_PKG_USING_WM_LIBRARIES is not set + +# +# Kendryte SDK +# +# CONFIG_PKG_USING_K210_SDK is not set +# CONFIG_PKG_USING_KENDRYTE_SDK is not set +# CONFIG_PKG_USING_INFRARED is not set +# CONFIG_PKG_USING_MULTI_INFRARED is not set +# CONFIG_PKG_USING_AGILE_BUTTON is not set +# CONFIG_PKG_USING_AGILE_LED is not set +# CONFIG_PKG_USING_AT24CXX is not set +# CONFIG_PKG_USING_MOTIONDRIVER2RTT is not set +# CONFIG_PKG_USING_AD7746 is not set +# CONFIG_PKG_USING_PCA9685 is not set +# CONFIG_PKG_USING_I2C_TOOLS is not set +# CONFIG_PKG_USING_NRF24L01 is not set +# CONFIG_PKG_USING_TOUCH_DRIVERS is not set +# CONFIG_PKG_USING_MAX17048 is not set +# CONFIG_PKG_USING_RPLIDAR is not set +# CONFIG_PKG_USING_AS608 is not set +# CONFIG_PKG_USING_RC522 is not set +# CONFIG_PKG_USING_WS2812B is not set +# CONFIG_PKG_USING_EMBARC_BSP is not set +# CONFIG_PKG_USING_EXTERN_RTC_DRIVERS is not set +# CONFIG_PKG_USING_MULTI_RTIMER is not set +# CONFIG_PKG_USING_MAX7219 is not set +# CONFIG_PKG_USING_BEEP is not set +# CONFIG_PKG_USING_EASYBLINK is not set +# CONFIG_PKG_USING_PMS_SERIES is not set +# CONFIG_PKG_USING_CAN_YMODEM is not set +# CONFIG_PKG_USING_LORA_RADIO_DRIVER is not set +# CONFIG_PKG_USING_QLED is not set +# CONFIG_PKG_USING_PAJ7620 is not set +# CONFIG_PKG_USING_AGILE_CONSOLE is not set +# CONFIG_PKG_USING_LD3320 is not set +# CONFIG_PKG_USING_WK2124 is not set +# CONFIG_PKG_USING_LY68L6400 is not set +# CONFIG_PKG_USING_DM9051 is not set +# CONFIG_PKG_USING_SSD1306 is not set +# CONFIG_PKG_USING_QKEY is not set +# CONFIG_PKG_USING_RS485 is not set +# CONFIG_PKG_USING_RS232 is not set +# CONFIG_PKG_USING_NES is not set +# CONFIG_PKG_USING_VIRTUAL_SENSOR is not set +# CONFIG_PKG_USING_VDEVICE is not set +# CONFIG_PKG_USING_SGM706 is not set +# CONFIG_PKG_USING_STM32WB55_SDK is not set +# CONFIG_PKG_USING_RDA58XX is not set +# CONFIG_PKG_USING_LIBNFC is not set +# CONFIG_PKG_USING_MFOC is not set +# CONFIG_PKG_USING_TMC51XX is not set +# CONFIG_PKG_USING_TCA9534 is not set +# CONFIG_PKG_USING_KOBUKI is not set +# CONFIG_PKG_USING_ROSSERIAL is not set +# CONFIG_PKG_USING_MICRO_ROS is not set +# CONFIG_PKG_USING_MCP23008 is not set +# CONFIG_PKG_USING_BLUETRUM_SDK is not set +# CONFIG_PKG_USING_MISAKA_AT24CXX is not set +# CONFIG_PKG_USING_MISAKA_RGB_BLING is not set +# CONFIG_PKG_USING_LORA_MODEM_DRIVER is not set +# CONFIG_PKG_USING_BL_MCU_SDK is not set +# CONFIG_PKG_USING_SOFT_SERIAL is not set +# CONFIG_PKG_USING_MB85RS16 is not set +# CONFIG_PKG_USING_CW2015 is not set +# CONFIG_PKG_USING_RFM300 is not set +# CONFIG_PKG_USING_IO_INPUT_FILTER is not set +# CONFIG_PKG_USING_RASPBERRYPI_PICO_SDK is not set + +# +# AI packages +# +# CONFIG_PKG_USING_LIBANN is not set +# CONFIG_PKG_USING_NNOM is not set +# CONFIG_PKG_USING_ONNX_BACKEND is not set +# CONFIG_PKG_USING_ONNX_PARSER is not set +# CONFIG_PKG_USING_TENSORFLOWLITEMICRO is not set +# CONFIG_PKG_USING_ELAPACK is not set +# CONFIG_PKG_USING_ULAPACK is not set +# CONFIG_PKG_USING_QUEST is not set +# CONFIG_PKG_USING_NAXOS is not set + +# +# miscellaneous packages +# + +# +# project laboratory +# + +# +# samples: kernel and components samples +# +# CONFIG_PKG_USING_KERNEL_SAMPLES is not set +# CONFIG_PKG_USING_FILESYSTEM_SAMPLES is not set +# CONFIG_PKG_USING_NETWORK_SAMPLES is not set +# CONFIG_PKG_USING_PERIPHERAL_SAMPLES is not set + +# +# entertainment: terminal games and other interesting software packages +# +# CONFIG_PKG_USING_CMATRIX is not set +# CONFIG_PKG_USING_SL is not set +# CONFIG_PKG_USING_CAL is not set +# CONFIG_PKG_USING_ACLOCK is not set +# CONFIG_PKG_USING_THREES is not set +# CONFIG_PKG_USING_2048 is not set +# CONFIG_PKG_USING_SNAKE is not set +# CONFIG_PKG_USING_TETRIS is not set +# CONFIG_PKG_USING_DONUT is not set +# CONFIG_PKG_USING_COWSAY is not set +# CONFIG_PKG_USING_LIBCSV is not set +# CONFIG_PKG_USING_OPTPARSE is not set +# CONFIG_PKG_USING_FASTLZ is not set +# CONFIG_PKG_USING_MINILZO is not set +# CONFIG_PKG_USING_QUICKLZ is not set +# CONFIG_PKG_USING_LZMA is not set +# CONFIG_PKG_USING_MULTIBUTTON is not set +# CONFIG_PKG_USING_FLEXIBLE_BUTTON is not set +# CONFIG_PKG_USING_CANFESTIVAL is not set +# CONFIG_PKG_USING_ZLIB is not set +# CONFIG_PKG_USING_MINIZIP is not set +# CONFIG_PKG_USING_HEATSHRINK is not set +# CONFIG_PKG_USING_DSTR is not set +# CONFIG_PKG_USING_TINYFRAME is not set +# CONFIG_PKG_USING_KENDRYTE_DEMO is not set +# CONFIG_PKG_USING_DIGITALCTRL is not set +# CONFIG_PKG_USING_UPACKER is not set +# CONFIG_PKG_USING_UPARAM is not set +# CONFIG_PKG_USING_HELLO is not set +# CONFIG_PKG_USING_VI is not set +# CONFIG_PKG_USING_KI is not set +# CONFIG_PKG_USING_ARMv7M_DWT is not set +# CONFIG_PKG_USING_UKAL is not set +# CONFIG_PKG_USING_CRCLIB is not set +# CONFIG_PKG_USING_LWGPS is not set +# CONFIG_PKG_USING_STATE_MACHINE is not set +# CONFIG_PKG_USING_DESIGN_PATTERN is not set +# CONFIG_PKG_USING_CONTROLLER is not set +# CONFIG_PKG_USING_PHASE_LOCKED_LOOP is not set +# CONFIG_PKG_USING_MFBD is not set +# CONFIG_PKG_USING_SLCAN2RTT is not set +# CONFIG_PKG_USING_SOEM is not set + +# +# Hardware Drivers Config +# + +# +# On-chip Peripheral Drivers +# +CONFIG_SOC_SERIES_MA35D1=y +# CONFIG_BSP_USE_STDDRIVER_SOURCE is not set +CONFIG_BSP_USING_PDMA=y +CONFIG_BSP_USING_PDMA2=y +CONFIG_BSP_USING_PDMA3=y +CONFIG_NU_PDMA_MEMFUN_ACTOR_MAX=2 +CONFIG_BSP_USING_GPIO=y +# CONFIG_BSP_USING_RTC is not set +# CONFIG_BSP_USING_EADC is not set +# CONFIG_BSP_USING_TMR is not set +CONFIG_BSP_USING_UART=y +# CONFIG_BSP_USING_UART1 is not set +# CONFIG_BSP_USING_UART2 is not set +# CONFIG_BSP_USING_UART3 is not set +# CONFIG_BSP_USING_UART4 is not set +# CONFIG_BSP_USING_UART5 is not set +# CONFIG_BSP_USING_UART6 is not set +# CONFIG_BSP_USING_UART7 is not set +# CONFIG_BSP_USING_UART8 is not set +# CONFIG_BSP_USING_UART9 is not set +# CONFIG_BSP_USING_UART10 is not set +# CONFIG_BSP_USING_UART11 is not set +# CONFIG_BSP_USING_UART12 is not set +# CONFIG_BSP_USING_UART13 is not set +# CONFIG_BSP_USING_UART14 is not set +# CONFIG_BSP_USING_UART15 is not set +CONFIG_BSP_USING_UART16=y +# CONFIG_BSP_USING_I2C is not set +# CONFIG_BSP_USING_CANFD is not set +# CONFIG_BSP_USING_EPWM is not set +# CONFIG_BSP_USING_SPI is not set +# CONFIG_BSP_USING_I2S is not set +# CONFIG_BSP_USING_QSPI is not set +# CONFIG_BSP_USING_SCUART is not set +# CONFIG_BSP_USING_ECAP is not set +# CONFIG_BSP_USING_QEI is not set +# CONFIG_BSP_USING_SOFT_I2C is not set +# CONFIG_BSP_USING_WDT is not set +# CONFIG_BSP_USING_EBI is not set + +# +# On-board Peripheral Drivers +# +CONFIG_BSP_USING_NULINKME=y + +# +# Board extended module drivers +# + +# +# Nuvoton Packages Config +# +CONFIG_NU_PKG_USING_UTILS=y +# CONFIG_NU_PKG_USING_DEMO is not set +# CONFIG_NU_PKG_USING_LVGL is not set +# CONFIG_NU_PKG_USING_BMX055 is not set +# CONFIG_NU_PKG_USING_MAX31875 is not set +# CONFIG_NU_PKG_USING_NCT7717U is not set +# CONFIG_NU_PKG_USING_NAU88L25 is not set +# CONFIG_NU_PKG_USING_NAU8822 is not set +# CONFIG_NU_PKG_USING_DA9062 is not set +# CONFIG_NU_PKG_USING_ILI9341 is not set +# CONFIG_NU_PKG_USING_SSD1963 is not set +# CONFIG_NU_PKG_USING_FSA506 is not set +# CONFIG_NU_PKG_USING_TPC is not set +# CONFIG_NU_PKG_USING_ADC_TOUCH is not set +# CONFIG_NU_PKG_USING_SPINAND is not set +CONFIG_UTEST_CMD_PREFIX="bsp.nuvoton.utest." +CONFIG_BOARD_USE_UTEST=y diff --git a/bsp/nuvoton/ma35-rtp/Kconfig b/bsp/nuvoton/ma35-rtp/Kconfig new file mode 100644 index 0000000000..03dd8ae611 --- /dev/null +++ b/bsp/nuvoton/ma35-rtp/Kconfig @@ -0,0 +1,27 @@ +mainmenu "RT-Thread Configuration" + +config BSP_DIR + string + option env="BSP_ROOT" + default "." + +config RTT_DIR + string + option env="RTT_ROOT" + default "../../.." + +# you can change the RTT_ROOT default "../../.." to your rtthread_root, +# example : default "F:/git_repositories/rt-thread" + +config PKGS_DIR + string + option env="PKGS_ROOT" + default "packages" + +config USE_MA35D1_SUBM + bool + default y + +source "$RTT_DIR/Kconfig" +source "$PKGS_DIR/Kconfig" +source "$BSP_DIR/board/Kconfig" diff --git a/bsp/nuvoton/ma35-rtp/Nu_Link_Driver.ini b/bsp/nuvoton/ma35-rtp/Nu_Link_Driver.ini new file mode 100644 index 0000000000..d089a0fa2a --- /dev/null +++ b/bsp/nuvoton/ma35-rtp/Nu_Link_Driver.ini @@ -0,0 +1,1144 @@ +[Version] +Nu_LinkVersion=V5.20 +[Process] +ProcessID=0x00005940 +ProcessCreationTime_L=0x2e4bfd5d +ProcessCreationTime_H=0x01d8d183 +NuLinkID=0x7788538f +DisableFirmwareUpdate=0 +NuLinkIDs_Count=0x00000001 +NuLinkID0=0x7788538f +[ChipSelect] +;ChipName= +ChipName=M481 +[NUC505] +Connect=0 +Reset=Autodetect +MaxClock=1MHz +MemoryVerify=0 +IOVoltage=3300 +Erase=1 +Program=1 +Verify=1 +ResetAndRun=0 +EnableFlashBreakpoint=0 +EnableLog=0 +MemAccessWhileRun=0 +RAMForAlgorithmStart=0x20000000 +RAMForAlgorithmSize=0x4000 +ProgramAlgorithm=NUC505_SPIFLASH.FLM +[NUC4xx] +Connect=0 +Reset=Autodetect +MaxClock=1MHz +MemoryVerify=0 +IOVoltage=3300 +FlashSelect=APROM +Erase=1 +Program=1 +Verify=1 +ResetAndRun=0 +EnableFlashBreakpoint=1 +EnableLog=0 +MemAccessWhileRun=0 +RAMForAlgorithmStart=0x20000000 +RAMForAlgorithmSize=0x4000 +ProgramAlgorithm=NUC400_AP_512.FLM +TraceConf0=0x00000002 +TraceConf1=0x014fb180 +TraceConf2=0x00000800 +TraceConf3=0x00000000 +TraceConf4=0x00000001 +TraceConf5=0x00000000 +[NUC2xx] +Connect=0 +Reset=Autodetect +MaxClock=1MHz +MemoryVerify=0 +IOVoltage=3300 +FlashSelect=APROM +Erase=1 +Program=1 +Verify=1 +ResetAndRun=0 +EnableFlashBreakpoint=1 +EnableLog=0 +MemAccessWhileRun=0 +RAMForAlgorithmStart=0x20000000 +RAMForAlgorithmSize=0x1000 +ProgramAlgorithm=NUC200_AP_128.FLM +[NUC1311] +Connect=0 +Reset=Autodetect +MaxClock=1MHz +MemoryVerify=0 +IOVoltage=3300 +FlashSelect=APROM +Erase=1 +Program=1 +Verify=1 +ResetAndRun=0 +EnableFlashBreakpoint=1 +EnableLog=0 +MemAccessWhileRun=0 +RAMForAlgorithmStart=0x20000000 +RAMForAlgorithmSize=0x1000 +ProgramAlgorithm=NUC1311_AP_64.FLM +[NUC126] +Connect=0 +Reset=Autodetect +MaxClock=1MHz +MemoryVerify=0 +IOVoltage=3300 +FlashSelect=APROM +Erase=1 +Program=1 +Verify=1 +ResetAndRun=0 +EnableFlashBreakpoint=1 +EnableLog=0 +MemAccessWhileRun=0 +RAMForAlgorithmStart=0x20000000 +RAMForAlgorithmSize=0x2000 +ProgramAlgorithm=NUC126_AP_256.FLM +[NUC121] +Connect=0 +Reset=Autodetect +MaxClock=1MHz +MemoryVerify=0 +IOVoltage=3300 +FlashSelect=APROM +Erase=1 +Program=1 +Verify=1 +ResetAndRun=0 +EnableFlashBreakpoint=1 +EnableLog=0 +MemAccessWhileRun=0 +RAMForAlgorithmStart=0x20000000 +RAMForAlgorithmSize=0x1000 +ProgramAlgorithm=NUC121_AP_32.FLM +[NUC1xx] +Connect=0 +Reset=Autodetect +MaxClock=1MHz +MemoryVerify=0 +IOVoltage=3300 +FlashSelect=APROM +Erase=1 +Program=1 +Verify=1 +ResetAndRun=0 +EnableFlashBreakpoint=1 +EnableLog=0 +MemAccessWhileRun=0 +RAMForAlgorithmStart=0x20000000 +RAMForAlgorithmSize=0x1000 +ProgramAlgorithm=NUC100_AP_128.FLM +[NUC029] +Connect=0 +Reset=Autodetect +MaxClock=1MHz +MemoryVerify=0 +IOVoltage=3300 +FlashSelect=APROM +Erase=1 +Program=1 +Verify=1 +ResetAndRun=0 +EnableFlashBreakpoint=1 +EnableLog=0 +MemAccessWhileRun=0 +RAMForAlgorithmStart=0x20000000 +RAMForAlgorithmSize=0x800 +ProgramAlgorithm=NUC029_AP_16.FLM +[NM1820] +Connect=0 +Reset=Autodetect +MaxClock=1MHz +MemoryVerify=0 +IOVoltage=3300 +FlashSelect=APROM +Erase=1 +Program=1 +Verify=1 +ResetAndRun=0 +EnableFlashBreakpoint=1 +EnableLog=0 +MemAccessWhileRun=0 +RAMForAlgorithmStart=0x20000000 +RAMForAlgorithmSize=0x800 +ProgramAlgorithm=NM1820_AP_17_5.FLM +[NM1810] +Connect=0 +Reset=Autodetect +MaxClock=1MHz +MemoryVerify=0 +IOVoltage=3300 +FlashSelect=APROM +Erase=1 +Program=1 +Verify=1 +ResetAndRun=0 +EnableFlashBreakpoint=1 +EnableLog=0 +MemAccessWhileRun=0 +RAMForAlgorithmStart=0x20000000 +RAMForAlgorithmSize=0x800 +ProgramAlgorithm=NM1810_AP_29_5.FLM +[NM1500] +Connect=0 +Reset=Autodetect +MaxClock=1MHz +MemoryVerify=0 +IOVoltage=3300 +FlashSelect=APROM +Erase=1 +Program=1 +Verify=1 +ResetAndRun=0 +EnableFlashBreakpoint=1 +EnableLog=0 +MemAccessWhileRun=0 +RAMForAlgorithmStart=0x20000000 +RAMForAlgorithmSize=0x1000 +ProgramAlgorithm=NM1500_AP_128.FLM +[NM1330] +Connect=0 +Reset=Autodetect +MaxClock=1MHz +MemoryVerify=0 +IOVoltage=3300 +FlashSelect=APROM +Erase=1 +Program=1 +Verify=1 +ResetAndRun=0 +EnableFlashBreakpoint=1 +EnableLog=0 +MemAccessWhileRun=0 +RAMForAlgorithmStart=0x20000000 +RAMForAlgorithmSize=0x1000 +ProgramAlgorithm=NM1330_AP_64.FLM +[NM1320] +Connect=0 +Reset=Autodetect +MaxClock=1MHz +MemoryVerify=0 +IOVoltage=3300 +FlashSelect=APROM +Erase=1 +Program=1 +Verify=1 +ResetAndRun=0 +EnableFlashBreakpoint=1 +EnableLog=0 +MemAccessWhileRun=0 +RAMForAlgorithmStart=0x20000000 +RAMForAlgorithmSize=0x1000 +ProgramAlgorithm=NM1320_AP_32.FLM +[NM1240] +Connect=0 +Reset=Autodetect +MaxClock=1MHz +MemoryVerify=0 +IOVoltage=3300 +FlashSelect=APROM +Erase=1 +Program=1 +Verify=1 +ResetAndRun=0 +EnableFlashBreakpoint=1 +EnableLog=0 +MemAccessWhileRun=0 +RAMForAlgorithmStart=0x20000000 +RAMForAlgorithmSize=0x1000 +ProgramAlgorithm=NM1240_AP_64.FLM +[NM1230] +Connect=0 +Reset=Autodetect +MaxClock=1MHz +MemoryVerify=0 +IOVoltage=3300 +FlashSelect=APROM +Erase=1 +Program=1 +Verify=1 +ResetAndRun=0 +EnableFlashBreakpoint=1 +EnableLog=0 +MemAccessWhileRun=0 +RAMForAlgorithmStart=0x20000000 +RAMForAlgorithmSize=0x1000 +ProgramAlgorithm=NM1230_AP_64.FLM +[NM1200] +Connect=0 +Reset=Autodetect +MaxClock=1MHz +MemoryVerify=0 +IOVoltage=3300 +FlashSelect=APROM +Erase=1 +Program=1 +Verify=1 +ResetAndRun=0 +EnableFlashBreakpoint=1 +EnableLog=0 +MemAccessWhileRun=0 +RAMForAlgorithmStart=0x20000000 +RAMForAlgorithmSize=0x800 +ProgramAlgorithm=NM1200_AP_8.FLM +[NM1120] +Connect=0 +Reset=Autodetect +MaxClock=1MHz +MemoryVerify=0 +IOVoltage=3300 +FlashSelect=APROM +Erase=1 +Program=1 +Verify=1 +ResetAndRun=0 +EnableFlashBreakpoint=1 +EnableLog=0 +MemAccessWhileRun=0 +RAMForAlgorithmStart=0x20000000 +RAMForAlgorithmSize=0x800 +ProgramAlgorithm=NM1120_AP_29_5.FLM +[N32F030] +Connect=0 +Reset=Autodetect +MaxClock=1MHz +MemoryVerify=0 +IOVoltage=3300 +FlashSelect=APROM +Erase=1 +Program=1 +Verify=1 +ResetAndRun=0 +EnableFlashBreakpoint=1 +EnableLog=0 +MemAccessWhileRun=0 +RAMForAlgorithmStart=0x20000000 +RAMForAlgorithmSize=0x1000 +ProgramAlgorithm=N32F030_AP_64.FLM +[TF5100] +Connect=0 +Reset=Autodetect +MaxClock=1MHz +MemoryVerify=0 +IOVoltage=3300 +FlashSelect=APROM +Erase=1 +Program=1 +Verify=1 +ResetAndRun=0 +EnableFlashBreakpoint=1 +EnableLog=0 +MemAccessWhileRun=0 +RAMForAlgorithmStart=0x20000000 +RAMForAlgorithmSize=0x1000 +ProgramAlgorithm=TF5100_AP_64.FLM +[NDA102] +Connect=0 +Reset=Autodetect +MaxClock=1MHz +MemoryVerify=0 +IOVoltage=3300 +FlashSelect=APROM +Erase=1 +Program=1 +Verify=1 +ResetAndRun=0 +EnableFlashBreakpoint=1 +EnableLog=0 +MemAccessWhileRun=0 +RAMForAlgorithmStart=0x20000000 +RAMForAlgorithmSize=0x800 +ProgramAlgorithm=NDA102_AP_29_5.FLM +[Nano103] +Connect=0 +Reset=Autodetect +MaxClock=1MHz +MemoryVerify=0 +IOVoltage=3300 +FlashSelect=APROM +Erase=1 +Program=1 +Verify=1 +ResetAndRun=0 +EnableFlashBreakpoint=1 +EnableLog=0 +MemAccessWhileRun=0 +RAMForAlgorithmStart=0x20000000 +RAMForAlgorithmSize=0x1000 +ProgramAlgorithm=Nano103_AP_64.FLM +[Nano100] +Connect=0 +Reset=Autodetect +MaxClock=1MHz +MemoryVerify=0 +IOVoltage=3300 +FlashSelect=APROM +Erase=1 +Program=1 +Verify=1 +ResetAndRun=0 +EnableFlashBreakpoint=1 +EnableLog=0 +MemAccessWhileRun=0 +RAMForAlgorithmStart=0x20000000 +RAMForAlgorithmSize=0x1000 +ProgramAlgorithm=Nano100_AP_64.FLM +[N576] +Connect=0 +Reset=Autodetect +MaxClock=1MHz +MemoryVerify=0 +IOVoltage=3300 +FlashSelect=APROM +Erase=1 +Program=1 +Verify=1 +ResetAndRun=0 +EnableFlashBreakpoint=0 +EnableLog=0 +MemAccessWhileRun=0 +RAMForAlgorithmStart=0x20000000 +RAMForAlgorithmSize=0x1000 +ProgramAlgorithm=N576_AP_145.FLM +[N575] +Connect=0 +Reset=Autodetect +MaxClock=1MHz +MemoryVerify=0 +IOVoltage=3300 +FlashSelect=APROM +Erase=1 +Program=1 +Verify=1 +ResetAndRun=0 +EnableFlashBreakpoint=0 +EnableLog=0 +MemAccessWhileRun=0 +RAMForAlgorithmStart=0x20000000 +RAMForAlgorithmSize=0x1000 +ProgramAlgorithm=N575_AP_145.FLM +[N574] +Connect=0 +Reset=Autodetect +MaxClock=1MHz +MemoryVerify=0 +IOVoltage=3300 +FlashSelect=APROM +Erase=1 +Program=1 +Verify=1 +ResetAndRun=0 +EnableFlashBreakpoint=0 +EnableLog=0 +MemAccessWhileRun=0 +RAMForAlgorithmStart=0x20000000 +RAMForAlgorithmSize=0x1000 +ProgramAlgorithm=N574_AP_512.FLM +[N572] +Connect=0 +Reset=Autodetect +MaxClock=1MHz +MemoryVerify=0 +IOVoltage=3300 +Erase=1 +Program=1 +Verify=1 +ResetAndRun=0 +EnableFlashBreakpoint=1 +EnableLog=0 +MemAccessWhileRun=0 +RAMForAlgorithmStart=0x20000000 +RAMForAlgorithmSize=0x2000 +ProgramAlgorithm=N572Fxxx.FLM +[N571] +Connect=0 +Reset=Autodetect +MaxClock=1MHz +MemoryVerify=0 +IOVoltage=3300 +Erase=1 +Program=1 +Verify=1 +ResetAndRun=0 +EnableFlashBreakpoint=1 +EnableLog=0 +MemAccessWhileRun=0 +RAMForAlgorithmStart=0x20000000 +RAMForAlgorithmSize=0x2000 +ProgramAlgorithm=N571E000.FLM +[N570] +Connect=0 +Reset=Autodetect +MaxClock=1MHz +MemoryVerify=0 +IOVoltage=3300 +FlashSelect=APROM +Erase=1 +Program=1 +Verify=1 +ResetAndRun=0 +EnableFlashBreakpoint=0 +EnableLog=0 +MemAccessWhileRun=0 +RAMForAlgorithmStart=0x20000000 +RAMForAlgorithmSize=0x1000 +ProgramAlgorithm=N570_AP_64.FLM +[N569] +Connect=0 +Reset=Autodetect +MaxClock=1MHz +MemoryVerify=0 +IOVoltage=3300 +FlashSelect=APROM +Erase=1 +Program=1 +Verify=1 +ResetAndRun=0 +EnableFlashBreakpoint=0 +EnableLog=0 +MemAccessWhileRun=0 +RAMForAlgorithmStart=0x20000000 +RAMForAlgorithmSize=0x1000 +ProgramAlgorithm=N569_AP_64.FLM +[N512] +Connect=0 +Reset=Autodetect +MaxClock=1MHz +MemoryVerify=0 +IOVoltage=3300 +FlashSelect=APROM +Erase=1 +Program=1 +Verify=1 +ResetAndRun=0 +EnableFlashBreakpoint=1 +EnableLog=0 +MemAccessWhileRun=0 +RAMForAlgorithmStart=0x20000000 +RAMForAlgorithmSize=0x1000 +ProgramAlgorithm=N512_AP_64.FLM +[Mini57] +Connect=0 +Reset=Autodetect +MaxClock=1MHz +MemoryVerify=0 +IOVoltage=3300 +FlashSelect=APROM +Erase=1 +Program=1 +Verify=1 +ResetAndRun=0 +EnableFlashBreakpoint=1 +EnableLog=0 +MemAccessWhileRun=0 +RAMForAlgorithmStart=0x20000000 +RAMForAlgorithmSize=0x800 +ProgramAlgorithm=Mini57_AP_29_5.FLM +[Mini51] +Connect=0 +Reset=Autodetect +MaxClock=1MHz +MemoryVerify=0 +IOVoltage=3300 +FlashSelect=APROM +Erase=1 +Program=1 +Verify=1 +ResetAndRun=0 +EnableFlashBreakpoint=1 +EnableLog=0 +MemAccessWhileRun=0 +RAMForAlgorithmStart=0x20000000 +RAMForAlgorithmSize=0x800 +ProgramAlgorithm=Mini51_AP_16.FLM +[M481] +Connect=0 +Reset=Autodetect +MaxClock=1MHz +MemoryVerify=0 +IOVoltage=3300 +FlashSelect=APROM +Erase=1 +Program=1 +Verify=1 +ResetAndRun=0 +EnableFlashBreakpoint=1 +EnableLog=0 +MemAccessWhileRun=0 +RAMForAlgorithmStart=0x20000000 +RAMForAlgorithmSize=0x4000 +ProgramAlgorithm=M481_AP_512.FLM +TraceConf0=0x00000002 +TraceConf1=0x00b71b00 +TraceConf2=0x00000800 +TraceConf3=0x00000000 +TraceConf4=0x00000001 +TraceConf5=0x00000000 +CheckDPM=0 +DisableTimeoutDetect=0 +[M480LD] +Connect=0 +Reset=Autodetect +MaxClock=1MHz +MemoryVerify=0 +IOVoltage=3300 +FlashSelect=APROM +Erase=1 +Program=1 +Verify=1 +ResetAndRun=0 +EnableFlashBreakpoint=1 +EnableLog=0 +MemAccessWhileRun=0 +RAMForAlgorithmStart=0x20000000 +RAMForAlgorithmSize=0x4000 +ProgramAlgorithm=M480LD_AP_256.FLM +[M479] +Connect=0 +Reset=Autodetect +MaxClock=1MHz +MemoryVerify=0 +IOVoltage=3300 +FlashSelect=APROM +Erase=1 +Program=1 +Verify=1 +ResetAndRun=0 +EnableFlashBreakpoint=1 +EnableLog=0 +MemAccessWhileRun=0 +RAMForAlgorithmStart=0x20000000 +RAMForAlgorithmSize=0x4000 +ProgramAlgorithm=M479_AP_256.FLM +[M471] +Connect=0 +Reset=Autodetect +MaxClock=1MHz +MemoryVerify=0 +IOVoltage=3300 +FlashSelect=APROM +Bank=0 +Erase=1 +Program=1 +Verify=1 +ResetAndRun=1 +EnableFlashBreakpoint=0 +EnableLog=0 +MemAccessWhileRun=0 +RAMForAlgorithmStart=0x20000000 +RAMForAlgorithmSize=0x4000 +ProgramAlgorithm=M471_AP_512.FLM +TraceConf0=0x00000002 +TraceConf1=0x00b71b00 +TraceConf2=0x00000800 +TraceConf3=0x00000000 +TraceConf4=0x00000001 +TraceConf5=0x00000000 +[M460] +Connect=0 +Reset=Autodetect +MaxClock=1MHz +MemoryVerify=0 +IOVoltage=3300 +FlashSelect=APROM +Bank=0 +SPIM=0 +SPIMOption=0xAD000000 +Erase=1 +Program=1 +Verify=1 +ResetAndRun=1 +EnableFlashBreakpoint=0 +EnableLog=0 +MemAccessWhileRun=0 +RAMForAlgorithmStart=0x20000000 +RAMForAlgorithmSize=0x8000 +ProgramAlgorithm=M460_AP_1M.FLM +ProgramAlgorithm1=M460_SPIM_AP_1M.FLM +TraceConf0=0x00000002 +TraceConf1=0x00b71b00 +TraceConf2=0x00000800 +TraceConf3=0x00000000 +TraceConf4=0x00000001 +TraceConf5=0x00000000 +[M451] +Connect=0 +Reset=Autodetect +MaxClock=1MHz +MemoryVerify=0 +IOVoltage=3300 +FlashSelect=APROM +Erase=1 +Program=1 +Verify=1 +ResetAndRun=0 +EnableFlashBreakpoint=1 +EnableLog=0 +MemAccessWhileRun=0 +RAMForAlgorithmStart=0x20000000 +RAMForAlgorithmSize=0x4000 +ProgramAlgorithm=M451_AP_256.FLM +[M2354] +Connect=0 +Reset=Autodetect +MaxClock=1MHz +MemoryVerify=0 +IOVoltage=3300 +FlashSelect=APROM +Bank=0 +Erase=1 +Program=1 +Verify=1 +ResetAndRun=1 +EnableFlashBreakpoint=0 +EnableLog=0 +MemAccessWhileRun=0 +CheckDPM=0 +RAMForAlgorithmStart=0x20000000 +RAMForAlgorithmSize=0x4000 +ProgramAlgorithm=M2354_AP_1M.FLM +TraceConf0=0x00000002 +TraceConf1=0x00b71b00 +TraceConf2=0x00000800 +TraceConf3=0x00000000 +TraceConf4=0x00000001 +TraceConf5=0x00000000 +[M2351] +Connect=0 +Reset=Autodetect +MaxClock=1MHz +MemoryVerify=0 +IOVoltage=3300 +FlashSelect=APROM +Erase=1 +Program=1 +Verify=1 +ResetAndRun=1 +EnableFlashBreakpoint=0 +EnableLog=0 +MemAccessWhileRun=0 +RAMForAlgorithmStart=0x20000000 +RAMForAlgorithmSize=0x4000 +ProgramAlgorithm=M2351_AP_512.FLM +TraceConf0=0x00000002 +TraceConf1=0x00b71b00 +TraceConf2=0x00000800 +TraceConf3=0x00000000 +TraceConf4=0x00000001 +TraceConf5=0x00000000 +[M261] +Connect=0 +Reset=Autodetect +MaxClock=1MHz +MemoryVerify=0 +IOVoltage=3300 +FlashSelect=APROM +Erase=1 +Program=1 +Verify=1 +ResetAndRun=1 +EnableFlashBreakpoint=0 +EnableLog=0 +MemAccessWhileRun=0 +RAMForAlgorithmStart=0x20000000 +RAMForAlgorithmSize=0x4000 +ProgramAlgorithm=M261_AP_512.FLM +TraceConf0=0x00000002 +TraceConf1=0x00b71b00 +TraceConf2=0x00000800 +TraceConf3=0x00000000 +TraceConf4=0x00000001 +TraceConf5=0x00000000 +[M251] +Connect=0 +Reset=Autodetect +MaxClock=1MHz +MemoryVerify=0 +IOVoltage=3300 +FlashSelect=APROM +Erase=1 +Program=1 +Verify=1 +ResetAndRun=0 +EnableFlashBreakpoint=1 +EnableLog=0 +MemAccessWhileRun=0 +RAMForAlgorithmStart=0x20000000 +RAMForAlgorithmSize=0x2000 +ProgramAlgorithm=M251_AP_192.FLM +[MR63] +Connect=0 +Reset=Autodetect +MaxClock=1MHz +MemoryVerify=0 +IOVoltage=3300 +FlashSelect=APROM +Erase=1 +Program=1 +Verify=1 +ResetAndRun=1 +EnableFlashBreakpoint=0 +EnableLog=0 +MemAccessWhileRun=0 +RAMForAlgorithmStart=0x20000000 +RAMForAlgorithmSize=0x4000 +ProgramAlgorithm=MR63_AP_512.FLM +TraceConf0=0x00000002 +TraceConf1=0x00b71b00 +TraceConf2=0x00000800 +TraceConf3=0x00000000 +TraceConf4=0x00000001 +TraceConf5=0x00000000 +[M071] +Connect=0 +Reset=Autodetect +MaxClock=1MHz +MemoryVerify=0 +IOVoltage=3300 +FlashSelect=APROM +Erase=1 +Program=1 +Verify=1 +ResetAndRun=0 +EnableFlashBreakpoint=1 +EnableLog=0 +MemAccessWhileRun=0 +RAMForAlgorithmStart=0x20000000 +RAMForAlgorithmSize=0x2000 +ProgramAlgorithm=M071_AP_128.FLM +[M0564] +Connect=0 +Reset=Autodetect +MaxClock=1MHz +MemoryVerify=0 +IOVoltage=3300 +FlashSelect=APROM +Erase=1 +Program=1 +Verify=1 +ResetAndRun=0 +EnableFlashBreakpoint=1 +EnableLog=0 +MemAccessWhileRun=0 +RAMForAlgorithmStart=0x20000000 +RAMForAlgorithmSize=0x2000 +ProgramAlgorithm=M0564_AP_256.FLM +[M0519] +Connect=0 +Reset=Autodetect +MaxClock=1MHz +MemoryVerify=0 +IOVoltage=3300 +FlashSelect=APROM +Erase=1 +Program=1 +Verify=1 +ResetAndRun=0 +EnableFlashBreakpoint=1 +EnableLog=0 +MemAccessWhileRun=0 +RAMForAlgorithmStart=0x20000000 +RAMForAlgorithmSize=0x1000 +ProgramAlgorithm=M0519_AP_128.FLM +[M0518] +Connect=0 +Reset=Autodetect +MaxClock=1MHz +MemoryVerify=0 +IOVoltage=3300 +FlashSelect=APROM +Erase=1 +Program=1 +Verify=1 +ResetAndRun=0 +EnableFlashBreakpoint=1 +EnableLog=0 +MemAccessWhileRun=0 +RAMForAlgorithmStart=0x20000000 +RAMForAlgorithmSize=0x1000 +ProgramAlgorithm=M0518_AP_64.FLM +[M05x] +Connect=0 +Reset=Autodetect +MaxClock=1MHz +MemoryVerify=0 +IOVoltage=3300 +FlashSelect=APROM +Erase=1 +Program=1 +Verify=1 +ResetAndRun=0 +EnableFlashBreakpoint=1 +EnableLog=0 +MemAccessWhileRun=0 +RAMForAlgorithmStart=0x20000000 +RAMForAlgorithmSize=0x800 +ProgramAlgorithm=M0516_AP_64.FLM +[M0A21] +Connect=0 +Reset=Autodetect +MaxClock=1MHz +MemoryVerify=0 +IOVoltage=3300 +FlashSelect=APROM +Erase=1 +Program=1 +Verify=1 +ResetAndRun=1 +EnableFlashBreakpoint=0 +EnableLog=0 +MemAccessWhileRun=0 +RAMForAlgorithmStart=0x20000000 +RAMForAlgorithmSize=0x800 +ProgramAlgorithm=M0A21_AP_32.FLM +[M030G] +Connect=0 +Reset=Autodetect +MaxClock=1MHz +MemoryVerify=0 +IOVoltage=3300 +FlashSelect=APROM +Erase=1 +Program=1 +Verify=1 +ResetAndRun=1 +EnableFlashBreakpoint=0 +EnableLog=0 +MemAccessWhileRun=0 +DisableTimeoutDetect=0 +RAMForAlgorithmStart=0x20000000 +RAMForAlgorithmSize=0x800 +ProgramAlgorithm=M030G_AP_64.FLM +[M031] +Connect=0 +Reset=Autodetect +MaxClock=1MHz +MemoryVerify=0 +IOVoltage=3300 +FlashSelect=APROM +Bank=0 +Erase=1 +Program=1 +Verify=1 +ResetAndRun=1 +EnableFlashBreakpoint=0 +EnableLog=0 +MemAccessWhileRun=0 +RAMForAlgorithmStart=0x20000000 +RAMForAlgorithmSize=0x800 +ProgramAlgorithm=M031_AP_128.FLM +[NPCX] +Connect=0 +Reset=Autodetect +MaxClock=1MHz +MemoryVerify=0 +IOVoltage=3300 +FlashSelect=APROM +Erase=1 +Program=1 +Verify=1 +ResetAndRun=0 +EnableFlashBreakpoint=0 +EnableLog=0 +MemAccessWhileRun=0 +RAMForAlgorithmStart=0x20000000 +RAMForAlgorithmSize=0x4000 +ProgramAlgorithm=NPCX_AP_512.FLM +[I96000] +Connect=0 +Reset=Autodetect +MaxClock=1MHz +MemoryVerify=0 +IOVoltage=3300 +Erase=2 +Program=0 +Verify=0 +ResetAndRun=0 +EnableLog=0 +MemAccessWhileRun=0 +RAMForAlgorithmStart=0x20000000 +RAMForAlgorithmSize=0x8000 +ProgramAlgorithm= +[I94000] +Connect=0 +Reset=Autodetect +MaxClock=1MHz +MemoryVerify=0 +IOVoltage=3300 +FlashSelect=APROM +Erase=1 +Program=1 +Verify=1 +ResetAndRun=0 +EnableFlashBreakpoint=0 +EnableLog=0 +MemAccessWhileRun=0 +RAMForAlgorithmStart=0x20000000 +RAMForAlgorithmSize=0x4000 +ProgramAlgorithm=I94000_AP_512.FLM +[I91500] +Connect=0 +Reset=Autodetect +MaxClock=1MHz +MemoryVerify=0 +IOVoltage=3300 +FlashSelect=APROM +Erase=1 +Program=1 +Verify=1 +ResetAndRun=0 +EnableFlashBreakpoint=0 +EnableLog=0 +MemAccessWhileRun=0 +RAMForAlgorithmStart=0x20000000 +RAMForAlgorithmSize=0x1000 +ProgramAlgorithm=I91500_AP_64.FLM +[ISD9300] +Connect=0 +Reset=Autodetect +MaxClock=1MHz +MemoryVerify=0 +IOVoltage=3300 +FlashSelect=APROM +Erase=1 +Program=1 +Verify=1 +ResetAndRun=0 +EnableFlashBreakpoint=0 +EnableLog=0 +MemAccessWhileRun=0 +RAMForAlgorithmStart=0x20000000 +RAMForAlgorithmSize=0x1000 +ProgramAlgorithm=ISD9300_AP_145.FLM +[I9200] +Connect=0 +Reset=Autodetect +MaxClock=1MHz +MemoryVerify=0 +IOVoltage=3300 +FlashSelect=APROM +Erase=1 +Program=1 +Verify=1 +ResetAndRun=0 +EnableFlashBreakpoint=0 +EnableLog=0 +MemAccessWhileRun=0 +RAMForAlgorithmStart=0x20000000 +RAMForAlgorithmSize=0x1000 +ProgramAlgorithm=I9200_AP_128.FLM +[ISD9xxx] +Connect=0 +Reset=Autodetect +MaxClock=1MHz +MemoryVerify=0 +IOVoltage=3300 +FlashSelect=APROM +Erase=1 +Program=1 +Verify=1 +ResetAndRun=0 +EnableFlashBreakpoint=0 +EnableLog=0 +MemAccessWhileRun=0 +RAMForAlgorithmStart=0x20000000 +RAMForAlgorithmSize=0x1000 +ProgramAlgorithm=ISD9100_AP_145.FLM +[ISD9000] +Connect=0 +Reset=Autodetect +MaxClock=1MHz +MemoryVerify=0 +IOVoltage=3300 +FlashSelect=APROM +Erase=1 +Program=1 +Verify=1 +ResetAndRun=0 +EnableFlashBreakpoint=0 +EnableLog=0 +MemAccessWhileRun=0 +RAMForAlgorithmStart=0x20000000 +RAMForAlgorithmSize=0x1000 +ProgramAlgorithm=ISD9000_AP_64.FLM +[AU9xxx] +Connect=0 +Reset=Autodetect +MaxClock=1MHz +MemoryVerify=0 +IOVoltage=3300 +FlashSelect=APROM +Erase=1 +Program=1 +Verify=1 +ResetAndRun=0 +EnableFlashBreakpoint=0 +EnableLog=0 +MemAccessWhileRun=0 +RAMForAlgorithmStart=0x20000000 +RAMForAlgorithmSize=0x1000 +ProgramAlgorithm=AU9100_AP_145.FLM +[KM1M7] +Connect=0 +Reset=Autodetect +MaxClock=4MHz +MemoryVerify=0 +IOVoltage=5000 +Erase=1 +Program=1 +Verify=1 +ResetAndRun=1 +EnableLog=0 +MemAccessWhileRun=0 +RAMForAlgorithmStart=0x20000000 +RAMForAlgorithmSize=0x00004000 +ProgramAlgorithm=KM1M7AFxxx_I.FLM +ProgramAlgorithm1=KM1M7AFxxx_D.FLM +TraceConf0=0x00000002 +TraceConf1=0x00b71b00 +TraceConf2=0x00000800 +TraceConf3=0x00000000 +TraceConf4=0x00000001 +TraceConf5=0x00000000 +EnableKeyfile=0 +Keycode0=0xFFFFFFFF +Keycode1=0xFFFFFFFF +Keycode2=0xFFFFFFFF +Keycode3=0xFFFFFFFF +[Autodetect] +Connect=0 +Reset=Autodetect +MaxClock=1MHz +MemoryVerify=0 +IOVoltage=3300 +Erase=1 +Program=1 +Verify=1 +ResetAndRun=0 +EnableLog=0 +MemAccessWhileRun=0 +RAMForAlgorithmStart=0x20000000 +RAMForAlgorithmSize=0x4000 +ProgramAlgorithm= +[General] +Connect=0 +Reset=Autodetect +MaxClock=1MHz +MemoryVerify=0 +IOVoltage=3300 +Erase=1 +Program=1 +Verify=1 +ResetAndRun=0 +EnableLog=0 +MemAccessWhileRun=0 +RAMForAlgorithmStart=0x20000000 +RAMForAlgorithmSize=0x4000 +ProgramAlgorithm= diff --git a/bsp/nuvoton/ma35-rtp/README.md b/bsp/nuvoton/ma35-rtp/README.md new file mode 100644 index 0000000000..4d22c3c329 --- /dev/null +++ b/bsp/nuvoton/ma35-rtp/README.md @@ -0,0 +1,22 @@ +# MA35-RTP + +## **Introduction** + +The MA35-RTP is a rt-thread porting for remote processor(RTP) of MA35 series. The firmware is copied to 0x0 by MA35 CPU. +### **RTP specification** + +| | Features | +| -- | -- | +| MCU | MA35 RTP(CM4) | +| Operation frequency | 180 MHz | +| SRAM size | 128 kB | +| DDR size | 3968 kB | +## **Supported compiler** +Support GCC compiler. More information of these compiler version as following: + +| IDE/Compiler | Tested version | +| ---------- | ---------------------------- | +| MDK5 | 5.26.2 | +| GCC | GCC 5.4.1 20160919 (release) | + +Notice: Please install Nu-Link_Keil_Driver for development. diff --git a/bsp/nuvoton/ma35-rtp/SConscript b/bsp/nuvoton/ma35-rtp/SConscript new file mode 100644 index 0000000000..fe0ae941ae --- /dev/null +++ b/bsp/nuvoton/ma35-rtp/SConscript @@ -0,0 +1,14 @@ +# for module compiling +import os +Import('RTT_ROOT') + +cwd = str(Dir('#')) +objs = [] +list = os.listdir(cwd) + +for d in list: + path = os.path.join(cwd, d) + if os.path.isfile(os.path.join(path, 'SConscript')): + objs = objs + SConscript(os.path.join(d, 'SConscript')) + +Return('objs') diff --git a/bsp/nuvoton/ma35-rtp/SConstruct b/bsp/nuvoton/ma35-rtp/SConstruct new file mode 100644 index 0000000000..cd14e5b0a7 --- /dev/null +++ b/bsp/nuvoton/ma35-rtp/SConstruct @@ -0,0 +1,59 @@ +import os +import sys +import rtconfig + +if os.getenv('RTT_ROOT'): + RTT_ROOT = os.getenv('RTT_ROOT') +else: + RTT_ROOT = os.path.normpath(os.getcwd() + '/../../..') + +sys.path = sys.path + [os.path.join(RTT_ROOT, 'tools')] +try: + from building import * +except: + print('Cannot found RT-Thread root directory, please check RTT_ROOT') + print(RTT_ROOT) + exit(-1) + +TARGET = 'rtthread.' + rtconfig.TARGET_EXT + +DefaultEnvironment(tools=[]) +env = Environment(tools = ['mingw'], + AS = rtconfig.AS, ASFLAGS = rtconfig.AFLAGS, + CC = rtconfig.CC, CCFLAGS = rtconfig.CFLAGS, + AR = rtconfig.AR, ARFLAGS = '-rc', + LINK = rtconfig.LINK, LINKFLAGS = rtconfig.LFLAGS) +env.PrependENVPath('PATH', rtconfig.EXEC_PATH) + +if rtconfig.PLATFORM == 'iar': + env.Replace(CCCOM = ['$CC $CCFLAGS $CPPFLAGS $_CPPDEFFLAGS $_CPPINCFLAGS -o $TARGET $SOURCES']) + env.Replace(ARFLAGS = ['']) + env.Replace(LINKCOM = env["LINKCOM"] + ' --map rt-thread.map') + +Export('RTT_ROOT') +Export('rtconfig') + +SDK_ROOT = os.path.abspath('./') + +if os.path.exists(SDK_ROOT + '/libraries'): + libraries_path_prefix = SDK_ROOT + '/libraries' +else: + libraries_path_prefix = os.path.dirname(SDK_ROOT) + '/libraries' + +SDK_LIB = libraries_path_prefix +Export('SDK_LIB') + +# prepare building environment +objs = PrepareBuilding(env, RTT_ROOT, has_libcpu=False) + +nuvoton_library = 'ma35' +rtconfig.BSP_LIBRARY_TYPE = nuvoton_library + +# include libraries +objs.extend(SConscript(os.path.join(libraries_path_prefix, nuvoton_library, 'SConscript'))) + +# include nu_pkgs +objs.extend(SConscript(os.path.join(libraries_path_prefix, 'nu_packages', 'SConscript'))) + +# make a building +DoBuilding(TARGET, objs) diff --git a/bsp/nuvoton/ma35-rtp/applications/SConscript b/bsp/nuvoton/ma35-rtp/applications/SConscript new file mode 100644 index 0000000000..9ffdbcd0f9 --- /dev/null +++ b/bsp/nuvoton/ma35-rtp/applications/SConscript @@ -0,0 +1,11 @@ +# RT-Thread building script for component + +from building import * + +cwd = GetCurrentDir() +src = Glob('*.c') + Glob('*.cpp') +CPPPATH = [cwd, str(Dir('#'))] + +group = DefineGroup('Applications', src, depend = [''], CPPPATH = CPPPATH) + +Return('group') diff --git a/bsp/nuvoton/ma35-rtp/applications/main.c b/bsp/nuvoton/ma35-rtp/applications/main.c new file mode 100644 index 0000000000..524596cee0 --- /dev/null +++ b/bsp/nuvoton/ma35-rtp/applications/main.c @@ -0,0 +1,47 @@ +/**************************************************************************//** +* @copyright (C) 2019 Nuvoton Technology Corp. All rights reserved. +* +* SPDX-License-Identifier: Apache-2.0 +* +* Change Logs: +* Date Author Notes +* 2021-7-20 Wayne First version +* +******************************************************************************/ + +#include +#include +#include "drv_common.h" + +#if defined(RT_USING_PIN) + + #include "drv_gpio.h" + /* defined the LED_1 pin: PJ15 */ + #define LED_1 NU_GET_PININDEX(NU_PJ, 15) + +#endif + +int main(int argc, char **argv) +{ + int counter = 10000; + +#if defined(RT_USING_PIN) + /* set LED_1 pin mode to output */ + rt_pin_mode(LED_1, PIN_MODE_OUTPUT); +#endif + + while (counter--) + { + rt_kprintf("Hello! MA35-RTP.\n"); + +#if defined(RT_USING_PIN) + rt_pin_write(LED_1, PIN_HIGH); + rt_thread_mdelay(1000); + rt_pin_write(LED_1, PIN_LOW); + rt_thread_mdelay(1000); +#else + rt_thread_mdelay(1000); +#endif + } + return 0; +} diff --git a/bsp/nuvoton/ma35-rtp/applications/mnt.c b/bsp/nuvoton/ma35-rtp/applications/mnt.c new file mode 100644 index 0000000000..9325b11090 --- /dev/null +++ b/bsp/nuvoton/ma35-rtp/applications/mnt.c @@ -0,0 +1,14 @@ +/**************************************************************************//** +* +* @copyright (C) 2019 Nuvoton Technology Corp. All rights reserved. +* +* SPDX-License-Identifier: Apache-2.0 +* +* Change Logs: +* Date Author Notes +* 2020-1-16 Wayne First version +* +******************************************************************************/ + +#include + diff --git a/bsp/nuvoton/ma35-rtp/board/Kconfig b/bsp/nuvoton/ma35-rtp/board/Kconfig new file mode 100644 index 0000000000..9fde36235a --- /dev/null +++ b/bsp/nuvoton/ma35-rtp/board/Kconfig @@ -0,0 +1,23 @@ +menu "Hardware Drivers Config" + + menu "On-chip Peripheral Drivers" + source "$BSP_DIR/../libraries/ma35/rtt_port/Kconfig" + endmenu + + menu "On-board Peripheral Drivers" + + config BSP_USING_NULINKME + bool "Enable UART16 for RTT Console(uart16)" + select BSP_USING_UART + select BSP_USING_UART16 + default y + + endmenu + + menu "Board extended module drivers" + + endmenu + + source "$BSP_DIR/../libraries/nu_packages/Kconfig" + +endmenu diff --git a/bsp/nuvoton/ma35-rtp/board/SConscript b/bsp/nuvoton/ma35-rtp/board/SConscript new file mode 100644 index 0000000000..38791565a2 --- /dev/null +++ b/bsp/nuvoton/ma35-rtp/board/SConscript @@ -0,0 +1,18 @@ +# RT-Thread building script for component + +from building import * + + +Import('RTT_ROOT') +from building import * + +cwd = GetCurrentDir() +src = Split(""" +nutool_pincfg/nutool_pincfg.c +""") +src += Glob('*.c') + Glob('*.cpp') + Glob('*.S') +CPPPATH = [cwd, cwd + '/nutool_pincfg'] + +group = DefineGroup('board', src, depend = [''], CPPPATH = CPPPATH) + +Return('group') diff --git a/bsp/nuvoton/ma35-rtp/board/board.h b/bsp/nuvoton/ma35-rtp/board/board.h new file mode 100644 index 0000000000..c08d84b5fc --- /dev/null +++ b/bsp/nuvoton/ma35-rtp/board/board.h @@ -0,0 +1,42 @@ +/**************************************************************************//** +* +* @copyright (C) 2020 Nuvoton Technology Corp. All rights reserved. +* +* SPDX-License-Identifier: Apache-2.0 +* +* Change Logs: +* Date Author Notes +* 2021-7-19 Wayne First version +* +******************************************************************************/ + +#ifndef __BOARD_H__ +#define __BOARD_H__ + +#include +#include "NuMicro.h" + +// Internal SRAM memory size[Kbytes] <8-64> +#define BOARD_SDRAM_START 0x00000000 +#define BOARD_SDRAM_SIZE (4*1024*1024) + +#if defined(__CC_ARM) || defined(__CLANG_ARM) + // extern int Image$$ER_IROM1$$ZI$$Limit; + // #define BOARD_HEAP_START ((void *)&Image$$ER_IROM1$$ZI$$Limit) + extern uint32_t __initial_sp; + #define BOARD_HEAP_START ((void *)&__initial_sp) +#elif __ICCARM__ + #pragma section="CSTACK" + #define BOARD_HEAP_START (__segment_end("CSTACK")) +#else + extern int __bss_end; + #define BOARD_HEAP_START ((void *)&__bss_end) +#endif + +#define BOARD_HEAP_END ((void*)(BOARD_SDRAM_START+BOARD_SDRAM_SIZE)) + +void rt_hw_board_init(void); +void rt_hw_cpu_reset(void); +void nu_pin_init(void); + +#endif /* BOARD_H_ */ diff --git a/bsp/nuvoton/ma35-rtp/board/board_dev.c b/bsp/nuvoton/ma35-rtp/board/board_dev.c new file mode 100644 index 0000000000..1e1c8ba564 --- /dev/null +++ b/bsp/nuvoton/ma35-rtp/board/board_dev.c @@ -0,0 +1,14 @@ +/**************************************************************************//** +* +* @copyright (C) 2019 Nuvoton Technology Corp. All rights reserved. +* +* SPDX-License-Identifier: Apache-2.0 +* +* Change Logs: +* Date Author Notes +* 2021-7-19 Wayne First version +* +******************************************************************************/ + +#include + diff --git a/bsp/nuvoton/ma35-rtp/board/nutool_pincfg/nutool_pincfg.c b/bsp/nuvoton/ma35-rtp/board/nutool_pincfg/nutool_pincfg.c new file mode 100644 index 0000000000..1d64bf258b --- /dev/null +++ b/bsp/nuvoton/ma35-rtp/board/nutool_pincfg/nutool_pincfg.c @@ -0,0 +1,52 @@ +/**************************************************************************** + * @file nutool_pincfg.c + * @version V1.24 + * @Date 2021/08/03-14:56:47 + * @brief NuMicro generated code file + * + * SPDX-License-Identifier: Apache-2.0 + * + * Copyright (C) 2013-2021 Nuvoton Technology Corp. All rights reserved. +*****************************************************************************/ + +/******************** +MCU:MA35D16A887C(BGA312) +Pin Configuration: + +PinG16:UART16_nRTS +PinH16:UART16_nCTS +PinJ16:UART16_TXD +PinK16:UART16_RXD +********************/ + +#include "ma35d1.h" +void nutool_pincfg_init_uart16(void) +{ + SYS->GPK_MFPL &= ~(SYS_GPK_MFPL_PK3MFP_Msk | SYS_GPK_MFPL_PK2MFP_Msk | SYS_GPK_MFPL_PK1MFP_Msk | SYS_GPK_MFPL_PK0MFP_Msk); + SYS->GPK_MFPL |= (SYS_GPK_MFPL_PK3MFP_UART16_TXD | SYS_GPK_MFPL_PK2MFP_UART16_RXD | SYS_GPK_MFPL_PK1MFP_UART16_nRTS | SYS_GPK_MFPL_PK0MFP_UART16_nCTS); + + return; +} + +void nutool_pincfg_deinit_uart16(void) +{ + SYS->GPK_MFPL &= ~(SYS_GPK_MFPL_PK3MFP_Msk | SYS_GPK_MFPL_PK2MFP_Msk | SYS_GPK_MFPL_PK1MFP_Msk | SYS_GPK_MFPL_PK0MFP_Msk); + + return; +} +void nutool_pincfg_init(void) +{ + nutool_pincfg_init_uart16(); + + return; +} + +void nutool_pincfg_deinit(void) +{ + + nutool_pincfg_deinit_uart16(); + + return; +} + +/*** (C) COPYRIGHT 2013-2021 Nuvoton Technology Corp. ***/ diff --git a/bsp/nuvoton/ma35-rtp/board/nutool_pincfg/nutool_pincfg.h b/bsp/nuvoton/ma35-rtp/board/nutool_pincfg/nutool_pincfg.h new file mode 100644 index 0000000000..16dd290d0c --- /dev/null +++ b/bsp/nuvoton/ma35-rtp/board/nutool_pincfg/nutool_pincfg.h @@ -0,0 +1,80 @@ +/**************************************************************************** + * @file nutool_pincfg.h + * @version V1.24 + * @Date 2021/08/03-14:56:47 + * @brief NuMicro generated code file + * + * SPDX-License-Identifier: Apache-2.0 + * + * Copyright (C) 2013-2021 Nuvoton Technology Corp. All rights reserved. +*****************************************************************************/ + +#ifndef __NUTOOL_PINCFG_H__ +#define __NUTOOL_PINCFG_H__ + +#ifdef __cplusplus +extern "C" +{ +#endif +void nutool_pincfg_init_adc0(void); +void nutool_pincfg_deinit_adc0(void); +void nutool_pincfg_init_can1(void); +void nutool_pincfg_deinit_can1(void); +void nutool_pincfg_init_can3(void); +void nutool_pincfg_deinit_can3(void); +void nutool_pincfg_init_eadc0(void); +void nutool_pincfg_deinit_eadc0(void); +void nutool_pincfg_init_epwm1(void); +void nutool_pincfg_deinit_epwm1(void); +void nutool_pincfg_init_hsusb0(void); +void nutool_pincfg_deinit_hsusb0(void); +void nutool_pincfg_init_hsusbh(void); +void nutool_pincfg_deinit_hsusbh(void); +void nutool_pincfg_init_i2c1(void); +void nutool_pincfg_deinit_i2c1(void); +void nutool_pincfg_init_i2c2(void); +void nutool_pincfg_deinit_i2c2(void); +void nutool_pincfg_init_i2c3(void); +void nutool_pincfg_deinit_i2c3(void); +void nutool_pincfg_init_i2c4(void); +void nutool_pincfg_deinit_i2c4(void); +void nutool_pincfg_init_i2c5(void); +void nutool_pincfg_deinit_i2c5(void); +void nutool_pincfg_init_i2s0(void); +void nutool_pincfg_deinit_i2s0(void); +void nutool_pincfg_init_lcm(void); +void nutool_pincfg_deinit_lcm(void); +void nutool_pincfg_init_nand(void); +void nutool_pincfg_deinit_nand(void); +void nutool_pincfg_init_qspi0(void); +void nutool_pincfg_deinit_qspi0(void); +void nutool_pincfg_init_rgmii0(void); +void nutool_pincfg_deinit_rgmii0(void); +void nutool_pincfg_init_rgmii1(void); +void nutool_pincfg_deinit_rgmii1(void); +void nutool_pincfg_init_sd0(void); +void nutool_pincfg_deinit_sd0(void); +void nutool_pincfg_init_sd1(void); +void nutool_pincfg_deinit_sd1(void); +void nutool_pincfg_init_uart0(void); +void nutool_pincfg_deinit_uart0(void); +void nutool_pincfg_init_uart11(void); +void nutool_pincfg_deinit_uart11(void); +void nutool_pincfg_init_uart12(void); +void nutool_pincfg_deinit_uart12(void); +void nutool_pincfg_init_uart14(void); +void nutool_pincfg_deinit_uart14(void); +void nutool_pincfg_init_uart16(void); +void nutool_pincfg_deinit_uart16(void); +void nutool_pincfg_init_vcap0(void); +void nutool_pincfg_deinit_vcap0(void); +void nutool_pincfg_init_vcap1(void); +void nutool_pincfg_deinit_vcap1(void); +void nutool_pincfg_init(void); +void nutool_pincfg_deinit(void); +#ifdef __cplusplus +} +#endif +#endif /*__NUTOOL_PINCFG_H__*/ + +/*** (C) COPYRIGHT 2013-2021 Nuvoton Technology Corp. ***/ diff --git a/bsp/nuvoton/ma35-rtp/linking_scripts/subm.ld b/bsp/nuvoton/ma35-rtp/linking_scripts/subm.ld new file mode 100644 index 0000000000..dbf7698510 --- /dev/null +++ b/bsp/nuvoton/ma35-rtp/linking_scripts/subm.ld @@ -0,0 +1,160 @@ +/**************************************************************************//** +* +* @copyright (C) 2019 Nuvoton Technology Corp. All rights reserved. +* +* SPDX-License-Identifier: Apache-2.0 +* +* Change Logs: +* Date Author Notes +* 2021-07-19 Wayne First version +* +******************************************************************************/ + +/* Program Entry, set to mark it as "used" and avoid gc */ +MEMORY +{ + SRAM0_DDR (rxw) : ORIGIN = 0x00000000, LENGTH = 4096k /* 128K SRAM0 + 3.8MB DDR */ +} +ENTRY(Reset_Handler) +_system_stack_size = 0x1000; + +SECTIONS +{ + .vector : + { + . = ALIGN(4); + _stext = .; + KEEP(*(.isr_vector)) /* Startup code */ + } > SRAM0_DDR = 0 + + .text : + { + . = ALIGN(4); + *(.text) /* remaining code */ + *(.text.*) /* remaining code */ + *(.rodata) /* read-only data (constants) */ + *(.rodata*) + *(.glue_7) + *(.glue_7t) + *(.gnu.linkonce.t*) + + /* section information for finsh shell */ + . = ALIGN(4); + __fsymtab_start = .; + KEEP(*(FSymTab)) + __fsymtab_end = .; + . = ALIGN(4); + __vsymtab_start = .; + KEEP(*(VSymTab)) + __vsymtab_end = .; + . = ALIGN(4); + + /* section information for initial. */ + . = ALIGN(4); + __rt_init_start = .; + KEEP(*(SORT(.rti_fn*))) + __rt_init_end = .; + . = ALIGN(4); + + /* section information for utest */ + . = ALIGN(4); + __rt_utest_tc_tab_start = .; + KEEP(*(UtestTcTab)) + __rt_utest_tc_tab_end = .; + + . = ALIGN(4); + _etext = .; + } > SRAM0_DDR + + /* .ARM.exidx is sorted, so has to go in its own output section. */ + __exidx_start = .; + .ARM.exidx : + { + *(.ARM.exidx* .gnu.linkonce.armexidx.*) + + /* This is used by the startup in order to initialize the .data section */ + _sidata = .; + } > SRAM0_DDR + __exidx_end = .; + + /* .data section which is used for initialized data */ + + .stack : + { + _sstack = .; + . = . + _system_stack_size; + . = ALIGN(4); + _estack = .; + } > SRAM0_DDR + + .data : AT (_sidata) + { + . = ALIGN(4); + /* This is used by the startup in order to initialize the .data section */ + _sdata = . ; + + *(.data) + *(.data.*) + *(.gnu.linkonce.d*) + + . = ALIGN(4); + /* This is used by the startup in order to initialize the .data section */ + _edata = . ; + } > SRAM0_DDR + + __bss_start = .; + .bss : + { + . = ALIGN(4); + /* This is used by the startup in order to initialize the .bss section */ + _sbss = .; + + *(.bss) + *(.bss.*) + *(COMMON) + + . = ALIGN(4); + /* This is used by the startup in order to initialize the .bss section */ + _ebss = . ; + + *(.bss.init) + } > SRAM0_DDR + __bss_end = .; + _end = .; + + __ram_top = ORIGIN(SRAM0_DDR) + LENGTH(SRAM0_DDR); + + /* Stabs debugging sections. */ + .stab 0 : { *(.stab) } + .stabstr 0 : { *(.stabstr) } + .stab.excl 0 : { *(.stab.excl) } + .stab.exclstr 0 : { *(.stab.exclstr) } + .stab.index 0 : { *(.stab.index) } + .stab.indexstr 0 : { *(.stab.indexstr) } + .comment 0 : { *(.comment) } + /* DWARF debug sections. + * Symbols in the DWARF debugging sections are relative to the beginning + * of the section so we begin them at 0. */ + /* DWARF 1 */ + .debug 0 : { *(.debug) } + .line 0 : { *(.line) } + /* GNU DWARF 1 extensions */ + .debug_srcinfo 0 : { *(.debug_srcinfo) } + .debug_sfnames 0 : { *(.debug_sfnames) } + /* DWARF 1.1 and DWARF 2 */ + .debug_aranges 0 : { *(.debug_aranges) } + .debug_pubnames 0 : { *(.debug_pubnames) } + /* DWARF 2 */ + .debug_info 0 : { *(.debug_info .gnu.linkonce.wi.*) } + .debug_abbrev 0 : { *(.debug_abbrev) } + .debug_line 0 : { *(.debug_line) } + .debug_frame 0 : { *(.debug_frame) } + .debug_str 0 : { *(.debug_str) } + .debug_loc 0 : { *(.debug_loc) } + .debug_macinfo 0 : { *(.debug_macinfo) } + /* SGI/MIPS DWARF 2 extensions */ + .debug_weaknames 0 : { *(.debug_weaknames) } + .debug_funcnames 0 : { *(.debug_funcnames) } + .debug_typenames 0 : { *(.debug_typenames) } + .debug_varnames 0 : { *(.debug_varnames) } +} diff --git a/bsp/nuvoton/ma35-rtp/ma35-rtp.uvprojx b/bsp/nuvoton/ma35-rtp/ma35-rtp.uvprojx new file mode 100644 index 0000000000..8abb92a0b6 --- /dev/null +++ b/bsp/nuvoton/ma35-rtp/ma35-rtp.uvprojx @@ -0,0 +1,1012 @@ + + + + 2.1 + +
### uVision Project, (C) Keil Software
+ + + + rtthread-subm + 0x4 + ARM-ADS + 5060750::V5.06 update 6 (build 750)::ARMCC + 0 + + + ARMCM4_FP + ARM + ARM.CMSIS.5.7.0 + http://www.keil.com/pack/ + IRAM(0x20000000,0x00020000) IROM(0x00000000,0x00040000) CPUTYPE("Cortex-M4") FPU2 CLOCK(12000000) ESEL ELITTLE + + + UL2CM3(-S0 -C0 -P0 -FD20000000 -FC1000) + 0 + $$Device:ARMCM4_FP$Device\ARM\ARMCM4\Include\ARMCM4_FP.h + + + + + + + + + + + 0 + 0 + + + + + + + 0 + 0 + 0 + 0 + 1 + + .\build\keil5\ + rtthread + 1 + 0 + 1 + 1 + 0 + .\build\keil5\ + 1 + 0 + 0 + + 0 + 0 + + + 0 + 0 + 0 + 0 + + + 0 + 0 + + + 0 + 0 + 0 + 0 + + + 1 + 1 + fromelf.exe --bin --output "$L@L.bin" "$L@L.axf" + fromelf --text -c "$L@L.axf" --output "$L@L.txt" + 0 + 0 + 0 + 0 + + 1 + + + + 0 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 3 + + + 1 + + + SARMCM3.DLL + -MPU + DCM.DLL + -pCM4 + SARMCM3.DLL + -MPU + TCM.DLL + -pCM4 + + + + 1 + 0 + 0 + 0 + 16 + + + + + 1 + 0 + 0 + 1 + 1 + 4099 + + 1 + BIN\UL2CM3.DLL + + + + + + 0 + + + + 0 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 1 + 1 + 0 + 1 + 1 + 0 + 0 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 1 + "Cortex-M4" + + 0 + 0 + 0 + 1 + 1 + 0 + 0 + 2 + 0 + 0 + 0 + 8 + 0 + 1 + 0 + 0 + 3 + 3 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 1 + 0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x20000000 + 0x20000 + + + 1 + 0x0 + 0x40000 + + + 0 + 0x0 + 0x0 + + + 1 + 0x0 + 0x0 + + + 1 + 0x0 + 0x0 + + + 1 + 0x0 + 0x0 + + + 1 + 0x0 + 0x40000 + + + 1 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x20000000 + 0x20000 + + + 0 + 0x0 + 0x0 + + + + + + 1 + 3 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 2 + 0 + 0 + 0 + 1 + 0 + 1 + 1 + 1 + 1 + 0 + 0 + 0 + + + RT_USING_LIBC, __RTTHREAD__, __STDC_LIMIT_MACROS, RT_USING_ARM_LIBC, __CLK_TCK=RT_TICK_PER_SECOND + + ..\..\..\components\libc\compilers\common\extension;..\..\..\components\libc\posix\io\stdio;..\..\..\libcpu\arm\common;..\..\..\components\drivers\include;..\..\..\components\libc\compilers\common\extension\fcntl\octal;..\libraries\ma35\CMSIS\Include;..\..\..\examples\utest\testcases\utest;board\nutool_pincfg;..\libraries\ma35\Device\Nuvoton\MA35D1\Include;..\..\..\components\finsh;..\..\..\components\utilities\utest;..\libraries\ma35\StdDriver\inc;..\..\..\examples\utest\testcases\kernel;..\..\..\components\drivers\include;..\libraries\ma35\rtt_port;..\..\..\components\libc\posix\ipc;..\libraries\nu_packages\TPC;board;..\..\..\components\drivers\include;..\..\..\components\libc\posix\io\poll;.;test\template;..\..\..\include;..\..\..\libcpu\arm\cortex-m4;applications;..\libraries\ma35\libcpu\arm\cortex-m4;..\..\..\components\libc\compilers\common\include;..\..\..\components\utilities\ulog;..\libraries\nu_packages\NuUtils\inc + + + + 1 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + + + + + + + + + 0 + 0 + 0 + 0 + 1 + 0 + 0x00000000 + + + + + + + + + + + + + + Applications + + + main.c + 1 + applications\main.c + + + mnt.c + 1 + applications\mnt.c + + + + + board + + + board_dev.c + 1 + board\board_dev.c + + + nutool_pincfg.c + 1 + board\nutool_pincfg\nutool_pincfg.c + + + + + Compiler + + + syscall_mem.c + 1 + ..\..\..\components\libc\compilers\armlibc\syscall_mem.c + + + syscalls.c + 1 + ..\..\..\components\libc\compilers\armlibc\syscalls.c + + + cctype.c + 1 + ..\..\..\components\libc\compilers\common\cctype.c + + + cstdio.c + 1 + ..\..\..\components\libc\compilers\common\cstdio.c + + + cstdlib.c + 1 + ..\..\..\components\libc\compilers\common\cstdlib.c + + + cstring.c + 1 + ..\..\..\components\libc\compilers\common\cstring.c + + + ctime.c + 1 + ..\..\..\components\libc\compilers\common\ctime.c + + + cwchar.c + 1 + ..\..\..\components\libc\compilers\common\cwchar.c + + + + + CPU + + + backtrace.c + 1 + ..\..\..\libcpu\arm\common\backtrace.c + + + div0.c + 1 + ..\..\..\libcpu\arm\common\div0.c + + + showmem.c + 1 + ..\..\..\libcpu\arm\common\showmem.c + + + context_rvds.S + 2 + ..\..\..\libcpu\arm\cortex-m4\context_rvds.S + + + cpuport.c + 1 + ..\..\..\libcpu\arm\cortex-m4\cpuport.c + + + interrupt.c + 1 + ..\libraries\ma35\libcpu\arm\cortex-m4\interrupt.c + + + + + DeviceDrivers + + + completion.c + 1 + ..\..\..\components\drivers\ipc\completion.c + + + dataqueue.c + 1 + ..\..\..\components\drivers\ipc\dataqueue.c + + + pipe.c + 1 + ..\..\..\components\drivers\ipc\pipe.c + + + ringblk_buf.c + 1 + ..\..\..\components\drivers\ipc\ringblk_buf.c + + + ringbuffer.c + 1 + ..\..\..\components\drivers\ipc\ringbuffer.c + + + waitqueue.c + 1 + ..\..\..\components\drivers\ipc\waitqueue.c + + + workqueue.c + 1 + ..\..\..\components\drivers\ipc\workqueue.c + + + pin.c + 1 + ..\..\..\components\drivers\misc\pin.c + + + serial.c + 1 + ..\..\..\components\drivers\serial\serial.c + + + + + Drivers + + + startup_ma35d1_subm.s + 2 + ..\libraries\ma35\Device\Nuvoton\MA35D1\Source\ARM\startup_ma35d1_subm.s + + + system_ma35d1_subm.c + 1 + ..\libraries\ma35\Device\Nuvoton\MA35D1\Source\system_ma35d1_subm.c + + + drv_adc.c + 1 + ..\libraries\ma35\rtt_port\drv_adc.c + + + drv_canfd.c + 1 + ..\libraries\ma35\rtt_port\drv_canfd.c + + + drv_ccap.c + 1 + ..\libraries\ma35\rtt_port\drv_ccap.c + + + drv_common.c + 1 + ..\libraries\ma35\rtt_port\drv_common.c + + + drv_disp.c + 1 + ..\libraries\ma35\rtt_port\drv_disp.c + + + drv_eadc.c + 1 + ..\libraries\ma35\rtt_port\drv_eadc.c + + + drv_ecap.c + 1 + ..\libraries\ma35\rtt_port\drv_ecap.c + + + drv_epwm.c + 1 + ..\libraries\ma35\rtt_port\drv_epwm.c + + + drv_epwm_capture.c + 1 + ..\libraries\ma35\rtt_port\drv_epwm_capture.c + + + drv_gpio.c + 1 + ..\libraries\ma35\rtt_port\drv_gpio.c + + + drv_i2c.c + 1 + ..\libraries\ma35\rtt_port\drv_i2c.c + + + drv_i2s.c + 1 + ..\libraries\ma35\rtt_port\drv_i2s.c + + + drv_pdma.c + 1 + ..\libraries\ma35\rtt_port\drv_pdma.c + + + drv_qei.c + 1 + ..\libraries\ma35\rtt_port\drv_qei.c + + + drv_qspi.c + 1 + ..\libraries\ma35\rtt_port\drv_qspi.c + + + drv_rtc.c + 1 + ..\libraries\ma35\rtt_port\drv_rtc.c + + + drv_rtp.c + 1 + ..\libraries\ma35\rtt_port\drv_rtp.c + + + drv_scuart.c + 1 + ..\libraries\ma35\rtt_port\drv_scuart.c + + + drv_sdio.c + 1 + ..\libraries\ma35\rtt_port\drv_sdio.c + + + drv_softi2c.c + 1 + ..\libraries\ma35\rtt_port\drv_softi2c.c + + + drv_spi.c + 1 + ..\libraries\ma35\rtt_port\drv_spi.c + + + drv_spii2s.c + 1 + ..\libraries\ma35\rtt_port\drv_spii2s.c + + + drv_sys.c + 1 + ..\libraries\ma35\rtt_port\drv_sys.c + + + drv_sys_i2c0.c + 1 + ..\libraries\ma35\rtt_port\drv_sys_i2c0.c + + + drv_timer.c + 1 + ..\libraries\ma35\rtt_port\drv_timer.c + + + drv_tpwm.c + 1 + ..\libraries\ma35\rtt_port\drv_tpwm.c + + + drv_uart.c + 1 + ..\libraries\ma35\rtt_port\drv_uart.c + + + drv_usbhost.c + 1 + ..\libraries\ma35\rtt_port\drv_usbhost.c + + + drv_wdt.c + 1 + ..\libraries\ma35\rtt_port\drv_wdt.c + + + nu_clock_init.c + 1 + ..\libraries\ma35\rtt_port\nu_clock_init.c + + + + + Finsh + + + shell.c + 1 + ..\..\..\components\finsh\shell.c + + + msh.c + 1 + ..\..\..\components\finsh\msh.c + + + msh_parse.c + 1 + ..\..\..\components\finsh\msh_parse.c + + + cmd.c + 1 + ..\..\..\components\finsh\cmd.c + + + + + Kernel + + + clock.c + 1 + ..\..\..\src\clock.c + + + components.c + 1 + ..\..\..\src\components.c + + + device.c + 1 + ..\..\..\src\device.c + + + idle.c + 1 + ..\..\..\src\idle.c + + + ipc.c + 1 + ..\..\..\src\ipc.c + + + irq.c + 1 + ..\..\..\src\irq.c + + + kservice.c + 1 + ..\..\..\src\kservice.c + + + mem.c + 1 + ..\..\..\src\mem.c + + + mempool.c + 1 + ..\..\..\src\mempool.c + + + object.c + 1 + ..\..\..\src\object.c + + + scheduler.c + 1 + ..\..\..\src\scheduler.c + + + thread.c + 1 + ..\..\..\src\thread.c + + + timer.c + 1 + ..\..\..\src\timer.c + + + + + Libraries + + + nu_sc.c + 1 + ..\libraries\ma35\StdDriver\src\nu_sc.c + + + nu_wdt.c + 1 + ..\libraries\ma35\StdDriver\src\nu_wdt.c + + + nu_ccap.c + 1 + ..\libraries\ma35\StdDriver\src\nu_ccap.c + + + nu_clk.c + 1 + ..\libraries\ma35\StdDriver\src\nu_clk.c + + + nu_i2s.c + 1 + ..\libraries\ma35\StdDriver\src\nu_i2s.c + + + nu_eadc.c + 1 + ..\libraries\ma35\StdDriver\src\nu_eadc.c + + + nu_ebi.c + 1 + ..\libraries\ma35\StdDriver\src\nu_ebi.c + + + nu_scuart.c + 1 + ..\libraries\ma35\StdDriver\src\nu_scuart.c + + + nu_rtc.c + 1 + ..\libraries\ma35\StdDriver\src\nu_rtc.c + + + nu_pdma.c + 1 + ..\libraries\ma35\StdDriver\src\nu_pdma.c + + + nu_i2c.c + 1 + ..\libraries\ma35\StdDriver\src\nu_i2c.c + + + nu_epwm.c + 1 + ..\libraries\ma35\StdDriver\src\nu_epwm.c + + + nu_spi.c + 1 + ..\libraries\ma35\StdDriver\src\nu_spi.c + + + nu_sys.c + 1 + ..\libraries\ma35\StdDriver\src\nu_sys.c + + + nu_wwdt.c + 1 + ..\libraries\ma35\StdDriver\src\nu_wwdt.c + + + nu_sdh.c + 1 + ..\libraries\ma35\StdDriver\src\nu_sdh.c + + + nu_adc.c + 1 + ..\libraries\ma35\StdDriver\src\nu_adc.c + + + nu_uart.c + 1 + ..\libraries\ma35\StdDriver\src\nu_uart.c + + + nu_timer.c + 1 + ..\libraries\ma35\StdDriver\src\nu_timer.c + + + nu_kpi.c + 1 + ..\libraries\ma35\StdDriver\src\nu_kpi.c + + + nu_ssmcc.c + 1 + ..\libraries\ma35\StdDriver\src\nu_ssmcc.c + + + nu_qei.c + 1 + ..\libraries\ma35\StdDriver\src\nu_qei.c + + + nu_qspi.c + 1 + ..\libraries\ma35\StdDriver\src\nu_qspi.c + + + nu_canfd.c + 1 + ..\libraries\ma35\StdDriver\src\nu_canfd.c + + + nu_gpio.c + 1 + ..\libraries\ma35\StdDriver\src\nu_gpio.c + + + nu_sspcc.c + 1 + ..\libraries\ma35\StdDriver\src\nu_sspcc.c + + + nu_timer_pwm.c + 1 + ..\libraries\ma35\StdDriver\src\nu_timer_pwm.c + + + nu_ecap.c + 1 + ..\libraries\ma35\StdDriver\src\nu_ecap.c + + + nu_disp.c + 1 + ..\libraries\ma35\StdDriver\src\nu_disp.c + + + nu_whc.c + 1 + ..\libraries\ma35\StdDriver\src\nu_whc.c + + + + + UTest + + + utest.c + 1 + ..\..\..\components\utilities\utest\utest.c + + + + + utestcases + + + utest_template.c + 1 + test\template\utest_template.c + + + mem_tc.c + 1 + ..\..\..\examples\utest\testcases\kernel\mem_tc.c + + + pass_tc.c + 1 + ..\..\..\examples\utest\testcases\utest\pass_tc.c + + + + + Utilities + + + ulog.c + 1 + ..\..\..\components\utilities\ulog\ulog.c + + + console_be.c + 1 + ..\..\..\components\utilities\ulog\backend\console_be.c + + + + + + + + + + + + + + diff --git a/bsp/nuvoton/ma35-rtp/rtconfig.py b/bsp/nuvoton/ma35-rtp/rtconfig.py new file mode 100644 index 0000000000..24f0a64fc5 --- /dev/null +++ b/bsp/nuvoton/ma35-rtp/rtconfig.py @@ -0,0 +1,99 @@ +import os + +# toolchains options +ARCH='arm' +CPU='cortex-m4' +CROSS_TOOL='gcc' + +if os.getenv('RTT_CC'): + CROSS_TOOL = os.getenv('RTT_CC') +if os.getenv('RTT_ROOT'): + RTT_ROOT = os.getenv('RTT_ROOT') + +# cross_tool provides the cross compiler +# EXEC_PATH is the compiler execute path, for example, CodeSourcery, Keil MDK, IAR + +if CROSS_TOOL == 'gcc': + PLATFORM = 'gcc' + EXEC_PATH = r'C:\Program Files (x86)\GNU Tools ARM Embedded\6 2017-q1-update\bin' +elif CROSS_TOOL == 'keil': + PLATFORM = 'armcc' + EXEC_PATH = r'C:\Keil_v5' + +if os.getenv('RTT_EXEC_PATH'): + EXEC_PATH = os.getenv('RTT_EXEC_PATH') + +BUILD = '' +# BUILD = 'debug' + + +if PLATFORM == 'gcc': + # toolchains + + PREFIX = 'arm-none-eabi-' + CC = PREFIX + 'gcc' + AS = PREFIX + 'gcc' + AR = PREFIX + 'ar' + CXX = PREFIX + 'g++' + LINK = PREFIX + 'gcc' + TARGET_EXT = 'elf' + SIZE = PREFIX + 'size' + OBJDUMP = PREFIX + 'objdump' + OBJCPY = PREFIX + 'objcopy' + + DEVICE = ' -mcpu=cortex-m4 -mthumb -ffunction-sections -fdata-sections -Wuninitialized' + + if BUILD == 'debug': + DEVICE = DEVICE + ' -DDEBUG' + + CFLAGS = DEVICE + AFLAGS = ' -c' + DEVICE + ' -x assembler-with-cpp' + LFLAGS = DEVICE + ' -nostartfiles -Wl,--gc-sections,-Map=rtthread.map -T ./linking_scripts/subm.ld ' + + CPATH = '' + LPATH = '' + + if BUILD == 'debug': + CFLAGS += ' -O0 -gdwarf-2 -g' + AFLAGS += ' -gdwarf-2' + else: + CFLAGS += ' -O2' + AFLAGS += ' -gdwarf-2' + + CXXFLAGS = CFLAGS + + POST_ACTION = OBJCPY + ' -O binary $TARGET rtthread.bin\n' + SIZE + ' $TARGET \n' + +elif PLATFORM == 'armcc': + # toolchains + CC = 'armcc' + AS = 'armasm' + AR = 'armar' + LINK = 'armlink' + TARGET_EXT = 'axf' + + DEVICE = ' --cpu=cortex-m4.fp' + CFLAGS = DEVICE + ' --apcs=interwork' + AFLAGS = DEVICE + LFLAGS = DEVICE + ' --info sizes --info totals --info unused --info veneers --list rtthread.map' + + CFLAGS += ' --c99' + CFLAGS += ' -I' + EXEC_PATH + '/ARM/RV31/INC' + LFLAGS += ' --libpath ' + EXEC_PATH + '/ARM/RV31/LIB' + + EXEC_PATH += '/arm/bin40/' + + if BUILD == 'debug': + CFLAGS += ' -g -O0' + AFLAGS += ' -g' + else: + CFLAGS += ' -O2' + + POST_ACTION = 'fromelf --bin $TARGET --output rtthread.bin \nfromelf -z $TARGET' + +def dist_handle(BSP_ROOT, dist_dir): + import sys + cwd_path = os.getcwd() + sys.path.append(os.path.join(os.path.dirname(BSP_ROOT), 'tools')) + from sdk_dist import dist_do_building + dist_do_building(BSP_ROOT, dist_dir) diff --git a/bsp/nuvoton/ma35-rtp/rtthread.bin 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z4D+A(UJg4I=3#t0(gd~}CL8NRH|#SoUD&6XxD&VuGj2L#?Kl+~g73K-p*stmrW?WO z#z6}4RSV#?1m_3P+}D7_78vtS7+btl0MBFW!=Ews7W|IETz>QF4gr4QFl=6x@aRm& zx~4JqHOy-8*WV>F_Ma&0VVEzY&^Itnm?4k literal 0 HcmV?d00001 diff --git a/bsp/nuvoton/ma35-rtp/template.uvprojx b/bsp/nuvoton/ma35-rtp/template.uvprojx new file mode 100644 index 0000000000..870e6b8fc9 --- /dev/null +++ b/bsp/nuvoton/ma35-rtp/template.uvprojx @@ -0,0 +1,390 @@ + + + + 2.1 + +
### uVision Project, (C) Keil Software
+ + + + rtthread-rtp + 0x4 + ARM-ADS + 5060750::V5.06 update 6 (build 750)::ARMCC + 0 + + + ARMCM4_FP + ARM + ARM.CMSIS.5.7.0 + http://www.keil.com/pack/ + IRAM(0x20000000,0x00020000) IROM(0x00000000,0x00040000) CPUTYPE("Cortex-M4") FPU2 CLOCK(12000000) ESEL ELITTLE + + + UL2CM3(-S0 -C0 -P0 -FD20000000 -FC1000) + 0 + $$Device:ARMCM4_FP$Device\ARM\ARMCM4\Include\ARMCM4_FP.h + + + + + + + + + + + 0 + 0 + + + + + + + 0 + 0 + 0 + 0 + 1 + + .\build\keil5\ + rtthread + 1 + 0 + 1 + 1 + 0 + .\build\keil5\ + 1 + 0 + 0 + + 0 + 0 + + + 0 + 0 + 0 + 0 + + + 0 + 0 + + + 0 + 0 + 0 + 0 + + + 1 + 1 + fromelf.exe --bin --output "$L@L.bin" "$L@L.axf" + fromelf --text -c "$L@L.axf" --output "$L@L.txt" + 0 + 0 + 0 + 0 + + 1 + + + + 0 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 3 + + + 1 + + + SARMCM3.DLL + -MPU + DCM.DLL + -pCM4 + SARMCM3.DLL + -MPU + TCM.DLL + -pCM4 + + + + 1 + 0 + 0 + 0 + 16 + + + + + 1 + 0 + 0 + 1 + 1 + 4099 + + 1 + BIN\UL2CM3.DLL + + + + + + 0 + + + + 0 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 1 + 1 + 0 + 1 + 1 + 0 + 0 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 1 + "Cortex-M4" + + 0 + 0 + 0 + 1 + 1 + 0 + 0 + 2 + 0 + 0 + 0 + 8 + 0 + 1 + 0 + 0 + 3 + 3 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 1 + 0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x20000000 + 0x20000 + + + 1 + 0x0 + 0x40000 + + + 0 + 0x0 + 0x0 + + + 1 + 0x0 + 0x0 + + + 1 + 0x0 + 0x0 + + + 1 + 0x0 + 0x0 + + + 1 + 0x0 + 0x40000 + + + 1 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x20000000 + 0x20000 + + + 0 + 0x0 + 0x0 + + + + + + 1 + 3 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 2 + 0 + 0 + 0 + 1 + 0 + 1 + 1 + 1 + 1 + 0 + 0 + 0 + + + + + + + + + 1 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + + + + + + + + + 0 + 0 + 0 + 0 + 1 + 0 + 0x00000000 + + + + + + + + + + + + + + + + + + + + + diff --git a/bsp/nuvoton/nk-n9h30/.config b/bsp/nuvoton/nk-n9h30/.config index 12bf2e1afd..a8fdd9106b 100644 --- a/bsp/nuvoton/nk-n9h30/.config +++ b/bsp/nuvoton/nk-n9h30/.config @@ -971,3 +971,5 @@ CONFIG_NU_PKG_USING_NAU8822=y CONFIG_NU_PKG_USING_ADC_TOUCH=y # CONFIG_NU_PKG_USING_ADC_TOUCH_SW is not set # CONFIG_NU_PKG_USING_SPINAND is not set +CONFIG_UTEST_CMD_PREFIX="bsp.nuvoton.utest." +CONFIG_BOARD_USE_UTEST=y diff --git a/bsp/nuvoton/numaker-hmi-ma35d1/.config b/bsp/nuvoton/numaker-hmi-ma35d1/.config new file mode 100644 index 0000000000..5cf42f36ff --- /dev/null +++ b/bsp/nuvoton/numaker-hmi-ma35d1/.config @@ -0,0 +1,1071 @@ +# +# Automatically generated file; DO NOT EDIT. +# RT-Thread Configuration +# +CONFIG_USE_MA35D1_AARCH32=y + +# +# RT-Thread Kernel +# +CONFIG_RT_NAME_MAX=8 +# CONFIG_RT_USING_ARCH_DATA_TYPE is not set +CONFIG_RT_USING_SMP=y +CONFIG_RT_CPUS_NR=2 +CONFIG_RT_ALIGN_SIZE=32 +# CONFIG_RT_THREAD_PRIORITY_8 is not set +CONFIG_RT_THREAD_PRIORITY_32=y +# CONFIG_RT_THREAD_PRIORITY_256 is not set +CONFIG_RT_THREAD_PRIORITY_MAX=32 +CONFIG_RT_TICK_PER_SECOND=1000 +CONFIG_RT_USING_OVERFLOW_CHECK=y +CONFIG_RT_USING_HOOK=y +CONFIG_RT_HOOK_USING_FUNC_PTR=y +CONFIG_RT_USING_IDLE_HOOK=y +CONFIG_RT_IDLE_HOOK_LIST_SIZE=4 +CONFIG_IDLE_THREAD_STACK_SIZE=4096 +CONFIG_SYSTEM_THREAD_STACK_SIZE=4096 +CONFIG_RT_USING_TIMER_SOFT=y +CONFIG_RT_TIMER_THREAD_PRIO=4 +CONFIG_RT_TIMER_THREAD_STACK_SIZE=4096 + +# +# kservice optimization +# +CONFIG_RT_KSERVICE_USING_STDLIB=y +# CONFIG_RT_KSERVICE_USING_STDLIB_MEMORY is not set +# CONFIG_RT_KSERVICE_USING_TINY_SIZE is not set +# CONFIG_RT_USING_TINY_FFS is not set +# CONFIG_RT_KPRINTF_USING_LONGLONG is not set +CONFIG_RT_DEBUG=y +CONFIG_RT_DEBUG_COLOR=y +# CONFIG_RT_DEBUG_INIT_CONFIG is not set +# CONFIG_RT_DEBUG_THREAD_CONFIG is not set +# CONFIG_RT_DEBUG_SCHEDULER_CONFIG is not set +# CONFIG_RT_DEBUG_IPC_CONFIG is not set +# CONFIG_RT_DEBUG_TIMER_CONFIG is not set +# CONFIG_RT_DEBUG_IRQ_CONFIG is not set +# CONFIG_RT_DEBUG_MEM_CONFIG is not set +# CONFIG_RT_DEBUG_SLAB_CONFIG is not set +# CONFIG_RT_DEBUG_MEMHEAP_CONFIG is not set +# CONFIG_RT_DEBUG_MODULE_CONFIG is not set + +# +# Inter-Thread communication +# +CONFIG_RT_USING_SEMAPHORE=y +CONFIG_RT_USING_MUTEX=y +CONFIG_RT_USING_EVENT=y +CONFIG_RT_USING_MAILBOX=y +CONFIG_RT_USING_MESSAGEQUEUE=y +# CONFIG_RT_USING_SIGNALS is not set + +# +# Memory Management +# +CONFIG_RT_USING_MEMPOOL=y +CONFIG_RT_USING_SMALL_MEM=y +# CONFIG_RT_USING_SLAB is not set +CONFIG_RT_USING_MEMHEAP=y +CONFIG_RT_MEMHEAP_FAST_MODE=y +# CONFIG_RT_MEMHEAP_BSET_MODE is not set +CONFIG_RT_USING_SMALL_MEM_AS_HEAP=y +# CONFIG_RT_USING_MEMHEAP_AS_HEAP is not set +# CONFIG_RT_USING_SLAB_AS_HEAP is not set +# CONFIG_RT_USING_USERHEAP is not set +# CONFIG_RT_USING_NOHEAP is not set +# CONFIG_RT_USING_MEMTRACE is not set +# CONFIG_RT_USING_HEAP_ISR is not set +CONFIG_RT_USING_HEAP=y + +# +# Kernel Device Object +# +CONFIG_RT_USING_DEVICE=y +# CONFIG_RT_USING_DEVICE_OPS is not set +CONFIG_RT_USING_INTERRUPT_INFO=y +CONFIG_RT_USING_CONSOLE=y +CONFIG_RT_CONSOLEBUF_SIZE=4096 +CONFIG_RT_CONSOLE_DEVICE_NAME="uart0" +CONFIG_RT_VER_NUM=0x50000 +CONFIG_ARCH_ARM=y +CONFIG_RT_USING_CPU_FFS=y +CONFIG_ARCH_ARM_CORTEX_A=y +CONFIG_RT_SMP_AUTO_BOOT=y +CONFIG_RT_USING_GIC_V2=y +# CONFIG_RT_USING_GIC_V3 is not set +CONFIG_ARCH_ARMV8=y +# CONFIG_ARCH_CPU_STACK_GROWS_UPWARD is not set + +# +# RT-Thread Components +# +CONFIG_RT_USING_COMPONENTS_INIT=y +CONFIG_RT_USING_USER_MAIN=y +CONFIG_RT_MAIN_THREAD_STACK_SIZE=4096 +CONFIG_RT_MAIN_THREAD_PRIORITY=10 +CONFIG_RT_USING_LEGACY=y +CONFIG_RT_USING_MSH=y +CONFIG_RT_USING_FINSH=y +CONFIG_FINSH_USING_MSH=y +CONFIG_FINSH_THREAD_NAME="tshell" +CONFIG_FINSH_THREAD_PRIORITY=20 +CONFIG_FINSH_THREAD_STACK_SIZE=4096 +CONFIG_FINSH_USING_HISTORY=y +CONFIG_FINSH_HISTORY_LINES=5 +CONFIG_FINSH_USING_SYMTAB=y +CONFIG_FINSH_CMD_SIZE=128 +CONFIG_MSH_USING_BUILT_IN_COMMANDS=y +CONFIG_FINSH_USING_DESCRIPTION=y +# CONFIG_FINSH_ECHO_DISABLE_DEFAULT is not set +# CONFIG_FINSH_USING_AUTH is not set +CONFIG_FINSH_ARG_MAX=10 +CONFIG_RT_USING_DFS=y +CONFIG_DFS_USING_POSIX=y +CONFIG_DFS_USING_WORKDIR=y +CONFIG_DFS_FILESYSTEMS_MAX=32 +CONFIG_DFS_FILESYSTEM_TYPES_MAX=32 +CONFIG_DFS_FD_MAX=128 +CONFIG_RT_USING_DFS_MNTTABLE=y +CONFIG_RT_USING_DFS_ELMFAT=y + +# +# elm-chan's FatFs, Generic FAT Filesystem Module +# +CONFIG_RT_DFS_ELM_CODE_PAGE=437 +CONFIG_RT_DFS_ELM_WORD_ACCESS=y +# CONFIG_RT_DFS_ELM_USE_LFN_0 is not set +# CONFIG_RT_DFS_ELM_USE_LFN_1 is not set +# CONFIG_RT_DFS_ELM_USE_LFN_2 is not set +CONFIG_RT_DFS_ELM_USE_LFN_3=y +CONFIG_RT_DFS_ELM_USE_LFN=3 +CONFIG_RT_DFS_ELM_LFN_UNICODE_0=y +# CONFIG_RT_DFS_ELM_LFN_UNICODE_1 is not set +# CONFIG_RT_DFS_ELM_LFN_UNICODE_2 is not set +# CONFIG_RT_DFS_ELM_LFN_UNICODE_3 is not set +CONFIG_RT_DFS_ELM_LFN_UNICODE=0 +CONFIG_RT_DFS_ELM_MAX_LFN=255 +CONFIG_RT_DFS_ELM_DRIVES=8 +CONFIG_RT_DFS_ELM_MAX_SECTOR_SIZE=512 +# CONFIG_RT_DFS_ELM_USE_ERASE is not set +CONFIG_RT_DFS_ELM_REENTRANT=y +CONFIG_RT_DFS_ELM_MUTEX_TIMEOUT=3000 +CONFIG_RT_USING_DFS_DEVFS=y +# CONFIG_RT_USING_DFS_ROMFS is not set +# CONFIG_RT_USING_DFS_RAMFS is not set +# CONFIG_RT_USING_DFS_NFS is not set +# CONFIG_RT_USING_FAL is not set +# CONFIG_RT_USING_LWP is not set + +# +# Device Drivers +# +CONFIG_RT_USING_DEVICE_IPC=y +CONFIG_RT_USING_SYSTEM_WORKQUEUE=y +CONFIG_RT_SYSTEM_WORKQUEUE_STACKSIZE=2048 +CONFIG_RT_SYSTEM_WORKQUEUE_PRIORITY=23 +CONFIG_RT_USING_SERIAL=y +CONFIG_RT_USING_SERIAL_V1=y +# CONFIG_RT_USING_SERIAL_V2 is not set +CONFIG_RT_SERIAL_USING_DMA=y +CONFIG_RT_SERIAL_RB_BUFSZ=256 +# CONFIG_RT_USING_CAN is not set +# CONFIG_RT_USING_HWTIMER is not set +# CONFIG_RT_USING_CPUTIME is not set +CONFIG_RT_USING_I2C=y +# CONFIG_RT_I2C_DEBUG is not set +CONFIG_RT_USING_I2C_BITOPS=y +# CONFIG_RT_I2C_BITOPS_DEBUG is not set +# CONFIG_RT_USING_PHY is not set +CONFIG_RT_USING_PIN=y +CONFIG_RT_USING_ADC=y +# CONFIG_RT_USING_DAC is not set +CONFIG_RT_USING_PWM=y +# CONFIG_RT_USING_MTD_NOR is not set +CONFIG_RT_USING_MTD_NAND=y +CONFIG_RT_MTD_NAND_DEBUG=y +# CONFIG_RT_USING_PM is not set +CONFIG_RT_USING_RTC=y +# CONFIG_RT_USING_ALARM is not set +# CONFIG_RT_USING_SOFT_RTC is not set +CONFIG_RT_USING_SDIO=y +CONFIG_RT_SDIO_STACK_SIZE=4096 +CONFIG_RT_SDIO_THREAD_PRIORITY=15 +CONFIG_RT_MMCSD_STACK_SIZE=4096 +CONFIG_RT_MMCSD_THREAD_PREORITY=22 +CONFIG_RT_MMCSD_MAX_PARTITION=8 +# CONFIG_RT_SDIO_DEBUG is not set +CONFIG_RT_USING_SPI=y +# CONFIG_RT_USING_SPI_BITOPS is not set +CONFIG_RT_USING_QSPI=y +# CONFIG_RT_USING_SPI_MSD is not set +# CONFIG_RT_USING_SFUD is not set +# CONFIG_RT_USING_ENC28J60 is not set +# CONFIG_RT_USING_SPI_WIFI is not set +# CONFIG_RT_USING_WDT is not set +CONFIG_RT_USING_AUDIO=y +CONFIG_RT_AUDIO_REPLAY_MP_BLOCK_SIZE=4096 +CONFIG_RT_AUDIO_REPLAY_MP_BLOCK_COUNT=2 +CONFIG_RT_AUDIO_RECORD_PIPE_SIZE=2048 +# CONFIG_RT_USING_SENSOR is not set +CONFIG_RT_USING_TOUCH=y +# CONFIG_RT_TOUCH_PIN_IRQ is not set +# CONFIG_RT_USING_HWCRYPTO is not set +# CONFIG_RT_USING_PULSE_ENCODER is not set +# CONFIG_RT_USING_INPUT_CAPTURE is not set +# CONFIG_RT_USING_WIFI is not set + +# +# Using USB +# +CONFIG_RT_USING_USB=y +CONFIG_RT_USING_USB_HOST=y +CONFIG_RT_USBH_MSTORAGE=y +CONFIG_UDISK_MOUNTPOINT="/mnt/udisk" +# CONFIG_RT_USBH_HID is not set +# CONFIG_RT_USING_USB_DEVICE is not set +CONFIG_RT_USBD_THREAD_STACK_SZ=4096 + +# +# C/C++ and POSIX layer +# +CONFIG_RT_LIBC_DEFAULT_TIMEZONE=8 + +# +# POSIX (Portable Operating System Interface) layer +# +CONFIG_RT_USING_POSIX_FS=y +# CONFIG_RT_USING_POSIX_DEVIO is not set +# CONFIG_RT_USING_POSIX_STDIO is not set +CONFIG_RT_USING_POSIX_POLL=y +CONFIG_RT_USING_POSIX_SELECT=y +CONFIG_RT_USING_POSIX_SOCKET=y +# CONFIG_RT_USING_POSIX_TERMIOS is not set +# CONFIG_RT_USING_POSIX_AIO is not set +# CONFIG_RT_USING_POSIX_MMAN is not set +CONFIG_RT_USING_POSIX_DELAY=y +CONFIG_RT_USING_POSIX_CLOCK=y +# CONFIG_RT_USING_POSIX_TIMER is not set +CONFIG_RT_USING_PTHREADS=y +CONFIG_PTHREAD_NUM_MAX=8 +CONFIG_RT_USING_MODULE=y +CONFIG_RT_USING_CUSTOM_DLMODULE=y + +# +# Interprocess Communication (IPC) +# +# CONFIG_RT_USING_POSIX_PIPE is not set +# CONFIG_RT_USING_POSIX_MESSAGE_QUEUE is not set +# CONFIG_RT_USING_POSIX_MESSAGE_SEMAPHORE is not set + +# +# Socket is in the 'Network' category +# +# CONFIG_RT_USING_CPLUSPLUS is not set + +# +# Network +# +CONFIG_RT_USING_SAL=y +# CONFIG_SAL_INTERNET_CHECK is not set + +# +# Docking with protocol stacks +# +CONFIG_SAL_USING_LWIP=y +# CONFIG_SAL_USING_AT is not set +# CONFIG_SAL_USING_TLS is not set +CONFIG_SAL_USING_POSIX=y +CONFIG_RT_USING_NETDEV=y +CONFIG_NETDEV_USING_IFCONFIG=y +CONFIG_NETDEV_USING_PING=y +CONFIG_NETDEV_USING_NETSTAT=y +CONFIG_NETDEV_USING_AUTO_DEFAULT=y +# CONFIG_NETDEV_USING_IPV6 is not set +CONFIG_NETDEV_IPV4=1 +CONFIG_NETDEV_IPV6=0 +# CONFIG_NETDEV_IPV6_SCOPES is not set +CONFIG_RT_USING_LWIP=y +# CONFIG_RT_USING_LWIP_LOCAL_VERSION is not set +# CONFIG_RT_USING_LWIP141 is not set +# CONFIG_RT_USING_LWIP203 is not set +CONFIG_RT_USING_LWIP212=y +# CONFIG_RT_USING_LWIP_LATEST is not set +CONFIG_RT_USING_LWIP_VER_NUM=0x20102 +# CONFIG_RT_USING_LWIP_IPV6 is not set +CONFIG_RT_LWIP_MEM_ALIGNMENT=32 +CONFIG_RT_LWIP_IGMP=y +CONFIG_RT_LWIP_ICMP=y +# CONFIG_RT_LWIP_SNMP is not set +CONFIG_RT_LWIP_DNS=y +CONFIG_RT_LWIP_DHCP=y +CONFIG_IP_SOF_BROADCAST=1 +CONFIG_IP_SOF_BROADCAST_RECV=1 + +# +# Static IPv4 Address +# +CONFIG_RT_LWIP_IPADDR="192.168.31.55" +CONFIG_RT_LWIP_GWADDR="192.168.31.1" +CONFIG_RT_LWIP_MSKADDR="255.255.255.0" +CONFIG_RT_LWIP_UDP=y +CONFIG_RT_LWIP_TCP=y +CONFIG_RT_LWIP_RAW=y +# CONFIG_RT_LWIP_PPP is not set +CONFIG_RT_MEMP_NUM_NETCONN=32 +CONFIG_RT_LWIP_PBUF_NUM=8192 +CONFIG_RT_LWIP_RAW_PCB_NUM=32 +CONFIG_RT_LWIP_UDP_PCB_NUM=32 +CONFIG_RT_LWIP_TCP_PCB_NUM=32 +CONFIG_RT_LWIP_TCP_SEG_NUM=1024 +CONFIG_RT_LWIP_TCP_SND_BUF=8192 +CONFIG_RT_LWIP_TCP_WND=10240 +CONFIG_RT_LWIP_TCPTHREAD_PRIORITY=10 +CONFIG_RT_LWIP_TCPTHREAD_MBOX_SIZE=8192 +CONFIG_RT_LWIP_TCPTHREAD_STACKSIZE=4096 +# CONFIG_LWIP_NO_RX_THREAD is not set +# CONFIG_LWIP_NO_TX_THREAD is not set +CONFIG_RT_LWIP_ETHTHREAD_PRIORITY=12 +CONFIG_RT_LWIP_ETHTHREAD_STACKSIZE=4096 +CONFIG_RT_LWIP_ETHTHREAD_MBOX_SIZE=8192 +CONFIG_RT_LWIP_REASSEMBLY_FRAG=y +CONFIG_LWIP_NETIF_STATUS_CALLBACK=1 +CONFIG_LWIP_NETIF_LINK_CALLBACK=1 +CONFIG_SO_REUSE=1 +CONFIG_LWIP_SO_RCVTIMEO=1 +CONFIG_LWIP_SO_SNDTIMEO=1 +CONFIG_LWIP_SO_RCVBUF=1 +CONFIG_LWIP_SO_LINGER=0 +CONFIG_RT_LWIP_NETIF_LOOPBACK=y +CONFIG_LWIP_NETIF_LOOPBACK=1 +CONFIG_RT_LWIP_STATS=y +CONFIG_RT_LWIP_USING_HW_CHECKSUM=y +CONFIG_RT_LWIP_USING_PING=y +# CONFIG_LWIP_USING_DHCPD is not set +# CONFIG_RT_LWIP_DEBUG is not set +# CONFIG_RT_USING_AT is not set + +# +# Utilities +# +# CONFIG_RT_USING_RYM is not set +CONFIG_RT_USING_ULOG=y +# CONFIG_ULOG_OUTPUT_LVL_A is not set +# CONFIG_ULOG_OUTPUT_LVL_E is not set +# CONFIG_ULOG_OUTPUT_LVL_W is not set +# CONFIG_ULOG_OUTPUT_LVL_I is not set +CONFIG_ULOG_OUTPUT_LVL_D=y +CONFIG_ULOG_OUTPUT_LVL=7 +CONFIG_ULOG_USING_ISR_LOG=y +CONFIG_ULOG_ASSERT_ENABLE=y +CONFIG_ULOG_LINE_BUF_SIZE=128 +# CONFIG_ULOG_USING_ASYNC_OUTPUT is not set + +# +# log format +# +# CONFIG_ULOG_OUTPUT_FLOAT is not set +CONFIG_ULOG_USING_COLOR=y +CONFIG_ULOG_OUTPUT_TIME=y +# CONFIG_ULOG_TIME_USING_TIMESTAMP is not set +CONFIG_ULOG_OUTPUT_LEVEL=y +CONFIG_ULOG_OUTPUT_TAG=y +# CONFIG_ULOG_OUTPUT_THREAD_NAME is not set +CONFIG_ULOG_BACKEND_USING_CONSOLE=y +# CONFIG_ULOG_BACKEND_USING_FILE is not set +# CONFIG_ULOG_USING_FILTER is not set +# CONFIG_ULOG_USING_SYSLOG is not set +CONFIG_RT_USING_UTEST=y +CONFIG_UTEST_THR_STACK_SIZE=4096 +CONFIG_UTEST_THR_PRIORITY=20 +# CONFIG_RT_USING_VAR_EXPORT is not set +# CONFIG_RT_USING_RT_LINK is not set +# CONFIG_RT_USING_VBUS is not set + +# +# RT-Thread Utestcases +# +CONFIG_RT_USING_UTESTCASES=y + +# +# Utest Self Testcase +# +CONFIG_UTEST_SELF_PASS_TC=y + +# +# Kernel Testcase +# +CONFIG_UTEST_MEMHEAP_TC=y +CONFIG_UTEST_SMALL_MEM_TC=y +# CONFIG_UTEST_IRQ_TC is not set +# CONFIG_UTEST_SEMAPHORE_TC is not set +# CONFIG_UTEST_EVENT_TC is not set +# CONFIG_UTEST_TIMER_TC is not set +# CONFIG_UTEST_MESSAGEQUEUE_TC is not set +# CONFIG_UTEST_SIGNAL_TC is not set +# CONFIG_UTEST_MUTEX_TC is not set +# CONFIG_UTEST_MAILBOX_TC is not set +# CONFIG_UTEST_THREAD_TC is not set + +# +# CPP11 Testcase +# +# CONFIG_UTEST_CPP11_THREAD_TC is not set + +# +# Utest Serial Testcase +# +# CONFIG_UTEST_SERIAL_TC is not set + +# +# RTT Posix Testcase +# +# CONFIG_RTT_POSIX_TESTCASE is not set + +# +# RT-Thread online packages +# + +# +# IoT - internet of things +# +# CONFIG_PKG_USING_LWIP is not set +# CONFIG_PKG_USING_LORAWAN_DRIVER is not set +# CONFIG_PKG_USING_PAHOMQTT is not set +# CONFIG_PKG_USING_UMQTT is not set +# CONFIG_PKG_USING_WEBCLIENT is not set +# CONFIG_PKG_USING_WEBNET is not set +# CONFIG_PKG_USING_MONGOOSE is not set +# CONFIG_PKG_USING_MYMQTT is not set +# CONFIG_PKG_USING_KAWAII_MQTT is not set +# CONFIG_PKG_USING_BC28_MQTT is not set +# CONFIG_PKG_USING_WEBTERMINAL is not set +# CONFIG_PKG_USING_LIBMODBUS is not set +# CONFIG_PKG_USING_FREEMODBUS is not set +# CONFIG_PKG_USING_NANOPB is not set + +# +# Wi-Fi +# + +# +# Marvell WiFi +# +# CONFIG_PKG_USING_WLANMARVELL is not set + +# +# Wiced WiFi +# +# CONFIG_PKG_USING_WLAN_WICED is not set +# CONFIG_PKG_USING_RW007 is not set +# CONFIG_PKG_USING_COAP is not set +# CONFIG_PKG_USING_NOPOLL is not set +# CONFIG_PKG_USING_NETUTILS is not set +# CONFIG_PKG_USING_CMUX is not set +# CONFIG_PKG_USING_PPP_DEVICE is not set +# CONFIG_PKG_USING_AT_DEVICE is not set +# CONFIG_PKG_USING_ATSRV_SOCKET is not set +# CONFIG_PKG_USING_WIZNET is not set +# CONFIG_PKG_USING_ZB_COORDINATOR is not set + +# +# IoT Cloud +# +# CONFIG_PKG_USING_ONENET is not set +# CONFIG_PKG_USING_GAGENT_CLOUD is not set +# CONFIG_PKG_USING_ALI_IOTKIT is not set +# CONFIG_PKG_USING_AZURE is not set +# CONFIG_PKG_USING_TENCENT_IOT_EXPLORER is not set +# CONFIG_PKG_USING_JIOT-C-SDK is not set +# CONFIG_PKG_USING_UCLOUD_IOT_SDK is not set +# CONFIG_PKG_USING_JOYLINK is not set +# CONFIG_PKG_USING_EZ_IOT_OS is not set +# CONFIG_PKG_USING_IOTSHARP_SDK is not set +# CONFIG_PKG_USING_NIMBLE is not set +# CONFIG_PKG_USING_LLSYNC_SDK_ADAPTER is not set +# CONFIG_PKG_USING_OTA_DOWNLOADER is not set +# CONFIG_PKG_USING_IPMSG is not set +# CONFIG_PKG_USING_LSSDP is not set +# CONFIG_PKG_USING_AIRKISS_OPEN is not set +# CONFIG_PKG_USING_LIBRWS is not set +# CONFIG_PKG_USING_TCPSERVER is not set +# CONFIG_PKG_USING_PROTOBUF_C is not set +# CONFIG_PKG_USING_DLT645 is not set +# CONFIG_PKG_USING_QXWZ is not set +# CONFIG_PKG_USING_SMTP_CLIENT is not set +# CONFIG_PKG_USING_ABUP_FOTA is not set +# CONFIG_PKG_USING_LIBCURL2RTT is not set +# CONFIG_PKG_USING_CAPNP is not set +# CONFIG_PKG_USING_AGILE_TELNET is not set +# CONFIG_PKG_USING_NMEALIB is not set +# CONFIG_PKG_USING_PDULIB is not set +# CONFIG_PKG_USING_BTSTACK is not set +# CONFIG_PKG_USING_LORAWAN_ED_STACK is not set +# CONFIG_PKG_USING_WAYZ_IOTKIT is not set +# CONFIG_PKG_USING_MAVLINK is not set +# CONFIG_PKG_USING_BSAL is not set +# CONFIG_PKG_USING_AGILE_MODBUS is not set +# CONFIG_PKG_USING_AGILE_FTP is not set +# CONFIG_PKG_USING_EMBEDDEDPROTO is not set +# CONFIG_PKG_USING_RT_LINK_HW is not set +# CONFIG_PKG_USING_LORA_PKT_FWD is not set +# CONFIG_PKG_USING_LORA_GW_DRIVER_LIB is not set +# CONFIG_PKG_USING_LORA_PKT_SNIFFER is not set +# CONFIG_PKG_USING_HM is not set +# CONFIG_PKG_USING_SMALL_MODBUS is not set +# CONFIG_PKG_USING_NET_SERVER is not set +# CONFIG_PKG_USING_ZFTP is not set + +# +# security packages +# +# CONFIG_PKG_USING_MBEDTLS is not set +# CONFIG_PKG_USING_LIBSODIUM is not set +# CONFIG_PKG_USING_LIBHYDROGEN is not set +# CONFIG_PKG_USING_TINYCRYPT is not set +# CONFIG_PKG_USING_TFM is not set +# CONFIG_PKG_USING_YD_CRYPTO is not set + +# +# language packages +# + +# +# JSON: JavaScript Object Notation, a lightweight data-interchange format +# +# CONFIG_PKG_USING_CJSON is not set +# CONFIG_PKG_USING_LJSON is not set +# CONFIG_PKG_USING_RT_CJSON_TOOLS is not set +# CONFIG_PKG_USING_RAPIDJSON is not set +# CONFIG_PKG_USING_JSMN is not set +# CONFIG_PKG_USING_AGILE_JSMN is not set +# CONFIG_PKG_USING_PARSON is not set + +# +# XML: Extensible Markup Language +# +# CONFIG_PKG_USING_SIMPLE_XML is not set +# CONFIG_PKG_USING_EZXML is not set +# CONFIG_PKG_USING_LUATOS_SOC is not set +# CONFIG_PKG_USING_LUA is not set +# CONFIG_PKG_USING_JERRYSCRIPT is not set +# CONFIG_PKG_USING_MICROPYTHON is not set +# CONFIG_PKG_USING_PIKASCRIPT is not set +# CONFIG_PKG_USING_RTT_RUST is not set + +# +# multimedia packages +# + +# +# LVGL: powerful and easy-to-use embedded GUI library +# +CONFIG_PKG_USING_LVGL=y +CONFIG_PKG_LVGL_PATH="/packages/multimedia/LVGL/LVGL" +CONFIG_PKG_LVGL_THREAD_PRIO=20 +CONFIG_PKG_LVGL_THREAD_STACK_SIZE=4096 +CONFIG_PKG_LVGL_DISP_REFR_PERIOD=5 +# CONFIG_PKG_LVGL_USING_EXAMPLES is not set +CONFIG_PKG_LVGL_USING_DEMOS=y +# CONFIG_PKG_LVGL_USING_V08020 is not set +# CONFIG_PKG_LVGL_USING_V08030 is not set +CONFIG_PKG_LVGL_USING_LATEST_VERSION=y +CONFIG_PKG_LVGL_VER_NUM=0x99999 +CONFIG_PKG_LVGL_VER="latest" +# CONFIG_PKG_USING_LITTLEVGL2RTT is not set +# CONFIG_PKG_USING_LV_MUSIC_DEMO is not set +# CONFIG_PKG_USING_GUI_GUIDER_DEMO is not set + +# +# u8g2: a monochrome graphic library +# +# CONFIG_PKG_USING_U8G2_OFFICIAL is not set +# CONFIG_PKG_USING_U8G2 is not set +# CONFIG_PKG_USING_OPENMV is not set +# CONFIG_PKG_USING_MUPDF is not set +# CONFIG_PKG_USING_STEMWIN is not set +CONFIG_PKG_USING_WAVPLAYER=y +CONFIG_PKG_WAVPLAYER_PATH="/packages/multimedia/wavplayer" +CONFIG_PKG_WP_USING_PLAY=y +CONFIG_PKG_WP_PLAY_DEVICE="sound0" +CONFIG_PKG_WP_USING_RECORD=y +CONFIG_PKG_WP_RECORD_DEVICE="sound0" +# CONFIG_PKG_USING_WAVPLAYER_V020 is not set +CONFIG_PKG_USING_WAVPLAYER_LATEST_VERSION=y +CONFIG_PKG_WAVPLAYER_VER="latest" +# CONFIG_PKG_USING_TJPGD is not set +# CONFIG_PKG_USING_PDFGEN is not set +# CONFIG_PKG_USING_HELIX is not set +# CONFIG_PKG_USING_HELIX_V100 is not set +# CONFIG_PKG_USING_HELIX_LATEST_VERSION is not set +# CONFIG_PKG_USING_AZUREGUIX is not set +# CONFIG_PKG_USING_TOUCHGFX2RTT is not set +# CONFIG_PKG_USING_NUEMWIN is not set +# CONFIG_PKG_USING_MP3PLAYER is not set +# CONFIG_PKG_USING_MP3PLAYER_V100 is not set +# CONFIG_PKG_USING_MP3PLAYER_LATEST_VERSION is not set +# CONFIG_PKG_USING_TINYJPEG is not set +# CONFIG_PKG_USING_UGUI is not set + +# +# PainterEngine: A cross-platform graphics application framework written in C language +# +# CONFIG_PKG_USING_PAINTERENGINE is not set +# CONFIG_PKG_USING_PAINTERENGINE_AUX is not set +# CONFIG_PKG_USING_MCURSES is not set +# CONFIG_PKG_USING_TERMBOX is not set +# CONFIG_PKG_USING_VT100 is not set +# CONFIG_PKG_USING_QRCODE is not set +# CONFIG_PKG_USING_GUIENGINE is not set +# CONFIG_PKG_USING_PERSIMMON is not set + +# +# tools packages +# +# CONFIG_PKG_USING_CMBACKTRACE is not set +# CONFIG_PKG_USING_EASYFLASH is not set +# CONFIG_PKG_USING_EASYLOGGER is not set +# CONFIG_PKG_USING_SYSTEMVIEW is not set +# CONFIG_PKG_USING_SEGGER_RTT is not set +# CONFIG_PKG_USING_RDB is not set +# CONFIG_PKG_USING_ULOG_EASYFLASH is not set +# CONFIG_PKG_USING_ULOG_FILE is not set +# CONFIG_PKG_USING_LOGMGR is not set +# CONFIG_PKG_USING_ADBD is not set +# CONFIG_PKG_USING_COREMARK is not set +# CONFIG_PKG_USING_DHRYSTONE is not set +# CONFIG_PKG_USING_MEMORYPERF is not set +# CONFIG_PKG_USING_NR_MICRO_SHELL is not set +# CONFIG_PKG_USING_CHINESE_FONT_LIBRARY is not set +# CONFIG_PKG_USING_LUNAR_CALENDAR is not set +# CONFIG_PKG_USING_BS8116A is not set +# CONFIG_PKG_USING_GPS_RMC is not set +# CONFIG_PKG_USING_URLENCODE is not set +# CONFIG_PKG_USING_UMCN is not set +# CONFIG_PKG_USING_LWRB2RTT is not set +# CONFIG_PKG_USING_CPU_USAGE is not set +# CONFIG_PKG_USING_GBK2UTF8 is not set +# CONFIG_PKG_USING_VCONSOLE is not set +# CONFIG_PKG_USING_KDB is not set +# CONFIG_PKG_USING_WAMR is not set +# CONFIG_PKG_USING_MICRO_XRCE_DDS_CLIENT is not set +# CONFIG_PKG_USING_LWLOG is not set +# CONFIG_PKG_USING_ANV_TRACE is not set +# CONFIG_PKG_USING_ANV_MEMLEAK is not set +# CONFIG_PKG_USING_ANV_TESTSUIT is not set +# CONFIG_PKG_USING_ANV_BENCH is not set +# CONFIG_PKG_USING_DEVMEM is not set +# CONFIG_PKG_USING_REGEX is not set +# CONFIG_PKG_USING_MEM_SANDBOX is not set +# CONFIG_PKG_USING_SOLAR_TERMS is not set +# CONFIG_PKG_USING_GAN_ZHI is not set +# CONFIG_PKG_USING_FDT is not set +# CONFIG_PKG_USING_CBOX is not set +# CONFIG_PKG_USING_SNOWFLAKE is not set +# CONFIG_PKG_USING_HASH_MATCH is not set +# CONFIG_PKG_USING_FIRE_PID_CURVE is not set +# CONFIG_PKG_USING_ARMV7M_DWT_TOOL is not set + +# +# system packages +# + +# +# enhanced kernel services +# +# CONFIG_PKG_USING_RT_MEMCPY_CM is not set +# CONFIG_PKG_USING_RT_KPRINTF_THREADSAFE is not set +# CONFIG_PKG_USING_RT_VSNPRINTF_FULL is not set + +# +# acceleration: Assembly language or algorithmic acceleration packages +# +# CONFIG_PKG_USING_QFPLIB_M0_FULL is not set +# CONFIG_PKG_USING_QFPLIB_M0_TINY is not set +# CONFIG_PKG_USING_QFPLIB_M3 is not set + +# +# CMSIS: ARM Cortex-M Microcontroller Software Interface Standard +# +# CONFIG_PKG_USING_CMSIS_5 is not set +# CONFIG_PKG_USING_CMSIS_RTOS1 is not set +# CONFIG_PKG_USING_CMSIS_RTOS2 is not set + +# +# Micrium: Micrium software products porting for RT-Thread +# +# CONFIG_PKG_USING_UCOSIII_WRAPPER is not set +# CONFIG_PKG_USING_UCOSII_WRAPPER is not set +# CONFIG_PKG_USING_UC_CRC is not set +# CONFIG_PKG_USING_UC_CLK is not set +# CONFIG_PKG_USING_UC_COMMON is not set +# CONFIG_PKG_USING_UC_MODBUS is not set +# CONFIG_PKG_USING_RTDUINO is not set +# CONFIG_PKG_USING_FREERTOS_WRAPPER is not set +# CONFIG_PKG_USING_CAIRO is not set +# CONFIG_PKG_USING_PIXMAN is not set +# CONFIG_PKG_USING_PARTITION is not set +# CONFIG_PKG_USING_PERF_COUNTER is not set +# CONFIG_PKG_USING_FLASHDB is not set +# CONFIG_PKG_USING_SQLITE is not set +# CONFIG_PKG_USING_RTI is not set +# CONFIG_PKG_USING_DFS_YAFFS is not set +# CONFIG_PKG_USING_LITTLEFS is not set +# CONFIG_PKG_USING_DFS_JFFS2 is not set +# CONFIG_PKG_USING_DFS_UFFS is not set +# CONFIG_PKG_USING_LWEXT4 is not set +# CONFIG_PKG_USING_THREAD_POOL is not set +# CONFIG_PKG_USING_ROBOTS is not set +# CONFIG_PKG_USING_EV is not set +# CONFIG_PKG_USING_SYSWATCH is not set +# CONFIG_PKG_USING_SYS_LOAD_MONITOR is not set +# CONFIG_PKG_USING_PLCCORE is not set +CONFIG_PKG_USING_RAMDISK=y +CONFIG_PKG_RAMDISK_PATH="/packages/system/ramdisk" +# CONFIG_PKG_USING_RAMDISK_V010 is not set +CONFIG_PKG_USING_RAMDISK_LATEST_VERSION=y +CONFIG_PKG_RAMDISK_VER="latest" +# CONFIG_PKG_USING_MININI is not set +# CONFIG_PKG_USING_QBOOT is not set +# CONFIG_PKG_USING_PPOOL is not set +# CONFIG_PKG_USING_OPENAMP is not set +# CONFIG_PKG_USING_LPM is not set +# CONFIG_PKG_USING_TLSF is not set +# CONFIG_PKG_USING_EVENT_RECORDER is not set +# CONFIG_PKG_USING_ARM_2D is not set +# CONFIG_PKG_USING_MCUBOOT is not set +# CONFIG_PKG_USING_TINYUSB is not set +# CONFIG_PKG_USING_CHERRYUSB is not set +# CONFIG_PKG_USING_KMULTI_RTIMER is not set +# CONFIG_PKG_USING_TFDB is not set +# CONFIG_PKG_USING_QPC is not set + +# +# peripheral libraries and drivers +# +# CONFIG_PKG_USING_SENSORS_DRIVERS is not set +# CONFIG_PKG_USING_REALTEK_AMEBA is not set +# CONFIG_PKG_USING_SHT2X is not set +# CONFIG_PKG_USING_SHT3X is not set +# CONFIG_PKG_USING_ADT74XX is not set +# CONFIG_PKG_USING_AS7341 is not set +# CONFIG_PKG_USING_STM32_SDIO is not set +# CONFIG_PKG_USING_ESP_IDF is not set +# CONFIG_PKG_USING_ICM20608 is not set +# CONFIG_PKG_USING_BUTTON is not set +# CONFIG_PKG_USING_PCF8574 is not set +# CONFIG_PKG_USING_SX12XX is not set +# CONFIG_PKG_USING_SIGNAL_LED is not set +# CONFIG_PKG_USING_LEDBLINK is not set +# CONFIG_PKG_USING_LITTLED is not set +# CONFIG_PKG_USING_LKDGUI is not set +# CONFIG_PKG_USING_NRF5X_SDK is not set +# CONFIG_PKG_USING_NRFX is not set +# CONFIG_PKG_USING_WM_LIBRARIES is not set + +# +# Kendryte SDK +# +# CONFIG_PKG_USING_K210_SDK is not set +# CONFIG_PKG_USING_KENDRYTE_SDK is not set +# CONFIG_PKG_USING_INFRARED is not set +# CONFIG_PKG_USING_MULTI_INFRARED is not set +# CONFIG_PKG_USING_AGILE_BUTTON is not set +# CONFIG_PKG_USING_AGILE_LED is not set +# CONFIG_PKG_USING_AT24CXX is not set +# CONFIG_PKG_USING_MOTIONDRIVER2RTT is not set +# CONFIG_PKG_USING_AD7746 is not set +# CONFIG_PKG_USING_PCA9685 is not set +# CONFIG_PKG_USING_I2C_TOOLS is not set +# CONFIG_PKG_USING_NRF24L01 is not set +# CONFIG_PKG_USING_TOUCH_DRIVERS is not set +# CONFIG_PKG_USING_MAX17048 is not set +# CONFIG_PKG_USING_RPLIDAR is not set +# CONFIG_PKG_USING_AS608 is not set +# CONFIG_PKG_USING_RC522 is not set +# CONFIG_PKG_USING_WS2812B is not set +# CONFIG_PKG_USING_EMBARC_BSP is not set +# CONFIG_PKG_USING_EXTERN_RTC_DRIVERS is not set +# CONFIG_PKG_USING_MULTI_RTIMER is not set +# CONFIG_PKG_USING_MAX7219 is not set +# CONFIG_PKG_USING_BEEP is not set +# CONFIG_PKG_USING_EASYBLINK is not set +# CONFIG_PKG_USING_PMS_SERIES is not set +# CONFIG_PKG_USING_CAN_YMODEM is not set +# CONFIG_PKG_USING_LORA_RADIO_DRIVER is not set +# CONFIG_PKG_USING_QLED is not set +# CONFIG_PKG_USING_PAJ7620 is not set +# CONFIG_PKG_USING_AGILE_CONSOLE is not set +# CONFIG_PKG_USING_LD3320 is not set +# CONFIG_PKG_USING_WK2124 is not set +# CONFIG_PKG_USING_LY68L6400 is not set +# CONFIG_PKG_USING_DM9051 is not set +# CONFIG_PKG_USING_SSD1306 is not set +# CONFIG_PKG_USING_QKEY is not set +# CONFIG_PKG_USING_RS485 is not set +# CONFIG_PKG_USING_RS232 is not set +# CONFIG_PKG_USING_NES is not set +# CONFIG_PKG_USING_VIRTUAL_SENSOR is not set +# CONFIG_PKG_USING_VDEVICE is not set +# CONFIG_PKG_USING_SGM706 is not set +# CONFIG_PKG_USING_STM32WB55_SDK is not set +# CONFIG_PKG_USING_RDA58XX is not set +# CONFIG_PKG_USING_LIBNFC is not set +# CONFIG_PKG_USING_MFOC is not set +# CONFIG_PKG_USING_TMC51XX is not set +# CONFIG_PKG_USING_TCA9534 is not set +# CONFIG_PKG_USING_KOBUKI is not set +# CONFIG_PKG_USING_ROSSERIAL is not set +# CONFIG_PKG_USING_MICRO_ROS is not set +# CONFIG_PKG_USING_MCP23008 is not set +# CONFIG_PKG_USING_BLUETRUM_SDK is not set +# CONFIG_PKG_USING_MISAKA_AT24CXX is not set +# CONFIG_PKG_USING_MISAKA_RGB_BLING is not set +# CONFIG_PKG_USING_LORA_MODEM_DRIVER is not set +# CONFIG_PKG_USING_BL_MCU_SDK is not set +# CONFIG_PKG_USING_SOFT_SERIAL is not set +# CONFIG_PKG_USING_MB85RS16 is not set +# CONFIG_PKG_USING_CW2015 is not set +# CONFIG_PKG_USING_RFM300 is not set +# CONFIG_PKG_USING_IO_INPUT_FILTER is not set +# CONFIG_PKG_USING_RASPBERRYPI_PICO_SDK is not set + +# +# AI packages +# +# CONFIG_PKG_USING_LIBANN is not set +# CONFIG_PKG_USING_NNOM is not set +# CONFIG_PKG_USING_ONNX_BACKEND is not set +# CONFIG_PKG_USING_ONNX_PARSER is not set +# CONFIG_PKG_USING_TENSORFLOWLITEMICRO is not set +# CONFIG_PKG_USING_ELAPACK is not set +# CONFIG_PKG_USING_ULAPACK is not set +# CONFIG_PKG_USING_QUEST is not set +# CONFIG_PKG_USING_NAXOS is not set + +# +# miscellaneous packages +# + +# +# project laboratory +# + +# +# samples: kernel and components samples +# +# CONFIG_PKG_USING_KERNEL_SAMPLES is not set +# CONFIG_PKG_USING_FILESYSTEM_SAMPLES is not set +# CONFIG_PKG_USING_NETWORK_SAMPLES is not set +# CONFIG_PKG_USING_PERIPHERAL_SAMPLES is not set + +# +# entertainment: terminal games and other interesting software packages +# +# CONFIG_PKG_USING_CMATRIX is not set +# CONFIG_PKG_USING_SL is not set +# CONFIG_PKG_USING_CAL is not set +# CONFIG_PKG_USING_ACLOCK is not set +# CONFIG_PKG_USING_THREES is not set +# CONFIG_PKG_USING_2048 is not set +# CONFIG_PKG_USING_SNAKE is not set +# CONFIG_PKG_USING_TETRIS is not set +# CONFIG_PKG_USING_DONUT is not set +# CONFIG_PKG_USING_COWSAY is not set +# CONFIG_PKG_USING_LIBCSV is not set +CONFIG_PKG_USING_OPTPARSE=y +CONFIG_PKG_OPTPARSE_PATH="/packages/misc/optparse" +CONFIG_PKG_USING_OPTPARSE_LATEST_VERSION=y +CONFIG_PKG_OPTPARSE_VER="latest" +# CONFIG_OPTPARSE_USING_DEMO is not set +# CONFIG_PKG_USING_FASTLZ is not set +# CONFIG_PKG_USING_MINILZO is not set +# CONFIG_PKG_USING_QUICKLZ is not set +# CONFIG_PKG_USING_LZMA is not set +# CONFIG_PKG_USING_MULTIBUTTON is not set +# CONFIG_PKG_USING_FLEXIBLE_BUTTON is not set +# CONFIG_PKG_USING_CANFESTIVAL is not set +# CONFIG_PKG_USING_ZLIB is not set +# CONFIG_PKG_USING_MINIZIP is not set +# CONFIG_PKG_USING_HEATSHRINK is not set +# CONFIG_PKG_USING_DSTR is not set +# CONFIG_PKG_USING_TINYFRAME is not set +# CONFIG_PKG_USING_KENDRYTE_DEMO is not set +# CONFIG_PKG_USING_DIGITALCTRL is not set +# CONFIG_PKG_USING_UPACKER is not set +# CONFIG_PKG_USING_UPARAM is not set +# CONFIG_PKG_USING_HELLO is not set +# CONFIG_PKG_USING_VI is not set +# CONFIG_PKG_USING_KI is not set +# CONFIG_PKG_USING_ARMv7M_DWT is not set +# CONFIG_PKG_USING_UKAL is not set +# CONFIG_PKG_USING_CRCLIB is not set +# CONFIG_PKG_USING_LWGPS is not set +# CONFIG_PKG_USING_STATE_MACHINE is not set +# CONFIG_PKG_USING_DESIGN_PATTERN is not set +# CONFIG_PKG_USING_CONTROLLER is not set +# CONFIG_PKG_USING_PHASE_LOCKED_LOOP is not set +# CONFIG_PKG_USING_MFBD is not set +# CONFIG_PKG_USING_SLCAN2RTT is not set +# CONFIG_PKG_USING_SOEM is not set +CONFIG_UTEST_CMD_PREFIX="bsp.nuvoton.utest." +CONFIG_BOARD_USE_UTEST=y + +# +# Hardware Drivers Config +# + +# +# On-chip Peripheral Drivers +# +CONFIG_SOC_SERIES_MA35D1=y +CONFIG_RT_USING_FPU=y +# CONFIG_BSP_USE_STDDRIVER_SOURCE is not set +CONFIG_BSP_USING_PDMA=y +CONFIG_BSP_USING_PDMA0=y +CONFIG_BSP_USING_PDMA1=y +# CONFIG_BSP_USING_PDMA2 is not set +# CONFIG_BSP_USING_PDMA3 is not set +CONFIG_NU_PDMA_MEMFUN_ACTOR_MAX=4 +CONFIG_BSP_USING_GPIO=y +CONFIG_BSP_USING_GMAC=y +CONFIG_BSP_USING_GMAC0=y +CONFIG_BSP_USING_GMAC1=y +CONFIG_BSP_USING_RTC=y +# CONFIG_NU_RTC_SUPPORT_IO_RW is not set +# CONFIG_NU_RTC_SUPPORT_MSH_CMD is not set +CONFIG_BSP_USING_ADC=y +CONFIG_BSP_USING_ADC_TOUCH=y +CONFIG_BSP_USING_CCAP=y +CONFIG_BSP_USING_CCAP0=y +# CONFIG_BSP_USING_CCAP1 is not set +# CONFIG_BSP_USING_EADC is not set +# CONFIG_BSP_USING_TMR is not set +CONFIG_BSP_USING_UART=y +CONFIG_BSP_USING_UART0=y +# CONFIG_BSP_USING_UART0_TX_DMA is not set +# CONFIG_BSP_USING_UART0_RX_DMA is not set +# CONFIG_BSP_USING_UART1 is not set +# CONFIG_BSP_USING_UART2 is not set +# CONFIG_BSP_USING_UART3 is not set +# CONFIG_BSP_USING_UART4 is not set +# CONFIG_BSP_USING_UART5 is not set +# CONFIG_BSP_USING_UART6 is not set +# CONFIG_BSP_USING_UART7 is not set +# CONFIG_BSP_USING_UART8 is not set +# CONFIG_BSP_USING_UART9 is not set +# CONFIG_BSP_USING_UART10 is not set +CONFIG_BSP_USING_UART11=y +CONFIG_BSP_USING_UART11_TX_DMA=y +CONFIG_BSP_USING_UART11_RX_DMA=y +CONFIG_BSP_USING_UART12=y +# CONFIG_BSP_USING_UART12_TX_DMA is not set +# CONFIG_BSP_USING_UART12_RX_DMA is not set +# CONFIG_BSP_USING_UART13 is not set +CONFIG_BSP_USING_UART14=y +# CONFIG_BSP_USING_UART14_TX_DMA is not set +# CONFIG_BSP_USING_UART14_RX_DMA is not set +# CONFIG_BSP_USING_UART15 is not set +CONFIG_BSP_USING_UART16=y +CONFIG_BSP_USING_UART16_TX_DMA=y +CONFIG_BSP_USING_UART16_RX_DMA=y +CONFIG_BSP_USING_I2C=y +CONFIG_BSP_USING_I2C0=y +CONFIG_BSP_USING_I2C1=y +CONFIG_BSP_USING_I2C2=y +CONFIG_BSP_USING_I2C3=y +CONFIG_BSP_USING_I2C4=y +CONFIG_BSP_USING_I2C5=y +CONFIG_BSP_USING_SDH=y +CONFIG_BSP_USING_SDH0=y +CONFIG_BSP_USING_SDH1=y +# CONFIG_BSP_USING_CANFD is not set +# CONFIG_BSP_USING_EPWM is not set +CONFIG_BSP_USING_SPI=y +# CONFIG_BSP_USING_SPI_PDMA is not set +CONFIG_BSP_USING_SPI0_NONE=y +# CONFIG_BSP_USING_SPI0 is not set +# CONFIG_BSP_USING_SPII2S0 is not set +CONFIG_BSP_USING_SPI1_NONE=y +# CONFIG_BSP_USING_SPI1 is not set +# CONFIG_BSP_USING_SPII2S1 is not set +CONFIG_BSP_USING_SPI2_NONE=y +# CONFIG_BSP_USING_SPI2 is not set +# CONFIG_BSP_USING_SPII2S2 is not set +CONFIG_BSP_USING_SPI3_NONE=y +# CONFIG_BSP_USING_SPI3 is not set +# CONFIG_BSP_USING_SPII2S3 is not set +CONFIG_BSP_USING_I2S=y +CONFIG_BSP_USING_I2S0=y +# CONFIG_BSP_USING_I2S1 is not set +CONFIG_NU_I2S_DMA_FIFO_SIZE=2048 +CONFIG_BSP_USING_QSPI=y +# CONFIG_BSP_USING_QSPI_PDMA is not set +CONFIG_BSP_USING_QSPI0=y +# CONFIG_BSP_USING_QSPI0_PDMA is not set +# CONFIG_BSP_USING_QSPI1 is not set +# CONFIG_BSP_USING_SCUART is not set +# CONFIG_BSP_USING_ECAP is not set +# CONFIG_BSP_USING_QEI is not set +# CONFIG_BSP_USING_CRYPTO is not set +# CONFIG_BSP_USING_TRNG is not set +# CONFIG_BSP_USING_CRC is not set +# CONFIG_BSP_USING_SOFT_I2C is not set +CONFIG_BSP_USING_DISP=y +CONFIG_LCM_USING_FW070TFT_WSVGA=y +# CONFIG_LCM_USING_FW070TFT_WVGA is not set +# CONFIG_LCM_USING_FHD is not set +CONFIG_DISP_USING_LCD_IDX=0 +CONFIG_BSP_LCD_BPP=32 +CONFIG_BSP_LCD_WIDTH=1024 +CONFIG_BSP_LCD_HEIGHT=600 +CONFIG_DISP_USING_OVERLAY=y +# CONFIG_BSP_USING_WDT is not set +# CONFIG_BSP_USING_EBI is not set +# CONFIG_BSP_USING_USBD is not set +CONFIG_BSP_USING_USBH=y +CONFIG_BSP_USING_HSUSBH0=y +CONFIG_BSP_USING_HSUSBH1=y + +# +# On-board Peripheral Drivers +# +CONFIG_BSP_USING_CONSOLE=y +CONFIG_BOARD_USING_NAU8822=y +CONFIG_BOARD_USING_STORAGE_SDCARD=y +CONFIG_BOARD_USING_STORAGE_EMMC=y +# CONFIG_BOARD_USING_STORAGE_SPIFLASH is not set +CONFIG_BOARD_USING_STORAGE_SPINAND=y +# CONFIG_BOARD_USING_BUZZER is not set +CONFIG_BOARD_USING_USBHOST=y + +# +# Board extended module drivers +# +CONFIG_BOARD_USING_LCM=y +# CONFIG_BOARD_USING_LCM_FW070TFT_WVGA is not set +CONFIG_BOARD_USING_LCM_FW070TFT_WSVGA=y +# CONFIG_BOARD_USING_GT911 is not set +CONFIG_BOARD_USING_ADCTOUCH=y +CONFIG_BOARD_USING_SENSOR0=y +CONFIG_BOARD_USING_SENSON0_ID=0 +# CONFIG_BOARD_USING_SENSOR1 is not set + +# +# Nuvoton Packages Config +# +CONFIG_NU_PKG_USING_UTILS=y +# CONFIG_NU_PKG_USING_DEMO is not set +CONFIG_NU_PKG_USING_LVGL=y +# CONFIG_NU_PKG_USING_BMX055 is not set +# CONFIG_NU_PKG_USING_MAX31875 is not set +# CONFIG_NU_PKG_USING_NCT7717U is not set +# CONFIG_NU_PKG_USING_NAU88L25 is not set +CONFIG_NU_PKG_USING_NAU8822=y +# CONFIG_NU_PKG_USING_DA9062 is not set +# CONFIG_NU_PKG_USING_ILI9341 is not set +# CONFIG_NU_PKG_USING_SSD1963 is not set +# CONFIG_NU_PKG_USING_FSA506 is not set +# CONFIG_NU_PKG_USING_TPC is not set +CONFIG_NU_PKG_USING_ADC_TOUCH=y +# CONFIG_NU_PKG_USING_ADC_TOUCH_SW is not set +CONFIG_NU_PKG_USING_SPINAND=y diff --git a/bsp/nuvoton/numaker-hmi-ma35d1/Kconfig b/bsp/nuvoton/numaker-hmi-ma35d1/Kconfig new file mode 100644 index 0000000000..a78782d615 --- /dev/null +++ b/bsp/nuvoton/numaker-hmi-ma35d1/Kconfig @@ -0,0 +1,27 @@ +mainmenu "RT-Thread Configuration" + +config BSP_DIR + string + option env="BSP_ROOT" + default "." + +config RTT_DIR + string + option env="RTT_ROOT" + default "../../.." + +# you can change the RTT_ROOT default "../../.." to your rtthread_root, +# example : default "F:/git_repositories/rt-thread" + +config PKGS_DIR + string + option env="PKGS_ROOT" + default "packages" + +config USE_MA35D1_AARCH32 + bool + default y + +source "$RTT_DIR/Kconfig" +source "$PKGS_DIR/Kconfig" +source "$BSP_DIR/board/Kconfig" diff --git a/bsp/nuvoton/numaker-hmi-ma35d1/README.md b/bsp/nuvoton/numaker-hmi-ma35d1/README.md new file mode 100644 index 0000000000..9343a68fd0 --- /dev/null +++ b/bsp/nuvoton/numaker-hmi-ma35d1/README.md @@ -0,0 +1,216 @@ +# **NuMaker-HMI-MA35D1** + +## **Introduction** + +The NuMaker-HMI-MA35D1 is an evaluation board for Nuvoton NuMicro MA35D1 series microprocessors, and consists of three parts: a NuMaker-SOM-MA35D16A81 SOM board, a NuMaker-BASE-MA35D1B1 base board and a 7 inch TFT-LCD daughter board. The SOM board integrates core components to simplify the system design, based on MA35D16A887C (BGA312 package, and stacking a 256 MB DDR), PMIC power solution, a 16 GB eMMC Flash, and two Gigabit Ethernet PHY. The NuMaker-HMI-MA35D1-S1 has rich peripherals such as 2 sets of Gigabit Ethernet, USB2.0 high-speed host and device, 2 sets of CAN FD, and SPI, I2C, UART, RS-485 serial communication ports for users to facilitate the evaluation in HMI and industrial control, home appliances, 2-wheel cluster, medical device, new energy applications, ML (Machine Learning) or your creative applications. + +The NuMicro MA35D1 series is a heterogeneous multi-core microprocessor targeted to high-end edge IIoT gateway. It is based on dual 64-bit Arm Cortex-A35 cores, and one 180 MHz Arm Cortex-M4 core. Based on the high-performance cores, the MA35D1 series facilities the tiny AI/ML for edge computing. The MA35D1 supports 16-bit DDR2 and DDR3/DDR3L SDRAM. For an easy system design and manufacture, the MA35D1 series also offers LQFP and BGA packages stacked with the DDR2/DDR3L SDRAM and density up to 512 MB, which significantly reduces PCB layer, size and electromagnetic interference (EMI). + +

+fishy +

+ +|NuMaker-BASE-MA35D1B1|NuMaker-SOM-MA35D16A81|7-inch LCD Panel| +|--|--|--| +|

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|

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|

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| + +## **NuMaker-SOM-MA35D16A81 Features** + +
    +
  • Target Chip
    • +
      +
    • MA35D16A887C (BGA 312-Ball) MCP package with DDR3L (256 MB), which can run up to 800 MHz
      • +
    +
  • Power
    • +
      +
    • DC 5V input through the high speed connector**
      • +
    • PMIC DA9062-3A
      • +
        +
      • Four DC/DC
        • + To supply 1.2V Core power, 1.2V CPU power, 1.35V DDR3L Memory power and 3.3V I/O power +
      • Four LDO
        • + To supply 3.0V RTC power, 1.8V I/O power, 2.5V PLL power and 3.3V/1.8V eMMC NAND Flash power +
      +
    • Battery input header
      • +
    +
  • Memory Devices
    • +
      +
    • An on-board eMMC NAND Flash memory device (16 GB)
      • +
    +
  • Two Gigabit Ethernet (RGMII) PHY devices
    • +
  • Two 120-pin high speed connectors to connect with BASE board
    • +
  • One PMIC reset key button
    • +
+ +## **NuMaker-BASE-MA35D1B1 Features** + +
    +
  • Power
    • +
      +
    • 5V/2A Power Jack and Slide Switch
      • +
    +
  • Debug/Trace
    • +
      +
    • UART0 debug port: USB Virtual COM (VCOM) port
      • +
    • Debug/Trace ports: SWJ (JTAG+SWD), ETM and SWD connectors
      • +
    +
  • Memory Devices
    • +
      +
    • An on-board Quad SPI NAND Flash device (512 MB)
      • +
    • An on-board NAND Flash device (1 GB)
      • +
    • Standard-SD (SD2.0) memory card slot
      • +
    + +
  • One power-on setting DIP-Switch for evaluation booting source selection
    • + +
  • Two 120-pin high speed connectors to connect with SOM board
    • +
  • Two sets of Gigabit Ethernet ports: Two Gigabit Ethernet transformer devices and two RJ45 port connectors
    • +
  • Two sets of high speed USB ports: One Host/Device port and one Host port
    • +
  • Two camera capture (CMOS sensor) header connectors
    • +
  • One LCM connector to connect with 7-inch 1024x600 LCD daughter board
    • +
  • One audio codec with microphone input and speaker output
    • +
  • One SIM card slot
    • +
  • One External Bus Interface (EBI) header connector
    • +
  • Two sets of UART transceivers and DB9 connectors
    • +
  • Two sets of RS485 transceivers and header connectors
    • +
  • Two sets of CAN FD transceivers and header connectors
    • +
  • One 8-channel ADC header connector
    • +
  • MEMS Microphone
    • +
  • MEMS G-Sensor
    • +
  • Three user key buttons
    • +
  • Two user LEDs
    • +
  • One set of buzzer pads
    • +
+ +## **Supported compiler** + +Support GCC compiler. More information of these compiler version as following: + +| Compiler | Tested version | +| -- | -- | +| GCC | 6-2017-q1-update| + +## **Build RT-Thread** +You can build rt-thread.bin for NuMaker-HMI-MA35D1 board. Steps as following. Notice, the building will include **ma35-rtp/rtthread.bin** file into **NuMaker-HMI-MA35D1/rtthread.bin** for heterogeneous multi-core demonstration. + +```bash +# cd rt-thread/bsp/nuvoton/numaker-hmi-ma35d1 +# menuconfig --generate +# scons -c +# pkgs --update +Cloning into '\bsp\bsp\nuvoton\numaker-hmi-ma35d1\packages\LVGL-latest'... +remote: Enumerating objects: 67821, done. +remote: Counting objects: 100% (1085/1085), done. +remote: Compressing objects: 100% (608/608), done. +remote: Total 67821 (delta 512), reused 964 (delta 476), pack-reused 66736 +Receiving objects: 100% (67821/67821), 109.32 MiB | 572.00 KiB/s, done. +Resolving deltas: 100% (52349/52349), done. +Updating files: 100% (1248/1248), done. +==============================> LVGL latest is downloaded successfully. +... +==============================> OPTPARSE latest is downloaded successfully. +==============================> wavplayer update done +==============================> ramdisk update done +==============================> optparse update done +Operation completed successfully. + +# scons -j 16 +… +… +LINK rtthread.elf +arm-none-eabi-objcopy -O binary rtthread.elf rtthread.bin +arm-none-eabi-size rtthread.elf + text data bss dec hex filename +1208928 14828 15507944 16731700 ff4e34 rtthread.elf +scons: done building targets. + +\bsp\nuvoton\numaker-hmi-ma35d1\rtthread.bin +``` + +## **Program firmware using NuWriter** + +To switch SW4 dip-switch on NuMaker-BASE-MA35D1B1 to do corresponding actions as below. + +**Power-on Setting** +L: OFF dip-switch +H: ON dip-switch + +| Memory Storage | **Burn to** settings | **Boot from** settings | +|--|--|--| +| **DDR** |
  • Switch 1(PG0) to ON.
  • Switch 3(PG2) to ON.
  • Switch 4(PG3) to ON.
  • Switch Others to OFF.
| | +| **EMMC**
(Select eMMC1 device and 8-bit mode) |
  • Switch 1(PG0) to ON.
  • Switch 3(PG2) to ON.
  • Switch 4(PG3) to ON.
  • Switch 7(PG6) to ON.
  • Switch 8(PG7) to ON.
  • Switch Others to OFF.
|
  • Switch 1(PG0) to ON.
  • Switch 3(PG2) to ON.
  • Switch 7(PG6) to ON.
  • Switch 8(PG7) to ON.
  • Switch Others to OFF.
| +| **Raw NAND**
(Select Ignore BCH and Page setting) |
  • Switch 1(PG0) to ON.
  • Switch 3(PG2) to ON.
  • Switch 4(PG3) to ON.
  • Switch Others to OFF.
|
  • Switch 1(PG0) to ON.
  • Switch 4(PG3) to ON.
  • Switch Others to OFF.
| +| **Serial NAND**
(Select 4-bit mode) |
  • Switch 1(PG0) to ON.
  • Switch 3(PG2) to ON.
  • Switch 4(PG3) to ON.
  • Switch 7(PG6) to ON.
  • Switch Others to OFF.
|
  • Switch 1(PG0) to ON.
  • Switch 7(PG6) to ON.
  • Switch Others to OFF.
+ +### **Download to DDR and Run** + +You can run windows batch script to download rtthread.bin into memory, then run it. The path of batch script as below,. + +```bash +\bsp\nuvoton\numaker-hmi-ma35d1\nuwriter_scripts\nuwriter_ddr_download_and_run.bat +``` + +

+ +

+ +### **Burn to EMMC** + +You can run windows batch script to download rtthread.bin into emmc flash, then run it. The path of batch script as below,. + +```bash +\bsp\nuvoton\numaker-hmi-ma35d1\nuwriter_scripts\nuwriter_sd_programming.bat +``` + +

+ +

+ +### **Burn to Serial NAND** + +You can run windows batch script to download rtthread.bin into SPI-NAND flash, then run it. The path of batch script as below,. + +```bash +\bsp\nuvoton\numaker-hmi-ma35d1\nuwriter_scripts\nuwriter_spinand_programming.bat +``` + +

+ +

+ +### **Burn to Raw NAND** + +You can run windows batch script to download rtthread.bin into Raw NAND flash, then run it. The path of batch script as below. + +```bash +\bsp\nuvoton\numaker-hmi-ma35d1\nuwriter_scripts\nuwriter_nand_programming.bat +``` + +

+ +

+ +## **Test** + +|Connector on board|Wiring|Usage| +|-|-|-| +|VCOM(CON21)|Use an USB line| rt-thread@RTP Console | +|RS232_16(CON14)|Using an USB to RS232 convert| rt-thread@CA35 Console | + +You can use Tera Term terminate emulator (or other software) to type commands of RTT. All parameters of serial communication are shown in below image. Here, you can find out the corresponding port number of Nuvoton Virtual Com Port in window device manager. + +

+fishy +

+
+ +## **Purchase** + +* [Nuvoton Direct](https://ComingSoon) + +## **Resources** + +* [Download Board Schematics](https://ComingSoon) +* [Download Quick Start Guide](https://ComingSoon) +* [Download TRM](https://ComingSoon) +* [Download NuWriter](https://github.com/OpenNuvoton/MA35D1_NuWriter) diff --git a/bsp/nuvoton/numaker-hmi-ma35d1/SConscript b/bsp/nuvoton/numaker-hmi-ma35d1/SConscript new file mode 100644 index 0000000000..fe0ae941ae --- /dev/null +++ b/bsp/nuvoton/numaker-hmi-ma35d1/SConscript @@ -0,0 +1,14 @@ +# for module compiling +import os +Import('RTT_ROOT') + +cwd = str(Dir('#')) +objs = [] +list = os.listdir(cwd) + +for d in list: + path = os.path.join(cwd, d) + if os.path.isfile(os.path.join(path, 'SConscript')): + objs = objs + SConscript(os.path.join(d, 'SConscript')) + +Return('objs') diff --git a/bsp/nuvoton/numaker-hmi-ma35d1/SConstruct b/bsp/nuvoton/numaker-hmi-ma35d1/SConstruct new file mode 100644 index 0000000000..5143e3012d --- /dev/null +++ b/bsp/nuvoton/numaker-hmi-ma35d1/SConstruct @@ -0,0 +1,58 @@ +import os +import sys +import rtconfig + +if os.getenv('RTT_ROOT'): + RTT_ROOT = os.getenv('RTT_ROOT') +else: + RTT_ROOT = os.path.normpath(os.getcwd() + '/../../..') + +sys.path = sys.path + [os.path.join(RTT_ROOT, 'tools')] +try: + from building import * +except: + print('Cannot found RT-Thread root directory, please check RTT_ROOT') + print(RTT_ROOT) + exit(-1) + +TARGET = 'rtthread.' + rtconfig.TARGET_EXT + +DefaultEnvironment(tools=[]) +env = Environment(tools = ['mingw'], + AS = rtconfig.AS, ASFLAGS = rtconfig.AFLAGS, + CC = rtconfig.CC, CCFLAGS = rtconfig.CFLAGS, + CXX = rtconfig.CXX, CXXFLAGS = rtconfig.CXXFLAGS, + AR = rtconfig.AR, ARFLAGS = '-rc', + LINK = rtconfig.LINK, LINKFLAGS = rtconfig.LFLAGS, + CXXCOM = '$CXX -o $TARGET -c $CXXFLAGS $_CCCOMCOM $SOURCES') + +env.PrependENVPath('PATH', rtconfig.EXEC_PATH) +env['ASCOM'] = env['ASPPCOM'] + +Export('RTT_ROOT') +Export('rtconfig') + +SDK_ROOT = os.path.abspath('./') + +if os.path.exists(SDK_ROOT + '/libraries'): + libraries_path_prefix = SDK_ROOT + '/libraries' +else: + libraries_path_prefix = os.path.dirname(SDK_ROOT) + '/libraries' + +SDK_LIB = libraries_path_prefix +Export('SDK_LIB') + +# prepare building environment +objs = PrepareBuilding(env, RTT_ROOT) + +nuvoton_library = 'ma35' +rtconfig.BSP_LIBRARY_TYPE = nuvoton_library + +# include libraries +objs.extend(SConscript(os.path.join(libraries_path_prefix, nuvoton_library, 'SConscript'))) + +# include nu_pkgs +objs.extend(SConscript(os.path.join(libraries_path_prefix, 'nu_packages', 'SConscript'))) + +# make a building +DoBuilding(TARGET, objs) diff --git a/bsp/nuvoton/numaker-hmi-ma35d1/applications/SConscript b/bsp/nuvoton/numaker-hmi-ma35d1/applications/SConscript new file mode 100644 index 0000000000..3769d125df --- /dev/null +++ b/bsp/nuvoton/numaker-hmi-ma35d1/applications/SConscript @@ -0,0 +1,21 @@ +# RT-Thread building script for component + +from building import * + +cwd = GetCurrentDir() +objs = [] +list = os.listdir(cwd) +for d in list: + path = os.path.join(cwd, d) + if os.path.isfile(os.path.join(path, 'SConscript')): + objs = objs + SConscript(os.path.join(d, 'SConscript')) + +src = Glob('*.c') + Glob('*.cpp') +CPPPATH = [cwd, str(Dir('#'))] + +group = DefineGroup('Applications', src, depend = [''], CPPPATH = CPPPATH) + +objs = objs + group + +Return('objs') + diff --git a/bsp/nuvoton/numaker-hmi-ma35d1/applications/lvgl/SConscript b/bsp/nuvoton/numaker-hmi-ma35d1/applications/lvgl/SConscript new file mode 100644 index 0000000000..18f793dbe0 --- /dev/null +++ b/bsp/nuvoton/numaker-hmi-ma35d1/applications/lvgl/SConscript @@ -0,0 +1,10 @@ +from building import * + +cwd = GetCurrentDir() +src = Glob('*.c') +CPPPATH = [cwd] + +group = DefineGroup('LVGL-port', src, depend = ['PKG_USING_LVGL'], CPPPATH = CPPPATH) + +Return('group') + diff --git a/bsp/nuvoton/numaker-hmi-ma35d1/applications/lvgl/lv_conf.h b/bsp/nuvoton/numaker-hmi-ma35d1/applications/lvgl/lv_conf.h new file mode 100644 index 0000000000..c902bc904c --- /dev/null +++ b/bsp/nuvoton/numaker-hmi-ma35d1/applications/lvgl/lv_conf.h @@ -0,0 +1,38 @@ +/* + * Copyright (c) 2006-2022, RT-Thread Development Team + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + * 2022-2-17 Wayne First version + */ + +#ifndef LV_CONF_H +#define LV_CONF_H + +#include "rtconfig.h" + +#define LV_COLOR_DEPTH BSP_LCD_BPP +#define LV_HOR_RES_MAX BSP_LCD_WIDTH +#define LV_VER_RES_MAX BSP_LCD_HEIGHT + +#define LV_FONT_MONTSERRAT_12 1 +#define LV_FONT_MONTSERRAT_16 1 +#define LV_USE_PERF_MONITOR 1 +//#define CONFIG_LV_LOG_LEVEL LV_LOG_LEVEL_TRACE + +//#define LV_USE_DEMO_RTT_MUSIC 1 +#if LV_USE_DEMO_RTT_MUSIC + #define LV_COLOR_SCREEN_TRANSP 1 + #define LV_DEMO_RTT_MUSIC_AUTO_PLAY 1 + + #define LV_USE_DEMO_MUSIC 1 + #define LV_DEMO_MUSIC_AUTO_PLAY 1 +#endif + +/* Please comment LV_USE_DEMO_RTT_MUSIC declaration before un-comment below */ +#define LV_USE_DEMO_WIDGETS 1 +//#define LV_USE_DEMO_BENCHMARK 1 + +#endif diff --git a/bsp/nuvoton/numaker-hmi-ma35d1/applications/lvgl/lv_demo.c b/bsp/nuvoton/numaker-hmi-ma35d1/applications/lvgl/lv_demo.c new file mode 100644 index 0000000000..7a04e1804a --- /dev/null +++ b/bsp/nuvoton/numaker-hmi-ma35d1/applications/lvgl/lv_demo.c @@ -0,0 +1,32 @@ +/* + * Copyright (c) 2006-2022, RT-Thread Development Team + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + * 2022-6-1 Wayne First version + */ + +#include + +void lv_user_gui_init(void) +{ + /* display demo; you may replace with your LVGL application at here and disable related definitions. */ + +#if LV_USE_DEMO_BENCHMARK + extern void lv_demo_benchmark(void); + lv_demo_benchmark(); +#endif + +#if LV_USE_DEMO_WIDGETS + extern void lv_demo_widgets(void); + lv_demo_widgets(); +#endif + +#if LV_USE_DEMO_MUSIC || LV_USE_DEMO_RTT_MUSIC + extern void lv_demo_music(void); + lv_demo_music(); +#endif + +} diff --git a/bsp/nuvoton/numaker-hmi-ma35d1/applications/lvgl/lv_port_disp.c b/bsp/nuvoton/numaker-hmi-ma35d1/applications/lvgl/lv_port_disp.c new file mode 100644 index 0000000000..8c1de86b8d --- /dev/null +++ b/bsp/nuvoton/numaker-hmi-ma35d1/applications/lvgl/lv_port_disp.c @@ -0,0 +1,189 @@ +/* + * Copyright (c) 2006-2022, RT-Thread Development Team + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + * 2021-12-17 Wayne The first version + */ +#include +#include "drv_common.h" + +#define LOG_TAG "lvgl.disp" +#define DBG_ENABLE +#define DBG_SECTION_NAME LOG_TAG +#define DBG_LEVEL DBG_ERROR +#define DBG_COLOR +#include + +/*A static or global variable to store the buffers*/ +static lv_disp_draw_buf_t disp_buf; +static rt_device_t lcd_device = 0; +static struct rt_device_graphic_info info; +static lv_disp_drv_t disp_drv; /*Descriptor of a display driver*/ + +static void *buf3_next = RT_NULL; + +static uint32_t u32FirstFlush = 0; + +static void nu_antitearing(lv_disp_draw_buf_t *draw_buf, lv_color_t *color_p) +{ + if (buf3_next) + { + /* vsync-none: Use triple screen-sized buffers. */ + if (draw_buf->buf1 == color_p) + draw_buf->buf1 = buf3_next; + else + draw_buf->buf2 = buf3_next; + + draw_buf->buf_act = buf3_next; + buf3_next = color_p; + } + else + { + /* vsync-after: Use ping-pong screen-sized buffers only.*/ + rt_device_control(lcd_device, RTGRAPHIC_CTRL_WAIT_VSYNC, RT_NULL); + } +} + +static void nu_flush_direct(lv_disp_drv_t *disp_drv, const lv_area_t *area, lv_color_t *color_p) +{ + /* Use PANDISPLAY */ + rt_device_control(lcd_device, RTGRAPHIC_CTRL_PAN_DISPLAY, color_p); + + //TODO + nu_antitearing(disp_drv->draw_buf, color_p); + + if (!u32FirstFlush) + { + /* Enable backlight at first flushing. */ + rt_device_control(lcd_device, RTGRAPHIC_CTRL_POWERON, RT_NULL); + u32FirstFlush = 1; + } + + lv_disp_flush_ready(disp_drv); +} + +static void nu_flush_full_refresh(lv_disp_drv_t *disp_drv, const lv_area_t *area, lv_color_t *color_p) +{ + rt_hw_cpu_dcache_clean(color_p, disp_drv->draw_buf->size * sizeof(lv_color_t)); + + /* Use PANDISPLAY without H/W copying */ + rt_device_control(lcd_device, RTGRAPHIC_CTRL_PAN_DISPLAY, color_p); + + nu_antitearing(disp_drv->draw_buf, color_p); + + if (!u32FirstFlush) + { + /* Enable backlight at first flushing. */ + rt_device_control(lcd_device, RTGRAPHIC_CTRL_POWERON, RT_NULL); + u32FirstFlush = 1; + } + + lv_disp_flush_ready(disp_drv); +} + +static void nu_flush(lv_disp_drv_t *disp_drv, const lv_area_t *area, lv_color_t *color_p) +{ + int32_t flush_area_w = lv_area_get_width(area); + int32_t flush_area_h = lv_area_get_height(area); + + rt_kprintf("[%s %08x] %dx%d %d %d %d %d\n", __func__, color_p, flush_area_w, flush_area_h, area->x1, area->y1, area->x2, area->y2); + + /* Update dirty region. */ + //TODO + + if (!u32FirstFlush) + { + /* Enable backlight at first flushing. */ + rt_device_control(lcd_device, RTGRAPHIC_CTRL_POWERON, RT_NULL); + u32FirstFlush = 1; + } + lv_disp_flush_ready(disp_drv); +} + +void nu_perf_monitor(struct _lv_disp_drv_t *disp_drv, uint32_t time, uint32_t px) +{ + rt_kprintf("Elapsed: %dms, Pixel: %d, Bytes:%d, %d%\n", time, px, px * sizeof(lv_color_t), px * 100 / disp_drv->draw_buf->size); +} + +void lv_port_disp_init(void) +{ + rt_err_t result; + void *buf1 = RT_NULL; + void *buf2 = RT_NULL; + uint32_t u32FBSize; + + lcd_device = rt_device_find("lcd"); + if (lcd_device == 0) + { + LOG_E("error!"); + return; + } + + /* get framebuffer address */ + result = rt_device_control(lcd_device, RTGRAPHIC_CTRL_GET_INFO, &info); + if (result != RT_EOK) + { + LOG_E("error!"); + /* get device information failed */ + return; + } + + /* Disable backlight at startup. */ + rt_device_control(lcd_device, RTGRAPHIC_CTRL_POWEROFF, RT_NULL); + + RT_ASSERT(info.bits_per_pixel == 8 || info.bits_per_pixel == 16 || + info.bits_per_pixel == 24 || info.bits_per_pixel == 32); + + lv_disp_drv_init(&disp_drv); /*Basic initialization*/ + + /*Set the resolution of the display*/ + disp_drv.hor_res = info.width; + disp_drv.ver_res = info.height; + disp_drv.full_refresh = 1; + //disp_drv.direct_mode = 1; + u32FBSize = info.height * info.width * (info.bits_per_pixel / 8); + + if (disp_drv.full_refresh || disp_drv.direct_mode) + { + buf1 = (void *)((uint32_t)info.framebuffer & (~UNCACHEABLE)); + buf2 = (void *)((uint32_t)buf1 + u32FBSize); + buf3_next = (void *)((uint32_t)buf2 + u32FBSize); + rt_kprintf("LVGL: Triple screen-sized buffers(%s) - buf1@%08x, buf2@%08x, buf3_next@%08x\n", (disp_drv.full_refresh == 1) ? "full_refresh" : "direct_mode", buf1, buf2, buf3_next); + + if (disp_drv.direct_mode) + disp_drv.flush_cb = nu_flush_direct; + else + disp_drv.flush_cb = nu_flush_full_refresh; + } + else + { + buf1 = (void *)(((uint32_t)info.framebuffer) + u32FBSize); + buf2 = (void *)((uint32_t)buf1 + u32FBSize); + rt_kprintf("LVGL: Two screen-sized buffers - buf1@%08x, buf2@%08x\n", buf1, buf2); + rt_device_control(lcd_device, RTGRAPHIC_CTRL_PAN_DISPLAY, info.framebuffer); + + disp_drv.flush_cb = nu_flush; + } + + /*Initialize `disp_buf` with the buffer(s).*/ + lv_disp_draw_buf_init(&disp_buf, buf1, buf2, info.width * info.height); + + result = rt_device_open(lcd_device, 0); + if (result != RT_EOK) + { + LOG_E("error!"); + return; + } + + /*Set a display buffer*/ + disp_drv.draw_buf = &disp_buf; + + /*Called after every refresh cycle to tell the rendering and flushing time + the number of flushed pixels*/ + //disp_drv.monitor_cb = nu_perf_monitor; + + /*Finally register the driver*/ + lv_disp_drv_register(&disp_drv); +} diff --git a/bsp/nuvoton/numaker-hmi-ma35d1/applications/lvgl/lv_port_disp.h b/bsp/nuvoton/numaker-hmi-ma35d1/applications/lvgl/lv_port_disp.h new file mode 100644 index 0000000000..b11ce3c5b6 --- /dev/null +++ b/bsp/nuvoton/numaker-hmi-ma35d1/applications/lvgl/lv_port_disp.h @@ -0,0 +1,23 @@ +/* + * Copyright (c) 2006-2022, RT-Thread Development Team + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + * 2021-10-18 Meco Man The first version + */ +#ifndef LV_PORT_DISP_H +#define LV_PORT_DISP_H + +#ifdef __cplusplus +extern "C" { +#endif + +void lv_port_disp_init(void); + +#ifdef __cplusplus +} /*extern "C"*/ +#endif + +#endif diff --git a/bsp/nuvoton/numaker-hmi-ma35d1/applications/lvgl/lv_port_indev.c b/bsp/nuvoton/numaker-hmi-ma35d1/applications/lvgl/lv_port_indev.c new file mode 100644 index 0000000000..b1f2e4c4b4 --- /dev/null +++ b/bsp/nuvoton/numaker-hmi-ma35d1/applications/lvgl/lv_port_indev.c @@ -0,0 +1,54 @@ +/* + * Copyright (c) 2006-2022, RT-Thread Development Team + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + * 2021-10-18 Meco Man The first version + * 2021-12-17 Wayne Add input event + */ +#include +#include +#include +#include "touch.h" + +static lv_indev_state_t last_state = LV_INDEV_STATE_REL; +static rt_int16_t last_x = 0; +static rt_int16_t last_y = 0; + +static void input_read(lv_indev_drv_t *indev_drv, lv_indev_data_t *data) +{ + data->point.x = last_x; + data->point.y = last_y; + data->state = last_state; +} + +void nu_touch_inputevent_cb(rt_int16_t x, rt_int16_t y, rt_uint8_t state) +{ + switch (state) + { + case RT_TOUCH_EVENT_UP: + last_state = LV_INDEV_STATE_RELEASED; + break; + case RT_TOUCH_EVENT_MOVE: + case RT_TOUCH_EVENT_DOWN: + last_x = x; + last_y = y; + last_state = LV_INDEV_STATE_PRESSED; + break; + } +} + +void lv_port_indev_init(void) +{ + static lv_indev_drv_t indev_drv; + + /* Basic initialization */ + lv_indev_drv_init(&indev_drv); + indev_drv.type = LV_INDEV_TYPE_POINTER; + indev_drv.read_cb = input_read; + + /* Register the driver in LVGL and save the created input device object */ + lv_indev_drv_register(&indev_drv); +} diff --git a/bsp/nuvoton/numaker-hmi-ma35d1/applications/lvgl/lv_port_indev.h b/bsp/nuvoton/numaker-hmi-ma35d1/applications/lvgl/lv_port_indev.h new file mode 100644 index 0000000000..bde7176807 --- /dev/null +++ b/bsp/nuvoton/numaker-hmi-ma35d1/applications/lvgl/lv_port_indev.h @@ -0,0 +1,28 @@ +/* + * Copyright (c) 2006-2022, RT-Thread Development Team + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + * 2021-10-18 Meco Man The first version + */ +#ifndef LV_PORT_INDEV_H +#define LV_PORT_INDEV_H + +#ifdef __cplusplus +extern "C" { +#endif + +#include + +extern lv_indev_t *button_indev; + +void lv_port_indev_init(void); +void lv_port_indev_input(rt_int16_t x, rt_int16_t y, lv_indev_state_t state); + +#ifdef __cplusplus +} /*extern "C"*/ +#endif + +#endif diff --git a/bsp/nuvoton/numaker-hmi-ma35d1/applications/main.c b/bsp/nuvoton/numaker-hmi-ma35d1/applications/main.c new file mode 100644 index 0000000000..4c781acff3 --- /dev/null +++ b/bsp/nuvoton/numaker-hmi-ma35d1/applications/main.c @@ -0,0 +1,71 @@ +/**************************************************************************//** +* +* @copyright (C) 2019 Nuvoton Technology Corp. All rights reserved. +* +* SPDX-License-Identifier: Apache-2.0 +* +* Change Logs: +* Date Author Notes +* 2021-6-1 Wayne First version +* +******************************************************************************/ + +#include +#include +#include "drv_common.h" + +#if defined(RT_USING_PIN) +#include "drv_gpio.h" + +/* defined the LED_0 pin: PJ14 */ +#define LED_0 NU_GET_PININDEX(NU_PJ, 14) + +int main(int argc, char **argv) +{ + int counter = 10000; + + /* set LED_0 pin mode to output */ + rt_pin_mode(LED_0, PIN_MODE_OUTPUT); + + while (counter--) + { + rt_pin_write(LED_0, PIN_HIGH); + rt_thread_mdelay(100); + rt_pin_write(LED_0, PIN_LOW); + rt_thread_mdelay(100); + } + + return 0; +} + +#else + +int main(int argc, char **argv) +{ + rt_kprintf("cpu-%d %d\r\n", rt_hw_cpu_id(), nu_cpu_dcache_line_size()); + return 0; +} + +#endif + +void happy_counter(void *pdata) +{ + uint32_t counter = 0; + while (1) + { + rt_kprintf("cpu-%d %d\r\n", rt_hw_cpu_id(), counter++); + rt_thread_mdelay(1000); + } +} + +void go_happy_counter(void) +{ + rt_thread_t tid = rt_thread_create("cpu-1", happy_counter, RT_NULL, 2048, 10, 20); + RT_ASSERT(tid != RT_NULL); + + rt_thread_control(tid, RT_THREAD_CTRL_BIND_CPU, (void *)1); + + rt_thread_startup(tid); +} +MSH_CMD_EXPORT(go_happy_counter, go happy counter); + diff --git a/bsp/nuvoton/numaker-hmi-ma35d1/applications/mnt.c b/bsp/nuvoton/numaker-hmi-ma35d1/applications/mnt.c new file mode 100644 index 0000000000..2ddb18f2ba --- /dev/null +++ b/bsp/nuvoton/numaker-hmi-ma35d1/applications/mnt.c @@ -0,0 +1,266 @@ +/**************************************************************************//** +* +* @copyright (C) 2019 Nuvoton Technology Corp. All rights reserved. +* +* SPDX-License-Identifier: Apache-2.0 +* +* Change Logs: +* Date Author Notes +* 2021-6-26 Wayne First version +* +******************************************************************************/ + +#include + +#define LOG_TAG "mnt" +#define DBG_ENABLE +#define DBG_SECTION_NAME "mnt" +#define DBG_LEVEL DBG_ERROR +#define DBG_COLOR +#include + +#include +#include +#include +#include +#include +#include + +#if defined(RT_USING_FAL) + #include +#endif + +#if defined(PKG_USING_RAMDISK) + #define RAMDISK_NAME "ramdisk0" + #define RAMDISK_UDC "ramdisk1" + #define MOUNT_POINT_RAMDISK0 "/" +#endif + +#if defined(BOARD_USING_STORAGE_SPIFLASH) + #define PARTITION_NAME_FILESYSTEM "filesystem" + #define MOUNT_POINT_SPIFLASH0 "/mnt/"PARTITION_NAME_FILESYSTEM +#endif + +#ifdef RT_USING_DFS_MNTTABLE + +/* +const char *device_name; +const char *path; +const char *filesystemtype; +unsigned long rwflag; +const void *data; +*/ + +const struct dfs_mount_tbl mount_table[] = +{ +#if defined(PKG_USING_RAMDISK) + { RAMDISK_UDC, "/mnt/ram_usbd", "elm", 0, RT_NULL }, +#endif +#if defined(PKG_USING_DFS_YAFFS) + { "nand1", "/mnt/filesystem", "yaffs", 0, RT_NULL }, +#elif defined(RT_USING_DFS_UFFS) + { "nand1", "/mnt/filesystem", "uffs", 0, RT_NULL }, +#endif + { "sd0", "/mnt/sd0", "elm", 0, RT_NULL }, + { "sd0p0", "/mnt/sd0p0", "elm", 0, RT_NULL }, + { "sd0p1", "/mnt/sd0p1", "elm", 0, RT_NULL }, + { "sd1", "/mnt/sd1", "elm", 0, RT_NULL }, + { "sd1p0", "/mnt/sd1p0", "elm", 0, RT_NULL }, + { "sd1p1", "/mnt/sd1p1", "elm", 0, RT_NULL }, + {0}, +}; +#endif + + +#if defined(PKG_USING_RAMDISK) + +extern rt_err_t ramdisk_init(const char *dev_name, rt_uint8_t *disk_addr, rt_size_t block_size, rt_size_t num_block); +int ramdisk_device_init(void) +{ + rt_err_t result = RT_EOK; + + /* Create a 16MB RAMDISK */ + result = ramdisk_init(RAMDISK_NAME, NULL, 512, 16 * 4096); + RT_ASSERT(result == RT_EOK); + + /* Create a 16MB RAMDISK */ + result = ramdisk_init(RAMDISK_UDC, NULL, 512, 16 * 4096); + RT_ASSERT(result == RT_EOK); + + return 0; +} +INIT_DEVICE_EXPORT(ramdisk_device_init); + +/* Recursive mkdir */ +static int mkdir_p(const char *dir, const mode_t mode) +{ + int ret = -1; + char *tmp = NULL; + char *p = NULL; + struct stat sb; + rt_size_t len; + + if (!dir) + goto exit_mkdir_p; + + /* Copy path */ + /* Get the string length */ + len = strlen(dir); + tmp = rt_strdup(dir); + + /* Remove trailing slash */ + if (tmp[len - 1] == '/') + { + tmp[len - 1] = '\0'; + len--; + } + + /* check if path exists and is a directory */ + if (stat(tmp, &sb) == 0) + { + if (S_ISDIR(sb.st_mode)) + { + ret = 0; + goto exit_mkdir_p; + } + } + + /* Recursive mkdir */ + for (p = tmp + 1; p - tmp <= len; p++) + { + if ((*p == '/') || (p - tmp == len)) + { + *p = 0; + + /* Test path */ + if (stat(tmp, &sb) != 0) + { + /* Path does not exist - create directory */ + if (mkdir(tmp, mode) < 0) + { + goto exit_mkdir_p; + } + } + else if (!S_ISDIR(sb.st_mode)) + { + /* Not a directory */ + goto exit_mkdir_p; + } + if (p - tmp != len) + *p = '/'; + } + } + + ret = 0; + +exit_mkdir_p: + + if (tmp) + rt_free(tmp); + + return ret; +} + +#if defined(PKG_USING_DFS_YAFFS) && defined(RT_USING_DFS_MNTTABLE) +#include "yaffs_guts.h" +void yaffs_dev_init(void) +{ + int i; + for (i = 0; i < sizeof(mount_table) / sizeof(struct dfs_mount_tbl); i++) + { + if (mount_table[i].filesystemtype && !rt_strcmp(mount_table[i].filesystemtype, "yaffs")) + { + struct rt_mtd_nand_device *psMtdNandDev = RT_MTD_NAND_DEVICE(rt_device_find(mount_table[i].device_name)); + if (psMtdNandDev) + { + yaffs_start_up(psMtdNandDev, (const char *)mount_table[i].path); + } + } + } +} +#endif + +/* Initialize the filesystem */ +int filesystem_init(void) +{ + rt_err_t result = RT_EOK; + +#if defined(RT_USING_FAL) + extern int fal_init_check(void); + if (!fal_init_check()) + fal_init(); +#endif + + // ramdisk as root + if (!rt_device_find(RAMDISK_NAME)) + { + LOG_E("cannot find %s device", RAMDISK_NAME); + result = -RT_ERROR; + goto exit_filesystem_init; + } + else + { + /* Format these ramdisk */ + result = (rt_err_t)dfs_mkfs("elm", RAMDISK_NAME); + RT_ASSERT(result == RT_EOK); + + /* mount ramdisk0 as root directory */ + if (dfs_mount(RAMDISK_NAME, "/", "elm", 0, RT_NULL) == 0) + { + LOG_I("ramdisk mounted on \"/\"."); + + /* now you can create dir dynamically. */ + mkdir_p("/mnt", 0x777); + mkdir_p("/cache", 0x777); + mkdir_p("/download", 0x777); + mkdir_p("/mnt/ram_usbd", 0x777); + mkdir_p("/mnt/filesystem", 0x777); + mkdir_p("/mnt/sd0", 0x777); + mkdir_p("/mnt/sd0p0", 0x777); + mkdir_p("/mnt/sd0p1", 0x777); + mkdir_p("/mnt/sd1", 0x777); + mkdir_p("/mnt/sd1p0", 0x777); + mkdir_p("/mnt/sd1p1", 0x777); +#if defined(RT_USBH_MSTORAGE) && defined(UDISK_MOUNTPOINT) + mkdir_p(UDISK_MOUNTPOINT, 0x777); +#endif + } + else + { + LOG_E("root folder creation failed!\n"); + goto exit_filesystem_init; + } + } + + if (!rt_device_find(RAMDISK_UDC)) + { + LOG_E("cannot find %s device", RAMDISK_UDC); + goto exit_filesystem_init; + } + else + { + /* Format these ramdisk */ + result = (rt_err_t)dfs_mkfs("elm", RAMDISK_UDC); + RT_ASSERT(result == RT_EOK); + } + +#if defined(BOARD_USING_STORAGE_SPIFLASH) + { + struct rt_device *psNorFlash = fal_blk_device_create(PARTITION_NAME_FILESYSTEM); + if (!psNorFlash) + { + rt_kprintf("Failed to create block device for %s.\n", PARTITION_NAME_FILESYSTEM); + } + } +#endif + +#if defined(PKG_USING_DFS_YAFFS) && defined(RT_USING_DFS_MNTTABLE) + yaffs_dev_init(); +#endif + +exit_filesystem_init: + + return -result; +} +INIT_ENV_EXPORT(filesystem_init); +#endif diff --git a/bsp/nuvoton/numaker-hmi-ma35d1/board/Kconfig b/bsp/nuvoton/numaker-hmi-ma35d1/board/Kconfig new file mode 100644 index 0000000000..2fbf0bf116 --- /dev/null +++ b/bsp/nuvoton/numaker-hmi-ma35d1/board/Kconfig @@ -0,0 +1,154 @@ +menu "Hardware Drivers Config" + + menu "On-chip Peripheral Drivers" + source "$BSP_DIR/../libraries/ma35/rtt_port/Kconfig" + endmenu + + menu "On-board Peripheral Drivers" + + config BSP_USING_CONSOLE + bool "Enable UART0 for RTT Console(uart0)" + select BSP_USING_UART + select BSP_USING_UART0 + default y + + config BOARD_USING_NAU8822 + bool "NAU8822 Audio Codec supporting(over i2s0, i2c2)" + select NU_PKG_USING_NAU8822 + select BSP_USING_I2C2 + select BSP_USING_I2S + select BSP_USING_I2S0 + default n + + config BOARD_USING_STORAGE_SDCARD + bool "SDCARD supporting(over sdh0)" + select BSP_USING_SDH + select BSP_USING_SDH0 + default y + + config BOARD_USING_STORAGE_EMMC + bool "EMMC supporting(over sdh1)" + select BSP_USING_SDH + select BSP_USING_SDH1 + default y + + config BOARD_USING_STORAGE_SPIFLASH + bool "SPI NOR FLASH supporting(over qspi0)" + select BSP_USING_QSPI + select BSP_USING_QSPI0 + default n + + config BOARD_USING_STORAGE_SPINAND + bool "SPI NAND FLASH supporting(over qspi0)" + select BSP_USING_QSPI + select BSP_USING_QSPI0 + select NU_PKG_USING_SPINAND + default y + + config BOARD_USING_BUZZER + bool "BUZZER function(over epwm1_ch5)" + select BSP_USING_EPWM + select BSP_USING_EPWM1 + select BSP_USING_EPWM1_PWM + default y + + config BOARD_USING_USBHOST + bool "USB HOST function" + select BSP_USING_USBH + default y + + endmenu + + menu "Board extended module drivers" + + config BOARD_USING_LCM + bool "Use LCD panel." + default y + + if BOARD_USING_LCM + + choice + prompt "Select LCD panel devices.(Over DISP)" + default BOARD_USING_LCM_FW070TFT_WSVGA + + config BOARD_USING_LCM_FW070TFT_WVGA + bool "NuDesign TFT-LCD7-WVGA" + select BSP_USING_DISP + select LCM_USING_FW070TFT + help + Choose this option if you use 7" 800x480x32b LCD panel. + + config BOARD_USING_LCM_FW070TFT_WSVGA + bool "NuDesign TFT-LCD7-WSVGA" + select BSP_USING_DISP + select LCM_USING_FW070TFT_WSVGA + help + Choose this option if you use 7" 1024x600x32b LCD panel. + endchoice + + choice + prompt "Select Touch devices." + default BOARD_USING_GT911 + + config BOARD_USING_GT911 + bool "GT911 TPC" + select BSP_USING_I2C + select BSP_USING_I2C0 + select NU_PKG_USING_TPC_GT911 + help + Choose this option if you use GT911 external TSC touching function. + + config BOARD_USING_ADCTOUCH + bool "ADC touching" + select BSP_USING_ADC_TOUCH + select NU_PKG_USING_ADC_TOUCH + help + Choose this option if you use internal ADC touching function. + + endchoice + endif + + + + config BOARD_USING_SENSOR0 + bool "CCAP-SENSOR PORT0(over i2c3/PM1/PK8)" + select BSP_USING_I2C + select BSP_USING_I2C3 + select BSP_USING_CCAP + select BSP_USING_CCAP0 + default n + + if BOARD_USING_SENSOR0 + config BOARD_USING_SENSON0_ID + int "Specify Sensor0 ID" + default 0 if BOARD_USING_SENSOR0 + range 0 2 + help + HM1055=0 + ADV728X=1 + endif + + config BOARD_USING_SENSOR1 + bool "CCAP-SENSOR PORT1(over i2c4/PN14/PD15)" + select BSP_USING_I2C + select BSP_USING_I2C4 + select BSP_USING_CCAP + select BSP_USING_CCAP1 + default n + + if BOARD_USING_SENSOR1 + config BOARD_USING_SENSON1_ID + int "Specify Sensor1 ID" + default 0 + range 0 2 + help + HM1055=0 + ADV728X=1 + endif + + + endmenu + + source "$BSP_DIR/../libraries/nu_packages/Kconfig" + +endmenu diff --git a/bsp/nuvoton/numaker-hmi-ma35d1/board/SConscript b/bsp/nuvoton/numaker-hmi-ma35d1/board/SConscript new file mode 100644 index 0000000000..38791565a2 --- /dev/null +++ b/bsp/nuvoton/numaker-hmi-ma35d1/board/SConscript @@ -0,0 +1,18 @@ +# RT-Thread building script for component + +from building import * + + +Import('RTT_ROOT') +from building import * + +cwd = GetCurrentDir() +src = Split(""" +nutool_pincfg/nutool_pincfg.c +""") +src += Glob('*.c') + Glob('*.cpp') + Glob('*.S') +CPPPATH = [cwd, cwd + '/nutool_pincfg'] + +group = DefineGroup('board', src, depend = [''], CPPPATH = CPPPATH) + +Return('group') diff --git a/bsp/nuvoton/numaker-hmi-ma35d1/board/board.h b/bsp/nuvoton/numaker-hmi-ma35d1/board/board.h new file mode 100644 index 0000000000..5d422bcf19 --- /dev/null +++ b/bsp/nuvoton/numaker-hmi-ma35d1/board/board.h @@ -0,0 +1,39 @@ +/**************************************************************************//** +* +* @copyright (C) 2019 Nuvoton Technology Corp. All rights reserved. +* +* SPDX-License-Identifier: Apache-2.0 +* +* Change Logs: +* Date Author Notes +* 2021-6-1 Wayne First version +* +******************************************************************************/ + +#ifndef __BOARD_H__ +#define __BOARD_H__ + +#include "NuMicro.h" +#include "drv_sys.h" +#include "nutool_pincfg.h" + +#define BOARD_SDRAM_START 0x80400000 +#define BOARD_SDRAM_SIZE 0x0FC00000 + +#define BOARD_HEAP_END ((void*)(BOARD_SDRAM_START+BOARD_SDRAM_SIZE)) +#define BOARD_HEAP_START ((void *)&__bss_end) + +extern int __bss_end; + +#if defined(RT_USING_MTD_NAND) + #include + #define MTD_SPINAND_PARTITION_NUM 3 + extern struct rt_mtd_nand_device mtd_partitions[MTD_SPINAND_PARTITION_NUM]; +#endif +extern void rt_hw_board_init(void); +extern void nu_clock_init(void); +extern void nu_clock_deinit(void); +extern void nu_pin_init(void); +extern void nu_pin_deinit(void); + +#endif /* BOARD_H_ */ diff --git a/bsp/nuvoton/numaker-hmi-ma35d1/board/board_dev.c b/bsp/nuvoton/numaker-hmi-ma35d1/board/board_dev.c new file mode 100644 index 0000000000..97959fc4a4 --- /dev/null +++ b/bsp/nuvoton/numaker-hmi-ma35d1/board/board_dev.c @@ -0,0 +1,611 @@ +/**************************************************************************//** +* +* @copyright (C) 2019 Nuvoton Technology Corp. All rights reserved. +* +* SPDX-License-Identifier: Apache-2.0 +* +* Change Logs: +* Date Author Notes +* 2021-6-1 Wayne First version +* +******************************************************************************/ + +#include +#include +#include "drv_gpio.h" +#include "drv_sys.h" +#include "board.h" + + +#if defined(BOARD_USING_STORAGE_SPIFLASH) +#if defined(RT_USING_SFUD) + #include "spi_flash.h" + #include "spi_flash_sfud.h" +#endif + +#include "drv_qspi.h" + +#define W25X_REG_READSTATUS (0x05) +#define W25X_REG_READSTATUS2 (0x35) +#define W25X_REG_WRITEENABLE (0x06) +#define W25X_REG_WRITESTATUS (0x01) +#define W25X_REG_QUADENABLE (0x02) + +static rt_uint8_t SpiFlash_ReadStatusReg(struct rt_qspi_device *qspi_device) +{ + rt_uint8_t u8Val; + rt_err_t result = RT_EOK; + rt_uint8_t w25x_txCMD1 = W25X_REG_READSTATUS; + + result = rt_qspi_send_then_recv(qspi_device, &w25x_txCMD1, 1, &u8Val, 1); + RT_ASSERT(result > 0); + + return u8Val; +} + +static rt_uint8_t SpiFlash_ReadStatusReg2(struct rt_qspi_device *qspi_device) +{ + rt_uint8_t u8Val; + rt_err_t result = RT_EOK; + rt_uint8_t w25x_txCMD1 = W25X_REG_READSTATUS2; + + result = rt_qspi_send_then_recv(qspi_device, &w25x_txCMD1, 1, &u8Val, 1); + RT_ASSERT(result > 0); + + return u8Val; +} + +static rt_err_t SpiFlash_WriteStatusReg(struct rt_qspi_device *qspi_device, uint8_t u8Value1, uint8_t u8Value2) +{ + rt_uint8_t w25x_txCMD1; + rt_uint8_t au8Val[2]; + rt_err_t result; + struct rt_qspi_message qspi_message = {0}; + + /* Enable WE */ + w25x_txCMD1 = W25X_REG_WRITEENABLE; + result = rt_qspi_send(qspi_device, &w25x_txCMD1, sizeof(w25x_txCMD1)); + if (result != sizeof(w25x_txCMD1)) + goto exit_SpiFlash_WriteStatusReg; + + /* Prepare status-1, 2 data */ + au8Val[0] = u8Value1; + au8Val[1] = u8Value2; + + /* 1-bit mode: Instruction+payload */ + qspi_message.instruction.content = W25X_REG_WRITESTATUS; + qspi_message.instruction.qspi_lines = 1; + + qspi_message.qspi_data_lines = 1; + qspi_message.parent.cs_take = 1; + qspi_message.parent.cs_release = 1; + qspi_message.parent.send_buf = &au8Val[0]; + qspi_message.parent.length = sizeof(au8Val); + qspi_message.parent.next = RT_NULL; + + if (rt_qspi_transfer_message(qspi_device, &qspi_message) != sizeof(au8Val)) + { + result = -RT_ERROR; + } + + result = RT_EOK; + +exit_SpiFlash_WriteStatusReg: + + return result; +} + +static void SpiFlash_WaitReady(struct rt_qspi_device *qspi_device) +{ + volatile uint8_t u8ReturnValue; + + do + { + u8ReturnValue = SpiFlash_ReadStatusReg(qspi_device); + u8ReturnValue = u8ReturnValue & 1; + } + while (u8ReturnValue != 0); // check the BUSY bit +} + +static void SpiFlash_EnterQspiMode(struct rt_qspi_device *qspi_device) +{ + rt_err_t result = RT_EOK; + + uint8_t u8Status1 = SpiFlash_ReadStatusReg(qspi_device); + uint8_t u8Status2 = SpiFlash_ReadStatusReg2(qspi_device); + + u8Status2 |= W25X_REG_QUADENABLE; + + result = SpiFlash_WriteStatusReg(qspi_device, u8Status1, u8Status2); + RT_ASSERT(result == RT_EOK); + + SpiFlash_WaitReady(qspi_device); +} + +static void SpiFlash_ExitQspiMode(struct rt_qspi_device *qspi_device) +{ + rt_err_t result = RT_EOK; + uint8_t u8Status1 = SpiFlash_ReadStatusReg(qspi_device); + uint8_t u8Status2 = SpiFlash_ReadStatusReg2(qspi_device); + + u8Status2 &= ~W25X_REG_QUADENABLE; + + result = SpiFlash_WriteStatusReg(qspi_device, u8Status1, u8Status2); + RT_ASSERT(result == RT_EOK); + + SpiFlash_WaitReady(qspi_device); +} + +static int rt_hw_spiflash_init(void) +{ + if (nu_qspi_bus_attach_device("qspi0", "qspi01", 4, SpiFlash_EnterQspiMode, SpiFlash_ExitQspiMode) != RT_EOK) + return -1; + +#if defined(RT_USING_SFUD) + if (rt_sfud_flash_probe(FAL_USING_NOR_FLASH_DEV_NAME, "qspi01") == RT_NULL) + { + return -(RT_ERROR); + } +#endif + return 0; +} +INIT_COMPONENT_EXPORT(rt_hw_spiflash_init); +#endif /* BOARD_USING_STORAGE_SPIFLASH */ + +#if defined(BOARD_USING_STORAGE_SPINAND) && defined(NU_PKG_USING_SPINAND) + +#include "drv_qspi.h" +#include "spinand.h" + +struct rt_mtd_nand_device mtd_partitions[MTD_SPINAND_PARTITION_NUM] = +{ + [0] = + { + /*nand0: U-boot, env, rtthread*/ + .block_start = 0, + .block_end = 63, + .block_total = 64, + }, + [1] = + { + /*nand1: for filesystem mounting*/ + .block_start = 64, + .block_end = 4095, + .block_total = 4032, + }, + [2] = + { + /*nand2: Whole blocks size, overlay*/ + .block_start = 0, + .block_end = 4095, + .block_total = 4096, + } +}; + +static int rt_hw_spinand_init(void) +{ + if (nu_qspi_bus_attach_device("qspi0", "qspi01", 4, RT_NULL, RT_NULL) != RT_EOK) + return -1; + + if (rt_hw_mtd_spinand_register("qspi01") != RT_EOK) + return -1; + + return 0; +} + +INIT_COMPONENT_EXPORT(rt_hw_spinand_init); +#endif + +#if defined(BOARD_USING_NAU8822) && defined(NU_PKG_USING_NAU8822) +#include +S_NU_NAU8822_CONFIG sCodecConfig = +{ + .i2c_bus_name = "i2c2", + + .i2s_bus_name = "sound0", + + .pin_phonejack_en = NU_GET_PININDEX(NU_PD, 13), + + .pin_phonejack_det = NU_GET_PININDEX(NU_PI, 0), +}; + +int rt_hw_nau8822_port(void) +{ + if (nu_hw_nau8822_init(&sCodecConfig) != RT_EOK) + return -1; + + return 0; +} +INIT_COMPONENT_EXPORT(rt_hw_nau8822_port); +#endif /* BOARD_USING_NAU8822 */ + +#if defined(NU_PKG_USING_ADC_TOUCH) +#include "adc_touch.h" +S_CALIBRATION_MATRIX g_sCalMat = { -17558, 1, 69298832, -10, 11142, -2549195, 65536 }; +#endif + +#if defined(NU_PKG_USING_TPC_GT911) && defined(BOARD_USING_GT911) +#include "drv_gpio.h" +#include "gt911.h" + +#define TPC_RST_PIN NU_GET_PININDEX(NU_PM, 12) +#define TPC_IRQ_PIN NU_GET_PININDEX(NU_PD, 12) + +extern int tpc_sample(const char *name); +int rt_hw_gt911_port(void) +{ + struct rt_touch_config cfg; + rt_uint8_t rst_pin; + + rst_pin = TPC_RST_PIN; + cfg.dev_name = "i2c5"; + cfg.irq_pin.pin = TPC_IRQ_PIN; + cfg.irq_pin.mode = PIN_MODE_INPUT_PULLDOWN; + cfg.user_data = &rst_pin; + + rt_hw_gt911_init("gt911", &cfg); + + return tpc_sample("gt911"); +} +INIT_ENV_EXPORT(rt_hw_gt911_port); +#endif /* if defined(BOARD_USING_GT911) && defined(PKG_USING_GT911) */ + +#if defined(BOARD_USING_BUZZER) + +#define EPWM_DEV_NAME "epwm1" +#define EPWM_DEV_CHANNEL (5) + +static void PlayRingTone(void) +{ + struct rt_device_pwm *epwm_dev; + rt_uint32_t period; + int i, j; + + period = 1000; + + if ((epwm_dev = (struct rt_device_pwm *)rt_device_find(EPWM_DEV_NAME)) != RT_NULL) + { + rt_pwm_set(epwm_dev, EPWM_DEV_CHANNEL, period, period); + rt_pwm_enable(epwm_dev, EPWM_DEV_CHANNEL); + + for (j = 0; j < 5; j++) + { + for (i = 0; i < 10; i++) + { + rt_pwm_set(epwm_dev, EPWM_DEV_CHANNEL, period, period); + rt_thread_mdelay(50); + + rt_pwm_set(epwm_dev, EPWM_DEV_CHANNEL, period, period / 2); + rt_thread_mdelay(50); + } + + /* Mute 2 seconds */ + rt_pwm_set(epwm_dev, EPWM_DEV_CHANNEL, period, period); + rt_thread_mdelay(2000); + } + rt_pwm_disable(epwm_dev, EPWM_DEV_CHANNEL); + } + else + { + rt_kprintf("Can't find %s\n", EPWM_DEV_NAME); + } +} + +#if defined(BOARD_USING_LCM) + +#if defined(PKG_USING_GUIENGINE) + #include +#endif + +#if defined(RT_USING_PIN) + #include + + /* defined the LCM_BLEN pin: PK7 */ + #define LCM_BACKLIGHT_CTRL NU_GET_PININDEX(NU_PK, 7) +#endif + +#define EPWM_DEV_NAME "epwm1" +#define LCM_PWM_CHANNEL (1) + +void nu_lcd_backlight_on(void) +{ + struct rt_device_pwm *pwm_dev; + + if ((pwm_dev = (struct rt_device_pwm *)rt_device_find(EPWM_DEV_NAME)) != RT_NULL) + { + rt_pwm_enable(pwm_dev, LCM_PWM_CHANNEL); + rt_pwm_set(pwm_dev, LCM_PWM_CHANNEL, 100000, 100); + } + else + { + rt_kprintf("Can't find %s\n", EPWM_DEV_NAME); + } + + rt_pin_mode(LCM_BACKLIGHT_CTRL, PIN_MODE_OUTPUT); + rt_pin_write(LCM_BACKLIGHT_CTRL, PIN_HIGH); +} + +void nu_lcd_backlight_off(void) +{ + struct rt_device_pwm *pwm_dev; + + if ((pwm_dev = (struct rt_device_pwm *)rt_device_find(EPWM_DEV_NAME)) != RT_NULL) + { + rt_pwm_disable(pwm_dev, LCM_PWM_CHANNEL); + } + else + { + rt_kprintf("Can't find %s\n", EPWM_DEV_NAME); + } + + rt_pin_mode(LCM_BACKLIGHT_CTRL, PIN_MODE_OUTPUT); + rt_pin_write(LCM_BACKLIGHT_CTRL, PIN_LOW); +} + +int rt_hw_lcm_port(void) +{ +#if defined(PKG_USING_GUIENGINE) + rt_device_t lcm_vpost; + lcm_vpost = rt_device_find("lcd"); + if (lcm_vpost) + { + rtgui_graphic_set_device(lcm_vpost); + } +#endif + + return 0; +} +INIT_COMPONENT_EXPORT(rt_hw_lcm_port); +#endif /* BOARD_USING_LCM */ + +int buzzer_test(void) +{ + PlayRingTone(); + return 0; +} +#ifdef FINSH_USING_MSH + MSH_CMD_EXPORT(buzzer_test, Buzzer - Play ring tone); +#endif +#endif /* BOARD_USING_BUZZER */ + +#if defined(BOARD_USING_SENSOR0) +#include "ccap_sensor.h" + +#define SENSOR0_RST_PIN NU_GET_PININDEX(NU_PM, 1) +#define SENSOR0_PD_PIN NU_GET_PININDEX(NU_PK, 8) + +ccap_sensor_io sIo_sensor0 = +{ + .RstPin = SENSOR0_RST_PIN, + .PwrDwnPin = SENSOR0_PD_PIN, + .I2cName = "i2c3" +}; +#endif /* BOARD_USING_SENSOR0 */ + +#if defined(BOARD_USING_SENSOR1) +#include "ccap_sensor.h" + +#define SENSOR1_RST_PIN NU_GET_PININDEX(NU_PN, 14) +#define SENSOR1_PD_PIN NU_GET_PININDEX(NU_PD, 15) + +ccap_sensor_io sIo_sensor1 = +{ + .RstPin = SENSOR1_RST_PIN, + .PwrDwnPin = SENSOR1_PD_PIN, + .I2cName = "i2c4" +}; +#endif /* BOARD_USING_SENSOR1 */ + +int rt_hw_sensors_port(void) +{ +#if defined(BOARD_USING_SENSOR0) + nu_ccap_sensor_create(&sIo_sensor0, (ccap_sensor_id)BOARD_USING_SENSON0_ID, "sensor0"); +#endif +#if defined(BOARD_USING_SENSOR1) + nu_ccap_sensor_create(&sIo_sensor1, (ccap_sensor_id)BOARD_USING_SENSON1_ID, "sensor1"); +#endif + return 0; +} +INIT_COMPONENT_EXPORT(rt_hw_sensors_port); + + +void nu_rtp_sspcc_setup(void) +{ + SSPCC_SET_REALM(SSPCC_UART16, SSPCC_SSET_SUBM); + SSPCC_SET_REALM(SSPCC_TMR23, SSPCC_SSET_SUBM); + + /* PDMA2/3 */ + SSPCC_SET_REALM(SSPCC_PDMA2, SSPCC_SSET_SUBM); + SSPCC_SET_REALM(SSPCC_PDMA3, SSPCC_SSET_SUBM); + + /* UART16 Pins */ + SSPCC_SET_GPIO_REALM(PK, 0, SSPCC_SSET_SUBM); + SSPCC_SET_GPIO_REALM(PK, 1, SSPCC_SSET_SUBM); + SSPCC_SET_GPIO_REALM(PK, 2, SSPCC_SSET_SUBM); + SSPCC_SET_GPIO_REALM(PK, 3, SSPCC_SSET_SUBM); + + /* LED_1 Pin */ + SSPCC_SET_GPIO_REALM(PJ, 15, SSPCC_SSET_SUBM); +} + +#define CLK_CLKDIV0_DCUPDIV_2 CLK_CLKDIV0_DCUP(1) +#define DISP_FRAMEBUFFERCONFIG0 (DISP_BASE + 0x1518U) +#define DISP_OVERLAYCONFIG0 (DISP_BASE + 0x1540U) + +static S_NU_REG s_NuReg_arr[] = +{ + /* DISP PIN */ + NUREG_EXPORT(SYS_GPH_MFPH, SYS_GPH_MFPH_PH15MFP_Msk, SYS_GPH_MFPH_PH15MFP_LCM_DATA23), + NUREG_EXPORT(SYS_GPH_MFPH, SYS_GPH_MFPH_PH14MFP_Msk, SYS_GPH_MFPH_PH14MFP_LCM_DATA22), + NUREG_EXPORT(SYS_GPH_MFPH, SYS_GPH_MFPH_PH13MFP_Msk, SYS_GPH_MFPH_PH13MFP_LCM_DATA21), + NUREG_EXPORT(SYS_GPH_MFPH, SYS_GPH_MFPH_PH12MFP_Msk, SYS_GPH_MFPH_PH12MFP_LCM_DATA20), + + NUREG_EXPORT(SYS_GPC_MFPH, SYS_GPC_MFPH_PC15MFP_Msk, SYS_GPC_MFPH_PC15MFP_LCM_DATA19), + NUREG_EXPORT(SYS_GPC_MFPH, SYS_GPC_MFPH_PC14MFP_Msk, SYS_GPC_MFPH_PC14MFP_LCM_DATA18), + NUREG_EXPORT(SYS_GPC_MFPH, SYS_GPC_MFPH_PC13MFP_Msk, SYS_GPC_MFPH_PC13MFP_LCM_DATA17), + NUREG_EXPORT(SYS_GPC_MFPH, SYS_GPC_MFPH_PC12MFP_Msk, SYS_GPC_MFPH_PC12MFP_LCM_DATA16), + + NUREG_EXPORT(SYS_GPH_MFPL, SYS_GPH_MFPL_PH7MFP_Msk, SYS_GPH_MFPL_PH7MFP_LCM_DATA15), + NUREG_EXPORT(SYS_GPH_MFPL, SYS_GPH_MFPL_PH6MFP_Msk, SYS_GPH_MFPL_PH6MFP_LCM_DATA14), + NUREG_EXPORT(SYS_GPH_MFPL, SYS_GPH_MFPL_PH5MFP_Msk, SYS_GPH_MFPL_PH5MFP_LCM_DATA13), + NUREG_EXPORT(SYS_GPH_MFPL, SYS_GPH_MFPL_PH4MFP_Msk, SYS_GPH_MFPL_PH4MFP_LCM_DATA12), + NUREG_EXPORT(SYS_GPH_MFPL, SYS_GPH_MFPL_PH3MFP_Msk, SYS_GPH_MFPL_PH3MFP_LCM_DATA11), + NUREG_EXPORT(SYS_GPH_MFPL, SYS_GPH_MFPL_PH2MFP_Msk, SYS_GPH_MFPL_PH2MFP_LCM_DATA10), + NUREG_EXPORT(SYS_GPH_MFPL, SYS_GPH_MFPL_PH1MFP_Msk, SYS_GPH_MFPL_PH1MFP_LCM_DATA9), + NUREG_EXPORT(SYS_GPH_MFPL, SYS_GPH_MFPL_PH0MFP_Msk, SYS_GPH_MFPL_PH0MFP_LCM_DATA8), + + NUREG_EXPORT(SYS_GPI_MFPH, SYS_GPI_MFPH_PI15MFP_Msk, SYS_GPI_MFPH_PI15MFP_LCM_DATA7), + NUREG_EXPORT(SYS_GPI_MFPH, SYS_GPI_MFPH_PI14MFP_Msk, SYS_GPI_MFPH_PI14MFP_LCM_DATA6), + NUREG_EXPORT(SYS_GPI_MFPH, SYS_GPI_MFPH_PI13MFP_Msk, SYS_GPI_MFPH_PI13MFP_LCM_DATA5), + NUREG_EXPORT(SYS_GPI_MFPH, SYS_GPI_MFPH_PI12MFP_Msk, SYS_GPI_MFPH_PI12MFP_LCM_DATA4), + NUREG_EXPORT(SYS_GPI_MFPH, SYS_GPI_MFPH_PI11MFP_Msk, SYS_GPI_MFPH_PI11MFP_LCM_DATA3), + NUREG_EXPORT(SYS_GPI_MFPH, SYS_GPI_MFPH_PI10MFP_Msk, SYS_GPI_MFPH_PI10MFP_LCM_DATA2), + NUREG_EXPORT(SYS_GPI_MFPH, SYS_GPI_MFPH_PI9MFP_Msk, SYS_GPI_MFPH_PI9MFP_LCM_DATA1), + NUREG_EXPORT(SYS_GPI_MFPH, SYS_GPI_MFPH_PI8MFP_Msk, SYS_GPI_MFPH_PI8MFP_LCM_DATA0), + + NUREG_EXPORT(SYS_GPK_MFPL, SYS_GPK_MFPL_PK4MFP_Msk, SYS_GPK_MFPL_PK4MFP_LCM_DEN), + + NUREG_EXPORT(SYS_GPG_MFPH, SYS_GPG_MFPH_PG10MFP_Msk, SYS_GPG_MFPH_PG10MFP_LCM_CLK), + NUREG_EXPORT(SYS_GPG_MFPH, SYS_GPG_MFPH_PG9MFP_Msk, SYS_GPG_MFPH_PG9MFP_LCM_HSYNC), + NUREG_EXPORT(SYS_GPG_MFPH, SYS_GPG_MFPH_PG8MFP_Msk, SYS_GPG_MFPH_PG8MFP_LCM_VSYNC), + + /* DISP CLK */ + NUREG_EXPORT(CLK_SYSCLK0, CLK_SYSCLK0_DCUEN_Msk, CLK_SYSCLK0_DCUEN_Msk), + + /* DISP Engine */ + NUREG_EXPORT(DISP_FRAMEBUFFERCONFIG0, DISP_FrameBufferConfig0_UNDERFLOW_Msk, DISP_FrameBufferConfig0_UNDERFLOW_Msk), + NUREG_EXPORT(DISP_OVERLAYCONFIG0, DISP_OverlayConfig0_UNDERFLOW_Msk, DISP_OverlayConfig0_UNDERFLOW_Msk), + + /* I2C5 */ + NUREG_EXPORT(SYS_GPJ_MFPH, SYS_GPJ_MFPH_PJ12MFP_Msk, SYS_GPJ_MFPH_PJ12MFP_I2C5_SDA), + NUREG_EXPORT(SYS_GPJ_MFPH, SYS_GPJ_MFPH_PJ13MFP_Msk, SYS_GPJ_MFPH_PJ13MFP_I2C5_SCL), + + /* GPD12, PM12 */ + NUREG_EXPORT(SYS_GPD_MFPH, SYS_GPD_MFPH_PD12MFP_Msk, (0 << SYS_GPD_MFPH_PD12MFP_Pos)), + NUREG_EXPORT(SYS_GPM_MFPH, SYS_GPM_MFPH_PM12MFP_Msk, (0 << SYS_GPM_MFPH_PM12MFP_Pos)), + + /* QSPI0 */ + NUREG_EXPORT(CLK_CLKSEL4, CLK_CLKSEL4_QSPI0SEL_Msk, CLK_CLKSEL4_QSPI0SEL_PCLK0), + NUREG_EXPORT(CLK_APBCLK1, CLK_APBCLK1_QSPI0CKEN_Msk, CLK_APBCLK1_QSPI0CKEN_Msk), + NUREG_EXPORT(SYS_GPD_MFPL, SYS_GPD_MFPL_PD5MFP_Msk, SYS_GPD_MFPL_PD5MFP_QSPI0_MISO1), + NUREG_EXPORT(SYS_GPD_MFPL, SYS_GPD_MFPL_PD4MFP_Msk, SYS_GPD_MFPL_PD4MFP_QSPI0_MOSI1), + NUREG_EXPORT(SYS_GPD_MFPL, SYS_GPD_MFPL_PD3MFP_Msk, SYS_GPD_MFPL_PD3MFP_QSPI0_MISO0), + NUREG_EXPORT(SYS_GPD_MFPL, SYS_GPD_MFPL_PD2MFP_Msk, SYS_GPD_MFPL_PD2MFP_QSPI0_MOSI0), + NUREG_EXPORT(SYS_GPD_MFPL, SYS_GPD_MFPL_PD1MFP_Msk, SYS_GPD_MFPL_PD1MFP_QSPI0_CLK), + NUREG_EXPORT(SYS_GPD_MFPL, SYS_GPD_MFPL_PD0MFP_Msk, SYS_GPD_MFPL_PD0MFP_QSPI0_SS0), + + /* TIMERn */ + NUREG_EXPORT(CLK_APBCLK0, CLK_APBCLK0_TMR0CKEN_Msk, CLK_APBCLK0_TMR0CKEN_Msk), + NUREG_EXPORT(CLK_APBCLK0, CLK_APBCLK0_TMR1CKEN_Msk, CLK_APBCLK0_TMR1CKEN_Msk), + NUREG_EXPORT(CLK_APBCLK0, CLK_APBCLK0_TMR2CKEN_Msk, CLK_APBCLK0_TMR2CKEN_Msk), + NUREG_EXPORT(CLK_APBCLK0, CLK_APBCLK0_TMR3CKEN_Msk, CLK_APBCLK0_TMR3CKEN_Msk), + NUREG_EXPORT(CLK_APBCLK0, CLK_APBCLK0_TMR4CKEN_Msk, CLK_APBCLK0_TMR4CKEN_Msk), + NUREG_EXPORT(CLK_APBCLK0, CLK_APBCLK0_TMR5CKEN_Msk, CLK_APBCLK0_TMR5CKEN_Msk), + NUREG_EXPORT(CLK_APBCLK0, CLK_APBCLK0_TMR6CKEN_Msk, CLK_APBCLK0_TMR6CKEN_Msk), + NUREG_EXPORT(CLK_APBCLK0, CLK_APBCLK0_TMR7CKEN_Msk, CLK_APBCLK0_TMR7CKEN_Msk), + NUREG_EXPORT(CLK_APBCLK0, CLK_APBCLK0_TMR8CKEN_Msk, CLK_APBCLK0_TMR8CKEN_Msk), + NUREG_EXPORT(CLK_APBCLK0, CLK_APBCLK0_TMR9CKEN_Msk, CLK_APBCLK0_TMR9CKEN_Msk), + NUREG_EXPORT(CLK_APBCLK0, CLK_APBCLK0_TMR10CKEN_Msk, CLK_APBCLK0_TMR10CKEN_Msk), + NUREG_EXPORT(CLK_APBCLK0, CLK_APBCLK0_TMR11CKEN_Msk, CLK_APBCLK0_TMR11CKEN_Msk), + + /* USB Host */ + NUREG_EXPORT(CLK_SYSCLK0, CLK_SYSCLK0_USBHEN_Msk, CLK_SYSCLK0_USBHEN_Msk), + NUREG_EXPORT(CLK_SYSCLK0, CLK_SYSCLK0_HUSBH0EN_Msk, CLK_SYSCLK0_HUSBH0EN_Msk), + NUREG_EXPORT(CLK_SYSCLK0, CLK_SYSCLK0_HUSBH1EN_Msk, CLK_SYSCLK0_HUSBH1EN_Msk), + NUREG_EXPORT(SYS_USBPMISCR, SYS_USBPMISCR_PHY0SUSPEND_Msk, SYS_USBPMISCR_PHY0SUSPEND_Msk), + NUREG_EXPORT(SYS_USBPMISCR, SYS_USBPMISCR_PHY1SUSPEND_Msk, SYS_USBPMISCR_PHY1SUSPEND_Msk), + NUREG_EXPORT(SYS_GPL_MFPH, SYS_GPL_MFPH_PL12MFP_Msk, SYS_GPL_MFPH_PL12MFP_HSUSBH_PWREN), + NUREG_EXPORT(SYS_GPL_MFPH, SYS_GPL_MFPH_PL13MFP_Msk, SYS_GPL_MFPH_PL13MFP_HSUSBH_OVC), + + /* SDH0 */ + NUREG_EXPORT(CLK_SYSCLK0, CLK_SYSCLK0_SDH0EN_Msk, CLK_SYSCLK0_SDH0EN_Msk), + NUREG_EXPORT(CLK_CLKSEL0, CLK_CLKSEL0_SD0SEL_Msk, CLK_CLKSEL0_SD0SEL_APLL), + NUREG_EXPORT(CLK_CLKSEL0, CLK_CLKSEL0_SD0SEL_Msk, CLK_CLKSEL0_SD0SEL_SYSPLL), + + NUREG_EXPORT(SYS_GPC_MFPL, SYS_GPC_MFPL_PC7MFP_Msk, SYS_GPC_MFPL_PC7MFP_SD0_WP), + NUREG_EXPORT(SYS_GPC_MFPL, SYS_GPC_MFPL_PC6MFP_Msk, SYS_GPC_MFPL_PC6MFP_SD0_nCD), + NUREG_EXPORT(SYS_GPC_MFPL, SYS_GPC_MFPL_PC5MFP_Msk, SYS_GPC_MFPL_PC5MFP_SD0_DAT3), + NUREG_EXPORT(SYS_GPC_MFPL, SYS_GPC_MFPL_PC4MFP_Msk, SYS_GPC_MFPL_PC4MFP_SD0_DAT2), + NUREG_EXPORT(SYS_GPC_MFPL, SYS_GPC_MFPL_PC3MFP_Msk, SYS_GPC_MFPL_PC3MFP_SD0_DAT1), + NUREG_EXPORT(SYS_GPC_MFPL, SYS_GPC_MFPL_PC2MFP_Msk, SYS_GPC_MFPL_PC2MFP_SD0_DAT0), + NUREG_EXPORT(SYS_GPC_MFPL, SYS_GPC_MFPL_PC1MFP_Msk, SYS_GPC_MFPL_PC1MFP_SD0_CLK), + NUREG_EXPORT(SYS_GPC_MFPL, SYS_GPC_MFPL_PC0MFP_Msk, SYS_GPC_MFPL_PC0MFP_SD0_CMD), + + /* SDH1 */ + NUREG_EXPORT(CLK_SYSCLK0, CLK_SYSCLK0_SDH1EN_Msk, CLK_SYSCLK0_SDH1EN_Msk), + NUREG_EXPORT(CLK_CLKSEL0, CLK_CLKSEL0_SD1SEL_Msk, CLK_CLKSEL0_SD1SEL_APLL), + NUREG_EXPORT(CLK_CLKSEL0, CLK_CLKSEL0_SD1SEL_Msk, CLK_CLKSEL0_SD1SEL_SYSPLL), + + NUREG_EXPORT(SYS_GPJ_MFPH, SYS_GPJ_MFPH_PJ11MFP_Msk, SYS_GPJ_MFPH_PJ11MFP_SD1_DAT3), + NUREG_EXPORT(SYS_GPJ_MFPH, SYS_GPJ_MFPH_PJ10MFP_Msk, SYS_GPJ_MFPH_PJ10MFP_SD1_DAT2), + NUREG_EXPORT(SYS_GPJ_MFPH, SYS_GPJ_MFPH_PJ9MFP_Msk, SYS_GPJ_MFPH_PJ9MFP_SD1_DAT1), + NUREG_EXPORT(SYS_GPJ_MFPH, SYS_GPJ_MFPH_PJ8MFP_Msk, SYS_GPJ_MFPH_PJ8MFP_SD1_DAT0), + NUREG_EXPORT(SYS_GPJ_MFPL, SYS_GPJ_MFPL_PJ7MFP_Msk, SYS_GPJ_MFPL_PJ7MFP_SD1_CLK), + NUREG_EXPORT(SYS_GPJ_MFPL, SYS_GPJ_MFPL_PJ6MFP_Msk, SYS_GPJ_MFPL_PJ6MFP_SD1_CMD), + NUREG_EXPORT(SYS_GPJ_MFPL, SYS_GPJ_MFPL_PJ5MFP_Msk, SYS_GPJ_MFPL_PJ5MFP_SD1_nCD), + NUREG_EXPORT(SYS_GPJ_MFPL, SYS_GPJ_MFPL_PJ4MFP_Msk, SYS_GPJ_MFPL_PJ4MFP_SD1_WP), + + /* UART11 */ + NUREG_EXPORT(SYS_GPL_MFPL, SYS_GPL_MFPL_PL0MFP_Msk, SYS_GPL_MFPL_PL0MFP_UART11_nCTS), + NUREG_EXPORT(SYS_GPL_MFPL, SYS_GPL_MFPL_PL1MFP_Msk, SYS_GPL_MFPL_PL1MFP_UART11_nRTS), + NUREG_EXPORT(SYS_GPL_MFPL, SYS_GPL_MFPL_PL2MFP_Msk, SYS_GPL_MFPL_PL2MFP_UART11_RXD), + NUREG_EXPORT(SYS_GPL_MFPL, SYS_GPL_MFPL_PL3MFP_Msk, SYS_GPL_MFPL_PL3MFP_UART11_TXD), + + NUREG_EXPORT(CLK_CLKSEL3, CLK_CLKSEL3_UART11SEL_Msk, CLK_CLKSEL3_UART11SEL_HXT), + NUREG_EXPORT(CLK_APBCLK0, CLK_APBCLK0_UART11CKEN_Msk, CLK_APBCLK0_UART11CKEN_Msk), + + /* WDT */ + NUREG_EXPORT(CLK_CLKSEL3, CLK_CLKSEL3_WDT0SEL_Msk, CLK_CLKSEL3_WDT0SEL_PCLK3_DIV4096), + + /* GMAC0 */ + NUREG_EXPORT(SYS_GPE_MFPL, SYS_GPE_MFPL_PE0MFP_Msk, SYS_GPE_MFPL_PE0MFP_RGMII0_MDC), + NUREG_EXPORT(SYS_GPE_MFPL, SYS_GPE_MFPL_PE1MFP_Msk, SYS_GPE_MFPL_PE1MFP_RGMII0_MDIO), + NUREG_EXPORT(SYS_GPE_MFPL, SYS_GPE_MFPL_PE2MFP_Msk, SYS_GPE_MFPL_PE2MFP_RGMII0_TXCTL), + NUREG_EXPORT(SYS_GPE_MFPL, SYS_GPE_MFPL_PE3MFP_Msk, SYS_GPE_MFPL_PE3MFP_RGMII0_TXD0), + NUREG_EXPORT(SYS_GPE_MFPL, SYS_GPE_MFPL_PE4MFP_Msk, SYS_GPE_MFPL_PE4MFP_RGMII0_TXD1), + NUREG_EXPORT(SYS_GPE_MFPL, SYS_GPE_MFPL_PE5MFP_Msk, SYS_GPE_MFPL_PE5MFP_RGMII0_RXCLK), + NUREG_EXPORT(SYS_GPE_MFPL, SYS_GPE_MFPL_PE6MFP_Msk, SYS_GPE_MFPL_PE6MFP_RGMII0_RXCTL), + NUREG_EXPORT(SYS_GPE_MFPL, SYS_GPE_MFPL_PE7MFP_Msk, SYS_GPE_MFPL_PE7MFP_RGMII0_RXD0), + NUREG_EXPORT(SYS_GPE_MFPH, SYS_GPE_MFPH_PE8MFP_Msk, SYS_GPE_MFPH_PE8MFP_RGMII0_RXD1), + NUREG_EXPORT(SYS_GPE_MFPH, SYS_GPE_MFPH_PE9MFP_Msk, SYS_GPE_MFPH_PE9MFP_RGMII0_RXD2), + NUREG_EXPORT(SYS_GPE_MFPH, SYS_GPE_MFPH_PE10MFP_Msk, SYS_GPE_MFPH_PE10MFP_RGMII0_RXD3), + NUREG_EXPORT(SYS_GPE_MFPH, SYS_GPE_MFPH_PE11MFP_Msk, SYS_GPE_MFPH_PE11MFP_RGMII0_TXCLK), + NUREG_EXPORT(SYS_GPE_MFPH, SYS_GPE_MFPH_PE12MFP_Msk, SYS_GPE_MFPH_PE12MFP_RGMII0_TXD2), + NUREG_EXPORT(SYS_GPE_MFPH, SYS_GPE_MFPH_PE13MFP_Msk, SYS_GPE_MFPH_PE13MFP_RGMII0_TXD3), + NUREG_EXPORT(SYS_GPE_MFPH, SYS_GPE_MFPH_PE13MFP_Msk, SYS_GPE_MFPH_PE13MFP_RGMII0_TXD3), + NUREG_EXPORT(CLK_SYSCLK0, CLK_SYSCLK0_GMAC0EN_Msk, CLK_SYSCLK0_GMAC0EN_Msk), + NUREG_EXPORT(CLK_SYSCLK1, CLK_SYSCLK1_GPECKEN_Msk, CLK_SYSCLK1_GPECKEN_Msk), + NUREG_EXPORT(CLK_CLKDIV0, CLK_CLKDIV0_EMAC0DIV_Msk, 0 << CLK_CLKDIV0_EMAC0DIV_Pos), //RGMII + + /* GMAC1 */ + NUREG_EXPORT(SYS_GPF_MFPL, SYS_GPF_MFPL_PF0MFP_Msk, SYS_GPF_MFPL_PF0MFP_RGMII1_MDC), + NUREG_EXPORT(SYS_GPF_MFPL, SYS_GPF_MFPL_PF1MFP_Msk, SYS_GPF_MFPL_PF1MFP_RGMII1_MDIO), + NUREG_EXPORT(SYS_GPF_MFPL, SYS_GPF_MFPL_PF2MFP_Msk, SYS_GPF_MFPL_PF2MFP_RGMII1_TXCTL), + NUREG_EXPORT(SYS_GPF_MFPL, SYS_GPF_MFPL_PF3MFP_Msk, SYS_GPF_MFPL_PF3MFP_RGMII1_TXD0), + NUREG_EXPORT(SYS_GPF_MFPL, SYS_GPF_MFPL_PF4MFP_Msk, SYS_GPF_MFPL_PF4MFP_RGMII1_TXD1), + NUREG_EXPORT(SYS_GPF_MFPL, SYS_GPF_MFPL_PF5MFP_Msk, SYS_GPF_MFPL_PF5MFP_RGMII1_RXCLK), + NUREG_EXPORT(SYS_GPF_MFPL, SYS_GPF_MFPL_PF6MFP_Msk, SYS_GPF_MFPL_PF6MFP_RGMII1_RXCTL), + NUREG_EXPORT(SYS_GPF_MFPL, SYS_GPF_MFPL_PF7MFP_Msk, SYS_GPF_MFPL_PF7MFP_RGMII1_RXD0), + NUREG_EXPORT(SYS_GPF_MFPH, SYS_GPF_MFPH_PF8MFP_Msk, SYS_GPF_MFPH_PF8MFP_RGMII1_RXD1), + NUREG_EXPORT(SYS_GPF_MFPH, SYS_GPF_MFPH_PF9MFP_Msk, SYS_GPF_MFPH_PF9MFP_RGMII1_RXD2), + NUREG_EXPORT(SYS_GPF_MFPH, SYS_GPF_MFPH_PF10MFP_Msk, SYS_GPF_MFPH_PF10MFP_RGMII1_RXD3), + NUREG_EXPORT(SYS_GPF_MFPH, SYS_GPF_MFPH_PF11MFP_Msk, SYS_GPF_MFPH_PF11MFP_RGMII1_TXCLK), + NUREG_EXPORT(SYS_GPF_MFPH, SYS_GPF_MFPH_PF12MFP_Msk, SYS_GPF_MFPH_PF12MFP_RGMII1_TXD2), + NUREG_EXPORT(SYS_GPF_MFPH, SYS_GPF_MFPH_PF13MFP_Msk, SYS_GPF_MFPH_PF13MFP_RGMII1_TXD3), + NUREG_EXPORT(CLK_SYSCLK0, CLK_SYSCLK0_GMAC1EN_Msk, CLK_SYSCLK0_GMAC1EN_Msk), + NUREG_EXPORT(CLK_SYSCLK1, CLK_SYSCLK1_GPFCKEN_Msk, CLK_SYSCLK1_GPFCKEN_Msk), + NUREG_EXPORT(CLK_CLKDIV0, CLK_CLKDIV0_EMAC1DIV_Msk, 0 << CLK_CLKDIV0_EMAC1DIV_Pos), //RGMII + + /* CANFD0 CLK */ + NUREG_EXPORT(CLK_SYSCLK0, CLK_SYSCLK0_CANFD0CKEN_Msk, CLK_SYSCLK0_CANFD0CKEN_Msk), + NUREG_EXPORT(CLK_CLKSEL4, CLK_CLKSEL4_CANFD0SEL_Msk, CLK_CLKSEL4_CANFD0SEL_APLL), + NUREG_EXPORT(CLK_CLKDIV0, CLK_CLKDIV0_CANFD0DIV_Msk, CLK_CLKDIV0_CANFD0(1)), + + {0} +}; + +void nu_check_register(void) +{ + nu_sys_check_register(&s_NuReg_arr[0]); +} +MSH_CMD_EXPORT(nu_check_register, Check registers); diff --git a/bsp/nuvoton/numaker-hmi-ma35d1/board/nutool_pincfg/nutool_pincfg.c b/bsp/nuvoton/numaker-hmi-ma35d1/board/nutool_pincfg/nutool_pincfg.c new file mode 100644 index 0000000000..e31c79cd08 --- /dev/null +++ b/bsp/nuvoton/numaker-hmi-ma35d1/board/nutool_pincfg/nutool_pincfg.c @@ -0,0 +1,774 @@ +/**************************************************************************** + * @file nutool_pincfg.c + * @version V1.24 + * @Date 2021/08/03-14:56:47 + * @brief NuMicro generated code file + * + * SPDX-License-Identifier: Apache-2.0 + * + * Copyright (C) 2013-2021 Nuvoton Technology Corp. All rights reserved. +*****************************************************************************/ + +/******************** +MCU:MA35D16A887C(BGA312) +Pin Configuration: +PinA2:I2C2_SCL +PinA3:EADC0_CH7 +PinA4:EADC0_CH3 +PinA5:RGMII1_TXCLK +PinA6:RGMII1_RXCLK +PinA7:RGMII1_RXCTL +PinA8:RGMII1_MDIO +PinA9:RGMII0_TXCLK +PinA10:RGMII0_RXD1 +PinA11:RGMII0_RXCLK +PinA12:RGMII0_TXCTL +PinA13:I2S0_DI +PinA14:VCAP1_SFIELD +PinA15:VCAP1_HSYNC +PinA16:VCAP1_PIXCLK +PinA17:VCAP1_DATA5 +PinB1:ADC0_CH4 +PinB2:I2C1_SCL +PinB3:EADC0_CH5 +PinB4:EADC0_CH4 +PinB5:EADC0_CH1 +PinB6:RGMII1_TXD3 +PinB7:RGMII1_RXD0 +PinB8:RGMII1_TXCTL +PinB9:RGMII0_TXD2 +PinB10:RGMII0_RXD2 +PinB11:RGMII0_RXCTL +PinB12:RGMII0_MDIO +PinB13:I2S0_BCLK +PinB14:VCAP1_VSYNC +PinB15:VCAP1_SCLK +PinB16:VCAP1_DATA7 +PinB17:VCAP1_DATA0 +PinB18:VCAP1_DATA2 +PinC1:ADC0_CH7 +PinC2:ADC0_CH5 +PinC3:I2C2_SDA +PinC4:EADC0_CH2 +PinC5:EADC0_CH0 +PinC6:RGMII1_TXD2 +PinC7:RGMII1_RXD2 +PinC8:RGMII1_TXD0 +PinC9:RGMII0_TXD3 +PinC10:RGMII0_RXD0 +PinC11:RGMII0_TXD1 +PinC12:RGMII0_MDC +PinC13:I2S0_LRCK +PinC14:VCAP1_DATA8 +PinC15:VCAP1_DATA6 +PinC16:VCAP1_DATA4 +PinC17:VCAP1_DATA1 +PinC18:VCAP1_DATA3 +PinD1:ADC0_CH6 +PinD2:I2C1_SDA +PinD3:EADC0_CH6 +PinD6:RGMII1_RXD3 +PinD7:RGMII1_RXD1 +PinD8:RGMII1_TXD1 +PinD9:RGMII1_MDC +PinD10:RGMII0_RXD3 +PinD11:RGMII0_TXD0 +PinD12:I2S0_DO +PinD13:I2S0_MCLK +PinD14:VCAP1_DATA9 +PinD16:UART10_nCTS +PinD17:UART10_TXD +PinD18:SD0_CLK +PinE1:HSUSBH_PWREN +PinE2:CAN1_RXD +PinE3:HSUSBH_OVC +PinE4:HSUSB0_VBUSVLD +PinE15:UART10_nRTS +PinE16:UART10_RXD +PinE17:SD0_WP +PinE18:SD0_DAT0 +PinF3:CAN1_TXD +PinF4:NAND_DATA3 +PinF16:UART14_RXD +PinF17:SD0_nCD +PinF18:SD0_CMD +PinG3:NAND_DATA0 +PinG4:NAND_DATA5 +PinG16:UART16_nRTS +PinG17:SD0_DAT3 +PinG18:SD0_DAT1 +PinH3:NAND_DATA1 +PinH4:NAND_DATA7 +PinH15:UART12_nRTS +PinH16:UART16_nCTS +PinH18:SD0_DAT2 +PinJ3:NAND_DATA6 +PinJ4:NAND_RDY +PinJ15:UART12_RXD +PinJ16:UART16_TXD +PinJ18:I2C4_SCL +PinK1:NAND_DATA2 +PinK2:NAND_DATA4 +PinK3:NAND_nRE +PinK4:NAND_ALE +PinK5:NAND_nWE +PinK16:UART16_RXD +PinK18:I2C4_SDA +PinL1:NAND_nCS +PinL2:NAND_CLE +PinL15:UART12_TXD +PinL16:I2C5_SDA +PinM5:NAND_nWP +PinM15:UART14_nRTS +PinM16:I2C5_SCL +PinM17:CAN3_RXD +PinN1:EPWM1_CH5 +PinN2:I2C3_SDA +PinN17:CAN3_TXD +PinP1:I2C3_SCL +PinP7:VCAP0_SFIELD +PinP8:SD1_nCD +PinP9:SD1_WP +PinP15:UART14_TXD +PinR5:VCAP0_DATA9 +PinR6:VCAP0_DATA7 +PinR9:SD1_DAT1 +PinR10:LCM_DEN +PinR11:LCM_DATA1 +PinR12:LCM_DATA6 +PinR13:LCM_DATA11 +PinR14:LCM_DATA15 +PinR16:LCM_DATA18 +PinR17:LCM_DATA20 +PinR18:LCM_DATA22 +PinT1:UART0_TXD +PinT2:UART0_RXD +PinT4:VCAP0_HSYNC +PinT5:VCAP0_DATA1 +PinT6:VCAP0_DATA5 +PinT7:VCAP0_DATA6 +PinT9:SD1_CMD +PinT10:LCM_VSYNC +PinT11:LCM_DATA0 +PinT12:LCM_DATA5 +PinT13:LCM_DATA10 +PinT14:LCM_DATA14 +PinT15:QSPI0_MISO1 +PinT16:LCM_DATA16 +PinT17:LCM_DATA17 +PinT18:LCM_DATA23 +PinU4:VCAP0_VSYNC +PinU5:VCAP0_DATA2 +PinU6:VCAP0_DATA3 +PinU7:VCAP0_DATA8 +PinU8:SD1_DAT3 +PinU9:SD1_DAT0 +PinU10:LCM_HSYNC +PinU11:LCM_DATA7 +PinU12:LCM_DATA4 +PinU13:LCM_DATA9 +PinU14:LCM_DATA13 +PinU15:QSPI0_MISO0 +PinU16:QSPI0_SS0 +PinU17:LCM_DATA19 +PinU18:LCM_DATA21 +PinV3:VCAP0_SCLK +PinV4:VCAP0_PIXCLK +PinV5:VCAP0_DATA0 +PinV6:VCAP0_DATA4 +PinV8:SD1_CLK +PinV9:SD1_DAT2 +PinV10:LCM_CLK +PinV11:LCM_DATA2 +PinV12:LCM_DATA3 +PinV13:LCM_DATA8 +PinV14:LCM_DATA12 +PinV15:QSPI0_MOSI1 +PinV16:QSPI0_MOSI0 +PinV17:QSPI0_CLK +********************/ + +#include "ma35d1.h" + +void nutool_pincfg_init_adc0(void) +{ + SYS->GPB_MFPH &= ~(SYS_GPB_MFPH_PB15MFP_Msk | SYS_GPB_MFPH_PB14MFP_Msk | SYS_GPB_MFPH_PB13MFP_Msk | SYS_GPB_MFPH_PB12MFP_Msk); + SYS->GPB_MFPH |= (SYS_GPB_MFPH_PB15MFP_ADC0_CH7 | SYS_GPB_MFPH_PB14MFP_ADC0_CH6 | SYS_GPB_MFPH_PB13MFP_ADC0_CH5 | SYS_GPB_MFPH_PB12MFP_ADC0_CH4); + + PB->MODE &= ~(GPIO_MODE_MODE12_Msk | GPIO_MODE_MODE13_Msk | GPIO_MODE_MODE14_Msk | GPIO_MODE_MODE15_Msk); + GPIO_DISABLE_DIGITAL_PATH(PB, BIT12 | BIT13 | BIT14 | BIT15); + + return; +} + +void nutool_pincfg_deinit_adc0(void) +{ + SYS->GPB_MFPH &= ~(SYS_GPB_MFPH_PB15MFP_Msk | SYS_GPB_MFPH_PB14MFP_Msk | SYS_GPB_MFPH_PB13MFP_Msk | SYS_GPB_MFPH_PB12MFP_Msk); + + return; +} + +void nutool_pincfg_init_can1(void) +{ + SYS->GPL_MFPH &= ~(SYS_GPL_MFPH_PL15MFP_Msk | SYS_GPL_MFPH_PL14MFP_Msk); + SYS->GPL_MFPH |= (SYS_GPL_MFPH_PL15MFP_CAN1_TXD | SYS_GPL_MFPH_PL14MFP_CAN1_RXD); + + return; +} + +void nutool_pincfg_deinit_can1(void) +{ + SYS->GPL_MFPH &= ~(SYS_GPL_MFPH_PL15MFP_Msk | SYS_GPL_MFPH_PL14MFP_Msk); + + return; +} + +void nutool_pincfg_init_can3(void) +{ + SYS->GPL_MFPH &= ~(SYS_GPL_MFPH_PL11MFP_Msk | SYS_GPL_MFPH_PL10MFP_Msk); + SYS->GPL_MFPH |= (SYS_GPL_MFPH_PL11MFP_CAN3_TXD | SYS_GPL_MFPH_PL10MFP_CAN3_RXD); + + return; +} + +void nutool_pincfg_deinit_can3(void) +{ + SYS->GPL_MFPH &= ~(SYS_GPL_MFPH_PL11MFP_Msk | SYS_GPL_MFPH_PL10MFP_Msk); + + return; +} + +void nutool_pincfg_init_eadc0(void) +{ + SYS->GPB_MFPL &= ~(SYS_GPB_MFPL_PB7MFP_Msk | SYS_GPB_MFPL_PB6MFP_Msk | SYS_GPB_MFPL_PB5MFP_Msk | SYS_GPB_MFPL_PB4MFP_Msk | SYS_GPB_MFPL_PB3MFP_Msk | SYS_GPB_MFPL_PB2MFP_Msk | SYS_GPB_MFPL_PB1MFP_Msk | SYS_GPB_MFPL_PB0MFP_Msk); + SYS->GPB_MFPL |= (SYS_GPB_MFPL_PB7MFP_EADC0_CH7 | SYS_GPB_MFPL_PB6MFP_EADC0_CH6 | SYS_GPB_MFPL_PB5MFP_EADC0_CH5 | SYS_GPB_MFPL_PB4MFP_EADC0_CH4 | SYS_GPB_MFPL_PB3MFP_EADC0_CH3 | SYS_GPB_MFPL_PB2MFP_EADC0_CH2 | SYS_GPB_MFPL_PB1MFP_EADC0_CH1 | SYS_GPB_MFPL_PB0MFP_EADC0_CH0); + + GPIO_DISABLE_DIGITAL_PATH(PB, BIT0 | BIT1 | BIT2 | BIT3 | BIT4 | BIT5 | BIT6 | BIT7); + + return; +} + +void nutool_pincfg_deinit_eadc0(void) +{ + SYS->GPB_MFPL &= ~(SYS_GPB_MFPL_PB7MFP_Msk | SYS_GPB_MFPL_PB6MFP_Msk | SYS_GPB_MFPL_PB5MFP_Msk | SYS_GPB_MFPL_PB4MFP_Msk | SYS_GPB_MFPL_PB3MFP_Msk | SYS_GPB_MFPL_PB2MFP_Msk | SYS_GPB_MFPL_PB1MFP_Msk | SYS_GPB_MFPL_PB0MFP_Msk); + + return; +} + +void nutool_pincfg_init_epwm1(void) +{ + SYS->GPM_MFPH &= ~(SYS_GPM_MFPH_PM13MFP_Msk); + SYS->GPM_MFPH |= (SYS_GPM_MFPH_PM13MFP_EPWM1_CH5); + + SYS->GPK_MFPL &= ~(SYS_GPK_MFPL_PK5MFP_Msk); + SYS->GPK_MFPL |= (SYS_GPK_MFPL_PK5MFP_EPWM1_CH1); + + return; +} + +void nutool_pincfg_deinit_epwm1(void) +{ + SYS->GPM_MFPH &= ~(SYS_GPM_MFPH_PM13MFP_Msk); + + SYS->GPK_MFPL &= ~(SYS_GPK_MFPL_PK5MFP_Msk); + return; +} + +void nutool_pincfg_init_hsusb0(void) +{ + SYS->GPF_MFPH &= ~(SYS_GPF_MFPH_PF15MFP_Msk); + SYS->GPF_MFPH |= (SYS_GPF_MFPH_PF15MFP_HSUSB0_VBUSVLD); + + return; +} + +void nutool_pincfg_deinit_hsusb0(void) +{ + SYS->GPF_MFPH &= ~(SYS_GPF_MFPH_PF15MFP_Msk); + + return; +} + +void nutool_pincfg_init_hsusbh(void) +{ + SYS->GPL_MFPH &= ~(SYS_GPL_MFPH_PL13MFP_Msk | SYS_GPL_MFPH_PL12MFP_Msk); + SYS->GPL_MFPH |= (SYS_GPL_MFPH_PL13MFP_HSUSBH_OVC | SYS_GPL_MFPH_PL12MFP_HSUSBH_PWREN); + + return; +} + +void nutool_pincfg_deinit_hsusbh(void) +{ + SYS->GPL_MFPH &= ~(SYS_GPL_MFPH_PL13MFP_Msk | SYS_GPL_MFPH_PL12MFP_Msk); + + return; +} + +void nutool_pincfg_init_i2c1(void) +{ + SYS->GPB_MFPH &= ~(SYS_GPB_MFPH_PB11MFP_Msk | SYS_GPB_MFPH_PB10MFP_Msk); + SYS->GPB_MFPH |= (SYS_GPB_MFPH_PB11MFP_I2C1_SCL | SYS_GPB_MFPH_PB10MFP_I2C1_SDA); + + return; +} + +void nutool_pincfg_deinit_i2c1(void) +{ + SYS->GPB_MFPH &= ~(SYS_GPB_MFPH_PB11MFP_Msk | SYS_GPB_MFPH_PB10MFP_Msk); + + return; +} + +void nutool_pincfg_init_i2c2(void) +{ + SYS->GPB_MFPH &= ~(SYS_GPB_MFPH_PB9MFP_Msk | SYS_GPB_MFPH_PB8MFP_Msk); + SYS->GPB_MFPH |= (SYS_GPB_MFPH_PB9MFP_I2C2_SCL | SYS_GPB_MFPH_PB8MFP_I2C2_SDA); + + return; +} + +void nutool_pincfg_deinit_i2c2(void) +{ + SYS->GPB_MFPH &= ~(SYS_GPB_MFPH_PB9MFP_Msk | SYS_GPB_MFPH_PB8MFP_Msk); + + return; +} + +void nutool_pincfg_init_i2c3(void) +{ + SYS->GPM_MFPH &= ~(SYS_GPM_MFPH_PM15MFP_Msk | SYS_GPM_MFPH_PM14MFP_Msk); + SYS->GPM_MFPH |= (SYS_GPM_MFPH_PM15MFP_I2C3_SCL | SYS_GPM_MFPH_PM14MFP_I2C3_SDA); + + return; +} + +void nutool_pincfg_deinit_i2c3(void) +{ + SYS->GPM_MFPH &= ~(SYS_GPM_MFPH_PM15MFP_Msk | SYS_GPM_MFPH_PM14MFP_Msk); + + return; +} + +void nutool_pincfg_init_i2c4(void) +{ + SYS->GPL_MFPL &= ~(SYS_GPL_MFPL_PL5MFP_Msk | SYS_GPL_MFPL_PL4MFP_Msk); + SYS->GPL_MFPL |= (SYS_GPL_MFPL_PL5MFP_I2C4_SCL | SYS_GPL_MFPL_PL4MFP_I2C4_SDA); + + return; +} + +void nutool_pincfg_deinit_i2c4(void) +{ + SYS->GPL_MFPL &= ~(SYS_GPL_MFPL_PL5MFP_Msk | SYS_GPL_MFPL_PL4MFP_Msk); + + return; +} + +void nutool_pincfg_init_i2c5(void) +{ + SYS->GPJ_MFPH &= ~(SYS_GPJ_MFPH_PJ13MFP_Msk | SYS_GPJ_MFPH_PJ12MFP_Msk); + SYS->GPJ_MFPH |= (SYS_GPJ_MFPH_PJ13MFP_I2C5_SCL | SYS_GPJ_MFPH_PJ12MFP_I2C5_SDA); + + return; +} + +void nutool_pincfg_deinit_i2c5(void) +{ + SYS->GPJ_MFPH &= ~(SYS_GPJ_MFPH_PJ13MFP_Msk | SYS_GPJ_MFPH_PJ12MFP_Msk); + + return; +} + +void nutool_pincfg_init_i2s0(void) +{ + SYS->GPK_MFPH &= ~(SYS_GPK_MFPH_PK15MFP_Msk | SYS_GPK_MFPH_PK14MFP_Msk | SYS_GPK_MFPH_PK13MFP_Msk | SYS_GPK_MFPH_PK12MFP_Msk); + SYS->GPK_MFPH |= (SYS_GPK_MFPH_PK15MFP_I2S0_DO | SYS_GPK_MFPH_PK14MFP_I2S0_DI | SYS_GPK_MFPH_PK13MFP_I2S0_BCLK | SYS_GPK_MFPH_PK12MFP_I2S0_LRCK); + SYS->GPN_MFPH &= ~(SYS_GPN_MFPH_PN15MFP_Msk); + SYS->GPN_MFPH |= (SYS_GPN_MFPH_PN15MFP_I2S0_MCLK); + + return; +} + +void nutool_pincfg_deinit_i2s0(void) +{ + SYS->GPK_MFPH &= ~(SYS_GPK_MFPH_PK15MFP_Msk | SYS_GPK_MFPH_PK14MFP_Msk | SYS_GPK_MFPH_PK13MFP_Msk | SYS_GPK_MFPH_PK12MFP_Msk); + SYS->GPN_MFPH &= ~(SYS_GPN_MFPH_PN15MFP_Msk); + + return; +} + +void nutool_pincfg_init_lcm(void) +{ + SYS->GPC_MFPH &= ~(SYS_GPC_MFPH_PC15MFP_Msk | SYS_GPC_MFPH_PC14MFP_Msk | SYS_GPC_MFPH_PC13MFP_Msk | SYS_GPC_MFPH_PC12MFP_Msk); + SYS->GPC_MFPH |= (SYS_GPC_MFPH_PC15MFP_LCM_DATA19 | SYS_GPC_MFPH_PC14MFP_LCM_DATA18 | SYS_GPC_MFPH_PC13MFP_LCM_DATA17 | SYS_GPC_MFPH_PC12MFP_LCM_DATA16); + SYS->GPG_MFPH &= ~(SYS_GPG_MFPH_PG10MFP_Msk | SYS_GPG_MFPH_PG9MFP_Msk | SYS_GPG_MFPH_PG8MFP_Msk); + SYS->GPG_MFPH |= (SYS_GPG_MFPH_PG10MFP_LCM_CLK | SYS_GPG_MFPH_PG9MFP_LCM_HSYNC | SYS_GPG_MFPH_PG8MFP_LCM_VSYNC); + SYS->GPH_MFPH &= ~(SYS_GPH_MFPH_PH15MFP_Msk | SYS_GPH_MFPH_PH14MFP_Msk | SYS_GPH_MFPH_PH13MFP_Msk | SYS_GPH_MFPH_PH12MFP_Msk); + SYS->GPH_MFPH |= (SYS_GPH_MFPH_PH15MFP_LCM_DATA23 | SYS_GPH_MFPH_PH14MFP_LCM_DATA22 | SYS_GPH_MFPH_PH13MFP_LCM_DATA21 | SYS_GPH_MFPH_PH12MFP_LCM_DATA20); + SYS->GPH_MFPL &= ~(SYS_GPH_MFPL_PH7MFP_Msk | SYS_GPH_MFPL_PH6MFP_Msk | SYS_GPH_MFPL_PH5MFP_Msk | SYS_GPH_MFPL_PH4MFP_Msk | SYS_GPH_MFPL_PH3MFP_Msk | SYS_GPH_MFPL_PH2MFP_Msk | SYS_GPH_MFPL_PH1MFP_Msk | SYS_GPH_MFPL_PH0MFP_Msk); + SYS->GPH_MFPL |= (SYS_GPH_MFPL_PH7MFP_LCM_DATA15 | SYS_GPH_MFPL_PH6MFP_LCM_DATA14 | SYS_GPH_MFPL_PH5MFP_LCM_DATA13 | SYS_GPH_MFPL_PH4MFP_LCM_DATA12 | SYS_GPH_MFPL_PH3MFP_LCM_DATA11 | SYS_GPH_MFPL_PH2MFP_LCM_DATA10 | SYS_GPH_MFPL_PH1MFP_LCM_DATA9 | SYS_GPH_MFPL_PH0MFP_LCM_DATA8); + SYS->GPI_MFPH &= ~(SYS_GPI_MFPH_PI15MFP_Msk | SYS_GPI_MFPH_PI14MFP_Msk | SYS_GPI_MFPH_PI13MFP_Msk | SYS_GPI_MFPH_PI12MFP_Msk | SYS_GPI_MFPH_PI11MFP_Msk | SYS_GPI_MFPH_PI10MFP_Msk | SYS_GPI_MFPH_PI9MFP_Msk | SYS_GPI_MFPH_PI8MFP_Msk); + SYS->GPI_MFPH |= (SYS_GPI_MFPH_PI15MFP_LCM_DATA7 | SYS_GPI_MFPH_PI14MFP_LCM_DATA6 | SYS_GPI_MFPH_PI13MFP_LCM_DATA5 | SYS_GPI_MFPH_PI12MFP_LCM_DATA4 | SYS_GPI_MFPH_PI11MFP_LCM_DATA3 | SYS_GPI_MFPH_PI10MFP_LCM_DATA2 | SYS_GPI_MFPH_PI9MFP_LCM_DATA1 | SYS_GPI_MFPH_PI8MFP_LCM_DATA0); + SYS->GPK_MFPL &= ~(SYS_GPK_MFPL_PK4MFP_Msk); + SYS->GPK_MFPL |= (SYS_GPK_MFPL_PK4MFP_LCM_DEN); + + return; +} + +void nutool_pincfg_deinit_lcm(void) +{ + SYS->GPC_MFPH &= ~(SYS_GPC_MFPH_PC15MFP_Msk | SYS_GPC_MFPH_PC14MFP_Msk | SYS_GPC_MFPH_PC13MFP_Msk | SYS_GPC_MFPH_PC12MFP_Msk); + SYS->GPG_MFPH &= ~(SYS_GPG_MFPH_PG10MFP_Msk | SYS_GPG_MFPH_PG9MFP_Msk | SYS_GPG_MFPH_PG8MFP_Msk); + SYS->GPH_MFPH &= ~(SYS_GPH_MFPH_PH15MFP_Msk | SYS_GPH_MFPH_PH14MFP_Msk | SYS_GPH_MFPH_PH13MFP_Msk | SYS_GPH_MFPH_PH12MFP_Msk); + SYS->GPH_MFPL &= ~(SYS_GPH_MFPL_PH7MFP_Msk | SYS_GPH_MFPL_PH6MFP_Msk | SYS_GPH_MFPL_PH5MFP_Msk | SYS_GPH_MFPL_PH4MFP_Msk | SYS_GPH_MFPL_PH3MFP_Msk | SYS_GPH_MFPL_PH2MFP_Msk | SYS_GPH_MFPL_PH1MFP_Msk | SYS_GPH_MFPL_PH0MFP_Msk); + SYS->GPI_MFPH &= ~(SYS_GPI_MFPH_PI15MFP_Msk | SYS_GPI_MFPH_PI14MFP_Msk | SYS_GPI_MFPH_PI13MFP_Msk | SYS_GPI_MFPH_PI12MFP_Msk | SYS_GPI_MFPH_PI11MFP_Msk | SYS_GPI_MFPH_PI10MFP_Msk | SYS_GPI_MFPH_PI9MFP_Msk | SYS_GPI_MFPH_PI8MFP_Msk); + SYS->GPK_MFPL &= ~(SYS_GPK_MFPL_PK4MFP_Msk); + + return; +} + +void nutool_pincfg_init_nand(void) +{ + SYS->GPA_MFPH &= ~(SYS_GPA_MFPH_PA14MFP_Msk | SYS_GPA_MFPH_PA13MFP_Msk | SYS_GPA_MFPH_PA12MFP_Msk | SYS_GPA_MFPH_PA11MFP_Msk | SYS_GPA_MFPH_PA10MFP_Msk | SYS_GPA_MFPH_PA9MFP_Msk | SYS_GPA_MFPH_PA8MFP_Msk); + SYS->GPA_MFPH |= (SYS_GPA_MFPH_PA14MFP_NAND_nWP | SYS_GPA_MFPH_PA13MFP_NAND_nCS | SYS_GPA_MFPH_PA12MFP_NAND_ALE | SYS_GPA_MFPH_PA11MFP_NAND_CLE | SYS_GPA_MFPH_PA10MFP_NAND_nWE | SYS_GPA_MFPH_PA9MFP_NAND_nRE | SYS_GPA_MFPH_PA8MFP_NAND_RDY); + SYS->GPA_MFPL &= ~(SYS_GPA_MFPL_PA7MFP_Msk | SYS_GPA_MFPL_PA6MFP_Msk | SYS_GPA_MFPL_PA5MFP_Msk | SYS_GPA_MFPL_PA4MFP_Msk | SYS_GPA_MFPL_PA3MFP_Msk | SYS_GPA_MFPL_PA2MFP_Msk | SYS_GPA_MFPL_PA1MFP_Msk | SYS_GPA_MFPL_PA0MFP_Msk); + SYS->GPA_MFPL |= (SYS_GPA_MFPL_PA7MFP_NAND_DATA7 | SYS_GPA_MFPL_PA6MFP_NAND_DATA6 | SYS_GPA_MFPL_PA5MFP_NAND_DATA5 | SYS_GPA_MFPL_PA4MFP_NAND_DATA4 | SYS_GPA_MFPL_PA3MFP_NAND_DATA3 | SYS_GPA_MFPL_PA2MFP_NAND_DATA2 | SYS_GPA_MFPL_PA1MFP_NAND_DATA1 | SYS_GPA_MFPL_PA0MFP_NAND_DATA0); + + return; +} + +void nutool_pincfg_deinit_nand(void) +{ + SYS->GPA_MFPH &= ~(SYS_GPA_MFPH_PA14MFP_Msk | SYS_GPA_MFPH_PA13MFP_Msk | SYS_GPA_MFPH_PA12MFP_Msk | SYS_GPA_MFPH_PA11MFP_Msk | SYS_GPA_MFPH_PA10MFP_Msk | SYS_GPA_MFPH_PA9MFP_Msk | SYS_GPA_MFPH_PA8MFP_Msk); + SYS->GPA_MFPL &= ~(SYS_GPA_MFPL_PA7MFP_Msk | SYS_GPA_MFPL_PA6MFP_Msk | SYS_GPA_MFPL_PA5MFP_Msk | SYS_GPA_MFPL_PA4MFP_Msk | SYS_GPA_MFPL_PA3MFP_Msk | SYS_GPA_MFPL_PA2MFP_Msk | SYS_GPA_MFPL_PA1MFP_Msk | SYS_GPA_MFPL_PA0MFP_Msk); + + return; +} + +void nutool_pincfg_init_qspi0(void) +{ + SYS->GPD_MFPL &= ~(SYS_GPD_MFPL_PD5MFP_Msk | SYS_GPD_MFPL_PD4MFP_Msk | SYS_GPD_MFPL_PD3MFP_Msk | SYS_GPD_MFPL_PD2MFP_Msk | SYS_GPD_MFPL_PD1MFP_Msk | SYS_GPD_MFPL_PD0MFP_Msk); + SYS->GPD_MFPL |= (SYS_GPD_MFPL_PD5MFP_QSPI0_MISO1 | SYS_GPD_MFPL_PD4MFP_QSPI0_MOSI1 | SYS_GPD_MFPL_PD3MFP_QSPI0_MISO0 | SYS_GPD_MFPL_PD2MFP_QSPI0_MOSI0 | SYS_GPD_MFPL_PD1MFP_QSPI0_CLK | SYS_GPD_MFPL_PD0MFP_QSPI0_SS0); + + GPIO_SetDrivingCtl(PD, (BIT0 | BIT1 | BIT2 | BIT3 | BIT4 | BIT5), 4); + + return; +} + +void nutool_pincfg_deinit_qspi0(void) +{ + SYS->GPD_MFPL &= ~(SYS_GPD_MFPL_PD5MFP_Msk | SYS_GPD_MFPL_PD4MFP_Msk | SYS_GPD_MFPL_PD3MFP_Msk | SYS_GPD_MFPL_PD2MFP_Msk | SYS_GPD_MFPL_PD1MFP_Msk | SYS_GPD_MFPL_PD0MFP_Msk); + + return; +} + +void nutool_pincfg_init_rgmii0(void) +{ + SYS->GPE_MFPH &= ~(SYS_GPE_MFPH_PE13MFP_Msk | SYS_GPE_MFPH_PE12MFP_Msk | SYS_GPE_MFPH_PE11MFP_Msk | SYS_GPE_MFPH_PE10MFP_Msk | SYS_GPE_MFPH_PE9MFP_Msk | SYS_GPE_MFPH_PE8MFP_Msk); + SYS->GPE_MFPH |= (SYS_GPE_MFPH_PE13MFP_RGMII0_TXD3 | SYS_GPE_MFPH_PE12MFP_RGMII0_TXD2 | SYS_GPE_MFPH_PE11MFP_RGMII0_TXCLK | SYS_GPE_MFPH_PE10MFP_RGMII0_RXD3 | SYS_GPE_MFPH_PE9MFP_RGMII0_RXD2 | SYS_GPE_MFPH_PE8MFP_RGMII0_RXD1); + SYS->GPE_MFPL &= ~(SYS_GPE_MFPL_PE7MFP_Msk | SYS_GPE_MFPL_PE6MFP_Msk | SYS_GPE_MFPL_PE5MFP_Msk | SYS_GPE_MFPL_PE4MFP_Msk | SYS_GPE_MFPL_PE3MFP_Msk | SYS_GPE_MFPL_PE2MFP_Msk | SYS_GPE_MFPL_PE1MFP_Msk | SYS_GPE_MFPL_PE0MFP_Msk); + SYS->GPE_MFPL |= (SYS_GPE_MFPL_PE7MFP_RGMII0_RXD0 | SYS_GPE_MFPL_PE6MFP_RGMII0_RXCTL | SYS_GPE_MFPL_PE5MFP_RGMII0_RXCLK | SYS_GPE_MFPL_PE4MFP_RGMII0_TXD1 | SYS_GPE_MFPL_PE3MFP_RGMII0_TXD0 | SYS_GPE_MFPL_PE2MFP_RGMII0_TXCTL | SYS_GPE_MFPL_PE1MFP_RGMII0_MDIO | SYS_GPE_MFPL_PE0MFP_RGMII0_MDC); + + /* RGMII Mode */ + SYS->GMAC0MISCR &= ~1; + + /* Set 1.8v */ + GPIO_SetPowerMode(PE, 0x3FFF, 0); + + GPIO_SetPullCtl(PE, 0x3FFF, GPIO_PUSEL_DISABLE); + + GPIO_SetSchmittTriggere(PE, 0x3FDF, 1); //except clk + + GPIO_SetSlewCtl(PE, 0x3FFF, GPIO_SLEWCTL_NORMAL); + + GPIO_SetDrivingCtl(PE, 0x3FFF, 1); + + return; +} + +void nutool_pincfg_deinit_rgmii0(void) +{ + SYS->GPE_MFPH &= ~(SYS_GPE_MFPH_PE13MFP_Msk | SYS_GPE_MFPH_PE12MFP_Msk | SYS_GPE_MFPH_PE11MFP_Msk | SYS_GPE_MFPH_PE10MFP_Msk | SYS_GPE_MFPH_PE9MFP_Msk | SYS_GPE_MFPH_PE8MFP_Msk); + SYS->GPE_MFPL &= ~(SYS_GPE_MFPL_PE7MFP_Msk | SYS_GPE_MFPL_PE6MFP_Msk | SYS_GPE_MFPL_PE5MFP_Msk | SYS_GPE_MFPL_PE4MFP_Msk | SYS_GPE_MFPL_PE3MFP_Msk | SYS_GPE_MFPL_PE2MFP_Msk | SYS_GPE_MFPL_PE1MFP_Msk | SYS_GPE_MFPL_PE0MFP_Msk); + + return; +} + +void nutool_pincfg_init_rgmii1(void) +{ + SYS->GPF_MFPH &= ~(SYS_GPF_MFPH_PF13MFP_Msk | SYS_GPF_MFPH_PF12MFP_Msk | SYS_GPF_MFPH_PF11MFP_Msk | SYS_GPF_MFPH_PF10MFP_Msk | SYS_GPF_MFPH_PF9MFP_Msk | SYS_GPF_MFPH_PF8MFP_Msk); + SYS->GPF_MFPH |= (SYS_GPF_MFPH_PF13MFP_RGMII1_TXD3 | SYS_GPF_MFPH_PF12MFP_RGMII1_TXD2 | SYS_GPF_MFPH_PF11MFP_RGMII1_TXCLK | SYS_GPF_MFPH_PF10MFP_RGMII1_RXD3 | SYS_GPF_MFPH_PF9MFP_RGMII1_RXD2 | SYS_GPF_MFPH_PF8MFP_RGMII1_RXD1); + SYS->GPF_MFPL &= ~(SYS_GPF_MFPL_PF7MFP_Msk | SYS_GPF_MFPL_PF6MFP_Msk | SYS_GPF_MFPL_PF5MFP_Msk | SYS_GPF_MFPL_PF4MFP_Msk | SYS_GPF_MFPL_PF3MFP_Msk | SYS_GPF_MFPL_PF2MFP_Msk | SYS_GPF_MFPL_PF1MFP_Msk | SYS_GPF_MFPL_PF0MFP_Msk); + SYS->GPF_MFPL |= (SYS_GPF_MFPL_PF7MFP_RGMII1_RXD0 | SYS_GPF_MFPL_PF6MFP_RGMII1_RXCTL | SYS_GPF_MFPL_PF5MFP_RGMII1_RXCLK | SYS_GPF_MFPL_PF4MFP_RGMII1_TXD1 | SYS_GPF_MFPL_PF3MFP_RGMII1_TXD0 | SYS_GPF_MFPL_PF2MFP_RGMII1_TXCTL | SYS_GPF_MFPL_PF1MFP_RGMII1_MDIO | SYS_GPF_MFPL_PF0MFP_RGMII1_MDC); + + /* RGMII Mode */ + SYS->GMAC1MISCR &= ~1; + + /* Set 1.8v */ + GPIO_SetPowerMode(PF, 0x3FFF, 0); + + GPIO_SetPullCtl(PF, 0x3FFF, GPIO_PUSEL_DISABLE); + + GPIO_SetSchmittTriggere(PF, 0x3FDF, 1); //except clk + + GPIO_SetSlewCtl(PF, 0x3FFF, GPIO_SLEWCTL_NORMAL); + + GPIO_SetDrivingCtl(PF, 0x3FFF, 1); + + return; +} + +void nutool_pincfg_deinit_rgmii1(void) +{ + SYS->GPF_MFPH &= ~(SYS_GPF_MFPH_PF13MFP_Msk | SYS_GPF_MFPH_PF12MFP_Msk | SYS_GPF_MFPH_PF11MFP_Msk | SYS_GPF_MFPH_PF10MFP_Msk | SYS_GPF_MFPH_PF9MFP_Msk | SYS_GPF_MFPH_PF8MFP_Msk); + SYS->GPF_MFPL &= ~(SYS_GPF_MFPL_PF7MFP_Msk | SYS_GPF_MFPL_PF6MFP_Msk | SYS_GPF_MFPL_PF5MFP_Msk | SYS_GPF_MFPL_PF4MFP_Msk | SYS_GPF_MFPL_PF3MFP_Msk | SYS_GPF_MFPL_PF2MFP_Msk | SYS_GPF_MFPL_PF1MFP_Msk | SYS_GPF_MFPL_PF0MFP_Msk); + + return; +} + +void nutool_pincfg_init_sd0(void) +{ + SYS->GPC_MFPL &= ~(SYS_GPC_MFPL_PC7MFP_Msk | SYS_GPC_MFPL_PC6MFP_Msk | SYS_GPC_MFPL_PC5MFP_Msk | SYS_GPC_MFPL_PC4MFP_Msk | SYS_GPC_MFPL_PC3MFP_Msk | SYS_GPC_MFPL_PC2MFP_Msk | SYS_GPC_MFPL_PC1MFP_Msk | SYS_GPC_MFPL_PC0MFP_Msk); + SYS->GPC_MFPL |= (SYS_GPC_MFPL_PC7MFP_SD0_WP | SYS_GPC_MFPL_PC6MFP_SD0_nCD | SYS_GPC_MFPL_PC5MFP_SD0_DAT3 | SYS_GPC_MFPL_PC4MFP_SD0_DAT2 | SYS_GPC_MFPL_PC3MFP_SD0_DAT1 | SYS_GPC_MFPL_PC2MFP_SD0_DAT0 | SYS_GPC_MFPL_PC1MFP_SD0_CLK | SYS_GPC_MFPL_PC0MFP_SD0_CMD); + + return; +} + +void nutool_pincfg_deinit_sd0(void) +{ + SYS->GPC_MFPL &= ~(SYS_GPC_MFPL_PC7MFP_Msk | SYS_GPC_MFPL_PC6MFP_Msk | SYS_GPC_MFPL_PC5MFP_Msk | SYS_GPC_MFPL_PC4MFP_Msk | SYS_GPC_MFPL_PC3MFP_Msk | SYS_GPC_MFPL_PC2MFP_Msk | SYS_GPC_MFPL_PC1MFP_Msk | SYS_GPC_MFPL_PC0MFP_Msk); + + return; +} + +void nutool_pincfg_init_sd1(void) +{ + SYS->GPJ_MFPH &= ~(SYS_GPJ_MFPH_PJ11MFP_Msk | SYS_GPJ_MFPH_PJ10MFP_Msk | SYS_GPJ_MFPH_PJ9MFP_Msk | SYS_GPJ_MFPH_PJ8MFP_Msk); + SYS->GPJ_MFPH |= (SYS_GPJ_MFPH_PJ11MFP_SD1_DAT3 | SYS_GPJ_MFPH_PJ10MFP_SD1_DAT2 | SYS_GPJ_MFPH_PJ9MFP_SD1_DAT1 | SYS_GPJ_MFPH_PJ8MFP_SD1_DAT0); + SYS->GPJ_MFPL &= ~(SYS_GPJ_MFPL_PJ7MFP_Msk | SYS_GPJ_MFPL_PJ6MFP_Msk | SYS_GPJ_MFPL_PJ5MFP_Msk | SYS_GPJ_MFPL_PJ4MFP_Msk); + SYS->GPJ_MFPL |= (SYS_GPJ_MFPL_PJ7MFP_SD1_CLK | SYS_GPJ_MFPL_PJ6MFP_SD1_CMD | SYS_GPJ_MFPL_PJ5MFP_SD1_nCD | SYS_GPJ_MFPL_PJ4MFP_SD1_WP); + SYS->GPJ_MFPL &= ~(SYS_GPJ_MFPL_PJ0MFP_Msk | SYS_GPJ_MFPL_PJ1MFP_Msk | SYS_GPJ_MFPL_PJ2MFP_Msk | SYS_GPJ_MFPL_PJ3MFP_Msk); + SYS->GPJ_MFPL |= (SYS_GPJ_MFPL_PJ0MFP_eMMC1_DAT4 | SYS_GPJ_MFPL_PJ1MFP_eMMC1_DAT5 | SYS_GPJ_MFPL_PJ2MFP_eMMC1_DAT6 | SYS_GPJ_MFPL_PJ3MFP_eMMC1_DAT7); + + return; +} + +void nutool_pincfg_deinit_sd1(void) +{ + SYS->GPJ_MFPH &= ~(SYS_GPJ_MFPH_PJ11MFP_Msk | SYS_GPJ_MFPH_PJ10MFP_Msk | SYS_GPJ_MFPH_PJ9MFP_Msk | SYS_GPJ_MFPH_PJ8MFP_Msk); + SYS->GPJ_MFPL &= ~(SYS_GPJ_MFPL_PJ7MFP_Msk | SYS_GPJ_MFPL_PJ6MFP_Msk | SYS_GPJ_MFPL_PJ5MFP_Msk | SYS_GPJ_MFPL_PJ4MFP_Msk); + SYS->GPJ_MFPL &= ~(SYS_GPJ_MFPL_PJ0MFP_Msk | SYS_GPJ_MFPL_PJ1MFP_Msk | SYS_GPJ_MFPL_PJ2MFP_Msk | SYS_GPJ_MFPL_PJ3MFP_Msk); + + return; +} + +void nutool_pincfg_init_uart0(void) +{ + SYS->GPE_MFPH &= ~(SYS_GPE_MFPH_PE15MFP_Msk | SYS_GPE_MFPH_PE14MFP_Msk); + SYS->GPE_MFPH |= (SYS_GPE_MFPH_PE15MFP_UART0_RXD | SYS_GPE_MFPH_PE14MFP_UART0_TXD); + + return; +} + +void nutool_pincfg_deinit_uart0(void) +{ + SYS->GPE_MFPH &= ~(SYS_GPE_MFPH_PE15MFP_Msk | SYS_GPE_MFPH_PE14MFP_Msk); + + return; +} + +void nutool_pincfg_init_uart11(void) +{ + SYS->GPL_MFPL &= ~(SYS_GPL_MFPL_PL0MFP_Msk | SYS_GPL_MFPL_PL1MFP_Msk | SYS_GPL_MFPL_PL2MFP_Msk | SYS_GPL_MFPL_PL3MFP_Msk); + SYS->GPL_MFPL |= (SYS_GPL_MFPL_PL3MFP_UART11_TXD | SYS_GPL_MFPL_PL2MFP_UART11_RXD | SYS_GPL_MFPL_PL1MFP_UART11_nRTS | SYS_GPL_MFPL_PL0MFP_UART11_nCTS); + + return; +} + +void nutool_pincfg_deinit_uart11(void) +{ + SYS->GPL_MFPL &= ~(SYS_GPL_MFPL_PL0MFP_Msk | SYS_GPL_MFPL_PL1MFP_Msk | SYS_GPL_MFPL_PL2MFP_Msk | SYS_GPL_MFPL_PL3MFP_Msk); + + return; +} + +void nutool_pincfg_init_uart12(void) +{ + SYS->GPI_MFPL &= ~(SYS_GPI_MFPL_PI3MFP_Msk | SYS_GPI_MFPL_PI2MFP_Msk | SYS_GPI_MFPL_PI1MFP_Msk); + SYS->GPI_MFPL |= (SYS_GPI_MFPL_PI3MFP_UART12_TXD | SYS_GPI_MFPL_PI2MFP_UART12_RXD | SYS_GPI_MFPL_PI1MFP_UART12_nRTS); + + return; +} + +void nutool_pincfg_deinit_uart12(void) +{ + SYS->GPI_MFPL &= ~(SYS_GPI_MFPL_PI3MFP_Msk | SYS_GPI_MFPL_PI2MFP_Msk | SYS_GPI_MFPL_PI1MFP_Msk); + + return; +} + +void nutool_pincfg_init_uart14(void) +{ + SYS->GPI_MFPL &= ~(SYS_GPI_MFPL_PI7MFP_Msk | SYS_GPI_MFPL_PI6MFP_Msk | SYS_GPI_MFPL_PI5MFP_Msk); + SYS->GPI_MFPL |= (SYS_GPI_MFPL_PI7MFP_UART14_TXD | SYS_GPI_MFPL_PI6MFP_UART14_RXD | SYS_GPI_MFPL_PI5MFP_UART14_nRTS); + + return; +} + +void nutool_pincfg_deinit_uart14(void) +{ + SYS->GPI_MFPL &= ~(SYS_GPI_MFPL_PI7MFP_Msk | SYS_GPI_MFPL_PI6MFP_Msk | SYS_GPI_MFPL_PI5MFP_Msk); + + return; +} + +void nutool_pincfg_init_uart16(void) +{ + SYS->GPK_MFPL &= ~(SYS_GPK_MFPL_PK3MFP_Msk | SYS_GPK_MFPL_PK2MFP_Msk | SYS_GPK_MFPL_PK1MFP_Msk | SYS_GPK_MFPL_PK0MFP_Msk); + SYS->GPK_MFPL |= (SYS_GPK_MFPL_PK3MFP_UART16_TXD | SYS_GPK_MFPL_PK2MFP_UART16_RXD | SYS_GPK_MFPL_PK1MFP_UART16_nRTS | SYS_GPK_MFPL_PK0MFP_UART16_nCTS); + + return; +} + +void nutool_pincfg_deinit_uart16(void) +{ + SYS->GPK_MFPL &= ~(SYS_GPK_MFPL_PK3MFP_Msk | SYS_GPK_MFPL_PK2MFP_Msk | SYS_GPK_MFPL_PK1MFP_Msk | SYS_GPK_MFPL_PK0MFP_Msk); + + return; +} + +void nutool_pincfg_init_vcap0(void) +{ + SYS->GPK_MFPH &= ~(SYS_GPK_MFPH_PK11MFP_Msk | SYS_GPK_MFPH_PK10MFP_Msk | SYS_GPK_MFPH_PK9MFP_Msk); + SYS->GPK_MFPH |= (SYS_GPK_MFPH_PK11MFP_VCAP0_HSYNC | SYS_GPK_MFPH_PK10MFP_VCAP0_PIXCLK | SYS_GPK_MFPH_PK9MFP_VCAP0_SCLK); + SYS->GPM_MFPH &= ~(SYS_GPM_MFPH_PM11MFP_Msk | SYS_GPM_MFPH_PM10MFP_Msk | SYS_GPM_MFPH_PM9MFP_Msk | SYS_GPM_MFPH_PM8MFP_Msk); + SYS->GPM_MFPH |= (SYS_GPM_MFPH_PM11MFP_VCAP0_DATA9 | SYS_GPM_MFPH_PM10MFP_VCAP0_DATA8 | SYS_GPM_MFPH_PM9MFP_VCAP0_DATA7 | SYS_GPM_MFPH_PM8MFP_VCAP0_DATA6); + SYS->GPM_MFPL &= ~(SYS_GPM_MFPL_PM7MFP_Msk | SYS_GPM_MFPL_PM6MFP_Msk | SYS_GPM_MFPL_PM5MFP_Msk | SYS_GPM_MFPL_PM4MFP_Msk | SYS_GPM_MFPL_PM3MFP_Msk | SYS_GPM_MFPL_PM2MFP_Msk | SYS_GPM_MFPL_PM1MFP_Msk | SYS_GPM_MFPL_PM0MFP_Msk); + SYS->GPM_MFPL |= (SYS_GPM_MFPL_PM7MFP_VCAP0_DATA5 | SYS_GPM_MFPL_PM6MFP_VCAP0_DATA4 | SYS_GPM_MFPL_PM5MFP_VCAP0_DATA3 | SYS_GPM_MFPL_PM4MFP_VCAP0_DATA2 | SYS_GPM_MFPL_PM3MFP_VCAP0_DATA1 | SYS_GPM_MFPL_PM2MFP_VCAP0_DATA0 | SYS_GPM_MFPL_PM1MFP_VCAP0_SFIELD | SYS_GPM_MFPL_PM0MFP_VCAP0_VSYNC); + + return; +} + +void nutool_pincfg_deinit_vcap0(void) +{ + SYS->GPK_MFPH &= ~(SYS_GPK_MFPH_PK11MFP_Msk | SYS_GPK_MFPH_PK10MFP_Msk | SYS_GPK_MFPH_PK9MFP_Msk); + SYS->GPM_MFPH &= ~(SYS_GPM_MFPH_PM11MFP_Msk | SYS_GPM_MFPH_PM10MFP_Msk | SYS_GPM_MFPH_PM9MFP_Msk | SYS_GPM_MFPH_PM8MFP_Msk); + SYS->GPM_MFPL &= ~(SYS_GPM_MFPL_PM7MFP_Msk | SYS_GPM_MFPL_PM6MFP_Msk | SYS_GPM_MFPL_PM5MFP_Msk | SYS_GPM_MFPL_PM4MFP_Msk | SYS_GPM_MFPL_PM3MFP_Msk | SYS_GPM_MFPL_PM2MFP_Msk | SYS_GPM_MFPL_PM1MFP_Msk | SYS_GPM_MFPL_PM0MFP_Msk); + + return; +} + +void nutool_pincfg_init_vcap1(void) +{ + SYS->GPN_MFPH &= ~(SYS_GPN_MFPH_PN14MFP_Msk | SYS_GPN_MFPH_PN13MFP_Msk | SYS_GPN_MFPH_PN12MFP_Msk | SYS_GPN_MFPH_PN11MFP_Msk | SYS_GPN_MFPH_PN10MFP_Msk | SYS_GPN_MFPH_PN9MFP_Msk | SYS_GPN_MFPH_PN8MFP_Msk); + SYS->GPN_MFPH |= (SYS_GPN_MFPH_PN14MFP_VCAP1_SFIELD | SYS_GPN_MFPH_PN13MFP_VCAP1_VSYNC | SYS_GPN_MFPH_PN12MFP_VCAP1_HSYNC | SYS_GPN_MFPH_PN11MFP_VCAP1_PIXCLK | SYS_GPN_MFPH_PN10MFP_VCAP1_SCLK | SYS_GPN_MFPH_PN9MFP_VCAP1_DATA9 | SYS_GPN_MFPH_PN8MFP_VCAP1_DATA8); + SYS->GPN_MFPL &= ~(SYS_GPN_MFPL_PN7MFP_Msk | SYS_GPN_MFPL_PN6MFP_Msk | SYS_GPN_MFPL_PN5MFP_Msk | SYS_GPN_MFPL_PN4MFP_Msk | SYS_GPN_MFPL_PN3MFP_Msk | SYS_GPN_MFPL_PN2MFP_Msk | SYS_GPN_MFPL_PN1MFP_Msk | SYS_GPN_MFPL_PN0MFP_Msk); + SYS->GPN_MFPL |= (SYS_GPN_MFPL_PN7MFP_VCAP1_DATA7 | SYS_GPN_MFPL_PN6MFP_VCAP1_DATA6 | SYS_GPN_MFPL_PN5MFP_VCAP1_DATA5 | SYS_GPN_MFPL_PN4MFP_VCAP1_DATA4 | SYS_GPN_MFPL_PN3MFP_VCAP1_DATA3 | SYS_GPN_MFPL_PN2MFP_VCAP1_DATA2 | SYS_GPN_MFPL_PN1MFP_VCAP1_DATA1 | SYS_GPN_MFPL_PN0MFP_VCAP1_DATA0); + + return; +} + +void nutool_pincfg_deinit_vcap1(void) +{ + SYS->GPN_MFPH &= ~(SYS_GPN_MFPH_PN14MFP_Msk | SYS_GPN_MFPH_PN13MFP_Msk | SYS_GPN_MFPH_PN12MFP_Msk | SYS_GPN_MFPH_PN11MFP_Msk | SYS_GPN_MFPH_PN10MFP_Msk | SYS_GPN_MFPH_PN9MFP_Msk | SYS_GPN_MFPH_PN8MFP_Msk); + SYS->GPN_MFPL &= ~(SYS_GPN_MFPL_PN7MFP_Msk | SYS_GPN_MFPL_PN6MFP_Msk | SYS_GPN_MFPL_PN5MFP_Msk | SYS_GPN_MFPL_PN4MFP_Msk | SYS_GPN_MFPL_PN3MFP_Msk | SYS_GPN_MFPL_PN2MFP_Msk | SYS_GPN_MFPL_PN1MFP_Msk | SYS_GPN_MFPL_PN0MFP_Msk); + + return; +} + +void nutool_pincfg_init(void) +{ + //SYS->GPA_MFPH = 0x06666666UL; + //SYS->GPA_MFPL = 0x66666666UL; + //SYS->GPB_MFPH = 0x8888CC44UL; + //SYS->GPB_MFPL = 0x88888888UL; + //SYS->GPC_MFPH = 0x66662222UL; + //SYS->GPC_MFPL = 0x66666666UL; + //SYS->GPD_MFPH = 0x00000000UL; + //SYS->GPD_MFPL = 0x00555555UL; + //SYS->GPE_MFPH = 0x11888888UL; + //SYS->GPE_MFPL = 0x88888888UL; + //SYS->GPF_MFPH = 0x10888888UL; + //SYS->GPF_MFPL = 0x88888888UL; + //SYS->GPG_MFPH = 0x00000666UL; + //SYS->GPG_MFPL = 0x00000000UL; + //SYS->GPH_MFPH = 0x66660000UL; + //SYS->GPH_MFPL = 0x66666666UL; + //SYS->GPI_MFPH = 0x66666666UL; + //SYS->GPI_MFPL = 0x22202220UL; + //SYS->GPJ_MFPH = 0x00446666UL; + //SYS->GPJ_MFPL = 0x66660000UL; + //SYS->GPK_MFPH = 0x55556660UL; + //SYS->GPK_MFPL = 0x00062222UL; + //SYS->GPL_MFPH = 0x44993300UL; + //SYS->GPL_MFPL = 0x00440000UL; + //SYS->GPM_MFPH = 0x66106666UL; + //SYS->GPM_MFPL = 0x66666666UL; + //SYS->GPN_MFPH = 0x56666666UL; + //SYS->GPN_MFPL = 0x66666666UL; + + nutool_pincfg_init_adc0(); + nutool_pincfg_init_can1(); + nutool_pincfg_init_can3(); + nutool_pincfg_init_eadc0(); + nutool_pincfg_init_epwm1(); + nutool_pincfg_init_hsusb0(); + nutool_pincfg_init_hsusbh(); + nutool_pincfg_init_i2c1(); + nutool_pincfg_init_i2c2(); + nutool_pincfg_init_i2c3(); + nutool_pincfg_init_i2c4(); + nutool_pincfg_init_i2c5(); + nutool_pincfg_init_i2s0(); + nutool_pincfg_init_lcm(); + nutool_pincfg_init_nand(); + nutool_pincfg_init_qspi0(); + nutool_pincfg_init_rgmii0(); + nutool_pincfg_init_rgmii1(); + nutool_pincfg_init_sd0(); + nutool_pincfg_init_sd1(); + nutool_pincfg_init_uart0(); + nutool_pincfg_init_uart11(); + nutool_pincfg_init_uart12(); + nutool_pincfg_init_uart14(); + nutool_pincfg_init_uart16(); + nutool_pincfg_init_vcap0(); + nutool_pincfg_init_vcap1(); + + return; +} + +void nutool_pincfg_deinit(void) +{ + nutool_pincfg_deinit_adc0(); + nutool_pincfg_deinit_can1(); + nutool_pincfg_deinit_can3(); + nutool_pincfg_deinit_eadc0(); + nutool_pincfg_deinit_epwm1(); + nutool_pincfg_deinit_hsusb0(); + nutool_pincfg_deinit_hsusbh(); + nutool_pincfg_deinit_i2c1(); + nutool_pincfg_deinit_i2c2(); + nutool_pincfg_deinit_i2c3(); + nutool_pincfg_deinit_i2c4(); + nutool_pincfg_deinit_i2c5(); + nutool_pincfg_deinit_i2s0(); + nutool_pincfg_deinit_lcm(); + nutool_pincfg_deinit_nand(); + nutool_pincfg_deinit_qspi0(); + nutool_pincfg_deinit_rgmii0(); + nutool_pincfg_deinit_rgmii1(); + nutool_pincfg_deinit_sd0(); + nutool_pincfg_deinit_sd1(); + nutool_pincfg_deinit_uart0(); + nutool_pincfg_deinit_uart11(); + nutool_pincfg_deinit_uart12(); + nutool_pincfg_deinit_uart14(); + nutool_pincfg_deinit_uart16(); + nutool_pincfg_deinit_vcap0(); + nutool_pincfg_deinit_vcap1(); + + return; +} + +/*** (C) COPYRIGHT 2013-2021 Nuvoton Technology Corp. ***/ diff --git a/bsp/nuvoton/numaker-hmi-ma35d1/board/nutool_pincfg/nutool_pincfg.cfg b/bsp/nuvoton/numaker-hmi-ma35d1/board/nutool_pincfg/nutool_pincfg.cfg new file mode 100644 index 0000000000..c51eaf23fe --- /dev/null +++ b/bsp/nuvoton/numaker-hmi-ma35d1/board/nutool_pincfg/nutool_pincfg.cfg @@ -0,0 +1,367 @@ +/**************************************************************************** + * @file nutool_pincfg.cfg + * @version V1.24 + * @Date 2021/08/03-14:56:48 + * @brief NuMicro config file + * + * @note Please do not modify this file. + * Otherwise, it may not be loaded successfully. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Copyright (C) 2013-2021 Nuvoton Technology Corp. All rights reserved. +*****************************************************************************/ +MCU:MA35D16A887C(BGA312) +PinA1:VSS +PinA2:I2C2_SCL +PinA3:EADC0_CH7 +PinA4:EADC0_CH3 +PinA5:RGMII1_TXCLK +PinA6:RGMII1_RXCLK +PinA7:RGMII1_RXCTL +PinA8:RGMII1_MDIO +PinA9:RGMII0_TXCLK +PinA10:RGMII0_RXD1 +PinA11:RGMII0_RXCLK +PinA12:RGMII0_TXCTL +PinA13:I2S0_DI +PinA14:VCAP1_SFIELD +PinA15:VCAP1_HSYNC +PinA16:VCAP1_PIXCLK +PinA17:VCAP1_DATA5 +PinA18:VSS +PinB1:ADC0_CH4 +PinB2:I2C1_SCL +PinB3:EADC0_CH5 +PinB4:EADC0_CH4 +PinB5:EADC0_CH1 +PinB6:RGMII1_TXD3 +PinB7:RGMII1_RXD0 +PinB8:RGMII1_TXCTL +PinB9:RGMII0_TXD2 +PinB10:RGMII0_RXD2 +PinB11:RGMII0_RXCTL +PinB12:RGMII0_MDIO +PinB13:I2S0_BCLK +PinB14:VCAP1_VSYNC +PinB15:VCAP1_SCLK +PinB16:VCAP1_DATA7 +PinB17:VCAP1_DATA0 +PinB18:VCAP1_DATA2 +PinC1:ADC0_CH7 +PinC2:ADC0_CH5 +PinC3:I2C2_SDA +PinC4:EADC0_CH2 +PinC5:EADC0_CH0 +PinC6:RGMII1_TXD2 +PinC7:RGMII1_RXD2 +PinC8:RGMII1_TXD0 +PinC9:RGMII0_TXD3 +PinC10:RGMII0_RXD0 +PinC11:RGMII0_TXD1 +PinC12:RGMII0_MDC +PinC13:I2S0_LRCK +PinC14:VCAP1_DATA8 +PinC15:VCAP1_DATA6 +PinC16:VCAP1_DATA4 +PinC17:VCAP1_DATA1 +PinC18:VCAP1_DATA3 +PinD1:ADC0_CH6 +PinD2:I2C1_SDA +PinD3:EADC0_CH6 +PinD4:VSS +PinD5:PF.14 +PinD6:RGMII1_RXD3 +PinD7:RGMII1_RXD1 +PinD8:RGMII1_TXD1 +PinD9:RGMII1_MDC +PinD10:RGMII0_RXD3 +PinD11:RGMII0_TXD0 +PinD12:I2S0_DO +PinD13:I2S0_MCLK +PinD14:VCAP1_DATA9 +PinD15:VSS +PinD16:UART10_nCTS +PinD17:UART10_TXD +PinD18:SD0_CLK +PinE1:HSUSBH_PWREN +PinE2:CAN1_RXD +PinE3:HSUSBH_OVC +PinE4:HSUSB0_VBUSVLD +PinE5:NC_ToolNotShow +PinE6:NC_ToolNotShow +PinE7:RTC_RPWR +PinE8:PH.9 +PinE9:PH.8 +PinE10:VDDIO9 +PinE11:VDDIO8 +PinE12:AVDDL_PLL2 +PinE13:NC_ToolNotShow +PinE14:NC_ToolNotShow +PinE15:UART10_nRTS +PinE16:UART10_RXD +PinE17:SD0_WP +PinE18:SD0_DAT0 +PinF1:XT1_IN +PinF2:XT1_OUT +PinF3:CAN1_TXD +PinF4:NAND_DATA3 +PinF5:NC_ToolNotShow +PinF6:VDD_HSUSB1 +PinF7:VBAT +PinF8:AVDD +PinF9:VREF_EADC0 +PinF10:AVDDH_PLL1 +PinF11:AVDDL_PLL1 +PinF12:VDD_PLL1 +PinF13:VDDIO7 +PinF14:NC_ToolNotShow +PinF15:PD.15 +PinF16:UART14_RXD +PinF17:SD0_nCD +PinF18:SD0_CMD +PinG1:X32_IN +PinG2:X32_OUT +PinG3:NAND_DATA0 +PinG4:NAND_DATA5 +PinG5:RTC_nRWAKE +PinG6:VDD_OTP +PinG7:VDD_HSUSB0 +PinG8:AVDD_ADC0 +PinG9:AVDD_EADC0 +PinG10:AVDDH_PLL0 +PinG11:AVDDL_PLL0 +PinG12:VDD_PLL0 +PinG13:VDDIO6 +PinG14:PD.13 +PinG15:PA.15 +PinG16:UART16_nRTS +PinG17:SD0_DAT3 +PinG18:SD0_DAT1 +PinH1:HSUSB1_D- +PinH2:HSUSB1_D+ +PinH3:NAND_DATA1 +PinH4:NAND_DATA7 +PinH5:nRESET +PinH6:HSUSB1_REXT +PinH7:AVDDL_PLL3 +PinH8:VDD_CORE +PinH9:AVSS +PinH10:AVSS_PLL +PinH11:VSS +PinH12:VDD_CORE +PinH13:MVDD +PinH14:MVREF +PinH15:UART12_nRTS +PinH16:UART16_nCTS +PinH17:PL.6 +PinH18:SD0_DAT2 +PinJ1:HSUSB0_D+ +PinJ2:HSUSB0_D- +PinJ3:NAND_DATA6 +PinJ4:NAND_RDY +PinJ5:HSUSB0_ID +PinJ6:HSUSB0_REXT +PinJ7:VDD_CORE +PinJ8:VSS +PinJ9:VSS +PinJ10:VSS +PinJ11:VSS +PinJ12:VDD_CORE +PinJ13:MVDD +PinJ14:MZQ_DDRPHY +PinJ15:UART12_RXD +PinJ16:UART16_TXD +PinJ17:PL.7 +PinJ18:I2C4_SCL +PinK1:NAND_DATA2 +PinK2:NAND_DATA4 +PinK3:NAND_nRE +PinK4:NAND_ALE +PinK5:NAND_nWE +PinK6:VDD_CORE +PinK7:VDD_CORE +PinK8:VSS +PinK9:VSS +PinK10:VSS +PinK11:VSS +PinK12:VDD_CORE +PinK13:MVDD +PinK14:MZQ_SDRAM +PinK15:PI.0 +PinK16:UART16_RXD +PinK17:PL.8 +PinK18:I2C4_SDA +PinL1:NAND_nCS +PinL2:NAND_CLE +PinL3:PG.2 +PinL4:PG.4 +PinL5:PG.6 +PinL6:VDDIO0 +PinL7:VDD_CPU +PinL8:VSS +PinL9:VSS +PinL10:VSS +PinL11:VSS +PinL12:VDD_CORE +PinL13:MVDD +PinL14:PD.14 +PinL15:UART12_TXD +PinL16:I2C5_SDA +PinL17:PL.9 +PinL18:PL.3 +PinM1:PG.1 +PinM2:PG.0 +PinM3:PG.5 +PinM4:PG.3 +PinM5:NAND_nWP +PinM6:VDDIO1 +PinM7:VDD_CPU +PinM8:VSS +PinM9:VSS +PinM10:VSS +PinM11:VSS +PinM12:MVDD_DPHYPLL +PinM13:VDDIO5 +PinM14:PD.12 +PinM15:UART14_nRTS +PinM16:I2C5_SCL +PinM17:CAN3_RXD +PinM18:PL.0 +PinN1:EPWM1_CH5 +PinN2:I2C3_SDA +PinN3:PM.12 +PinN4:PG.7 +PinN5:NC_ToolNotShow +PinN6:VDDIO2 +PinN7:VDD_CPU +PinN8:VDD_CPU +PinN9:VDD_CORE +PinN10:VDD_CORE +PinN11:VDD_CORE +PinN12:VDDIO3 +PinN13:VDDIO4 +PinN14:NC_ToolNotShow +PinN15:PI.4 +PinN16:PJ.15 +PinN17:CAN3_TXD +PinN18:PL.1 +PinP1:I2C3_SCL +PinP2:PG.12 +PinP3:PG.15 +PinP4:PG.11 +PinP5:NC_ToolNotShow +PinP6:NC_ToolNotShow +PinP7:VCAP0_SFIELD +PinP8:SD1_nCD +PinP9:SD1_WP +PinP10:PK.5 +PinP11:PK.6 +PinP12:PK.7 +PinP13:NC_ToolNotShow +PinP14:NC_ToolNotShow +PinP15:UART14_TXD +PinP16:PJ.14 +PinP17:PK.8 +PinP18:PL.2 +PinR1:PG.14 +PinR2:PG.13 +PinR3:PD.7 +PinR4:VSS +PinR5:VCAP0_DATA9 +PinR6:VCAP0_DATA7 +PinR7:PJ.1 +PinR8:PJ.3 +PinR9:SD1_DAT1 +PinR10:LCM_DEN +PinR11:LCM_DATA1 +PinR12:LCM_DATA6 +PinR13:LCM_DATA11 +PinR14:LCM_DATA15 +PinR15:VSS +PinR16:LCM_DATA18 +PinR17:LCM_DATA20 +PinR18:LCM_DATA22 +PinT1:UART0_TXD +PinT2:UART0_RXD +PinT3:PD.11 +PinT4:VCAP0_HSYNC +PinT5:VCAP0_DATA1 +PinT6:VCAP0_DATA5 +PinT7:VCAP0_DATA6 +PinT8:PJ.2 +PinT9:SD1_CMD +PinT10:LCM_VSYNC +PinT11:LCM_DATA0 +PinT12:LCM_DATA5 +PinT13:LCM_DATA10 +PinT14:LCM_DATA14 +PinT15:QSPI0_MISO1 +PinT16:LCM_DATA16 +PinT17:LCM_DATA17 +PinT18:LCM_DATA23 +PinU1:PD.6 +PinU2:PD.8 +PinU3:PD.10 +PinU4:VCAP0_VSYNC +PinU5:VCAP0_DATA2 +PinU6:VCAP0_DATA3 +PinU7:VCAP0_DATA8 +PinU8:SD1_DAT3 +PinU9:SD1_DAT0 +PinU10:LCM_HSYNC +PinU11:LCM_DATA7 +PinU12:LCM_DATA4 +PinU13:LCM_DATA9 +PinU14:LCM_DATA13 +PinU15:QSPI0_MISO0 +PinU16:QSPI0_SS0 +PinU17:LCM_DATA19 +PinU18:LCM_DATA21 +PinV1:VSS +PinV2:PD.9 +PinV3:VCAP0_SCLK +PinV4:VCAP0_PIXCLK +PinV5:VCAP0_DATA0 +PinV6:VCAP0_DATA4 +PinV7:PJ.0 +PinV8:SD1_CLK +PinV9:SD1_DAT2 +PinV10:LCM_CLK +PinV11:LCM_DATA2 +PinV12:LCM_DATA3 +PinV13:LCM_DATA8 +PinV14:LCM_DATA12 +PinV15:QSPI0_MOSI1 +PinV16:QSPI0_MOSI0 +PinV17:QSPI0_CLK +PinV18:VSS +SYS->GPA_MFPH = 0x06666666 +SYS->GPA_MFPL = 0x66666666 +SYS->GPB_MFPH = 0x8888CC44 +SYS->GPB_MFPL = 0x88888888 +SYS->GPC_MFPH = 0x66662222 +SYS->GPC_MFPL = 0x66666666 +SYS->GPD_MFPH = 0x00000000 +SYS->GPD_MFPL = 0x00555555 +SYS->GPE_MFPH = 0x11888888 +SYS->GPE_MFPL = 0x88888888 +SYS->GPF_MFPH = 0x10888888 +SYS->GPF_MFPL = 0x88888888 +SYS->GPG_MFPH = 0x00000666 +SYS->GPG_MFPL = 0x00000000 +SYS->GPH_MFPH = 0x66660000 +SYS->GPH_MFPL = 0x66666666 +SYS->GPI_MFPH = 0x66666666 +SYS->GPI_MFPL = 0x22202220 +SYS->GPJ_MFPH = 0x00446666 +SYS->GPJ_MFPL = 0x66660000 +SYS->GPK_MFPH = 0x55556660 +SYS->GPK_MFPL = 0x00062222 +SYS->GPL_MFPH = 0x44993300 +SYS->GPL_MFPL = 0x00440000 +SYS->GPM_MFPH = 0x66106666 +SYS->GPM_MFPL = 0x66666666 +SYS->GPN_MFPH = 0x56666666 +SYS->GPN_MFPL = 0x66666666 +/*** (C) COPYRIGHT 2013-2021 Nuvoton Technology Corp. ***/ diff --git a/bsp/nuvoton/numaker-hmi-ma35d1/board/nutool_pincfg/nutool_pincfg.h b/bsp/nuvoton/numaker-hmi-ma35d1/board/nutool_pincfg/nutool_pincfg.h new file mode 100644 index 0000000000..91a44d9411 --- /dev/null +++ b/bsp/nuvoton/numaker-hmi-ma35d1/board/nutool_pincfg/nutool_pincfg.h @@ -0,0 +1,26 @@ +/**************************************************************************** + * @file nutool_pincfg.h + * @version V1.24 + * @Date 2021/08/03-14:56:47 + * @brief NuMicro generated code file + * + * SPDX-License-Identifier: Apache-2.0 + * + * Copyright (C) 2013-2021 Nuvoton Technology Corp. All rights reserved. +*****************************************************************************/ + +#ifndef __NUTOOL_PINCFG_H__ +#define __NUTOOL_PINCFG_H__ + +#ifdef __cplusplus +extern "C" +{ +#endif +void nutool_pincfg_init_uart16(void); +void nutool_pincfg_deinit_uart16(void); +#ifdef __cplusplus +} +#endif +#endif /*__NUTOOL_PINCFG_H__*/ + +/*** (C) COPYRIGHT 2013-2021 Nuvoton Technology Corp. ***/ diff --git a/bsp/nuvoton/numaker-hmi-ma35d1/figures/LCD-Panel.png b/bsp/nuvoton/numaker-hmi-ma35d1/figures/LCD-Panel.png new file mode 100644 index 0000000000000000000000000000000000000000..eaa4bcfed1ccac036fd8475acc3d595899e4e9a0 GIT binary patch literal 585100 zcmZ^JWmH_v((d3cf#43og1c*QO>lR2cMSx$1b25E7+ePk4uiY9yZe35x%bnx?yp^| z_U@-@KUKZDySgI3D@mgv6Cwiu05n+{2^9bUHUt2Gu}6geM+39n9{tY)%2h>L98d!x zJ^}#90kRTeYF-AXow`+3vMC#llwI-`=cBE2eERxA{`304VMH0d@u5daqvy&0JdIO+ZXwmMEsG%{{^WO*4sYl1FbEOaKtsLDfT{xc@=AUanbQl(&P8fqhun;U>`OSX` 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index 0000000000..77ed9cf2e6 --- /dev/null +++ b/bsp/nuvoton/numaker-hmi-ma35d1/nuwriter_scripts/README.md @@ -0,0 +1,36 @@ +# nuwriter_scripts + +Some scripts can help you program firmware into storages in this folder. + +## Requirement + +### [Python for Window](https://www.python.org/downloads/windows/) + +After installing Python, some plug-in as below must be installed. +```bash +$ pip3 install pyusb usb crypto ecdsa crcmod tqdm pycryptodome +``` + +### [Libusb for Window](http://sourceforge.net/projects/libusb/files/libusb-1.0/libusb-1.0.20/libusb-1.0.20.7z/download) + +In Windows platform, it is required to install libusb manually. + +```bash +Step 1: Download the library extract the download file. +Step 2: Copy MS64\dll\libusb-1.0.dll to C:\Windows\System32. +Step 3: Copy MS64\dll\libusb-1.0.lib to C:\Users\\AppData\Local\Programs\Python\\Lib. +``` + +## Scripts + +### nuwriter_ddr_download_and_run.bat + +Download rttthread binary file into DDR. The address is 0x80400000. + +### nuwriter_nand_programming.bat + +Program header, DDR timing setting and rttthread binary file into NAND flash. + +### nuwriter_spinand_programming.bat + +Program header, DDR timing setting and rttthread binary file into SPI NAND flash. diff --git a/bsp/nuvoton/numaker-hmi-ma35d1/nuwriter_scripts/UnpackImage.py b/bsp/nuvoton/numaker-hmi-ma35d1/nuwriter_scripts/UnpackImage.py new file mode 100644 index 0000000000..29ae007767 --- /dev/null +++ b/bsp/nuvoton/numaker-hmi-ma35d1/nuwriter_scripts/UnpackImage.py @@ -0,0 +1,62 @@ +# NOTE: This script is test under Python 3.x + +__copyright__ = "Copyright (C) 2020 Nuvoton Technology Corp. All rights reserved" + +import sys +import crcmod + + +class UnpackImage: + + def __init__(self, pack_file_name): + self.img_list = [] + try: + with open(pack_file_name, "rb") as pack_file: + self.pack_data = pack_file.read() + except (IOError, OSError) as err: + print(f"Open {pack_file_name} failed") + sys.exit(err) + + if self.pack_data[0:4] != b'\x20\x54\x56\x4e': + print(f"{pack_file_name} marker check failed") + sys.exit(0) + + crc32_func = crcmod.predefined.mkCrcFun('crc-32') + checksum = crc32_func(self.pack_data[8:]) + if checksum != int.from_bytes(self.pack_data[4:8], byteorder='little'): + print(f"{pack_file_name} CRC check failed") + sys.exit(0) + self.image_cnt = int.from_bytes(self.pack_data[8:12], byteorder='little') + # 1st image descriptor begins @ 0x10 + index = 0x10 + for _ in range(self.image_cnt): + # Put the image length, offset ,attribute in list + self.img_list.append([int.from_bytes(self.pack_data[index: index + 8], byteorder='little'), + int.from_bytes(self.pack_data[index + 8: index + 16], byteorder='little'), + int.from_bytes(self.pack_data[index + 16: index + 20], byteorder='little'), + index + 24]) + index += int.from_bytes(self.pack_data[index: index + 8], byteorder='little') + 24 # 24 is image header + if index % 16 != 0: + index += 16 - (index & 0xF) # round to 16-byte align + + def img_count(self): + return self.image_cnt + + def img_attr(self, index): + if index < self.image_cnt: + # No need to return the last entry, actual offset in image file. + # And should return integers instead of list of integer here + return self.img_list[index][0], self.img_list[index][1], self.img_list[index][2] + else: + print("Invalid image index") + return 0, 0, 0 + + def img_content(self, index, offset, size): + if index >= self.image_cnt: + print("Invalid image index") + return '' + if offset > self.img_list[index][0] or offset + size > self.img_list[index][0]: + print("Invalid offset") + return '' + + return self.pack_data[self.img_list[index][3] + offset: self.img_list[index][3] + offset + size] diff --git a/bsp/nuvoton/numaker-hmi-ma35d1/nuwriter_scripts/_nuwriter_nand_generate_header_bin.bat b/bsp/nuvoton/numaker-hmi-ma35d1/nuwriter_scripts/_nuwriter_nand_generate_header_bin.bat new file mode 100644 index 0000000000..90242c39c5 --- /dev/null +++ b/bsp/nuvoton/numaker-hmi-ma35d1/nuwriter_scripts/_nuwriter_nand_generate_header_bin.bat @@ -0,0 +1,2 @@ +py -3 nuwriter.py -c header-nand.json +pause diff --git a/bsp/nuvoton/numaker-hmi-ma35d1/nuwriter_scripts/_nuwriter_nand_generate_pack_bin.bat b/bsp/nuvoton/numaker-hmi-ma35d1/nuwriter_scripts/_nuwriter_nand_generate_pack_bin.bat new file mode 100644 index 0000000000..80110b5deb --- /dev/null +++ b/bsp/nuvoton/numaker-hmi-ma35d1/nuwriter_scripts/_nuwriter_nand_generate_pack_bin.bat @@ -0,0 +1,2 @@ +py -3 nuwriter.py -p pack-nand.json +pause \ No newline at end of file diff --git a/bsp/nuvoton/numaker-hmi-ma35d1/nuwriter_scripts/header-nand.json b/bsp/nuvoton/numaker-hmi-ma35d1/nuwriter_scripts/header-nand.json new file mode 100644 index 0000000000..32ac04615d --- /dev/null +++ b/bsp/nuvoton/numaker-hmi-ma35d1/nuwriter_scripts/header-nand.json @@ -0,0 +1,36 @@ +{ + "header": + { + "version": "0x20210119", + "spiinfo": + { + "pagesize": "2048", + "sparearea": "64", + "pageperblk": "64", + "quadread": "0x6B", + "readsts": "0x05", + "writests": "0x01", + "stsvalue": "0x02", + "dummy1": "0", + "dummy2": "1", + "suspintvl": "1" + }, + "secureboot": "no", + "entrypoint": "0x80400000", + "image": + [ + { + "offset": "0x20000", + "loadaddr": "0x28030000", + "type": "2", + "file": "ddrimg/enc_ddr3_winbond_256mb.bin" + }, + { + "offset": "0x80000", + "loadaddr": "0x80400000", + "type": "4", + "file": "../rtthread.bin" + } + ] + } +} diff --git a/bsp/nuvoton/numaker-hmi-ma35d1/nuwriter_scripts/header-sd.json b/bsp/nuvoton/numaker-hmi-ma35d1/nuwriter_scripts/header-sd.json new file mode 100644 index 0000000000..9308222ab6 --- /dev/null +++ b/bsp/nuvoton/numaker-hmi-ma35d1/nuwriter_scripts/header-sd.json @@ -0,0 +1,36 @@ +{ + "header": + { + "version": "0x20210119", + "spiinfo": + { + "pagesize": "2048", + "sparearea": "64", + "pageperblk": "64", + "quadread": "0x6B", + "readsts": "0x05", + "writests": "0x01", + "stsvalue": "0x02", + "dummy1": "0", + "dummy2": "1", + "suspintvl": "1" + }, + "secureboot": "no", + "entrypoint": "0x80400000", + "image": + [ + { + "offset": "0x1000", + "loadaddr": "0x28030000", + "type": "2", + "file": "ddrimg/enc_ddr3_winbond_256mb.bin" + }, + { + "offset": "0x4000", + "loadaddr": "0x80400000", + "type": "4", + "file": "../rtthread.bin" + } + ] + } +} diff --git a/bsp/nuvoton/numaker-hmi-ma35d1/nuwriter_scripts/nuwriter.py b/bsp/nuvoton/numaker-hmi-ma35d1/nuwriter_scripts/nuwriter.py new file mode 100644 index 0000000000..a9dfea35b5 --- /dev/null +++ b/bsp/nuvoton/numaker-hmi-ma35d1/nuwriter_scripts/nuwriter.py @@ -0,0 +1,1938 @@ +# NOTE: This script is test under Python 3.x + +__copyright__ = "Copyright (C) 2020~2021 Nuvoton Technology Corp. All rights reserved" +__version__ = "v0.37" + +import os +import sys +import argparse +import json +import crcmod +from Crypto.Cipher import AES +import hashlib +import ecdsa +import binascii +from datetime import datetime +import random +import shutil +from tqdm import tqdm +from xusbcom import XUsbComList +from concurrent.futures import ThreadPoolExecutor, as_completed +from UnpackImage import UnpackImage +from collections import namedtuple +from struct import unpack +import time +import platform +# for debug +import usb.core +import usb.util + +ACK = 0x55AA55AA +TRANSFER_SIZE = 4096 +MAX_HEADER_IMG = 4 +# SPI NOR align for erase/program starting address +SPINOR_ALIGN = 4096 + +# Storage device type +DEV_DDR_SRAM = 0 +DEV_NAND = 1 +DEV_SD_EMMC = 2 +DEV_SPINOR = 3 +DEV_SPINAND = 4 +DEV_OTP = 6 +DEV_USBH = 7 +DEV_UNKNOWN = 0xFF + +# For OTP programming +ACT_LOAD = 1 +ACT_WRITE = 2 +ACT_ERASE = 3 +ACT_READ = 4 +ACT_MSC = 5 + +# Command options +OPT_NONE = 0 +OPT_SCRUB = 1 # For erase, use with care +OPT_WITHBAD = 1 # For read +OPT_EXECUTE = 2 # For write +OPT_VERIFY = 3 # For write +OPT_UNPACK = 4 # For pack +OPT_RAW = 5 # For write +OPT_EJECT = 6 # For msc +OPT_STUFF = 7 # For stuff pack, output could be used by dd command +OPT_SETINFO = 8 # For set storage info for attach +OPT_CONCAT = 9 # For convert, concatenate at the end of encrypted data file +OPT_SHOWHDR = 10 # For convert. Instead of convert, show header content instead +OPT_UNKNOWN = 0xFF # Error + + +# OPT block definitions +OPT_OTPBLK1 = 0x100 +OPT_OTPBLK2 = 0x200 +OPT_OTPBLK3 = 0x400 +OPT_OTPBLK4 = 0x800 +OPT_OTPBLK5 = 0x1000 +OPT_OTPBLK6 = 0x2000 +OPT_OTPBLK7 = 0x4000 +OPT_OTPKEY = 0x8000 + +# for key lock +OPT_OTPKEY0 = 0x10000 +OPT_OTPKEY1 = 0x20000 +OPT_OTPKEY2 = 0x40000 +OPT_OTPKEY3 = 0x80000 +OPT_OTPKEY4 = 0x100000 +OPT_OTPKEY5 = 0x200000 + + +# Image type definitions +IMG_DATA = 0 +IMG_TFA = 1 +IMG_UBOOT = 2 +IMG_LINUX = 3 +IMG_DDR = 4 +IMG_TEE = 5 +IMG_DTB = 6 + +# If attach is a must. maybe better for real chip. +# devices = [] +mp_mode = False + +WINDOWS_PATH = "C:\\Program Files (x86)\\Nuvoton Tools\\NuWriter\\" +LINUX_PATH = "/usr/share/nuwriter/" + + +def conv_env(env_file_name, blk_size) -> bytearray: + + try: + with open(env_file_name, "r") as env_file: + env_data = env_file.read().splitlines() + except (IOError, OSError) as err: + print(f"Open {env_file_name} failed") + sys.exit(err) + + out = bytearray(4) # Reserved for CRC + for lines in env_data: + out += bytes(lines, 'ascii') + out += b'\x00' + out += b'\x00' + out += b'\xFF' * (blk_size - len(out)) + + crc32_func = crcmod.predefined.mkCrcFun('crc-32') + checksum = crc32_func(out[4:]) + out[0:4] = checksum.to_bytes(4, byteorder="little") + + return out + + +def get_dpm(dpm) -> int: + return { + 'a35sdsdis': 0x00000001, + 'a35sdslock': 0x00000002, + 'a35sndsdis': 0x00000004, + 'a35sndslock': 0x00000008, + 'a35nsdsdis': 0x00000010, + 'a35nsdslock': 0x00000020, + 'a35nsndsdis': 0x00000040, + 'a35nsndslock': 0x00000080, + 'm4dsdis': 0x00000100, + 'm4dslock': 0x00000200, + 'm4ndsdis': 0x00000400, + 'm4ndslock': 0x00000800, + 'extdis': 0x00001000, + 'extlock': 0x00002000, + 'exttdis': 0x00004000, + 'exttlock': 0x00008000, + 'giccfgsdis': 0x00010000, + 'giccfgslock': 0x00020000 + }.get(dpm, 0) + + +def get_plm(plm) -> int: + return { + 'oem': 0x1, + 'deploy': 0x3, + 'rma': 0x7, + 'prma': 0xF + }.get(plm, 0) + + +def conv_otp(opt_file_name) -> (bytearray, int): + try: + with open(opt_file_name, "r") as json_file: + try: + d = json.load(json_file) + except json.decoder.JSONDecodeError as err: + print(f"{opt_file_name} parsing error") + sys.exit(err) + except (IOError, OSError) as err: + print(f"Open {opt_file_name} failed") + sys.exit(err) + # Bootcfg, DPM, PLM, and PWD 4 bytes each, MAC addr 8 bytes each, sec/nsec 88 bytes each + data = bytearray(208) + + option = 0 + for key in d.keys(): + if key == 'boot_cfg': + cfg_val = 0 + for sub_key in d['boot_cfg'].keys(): + if sub_key == 'posotp': + if d['boot_cfg']['posotp'] == 'enable': + cfg_val |= 1 + if sub_key == 'qspiclk': + if d['boot_cfg']['qspiclk'] == '50mhz': + cfg_val |= 2 + if sub_key == 'wdt1en': + if d['boot_cfg']['wdt1en'] == 'enable': + cfg_val |= 4 + if sub_key == 'uart0en': + if d['boot_cfg']['uart0en'] == 'disable': + cfg_val |= 0x10 + if sub_key == 'sd0bken': + if d['boot_cfg']['sd0bken'] == 'enable': + cfg_val |= 0x20 + if sub_key == 'tsiimg': + if d['boot_cfg']['tsiimg'] == 'enable': + cfg_val |= 0x40 + if sub_key == 'tsidbg': + if d['boot_cfg']['tsidbg'] == 'disable': + cfg_val |= 0x80 + if sub_key == 'bootsrc': + if d['boot_cfg']['bootsrc'] == 'sd' or d['boot_cfg']['bootsrc'] == 'emmc': + cfg_val |= 0x400 + elif d['boot_cfg']['bootsrc'] == 'nand': + cfg_val |= 0x800 + elif d['boot_cfg']['bootsrc'] == 'usb': + cfg_val |= 0xC00 + if sub_key == 'page': + if d['boot_cfg']['page'] == '2k': + cfg_val |= 0x1000 + elif d['boot_cfg']['page'] == '4k': + cfg_val |= 0x2000 + elif d['boot_cfg']['page'] == '8k': + cfg_val |= 0x3000 + if sub_key == 'option': + if d['boot_cfg']['option'] == 'sd1' or d['boot_cfg']['option'] == 'emmc1' or \ + d['boot_cfg']['option'] == 't12' or d['boot_cfg']['option'] == 'spinand4': + cfg_val |= 0x4000 + elif d['boot_cfg']['option'] == 't24' or d['boot_cfg']['option'] == 'spinor1': + cfg_val |= 0x8000 + elif d['boot_cfg']['option'] == 'noecc' or d['boot_cfg']['option'] == 'spinor4': + cfg_val |= 0xC000 + if sub_key == 'secboot': + if d['boot_cfg']['secboot'] == 'disable': + cfg_val |= 0x5A000000 + data[0:4] = cfg_val.to_bytes(4, byteorder='little') + option |= OPT_OTPBLK1 + elif key == 'dpm_plm': + for sub_key in d['dpm_plm'].keys(): + if sub_key == 'dpm': + dpm_val = 0 + for dpm_key in d['dpm_plm']['dpm'].keys(): + dpm_val |= get_dpm(dpm_key) + if dpm_val != 0: + data[4:8] = dpm_val.to_bytes(4, byteorder='little') + elif sub_key == 'plm': + plm_val = get_plm(d['dpm_plm']['plm']) + if plm_val != 0: + data[8:12] = plm_val.to_bytes(4, byteorder='little') + option |= OPT_OTPBLK2 + elif key == 'mac0': + data[12:18] = bytes.fromhex(d['mac0']) + option |= OPT_OTPBLK3 + elif key == 'mac1': + data[20:26] = bytes.fromhex(d['mac1']) + option |= OPT_OTPBLK4 + elif key == 'dplypwd': + data[28:32] = bytes.fromhex(d['dplypwd']) + option |= OPT_OTPBLK5 + elif key == 'sec': + newkey = bytes.fromhex(d['sec']) + newkey += b'\x00' * (88 - len(newkey)) + data[32:120] = newkey + option |= OPT_OTPBLK6 + elif key == 'nonsec': + newkey = bytes.fromhex(d['nonsec']) + newkey += b'\x00' * (88 - len(newkey)) + data[120:208] = newkey + option |= OPT_OTPBLK7 + elif key == 'huk0': + newkey = bytes.fromhex(d['huk0']['key']) + if len(newkey) != 16: + print("HUK0 is 128-bit") + sys.exit(2) + newkey += b'\x00' * (32 - len(newkey)) + # size - 128-bit + newkey += b'\x08\x00\x00\x00' + # key number - 0 + newkey += b'\x00\x00\x00\x00' + # meta - owner: cpu, cpu readable + newkey += b'\x04\x00\x05\x80' + data += newkey + + elif key == 'huk1': + newkey = bytes.fromhex(d['huk1']['key']) + if len(newkey) != 16: + print("HUK1 is 128-bit") + sys.exit(2) + newkey += b'\x00' * (32 - len(newkey)) + # size - 128-bit + newkey += b'\x08\x00\x00\x00' + # key number - 1 + newkey += b'\x01\x00\x00\x00' + # meta - owner: cpu, cpu readable + newkey += b'\x04\x00\x05\x80' + data += newkey + + elif key == 'huk2': + newkey = bytes.fromhex(d['huk2']['key']) + if len(newkey) != 16: + print("HUK0 is 128-bit") + sys.exit(2) + newkey += b'\x00' * (32 - len(newkey)) + # size - 128-bit + newkey += b'\x08\x00\x00\x00' + # key number - 2 + newkey += b'\x02\x00\x00\x00' + # meta - owner: cpu, cpu readable + newkey += b'\x04\x00\x05\x80' + data += newkey + + elif key == 'key3': + newkey = bytes.fromhex(d['key3']['key']) + if len(newkey) != 32: + print("key3 is 256-bit") + sys.exit(2) + newkey += b'\x00' * (32 - len(newkey)) + # size - 256-bit + newkey += b'\x00\x01\x00\x00' + # key number - 3 + newkey += b'\x03\x00\x00\x00' + + if d['key3']['meta'] == 'aes256-unreadable': + newkey += b'\x00\x06\x00\x80' + elif d['key3']['meta'] == 'aes256-cpu-readable': + newkey += b'\x04\x06\x00\x80' + elif d['key3']['meta'] == 'sha256-unreadable': + newkey += b'\x00\x06\x01\x80' + elif d['key3']['meta'] == 'sha256-cpu-readable': + newkey += b'\x04\x06\x01\x80' + elif d['key3']['meta'] == 'eccp256-unreadable': + newkey += b'\x00\x06\x04\x80' + elif d['key3']['meta'] == 'eccp256-cpu-readable': + newkey += b'\x04\x06\x04\x80' + + data += newkey + elif key == 'key4': + newkey = bytes.fromhex(d['key4']['key']) + if len(newkey) != 32: + print("key4 is 256-bit") + sys.exit(2) + newkey += b'\x00' * (32 - len(newkey)) + # size - 256-bit + newkey += b'\x00\x01\x00\x00' + # key number - 4 + newkey += b'\x04\x00\x00\x00' + + if d['key4']['meta'] == 'aes256-unreadable': + newkey += b'\x00\x06\x00\x80' + elif d['key4']['meta'] == 'aes256-cpu-readable': + newkey += b'\x04\x06\x00\x80' + elif d['key4']['meta'] == 'sha256-unreadable': + newkey += b'\x00\x06\x01\x80' + elif d['key4']['meta'] == 'sha256-cpu-readable': + newkey += b'\x04\x06\x01\x80' + elif d['key4']['meta'] == 'eccp256-unreadable': + newkey += b'\x00\x06\x04\x80' + elif d['key4']['meta'] == 'eccp256-cpu-readable': + newkey += b'\x04\x06\x04\x80' + + data += newkey + elif key == 'key5': + newkey = bytes.fromhex(d['key5']['key']) + if len(newkey) != 32: + print("key5 is 256-bit") + sys.exit(2) + newkey += b'\x00' * (32 - len(newkey)) + # size - 256-bit + newkey += b'\x00\x01\x00\x00' + # key number - 5 + newkey += b'\x05\x00\x00\x00' + + if d['key5']['meta'] == 'aes256-unreadable': + newkey += b'\x00\x06\x00\x80' + elif d['key5']['meta'] == 'aes256-cpu-readable': + newkey += b'\x04\x06\x00\x80' + elif d['key5']['meta'] == 'sha256-unreadable': + newkey += b'\x00\x06\x01\x80' + elif d['key5']['meta'] == 'sha256-cpu-readable': + newkey += b'\x04\x06\x01\x80' + elif d['key5']['meta'] == 'eccp256-unreadable': + newkey += b'\x00\x06\x04\x80' + elif d['key5']['meta'] == 'eccp256-cpu-readable': + newkey += b'\x04\x06\x04\x80' + + data += newkey + elif key == 'publicx': + newkey = bytes.fromhex(d['publicx']) + if len(newkey) != 32: + print("IBR publicx is 256-bit") + sys.exit(2) + data += bytes.fromhex(d['publicx']) + data += b'\x00\x01\x00\x00' # 256 bits + data += b'\x06\x00\x00\x00' + data += b'\x01\x06\x04\x80' + elif key == 'publicy': + newkey = bytes.fromhex(d['publicy']) + if len(newkey) != 32: + print("IBR publicy is 256-bit") + sys.exit(2) + data += bytes.fromhex(d['publicy']) + data += b'\x00\x01\x00\x00' # 256 bits + data += b'\x07\x00\x00\x00' + data += b'\x01\x06\x04\x80' + elif key == 'aeskey': + newkey = bytes.fromhex(d['aeskey']) + if len(newkey) != 32: + print("IBR aeskey is 256-bit") + sys.exit(2) + data += bytes.fromhex(d['aeskey']) + data += b'\x00\x01\x00\x00' # 256 bits + data += b'\x08\x00\x00\x00' + data += b'\x01\x06\x00\x80' + + try: + with open("otp_data.bin", "wb") as out_file: + out_file.write(data[0:len(data)]) + except (IOError, OSError) as err: + print(f"Open otp_data.bin failed") + sys.exit(err) + + if len(data) > 208: + option |= OPT_OTPKEY + return data, option + + +def __img_erase(dev, media, start, length, option) -> int: + + nand_align, spinand_align = dev.get_align() + + if (media == DEV_NAND and nand_align == 0) or \ + (media == DEV_SPINAND and spinand_align == 0): + print("Unable to get block size") + return -1 + + if (media == DEV_NAND and start % nand_align != 0) or\ + (media == DEV_SPINAND and start % spinand_align != 0) or \ + (media == DEV_SPINOR and start % SPINOR_ALIGN != 0): + print("Starting address must be block aligned") + return -1 + + cmd = start.to_bytes(8, byteorder='little') + cmd += length.to_bytes(8, byteorder='little') + cmd += ACT_ERASE.to_bytes(4, byteorder='little') + cmd += option.to_bytes(4, byteorder='little') + + dev.set_media(media) + dev.write(cmd) + ack = dev.read(4) + if int.from_bytes(ack, byteorder="little") != ACK: + print("Receive ACK error") + return -1 + bar = tqdm(total=100, position=dev.get_id(), ascii=True) + previous_progress = 0 + while True: + # xusb ack with total erase progress. + ack = dev.read(4) + if int.from_bytes(ack, byteorder="little") <= 100: + bar.update(int.from_bytes(ack, byteorder="little") - previous_progress) + previous_progress = int.from_bytes(ack, byteorder="little") + if int.from_bytes(ack, byteorder="little") == 100: + break + bar.close() + return 0 + + +# default erase all (count=0) +def do_img_erase(media, start, length=0, option=OPT_NONE) -> None: + global mp_mode + + # devices = XUsbComList(attach_all=mp_mode).get_dev() + _XUsbComList = XUsbComList(attach_all=mp_mode) + devices = _XUsbComList.get_dev() + + if len(devices) == 0: + print("Device not found") + sys.exit(2) + + with ThreadPoolExecutor(max_workers=8) as executor: + futures = [executor.submit(__img_erase, dev, media, start, length, option) for dev in devices] + success = 0 + failed = 0 + for future in as_completed(futures): + if future.result() == 0: + success += 1 + else: + failed += 1 + + print(f"Successfully erased {success} device(s)") + if failed > 0: + print(f"Failed to erase {failed} device(s)") + + +def do_otp_erase(option) -> None: + global mp_mode + + # devices = XUsbComList(attach_all=mp_mode).get_dev() + _XUsbComList = XUsbComList(attach_all=mp_mode) + devices = _XUsbComList.get_dev() + + if len(devices) == 0: + print("Device not found") + sys.exit(2) + + start = 0 + length = 0 + dev = devices[0] + load_otp_writer(dev) + cmd = start.to_bytes(8, byteorder='little') + cmd += length.to_bytes(8, byteorder='little') + cmd += ACT_ERASE.to_bytes(4, byteorder='little') + cmd += option.to_bytes(4, byteorder='little') + + dev.set_media(DEV_OTP) + dev.write(cmd) + ack = dev.read(4) + if int.from_bytes(ack, byteorder="little") != ACK: + print("Receive ACK error") + print(f"Failed to erase device(s)") + + # There's no way to tell the progress... + ack = dev.read(4) + data = int.from_bytes(ack, byteorder="little") + if option == 0x100: + data >>= 2 + data &= 0x3 + if option == 0x400: + data >>= 6 + data &= 0x3 + if option == 0x800: + data >>= 8 + data &= 0x3 + if option & 0x8000: + data >>= 16 + #print(f"Erase count state {hex(data)}") + + print(f"Successfully erased device(s)") + +def load_otp_writer(dev) -> int: + try: + with open("otp_writer.bin", "rb") as writer_file: + otp_writer = writer_file.read() + except (IOError, OSError) as err: + print(f"Open {opt_file_name} failed") + sys.exit(err) + + option = 0 + img_length = len(otp_writer) + cmd = b'\x00\x00\xf0\x86\x00\x00\x00\x00' + cmd += img_length.to_bytes(8, byteorder='little') + cmd += ACT_LOAD.to_bytes(4, byteorder='little') + cmd += option.to_bytes(4, byteorder='little') + dev.set_media(DEV_OTP) + dev.write(cmd) + ack = dev.read(4) + if int.from_bytes(ack, byteorder="little") != ACK: + print("Receive ACK error") + return -1 + + for offset in range(0, img_length, TRANSFER_SIZE): + xfer_size = TRANSFER_SIZE if offset + TRANSFER_SIZE < img_length else img_length - offset + dev.write(otp_writer[offset: offset + xfer_size]) + ack = dev.read(4) + if int.from_bytes(ack, byteorder="little") != xfer_size: + print("Acked size error") + return -1 + + while True: + # wait TSI update firmware + ack = dev.read(4) + if int.from_bytes(ack, byteorder="little") == ACK: + break + + return 0 + +def __otp_program(dev, otp_data, option) -> int: + + img_length = len(otp_data) + + cmd = b'\x00\x00\xf0\x86\x00\x00\x00\x00' + cmd += img_length.to_bytes(8, byteorder='little') + cmd += ACT_WRITE.to_bytes(4, byteorder='little') + cmd += option.to_bytes(4, byteorder='little') + + dev.set_media(DEV_OTP) + dev.write(cmd) + ack = dev.read(4) + if int.from_bytes(ack, byteorder="little") != ACK: + print("Receive ACK error") + return -1 + # There's no way to tell the progress... + dev.write(otp_data) + ack = dev.read(4) + if int.from_bytes(ack, byteorder="little") != img_length: + print("Acked size error") + return -1 + + # There's no way to tell the progress... + ack = dev.read(4) + data = int.from_bytes(ack, byteorder="little") + #print(f"Can program count {hex(data)}") + + return 0 + + +def do_otp_program(opt_file_name) -> None: + global mp_mode + + # devices = XUsbComList(attach_all=mp_mode).get_dev() + _XUsbComList = XUsbComList(attach_all=mp_mode) + devices = _XUsbComList.get_dev() + + if len(devices) == 0: + print("Device not found") + sys.exit(2) + + load_otp_writer(devices[0]) + otp_data, option = conv_otp(opt_file_name) + + with ThreadPoolExecutor(max_workers=8) as executor: + futures = [executor.submit(__otp_program, dev, otp_data, option) for dev in devices] + success = 0 + failed = 0 + for future in as_completed(futures): + if future.result() == 0: + success += 1 + else: + failed += 1 + + print(f"Successfully programmed {success} device(s)") + if failed > 0: + print(f"Failed to program {failed} device(s)") + + +def do_otp_read(media, start, out_file_name, length=0x1, option=OPT_NONE) -> None: + global mp_mode + + # devices = XUsbComList(attach_all=mp_mode).get_dev() + _XUsbComList = XUsbComList(attach_all=mp_mode) + devices = _XUsbComList.get_dev() + + if len(devices) == 0: + print("Device not found") + sys.exit(2) + + # Only support one device in read function + dev = devices[0] + load_otp_writer(dev) + + cmd = start.to_bytes(8, byteorder='little') + cmd += length.to_bytes(8, byteorder='little') + cmd += ACT_READ.to_bytes(4, byteorder='little') + cmd += option.to_bytes(4, byteorder='little') + + dev.set_media(media) + dev.write(cmd) + ack = dev.read(4) + if int.from_bytes(ack, byteorder="little") != ACK: + print("Receive ACK error") + return + # FIXME: Don't know real length for "read all" + bar = tqdm(total=length, ascii=True) + data = b'' + remain = length + + while remain > 0: + ack = dev.read(4) + # Get the transfer length of next read + xfer_size = int.from_bytes(ack, byteorder="little") + + data += dev.read(xfer_size) + dev.write(xfer_size.to_bytes(4, byteorder='little')) # ack + remain -= xfer_size + bar.update(xfer_size) + try: + with open(out_file_name, "wb") as out_file: + out_file.write(data[0:length]) + except (IOError, OSError) as err: + print(f"Open {out_file_name} failed") + sys.exit(err) + + bar.close() + + +def __pack_program(dev, media, pack_image, option) -> int: + + nand_align, spinand_align = dev.get_align() + image_cnt = pack_image.img_count() + + if (media == DEV_NAND and nand_align == 0) or \ + (media == DEV_SPINAND and spinand_align == 0): + print("Unable to get block size") + return -1 + + for i in range(image_cnt): + img_length, img_start, img_type = pack_image.img_attr(i) + if (media == DEV_NAND and img_start % nand_align != 0) or \ + (media == DEV_SPINAND and img_start % spinand_align != 0) or \ + (media == DEV_SPINOR and img_start % SPINOR_ALIGN != 0): + print("Starting address must be block aligned") + return -1 + time.sleep(1) + dev.set_media(media) + cmd = img_start.to_bytes(8, byteorder='little') + cmd += img_length.to_bytes(8, byteorder='little') + cmd += ACT_WRITE.to_bytes(4, byteorder='little') + cmd += img_type.to_bytes(4, byteorder='little') + + dev.write(cmd) + ack = dev.read(4) + if int.from_bytes(ack, byteorder="little") != ACK: + print("Receive ACK error") + return -1 + text = f"Programming {i}/{image_cnt}" + bar = tqdm(total=img_length, position=dev.get_id(), ascii=True, desc=text) + for offset in range(0, img_length, TRANSFER_SIZE): + xfer_size = TRANSFER_SIZE if offset + TRANSFER_SIZE < img_length else img_length - offset + dev.write(pack_image.img_content(i, offset, xfer_size)) + ack = dev.read(4) + if int.from_bytes(ack, byteorder="little") != xfer_size: + print("Ack size error") + return -1 + bar.update(xfer_size) + bar.close() + dev.read(4) + + # FIXME: Added time.sleep(1) to make SPI NAND Pack Program + Verify PASS + time.sleep(1) + + if option == OPT_VERIFY: + dev.set_media(media) + cmd = img_start.to_bytes(8, byteorder='little') + cmd += img_length.to_bytes(8, byteorder='little') + cmd += ACT_READ.to_bytes(4, byteorder='little') + cmd += b'\x00' * 4 + + dev.write(cmd) + ack = dev.read(4) + if int.from_bytes(ack, byteorder="little") != ACK: + print("Receive ACK error") + return -1 + remain = img_length + text = f"Verifying {i}/{image_cnt}" + bar = tqdm(total=img_length, position=dev.get_id(), ascii=True, desc=text) + while remain > 0: + ack = dev.read(4) + # Get the transfer length of next read + xfer_size = int.from_bytes(ack, byteorder="little") + + data = dev.read(xfer_size) + dev.write(xfer_size.to_bytes(4, byteorder='little')) + offset = img_length - remain + + # For SD/eMMC + if xfer_size > remain: + xfer_size = remain + data = data[0: remain] + + if data != bytearray(pack_image.img_content(i, offset, xfer_size)): + print("Verify failed") + return -1 + remain -= xfer_size + bar.update(xfer_size) + bar.close() + return 0 + + +def do_pack_program(media, pack_file_name, option=OPT_NONE) -> None: + global mp_mode + + # devices = XUsbComList(attach_all=mp_mode).get_dev() + _XUsbComList = XUsbComList(attach_all=mp_mode) + devices = _XUsbComList.get_dev() + + if len(devices) == 0: + print("Device not found") + sys.exit(2) + + pack_image = UnpackImage(pack_file_name) + with ThreadPoolExecutor(max_workers=8) as executor: + futures = [executor.submit(__pack_program, dev, media, pack_image, option) for dev in devices] + success = 0 + failed = 0 + for future in as_completed(futures): + if future.result() == 0: + success += 1 + else: + failed += 1 + + print(f"Successfully programmed {success} device(s)") + if failed > 0: + print(f"Failed to program {failed} device(s)") + + +def __img_program(dev, media, start, img_data, option) -> int: + + nand_align, spinand_align = dev.get_align() + + if (media == DEV_NAND and nand_align == 0) or \ + (media == DEV_SPINAND and spinand_align == 0): + print("Unable to get block size") + return -1 + + if (media == DEV_NAND and start % nand_align != 0) or\ + (media == DEV_SPINAND and start % spinand_align != 0) or \ + (media == DEV_SPINOR and start % SPINOR_ALIGN != 0): + print("Starting address must be block aligned") + return -1 + + img_length = len(img_data) + print(f"image length is {img_length}") + cmd = start.to_bytes(8, byteorder='little') + cmd += img_length.to_bytes(8, byteorder='little') + cmd += ACT_WRITE.to_bytes(4, byteorder='little') + if option == OPT_EXECUTE: + cmd += option.to_bytes(4, byteorder='little') + else: + cmd += b'\x00' * 4 + + dev.set_media(media) + dev.write(cmd) + ack = dev.read(4) + if int.from_bytes(ack, byteorder="little") != ACK: + print("Receive ACK error") + return -1 + + # Set ascii=True is for Windows cmd terminal, position > 0 doesn't work as expected in cmd though... + bar = tqdm(total=img_length, position=dev.get_id(), ascii=True, desc="Programming") + for offset in range(0, img_length, TRANSFER_SIZE): + xfer_size = TRANSFER_SIZE if offset + TRANSFER_SIZE < img_length else img_length - offset + dev.write(img_data[offset: offset + xfer_size]) + ack = dev.read(4) + if int.from_bytes(ack, byteorder="little") != xfer_size: + print("Ack size error") + return -1 + bar.update(xfer_size) + dev.read(4) + bar.close() + if option == OPT_VERIFY: + dev.set_media(media) + cmd = start.to_bytes(8, byteorder='little') + cmd += img_length.to_bytes(8, byteorder='little') + cmd += ACT_READ.to_bytes(4, byteorder='little') + cmd += b'\x00' * 4 + + dev.write(cmd) + ack = dev.read(4) + if int.from_bytes(ack, byteorder="little") != ACK: + print("Receive ACK error") + return -1 + + remain = img_length + bar = tqdm(total=img_length, position=dev.get_id(), ascii=True, desc="Verifying") + while remain > 0: + ack = dev.read(4) + # Get the transfer length of next read + xfer_size = int.from_bytes(ack, byteorder="little") + + data = dev.read(xfer_size) + dev.write(xfer_size.to_bytes(4, byteorder='little')) # ack + offset = img_length - remain + + # For SD/eMMC + if xfer_size > remain: + xfer_size = remain + data = data[0: remain] + + if data != bytearray(img_data[offset: offset + xfer_size]): + print("Verify failed") + return -1 + remain -= xfer_size + bar.update(xfer_size) + print("Verify pass") + bar.close() + return 0 + + +def do_img_program(media, start, image_file_name, option=OPT_NONE) -> None: + global mp_mode + + # devices = XUsbComList(attach_all=mp_mode).get_dev() + _XUsbComList = XUsbComList(attach_all=mp_mode) + devices = _XUsbComList.get_dev() + + if len(devices) == 0: + print("Device not found") + sys.exit(2) + try: + with open(image_file_name, "rb") as image_file: + img_data = image_file.read() + + except (IOError, OSError) as err: + print(f"Open {image_file_name} failed") + sys.exit(err) + + with ThreadPoolExecutor(max_workers=8) as executor: + futures = [executor.submit(__img_program, dev, media, start, img_data, option) for dev in devices] + success = 0 + failed = 0 + for future in as_completed(futures): + if future.result() == 0: + success += 1 + else: + failed += 1 + + print(f"Successfully programmed {success} device(s)") + if failed > 0: + print(f"Failed to program {failed} device(s)") + + +def do_img_read(media, start, out_file_name, length=0x1, option=OPT_NONE) -> None: + # only support read from 1 device + # devices = XUsbComList(attach_all=False).get_dev() + _XUsbComList = XUsbComList(attach_all=False) + devices = _XUsbComList.get_dev() + + if len(devices) == 0: + print("Device not found") + sys.exit(2) + # Only support one device in read function + dev = devices[0] + + cmd = start.to_bytes(8, byteorder='little') + cmd += length.to_bytes(8, byteorder='little') + cmd += ACT_READ.to_bytes(4, byteorder='little') + cmd += option.to_bytes(4, byteorder='little') + + dev.set_media(media) + dev.write(cmd) + ack = dev.read(4) + if int.from_bytes(ack, byteorder="little") != ACK: + print("Receive ACK error") + return + # FIXME: Don't know real length for "read all" + bar = tqdm(total=length, ascii=True) + data = b'' + remain = length + + while remain > 0: + ack = dev.read(4) + # Get the transfer length of next read + xfer_size = int.from_bytes(ack, byteorder="little") + + data += dev.read(xfer_size) + dev.write(xfer_size.to_bytes(4, byteorder='little')) # ack + remain -= xfer_size + bar.update(xfer_size) + try: + with open(out_file_name, "wb") as out_file: + out_file.write(data[0:length]) + except (IOError, OSError) as err: + print(f"Open {out_file_name} failed") + sys.exit(err) + + bar.close() + + +def __attach(dev, ini_data, xusb_data) -> int: + ini_len = len(ini_data) + out = int(ini_len).to_bytes(4, byteorder="little") + out += b'\x00\x00\x03\x28' # Execute address is 0x28030000 + dev.write(out) + dev.write(ini_data) + + in_buf = dev.read(4) + if int.from_bytes(in_buf, byteorder="little") != ini_len: + print("Length error") + return -1 + + in_buf = dev.read(4) + if int.from_bytes(in_buf, byteorder="little") != ACK: + val = int.from_bytes(in_buf, byteorder="little") + print(f"Ack error {val}") + return -1 + + xusb_len = len(xusb_data) + out = int(xusb_len).to_bytes(4, byteorder="little") + out += b'\x00\x00\x00\x87' # Execute address is 0x87000000 + dev.write(out) + for offset in range(0, xusb_len, TRANSFER_SIZE): + xfer_size = TRANSFER_SIZE if offset + TRANSFER_SIZE < xusb_len else xusb_len - offset + + dev.write(xusb_data[offset: offset + xfer_size]) + if offset + xfer_size != xusb_len: # Ignore the ack of last packet + ack = dev.read(4) + if int.from_bytes(ack, byteorder="little") != xfer_size: + _ack = int.from_bytes(ack, byteorder="little") + print(f"Ack size error {_ack} {xfer_size}") + return -1 + + return 0 + + +def __get_info(dev, data) -> int: + try: + info = dev.get_info(data) + except usb.core.USBError as err: + sys.exit(err) + + _info_struct = namedtuple('_info_struct', + 'page_per_blk page_size blk_cnt bad_clk_cnt oob_size usr_cfg0 spi_id usr_cfg1 quad_cmd \ + read_sts_cmd write_sts_cmd sts_val dummy_byte blk rsv use_cfg2 snand_id snand_page_size \ + snand_oob snand_quad_cmd snand_read_sts_cmd snand_write_sts_cmd snand_sts_val \ + snand_dummy_byte snand_blk_cnt snand_page_per_blk') + info_struct = _info_struct._make(unpack(' None: + global mp_mode + + init_location = "missing" + if os.path.exists(ini_file_name): # default use the init file in current directory + init_location = ini_file_name + else: + if platform.system() == 'Windows': + if os.path.exists(WINDOWS_PATH + "ddrimg\\" + ini_file_name): + init_location = WINDOWS_PATH + "ddrimg\\" + ini_file_name + elif platform.system() == 'Linux': + if os.path.exists(LINUX_PATH + "ddrimg/" + ini_file_name): + init_location = LINUX_PATH + "ddrimg/" + ini_file_name + + if init_location == "missing": + print(f"Cannot find {ini_file_name}") + sys.exit(3) + try: + with open(init_location, "rb") as ini_file: + ini_data = ini_file.read() + except (IOError, OSError) as err: + print(f"Open {ini_file_name} failed") + sys.exit(err) + xusb_location = "missing" + if os.path.exists("xusb.bin"): # default use the xusb.bin in current directory + xusb_location = "xusb.bin" + else: + if platform.system() == 'Windows': + if os.path.exists(WINDOWS_PATH + "xusb.bin"): + xusb_location = WINDOWS_PATH + "xusb.bin" + elif platform.system() == 'Linux': + if os.path.exists(LINUX_PATH + "xusb.bin"): + xusb_location = LINUX_PATH + "xusb.bin" + if xusb_location == "missing": + print("Cannot find xusb.bin") + sys.exit(3) + + try: + with open(xusb_location, "rb") as xusb_file: + xusb_data = xusb_file.read() + except (IOError, OSError) as err: + print("Open xusb.bin failed") + sys.exit(err) + + # devices = XUsbComList(attach_all=mp_mode).get_dev() + _XUsbComList = XUsbComList(attach_all=mp_mode) + devices = _XUsbComList.get_dev() + + if len(devices) == 0: + print("Device not found") + sys.exit(2) + + with ThreadPoolExecutor(max_workers=8) as executor: + futures = [executor.submit(__attach, dev, ini_data, xusb_data) for dev in devices] + success = 0 + failed = 0 + for future in as_completed(futures, timeout=2): + if future.result() == 0: + success += 1 + else: + failed += 1 + + print(f"Successfully attached {success} device(s)") + if failed > 0: + print(f"Failed to attach {failed} device(s)") + if success == 0: + return + + time.sleep(1) + + # devices = XUsbComList(attach_all=mp_mode).get_dev() + _XUsbComListNew = XUsbComList(attach_all=mp_mode) + devices = _XUsbComListNew.get_dev() + + data = bytearray(76) + # assign option file to set media info + if option == OPT_SETINFO: + try: + with open("info.json", "r") as json_file: + try: + d = json.load(json_file) + except json.decoder.JSONDecodeError as err: + print(f"{json_file} parsing error") + sys.exit(err) + except (IOError, OSError) as err: + print("Open info.json failed") + sys.exit(err) + # now generate info from info.json + for key in d.keys(): + if key == 'spinand': + data[48] = 1 + for sub_key in d['spinand'].keys(): + if sub_key == 'pagesize': + data[56:58] = int(d['spinand']['pagesize'], 0).to_bytes(2, byteorder="little") + elif sub_key == 'sparearea': + data[58:60] = int(d['spinand']['sparearea'], 0).to_bytes(2, byteorder="little") + elif sub_key == 'quadread': + data[60:61] = int(d['spinand']['quadread'], 0).to_bytes(1, byteorder="little") + elif sub_key == 'readsts': + data[61:62] = int(d['spinand']['readsts'], 0).to_bytes(1, byteorder="little") + elif sub_key == 'writests': + data[62:63] = int(d['spinand']['writests'], 0).to_bytes(1, byteorder="little") + elif sub_key == 'stsvalue': + data[63:64] = int(d['spinand']['stsvalue'], 0).to_bytes(1, byteorder="little") + elif sub_key == 'dummy': + data[64:68] = int(d['spinand']['dummy'], 0).to_bytes(4, byteorder="little") + elif sub_key == 'blkcnt': + data[68:72] = int(d['spinand']['blkcnt'], 0).to_bytes(4, byteorder="little") + elif sub_key == 'pageperblk': + data[72:76] = int(d['spinand']['pageperblk'], 0).to_bytes(4, byteorder="little") + elif key == 'spinor': + data[28] = 1 + for sub_key in d['spinor'].keys(): + if sub_key == 'quadread': + data[32:33] = int(d['spinor']['quadread'], 0).to_bytes(1, byteorder="little") + elif sub_key == 'readsts': + data[33:34] = int(d['spinor']['readsts'], 0).to_bytes(1, byteorder="little") + elif sub_key == 'writests': + data[34:35] = int(d['spinor']['writests'], 0).to_bytes(1, byteorder="little") + elif sub_key == 'stsvalue': + data[35:36] = int(d['spinor']['stsvalue'], 0).to_bytes(1, byteorder="little") + elif sub_key == 'dummy': + data[36:40] = int(d['spinor']['dummy'], 0).to_bytes(4, byteorder="little") + elif key == 'nand': + data[20] = 1 + for sub_key in d['nand'].keys(): + if sub_key == 'blkcnt': + data[8:12] = int(d['nand']['blkcnt'], 0).to_bytes(4, byteorder="little") + elif sub_key == 'pageperblk': + data[0:4] = int(d['nand']['pageperblk'], 0).to_bytes(4, byteorder="little") + if len(devices) == 0: + print("Device not found") + sys.exit(2) + with ThreadPoolExecutor(max_workers=8) as executor: + futures = [executor.submit(__get_info, dev, data) for dev in devices] + + success = 0 + failed = 0 + for future in as_completed(futures, timeout=2): + if future.result() == 0: + success += 1 + else: + failed += 1 + + print(f"Successfully get info from {success} device(s)") + + +def do_unpack(pack_file_name) -> None: + + now = datetime.now() + pack_image = UnpackImage(pack_file_name) + image_cnt = pack_image.img_count() + + try: + os.mkdir(now.strftime("%m%d-%H%M%S%f")) + except (IOError, OSError) as err: + sys.exit(err) + + for i in range(image_cnt): + img_length, _, _ = pack_image.img_attr(i) + try: + with open(now.strftime("%m%d-%H%M%S%f") + "/img" + str(i) + ".bin", "wb") as img_file: + img_file.write(pack_image.img_content(i, 0, img_length)) + except (IOError, OSError) as err: + print("Create output image file failed") + sys.exit(err) + try: + os.unlink("unpack") + except (IOError, OSError): + pass + try: + os.symlink(now.strftime("%m%d-%H%M%S%f"), "unpack") + except (IOError, OSError): + print("Create symbolic folder unpack failed") + print("Unpack images to directory {} complete".format(now.strftime("%m%d-%H%M%S%f"))) + + +def do_stuff(cfg_file) -> None: + now = datetime.now() + + try: + with open(cfg_file, "r") as json_file: + try: + d = json.load(json_file) + except json.decoder.JSONDecodeError as err: + print(f"{cfg_file} parsing error") + sys.exit(err) + except (IOError, OSError) as err: + print(f"Open {cfg_file} failed") + sys.exit(err) + + try: + os.mkdir(now.strftime("%m%d-%H%M%S%f")) + pack_file = open(now.strftime("%m%d-%H%M%S%f") + "/pack.bin", "wb") + except (IOError, OSError) as err: + sys.exit(err) + + offset = 0 + out = bytearray() + + # Start stuffing image + for img in d["image"]: + try: + with open(img["file"], "rb") as img_file: + data = img_file.read() + except (IOError, OSError) as err: + print(f"Open {img_file} failed") + shutil.rmtree(now.strftime("%m%d-%H%M%S%f")) + sys.exit(err) + if int(img["offset"], 0) < offset: + print(f"Please place the files in {cfg_file} based on the ascending offset") + sys.exit(4) + elif int(img["offset"], 0) > offset: + out += b'\xFF' * (int(img["offset"], 0) - offset) + offset = int(img["offset"], 0) + out += data + offset += len(data) + pack_file.write(out) + pack_file.close() + try: + os.unlink("pack") + except (IOError, OSError): + pass + try: + os.symlink(now.strftime("%m%d-%H%M%S%f"), "pack") + except (IOError, OSError): + print("Create symbolic folder pack failed") + print("Generate pack file in directory {} complete".format(now.strftime("%m%d-%H%M%S%f"))) + + +def do_pack(cfg_file) -> None: + now = datetime.now() + + try: + with open(cfg_file, "r") as json_file: + try: + d = json.load(json_file) + except json.decoder.JSONDecodeError as err: + print(f"{cfg_file} parsing error") + sys.exit(err) + except (IOError, OSError) as err: + print(f"Open {cfg_file} failed") + sys.exit(err) + + try: + os.mkdir(now.strftime("%m%d-%H%M%S%f")) + pack_file = open(now.strftime("%m%d-%H%M%S%f") + "/pack.bin", "wb") + except (IOError, OSError) as err: + sys.exit(err) + + out = bytearray(b'\x20\x54\x56\x4e' + b'\xFF' * 12) # NVT + CRC32 + image count + 4 reserved bytes + + # Start packing image + img_cnt = 0 + for img in d["image"]: + try: + with open(img["file"], "rb") as img_file: + data = img_file.read() + except (IOError, OSError) as err: + print(f"Open {img_file} failed") + shutil.rmtree(now.strftime("%m%d-%H%M%S%f")) + sys.exit(err) + + img_cnt = img_cnt + 1 + + img_len = len(data) + out += img_len.to_bytes(8, byteorder="little") + try: + out += int(img["offset"], 0).to_bytes(8, byteorder="little") + except ValueError as err: + shutil.rmtree(now.strftime("%m%d-%H%M%S%f")) + sys.exit(err) + out += img["type"].to_bytes(4, byteorder="little") + out += b'\xFF' * 4 + out += data + # Always put image start @ 16 byte boundary + pad = 16 - (img_len + 8) & 0xF + if pad != 16: + out += b'\xFF' * pad + + # Fill image count + out[8:12] = img_cnt.to_bytes(4, byteorder="little") + + # Fill CRC field + crc32_func = crcmod.predefined.mkCrcFun('crc-32') + checksum = crc32_func(out[8:]) + out[4:8] = checksum.to_bytes(4, byteorder="little") + + pack_file.write(out) + pack_file.close() + try: + os.unlink("pack") + except (IOError, OSError): + pass + try: + os.symlink(now.strftime("%m%d-%H%M%S%f"), "pack") + except (IOError, OSError): + print("Create symbolic folder pack failed") + print("Generate pack file in directory {} complete".format(now.strftime("%m%d-%H%M%S%f"))) + + +def do_showhdr(cfg_file) -> None: + try: + header_file = open(cfg_file, "br") + except (IOError, OSError) as err: + print(f"Open {cfg_file} failed") + sys.exit(err) + + if unpack(' None: + now = datetime.now() + + try: + with open(cfg_file, "r") as json_file: + try: + d = json.load(json_file) + except json.decoder.JSONDecodeError as err: + print(f"{cfg_file} parsing error") + sys.exit(err) + except (IOError, OSError) as err: + print(f"Open {cfg_file} failed") + sys.exit(err) + try: + os.mkdir(now.strftime("%m%d-%H%M%S%f")) + except (IOError, OSError) as err: + print("Create output directory failed") + sys.exit(err) + + if "header" in d: + out = bytearray(b'\x20\x54\x56\x4e' + b'\x00' * 8) # NVT + CRC + LEN + try: + out += int(d["header"]["version"], 0).to_bytes(4, byteorder="little") + # Fill SPI flash info + out += int(d["header"]["spiinfo"]["pagesize"], 0).to_bytes(2, byteorder="little") + out += int(d["header"]["spiinfo"]["sparearea"], 0).to_bytes(2, byteorder="little") + out += int(d["header"]["spiinfo"]["pageperblk"], 0).to_bytes(2, byteorder="little") + out += int(d["header"]["spiinfo"]["quadread"], 0).to_bytes(1, byteorder="little") + out += int(d["header"]["spiinfo"]["readsts"], 0).to_bytes(1, byteorder="little") + out += int(d["header"]["spiinfo"]["writests"], 0).to_bytes(1, byteorder="little") + out += int(d["header"]["spiinfo"]["stsvalue"], 0).to_bytes(1, byteorder="little") + out += int(d["header"]["spiinfo"]["dummy1"], 0).to_bytes(1, byteorder="little") + out += int(d["header"]["spiinfo"]["dummy2"], 0).to_bytes(1, byteorder="little") + out += int(d["header"]["spiinfo"]["suspintvl"], 0).to_bytes(1, byteorder="little") + out += b'\xFF' * 3 # 3 reserved bytes + out += int(d["header"]["entrypoint"], 0).to_bytes(4, byteorder="little") + except ValueError as err: + shutil.rmtree(now.strftime("%m%d-%H%M%S%f")) + sys.exit(err) + + out += b'\xFF' * 4 # Reserve 4 bytes for image count + + # Generate key file iff secure boot is enabled + if d["header"]["secureboot"] == 'yes': + + try: + key_file = open(now.strftime("%m%d-%H%M%S%f") + "/header_key.txt", "w+") + except (IOError, OSError) as err: + print("Create key file failed") + shutil.rmtree(now.strftime("%m%d-%H%M%S%f")) + sys.exit(err) + + if "aeskey" in d["header"]: + try: + aeskey = bytes.fromhex(d["header"]["aeskey"]) + except ValueError as err: + sys.exit(err) + else: + aeskey = ''.join(['%x' % random.randrange(16) for _ in range(0, 64)]) + aeskey = binascii.unhexlify(bytes(aeskey, 'utf-8')) + key_file.write("AES key:\n" + str.upper(aeskey.hex())) + + if "ecdsakey" in d["header"]: + try: + sk = ecdsa.SigningKey.from_string(bytes.fromhex(d["header"]["ecdsakey"]), + curve=ecdsa.NIST256p, + hashfunc=hashlib.sha256) + except ValueError as err: + sys.exit(err) + else: + sk = ecdsa.SigningKey.generate(curve=ecdsa.NIST256p, hashfunc=hashlib.sha256) + key_file.write("\nECDSA private key:\n" + str.upper(sk.to_string().hex())) + + vk = sk.verifying_key + key_file.write("\nECDSA public key:\n" + format(vk.pubkey.point.x(), 'X') + + "\n" + format(vk.pubkey.point.y(), 'X') + "\n") + + key_file.close() + + img_cnt = len(d["header"]["image"]) + if img_cnt > MAX_HEADER_IMG: + print("Can process 4 images in header max") + shutil.rmtree(now.strftime("%m%d-%H%M%S%f")) + sys.exit(2) + + # Fill image information + for i in range(img_cnt): + img = d["header"]["image"][i] + try: + with open(img["file"], "rb") as img_file: + data = img_file.read() + except (IOError, OSError) as err: + print("Open image file failed") + shutil.rmtree(now.strftime("%m%d-%H%M%S%f")) + sys.exit(err) + try: + out += int(img["offset"], 0).to_bytes(4, byteorder="little") + out += int(img["loadaddr"], 0).to_bytes(4, byteorder="little") + out += os.path.getsize(img["file"]).to_bytes(4, byteorder="little") + out += int(img["type"]).to_bytes(4, byteorder="little") + except ValueError as err: + shutil.rmtree(now.strftime("%m%d-%H%M%S%f")) + sys.exit(err) + + if d["header"]["secureboot"] == 'yes': + + # Use CFB and each image is process independently, so call new() for every image + aes_enc = AES.new(aeskey, AES.MODE_CFB, b'\x00' * 16, segment_size=128) + data_out = aes_enc.encrypt(data) + # R & S + out += sk.sign(data_out) + + # Write encrypt image + try: + with open(now.strftime("%m%d-%H%M%S%f") + '/enc_' + + os.path.basename(img["file"]), "wb") as enc_file: + enc_file.write(data_out) + except (IOError, OSError) as err: + print("Create encrypt file failed") + shutil.rmtree(now.strftime("%m%d-%H%M%S%f")) + sys.exit(err) + + else: + out += b'\xFF' * 64 # Just pack 0xFF if secure boot is disabled + + # Fill header length + out[8:12] = int(len(out) - 8).to_bytes(4, byteorder="little") + # Fill image count + out[36:40] = img_cnt.to_bytes(4, byteorder="little") + # Fill header checksum + crc32_func = crcmod.predefined.mkCrcFun('crc-32') + out[4:8] = crc32_func(out[8:]).to_bytes(4, byteorder="little") + + try: + with open(now.strftime("%m%d-%H%M%S%f") + "/header.bin", "wb") as header_file: + header_file.write(out) + except (IOError, OSError) as err: + print("Create header file failed") + sys.exit(err) + + if "env" in d: + try: + with open(now.strftime("%m%d-%H%M%S%f") + "/uboot-env.bin", "wb") as out_file: + out_file.write(conv_env(d["env"]["file"], int(d["env"]["blksize"], 0))) + except (IOError, OSError, ValueError) as err: + print("Create header file failed") + sys.exit(err) + # Misc images + if "data" in d: + try: + key_file = open(now.strftime("%m%d-%H%M%S%f") + "/data_key.txt", "w+") + except (IOError, OSError) as err: + print("Create key file failed") + shutil.rmtree(now.strftime("%m%d-%H%M%S%f")) + sys.exit(err) + + if "aeskey" in d["data"]: + try: + aeskey = bytes.fromhex(d["data"]["aeskey"]) + except ValueError as err: + sys.exit(err) + else: + aeskey = ''.join(['%x' % random.randrange(16) for _ in range(0, 64)]) + aeskey = binascii.unhexlify(bytes(aeskey, 'utf-8')) + key_file.write("AES key:\n" + str.upper(aeskey.hex())) + + if "ecdsakey" in d["data"]: + try: + sk = ecdsa.SigningKey.from_string(bytes.fromhex(d["data"]["ecdsakey"]), + curve=ecdsa.NIST256p, + hashfunc=hashlib.sha256) + except ValueError as err: + sys.exit(err) + else: + sk = ecdsa.SigningKey.generate(curve=ecdsa.NIST256p, hashfunc=hashlib.sha256) + key_file.write("\nECDSA private key:\n" + str.upper(sk.to_string().hex())) + + vk = sk.verifying_key + key_file.write("\nECDSA public key:\n" + format(vk.pubkey.point.x(), 'X') + + "\n" + format(vk.pubkey.point.y(), 'X') + "\n") + key_file.close() + + for img in d["data"]["image"]: + try: + with open(img["file"], "rb") as img_file: + data = img_file.read() + except (IOError, OSError) as err: + print(f"Open {img_file} failed") + shutil.rmtree(now.strftime("%m%d-%H%M%S%f")) + sys.exit(err) + + aes_enc = AES.new(aeskey, AES.MODE_CFB, b'\x00' * 16, segment_size=128) + data_out = aes_enc.encrypt(data) + signature = sk.sign(data_out) + try: + if option is OPT_CONCAT: + # Append the R & S at the end of signed image instead of writing to a separate file. + # The signed image could be used in deployed mode + data_out += signature + else: + with open(now.strftime("%m%d-%H%M%S%f") + '/sig_' + img["file"], "wb") as sig_file: + sig_file.write(signature) # R & S + + with open(now.strftime("%m%d-%H%M%S%f") + '/enc_' + img["file"], "wb") as enc_file: + enc_file.write(data_out) + + except (IOError, OSError) as err: + print("Create encrypt/signature file failed") + shutil.rmtree(now.strftime("%m%d-%H%M%S%f")) + sys.exit(err) + try: + os.unlink("conv") + except (IOError, OSError): + pass + try: + os.symlink(now.strftime("%m%d-%H%M%S%f"), "conv") + except (IOError, OSError): + print("Create symbolic folder conv failed") + print("Generate output image(s) in directory {} complete".format(now.strftime("%m%d-%H%M%S%f"))) + + +def __msc(dev, media, reserve, option) -> int: + + cmd = reserve.to_bytes(8, byteorder='little') + cmd += b'\x00' * 8 + cmd += ACT_MSC.to_bytes(4, byteorder='little') + cmd += option.to_bytes(4, byteorder='little') + + dev.set_media(media) + dev.write(cmd) + ack = dev.read(4) + if int.from_bytes(ack, byteorder="little") != ACK: + print("Receive ACK error") + return -1 + return 0 + + +def do_msc(media, reserve, option=OPT_NONE) -> None: + global mp_mode + + # devices = XUsbComList(attach_all=mp_mode).get_dev() + _XUsbComList = XUsbComList(attach_all=mp_mode) + devices = _XUsbComList.get_dev() + + if len(devices) == 0: + print("Device not found") + sys.exit(2) + + with ThreadPoolExecutor(max_workers=8) as executor: + futures = [executor.submit(__msc, dev, media, reserve, option) for dev in devices] + success = 0 + failed = 0 + for future in as_completed(futures): + if future.result() == 0: + success += 1 + else: + failed += 1 + + print("Successfully {} {} MSC device(s)".format("set" if option == "OPT_NONE" else "eject", success)) + if failed > 0: + print("Failed to {} {} MSC device(s)".format("set" if option == "OPT_NONE" else "eject", failed)) + + +def get_media(media) -> int: + media = str.upper(media) + return { + 'DDR': DEV_DDR_SRAM, + 'SRAM': DEV_DDR_SRAM, + 'SD': DEV_SD_EMMC, + 'EMMC': DEV_SD_EMMC, + 'NAND': DEV_NAND, + 'SPINAND': DEV_SPINAND, + 'SPINOR': DEV_SPINOR, + 'OTP': DEV_OTP, + 'USBH': DEV_USBH + }.get(media, DEV_UNKNOWN) + + +def get_option(option) -> int: + option = str.upper(option) + return { + 'SCRUB': OPT_SCRUB, + 'WITHBAD': OPT_WITHBAD, + 'VERIFY': OPT_VERIFY, + 'EXECUTE': OPT_EXECUTE, + 'UNPACK': OPT_UNPACK, + 'RAW': OPT_RAW, + 'EJECT': OPT_EJECT, + 'STUFF': OPT_STUFF, + 'SETINFO': OPT_SETINFO, + 'CONCAT': OPT_CONCAT, + 'SHOWHDR': OPT_SHOWHDR + }.get(option, OPT_UNKNOWN) + + +def get_type(img_type) -> int: + img_type = str.upper(img_type) + return { + 'TFA': IMG_TFA, + 'UBOOT': IMG_UBOOT, + 'LINUX': IMG_LINUX, + 'DDR': IMG_DDR, + 'TEE': IMG_TEE + }.get(img_type, IMG_DATA) + +def get_otpblock(num) -> int: + num = str.upper(num) + return { + 'OTP1': OPT_OTPBLK1, + 'OTP2': OPT_OTPBLK2, + 'OTP3': OPT_OTPBLK3, + 'OTP4': OPT_OTPBLK4, + 'OTP5': OPT_OTPBLK5, + 'OTP6': OPT_OTPBLK6, + 'OTP7': OPT_OTPBLK7, + 'KEY0': OPT_OTPKEY0+OPT_OTPKEY, + 'KEY1': OPT_OTPKEY1+OPT_OTPKEY, + 'KEY2': OPT_OTPKEY2+OPT_OTPKEY, + 'KEY3': OPT_OTPKEY3+OPT_OTPKEY, + 'KEY4': OPT_OTPKEY4+OPT_OTPKEY, + 'KEY5': OPT_OTPKEY5+OPT_OTPKEY + }.get(num, OPT_UNKNOWN) + + +def main(): + parser = argparse.ArgumentParser() + + parser.add_argument("CONFIG", nargs='?', help="Config file", type=str, default='') + parser.add_argument("-a", "--attach", action='store_true', help="Attach to MA35D1") + parser.add_argument("-o", "--option", nargs='+', help="Option flag") + parser.add_argument("-t", "--type", nargs='+', help="Type flag") + group = parser.add_mutually_exclusive_group() + group.add_argument("-c", "--convert", action='store_true', help="Convert images") + group.add_argument("-p", "--pack", action='store_true', help="Generate pack file") + group.add_argument("-v", "--version", action='store_true', help="Show version number") + group.add_argument("-r", "--read", nargs='+', help="Read flash") + group.add_argument("-w", "--write", nargs='+', help="Write flash") + group.add_argument("-e", "--erase", nargs='+', help="Erase flash") + group.add_argument("-s", "--storage", nargs='+', help="Export eMMC/SD as Mass Storage Class") + + if len(sys.argv) == 1: + parser.print_help() + sys.exit(0) + + args = parser.parse_args() + + if args.option: + option = get_option(args.option[0]) + else: + option = OPT_NONE + + if option is OPT_UNKNOWN: + print("Unknown option: " + args.option[0]) + sys.exit(0) + # if args.type: + # img_type = get_type(args.type[0]) + # else: + # img_type = IMG_DATA + + cfg_file = args.CONFIG + + if args.attach: + if not cfg_file: + print("Please assign a DDR ini file") + sys.exit(0) + do_attach(cfg_file, option) + + if args.convert: + if cfg_file == '': + print("No config file assigned") + sys.exit(0) + else: + if option == OPT_SHOWHDR: + do_showhdr(cfg_file) + else: + do_convert(cfg_file, option) + elif args.pack: + if cfg_file == '': + print("No config file assigned") + sys.exit(0) + else: + if option == OPT_UNPACK: + do_unpack(cfg_file) + elif option == OPT_STUFF: + do_stuff(cfg_file) + else: + do_pack(cfg_file) + elif args.read: + # -r spinor all out.bin + # -r nand 0x1000 0x100 out.bin + # -r otp all out.bin (block1 ~ block7) + # -r otp blockno 0x4 out.bin + arg_count = len(args.read) + if arg_count < 3: + print("At lease take 3 arguments") + sys.exit(0) + media = get_media(args.read[0]) + + try: + if media == DEV_UNKNOWN: + raise ValueError(f"Cannot support read {str.upper(args.read[0])}") + if arg_count == 3 and str.upper(args.read[1]) != 'ALL': + raise ValueError("Unknown arguments") + except ValueError as err: + sys.exit(err) + + if str.upper(args.read[1]) == 'ALL': + if media == DEV_OTP: + option |= 0x3fff00 + do_otp_read(media, 0, args.read[2], 352, option) + else: + do_img_read(media, 0, args.read[2], 0, option) + else: + try: + if media == DEV_OTP: + option = get_otpblock(args.read[1]) | option + else: + start = int(args.read[1], 0) + length = int(args.read[2], 0) + except ValueError as err: + print("Wrong start/length value") + sys.exit(err) + + if media == DEV_OTP: + do_otp_read(media, 0, args.read[3], length, option) + else: + do_img_read(media, start, args.read[3], length, option) + + elif args.write: + # -w spinor 0x1000 image.bin + # -w otp otp.json + # -w nand pack.img + arg_count = len(args.write) + if arg_count < 2: + print("At lease take 2 arguments") + sys.exit(0) + media = get_media(args.write[0]) + + try: + if media == DEV_UNKNOWN: + raise ValueError(f"Unknown storage media {str.upper(args.write[0])}") + if option == OPT_VERIFY and media == DEV_OTP: + raise ValueError(f"Do not support verify option on {str.upper(args.write[0])}") + if option == OPT_EXECUTE and media != DEV_DDR_SRAM: + raise ValueError(f"Do not support execution on {str.upper(args.write[0])}") + if option == OPT_RAW and media != DEV_NAND: + raise ValueError(f"Do not support raw write on {str.upper(args.write[0])}") + except ValueError as err: + sys.exit(err) + + if arg_count == 2: + if media == DEV_OTP: + do_otp_program(args.write[1]) + else: + do_pack_program(media, args.write[1], option) + else: + try: + start = int(args.write[1], 0) + except ValueError as err: + print("Wrong start value") + sys.exit(err) + do_img_program(media, start, args.write[2], option) + + elif args.erase: + # -e spinor all + # -e nand 0x100000 0x10000 -o withbad + # -e otp blockno + arg_count = len(args.erase) + if arg_count < 2: + print("At lease take 2 arguments") + sys.exit(0) + media = get_media(args.erase[0]) + + try: + if media in [DEV_DDR_SRAM, DEV_SD_EMMC, DEV_UNKNOWN]: + raise ValueError(f"{str.upper(args.erase[0])} does not support erase") + if arg_count == 2 and str.upper(args.erase[1]) != 'ALL' and media != DEV_OTP: + raise ValueError("Unknown arguments") + if str.upper(args.erase[1]) == 'ALL' and media == DEV_OTP: + raise ValueError("Wrong arguments") + except ValueError as err: + sys.exit(err) + + if media == DEV_OTP: + option = get_otpblock(args.erase[1]) + try: + # only can erase block 1, 3, 4 + if option == OPT_OTPBLK2: + raise ValueError(f"Error block 2, only erase block 1, 3, 4") + if option == OPT_OTPBLK5: + raise ValueError(f"Error block 5, only erase block 1, 3, 4") + if option == OPT_OTPBLK6: + raise ValueError(f"Error block 6, only erase block 1, 3, 4") + if option == OPT_OTPBLK7: + raise ValueError(f"Error block 7, only erase block 1, 3, 4") + if option == OPT_UNKNOWN: + raise ValueError(f"Error key number") + except ValueError as err: + sys.exit(err) + do_otp_erase(option) + else: + if str.upper(args.erase[1]) == 'ALL': + do_img_erase(media, 0, 0, option) + else: + try: + start = int(args.erase[1], 0) + length = int(args.erase[2], 0) + except ValueError as err: + print("Wrong start/length value") + sys.exit(err) + do_img_erase(media, start, length, option) + + elif args.storage: + # -s emmc 0x800000 + # -s emmc -o remove + arg_count = len(args.erase) + if arg_count != 2 and option != OPT_EJECT: + print("Takes 2 arguments. Storage device and reserved size") + sys.exit(0) + media = get_media(args.storage[0]) + try: + if media not in [DEV_SD_EMMC]: + raise ValueError("Only support eMMC/SD") + if option != OPT_NONE and option != OPT_EJECT: + raise ValueError("Unsupported option") + except ValueError as err: + sys.exit(err) + + if option == OPT_EJECT: + do_msc(media, 0, OPT_EJECT) + else: + try: + reserve = int(args.storage[1], 0) + except ValueError as err: + print("Wrong reserve size") + sys.exit(err) + do_msc(media, reserve) + elif args.version: + print('NuWriter ' + __version__) + print(__copyright__) + + +# Here goes the main function +if __name__ == "__main__": + #os.system("start cmd.exe") #Call do it. Will open cmd window in each process + main() diff --git a/bsp/nuvoton/numaker-hmi-ma35d1/nuwriter_scripts/nuwriter_ddr_download_and_run.bat b/bsp/nuvoton/numaker-hmi-ma35d1/nuwriter_scripts/nuwriter_ddr_download_and_run.bat new file mode 100644 index 0000000000..7eecc00fab --- /dev/null +++ b/bsp/nuvoton/numaker-hmi-ma35d1/nuwriter_scripts/nuwriter_ddr_download_and_run.bat @@ -0,0 +1,8 @@ +:forever_develop +py -3 nuwriter.py -a ddrimg\enc_ddr3_winbond_256mb.bin +IF %ERRORLEVEL% EQU 0 ( + py -3 nuwriter.py -o execute -w ddr 0x80400000 ..\rtthread.bin +) +pause + +goto :forever_develop \ No newline at end of file diff --git a/bsp/nuvoton/numaker-hmi-ma35d1/nuwriter_scripts/nuwriter_leave_ibr_download_and_run.bat b/bsp/nuvoton/numaker-hmi-ma35d1/nuwriter_scripts/nuwriter_leave_ibr_download_and_run.bat new file mode 100644 index 0000000000..f60706d163 --- /dev/null +++ b/bsp/nuvoton/numaker-hmi-ma35d1/nuwriter_scripts/nuwriter_leave_ibr_download_and_run.bat @@ -0,0 +1,8 @@ +:forever_develop +py -3 nuwriter.py -a ddrimg\enc_ddr3_winbond_256mb.bin +IF %ERRORLEVEL% EQU 0 ( + py -3 nuwriter.py -o execute -w ddr 0x28000000 ..\preload\leave_ibr.bin +) +pause + +goto :forever_develop \ No newline at end of file diff --git a/bsp/nuvoton/numaker-hmi-ma35d1/nuwriter_scripts/nuwriter_leave_ibr_sd_pack.bat b/bsp/nuvoton/numaker-hmi-ma35d1/nuwriter_scripts/nuwriter_leave_ibr_sd_pack.bat new file mode 100644 index 0000000000..c1deb2296f --- /dev/null +++ b/bsp/nuvoton/numaker-hmi-ma35d1/nuwriter_scripts/nuwriter_leave_ibr_sd_pack.bat @@ -0,0 +1,5 @@ +py -3 nuwriter.py -c header-sram-leave_ibr.json +IF %ERRORLEVEL% EQU 0 ( + py -3 nuwriter.py -p pack-sd-leave_ibr.json -o stuff +) +pause \ No newline at end of file diff --git a/bsp/nuvoton/numaker-hmi-ma35d1/nuwriter_scripts/nuwriter_nand_programming.bat b/bsp/nuvoton/numaker-hmi-ma35d1/nuwriter_scripts/nuwriter_nand_programming.bat new file mode 100644 index 0000000000..51fa333d3a --- /dev/null +++ b/bsp/nuvoton/numaker-hmi-ma35d1/nuwriter_scripts/nuwriter_nand_programming.bat @@ -0,0 +1,7 @@ +py -3 nuwriter.py -c header-nand.json +py -3 nuwriter.py -p pack-nand.json + +py -3 nuwriter.py -a ddrimg\enc_ddr3_winbond_256mb.bin +IF %ERRORLEVEL% EQU 0 ( + py -3 nuwriter.py -w nand pack/pack.bin +) \ No newline at end of file diff --git a/bsp/nuvoton/numaker-hmi-ma35d1/nuwriter_scripts/nuwriter_sd_programming.bat b/bsp/nuvoton/numaker-hmi-ma35d1/nuwriter_scripts/nuwriter_sd_programming.bat new file mode 100644 index 0000000000..01f13e1b33 --- /dev/null +++ b/bsp/nuvoton/numaker-hmi-ma35d1/nuwriter_scripts/nuwriter_sd_programming.bat @@ -0,0 +1,8 @@ +py -3 nuwriter.py -c header-sd.json +py -3 nuwriter.py -p pack-sd.json + +py -3 nuwriter.py -a ddrimg\enc_ddr3_winbond_256mb.bin +IF %ERRORLEVEL% EQU 0 ( + py -3 nuwriter.py -w sd pack/pack.bin +) +PAUSE \ No newline at end of file diff --git a/bsp/nuvoton/numaker-hmi-ma35d1/nuwriter_scripts/nuwriter_spinand_programming.bat b/bsp/nuvoton/numaker-hmi-ma35d1/nuwriter_scripts/nuwriter_spinand_programming.bat new file mode 100644 index 0000000000..2325de7aef --- /dev/null +++ b/bsp/nuvoton/numaker-hmi-ma35d1/nuwriter_scripts/nuwriter_spinand_programming.bat @@ -0,0 +1,7 @@ +py -3 nuwriter.py -c header-nand.json +py -3 nuwriter.py -p pack-nand.json + +py -3 nuwriter.py -a ddrimg\enc_ddr3_winbond_256mb.bin +IF %ERRORLEVEL% EQU 0 ( + py -3 nuwriter.py -w spinand pack/pack.bin +) \ No newline at end of file diff --git a/bsp/nuvoton/numaker-hmi-ma35d1/nuwriter_scripts/pack-nand.json b/bsp/nuvoton/numaker-hmi-ma35d1/nuwriter_scripts/pack-nand.json new file mode 100644 index 0000000000..12eae70b7e --- /dev/null +++ b/bsp/nuvoton/numaker-hmi-ma35d1/nuwriter_scripts/pack-nand.json @@ -0,0 +1,21 @@ +{ + "image": + [ + { + "offset": "0x0", + "file": "conv/header.bin", + "type": 1 + }, + + { + "offset": "0x20000", + "file": "ddrimg/enc_ddr3_winbond_256mb.bin", + "type": 0 + }, + { + "offset": "0x80000", + "file": "../rtthread.bin", + "type": 1 + } + ] +} diff --git a/bsp/nuvoton/numaker-hmi-ma35d1/nuwriter_scripts/pack-sd.json b/bsp/nuvoton/numaker-hmi-ma35d1/nuwriter_scripts/pack-sd.json new file mode 100644 index 0000000000..2f256debc9 --- /dev/null +++ b/bsp/nuvoton/numaker-hmi-ma35d1/nuwriter_scripts/pack-sd.json @@ -0,0 +1,20 @@ +{ + "image": + [ + { + "offset": "0x400", + "file": "conv/header.bin", + "type": 0 + }, + { + "offset": "0x1000", + "file": "ddrimg/enc_ddr3_winbond_256mb.bin", + "type": 0 + }, + { + "offset": "0x4000", + "file": "../rtthread.bin", + "type": 0 + } + ] +} diff --git a/bsp/nuvoton/numaker-hmi-ma35d1/nuwriter_scripts/xusbcom.py b/bsp/nuvoton/numaker-hmi-ma35d1/nuwriter_scripts/xusbcom.py new file mode 100644 index 0000000000..da14584865 --- /dev/null +++ b/bsp/nuvoton/numaker-hmi-ma35d1/nuwriter_scripts/xusbcom.py @@ -0,0 +1,154 @@ +# NOTE: This script is test under Python 3.x + +__copyright__ = "Copyright (C) 2020~2021 Nuvoton Technology Corp. All rights reserved" + +import sys +import usb.core +import usb.util +import json +import typing + +XFER_LEN_CMD = 0x0012 +GET_INFO_CMD = 0x0005 + + +class XUsbCom: + + def __init__(self, _dev): + self.dev = _dev + self.write_addr = 0x1 + self.read_addr = 0x81 + self.attach = False + self.id = 0 + self.info = b'' + + def write(self, data) -> None: + try: + # Vendor command set transfer length + self.dev.ctrl_transfer(0x40, 0xA0, wValue=XFER_LEN_CMD, wIndex=len(data), data_or_wLength='') + # Actual data + self.dev.write(self.write_addr, data, timeout=1000) + except usb.core.USBError as err: + sys.exit(err) + + def read(self, size) -> bytes: + try: + buf = self.dev.read(self.read_addr, size, timeout=1000) + except usb.core.USBError as err: + sys.exit(err) + return buf + + def set_media(self, media) -> None: + try: + # Vendor command set type + self.dev.ctrl_transfer(0x40, 0xB0, wValue=media, wIndex=0, data_or_wLength='') + except usb.core.USBError as err: + sys.exit(err) + return + + def get_info(self, data) -> bytes: + try: + self.dev.ctrl_transfer(0x40, 0xB0, wValue=GET_INFO_CMD, wIndex=0, data_or_wLength='') + self.dev.ctrl_transfer(0x40, 0xA0, wValue=XFER_LEN_CMD, wIndex=76, data_or_wLength='') + self.dev.write(0x01, data, timeout=1000) + self.info = self.dev.read(0x81, 76, timeout=1000) + # not used + self.dev.read(0x81, 4, timeout=5000) + + except usb.core.USBError as err: + sys.exit(err) + return self.info + + def set_id(self, i) -> None: + self.id = i + + def get_id(self) -> int: + return self.id + + @staticmethod + def set_align(nand, spinand) -> None: + # See if we need to overwrite existing json file. + overwrite = False + try: + with open(".config", "r") as json_file: + cfg = json.load(json_file) + for key in cfg.keys(): + if key == 'nand_align': + if nand != int(cfg['nand_align']): + overwrite = True + elif key == 'spinand_align': + if spinand != int(cfg['spinand_align']): + overwrite = True + except (IOError, OSError, json.decoder.JSONDecodeError) as err: + overwrite = True + + if overwrite is True: + try: + with open(".config", "w+") as json_file: + new_key = {'nand_align': nand, 'spinand_align': spinand} + json.dump(new_key, json_file) + except (IOError, OSError) as err: + print("Write .config failed. Please re-attach") + sys.exit(err) + + @staticmethod + def get_align() -> typing.Tuple[int, int]: + try: + with open(".config", "r") as json_file: + cfg = json.load(json_file) + except (IOError, OSError, json.decoder.JSONDecodeError) as err: + print("Open/parsing .config failed. Please re-attach") + sys.exit(err) + nand_align = spinand_align = 0 + for key in cfg.keys(): + if key == 'nand_align': + nand_align = int(cfg['nand_align']) + elif key == 'spinand_align': + spinand_align = int(cfg['spinand_align']) + return nand_align, spinand_align + + +class XUsbComList: + + def __init__(self, attach_all=False): + vid = 0x0416 + pid = 0x5963 + try: + self.devices = list(usb.core.find(idVendor=vid, idProduct=pid, + find_all=True if attach_all is True else False)) + except TypeError: + # list will raise exception if there's no device + self.devices = [] + return + except usb.core.NoBackendError as err: + sys.exit(err) + + if len(self.devices) != 0 and attach_all is False: + # Object type return on attach_all == False is different + self.devices[0] = self.devices[0].device + + for dev in self.devices: + try: + dev.set_configuration() + except (usb.core.USBError, NotImplementedError) as err: + sys.exit(err) + + for i in range(0, len(self.devices)): + self.devices[i] = XUsbCom(self.devices[i]) + self.devices[i].set_id(i) + + def __del__(self): + if len(self.devices) != 0: + for dev in self.devices: + try: + usb.util.dispose_resources(dev.dev) + # dev.dev.reset() + dev = None + #except (usb.core.USBError, NotImplementedError) as err: + except usb.core.USBError as err: + sys.exit(err) + + self.devices = None + + def get_dev(self): + return self.devices diff --git a/bsp/nuvoton/numaker-hmi-ma35d1/preload/Makefile b/bsp/nuvoton/numaker-hmi-ma35d1/preload/Makefile new file mode 100644 index 0000000000..3a2124ab09 --- /dev/null +++ b/bsp/nuvoton/numaker-hmi-ma35d1/preload/Makefile @@ -0,0 +1,68 @@ +TARGET ?= preload + +################################# +# GNU ARM Embedded Toolchain +################################# +CC=aarch64-elf-gcc +CXX=aarch64-elf-g++ +LD=aarch64-elf-ld +AR=aarch64-elf-ar +AS=aarch64-elf-as +CP=aarch64-elf-objcopy +OD=aarch64-elf-objdump +NM=aarch64-elf-nm +SIZE=aarch64-elf-size +A2L=aarch64-elf-addr2line + +################################# +# Working directories +################################# +ROOT = . + +################################# +# Source Files +################################# + +# Search path and source files + +ASMSOURCES = $(notdir $(wildcard *.ASM)) + +INCLUDE_DIRS = -I$(ROOT) + +################################# +# Object List +################################# +OBJECTS= + +################################# +# Target Output Files +################################# +TARGET_O=$(TARGET).o +TARGET_ASM=$(TARGET).asm + +################################# +# Flags +################################# +MCFLAGS=-march=armv8-a +OPTIMIZE = -O2 +AFLAGS=-c $(MCFLAGS) -x assembler-with-cpp -D__ASSEMBLY__ +LDSCRIPT= +LDFLAGS = -nostartfiles -Wl,--gc-sections,-cref,-Map=$(TARGET).map,-cref,-u,_start -T $(TARGET).ld + +################################# +# Build +################################# +all: clean $(TARGET_O) + +$(TARGET_O): + @echo -n "Build $@ ..." + $(CC) -c $(INCLUDE_DIRS) $(AFLAGS) $(ASMSOURCES) $(LDFLAGS) + $(OD) -d $@ > $(TARGET).txt + +################################# +# Recipes +################################# +.PHONY: all clean + +clean: + rm -f $(TARGET_O) \ No newline at end of file diff --git a/bsp/nuvoton/numaker-hmi-ma35d1/preload/Makefile.leave_ibr b/bsp/nuvoton/numaker-hmi-ma35d1/preload/Makefile.leave_ibr new file mode 100644 index 0000000000..d0e949ca1c --- /dev/null +++ b/bsp/nuvoton/numaker-hmi-ma35d1/preload/Makefile.leave_ibr @@ -0,0 +1,69 @@ +TARGET ?= leave_ibr + +################################# +# GNU ARM Embedded Toolchain +################################# +CC=aarch64-elf-gcc +CXX=aarch64-elf-g++ +LD=aarch64-elf-ld +AR=aarch64-elf-ar +AS=aarch64-elf-as +CP=aarch64-elf-objcopy +OD=aarch64-elf-objdump +NM=aarch64-elf-nm +SIZE=aarch64-elf-size +A2L=aarch64-elf-addr2line + +################################# +# Working directories +################################# +ROOT = . + +################################# +# Source Files +################################# + +# Search path and source files for the ST stdperiph library + +ASMSOURCES = $(notdir $(wildcard *.ASM)) + +INCLUDE_DIRS = -I$(ROOT) + +################################# +# Object List +################################# +OBJECTS= + +################################# +# Target Output Files +################################# +TARGET_O=$(TARGET).o +TARGET_ASM=$(TARGET).asm + +################################# +# Flags +################################# +MCFLAGS=-march=armv8-a +OPTIMIZE = -O2 +AFLAGS=-c $(MCFLAGS) -x assembler-with-cpp -D__ASSEMBLY__ +LDSCRIPT= +LDFLAGS = -nostartfiles -Wl,--gc-sections,-cref,-Map=$(TARGET).map,-cref,-u,_start -T $(TARGET).ld + +################################# +# Build +################################# +all: clean $(TARGET_O) + +$(TARGET_O): + @echo -n "Build $@ ..." + $(CC) -c $(INCLUDE_DIRS) $(AFLAGS) $(ASMSOURCES) $(LDFLAGS) + $(OD) -d $@ > $(TARGET).txt + $(CP) -O binary $(TARGET_O) ../nuwriter_scripts/$(TARGET).bin + +################################# +# Recipes +################################# +.PHONY: all clean + +clean: + rm -f $(TARGET_O) \ No newline at end of file diff --git a/bsp/nuvoton/numaker-hmi-ma35d1/preload/SConscript b/bsp/nuvoton/numaker-hmi-ma35d1/preload/SConscript new file mode 100644 index 0000000000..73123b415f --- /dev/null +++ b/bsp/nuvoton/numaker-hmi-ma35d1/preload/SConscript @@ -0,0 +1,14 @@ +# RT-Thread building script for component + +from building import * + + +Import('RTT_ROOT') +from building import * + +cwd = GetCurrentDir() +src = Glob('*.c') + Glob('*.cpp') + Glob('*.S') +CPPPATH = [ cwd ] + +group = DefineGroup('board', src, depend = [''], CPPPATH = CPPPATH) +Return('group') diff --git a/bsp/nuvoton/numaker-hmi-ma35d1/preload/entry_point.S b/bsp/nuvoton/numaker-hmi-ma35d1/preload/entry_point.S new file mode 100644 index 0000000000..210a262d4a --- /dev/null +++ b/bsp/nuvoton/numaker-hmi-ma35d1/preload/entry_point.S @@ -0,0 +1,109 @@ +.section ".text.entrypoint" +.globl system_vectors + +ma35d1_start: + .word 0x10000014 + .word 0x9100029f + .word 0xd539f220 + .word 0xb27a0000 + .word 0xd519f220 + .word 0xd53800a1 + .word 0x92400421 + .word 0xb4000141 + .word 0xd503205f + .word 0xd2800900 + .word 0xf2a808c0 + .word 0xf9400001 + .word 0xf100003f + .word 0x54ffff60 + .word 0x91001000 + .word 0xb9000001 + .word 0x14000012 + .word 0xd2800980 + .word 0xf2a808c0 + .word 0xaa1f03e1 + .word 0xb9000001 + .word 0xd282000a + .word 0xd100054a + .word 0xf100015f + .word 0x54000140 + .word 0xd2800900 + .word 0xf2a808c0 + .word 0xaa1403e1 + .word 0xb9000001 + .word 0xd503209f + .word 0x91001000 + .word 0xb9400002 + .word 0xeb02003f + .word 0x54fffea1 + .word 0xd2836000 + .word 0xf2a016e0 + .word 0xd51be000 + .word 0xd2820000 + .word 0xf2aa1000 + .word 0x52800069 + .word 0xb9000009 + .word 0xb9400409 + .word 0x1200112a + .word 0x340001aa + .word 0x9102000b + .word 0x52800009 + .word 0xb8004569 + .word 0xb8004569 + .word 0x5100054a + .word 0x35ffffca + .word 0xd2840001 + .word 0xf2aa1001 + .word 0x52800060 + .word 0xb9000020 + .word 0x52801000 + .word 0xb9000420 + .word 0xd2820000 + .word 0xf2aa1000 + .word 0xd2840001 + .word 0xf2aa1001 + .word 0x52800009 + .word 0xb9008009 + .word 0x52800029 + .word 0xb9010009 + .word 0x52803ce9 + .word 0xb9000029 + .word 0x52801009 + .word 0xb9000429 + .word 0xd2a00600 + .word 0xd5181040 + .word 0xaa1f03e0 + .word 0xb2630000 + .word 0xb2640000 + .word 0xb2690000 + .word 0xb26a0000 + .word 0xb26c0000 + .word 0xb2750000 + .word 0xd5181000 + .word 0xaa1f03e0 + .word 0xb2770000 + .word 0xb2780000 + .word 0xb2790000 + .word 0xb27b0000 + .word 0xb27c0000 + .word 0xd51e1100 + .word 0xaa1f03e0 + .word 0xd2800060 + .word 0xb2780000 + .word 0xb2790000 + .word 0xb27a0000 + .word 0xb27c0000 + .word 0xd51e4000 + .word 0x10000060 + .word 0xd51e4020 + .word 0xd69f03e0 + +.L__aarch32_code: + + nop + nop + nop + nop + ldr r0, =ma35d1_start + mov sp, r0 + ldr pc, =system_vectors diff --git a/bsp/nuvoton/numaker-hmi-ma35d1/preload/env_build.bat b/bsp/nuvoton/numaker-hmi-ma35d1/preload/env_build.bat new file mode 100644 index 0000000000..ad8f1ad7b9 --- /dev/null +++ b/bsp/nuvoton/numaker-hmi-ma35d1/preload/env_build.bat @@ -0,0 +1,9 @@ +@set RTT_CC=gcc +@set RTT_EXEC_PATH=C:\Program Files (x86)\GNU Tools ARM Embedded\8 2019-q3-aarch64-elf\bin +@set RTT_CC_PREFIX=aarch64-elf- +@set PATH=%RTT_EXEC_PATH%;%ENV_ROOT%\tools\gnu_gcc\arm_gcc\mingw\bin;%PATH% + +make +python transcode.py + +make -f Makefile.leave_ibr diff --git a/bsp/nuvoton/numaker-hmi-ma35d1/preload/leave_ibr.ASM b/bsp/nuvoton/numaker-hmi-ma35d1/preload/leave_ibr.ASM new file mode 100644 index 0000000000..91571076a7 --- /dev/null +++ b/bsp/nuvoton/numaker-hmi-ma35d1/preload/leave_ibr.ASM @@ -0,0 +1,53 @@ +/* + * Copyright (c) 2006-2020, RT-Thread Development Team + * + * SPDX-License-Identifier: Apache-2.0 + * + * Date Author Notes + * 2021-06-29 Wayne the first version + * + * Description: Load the routine into SRAM0 0x28000000 + * + */ + +.section ".text.boot" +.global _start + +_start: + /* Give execution address for secondary CPU */ + adr x20, . + + /*=============================================================*/ + /* Read CPU id */ + /* Primary core(id=0): Help Secondary core leaving. */ + /* Secondary core(id>0): Notice 'Ready' to Primary core. */ + /*=============================================================*/ + /* MPIDR_EL1: Multi-Processor Affinity Register */ + mrs x1, mpidr_el1 + and x1, x1, #3 + cbz x1, .L__cpu_0_loop + +.L__cpu_1_loop: + /*=============================================================*/ + /* Secondary CPU notification */ + /*=============================================================*/ + wfe /* Wait for Primary CPU's notification */ + + mov x0, #0x48 /* if (*(0x40460048)==PC) */ + movk x0, #0x4046, LSL #16 /* goto L__cpu_1_loop */ + ldr x1, [x0] /* else */ + cmp x1, x20 /* goto *(0x40460048) */ + b.eq .L__cpu_1_loop + br x1 + +.L__cpu_0_loop: + /*=============================================================*/ + /* Help CPU-1 to leave IBR. */ + /*=============================================================*/ + mov x0, #0x48 /* *(0x40460048) = _start */ + movk x0, #0x4046, LSL #16 + mov x1, x20 + str w1, [x0] + sev /* Wakeup Secondary CPU */ + b .L__cpu_0_loop + diff --git a/bsp/nuvoton/numaker-hmi-ma35d1/preload/preload.ASM b/bsp/nuvoton/numaker-hmi-ma35d1/preload/preload.ASM new file mode 100644 index 0000000000..59acab7d19 --- /dev/null +++ b/bsp/nuvoton/numaker-hmi-ma35d1/preload/preload.ASM @@ -0,0 +1,228 @@ +/* + * Copyright (c) 2006-2020, RT-Thread Development Team + * + * SPDX-License-Identifier: Apache-2.0 + * + * Date Author Notes + * 2021-06-29 Wayne the first version + */ + +/* GICv2 - Distributor Registers */ +#define GICD_CTLR 0x0000 +#define GICD_TYPER 0x0004 +#define GICD_IIDR 0x0008 +#define GICD_STATUSR 0x0010 +#define GICD_SETSPI_NSR 0x0040 +#define GICD_CLRSPI_NSR 0x0048 +#define GICD_SETSPI_SR 0x0050 +#define GICD_CLRSPI_SR 0x0058 +#define GICD_SEIR 0x0068 +#define GICD_IGROUPRn 0x0080 +#define GICD_ISENABLERn 0x0100 +#define GICD_ICENABLERn 0x0180 +#define GICD_ISPENDRn 0x0200 +#define GICD_ICPENDRn 0x0280 +#define GICD_ISACTIVERn 0x0300 +#define GICD_ICACTIVERn 0x0380 +#define GICD_IPRIORITYRn 0x0400 +#define GICD_ITARGETSRn 0x0800 +#define GICD_ICFGR 0x0c00 +#define GICD_IGROUPMODRn 0x0d00 +#define GICD_NSACRn 0x0e00 +#define GICD_SGIR 0x0f00 +#define GICD_CPENDSGIRn 0x0f10 +#define GICD_SPENDSGIRn 0x0f20 +#define GICD_IROUTERn 0x6000 + +/* GICv2 - CPU Interface Memory Mapped Registers */ +#define GICC_CTLR 0x0000 +#define GICC_PMR 0x0004 +#define GICC_BPR 0x0008 +#define GICC_IAR 0x000C +#define GICC_EOIR 0x0010 +#define GICC_RPR 0x0014 +#define GICC_HPPIR 0x0018 +#define GICC_ABPR 0x001c +#define GICC_AIAR 0x0020 +#define GICC_AEOIR 0x0024 +#define GICC_AHPPIR 0x0028 +#define GICC_APRn 0x00d0 +#define GICC_NSAPRn 0x00e0 +#define GICC_IIDR 0x00fc +#define GICC_DIR 0x1000 + +.section ".text.entrypoint" +.global _start + +_start: + /* Give execution address for secondary CPU */ + adr x20, . + mov sp, x20 + + /*=============================================================*/ + /* Enable the SMP bit. */ + /*=============================================================*/ + mrs x0, S3_1_C15_C2_1 + orr x0, x0, #(1<<6) + msr S3_1_C15_C2_1, x0 + + /*=============================================================*/ + /* Read CPU id */ + /* Primary core(id=0): Help Secondary core leaving. */ + /* Secondary core(id>0): Notice 'Ready' to Primary core. */ + /*=============================================================*/ + /* MPIDR_EL1: Multi-Processor Affinity Register */ + mrs x1, mpidr_el1 + and x1, x1, #3 + cbz x1, .L__cpu_0 + +.L__current_cpu_idle: + /*=============================================================*/ + /* Secondary CPU notification */ + /*=============================================================*/ + wfe /* Wait for Primary CPU's notification */ + + mov x0, #0x48 /* if (*(0x40460048)==0) */ + movk x0, #0x4046, LSL #16 /* goto L__current_cpu_idle */ + ldr x1, [x0] /* else */ + cmp x1, #0 /* *(0x4046004C)=_start */ + b.eq .L__current_cpu_idle /* goto L__cpus_trans_state */ + add x0, x0, #4 + str w1, [x0] + + b .L__cpus_trans_state + +.L__cpu_0: + + // *(0x4046004C) = 0 + mov x0, #0x4C + movk x0, #0x4046, LSL #16 + mov x1, xzr + str w1, [x0] + + mov x10, #0x1000 /* 4096 times looping */ +.L__cpu_0_loop: + sub x10, x10, #0x1 + cmp x10, #0 + b.eq .L__cpus_trans_state + /*=============================================================*/ + /* Help CPU-1 to leave IBR. */ + /*=============================================================*/ + mov x0, #0x48 /* *(0x40460048) = _start */ + movk x0, #0x4046, LSL #16 + mov x1, x20 + str w1, [x0] + + sev /* Wakeup Secondary CPU */ + + add x0, x0, #4 /* if(*(0x4046004C)!=_start) */ + ldr w2, [x0] /* goto L__cpu_0_loop */ + cmp x1, x2 + bne .L__cpu_0_loop + +.L__cpus_trans_state: + + /*=============================================================*/ + /* Initialize Gtimer. Set frequency to 12MHz. */ + /*=============================================================*/ + mov x0, #0x1B00 + movk x0, #0xB7, LSL #16 + msr CNTFRQ_EL0, x0 + + /*=============================================================*/ + /* Enable GICv2. */ + /* Assign all IRQs to secure group. */ + /*=============================================================*/ + /* Route to secure Group */ + mov x0, #0x1000 + movk x0, #0x5080, LSL #16 + mov w9, #0x3 + str w9, [x0, GICD_CTLR] + ldr w9, [x0, GICD_TYPER] + and w10, w9, #0x1f + cbz w10, 1f + add x11, x0, GICD_IGROUPRn + mov w9, #0 + str w9, [x11], #0x04 +0: str w9, [x11], #0x04 + sub w10, w10, #0x1 + cbnz w10, 0b + + mov x1, #0x2000 + movk x1, #0x5080, LSL #16 + mov w0, #3 + str w0, [x1] + + mov w0, #1 << 7 + str w0, [x1, #4] +1: + mov x0, #0x1000 + movk x0, #0x5080, LSL #16 + mov x1, #0x2000 + movk x1, #0x5080, LSL #16 + + mov w9, #0 + str w9, [x0, GICD_IGROUPRn] + mov w9, #0x1 + str w9, [x0, GICD_ISENABLERn] + + mov w9, #0x1e7 + str w9, [x1, GICC_CTLR] + + mov w9, #0x1 << 7 + str w9, [x1, GICC_PMR] + + /*=============================================================*/ + /* Enable FP/SIMD at EL1 */ + /*=============================================================*/ + mov x0, #(3 << 20) + msr cpacr_el1, x0 /* Enable FP/SIMD at EL1 */ + + /*=============================================================*/ + /* Initialize sctlr_el1 */ + /*=============================================================*/ + mov x0, xzr + orr x0, x0, #(1 << 29) /* Enable LSMAOE at EL1 */ + orr x0, x0, #(1 << 28) /* Enable nTLSMD at EL1 */ + orr x0, x0, #(1 << 23) /* Enable SPAN at EL1 */ + orr x0, x0, #(1 << 22) /* Enable EIS at EL1 */ + orr x0, x0, #(1 << 20) /* Enable TSCXT at EL1 */ + orr x0, x0, #(1 << 11) /* Enable EOS at EL1 */ + msr sctlr_el1, x0 + + /*=============================================================*/ + /* Initialize scr_el3 */ + /*=============================================================*/ + mov x0, xzr + /* RW, Lower levels are all AArch32. */ + orr x0, x0, #(1 << 9) /* Enable SIF */ + orr x0, x0, #(1 << 8) /* Enable HCE */ + orr x0, x0, #(1 << 7) /* Enable SMD */ + orr x0, x0, #(1 << 5) /* RES1[5:4] */ + orr x0, x0, #(1 << 4) + /* Disable FIQ routing */ + /* Disable IRQ routing */ + /* Disable NS */ + msr scr_el3, x0 + + /*=============================================================*/ + /* Initialize spsr_el3 */ + /*=============================================================*/ + mov x0, xzr + mov x0, #0b00011 /* AARCH32_SVC */ + orr x0, x0, #(1 << 8) /* Enable SError and External Abort. */ + orr x0, x0, #(1 << 7) /* IRQ interrupt Process state mask. */ + orr x0, x0, #(1 << 6) /* FIQ interrupt Process state mask. */ + orr x0, x0, #(1 << 4) /* FIQ interrupt Process state mask. */ + msr spsr_el3, x0 + + /*=============================================================*/ + /* Initialize elr_el3 */ + /* Jump to Secure AARCH32_SVC from EL3. */ + /*=============================================================*/ + adr x0, .aarch32_code /* Exception return to aarch32_code */ + msr elr_el3, x0 + eret + +.aarch32_code: + diff --git a/bsp/nuvoton/numaker-hmi-ma35d1/preload/preload.ld b/bsp/nuvoton/numaker-hmi-ma35d1/preload/preload.ld new file mode 100644 index 0000000000..bfe4705d25 --- /dev/null +++ b/bsp/nuvoton/numaker-hmi-ma35d1/preload/preload.ld @@ -0,0 +1,113 @@ +SECTIONS +{ + . = 0x80400000; + . = ALIGN(4096); + .text : + { + KEEP(*(.text.entrypoint)) /* The entry point */ + *(.vectors) + *(.text) /* remaining code */ + *(.text.*) /* remaining code */ + + *(.rodata) /* read-only data (constants) */ + *(.rodata*) + *(.glue_7) + *(.glue_7t) + *(.gnu.linkonce.t*) + + *(COMMON) + + _etext = .; + } + + . = ALIGN(16); + .eh_frame_hdr : + { + *(.eh_frame_hdr) + *(.eh_frame_entry) + } + .eh_frame : ONLY_IF_RO { KEEP (*(.eh_frame)) } + + . = ALIGN(16); + .data : + { + *(.data) + *(.data.*) + + *(.data1) + *(.data1.*) + + . = ALIGN(16); + _gp = ABSOLUTE(.); /* Base of small data */ + + *(.sdata) + *(.sdata.*) + } + + . = ALIGN(16); + .ctors : + { + PROVIDE(__ctors_start__ = .); + KEEP(*(SORT(.ctors.*))) + KEEP(*(.ctors)) + PROVIDE(__ctors_end__ = .); + } + + .dtors : + { + PROVIDE(__dtors_start__ = .); + KEEP(*(SORT(.dtors.*))) + KEEP(*(.dtors)) + PROVIDE(__dtors_end__ = .); + } + + . = ALIGN(16); + .nobss : { *(.nobss) } + + . = ALIGN(16); + __bss_start__ = .; + __bss_start = .; + .bss : { *(.bss)} + . = ALIGN(16); + __bss_end = .; + __bss_end__ = .; + . = ALIGN(16); + + /* Stabs debugging sections. */ + .stab 0 : { *(.stab) } + .stabstr 0 : { *(.stabstr) } + .stab.excl 0 : { *(.stab.excl) } + .stab.exclstr 0 : { *(.stab.exclstr) } + .stab.index 0 : { *(.stab.index) } + .stab.indexstr 0 : { *(.stab.indexstr) } + .comment 0 : { *(.comment) } + /* DWARF debug sections. + * Symbols in the DWARF debugging sections are relative to the beginning + * of the section so we begin them at 0. */ + /* DWARF 1 */ + .debug 0 : { *(.debug) } + .line 0 : { *(.line) } + /* GNU DWARF 1 extensions */ + .debug_srcinfo 0 : { *(.debug_srcinfo) } + .debug_sfnames 0 : { *(.debug_sfnames) } + /* DWARF 1.1 and DWARF 2 */ + .debug_aranges 0 : { *(.debug_aranges) } + .debug_pubnames 0 : { *(.debug_pubnames) } + /* DWARF 2 */ + .debug_info 0 : { *(.debug_info .gnu.linkonce.wi.*) } + .debug_abbrev 0 : { *(.debug_abbrev) } + .debug_line 0 : { *(.debug_line) } + .debug_frame 0 : { *(.debug_frame) } + .debug_str 0 : { *(.debug_str) } + .debug_loc 0 : { *(.debug_loc) } + .debug_macinfo 0 : { *(.debug_macinfo) } + /* SGI/MIPS DWARF 2 extensions */ + .debug_weaknames 0 : { *(.debug_weaknames) } + .debug_funcnames 0 : { *(.debug_funcnames) } + .debug_typenames 0 : { *(.debug_typenames) } + .debug_varnames 0 : { *(.debug_varnames) } + + _end = .; +} + +__bss_size = (__bss_end - __bss_start)>>3; diff --git a/bsp/nuvoton/numaker-hmi-ma35d1/preload/transcode.py b/bsp/nuvoton/numaker-hmi-ma35d1/preload/transcode.py new file mode 100644 index 0000000000..a918f45245 --- /dev/null +++ b/bsp/nuvoton/numaker-hmi-ma35d1/preload/transcode.py @@ -0,0 +1,41 @@ +# -*- coding: UTF-8 -*- + +import os + +def extract_line(fname, pattern): + with open(fname, "r") as f: + lines = f.readlines() + f.close() + with open("entry_point.S", "w") as f: + counter=0 + f.write(".section \".text.entrypoint\"\n") + f.write(".globl system_vectors\n") + f.write("\n") + f.write("ma35d1_start:\n") + for line in lines: + if pattern in line: + new_line = " .word 0x" + line[6:14] + "\n" + f.write(new_line) + counter = counter+1 + f.write("\n") + f.write(".L__aarch32_code:\n") + f.write("\n") + # Append NOP to align vector table. + counter = (counter+5)*4 + counter_align = (counter+32-1) & ~(32-1) + nop_num = (counter_align - counter) / 4 + print hex(counter), hex(counter_align), nop_num + j = 0 + while j < nop_num: + f.write(" nop\n") + j += 1 + f.write(" ldr r0, =ma35d1_start\n") + f.write(" mov sp, r0\n") + f.write(" ldr pc, =system_vectors\n") + f.close() + +def formatfiles(): + extract_line("preload.txt", ":\t") + +if __name__ == '__main__': + formatfiles() diff --git a/bsp/nuvoton/numaker-hmi-ma35d1/rtconfig.py b/bsp/nuvoton/numaker-hmi-ma35d1/rtconfig.py new file mode 100644 index 0000000000..5d1b514111 --- /dev/null +++ b/bsp/nuvoton/numaker-hmi-ma35d1/rtconfig.py @@ -0,0 +1,77 @@ +import os +# toolchains options +ARCH = 'arm' +CPU = 'cortex-a' +# toolchains options +CROSS_TOOL = 'gcc' + +if os.getenv('RTT_CC'): + CROSS_TOOL = os.getenv('RTT_CC') +if os.getenv('RTT_ROOT'): + RTT_ROOT = os.getenv('RTT_ROOT') + +# cross_tool provides the cross compiler +# EXEC_PATH is the compiler execute path, for example, CodeSourcery, Keil MDK, IAR + +if CROSS_TOOL == 'gcc': + PLATFORM = 'gcc' + EXEC_PATH = r'C:\Program Files (x86)\GNU Tools ARM Embedded\6 2017-q1-update\bin' +elif os.getenv('RTT_EXEC_PATH'): + EXEC_PATH = os.getenv('RTT_EXEC_PATH') + +#BUILD = 'debug' +BUILD = '' +MAP_FILE = 'rtthread_ma35d1.map' +LINK_FILE = 'linking_scripts/aarch32' +TARGET_NAME = 'rtthread.bin' + +#------- GCC settings ---------------------------------------------------------- +if PLATFORM == 'gcc': + # toolchains + PREFIX = 'arm-none-eabi-' + CC = PREFIX + 'gcc' + AS = PREFIX + 'gcc' + AR = PREFIX + 'ar' + CXX = PREFIX + 'g++' + LINK = PREFIX + 'gcc' + TARGET_EXT = 'elf' + SIZE = PREFIX + 'size' + OBJDUMP = PREFIX + 'objdump' + OBJCPY = PREFIX + 'objcopy' + STRIP = PREFIX + 'strip' + + DEVICE = ' -march=armv8-a -mfpu=neon-vfpv4 -ftree-vectorize -ffast-math -mfloat-abi=softfp' +# DEVICE = ' -march=armv7-a -mfpu=vfpv3-d16 -ftree-vectorize -ffast-math -mfloat-abi=softfp' + CFLAGS = DEVICE + ' -Wall -fno-zero-initialized-in-bss ' + AFLAGS = ' -c' + DEVICE + ' -x assembler-with-cpp -D__ASSEMBLY__' + LFLAGS = DEVICE + ' -nostartfiles -Wl,--gc-sections,-cref,-Map=' + MAP_FILE + ',-cref,-u,system_vectors' + ' -T ' + LINK_FILE + '.ld' + CXXFLAGS = ' -march=armv8-a -mfpu=neon-vfpv4 -std=c++11 ' + + M_CFLAGS = CFLAGS + ' -mlong-calls -fPIC ' + M_CXXFLAGS = CXXFLAGS + ' -mlong-calls -fPIC' + M_LFLAGS = DEVICE + CXXFLAGS + ' -Wl,--gc-sections,-z,max-page-size=0x4' +\ + ' -shared -fPIC -nostartfiles -nostdlib -static-libgcc' + M_POST_ACTION = STRIP + ' -R .hash $TARGET\n' + SIZE + ' $TARGET \n' + #M_BIN_PATH = r'z:\fatdisk\root' + + CPATH = '' + LPATH = '' + + if BUILD == 'debug': + CFLAGS += ' -O0 -gdwarf-2 -g' + AFLAGS += ' -gdwarf-2' + else: + CFLAGS += ' -O2' + + CXXFLAGS = CFLAGS + + POST_ACTION = OBJCPY + ' -O binary $TARGET ' + TARGET_NAME + '\n' + POST_ACTION += SIZE + ' $TARGET\n' + + +def dist_handle(BSP_ROOT, dist_dir): + import sys + cwd_path = os.getcwd() + sys.path.append(os.path.join(os.path.dirname(BSP_ROOT), 'tools')) + from sdk_dist import dist_do_building + dist_do_building(BSP_ROOT, dist_dir) diff --git a/bsp/nuvoton/numaker-iot-m467/.config b/bsp/nuvoton/numaker-iot-m467/.config index b23d434f74..46b064294d 100644 --- a/bsp/nuvoton/numaker-iot-m467/.config +++ b/bsp/nuvoton/numaker-iot-m467/.config @@ -798,7 +798,7 @@ CONFIG_PKG_USING_MPU6XXX_LATEST_VERSION=y CONFIG_PKG_MPU6XXX_VER="latest" CONFIG_PKG_USING_MPU6XXX_ACCE=y CONFIG_PKG_USING_MPU6XXX_GYRO=y -# CONFIG_PKG_USING_MPU6XXX_MAG is not set +CONFIG_PKG_USING_MPU6XXX_MAG=y # CONFIG_PKG_USING_AHT10 is not set # CONFIG_PKG_USING_AP3216C is not set # CONFIG_PKG_USING_TSL4531 is not set @@ -1152,7 +1152,6 @@ CONFIG_BOARD_USING_HSUSBH_USBD=y # # Board extended module drivers # -# CONFIG_BOARD_USING_LCD_ILI9341 is not set # # Nuvoton Packages Config @@ -1172,3 +1171,5 @@ CONFIG_NU_PKG_USING_NCT7717U=y # CONFIG_NU_PKG_USING_TPC is not set # CONFIG_NU_PKG_USING_ADC_TOUCH is not set # CONFIG_NU_PKG_USING_SPINAND is not set +CONFIG_UTEST_CMD_PREFIX="bsp.nuvoton.utest." +CONFIG_BOARD_USE_UTEST=y diff --git a/bsp/nuvoton/numaker-iot-m467/applications/mnt.c b/bsp/nuvoton/numaker-iot-m467/applications/mnt.c index dd8a5cb210..ebea69fdc7 100644 --- a/bsp/nuvoton/numaker-iot-m467/applications/mnt.c +++ b/bsp/nuvoton/numaker-iot-m467/applications/mnt.c @@ -30,11 +30,6 @@ #include #endif -#if defined(BOARD_USING_STORAGE_SPIFLASH) - #define PARTITION_NAME_FILESYSTEM "filesystem" - #define MOUNT_POINT_SPIFLASH0 "/" -#endif - #ifdef RT_USING_DFS_MNTTABLE /* @@ -57,8 +52,11 @@ const struct dfs_mount_tbl mount_table[] = }; #endif +#if defined(BOARD_USING_STORAGE_SPIFLASH) + #define PARTITION_NAME_FILESYSTEM "filesystem" + #define MOUNT_POINT_SPIFLASH0 "/" + /* Recursive mkdir */ -#if defined(RT_USBH_MSTORAGE) && defined(UDISK_MOUNTPOINT) static int mkdir_p(const char *dir, const mode_t mode) { int ret = -1; @@ -127,9 +125,7 @@ exit_mkdir_p: return ret; } -#endif -#if defined(BOARD_USING_STORAGE_SPIFLASH) int mnt_init_spiflash0(void) { #if defined(RT_USING_FAL) @@ -156,13 +152,8 @@ int mnt_init_spiflash0(void) mkdir_p("/mnt/sd1", 0x777); mkdir_p("/mnt/sd1p0", 0x777); mkdir_p("/mnt/sd1p1", 0x777); + mkdir_p(UDISK_MOUNTPOINT, 0x777); -#if defined(RT_USBH_MSTORAGE) && defined(UDISK_MOUNTPOINT) - if (mkdir_p(UDISK_MOUNTPOINT, 0) < 0) - { - rt_kprintf("Failed to create directory on %s for RT_USBH_MSTORAGE.\n", UDISK_MOUNTPOINT); - } -#endif exit_mnt_init_spiflash0: return 0; diff --git a/bsp/nuvoton/numaker-m032ki/.config b/bsp/nuvoton/numaker-m032ki/.config index 6f62b8ecd0..6ff71a489c 100644 --- a/bsp/nuvoton/numaker-m032ki/.config +++ b/bsp/nuvoton/numaker-m032ki/.config @@ -796,3 +796,5 @@ CONFIG_NU_PKG_USING_DEMO=y # CONFIG_NU_PKG_USING_TPC is not set # CONFIG_NU_PKG_USING_ADC_TOUCH is not set # CONFIG_NU_PKG_USING_SPINAND is not set +CONFIG_UTEST_CMD_PREFIX="bsp.nuvoton.utest." +CONFIG_BOARD_USE_UTEST=y diff --git a/bsp/nuvoton/numaker-m467hj/.config b/bsp/nuvoton/numaker-m467hj/.config index 50c9c014f9..aae4c090b7 100644 --- a/bsp/nuvoton/numaker-m467hj/.config +++ b/bsp/nuvoton/numaker-m467hj/.config @@ -1086,3 +1086,5 @@ CONFIG_NU_PKG_USING_NAU8822=y # CONFIG_NU_PKG_USING_TPC is not set # CONFIG_NU_PKG_USING_ADC_TOUCH is not set # CONFIG_NU_PKG_USING_SPINAND is not set +CONFIG_UTEST_CMD_PREFIX="bsp.nuvoton.utest." +CONFIG_BOARD_USE_UTEST=y diff --git a/bsp/nuvoton/numaker-m467hj/board/board_dev.c b/bsp/nuvoton/numaker-m467hj/board/board_dev.c index 16e6ac85fc..e1399a6cbf 100644 --- a/bsp/nuvoton/numaker-m467hj/board/board_dev.c +++ b/bsp/nuvoton/numaker-m467hj/board/board_dev.c @@ -332,7 +332,7 @@ ccap_sensor_io sIo_sensor0 = int rt_hw_sensor0_port(void) { - return nu_ccap_sensor_create(&sIo_sensor0, (ccap_sensor_id)BOARD_USING_SENSON0_ID); + return nu_ccap_sensor_create(&sIo_sensor0, (ccap_sensor_id)BOARD_USING_SENSON0_ID, "sensor0"); } INIT_COMPONENT_EXPORT(rt_hw_sensor0_port);

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