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Add the BSP of HC32 series. (#5905) 

* Add the BSP of HC32 series.
This commit is contained in:
Jamie 2022-05-06 09:28:21 +08:00 committed by GitHub
parent 0e66f3f833
commit 28b551bfe3
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345 changed files with 402773 additions and 0 deletions
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# HC32 BSP 说明
HC32 系列 BSP 目前支持情况如下表所示：
| **BSP 文件夹名称** | **开发板名称** |
|:------------------------- |:------------------------- |
| **F1 系列** | |
| **F4 系列** | |
| [ev_hc32f4a0_lqfp176](ev_hc32f4a0_lqfp176) | 小华 官方 EV_F4A0_LQ176 开发板 |
| **M1 系列** | |
| **M4 系列** | |
可以通过阅读相应 BSP 下的 README 来快速上手，如果想要使用 BSP 更多功能可参考 docs 文件夹下提供的说明文档，如下表所示：
| **BSP 使用教程** | **简介** |
|:-------------------- |:------------------------------------------------- |
| [外设驱动使用教程](docs/HC32系列BSP外设驱动使用教程.md) | 讲解 BSP 上更多外设驱动的使用方法 |
| [外设驱动介绍与应用](docs/HC32系列驱动介绍.md) | 讲解 HC32 系列 BSP 驱动的支持情况，以及如何利用驱动框架开发应用程序 |
| **BSP 制作与提交** | **简介** |
| [BSP 制作教程](docs/HC32系列BSP制作教程.md) | 讲解 HC32 系列 BSP 的制作方法 |

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# HC32 系列 BSP 制作教程

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# HC32系列BSP外设驱动使用教程

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# HC32系列驱动介绍

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bsp/hc32/ev_hc32f4a0_lqfp176/.config Normal file
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#
# Automatically generated file; DO NOT EDIT.
# RT-Thread Configuration
#
#
# RT-Thread Kernel
#
CONFIG_RT_NAME_MAX=8
# CONFIG_RT_USING_ARCH_DATA_TYPE is not set
# CONFIG_RT_USING_SMP is not set
CONFIG_RT_ALIGN_SIZE=4
# CONFIG_RT_THREAD_PRIORITY_8 is not set
CONFIG_RT_THREAD_PRIORITY_32=y
# CONFIG_RT_THREAD_PRIORITY_256 is not set
CONFIG_RT_THREAD_PRIORITY_MAX=32
CONFIG_RT_TICK_PER_SECOND=1000
CONFIG_RT_USING_OVERFLOW_CHECK=y
CONFIG_RT_USING_HOOK=y
CONFIG_RT_HOOK_USING_FUNC_PTR=y
CONFIG_RT_USING_IDLE_HOOK=y
CONFIG_RT_IDLE_HOOK_LIST_SIZE=4
CONFIG_IDLE_THREAD_STACK_SIZE=256
# CONFIG_RT_USING_TIMER_SOFT is not set
#
# kservice optimization
#
# CONFIG_RT_KSERVICE_USING_STDLIB is not set
# CONFIG_RT_KSERVICE_USING_TINY_SIZE is not set
# CONFIG_RT_USING_TINY_FFS is not set
# CONFIG_RT_KPRINTF_USING_LONGLONG is not set
CONFIG_RT_DEBUG=y
CONFIG_RT_DEBUG_COLOR=y
# CONFIG_RT_DEBUG_INIT_CONFIG is not set
# CONFIG_RT_DEBUG_THREAD_CONFIG is not set
# CONFIG_RT_DEBUG_SCHEDULER_CONFIG is not set
# CONFIG_RT_DEBUG_IPC_CONFIG is not set
# CONFIG_RT_DEBUG_TIMER_CONFIG is not set
# CONFIG_RT_DEBUG_IRQ_CONFIG is not set
# CONFIG_RT_DEBUG_MEM_CONFIG is not set
# CONFIG_RT_DEBUG_SLAB_CONFIG is not set
# CONFIG_RT_DEBUG_MEMHEAP_CONFIG is not set
# CONFIG_RT_DEBUG_MODULE_CONFIG is not set
#
# Inter-Thread communication
#
CONFIG_RT_USING_SEMAPHORE=y
CONFIG_RT_USING_MUTEX=y
CONFIG_RT_USING_EVENT=y
CONFIG_RT_USING_MAILBOX=y
CONFIG_RT_USING_MESSAGEQUEUE=y
# CONFIG_RT_USING_SIGNALS is not set
#
# Memory Management
#
CONFIG_RT_USING_MEMPOOL=y
CONFIG_RT_USING_SMALL_MEM=y
# CONFIG_RT_USING_SLAB is not set
# CONFIG_RT_USING_MEMHEAP is not set
CONFIG_RT_USING_SMALL_MEM_AS_HEAP=y
# CONFIG_RT_USING_MEMHEAP_AS_HEAP is not set
# CONFIG_RT_USING_SLAB_AS_HEAP is not set
# CONFIG_RT_USING_USERHEAP is not set
# CONFIG_RT_USING_NOHEAP is not set
# CONFIG_RT_USING_MEMTRACE is not set
# CONFIG_RT_USING_HEAP_ISR is not set
CONFIG_RT_USING_HEAP=y
#
# Kernel Device Object
#
CONFIG_RT_USING_DEVICE=y
# CONFIG_RT_USING_DEVICE_OPS is not set
# CONFIG_RT_USING_INTERRUPT_INFO is not set
CONFIG_RT_USING_CONSOLE=y
CONFIG_RT_CONSOLEBUF_SIZE=128
CONFIG_RT_CONSOLE_DEVICE_NAME="uart1"
CONFIG_RT_VER_NUM=0x40100
CONFIG_ARCH_ARM=y
CONFIG_RT_USING_CPU_FFS=y
CONFIG_ARCH_ARM_CORTEX_M=y
CONFIG_ARCH_ARM_CORTEX_M4=y
# CONFIG_ARCH_CPU_STACK_GROWS_UPWARD is not set
#
# RT-Thread Components
#
CONFIG_RT_USING_COMPONENTS_INIT=y
CONFIG_RT_USING_USER_MAIN=y
CONFIG_RT_MAIN_THREAD_STACK_SIZE=2048
CONFIG_RT_MAIN_THREAD_PRIORITY=10
# CONFIG_RT_USING_LEGACY is not set
CONFIG_RT_USING_MSH=y
CONFIG_RT_USING_FINSH=y
CONFIG_FINSH_USING_MSH=y
CONFIG_FINSH_THREAD_NAME="tshell"
CONFIG_FINSH_THREAD_PRIORITY=20
CONFIG_FINSH_THREAD_STACK_SIZE=4096
CONFIG_FINSH_USING_HISTORY=y
CONFIG_FINSH_HISTORY_LINES=5
CONFIG_FINSH_USING_SYMTAB=y
CONFIG_FINSH_CMD_SIZE=80
CONFIG_MSH_USING_BUILT_IN_COMMANDS=y
CONFIG_FINSH_USING_DESCRIPTION=y
# CONFIG_FINSH_ECHO_DISABLE_DEFAULT is not set
# CONFIG_FINSH_USING_AUTH is not set
CONFIG_FINSH_ARG_MAX=10
# CONFIG_RT_USING_DFS is not set
# CONFIG_RT_USING_FAL is not set
# CONFIG_RT_USING_LWP is not set
#
# Device Drivers
#
CONFIG_RT_USING_DEVICE_IPC=y
CONFIG_RT_USING_SYSTEM_WORKQUEUE=y
CONFIG_RT_SYSTEM_WORKQUEUE_STACKSIZE=2048
CONFIG_RT_SYSTEM_WORKQUEUE_PRIORITY=23
CONFIG_RT_USING_SERIAL=y
CONFIG_RT_USING_SERIAL_V1=y
# CONFIG_RT_USING_SERIAL_V2 is not set
CONFIG_RT_SERIAL_USING_DMA=y
CONFIG_RT_SERIAL_RB_BUFSZ=64
# CONFIG_RT_USING_CAN is not set
CONFIG_RT_USING_HWTIMER=y
# CONFIG_RT_USING_CPUTIME is not set
CONFIG_RT_USING_I2C=y
# CONFIG_RT_I2C_DEBUG is not set
CONFIG_RT_USING_I2C_BITOPS=y
# CONFIG_RT_I2C_BITOPS_DEBUG is not set
# CONFIG_RT_USING_PHY is not set
CONFIG_RT_USING_PIN=y
# CONFIG_RT_USING_ADC is not set
# CONFIG_RT_USING_DAC is not set
CONFIG_RT_USING_PWM=y
# CONFIG_RT_USING_MTD_NOR is not set
# CONFIG_RT_USING_MTD_NAND is not set
# CONFIG_RT_USING_PM is not set
CONFIG_RT_USING_RTC=y
# CONFIG_RT_USING_ALARM is not set
# CONFIG_RT_USING_SOFT_RTC is not set
# CONFIG_RT_USING_SDIO is not set
CONFIG_RT_USING_SPI=y
# CONFIG_RT_USING_SPI_BITOPS is not set
# CONFIG_RT_USING_QSPI is not set
# CONFIG_RT_USING_SPI_MSD is not set
# CONFIG_RT_USING_SFUD is not set
# CONFIG_RT_USING_ENC28J60 is not set
# CONFIG_RT_USING_SPI_WIFI is not set
# CONFIG_RT_USING_WDT is not set
# CONFIG_RT_USING_AUDIO is not set
# CONFIG_RT_USING_SENSOR is not set
# CONFIG_RT_USING_TOUCH is not set
# CONFIG_RT_USING_HWCRYPTO is not set
CONFIG_RT_USING_PULSE_ENCODER=y
# CONFIG_RT_USING_INPUT_CAPTURE is not set
# CONFIG_RT_USING_WIFI is not set
#
# Using USB
#
# CONFIG_RT_USING_USB is not set
# CONFIG_RT_USING_USB_HOST is not set
# CONFIG_RT_USING_USB_DEVICE is not set
#
# C/C++ and POSIX layer
#
CONFIG_RT_LIBC_DEFAULT_TIMEZONE=8
#
# POSIX (Portable Operating System Interface) layer
#
# CONFIG_RT_USING_POSIX_FS is not set
# CONFIG_RT_USING_POSIX_DELAY is not set
# CONFIG_RT_USING_POSIX_CLOCK is not set
# CONFIG_RT_USING_POSIX_TIMER is not set
# CONFIG_RT_USING_PTHREADS is not set
# CONFIG_RT_USING_MODULE is not set
#
# Interprocess Communication (IPC)
#
# CONFIG_RT_USING_POSIX_PIPE is not set
# CONFIG_RT_USING_POSIX_MESSAGE_QUEUE is not set
# CONFIG_RT_USING_POSIX_MESSAGE_SEMAPHORE is not set
#
# Socket is in the 'Network' category
#
# CONFIG_RT_USING_CPLUSPLUS is not set
#
# Network
#
# CONFIG_RT_USING_SAL is not set
# CONFIG_RT_USING_NETDEV is not set
# CONFIG_RT_USING_LWIP is not set
# CONFIG_RT_USING_AT is not set
#
# Utilities
#
# CONFIG_RT_USING_RYM is not set
# CONFIG_RT_USING_ULOG is not set
# CONFIG_RT_USING_UTEST is not set
# CONFIG_RT_USING_VAR_EXPORT is not set
# CONFIG_RT_USING_RT_LINK is not set
# CONFIG_RT_USING_VBUS is not set
#
# RT-Thread Utestcases
#
# CONFIG_RT_USING_UTESTCASES is not set
#
# RT-Thread online packages
#
#
# IoT - internet of things
#
# CONFIG_PKG_USING_LWIP is not set
# CONFIG_PKG_USING_LORAWAN_DRIVER is not set
# CONFIG_PKG_USING_PAHOMQTT is not set
# CONFIG_PKG_USING_UMQTT is not set
# CONFIG_PKG_USING_WEBCLIENT is not set
# CONFIG_PKG_USING_WEBNET is not set
# CONFIG_PKG_USING_MONGOOSE is not set
# CONFIG_PKG_USING_MYMQTT is not set
# CONFIG_PKG_USING_KAWAII_MQTT is not set
# CONFIG_PKG_USING_BC28_MQTT is not set
# CONFIG_PKG_USING_WEBTERMINAL is not set
# CONFIG_PKG_USING_LIBMODBUS is not set
# CONFIG_PKG_USING_FREEMODBUS is not set
# CONFIG_PKG_USING_NANOPB is not set
#
# Wi-Fi
#
#
# Marvell WiFi
#
# CONFIG_PKG_USING_WLANMARVELL is not set
#
# Wiced WiFi
#
# CONFIG_PKG_USING_WLAN_WICED is not set
# CONFIG_PKG_USING_RW007 is not set
# CONFIG_PKG_USING_COAP is not set
# CONFIG_PKG_USING_NOPOLL is not set
# CONFIG_PKG_USING_NETUTILS is not set
# CONFIG_PKG_USING_CMUX is not set
# CONFIG_PKG_USING_PPP_DEVICE is not set
# CONFIG_PKG_USING_AT_DEVICE is not set
# CONFIG_PKG_USING_ATSRV_SOCKET is not set
# CONFIG_PKG_USING_WIZNET is not set
# CONFIG_PKG_USING_ZB_COORDINATOR is not set
#
# IoT Cloud
#
# CONFIG_PKG_USING_ONENET is not set
# CONFIG_PKG_USING_GAGENT_CLOUD is not set
# CONFIG_PKG_USING_ALI_IOTKIT is not set
# CONFIG_PKG_USING_AZURE is not set
# CONFIG_PKG_USING_TENCENT_IOT_EXPLORER is not set
# CONFIG_PKG_USING_JIOT-C-SDK is not set
# CONFIG_PKG_USING_UCLOUD_IOT_SDK is not set
# CONFIG_PKG_USING_JOYLINK is not set
# CONFIG_PKG_USING_EZ_IOT_OS is not set
# CONFIG_PKG_USING_NIMBLE is not set
# CONFIG_PKG_USING_LLSYNC_SDK_ADAPTER is not set
# CONFIG_PKG_USING_OTA_DOWNLOADER is not set
# CONFIG_PKG_USING_IPMSG is not set
# CONFIG_PKG_USING_LSSDP is not set
# CONFIG_PKG_USING_AIRKISS_OPEN is not set
# CONFIG_PKG_USING_LIBRWS is not set
# CONFIG_PKG_USING_TCPSERVER is not set
# CONFIG_PKG_USING_PROTOBUF_C is not set
# CONFIG_PKG_USING_DLT645 is not set
# CONFIG_PKG_USING_QXWZ is not set
# CONFIG_PKG_USING_SMTP_CLIENT is not set
# CONFIG_PKG_USING_ABUP_FOTA is not set
# CONFIG_PKG_USING_LIBCURL2RTT is not set
# CONFIG_PKG_USING_CAPNP is not set
# CONFIG_PKG_USING_AGILE_TELNET is not set
# CONFIG_PKG_USING_NMEALIB is not set
# CONFIG_PKG_USING_PDULIB is not set
# CONFIG_PKG_USING_BTSTACK is not set
# CONFIG_PKG_USING_LORAWAN_ED_STACK is not set
# CONFIG_PKG_USING_WAYZ_IOTKIT is not set
# CONFIG_PKG_USING_MAVLINK is not set
# CONFIG_PKG_USING_BSAL is not set
# CONFIG_PKG_USING_AGILE_MODBUS is not set
# CONFIG_PKG_USING_AGILE_FTP is not set
# CONFIG_PKG_USING_EMBEDDEDPROTO is not set
# CONFIG_PKG_USING_RT_LINK_HW is not set
# CONFIG_PKG_USING_LORA_PKT_FWD is not set
# CONFIG_PKG_USING_LORA_GW_DRIVER_LIB is not set
# CONFIG_PKG_USING_LORA_PKT_SNIFFER is not set
# CONFIG_PKG_USING_HM is not set
# CONFIG_PKG_USING_SMALL_MODBUS is not set
# CONFIG_PKG_USING_NET_SERVER is not set
#
# security packages
#
# CONFIG_PKG_USING_MBEDTLS is not set
# CONFIG_PKG_USING_LIBSODIUM is not set
# CONFIG_PKG_USING_TINYCRYPT is not set
# CONFIG_PKG_USING_TFM is not set
# CONFIG_PKG_USING_YD_CRYPTO is not set
#
# language packages
#
#
# JSON: JavaScript Object Notation, a lightweight data-interchange format
#
# CONFIG_PKG_USING_CJSON is not set
# CONFIG_PKG_USING_LJSON is not set
# CONFIG_PKG_USING_RT_CJSON_TOOLS is not set
# CONFIG_PKG_USING_RAPIDJSON is not set
# CONFIG_PKG_USING_JSMN is not set
# CONFIG_PKG_USING_AGILE_JSMN is not set
#
# XML: Extensible Markup Language
#
# CONFIG_PKG_USING_SIMPLE_XML is not set
# CONFIG_PKG_USING_EZXML is not set
# CONFIG_PKG_USING_LUATOS_SOC is not set
# CONFIG_PKG_USING_LUA is not set
# CONFIG_PKG_USING_JERRYSCRIPT is not set
# CONFIG_PKG_USING_MICROPYTHON is not set
# CONFIG_PKG_USING_PIKASCRIPT is not set
#
# multimedia packages
#
#
# LVGL: powerful and easy-to-use embedded GUI library
#
# CONFIG_PKG_USING_LVGL is not set
# CONFIG_PKG_USING_LITTLEVGL2RTT is not set
# CONFIG_PKG_USING_LV_MUSIC_DEMO is not set
#
# u8g2: a monochrome graphic library
#
# CONFIG_PKG_USING_U8G2_OFFICIAL is not set
# CONFIG_PKG_USING_U8G2 is not set
# CONFIG_PKG_USING_OPENMV is not set
# CONFIG_PKG_USING_MUPDF is not set
# CONFIG_PKG_USING_STEMWIN is not set
# CONFIG_PKG_USING_WAVPLAYER is not set
# CONFIG_PKG_USING_TJPGD is not set
# CONFIG_PKG_USING_PDFGEN is not set
# CONFIG_PKG_USING_HELIX is not set
# CONFIG_PKG_USING_AZUREGUIX is not set
# CONFIG_PKG_USING_TOUCHGFX2RTT is not set
# CONFIG_PKG_USING_NUEMWIN is not set
# CONFIG_PKG_USING_MP3PLAYER is not set
# CONFIG_PKG_USING_TINYJPEG is not set
# CONFIG_PKG_USING_UGUI is not set
#
# PainterEngine: A cross-platform graphics application framework written in C language
#
# CONFIG_PKG_USING_PAINTERENGINE is not set
# CONFIG_PKG_USING_PAINTERENGINE_AUX is not set
# CONFIG_PKG_USING_MCURSES is not set
# CONFIG_PKG_USING_TERMBOX is not set
# CONFIG_PKG_USING_VT100 is not set
# CONFIG_PKG_USING_QRCODE is not set
# CONFIG_PKG_USING_GUIENGINE is not set
# CONFIG_PKG_USING_PERSIMMON is not set
#
# tools packages
#
# CONFIG_PKG_USING_CMBACKTRACE is not set
# CONFIG_PKG_USING_EASYFLASH is not set
# CONFIG_PKG_USING_EASYLOGGER is not set
# CONFIG_PKG_USING_SYSTEMVIEW is not set
# CONFIG_PKG_USING_SEGGER_RTT is not set
# CONFIG_PKG_USING_RDB is not set
# CONFIG_PKG_USING_ULOG_EASYFLASH is not set
# CONFIG_PKG_USING_ULOG_FILE is not set
# CONFIG_PKG_USING_LOGMGR is not set
# CONFIG_PKG_USING_ADBD is not set
# CONFIG_PKG_USING_COREMARK is not set
# CONFIG_PKG_USING_DHRYSTONE is not set
# CONFIG_PKG_USING_MEMORYPERF is not set
# CONFIG_PKG_USING_NR_MICRO_SHELL is not set
# CONFIG_PKG_USING_CHINESE_FONT_LIBRARY is not set
# CONFIG_PKG_USING_LUNAR_CALENDAR is not set
# CONFIG_PKG_USING_BS8116A is not set
# CONFIG_PKG_USING_GPS_RMC is not set
# CONFIG_PKG_USING_URLENCODE is not set
# CONFIG_PKG_USING_UMCN is not set
# CONFIG_PKG_USING_LWRB2RTT is not set
# CONFIG_PKG_USING_CPU_USAGE is not set
# CONFIG_PKG_USING_GBK2UTF8 is not set
# CONFIG_PKG_USING_VCONSOLE is not set
# CONFIG_PKG_USING_KDB is not set
# CONFIG_PKG_USING_WAMR is not set
# CONFIG_PKG_USING_MICRO_XRCE_DDS_CLIENT is not set
# CONFIG_PKG_USING_LWLOG is not set
# CONFIG_PKG_USING_ANV_TRACE is not set
# CONFIG_PKG_USING_ANV_MEMLEAK is not set
# CONFIG_PKG_USING_ANV_TESTSUIT is not set
# CONFIG_PKG_USING_ANV_BENCH is not set
# CONFIG_PKG_USING_DEVMEM is not set
# CONFIG_PKG_USING_REGEX is not set
# CONFIG_PKG_USING_MEM_SANDBOX is not set
# CONFIG_PKG_USING_SOLAR_TERMS is not set
# CONFIG_PKG_USING_GAN_ZHI is not set
# CONFIG_PKG_USING_FDT is not set
# CONFIG_PKG_USING_CBOX is not set
# CONFIG_PKG_USING_SNOWFLAKE is not set
# CONFIG_PKG_USING_HASH_MATCH is not set
#
# system packages
#
#
# enhanced kernel services
#
# CONFIG_PKG_USING_RT_MEMCPY_CM is not set
# CONFIG_PKG_USING_RT_KPRINTF_THREADSAFE is not set
# CONFIG_PKG_USING_RT_VSNPRINTF_FULL is not set
#
# POSIX extension functions
#
# CONFIG_PKG_USING_POSIX_GETLINE is not set
# CONFIG_PKG_USING_POSIX_WCWIDTH is not set
# CONFIG_PKG_USING_POSIX_ITOA is not set
# CONFIG_PKG_USING_POSIX_STRINGS is not set
#
# acceleration: Assembly language or algorithmic acceleration packages
#
# CONFIG_PKG_USING_QFPLIB_M0_FULL is not set
# CONFIG_PKG_USING_QFPLIB_M0_TINY is not set
# CONFIG_PKG_USING_QFPLIB_M3 is not set
#
# CMSIS: ARM Cortex-M Microcontroller Software Interface Standard
#
# CONFIG_PKG_USING_CMSIS_5 is not set
# CONFIG_PKG_USING_CMSIS_RTOS2 is not set
#
# Micrium: Micrium software products porting for RT-Thread
#
# CONFIG_PKG_USING_UCOSIII_WRAPPER is not set
# CONFIG_PKG_USING_UCOSII_WRAPPER is not set
# CONFIG_PKG_USING_UC_CRC is not set
# CONFIG_PKG_USING_UC_CLK is not set
# CONFIG_PKG_USING_UC_COMMON is not set
# CONFIG_PKG_USING_UC_MODBUS is not set
# CONFIG_PKG_USING_RTDUINO is not set
# CONFIG_PKG_USING_CAIRO is not set
# CONFIG_PKG_USING_PIXMAN is not set
# CONFIG_PKG_USING_PARTITION is not set
# CONFIG_PKG_USING_FLASHDB is not set
# CONFIG_PKG_USING_SQLITE is not set
# CONFIG_PKG_USING_RTI is not set
# CONFIG_PKG_USING_DFS_YAFFS is not set
# CONFIG_PKG_USING_LITTLEFS is not set
# CONFIG_PKG_USING_DFS_JFFS2 is not set
# CONFIG_PKG_USING_DFS_UFFS is not set
# CONFIG_PKG_USING_LWEXT4 is not set
# CONFIG_PKG_USING_THREAD_POOL is not set
# CONFIG_PKG_USING_ROBOTS is not set
# CONFIG_PKG_USING_EV is not set
# CONFIG_PKG_USING_SYSWATCH is not set
# CONFIG_PKG_USING_SYS_LOAD_MONITOR is not set
# CONFIG_PKG_USING_PLCCORE is not set
# CONFIG_PKG_USING_RAMDISK is not set
# CONFIG_PKG_USING_MININI is not set
# CONFIG_PKG_USING_QBOOT is not set
# CONFIG_PKG_USING_PPOOL is not set
# CONFIG_PKG_USING_OPENAMP is not set
# CONFIG_PKG_USING_LPM is not set
# CONFIG_PKG_USING_TLSF is not set
# CONFIG_PKG_USING_EVENT_RECORDER is not set
# CONFIG_PKG_USING_ARM_2D is not set
# CONFIG_PKG_USING_MCUBOOT is not set
# CONFIG_PKG_USING_TINYUSB is not set
# CONFIG_PKG_USING_CHERRYUSB is not set
# CONFIG_PKG_USING_KMULTI_RTIMER is not set
# CONFIG_PKG_USING_TFDB is not set
#
# peripheral libraries and drivers
#
# CONFIG_PKG_USING_SENSORS_DRIVERS is not set
# CONFIG_PKG_USING_REALTEK_AMEBA is not set
# CONFIG_PKG_USING_SHT2X is not set
# CONFIG_PKG_USING_SHT3X is not set
# CONFIG_PKG_USING_AS7341 is not set
# CONFIG_PKG_USING_STM32_SDIO is not set
# CONFIG_PKG_USING_ICM20608 is not set
# CONFIG_PKG_USING_BUTTON is not set
# CONFIG_PKG_USING_PCF8574 is not set
# CONFIG_PKG_USING_SX12XX is not set
# CONFIG_PKG_USING_SIGNAL_LED is not set
# CONFIG_PKG_USING_LEDBLINK is not set
# CONFIG_PKG_USING_LITTLED is not set
# CONFIG_PKG_USING_LKDGUI is not set
# CONFIG_PKG_USING_NRF5X_SDK is not set
# CONFIG_PKG_USING_NRFX is not set
# CONFIG_PKG_USING_WM_LIBRARIES is not set
# CONFIG_PKG_USING_KENDRYTE_SDK is not set
# CONFIG_PKG_USING_INFRARED is not set
# CONFIG_PKG_USING_MULTI_INFRARED is not set
# CONFIG_PKG_USING_AGILE_BUTTON is not set
# CONFIG_PKG_USING_AGILE_LED is not set
# CONFIG_PKG_USING_AT24CXX is not set
# CONFIG_PKG_USING_MOTIONDRIVER2RTT is not set
# CONFIG_PKG_USING_AD7746 is not set
# CONFIG_PKG_USING_PCA9685 is not set
# CONFIG_PKG_USING_I2C_TOOLS is not set
# CONFIG_PKG_USING_NRF24L01 is not set
# CONFIG_PKG_USING_TOUCH_DRIVERS is not set
# CONFIG_PKG_USING_MAX17048 is not set
# CONFIG_PKG_USING_RPLIDAR is not set
# CONFIG_PKG_USING_AS608 is not set
# CONFIG_PKG_USING_RC522 is not set
# CONFIG_PKG_USING_WS2812B is not set
# CONFIG_PKG_USING_EMBARC_BSP is not set
# CONFIG_PKG_USING_EXTERN_RTC_DRIVERS is not set
# CONFIG_PKG_USING_MULTI_RTIMER is not set
# CONFIG_PKG_USING_MAX7219 is not set
# CONFIG_PKG_USING_BEEP is not set
# CONFIG_PKG_USING_EASYBLINK is not set
# CONFIG_PKG_USING_PMS_SERIES is not set
# CONFIG_PKG_USING_CAN_YMODEM is not set
# CONFIG_PKG_USING_LORA_RADIO_DRIVER is not set
# CONFIG_PKG_USING_QLED is not set
# CONFIG_PKG_USING_PAJ7620 is not set
# CONFIG_PKG_USING_AGILE_CONSOLE is not set
# CONFIG_PKG_USING_LD3320 is not set
# CONFIG_PKG_USING_WK2124 is not set
# CONFIG_PKG_USING_LY68L6400 is not set
# CONFIG_PKG_USING_DM9051 is not set
# CONFIG_PKG_USING_SSD1306 is not set
# CONFIG_PKG_USING_QKEY is not set
# CONFIG_PKG_USING_RS485 is not set
# CONFIG_PKG_USING_RS232 is not set
# CONFIG_PKG_USING_NES is not set
# CONFIG_PKG_USING_VIRTUAL_SENSOR is not set
# CONFIG_PKG_USING_VDEVICE is not set
# CONFIG_PKG_USING_SGM706 is not set
# CONFIG_PKG_USING_STM32WB55_SDK is not set
# CONFIG_PKG_USING_RDA58XX is not set
# CONFIG_PKG_USING_LIBNFC is not set
# CONFIG_PKG_USING_MFOC is not set
# CONFIG_PKG_USING_TMC51XX is not set
# CONFIG_PKG_USING_TCA9534 is not set
# CONFIG_PKG_USING_KOBUKI is not set
# CONFIG_PKG_USING_ROSSERIAL is not set
# CONFIG_PKG_USING_MICRO_ROS is not set
# CONFIG_PKG_USING_MCP23008 is not set
# CONFIG_PKG_USING_BLUETRUM_SDK is not set
# CONFIG_PKG_USING_MISAKA_AT24CXX is not set
# CONFIG_PKG_USING_MISAKA_RGB_BLING is not set
# CONFIG_PKG_USING_LORA_MODEM_DRIVER is not set
# CONFIG_PKG_USING_BL_MCU_SDK is not set
# CONFIG_PKG_USING_SOFT_SERIAL is not set
# CONFIG_PKG_USING_MB85RS16 is not set
# CONFIG_PKG_USING_CW2015 is not set
# CONFIG_PKG_USING_RFM300 is not set
#
# AI packages
#
# CONFIG_PKG_USING_LIBANN is not set
# CONFIG_PKG_USING_NNOM is not set
# CONFIG_PKG_USING_ONNX_BACKEND is not set
# CONFIG_PKG_USING_ONNX_PARSER is not set
# CONFIG_PKG_USING_TENSORFLOWLITEMICRO is not set
# CONFIG_PKG_USING_ELAPACK is not set
# CONFIG_PKG_USING_ULAPACK is not set
# CONFIG_PKG_USING_QUEST is not set
# CONFIG_PKG_USING_NAXOS is not set
#
# miscellaneous packages
#
#
# project laboratory
#
#
# samples: kernel and components samples
#
# CONFIG_PKG_USING_KERNEL_SAMPLES is not set
# CONFIG_PKG_USING_FILESYSTEM_SAMPLES is not set
# CONFIG_PKG_USING_NETWORK_SAMPLES is not set
# CONFIG_PKG_USING_PERIPHERAL_SAMPLES is not set
#
# entertainment: terminal games and other interesting software packages
#
# CONFIG_PKG_USING_CMATRIX is not set
# CONFIG_PKG_USING_SL is not set
# CONFIG_PKG_USING_CAL is not set
# CONFIG_PKG_USING_ACLOCK is not set
# CONFIG_PKG_USING_THREES is not set
# CONFIG_PKG_USING_2048 is not set
# CONFIG_PKG_USING_SNAKE is not set
# CONFIG_PKG_USING_TETRIS is not set
# CONFIG_PKG_USING_DONUT is not set
# CONFIG_PKG_USING_COWSAY is not set
# CONFIG_PKG_USING_LIBCSV is not set
# CONFIG_PKG_USING_OPTPARSE is not set
# CONFIG_PKG_USING_FASTLZ is not set
# CONFIG_PKG_USING_MINILZO is not set
# CONFIG_PKG_USING_QUICKLZ is not set
# CONFIG_PKG_USING_LZMA is not set
# CONFIG_PKG_USING_MULTIBUTTON is not set
# CONFIG_PKG_USING_FLEXIBLE_BUTTON is not set
# CONFIG_PKG_USING_CANFESTIVAL is not set
# CONFIG_PKG_USING_ZLIB is not set
# CONFIG_PKG_USING_MINIZIP is not set
# CONFIG_PKG_USING_HEATSHRINK is not set
# CONFIG_PKG_USING_DSTR is not set
# CONFIG_PKG_USING_TINYFRAME is not set
# CONFIG_PKG_USING_KENDRYTE_DEMO is not set
# CONFIG_PKG_USING_DIGITALCTRL is not set
# CONFIG_PKG_USING_UPACKER is not set
# CONFIG_PKG_USING_UPARAM is not set
# CONFIG_PKG_USING_HELLO is not set
# CONFIG_PKG_USING_VI is not set
# CONFIG_PKG_USING_KI is not set
# CONFIG_PKG_USING_ARMv7M_DWT is not set
# CONFIG_PKG_USING_UKAL is not set
# CONFIG_PKG_USING_CRCLIB is not set
# CONFIG_PKG_USING_LWGPS is not set
# CONFIG_PKG_USING_STATE_MACHINE is not set
# CONFIG_PKG_USING_DESIGN_PATTERN is not set
# CONFIG_PKG_USING_CONTROLLER is not set
# CONFIG_PKG_USING_PHASE_LOCKED_LOOP is not set
# CONFIG_PKG_USING_MFBD is not set
CONFIG_SOC_FAMILY_HC32=y
CONFIG_SOC_SERIES_HC32F4=y
#
# Hardware Drivers Config
#
CONFIG_SOC_HC32F4A0SI=y
#
# Onboard Peripheral Drivers
#
# CONFIG_BSP_USING_ETH is not set
# CONFIG_BSP_USING_TCA9539 is not set
# CONFIG_BSP_USING_SPI_FLASH is not set
#
# On-chip Peripheral Drivers
#
CONFIG_BSP_USING_GPIO=y
CONFIG_BSP_USING_UART=y
CONFIG_BSP_USING_UART1=y
# CONFIG_BSP_UART1_RX_USING_DMA is not set
# CONFIG_BSP_UART1_TX_USING_DMA is not set
# CONFIG_BSP_USING_UART2 is not set
# CONFIG_BSP_USING_UART3 is not set
# CONFIG_BSP_USING_UART4 is not set
# CONFIG_BSP_USING_UART5 is not set
# CONFIG_BSP_USING_UART6 is not set
# CONFIG_BSP_USING_UART7 is not set
# CONFIG_BSP_USING_UART8 is not set
# CONFIG_BSP_USING_UART9 is not set
# CONFIG_BSP_USING_UART10 is not set
# CONFIG_BSP_USING_I2C1 is not set
# CONFIG_BSP_USING_SPI is not set
# CONFIG_BSP_USING_RTC is not set
# CONFIG_BSP_USING_PWM is not set
# CONFIG_BSP_USING_TIMER is not set
# CONFIG_BSP_USING_PULSE_ENCODER is not set
# CONFIG_BSP_USING_ADC is not set
# CONFIG_BSP_USING_CAN is not set
#
# Board extended module Drivers
#

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*.pyc
*.map
*.dblite
*.elf
*.bin
*.hex
*.axf
*.exe
*.pdb
*.idb
*.ilk
*.old
build
Debug
documentation/html
packages/
*~
*.o
*.obj
*.out
*.bak
*.dep
*.lib
*.i
*.d
.DS_Stor*
.config 3
.config 4
.config 5
Midea-X1
*.uimg
GPATH
GRTAGS
GTAGS
.vscode
JLinkLog.txt
JLinkSettings.ini
DebugConfig/
RTE/
settings/
*.uvguix*
cconfig.h

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mainmenu "RT-Thread Configuration"
config BSP_DIR
string
option env="BSP_ROOT"
default "."
config RTT_DIR
string
option env="RTT_ROOT"
default "../../.."
config PKGS_DIR
string
option env="PKGS_ROOT"
default "packages"
source "$RTT_DIR/Kconfig"
source "$PKGS_DIR/Kconfig"
source "../libraries/Kconfig"
source "board/Kconfig"

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# XHSC EV_F4A0_LQ176 开发板 BSP 说明
## 简介
本文档为小华半导体为 EV_F4A0_LQ176 开发板提供的 BSP (板级支持包) 说明。
主要内容如下：
- 开发板资源介绍
- BSP 快速上手
- 进阶使用方法
通过阅读快速上手章节开发者可以快速地上手该 BSP，将 RT-Thread 运行在开发板上。在进阶使用指南章节，将会介绍更多高级功能，帮助开发者利用 RT-Thread 驱动更多板载资源。
## 开发板介绍
EV_F4A0_LQ176 是 XHSC 官方推出的开发板，搭载 HC32F4A0SITB 芯片，基于 ARM Cortex-M4 内核，最高主频 240 MHz，具有丰富的板载资源，可以充分发挥 HC32F4A0SITB 的芯片性能。
开发板外观如下图所示：
![board](figures/board.jpg)
EV_F4A0_LQ176 开发板常用 **板载资源** 如下：
- MCU：HC32F4A0SITB，主频240MHz，2048KB FLASH，512KB RAM
- 外部RAM：IS62WV51216(SRAM, 1MB) IS42S16400J(SDRAM, 8MB)
- 外部FLASH: MT29F2G08AB(Nand, 256MB) W25Q64(SPI NOR, 64MB)
- 常用外设
- LED：3 个， user LED(LED0,LED1,LED2)。
- 按键：11 个，矩阵键盘(K1~K9)、WAKEUP(K10)、RESET(K11)。
- 常用接口：USB转串口、SD卡接口、以太网接口、LCD接口、USB HS、USB FS、USB 3300、DVP接口、3.5mm耳机接口、Line in接口、喇叭接口
- 调试接口：板载DAP调试器、标准JTAG/SWD。
开发板更多详细信息请参考小华半导体半导体[EV_F4A0_LQ176](http://www.xhsc.com.cn)
## 外设支持
本 BSP 目前对外设的支持情况如下：
| **板载外设** | **支持情况** | **备注** |
| :------------ | :-----------: | :-----------------------------------: |
| USB 转串口 | 支持 | 使用 UART1 |
| SPI Flash | 支持 | 使用 SPI1 |
| LED | 支持 | LED |
| **片上外设** | **支持情况** | **备注** |
| :------------ | :-----------: | :-----------------------------------: |
| GPIO | 支持 | PA0, PA1... PI13 ---> PIN: 0, 1...141 |
| UART | 支持 | UART1~10 |
| SPI | 支持 | SPI1~6 |
| I2C | 支持 | 软件 I2C |
| RTC | 支持 | 支持外部晶振和内部低速时钟 |
| PWM | 支持 | |
| HWTIMER | 支持 | |
| LED | 支持 | LED11 |
## 使用说明
使用说明分为如下两个章节：
- 快速上手
本章节是为刚接触 RT-Thread 的新手准备的使用说明，遵循简单的步骤即可将 RT-Thread 操作系统运行在该开发板上，看到实验效果 。
- 进阶使用
本章节是为需要在 RT-Thread 操作系统上使用更多开发板资源的开发者准备的。通过使用 ENV 工具对 BSP 进行配置，可以开启更多板载资源，实现更多高级功能。
### 快速上手
本 BSP 为开发者提供 MDK5 和 IAR 工程，并且支持 GCC 开发环境。下面以 MDK5 开发环境为例，介绍如何将系统运行起来。
#### 硬件连接
使用Type-A to MircoUSB线连接开发板和PC供电。
#### 编译下载
双击 project.uvprojx 文件，打开 MDK5 工程，编译并下载程序到开发板。
> 工程默认配置使用 J-LINK 下载程序，点击下载按钮即可下载程序到开发板。
#### 运行结果
下载程序成功之后，系统会自动运行，观察开发板上LED的运行效果，绿色LED11会周期性闪烁。
USB虚拟COM端口默认连接串口1，在终端工具里打开相应的串口，复位设备后，可以看到 RT-Thread 的输出信息:
```
\ | /
- RT - Thread Operating System
/ | \ 4.1.0 build Apr 24 2022 13:32:39
2006 - 2022 Copyright by RT-Thread team
msh >
```
### 进阶使用
此 BSP 默认只开启了 GPIO 和 串口 1 的功能，更多高级功能需要利用 env 工具对 BSP 进行配置，步骤如下：
1. 在 bsp 下打开 env 工具。
2. 输入`menuconfig`命令配置工程，配置好之后保存退出。
3. 输入`pkgs --update`命令更新软件包。
4. 输入`scons --target=mdk5/iar` 命令重新生成工程。
## 注意事项
## 联系人信息
维护人:
- [小华半导体MCU](http://www.xhsc.com.cn)，邮箱：<mcu_eco@xhsc.com.cn>

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# for module compiling
import os
Import('RTT_ROOT')
from building import *
cwd = GetCurrentDir()
objs = []
list = os.listdir(cwd)
for d in list:
path = os.path.join(cwd, d)
if os.path.isfile(os.path.join(path, 'SConscript')):
objs = objs + SConscript(os.path.join(d, 'SConscript'))
Return('objs')

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import os
import sys
import rtconfig
if os.getenv('RTT_ROOT'):
RTT_ROOT = os.getenv('RTT_ROOT')
else:
RTT_ROOT = os.path.normpath(os.getcwd() + '/../../..')
sys.path = sys.path + [os.path.join(RTT_ROOT, 'tools')]
try:
from building import *
except:
print('Cannot found RT-Thread root directory, please check RTT_ROOT')
print(RTT_ROOT)
exit(-1)
TARGET = 'rtthread.' + rtconfig.TARGET_EXT
DefaultEnvironment(tools=[])
env = Environment(tools = ['mingw'],
AS = rtconfig.AS, ASFLAGS = rtconfig.AFLAGS,
CC = rtconfig.CC, CCFLAGS = rtconfig.CFLAGS,
AR = rtconfig.AR, ARFLAGS = '-rc',
CXX = rtconfig.CXX, CXXFLAGS = rtconfig.CXXFLAGS,
LINK = rtconfig.LINK, LINKFLAGS = rtconfig.LFLAGS)
env.PrependENVPath('PATH', rtconfig.EXEC_PATH)
if rtconfig.PLATFORM == 'iar':
env.Replace(CCCOM = ['$CC $CCFLAGS $CPPFLAGS $_CPPDEFFLAGS $_CPPINCFLAGS -o $TARGET $SOURCES'])
env.Replace(ARFLAGS = [''])
env.Replace(LINKCOM = env["LINKCOM"] + ' --map rtthread.map')
Export('RTT_ROOT')
Export('rtconfig')
SDK_ROOT = os.path.abspath('./')
if os.path.exists(SDK_ROOT + '/libraries'):
libraries_path_prefix = SDK_ROOT + '/libraries'
else:
libraries_path_prefix = os.path.dirname(SDK_ROOT) + '/libraries'
SDK_LIB = libraries_path_prefix
Export('SDK_LIB')
# prepare building environment
objs = PrepareBuilding(env, RTT_ROOT, has_libcpu=False)
hc32_library = 'hc32f4a0_ddl'
rtconfig.BSP_LIBRARY_TYPE = hc32_library
# include libraries
objs.extend(SConscript(os.path.join(libraries_path_prefix, hc32_library, 'SConscript')))
# include drivers
objs.extend(SConscript(os.path.join(libraries_path_prefix, 'hc32_drivers', 'SConscript')))
# make a building
DoBuilding(TARGET, objs)

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Import('RTT_ROOT')
Import('rtconfig')
from building import *
cwd = os.path.join(str(Dir('#')), 'applications')
src = Glob('*.c')
CPPPATH = [cwd, str(Dir('#'))]
group = DefineGroup('Applications', src, depend = [''], CPPPATH = CPPPATH)
Return('group')

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/*
* Copyright (C) 2022, Xiaohua Semiconductor Co., Ltd.
*
* SPDX-License-Identifier: Apache-2.0
*
* Change Logs:
* Date Author Notes
* 2022-04-28 CDT first version
*/
#include <rtthread.h>
#include <rtdevice.h>
#include <board.h>
/* defined the LED_GREEN pin: PC9 */
#define LED_GREEN_PIN GET_PIN(C, 9)
int main(void)
{
/* set LED_GREEN_PIN pin mode to output */
rt_pin_mode(LED_GREEN_PIN, PIN_MODE_OUTPUT);
while (1)
{
rt_pin_write(LED_GREEN_PIN, PIN_HIGH);
rt_thread_mdelay(500);
rt_pin_write(LED_GREEN_PIN, PIN_LOW);
rt_thread_mdelay(500);
}
}

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menu "Hardware Drivers Config"
config SOC_HC32F4A0SI
bool
select SOC_SERIES_HC32F4
select RT_USING_COMPONENTS_INIT
select RT_USING_USER_MAIN
default y
menu "Onboard Peripheral Drivers"
config PHY_USING_RTL8201F
bool
menuconfig BSP_USING_ETH
bool "Enable Ethernet"
default n
select BSP_USING_I2C1
select RT_USING_LWIP
select PHY_USING_RTL8201F
select RT_LWIP_USING_HW_CHECKSUM
select BSP_USING_TCA9539
if BSP_USING_ETH
config ETH_USING_INTERFACE_RMII
bool "select RMII interface"
default n
config PHY_USING_INTERRUPT_MODE
bool "enable phy interrupt mode"
select ETH_PHY_INT_PIN
default n
config ETH_PHY_INT_PIN
int
default 16
endif
config BSP_USING_TCA9539
bool "Enable TCA9539"
select BSP_USING_I2C1
default n
config BSP_USING_SPI_FLASH
bool "Enable SPI FLASH (spi1)"
select BSP_USING_SPI
select BSP_USING_SPI1
default n
endmenu
menu "On-chip Peripheral Drivers"
config BSP_USING_GPIO
bool "Enable GPIO"
select RT_USING_PIN
default y
menuconfig BSP_USING_UART
bool "Enable UART"
default y
select RT_USING_SERIAL
if BSP_USING_UART
config BSP_USING_UART1
bool "Enable UART1"
default y
config BSP_UART1_RX_USING_DMA
bool "Enable UART1 RX DMA"
depends on BSP_USING_UART1 && RT_SERIAL_USING_DMA
default n
config BSP_UART1_TX_USING_DMA
bool "Enable UART1 TX DMA"
depends on BSP_USING_UART1 && RT_SERIAL_USING_DMA
default n
config BSP_USING_UART2
bool "Enable UART2"
default n
config BSP_UART2_RX_USING_DMA
bool "Enable UART2 RX DMA"
depends on BSP_USING_UART2 && RT_SERIAL_USING_DMA
default n
config BSP_UART2_TX_USING_DMA
bool "Enable UART2 TX DMA"
depends on BSP_USING_UART2 && RT_SERIAL_USING_DMA
default n
config BSP_USING_UART3
bool "Enable UART3"
default n
config BSP_USING_UART4
bool "Enable UART4"
default n
config BSP_USING_UART5
bool "Enable UART5"
default n
config BSP_USING_UART6
bool "Enable UART6"
default n
config BSP_UART6_RX_USING_DMA
bool "Enable UART6 RX DMA"
depends on BSP_USING_UART6 && RT_SERIAL_USING_DMA
default n
config BSP_UART6_TX_USING_DMA
bool "Enable UART6 TX DMA"
depends on BSP_USING_UART6 && RT_SERIAL_USING_DMA
default n
config BSP_USING_UART7
bool "Enable UART7"
default n
config BSP_UART7_RX_USING_DMA
bool "Enable UART7 RX DMA"
depends on BSP_USING_UART7 && RT_SERIAL_USING_DMA
default n
config BSP_UART7_TX_USING_DMA
bool "Enable UART7 TX DMA"
depends on BSP_USING_UART7 && RT_SERIAL_USING_DMA
default n
config BSP_USING_UART8
bool "Enable UART8"
default n
config BSP_USING_UART9
bool "Enable UART9"
default n
config BSP_USING_UART10
bool "Enable UART10"
default n
endif
menuconfig BSP_USING_I2C1
bool "Enable I2C1 BUS (software simulation)"
default y
select RT_USING_I2C
select RT_USING_I2C_BITOPS
select RT_USING_PIN
if BSP_USING_I2C1
config BSP_I2C1_SCL_PIN
int "i2c1 scl pin number"
range 1 176
default 51
config BSP_I2C1_SDA_PIN
int "I2C1 sda pin number"
range 1 176
default 90
endif
menuconfig BSP_USING_SPI
bool "Enable SPI BUS"
default n
select RT_USING_SPI
if BSP_USING_SPI
config BSP_USING_SPI1
bool "Enable SPI1 BUS"
default n
config BSP_SPI1_TX_USING_DMA
bool "Enable SPI1 TX DMA"
depends on BSP_USING_SPI1
default n
config BSP_SPI1_RX_USING_DMA
bool "Enable SPI1 RX DMA"
depends on BSP_USING_SPI1
select BSP_SPI1_TX_USING_DMA
default n
config BSP_USING_SPI2
bool "Enable SPI2 BUS"
default n
config BSP_SPI2_TX_USING_DMA
bool "Enable SPI2 TX DMA"
depends on BSP_USING_SPI2
default n
config BSP_SPI2_RX_USING_DMA
bool "Enable SPI2 RX DMA"
depends on BSP_USING_SPI2
select BSP_SPI2_TX_USING_DMA
default n
config BSP_USING_SPI3
bool "Enable SPI3 BUS"
default n
config BSP_SPI3_TX_USING_DMA
bool "Enable SPI3 TX DMA"
depends on BSP_USING_SPI3
default n
config BSP_SPI3_RX_USING_DMA
bool "Enable SPI3 RX DMA"
depends on BSP_USING_SPI3
select BSP_SPI3_TX_USING_DMA
default n
config BSP_USING_SPI4
bool "Enable SPI4 BUS"
default n
config BSP_SPI4_TX_USING_DMA
bool "Enable SPI4 TX DMA"
depends on BSP_USING_SPI4
default n
config BSP_SPI4_RX_USING_DMA
bool "Enable SPI4 RX DMA"
depends on BSP_USING_SPI4
select BSP_SPI4_TX_USING_DMA
default n
endif
menuconfig BSP_USING_RTC
bool "Enable RTC"
select RT_USING_RTC
default n
if BSP_USING_RTC
choice
prompt "Select clock source"
default BSP_RTC_USING_LRC
config BSP_RTC_USING_XTAL32
bool "RTC USING XTAL32"
config BSP_RTC_USING_LRC
bool "RTC USING LRC"
endchoice
endif
menuconfig BSP_USING_PWM
bool "Enable PWM"
default n
select RT_USING_PWM
if BSP_USING_PWM
menuconfig BSP_USING_PWM1
bool "Enable timer1 output PWM"
default n
if BSP_USING_PWM1
config BSP_USING_PWM1_CH1
bool "Enable PWM1 channel1"
default n
config BSP_USING_PWM1_CH2
bool "Enable PWM1 channel2"
default n
config BSP_USING_PWM1_CH3
bool "Enable PWM1 channel3"
default n
config BSP_USING_PWM1_CH4
bool "Enable PWM1 channel4"
default n
endif
menuconfig BSP_USING_PWM2
bool "Enable timer2 output PWM"
default n
if BSP_USING_PWM2
config BSP_USING_PWM2_CH1
bool "Enable PWM2 channel1"
default n
config BSP_USING_PWM2_CH2
bool "Enable PWM2 channel2"
default n
config BSP_USING_PWM2_CH3
bool "Enable PWM2 channel3"
default n
config BSP_USING_PWM2_CH4
bool "Enable PWM2 channel4"
default n
endif
endif
menuconfig BSP_USING_TIMER
bool "Enable TIMER"
default n
select RT_USING_HWTIMER
if BSP_USING_TIMER
config BSP_USING_TIMER5
bool "Enable TIMER5"
default n
config BSP_USING_TIMER6
bool "Enable TIMER6"
default n
config BSP_USING_TIMER7
bool "Enable TIMER7"
default n
config BSP_USING_TIMER8
bool "Enable TIMER8"
default n
endif
menuconfig BSP_USING_PULSE_ENCODER
bool "Enable Pulse Encoder"
default n
select RT_USING_PULSE_ENCODER
if BSP_USING_PULSE_ENCODER
config BSP_USING_PULSE_ENCODER9
bool "Enable Pulse Encoder9"
default n
config BSP_USING_PULSE_ENCODER10
bool "Enable Pulse Encoder10"
default n
config BSP_USING_PULSE_ENCODER11
bool "Enable Pulse Encoder11"
default n
config BSP_USING_PULSE_ENCODER12
bool "Enable Pulse Encoder12"
default n
endif
menuconfig BSP_USING_ADC
bool "Enable ADC"
default n
select RT_USING_ADC
if BSP_USING_ADC
config BSP_USING_ADC1
bool "using adc1"
default n
config BSP_USING_ADC2
bool "using adc2"
default n
config BSP_USING_ADC3
bool "using adc3"
default n
endif
menuconfig BSP_USING_CAN
bool "Enable CAN"
default n
select RT_USING_CAN
select BSP_USING_TCA9539
if BSP_USING_CAN
config BSP_USING_CAN1
bool "using can1"
default n
config BSP_USING_CAN2
bool "using can2"
default n
endif
endmenu
menu "Board extended module Drivers"
endmenu
endmenu

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import os
import rtconfig
from building import *
Import('SDK_LIB')
cwd = GetCurrentDir()
# add general drivers
src = Split('''
board.c
board_config.c
''')
if GetDepend(['BSP_USING_TCA9539']):
src += Glob('ports/tca9539.c')
if GetDepend(['BSP_USING_SPI_FLASH']):
src += Glob('ports/spi_flash.c')
path = [cwd]
path += [cwd + '/ports']
startup_path_prefix = SDK_LIB
if rtconfig.CROSS_TOOL == 'gcc':
src += [startup_path_prefix + '/hc32f4a0_ddl/drivers/cmsis/Device/HDSC/hc32f4xx/Source/GCC/startup_hc32f4a0.S']
elif rtconfig.CROSS_TOOL == 'keil':
src += [startup_path_prefix + '/hc32f4a0_ddl/drivers/cmsis/Device/HDSC/hc32f4xx/Source/ARM/startup_hc32f4a0.s']
elif rtconfig.CROSS_TOOL == 'iar':
src += [startup_path_prefix + '/hc32f4a0_ddl/drivers/cmsis/Device/HDSC/hc32f4xx/Source/IAR/startup_hc32f4a0.s']
CPPDEFINES = ['HC32F4A0']
group = DefineGroup('Drivers', src, depend = [''], CPPPATH = path, CPPDEFINES = CPPDEFINES)
Return('group')

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/*
* Copyright (C) 2022, Xiaohua Semiconductor Co., Ltd.
*
* SPDX-License-Identifier: Apache-2.0
*
* Change Logs:
* Date Author Notes
* 2022-04-28 CDT first version
*/
#include "board.h"
/* unlock/lock peripheral */
#define EXAMPLE_PERIPH_WE (LL_PERIPH_GPIO | LL_PERIPH_EFM | LL_PERIPH_FCG | \
LL_PERIPH_PWC_CLK_RMU | LL_PERIPH_SRAM)
#define EXAMPLE_PERIPH_WP (LL_PERIPH_EFM | LL_PERIPH_FCG | LL_PERIPH_SRAM)
/**
* @brief This function is executed in case of error occurrence.
* @param None
* @retval None
*/
void Error_Handler(void)
{
/* USER CODE BEGIN Error_Handler */
/* User can add his own implementation to report the HAL error return state */
while (1)
{
}
/* USER CODE END Error_Handler */
}
/** System Clock Configuration
*/
void SystemClock_Config(void)
{
stc_clock_xtal_init_t stcXtalInit;
stc_clock_pll_init_t stcPLLHInit;
/* PCLK0, HCLK Max 240MHz */
/* PCLK1, PCLK4 Max 120MHz */
/* PCLK2, PCLK3 Max 60MHz */
/* EX BUS Max 120MHz */
CLK_SetClockDiv(CLK_BUS_CLK_ALL, \
(CLK_PCLK0_DIV1 | CLK_PCLK1_DIV2 | CLK_PCLK2_DIV4 | \
CLK_PCLK3_DIV4 | CLK_PCLK4_DIV2 | CLK_EXCLK_DIV2 | \
CLK_HCLK_DIV1));
(void)CLK_XtalStructInit(&stcXtalInit);
/* Config Xtal and enable Xtal */
stcXtalInit.u8Mode = CLK_XTAL_MD_OSC;
stcXtalInit.u8Drv = CLK_XTAL_DRV_ULOW;
stcXtalInit.u8State = CLK_XTAL_ON;
stcXtalInit.u8StableTime = CLK_XTAL_STB_2MS;
(void)CLK_XtalInit(&stcXtalInit);
(void)CLK_PLLStructInit(&stcPLLHInit);
/* VCO = (8/1)*120 = 960MHz*/
stcPLLHInit.u8PLLState = CLK_PLL_ON;
stcPLLHInit.PLLCFGR = 0UL;
stcPLLHInit.PLLCFGR_f.PLLM = 1UL - 1UL;
stcPLLHInit.PLLCFGR_f.PLLN = 120UL - 1UL;
stcPLLHInit.PLLCFGR_f.PLLP = 4UL - 1UL;
stcPLLHInit.PLLCFGR_f.PLLQ = 4UL - 1UL;
stcPLLHInit.PLLCFGR_f.PLLR = 4UL - 1UL;
stcPLLHInit.PLLCFGR_f.PLLSRC = CLK_PLL_SRC_XTAL;
(void)CLK_PLLInit(&stcPLLHInit);
/* Highspeed SRAM set to 0 Read/Write wait cycle */
SRAM_SetWaitCycle(SRAM_SRAMH, SRAM_WAIT_CYCLE0, SRAM_WAIT_CYCLE0);
/* SRAM1_2_3_4_backup set to 1 Read/Write wait cycle */
SRAM_SetWaitCycle((SRAM_SRAM123 | SRAM_SRAM4 | SRAM_SRAMB), SRAM_WAIT_CYCLE1, SRAM_WAIT_CYCLE1);
/* 0-wait @ 40MHz */
(void)EFM_SetWaitCycle(EFM_WAIT_CYCLE5);
/* 4 cycles for 200 ~ 250MHz */
GPIO_SetReadWaitCycle(GPIO_RD_WAIT4);
CLK_SetSysClockSrc(CLK_SYSCLK_SRC_PLL);
}
/*******************************************************************************
* Function Name : SysTick_Configuration
* Description : Configures the SysTick for OS tick.
* Input : None
* Output : None
* Return : None
*******************************************************************************/
void SysTick_Configuration(void)
{
stc_clock_freq_t stcClkFreq;
rt_uint32_t cnts;
CLK_GetClockFreq(&stcClkFreq);
cnts = (rt_uint32_t)stcClkFreq.u32HclkFreq / RT_TICK_PER_SECOND;
SysTick_Config(cnts);
}
/**
* This is the timer interrupt service routine.
*
*/
void SysTick_Handler(void)
{
/* enter interrupt */
rt_interrupt_enter();
rt_tick_increase();
/* leave interrupt */
rt_interrupt_leave();
}
/**
* This function will initial GD32 board.
*/
void rt_hw_board_init()
{
/* Peripheral registers write unprotected */
LL_PERIPH_WE(EXAMPLE_PERIPH_WE);
SystemClock_Config();
/* Configure the SysTick */
SysTick_Configuration();
/* Heap initialization */
#if defined(RT_USING_HEAP)
rt_system_heap_init((void *)HEAP_BEGIN, (void *)HEAP_END);
#endif
/* Board underlying hardware initialization */
#ifdef RT_USING_COMPONENTS_INIT
rt_components_board_init();
#endif
#if defined(RT_USING_CONSOLE) && defined(RT_USING_DEVICE)
rt_console_set_device(RT_CONSOLE_DEVICE_NAME);
#endif
}
void rt_hw_us_delay(rt_uint32_t us)
{
uint32_t start, now, delta, reload, us_tick;
start = SysTick->VAL;
reload = SysTick->LOAD;
us_tick = SystemCoreClock / 1000000UL;
do
{
now = SysTick->VAL;
delta = start > now ? start - now : reload + start - now;
}
while (delta < us_tick * us);
}
/*@}*/

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/*
* Copyright (C) 2022, Xiaohua Semiconductor Co., Ltd.
*
* SPDX-License-Identifier: Apache-2.0
*
* Change Logs:
* Date Author Notes
* 2022-04-28 CDT first version
*/
#ifndef __BOARD_H__
#define __BOARD_H__
#include <rtthread.h>
#include "hc32_ll.h"
#include "drv_gpio.h"
#ifdef __cplusplus
extern "C" {
#endif
#define HC32_SRAM_SIZE (512)
#define HC32_SRAM_END (0x1FFE0000 + HC32_SRAM_SIZE * 1024)
#ifdef __CC_ARM
extern int Image$$RW_IRAM1$$ZI$$Limit;
#define HEAP_BEGIN (&Image$$RW_IRAM1$$ZI$$Limit)
#elif __ICCARM__
#pragma section="HEAP"
#define HEAP_BEGIN (__segment_end("HEAP"))
#else
extern int __bss_end;
#define HEAP_BEGIN (&__bss_end)
#endif
#define HEAP_END HC32_SRAM_END
#ifdef __cplusplus
}
#endif
#endif

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/*
* Copyright (C) 2022, Xiaohua Semiconductor Co., Ltd.
*
* SPDX-License-Identifier: Apache-2.0
*
* Change Logs:
* Date Author Notes
* 2022-04-28 CDT first version
*/
#include <rtdevice.h>
#include "board_config.h"
#include "tca9539.h"
/**
* The below functions will initialize HC32 board.
*/
#if defined RT_USING_SERIAL
rt_err_t rt_hw_board_uart_init(CM_USART_TypeDef *USARTx)
{
rt_err_t result = RT_EOK;
switch ((rt_uint32_t)USARTx)
{
#if defined(BSP_USING_UART1)
case (rt_uint32_t)CM_USART1:
/* Configure USART RX/TX pin. */
GPIO_SetFunc(USART1_RX_PORT, USART1_RX_PIN, GPIO_FUNC_33);
GPIO_SetFunc(USART1_TX_PORT, USART1_TX_PIN, GPIO_FUNC_32);
break;
#endif
#if defined(BSP_USING_UART6)
case (rt_uint32_t)CM_USART6:
/* Configure USART RX/TX pin. */
GPIO_SetFunc(USART6_RX_PORT, USART6_RX_PIN, GPIO_FUNC_37);
GPIO_SetFunc(USART6_TX_PORT, USART6_TX_PIN, GPIO_FUNC_36);
break;
#endif
default:
result = -RT_ERROR;
break;
}
return result;
}
#endif
#if defined(RT_USING_PWM)
rt_err_t rt_hw_board_pwm_init(CM_TMRA_TypeDef *TMRAx)
{
rt_err_t result = RT_EOK;
switch ((rt_uint32_t)TMRAx)
{
#if defined(BSP_USING_PWM1)
case (rt_uint32_t)CM_TMRA_1:
#if defined(BSP_USING_PWM1_CH1)
GPIO_SetFunc(PWM1_CH1_PORT, PWM1_CH1_PIN, PWM1_CH1_FUNC);
#endif
#if defined(BSP_USING_PWM1_CH2)
GPIO_SetFunc(PWM1_CH2_PORT, PWM1_CH2_PIN, PWM1_CH2_FUNC);
#endif
break;
#endif
default:
result = -RT_ERROR;
break;
}
return result;
}
#endif
#if defined(RT_USING_PULSE_ENCODER)
rt_err_t rt_hw_board_pulse_encoder_init(CM_TMRA_TypeDef *TMRAx)
{
rt_err_t result = RT_EOK;
switch ((rt_uint32_t)TMRAx)
{
#if defined(BSP_USING_PULSE_ENCODER9)
case (rt_uint32_t)CM_TMRA_9:
GPIO_SetFunc(PULSE_ENCODER9_CLKA_PORT, PULSE_ENCODER9_CLKA_PIN, PULSE_ENCODER9_CLKA_FUNC);
GPIO_SetFunc(PULSE_ENCODER9_CLKB_PORT, PULSE_ENCODER9_CLKB_PIN, PULSE_ENCODER9_CLKB_FUNC);
break;
#endif
default:
result = -RT_ERROR;
break;
}
return result;
}
#endif
#if defined(RT_USING_ADC)
void rt_hw_board_adc_clock_init(void)
{
CLK_SetPeriClockSrc(CLK_PERIPHCLK_PCLK);
/* 1. Enable ADC peripheral clock. */
#if defined(BSP_USING_ADC1)
FCG_Fcg3PeriphClockCmd(FCG3_PERIPH_ADC1, ENABLE);
#endif
#if defined(BSP_USING_ADC2)
FCG_Fcg3PeriphClockCmd(FCG3_PERIPH_ADC2, ENABLE);
#endif
#if defined(BSP_USING_ADC3)
FCG_Fcg3PeriphClockCmd(FCG3_PERIPH_ADC3, ENABLE);
#endif
}
rt_err_t rt_hw_board_adc_init(CM_ADC_TypeDef *ADCx)
{
rt_err_t result = RT_EOK;
stc_gpio_init_t stcGpioInit;
(void)GPIO_StructInit(&stcGpioInit);
stcGpioInit.u16PinAttr = PIN_ATTR_ANALOG;
switch ((rt_uint32_t)ADCx)
{
#if defined(BSP_USING_ADC1)
case (rt_uint32_t)CM_ADC1:
(void)GPIO_Init(ADC1_CH_PORT, ADC1_CH_PIN, &stcGpioInit);
break;
#endif
#if defined(BSP_USING_ADC2)
case (rt_uint32_t)CM_ADC2:
(void)GPIO_Init(ADC2_CH_PORT, ADC2_CH_PIN, &stcGpioInit);
break;
#endif
#if defined(BSP_USING_ADC3)
case (rt_uint32_t)CM_ADC3:
(void)GPIO_Init(ADC3_CH_PORT, ADC3_CH_PIN, &stcGpioInit);
break;
#endif
default:
result = -RT_ERROR;
break;
}
return result;
}
#endif
#if defined(RT_USING_CAN)
void CanPhyEnable(void)
{
TCA9539_WritePin(CAN_STB_PORT, CAN_STB_PIN, TCA9539_PIN_RESET);
TCA9539_ConfigPin(CAN_STB_PORT, CAN_STB_PIN, TCA9539_DIR_OUT);
}
rt_err_t rt_hw_board_can_init(CM_CAN_TypeDef *CANx)
{
rt_err_t result = RT_EOK;
switch ((rt_uint32_t)CANx)
{
#if defined(BSP_USING_CAN1)
case (rt_uint32_t)CM_CAN1:
GPIO_SetFunc(CAN1_TX_PORT, CAN1_TX_PIN, CAN1_TX_PIN_FUNC);
GPIO_SetFunc(CAN1_RX_PORT, CAN1_RX_PIN, CAN1_RX_PIN_FUNC);
break;
#endif
#if defined(BSP_USING_CAN2)
case (rt_uint32_t)CM_CAN2:
GPIO_SetFunc(CAN2_TX_PORT, CAN2_TX_PIN, CAN2_TX_PIN_FUNC);
GPIO_SetFunc(CAN2_RX_PORT, CAN2_RX_PIN, CAN2_RX_PIN_FUNC);
break;
#endif
default:
result = -RT_ERROR;
break;
}
return result;
}
#endif
#if defined (RT_USING_SPI)
rt_err_t rt_hw_spi_board_init(CM_SPI_TypeDef *CM_SPIx)
{
rt_err_t result = RT_EOK;
switch ((rt_uint32_t)CM_SPIx)
{
#if defined(BSP_USING_SPI1)
case (rt_uint32_t)CM_SPI1:
GPIO_SetFunc(GPIO_PORT_C, GPIO_PIN_06, GPIO_FUNC_40); /* SCK */
GPIO_SetFunc(GPIO_PORT_B, GPIO_PIN_13, GPIO_FUNC_41); /* MOSI */
GPIO_SetFunc(GPIO_PORT_B, GPIO_PIN_12, GPIO_FUNC_42); /* MISO */
break;
#endif
default:
result = -RT_ERROR;
break;
}
return result;
}
#endif
#if defined(BSP_USING_ETH)
/* PHY hardware reset time */
#define PHY_HW_RST_DELAY (0x40U)
rt_err_t rt_hw_eth_phy_reset(CM_ETH_TypeDef *CM_ETHx)
{
TCA9539_ConfigPin(TCA9539_IO_PORT1, EIO_ETH_RST, TCA9539_DIR_OUT);
TCA9539_WritePin(TCA9539_IO_PORT1, EIO_ETH_RST, TCA9539_PIN_RESET);
rt_thread_mdelay(PHY_HW_RST_DELAY);
TCA9539_WritePin(TCA9539_IO_PORT1, EIO_ETH_RST, TCA9539_PIN_SET);
rt_thread_mdelay(PHY_HW_RST_DELAY);
return RT_EOK;
}
rt_err_t rt_hw_eth_board_init(CM_ETH_TypeDef *CM_ETHx)
{
#if defined(ETH_USING_INTERFACE_RMII)
/*
ETH_SMI_MDIO ----------------> PA2
ETH_SMI_MDC -----------------> PC1
ETH_RMII_TX_EN --------------> PG11
ETH_RMII_TXD0 ---------------> PG13
ETH_RMII_TXD1 ---------------> PG14
ETH_RMII_REF_CLK ------------> PA1
ETH_RMII_CRS_DV -------------> PA7
ETH_RMII_RXD0 ---------------> PC4
ETH_RMII_RXD1 ---------------> PC5
ETH_RMII_RX_ER --------------> PI10
*/
/* Configure PA1, PA2 and PA7 */
GPIO_SetFunc(GPIO_PORT_A, (GPIO_PIN_01 | GPIO_PIN_02 | GPIO_PIN_07), GPIO_FUNC_11);
/* Configure PC1, PC4 and PC5 */
GPIO_SetFunc(GPIO_PORT_C, (GPIO_PIN_01 | GPIO_PIN_04 | GPIO_PIN_05), GPIO_FUNC_11);
/* Configure PG11, PG13 and PG14 */
GPIO_SetFunc(GPIO_PORT_G, (GPIO_PIN_11 | GPIO_PIN_13 | GPIO_PIN_14), GPIO_FUNC_11);
/* Configure PI10 */
GPIO_SetFunc(GPIO_PORT_I, GPIO_PIN_10, GPIO_FUNC_11);
#else
/*
ETH_SMI_MDIO ----------------> PA2
ETH_SMI_MDC -----------------> PC1
ETH_MII_TX_CLK --------------> PB6
ETH_MII_TX_EN ---------------> PG11
ETH_MII_TXD0 ----------------> PG13
ETH_MII_TXD1 ----------------> PG14
ETH_MII_TXD2 ----------------> PB9
ETH_MII_TXD3 ----------------> PB8
ETH_MII_RX_CLK --------------> PA1
ETH_MII_RX_DV ---------------> PA7
ETH_MII_RXD0 ----------------> PC4
ETH_MII_RXD1 ----------------> PC5
ETH_MII_RXD2 ----------------> PB0
ETH_MII_RXD3 ----------------> PB1
ETH_MII_RX_ER ---------------> PI10
ETH_MII_CRS -----------------> PH2
ETH_MII_COL -----------------> PH3
*/
/* Configure PA1, PA2 and PA7 */
GPIO_SetFunc(GPIO_PORT_A, (GPIO_PIN_01 | GPIO_PIN_02 | GPIO_PIN_07), GPIO_FUNC_11);
/* Configure PB0, PB1, PB6, PB8 and PB9 */
GPIO_SetFunc(GPIO_PORT_B, (GPIO_PIN_00 | GPIO_PIN_01 | GPIO_PIN_06 | GPIO_PIN_08 | GPIO_PIN_09), GPIO_FUNC_11);
/* Configure PC1, PC4 and PC5 */
GPIO_SetFunc(GPIO_PORT_C, (GPIO_PIN_01 | GPIO_PIN_04 | GPIO_PIN_05), GPIO_FUNC_11);
/* Configure PG11, PG13 and PG14 */
GPIO_SetFunc(GPIO_PORT_G, (GPIO_PIN_11 | GPIO_PIN_13 | GPIO_PIN_14), GPIO_FUNC_11);
/* Configure PH2, PH3 */
GPIO_SetFunc(GPIO_PORT_H, (GPIO_PIN_02 | GPIO_PIN_03), GPIO_FUNC_11);
/* Configure PI10 */
GPIO_SetFunc(GPIO_PORT_I, GPIO_PIN_10, GPIO_FUNC_11);
#endif
return RT_EOK;
}
#endif

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/*
* Copyright (C) 2022, Xiaohua Semiconductor Co., Ltd.
*
* SPDX-License-Identifier: Apache-2.0
*
* Change Logs:
* Date Author Notes
* 2022-04-28 CDT first version
*/
#ifndef __BOARD_CONFIG_H__
#define __BOARD_CONFIG_H__
#include <rtconfig.h>
#include "hc32_ll.h"
#include "drv_config.h"
/************************ USART port **********************/
#if defined(BSP_USING_UART1)
#define USART1_RX_PORT (GPIO_PORT_H)
#define USART1_RX_PIN (GPIO_PIN_13)
#define USART1_TX_PORT (GPIO_PORT_H)
#define USART1_TX_PIN (GPIO_PIN_15)
#endif
#if defined(BSP_USING_UART6)
#define USART6_RX_PORT (GPIO_PORT_H)
#define USART6_RX_PIN (GPIO_PIN_06)
#define USART6_TX_PORT (GPIO_PORT_E)
#define USART6_TX_PIN (GPIO_PIN_06)
#endif
/*********************** PWM port *************************/
#if defined(BSP_USING_PWM1)
#if defined(BSP_USING_PWM1_CH1)
#define PWM1_CH1_PORT (GPIO_PORT_A)
#define PWM1_CH1_PIN (GPIO_PIN_08)
#define PWM1_CH1_FUNC (GPIO_FUNC_4)
#endif
#if defined(BSP_USING_PWM1_CH2)
#define PWM1_CH2_PORT (GPIO_PORT_A)
#define PWM1_CH2_PIN (GPIO_PIN_09)
#define PWM1_CH2_FUNC (GPIO_FUNC_4)
#endif
#endif
/****************** Pulse encoder port ********************/
#if defined(BSP_USING_PULSE_ENCODER9)
#define PULSE_ENCODER9_CLKA_PORT (GPIO_PORT_G)
#define PULSE_ENCODER9_CLKA_PIN (GPIO_PIN_04)
#define PULSE_ENCODER9_CLKA_FUNC (GPIO_FUNC_4)
#define PULSE_ENCODER9_CLKB_PORT (GPIO_PORT_G)
#define PULSE_ENCODER9_CLKB_PIN (GPIO_PIN_05)
#define PULSE_ENCODER9_CLKB_FUNC (GPIO_FUNC_4)
#endif
/*********** ADC configure *********/
#if defined(BSP_USING_ADC1)
#define ADC1_CH_PORT (GPIO_PORT_C)
#define ADC1_CH_PIN (GPIO_PIN_00)
#endif
#if defined(BSP_USING_ADC2)
#define ADC2_CH_PORT (GPIO_PORT_C)
#define ADC2_CH_PIN (GPIO_PIN_01)
#endif
#if defined(BSP_USING_ADC3)
#define ADC3_CH_PORT (GPIO_PORT_C)
#define ADC3_CH_PIN (GPIO_PIN_02)
#endif
/*********** CAN configure *********/
#if defined(BSP_USING_CAN1)
#define CAN1_TX_PORT (GPIO_PORT_D)
#define CAN1_TX_PIN (GPIO_PIN_05)
#define CAN1_TX_PIN_FUNC (GPIO_FUNC_60)
#define CAN1_RX_PORT (GPIO_PORT_D)
#define CAN1_RX_PIN (GPIO_PIN_04)
#define CAN1_RX_PIN_FUNC (GPIO_FUNC_61)
#define CAN1_INT_PRIO (DDL_IRQ_PRIO_03)
#define CAN1_INT_SRC (INT_SRC_CAN1_HOST)
#define CAN1_INT_IRQn (INT004_IRQn)
#endif
#if defined(BSP_USING_CAN2)
#define CAN2_TX_PORT (GPIO_PORT_D)
#define CAN2_TX_PIN (GPIO_PIN_07)
#define CAN2_TX_PIN_FUNC (GPIO_FUNC_62)
#define CAN2_RX_PORT (GPIO_PORT_D)
#define CAN2_RX_PIN (GPIO_PIN_06)
#define CAN2_RX_PIN_FUNC (GPIO_FUNC_63)
#define CAN2_INT_PRIO (DDL_IRQ_PRIO_03)
#define CAN2_INT_SRC (INT_SRC_CAN2_HOST)
#define CAN2_INT_IRQn (INT005_IRQn)
#endif
#endif

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/*
* Copyright (C) 2022, Xiaohua Semiconductor Co., Ltd.
*
* SPDX-License-Identifier: Apache-2.0
*
* Change Logs:
* Date Author Notes
* 2022-04-28 CDT first version
*/
#ifndef __ADC_CONFIG_H__
#define __ADC_CONFIG_H__
#include <rtthread.h>
#ifdef __cplusplus
extern "C" {
#endif
#ifdef BSP_USING_ADC1
#ifndef ADC1_CONFIG
#define ADC1_CONFIG \
{ \
.name = "adc1", \
.resolution = ADC_RESOLUTION_12BIT, \
.data_align = ADC_DATAALIGN_RIGHT, \
.eoc_poll_time_max = 100, \
.hard_trig_enable = RT_FALSE, \
.hard_trig_src = ADC_HARDTRIG_ADTRG_PIN, \
.internal_trig0_comtrg0_enable = RT_FALSE, \
.internal_trig0_comtrg1_enable = RT_FALSE, \
.internal_trig0_sel = EVT_SRC_MAX, \
.internal_trig1_comtrg0_enable = RT_FALSE, \
.internal_trig1_comtrg1_enable = RT_FALSE, \
.internal_trig1_sel = EVT_SRC_MAX, \
.continue_conv_mode_enable = RT_FALSE, \
.data_reg_auto_clear = RT_TRUE, \
}
#endif /* ADC1_CONFIG */
#endif /* BSP_USING_ADC1 */
#ifdef BSP_USING_ADC2
#ifndef ADC2_CONFIG
#define ADC2_CONFIG \
{ \
.name = "adc2", \
.resolution = ADC_RESOLUTION_12BIT, \
.data_align = ADC_DATAALIGN_RIGHT, \
.eoc_poll_time_max = 100, \
.hard_trig_enable = RT_FALSE, \
.hard_trig_src = ADC_HARDTRIG_ADTRG_PIN, \
.internal_trig0_comtrg0_enable = RT_FALSE, \
.internal_trig0_comtrg1_enable = RT_FALSE, \
.internal_trig0_sel = EVT_SRC_MAX, \
.internal_trig1_comtrg0_enable = RT_FALSE, \
.internal_trig1_comtrg1_enable = RT_FALSE, \
.internal_trig1_sel = EVT_SRC_MAX, \
.continue_conv_mode_enable = RT_FALSE, \
.data_reg_auto_clear = RT_TRUE, \
}
#endif /* ADC2_CONFIG */
#endif /* BSP_USING_ADC2 */
#ifdef BSP_USING_ADC3
#ifndef ADC3_CONFIG
#define ADC3_CONFIG \
{ \
.name = "adc3", \
.resolution = ADC_RESOLUTION_12BIT, \
.data_align = ADC_DATAALIGN_RIGHT, \
.eoc_poll_time_max = 100, \
.hard_trig_enable = RT_FALSE, \
.hard_trig_src = ADC_HARDTRIG_ADTRG_PIN, \
.internal_trig0_comtrg0_enable = RT_FALSE, \
.internal_trig0_comtrg1_enable = RT_FALSE, \
.internal_trig0_sel = EVT_SRC_MAX, \
.internal_trig1_comtrg0_enable = RT_FALSE, \
.internal_trig1_comtrg1_enable = RT_FALSE, \
.internal_trig1_sel = EVT_SRC_MAX, \
.continue_conv_mode_enable = RT_FALSE, \
.data_reg_auto_clear = RT_TRUE, \
}
#endif /* ADC3_CONFIG */
#endif /* BSP_USING_ADC3 */
#ifdef __cplusplus
}
#endif
#endif /* __ADC_CONFIG_H__ */

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/*
* Copyright (C) 2022, Xiaohua Semiconductor Co., Ltd.
*
* SPDX-License-Identifier: Apache-2.0
*
* Change Logs:
* Date Author Notes
* 2022-04-28 CDT first version
*/
#ifndef __CAN_CONFIG_H__
#define __CAN_CONFIG_H__
#include <rtthread.h>
#ifdef __cplusplus
extern "C" {
#endif
#ifdef BSP_USING_CAN1
#ifndef CAN1_CONFIG
#define CAN1_CONFIG \
{ \
.name = "can1", \
}
#endif /* CAN1_CONFIG */
#endif /* BSP_USING_CAN1 */
#ifdef BSP_USING_CAN2
#ifndef CAN2_CONFIG
#define CAN2_CONFIG \
{ \
.name = "can2", \
}
#endif /* CAN2_CONFIG */
#endif /* BSP_USING_CAN2 */
#ifdef __cplusplus
}
#endif
#endif /* __CAN_CONFIG_H__ */

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/*
* Copyright (C) 2022, Xiaohua Semiconductor Co., Ltd.
*
* SPDX-License-Identifier: Apache-2.0
*
* Change Logs:
* Date Author Notes
* 2022-04-28 CDT first version
*/
#ifndef __DMA_CONFIG_H__
#define __DMA_CONFIG_H__
#include <rtthread.h>
#ifdef __cplusplus
extern "C" {
#endif
/* DMA1 ch0 */
#if defined(BSP_SPI1_RX_USING_DMA) && !defined(SPI1_RX_DMA_INSTANCE)
#define SPI1_RX_DMA_INSTANCE CM_DMA1
#define SPI1_RX_DMA_CHANNEL DMA_CH0
#define SPI1_RX_DMA_CLOCK (PWC_FCG0_DMA1 | PWC_FCG0_AOS)
#define SPI1_RX_DMA_TRIG_SELECT AOS_DMA1_0
#define SPI1_RX_DMA_IRQn INT038_IRQn
#define SPI1_RX_DMA_INT_PRIO DDL_IRQ_PRIO_DEFAULT
#define SPI1_RX_DMA_INT_SRC INT_SRC_DMA1_TC0
#endif
/* DMA1 ch1 */
#if defined(BSP_SPI1_TX_USING_DMA) && !defined(SPI1_TX_DMA_INSTANCE)
#define SPI1_TX_DMA_INSTANCE CM_DMA1
#define SPI1_TX_DMA_CHANNEL DMA_CH1
#define SPI1_TX_DMA_CLOCK (PWC_FCG0_DMA1 | PWC_FCG0_AOS)
#define SPI1_TX_DMA_TRIG_SELECT AOS_DMA1_1
#define SPI1_TX_DMA_IRQn INT039_IRQn
#define SPI1_TX_DMA_INT_PRIO DDL_IRQ_PRIO_DEFAULT
#define SPI1_TX_DMA_INT_SRC INT_SRC_DMA1_TC1
#endif
/* DMA1 ch2 */
#if defined(BSP_SPI2_RX_USING_DMA) && !defined(SPI2_RX_DMA_INSTANCE)
#define SPI2_RX_DMA_INSTANCE CM_DMA1
#define SPI2_RX_DMA_CHANNEL DMA_CH2
#define SPI2_RX_DMA_CLOCK (PWC_FCG0_DMA1 | PWC_FCG0_AOS)
#define SPI2_RX_DMA_TRIG_SELECT AOS_DMA1_2
#define SPI2_RX_DMA_IRQn INT040_IRQn
#define SPI2_RX_DMA_INT_PRIO DDL_IRQ_PRIO_DEFAULT
#define SPI2_RX_DMA_INT_SRC INT_SRC_DMA1_TC2
#endif
/* DMA1 ch3 */
#if defined(BSP_SPI2_TX_USING_DMA) && !defined(SPI2_TX_DMA_INSTANCE)
#define SPI2_TX_DMA_INSTANCE CM_DMA1
#define SPI2_TX_DMA_CHANNEL DMA_CH3
#define SPI2_TX_DMA_CLOCK (PWC_FCG0_DMA1 | PWC_FCG0_AOS)
#define SPI2_TX_DMA_TRIG_SELECT AOS_DMA1_3
#define SPI2_TX_DMA_IRQn INT041_IRQn
#define SPI2_TX_DMA_INT_PRIO DDL_IRQ_PRIO_DEFAULT
#define SPI2_TX_DMA_INT_SRC INT_SRC_DMA1_TC3
#endif
/* DMA1 ch4 */
#if defined(BSP_SPI3_RX_USING_DMA) && !defined(SPI3_RX_DMA_INSTANCE)
#define SPI3_RX_DMA_INSTANCE CM_DMA1
#define SPI3_RX_DMA_CHANNEL DMA_CH4
#define SPI3_RX_DMA_CLOCK (PWC_FCG0_DMA1 | PWC_FCG0_AOS)
#define SPI3_RX_DMA_TRIG_SELECT AOS_DMA1_4
#define SPI3_RX_DMA_IRQn INT042_IRQn
#define SPI3_RX_DMA_INT_PRIO DDL_IRQ_PRIO_DEFAULT
#define SPI3_RX_DMA_INT_SRC INT_SRC_DMA1_TC4
#endif
/* DMA1 ch5 */
#if defined(BSP_SPI3_TX_USING_DMA) && !defined(SPI3_TX_DMA_INSTANCE)
#define SPI3_TX_DMA_INSTANCE CM_DMA1
#define SPI3_TX_DMA_CHANNEL DMA_CH5
#define SPI3_TX_DMA_CLOCK (PWC_FCG0_DMA1 | PWC_FCG0_AOS)
#define SPI3_TX_DMA_TRIG_SELECT AOS_DMA1_5
#define SPI3_TX_DMA_IRQn INT043_IRQn
#define SPI3_TX_DMA_INT_PRIO DDL_IRQ_PRIO_DEFAULT
#define SPI3_TX_DMA_INT_SRC INT_SRC_DMA1_TC5
#endif
/* DMA1 ch6 */
#if defined(BSP_SPI4_RX_USING_DMA) && !defined(SPI4_RX_DMA_INSTANCE)
#define SPI4_RX_DMA_INSTANCE CM_DMA1
#define SPI4_RX_DMA_CHANNEL DMA_CH6
#define SPI4_RX_DMA_CLOCK (PWC_FCG0_DMA1 | PWC_FCG0_AOS)
#define SPI4_RX_DMA_TRIG_SELECT AOS_DMA1_6
#define SPI4_RX_DMA_IRQn INT018_IRQn
#define SPI4_RX_DMA_INT_PRIO DDL_IRQ_PRIO_DEFAULT
#define SPI4_RX_DMA_INT_SRC INT_SRC_DMA1_TC6
#endif
/* DMA1 ch7 */
#if defined(BSP_SPI4_TX_USING_DMA) && !defined(SPI4_TX_DMA_INSTANCE)
#define SPI4_TX_DMA_INSTANCE CM_DMA1
#define SPI4_TX_DMA_CHANNEL DMA_CH7
#define SPI4_TX_DMA_CLOCK (PWC_FCG0_DMA1 | PWC_FCG0_AOS)
#define SPI4_TX_DMA_TRIG_SELECT AOS_DMA1_7
#define SPI4_TX_DMA_IRQn INT019_IRQn
#define SPI4_TX_DMA_INT_PRIO DDL_IRQ_PRIO_DEFAULT
#define SPI4_TX_DMA_INT_SRC INT_SRC_DMA1_TC7
#endif
/* DMA2 ch0 */
#if defined(BSP_UART1_RX_USING_DMA) && !defined(UART1_RX_DMA_INSTANCE)
#define UART1_RX_DMA_INSTANCE CM_DMA2
#define UART1_RX_DMA_CHANNEL DMA_CH0
#define UART1_RX_DMA_CLOCK (PWC_FCG0_DMA2 | PWC_FCG0_AOS)
#define UART1_RX_DMA_TRIG_SELECT AOS_DMA2_0
#define UART1_RX_DMA_IRQn INT044_IRQn
#define UART1_RX_DMA_INT_PRIO DDL_IRQ_PRIO_DEFAULT
#define UART1_RX_DMA_INT_SRC INT_SRC_DMA2_TC0
#endif
/* DMA2 ch1 */
#if defined(BSP_UART1_TX_USING_DMA) && !defined(UART1_TX_DMA_INSTANCE)
#define UART1_TX_DMA_INSTANCE CM_DMA2
#define UART1_TX_DMA_CHANNEL DMA_CH1
#define UART1_TX_DMA_CLOCK (PWC_FCG0_DMA2 | PWC_FCG0_AOS)
#define UART1_TX_DMA_TRIG_SELECT AOS_DMA2_1
#define UART1_TX_DMA_IRQn INT045_IRQn
#define UART1_TX_DMA_INT_PRIO DDL_IRQ_PRIO_DEFAULT
#define UART1_TX_DMA_INT_SRC INT_SRC_DMA2_TC1
#endif
/* DMA2 ch2 */
#if defined(BSP_UART2_RX_USING_DMA) && !defined(UART2_RX_DMA_INSTANCE)
#define UART2_RX_DMA_INSTANCE CM_DMA2
#define UART2_RX_DMA_CHANNEL DMA_CH2
#define UART2_RX_DMA_CLOCK (PWC_FCG0_DMA2 | PWC_FCG0_AOS)
#define UART2_RX_DMA_TRIG_SELECT AOS_DMA2_2
#define UART2_RX_DMA_IRQn INT046_IRQn
#define UART2_RX_DMA_INT_PRIO DDL_IRQ_PRIO_DEFAULT
#define UART2_RX_DMA_INT_SRC INT_SRC_DMA2_TC2
#endif
/* DMA2 ch3 */
#if defined(BSP_UART2_TX_USING_DMA) && !defined(UART2_TX_DMA_INSTANCE)
#define UART2_TX_DMA_INSTANCE CM_DMA2
#define UART2_TX_DMA_CHANNEL DMA_CH3
#define UART2_TX_DMA_CLOCK (PWC_FCG0_DMA2 | PWC_FCG0_AOS)
#define UART2_TX_DMA_TRIG_SELECT AOS_DMA2_3
#define UART2_TX_DMA_IRQn INT047_IRQn
#define UART2_TX_DMA_INT_PRIO DDL_IRQ_PRIO_DEFAULT
#define UART2_TX_DMA_INT_SRC INT_SRC_DMA2_TC3
#endif
/* DMA2 ch4 */
#if defined(BSP_UART6_RX_USING_DMA) && !defined(UART6_RX_DMA_INSTANCE)
#define UART6_RX_DMA_INSTANCE CM_DMA2
#define UART6_RX_DMA_CHANNEL DMA_CH4
#define UART6_RX_DMA_CLOCK (PWC_FCG0_DMA2 | PWC_FCG0_AOS)
#define UART6_RX_DMA_TRIG_SELECT AOS_DMA2_4
#define UART6_RX_DMA_IRQn INT048_IRQn
#define UART6_RX_DMA_INT_PRIO DDL_IRQ_PRIO_DEFAULT
#define UART6_RX_DMA_INT_SRC INT_SRC_DMA2_TC4
#endif
/* DMA2 ch5 */
#if defined(BSP_UART6_TX_USING_DMA) && !defined(UART6_TX_DMA_INSTANCE)
#define UART6_TX_DMA_INSTANCE CM_DMA2
#define UART6_TX_DMA_CHANNEL DMA_CH5
#define UART6_TX_DMA_CLOCK (PWC_FCG0_DMA2 | PWC_FCG0_AOS)
#define UART6_TX_DMA_TRIG_SELECT AOS_DMA2_5
#define UART6_TX_DMA_IRQn INT049_IRQn
#define UART6_TX_DMA_INT_PRIO DDL_IRQ_PRIO_DEFAULT
#define UART6_TX_DMA_INT_SRC INT_SRC_DMA2_TC5
#endif
/* DMA2 ch6 */
#if defined(BSP_UART7_RX_USING_DMA) && !defined(UART7_RX_DMA_INSTANCE)
#define UART7_RX_DMA_INSTANCE CM_DMA2
#define UART7_RX_DMA_CHANNEL DMA_CH6
#define UART7_RX_DMA_CLOCK (PWC_FCG0_DMA2 | PWC_FCG0_AOS)
#define UART7_RX_DMA_TRIG_SELECT AOS_DMA2_6
#define UART7_RX_DMA_IRQn INT020_IRQn
#define UART7_RX_DMA_INT_PRIO DDL_IRQ_PRIO_DEFAULT
#define UART7_RX_DMA_INT_SRC INT_SRC_DMA2_TC6
#endif
/* DMA2 ch7 */
#if defined(BSP_UART7_TX_USING_DMA) && !defined(UART7_TX_DMA_INSTANCE)
#define UART7_TX_DMA_INSTANCE CM_DMA2
#define UART7_TX_DMA_CHANNEL DMA_CH7
#define UART7_TX_DMA_CLOCK (PWC_FCG0_DMA2 | PWC_FCG0_AOS)
#define UART7_TX_DMA_TRIG_SELECT AOS_DMA2_7
#define UART7_TX_DMA_IRQn INT021_IRQn
#define UART7_TX_DMA_INT_PRIO DDL_IRQ_PRIO_DEFAULT
#define UART7_TX_DMA_INT_SRC INT_SRC_DMA2_TC7
#endif
#ifdef __cplusplus
}
#endif
#endif /* __DMA_CONFIG_H__ */

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/*
* Copyright (C) 2022, Xiaohua Semiconductor Co., Ltd.
*
* SPDX-License-Identifier: Apache-2.0
*
* Change Logs:
* Date Author Notes
* 2022-04-28 CDT first version
*/
#ifndef __ETH_CONFIG_H__
#define __ETH_CONFIG_H__
#include <rtthread.h>
#ifdef __cplusplus
extern "C" {
#endif
#if defined(BSP_USING_ETH)
#ifndef ETH_IRQ_CONFIG
#define ETH_IRQ_CONFIG \
{ \
.irq_num = INT104_IRQn, \
.irq_prio = DDL_IRQ_PRIO_DEFAULT, \
.int_src = INT_SRC_ETH_GLB_INT, \
}
#endif /* ETH_IRQ_CONFIG */
#endif
#ifdef __cplusplus
}
#endif
#endif /* __ETH_CONFIG_H__ */

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/*
* Copyright (C) 2022, Xiaohua Semiconductor Co., Ltd.
*
* SPDX-License-Identifier: Apache-2.0
*
* Change Logs:
* Date Author Notes
* 2022-04-28 CDT first version
*/
#ifndef __GPIO_CONFIG_H__
#define __GPIO_CONFIG_H__
#include <rtthread.h>
#ifdef __cplusplus
extern "C" {
#endif
#if defined(RT_USING_PIN)
#ifndef EXTINT0_IRQ_CONFIG
#define EXTINT0_IRQ_CONFIG \
{ \
.irq_num = INT022_IRQn, \
.irq_prio = DDL_IRQ_PRIO_DEFAULT, \
.int_src = INT_SRC_PORT_EIRQ0, \
}
#endif /* EXTINT1_IRQ_CONFIG */
#ifndef EXTINT1_IRQ_CONFIG
#define EXTINT1_IRQ_CONFIG \
{ \
.irq_num = INT023_IRQn, \
.irq_prio = DDL_IRQ_PRIO_DEFAULT, \
.int_src = INT_SRC_PORT_EIRQ1, \
}
#endif /* EXTINT1_IRQ_CONFIG */
#ifndef EXTINT2_IRQ_CONFIG
#define EXTINT2_IRQ_CONFIG \
{ \
.irq_num = INT024_IRQn, \
.irq_prio = DDL_IRQ_PRIO_DEFAULT, \
.int_src = INT_SRC_PORT_EIRQ2, \
}
#endif /* EXTINT2_IRQ_CONFIG */
#ifndef EXTINT3_IRQ_CONFIG
#define EXTINT3_IRQ_CONFIG \
{ \
.irq_num = INT025_IRQn, \
.irq_prio = DDL_IRQ_PRIO_DEFAULT, \
.int_src = INT_SRC_PORT_EIRQ3, \
}
#endif /* EXTINT3_IRQ_CONFIG */
#ifndef EXTINT4_IRQ_CONFIG
#define EXTINT4_IRQ_CONFIG \
{ \
.irq_num = INT026_IRQn, \
.irq_prio = DDL_IRQ_PRIO_DEFAULT, \
.int_src = INT_SRC_PORT_EIRQ4, \
}
#endif /* EXTINT4_IRQ_CONFIG */
#ifndef EXTINT5_IRQ_CONFIG
#define EXTINT5_IRQ_CONFIG \
{ \
.irq_num = INT027_IRQn, \
.irq_prio = DDL_IRQ_PRIO_DEFAULT, \
.int_src = INT_SRC_PORT_EIRQ5, \
}
#endif /* EXTINT5_IRQ_CONFIG */
#ifndef EXTINT6_IRQ_CONFIG
#define EXTINT6_IRQ_CONFIG \
{ \
.irq_num = INT028_IRQn, \
.irq_prio = DDL_IRQ_PRIO_DEFAULT, \
.int_src = INT_SRC_PORT_EIRQ6, \
}
#endif /* EXTINT6_IRQ_CONFIG */
#ifndef EXTINT7_IRQ_CONFIG
#define EXTINT7_IRQ_CONFIG \
{ \
.irq_num = INT029_IRQn, \
.irq_prio = DDL_IRQ_PRIO_DEFAULT, \
.int_src = INT_SRC_PORT_EIRQ7, \
}
#endif /* EXTINT7_IRQ_CONFIG */
#ifndef EXTINT8_IRQ_CONFIG
#define EXTINT8_IRQ_CONFIG \
{ \
.irq_num = INT030_IRQn, \
.irq_prio = DDL_IRQ_PRIO_DEFAULT, \
.int_src = INT_SRC_PORT_EIRQ8, \
}
#endif /* EXTINT8_IRQ_CONFIG */
#ifndef EXTINT9_IRQ_CONFIG
#define EXTINT9_IRQ_CONFIG \
{ \
.irq_num = INT031_IRQn, \
.irq_prio = DDL_IRQ_PRIO_DEFAULT, \
.int_src = INT_SRC_PORT_EIRQ9, \
}
#endif /* EXTINT9_IRQ_CONFIG */
#ifndef EXTINT10_IRQ_CONFIG
#define EXTINT10_IRQ_CONFIG \
{ \
.irq_num = INT032_IRQn, \
.irq_prio = DDL_IRQ_PRIO_DEFAULT, \
.int_src = INT_SRC_PORT_EIRQ10, \
}
#endif /* EXTINT10_IRQ_CONFIG */
#ifndef EXTINT11_IRQ_CONFIG
#define EXTINT11_IRQ_CONFIG \
{ \
.irq_num = INT033_IRQn, \
.irq_prio = DDL_IRQ_PRIO_DEFAULT, \
.int_src = INT_SRC_PORT_EIRQ11, \
}
#endif /* EXTINT11_IRQ_CONFIG */
#ifndef EXTINT12_IRQ_CONFIG
#define EXTINT12_IRQ_CONFIG \
{ \
.irq_num = INT034_IRQn, \
.irq_prio = DDL_IRQ_PRIO_DEFAULT, \
.int_src = INT_SRC_PORT_EIRQ12, \
}
#endif /* EXTINT12_IRQ_CONFIG */
#ifndef EXTINT13_IRQ_CONFIG
#define EXTINT13_IRQ_CONFIG \
{ \
.irq_num = INT035_IRQn, \
.irq_prio = DDL_IRQ_PRIO_DEFAULT, \
.int_src = INT_SRC_PORT_EIRQ13, \
}
#endif /* EXTINT13_IRQ_CONFIG */
#ifndef EXTINT14_IRQ_CONFIG
#define EXTINT14_IRQ_CONFIG \
{ \
.irq_num = INT036_IRQn, \
.irq_prio = DDL_IRQ_PRIO_DEFAULT, \
.int_src = INT_SRC_PORT_EIRQ14, \
}
#endif /* EXTINT14_IRQ_CONFIG */
#ifndef EXTINT15_IRQ_CONFIG
#define EXTINT15_IRQ_CONFIG \
{ \
.irq_num = INT037_IRQn, \
.irq_prio = DDL_IRQ_PRIO_DEFAULT, \
.int_src = INT_SRC_PORT_EIRQ15, \
}
#endif /* EXTINT15_IRQ_CONFIG */
#endif
#ifdef __cplusplus
}
#endif
#endif /* __GPIO_CONFIG_H__ */

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/*
* Copyright (C) 2022, Xiaohua Semiconductor Co., Ltd.
*
* SPDX-License-Identifier: Apache-2.0
*
* Change Logs:
* Date Author Notes
* 2022-04-28 CDT first version
*/
#ifndef __SPI_CONFIG_H__
#define __SPI_CONFIG_H__
#include <rtthread.h>
#ifdef __cplusplus
extern "C" {
#endif
#ifdef BSP_USING_SPI1
#ifndef SPI1_BUS_CONFIG
#define SPI1_BUS_CONFIG \
{ \
.Instance = CM_SPI1, \
.bus_name = "spi1", \
.clock = FCG1_PERIPH_SPI1, \
}
#endif /* SPI1_BUS_CONFIG */
#endif /* BSP_USING_SPI1 */
#ifdef BSP_SPI1_TX_USING_DMA
#ifndef SPI1_TX_DMA_CONFIG
#define SPI1_TX_DMA_CONFIG \
{ \
.Instance = SPI1_TX_DMA_INSTANCE, \
.channel = SPI1_TX_DMA_CHANNEL, \
.clock = SPI1_TX_DMA_CLOCK, \
.trigger_select = SPI1_TX_DMA_TRIG_SELECT, \
.trigger_event = EVT_SRC_SPI1_SPTI, \
.irq_config = \
{ \
.irq_num = SPI1_TX_DMA_IRQn, \
.irq_prio = SPI1_TX_DMA_INT_PRIO, \
.int_src = SPI1_TX_DMA_INT_SRC, \
} \
}
#endif /* SPI1_TX_DMA_CONFIG */
#endif /* BSP_SPI1_TX_USING_DMA */
#ifdef BSP_SPI1_RX_USING_DMA
#ifndef SPI1_RX_DMA_CONFIG
#define SPI1_RX_DMA_CONFIG \
{ \
.Instance = SPI1_RX_DMA_INSTANCE, \
.channel = SPI1_RX_DMA_CHANNEL, \
.clock = SPI1_RX_DMA_CLOCK, \
.trigger_select = SPI1_RX_DMA_TRIG_SELECT, \
.trigger_event = EVT_SRC_SPI1_SPRI, \
.irq_config = \
{ \
.irq_num = SPI1_RX_DMA_IRQn, \
.irq_prio = SPI1_RX_DMA_INT_PRIO, \
.int_src = SPI1_RX_DMA_INT_SRC, \
} \
}
#endif /* SPI1_RX_DMA_CONFIG */
#endif /* BSP_SPI1_RX_USING_DMA */
#ifdef BSP_USING_SPI2
#ifndef SPI2_BUS_CONFIG
#define SPI2_BUS_CONFIG \
{ \
.Instance = CM_SPI2, \
.bus_name = "spi2", \
.clock = FCG1_PERIPH_SPI2, \
}
#endif /* SPI2_BUS_CONFIG */
#endif /* BSP_USING_SPI2 */
#ifdef BSP_SPI2_TX_USING_DMA
#ifndef SPI2_TX_DMA_CONFIG
#define SPI2_TX_DMA_CONFIG \
{ \
.Instance = SPI2_TX_DMA_INSTANCE, \
.channel = SPI2_TX_DMA_CHANNEL, \
.clock = SPI2_TX_DMA_CLOCK, \
.trigger_select = SPI2_TX_DMA_TRIG_SELECT, \
.trigger_event = EVT_SRC_SPI2_SPTI, \
.irq_config = \
{ \
.irq_num = SPI2_TX_DMA_IRQn, \
.irq_prio = SPI2_TX_DMA_INT_PRIO, \
.int_src = SPI2_TX_DMA_INT_SRC, \
} \
}
#endif /* SPI2_TX_DMA_CONFIG */
#endif /* BSP_SPI2_TX_USING_DMA */
#ifdef BSP_SPI2_RX_USING_DMA
#ifndef SPI2_RX_DMA_CONFIG
#define SPI2_RX_DMA_CONFIG \
{ \
.Instance = SPI2_RX_DMA_INSTANCE, \
.channel = SPI2_RX_DMA_CHANNEL, \
.clock = SPI2_RX_DMA_CLOCK, \
.trigger_select = SPI2_RX_DMA_TRIG_SELECT, \
.trigger_event = EVT_SRC_SPI2_SPRI, \
.irq_config = \
{ \
.irq_num = SPI2_RX_DMA_IRQn, \
.irq_prio = SPI2_RX_DMA_INT_PRIO, \
.int_src = SPI2_RX_DMA_INT_SRC, \
} \
}
#endif /* SPI2_RX_DMA_CONFIG */
#endif /* BSP_SPI2_RX_USING_DMA */
#ifdef BSP_USING_SPI3
#ifndef SPI3_BUS_CONFIG
#define SPI3_BUS_CONFIG \
{ \
.Instance = CM_SPI3, \
.bus_name = "spi3", \
.clock = FCG1_PERIPH_SPI3, \
}
#endif /* SPI3_BUS_CONFIG */
#endif /* BSP_USING_SPI3 */
#ifdef BSP_SPI3_TX_USING_DMA
#ifndef SPI3_TX_DMA_CONFIG
#define SPI3_TX_DMA_CONFIG \
{ \
.Instance = SPI3_TX_DMA_INSTANCE, \
.channel = SPI3_TX_DMA_CHANNEL, \
.clock = SPI3_TX_DMA_CLOCK, \
.trigger_select = SPI3_TX_DMA_TRIG_SELECT, \
.trigger_event = EVT_SRC_SPI3_SPTI, \
.irq_config = \
{ \
.irq_num = SPI3_TX_DMA_IRQn, \
.irq_prio = SPI3_TX_DMA_INT_PRIO, \
.int_src = SPI3_TX_DMA_INT_SRC, \
} \
}
#endif /* SPI3_TX_DMA_CONFIG */
#endif /* BSP_SPI3_TX_USING_DMA */
#ifdef BSP_SPI3_RX_USING_DMA
#ifndef SPI3_RX_DMA_CONFIG
#define SPI3_RX_DMA_CONFIG \
{ \
.Instance = SPI3_RX_DMA_INSTANCE, \
.channel = SPI3_RX_DMA_CHANNEL, \
.clock = SPI3_RX_DMA_CLOCK, \
.trigger_select = SPI3_RX_DMA_TRIG_SELECT, \
.trigger_event = EVT_SRC_SPI3_SPRI, \
.irq_config = \
{ \
.irq_num = SPI3_RX_DMA_IRQn, \
.irq_prio = SPI3_RX_DMA_INT_PRIO, \
.int_src = SPI3_RX_DMA_INT_SRC, \
} \
}
#endif /* SPI3_RX_DMA_CONFIG */
#endif /* BSP_SPI3_RX_USING_DMA */
#ifdef BSP_USING_SPI4
#ifndef SPI4_BUS_CONFIG
#define SPI4_BUS_CONFIG \
{ \
.Instance = CM_SPI4, \
.bus_name = "spi4", \
.clock = FCG1_PERIPH_SPI4, \
}
#endif /* SPI4_BUS_CONFIG */
#endif /* BSP_USING_SPI4 */
#ifdef BSP_SPI4_TX_USING_DMA
#ifndef SPI4_TX_DMA_CONFIG
#define SPI4_TX_DMA_CONFIG \
{ \
.Instance = SPI4_TX_DMA_INSTANCE, \
.channel = SPI4_TX_DMA_CHANNEL, \
.clock = SPI4_TX_DMA_CLOCK, \
.trigger_select = SPI4_TX_DMA_TRIG_SELECT, \
.trigger_event = EVT_SRC_SPI4_SPTI, \
.irq_config = \
{ \
.irq_num = SPI4_TX_DMA_IRQn, \
.irq_prio = SPI4_TX_DMA_INT_PRIO, \
.int_src = SPI4_TX_DMA_INT_SRC, \
} \
}
#endif /* SPI4_TX_DMA_CONFIG */
#endif /* BSP_SPI4_TX_USING_DMA */
#ifdef BSP_SPI4_RX_USING_DMA
#ifndef SPI4_RX_DMA_CONFIG
#define SPI4_RX_DMA_CONFIG \
{ \
.Instance = SPI4_RX_DMA_INSTANCE, \
.channel = SPI4_RX_DMA_CHANNEL, \
.clock = SPI4_RX_DMA_CLOCK, \
.trigger_select = SPI4_RX_DMA_TRIG_SELECT, \
.trigger_event = EVT_SRC_SPI4_SPRI, \
.irq_config = \
{ \
.irq_num = SPI4_RX_DMA_IRQn, \
.irq_prio = SPI4_RX_DMA_INT_PRIO, \
.int_src = SPI4_RX_DMA_INT_SRC, \
} \
}
#endif /* SPI4_RX_DMA_CONFIG */
#endif /* BSP_SPI4_RX_USING_DMA */
#ifdef BSP_USING_SPI5
#ifndef SPI5_BUS_CONFIG
#define SPI5_BUS_CONFIG \
{ \
.Instance = CM_SPI5, \
.bus_name = "spi5", \
.clock = FCG1_PERIPH_SPI5, \
}
#endif /* SPI5_BUS_CONFIG */
#endif /* BSP_USING_SPI5 */
#ifdef BSP_SPI5_TX_USING_DMA
#ifndef SPI5_TX_DMA_CONFIG
#define SPI5_TX_DMA_CONFIG \
{ \
.Instance = SPI5_TX_DMA_INSTANCE, \
.channel = SPI5_TX_DMA_CHANNEL, \
.clock = SPI5_TX_DMA_CLOCK, \
.trigger_select = SPI5_TX_DMA_TRIG_SELECT, \
.trigger_event = EVT_SRC_SPI5_SPTI, \
.irq_config = \
{ \
.irq_num = SPI5_TX_DMA_IRQn, \
.irq_prio = SPI5_TX_DMA_INT_PRIO, \
.int_src = SPI5_TX_DMA_INT_SRC, \
} \
}
#endif /* SPI5_TX_DMA_CONFIG */
#endif /* BSP_SPI5_TX_USING_DMA */
#ifdef BSP_SPI5_RX_USING_DMA
#ifndef SPI5_RX_DMA_CONFIG
#define SPI5_RX_DMA_CONFIG \
{ \
.Instance = SPI5_RX_DMA_INSTANCE, \
.channel = SPI5_RX_DMA_CHANNEL, \
.clock = SPI5_RX_DMA_CLOCK, \
.trigger_select = SPI5_RX_DMA_TRIG_SELECT, \
.trigger_event = EVT_SRC_SPI5_SPRI, \
.irq_config = \
{ \
.irq_num = SPI5_RX_DMA_IRQn, \
.irq_prio = SPI5_RX_DMA_INT_PRIO, \
.int_src = SPI5_RX_DMA_INT_SRC, \
} \
}
#endif /* SPI5_RX_DMA_CONFIG */
#endif /* BSP_SPI5_RX_USING_DMA */
#ifdef BSP_USING_SPI6
#ifndef SPI6_BUS_CONFIG
#define SPI6_BUS_CONFIG \
{ \
.Instance = CM_SPI6, \
.bus_name = "spi6", \
.clock = FCG1_PERIPH_SPI6, \
}
#endif /* SPI6_BUS_CONFIG */
#endif /* BSP_USING_SPI6 */
#ifdef BSP_SPI6_TX_USING_DMA
#ifndef SPI6_TX_DMA_CONFIG
#define SPI6_TX_DMA_CONFIG \
{ \
.Instance = SPI6_TX_DMA_INSTANCE, \
.channel = SPI6_TX_DMA_CHANNEL, \
.clock = SPI6_TX_DMA_CLOCK, \
.trigger_select = SPI6_TX_DMA_TRIG_SELECT, \
.trigger_event = EVT_SRC_SPI6_SPTI, \
.irq_config = \
{ \
.irq_num = SPI6_TX_DMA_IRQn, \
.irq_prio = SPI6_TX_DMA_INT_PRIO, \
.int_src = SPI6_TX_DMA_INT_SRC, \
} \
}
#endif /* SPI6_TX_DMA_CONFIG */
#endif /* BSP_SPI6_TX_USING_DMA */
#ifdef BSP_SPI6_RX_USING_DMA
#ifndef SPI6_RX_DMA_CONFIG
#define SPI6_RX_DMA_CONFIG \
{ \
.Instance = SPI6_RX_DMA_INSTANCE, \
.channel = SPI6_RX_DMA_CHANNEL, \
.clock = SPI6_RX_DMA_CLOCK, \
.trigger_select = SPI6_RX_DMA_TRIG_SELECT, \
.trigger_event = EVT_SRC_SPI6_SPRI, \
.irq_config = \
{ \
.irq_num = SPI6_RX_DMA_IRQn, \
.irq_prio = SPI6_RX_DMA_INT_PRIO, \
.int_src = SPI6_RX_DMA_INT_SRC, \
} \
}
#endif /* SPI6_RX_DMA_CONFIG */
#endif /* BSP_SPI6_RX_USING_DMA */
#ifdef __cplusplus
}
#endif
#endif /*__SPI_CONFIG_H__ */

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/*
* Copyright (C) 2022, Xiaohua Semiconductor Co., Ltd.
*
* SPDX-License-Identifier: Apache-2.0
*
* Change Logs:
* Date Author Notes
* 2022-04-28 CDT first version
*/
#ifndef __TIM_CONFIG_H__
#define __TIM_CONFIG_H__
#include <rtthread.h>
#ifdef __cplusplus
extern "C" {
#endif
#ifndef TIM_DEV_INFO_CONFIG
#define TIM_DEV_INFO_CONFIG \
{ \
.maxfreq = 1000000, \
.minfreq = 3000, \
.maxcnt = 0xFFFF, \
.cntmode = HWTIMER_CNTMODE_UP, \
}
#endif /* TIM_DEV_INFO_CONFIG */
#ifdef BSP_USING_TIM3
#ifndef TIM3_CONFIG
#define TIM3_CONFIG \
{ \
.tim_handle.Instance = TIM3, \
.tim_irqn = TIM3_IRQn, \
.name = "timer3", \
}
#endif /* TIM3_CONFIG */
#endif /* BSP_USING_TIM3 */
#ifdef BSP_USING_TIM11
#ifndef TIM11_CONFIG
#define TIM11_CONFIG \
{ \
.tim_handle.Instance = TIM11, \
.tim_irqn = TIM1_TRG_COM_TIM11_IRQn, \
.name = "timer11", \
}
#endif /* TIM11_CONFIG */
#endif /* BSP_USING_TIM11 */
#ifdef BSP_USING_TIM13
#ifndef TIM13_CONFIG
#define TIM13_CONFIG \
{ \
.tim_handle.Instance = TIM13, \
.tim_irqn = TIM8_UP_TIM13_IRQn, \
.name = "timer13", \
}
#endif /* TIM13_CONFIG */
#endif /* BSP_USING_TIM13 */
#ifdef BSP_USING_TIM14
#ifndef TIM14_CONFIG
#define TIM14_CONFIG \
{ \
.tim_handle.Instance = TIM14, \
.tim_irqn = TIM8_TRG_COM_TIM14_IRQn, \
.name = "timer14", \
}
#endif /* TIM14_CONFIG */
#endif /* BSP_USING_TIM14 */
#ifdef __cplusplus
}
#endif
#endif /* __TIM_CONFIG_H__ */

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/*
* Copyright (C) 2022, Xiaohua Semiconductor Co., Ltd.
*
* SPDX-License-Identifier: Apache-2.0
*
* Change Logs:
* Date Author Notes
* 2022-04-28 CDT first version
*/
#ifndef __UART_CONFIG_H__
#define __UART_CONFIG_H__
#include <rtthread.h>
#ifdef __cplusplus
extern "C" {
#endif
#if defined(BSP_USING_UART1)
#ifndef UART1_CONFIG
#define UART1_CONFIG \
{ \
.name = "uart1", \
.Instance = CM_USART1, \
.clock = FCG3_PERIPH_USART1, \
.rxerr_irq.irq_config = \
{ \
.irq_num = INT010_IRQn, \
.irq_prio = DDL_IRQ_PRIO_DEFAULT, \
.int_src = INT_SRC_USART1_EI, \
}, \
.rx_irq.irq_config = \
{ \
.irq_num = INT089_IRQn, \
.irq_prio = DDL_IRQ_PRIO_DEFAULT, \
.int_src = INT_SRC_USART1_RI, \
}, \
.tx_irq.irq_config = \
{ \
.irq_num = INT088_IRQn, \
.irq_prio = DDL_IRQ_PRIO_DEFAULT, \
.int_src = INT_SRC_USART1_TI, \
}, \
}
#endif /* UART1_CONFIG */
#if defined(BSP_UART1_RX_USING_DMA)
#ifndef UART1_DMA_RX_CONFIG
#define UART1_DMA_RX_CONFIG \
{ \
.Instance = UART1_RX_DMA_INSTANCE, \
.channel = UART1_RX_DMA_CHANNEL, \
.clock = UART1_RX_DMA_CLOCK, \
.trigger_select = UART1_RX_DMA_TRIG_SELECT, \
.trigger_event = EVT_SRC_USART1_RI, \
.irq_config = \
{ \
.irq_num = UART1_RX_DMA_IRQn, \
.irq_prio = UART1_RX_DMA_INT_PRIO, \
.int_src = UART1_RX_DMA_INT_SRC, \
}, \
}
#endif /* UART1_DMA_RX_CONFIG */
#ifndef UART1_RXTO_CONFIG
#define UART1_RXTO_CONFIG \
{ \
.TMR0_Instance = CM_TMR0_1, \
.channel = TMR0_CH_A, \
.clock = FCG2_PERIPH_TMR0_1, \
.timeout_bits = 20UL, \
.irq_config = \
{ \
.irq_num = INT006_IRQn, \
.irq_prio = DDL_IRQ_PRIO_DEFAULT, \
.int_src = INT_SRC_USART1_RTO, \
}, \
}
#endif /* UART1_RXTO_CONFIG */
#endif /* BSP_UART1_RX_USING_DMA */
#if defined(BSP_UART1_TX_USING_DMA)
#ifndef UART1_TX_CPLT_CONFIG
#define UART1_TX_CPLT_CONFIG \
{ \
.irq_config = \
{ \
.irq_num = INT086_IRQn, \
.irq_prio = DDL_IRQ_PRIO_DEFAULT, \
.int_src = INT_SRC_USART1_TCI, \
}, \
}
#endif /* UART1_TX_CPLT_CONFIG */
#ifndef UART1_DMA_TX_CONFIG
#define UART1_DMA_TX_CONFIG \
{ \
.Instance = UART1_TX_DMA_INSTANCE, \
.channel = UART1_TX_DMA_CHANNEL, \
.clock = UART1_TX_DMA_CLOCK, \
.trigger_select = UART1_TX_DMA_TRIG_SELECT, \
.trigger_event = EVT_SRC_USART1_TI, \
.irq_config = \
{ \
.irq_num = UART1_TX_DMA_IRQn, \
.irq_prio = UART1_TX_DMA_INT_PRIO, \
.int_src = UART1_TX_DMA_INT_SRC, \
}, \
}
#endif /* UART1_DMA_TX_CONFIG */
#endif /* BSP_UART1_TX_USING_DMA */
#endif /* BSP_USING_UART1 */
#if defined(BSP_USING_UART2)
#ifndef UART2_CONFIG
#define UART2_CONFIG \
{ \
.name = "uart2", \
.Instance = CM_USART2, \
.clock = FCG3_PERIPH_USART2, \
.rxerr_irq.irq_config = \
{ \
.irq_num = INT011_IRQn, \
.irq_prio = DDL_IRQ_PRIO_DEFAULT, \
.int_src = INT_SRC_USART2_EI, \
}, \
.rx_irq.irq_config = \
{ \
.irq_num = INT091_IRQn, \
.irq_prio = DDL_IRQ_PRIO_DEFAULT, \
.int_src = INT_SRC_USART2_RI, \
}, \
.tx_irq.irq_config = \
{ \
.irq_num = INT090_IRQn, \
.irq_prio = DDL_IRQ_PRIO_DEFAULT, \
.int_src = INT_SRC_USART2_TI, \
}, \
}
#endif /* UART2_CONFIG */
#if defined(BSP_UART2_RX_USING_DMA)
#ifndef UART2_DMA_RX_CONFIG
#define UART2_DMA_RX_CONFIG \
{ \
.Instance = UART2_RX_DMA_INSTANCE, \
.channel = UART2_RX_DMA_CHANNEL, \
.clock = UART2_RX_DMA_CLOCK, \
.trigger_select = UART2_RX_DMA_TRIG_SELECT, \
.trigger_event = EVT_SRC_USART2_RI, \
.irq_config = \
{ \
.irq_num = UART2_RX_DMA_IRQn, \
.irq_prio = UART2_RX_DMA_INT_PRIO, \
.int_src = UART2_RX_DMA_INT_SRC, \
}, \
}
#endif /* UART2_DMA_RX_CONFIG */
#ifndef UART2_RXTO_CONFIG
#define UART2_RXTO_CONFIG \
{ \
.TMR0_Instance = CM_TMR0_1, \
.channel = TMR0_CH_B, \
.clock = FCG2_PERIPH_TMR0_1, \
.timeout_bits = 20UL, \
.irq_config = \
{ \
.irq_num = INT007_IRQn, \
.irq_prio = DDL_IRQ_PRIO_DEFAULT, \
.int_src = INT_SRC_USART2_RTO, \
}, \
}
#endif /* UART2_RXTO_CONFIG */
#endif /* BSP_UART2_RX_USING_DMA */
#if defined(BSP_UART2_TX_USING_DMA)
#ifndef UART2_TX_CPLT_CONFIG
#define UART2_TX_CPLT_CONFIG \
{ \
.irq_config = \
{ \
.irq_num = INT087_IRQn, \
.irq_prio = DDL_IRQ_PRIO_DEFAULT, \
.int_src = INT_SRC_USART2_TCI, \
}, \
}
#endif /* UART2_TX_CPLT_CONFIG */
#ifndef UART2_DMA_TX_CONFIG
#define UART2_DMA_TX_CONFIG \
{ \
.Instance = UART2_TX_DMA_INSTANCE, \
.channel = UART2_TX_DMA_CHANNEL, \
.clock = UART2_TX_DMA_CLOCK, \
.trigger_select = UART2_TX_DMA_TRIG_SELECT, \
.trigger_event = EVT_SRC_USART2_TI, \
.irq_config = \
{ \
.irq_num = UART2_TX_DMA_IRQn, \
.irq_prio = UART2_TX_DMA_INT_PRIO, \
.int_src = UART2_TX_DMA_INT_SRC, \
}, \
}
#endif /* UART2_DMA_TX_CONFIG */
#endif /* BSP_UART2_TX_USING_DMA */
#endif /* BSP_USING_UART2 */
#if defined(BSP_USING_UART3)
#ifndef UART3_CONFIG
#define UART3_CONFIG \
{ \
.name = "uart3", \
.Instance = CM_USART3, \
.clock = FCG3_PERIPH_USART3, \
.rxerr_irq.irq_config = \
{ \
.irq_num = INT012_IRQn, \
.irq_prio = DDL_IRQ_PRIO_DEFAULT, \
.int_src = INT_SRC_USART3_EI, \
}, \
.rx_irq.irq_config = \
{ \
.irq_num = INT095_IRQn, \
.irq_prio = DDL_IRQ_PRIO_DEFAULT, \
.int_src = INT_SRC_USART3_RI, \
}, \
.tx_irq.irq_config = \
{ \
.irq_num = INT094_IRQn, \
.irq_prio = DDL_IRQ_PRIO_DEFAULT, \
.int_src = INT_SRC_USART3_TI, \
}, \
}
#endif /* UART3_CONFIG */
#endif /* BSP_USING_UART3 */
#if defined(BSP_USING_UART4)
#ifndef UART4_CONFIG
#define UART4_CONFIG \
{ \
.name = "uart4", \
.Instance = CM_USART4, \
.clock = FCG3_PERIPH_USART4, \
.rxerr_irq.irq_config = \
{ \
.irq_num = INT013_IRQn, \
.irq_prio = DDL_IRQ_PRIO_DEFAULT, \
.int_src = INT_SRC_USART4_EI, \
}, \
.rx_irq.irq_config = \
{ \
.irq_num = INT097_IRQn, \
.irq_prio = DDL_IRQ_PRIO_DEFAULT, \
.int_src = INT_SRC_USART4_RI, \
}, \
.tx_irq.irq_config = \
{ \
.irq_num = INT096_IRQn, \
.irq_prio = DDL_IRQ_PRIO_DEFAULT, \
.int_src = INT_SRC_USART4_TI, \
}, \
}
#endif /* UART4_CONFIG */
#endif /* BSP_USING_UART4 */
#if defined(BSP_USING_UART5)
#ifndef UART5_CONFIG
#define UART5_CONFIG \
{ \
.name = "uart5", \
.Instance = CM_USART5, \
.clock = FCG3_PERIPH_USART5, \
.rxerr_irq.irq_config = \
{ \
.irq_num = INT014_IRQn, \
.irq_prio = DDL_IRQ_PRIO_DEFAULT, \
.int_src = INT_SRC_USART5_EI, \
}, \
.rx_irq.irq_config = \
{ \
.irq_num = INT101_IRQn, \
.irq_prio = DDL_IRQ_PRIO_DEFAULT, \
.int_src = INT_SRC_USART5_RI, \
}, \
.tx_irq.irq_config = \
{ \
.irq_num = INT100_IRQn, \
.irq_prio = DDL_IRQ_PRIO_DEFAULT, \
.int_src = INT_SRC_USART5_TI, \
}, \
}
#endif /* UART5_CONFIG */
#endif /* BSP_USING_UART5 */
#if defined(BSP_USING_UART6)
#ifndef UART6_CONFIG
#define UART6_CONFIG \
{ \
.name = "uart6", \
.Instance = CM_USART6, \
.clock = FCG3_PERIPH_USART6, \
.rxerr_irq.irq_config = \
{ \
.irq_num = INT015_IRQn, \
.irq_prio = DDL_IRQ_PRIO_DEFAULT, \
.int_src = INT_SRC_USART6_EI, \
}, \
.rx_irq.irq_config = \
{ \
.irq_num = INT103_IRQn, \
.irq_prio = DDL_IRQ_PRIO_DEFAULT, \
.int_src = INT_SRC_USART6_RI, \
}, \
.tx_irq.irq_config = \
{ \
.irq_num = INT102_IRQn, \
.irq_prio = DDL_IRQ_PRIO_DEFAULT, \
.int_src = INT_SRC_USART6_TI, \
}, \
}
#endif /* UART6_CONFIG */
#if defined(BSP_UART6_RX_USING_DMA)
#ifndef UART6_DMA_RX_CONFIG
#define UART6_DMA_RX_CONFIG \
{ \
.Instance = UART6_RX_DMA_INSTANCE, \
.channel = UART6_RX_DMA_CHANNEL, \
.clock = UART6_RX_DMA_CLOCK, \
.trigger_select = UART6_RX_DMA_TRIG_SELECT, \
.trigger_event = EVT_SRC_USART6_RI, \
.irq_config = \
{ \
.irq_num = UART6_RX_DMA_IRQn, \
.irq_prio = UART6_RX_DMA_INT_PRIO, \
.int_src = UART6_RX_DMA_INT_SRC, \
}, \
}
#endif /* UART6_DMA_RX_CONFIG */
#ifndef UART6_RXTO_CONFIG
#define UART6_RXTO_CONFIG \
{ \
.TMR0_Instance = CM_TMR0_2, \
.channel = TMR0_CH_A, \
.clock = FCG2_PERIPH_TMR0_2, \
.timeout_bits = 20UL, \
.irq_config = \
{ \
.irq_num = INT008_IRQn, \
.irq_prio = DDL_IRQ_PRIO_DEFAULT, \
.int_src = INT_SRC_USART6_RTO, \
}, \
}
#endif /* UART6_RXTO_CONFIG */
#endif /* BSP_UART6_RX_USING_DMA */
#if defined(BSP_UART6_TX_USING_DMA)
#ifndef UART6_TX_CPLT_CONFIG
#define UART6_TX_CPLT_CONFIG \
{ \
.irq_config = \
{ \
.irq_num = INT099_IRQn, \
.irq_prio = DDL_IRQ_PRIO_DEFAULT, \
.int_src = INT_SRC_USART6_TCI, \
}, \
}
#endif /* UART6_TX_CPLT_CONFIG */
#ifndef UART6_DMA_TX_CONFIG
#define UART6_DMA_TX_CONFIG \
{ \
.Instance = UART6_TX_DMA_INSTANCE, \
.channel = UART6_TX_DMA_CHANNEL, \
.clock = UART6_TX_DMA_CLOCK, \
.trigger_select = UART6_TX_DMA_TRIG_SELECT, \
.trigger_event = EVT_SRC_USART6_TI, \
.irq_config = \
{ \
.irq_num = UART6_TX_DMA_IRQn, \
.irq_prio = UART6_TX_DMA_INT_PRIO, \
.int_src = UART6_TX_DMA_INT_SRC, \
}, \
}
#endif /* UART6_DMA_TX_CONFIG */
#endif /* BSP_UART6_TX_USING_DMA */
#endif /* BSP_USING_UART6 */
#if defined(BSP_USING_UART7)
#ifndef UART7_CONFIG
#define UART7_CONFIG \
{ \
.name = "uart7", \
.Instance = CM_USART7, \
.clock = FCG3_PERIPH_USART7, \
.rxerr_irq.irq_config = \
{ \
.irq_num = INT016_IRQn, \
.irq_prio = DDL_IRQ_PRIO_DEFAULT, \
.int_src = INT_SRC_USART7_EI, \
}, \
.rx_irq.irq_config = \
{ \
.irq_num = INT107_IRQn, \
.irq_prio = DDL_IRQ_PRIO_DEFAULT, \
.int_src = INT_SRC_USART7_RI, \
}, \
.tx_irq.irq_config = \
{ \
.irq_num = INT106_IRQn, \
.irq_prio = DDL_IRQ_PRIO_DEFAULT, \
.int_src = INT_SRC_USART7_TI, \
}, \
}
#endif /* UART7_CONFIG */
#if defined(BSP_UART7_RX_USING_DMA)
#ifndef UART7_DMA_RX_CONFIG
#define UART7_DMA_RX_CONFIG \
{ \
.Instance = UART7_RX_DMA_INSTANCE, \
.channel = UART7_RX_DMA_CHANNEL, \
.clock = UART7_RX_DMA_CLOCK, \
.trigger_select = UART7_RX_DMA_TRIG_SELECT, \
.trigger_event = EVT_SRC_USART7_RI, \
.irq_config = \
{ \
.irq_num = UART7_RX_DMA_IRQn, \
.irq_prio = UART7_RX_DMA_INT_PRIO, \
.int_src = UART7_RX_DMA_INT_SRC, \
}, \
}
#endif /* UART7_DMA_RX_CONFIG */
#ifndef UART7_RXTO_CONFIG
#define UART7_RXTO_CONFIG \
{ \
.TMR0_Instance = CM_TMR0_2, \
.channel = TMR0_CH_B, \
.clock = FCG2_PERIPH_TMR0_2, \
.timeout_bits = 20UL, \
.irq_config = \
{ \
.irq_num = INT009_IRQn, \
.irq_prio = DDL_IRQ_PRIO_DEFAULT, \
.int_src = INT_SRC_USART7_RTO, \
}, \
}
#endif /* UART6_RXTO_CONFIG */
#endif /* BSP_UART7_RX_USING_DMA */
#if defined(BSP_UART7_TX_USING_DMA)
#ifndef UART7_TX_CPLT_CONFIG
#define UART7_TX_CPLT_CONFIG \
{ \
.irq_config = \
{ \
.irq_num = INT105_IRQn, \
.irq_prio = DDL_IRQ_PRIO_DEFAULT, \
.int_src = INT_SRC_USART6_TCI, \
}, \
}
#endif /* UART7_TX_CPLT_CONFIG */
#ifndef UART7_DMA_TX_CONFIG
#define UART7_DMA_TX_CONFIG \
{ \
.Instance = UART7_TX_DMA_INSTANCE, \
.channel = UART7_TX_DMA_CHANNEL, \
.clock = UART7_TX_DMA_CLOCK, \
.trigger_select = UART7_TX_DMA_TRIG_SELECT, \
.trigger_event = EVT_SRC_USART7_TI, \
.irq_config = \
{ \
.irq_num = UART7_TX_DMA_IRQn, \
.irq_prio = UART7_TX_DMA_INT_PRIO, \
.int_src = UART7_TX_DMA_INT_SRC, \
}, \
}
#endif /* UART7_DMA_TX_CONFIG */
#endif /* BSP_UART7_RX_USING_DMA */
#endif /* BSP_USING_UART7 */
#if defined(BSP_USING_UART8)
#ifndef UART8_CONFIG
#define UART8_CONFIG \
{ \
.name = "uart8", \
.Instance = CM_USART8, \
.clock = FCG3_PERIPH_USART8, \
.rxerr_irq.irq_config = \
{ \
.irq_num = INT017_IRQn, \
.irq_prio = DDL_IRQ_PRIO_DEFAULT, \
.int_src = INT_SRC_USART8_EI, \
}, \
.rx_irq.irq_config = \
{ \
.irq_num = INT109_IRQn, \
.irq_prio = DDL_IRQ_PRIO_DEFAULT, \
.int_src = INT_SRC_USART8_RI, \
}, \
.tx_irq.irq_config = \
{ \
.irq_num = INT108_IRQn, \
.irq_prio = DDL_IRQ_PRIO_DEFAULT, \
.int_src = INT_SRC_USART8_TI, \
}, \
}
#endif /* UART8_CONFIG */
#endif /* BSP_USING_UART8 */
#if defined(BSP_USING_UART9)
#ifndef UART9_CONFIG
#define UART9_CONFIG \
{ \
.name = "uart9", \
.Instance = CM_USART9, \
.clock = FCG3_PERIPH_USART9, \
.rxerr_irq.irq_config = \
{ \
.irq_num = INT112_IRQn, \
.irq_prio = DDL_IRQ_PRIO_DEFAULT, \
.int_src = INT_SRC_USART9_EI, \
}, \
.rx_irq.irq_config = \
{ \
.irq_num = INT110_IRQn, \
.irq_prio = DDL_IRQ_PRIO_DEFAULT, \
.int_src = INT_SRC_USART9_RI, \
}, \
.tx_irq.irq_config = \
{ \
.irq_num = INT111_IRQn, \
.irq_prio = DDL_IRQ_PRIO_DEFAULT, \
.int_src = INT_SRC_USART9_TI, \
}, \
}
#endif /* UART9_CONFIG */
#endif /* BSP_USING_UART9 */
#if defined(BSP_USING_UART10)
#ifndef UART10_CONFIG
#define UART10_CONFIG \
{ \
.name = "uart10", \
.Instance = CM_USART10, \
.clock = FCG3_PERIPH_USART10, \
.rxerr_irq.irq_config = \
{ \
.irq_num = INT115_IRQn, \
.irq_prio = DDL_IRQ_PRIO_DEFAULT, \
.int_src = INT_SRC_USART7_EI, \
}, \
.rx_irq.irq_config = \
{ \
.irq_num = INT114_IRQn, \
.irq_prio = DDL_IRQ_PRIO_DEFAULT, \
.int_src = INT_SRC_USART7_RI, \
}, \
.tx_irq.irq_config = \
{ \
.irq_num = INT113_IRQn, \
.irq_prio = DDL_IRQ_PRIO_DEFAULT, \
.int_src = INT_SRC_USART7_TI, \
}, \
}
#endif /* UART10_CONFIG */
#endif /* BSP_USING_UART10 */
#ifdef __cplusplus
}
#endif
#endif

34
bsp/hc32/ev_hc32f4a0_lqfp176/board/drv_config.h Normal file
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/*
* Copyright (C) 2022, Xiaohua Semiconductor Co., Ltd.
*
* SPDX-License-Identifier: Apache-2.0
*
* Change Logs:
* Date Author Notes
* 2022-04-28 CDT first version
*/
#ifndef __DRV_CONFIG_H__
#define __DRV_CONFIG_H__
#include <board.h>
#include <rtthread.h>
#ifdef __cplusplus
extern "C" {
#endif
#include "config/dma_config.h"
#include "config/uart_config.h"
#include "config/spi_config.h"
#include "config/adc_config.h"
#include "config/tim_config.h"
#include "config/gpio_config.h"
#include "config/eth_config.h"
#include "config/can_config.h"
#ifdef __cplusplus
}
#endif
#endif

210
bsp/hc32/ev_hc32f4a0_lqfp176/board/hc32f4xx_conf.h Normal file
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/**
*******************************************************************************
* @file template/source/hc32f4xx_conf.h
* @brief This file contains HC32 Series Device Driver Library usage management.
@verbatim
Change Logs:
Date Author Notes
2022-04-28 CDT First version
@endverbatim
*******************************************************************************
* Copyright (C) 2022, Xiaohua Semiconductor Co., Ltd. Ltd. All rights reserved.
*
* This software component is licensed by XHSC under BSD 3-Clause license
* (the "License"); You may not use this file except in compliance with the
* License. You may obtain a copy of the License at:
* opensource.org/licenses/BSD-3-Clause
*
*******************************************************************************
*/
#ifndef __HC32F4XX_CONF_H__
#define __HC32F4XX_CONF_H__
/*******************************************************************************
* Include files
******************************************************************************/
/* C binding of definitions if building with C++ compiler */
#ifdef __cplusplus
extern "C"
{
#endif
/*******************************************************************************
* Global type definitions ('typedef')
******************************************************************************/
/*******************************************************************************
* Global pre-processor symbols/macros ('#define')
******************************************************************************/
/**
* @brief This is the list of modules to be used in the Device Driver Library.
* Select the modules you need to use to DDL_ON.
* @note LL_ICG_ENABLE must be turned on(DDL_ON) to ensure that the chip works
* properly.
* @note LL_UTILITY_ENABLE must be turned on(DDL_ON) if using Device Driver
* Library.
* @note LL_PRINT_ENABLE must be turned on(DDL_ON) if using printf function.
*/
#define LL_ICG_ENABLE (DDL_ON)
#define LL_UTILITY_ENABLE (DDL_ON)
#define LL_PRINT_ENABLE (DDL_OFF)
#define LL_ADC_ENABLE (DDL_ON)
#define LL_AES_ENABLE (DDL_ON)
#define LL_AOS_ENABLE (DDL_ON)
#define LL_CAN_ENABLE (DDL_ON)
#define LL_CLK_ENABLE (DDL_ON)
#define LL_CMP_ENABLE (DDL_ON)
#define LL_CRC_ENABLE (DDL_ON)
#define LL_CTC_ENABLE (DDL_ON)
#define LL_DAC_ENABLE (DDL_ON)
#define LL_DCU_ENABLE (DDL_ON)
#define LL_DMA_ENABLE (DDL_ON)
#define LL_DMC_ENABLE (DDL_ON)
#define LL_DVP_ENABLE (DDL_ON)
#define LL_EFM_ENABLE (DDL_ON)
#define LL_EMB_ENABLE (DDL_ON)
#define LL_ETH_ENABLE (DDL_ON)
#define LL_EVENT_PORT_ENABLE (DDL_OFF)
#define LL_FCG_ENABLE (DDL_ON)
#define LL_FCM_ENABLE (DDL_ON)
#define LL_FMAC_ENABLE (DDL_ON)
#define LL_GPIO_ENABLE (DDL_ON)
#define LL_HASH_ENABLE (DDL_ON)
#define LL_HRPWM_ENABLE (DDL_ON)
#define LL_I2C_ENABLE (DDL_ON)
#define LL_I2S_ENABLE (DDL_ON)
#define LL_INTERRUPTS_ENABLE (DDL_ON)
#define LL_INTERRUPTS_SHARE_ENABLE (DDL_ON)
#define LL_KEYSCAN_ENABLE (DDL_ON)
#define LL_MAU_ENABLE (DDL_ON)
#define LL_MDIO_ENABLE (DDL_OFF)
#define LL_MPU_ENABLE (DDL_ON)
#define LL_NFC_ENABLE (DDL_ON)
#define LL_OTS_ENABLE (DDL_ON)
#define LL_PLA_ENABLE (DDL_OFF)
#define LL_PWC_ENABLE (DDL_ON)
#define LL_QSPI_ENABLE (DDL_ON)
#define LL_RMU_ENABLE (DDL_ON)
#define LL_RTC_ENABLE (DDL_ON)
#define LL_SDIOC_ENABLE (DDL_ON)
#define LL_SMC_ENABLE (DDL_ON)
#define LL_SPI_ENABLE (DDL_ON)
#define LL_SRAM_ENABLE (DDL_ON)
#define LL_SWDT_ENABLE (DDL_ON)
#define LL_TMR0_ENABLE (DDL_ON)
#define LL_TMR2_ENABLE (DDL_ON)
#define LL_TMR4_ENABLE (DDL_ON)
#define LL_TMR6_ENABLE (DDL_ON)
#define LL_TMRA_ENABLE (DDL_ON)
#define LL_TRNG_ENABLE (DDL_ON)
#define LL_USART_ENABLE (DDL_ON)
#define LL_USB_ENABLE (DDL_OFF)
#define LL_VREF_ENABLE (DDL_OFF)
#define LL_WDT_ENABLE (DDL_ON)
/**
* @brief The following is a list of currently supported BSP boards.
*/
#define BSP_EV_HC32F4A0_LQFP176 (1U)
#define BSP_EV_HC32F4A0_LQFP176_MEM (2U)
#define BSP_EV_HC32F460_LQFP100_V1 (3U)
#define BSP_EV_HC32F460_LQFP100_V2 (4U)
#define BSP_EV_HC32F451_LQFP100 (5U)
#define BSP_EV_HC32F452_LQFP100 (6U)
#define BSP_EV_HC32F472_LQFP100 (7U)
#define BSP_SK_HC32F4A0_LQFP100 (8U)
/**
* @brief The macro BSP_EV_HC32F4XX is used to specify the BSP board currently
* in use.
* The value should be set to one of the list of currently supported BSP boards.
* @note If there is no supported BSP board or the BSP function is not used,
* the value needs to be set to 0U.
*/
#define BSP_EV_HC32F4XX (BSP_EV_HC32F4A0_LQFP176)
/**
* @brief This is the list of BSP components to be used.
* Select the components you need to use to DDL_ON.
*/
#define BSP_24CXX_ENABLE (DDL_OFF)
#define BSP_CY62167EV30LL_ENABLE (DDL_OFF)
#define BSP_IS42S16400J7TLI_ENABLE (DDL_OFF)
#define BSP_IS62WV51216_ENABLE (DDL_OFF)
#define BSP_MT29F2G08AB_ENABLE (DDL_OFF)
#define BSP_NT35510_ENABLE (DDL_OFF)
#define BSP_OV5640_ENABLE (DDL_OFF)
#define BSP_S29GL064N90TFI03_ENABLE (DDL_OFF)
#define BSP_TCA9539_ENABLE (DDL_OFF)
#define BSP_W25QXX_ENABLE (DDL_OFF)
#define BSP_WM8731_ENABLE (DDL_OFF)
/**
* @brief Ethernet and PHY Configuration.
*/
/* MAC ADDRESS */
#define ETH_MAC_ADDR0 (0x02U)
#define ETH_MAC_ADDR1 (0x00U)
#define ETH_MAC_ADDR2 (0x00U)
#define ETH_MAC_ADDR3 (0x00U)
#define ETH_MAC_ADDR4 (0x00U)
#define ETH_MAC_ADDR5 (0x00U)
/* PHY(RTL8201F) Address*/
#define ETH_PHY_ADDR (0x00U)
/* PHY Configuration delay(ms) */
#define ETH_PHY_RST_DELAY (0x0080UL)
#define ETH_PHY_CONFIG_DELAY (0x0040UL)
#define ETH_PHY_RD_TIMEOUT (0x0005UL)
#define ETH_PHY_WR_TIMEOUT (0x0005UL)
/* Common PHY Registers */
#define PHY_BCR (0x00U) /*!< Basic Control Register */
#define PHY_BSR (0x01U) /*!< Basic Status Register */
#define PHY_SOFT_RESET (0x8000U) /*!< PHY Soft Reset */
#define PHY_LOOPBACK (0x4000U) /*!< Select loop-back mode */
#define PHY_FULLDUPLEX_100M (0x2100U) /*!< SET the full-duplex mode at 100 Mb/s */
#define PHY_HALFDUPLEX_100M (0x2000U) /*!< SET the half-duplex mode at 100 Mb/s */
#define PHY_FULLDUPLEX_10M (0x0100U) /*!< SET the full-duplex mode at 10 Mb/s */
#define PHY_HALFDUPLEX_10M (0x0000U) /*!< SET the half-duplex mode at 10 Mb/s */
#define PHY_AUTONEGOTIATION (0x1000U) /*!< Enable auto-negotiation function */
#define PHY_POWERDOWN (0x0800U) /*!< Select the power down mode */
#define PHY_ISOLATE (0x0400U) /*!< Isolate PHY from MII */
#define PHY_RESTART_AUTONEGOTIATION (0x0200U) /*!< Restart auto-negotiation function */
#define PHY_100BASE_TX_FD (0x4000U) /*!< 100Base-TX full duplex support */
#define PHY_100BASE_TX_HD (0x2000U) /*!< 100Base-TX half duplex support */
#define PHY_10BASE_T_FD (0x1000U) /*!< 10Base-T full duplex support */
#define PHY_10BASE_T_HD (0x0800U) /*!< 10Base-T half duplex support */
#define PHY_AUTONEGO_COMPLETE (0x0020U) /*!< Auto-Negotiation process completed */
#define PHY_LINK_STATUS (0x0004U) /*!< Valid link established */
#define PHY_JABBER_DETECTION (0x0002U) /*!< Jabber condition detected */
/**
* @brief The macro is used to re-define main function in system_device.c(eg. device=hc32f4a0).
* @note Set value to non-zero if re-define main function.
*/
#define RE_DEFINE_MAIN (0)
/*******************************************************************************
* Global variable definitions ('extern')
******************************************************************************/
/*******************************************************************************
* Global function prototypes (definition in C source)
******************************************************************************/
#ifdef __cplusplus
}
#endif
#endif /* __HC32F4XX_CONF_H__ */
/*******************************************************************************
* EOF (not truncated)
******************************************************************************/

51
bsp/hc32/ev_hc32f4a0_lqfp176/board/linker_scripts/link.icf Normal file
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/*###ICF### Section handled by ICF editor, don't touch! ****/
/*-Editor annotation file-*/
/* IcfEditorFile="$TOOLKIT_DIR$\config\ide\IcfEditor\cortex_v1_4.xml" */
/*-Specials-*/
define symbol __ICFEDIT_intvec_start__ = 0x00000000;
/*-Memory Regions-*/
define symbol __ICFEDIT_region_IROM1_start__ = 0x00000000;
define symbol __ICFEDIT_region_IROM1_end__ = 0x001FFFFF;
define symbol __ICFEDIT_region_IROM2_start__ = 0x03000000;
define symbol __ICFEDIT_region_IROM2_end__ = 0x030017FF;
define symbol __ICFEDIT_region_EROM1_start__ = 0x0;
define symbol __ICFEDIT_region_EROM1_end__ = 0x0;
define symbol __ICFEDIT_region_EROM2_start__ = 0x0;
define symbol __ICFEDIT_region_EROM2_end__ = 0x0;
define symbol __ICFEDIT_region_EROM3_start__ = 0x0;
define symbol __ICFEDIT_region_EROM3_end__ = 0x0;
define symbol __ICFEDIT_region_IRAM1_start__ = 0x1FFE0000;
define symbol __ICFEDIT_region_IRAM1_end__ = 0x2005FFFF;
define symbol __ICFEDIT_region_IRAM2_start__ = 0x200F0000;
define symbol __ICFEDIT_region_IRAM2_end__ = 0x200F0FFF;
define symbol __ICFEDIT_region_ERAM1_start__ = 0x0;
define symbol __ICFEDIT_region_ERAM1_end__ = 0x0;
define symbol __ICFEDIT_region_ERAM2_start__ = 0x0;
define symbol __ICFEDIT_region_ERAM2_end__ = 0x0;
define symbol __ICFEDIT_region_ERAM3_start__ = 0x0;
define symbol __ICFEDIT_region_ERAM3_end__ = 0x0;
/*-Sizes-*/
define symbol __ICFEDIT_size_cstack__ = 0x2000;
define symbol __ICFEDIT_size_proc_stack__ = 0x0;
define symbol __ICFEDIT_size_heap__ = 0x2000;
/**** End of ICF editor section. ###ICF###*/
define memory mem with size = 4G;
define region ROM_region = mem:[from __ICFEDIT_region_IROM1_start__ to __ICFEDIT_region_IROM1_end__]
| mem:[from __ICFEDIT_region_IROM2_start__ to __ICFEDIT_region_IROM2_end__];
define region RAM_region = mem:[from __ICFEDIT_region_IRAM1_start__ to __ICFEDIT_region_IRAM1_end__]
| mem:[from __ICFEDIT_region_IRAM2_start__ to __ICFEDIT_region_IRAM2_end__];
define block CSTACK with alignment = 8, size = __ICFEDIT_size_cstack__ { };
define block HEAP with alignment = 8, size = __ICFEDIT_size_heap__ { };
initialize by copy { readwrite };
do not initialize { section .noinit };
place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec };
place in ROM_region { readonly };
place in RAM_region { readwrite,
block CSTACK, block HEAP };

267
bsp/hc32/ev_hc32f4a0_lqfp176/board/linker_scripts/link.ld Normal file
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/******************************************************************************
* Copyright (C) 2022, Xiaohua Semiconductor Co., Ltd. Ltd. All rights reserved.
*
* This software component is licensed by XHSC under BSD 3-Clause license
* (the "License"); You may not use this file except in compliance with the
* License. You may obtain a copy of the License at:
* opensource.org/licenses/BSD-3-Clause
*
*/
/*****************************************************************************/
/* File HC32F4A0xI.ld */
/* Abstract Linker script for HC32F4A0 Device with */
/* 2MByte FLASH, 516KByte RAM */
/* Version V1.0 */
/* Date 2022-04-28 */
/*****************************************************************************/
/* Custom defines, according to section 7.7 of the user manual.
Take OTP sector 16 for example. */
__OTP_DATA_START = 0x03000000;
__OTP_DATA_SIZE = 2048;
__OTP_LOCK_START = 0x03001840;
__OTP_LOCK_SIZE = 4;
/* Use contiguous memory regions for simple. */
MEMORY
{
FLASH (rx): ORIGIN = 0x00000000, LENGTH = 2M
OTP_DATA (rx): ORIGIN = __OTP_DATA_START, LENGTH = __OTP_DATA_SIZE
OTP_LOCK (rx): ORIGIN = __OTP_LOCK_START, LENGTH = __OTP_LOCK_SIZE
RAM (rwx): ORIGIN = 0x1FFE0000, LENGTH = 512K
RAMB (rwx): ORIGIN = 0x200F0000, LENGTH = 4K
}
ENTRY(Reset_Handler)
SECTIONS
{
.vectors :
{
. = ALIGN(4);
KEEP(*(.vectors))
. = ALIGN(4);
} >FLASH
.icg_sec 0x00000400 :
{
KEEP(*(.icg_sec))
} >FLASH
.text :
{
. = ALIGN(4);
_stext = .;
KEEP(*(.isr_vector)) /* Startup code */
. = ALIGN(4);
*(.text) /* remaining code */
*(.text.*) /* remaining code */
*(.rodata) /* read-only data (constants) */
*(.rodata*)
*(.glue_7)
*(.glue_7t)
*(.gnu.linkonce.t*)
/* section information for finsh shell */
. = ALIGN(4);
__fsymtab_start = .;
KEEP(*(FSymTab))
__fsymtab_end = .;
. = ALIGN(4);
__vsymtab_start = .;
KEEP(*(VSymTab))
__vsymtab_end = .;
. = ALIGN(4);
/* section information for initial. */
. = ALIGN(4);
__rt_init_start = .;
KEEP(*(SORT(.rti_fn*)))
__rt_init_end = .;
. = ALIGN(4);
. = ALIGN(4);
_etext = .;
} >FLASH
.rodata :
{
. = ALIGN(4);
*(.rodata)
*(.rodata*)
. = ALIGN(4);
} >FLASH
.ARM.extab :
{
*(.ARM.extab* .gnu.linkonce.armextab.*)
} >FLASH
__exidx_start = .;
.ARM.exidx :
{
*(.ARM.exidx* .gnu.linkonce.armexidx.*)
} >FLASH
__exidx_end = .;
.preinit_array :
{
. = ALIGN(4);
/* preinit data */
PROVIDE_HIDDEN (__preinit_array_start = .);
KEEP(*(.preinit_array))
PROVIDE_HIDDEN (__preinit_array_end = .);
. = ALIGN(4);
} >FLASH
.init_array :
{
. = ALIGN(4);
/* init data */
PROVIDE_HIDDEN (__init_array_start = .);
KEEP(*(SORT(.init_array.*)))
KEEP(*(.init_array))
PROVIDE_HIDDEN (__init_array_end = .);
. = ALIGN(4);
} >FLASH
.fini_array :
{
. = ALIGN(4);
/* finit data */
PROVIDE_HIDDEN (__fini_array_start = .);
KEEP(*(SORT(.fini_array.*)))
KEEP(*(.fini_array))
PROVIDE_HIDDEN (__fini_array_end = .);
. = ALIGN(4);
} >FLASH
__etext = ALIGN(4);
.otp_data_sec :
{
KEEP(*(.otp_data_sec))
} >OTP_DATA
.otp_lock_sec :
{
KEEP(*(.otp_lock_sec))
} >OTP_LOCK
.data : AT (__etext)
{
. = ALIGN(4);
__data_start__ = .;
*(vtable)
*(.data)
*(.data*)
*(.gnu.linkonce.d*)
. = ALIGN(4);
*(.ramfunc)
*(.ramfunc*)
. = ALIGN(4);
__data_end__ = .;
} >RAM
__etext_ramb = __etext + ALIGN (SIZEOF(.data), 4);
.ramb_data : AT (__etext_ramb)
{
. = ALIGN(4);
__data_start_ramb__ = .;
*(.ramb_data)
*(.ramb_data*)
. = ALIGN(4);
__data_end_ramb__ = .;
} >RAMB
__bss_start = .;
.bss :
{
. = ALIGN(4);
_sbss = .;
__bss_start__ = _sbss;
*(.bss)
*(.bss*)
*(COMMON)
. = ALIGN(4);
_ebss = .;
__bss_end__ = _ebss;
} >RAM
__bss_end = .;
.ramb_bss :
{
. = ALIGN(4);
__bss_start_ramb__ = .;
*(.ramb_bss)
*(.ramb_bss*)
. = ALIGN(4);
__bss_end_ramb__ = .;
} >RAMB
.heap_stack (COPY) :
{
. = ALIGN(8);
__end__ = .;
PROVIDE(end = .);
PROVIDE(_end = .);
*(.heap*)
. = ALIGN(8);
__HeapLimit = .;
__StackLimit = .;
*(.stack*)
. = ALIGN(8);
__StackTop = .;
} >RAM
/DISCARD/ :
{
libc.a (*)
libm.a (*)
libgcc.a (*)
}
.ARM.attributes 0 : { *(.ARM.attributes) }
PROVIDE(_stack = __StackTop);
PROVIDE(_Min_Heap_Size = __HeapLimit - __HeapBase);
PROVIDE(_Min_Stack_Size = __StackTop - __StackLimit);
__RamEnd = ORIGIN(RAM) + LENGTH(RAM);
ASSERT(__StackTop <= __RamEnd, "region RAM overflowed with stack")
/* Stabs debugging sections. */
.stab 0 : { *(.stab) }
.stabstr 0 : { *(.stabstr) }
.stab.excl 0 : { *(.stab.excl) }
.stab.exclstr 0 : { *(.stab.exclstr) }
.stab.index 0 : { *(.stab.index) }
.stab.indexstr 0 : { *(.stab.indexstr) }
.comment 0 : { *(.comment) }
/* DWARF debug sections.
* Symbols in the DWARF debugging sections are relative to the beginning
* of the section so we begin them at 0. */
/* DWARF 1 */
.debug 0 : { *(.debug) }
.line 0 : { *(.line) }
/* GNU DWARF 1 extensions */
.debug_srcinfo 0 : { *(.debug_srcinfo) }
.debug_sfnames 0 : { *(.debug_sfnames) }
/* DWARF 1.1 and DWARF 2 */
.debug_aranges 0 : { *(.debug_aranges) }
.debug_pubnames 0 : { *(.debug_pubnames) }
/* DWARF 2 */
.debug_info 0 : { *(.debug_info .gnu.linkonce.wi.*) }
.debug_abbrev 0 : { *(.debug_abbrev) }
.debug_line 0 : { *(.debug_line) }
.debug_frame 0 : { *(.debug_frame) }
.debug_str 0 : { *(.debug_str) }
.debug_loc 0 : { *(.debug_loc) }
.debug_macinfo 0 : { *(.debug_macinfo) }
/* SGI/MIPS DWARF 2 extensions */
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.debug_funcnames 0 : { *(.debug_funcnames) }
.debug_typenames 0 : { *(.debug_typenames) }
.debug_varnames 0 : { *(.debug_varnames) }
}

15
bsp/hc32/ev_hc32f4a0_lqfp176/board/linker_scripts/link.sct Normal file
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; ****************************************************************
; Scatter-Loading Description File
; ****************************************************************
LR_IROM1 0x00000000 0x00200000 { ; load region size_region
ER_IROM1 0x00000000 0x00200000 { ; load address = execution address
*.o (RESET, +First)
*(InRoot$$Sections)
.ANY (+RO)
.ANY (+XO)
}
RW_IRAM1 0x1FFE0000 0x00080000 { ; RW data
.ANY (+RW +ZI)
}
}

46
bsp/hc32/ev_hc32f4a0_lqfp176/board/ports/spi_flash.c Normal file
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/*
* Copyright (C) 2022, Xiaohua Semiconductor Co., Ltd.
*
* SPDX-License-Identifier: Apache-2.0
*
* Change Logs:
* Date Author Notes
* 2022-04-28 CDT first version
*/
#include <rtthread.h>
#include "drv_spi.h"
#if defined(BSP_USING_SPI_FLASH)
/*******************************************************************************
* Local type definitions ('typedef')
******************************************************************************/
/*******************************************************************************
* Local pre-processor symbols/macros ('#define')
******************************************************************************/
/*******************************************************************************
* Global variable definitions (declared in header file with 'extern')
******************************************************************************/
/*******************************************************************************
* Local function prototypes ('static')
******************************************************************************/
/*******************************************************************************
* Local variable definitions ('static')
******************************************************************************/
/*******************************************************************************
* Function implementation - global ('extern') and local ('static')
******************************************************************************/
static int rt_hw_spi_flash_init(void)
{
rt_hw_spi_device_attach("spi1", "spi10", GPIO_PORT_C, GPIO_PIN_07);
return RT_EOK;
}
INIT_COMPONENT_EXPORT(rt_hw_spi_flash_init);
#endif

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/*
* Copyright (C) 2022, Xiaohua Semiconductor Co., Ltd.
*
* SPDX-License-Identifier: Apache-2.0
*
* Change Logs:
* Date Author Notes
* 2022-04-28 CDT first version
*/
#include <rtthread.h>
#include <rtdevice.h>
#include <rtdbg.h>
#ifdef BSP_USING_TCA9539
#include "tca9539.h"
/*******************************************************************************
* Local type definitions ('typedef')
******************************************************************************/
/*******************************************************************************
* Local pre-processor symbols/macros ('#define')
******************************************************************************/
/* Define for TCA9539 */
#define BSP_TCA9539_I2C_BUS_NAME "i2c1"
#define BSP_TCA9539_DEV_ADDR (0x74U)
#define TCA9539_RST_PIN (45) /* PC13 */
/*******************************************************************************
* Global variable definitions (declared in header file with 'extern')
******************************************************************************/
/*******************************************************************************
* Local function prototypes ('static')
******************************************************************************/
/*******************************************************************************
* Local variable definitions ('static')
******************************************************************************/
static struct rt_i2c_bus_device *i2c_bus = RT_NULL;
/*******************************************************************************
* Function implementation - global ('extern') and local ('static')
******************************************************************************/
/**
* @brief BSP TCA9539 write data.
* @param [in] bus: Pointer to the i2c bus device.
* @param [in] reg: Register to be written.
* @param [in] data: The pointer to the buffer contains the data to be written.
* @param [in] len: Buffer size in byte.
* @retval rt_err_t:
* - RT_EOK
* - -RT_ERROR
*/
static rt_err_t BSP_TCA9539_I2C_Write(struct rt_i2c_bus_device *bus, rt_uint8_t reg, rt_uint8_t *data, rt_uint16_t len)
{
struct rt_i2c_msg msgs;
rt_uint8_t buf[6];
buf[0] = reg;
if (len > 0)
{
if (len < 6)
{
rt_memcpy(buf + 1, data, len);
}
else
{
return -RT_ERROR;
}
}
msgs.addr = BSP_TCA9539_DEV_ADDR;
msgs.flags = RT_I2C_WR;
msgs.buf = buf;
msgs.len = len + 1;
if (rt_i2c_transfer(bus, &msgs, 1) == 1)
{
return RT_EOK;
}
else
{
return -RT_ERROR;
}
}
/**
* @brief BSP TCA9539 Read data.
* @param [in] bus: Pointer to the i2c bus device.
* @param [in] reg: Register to be read.
* @param [out] data: The pointer to the buffer contains the data to be read.
* @param [in] len: Buffer size in byte.
* @retval rt_err_t:
* - RT_EOK
* - -RT_ERROR
*/
static rt_err_t BSP_TCA9539_I2C_Read(struct rt_i2c_bus_device *bus, rt_uint8_t reg, rt_uint8_t *data, rt_uint16_t len)
{
struct rt_i2c_msg msgs;
if (RT_EOK != BSP_TCA9539_I2C_Write(bus, reg, RT_NULL, 0))
{
return -RT_ERROR;
}
msgs.addr = BSP_TCA9539_DEV_ADDR;
msgs.flags = RT_I2C_RD;
msgs.buf = data;
msgs.len = len;
if (rt_i2c_transfer(bus, &msgs, 1) == 1)
{
return RT_EOK;
}
else
{
return -RT_ERROR;
}
}
/**
* @brief Reset TCA9539.
* @param [in] None
* @retval None
*/
static void TCA9539_Reset(void)
{
rt_pin_mode(TCA9539_RST_PIN, PIN_MODE_OUTPUT);
/* Reset the device */
rt_pin_write(TCA9539_RST_PIN, PIN_LOW);
rt_thread_mdelay(3U);
rt_pin_write(TCA9539_RST_PIN, PIN_HIGH);
}
/**
* @brief Write TCA9539 pin output value.
* @param [in] u8Port Port number.
* This parameter can be one of the following values:
* @arg @ref TCA9539_Port_Definition
* @param [in] u8Pin Pin number.
* This parameter can be one or any combination of the following values:
* @arg @ref TCA9539_Pin_Definition
* @param [in] u8PinState Pin state to be written.
* This parameter can be one of the following values:
* @arg @ref TCA9539_Pin_State_Definition
* @retval rt_err_t:
* - RT_ERROR
* - RT_EOK
*/
rt_err_t TCA9539_WritePin(uint8_t u8Port, uint8_t u8Pin, uint8_t u8PinState)
{
uint8_t u8TempData[2];
u8TempData[0] = u8Port + TCA9539_REG_OUTPUT_PORT0;
if (RT_EOK != BSP_TCA9539_I2C_Read(i2c_bus, u8TempData[0], &u8TempData[1], 1U))
{
return RT_ERROR;
}
if (0U == u8PinState)
{
u8TempData[1] &= (uint8_t)(~u8Pin);
}
else
{
u8TempData[1] |= u8Pin;
}
if (RT_EOK != BSP_TCA9539_I2C_Write(i2c_bus, u8TempData[0], &u8TempData[1], 1U))
{
return RT_ERROR;
}
return RT_EOK;
}
/**
* @brief Read TCA9539 pin input value.
* @param [in] u8Port Port number.
* This parameter can be one of the following values:
* @arg @ref TCA9539_Port_Definition
* @param [in] u8Pin Pin number.
* This parameter can be one or any combination of the following values:
* @arg @ref TCA9539_Pin_Definition
* @param [in] u8PinState Pin state to be written.
* This parameter can be one of the following values:
* @arg @ref TCA9539_Pin_State_Definition
* @retval rt_err_t:
* - RT_ERROR
* - RT_EOK
*/
rt_err_t TCA9539_ReadPin(uint8_t u8Port, uint8_t u8Pin, uint8_t *pu8PinState)
{
uint8_t u8TempData[2];
u8TempData[0] = u8Port + TCA9539_REG_INPUT_PORT0;
if (RT_EOK != BSP_TCA9539_I2C_Read(i2c_bus, u8TempData[0], &u8TempData[1], 1U))
{
return RT_ERROR;
}
if (0U != (u8TempData[1] & u8Pin))
{
*pu8PinState = TCA9539_PIN_SET;
}
else
{
*pu8PinState = TCA9539_PIN_RESET;
}
return RT_EOK;
}
/**
* @brief Toggle TCA9539 pin output value.
* @param [in] u8Port Port number.
* This parameter can be one of the following values:
* @arg @ref TCA9539_Port_Definition
* @param [in] u8Pin Pin number.
* This parameter can be one or any combination of the following values:
* @arg @ref TCA9539_Pin_Definition
* @retval rt_err_t:
* - RT_ERROR
* - RT_EOK
*/
rt_err_t TCA9539_TogglePin(uint8_t u8Port, uint8_t u8Pin)
{
uint8_t u8TempData[2];
u8TempData[0] = u8Port + TCA9539_REG_OUTPUT_PORT0;
if (RT_EOK != BSP_TCA9539_I2C_Read(i2c_bus, u8TempData[0], &u8TempData[1], 1U))
{
return RT_ERROR;
}
u8TempData[1] ^= u8Pin;
if (RT_EOK != BSP_TCA9539_I2C_Write(i2c_bus, u8TempData[0], &u8TempData[1], 1U))
{
return RT_ERROR;
}
return RT_EOK;
}
/**
* @brief Configuration TCA9539 pin.
* @param [in] u8Port Port number.
* This parameter can be one of the following values:
* @arg @ref TCA9539_Port_Definition
* @param [in] u8Pin Pin number.
* This parameter can be one or any combination of the following values:
* @arg @ref TCA9539_Pin_Definition
* @param [in] u8Dir Pin output direction.
* This parameter can be one of the following values:
* @arg @ref TCA9539_Direction_Definition
* @retval rt_err_t:
* - RT_ERROR
* - RT_EOK
*/
rt_err_t TCA9539_ConfigPin(uint8_t u8Port, uint8_t u8Pin, uint8_t u8Dir)
{
uint8_t u8TempData[2];
u8TempData[0] = u8Port + TCA9539_REG_CONFIG_PORT0;
if (RT_EOK != BSP_TCA9539_I2C_Read(i2c_bus, u8TempData[0], &u8TempData[1], 1U))
{
return RT_ERROR;
}
if (TCA9539_DIR_OUT == u8Dir)
{
u8TempData[1] &= (uint8_t)(~u8Pin);
}
else
{
u8TempData[1] |= u8Pin;
}
if (RT_EOK != BSP_TCA9539_I2C_Write(i2c_bus, u8TempData[0], &u8TempData[1], 1U))
{
return RT_ERROR;
}
return RT_EOK;
}
/**
* @brief Initialize TCA9539.
* @param [in] None
* @retval rt_err_t:
* - RT_ERROR
* - RT_EOK
*/
int TCA9539_Init(void)
{
char name[RT_NAME_MAX];
uint8_t u8TempData[2];
TCA9539_Reset();
rt_strncpy(name, BSP_TCA9539_I2C_BUS_NAME, RT_NAME_MAX);
i2c_bus = (struct rt_i2c_bus_device *)rt_device_find(name);
if (i2c_bus == RT_NULL)
{
rt_kprintf("can't find %s device!\n", BSP_TCA9539_I2C_BUS_NAME);
return RT_ERROR;
}
/* All Pins are input as default */
u8TempData[0] = TCA9539_REG_CONFIG_PORT0;
u8TempData[1] = 0xFFU;
if (RT_EOK != BSP_TCA9539_I2C_Write(i2c_bus, u8TempData[0], &u8TempData[1], 1U))
{
return RT_ERROR;
}
u8TempData[0] = TCA9539_REG_CONFIG_PORT1;
if (RT_EOK != BSP_TCA9539_I2C_Write(i2c_bus, u8TempData[0], &u8TempData[1], 1U))
{
return RT_ERROR;
}
return RT_EOK;
}
INIT_PREV_EXPORT(TCA9539_Init);
#endif /* BSP_USING_TCA9539 */

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/*
* Copyright (C) 2022, Xiaohua Semiconductor Co., Ltd.
*
* SPDX-License-Identifier: Apache-2.0
*
* Change Logs:
* Date Author Notes
* 2022-04-28 CDT first version
*/
#ifndef __TCA9539_H__
#define __TCA9539_H__
#include <rtdevice.h>
/**
* @defgroup TCA9539_REGISTER_Definition TCA9539 Register Definition
* @{
*/
#define TCA9539_REG_INPUT_PORT0 (0x00U)
#define TCA9539_REG_INPUT_PORT1 (0x01U)
#define TCA9539_REG_OUTPUT_PORT0 (0x02U)
#define TCA9539_REG_OUTPUT_PORT1 (0x03U)
#define TCA9539_REG_INVERT_PORT0 (0x04U)
#define TCA9539_REG_INVERT_PORT1 (0x05U)
#define TCA9539_REG_CONFIG_PORT0 (0x06U)
#define TCA9539_REG_CONFIG_PORT1 (0x07U)
/**
* @}
*/
/**
* @defgroup TCA9539_Port_Definition TCA9539 Port Definition
* @{
*/
#define TCA9539_IO_PORT0 (0x00U)
#define TCA9539_IO_PORT1 (0x01U)
/**
* @}
*/
/**
* @defgroup TCA9539_Pin_Definition TCA9539 Pin Definition
* @{
*/
#define TCA9539_IO_PIN0 (0x01U)
#define TCA9539_IO_PIN1 (0x02U)
#define TCA9539_IO_PIN2 (0x04U)
#define TCA9539_IO_PIN3 (0x08U)
#define TCA9539_IO_PIN4 (0x10U)
#define TCA9539_IO_PIN5 (0x20U)
#define TCA9539_IO_PIN6 (0x40U)
#define TCA9539_IO_PIN7 (0x80U)
#define TCA9539_IO_PIN_ALL (0xFFU)
/**
* @}
*/
/**
* @defgroup TCA9539_Direction_Definition TCA9539 Direction Definition
* @{
*/
#define TCA9539_DIR_OUT (0x00U)
#define TCA9539_DIR_IN (0x01U)
/**
* @}
*/
/**
* @defgroup TCA9539_Pin_State_Definition TCA9539 Pin State Definition
* @{
*/
#define TCA9539_PIN_RESET (0x00U)
#define TCA9539_PIN_SET (0x01U)
/**
* @}
*/
/**
* @defgroup HC32F4A0_EV_IO_Function_Sel Expand IO function definition
* @{
*/
#define EIO_USBFS_OC (TCA9539_IO_PIN0) /* USBFS over-current, input */
#define EIO_USBHS_OC (TCA9539_IO_PIN1) /* USBHS over-current, input */
#define EIO_SDIC1_CD (TCA9539_IO_PIN2) /* SDIC1 card detect, input */
#define EIO_SCI_CD (TCA9539_IO_PIN3) /* Smart card detect, input */
#define EIO_TOUCH_INT (TCA9539_IO_PIN4) /* Touch screen interrupt, input */
#define EIO_LIN_SLEEP (TCA9539_IO_PIN5) /* LIN PHY sleep, output */
#define EIO_RTCS_CTRST (TCA9539_IO_PIN6) /* 'CS' for Resistor touch panel or 'Reset' for Cap touch panel, output */
#define EIO_LCD_RST (TCA9539_IO_PIN7) /* LCD panel reset, output */
#define EIO_CAM_RST (TCA9539_IO_PIN0) /* Camera module reset, output */
#define EIO_CAM_STB (TCA9539_IO_PIN1) /* Camera module standby, output */
#define EIO_USB3300_RST (TCA9539_IO_PIN2) /* USBHS PHY USB3300 reset, output */
#define EIO_ETH_RST (TCA9539_IO_PIN3) /* ETH PHY reset, output */
#define EIO_CAN_STB (TCA9539_IO_PIN4) /* CAN PHY standby, output */
#define EIO_LED_RED (TCA9539_IO_PIN5) /* Red LED, output */
#define EIO_LED_YELLOW (TCA9539_IO_PIN6) /* Yellow LED, output */
#define EIO_LED_BLUE (TCA9539_IO_PIN7) /* Blue LED, output */
/**
* @}
*/
/**
* @defgroup BSP_LED_PortPin_Sel BSP LED port/pin definition
* @{
*/
#define LED_PORT (TCA9539_IO_PORT1)
#define LED_RED_PORT (TCA9539_IO_PORT1)
#define LED_RED_PIN (EIO_LED_RED)
#define LED_YELLOW_PORT (TCA9539_IO_PORT1)
#define LED_YELLOW_PIN (EIO_LED_YELLOW)
#define LED_BLUE_PORT (TCA9539_IO_PORT1)
#define LED_BLUE_PIN (EIO_LED_BLUE)
/**
* @}
*/
/**
* @defgroup BSP CAN PHY STB port/pin definition
* @{
*/
#define CAN_STB_PORT (TCA9539_IO_PORT1)
#define CAN_STB_PIN (EIO_CAN_STB)
/**
* @}
*/
int TCA9539_Init(void);
rt_err_t TCA9539_WritePin(uint8_t u8Port, uint8_t u8Pin, uint8_t u8PinState);
rt_err_t TCA9539_ReadPin(uint8_t u8Port, uint8_t u8Pin, uint8_t *pu8PinState);
rt_err_t TCA9539_TogglePin(uint8_t u8Port, uint8_t u8Pin);
rt_err_t TCA9539_ConfigPin(uint8_t u8Port, uint8_t u8Pin, uint8_t u8Dir);
#endif

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<?xml version="1.0" encoding="iso-8859-1"?>
<workspace>
<project>
<path>$WS_DIR$\project.ewp</path>
</project>
<batchBuild/>
</workspace>

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<ProjectOpt xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance" xsi:noNamespaceSchemaLocation="project_optx.xsd">
<SchemaVersion>1.0</SchemaVersion>
<Header>### uVision Project, (C) Keil Software</Header>
<Extensions>
<cExt>*.c</cExt>
<aExt>*.s*; *.src; *.a*</aExt>
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<lExt>*.lib</lExt>
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<pExt>*.plm</pExt>
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</Extensions>
<DaveTm>
<dwLowDateTime>0</dwLowDateTime>
<dwHighDateTime>0</dwHighDateTime>
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<Target>
<TargetName>rt-thread</TargetName>
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<TargetOption>
<CLKADS>12000000</CLKADS>
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<HexSelection>1</HexSelection>
<FlashByte>65535</FlashByte>
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<OPTLEX>
<PageWidth>79</PageWidth>
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<ListingPage>
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<LMap>1</LMap>
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<LLines>1</LLines>
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</OPTXL>
<OPTFL>
<tvExp>1</tvExp>
<tvExpOptDlg>0</tvExpOptDlg>
<IsCurrentTarget>1</IsCurrentTarget>
</OPTFL>
<CpuCode>255</CpuCode>
<DebugOpt>
<uSim>0</uSim>
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<sDll></sDll>
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<tDlgPa></tDlgPa>
<tIfile></tIfile>
<pMon>BIN\CMSIS_AGDI.dll</pMon>
</DebugOpt>
<TargetDriverDllRegistry>
<SetRegEntry>
<Number>0</Number>
<Key>CMSIS_AGDI</Key>
<Name>-X"Any" -UAny -O206 -S0 -C0 -P00 -N00("") -D00(00000000) -L00(0) -TO65554 -TC10000000 -TT10000000 -TP20 -TDS8007 -TDT0 -TDC1F -TIEFFFFFFFF -TIP8 -FO7 -FD1FFE0000 -FC1000 -FN1 -FF0HC32F4A0_2M.FLM -FS00 -FL0200000 -FP0($$Device:HC32F4A0SITB$FlashARM\HC32F4A0_2M.FLM)</Name>
</SetRegEntry>
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<Number>0</Number>
<Key>UL2CM3</Key>
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<Key>JL2CM3</Key>
<Name>-U261009725 -O78 -S2 -ZTIFSpeedSel5000 -A0 -C0 -JU1 -JI127.0.0.1 -JP0 -RST2 -TO18 -TC10000000 -TP21 -TDS8000 -TDT0 -TDC1F -TIEFFFFFFFF -TIP8 -TB1 -TFE0 -FO15 -FD1FFE0000 -FC1000 -FN1 -FF0HC32F4A0_2M.FLM -FS00 -FL0200000 -FP0($$Device:HC32F4A0SITB$FlashARM\HC32F4A0_2M.FLM)</Name>
</SetRegEntry>
</TargetDriverDllRegistry>
<Breakpoint/>
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</DebugFlag>
<LintExecutable></LintExecutable>
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<pMisraName></pMisraName>
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<pSingCmdsp></pSingCmdsp>
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</DebugDescription>
</TargetOption>
</Target>
</ProjectOpt>

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bsp/hc32/ev_hc32f4a0_lqfp176/project.uvprojx Normal file
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<?xml version="1.0" encoding="UTF-8" standalone="no" ?>
<Project xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance" xsi:noNamespaceSchemaLocation="project_projx.xsd">
<SchemaVersion>2.1</SchemaVersion>
<Header>### uVision Project, (C) Keil Software</Header>
<Targets>
<Target>
<TargetName>rt-thread</TargetName>
<ToolsetNumber>0x4</ToolsetNumber>
<ToolsetName>ARM-ADS</ToolsetName>
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<PackURL>https://raw.githubusercontent.com/hdscmcu/pack/master/</PackURL>
<Cpu>IROM(0x00000000,0x200000) IRAM(0x1FFE0000,0x80000) IRAM2(0X200F0000,0x1000) CPUTYPE("Cortex-M4") FPU2 CLOCK(240000000) ESEL ELITTLE</Cpu>
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<Linker />
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<Flash2>BIN\UL2CM3.DLL</Flash2>
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<Flash4 />
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</File>
</Files>
<Files>
<File>
<FileName>components.c</FileName>
<FileType>1</FileType>
<FilePath>..\..\..\src\components.c</FilePath>
</File>
</Files>
<Files>
<File>
<FileName>kservice.c</FileName>
<FileType>1</FileType>
<FilePath>..\..\..\src\kservice.c</FilePath>
</File>
</Files>
<Files>
<File>
<FileName>timer.c</FileName>
<FileType>1</FileType>
<FilePath>..\..\..\src\timer.c</FilePath>
</File>
</Files>
<Files>
<File>
<FileName>mempool.c</FileName>
<FileType>1</FileType>
<FilePath>..\..\..\src\mempool.c</FilePath>
</File>
</Files>
<Files>
<File>
<FileName>mem.c</FileName>
<FileType>1</FileType>
<FilePath>..\..\..\src\mem.c</FilePath>
</File>
</Files>
</Group>
<Group>
<GroupName>Libraries</GroupName>
<Files>
<File>
<FileName>hc32_ll_clk.c</FileName>
<FileType>1</FileType>
<FilePath>..\libraries\hc32f4a0_ddl\drivers\hc32_ll_driver\src\hc32_ll_clk.c</FilePath>
</File>
</Files>
<Files>
<File>
<FileName>hc32_ll_icg.c</FileName>
<FileType>1</FileType>
<FilePath>..\libraries\hc32f4a0_ddl\drivers\hc32_ll_driver\src\hc32_ll_icg.c</FilePath>
</File>
</Files>
<Files>
<File>
<FileName>hc32_ll_utility.c</FileName>
<FileType>1</FileType>
<FilePath>..\libraries\hc32f4a0_ddl\drivers\hc32_ll_driver\src\hc32_ll_utility.c</FilePath>
</File>
</Files>
<Files>
<File>
<FileName>hc32_ll_fcg.c</FileName>
<FileType>1</FileType>
<FilePath>..\libraries\hc32f4a0_ddl\drivers\hc32_ll_driver\src\hc32_ll_fcg.c</FilePath>
</File>
</Files>
<Files>
<File>
<FileName>hc32_ll_interrupts.c</FileName>
<FileType>1</FileType>
<FilePath>..\libraries\hc32f4a0_ddl\drivers\hc32_ll_driver\src\hc32_ll_interrupts.c</FilePath>
</File>
</Files>
<Files>
<File>
<FileName>hc32_ll_pwc.c</FileName>
<FileType>1</FileType>
<FilePath>..\libraries\hc32f4a0_ddl\drivers\hc32_ll_driver\src\hc32_ll_pwc.c</FilePath>
</File>
</Files>
<Files>
<File>
<FileName>hc32_ll_aos.c</FileName>
<FileType>1</FileType>
<FilePath>..\libraries\hc32f4a0_ddl\drivers\hc32_ll_driver\src\hc32_ll_aos.c</FilePath>
</File>
</Files>
<Files>
<File>
<FileName>hc32_ll_sram.c</FileName>
<FileType>1</FileType>
<FilePath>..\libraries\hc32f4a0_ddl\drivers\hc32_ll_driver\src\hc32_ll_sram.c</FilePath>
</File>
</Files>
<Files>
<File>
<FileName>hc32_ll.c</FileName>
<FileType>1</FileType>
<FilePath>..\libraries\hc32f4a0_ddl\drivers\hc32_ll_driver\src\hc32_ll.c</FilePath>
</File>
</Files>
<Files>
<File>
<FileName>hc32_ll_efm.c</FileName>
<FileType>1</FileType>
<FilePath>..\libraries\hc32f4a0_ddl\drivers\hc32_ll_driver\src\hc32_ll_efm.c</FilePath>
</File>
</Files>
<Files>
<File>
<FileName>hc32f4a0_ll_interrupts_share.c</FileName>
<FileType>1</FileType>
<FilePath>..\libraries\hc32f4a0_ddl\drivers\hc32_ll_driver\src\hc32f4a0_ll_interrupts_share.c</FilePath>
</File>
</Files>
<Files>
<File>
<FileName>hc32_ll_gpio.c</FileName>
<FileType>1</FileType>
<FilePath>..\libraries\hc32f4a0_ddl\drivers\hc32_ll_driver\src\hc32_ll_gpio.c</FilePath>
</File>
</Files>
<Files>
<File>
<FileName>hc32_ll_usart.c</FileName>
<FileType>1</FileType>
<FilePath>..\libraries\hc32f4a0_ddl\drivers\hc32_ll_driver\src\hc32_ll_usart.c</FilePath>
</File>
</Files>
<Files>
<File>
<FileName>hc32_ll_rmu.c</FileName>
<FileType>1</FileType>
<FilePath>..\libraries\hc32f4a0_ddl\drivers\hc32_ll_driver\src\hc32_ll_rmu.c</FilePath>
</File>
</Files>
<Files>
<File>
<FileName>system_hc32f4a0.c</FileName>
<FileType>1</FileType>
<FilePath>..\libraries\hc32f4a0_ddl\drivers\cmsis\Device\HDSC\hc32f4xx\Source\system_hc32f4a0.c</FilePath>
</File>
</Files>
<Files>
<File>
<FileName>hc32_ll_tmr0.c</FileName>
<FileType>1</FileType>
<FilePath>..\libraries\hc32f4a0_ddl\drivers\hc32_ll_driver\src\hc32_ll_tmr0.c</FilePath>
</File>
</Files>
<Files>
<File>
<FileName>hc32_ll_dma.c</FileName>
<FileType>1</FileType>
<FilePath>..\libraries\hc32f4a0_ddl\drivers\hc32_ll_driver\src\hc32_ll_dma.c</FilePath>
</File>
</Files>
</Group>
</Groups>
</Target>
</Targets>
<RTE>
<apis />
<components />
<files />
</RTE>
</Project>

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#ifndef RT_CONFIG_H__
#define RT_CONFIG_H__
/* Automatically generated file; DO NOT EDIT. */
/* RT-Thread Configuration */
/* RT-Thread Kernel */
#define RT_NAME_MAX 8
#define RT_ALIGN_SIZE 4
#define RT_THREAD_PRIORITY_32
#define RT_THREAD_PRIORITY_MAX 32
#define RT_TICK_PER_SECOND 1000
#define RT_USING_OVERFLOW_CHECK
#define RT_USING_HOOK
#define RT_HOOK_USING_FUNC_PTR
#define RT_USING_IDLE_HOOK
#define RT_IDLE_HOOK_LIST_SIZE 4
#define IDLE_THREAD_STACK_SIZE 256
/* kservice optimization */
#define RT_DEBUG
#define RT_DEBUG_COLOR
/* Inter-Thread communication */
#define RT_USING_SEMAPHORE
#define RT_USING_MUTEX
#define RT_USING_EVENT
#define RT_USING_MAILBOX
#define RT_USING_MESSAGEQUEUE
/* Memory Management */
#define RT_USING_MEMPOOL
#define RT_USING_SMALL_MEM
#define RT_USING_SMALL_MEM_AS_HEAP
#define RT_USING_HEAP
/* Kernel Device Object */
#define RT_USING_DEVICE
#define RT_USING_CONSOLE
#define RT_CONSOLEBUF_SIZE 128
#define RT_CONSOLE_DEVICE_NAME "uart1"
#define RT_VER_NUM 0x40100
#define ARCH_ARM
#define RT_USING_CPU_FFS
#define ARCH_ARM_CORTEX_M
#define ARCH_ARM_CORTEX_M4
/* RT-Thread Components */
#define RT_USING_COMPONENTS_INIT
#define RT_USING_USER_MAIN
#define RT_MAIN_THREAD_STACK_SIZE 2048
#define RT_MAIN_THREAD_PRIORITY 10
#define RT_USING_MSH
#define RT_USING_FINSH
#define FINSH_USING_MSH
#define FINSH_THREAD_NAME "tshell"
#define FINSH_THREAD_PRIORITY 20
#define FINSH_THREAD_STACK_SIZE 4096
#define FINSH_USING_HISTORY
#define FINSH_HISTORY_LINES 5
#define FINSH_USING_SYMTAB
#define FINSH_CMD_SIZE 80
#define MSH_USING_BUILT_IN_COMMANDS
#define FINSH_USING_DESCRIPTION
#define FINSH_ARG_MAX 10
/* Device Drivers */
#define RT_USING_DEVICE_IPC
#define RT_USING_SYSTEM_WORKQUEUE
#define RT_SYSTEM_WORKQUEUE_STACKSIZE 2048
#define RT_SYSTEM_WORKQUEUE_PRIORITY 23
#define RT_USING_SERIAL
#define RT_USING_SERIAL_V1
#define RT_SERIAL_RB_BUFSZ 64
#define RT_USING_PIN
/* Using USB */
/* C/C++ and POSIX layer */
#define RT_LIBC_DEFAULT_TIMEZONE 8
/* POSIX (Portable Operating System Interface) layer */
/* Interprocess Communication (IPC) */
/* Socket is in the 'Network' category */
/* Network */
/* Utilities */
/* RT-Thread Utestcases */
/* RT-Thread online packages */
/* IoT - internet of things */
/* Wi-Fi */
/* Marvell WiFi */
/* Wiced WiFi */
/* IoT Cloud */
/* security packages */
/* language packages */
/* JSON: JavaScript Object Notation, a lightweight data-interchange format */
/* XML: Extensible Markup Language */
/* multimedia packages */
/* LVGL: powerful and easy-to-use embedded GUI library */
/* u8g2: a monochrome graphic library */
/* PainterEngine: A cross-platform graphics application framework written in C language */
/* tools packages */
/* system packages */
/* enhanced kernel services */
/* POSIX extension functions */
/* acceleration: Assembly language or algorithmic acceleration packages */
/* CMSIS: ARM Cortex-M Microcontroller Software Interface Standard */
/* Micrium: Micrium software products porting for RT-Thread */
/* peripheral libraries and drivers */
/* AI packages */
/* miscellaneous packages */
/* project laboratory */
/* samples: kernel and components samples */
/* entertainment: terminal games and other interesting software packages */
#define SOC_FAMILY_HC32
#define SOC_SERIES_HC32F4
/* Hardware Drivers Config */
#define SOC_HC32F4A0SI
/* Onboard Peripheral Drivers */
/* On-chip Peripheral Drivers */
#define BSP_USING_GPIO
#define BSP_USING_UART
#define BSP_USING_UART1
/* Board extended module Drivers */
#endif

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import os
# toolchains options
ARCH='arm'
CPU='cortex-m4'
CROSS_TOOL='gcc'
# bsp lib config
BSP_LIBRARY_TYPE = None
if os.getenv('RTT_CC'):
CROSS_TOOL = os.getenv('RTT_CC')
if os.getenv('RTT_ROOT'):
RTT_ROOT = os.getenv('RTT_ROOT')
# cross_tool provides the cross compiler
# EXEC_PATH is the compiler execute path, for example, CodeSourcery, Keil MDK, IAR
if CROSS_TOOL == 'gcc':
PLATFORM = 'gcc'
EXEC_PATH = r'C:/Users/XXYYZZ'
elif CROSS_TOOL == 'keil':
PLATFORM = 'armcc'
EXEC_PATH = r'C:/Keil_v5'
elif CROSS_TOOL == 'iar':
PLATFORM = 'iar'
EXEC_PATH = r'C:/Program Files (x86)/IAR Systems/Embedded Workbench 8.4'
if os.getenv('RTT_EXEC_PATH'):
EXEC_PATH = os.getenv('RTT_EXEC_PATH')
BUILD = 'debug'
if PLATFORM == 'gcc':
# toolchains
PREFIX = 'arm-none-eabi-'
CC = PREFIX + 'gcc'
AS = PREFIX + 'gcc'
AR = PREFIX + 'ar'
CXX = PREFIX + 'g++'
LINK = PREFIX + 'gcc'
TARGET_EXT = 'elf'
SIZE = PREFIX + 'size'
OBJDUMP = PREFIX + 'objdump'
OBJCPY = PREFIX + 'objcopy'
DEVICE = ' -mcpu=cortex-m4 -mthumb -mfpu=fpv4-sp-d16 -mfloat-abi=hard -ffunction-sections -fdata-sections'
CFLAGS = DEVICE + ' -Dgcc'
AFLAGS = ' -c' + DEVICE + ' -x assembler-with-cpp -Wa,-mimplicit-it=thumb '
LFLAGS = DEVICE + ' -Wl,--gc-sections,-Map=rtthread.map,-cref,-u,Reset_Handler -T board/linker_scripts/link.ld'
CPATH = ''
LPATH = ''
if BUILD == 'debug':
CFLAGS += ' -O0 -gdwarf-2 -g'
AFLAGS += ' -gdwarf-2'
else:
CFLAGS += ' -O2'
CXXFLAGS = CFLAGS
POST_ACTION = OBJCPY + ' -O binary $TARGET rtthread.bin\n' + SIZE + ' $TARGET \n'
elif PLATFORM == 'armcc':
# toolchains
CC = 'armcc'
CXX = 'armcc'
AS = 'armasm'
AR = 'armar'
LINK = 'armlink'
TARGET_EXT = 'axf'
DEVICE = ' --cpu Cortex-M4.fp '
CFLAGS = '-c ' + DEVICE + ' --apcs=interwork --c99'
AFLAGS = DEVICE + ' --apcs=interwork '
LFLAGS = DEVICE + ' --scatter "board\linker_scripts\link.sct" --info sizes --info totals --info unused --info veneers --list rtthread.map --strict'
CFLAGS += ' -I' + EXEC_PATH + '/ARM/ARMCC/include'
LFLAGS += ' --libpath=' + EXEC_PATH + '/ARM/ARMCC/lib'
CFLAGS += ' -D__MICROLIB '
AFLAGS += ' --pd "__MICROLIB SETA 1" '
LFLAGS += ' --library_type=microlib '
EXEC_PATH += '/ARM/ARMCC/bin/'
if BUILD == 'debug':
CFLAGS += ' -g -O0'
AFLAGS += ' -g'
else:
CFLAGS += ' -O2'
CXXFLAGS = CFLAGS
CFLAGS += ' -std=c99'
POST_ACTION = 'fromelf --bin $TARGET --output rtthread.bin \nfromelf -z $TARGET'
elif PLATFORM == 'iar':
# toolchains
CC = 'iccarm'
CXX = 'iccarm'
AS = 'iasmarm'
AR = 'iarchive'
LINK = 'ilinkarm'
TARGET_EXT = 'out'
DEVICE = '-Dewarm'
CFLAGS = DEVICE
CFLAGS += ' --diag_suppress Pa050'
CFLAGS += ' --no_cse'
CFLAGS += ' --no_unroll'
CFLAGS += ' --no_inline'
CFLAGS += ' --no_code_motion'
CFLAGS += ' --no_tbaa'
CFLAGS += ' --no_clustering'
CFLAGS += ' --no_scheduling'
CFLAGS += ' --endian=little'
CFLAGS += ' --cpu=Cortex-M4'
CFLAGS += ' -e'
CFLAGS += ' --fpu=VFPv4_sp'
CFLAGS += ' --dlib_config "' + EXEC_PATH + '/arm/INC/c/DLib_Config_Normal.h"'
CFLAGS += ' --silent'
AFLAGS = DEVICE
AFLAGS += ' -s+'
AFLAGS += ' -w+'
AFLAGS += ' -r'
AFLAGS += ' --cpu Cortex-M4'
AFLAGS += ' --fpu VFPv4_sp'
AFLAGS += ' -S'
if BUILD == 'debug':
CFLAGS += ' --debug'
CFLAGS += ' -On'
else:
CFLAGS += ' -Oh'
LFLAGS = ' --config "board/linker_scripts/link.icf"'
LFLAGS += ' --entry __iar_program_start'
CXXFLAGS = CFLAGS
EXEC_PATH = EXEC_PATH + '/arm/bin/'
POST_ACTION = 'ielftool --bin $TARGET rtthread.bin'
def dist_handle(BSP_ROOT, dist_dir):
import sys
cwd_path = os.getcwd()
sys.path.append(os.path.join(os.path.dirname(BSP_ROOT), 'tools'))
from sdk_dist import dist_do_building
dist_do_building(BSP_ROOT, dist_dir)

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<?xml version="1.0" encoding="iso-8859-1"?>
<workspace>
<project>
<path>$WS_DIR$\template.ewp</path>
</project>
<batchBuild/>
</workspace>

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<?xml version="1.0" encoding="UTF-8" standalone="no" ?>
<ProjectOpt xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance" xsi:noNamespaceSchemaLocation="project_optx.xsd">
<SchemaVersion>1.0</SchemaVersion>
<Header>### uVision Project, (C) Keil Software</Header>
<Extensions>
<cExt>*.c</cExt>
<aExt>*.s*; *.src; *.a*</aExt>
<oExt>*.obj; *.o</oExt>
<lExt>*.lib</lExt>
<tExt>*.txt; *.h; *.inc</tExt>
<pExt>*.plm</pExt>
<CppX>*.cpp</CppX>
<nMigrate>0</nMigrate>
</Extensions>
<DaveTm>
<dwLowDateTime>0</dwLowDateTime>
<dwHighDateTime>0</dwHighDateTime>
</DaveTm>
<Target>
<TargetName>rt-thread</TargetName>
<ToolsetNumber>0x4</ToolsetNumber>
<ToolsetName>ARM-ADS</ToolsetName>
<TargetOption>
<CLKADS>12000000</CLKADS>
<OPTTT>
<gFlags>1</gFlags>
<BeepAtEnd>1</BeepAtEnd>
<RunSim>0</RunSim>
<RunTarget>1</RunTarget>
<RunAbUc>0</RunAbUc>
</OPTTT>
<OPTHX>
<HexSelection>1</HexSelection>
<FlashByte>65535</FlashByte>
<HexRangeLowAddress>0</HexRangeLowAddress>
<HexRangeHighAddress>0</HexRangeHighAddress>
<HexOffset>0</HexOffset>
</OPTHX>
<OPTLEX>
<PageWidth>79</PageWidth>
<PageLength>66</PageLength>
<TabStop>8</TabStop>
<ListingPath>.\build\keil\List\</ListingPath>
</OPTLEX>
<ListingPage>
<CreateCListing>1</CreateCListing>
<CreateAListing>1</CreateAListing>
<CreateLListing>1</CreateLListing>
<CreateIListing>0</CreateIListing>
<AsmCond>1</AsmCond>
<AsmSymb>1</AsmSymb>
<AsmXref>0</AsmXref>
<CCond>1</CCond>
<CCode>0</CCode>
<CListInc>0</CListInc>
<CSymb>0</CSymb>
<LinkerCodeListing>0</LinkerCodeListing>
</ListingPage>
<OPTXL>
<LMap>1</LMap>
<LComments>1</LComments>
<LGenerateSymbols>1</LGenerateSymbols>
<LLibSym>1</LLibSym>
<LLines>1</LLines>
<LLocSym>1</LLocSym>
<LPubSym>1</LPubSym>
<LXref>0</LXref>
<LExpSel>0</LExpSel>
</OPTXL>
<OPTFL>
<tvExp>1</tvExp>
<tvExpOptDlg>0</tvExpOptDlg>
<IsCurrentTarget>1</IsCurrentTarget>
</OPTFL>
<CpuCode>255</CpuCode>
<DebugOpt>
<uSim>0</uSim>
<uTrg>1</uTrg>
<sLdApp>1</sLdApp>
<sGomain>1</sGomain>
<sRbreak>1</sRbreak>
<sRwatch>1</sRwatch>
<sRmem>1</sRmem>
<sRfunc>1</sRfunc>
<sRbox>1</sRbox>
<tLdApp>1</tLdApp>
<tGomain>1</tGomain>
<tRbreak>1</tRbreak>
<tRwatch>1</tRwatch>
<tRmem>1</tRmem>
<tRfunc>0</tRfunc>
<tRbox>1</tRbox>
<tRtrace>1</tRtrace>
<sRSysVw>1</sRSysVw>
<tRSysVw>1</tRSysVw>
<sRunDeb>0</sRunDeb>
<sLrtime>0</sLrtime>
<bEvRecOn>1</bEvRecOn>
<bSchkAxf>0</bSchkAxf>
<bTchkAxf>0</bTchkAxf>
<nTsel>3</nTsel>
<sDll></sDll>
<sDllPa></sDllPa>
<sDlgDll></sDlgDll>
<sDlgPa></sDlgPa>
<sIfile></sIfile>
<tDll></tDll>
<tDllPa></tDllPa>
<tDlgDll></tDlgDll>
<tDlgPa></tDlgPa>
<tIfile></tIfile>
<pMon>BIN\CMSIS_AGDI.dll</pMon>
</DebugOpt>
<TargetDriverDllRegistry>
<SetRegEntry>
<Number>0</Number>
<Key>CMSIS_AGDI</Key>
<Name>-X"Any" -UAny -O206 -S0 -C0 -P00 -N00("") -D00(00000000) -L00(0) -TO65554 -TC10000000 -TT10000000 -TP20 -TDS8007 -TDT0 -TDC1F -TIEFFFFFFFF -TIP8 -FO7 -FD1FFE0000 -FC1000 -FN1 -FF0HC32F4A0_2M.FLM -FS00 -FL0200000 -FP0($$Device:HC32F4A0SITB$FlashARM\HC32F4A0_2M.FLM)</Name>
</SetRegEntry>
<SetRegEntry>
<Number>0</Number>
<Key>UL2CM3</Key>
<Name>UL2CM3(-S0 -C0 -P0 -FD1FFE0000 -FC1000 -FN1 -FF0HC32F4A0 -FS00 -FL0200000 -FP0($$Device:HC32F4A0SITB$FlashARM\HC32F4A0_2M.FLM))</Name>
</SetRegEntry>
<SetRegEntry>
<Number>0</Number>
<Key>JL2CM3</Key>
<Name>-U261009725 -O78 -S2 -ZTIFSpeedSel5000 -A0 -C0 -JU1 -JI127.0.0.1 -JP0 -RST2 -TO18 -TC10000000 -TP21 -TDS8000 -TDT0 -TDC1F -TIEFFFFFFFF -TIP8 -TB1 -TFE0 -FO15 -FD1FFE0000 -FC1000 -FN1 -FF0HC32F4A0_2M.FLM -FS00 -FL0200000 -FP0($$Device:HC32F4A0SITB$FlashARM\HC32F4A0_2M.FLM)</Name>
</SetRegEntry>
</TargetDriverDllRegistry>
<Breakpoint/>
<Tracepoint>
<THDelay>0</THDelay>
</Tracepoint>
<DebugFlag>
<trace>0</trace>
<periodic>0</periodic>
<aLwin>0</aLwin>
<aCover>0</aCover>
<aSer1>0</aSer1>
<aSer2>0</aSer2>
<aPa>0</aPa>
<viewmode>0</viewmode>
<vrSel>0</vrSel>
<aSym>0</aSym>
<aTbox>0</aTbox>
<AscS1>0</AscS1>
<AscS2>0</AscS2>
<AscS3>0</AscS3>
<aSer3>0</aSer3>
<eProf>0</eProf>
<aLa>0</aLa>
<aPa1>0</aPa1>
<AscS4>0</AscS4>
<aSer4>0</aSer4>
<StkLoc>0</StkLoc>
<TrcWin>0</TrcWin>
<newCpu>0</newCpu>
<uProt>0</uProt>
</DebugFlag>
<LintExecutable></LintExecutable>
<LintConfigFile></LintConfigFile>
<bLintAuto>0</bLintAuto>
<bAutoGenD>0</bAutoGenD>
<LntExFlags>0</LntExFlags>
<pMisraName></pMisraName>
<pszMrule></pszMrule>
<pSingCmds></pSingCmds>
<pMultCmds></pMultCmds>
<pMisraNamep></pMisraNamep>
<pszMrulep></pszMrulep>
<pSingCmdsp></pSingCmdsp>
<pMultCmdsp></pMultCmdsp>
<DebugDescription>
<Enable>1</Enable>
<EnableFlashSeq>0</EnableFlashSeq>
<EnableLog>0</EnableLog>
<Protocol>2</Protocol>
<DbgClock>1000000</DbgClock>
</DebugDescription>
</TargetOption>
</Target>
</ProjectOpt>

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<?xml version="1.0" encoding="UTF-8" standalone="no" ?>
<Project xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance" xsi:noNamespaceSchemaLocation="project_projx.xsd">
<SchemaVersion>2.1</SchemaVersion>
<Header>### uVision Project, (C) Keil Software</Header>
<Targets>
<Target>
<TargetName>rt-thread</TargetName>
<ToolsetNumber>0x4</ToolsetNumber>
<ToolsetName>ARM-ADS</ToolsetName>
<pCCUsed>5060750::V5.06 update 6 (build 750)::ARMCC</pCCUsed>
<uAC6>0</uAC6>
<TargetOption>
<TargetCommonOption>
<Device>HC32F4A0SITB</Device>
<Vendor>HDSC</Vendor>
<PackID>HDSC.HC32F4A0.1.0.6</PackID>
<PackURL>https://raw.githubusercontent.com/hdscmcu/pack/master/</PackURL>
<Cpu>IROM(0x00000000,0x200000) IRAM(0x1FFE0000,0x80000) IRAM2(0X200F0000,0x1000) CPUTYPE("Cortex-M4") FPU2 CLOCK(240000000) ESEL ELITTLE</Cpu>
<FlashUtilSpec></FlashUtilSpec>
<StartupFile></StartupFile>
<FlashDriverDll>UL2CM3(-S0 -C0 -P0 -FD1FFE0000 -FC1000 -FN1 -FF0HC32F4A0 -FS00 -FL0200000 -FP0($$Device:HC32F4A0SITB$FlashARM\HC32F4A0_2M.FLM))</FlashDriverDll>
<DeviceId>0</DeviceId>
<RegisterFile>$$Device:HC32F4A0SITB$Device\Include\HC32F4A0SITB.h</RegisterFile>
<MemoryEnv></MemoryEnv>
<Cmp></Cmp>
<Asm></Asm>
<Linker></Linker>
<OHString></OHString>
<InfinionOptionDll></InfinionOptionDll>
<SLE66CMisc></SLE66CMisc>
<SLE66AMisc></SLE66AMisc>
<SLE66LinkerMisc></SLE66LinkerMisc>
<SFDFile>../libraries/hc32f4a0_ddl/drivers/cmsis/Device/HDSC/hc32f4xx/Source/ARM/sfr/HDSC_HC32F4A0.SFR</SFDFile>
<bCustSvd>1</bCustSvd>
<UseEnv>0</UseEnv>
<BinPath></BinPath>
<IncludePath></IncludePath>
<LibPath></LibPath>
<RegisterFilePath></RegisterFilePath>
<DBRegisterFilePath></DBRegisterFilePath>
<TargetStatus>
<Error>0</Error>
<ExitCodeStop>0</ExitCodeStop>
<ButtonStop>0</ButtonStop>
<NotGenerated>0</NotGenerated>
<InvalidFlash>1</InvalidFlash>
</TargetStatus>
<OutputDirectory>.\build\keil\Obj\</OutputDirectory>
<OutputName>rtthread</OutputName>
<CreateExecutable>1</CreateExecutable>
<CreateLib>0</CreateLib>
<CreateHexFile>0</CreateHexFile>
<DebugInformation>1</DebugInformation>
<BrowseInformation>0</BrowseInformation>
<ListingPath>.\build\keil\List\</ListingPath>
<HexFormatSelection>1</HexFormatSelection>
<Merge32K>0</Merge32K>
<CreateBatchFile>0</CreateBatchFile>
<BeforeCompile>
<RunUserProg1>0</RunUserProg1>
<RunUserProg2>0</RunUserProg2>
<UserProg1Name></UserProg1Name>
<UserProg2Name></UserProg2Name>
<UserProg1Dos16Mode>0</UserProg1Dos16Mode>
<UserProg2Dos16Mode>0</UserProg2Dos16Mode>
<nStopU1X>0</nStopU1X>
<nStopU2X>0</nStopU2X>
</BeforeCompile>
<BeforeMake>
<RunUserProg1>0</RunUserProg1>
<RunUserProg2>0</RunUserProg2>
<UserProg1Name></UserProg1Name>
<UserProg2Name></UserProg2Name>
<UserProg1Dos16Mode>0</UserProg1Dos16Mode>
<UserProg2Dos16Mode>0</UserProg2Dos16Mode>
<nStopB1X>0</nStopB1X>
<nStopB2X>0</nStopB2X>
</BeforeMake>
<AfterMake>
<RunUserProg1>1</RunUserProg1>
<RunUserProg2>0</RunUserProg2>
<UserProg1Name>fromelf --bin !L --output rtthread.bin</UserProg1Name>
<UserProg2Name></UserProg2Name>
<UserProg1Dos16Mode>0</UserProg1Dos16Mode>
<UserProg2Dos16Mode>0</UserProg2Dos16Mode>
<nStopA1X>0</nStopA1X>
<nStopA2X>0</nStopA2X>
</AfterMake>
<SelectedForBatchBuild>0</SelectedForBatchBuild>
<SVCSIdString></SVCSIdString>
</TargetCommonOption>
<CommonProperty>
<UseCPPCompiler>0</UseCPPCompiler>
<RVCTCodeConst>0</RVCTCodeConst>
<RVCTZI>0</RVCTZI>
<RVCTOtherData>0</RVCTOtherData>
<ModuleSelection>0</ModuleSelection>
<IncludeInBuild>1</IncludeInBuild>
<AlwaysBuild>0</AlwaysBuild>
<GenerateAssemblyFile>0</GenerateAssemblyFile>
<AssembleAssemblyFile>0</AssembleAssemblyFile>
<PublicsOnly>0</PublicsOnly>
<StopOnExitCode>3</StopOnExitCode>
<CustomArgument></CustomArgument>
<IncludeLibraryModules></IncludeLibraryModules>
<ComprImg>1</ComprImg>
</CommonProperty>
<DllOption>
<SimDllName>SARMCM3.DLL</SimDllName>
<SimDllArguments> -REMAP -MPU</SimDllArguments>
<SimDlgDll>DCM.DLL</SimDlgDll>
<SimDlgDllArguments>-pCM4</SimDlgDllArguments>
<TargetDllName>SARMCM3.DLL</TargetDllName>
<TargetDllArguments> -MPU</TargetDllArguments>
<TargetDlgDll>TCM.DLL</TargetDlgDll>
<TargetDlgDllArguments>-pCM4</TargetDlgDllArguments>
</DllOption>
<DebugOption>
<OPTHX>
<HexSelection>1</HexSelection>
<HexRangeLowAddress>0</HexRangeLowAddress>
<HexRangeHighAddress>0</HexRangeHighAddress>
<HexOffset>0</HexOffset>
<Oh166RecLen>16</Oh166RecLen>
</OPTHX>
</DebugOption>
<Utilities>
<Flash1>
<UseTargetDll>1</UseTargetDll>
<UseExternalTool>0</UseExternalTool>
<RunIndependent>0</RunIndependent>
<UpdateFlashBeforeDebugging>1</UpdateFlashBeforeDebugging>
<Capability>1</Capability>
<DriverSelection>4096</DriverSelection>
</Flash1>
<bUseTDR>1</bUseTDR>
<Flash2>BIN\UL2CM3.DLL</Flash2>
<Flash3></Flash3>
<Flash4></Flash4>
<pFcarmOut></pFcarmOut>
<pFcarmGrp></pFcarmGrp>
<pFcArmRoot></pFcArmRoot>
<FcArmLst>0</FcArmLst>
</Utilities>
<TargetArmAds>
<ArmAdsMisc>
<GenerateListings>0</GenerateListings>
<asHll>1</asHll>
<asAsm>1</asAsm>
<asMacX>1</asMacX>
<asSyms>1</asSyms>
<asFals>1</asFals>
<asDbgD>1</asDbgD>
<asForm>1</asForm>
<ldLst>0</ldLst>
<ldmm>1</ldmm>
<ldXref>1</ldXref>
<BigEnd>0</BigEnd>
<AdsALst>1</AdsALst>
<AdsACrf>1</AdsACrf>
<AdsANop>0</AdsANop>
<AdsANot>0</AdsANot>
<AdsLLst>1</AdsLLst>
<AdsLmap>1</AdsLmap>
<AdsLcgr>1</AdsLcgr>
<AdsLsym>1</AdsLsym>
<AdsLszi>1</AdsLszi>
<AdsLtoi>1</AdsLtoi>
<AdsLsun>1</AdsLsun>
<AdsLven>1</AdsLven>
<AdsLsxf>1</AdsLsxf>
<RvctClst>0</RvctClst>
<GenPPlst>0</GenPPlst>
<AdsCpuType>"Cortex-M4"</AdsCpuType>
<RvctDeviceName></RvctDeviceName>
<mOS>0</mOS>
<uocRom>0</uocRom>
<uocRam>0</uocRam>
<hadIROM>1</hadIROM>
<hadIRAM>1</hadIRAM>
<hadXRAM>0</hadXRAM>
<uocXRam>0</uocXRam>
<RvdsVP>1</RvdsVP>
<RvdsMve>0</RvdsMve>
<hadIRAM2>1</hadIRAM2>
<hadIROM2>0</hadIROM2>
<StupSel>8</StupSel>
<useUlib>0</useUlib>
<EndSel>1</EndSel>
<uLtcg>0</uLtcg>
<nSecure>0</nSecure>
<RoSelD>3</RoSelD>
<RwSelD>3</RwSelD>
<CodeSel>0</CodeSel>
<OptFeed>0</OptFeed>
<NoZi1>0</NoZi1>
<NoZi2>0</NoZi2>
<NoZi3>0</NoZi3>
<NoZi4>0</NoZi4>
<NoZi5>0</NoZi5>
<Ro1Chk>0</Ro1Chk>
<Ro2Chk>0</Ro2Chk>
<Ro3Chk>0</Ro3Chk>
<Ir1Chk>1</Ir1Chk>
<Ir2Chk>0</Ir2Chk>
<Ra1Chk>0</Ra1Chk>
<Ra2Chk>0</Ra2Chk>
<Ra3Chk>0</Ra3Chk>
<Im1Chk>1</Im1Chk>
<Im2Chk>0</Im2Chk>
<OnChipMemories>
<Ocm1>
<Type>0</Type>
<StartAddress>0x0</StartAddress>
<Size>0x0</Size>
</Ocm1>
<Ocm2>
<Type>0</Type>
<StartAddress>0x0</StartAddress>
<Size>0x0</Size>
</Ocm2>
<Ocm3>
<Type>0</Type>
<StartAddress>0x0</StartAddress>
<Size>0x0</Size>
</Ocm3>
<Ocm4>
<Type>0</Type>
<StartAddress>0x0</StartAddress>
<Size>0x0</Size>
</Ocm4>
<Ocm5>
<Type>0</Type>
<StartAddress>0x0</StartAddress>
<Size>0x0</Size>
</Ocm5>
<Ocm6>
<Type>0</Type>
<StartAddress>0x0</StartAddress>
<Size>0x0</Size>
</Ocm6>
<IRAM>
<Type>0</Type>
<StartAddress>0x1ffe0000</StartAddress>
<Size>0x80000</Size>
</IRAM>
<IROM>
<Type>1</Type>
<StartAddress>0x0</StartAddress>
<Size>0x200000</Size>
</IROM>
<XRAM>
<Type>0</Type>
<StartAddress>0x0</StartAddress>
<Size>0x0</Size>
</XRAM>
<OCR_RVCT1>
<Type>1</Type>
<StartAddress>0x0</StartAddress>
<Size>0x0</Size>
</OCR_RVCT1>
<OCR_RVCT2>
<Type>1</Type>
<StartAddress>0x0</StartAddress>
<Size>0x0</Size>
</OCR_RVCT2>
<OCR_RVCT3>
<Type>1</Type>
<StartAddress>0x0</StartAddress>
<Size>0x0</Size>
</OCR_RVCT3>
<OCR_RVCT4>
<Type>1</Type>
<StartAddress>0x0</StartAddress>
<Size>0x200000</Size>
</OCR_RVCT4>
<OCR_RVCT5>
<Type>1</Type>
<StartAddress>0x3000000</StartAddress>
<Size>0x1800</Size>
</OCR_RVCT5>
<OCR_RVCT6>
<Type>0</Type>
<StartAddress>0x0</StartAddress>
<Size>0x0</Size>
</OCR_RVCT6>
<OCR_RVCT7>
<Type>0</Type>
<StartAddress>0x0</StartAddress>
<Size>0x0</Size>
</OCR_RVCT7>
<OCR_RVCT8>
<Type>0</Type>
<StartAddress>0x0</StartAddress>
<Size>0x0</Size>
</OCR_RVCT8>
<OCR_RVCT9>
<Type>0</Type>
<StartAddress>0x1ffe0000</StartAddress>
<Size>0x80000</Size>
</OCR_RVCT9>
<OCR_RVCT10>
<Type>0</Type>
<StartAddress>0x200f0000</StartAddress>
<Size>0x1000</Size>
</OCR_RVCT10>
</OnChipMemories>
<RvctStartVector></RvctStartVector>
</ArmAdsMisc>
<Cads>
<interw>1</interw>
<Optim>1</Optim>
<oTime>0</oTime>
<SplitLS>0</SplitLS>
<OneElfS>1</OneElfS>
<Strict>0</Strict>
<EnumInt>0</EnumInt>
<PlainCh>0</PlainCh>
<Ropi>0</Ropi>
<Rwpi>0</Rwpi>
<wLevel>2</wLevel>
<uThumb>0</uThumb>
<uSurpInc>0</uSurpInc>
<uC99>1</uC99>
<uGnu>0</uGnu>
<useXO>0</useXO>
<v6Lang>0</v6Lang>
<v6LangP>0</v6LangP>
<vShortEn>0</vShortEn>
<vShortWch>0</vShortWch>
<v6Lto>0</v6Lto>
<v6WtE>0</v6WtE>
<v6Rtti>0</v6Rtti>
<VariousControls>
<MiscControls></MiscControls>
<Define></Define>
<Undefine></Undefine>
<IncludePath></IncludePath>
</VariousControls>
</Cads>
<Aads>
<interw>1</interw>
<Ropi>0</Ropi>
<Rwpi>0</Rwpi>
<thumb>0</thumb>
<SplitLS>0</SplitLS>
<SwStkChk>0</SwStkChk>
<NoWarn>0</NoWarn>
<uSurpInc>0</uSurpInc>
<useXO>0</useXO>
<uClangAs>0</uClangAs>
<VariousControls>
<MiscControls></MiscControls>
<Define></Define>
<Undefine></Undefine>
<IncludePath></IncludePath>
</VariousControls>
</Aads>
<LDads>
<umfTarg>0</umfTarg>
<Ropi>0</Ropi>
<Rwpi>0</Rwpi>
<noStLib>0</noStLib>
<RepFail>1</RepFail>
<useFile>0</useFile>
<TextAddressRange>0x00000000</TextAddressRange>
<DataAddressRange>0x1FFF8000</DataAddressRange>
<pXoBase></pXoBase>
<ScatterFile>.\board\linker_scripts\link.sct</ScatterFile>
<IncludeLibs></IncludeLibs>
<IncludeLibsPath></IncludeLibsPath>
<Misc></Misc>
<LinkerInputFile></LinkerInputFile>
<DisabledWarnings></DisabledWarnings>
</LDads>
</TargetArmAds>
</TargetOption>
</Target>
</Targets>
<RTE>
<apis/>
<components/>
<files/>
</RTE>
</Project>

6
bsp/hc32/libraries/.ignore_format.yml Normal file
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@ -0,0 +1,6 @@
# files format check exclude path, please follow the instructions below to modify;
# If you need to exclude an entire folder, add the folder path in dir_path;
# If you need to exclude a file, add the path to the file in file_path.
dir_path:
- hc32f4a0_ddl

22
bsp/hc32/libraries/Kconfig Normal file
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@ -0,0 +1,22 @@
config SOC_FAMILY_HC32
bool
config SOC_SERIES_HC32F1
bool
select ARCH_ARM_CORTEX_M0
select SOC_FAMILY_HC32
config SOC_SERIES_HC32F4
bool
select ARCH_ARM_CORTEX_M4
select SOC_FAMILY_HC32
config SOC_SERIES_HC32M1
bool
select ARCH_ARM_CORTEX_M0
select SOC_FAMILY_HC32
config SOC_SERIES_HC32M4
bool
select ARCH_ARM_CORTEX_M4
select SOC_FAMILY_HC32

26
bsp/hc32/libraries/hc32_drivers/Kconfig Normal file
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@ -0,0 +1,26 @@
if BSP_USING_USBD
config BSP_USBD_TYPE_FS
bool
# "USB Full Speed (FS) Core"
config BSP_USBD_TYPE_HS
bool
# "USB High Speed (HS) Core"
config BSP_USBD_SPEED_HS
bool
# "USB High Speed (HS) Mode"
config BSP_USBD_SPEED_HSINFS
bool
# "USB High Speed (HS) Core in FS mode"
config BSP_USBD_PHY_EMBEDDED
bool
# "Using Embedded phy interface"
config BSP_USBD_PHY_UTMI
bool
# "UTMI: USB 2.0 Transceiver Macrocell Interace"
config BSP_USBD_PHY_ULPI
bool
# "ULPI: UTMI+ Low Pin Interface"
endif

74
bsp/hc32/libraries/hc32_drivers/SConscript Normal file
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@ -0,0 +1,74 @@
Import('RTT_ROOT')
Import('rtconfig')
from building import *
cwd = GetCurrentDir()
# add the general drivers.
src = Split("""
drv_irq.c
""")
if GetDepend(['RT_USING_PIN']):
src += ['drv_gpio.c']
if GetDepend(['RT_USING_SERIAL']):
src += ['drv_usart.c']
if GetDepend(['RT_USING_HWTIMER']):
src += ['drv_hwtimer.c']
if GetDepend(['RT_USING_PWM']):
src += ['drv_pwm.c']
if GetDepend(['RT_USING_PULSE_ENCODER']):
src += ['drv_pulse_encoder.c']
if GetDepend(['RT_USING_SPI']):
src += ['drv_spi.c']
if GetDepend(['RT_USING_QSPI']):
src += ['drv_qspi.c']
if GetDepend(['RT_USING_I2C', 'RT_USING_I2C_BITOPS']):
src += ['drv_soft_i2c.c']
if GetDepend(['BSP_USING_ETH', 'RT_USING_LWIP']):
src += ['drv_eth.c']
if GetDepend(['RT_USING_ADC']):
src += ['drv_adc.c']
if GetDepend(['RT_USING_DAC']):
src += ['drv_dac.c']
if GetDepend(['RT_USING_CAN']):
src += ['drv_can.c']
if GetDepend(['RT_USING_PM']):
src += ['drv_pm.c']
if GetDepend(['RT_USING_RTC']):
src += ['drv_rtc.c']
if GetDepend(['RT_USING_ON_CHIP_FLASH']):
src += ['drv_flash.c']
if GetDepend(['RT_USING_WDT']):
src += ['drv_wdt.c']
if GetDepend(['RT_USING_SDIO']):
src += ['drv_sdio.c']
if GetDepend(['RT_USING_USBD']):
src += ['drv_usbd.c']
if GetDepend(['RT_USING_USBH']):
src += ['drv_usbh.c']
path = [cwd]
group = DefineGroup('Drivers', src, depend = [''], CPPPATH = path)
Return('group')

217
bsp/hc32/libraries/hc32_drivers/drv_adc.c Normal file
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/*
* Copyright (C) 2022, Xiaohua Semiconductor Co., Ltd.
*
* SPDX-License-Identifier: Apache-2.0
*
* Change Logs:
* Date Author Notes
* 2022-04-28 CDT first version
*/
#include <board.h>
#include <drivers/adc.h>
#include <drv_adc.h>
#include <drv_config.h>
#define DBG_TAG "drv.adc"
#define DBG_LVL DBG_INFO
#include <rtdbg.h>
#ifdef RT_USING_ADC
typedef struct
{
struct rt_adc_device adc_dev;
CM_ADC_TypeDef *hc32_adc_instance;
struct hc32_adc_init_type init;
} hc32_adc_device;
#if !defined(BSP_USING_ADC1) && !defined(BSP_USING_ADC2) && !defined(BSP_USING_ADC3)
#error "Please define at least one BSP_USING_ADCx"
#endif
static hc32_adc_device g_hc32_devs[] =
{
#ifdef BSP_USING_ADC1
{
{0},
CM_ADC1,
ADC1_CONFIG,
},
#endif
#ifdef BSP_USING_ADC2
{
{0},
CM_ADC2,
ADC2_CONFIG,
},
#endif
#ifdef BSP_USING_ADC3
{
{0},
CM_ADC3,
ADC3_CONFIG,
},
#endif
};
static void internal_trigger0_set(hc32_adc_device *dev)
{
uint32_t u32TriggerSel;
rt_bool_t is_internal_trig0_enabled = (dev->init.hard_trig_src == ADC_HARDTRIG_EVT0 || dev->init.hard_trig_src == ADC_HARDTRIG_EVT0_EVT1);
if (is_internal_trig0_enabled == RT_FALSE)
{
return;
}
#if defined(HC32F4A0)
switch ((rt_uint32_t)dev->hc32_adc_instance)
{
case (rt_uint32_t)CM_ADC1:
u32TriggerSel = AOS_ADC1_0;
break;
case (rt_uint32_t)CM_ADC2:
u32TriggerSel = AOS_ADC2_0;
break;
case (rt_uint32_t)CM_ADC3:
u32TriggerSel = AOS_ADC3_0;
break;
default:
break;
}
AOS_CommonTriggerCmd(u32TriggerSel, AOS_COMM_TRIG1, (en_functional_state_t)dev->init.internal_trig0_comtrg0_enable);
AOS_CommonTriggerCmd(u32TriggerSel, AOS_COMM_TRIG2, (en_functional_state_t)dev->init.internal_trig0_comtrg1_enable);
#endif
AOS_SetTriggerEventSrc(u32TriggerSel, dev->init.internal_trig0_sel);
}
static void internal_trigger1_set(hc32_adc_device *dev)
{
uint32_t u32TriggerSel;
rt_bool_t is_internal_trig1_enabled = (dev->init.hard_trig_src == ADC_HARDTRIG_EVT1 || dev->init.hard_trig_src == ADC_HARDTRIG_EVT0_EVT1);
if (is_internal_trig1_enabled == RT_FALSE)
{
return;
}
#if defined(HC32F4A0)
switch ((rt_uint32_t)dev->hc32_adc_instance)
{
case (rt_uint32_t)CM_ADC1:
u32TriggerSel = AOS_ADC1_1;
break;
case (rt_uint32_t)CM_ADC2:
u32TriggerSel = AOS_ADC2_1;
break;
case (rt_uint32_t)CM_ADC3:
u32TriggerSel = AOS_ADC3_1;
break;
default:
break;
}
AOS_CommonTriggerCmd(u32TriggerSel, AOS_COMM_TRIG1, (en_functional_state_t)dev->init.internal_trig0_comtrg0_enable);
AOS_CommonTriggerCmd(u32TriggerSel, AOS_COMM_TRIG2, (en_functional_state_t)dev->init.internal_trig0_comtrg1_enable);
#endif
AOS_SetTriggerEventSrc(u32TriggerSel, dev->init.internal_trig1_sel);
}
static rt_err_t hc32_adc_enabled(struct rt_adc_device *device, rt_uint32_t channel, rt_bool_t enabled)
{
hc32_adc_device *adc;
adc = rt_container_of(device, hc32_adc_device, adc_dev);
ADC_ChCmd(adc->hc32_adc_instance, ADC_SEQ_A, channel, (en_functional_state_t)enabled);
return 0;
}
static rt_err_t hc32_adc_convert(struct rt_adc_device *device, rt_uint32_t channel, rt_uint32_t *value)
{
rt_err_t rt_ret = RT_ERROR;
if (!value)
{
return -RT_EINVAL;
}
hc32_adc_device *adc;
adc = rt_container_of(device, hc32_adc_device, adc_dev);
if (adc->init.hard_trig_enable == RT_FALSE && adc->hc32_adc_instance->STR == 0)
{
ADC_Start(adc->hc32_adc_instance);
}
uint32_t start_time = rt_tick_get();
do
{
if (ADC_GetStatus(adc->hc32_adc_instance, ADC_FLAG_EOCA) == SET)
{
ADC_ClearStatus(adc->hc32_adc_instance, ADC_FLAG_EOCA);
rt_ret = LL_OK;
break;
}
}
while ((rt_tick_get() - start_time) < adc->init.eoc_poll_time_max);
if (rt_ret == LL_OK)
{
/* Get any ADC value of sequence A channel that needed. */
*value = ADC_GetValue(adc->hc32_adc_instance, channel);
}
return rt_ret;
}
static struct rt_adc_ops g_hc32_adc_ops =
{
hc32_adc_enabled,
hc32_adc_convert,
};
extern rt_err_t rt_hw_board_adc_init(CM_ADC_TypeDef *ADCx);
extern void rt_hw_board_adc_clock_init(void);
static int rt_hw_adc_init(void)
{
int ret, i = 0;
stc_adc_init_t stcAdcInit = {0};
int32_t ll_ret = 0;
rt_hw_board_adc_clock_init();
uint32_t dev_cnt = sizeof(g_hc32_devs) / sizeof(g_hc32_devs[0]);
for (; i < dev_cnt; i++)
{
ADC_DeInit(g_hc32_devs[i].hc32_adc_instance);
/* Initializes ADC. */
stcAdcInit.u16Resolution = g_hc32_devs[i].init.resolution;
stcAdcInit.u16DataAlign = g_hc32_devs[i].init.data_align;
stcAdcInit.u16ScanMode = (g_hc32_devs[i].init.continue_conv_mode_enable) ? ADC_MD_SEQA_CONT : ADC_MD_SEQA_SINGLESHOT;
ll_ret = ADC_Init((void *)g_hc32_devs[i].hc32_adc_instance, &stcAdcInit);
if (ll_ret != LL_OK)
{
ret = -RT_ERROR;
break;
}
ADC_TriggerCmd(g_hc32_devs[i].hc32_adc_instance, ADC_SEQ_A, (en_functional_state_t)g_hc32_devs[i].init.hard_trig_enable);
ADC_TriggerConfig(g_hc32_devs[i].hc32_adc_instance, ADC_SEQ_A, g_hc32_devs[i].init.hard_trig_src);
if (g_hc32_devs[i].init.hard_trig_enable && g_hc32_devs[i].init.hard_trig_src != ADC_HARDTRIG_ADTRG_PIN)
{
internal_trigger0_set(&g_hc32_devs[i]);
internal_trigger1_set(&g_hc32_devs[i]);
}
rt_hw_board_adc_init((void *)g_hc32_devs[i].hc32_adc_instance);
ret = rt_hw_adc_register(&g_hc32_devs[i].adc_dev, \
(const char *)g_hc32_devs[i].init.name, \
&g_hc32_adc_ops, (void *)g_hc32_devs[i].hc32_adc_instance);
if (ret != RT_EOK)
{
/* TODO err handler */
// LOG_E("failed register %s, err=%d", g_hc32_devs[i].name, ret);
}
}
return ret;
}
INIT_DEVICE_EXPORT(rt_hw_adc_init);
#endif

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/*
* Copyright (C) 2022, Xiaohua Semiconductor Co., Ltd.
*
* SPDX-License-Identifier: Apache-2.0
*
* Change Logs:
* Date Author Notes
* 2022-04-28 CDT first version
*/
#ifndef __DRV_ADC_H__
#define __DRV_ADC_H__
/*******************************************************************************
* Include files
******************************************************************************/
#include <rtthread.h>
#include "rtdevice.h"
#include "hc32_ll.h"
/* C binding of definitions if building with C++ compiler */
#ifdef __cplusplus
extern "C"
{
#endif
/*******************************************************************************
* Global type definitions ('typedef')
******************************************************************************/
struct hc32_adc_init_type
{
char name[8];
uint16_t resolution; /*!< Specifies the ADC resolution.
This parameter can be a value of @ref ADC_Resolution */
uint16_t data_align; /*!< Specifies ADC data alignment.
This parameter can be a value of @ref ADC_Data_Align */
rt_bool_t hard_trig_enable;
uint32_t hard_trig_src; /*a value of @ref ADC_Hard_Trigger_Sel */
rt_bool_t internal_trig0_comtrg0_enable;
rt_bool_t internal_trig0_comtrg1_enable;
en_event_src_t internal_trig0_sel; /*@ref en_event_src_t in details */
rt_bool_t internal_trig1_comtrg0_enable;
rt_bool_t internal_trig1_comtrg1_enable;
en_event_src_t internal_trig1_sel; /*@ref en_event_src_t in details */
rt_bool_t continue_conv_mode_enable;
rt_bool_t data_reg_auto_clear;
uint32_t eoc_poll_time_max;
};
/*******************************************************************************
* Global pre-processor symbols/macros ('#define')
******************************************************************************/
/*******************************************************************************
* Global variable definitions ('extern')
******************************************************************************/
/*******************************************************************************
* Global function prototypes (definition in C source)
******************************************************************************/
int rt_hw_uart_init(void);
#ifdef __cplusplus
}
#endif
#endif /* __DRV_USART_H__ */
/*******************************************************************************
* EOF (not truncated)
******************************************************************************/

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/*
* Copyright (C) 2022, Xiaohua Semiconductor Co., Ltd.
*
* SPDX-License-Identifier: Apache-2.0
*
* Change Logs:
* Date Author Notes
* 2022-04-28 CDT first version
*/
#include "drv_can.h"
#include <drv_config.h>
#include <board_config.h>
#ifdef BSP_USING_CAN
#define LOG_TAG "drv_can"
#if !defined(BSP_USING_CAN1) && !defined(BSP_USING_CAN2)
#error "Please define at least one BSP_USING_CANx"
#endif
#if defined (HC32F4A0)
#define FILTER_COUNT (16)
#endif
enum
{
#ifdef BSP_USING_CAN1
CAN1_INDEX,
#endif
#ifdef BSP_USING_CAN2
CAN2_INDEX,
#endif
CAN_INDEX_MAX,
};
struct hc32_baud_rate_tab
{
rt_uint32_t baud_rate;
stc_can_bit_time_config_t ll_sbt;
};
#if defined (HC32F4A0)
static const struct hc32_baud_rate_tab can_baud_rate_tab[] =
{
{CAN1MBaud, {2, 16, 4, 4}},
{CAN800kBaud, {2, 20, 5, 4}},
{CAN500kBaud, {4, 16, 4, 4}},
{CAN250kBaud, {8, 16, 4, 4}},
{CAN125kBaud, {16, 16, 4, 4}},
{CAN100kBaud, {20, 16, 4, 4}},
{CAN50kBaud, {40, 16, 4, 4}},
{CAN20kBaud, {100, 16, 4, 4}},
{CAN10kBaud, {200, 16, 4, 4}},
};
#endif
typedef struct
{
struct rt_can_device rt_can;
struct hc32_can_init_type init;
CM_CAN_TypeDef *instance;
stc_can_init_t ll_init;
stc_can_filter_config_t *p_ll_can_filter_cfg;
} hc32_drv_can;
static hc32_drv_can drv_can[] =
{
#ifdef BSP_USING_CAN1
{
{0},
CAN1_CONFIG,
.instance = CM_CAN1,
},
#endif
#ifdef BSP_USING_CAN2
{
{0},
CAN2_CONFIG,
.instance = CM_CAN2,
},
#endif
};
static rt_uint32_t get_can_baud_index(rt_uint32_t baud)
{
rt_uint32_t len, index;
len = sizeof(can_baud_rate_tab) / sizeof(can_baud_rate_tab[0]);
for (index = 0; index < len; index++)
{
if (can_baud_rate_tab[index].baud_rate == baud)
return index;
}
return 0; /* default baud is CAN1MBaud */
}
static rt_uint32_t get_can_work_mode(rt_uint32_t mode)
{
rt_uint32_t work_mode;
switch (mode)
{
case RT_CAN_MODE_NORMAL:
work_mode = CAN_WORK_MD_NORMAL;
break;
case RT_CAN_MODE_LISEN:
work_mode = CAN_WORK_MD_SILENT;
break;
case RT_CAN_MODE_LOOPBACK:
work_mode = CAN_WORK_MD_ELB;
break;
case RT_CAN_MODE_LOOPBACKANLISEN:
work_mode = CAN_WORK_MD_ELB_SILENT;
break;
default:
work_mode = CAN_WORK_MD_NORMAL;
break;
}
return work_mode;
}
static rt_err_t _can_config(struct rt_can_device *can, struct can_configure *cfg)
{
rt_uint32_t baud_index;
hc32_drv_can *hc32_can;
rt_err_t rt_ret = RT_EOK;
RT_ASSERT(can);
RT_ASSERT(cfg);
hc32_can = (hc32_drv_can *)rt_container_of(can, hc32_drv_can, rt_can);
RT_ASSERT(hc32_can);
hc32_can->ll_init.u8WorkMode = get_can_work_mode(cfg->mode);
baud_index = get_can_baud_index(cfg->baud_rate);
hc32_can->ll_init.stcBitCfg = can_baud_rate_tab[baud_index].ll_sbt;
/* init can */
int32_t ret = CAN_Init(hc32_can->instance, &hc32_can->ll_init);
if (ret != LL_OK)
{
rt_ret = RT_EINVAL;
}
return rt_ret;
}
static uint16_t get_filter_idx(struct rt_can_filter_config *filter_cfg)
{
uint16_t u16FilterSelected = 0;
for (int i = 0; i < filter_cfg->count; i++)
{
if (filter_cfg->items[i].hdr != -1)
{
u16FilterSelected |= 1 << filter_cfg->items[i].hdr;
}
}
for (int i = 0; i < filter_cfg->count; i++)
{
if (filter_cfg->items[i].hdr == -1)
{
for (int j = 0; j < FILTER_COUNT; j++)
{
if ((u16FilterSelected & 1 << j) == 0)
{
filter_cfg->items[i].hdr = j;
u16FilterSelected |= 1 << filter_cfg->items[i].hdr;
break;
}
}
}
}
return u16FilterSelected;
}
static rt_err_t _can_control(struct rt_can_device *can, int cmd, void *arg)
{
hc32_drv_can *hc32_can;
rt_uint32_t argval;
struct rt_can_filter_config *filter_cfg;
RT_ASSERT(can != RT_NULL);
hc32_can = (hc32_drv_can *)rt_container_of(can, hc32_drv_can, rt_can);
RT_ASSERT(hc32_can);
switch (cmd)
{
case RT_DEVICE_CTRL_CLR_INT:
argval = (rt_uint32_t) arg;
switch (argval)
{
case RT_DEVICE_FLAG_INT_RX:
CAN_IntCmd(hc32_can->instance, CAN_FLAG_RX, DISABLE);
CAN_IntCmd(hc32_can->instance, CAN_FLAG_RX_BUF_WARN, DISABLE);
CAN_IntCmd(hc32_can->instance, CAN_FLAG_RX_BUF_FULL, DISABLE);
CAN_IntCmd(hc32_can->instance, CAN_FLAG_RX_OVERRUN, DISABLE);
break;
case RT_DEVICE_FLAG_INT_TX:
CAN_IntCmd(hc32_can->instance, CAN_FLAG_STB_TX, DISABLE);
CAN_IntCmd(hc32_can->instance, CAN_FLAG_PTB_TX, DISABLE);
break;
case RT_DEVICE_CAN_INT_ERR:
CAN_IntCmd(hc32_can->instance, CAN_INT_ERR_INT, DISABLE);
CAN_IntCmd(hc32_can->instance, CAN_INT_ARBITR_LOST, DISABLE);
CAN_IntCmd(hc32_can->instance, CAN_INT_ERR_PASSIVE, DISABLE);
CAN_IntCmd(hc32_can->instance, CAN_INT_BUS_ERR, DISABLE);
break;
default:
break;
}
break;
case RT_DEVICE_CTRL_SET_INT:
argval = (rt_uint32_t) arg;
switch (argval)
{
case RT_DEVICE_FLAG_INT_RX:
CAN_IntCmd(hc32_can->instance, CAN_FLAG_RX, ENABLE);
CAN_IntCmd(hc32_can->instance, CAN_FLAG_RX_BUF_WARN, ENABLE);
CAN_IntCmd(hc32_can->instance, CAN_FLAG_RX_BUF_FULL, ENABLE);
CAN_IntCmd(hc32_can->instance, CAN_FLAG_RX_OVERRUN, ENABLE);
break;
case RT_DEVICE_FLAG_INT_TX:
CAN_IntCmd(hc32_can->instance, CAN_FLAG_STB_TX, ENABLE);
CAN_IntCmd(hc32_can->instance, CAN_FLAG_PTB_TX, ENABLE);
break;
case RT_DEVICE_CAN_INT_ERR:
CAN_IntCmd(hc32_can->instance, CAN_INT_ERR_INT, ENABLE);
CAN_IntCmd(hc32_can->instance, CAN_INT_ARBITR_LOST, ENABLE);
CAN_IntCmd(hc32_can->instance, CAN_INT_ERR_PASSIVE, ENABLE);
CAN_IntCmd(hc32_can->instance, CAN_INT_BUS_ERR, ENABLE);
break;
default:
break;
}
break;
case RT_CAN_CMD_SET_FILTER:
if (RT_NULL != arg)
{
filter_cfg = (struct rt_can_filter_config *)arg;
if (filter_cfg->count == 0)
{
return -RT_EINVAL;
}
RT_ASSERT(filter_cfg->count <= FILTER_COUNT);
/* get default filter */
if (hc32_can->p_ll_can_filter_cfg)
{
hc32_can->ll_init.u16FilterSelect = get_filter_idx(filter_cfg);
for (int i = 0; i < filter_cfg->count; i++)
{
hc32_can->p_ll_can_filter_cfg[i].u32ID = filter_cfg->items[i].id;
hc32_can->p_ll_can_filter_cfg[i].u32IDMask = filter_cfg->items[i].mask;
hc32_can->p_ll_can_filter_cfg[i].u32IDType = filter_cfg->items[i].ide;
}
}
(void)CAN_Init(hc32_can->instance, &hc32_can->ll_init);
break;
}
case RT_CAN_CMD_SET_MODE:
argval = (rt_uint32_t) arg;
if (argval != RT_CAN_MODE_NORMAL &&
argval != RT_CAN_MODE_LISEN &&
argval != RT_CAN_MODE_LOOPBACK &&
argval != RT_CAN_MODE_LOOPBACKANLISEN)
{
return -RT_ERROR;
}
if (argval != hc32_can->rt_can.config.mode)
{
hc32_can->rt_can.config.mode = argval;
_can_config(can, &hc32_can->rt_can.config);
}
break;
case RT_CAN_CMD_SET_BAUD:
argval = (rt_uint32_t) arg;
if (argval != CAN1MBaud &&
argval != CAN800kBaud &&
argval != CAN500kBaud &&
argval != CAN250kBaud &&
argval != CAN125kBaud &&
argval != CAN100kBaud &&
argval != CAN50kBaud &&
argval != CAN20kBaud &&
argval != CAN10kBaud)
{
return -RT_ERROR;
}
if (argval != hc32_can->rt_can.config.baud_rate)
{
hc32_can->rt_can.config.baud_rate = argval;
_can_config(can, &hc32_can->rt_can.config);
}
break;
case RT_CAN_CMD_SET_PRIV:
argval = (rt_uint32_t) arg;
if (argval != RT_CAN_MODE_PRIV &&
argval != RT_CAN_MODE_NOPRIV)
{
return -RT_ERROR;
}
if (argval != hc32_can->rt_can.config.privmode)
{
hc32_can->rt_can.config.privmode = argval;
return _can_config(can, &hc32_can->rt_can.config);
}
break;
case RT_CAN_CMD_GET_STATUS:
{
struct rt_can_status *rt_can_stat = (struct rt_can_status *)arg;
stc_can_error_info_t stcErr = {0};
CAN_GetErrorInfo(hc32_can->instance, &stcErr);
rt_can_stat->rcverrcnt = stcErr.u8RxErrorCount;
rt_can_stat->snderrcnt = stcErr.u8TxErrorCount;
rt_can_stat->lasterrtype = stcErr.u8ErrorType;
rt_can_stat->errcode = CAN_GetStatusValue(hc32_can->instance);
}
break;
default:
break;
}
return RT_EOK;
}
static int _can_sendmsg(struct rt_can_device *can, const void *buf, rt_uint32_t box_num)
{
struct rt_can_msg *pmsg = (struct rt_can_msg *) buf;
stc_can_tx_frame_t stc_tx_frame = {0};
int32_t ll_ret;
RT_ASSERT(can != RT_NULL);
hc32_drv_can *hc32_can = (hc32_drv_can *)rt_container_of(can, hc32_drv_can, rt_can);
RT_ASSERT(hc32_can);
/*check select mailbox is empty */
stc_tx_frame.u32ID = pmsg->id;
if (RT_CAN_DTR == pmsg->rtr)
{
stc_tx_frame.RTR = 0;
}
else
{
stc_tx_frame.RTR = 1;
}
/* Set up the DLC */
stc_tx_frame.DLC = pmsg->len & 0x0FU;
/* Set up the data field */
rt_memcpy(&stc_tx_frame.au8Data, pmsg->data, sizeof(stc_tx_frame.au8Data));
ll_ret = CAN_FillTxFrame(hc32_can->instance, CAN_TX_BUF_PTB, &stc_tx_frame);
if (ll_ret != LL_OK)
{
return RT_ERROR;
}
/* Request transmission */
CAN_StartTx(hc32_can->instance, CAN_TX_REQ_PTB);
return RT_EOK;
}
static int _can_recvmsg(struct rt_can_device *can, void *buf, rt_uint32_t fifo)
{
int32_t ll_ret;
struct rt_can_msg *pmsg;
stc_can_rx_frame_t ll_rx_frame;
RT_ASSERT(can != RT_NULL);
hc32_drv_can *hc32_can = (hc32_drv_can *)rt_container_of(can, hc32_drv_can, rt_can);
RT_ASSERT(hc32_can);
pmsg = (struct rt_can_msg *) buf;
/* get data */
ll_ret = CAN_GetRxFrame(hc32_can->instance, &ll_rx_frame);
if (ll_ret != LL_OK)
return -RT_ERROR;
/* get id */
if (CAN_ID_STD == ll_rx_frame.IDE)
{
pmsg->ide = RT_CAN_STDID;
}
else
{
pmsg->ide = RT_CAN_EXTID;
}
pmsg->id = ll_rx_frame.u32ID;
/* get type */
if (0 == ll_rx_frame.RTR)
{
pmsg->rtr = RT_CAN_DTR;
}
else
{
pmsg->rtr = RT_CAN_RTR;
}
/* get len */
pmsg->len = ll_rx_frame.DLC;
/* get hdr */
pmsg->hdr = 0;
rt_memcpy(pmsg->data, &ll_rx_frame.au8Data, ll_rx_frame.DLC);
return RT_EOK;
}
static const struct rt_can_ops _can_ops =
{
_can_config,
_can_control,
_can_sendmsg,
_can_recvmsg,
};
static void can_isr(hc32_drv_can *hc32_can)
{
stc_can_error_info_t stcErr;
(void)CAN_GetErrorInfo(hc32_can->instance, &stcErr);
if (CAN_GetStatus(hc32_can->instance, CAN_FLAG_BUS_OFF) == SET)
{
DDL_Printf("BUS OFF.\r\n");
}
if (CAN_GetStatus(hc32_can->instance, CAN_FLAG_RX_BUF_OVF) == SET)
{
DDL_Printf("RX overflow.\r\n");
rt_hw_can_isr(&hc32_can->rt_can, RT_CAN_EVENT_RXOF_IND);
CAN_ClearStatus(hc32_can->instance, CAN_FLAG_RX_BUF_OVF);
}
if (CAN_GetStatus(hc32_can->instance, CAN_FLAG_TX_BUF_FULL) == SET)
{
DDL_Printf("TX buffer full.\r\n");
}
if (CAN_GetStatus(hc32_can->instance, CAN_FLAG_TX_ABORTED) == SET)
{
DDL_Printf("TX aborted.\r\n");
CAN_ClearStatus(hc32_can->instance, CAN_FLAG_TX_ABORTED);
}
if (CAN_GetStatus(hc32_can->instance, CAN_FLAG_ARBITR_LOST) == SET)
{
rt_hw_can_isr(&hc32_can->rt_can, RT_CAN_EVENT_TX_FAIL);
CAN_ClearStatus(hc32_can->instance, CAN_FLAG_ARBITR_LOST);
}
if (CAN_GetStatus(hc32_can->instance, CAN_FLAG_STB_TX) == SET)
{
DDL_Printf("STB transmitted.\r\n");
CAN_ClearStatus(hc32_can->instance, CAN_FLAG_STB_TX);
rt_hw_can_isr(&hc32_can->rt_can, RT_CAN_EVENT_TX_DONE);
}
if (CAN_GetStatus(hc32_can->instance, CAN_FLAG_PTB_TX) == SET)
{
DDL_Printf("PTB transmitted.\r\n");
CAN_ClearStatus(hc32_can->instance, CAN_FLAG_PTB_TX);
rt_hw_can_isr(&hc32_can->rt_can, RT_CAN_EVENT_TX_DONE);
}
if (CAN_GetStatus(hc32_can->instance, CAN_FLAG_RX) == SET)
{
/* Received frame can be read here. */
DDL_Printf("Received a frame.\r\n");
CAN_ClearStatus(hc32_can->instance, CAN_FLAG_RX);
rt_hw_can_isr(&hc32_can->rt_can, RT_CAN_EVENT_RX_IND);
}
if (CAN_GetStatus(hc32_can->instance, CAN_FLAG_RX_BUF_WARN) == SET)
{
/* Received frames can be read here. */
DDL_Printf("RX buffer warning.\r\n");
CAN_ClearStatus(hc32_can->instance, CAN_FLAG_RX_BUF_WARN);
}
if (CAN_GetStatus(hc32_can->instance, CAN_FLAG_RX_BUF_FULL) == SET)
{
/* Received frames can be read here. */
DDL_Printf("RX buffer full.\r\n");
CAN_ClearStatus(hc32_can->instance, CAN_FLAG_RX_BUF_FULL);
}
if (CAN_GetStatus(hc32_can->instance, CAN_FLAG_RX_OVERRUN) == SET)
{
DDL_Printf("RX buffer overrun.\r\n");
CAN_ClearStatus(hc32_can->instance, CAN_FLAG_RX_OVERRUN);
}
if (CAN_GetStatus(hc32_can->instance, CAN_FLAG_TEC_REC_WARN) == SET)
{
DDL_Printf("TEC or REC reached warning limit.\r\n");
CAN_ClearStatus(hc32_can->instance, CAN_FLAG_TEC_REC_WARN);
}
if (CAN_TTC_GetStatus(hc32_can->instance, CAN_TTC_FLAG_TIME_TRIG) == SET)
{
DDL_Printf("Time trigger interrupt.\r\n");
CAN_TTC_ClearStatus(hc32_can->instance, CAN_TTC_FLAG_TIME_TRIG);
}
if (CAN_TTC_GetStatus(hc32_can->instance, CAN_TTC_FLAG_TRIG_ERR) == SET)
{
DDL_Printf("Trigger error interrupt.\r\n");
}
if (CAN_TTC_GetStatus(hc32_can->instance, CAN_TTC_FLAG_WATCH_TRIG) == SET)
{
DDL_Printf("Watch trigger interrupt.\r\n");
CAN_TTC_ClearStatus(hc32_can->instance, CAN_TTC_FLAG_WATCH_TRIG);
}
}
#if defined(BSP_USING_CAN1)
static void can1_irq_handler(void)
{
rt_interrupt_enter();
can_isr(&drv_can[CAN1_INDEX]);
rt_interrupt_leave();
}
#endif
#if defined(BSP_USING_CAN2)
static void can2_irq_handler(void)
{
rt_interrupt_enter();
can_isr(&drv_can[CAN2_INDEX]);
rt_interrupt_leave();
}
#endif
extern rt_err_t rt_hw_board_can_init(CM_CAN_TypeDef *CANx);
extern void CanPhyEnable(void);
int rt_hw_can_init(void)
{
struct can_configure rt_can_config = CANDEFAULTCONFIG;
rt_can_config.privmode = RT_CAN_MODE_NOPRIV;
rt_can_config.ticks = 50;
#ifdef RT_CAN_USING_HDR
rt_can_config.maxhdr = FILTER_COUNT;
#endif
struct hc32_irq_config irq_config;
#if defined(BSP_USING_CAN1)
irq_config.irq_num = CAN1_INT_IRQn;
irq_config.int_src = CAN1_INT_SRC;
irq_config.irq_prio = CAN1_INT_PRIO;
/* register interrupt */
hc32_install_irq_handler(&irq_config,
can1_irq_handler,
RT_TRUE);
#endif
#if defined(BSP_USING_CAN2)
irq_config.irq_num = CAN2_INT_IRQn;
irq_config.int_src = CAN2_INT_SRC;
irq_config.irq_prio = CAN2_INT_PRIO;
/* register interrupt */
hc32_install_irq_handler(&irq_config,
can2_irq_handler,
RT_TRUE);
#endif
#if defined(HC32F4A0)
#if defined(BSP_USING_CAN1)
CLK_SetCANClockSrc(CLK_CAN1, CLK_CANCLK_SYSCLK_DIV6);
FCG_Fcg1PeriphClockCmd(FCG1_PERIPH_CAN1, ENABLE);
#endif
#if defined(BSP_USING_CAN2)
CLK_SetCANClockSrc(CLK_CAN2, CLK_CANCLK_SYSCLK_DIV6);
FCG_Fcg1PeriphClockCmd(FCG1_PERIPH_CAN2, ENABLE);
#endif
#endif
CanPhyEnable();
int result = RT_EOK;
uint32_t i = 0;
for (; i < CAN_INDEX_MAX; i++)
{
if (drv_can[i].p_ll_can_filter_cfg == RT_NULL)
{
drv_can[i].p_ll_can_filter_cfg = (stc_can_filter_config_t *)rt_malloc(sizeof(stc_can_filter_config_t) * FILTER_COUNT);
}
RT_ASSERT((drv_can[i].p_ll_can_filter_cfg != RT_NULL));
rt_memset(drv_can[i].p_ll_can_filter_cfg, 0, sizeof(stc_can_filter_config_t) * FILTER_COUNT);
drv_can[i].p_ll_can_filter_cfg[0].u32ID = 0U;
drv_can[i].p_ll_can_filter_cfg[0].u32IDMask = 0x1FFFFFFF;
drv_can[i].p_ll_can_filter_cfg[0].u32IDType = CAN_ID_STD;
CAN_StructInit(&drv_can[i].ll_init);
drv_can[i].ll_init.pstcFilter = &drv_can[i].p_ll_can_filter_cfg[0];
drv_can[i].ll_init.u16FilterSelect = CAN_FILTER1;
drv_can[i].rt_can.config = rt_can_config;
/* register CAN1 device */
rt_hw_board_can_init(drv_can[i].instance);
rt_hw_can_register(&drv_can[i].rt_can,
drv_can[i].init.name,
&_can_ops,
&drv_can[i]);
}
return result;
}
INIT_DEVICE_EXPORT(rt_hw_can_init);
#endif /* BSP_USING_CAN */
/************************** end of file ******************/

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/*
* Copyright (C) 2022, Xiaohua Semiconductor Co., Ltd.
*
* SPDX-License-Identifier: Apache-2.0
*
* Change Logs:
* Date Author Notes
* 2022-04-28 CDT first version
*/
#ifndef __DRV_CAN_H__
#define __DRV_CAN_H__
#ifdef __cplusplus
extern "C" {
#endif
#include <board.h>
#include <rtdevice.h>
#include <rtthread.h>
/* stm32 can device */
struct hc32_can_init_type
{
char *name;
};
int rt_hw_can_init(void);
#ifdef __cplusplus
}
#endif
#endif /*__DRV_CAN_H__ */
/************************** end of file ******************/

40
bsp/hc32/libraries/hc32_drivers/drv_dma.h Normal file
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/*
* Copyright (C) 2022, Xiaohua Semiconductor Co., Ltd.
*
* SPDX-License-Identifier: Apache-2.0
*
* Change Logs:
* Date Author Notes
* 2022-04-28 CDT first version
*/
#ifndef __DRV_DMA_H__
#define __DRV_DMA_H__
/*******************************************************************************
* Include files
******************************************************************************/
#include <rtthread.h>
#include "drv_irq.h"
#ifdef __cplusplus
extern "C" {
#endif
struct dma_config
{
CM_DMA_TypeDef *Instance;
rt_uint32_t channel;
rt_uint32_t clock;
rt_uint32_t trigger_select;
en_event_src_t trigger_event;
struct hc32_irq_config irq_config;
func_ptr_t irq_callback;
};
#ifdef __cplusplus
}
#endif
#endif /* __DRV_DMA_H__ */

642
bsp/hc32/libraries/hc32_drivers/drv_eth.c Normal file
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/*
* Copyright (C) 2022, Xiaohua Semiconductor Co., Ltd.
*
* SPDX-License-Identifier: Apache-2.0
*
* Change Logs:
* Date Author Notes
* 2022-04-28 CDT first version
*/
/*******************************************************************************
* Include files
******************************************************************************/
#include "drv_eth.h"
#if defined(BSP_USING_ETH)
#include <netif/ethernetif.h>
#include <lwipopts.h>
#include "drv_irq.h"
#include "board_config.h"
/*******************************************************************************
* Local pre-processor symbols/macros ('#define')
******************************************************************************/
//#define DRV_DEBUG
#define LOG_TAG "drv.eth"
#include <drv_log.h>
#define MAX_ADDR_LEN 6
/*******************************************************************************
* Local type definitions ('typedef')
******************************************************************************/
struct hc32_eth
{
/* inherit from ethernet device */
struct eth_device parent;
#if !(defined(PHY_USING_INTERRUPT_MODE) && defined(ETH_USING_INTERFACE_RMII))
rt_timer_t poll_link_timer;
#endif
/* interface address info, hw address */
rt_uint8_t dev_addr[MAX_ADDR_LEN];
/* ETH_Speed */
rt_uint32_t eth_speed;
/* ETH_Duplex_Mode */
rt_uint32_t eth_mode;
/* eth irq */
struct hc32_irq_config irq_config;
func_ptr_t irq_callback;
};
/* eth phy status */
enum
{
ETH_PHY_LINK = 0x01U,
ETH_PHY_100M = 0x02U,
ETH_PHY_FULL_DUPLEX = 0x04U,
};
/*******************************************************************************
* Global variable definitions (declared in header file with 'extern')
******************************************************************************/
extern rt_err_t rt_hw_eth_board_init(CM_ETH_TypeDef *CM_ETHx);
extern rt_err_t rt_hw_eth_phy_reset(CM_ETH_TypeDef *CM_ETHx);
/*******************************************************************************
* Local function prototypes ('static')
******************************************************************************/
static void eth_global_irq_handle(void);
/*******************************************************************************
* Local variable definitions ('static')
******************************************************************************/
static stc_eth_handle_t EthHandle;
/* Ethernet Tx,Rx DMA Descriptor */
static stc_eth_dma_desc_t *EthDmaTxDscrTab, *EthDmaRxDscrTab;
/* Ethernet Transmit,Receive Buffer */
static rt_uint8_t *EthTxBuff, *EthRxBuff;
static struct hc32_eth hc32_eth_device =
{
.irq_config = ETH_IRQ_CONFIG,
.irq_callback = eth_global_irq_handle,
};
/*******************************************************************************
* Function implementation - global ('extern') and local ('static')
******************************************************************************/
static rt_err_t rt_hc32_eth_init(rt_device_t dev)
{
stc_eth_init_t stcEthInit;
uint16_t u16RegVal;
/* Enable ETH clock */
FCG_Fcg1PeriphClockCmd(FCG1_PERIPH_ETHMAC, ENABLE);
/* Init Ethernet GPIO */
rt_hw_eth_phy_reset(CM_ETH);
rt_hw_eth_board_init(CM_ETH);
/* Reset ETHERNET */
(void)ETH_DeInit();
/* Configure structure initialization */
(void)ETH_CommStructInit(&EthHandle.stcCommInit);
(void)ETH_StructInit(&stcEthInit);
EthHandle.stcCommInit.u16AutoNego = ETH_AUTO_NEGO_DISABLE;
EthHandle.stcCommInit.au8MacAddr[0] = hc32_eth_device.dev_addr[0];
EthHandle.stcCommInit.au8MacAddr[1] = hc32_eth_device.dev_addr[1];
EthHandle.stcCommInit.au8MacAddr[2] = hc32_eth_device.dev_addr[2];
EthHandle.stcCommInit.au8MacAddr[3] = hc32_eth_device.dev_addr[3];
EthHandle.stcCommInit.au8MacAddr[4] = hc32_eth_device.dev_addr[4];
EthHandle.stcCommInit.au8MacAddr[5] = hc32_eth_device.dev_addr[5];
#ifdef ETH_USING_INTERFACE_RMII
EthHandle.stcCommInit.u32Interface = ETH_MAC_IF_RMII;
#else
EthHandle.stcCommInit.u32Interface = ETH_MAC_IF_MII;
#endif
EthHandle.stcCommInit.u32ReceiveMode = ETH_RX_MD_INT;
#ifdef RT_LWIP_USING_HW_CHECKSUM
EthHandle.stcCommInit.u32ChecksumMode = ETH_MAC_CHECKSUM_MD_HW;
#else
EthHandle.stcCommInit.u32ChecksumMode = ETH_MAC_CHECKSUM_MD_SW;
#endif
/* Configure ethernet peripheral */
if (LL_OK != ETH_Init(&EthHandle, &stcEthInit))
{
LOG_E("eth hardware init failed");
}
else
{
LOG_D("eth hardware init success");
}
/* Initialize Tx Descriptors list: Chain Mode */
(void)ETH_DMA_TxDescListInit(&EthHandle, EthDmaTxDscrTab, EthTxBuff, ETH_TX_BUF_NUM);
/* Initialize Rx Descriptors list: Chain Mode */
(void)ETH_DMA_RxDescListInit(&EthHandle, EthDmaRxDscrTab, EthRxBuff, ETH_RX_BUF_NUM);
/* Enable ETH interrupt */
NVIC_EnableIRQ(hc32_eth_device.irq_config.irq_num);
/* Enable MAC and DMA transmission and reception */
if (LL_OK == ETH_Start())
{
LOG_D("eth hardware start");
}
else
{
LOG_E("eth hardware start faild");
return -RT_ERROR;
}
/* Configure PHY LED mode */
u16RegVal = PHY_PAGE_ADDR_7;
(void)ETH_PHY_WriteReg(&EthHandle, PHY_PSR, u16RegVal);
(void)ETH_PHY_ReadReg(&EthHandle, PHY_P7_IWLFR, &u16RegVal);
MODIFY_REG16(u16RegVal, PHY_LED_SELECT, PHY_LED_SELECT_10);
(void)ETH_PHY_WriteReg(&EthHandle, PHY_P7_IWLFR, u16RegVal);
u16RegVal = PHY_PAGE_ADDR_0;
(void)ETH_PHY_WriteReg(&EthHandle, PHY_PSR, u16RegVal);
#ifdef ETH_USING_INTERFACE_RMII
/* Disable Power Saving Mode */
(void)ETH_PHY_ReadReg(&EthHandle, PHY_PSMR, &u16RegVal);
CLR_REG16_BIT(u16RegVal, PHY_EN_PWR_SAVE);
(void)ETH_PHY_WriteReg(&EthHandle, PHY_PSMR, u16RegVal);
#endif
return RT_EOK;
}
static rt_err_t rt_hc32_eth_open(rt_device_t dev, rt_uint16_t oflag)
{
LOG_D("eth open");
return RT_EOK;
}
static rt_err_t rt_hc32_eth_close(rt_device_t dev)
{
LOG_D("eth close");
return RT_EOK;
}
static rt_size_t rt_hc32_eth_read(rt_device_t dev, rt_off_t pos, void *buffer, rt_size_t size)
{
LOG_D("eth read");
rt_set_errno(-RT_ENOSYS);
return 0;
}
static rt_size_t rt_hc32_eth_write(rt_device_t dev, rt_off_t pos, const void *buffer, rt_size_t size)
{
LOG_D("eth write");
rt_set_errno(-RT_ENOSYS);
return 0;
}
static rt_err_t rt_hc32_eth_control(rt_device_t dev, int cmd, void *args)
{
switch (cmd)
{
case NIOCTL_GADDR:
/* get mac address */
if (args)
{
SMEMCPY(args, hc32_eth_device.dev_addr, 6);
}
else
{
return -RT_ERROR;
}
break;
default :
break;
}
return RT_EOK;
}
/* ethernet device interface */
/* transmit data*/
rt_err_t rt_hc32_eth_tx(rt_device_t dev, struct pbuf *p)
{
rt_err_t errval = RT_ERROR;
struct pbuf *q;
uint8_t *txBuffer;
__IO stc_eth_dma_desc_t *DmaTxDesc;
uint32_t byteCnt;
uint32_t frameLength = 0UL;
uint32_t bufferOffset;
uint32_t payloadOffset;
DmaTxDesc = EthHandle.stcTxDesc;
txBuffer = (uint8_t *)((EthHandle.stcTxDesc)->u32Buf1Addr);
bufferOffset = 0UL;
/* Copy frame from pbufs to driver buffers */
for (q = p; q != NULL; q = q->next)
{
/* If this buffer isn't available, goto error */
if (0UL != (DmaTxDesc->u32ControlStatus & ETH_DMA_TXDESC_OWN))
{
LOG_D("buffer not valid");
errval = (err_t)ERR_USE;
goto error;
}
/* Get bytes in current lwIP buffer */
byteCnt = q->len;
payloadOffset = 0UL;
/* Check if the length of data to copy is bigger than Tx buffer size */
while ((byteCnt + bufferOffset) > ETH_TX_BUF_SIZE)
{
/* Copy data to Tx buffer*/
SMEMCPY((uint8_t *) & (txBuffer[bufferOffset]), (uint8_t *) & (((uint8_t *)q->payload)[payloadOffset]), (ETH_TX_BUF_SIZE - bufferOffset));
/* Point to next descriptor */
DmaTxDesc = (stc_eth_dma_desc_t *)(DmaTxDesc->u32Buf2NextDescAddr);
/* Check if the buffer is available */
if (0UL != (DmaTxDesc->u32ControlStatus & ETH_DMA_TXDESC_OWN))
{
errval = (err_t)ERR_USE;
goto error;
}
txBuffer = (uint8_t *)(DmaTxDesc->u32Buf1Addr);
byteCnt = byteCnt - (ETH_TX_BUF_SIZE - bufferOffset);
payloadOffset = payloadOffset + (ETH_TX_BUF_SIZE - bufferOffset);
frameLength = frameLength + (ETH_TX_BUF_SIZE - bufferOffset);
bufferOffset = 0UL;
}
/* Copy the remaining bytes */
SMEMCPY((uint8_t *) & (txBuffer[bufferOffset]), (uint8_t *) & (((uint8_t *)q->payload)[payloadOffset]), byteCnt);
bufferOffset = bufferOffset + byteCnt;
frameLength = frameLength + byteCnt;
}
LOG_D("transmit frame length :%d", framelength);
/* Prepare transmit descriptors to give to DMA */
(void)ETH_DMA_SetTransFrame(&EthHandle, frameLength);
errval = (err_t)ERR_OK;
error:
/* When Transmit Underflow flag is set, clear it and issue a Transmit Poll Demand to resume transmission */
if (RESET != ETH_DMA_GetStatus(ETH_DMA_FLAG_UNS))
{
/* Clear DMA UNS flag */
ETH_DMA_ClearStatus(ETH_DMA_FLAG_UNS);
/* Resume DMA transmission */
WRITE_REG32(CM_ETH->DMA_TXPOLLR, 0UL);
}
return errval;
}
/* receive data*/
struct pbuf *rt_hc32_eth_rx(rt_device_t dev)
{
struct pbuf *p = NULL;
struct pbuf *q;
uint32_t len;
uint8_t *rxBuffer;
__IO stc_eth_dma_desc_t *DmaRxDesc;
uint32_t byteCnt;
uint32_t bufferOffset;
uint32_t payloadOffset;
uint32_t i;
/* Get received frame */
if (LL_OK != ETH_DMA_GetReceiveFrame_Int(&EthHandle))
{
LOG_D("receive frame faild");
return NULL;
}
/* Obtain the size of the packet */
len = (EthHandle.stcRxFrame).u32Len;
rxBuffer = (uint8_t *)(EthHandle.stcRxFrame).u32Buf;
LOG_D("receive frame len : %d", len);
if (len > 0UL)
{
/* Allocate a pbuf chain of pbufs from the Lwip buffer pool */
p = pbuf_alloc(PBUF_RAW, (uint16_t)len, PBUF_POOL);
}
if (p != NULL)
{
DmaRxDesc = (EthHandle.stcRxFrame).pstcFSDesc;
bufferOffset = 0UL;
for (q = p; q != NULL; q = q->next)
{
byteCnt = q->len;
payloadOffset = 0UL;
/* Check if the length of bytes to copy in current pbuf is bigger than Rx buffer size */
while ((byteCnt + bufferOffset) > ETH_RX_BUF_SIZE)
{
/* Copy data to pbuf */
SMEMCPY((uint8_t *) & (((uint8_t *)q->payload)[payloadOffset]), (uint8_t *) & (rxBuffer[bufferOffset]), (ETH_RX_BUF_SIZE - bufferOffset));
/* Point to next descriptor */
DmaRxDesc = (stc_eth_dma_desc_t *)(DmaRxDesc->u32Buf2NextDescAddr);
rxBuffer = (uint8_t *)(DmaRxDesc->u32Buf1Addr);
byteCnt = byteCnt - (ETH_RX_BUF_SIZE - bufferOffset);
payloadOffset = payloadOffset + (ETH_RX_BUF_SIZE - bufferOffset);
bufferOffset = 0UL;
}
/* Copy remaining data in pbuf */
SMEMCPY((uint8_t *) & (((uint8_t *)q->payload)[payloadOffset]), (uint8_t *) & (rxBuffer[bufferOffset]), byteCnt);
bufferOffset = bufferOffset + byteCnt;
}
}
/* Release descriptors to DMA */
DmaRxDesc = (EthHandle.stcRxFrame).pstcFSDesc;
for (i = 0UL; i < (EthHandle.stcRxFrame).u32SegCount; i++)
{
DmaRxDesc->u32ControlStatus |= ETH_DMA_RXDESC_OWN;
DmaRxDesc = (stc_eth_dma_desc_t *)(DmaRxDesc->u32Buf2NextDescAddr);
}
/* Clear Segment_Count */
(EthHandle.stcRxFrame).u32SegCount = 0UL;
/* When Rx Buffer unavailable flag is set, clear it and resume reception */
if (RESET != ETH_DMA_GetStatus(ETH_DMA_FLAG_RUS))
{
/* Clear DMA RUS flag */
ETH_DMA_ClearStatus(ETH_DMA_FLAG_RUS);
/* Resume DMA reception */
WRITE_REG32(CM_ETH->DMA_RXPOLLR, 0UL);
}
return p;
}
static void hc32_eth_irq_handle(stc_eth_handle_t *eth_handle)
{
rt_err_t result;
(void)eth_handle;
/* Frame received */
if (RESET != ETH_DMA_GetStatus(ETH_DMA_FLAG_RIS))
{
result = eth_device_ready(&(hc32_eth_device.parent));
if (result != RT_EOK)
{
LOG_I("eth rx complete callback err = %d", result);
}
/* Clear the Eth DMA Rx IT pending bits */
ETH_DMA_ClearStatus(ETH_DMA_FLAG_RIS | ETH_DMA_FLAG_NIS);
}
}
/* interrupt service routine */
static void eth_global_irq_handle(void)
{
/* enter interrupt */
rt_interrupt_enter();
hc32_eth_irq_handle(&EthHandle);
/* leave interrupt */
rt_interrupt_leave();
}
static void hc32_phy_link_change(void)
{
static rt_uint8_t phy_status = 0;
rt_uint8_t phy_status_new = 0;
uint16_t u16RegVal = 0U;
uint16_t u16Page = 0U;
/* Switch page */
(void)ETH_PHY_ReadReg(&EthHandle, PHY_PSR, &u16Page);
if (u16Page != PHY_PAGE_ADDR_0)
{
u16RegVal = PHY_PAGE_ADDR_0;
(void)ETH_PHY_WriteReg(&EthHandle, PHY_PSR, u16RegVal);
}
/* Read PHY_BSR */
(void)ETH_PHY_ReadReg(&EthHandle, PHY_BASIC_STATUS_REG, &u16RegVal);
LOG_D("phy basic status reg is 0x%X", u16RegVal);
if ((0x0000U != u16RegVal) && (0xFFFFU != u16RegVal))
{
if (u16RegVal & (PHY_AUTONEGO_COMPLETE_MASK | PHY_LINKED_STATUS_MASK))
{
phy_status_new |= ETH_PHY_LINK;
if (0U != (u16RegVal & (PHY_100BASE_TX_FD | PHY_10BASE_T_FD)))
{
phy_status_new |= ETH_PHY_FULL_DUPLEX;
}
if (0U != (u16RegVal & (PHY_100BASE_TX_FD | PHY_100BASE_TX_HD)))
{
phy_status_new |= ETH_PHY_100M;
}
}
}
/* Restore page */
if (u16Page != PHY_PAGE_ADDR_0)
{
(void)ETH_PHY_WriteReg(&EthHandle, PHY_PSR, u16Page);
}
if (phy_status != phy_status_new)
{
phy_status = phy_status_new;
if (phy_status & ETH_PHY_LINK)
{
if (phy_status & ETH_PHY_FULL_DUPLEX)
{
hc32_eth_device.eth_mode = ETH_MAC_DUPLEX_MD_FULL;
}
else
{
hc32_eth_device.eth_mode = ETH_MAC_DUPLEX_MD_HALF;
}
if (phy_status & ETH_PHY_100M)
{
hc32_eth_device.eth_speed = ETH_MAC_SPEED_100M;
}
else
{
hc32_eth_device.eth_speed = ETH_MAC_SPEED_10M;
}
LOG_D("link up");
eth_device_linkchange(&hc32_eth_device.parent, RT_TRUE);
}
else
{
LOG_I("link down");
eth_device_linkchange(&hc32_eth_device.parent, RT_FALSE);
}
}
}
#if defined(PHY_USING_INTERRUPT_MODE) && defined(ETH_USING_INTERFACE_RMII)
static void eth_phy_irq_handler(void *args)
{
rt_uint16_t status = 0;
ETH_PHY_ReadReg(&EthHandle, PHY_IISDR, &status);
LOG_D("phy interrupt status reg is 0x%X", status);
hc32_phy_link_change();
}
#endif
static void hc32_phy_monitor_thread(void *parameter)
{
uint8_t phy_addr = 0xFF;
uint8_t detected_count = 0;
/* phy search */
while (phy_addr == 0xFF)
{
rt_uint16_t i, temp;
for (i = 0; i <= 0x1F; i++)
{
EthHandle.stcCommInit.u16PhyAddr = i;
ETH_PHY_ReadReg(&EthHandle, PHY_ID1_REG, &temp);
if (temp != 0xFFFF && temp != 0x00)
{
phy_addr = i;
break;
}
}
detected_count++;
rt_thread_mdelay(1000);
if (detected_count > 10)
{
LOG_E("No PHY device was detected!");
}
}
LOG_D("Found a phy, address:0x%02X", phy_addr);
/* Reset PHY */
ETH_PHY_WriteReg(&EthHandle, PHY_BASIC_CONTROL_REG, PHY_RESET_MASK);
rt_thread_mdelay(2000);
ETH_PHY_WriteReg(&EthHandle, PHY_BASIC_CONTROL_REG, PHY_AUTO_NEGOTIATION_MASK);
hc32_phy_link_change();
#if defined(PHY_USING_INTERRUPT_MODE) && defined(ETH_USING_INTERFACE_RMII)
/* configuration intterrupt pin */
rt_pin_mode(ETH_PHY_INT_PIN, PIN_MODE_INPUT_PULLUP);
rt_pin_attach_irq(ETH_PHY_INT_PIN, PIN_IRQ_MODE_FALLING, eth_phy_irq_handler, (void *)"callbackargs");
rt_pin_irq_enable(ETH_PHY_INT_PIN, PIN_IRQ_ENABLE);
uint16_t u16RegVal;
/* Configure PHY to generate an interrupt when Eth Link state changes */
u16RegVal = PHY_PAGE_ADDR_7;
(void)ETH_PHY_WriteReg(&EthHandle, PHY_PSR, u16RegVal);
/* Enable Interrupt on change of link status */
(void)ETH_PHY_ReadReg(&EthHandle, PHY_P7_IWLFR, &u16RegVal);
SET_REG16_BIT(u16RegVal, PHY_INT_LINK_CHANGE);
(void)ETH_PHY_WriteReg(&EthHandle, PHY_P7_IWLFR, u16RegVal);
u16RegVal = PHY_PAGE_ADDR_0;
(void)ETH_PHY_WriteReg(&EthHandle, PHY_PSR, u16RegVal);
#else
hc32_eth_device.poll_link_timer = rt_timer_create("eth_phy_link", (void (*)(void *))hc32_phy_link_change,
NULL, RT_TICK_PER_SECOND, RT_TIMER_FLAG_PERIODIC);
if (!hc32_eth_device.poll_link_timer || rt_timer_start(hc32_eth_device.poll_link_timer) != RT_EOK)
{
LOG_E("Start eth phy link change detection timer failed");
}
#endif
}
/* Register the eth device */
static int rt_hw_hc32_eth_init(void)
{
rt_err_t state = RT_EOK;
/* register eth handler */
hc32_install_irq_handler(&hc32_eth_device.irq_config, hc32_eth_device.irq_callback, RT_FALSE);
/* Prepare receive and send buffers */
EthRxBuff = (rt_uint8_t *)rt_calloc(ETH_RX_BUF_NUM, ETH_MAX_PACKET_SIZE);
if (EthRxBuff == RT_NULL)
{
LOG_E("No memory");
state = -RT_ENOMEM;
goto __exit;
}
EthTxBuff = (rt_uint8_t *)rt_calloc(ETH_TX_BUF_NUM, ETH_MAX_PACKET_SIZE);
if (EthTxBuff == RT_NULL)
{
LOG_E("No memory");
state = -RT_ENOMEM;
goto __exit;
}
EthDmaRxDscrTab = (stc_eth_dma_desc_t *)rt_calloc(ETH_RX_BUF_NUM, sizeof(stc_eth_dma_desc_t));
if (EthDmaRxDscrTab == RT_NULL)
{
LOG_E("No memory");
state = -RT_ENOMEM;
goto __exit;
}
EthDmaTxDscrTab = (stc_eth_dma_desc_t *)rt_calloc(ETH_TX_BUF_NUM, sizeof(stc_eth_dma_desc_t));
if (EthDmaTxDscrTab == RT_NULL)
{
LOG_E("No memory");
state = -RT_ENOMEM;
goto __exit;
}
hc32_eth_device.eth_speed = ETH_MAC_SPEED_100M;
hc32_eth_device.eth_mode = ETH_MAC_DUPLEX_MD_FULL;
/* 00-80 uid */
hc32_eth_device.dev_addr[0] = 0x02;
hc32_eth_device.dev_addr[1] = 0x80;
hc32_eth_device.dev_addr[2] = 0x00;
/* generate MAC addr from unique ID */
hc32_eth_device.dev_addr[3] = (rt_uint8_t)READ_REG32(CM_EFM->UQID0);
hc32_eth_device.dev_addr[4] = (rt_uint8_t)READ_REG32(CM_EFM->UQID1);
hc32_eth_device.dev_addr[5] = (rt_uint8_t)READ_REG32(CM_EFM->UQID2);
hc32_eth_device.parent.parent.init = rt_hc32_eth_init;
hc32_eth_device.parent.parent.open = rt_hc32_eth_open;
hc32_eth_device.parent.parent.close = rt_hc32_eth_close;
hc32_eth_device.parent.parent.read = rt_hc32_eth_read;
hc32_eth_device.parent.parent.write = rt_hc32_eth_write;
hc32_eth_device.parent.parent.control = rt_hc32_eth_control;
hc32_eth_device.parent.parent.user_data = RT_NULL;
hc32_eth_device.parent.eth_rx = rt_hc32_eth_rx;
hc32_eth_device.parent.eth_tx = rt_hc32_eth_tx;
/* register eth device */
state = eth_device_init(&(hc32_eth_device.parent), "e0");
if (RT_EOK == state)
{
LOG_D("eth device init success");
}
else
{
LOG_E("eth device init faild: %d", state);
state = -RT_ERROR;
goto __exit;
}
/* start phy monitor */
rt_thread_t tid;
tid = rt_thread_create("phy_monitor", hc32_phy_monitor_thread, RT_NULL, 1024, 12, 5);
if (tid != RT_NULL)
{
rt_thread_startup(tid);
}
else
{
state = -RT_ERROR;
}
__exit:
if (state != RT_EOK)
{
if (EthRxBuff)
{
rt_free(EthRxBuff);
}
if (EthTxBuff)
{
rt_free(EthTxBuff);
}
if (EthDmaRxDscrTab)
{
rt_free(EthDmaRxDscrTab);
}
if (EthDmaTxDscrTab)
{
rt_free(EthDmaTxDscrTab);
}
}
return state;
}
INIT_DEVICE_EXPORT(rt_hw_hc32_eth_init);
#endif

82
bsp/hc32/libraries/hc32_drivers/drv_eth.h Normal file
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@ -0,0 +1,82 @@
/*
* Copyright (C) 2022, Xiaohua Semiconductor Co., Ltd.
*
* SPDX-License-Identifier: Apache-2.0
*
* Change Logs:
* Date Author Notes
* 2022-04-28 CDT first version
*/
#ifndef __DRV_ETH_H__
#define __DRV_ETH_H__
/*******************************************************************************
* Include files
******************************************************************************/
#include <rtthread.h>
#include <rthw.h>
#include <rtdevice.h>
#ifdef __cplusplus
extern "C" {
#endif
/* The PHY basic control register */
#define PHY_BASIC_CONTROL_REG 0x00U
#define PHY_RESET_MASK (1<<15)
#define PHY_AUTO_NEGOTIATION_MASK (1<<12)
/* The PHY basic status register */
#define PHY_BASIC_STATUS_REG 0x01U
#define PHY_LINKED_STATUS_MASK (1<<2)
#define PHY_AUTONEGO_COMPLETE_MASK (1<<5)
/* The PHY ID one register */
#define PHY_ID1_REG 0x02U
#ifdef PHY_USING_RTL8201F
/* Extended PHY Registers */
#define PHY_PSMR (0x18U) /*!< Power Saving Mode Register */
#define PHY_IISDR (0x1EU) /*!< Interrupt Indicators and SNR Display Register */
#define PHY_PSR (0x1FU) /*!< Page Select Register */
#define PHY_P7_RMSR (0x10U) /*!< RMII Mode Setting Register */
#define PHY_P7_IWLFR (0x13U) /*!< Interrupt, WOL Enable, and LED Function Registers */
/* The following parameters will return to default values after a software reset */
#define PHY_EN_PWR_SAVE (0x8000U) /*!< Enable Power Saving Mode */
#define PHY_FLAG_AUTO_NEGO_ERROR (0x8000U) /*!< Auto-Negotiation Error Interrupt Flag */
#define PHY_FLAG_SPEED_MODE_CHANGE (0x4000U) /*!< Speed Mode Change Interrupt Flag */
#define PHY_FLAG_DUPLEX_MODE_CHANGE (0x2000U) /*!< Duplex Mode Change Interrupt Flag */
#define PHY_FLAG_LINK_STATUS_CHANGE (0x0800U) /*!< Link Status Change Interrupt Flag */
#define PHY_PAGE_ADDR_0 (0x0000U) /*!< Page Address 0 (default) */
#define PHY_PAGE_ADDR_7 (0x0007U) /*!< Page Address 7 */
#define PHY_RMII_CLK_DIR (0x1000U) /*!< TXC direction in RMII Mode */
#define PHY_RMII_MODE (0x0008U) /*!< RMII Mode or MII Mode */
#define PHY_RMII_RXDV_CRSDV (0x0004U) /*!< CRS_DV or RXDV select */
#define PHY_INT_LINK_CHANGE (0x2000U) /*!< Link Change Interrupt Mask */
#define PHY_INT_DUPLEX_CHANGE (0x1000U) /*!< Duplex Change Interrupt Mask */
#define PHY_INT_AUTO_NEGO_ERROR (0x0800U) /*!< Auto-Negotiation Error Interrupt Mask */
#define PHY_LED_WOL_SELECT (0x0400U) /*!< LED and Wake-On-LAN Function Selection */
#define PHY_LED_SELECT (0x0030U) /*!< Traditional LED Function Selection. */
#define PHY_LED_SELECT_00 (0x0000U) /*!< LED0: ACT(all) LED1: LINK(100) */
#define PHY_LED_SELECT_01 (0x0010U) /*!< LED0: LINK(ALL)/ACT(all) LED1: LINK(100) */
#define PHY_LED_SELECT_10 (0x0020U) /*!< LED0: LINK(10)/ACT(all) LED1: LINK(100) */
#define PHY_LED_SELECT_11 (0x0030U) /*!< LED0: LINK(10)/ACT(10) LED1: LINK(100)/ACT(100) */
#define PHY_EN_10M_LED_FUNC (0x0001U) /*!< Enable 10M LPI LED Function */
#endif
#ifdef __cplusplus
}
#endif
#endif /* __DRV_ETH_H__ */

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/*
* Copyright (C) 2022, Xiaohua Semiconductor Co., Ltd.
*
* SPDX-License-Identifier: Apache-2.0
*
* Change Logs:
* Date Author Notes
* 2022-04-28 CDT first version
*/
#include <rtthread.h>
#include <rthw.h>
#include "drv_gpio.h"
#include "board_config.h"
#ifdef RT_USING_PIN
#define GPIO_PIN_INDEX(pin) ((uint8_t)((pin) & 0x0F))
#define PIN_NUM(port, pin) (((((port) & 0x0F) << 4) | ((pin) & 0x0F)))
#define GPIO_PORT(pin) ((uint8_t)(((pin) >> 4) & 0x0F))
#define GPIO_PIN(pin) ((uint16_t)(0x01U << GPIO_PIN_INDEX(pin)))
#if defined (HC32F4A0)
#define PIN_MAX_NUM ((GPIO_PORT_I * 16) + (__CLZ(__RBIT(GPIO_PIN_13))) + 1)
#endif
#define ITEM_NUM(items) sizeof(items) / sizeof(items[0])
#ifndef HC32_PIN_CONFIG
#define HC32_PIN_CONFIG(pin, callback, config) \
{ \
.pinbit = pin, \
.irq_callback = callback, \
.irq_config = config, \
}
#endif /* HC32_PIN_CONFIG */
static void extint0_irq_handler(void);
static void extint1_irq_handler(void);
static void extint2_irq_handler(void);
static void extint3_irq_handler(void);
static void extint4_irq_handler(void);
static void extint5_irq_handler(void);
static void extint6_irq_handler(void);
static void extint7_irq_handler(void);
static void extint8_irq_handler(void);
static void extint9_irq_handler(void);
static void extint10_irq_handler(void);
static void extint11_irq_handler(void);
static void extint12_irq_handler(void);
static void extint13_irq_handler(void);
static void extint14_irq_handler(void);
static void extint15_irq_handler(void);
static struct hc32_pin_irq_map pin_irq_map[] =
{
HC32_PIN_CONFIG(GPIO_PIN_00, extint0_irq_handler, EXTINT0_IRQ_CONFIG),
HC32_PIN_CONFIG(GPIO_PIN_01, extint1_irq_handler, EXTINT1_IRQ_CONFIG),
HC32_PIN_CONFIG(GPIO_PIN_02, extint2_irq_handler, EXTINT2_IRQ_CONFIG),
HC32_PIN_CONFIG(GPIO_PIN_03, extint3_irq_handler, EXTINT3_IRQ_CONFIG),
HC32_PIN_CONFIG(GPIO_PIN_04, extint4_irq_handler, EXTINT4_IRQ_CONFIG),
HC32_PIN_CONFIG(GPIO_PIN_05, extint5_irq_handler, EXTINT5_IRQ_CONFIG),
HC32_PIN_CONFIG(GPIO_PIN_06, extint6_irq_handler, EXTINT6_IRQ_CONFIG),
HC32_PIN_CONFIG(GPIO_PIN_07, extint7_irq_handler, EXTINT7_IRQ_CONFIG),
HC32_PIN_CONFIG(GPIO_PIN_08, extint8_irq_handler, EXTINT8_IRQ_CONFIG),
HC32_PIN_CONFIG(GPIO_PIN_09, extint9_irq_handler, EXTINT9_IRQ_CONFIG),
HC32_PIN_CONFIG(GPIO_PIN_10, extint10_irq_handler, EXTINT10_IRQ_CONFIG),
HC32_PIN_CONFIG(GPIO_PIN_11, extint11_irq_handler, EXTINT11_IRQ_CONFIG),
HC32_PIN_CONFIG(GPIO_PIN_12, extint12_irq_handler, EXTINT12_IRQ_CONFIG),
HC32_PIN_CONFIG(GPIO_PIN_13, extint13_irq_handler, EXTINT13_IRQ_CONFIG),
HC32_PIN_CONFIG(GPIO_PIN_14, extint14_irq_handler, EXTINT14_IRQ_CONFIG),
HC32_PIN_CONFIG(GPIO_PIN_15, extint15_irq_handler, EXTINT15_IRQ_CONFIG),
};
struct rt_pin_irq_hdr pin_irq_hdr_tab[] =
{
{-1, 0, RT_NULL, RT_NULL},
{-1, 0, RT_NULL, RT_NULL},
{-1, 0, RT_NULL, RT_NULL},
{-1, 0, RT_NULL, RT_NULL},
{-1, 0, RT_NULL, RT_NULL},
{-1, 0, RT_NULL, RT_NULL},
{-1, 0, RT_NULL, RT_NULL},
{-1, 0, RT_NULL, RT_NULL},
{-1, 0, RT_NULL, RT_NULL},
{-1, 0, RT_NULL, RT_NULL},
{-1, 0, RT_NULL, RT_NULL},
{-1, 0, RT_NULL, RT_NULL},
{-1, 0, RT_NULL, RT_NULL},
{-1, 0, RT_NULL, RT_NULL},
{-1, 0, RT_NULL, RT_NULL},
{-1, 0, RT_NULL, RT_NULL},
};
static void pin_irq_handler(rt_uint16_t pinbit)
{
rt_int32_t irqindex = -1;
if (SET == EXTINT_GetExtIntStatus(pinbit))
{
EXTINT_ClearExtIntStatus(pinbit);
irqindex = __CLZ(__RBIT(pinbit));
if (pin_irq_hdr_tab[irqindex].hdr)
{
pin_irq_hdr_tab[irqindex].hdr(pin_irq_hdr_tab[irqindex].args);
}
}
}
static void extint0_irq_handler(void)
{
rt_interrupt_enter();
pin_irq_handler(pin_irq_map[0].pinbit);
rt_interrupt_leave();
}
static void extint1_irq_handler(void)
{
rt_interrupt_enter();
pin_irq_handler(pin_irq_map[1].pinbit);
rt_interrupt_leave();
}
static void extint2_irq_handler(void)
{
rt_interrupt_enter();
pin_irq_handler(pin_irq_map[2].pinbit);
rt_interrupt_leave();
}
static void extint3_irq_handler(void)
{
rt_interrupt_enter();
pin_irq_handler(pin_irq_map[3].pinbit);
rt_interrupt_leave();
}
static void extint4_irq_handler(void)
{
rt_interrupt_enter();
pin_irq_handler(pin_irq_map[4].pinbit);
rt_interrupt_leave();
}
static void extint5_irq_handler(void)
{
rt_interrupt_enter();
pin_irq_handler(pin_irq_map[5].pinbit);
rt_interrupt_leave();
}
static void extint6_irq_handler(void)
{
rt_interrupt_enter();
pin_irq_handler(pin_irq_map[6].pinbit);
rt_interrupt_leave();
}
static void extint7_irq_handler(void)
{
rt_interrupt_enter();
pin_irq_handler(pin_irq_map[7].pinbit);
rt_interrupt_leave();
}
static void extint8_irq_handler(void)
{
rt_interrupt_enter();
pin_irq_handler(pin_irq_map[8].pinbit);
rt_interrupt_leave();
}
static void extint9_irq_handler(void)
{
rt_interrupt_enter();
pin_irq_handler(pin_irq_map[9].pinbit);
rt_interrupt_leave();
}
static void extint10_irq_handler(void)
{
rt_interrupt_enter();
pin_irq_handler(pin_irq_map[10].pinbit);
rt_interrupt_leave();
}
static void extint11_irq_handler(void)
{
rt_interrupt_enter();
pin_irq_handler(pin_irq_map[11].pinbit);
rt_interrupt_leave();
}
static void extint12_irq_handler(void)
{
rt_interrupt_enter();
pin_irq_handler(pin_irq_map[12].pinbit);
rt_interrupt_leave();
}
static void extint13_irq_handler(void)
{
rt_interrupt_enter();
pin_irq_handler(pin_irq_map[13].pinbit);
rt_interrupt_leave();
}
static void extint14_irq_handler(void)
{
rt_interrupt_enter();
pin_irq_handler(pin_irq_map[14].pinbit);
rt_interrupt_leave();
}
static void extint15_irq_handler(void)
{
rt_interrupt_enter();
pin_irq_handler(pin_irq_map[15].pinbit);
rt_interrupt_leave();
}
static void hc32_pin_mode(struct rt_device *device, rt_base_t pin, rt_base_t mode)
{
stc_gpio_init_t stcGpioInit;
if (pin >= PIN_MAX_NUM)
{
return;
}
GPIO_StructInit(&stcGpioInit);
switch (mode)
{
case PIN_MODE_OUTPUT:
stcGpioInit.u16PinDir = PIN_DIR_OUT;
stcGpioInit.u16PinOutputType = PIN_OUT_TYPE_CMOS;
break;
case PIN_MODE_INPUT:
stcGpioInit.u16PinDir = PIN_DIR_IN;
break;
case PIN_MODE_INPUT_PULLUP:
stcGpioInit.u16PinDir = PIN_DIR_IN;
stcGpioInit.u16PullUp = PIN_PU_ON;
break;
case PIN_MODE_INPUT_PULLDOWN:
stcGpioInit.u16PinDir = PIN_DIR_IN;
stcGpioInit.u16PullUp = PIN_PU_OFF;
break;
case PIN_MODE_OUTPUT_OD:
stcGpioInit.u16PinDir = PIN_DIR_OUT;
stcGpioInit.u16PinOutputType = PIN_OUT_TYPE_NMOS;
break;
default:
break;
}
GPIO_Init(GPIO_PORT(pin), GPIO_PIN(pin), &stcGpioInit);
}
static void hc32_pin_write(struct rt_device *device, rt_base_t pin, rt_base_t value)
{
uint8_t gpio_port;
uint16_t gpio_pin;
if (pin < PIN_MAX_NUM)
{
gpio_port = GPIO_PORT(pin);
gpio_pin = GPIO_PIN(pin);
if (PIN_LOW == value)
{
GPIO_ResetPins(gpio_port, gpio_pin);
}
else
{
GPIO_SetPins(gpio_port, gpio_pin);
}
}
}
static int hc32_pin_read(struct rt_device *device, rt_base_t pin)
{
uint8_t gpio_port;
uint16_t gpio_pin;
int value = PIN_LOW;
if (pin < PIN_MAX_NUM)
{
gpio_port = GPIO_PORT(pin);
gpio_pin = GPIO_PIN(pin);
if (PIN_RESET == GPIO_ReadInputPins(gpio_port, gpio_pin))
{
value = PIN_LOW;
}
else
{
value = PIN_HIGH;
}
}
return value;
}
static rt_err_t hc32_pin_attach_irq(struct rt_device *device, rt_int32_t pin,
rt_uint32_t mode, void (*hdr)(void *args), void *args)
{
rt_base_t level;
rt_int32_t irqindex = -1;
if (pin >= PIN_MAX_NUM)
{
return -RT_ENOSYS;
}
irqindex = GPIO_PIN_INDEX(pin);
if (irqindex >= ITEM_NUM(pin_irq_map))
{
return RT_ENOSYS;
}
level = rt_hw_interrupt_disable();
if (pin_irq_hdr_tab[irqindex].pin == pin &&
pin_irq_hdr_tab[irqindex].hdr == hdr &&
pin_irq_hdr_tab[irqindex].mode == mode &&
pin_irq_hdr_tab[irqindex].args == args)
{
rt_hw_interrupt_enable(level);
return RT_EOK;
}
if (pin_irq_hdr_tab[irqindex].pin != -1)
{
rt_hw_interrupt_enable(level);
return RT_EBUSY;
}
pin_irq_hdr_tab[irqindex].pin = pin;
pin_irq_hdr_tab[irqindex].hdr = hdr;
pin_irq_hdr_tab[irqindex].mode = mode;
pin_irq_hdr_tab[irqindex].args = args;
rt_hw_interrupt_enable(level);
return RT_EOK;
}
static rt_err_t hc32_pin_detach_irq(struct rt_device *device, rt_int32_t pin)
{
rt_base_t level;
rt_int32_t irqindex = -1;
if (pin >= PIN_MAX_NUM)
{
return -RT_ENOSYS;
}
irqindex = GPIO_PIN_INDEX(pin);
if (irqindex >= ITEM_NUM(pin_irq_map))
{
return RT_ENOSYS;
}
level = rt_hw_interrupt_disable();
if (pin_irq_hdr_tab[irqindex].pin == -1)
{
rt_hw_interrupt_enable(level);
return RT_EOK;
}
pin_irq_hdr_tab[irqindex].pin = -1;
pin_irq_hdr_tab[irqindex].hdr = RT_NULL;
pin_irq_hdr_tab[irqindex].mode = 0;
pin_irq_hdr_tab[irqindex].args = RT_NULL;
rt_hw_interrupt_enable(level);
return RT_EOK;
}
static void gpio_irq_config(uint8_t u8Port, uint16_t u16Pin, uint16_t u16ExInt)
{
__IO uint16_t *PCRx;
uint16_t pin_num;
pin_num = __CLZ(__RBIT(u16Pin));
PCRx = (__IO uint16_t *)((uint32_t)(&CM_GPIO->PCRA0) + ((uint32_t)u8Port * 0x40UL) + (pin_num * 4UL));
MODIFY_REG16(*PCRx, GPIO_PCR_INTE, u16ExInt);
}
static rt_err_t hc32_pin_irq_enable(struct rt_device *device, rt_base_t pin, rt_uint32_t enabled)
{
struct hc32_pin_irq_map *irq_map;
rt_base_t level;
rt_int32_t irqindex = -1;
stc_extint_init_t stcExtIntInit;
uint8_t gpio_port;
uint16_t gpio_pin;
if ((pin >= PIN_MAX_NUM) || ((PIN_IRQ_ENABLE != enabled) && (PIN_IRQ_DISABLE != enabled)))
{
return -RT_ENOSYS;
}
irqindex = GPIO_PIN_INDEX(pin);
if (irqindex >= ITEM_NUM(pin_irq_map))
{
return RT_ENOSYS;
}
irq_map = &pin_irq_map[irqindex];
gpio_port = GPIO_PORT(pin);
gpio_pin = GPIO_PIN(pin);
if (enabled == PIN_IRQ_ENABLE)
{
level = rt_hw_interrupt_disable();
if (pin_irq_hdr_tab[irqindex].pin == -1)
{
rt_hw_interrupt_enable(level);
return RT_ENOSYS;
}
/* Exint config */
EXTINT_StructInit(&stcExtIntInit);
switch (pin_irq_hdr_tab[irqindex].mode)
{
case PIN_IRQ_MODE_RISING:
stcExtIntInit.u32Edge = EXTINT_TRIG_RISING;
break;
case PIN_IRQ_MODE_FALLING:
stcExtIntInit.u32Edge = EXTINT_TRIG_FALLING;
break;
case PIN_IRQ_MODE_RISING_FALLING:
stcExtIntInit.u32Edge = EXTINT_TRIG_BOTH;
break;
case PIN_IRQ_MODE_LOW_LEVEL:
stcExtIntInit.u32Edge = EXTINT_TRIG_LOW;
break;
}
EXTINT_Init(gpio_pin, &stcExtIntInit);
NVIC_EnableIRQ(irq_map->irq_config.irq_num);
gpio_irq_config(gpio_port, gpio_pin, PIN_EXTINT_ON);
}
else
{
level = rt_hw_interrupt_disable();
gpio_irq_config(gpio_port, gpio_pin, PIN_EXTINT_OFF);
NVIC_DisableIRQ(irq_map->irq_config.irq_num);
}
rt_hw_interrupt_enable(level);
return RT_EOK;
}
static rt_base_t hc32_pin_get(const char *name)
{
rt_base_t pin = 0;
int hw_port_num, hw_pin_num = 0;
int i, name_len;
name_len = rt_strlen(name);
if ((name_len < 4) || (name_len >= 6))
{
return -RT_EINVAL;
}
if ((name[0] != 'P') || (name[2] != '.'))
{
return -RT_EINVAL;
}
if ((name[1] >= 'A') && (name[1] <= 'Z'))
{
hw_port_num = (int)(name[1] - 'A');
}
else
{
return -RT_EINVAL;
}
for (i = 3; i < name_len; i++)
{
hw_pin_num *= 10;
hw_pin_num += name[i] - '0';
}
pin = PIN_NUM(hw_port_num, hw_pin_num);
return pin;
}
static const struct rt_pin_ops hc32_pin_ops =
{
hc32_pin_mode,
hc32_pin_write,
hc32_pin_read,
hc32_pin_attach_irq,
hc32_pin_detach_irq,
hc32_pin_irq_enable,
hc32_pin_get,
};
int rt_hw_pin_init(void)
{
uint8_t u32MaxExtInt;
/* register extint */
u32MaxExtInt = ITEM_NUM(pin_irq_map);
for (uint8_t i = 0; i < u32MaxExtInt; i++)
{
hc32_install_irq_handler(&pin_irq_map[i].irq_config, pin_irq_map[i].irq_callback, RT_FALSE);
}
return rt_device_pin_register("pin", &hc32_pin_ops, RT_NULL);
}
INIT_BOARD_EXPORT(rt_hw_pin_init);
#endif /* RT_USING_PIN */

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bsp/hc32/libraries/hc32_drivers/drv_gpio.h Normal file
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/*
* Copyright (C) 2022, Xiaohua Semiconductor Co., Ltd.
*
* SPDX-License-Identifier: Apache-2.0
*
* Change Logs:
* Date Author Notes
* 2022-04-28 CDT first version
*/
#ifndef __DRV_GPIO_H__
#define __DRV_GPIO_H__
#include <rtdevice.h>
#include "drv_irq.h"
#if defined(RT_USING_PIN)
#define __HC_PORT(port) GPIO_PORT_##port
#define GET_PIN(PORT, PIN) (rt_base_t)(((rt_uint16_t)__HC_PORT(PORT) * 16) + PIN)
struct hc32_pin_irq_map
{
rt_uint16_t pinbit;
func_ptr_t irq_callback;
struct hc32_irq_config irq_config;
};
#endif
#endif /* __DRV_GPIO_H__ */

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bsp/hc32/libraries/hc32_drivers/drv_hwtimer.c Normal file
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/*
* Copyright (C) 2022, Xiaohua Semiconductor Co., Ltd.
*
* SPDX-License-Identifier: Apache-2.0
*
* Change Logs:
* Date Author Notes
* 2022-04-28 CDT first version
*/
#include <rtdevice.h>
#include <rtdbg.h>
#if defined(RT_USING_HWTIMER)
#if defined(BSP_USING_TIMER1) || defined(BSP_USING_TIMER2) || defined(BSP_USING_TIMER3) || \
defined(BSP_USING_TIMER4) || defined(BSP_USING_TIMER5) || defined(BSP_USING_TIMER6) || \
defined(BSP_USING_TIMER7) || defined(BSP_USING_TIMER8) || defined(BSP_USING_TIMER9) || \
defined(BSP_USING_TIMER10) || defined(BSP_USING_TIMER11) || defined(BSP_USING_TIMER12)
#include "drv_hwtimer.h"
#include "drv_irq.h"
enum
{
#ifdef BSP_USING_TIMER1
TIMER1_INDEX,
#endif
#ifdef BSP_USING_TIMER2
TIMER2_INDEX,
#endif
#ifdef BSP_USING_TIMER3
TIMER3_INDEX,
#endif
#ifdef BSP_USING_TIMER4
TIMER4_INDEX,
#endif
#ifdef BSP_USING_TIMER5
TIMER5_INDEX,
#endif
#ifdef BSP_USING_TIMER6
TIMER6_INDEX,
#endif
#ifdef BSP_USING_TIMER7
TIMER7_INDEX,
#endif
#ifdef BSP_USING_TIMER8
TIMER8_INDEX,
#endif
#ifdef BSP_USING_TIMER9
TIMER9_INDEX,
#endif
#ifdef BSP_USING_TIMER10
TIMER10_INDEX,
#endif
#ifdef BSP_USING_TIMER11
TIMER11_INDEX,
#endif
#ifdef BSP_USING_TIMER12
TIMER12_INDEX,
#endif
};
#ifdef BSP_USING_TIMER1
static void timer1_irq_handler(void);
#endif
#ifdef BSP_USING_TIMER2
static void timer2_irq_handler(void);
#endif
#ifdef BSP_USING_TIMER3
static void timer3_irq_handler(void);
#endif
#ifdef BSP_USING_TIMER4
static void timer4_irq_handler(void);
#endif
#ifdef BSP_USING_TIMER5
static void timer5_irq_handler(void);
#endif
#ifdef BSP_USING_TIMER6
static void timer6_irq_handler(void);
#endif
#ifdef BSP_USING_TIMER7
static void timer7_irq_handler(void);
#endif
#ifdef BSP_USING_TIMER8
static void timer8_irq_handler(void);
#endif
#ifdef BSP_USING_TIMER9
static void timer9_irq_handler(void);
#endif
#ifdef BSP_USING_TIMER10
static void timer10_irq_handler(void);
#endif
#ifdef BSP_USING_TIMER11
static void timer11_irq_handler(void);
#endif
#ifdef BSP_USING_TIMER12
static void timer12_irq_handler(void);
#endif
struct hc32_hwtimer_config
{
rt_hwtimer_t time_device;
CM_TMRA_TypeDef *timer_periph;
struct hc32_irq_config irq_config;
func_ptr_t irq_callback;
uint32_t extend_div;
uint32_t extend_cnt;
char *name;
};
#ifndef HC32_TIMER_CONFIG
#define HC32_TIMER_CONFIG(periph, irq, label, src, irq_info) \
{ \
.timer_periph = periph, \
.irq_callback = irq, \
.name = label, \
.irq_config = irq_info, \
.irq_config.int_src = src, \
}
#endif /* HC32_TIMER_CONFIG */
static struct hc32_hwtimer_config hwtimer_obj[] =
{
#ifdef BSP_USING_TIMER1
HC32_TIMER_CONFIG(CM_TMRA_1, timer1_irq_handler, "timer1", INT_SRC_TMRA_1_OVF, TIMER1_IRQ_CONFIG),
#endif
#ifdef BSP_USING_TIMER2
HC32_TIMER_CONFIG(CM_TMRA_2, timer2_irq_handler, "timer2", INT_SRC_TMRA_2_OVF, TIMER2_IRQ_CONFIG),
#endif
#ifdef BSP_USING_TIMER3
HC32_TIMER_CONFIG(CM_TMRA_3, timer3_irq_handler, "timer3", INT_SRC_TMRA_3_OVF, TIMER3_IRQ_CONFIG),
#endif
#ifdef BSP_USING_TIMER4
HC32_TIMER_CONFIG(CM_TMRA_4, timer4_irq_handler, "timer4", INT_SRC_TMRA_4_OVF, TIMER4_IRQ_CONFIG),
#endif
#ifdef BSP_USING_TIMER5
HC32_TIMER_CONFIG(CM_TMRA_5, timer5_irq_handler, "timer5", INT_SRC_TMRA_5_OVF, TIMER5_IRQ_CONFIG),
#endif
#ifdef BSP_USING_TIMER6
HC32_TIMER_CONFIG(CM_TMRA_6, timer6_irq_handler, "timer6", INT_SRC_TMRA_6_OVF, TIMER6_IRQ_CONFIG),
#endif
#ifdef BSP_USING_TIMER7
HC32_TIMER_CONFIG(CM_TMRA_7, timer7_irq_handler, "timer7", INT_SRC_TMRA_7_OVF, TIMER7_IRQ_CONFIG),
#endif
#ifdef BSP_USING_TIMER8
HC32_TIMER_CONFIG(CM_TMRA_8, timer8_irq_handler, "timer8", INT_SRC_TMRA_8_OVF, TIMER8_IRQ_CONFIG),
#endif
#ifdef BSP_USING_TIMER9
HC32_TIMER_CONFIG(CM_TMRA_9, timer9_irq_handler, "timer9", INT_SRC_TMRA_9_OVF, TIMER9_IRQ_CONFIG),
#endif
#ifdef BSP_USING_TIMER10
HC32_TIMER_CONFIG(CM_TMRA_10, timer10_irq_handler, "timer10", INT_SRC_TMRA_10_OVF, TIMER10_IRQ_CONFIG),
#endif
#ifdef BSP_USING_TIMER11
HC32_TIMER_CONFIG(CM_TMRA_11, timer11_irq_handler, "timer11", INT_SRC_TMRA_11_OVF, TIMER11_IRQ_CONFIG),
#endif
#ifdef BSP_USING_TIMER12
HC32_TIMER_CONFIG(CM_TMRA_12, timer12_irq_handler, "timer12", INT_SRC_TMRA_12_OVF, TIMER12_IRQ_CONFIG),
#endif
};
static void hc32_timer_irq_handler(struct hc32_hwtimer_config *timer_config)
{
if ((++timer_config->extend_cnt) >= timer_config->extend_div)
{
timer_config->extend_cnt = 0;
rt_device_hwtimer_isr(&timer_config->time_device);
}
TMRA_ClearStatus(timer_config->timer_periph, (TMRA_FLAG_OVF | TMRA_FLAG_UDF));
}
#ifdef BSP_USING_TIMER1
static void timer1_irq_handler(void)
{
/* enter interrupt */
rt_interrupt_enter();
hc32_timer_irq_handler(&hwtimer_obj[TIMER1_INDEX]);
/* leave interrupt */
rt_interrupt_leave();
}
#endif
#ifdef BSP_USING_TIMER2
static void timer2_irq_handler(void)
{
/* enter interrupt */
rt_interrupt_enter();
hc32_timer_irq_handler(&hwtimer_obj[TIMER2_INDEX]);
/* leave interrupt */
rt_interrupt_leave();
}
#endif
#ifdef BSP_USING_TIMER3
static void timer3_irq_handler(void)
{
/* enter interrupt */
rt_interrupt_enter();
hc32_timer_irq_handler(&hwtimer_obj[TIMER3_INDEX]);
/* leave interrupt */
rt_interrupt_leave();
}
#endif
#ifdef BSP_USING_TIMER4
static void timer4_irq_handler(void)
{
/* enter interrupt */
rt_interrupt_enter();
hc32_timer_irq_handler(&hwtimer_obj[TIMER4_INDEX]);
/* leave interrupt */
rt_interrupt_leave();
}
#endif
#ifdef BSP_USING_TIMER5
static void timer5_irq_handler(void)
{
/* enter interrupt */
rt_interrupt_enter();
hc32_timer_irq_handler(&hwtimer_obj[TIMER5_INDEX]);
/* leave interrupt */
rt_interrupt_leave();
}
#endif
#ifdef BSP_USING_TIMER6
static void timer6_irq_handler(void)
{
/* enter interrupt */
rt_interrupt_enter();
hc32_timer_irq_handler(&hwtimer_obj[TIMER6_INDEX]);
/* leave interrupt */
rt_interrupt_leave();
}
#endif
#ifdef BSP_USING_TIMER7
static void timer7_irq_handler(void)
{
/* enter interrupt */
rt_interrupt_enter();
hc32_timer_irq_handler(&hwtimer_obj[TIMER7_INDEX]);
/* leave interrupt */
rt_interrupt_leave();
}
#endif
#ifdef BSP_USING_TIMER8
static void timer8_irq_handler(void)
{
/* enter interrupt */
rt_interrupt_enter();
hc32_timer_irq_handler(&hwtimer_obj[TIMER8_INDEX]);
/* leave interrupt */
rt_interrupt_leave();
}
#endif
#ifdef BSP_USING_TIMER9
static void timer9_irq_handler(void)
{
/* enter interrupt */
rt_interrupt_enter();
hc32_timer_irq_handler(&hwtimer_obj[TIMER9_INDEX]);
/* leave interrupt */
rt_interrupt_leave();
}
#endif
#ifdef BSP_USING_TIMER10
static void timer10_irq_handler(void)
{
/* enter interrupt */
rt_interrupt_enter();
hc32_timer_irq_handler(&hwtimer_obj[TIMER10_INDEX]);
/* leave interrupt */
rt_interrupt_leave();
}
#endif
#ifdef BSP_USING_TIMER11
static void timer11_irq_handler(void)
{
/* enter interrupt */
rt_interrupt_enter();
hc32_timer_irq_handler(&hwtimer_obj[TIMER11_INDEX]);
/* leave interrupt */
rt_interrupt_leave();
}
#endif
#ifdef BSP_USING_TIMER12
static void timer12_irq_handler(void)
{
/* enter interrupt */
rt_interrupt_enter();
hc32_timer_irq_handler(&hwtimer_obj[TIMER12_INDEX]);
/* leave interrupt */
rt_interrupt_leave();
}
#endif
static rt_uint16_t hc32_timer_get_unit_number(CM_TMRA_TypeDef *TMRAx)
{
rt_uint16_t unit_num;
const rt_uint32_t unit_step = 0x400U;
if (((rt_uint32_t)TMRAx) >= ((rt_uint32_t)CM_TMRA_1))
{
unit_num = (((rt_uint32_t)TMRAx) - ((rt_uint32_t)CM_TMRA_1)) / unit_step;
}
else
{
unit_num = (((rt_uint32_t)TMRAx) - ((rt_uint32_t)CM_TMRA_5)) / unit_step + 4;
}
return unit_num;
}
static void hc32_timer_clock_config(CM_TMRA_TypeDef *TMRAx, en_functional_state_t enNewState)
{
rt_uint32_t timer_periph;
rt_uint16_t unit_num;
unit_num = hc32_timer_get_unit_number(TMRAx);
timer_periph = PWC_FCG2_TMRA_1 << unit_num;
FCG_Fcg2PeriphClockCmd(timer_periph, enNewState);
}
static void hc32_timer_get_div_value(CM_TMRA_TypeDef *TMRAx, uint32_t freq, uint16_t *div, uint32_t *extend_div)
{
stc_clock_freq_t stcClkFreq;
rt_uint32_t divisor, remainder;
rt_uint16_t div_val;
rt_uint32_t clk_freq;
rt_uint16_t unit_num;
CLK_GetClockFreq(&stcClkFreq);
unit_num = hc32_timer_get_unit_number(TMRAx);
if (unit_num >= 4)
{
clk_freq = stcClkFreq.u32Pclk1Freq;
}
else
{
clk_freq = stcClkFreq.u32Pclk0Freq;
}
divisor = clk_freq / freq;
remainder = clk_freq % freq;
for (div_val = 1; div_val <= 1024; div_val <<= 1)
{
if (((divisor % 2) == 0) && (remainder == 0))
{
remainder = divisor % 2;
divisor = divisor / 2;
}
else
{
break;
}
}
*extend_div = divisor;
*div = (__CLZ(__RBIT(div_val))) << TMRA_BCSTR_CKDIV_POS;
}
static void hc32_timer_interrupt_config(struct rt_hwtimer_device *timer, en_functional_state_t enNewState)
{
struct hc32_hwtimer_config *timer_config = RT_NULL;
timer_config = (struct hc32_hwtimer_config *)timer;
if (INT_SRC_MAX == timer_config->irq_config.int_src)
{
LOG_D("%s interrupt init failed", timer_config->name);
return;
}
if (ENABLE == enNewState)
{
/* Enable the specified interrupts of Timer */
hc32_install_irq_handler(&timer_config->irq_config, timer_config->irq_callback, RT_FALSE);
NVIC_EnableIRQ(timer_config->irq_config.irq_num);
TMRA_IntCmd(timer_config->timer_periph, TMRA_INT_OVF, ENABLE);
}
else
{
/* Disable the specified interrupts of Timer */
TMRA_IntCmd(timer_config->timer_periph, TMRA_INT_OVF, DISABLE);
NVIC_DisableIRQ(timer_config->irq_config.irq_num);
}
}
static void hc32_timer_init(struct rt_hwtimer_device *timer, rt_uint32_t state)
{
stc_tmra_init_t stcTmraInit;
struct hc32_hwtimer_config *timer_config = RT_NULL;
RT_ASSERT(timer != RT_NULL);
timer_config = (struct hc32_hwtimer_config *)timer;
if (state)
{
/* Enable Timer peripheral clock. */
hc32_timer_clock_config(timer_config->timer_periph, ENABLE);
TMRA_DeInit(timer_config->timer_periph);
TMRA_StructInit(&stcTmraInit);
stcTmraInit.sw_count.u16CountDir = TMRA_DIR_UP;
TMRA_Init(timer_config->timer_periph, &stcTmraInit);
LOG_D("%s init success", timer_config->name);
}
else
{
TMRA_DeInit(timer_config->timer_periph);
hc32_timer_interrupt_config(timer, DISABLE);
/* Disable Timer peripheral clock. */
hc32_timer_clock_config(timer_config->timer_periph, DISABLE);
}
}
static rt_err_t hc32_timer_start(struct rt_hwtimer_device *timer, rt_uint32_t cnt, rt_hwtimer_mode_t mode)
{
rt_err_t result = RT_EOK;
struct hc32_hwtimer_config *timer_config = RT_NULL;
RT_ASSERT(timer != RT_NULL);
timer_config = (struct hc32_hwtimer_config *)timer;
if (mode == HWTIMER_MODE_ONESHOT)
{
TMRA_CountReloadCmd(timer_config->timer_periph, DISABLE);
}
else
{
TMRA_CountReloadCmd(timer_config->timer_periph, ENABLE);
}
timer_config->extend_cnt = 0;
TMRA_SetCountValue(timer_config->timer_periph, 0);
TMRA_SetPeriodValue(timer_config->timer_periph, cnt - 1);
hc32_timer_interrupt_config(timer, ENABLE);
TMRA_Start(timer_config->timer_periph);
return result;
}
static void hc32_timer_stop(struct rt_hwtimer_device *timer)
{
struct hc32_hwtimer_config *timer_config = RT_NULL;
RT_ASSERT(timer != RT_NULL);
timer_config = (struct hc32_hwtimer_config *)timer;
/* stop timer */
TMRA_Stop(timer_config->timer_periph);
hc32_timer_interrupt_config(timer, DISABLE);
TMRA_SetCountValue(timer_config->timer_periph, 0);
}
static rt_uint32_t hc32_timer_get_counter(struct rt_hwtimer_device *timer)
{
rt_uint32_t count_val;
rt_uint32_t period_val;
float temp;
struct hc32_hwtimer_config *timer_config = RT_NULL;
RT_ASSERT(timer != RT_NULL);
timer_config = (struct hc32_hwtimer_config *)timer;
period_val = TMRA_GetPeriodValue(timer_config->timer_periph);
count_val = TMRA_GetCountValue(timer_config->timer_periph);
temp = (timer_config->extend_cnt * period_val + count_val);
temp = temp / (timer_config->extend_div * period_val) * period_val;
count_val = (rt_uint32_t)temp;
return count_val;
}
static rt_err_t hc32_timer_ctrl(struct rt_hwtimer_device *timer, rt_uint32_t cmd, void *args)
{
struct hc32_hwtimer_config *timer_config = RT_NULL;
rt_err_t result = RT_EOK;
RT_ASSERT(timer != RT_NULL);
RT_ASSERT(args != RT_NULL);
timer_config = (struct hc32_hwtimer_config *)timer;
switch (cmd)
{
case HWTIMER_CTRL_FREQ_SET:
{
rt_uint32_t freq;
rt_uint16_t div_val;
rt_uint32_t extend_div_val;
/* set timer frequency */
freq = *((rt_uint32_t *)args);
hc32_timer_get_div_value(timer_config->timer_periph, freq, &div_val, &extend_div_val);
TMRA_SetClockDiv(timer_config->timer_periph, div_val);
timer_config->extend_div = extend_div_val;
}
break;
default:
{
result = -RT_ENOSYS;
}
break;
}
return result;
}
static const struct rt_hwtimer_ops hwtimer_ops =
{
.init = hc32_timer_init,
.start = hc32_timer_start,
.stop = hc32_timer_stop,
.count_get = hc32_timer_get_counter,
.control = hc32_timer_ctrl,
};
static const struct rt_hwtimer_info hwtimer_info =
{
.maxfreq = 30000000,
.minfreq = 1000,
.maxcnt = 0xFFFF,
.cntmode = HWTIMER_CNTMODE_UP,
};
static int rt_hwtimer_init(void)
{
int i = 0;
int result = RT_EOK;
for (i = 0; i < sizeof(hwtimer_obj) / sizeof(hwtimer_obj[0]); i++)
{
hwtimer_obj[i].time_device.info = &hwtimer_info;
hwtimer_obj[i].time_device.ops = &hwtimer_ops;
if (rt_device_hwtimer_register(&hwtimer_obj[i].time_device, hwtimer_obj[i].name, hwtimer_obj[i].timer_periph) == RT_EOK)
{
LOG_D("%s register success", hwtimer_obj[i].name);
}
else
{
LOG_E("%s register failed", hwtimer_obj[i].name);
result = -RT_ERROR;
}
}
return result;
}
INIT_BOARD_EXPORT(rt_hwtimer_init);
#endif
#endif /* RT_USING_HWTIMER */

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/*
* Copyright (C) 2022, Xiaohua Semiconductor Co., Ltd.
*
* SPDX-License-Identifier: Apache-2.0
*
* Change Logs:
* Date Author Notes
* 2022-04-28 CDT first version
*/
#ifndef __DRV_HWTIMER_H__
#define __DRV_HWTIMER_H__
#include <rtthread.h>
#include "board_config.h"
#ifdef __cplusplus
extern "C" {
#endif
#ifdef BSP_USING_TIMER1
#ifndef TIMER1_IRQ_CONFIG
#define TIMER1_IRQ_CONFIG \
{ \
.irq_num = TIMER1_CNT_INT_IRQn, \
.irq_prio = TIMER1_CNT_INT_PRIO, \
}
#endif /* TIMER1_IRQ_CONFIG */
#endif /* BSP_USING_TIMER1 */
#ifdef BSP_USING_TIMER2
#ifndef TIMER2_IRQ_CONFIG
#define TIMER2_IRQ_CONFIG \
{ \
.irq_num = TIMER2_CNT_INT_IRQn, \
.irq_prio = TIMER2_CNT_INT_PRIO, \
}
#endif /* TIMER2_IRQ_CONFIG */
#endif /* BSP_USING_TIMER2 */
#ifdef BSP_USING_TIMER3
#ifndef TIMER3_IRQ_CONFIG
#define TIMER3_IRQ_CONFIG \
{ \
.irq_num = TIMER3_CNT_INT_IRQn, \
.irq_prio = TIMER3_CNT_INT_PRIO, \
}
#endif /* TIMER3_IRQ_CONFIG */
#endif /* BSP_USING_TIMER3 */
#ifdef BSP_USING_TIMER4
#ifndef TIMER4_IRQ_CONFIG
#define TIMER4_IRQ_CONFIG \
{ \
.irq_num = TIMER4_CNT_INT_IRQn, \
.irq_prio = TIMER4_CNT_INT_PRIO, \
}
#endif /* TIMER4_IRQ_CONFIG */
#endif /* BSP_USING_TIMER4 */
#ifdef BSP_USING_TIMER5
#ifndef TIMER5_IRQ_CONFIG
#define TIMER5_IRQ_CONFIG \
{ \
.irq_num = TIMER5_CNT_INT_IRQn, \
.irq_prio = TIMER5_CNT_INT_PRIO, \
}
#endif /* TIMER5_IRQ_CONFIG */
#endif /* BSP_USING_TIMER5 */
#ifdef BSP_USING_TIMER6
#ifndef TIMER6_IRQ_CONFIG
#define TIMER6_IRQ_CONFIG \
{ \
.irq_num = TIMER6_CNT_INT_IRQn, \
.irq_prio = TIMER6_CNT_INT_PRIO, \
}
#endif /* TIMER6_IRQ_CONFIG */
#endif /* BSP_USING_TIMER6 */
#ifdef BSP_USING_TIMER7
#ifndef TIMER7_IRQ_CONFIG
#define TIMER7_IRQ_CONFIG \
{ \
.irq_num = TIMER7_CNT_INT_IRQn, \
.irq_prio = TIMER7_CNT_INT_PRIO, \
}
#endif /* TIMER7_IRQ_CONFIG */
#endif /* BSP_USING_TIMER7 */
#ifdef BSP_USING_TIMER8
#ifndef TIMER8_IRQ_CONFIG
#define TIMER8_IRQ_CONFIG \
{ \
.irq_num = TIMER8_CNT_INT_IRQn, \
.irq_prio = TIMER8_CNT_INT_PRIO, \
}
#endif /* TIMER8_IRQ_CONFIG */
#endif /* BSP_USING_TIMER8 */
#ifdef BSP_USING_TIMER9
#ifndef TIMER9_IRQ_CONFIG
#define TIMER9_IRQ_CONFIG \
{ \
.irq_num = TIMER9_CNT_INT_IRQn, \
.irq_prio = TIMER9_CNT_INT_PRIO, \
}
#endif /* TIMER9_IRQ_CONFIG */
#endif /* BSP_USING_TIMER9 */
#ifdef BSP_USING_TIMER10
#ifndef TIMER10_IRQ_CONFIG
#define TIMER10_IRQ_CONFIG \
{ \
.irq_num = TIMER10_CNT_INT_IRQn, \
.irq_prio = TIMER10_CNT_INT_PRIO, \
}
#endif /* TIMER10_IRQ_CONFIG */
#endif /* BSP_USING_TIMER10 */
#ifdef BSP_USING_TIMER11
#ifndef TIMER11_IRQ_CONFIG
#define TIMER11_IRQ_CONFIG \
{ \
.irq_num = TIMER11_CNT_INT_IRQn, \
.irq_prio = TIMER11_CNT_INT_PRIO, \
}
#endif /* TIMER11_IRQ_CONFIG */
#endif /* BSP_USING_TIMER11 */
#ifdef BSP_USING_TIMER12
#ifndef TIMER12_IRQ_CONFIG
#define TIMER12_IRQ_CONFIG \
{ \
.irq_num = TIMER12_CNT_INT_IRQn, \
.irq_prio = TIMER12_CNT_INT_PRIO, \
}
#endif /* TIMER12_IRQ_CONFIG */
#endif /* BSP_USING_TIMER12 */
#ifdef __cplusplus
}
#endif
#endif /* __DRV_HWTIMER_H__ */

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/*
* Copyright (C) 2022, Xiaohua Semiconductor Co., Ltd.
*
* SPDX-License-Identifier: Apache-2.0
*
* Change Logs:
* Date Author Notes
* 2022-04-28 CDT first version
*/
/*******************************************************************************
* Include files
******************************************************************************/
#include <rtthread.h>
#include "drv_irq.h"
/*******************************************************************************
* Local type definitions ('typedef')
******************************************************************************/
/*******************************************************************************
* Local pre-processor symbols/macros ('#define')
******************************************************************************/
/*******************************************************************************
* Global variable definitions (declared in header file with 'extern')
******************************************************************************/
/*******************************************************************************
* Local function prototypes ('static')
******************************************************************************/
/*******************************************************************************
* Local variable definitions ('static')
******************************************************************************/
/*******************************************************************************
* Function implementation - global ('extern') and local ('static')
******************************************************************************/
rt_err_t hc32_install_irq_handler(struct hc32_irq_config *irq_config,
void (*irq_hdr)(void),
rt_bool_t irq_enable)
{
rt_err_t result = -RT_ERROR;
stc_irq_signin_config_t stcIrqSignConfig;
RT_ASSERT(RT_NULL != irq_config);
RT_ASSERT(RT_NULL != irq_hdr);
stcIrqSignConfig.enIRQn = irq_config->irq_num;
stcIrqSignConfig.enIntSrc = irq_config->int_src;
stcIrqSignConfig.pfnCallback = irq_hdr;
if (LL_OK == INTC_IrqSignIn(&stcIrqSignConfig))
{
NVIC_ClearPendingIRQ(stcIrqSignConfig.enIRQn);
NVIC_SetPriority(stcIrqSignConfig.enIRQn, irq_config->irq_prio);
if (RT_TRUE == irq_enable)
{
NVIC_EnableIRQ(stcIrqSignConfig.enIRQn);
}
else
{
NVIC_DisableIRQ(stcIrqSignConfig.enIRQn);
}
result = RT_EOK;
}
return result;
}
/*******************************************************************************
* EOF (not truncated)
******************************************************************************/

59
bsp/hc32/libraries/hc32_drivers/drv_irq.h Normal file
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/*
* Copyright (C) 2022, Xiaohua Semiconductor Co., Ltd.
*
* SPDX-License-Identifier: Apache-2.0
*
* Change Logs:
* Date Author Notes
* 2022-04-28 CDT first version
*/
#ifndef __DRV_IRQ_H__
#define __DRV_IRQ_H__
/*******************************************************************************
* Include files
******************************************************************************/
#include <rtdef.h>
#include "hc32_ll.h"
/* C binding of definitions if building with C++ compiler */
#ifdef __cplusplus
extern "C"
{
#endif
/*******************************************************************************
* Global type definitions ('typedef')
******************************************************************************/
struct hc32_irq_config
{
IRQn_Type irq_num;
uint32_t irq_prio;
en_int_src_t int_src;
};
/*******************************************************************************
* Global pre-processor symbols/macros ('#define')
******************************************************************************/
/*******************************************************************************
* Global variable definitions ('extern')
******************************************************************************/
/*******************************************************************************
* Global function prototypes (definition in C source)
******************************************************************************/
rt_err_t hc32_install_irq_handler(struct hc32_irq_config *irq_config,
void (*irq_hdr)(void),
rt_bool_t irq_enable);
#ifdef __cplusplus
}
#endif
#endif /* __DRV_IRQ_H__ */
/*******************************************************************************
* EOF (not truncated)
******************************************************************************/

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bsp/hc32/libraries/hc32_drivers/drv_log.h Normal file
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/*
* Copyright (C) 2022, Xiaohua Semiconductor Co., Ltd.
*
* SPDX-License-Identifier: Apache-2.0
*
* Change Logs:
* Date Author Notes
* 2022-04-28 CDT first version
*/
/*
* NOTE: DO NOT include this file on the header file.
*/
#ifndef LOG_TAG
#define DBG_TAG "drv"
#else
#define DBG_TAG LOG_TAG
#endif /* LOG_TAG */
#ifdef DRV_DEBUG
#define DBG_LVL DBG_LOG
#else
#define DBG_LVL DBG_INFO
#endif /* DRV_DEBUG */
#include <rtdbg.h>

472
bsp/hc32/libraries/hc32_drivers/drv_pulse_encoder.c Normal file
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/*
* Copyright (C) 2022, Xiaohua Semiconductor Co., Ltd.
*
* SPDX-License-Identifier: Apache-2.0
*
* Change Logs:
* Date Author Notes
* 2022-04-28 CDT first version
*/
#include <rtdevice.h>
#include <rtdbg.h>
#ifdef RT_USING_PULSE_ENCODER
#if defined(BSP_USING_PULSE_ENCODER1) || defined(BSP_USING_PULSE_ENCODER2) || defined(BSP_USING_PULSE_ENCODER3) || \
defined(BSP_USING_PULSE_ENCODER4) || defined(BSP_USING_PULSE_ENCODER5) || defined(BSP_USING_PULSE_ENCODER6) || \
defined(BSP_USING_PULSE_ENCODER7) || defined(BSP_USING_PULSE_ENCODER8) || defined(BSP_USING_PULSE_ENCODER9) || \
defined(BSP_USING_PULSE_ENCODER10) || defined(BSP_USING_PULSE_ENCODER11) || defined(BSP_USING_PULSE_ENCODER12)
#include "drv_pulse_encoder.h"
#include "drv_irq.h"
#define TIMER_AUTO_RELOAD_VALUE (0xFFFFU)
enum
{
#ifdef BSP_USING_PULSE_ENCODER1
PULSE_ENCODER1_INDEX,
#endif
#ifdef BSP_USING_PULSE_ENCODER2
PULSE_ENCODER2_INDEX,
#endif
#ifdef BSP_USING_PULSE_ENCODER3
PULSE_ENCODER3_INDEX,
#endif
#ifdef BSP_USING_PULSE_ENCODER4
PULSE_ENCODER4_INDEX,
#endif
#ifdef BSP_USING_PULSE_ENCODER5
PULSE_ENCODER5_INDEX,
#endif
#ifdef BSP_USING_PULSE_ENCODER6
PULSE_ENCODER6_INDEX,
#endif
#ifdef BSP_USING_PULSE_ENCODER7
PULSE_ENCODER7_INDEX,
#endif
#ifdef BSP_USING_PULSE_ENCODER8
PULSE_ENCODER8_INDEX,
#endif
#ifdef BSP_USING_PULSE_ENCODER9
PULSE_ENCODER9_INDEX,
#endif
#ifdef BSP_USING_PULSE_ENCODER10
PULSE_ENCODER10_INDEX,
#endif
#ifdef BSP_USING_PULSE_ENCODER11
PULSE_ENCODER11_INDEX,
#endif
#ifdef BSP_USING_PULSE_ENCODER12
PULSE_ENCODER12_INDEX,
#endif
};
#ifdef BSP_USING_PULSE_ENCODER1
static void pulse_encoder1_irq_handler(void);
#endif
#ifdef BSP_USING_PULSE_ENCODER2
static void pulse_encoder2_irq_handler(void);
#endif
#ifdef BSP_USING_PULSE_ENCODER3
static void pulse_encoder3_irq_handler(void);
#endif
#ifdef BSP_USING_PULSE_ENCODER4
static void pulse_encoder4_irq_handler(void);
#endif
#ifdef BSP_USING_PULSE_ENCODER5
static void pulse_encoder5_irq_handler(void);
#endif
#ifdef BSP_USING_PULSE_ENCODER6
static void pulse_encoder6_irq_handler(void);
#endif
#ifdef BSP_USING_PULSE_ENCODER7
static void pulse_encoder7_irq_handler(void);
#endif
#ifdef BSP_USING_PULSE_ENCODER8
static void pulse_encoder8_irq_handler(void);
#endif
#ifdef BSP_USING_PULSE_ENCODER9
static void pulse_encoder9_irq_handler(void);
#endif
#ifdef BSP_USING_PULSE_ENCODER10
static void pulse_encoder10_irq_handler(void);
#endif
#ifdef BSP_USING_PULSE_ENCODER11
static void pulse_encoder11_irq_handler(void);
#endif
#ifdef BSP_USING_PULSE_ENCODER12
static void pulse_encoder12_irq_handler(void);
#endif
struct hc32_pulse_encoder_config
{
struct rt_pulse_encoder_device pulse_encoder;
CM_TMRA_TypeDef *timer_periph;
struct hc32_irq_config ovf_irq_config;
struct hc32_irq_config udf_irq_config;
func_ptr_t irq_callback;
rt_int32_t ovf_udf_count;
char *name;
};
#ifndef HC32_PULSE_ENCODER_CONFIG
#define HC32_PULSE_ENCODER_CONFIG(periph, irq, label, ovf_src, udf_src, \
ovf_irq_info, udf_irq_info) \
{ \
.timer_periph = periph, \
.irq_callback = irq, \
.name = label, \
.ovf_irq_config = ovf_irq_info, \
.udf_irq_config = udf_irq_info, \
.ovf_irq_config.int_src = ovf_src, \
.udf_irq_config.int_src = udf_src, \
}
#endif /* HC32_PULSE_ENCODER_CONFIG */
static struct hc32_pulse_encoder_config pulse_encoder_obj[] =
{
#ifdef BSP_USING_PULSE_ENCODER1
HC32_PULSE_ENCODER_CONFIG(CM_TMRA_1, pulse_encoder1_irq_handler, "pulse1", INT_SRC_TMRA_1_OVF, INT_SRC_TMRA_1_UDF,
PULSE_ENCODER1_OVF_IRQ_CONFIG, PULSE_ENCODER1_UDF_IRQ_CONFIG),
#endif
#ifdef BSP_USING_PULSE_ENCODER2
HC32_PULSE_ENCODER_CONFIG(CM_TMRA_2, pulse_encoder2_irq_handler, "pulse2", INT_SRC_TMRA_2_OVF, INT_SRC_TMRA_2_UDF,
PULSE_ENCODER2_OVF_IRQ_CONFIG, PULSE_ENCODER2_UDF_IRQ_CONFIG),
#endif
#ifdef BSP_USING_PULSE_ENCODER3
HC32_PULSE_ENCODER_CONFIG(CM_TMRA_3, pulse_encoder3_irq_handler, "pulse3", INT_SRC_TMRA_3_OVF, INT_SRC_TMRA_3_UDF,
PULSE_ENCODER3_OVF_IRQ_CONFIG, PULSE_ENCODER3_UDF_IRQ_CONFIG),
#endif
#ifdef BSP_USING_PULSE_ENCODER4
HC32_PULSE_ENCODER_CONFIG(CM_TMRA_4, pulse_encoder4_irq_handler, "pulse4", INT_SRC_TMRA_4_OVF, INT_SRC_TMRA_4_UDF,
PULSE_ENCODER4_OVF_IRQ_CONFIG, PULSE_ENCODER4_UDF_IRQ_CONFIG),
#endif
#ifdef BSP_USING_PULSE_ENCODER5
HC32_PULSE_ENCODER_CONFIG(CM_TMRA_5, pulse_encoder5_irq_handler, "pulse5", INT_SRC_TMRA_5_OVF, INT_SRC_TMRA_5_UDF,
PULSE_ENCODER5_OVF_IRQ_CONFIG, PULSE_ENCODER5_UDF_IRQ_CONFIG),
#endif
#ifdef BSP_USING_PULSE_ENCODER6
HC32_PULSE_ENCODER_CONFIG(CM_TMRA_6, pulse_encoder6_irq_handler, "pulse6", INT_SRC_TMRA_6_OVF, INT_SRC_TMRA_6_UDF,
PULSE_ENCODER6_OVF_IRQ_CONFIG, PULSE_ENCODER6_UDF_IRQ_CONFIG),
#endif
#ifdef BSP_USING_PULSE_ENCODER7
HC32_PULSE_ENCODER_CONFIG(CM_TMRA_7, pulse_encoder7_irq_handler, "pulse7", INT_SRC_TMRA_7_OVF, INT_SRC_TMRA_7_UDF,
PULSE_ENCODER7_OVF_IRQ_CONFIG, PULSE_ENCODER7_UDF_IRQ_CONFIG),
#endif
#ifdef BSP_USING_PULSE_ENCODER8
HC32_PULSE_ENCODER_CONFIG(CM_TMRA_8, pulse_encoder8_irq_handler, "pulse8", INT_SRC_TMRA_8_OVF, INT_SRC_TMRA_8_UDF,
PULSE_ENCODER8_OVF_IRQ_CONFIG, PULSE_ENCODER8_UDF_IRQ_CONFIG),
#endif
#ifdef BSP_USING_PULSE_ENCODER9
HC32_PULSE_ENCODER_CONFIG(CM_TMRA_9, pulse_encoder9_irq_handler, "pulse9", INT_SRC_TMRA_9_OVF, INT_SRC_TMRA_9_UDF,
PULSE_ENCODER9_OVF_IRQ_CONFIG, PULSE_ENCODER9_UDF_IRQ_CONFIG),
#endif
#ifdef BSP_USING_PULSE_ENCODER10
HC32_PULSE_ENCODER_CONFIG(CM_TMRA_10, pulse_encoder10_irq_handler, "pulse10", INT_SRC_TMRA_10_OVF, INT_SRC_TMRA_10_UDF,
PULSE_ENCODER10_OVF_IRQ_CONFIG, PULSE_ENCODER10_UDF_IRQ_CONFIG),
#endif
#ifdef BSP_USING_PULSE_ENCODER11
HC32_PULSE_ENCODER_CONFIG(CM_TMRA_11, pulse_encoder11_irq_handler, "pulse11", INT_SRC_TMRA_11_OVF, INT_SRC_TMRA_11_UDF,
PULSE_ENCODER11_OVF_IRQ_CONFIG, PULSE_ENCODER11_UDF_IRQ_CONFIG),
#endif
#ifdef BSP_USING_PULSE_ENCODER12
HC32_PULSE_ENCODER_CONFIG(CM_TMRA_12, pulse_encoder12_irq_handler, "pulse12", INT_SRC_TMRA_12_OVF, INT_SRC_TMRA_12_UDF,
PULSE_ENCODER12_OVF_IRQ_CONFIG, PULSE_ENCODER12_UDF_IRQ_CONFIG),
#endif
};
static void hc32_pulse_encoder_irq_handler(struct hc32_pulse_encoder_config *pulse_encoder_config)
{
if (SET == TMRA_GetStatus(pulse_encoder_config->timer_periph, TMRA_FLAG_OVF))
{
pulse_encoder_config->ovf_udf_count++;
TMRA_ClearStatus(pulse_encoder_config->timer_periph, TMRA_FLAG_OVF);
}
if (SET == TMRA_GetStatus(pulse_encoder_config->timer_periph, TMRA_FLAG_UDF))
{
pulse_encoder_config->ovf_udf_count--;
TMRA_ClearStatus(pulse_encoder_config->timer_periph, TMRA_FLAG_UDF);
}
}
#ifdef BSP_USING_PULSE_ENCODER1
static void pulse_encoder1_irq_handler(void)
{
/* enter interrupt */
rt_interrupt_enter();
hc32_pulse_encoder_irq_handler(&pulse_encoder_obj[PULSE_ENCODER1_INDEX]);
/* leave interrupt */
rt_interrupt_leave();
}
#endif
#ifdef BSP_USING_PULSE_ENCODER2
static void pulse_encoder2_irq_handler(void)
{
/* enter interrupt */
rt_interrupt_enter();
hc32_pulse_encoder_irq_handler(&pulse_encoder_obj[PULSE_ENCODER2_INDEX]);
/* leave interrupt */
rt_interrupt_leave();
}
#endif
#ifdef BSP_USING_PULSE_ENCODER3
static void pulse_encoder3_irq_handler(void)
{
/* enter interrupt */
rt_interrupt_enter();
hc32_pulse_encoder_irq_handler(&pulse_encoder_obj[PULSE_ENCODER3_INDEX]);
/* leave interrupt */
rt_interrupt_leave();
}
#endif
#ifdef BSP_USING_PULSE_ENCODER4
static void pulse_encoder4_irq_handler(void)
{
/* enter interrupt */
rt_interrupt_enter();
hc32_pulse_encoder_irq_handler(&pulse_encoder_obj[PULSE_ENCODER4_INDEX]);
/* leave interrupt */
rt_interrupt_leave();
}
#endif
#ifdef BSP_USING_PULSE_ENCODER5
static void pulse_encoder5_irq_handler(void)
{
/* enter interrupt */
rt_interrupt_enter();
hc32_pulse_encoder_irq_handler(&pulse_encoder_obj[PULSE_ENCODER5_INDEX]);
/* leave interrupt */
rt_interrupt_leave();
}
#endif
#ifdef BSP_USING_PULSE_ENCODER6
static void pulse_encoder6_irq_handler(void)
{
/* enter interrupt */
rt_interrupt_enter();
hc32_pulse_encoder_irq_handler(&pulse_encoder_obj[PULSE_ENCODER6_INDEX]);
/* leave interrupt */
rt_interrupt_leave();
}
#endif
#ifdef BSP_USING_PULSE_ENCODER7
static void pulse_encoder7_irq_handler(void)
{
/* enter interrupt */
rt_interrupt_enter();
hc32_pulse_encoder_irq_handler(&pulse_encoder_obj[PULSE_ENCODER7_INDEX]);
/* leave interrupt */
rt_interrupt_leave();
}
#endif
#ifdef BSP_USING_PULSE_ENCODER8
static void pulse_encoder8_irq_handler(void)
{
/* enter interrupt */
rt_interrupt_enter();
hc32_pulse_encoder_irq_handler(&pulse_encoder_obj[PULSE_ENCODER8_INDEX]);
/* leave interrupt */
rt_interrupt_leave();
}
#endif
#ifdef BSP_USING_PULSE_ENCODER9
static void pulse_encoder9_irq_handler(void)
{
/* enter interrupt */
rt_interrupt_enter();
hc32_pulse_encoder_irq_handler(&pulse_encoder_obj[PULSE_ENCODER9_INDEX]);
/* leave interrupt */
rt_interrupt_leave();
}
#endif
#ifdef BSP_USING_PULSE_ENCODER10
static void pulse_encoder10_irq_handler(void)
{
/* enter interrupt */
rt_interrupt_enter();
hc32_pulse_encoder_irq_handler(&pulse_encoder_obj[PULSE_ENCODER10_INDEX]);
/* leave interrupt */
rt_interrupt_leave();
}
#endif
#ifdef BSP_USING_PULSE_ENCODER11
static void pulse_encoder11_irq_handler(void)
{
/* enter interrupt */
rt_interrupt_enter();
hc32_pulse_encoder_irq_handler(&pulse_encoder_obj[PULSE_ENCODER11_INDEX]);
/* leave interrupt */
rt_interrupt_leave();
}
#endif
#ifdef BSP_USING_PULSE_ENCODER12
static void pulse_encoder12_irq_handler(void)
{
/* enter interrupt */
rt_interrupt_enter();
hc32_pulse_encoder_irq_handler(&pulse_encoder_obj[PULSE_ENCODER12_INDEX]);
/* leave interrupt */
rt_interrupt_leave();
}
#endif
static rt_uint16_t hc32_timer_get_unit_number(CM_TMRA_TypeDef *TMRAx)
{
rt_uint16_t unit_num;
const rt_uint32_t unit_step = 0x400U;
if (((rt_uint32_t)TMRAx) >= ((rt_uint32_t)CM_TMRA_1))
{
unit_num = (((rt_uint32_t)TMRAx) - ((rt_uint32_t)CM_TMRA_1)) / unit_step;
}
else
{
unit_num = (((rt_uint32_t)TMRAx) - ((rt_uint32_t)CM_TMRA_5)) / unit_step + 4;
}
return unit_num;
}
static void hc32_timer_clock_config(CM_TMRA_TypeDef *TMRAx, en_functional_state_t enNewState)
{
rt_uint32_t timer_periph;
rt_uint16_t unit_num;
unit_num = hc32_timer_get_unit_number(TMRAx);
timer_periph = PWC_FCG2_TMRA_1 << unit_num;
FCG_Fcg2PeriphClockCmd(timer_periph, enNewState);
}
extern rt_err_t rt_hw_board_pulse_encoder_init(CM_TMRA_TypeDef *TMRAx);
rt_err_t hc32_pulse_encoder_init(struct rt_pulse_encoder_device *pulse_encoder)
{
struct hc32_pulse_encoder_config *pulse_encoder_device;
stc_tmra_init_t stcTmraInit;
rt_err_t result;
RT_ASSERT(pulse_encoder != RT_NULL);
pulse_encoder_device = (struct hc32_pulse_encoder_config *)pulse_encoder;
/* Enable Timer peripheral clock. */
hc32_timer_clock_config(pulse_encoder_device->timer_periph, ENABLE);
/* pwm pin configuration */
result = rt_hw_board_pulse_encoder_init(pulse_encoder_device->timer_periph);
if (RT_EOK == result)
{
TMRA_DeInit(pulse_encoder_device->timer_periph);
TMRA_StructInit(&stcTmraInit);
stcTmraInit.u32PeriodValue = TIMER_AUTO_RELOAD_VALUE;
stcTmraInit.u8CountSrc = TMRA_CNT_SRC_HW;
stcTmraInit.hw_count.u16CountUpCond = TMRA_CNT_UP_COND_CLKB_HIGH_CLKA_RISING;
stcTmraInit.hw_count.u16CountDownCond = TMRA_CNT_DOWN_COND_CLKB_LOW_CLKA_RISING;
TMRA_Init(pulse_encoder_device->timer_periph, &stcTmraInit);
LOG_D("%s init success", pulse_encoder_device->name);
hc32_install_irq_handler(&pulse_encoder_device->ovf_irq_config, pulse_encoder_device->irq_callback, RT_FALSE);
NVIC_EnableIRQ(pulse_encoder_device->ovf_irq_config.irq);
hc32_install_irq_handler(&pulse_encoder_device->udf_irq_config, pulse_encoder_device->irq_callback, RT_FALSE);
NVIC_EnableIRQ(pulse_encoder_device->udf_irq_config.irq);
/* clear update flag */
TMRA_ClearStatus(pulse_encoder_device->timer_periph, (TMRA_FLAG_OVF | TMRA_FLAG_UDF));
}
return result;
}
rt_err_t hc32_pulse_encoder_clear_count(struct rt_pulse_encoder_device *pulse_encoder)
{
struct hc32_pulse_encoder_config *pulse_encoder_device;
pulse_encoder_device = (struct hc32_pulse_encoder_config *)pulse_encoder;
pulse_encoder_device->ovf_udf_count = 0;
TMRA_Stop(pulse_encoder_device->timer_periph);
TMRA_SetCountValue(pulse_encoder_device->timer_periph, 0);
TMRA_ClearStatus(pulse_encoder_device->timer_periph, (TMRA_FLAG_OVF | TMRA_FLAG_UDF));
TMRA_Start(pulse_encoder_device->timer_periph);
return RT_EOK;
}
rt_int32_t hc32_pulse_encoder_get_count(struct rt_pulse_encoder_device *pulse_encoder)
{
struct hc32_pulse_encoder_config *pulse_encoder_device;
rt_int32_t period_val;
rt_int32_t count_val;
pulse_encoder_device = (struct hc32_pulse_encoder_config *)pulse_encoder;
period_val = TMRA_GetCountValue(pulse_encoder_device->timer_periph);
count_val = period_val + pulse_encoder_device->ovf_udf_count * TIMER_AUTO_RELOAD_VALUE;
return count_val;
}
rt_err_t hc32_pulse_encoder_control(struct rt_pulse_encoder_device *pulse_encoder, rt_uint32_t cmd, void *args)
{
rt_err_t result = RT_EOK;
struct hc32_pulse_encoder_config *pulse_encoder_device;
pulse_encoder_device = (struct hc32_pulse_encoder_config *)pulse_encoder;
switch (cmd)
{
case PULSE_ENCODER_CMD_ENABLE:
TMRA_IntCmd(pulse_encoder_device->timer_periph, (TMRA_INT_OVF | TMRA_INT_UDF), ENABLE);
TMRA_Start(pulse_encoder_device->timer_periph);
break;
case PULSE_ENCODER_CMD_DISABLE:
TMRA_Stop(pulse_encoder_device->timer_periph);
TMRA_IntCmd(pulse_encoder_device->timer_periph, (TMRA_INT_OVF | TMRA_INT_UDF), DISABLE);
break;
default:
result = -RT_ENOSYS;
break;
}
return result;
}
static const struct rt_pulse_encoder_ops pulse_encoder_ops =
{
.init = hc32_pulse_encoder_init,
.get_count = hc32_pulse_encoder_get_count,
.clear_count = hc32_pulse_encoder_clear_count,
.control = hc32_pulse_encoder_control,
};
int hw_pulse_encoder_init(void)
{
int i;
int result;
result = RT_EOK;
for (i = 0; i < sizeof(pulse_encoder_obj) / sizeof(pulse_encoder_obj[0]); i++)
{
pulse_encoder_obj[i].pulse_encoder.type = AB_PHASE_PULSE_ENCODER;
pulse_encoder_obj[i].pulse_encoder.ops = &pulse_encoder_ops;
if (rt_device_pulse_encoder_register(&pulse_encoder_obj[i].pulse_encoder, pulse_encoder_obj[i].name, pulse_encoder_obj[i].timer_periph) != RT_EOK)
{
LOG_E("%s register failed", pulse_encoder_obj[i].name);
result = -RT_ERROR;
}
}
return result;
}
INIT_BOARD_EXPORT(hw_pulse_encoder_init);
#endif
#endif

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/*
* Copyright (C) 2022, Xiaohua Semiconductor Co., Ltd.
*
* SPDX-License-Identifier: Apache-2.0
*
* Change Logs:
* Date Author Notes
* 2022-04-28 CDT first version
*/
#ifndef __DRV_PULSE_ENCODER_H__
#define __DRV_PULSE_ENCODER_H__
#include <rtthread.h>
#include "board_config.h"
#ifdef __cplusplus
extern "C" {
#endif
#ifdef BSP_USING_PULSE_ENCODER1
#ifndef PULSE_ENCODER1_OVF_IRQ_CONFIG
#define PULSE_ENCODER1_OVF_IRQ_CONFIG \
{ \
.irq = PULSE_ENCODER1_OVF_INT_IRQn, \
.irq_prio = PULSE_ENCODER1_OVF_INT_PRIO, \
}
#endif /* PULSE_ENCODER1_OVF_IRQ_CONFIG */
#ifndef PULSE_ENCODER1_UDF_IRQ_CONFIG
#define PULSE_ENCODER1_UDF_IRQ_CONFIG \
{ \
.irq = PULSE_ENCODER1_UNF_INT_IRQn, \
.irq_prio = PULSE_ENCODER1_UNF_INT_PRIO, \
}
#endif /* PULSE_ENCODER1_UDF_IRQ_CONFIG */
#endif /* BSP_USING_PULSE_ENCODER1 */
#ifdef BSP_USING_PULSE_ENCODER2
#ifndef PULSE_ENCODER2_OVF_IRQ_CONFIG
#define PULSE_ENCODER2_OVF_IRQ_CONFIG \
{ \
.irq = PULSE_ENCODER2_OVF_INT_IRQn, \
.irq_prio = PULSE_ENCODER2_OVF_INT_PRIO, \
}
#endif /* PULSE_ENCODER2_OVF_IRQ_CONFIG */
#ifndef PULSE_ENCODER2_UDF_IRQ_CONFIG
#define PULSE_ENCODER2_UDF_IRQ_CONFIG \
{ \
.irq = PULSE_ENCODER2_UNF_INT_IRQn, \
.irq_prio = PULSE_ENCODER2_UNF_INT_PRIO, \
}
#endif /* PULSE_ENCODER2_UDF_IRQ_CONFIG */
#endif /* BSP_USING_PULSE_ENCODER2 */
#ifdef BSP_USING_PULSE_ENCODER3
#ifndef PULSE_ENCODER3_OVF_IRQ_CONFIG
#define PULSE_ENCODER3_OVF_IRQ_CONFIG \
{ \
.irq = PULSE_ENCODER3_OVF_INT_IRQn, \
.irq_prio = PULSE_ENCODER3_OVF_INT_PRIO, \
}
#endif /* PULSE_ENCODER3_OVF_IRQ_CONFIG */
#ifndef PULSE_ENCODER3_UDF_IRQ_CONFIG
#define PULSE_ENCODER3_UDF_IRQ_CONFIG \
{ \
.irq = PULSE_ENCODER3_UNF_INT_IRQn, \
.irq_prio = PULSE_ENCODER3_UNF_INT_PRIO, \
}
#endif /* PULSE_ENCODER3_UDF_IRQ_CONFIG */
#endif /* BSP_USING_PULSE_ENCODER3 */
#ifdef BSP_USING_PULSE_ENCODER4
#ifndef PULSE_ENCODER4_OVF_IRQ_CONFIG
#define PULSE_ENCODER4_OVF_IRQ_CONFIG \
{ \
.irq = PULSE_ENCODER4_OVF_INT_IRQn, \
.irq_prio = PULSE_ENCODER4_OVF_INT_PRIO, \
}
#endif /* PULSE_ENCODER4_OVF_IRQ_CONFIG */
#ifndef PULSE_ENCODER4_UDF_IRQ_CONFIG
#define PULSE_ENCODER4_UDF_IRQ_CONFIG \
{ \
.irq = PULSE_ENCODER4_UNF_INT_IRQn, \
.irq_prio = PULSE_ENCODER4_UNF_INT_PRIO, \
}
#endif /* PULSE_ENCODER4_UDF_IRQ_CONFIG */
#endif /* BSP_USING_PULSE_ENCODER4 */
#ifdef BSP_USING_PULSE_ENCODER5
#ifndef PULSE_ENCODER5_OVF_IRQ_CONFIG
#define PULSE_ENCODER5_OVF_IRQ_CONFIG \
{ \
.irq = PULSE_ENCODER5_OVF_INT_IRQn, \
.irq_prio = PULSE_ENCODER5_OVF_INT_PRIO, \
}
#endif /* PULSE_ENCODER5_OVF_IRQ_CONFIG */
#ifndef PULSE_ENCODER5_UDF_IRQ_CONFIG
#define PULSE_ENCODER5_UDF_IRQ_CONFIG \
{ \
.irq = PULSE_ENCODER5_UNF_INT_IRQn, \
.irq_prio = PULSE_ENCODER5_UNF_INT_PRIO, \
}
#endif /* PULSE_ENCODER5_UDF_IRQ_CONFIG */
#endif /* BSP_USING_PULSE_ENCODER5 */
#ifdef BSP_USING_PULSE_ENCODER6
#ifndef PULSE_ENCODER6_OVF_IRQ_CONFIG
#define PULSE_ENCODER6_OVF_IRQ_CONFIG \
{ \
.irq = PULSE_ENCODER6_OVF_INT_IRQn, \
.irq_prio = PULSE_ENCODER6_OVF_INT_PRIO, \
}
#endif /* PULSE_ENCODER6_OVF_IRQ_CONFIG */
#ifndef PULSE_ENCODER6_UDF_IRQ_CONFIG
#define PULSE_ENCODER6_UDF_IRQ_CONFIG \
{ \
.irq = PULSE_ENCODER6_UNF_INT_IRQn, \
.irq_prio = PULSE_ENCODER6_UNF_INT_PRIO, \
}
#endif /* PULSE_ENCODER6_UDF_IRQ_CONFIG */
#endif /* BSP_USING_PULSE_ENCODER6 */
#ifdef BSP_USING_PULSE_ENCODER7
#ifndef PULSE_ENCODER7_OVF_IRQ_CONFIG
#define PULSE_ENCODER7_OVF_IRQ_CONFIG \
{ \
.irq = PULSE_ENCODER7_OVF_INT_IRQn, \
.irq_prio = PULSE_ENCODER7_OVF_INT_PRIO, \
}
#endif /* PULSE_ENCODER7_OVF_IRQ_CONFIG */
#ifndef PULSE_ENCODER7_UDF_IRQ_CONFIG
#define PULSE_ENCODER7_UDF_IRQ_CONFIG \
{ \
.irq = PULSE_ENCODER7_UNF_INT_IRQn, \
.irq_prio = PULSE_ENCODER7_UNF_INT_PRIO, \
}
#endif /* PULSE_ENCODER7_UDF_IRQ_CONFIG */
#endif /* BSP_USING_PULSE_ENCODER7 */
#ifdef BSP_USING_PULSE_ENCODER8
#ifndef PULSE_ENCODER8_OVF_IRQ_CONFIG
#define PULSE_ENCODER8_OVF_IRQ_CONFIG \
{ \
.irq = PULSE_ENCODER8_OVF_INT_IRQn, \
.irq_prio = PULSE_ENCODER8_OVF_INT_PRIO, \
}
#endif /* PULSE_ENCODER8_OVF_IRQ_CONFIG */
#ifndef PULSE_ENCODER8_UDF_IRQ_CONFIG
#define PULSE_ENCODER8_UDF_IRQ_CONFIG \
{ \
.irq = PULSE_ENCODER8_UNF_INT_IRQn, \
.irq_prio = PULSE_ENCODER8_UNF_INT_PRIO, \
}
#endif /* PULSE_ENCODER8_UDF_IRQ_CONFIG */
#endif /* BSP_USING_PULSE_ENCODER8 */
#ifdef BSP_USING_PULSE_ENCODER9
#ifndef PULSE_ENCODER9_OVF_IRQ_CONFIG
#define PULSE_ENCODER9_OVF_IRQ_CONFIG \
{ \
.irq = PULSE_ENCODER9_OVF_INT_IRQn, \
.irq_prio = PULSE_ENCODER9_OVF_INT_PRIO, \
}
#endif /* PULSE_ENCODER9_OVF_IRQ_CONFIG */
#ifndef PULSE_ENCODER9_UDF_IRQ_CONFIG
#define PULSE_ENCODER9_UDF_IRQ_CONFIG \
{ \
.irq = PULSE_ENCODER9_UNF_INT_IRQn, \
.irq_prio = PULSE_ENCODER9_UNF_INT_PRIO, \
}
#endif /* PULSE_ENCODER9_UDF_IRQ_CONFIG */
#endif /* BSP_USING_PULSE_ENCODER9 */
#ifdef BSP_USING_PULSE_ENCODER10
#ifndef PULSE_ENCODER10_OVF_IRQ_CONFIG
#define PULSE_ENCODER10_OVF_IRQ_CONFIG \
{ \
.irq = PULSE_ENCODER10_OVF_INT_IRQn, \
.irq_prio = PULSE_ENCODER10_OVF_INT_PRIO, \
}
#endif /* PULSE_ENCODER10_OVF_IRQ_CONFIG */
#ifndef PULSE_ENCODER10_UDF_IRQ_CONFIG
#define PULSE_ENCODER10_UDF_IRQ_CONFIG \
{ \
.irq = PULSE_ENCODER10_UNF_INT_IRQn, \
.irq_prio = PULSE_ENCODER10_UNF_INT_PRIO, \
}
#endif /* PULSE_ENCODER10_UDF_IRQ_CONFIG */
#endif /* BSP_USING_PULSE_ENCODER10 */
#ifdef BSP_USING_PULSE_ENCODER11
#ifndef PULSE_ENCODER11_OVF_IRQ_CONFIG
#define PULSE_ENCODER11_OVF_IRQ_CONFIG \
{ \
.irq = PULSE_ENCODER11_OVF_INT_IRQn, \
.irq_prio = PULSE_ENCODER11_OVF_INT_PRIO, \
}
#endif /* PULSE_ENCODER11_OVF_IRQ_CONFIG */
#ifndef PULSE_ENCODER11_UDF_IRQ_CONFIG
#define PULSE_ENCODER11_UDF_IRQ_CONFIG \
{ \
.irq = PULSE_ENCODER11_UNF_INT_IRQn, \
.irq_prio = PULSE_ENCODER11_UNF_INT_PRIO, \
}
#endif /* PULSE_ENCODER11_UDF_IRQ_CONFIG */
#endif /* BSP_USING_PULSE_ENCODER11 */
#ifdef BSP_USING_PULSE_ENCODER12
#ifndef PULSE_ENCODER12_OVF_IRQ_CONFIG
#define PULSE_ENCODER12_OVF_IRQ_CONFIG \
{ \
.irq = PULSE_ENCODER12_OVF_INT_IRQn, \
.irq_prio = PULSE_ENCODER12_OVF_INT_PRIO, \
}
#endif /* PULSE_ENCODER12_OVF_IRQ_CONFIG */
#ifndef PULSE_ENCODER12_UDF_IRQ_CONFIG
#define PULSE_ENCODER12_UDF_IRQ_CONFIG \
{ \
.irq = PULSE_ENCODER12_UNF_INT_IRQn, \
.irq_prio = PULSE_ENCODER12_UNF_INT_PRIO, \
}
#endif /* PULSE_ENCODER12_UDF_IRQ_CONFIG */
#endif /* BSP_USING_PULSE_ENCODER12 */
#ifdef __cplusplus
}
#endif
#endif /* __DRV_PULSE_ENCODER_H__ */

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/*
* Copyright (C) 2022, Xiaohua Semiconductor Co., Ltd.
*
* SPDX-License-Identifier: Apache-2.0
*
* Change Logs:
* Date Author Notes
* 2022-04-28 CDT first version
*/
#include <board.h>
#include <rtdbg.h>
#if defined(RT_USING_PWM)
#if defined(BSP_USING_PWM1) || defined(BSP_USING_PWM2) || defined(BSP_USING_PWM3) || \
defined(BSP_USING_PWM4) || defined(BSP_USING_PWM5) || defined(BSP_USING_PWM6) || \
defined(BSP_USING_PWM7) || defined(BSP_USING_PWM8) || defined(BSP_USING_PWM9) || \
defined(BSP_USING_PWM10) || defined(BSP_USING_PWM11) || defined(BSP_USING_PWM12)
#define PWM_MAX_PERIOD (65535U)
#define PWM_MIN_PERIOD (1U)
#define PWM_MIN_PULSE (1U)
#define PWM_MAX_CHANNEL (TMRA_CH4)
enum
{
#ifdef BSP_USING_PWM1
PWM1_INDEX,
#endif
#ifdef BSP_USING_PWM2
PWM2_INDEX,
#endif
#ifdef BSP_USING_PWM3
PWM3_INDEX,
#endif
#ifdef BSP_USING_PWM4
PWCM_INDEX,
#endif
#ifdef BSP_USING_PWM5
PWM5_INDEX,
#endif
#ifdef BSP_USING_PWM6
PWM6_INDEX,
#endif
#ifdef BSP_USING_PWM7
PWM7_INDEX,
#endif
#ifdef BSP_USING_PWM8
PWM8_INDEX,
#endif
#ifdef BSP_USING_PWM9
PWM9_INDEX,
#endif
#ifdef BSP_USING_PWM10
PWM10_INDEX,
#endif
#ifdef BSP_USING_PWM11
PWM11_INDEX,
#endif
#ifdef BSP_USING_PWM12
PWM12_INDEX,
#endif
};
struct hc32_pwm_config
{
struct rt_device_pwm pwm_device;
CM_TMRA_TypeDef *timer_periph;
rt_uint8_t channel;
char *name;
};
#ifndef HC32_PWM_CONFIG
#define HC32_PWM_CONFIG(periph, ch, label) \
{ \
.timer_periph = periph, \
.channel = ch, \
.name = label \
}
#endif /* HC32_PWM_CONFIG */
static struct hc32_pwm_config pwm_obj[] =
{
#ifdef BSP_USING_PWM1
HC32_PWM_CONFIG(CM_TMRA_1, 0, "pwm1"),
#endif
#ifdef BSP_USING_PWM2
HC32_PWM_CONFIG(CM_TMRA_2, 0, "pwm2"),
#endif
#ifdef BSP_USING_PWM3
HC32_PWM_CONFIG(CM_TMRA_3, 0, "pwm3"),
#endif
#ifdef BSP_USING_PWM4
HC32_PWM_CONFIG(CM_TMRA_4, 0, "pwm4"),
#endif
#ifdef BSP_USING_PWM5
HC32_PWM_CONFIG(CM_TMRA_5, 0, "pwm5"),
#endif
#ifdef BSP_USING_PWM6
HC32_PWM_CONFIG(CM_TMRA_6, 0, "pwm6"),
#endif
#ifdef BSP_USING_PWM7
HC32_PWM_CONFIG(CM_TMRA_7, 0, "pwm7"),
#endif
#ifdef BSP_USING_PWM8
HC32_PWM_CONFIG(CM_TMRA_8, 0, "pwm8"),
#endif
#ifdef BSP_USING_PWM9
HC32_PWM_CONFIG(CM_TMRA_9, 0, "pwm9"),
#endif
#ifdef BSP_USING_PWM10
HC32_PWM_CONFIG(CM_TMRA_10, 0, "pwm10"),
#endif
#ifdef BSP_USING_PWM11
HC32_PWM_CONFIG(CM_TMRA_11, 0, "pwm11"),
#endif
#ifdef BSP_USING_PWM12
HC32_PWM_CONFIG(CM_TMRA_12, 0, "pwm12"),
#endif
};
static rt_uint16_t hc32_pwm_get_unit_number(CM_TMRA_TypeDef *TMRAx)
{
rt_uint16_t unit_num;
const rt_uint32_t unit_step = 0x400U;
if (((rt_uint32_t)TMRAx) >= ((rt_uint32_t)CM_TMRA_1))
{
unit_num = (((rt_uint32_t)TMRAx) - ((rt_uint32_t)CM_TMRA_1)) / unit_step;
}
else
{
unit_num = (((rt_uint32_t)TMRAx) - ((rt_uint32_t)CM_TMRA_5)) / unit_step + 4;
}
return unit_num;
}
static void hc32_pwm_clock_config(CM_TMRA_TypeDef *TMRAx, en_functional_state_t enNewState)
{
rt_uint32_t timer_periph;
rt_uint16_t unit_num;
unit_num = hc32_pwm_get_unit_number(TMRAx);
timer_periph = PWC_FCG2_TMRA_1 << unit_num;
FCG_Fcg2PeriphClockCmd(timer_periph, enNewState);
}
static rt_err_t hc32_pwm_enable(CM_TMRA_TypeDef *TMRAx, struct rt_pwm_configuration *configuration, rt_bool_t enable)
{
if (configuration->channel > PWM_MAX_CHANNEL)
{
return RT_EINVAL;
}
if (!enable)
{
TMRA_PWM_OutputCmd(TMRAx, configuration->channel, DISABLE);
}
else
{
TMRA_PWM_OutputCmd(TMRAx, configuration->channel, ENABLE);
}
return RT_EOK;
}
static rt_err_t hc32_pwm_get(CM_TMRA_TypeDef *TMRAx, struct rt_pwm_configuration *configuration)
{
stc_clock_freq_t stcClkFreq;
rt_uint32_t clk_freq;
rt_uint16_t unit_num;
rt_uint16_t div_val;
CLK_GetClockFreq(&stcClkFreq);
unit_num = hc32_pwm_get_unit_number(TMRAx);
if (unit_num >= 4)
{
clk_freq = stcClkFreq.u32Pclk1Freq;
}
else
{
clk_freq = stcClkFreq.u32Pclk0Freq;
}
/* Convert nanosecond to frequency and duty cycle */
div_val = 0x01 << (READ_REG32_BIT(TMRAx->BCSTR, TMRA_BCSTR_CKDIV) >> TMRA_BCSTR_CKDIV_POS);
clk_freq /= 1000000UL;
configuration->period = (TMRA_GetPeriodValue(TMRAx) + 1) * div_val * 1000UL / clk_freq;
configuration->pulse = (TMRA_GetCompareValue(TMRAx, configuration->channel) + 1) * div_val * 1000UL / clk_freq;
return RT_EOK;
}
static rt_err_t hc32_pwm_set(CM_TMRA_TypeDef *TMRAx, struct rt_pwm_configuration *configuration)
{
rt_uint32_t period, pulse;
rt_uint64_t clk_div;
stc_clock_freq_t stcClkFreq;
rt_uint32_t clk_freq;
rt_uint16_t unit_num;
rt_uint16_t div_val;
CLK_GetClockFreq(&stcClkFreq);
unit_num = hc32_pwm_get_unit_number(TMRAx);
if (unit_num >= 4)
{
clk_freq = stcClkFreq.u32Pclk1Freq;
}
else
{
clk_freq = stcClkFreq.u32Pclk0Freq;
}
/* Convert nanosecond to frequency and duty cycle */
clk_freq /= 1000000UL;
period = (unsigned long long)configuration->period * clk_freq / 1000UL;
clk_div = period / PWM_MAX_PERIOD + 1;
if (clk_div > 1024)
{
return RT_EINVAL;
}
else if (clk_div != 1)
{
for (div_val = 512; div_val > 1; div_val >>= 1)
{
if (clk_div > div_val)
{
clk_div = div_val << 1;
break;
}
}
}
period = period / clk_div;
TMRA_SetClockDiv(TMRAx, ((__CLZ(__RBIT(clk_div))) << TMRA_BCSTR_CKDIV_POS));
if (period < PWM_MIN_PERIOD)
{
period = PWM_MIN_PERIOD;
}
TMRA_SetPeriodValue(TMRAx, period - 1);
pulse = (unsigned long long)configuration->pulse * clk_freq / clk_div / 1000UL;
if (pulse < PWM_MIN_PULSE)
{
pulse = PWM_MIN_PULSE;
}
else if (pulse > period)
{
pulse = period;
}
TMRA_SetCompareValue(TMRAx, configuration->channel, pulse - 1);
TMRA_SetCountValue(TMRAx, 0);
return RT_EOK;
}
static rt_err_t hc32_pwm_control(struct rt_device_pwm *device, int cmd, void *arg)
{
struct rt_pwm_configuration *configuration = (struct rt_pwm_configuration *)arg;
CM_TMRA_TypeDef *timer_periph = (CM_TMRA_TypeDef *)device->parent.user_data;
switch (cmd)
{
case PWM_CMD_ENABLE:
return hc32_pwm_enable(timer_periph, configuration, RT_TRUE);
case PWM_CMD_DISABLE:
return hc32_pwm_enable(timer_periph, configuration, RT_FALSE);
case PWM_CMD_SET:
return hc32_pwm_set(timer_periph, configuration);
case PWM_CMD_GET:
return hc32_pwm_get(timer_periph, configuration);
default:
return RT_EINVAL;
}
}
extern rt_err_t rt_hw_board_pwm_init(CM_TMRA_TypeDef *TMRAx);
static rt_err_t hc32_pwm_init(struct hc32_pwm_config *device)
{
rt_err_t result = RT_EOK;
stc_tmra_init_t stcTmraInit;
stc_tmra_pwm_init_t stcPwmCfg;
RT_ASSERT(device != RT_NULL);
/* ENABLE Timer peripheral clock. */
hc32_pwm_clock_config(device->timer_periph, ENABLE);
/* pwm pin configuration */
result = rt_hw_board_pwm_init(device->timer_periph);
if (RT_EOK == result)
{
TMRA_DeInit(device->timer_periph);
TMRA_StructInit(&stcTmraInit);
stcTmraInit.sw_count.u16ClockDiv = TMRA_CLK_DIV1;
stcTmraInit.u16CountReload = TMRA_CNT_RELOAD_ENABLE;
stcTmraInit.u32PeriodValue = 0xFFFF;
TMRA_Init(device->timer_periph, &stcTmraInit);
/* Set the comparison reference value */
TMRA_PWM_StructInit(&stcPwmCfg);
stcPwmCfg.u16StartPolarity = TMRA_PWM_HIGH;
stcPwmCfg.u16StopPolarity = TMRA_PWM_LOW;
stcPwmCfg.u16CompareMatchPolarity = TMRA_PWM_LOW;
stcPwmCfg.u16PeriodMatchPolarity = TMRA_PWM_HIGH;
/* config pwm channel */
if (0 != (device->channel & 0x01))
{
TMRA_PWM_Init(device->timer_periph, TMRA_CH1, &stcPwmCfg);
TMRA_SetCompareValue(device->timer_periph, TMRA_CH1, 0x7FFF);
}
if (0 != (device->channel & 0x02))
{
TMRA_PWM_Init(device->timer_periph, TMRA_CH2, &stcPwmCfg);
TMRA_SetCompareValue(device->timer_periph, TMRA_CH2, 0x7FFF);
}
if (0 != (device->channel & 0x04))
{
TMRA_PWM_Init(device->timer_periph, TMRA_CH3, &stcPwmCfg);
TMRA_SetCompareValue(device->timer_periph, TMRA_CH3, 0x7FFF);
}
if (0 != (device->channel & 0x08))
{
TMRA_PWM_Init(device->timer_periph, TMRA_CH4, &stcPwmCfg);
TMRA_SetCompareValue(device->timer_periph, TMRA_CH4, 0x7FFF);
}
/* start timer */
TMRA_Start(device->timer_periph);
}
return result;
}
static void hc32_pwm_get_channel(void)
{
#ifdef BSP_USING_PWM1_CH1
pwm_obj[PWM1_INDEX].channel |= (0x01 << 0);
#endif
#ifdef BSP_USING_PWM1_CH2
pwm_obj[PWM1_INDEX].channel |= (0x01 << 1);
#endif
#ifdef BSP_USING_PWM1_CH3
pwm_obj[PWM1_INDEX].channel |= (0x01 << 2);
#endif
#ifdef BSP_USING_PWM1_CH4
pwm_obj[PWM1_INDEX].channel |= (0x01 << 3);
#endif
#ifdef BSP_USING_PWM2_CH1
pwm_obj[PWM2_INDEX].channel |= (0x01 << 0);
#endif
#ifdef BSP_USING_PWM2_CH2
pwm_obj[PWM2_INDEX].channel |= (0x01 << 1);
#endif
#ifdef BSP_USING_PWM2_CH3
pwm_obj[PWM2_INDEX].channel |= (0x01 << 2);
#endif
#ifdef BSP_USING_PWM2_CH4
pwm_obj[PWM2_INDEX].channel |= (0x01 << 3);
#endif
#ifdef BSP_USING_PWM3_CH1
pwm_obj[PWM3_INDEX].channel |= (0x01 << 0);
#endif
#ifdef BSP_USING_PWM3_CH2
pwm_obj[PWM3_INDEX].channel |= (0x01 << 1);
#endif
#ifdef BSP_USING_PWM3_CH3
pwm_obj[PWM3_INDEX].channel |= (0x01 << 2);
#endif
#ifdef BSP_USING_PWM3_CH4
pwm_obj[PWM3_INDEX].channel |= (0x01 << 3);
#endif
#ifdef BSP_USING_PWCM_CH1
pwm_obj[PWCM_INDEX].channel |= (0x01 << 0);
#endif
#ifdef BSP_USING_PWCM_CH2
pwm_obj[PWCM_INDEX].channel |= (0x01 << 1);
#endif
#ifdef BSP_USING_PWCM_CH3
pwm_obj[PWCM_INDEX].channel |= (0x01 << 2);
#endif
#ifdef BSP_USING_PWCM_CH4
pwm_obj[PWCM_INDEX].channel |= (0x01 << 3);
#endif
#ifdef BSP_USING_PWM5_CH1
pwm_obj[PWM5_INDEX].channel |= (0x01 << 0);
#endif
#ifdef BSP_USING_PWM5_CH2
pwm_obj[PWM5_INDEX].channel |= (0x01 << 1);
#endif
#ifdef BSP_USING_PWM5_CH3
pwm_obj[PWM5_INDEX].channel |= (0x01 << 2);
#endif
#ifdef BSP_USING_PWM5_CH4
pwm_obj[PWM5_INDEX].channel |= (0x01 << 3);
#endif
#ifdef BSP_USING_PWM6_CH1
pwm_obj[PWM6_INDEX].channel |= (0x01 << 0);
#endif
#ifdef BSP_USING_PWM6_CH2
pwm_obj[PWM6_INDEX].channel |= (0x01 << 1);
#endif
#ifdef BSP_USING_PWM6_CH3
pwm_obj[PWM6_INDEX].channel |= (0x01 << 2);
#endif
#ifdef BSP_USING_PWM6_CH4
pwm_obj[PWM6_INDEX].channel |= (0x01 << 3);
#endif
#ifdef BSP_USING_PWM7_CH1
pwm_obj[PWM7_INDEX].channel |= (0x01 << 0);
#endif
#ifdef BSP_USING_PWM7_CH2
pwm_obj[PWM7_INDEX].channel |= (0x01 << 1);
#endif
#ifdef BSP_USING_PWM7_CH3
pwm_obj[PWM7_INDEX].channel |= (0x01 << 2);
#endif
#ifdef BSP_USING_PWM7_CH4
pwm_obj[PWM7_INDEX].channel |= (0x01 << 3);
#endif
#ifdef BSP_USING_PWM8_CH1
pwm_obj[PWM8_INDEX].channel |= (0x01 << 0);
#endif
#ifdef BSP_USING_PWM8_CH2
pwm_obj[PWM8_INDEX].channel |= (0x01 << 1);
#endif
#ifdef BSP_USING_PWM8_CH3
pwm_obj[PWM8_INDEX].channel |= (0x01 << 2);
#endif
#ifdef BSP_USING_PWM8_CH4
pwm_obj[PWM8_INDEX].channel |= (0x01 << 3);
#endif
#ifdef BSP_USING_PWM9_CH1
pwm_obj[PWM9_INDEX].channel |= (0x01 << 0);
#endif
#ifdef BSP_USING_PWM9_CH2
pwm_obj[PWM9_INDEX].channel |= (0x01 << 1);
#endif
#ifdef BSP_USING_PWM9_CH3
pwm_obj[PWM9_INDEX].channel |= (0x01 << 2);
#endif
#ifdef BSP_USING_PWM9_CH4
pwm_obj[PWM9_INDEX].channel |= (0x01 << 3);
#endif
#ifdef BSP_USING_PWM10_CH1
pwm_obj[PWM10_INDEX].channel |= (0x01 << 0);
#endif
#ifdef BSP_USING_PWM10_CH2
pwm_obj[PWM10_INDEX].channel |= (0x01 << 1);
#endif
#ifdef BSP_USING_PWM10_CH3
pwm_obj[PWM10_INDEX].channel |= (0x01 << 2);
#endif
#ifdef BSP_USING_PWM10_CH4
pwm_obj[PWM10_INDEX].channel |= (0x01 << 3);
#endif
#ifdef BSP_USING_PWM11_CH1
pwm_obj[PWM11_INDEX].channel |= (0x01 << 0);
#endif
#ifdef BSP_USING_PWM11_CH2
pwm_obj[PWM11_INDEX].channel |= (0x01 << 1);
#endif
#ifdef BSP_USING_PWM11_CH3
pwm_obj[PWM11_INDEX].channel |= (0x01 << 2);
#endif
#ifdef BSP_USING_PWM11_CH4
pwm_obj[PWM11_INDEX].channel |= (0x01 << 3);
#endif
#ifdef BSP_USING_PWM12_CH1
pwm_obj[PWM12_INDEX].channel |= (0x01 << 0);
#endif
#ifdef BSP_USING_PWM12_CH2
pwm_obj[PWM12_INDEX].channel |= (0x01 << 1);
#endif
#ifdef BSP_USING_PWM12_CH3
pwm_obj[PWM12_INDEX].channel |= (0x01 << 2);
#endif
#ifdef BSP_USING_PWM12_CH4
pwm_obj[PWM12_INDEX].channel |= (0x01 << 3);
#endif
}
static struct rt_pwm_ops pwm_ops =
{
.control = hc32_pwm_control
};
static int rt_hw_pwm_init(void)
{
int i = 0;
int result = RT_EOK;
hc32_pwm_get_channel();
for (i = 0; i < sizeof(pwm_obj) / sizeof(pwm_obj[0]); i++)
{
if (hc32_pwm_init(&pwm_obj[i]) != RT_EOK)
{
LOG_E("%s init failed", pwm_obj[i].name);
result = -RT_ERROR;
}
else
{
LOG_D("%s init success", pwm_obj[i].name);
/* register pwm device */
if (rt_device_pwm_register(&pwm_obj[i].pwm_device, pwm_obj[i].name, &pwm_ops, pwm_obj[i].timer_periph) == RT_EOK)
{
LOG_D("%s register success", pwm_obj[i].name);
}
else
{
LOG_E("%s register failed", pwm_obj[i].name);
result = -RT_ERROR;
}
}
}
return result;
}
INIT_DEVICE_EXPORT(rt_hw_pwm_init);
#endif
#endif /* RT_USING_PWM */

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/*
* Copyright (C) 2022, Xiaohua Semiconductor Co., Ltd.
*
* SPDX-License-Identifier: Apache-2.0
*
* Change Logs:
* Date Author Notes
* 2022-04-28 CDT first version
*/
#include <board.h>
#include <rtdbg.h>
#include <rtthread.h>
#include <rtdevice.h>
#include <sys/time.h>
#ifdef BSP_USING_RTC
static struct rt_device rtc;
static time_t hc32_rtc_get_time_stamp(void)
{
stc_rtc_time_t stcRtcTime = {0};
stc_rtc_date_t stcRtcDate = {0};
struct tm tm_new = {0};
RTC_GetTime(RTC_DATA_FMT_DEC, &stcRtcTime);
RTC_GetDate(RTC_DATA_FMT_DEC, &stcRtcDate);
tm_new.tm_sec = stcRtcTime.u8Second;
tm_new.tm_min = stcRtcTime.u8Minute;
tm_new.tm_hour = stcRtcTime.u8Hour;
tm_new.tm_mday = stcRtcDate.u8Day;
tm_new.tm_mon = stcRtcDate.u8Month - 1;
tm_new.tm_year = stcRtcDate.u8Year + 100;
tm_new.tm_wday = stcRtcDate.u8Weekday;
LOG_D("get rtc time.");
return timegm(&tm_new);
}
static rt_err_t hc32_rtc_set_time_stamp(time_t time_stamp)
{
stc_rtc_time_t stcRtcTime = {0};
stc_rtc_date_t stcRtcDate = {0};
struct tm *p_tm;
p_tm = gmtime(&time_stamp);
if (p_tm->tm_year < 100)
{
return -RT_ERROR;
}
stcRtcTime.u8Second = p_tm->tm_sec ;
stcRtcTime.u8Minute = p_tm->tm_min ;
stcRtcTime.u8Hour = p_tm->tm_hour;
stcRtcDate.u8Day = p_tm->tm_mday;
stcRtcDate.u8Month = p_tm->tm_mon + 1 ;
stcRtcDate.u8Year = p_tm->tm_year - 100;
stcRtcDate.u8Weekday = p_tm->tm_wday;
if (LL_OK != RTC_SetTime(RTC_DATA_FMT_DEC, &stcRtcTime))
{
return -RT_ERROR;
}
if (LL_OK != RTC_SetDate(RTC_DATA_FMT_DEC, &stcRtcDate))
{
return -RT_ERROR;
}
LOG_D("set rtc time.");
return RT_EOK;
}
static rt_err_t hc32_rtc_init(struct rt_device *dev)
{
stc_rtc_init_t stcRtcInit;
#ifdef BSP_RTC_USING_XTAL32
stc_clk_xtal32_init_t stcXtal32Init;
/* Xtal32 config */
stcXtal32Init.u8Xtal32State = CLK_XTAL32_ON;
stcXtal32Init.u8Xtal32Drv = CLK_XTAL32DRV_HIGH;
stcXtal32Init.u8Xtal32NF = CLK_XTAL32NF_PART;
(void)CLK_Xtal32Init(&stcXtal32Init);
/* Waiting for XTAL32 stabilization */
rt_thread_delay(1000);
#endif
/* Reset RTC counter */
if (LL_ERR_TIMEOUT == RTC_DeInit())
{
return -RT_ERROR;
}
else
{
/* Configure structure initialization */
(void)RTC_StructInit(&stcRtcInit);
/* Configuration RTC structure */
#ifdef BSP_RTC_USING_XTAL32
stcRtcInit.u8ClockSrc = RTC_CLK_SRC_XTAL32;
#else
stcRtcInit.u8ClockSrc = RTC_CLK_SRC_LRC;
#endif
stcRtcInit.u8HourFormat = RTC_HOUR_FMT_24H;
(void)RTC_Init(&stcRtcInit);
/* Startup RTC count */
RTC_Cmd(ENABLE);
}
return RT_EOK;
}
static rt_err_t hc32_rtc_control(rt_device_t dev, int cmd, void *args)
{
rt_err_t result = RT_EOK;
RT_ASSERT(dev != RT_NULL);
switch (cmd)
{
case RT_DEVICE_CTRL_RTC_GET_TIME:
*(rt_uint32_t *)args = hc32_rtc_get_time_stamp();
LOG_D("RTC: get rtc_time %x\n", *(rt_uint32_t *)args);
break;
case RT_DEVICE_CTRL_RTC_SET_TIME:
if (hc32_rtc_set_time_stamp(*(rt_uint32_t *)args))
{
result = -RT_ERROR;
}
LOG_D("RTC: set rtc_time %x\n", *(rt_uint32_t *)args);
break;
default:
return RT_EINVAL;
}
return result;
}
#ifdef RT_USING_DEVICE_OPS
const static struct rt_device_ops rtc_ops =
{
RT_NULL,
RT_NULL,
RT_NULL,
RT_NULL,
RT_NULL,
hc32_rtc_control
};
#endif
//static rt_err_t rt_hw_rtc_register(rt_device_t device, const char *name, rt_uint32_t flag)
//{
// RT_ASSERT(device != RT_NULL);
// if (hc32_rtc_init(device) != RT_EOK)
// {
// return -RT_ERROR;
// }
//#ifdef RT_USING_DEVICE_OPS
// device->ops = &rtc_ops;
//#else
// device->init = RT_NULL;
// device->open = RT_NULL;
// device->close = RT_NULL;
// device->read = RT_NULL;
// device->write = RT_NULL;
// device->control = hc32_rtc_control;
//#endif
// device->type = RT_Device_Class_RTC;
// device->rx_indicate = RT_NULL;
// device->tx_complete = RT_NULL;
// device->user_data = RT_NULL;
// /* register a character device */
// return rt_device_register(device, name, flag);
//}
int rt_hw_rtc_init(void)
{
// rt_err_t result;
// result = rt_hw_rtc_register(&rtc, "rtc", RT_DEVICE_FLAG_RDWR);
// if (result != RT_EOK)
// {
// LOG_E("rtc register err code: %d", result);
// return result;
// }
// LOG_D("rtc init success");
return RT_EOK;
}
INIT_DEVICE_EXPORT(rt_hw_rtc_init);
#endif /* BSP_USING_RTC */

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/*
* Copyright (C) 2022, Xiaohua Semiconductor Co., Ltd.
*
* SPDX-License-Identifier: Apache-2.0
*
* Change Logs:
* Date Author Notes
* 2022-04-28 CDT first version
*/
/*******************************************************************************
* Include files
******************************************************************************/
#include "drv_soft_i2c.h"
#include "board_config.h"
#if defined(RT_USING_I2C)
#if defined(BSP_USING_I2C1) || defined(BSP_USING_I2C2) || defined(BSP_USING_I2C3) || \
defined(BSP_USING_I2C4) || defined(BSP_USING_I2C5) || defined(BSP_USING_I2C6)
/*******************************************************************************
* Local type definitions ('typedef')
******************************************************************************/
/*******************************************************************************
* Local pre-processor symbols/macros ('#define')
******************************************************************************/
//#define DRV_DEBUG
#define LOG_TAG "drv.i2c"
#include <drv_log.h>
/*******************************************************************************
* Global variable definitions (declared in header file with 'extern')
******************************************************************************/
/*******************************************************************************
* Local function prototypes ('static')
******************************************************************************/
/*******************************************************************************
* Local variable definitions ('static')
******************************************************************************/
static const struct hc32_soft_i2c_config soft_i2c_config[] =
{
#ifdef BSP_USING_I2C1
I2C1_BUS_CONFIG,
#endif
#ifdef BSP_USING_I2C2
I2C2_BUS_CONFIG,
#endif
#ifdef BSP_USING_I2C3
I2C3_BUS_CONFIG,
#endif
#ifdef BSP_USING_I2C4
I2C4_BUS_CONFIG,
#endif
#ifdef BSP_USING_I2C5
I2C5_BUS_CONFIG,
#endif
#ifdef BSP_USING_I2C6
I2C6_BUS_CONFIG,
#endif
};
static struct hc32_i2c i2c_obj[sizeof(soft_i2c_config) / sizeof(soft_i2c_config[0])];
/*******************************************************************************
* Function implementation - global ('extern') and local ('static')
******************************************************************************/
/**
* This function initializes the i2c pin.
*
* @param Hc32 i2c dirver class.
*/
static void hc32_i2c_gpio_init(struct hc32_i2c *i2c)
{
struct hc32_soft_i2c_config *cfg = (struct hc32_soft_i2c_config *)i2c->ops.data;
rt_pin_mode(cfg->scl_pin, PIN_MODE_OUTPUT_OD);
rt_pin_mode(cfg->sda_pin, PIN_MODE_OUTPUT_OD);
rt_pin_write(cfg->scl_pin, PIN_HIGH);
rt_pin_write(cfg->sda_pin, PIN_HIGH);
}
/**
* This function sets the sda pin.
*
* @param Hc32 config class.
* @param The sda pin state.
*/
static void hc32_set_sda(void *data, rt_int32_t state)
{
struct hc32_soft_i2c_config *cfg = (struct hc32_soft_i2c_config *)data;
if (state)
{
rt_pin_write(cfg->sda_pin, PIN_HIGH);
}
else
{
rt_pin_write(cfg->sda_pin, PIN_LOW);
}
}
/**
* This function sets the scl pin.
*
* @param Hc32 config class.
* @param The scl pin state.
*/
static void hc32_set_scl(void *data, rt_int32_t state)
{
struct hc32_soft_i2c_config *cfg = (struct hc32_soft_i2c_config *)data;
if (state)
{
rt_pin_write(cfg->scl_pin, PIN_HIGH);
}
else
{
rt_pin_write(cfg->scl_pin, PIN_LOW);
}
}
/**
* This function gets the sda pin state.
*
* @param The sda pin state.
*/
static rt_int32_t hc32_get_sda(void *data)
{
struct hc32_soft_i2c_config *cfg = (struct hc32_soft_i2c_config *)data;
return rt_pin_read(cfg->sda_pin);
}
/**
* This function gets the scl pin state.
*
* @param The scl pin state.
*/
static rt_int32_t hc32_get_scl(void *data)
{
struct hc32_soft_i2c_config *cfg = (struct hc32_soft_i2c_config *)data;
return rt_pin_read(cfg->scl_pin);
}
/**
* The time delay function.
*
* @param microseconds.
*/
static void hc32_udelay(rt_uint32_t us)
{
rt_uint32_t ticks;
rt_uint32_t told, tnow, tcnt = 0;
rt_uint32_t reload = SysTick->LOAD;
ticks = us * reload / (1000000 / RT_TICK_PER_SECOND);
told = SysTick->VAL;
while (1)
{
tnow = SysTick->VAL;
if (tnow != told)
{
if (tnow < told)
{
tcnt += told - tnow;
}
else
{
tcnt += reload - tnow + told;
}
told = tnow;
if (tcnt >= ticks)
{
break;
}
}
}
}
static const struct rt_i2c_bit_ops hc32_bit_ops_default =
{
.data = RT_NULL,
.set_sda = hc32_set_sda,
.set_scl = hc32_set_scl,
.get_sda = hc32_get_sda,
.get_scl = hc32_get_scl,
.udelay = hc32_udelay,
.delay_us = 1,
.timeout = 100
};
/**
* if i2c is locked, this function will unlock it
*
* @param hc32 config class
*
* @return RT_EOK indicates successful unlock.
*/
static rt_err_t hc32_i2c_bus_unlock(const struct hc32_soft_i2c_config *cfg)
{
rt_uint32_t i = 0;
if (PIN_LOW == rt_pin_read(cfg->sda_pin))
{
while (i++ < 9)
{
rt_pin_write(cfg->scl_pin, PIN_HIGH);
hc32_udelay(100);
rt_pin_write(cfg->scl_pin, PIN_LOW);
hc32_udelay(100);
}
}
if (PIN_LOW == rt_pin_read(cfg->sda_pin))
{
return -RT_ERROR;
}
return RT_EOK;
}
/* I2C initialization function */
int hc32_hw_i2c_init(void)
{
rt_size_t obj_num = sizeof(i2c_obj) / sizeof(struct hc32_i2c);
rt_err_t result;
for (int i = 0; i < obj_num; i++)
{
i2c_obj[i].ops = hc32_bit_ops_default;
i2c_obj[i].ops.data = (void *)&soft_i2c_config[i];
i2c_obj[i].i2c_bus.priv = &i2c_obj[i].ops;
hc32_i2c_gpio_init(&i2c_obj[i]);
result = rt_i2c_bit_add_bus(&i2c_obj[i].i2c_bus, soft_i2c_config[i].bus_name);
RT_ASSERT(result == RT_EOK);
hc32_i2c_bus_unlock(&soft_i2c_config[i]);
}
return RT_EOK;
}
INIT_BOARD_EXPORT(hc32_hw_i2c_init);
#endif
#endif /* RT_USING_I2C */
/*******************************************************************************
* EOF (not truncated)
******************************************************************************/

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/*
* Copyright (C) 2022, Xiaohua Semiconductor Co., Ltd.
*
* SPDX-License-Identifier: Apache-2.0
*
* Change Logs:
* Date Author Notes
* 2022-04-28 CDT first version
*/
#ifndef __DRV_I2C_H__
#define __DRV_I2C_H__
/*******************************************************************************
* Include files
******************************************************************************/
#include <rtdevice.h>
/* C binding of definitions if building with C++ compiler */
#ifdef __cplusplus
extern "C"
{
#endif
/*******************************************************************************
* Global type definitions ('typedef')
******************************************************************************/
struct hc32_soft_i2c_config
{
rt_uint16_t scl_pin;
rt_uint16_t sda_pin;
const char *bus_name;
};
struct hc32_i2c
{
struct rt_i2c_bit_ops ops;
struct rt_i2c_bus_device i2c_bus;
};
#ifdef BSP_USING_I2C1
#define I2C1_BUS_CONFIG \
{ \
.scl_pin = BSP_I2C1_SCL_PIN, \
.sda_pin = BSP_I2C1_SDA_PIN, \
.bus_name = "i2c1", \
}
#endif
#ifdef BSP_USING_I2C2
#define I2C2_BUS_CONFIG \
{ \
.scl = BSP_I2C2_SCL_PIN, \
.sda = BSP_I2C2_SDA_PIN, \
.bus_name = "i2c2", \
}
#endif
#ifdef BSP_USING_I2C3
#define I2C3_BUS_CONFIG \
{ \
.scl = BSP_I2C3_SCL_PIN, \
.sda = BSP_I2C3_SDA_PIN, \
.bus_name = "i2c3", \
}
#endif
#ifdef BSP_USING_I2C4
#define I2C4_BUS_CONFIG \
{ \
.scl = BSP_I2C4_SCL_PIN, \
.sda = BSP_I2C4_SDA_PIN, \
.bus_name = "i2c4", \
}
#endif
#ifdef BSP_USING_I2C5
#define I2C5_BUS_CONFIG \
{ \
.scl = BSP_I2C5_SCL_PIN, \
.sda = BSP_I2C5_SDA_PIN, \
.bus_name = "i2c5", \
}
#endif
#ifdef BSP_USING_I2C6
#define I2C6_BUS_CONFIG \
{ \
.scl = BSP_I2C6_SCL_PIN, \
.sda = BSP_I2C6_SDA_PIN, \
.bus_name = "i2c6", \
}
#endif
#ifdef __cplusplus
}
#endif
#endif /* __DRV_I2C_H__ */
/*******************************************************************************
* EOF (not truncated)
******************************************************************************/

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/*
* Copyright (C) 2022, Xiaohua Semiconductor Co., Ltd.
*
* SPDX-License-Identifier: Apache-2.0
*
* Change Logs:
* Date Author Notes
* 2022-04-28 CDT first version
*/
/*******************************************************************************
* Include files
******************************************************************************/
#include <rtthread.h>
#include <rtdevice.h>
#if defined(RT_USING_SPI)
#if defined(BSP_USING_SPI1) || defined(BSP_USING_SPI2) || defined(BSP_USING_SPI3) || \
defined(BSP_USING_SPI4) || defined(BSP_USING_SPI5) || defined(BSP_USING_SPI6)
#include "drv_spi.h"
#include "board_config.h"
/*******************************************************************************
* Local type definitions ('typedef')
******************************************************************************/
/*******************************************************************************
* Local pre-processor symbols/macros ('#define')
******************************************************************************/
//#define DRV_DEBUG
#define LOG_TAG "drv.spi"
#include <drv_log.h>
/*******************************************************************************
* Global variable definitions (declared in header file with 'extern')
******************************************************************************/
extern rt_err_t rt_hw_spi_board_init(CM_SPI_TypeDef *CM_SPIx);
/*******************************************************************************
* Local function prototypes ('static')
******************************************************************************/
#if defined(BSP_USING_SPI1)
static void spi1_rx_dma_irq_handle(void);
static void spi1_tx_dma_irq_handle(void);
#endif /* BSP_USING_SPI1 */
#if defined(BSP_USING_SPI2)
static void spi2_rx_dma_irq_handle(void);
static void spi2_tx_dma_irq_handle(void);
#endif /* BSP_USING_SPI2 */
#if defined(BSP_USING_SPI3)
static void spi3_rx_dma_irq_handle(void);
static void spi3_tx_dma_irq_handle(void);
#endif /* BSP_USING_SPI3 */
#if defined(BSP_USING_SPI4)
static void spi4_rx_dma_irq_handle(void);
static void spi4_tx_dma_irq_handle(void);
#endif /* BSP_USING_SPI4 */
#if defined(BSP_USING_SPI5)
static void spi5_rx_dma_irq_handle(void);
static void spi5_tx_dma_irq_handle(void);
#endif /* BSP_USING_SPI5 */
#if defined(BSP_USING_SPI6)
static void spi6_rx_dma_irq_handle(void);
static void spi6_tx_dma_irq_handle(void);
#endif /* BSP_USING_SPI6 */
/*******************************************************************************
* Local variable definitions ('static')
******************************************************************************/
enum
{
#ifdef BSP_USING_SPI1
SPI1_INDEX,
#endif
#ifdef BSP_USING_SPI2
SPI2_INDEX,
#endif
#ifdef BSP_USING_SPI3
SPI3_INDEX,
#endif
#ifdef BSP_USING_SPI4
SPI4_INDEX,
#endif
#ifdef BSP_USING_SPI5
SPI5_INDEX,
#endif
#ifdef BSP_USING_SPI6
SPI6_INDEX,
#endif
};
static struct hc32_spi_config spi_config[] =
{
#ifdef BSP_USING_SPI1
SPI1_BUS_CONFIG,
#endif
#ifdef BSP_USING_SPI2
SPI2_BUS_CONFIG,
#endif
#ifdef BSP_USING_SPI3
SPI3_BUS_CONFIG,
#endif
#ifdef BSP_USING_SPI4
SPI4_BUS_CONFIG,
#endif
#ifdef BSP_USING_SPI5
SPI5_BUS_CONFIG,
#endif
#ifdef BSP_USING_SPI6
SPI6_BUS_CONFIG,
#endif
};
static struct hc32_spi spi_bus_obj[sizeof(spi_config) / sizeof(spi_config[0])] = {0};
/*******************************************************************************
* Function implementation - global ('extern') and local ('static')
******************************************************************************/
static rt_err_t hc32_spi_init(struct hc32_spi *spi_drv, struct rt_spi_configuration *cfg)
{
RT_ASSERT(spi_drv != RT_NULL);
RT_ASSERT(cfg != RT_NULL);
stc_spi_init_t stcSpiInit;
stc_clock_freq_t stcClkFreq;
CM_SPI_TypeDef *spi_instance = spi_drv->config->Instance;
/* Enable spi clock */
FCG_Fcg1PeriphClockCmd(spi_drv->config->clock, ENABLE);
/* Init spi struct as default value */
SPI_StructInit(&stcSpiInit);
/* Slave or master mode */
if (cfg->mode & RT_SPI_SLAVE)
{
stcSpiInit.u32MasterSlave = SPI_SLAVE;
}
else
{
stcSpiInit.u32MasterSlave = SPI_MASTER;
}
/* SI/SO pin shared */
if (cfg->mode & RT_SPI_3WIRE)
{
return RT_EINVAL;
}
else
{
stcSpiInit.u32TransMode = SPI_FULL_DUPLEX;
}
/* clock phase & polarity */
if (RT_SPI_MODE_3 == (cfg->mode & RT_SPI_MODE_3))
{
stcSpiInit.u32SpiMode = SPI_MD_3;
}
else if (RT_SPI_MODE_2 == (cfg->mode & RT_SPI_MODE_3))
{
stcSpiInit.u32SpiMode = SPI_MD_2;
}
else if (RT_SPI_MODE_1 == (cfg->mode & RT_SPI_MODE_3))
{
stcSpiInit.u32SpiMode = SPI_MD_1;
}
else
{
stcSpiInit.u32SpiMode = SPI_MD_0;
}
/* No chipselect */
if (cfg->mode & RT_SPI_NO_CS)
{
stcSpiInit.u32WireMode = SPI_4_WIRE;
}
else
{
stcSpiInit.u32WireMode = SPI_3_WIRE;
}
/* LSB or MSB */
if (cfg->mode & RT_SPI_MSB)
{
stcSpiInit.u32FirstBit = SPI_FIRST_MSB;
}
else
{
stcSpiInit.u32FirstBit = SPI_FIRST_LSB;
}
/* config data width 8,16,32 */
if (8 == cfg->data_width)
{
stcSpiInit.u32DataBits = SPI_DATA_SIZE_8BIT;
}
else if (16 == cfg->data_width)
{
stcSpiInit.u32DataBits = SPI_DATA_SIZE_16BIT;
}
else if (32 == cfg->data_width)
{
stcSpiInit.u32DataBits = SPI_DATA_SIZE_32BIT;
}
else
{
return RT_EIO;
}
/* Get BUS clock */
CLK_GetClockFreq(&stcClkFreq);
if (cfg->max_hz >= stcClkFreq.u32Pclk1Freq / 2)
{
stcSpiInit.u32BaudRatePrescaler = SPI_BR_CLK_DIV2;
}
else if (cfg->max_hz >= stcClkFreq.u32Pclk1Freq / 4)
{
stcSpiInit.u32BaudRatePrescaler = SPI_BR_CLK_DIV4;
}
else if (cfg->max_hz >= stcClkFreq.u32Pclk1Freq / 8)
{
stcSpiInit.u32BaudRatePrescaler = SPI_BR_CLK_DIV8;
}
else if (cfg->max_hz >= stcClkFreq.u32Pclk1Freq / 16)
{
stcSpiInit.u32BaudRatePrescaler = SPI_BR_CLK_DIV16;
}
else if (cfg->max_hz >= stcClkFreq.u32Pclk1Freq / 32)
{
stcSpiInit.u32BaudRatePrescaler = SPI_BR_CLK_DIV32;
}
else if (cfg->max_hz >= stcClkFreq.u32Pclk1Freq / 64)
{
stcSpiInit.u32BaudRatePrescaler = SPI_BR_CLK_DIV64;
}
else if (cfg->max_hz >= stcClkFreq.u32Pclk1Freq / 128)
{
stcSpiInit.u32BaudRatePrescaler = SPI_BR_CLK_DIV128;
}
else
{
stcSpiInit.u32BaudRatePrescaler = SPI_BR_CLK_DIV256;
}
if ((cfg->mode & RT_SPI_SLAVE) && (stcSpiInit.u32BaudRatePrescaler < SPI_BR_CLK_DIV8))
{
stcSpiInit.u32BaudRatePrescaler = SPI_BR_CLK_DIV8;
}
LOG_D("sys freq: %d, SPI freq: %d, BaudRatePrescaler: %d", stcClkFreq.u32HclkFreq, cfg->max_hz, stcSpiInit.u32BaudRatePrescaler);
/* spi port init */
rt_hw_spi_board_init(spi_instance);
if (LL_OK != SPI_Init(spi_instance, &stcSpiInit))
{
return RT_EIO;
}
/* DMA configuration */
if (spi_drv->spi_dma_flag & RT_DEVICE_FLAG_DMA_RX)
{
struct dma_config *spi_dma;
stc_dma_init_t stcDmaInit;
/* Get spi dma_rx */
spi_dma = spi_drv->config->dma_rx;
/* Enable Dma clock */
FCG_Fcg0PeriphClockCmd(spi_dma->clock, ENABLE);
AOS_SetTriggerEventSrc(spi_dma->trigger_select, spi_dma->trigger_event);
/* Config Dma */
DMA_StructInit(&stcDmaInit);
stcDmaInit.u32IntEn = DMA_INT_ENABLE;
stcDmaInit.u32BlockSize = 1UL;
stcDmaInit.u32TransCount = 0;
stcDmaInit.u32DestAddr = 0;
stcDmaInit.u32SrcAddr = (uint32_t)(&spi_instance->DR);
stcDmaInit.u32SrcAddrInc = DMA_SRC_ADDR_FIX;
stcDmaInit.u32DestAddrInc = DMA_DEST_ADDR_INC;
if (8 == cfg->data_width)
{
stcDmaInit.u32DataWidth = DMA_DATAWIDTH_8BIT;
}
else if (16 == cfg->data_width)
{
stcDmaInit.u32DataWidth = DMA_DATAWIDTH_16BIT;
}
else
{
stcDmaInit.u32DataWidth = DMA_DATAWIDTH_32BIT;
}
/* Init Dma */
if (LL_OK != DMA_Init(spi_dma->Instance, spi_dma->channel, &stcDmaInit))
{
return RT_EIO;
}
NVIC_EnableIRQ(spi_dma->irq_config.irq_num);
/* Enable Dma */
DMA_Cmd(spi_dma->Instance, ENABLE);
}
if (spi_drv->spi_dma_flag & RT_DEVICE_FLAG_DMA_TX)
{
struct dma_config *spi_dma;
stc_dma_init_t stcDmaInit;
/* Get spi dma_tx */
spi_dma = spi_drv->config->dma_tx;
FCG_Fcg0PeriphClockCmd(spi_dma->clock, ENABLE);
AOS_SetTriggerEventSrc(spi_dma->trigger_select, spi_dma->trigger_event);
/* Config Dma */
DMA_StructInit(&stcDmaInit);
stcDmaInit.u32IntEn = DMA_INT_ENABLE;
stcDmaInit.u32BlockSize = 1UL;
stcDmaInit.u32TransCount = 0;
stcDmaInit.u32DestAddr = (uint32_t)(&spi_instance->DR);;
stcDmaInit.u32SrcAddr = 0;
stcDmaInit.u32SrcAddrInc = DMA_SRC_ADDR_INC;
stcDmaInit.u32DestAddrInc = DMA_DEST_ADDR_FIX;
if (8 == cfg->data_width)
{
stcDmaInit.u32DataWidth = DMA_DATAWIDTH_8BIT;
}
else if (16 == cfg->data_width)
{
stcDmaInit.u32DataWidth = DMA_DATAWIDTH_16BIT;
}
else
{
stcDmaInit.u32DataWidth = DMA_DATAWIDTH_32BIT;
}
/* Init Dma */
if (LL_OK != DMA_Init(spi_dma->Instance, spi_dma->channel, &stcDmaInit))
{
return RT_EIO;
}
NVIC_EnableIRQ(spi_dma->irq_config.irq_num);
/* Enable Dma */
DMA_Cmd(spi_dma->Instance, ENABLE);
}
LOG_D("%s init done", spi_drv->config->bus_name);
return RT_EOK;
}
static rt_err_t hc32_spi_configure(struct rt_spi_device *device,
struct rt_spi_configuration *configuration)
{
RT_ASSERT(device != RT_NULL);
RT_ASSERT(configuration != RT_NULL);
struct hc32_spi *spi_drv = rt_container_of(device->bus, struct hc32_spi, spi_bus);
spi_drv->cfg = configuration;
return hc32_spi_init(spi_drv, configuration);
}
static int32_t hc32_spi_dma_trans(struct hc32_spi_config *spi_config, const uint8_t *pvTxBuf, void *pvRxBuf, uint32_t u32Length)
{
if ((spi_config == RT_NULL) || (pvTxBuf == RT_NULL) || (pvRxBuf == RT_NULL))
{
return LL_ERR;
}
SPI_Cmd(spi_config->Instance, DISABLE);
if (RT_NULL == pvTxBuf)
{
DMA_SetSrcAddr(spi_config->dma_tx->Instance, spi_config->dma_tx->channel, (uint32_t)pvTxBuf);
DMA_SetTransCount(spi_config->dma_tx->Instance, spi_config->dma_tx->channel, u32Length);
DMA_ChCmd(spi_config->dma_tx->Instance, spi_config->dma_tx->channel, ENABLE);
}
if (RT_NULL == pvRxBuf)
{
DMA_SetDestAddr(spi_config->dma_rx->Instance, spi_config->dma_rx->channel, (uint32_t)pvRxBuf);
DMA_SetTransCount(spi_config->dma_rx->Instance, spi_config->dma_rx->channel, u32Length);
DMA_ChCmd(spi_config->dma_rx->Instance, spi_config->dma_rx->channel, ENABLE);
}
SPI_Cmd(spi_config->Instance, ENABLE);
return LL_OK;
}
static void hc32_spi_enable(CM_SPI_TypeDef *SPIx)
{
/* Check if the SPI is already enabled */
if ((SPIx->CR1 & SPI_CR1_SPE) != SPI_CR1_SPE)
{
SPI_Cmd(SPIx, ENABLE);
}
}
static rt_uint32_t hc32_spi_xfer(struct rt_spi_device *device, struct rt_spi_message *message)
{
int32_t state;
rt_size_t message_length, already_send_length;
rt_uint16_t send_length;
rt_uint8_t *recv_buf;
const rt_uint8_t *send_buf;
RT_ASSERT(device != RT_NULL);
RT_ASSERT(device->bus != RT_NULL);
RT_ASSERT(device->bus->parent.user_data != RT_NULL);
RT_ASSERT(message != RT_NULL);
struct hc32_spi *spi_drv = rt_container_of(device->bus, struct hc32_spi, spi_bus);
CM_SPI_TypeDef *spi_instance = spi_drv->config->Instance;
struct hc32_hw_spi_cs *cs = device->parent.user_data;
if (message->cs_take && !(device->config.mode & RT_SPI_NO_CS))
{
if (device->config.mode & RT_SPI_CS_HIGH)
{
GPIO_SetPins(cs->port, cs->pin);
}
else
{
GPIO_ResetPins(cs->port, cs->pin);
}
}
LOG_D("%s sendbuf: %X, recvbuf: %X, length: %d", spi_drv->config->bus_name,
(uint32_t)message->send_buf, (uint32_t)message->recv_buf, message->length);
message_length = message->length;
recv_buf = message->recv_buf;
send_buf = message->send_buf;
while (message_length)
{
if (message_length > 65535)
{
send_length = 65535;
message_length = message_length - 65535;
}
else
{
send_length = message_length;
message_length = 0;
}
/* calculate the start address */
already_send_length = message->length - send_length - message_length;
send_buf = (rt_uint8_t *)message->send_buf + already_send_length;
recv_buf = (rt_uint8_t *)message->recv_buf + already_send_length;
if (message->send_buf && message->recv_buf)
{
if ((spi_drv->spi_dma_flag & RT_DEVICE_FLAG_DMA_TX) && (spi_drv->spi_dma_flag & RT_DEVICE_FLAG_DMA_RX))
{
state = hc32_spi_dma_trans(spi_drv->config, send_buf, recv_buf, send_length);
}
else
{
hc32_spi_enable(spi_instance);
state = SPI_TransReceive(spi_instance, send_buf, recv_buf, send_length, 1000);
}
}
else if (message->send_buf)
{
if (spi_drv->spi_dma_flag & RT_DEVICE_FLAG_DMA_TX)
{
/* Maybe need to switch to send only mode */
state = hc32_spi_dma_trans(spi_drv->config, send_buf, RT_NULL, send_length);
}
else
{
hc32_spi_enable(spi_instance);
state = SPI_Trans(spi_instance, send_buf, send_length, 1000);
}
}
else
{
rt_memset((uint8_t *)recv_buf, 0xFF, send_length);
if (spi_drv->spi_dma_flag & RT_DEVICE_FLAG_DMA_RX)
{
state = hc32_spi_dma_trans(spi_drv->config, recv_buf, recv_buf, send_length);
}
else
{
hc32_spi_enable(spi_instance);
state = SPI_Receive(spi_instance, recv_buf, send_length, 1000);
}
}
if (state != LL_OK)
{
LOG_I("spi transfer error : %d", state);
message->length = 0;
}
/* Wait for the spi transfer complete */
while (RESET != SPI_GetStatus(spi_instance, SPI_FLAG_IDLE));
}
/* clear error flag */
SPI_ClearStatus(spi_instance, SPI_FLAG_CLR_ALL | SPI_FLAG_RX_BUF_FULL);
if (message->cs_release && !(device->config.mode & RT_SPI_NO_CS))
{
if (device->config.mode & RT_SPI_CS_HIGH)
{
GPIO_ResetPins(cs->port, cs->pin);
}
else
{
GPIO_SetPins(cs->port, cs->pin);
}
}
return message->length;
}
static const struct rt_spi_ops hc32_spi_ops =
{
.configure = hc32_spi_configure,
.xfer = hc32_spi_xfer,
};
/**
* Attach the spi device to SPI bus, this function must be used after initialization.
*/
rt_err_t rt_hw_spi_device_attach(const char *bus_name, const char *device_name, uint8_t cs_gpio_port, uint16_t cs_gpio_pin)
{
RT_ASSERT(bus_name != RT_NULL);
RT_ASSERT(device_name != RT_NULL);
rt_err_t result;
struct rt_spi_device *spi_device;
struct hc32_hw_spi_cs *cs_pin;
stc_gpio_init_t stcGpioInit;
GPIO_StructInit(&stcGpioInit);
stcGpioInit.u16PinState = PIN_STAT_SET;
stcGpioInit.u16PinDir = PIN_DIR_OUT;
stcGpioInit.u16PullUp = PIN_PU_ON;
GPIO_Init(cs_gpio_port, cs_gpio_pin, &stcGpioInit);
/* attach the device to spi bus*/
spi_device = (struct rt_spi_device *)rt_malloc(sizeof(struct rt_spi_device));
RT_ASSERT(spi_device != RT_NULL);
cs_pin = (struct hc32_hw_spi_cs *)rt_malloc(sizeof(struct hc32_hw_spi_cs));
RT_ASSERT(cs_pin != RT_NULL);
cs_pin->port = cs_gpio_port;
cs_pin->pin = cs_gpio_pin;
result = rt_spi_bus_attach_device(spi_device, device_name, bus_name, (void *)cs_pin);
if (result != RT_EOK)
{
LOG_E("%s attach to %s faild, %d\n", device_name, bus_name, result);
}
return result;
}
/**
* @brief Clear DMA transfer complete flag.
* @param dma specific dam witch spi used.
* @retval None
*/
static void hc32_dma_irq_handle(struct dma_config *dma)
{
DMA_ClearTransCompleteStatus(dma->Instance, (1U << dma->channel));
}
#if defined(BSP_USING_SPI1) && defined(BSP_SPI1_RX_USING_DMA)
/**
* @brief This function handles DMA Rx complete interrupt request.
* @param None
* @retval None
*/
static void spi1_rx_dma_irq_handle(void)
{
/* enter interrupt */
rt_interrupt_enter();
hc32_dma_irq_handle(spi_config[SPI1_INDEX].dma_rx);
/* leave interrupt */
rt_interrupt_leave();
}
#endif
#if defined(BSP_USING_SPI1) && defined(BSP_SPI1_TX_USING_DMA)
/**
* @brief This function handles DMA Tx complete interrupt request.
* @param None
* @retval None
*/
static void spi1_tx_dma_irq_handle(void)
{
/* enter interrupt */
rt_interrupt_enter();
hc32_dma_irq_handle(spi_config[SPI1_INDEX].dma_tx);
/* leave interrupt */
rt_interrupt_leave();
}
#endif
#if defined(BSP_USING_SPI2) && defined(BSP_SPI2_RX_USING_DMA)
/**
* @brief This function handles DMA Rx complete interrupt request.
* @param None
* @retval None
*/
static void spi2_rx_dma_irq_handle(void)
{
/* enter interrupt */
rt_interrupt_enter();
hc32_dma_irq_handle(spi_config[SPI2_INDEX].dma_rx);
/* leave interrupt */
rt_interrupt_leave();
}
#endif
#if defined(BSP_USING_SPI2) && defined(BSP_SPI2_TX_USING_DMA)
/**
* @brief This function handles DMA Tx complete interrupt request.
* @param None
* @retval None
*/
static void spi2_tx_dma_irq_handle(void)
{
/* enter interrupt */
rt_interrupt_enter();
hc32_dma_irq_handle(spi_config[SPI2_INDEX].dma_tx);
/* leave interrupt */
rt_interrupt_leave();
}
#endif
#if defined(BSP_USING_SPI3) && defined(BSP_SPI3_RX_USING_DMA)
/**
* @brief This function handles DMA Rx complete interrupt request.
* @param None
* @retval None
*/
static void spi3_rx_dma_irq_handle(void)
{
/* enter interrupt */
rt_interrupt_enter();
hc32_dma_irq_handle(spi_config[SPI3_INDEX].dma_rx);
/* leave interrupt */
rt_interrupt_leave();
}
#endif
#if defined(BSP_USING_SPI3) && defined(BSP_SPI3_TX_USING_DMA)
/**
* @brief This function handles DMA Tx complete interrupt request.
* @param None
* @retval None
*/
static void spi3_tx_dma_irq_handle(void)
{
/* enter interrupt */
rt_interrupt_enter();
hc32_dma_irq_handle(spi_config[SPI3_INDEX].dma_tx);
/* leave interrupt */
rt_interrupt_leave();
}
#endif
#if defined(BSP_USING_SPI4) && defined(BSP_SPI4_RX_USING_DMA)
/**
* @brief This function handles DMA Rx complete interrupt request.
* @param None
* @retval None
*/
static void spi4_rx_dma_irq_handle(void)
{
/* enter interrupt */
rt_interrupt_enter();
hc32_dma_irq_handle(spi_config[SPI4_INDEX].dma_rx);
/* leave interrupt */
rt_interrupt_leave();
}
#endif
#if defined(BSP_USING_SPI4) && defined(BSP_SPI4_TX_USING_DMA)
/**
* @brief This function handles DMA Tx complete interrupt request.
* @param None
* @retval None
*/
static void spi4_tx_dma_irq_handle(void)
{
/* enter interrupt */
rt_interrupt_enter();
hc32_dma_irq_handle(spi_config[SPI4_INDEX].dma_tx);
/* leave interrupt */
rt_interrupt_leave();
}
#endif
#if defined(BSP_USING_SPI5) && defined(BSP_SPI5_RX_USING_DMA)
/**
* @brief This function handles DMA Rx complete interrupt request.
* @param None
* @retval None
*/
static void spi5_rx_dma_irq_handle(void)
{
/* enter interrupt */
rt_interrupt_enter();
hc32_dma_irq_handle(spi_config[SPI5_INDEX].dma_rx);
/* leave interrupt */
rt_interrupt_leave();
}
#endif
#if defined(BSP_USING_SPI5) && defined(BSP_SPI5_TX_USING_DMA)
/**
* @brief This function handles DMA Tx complete interrupt request.
* @param None
* @retval None
*/
static void spi5_tx_dma_irq_handle(void)
{
/* enter interrupt */
rt_interrupt_enter();
hc32_dma_irq_handle(spi_config[SPI5_INDEX].dma_tx);
/* leave interrupt */
rt_interrupt_leave();
}
#endif
#if defined(BSP_USING_SPI6) && defined(BSP_SPI6_RX_USING_DMA)
/**
* @brief This function handles DMA Rx complete interrupt request.
* @param None
* @retval None
*/
static void spi6_rx_dma_irq_handle(void)
{
/* enter interrupt */
rt_interrupt_enter();
hc32_dma_irq_handle(spi_config[SPI6_INDEX].dma_rx);
/* leave interrupt */
rt_interrupt_leave();
}
#endif
#if defined(BSP_USING_SPI6) && defined(BSP_SPI6_TX_USING_DMA)
/**
* @brief This function handles DMA Tx complete interrupt request.
* @param None
* @retval None
*/
static void spi6_tx_dma_irq_handle(void)
{
/* enter interrupt */
rt_interrupt_enter();
hc32_dma_irq_handle(spi_config[SPI6_INDEX].dma_tx);
/* leave interrupt */
rt_interrupt_leave();
}
#endif
/**
* @brief This function gets dma witch spi used infomation include unit,
* channel, interrupt etc.
* @param None
* @retval None
*/
static void hc32_get_dma_info(void)
{
#ifdef BSP_SPI1_RX_USING_DMA
spi_bus_obj[SPI1_INDEX].spi_dma_flag |= RT_DEVICE_FLAG_DMA_RX;
static struct dma_config spi1_dma_rx = SPI1_RX_DMA_CONFIG;
spi1_dma_rx.irq_callback = spi1_rx_dma_irq_handle;
spi_config[SPI1_INDEX].dma_rx = &spi1_dma_rx;
#endif
#ifdef BSP_SPI1_TX_USING_DMA
spi_bus_obj[SPI1_INDEX].spi_dma_flag |= RT_DEVICE_FLAG_DMA_TX;
static struct dma_config spi1_dma_tx = SPI1_TX_DMA_CONFIG;
spi1_dma_tx.irq_callback = spi1_tx_dma_irq_handle;
spi_config[SPI1_INDEX].dma_tx = &spi1_dma_tx;
#endif
#ifdef BSP_SPI2_RX_USING_DMA
spi_bus_obj[SPI2_INDEX].spi_dma_flag |= RT_DEVICE_FLAG_DMA_RX;
static struct dma_config spi2_dma_rx = SPI2_RX_DMA_CONFIG;
spi2_dma_rx.irq_callback = spi2_rx_dma_irq_handle;
spi_config[SPI2_INDEX].dma_rx = &spi2_dma_rx;
#endif
#ifdef BSP_SPI2_TX_USING_DMA
spi_bus_obj[SPI2_INDEX].spi_dma_flag |= RT_DEVICE_FLAG_DMA_TX;
static struct dma_config spi2_dma_tx = SPI2_TX_DMA_CONFIG;
spi2_dma_tx.irq_callback = spi2_tx_dma_irq_handle;
spi_config[SPI2_INDEX].dma_tx = &spi2_dma_tx;
#endif
#ifdef BSP_SPI3_RX_USING_DMA
spi_bus_obj[SPI3_INDEX].spi_dma_flag |= RT_DEVICE_FLAG_DMA_RX;
static struct dma_config spi3_dma_rx = SPI3_RX_DMA_CONFIG;
spi3_dma_rx.irq_callback = spi3_rx_dma_irq_handle;
spi_config[SPI3_INDEX].dma_rx = &spi3_dma_rx;
#endif
#ifdef BSP_SPI3_TX_USING_DMA
spi_bus_obj[SPI3_INDEX].spi_dma_flag |= RT_DEVICE_FLAG_DMA_TX;
static struct dma_config spi3_dma_tx = SPI3_TX_DMA_CONFIG;
spi3_dma_tx.irq_callback = spi3_tx_dma_irq_handle;
spi_config[SPI3_INDEX].dma_tx = &spi3_dma_tx;
#endif
#ifdef BSP_SPI4_RX_USING_DMA
spi_bus_obj[SPI4_INDEX].spi_dma_flag |= RT_DEVICE_FLAG_DMA_RX;
static struct dma_config spi4_dma_rx = SPI4_RX_DMA_CONFIG;
spi4_dma_rx.irq_callback = spi4_rx_dma_irq_handle;
spi_config[SPI4_INDEX].dma_rx = &spi4_dma_rx;
#endif
#ifdef BSP_SPI4_TX_USING_DMA
spi_bus_obj[SPI4_INDEX].spi_dma_flag |= RT_DEVICE_FLAG_DMA_TX;
static struct dma_config spi4_dma_tx = SPI4_TX_DMA_CONFIG;
spi4_dma_tx.irq_callback = spi4_tx_dma_irq_handle;
spi_config[SPI4_INDEX].dma_tx = &spi4_dma_tx;
#endif
#ifdef BSP_SPI5_RX_USING_DMA
spi_bus_obj[SPI5_INDEX].spi_dma_flag |= RT_DEVICE_FLAG_DMA_RX;
static struct dma_config spi5_dma_rx = SPI5_RX_DMA_CONFIG;
spi5_dma_rx.irq_callback = spi5_rx_dma_irq_handle;
spi_config[SPI5_INDEX].dma_rx = &spi5_dma_rx;
#endif
#ifdef BSP_SPI5_TX_USING_DMA
spi_bus_obj[SPI5_INDEX].spi_dma_flag |= RT_DEVICE_FLAG_DMA_TX;
static struct dma_config spi5_dma_tx = SPI5_TX_DMA_CONFIG;
spi5_dma_tx.irq_callback = spi5_tx_dma_irq_handle;
spi_config[SPI5_INDEX].dma_tx = &spi5_dma_tx;
#endif
#ifdef BSP_SPI6_RX_USING_DMA
spi_bus_obj[SPI6_INDEX].spi_dma_flag |= RT_DEVICE_FLAG_DMA_RX;
static struct dma_config spi6_dma_rx = SPI6_RX_DMA_CONFIG;
spi6_dma_rx.irq_callback = spi6_rx_dma_irq_handle;
spi_config[SPI6_INDEX].dma_rx = &spi6_dma_rx;
#endif
#ifdef BSP_SPI6_TX_USING_DMA
spi_bus_obj[SPI6_INDEX].spi_dma_flag |= RT_DEVICE_FLAG_DMA_TX;
static struct dma_config spi6_dma_tx = SPI6_TX_DMA_CONFIG;
spi6_dma_tx.irq_callback = spi6_tx_dma_irq_handle;
spi_config[SPI6_INDEX].dma_tx = &spi6_dma_tx;
#endif
}
static int hc32_hw_spi_bus_init(void)
{
rt_err_t result;
for (int i = 0; i < sizeof(spi_config) / sizeof(spi_config[0]); i++)
{
spi_bus_obj[i].config = &spi_config[i];
spi_bus_obj[i].spi_bus.parent.user_data = &spi_config[i];
if (spi_bus_obj[i].spi_dma_flag & RT_DEVICE_FLAG_DMA_RX)
{
/* Configure the DMA handler */
hc32_install_irq_handler(&spi_config[i].dma_rx->irq_config, spi_config[i].dma_rx->irq_callback, RT_FALSE);
}
if (spi_bus_obj[i].spi_dma_flag & RT_DEVICE_FLAG_DMA_TX)
{
/* Configure the DMA handler */
hc32_install_irq_handler(&spi_config[i].dma_tx->irq_config, spi_config[i].dma_tx->irq_callback, RT_FALSE);
}
result = rt_spi_bus_register(&spi_bus_obj[i].spi_bus, spi_config[i].bus_name, &hc32_spi_ops);
LOG_D("%s bus init done", spi_config[i].bus_name);
}
return result;
}
int hc32_hw_spi_init(void)
{
hc32_get_dma_info();
return hc32_hw_spi_bus_init();
}
INIT_BOARD_EXPORT(hc32_hw_spi_init);
#endif
#endif /* BSP_USING_SPI */

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/*
* Copyright (C) 2022, Xiaohua Semiconductor Co., Ltd.
*
* SPDX-License-Identifier: Apache-2.0
*
* Change Logs:
* Date Author Notes
* 2022-04-28 CDT first version
*/
#ifndef __DRV_SPI_H__
#define __DRV_SPI_H__
/*******************************************************************************
* Include files
******************************************************************************/
#include <rtthread.h>
#include "rtdevice.h"
#include "drv_dma.h"
#include "drv_irq.h"
#ifdef __cplusplus
extern "C" {
#endif
struct hc32_hw_spi_cs
{
rt_uint8_t port;
rt_uint16_t pin;
};
struct hc32_spi_config
{
CM_SPI_TypeDef *Instance;
char *bus_name;
rt_uint32_t clock;
// struct hc32_irq_config irq_config;
struct dma_config *dma_rx;
struct dma_config *dma_tx;
};
struct hc32_spi
{
struct hc32_spi_config *config;
struct rt_spi_configuration *cfg;
struct rt_spi_bus spi_bus;
rt_uint8_t spi_dma_flag;
};
rt_err_t rt_hw_spi_device_attach(const char *bus_name, const char *device_name, uint8_t cs_gpio_port, uint16_t cs_gpio_pin);
#ifdef __cplusplus
}
#endif
#endif /* __DRV_SPI_H__ */

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bsp/hc32/libraries/hc32_drivers/drv_usart.c Normal file
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bsp/hc32/libraries/hc32_drivers/drv_usart.h Normal file
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/*
* Copyright (C) 2022, Xiaohua Semiconductor Co., Ltd.
*
* SPDX-License-Identifier: Apache-2.0
*
* Change Logs:
* Date Author Notes
* 2022-04-28 CDT first version
*/
#ifndef __DRV_USART_H__
#define __DRV_USART_H__
/*******************************************************************************
* Include files
******************************************************************************/
#include <rtthread.h>
#include "rtdevice.h"
#include "drv_irq.h"
#include "drv_dma.h"
/* C binding of definitions if building with C++ compiler */
#ifdef __cplusplus
extern "C"
{
#endif
/*******************************************************************************
* Global type definitions ('typedef')
******************************************************************************/
struct hc32_uart_irq_config
{
struct hc32_irq_config irq_config;
func_ptr_t irq_callback;
};
/* HC32 config Rx timeout */
struct hc32_uart_rxto
{
CM_TMR0_TypeDef *TMR0_Instance;
rt_uint32_t channel;
rt_uint32_t clock;
rt_size_t timeout_bits;
struct hc32_irq_config irq_config;
func_ptr_t irq_callback;
};
/* HC32 config uart class */
struct hc32_uart_config
{
const char *name;
CM_USART_TypeDef *Instance;
rt_uint32_t clock;
struct hc32_uart_irq_config rxerr_irq;
struct hc32_uart_irq_config rx_irq;
struct hc32_uart_irq_config tx_irq;
#ifdef RT_SERIAL_USING_DMA
struct hc32_uart_rxto *rx_timeout;
struct dma_config *dma_rx;
struct hc32_uart_irq_config *tc_irq;
struct dma_config *dma_tx;
#endif
};
/* HC32 uart dirver class */
struct hc32_uart
{
struct hc32_uart_config *config;
#ifdef RT_SERIAL_USING_DMA
rt_size_t dma_rx_last_index;
#endif
rt_uint16_t uart_dma_flag;
struct rt_serial_device serial;
};
/*******************************************************************************
* Global pre-processor symbols/macros ('#define')
******************************************************************************/
/*******************************************************************************
* Global variable definitions ('extern')
******************************************************************************/
/*******************************************************************************
* Global function prototypes (definition in C source)
******************************************************************************/
#ifdef __cplusplus
}
#endif
#endif /* __DRV_USART_H__ */
/*******************************************************************************
* EOF (not truncated)
******************************************************************************/

29
bsp/hc32/libraries/hc32f4a0_ddl/LICENSE Normal file
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BSD 3-Clause License
Copyright (c) 2022, Xiaohua Semiconductor Co., Ltd. ("XHSC")
All rights reserved.
Redistribution and use in source and binary forms, with or without
modification, are permitted provided that the following conditions are met:
* Redistributions of source code must retain the above copyright notice, this
list of conditions and the following disclaimer.
* Redistributions in binary form must reproduce the above copyright notice,
this list of conditions and the following disclaimer in the documentation
and/or other materials provided with the distribution.
* Neither the name of the copyright holder nor the names of its
contributors may be used to endorse or promote products derived from
this software without specific prior written permission.
THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.

4
bsp/hc32/libraries/hc32f4a0_ddl/README.txt Normal file
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version date comment
2.0.0
Mar 31, 2022 Initial release.
EOF

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bsp/hc32/libraries/hc32f4a0_ddl/SConscript Normal file
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import rtconfig
from building import *
# get current directory
cwd = GetCurrentDir()
# The set of source files associated with this SConscript file.
src = Split('''
drivers/cmsis/Device/HDSC/hc32f4xx/Source/system_hc32f4a0.c
drivers/hc32_ll_driver/src/hc32_ll.c
drivers/hc32_ll_driver/src/hc32_ll_aos.c
drivers/hc32_ll_driver/src/hc32_ll_clk.c
drivers/hc32_ll_driver/src/hc32_ll_dma.c
drivers/hc32_ll_driver/src/hc32_ll_efm.c
drivers/hc32_ll_driver/src/hc32_ll_fcg.c
drivers/hc32_ll_driver/src/hc32_ll_gpio.c
drivers/hc32_ll_driver/src/hc32_ll_icg.c
drivers/hc32_ll_driver/src/hc32_ll_interrupts.c
drivers/hc32_ll_driver/src/hc32_ll_pwc.c
drivers/hc32_ll_driver/src/hc32_ll_rmu.c
drivers/hc32_ll_driver/src/hc32_ll_sram.c
drivers/hc32_ll_driver/src/hc32_ll_utility.c
drivers/hc32_ll_driver/src/hc32f4a0_ll_interrupts_share.c
''')
if GetDepend(['RT_USING_SERIAL']):
src += ['drivers/hc32_ll_driver/src/hc32_ll_usart.c']
src += ['drivers/hc32_ll_driver/src/hc32_ll_tmr0.c']
if GetDepend(['RT_USING_I2C']):
src += ['drivers/hc32_ll_driver/src/hc32_ll_i2c.c']
if GetDepend(['RT_USING_SPI']):
src += ['drivers/hc32_ll_driver/src/hc32_ll_spi.c']
if GetDepend(['RT_USING_CAN']):
src += ['drivers/hc32_ll_driver/src/hc32_ll_can.c']
if GetDepend(['BSP_USING_ETH']):
src += ['drivers/hc32_ll_driver/src/hc32_ll_eth.c']
if GetDepend(['RT_USING_ADC']):
src += ['drivers/hc32_ll_driver/src/hc32_ll_adc.c']
if GetDepend(['RT_USING_DAC']):
src += ['drivers/hc32_ll_driver/src/hc32_ll_dac.c']
if GetDepend(['RT_USING_RTC']):
src += ['drivers/hc32_ll_driver/src/hc32_ll_rtc.c']
if GetDepend(['RT_USING_WDT']):
src += ['drivers/hc32_ll_driver/src/hc32_ll_swdt.c']
src += ['drivers/hc32_ll_driver/src/hc32_ll_wdt.c']
if GetDepend(['RT_USING_SDIO']):
src += ['drivers/hc32_ll_driver/src/hc32_ll_sdioc.c']
if GetDepend(['RT_USING_ON_CHIP_FLASH']):
src += ['drivers/hc32_ll_driver/src/hc32_ll_efm.c']
if GetDepend(['RT_USING_HWTIMER']) or GetDepend(['RT_USING_PWM'] or GetDepend(['RT_USING_PULSE_ENCODER'])):
src += ['drivers/hc32_ll_driver/src/hc32_ll_tmra.c']
path = [
cwd + '/drivers/cmsis/Device/HDSC/hc32f4xx/Include',
cwd + '/drivers/cmsis/Include',
cwd + '/drivers/hc32_ll_driver/inc',]
CPPDEFINES = ['USE_DDL_DRIVER']
group = DefineGroup('Libraries', src, depend = [''], CPPPATH = path, CPPDEFINES = CPPDEFINES)
Return('group')

16
bsp/hc32/libraries/hc32f4a0_ddl/config/flashloader/FlashHC32F4A0.mac Normal file
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@ -0,0 +1,16 @@
setup()
{
;
}
execUserPreload()
{
__message "----- Prepare hardware for Flashloader -----\n";
setup();
}
execUserFlashInit() // Called by debugger before loading flash loader in RAM.
{
__message "----- Prepare hardware for Flashloader -----\n";
setup();
}

BIN
bsp/hc32/libraries/hc32f4a0_ddl/config/flashloader/FlashHC32F4A0.out Normal file
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10
bsp/hc32/libraries/hc32f4a0_ddl/config/flashloader/FlashHC32F4A0_otp.flash Normal file
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@ -0,0 +1,10 @@
<?xml version="1.0" encoding="iso-8859-1"?>
<flash_device>
<exe>$PROJ_DIR$\..\libraries\hc32f4a0_ddl\config\flashloader\FlashHC32F4A0_otp.out</exe>
<page>4</page>
<block>1 0x1800</block>
<flash_base>0x03000000</flash_base>
<macro>$PROJ_DIR$\..\libraries\hc32f4a0_ddl\config\flashloader\FlashHC32F4A0.mac</macro>
<aggregate>0</aggregate>
</flash_device>

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bsp/hc32/libraries/hc32f4a0_ddl/config/flashloader/FlashHC32F4A0_otp.out Normal file
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9
bsp/hc32/libraries/hc32f4a0_ddl/config/flashloader/FlashHC32F4A0_qspi.flash Normal file
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@ -0,0 +1,9 @@
<?xml version="1.0" encoding="iso-8859-1"?>
<flash_device>
<exe>$PROJ_DIR$\..\libraries\hc32f4a0_ddl\config\flashloader\FlashHC32F4A0_qspi.out</exe>
<page>256</page>
<block>2048 0x1000</block>
<flash_base>0x98000000</flash_base>
<aggregate>0</aggregate>
</flash_device>

BIN
bsp/hc32/libraries/hc32f4a0_ddl/config/flashloader/FlashHC32F4A0_qspi.out Normal file
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10
bsp/hc32/libraries/hc32f4a0_ddl/config/flashloader/FlashHC32F4A0xG.flash Normal file
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@ -0,0 +1,10 @@
<?xml version="1.0" encoding="iso-8859-1"?>
<flash_device>
<exe>$PROJ_DIR$\..\libraries\hc32f4a0_ddl\config\flashloader\FlashHC32F4A0.out</exe>
<page>4</page>
<block>128 0x2000</block>
<flash_base>0x00000000</flash_base>
<macro>$PROJ_DIR$\..\libraries\hc32f4a0_ddl\config\flashloader\FlashHC32F4A0.mac</macro>
<aggregate>0</aggregate>
</flash_device>

10
bsp/hc32/libraries/hc32f4a0_ddl/config/flashloader/FlashHC32F4A0xI.flash Normal file
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@ -0,0 +1,10 @@
<?xml version="1.0" encoding="iso-8859-1"?>
<flash_device>
<exe>$PROJ_DIR$\..\libraries\hc32f4a0_ddl\config\flashloader\FlashHC32F4A0.out</exe>
<page>4</page>
<block>256 0x2000</block>
<flash_base>0x00000000</flash_base>
<macro>$PROJ_DIR$\..\libraries\hc32f4a0_ddl\config\flashloader\FlashHC32F4A0.mac</macro>
<aggregate>0</aggregate>
</flash_device>

18
bsp/hc32/libraries/hc32f4a0_ddl/config/flashloader/HC32F4A0xG.board Normal file
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@ -0,0 +1,18 @@
<?xml version="1.0" encoding="iso-8859-1"?>
<flash_board>
<pass>
<loader>$PROJ_DIR$\..\libraries\hc32f4a0_ddl\config\flashloader\FlashHC32F4A0xG.flash</loader>
<range>CODE 0x0 0xFFFFF</range>
</pass>
<pass>
<loader>$PROJ_DIR$\..\libraries\hc32f4a0_ddl\config\flashloader\FlashHC32F4A0_otp.flash</loader>
<range>CODE 0x03000000 0x030017FF</range>
</pass>
<pass>
<loader>$PROJ_DIR$\..\libraries\hc32f4a0_ddl\config\flashloader\FlashHC32F4A0_qspi.flash</loader>
<range>CODE 0x98000000 0x987FFFFF</range>
</pass>
</flash_board>

18
bsp/hc32/libraries/hc32f4a0_ddl/config/flashloader/HC32F4A0xI.board Normal file
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@ -0,0 +1,18 @@
<?xml version="1.0" encoding="iso-8859-1"?>
<flash_board>
<pass>
<loader>$PROJ_DIR$\..\libraries\hc32f4a0_ddl\config\flashloader\FlashHC32F4A0xI.flash</loader>
<range>CODE 0x0 0x1FFFFF</range>
</pass>
<pass>
<loader>$PROJ_DIR$\..\libraries\hc32f4a0_ddl\config\flashloader\FlashHC32F4A0_otp.flash</loader>
<range>CODE 0x03000000 0x030017FF</range>
</pass>
<pass>
<loader>$PROJ_DIR$\..\libraries\hc32f4a0_ddl\config\flashloader\FlashHC32F4A0_qspi.flash</loader>
<range>CODE 0x98000000 0x987FFFFF</range>
</pass>
</flash_board>

51
bsp/hc32/libraries/hc32f4a0_ddl/config/linker/HC32F4A0_RAM.icf Normal file
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/*###ICF### Section handled by ICF editor, don't touch! ****/
/*-Editor annotation file-*/
/* IcfEditorFile="$TOOLKIT_DIR$\config\ide\IcfEditor\cortex_v1_4.xml" */
/*-Specials-*/
define symbol __ICFEDIT_intvec_start__ = 0x1FFE0000;
/*-Memory Regions-*/
define symbol __ICFEDIT_region_IROM1_start__ = 0x1FFE0000;
define symbol __ICFEDIT_region_IROM1_end__ = 0x1FFFFFFF;
define symbol __ICFEDIT_region_IROM2_start__ = 0x20000000;
define symbol __ICFEDIT_region_IROM2_end__ = 0x2001FFFF;
define symbol __ICFEDIT_region_EROM1_start__ = 0x0;
define symbol __ICFEDIT_region_EROM1_end__ = 0x0;
define symbol __ICFEDIT_region_EROM2_start__ = 0x0;
define symbol __ICFEDIT_region_EROM2_end__ = 0x0;
define symbol __ICFEDIT_region_EROM3_start__ = 0x0;
define symbol __ICFEDIT_region_EROM3_end__ = 0x0;
define symbol __ICFEDIT_region_IRAM1_start__ = 0x20020000;
define symbol __ICFEDIT_region_IRAM1_end__ = 0x2005FFFF;
define symbol __ICFEDIT_region_IRAM2_start__ = 0x200F0000;
define symbol __ICFEDIT_region_IRAM2_end__ = 0x200F0FFF;
define symbol __ICFEDIT_region_ERAM1_start__ = 0x0;
define symbol __ICFEDIT_region_ERAM1_end__ = 0x0;
define symbol __ICFEDIT_region_ERAM2_start__ = 0x0;
define symbol __ICFEDIT_region_ERAM2_end__ = 0x0;
define symbol __ICFEDIT_region_ERAM3_start__ = 0x0;
define symbol __ICFEDIT_region_ERAM3_end__ = 0x0;
/*-Sizes-*/
define symbol __ICFEDIT_size_cstack__ = 0x2000;
define symbol __ICFEDIT_size_proc_stack__ = 0x0;
define symbol __ICFEDIT_size_heap__ = 0x2000;
/**** End of ICF editor section. ###ICF###*/
define memory mem with size = 4G;
define region ROM_region = mem:[from __ICFEDIT_region_IROM1_start__ to __ICFEDIT_region_IROM1_end__]
| mem:[from __ICFEDIT_region_IROM2_start__ to __ICFEDIT_region_IROM2_end__];
define region RAM_region = mem:[from __ICFEDIT_region_IRAM1_start__ to __ICFEDIT_region_IRAM1_end__]
| mem:[from __ICFEDIT_region_IRAM2_start__ to __ICFEDIT_region_IRAM2_end__];
define block CSTACK with alignment = 8, size = __ICFEDIT_size_cstack__ { };
define block HEAP with alignment = 8, size = __ICFEDIT_size_heap__ { };
initialize by copy { readwrite };
do not initialize { section .noinit };
place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec };
place in ROM_region { readonly };
place in RAM_region { readwrite,
block CSTACK, block HEAP };

53
bsp/hc32/libraries/hc32f4a0_ddl/config/linker/HC32F4A0xG.icf Normal file
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@ -0,0 +1,53 @@
/*###ICF### Section handled by ICF editor, don't touch! ****/
/*-Editor annotation file-*/
/* IcfEditorFile="$TOOLKIT_DIR$\config\ide\IcfEditor\cortex_v1_4.xml" */
/*-Specials-*/
define symbol __ICFEDIT_intvec_start__ = 0x00000000;
/*-Memory Regions-*/
define symbol __ICFEDIT_region_IROM1_start__ = 0x00000000;
define symbol __ICFEDIT_region_IROM1_end__ = 0x000FFFFF;
define symbol __ICFEDIT_region_IROM2_start__ = 0x03000000;
define symbol __ICFEDIT_region_IROM2_end__ = 0x030017FF;
define symbol __ICFEDIT_region_EROM1_start__ = 0x98000000;
define symbol __ICFEDIT_region_EROM1_end__ = 0x987FFFFF;
define symbol __ICFEDIT_region_EROM2_start__ = 0x0;
define symbol __ICFEDIT_region_EROM2_end__ = 0x0;
define symbol __ICFEDIT_region_EROM3_start__ = 0x0;
define symbol __ICFEDIT_region_EROM3_end__ = 0x0;
define symbol __ICFEDIT_region_IRAM1_start__ = 0x1FFE0000;
define symbol __ICFEDIT_region_IRAM1_end__ = 0x2005FFFF;
define symbol __ICFEDIT_region_IRAM2_start__ = 0x200F0000;
define symbol __ICFEDIT_region_IRAM2_end__ = 0x200F0FFF;
define symbol __ICFEDIT_region_ERAM1_start__ = 0x0;
define symbol __ICFEDIT_region_ERAM1_end__ = 0x0;
define symbol __ICFEDIT_region_ERAM2_start__ = 0x0;
define symbol __ICFEDIT_region_ERAM2_end__ = 0x0;
define symbol __ICFEDIT_region_ERAM3_start__ = 0x0;
define symbol __ICFEDIT_region_ERAM3_end__ = 0x0;
/*-Sizes-*/
define symbol __ICFEDIT_size_cstack__ = 0x2000;
define symbol __ICFEDIT_size_proc_stack__ = 0x0;
define symbol __ICFEDIT_size_heap__ = 0x2000;
/**** End of ICF editor section. ###ICF###*/
define memory mem with size = 4G;
define region ROM_region = mem:[from __ICFEDIT_region_IROM1_start__ to __ICFEDIT_region_IROM1_end__]
| mem:[from __ICFEDIT_region_IROM2_start__ to __ICFEDIT_region_IROM2_end__];
define region QSPI_region = mem:[from __ICFEDIT_region_EROM1_start__ to __ICFEDIT_region_EROM1_end__];
define region RAM_region = mem:[from __ICFEDIT_region_IRAM1_start__ to __ICFEDIT_region_IRAM1_end__]
| mem:[from __ICFEDIT_region_IRAM2_start__ to __ICFEDIT_region_IRAM2_end__];
define block CSTACK with alignment = 8, size = __ICFEDIT_size_cstack__ { };
define block HEAP with alignment = 8, size = __ICFEDIT_size_heap__ { };
initialize by copy { readwrite };
do not initialize { section .noinit };
place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec };
place in ROM_region { readonly };
place in QSPI_region { readonly section .ex_rom };
place in RAM_region { readwrite,
block CSTACK, block HEAP };

53
bsp/hc32/libraries/hc32f4a0_ddl/config/linker/HC32F4A0xI.icf Normal file
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/*###ICF### Section handled by ICF editor, don't touch! ****/
/*-Editor annotation file-*/
/* IcfEditorFile="$TOOLKIT_DIR$\config\ide\IcfEditor\cortex_v1_4.xml" */
/*-Specials-*/
define symbol __ICFEDIT_intvec_start__ = 0x00000000;
/*-Memory Regions-*/
define symbol __ICFEDIT_region_IROM1_start__ = 0x00000000;
define symbol __ICFEDIT_region_IROM1_end__ = 0x001FFFFF;
define symbol __ICFEDIT_region_IROM2_start__ = 0x03000000;
define symbol __ICFEDIT_region_IROM2_end__ = 0x030017FF;
define symbol __ICFEDIT_region_EROM1_start__ = 0x98000000;
define symbol __ICFEDIT_region_EROM1_end__ = 0x987FFFFF;
define symbol __ICFEDIT_region_EROM2_start__ = 0x0;
define symbol __ICFEDIT_region_EROM2_end__ = 0x0;
define symbol __ICFEDIT_region_EROM3_start__ = 0x0;
define symbol __ICFEDIT_region_EROM3_end__ = 0x0;
define symbol __ICFEDIT_region_IRAM1_start__ = 0x1FFE0000;
define symbol __ICFEDIT_region_IRAM1_end__ = 0x2005FFFF;
define symbol __ICFEDIT_region_IRAM2_start__ = 0x200F0000;
define symbol __ICFEDIT_region_IRAM2_end__ = 0x200F0FFF;
define symbol __ICFEDIT_region_ERAM1_start__ = 0x0;
define symbol __ICFEDIT_region_ERAM1_end__ = 0x0;
define symbol __ICFEDIT_region_ERAM2_start__ = 0x0;
define symbol __ICFEDIT_region_ERAM2_end__ = 0x0;
define symbol __ICFEDIT_region_ERAM3_start__ = 0x0;
define symbol __ICFEDIT_region_ERAM3_end__ = 0x0;
/*-Sizes-*/
define symbol __ICFEDIT_size_cstack__ = 0x2000;
define symbol __ICFEDIT_size_proc_stack__ = 0x0;
define symbol __ICFEDIT_size_heap__ = 0x2000;
/**** End of ICF editor section. ###ICF###*/
define memory mem with size = 4G;
define region ROM_region = mem:[from __ICFEDIT_region_IROM1_start__ to __ICFEDIT_region_IROM1_end__]
| mem:[from __ICFEDIT_region_IROM2_start__ to __ICFEDIT_region_IROM2_end__];
define region QSPI_region = mem:[from __ICFEDIT_region_EROM1_start__ to __ICFEDIT_region_EROM1_end__];
define region RAM_region = mem:[from __ICFEDIT_region_IRAM1_start__ to __ICFEDIT_region_IRAM1_end__]
| mem:[from __ICFEDIT_region_IRAM2_start__ to __ICFEDIT_region_IRAM2_end__];
define block CSTACK with alignment = 8, size = __ICFEDIT_size_cstack__ { };
define block HEAP with alignment = 8, size = __ICFEDIT_size_heap__ { };
initialize by copy { readwrite };
do not initialize { section .noinit };
place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec };
place in ROM_region { readonly };
place in QSPI_region { readonly section .ex_rom };
place in RAM_region { readwrite,
block CSTACK, block HEAP };

23785
bsp/hc32/libraries/hc32f4a0_ddl/drivers/cmsis/Device/HDSC/hc32f4xx/Include/hc32f4a0.h Normal file
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66
bsp/hc32/libraries/hc32f4a0_ddl/drivers/cmsis/Device/HDSC/hc32f4xx/Include/hc32f4xx.h Normal file
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/**
*******************************************************************************
* @file hc32f4xx.h
* @brief This file contains the common part of the HC32 series.
@verbatim
Change Logs:
Date Author Notes
2022-03-31 CDT First version
@endverbatim
*******************************************************************************
* Copyright (C) 2022, Xiaohua Semiconductor Co., Ltd. All rights reserved.
*
* This software component is licensed by XHSC under BSD 3-Clause license
* (the "License"); You may not use this file except in compliance with the
* License. You may obtain a copy of the License at:
* opensource.org/licenses/BSD-3-Clause
*
*******************************************************************************
*/
#ifndef __HC32F4XX_H__
#define __HC32F4XX_H__
/* C binding of definitions if building with C++ compiler */
#ifdef __cplusplus
extern "C"
{
#endif
/*******************************************************************************
* Include files
******************************************************************************/
/**
* @brief HC32F4xx Device Include
*/
#if defined(HC32F4A0)
#include "hc32f4a0.h"
#include "system_hc32f4a0.h"
#else
#error "Please select first the target HC32xxxx device used in your application (in hc32xxxx.h file)"
#endif
/*******************************************************************************
* Global type definitions ('typedef')
******************************************************************************/
/*******************************************************************************
* Global pre-processor symbols/macros ('#define')
******************************************************************************/
/*******************************************************************************
* Global variable definitions ('extern')
******************************************************************************/
/*******************************************************************************
* Global function prototypes (definition in C source)
******************************************************************************/
#ifdef __cplusplus
}
#endif
#endif /* __HC32F4XX_H__ */
/*******************************************************************************
* EOF (not truncated)
******************************************************************************/

142
bsp/hc32/libraries/hc32f4a0_ddl/drivers/cmsis/Device/HDSC/hc32f4xx/Include/system_hc32f4a0.h Normal file
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/**
*******************************************************************************
* @file system_hc32f4a0.h
* @brief This file contains all the functions prototypes of the HC32 System.
@verbatim
Change Logs:
Date Author Notes
2022-03-31 CDT First version
@endverbatim
*******************************************************************************
* Copyright (C) 2022, Xiaohua Semiconductor Co., Ltd. All rights reserved.
*
* This software component is licensed by XHSC under BSD 3-Clause license
* (the "License"); You may not use this file except in compliance with the
* License. You may obtain a copy of the License at:
* opensource.org/licenses/BSD-3-Clause
*
*******************************************************************************
*/
#ifndef __SYSTEM_HC32F4A0_H__
#define __SYSTEM_HC32F4A0_H__
/* C binding of definitions if building with C++ compiler */
#ifdef __cplusplus
extern "C"
{
#endif
/*******************************************************************************
* Include files
******************************************************************************/
#include <stdint.h>
/**
* @addtogroup CMSIS
* @{
*/
/**
* @addtogroup HC32F4A0_System
* @{
*/
/*******************************************************************************
* Global pre-processor symbols/macros ('define')
******************************************************************************/
/**
* @addtogroup HC32F4A0_System_Global_Macros
* @{
*/
/**
* @addtogroup HC32F4A0_System_Clock_Source
* @{
*/
#if !defined (MRC_VALUE)
#define MRC_VALUE (8000000UL) /*!< Internal middle speed RC freq. */
#endif
#if !defined (LRC_VALUE)
#define LRC_VALUE (32768UL) /*!< Internal low speed RC freq. */
#endif
#if !defined (RTCLRC_VALUE)
#define RTCLRC_VALUE (32768UL) /*!< Internal RTC low speed RC freq. */
#endif
#if !defined (SWDTLRC_VALUE)
#define SWDTLRC_VALUE (10000UL) /*!< Internal SWDT low speed RC freq. */
#endif
#if !defined (XTAL_VALUE)
#define XTAL_VALUE (8000000UL) /*!< External high speed OSC freq. */
#endif
#if !defined (XTAL32_VALUE)
#define XTAL32_VALUE (32768UL) /*!< External low speed OSC freq. */
#endif
#if !defined (HCLK_VALUE)
#define HCLK_VALUE (SystemCoreClock >> ((CM_CMU->SCFGR & CMU_SCFGR_HCLKS) >> CMU_SCFGR_HCLKS_POS))
#endif
/**
* @}
*/
/**
* @}
*/
/*******************************************************************************
* Global variable definitions ('extern')
******************************************************************************/
/**
* @addtogroup HC32F4A0_System_Exported_Variable
* @{
*/
extern uint32_t SystemCoreClock; /*!< System clock frequency (Core clock) */
extern uint32_t HRC_VALUE; /*!< HRC frequency */
/**
* @}
*/
/*******************************************************************************
* Global function prototypes (definition in C source)
******************************************************************************/
/**
* @addtogroup HC32F4A0_System_Global_Functions
* @{
*/
extern void SystemInit(void); /*!< Initialize the system */
extern void SystemCoreClockUpdate(void); /*!< Update SystemCoreClock variable */
#if defined (ROM_EXT_QSPI)
void SystemInit_QspiMem(void);
#endif
/**
* @}
*/
/**
* @}
*/
/**
* @}
*/
#ifdef __cplusplus
}
#endif
#endif /* __SYSTEM_HC32F4A0_H__ */
/*******************************************************************************
* EOF (not truncated)
******************************************************************************/

BIN
bsp/hc32/libraries/hc32f4a0_ddl/drivers/cmsis/Device/HDSC/hc32f4xx/Source/ARM/flashloader/HC32F4A0_1M.FLM Normal file
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bsp/hc32/libraries/hc32f4a0_ddl/drivers/cmsis/Device/HDSC/hc32f4xx/Source/ARM/flashloader/HC32F4A0_RAM.FLM Normal file
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bsp/hc32/libraries/hc32f4a0_ddl/drivers/cmsis/Device/HDSC/hc32f4xx/Source/ARM/flashloader/HC32F4A0_otp.FLM Normal file
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16
bsp/hc32/libraries/hc32f4a0_ddl/drivers/cmsis/Device/HDSC/hc32f4xx/Source/ARM/flashloader/ram.ini Normal file
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FUNC void Setup (void) {
SP = _RDWORD(0x1FFE0000);
PC = _RDWORD(0x1FFE0004);
_WDWORD(0xE000ED08, 0x1FFE0000);
}
LOAD .\output\release\efm_sequence_program.axf INCREMENTAL
Setup();
g, main

BIN
bsp/hc32/libraries/hc32f4a0_ddl/drivers/cmsis/Device/HDSC/hc32f4xx/Source/ARM/sfr/HDSC_HC32F4A0.SFR Normal file
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594
bsp/hc32/libraries/hc32f4a0_ddl/drivers/cmsis/Device/HDSC/hc32f4xx/Source/ARM/startup_hc32f4a0.s Normal file
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;/*****************************************************************************
; * Copyright (C) 2022, Xiaohua Semiconductor Co., Ltd. All rights reserved.
; *
; * This software component is licensed by XHSC under BSD 3-Clause license
; * (the "License"); You may not use this file except in compliance with the
; * License. You may obtain a copy of the License at:
; * opensource.org/licenses/BSD-3-Clause
; *
; */
;/****************************************************************************/
;/* Startup for MDK */
;/* Version V1.0 */
;/* Date 2022-03-31 */
;/* Target-mcu HC32F4A0 */
;/****************************************************************************/
; Stack Configuration
; Stack Size (in Bytes) <0x0-0xFFFFFFFF:8>
Stack_Size EQU 0x00002000
AREA STACK, NOINIT, READWRITE, ALIGN=3
Stack_Mem SPACE Stack_Size
__initial_sp
; Heap Configuration
; Heap Size (in Bytes) <0x0-0xFFFFFFFF:8>
Heap_Size EQU 0x00002000
AREA HEAP, NOINIT, READWRITE, ALIGN=3
__heap_base
Heap_Mem SPACE Heap_Size
__heap_limit
PRESERVE8
THUMB
; Vector Table Mapped to Address 0 at Reset
AREA RESET, DATA, READONLY
EXPORT __Vectors
EXPORT __Vectors_End
EXPORT __Vectors_Size
__Vectors DCD __initial_sp ; Top of Stack
DCD Reset_Handler ; Reset Handler
DCD NMI_Handler ; NMI Handler
DCD HardFault_Handler ; Hard Fault Handler
DCD MemManage_Handler ; MPU Fault Handler
DCD BusFault_Handler ; Bus Fault Handler
DCD UsageFault_Handler ; Usage Fault Handler
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD SVC_Handler ; SVCall Handler
DCD DebugMon_Handler ; Debug Monitor Handler
DCD 0 ; Reserved
DCD PendSV_Handler ; PendSV Handler
DCD SysTick_Handler ; SysTick Handler
; Peripheral Interrupts
DCD IRQ000_Handler
DCD IRQ001_Handler
DCD IRQ002_Handler
DCD IRQ003_Handler
DCD IRQ004_Handler
DCD IRQ005_Handler
DCD IRQ006_Handler
DCD IRQ007_Handler
DCD IRQ008_Handler
DCD IRQ009_Handler
DCD IRQ010_Handler
DCD IRQ011_Handler
DCD IRQ012_Handler
DCD IRQ013_Handler
DCD IRQ014_Handler
DCD IRQ015_Handler
DCD IRQ016_Handler
DCD IRQ017_Handler
DCD IRQ018_Handler
DCD IRQ019_Handler
DCD IRQ020_Handler
DCD IRQ021_Handler
DCD IRQ022_Handler
DCD IRQ023_Handler
DCD IRQ024_Handler
DCD IRQ025_Handler
DCD IRQ026_Handler
DCD IRQ027_Handler
DCD IRQ028_Handler
DCD IRQ029_Handler
DCD IRQ030_Handler
DCD IRQ031_Handler
DCD IRQ032_Handler
DCD IRQ033_Handler
DCD IRQ034_Handler
DCD IRQ035_Handler
DCD IRQ036_Handler
DCD IRQ037_Handler
DCD IRQ038_Handler
DCD IRQ039_Handler
DCD IRQ040_Handler
DCD IRQ041_Handler
DCD IRQ042_Handler
DCD IRQ043_Handler
DCD IRQ044_Handler
DCD IRQ045_Handler
DCD IRQ046_Handler
DCD IRQ047_Handler
DCD IRQ048_Handler
DCD IRQ049_Handler
DCD IRQ050_Handler
DCD IRQ051_Handler
DCD IRQ052_Handler
DCD IRQ053_Handler
DCD IRQ054_Handler
DCD IRQ055_Handler
DCD IRQ056_Handler
DCD IRQ057_Handler
DCD IRQ058_Handler
DCD IRQ059_Handler
DCD IRQ060_Handler
DCD IRQ061_Handler
DCD IRQ062_Handler
DCD IRQ063_Handler
DCD IRQ064_Handler
DCD IRQ065_Handler
DCD IRQ066_Handler
DCD IRQ067_Handler
DCD IRQ068_Handler
DCD IRQ069_Handler
DCD IRQ070_Handler
DCD IRQ071_Handler
DCD IRQ072_Handler
DCD IRQ073_Handler
DCD IRQ074_Handler
DCD IRQ075_Handler
DCD IRQ076_Handler
DCD IRQ077_Handler
DCD IRQ078_Handler
DCD IRQ079_Handler
DCD IRQ080_Handler
DCD IRQ081_Handler
DCD IRQ082_Handler
DCD IRQ083_Handler
DCD IRQ084_Handler
DCD IRQ085_Handler
DCD IRQ086_Handler
DCD IRQ087_Handler
DCD IRQ088_Handler
DCD IRQ089_Handler
DCD IRQ090_Handler
DCD IRQ091_Handler
DCD IRQ092_Handler
DCD IRQ093_Handler
DCD IRQ094_Handler
DCD IRQ095_Handler
DCD IRQ096_Handler
DCD IRQ097_Handler
DCD IRQ098_Handler
DCD IRQ099_Handler
DCD IRQ100_Handler
DCD IRQ101_Handler
DCD IRQ102_Handler
DCD IRQ103_Handler
DCD IRQ104_Handler
DCD IRQ105_Handler
DCD IRQ106_Handler
DCD IRQ107_Handler
DCD IRQ108_Handler
DCD IRQ109_Handler
DCD IRQ110_Handler
DCD IRQ111_Handler
DCD IRQ112_Handler
DCD IRQ113_Handler
DCD IRQ114_Handler
DCD IRQ115_Handler
DCD IRQ116_Handler
DCD IRQ117_Handler
DCD IRQ118_Handler
DCD IRQ119_Handler
DCD IRQ120_Handler
DCD IRQ121_Handler
DCD IRQ122_Handler
DCD IRQ123_Handler
DCD IRQ124_Handler
DCD IRQ125_Handler
DCD IRQ126_Handler
DCD IRQ127_Handler
DCD IRQ128_Handler
DCD IRQ129_Handler
DCD IRQ130_Handler
DCD IRQ131_Handler
DCD IRQ132_Handler
DCD IRQ133_Handler
DCD IRQ134_Handler
DCD IRQ135_Handler
DCD IRQ136_Handler
DCD IRQ137_Handler
DCD IRQ138_Handler
DCD IRQ139_Handler
DCD IRQ140_Handler
DCD IRQ141_Handler
DCD IRQ142_Handler
DCD IRQ143_Handler
__Vectors_End
__Vectors_Size EQU __Vectors_End - __Vectors
AREA |.text|, CODE, READONLY
; Reset Handler
Reset_Handler PROC
EXPORT Reset_Handler [WEAK]
IMPORT SystemInit
IMPORT __main
LDR R0, =SystemInit
BLX R0
LDR R0, =__main
BX R0
ENDP
; Dummy Exception Handlers (infinite loops which can be modified)
NMI_Handler PROC
EXPORT NMI_Handler [WEAK]
B .
ENDP
HardFault_Handler\
PROC
EXPORT HardFault_Handler [WEAK]
B .
ENDP
MemManage_Handler\
PROC
EXPORT MemManage_Handler [WEAK]
B .
ENDP
BusFault_Handler\
PROC
EXPORT BusFault_Handler [WEAK]
B .
ENDP
UsageFault_Handler\
PROC
EXPORT UsageFault_Handler [WEAK]
B .
ENDP
SVC_Handler PROC
EXPORT SVC_Handler [WEAK]
B .
ENDP
DebugMon_Handler\
PROC
EXPORT DebugMon_Handler [WEAK]
B .
ENDP
PendSV_Handler PROC
EXPORT PendSV_Handler [WEAK]
B .
ENDP
SysTick_Handler PROC
EXPORT SysTick_Handler [WEAK]
B .
ENDP
Default_Handler PROC
EXPORT IRQ000_Handler [WEAK]
EXPORT IRQ001_Handler [WEAK]
EXPORT IRQ002_Handler [WEAK]
EXPORT IRQ003_Handler [WEAK]
EXPORT IRQ004_Handler [WEAK]
EXPORT IRQ005_Handler [WEAK]
EXPORT IRQ006_Handler [WEAK]
EXPORT IRQ007_Handler [WEAK]
EXPORT IRQ008_Handler [WEAK]
EXPORT IRQ009_Handler [WEAK]
EXPORT IRQ010_Handler [WEAK]
EXPORT IRQ011_Handler [WEAK]
EXPORT IRQ012_Handler [WEAK]
EXPORT IRQ013_Handler [WEAK]
EXPORT IRQ014_Handler [WEAK]
EXPORT IRQ015_Handler [WEAK]
EXPORT IRQ016_Handler [WEAK]
EXPORT IRQ017_Handler [WEAK]
EXPORT IRQ018_Handler [WEAK]
EXPORT IRQ019_Handler [WEAK]
EXPORT IRQ020_Handler [WEAK]
EXPORT IRQ021_Handler [WEAK]
EXPORT IRQ022_Handler [WEAK]
EXPORT IRQ023_Handler [WEAK]
EXPORT IRQ024_Handler [WEAK]
EXPORT IRQ025_Handler [WEAK]
EXPORT IRQ026_Handler [WEAK]
EXPORT IRQ027_Handler [WEAK]
EXPORT IRQ028_Handler [WEAK]
EXPORT IRQ029_Handler [WEAK]
EXPORT IRQ030_Handler [WEAK]
EXPORT IRQ031_Handler [WEAK]
EXPORT IRQ032_Handler [WEAK]
EXPORT IRQ033_Handler [WEAK]
EXPORT IRQ034_Handler [WEAK]
EXPORT IRQ035_Handler [WEAK]
EXPORT IRQ036_Handler [WEAK]
EXPORT IRQ037_Handler [WEAK]
EXPORT IRQ038_Handler [WEAK]
EXPORT IRQ039_Handler [WEAK]
EXPORT IRQ040_Handler [WEAK]
EXPORT IRQ041_Handler [WEAK]
EXPORT IRQ042_Handler [WEAK]
EXPORT IRQ043_Handler [WEAK]
EXPORT IRQ044_Handler [WEAK]
EXPORT IRQ045_Handler [WEAK]
EXPORT IRQ046_Handler [WEAK]
EXPORT IRQ047_Handler [WEAK]
EXPORT IRQ048_Handler [WEAK]
EXPORT IRQ049_Handler [WEAK]
EXPORT IRQ050_Handler [WEAK]
EXPORT IRQ051_Handler [WEAK]
EXPORT IRQ052_Handler [WEAK]
EXPORT IRQ053_Handler [WEAK]
EXPORT IRQ054_Handler [WEAK]
EXPORT IRQ055_Handler [WEAK]
EXPORT IRQ056_Handler [WEAK]
EXPORT IRQ057_Handler [WEAK]
EXPORT IRQ058_Handler [WEAK]
EXPORT IRQ059_Handler [WEAK]
EXPORT IRQ060_Handler [WEAK]
EXPORT IRQ061_Handler [WEAK]
EXPORT IRQ062_Handler [WEAK]
EXPORT IRQ063_Handler [WEAK]
EXPORT IRQ064_Handler [WEAK]
EXPORT IRQ065_Handler [WEAK]
EXPORT IRQ066_Handler [WEAK]
EXPORT IRQ067_Handler [WEAK]
EXPORT IRQ068_Handler [WEAK]
EXPORT IRQ069_Handler [WEAK]
EXPORT IRQ070_Handler [WEAK]
EXPORT IRQ071_Handler [WEAK]
EXPORT IRQ072_Handler [WEAK]
EXPORT IRQ073_Handler [WEAK]
EXPORT IRQ074_Handler [WEAK]
EXPORT IRQ075_Handler [WEAK]
EXPORT IRQ076_Handler [WEAK]
EXPORT IRQ077_Handler [WEAK]
EXPORT IRQ078_Handler [WEAK]
EXPORT IRQ079_Handler [WEAK]
EXPORT IRQ080_Handler [WEAK]
EXPORT IRQ081_Handler [WEAK]
EXPORT IRQ082_Handler [WEAK]
EXPORT IRQ083_Handler [WEAK]
EXPORT IRQ084_Handler [WEAK]
EXPORT IRQ085_Handler [WEAK]
EXPORT IRQ086_Handler [WEAK]
EXPORT IRQ087_Handler [WEAK]
EXPORT IRQ088_Handler [WEAK]
EXPORT IRQ089_Handler [WEAK]
EXPORT IRQ090_Handler [WEAK]
EXPORT IRQ091_Handler [WEAK]
EXPORT IRQ092_Handler [WEAK]
EXPORT IRQ093_Handler [WEAK]
EXPORT IRQ094_Handler [WEAK]
EXPORT IRQ095_Handler [WEAK]
EXPORT IRQ096_Handler [WEAK]
EXPORT IRQ097_Handler [WEAK]
EXPORT IRQ098_Handler [WEAK]
EXPORT IRQ099_Handler [WEAK]
EXPORT IRQ100_Handler [WEAK]
EXPORT IRQ101_Handler [WEAK]
EXPORT IRQ102_Handler [WEAK]
EXPORT IRQ103_Handler [WEAK]
EXPORT IRQ104_Handler [WEAK]
EXPORT IRQ105_Handler [WEAK]
EXPORT IRQ106_Handler [WEAK]
EXPORT IRQ107_Handler [WEAK]
EXPORT IRQ108_Handler [WEAK]
EXPORT IRQ109_Handler [WEAK]
EXPORT IRQ110_Handler [WEAK]
EXPORT IRQ111_Handler [WEAK]
EXPORT IRQ112_Handler [WEAK]
EXPORT IRQ113_Handler [WEAK]
EXPORT IRQ114_Handler [WEAK]
EXPORT IRQ115_Handler [WEAK]
EXPORT IRQ116_Handler [WEAK]
EXPORT IRQ117_Handler [WEAK]
EXPORT IRQ118_Handler [WEAK]
EXPORT IRQ119_Handler [WEAK]
EXPORT IRQ120_Handler [WEAK]
EXPORT IRQ121_Handler [WEAK]
EXPORT IRQ122_Handler [WEAK]
EXPORT IRQ123_Handler [WEAK]
EXPORT IRQ124_Handler [WEAK]
EXPORT IRQ125_Handler [WEAK]
EXPORT IRQ126_Handler [WEAK]
EXPORT IRQ127_Handler [WEAK]
EXPORT IRQ128_Handler [WEAK]
EXPORT IRQ129_Handler [WEAK]
EXPORT IRQ130_Handler [WEAK]
EXPORT IRQ131_Handler [WEAK]
EXPORT IRQ132_Handler [WEAK]
EXPORT IRQ133_Handler [WEAK]
EXPORT IRQ134_Handler [WEAK]
EXPORT IRQ135_Handler [WEAK]
EXPORT IRQ136_Handler [WEAK]
EXPORT IRQ137_Handler [WEAK]
EXPORT IRQ138_Handler [WEAK]
EXPORT IRQ139_Handler [WEAK]
EXPORT IRQ140_Handler [WEAK]
EXPORT IRQ141_Handler [WEAK]
EXPORT IRQ142_Handler [WEAK]
EXPORT IRQ143_Handler [WEAK]
IRQ000_Handler
IRQ001_Handler
IRQ002_Handler
IRQ003_Handler
IRQ004_Handler
IRQ005_Handler
IRQ006_Handler
IRQ007_Handler
IRQ008_Handler
IRQ009_Handler
IRQ010_Handler
IRQ011_Handler
IRQ012_Handler
IRQ013_Handler
IRQ014_Handler
IRQ015_Handler
IRQ016_Handler
IRQ017_Handler
IRQ018_Handler
IRQ019_Handler
IRQ020_Handler
IRQ021_Handler
IRQ022_Handler
IRQ023_Handler
IRQ024_Handler
IRQ025_Handler
IRQ026_Handler
IRQ027_Handler
IRQ028_Handler
IRQ029_Handler
IRQ030_Handler
IRQ031_Handler
IRQ032_Handler
IRQ033_Handler
IRQ034_Handler
IRQ035_Handler
IRQ036_Handler
IRQ037_Handler
IRQ038_Handler
IRQ039_Handler
IRQ040_Handler
IRQ041_Handler
IRQ042_Handler
IRQ043_Handler
IRQ044_Handler
IRQ045_Handler
IRQ046_Handler
IRQ047_Handler
IRQ048_Handler
IRQ049_Handler
IRQ050_Handler
IRQ051_Handler
IRQ052_Handler
IRQ053_Handler
IRQ054_Handler
IRQ055_Handler
IRQ056_Handler
IRQ057_Handler
IRQ058_Handler
IRQ059_Handler
IRQ060_Handler
IRQ061_Handler
IRQ062_Handler
IRQ063_Handler
IRQ064_Handler
IRQ065_Handler
IRQ066_Handler
IRQ067_Handler
IRQ068_Handler
IRQ069_Handler
IRQ070_Handler
IRQ071_Handler
IRQ072_Handler
IRQ073_Handler
IRQ074_Handler
IRQ075_Handler
IRQ076_Handler
IRQ077_Handler
IRQ078_Handler
IRQ079_Handler
IRQ080_Handler
IRQ081_Handler
IRQ082_Handler
IRQ083_Handler
IRQ084_Handler
IRQ085_Handler
IRQ086_Handler
IRQ087_Handler
IRQ088_Handler
IRQ089_Handler
IRQ090_Handler
IRQ091_Handler
IRQ092_Handler
IRQ093_Handler
IRQ094_Handler
IRQ095_Handler
IRQ096_Handler
IRQ097_Handler
IRQ098_Handler
IRQ099_Handler
IRQ100_Handler
IRQ101_Handler
IRQ102_Handler
IRQ103_Handler
IRQ104_Handler
IRQ105_Handler
IRQ106_Handler
IRQ107_Handler
IRQ108_Handler
IRQ109_Handler
IRQ110_Handler
IRQ111_Handler
IRQ112_Handler
IRQ113_Handler
IRQ114_Handler
IRQ115_Handler
IRQ116_Handler
IRQ117_Handler
IRQ118_Handler
IRQ119_Handler
IRQ120_Handler
IRQ121_Handler
IRQ122_Handler
IRQ123_Handler
IRQ124_Handler
IRQ125_Handler
IRQ126_Handler
IRQ127_Handler
IRQ128_Handler
IRQ129_Handler
IRQ130_Handler
IRQ131_Handler
IRQ132_Handler
IRQ133_Handler
IRQ134_Handler
IRQ135_Handler
IRQ136_Handler
IRQ137_Handler
IRQ138_Handler
IRQ139_Handler
IRQ140_Handler
IRQ141_Handler
IRQ142_Handler
IRQ143_Handler
B .
ENDP
ALIGN
; User Initial Stack & Heap
IF :DEF:__MICROLIB
EXPORT __initial_sp
EXPORT __heap_base
EXPORT __heap_limit
ELSE
IMPORT __use_two_region_memory
EXPORT __user_initial_stackheap
__user_initial_stackheap
LDR R0, = Heap_Mem
LDR R1, =(Stack_Mem + Stack_Size)
LDR R2, = (Heap_Mem + Heap_Size)
LDR R3, = Stack_Mem
BX LR
ALIGN
ENDIF
END

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