diff --git a/bsp/xplorer4330/applications/SConscript b/bsp/xplorer4330/applications/SConscript new file mode 100644 index 0000000000..2939090ba9 --- /dev/null +++ b/bsp/xplorer4330/applications/SConscript @@ -0,0 +1,11 @@ +Import('RTT_ROOT') +Import('rtconfig') +from building import * + +cwd = GetCurrentDir() +src = Glob('*.c') +CPPPATH = [cwd, str(Dir('#'))] + +group = DefineGroup('applications', src, depend = [''], CPPPATH = CPPPATH) + +Return('group') diff --git a/bsp/xplorer4330/applications/application.c b/bsp/xplorer4330/applications/application.c new file mode 100644 index 0000000000..295fb903bb --- /dev/null +++ b/bsp/xplorer4330/applications/application.c @@ -0,0 +1,62 @@ +/* + * File : application.c + * This file is part of RT-Thread RTOS + * COPYRIGHT (C) 2012, RT-Thread Development Team + * + * The license and distribution terms for this file may be + * found in the file LICENSE in this distribution or at + * http://www.rt-thread.org/license/LICENSE + * + * Change Logs: + * Date Author Notes + * 2009-01-05 Bernard the first version + */ + +/** + * @addtogroup LPC4330 + */ + +/*@{*/ + +#include + +#ifdef RT_USING_COMPONENTS_INIT +#include +#endif + +#include "board_ngx_xplorer_18304330.h" + +static void rt_init_thread_entry(void *parameter) +{ + Board_LED_Init(); + +#ifdef RT_USING_COMPONENTS_INIT + /* initialization RT-Thread Components */ + rt_components_init(); +#endif + + while (1) + { + Board_LED_Set(0, 1); + rt_thread_delay(50); + Board_LED_Set(0, 0); + rt_thread_delay(50); + } +} + +void rt_application_init(void) +{ + rt_thread_t tid; + + tid = rt_thread_create("init", + rt_init_thread_entry, + RT_NULL, + 2048, + RT_THREAD_PRIORITY_MAX / 3, + 20); + + if (tid != RT_NULL) + rt_thread_startup(tid); +} + +/*@}*/ diff --git a/bsp/xplorer4330/applications/startup.c b/bsp/xplorer4330/applications/startup.c new file mode 100644 index 0000000000..236854ab9b --- /dev/null +++ b/bsp/xplorer4330/applications/startup.c @@ -0,0 +1,91 @@ +/* + * File : startup.c + * This file is part of RT-Thread RTOS + * COPYRIGHT (C) 2012, RT-Thread Development Team + * + * The license and distribution terms for this file may be + * found in the file LICENSE in this distribution or at + * http://www.rt-thread.org/license/LICENSE + * + * Change Logs: + * Date Author Notes + * 2009-01-05 Bernard first implementation + * 2012-12-11 lgnq modified for LPC4330 + */ + +#include +#include + +#include "platform.h" + +/** + * @addtogroup LPC4330 + */ + +/*@{*/ + +extern int rt_application_init(void); + +#ifdef __CC_ARM +extern int Image$$RW_IRAM1$$ZI$$Limit; +#define LPC4300_SRAM_BEGIN (&Image$$RW_IRAM1$$ZI$$Limit) +#elif __ICCARM__ +#pragma section="HEAP" +#define LPC4300_SRAM_BEGIN (__segment_end("HEAP")) +#else +extern int __bss_end; +#define LPC4300_SRAM_BEGIN (&__bss_end) +#endif + +/** + * This function will startup RT-Thread RTOS. + */ +void rtthread_startup(void) +{ + /* init board */ + rt_hw_board_init(); + + /* show version */ + rt_show_version(); + +#ifdef RT_USING_HEAP + /* initialize memory system */ + rt_system_heap_init((void *)LPC4300_SRAM_BEGIN, (void *)(0x10000000 + 1024*128)); +#endif + + /* init scheduler system */ + rt_system_scheduler_init(); + +#ifdef RT_USING_DEVICE + /* init all device */ + rt_device_init_all(); +#endif + + /* init application */ + rt_application_init(); + + /* init timer thread */ + rt_system_timer_thread_init(); + + /* init idle thread */ + rt_thread_idle_init(); + + /* start scheduler */ + rt_system_scheduler_start(); + + /* never reach here */ + return ; +} + +int main(void) +{ + /* disable interrupt first */ + rt_hw_interrupt_disable(); + + /* startup RT-Thread RTOS */ + rtthread_startup(); + + return 0; +} + +/*@}*/ diff --git a/bsp/xplorer4330/drivers/SConscript b/bsp/xplorer4330/drivers/SConscript new file mode 100644 index 0000000000..01177dc4c9 --- /dev/null +++ b/bsp/xplorer4330/drivers/SConscript @@ -0,0 +1,16 @@ +Import('RTT_ROOT') +Import('rtconfig') +from building import * + +cwd = GetCurrentDir() +src = Glob('*.c') + +# remove no need file. +if GetDepend('RT_USING_SERIAL') == False: + SrcRemove(src, 'usart.c') + +CPPPATH = [cwd] + +group = DefineGroup('drivers', src, depend = [''], CPPPATH = CPPPATH) + +Return('group') diff --git a/bsp/xplorer4330/drivers/platform.c b/bsp/xplorer4330/drivers/platform.c new file mode 100644 index 0000000000..7156f95724 --- /dev/null +++ b/bsp/xplorer4330/drivers/platform.c @@ -0,0 +1,64 @@ +/* + * File : board.c + * This file is part of RT-Thread RTOS + * COPYRIGHT (C) 2012 RT-Thread Develop Team + * + * The license and distribution terms for this file may be + * found in the file LICENSE in this distribution or at + * http://www.rt-thread.org/license/LICENSE + * + * Change Logs: + * Date Author Notes + * 2012-12-13 lgnq first implementation + */ + +#include +#include + +#include "board.h" +#include "cmsis.h" + +#ifdef RT_USING_SERIAL +#include "usart.h" +#endif + +/** + * @addtogroup LPC4330 + */ + +/*@{*/ + +/** + * This is the timer interrupt service routine. + */ +void SysTick_Handler(void) +{ + /* enter interrupt */ + rt_interrupt_enter(); + + rt_tick_increase(); + + /* leave interrupt */ + rt_interrupt_leave(); +} + +/** + * This function will initialize the LPC4330 Xplorer board. + */ +void rt_hw_board_init(void) +{ + Board_Init(); + + /* Configure the SysTick - Generate interrupt @ 100 Hz*/ + SysTick_Config(Chip_Clock_GetRate(CLK_MX_MXCORE) / 100); + +#ifdef RT_USING_SERIAL + rt_hw_serial_init(); + +#ifdef RT_USING_CONSOLE + rt_console_set_device(RT_CONSOLE_DEVICE_NAME); +#endif +#endif +} + +/*@}*/ diff --git a/bsp/xplorer4330/drivers/platform.h b/bsp/xplorer4330/drivers/platform.h new file mode 100644 index 0000000000..50bc17e071 --- /dev/null +++ b/bsp/xplorer4330/drivers/platform.h @@ -0,0 +1,19 @@ +/* + * File : platform.h + * This file is part of RT-Thread RTOS + * COPYRIGHT (C) 2012, RT-Thread Development Team + * + * The license and distribution terms for this file may be + * found in the file LICENSE in this distribution or at + * http://www.rt-thread.org/license/LICENSE + * + * Change Logs: + * Date Author Notes + */ + +#ifndef __PLATFORM_H__ +#define __PLATFORM_H__ + +void rt_hw_board_init(void); + +#endif diff --git a/bsp/xplorer4330/drivers/usart.c b/bsp/xplorer4330/drivers/usart.c new file mode 100644 index 0000000000..8866519343 --- /dev/null +++ b/bsp/xplorer4330/drivers/usart.c @@ -0,0 +1,394 @@ +/* + * File : usart.c + * mb9bf506r uart driver + * This file is part of RT-Thread RTOS + * COPYRIGHT (C) 2006 - 2012, RT-Thread Development Team + * + * The license and distribution terms for this file may be + * found in the file LICENSE in this distribution or at + * http://www.rt-thread.org/license/LICENSE + * + * Change Logs: + * Date Author Notes + * 2012-11-30 lgnq first version + */ + +#include +#include +#include "usart.h" +#include "uart_18xx_43xx.h" +#include "scu_18xx_43xx.h" + +#if defined(RT_USING_UART0) +/* UART0 device driver structure */ +struct serial_ringbuffer uart0_int_rx; +struct uart_device uart0 = +{ + LPC_USART0, + USART0_IRQn, +}; +struct rt_serial_device serial0; + +void UART0_IRQHandler(void) +{ + UART_Int_Status status; + + /* enter interrupt */ + rt_interrupt_enter(); + + status = Chip_UART_GetIntStatus(LPC_USART0); + + /* error */ + if (status == UART_ERROR) + { + return; + } + + /* ready for Read Data */ + if (status & READY_TO_RECEIVE) + { + rt_hw_serial_isr(&serial0); + } + + /* leave interrupt */ + rt_interrupt_leave(); +} +#endif + +#if defined(RT_USING_UART1) +/* UART1 device driver structure */ +struct serial_ringbuffer uart1_int_rx; +struct uart_device uart1 = +{ + LPC_UART1, + USART1_IRQn, +}; +struct rt_serial_device serial1; + +void UART1_IRQHandler(void) +{ + UART_Int_Status status; + + /* enter interrupt */ + rt_interrupt_enter(); + + status = Chip_UART_GetIntStatus(LPC_UART1); + + /* error */ + if (status == UART_ERROR) + { + return; + } + + /* ready for Read Data */ + if (status & READY_TO_RECEIVE) + { + rt_hw_serial_isr(&serial1); + } + + /* leave interrupt */ + rt_interrupt_leave(); +} +#endif + +#if defined(RT_USING_UART2) +/* UART2 device driver structure */ +struct serial_ringbuffer uart2_int_rx; +struct uart_device uart2 = +{ + LPC_USART2, + USART2_IRQn, +}; +struct rt_serial_device serial2; + +void UART2_IRQHandler(void) +{ + UART_Int_Status status; + + /* enter interrupt */ + rt_interrupt_enter(); + + status = Chip_UART_GetIntStatus(LPC_USART2); + + /* error */ + if (status == UART_ERROR) + { + return; + } + + /* ready for Read Data */ + if (status & READY_TO_RECEIVE) + { + rt_hw_serial_isr(&serial2); + } + + /* leave interrupt */ + rt_interrupt_leave(); +} +#endif + +#if defined(RT_USING_UART3) +/* UART3 device driver structure */ +struct serial_ringbuffer uart3_int_rx; +struct uart_device uart3 = +{ + LPC_USART3, + USART3_IRQn, +}; +struct rt_serial_device serial3; + +void UART3_IRQHandler(void) +{ + UART_Int_Status status; + + /* enter interrupt */ + rt_interrupt_enter(); + + status = Chip_UART_GetIntStatus(LPC_USART3); + + /* error */ + if (status == UART_ERROR) + { + return; + } + + /* ready for Read Data */ + if (status & READY_TO_RECEIVE) + { + rt_hw_serial_isr(&serial3); + } + + /* leave interrupt */ + rt_interrupt_leave(); +} +#endif + +void uart_pin_setup(void) +{ +#if defined(RT_USING_UART0) + Chip_SCU_PinMux(0x6, 4, MD_PDN, FUNC2); /* P6.5 : UART0_TXD */ + Chip_SCU_PinMux(0x6, 5, MD_PLN | MD_EZI | MD_ZI, FUNC2); /* P6.4 : UART0_RXD */ +#endif + +#if defined(RT_USING_UART1) + Chip_SCU_PinMux(0x1, 13, MD_PDN, FUNC2); /* P1.13 : UART1_TXD */ + Chip_SCU_PinMux(0x1, 14, MD_PLN | MD_EZI | MD_ZI, FUNC2); /* P1.14 : UART1_RX */ +#endif +} + +static rt_err_t uart_configure(struct rt_serial_device *serial, struct serial_configure *cfg) +{ + struct uart_device *uart; + UART_DATABIT_Type databit; + UART_STOPBIT_Type stopbit; + UART_PARITY_Type parity; + + /* UART FIFO configuration Struct variable */ + UART_FIFO_CFG_Type UARTFIFOConfigStruct; + + RT_ASSERT(serial != RT_NULL); + + uart = (struct uart_device *)serial->parent.user_data; + + Chip_UART_Init(uart->uart_regs); + + Chip_UART_SetBaud(uart->uart_regs, cfg->baud_rate); + + /* set stop bits */ + switch (cfg->stop_bits) + { + case STOP_BITS_1: + stopbit = UART_STOPBIT_1; + break; + case STOP_BITS_2: + stopbit = UART_STOPBIT_2; + break; + default: + return RT_ERROR; + } + + /* set data bits */ + switch (cfg->data_bits) + { + case DATA_BITS_5: + databit = UART_DATABIT_5; + break; + case DATA_BITS_6: + databit = UART_DATABIT_6; + break; + case DATA_BITS_7: + databit = UART_DATABIT_7; + break; + case DATA_BITS_8: + databit = UART_DATABIT_8; + break; + default: + return RT_ERROR; + } + + /* set parity */ + switch (cfg->parity) + { + case PARITY_NONE: + parity = UART_PARITY_NONE; + break; + case PARITY_EVEN: + parity = UART_PARITY_EVEN; + break; + case PARITY_ODD: + parity = UART_PARITY_ODD; + break; + default: + return RT_ERROR; + } + + Chip_UART_ConfigData(uart->uart_regs, databit, parity, stopbit); + + /* Enable UART Transmit */ + Chip_UART_TxCmd(uart->uart_regs, ENABLE); + + Chip_UART_FIFOConfigStructInit(&UARTFIFOConfigStruct); + + /* Enable DMA mode in UART */ + UARTFIFOConfigStruct.FIFO_DMAMode = ENABLE; + /* Initialize FIFO for UART0 peripheral */ + Chip_UART_FIFOConfig(uart->uart_regs, &UARTFIFOConfigStruct); + + /* Enable UART Rx interrupt */ + Chip_UART_IntConfig(uart->uart_regs, UART_INTCFG_RBR, ENABLE); + /* Enable UART line status interrupt */ + Chip_UART_IntConfig(uart->uart_regs, UART_INTCFG_RLS, ENABLE); + + /* Enable Interrupt for UART channel */ + /* Priority = 1 */ + NVIC_SetPriority(uart->irq_num, 1); + + return RT_EOK; +} + +static rt_err_t uart_control(struct rt_serial_device *serial, int cmd, void *arg) +{ + struct uart_device *uart; + + RT_ASSERT(serial != RT_NULL); + uart = (struct uart_device *)serial->parent.user_data; + + switch (cmd) + { + case RT_DEVICE_CTRL_CLR_INT: + /* disable rx irq */ + UART_DISABLE_IRQ(uart->irq_num); + break; + case RT_DEVICE_CTRL_SET_INT: + /* enable rx irq */ + UART_ENABLE_IRQ(uart->irq_num); + break; + } + + return (RT_EOK); +} + +static int uart_putc(struct rt_serial_device *serial, char c) +{ + struct uart_device *uart; + + RT_ASSERT(serial != RT_NULL); + + uart = (struct uart_device *)serial->parent.user_data; + + /* wait send buffer is empty */ + while (!(uart->uart_regs->LSR & UART_LSR_THRE)) + ; + /* write to send buffer */ + uart->uart_regs->THR = c & UART_THR_MASKBIT; + + return (1); +} + +static int uart_getc(struct rt_serial_device *serial) +{ + struct uart_device *uart; + uint8_t ch; + + RT_ASSERT(serial != RT_NULL); + + uart = (struct uart_device *)serial->parent.user_data; + + /* receive buffer is full */ + if (uart->uart_regs->LSR & UART_LSR_RDR) + { + ch = uart->uart_regs->RBR & UART_RBR_MASKBIT; + + return (ch); + } + else + return (-1); +} + +static struct rt_uart_ops uart_ops = +{ + uart_configure, + uart_control, + uart_putc, + uart_getc, +}; + +void rt_hw_serial_init(void) +{ + struct serial_configure config; + + config.baud_rate = BAUD_RATE_115200; + config.data_bits = DATA_BITS_8; + config.parity = PARITY_NONE; + config.stop_bits = STOP_BITS_1; + + uart_pin_setup(); + +#if defined(RT_USING_UART0) + serial0.ops = &uart_ops; + serial0.int_rx = &uart0_int_rx; + serial0.config = config; + + /* register UART0 device */ + rt_hw_serial_register(&serial0, + "uart0", + RT_DEVICE_FLAG_RDWR | RT_DEVICE_FLAG_INT_RX | RT_DEVICE_FLAG_STREAM, + &uart0); +#endif + +#if defined(RT_USING_UART1) + serial1.ops = &uart_ops; + serial1.int_rx = &uart1_int_rx; + serial1.config = config; + + /* register UART1 device */ + rt_hw_serial_register(&serial1, + "uart1", + RT_DEVICE_FLAG_RDWR | RT_DEVICE_FLAG_INT_RX | RT_DEVICE_FLAG_STREAM, + &uart1); +#endif + +#if defined(RT_USING_UART2) + serial2.ops = &uart_ops; + serial2.int_rx = &uart2_int_rx; + serial2.config = config; + + /* register UART2 device */ + rt_hw_serial_register(&serial2, + "uart2", + RT_DEVICE_FLAG_RDWR | RT_DEVICE_FLAG_INT_RX | RT_DEVICE_FLAG_STREAM, + &uart2); +#endif + +#if defined(RT_USING_UART3) + serial3.ops = &uart_ops; + serial3.int_rx = &uart3_int_rx; + serial3.config = config; + + /* register UART3 device */ + rt_hw_serial_register(&serial3, + "uart3", + RT_DEVICE_FLAG_RDWR | RT_DEVICE_FLAG_INT_RX | RT_DEVICE_FLAG_STREAM, + &uart3); +#endif +} diff --git a/bsp/xplorer4330/drivers/usart.h b/bsp/xplorer4330/drivers/usart.h new file mode 100644 index 0000000000..e8d9c42ed9 --- /dev/null +++ b/bsp/xplorer4330/drivers/usart.h @@ -0,0 +1,39 @@ +/* + * File : usart.h + * This file is part of RT-Thread RTOS + * COPYRIGHT (C) 2006, RT-Thread Development Team + * + * The license and distribution terms for this file may be + * found in the file LICENSE in this distribution or at + * http://www.rt-thread.org/license/LICENSE + * + * Change Logs: + * Date Author Notes + * 2011-05-15 lgnq modified according bernard's implementaion. + */ + +#ifndef __USART_H__ +#define __USART_H__ + +#include + +#include "chip_lpc43xx.h" +#include "cmsis.h" + +/** + * Enable/DISABLE Interrupt Controller + */ +#define UART_ENABLE_IRQ(n) NVIC_EnableIRQ((n)) +#define UART_DISABLE_IRQ(n) NVIC_DisableIRQ((n)) + +struct uart_device +{ + LPC_USART_Type *uart_regs; + + /* irq number */ + IRQn_Type irq_num; +}; + +void rt_hw_serial_init(void); + +#endif diff --git a/bsp/xplorer4330/libraries/SConscript b/bsp/xplorer4330/libraries/SConscript new file mode 100644 index 0000000000..1cb7618499 --- /dev/null +++ b/bsp/xplorer4330/libraries/SConscript @@ -0,0 +1,14 @@ +# for module compiling +import os +from building import * + +cwd = GetCurrentDir() +objs = [] +list = os.listdir(cwd) + +for d in list: + path = os.path.join(cwd, d) + if os.path.isfile(os.path.join(path, 'SConscript')): + objs = objs + SConscript(os.path.join(d, 'SConscript')) + +Return('objs') diff --git a/bsp/xplorer4330/libraries/lpc_board/SConscript b/bsp/xplorer4330/libraries/lpc_board/SConscript new file mode 100644 index 0000000000..f69be2d1b8 --- /dev/null +++ b/bsp/xplorer4330/libraries/lpc_board/SConscript @@ -0,0 +1,44 @@ +Import('RTT_ROOT') +Import('rtconfig') +from building import * + +cwd = GetCurrentDir() + +#src = Glob('board_common/*.c') +src = [] +path = [cwd + '/board_common'] + +if rtconfig.LPC43xx_BOARD == 'NGX_XPLORER_4330': + src += ['boards_18xx_43xx/ngx_xplorer_18304330/board_ngx_xplorer_18304330.c', + 'boards_18xx_43xx/ngx_xplorer_18304330/sysinit_ngx_xplorer_18304330.c'] + path += [cwd + '/boards_18xx_43xx/ngx_xplorer_18304330', + cwd + '/boards_18xx_43xx/ngx_xplorer_18304330/ngx_xplorer_4330'] +elif rtconfig.LPC43xx_BOARD == 'NGX_XPLORER_1830': + src += ['boards_18xx_43xx/ngx_xplorer_18304330/board_ngx_xplorer_18304330.c', + 'boards_18xx_43xx/ngx_xplorer_18304330/sysinit_ngx_xplorer_18304330.c'] + path += [cwd + '/boards_18xx_43xx/ngx_xplorer_18304330', + cwd + '/boards_18xx_43xx/ngx_xplorer_18304330/ngx_xplorer_1830'] +elif rtconfig.LPC43xx_BOARD == 'KEIL_MCB_4357': + src += ['boards_18xx_43xx/keil_mcb_18574357/board_keil_mcb_18574357.c', + 'boards_18xx_43xx/keil_mcb_18574357/sysinit_keil_mcb_18574357.c'] + path += [cwd + '/boards_18xx_43xx/keil_mcb_18574357', + cwd + '/boards_18xx_43xx/keil_mcb_18574357/keil_mcb_4357'] +elif rtconfig.LPC43xx_BOARD == 'KEIL_MCB_1857': + src += ['boards_18xx_43xx/keil_mcb_18574357/board_keil_mcb_18574357.c', + 'boards_18xx_43xx/keil_mcb_18574357/sysinit_keil_mcb_18574357.c'] + path += [cwd + '/boards_18xx_43xx/keil_mcb_18574357', + cwd + '/boards_18xx_43xx/keil_mcb_18574357/keil_mcb_1857'] +elif rtconfig.LPC43xx_BOARD == 'HITEX_EVA_4350': + src += ['boards_18xx_43xx/hitex_eva_18504350/board_hitex_eva_18504350.c', + 'boards_18xx_43xx/hitex_eva_18504350/sysinit_hitex_eva_18504350.c'] + path += [cwd + '/boards_18xx_43xx/hitex_eva_18504350', + cwd + '/boards_18xx_43xx/hitex_eva_18504350/hitex_eva_4350'] +elif rtconfig.LPC43xx_BOARD == 'HITEX_EVA_1850': + src += ['boards_18xx_43xx/hitex_eva_18504350/board_hitex_eva_18504350.c', + 'boards_18xx_43xx/hitex_eva_18504350/sysinit_hitex_eva_18504350.c'] + path += [cwd + '/boards_18xx_43xx/hitex_eva_18504350', + cwd + '/boards_18xx_43xx/hitex_eva_18504350/hitex_eva_1850'] + +group = DefineGroup('lpc_board', src, depend = [''], CPPPATH = path) + +Return('group') diff --git a/bsp/xplorer4330/libraries/lpc_board/board_common/Retarget.c b/bsp/xplorer4330/libraries/lpc_board/board_common/Retarget.c new file mode 100644 index 0000000000..3b47f8bde5 --- /dev/null +++ b/bsp/xplorer4330/libraries/lpc_board/board_common/Retarget.c @@ -0,0 +1,253 @@ +/* + * @brief IO redirection support + * + * This file adds re-direction support to the library for various + * projects. It can be configured in one of 3 ways - no redirection, + * redirection via a UART, or redirection via semihosting. If DEBUG + * is not defined, all printf statements will do nothing with the + * output being throw away. If DEBUG is defined, then the choice of + * output is selected by the DEBUG_SEMIHOSTING define. If the + * DEBUG_SEMIHOSTING is not defined, then output is redirected via + * the UART. If DEBUG_SEMIHOSTING is defined, then output will be + * attempted to be redirected via semihosting. If the UART method + * is used, then the Board_UARTPutChar and Board_UARTGetChar + * functions must be defined to be used by this driver and the UART + * must already be initialized to the correct settings. + * + * @note + * Copyright(C) NXP Semiconductors, 2012 + * All rights reserved. + * + * @par + * Software that is described herein is for illustrative purposes only + * which provides customers with programming information regarding the + * LPC products. This software is supplied "AS IS" without any warranties of + * any kind, and NXP Semiconductors and its licensor disclaim any and + * all warranties, express or implied, including all implied warranties of + * merchantability, fitness for a particular purpose and non-infringement of + * intellectual property rights. NXP Semiconductors assumes no responsibility + * or liability for the use of the software, conveys no license or rights under any + * patent, copyright, mask work right, or any other intellectual property rights in + * or to any products. NXP Semiconductors reserves the right to make changes + * in the software without notification. NXP Semiconductors also makes no + * representation or warranty that such application will be suitable for the + * specified use without further testing or modification. + * + * @par + * Permission to use, copy, modify, and distribute this software and its + * documentation is hereby granted, under NXP Semiconductors' and its + * licensor's relevant copyrights in the software, without fee, provided that it + * is used in conjunction with NXP Semiconductors microcontrollers. This + * copyright, permission, and disclaimer notice must appear in all copies of + * this code. + */ + +#include "sys_config.h" +#include "board.h" + +/* Keil (Realview) support */ +#if defined(__CC_ARM) + +#include +#include + +#if defined(DEBUG) +#if defined(DEBUG_SEMIHOSTING) +#define ITM_Port8(n) (*((volatile unsigned char *) (0xE0000000 + 4 * n))) +#define ITM_Port16(n) (*((volatile unsigned short *) (0xE0000000 + 4 * n))) +#define ITM_Port32(n) (*((volatile unsigned long *) (0xE0000000 + 4 * n))) + +#define DEMCR (*((volatile unsigned long *) (0xE000EDFC))) +#define TRCENA 0x01000000 + +/* Write to SWO */ +void _ttywrch(int ch) +{ + if (DEMCR & TRCENA) { + while (ITM_Port32(0) == 0) {} + ITM_Port8(0) = ch; + } +} + +#else +static INLINE void BoardOutChar(char ch) +{ + Board_UARTPutChar(ch); +} + +#endif /* defined(DEBUG_SEMIHOSTING) */ +#endif /* defined(DEBUG) */ + +struct __FILE { + int handle; +}; + +FILE __stdout; +FILE __stdin; +FILE __stderr; + +void *_sys_open(const char *name, int openmode) +{ + return 0; +} + +int fputc(int c, FILE *f) +{ +#if defined(DEBUG) +#if defined(DEBUG_SEMIHOSTING) + _ttywrch(c); +#else + BoardOutChar((char) c); +#endif +#endif + return 0; +} + +int fgetc(FILE *f) +{ +#if defined(DEBUG) && !defined(DEBUG_SEMIHOSTING) + return Board_UARTGetChar(); +#else + return 0; +#endif +} + +int ferror(FILE *f) +{ + return EOF; +} + +void _sys_exit(int return_code) +{ +label: goto label; /* endless loop */ +} + +#endif /* defined (__CC_ARM) */ + +/* IAR support */ +#if defined(__ICCARM__) +/******************* + * + * Copyright 1998-2003 IAR Systems. All rights reserved. + * + * $Revision: 30870 $ + * + * This is a template implementation of the "__write" function used by + * the standard library. Replace it with a system-specific + * implementation. + * + * The "__write" function should output "size" number of bytes from + * "buffer" in some application-specific way. It should return the + * number of characters written, or _LLIO_ERROR on failure. + * + * If "buffer" is zero then __write should perform flushing of + * internal buffers, if any. In this case "handle" can be -1 to + * indicate that all handles should be flushed. + * + * The template implementation below assumes that the application + * provides the function "MyLowLevelPutchar". It should return the + * character written, or -1 on failure. + * + ********************/ + +#include + +_STD_BEGIN + +#pragma module_name = "?__write" + +#if defined(DEBUG) +#if defined(DEBUG_SEMIHOSTING) +#error Semihosting support not yet working on IAR +#endif /* defined(DEBUG_SEMIHOSTING) */ +#endif /* defined(DEBUG) */ + +/* + If the __write implementation uses internal buffering, uncomment + the following line to ensure that we are called with "buffer" as 0 + (i.e. flush) when the application terminates. */ +size_t __write(int handle, const unsigned char *buffer, size_t size) +{ +#if defined(DEBUG) + size_t nChars = 0; + + if (buffer == 0) { + /* + This means that we should flush internal buffers. Since we + don't we just return. (Remember, "handle" == -1 means that all + handles should be flushed.) + */ + return 0; + } + + /* This template only writes to "standard out" and "standard err", + for all other file handles it returns failure. */ + if (( handle != _LLIO_STDOUT) && ( handle != _LLIO_STDERR) ) { + return _LLIO_ERROR; + } + + for ( /* Empty */; size != 0; --size) { + Board_UARTPutChar(*buffer++); + ++nChars; + } + + return nChars; +#else + return size; +#endif /* defined(DEBUG) */ +} + +_STD_END + +#endif /* defined (__ICCARM__) */ + +#if defined( __GNUC__ ) +/* Include stdio.h to pull in __REDLIB_INTERFACE_VERSION__ */ +#include + +#if (__REDLIB_INTERFACE_VERSION__ >= 20000) +/* We are using new Redlib_v2 semihosting interface */ + #define WRITEFUNC __sys_write + #define READFUNC __sys_readc +#else +/* We are using original Redlib semihosting interface */ + #define WRITEFUNC __write + #define READFUNC __readc +#endif + +#if defined(DEBUG) +#if defined(DEBUG_SEMIHOSTING) +/* Do nothing, semihosting is enabled by default in LPCXpresso */ +#endif /* defined(DEBUG_SEMIHOSTING) */ +#endif /* defined(DEBUG) */ + +#if !defined(DEBUG_SEMIHOSTING) +int WRITEFUNC(int iFileHandle, char *pcBuffer, int iLength) +{ +#if defined(DEBUG) + unsigned int i; + for (i = 0; i < iLength; i++) { + Board_UARTPutChar(pcBuffer[i]); + } +#endif + + return iLength; +} + +/* Called by bottom level of scanf routine within RedLib C library to read + a character. With the default semihosting stub, this would read the character + from the debugger console window (which acts as stdin). But this version reads + the character from the LPC1768/RDB1768 UART. */ +int READFUNC(void) +{ +#if defined(DEBUG) + char c = Board_UARTGetChar(); + return (int) c; + +#else + return (int) -1; +#endif +} + +#endif /* !defined(DEBUG_SEMIHOSTING) */ +#endif /* defined ( __GNUC__ ) */ diff --git a/bsp/xplorer4330/libraries/lpc_board/board_common/board_api.h b/bsp/xplorer4330/libraries/lpc_board/board_common/board_api.h new file mode 100644 index 0000000000..4fc4bdac58 --- /dev/null +++ b/bsp/xplorer4330/libraries/lpc_board/board_common/board_api.h @@ -0,0 +1,176 @@ +/* + * @brief Common board API functions + * + * @note + * Copyright(C) NXP Semiconductors, 2012 + * All rights reserved. + * + * @par + * Software that is described herein is for illustrative purposes only + * which provides customers with programming information regarding the + * LPC products. This software is supplied "AS IS" without any warranties of + * any kind, and NXP Semiconductors and its licensor disclaim any and + * all warranties, express or implied, including all implied warranties of + * merchantability, fitness for a particular purpose and non-infringement of + * intellectual property rights. NXP Semiconductors assumes no responsibility + * or liability for the use of the software, conveys no license or rights under any + * patent, copyright, mask work right, or any other intellectual property rights in + * or to any products. NXP Semiconductors reserves the right to make changes + * in the software without notification. NXP Semiconductors also makes no + * representation or warranty that such application will be suitable for the + * specified use without further testing or modification. + * + * @par + * Permission to use, copy, modify, and distribute this software and its + * documentation is hereby granted, under NXP Semiconductors' and its + * licensor's relevant copyrights in the software, without fee, provided that it + * is used in conjunction with NXP Semiconductors microcontrollers. This + * copyright, permission, and disclaimer notice must appear in all copies of + * this code. + */ + +#ifndef __BOARD_API_H_ +#define __BOARD_API_H_ + +#include "lpc_types.h" +#include + +#ifdef __cplusplus +extern "C" { +#endif + +/** @defgroup BOARD_COMMON_API BOARD: Common board functions + * @ingroup BOARD_Common + * This file contains common board definitions that are shared across + * boards and devices. All of these functions do not need to be + * impemented for a specific board, but if they are implemented, they + * should use this API standard. + * @{ + */ + +/** + * @brief Set up and initialize all required blocks and functions related to the board hardware. + * @return None + */ +void Board_Init(void); + +/** + * @brief Initializes board UART for output, required for printf redirection + * @return None + */ +void Board_Debug_Init(void); + +/** + * @brief Sends a single character on the UART, required for printf redirection + * @param ch : character to send + * @return None + */ +void Board_UARTPutChar(char ch); + +/** + * @brief Get a single character from the UART, required for scanf input + * @return EOF if not character was received, or character value + */ +int Board_UARTGetChar(void); + +/** + * @brief Prints a string to the UART + * @param str : Terminated string to output + * @return None + */ +void Board_UARTPutSTR(char *str); + +/** + * @brief Initializes board LED(s) + * @return None + */ +void Board_LED_Init(void); + +/** + * @brief Sets the state of a board LED to on or off + * @param LEDNumber : LED number to set state for + * @param State : true for on, false for off + * @return None + */ +void Board_LED_Set(uint8_t LEDNumber, bool State); + +/** + * @brief Returns the current state of a board LED + * @param LEDNumber : LED number to set state for + * @return true if the LED is on, otherwise false + */ +bool Board_LED_Test(uint8_t LEDNumber); + +/** + * @brief Toggles the current state of a board LED + * @param LEDNumber : LED number to change state for + * @return None + */ +STATIC INLINE void Board_LED_Toggle(uint8_t LEDNumber) +{ + Board_LED_Set(LEDNumber, !Board_LED_Test(LEDNumber)); +} + + +/** + * @brief Current system clock rate, mainly used for sysTick + */ +extern uint32_t SystemCoreClock; + +/** + * @brief Update system core clock rate, should be called if the + * system has a clock rate change + * @return None + */ +void SystemCoreClockUpdate(void); + +/** + * @brief Turn on Board LCD Backlight + * @param Intensity : Backlight intensity (0 = off, >=1 = on) + * @return None + * On boards where a GPIO is used to control backlight on/off state, a '0' or '1' + * value will turn off or on the backlight. On some boards, a non-0 value will + * control backlight intensity via a PWN. For PWM systems, the intensity value + * is a percentage value between 0 and 100%. + */ +void Board_LCD_Set_Backlight(uint8_t Intensity); + +/** + * @brief Function prototype for a MS delay function. Board layers or example code may + * define this function as needed. + */ +typedef void (*p_msDelay_func_t)(uint32_t); + +/* The DEBUG* functions are selected based on system configuration. + Code that uses the DEBUG* functions will have their I/O routed to + the UART, semihosting, or nowhere. */ +#if defined(DEBUG) +#if defined(DEBUG_SEMIHOSTING) +#define DEBUGINIT() +#define DEBUGOUT(...) printf(__VA_ARGS__) +#define DEBUGSTR(str) printf(str) +#define DEBUGIN() (int) EOF + +#else +#define DEBUGINIT() Board_Debug_Init() +#define DEBUGOUT(...) printf(__VA_ARGS__) +#define DEBUGSTR(str) Board_UARTPutSTR(str) +#define DEBUGIN() Board_UARTGetChar() +#endif /* defined(DEBUG_SEMIHOSTING) */ + +#else +#define DEBUGINIT() +#define DEBUGOUT(...) +#define DEBUGSTR(str) +#define DEBUGIN() (int) EOF +#endif /* defined(DEBUG) */ + +/** + * @} + */ + +#ifdef __cplusplus +} +#endif + +#endif /* __BOARD_API_H_ */ diff --git a/bsp/xplorer4330/libraries/lpc_board/board_common/lpc_phy.h b/bsp/xplorer4330/libraries/lpc_board/board_common/lpc_phy.h new file mode 100644 index 0000000000..e9dce882c5 --- /dev/null +++ b/bsp/xplorer4330/libraries/lpc_board/board_common/lpc_phy.h @@ -0,0 +1,90 @@ +/* + * @brief Common PHY functions + * + * @note + * Copyright(C) NXP Semiconductors, 2012 + * All rights reserved. + * + * @par + * Software that is described herein is for illustrative purposes only + * which provides customers with programming information regarding the + * LPC products. This software is supplied "AS IS" without any warranties of + * any kind, and NXP Semiconductors and its licensor disclaim any and + * all warranties, express or implied, including all implied warranties of + * merchantability, fitness for a particular purpose and non-infringement of + * intellectual property rights. NXP Semiconductors assumes no responsibility + * or liability for the use of the software, conveys no license or rights under any + * patent, copyright, mask work right, or any other intellectual property rights in + * or to any products. NXP Semiconductors reserves the right to make changes + * in the software without notification. NXP Semiconductors also makes no + * representation or warranty that such application will be suitable for the + * specified use without further testing or modification. + * + * @par + * Permission to use, copy, modify, and distribute this software and its + * documentation is hereby granted, under NXP Semiconductors' and its + * licensor's relevant copyrights in the software, without fee, provided that it + * is used in conjunction with NXP Semiconductors microcontrollers. This + * copyright, permission, and disclaimer notice must appear in all copies of + * this code. + */ + +#ifndef __LPC_PHY_H_ +#define __LPC_PHY_H_ + +#include "board.h" +#include "chip.h" + +#ifdef __cplusplus +extern "C" { +#endif + +/** @defgroup BOARD_PHY BOARD: Board specific PHY drivers + * @ingroup BOARD_Common + * The simple PHY function API provides simple non-blocking PHY status + * monitoring and initialization support for various Ethernet PHYs. + * To initialize the PHY, call lpc_phy_init() once. lpc_phy_init() requires + * several standard functions from the MAC driver for interfacing to the + * PHY via a MII link (Chip_ENET_Start_MII_Write(), Chip_ENET_Is_MII_Busy(), + * Chip_ENET_Start_MII_Read(), and Chip_ENET_Read_MII_Data()). + * + * Once initialized, just preiodically call the lpcPHYStsPoll() function + * from the background loop or a thread and monitor the returned status + * to determine if the PHY state has changed and the current PHY state. + * @{ + */ +#define PHY_LINK_ERROR (1 << 0) /*!< PHY status bit for link error */ +#define PHY_LINK_BUSY (1 << 1) /*!< PHY status bit for MII link busy */ +#define PHY_LINK_CHANGED (1 << 2) /*!< PHY status bit for changed state (not persistent) */ +#define PHY_LINK_CONNECTED (1 << 3) /*!< PHY status bit for connected state */ +#define PHY_LINK_SPEED100 (1 << 4) /*!< PHY status bit for 100Mbps mode */ +#define PHY_LINK_FULLDUPLX (1 << 5) /*!< PHY status bit for full duplex mode */ + +/** + * @brief Phy status update state machine + * @return An Or'ed value of PHY_LINK_* statuses + * This function can be called at any rate and will poll the the PHY status. Multiple + * calls may be needed to determine PHY status. + */ +uint32_t lpcPHYStsPoll(void); + +/** + * @brief Initialize the PHY + * @param rmii : Initializes PHY for RMII mode if true, MII if false + * @param pDelayMsFunc : Delay function (in mS) used for this driver + * @return PHY_LINK_ERROR or 0 on success + * This function initializes the PHY. It will block until complete. It will not + * wait for the PHY to detect a connected cable and remain busy. Use lpcPHYStsPoll to + * detect cable insertion. + */ +uint32_t lpc_phy_init(bool rmii, p_msDelay_func_t pDelayMsFunc); + +/** + * @} + */ + +#ifdef __cplusplus +} +#endif + +#endif /* __LPC_PHY_H_ */ diff --git a/bsp/xplorer4330/libraries/lpc_board/board_common/lpc_phy_dp83848.c b/bsp/xplorer4330/libraries/lpc_board/board_common/lpc_phy_dp83848.c new file mode 100644 index 0000000000..e83ae64de2 --- /dev/null +++ b/bsp/xplorer4330/libraries/lpc_board/board_common/lpc_phy_dp83848.c @@ -0,0 +1,281 @@ +/* + * @brief Mational DP83848 simple PHY driver + * + * @note + * Copyright(C) NXP Semiconductors, 2012 + * All rights reserved. + * + * @par + * Software that is described herein is for illustrative purposes only + * which provides customers with programming information regarding the + * LPC products. This software is supplied "AS IS" without any warranties of + * any kind, and NXP Semiconductors and its licensor disclaim any and + * all warranties, express or implied, including all implied warranties of + * merchantability, fitness for a particular purpose and non-infringement of + * intellectual property rights. NXP Semiconductors assumes no responsibility + * or liability for the use of the software, conveys no license or rights under any + * patent, copyright, mask work right, or any other intellectual property rights in + * or to any products. NXP Semiconductors reserves the right to make changes + * in the software without notification. NXP Semiconductors also makes no + * representation or warranty that such application will be suitable for the + * specified use without further testing or modification. + * + * @par + * Permission to use, copy, modify, and distribute this software and its + * documentation is hereby granted, under NXP Semiconductors' and its + * licensor's relevant copyrights in the software, without fee, provided that it + * is used in conjunction with NXP Semiconductors microcontrollers. This + * copyright, permission, and disclaimer notice must appear in all copies of + * this code. + */ + +#include "chip.h" +#include "lpc_phy.h" + +/** @defgroup DP83848_PHY BOARD: PHY status and control driver for the DP83848 + * @ingroup BOARD_PHY + * Various functions for controlling and monitoring the status of the + * DP83848 PHY. + * @{ + */ + +/** @brief DP83848 PHY register offsets */ +#define DP8_BMCR_REG 0x0 /*!< Basic Mode Control Register */ +#define DP8_BMSR_REG 0x1 /*!< Basic Mode Status Reg */ +#define DP8_ANADV_REG 0x4 /*!< Auto_Neg Advt Reg */ +#define DP8_ANLPA_REG 0x5 /*!< Auto_neg Link Partner Ability Reg */ +#define DP8_ANEEXP_REG 0x6 /*!< Auto-neg Expansion Reg */ +#define DP8_PHY_STAT_REG 0x10/*!< PHY Status Register */ +#define DP8_PHY_INT_CTL_REG 0x11/*!< PHY Interrupt Control Register */ +#define DP8_PHY_RBR_REG 0x17/*!< PHY RMII and Bypass Register */ +#define DP8_PHY_STS_REG 0x19/*!< PHY Status Register */ + +/* DP83848 Control register definitions */ +#define DP8_RESET (1 << 15) /*!< 1= S/W Reset */ +#define DP8_LOOPBACK (1 << 14) /*!< 1=loopback Enabled */ +#define DP8_SPEED_SELECT (1 << 13) /*!< 1=Select 100MBps */ +#define DP8_AUTONEG (1 << 12) /*!< 1=Enable auto-negotiation */ +#define DP8_POWER_DOWN (1 << 11) /*!< 1=Power down PHY */ +#define DP8_ISOLATE (1 << 10) /*!< 1=Isolate PHY */ +#define DP8_RESTART_AUTONEG (1 << 9) /*!< 1=Restart auto-negoatiation */ +#define DP8_DUPLEX_MODE (1 << 8) /*!< 1=Full duplex mode */ +#define DP8_COLLISION_TEST (1 << 7) /*!< 1=Perform collsion test */ + +/* DP83848 Status register definitions */ +#define DP8_100BASE_T4 (1 << 15) /*!< T4 mode */ +#define DP8_100BASE_TX_FD (1 << 14) /*!< 100MBps full duplex */ +#define DP8_100BASE_TX_HD (1 << 13) /*!< 100MBps half duplex */ +#define DP8_10BASE_T_FD (1 << 12) /*!< 100Bps full duplex */ +#define DP8_10BASE_T_HD (1 << 11) /*!< 10MBps half duplex */ +#define DP8_MF_PREAMB_SUPPR (1 << 6) /*!< Preamble suppress */ +#define DP8_AUTONEG_COMP (1 << 5) /*!< Auto-negotation complete */ +#define DP8_RMT_FAULT (1 << 4) /*!< Fault */ +#define DP8_AUTONEG_ABILITY (1 << 3) /*!< Auto-negotation supported */ +#define DP8_LINK_STATUS (1 << 2) /*!< 1=Link active */ +#define DP8_JABBER_DETECT (1 << 1) /*!< Jabber detect */ +#define DP8_EXTEND_CAPAB (1 << 0) /*!< Supports extended capabilities */ + +/* DP83848 PHY RBR MII dode definitions */ +#define DP8_RBR_RMII_MODE (1 << 5) /*!< Use RMII mode */ + +/* DP83848 PHY status definitions */ +#define DP8_REMOTEFAULT (1 << 6) /*!< Remote fault */ +#define DP8_FULLDUPLEX (1 << 2) /*!< 1=full duplex */ +#define DP8_SPEED10MBPS (1 << 1) /*!< 1=10MBps speed */ +#define DP8_VALID_LINK (1 << 0) /*!< 1=Link active */ + +/* DP83848 PHY ID register definitions */ +#define DP8_PHYID1_OUI 0x2000 /*!< Expected PHY ID1 */ +#define DP8_PHYID2_OUI 0x5c90 /*!< Expected PHY ID2 */ + +/* DP83848 PHY update flags */ +static uint32_t physts, olddphysts; + +/* PHY update counter for state machine */ +static int32_t phyustate; + +/* Pointer to delay function used for this driver */ +static p_msDelay_func_t pDelayMs; + +/* Write to the PHY. Will block for delays based on the pDelayMs function. Returns + true on success, or false on failure */ +static Status lpc_mii_write(uint8_t reg, uint16_t data) +{ + Status sts = ERROR; + int32_t mst = 250; + + /* Write value for register */ + Chip_ENET_Start_MII_Write(reg, data); + + /* Wait for unbusy status */ + while (mst > 0) { + if (Chip_ENET_Is_MII_Busy()) { + mst--; + pDelayMs(1); + } + else { + mst = 0; + sts = SUCCESS; + } + } + + return sts; +} + +/* Read from the PHY. Will block for delays based on the pDelayMs function. Returns + true on success, or false on failure */ +static Status lpc_mii_read(uint8_t reg, uint16_t *data) +{ + Status sts = ERROR; + int32_t mst = 250; + + /* Start register read */ + Chip_ENET_Start_MII_Read(reg); + + /* Wait for unbusy status */ + while (mst > 0) { + if (!Chip_ENET_Is_MII_Busy()) { + mst = 0; + *data = Chip_ENET_Read_MII_Data(); + sts = SUCCESS; + } + else { + mst--; + pDelayMs(1); + } + } + + return sts; +} + +/* Update PHY status from passed value */ +static void lpc_update_phy_sts(uint16_t linksts) +{ + /* Update link active status */ + if (linksts & DP8_VALID_LINK) { + physts |= PHY_LINK_CONNECTED; + } + else { + physts &= ~PHY_LINK_CONNECTED; + } + + /* Full or half duplex */ + if (linksts & DP8_FULLDUPLEX) { + physts |= PHY_LINK_FULLDUPLX; + } + else { + physts &= ~PHY_LINK_FULLDUPLX; + } + + /* Configure 100MBit/10MBit mode. */ + if (linksts & DP8_SPEED10MBPS) { + physts &= ~PHY_LINK_SPEED100; + } + else { + physts |= PHY_LINK_SPEED100; + } + + /* If the status has changed, indicate via change flag */ + if ((physts & (PHY_LINK_SPEED100 | PHY_LINK_FULLDUPLX | PHY_LINK_CONNECTED)) != + (olddphysts & (PHY_LINK_SPEED100 | PHY_LINK_FULLDUPLX | PHY_LINK_CONNECTED))) { + olddphysts = physts; + physts |= PHY_LINK_CHANGED; + } +} + +/* Initialize the DP83848 PHY */ +uint32_t lpc_phy_init(bool rmii, p_msDelay_func_t pDelayMsFunc) +{ + uint16_t tmp; + int32_t i; + + pDelayMs = pDelayMsFunc; + + /* Initial states for PHY status and state machine */ + olddphysts = physts = phyustate = 0; + + /* Only first read and write are checked for failure */ + /* Put the DP83848C in reset mode and wait for completion */ + if (lpc_mii_write(DP8_BMCR_REG, DP8_RESET) != SUCCESS) { + return ERROR; + } + i = 400; + while (i > 0) { + pDelayMs(1); + if (lpc_mii_read(DP8_BMCR_REG, &tmp) != SUCCESS) { + return ERROR; + } + + if (!(tmp & (DP8_RESET | DP8_POWER_DOWN))) { + i = -1; + } + else { + i--; + } + } + /* Timeout? */ + if (i == 0) { + return ERROR; + } + +#if 0 + /* Setup link based on configuration options */ +#if PHY_USE_AUTONEG == 1 + tmp = DP8_AUTONEG; +#else + tmp = 0; +#endif +#if PHY_USE_100MBS == 1 + tmp |= DP8_SPEED_SELECT; +#endif +#if PHY_USE_FULL_DUPLEX == 1 + tmp |= DP8_DUPLEX_MODE; +#endif + +#else + tmp = DP8_AUTONEG; +#endif + + lpc_mii_write(DP8_BMCR_REG, tmp); + + /* Enable RMII mode for PHY */ + if (rmii) { + lpc_mii_write(DP8_PHY_RBR_REG, DP8_RBR_RMII_MODE); + } + + /* The link is not set active at this point, but will be detected + later */ + + return SUCCESS; +} + +/* Phy status update state machine */ +uint32_t lpcPHYStsPoll(void) +{ + switch (phyustate) { + default: + case 0: + /* Read BMSR to clear faults */ + Chip_ENET_Start_MII_Read(DP8_PHY_STAT_REG); + physts &= ~PHY_LINK_CHANGED; + physts = physts | PHY_LINK_BUSY; + phyustate = 1; + break; + + case 1: + /* Wait for read status state */ + if (!Chip_ENET_Is_MII_Busy()) { + /* Update PHY status */ + physts &= ~PHY_LINK_BUSY; + lpc_update_phy_sts(Chip_ENET_Read_MII_Data()); + phyustate = 0; + } + break; + } + + return physts; +} + +/** + * @} + */ diff --git a/bsp/xplorer4330/libraries/lpc_board/board_common/lpc_phy_smsc87x0.c b/bsp/xplorer4330/libraries/lpc_board/board_common/lpc_phy_smsc87x0.c new file mode 100644 index 0000000000..37d950afa7 --- /dev/null +++ b/bsp/xplorer4330/libraries/lpc_board/board_common/lpc_phy_smsc87x0.c @@ -0,0 +1,270 @@ +/* + * @brief SMSC 87x0 simple PHY driver + * + * @note + * Copyright(C) NXP Semiconductors, 2012 + * All rights reserved. + * + * @par + * Software that is described herein is for illustrative purposes only + * which provides customers with programming information regarding the + * LPC products. This software is supplied "AS IS" without any warranties of + * any kind, and NXP Semiconductors and its licensor disclaim any and + * all warranties, express or implied, including all implied warranties of + * merchantability, fitness for a particular purpose and non-infringement of + * intellectual property rights. NXP Semiconductors assumes no responsibility + * or liability for the use of the software, conveys no license or rights under any + * patent, copyright, mask work right, or any other intellectual property rights in + * or to any products. NXP Semiconductors reserves the right to make changes + * in the software without notification. NXP Semiconductors also makes no + * representation or warranty that such application will be suitable for the + * specified use without further testing or modification. + * + * @par + * Permission to use, copy, modify, and distribute this software and its + * documentation is hereby granted, under NXP Semiconductors' and its + * licensor's relevant copyrights in the software, without fee, provided that it + * is used in conjunction with NXP Semiconductors microcontrollers. This + * copyright, permission, and disclaimer notice must appear in all copies of + * this code. + */ + +#include "chip.h" +#include "lpc_phy.h" + +/** @defgroup SMSC87X0_PHY BOARD: PHY status and control driver for the SMSC 87x0 + * @ingroup BOARD_PHY + * Various functions for controlling and monitoring the status of the + * SMSC 87x0 PHY. + * @{ + */ + +/* LAN8720 PHY register offsets */ +#define LAN8_BCR_REG 0x0 /*!< Basic Control Register */ +#define LAN8_BSR_REG 0x1 /*!< Basic Status Reg */ +#define LAN8_PHYID1_REG 0x2 /*!< PHY ID 1 Reg */ +#define LAN8_PHYID2_REG 0x3 /*!< PHY ID 2 Reg */ +#define LAN8_PHYSPLCTL_REG 0x1F/*!< PHY special control/status Reg */ + +/* LAN8720 BCR register definitions */ +#define LAN8_RESET (1 << 15) /*!< 1= S/W Reset */ +#define LAN8_LOOPBACK (1 << 14) /*!< 1=loopback Enabled */ +#define LAN8_SPEED_SELECT (1 << 13) /*!< 1=Select 100MBps */ +#define LAN8_AUTONEG (1 << 12) /*!< 1=Enable auto-negotiation */ +#define LAN8_POWER_DOWN (1 << 11) /*!< 1=Power down PHY */ +#define LAN8_ISOLATE (1 << 10) /*!< 1=Isolate PHY */ +#define LAN8_RESTART_AUTONEG (1 << 9) /*!< 1=Restart auto-negoatiation */ +#define LAN8_DUPLEX_MODE (1 << 8) /*!< 1=Full duplex mode */ + +/* LAN8720 BSR register definitions */ +#define LAN8_100BASE_T4 (1 << 15) /*!< T4 mode */ +#define LAN8_100BASE_TX_FD (1 << 14) /*!< 100MBps full duplex */ +#define LAN8_100BASE_TX_HD (1 << 13) /*!< 100MBps half duplex */ +#define LAN8_10BASE_T_FD (1 << 12) /*!< 100Bps full duplex */ +#define LAN8_10BASE_T_HD (1 << 11) /*!< 10MBps half duplex */ +#define LAN8_AUTONEG_COMP (1 << 5) /*!< Auto-negotation complete */ +#define LAN8_RMT_FAULT (1 << 4) /*!< Fault */ +#define LAN8_AUTONEG_ABILITY (1 << 3) /*!< Auto-negotation supported */ +#define LAN8_LINK_STATUS (1 << 2) /*!< 1=Link active */ +#define LAN8_JABBER_DETECT (1 << 1) /*!< Jabber detect */ +#define LAN8_EXTEND_CAPAB (1 << 0) /*!< Supports extended capabilities */ + +/* LAN8720 PHYSPLCTL status definitions */ +#define LAN8_SPEEDMASK (7 << 2) /*!< Speed and duplex mask */ +#define LAN8_SPEED100F (6 << 2) /*!< 100BT full duplex */ +#define LAN8_SPEED10F (5 << 2) /*!< 10BT full duplex */ +#define LAN8_SPEED100H (2 << 2) /*!< 100BT half duplex */ +#define LAN8_SPEED10H (1 << 2) /*!< 10BT half duplex */ + +/* LAN8720 PHY ID 1/2 register definitions */ +#define LAN8_PHYID1_OUI 0x0007 /*!< Expected PHY ID1 */ +#define LAN8_PHYID2_OUI 0xC0F0 /*!< Expected PHY ID2, except last 4 bits */ + +/* DP83848 PHY update flags */ +static uint32_t physts, olddphysts; + +/* PHY update counter for state machine */ +static int32_t phyustate; + +/* Pointer to delay function used for this driver */ +static p_msDelay_func_t pDelayMs; + +/* Write to the PHY. Will block for delays based on the pDelayMs function. Returns + true on success, or false on failure */ +static Status lpc_mii_write(uint8_t reg, uint16_t data) +{ + Status sts = ERROR; + int32_t mst = 250; + + /* Write value for register */ + Chip_ENET_Start_MII_Write(reg, data); + + /* Wait for unbusy status */ + while (mst > 0) { + if (Chip_ENET_Is_MII_Busy()) { + mst--; + pDelayMs(1); + } + else { + mst = 0; + sts = SUCCESS; + } + } + + return sts; +} + +/* Read from the PHY. Will block for delays based on the pDelayMs function. Returns + true on success, or false on failure */ +static Status lpc_mii_read(uint8_t reg, uint16_t *data) +{ + Status sts = ERROR; + int32_t mst = 250; + + /* Start register read */ + Chip_ENET_Start_MII_Read(reg); + + /* Wait for unbusy status */ + while (mst > 0) { + if (!Chip_ENET_Is_MII_Busy()) { + mst = 0; + *data = Chip_ENET_Read_MII_Data(); + sts = SUCCESS; + } + else { + mst--; + pDelayMs(1); + } + } + + return sts; +} + +/* Update PHY status from passed value */ +static void smsc_update_phy_sts(uint16_t linksts, uint16_t sdsts) +{ + /* Update link active status */ + if (linksts & LAN8_LINK_STATUS) { + physts |= PHY_LINK_CONNECTED; + } + else { + physts &= ~PHY_LINK_CONNECTED; + } + + switch (sdsts & LAN8_SPEEDMASK) { + case LAN8_SPEED100F: + default: + physts |= PHY_LINK_SPEED100; + physts |= PHY_LINK_FULLDUPLX; + break; + + case LAN8_SPEED10F: + physts &= ~PHY_LINK_SPEED100; + physts |= PHY_LINK_FULLDUPLX; + break; + + case LAN8_SPEED100H: + physts |= PHY_LINK_SPEED100; + physts &= ~PHY_LINK_FULLDUPLX; + break; + + case LAN8_SPEED10H: + physts &= ~PHY_LINK_SPEED100; + physts &= ~PHY_LINK_FULLDUPLX; + break; + } + + /* If the status has changed, indicate via change flag */ + if ((physts & (PHY_LINK_SPEED100 | PHY_LINK_FULLDUPLX | PHY_LINK_CONNECTED)) != + (olddphysts & (PHY_LINK_SPEED100 | PHY_LINK_FULLDUPLX | PHY_LINK_CONNECTED))) { + olddphysts = physts; + physts |= PHY_LINK_CHANGED; + } +} + +/* Initialize the SMSC 87x0 PHY */ +uint32_t lpc_phy_init(bool rmii, p_msDelay_func_t pDelayMsFunc) +{ + uint16_t tmp; + int32_t i; + + pDelayMs = pDelayMsFunc; + + /* Initial states for PHY status and state machine */ + olddphysts = physts = phyustate = 0; + + /* Only first read and write are checked for failure */ + /* Put the DP83848C in reset mode and wait for completion */ + if (lpc_mii_write(LAN8_BCR_REG, LAN8_RESET) != SUCCESS) { + return ERROR; + } + i = 400; + while (i > 0) { + pDelayMs(1); + if (lpc_mii_read(LAN8_BCR_REG, &tmp) != SUCCESS) { + return ERROR; + } + + if (!(tmp & (LAN8_RESET | LAN8_POWER_DOWN))) { + i = -1; + } + else { + i--; + } + } + /* Timeout? */ + if (i == 0) { + return ERROR; + } + + /* Setup link */ + lpc_mii_write(LAN8_BCR_REG, LAN8_AUTONEG); + + /* The link is not set active at this point, but will be detected + later */ + + return SUCCESS; +} + +/* Phy status update state machine */ +uint32_t lpcPHYStsPoll(void) +{ + static uint16_t sts; + + switch (phyustate) { + default: + case 0: + /* Read BMSR to clear faults */ + Chip_ENET_Start_MII_Read(LAN8_BSR_REG); + physts &= ~PHY_LINK_CHANGED; + physts = physts | PHY_LINK_BUSY; + phyustate = 1; + break; + + case 1: + /* Wait for read status state */ + if (!Chip_ENET_Is_MII_Busy()) { + /* Get PHY status with link state */ + sts = Chip_ENET_Read_MII_Data(); + Chip_ENET_Start_MII_Read(LAN8_PHYSPLCTL_REG); + phyustate = 2; + } + break; + + case 2: + /* Wait for read status state */ + if (!Chip_ENET_Is_MII_Busy()) { + /* Update PHY status */ + physts &= ~PHY_LINK_BUSY; + smsc_update_phy_sts(sts, Chip_ENET_Read_MII_Data()); + phyustate = 0; + } + break; + } + + return physts; +} + +/** + * @} + */ diff --git a/bsp/xplorer4330/libraries/lpc_board/boards_18xx_43xx/boards_18xx43xx.dox b/bsp/xplorer4330/libraries/lpc_board/boards_18xx_43xx/boards_18xx43xx.dox new file mode 100644 index 0000000000..8f54921c63 --- /dev/null +++ b/bsp/xplorer4330/libraries/lpc_board/boards_18xx_43xx/boards_18xx43xx.dox @@ -0,0 +1,62 @@ +/* + * @brief LPCOpen 18xx/43xx board support page + * + * @note + * Copyright(C) NXP Semiconductors, 2012 + * All rights reserved. + * + * @par + * Software that is described herein is for illustrative purposes only + * which provides customers with programming information regarding the + * LPC products. This software is supplied "AS IS" without any warranties of + * any kind, and NXP Semiconductors and its licensor disclaim any and + * all warranties, express or implied, including all implied warranties of + * merchantability, fitness for a particular purpose and non-infringement of + * intellectual property rights. NXP Semiconductors assumes no responsibility + * or liability for the use of the software, conveys no license or rights under any + * patent, copyright, mask work right, or any other intellectual property rights in + * or to any products. NXP Semiconductors reserves the right to make changes + * in the software without notification. NXP Semiconductors also makes no + * representation or warranty that such application will be suitable for the + * specified use without further testing or modification. + * + * @par + * Permission to use, copy, modify, and distribute this software and its + * documentation is hereby granted, under NXP Semiconductors' and its + * licensor's relevant copyrights in the software, without fee, provided that it + * is used in conjunction with NXP Semiconductors microcontrollers. This + * copyright, permission, and disclaimer notice must appear in all copies of + * this code. + */ + +/** @defgroup BOARDS_18XX_43XX BOARD: LPC18XX and LPC43XX boards + * @ingroup Board_Layer + * @{ + */ + +/** + * @} + */ + +/*! + * @page LPCOPEN_BSP_18XX43XX Supported 18xx/43xx platforms + * + * Device Support
+ * All LPC18xx and LPC43xx device variants are supported.

+ * LPC18xx documentation links
+ * LPC43xx documentation links

+ * Board Support
+ * Hitex, Keil, and NGX boards for both 18xx and 43xx variants are supported. + * Click here for LPCOpen build procedures and default jumper configuration for supported boards.

+ * Hitex LPC1857 and LPC4357 evaluation boards
+ * Keil MCB1800 and Keil MCB4300 boards
+ * NGX LPC1830 Xplorer and + * NGX LPC4330 Xplorer boards
+ * + * Toolchain Support
+ * Code Red Xpresso, IAR EWARM, and Keil MDK are all supported. See the build support pages + * for information on specific versions of the toolchains tested with the LPCOpen platform.

+ * IAR EWARM
+ * ARM MDK-ARM
+ * LPCXpresso + */ diff --git a/bsp/xplorer4330/libraries/lpc_board/boards_18xx_43xx/hitex_eva_18504350/board.h b/bsp/xplorer4330/libraries/lpc_board/boards_18xx_43xx/hitex_eva_18504350/board.h new file mode 100644 index 0000000000..960c9d7854 --- /dev/null +++ b/bsp/xplorer4330/libraries/lpc_board/boards_18xx_43xx/hitex_eva_18504350/board.h @@ -0,0 +1,37 @@ +/* + * @brief Hitex EVA 1850/4350 board file + * + * @note + * Copyright(C) NXP Semiconductors, 2012 + * All rights reserved. + * + * @par + * Software that is described herein is for illustrative purposes only + * which provides customers with programming information regarding the + * LPC products. This software is supplied "AS IS" without any warranties of + * any kind, and NXP Semiconductors and its licensor disclaim any and + * all warranties, express or implied, including all implied warranties of + * merchantability, fitness for a particular purpose and non-infringement of + * intellectual property rights. NXP Semiconductors assumes no responsibility + * or liability for the use of the software, conveys no license or rights under any + * patent, copyright, mask work right, or any other intellectual property rights in + * or to any products. NXP Semiconductors reserves the right to make changes + * in the software without notification. NXP Semiconductors also makes no + * representation or warranty that such application will be suitable for the + * specified use without further testing or modification. + * + * @par + * Permission to use, copy, modify, and distribute this software and its + * documentation is hereby granted, under NXP Semiconductors' and its + * licensor's relevant copyrights in the software, without fee, provided that it + * is used in conjunction with NXP Semiconductors microcontrollers. This + * copyright, permission, and disclaimer notice must appear in all copies of + * this code. + */ + +#ifndef __BOARD_H_ +#define __BOARD_H_ + +#include "board_hitex_eva_18504350.h" + +#endif /* __BOARD_H_ */ diff --git a/bsp/xplorer4330/libraries/lpc_board/boards_18xx_43xx/hitex_eva_18504350/board_hitex_eva_18504350.c b/bsp/xplorer4330/libraries/lpc_board/boards_18xx_43xx/hitex_eva_18504350/board_hitex_eva_18504350.c new file mode 100644 index 0000000000..155116b105 --- /dev/null +++ b/bsp/xplorer4330/libraries/lpc_board/boards_18xx_43xx/hitex_eva_18504350/board_hitex_eva_18504350.c @@ -0,0 +1,898 @@ +/* + * @brief Hitex EVA 1850/4350 board file + * + * @note + * Copyright(C) NXP Semiconductors, 2012 + * All rights reserved. + * + * @par + * Software that is described herein is for illustrative purposes only + * which provides customers with programming information regarding the + * LPC products. This software is supplied "AS IS" without any warranties of + * any kind, and NXP Semiconductors and its licensor disclaim any and + * all warranties, express or implied, including all implied warranties of + * merchantability, fitness for a particular purpose and non-infringement of + * intellectual property rights. NXP Semiconductors assumes no responsibility + * or liability for the use of the software, conveys no license or rights under any + * patent, copyright, mask work right, or any other intellectual property rights in + * or to any products. NXP Semiconductors reserves the right to make changes + * in the software without notification. NXP Semiconductors also makes no + * representation or warranty that such application will be suitable for the + * specified use without further testing or modification. + * + * @par + * Permission to use, copy, modify, and distribute this software and its + * documentation is hereby granted, under NXP Semiconductors' and its + * licensor's relevant copyrights in the software, without fee, provided that it + * is used in conjunction with NXP Semiconductors microcontrollers. This + * copyright, permission, and disclaimer notice must appear in all copies of + * this code. + */ + +#include "board.h" +#include "string.h" + +/* Include other sources files specific to this board */ +#include "lpc_phy_dp83848.c" +#include "retarget.c" + +/** @ingroup BOARD_HITEX_EVA_18504350 + * @{ + */ + +/***************************************************************************** + * Private types/enumerations/variables + ****************************************************************************/ + +/* Port and bit mapping for LEDs on GPIOs */ +static const uint8_t ledports[] = {4, 7, 7, 7}; +static const uint8_t ledbits[] = {1, 5, 6, 8}; + +/* TSC2046 control byte definitions */ +#define TSC_START (0x01 << 7) +#define TSC_CHANNEL_X (0x05 << 4) /* differential */ +#define TSC_CHANNEL_Y (0x01 << 4) /* differential */ +#define TSC_CHANNEL_Z1 (0x03 << 4) /* differential */ +#define TSC_CHANNEL_Z2 (0x04 << 4) /* differential */ +#define TSC_8BIT (0x01 << 3) +#define TSC_12BIT (0x00 << 3) +#define TSC_PD 0x00 +#define TSC_ADC_ON 0x01 +#define TSC_REF_ON 0x02 +#if (TSC2046_CONVERSION_BITS == 12) +#define TSC_CONVERSION_MODE TSC_12BIT +#else +#define TSC_CONVERSION_MODE TSC_8BIT +#endif + +#define TSC_SER_MODE (0x01 << 2) /* Single-Ended Reference Mode */ +#define TSC_DFR_MODE (0x00 << 2) /* Differential Reference Mode */ + +#define X_MEASURE (TSC_START | TSC_CHANNEL_X | TSC_CONVERSION_MODE | TSC_DFR_MODE | TSC_ADC_ON) +#define Y_MEASURE (TSC_START | TSC_CHANNEL_Y | TSC_CONVERSION_MODE | TSC_DFR_MODE | TSC_ADC_ON) +#define Z1_MEASURE (TSC_START | TSC_CHANNEL_Z1 | TSC_CONVERSION_MODE | TSC_DFR_MODE | TSC_ADC_ON) +#define Z2_MEASURE (TSC_START | TSC_CHANNEL_Z2 | TSC_CONVERSION_MODE | TSC_DFR_MODE | TSC_ADC_ON) +#define PWRDOWN (TSC_START | TSC_CHANNEL_Y | TSC_CONVERSION_MODE | TSC_DFR_MODE | TSC_PD) + +typedef struct { + int16_t ad_left; /* left margin */ + int16_t ad_right; /* right margin */ + int16_t ad_top; /* top margin */ + int16_t ad_bottom; /* bottom margin */ + int16_t lcd_width; /* lcd horizontal size */ + int16_t lcd_height; /* lcd vertical size */ + uint8_t swap_xy; /* 1: swap x-y coords */ +} TSC2046_Init_Type; + +#define DC_CMD (Chip_GPIO_WritePortBit(0x07, 8, false)) +#define DC_DATA (Chip_GPIO_WritePortBit(0x07, 8, true)) + +#define TSC2046_CONVERSION_BITS 12 + +#if (TSC2046_CONVERSION_BITS == 12) +#define TSC2046_COORD_MAX (0xFFF) +#define TSC2046_DELTA_VARIANCE (0x50) +#else +#define TSC2046_COORD_MAX (0xFF) +#define TSC2046_DELTA_VARIANCE (0x03) +#endif +#define COORD_GET_NUM (10) + +/** Local variables */ +static TSC2046_Init_Type TSC_Config = { + 3686, 205, 3842, 267, 240, 320, 1 +}; + +/** + * LCD configuration data + */ +const LCD_Config_Type EA320x240 = { + 28, /* Horizontal back porch in clocks */ + 10, /* Horizontal front porch in clocks */ + 2, /* HSYNC pulse width in clocks */ + 240, /* Pixels per line */ + 2, /* Vertical back porch in clocks */ + 1, /* Vertical front porch in clocks */ + 2, /* VSYNC pulse width in clocks */ + 320, /* Lines per panel */ + 0, /* Invert output enable, 1 = invert */ + 1, /* Invert panel clock, 1 = invert */ + 1, /* Invert HSYNC, 1 = invert */ + 1, /* Invert VSYNC, 1 = invert */ + 1, /* AC bias frequency in clocks (not used) */ + 6, /* Maximum bits per pixel the display supports */ + LCD_TFT, /* LCD panel type */ + LCD_COLOR_FORMAT_BGR, /* BGR or RGB */ + 0 /* Dual panel, 1 = dual panel display */ +}; + +/* UDA1380 Register Address */ +typedef enum { + UDA_EVALM_CLK = 0x00, + UDA_BUS_CTRL, + UDA_POWER_CTRL, + UDA_ANALOG_CTRL, + UDA_HPAMP_CTRL, + UDA_MASTER_VOL_CTRL = 0x10, + UDA_MIXER_VOL_CTRL, + UDA_MODE_CTRL, + UDA_MUTE_CTRL, + UDA_MIXER_FILTER_CTRL, + UDA_DEC_VOL_CTRL = 0x20, + UDA_PGA_CTRL, + UDA_ADC_CTRL, + UDA_AGC_CTRL, + UDA_TOTAL_REG +} UDA1380_REG; + +#define UDA1380_REG_EVALCLK_DEFAULT_VALUE (0xF << 8 | 0x3 << 4 | 1 << 1) +#define UDA1380_REG_I2S_DEFAULT_VALUE 0x0000 + +#define UDA1380_REG_PWRCTRL_DEFAULT_VALUE (1 << 15 | 1 << 13 | 1 << 10 | 1 << 8 | 1 << 6 | 1 << 4 | 0x0F) +#define UDA1380_REG_ANAMIX_DEFAULT_VALUE 0x0000 +#define UDA1380_REG_HEADAMP_DEFAULT_VALUE ( 1 << 9 | 2) + +#define UDA1380_REG_MSTRVOL_DEFAULT_VALUE 0x0000 +#define UDA1380_REG_MIXVOL_DEFAULT_VALUE 0x0000 +#define UDA1380_REG_MODEBBT_DEFAULT_VALUE 0x0000 +#define UDA1380_REG_MSTRMUTE_DEFAULT_VALUE (2 << 8 | 2) +#define UDA1380_REG_MIXSDO_DEFAULT_VALUE 0x0000 + +#define UDA1380_REG_DECVOL_DEFAULT_VALUE 0xE4E4 /* Decrease Volume -28dB */ +#define UDA1380_REG_PGA_DEFAULT_VALUE 0x0000 +#define UDA1380_REG_ADC_DEFAULT_VALUE 0x0001 /* Apply 0bB VGA Gain, enable DC Filter */ +#define UDA1380_REG_AGC_DEFAULT_VALUE 0x0000 + +#define UDA1380_REG_L3_DEFAULT_VALUE 0x0000 + +/* System Register Data Set */ +static uint16_t UDA_sys_regs_dat[] = { + UDA1380_REG_EVALCLK_DEFAULT_VALUE, + UDA1380_REG_I2S_DEFAULT_VALUE, + UDA1380_REG_PWRCTRL_DEFAULT_VALUE, + UDA1380_REG_ANAMIX_DEFAULT_VALUE, + UDA1380_REG_HEADAMP_DEFAULT_VALUE +}; + +/* System Register Data Set */ +static uint16_t UDA_interfil_regs_dat[] = { + UDA1380_REG_MSTRVOL_DEFAULT_VALUE, + UDA1380_REG_MIXVOL_DEFAULT_VALUE, + UDA1380_REG_MODEBBT_DEFAULT_VALUE, + UDA1380_REG_MSTRMUTE_DEFAULT_VALUE, + UDA1380_REG_MIXSDO_DEFAULT_VALUE +}; +/* decimator Register Data Set */ +static uint16_t UDA_decimator_regs_dat[] = { + UDA1380_REG_DECVOL_DEFAULT_VALUE, + UDA1380_REG_PGA_DEFAULT_VALUE, + UDA1380_REG_ADC_DEFAULT_VALUE, + UDA1380_REG_AGC_DEFAULT_VALUE +}; + +/***************************************************************************** + * Public types/enumerations/variables + ****************************************************************************/ + +/***************************************************************************** + * Private functions + ****************************************************************************/ + +/* Very simple (inaccurate) delay function */ +static void DelayMs(uint32_t ms) +{ + uint32_t i; + for (i = 0; i < 100 * ms; i++) {} +} + +/* Additional (SPI) pin configuration for LCD interface signals */ +static void lcdPinConfig(void) +{ + /* PC.11 connected to GPIO = SSEL_MUX_A, PC.12 connected to GPIO = SSEL_MUX_B */ + Chip_SCU_PinMux(0xC, 11, MD_PLN, FUNC4); + Chip_SCU_PinMux(0xC, 12, MD_PLN, FUNC4); + Chip_GPIO_WriteDirBit(0x6, 10, true); + Chip_GPIO_WriteDirBit(0x6, 11, true); + + /* Configure SSP0 pins */ + /* PF.0 connected to SCL/SCLK */ + Chip_SCU_PinMux(0xF, 0, MD_PLN_FAST, FUNC0); + /* PF.1 connected to nCS */ + Chip_SCU_PinMux(0xF, 1, MD_PLN_FAST, FUNC2); + /* PF.2 connected to SO */ + Chip_SCU_PinMux(0xF, 2, MD_PLN_FAST, FUNC2); + /* PF.3 connected to nSI */ + Chip_SCU_PinMux(0xF, 3, MD_PLN_FAST, FUNC2); + + /* DC PIN */ + Chip_SCU_PinMux(0x0E, 8, MD_PUP, FUNC4); + Chip_GPIO_WriteDirBit(7, 8, true); +} + +/* Write to a LCD register using SPI */ +static void writeToReg(uint16_t addr, uint16_t data) +{ + uint8_t buf[2]; + + Chip_GPIO_WritePortBit(0x06, 10, true); + Chip_GPIO_WritePortBit(0x06, 11, false); + + DC_CMD; + + buf[0] = 0; + buf[1] = (addr & 0xff); + + Chip_SSP_WriteFrames_Blocking(LPC_SSP0, buf, 2); + + DC_DATA; + buf[0] = (data >> 8); + buf[1] = (data & 0xff); + Chip_SSP_WriteFrames_Blocking(LPC_SSP0, buf, 2); + + DC_CMD; + + buf[0] = (0); + buf[1] = (0x22); + Chip_SSP_WriteFrames_Blocking(LPC_SSP0, buf, 2); +} + +/* Initialize SSD1289 LCD Controller */ +static void ssd1289_init(void) +{ + writeToReg(0x00, 0x0001); + DelayMs(15); + writeToReg(0x03, 0x6E3E); // 0xAEAC + writeToReg(0x0C, 0x0007); + writeToReg(0x0D, 0x000E); // 0x000F + writeToReg(0x0E, 0x2C00); // 0x2900 + writeToReg(0x1E, 0x00AE); // 0x00B3 + DelayMs(15); + writeToReg(0x07, 0x0021); + DelayMs(50); + writeToReg(0x07, 0x0023); + DelayMs(50); + writeToReg(0x07, 0x0033); + DelayMs(50); + + writeToReg(0x01, 0x2B3F); + writeToReg(0x02, 0x0600); + writeToReg(0x10, 0x0000); + DelayMs(15); + writeToReg(0x11, 0xC5B0); // 0x65b0 + DelayMs(20); + writeToReg(0x05, 0x0000); + writeToReg(0x06, 0x0000); + writeToReg(0x16, 0xEF1C); + writeToReg(0x17, 0x0003); + writeToReg(0x07, 0x0233); + writeToReg(0x0B, 0x5312); + writeToReg(0x0F, 0x0000); + writeToReg(0x25, 0xE000); + DelayMs(20); + writeToReg(0x41, 0x0000); + writeToReg(0x42, 0x0000); + writeToReg(0x48, 0x0000); + writeToReg(0x49, 0x013F); + writeToReg(0x44, 0xEF00); + writeToReg(0x45, 0x0000); + writeToReg(0x46, 0x013F); + writeToReg(0x4A, 0x0000); + writeToReg(0x4B, 0x0000); + DelayMs(20); + writeToReg(0x30, 0x0707); + writeToReg(0x31, 0x0704); + writeToReg(0x32, 0x0005); // 0x0204 + writeToReg(0x33, 0x0402); // 0x0201 + writeToReg(0x34, 0x0203); + writeToReg(0x35, 0x0204); + writeToReg(0x36, 0x0204); + writeToReg(0x37, 0x0401); // 0x0502 + writeToReg(0x3A, 0x0302); + writeToReg(0x3B, 0x0500); + DelayMs(20); + writeToReg(0x22, 0x0000); +} + +/* Send/Receive data to/from TSC2046. */ +static void TSC2046_ReadWrite(uint8_t command, uint16_t *data) +{ + uint32_t tmp; + uint8_t rx_data[2], tx_data[1] = {0x00}; + + tx_data[0] = command; + Chip_GPIO_WritePortBit(6, 10, false); + Chip_GPIO_WritePortBit(6, 11, true); + + Chip_GPIO_WritePortBit(7, 16, false); + + for (tmp = 0x100; tmp; tmp--) {} + + Chip_SSP_WriteFrames_Blocking(LPC_SSP0, tx_data, 1); + Chip_SSP_ReadFrames_Blocking(LPC_SSP0, rx_data, 2); + + for (tmp = 0x100; tmp; tmp--) {} + +#if (TSC2046_CONVERSION_BITS == 8) + *data = (((rx_data[0] << 8) | (rx_data[1])) >> 7) & 0xFF; +#else + *data = (((rx_data[0] << 8) | rx_data[1]) >> 3) & 0xFFF; +#endif + Chip_GPIO_WritePortBit(7, 16, true); +} + +/* Evaluate the coordinates received from TSC. */ +static Status EvalCoord(uint8_t command, uint16_t *coord) +{ + uint32_t i; + uint16_t Tmp = 0, previousTmp; + int16_t diff = 0; + *coord = 0; + for (i = 0; i < COORD_GET_NUM; i++) { + previousTmp = Tmp; + TSC2046_ReadWrite(command, &Tmp); + if (Tmp > TSC2046_COORD_MAX) { + return ERROR; + } + if (i > 0) { + diff = Tmp - previousTmp; + } + if (diff < 0) { + diff = 0 - diff; + } + if (diff > TSC2046_DELTA_VARIANCE) { + return ERROR; + } + *coord += Tmp; + } + *coord /= COORD_GET_NUM; + return SUCCESS; +} + +/* Convert the coord received from TSC to a value on truly LCD */ +static int16_t TSCCalibrate(int16_t Coord, int16_t MinVal, int16_t MaxVal, int16_t TrueSize) +{ + int16_t tmp; + int16_t ret; + uint8_t convert = 0; + + /* Swap value? */ + if (MinVal > MaxVal) { + tmp = MaxVal; + MaxVal = MinVal; + MinVal = tmp; + convert = 1; + } + + ret = (Coord - MinVal) * TrueSize / (MaxVal - MinVal); + if (convert) { + ret = TrueSize - ret; + } + + return ret; +} + +static void delay(uint32_t i) { + while (i--) {} +} + +/* Write value to a UDA1380 register */ +static void UDA_Reg_write(UDA1380_REG reg, unsigned short value, I2C_M_SETUP_Type *I2C_Config) { + + I2C_Config->tx_data[0] = reg; + I2C_Config->tx_data[1] = value >> 8; + I2C_Config->tx_data[2] = value & 0xFF; + Chip_I2C_MasterTransmitData(LPC_I2C0, I2C_Config, I2C_TRANSFER_POLLING); + delay(10000); +} + +/* Read value from a UDA1380 register */ +static uint16_t UDA_Reg_read(UDA1380_REG reg) { + uint8_t rx_data[2]; + Chip_I2C_MasterReadReg(LPC_I2C0, I2CDEV_UDA1380_ADDR, reg, rx_data, 2); + return rx_data[0] << 8 | rx_data[1]; +} + +/* Initialize UDA1380 CODEC */ +static Status UDA1380_init(I2C_M_SETUP_Type *I2C_Config, Board_Audio_Input_Sel_Type audio_in_sel) +{ + uint16_t temp; + uint8_t i; + /* Reset UDA1380 on board Hitex A4*/ + /* PE_9: UDA_RST on Hitex A4 */ + Chip_SCU_PinMux(0x0E, 9, MD_PUP, FUNC4); + Chip_GPIO_WriteDirBit(7, 9, true); + Chip_GPIO_WritePortBit(7, 9, true); + /* delay 1us */ + delay(100000); + Chip_GPIO_WritePortBit(7, 9, false); + delay(100000); + for (i = 0; i < 5; i++) { + UDA_Reg_write((UDA1380_REG) (UDA_EVALM_CLK + i), UDA_sys_regs_dat[i], I2C_Config); + temp = UDA_Reg_read((UDA1380_REG) (UDA_EVALM_CLK + i)); + if (temp != UDA_sys_regs_dat[i]) { + return ERROR; + } + } + + /* interfilter regs init */ + for (i = 0; i < 5; i++) { + UDA_Reg_write((UDA1380_REG) (UDA_MASTER_VOL_CTRL + i), UDA_interfil_regs_dat[i], I2C_Config); + temp = UDA_Reg_read((UDA1380_REG) (UDA_MASTER_VOL_CTRL + i)); + if (temp != UDA_interfil_regs_dat[i]) { + return ERROR; + } + } + /* decimator regs init */ + for (i = 0; i < 4; i++) { + UDA_Reg_write((UDA1380_REG) (UDA_DEC_VOL_CTRL + i), UDA_decimator_regs_dat[i], I2C_Config); + temp = UDA_Reg_read((UDA1380_REG) (UDA_DEC_VOL_CTRL + i)); + if (temp != UDA_decimator_regs_dat[i]) { + return ERROR; + } + } + + if (audio_in_sel == MCB_18XX_AUDIO_MIC_SELECT) { + /* Disable Power On for ADCR, PGAR, PGAL to get mic sound more clearly */ + UDA_Reg_write((UDA1380_REG) (UDA_POWER_CTRL), UDA1380_REG_PWRCTRL_DEFAULT_VALUE & (~(0x0B)), I2C_Config); + temp = UDA_Reg_read((UDA1380_REG) (UDA_ADC_CTRL)); + if (temp != (UDA1380_REG_ADC_DEFAULT_VALUE | MCB_18XX_AUDIO_MIC_SELECT)) { + return ERROR; + } + UDA_Reg_write((UDA1380_REG) (UDA_ADC_CTRL), + UDA1380_REG_ADC_DEFAULT_VALUE | MCB_18XX_AUDIO_MIC_SELECT, + I2C_Config); + temp = UDA_Reg_read((UDA1380_REG) (UDA_ADC_CTRL)); + if (temp != (UDA1380_REG_ADC_DEFAULT_VALUE | MCB_18XX_AUDIO_MIC_SELECT)) { + return ERROR; + } + } + return SUCCESS; + +} + +/***************************************************************************** + * Public functions + ****************************************************************************/ + +/* Initialize pin muxing for a UART */ +void Board_UART_Init(LPC_USART_Type *UARTx) +{ + if (UARTx == LPC_USART0) { + Chip_SCU_PinMux(0xF, 10, MD_PDN, FUNC1); /* PF.10 : UART0_TXD */ + Chip_SCU_PinMux(0xF, 11, MD_PLN | MD_EZI | MD_ZI, FUNC1); /* PF.11 : UART0_RXD */ + } + else if (UARTx == LPC_UART1) { + Chip_SCU_PinMux(0xC, 13, MD_PDN, FUNC2); /* PC.13 : UART1_TXD - pin 1 of SV14 */ + Chip_SCU_PinMux(0xC, 14, MD_PLN | MD_EZI | MD_ZI, FUNC2); /* PC.14 : UART1_RX - pin 2 of SV14 */ + } + else if (UARTx == LPC_USART2) { + /* P1.15 : UART2_TXD - pin 11 of SV6, P1.16 : UART2_RXD - pin 3 of SV6 */ + Chip_SCU_PinMux(0x1, 15, MD_PDN, FUNC1); + Chip_SCU_PinMux(0x1, 16, MD_PLN | MD_EZI | MD_ZI, FUNC1); + } + else if (UARTx == LPC_USART3) { + /* P9.3 : UART3_TXD - pin 15 of SV6, P9.4 : UART3_RXD - pin 7 of SV3 */ + Chip_SCU_PinMux(0x9, 3, MD_PDN, FUNC7); + Chip_SCU_PinMux(0x9, 4, MD_PLN | MD_EZI | MD_ZI, FUNC7); + } +} + +/* Initialize debug output via UART for board */ +void Board_Debug_Init(void) +{ +#if defined(DEBUG_UART) + Board_UART_Init(DEBUG_UART); + + Chip_UART_Init(DEBUG_UART); + Chip_UART_SetBaud(DEBUG_UART, 115200); + Chip_UART_ConfigData(DEBUG_UART, UART_DATABIT_8, UART_PARITY_NONE, UART_STOPBIT_1); + + /* Enable UART Transmit */ + Chip_UART_TxCmd(DEBUG_UART, ENABLE); +#endif +} + +/* Sends a character on the UART */ +void Board_UARTPutChar(char ch) +{ +#if defined(DEBUG_UART) + while (Chip_UART_SendByte(DEBUG_UART, (uint8_t) ch) == ERROR) {} +#endif +} + +/* Gets a character from the UART, returns EOF if no character is ready */ +int Board_UARTGetChar(void) +{ +#if defined(DEBUG_UART) + uint8_t data; + + if (Chip_UART_ReceiveByte(DEBUG_UART, &data) == SUCCESS) { + return (int) data; + } +#endif + return EOF; +} + +/* Outputs a string on the debug UART */ +void Board_UARTPutSTR(char *str) +{ +#if defined(DEBUG_UART) + while (*str != '\0') { + Board_UARTPutChar(*str++); + } +#endif +} + +/* Initializes board LED(s) */ +void Board_LED_Init() +{ + int i; + + /* Set ports as outputs with initial states off */ + for (i = 0; i < (sizeof(ledports) / sizeof(ledports[0])); i++) { + Chip_GPIO_WriteDirBit(ledports[i], ledbits[i], true); + Chip_GPIO_WritePortBit(ledports[i], ledbits[i], true); + } + Chip_GPIO_WritePortBit(ledports[0], ledbits[0], false); +} + +/* Sets the state of a board LED to on or off */ +void Board_LED_Set(uint8_t LEDNumber, bool On) +{ + /* Must connect JP3 to see LED0 and JP4 to see LED1 */ + if (LEDNumber == 0) { + On = !On; + } + + if (LEDNumber < 4) { + Chip_GPIO_WritePortBit(ledports[LEDNumber], ledbits[LEDNumber], !On); + } +} + +/* Returns the current state of a board LED */ +bool Board_LED_Test(uint8_t LEDNumber) +{ + bool On = false; + + if (LEDNumber < 4) { + On = (bool) !Chip_GPIO_ReadPortBit(ledports[LEDNumber], ledbits[LEDNumber]); + + if (LEDNumber == 0) { + On = ~On; + } + } + + return On; +} + +/* Initialize button(s) interface on board */ +void Board_Buttons_Init(void) // FIXME not functional ATM +{ + Chip_SCU_PinMux(0xD, 7, MD_PUP | MD_EZI, FUNC4); // GPIO6[21] + Chip_GPIO_WriteDirBit(BUTTONS_BUTTON1_GPIO_PORT_NUM, BUTTONS_BUTTON1_GPIO_BIT_NUM, false); // input +} + +/* Returns button(s) state on board */ +uint32_t Buttons_GetStatus(void) +{ + uint8_t ret = NO_BUTTON_PRESSED; + if (Chip_GPIO_ReadPortBit(BUTTONS_BUTTON1_GPIO_PORT_NUM, BUTTONS_BUTTON1_GPIO_BIT_NUM) == 0) { + ret |= BUTTONS_BUTTON1; + } + return ret; +} + +/* Initialize joystick interface on board */ +void Board_Joystick_Init(void) +{} + +/* Returns joystick states on board */ +uint8_t Joystick_GetStatus(void) +{ + return NO_BUTTON_PRESSED; +} + +/** + * System Clock Frequency (Core Clock) + */ +uint32_t SystemCoreClock; + +/* Update system core clock rate, should be called if the system has + a clock rate change */ +void SystemCoreClockUpdate(void) +{ + /* CPU core speed */ + SystemCoreClock = Chip_Clock_GetRate(CLK_MX_MXCORE); +} + +/* Returns the MAC address assigned to this board */ +void Board_ENET_GetMacADDR(uint8_t *mcaddr) +{ + const uint8_t boardmac[] = {0x00, 0x60, 0x37, 0x12, 0x34, 0x56}; + + memcpy(mcaddr, boardmac, 6); +} + +/* Set up and initialize all required blocks and functions related to the + board hardware */ +void Board_Init(void) +{ + /* Sets up DEBUG UART */ + DEBUGINIT(); + + /* Updates SystemCoreClock global var with current clock speed */ + SystemCoreClockUpdate(); + + /* Initializes GPIO */ + Chip_GPIO_Init(); + + /* Setup GPIOs for USB demos */ +#if 0 /* FIXME: the following call removed on the Hitex board as it interferes with muxed MII state */ + // Chip_SCU_PinMux(0x9, 5, (MD_PUP | MD_EZI), FUNC2); // P9_5 USB1_VBUS_EN, USB1 VBus function +#endif + Chip_SCU_PinMux(0x2, 5, (MD_PLN | MD_EZI | MD_ZI), FUNC2); // P2_5 USB1_VBUS, MUST CONFIGURE THIS SIGNAL FOR USB1 NORMAL OPERATION + Chip_SCU_PinMux(0x6, 3, (MD_PUP | MD_EZI), FUNC1); // P6_3 USB0_PWR_EN, USB0 VBus function +} + +/* Sets up board specific ADC interface */ +void Board_ADC_Init(void) +{ + /* Analog function ADC1_2 selected on pin PF_9 */ + Chip_SCU_ADC_Channel_Config(1, 2); +} + +/* Sets up board specific I2C interface */ +void Board_I2C_Init(LPC_I2C_Type *I2Cx) +{ + if (I2Cx == LPC_I2C1) { + /* Configure pin function for I2C1 on PE.13 (I2C1_SDA) and PE.15 (I2C1_SCL) */ + Chip_SCU_PinMux(0xE, 13, MD_ZI | MD_EZI, FUNC2); + Chip_SCU_PinMux(0xE, 15, MD_ZI | MD_EZI, FUNC2); + } +} + +/* Initialize the LCD interface */ +void Board_LCD_Init(void) +{ + SSP_ConfigFormat ssp_format1; + /* Attach main PLL clock to divider A with a divider of 2 */ + Chip_Clock_SetDivider(CLK_IDIV_A, CLKIN_MAINPLL, 2); + + /* Route divider A output to LCD base clock and enable base clock */ + Chip_Clock_SetBaseClock(CLK_BASE_LCD, CLKIN_IDIVA, true, false); + + /* Reset LCD and wait for reset to complete */ + Chip_RGU_TriggerReset(RGU_LCD_RST); + while (Chip_RGU_InReset(RGU_LCD_RST)) {} + + lcdPinConfig(); + Chip_Clock_Enable(CLK_MX_SSP0); + Chip_SSP_Init(LPC_SSP0); + Chip_SSP_Set_Master(LPC_SSP0, true); + Chip_SSP_Set_BitRate(LPC_SSP0, 1000000); + + ssp_format1.frameFormat = SSP_FRAMEFORMAT_SPI; + ssp_format1.bits = SSP_BITS_8; + ssp_format1.clockFormat = SSP_CLOCK_MODE0; + + Chip_SSP_Set_Format(LPC_SSP0, &ssp_format1); + Chip_SSP_Cmd(LPC_SSP0, ENABLE); + + DelayMs(200); + + /* initialize LCD controller */ + ssd1289_init(); + + Chip_SSP_Cmd(LPC_SSP0, DISABLE); + Chip_SSP_DeInit(LPC_SSP0); +} + +/* Initialize TSC2046 touchscreen controller */ +void Init_Touch_Controller(void) +{ + uint16_t dummy_data; + SSP_ConfigFormat ssp_format1; + + /* Configure SSP0 pins*/ + lcdPinConfig(); + Chip_SCU_PinMux(0xF, 1, MD_PUP, FUNC4); + + Chip_GPIO_WriteDirBit(7, 16, true); + + Chip_GPIO_WritePortBit(6, 10, false); + Chip_GPIO_WritePortBit(6, 11, true); + + Chip_SSP_Init(LPC_SSP0); + + Chip_SSP_Set_Master(LPC_SSP0, true); + Chip_SSP_Set_BitRate(LPC_SSP0, 200000); + + ssp_format1.frameFormat = SSP_FRAMEFORMAT_SPI; + ssp_format1.bits = SSP_BITS_8; + ssp_format1.clockFormat = SSP_CLOCK_MODE0; + + Chip_SSP_Set_Format(LPC_SSP0, &ssp_format1); + Chip_SSP_Cmd(LPC_SSP0, ENABLE); + + /* Enable Touch Screen Controller */ + TSC2046_ReadWrite(PWRDOWN, &dummy_data); +} + +/* Get Touch coordinates */ +bool GetTouchPos(int16_t *pX, int16_t *pY) +{ + uint16_t tmp; + uint16_t x, y, z1, z2, z = 0; + Status Sts = SUCCESS; + + TSC2046_ReadWrite(X_MEASURE, &x); + TSC2046_ReadWrite(Y_MEASURE, &y); + TSC2046_ReadWrite(Z1_MEASURE, &z1); + TSC2046_ReadWrite(Z2_MEASURE, &z2); + + if (z1 != 0) { + z = x * ((z2 / z1) - 1); + } + if ((z <= 0) || (z > 35000)) { + return false; + } + /* Get X-Coordinate */ + Sts = EvalCoord(X_MEASURE, &x); + + if (Sts == ERROR) { + return false; + } + /* Get Y-Coordinate */ + Sts = EvalCoord(Y_MEASURE, &y); + if (Sts == ERROR) { + return false; + } + /* Get Z1-Value */ + Sts = EvalCoord(Z1_MEASURE, &z1); + if (Sts == ERROR) { + return false; + } + /* Get Z2-Value */ + Sts = EvalCoord(Z2_MEASURE, &z2); + if (Sts == ERROR) { + return false; + } + + z = x * ((z2 / z1) - 1); + if ((z <= 0) || (z > 35000)) { + return false; + } + else { + /* Swap, adjust to truly size of LCD */ + if (TSC_Config.swap_xy) { + *pY = TSCCalibrate(x, TSC_Config.ad_top, TSC_Config.ad_bottom, TSC_Config.lcd_height); + *pX = TSCCalibrate(y, TSC_Config.ad_left, TSC_Config.ad_right, TSC_Config.lcd_width); + } + else { + *pX = TSCCalibrate(x, TSC_Config.ad_top, TSC_Config.ad_bottom, TSC_Config.lcd_width); + *pY = TSCCalibrate(y, TSC_Config.ad_left, TSC_Config.ad_right, TSC_Config.lcd_height); + } + } + TSC2046_ReadWrite(PWRDOWN, &tmp); + + return true; +} + +/* Turn on Board LCD Backlight */ +void Board_LCD_Set_Backlight(uint8_t Intensity) +{ + bool OnOff = (bool) (Intensity != 0); + + Chip_GPIO_WritePortBit(3, 8, OnOff); +} + +/* Initialize pin muxing for SDMMC interface */ +void Board_SDMMC_Init(void) +{ + Chip_SCU_PinMux(0xc, 9, MD_PLN, FUNC7); /* Pc.9 SDIO power */ + Chip_SCU_PinMux(0xc, 2, MD_PLN, FUNC7); /* Pc.2 SDIO LED */ + Chip_SCU_PinMux(0xf, 10, MD_PLN | MD_EZI, FUNC6); /* Pf.10 SDIO WP */ + Chip_SCU_PinMux(0xc, 8, MD_PLN | MD_EZI, FUNC7); /* Pc.8 SDIO CD */ + Chip_SCU_PinMux(0xc, 6, MD_PLN_FAST, FUNC7); /* Pc.6 SDIO D2 */ + Chip_SCU_PinMux(0xc, 5, MD_PLN_FAST, FUNC7); /* Pc.5 SDIO D1 */ + Chip_SCU_PinMux(0xc, 4, MD_PLN_FAST, FUNC7); /* Pc.4 SDIO D0 */ + Chip_SCU_PinMux(0xc, 0, MD_PLN | MD_EHS, FUNC7); /* Pc.0 SDIO clock */ + Chip_SCU_PinMux(0xc, 10, MD_PLN_FAST, FUNC7); /* Pc.10 SDIO command */ + Chip_SCU_PinMux(0xc, 7, MD_PLN_FAST, FUNC7); /* Pc.7 SDIO D3 */ +} + +/* Initialize pin muxing for SSP interface */ +void Board_SSP_Init(LPC_SSP_Type *SSPx) +{ + if (SSPx == LPC_SSP0) { + /* Set up clock and muxing for SSP0 interface */ + // #if !defined(HITEX_LCD_TERM) + /* PC.11 connected to GPIO = SSEL_MUX_A, PC.12 connected to GPIO = SSEL_MUX_B */ + Chip_SCU_PinMux(0xC, 11, MD_PLN, FUNC4); + Chip_SCU_PinMux(0xC, 12, MD_PLN, FUNC4); + Chip_GPIO_WriteDirBit(0x6, 10, true); + Chip_GPIO_WriteDirBit(0x6, 11, true); + // #endif + /* PF.0 connected to SCL/SCLK func2=SSP0 SCK0 */ + Chip_SCU_PinMux(0xF, 0, MD_PLN_FAST, FUNC0); + /* PF.1 connected to nCS func2=SSP0 SSEL0 */ + Chip_SCU_PinMux(0xF, 1, MD_PLN_FAST, FUNC2); + /* PF.2 connected to SO func2=SSP0 MISO0 */ + Chip_SCU_PinMux(0xF, 2, MD_PLN | MD_EZI | MD_ZI, FUNC2); + /* PF.3 connected to nSI func2=SSP0 MOSI0 */ + Chip_SCU_PinMux(0xF, 3, MD_PLN | MD_EZI | MD_ZI, FUNC2); + + Chip_Clock_Enable(CLK_MX_SSP0); + } + else if (SSPx == LPC_SSP1) { + /* Set up clock and muxing for SSP1 interface */ + /* P1.19 connected to SCL/SCLK func1=SSP1 SCK1 */ + Chip_SCU_PinMux(0x1, 19, MD_PLN_FAST, FUNC1); + /* P1.20 connected to nCS func1=SSP1 SSEL1 */ + Chip_SCU_PinMux(0x1, 20, MD_PLN_FAST, FUNC1); + /* P0.0 connected to SO func1=SSP1 MISO1 */ + Chip_SCU_PinMux(0x0, 0, MD_PLN | MD_EZI | MD_ZI, FUNC1); + /* P0.1 connected to nSI func2=SSP1 MOSI1 */ + Chip_SCU_PinMux(0x0, 1, MD_PLN | MD_EZI | MD_ZI, FUNC1); + + Chip_Clock_Enable(CLK_MX_SSP1); + } +} + +/* Initialize I2S interface for the board and UDA1380 */ +void Board_Audio_Init(LPC_I2S_Type *I2Sx, Board_Audio_Input_Sel_Type audio_in_sel) +{ + uint8_t uda1380_tx_data_buf[3]; + Chip_I2S_Audio_Format_Type I2S_Config; + I2C_M_SETUP_Type I2C_Config; + I2C_Config.sl_addr7bit = I2CDEV_UDA1380_ADDR; + I2C_Config.retransmissions_max = 5; + I2C_Config.tx_length = 3; + I2C_Config.tx_data = uda1380_tx_data_buf; + I2C_Config.rx_length = 0; + I2C_Config.rx_data = NULL; + + /* Initialize I2C to the UDA1380 CODEC */ + Chip_I2C_Init(LPC_I2C0); + Chip_I2C_SetClockRate(LPC_I2C0, 100000); + + I2S_Config.SampleRate = 48000; + I2S_Config.ChannelNumber = 2; // 1 is mono, 2 is stereo + I2S_Config.WordWidth = 16; // 8, 16 or 32 bits + Chip_I2S_Init(LPC_I2S0); + Chip_I2S_Config(LPC_I2S0, I2S_TX_MODE, &I2S_Config); + /* Enable Slave I2C operation */ + Chip_I2C_Cmd(LPC_I2C0, I2C_MASTER_MODE, ENABLE); + /* Init UDA1380 CODEC */ + while (UDA1380_init(&I2C_Config, audio_in_sel) != SUCCESS) {} +} + +/* FIXME */ +void Serial_CreateStream(void *Stream) +{ + // implement later +} + +/** + * @} + */ diff --git a/bsp/xplorer4330/libraries/lpc_board/boards_18xx_43xx/hitex_eva_18504350/board_hitex_eva_18504350.h b/bsp/xplorer4330/libraries/lpc_board/boards_18xx_43xx/hitex_eva_18504350/board_hitex_eva_18504350.h new file mode 100644 index 0000000000..0deb8c62c0 --- /dev/null +++ b/bsp/xplorer4330/libraries/lpc_board/boards_18xx_43xx/hitex_eva_18504350/board_hitex_eva_18504350.h @@ -0,0 +1,244 @@ +/* + * @brief Hitex EVA 1850/4350 board file + * + * @note + * Copyright(C) NXP Semiconductors, 2012 + * All rights reserved. + * + * @par + * Software that is described herein is for illustrative purposes only + * which provides customers with programming information regarding the + * LPC products. This software is supplied "AS IS" without any warranties of + * any kind, and NXP Semiconductors and its licensor disclaim any and + * all warranties, express or implied, including all implied warranties of + * merchantability, fitness for a particular purpose and non-infringement of + * intellectual property rights. NXP Semiconductors assumes no responsibility + * or liability for the use of the software, conveys no license or rights under any + * patent, copyright, mask work right, or any other intellectual property rights in + * or to any products. NXP Semiconductors reserves the right to make changes + * in the software without notification. NXP Semiconductors also makes no + * representation or warranty that such application will be suitable for the + * specified use without further testing or modification. + * + * @par + * Permission to use, copy, modify, and distribute this software and its + * documentation is hereby granted, under NXP Semiconductors' and its + * licensor's relevant copyrights in the software, without fee, provided that it + * is used in conjunction with NXP Semiconductors microcontrollers. This + * copyright, permission, and disclaimer notice must appear in all copies of + * this code. + */ + +#ifndef __BOARD_HITEX_EVA_18504350_H_ +#define __BOARD_HITEX_EVA_18504350_H_ + +#include "chip.h" +#include "board_api.h" +#include "lpc_phy.h" + +#ifdef __cplusplus +extern "C" { +#endif + +/** @defgroup BOARD_HITEX_EVA_18504350 LPC1850 and LPC4350 Hitex EVA board support functions + * @ingroup BOARDS_18XX_43XX + * @{ + */ + +/** @defgroup BOARD_HITEX_EVA_18504350_OPTIONS BOARD: LPC1850 and LPC4350 Hitex EVA board builds options + * The NGX board has options that configure it's operation at build-time.
+ * CHIP_LPC* + * - One of @ref CHIP_LPC18XX or @ref CHIP_LPC43XX must be defined for this board + * DEBUG:
+ * - When defined, DEBUGOUT and DEBUGSTR functions are routed to the UART defined by DEBUG_UART
+ * - When not defined, DEBUGOUT and DEBUGSTR are null functions

+ * DEBUG_UART:
+ * - This defines the UART used for debug output when DEBUG is defined, example: @ref LPC_USART0

+ * CRYSTAL_MAIN_FREQ_IN:
+ * - This define specifies the crystal input clock into the chip, example: 12000000

+ * CRYSTAL_32K_FREQ_IN:
+ * - This define specifies the RTC crystal input clock into the chip, example: 32768

+ * EXTERNAL_CLKIN_FREQ_IN:
+ * - This define specifies the clock rate input into the EXTCLKIN pin, example: 28000000

+ * MAX_CLOCK_FREQ:
+ * - When defined, this will be used to configure the CPU clock rate, example: 150000000
+ * - When not defined, the system will use the maximum CPU clokc rate

+ * USE_RMII:
+ * - When defined, the system will be configured for RMII mode for Ethernet
+ * - When not defined, the system will be configured for MII mode for Ethernet

+ * BOARD_HITEX_EVA_18504350:
+ * - When building for Hitex boards, BOARD_HITEX_EVA_18504350 is defined
+ *

+ * For more information on driver options see @ref LPCOPEN_DESIGN_ARPPROACH
+ * @{ + */ + +/** + * @} + */ + +/** + * HITEX board defintion, can be used in examples for board specific code + */ +#define BOARD_HITEX_EVA_18504350 + +/* For USBLIB examples */ +#define LEDS_LED1 0x01 +#define LEDS_LED2 0x02 +#define LEDS_LED3 0x04 +#define LEDS_LED4 0x08 +#define LEDS_NO_LEDS 0x00 +#define BUTTONS_BUTTON1 0x01 +#define JOY_UP 0x01 +#define JOY_DOWN 0x02 +#define JOY_LEFT 0x04 +#define JOY_RIGHT 0x08 +#define JOY_PRESS 0x10 +#define NO_BUTTON_PRESSED 0x00 + +#define BUTTONS_BUTTON1_GPIO_PORT_NUM 6 +#define BUTTONS_BUTTON1_GPIO_BIT_NUM 21 + +#define I2CDEV_PCA9502_ADDR (0x9A >> 1) +#define PCA9502_REG_IODIR 0x0A +#define PCA9502_REG_IOSTATE 0x0B +#define PCA9502_REG_IOINTENA 0x0C +#define PCA9502_REG_IOCONTROL 0x0E +#define PCA9502_REG_ADDR(x) (((x) & 0x0F) << 3) + +/** + * Address of I2C device (UDA1380 CODEC) on board + */ +#define I2CDEV_UDA1380_ADDR (0x34 >> 1) + +/** + * Default location of LCD buffer is in DRAM + */ +#define FRAMEBUFFER_ADDR 0x28000000 + +/** + * LCD configuration data + */ +extern const LCD_Config_Type EA320x240; + +/** + * Default LCD configuration data for examples + */ +#define BOARD_LCD EA320x240 + +/** + * CODEC audio input sources + */ +typedef enum { + MCB_18XX_AUDIO_MIC_SELECT = 1 << 2 | 1 << 3, + MCB_18XX_AUDIO_LINE_IN_SELECT = 0x00, +} Board_Audio_Input_Sel_Type; + +/** + * @brief Initialize pin muxing for a UART + * @param UARTx : Pointer to UART register block for UART pins to init + * @return Nothing + */ +void Board_UART_Init(LPC_USART_Type *UARTx); + +/** + * @brief Initialize button(s) interface on board + * @return Nothing + */ +void Board_Buttons_Init(void); + +/** + * @brief Returns button(s) state on board + * @return Returns BUTTONS_BUTTON1 if button1 is pressed + */ +uint32_t Buttons_GetStatus(void); + +/** + * @brief Initialize joystick interface on board + * @return Nothing + */ +void Board_Joystick_Init(void); + +/** + * @brief Returns joystick states on board + * @return Returns a JOY_* value, ir JOY_PRESS or JOY_UP + */ +uint8_t Joystick_GetStatus(void); + +/** + * @brief Returns the MAC address assigned to this board + * @param mcaddr : Pointer to 6-byte character array to populate with MAC address + * @return Nothing + */ +void Board_ENET_GetMacADDR(uint8_t *mcaddr); + +/** + * @brief Sets up board specific ADC interface + * @return Nothing + */ +void Board_ADC_Init(void); + +/** + * @brief Sets up board specific I2C interface + * @param I2Cx : Pointer to I2C interface to initialize + * @return Nothing + */ +void Board_I2C_Init(LPC_I2C_Type *I2Cx); + +/** + * @brief Initialize the LCD interface + * @return Nothing + */ +void Board_LCD_Init(void); + +/** + * @brief Initialize TSC2046 touchscreen controller + * @return Nothing + */ +void Init_Touch_Controller(void); + +/** + * @brief Get Touch coordinates + * @param pX : Pointer to x-Coord to populate + * @param pY : Pointer to y-Coord to populate + * @return Nothing + */ +bool GetTouchPos(int16_t *pX, int16_t *pY); + +/** + * @brief Initialize pin muxing for SDMMC interface + * @return Nothing + */ +void Board_SDMMC_Init(void); + +/** + * @brief Initialize pin muxing for SSP interface + * @param SSPx : Pointer to SSP interface to initialize + * @return Nothing + */ +void Board_SSP_Init(LPC_SSP_Type *SSPx); + +/** + * @brief Initialize I2S interface for the board and UDA1380 + * @param I2Sx : Pointer to I2S register interface used on this board + * @param audio_in_sel : Audio input selection + * @return Nothing + */ +void Board_Audio_Init(LPC_I2S_Type *I2Sx, Board_Audio_Input_Sel_Type audio_in_sel); + +/** + * @brief FIXME + * @param Stream : FIXME + * @return Nothing + */ +void Serial_CreateStream(void *Stream); + +/** + * @} + */ + +#ifdef __cplusplus +} +#endif + +#endif /* __BOARD_HITEX_EVA_18504350_H_ */ diff --git a/bsp/xplorer4330/libraries/lpc_board/boards_18xx_43xx/hitex_eva_18504350/hitex_eva_1850/sys_config.h b/bsp/xplorer4330/libraries/lpc_board/boards_18xx_43xx/hitex_eva_18504350/hitex_eva_1850/sys_config.h new file mode 100644 index 0000000000..f129c4c5ca --- /dev/null +++ b/bsp/xplorer4330/libraries/lpc_board/boards_18xx_43xx/hitex_eva_18504350/hitex_eva_1850/sys_config.h @@ -0,0 +1,58 @@ +/* + * @note + * Copyright(C) NXP Semiconductors, 2012 + * All rights reserved. + * + * @par + * Software that is described herein is for illustrative purposes only + * which provides customers with programming information regarding the + * LPC products. This software is supplied "AS IS" without any warranties of + * any kind, and NXP Semiconductors and its licensor disclaim any and + * all warranties, express or implied, including all implied warranties of + * merchantability, fitness for a particular purpose and non-infringement of + * intellectual property rights. NXP Semiconductors assumes no responsibility + * or liability for the use of the software, conveys no license or rights under any + * patent, copyright, mask work right, or any other intellectual property rights in + * or to any products. NXP Semiconductors reserves the right to make changes + * in the software without notification. NXP Semiconductors also makes no + * representation or warranty that such application will be suitable for the + * specified use without further testing or modification. + * + * @par + * Permission to use, copy, modify, and distribute this software and its + * documentation is hereby granted, under NXP Semiconductors' and its + * licensor's relevant copyrights in the software, without fee, provided that it + * is used in conjunction with NXP Semiconductors microcontrollers. This + * copyright, permission, and disclaimer notice must appear in all copies of + * this code. + */ + +#ifndef __SYS_CONFIG_H_ +#define __SYS_CONFIG_H_ + +// #define USE_RMII +#define CHIP_LPC18XX + +/* Enable DEBUG for IO support via the UART */ +#define DEBUG + +/* Enable DEBUG_SEMIHOSTING along with DEBUG to enable IO support + via semihosting */ +// #define DEBUG_SEMIHOSTING + +/* Board UART used for debug output */ +#define DEBUG_UART LPC_USART0 + +/* Crystal frequency into device */ +#define CRYSTAL_MAIN_FREQ_IN 12000000 + +/* Crystal frequency into device for RTC/32K input */ +#define CRYSTAL_32K_FREQ_IN 32768 + +/* Frequency on external clock in pin */ +#define EXTERNAL_CLKIN_FREQ_IN 0 + +/* Default CPU clock frequency */ +#define MAX_CLOCK_FREQ (180000000) + +#endif /* __SYS_CONFIG_H_ */ diff --git a/bsp/xplorer4330/libraries/lpc_board/boards_18xx_43xx/hitex_eva_18504350/hitex_eva_4350/sys_config.h b/bsp/xplorer4330/libraries/lpc_board/boards_18xx_43xx/hitex_eva_18504350/hitex_eva_4350/sys_config.h new file mode 100644 index 0000000000..94ba5c68f0 --- /dev/null +++ b/bsp/xplorer4330/libraries/lpc_board/boards_18xx_43xx/hitex_eva_18504350/hitex_eva_4350/sys_config.h @@ -0,0 +1,58 @@ +/* + * @note + * Copyright(C) NXP Semiconductors, 2012 + * All rights reserved. + * + * @par + * Software that is described herein is for illustrative purposes only + * which provides customers with programming information regarding the + * LPC products. This software is supplied "AS IS" without any warranties of + * any kind, and NXP Semiconductors and its licensor disclaim any and + * all warranties, express or implied, including all implied warranties of + * merchantability, fitness for a particular purpose and non-infringement of + * intellectual property rights. NXP Semiconductors assumes no responsibility + * or liability for the use of the software, conveys no license or rights under any + * patent, copyright, mask work right, or any other intellectual property rights in + * or to any products. NXP Semiconductors reserves the right to make changes + * in the software without notification. NXP Semiconductors also makes no + * representation or warranty that such application will be suitable for the + * specified use without further testing or modification. + * + * @par + * Permission to use, copy, modify, and distribute this software and its + * documentation is hereby granted, under NXP Semiconductors' and its + * licensor's relevant copyrights in the software, without fee, provided that it + * is used in conjunction with NXP Semiconductors microcontrollers. This + * copyright, permission, and disclaimer notice must appear in all copies of + * this code. + */ + +#ifndef __SYS_CONFIG_H_ +#define __SYS_CONFIG_H_ + +// #define USE_RMII +#define CHIP_LPC43XX + +/* Enable DEBUG for IO support via the UART */ +#define DEBUG + +/* Enable DEBUG_SEMIHOSTING along with DEBUG to enable IO support + via semihosting */ +// #define DEBUG_SEMIHOSTING + +/* Board UART used for debug output */ +#define DEBUG_UART LPC_USART0 + +/* Crystal frequency into device */ +#define CRYSTAL_MAIN_FREQ_IN 12000000 + +/* Crystal frequency into device for RTC/32K input */ +#define CRYSTAL_32K_FREQ_IN 32768 + +/* Frequency on external clock in pin */ +#define EXTERNAL_CLKIN_FREQ_IN 0 + +/* Default CPU clock frequency */ +#define MAX_CLOCK_FREQ (204000000) + +#endif /* __SYS_CONFIG_H_ */ diff --git a/bsp/xplorer4330/libraries/lpc_board/boards_18xx_43xx/hitex_eva_18504350/sysinit_hitex_eva_18504350.c b/bsp/xplorer4330/libraries/lpc_board/boards_18xx_43xx/hitex_eva_18504350/sysinit_hitex_eva_18504350.c new file mode 100644 index 0000000000..3e61c9b1b5 --- /dev/null +++ b/bsp/xplorer4330/libraries/lpc_board/boards_18xx_43xx/hitex_eva_18504350/sysinit_hitex_eva_18504350.c @@ -0,0 +1,455 @@ +/* + * Copyright(C) NXP Semiconductors, 2012 + * All rights reserved. + * + * Software that is described herein is for illustrative purposes only + * which provides customers with programming information regarding the + * LPC products. This software is supplied "AS IS" without any warranties of + * any kind, and NXP Semiconductors and its licensor disclaim any and + * all warranties, express or implied, including all implied warranties of + * merchantability, fitness for a particular purpose and non-infringement of + * intellectual property rights. NXP Semiconductors assumes no responsibility + * or liability for the use of the software, conveys no license or rights under any + * patent, copyright, mask work right, or any other intellectual property rights in + * or to any products. NXP Semiconductors reserves the right to make changes + * in the software without notification. NXP Semiconductors also makes no + * representation or warranty that such application will be suitable for the + * specified use without further testing or modification. + * + * Permission to use, copy, modify, and distribute this software and its + * documentation is hereby granted, under NXP Semiconductors' and its + * licensor's relevant copyrights in the software, without fee, provided that it + * is used in conjunction with NXP Semiconductors microcontrollers. This + * copyright, permission, and disclaimer notice must appear in all copies of + * this code. + */ + +#include "board.h" + +/** @defgroup BOARD_HITEX_EVA_18504350_SYSINIT LPC1850 and LPC4350 Hitex EVA board System Init code + * @ingroup BOARD_HITEX_EVA_18504350 + * The System initialization code is called prior to the application and + * initializes the board for run-time operation. Board initialization + * for the Hitex EVA boards includes clock setup, default pin muxing, and + * memory configuration. + * + * With the exception of stack space, no RW memory is used for this call. + * + * LPC1850 and LPC4350 Hitex EVA setup
+ * Clocking:
+ * All base clocks enabled by default (Save power by disabling un-needed clocks)
+ * CPU PLL set to maximum clock frequency (as defined by MAX_CLOCK_FREQ value)
+ * SPIFI FLASH clock setup for fastest speed
+ * Pin muxing:
+ * Sets up various pin mux functions for the board (Ethernet, LEDs, etc.)
+ * Sets up the external memory controller signals
+ * Memory:
+ * Sets up DRAM, static RAM, and NOR FLASH. + * @{ + */ + +#ifndef CORE_M0 +/* SCR pin definitions for pin muxing */ +typedef struct { + uint8_t pingrp; /* Pin group */ + uint8_t pinnum; /* Pin number */ + uint8_t pincfg; /* Pin configuration for SCU */ + uint8_t funcnum;/* Function number */ +} PINMUX_GRP_T; + +/* Structure for initial base clock states */ +struct CLK_BASE_STATES { + CGU_BASE_CLK_T clk; /* Base clock */ + CGU_CLKIN_T clkin; /* Base clock source, see UM for allowable souorces per base clock */ + bool autoblock_enab;/* Set to true to enable autoblocking on frequency change */ + bool powerdn; /* Set to true if the base clock is initially powered down */ +}; + +/* Initial base clock states are mostly on */ +STATIC const struct CLK_BASE_STATES InitClkStates[] = { + {CLK_BASE_SAFE, CLKIN_IRC, true, false}, + {CLK_BASE_APB1, CLKIN_MAINPLL, true, false}, + {CLK_BASE_APB3, CLKIN_MAINPLL, true, false}, + {CLK_BASE_USB0, CLKIN_USBPLL, true, false}, +#if defined(CHIP_LPC43XX) + {CLK_BASE_PERIPH, CLKIN_MAINPLL, true, false}, +#endif + {CLK_BASE_USB1, CLKIN_USBPLL, true, false}, +#if defined(CHIP_LPC43XX) + {CLK_BASE_SPI, CLKIN_MAINPLL, true, false}, +#endif + {CLK_BASE_PHY_TX, CLKIN_ENET_TX, true, false}, +#if defined(USE_RMII) + {CLK_BASE_PHY_RX, CLKIN_ENET_TX, true, false}, +#else + {CLK_BASE_PHY_RX, CLKIN_ENET_RX, true, false}, +#endif + {CLK_BASE_LCD, CLKIN_MAINPLL, true, true}, +#if defined(CHIP_LPC43XX) + {CLK_BASE_VADC, CLKIN_MAINPLL, true, true}, +#endif + {CLK_BASE_SDIO, CLKIN_MAINPLL, true, false}, + {CLK_BASE_SSP0, CLKIN_MAINPLL, true, false}, + {CLK_BASE_SSP1, CLKIN_MAINPLL, true, false}, + {CLK_BASE_UART0, CLKIN_MAINPLL, true, false}, + {CLK_BASE_UART1, CLKIN_MAINPLL, true, false}, + {CLK_BASE_UART2, CLKIN_MAINPLL, true, false}, + {CLK_BASE_UART3, CLKIN_MAINPLL, true, false}, + {CLK_BASE_OUT, CLKINPUT_PD, true, false}, + {CLK_BASE_APLL, CLKINPUT_PD, true, false}, + {CLK_BASE_CGU_OUT0, CLKINPUT_PD, true, false}, + {CLK_BASE_CGU_OUT1, CLKINPUT_PD, true, false} +}; + +/* SPIFI high speed pin mode setup */ +STATIC const PINMUX_GRP_T spifipinmuxing[] = { + {0x3, 3, (MD_PLN_FAST), FUNC3}, /* SPIFI CLK */ + {0x3, 4, (MD_PLN_FAST), FUNC3}, /* SPIFI D3 */ + {0x3, 5, (MD_PLN_FAST), FUNC3}, /* SPIFI D2 */ + {0x3, 6, (MD_PLN_FAST), FUNC3}, /* SPIFI D1 */ + {0x3, 7, (MD_PLN_FAST), FUNC3}, /* SPIFI D0 */ + {0x3, 8, (MD_PLN_FAST), FUNC3} /* SPIFI CS/SSEL */ +}; + +/* Setup system clocking */ +STATIC void SystemSetupClocking(void) +{ + int i; + + /* Switch main system clocking to crystal */ + Chip_Clock_EnableCrystal(); + Chip_Clock_SetBaseClock(CLK_BASE_MX, CLKIN_CRYSTAL, true, false); + + /* Setup PLL for 100MHz and switch main system clocking */ + Chip_Clock_SetupMainPLLHz(CLKIN_CRYSTAL, CRYSTAL_MAIN_FREQ_IN, 100 * 1000000, 100 * 1000000); + Chip_Clock_SetBaseClock(CLK_BASE_MX, CLKIN_MAINPLL, true, false); + + /* Setup PLL for maximum clock */ + Chip_Clock_SetupMainPLLHz(CLKIN_CRYSTAL, CRYSTAL_MAIN_FREQ_IN, MAX_CLOCK_FREQ, MAX_CLOCK_FREQ); + + /* Setup system base clocks and initial states. This won't enable and + disable individual clocks, but sets up the base clock sources for + each individual peripheral clock. */ + for (i = 0; i < (sizeof(InitClkStates) / sizeof(InitClkStates[0])); i++) { + Chip_Clock_SetBaseClock(InitClkStates[i].clk, InitClkStates[i].clkin, + InitClkStates[i].autoblock_enab, InitClkStates[i].powerdn); + } + + /* Reset and enable 32Khz oscillator */ + LPC_CREG->CREG0 &= ~((1 << 3) | (1 << 2)); + LPC_CREG->CREG0 |= (1 << 1) | (1 << 0); + + /* SPIFI pin setup is done prior to setting up system clocking */ + for (i = 0; i < (sizeof(spifipinmuxing) / sizeof(spifipinmuxing[0])); i++) { + Chip_SCU_PinMux(spifipinmuxing[i].pingrp, spifipinmuxing[i].pinnum, + spifipinmuxing[i].pincfg, spifipinmuxing[i].funcnum); + } + + /* Setup a divider E for main PLL clock switch SPIFI clock to that divider. + Divide rate is based on CPU speed and speed of SPI FLASH part. */ +#if (MAX_CLOCK_FREQ > 180000000) + Chip_Clock_SetDivider(CLK_IDIV_E, CLKIN_MAINPLL, 5); +#else + Chip_Clock_SetDivider(CLK_IDIV_E, CLKIN_MAINPLL, 4); +#endif + Chip_Clock_SetBaseClock(CLK_BASE_SPIFI, CLKIN_IDIVE, true, false); +} + +STATIC const PINMUX_GRP_T pinmuxing[] = { +#if defined(USE_RMII) + /* RMII pin group */ + {0x1, 19, (MD_EHS | MD_PLN | MD_EZI | MD_ZI), FUNC0}, + {0x0, 1, (MD_EHS | MD_PLN | MD_ZI), FUNC6}, + {0x1, 18, (MD_EHS | MD_PLN | MD_ZI), FUNC3}, + {0x1, 20, (MD_EHS | MD_PLN | MD_ZI), FUNC3}, + {0x1, 17, (MD_EHS | MD_PLN | MD_EZI | MD_ZI), FUNC3}, + {0xC, 1, (MD_EHS | MD_PLN | MD_ZI), FUNC3}, + {0x1, 16, (MD_EHS | MD_PLN | MD_EZI | MD_ZI), FUNC7}, + {0x1, 15, (MD_EHS | MD_PLN | MD_EZI | MD_ZI), FUNC3}, + {0x0, 0, (MD_EHS | MD_PLN | MD_EZI | MD_ZI), FUNC2}, +#else + /* MII pin group */ + {0x1, 19, (MD_PLN | MD_EZI), FUNC0}, + {0x0, 1, (MD_PLN), FUNC6}, + {0x1, 18, (MD_PLN), FUNC3}, + {0x1, 20, (MD_PLN), FUNC3}, + {0x1, 17, (MD_PLN | MD_EZI), FUNC3}, + {0xC, 1, (MD_PLN), FUNC3}, + {0x1, 16, (MD_PLN | MD_EZI), FUNC7}, + {0x1, 15, (MD_PLN | MD_EZI), FUNC3}, + {0x0, 0, (MD_PLN | MD_EZI), FUNC2}, + {0x9, 4, (MD_PLN), FUNC5}, + {0x9, 5, (MD_PLN), FUNC5}, + {0xC, 0, (MD_PLN | MD_EZI), FUNC3}, + {0x9, 0, (MD_PLN | MD_EZI), FUNC5}, + {0x9, 1, (MD_PLN | MD_EZI), FUNC5}, + {0x9, 6, (MD_PLN | MD_EZI), FUNC5}, + {0x9, 3, (MD_PLN | MD_EZI), FUNC5}, + {0x9, 2, (MD_PLN | MD_EZI), FUNC5}, + {0xC, 8, (MD_PLN | MD_EZI), FUNC4}, +#endif + /* External data lines D0 .. D15 */ + {0x1, 7, (MD_PLN | MD_EZI | MD_ZI | MD_EHS), FUNC3}, + {0x1, 8, (MD_PLN | MD_EZI | MD_ZI | MD_EHS), FUNC3}, + {0x1, 9, (MD_PLN | MD_EZI | MD_ZI | MD_EHS), FUNC3}, + {0x1, 10, (MD_PLN | MD_EZI | MD_ZI | MD_EHS), FUNC3}, + {0x1, 11, (MD_PLN | MD_EZI | MD_ZI | MD_EHS), FUNC3}, + {0x1, 12, (MD_PLN | MD_EZI | MD_ZI | MD_EHS), FUNC3}, + {0x1, 13, (MD_PLN | MD_EZI | MD_ZI | MD_EHS), FUNC3}, + {0x1, 14, (MD_PLN | MD_EZI | MD_ZI | MD_EHS), FUNC3}, + {0x5, 4, (MD_PLN | MD_EZI | MD_ZI | MD_EHS), FUNC2}, + {0x5, 5, (MD_PLN | MD_EZI | MD_ZI | MD_EHS), FUNC2}, + {0x5, 6, (MD_PLN | MD_EZI | MD_ZI | MD_EHS), FUNC2}, + {0x5, 7, (MD_PLN | MD_EZI | MD_ZI | MD_EHS), FUNC2}, + {0x5, 0, (MD_PLN | MD_EZI | MD_ZI | MD_EHS), FUNC2}, + {0x5, 1, (MD_PLN | MD_EZI | MD_ZI | MD_EHS), FUNC2}, + {0x5, 2, (MD_PLN | MD_EZI | MD_ZI | MD_EHS), FUNC2}, + {0x5, 3, (MD_PLN | MD_EZI | MD_ZI | MD_EHS), FUNC2}, + /* Address lines A0 .. A23 */ + {0x2, 9, (MD_PLN | MD_EZI | MD_ZI | MD_EHS), FUNC3}, + {0x2, 10, (MD_PLN | MD_EZI | MD_ZI | MD_EHS), FUNC3}, + {0x2, 11, (MD_PLN | MD_EZI | MD_ZI | MD_EHS), FUNC3}, + {0x2, 12, (MD_PLN | MD_EZI | MD_ZI | MD_EHS), FUNC3}, + {0x2, 13, (MD_PLN | MD_EZI | MD_ZI | MD_EHS), FUNC3}, + {0x1, 0, (MD_PLN | MD_EZI | MD_ZI | MD_EHS), FUNC2}, + {0x1, 1, (MD_PLN | MD_EZI | MD_ZI | MD_EHS), FUNC2}, + {0x1, 2, (MD_PLN | MD_EZI | MD_ZI | MD_EHS), FUNC2}, + {0x2, 8, (MD_PLN | MD_EZI | MD_ZI | MD_EHS), FUNC3}, + {0x2, 7, (MD_PLN | MD_EZI | MD_ZI | MD_EHS), FUNC3}, + {0x2, 6, (MD_PLN | MD_EZI | MD_ZI | MD_EHS), FUNC2}, + {0x2, 2, (MD_PLN | MD_EZI | MD_ZI | MD_EHS), FUNC2}, + {0x2, 1, (MD_PLN | MD_EZI | MD_ZI | MD_EHS), FUNC2}, + {0x2, 0, (MD_PLN | MD_EZI | MD_ZI | MD_EHS), FUNC2}, + {0x6, 8, (MD_PLN | MD_EZI | MD_ZI | MD_EHS), FUNC1}, + {0x6, 7, (MD_PLN | MD_EZI | MD_ZI | MD_EHS), FUNC1}, + {0xD, 16, (MD_PLN | MD_EZI | MD_ZI | MD_EHS), FUNC2}, + {0xD, 15, (MD_PLN | MD_EZI | MD_ZI | MD_EHS), FUNC2}, + {0xE, 0, (MD_PLN | MD_EZI | MD_ZI | MD_EHS), FUNC3}, + {0xE, 1, (MD_PLN | MD_EZI | MD_ZI | MD_EHS), FUNC3}, + {0xE, 2, (MD_PLN | MD_EZI | MD_ZI | MD_EHS), FUNC3}, + {0xE, 3, (MD_PLN | MD_EZI | MD_ZI | MD_EHS), FUNC3}, + {0xE, 4, (MD_PLN | MD_EZI | MD_ZI | MD_EHS), FUNC3}, + {0xA, 4, (MD_PLN | MD_EZI | MD_ZI | MD_EHS), FUNC3}, + /* EMC control signals */ + {0x1, 4, (MD_PLN | MD_EZI | MD_ZI | MD_EHS), FUNC3}, + {0x6, 6, (MD_PLN | MD_EZI | MD_ZI | MD_EHS), FUNC1}, + {0xD, 13, (MD_PLN | MD_EZI | MD_ZI | MD_EHS), FUNC2}, + {0xD, 10, (MD_PLN | MD_EZI | MD_ZI | MD_EHS), FUNC2}, + {0x6, 9, (MD_PLN | MD_EZI | MD_ZI | MD_EHS), FUNC3}, + {0x1, 6, (MD_PLN | MD_EZI | MD_ZI | MD_EHS), FUNC3}, + {0x6, 4, (MD_PLN | MD_EZI | MD_ZI | MD_EHS), FUNC3}, + {0x6, 5, (MD_PLN | MD_EZI | MD_ZI | MD_EHS), FUNC3}, + {PINMUX_CLK, 0, (MD_PLN | MD_EZI | MD_ZI | MD_EHS), FUNC0}, + {PINMUX_CLK, 1, (MD_PLN | MD_EZI | MD_ZI | MD_EHS), FUNC0}, + {PINMUX_CLK, 2, (MD_PLN | MD_EZI | MD_ZI | MD_EHS), FUNC0}, + {PINMUX_CLK, 3, (MD_PLN | MD_EZI | MD_ZI | MD_EHS), FUNC0}, + {0x6, 11, (MD_PLN | MD_EZI | MD_ZI | MD_EHS), FUNC3}, + {0x6, 12, (MD_PLN | MD_EZI | MD_ZI | MD_EHS), FUNC3}, + {0x6, 10, (MD_PLN | MD_EZI | MD_ZI | MD_EHS), FUNC3}, + {0xD, 0, (MD_PLN | MD_EZI | MD_ZI | MD_EHS), FUNC2}, + {0xE, 13, (MD_PLN | MD_EZI | MD_ZI | MD_EHS), FUNC3}, + {0x1, 3, MD_PLN_FAST, FUNC3}, + {0x1, 4, MD_PLN_FAST, FUNC3}, + {0x6, 6, MD_PLN_FAST, FUNC3}, + {0x1, 5, MD_PLN_FAST, FUNC3}, + /* LCD interface, 24bpp */ + {0x7, 7, MD_PUP, FUNC3}, + {0x4, 7, MD_PUP, FUNC0}, + {0x4, 5, MD_PUP, FUNC2}, + {0x4, 6, MD_PUP, FUNC2}, + {0x7, 6, MD_PUP, FUNC3}, + {0x4, 1, MD_PUP, FUNC2}, + {0x4, 4, MD_PUP, FUNC2}, + {0x4, 2, MD_PUP, FUNC2}, + {0x8, 7, MD_PUP, FUNC3}, + {0x8, 6, MD_PUP, FUNC3}, + {0x8, 5, MD_PUP, FUNC3}, + {0x8, 4, MD_PUP, FUNC3}, + {0x7, 5, MD_PUP, FUNC3}, + {0x4, 8, MD_PUP, FUNC2}, + {0x4, 10, MD_PUP, FUNC2}, + {0x4, 9, MD_PUP, FUNC2}, + {0x8, 3, MD_PUP, FUNC3}, + {0xB, 6, MD_PUP, FUNC2}, + {0xB, 5, MD_PUP, FUNC2}, + {0xB, 4, MD_PUP, FUNC2}, + {0x7, 4, MD_PUP, FUNC3}, + {0x7, 2, MD_PUP, FUNC3}, + {0x7, 1, MD_PUP, FUNC3}, + {0xB, 3, MD_PUP, FUNC2}, + {0xB, 2, MD_PUP, FUNC2}, + {0xB, 1, MD_PUP, FUNC2}, + {0xB, 0, MD_PUP, FUNC2}, + {0x7, 0, MD_PUP, FUNC3}, + {0x4, 4, MD_PUP, FUNC0}, + {0x7, 3, MD_PUP, FUNC0}, + {0x4, 1, MD_PUP, FUNC0}, + /* Board LEDs */ + {0x8, 1, MD_PDN, FUNC0}, + {0xE, 6, MD_PDN, FUNC4}, /* GPIO7.6, green */ + {0xE, 8, MD_PDN, FUNC4}, /* GPIO7.8, blue */ + {0xE, 5, MD_PDN, FUNC4}, /* GPIO7.5, red */ + /* Board ADC */ + {0xF, 9, MD_PLN, FUNC7}, + /* I2S */ + {0x3, 0, MD_PLN_FAST, FUNC2}, + {0x6, 0, MD_PLN_FAST, FUNC4}, + {0x7, 2, MD_PLN_FAST, FUNC2}, + {0x6, 2, MD_PLN_FAST, FUNC3}, + {0x7, 1, MD_PLN_FAST, FUNC2}, + {0x6, 1, MD_PLN_FAST, FUNC3}, +}; + +/* Sets up system pin muxing */ +STATIC void SystemSetupMuxing(void) +{ + int i; + + /* Setup system level pin muxing */ + for (i = 0; i < (sizeof(pinmuxing) / sizeof(pinmuxing[0])); i++) { + Chip_SCU_PinMux(pinmuxing[i].pingrp, pinmuxing[i].pinnum, + pinmuxing[i].pincfg, pinmuxing[i].funcnum); + } +} + +/* EMC clock delay */ +#define CLK0_DELAY 7 + +/* Hitex SDRAM timing and chip Config */ +STATIC const IP_EMC_DYN_CONFIG_Type IS42S16400_config = { + EMC_NANOSECOND(64000000 / 4096), /* Row refresh time */ + 0x01, /* Command Delayed */ + EMC_NANOSECOND(20), + EMC_NANOSECOND(60), + EMC_NANOSECOND(63), + EMC_CLOCK(0x05), + EMC_CLOCK(0x05), + EMC_CLOCK(0x04), + EMC_NANOSECOND(63), + EMC_NANOSECOND(63), + EMC_NANOSECOND(63), + EMC_NANOSECOND(14), + EMC_CLOCK(0x02), + { + { + EMC_ADDRESS_DYCS0, /* Hitex Board uses DYCS0 for SDRAM */ + 3, /* RAS */ + + EMC_DYN_MODE_WBMODE_PROGRAMMED | + EMC_DYN_MODE_OPMODE_STANDARD | + EMC_DYN_MODE_CAS_3 | + EMC_DYN_MODE_BURST_TYPE_SEQUENTIAL | + EMC_DYN_MODE_BURST_LEN_8, + + EMC_DYN_CONFIG_DATA_BUS_16 | + EMC_DYN_CONFIG_LPSDRAM | + EMC_DYN_CONFIG_4Mx16_4BANKS_12ROWS_8COLS | + EMC_DYN_CONFIG_MD_SDRAM + }, + {0, 0, 0, 0}, + {0, 0, 0, 0}, + {0, 0, 0, 0} + } +}; + +/* Hitex Static RAM timing and chip Config */ +STATIC const IP_EMC_STATIC_CONFIG_Type IS62WV25616_config = { + 2, + EMC_STATIC_CONFIG_MEM_WIDTH_16 | + EMC_STATIC_CONFIG_CS_POL_ACTIVE_LOW | + EMC_STATIC_CONFIG_BLS_HIGH /* | + EMC_CONFIG_BUFFER_ENABLE*/, + + EMC_NANOSECOND(0), + EMC_NANOSECOND(30), + EMC_NANOSECOND(90), + EMC_NANOSECOND(55), + EMC_NANOSECOND(55), + EMC_NANOSECOND(55) +}; + +/* Hitex NorFlash timing and chip Config */ +STATIC const IP_EMC_STATIC_CONFIG_Type SST39VF320_config = { + 0, + EMC_STATIC_CONFIG_MEM_WIDTH_16 | + EMC_STATIC_CONFIG_CS_POL_ACTIVE_LOW | + EMC_STATIC_CONFIG_BLS_HIGH /* | + EMC_CONFIG_BUFFER_ENABLE*/, + + EMC_NANOSECOND(0), + EMC_NANOSECOND(35), + EMC_NANOSECOND(70), + EMC_NANOSECOND(70), + EMC_NANOSECOND(40), + EMC_CLOCK(4) +}; + +/* Setup external memories */ +STATIC void SystemSetupMemory(void) +{ + /* Setup EMC Delays */ + /* Move all clock delays together */ + LPC_SCU->EMCDELAYCLK = ((CLK0_DELAY) | (CLK0_DELAY << 4) | (CLK0_DELAY << 8) | (CLK0_DELAY << 12)); + + /* Setup EMC Clock Divider for divide by 2 */ + Chip_Clock_EnableOpts(CLK_MX_EMC_DIV, true, true, 2); + LPC_CREG->CREG6 |= (1 << 16); + Chip_Clock_Enable(CLK_MX_EMC); + + /* Init EMC Controller -Enable-LE mode- clock ratio 1:1 */ + Chip_EMC_Init(1, 0, 0); + /* Init EMC Dynamic Controller */ + Chip_EMC_Dynamic_Init((IP_EMC_DYN_CONFIG_Type *) &IS42S16400_config); + /* Init EMC Static Controller CS2 */ + Chip_EMC_Static_Init((IP_EMC_STATIC_CONFIG_Type *) &IS62WV25616_config); + /* Init EMC Static Controller CS0 */ + Chip_EMC_Static_Init((IP_EMC_STATIC_CONFIG_Type *) &SST39VF320_config); + + /* Enable Buffer for External Flash */ + LPC_EMC->STATICCONFIG0 |= 1 << 19; +} + +#endif + +/** + * @brief Setup the system + * SystemInit() is called prior to the application and sets up system + * clocking, memory, and any resources needed prior to the application + * starting. + * @return none + */ +void SystemInit(void) +{ +#if defined(CORE_M3) || defined(CORE_M4) + unsigned int *pSCB_VTOR = (unsigned int *) 0xE000ED08; + +#if defined(__IAR_SYSTEMS_ICC__) + extern void *__vector_table; + + *pSCB_VTOR = (unsigned int) &__vector_table; +#elif defined(__CODE_RED) + extern void *g_pfnVectors; + + *pSCB_VTOR = (unsigned int) &g_pfnVectors; +#elif defined(__ARMCC_VERSION) + extern void *__Vectors; + + *pSCB_VTOR = (unsigned int) &__Vectors; +#endif + +#if defined(__FPU_PRESENT) && __FPU_PRESENT == 1 + fpuInit(); +#endif + + /* Setup system clocking and memory. This is done early to allow the + application and tools to clear memory and use scatter loading to + external memory. */ + SystemSetupClocking(); + SystemSetupMuxing(); + SystemSetupMemory(); +#endif +} + +/** + * @} + */ diff --git a/bsp/xplorer4330/libraries/lpc_board/boards_18xx_43xx/keil_mcb_18574357/board.h b/bsp/xplorer4330/libraries/lpc_board/boards_18xx_43xx/keil_mcb_18574357/board.h new file mode 100644 index 0000000000..f0be4a28f5 --- /dev/null +++ b/bsp/xplorer4330/libraries/lpc_board/boards_18xx_43xx/keil_mcb_18574357/board.h @@ -0,0 +1,37 @@ +/* + * @brief Keil MCB 1857/4357 board file + * + * @note + * Copyright(C) NXP Semiconductors, 2012 + * All rights reserved. + * + * @par + * Software that is described herein is for illustrative purposes only + * which provides customers with programming information regarding the + * LPC products. This software is supplied "AS IS" without any warranties of + * any kind, and NXP Semiconductors and its licensor disclaim any and + * all warranties, express or implied, including all implied warranties of + * merchantability, fitness for a particular purpose and non-infringement of + * intellectual property rights. NXP Semiconductors assumes no responsibility + * or liability for the use of the software, conveys no license or rights under any + * patent, copyright, mask work right, or any other intellectual property rights in + * or to any products. NXP Semiconductors reserves the right to make changes + * in the software without notification. NXP Semiconductors also makes no + * representation or warranty that such application will be suitable for the + * specified use without further testing or modification. + * + * @par + * Permission to use, copy, modify, and distribute this software and its + * documentation is hereby granted, under NXP Semiconductors' and its + * licensor's relevant copyrights in the software, without fee, provided that it + * is used in conjunction with NXP Semiconductors microcontrollers. This + * copyright, permission, and disclaimer notice must appear in all copies of + * this code. + */ + +#ifndef __BOARD_H_ +#define __BOARD_H_ + +#include "board_keil_mcb_18574357.h" + +#endif /* __BOARD_H_ */ diff --git a/bsp/xplorer4330/libraries/lpc_board/boards_18xx_43xx/keil_mcb_18574357/board_keil_mcb_18574357.c b/bsp/xplorer4330/libraries/lpc_board/boards_18xx_43xx/keil_mcb_18574357/board_keil_mcb_18574357.c new file mode 100644 index 0000000000..6955b4fd1c --- /dev/null +++ b/bsp/xplorer4330/libraries/lpc_board/boards_18xx_43xx/keil_mcb_18574357/board_keil_mcb_18574357.c @@ -0,0 +1,841 @@ +/* + * @brief Keil MCB 1857/4357 board file + * + * @note + * Copyright(C) NXP Semiconductors, 2012 + * All rights reserved. + * + * @par + * Software that is described herein is for illustrative purposes only + * which provides customers with programming information regarding the + * LPC products. This software is supplied "AS IS" without any warranties of + * any kind, and NXP Semiconductors and its licensor disclaim any and + * all warranties, express or implied, including all implied warranties of + * merchantability, fitness for a particular purpose and non-infringement of + * intellectual property rights. NXP Semiconductors assumes no responsibility + * or liability for the use of the software, conveys no license or rights under any + * patent, copyright, mask work right, or any other intellectual property rights in + * or to any products. NXP Semiconductors reserves the right to make changes + * in the software without notification. NXP Semiconductors also makes no + * representation or warranty that such application will be suitable for the + * specified use without further testing or modification. + * + * @par + * Permission to use, copy, modify, and distribute this software and its + * documentation is hereby granted, under NXP Semiconductors' and its + * licensor's relevant copyrights in the software, without fee, provided that it + * is used in conjunction with NXP Semiconductors microcontrollers. This + * copyright, permission, and disclaimer notice must appear in all copies of + * this code. + */ + +#include "board.h" +#include "string.h" + +/* Keil board uses 83848 PHY and retarget */ +#include "lpc_phy_dp83848.c" +#include "retarget.c" + +/** @ingroup BOARD_KEIL_MCB_18574357 + * @{ + */ + +/***************************************************************************** + * Private types/enumerations/variables + ****************************************************************************/ +/* Port and bit mapping for LEDs on GPIOs */ +static const uint8_t ledports[] = {6, 6, 6, 6, 6, 4, 4, 4}; +static const uint8_t ledbits[] = {24, 25, 26, 27, 28, 12, 13, 14}; + +/** UDA specified variables */ +/* System Register Data Set */ +uint16_t UDA_sys_regs_dat[] = { + UDA1380_REG_EVALCLK_DEFAULT_VALUE, + UDA1380_REG_I2S_DEFAULT_VALUE, + UDA1380_REG_PWRCTRL_DEFAULT_VALUE, + UDA1380_REG_ANAMIX_DEFAULT_VALUE, + UDA1380_REG_HEADAMP_DEFAULT_VALUE +}; + +/* System Register Data Set */ +uint16_t UDA_interfil_regs_dat[] = { + UDA1380_REG_MSTRVOL_DEFAULT_VALUE, + UDA1380_REG_MIXVOL_DEFAULT_VALUE, + UDA1380_REG_MODEBBT_DEFAULT_VALUE, + UDA1380_REG_MSTRMUTE_DEFAULT_VALUE, + UDA1380_REG_MIXSDO_DEFAULT_VALUE +}; +/* decimator Register Data Set */ +uint16_t UDA_decimator_regs_dat[] = { + UDA1380_REG_DECVOL_DEFAULT_VALUE, + UDA1380_REG_PGA_DEFAULT_VALUE, + UDA1380_REG_ADC_DEFAULT_VALUE, + UDA1380_REG_AGC_DEFAULT_VALUE +}; + +/** Private definitions for LCD */ +#define LCD_CS(x) ((x) ? (Chip_GPIO_WritePortBit(7, 16, true)) : (Chip_GPIO_WritePortBit(7, 16, false))) + +/** Private variables for LCD */ +uint32_t g_isPenDn; +uint32_t g_isNewPenDn; +const int32_t ad_left = 3813; +const int32_t ad_top = 3805;// 237; +const int32_t ad_right = 360; +const int32_t ad_bottom = 237; // 3805; + +const LCD_Config_Type MCB4300_LCD = { + 8, /*!< Horizontal back porch in clocks */ + 4, /*!< Horizontal front porch in clocks */ + 4, /*!< HSYNC pulse width in clocks */ + 240, /*!< Pixels per line */ + 4, /*!< Vertical back porch in clocks */ + 3, /*!< Vertical front porch in clocks */ + 4, /*!< VSYNC pulse width in clocks */ + 320, /*!< Lines per panel */ + 0, /*!< Invert output enable, 1 = invert */ + 1, /*!< Invert panel clock, 1 = invert */ + 1, /*!< Invert HSYNC, 1 = invert */ + 1, /*!< Invert VSYNC, 1 = invert */ + 1, /*!< AC bias frequency in clocks (not used) */ + 6, /*!< Maximum bits per pixel the display supports */ + LCD_TFT, /*!< LCD panel type */ + LCD_COLOR_FORMAT_RGB, /*!< BGR or RGB */ + 0 /*!< Dual panel, 1 = dual panel display */ +}; + +/***************************************************************************** + * Public types/enumerations/variables + ****************************************************************************/ + +/*!< System Clock Frequency (Core Clock)*/ +uint32_t SystemCoreClock; + +/***************************************************************************** + * Private functions + ****************************************************************************/ + +/* Very simple (inaccurate) delay function */ +static void delay(uint32_t i) { + while (i--) {} +} + +/* Write data to UDA register */ +static void UDA_Reg_write(UDA1380_REG reg, unsigned short value, I2C_M_SETUP_Type *I2C_Config) { + + I2C_Config->tx_data[0] = reg; + I2C_Config->tx_data[1] = value >> 8; + I2C_Config->tx_data[2] = value & 0xFF; + Chip_I2C_MasterTransmitData(LPC_I2C0, I2C_Config, I2C_TRANSFER_POLLING); + delay(10000); +} + +/* Read data from UDA register */ +static uint16_t UDA_Reg_read(UDA1380_REG reg) { + uint8_t rx_data[2]; + Chip_I2C_MasterReadReg(LPC_I2C0, I2CDEV_UDA1380_ADDR, reg, rx_data, 2); + return rx_data[0] << 8 | rx_data[1]; +} + +/* Initializes default settings for UDA1380 */ +static Status UDA1380_init(I2C_M_SETUP_Type *I2C_Config, Board_Audio_Input_Sel_Type audio_in_sel) +{ + uint16_t temp; + uint8_t i; + /* Reset UDA1380 on board Keil */ + Chip_SCU_PinMux(0x8, 0, MD_PUP, FUNC0); + Chip_GPIO_WriteDirBit(4, 0, true); + Chip_GPIO_WritePortBit(4, 0, true); + /* delay 1us */ + delay(100000); + Chip_GPIO_WritePortBit(4, 0, false); + delay(100000); + for (i = 0; i < 5; i++) { + UDA_Reg_write((UDA1380_REG) (UDA_EVALM_CLK + i), UDA_sys_regs_dat[i], I2C_Config); + temp = UDA_Reg_read((UDA1380_REG) (UDA_EVALM_CLK + i)); + if (temp != UDA_sys_regs_dat[i]) { + return ERROR; + } + } + + /* interfilter regs init */ + for (i = 0; i < 5; i++) { + UDA_Reg_write((UDA1380_REG) (UDA_MASTER_VOL_CTRL + i), UDA_interfil_regs_dat[i], I2C_Config); + temp = UDA_Reg_read((UDA1380_REG) (UDA_MASTER_VOL_CTRL + i)); + if (temp != UDA_interfil_regs_dat[i]) { + return ERROR; + } + } + /* decimator regs init */ + for (i = 0; i < 4; i++) { + UDA_Reg_write((UDA1380_REG) (UDA_DEC_VOL_CTRL + i), UDA_decimator_regs_dat[i], I2C_Config); + temp = UDA_Reg_read((UDA1380_REG) (UDA_DEC_VOL_CTRL + i)); + if (temp != UDA_decimator_regs_dat[i]) { + return ERROR; + } + } + + if (audio_in_sel == MCB_18XX_AUDIO_MIC_SELECT) { + /* Disable Power On for ADCR, PGAR, PGAL to get mic sound more clearly */ + UDA_Reg_write((UDA1380_REG) (UDA_POWER_CTRL), UDA1380_REG_PWRCTRL_DEFAULT_VALUE & (~(0x0B)), I2C_Config); + temp = UDA_Reg_read((UDA1380_REG) (UDA_ADC_CTRL)); + if (temp != (UDA1380_REG_ADC_DEFAULT_VALUE | MCB_18XX_AUDIO_MIC_SELECT)) { + return ERROR; + } + UDA_Reg_write((UDA1380_REG) (UDA_ADC_CTRL), + UDA1380_REG_ADC_DEFAULT_VALUE | MCB_18XX_AUDIO_MIC_SELECT, + I2C_Config); + temp = UDA_Reg_read((UDA1380_REG) (UDA_ADC_CTRL)); + if (temp != (UDA1380_REG_ADC_DEFAULT_VALUE | MCB_18XX_AUDIO_MIC_SELECT)) { + return ERROR; + } + } + return SUCCESS; + +} + +/** Private functions for LCD controller */ +/* Write to LCD controller, with A0 = 0 */ +static void LCD_X_Write00_16(uint16_t c) { + + uint8_t buf[1]; + LCD_CS(0); + buf[0] = 0x70; + Chip_SSP_WriteFrames_Blocking(SSP_ID, buf, 1); // Start + WR Register + buf[0] = (uint8_t) (c); + Chip_SSP_WriteFrames_Blocking(SSP_ID, buf, 1); + LCD_CS(1); +} + +/* Write to LCD controller, with A0 = 1 */ +static void LCD_X_Write01_16(uint16_t c) { + + uint8_t buf[1]; + LCD_CS(0); + buf[0] = 0x72; + Chip_SSP_WriteFrames_Blocking(SSP_ID, buf, 1); /* Start + WR Data */ + buf[0] = (uint8_t) (c >> 8); + Chip_SSP_WriteFrames_Blocking(SSP_ID, buf, 1); + buf[0] = (uint8_t) (c); + Chip_SSP_WriteFrames_Blocking(SSP_ID, buf, 1); + LCD_CS(1); +} + +/* Write to LCD controller's register */ +static void wr_reg(uint16_t reg, uint16_t dat) { + LCD_X_Write00_16(reg); + LCD_X_Write01_16(dat); +} + +/* Pin configuration to communicate with LCD Controller */ +static void pinConfig(void) +{ + /* (DC) */ + Chip_GPIO_WriteDirBit(7, 16, true); + // Chip_Clock_EnableOpts(sspclk, true, true, 1); +} + +/* Writes a value to the STMPE811 register */ +static uint32_t Board_TSC_WriteReg(IP_I2C_001_Type *I2Cx, uint8_t regAddr, uint8_t value) +{ + return Chip_I2C_MasterWriteReg(I2Cx, TSC_I2C_ADDR, regAddr, &value, 1); +} + +/* Reads a value to the STMPE811 register */ +static uint32_t Board_TSC_ReadReg(IP_I2C_001_Type *I2Cx, uint8_t regAddr, uint8_t *value) +{ + return Chip_I2C_MasterReadReg(I2Cx, TSC_I2C_ADDR, regAddr, value, 1); +} + +/* Check if touch is detected or not */ +static bool Board_TSC_TouchDetect(IP_I2C_001_Type *I2Cx) +{ + uint8_t CtrRegVal = 0; + + if (Board_TSC_ReadReg(I2Cx, TSC_CTRL, &CtrRegVal) == 1) { + if (CtrRegVal & (1 << 7)) { + return true; + } + } + return false; +} + +/* Get the touch coordinates from STMPE811 registers */ +static Status Board_TSC_GetTouchCoord(IP_I2C_001_Type *I2Cx, int16_t *x, int16_t *y) +{ + uint8_t fifo_size, tscData[4], i; + + /* Read all samples except the last one */ + Board_TSC_ReadReg(I2Cx, FIFO_SIZE, &fifo_size); + for (i = 0; i < fifo_size; ++i) + if (Chip_I2C_MasterReadReg(I2Cx, TSC_I2C_ADDR, DATA_XYZ, tscData, 4) == 0) { + return ERROR; + } + + /* Retrieve last taken sample */ + Chip_I2C_MasterReadReg(I2Cx, TSC_I2C_ADDR, DATA_XYZ, tscData, 4); + *x = (tscData[0] << 4) | ((tscData[1] & 0xF0) >> 4); + *y = ((tscData[1] & 0x0F) << 8) | tscData[2]; + + /* Clear interrupt flags */ + Board_TSC_WriteReg(I2Cx, INT_STA, 0x1F); + + return SUCCESS; +} + +/***************************************************************************** + * Public functions + ****************************************************************************/ + +/* Update system core clock rate, should be called if the system has + a clock rate change */ +void SystemCoreClockUpdate(void) +{ + /* CPU core speed */ + SystemCoreClock = Chip_Clock_GetRate(CLK_MX_MXCORE); +} + +/* Initialize UART pins */ +void Board_UART_Init(LPC_USART_Type *UARTx) +{ + if (UARTx == LPC_USART0) { + Chip_SCU_PinMux(0x2, 0, MD_PDN, FUNC1); /* P2.0 : UART0_TXD */ + Chip_SCU_PinMux(0x2, 1, MD_PLN | MD_EZI | MD_ZI, FUNC1); /* P2.1 : UART0_RXD */ + } + else if (UARTx == LPC_USART3) { + Chip_SCU_PinMux(0x2, 3, MD_PDN, FUNC2); /* P2.3 : UART3_TXD */ + Chip_SCU_PinMux(0x2, 4, MD_PLN | MD_EZI | MD_ZI, FUNC2); /* P2.4 : UART3_RXD */ + } +} + +/* Initialize debug output via UART for board */ +void Board_Debug_Init(void) +{ +#if defined(DEBUG_UART) + Board_UART_Init(DEBUG_UART); + + Chip_UART_Init(DEBUG_UART); + Chip_UART_SetBaud(DEBUG_UART, 115200); + Chip_UART_ConfigData(DEBUG_UART, UART_DATABIT_8, UART_PARITY_NONE, UART_STOPBIT_1); + + /* Enable UART Transmit */ + Chip_UART_TxCmd(DEBUG_UART, ENABLE); +#endif +} + +/* Sends a character on the UART */ +void Board_UARTPutChar(char ch) +{ +#if defined(DEBUG_UART) + while (Chip_UART_SendByte(DEBUG_UART, (uint8_t) ch) == ERROR) {} +#endif +} + +/* Gets a character from the UART, returns EOF if no character is ready */ +int Board_UARTGetChar(void) +{ +#if defined(DEBUG_UART) + uint8_t data; + + if (Chip_UART_ReceiveByte(DEBUG_UART, &data) == SUCCESS) { + return (int) data; + } +#endif + return EOF; +} + +/* Outputs a string on the debug UART */ +void Board_UARTPutSTR(char *str) +{ +#if defined(DEBUG_UART) + while (*str != '\0') { + Board_UARTPutChar(*str++); + } +#endif +} + +/* Initializes board LED(s) */ +void Board_LED_Init() +{ + int i; + + /* Must make sure J21 is installed to enabled LEDs */ + /* PD.10 : LED 0 (leftmost) */ + /* PD.11 : LED 1 */ + /* PD.12 : LED 2 */ + /* PD.13 : LED 3 */ + /* PD.14 : LED 4 */ + /* P9.0 : LED 5 */ + /* P9.1 : LED 6 */ + /* P9.2 : LED 7 (rightmost) */ + for (i = 0; i < (sizeof(ledports) / sizeof(ledports[0])); i++) { + Chip_GPIO_WriteDirBit(ledports[i], ledbits[i], true); + } +} + +#ifndef BOARD_LED_TEST_FUNCTION_WORKS + /* FIXME: temporary code for toggle LED support only */ + static uint8_t LEDStates; /* shadow variable for LED states */ +#endif + +/* Sets the state of a board LED to on or off */ +void Board_LED_Set(uint8_t LEDNumber, bool On) +{ + if (LEDNumber <= 7) { + Chip_GPIO_WritePortBit(ledports[LEDNumber], ledbits[LEDNumber], On); +#ifndef BOARD_LED_TEST_FUNCTION_WORKS + if (On) { + LEDStates |= (1 << LEDNumber); /* set the state */ + } else { + LEDStates &= ~(1 << LEDNumber); /* clear the state */ + } +#endif + } +} + +/* Returns the current state of a board LED */ +bool Board_LED_Test(uint8_t LEDNumber) +{ + if (LEDNumber <= 7) { +#ifndef BOARD_LED_TEST_FUNCTION_WORKS + if (LEDStates & (1 << LEDNumber)) { /* LED is on */ + return true; + } else { /* LED is off */ + return false; + } +#else + return (bool)Chip_GPIO_ReadPortBit(ledports[LEDNumber], ledbits[LEDNumber]); +#endif + } + return false; +} + +/* Returns the MAC address assigned to this board */ +void Board_ENET_GetMacADDR(uint8_t *mcaddr) +{ + const uint8_t boardmac[] = {0x00, 0x60, 0x37, 0x12, 0x34, 0x56}; + + memcpy(mcaddr, boardmac, 6); +} + +/* Set up and initialize all required blocks and functions related to the + board hardware */ +void Board_Init(void) +{ + /* Sets up DEBUG UART */ + DEBUGINIT(); + + /* Updates SystemCoreClock global var with current clock speed */ + SystemCoreClockUpdate(); + + /* Initializes GPIO */ + Chip_GPIO_Init(); + + /* Setup GPIOs for USB demos */ + Chip_SCU_PinMux(0x9, 5, (MD_PUP | MD_EZI), FUNC2); /* P9_5 USB1_VBUS_EN, USB1 VBus function */ + Chip_SCU_PinMux(0x2, 5, (MD_PLN | MD_EZI | MD_ZI), FUNC2); /* P2_5 USB1_VBUS, MUST CONFIGURE THIS SIGNAL FOR USB1 NORMAL OPERATION */ + Chip_SCU_PinMux(0x6, 3, (MD_PUP | MD_EZI), FUNC1); /* P6_3 USB0_PWR_EN, USB0 VBus function */ +} + +/* Sets up board specific ADC interface */ +void Board_ADC_Init(void) +{} + +/* Sets up board specific I2C interface */ +void Board_I2C_Init(LPC_I2C_Type *I2Cx) +{ + if (I2Cx == LPC_I2C1) { + /* Configure pin function for I2C1 on PE.13 (I2C1_SDA) and PE.15 (I2C1_SCL) */ + Chip_SCU_PinMux(0xE, 13, MD_ZI | MD_EZI, FUNC2); + Chip_SCU_PinMux(0xE, 15, MD_ZI | MD_EZI, FUNC2); + } +} + +/* Sets up board specific I2S interface and UDA1380 */ +void Board_Audio_Init(LPC_I2S_Type *I2Sx, Board_Audio_Input_Sel_Type audio_in_sel) +{ + uint8_t uda1380_tx_data_buf[3]; + Chip_I2S_Audio_Format_Type I2S_Config; + I2C_M_SETUP_Type I2C_Config; + I2C_Config.sl_addr7bit = I2CDEV_UDA1380_ADDR; + I2C_Config.retransmissions_max = 5; + I2C_Config.tx_length = 3; + I2C_Config.tx_data = uda1380_tx_data_buf; + I2C_Config.rx_length = 0; + I2C_Config.rx_data = NULL; + + /* Initialize I2C peripheral ------------------------------------*/ + /* Init I2C */ + Chip_I2C_Init(LPC_I2C0); + Chip_I2C_SetClockRate(LPC_I2C0, 100000); + + I2S_Config.SampleRate = 48000; + I2S_Config.ChannelNumber = 2; /* 1 is mono, 2 is stereo */ + I2S_Config.WordWidth = 16; /* 8, 16 or 32 bits */ + Chip_I2S_Init(LPC_I2S0); + Chip_I2S_Config(LPC_I2S0, I2S_TX_MODE, &I2S_Config); + /* Enable Slave I2C operation */ + Chip_I2C_Cmd(LPC_I2C0, I2C_MASTER_MODE, ENABLE); + /* Init UDA1380 CODEC */ + while (UDA1380_init(&I2C_Config, audio_in_sel) != SUCCESS) {} +} + +/* Initialize the LCD interface */ +void Board_LCD_Init(void) +{ + /* LCD with HX8347-D LCD Controller */ + SSP_ConfigFormat ssp_format1; + /* Attach main PLL clock to divider A with a divider of 2 */ + Chip_Clock_SetDivider(CLK_IDIV_A, CLKIN_MAINPLL, 2); + + /* Route divider A output to LCD base clock and enable base clock */ + Chip_Clock_SetBaseClock(CLK_BASE_LCD, CLKIN_IDIVA, true, false); + + /* Reset LCD and wait for reset to complete */ + Chip_RGU_TriggerReset(RGU_LCD_RST); + while (Chip_RGU_InReset(RGU_LCD_RST)) {} + + /* Set backlight GPIO as an output */ + Chip_GPIO_WriteDirBit(3, 8, true); + + delay(5); + + pinConfig(); + // Chip_Clock_EnablePeripheralMax(SSP_ID); + /* TBD Externally */ + Chip_SSP_Init(SSP_ID); + // NVIC_EnableIRQ(SSP_ID); + Chip_SSP_Set_Master(SSP_ID, true); + Chip_SSP_Set_BitRate(SSP_ID, 1000000); + + ssp_format1.frameFormat = SSP_FRAMEFORMAT_SPI; + ssp_format1.bits = SSP_BITS_8; + ssp_format1.clockFormat = SSP_CLOCK_MODE0; + + Chip_SSP_Set_Format(SSP_ID, &ssp_format1); + Chip_SSP_Cmd(SSP_ID, ENABLE); + + delay(200); + + /* Driving ability settings ------------------------------------------------*/ + wr_reg(0xEA, 0x00); /* Power control internal used (1) */ + wr_reg(0xEB, 0x20); /* Power control internal used (2) */ + wr_reg(0xEC, 0x0C); /* Source control internal used (1) */ + wr_reg(0xED, 0xC7); /* Source control internal used (2) */ + wr_reg(0xE8, 0x38); /* Source output period Normal mode */ + wr_reg(0xE9, 0x10); /* Source output period Idle mode */ + wr_reg(0xF1, 0x01); /* RGB 18-bit interface ;0x0110 */ + wr_reg(0xF2, 0x10); + + /* Adjust the Gamma Curve --------------------------------------------------*/ + wr_reg(0x40, 0x01); + wr_reg(0x41, 0x00); + wr_reg(0x42, 0x00); + wr_reg(0x43, 0x10); + wr_reg(0x44, 0x0E); + wr_reg(0x45, 0x24); + wr_reg(0x46, 0x04); + wr_reg(0x47, 0x50); + wr_reg(0x48, 0x02); + wr_reg(0x49, 0x13); + wr_reg(0x4A, 0x19); + wr_reg(0x4B, 0x19); + wr_reg(0x4C, 0x16); + + wr_reg(0x50, 0x1B); + wr_reg(0x51, 0x31); + wr_reg(0x52, 0x2F); + wr_reg(0x53, 0x3F); + wr_reg(0x54, 0x3F); + wr_reg(0x55, 0x3E); + wr_reg(0x56, 0x2F); + wr_reg(0x57, 0x7B); + wr_reg(0x58, 0x09); + wr_reg(0x59, 0x06); + wr_reg(0x5A, 0x06); + wr_reg(0x5B, 0x0C); + wr_reg(0x5C, 0x1D); + wr_reg(0x5D, 0xCC); + + /* Power voltage setting ---------------------------------------------------*/ + wr_reg(0x1B, 0x1B); + wr_reg(0x1A, 0x01); + wr_reg(0x24, 0x2F); + wr_reg(0x25, 0x57); + wr_reg(0x23, 0x88); + + /* Power on setting --------------------------------------------------------*/ + wr_reg(0x18, 0x36); /* Internal oscillator frequency adj */ + wr_reg(0x19, 0x01); /* Enable internal oscillator */ + wr_reg(0x01, 0x00); /* Normal mode, no scrool */ + wr_reg(0x1F, 0x88); /* Power control 6 - DDVDH Off */ + delay(20); + wr_reg(0x1F, 0x82); /* Power control 6 - Step-up: 3 x VCI */ + delay(5); + wr_reg(0x1F, 0x92); /* Power control 6 - Step-up: On */ + delay(5); + wr_reg(0x1F, 0xD2); /* Power control 6 - VCOML active */ + delay(5); + + /* Color selection ---------------------------------------------------------*/ + wr_reg(0x17, 0x55); /* RGB, System interface: 16 Bit/Pixel*/ + wr_reg(0x00, 0x00); /* Scrolling off, no standby */ + + /* Interface config --------------------------------------------------------*/ + wr_reg(0x2F, 0x11); /* LCD Drive: 1-line inversion */ + wr_reg(0x31, 0x02); /* Value for SPI: 0x00, RBG: 0x02 */ + wr_reg(0x32, 0x00); /* DPL=0, HSPL=0, VSPL=0, EPL=0 */ + + /* Display on setting ------------------------------------------------------*/ + wr_reg(0x28, 0x38); /* PT(0,0) active, VGL/VGL */ + delay(20); + wr_reg(0x28, 0x3C); /* Display active, VGL/VGL */ + + wr_reg(0x16, 0x00); /* Mem Access Control (MX/Y/V/L,BGR) */ + + /* Display scrolling settings ----------------------------------------------*/ + wr_reg(0x0E, 0x00); /* TFA MSB */ + wr_reg(0x0F, 0x00); /* TFA LSB */ + wr_reg(0x10, 320 >> 8); /* VSA MSB */ + wr_reg(0x11, 320 & 0xFF); /* VSA LSB */ + wr_reg(0x12, 0x00); /* BFA MSB */ + wr_reg(0x13, 0x00); /* BFA LSB */ + +} + +/* Initializes the STMPE811 touch screen controller */ +void Init_Touch_Controller(void) +{ + volatile int32_t i; + + /* Init I2C */ + Chip_I2C_Init(LPC_I2C0); + Chip_I2C_SetClockRate(LPC_I2C0, 100000); + + /* Enable Slave I2C operation */ + Chip_I2C_Cmd(LPC_I2C0, I2C_MASTER_MODE, ENABLE); + + /* Reset Touch-screen controller */ + Board_TSC_WriteReg(LPC_I2C0, SYS_CTRL1, 0x02); + + for (i = 0; i < 200000; i++) {} + + /* Enable TSC and ADC */ + Board_TSC_WriteReg(LPC_I2C0, SYS_CTRL2, 0x0C); + /* Enable Touch detect, FIFO */ + Board_TSC_WriteReg(LPC_I2C0, INT_EN, 0x07); + /* Set sample time , 12-bit mode */ + Board_TSC_WriteReg(LPC_I2C0, ADC_CTRL1, 0x69); + + for (i = 0; i < 40000; i++) {} + + /* ADC frequency 3.25 MHz */ + Board_TSC_WriteReg(LPC_I2C0, ADC_CTRL2, 0x01); + /* Tracking index: 8, operation mode : XY only */ + Board_TSC_WriteReg(LPC_I2C0, TSC_CTRL, 0x22); + /* Detect delay 10us Settle time 500us*/ + Board_TSC_WriteReg(LPC_I2C0, TSC_CFG, 0xC2); + /* Threshold for FIFO */ + Board_TSC_WriteReg(LPC_I2C0, FIFO_TH, 0x01); + /* FIFO reset */ + Board_TSC_WriteReg(LPC_I2C0, FIFO_STA, 0x01); + /* FIFO not reset */ + Board_TSC_WriteReg(LPC_I2C0, FIFO_STA, 0x00); + /* Drive 50 mA typical */ + Board_TSC_WriteReg(LPC_I2C0, TSC_I_DRIVE, 0x01); + /* Pins are used for touchscreen */ + Board_TSC_WriteReg(LPC_I2C0, GPIO_ALT_FUNCT, 0x00); + /* Enable TSC */ + Board_TSC_WriteReg(LPC_I2C0, TSC_CTRL, 0x01); + /* Clear interrupt status */ + Board_TSC_WriteReg(LPC_I2C0, INT_STA, 0xFF); +} + +/* Get touch screen position */ +bool GetTouchPos(int16_t *pX, int16_t *pY) +{ + int16_t x, y, rng; + if (Board_TSC_TouchDetect(LPC_I2C0)) { + Board_TSC_GetTouchCoord(LPC_I2C0, &x, &y); + g_isPenDn = 1; + g_isNewPenDn = 1; + + /* calibrate X */ + rng = ad_right - ad_left; + if (rng < 0) { + rng = -rng; + } + x -= (ad_right < ad_left) ? ad_right : ad_left; + *pX = (x * C_GLCD_H_SIZE) / rng; + if (ad_left > ad_right) { + *pX = C_GLCD_H_SIZE - *pX; + } + + /* calibrate Y */ + rng = ad_bottom - ad_top; + if (rng < 0) { + rng = -rng; + } + y -= (ad_bottom < ad_top) ? ad_bottom : ad_top; + *pY = (y * C_GLCD_V_SIZE) / rng; + if (ad_top > ad_bottom) { + *pY = C_GLCD_V_SIZE - *pY; + } + } + else { + g_isPenDn = 0; + } + + if (g_isNewPenDn) { + g_isNewPenDn = 0; + if (*pX < 0) { + *pX = -*pX; + } + if (*pY < 0) { + *pY = -*pY; + } + return true; + } + return false; +} + +/* Turn on LCD backlight */ +void Board_LCD_Set_Backlight(uint8_t Intensity) +{ + bool OnOff = (bool) (Intensity != 0); + + Chip_GPIO_WritePortBit(3, 8, OnOff); +} + +/* Interrupt handler for GPIO0 */ +void GPIO0_IRQHandler(void) +{ + static bool On; + + if (Chip_GPIO_IntGetStatus(0, 0, 0)) { + Chip_GPIO_IntClear(0, 0); + On = (bool) !On; + Board_LED_Set(1, On); + } +} + +/* Initializes board specific GPIO Interrupt */ +void Board_GPIO_Int_Init() +{ + Chip_SCU_PinMux(0xF, 9, (MD_PLN | MD_EZI | MD_ZI), FUNC0); /* PF.9 : POTI button */ + Chip_GPIO_WriteDirBit(7, 23, false); /* PF.9 -> GPIO7[23] : input */ + Chip_SCU_GPIOIntPinSel(0, 7, 23); + Chip_GPIO_IntCmd(0, 0, IP_GPIOPININT_FALLING_EDGE); /* Configure GPIO0[7] to interrupt pin (SW2 switch) */ + + NVIC_EnableIRQ(PIN_INT0_IRQn); /* enable GPIO interrupt 0 */ +} + +/* Initializes SDMMC interface */ +void Board_SDMMC_Init(void) +{ + Chip_SCU_PinMux(0xC, 4, MD_PLN_FAST, FUNC7); /* PC.4 connected to SDIO_D0 */ + Chip_SCU_PinMux(0xC, 5, MD_PLN_FAST, FUNC7); /* PC.5 connected to SDIO_D1 */ + Chip_SCU_PinMux(0xC, 6, MD_PLN_FAST, FUNC7); /* PC.6 connected to SDIO_D2 */ + Chip_SCU_PinMux(0xC, 7, MD_PLN_FAST, FUNC7); /* PC.7 connected to SDIO_D3 */ + + Chip_SCU_PinMux(0xC, 8, MD_PLN | MD_EZI, FUNC7);/* PC.4 connected to SDIO_CD */ + Chip_SCU_PinMux(0xC, 10, MD_PLN_FAST, FUNC7); /* PC.10 connected to SDIO_CMD */ + Chip_SCU_PinMux(0xC, 0, MD_PLN | MD_EHS, FUNC7);/* PC.0 connected to SDIO_CLK */ +} + +/* Initializes SSP interface */ +void Board_SSP_Init(LPC_SSP_Type *SSPx) +{ + if (SSPx == LPC_SSP0) { + /* Set up clock and power for SSP0 module */ + /* Configure SSP0 pins*/ + Chip_SCU_PinMux(0x3, 3, MD_PLN_FAST, FUNC2); /* P3.3 connected to SCL/SCLK func2=SSP0 SCK0 */ + Chip_SCU_PinMux(0x3, 6, MD_PLN_FAST, FUNC2); /* P3.6 connected to nCS func2=SSP0 SSEL0 */ + Chip_SCU_PinMux(0x3, 7, MD_PLN | MD_EZI | MD_ZI, FUNC2); /* P3.7 connected to SO func2=SSP0 MISO0 */ + Chip_SCU_PinMux(0x3, 8, MD_PLN | MD_EZI | MD_ZI, FUNC2); /* P3.8 connected to nSI func2=SSP0 MOSI0 */ + + Chip_Clock_EnableOpts(CLK_MX_SSP0, true, true, 1); + } + else if (SSPx == LPC_SSP1) { + /* Set up clock and power for SSP1 module */ + /* Configure SSP1 pins*/ + Chip_SCU_PinMux(0xF, 4, MD_PLN_FAST, FUNC0); /* PF.4 connected to SCL/SCLK func0 = SSP1 SCK1 */ + Chip_SCU_PinMux(0xF, 5, MD_PLN_FAST, FUNC2); /* PF.5 connected to nCS func2 = SSP1 SSEL1 */ + Chip_SCU_PinMux(0xF, 6, MD_PLN | MD_EZI | MD_ZI, FUNC2); /* PF.6 connected to SO func2 = SSP1 MISO1 */ + Chip_SCU_PinMux(0xF, 7, MD_PLN | MD_EZI | MD_ZI, FUNC2); /* PF.7 connected to nSI func2 = SSP1 MOSI1 */ + + Chip_Clock_EnableOpts(CLK_MX_SSP1, true, true, 1); + } + else { + return; + } +} + +/* Initializes board specific buttons */ +void Board_Buttons_Init(void) +{ + Chip_SCU_PinMux(0x4, 0, MD_PUP | MD_EZI | MD_ZI, FUNC0); /* P9.1 : LED 6 */ + Chip_GPIO_WriteDirBit(BUTTONS_BUTTON1_GPIO_PORT_NUM, BUTTONS_BUTTON1_GPIO_BIT_NUM, false); +} + +/* Sets up default states for joystick */ +void Board_Joystick_Init(void) +{ + Chip_SCU_PinMux(0xC, 9, MD_PUP | MD_EZI | MD_ZI, FUNC4); /* PC_9 as GPIO6[8] */ + Chip_SCU_PinMux(0xC, 11, MD_PUP | MD_EZI | MD_ZI, FUNC4); /* PC_11 as GPIO6[10] */ + Chip_SCU_PinMux(0xC, 12, MD_PUP | MD_EZI | MD_ZI, FUNC4); /* PC_12 as GPIO6[11] */ + Chip_SCU_PinMux(0xC, 13, MD_PUP | MD_EZI | MD_ZI, FUNC4); /* PC_13 as GPIO6[12] */ + Chip_SCU_PinMux(0xC, 14, MD_PUP | MD_EZI | MD_ZI, FUNC4); /* PC_14 as GPIO6[13] */ + + Chip_GPIO_WriteDirBit(JOYSTICK_UP_GPIO_PORT_NUM, JOYSTICK_UP_GPIO_BIT_NUM, false); /* input */ + Chip_GPIO_WriteDirBit(JOYSTICK_DOWN_GPIO_PORT_NUM, JOYSTICK_DOWN_GPIO_BIT_NUM, false); /* input */ + Chip_GPIO_WriteDirBit(JOYSTICK_LEFT_GPIO_PORT_NUM, JOYSTICK_LEFT_GPIO_BIT_NUM, false); /* input */ + Chip_GPIO_WriteDirBit(JOYSTICK_RIGHT_GPIO_PORT_NUM, JOYSTICK_RIGHT_GPIO_BIT_NUM, false); /* input */ + Chip_GPIO_WriteDirBit(JOYSTICK_PRESS_GPIO_PORT_NUM, JOYSTICK_PRESS_GPIO_BIT_NUM, false); /* input */ +} + +/* Gets joystick status */ +uint8_t Joystick_GetStatus(void) +{ + + uint8_t ret = NO_BUTTON_PRESSED; + + if (Chip_GPIO_ReadPortBit(JOYSTICK_UP_GPIO_PORT_NUM, JOYSTICK_UP_GPIO_BIT_NUM) == 0) { + ret |= JOY_UP; + } + else if (Chip_GPIO_ReadPortBit(JOYSTICK_DOWN_GPIO_PORT_NUM, JOYSTICK_DOWN_GPIO_BIT_NUM) == 0) { + ret |= JOY_DOWN; + } + else if (Chip_GPIO_ReadPortBit(JOYSTICK_LEFT_GPIO_PORT_NUM, JOYSTICK_LEFT_GPIO_BIT_NUM) == 0) { + ret |= JOY_LEFT; + } + else if (Chip_GPIO_ReadPortBit(JOYSTICK_RIGHT_GPIO_PORT_NUM, JOYSTICK_RIGHT_GPIO_BIT_NUM) == 0) { + ret |= JOY_RIGHT; + } + else if (Chip_GPIO_ReadPortBit(JOYSTICK_PRESS_GPIO_PORT_NUM, JOYSTICK_PRESS_GPIO_BIT_NUM) == 0) { + ret |= JOY_PRESS; + } + + return ret; +} + +/* Gets buttons status */ +uint32_t Buttons_GetStatus(void) +{ + uint8_t ret = NO_BUTTON_PRESSED; + + if (Chip_GPIO_ReadPortBit(BUTTONS_BUTTON1_GPIO_PORT_NUM, BUTTONS_BUTTON1_GPIO_BIT_NUM) == 0) { + ret |= BUTTONS_BUTTON1; + } + return ret; +} + +/* FIXME Should we remove this function? */ +void Serial_CreateStream(void *Stream) +{ + // implement later +} + +/** + * @} + */ diff --git a/bsp/xplorer4330/libraries/lpc_board/boards_18xx_43xx/keil_mcb_18574357/board_keil_mcb_18574357.h b/bsp/xplorer4330/libraries/lpc_board/boards_18xx_43xx/keil_mcb_18574357/board_keil_mcb_18574357.h new file mode 100644 index 0000000000..400904f7d7 --- /dev/null +++ b/bsp/xplorer4330/libraries/lpc_board/boards_18xx_43xx/keil_mcb_18574357/board_keil_mcb_18574357.h @@ -0,0 +1,304 @@ +/* + * @brief Keil MCB 1857/4357 board file + * + * @note + * Copyright(C) NXP Semiconductors, 2012 + * All rights reserved. + * + * @par + * Software that is described herein is for illustrative purposes only + * which provides customers with programming information regarding the + * LPC products. This software is supplied "AS IS" without any warranties of + * any kind, and NXP Semiconductors and its licensor disclaim any and + * all warranties, express or implied, including all implied warranties of + * merchantability, fitness for a particular purpose and non-infringement of + * intellectual property rights. NXP Semiconductors assumes no responsibility + * or liability for the use of the software, conveys no license or rights under any + * patent, copyright, mask work right, or any other intellectual property rights in + * or to any products. NXP Semiconductors reserves the right to make changes + * in the software without notification. NXP Semiconductors also makes no + * representation or warranty that such application will be suitable for the + * specified use without further testing or modification. + * + * @par + * Permission to use, copy, modify, and distribute this software and its + * documentation is hereby granted, under NXP Semiconductors' and its + * licensor's relevant copyrights in the software, without fee, provided that it + * is used in conjunction with NXP Semiconductors microcontrollers. This + * copyright, permission, and disclaimer notice must appear in all copies of + * this code. + */ + +#ifndef __BOARD_KEIL_MCB_18574357_H_ +#define __BOARD_KEIL_MCB_18574357_H_ + +#include "chip.h" +#include "board_api.h" +#include "lpc_phy.h" + +#ifdef __cplusplus +extern "C" { +#endif + +/** @defgroup BOARD_KEIL_MCB_18574357 LPC1857 and LPC4357 Keil MCB board support functions + * @ingroup BOARDS_18XX_43XX + * @{ + */ + +/** @defgroup BOARD_KEIL_MCB_18574357_OPTIONS BOARD: LPC1857 and LPC4357 Keil MCB board builds options + * The NGX board has options that configure it's operation at build-time.
+ * CHIP_LPC* + * - One of @ref CHIP_LPC18XX or @ref CHIP_LPC43XX must be defined for this board + * DEBUG:
+ * - When defined, DEBUGOUT and DEBUGSTR functions are routed to the UART defined by DEBUG_UART
+ * - When not defined, DEBUGOUT and DEBUGSTR are null functions

+ * DEBUG_UART:
+ * - This defines the UART used for debug output when DEBUG is defined, example: @ref LPC_USART0

+ * CRYSTAL_MAIN_FREQ_IN:
+ * - This define specifies the crystal input clock into the chip, example: 12000000

+ * CRYSTAL_32K_FREQ_IN:
+ * - This define specifies the RTC crystal input clock into the chip, example: 32768

+ * EXTERNAL_CLKIN_FREQ_IN:
+ * - This define specifies the clock rate input into the EXTCLKIN pin, example: 28000000

+ * MAX_CLOCK_FREQ:
+ * - When defined, this will be used to configure the CPU clock rate, example: 150000000
+ * - When not defined, the system will use the maximum CPU clokc rate

+ * BOARD_HITEX_EVA_18504350:
+ * - When building for Keil boards, BOARD_KEIL_MCB_18574357 is defined
+ *

+ * For more information on driver options see @ref LPCOPEN_DESIGN_ARPPROACH
+ * @{ + */ + +/** + * @} + */ + +#define BOARD_KEIL_MCB_18574357 + +#define LED_NUMBER_OF 1 + +#define BUTTONS_BUTTON1_GPIO_PORT_NUM 2 +#define BUTTONS_BUTTON1_GPIO_BIT_NUM 0 +#define JOYSTICK_UP_GPIO_PORT_NUM 6 +#define JOYSTICK_UP_GPIO_BIT_NUM 10 +#define JOYSTICK_DOWN_GPIO_PORT_NUM 6 +#define JOYSTICK_DOWN_GPIO_BIT_NUM 11 +#define JOYSTICK_LEFT_GPIO_PORT_NUM 6 +#define JOYSTICK_LEFT_GPIO_BIT_NUM 12 +#define JOYSTICK_RIGHT_GPIO_PORT_NUM 6 +#define JOYSTICK_RIGHT_GPIO_BIT_NUM 13 +#define JOYSTICK_PRESS_GPIO_PORT_NUM 6 +#define JOYSTICK_PRESS_GPIO_BIT_NUM 8 + +#define JOY_UP 0x01 +#define JOY_DOWN 0x02 +#define JOY_LEFT 0x04 +#define JOY_RIGHT 0x08 +#define JOY_PRESS 0x10 +#define NO_BUTTON_PRESSED 0x00 + +#define BUTTONS_BUTTON1 0x01 + +#define LEDS_LED1 0x01 +#define LEDS_LED2 0x02 +#define LEDS_LED3 0x04 +#define LEDS_LED4 0x08 +#define LEDS_NO_LEDS 0x00 + +/** UDA1380 register values */ +#define UDA1380_REG_EVALCLK_DEFAULT_VALUE (0xF << 8 | 0x3 << 4 | 1 << 1) +#define UDA1380_REG_I2S_DEFAULT_VALUE 0x0000 + +#define UDA1380_REG_PWRCTRL_DEFAULT_VALUE (1 << 15 | 1 << 13 | 1 << 10 | 1 << 8 | 1 << 6 | 1 << 4 | 0x0F) +#define UDA1380_REG_ANAMIX_DEFAULT_VALUE 0x0000 +#define UDA1380_REG_HEADAMP_DEFAULT_VALUE ( 1 << 9 | 2) + +#define UDA1380_REG_MSTRVOL_DEFAULT_VALUE 0x0000 +#define UDA1380_REG_MIXVOL_DEFAULT_VALUE 0x0000 +#define UDA1380_REG_MODEBBT_DEFAULT_VALUE 0x0000 +#define UDA1380_REG_MSTRMUTE_DEFAULT_VALUE (2 << 8 | 2) +#define UDA1380_REG_MIXSDO_DEFAULT_VALUE 0x0000 + +#define UDA1380_REG_DECVOL_DEFAULT_VALUE 0xE4E4 /* Decrease Volume -28dB */ +#define UDA1380_REG_PGA_DEFAULT_VALUE 0x0000 +#define UDA1380_REG_ADC_DEFAULT_VALUE 0x0001 /* Apply 0bB VGA Gain, enable DC Filter */ +#define UDA1380_REG_AGC_DEFAULT_VALUE 0x0000 + +#define UDA1380_REG_L3_DEFAULT_VALUE 0x0000 + +/* UDA1380 address */ +#define I2CDEV_UDA1380_ADDR (0x34 >> 1) + +/* UDA1380 Register Address */ +typedef enum { + UDA_EVALM_CLK = 0x00, + UDA_BUS_CTRL, + UDA_POWER_CTRL, + UDA_ANALOG_CTRL, + UDA_HPAMP_CTRL, + UDA_MASTER_VOL_CTRL = 0x10, + UDA_MIXER_VOL_CTRL, + UDA_MODE_CTRL, + UDA_MUTE_CTRL, + UDA_MIXER_FILTER_CTRL, + UDA_DEC_VOL_CTRL = 0x20, + UDA_PGA_CTRL, + UDA_ADC_CTRL, + UDA_AGC_CTRL, + UDA_TOTAL_REG +} UDA1380_REG; + +/* Frame buffer address for lcd */ +#define FRAMEBUFFER_ADDR 0x28000000 + +extern const LCD_Config_Type MCB4300_LCD; +#define BOARD_LCD MCB4300_LCD + +/** Audio input select structure */ +typedef enum { + MCB_18XX_AUDIO_MIC_SELECT = 1 << 2 | 1 << 3, + MCB_18XX_AUDIO_LINE_IN_SELECT = 0x00, +} Board_Audio_Input_Sel_Type; + +/** LCD controller definitions */ +#define SSP_ID LPC_SSP0 +#define C_GLCD_H_SIZE 240 +#define C_GLCD_V_SIZE 320 + +/** Private types/definitions for touch screen controller (STMPE811) */ + +#define TSC_I2C_ADDR (0x82 >> 1) /* Touchscreen 7-bit I2C address */ + +/** STMPE811 Register addresses */ +#define SYS_CTRL1 0x03 +#define SYS_CTRL2 0x04 +#define INT_CTRL 0x09 +#define INT_EN 0x0A +#define INT_STA 0x0B +#define GPIO_ALT_FUNCT 0x17 +#define ADC_CTRL1 0x20 +#define ADC_CTRL2 0x21 +#define TSC_CTRL 0x40 +#define TSC_CFG 0x41 +#define FIFO_TH 0x4A +#define FIFO_STA 0x4B +#define FIFO_SIZE 0x4C +#define DATA_X 0x4D +#define DATA_Y 0x4F +#define DATA_Z 0x51 +#define TSC_FRACTION_Z 0x56 +#define TSC_I_DRIVE 0x58 +#define TSC_SHIELD 0x59 +#define DATA_XYZ 0xD7 + +/** + * @brief Sets up board specific ADC interface + * @return Nothing + */ +void Board_ADC_Init(void); + +/** + * @brief Sets up board specific I2C interface + * @param I2Cx : Pointer to I2C interface to initialize + * @return Nothing + */ +void Board_I2C_Init(LPC_I2C_Type *I2Cx); + +/** + * @brief Initializes board specific GPIO Interrupt + * @return Nothing + */ +void Board_GPIO_Int_Init(void); + +/** + * @brief Sets up board specific SDMMC interface + * @return Nothing + */ +void Board_SDMMC_Init(void); + +/** + * @brief Sets up board specific SSP interface + * @param SSPx : Pointer to SSP interface to initialize + * @return Nothing + */ +void Board_SSP_Init(LPC_SSP_Type *SSPx); + +/** + * @brief Returns the MAC address assigned to this board + * @param mcaddr : Pointer to 6-byte character array to populate with MAC address + * @return Nothing + */ +void Board_ENET_GetMacADDR(uint8_t *mcaddr); + +/** + * @brief Initialize pin muxing for a UART + * @param UARTx : Pointer to UART register block for UART pins to init + * @return Nothing + */ +void Board_UART_Init(LPC_USART_Type *UARTx); + +/** + * @brief Initialize the LCD interface + * @return Nothing + */ +void Board_LCD_Init(void); + +/** + * @brief Initializes the STMPE811 touch screen controller + * @return Nothing + */ +void Init_Touch_Controller(void); + +/** + * @brief Get touch screen position + * @param pX : pointer to X position + * @param pY : pointer to Y position + * @return true if touch is detected or false if otherwise + */ +bool GetTouchPos(int16_t *pX, int16_t *pY); + +/** + * @brief Initializes board specific buttons + * @return Nothing + */ +void Board_Buttons_Init (void); + +/** + * @brief Initializes board specific joystick + * @return Nothing + */ +void Board_Joystick_Init (void); + +/** + * @brief Initialize joystick interface on board + * @return joystick status: up, down, left or right + */ +uint8_t Joystick_GetStatus (void); + +/** + * @brief Returns button(s) state on board + * @return Returns BUTTONS_BUTTON1 if button1 is pressed + */ +uint32_t Buttons_GetStatus(void); + +/** + * @brief Sets up board specific I2S interface and UDA1380 + * @param I2Sx : Pointer to I2S interface to initialize + * @param audio_in_sel : audio input selection + * @return Nothing + */ +void Board_Audio_Init(LPC_I2S_Type *I2Sx, Board_Audio_Input_Sel_Type audio_in_sel); + +//FIXME Should we remove this function? +void Serial_CreateStream(void *Stream); + +/** + * @} + */ + +#ifdef __cplusplus +} +#endif + +#endif /* __BOARD_KEIL_MCB_18574357_H_ */ diff --git a/bsp/xplorer4330/libraries/lpc_board/boards_18xx_43xx/keil_mcb_18574357/keil_mcb_1857/sys_config.h b/bsp/xplorer4330/libraries/lpc_board/boards_18xx_43xx/keil_mcb_18574357/keil_mcb_1857/sys_config.h new file mode 100644 index 0000000000..509cc50a48 --- /dev/null +++ b/bsp/xplorer4330/libraries/lpc_board/boards_18xx_43xx/keil_mcb_18574357/keil_mcb_1857/sys_config.h @@ -0,0 +1,58 @@ +/* + * @note + * Copyright(C) NXP Semiconductors, 2012 + * All rights reserved. + * + * @par + * Software that is described herein is for illustrative purposes only + * which provides customers with programming information regarding the + * LPC products. This software is supplied "AS IS" without any warranties of + * any kind, and NXP Semiconductors and its licensor disclaim any and + * all warranties, express or implied, including all implied warranties of + * merchantability, fitness for a particular purpose and non-infringement of + * intellectual property rights. NXP Semiconductors assumes no responsibility + * or liability for the use of the software, conveys no license or rights under any + * patent, copyright, mask work right, or any other intellectual property rights in + * or to any products. NXP Semiconductors reserves the right to make changes + * in the software without notification. NXP Semiconductors also makes no + * representation or warranty that such application will be suitable for the + * specified use without further testing or modification. + * + * @par + * Permission to use, copy, modify, and distribute this software and its + * documentation is hereby granted, under NXP Semiconductors' and its + * licensor's relevant copyrights in the software, without fee, provided that it + * is used in conjunction with NXP Semiconductors microcontrollers. This + * copyright, permission, and disclaimer notice must appear in all copies of + * this code. + */ + +#ifndef __SYS_CONFIG_H_ +#define __SYS_CONFIG_H_ + +#define USE_RMII +#define CHIP_LPC18XX + +/* Enable DEBUG for IO support via the UART */ +#define DEBUG + +/* Enable DEBUG_SEMIHOSTING along with DEBUG to enable IO support + via semihosting */ +// #define DEBUG_SEMIHOSTING + +/* Board UART used for debug output */ +#define DEBUG_UART LPC_USART3 + +/* Crystal frequency into device */ +#define CRYSTAL_MAIN_FREQ_IN 12000000 + +/* Crystal frequency into device for RTC/32K input */ +#define CRYSTAL_32K_FREQ_IN 32768 + +/* Frequency on external clock in pin */ +#define EXTERNAL_CLKIN_FREQ_IN 0 + +/* Default CPU clock frequency */ +#define MAX_CLOCK_FREQ (180000000) + +#endif /* __SYS_CONFIG_H_ */ diff --git a/bsp/xplorer4330/libraries/lpc_board/boards_18xx_43xx/keil_mcb_18574357/keil_mcb_4357/sys_config.h b/bsp/xplorer4330/libraries/lpc_board/boards_18xx_43xx/keil_mcb_18574357/keil_mcb_4357/sys_config.h new file mode 100644 index 0000000000..4f864551ff --- /dev/null +++ b/bsp/xplorer4330/libraries/lpc_board/boards_18xx_43xx/keil_mcb_18574357/keil_mcb_4357/sys_config.h @@ -0,0 +1,58 @@ +/* + * @note + * Copyright(C) NXP Semiconductors, 2012 + * All rights reserved. + * + * @par + * Software that is described herein is for illustrative purposes only + * which provides customers with programming information regarding the + * LPC products. This software is supplied "AS IS" without any warranties of + * any kind, and NXP Semiconductors and its licensor disclaim any and + * all warranties, express or implied, including all implied warranties of + * merchantability, fitness for a particular purpose and non-infringement of + * intellectual property rights. NXP Semiconductors assumes no responsibility + * or liability for the use of the software, conveys no license or rights under any + * patent, copyright, mask work right, or any other intellectual property rights in + * or to any products. NXP Semiconductors reserves the right to make changes + * in the software without notification. NXP Semiconductors also makes no + * representation or warranty that such application will be suitable for the + * specified use without further testing or modification. + * + * @par + * Permission to use, copy, modify, and distribute this software and its + * documentation is hereby granted, under NXP Semiconductors' and its + * licensor's relevant copyrights in the software, without fee, provided that it + * is used in conjunction with NXP Semiconductors microcontrollers. This + * copyright, permission, and disclaimer notice must appear in all copies of + * this code. + */ + +#ifndef __SYS_CONFIG_H_ +#define __SYS_CONFIG_H_ + +#define USE_RMII +#define CHIP_LPC43XX + +/* Enable DEBUG for IO support via the UART */ +#define DEBUG + +/* Enable DEBUG_SEMIHOSTING along with DEBUG to enable IO support + via semihosting */ +// #define DEBUG_SEMIHOSTING' + +/* Board UART used for debug output */ +#define DEBUG_UART LPC_USART3 + +/* Crystal frequency into device */ +#define CRYSTAL_MAIN_FREQ_IN 12000000 + +/* Crystal frequency into device for RTC/32K input */ +#define CRYSTAL_32K_FREQ_IN 32768 + +/* Frequency on external clock in pin */ +#define EXTERNAL_CLKIN_FREQ_IN 0 + +/* Default CPU clock frequency */ +#define MAX_CLOCK_FREQ (204000000) + +#endif /* __SYS_CONFIG_H_ */ diff --git a/bsp/xplorer4330/libraries/lpc_board/boards_18xx_43xx/keil_mcb_18574357/sysinit_keil_mcb_18574357.c b/bsp/xplorer4330/libraries/lpc_board/boards_18xx_43xx/keil_mcb_18574357/sysinit_keil_mcb_18574357.c new file mode 100644 index 0000000000..38bd49e0f6 --- /dev/null +++ b/bsp/xplorer4330/libraries/lpc_board/boards_18xx_43xx/keil_mcb_18574357/sysinit_keil_mcb_18574357.c @@ -0,0 +1,433 @@ +/* + * Copyright(C) NXP Semiconductors, 2012 + * All rights reserved. + * + * Software that is described herein is for illustrative purposes only + * which provides customers with programming information regarding the + * LPC products. This software is supplied "AS IS" without any warranties of + * any kind, and NXP Semiconductors and its licensor disclaim any and + * all warranties, express or implied, including all implied warranties of + * merchantability, fitness for a particular purpose and non-infringement of + * intellectual property rights. NXP Semiconductors assumes no responsibility + * or liability for the use of the software, conveys no license or rights under any + * patent, copyright, mask work right, or any other intellectual property rights in + * or to any products. NXP Semiconductors reserves the right to make changes + * in the software without notification. NXP Semiconductors also makes no + * representation or warranty that such application will be suitable for the + * specified use without further testing or modification. + * + * Permission to use, copy, modify, and distribute this software and its + * documentation is hereby granted, under NXP Semiconductors' and its + * licensor's relevant copyrights in the software, without fee, provided that it + * is used in conjunction with NXP Semiconductors microcontrollers. This + * copyright, permission, and disclaimer notice must appear in all copies of + * this code. + */ + +#include "board.h" + +/** @defgroup BOARD_KEIL_MCB_18574357_SYSINIT LPC1857 and LPC4357 Keil MCB board System Init code + * @ingroup BOARD_KEIL_MCB_18574357 + * The System initialization code is called prior to the application and + * initializes the board for run-time operation. Board initialization + * for the Keil MCB boards includes clock setup, default pin muxing, and + * memory configuration. + * + * With the exception of stack space, no RW memory is used for this call. + * + * LPC1857 and LPC4357 Keil MCB setup
+ * Clocking:
+ * All base clocks enabled by default (Save power by disabling un-needed clocks)
+ * CPU PLL set to maximum clock frequency (as defined by MAX_CLOCK_FREQ value)
+ * SPIFI FLASH clock setup for fastest speed
+ * Pin muxing:
+ * Sets up various pin mux functions for the board (Ethernet, LEDs, etc.)
+ * Sets up the external memory controller signals
+ * Memory:
+ * Sets up DRAM and NOR FLASH. + * @{ + */ + +#ifndef CORE_M0 +/* SCR pin definitions for pin muxing */ +typedef struct { + uint8_t pingrp; /* Pin group */ + uint8_t pinnum; /* Pin number */ + uint8_t pincfg; /* Pin configuration for SCU */ + uint8_t funcnum;/* Function number */ +} PINMUX_GRP_T; + +/* Structure for initial base clock states */ +struct CLK_BASE_STATES { + CGU_BASE_CLK_T clk; /* Base clock */ + CGU_CLKIN_T clkin; /* Base clock source, see UM for allowable souorces per base clock */ + bool autoblock_enab;/* Set to true to enable autoblocking on frequency change */ + bool powerdn; /* Set to true if the base clock is initially powered down */ +}; + +/* Initial base clock states are mostly on */ +STATIC const struct CLK_BASE_STATES InitClkStates[] = { + {CLK_BASE_SAFE, CLKIN_IRC, true, false}, + {CLK_BASE_APB1, CLKIN_MAINPLL, true, false}, + {CLK_BASE_APB3, CLKIN_MAINPLL, true, false}, + {CLK_BASE_USB0, CLKIN_USBPLL, true, false}, +#if defined(CHIP_LPC43XX) + {CLK_BASE_PERIPH, CLKIN_MAINPLL, true, false}, +#endif + {CLK_BASE_USB1, CLKIN_USBPLL, true, false}, +#if defined(CHIP_LPC43XX) + {CLK_BASE_SPI, CLKIN_MAINPLL, true, false}, +#endif + {CLK_BASE_PHY_TX, CLKIN_ENET_TX, true, false}, +#if defined(USE_RMII) + {CLK_BASE_PHY_RX, CLKIN_ENET_TX, true, false}, +#else + {CLK_BASE_PHY_RX, CLKIN_ENET_RX, true, false}, +#endif + {CLK_BASE_LCD, CLKIN_MAINPLL, true, true}, +#if defined(CHIP_LPC43XX) + {CLK_BASE_VADC, CLKIN_MAINPLL, true, true}, +#endif + {CLK_BASE_SDIO, CLKIN_MAINPLL, true, false}, + {CLK_BASE_SSP0, CLKIN_MAINPLL, true, false}, + {CLK_BASE_SSP1, CLKIN_MAINPLL, true, false}, + {CLK_BASE_UART0, CLKIN_MAINPLL, true, false}, + {CLK_BASE_UART1, CLKIN_MAINPLL, true, false}, + {CLK_BASE_UART2, CLKIN_MAINPLL, true, false}, + {CLK_BASE_UART3, CLKIN_MAINPLL, true, false}, + {CLK_BASE_OUT, CLKINPUT_PD, true, false}, + {CLK_BASE_APLL, CLKINPUT_PD, true, false}, + {CLK_BASE_CGU_OUT0, CLKINPUT_PD, true, false}, + {CLK_BASE_CGU_OUT1, CLKINPUT_PD, true, false} +}; + +/* SPIFI high speed pin mode setup */ +STATIC const PINMUX_GRP_T spifipinmuxing[] = { + {0x3, 3, (MD_PLN_FAST), FUNC3}, + {0x3, 4, (MD_PLN_FAST), FUNC3}, + {0x3, 5, (MD_PLN_FAST), FUNC3}, + {0x3, 6, (MD_PLN_FAST), FUNC3}, + {0x3, 7, (MD_PLN_FAST), FUNC3}, + {0x3, 8, (MD_PLN_FAST), FUNC3} +}; + +/* Setup system clocking */ +STATIC void SystemSetupClocking(void) +{ + int i; + + /* Setup FLASH acceleration to target clock rate prior to clock switch */ + Chip_CREG_SetFlashAcceleration(MAX_CLOCK_FREQ); + + /* Switch main system clocking to crystal */ + Chip_Clock_EnableCrystal(); + Chip_Clock_SetBaseClock(CLK_BASE_MX, CLKIN_CRYSTAL, true, false); + + /* Setup PLL for 100MHz and switch main system clocking */ + Chip_Clock_SetupMainPLLHz(CLKIN_CRYSTAL, CRYSTAL_MAIN_FREQ_IN, 100 * 1000000, 100 * 1000000); + Chip_Clock_SetBaseClock(CLK_BASE_MX, CLKIN_MAINPLL, true, false); + + /* Setup PLL for maximum clock */ + Chip_Clock_SetupMainPLLHz(CLKIN_CRYSTAL, CRYSTAL_MAIN_FREQ_IN, MAX_CLOCK_FREQ, MAX_CLOCK_FREQ); + + /* Setup system base clocks and initial states. This won't enable and + disable individual clocks, but sets up the base clock sources for + each individual peripheral clock. */ + for (i = 0; i < (sizeof(InitClkStates) / sizeof(InitClkStates[0])); i++) { + Chip_Clock_SetBaseClock(InitClkStates[i].clk, InitClkStates[i].clkin, + InitClkStates[i].autoblock_enab, InitClkStates[i].powerdn); + } + + /* Reset and enable 32Khz oscillator */ + LPC_CREG->CREG0 &= ~((1 << 3) | (1 << 2)); + LPC_CREG->CREG0 |= (1 << 1) | (1 << 0); + + /* SPIFI pin setup is done prior to setting up system clocking */ + for (i = 0; i < (sizeof(spifipinmuxing) / sizeof(spifipinmuxing[0])); i++) { + Chip_SCU_PinMux(spifipinmuxing[i].pingrp, spifipinmuxing[i].pinnum, + spifipinmuxing[i].pincfg, spifipinmuxing[i].funcnum); + } + + /* Setup a divider E for main PLL clock switch SPIFI clock to that divider. + Divide rate is based on CPU speed and speed of SPI FLASH part. */ +#if (MAX_CLOCK_FREQ > 180000000) + Chip_Clock_SetDivider(CLK_IDIV_E, CLKIN_MAINPLL, 5); +#else + Chip_Clock_SetDivider(CLK_IDIV_E, CLKIN_MAINPLL, 4); +#endif + Chip_Clock_SetBaseClock(CLK_BASE_SPIFI, CLKIN_IDIVE, true, false); +} + +STATIC const PINMUX_GRP_T pinmuxing[] = { + /* RMII pin group */ + {0x1, 19, (MD_EHS | MD_PLN | MD_EZI | MD_ZI), FUNC0}, + {0x0, 1, (MD_EHS | MD_PLN | MD_ZI), FUNC6}, + {0x1, 18, (MD_EHS | MD_PLN | MD_ZI), FUNC3}, + {0x1, 20, (MD_EHS | MD_PLN | MD_ZI), FUNC3}, + {0x1, 17, (MD_EHS | MD_PLN | MD_EZI | MD_ZI), FUNC3}, + {0xC, 1, (MD_EHS | MD_PLN | MD_ZI), FUNC3}, + {0x1, 16, (MD_EHS | MD_PLN | MD_EZI | MD_ZI), FUNC7}, + {0x1, 15, (MD_EHS | MD_PLN | MD_EZI | MD_ZI), FUNC3}, + {0x0, 0, (MD_EHS | MD_PLN | MD_EZI | MD_ZI), FUNC2}, + /* External data lines D0 .. D15 */ + {0x1, 7, (MD_PLN | MD_EZI | MD_ZI | MD_EHS), FUNC3}, + {0x1, 8, (MD_PLN | MD_EZI | MD_ZI | MD_EHS), FUNC3}, + {0x1, 9, (MD_PLN | MD_EZI | MD_ZI | MD_EHS), FUNC3}, + {0x1, 10, (MD_PLN | MD_EZI | MD_ZI | MD_EHS), FUNC3}, + {0x1, 11, (MD_PLN | MD_EZI | MD_ZI | MD_EHS), FUNC3}, + {0x1, 12, (MD_PLN | MD_EZI | MD_ZI | MD_EHS), FUNC3}, + {0x1, 13, (MD_PLN | MD_EZI | MD_ZI | MD_EHS), FUNC3}, + {0x1, 14, (MD_PLN | MD_EZI | MD_ZI | MD_EHS), FUNC3}, + {0x5, 4, (MD_PLN | MD_EZI | MD_ZI | MD_EHS), FUNC2}, + {0x5, 5, (MD_PLN | MD_EZI | MD_ZI | MD_EHS), FUNC2}, + {0x5, 6, (MD_PLN | MD_EZI | MD_ZI | MD_EHS), FUNC2}, + {0x5, 7, (MD_PLN | MD_EZI | MD_ZI | MD_EHS), FUNC2}, + {0x5, 0, (MD_PLN | MD_EZI | MD_ZI | MD_EHS), FUNC2}, + {0x5, 1, (MD_PLN | MD_EZI | MD_ZI | MD_EHS), FUNC2}, + {0x5, 2, (MD_PLN | MD_EZI | MD_ZI | MD_EHS), FUNC2}, + {0x5, 3, (MD_PLN | MD_EZI | MD_ZI | MD_EHS), FUNC2}, + {0xD, 2, (MD_PLN | MD_EZI | MD_ZI | MD_EHS), FUNC2}, + {0xD, 3, (MD_PLN | MD_EZI | MD_ZI | MD_EHS), FUNC2}, + {0xD, 4, (MD_PLN | MD_EZI | MD_ZI | MD_EHS), FUNC2}, + {0xD, 5, (MD_PLN | MD_EZI | MD_ZI | MD_EHS), FUNC2}, + {0xD, 6, (MD_PLN | MD_EZI | MD_ZI | MD_EHS), FUNC2}, + {0xD, 7, (MD_PLN | MD_EZI | MD_ZI | MD_EHS), FUNC2}, + {0xD, 8, (MD_PLN | MD_EZI | MD_ZI | MD_EHS), FUNC2}, + {0xD, 9, (MD_PLN | MD_EZI | MD_ZI | MD_EHS), FUNC2}, + {0xE, 5, (MD_PLN | MD_EZI | MD_ZI | MD_EHS), FUNC3}, + {0xE, 6, (MD_PLN | MD_EZI | MD_ZI | MD_EHS), FUNC3}, + {0xE, 7, (MD_PLN | MD_EZI | MD_ZI | MD_EHS), FUNC3}, + {0xE, 8, (MD_PLN | MD_EZI | MD_ZI | MD_EHS), FUNC3}, + {0xE, 9, (MD_PLN | MD_EZI | MD_ZI | MD_EHS), FUNC3}, + {0xE, 10, (MD_PLN | MD_EZI | MD_ZI | MD_EHS), FUNC3}, + {0xE, 11, (MD_PLN | MD_EZI | MD_ZI | MD_EHS), FUNC3}, + {0xE, 12, (MD_PLN | MD_EZI | MD_ZI | MD_EHS), FUNC3}, + /* Address lines A0 .. A23 */ + {0x2, 9, (MD_PLN | MD_EZI | MD_ZI | MD_EHS), FUNC3}, + {0x2, 10, (MD_PLN | MD_EZI | MD_ZI | MD_EHS), FUNC3}, + {0x2, 11, (MD_PLN | MD_EZI | MD_ZI | MD_EHS), FUNC3}, + {0x2, 12, (MD_PLN | MD_EZI | MD_ZI | MD_EHS), FUNC3}, + {0x2, 13, (MD_PLN | MD_EZI | MD_ZI | MD_EHS), FUNC3}, + {0x1, 0, (MD_PLN | MD_EZI | MD_ZI | MD_EHS), FUNC2}, + {0x1, 1, (MD_PLN | MD_EZI | MD_ZI | MD_EHS), FUNC2}, + {0x1, 2, (MD_PLN | MD_EZI | MD_ZI | MD_EHS), FUNC2}, + {0x2, 8, (MD_PLN | MD_EZI | MD_ZI | MD_EHS), FUNC3}, + {0x2, 7, (MD_PLN | MD_EZI | MD_ZI | MD_EHS), FUNC3}, + {0x2, 6, (MD_PLN | MD_EZI | MD_ZI | MD_EHS), FUNC2}, + {0x2, 2, (MD_PLN | MD_EZI | MD_ZI | MD_EHS), FUNC2}, + {0x2, 1, (MD_PLN | MD_EZI | MD_ZI | MD_EHS), FUNC2}, + {0x2, 0, (MD_PLN | MD_EZI | MD_ZI | MD_EHS), FUNC2}, + {0x6, 8, (MD_PLN | MD_EZI | MD_ZI | MD_EHS), FUNC1}, + {0x6, 7, (MD_PLN | MD_EZI | MD_ZI | MD_EHS), FUNC1}, + {0xD, 16, (MD_PLN | MD_EZI | MD_ZI | MD_EHS), FUNC2}, + {0xD, 15, (MD_PLN | MD_EZI | MD_ZI | MD_EHS), FUNC2}, + {0xE, 0, (MD_PLN | MD_EZI | MD_ZI | MD_EHS), FUNC3}, + {0xE, 1, (MD_PLN | MD_EZI | MD_ZI | MD_EHS), FUNC3}, + {0xE, 2, (MD_PLN | MD_EZI | MD_ZI | MD_EHS), FUNC3}, + {0xE, 3, (MD_PLN | MD_EZI | MD_ZI | MD_EHS), FUNC3}, + {0xE, 4, (MD_PLN | MD_EZI | MD_ZI | MD_EHS), FUNC3}, + {0xA, 4, (MD_PLN | MD_EZI | MD_ZI | MD_EHS), FUNC3}, + /* EMC control signals */ + {0x1, 4, (MD_PLN | MD_EZI | MD_ZI | MD_EHS), FUNC3}, + {0x6, 6, (MD_PLN | MD_EZI | MD_ZI | MD_EHS), FUNC1}, + {0xD, 13, (MD_PLN | MD_EZI | MD_ZI | MD_EHS), FUNC2}, + {0xD, 10, (MD_PLN | MD_EZI | MD_ZI | MD_EHS), FUNC2}, + {0x6, 9, (MD_PLN | MD_EZI | MD_ZI | MD_EHS), FUNC3}, + {0x1, 6, (MD_PLN | MD_EZI | MD_ZI | MD_EHS), FUNC3}, + {0x6, 4, (MD_PLN | MD_EZI | MD_ZI | MD_EHS), FUNC3}, + {0x6, 5, (MD_PLN | MD_EZI | MD_ZI | MD_EHS), FUNC3}, + {PINMUX_CLK, 0, (MD_PLN | MD_EZI | MD_ZI | MD_EHS), FUNC0}, + {PINMUX_CLK, 1, (MD_PLN | MD_EZI | MD_ZI | MD_EHS), FUNC0}, + {PINMUX_CLK, 2, (MD_PLN | MD_EZI | MD_ZI | MD_EHS), FUNC0}, + {PINMUX_CLK, 3, (MD_PLN | MD_EZI | MD_ZI | MD_EHS), FUNC0}, + {0x6, 11, (MD_PLN | MD_EZI | MD_ZI | MD_EHS), FUNC3}, + {0x6, 12, (MD_PLN | MD_EZI | MD_ZI | MD_EHS), FUNC3}, + {0x6, 10, (MD_PLN | MD_EZI | MD_ZI | MD_EHS), FUNC3}, + {0xD, 0, (MD_PLN | MD_EZI | MD_ZI | MD_EHS), FUNC2}, + {0xE, 13, (MD_PLN | MD_EZI | MD_ZI | MD_EHS), FUNC3}, + {0x1, 3, MD_PLN_FAST, FUNC3}, + {0x1, 4, MD_PLN_FAST, FUNC3}, + {0x6, 6, MD_PLN_FAST, FUNC1}, + {0x1, 5, MD_PLN_FAST, FUNC3}, + {0x1, 6, MD_PLN_FAST, FUNC3}, + /* Board LEDs */ + {0xD, 10, (MD_PLN), FUNC4}, + {0xD, 11, (MD_PLN), FUNC4}, + {0xD, 12, (MD_PLN), FUNC4}, + {0xD, 13, (MD_PLN), FUNC4}, + {0xD, 14, (MD_PLN), FUNC4}, + {0x9, 0, (MD_PLN), FUNC0}, + {0x9, 1, (MD_PLN), FUNC0}, + {0x9, 2, (MD_PLN), FUNC0}, + /* SSP0 */ + {0xF, 0, (MD_PLN_FAST), FUNC0}, + {0xF, 1, (MD_PLN_FAST), FUNC4}, + {0xF, 2, (MD_PLN_FAST), FUNC2}, + {0xF, 3, (MD_PLN_FAST), FUNC2}, + /* LCD interface, 16bpp */ + {0x4, 1, MD_PUP, FUNC5}, + {0x4, 2, MD_PUP, FUNC2}, + {0x4, 5, MD_PUP, FUNC2}, + {0x4, 6, MD_PUP, FUNC2}, + {0x4, 7, MD_PUP, FUNC0}, + {0x4, 9, MD_PUP, FUNC2}, + {0x4, 10, MD_PUP, FUNC2}, + {0x7, 0, MD_PUP, FUNC0}, + {0x7, 6, MD_PUP, FUNC3}, + {0x8, 3, MD_PUP, FUNC3}, + {0x8, 4, MD_PUP, FUNC3}, + {0x8, 5, MD_PUP, FUNC3}, + {0x8, 6, MD_PUP, FUNC3}, + {0x8, 7, MD_PUP, FUNC3}, + {0xB, 0, MD_PUP, FUNC2}, + {0xB, 1, MD_PUP, FUNC2}, + {0xB, 2, MD_PUP, FUNC2}, + {0xB, 3, MD_PUP, FUNC2}, + {0xB, 4, MD_PUP, FUNC2}, + {0xB, 5, MD_PUP, FUNC2}, + {0xB, 6, MD_PUP, FUNC2}, + /* I2S */ + {0x3, 0, MD_PLN_FAST, FUNC2}, + {0x6, 0, MD_PLN_FAST, FUNC4}, + {0x7, 2, MD_PLN_FAST, FUNC2}, + {0x6, 2, MD_PLN_FAST, FUNC3}, + {0x7, 1, MD_PLN_FAST, FUNC2}, + {0x6, 1, MD_PLN_FAST, FUNC3}, +}; + +/* Sets up system pin muxing */ +STATIC void SystemSetupMuxing(void) +{ + int i; + + /* Setup system level pin muxing */ + for (i = 0; i < (sizeof(pinmuxing) / sizeof(pinmuxing[0])); i++) { + Chip_SCU_PinMux(pinmuxing[i].pingrp, pinmuxing[i].pinnum, + pinmuxing[i].pincfg, pinmuxing[i].funcnum); + } +} + +/* EMC clock delay */ +#define CLK0_DELAY 7 + +/* Keil SDRAM timing and chip Config */ +STATIC const IP_EMC_DYN_CONFIG_Type MT48LC4M32_config = { + EMC_NANOSECOND(64000000 / 4096), /* Row refresh time */ + 0x01, /* Command Delayed */ + EMC_NANOSECOND(18), + EMC_NANOSECOND(42), + EMC_NANOSECOND(70), + EMC_CLOCK(0x01), + EMC_CLOCK(0x05), + EMC_NANOSECOND(12), + EMC_NANOSECOND(60), + EMC_NANOSECOND(60), + EMC_NANOSECOND(70), + EMC_NANOSECOND(12), + EMC_CLOCK(0x02), + { + { + EMC_ADDRESS_DYCS0, /* Keil Board uses DYCS0 for SDRAM */ + 3, /* RAS */ + + EMC_DYN_MODE_WBMODE_PROGRAMMED | + EMC_DYN_MODE_OPMODE_STANDARD | + EMC_DYN_MODE_CAS_3 | + EMC_DYN_MODE_BURST_TYPE_SEQUENTIAL | + EMC_DYN_MODE_BURST_LEN_4, + + EMC_DYN_CONFIG_DATA_BUS_32 | + EMC_DYN_CONFIG_LPSDRAM | + EMC_DYN_CONFIG_4Mx32_4BANKS_12ROWS_8COLS | + EMC_DYN_CONFIG_MD_SDRAM + }, + {0, 0, 0, 0}, + {0, 0, 0, 0}, + {0, 0, 0, 0} + } +}; + +/* Keil NorFlash timing and chip Config */ +/* FIXME : Keil NOR FLASH not yet tested */ +STATIC const IP_EMC_STATIC_CONFIG_Type S29GL64N90_config = { + 0, + EMC_STATIC_CONFIG_MEM_WIDTH_32 | + EMC_STATIC_CONFIG_CS_POL_ACTIVE_LOW | + EMC_STATIC_CONFIG_BLS_HIGH /* | + EMC_CONFIG_BUFFER_ENABLE*/, + + EMC_NANOSECOND(0), + EMC_NANOSECOND(65), + EMC_NANOSECOND(90), + EMC_NANOSECOND(90), + EMC_NANOSECOND(35), + EMC_CLOCK(4) +}; + +/* Setup external memories */ +STATIC void SystemSetupMemory(void) +{ + /* Setup EMC Delays */ + /* Move all clock delays together */ + LPC_SCU->EMCDELAYCLK = ((CLK0_DELAY) | (CLK0_DELAY << 4) | (CLK0_DELAY << 8) | (CLK0_DELAY << 12)); + + /* Setup EMC Clock Divider for divide by 2 */ + Chip_Clock_EnableOpts(CLK_MX_EMC_DIV, true, true, 2); + LPC_CREG->CREG6 |= (1 << 16); + Chip_Clock_Enable(CLK_MX_EMC); + + /* Init EMC Controller -Enable-LE mode- clock ratio 1:1 */ + Chip_EMC_Init(1, 0, 0); + /* Init EMC Dynamic Controller */ + Chip_EMC_Dynamic_Init((IP_EMC_DYN_CONFIG_Type *) &MT48LC4M32_config); + /* Init EMC Static Controller CS0 */ + Chip_EMC_Static_Init((IP_EMC_STATIC_CONFIG_Type *) &S29GL64N90_config); + + /* Enable Buffer for External Flash */ + LPC_EMC->STATICCONFIG0 |= 1 << 19; +} + +#endif + +/** + * @brief Setup the system + * SystemInit() is called prior to the application and sets up system + * clocking, memory, and any resources needed prior to the application + * starting. + * @return none + */ +void SystemInit(void) +{ +#if defined(CORE_M3) || defined(CORE_M4) + unsigned int *pSCB_VTOR = (unsigned int *) 0xE000ED08; + +#if defined(__IAR_SYSTEMS_ICC__) + extern void *__vector_table; + + *pSCB_VTOR = (unsigned int) &__vector_table; +#elif defined(__CODE_RED) + extern void *g_pfnVectors; + + *pSCB_VTOR = (unsigned int) &g_pfnVectors; +#elif defined(__ARMCC_VERSION) + extern void *__Vectors; + + *pSCB_VTOR = (unsigned int) &__Vectors; +#endif + +#if defined(__FPU_PRESENT) && __FPU_PRESENT == 1 + fpuInit(); +#endif + + /* Setup system clocking and memory. This is done early to allow the + application and tools to clear memory and use scatter loading to + external memory. */ + SystemSetupClocking(); + SystemSetupMuxing(); + SystemSetupMemory(); +#endif +} + +/** + * @} + */ diff --git a/bsp/xplorer4330/libraries/lpc_board/boards_18xx_43xx/ngx_xplorer_18304330/board.h b/bsp/xplorer4330/libraries/lpc_board/boards_18xx_43xx/ngx_xplorer_18304330/board.h new file mode 100644 index 0000000000..81b779262c --- /dev/null +++ b/bsp/xplorer4330/libraries/lpc_board/boards_18xx_43xx/ngx_xplorer_18304330/board.h @@ -0,0 +1,37 @@ +/* + * @brief NGX Xplorer 1830/4330 board file + * + * @note + * Copyright(C) NXP Semiconductors, 2012 + * All rights reserved. + * + * @par + * Software that is described herein is for illustrative purposes only + * which provides customers with programming information regarding the + * LPC products. This software is supplied "AS IS" without any warranties of + * any kind, and NXP Semiconductors and its licensor disclaim any and + * all warranties, express or implied, including all implied warranties of + * merchantability, fitness for a particular purpose and non-infringement of + * intellectual property rights. NXP Semiconductors assumes no responsibility + * or liability for the use of the software, conveys no license or rights under any + * patent, copyright, mask work right, or any other intellectual property rights in + * or to any products. NXP Semiconductors reserves the right to make changes + * in the software without notification. NXP Semiconductors also makes no + * representation or warranty that such application will be suitable for the + * specified use without further testing or modification. + * + * @par + * Permission to use, copy, modify, and distribute this software and its + * documentation is hereby granted, under NXP Semiconductors' and its + * licensor's relevant copyrights in the software, without fee, provided that it + * is used in conjunction with NXP Semiconductors microcontrollers. This + * copyright, permission, and disclaimer notice must appear in all copies of + * this code. + */ + +#ifndef __BOARD_H_ +#define __BOARD_H_ + +#include "board_ngx_xplorer_18304330.h" + +#endif /* __BOARD_H_ */ diff --git a/bsp/xplorer4330/libraries/lpc_board/boards_18xx_43xx/ngx_xplorer_18304330/board_ngx_xplorer_18304330.c b/bsp/xplorer4330/libraries/lpc_board/boards_18xx_43xx/ngx_xplorer_18304330/board_ngx_xplorer_18304330.c new file mode 100644 index 0000000000..b63c77311d --- /dev/null +++ b/bsp/xplorer4330/libraries/lpc_board/boards_18xx_43xx/ngx_xplorer_18304330/board_ngx_xplorer_18304330.c @@ -0,0 +1,385 @@ +/* + * Copyright(C) NXP Semiconductors, 2012 + * All rights reserved. + * + * Software that is described herein is for illustrative purposes only + * which provides customers with programming information regarding the + * LPC products. This software is supplied "AS IS" without any warranties of + * any kind, and NXP Semiconductors and its licensor disclaim any and + * all warranties, express or implied, including all implied warranties of + * merchantability, fitness for a particular purpose and non-infringement of + * intellectual property rights. NXP Semiconductors assumes no responsibility + * or liability for the use of the software, conveys no license or rights under any + * patent, copyright, mask work right, or any other intellectual property rights in + * or to any products. NXP Semiconductors reserves the right to make changes + * in the software without notification. NXP Semiconductors also makes no + * representation or warranty that such application will be suitable for the + * specified use without further testing or modification. + * + * Permission to use, copy, modify, and distribute this software and its + * documentation is hereby granted, under NXP Semiconductors' and its + * licensor's relevant copyrights in the software, without fee, provided that it + * is used in conjunction with NXP Semiconductors microcontrollers. This + * copyright, permission, and disclaimer notice must appear in all copies of + * this code. + */ + +#include "board.h" +#include "string.h" + +#include "lpc_phy_smsc87x0.c" +#include "retarget.c" + +/** @ingroup BOARD_NGX_XPLORER_18304330 + * @{ + */ + +void Board_UART_Init(LPC_USART_Type *UARTx) +{ + if (UARTx == LPC_USART0) { + Chip_SCU_PinMux(0x6, 4, MD_PDN, FUNC2); /* P6.5 : UART0_TXD */ + Chip_SCU_PinMux(0x6, 5, MD_PLN | MD_EZI | MD_ZI, FUNC2);/* P6.4 : UART0_RXD */ + } + else if (UARTx == LPC_UART1) { + Chip_SCU_PinMux(0x1, 13, MD_PDN, FUNC2); /* P1.13 : UART1_TXD */ + Chip_SCU_PinMux(0x1, 14, MD_PLN | MD_EZI | MD_ZI, FUNC2);/* P1.14 : UART1_RX */ + } +} + +/* Initialize debug output via UART for board */ +void Board_Debug_Init(void) +{ +#if defined(DEBUG_UART) + Board_UART_Init(DEBUG_UART); + + Chip_UART_Init(DEBUG_UART); + Chip_UART_SetBaud(DEBUG_UART, 115200); + Chip_UART_ConfigData(DEBUG_UART, UART_DATABIT_8, UART_PARITY_NONE, UART_STOPBIT_1); + + /* Enable UART Transmit */ + Chip_UART_TxCmd(DEBUG_UART, ENABLE); +#endif +} + +/* Sends a character on the UART */ +void Board_UARTPutChar(char ch) +{ +#if defined(DEBUG_UART) + while (Chip_UART_SendByte(DEBUG_UART, (uint8_t) ch) == ERROR) {} +#endif +} + +/* Gets a character from the UART, returns EOF if no character is ready */ +int Board_UARTGetChar(void) +{ +#if defined(DEBUG_UART) + uint8_t data; + + if (Chip_UART_ReceiveByte(DEBUG_UART, &data) == SUCCESS) { + return (int) data; + } +#endif + return EOF; +} + +/* Outputs a string on the debug UART */ +void Board_UARTPutSTR(char *str) +{ +#if defined(DEBUG_UART) + while (*str != '\0') { + Board_UARTPutChar(*str++); + } +#endif +} + +void Board_LED_Init() +{ + /* P2.12 : LED D2 as output */ + Chip_GPIO_WriteDirBit(1, 12, true); + + /* P2.11 : LED D3 as output */ + Chip_GPIO_WriteDirBit(1, 11, true); + + /* Set initial states to off (true to disable) */ + Chip_GPIO_WritePortBit(1, 12, (bool) true); + Chip_GPIO_WritePortBit(1, 11, (bool) true); +} + +void Board_LED_Set(uint8_t LEDNumber, bool On) +{ + if (LEDNumber == 0) { + Chip_GPIO_WritePortBit(1, 12, (bool) !On); + } + else if (LEDNumber == 1) { + Chip_GPIO_WritePortBit(1, 11, (bool) !On); + } +} + +bool Board_LED_Test(uint8_t LEDNumber) +{ + if (LEDNumber == 0) { + return (bool) !Chip_GPIO_ReadPortBit(1, 12); + } + else if (LEDNumber == 1) { + return (bool) !Chip_GPIO_ReadPortBit(1, 11); + } + + return false; +} + +void Board_Buttons_Init(void) // FIXME not functional ATM +{ + Chip_SCU_PinMux(0x2, 7, MD_PUP | MD_EZI | MD_ZI, FUNC0); // P2_7 as GPIO0[7] + Chip_GPIO_WriteDirBit(BUTTONS_BUTTON1_GPIO_PORT_NUM, (1 << BUTTONS_BUTTON1_GPIO_BIT_NUM), false); // input +} + +uint32_t Buttons_GetStatus(void) +{ + uint8_t ret = NO_BUTTON_PRESSED; + if (Chip_GPIO_ReadPortBit(BUTTONS_BUTTON1_GPIO_PORT_NUM, BUTTONS_BUTTON1_GPIO_BIT_NUM) == 0) { + ret |= BUTTONS_BUTTON1; + } + return ret; +} + +void Board_Joystick_Init(void) +{} + +uint8_t Joystick_GetStatus(void) +{ + return NO_BUTTON_PRESSED; +} + +/*!< System Clock Frequency (Core Clock)*/ +uint32_t SystemCoreClock; + +/* Update system core clock rate, should be called if the system has + a clock rate change */ +void SystemCoreClockUpdate(void) +{ + /* CPU core speed */ + SystemCoreClock = Chip_Clock_GetRate(CLK_MX_MXCORE); +} + +/* Returns the MAC address assigned to this board */ +void Board_ENET_GetMacADDR(uint8_t *mcaddr) +{ + uint8_t boardmac[] = {0x00, 0x60, 0x37, 0x12, 0x34, 0x56}; + + memcpy(mcaddr, boardmac, 6); +} + +/* Set up and initialize all required blocks and functions related to the + board hardware */ +void Board_Init(void) +{ + /* Sets up DEBUG UART */ + DEBUGINIT(); + + /* Updates SystemCoreClock global var with current clock speed */ + SystemCoreClockUpdate(); + + /* Initializes GPIO */ + Chip_GPIO_Init(); + + /* Setup GPIOs for USB demos */ + Chip_SCU_PinMux(0x2, 6, (MD_PUP | MD_EZI), FUNC4); /* P2_6 USB1_PWR_EN, USB1 VBus function */ + Chip_SCU_PinMux(0x2, 5, (MD_PLN | MD_EZI | MD_ZI), FUNC2); /* P2_5 USB1_VBUS, MUST CONFIGURE THIS SIGNAL FOR USB1 NORMAL OPERATION */ + Chip_SCU_PinMux(0x1, 7, (MD_PUP | MD_EZI), FUNC4); /* P1_7 USB0_PWR_EN, USB0 VBus function Xplorer */ + Chip_GPIO_WriteDirBit(5, 6, true); /* GPIO5[6] = USB1_PWR_EN */ + Chip_GPIO_WritePortBit(5, 6, true); /* GPIO5[6] output high */ +} + +void Board_I2C_Init(LPC_I2C_Type *I2Cx) +{ + if (I2Cx == LPC_I2C1) { + /* Configure pin function for I2C1*/ + Chip_SCU_PinMux(0x2, 3, MD_ZI | MD_EZI, FUNC1); /* P2.3 : I2C1_SDA */ + Chip_SCU_PinMux(0x2, 4, MD_ZI | MD_EZI, FUNC1); /* P2.4 : I2C1_SCL */ + } +} + +void GPIO0_IRQHandler(void) +{ + static bool On; + + if (Chip_GPIO_IntGetStatus(0, 0, 0)) { + Chip_GPIO_IntClear(0, 0); + On = (bool) !On; + Board_LED_Set(1, On); + } +} + +void Board_GPIO_Int_Init() +{ + Chip_SCU_PinMux(0xF, 9, (MD_PLN | MD_EZI | MD_ZI), FUNC0); /* PF.9 : POTI button */ + Chip_GPIO_WriteDirBit(7, 23, false); /* PF.9 -> GPIO7[23] : input */ + Chip_SCU_GPIOIntPinSel(0, 7, 23); + Chip_GPIO_IntCmd(0, 0, IP_GPIOPININT_FALLING_EDGE); /* Configure GPIO0[7] to interrupt pin (SW2 switch) */ + + NVIC_EnableIRQ(PIN_INT0_IRQn); /* enable GPIO interrupt 0 */ +} + +void Board_SDMMC_Init(void) +{ + Chip_SCU_PinMux(0x1, 9, MD_PLN_FAST, FUNC7); /* P1.9 connected to SDIO_D0 */ + Chip_SCU_PinMux(0x1, 10, MD_PLN_FAST, FUNC7); /* P1.10 connected to SDIO_D1 */ + Chip_SCU_PinMux(0x1, 11, MD_PLN_FAST, FUNC7); /* P1.11 connected to SDIO_D2 */ + Chip_SCU_PinMux(0x1, 12, MD_PLN_FAST, FUNC7); /* P1.12 connected to SDIO_D3 */ + + Chip_SCU_PinMux(PINMUX_CLK, 2, MD_PLN | MD_EZI, FUNC4); /* CLK2 connected to SDIO_CLK */ + Chip_SCU_PinMux(0x1, 6, MD_PLN_FAST, FUNC7); /* P1.6 connected to SDIO_CMD */ +} + +void Board_SSP_Init(LPC_SSP_Type *SSPx) +{ + if (SSPx == LPC_SSP1) { + /* Set up clock and power for SSP1 module */ + /* Configure SSP1 pins*/ + /* SCLK comes out pin CLK0 */ + Chip_SCU_PinMux(PINMUX_CLK, 0, MD_PLN_FAST, FUNC6); /* CLK0 connected to CLK func6=SSP1 CLK1 */ + Chip_SCU_PinMux(0x1, 5, MD_PLN_FAST, FUNC5); /* P1.5 connected to nCS func5=SSP1 SSEL1 */ + Chip_SCU_PinMux(0x1, 3, MD_PLN | MD_EZI | MD_ZI, FUNC5);/* P1.3 connected to SO func5=SSP1 MISO1 */ + Chip_SCU_PinMux(0x1, 4, MD_PLN | MD_EZI | MD_ZI, FUNC5);/* P1.4 connected to nSI func5=SSP1 MOSI1 */ + Chip_Clock_EnableOpts(CLK_MX_SSP1, true, true, 1); + } + else { + return; + } +} + +/* System Register Data Set */ +uint16_t UDA_sys_regs_dat[] = { + UDA1380_REG_EVALCLK_DEFAULT_VALUE, + UDA1380_REG_I2S_DEFAULT_VALUE, + UDA1380_REG_PWRCTRL_DEFAULT_VALUE, + UDA1380_REG_ANAMIX_DEFAULT_VALUE, + UDA1380_REG_HEADAMP_DEFAULT_VALUE +}; + +/* System Register Data Set */ +uint16_t UDA_interfil_regs_dat[] = { + UDA1380_REG_MSTRVOL_DEFAULT_VALUE, + UDA1380_REG_MIXVOL_DEFAULT_VALUE, + UDA1380_REG_MODEBBT_DEFAULT_VALUE, + UDA1380_REG_MSTRMUTE_DEFAULT_VALUE, + UDA1380_REG_MIXSDO_DEFAULT_VALUE +}; +/* decimator Register Data Set */ +uint16_t UDA_decimator_regs_dat[] = { + UDA1380_REG_DECVOL_DEFAULT_VALUE, + UDA1380_REG_PGA_DEFAULT_VALUE, + UDA1380_REG_ADC_DEFAULT_VALUE, + UDA1380_REG_AGC_DEFAULT_VALUE +}; +static void delay(uint32_t i) { + while (i--) {} +} + +static void UDA_Reg_write(UDA1380_REG reg, unsigned short value, I2C_M_SETUP_Type *I2C_Config) { + + I2C_Config->tx_data[0] = reg; + I2C_Config->tx_data[1] = value >> 8; + I2C_Config->tx_data[2] = value & 0xFF; + Chip_I2C_MasterTransmitData(LPC_I2C0, I2C_Config, I2C_TRANSFER_POLLING); + delay(10000); +} + +static uint16_t UDA_Reg_read(UDA1380_REG reg) { + uint8_t rx_data[2]; + Chip_I2C_MasterReadReg(LPC_I2C0, I2CDEV_UDA1380_ADDR, reg, rx_data, 2); + return rx_data[0] << 8 | rx_data[1]; +} + +static Status UDA1380_init(I2C_M_SETUP_Type *I2C_Config, Board_Audio_Input_Sel_Type audio_in_sel) +{ + uint16_t temp; + uint8_t i; + /* Reset UDA1380 on board NGX Xplorer */ + Chip_SCU_PinMux(0x2, 10, MD_PUP, FUNC0); + Chip_GPIO_WriteDirBit(0, 14, true); + Chip_GPIO_WritePortBit(0, 14, true); + // delay 1us + delay(100000); + Chip_GPIO_WritePortBit(0, 14, false); + delay(100000); + for (i = 0; i < 5; i++) { + UDA_Reg_write((UDA1380_REG) (UDA_EVALM_CLK + i), UDA_sys_regs_dat[i], I2C_Config); + temp = UDA_Reg_read((UDA1380_REG) (UDA_EVALM_CLK + i)); + if (temp != UDA_sys_regs_dat[i]) { + return ERROR; + } + } + + /* interfilter regs init */ + for (i = 0; i < 5; i++) { + UDA_Reg_write((UDA1380_REG) (UDA_MASTER_VOL_CTRL + i), UDA_interfil_regs_dat[i], I2C_Config); + temp = UDA_Reg_read((UDA1380_REG) (UDA_MASTER_VOL_CTRL + i)); + if (temp != UDA_interfil_regs_dat[i]) { + return ERROR; + } + } + /* decimator regs init */ + for (i = 0; i < 4; i++) { + UDA_Reg_write((UDA1380_REG) (UDA_DEC_VOL_CTRL + i), UDA_decimator_regs_dat[i], I2C_Config); + temp = UDA_Reg_read((UDA1380_REG) (UDA_DEC_VOL_CTRL + i)); + if (temp != UDA_decimator_regs_dat[i]) { + return ERROR; + } + } + + if (audio_in_sel == MCB_18XX_AUDIO_MIC_SELECT) { + /* Disable Power On for ADCR, PGAR, PGAL to get mic sound more clearly */ + UDA_Reg_write((UDA1380_REG) (UDA_POWER_CTRL), UDA1380_REG_PWRCTRL_DEFAULT_VALUE & (~(0x0B)), I2C_Config); + temp = UDA_Reg_read((UDA1380_REG) (UDA_ADC_CTRL)); + if (temp != (UDA1380_REG_ADC_DEFAULT_VALUE | MCB_18XX_AUDIO_MIC_SELECT)) { + return ERROR; + } + UDA_Reg_write((UDA1380_REG) (UDA_ADC_CTRL), + UDA1380_REG_ADC_DEFAULT_VALUE | MCB_18XX_AUDIO_MIC_SELECT, + I2C_Config); + temp = UDA_Reg_read((UDA1380_REG) (UDA_ADC_CTRL)); + if (temp != (UDA1380_REG_ADC_DEFAULT_VALUE | MCB_18XX_AUDIO_MIC_SELECT)) { + return ERROR; + } + } + return SUCCESS; + +} + +void Board_Audio_Init(LPC_I2S_Type *I2Sx, Board_Audio_Input_Sel_Type audio_in_sel) +{ + uint8_t uda1380_tx_data_buf[3]; + Chip_I2S_Audio_Format_Type I2S_Config; + I2C_M_SETUP_Type I2C_Config; + I2C_Config.sl_addr7bit = I2CDEV_UDA1380_ADDR; + I2C_Config.retransmissions_max = 5; + I2C_Config.tx_length = 3; + I2C_Config.tx_data = uda1380_tx_data_buf; + I2C_Config.rx_length = 0; + I2C_Config.rx_data = NULL; + + /* Initialize I2C peripheral ------------------------------------*/ + /* Init I2C */ + Chip_I2C_Init(LPC_I2C0); + Chip_I2C_SetClockRate(LPC_I2C0, 100000); + + I2S_Config.SampleRate = 48000; + I2S_Config.ChannelNumber = 2; /* 1 is mono, 2 is stereo */ + I2S_Config.WordWidth = 16; /* 8, 16 or 32 bits */ + Chip_I2S_Init(LPC_I2S0); + Chip_I2S_Config(LPC_I2S0, I2S_TX_MODE, &I2S_Config); + /* Enable Slave I2C operation */ + Chip_I2C_Cmd(LPC_I2C0, I2C_MASTER_MODE, ENABLE); + /* Init UDA1380 CODEC */ + while (UDA1380_init(&I2C_Config, audio_in_sel) != SUCCESS) {} + +} + +/* FIXME Should we remove this function? */ +void Serial_CreateStream(void *Stream) +{} + +/** + * @} + */ diff --git a/bsp/xplorer4330/libraries/lpc_board/boards_18xx_43xx/ngx_xplorer_18304330/board_ngx_xplorer_18304330.h b/bsp/xplorer4330/libraries/lpc_board/boards_18xx_43xx/ngx_xplorer_18304330/board_ngx_xplorer_18304330.h new file mode 100644 index 0000000000..70e32d04e4 --- /dev/null +++ b/bsp/xplorer4330/libraries/lpc_board/boards_18xx_43xx/ngx_xplorer_18304330/board_ngx_xplorer_18304330.h @@ -0,0 +1,232 @@ +/* + * @brief NGX Xplorer 1830/4330 board file + * + * @note + * Copyright(C) NXP Semiconductors, 2012 + * All rights reserved. + * + * @par + * Software that is described herein is for illustrative purposes only + * which provides customers with programming information regarding the + * LPC products. This software is supplied "AS IS" without any warranties of + * any kind, and NXP Semiconductors and its licensor disclaim any and + * all warranties, express or implied, including all implied warranties of + * merchantability, fitness for a particular purpose and non-infringement of + * intellectual property rights. NXP Semiconductors assumes no responsibility + * or liability for the use of the software, conveys no license or rights under any + * patent, copyright, mask work right, or any other intellectual property rights in + * or to any products. NXP Semiconductors reserves the right to make changes + * in the software without notification. NXP Semiconductors also makes no + * representation or warranty that such application will be suitable for the + * specified use without further testing or modification. + * + * @par + * Permission to use, copy, modify, and distribute this software and its + * documentation is hereby granted, under NXP Semiconductors' and its + * licensor's relevant copyrights in the software, without fee, provided that it + * is used in conjunction with NXP Semiconductors microcontrollers. This + * copyright, permission, and disclaimer notice must appear in all copies of + * this code. + */ + +#ifndef __BOARD_NGX_XPLORER_18304330_H_ +#define __BOARD_NGX_XPLORER_18304330_H_ + +#include "chip.h" +#include "board_api.h" +#include "lpc_phy.h" + +#ifdef __cplusplus +extern "C" { +#endif + +/** @defgroup BOARD_NGX_XPLORER_18304330 LPC1830 and LPC4330 NGX Xplorer board support functions + * @ingroup BOARDS_18XX_43XX + * @{ + */ + +/** @defgroup BOARD_NGX_XPLORER_18304330_OPTIONS BOARD: LPC1830 and LPC4330 NGX Xplorer board builds options + * The NGX board has options that configure it's operation at build-time.
+ * CHIP_LPC* + * - One of @ref CHIP_LPC18XX or @ref CHIP_LPC43XX must be defined for this board + * DEBUG:
+ * - When defined, DEBUGOUT and DEBUGSTR functions are routed to the UART defined by DEBUG_UART
+ * - When not defined, DEBUGOUT and DEBUGSTR are null functions

+ * DEBUG_UART:
+ * - This defines the UART used for debug output when DEBUG is defined, example: @ref LPC_USART0

+ * CRYSTAL_MAIN_FREQ_IN:
+ * - This define specifies the crystal input clock into the chip, example: 12000000

+ * CRYSTAL_32K_FREQ_IN:
+ * - This define specifies the RTC crystal input clock into the chip, example: 32768

+ * EXTERNAL_CLKIN_FREQ_IN:
+ * - This define specifies the clock rate input into the EXTCLKIN pin, example: 28000000

+ * MAX_CLOCK_FREQ:
+ * - When defined, this will be used to configure the CPU clock rate, example: 150000000
+ * - When not defined, the system will use the maximum CPU clokc rate

+ * BOARD_HITEX_EVA_18504350:
+ * - When building for NGX boards, BOARD_NGX_XPLORER_18304330 is defined
+ *

+ * For more information on driver options see @ref LPCOPEN_DESIGN_ARPPROACH
+ * @{ + */ + +/** + * @} + */ + +#define BOARD_NGX_XPLORER_18304330 + +#define I2CDEV_UDA1380_ADDR (0x34 >> 1) + +#define UDA1380_REG_EVALCLK_DEFAULT_VALUE (0xF << 8 | 0x3 << 4 | 1 << 1) +#define UDA1380_REG_I2S_DEFAULT_VALUE 0x0000 + +#define UDA1380_REG_PWRCTRL_DEFAULT_VALUE (1 << 15 | 1 << 13 | 1 << 10 | 1 << 8 | 1 << 6 | 1 << 4 | 0x0F) +#define UDA1380_REG_ANAMIX_DEFAULT_VALUE 0x0000 +#define UDA1380_REG_HEADAMP_DEFAULT_VALUE ( 1 << 9 | 2) + +#define UDA1380_REG_MSTRVOL_DEFAULT_VALUE 0x0000 +#define UDA1380_REG_MIXVOL_DEFAULT_VALUE 0x0000 +#define UDA1380_REG_MODEBBT_DEFAULT_VALUE 0x0000 +#define UDA1380_REG_MSTRMUTE_DEFAULT_VALUE (2 << 8 | 2) +#define UDA1380_REG_MIXSDO_DEFAULT_VALUE 0x0000 + +#define UDA1380_REG_DECVOL_DEFAULT_VALUE 0xE4E4 /* Decrease Volume -28dB */ +#define UDA1380_REG_PGA_DEFAULT_VALUE 0x0000 +#define UDA1380_REG_ADC_DEFAULT_VALUE 0x0001 /* Apply 0bB VGA Gain, enable DC Filter */ +#define UDA1380_REG_AGC_DEFAULT_VALUE 0x0000 +#define UDA1380_REG_L3_DEFAULT_VALUE 0x0000 + +/* For USBLIB examples */ +#define LEDS_LED1 0x01 +#define LEDS_LED2 0x02 +#define LEDS_LED3 0x04 +#define LEDS_LED4 0x08 +#define LEDS_NO_LEDS 0x00 +#define BUTTONS_BUTTON1 0x01 +#define JOY_UP 0x01 +#define JOY_DOWN 0x02 +#define JOY_LEFT 0x04 +#define JOY_RIGHT 0x08 +#define JOY_PRESS 0x10 +#define NO_BUTTON_PRESSED 0x00 + +#define BUTTONS_BUTTON1_GPIO_PORT_NUM 0 +#define BUTTONS_BUTTON1_GPIO_BIT_NUM 7 +#define LED1_GPIO_PORT_NUM 1 +#define LED1_GPIO_BIT_NUM 11 +#define LED2_GPIO_PORT_NUM 1 +#define LED2_GPIO_BIT_NUM 12 + +typedef enum { + MCB_18XX_AUDIO_MIC_SELECT = 1 << 2 | 1 << 3, + MCB_18XX_AUDIO_LINE_IN_SELECT = 0x00, +} Board_Audio_Input_Sel_Type; + +/* UDA1380 Register Address */ +typedef enum { + UDA_EVALM_CLK = 0x00, + UDA_BUS_CTRL, + UDA_POWER_CTRL, + UDA_ANALOG_CTRL, + UDA_HPAMP_CTRL, + UDA_MASTER_VOL_CTRL = 0x10, + UDA_MIXER_VOL_CTRL, + UDA_MODE_CTRL, + UDA_MUTE_CTRL, + UDA_MIXER_FILTER_CTRL, + UDA_DEC_VOL_CTRL = 0x20, + UDA_PGA_CTRL, + UDA_ADC_CTRL, + UDA_AGC_CTRL, + UDA_TOTAL_REG +} UDA1380_REG; + +/** + * @brief Sets up board specific I2C interface + * @param I2Cx : Pointer to I2C interface to initialize + * @return Nothing + */ +void Board_I2C_Init(LPC_I2C_Type *I2Cx); + +/** + * @brief Initializes board specific GPIO Interrupt + * @return Nothing + */ +void Board_GPIO_Int_Init(void); + +/** + * @brief Initialize pin muxing for SSP interface + * @param SSPx : Pointer to SSP interface to initialize + * @return Nothing + */ +void Board_SSP_Init(LPC_SSP_Type *SSPx); + +/** + * @brief Returns the MAC address assigned to this board + * @param mcaddr : Pointer to 6-byte character array to populate with MAC address + * @return Nothing + */ +void Board_ENET_GetMacADDR(uint8_t *mcaddr); + +/** + * @brief Initialize pin muxing for a UART + * @param UARTx : Pointer to UART register block for UART pins to init + * @return Nothing + */ +void Board_UART_Init(LPC_USART_Type *UARTx); + +/** + * @brief Initialize pin muxing for SDMMC interface + * @return Nothing + */ +void Board_SDMMC_Init(void); + +/** + * @brief Initialize button(s) interface on board + * @return Nothing + */ +void Board_Buttons_Init(void); + +/** + * @brief Initialize joystick interface on board + * @return Nothing + */ +void Board_Joystick_Init(void); + +/** + * @brief Returns joystick states on board + * @return Returns a JOY_* value, ir JOY_PRESS or JOY_UP + */ +uint8_t Joystick_GetStatus(void); + +/** + * @brief Returns button(s) state on board + * @return Returns BUTTONS_BUTTON1 if button1 is pressed + */ +uint32_t Buttons_GetStatus (void); + +/** + * @brief Initialize I2S interface for the board and UDA1380 + * @param I2Sx : Pointer to I2S register interface used on this board + * @param audio_in_sel : Audio input selection + * @return Nothing + */ +void Board_Audio_Init(LPC_I2S_Type *I2Sx, Board_Audio_Input_Sel_Type audio_in_sel); + +/** + * @brief FIXME + * @param Stream : FIXME + * @return Nothing + */ +void Serial_CreateStream(void *Stream); + +/** + * @} + */ + +#ifdef __cplusplus +} +#endif + +#endif /* __BOARD_NGX_XPLORER_18304330_H_ */ diff --git a/bsp/xplorer4330/libraries/lpc_board/boards_18xx_43xx/ngx_xplorer_18304330/ngx_xplorer_1830/sys_config.h b/bsp/xplorer4330/libraries/lpc_board/boards_18xx_43xx/ngx_xplorer_18304330/ngx_xplorer_1830/sys_config.h new file mode 100644 index 0000000000..8c446bccb7 --- /dev/null +++ b/bsp/xplorer4330/libraries/lpc_board/boards_18xx_43xx/ngx_xplorer_18304330/ngx_xplorer_1830/sys_config.h @@ -0,0 +1,58 @@ +/* + * @note + * Copyright(C) NXP Semiconductors, 2012 + * All rights reserved. + * + * @par + * Software that is described herein is for illustrative purposes only + * which provides customers with programming information regarding the + * LPC products. This software is supplied "AS IS" without any warranties of + * any kind, and NXP Semiconductors and its licensor disclaim any and + * all warranties, express or implied, including all implied warranties of + * merchantability, fitness for a particular purpose and non-infringement of + * intellectual property rights. NXP Semiconductors assumes no responsibility + * or liability for the use of the software, conveys no license or rights under any + * patent, copyright, mask work right, or any other intellectual property rights in + * or to any products. NXP Semiconductors reserves the right to make changes + * in the software without notification. NXP Semiconductors also makes no + * representation or warranty that such application will be suitable for the + * specified use without further testing or modification. + * + * @par + * Permission to use, copy, modify, and distribute this software and its + * documentation is hereby granted, under NXP Semiconductors' and its + * licensor's relevant copyrights in the software, without fee, provided that it + * is used in conjunction with NXP Semiconductors microcontrollers. This + * copyright, permission, and disclaimer notice must appear in all copies of + * this code. + */ + +#ifndef __SYS_CONFIG_H_ +#define __SYS_CONFIG_H_ + +#define USE_RMII +#define CHIP_LPC18XX + +/* Enable DEBUG for IO support via the UART */ +// #define DEBUG + +/* Enable DEBUG_SEMIHOSTING along with DEBUG to enable IO support + via semihosting */ +// #define DEBUG_SEMIHOSTING + +/* Board UART used for debug output */ +#define DEBUG_UART LPC_USART0 /* No port on Xplorer */ + +/* Crystal frequency into device */ +#define CRYSTAL_MAIN_FREQ_IN 12000000 + +/* Crystal frequency into device for RTC/32K input */ +#define CRYSTAL_32K_FREQ_IN 32768 + +/* Frequency on external clock in pin */ +#define EXTERNAL_CLKIN_FREQ_IN 0 + +/* Default CPU clock frequency */ +#define MAX_CLOCK_FREQ (180000000) + +#endif /* __SYS_CONFIG_H_ */ diff --git a/bsp/xplorer4330/libraries/lpc_board/boards_18xx_43xx/ngx_xplorer_18304330/ngx_xplorer_4330/sys_config.h b/bsp/xplorer4330/libraries/lpc_board/boards_18xx_43xx/ngx_xplorer_18304330/ngx_xplorer_4330/sys_config.h new file mode 100644 index 0000000000..994aa79347 --- /dev/null +++ b/bsp/xplorer4330/libraries/lpc_board/boards_18xx_43xx/ngx_xplorer_18304330/ngx_xplorer_4330/sys_config.h @@ -0,0 +1,58 @@ +/* + * @note + * Copyright(C) NXP Semiconductors, 2012 + * All rights reserved. + * + * @par + * Software that is described herein is for illustrative purposes only + * which provides customers with programming information regarding the + * LPC products. This software is supplied "AS IS" without any warranties of + * any kind, and NXP Semiconductors and its licensor disclaim any and + * all warranties, express or implied, including all implied warranties of + * merchantability, fitness for a particular purpose and non-infringement of + * intellectual property rights. NXP Semiconductors assumes no responsibility + * or liability for the use of the software, conveys no license or rights under any + * patent, copyright, mask work right, or any other intellectual property rights in + * or to any products. NXP Semiconductors reserves the right to make changes + * in the software without notification. NXP Semiconductors also makes no + * representation or warranty that such application will be suitable for the + * specified use without further testing or modification. + * + * @par + * Permission to use, copy, modify, and distribute this software and its + * documentation is hereby granted, under NXP Semiconductors' and its + * licensor's relevant copyrights in the software, without fee, provided that it + * is used in conjunction with NXP Semiconductors microcontrollers. This + * copyright, permission, and disclaimer notice must appear in all copies of + * this code. + */ + +#ifndef __SYS_CONFIG_H_ +#define __SYS_CONFIG_H_ + +#define USE_RMII +#define CHIP_LPC43XX + +/* Enable DEBUG for IO support via the UART */ +// #define DEBUG + +/* Enable DEBUG_SEMIHOSTING along with DEBUG to enable IO support + via semihosting */ +// #define DEBUG_SEMIHOSTING + +/* Board UART used for debug output */ +#define DEBUG_UART LPC_USART0 /* No port on Xplorer */ + +/* Crystal frequency into device */ +#define CRYSTAL_MAIN_FREQ_IN 12000000 + +/* Crystal frequency into device for RTC/32K input */ +#define CRYSTAL_32K_FREQ_IN 32768 + +/* Frequency on external clock in pin */ +#define EXTERNAL_CLKIN_FREQ_IN 0 + +/* Default CPU clock frequency */ +#define MAX_CLOCK_FREQ (204000000) + +#endif /* __SYS_CONFIG_H_ */ diff --git a/bsp/xplorer4330/libraries/lpc_board/boards_18xx_43xx/ngx_xplorer_18304330/sysinit_ngx_xplorer_18304330.c b/bsp/xplorer4330/libraries/lpc_board/boards_18xx_43xx/ngx_xplorer_18304330/sysinit_ngx_xplorer_18304330.c new file mode 100644 index 0000000000..19fcc92359 --- /dev/null +++ b/bsp/xplorer4330/libraries/lpc_board/boards_18xx_43xx/ngx_xplorer_18304330/sysinit_ngx_xplorer_18304330.c @@ -0,0 +1,239 @@ +/* + * Copyright(C) NXP Semiconductors, 2012 + * All rights reserved. + * + * Software that is described herein is for illustrative purposes only + * which provides customers with programming information regarding the + * LPC products. This software is supplied "AS IS" without any warranties of + * any kind, and NXP Semiconductors and its licensor disclaim any and + * all warranties, express or implied, including all implied warranties of + * merchantability, fitness for a particular purpose and non-infringement of + * intellectual property rights. NXP Semiconductors assumes no responsibility + * or liability for the use of the software, conveys no license or rights under any + * patent, copyright, mask work right, or any other intellectual property rights in + * or to any products. NXP Semiconductors reserves the right to make changes + * in the software without notification. NXP Semiconductors also makes no + * representation or warranty that such application will be suitable for the + * specified use without further testing or modification. + * + * Permission to use, copy, modify, and distribute this software and its + * documentation is hereby granted, under NXP Semiconductors' and its + * licensor's relevant copyrights in the software, without fee, provided that it + * is used in conjunction with NXP Semiconductors microcontrollers. This + * copyright, permission, and disclaimer notice must appear in all copies of + * this code. + */ + +#include "board.h" + +/** @defgroup BOARD_NGX_XPLORER_18304330_SYSINIT LPC1830 and LPC4330 NGX Xplorer board System Init code + * @ingroup BOARD_NGX_XPLORER_18304330 + * The System initialization code is called prior to the application and + * initializes the board for run-time operation. Board initialization + * for the NGX Xplorer boards includes clock setup and default pin muxing + * configuration. + * + * With the exception of stack space, no RW memory is used for this call. + * + * LPC1830 and LPC4330 NGX Xplorer setup
+ * Clocking:
+ * All base clocks enabled by default (Save power by disabling un-needed clocks)
+ * CPU PLL set to maximum clock frequency (as defined by MAX_CLOCK_FREQ value)
+ * SPIFI FLASH clock setup for fastest speed
+ * Pin muxing:
+ * Sets up various pin mux functions for the board (Ethernet, LEDs, etc.)
+ * Memory:
+ * There is no memory setup for this board. + * @{ + */ + +#ifndef CORE_M0 +/* SCR pin definitions for pin muxing */ +typedef struct { + uint8_t pingrp; /* Pin group */ + uint8_t pinnum; /* Pin number */ + uint8_t pincfg; /* Pin configuration for SCU */ + uint8_t funcnum;/* Function number */ +} PINMUX_GRP_T; + +/* Structure for initial base clock states */ +struct CLK_BASE_STATES { + CGU_BASE_CLK_T clk; /* Base clock */ + CGU_CLKIN_T clkin; /* Base clock source, see UM for allowable souorces per base clock */ + bool autoblock_enab;/* Set to true to enable autoblocking on frequency change */ + bool powerdn; /* Set to true if the base clock is initially powered down */ +}; + +/* Initial base clock states are mostly on */ +STATIC const struct CLK_BASE_STATES InitClkStates[] = { + {CLK_BASE_SAFE, CLKIN_IRC, true, false}, + {CLK_BASE_APB1, CLKIN_MAINPLL, true, false}, + {CLK_BASE_APB3, CLKIN_MAINPLL, true, false}, + {CLK_BASE_USB0, CLKIN_USBPLL, true, false}, +#if defined(CHIP_LPC43XX) + {CLK_BASE_PERIPH, CLKIN_MAINPLL, true, false}, +#endif + {CLK_BASE_USB1, CLKIN_USBPLL, true, false}, +#if defined(CHIP_LPC43XX) + {CLK_BASE_SPI, CLKIN_MAINPLL, true, false}, +#endif + {CLK_BASE_PHY_TX, CLKIN_ENET_TX, true, false}, +#if defined(USE_RMII) + {CLK_BASE_PHY_RX, CLKIN_ENET_TX, true, false}, +#else + {CLK_BASE_PHY_RX, CLKIN_ENET_RX, true, false}, +#endif + {CLK_BASE_LCD, CLKIN_MAINPLL, false, true}, +#if defined(CHIP_LPC43XX) + {CLK_BASE_VADC, CLKIN_MAINPLL, true, true}, +#endif + {CLK_BASE_SDIO, CLKIN_MAINPLL, true, false}, + {CLK_BASE_SSP0, CLKIN_MAINPLL, true, false}, + {CLK_BASE_SSP1, CLKIN_MAINPLL, true, false}, + {CLK_BASE_UART0, CLKIN_MAINPLL, true, false}, + {CLK_BASE_UART1, CLKIN_MAINPLL, true, false}, + {CLK_BASE_UART2, CLKIN_MAINPLL, true, false}, + {CLK_BASE_UART3, CLKIN_MAINPLL, true, false}, + {CLK_BASE_OUT, CLKINPUT_PD, true, false}, + {CLK_BASE_APLL, CLKINPUT_PD, true, false}, + {CLK_BASE_CGU_OUT0, CLKINPUT_PD, true, false}, + {CLK_BASE_CGU_OUT1, CLKINPUT_PD, true, false} +}; + +/* SPIFI high speed pin mode setup */ +STATIC const PINMUX_GRP_T spifipinmuxing[] = { + {0x3, 3, (MD_PLN_FAST), FUNC3}, /* SPIFI CLK */ + {0x3, 4, (MD_PLN_FAST), FUNC3}, /* SPIFI D3 */ + {0x3, 5, (MD_PLN_FAST), FUNC3}, /* SPIFI D2 */ + {0x3, 6, (MD_PLN_FAST), FUNC3}, /* SPIFI D1 */ + {0x3, 7, (MD_PLN_FAST), FUNC3}, /* SPIFI D0 */ + {0x3, 8, (MD_PLN_FAST), FUNC3} /* SPIFI CS/SSEL */ +}; + +/* Setup system clocking */ +STATIC void SystemSetupClocking(void) +{ + int i; + + /* Switch main system clocking to crystal */ + Chip_Clock_EnableCrystal(); + Chip_Clock_SetBaseClock(CLK_BASE_MX, CLKIN_CRYSTAL, true, false); + + /* Setup PLL for 100MHz and switch main system clocking */ + Chip_Clock_SetupMainPLLHz(CLKIN_CRYSTAL, CRYSTAL_MAIN_FREQ_IN, 100 * 1000000, 100 * 1000000); + Chip_Clock_SetBaseClock(CLK_BASE_MX, CLKIN_MAINPLL, true, false); + + /* Setup PLL for maximum clock */ + Chip_Clock_SetupMainPLLHz(CLKIN_CRYSTAL, CRYSTAL_MAIN_FREQ_IN, MAX_CLOCK_FREQ, MAX_CLOCK_FREQ); + + /* Setup system base clocks and initial states. This won't enable and + disable individual clocks, but sets up the base clock sources for + each individual peripheral clock. */ + for (i = 0; i < (sizeof(InitClkStates) / sizeof(InitClkStates[0])); i++) { + Chip_Clock_SetBaseClock(InitClkStates[i].clk, InitClkStates[i].clkin, + InitClkStates[i].autoblock_enab, InitClkStates[i].powerdn); + } + + /* Reset and enable 32Khz oscillator */ + LPC_CREG->CREG0 &= ~((1 << 3) | (1 << 2)); + LPC_CREG->CREG0 |= (1 << 1) | (1 << 0); + + /* SPIFI pin setup is done prior to setting up system clocking */ + for (i = 0; i < (sizeof(spifipinmuxing) / sizeof(spifipinmuxing[0])); i++) { + Chip_SCU_PinMux(spifipinmuxing[i].pingrp, spifipinmuxing[i].pinnum, + spifipinmuxing[i].pincfg, spifipinmuxing[i].funcnum); + } + + /* Setup a divider E for main PLL clock switch SPIFI clock to that divider. + Divide rate is based on CPU speed and speed of SPI FLASH part. */ +#if (MAX_CLOCK_FREQ > 180000000) + Chip_Clock_SetDivider(CLK_IDIV_E, CLKIN_MAINPLL, 5); +#else + Chip_Clock_SetDivider(CLK_IDIV_E, CLKIN_MAINPLL, 4); +#endif + Chip_Clock_SetBaseClock(CLK_BASE_SPIFI, CLKIN_IDIVE, true, false); +} + +STATIC const PINMUX_GRP_T pinmuxing[] = { + /* RMII pin group */ + {0x1, 15, (MD_EHS | MD_PLN | MD_EZI | MD_ZI), FUNC3}, + {0x0, 0, (MD_EHS | MD_PLN | MD_EZI | MD_ZI), FUNC2}, + {0x1, 16, (MD_EHS | MD_PLN | MD_EZI | MD_ZI), FUNC7}, + {0x0, 1, (MD_EHS | MD_PLN | MD_ZI), FUNC6}, + {0x1, 19, (MD_EHS | MD_PLN | MD_EZI | MD_ZI), FUNC0}, + {0x1, 18, (MD_EHS | MD_PLN | MD_ZI), FUNC3}, + {0x1, 20, (MD_EHS | MD_PLN | MD_ZI), FUNC3}, + {0x1, 17, (MD_EHS | MD_PLN | MD_EZI | MD_ZI), FUNC3}, + {0x2, 0, (MD_EHS | MD_PLN | MD_ZI), FUNC7}, + /* Board LEDs */ + {0x2, 11, MD_PDN, FUNC0}, + {0x2, 12, MD_PDN, FUNC0}, + /* I2S */ + {0x3, 0, MD_PLN_FAST, FUNC2}, + {0x6, 0, MD_PLN_FAST, FUNC4}, + {0x7, 2, MD_PLN_FAST, FUNC2}, + {0x6, 2, MD_PLN_FAST, FUNC3}, + {0x7, 1, MD_PLN_FAST, FUNC2}, + {0x6, 1, MD_PLN_FAST, FUNC3}, +}; + +/* Sets up system pin muxing */ +STATIC void SystemSetupMuxing(void) +{ + int i; + + /* Setup system level pin muxing */ + for (i = 0; i < (sizeof(pinmuxing) / sizeof(pinmuxing[0])); i++) { + Chip_SCU_PinMux(pinmuxing[i].pingrp, pinmuxing[i].pinnum, + pinmuxing[i].pincfg, pinmuxing[i].funcnum); + } +} + +/* Nothing to do for the Xplorer board */ +STATIC void SystemSetupMemory(void) +{} + +#endif + +/** + * @brief Setup the system + * @return none + * SystemInit() is called prior to the application and sets up system + * clocking, memory, and any resources needed prior to the application + * starting. + */ +void SystemInit(void) +{ +#if defined(CORE_M3) || defined(CORE_M4) + volatile unsigned int *pSCB_VTOR = (volatile unsigned int *) 0xE000ED08; + +#if defined(__IAR_SYSTEMS_ICC__) + extern void *__vector_table; + + *pSCB_VTOR = (unsigned int) &__vector_table; +#elif defined(__CODE_RED) + extern void *g_pfnVectors; + + *pSCB_VTOR = (unsigned int) &g_pfnVectors; +#elif defined(__ARMCC_VERSION) + extern void *__Vectors; + + *pSCB_VTOR = (unsigned int) &__Vectors; +#endif + +#if defined(__FPU_PRESENT) && __FPU_PRESENT == 1 + fpuInit(); +#endif + + /* Setup system clocking and memory. This is done early to allow the + application and tools to clear memory and use scatter loading to + external memory. */ + SystemSetupClocking(); + SystemSetupMuxing(); + SystemSetupMemory(); +#endif +} + +/** + * @} + */ diff --git a/bsp/xplorer4330/libraries/lpc_chip/SConscript b/bsp/xplorer4330/libraries/lpc_chip/SConscript new file mode 100644 index 0000000000..d96decd18a --- /dev/null +++ b/bsp/xplorer4330/libraries/lpc_chip/SConscript @@ -0,0 +1,15 @@ +Import('RTT_ROOT') +Import('rtconfig') +from building import * + +cwd = GetCurrentDir() + +src = Glob('chip_18xx_43xx/*.c') +src += Glob('chip_common/*.c') + +path = [cwd + '/chip_18xx_43xx', + cwd + '/chip_common'] + +group = DefineGroup('lpc_chip', src, depend = [], CPPPATH = path) + +Return('group') diff --git a/bsp/xplorer4330/libraries/lpc_chip/chip_18xx_43xx/adc_18xx_43xx.c b/bsp/xplorer4330/libraries/lpc_chip/chip_18xx_43xx/adc_18xx_43xx.c new file mode 100644 index 0000000000..e3f531220b --- /dev/null +++ b/bsp/xplorer4330/libraries/lpc_chip/chip_18xx_43xx/adc_18xx_43xx.c @@ -0,0 +1,136 @@ +/* + * @brief LPC18xx/43xx A/D conversion driver + * + * @note + * Copyright(C) NXP Semiconductors, 2012 + * All rights reserved. + * + * @par + * Software that is described herein is for illustrative purposes only + * which provides customers with programming information regarding the + * LPC products. This software is supplied "AS IS" without any warranties of + * any kind, and NXP Semiconductors and its licensor disclaim any and + * all warranties, express or implied, including all implied warranties of + * merchantability, fitness for a particular purpose and non-infringement of + * intellectual property rights. NXP Semiconductors assumes no responsibility + * or liability for the use of the software, conveys no license or rights under any + * patent, copyright, mask work right, or any other intellectual property rights in + * or to any products. NXP Semiconductors reserves the right to make changes + * in the software without notification. NXP Semiconductors also makes no + * representation or warranty that such application will be suitable for the + * specified use without further testing or modification. + * + * @par + * Permission to use, copy, modify, and distribute this software and its + * documentation is hereby granted, under NXP Semiconductors' and its + * licensor's relevant copyrights in the software, without fee, provided that it + * is used in conjunction with NXP Semiconductors microcontrollers. This + * copyright, permission, and disclaimer notice must appear in all copies of + * this code. + */ + +#include "adc_18xx_43xx.h" + +/***************************************************************************** + * Private types/enumerations/variables + ****************************************************************************/ + +/*The channel to be operated on */ +static uint8_t active_channel; + +/***************************************************************************** + * Public types/enumerations/variables + ****************************************************************************/ + +/***************************************************************************** + * Private functions + ****************************************************************************/ + +/* Returns the clock for the selected ADC */ +static CCU_CLK_T Chip_ADC_GetClk(LPC_ADC_Type *pADC) +{ + CCU_CLK_T adcclk; + + if (pADC == LPC_ADC0) { + adcclk = CLK_APB3_ADC0; + } + else { + adcclk = CLK_APB3_ADC1; + } + + return adcclk; +} + +/***************************************************************************** + * Public functions + ****************************************************************************/ + +/* Initialize the ADC peripheral and the ADC setup structure to default value */ +void Chip_ADC_Init(LPC_ADC_Type *pADC, ADC_Clock_Setup_Type *ADCSetup) +{ + CCU_CLK_T adcclk = Chip_ADC_GetClk(pADC); + + /* Enable ADC clocking */ + Chip_Clock_EnableOpts(adcclk, true, true, 1); + ADCSetup->adcPerClock = Chip_Clock_GetRate(adcclk); + + ADCSetup->adcRate = 400000; + ADCSetup->bitsAccuracy = ADC_10BITS; + IP_ADC_Init(pADC, ADCSetup->adcRate, ADCSetup->adcPerClock, ADCSetup->bitsAccuracy); +} + +/* Select the mode starting the AD conversion */ +void Chip_ADC_Set_StartMode(LPC_ADC_Type *pADC, ADC_StartMode mode, ADC_EdgeCfg EdgeOption) +{ + if ((mode != ADC_START_NOW) && (mode != ADC_NO_START)) { + IP_ADC_EdgeStartConfig(pADC, (uint8_t) EdgeOption); + } + IP_ADC_SetStartMode(pADC, (uint8_t) mode); +} + +/* Set the ADC Sample rate */ +void Chip_ADC_Set_SampleRate(LPC_ADC_Type *pADC, ADC_Clock_Setup_Type *ADCSetup, uint32_t rate) +{ + ADCSetup->adcRate = rate; + IP_ADC_Init(pADC, ADCSetup->adcRate, ADCSetup->adcPerClock, ADCSetup->bitsAccuracy); + +} + +/* Set the ADC accuracy bits */ +void Chip_ADC_Set_Resolution(LPC_ADC_Type *pADC, ADC_Clock_Setup_Type *ADCSetup, ADC_Resolution resolution) +{ + ADCSetup->bitsAccuracy = resolution; + IP_ADC_Init(pADC, ADCSetup->adcRate, ADCSetup->adcPerClock, ADCSetup->bitsAccuracy); +} + +/* Enable or disable the ADC channel on ADC peripheral */ +void Chip_ADC_Channel_Enable_Cmd(LPC_ADC_Type *pADC, ADC_Channel channel, FunctionalState NewState) +{ + IP_ADC_SetChannelNumber(pADC, channel, NewState); + active_channel = channel; +} + +/* Enable burst mode */ +void Chip_ADC_Burst_Cmd(LPC_ADC_Type *pADC, FunctionalState NewState) +{ + IP_ADC_SetStartMode(pADC, ADC_NO_START); + IP_ADC_SetBurstMode(pADC, NewState); +} + +/* Read the ADC value and convert it to 8bits value */ +Status Chip_ADC_Read_Byte(LPC_ADC_Type *pADC, uint8_t *data) +{ + uint16_t temp; + Status rt; + + rt = IP_ADC_Get_Val(pADC, active_channel, &temp); + *data = (uint8_t) temp; + + return rt; +} + +/* Set a channel to be read A/D data */ +void Chip_ADC_Active_Channel(uint8_t channel) +{ + active_channel = channel; +} diff --git a/bsp/xplorer4330/libraries/lpc_chip/chip_18xx_43xx/adc_18xx_43xx.h b/bsp/xplorer4330/libraries/lpc_chip/chip_18xx_43xx/adc_18xx_43xx.h new file mode 100644 index 0000000000..8765b43ffe --- /dev/null +++ b/bsp/xplorer4330/libraries/lpc_chip/chip_18xx_43xx/adc_18xx_43xx.h @@ -0,0 +1,240 @@ +/* + * @brief LPC18xx/43xx A/D conversion driver + * + * @note + * Copyright(C) NXP Semiconductors, 2012 + * All rights reserved. + * + * @par + * Software that is described herein is for illustrative purposes only + * which provides customers with programming information regarding the + * LPC products. This software is supplied "AS IS" without any warranties of + * any kind, and NXP Semiconductors and its licensor disclaim any and + * all warranties, express or implied, including all implied warranties of + * merchantability, fitness for a particular purpose and non-infringement of + * intellectual property rights. NXP Semiconductors assumes no responsibility + * or liability for the use of the software, conveys no license or rights under any + * patent, copyright, mask work right, or any other intellectual property rights in + * or to any products. NXP Semiconductors reserves the right to make changes + * in the software without notification. NXP Semiconductors also makes no + * representation or warranty that such application will be suitable for the + * specified use without further testing or modification. + * + * @par + * Permission to use, copy, modify, and distribute this software and its + * documentation is hereby granted, under NXP Semiconductors' and its + * licensor's relevant copyrights in the software, without fee, provided that it + * is used in conjunction with NXP Semiconductors microcontrollers. This + * copyright, permission, and disclaimer notice must appear in all copies of + * this code. + */ + +#ifndef __ADC_18XX_43XX_H_ +#define __ADC_18XX_43XX_H_ + +#include "chip.h" + +#ifdef __cplusplus +extern "C" { +#endif + +/** @defgroup ADC_18XX_43XX CHIP: LPC18xx/43xx A/D conversion driver + * @ingroup CHIP_18XX_43XX_Drivers + * @{ + */ + +/** The channels on one ADC peripheral*/ +typedef enum ADC_Channel { + ADC_CH0 = 0, /**< ADC channel 0 */ + ADC_CH1, /**< ADC channel 1 */ + ADC_CH2, /**< ADC channel 2 */ + ADC_CH3, /**< ADC channel 3 */ + ADC_CH4, /**< ADC channel 4 */ + ADC_CH5, /**< ADC channel 5 */ + ADC_CH6, /**< ADC channel 6 */ + ADC_CH7, /**< ADC channel 7 */ +} ADC_Channel; + +/** The number of bits of accuracy of the result in the LS bits of ADDR*/ +typedef enum ADC_Resolution { + ADC_10BITS = 0, /**< ADC 10 bits */ + ADC_9BITS, /**< ADC 9 bits */ + ADC_8BITS, /**< ADC 8 bits */ + ADC_7BITS, /**< ADC 7 bits */ + ADC_6BITS, /**< ADC 6 bits */ + ADC_5BITS, /**< ADC 5 bits */ + ADC_4BITS, /**< ADC 4 bits */ + ADC_3BITS, /**< ADC 3 bits */ +} ADC_Resolution; + +/** Edge configuration, which controls rising or falling edge on the selected signal for the start of a conversion */ +typedef enum ADC_EdgeCfg { + ADC_TRIGGERMODE_RISING = 0, /**< Trigger event: rising edge */ + ADC_TRIGGERMODE_FALLING, /**< Trigger event: falling edge */ +} ADC_EdgeCfg; + +/** Start mode, which controls the start of an A/D conversion when the BURST bit is 0. */ +typedef enum ADC_StartMode { + ADC_NO_START = 0, + ADC_START_NOW, /*!< Start conversion now */ + ADC_START_ON_CTOUT15, /*!< Start conversion when the edge selected by bit 27 occurs on CTOUT_15 */ + ADC_START_ON_CTOUT8, /*!< Start conversion when the edge selected by bit 27 occurs on CTOUT_8 */ + ADC_START_ON_ADCTRIG0, /*!< Start conversion when the edge selected by bit 27 occurs on ADCTRIG0 */ + ADC_START_ON_ADCTRIG1, /*!< Start conversion when the edge selected by bit 27 occurs on ADCTRIG1 */ + ADC_START_ON_MCOA2 /*!< Start conversion when the edge selected by bit 27 occurs on Motocon PWM output MCOA2 */ +} ADC_StartMode; + +/** Clock setup structure for ADC controller passed to the initialize function */ +typedef struct { + uint32_t adcPerClock; /*!< ADC peripheral Clock */ + uint32_t adcRate; /*!< ADC rate */ + uint8_t bitsAccuracy; /*!< ADC bit accuracy */ +} ADC_Clock_Setup_Type; + +/** + * @brief Read the ADC value from a channel + * @param pADC : The base of ADC peripheral on the chip + * @param channel : ADC channel to read + * @param data : Pointer to where to put data + * @return SUCCESS or ERROR if no conversion is ready + */ +STATIC INLINE Status Chip_ADC_Read_Value(LPC_ADC_Type *pADC, uint8_t channel, uint16_t *data) +{ + return IP_ADC_Get_Val(pADC, channel, data); +} + +/** + * @brief Read the ADC channel status + * @param pADC : The base of ADC peripheral on the chip + * @param channel : ADC channel to read + * @param StatusType : Status type of ADC_DR_* + * @return SET or RESET + */ +STATIC INLINE FlagStatus Chip_ADC_Read_Status(LPC_ADC_Type *pADC, uint8_t channel, uint32_t StatusType) +{ + return IP_ADC_GetStatus(pADC, channel, StatusType); +} + +/** + * @brief Enable/Disable interrupt for ADC channel + * @param pADC : The base of ADC peripheral on the chip + * @param channel : ADC channel to read + * @param NewState : New state, ENABLE or DISABLE + * @return SET or RESET + */ +STATIC INLINE void Chip_ADC_Channel_Int_Cmd(LPC_ADC_Type *pADC, uint8_t channel, FunctionalState NewState) +{ + IP_ADC_Int_Enable(pADC, channel, NewState); +} + +/** + * @brief Enable/Disable global interrupt for ADC channel + * @param pADC : The base of ADC peripheral on the chip + * @param NewState : New state, ENABLE or DISABLE + * @return Nothing + */ +STATIC INLINE void Chip_ADC_Global_Int_Cmd(LPC_ADC_Type *pADC, FunctionalState NewState) +{ + IP_ADC_Int_Enable(pADC, 8, NewState); +} + +/** + * @brief Shutdown ADC + * @param pADC : The base of ADC peripheral on the chip + * @return Nothing + */ +STATIC INLINE void Chip_ADC_DeInit(LPC_ADC_Type *pADC) +{ + IP_ADC_DeInit(pADC); +} + +/** + * @brief Initialize the ADC peripheral and the ADC setup structure to default value + * @param pADC : The base of ADC peripheral on the chip + * @param ADCSetup : ADC setup structure to be set + * @return Nothing + * Default setting for ADC is 400kHz - 10bits + */ +void Chip_ADC_Init(LPC_ADC_Type *pADC, ADC_Clock_Setup_Type *ADCSetup); + +/** + * @brief Select the mode starting the AD conversion + * @param pADC : The base of ADC peripheral on the chip + * @param mode : Stating mode, should be : + * - ADC_NO_START : Must be set for Burst mode + * - ADC_START_NOW : Start conversion now + * - ADC_START_ON_CTOUT15 : Start conversion when the edge selected by bit 27 occurs on CTOUT_15 + * - ADC_START_ON_CTOUT8 : Start conversion when the edge selected by bit 27 occurs on CTOUT_8 + * - ADC_START_ON_ADCTRIG0 : Start conversion when the edge selected by bit 27 occurs on ADCTRIG0 + * - ADC_START_ON_ADCTRIG1 : Start conversion when the edge selected by bit 27 occurs on ADCTRIG1 + * - ADC_START_ON_MCOA2 : Start conversion when the edge selected by bit 27 occurs on Motocon PWM output MCOA2 + * @param EdgeOption : Stating Edge Condition, should be : + * - ADC_TRIGGERMODE_RISING : Trigger event on rising edge + * - ADC_TRIGGERMODE_FALLING : Trigger event on falling edge + * @return Nothing + */ +void Chip_ADC_Set_StartMode(LPC_ADC_Type *pADC, ADC_StartMode mode, ADC_EdgeCfg EdgeOption); + +/** + * @brief Set the ADC Sample rate + * @param pADC : The base of ADC peripheral on the chip + * @param ADCSetup : ADC setup structure to be modified + * @param rate : Sample rate, should be set so the clock for A/D converter is less than or equal to 4.5MHz. + * @return Nothing + */ +void Chip_ADC_Set_SampleRate(LPC_ADC_Type *pADC, ADC_Clock_Setup_Type *ADCSetup, uint32_t rate); + +/** + * @brief Set the ADC accuracy bits + * @param pADC : The base of ADC peripheral on the chip + * @param ADCSetup : ADC setup structure to be modified + * @param resolution : The resolution, should be ADC_10BITS -> ADC_3BITS + * @return Nothing + */ +void Chip_ADC_Set_Resolution(LPC_ADC_Type *pADC, ADC_Clock_Setup_Type *ADCSetup, ADC_Resolution resolution); + +/** + * @brief Enable or disable the ADC channel on ADC peripheral + * @param pADC : The base of ADC peripheral on the chip + * @param channel : Channel to be enable or disable + * @param NewState : New state, should be: + * - ENABLE + * - DISABLE + * @return Nothing + */ +void Chip_ADC_Channel_Enable_Cmd(LPC_ADC_Type *pADC, ADC_Channel channel, FunctionalState NewState); + +/** + * @brief Enable burst mode + * @param pADC : The base of ADC peripheral on the chip + * @param NewState : New state, should be: + * - ENABLE + * - DISABLE + * @return Nothing + */ +void Chip_ADC_Burst_Cmd(LPC_ADC_Type *pADC, FunctionalState NewState); + +/** + * @brief Read the ADC value and convert it to 8bits value + * @param pADC : The base of ADC peripheral on the chip + * @param data : Storage for data + * @return Status : ERROR or SUCCESS + */ +Status Chip_ADC_Read_Byte(LPC_ADC_Type *pADC, uint8_t *data); + +/** + * @brief Set a channel to be read A/D data + * @param channel : Channel to be active + * @return Nothing + */ +void Chip_ADC_Active_Channel(uint8_t channel); + +/** + * @} + */ + +#ifdef __cplusplus +} +#endif + +#endif /* __ADC_18XX_43XX_H_ */ diff --git a/bsp/xplorer4330/libraries/lpc_chip/chip_18xx_43xx/atimer_18xx_43xx.c b/bsp/xplorer4330/libraries/lpc_chip/chip_18xx_43xx/atimer_18xx_43xx.c new file mode 100644 index 0000000000..b47595e7cf --- /dev/null +++ b/bsp/xplorer4330/libraries/lpc_chip/chip_18xx_43xx/atimer_18xx_43xx.c @@ -0,0 +1,55 @@ +/* + * @brief LPC18xx/43xx ATimer chip driver + * + * @note + * Copyright(C) NXP Semiconductors, 2012 + * All rights reserved. + * + * @par + * Software that is described herein is for illustrative purposes only + * which provides customers with programming information regarding the + * LPC products. This software is supplied "AS IS" without any warranties of + * any kind, and NXP Semiconductors and its licensor disclaim any and + * all warranties, express or implied, including all implied warranties of + * merchantability, fitness for a particular purpose and non-infringement of + * intellectual property rights. NXP Semiconductors assumes no responsibility + * or liability for the use of the software, conveys no license or rights under any + * patent, copyright, mask work right, or any other intellectual property rights in + * or to any products. NXP Semiconductors reserves the right to make changes + * in the software without notification. NXP Semiconductors also makes no + * representation or warranty that such application will be suitable for the + * specified use without further testing or modification. + * + * @par + * Permission to use, copy, modify, and distribute this software and its + * documentation is hereby granted, under NXP Semiconductors' and its + * licensor's relevant copyrights in the software, without fee, provided that it + * is used in conjunction with NXP Semiconductors microcontrollers. This + * copyright, permission, and disclaimer notice must appear in all copies of + * this code. + */ + +#include "atimer_18xx_43xx.h" + +/***************************************************************************** + * Private types/enumerations/variables + ****************************************************************************/ + +/***************************************************************************** + * Public types/enumerations/variables + ****************************************************************************/ + +/***************************************************************************** + * Private functions + ****************************************************************************/ + +/***************************************************************************** + * Public functions + ****************************************************************************/ + +/* Initialize Alarm Timer */ +void Chip_ATIMER_Init(uint32_t PresetValue) +{ + Chip_ATIMER_UpdatePresetValue(PresetValue); + Chip_ATIMER_ClearIntStatus(); +} diff --git a/bsp/xplorer4330/libraries/lpc_chip/chip_18xx_43xx/atimer_18xx_43xx.h b/bsp/xplorer4330/libraries/lpc_chip/chip_18xx_43xx/atimer_18xx_43xx.h new file mode 100644 index 0000000000..ca1c008a0e --- /dev/null +++ b/bsp/xplorer4330/libraries/lpc_chip/chip_18xx_43xx/atimer_18xx_43xx.h @@ -0,0 +1,117 @@ +/* + * @brief LPC18xx/43xx ATimer chip driver + * + * @note + * Copyright(C) NXP Semiconductors, 2012 + * All rights reserved. + * + * @par + * Software that is described herein is for illustrative purposes only + * which provides customers with programming information regarding the + * LPC products. This software is supplied "AS IS" without any warranties of + * any kind, and NXP Semiconductors and its licensor disclaim any and + * all warranties, express or implied, including all implied warranties of + * merchantability, fitness for a particular purpose and non-infringement of + * intellectual property rights. NXP Semiconductors assumes no responsibility + * or liability for the use of the software, conveys no license or rights under any + * patent, copyright, mask work right, or any other intellectual property rights in + * or to any products. NXP Semiconductors reserves the right to make changes + * in the software without notification. NXP Semiconductors also makes no + * representation or warranty that such application will be suitable for the + * specified use without further testing or modification. + * + * @par + * Permission to use, copy, modify, and distribute this software and its + * documentation is hereby granted, under NXP Semiconductors' and its + * licensor's relevant copyrights in the software, without fee, provided that it + * is used in conjunction with NXP Semiconductors microcontrollers. This + * copyright, permission, and disclaimer notice must appear in all copies of + * this code. + */ + +#ifndef __ATIMER_18XX_43XX_H_ +#define __ATIMER_18XX_43XX_H_ + +#include "chip.h" + +/** @defgroup ATIMER_18XX_43XX CHIP: LPC18xx/43xx ATimer Driver + * @ingroup CHIP_18XX_43XX_Drivers + * @{ + */ + +/** + * @brief Initialize Alarm Timer + * @param PresetValue Count of 1 to 1024s for Alarm + * @return None + */ +void Chip_ATIMER_Init(uint32_t PresetValue); + +/** + * @brief Close ATIMER device + * @return None + */ +STATIC INLINE void Chip_ATIMER_DeInit(void) +{ + IP_ATIMER_DeInit(LPC_ATIMER); +} + +/** + * @brief Enable ATIMER Interrupt + * @return None + */ +STATIC INLINE void Chip_ATIMER_IntEnable(void) +{ + IP_ATIMER_IntEnable(LPC_ATIMER); +} + +/** + * @brief Disable ATIMER Interrupt + * @return None + */ +STATIC INLINE void Chip_ATIMER_IntDisable(void) +{ + IP_ATIMER_IntDisable(LPC_ATIMER); +} + +/** + * @brief Clear ATIMER Interrupt Status + * @return None + */ +STATIC INLINE void Chip_ATIMER_ClearIntStatus(void) +{ + IP_ATIMER_ClearIntStatus(LPC_ATIMER); +} + +/** + * @brief Set ATIMER Interrupt Status + * @return None + */ +STATIC INLINE void Chip_ATIMER_SetIntStatus(void) +{ + IP_ATIMER_SetIntStatus(LPC_ATIMER); +} + +/** + * @brief Update Preset value + * @param PresetValue : updated preset value + * @return Nothing + */ +STATIC INLINE void Chip_ATIMER_UpdatePresetValue(uint32_t PresetValue) +{ + IP_ATIMER_UpdatePresetValue(LPC_ATIMER, PresetValue); +} + +/** + * @brief Read value of preset register + * @return Value of capture register + */ +STATIC INLINE uint32_t Chip_ATIMER_GetPresetValue(void) +{ + return IP_ATIMER_GetPresetValue(LPC_ATIMER); +} + +/** + * @} + */ + + #endif /* __ATIMER_18XX_43XX_H_ */ diff --git a/bsp/xplorer4330/libraries/lpc_chip/chip_18xx_43xx/cguccu_18xx_43xx.h b/bsp/xplorer4330/libraries/lpc_chip/chip_18xx_43xx/cguccu_18xx_43xx.h new file mode 100644 index 0000000000..964c564e47 --- /dev/null +++ b/bsp/xplorer4330/libraries/lpc_chip/chip_18xx_43xx/cguccu_18xx_43xx.h @@ -0,0 +1,104 @@ +/* + * @brief CGU/CCU registers and control functions + * + * @note + * Copyright(C) NXP Semiconductors, 2012 + * All rights reserved. + * + * @par + * Software that is described herein is for illustrative purposes only + * which provides customers with programming information regarding the + * LPC products. This software is supplied "AS IS" without any warranties of + * any kind, and NXP Semiconductors and its licensor disclaim any and + * all warranties, express or implied, including all implied warranties of + * merchantability, fitness for a particular purpose and non-infringement of + * intellectual property rights. NXP Semiconductors assumes no responsibility + * or liability for the use of the software, conveys no license or rights under any + * patent, copyright, mask work right, or any other intellectual property rights in + * or to any products. NXP Semiconductors reserves the right to make changes + * in the software without notification. NXP Semiconductors also makes no + * representation or warranty that such application will be suitable for the + * specified use without further testing or modification. + * + * @par + * Permission to use, copy, modify, and distribute this software and its + * documentation is hereby granted, under NXP Semiconductors' and its + * licensor's relevant copyrights in the software, without fee, provided that it + * is used in conjunction with NXP Semiconductors microcontrollers. This + * copyright, permission, and disclaimer notice must appear in all copies of + * this code. + */ + +#ifndef __CGUCCU_18XX_43XX_H_ +#define __CGUCCU_18XX_43XX_H_ + +#include "cmsis.h" +#include "chip_clocks.h" + +#ifdef __cplusplus +extern "C" { +#endif + +/** @ingroup CLOCK_18XX_43XX + * @{ + */ + +/** + * @brief LPC18XX/43XX CGU register block structure + */ +typedef struct { /*!< (@ 0x40050000) CGU Structure */ + __I uint32_t RESERVED0[5]; + __IO uint32_t FREQ_MON; /*!< (@ 0x40050014) Frequency monitor register */ + __IO uint32_t XTAL_OSC_CTRL; /*!< (@ 0x40050018) Crystal oscillator control register */ + __I uint32_t PLL0USB_STAT; /*!< (@ 0x4005001C) PLL0 (USB) status register */ + __IO uint32_t PLL0USB_CTRL; /*!< (@ 0x40050020) PLL0 (USB) control register */ + __IO uint32_t PLL0USB_MDIV; /*!< (@ 0x40050024) PLL0 (USB) M-divider register */ + __IO uint32_t PLL0USB_NP_DIV; /*!< (@ 0x40050028) PLL0 (USB) N/P-divider register */ + __I uint32_t PLL0AUDIO_STAT; /*!< (@ 0x4005002C) PLL0 (audio) status register */ + __IO uint32_t PLL0AUDIO_CTRL; /*!< (@ 0x40050030) PLL0 (audio) control register */ + __IO uint32_t PLL0AUDIO_MDIV; /*!< (@ 0x40050034) PLL0 (audio) M-divider register */ + __IO uint32_t PLL0AUDIO_NP_DIV; /*!< (@ 0x40050038) PLL0 (audio) N/P-divider register */ + __IO uint32_t PLL0AUDIO_FRAC; /*!< (@ 0x4005003C) PLL0 (audio) */ + __I uint32_t PLL1_STAT; /*!< (@ 0x40050040) PLL1 status register */ + __IO uint32_t PLL1_CTRL; /*!< (@ 0x40050044) PLL1 control register */ + __IO uint32_t IDIV_CTRL[CLK_IDIV_LAST];/*!< (@ 0x40050048) Integer divider A-E control registers */ + __IO uint32_t BASE_CLK[CLK_BASE_LAST]; /*!< (@ 0x4005005C) Start of base clock registers */ +} LPC_CGU_T; + +/** + * @brief CCU clock config/status register pair + */ +typedef struct { + __IO uint32_t CFG; /*!< CCU clock configuration register */ + __I uint32_t STAT; /*!< CCU clock status register */ +} CCU_CFGSTAT_T; + +/** + * @brief CCU1 register block structure + */ +typedef struct { /*!< (@ 0x40051000) CCU1 Structure */ + __IO uint32_t PM; /*!< (@ 0x40051000) CCU1 power mode register */ + __I uint32_t BASE_STAT; /*!< (@ 0x40051004) CCU1 base clocks status register */ + __I uint32_t RESERVED0[62]; + CCU_CFGSTAT_T CLKCCU[CLK_CCU1_LAST]; /*!< (@ 0x40051100) Start of CCU1 clock registers */ +} LPC_CCU1_Type; + +/** + * @brief CCU2 register block structure + */ +typedef struct { /*!< (@ 0x40052000) CCU2 Structure */ + __IO uint32_t PM; /*!< (@ 0x40052000) Power mode register */ + __I uint32_t BASE_STAT; /*!< (@ 0x40052004) CCU base clocks status register */ + __I uint32_t RESERVED0[62]; + CCU_CFGSTAT_T CLKCCU[CLK_CCU2_LAST - CLK_CCU1_LAST]; /*!< (@ 0x40052100) Start of CCU2 clock registers */ +} LPC_CCU2_Type; + +/** + * @} + */ + +#ifdef __cplusplus +} +#endif + +#endif /* __CGUCCU_18XX_43XX_H_ */ diff --git a/bsp/xplorer4330/libraries/lpc_chip/chip_18xx_43xx/chip.h b/bsp/xplorer4330/libraries/lpc_chip/chip_18xx_43xx/chip.h new file mode 100644 index 0000000000..b64f2d111b --- /dev/null +++ b/bsp/xplorer4330/libraries/lpc_chip/chip_18xx_43xx/chip.h @@ -0,0 +1,44 @@ +/* + * @brief Chip inclusion selector file + * + * Copyright(C) NXP Semiconductors, 2012 + * All rights reserved. + * + * Software that is described herein is for illustrative purposes only + * which provides customers with programming information regarding the + * LPC products. This software is supplied "AS IS" without any warranties of + * any kind, and NXP Semiconductors and its licensor disclaim any and + * all warranties, express or implied, including all implied warranties of + * merchantability, fitness for a particular purpose and non-infringement of + * intellectual property rights. NXP Semiconductors assumes no responsibility + * or liability for the use of the software, conveys no license or rights under any + * patent, copyright, mask work right, or any other intellectual property rights in + * or to any products. NXP Semiconductors reserves the right to make changes + * in the software without notification. NXP Semiconductors also makes no + * representation or warranty that such application will be suitable for the + * specified use without further testing or modification. + * + * Permission to use, copy, modify, and distribute this software and its + * documentation is hereby granted, under NXP Semiconductors' and its + * licensor's relevant copyrights in the software, without fee, provided that it + * is used in conjunction with NXP Semiconductors microcontrollers. This + * copyright, permission, and disclaimer notice must appear in all copies of + * this code. + */ + +#ifndef __CHIP_H_ +#define __CHIP_H_ + +#include "sys_config.h" + +#if defined(CHIP_LPC18XX) +#include "chip_lpc18xx.h" + +#elif defined(CHIP_LPC43XX) +#include "chip_lpc43xx.h" + +#else +#error CHIP_LPC18XX or CHIP_LPC43XX must be defined +#endif + +#endif /* __CHIP_H_ */ diff --git a/bsp/xplorer4330/libraries/lpc_chip/chip_18xx_43xx/chip_18xx43xx.dox b/bsp/xplorer4330/libraries/lpc_chip/chip_18xx_43xx/chip_18xx43xx.dox new file mode 100644 index 0000000000..3af83bda0a --- /dev/null +++ b/bsp/xplorer4330/libraries/lpc_chip/chip_18xx_43xx/chip_18xx43xx.dox @@ -0,0 +1,51 @@ +/* + * @brief LPCOpen 18xx/43xx chip group page + * + * @note + * Copyright(C) NXP Semiconductors, 2012 + * All rights reserved. + * + * @par + * Software that is described herein is for illustrative purposes only + * which provides customers with programming information regarding the + * LPC products. This software is supplied "AS IS" without any warranties of + * any kind, and NXP Semiconductors and its licensor disclaim any and + * all warranties, express or implied, including all implied warranties of + * merchantability, fitness for a particular purpose and non-infringement of + * intellectual property rights. NXP Semiconductors assumes no responsibility + * or liability for the use of the software, conveys no license or rights under any + * patent, copyright, mask work right, or any other intellectual property rights in + * or to any products. NXP Semiconductors reserves the right to make changes + * in the software without notification. NXP Semiconductors also makes no + * representation or warranty that such application will be suitable for the + * specified use without further testing or modification. + * + * @par + * Permission to use, copy, modify, and distribute this software and its + * documentation is hereby granted, under NXP Semiconductors' and its + * licensor's relevant copyrights in the software, without fee, provided that it + * is used in conjunction with NXP Semiconductors microcontrollers. This + * copyright, permission, and disclaimer notice must appear in all copies of + * this code. + */ + +/** @defgroup CHIP_18XX_43XX_Drivers LPC18XX/43XX chip specific drivers + * @ingroup Chip_Drivers + * @{ + */ + +/** @defgroup CHIP_18XX_43XX_DRIVER_OPTIONS CHIP: LPC18XX/43XX Chip driver build time options + * Some chip drivers require build-time configuration. Using a build-time + * configuration option allows the driver to be smaller and faster. A + * build-time option is configured by the use of a definition passed to + * the compiler during the build. + * @{ + */ + +/** + * @} + */ + +/** + * @} + */ diff --git a/bsp/xplorer4330/libraries/lpc_chip/chip_18xx_43xx/chip_clocks.h b/bsp/xplorer4330/libraries/lpc_chip/chip_18xx_43xx/chip_clocks.h new file mode 100644 index 0000000000..59e4a95f47 --- /dev/null +++ b/bsp/xplorer4330/libraries/lpc_chip/chip_18xx_43xx/chip_clocks.h @@ -0,0 +1,252 @@ +/* + * @brief LPC18xx/43xx chip clock list used by CGU and CCU drivers + * + * @note + * Copyright(C) NXP Semiconductors, 2012 + * All rights reserved. + * + * @par + * Software that is described herein is for illustrative purposes only + * which provides customers with programming information regarding the + * LPC products. This software is supplied "AS IS" without any warranties of + * any kind, and NXP Semiconductors and its licensor disclaim any and + * all warranties, express or implied, including all implied warranties of + * merchantability, fitness for a particular purpose and non-infringement of + * intellectual property rights. NXP Semiconductors assumes no responsibility + * or liability for the use of the software, conveys no license or rights under any + * patent, copyright, mask work right, or any other intellectual property rights in + * or to any products. NXP Semiconductors reserves the right to make changes + * in the software without notification. NXP Semiconductors also makes no + * representation or warranty that such application will be suitable for the + * specified use without further testing or modification. + * + * @par + * Permission to use, copy, modify, and distribute this software and its + * documentation is hereby granted, under NXP Semiconductors' and its + * licensor's relevant copyrights in the software, without fee, provided that it + * is used in conjunction with NXP Semiconductors microcontrollers. This + * copyright, permission, and disclaimer notice must appear in all copies of + * this code. + */ + +#ifndef __CHIP_CLOCKS_H_ +#define __CHIP_CLOCKS_H_ + +#include "sys_config.h" + +#ifdef __cplusplus +extern "C" { +#endif + +/** @ingroup CLOCK_18XX_43XX + * @{ + */ + +/** + * @brief CGU clock input list + * These are possible input clocks for the CGU and can come + * from both external (crystal) and internal (PLL) sources. These + * clock inputs can be routed to the base clocks (@ref CGU_BASE_CLK_T). + */ +typedef enum { + CLKIN_32K, /*!< External 32KHz input */ + CLKIN_IRC, /*!< Internal IRC (12MHz) input */ + CLKIN_ENET_RX, /*!< External ENET_RX pin input */ + CLKIN_ENET_TX, /*!< External ENET_TX pin input */ + CLKIN_CLKIN, /*!< External GPCLKIN pin input */ + CLKIN_RESERVED1, + CLKIN_CRYSTAL, /*!< External (main) crystal pin input */ + CLKIN_USBPLL, /*!< Internal USB PLL input */ + CLKIN_AUDIOPLL, /*!< Internal Audio PLL input */ + CLKIN_MAINPLL, /*!< Internal Main PLL input */ + CLKIN_RESERVED2, + CLKIN_RESERVED3, + CLKIN_IDIVA, /*!< Internal divider A input */ + CLKIN_IDIVB, /*!< Internal divider B input */ + CLKIN_IDIVC, /*!< Internal divider C input */ + CLKIN_IDIVD, /*!< Internal divider D input */ + CLKIN_IDIVE, /*!< Internal divider E input */ + CLKINPUT_PD /*!< External 32KHz input */ +} CGU_CLKIN_T; + +/** + * @brief CGU base clocks + * CGU base clocks are clocks that are associated with a single input clock + * and are routed out to 1 or more peripherals. For example, the CLK_BASE_PERIPH + * clock can be configured to use the CLKIN_MAINPLL input clock, which will in + * turn route that clock to the CLK_PERIPH_BUS, CLK_PERIPH_CORE, and + * CLK_PERIPH_SGPIO periphral clocks. + */ +typedef enum { + CLK_BASE_SAFE, /*!< Base clock for WDT oscillator, IRC input only */ + CLK_BASE_USB0, /*!< Base USB clock for USB0, USB PLL input only */ +#if defined(CHIP_LPC43XX) + CLK_BASE_PERIPH, /*!< Base clock for SGPIO */ +#else + CLK_BASE_RESERVED1, +#endif + CLK_BASE_USB1, /*!< Base USB clock for USB1 */ + CLK_BASE_MX, /*!< Base clock for CPU core */ + CLK_BASE_SPIFI, /*!< Base clock for SPIFI */ +#if defined(CHIP_LPC43XX) + CLK_BASE_SPI, /*!< Base clock for SPI */ +#else + CLK_BASE_RESERVED2, +#endif + CLK_BASE_PHY_RX, /*!< Base clock for PHY RX */ + CLK_BASE_PHY_TX, /*!< Base clock for PHY TX */ + CLK_BASE_APB1, /*!< Base clock for APB1 group */ + CLK_BASE_APB3, /*!< Base clock for APB3 group */ + CLK_BASE_LCD, /*!< Base clock for LCD pixel clock */ +#if defined(CHIP_LPC43XX) + CLK_BASE_VADC, /*!< Base clock for VADC */ +#else + CLK_BASE_RESERVED3, +#endif + CLK_BASE_SDIO, /*!< Base clock for SDIO */ + CLK_BASE_SSP0, /*!< Base clock for SSP0 */ + CLK_BASE_SSP1, /*!< Base clock for SSP1 */ + CLK_BASE_UART0, /*!< Base clock for UART0 */ + CLK_BASE_UART1, /*!< Base clock for UART1 */ + CLK_BASE_UART2, /*!< Base clock for UART2 */ + CLK_BASE_UART3, /*!< Base clock for UART3 */ + CLK_BASE_OUT, /*!< Base clock for CLKOUT pin */ + CLK_BASE_RESERVED4, + CLK_BASE_RESERVED5, + CLK_BASE_RESERVED6, + CLK_BASE_RESERVED7, + CLK_BASE_APLL, /*!< Base clock for audio PLL */ + CLK_BASE_CGU_OUT0, /*!< Base clock for CGUOUT0 pin */ + CLK_BASE_CGU_OUT1, /*!< Base clock for CGUOUT1 pin */ + CLK_BASE_LAST, + CLK_BASE_NONE = CLK_BASE_LAST +} CGU_BASE_CLK_T; + +/** + * @brief CGU dividers + * CGU dividers provide an extra clock state where a specific clock can be + * divided before being routed to a peripheral group. A divider accepts an + * input clock and then divides it. To use the divided clock for a base clock + * group, use the divider as the input clock for the base clock (for example, + * use CLKIN_IDIVB, where CLKIN_MAINPLL might be the input into the divider). + */ +typedef enum { + CLK_IDIV_A, /*!< CGU clock divider A */ + CLK_IDIV_B, /*!< CGU clock divider B */ + CLK_IDIV_C, /*!< CGU clock divider A */ + CLK_IDIV_D, /*!< CGU clock divider D */ + CLK_IDIV_E, /*!< CGU clock divider E */ + CLK_IDIV_LAST +} CGU_IDIV_T; + +/** + * @brief Peripheral clocks + * Peripheral clocks are individual clocks routed to peripherals. Although + * multiple peripherals may share a same base clock, each peripheral's clock + * can be enabled or disabled individually. Some peripheral clocks also have + * additional dividers associated with them. + */ +typedef enum { + /* CCU1 clocks */ + CLK_APB3_BUS, /*!< APB3 bus clock from base clock CLK_BASE_APB3 */ + CLK_APB3_I2C1, /*!< I2C1 register/perigheral clock from base clock CLK_BASE_APB3 */ + CLK_APB3_DAC, /*!< DAC peripheral clock from base clock CLK_BASE_APB3 */ + CLK_APB3_ADC0, /*!< ADC0 register/perigheral clock from base clock CLK_BASE_APB3 */ + CLK_APB3_ADC1, /*!< ADC1 register/perigheral clock from base clock CLK_BASE_APB3 */ + CLK_APB3_CAN0, /*!< CAN0 register/perigheral clock from base clock CLK_BASE_APB3 */ + CLK_APB1_BUS = 32, /*!< APB1 bus clock clock from base clock CLK_BASE_APB1 */ + CLK_APB1_MOTOCON, /*!< Motor controller register/perigheral clock from base clock CLK_BASE_APB1 */ + CLK_APB1_I2C0, /*!< I2C0 register/perigheral clock from base clock CLK_BASE_APB1 */ + CLK_APB1_I2S, /*!< I2S register/perigheral clock from base clock CLK_BASE_APB1 */ + CLK_APB1_CAN1, /*!< CAN1 register/perigheral clock from base clock CLK_BASE_APB1 */ + CLK_SPIFI = 64, /*!< SPIFI SCKI input clock from base clock CLK_BASE_SPIFI */ + CLK_MX_BUS = 96, /*!< M3/M4 BUS core clock from base clock CLK_BASE_MX */ + CLK_MX_SPIFI, /*!< SPIFI register clock from base clock CLK_BASE_MX */ + CLK_MX_GPIO, /*!< GPIO register clock from base clock CLK_BASE_MX */ + CLK_MX_LCD, /*!< LCD register clock from base clock CLK_BASE_MX */ + CLK_MX_ETHERNET, /*!< ETHERNET register clock from base clock CLK_BASE_MX */ + CLK_MX_USB0, /*!< USB0 register clock from base clock CLK_BASE_MX */ + CLK_MX_EMC, /*!< EMC clock from base clock CLK_BASE_MX */ + CLK_MX_SDIO, /*!< SDIO register clock from base clock CLK_BASE_MX */ + CLK_MX_DMA, /*!< DMA register clock from base clock CLK_BASE_MX */ + CLK_MX_MXCORE, /*!< M3/M4 CPU core clock from base clock CLK_BASE_MX */ + RESERVED_ALIGN = CLK_MX_MXCORE + 3, + CLK_MX_SCT, /*!< SCT register clock from base clock CLK_BASE_MX */ + CLK_MX_USB1, /*!< USB1 register clock from base clock CLK_BASE_MX */ + CLK_MX_EMC_DIV, /*!< ENC divider clock from base clock CLK_BASE_MX */ + CLK_MX_FLASHA, /*!< FLASHA bank clock from base clock CLK_BASE_MX */ + CLK_MX_FLASHB, /*!< FLASHB bank clock from base clock CLK_BASE_MX */ +#if defined(CHIP_LPC43XX) + CLK_M4_M0APP, /*!< M0 app CPU core clock from base clock CLK_BASE_MX */ + CLK_MX_VADC, /*!< VADC clock from base clock CLK_BASE_MX */ +#else + CLK_RESERVED1, + CLK_RESERVED2, +#endif + CLK_MX_EEPROM, /*!< EEPROM clock from base clock CLK_BASE_MX */ + CLK_MX_WWDT = 128, /*!< WWDT register clock from base clock CLK_BASE_MX */ + CLK_MX_UART0, /*!< UART0 register clock from base clock CLK_BASE_MX */ + CLK_MX_UART1, /*!< UART1 register clock from base clock CLK_BASE_MX */ + CLK_MX_SSP0, /*!< SSP0 register clock from base clock CLK_BASE_MX */ + CLK_MX_TIMER0, /*!< TIMER0 register/perigheral clock from base clock CLK_BASE_MX */ + CLK_MX_TIMER1, /*!< TIMER1 register/perigheral clock from base clock CLK_BASE_MX */ + CLK_MX_SCU, /*!< SCU register/perigheral clock from base clock CLK_BASE_MX */ + CLK_MX_CREG, /*!< CREG clock from base clock CLK_BASE_MX */ + CLK_MX_RITIMER = 160, /*!< RITIMER register/perigheral clock from base clock CLK_BASE_MX */ + CLK_MX_UART2, /*!< UART3 register clock from base clock CLK_BASE_MX */ + CLK_MX_UART3, /*!< UART4 register clock from base clock CLK_BASE_MX */ + CLK_MX_TIMER2, /*!< TIMER2 register/perigheral clock from base clock CLK_BASE_MX */ + CLK_MX_TIMER3, /*!< TIMER3 register/perigheral clock from base clock CLK_BASE_MX */ + CLK_MX_SSP1, /*!< SSP1 register clock from base clock CLK_BASE_MX */ + CLK_MX_QEI, /*!< QEI register/perigheral clock from base clock CLK_BASE_MX */ +#if defined(CHIP_LPC43XX) + CLK_PERIPH_BUS = 192, /*!< Peripheral bus clock from base clock CLK_BASE_PERIPH */ + CLK_RESERVED3, + CLK_PERIPH_CORE, /*!< Peripheral core clock from base clock CLK_BASE_PERIPH */ + CLK_PERIPH_SGPIO, /*!< SGPIO clock from base clock CLK_BASE_PERIPH */ +#else + CLK_RESERVED3 = 192, + CLK_RESERVED3A, + CLK_RESERVED4, + CLK_RESERVED5, +#endif + CLK_USB0 = 224, /*!< USB0 clock from base clock CLK_BASE_USB0 */ + CLK_USB1 = 256, /*!< USB1 clock from base clock CLK_BASE_USB1 */ +#if defined(CHIP_LPC43XX) + CLK_SPI = 288, /*!< SPI clock from base clock CLK_BASE_SPI */ + CLK_VADC, /*!< VADC clock from base clock CLK_BASE_VADC */ +#else + CLK_RESERVED7 = 320, + CLK_RESERVED8, +#endif + CLK_CCU1_LAST, + + /* CCU2 clocks */ + CLK_CCU2_START, + CLK_APLL = CLK_CCU2_START, /*!< Audio PLL clock from base clock CLK_BASE_APLL */ + RESERVED_ALIGNB = CLK_CCU2_START + 31, + CLK_APB2_UART3, /*!< UART3 clock from base clock CLK_BASE_UART3 */ + RESERVED_ALIGNC = CLK_CCU2_START + 63, + CLK_APB2_UART2, /*!< UART2 clock from base clock CLK_BASE_UART2 */ + RESERVED_ALIGND = CLK_CCU2_START + 95, + CLK_APB0_UART1, /*!< UART1 clock from base clock CLK_BASE_UART1 */ + RESERVED_ALIGNE = CLK_CCU2_START + 127, + CLK_APB0_UART0, /*!< UART0 clock from base clock CLK_BASE_UART0 */ + RESERVED_ALIGNF = CLK_CCU2_START + 159, + CLK_APB2_SSP1, /*!< SSP1 clock from base clock CLK_BASE_SSP1 */ + RESERVED_ALIGNG = CLK_CCU2_START + 191, + CLK_APB0_SSP0, /*!< SSP0 clock from base clock CLK_BASE_SSP0 */ + RESERVED_ALIGNH = CLK_CCU2_START + 223, + CLK_APB2_SDIO, /*!< SDIO clock from base clock CLK_BASE_SDIO */ + CLK_CCU2_LAST +} CCU_CLK_T; + +/** + * @} + */ + +#ifdef __cplusplus +} +#endif + +#endif /* __CHIP_CLOCKS_H_ */ diff --git a/bsp/xplorer4330/libraries/lpc_chip/chip_18xx_43xx/chip_lpc18xx.h b/bsp/xplorer4330/libraries/lpc_chip/chip_18xx_43xx/chip_lpc18xx.h new file mode 100644 index 0000000000..1a1fa71a22 --- /dev/null +++ b/bsp/xplorer4330/libraries/lpc_chip/chip_18xx_43xx/chip_lpc18xx.h @@ -0,0 +1,240 @@ +/* + * @brief LPC18xx basic chip inclusion file + * + * Copyright(C) NXP Semiconductors, 2012 + * All rights reserved. + * + * Software that is described herein is for illustrative purposes only + * which provides customers with programming information regarding the + * LPC products. This software is supplied "AS IS" without any warranties of + * any kind, and NXP Semiconductors and its licensor disclaim any and + * all warranties, express or implied, including all implied warranties of + * merchantability, fitness for a particular purpose and non-infringement of + * intellectual property rights. NXP Semiconductors assumes no responsibility + * or liability for the use of the software, conveys no license or rights under any + * patent, copyright, mask work right, or any other intellectual property rights in + * or to any products. NXP Semiconductors reserves the right to make changes + * in the software without notification. NXP Semiconductors also makes no + * representation or warranty that such application will be suitable for the + * specified use without further testing or modification. + * + * Permission to use, copy, modify, and distribute this software and its + * documentation is hereby granted, under NXP Semiconductors' and its + * licensor's relevant copyrights in the software, without fee, provided that it + * is used in conjunction with NXP Semiconductors microcontrollers. This + * copyright, permission, and disclaimer notice must appear in all copies of + * this code. + */ + +#ifndef __CHIP_LPC18XX_H_ +#define __CHIP_LPC18XX_H_ + +#ifdef __cplusplus +extern "C" { +#endif + +#include "lpc_types.h" +#include "sys_config.h" + +#ifndef CORE_M3 +#error CORE_M3 is not defined for the LPC18xx architecture +#error CORE_M3 should be defined as part of your compiler define list +#endif + +#ifndef CHIP_LPC18XX +#error The LPC18XX Chip include path is used for this build, but +#error CHIP_LPC18XX is not defined! +#endif + +#include "adc_001.h" +#include "atimer_001.h" +#include "ccan_001.h" +#include "dac_001.h" +#include "emc_001.h" +#include "enet_001.h" +#include "gima_001.h" +#include "gpdma_001.h" +#include "gpiogrpint_001.h" +#include "gpiopinint_001.h" +#include "gpio_001.h" +#include "i2c_001.h" +#include "i2s_001.h" +#include "lcd_001.h" +#include "mcpwm_001.h" +#include "pmc_001.h" +#include "qei_001.h" +#include "regfile_001.h" +#include "ritimer_001.h" +#include "rtc_001.h" +#include "sct_001.h" +#include "sdmmc_001.h" +#include "ssp_001.h" +#include "timer_001.h" +#include "usart_001.h" +#include "usbhs_001.h" +#include "wwdt_001.h" +#include "spifi_001.h" +#include "rgu_18xx_43xx.h" +#include "cguccu_18xx_43xx.h" + +/** @defgroup PERIPH_18XX_BASE CHIP: LPC18xx Peripheral addresses and register set declarations + * @ingroup CHIP_18XX_43XX_Drivers + * @{ + */ + +#define LPC_SCT_BASE 0x40000000 +#define LPC_GPDMA_BASE 0x40002000 +#define LPC_SDMMC_BASE 0x40004000 +#define LPC_EMC_BASE 0x40005000 +#define LPC_USB0_BASE 0x40006000 +#define LPC_USB1_BASE 0x40007000 +#define LPC_LCD_BASE 0x40008000 +#define LPC_ETHERNET_BASE 0x40010000 +#define LPC_ATIMER_BASE 0x40040000 +#define LPC_REGFILE_BASE 0x40041000 +#define LPC_PMC_BASE 0x40042000 +#define LPC_CREG_BASE 0x40043000 +#define LPC_EVRT_BASE 0x40044000 +#define LPC_RTC_BASE 0x40046000 +#define LPC_CGU_BASE 0x40050000 +#define LPC_CCU1_BASE 0x40051000 +#define LPC_CCU2_BASE 0x40052000 +#define LPC_RGU_BASE 0x40053000 +#define LPC_WWDT_BASE 0x40080000 +#define LPC_USART0_BASE 0x40081000 +#define LPC_USART2_BASE 0x400C1000 +#define LPC_USART3_BASE 0x400C2000 +#define LPC_UART1_BASE 0x40082000 +#define LPC_SSP0_BASE 0x40083000 +#define LPC_SSP1_BASE 0x400C5000 +#define LPC_TIMER0_BASE 0x40084000 +#define LPC_TIMER1_BASE 0x40085000 +#define LPC_TIMER2_BASE 0x400C3000 +#define LPC_TIMER3_BASE 0x400C4000 +#define LPC_SCU_BASE 0x40086000 +#define LPC_GPIO_PIN_INT_BASE 0x40087000 +#define LPC_GPIO_GROUP_INT0_BASE 0x40088000 +#define LPC_GPIO_GROUP_INT1_BASE 0x40089000 +#define LPC_MCPWM_BASE 0x400A0000 +#define LPC_I2C0_BASE 0x400A1000 +#define LPC_I2C1_BASE 0x400E0000 +#define LPC_I2S0_BASE 0x400A2000 +#define LPC_I2S1_BASE 0x400A3000 +#define LPC_C_CAN1_BASE 0x400A4000 +#define LPC_RITIMER_BASE 0x400C0000 +#define LPC_QEI_BASE 0x400C6000 +#define LPC_GIMA_BASE 0x400C7000 +#define LPC_DAC_BASE 0x400E1000 +#define LPC_C_CAN0_BASE 0x400E2000 +#define LPC_ADC0_BASE 0x400E3000 +#define LPC_ADC1_BASE 0x400E4000 +#define LPC_GPIO_PORT_BASE 0x400F4000 +#define LPC_SPI_BASE 0x40100000 +#define LPC_SGPIO_BASE 0x40101000 + +/* Normalize types */ +typedef IP_SCT_001_Type LPC_SCT_Type; +typedef IP_GPDMA_001_Type LPC_GPDMA_Type; +typedef IP_SDMMC_001_Type LPC_SDMMC_Type; +typedef IP_EMC_001_Type LPC_EMC_Type; +typedef IP_USBHS_001_Type LPC_USBHS_Type; +typedef IP_ENET_001_Type LPC_ENET_Type; +typedef IP_ATIMER_001_Type LPC_ATIMER_Type; +typedef IP_REGFILE_001_T LPC_REGFILE_T; +typedef IP_PMC_001_Type LPC_PMC_Type; +typedef IP_RTC_001_T LPC_RTC_Type; +typedef IP_WWDT_001_Type LPC_WWDT_Type; +typedef IP_USART_001_Type LPC_USART_Type; +typedef IP_SSP_001_Type LPC_SSP_Type; +typedef IP_TIMER_001_Type LPC_TIMER_Type; +typedef IP_GPIOPININT_001_Type LPC_GPIOPININT_Type; +typedef IP_MCPWM_001_Type LPC_MCPWM_Type; +typedef IP_I2C_001_Type LPC_I2C_Type; +typedef IP_I2S_001_Type LPC_I2S_Type; +typedef IP_CCAN_001_Type LPC_CCAN_Type; +typedef IP_RITIMER_001_Type LPC_RITIMER_Type; +typedef IP_QEI_001_Type LPC_QEI_Type; +typedef IP_GIMA_001_Type LPC_GIMA_Type; +typedef IP_DAC_001_Type LPC_DAC_Type; +typedef IP_ADC_001_Type LPC_ADC_Type; +typedef IP_GPIO_001_Type LPC_GPIO_Type; +typedef IP_LCD_001_Type LPC_LCD_Type; + +#define LPC_SCT ((IP_SCT_001_Type *) LPC_SCT_BASE) +#define LPC_GPDMA ((IP_GPDMA_001_Type *) LPC_GPDMA_BASE) +#define LPC_SDMMC ((IP_SDMMC_001_Type *) LPC_SDMMC_BASE) +#define LPC_EMC ((IP_EMC_001_Type *) LPC_EMC_BASE) +#define LPC_USB0 ((IP_USBHS_001_Type *) LPC_USB0_BASE) +#define LPC_USB1 ((IP_USBHS_001_Type *) LPC_USB1_BASE) +#define LPC_LCD ((IP_LCD_001_Type *) LPC_LCD_BASE) +#define LPC_ETHERNET ((IP_ENET_001_Type *) LPC_ETHERNET_BASE) +#define LPC_ATIMER ((IP_ATIMER_001_Type *) LPC_ATIMER_BASE) +#define LPC_REGFILE ((IP_REGFILE_001_T *) LPC_REGFILE_BASE) +#define LPC_PMC ((IP_PMC_001_Type *) LPC_PMC_BASE) +#define LPC_EVRT ((LPC_EVRT_Type *) LPC_EVRT_BASE) +#define LPC_RTC ((IP_RTC_001_T *) LPC_RTC_BASE) +#define LPC_CGU ((LPC_CGU_T *) LPC_CGU_BASE) +#define LPC_CCU1 ((LPC_CCU1_Type *) LPC_CCU1_BASE) +#define LPC_CCU2 ((LPC_CCU2_Type *) LPC_CCU2_BASE) +#define LPC_CREG ((LPC_CREG_T *) LPC_CREG_BASE) +#define LPC_RGU ((LPC_RGU_T *) LPC_RGU_BASE) +#define LPC_WWDT ((IP_WWDT_001_Type *) LPC_WWDT_BASE) +#define LPC_USART0 ((IP_USART_001_Type *) LPC_USART0_BASE) +#define LPC_USART2 ((IP_USART_001_Type *) LPC_USART2_BASE) +#define LPC_USART3 ((IP_USART_001_Type *) LPC_USART3_BASE) +#define LPC_UART1 ((IP_USART_001_Type *) LPC_UART1_BASE) +#define LPC_SSP0 ((IP_SSP_001_Type *) LPC_SSP0_BASE) +#define LPC_SSP1 ((IP_SSP_001_Type *) LPC_SSP1_BASE) +#define LPC_TIMER0 ((IP_TIMER_001_Type *) LPC_TIMER0_BASE) +#define LPC_TIMER1 ((IP_TIMER_001_Type *) LPC_TIMER1_BASE) +#define LPC_TIMER2 ((IP_TIMER_001_Type *) LPC_TIMER2_BASE) +#define LPC_TIMER3 ((IP_TIMER_001_Type *) LPC_TIMER3_BASE) +#define LPC_SCU ((LPC_SCU_Type *) LPC_SCU_BASE) +#define LPC_GPIO_PIN_INT ((IP_GPIOPININT_001_Type *) LPC_GPIO_PIN_INT_BASE) +#define LPC_GPIO_GROUP_INT0 ((IP_GPIOGROUPINT_001_Type *) LPC_GPIO_GROUP_INT0_BASE) +#define LPC_GPIO_GROUP_INT1 ((IP_GPIOGROUPINT_001_Type *) LPC_GPIO_GROUP_INT1_BASE) +#define LPC_MCPWM ((IP_MCPWM_001_Type *) LPC_MCPWM_BASE) +#define LPC_I2C0 ((IP_I2C_001_Type *) LPC_I2C0_BASE) +#define LPC_I2C1 ((IP_I2C_001_Type *) LPC_I2C1_BASE) +#define LPC_I2S0 ((IP_I2S_001_Type *) LPC_I2S0_BASE) +#define LPC_I2S1 ((IP_I2S_001_Type *) LPC_I2S1_BASE) +#define LPC_C_CAN1 ((IP_CCAN_001_Type *) LPC_C_CAN1_BASE) +#define LPC_RITIMER ((IP_RITIMER_001_Type *) LPC_RITIMER_BASE) +#define LPC_QEI ((IP_QEI_001_Type *) LPC_QEI_BASE) +#define LPC_GIMA ((IP_GIMA_001_Type *) LPC_GIMA_BASE) +#define LPC_DAC ((IP_DAC_001_Type *) LPC_DAC_BASE) +#define LPC_C_CAN0 ((IP_CCAN_001_Type *) LPC_C_CAN0_BASE) +#define LPC_ADC0 ((IP_ADC_001_Type *) LPC_ADC0_BASE) +#define LPC_ADC1 ((IP_ADC_001_Type *) LPC_ADC1_BASE) +#define LPC_GPIO_PORT ((IP_GPIO_001_Type *) LPC_GPIO_PORT_BASE) + +/** + * @} + */ + +#include "clock_18xx_43xx.h" +#include "gpio_18xx_43xx.h" +#include "uart_18xx_43xx.h" +#include "gpdma_18xx_43xx.h" +#include "enet_18xx_43xx.h" +#include "i2c_18xx_43xx.h" +#include "i2s_18xx_43xx.h" +#include "ssp_18xx_43xx.h" +#include "rtc_18xx_43xx.h" +#include "evrt_18xx_43xx.h" +#include "atimer_18xx_43xx.h" +#include "wwdt_18xx_43xx.h" +#include "ritimer_18xx_43xx.h" +#include "emc_18xx_43xx.h" +#include "lcd_18xx_43xx.h" +#include "adc_18xx_43xx.h" +#include "sdmmc_18xx_43xx.h" +#include "timer_18xx_43xx.h" +#include "creg_18xx_43xx.h" +#include "scu_18xx_43xx.h" + +#ifdef __cplusplus +} +#endif + +#endif /* __CHIP_LPC18XX_H_ */ diff --git a/bsp/xplorer4330/libraries/lpc_chip/chip_18xx_43xx/chip_lpc43xx.h b/bsp/xplorer4330/libraries/lpc_chip/chip_18xx_43xx/chip_lpc43xx.h new file mode 100644 index 0000000000..4e137f90f2 --- /dev/null +++ b/bsp/xplorer4330/libraries/lpc_chip/chip_18xx_43xx/chip_lpc43xx.h @@ -0,0 +1,248 @@ +/* + * @brief LPC43xx basic chip inclusion file + * + * Copyright(C) NXP Semiconductors, 2012 + * All rights reserved. + * + * Software that is described herein is for illustrative purposes only + * which provides customers with programming information regarding the + * LPC products. This software is supplied "AS IS" without any warranties of + * any kind, and NXP Semiconductors and its licensor disclaim any and + * all warranties, express or implied, including all implied warranties of + * merchantability, fitness for a particular purpose and non-infringement of + * intellectual property rights. NXP Semiconductors assumes no responsibility + * or liability for the use of the software, conveys no license or rights under any + * patent, copyright, mask work right, or any other intellectual property rights in + * or to any products. NXP Semiconductors reserves the right to make changes + * in the software without notification. NXP Semiconductors also makes no + * representation or warranty that such application will be suitable for the + * specified use without further testing or modification. + * + * Permission to use, copy, modify, and distribute this software and its + * documentation is hereby granted, under NXP Semiconductors' and its + * licensor's relevant copyrights in the software, without fee, provided that it + * is used in conjunction with NXP Semiconductors microcontrollers. This + * copyright, permission, and disclaimer notice must appear in all copies of + * this code. + */ + +#ifndef __CHIP_LPC43XX_H_ +#define __CHIP_LPC43XX_H_ + +#include "lpc_types.h" +#include "sys_config.h" + +#ifdef __cplusplus +extern "C" { +#endif + +#if !defined(CORE_M4) && !defined(CORE_M0) +#error CORE_M4 or CORE_M0 is not defined for the LPC43xx architecture +#error CORE_M4 or CORE_M0 should be defined as part of your compiler define list +#endif + +#ifndef CHIP_LPC43XX +#error The LPC43XX Chip include path is used for this build, but +#error CHIP_LPC43XX is not defined! +#endif + +#include "adc_001.h" +#include "atimer_001.h" +#include "ccan_001.h" +#include "dac_001.h" +#include "emc_001.h" +#include "enet_001.h" +#include "gima_001.h" +#include "gpdma_001.h" +#include "gpiogrpint_001.h" +#include "gpiopinint_001.h" +#include "gpio_001.h" +#include "i2c_001.h" +#include "i2s_001.h" +#include "lcd_001.h" +#include "mcpwm_001.h" +#include "pmc_001.h" +#include "qei_001.h" +#include "regfile_001.h" +#include "ritimer_001.h" +#include "rtc_001.h" +#include "sct_001.h" +#include "sdmmc_001.h" +#include "sgpio_001.h" +#include "spi_001.h" +#include "ssp_001.h" +#include "timer_001.h" +#include "usart_001.h" +#include "usbhs_001.h" +#include "wwdt_001.h" +#include "spifi_001.h" +#include "rgu_18xx_43xx.h" +#include "cguccu_18xx_43xx.h" + +/** @defgroup PERIPH_43XX_BASE CHIP: LPC43xx Peripheral addresses and register set declarations + * @ingroup CHIP_18XX_43XX_Drivers + * @{ + */ + +#define LPC_SCT_BASE 0x40000000 +#define LPC_GPDMA_BASE 0x40002000 +#define LPC_SDMMC_BASE 0x40004000 +#define LPC_EMC_BASE 0x40005000 +#define LPC_USB0_BASE 0x40006000 +#define LPC_USB1_BASE 0x40007000 +#define LPC_LCD_BASE 0x40008000 +#define LPC_ETHERNET_BASE 0x40010000 +#define LPC_ATIMER_BASE 0x40040000 +#define LPC_REGFILE_BASE 0x40041000 +#define LPC_PMC_BASE 0x40042000 +#define LPC_CREG_BASE 0x40043000 +#define LPC_EVRT_BASE 0x40044000 +#define LPC_RTC_BASE 0x40046000 +#define LPC_CGU_BASE 0x40050000 +#define LPC_CCU1_BASE 0x40051000 +#define LPC_CCU2_BASE 0x40052000 +#define LPC_RGU_BASE 0x40053000 +#define LPC_WWDT_BASE 0x40080000 +#define LPC_USART0_BASE 0x40081000 +#define LPC_USART2_BASE 0x400C1000 +#define LPC_USART3_BASE 0x400C2000 +#define LPC_UART1_BASE 0x40082000 +#define LPC_SSP0_BASE 0x40083000 +#define LPC_SSP1_BASE 0x400C5000 +#define LPC_TIMER0_BASE 0x40084000 +#define LPC_TIMER1_BASE 0x40085000 +#define LPC_TIMER2_BASE 0x400C3000 +#define LPC_TIMER3_BASE 0x400C4000 +#define LPC_SCU_BASE 0x40086000 +#define LPC_GPIO_PIN_INT_BASE 0x40087000 +#define LPC_GPIO_GROUP_INT0_BASE 0x40088000 +#define LPC_GPIO_GROUP_INT1_BASE 0x40089000 +#define LPC_MCPWM_BASE 0x400A0000 +#define LPC_I2C0_BASE 0x400A1000 +#define LPC_I2C1_BASE 0x400E0000 +#define LPC_I2S0_BASE 0x400A2000 +#define LPC_I2S1_BASE 0x400A3000 +#define LPC_C_CAN1_BASE 0x400A4000 +#define LPC_RITIMER_BASE 0x400C0000 +#define LPC_QEI_BASE 0x400C6000 +#define LPC_GIMA_BASE 0x400C7000 +#define LPC_DAC_BASE 0x400E1000 +#define LPC_C_CAN0_BASE 0x400E2000 +#define LPC_ADC0_BASE 0x400E3000 +#define LPC_ADC1_BASE 0x400E4000 +#define LPC_GPIO_PORT_BASE 0x400F4000 +#define LPC_SPI_BASE 0x40100000 +#define LPC_SGPIO_BASE 0x40101000 + +/* Normalize types */ +typedef IP_SCT_001_Type LPC_SCT_Type; +typedef IP_GPDMA_001_Type LPC_GPDMA_Type; +typedef IP_SDMMC_001_Type LPC_SDMMC_Type; +typedef IP_EMC_001_Type LPC_EMC_Type; +typedef IP_USBHS_001_Type LPC_USBHS_Type; +typedef IP_ENET_001_Type LPC_ENET_Type; +typedef IP_ATIMER_001_Type LPC_ATIMER_Type; +typedef IP_REGFILE_001_T LPC_REGFILE_Type; +typedef IP_PMC_001_Type LPC_PMC_Type; +typedef IP_RTC_001_T LPC_RTC_Type; +typedef IP_WWDT_001_Type LPC_WWDT_Type; +typedef IP_USART_001_Type LPC_USART_Type; +typedef IP_SSP_001_Type LPC_SSP_Type; +typedef IP_TIMER_001_Type LPC_TIMER_Type; +typedef IP_GPIOPININT_001_Type LPC_GPIOPININT_Type; +typedef IP_MCPWM_001_Type LPC_MCPWM_Type; +typedef IP_I2C_001_Type LPC_I2C_Type; +typedef IP_I2S_001_Type LPC_I2S_Type; +typedef IP_CCAN_001_Type LPC_CCAN_Type; +typedef IP_RITIMER_001_Type LPC_RITIMER_Type; +typedef IP_QEI_001_Type LPC_QEI_Type; +typedef IP_GIMA_001_Type LPC_GIMA_Type; +typedef IP_DAC_001_Type LPC_DAC_Type; +typedef IP_ADC_001_Type LPC_ADC_Type; +typedef IP_GPIO_001_Type LPC_GPIO_Type; +typedef IP_SPI_001_Type LPC_SPI_Type; +typedef IP_SGPIO_001_Type LPC_SGPIO_Type; +typedef IP_LCD_001_Type LPC_LCD_Type; + +#define LPC_SCT ((IP_SCT_001_Type *) LPC_SCT_BASE) +#define LPC_GPDMA ((IP_GPDMA_001_Type *) LPC_GPDMA_BASE) +#define LPC_SDMMC ((IP_SDMMC_001_Type *) LPC_SDMMC_BASE) +#define LPC_EMC ((IP_EMC_001_Type *) LPC_EMC_BASE) +#define LPC_USB0 ((IP_USBHS_001_Type *) LPC_USB0_BASE) +#define LPC_USB1 ((IP_USBHS_001_Type *) LPC_USB1_BASE) +#define LPC_LCD ((IP_LCD_001_Type *) LPC_LCD_BASE) +#define LPC_ETHERNET ((IP_ENET_001_Type *) LPC_ETHERNET_BASE) +#define LPC_ATIMER ((IP_ATIMER_001_Type *) LPC_ATIMER_BASE) +#define LPC_REGFILE ((IP_REGFILE_001_T *) LPC_REGFILE_BASE) +#define LPC_PMC ((IP_PMC_001_Type *) LPC_PMC_BASE) +#define LPC_EVRT ((LPC_EVRT_Type *) LPC_EVRT_BASE) +#define LPC_RTC ((IP_RTC_001_T *) LPC_RTC_BASE) +#define LPC_CGU ((LPC_CGU_T *) LPC_CGU_BASE) +#define LPC_CCU1 ((LPC_CCU1_Type *) LPC_CCU1_BASE) +#define LPC_CCU2 ((LPC_CCU2_Type *) LPC_CCU2_BASE) +#define LPC_CREG ((LPC_CREG_T *) LPC_CREG_BASE) +#define LPC_RGU ((LPC_RGU_T *) LPC_RGU_BASE) +#define LPC_WWDT ((IP_WWDT_001_Type *) LPC_WWDT_BASE) +#define LPC_USART0 ((IP_USART_001_Type *) LPC_USART0_BASE) +#define LPC_USART2 ((IP_USART_001_Type *) LPC_USART2_BASE) +#define LPC_USART3 ((IP_USART_001_Type *) LPC_USART3_BASE) +#define LPC_UART1 ((IP_USART_001_Type *) LPC_UART1_BASE) +#define LPC_SSP0 ((IP_SSP_001_Type *) LPC_SSP0_BASE) +#define LPC_SSP1 ((IP_SSP_001_Type *) LPC_SSP1_BASE) +#define LPC_TIMER0 ((IP_TIMER_001_Type *) LPC_TIMER0_BASE) +#define LPC_TIMER1 ((IP_TIMER_001_Type *) LPC_TIMER1_BASE) +#define LPC_TIMER2 ((IP_TIMER_001_Type *) LPC_TIMER2_BASE) +#define LPC_TIMER3 ((IP_TIMER_001_Type *) LPC_TIMER3_BASE) +#define LPC_SCU ((LPC_SCU_Type *) LPC_SCU_BASE) +#define LPC_GPIO_PIN_INT ((IP_GPIOPININT_001_Type *) LPC_GPIO_PIN_INT_BASE) +#define LPC_GPIO_GROUP_INT0 ((IP_GPIOGROUPINT_001_Type *) LPC_GPIO_GROUP_INT0_BASE) +#define LPC_GPIO_GROUP_INT1 ((IP_GPIOGROUPINT_001_Type *) LPC_GPIO_GROUP_INT1_BASE) +#define LPC_MCPWM ((IP_MCPWM_001_Type *) LPC_MCPWM_BASE) +#define LPC_I2C0 ((IP_I2C_001_Type *) LPC_I2C0_BASE) +#define LPC_I2C1 ((IP_I2C_001_Type *) LPC_I2C1_BASE) +#define LPC_I2S0 ((IP_I2S_001_Type *) LPC_I2S0_BASE) +#define LPC_I2S1 ((IP_I2S_001_Type *) LPC_I2S1_BASE) +#define LPC_C_CAN1 ((IP_CCAN_001_Type *) LPC_C_CAN1_BASE) +#define LPC_RITIMER ((IP_RITIMER_001_Type *) LPC_RITIMER_BASE) +#define LPC_QEI ((IP_QEI_001_Type *) LPC_QEI_BASE) +#define LPC_GIMA ((IP_GIMA_001_Type *) LPC_GIMA_BASE) +#define LPC_DAC ((IP_DAC_001_Type *) LPC_DAC_BASE) +#define LPC_C_CAN0 ((IP_CCAN_001_Type *) LPC_C_CAN0_BASE) +#define LPC_ADC0 ((IP_ADC_001_Type *) LPC_ADC0_BASE) +#define LPC_ADC1 ((IP_ADC_001_Type *) LPC_ADC1_BASE) +#define LPC_GPIO_PORT ((IP_GPIO_001_Type *) LPC_GPIO_PORT_BASE) +#define LPC_SPI ((IP_SPI_001_Type *) LPC_SPI_BASE) +#define LPC_SGPIO ((IP_SGPIO_001_Type *) LPC_SGPIO_BASE) + +/** + * @} + */ + +#include "clock_18xx_43xx.h" +#include "gpio_18xx_43xx.h" +#include "scu_18xx_43xx.h" +#include "uart_18xx_43xx.h" +#include "gpdma_18xx_43xx.h" +#include "enet_18xx_43xx.h" +#include "rgu_18xx_43xx.h" +#include "i2c_18xx_43xx.h" +#include "i2s_18xx_43xx.h" +#include "ssp_18xx_43xx.h" +#include "rtc_18xx_43xx.h" +#include "evrt_18xx_43xx.h" +#include "atimer_18xx_43xx.h" +#include "wwdt_18xx_43xx.h" +#include "ritimer_18xx_43xx.h" +#include "emc_18xx_43xx.h" +#include "lcd_18xx_43xx.h" +#include "adc_18xx_43xx.h" +#include "timer_18xx_43xx.h" +#include "sdmmc_18xx_43xx.h" +#include "fpu_init.h" +#include "creg_18xx_43xx.h" + +#ifdef __cplusplus +} +#endif + +#endif /* __CHIP_LPC43XX_H_ */ diff --git a/bsp/xplorer4330/libraries/lpc_chip/chip_18xx_43xx/clock_18xx_43xx.c b/bsp/xplorer4330/libraries/lpc_chip/chip_18xx_43xx/clock_18xx_43xx.c new file mode 100644 index 0000000000..dfc416efdb --- /dev/null +++ b/bsp/xplorer4330/libraries/lpc_chip/chip_18xx_43xx/clock_18xx_43xx.c @@ -0,0 +1,576 @@ +/* + * @brief LPC18xx/43xx clock driver + * + * @note + * Copyright(C) NXP Semiconductors, 2012 + * All rights reserved. + * + * @par + * Software that is described herein is for illustrative purposes only + * which provides customers with programming information regarding the + * LPC products. This software is supplied "AS IS" without any warranties of + * any kind, and NXP Semiconductors and its licenser disclaim any and + * all warranties, express or implied, including all implied warranties of + * merchantability, fitness for a particular purpose and non-infringement of + * intellectual property rights. NXP Semiconductors assumes no responsibility + * or liability for the use of the software, conveys no license or rights under any + * patent, copyright, mask work right, or any other intellectual property rights in + * or to any products. NXP Semiconductors reserves the right to make changes + * in the software without notification. NXP Semiconductors also makes no + * representation or warranty that such application will be suitable for the + * specified use without further testing or modification. + * + * @par + * Permission to use, copy, modify, and distribute this software and its + * documentation is hereby granted, under NXP Semiconductors' and its + * licensor's relevant copyrights in the software, without fee, provided that it + * is used in conjunction with NXP Semiconductors microcontrollers. This + * copyright, permission, and disclaimer notice must appear in all copies of + * this code. + */ + +#include "clock_18xx_43xx.h" + +/***************************************************************************** + * Private types/enumerations/variables + ****************************************************************************/ + +/* Maps a peripheral clock to it's base clock */ +typedef struct { + CCU_CLK_T clkstart; + CCU_CLK_T clkend; + CGU_BASE_CLK_T clkbase; +} CLK_PERIPH_TO_BASE_T; +static const CLK_PERIPH_TO_BASE_T periph_to_base[] = { + {CLK_APB3_BUS, CLK_APB3_CAN0, CLK_BASE_APB3}, + {CLK_APB1_BUS, CLK_APB1_CAN1, CLK_BASE_APB1}, + {CLK_SPIFI, CLK_SPIFI, CLK_BASE_SPIFI}, + {CLK_MX_BUS, CLK_MX_QEI, CLK_BASE_MX}, +#if 0 +#if defined(CHIP_LPC43XX) + {CLK_PERIPH_BUS, CLK_PERIPH_SGPIO, CLK_BASE_PERIPH}, +#endif + {CLK_USB0, CLK_USB0, CLK_BASE_USB0}, + {CLK_USB1, CLK_USB1, CLK_BASE_USB1}, +#if defined(CHIP_LPC43XX) + {CLK_SPI, CLK_SPI, CLK_BASE_SPI}, + {CLK_VADC, CLK_VADC, CLK_BASE_VADC}, +#endif + {CLK_APLL, CLK_APLL, CLK_BASE_APLL}, + {CLK_APB2_UART3, CLK_APB2_UART3, CLK_BASE_UART3}, + {CLK_APB2_UART2, CLK_APB2_UART2, CLK_BASE_UART2}, + {CLK_APB2_UART1, CLK_APB2_UART1, CLK_BASE_UART1}, + {CLK_APB2_UART0, CLK_APB2_UART0, CLK_BASE_UART0}, + {CLK_APB2_SSP1, CLK_APB2_SSP1, CLK_BASE_SSP1}, + {CLK_APB2_SSP0, CLK_APB2_SSP0, CLK_BASE_SSP0}, + {CLK_APB2_SDIO, CLK_APB2_SDIO, CLK_BASE_SDIO}, + {CLK_CCU2_LAST, CLK_CCU2_LAST, CLK_BASE_NONE} +#endif +}; + +/***************************************************************************** + * Public types/enumerations/variables + ****************************************************************************/ + +/***************************************************************************** + * Private functions + ****************************************************************************/ + +/* Test PLL input values for a specific frequency range */ +static uint32_t Chip_Clock_TestMainPLLMultiplier(uint32_t InputHz, uint32_t TestMult, uint32_t MinHz, uint32_t MaxHz) +{ + uint32_t TestHz = TestMult * InputHz; + + if ((TestHz < MinHz) || (TestHz > MAX_CLOCK_FREQ) || (TestHz > MaxHz)) { + TestHz = 0; + } + + return TestHz; +} + +/* Returns clock rate out of a divider */ +static uint32_t Chip_Clock_GetDivRate(CGU_CLKIN_T clock, CGU_IDIV_T divider) +{ + CGU_CLKIN_T input; + uint32_t div; + + input = Chip_Clock_GetDividerSource(divider); + div = Chip_Clock_GetDividerDivisor(divider); + return Chip_Clock_GetClockInputHz(input) / (div + 1); +} + +/* Finds the base clock for the peripheral clock */ +static CGU_BASE_CLK_T Chip_Clock_FindBseClock(CCU_CLK_T clk) +{ + CGU_BASE_CLK_T baseclk = CLK_BASE_NONE; + int i = 0; + + while ((baseclk == CLK_BASE_NONE) && (periph_to_base[i].clkbase != baseclk)) { + if ((clk >= periph_to_base[i].clkstart) && (clk <= periph_to_base[i].clkend)) { + baseclk = periph_to_base[i].clkbase; + } + else { + i++; + } + } + + return baseclk; +} + +/***************************************************************************** + * Public functions + ****************************************************************************/ + +/* Enables the crystal oscillator */ +void Chip_Clock_EnableCrystal(void) +{ + uint32_t OldCrystalConfig = LPC_CGU->XTAL_OSC_CTRL; + + /* Clear bypass mode */ + OldCrystalConfig &= (~2); + if (OldCrystalConfig != LPC_CGU->XTAL_OSC_CTRL) { + LPC_CGU->XTAL_OSC_CTRL = OldCrystalConfig; + } + + /* Enable crystal oscillator */ + OldCrystalConfig &= (~1); + if (CRYSTAL_MAIN_FREQ_IN >= 20000000) { + OldCrystalConfig |= 4; /* Set high frequency mode */ + + } + LPC_CGU->XTAL_OSC_CTRL = OldCrystalConfig; +} + +/* Disables the crystal oscillator */ +void IP_Clock_DisableCrystal(void) +{ + /* Disable crystal oscillator */ + LPC_CGU->XTAL_OSC_CTRL &= (~1); +} + +/* Configures the main PLL */ +uint32_t Chip_Clock_SetupMainPLLHz(CGU_CLKIN_T Input, uint32_t MinHz, uint32_t DesiredHz, uint32_t MaxHz) +{ + uint32_t freqin = Chip_Clock_GetClockInputHz(Input); + uint32_t Mult, LastMult, MultEnd; + uint32_t freqout, freqout2; + + if (DesiredHz != 0xFFFFFFFF) { + /* Test DesiredHz rounded down */ + Mult = DesiredHz / freqin; + freqout = Chip_Clock_TestMainPLLMultiplier(freqin, Mult, MinHz, MaxHz); + + /* Test DesiredHz rounded up */ + Mult++; + freqout2 = Chip_Clock_TestMainPLLMultiplier(freqin, Mult, MinHz, MaxHz); + + if (freqout && !freqout2) { /* rounding up is no good? set first multiplier */ + Mult--; + return Chip_Clock_SetupMainPLLMult(Input, Mult); + } + if (!freqout && freqout2) { /* didn't work until rounded up? set 2nd multiplier */ + return Chip_Clock_SetupMainPLLMult(Input, Mult); + } + + if (freqout && freqout2) { /* either multiplier okay? choose closer one */ + if ((DesiredHz - freqout) > (freqout2 - DesiredHz)) { + Mult--; + return Chip_Clock_SetupMainPLLMult(Input, Mult); + } + else { + return Chip_Clock_SetupMainPLLMult(Input, Mult); + } + } + } + + /* Neither multiplier okay? Try to start at MinHz and increment. + This should find the highest multiplier that is still good */ + Mult = MinHz / freqin; + MultEnd = MaxHz / freqin; + LastMult = 0; + while (1) { + freqout = Chip_Clock_TestMainPLLMultiplier(freqin, Mult, MinHz, MaxHz); + + if (freqout) { + LastMult = Mult; + } + + if (Mult >= MultEnd) { + break; + } + Mult++; + } + + if (LastMult) { + return Chip_Clock_SetupMainPLLMult(Input, LastMult); + } + + return 0; +} + +/* Directly set the PLL multipler */ +uint32_t Chip_Clock_SetupMainPLLMult(CGU_CLKIN_T Input, uint32_t mult) +{ + uint32_t freq = Chip_Clock_GetClockInputHz(Input); + uint32_t msel = 0, nsel = 0, psel = 0, pval = 1; + uint32_t PLLReg = LPC_CGU->PLL1_CTRL; + + freq *= mult; + msel = mult - 1; + + PLLReg &= ~(0x1F << 24);/* clear input source bits */ + PLLReg |= Input << 24; /* set input source bits to parameter */ + + /* Clear other PLL input bits */ + PLLReg &= ~((1 << 6) | /* FBSEL */ + (1 << 1) | /* BYPASS */ + (1 << 7) | /* DIRECT */ + (0x03 << 8) | (0xFF << 16) | (0x03 << 12)); /* PSEL, MSEL, NSEL- divider ratios */ + + if (freq < 156000000) { + /* psel is encoded such that 0=1, 1=2, 2=4, 3=8 */ + while ((2 * (pval) * freq) < 156000000) { + psel++; + pval *= 2; + } + + PLLReg |= (msel << 16) | (nsel << 12) | (psel << 8) | (1 << 6); /* dividers + FBSEL */ + } + else if (freq < 320000000) { + PLLReg |= (msel << 16) | (nsel << 12) | (psel << 8) | (1 << 7) | (1 << 6); /* dividers + DIRECT + FBSEL */ + } + else { + Chip_Clock_DisableMainPLL(); + return 0; + } + LPC_CGU->PLL1_CTRL = PLLReg & ~(1 << 0); + + return freq; +} + +/* Returns the frequency of the main PLL */ +uint32_t Chip_Clock_GetMainPLLHz(void) +{ + uint32_t PLLReg = LPC_CGU->PLL1_CTRL; + uint32_t freq = Chip_Clock_GetClockInputHz((CGU_CLKIN_T) ((PLLReg >> 24) & 0xF)); + uint32_t msel, nsel, psel, direct, fbsel; + uint32_t m, n, p; + const uint8_t ptab[] = {1, 2, 4, 8}; + + /* No lock? */ + if (!(LPC_CGU->PLL1_STAT & 1)) { + return 0; + } + + msel = (PLLReg >> 16) & 0xFF; + nsel = (PLLReg >> 12) & 0x3; + psel = (PLLReg >> 8) & 0x3; + direct = (PLLReg >> 7) & 0x1; + fbsel = (PLLReg >> 6) & 0x1; + + m = msel + 1; + n = nsel + 1; + p = ptab[psel]; + + if (direct || fbsel) { + return m * (freq / n); + } + + return (m / (2 * p)) * (freq / n); +} + +/* Disables the main PLL */ +void Chip_Clock_DisableMainPLL(void) +{ + /* power down main PLL */ + LPC_CGU->PLL1_CTRL |= 1; +} + +/* Returns the lock status of the main PLL */ +bool Chip_Clock_MainPLLLocked(void) +{ + /* Return true if locked */ + return (bool) (LPC_CGU->PLL1_STAT & 1); +} + +/* Sets up a CGU clock divider and it's input clock */ +void Chip_Clock_SetDivider(CGU_IDIV_T Divider, CGU_CLKIN_T Input, uint32_t Divisor) +{ + uint32_t reg = LPC_CGU->IDIV_CTRL[Divider]; + + Divisor--; + + if (Input != CLKINPUT_PD) { + /* Mask off bits that need to changes */ + reg &= ~((0x1F << 24) | 1 | (0xF << 2)); + + /* Enable autoblocking, clear PD, and set clock source & divisor */ + LPC_CGU->IDIV_CTRL[Divider] = reg | (1 << 11) | (Input << 24) | (Divisor << 2); + } + else { + LPC_CGU->IDIV_CTRL[Divider] = reg | 1; /* Power down this divider */ + } +} + +/* Gets a CGU clock divider source */ +CGU_CLKIN_T Chip_Clock_GetDividerSource(CGU_IDIV_T Divider) +{ + uint32_t reg = LPC_CGU->IDIV_CTRL[Divider]; + + if (reg & 1) { /* divider is powered down */ + return CLKINPUT_PD; + } + + return (CGU_CLKIN_T) ((reg >> 24) & 0x1F); +} + +/* Gets a CGU clock divider divisor */ +uint32_t Chip_Clock_GetDividerDivisor(CGU_IDIV_T Divider) +{ + return (CGU_CLKIN_T) ((LPC_CGU->IDIV_CTRL[Divider] >> 2) & 0xF); +} + +/* Returns the frequency of the specified input clock source */ +uint32_t Chip_Clock_GetClockInputHz(CGU_CLKIN_T input) +{ + uint32_t rate = 0; + + switch (input) { + case CLKIN_32K: + rate = CRYSTAL_32K_FREQ_IN; + break; + + case CLKIN_IRC: + rate = CGU_IRC_FREQ; + break; + + case CLKIN_ENET_RX: +#if defined(USE_RMII) + /* In RMII mode, this clock is not attached */ +#else + /* MII mode requires 25MHz clock */ + rate = 25000000; +#endif + break; + + case CLKIN_ENET_TX: +#if defined(USE_RMII) + /* MII mode requires 50MHz clock */ + rate = 50000000; +#else + /* MII mode requires 25MHz clock */ + rate = 25000000; +#endif + break; + + case CLKIN_CLKIN: +#if defined(EXTERNAL_CLKIN_FREQ_IN) + rate = EXTERNAL_CLKIN_FREQ_IN; +#else + /* Assume no clock in if a rate wasn't defined */ +#endif + break; + + case CLKIN_CRYSTAL: + rate = CRYSTAL_MAIN_FREQ_IN; + break; + + case CLKIN_USBPLL: + rate = 0; // FIXME + break; + + case CLKIN_AUDIOPLL: + rate = 0; // FIXME + break; + + case CLKIN_MAINPLL: + rate = Chip_Clock_GetMainPLLHz(); + break; + + case CLKIN_IDIVA: + rate = Chip_Clock_GetDivRate(input, CLK_IDIV_A); + break; + + case CLKIN_IDIVB: + rate = Chip_Clock_GetDivRate(input, CLK_IDIV_B); + break; + + case CLKIN_IDIVC: + rate = Chip_Clock_GetDivRate(input, CLK_IDIV_C); + break; + + case CLKIN_IDIVD: + rate = Chip_Clock_GetDivRate(input, CLK_IDIV_D); + break; + + case CLKIN_IDIVE: + rate = Chip_Clock_GetDivRate(input, CLK_IDIV_E); + break; + + case CLKINPUT_PD: + rate = 0; + break; + + default: + break; + } + + return rate; +} + +/* Returns the frequency of the specified base clock source */ +uint32_t Chip_Clock_GetBaseClocktHz(CGU_BASE_CLK_T clock) +{ + return Chip_Clock_GetClockInputHz(Chip_Clock_GetBaseClock(clock)); +} + +/* Sets a CGU Base Clock clock source */ +void Chip_Clock_SetBaseClock(CGU_BASE_CLK_T BaseClock, CGU_CLKIN_T Input, bool autoblocken, bool powerdn) +{ + uint32_t reg = LPC_CGU->BASE_CLK[BaseClock]; + + if (BaseClock < CLK_BASE_NONE) { + if (Input != CLKINPUT_PD) { + /* Mask off fields we plan to update */ + reg &= ~((0x1F << 24) | 1 | (1 << 11)); + + if (autoblocken) { + reg |= (1 << 11); + } + if (powerdn) { + reg |= (1 << 0); + } + + /* Set clock source */ + reg |= (Input << 24); + + LPC_CGU->BASE_CLK[BaseClock] = reg; + } + } + else { + LPC_CGU->BASE_CLK[BaseClock] = reg | 1; /* Power down this base clock */ + } +} + +/*Enables a base clock source */ +void Chip_Clock_EnableBaseClock(CGU_BASE_CLK_T BaseClock) +{ + if (BaseClock < CLK_BASE_NONE) { + LPC_CGU->BASE_CLK[BaseClock] &= ~1; + } +} + +/* Disables a base clock source */ +void Chip_Clock_DisableBaseClock(CGU_BASE_CLK_T BaseClock) +{ + if (BaseClock < CLK_BASE_NONE) { + LPC_CGU->BASE_CLK[BaseClock] |= 1; + } +} + +/* Gets a CGU Base Clock clock source */ +CGU_CLKIN_T Chip_Clock_GetBaseClock(CGU_BASE_CLK_T BaseClock) +{ + uint32_t reg = LPC_CGU->BASE_CLK[BaseClock]; + + if (BaseClock >= CLK_BASE_NONE) { + return CLKINPUT_PD; + } + + /* base clock is powered down? */ + if (reg & 1) { + return CLKINPUT_PD; + } + + return (CGU_CLKIN_T) ((reg >> 24) & 0x1F); +} + +/* Enables a peripheral clock and sets clock states */ +void Chip_Clock_EnableOpts(CCU_CLK_T clk, bool autoen, bool wakeupen, int div) +{ + uint32_t reg = 1; + + if (autoen) { + reg |= (1 << 1); + } + if (wakeupen) { + reg |= (1 << 2); + } + + /* Not all clocks support a divider, but we won't check that here. Only + dividers of 1 and 2 are allowed. Assume 1 if not 2 */ + if (div == 2) { + reg |= (1 << 5); + } + + /* Setup peripheral clock and start running */ + if (clk >= CLK_CCU2_START) { + LPC_CCU2->CLKCCU[clk - CLK_CCU2_START].CFG = reg; + } + else { + LPC_CCU1->CLKCCU[clk].CFG = reg; + } +} + +/* Enables a peripheral clock */ +void Chip_Clock_Enable(CCU_CLK_T clk) +{ + /* Start peripheral clock running */ + if (clk >= CLK_CCU2_START) { + LPC_CCU2->CLKCCU[clk - CLK_CCU2_START].CFG |= 1; + } + else { + LPC_CCU1->CLKCCU[clk].CFG |= 1; + } +} + +/* Disables a peripheral clock */ +void Chip_Clock_Disable(CCU_CLK_T clk) +{ + /* Stop peripheral clock */ + if (clk >= CLK_CCU2_START) { + LPC_CCU2->CLKCCU[clk - CLK_CCU2_START].CFG &= ~1; + } + else { + LPC_CCU1->CLKCCU[clk].CFG &= ~1; + } +} + +/* Returns a peripheral clock rate */ +uint32_t Chip_Clock_GetRate(CCU_CLK_T clk) +{ + CGU_BASE_CLK_T baseclk; + uint32_t reg, div, rate; + + /* Get CCU config register for clock */ + if (clk >= CLK_CCU2_START) { + reg = LPC_CCU2->CLKCCU[clk - CLK_CCU2_START].CFG; + } + else { + reg = LPC_CCU1->CLKCCU[clk].CFG; + } + + /* Is the clock enabled? */ + if (reg & 1) { + /* Get base clock for this peripheral clock */ + baseclk = Chip_Clock_FindBseClock(clk); + + /* Get base clock rate */ + rate = Chip_Clock_GetBaseClocktHz(baseclk); + + /* Get divider for this clock */ + if (((reg >> 5) & 0x7) == 0) { + div = 1; + } + else { + div = 2;/* No other dividers supported */ + + } + rate = rate / div; + } + else { + rate = 0; + } + + return rate; +} diff --git a/bsp/xplorer4330/libraries/lpc_chip/chip_18xx_43xx/clock_18xx_43xx.h b/bsp/xplorer4330/libraries/lpc_chip/chip_18xx_43xx/clock_18xx_43xx.h new file mode 100644 index 0000000000..c69b322c60 --- /dev/null +++ b/bsp/xplorer4330/libraries/lpc_chip/chip_18xx_43xx/clock_18xx_43xx.h @@ -0,0 +1,238 @@ +/* + * @brief LPC18xx/43xx clock driver + * + * @note + * Copyright(C) NXP Semiconductors, 2012 + * All rights reserved. + * + * @par + * Software that is described herein is for illustrative purposes only + * which provides customers with programming information regarding the + * LPC products. This software is supplied "AS IS" without any warranties of + * any kind, and NXP Semiconductors and its licenser disclaim any and + * all warranties, express or implied, including all implied warranties of + * merchantability, fitness for a particular purpose and non-infringement of + * intellectual property rights. NXP Semiconductors assumes no responsibility + * or liability for the use of the software, conveys no license or rights under any + * patent, copyright, mask work right, or any other intellectual property rights in + * or to any products. NXP Semiconductors reserves the right to make changes + * in the software without notification. NXP Semiconductors also makes no + * representation or warranty that such application will be suitable for the + * specified use without further testing or modification. + * + * @par + * Permission to use, copy, modify, and distribute this software and its + * documentation is hereby granted, under NXP Semiconductors' and its + * licensor's relevant copyrights in the software, without fee, provided that it + * is used in conjunction with NXP Semiconductors microcontrollers. This + * copyright, permission, and disclaimer notice must appear in all copies of + * this code. + */ + +#ifndef __CLOCK_18XX_43XX_H_ +#define __CLOCK_18XX_43XX_H_ + +#include "chip.h" + +#ifdef __cplusplus +extern "C" { +#endif + +/** @defgroup CLOCK_18XX_43XX CHIP: LPC18xx/43xx Clock Driver + * @ingroup CHIP_18XX_43XX_Drivers + * @{ + */ + +/** @defgroup CLOCK_18XX_43XX_OPTIONS CHIP: LPC18xx/43xx Clock Driver driver options + * @ingroup CLOCK_18XX_43XX CHIP_18XX_43XX_DRIVER_OPTIONS + * The clock driver has options that configure it's operation at build-time.
+ * MAX_CLOCK_FREQ: + * - This define, when set, identifies the maximumCPU clock rate of the system (change this to alter running CPU speed) + * - When this is not defined, The maximum clock rate for the CPU is used + *

+ * For more information on driver options see @ref LPCOPEN_DESIGN_ARPPROACH
+ * @{ + */ + +/** + * @} + */ + +/* Internal oscillator frequency */ +#define CGU_IRC_FREQ (12000000) + +#ifndef MAX_CLOCK_FREQ +#if defined(CHIP_LPC43XX) +#define MAX_CLOCK_FREQ (204000000) +#else +#define MAX_CLOCK_FREQ (180000000) +#endif +#endif /* MAX_CLOCK_FREQ */ + +/** + * @brief Enables the crystal oscillator + * @return Nothing + */ +void Chip_Clock_EnableCrystal(void); + +/** + * @brief Disables the crystal oscillator + * @return Nothing + */ +void Chip_Clock_DisableCrystal(void); + +/** + * @brief Configures the main PLL + * @param Input : Which clock input to use as the PLL input + * @param MinHz : Minimum allowable PLL output frequency + * @param DesiredHz : Desired PLL output frequency + * @param MaxHz : Maximum allowable PLL output frequency + * @return Frequency of the PLL in Hz + * Returns the configured PLL frequency or zero if the PLL can not be configured between MinHz + * and MaxHz. This will not wait for PLL lock. Call Chip_Clock_MainPLLLocked() to determine if + * the PLL is locked. + */ +uint32_t Chip_Clock_SetupMainPLLHz(CGU_CLKIN_T Input, uint32_t MinHz, uint32_t DesiredHz, uint32_t MaxHz); + +/** + * @brief Directly set the PLL multipler + * @param Input : Which clock input to use as the PLL input + * @param mult : How many times to multiply the input clock + * @return Frequency of the PLL in Hz + */ +uint32_t Chip_Clock_SetupMainPLLMult(CGU_CLKIN_T Input, uint32_t mult); + +/** + * @brief Returns the frequency of the main PLL + * @return Frequency of the PLL in Hz + * Returns zero if the main PLL is not running. + */ +uint32_t Chip_Clock_GetMainPLLHz(void); + +/** + * @brief Disables the main PLL + * @return none + * Make sure the main PLL is not needed to clock the part before disabling it. + * Saves power if the main PLL is not needed. + */ +void Chip_Clock_DisableMainPLL(void); + +/** + * @brief Returns the lock status of the main PLL + * @return true if the PLL is locked, otherwise false + * The main PLL should be locked prior to using it as a clock input for a base clock. + */ +bool Chip_Clock_MainPLLLocked(void); + +/** + * @brief Sets up a CGU clock divider and it's input clock + * @param Divider : CGU_IDIV_T value indicating which divider to configure + * @param Input : CGU_CLKIN_T value indicating which clock source to use or CLOCKINPUT_PD to power down divider + * @param Divisor : value to divide Input clock by + * @return Nothing + */ +void Chip_Clock_SetDivider(CGU_IDIV_T Divider, CGU_CLKIN_T Input, uint32_t Divisor); + +/** + * @brief Gets a CGU clock divider source + * @param Divider : CGU_IDIV_T value indicating which divider to get the source of + * @return CGU_CLKIN_T indicating which clock source is set or CLOCKINPUT_PD + */ +CGU_CLKIN_T Chip_Clock_GetDividerSource(CGU_IDIV_T Divider); + +/** + * @brief Gets a CGU clock divider divisor + * @param Divider : CGU_IDIV_T value indicating which divider to get the source of + * @return the divider value for the divider + */ +uint32_t Chip_Clock_GetDividerDivisor(CGU_IDIV_T Divider); + +/** + * @brief Returns the frequency of the specified input clock source + * @param input : Which clock input to return the frequency of + * @return Frequency of input source in Hz + * This function returns an ideal frequency and not the actual frequency. Returns + * zero if the clock source is disabled. + */ +uint32_t Chip_Clock_GetClockInputHz(CGU_CLKIN_T input); + +/** + * @brief Returns the frequency of the specified base clock source + * @param clock : which base clock to return the frequency of. + * @return Frequency of base source in Hz + * This function returns an ideal frequency and not the actual frequency. Returns + * zero if the clock source is disabled. + */ +uint32_t Chip_Clock_GetBaseClocktHz(CGU_BASE_CLK_T clock); + +/** + * @brief Sets a CGU Base Clock clock source + * @param BaseClock : CGU_BASE_CLK_T value indicating which base clock to set + * @param Input : CGU_CLKIN_T value indicating which clock source to use or CLOCKINPUT_PD to power down base clock + * @param autoblocken : Enables autoblocking during frequency change if true + * @param powerdn : The clock base is setup, but powered down if true + * @return Nothing + */ +void Chip_Clock_SetBaseClock(CGU_BASE_CLK_T BaseClock, CGU_CLKIN_T Input, bool autoblocken, bool powerdn); + +/** + * @brief Gets a CGU Base Clock clock source + * @param BaseClock : CGU_BASE_CLK_T value indicating which base clock to get inpuot clock for + * @return CGU_CLKIN_T indicating which clock source is set or CLOCKINPUT_PD + */ +CGU_CLKIN_T Chip_Clock_GetBaseClock(CGU_BASE_CLK_T BaseClock); + +/** + * @brief Enables a base clock source + * @param BaseClock : CGU_BASE_CLK_T value indicating which base clock to enable + * @return Nothing + */ +void Chip_Clock_EnableBaseClock(CGU_BASE_CLK_T BaseClock); + +/** + * @brief Disables a base clock source + * @param BaseClock : CGU_BASE_CLK_T value indicating which base clock to disable + * @return Nothing + */ +void Chip_Clock_DisableBaseClock(CGU_BASE_CLK_T BaseClock); + +/** + * @brief Enables a peripheral clock and sets clock states + * @param clk : CCU_CLK_T value indicating which clock to enable + * @param autoen : true to enable autoblocking on a clock rate change, false to disable + * @param wakeupen : true to enable wakeup mechanism, false to disable + * @param div : Divider for the clock, must be 1 for most clocks, 2 supported on others + * @return Nothing + */ +void Chip_Clock_EnableOpts(CCU_CLK_T clk, bool autoen, bool wakeupen, int div); + +/** + * @brief Enables a peripheral clock + * @param clk : CCU_CLK_T value indicating which clock to enable + * @return Nothing + */ +void Chip_Clock_Enable(CCU_CLK_T clk); + +/** + * @brief Disables a peripheral clock + * @param clk : CCU_CLK_T value indicating which clock to disable + * @return Nothing + */ +void Chip_Clock_Disable(CCU_CLK_T clk); + +/** + * @brief Returns a peripheral clock rate + * @param clk : CCU_CLK_T value indicating which clock to get rate for + * @return 0 if the clock is disabled, or the rate of the clock + */ +uint32_t Chip_Clock_GetRate(CCU_CLK_T clk); + +/** + * @} + */ + +#ifdef __cplusplus +} +#endif + +#endif /* __CLOCK_18XX_43XX_H_ */ diff --git a/bsp/xplorer4330/libraries/lpc_chip/chip_18xx_43xx/cmsis.h b/bsp/xplorer4330/libraries/lpc_chip/chip_18xx_43xx/cmsis.h new file mode 100644 index 0000000000..95872b9e68 --- /dev/null +++ b/bsp/xplorer4330/libraries/lpc_chip/chip_18xx_43xx/cmsis.h @@ -0,0 +1,355 @@ +/* + * @brief Basic CMSIS include file + * + * @note + * Copyright(C) NXP Semiconductors, 2012 + * All rights reserved. + * + * @par + * Software that is described herein is for illustrative purposes only + * which provides customers with programming information regarding the + * LPC products. This software is supplied "AS IS" without any warranties of + * any kind, and NXP Semiconductors and its licensor disclaim any and + * all warranties, express or implied, including all implied warranties of + * merchantability, fitness for a particular purpose and non-infringement of + * intellectual property rights. NXP Semiconductors assumes no responsibility + * or liability for the use of the software, conveys no license or rights under any + * patent, copyright, mask work right, or any other intellectual property rights in + * or to any products. NXP Semiconductors reserves the right to make changes + * in the software without notification. NXP Semiconductors also makes no + * representation or warranty that such application will be suitable for the + * specified use without further testing or modification. + * + * @par + * Permission to use, copy, modify, and distribute this software and its + * documentation is hereby granted, under NXP Semiconductors' and its + * licensor's relevant copyrights in the software, without fee, provided that it + * is used in conjunction with NXP Semiconductors microcontrollers. This + * copyright, permission, and disclaimer notice must appear in all copies of + * this code. + */ + +#ifndef __CMSIS_H_ +#define __CMSIS_H_ + +#include "lpc_types.h" + +#ifdef __cplusplus +extern "C" { +#endif + +/** @defgroup CMSIS_18XX_43XX CHIP: LPC18xx/43xx CMSIS include file + * @ingroup CHIP_18XX_43XX_Drivers + * @{ + */ + +#if defined(__ARMCC_VERSION) +// Kill warning "#pragma push with no matching #pragma pop" + #pragma diag_suppress 2525 + #pragma push + #pragma anon_unions +#elif defined(__CWCC__) + #pragma push + #pragma cpp_extensions on +#elif defined(__GNUC__) +/* anonymous unions are enabled by default */ +#elif defined(__IAR_SYSTEMS_ICC__) +// #pragma push // FIXME not usable for IAR + #pragma language=extended +#else + #error Not supported compiler type +#endif + +#if defined(CORE_M4) +/** @defgroup CMSIS_43XX CHIP: LPC43xx Cortex CMSIS definitions + * @{ + */ + +#define __CM4_REV 0x0000 /*!< Cortex-M4 Core Revision */ +#define __MPU_PRESENT 1 /*!< MPU present or not */ +#define __NVIC_PRIO_BITS 3 /*!< Number of Bits used for Priority Levels */ +#define __Vendor_SysTickConfig 0 /*!< Set to 1 if different SysTick Config is used */ +#ifdef CHIP_LPC43XX +#define __FPU_PRESENT 1 /*!< FPU present or not */ +#else +#define __FPU_PRESENT 0 /*!< FPU present or not */ +#endif + +/** + * @} + */ + +/** @defgroup CMSIS_43XX_IRQ CHIP: LPC43xx peripheral interrupt numbers + * @{ + */ + +typedef enum { + /* ------------------------- Cortex-M4 Processor Exceptions Numbers ----------------------------- */ + Reset_IRQn = -15,/*!< 1 Reset Vector, invoked on Power up and warm reset */ + NonMaskableInt_IRQn = -14,/*!< 2 Non maskable Interrupt, cannot be stopped or preempted */ + HardFault_IRQn = -13,/*!< 3 Hard Fault, all classes of Fault */ + MemoryManagement_IRQn = -12,/*!< 4 Memory Management, MPU mismatch, including Access Violation and No Match */ + BusFault_IRQn = -11,/*!< 5 Bus Fault, Pre-Fetch-, Memory Access Fault, other address/memory related Fault */ + UsageFault_IRQn = -10,/*!< 6 Usage Fault, i.e. Undef Instruction, Illegal State Transition */ + SVCall_IRQn = -5,/*!< 11 System Service Call via SVC instruction */ + DebugMonitor_IRQn = -4,/*!< 12 Debug Monitor */ + PendSV_IRQn = -2,/*!< 14 Pendable request for system service */ + SysTick_IRQn = -1,/*!< 15 System Tick Timer */ + + /* --------------------------- LPC18xx/43xx Specific Interrupt Numbers ------------------------------- */ + DAC_IRQn = 0,/*!< 0 DAC */ + M0CORE_IRQn = 1,/*!< 1 M0a */ + DMA_IRQn = 2,/*!< 2 DMA */ + RESERVED1_IRQn = 3,/*!< 3 EZH/EDM */ + RESERVED2_IRQn = 4, + ETHERNET_IRQn = 5,/*!< 5 ETHERNET */ + SDIO_IRQn = 6,/*!< 6 SDIO */ + LCD_IRQn = 7,/*!< 7 LCD */ + USB0_IRQn = 8,/*!< 8 USB0 */ + USB1_IRQn = 9,/*!< 9 USB1 */ + SCT_IRQn = 10,/*!< 10 SCT */ + RITIMER_IRQn = 11,/*!< 11 RITIMER */ + TIMER0_IRQn = 12,/*!< 12 TIMER0 */ + TIMER1_IRQn = 13,/*!< 13 TIMER1 */ + TIMER2_IRQn = 14,/*!< 14 TIMER2 */ + TIMER3_IRQn = 15,/*!< 15 TIMER3 */ + MCPWM_IRQn = 16,/*!< 16 MCPWM */ + ADC0_IRQn = 17,/*!< 17 ADC0 */ + I2C0_IRQn = 18,/*!< 18 I2C0 */ + I2C1_IRQn = 19,/*!< 19 I2C1 */ + SPI_INT_IRQn = 20,/*!< 20 SPI_INT */ + ADC1_IRQn = 21,/*!< 21 ADC1 */ + SSP0_IRQn = 22,/*!< 22 SSP0 */ + SSP1_IRQn = 23,/*!< 23 SSP1 */ + USART0_IRQn = 24,/*!< 24 USART0 */ + UART1_IRQn = 25,/*!< 25 UART1 */ + USART2_IRQn = 26,/*!< 26 USART2 */ + USART3_IRQn = 27,/*!< 27 USART3 */ + I2S0_IRQn = 28,/*!< 28 I2S0 */ + I2S1_IRQn = 29,/*!< 29 I2S1 */ + RESERVED4_IRQn = 30, + SGPIO_INT_IRQn = 31,/*!< 31 SGPIO_IINT */ + PIN_INT0_IRQn = 32,/*!< 32 PIN_INT0 */ + PIN_INT1_IRQn = 33,/*!< 33 PIN_INT1 */ + PIN_INT2_IRQn = 34,/*!< 34 PIN_INT2 */ + PIN_INT3_IRQn = 35,/*!< 35 PIN_INT3 */ + PIN_INT4_IRQn = 36,/*!< 36 PIN_INT4 */ + PIN_INT5_IRQn = 37,/*!< 37 PIN_INT5 */ + PIN_INT6_IRQn = 38,/*!< 38 PIN_INT6 */ + PIN_INT7_IRQn = 39,/*!< 39 PIN_INT7 */ + GINT0_IRQn = 40,/*!< 40 GINT0 */ + GINT1_IRQn = 41,/*!< 41 GINT1 */ + EVENTROUTER_IRQn = 42,/*!< 42 EVENTROUTER */ + C_CAN1_IRQn = 43,/*!< 43 C_CAN1 */ + RESERVED6_IRQn = 44, + RESERVED7_IRQn = 45,/*!< 45 VADC */ + ATIMER_IRQn = 46,/*!< 46 ATIMER */ + RTC_IRQn = 47,/*!< 47 RTC */ + RESERVED8_IRQn = 48, + WWDT_IRQn = 49,/*!< 49 WWDT */ + RESERVED9_IRQn = 50, + C_CAN0_IRQn = 51,/*!< 51 C_CAN0 */ + QEI_IRQn = 52,/*!< 52 QEI */ +} IRQn_Type; + +/** + * @} + */ + +#include "core_cm4.h" /*!< Cortex-M4 processor and core peripherals */ + +#elif defined(CORE_M3) +/** @defgroup CMSIS_18XX CHIP: LPC18xx Cortex CMSIS definitions + * @{ + */ + +#define __MPU_PRESENT 1 /*!< MPU present or not */ +#define __NVIC_PRIO_BITS 3 /*!< Number of Bits used for Priority Levels */ +#define __Vendor_SysTickConfig 0 /*!< Set to 1 if different SysTick Config is used */ +#define __FPU_PRESENT 0 /*!< FPU present or not */ + +/** + * @} + */ + +/** @defgroup CMSIS_18XX_IRQ CHIP: LPC18xx peripheral interrupt numbers + * @{ + */ + +typedef enum { + /* ------------------------- Cortex-M3 Processor Exceptions Numbers ----------------------------- */ + Reset_IRQn = -15,/*!< 1 Reset Vector, invoked on Power up and warm reset */ + NonMaskableInt_IRQn = -14,/*!< 2 Non maskable Interrupt, cannot be stopped or preempted */ + HardFault_IRQn = -13,/*!< 3 Hard Fault, all classes of Fault */ + MemoryManagement_IRQn = -12,/*!< 4 Memory Management, MPU mismatch, including Access Violation and No Match */ + BusFault_IRQn = -11,/*!< 5 Bus Fault, Pre-Fetch-, Memory Access Fault, other address/memory related Fault */ + UsageFault_IRQn = -10,/*!< 6 Usage Fault, i.e. Undef Instruction, Illegal State Transition */ + SVCall_IRQn = -5, /*!< 11 System Service Call via SVC instruction */ + DebugMonitor_IRQn = -4, /*!< 12 Debug Monitor */ + PendSV_IRQn = -2, /*!< 14 Pendable request for system service */ + SysTick_IRQn = -1, /*!< 15 System Tick Timer */ + + /* --------------------------- LPC18xx/43xx Specific Interrupt Numbers ------------------------------- */ + DAC_IRQn = 0,/*!< 0 DAC */ + RESERVED0_IRQn = 1, + DMA_IRQn = 2,/*!< 2 DMA */ + RESERVED1_IRQn = 3,/*!< 3 EZH/EDM */ + RESERVED2_IRQn = 4, + ETHERNET_IRQn = 5,/*!< 5 ETHERNET */ + SDIO_IRQn = 6,/*!< 6 SDIO */ + LCD_IRQn = 7,/*!< 7 LCD */ + USB0_IRQn = 8,/*!< 8 USB0 */ + USB1_IRQn = 9,/*!< 9 USB1 */ + SCT_IRQn = 10,/*!< 10 SCT */ + RITIMER_IRQn = 11,/*!< 11 RITIMER */ + TIMER0_IRQn = 12,/*!< 12 TIMER0 */ + TIMER1_IRQn = 13,/*!< 13 TIMER1 */ + TIMER2_IRQn = 14,/*!< 14 TIMER2 */ + TIMER3_IRQn = 15,/*!< 15 TIMER3 */ + MCPWM_IRQn = 16,/*!< 16 MCPWM */ + ADC0_IRQn = 17,/*!< 17 ADC0 */ + I2C0_IRQn = 18,/*!< 18 I2C0 */ + I2C1_IRQn = 19,/*!< 19 I2C1 */ + RESERVED3_IRQn = 20, + ADC1_IRQn = 21,/*!< 21 ADC1 */ + SSP0_IRQn = 22,/*!< 22 SSP0 */ + SSP1_IRQn = 23,/*!< 23 SSP1 */ + USART0_IRQn = 24,/*!< 24 USART0 */ + UART1_IRQn = 25,/*!< 25 UART1 */ + USART2_IRQn = 26,/*!< 26 USART2 */ + USART3_IRQn = 27,/*!< 27 USART3 */ + I2S0_IRQn = 28,/*!< 28 I2S0 */ + I2S1_IRQn = 29,/*!< 29 I2S1 */ + RESERVED4_IRQn = 30, + RESERVED5_IRQn = 31, + PIN_INT0_IRQn = 32,/*!< 32 PIN_INT0 */ + PIN_INT1_IRQn = 33,/*!< 33 PIN_INT1 */ + PIN_INT2_IRQn = 34,/*!< 34 PIN_INT2 */ + PIN_INT3_IRQn = 35,/*!< 35 PIN_INT3 */ + PIN_INT4_IRQn = 36,/*!< 36 PIN_INT4 */ + PIN_INT5_IRQn = 37,/*!< 37 PIN_INT5 */ + PIN_INT6_IRQn = 38,/*!< 38 PIN_INT6 */ + PIN_INT7_IRQn = 39,/*!< 39 PIN_INT7 */ + GINT0_IRQn = 40,/*!< 40 GINT0 */ + GINT1_IRQn = 41,/*!< 41 GINT1 */ + EVENTROUTER_IRQn = 42,/*!< 42 EVENTROUTER */ + C_CAN1_IRQn = 43,/*!< 43 C_CAN1 */ + RESERVED6_IRQn = 44, + RESERVED7_IRQn = 45,/*!< 45 VADC */ + ATIMER_IRQn = 46,/*!< 46 ATIMER */ + RTC_IRQn = 47,/*!< 47 RTC */ + RESERVED8_IRQn = 48, + WWDT_IRQn = 49,/*!< 49 WWDT */ + RESERVED9_IRQn = 50, + C_CAN0_IRQn = 51,/*!< 51 C_CAN0 */ + QEI_IRQn = 52,/*!< 52 QEI */ +} IRQn_Type; + +/** + * @} + */ + +#include "core_cm3.h" /*!< Cortex-M3 processor and core peripherals */ + +#elif defined(CORE_M0) +/** @defgroup CMSIS_43XX_M0 CHIP: LPC43xx (M0 Core) Cortex CMSIS definitions + * @{ + */ + +#define __MPU_PRESENT 0 /*!< MPU present or not */ +#define __NVIC_PRIO_BITS 2 /*!< Number of Bits used for Priority Levels */ +#define __Vendor_SysTickConfig 0 /*!< Set to 1 if different SysTick Config is used */ +#define __FPU_PRESENT 0 /*!< FPU present or not */ + +/** + * @} + */ + +/** @defgroup CMSIS_43XX_M0_IRQ CHIP: LPC43xx (M0 Core) peripheral interrupt numbers + * @{ + */ + +typedef enum { + /* ------------------------- Cortex-M0 Processor Exceptions Numbers ----------------------------- */ + Reset_IRQn = -15,/*!< 1 Reset Vector, invoked on Power up and warm reset */ + NonMaskableInt_IRQn = -14,/*!< 2 Non maskable Interrupt, cannot be stopped or preempted */ + HardFault_IRQn = -13,/*!< 3 Hard Fault, all classes of Fault */ + SVCall_IRQn = -5, /*!< 11 System Service Call via SVC instruction */ + DebugMonitor_IRQn = -4, /*!< 12 Debug Monitor */ + PendSV_IRQn = -2, /*!< 14 Pendable request for system service */ + SysTick_IRQn = -1, /*!< 15 System Tick Timer */ + + /* --------------------------- LPC18xx/43xx Specific Interrupt Numbers ------------------------------- */ + DAC_IRQn = 0,/*!< 0 DAC */ + M0_M4CORE_IRQn = 1,/*!< 1 M0a */ + DMA_IRQn = 2,/*!< 2 DMA */ + RESERVED1_IRQn = 3,/*!< 3 EZH/EDM */ + RESERVED2_IRQn = 4, + ETHERNET_IRQn = 5,/*!< 5 ETHERNET */ + SDIO_IRQn = 6,/*!< 6 SDIO */ + LCD_IRQn = 7,/*!< 7 LCD */ + USB0_IRQn = 8,/*!< 8 USB0 */ + USB1_IRQn = 9,/*!< 9 USB1 */ + SCT_IRQn = 10,/*!< 10 SCT */ + RITIMER_IRQn = 11,/*!< 11 RITIMER */ + TIMER0_IRQn = 12,/*!< 12 TIMER0 */ + TIMER1_IRQn = 13,/*!< 13 TIMER1 */ + TIMER2_IRQn = 14,/*!< 14 TIMER2 */ + TIMER3_IRQn = 15,/*!< 15 TIMER3 */ + MCPWM_IRQn = 16,/*!< 16 MCPWM */ + ADC0_IRQn = 17,/*!< 17 ADC0 */ + I2C0_IRQn = 18,/*!< 18 I2C0 */ + I2C1_IRQn = 19,/*!< 19 I2C1 */ + SPI_INT_IRQn = 20,/*!< 20 SPI_INT */ + ADC1_IRQn = 21,/*!< 21 ADC1 */ + SSP0_IRQn = 22,/*!< 22 SSP0 */ + SSP1_IRQn = 23,/*!< 23 SSP1 */ + USART0_IRQn = 24,/*!< 24 USART0 */ + UART1_IRQn = 25,/*!< 25 UART1 */ + USART2_IRQn = 26,/*!< 26 USART2 */ + USART3_IRQn = 27,/*!< 27 USART3 */ + I2S0_IRQn = 28,/*!< 28 I2S0 */ + I2S1_IRQn = 29,/*!< 29 I2S1 */ + RESERVED4_IRQn = 30, + SGPIO_INT_IRQn = 31,/*!< 31 SGPIO_IINT */ + PIN_INT0_IRQn = 32,/*!< 32 PIN_INT0 */ + PIN_INT1_IRQn = 33,/*!< 33 PIN_INT1 */ + PIN_INT2_IRQn = 34,/*!< 34 PIN_INT2 */ + PIN_INT3_IRQn = 35,/*!< 35 PIN_INT3 */ + PIN_INT4_IRQn = 36,/*!< 36 PIN_INT4 */ + PIN_INT5_IRQn = 37,/*!< 37 PIN_INT5 */ + PIN_INT6_IRQn = 38,/*!< 38 PIN_INT6 */ + PIN_INT7_IRQn = 39,/*!< 39 PIN_INT7 */ + GINT0_IRQn = 40,/*!< 40 GINT0 */ + GINT1_IRQn = 41,/*!< 41 GINT1 */ + EVENTROUTER_IRQn = 42,/*!< 42 EVENTROUTER */ + C_CAN1_IRQn = 43,/*!< 43 C_CAN1 */ + RESERVED6_IRQn = 44, + RESERVED7_IRQn = 45,/*!< 45 VADC */ + ATIMER_IRQn = 46,/*!< 46 ATIMER */ + RTC_IRQn = 47,/*!< 47 RTC */ + RESERVED8_IRQn = 48, + WWDT_IRQn = 49,/*!< 49 WWDT */ + RESERVED9_IRQn = 50, + C_CAN0_IRQn = 51,/*!< 51 C_CAN0 */ + QEI_IRQn = 52,/*!< 52 QEI */ +} IRQn_Type; + +/** + * @} + */ + +#include "core_cm0.h" /*!< Cortex-M4 processor and core peripherals */ +#else +#error Please #define CORE_M0, CORE_M3, or CORE_M4 +#endif + +/** + * @} + */ + +#ifdef __cplusplus +} +#endif + +#endif /* __CMSIS_H_ */ diff --git a/bsp/xplorer4330/libraries/lpc_chip/chip_18xx_43xx/creg_18xx_43xx.h b/bsp/xplorer4330/libraries/lpc_chip/chip_18xx_43xx/creg_18xx_43xx.h new file mode 100644 index 0000000000..9573f39cc9 --- /dev/null +++ b/bsp/xplorer4330/libraries/lpc_chip/chip_18xx_43xx/creg_18xx_43xx.h @@ -0,0 +1,181 @@ +/* + * @brief LPC18XX/43XX CREG control functions + * + * @note + * Copyright(C) NXP Semiconductors, 2012 + * All rights reserved. + * + * @par + * Software that is described herein is for illustrative purposes only + * which provides customers with programming information regarding the + * LPC products. This software is supplied "AS IS" without any warranties of + * any kind, and NXP Semiconductors and its licensor disclaim any and + * all warranties, express or implied, including all implied warranties of + * merchantability, fitness for a particular purpose and non-infringement of + * intellectual property rights. NXP Semiconductors assumes no responsibility + * or liability for the use of the software, conveys no license or rights under any + * patent, copyright, mask work right, or any other intellectual property rights in + * or to any products. NXP Semiconductors reserves the right to make changes + * in the software without notification. NXP Semiconductors also makes no + * representation or warranty that such application will be suitable for the + * specified use without further testing or modification. + * + * @par + * Permission to use, copy, modify, and distribute this software and its + * documentation is hereby granted, under NXP Semiconductors' and its + * licensor's relevant copyrights in the software, without fee, provided that it + * is used in conjunction with NXP Semiconductors microcontrollers. This + * copyright, permission, and disclaimer notice must appear in all copies of + * this code. + */ + +#ifndef __CREG_18XX_43XX_H_ +#define __CREG_18XX_43XX_H_ + +#include "chip.h" + +#ifdef __cplusplus +extern "C" { +#endif + +/** @defgroup CREG_18XX_43XX CHIP: LPC18xx/43xx CREG driver + * @ingroup CHIP_18XX_43XX_Drivers + * @{ + */ + +/** + * @brief CREG Register Block + */ +typedef struct { /*!< CREG Structure */ + __I uint32_t RESERVED0; + __IO uint32_t CREG0; /*!< Chip configuration register 32 kHz oscillator output and BOD control register. */ + __I uint32_t RESERVED1[62]; + __IO uint32_t MXMEMMAP; /*!< ARM Cortex-M3/M4 memory mapping */ +#if defined(CHIP_LPC18XX) + __I uint32_t RESERVED2[5]; +#else + __I uint32_t RESERVED2; + __I uint32_t CREG1; /*!< Configuration Register 1 */ + __I uint32_t CREG2; /*!< Configuration Register 2 */ + __I uint32_t CREG3; /*!< Configuration Register 3 */ + __I uint32_t CREG4; /*!< Configuration Register 4 */ +#endif + __IO uint32_t CREG5; /*!< Chip configuration register 5. Controls JTAG access. */ + __IO uint32_t DMAMUX; /*!< DMA muxing control */ + __IO uint32_t FLASHCFGA; /*!< Flash accelerator configuration register for flash bank A */ + __IO uint32_t FLASHCFGB; /*!< Flash accelerator configuration register for flash bank B */ + __IO uint32_t ETBCFG; /*!< ETB RAM configuration */ + __IO uint32_t CREG6; /*!< Chip configuration register 6. */ +#if defined(CHIP_LPC18XX) + __I uint32_t RESERVED4[52]; +#else + __IO uint32_t M4TXEVENT; /*!< M4 IPC event register */ + __I uint32_t RESERVED4[51]; +#endif + __I uint32_t CHIPID; /*!< Part ID */ +#if defined(CHIP_LPC18XX) + __I uint32_t RESERVED5[191]; +#else + __I uint32_t RESERVED5[127]; + __IO uint32_t M0TXEVENT; /*!< M0 IPC Event register */ + __IO uint32_t M0APPMEMMAP; /*!< ARM Cortex M0 memory mapping */ + __I uint32_t RESERVED6[62]; +#endif + __IO uint32_t USB0FLADJ; /*!< USB0 frame length adjust register */ + __I uint32_t RESERVED7[63]; + __IO uint32_t USB1FLADJ; /*!< USB1 frame length adjust register */ +} LPC_CREG_T; + +/** + * @brief Identifies whether on-chip flash is present + * @return true if on chip flash is available, otherwise false + */ +STATIC INLINE uint32_t Chip_CREG_OnChipFlashIsPresent(void) +{ + return LPC_CREG->CHIPID != 0x3284E02B; +} + +/** + * @brief Configures the onboard Flash Accelerator in flash-based LPC18xx/LPC43xx parts. + * @param Hz : Current frequency in Hz of the CPU + * @return Nothing + * This function should be called with the higher frequency before the clock frequency is + * increased and it should be called with the new lower value after the clock frequency is + * decreased. + */ +STATIC INLINE void Chip_CREG_SetFlashAcceleration(uint32_t Hz) +{ + uint32_t FAValue = Hz / 21510000; + + LPC_CREG->FLASHCFGA = (LPC_CREG->FLASHCFGA & (~(0xF << 12))) | (FAValue << 12); + LPC_CREG->FLASHCFGB = (LPC_CREG->FLASHCFGB & (~(0xF << 12))) | (FAValue << 12); +} + +/** + * @brief Enables the USB0 high-speed PHY on LPC18xx/LPC43xx parts + * @param Enable : true to enable PHY, false to disable + * @return Nothing + * The USB0 PLL & clock should be configured before calling this function. This function + * should be called before the USB0 registers are accessed. + */ +STATIC INLINE void Chip_CREG_EnableUSB0Phy(bool Enable) +{ + if (Enable) { + LPC_CREG->CREG0 &= ~(1 << 5); + } + else { + LPC_CREG->CREG0 |= (1 << 5); + } +} + +/** + * @brief Configures the BOD and Reset on LPC18xx/LPC43xx parts. + * @param BODVL : Brown-Out Detect voltage level (0-3) + * @param BORVL : Brown-Out Reset voltage level (0-3) + * @return Nothing + */ +STATIC INLINE void Chip_CREG_ConfigureBODaR(uint32_t BODVL, uint32_t BORVL) +{ + LPC_CREG->CREG0 = (LPC_CREG->CREG0 & ~((3 << 8) | (3 << 10))) | (BODVL << 8) | (BORVL << 10); +} + +#if (defined(CHIP_LPC43XX) && defined(LPC_CREG)) +/** + * @brief Configures base address of image to be run in the Cortex M0 Core. + * @param memaddr : Address of the image (must be aligned to 4K) + * @return Nothing + */ +STATIC INLINE void Chip_CREG_SetM0AppMemMap(uint32_t memaddr) +{ + LPC_CREG->M0APPMEMMAP = memaddr & ~0xFFF; +} + +/** + * @brief Clear M4 IPC Event + * @return Nothing + */ +STATIC INLINE void Chip_CREG_ClearM4Event(void) +{ + LPC_CREG->M4TXEVENT = 0; +} + +/** + * @brief Clear M0 IPC Event + * @return Nothing + */ +STATIC INLINE void Chip_CREG_ClearM0Event(void) +{ + LPC_CREG->M0TXEVENT = 0; +} + +#endif + +/** + * @} + */ + +#ifdef __cplusplus +} +#endif + +#endif /* __CREG_18XX_43XX_H_ */ diff --git a/bsp/xplorer4330/libraries/lpc_chip/chip_18xx_43xx/emc_18xx_43xx.c b/bsp/xplorer4330/libraries/lpc_chip/chip_18xx_43xx/emc_18xx_43xx.c new file mode 100644 index 0000000000..218e75745b --- /dev/null +++ b/bsp/xplorer4330/libraries/lpc_chip/chip_18xx_43xx/emc_18xx_43xx.c @@ -0,0 +1,89 @@ +/* + * @brief LPC18xx/43xx EMC driver + * + * @note + * Copyright(C) NXP Semiconductors, 2012 + * All rights reserved. + * + * @par + * Software that is described herein is for illustrative purposes only + * which provides customers with programming information regarding the + * LPC products. This software is supplied "AS IS" without any warranties of + * any kind, and NXP Semiconductors and its licensor disclaim any and + * all warranties, express or implied, including all implied warranties of + * merchantability, fitness for a particular purpose and non-infringement of + * intellectual property rights. NXP Semiconductors assumes no responsibility + * or liability for the use of the software, conveys no license or rights under any + * patent, copyright, mask work right, or any other intellectual property rights in + * or to any products. NXP Semiconductors reserves the right to make changes + * in the software without notification. NXP Semiconductors also makes no + * representation or warranty that such application will be suitable for the + * specified use without further testing or modification. + * + * @par + * Permission to use, copy, modify, and distribute this software and its + * documentation is hereby granted, under NXP Semiconductors' and its + * licensor's relevant copyrights in the software, without fee, provided that it + * is used in conjunction with NXP Semiconductors microcontrollers. This + * copyright, permission, and disclaimer notice must appear in all copies of + * this code. + */ + +#include "emc_18xx_43xx.h" + +/***************************************************************************** + * Private types/enumerations/variables + ****************************************************************************/ + +/***************************************************************************** + * Public types/enumerations/variables + ****************************************************************************/ + +/***************************************************************************** + * Private functions + ****************************************************************************/ + +/***************************************************************************** + * Public functions + ****************************************************************************/ + +/* Dyanmic memory setup */ +void Chip_EMC_Dynamic_Init(IP_EMC_DYN_CONFIG_Type *Dynamic_Config) +{ + uint32_t ClkFreq; + uint32_t EMCDiv; + + /* Note clocks must be enabled prior to this call */ + ClkFreq = Chip_Clock_GetRate(CLK_MX_EMC); + + /* EMC Divider readback at pos 27 + TODO: just checked but dont mention in UM */ + EMCDiv = (LPC_CCU1->CLKCCU[CLK_MX_EMC_DIV].CFG >> 27) & 0x07; + + /* Check EMC Divider to get real EMC clock out */ + if ((EMCDiv == 1) && (LPC_CREG->CREG6 & (1 << 16))) { + ClkFreq >>= 1; + } + + IP_EMC_Dynamic_Init(LPC_EMC, Dynamic_Config, ClkFreq); +} + +/* Static memory setup */ +void Chip_EMC_Static_Init(IP_EMC_STATIC_CONFIG_Type *Static_Config) +{ + uint32_t ClkFreq; + uint32_t EMCDiv; + + /* Note clocks must be enabled prior to this call */ + ClkFreq = Chip_Clock_GetRate(CLK_MX_EMC); + + /* EMC Divider readback at pos 27 */ + EMCDiv = (LPC_CCU1->CLKCCU[CLK_MX_EMC_DIV].CFG >> 27) & 0x07; + + /* Check EMC Divider to get real EMC clock out */ + if ((EMCDiv == 1) && (LPC_CREG->CREG6 & (1 << 16))) { + ClkFreq >>= 1; + } + + IP_EMC_Static_Init(LPC_EMC, Static_Config, ClkFreq); +} diff --git a/bsp/xplorer4330/libraries/lpc_chip/chip_18xx_43xx/emc_18xx_43xx.h b/bsp/xplorer4330/libraries/lpc_chip/chip_18xx_43xx/emc_18xx_43xx.h new file mode 100644 index 0000000000..502b207263 --- /dev/null +++ b/bsp/xplorer4330/libraries/lpc_chip/chip_18xx_43xx/emc_18xx_43xx.h @@ -0,0 +1,156 @@ +/* + * @brief LPC18xx/43xx EMC driver + * + * @note + * Copyright(C) NXP Semiconductors, 2012 + * All rights reserved. + * + * @par + * Software that is described herein is for illustrative purposes only + * which provides customers with programming information regarding the + * LPC products. This software is supplied "AS IS" without any warranties of + * any kind, and NXP Semiconductors and its licensor disclaim any and + * all warranties, express or implied, including all implied warranties of + * merchantability, fitness for a particular purpose and non-infringement of + * intellectual property rights. NXP Semiconductors assumes no responsibility + * or liability for the use of the software, conveys no license or rights under any + * patent, copyright, mask work right, or any other intellectual property rights in + * or to any products. NXP Semiconductors reserves the right to make changes + * in the software without notification. NXP Semiconductors also makes no + * representation or warranty that such application will be suitable for the + * specified use without further testing or modification. + * + * @par + * Permission to use, copy, modify, and distribute this software and its + * documentation is hereby granted, under NXP Semiconductors' and its + * licensor's relevant copyrights in the software, without fee, provided that it + * is used in conjunction with NXP Semiconductors microcontrollers. This + * copyright, permission, and disclaimer notice must appear in all copies of + * this code. + */ + +#ifndef __EMC_18XX_43XX_H_ +#define __EMC_18XX_43XX_H_ + +#include "chip.h" + +#ifdef __cplusplus +extern "C" { +#endif + +/** @defgroup EMC_18XX_43XX CHIP: LPC18xx/43xx EMC Driver + * @ingroup CHIP_18XX_43XX_Drivers + * @{ + */ + +/** + * Dynamic Chip Select Address + */ +#define EMC_ADDRESS_DYCS0 (0x28000000) +#define EMC_ADDRESS_DYCS1 (0x30000000) +#define EMC_ADDRESS_DYCS2 (0x60000000) +#define EMC_ADDRESS_DYCS3 (0x70000000) + +/** + * Static Chip Select Address + */ +#define EMC_ADDRESS_CS0 (0x1C000000) +#define EMC_ADDRESS_CS1 (0x1D000000) +#define EMC_ADDRESS_CS2 (0x1E000000) +#define EMC_ADDRESS_CS3 (0x1F000000) + +/** + * @brief Dyanmic memory setup + * @param Dynamic_Config : Pointer to dynamic memory setup data + * @return None + */ +void Chip_EMC_Dynamic_Init(IP_EMC_DYN_CONFIG_Type *Dynamic_Config); + +/** + * @brief Static memory setup + * @param Static_Config : Pointer to static memory setup data + * @return None + */ +void Chip_EMC_Static_Init(IP_EMC_STATIC_CONFIG_Type *Static_Config); + +/** + * @brief Set Deep Sleep Mode for Dynamic Memory Controller + * @param Enable : 1 = enter DeepSleep Mode, 0 = Normal Mode + * @return None + */ +STATIC INLINE void Chip_EMC_Dynamic_DeepSleepMode(uint32_t Enable) +{ + IP_EMC_Dynamic_DeepSleepMode(LPC_EMC, Enable); +} + +/** + * @brief Enable Dynamic Memory Controller + * @param Enable : 1 = Enable Dynamic Memory Controller, 0 = Disable + * @return None + */ +STATIC INLINE void Chip_EMC_Dynamic_Enable(uint8_t Enable) +{ + IP_EMC_Dynamic_Enable(LPC_EMC, Enable); +} + +/** + * @brief Mirror CS1 to CS0 and DYCS0 + * @param Enable : 1 = Mirror, 0 = Normal Memory Map + * @return None + */ +STATIC INLINE void Chip_EMC_Mirror(uint8_t Enable) +{ + IP_EMC_Mirror(LPC_EMC, Enable); +} + +/** + * @brief Enable EMC + * @param Enable : 1 = Enable, 0 = Disable + * @return None + */ +STATIC INLINE void Chip_EMC_Enable(uint8_t Enable) +{ + IP_EMC_Enable(LPC_EMC, Enable); +} + +/** + * @brief Set EMC LowPower Mode + * @param Enable : 1 = Enable, 0 = Disable + * @return None + */ +STATIC INLINE void Chip_EMC_LowPowerMode(uint8_t Enable) +{ + IP_EMC_LowPowerMode(LPC_EMC, Enable); +} + +/** + * @brief Initialize EMC + * @param Enable : 1 = Enable, 0 = Disable + * @param ClockRatio : clock out ratio, 0 = 1:1, 1 = 1:2 + * @param EndianMode : Endian Mode, 0 = Little, 1 = Big + * @return None + */ +STATIC INLINE void Chip_EMC_Init(uint32_t Enable, uint32_t ClockRatio, uint32_t EndianMode) +{ + IP_EMC_Init(LPC_EMC, Enable, ClockRatio, EndianMode); +} + +/** + * @brief Set Static Memory Extended Wait in Clock + * @param Wait16Clks : Number of '16 clock' delay cycles + * @return None + */ +STATIC INLINE void Chip_EMC_SetStaticExtendedWait(uint32_t Wait16Clks) +{ + IP_EMC_SetStaticExtendedWait(LPC_EMC, Wait16Clks); +} + +/** + * @} + */ + +#ifdef __cplusplus +} +#endif + +#endif /* __EMC_18XX_43XX_H_ */ diff --git a/bsp/xplorer4330/libraries/lpc_chip/chip_18xx_43xx/enet_18xx_43xx.c b/bsp/xplorer4330/libraries/lpc_chip/chip_18xx_43xx/enet_18xx_43xx.c new file mode 100644 index 0000000000..f76edea185 --- /dev/null +++ b/bsp/xplorer4330/libraries/lpc_chip/chip_18xx_43xx/enet_18xx_43xx.c @@ -0,0 +1,82 @@ +/* + * @brief LPC18xx/43xx ethernet driver + * + * @note + * Copyright(C) NXP Semiconductors, 2012 + * All rights reserved. + * + * @par + * Software that is described herein is for illustrative purposes only + * which provides customers with programming information regarding the + * LPC products. This software is supplied "AS IS" without any warranties of + * any kind, and NXP Semiconductors and its licensor disclaim any and + * all warranties, express or implied, including all implied warranties of + * merchantability, fitness for a particular purpose and non-infringement of + * intellectual property rights. NXP Semiconductors assumes no responsibility + * or liability for the use of the software, conveys no license or rights under any + * patent, copyright, mask work right, or any other intellectual property rights in + * or to any products. NXP Semiconductors reserves the right to make changes + * in the software without notification. NXP Semiconductors also makes no + * representation or warranty that such application will be suitable for the + * specified use without further testing or modification. + * + * @par + * Permission to use, copy, modify, and distribute this software and its + * documentation is hereby granted, under NXP Semiconductors' and its + * licensor's relevant copyrights in the software, without fee, provided that it + * is used in conjunction with NXP Semiconductors microcontrollers. This + * copyright, permission, and disclaimer notice must appear in all copies of + * this code. + */ + +#include "enet_18xx_43xx.h" + +/***************************************************************************** + * Private types/enumerations/variables + ****************************************************************************/ + +/***************************************************************************** + * Public types/enumerations/variables + ****************************************************************************/ + +/***************************************************************************** + * Private functions + ****************************************************************************/ + +/***************************************************************************** + * Public functions + ****************************************************************************/ + +/* Basic Ethernet interface initialization */ +void Chip_ENET_Init(void) +{ + LPC_CREG->CREG6 &= ~0x7; + + /* Enable ethernet clock */ + Chip_Clock_EnableOpts(CLK_MX_ETHERNET, true, true, 1); + + /* PHY TX/RX base clock routing is setup as part of SystemInit() */ + +#if defined(USE_RMII) + LPC_CREG->CREG6 |= 0x4; +#endif + + /* Reset ethernet and wait for reset to complete */ + Chip_RGU_TriggerReset(RGU_ETHERNET_RST); + while (Chip_RGU_InReset(RGU_ETHERNET_RST)) {} + + /* Reset ethernet peripheral */ + Chip_ENET_Reset(); + + /* Setup MII link divider to /102 and PHY address 1 */ + Chip_ENET_Setup_MII(4, 1); + + IP_ENET_Init(LPC_ETHERNET); +} + +/* Ethernet interface shutdown */ +void Chip_ENET_DeInit(void) +{ + IP_ENET_DeInit(LPC_ETHERNET); + Chip_Clock_Disable(CLK_MX_ETHERNET); +} diff --git a/bsp/xplorer4330/libraries/lpc_chip/chip_18xx_43xx/enet_18xx_43xx.h b/bsp/xplorer4330/libraries/lpc_chip/chip_18xx_43xx/enet_18xx_43xx.h new file mode 100644 index 0000000000..226f037427 --- /dev/null +++ b/bsp/xplorer4330/libraries/lpc_chip/chip_18xx_43xx/enet_18xx_43xx.h @@ -0,0 +1,230 @@ +/* + * @brief LPC18xx/43xx ethernet driver + * + * @note + * Copyright(C) NXP Semiconductors, 2012 + * All rights reserved. + * + * @par + * Software that is described herein is for illustrative purposes only + * which provides customers with programming information regarding the + * LPC products. This software is supplied "AS IS" without any warranties of + * any kind, and NXP Semiconductors and its licensor disclaim any and + * all warranties, express or implied, including all implied warranties of + * merchantability, fitness for a particular purpose and non-infringement of + * intellectual property rights. NXP Semiconductors assumes no responsibility + * or liability for the use of the software, conveys no license or rights under any + * patent, copyright, mask work right, or any other intellectual property rights in + * or to any products. NXP Semiconductors reserves the right to make changes + * in the software without notification. NXP Semiconductors also makes no + * representation or warranty that such application will be suitable for the + * specified use without further testing or modification. + * + * @par + * Permission to use, copy, modify, and distribute this software and its + * documentation is hereby granted, under NXP Semiconductors' and its + * licensor's relevant copyrights in the software, without fee, provided that it + * is used in conjunction with NXP Semiconductors microcontrollers. This + * copyright, permission, and disclaimer notice must appear in all copies of + * this code. + */ + +#ifndef __ENET_18XX_43XX_H_ +#define __ENET_18XX_43XX_H_ + +#include "chip.h" + +#ifdef __cplusplus +extern "C" { +#endif + +/** @defgroup ENET_18XX_43XX CHIP: LPC18xx/43xx Ethernet driver + * @ingroup CHIP_18XX_43XX_Drivers + * @{ + */ + +/** @defgroup ENET_18XX_43XX_OPTIONS CHIP: LPC18xx/43xx Ethernet driver build options + * @ingroup ENET_18XX_43XX CHIP_18XX_43XX_DRIVER_OPTIONS + * The ethernet driver has options that configure it's operation at build-time.
+ * USE_RMII: + * - When defined, the driver will be built for RMII operation. + * - When not defined, the driver will be built for MII operation. + *

+ * For more information on driver options see @ref LPCOPEN_DESIGN_ARPPROACH
+ * @{ + */ + +/** + * @} + */ + +/** + * @brief Initialize ethernet interface + * @return Nothing + * Performs basic initialization of the ethernet interface in a default + * state. This is enough to place the interface in a usable state, but + * may require more setup outside this function. + */ +void Chip_ENET_Init(void); + +/** + * @brief De-initialize the ethernet interface + * @return Nothing + */ +void Chip_ENET_DeInit(void); + +/** + * @brief Resets the ethernet interface + * @return Nothing + * Resets the ethernet interface. This should be called prior to + * Chip_ENET_Init with a small delay after this call. + */ +STATIC INLINE void Chip_ENET_Reset(void) +{ + IP_ENET_Reset(LPC_ETHERNET); +} + +/** + * @brief Sets the address of the interface + * @param macAddr : Pointer to the 6 bytes used for the MAC address + * @return Nothing + */ +STATIC INLINE void Chip_ENET_SetADDR(const uint8_t *macAddr) +{ + IP_ENET_SetADDR(LPC_ETHERNET, macAddr); +} + +/** + * @brief Sets up the PHY link clock divider and PHY address + * @param div : Divider value, may vary per chip + * @param addr : PHY address, used with MII read and write + * @return Nothing + */ +STATIC INLINE void Chip_ENET_Setup_MII(uint32_t div, uint8_t addr) +{ + IP_ENET_SetupMII(LPC_ETHERNET, div, addr); +} + +/** + * @brief Starts a PHY write via the MII + * @param reg : PHY register to write + * @param data : Data to write to PHY register + * @return Nothing + * Start a PHY write operation. Does not block, requires calling + * IP_ENET_IsMIIBusy to determine when write is complete. + */ +STATIC INLINE void Chip_ENET_Start_MII_Write(uint8_t reg, uint16_t data) +{ + IP_ENET_StartMIIWrite(LPC_ETHERNET, reg, data); +} + +/** + * @brief Starts a PHY read via the MII + * @param reg : PHY register to read + * @return Nothing + * Start a PHY read operation. Does not block, requires calling + * IP_ENET_IsMIIBusy to determine when read is complete and calling + * IP_ENET_ReadMIIData to get the data. + */ +STATIC INLINE void Chip_ENET_Start_MII_Read(uint8_t reg) +{ + IP_ENET_StartMIIRead(LPC_ETHERNET, reg); +} + +/** + * @brief Returns MII link (PHY) busy status + * @return Returns true if busy, otherwise false + */ +STATIC INLINE bool Chip_ENET_Is_MII_Busy(void) +{ + return IP_ENET_IsMIIBusy(LPC_ETHERNET); +} + +/** + * @brief Returns the value read from the PHY + * @return Read value from PHY + */ +STATIC INLINE uint16_t Chip_ENET_Read_MII_Data(void) +{ + return IP_ENET_ReadMIIData(LPC_ETHERNET); +} + +/** + * @brief Enables or disables ethernet transmit + * @param Enable : true to enable transmit, false to disable + * @return Nothing + */ +STATIC INLINE void Chip_ENET_TX_Enable(bool Enable) +{ + IP_ENET_TXEnable(LPC_ETHERNET, Enable); +} + +/** + * @brief Enables or disables ethernet packet reception + * @param Enable : true to enable receive, false to disable + * @return Nothing + */ +STATIC INLINE void Chip_ENET_RX_Enable(bool Enable) +{ + IP_ENET_RXEnable(LPC_ETHERNET, Enable); +} + +/** + * @brief Sets full or half duplex for the interface + * @param full : true to selected full duplex, false for half + * @return Nothing + */ +STATIC INLINE void Chip_ENET_Set_Duplex(bool full) +{ + IP_ENET_SetDuplex(LPC_ETHERNET, full); +} + +/** + * @brief Sets speed for the interface + * @param speed100 : true to select 100Mbps mode, false for 10Mbps + * @return Nothing + */ +STATIC INLINE void Chip_ENET_Set_Speed(bool speed100) +{ + IP_ENET_SetSpeed(LPC_ETHERNET, speed100); +} + +/** + * @brief Configures the initial ethernet descriptors + * @param pTXDescs : Pointer to TX descriptor list + * @param pRXDescs : Pointer to RX descriptor list + * @return Nothing + */ +STATIC INLINE void Chip_ENET_InitDescriptors( + IP_ENET_001_ENHTXDESC_Type *pTXDescs, IP_ENET_001_ENHRXDESC_Type *pRXDescs) +{ + IP_ENET_InitDescriptors(LPC_ETHERNET, pTXDescs, pRXDescs); +} + +/** + * @brief Starts receive polling of RX descriptors + * @return Nothing + */ +STATIC INLINE void Chip_ENET_RXStart(void) +{ + IP_ENET_RXStart(LPC_ETHERNET); +} + +/** + * @brief Starts transmit polling of TX descriptors + * @return Nothing + */ +STATIC INLINE void Chip_ENET_TXStart(void) +{ + IP_ENET_TXStart(LPC_ETHERNET); +} + +/** + * @} + */ + +#ifdef __cplusplus +} +#endif + +#endif /* __ENET_18XX_43XX_H_ */ diff --git a/bsp/xplorer4330/libraries/lpc_chip/chip_18xx_43xx/evrt_18xx_43xx.c b/bsp/xplorer4330/libraries/lpc_chip/chip_18xx_43xx/evrt_18xx_43xx.c new file mode 100644 index 0000000000..a76a7065e2 --- /dev/null +++ b/bsp/xplorer4330/libraries/lpc_chip/chip_18xx_43xx/evrt_18xx_43xx.c @@ -0,0 +1,111 @@ +/* + * @brief LPC18xx/43xx event router driver + * + * @note + * Copyright(C) NXP Semiconductors, 2012 + * All rights reserved. + * + * @par + * Software that is described herein is for illustrative purposes only + * which provides customers with programming information regarding the + * LPC products. This software is supplied "AS IS" without any warranties of + * any kind, and NXP Semiconductors and its licensor disclaim any and + * all warranties, express or implied, including all implied warranties of + * merchantability, fitness for a particular purpose and non-infringement of + * intellectual property rights. NXP Semiconductors assumes no responsibility + * or liability for the use of the software, conveys no license or rights under any + * patent, copyright, mask work right, or any other intellectual property rights in + * or to any products. NXP Semiconductors reserves the right to make changes + * in the software without notification. NXP Semiconductors also makes no + * representation or warranty that such application will be suitable for the + * specified use without further testing or modification. + * + * @par + * Permission to use, copy, modify, and distribute this software and its + * documentation is hereby granted, under NXP Semiconductors' and its + * licensor's relevant copyrights in the software, without fee, provided that it + * is used in conjunction with NXP Semiconductors microcontrollers. This + * copyright, permission, and disclaimer notice must appear in all copies of + * this code. + */ + +#include "evrt_18xx_43xx.h" + +/***************************************************************************** + * Private types/enumerations/variables + ****************************************************************************/ + +/***************************************************************************** + * Public types/enumerations/variables + ****************************************************************************/ + +/***************************************************************************** + * Private functions + ****************************************************************************/ + +/***************************************************************************** + * Public functions + ****************************************************************************/ + +/* Initialize the EVRT */ +void Chip_EVRT_Init(void) +{ + uint8_t i = 0; + // Clear all register to be default + LPC_EVRT->HILO = 0x0000; + LPC_EVRT->EDGE = 0x0000; + LPC_EVRT->CLR_EN = 0xFFFF; + do { + i++; + LPC_EVRT->CLR_STAT = 0xFFFFF; + } while ((LPC_EVRT->STATUS != 0) && (i < 10)); +} + +/* Set up the type of interrupt type for a source to EVRT */ +void Chip_EVRT_ConfigIntSrcActiveType(Chip_EVRT_SRC_ENUM EVRT_Src, EVRT_SRC_ACTIVE_TYPE type) +{ + switch (type) { + case EVRT_SRC_ACTIVE_LOW_LEVEL: + LPC_EVRT->HILO &= ~(1 << (uint8_t) EVRT_Src); + LPC_EVRT->EDGE &= ~(1 << (uint8_t) EVRT_Src); + break; + + case EVRT_SRC_ACTIVE_HIGH_LEVEL: + LPC_EVRT->HILO |= (1 << (uint8_t) EVRT_Src); + LPC_EVRT->EDGE &= ~(1 << (uint8_t) EVRT_Src); + break; + + case EVRT_SRC_ACTIVE_FALLING_EDGE: + LPC_EVRT->HILO &= ~(1 << (uint8_t) EVRT_Src); + LPC_EVRT->EDGE |= (1 << (uint8_t) EVRT_Src); + break; + + case EVRT_SRC_ACTIVE_RISING_EDGE: + LPC_EVRT->HILO |= (1 << (uint8_t) EVRT_Src); + LPC_EVRT->EDGE |= (1 << (uint8_t) EVRT_Src); + break; + + default: + break; + } +} + +/* Enable or disable interrupt sources to EVRT */ +void Chip_EVRT_SetUpIntSrc(Chip_EVRT_SRC_ENUM EVRT_Src, FunctionalState state) +{ + if (state == ENABLE) { + LPC_EVRT->SET_EN = (1 << (uint8_t) EVRT_Src); + } + else { + LPC_EVRT->CLR_EN = (1 << (uint8_t) EVRT_Src); + } +} + +/* Check if a source is sending interrupt to EVRT */ +IntStatus Chip_EVRT_IsSourceInterrupting(Chip_EVRT_SRC_ENUM EVRT_Src) +{ + if (LPC_EVRT->STATUS & (1 << (uint8_t) EVRT_Src)) { + return SET; + } + else {return RESET; } +} diff --git a/bsp/xplorer4330/libraries/lpc_chip/chip_18xx_43xx/evrt_18xx_43xx.h b/bsp/xplorer4330/libraries/lpc_chip/chip_18xx_43xx/evrt_18xx_43xx.h new file mode 100644 index 0000000000..eef48c451a --- /dev/null +++ b/bsp/xplorer4330/libraries/lpc_chip/chip_18xx_43xx/evrt_18xx_43xx.h @@ -0,0 +1,173 @@ +/* + * @brief LPC18xx/43xx event router driver + * + * @note + * Copyright(C) NXP Semiconductors, 2012 + * All rights reserved. + * + * @par + * Software that is described herein is for illustrative purposes only + * which provides customers with programming information regarding the + * LPC products. This software is supplied "AS IS" without any warranties of + * any kind, and NXP Semiconductors and its licensor disclaim any and + * all warranties, express or implied, including all implied warranties of + * merchantability, fitness for a particular purpose and non-infringement of + * intellectual property rights. NXP Semiconductors assumes no responsibility + * or liability for the use of the software, conveys no license or rights under any + * patent, copyright, mask work right, or any other intellectual property rights in + * or to any products. NXP Semiconductors reserves the right to make changes + * in the software without notification. NXP Semiconductors also makes no + * representation or warranty that such application will be suitable for the + * specified use without further testing or modification. + * + * @par + * Permission to use, copy, modify, and distribute this software and its + * documentation is hereby granted, under NXP Semiconductors' and its + * licensor's relevant copyrights in the software, without fee, provided that it + * is used in conjunction with NXP Semiconductors microcontrollers. This + * copyright, permission, and disclaimer notice must appear in all copies of + * this code. + */ + +#ifndef __EVRT_18XX_43XX_H_ +#define __EVRT_18XX_43XX_H_ + +#include "chip.h" + +#ifdef __cplusplus +extern "C" { +#endif + +/** @defgroup EVRT_18XX_43XX CHIP: LPC18xx/43xx Event router driver + * @ingroup CHIP_18XX_43XX_Drivers + * @{ + */ + +/** + * @brief Event Router register structure + */ +typedef struct { /*!< EVENTROUTER Structure */ + __IO uint32_t HILO; /*!< Level configuration register */ + __IO uint32_t EDGE; /*!< Edge configuration */ + __I uint32_t RESERVED0[1012]; + __O uint32_t CLR_EN; /*!< Event clear enable register */ + __O uint32_t SET_EN; /*!< Event set enable register */ + __I uint32_t STATUS; /*!< Status register */ + __I uint32_t ENABLE; /*!< Enable register */ + __O uint32_t CLR_STAT; /*!< Clear register */ + __O uint32_t SET_STAT; /*!< Set register */ +} LPC_EVRT_Type; + +/** + * @brief EVRT input sources + */ +typedef enum { + EVRT_SRC_WAKEUP0, /*!< WAKEUP0 event router source */ + EVRT_SRC_WAKEUP1, /*!< WAKEUP1 event router source */ + EVRT_SRC_WAKEUP2, /*!< WAKEUP2 event router source */ + EVRT_SRC_WAKEUP3, /*!< WAKEUP3 event router source */ + EVRT_SRC_ATIMER, /*!< Alarm timer event router source */ + EVRT_SRC_RTC, /*!< RTC event router source */ + EVRT_SRC_BOD1, /*!< BOD event router source */ + EVRT_SRC_WWDT, /*!< WWDT event router source */ + EVRT_SRC_ETHERNET, /*!< Ethernet event router source */ + EVRT_SRC_USB0, /*!< USB0 event router source */ + EVRT_SRC_USB1, /*!< USB1 event router source */ + EVRT_SRC_SDIO, /*!< Reserved */ + EVRT_SRC_CCAN, /*!< C_CAN event router source */ + EVRT_SRC_COMBINE_TIMER2, /*!< Combined timer 2 event router source */ + EVRT_SRC_COMBINE_TIMER6, /*!< Combined timer 6 event router source */ + EVRT_SRC_QEI, /*!< QEI event router source */ + EVRT_SRC_COMBINE_TIMER14, /*!< Combined timer 14 event router source */ + EVRT_SRC_RESERVED1, /*!< Reserved */ + EVRT_SRC_RESERVED2, /*!< Reserved */ + EVRT_SRC_RESET /*!< Reset event router source */ +} Chip_EVRT_SRC_ENUM; + +/** + * @brief Macro for checking for a valid EVRT source + */ +#define PARAM_EVRT_SOURCE(n) ((n == EVRT_SRC_WAKEUP0) || (n == EVRT_SRC_WAKEUP1) \ + || (n == EVRT_SRC_WAKEUP2) || (n == EVRT_SRC_WAKEUP3) \ + || (n == EVRT_SRC_ATIMER) || (n == EVRT_SRC_RTC) \ + || (n == EVRT_SRC_BOD1) || (n == EVRT_SRC_WWDT) \ + || (n == EVRT_SRC_ETHERNET) || (n == EVRT_SRC_USB0) \ + || (n == EVRT_SRC_USB1) || (n == EVRT_SRC_CCAN) || (n == EVRT_SRC_SDIO) \ + || (n == EVRT_SRC_COMBINE_TIMER2) || (n == EVRT_SRC_COMBINE_TIMER6) \ + || (n == EVRT_SRC_QEI) || (n == EVRT_SRC_COMBINE_TIMER14) \ + || (n == EVRT_SRC_RESET)) \ + +/** + * @brief EVRT input state detecting type + */ +typedef enum { + EVRT_SRC_ACTIVE_LOW_LEVEL, /*!< Active low level */ + EVRT_SRC_ACTIVE_HIGH_LEVEL, /*!< Active high level */ + EVRT_SRC_ACTIVE_FALLING_EDGE, /*!< Active falling edge */ + EVRT_SRC_ACTIVE_RISING_EDGE /*!< Active rising edge */ +} EVRT_SRC_ACTIVE_TYPE; + +/** + * @brief Macro for checking for a valid EVRT state type + */ +#define PARAM_EVRT_SOURCE_ACTIVE_TYPE(n) ((n == EVRT_SRC_ACTIVE_LOW_LEVEL) || (n == EVRT_SRC_ACTIVE_HIGH_LEVEL) \ + || (n == EVRT_SRC_ACTIVE_FALLING_EDGE) || (n == EVRT_SRC_ACTIVE_RISING_EDGE)) + +/** + * @brief Initialize the EVRT + * @return Nothing + */ +void Chip_EVRT_Init (void); + +/** + * @brief Set up the type of interrupt type for a source to EVRT + * @param EVRT_Src : EVRT source, should be one of Chip_EVRT_SRC_ENUM type + * @param type : EVRT type, should be one of EVRT_SRC_ACTIVE_TYPE type + * @return Nothing + */ +void Chip_EVRT_ConfigIntSrcActiveType(Chip_EVRT_SRC_ENUM EVRT_Src, EVRT_SRC_ACTIVE_TYPE type); + +/** + * @brief Check if a source is sending interrupt to EVRT + * @param EVRT_Src : EVRT source, should be one of Chip_EVRT_SRC_ENUM type + * @return true if the interrupt from the source is pending, otherwise false + */ +IntStatus Chip_EVRT_IsSourceInterrupting(Chip_EVRT_SRC_ENUM EVRT_Src); + +/** + * @brief Enable or disable interrupt sources to EVRT + * @param EVRT_Src : EVRT source, should be one of Chip_EVRT_SRC_ENUM type + * @param state : ENABLE or DISABLE to enable or disable event router source + * @return Nothing + */ +void Chip_EVRT_SetUpIntSrc(Chip_EVRT_SRC_ENUM EVRT_Src, FunctionalState state); + +/** + * @brief De-initializes the EVRT peripheral + * @return Nothing + */ +STATIC INLINE void Chip_EVRT_DeInit(void) +{ + LPC_EVRT->CLR_EN = 0xFFFF; + LPC_EVRT->CLR_STAT = 0xFFFF; +} + +/** + * @brief Clear pending interrupt EVRT source + * @param EVRT_Src : EVRT source, should be one of Chip_EVRT_SRC_ENUM type + * @return Nothing + */ +STATIC INLINE void Chip_EVRT_ClrPendIntSrc(Chip_EVRT_SRC_ENUM EVRT_Src) +{ + LPC_EVRT->CLR_STAT = (1 << (uint8_t) EVRT_Src); +} + +/** + * @} + */ + +#ifdef __cplusplus +} +#endif + +#endif /* __EVRT_18XX_43XX_H_ */ diff --git a/bsp/xplorer4330/libraries/lpc_chip/chip_18xx_43xx/gpdma_18xx_43xx.c b/bsp/xplorer4330/libraries/lpc_chip/chip_18xx_43xx/gpdma_18xx_43xx.c new file mode 100644 index 0000000000..deb90cadf4 --- /dev/null +++ b/bsp/xplorer4330/libraries/lpc_chip/chip_18xx_43xx/gpdma_18xx_43xx.c @@ -0,0 +1,424 @@ +/* + * @brief LPC18xx/43xx DMA driver + * + * @note + * Copyright(C) NXP Semiconductors, 2012 + * All rights reserved. + * + * @par + * Software that is described herein is for illustrative purposes only + * which provides customers with programming information regarding the + * LPC products. This software is supplied "AS IS" without any warranties of + * any kind, and NXP Semiconductors and its licensor disclaim any and + * all warranties, express or implied, including all implied warranties of + * merchantability, fitness for a particular purpose and non-infringement of + * intellectual property rights. NXP Semiconductors assumes no responsibility + * or liability for the use of the software, conveys no license or rights under any + * patent, copyright, mask work right, or any other intellectual property rights in + * or to any products. NXP Semiconductors reserves the right to make changes + * in the software without notification. NXP Semiconductors also makes no + * representation or warranty that such application will be suitable for the + * specified use without further testing or modification. + * + * @par + * Permission to use, copy, modify, and distribute this software and its + * documentation is hereby granted, under NXP Semiconductors' and its + * licensor's relevant copyrights in the software, without fee, provided that it + * is used in conjunction with NXP Semiconductors microcontrollers. This + * copyright, permission, and disclaimer notice must appear in all copies of + * this code. + */ + +#include "gpdma_18xx_43xx.h" + +/***************************************************************************** + * Private types/enumerations/variables + ****************************************************************************/ + +/* Channel array to monitor free channel */ +static DMA_ChannelHandle_t ChannelHandlerArray[GPDMA_NUMBER_CHANNELS]; + +/* Optimized Peripheral Source and Destination burst size (18xx,43xx) */ +static const uint8_t GPDMA_LUTPerBurst[] = { + GPDMA_BSIZE_4, /* MEMORY */ + GPDMA_BSIZE_1, /* MAT0.0 */ + GPDMA_BSIZE_1, /* UART0 Tx */ + GPDMA_BSIZE_1, /* MAT0.1 */ + GPDMA_BSIZE_1, /* UART0 Rx */ + GPDMA_BSIZE_1, /* MAT1.0 */ + GPDMA_BSIZE_1, /* UART1 Tx */ + GPDMA_BSIZE_1, /* MAT1.1 */ + GPDMA_BSIZE_1, /* UART1 Rx */ + GPDMA_BSIZE_1, /* MAT2.0 */ + GPDMA_BSIZE_1, /* UART2 Tx */ + GPDMA_BSIZE_1, /* MAT2.1 */ + GPDMA_BSIZE_1, /* UART2 Rx */ + GPDMA_BSIZE_1, /* MAT3.0 */ + GPDMA_BSIZE_1, /* UART3 Tx */ + 0, /* SCT timer channel 0*/ + GPDMA_BSIZE_1, /* MAT3.1 */ + GPDMA_BSIZE_1, /* UART3 Rx */ + 0, /* SCT timer channel 1*/ + GPDMA_BSIZE_4, /* SSP0 Rx */ + GPDMA_BSIZE_32, /* I2S channel 0 */ + GPDMA_BSIZE_4, /* SSP0 Tx */ + GPDMA_BSIZE_32, /* I2S channel 1 */ + GPDMA_BSIZE_4, /* SSP1 Rx */ + GPDMA_BSIZE_4, /* SSP1 Tx */ + GPDMA_BSIZE_4, /* ADC 0 */ + GPDMA_BSIZE_4, /* ADC 1 */ + GPDMA_BSIZE_1, /* DAC */ + GPDMA_BSIZE_32, /* I2S channel 0 */ + GPDMA_BSIZE_32 /* I2S channel 0 */ +}; + +/* Optimized Peripheral Source and Destination transfer width (18xx,43xx) */ +static const uint8_t GPDMA_LUTPerWid[] = { + GPDMA_WIDTH_WORD, /* MEMORY */ + GPDMA_WIDTH_WORD, /* MAT0.0 */ + GPDMA_WIDTH_BYTE, /* UART0 Tx */ + GPDMA_WIDTH_WORD, /* MAT0.1 */ + GPDMA_WIDTH_BYTE, /* UART0 Rx */ + GPDMA_WIDTH_WORD, /* MAT1.0 */ + GPDMA_WIDTH_BYTE, /* UART1 Tx */ + GPDMA_WIDTH_WORD, /* MAT1.1 */ + GPDMA_WIDTH_BYTE, /* UART1 Rx */ + GPDMA_WIDTH_WORD, /* MAT2.0 */ + GPDMA_WIDTH_BYTE, /* UART2 Tx */ + GPDMA_WIDTH_WORD, /* MAT2.1 */ + GPDMA_WIDTH_BYTE, /* UART2 Rx */ + GPDMA_WIDTH_WORD, /* MAT3.0 */ + GPDMA_WIDTH_BYTE, /* UART3 Tx */ + 0, /* SCT timer channel 0*/ + GPDMA_WIDTH_WORD, /* MAT3.1 */ + GPDMA_WIDTH_BYTE, /* UART3 Rx */ + 0, /* SCT timer channel 1*/ + GPDMA_WIDTH_BYTE, /* SSP0 Rx */ + GPDMA_WIDTH_WORD, /* I2S channel 0 */ + GPDMA_WIDTH_BYTE, /* SSP0 Tx */ + GPDMA_WIDTH_WORD, /* I2S channel 1 */ + GPDMA_WIDTH_BYTE, /* SSP1 Rx */ + GPDMA_WIDTH_BYTE, /* SSP1 Tx */ + GPDMA_WIDTH_WORD, /* ADC 0 */ + GPDMA_WIDTH_WORD, /* ADC 1 */ + GPDMA_WIDTH_WORD, /* DAC */ + GPDMA_WIDTH_WORD, /* I2S channel 0 */ + GPDMA_WIDTH_WORD/* I2S channel 0 */ +}; + +/* Lookup Table of Connection Type matched with (18xx,43xx) Peripheral Data (FIFO) register base address */ +volatile static const void *GPDMA_LUTPerAddr[] = { + NULL, /* MEMORY */ + (&LPC_TIMER0->MR), /* MAT0.0 */ + (&LPC_USART0-> /*RBTHDLR.*/ THR), /* UART0 Tx */ + ((uint32_t *) &LPC_TIMER0->MR + 1), /* MAT0.1 */ + (&LPC_USART0-> /*RBTHDLR.*/ RBR), /* UART0 Rx */ + (&LPC_TIMER1->MR), /* MAT1.0 */ + (&LPC_UART1-> /*RBTHDLR.*/ THR),/* UART1 Tx */ + ((uint32_t *) &LPC_TIMER1->MR + 1), /* MAT1.1 */ + (&LPC_UART1-> /*RBTHDLR.*/ RBR),/* UART1 Rx */ + (&LPC_TIMER2->MR), /* MAT2.0 */ + (&LPC_USART2-> /*RBTHDLR.*/ THR), /* UART2 Tx */ + ((uint32_t *) &LPC_TIMER2->MR + 1), /* MAT2.1 */ + (&LPC_USART2-> /*RBTHDLR.*/ RBR), /* UART2 Rx */ + (&LPC_TIMER3->MR), /* MAT3.0 */ + (&LPC_USART3-> /*RBTHDLR.*/ THR), /* UART3 Tx */ + 0, /* SCT timer channel 0*/ + ((uint32_t *) &LPC_TIMER3->MR + 1), /* MAT3.1 */ + (&LPC_USART3-> /*RBTHDLR.*/ RBR), /* UART3 Rx */ + 0, /* SCT timer channel 1*/ + (&LPC_SSP0->DR), /* SSP0 Rx */ + (&LPC_I2S0->TXFIFO), /* I2S channel 0 */ + (&LPC_SSP0->DR), /* SSP0 Tx */ + (&LPC_I2S0->RXFIFO), /* I2S channel 1 */ + (&LPC_SSP1->DR), /* SSP1 Rx */ + (&LPC_SSP1->DR), /* SSP1 Tx */ + (&LPC_ADC0->GDR), /* ADC 0 */ + (&LPC_ADC1->GDR), /* ADC 1 */ + (&LPC_DAC->CR), /* DAC */ + (&LPC_I2S0->TXFIFO), /* I2S channel 0 */ + (&LPC_I2S0->RXFIFO) /* I2S channel 0 */ +}; + +/***************************************************************************** + * Public types/enumerations/variables + ****************************************************************************/ + +/***************************************************************************** + * Private functions + ****************************************************************************/ + +/* Control which set of peripherals is connected to the DMA controller */ +static uint8_t DMAMUX_Config(uint32_t gpdma_peripheral_connection_number) +{ + uint8_t function, channel; + + switch (gpdma_peripheral_connection_number) { + case GPDMA_CONN_MAT0_0: + function = 0; + channel = 1; + break; + + case GPDMA_CONN_UART0_Tx: + function = 1; + channel = 1; + break; + + case GPDMA_CONN_MAT0_1: + function = 0; + channel = 2; + break; + + case GPDMA_CONN_UART0_Rx: + function = 1; + channel = 2; + break; + + case GPDMA_CONN_MAT1_0: + function = 0; + channel = 3; + break; + + case GPDMA_CONN_UART1_Tx: + function = 1; + channel = 3; + break; + + case GPDMA_CONN_MAT1_1: + function = 0; + channel = 4; + break; + + case GPDMA_CONN_UART1_Rx: + function = 1; + channel = 4; + break; + + case GPDMA_CONN_MAT2_0: + function = 0; + channel = 5; + break; + + case GPDMA_CONN_UART2_Tx: + function = 1; + channel = 5; + break; + + case GPDMA_CONN_MAT2_1: + function = 0; + channel = 6; + break; + + case GPDMA_CONN_UART2_Rx: + function = 1; + channel = 6; + break; + + case GPDMA_CONN_MAT3_0: + function = 0; + channel = 7; + break; + + case GPDMA_CONN_UART3_Tx: + function = 1; + channel = 7; + break; + + case GPDMA_CONN_SCT_0: + function = 2; + channel = 7; + break; + + case GPDMA_CONN_MAT3_1: + function = 0; + channel = 8; + break; + + case GPDMA_CONN_UART3_Rx: + function = 1; + channel = 8; + break; + + case GPDMA_CONN_SCT_1: + function = 2; + channel = 8; + break; + + case GPDMA_CONN_SSP0_Rx: + function = 0; + channel = 9; + break; + + case GPDMA_CONN_I2S_Tx_Channel_0: + case GPDMA_CONN_I2S_Rx_Channel_0: + function = 1; + channel = 9; + break; + + case GPDMA_CONN_SSP0_Tx: + function = 0; + channel = 10; + break; + + case GPDMA_CONN_I2S_Tx_Channel_1: + case GPDMA_CONN_I2S_Rx_Channel_1: + function = 1; + channel = 10; + break; + + case GPDMA_CONN_SSP1_Rx: + function = 0; + channel = 11; + break; + + case GPDMA_CONN_SSP1_Tx: + function = 0; + channel = 12; + break; + + case GPDMA_CONN_ADC_0: + function = 0; + channel = 13; + break; + + case GPDMA_CONN_ADC_1: + function = 0; + channel = 14; + break; + + case GPDMA_CONN_DAC: + function = 0; + channel = 15; + break; + + default: + function = 3; + channel = 15; + break; + } + /* Set select function to dmamux register */ + if (0 != gpdma_peripheral_connection_number) { + LPC_CREG->DMAMUX &= ~(0x03 << (2 * channel)); + LPC_CREG->DMAMUX |= (function << (2 * channel)); + } + return channel; +} + +/***************************************************************************** + * Public functions + ****************************************************************************/ + +/* Initialize the GPDMA */ +void Chip_GPDMA_Init(void) +{ + uint8_t i; + IP_GPDMA_Init(LPC_GPDMA); + /* Reset all channels are free */ + for (i = 0; i < GPDMA_NUMBER_CHANNELS; i++) + ChannelHandlerArray[i].ChannelStatus = DISABLE; +} + +/* Stop a stream DMA transfer */ +void Chip_DMA_Stop(uint8_t ChannelNum) +{ + IP_GPDMA_ChannelCmd(LPC_GPDMA, (ChannelNum), DISABLE); + if (Chip_GPDMA_IntGetStatus(GPDMA_STAT_INTTC, ChannelNum)) { + /* Clear terminate counter Interrupt pending */ + Chip_GPDMA_ClearIntPending(GPDMA_STATCLR_INTTC, ChannelNum); + } + if (Chip_GPDMA_IntGetStatus(GPDMA_STAT_INTERR, ChannelNum)) { + /* Clear terminate counter Interrupt pending */ + Chip_GPDMA_ClearIntPending(GPDMA_STATCLR_INTERR, ChannelNum); + } + ChannelHandlerArray[ChannelNum].ChannelStatus = DISABLE; +} + +/* The GPDMA stream interrupt status checking */ +Status Chip_DMA_Interrupt(uint8_t ChannelNum) +{ + + if (Chip_GPDMA_IntGetStatus(GPDMA_STAT_INT, ChannelNum)) { + /* Check counter terminal status */ + if (Chip_GPDMA_IntGetStatus(GPDMA_STAT_INTTC, ChannelNum)) { + /* Clear terminate counter Interrupt pending */ + Chip_GPDMA_ClearIntPending(GPDMA_STATCLR_INTTC, ChannelNum); + return SUCCESS; + } + /* Check error terminal status */ + if (Chip_GPDMA_IntGetStatus(GPDMA_STAT_INTERR, ChannelNum)) { + /* Clear error counter Interrupt pending */ + + Chip_GPDMA_ClearIntPending(GPDMA_STATCLR_INTERR, ChannelNum); + return ERROR; + } + } + return ERROR; +} + +/* Do a DMA transfer M2M, M2P,P2M or P2P */ +void Chip_DMA_Transfer(uint8_t ChannelNum, uint32_t src, uint32_t dst, FlowControlType TransferType, uint32_t Size) +{ + GPDMA_Channel_CFG_Type GPDMACfg; + uint8_t SrcPeripheral = 0, DstPeripheral = 0; + + GPDMACfg.ChannelNum = ChannelNum; + GPDMACfg.TransferType = TransferType; + GPDMACfg.TransferSize = Size; + + switch (TransferType) { + case GPDMA_TRANSFERTYPE_M2M_CONTROLLER_DMA: + GPDMACfg.SrcAddr = (uint32_t) src; + GPDMACfg.DstAddr = (uint32_t) dst; + src = 0; dst = 0; + GPDMACfg.TransferWidth = GPDMA_WIDTH_BYTE; + break; + + case GPDMA_TRANSFERTYPE_M2P_CONTROLLER_DMA: + case GPDMA_TRANSFERTYPE_M2P_CONTROLLER_PERIPHERAL: + GPDMACfg.SrcAddr = (uint32_t) src; + src = 0; + GPDMACfg.DstAddr = (uint32_t) GPDMA_LUTPerAddr[dst]; + DstPeripheral = DMAMUX_Config(dst); + break; + + case GPDMA_TRANSFERTYPE_P2M_CONTROLLER_DMA: + case GPDMA_TRANSFERTYPE_P2M_CONTROLLER_PERIPHERAL: + GPDMACfg.SrcAddr = (uint32_t) GPDMA_LUTPerAddr[src]; + GPDMACfg.DstAddr = (uint32_t) dst; + SrcPeripheral = DMAMUX_Config(src); + dst = 0; + break; + + case GPDMA_TRANSFERTYPE_P2P_CONTROLLER_DMA: + case GPDMA_TRANSFERTYPE_P2P_CONTROLLER_DestPERIPHERAL: + case GPDMA_TRANSFERTYPE_P2P_CONTROLLER_SrcPERIPHERAL: + GPDMACfg.SrcAddr = (uint32_t) GPDMA_LUTPerAddr[src]; + GPDMACfg.DstAddr = (uint32_t) GPDMA_LUTPerAddr[dst]; + SrcPeripheral = DMAMUX_Config(src); + DstPeripheral = DMAMUX_Config(dst); + break; + + default: + break; + } + + IP_GPDMA_Setup(LPC_GPDMA, &GPDMACfg, (uint32_t) GPDMA_LUTPerBurst[src], (uint32_t) GPDMA_LUTPerBurst[dst], + (uint32_t) GPDMA_LUTPerWid[src], (uint32_t) GPDMA_LUTPerWid[dst], (uint32_t) GPDMA_LUTPerAddr[src], + (uint32_t) GPDMA_LUTPerAddr[dst], SrcPeripheral, DstPeripheral); + + /* Start the Channel */ + IP_GPDMA_ChannelCmd(LPC_GPDMA, ChannelNum, ENABLE); +} + +/* Get a free GPDMA channel for one DMA connection */ +uint8_t Chip_DMA_GetFreeChannel(uint32_t PeripheralConnection_ID) +{ + uint8_t temp = 0; + for (temp = 0; temp < GPDMA_NUMBER_CHANNELS; temp++) + if (!Chip_GPDMA_IntGetStatus(GPDMA_STAT_ENABLED_CH, + temp) && (ChannelHandlerArray[temp].ChannelStatus == DISABLE)) { + ChannelHandlerArray[temp].ChannelStatus = ENABLE; + return temp; + } + return 0; +} diff --git a/bsp/xplorer4330/libraries/lpc_chip/chip_18xx_43xx/gpdma_18xx_43xx.h b/bsp/xplorer4330/libraries/lpc_chip/chip_18xx_43xx/gpdma_18xx_43xx.h new file mode 100644 index 0000000000..0ef96cca25 --- /dev/null +++ b/bsp/xplorer4330/libraries/lpc_chip/chip_18xx_43xx/gpdma_18xx_43xx.h @@ -0,0 +1,167 @@ +/* + * @brief LPC18xx/43xx DMA driver + * + * @note + * Copyright(C) NXP Semiconductors, 2012 + * All rights reserved. + * + * @par + * Software that is described herein is for illustrative purposes only + * which provides customers with programming information regarding the + * LPC products. This software is supplied "AS IS" without any warranties of + * any kind, and NXP Semiconductors and its licensor disclaim any and + * all warranties, express or implied, including all implied warranties of + * merchantability, fitness for a particular purpose and non-infringement of + * intellectual property rights. NXP Semiconductors assumes no responsibility + * or liability for the use of the software, conveys no license or rights under any + * patent, copyright, mask work right, or any other intellectual property rights in + * or to any products. NXP Semiconductors reserves the right to make changes + * in the software without notification. NXP Semiconductors also makes no + * representation or warranty that such application will be suitable for the + * specified use without further testing or modification. + * + * @par + * Permission to use, copy, modify, and distribute this software and its + * documentation is hereby granted, under NXP Semiconductors' and its + * licensor's relevant copyrights in the software, without fee, provided that it + * is used in conjunction with NXP Semiconductors microcontrollers. This + * copyright, permission, and disclaimer notice must appear in all copies of + * this code. + */ + +#ifndef __GPDMA_18XX_43XX_H_ +#define __GPDMA_18XX_43XX_H_ + +#include "chip.h" + +#ifdef __cplusplus +extern "C" { +#endif + +/** @defgroup GPDMA_18XX_43XX CHIP: LPC18xx/43xx General Purpose DMA driver + * @ingroup CHIP_18XX_43XX_Drivers + * @{ + */ + +/** Number of channels on GPDMA */ +#define GPDMA_NUMBER_CHANNELS 8 + +/** DMA Connection number definitions */ +#define GPDMA_CONN_MEMORY ((0UL)) /**< MEMORY */ +#define GPDMA_CONN_MAT0_0 ((1UL)) /**< MAT0.0 */ +#define GPDMA_CONN_UART0_Tx ((2UL)) /**< UART0 Tx */ +#define GPDMA_CONN_MAT0_1 ((3UL)) /**< MAT0.1 */ +#define GPDMA_CONN_UART0_Rx ((4UL)) /**< UART0 Rx */ +#define GPDMA_CONN_MAT1_0 ((5UL)) /**< MAT1.0 */ +#define GPDMA_CONN_UART1_Tx ((6UL)) /**< UART1 Tx */ +#define GPDMA_CONN_MAT1_1 ((7UL)) /**< MAT1.1 */ +#define GPDMA_CONN_UART1_Rx ((8UL)) /**< UART1 Rx */ +#define GPDMA_CONN_MAT2_0 ((9UL)) /**< MAT2.0 */ +#define GPDMA_CONN_UART2_Tx ((10UL)) /**< UART2 Tx */ +#define GPDMA_CONN_MAT2_1 ((11UL)) /**< MAT2.1 */ +#define GPDMA_CONN_UART2_Rx ((12UL)) /**< UART2 Rx */ +#define GPDMA_CONN_MAT3_0 ((13UL)) /**< MAT3.0 */ +#define GPDMA_CONN_UART3_Tx ((14UL)) /**< UART3 Tx */ +#define GPDMA_CONN_SCT_0 ((15UL)) /**< SCT timer channel 0*/ +#define GPDMA_CONN_MAT3_1 ((16UL)) /**< MAT3.1 */ +#define GPDMA_CONN_UART3_Rx ((17UL)) /**< UART3 Rx */ +#define GPDMA_CONN_SCT_1 ((18UL)) /**< SCT timer channel 1*/ +#define GPDMA_CONN_SSP0_Rx ((19UL)) /**< SSP0 Rx */ +#define GPDMA_CONN_I2S_Tx_Channel_0 ((20UL)) /**< I2S channel 0 */ +#define GPDMA_CONN_SSP0_Tx ((21UL)) /**< SSP0 Tx */ +#define GPDMA_CONN_I2S_Rx_Channel_1 ((22UL)) /**< I2S channel 1 */ +#define GPDMA_CONN_SSP1_Rx ((23UL)) /**< SSP1 Rx */ +#define GPDMA_CONN_SSP1_Tx ((24UL)) /**< SSP1 Tx */ +#define GPDMA_CONN_ADC_0 ((25UL)) /**< ADC 0 */ +#define GPDMA_CONN_ADC_1 ((26UL)) /**< ADC 1 */ +#define GPDMA_CONN_DAC ((27UL)) /**< DAC */ +#define GPDMA_CONN_I2S_Tx_Channel_1 ((28UL)) /**< I2S channel 0 */ +#define GPDMA_CONN_I2S_Rx_Channel_0 ((29UL)) /**< I2S channel 0 */ + +/** Burst size in Source and Destination definitions */ +#define GPDMA_BSIZE_1 ((0UL)) /**< Burst size = 1 */ +#define GPDMA_BSIZE_4 ((1UL)) /**< Burst size = 4 */ +#define GPDMA_BSIZE_8 ((2UL)) /**< Burst size = 8 */ +#define GPDMA_BSIZE_16 ((3UL)) /**< Burst size = 16 */ +#define GPDMA_BSIZE_32 ((4UL)) /**< Burst size = 32 */ +#define GPDMA_BSIZE_64 ((5UL)) /**< Burst size = 64 */ +#define GPDMA_BSIZE_128 ((6UL)) /**< Burst size = 128 */ +#define GPDMA_BSIZE_256 ((7UL)) /**< Burst size = 256 */ + +/** Width in Source transfer width and Destination transfer width definitions */ +#define GPDMA_WIDTH_BYTE ((0UL)) /**< Width = 1 byte */ +#define GPDMA_WIDTH_HALFWORD ((1UL)) /**< Width = 2 bytes */ +#define GPDMA_WIDTH_WORD ((2UL)) /**< Width = 4 bytes */ + +/** Flow control definitions */ +#define DMA_CONTROLLER 0 /**< Flow control is DMA controller*/ +#define SRC_PER_CONTROLLER 1 /**< Flow control is Source peripheral controller*/ +#define DST_PER_CONTROLLER 2 /**< Flow control is Destination peripheral controller*/ + +typedef struct { + FunctionalState ChannelStatus; +} DMA_ChannelHandle_t; + +#define Chip_GPDMA_IntGetStatus(type, channel) IP_GPDMA_IntGetStatus(LPC_GPDMA, type, channel) + +#define Chip_GPDMA_ClearIntPending(type, channel) IP_GPDMA_ClearIntPending(LPC_GPDMA, type, channel) + +#define Chip_GPDMA_ChannelCmd(channelNum, NewState) IP_GPDMA_ChannelCmd(LPC_GPDMA, channelNum, NewState) + +/** + * @brief Initialize the GPDMA + * @return Nothing + */ +void Chip_GPDMA_Init(void); + +/** + * @brief Stop a stream DMA transfer + * @param ChannelNum : Channel Number to be closed + * @return Nothing + */ +void Chip_DMA_Stop(uint8_t ChannelNum); + +/** + * @brief The GPDMA stream interrupt status checking + * @param ChannelNum : Channel Number to be checked on interruption + * @return Status: + * - SUCCESS : DMA transfer success + * - ERROR : DMA transfer failed + */ +Status Chip_DMA_Interrupt(uint8_t ChannelNum); + +/** + * @brief Get a free GPDMA channel for one DMA connection + * @param PeripheralConnection_ID : Some chip fix each peripheral DMA connection on a specified channel ( have not used in 18xx/43xx ) + * @return The channel number which is selected + */ +uint8_t Chip_DMA_GetFreeChannel(uint32_t PeripheralConnection_ID); + +/** + * @brief Do a DMA transfer M2M, M2P,P2M or P2P + * @param ChannelNum : Channel used for transfer + * @param src : Address of Memory or PeripheralConnection_ID which is the source + * @param dst : Address of Memory or PeripheralConnection_ID which is the destination + * @param TransferType : Select the transfer controller and the type of transfer. Should be: + * - GPDMA_TRANSFERTYPE_M2M_CONTROLLER_DMA + * - GPDMA_TRANSFERTYPE_M2P_CONTROLLER_DMA + * - GPDMA_TRANSFERTYPE_P2M_CONTROLLER_DMA + * - GPDMA_TRANSFERTYPE_P2P_CONTROLLER_DMA + * - GPDMA_TRANSFERTYPE_P2P_CONTROLLER_DestPERIPHERAL + * - GPDMA_TRANSFERTYPE_M2P_CONTROLLER_PERIPHERAL + * - GPDMA_TRANSFERTYPE_P2M_CONTROLLER_PERIPHERAL + * - GPDMA_TRANSFERTYPE_P2P_CONTROLLER_SrcPERIPHERAL + * @param Size : The number of DMA transfers + * @return Nothing + */ +void Chip_DMA_Transfer(uint8_t ChannelNum, uint32_t src, uint32_t dst, FlowControlType TransferType, uint32_t Size); + +/** + * @} + */ + +#ifdef __cplusplus +} +#endif + +#endif /* __GPDMA_18XX_43XX_H_ */ diff --git a/bsp/xplorer4330/libraries/lpc_chip/chip_18xx_43xx/gpio_18xx_43xx.c b/bsp/xplorer4330/libraries/lpc_chip/chip_18xx_43xx/gpio_18xx_43xx.c new file mode 100644 index 0000000000..366c4aa510 --- /dev/null +++ b/bsp/xplorer4330/libraries/lpc_chip/chip_18xx_43xx/gpio_18xx_43xx.c @@ -0,0 +1,53 @@ +/** @brief LPC18xx/43xx GPIO driver** Copyright(C) NXP Semiconductors, 2012 + * All rights reserved. + * + * Software that is described herein is for illustrative purposes only + * which provides customers with programming information regarding the + * LPC products. This software is supplied "AS IS" without any warranties of + * any kind, and NXP Semiconductors and its licensor disclaim any and + * all warranties, express or implied, including all implied warranties of + * merchantability, fitness for a particular purpose and non-infringement of + * intellectual property rights. NXP Semiconductors assumes no responsibility + * or liability for the use of the software, conveys no license or rights under any + * patent, copyright, mask work right, or any other intellectual property rights in + * or to any products. NXP Semiconductors reserves the right to make changes + * in the software without notification. NXP Semiconductors also makes no + * representation or warranty that such application will be suitable for the + * specified use without further testing or modification. + * + * Permission to use, copy, modify, and distribute this software and its + * documentation is hereby granted, under NXP Semiconductors' and its + * licensor's relevant copyrights in the software, without fee, provided that it + * is used in conjunction with NXP Semiconductors microcontrollers. This + * copyright, permission, and disclaimer notice must appear in all copies of + * this code. + */ + +#include "gpio_18xx_43xx.h" + +/***************************************************************************** + * Private types/enumerations/variables + ****************************************************************************/ + +/***************************************************************************** + * Public types/enumerations/variables + ****************************************************************************/ + +/***************************************************************************** + * Private functions + ****************************************************************************/ + +/***************************************************************************** + * Public functions + ****************************************************************************/ + +/* Set Direction for a GPIO port */ +void Chip_GPIO_SetDir(uint8_t portNum, uint32_t bitValue, uint8_t out) +{ + if (out) { + LPC_GPIO_PORT->DIR[portNum] |= bitValue; + } + else { + LPC_GPIO_PORT->DIR[portNum] &= ~bitValue; + } +} diff --git a/bsp/xplorer4330/libraries/lpc_chip/chip_18xx_43xx/gpio_18xx_43xx.h b/bsp/xplorer4330/libraries/lpc_chip/chip_18xx_43xx/gpio_18xx_43xx.h new file mode 100644 index 0000000000..d6bc3549a4 --- /dev/null +++ b/bsp/xplorer4330/libraries/lpc_chip/chip_18xx_43xx/gpio_18xx_43xx.h @@ -0,0 +1,308 @@ +/* + * @brief LPC18xx/43xx GPIO driver + * + * Copyright(C) NXP Semiconductors, 2012 + * All rights reserved. + * + * Software that is described herein is for illustrative purposes only + * which provides customers with programming information regarding the + * LPC products. This software is supplied "AS IS" without any warranties of + * any kind, and NXP Semiconductors and its licensor disclaim any and + * all warranties, express or implied, including all implied warranties of + * merchantability, fitness for a particular purpose and non-infringement of + * intellectual property rights. NXP Semiconductors assumes no responsibility + * or liability for the use of the software, conveys no license or rights under any + * patent, copyright, mask work right, or any other intellectual property rights in + * or to any products. NXP Semiconductors reserves the right to make changes + * in the software without notification. NXP Semiconductors also makes no + * representation or warranty that such application will be suitable for the + * specified use without further testing or modification. + * + * Permission to use, copy, modify, and distribute this software and its + * documentation is hereby granted, under NXP Semiconductors' and its + * licensor's relevant copyrights in the software, without fee, provided that it + * is used in conjunction with NXP Semiconductors microcontrollers. This + * copyright, permission, and disclaimer notice must appear in all copies of + * this code. + */ + +#ifndef __GPIO_18XX_43XX_H_ +#define __GPIO_18XX_43XX_H_ + +#include "chip.h" + +#ifdef __cplusplus +extern "C" { +#endif + +/** @defgroup GPIO_18XX_43XX CHIP: LPC18xx/43xx GPIO Driver + * @ingroup CHIP_18XX_43XX_Drivers + * @{ + */ + +/** + * @brief Initialize GPIO block + * @return Nothing + */ +STATIC INLINE void Chip_GPIO_Init(void) +{ + IP_GPIO_Init(LPC_GPIO_PORT); +} + +/** + * @brief Set a GPIO port/bit state + * @param Port : GPIO port to set + * @param Bit : GPIO bit to set + * @param Setting : true for high, false for low + * @return Nothing + */ +STATIC INLINE void Chip_GPIO_WritePortBit(uint32_t Port, uint8_t Bit, bool Setting) +{ + IP_GPIO_WritePortBit(LPC_GPIO_PORT, Port, Bit, Setting); +} + +/** + * @brief Seta GPIO direction + * @param Port : GPIO port to set + * @param Bit : GPIO bit to set + * @param Setting : true for output, false for input + * @return Nothing + */ +STATIC INLINE void Chip_GPIO_WriteDirBit(uint32_t Port, uint8_t Bit, bool Setting) +{ + IP_GPIO_WriteDirBit(LPC_GPIO_PORT, Port, Bit, Setting); +} + +/** + * @brief Read a GPIO state + * @param Port : GPIO port to read + * @param Bit : GPIO bit to read + * @return true of the GPIO is high, false if low + */ +STATIC INLINE bool Chip_GPIO_ReadPortBit(uint32_t Port, uint8_t Bit) +{ + return IP_GPIO_ReadPortBit(LPC_GPIO_PORT, Port, Bit); +} + +/** + * @brief Read a GPIO direction (out ot in) + * @param Port : GPIO port to read + * @param Bit : GPIO bit to read + * @return true of the GPIO is an output, false if input + */ +STATIC INLINE bool Chip_GPIO_ReadDirBit(uint32_t Port, uint8_t Bit) +{ + return IP_GPIO_ReadDirBit(LPC_GPIO_PORT, Port, Bit); +} + +/** + * @brief Enable GPIO Interrupt + * @param PortNum : GPIO port number interrupt, should be: 0 to 7 + * @param BitValue : GPIO bit to enable (Not used) + * @param IntMode : Interrupt mode, should be: + * 0: Rising edge interrupt mode + * 1: Falling edge interrupt mode + * 2: Active-High interrupt mode + * 3: Active-Low interrupt mode + * @return None + */ +STATIC INLINE void Chip_GPIO_IntCmd(uint8_t PortNum, uint8_t BitValue, Gpio_PinInt_Mode_Enum IntMode) +{ + IP_GPIOPININT_IntCmd(LPC_GPIO_PIN_INT, PortNum, IntMode); +} + +/** + * @brief Get GPIO Interrupt Status + * @param PortNum : GPIO port number interrupt, should be: 0 to 7 + * @param PinNum : GPIO pin to check (Not used) + * @param IntMode : Interrupt mode (Not used) + * @return true if interrupt is pending, otherwise false + */ +STATIC INLINE bool Chip_GPIO_IntGetStatus(uint8_t PortNum, uint8_t PinNum, uint8_t IntMode) +{ + return IP_GPIOPININT_IntGetStatus(LPC_GPIO_PIN_INT, PortNum); +} + +/** + * @brief Clear GPIO Interrupt (Edge interrupt cases only) + * @param PortNum : GPIO port number interrupt, should be: 0 to 7 + * @param BitValue : GPIO bit to clear (Not used) + * @return None + */ +STATIC INLINE void Chip_GPIO_IntClear(uint8_t PortNum, uint8_t BitValue) +{ + IP_GPIOPININT_IntClear(LPC_GPIO_PIN_INT, PortNum); +} + +/** + * @brief GPIO Group Interrupt Pin Initialization + * @param pGPIOGPINT : Pointer to GPIOIR register block + * @param PortComb : GPIO group combined enable, should be: 0 (OR functionality) and 1 (AND functionality) + * @param PortTrigger : GPIO group interrupt trigger, should be: 0 (Edge-triggered) 1 (Level triggered) + * @return None + */ +STATIC INLINE void Chip_GPIOGP_IntInit(IP_GPIOGROUPINT_001_Type *pGPIOGPINT, uint8_t PortComb, uint8_t PortTrigger) +{ + IP_GPIOGP_IntInit(pGPIOGPINT, PortComb, PortTrigger); +} + +/** + * @brief GPIO Group Interrupt Pin Add to Group + * @param pGPIOGPINT : Pointer to GPIOIR register block + * @param PortNum : GPIO port number, should be 0 to 7 + * @param PinNum : GPIO pin number, should be 0 to 31 + * @param ActiveMode : GPIO active mode, should be 0 (active LOW) and 1 (active HIGH) + * @return None + */ +STATIC INLINE void Chip_GPIOGP_IntPinAdd(IP_GPIOGROUPINT_001_Type *pGPIOGPINT, + uint8_t PortNum, + uint8_t PinNum, + bool ActiveMode) +{ + IP_GPIOGP_IntPinAdd(pGPIOGPINT, PortNum, PinNum, ActiveMode); +} + +/** + * @brief GPIO Group Interrupt Pin Remove from Group + * @param pGPIOGPINT : Pointer to GPIOIR register block + * @param PortNum : GPIO port number, should be 0 to 7 + * @param PinNum : GPIO pin number, should be 0 to 31 + * @return None + */ +STATIC INLINE void Chip_GPIOGP_IntPinRemove(IP_GPIOGROUPINT_001_Type *pGPIOGPINT, uint8_t PortNum, uint8_t PinNum) +{ + IP_GPIOGP_IntPinRemove(pGPIOGPINT, PortNum, PinNum); +} + +/** + * @brief Get GPIO Group Interrupt Get Status + * @param pGPIOGPINT : Pointer to GPIOIR register block + * @return true if interrupt is pending, otherwise false + */ +STATIC INLINE bool Chip_GPIOGP_IntGetStatus(IP_GPIOGROUPINT_001_Type *pGPIOGPINT) +{ + return IP_GPIOGP_IntGetStatus(pGPIOGPINT); +} + +/** + * @brief Clear GPIO Group Interrupt + * @param pGPIOGPINT : Pointer to GPIOIR register block + * @return None + */ +STATIC INLINE void Chip_GPIOGP_IntClear(IP_GPIOGROUPINT_001_Type *pGPIOGPINT) +{ + IP_GPIOGP_IntClear(pGPIOGPINT); +} + +/** + * @brief Set Direction for a GPIO port + * @param portNum : Port Number + * @param bitValue : GPIO bit to set + * @param out : Direction value, 0 = input, !0 = output + * @return None + * Bits set to '0' are not altered. + */ +void Chip_GPIO_SetDir(uint8_t portNum, uint32_t bitValue, uint8_t out); + +/** + * @brief Set Direction for a GPIO port + * @param portNum : Port Number + * @param bitValue : GPIO bit to set + * @param out : Direction value, 0 = input, !0 = output + * @return None + * Bits set to '0' are not altered. + */ +STATIC INLINE void Chip_FIO_SetDir(uint8_t portNum, uint32_t bitValue, uint8_t out) +{ + /* Same with Chip_GPIO_SetDir() */ + Chip_GPIO_SetDir(portNum, bitValue, out); +} + +/** + * @brief Set a GPIO port/bit to the high state + * @param portNum : Port number + * @param bitValue : Bit(s) in the port to set high + * @return None + * Any bit set as a '0' will not have it's state changed. This only + * applies to ports configured as an output. + */ +STATIC INLINE void Chip_FIO_SetValue(uint8_t portNum, uint32_t bitValue) +{ + /* Same with GPIO_SetValue() */ + LPC_GPIO_PORT->SET[portNum] = bitValue; +} + +/** + * @brief Set a GPIO port/bit to the low state + * @param portNum : Port number + * @param bitValue : Bit(s) in the port to set low + * @return None + * Any bit set as a '0' will not have it's state changed. This only + * applies to ports configured as an output. + */ +STATIC INLINE void Chip_FIO_ClearValue(uint8_t portNum, uint32_t bitValue) +{ + /* Same with GPIO_ClearValue() */ + LPC_GPIO_PORT->CLR[portNum] = bitValue; +} + +/** + * @brief Read current bit states for the selected port + * @param portNum : Port number to read + * @return Current value of GPIO port + * The current states of the bits for the port are read, regardless of + * whether the GPIO port bits are input or output. + */ +STATIC INLINE uint32_t Chip_FIO_ReadValue(uint8_t portNum) +{ + /* Same with GPIO_ReadValue() */ + return LPC_GPIO_PORT->PIN[portNum]; +} + +/** + * @brief Set a GPIO port/bit to the high state + * @param portNum : Port number + * @param bitValue : Bit(s) in the port to set high + * @return None + * Any bit set as a '0' will not have it's state changed. This only + * applies to ports configured as an output. + */ +STATIC INLINE void Chip_GPIO_SetValue(uint8_t portNum, uint32_t bitValue) +{ + LPC_GPIO_PORT->SET[portNum] = bitValue; +} + +/** + * @brief Set a GPIO port/bit to the low state + * @param portNum : Port number + * @param bitValue : Bit(s) in the port to set low + * @return None + * Any bit set as a '0' will not have it's state changed. This only + * applies to ports configured as an output. + */ +STATIC INLINE void Chip_GPIO_ClearValue(uint8_t portNum, uint32_t bitValue) +{ + LPC_GPIO_PORT->CLR[portNum] = bitValue; +} + +/** + * @brief Read current bit states for the selected port + * @param portNum : Port number to read + * @return Current value of GPIO port + * The current states of the bits for the port are read, regardless of + * whether the GPIO port bits are input or output. + */ +STATIC INLINE uint32_t Chip_GPIO_ReadValue(uint8_t portNum) +{ + return LPC_GPIO_PORT->PIN[portNum]; +} + +/** + * @} + */ + + #ifdef __cplusplus +} +#endif + +#endif /* __GPIO_18XX_43XX_H_ */ diff --git a/bsp/xplorer4330/libraries/lpc_chip/chip_18xx_43xx/i2c_18xx_43xx.c b/bsp/xplorer4330/libraries/lpc_chip/chip_18xx_43xx/i2c_18xx_43xx.c new file mode 100644 index 0000000000..ee55e13954 --- /dev/null +++ b/bsp/xplorer4330/libraries/lpc_chip/chip_18xx_43xx/i2c_18xx_43xx.c @@ -0,0 +1,313 @@ +/* + * @brief LPC18xx/43xx I2C driver + * + * @note + * Copyright(C) NXP Semiconductors, 2012 + * All rights reserved. + * + * @par + * Software that is described herein is for illustrative purposes only + * which provides customers with programming information regarding the + * LPC products. This software is supplied "AS IS" without any warranties of + * any kind, and NXP Semiconductors and its licensor disclaim any and + * all warranties, express or implied, including all implied warranties of + * merchantability, fitness for a particular purpose and non-infringement of + * intellectual property rights. NXP Semiconductors assumes no responsibility + * or liability for the use of the software, conveys no license or rights under any + * patent, copyright, mask work right, or any other intellectual property rights in + * or to any products. NXP Semiconductors reserves the right to make changes + * in the software without notification. NXP Semiconductors also makes no + * representation or warranty that such application will be suitable for the + * specified use without further testing or modification. + * + * @par + * Permission to use, copy, modify, and distribute this software and its + * documentation is hereby granted, under NXP Semiconductors' and its + * licensor's relevant copyrights in the software, without fee, provided that it + * is used in conjunction with NXP Semiconductors microcontrollers. This + * copyright, permission, and disclaimer notice must appear in all copies of + * this code. + */ + +#include "i2c_18xx_43xx.h" +#include "scu_18xx_43xx.h" + +/***************************************************************************** + * Private types/enumerations/variables + ****************************************************************************/ + +#define MAX_TX_BUFFER_SIZE 10 /* Maximum transmit buffer size in Chip_I2C_MasterWriteReg() function */ + +static uint32_t i2cClockrate[2]; +static I2C_M_SETUP_Type TransferMCfg; +static uint8_t p_regAddr; +static uint8_t tx_buffer[MAX_TX_BUFFER_SIZE]; + +/***************************************************************************** + * Public types/enumerations/variables + ****************************************************************************/ + +/***************************************************************************** + * Private functions + ****************************************************************************/ + +/* Determine clock for uart BASED ON SELECTED uart */ +static CCU_CLK_T Chip_I2C_DetermineClk(LPC_I2C_Type *I2Cx) { + + CCU_CLK_T i2cclk; + + /* Pick clock for uart BASED ON SELECTED uart */ + if (I2Cx == LPC_I2C0) { + i2cclk = CLK_APB1_I2C0; + } + else { + i2cclk = CLK_APB3_I2C1; + } + + return i2cclk; +} + +/* Get UART bus number BASED ON SELECTED uart */ +static I2C_ID_Type Chip_I2C_Get_BusNum(LPC_I2C_Type *I2Cx) +{ + if (I2Cx == LPC_I2C1) { + return I2C1; + } + + return I2C0; +} + +/***************************************************************************** + * Public functions + ****************************************************************************/ + +/* Initializes the LPC_I2C peripheral with specified parameter */ +void Chip_I2C_Init(LPC_I2C_Type *I2Cx) +{ + /* Enable I2C Clocking */ + // Chip_Clock_EnableOpts(Chip_I2C_DetermineClk(I2Cx), false, false, 1); + Chip_Clock_Enable(Chip_I2C_DetermineClk(I2Cx)); + + IP_I2C_Init(I2Cx); +} + +/* De-initializes the I2C peripheral registers to their default reset values */ +void Chip_I2C_DeInit(LPC_I2C_Type *I2Cx) +{ + IP_I2C_DeInit(I2Cx); + + /* Disable UART clocking */ + Chip_Clock_Disable(Chip_I2C_DetermineClk(I2Cx)); +} + +/* Set up clock rate for LPC_I2C peripheral */ +void Chip_I2C_SetClockRate(LPC_I2C_Type *I2Cx, uint32_t clockrate) +{ + if (I2Cx == LPC_I2C0) { + i2cClockrate[0] = clockrate; + /* Select weather standard, fast, fast plus mode*/ + if (clockrate >= 1000000) { /* Fast mode plus: 1MHz, high speed 3.4MHz */ + Chip_SCU_I2C0PinConfig(I2C0_FAST_MODE_PLUS); + } + else { /* standard 100KHz, fast 400KHz */ + Chip_SCU_I2C0PinConfig(I2C0_STANDARD_FAST_MODE); + } + } + else if (I2Cx == LPC_I2C1) { + i2cClockrate[1] = clockrate; + /* Check if I2C1 run fast mode*/ + if (clockrate > 400000) { + return; + } + } + else {return; } + + /* Set clock rate */ + if (clockrate < 1000) { /* make sure SCLH,SCLL not exceed its 16bit value */ + return; + } + + IP_I2C_SetClockRate(I2Cx, (Chip_Clock_GetRate(Chip_I2C_DetermineClk(I2Cx)) / clockrate)); +} + +/* Get current clock rate for LPC_I2C peripheral */ +uint32_t Chip_I2C_GetClockRate(LPC_I2C_Type *I2Cx) +{ + if (I2Cx == LPC_I2C0) { + return i2cClockrate[0]; + } + else if (I2Cx == LPC_I2C1) { + return i2cClockrate[1]; + } + return 0; +} + +/* Transmit and Receive data in master mode */ +Status Chip_I2C_MasterTransferData(LPC_I2C_Type *I2Cx, I2C_M_SETUP_Type *TransferCfg, I2C_TRANSFER_OPT_Type Opt) +{ + I2C_ID_Type I2C_Num = Chip_I2C_Get_BusNum(I2Cx); + + TransferCfg->retransmissions_max = 3; + TransferCfg->tx_count = 0; + TransferCfg->rx_count = 0; + TransferCfg->retransmissions_count = 0; + + return IP_I2C_MasterTransferData(I2Cx, I2C_Num, TransferCfg, Opt); +} + +/* Transmit an array of bytes in Master mode */ +Status Chip_I2C_MasterTransmitData(LPC_I2C_Type *I2Cx, I2C_M_SETUP_Type *TransferCfg, I2C_TRANSFER_OPT_Type Opt) +{ + I2C_ID_Type I2C_Num = Chip_I2C_Get_BusNum(I2Cx); + + TransferCfg->rx_data = NULL; + TransferCfg->rx_length = 0; + TransferCfg->retransmissions_max = 3; + TransferCfg->tx_count = 0; + TransferCfg->rx_count = 0; + TransferCfg->retransmissions_count = 0; + + return IP_I2C_MasterTransferData(I2Cx, I2C_Num, TransferCfg, Opt); +} + +/* Receive an array of bytes in Master mode */ +Status Chip_I2C_MasterReceiveData(LPC_I2C_Type *I2Cx, I2C_M_SETUP_Type *TransferCfg, I2C_TRANSFER_OPT_Type Opt) +{ + I2C_ID_Type I2C_Num = Chip_I2C_Get_BusNum(I2Cx); + + TransferCfg->tx_data = NULL; + TransferCfg->tx_length = 0; + TransferCfg->retransmissions_max = 3; + TransferCfg->tx_count = 0; + TransferCfg->rx_count = 0; + TransferCfg->retransmissions_count = 0; + + return IP_I2C_MasterTransferData(I2Cx, I2C_Num, TransferCfg, Opt); +} + +/* Transmit one byte and continue to send an array of bytes + * after a repeated start condition is generated in Master mode + */ +uint32_t Chip_I2C_MasterWriteReg(LPC_I2C_Type *I2Cx, + uint32_t SlaveAddr, + uint8_t regAddr, + uint8_t *buffer, + uint8_t buffer_len) +{ + uint8_t i = 0; + I2C_ID_Type I2C_Num = Chip_I2C_Get_BusNum(I2Cx); + + tx_buffer[0] = regAddr; + + for (i = 0; i < buffer_len; i++) + tx_buffer[i + 1] = *(buffer + i); + + TransferMCfg.sl_addr7bit = SlaveAddr; + TransferMCfg.tx_data = tx_buffer; + TransferMCfg.tx_length = buffer_len + 1; + TransferMCfg.rx_data = NULL; + TransferMCfg.rx_length = 0; + TransferMCfg.retransmissions_max = 3; + TransferMCfg.tx_count = 0; + TransferMCfg.rx_count = 0; + TransferMCfg.retransmissions_count = 0; + IP_I2C_MasterTransferData(I2Cx, I2C_Num, &TransferMCfg, I2C_TRANSFER_POLLING); + + return TransferMCfg.tx_count; +} + +/* Transmit one byte and receive an array of bytes after a repeated start condition is generated in Master mode. + * This function is useful for communicating with the I2C slave registers + */ +uint32_t Chip_I2C_MasterReadReg(LPC_I2C_Type *I2Cx, + uint32_t SlaveAddr, + uint8_t regAddr, + uint8_t *buffer, + uint8_t buffer_len) +{ + I2C_ID_Type I2C_Num = Chip_I2C_Get_BusNum(I2Cx); + + p_regAddr = regAddr; + + TransferMCfg.sl_addr7bit = SlaveAddr; + TransferMCfg.tx_data = &p_regAddr; + TransferMCfg.tx_length = 1; + TransferMCfg.rx_data = buffer; + TransferMCfg.rx_length = buffer_len; + TransferMCfg.retransmissions_max = 3; + TransferMCfg.tx_count = 0; + TransferMCfg.rx_count = 0; + TransferMCfg.retransmissions_count = 0; + IP_I2C_MasterTransferData(I2Cx, I2C_Num, &TransferMCfg, I2C_TRANSFER_POLLING); + + return TransferMCfg.rx_count; +} + +/* General Master Interrupt handler for I2C peripheral */ +void Chip_I2C_Interrupt_MasterHandler(LPC_I2C_Type *I2Cx) +{ + I2C_ID_Type I2C_Num = Chip_I2C_Get_BusNum(I2Cx); + + IP_I2C_Interrupt_MasterHandler(I2Cx, I2C_Num); +} + +/* Get status of Master Transfer */ +bool Chip_I2C_Interrupt_MasterTransferComplete(LPC_I2C_Type *I2Cx) +{ + I2C_ID_Type I2C_Num = Chip_I2C_Get_BusNum(I2Cx); + + return IP_I2C_Interrupt_MasterTransferComplete(I2C_Num); +} + +/* Receive and Transmit data in slave mode */ +Status Chip_I2C_SlaveTransferData(LPC_I2C_Type *I2Cx, I2C_S_SETUP_Type *TransferCfg, I2C_TRANSFER_OPT_Type Opt) +{ + I2C_ID_Type I2C_Num = Chip_I2C_Get_BusNum(I2Cx); + + TransferCfg->tx_count = 0; + TransferCfg->rx_count = 0; + + return IP_I2C_SlaveTransferData(I2Cx, I2C_Num, TransferCfg, Opt); +} + +/* Transmit an array of bytes in Slave mode */ +Status Chip_I2C_SlaveTransmitData(LPC_I2C_Type *I2Cx, I2C_S_SETUP_Type *TransferCfg, I2C_TRANSFER_OPT_Type Opt) +{ + I2C_ID_Type I2C_Num = Chip_I2C_Get_BusNum(I2Cx); + + TransferCfg->tx_count = 0; + TransferCfg->rx_data = NULL; + TransferCfg->rx_length = 0; + TransferCfg->rx_count = 0; + + return IP_I2C_SlaveTransferData(I2Cx, I2C_Num, TransferCfg, Opt); +} + +/* Receive an array of bytes in Slave mode */ +Status Chip_I2C_SlaveReceiveData(LPC_I2C_Type *I2Cx, I2C_S_SETUP_Type *TransferCfg, I2C_TRANSFER_OPT_Type Opt) +{ + I2C_ID_Type I2C_Num = Chip_I2C_Get_BusNum(I2Cx); + + TransferCfg->tx_data = NULL; + TransferCfg->tx_length = 0; + TransferCfg->tx_count = 0; + TransferCfg->rx_count = 0; + + return IP_I2C_SlaveTransferData(I2Cx, I2C_Num, TransferCfg, Opt); +} + +/* General Slave Interrupt handler for I2C peripheral */ +void Chip_I2C_Interrupt_SlaveHandler(LPC_I2C_Type *I2Cx) +{ + I2C_ID_Type I2C_Num = Chip_I2C_Get_BusNum(I2Cx); + + IP_I2C_Interrupt_SlaveHandler(I2Cx, I2C_Num); +} + +/* Get status of Slave Transfer */ +bool Chip_I2C_Interrupt_SlaveTransferComplete(LPC_I2C_Type *I2Cx) +{ + I2C_ID_Type I2C_Num = Chip_I2C_Get_BusNum(I2Cx); + + return IP_I2C_Interrupt_SlaveTransferComplete(I2C_Num); +} diff --git a/bsp/xplorer4330/libraries/lpc_chip/chip_18xx_43xx/i2c_18xx_43xx.h b/bsp/xplorer4330/libraries/lpc_chip/chip_18xx_43xx/i2c_18xx_43xx.h new file mode 100644 index 0000000000..3597fd3472 --- /dev/null +++ b/bsp/xplorer4330/libraries/lpc_chip/chip_18xx_43xx/i2c_18xx_43xx.h @@ -0,0 +1,229 @@ +/* + * @brief LPC18xx/43xx I2C driver + * + * @note + * Copyright(C) NXP Semiconductors, 2012 + * All rights reserved. + * + * @par + * Software that is described herein is for illustrative purposes only + * which provides customers with programming information regarding the + * LPC products. This software is supplied "AS IS" without any warranties of + * any kind, and NXP Semiconductors and its licensor disclaim any and + * all warranties, express or implied, including all implied warranties of + * merchantability, fitness for a particular purpose and non-infringement of + * intellectual property rights. NXP Semiconductors assumes no responsibility + * or liability for the use of the software, conveys no license or rights under any + * patent, copyright, mask work right, or any other intellectual property rights in + * or to any products. NXP Semiconductors reserves the right to make changes + * in the software without notification. NXP Semiconductors also makes no + * representation or warranty that such application will be suitable for the + * specified use without further testing or modification. + * + * @par + * Permission to use, copy, modify, and distribute this software and its + * documentation is hereby granted, under NXP Semiconductors' and its + * licensor's relevant copyrights in the software, without fee, provided that it + * is used in conjunction with NXP Semiconductors microcontrollers. This + * copyright, permission, and disclaimer notice must appear in all copies of + * this code. + */ + +#ifndef I2C_18XX_43XX_H_ +#define I2C_18XX_43XX_H_ + +#include "chip.h" + +#ifdef __cplusplus +extern "C" { +#endif + +/** @defgroup I2C_18XX_43XX CHIP: LPC18xx/43xx I2C Driver + * @ingroup CHIP_18XX_43XX_Drivers + * @{ + */ + +/** + * @brief Initializes the LPC_I2C peripheral with specified parameter. + * @param I2Cx : I2C peripheral selected, should be LPC_I2C0 or LPC_I2C1 + * @return Nothing + */ +void Chip_I2C_Init(LPC_I2C_Type *I2Cx); + +/** + * @brief De-initializes the I2C peripheral registers to their default reset values + * @param I2Cx : I2C peripheral selected, should be LPC_I2C0 or LPC_I2C1 + * @return Nothing + */ +void Chip_I2C_DeInit(LPC_I2C_Type *I2Cx); + +/** + * @brief Set up clock rate for LPC_I2C peripheral. + * @param I2Cx : I2C peripheral selected, should be LPC_I2C0 or LPC_I2C1 + * @param clockrate : Target clock rate value to initialized I2C peripheral (Hz) + * @return Nothing + */ +void Chip_I2C_SetClockRate(LPC_I2C_Type *I2Cx, uint32_t clockrate); + +/** + * @brief Get current clock rate for LPC_I2C peripheral. + * @param I2Cx : I2C peripheral selected, should be LPC_I2C0 or LPC_I2C1 + * @return the current I2Cx clock rate + */ +uint32_t Chip_I2C_GetClockRate(LPC_I2C_Type *I2Cx); + +/** + * @brief Transmit and Receive data in master mode + * @param I2Cx : I2C peripheral selected, should be LPC_I2C0 or LPC_I2C1 + * @param TransferCfg : Pointer to a I2C_M_SETUP_Type structure that contains specified + * information about the configuration for master transfer. + * @param Opt : a I2C_TRANSFER_OPT_Type type that selected for interrupt or polling mode + * @return SUCCESS or ERROR + */ +Status Chip_I2C_MasterTransferData(LPC_I2C_Type *I2Cx, I2C_M_SETUP_Type *TransferCfg, I2C_TRANSFER_OPT_Type Opt); + +/** + * @brief Transmit an array of bytes in Master mode + * @param I2Cx : I2C peripheral selected, should be LPC_I2C0 or LPC_I2C1 + * @param TransferCfg : Pointer to a I2C_M_SETUP_Type structure that contains specified + * information about the configuration for master transfer + * @param Opt : a I2C_TRANSFER_OPT_Type type that selected for interrupt or polling mode + * @return SUCCESS or ERROR + */ +Status Chip_I2C_MasterTransmitData(LPC_I2C_Type *I2Cx, I2C_M_SETUP_Type *TransferCfg, I2C_TRANSFER_OPT_Type Opt); + +/** + * @brief Receive an array of bytes in Master mode + * @param I2Cx : I2C peripheral selected, should be LPC_I2C0 or LPC_I2C1 + * @param TransferCfg : Pointer to a I2C_M_SETUP_Type structure that contains specified + * information about the configuration for master transfer. + * @param Opt : a I2C_TRANSFER_OPT_Type type that selected for interrupt or polling mode. + * @return SUCCESS or ERROR + */ +Status Chip_I2C_MasterReceiveData(LPC_I2C_Type *I2Cx, I2C_M_SETUP_Type *TransferCfg, I2C_TRANSFER_OPT_Type Opt); + +/** + * @brief Write byte(s) to slave register + * @param I2Cx : I2C peripheral selected, should be LPC_I2C0 or LPC_I2C1 + * @param SlaveAddr : Slave address in 7-bit mode + * @param regAddr : Slave register address + * @param buffer : pointer to data array needed to send + * @param buffer_len : data length (number of bytes) + * @return Number of bytes sent + * Transmit one byte and an array of bytes after a repeated start condition is generated in Master mode. + * This function is useful for communicating with the I2C slave registers. + */ +uint32_t Chip_I2C_MasterWriteReg(LPC_I2C_Type *I2Cx, + uint32_t SlaveAddr, + uint8_t regAddr, + uint8_t *buffer, + uint8_t buffer_len); + +/** + * @brief Read slave register content + * @param I2Cx : I2C peripheral selected, should be LPC_I2C0 or LPC_I2C1 + * @param SlaveAddr : Slave address in 7-bit mode + * @param regAddr : Slave register address + * @param buffer : pointer to data array needed to receive + * @param buffer_len : data length (number of bytes) + * @return Number of bytes received + * Transmit one byte and continue to receive an array of bytes after a repeated start condition is + * generated in Master mode. This function is useful for communicating with the I2C slave registers. + */ +uint32_t Chip_I2C_MasterReadReg(LPC_I2C_Type *I2Cx, + uint32_t SlaveAddr, + uint8_t regAddr, + uint8_t *buffer, + uint8_t buffer_len); + +/** + * @brief General Master Interrupt handler for I2C peripheral + * @param I2Cx : I2C peripheral selected, should be LPC_I2C0 or LPC_I2C1 + * @return Nothing + */ +void Chip_I2C_Interrupt_MasterHandler (LPC_I2C_Type *I2Cx); + +/** + * @brief Get status of Master Transfer + * @param I2Cx : I2C peripheral selected, should be LPC_I2C0 or LPC_I2C1 + * @return Master transfer status: TRUE (transfer completed) or FALSE (not completed yet) + */ +bool Chip_I2C_Interrupt_MasterTransferComplete(LPC_I2C_Type *I2Cx); + +/** + * @brief Receive and Transmit data in slave mode + * @param I2Cx : I2C peripheral selected, should be LPC_I2C0 or LPC_I2C1 + * @param TransferCfg : Pointer to a I2C_S_SETUP_Type structure that contains specified + * information about the configuration for master transfer. + * @param Opt : I2C_TRANSFER_OPT_Type type that selected for interrupt or polling mode. + * @return SUCCESS or ERROR + */ +Status Chip_I2C_SlaveTransferData(LPC_I2C_Type *I2Cx, I2C_S_SETUP_Type *TransferCfg, I2C_TRANSFER_OPT_Type Opt); + +/** + * @brief Transmit an array of bytes in Slave mode + * @param I2Cx : I2C peripheral selected, should be LPC_I2C0 or LPC_I2C1 + * @param TransferCfg : Pointer to a I2C_S_SETUP_Type structure that contains specified + * information about the configuration for slave transfer. + * @param Opt : a I2C_TRANSFER_OPT_Type type that selected for interrupt or polling mode. + * @return SUCCESS or ERROR + */ +Status Chip_I2C_SlaveTransmitData(LPC_I2C_Type *I2Cx, I2C_S_SETUP_Type *TransferCfg, I2C_TRANSFER_OPT_Type Opt); + +/** + * @brief Receive an array of bytes in Slave mode + * @param I2Cx : I2C peripheral selected, should be LPC_I2C0 or LPC_I2C1 + * @param TransferCfg : Pointer to a I2C_S_SETUP_Type structure that contains specified + * information about the configuration for slave transfer. + * @param Opt : a I2C_TRANSFER_OPT_Type type that selected for interrupt or polling mode. + * @return SUCCESS or ERROR + */ +Status Chip_I2C_SlaveReceiveData(LPC_I2C_Type *I2Cx, I2C_S_SETUP_Type *TransferCfg, I2C_TRANSFER_OPT_Type Opt); + +/** + * @brief General Slave Interrupt handler for I2C peripheral + * @param I2Cx : I2C peripheral selected, should be LPC_I2C0 or LPC_I2C1 + * @return Nothing + */ +void Chip_I2C_Interrupt_SlaveHandler (LPC_I2C_Type *I2Cx); + +/** + * @brief Get status of Slave Transfer + * @param I2Cx : I2C peripheral selected, should be LPC_I2C0 or LPC_I2C1 + * @return Slave transfer status: TRUE (transfer completed) or FALSE (not completed yet) + */ +bool Chip_I2C_Interrupt_SlaveTransferComplete(LPC_I2C_Type *I2Cx); + +/** + * @brief Set Own slave address in I2C peripheral corresponding to parameter specified in OwnSlaveAddrConfigStruct. + * @param I2Cx : I2C peripheral selected, should be LPC_I2C0 or LPC_I2C1 + * @param OwnSlaveAddrConfigStruct : Pointer to a I2C_OWNSLAVEADDR_CFG_Type structure that contains the + * configuration information for the specified I2C slave address. + * @return Nothing + */ +STATIC INLINE void Chip_I2C_SetOwnSlaveAddr(LPC_I2C_Type *I2Cx, I2C_OWNSLAVEADDR_CFG_Type *OwnSlaveAddrConfigStruct) +{ + IP_I2C_SetOwnSlaveAddr(I2Cx, OwnSlaveAddrConfigStruct); +} + +/** + * @brief Enable or disable I2C peripheral's operation + * @param I2Cx : I2C peripheral selected, should be LPC_I2C0 or LPC_I2C1 + * @param Mode : I2C mode, should be I2C_MASTER_MODE, I2C_SLAVE_MODE or I2C_GENERAL_MODE + * @param NewState: New State of LPC_I2C peripheral's operation, should be ENABLE or DISABLE + * @return Nothing + */ +STATIC INLINE void Chip_I2C_Cmd(LPC_I2C_Type *I2Cx, I2C_Mode Mode, FunctionalState NewState) +{ + IP_I2C_Cmd(I2Cx, Mode, NewState); +} + +/** + * @} + */ + + #ifdef __cplusplus +} +#endif + +#endif /* I2C_18XX_43XX_H_ */ diff --git a/bsp/xplorer4330/libraries/lpc_chip/chip_18xx_43xx/i2s_18xx_43xx.c b/bsp/xplorer4330/libraries/lpc_chip/chip_18xx_43xx/i2s_18xx_43xx.c new file mode 100644 index 0000000000..9a23b9e4d1 --- /dev/null +++ b/bsp/xplorer4330/libraries/lpc_chip/chip_18xx_43xx/i2s_18xx_43xx.c @@ -0,0 +1,138 @@ +/* + * @brief LPC18xx/43xx I2S driver + * + * @note + * Copyright(C) NXP Semiconductors, 2012 + * All rights reserved. + * + * @par + * Software that is described herein is for illustrative purposes only + * which provides customers with programming information regarding the + * LPC products. This software is supplied "AS IS" without any warranties of + * any kind, and NXP Semiconductors and its licensor disclaim any and + * all warranties, express or implied, including all implied warranties of + * merchantability, fitness for a particular purpose and non-infringement of + * intellectual property rights. NXP Semiconductors assumes no responsibility + * or liability for the use of the software, conveys no license or rights under any + * patent, copyright, mask work right, or any other intellectual property rights in + * or to any products. NXP Semiconductors reserves the right to make changes + * in the software without notification. NXP Semiconductors also makes no + * representation or warranty that such application will be suitable for the + * specified use without further testing or modification. + * + * @par + * Permission to use, copy, modify, and distribute this software and its + * documentation is hereby granted, under NXP Semiconductors' and its + * licensor's relevant copyrights in the software, without fee, provided that it + * is used in conjunction with NXP Semiconductors microcontrollers. This + * copyright, permission, and disclaimer notice must appear in all copies of + * this code. + */ + +#include "i2s_18xx_43xx.h" +#include "scu_18xx_43xx.h" + +/***************************************************************************** + * Private types/enumerations/variables + ****************************************************************************/ + +/***************************************************************************** + * Public types/enumerations/variables + ****************************************************************************/ + +/***************************************************************************** + * Private functions + ****************************************************************************/ + +/***************************************************************************** + * Public functions + ****************************************************************************/ + +/* Configure I2S for Audio Format input */ +Status Chip_I2S_Config(LPC_I2S_Type *I2Sx, uint8_t TRMode, Chip_I2S_Audio_Format_Type *audio_format) +{ + uint32_t pClk; + uint32_t x, y; + uint64_t divider; + uint16_t dif; + uint16_t x_divide = 0, y_divide = 0; + uint32_t N; + uint16_t err, ErrorOptimal = 0xFFFF; + + pClk = (uint64_t)Chip_Clock_GetRate(CLK_APB1_I2S); + + /* divider is a fixed point number with 16 fractional bits */ + divider = (((uint64_t)(audio_format->SampleRate) * 2 * (audio_format->WordWidth) * 2) << 16) / pClk; + /* find N that make x/y <= 1 -> divider <= 2^16 */ + for (N = 64; N > 0; N--) { + if ((divider * N) < (1 << 16)) { + break; + } + } + if (N == 0) { + return ERROR; + } + divider *= N; + for (y = 255; y > 0; y--) { + x = y * divider; + if (x & (0xFF000000)) { + continue; + } + dif = x & 0xFFFF; + if (dif > 0x8000) { + err = 0x10000 - dif; + } + else { + err = dif; + } + if (err == 0) { + y_divide = y; + break; + } + else if (err < ErrorOptimal) { + ErrorOptimal = err; + y_divide = y; + } + } + x_divide = ((uint64_t)y_divide * (audio_format->SampleRate) * 2 * (audio_format->WordWidth) * N * 2) / pClk; + if (x_divide >= 256) { + x_divide = 0xFF; + } + if (x_divide == 0) { + x_divide = 1; + } + if (audio_format->WordWidth <= 8) { + IP_I2S_SetWordWidth(I2Sx, TRMode, I2S_WORDWIDTH_8); + } + else if (audio_format->WordWidth <= 16) { + IP_I2S_SetWordWidth(I2Sx, TRMode, I2S_WORDWIDTH_16); + } + else { + IP_I2S_SetWordWidth(I2Sx, TRMode, I2S_WORDWIDTH_32); + } + IP_I2S_SetMono(I2Sx, TRMode, (audio_format->ChannelNumber) == 1 ? I2S_MONO : I2S_STEREO); + IP_I2S_SetMasterSlaveMode(I2Sx, TRMode, I2S_MASTER_MODE); + IP_I2S_SetWS_Halfperiod(I2Sx, TRMode, audio_format->WordWidth - 1); + IP_I2S_ModeConfig(I2Sx, TRMode, I2S_TXMODE_CLKSEL(0), !I2S_TXMODE_4PIN_ENABLE, !I2S_TXMODE_MCENA); + IP_I2S_SetBitRate(I2Sx, TRMode, N - 1); + IP_I2S_SetXYDivider(I2Sx, TRMode, x_divide, y_divide); + return SUCCESS; +} + +/* Enable/Disable Interrupt with a specific FIFO depth */ +void Chip_I2S_Int_Cmd(LPC_I2S_Type *I2Sx, uint8_t TRMode, FunctionalState NewState, uint8_t FIFO_Depth) +{ + IP_I2S_InterruptCmd(I2Sx, TRMode, NewState); + IP_I2S_SetFIFODepthIRQ(I2Sx, TRMode, FIFO_Depth); +} + +/* Enable/Disable DMA with a specific FIFO depth */ +void Chip_I2S_DMA_Cmd(LPC_I2S_Type *I2Sx, + uint8_t TRMode, + uint8_t DMANum, + FunctionalState NewState, + uint8_t FIFO_Depth) +{ + IP_I2S_SetFIFODepthDMA(I2Sx, TRMode, (IP_I2S_DMARequestNumber_Type) DMANum, FIFO_Depth); + IP_I2S_DMACmd(I2Sx, (IP_I2S_DMARequestNumber_Type) DMANum, TRMode, NewState); +} diff --git a/bsp/xplorer4330/libraries/lpc_chip/chip_18xx_43xx/i2s_18xx_43xx.h b/bsp/xplorer4330/libraries/lpc_chip/chip_18xx_43xx/i2s_18xx_43xx.h new file mode 100644 index 0000000000..88102e86ea --- /dev/null +++ b/bsp/xplorer4330/libraries/lpc_chip/chip_18xx_43xx/i2s_18xx_43xx.h @@ -0,0 +1,221 @@ +/* + * @brief LPC18xx/43xx I2S driver + * + * @note + * Copyright(C) NXP Semiconductors, 2012 + * All rights reserved. + * + * @par + * Software that is described herein is for illustrative purposes only + * which provides customers with programming information regarding the + * LPC products. This software is supplied "AS IS" without any warranties of + * any kind, and NXP Semiconductors and its licensor disclaim any and + * all warranties, express or implied, including all implied warranties of + * merchantability, fitness for a particular purpose and non-infringement of + * intellectual property rights. NXP Semiconductors assumes no responsibility + * or liability for the use of the software, conveys no license or rights under any + * patent, copyright, mask work right, or any other intellectual property rights in + * or to any products. NXP Semiconductors reserves the right to make changes + * in the software without notification. NXP Semiconductors also makes no + * representation or warranty that such application will be suitable for the + * specified use without further testing or modification. + * + * @par + * Permission to use, copy, modify, and distribute this software and its + * documentation is hereby granted, under NXP Semiconductors' and its + * licensor's relevant copyrights in the software, without fee, provided that it + * is used in conjunction with NXP Semiconductors microcontrollers. This + * copyright, permission, and disclaimer notice must appear in all copies of + * this code. + */ + +#ifndef __I2S_18XX_43XX_H_ +#define __I2S_18XX_43XX_H_ + +#include "chip.h" + +#ifdef __cplusplus +extern "C" { +#endif + +/** @defgroup I2S_18XX_43XX CHIP: LPC18xx/43xx I2S driver + * @ingroup CHIP_18XX_43XX_Drivers + * @{ + */ + +#define I2S_DMA_REQUEST_NUMBER_1 IP_I2S_DMA_REQUEST_NUMBER_1 +#define I2S_DMA_REQUEST_NUMBER_2 IP_I2S_DMA_REQUEST_NUMBER_2 + +/** + * @brief I2S Audio Format Structure + */ +typedef struct { + uint32_t SampleRate; /*!< Sample Rate */ + uint8_t ChannelNumber; /*!< Channel Number - 1 is mono, 2 is stereo */ + uint8_t WordWidth; /*!< Word Width - 8, 16 or 32 bits */ +} Chip_I2S_Audio_Format_Type; + +/** + * @brief Initialize for I2S + * @param pI2S : The base of I2S peripheral on the chip + * @return Nothing + */ +STATIC INLINE void Chip_I2S_Init(LPC_I2S_Type *pI2S) +{ + IP_I2S_Init(pI2S); +} + +/** + * @brief Shutdown I2S + * @param pI2S : The base of I2S peripheral on the chip + * @return Nothing + * Reset all relative registers (DMA, transmit/receive control, interrupt) to default value + */ +STATIC INLINE void Chip_I2S_DeInit(LPC_I2S_Type *pI2S) +{ + IP_I2S_DeInit(pI2S); +} + +/** + * @brief Send a 32-bit data to TXFIFO for transmition + * @param pI2S : The base of I2S peripheral on the chip + * @param data : Data to be transmited + * @return Nothing + * The function writes to TXFIFO without checking any condition. + */ +STATIC INLINE void Chip_I2S_Send(LPC_I2S_Type *pI2S, uint32_t data) +{ + IP_I2S_Send(pI2S, data); +} + +/** + * @brief Get received data from RXFIFO + * @param pI2S : The base of I2S peripheral on the chip + * @return Data received in RXFIFO + * The function reads from RXFIFO without checking any condition. + */ +STATIC INLINE uint32_t Chip_I2S_Receive(LPC_I2S_Type *pI2S) +{ + return IP_I2S_Receive(pI2S); +} + +/** + * @brief Start the I2S + * @param pI2S : The base of I2S peripheral on the chip + * @param TRMode : Transmit/Receive mode, should be I2S_RX_MODE or I2S_TX_MODE + * @return Nothing + */ +STATIC INLINE void Chip_I2S_Start(LPC_I2S_Type *pI2S, uint8_t TRMode) +{ + IP_I2S_Start(pI2S, TRMode); +} + +/** + * @brief Disables accesses on FIFOs, places the transmit channel in mute mode + * @param pI2S : The base of I2S peripheral on the chip + * @param TRMode : Transmit/Receive mode, should be I2S_RX_MODE or I2S_TX_MODE + * @return Nothing + */ +STATIC INLINE void Chip_I2S_Pause(LPC_I2S_Type *pI2S, uint8_t TRMode) +{ + IP_I2S_Pause(pI2S, TRMode); +} + +/** + * @brief Transmit channel sends only zeroes + * @param pI2S : The base of I2S peripheral on the chip + * @param NewState : Transmit/Receive mode, should be I2S_RX_MODE or I2S_TX_MODE + * @return Nothing + * The data output from I2S transmit channel is always zeroes + */ +STATIC INLINE void Chip_I2S_Mute(LPC_I2S_Type *pI2S, FunctionalState NewState) +{ + IP_I2S_Mute(pI2S, NewState); +} + +/** + * @brief Stop I2S asynchronously + * @param pI2S : The base of I2S peripheral on the chip + * @param TRMode : Transmit/Receive mode, should be I2S_RX_MODE or I2S_TX_MODE + * @return Nothing + * Pause, resets the transmit channel and FIFO asynchronously + */ +STATIC INLINE void Chip_I2S_Stop(LPC_I2S_Type *pI2S, uint8_t TRMode) +{ + IP_I2S_Stop(pI2S, TRMode); +} + +/** + * @brief Set the I2S operating modes + * @param pI2S : The base of I2S peripheral on the chip + * @param TRMode : Transmit/Receive mode, should be I2S_RX_MODE or I2S_TX_MODE + * @param clksel : Clock source selection for the receive bit clock divider + * @param fpin : Receive 4-pin mode selection + * @param mcena : Enable for the RX_MCLK output + * @return Nothing + * In addition to master and slave modes, which are independently configurable for + * the transmitter and the receiver, several different clock sources are possible, + * including variations that share the clock and/or WS between the transmitter and + * receiver. It also allows using I2S with fewer pins, typically four. + */ +STATIC INLINE void Chip_I2S_ModeConfig(LPC_I2S_Type *pI2S, + uint8_t TRMode, + uint32_t clksel, + uint32_t fpin, + uint32_t mcena) +{ + IP_I2S_ModeConfig(pI2S, TRMode, clksel, fpin, mcena); +} + +/** + * @brief Get the current level of the Transmit/Receive FIFO + * @param pI2S : The base of I2S peripheral on the chip + * @param TRMode : Transmit/Receive mode, should be I2S_RX_MODE or I2S_TX_MODE + * @return Current level of the Transmit/Receive FIFO + */ +STATIC INLINE uint8_t Chip_I2S_GetLevel(LPC_I2S_Type *pI2S, uint8_t TRMode) +{ + return IP_I2S_GetLevel(pI2S, TRMode); +} + +/** + * @brief Configure I2S for Audio Format input + * @param pI2S : The base I2S peripheral on the chip + * @param TRMode : Mode Rx/Tx + * @param audio_format : Audio Format + * @return SUCCESS or ERROR + */ +Status Chip_I2S_Config(LPC_I2S_Type *pI2S, uint8_t TRMode, Chip_I2S_Audio_Format_Type *audio_format); + +/** + * @brief Enable/Disable Interrupt with a specific FIFO depth + * @param pI2S : The base I2S peripheral on the chip + * @param TRMode : Mode Rx/Tx + * @param NewState : ENABLE or DISABLE interrupt + * @param FIFO_Depth : FIFO level creating an irq request + * @return Nothing + */ +void Chip_I2S_Int_Cmd(LPC_I2S_Type *pI2S, uint8_t TRMode, FunctionalState NewState, uint8_t FIFO_Depth); + +/** + * @brief Enable/Disable DMA with a specific FIFO depth + * @param pI2S : The base I2S peripheral on the chip + * @param TRMode : Mode Rx/Tx + * @param DMANum : Should be + * - IP_I2S_DMA_REQUEST_NUMBER_1 : Using DMA1 + * - IP_I2S_DMA_REQUEST_NUMBER_2 : Using DMA2 + * @param NewState : ENABLE or DISABLE interrupt + * @param FIFO_Depth : FIFO level creating an irq request + * @return Nothing + */ +void Chip_I2S_DMA_Cmd(LPC_I2S_Type *pI2S, uint8_t TRMode, uint8_t DMANum, FunctionalState NewState, uint8_t FIFO_Depth); + +/** + * @} + */ + +#ifdef __cplusplus +} +#endif + +#endif /* __I2S_18XX_43XX_H_ */ diff --git a/bsp/xplorer4330/libraries/lpc_chip/chip_18xx_43xx/lcd_18xx_43xx.c b/bsp/xplorer4330/libraries/lpc_chip/chip_18xx_43xx/lcd_18xx_43xx.c new file mode 100644 index 0000000000..4142dcb5cc --- /dev/null +++ b/bsp/xplorer4330/libraries/lpc_chip/chip_18xx_43xx/lcd_18xx_43xx.c @@ -0,0 +1,118 @@ +/* + * @brief LPC18xx/43xx LCD chip driver + * + * @note + * Copyright(C) NXP Semiconductors, 2012 + * All rights reserved. + * + * @par + * Software that is described herein is for illustrative purposes only + * which provides customers with programming information regarding the + * LPC products. This software is supplied "AS IS" without any warranties of + * any kind, and NXP Semiconductors and its licensor disclaim any and + * all warranties, express or implied, including all implied warranties of + * merchantability, fitness for a particular purpose and non-infringement of + * intellectual property rights. NXP Semiconductors assumes no responsibility + * or liability for the use of the software, conveys no license or rights under any + * patent, copyright, mask work right, or any other intellectual property rights in + * or to any products. NXP Semiconductors reserves the right to make changes + * in the software without notification. NXP Semiconductors also makes no + * representation or warranty that such application will be suitable for the + * specified use without further testing or modification. + * + * @par + * Permission to use, copy, modify, and distribute this software and its + * documentation is hereby granted, under NXP Semiconductors' and its + * licensor's relevant copyrights in the software, without fee, provided that it + * is used in conjunction with NXP Semiconductors microcontrollers. This + * copyright, permission, and disclaimer notice must appear in all copies of + * this code. + */ + +#include "lcd_18xx_43xx.h" + +/***************************************************************************** + * Private types/enumerations/variables + ****************************************************************************/ + +static LCD_CURSOR_SIZE_OPT LCD_Cursor_Size = LCD_CURSOR_64x64; + +/***************************************************************************** + * Public types/enumerations/variables + ****************************************************************************/ + +/***************************************************************************** + * Private functions + ****************************************************************************/ + +/***************************************************************************** + * Public functions + ****************************************************************************/ + +/* Configure Cursor */ +void Chip_LCD_Cursor_Config(LCD_CURSOR_SIZE_OPT cursor_size, bool sync) +{ + LCD_Cursor_Size = cursor_size; + IP_LCD_Cursor_Config(LPC_LCD, cursor_size, sync); +} + +/* Write Cursor Image into Internal Cursor Image Buffer */ +void Chip_LCD_Cursor_WriteImage(uint8_t cursor_num, void *Image) +{ + int i, j; + uint32_t *fifoptr, *crsr_ptr = (uint32_t *) Image; + + /* Check if Cursor Size was configured as 32x32 or 64x64*/ + if (LCD_Cursor_Size == LCD_CURSOR_32x32) { + i = cursor_num * 64; + j = i + 64; + } + else { + i = 0; + j = 256; + } + fifoptr = IP_LCD_Cursor_GetImageBufferAddress(LPC_LCD, 0); + + /* Copy Cursor Image content to FIFO */ + for (; i < j; i++) { + + *fifoptr = *crsr_ptr; + crsr_ptr++; + fifoptr++; + } +} + +/* Load LCD Palette */ +void Chip_LCD_LoadPalette(void *palette) { + LCD_PALETTE_ENTRY_Type pal_entry, *ptr_pal_entry; + uint8_t i, *pal_ptr; + /* This function supports loading of the color palette from + the C file generated by the bmp2c utility. It expects the + palette to be passed as an array of 32-bit BGR entries having + the following format: + 2:0 - Not used + 7:3 - Blue + 10:8 - Not used + 15:11 - Green + 18:16 - Not used + 23:19 - Red + 31:24 - Not used + arg = pointer to input palette table address */ + ptr_pal_entry = &pal_entry; + pal_ptr = (uint8_t *) palette; + + /* 256 entry in the palette table */ + for (i = 0; i < 256 / 2; i++) { + pal_entry.Bl = (*pal_ptr++) >> 3; /* blue first */ + pal_entry.Gl = (*pal_ptr++) >> 3; /* get green */ + pal_entry.Rl = (*pal_ptr++) >> 3; /* get red */ + pal_ptr++; /* skip over the unused byte */ + /* do the most significant halfword of the palette */ + pal_entry.Bu = (*pal_ptr++) >> 3; /* blue first */ + pal_entry.Gu = (*pal_ptr++) >> 3; /* get green */ + pal_entry.Ru = (*pal_ptr++) >> 3; /* get red */ + pal_ptr++; /* skip over the unused byte */ + + IP_LCD_Color_LoadPalette(LPC_LCD, (uint32_t *) &ptr_pal_entry, i); + } +} diff --git a/bsp/xplorer4330/libraries/lpc_chip/chip_18xx_43xx/lcd_18xx_43xx.h b/bsp/xplorer4330/libraries/lpc_chip/chip_18xx_43xx/lcd_18xx_43xx.h new file mode 100644 index 0000000000..71916e1575 --- /dev/null +++ b/bsp/xplorer4330/libraries/lpc_chip/chip_18xx_43xx/lcd_18xx_43xx.h @@ -0,0 +1,216 @@ +/* + * @brief LPC18xx/43xx LCD chip driver + * + * @note + * Copyright(C) NXP Semiconductors, 2012 + * All rights reserved. + * + * @par + * Software that is described herein is for illustrative purposes only + * which provides customers with programming information regarding the + * LPC products. This software is supplied "AS IS" without any warranties of + * any kind, and NXP Semiconductors and its licensor disclaim any and + * all warranties, express or implied, including all implied warranties of + * merchantability, fitness for a particular purpose and non-infringement of + * intellectual property rights. NXP Semiconductors assumes no responsibility + * or liability for the use of the software, conveys no license or rights under any + * patent, copyright, mask work right, or any other intellectual property rights in + * or to any products. NXP Semiconductors reserves the right to make changes + * in the software without notification. NXP Semiconductors also makes no + * representation or warranty that such application will be suitable for the + * specified use without further testing or modification. + * + * @par + * Permission to use, copy, modify, and distribute this software and its + * documentation is hereby granted, under NXP Semiconductors' and its + * licensor's relevant copyrights in the software, without fee, provided that it + * is used in conjunction with NXP Semiconductors microcontrollers. This + * copyright, permission, and disclaimer notice must appear in all copies of + * this code. + */ + +#ifndef __LCD_18XX_43XX_H_ +#define __LCD_18XX_43XX_H_ + +#include "chip.h" + +#ifdef __cplusplus +extern "C" { +#endif + +/** @defgroup LCD_18XX_43XX CHIP: LPC18xx/43xx LCD driver + * @ingroup CHIP_18XX_43XX_Drivers + * @{ + */ + +/** + * @brief Initialize the LCD controller + * @param LCD_ConfigStruct : Pointer to LCD configuration + * @return LCD_FUNC_OK is executed successfully or LCD_FUNC_ERR on error + */ +STATIC INLINE void Chip_LCD_Init(LCD_Config_Type *LCD_ConfigStruct) +{ + IP_LCD_Init(LPC_LCD, LCD_ConfigStruct); +} + +/** + * @brief Power the LCD Panel (power pin) + * @param OnOff : true to power on, false to power off + * @return None + */ +STATIC INLINE void Chip_LCD_Power(FunctionalState OnOff) +{ + IP_LCD_Power(LPC_LCD, OnOff); +} + +/** + * @brief Enable/Disable the LCD Controller + * @param EnDis : true to enable, false to disable + * @return None + */ +STATIC INLINE void Chip_LCD_Enable(FunctionalState EnDis) +{ + IP_LCD_Enable(LPC_LCD, EnDis); +} + +/** + * @brief Set LCD Upper Panel Frame Buffer for Single Panel or Upper Panel Frame + * Buffer for Dual Panel + * @param buffer : address of buffer + * @return None + */ +STATIC INLINE void Chip_LCD_SetUPFrameBuffer(void *buffer) +{ + IP_LCD_SetUPFrameBuffer(LPC_LCD, buffer); +} + +/** + * @brief Set LCD Lower Panel Frame Buffer for Dual Panel + * @param buffer : address of buffer + * @return None + */ +STATIC INLINE void Chip_LCD_SetLPFrameBuffer(void *buffer) +{ + IP_LCD_SetLPFrameBuffer(LPC_LCD, buffer); +} + +/** + * @brief Configure Cursor + * @param cursor_size : specify size of cursor + * - LCD_CURSOR_32x32 :cursor size is 32x32 pixels + * - LCD_CURSOR_64x64 :cursor size is 64x64 pixels + * @param sync : cursor sync mode + * - TRUE :cursor sync to the frame sync pulse + * - FALSE :cursor async mode + * @return None + */ +void Chip_LCD_Cursor_Config(LCD_CURSOR_SIZE_OPT cursor_size, bool sync); + +/** + * @brief Enable Cursor + * @param cursor_num : specify number of cursor is going to be written + * this param must < 4 + * @param OnOff : true to turn on LCD, false to turn off + * @return None + */ +STATIC INLINE void Chip_LCD_Cursor_Enable(uint8_t cursor_num, FunctionalState OnOff) +{ + IP_LCD_Cursor_Enable(LPC_LCD, cursor_num, OnOff); +} + +/** + * @brief Load Cursor Palette + * @param palette_color : cursor palette 0 value + * @return None + */ +STATIC INLINE void Chip_LCD_Cursor_LoadPalette0(uint32_t palette_color) +{ + IP_LCD_Cursor_LoadPalette0(LPC_LCD, palette_color); +} + +/** + * @brief Load Cursor Palette + * @param palette_color : cursor palette 1 value + * @return None + */ +STATIC INLINE void Chip_LCD_Cursor_LoadPalette1(uint32_t palette_color) +{ + IP_LCD_Cursor_LoadPalette1(LPC_LCD, palette_color); +} + +/** + * @brief Set Cursor Position + * @param x : horizontal position + * @param y : vertical position + * @return None + */ +STATIC INLINE void Chip_LCD_Cursor_SetPos(uint16_t x, uint16_t y) +{ + IP_LCD_Cursor_SetPos(LPC_LCD, x, y); +} + +/** + * @brief Set Cursor Clipping Position + * @param x : horizontal position, should be in range: 0..63 + * @param y : vertical position, should be in range: 0..63 + * @return None + */ +STATIC INLINE void Chip_LCD_Cursor_SetClip(uint16_t x, uint16_t y) +{ + IP_LCD_Cursor_SetClip(LPC_LCD, x, y); +} + +/** + * @brief Enable Controller Interrupt + * @param ints : OR'ed interrupt bits to enable + * @return None + */ +STATIC INLINE void Chip_LCD_EnableInts(uint32_t ints) +{ + IP_LCD_EnableInts(LPC_LCD, ints); +} + +/** + * @brief Disable Controller Interrupt + * @param ints : OR'ed interrupt bits to disable + * @return None + */ +STATIC INLINE void Chip_LCD_DisableInts(uint32_t ints) +{ + IP_LCD_DisableInts(LPC_LCD, ints); +} + +/** + * @brief Clear Controller Interrupt + * @param ints : OR'ed interrupt bits to clear + * @return None + */ +STATIC INLINE void Chip_LCD_ClearInts(uint32_t ints) +{ + IP_LCD_ClearInts(LPC_LCD, ints); +} + +/** + * @brief Write Cursor Image into Internal Cursor Image Buffer + * @param cursor_num : Cursor index + * @param Image : Pointer to image data + * @return None + */ +void Chip_LCD_Cursor_WriteImage(uint8_t cursor_num, void *Image); + +/** + * @brief Load LCD Palette + * @param palette : Address of palette table to load + * @return None + */ +void Chip_LCD_LoadPalette(void *palette); + +#ifdef __cplusplus +} +#endif + +/** + * @} + */ + +#endif /* __LCD_18XX_43XX_H_ */ diff --git a/bsp/xplorer4330/libraries/lpc_chip/chip_18xx_43xx/rgu_18xx_43xx.c b/bsp/xplorer4330/libraries/lpc_chip/chip_18xx_43xx/rgu_18xx_43xx.c new file mode 100644 index 0000000000..3dcfcb7282 --- /dev/null +++ b/bsp/xplorer4330/libraries/lpc_chip/chip_18xx_43xx/rgu_18xx_43xx.c @@ -0,0 +1,92 @@ +/* + * @brief LPC18xx/43xx Reset Generator Unit driver + * + * @note + * Copyright(C) NXP Semiconductors, 2012 + * All rights reserved. + * + * @par + * Software that is described herein is for illustrative purposes only + * which provides customers with programming information regarding the + * LPC products. This software is supplied "AS IS" without any warranties of + * any kind, and NXP Semiconductors and its licensor disclaim any and + * all warranties, express or implied, including all implied warranties of + * merchantability, fitness for a particular purpose and non-infringement of + * intellectual property rights. NXP Semiconductors assumes no responsibility + * or liability for the use of the software, conveys no license or rights under any + * patent, copyright, mask work right, or any other intellectual property rights in + * or to any products. NXP Semiconductors reserves the right to make changes + * in the software without notification. NXP Semiconductors also makes no + * representation or warranty that such application will be suitable for the + * specified use without further testing or modification. + * + * @par + * Permission to use, copy, modify, and distribute this software and its + * documentation is hereby granted, under NXP Semiconductors' and its + * licensor's relevant copyrights in the software, without fee, provided that it + * is used in conjunction with NXP Semiconductors microcontrollers. This + * copyright, permission, and disclaimer notice must appear in all copies of + * this code. + */ + +#include "rgu_18xx_43xx.h" + +/***************************************************************************** + * Private types/enumerations/variables + ****************************************************************************/ + +/***************************************************************************** + * Public types/enumerations/variables + ****************************************************************************/ + +/***************************************************************************** + * Private functions + ****************************************************************************/ + +/***************************************************************************** + * Public functions + ****************************************************************************/ + +/* Trigger a peripheral reset for the selected peripheral */ +void Chip_RGU_TriggerReset(RGU_RST_TYPE ResetNumber) +{ + volatile uint32_t *p; + + /* To trigger reset- write RESET_CTRLx with a 1 bit */ + p = (volatile uint32_t *) &(LPC_RGU->RESET_CTRL0); + + /* higher numbers are in RESET_CTRL1, RESET_CTRL2, etc. */ + p += ResetNumber / 32; + + /* On the LPC18xx and LPC43xx, most of the reset bits automatically clear + after 1 clock cycle, so set the bit and return */ + *p = (1 << (ResetNumber % 32)); +} + +/* Clears reset for the selected peripheral */ +void Chip_RGU_ClearReset(RGU_RST_TYPE ResetNumber) +{ + volatile uint32_t *p; + + /* To trigger reset- write RESET_CTRLx with a 1 bit */ + p = (volatile uint32_t *) &(LPC_RGU->RESET_CTRL0); + + /* higher numbers are in RESET_CTRL1, RESET_CTRL2, etc. */ + p += ResetNumber / 32; + + /* On the LPC18xx and LPC43xx, most of the reset bits automatically clear + after 1 clock cycle, so set the bit and return */ + *p = 0; +} + +/* Checks the reset status of a peripheral */ +bool Chip_RGU_InReset(RGU_RST_TYPE ResetNumber) +{ + volatile uint32_t *read; + + read = (volatile uint32_t *) &(LPC_RGU->RESET_ACTIVE_STATUS0); + read += ResetNumber / 32; + + /* Reset not asserted if bit is set */ + return (bool) ((*read & (1 << (ResetNumber % 32))) == 0); +} diff --git a/bsp/xplorer4330/libraries/lpc_chip/chip_18xx_43xx/rgu_18xx_43xx.h b/bsp/xplorer4330/libraries/lpc_chip/chip_18xx_43xx/rgu_18xx_43xx.h new file mode 100644 index 0000000000..91c8f4dec7 --- /dev/null +++ b/bsp/xplorer4330/libraries/lpc_chip/chip_18xx_43xx/rgu_18xx_43xx.h @@ -0,0 +1,151 @@ +/* + * @brief LPC18xx/43xx Reset Generator Unit driver + * + * @note + * Copyright(C) NXP Semiconductors, 2012 + * All rights reserved. + * + * @par + * Software that is described herein is for illustrative purposes only + * which provides customers with programming information regarding the + * LPC products. This software is supplied "AS IS" without any warranties of + * any kind, and NXP Semiconductors and its licensor disclaim any and + * all warranties, express or implied, including all implied warranties of + * merchantability, fitness for a particular purpose and non-infringement of + * intellectual property rights. NXP Semiconductors assumes no responsibility + * or liability for the use of the software, conveys no license or rights under any + * patent, copyright, mask work right, or any other intellectual property rights in + * or to any products. NXP Semiconductors reserves the right to make changes + * in the software without notification. NXP Semiconductors also makes no + * representation or warranty that such application will be suitable for the + * specified use without further testing or modification. + * + * @par + * Permission to use, copy, modify, and distribute this software and its + * documentation is hereby granted, under NXP Semiconductors' and its + * licensor's relevant copyrights in the software, without fee, provided that it + * is used in conjunction with NXP Semiconductors microcontrollers. This + * copyright, permission, and disclaimer notice must appear in all copies of + * this code. + */ + +#ifndef __RGU_18XX_43XX_H_ +#define __RGU_18XX_43XX_H_ + +#include "chip.h" + +#ifdef __cplusplus +extern "C" { +#endif + +/** @defgroup RGU_18XX_43XX CHIP: LPC18xx/43xx Reset Generator Unit (RGU) driver + * @ingroup CHIP_18XX_43XX_Drivers + * @{ + */ + +/** + * @brief RGU reset enumerations + */ +typedef enum { + RGU_CORE_RST, + RGU_PERIPH_RST, + RGU_MASTER_RST, + RGU_WWDT_RST = 4, + RGU_CREG_RST, + RGU_BUS_RST = 8, + RGU_SCU_RST, + RGU_M3_RST = 13, + RGU_LCD_RST = 16, + RGU_USB0_RST, + RGU_USB1_RST, + RGU_DMA_RST, + RGU_SDIO_RST, + RGU_EMC_RST, + RGU_ETHERNET_RST, + RGU_FLASHA_RST = 25, + RGU_EEPROM_RST = 27, + RGU_GPIO_RST, + RGU_FLASHB_RST, + RGU_TIMER0_RST = 32, + RGU_TIMER1_RST, + RGU_TIMER2_RST, + RGU_TIMER3_RST, + RGU_RITIMER_RST, + RGU_SCT_RST, + RGU_MOTOCONPWM_RST, + RGU_QEI_RST, + RGU_ADC0_RST, + RGU_ADC1_RST, + RGU_DAC_RST, + RGU_UART0_RST = 44, + RGU_UART1_RST, + RGU_UART2_RST, + RGU_UART3_RST, + RGU_I2C0_RST, + RGU_I2C1_RST, + RGU_SSP0_RST, + RGU_SSP1_RST, + RGU_I2S_RST, + RGU_SPIFI_RST, + RGU_CAN1_RST, + RGU_CAN0_RST, +#ifdef CHIP_LPC43XX + RGU_M0APP_RST, + RGU_SGPIO_RST, + RGU_SPI_RST, +#endif + RGU_LAST_RST = 63, +} RGU_RST_TYPE; + +/** + * @brief RGU register structure + */ +typedef struct { /*!< RGU Structure */ + __I uint32_t RESERVED0[64]; + __O uint32_t RESET_CTRL0; /*!< Reset control register 0 */ + __O uint32_t RESET_CTRL1; /*!< Reset control register 1 */ + __I uint32_t RESERVED1[2]; + __IO uint32_t RESET_STATUS0; /*!< Reset status register 0 */ + __IO uint32_t RESET_STATUS1; /*!< Reset status register 1 */ + __IO uint32_t RESET_STATUS2; /*!< Reset status register 2 */ + __IO uint32_t RESET_STATUS3; /*!< Reset status register 3 */ + __I uint32_t RESERVED2[12]; + __I uint32_t RESET_ACTIVE_STATUS0; /*!< Reset active status register 0 */ + __I uint32_t RESET_ACTIVE_STATUS1; /*!< Reset active status register 1 */ + __I uint32_t RESERVED3[170]; + __IO uint32_t RESET_EXT_STAT[RGU_LAST_RST + 1];/*!< Reset external status registers */ +} LPC_RGU_T; + +/** + * @brief Trigger a peripheral reset for the selected peripheral + * @param ResetNumber : Peripheral reset number to trigger + * @return Nothing + */ +void Chip_RGU_TriggerReset(RGU_RST_TYPE ResetNumber); + +/** + * @brief Checks the reset status of a peripheral + * @param ResetNumber : Peripheral reset number to trigger + * @return true if the periperal is still being reset + */ +bool Chip_RGU_InReset(RGU_RST_TYPE ResetNumber); + +/** + * @brief Clears reset for the selected peripheral + * @param ResetNumber : Peripheral reset number to trigger + * @return Nothing + * Almost all peripherals will auto clear the reset bit. Only a few peripherals + * like the Cortex M0 Core in LPC43xx will not auto clear the reset and require + * this function to clear the reset bit. + */ +void Chip_RGU_ClearReset(RGU_RST_TYPE ResetNumber); + +/** + * @} + */ + +#ifdef __cplusplus +} +#endif + +#endif /* __RGU_18XX_43XX_H_ */ diff --git a/bsp/xplorer4330/libraries/lpc_chip/chip_18xx_43xx/ritimer_18xx_43xx.c b/bsp/xplorer4330/libraries/lpc_chip/chip_18xx_43xx/ritimer_18xx_43xx.c new file mode 100644 index 0000000000..7bef152182 --- /dev/null +++ b/bsp/xplorer4330/libraries/lpc_chip/chip_18xx_43xx/ritimer_18xx_43xx.c @@ -0,0 +1,67 @@ +/* + * @brief LPC18xx/43xx RITimer chip driver + * + * @note + * Copyright(C) NXP Semiconductors, 2012 + * All rights reserved. + * + * @par + * Software that is described herein is for illustrative purposes only + * which provides customers with programming information regarding the + * LPC products. This software is supplied "AS IS" without any warranties of + * any kind, and NXP Semiconductors and its licensor disclaim any and + * all warranties, express or implied, including all implied warranties of + * merchantability, fitness for a particular purpose and non-infringement of + * intellectual property rights. NXP Semiconductors assumes no responsibility + * or liability for the use of the software, conveys no license or rights under any + * patent, copyright, mask work right, or any other intellectual property rights in + * or to any products. NXP Semiconductors reserves the right to make changes + * in the software without notification. NXP Semiconductors also makes no + * representation or warranty that such application will be suitable for the + * specified use without further testing or modification. + * + * @par + * Permission to use, copy, modify, and distribute this software and its + * documentation is hereby granted, under NXP Semiconductors' and its + * licensor's relevant copyrights in the software, without fee, provided that it + * is used in conjunction with NXP Semiconductors microcontrollers. This + * copyright, permission, and disclaimer notice must appear in all copies of + * this code. + */ + +#include "ritimer_18xx_43xx.h" + +/***************************************************************************** + * Private types/enumerations/variables + ****************************************************************************/ + +/***************************************************************************** + * Public types/enumerations/variables + ****************************************************************************/ + +/***************************************************************************** + * Private functions + ****************************************************************************/ + +/***************************************************************************** + * Public functions + ****************************************************************************/ + +/* Set timer interval value */ +void Chip_RIT_SetTimerInterval(uint32_t time_interval) +{ + uint32_t clock_rate, cmp_value; + + /* Get clock rate for RITimer */ + clock_rate = Chip_Clock_GetRate(CLK_MX_RITIMER); + + /* Determine aapproximate compare value based on clock rate and passed interval */ + cmp_value = (clock_rate / 1000) * time_interval; + + /* Set timer compare value */ + Chip_RIT_SetCOMPVAL(cmp_value); + + /* Set timer enable clear bit to clear timer to 0 whenever + counter value equals the contents of RICOMPVAL */ + Chip_RIT_EnableCTRL(RIT_CTRL_ENCLR); +} diff --git a/bsp/xplorer4330/libraries/lpc_chip/chip_18xx_43xx/ritimer_18xx_43xx.h b/bsp/xplorer4330/libraries/lpc_chip/chip_18xx_43xx/ritimer_18xx_43xx.h new file mode 100644 index 0000000000..79b52bfe5d --- /dev/null +++ b/bsp/xplorer4330/libraries/lpc_chip/chip_18xx_43xx/ritimer_18xx_43xx.h @@ -0,0 +1,146 @@ +/* + * @brief LPC18xx/43xx RITimer chip driver + * + * @note + * Copyright(C) NXP Semiconductors, 2012 + * All rights reserved. + * + * @par + * Software that is described herein is for illustrative purposes only + * which provides customers with programming information regarding the + * LPC products. This software is supplied "AS IS" without any warranties of + * any kind, and NXP Semiconductors and its licensor disclaim any and + * all warranties, express or implied, including all implied warranties of + * merchantability, fitness for a particular purpose and non-infringement of + * intellectual property rights. NXP Semiconductors assumes no responsibility + * or liability for the use of the software, conveys no license or rights under any + * patent, copyright, mask work right, or any other intellectual property rights in + * or to any products. NXP Semiconductors reserves the right to make changes + * in the software without notification. NXP Semiconductors also makes no + * representation or warranty that such application will be suitable for the + * specified use without further testing or modification. + * + * @par + * Permission to use, copy, modify, and distribute this software and its + * documentation is hereby granted, under NXP Semiconductors' and its + * licensor's relevant copyrights in the software, without fee, provided that it + * is used in conjunction with NXP Semiconductors microcontrollers. This + * copyright, permission, and disclaimer notice must appear in all copies of + * this code. + */ + +#ifndef __RITIMER_18XX_43XX_H_ +#define __RITIMER_18XX_43XX_H_ + +#include "chip.h" + +#ifdef __cplusplus +extern "C" { +#endif + +/** @defgroup RIT_18XX_43XX CHIP: LPC18xx/43xx RIT driver + * @ingroup CHIP_18XX_43XX_Drivers + * @{ + */ + +/** + * @brief Initialize the RIT + * @return None + */ +STATIC INLINE void Chip_RIT_Init(void) +{ + IP_RIT_Init(LPC_RITIMER); +} + +/** + * @brief DeInitialize the RIT + * @return None + */ +STATIC INLINE void Chip_RIT_DeInit(void) +{ + IP_RIT_DeInit(LPC_RITIMER); +} + +/** + * @brief Enable/Disable Timer + * @param NewState : ENABLE to enable timer, DISABLE to stop timer + * @return None + */ +STATIC INLINE void Chip_RIT_Cmd(FunctionalState NewState) +{ + IP_RIT_Enable(LPC_RITIMER, NewState); +} + +/** + * @brief Enable or disable timer debug + * @param NewState : ENABLE to halt timer whenever a hardware break condition occurs + * @return None + */ +STATIC INLINE void Chip_RIT_TimerDebugCmd(FunctionalState NewState) +{ + IP_RIT_TimerDebugCmd(LPC_RITIMER, NewState); +} + +/** + * @brief Check whether interrupt flag is set or not + * @return Current interrupt status, either ET or UNSET + */ +STATIC INLINE IntStatus Chip_RIT_GetIntStatus(void) +{ + return IP_RIT_GetIntStatus(LPC_RITIMER); +} + +/** + * @brief Set a tick value for the interrupt to time out + * @param val : value (in ticks) of the interrupt to be set + * @return None + */ +STATIC INLINE void Chip_RIT_SetCOMPVAL(uint32_t val) +{ + IP_RIT_SetCOMPVAL(LPC_RITIMER, val); +} + +/** + * @brief Enables or clears the RIT or interrupt + * @param val : RIT to be set, one or more RIT_CTRL_* values + * @return None + */ +STATIC INLINE void Chip_RIT_EnableCTRL(uint32_t val) +{ + IP_RIT_EnableCTRL(LPC_RITIMER, val); +} + +/** + * @brief Clears the RIT interrupt + * @return None + */ +STATIC INLINE void Chip_RIT_ClearInt(void) +{ + IP_RIT_EnableCTRL(LPC_RITIMER, RIT_CTRL_INT); +} + +/** + * @brief Returns the current RIT Counter value + * @return the current timer counter value + */ +STATIC INLINE uint32_t Chip_RIT_GetCounter(void) +{ + return IP_RIT_GetCounter(LPC_RITIMER); +} + +/** + * @brief Set timer interval value + * @param time_interval : timer interval value (ms) + * @return None + */ +void Chip_RIT_SetTimerInterval(uint32_t time_interval); + +/** + * @} + */ + +#ifdef __cplusplus +} +#endif + +#endif /* __RITIMER_18XX_43XX_H_ */ diff --git a/bsp/xplorer4330/libraries/lpc_chip/chip_18xx_43xx/rtc_18xx_43xx.c b/bsp/xplorer4330/libraries/lpc_chip/chip_18xx_43xx/rtc_18xx_43xx.c new file mode 100644 index 0000000000..b0d1354f6c --- /dev/null +++ b/bsp/xplorer4330/libraries/lpc_chip/chip_18xx_43xx/rtc_18xx_43xx.c @@ -0,0 +1,57 @@ +/* + * @brief LPC18xx/43xx RTC driver + * + * @note + * Copyright(C) NXP Semiconductors, 2012 + * All rights reserved. + * + * @par + * Software that is described herein is for illustrative purposes only + * which provides customers with programming information regarding the + * LPC products. This software is supplied "AS IS" without any warranties of + * any kind, and NXP Semiconductors and its licensor disclaim any and + * all warranties, express or implied, including all implied warranties of + * merchantability, fitness for a particular purpose and non-infringement of + * intellectual property rights. NXP Semiconductors assumes no responsibility + * or liability for the use of the software, conveys no license or rights under any + * patent, copyright, mask work right, or any other intellectual property rights in + * or to any products. NXP Semiconductors reserves the right to make changes + * in the software without notification. NXP Semiconductors also makes no + * representation or warranty that such application will be suitable for the + * specified use without further testing or modification. + * + * @par + * Permission to use, copy, modify, and distribute this software and its + * documentation is hereby granted, under NXP Semiconductors' and its + * licensor's relevant copyrights in the software, without fee, provided that it + * is used in conjunction with NXP Semiconductors microcontrollers. This + * copyright, permission, and disclaimer notice must appear in all copies of + * this code. + */ + +#include "rtc_18xx_43xx.h" + +/***************************************************************************** + * Private types/enumerations/variables + ****************************************************************************/ + +/***************************************************************************** + * Public types/enumerations/variables + ****************************************************************************/ + +/***************************************************************************** + * Private functions + ****************************************************************************/ + +/***************************************************************************** + * Public functions + ****************************************************************************/ + +/* Initialize the RTC peripheral */ +void Chip_RTC_Init(void) +{ + LPC_CREG->CREG0 &= ~((1 << 3) | (1 << 2)); /* Reset 32Khz oscillator */ + LPC_CREG->CREG0 |= (1 << 1) | (1 << 0); /* Enable 32 kHz & 1 kHz on osc32k and release reset */ + LPC_SCU->SFSCLK[0] = 1 | (0x3 << 2);/* function 1; CGU clk out, pull down */ + IP_RTC_Init(LPC_RTC); +} diff --git a/bsp/xplorer4330/libraries/lpc_chip/chip_18xx_43xx/rtc_18xx_43xx.h b/bsp/xplorer4330/libraries/lpc_chip/chip_18xx_43xx/rtc_18xx_43xx.h new file mode 100644 index 0000000000..b5c42c60fc --- /dev/null +++ b/bsp/xplorer4330/libraries/lpc_chip/chip_18xx_43xx/rtc_18xx_43xx.h @@ -0,0 +1,281 @@ +/* + * @brief LPC18xx/43xx RTC driver + * + * @note + * Copyright(C) NXP Semiconductors, 2012 + * All rights reserved. + * + * @par + * Software that is described herein is for illustrative purposes only + * which provides customers with programming information regarding the + * LPC products. This software is supplied "AS IS" without any warranties of + * any kind, and NXP Semiconductors and its licensor disclaim any and + * all warranties, express or implied, including all implied warranties of + * merchantability, fitness for a particular purpose and non-infringement of + * intellectual property rights. NXP Semiconductors assumes no responsibility + * or liability for the use of the software, conveys no license or rights under any + * patent, copyright, mask work right, or any other intellectual property rights in + * or to any products. NXP Semiconductors reserves the right to make changes + * in the software without notification. NXP Semiconductors also makes no + * representation or warranty that such application will be suitable for the + * specified use without further testing or modification. + * + * @par + * Permission to use, copy, modify, and distribute this software and its + * documentation is hereby granted, under NXP Semiconductors' and its + * licensor's relevant copyrights in the software, without fee, provided that it + * is used in conjunction with NXP Semiconductors microcontrollers. This + * copyright, permission, and disclaimer notice must appear in all copies of + * this code. + */ + +#ifndef __RTC_18XX_43XX_H_ +#define __RTC_18XX_43XX_H_ + +#include "chip.h" + +#ifdef __cplusplus +extern "C" { +#endif + +/** @defgroup RTC_18XX_43XX CHIP: LPC18xx/43xx RTC driver + * @ingroup CHIP_18XX_43XX_Drivers + * @{ + */ + +/** + * @brief Initialize the RTC peripheral + * @return None + */ +void Chip_RTC_Init(void); + +/** + * @brief De-initialize the RTC peripheral + * @return None + */ +STATIC INLINE void Chip_RTC_DeInit(void) +{ + IP_RTC_DeInit(LPC_RTC); +} + +/** + * @brief Reset clock tick counter in the RTC peripheral + * @return None + */ +STATIC INLINE void Chip_RTC_ResetClockTickCounter(void) +{ + IP_RTC_ResetClockTickCounter(LPC_RTC); +} + +/** + * @brief Start/Stop RTC peripheral + * @param NewState : New State of this function, should be: + * - ENABLE :The time counters are enabled + * - DISABLE :The time counters are disabled + * @return None + */ +STATIC INLINE void Chip_RTC_Enable(FunctionalState NewState) +{ + IP_RTC_Enable(LPC_RTC, NewState); +} + +/** + * @brief Enable/Disable Counter increment interrupt for a time type + * in the RTC peripheral + * @param cntrMask : Or'ed bit values for time types (RTC_AMR_CIIR_IM*) + * @param NewState : ENABLE or DISABLE + * @return None + */ +STATIC INLINE void Chip_RTC_CntIncrIntConfig(uint32_t cntrMask, FunctionalState NewState) +{ + IP_RTC_CntIncrIntConfig(LPC_RTC, cntrMask, NewState); +} + +/** + * @brief Enable/Disable Alarm interrupt for a time type + * in the RTC peripheral + * @param alarmMask : Or'ed bit values for ALARM types (RTC_AMR_CIIR_IM*) + * @param NewState : ENABLE or DISABLE + * @return None + */ +STATIC INLINE void Chip_RTC_AlarmIntConfig(uint32_t alarmMask, FunctionalState NewState) +{ + IP_RTC_AlarmIntConfig(LPC_RTC, alarmMask, NewState); +} + +/** + * @brief Set current time value for a time type in the RTC peripheral + * @param Timetype : time field index type to set + * @param TimeValue : Value to palce in time field + * @return None + */ +STATIC INLINE void Chip_RTC_SetTime(IP_RTC_TIMEINDEX_T Timetype, uint32_t TimeValue) +{ + IP_RTC_SetTime(LPC_RTC, Timetype, TimeValue); +} + +/** + * @brief Get current time value for a type time type + * @param Timetype : Time field index type to get + * @return Value of time field according to specified time type + */ +STATIC INLINE uint32_t Chip_RTC_GetTime(IP_RTC_TIMEINDEX_T Timetype) +{ + return IP_RTC_GetTime(LPC_RTC, Timetype); +} + +/** + * @brief Set full time in the RTC peripheral + * @param pFullTime : Pointer to full time data + * @return None + */ +STATIC INLINE void Chip_RTC_SetFullTime(IP_RTC_TIME_T *pFullTime) +{ + IP_RTC_SetFullTime(LPC_RTC, pFullTime); +} + +/** + * @brief Get full time from the RTC peripheral + * @param pFullTime : Pointer to full time record to fill + * @return None + */ +STATIC INLINE void Chip_RTC_GetFullTime(IP_RTC_TIME_T *pFullTime) +{ + IP_RTC_GetFullTime(LPC_RTC, pFullTime); +} + +/** + * @brief Set alarm time value for a time type + * @param Timetype : Time index field to set + * @param ALValue : Alarm time value to set + * @return None + */ +STATIC INLINE void Chip_RTC_SetAlarmTime(IP_RTC_TIMEINDEX_T Timetype, uint32_t ALValue) +{ + IP_RTC_SetAlarmTime(LPC_RTC, Timetype, ALValue); +} + +/** + * @brief Get alarm time value for a time type + * @param Timetype : Time index field to get + * @return Value of Alarm time according to specified time type + */ +STATIC INLINE uint32_t Chip_RTC_GetAlarmTime(IP_RTC_TIMEINDEX_T Timetype) +{ + return IP_RTC_GetAlarmTime(LPC_RTC, Timetype); +} + +/** + * @brief Set full alarm time in the RTC peripheral + * @param pFullTime : Pointer to full time record to set alarm + * @return None + */ +STATIC INLINE void Chip_RTC_SetFullAlarmTime(IP_RTC_TIME_T *pFullTime) +{ + IP_RTC_SetFullAlarmTime(LPC_RTC, pFullTime); +} + +/** + * @brief Get full alarm time in the RTC peripheral + * @param pFullTime : Pointer to full time record to fill + * @return None + */ +STATIC INLINE void Chip_RTC_GetFullAlarmTime(IP_RTC_TIME_T *pFullTime) +{ + IP_RTC_GetFullAlarmTime(LPC_RTC, pFullTime); +} + +/** + * @brief Write value to General purpose registers + * @param index : General purpose register index + * @param Value : Value to write + * @return None + * Note: These General purpose registers can be used to store important + + * information when the main power supply is off. The value in these + + * registers is not affected by chip reset. These registers are + + * powered in the RTC power domain. + */ +STATIC INLINE void Chip_REGFILE_Write(uint8_t index, uint32_t Value) +{ + IP_REGFILE_Write(LPC_REGFILE, index, Value); +} + +/** + * @brief Read value from General purpose registers + * @param index : General purpose register index + * @return Read Value + * These General purpose registers can be used to store important + + * information when the main power supply is off. The value in these + + * registers is not affected by chip reset. These registers are + + * powered in the RTC power domain. + */ +STATIC INLINE uint32_t Chip_REGFILE_Read(uint8_t index) +{ + return IP_REGFILE_Read(LPC_REGFILE, index); +} + +/** + * @brief Enable/Disable calibration counter in the RTC peripheral + * @param NewState : New State of this function, should be: + * - ENABLE :The calibration counter is enabled and counting + * - DISABLE :The calibration counter is disabled and reset to zero + * @return None + */ +STATIC INLINE void Chip_RTC_CalibCounterCmd(FunctionalState NewState) +{ + IP_RTC_CalibCounterCmd(LPC_RTC, NewState); +} + +/** + * @brief Configures Calibration in the RTC peripheral + * @param CalibValue : Calibration value, should be in range from 0 to 131,072 + * @param CalibDir : Calibration Direction, should be: + * - RTC_CALIB_DIR_FORWARD :Forward calibration + * - RTC_CALIB_DIR_BACKWARD :Backward calibration + * @return None + */ +STATIC INLINE void Chip_RTC_CalibConfig(uint32_t CalibValue, uint8_t CalibDir) +{ + IP_RTC_CalibConfig(LPC_RTC, CalibValue, CalibDir); +} + +/** + * @brief Clear specified Location interrupt pending in the RTC peripheral + * @param IntType : Interrupt location type, should be: + * - RTC_INT_COUNTER_INCREASE :Clear Counter Increment Interrupt pending. + * - RTC_INT_ALARM :Clear alarm interrupt pending + * @return None + */ +STATIC INLINE void Chip_RTC_ClearIntPending(uint32_t IntType) +{ + IP_RTC_ClearIntPending(LPC_RTC, IntType); +} + +/** + * @brief Check whether if specified location interrupt in the + * RTC peripheral is set or not + * @param IntType : Interrupt location type, should be: + * - RTC_INT_COUNTER_INCREASE: Counter Increment Interrupt block generated an interrupt. + * - RTC_INT_ALARM: Alarm generated an interrupt. + * @return New state of specified Location interrupt in RTC peripheral, SET OR RESET + */ +STATIC INLINE IntStatus Chip_RTC_GetIntPending(uint32_t IntType) +{ + return IP_RTC_GetIntPending(LPC_RTC, IntType); +} + +/** + * @} + */ + +#ifdef __cplusplus +} +#endif + +#endif /* __RTC_18XX_43XX_H_ */ diff --git a/bsp/xplorer4330/libraries/lpc_chip/chip_18xx_43xx/scu_18xx_43xx.c b/bsp/xplorer4330/libraries/lpc_chip/chip_18xx_43xx/scu_18xx_43xx.c new file mode 100644 index 0000000000..17ceb5a7f1 --- /dev/null +++ b/bsp/xplorer4330/libraries/lpc_chip/chip_18xx_43xx/scu_18xx_43xx.c @@ -0,0 +1,80 @@ +/* + * @brief LPC18xx/43xx System Control Unit (SCU) control functions + * + * @note + * Copyright(C) NXP Semiconductors, 2012 + * All rights reserved. + * + * @par + * Software that is described herein is for illustrative purposes only + * which provides customers with programming information regarding the + * LPC products. This software is supplied "AS IS" without any warranties of + * any kind, and NXP Semiconductors and its licensor disclaim any and + * all warranties, express or implied, including all implied warranties of + * merchantability, fitness for a particular purpose and non-infringement of + * intellectual property rights. NXP Semiconductors assumes no responsibility + * or liability for the use of the software, conveys no license or rights under any + * patent, copyright, mask work right, or any other intellectual property rights in + * or to any products. NXP Semiconductors reserves the right to make changes + * in the software without notification. NXP Semiconductors also makes no + * representation or warranty that such application will be suitable for the + * specified use without further testing or modification. + * + * @par + * Permission to use, copy, modify, and distribute this software and its + * documentation is hereby granted, under NXP Semiconductors' and its + * licensor's relevant copyrights in the software, without fee, provided that it + * is used in conjunction with NXP Semiconductors microcontrollers. This + * copyright, permission, and disclaimer notice must appear in all copies of + * this code. + */ + +#include "scu_18xx_43xx.h" + +/***************************************************************************** + * Private types/enumerations/variables + ****************************************************************************/ + +/***************************************************************************** + * Public types/enumerations/variables + ****************************************************************************/ + +/***************************************************************************** + * Private functions + ****************************************************************************/ + +/***************************************************************************** + * Public functions + ****************************************************************************/ + +/* Configure pin function */ +void Chip_SCU_PinMux(uint8_t port, uint8_t pin, uint8_t mode, uint8_t func) +{ + if (port == PINMUX_CLK) { + LPC_SCU_CLK(((uint32_t) LPC_SCU), pin) = mode + func; + } + else { + LPC_SCU->SFSP[port][pin] = mode + func; + } +} + +/* GPIO Interrupt Pin Select */ +void Chip_SCU_GPIOIntPinSel(uint8_t PortSel, uint8_t PortNum, uint8_t PinNum) +{ + uint8_t pinInt; + volatile uint32_t pinSel; + + pinInt = ((PortNum & 0x7) << 5) | (PinNum & 0x1F); + if (PortSel < 4) { + pinSel = LPC_SCU->PINTSEL0; + pinSel &= ~(0xFF << (PortSel * 8)); + pinSel |= (pinInt << (PortSel * 8)); + LPC_SCU->PINTSEL0 = pinSel; + } + else { + pinSel = LPC_SCU->PINTSEL1; + pinSel &= ~(0xFF << ((PortSel - 4) * 8)); + pinSel |= (pinInt << ((PortSel - 4) * 8)); + LPC_SCU->PINTSEL1 = pinSel; + } +} diff --git a/bsp/xplorer4330/libraries/lpc_chip/chip_18xx_43xx/scu_18xx_43xx.h b/bsp/xplorer4330/libraries/lpc_chip/chip_18xx_43xx/scu_18xx_43xx.h new file mode 100644 index 0000000000..5ca9db2c4b --- /dev/null +++ b/bsp/xplorer4330/libraries/lpc_chip/chip_18xx_43xx/scu_18xx_43xx.h @@ -0,0 +1,171 @@ +/* + * Copyright(C) NXP Semiconductors, 2012 + * All rights reserved. + * + * Software that is described herein is for illustrative purposes only + * which provides customers with programming information regarding the + * LPC products. This software is supplied "AS IS" without any warranties of + * any kind, and NXP Semiconductors and its licensor disclaim any and + * all warranties, express or implied, including all implied warranties of + * merchantability, fitness for a particular purpose and non-infringement of + * intellectual property rights. NXP Semiconductors assumes no responsibility + * or liability for the use of the software, conveys no license or rights under any + * patent, copyright, mask work right, or any other intellectual property rights in + * or to any products. NXP Semiconductors reserves the right to make changes + * in the software without notification. NXP Semiconductors also makes no + * representation or warranty that such application will be suitable for the + * specified use without further testing or modification. + * + * Permission to use, copy, modify, and distribute this software and its + * documentation is hereby granted, under NXP Semiconductors' and its + * licensor's relevant copyrights in the software, without fee, provided that it + * is used in conjunction with NXP Semiconductors microcontrollers. This + * copyright, permission, and disclaimer notice must appear in all copies of + * this code. + */ + +#ifndef __SCU_18XX_43XX_H_ +#define __SCU_18XX_43XX_H_ + +#include "chip.h" + +#ifdef __cplusplus +extern "C" { +#endif + +/** @defgroup SCU_18XX_43XX CHIP: LPC18xx/43xx SCU Driver (configures pin functions) + * @ingroup CHIP_18XX_43XX_Drivers + * @{ + */ + +/** + * @brief System Control Unit register block + */ +typedef struct { + __IO uint32_t SFSP[16][32]; + __I uint32_t RESERVED0[256]; + __IO uint32_t SFSCLK[4]; /*!< Pin configuration register for pins CLK0-3 */ + __I uint32_t RESERVED16[28]; + __IO uint32_t SFSUSB; /*!< Pin configuration register for USB */ + __IO uint32_t SFSI2C0; /*!< Pin configuration register for I2C0-bus pins */ + __IO uint32_t ENAIO[3]; /*!< Analog function select registerS */ + __I uint32_t RESERVED17[27]; + __IO uint32_t EMCDELAYCLK; /*!< EMC clock delay register */ + __I uint32_t RESERVED18[63]; + __IO uint32_t PINTSEL0; /*!< Pin interrupt select register for pin interrupts 0 to 3. */ + __IO uint32_t PINTSEL1; /*!< Pin interrupt select register for pin interrupts 4 to 7. */ +} LPC_SCU_Type; + +/** Port offset definition */ +#define PORT_OFFSET 0x80 + +/** Pin offset definition */ +#define PIN_OFFSET 0x04 + +/** Disable pull-down and pull-up resistor at resistor at pad */ +#define MD_PUP (0x0 << 3) + +/** Enable pull-down resistor at pad */ +#define MD_BUK (0x1 << 3) + +/** Enable pull-up resistor at pad */ +#define MD_PLN (0x2 << 3) + +/** Enable pull-down and pull-up resistor at resistor at pad (repeater mode) */ +#define MD_PDN (0x3 << 3) + +/** Enable fast slew rate */ +#define MD_EHS (0x1 << 5) + +/** Input buffer enable */ +#define MD_EZI (0x1 << 6) + +/** Disable input glitch filter */ +#define MD_ZI (0x1 << 7) + +/** EHD driver strength low bit */ +#define MD_EHD0 (0x1 << 8) + +/** EHD driver strength high bit */ +#define MD_EHD1 (0x1 << 8) + +#define MD_PLN_FAST (MD_PLN | MD_EZI | MD_ZI | MD_EHS) + +/** Pin configuration for STANDARD/FAST mode I2C */ +#define I2C0_STANDARD_FAST_MODE (1 << 3 | 1 << 11) + +/** Pin configuration for Fast-mode Plus I2C */ +#define I2C0_FAST_MODE_PLUS (2 << 1 | 1 << 3 | 1 << 7 | 1 << 10 | 1 << 11) + +#define FUNC0 0x0 /** Pin function 0 */ +#define FUNC1 0x1 /** Pin function 1 */ +#define FUNC2 0x2 /** Pin function 2 */ +#define FUNC3 0x3 /** Pin function 3 */ +#define FUNC4 0x4 /** Pin function 4 */ +#define FUNC5 0x5 /** Pin function 5 */ +#define FUNC6 0x6 /** Pin function 6 */ +#define FUNC7 0x7 /** Pin function 7 */ + +/** Returns the SFSP register address in the SCU for a pin and port */ +#define LPC_SCU_PIN(LPC_SCU_BASE, po, pi) (*(volatile int *) ((LPC_SCU_BASE) + ((po) * 0x80) + ((pi) * 0x4)) + +/** Returns the address in the SCU for a SFSCLK clock register */ +#define LPC_SCU_CLK(LPC_SCU_BASE, c) (*(volatile int *) ((LPC_SCU_BASE) +0xC00 + ((c) * 0x4))) + +#define PINMUX_CLK 0xFF + +/** + * @brief Configure pin function + * @param port : Port number, should be: 0..15 + * @param pin : Pin number, should be: 0..31 + * @param mode : Pin mode, should be: + * - MD_PUP :Pull-up enabled + * - MD_BUK :Plain input + * - MD_PLN :Repeater mode + * - MD_PDN :Pull-down enabled + * @param func : Function mode, should be: FUNC0 to FUNC7 + * @return None + */ +void Chip_SCU_PinMux(uint8_t port, uint8_t pin, uint8_t mode, uint8_t func); + +/** + * @brief GPIO Interrupt Pin Select + * @param PortSel : GPIO PINTSEL interrupt, should be: 0 to 7 + * @param PortNum : GPIO port number interrupt, should be: 0 to 7 + * @param PinNum : GPIO pin number Interrupt , should be: 0 to 31 + * @return None + */ +void Chip_SCU_GPIOIntPinSel(uint8_t PortSel, uint8_t PortNum, uint8_t PinNum); + +/** + * @brief I2C Pin Configuration + * @param I2C0Mode : I2C0 mode, should be: + * - I2C0_STANDARD_FAST_MODE: Standard/Fast mode transmit + * - I2C0_FAST_MODE_PLUS: Fast-mode Plus transmit + * @return None + */ +STATIC INLINE void Chip_SCU_I2C0PinConfig(uint32_t I2C0Mode) +{ + LPC_SCU->SFSI2C0 = I2C0Mode; +} + +/** + * @brief ADC Pin Configuration + * @param ADC_ID : ADC number + * @param channel : ADC channel + * @return None + */ +STATIC INLINE void Chip_SCU_ADC_Channel_Config(uint32_t ADC_ID, uint8_t channel) +{ + LPC_SCU->ENAIO[ADC_ID] |= 1UL << channel; +} + +/** + * @} + */ + +#ifdef __cplusplus +} +#endif + +#endif /* __SCU_18XX_43XX_H_ */ diff --git a/bsp/xplorer4330/libraries/lpc_chip/chip_18xx_43xx/sdmmc_18xx_43xx.c b/bsp/xplorer4330/libraries/lpc_chip/chip_18xx_43xx/sdmmc_18xx_43xx.c new file mode 100644 index 0000000000..4362f826fd --- /dev/null +++ b/bsp/xplorer4330/libraries/lpc_chip/chip_18xx_43xx/sdmmc_18xx_43xx.c @@ -0,0 +1,597 @@ +/* + * @brief LPC18xx/43xx SD/SDIO driver + * + * @note + * Copyright(C) NXP Semiconductors, 2012 + * All rights reserved. + * + * @par + * Software that is described herein is for illustrative purposes only + * which provides customers with programming information regarding the + * LPC products. This software is supplied "AS IS" without any warranties of + * any kind, and NXP Semiconductors and its licensor disclaim any and + * all warranties, express or implied, including all implied warranties of + * merchantability, fitness for a particular purpose and non-infringement of + * intellectual property rights. NXP Semiconductors assumes no responsibility + * or liability for the use of the software, conveys no license or rights under any + * patent, copyright, mask work right, or any other intellectual property rights in + * or to any products. NXP Semiconductors reserves the right to make changes + * in the software without notification. NXP Semiconductors also makes no + * representation or warranty that such application will be suitable for the + * specified use without further testing or modification. + * + * @par + * Permission to use, copy, modify, and distribute this software and its + * documentation is hereby granted, under NXP Semiconductors' and its + * licensor's relevant copyrights in the software, without fee, provided that it + * is used in conjunction with NXP Semiconductors microcontrollers. This + * copyright, permission, and disclaimer notice must appear in all copies of + * this code. + */ + +#include "sdmmc_18xx_43xx.h" +#include "string.h" + +/***************************************************************************** + * Private types/enumerations/variables + ****************************************************************************/ + +/* Global instance of the current card */ +static mci_card_struct *g_card_info; + +/* Helper definition: all SD error conditions in the status word */ +#define SD_INT_ERROR (MCI_INT_RESP_ERR | MCI_INT_RCRC | MCI_INT_DCRC | \ + MCI_INT_RTO | MCI_INT_DTO | MCI_INT_HTO | MCI_INT_FRUN | MCI_INT_HLE | \ + MCI_INT_SBE | MCI_INT_EBE) + +/***************************************************************************** + * Public types/enumerations/variables + ****************************************************************************/ + +/***************************************************************************** + * Private functions + ****************************************************************************/ + +/* Function to execute a command */ +static int32_t sdmmc_execute_command(uint32_t cmd, uint32_t arg, uint32_t wait_status) +{ + int32_t step = (cmd & CMD_BIT_APP) ? 2 : 1; + int32_t status = 0; + uint32_t cmd_reg = 0; + + if (!wait_status) { + wait_status = (cmd & CMD_MASK_RESP) ? MCI_INT_CMD_DONE : MCI_INT_DATA_OVER; + } + + /* Clear the interrupts & FIFOs*/ + if (cmd & CMD_BIT_DATA) { + IP_SDMMC_SetClearIntFifo(LPC_SDMMC); + } + + /* also check error conditions */ + wait_status |= MCI_INT_EBE | MCI_INT_SBE | MCI_INT_HLE | MCI_INT_RTO | MCI_INT_RCRC | MCI_INT_RESP_ERR; + if (wait_status & MCI_INT_DATA_OVER) { + wait_status |= MCI_INT_FRUN | MCI_INT_HTO | MCI_INT_DTO | MCI_INT_DCRC; + } + + while (step) { + IP_SDMMC_SetClock(LPC_SDMMC, g_card_info->clk_rate, g_card_info->speed); + + /* Clear the interrupts */ + IP_SDMMC_SetRawIntStatus(LPC_SDMMC, 0xFFFFFFFF); + + g_card_info->evsetup_cb(wait_status); + + switch (step) { + case 1: /* Execute command */ + cmd_reg = ((cmd & CMD_MASK_CMD) >> CMD_SHIFT_CMD) | + ((cmd & CMD_BIT_INIT) ? MCI_CMD_INIT : 0) | + ((cmd & CMD_BIT_DATA) ? (MCI_CMD_DAT_EXP | MCI_CMD_PRV_DAT_WAIT) : 0) | + (((cmd & CMD_MASK_RESP) == CMD_RESP_R2) ? MCI_CMD_RESP_LONG : 0) | + ((cmd & CMD_MASK_RESP) ? MCI_CMD_RESP_EXP : 0) | + ((cmd & CMD_BIT_WRITE) ? MCI_CMD_DAT_WR : 0) | + ((cmd & CMD_BIT_STREAM) ? MCI_CMD_STRM_MODE : 0) | + ((cmd & CMD_BIT_BUSY) ? MCI_CMD_STOP : 0) | + ((cmd & CMD_BIT_AUTO_STOP) ? MCI_CMD_SEND_STOP : 0) | + MCI_CMD_START; + + /* wait for previos data finsh for select/deselect commands */ + if (((cmd & CMD_MASK_CMD) >> CMD_SHIFT_CMD) == MMC_SELECT_CARD) { + cmd_reg |= MCI_CMD_PRV_DAT_WAIT; + } + + /* wait for command to be accepted by CIU */ + if (IP_SDMMC_SendCmd(LPC_SDMMC, cmd_reg, arg) == 0) { + --step; + } + break; + + case 0: + return 0; + + case 2: /* APP prefix */ + cmd_reg = MMC_APP_CMD | MCI_CMD_RESP_EXP | + ((cmd & CMD_BIT_INIT) ? MCI_CMD_INIT : 0) | + MCI_CMD_START; + + if (IP_SDMMC_SendCmd(LPC_SDMMC, cmd_reg, g_card_info->rca << 16) == 0) { + --step; + } + break; + } + + /* wait for command response */ + status = g_card_info->waitfunc_cb(); + + /* We return an error if there is a timeout, even if we've fetched a response */ + if (status & SD_INT_ERROR) { + return status; + } + + if (status & MCI_INT_CMD_DONE) { + switch (cmd & CMD_MASK_RESP) { + case 0: + break; + + case CMD_RESP_R1: + case CMD_RESP_R3: + case CMD_RESP_R2: + IP_SDMMC_GetResponse(LPC_SDMMC, &g_card_info->response[0]); + break; + } + } + } + + return 0; +} + +/* Checks whether card is acquired properly or not */ +static int32_t prv_card_acquired(void) +{ + return g_card_info->cid[0] != 0; +} + +/* Helper function to get a bit field withing multi-word buffer. Used to get + fields with-in CSD & EXT-CSD */ +static uint32_t prv_get_bits(int32_t start, int32_t end, uint32_t *data) +{ + uint32_t v; + uint32_t i = end >> 5; + uint32_t j = start & 0x1f; + + if (i == (start >> 5)) { + v = (data[i] >> j); + } + else { + v = ((data[i] << (32 - j)) | (data[start >> 5] >> j)); + } + + return v & ((1 << (end - start + 1)) - 1); +} + +/* Function to process the CSD & EXT-CSD of the card */ +static void prv_process_csd(void) +{ + int32_t status = 0; + int32_t c_size = 0; + int32_t c_size_mult = 0; + int32_t mult = 0; + + /* compute block length based on CSD response */ + g_card_info->block_len = 1 << prv_get_bits(80, 83, g_card_info->csd); + + if ((g_card_info->card_type & CARD_TYPE_HC) && (g_card_info->card_type & CARD_TYPE_SD)) { + /* See section 5.3.3 CSD Register (CSD Version 2.0) of SD2.0 spec an explanation for the calculation of these values */ + c_size = prv_get_bits(48, 63, (uint32_t *) g_card_info->csd) + 1; + g_card_info->blocknr = c_size << 10;/* 512 byte blocks */ + } + else { + /* See section 5.3 of the 4.1 revision of the MMC specs for an explanation for the calculation of these values */ + c_size = prv_get_bits(62, 73, (uint32_t *) g_card_info->csd); + c_size_mult = prv_get_bits(47, 49, (uint32_t *) g_card_info->csd); + mult = 1 << (c_size_mult + 2); + g_card_info->blocknr = (c_size + 1) * mult; + + /* adjust blocknr to 512/block */ + if (g_card_info->block_len > MMC_SECTOR_SIZE) { + g_card_info->blocknr = g_card_info->blocknr * (g_card_info->block_len >> 9); + } + + /* get extended CSD for newer MMC cards CSD spec >= 4.0*/ + if (((g_card_info->card_type & CARD_TYPE_SD) == 0) && + (prv_get_bits(122, 125, (uint32_t *) g_card_info->csd) >= 4)) { + /* put card in trans state */ + status = sdmmc_execute_command(CMD_SELECT_CARD, g_card_info->rca << 16, 0); + + /* set block size and byte count */ + IP_SDMMC_SetBlockSize(LPC_SDMMC, MMC_SECTOR_SIZE); + + /* send EXT_CSD command */ + IP_SDMMC_DmaSetup(LPC_SDMMC, &g_card_info->sdif_dev, (uint32_t) g_card_info->ext_csd, MMC_SECTOR_SIZE); + + status = sdmmc_execute_command(CMD_SEND_EXT_CSD, 0, 0 | MCI_INT_DATA_OVER); + if ((status & SD_INT_ERROR) == 0) { + /* check EXT_CSD_VER is greater than 1.1 */ + if ((g_card_info->ext_csd[48] & 0xFF) > 1) { + g_card_info->blocknr = g_card_info->ext_csd[53];/* bytes 212:215 represent sec count */ + + } + /* switch to 52MHz clock if card type is set to 1 or else set to 26MHz */ + if ((g_card_info->ext_csd[49] & 0xFF) == 1) { + /* for type 1 MMC cards high speed is 52MHz */ + g_card_info->speed = MMC_HIGH_BUS_MAX_CLOCK; + } + else { + /* for type 0 MMC cards high speed is 26MHz */ + g_card_info->speed = MMC_LOW_BUS_MAX_CLOCK; + } + } + } + } + + g_card_info->device_size = g_card_info->blocknr << 9; /* blocknr * 512 */ +} + +/* Puts current selected card in trans state */ +static int32_t prv_set_trans_state(void) +{ + uint32_t status; + + /* get current state of the card */ + status = sdmmc_execute_command(CMD_SEND_STATUS, g_card_info->rca << 16, 0); + if (status & MCI_INT_RTO) { + /* unable to get the card state. So return immediatly. */ + return -1; + } + + /* check card state in response */ + status = R1_CURRENT_STATE(g_card_info->response[0]); + switch (status) { + case SDMMC_STBY_ST: + /* put card in 'Trans' state */ + status = sdmmc_execute_command(CMD_SELECT_CARD, g_card_info->rca << 16, 0); + if (status != 0) { + /* unable to put the card in Trans state. So return immediatly. */ + return -1; + } + break; + + case SDMMC_TRAN_ST: + /*do nothing */ + break; + + default: + /* card shouldn't be in other states so return */ + return -1; + } + + return 0; +} + +/* Sets card data width and block size */ +static int32_t prv_set_card_params(void) +{ + int32_t status; + +#if SDIO_BUS_WIDTH > 1 + if (g_card_info->card_type & CARD_TYPE_SD) { + status = sdmmc_execute_command(CMD_SD_SET_WIDTH, 2, 0); + if (status != 0) { + return -1; + } + + /* if positive response */ + IP_SDMMC_SetCardType(LPC_SDMMC, MCI_CTYPE_4BIT); + LPC_SDMMC->CTYPE = MCI_CTYPE_4BIT; + } +#elif SDIO_BUS_WIDTH > 4 +#error 8-bit mode not supported yet! +#endif + + /* set block length */ + IP_SDMMC_SetBlkSize(LPC_SDMMC, MMC_SECTOR_SIZE); + status = sdmmc_execute_command(CMD_SET_BLOCKLEN, MMC_SECTOR_SIZE, 0); + if (status != 0) { + return -1; + } + + return 0; +} + +/***************************************************************************** + * Public functions + ****************************************************************************/ + +/* Returns the current SD status, clears pending ints, and disables all ints */ +uint32_t Chip_SDMMC_GetIntStatus(void) +{ + uint32_t status; + + /* Get status and clear interrupts */ + status = IP_SDMMC_GetRawIntStatus(LPC_SDMMC); + IP_SDMMC_SetRawIntStatus(LPC_SDMMC, status); + IP_SDMMC_SetIntMask(LPC_SDMMC, 0); + + return status; +} + +/* Get card's current state (idle, transfer, program, etc.) */ +int32_t Chip_SDMMC_GetState(void) +{ + uint32_t status; + + /* get current state of the card */ + status = sdmmc_execute_command(CMD_SEND_STATUS, g_card_info->rca << 16, 0); + if (status & MCI_INT_RTO) { + return -1; + } + + /* check card state in response */ + return (int32_t) R1_CURRENT_STATE(g_card_info->response[0]); +} + +/* Function to enumerate the SD/MMC/SDHC/MMC+ cards */ +uint32_t Chip_SDMMC_Acquire(mci_card_struct *pcardinfo) +{ + int32_t status; + int32_t tries = 0; + uint32_t ocr = OCR_VOLTAGE_RANGE_MSK; + uint32_t r; + int32_t state = 0; + uint32_t command = 0; + + g_card_info = pcardinfo; + + /* clear card type */ + IP_SDMMC_SetCardType(LPC_SDMMC, 0); + + /* set high speed for the card as 20MHz */ + g_card_info->speed = MMC_MAX_CLOCK; + + status = sdmmc_execute_command(CMD_IDLE, 0, MCI_INT_CMD_DONE); + + while (state < 100) { + switch (state) { + case 0: /* Setup for SD */ + /* check if it is SDHC card */ + status = sdmmc_execute_command(CMD_SD_SEND_IF_COND, SD_SEND_IF_ARG, 0); + if (!(status & MCI_INT_RTO)) { + /* check response has same echo pattern */ + if ((g_card_info->response[0] & SD_SEND_IF_ECHO_MSK) == SD_SEND_IF_RESP) { + ocr |= OCR_HC_CCS; + } + } + + ++state; + command = CMD_SD_OP_COND; + tries = INIT_OP_RETRIES; + + /* assume SD card */ + g_card_info->card_type |= CARD_TYPE_SD; + g_card_info->speed = SD_MAX_CLOCK; + break; + + case 10: /* Setup for MMC */ + /* start fresh for MMC crds */ + g_card_info->card_type &= ~CARD_TYPE_SD; + status = sdmmc_execute_command(CMD_IDLE, 0, MCI_INT_CMD_DONE); + command = CMD_MMC_OP_COND; + tries = INIT_OP_RETRIES; + ocr |= OCR_HC_CCS; + ++state; + + /* for MMC cards high speed is 20MHz */ + g_card_info->speed = MMC_MAX_CLOCK; + break; + + case 1: + case 11: + status = sdmmc_execute_command(command, 0, 0); + if (status & MCI_INT_RTO) { + state += 9; /* Mode unavailable */ + } + else { + ++state; + } + break; + + case 2: /* Initial OCR check */ + case 12: + ocr = g_card_info->response[0] | (ocr & OCR_HC_CCS); + if (ocr & OCR_ALL_READY) { + ++state; + } + else { + state += 2; + } + break; + + case 3: /* Initial wait for OCR clear */ + case 13: + while ((ocr & OCR_ALL_READY) && --tries > 0) { + g_card_info->msdelay_func(MS_ACQUIRE_DELAY); + status = sdmmc_execute_command(command, 0, 0); + ocr = g_card_info->response[0] | (ocr & OCR_HC_CCS); + } + if (ocr & OCR_ALL_READY) { + state += 7; + } + else { + ++state; + } + break; + + case 14: + /* for MMC cards set high capacity bit */ + ocr |= OCR_HC_CCS; + + case 4: /* Assign OCR */ + tries = SET_OP_RETRIES; + ocr &= OCR_VOLTAGE_RANGE_MSK | OCR_HC_CCS; /* Mask for the bits we care about */ + do { + g_card_info->msdelay_func(MS_ACQUIRE_DELAY); + status = sdmmc_execute_command(command, ocr, 0); + r = g_card_info->response[0]; + } while (!(r & OCR_ALL_READY) && --tries > 0); + + if (r & OCR_ALL_READY) { + /* is it high capacity card */ + g_card_info->card_type |= (r & OCR_HC_CCS); + ++state; + } + else { + state += 6; + } + break; + + case 5: /* CID polling */ + case 15: + status = sdmmc_execute_command(CMD_ALL_SEND_CID, 0, 0); + memcpy(&g_card_info->cid, &g_card_info->response[0], 16); + ++state; + break; + + case 6: /* RCA send, for SD get RCA */ + status = sdmmc_execute_command(CMD_SD_SEND_RCA, 0, 0); + g_card_info->rca = (g_card_info->response[0]) >> 16; + ++state; + break; + + case 16: /* RCA assignment for MMC set to 1 */ + g_card_info->rca = 1; + status = sdmmc_execute_command(CMD_MMC_SET_RCA, g_card_info->rca << 16, 0); + ++state; + break; + + case 7: + case 17: + status = sdmmc_execute_command(CMD_SEND_CSD, g_card_info->rca << 16, 0); + memcpy(&g_card_info->csd, &g_card_info->response[0], 16); + state = 100; + break; + + default: + state += 100; /* break from while loop */ + break; + } + } + + /* Compute card size, block size and no. of blocks based on CSD response recived. */ + if (prv_card_acquired()) { + prv_process_csd(); + + /* Setup card data width and block size (once) */ + if (prv_set_trans_state() != 0) { + return 0; + } + if (prv_set_card_params() != 0) { + return 0; + } + } + + return prv_card_acquired(); +} + +/* Get the device size of SD/MMC card (after enumeration) */ +int32_t Chip_SDMMC_GetDeviceSize(void) +{ + return g_card_info->device_size; +} + +/* Performs the read of data from the SD/MMC card */ +int32_t Chip_SDMMC_ReadBlocks(void *buffer, int32_t start_block, int32_t num_blocks) +{ + int32_t cbRead = (num_blocks) * MMC_SECTOR_SIZE; + int32_t status = 0; + int32_t index; + + /* if card is not acquired return immediately */ + if (( start_block < 0) || ( (start_block + num_blocks) > g_card_info->blocknr) ) { + return 0; + } + + /* put card in trans state */ + if (prv_set_trans_state() != 0) { + return 0; + } + + /* set number of bytes to read */ + LPC_SDMMC->BYTCNT = cbRead; + + /* if high capacity card use block indexing */ + if (g_card_info->card_type & CARD_TYPE_HC) { + index = start_block; + } + else { /*fix at 512 bytes*/ + index = start_block << 9; // \* g_card_info->block_len; + + } + IP_SDMMC_DmaSetup(LPC_SDMMC, &g_card_info->sdif_dev, (uint32_t) buffer, cbRead); + + /* Select single or multiple read based on number of blocks */ + if (num_blocks == 1) { + status = sdmmc_execute_command(CMD_READ_SINGLE, index, 0 | MCI_INT_DATA_OVER); + } + else { + status = sdmmc_execute_command(CMD_READ_MULTIPLE, index, 0 | MCI_INT_DATA_OVER); + } + + if (status != 0) { + cbRead = 0; + } + /*Wait for card program to finish*/ + while (Chip_SDMMC_GetState() != SDMMC_TRAN_ST) ; + + return cbRead; +} + +/* Performs write of data to the SD/MMC card */ +int32_t Chip_SDMMC_WriteBlocks(void *buffer, int32_t start_block, int32_t num_blocks) +{ + int32_t cbWrote = num_blocks * MMC_SECTOR_SIZE; + int32_t status; + int32_t index; + + /* if card is not acquired return immediately */ + if (( start_block < 0) || ( (start_block + num_blocks) > g_card_info->blocknr) ) { + return 0; + } + + /*Wait for card program to finish*/ + while (Chip_SDMMC_GetState() != SDMMC_TRAN_ST) ; + + /* put card in trans state */ + if (prv_set_trans_state() != 0) { + return 0; + } + + /* set number of bytes to write */ + LPC_SDMMC->BYTCNT = cbWrote; + + /* if high capacity card use block indexing */ + if (g_card_info->card_type & CARD_TYPE_HC) { + index = start_block; + } + else { /*fix at 512 bytes*/ + index = start_block << 9; // * g_card_info->block_len; + + } + IP_SDMMC_DmaSetup(LPC_SDMMC, &g_card_info->sdif_dev, (uint32_t) buffer, cbWrote); + + /* Select single or multiple write based on number of blocks */ + if (num_blocks == 1) { + status = sdmmc_execute_command(CMD_WRITE_SINGLE, index, 0 | MCI_INT_DATA_OVER); + } + else { + status = sdmmc_execute_command(CMD_WRITE_MULTIPLE, index, 0 | MCI_INT_DATA_OVER); + } + + /*Wait for card program to finish*/ + while (Chip_SDMMC_GetState() != SDMMC_TRAN_ST) ; + + if (status != 0) { + cbWrote = 0; + } + + return cbWrote; +} diff --git a/bsp/xplorer4330/libraries/lpc_chip/chip_18xx_43xx/sdmmc_18xx_43xx.h b/bsp/xplorer4330/libraries/lpc_chip/chip_18xx_43xx/sdmmc_18xx_43xx.h new file mode 100644 index 0000000000..6a71b55e15 --- /dev/null +++ b/bsp/xplorer4330/libraries/lpc_chip/chip_18xx_43xx/sdmmc_18xx_43xx.h @@ -0,0 +1,480 @@ +/* + * @brief LPC18xx/43xx SD/SDIO driver + * + * @note + * Copyright(C) NXP Semiconductors, 2012 + * All rights reserved. + * + * @par + * Software that is described herein is for illustrative purposes only + * which provides customers with programming information regarding the + * LPC products. This software is supplied "AS IS" without any warranties of + * any kind, and NXP Semiconductors and its licensor disclaim any and + * all warranties, express or implied, including all implied warranties of + * merchantability, fitness for a particular purpose and non-infringement of + * intellectual property rights. NXP Semiconductors assumes no responsibility + * or liability for the use of the software, conveys no license or rights under any + * patent, copyright, mask work right, or any other intellectual property rights in + * or to any products. NXP Semiconductors reserves the right to make changes + * in the software without notification. NXP Semiconductors also makes no + * representation or warranty that such application will be suitable for the + * specified use without further testing or modification. + * + * @par + * Permission to use, copy, modify, and distribute this software and its + * documentation is hereby granted, under NXP Semiconductors' and its + * licensor's relevant copyrights in the software, without fee, provided that it + * is used in conjunction with NXP Semiconductors microcontrollers. This + * copyright, permission, and disclaimer notice must appear in all copies of + * this code. + */ + +#ifndef __SDMMC_18XX_43XX_H_ +#define __SDMMC_18XX_43XX_H_ + +#include "chip.h" + +#ifdef __cplusplus +extern "C" { +#endif + +/** @defgroup SDMMC_18XX_43XX CHIP: LPC18xx/43xx SD/SDIO driver + * @ingroup CHIP_18XX_43XX_Drivers + * @{ + */ + +/* SD/MMC commands - this matrix shows the command, response types, and + supported card type for that command. + Command Number Resp SD MMC + ----------------------- ------ ----- --- --- + Reset (go idle) CMD0 NA x x + Send op condition CMD1 R3 x + All send CID CMD2 R2 x x + Send relative address CMD3 R1 x + Send relative address CMD3 R6 x + Program DSR CMD4 NA x + Select/deselect card CMD7 R1b x + Select/deselect card CMD7 R1 x + Send CSD CMD9 R2 x x + Send CID CMD10 R2 x x + Read data until stop CMD11 R1 x x + Stop transmission CMD12 R1/b x x + Send status CMD13 R1 x x + Go inactive state CMD15 NA x x + Set block length CMD16 R1 x x + Read single block CMD17 R1 x x + Read multiple blocks CMD18 R1 x x + Write data until stop CMD20 R1 x + Setblock count CMD23 R1 x + Write single block CMD24 R1 x x + Write multiple blocks CMD25 R1 x x + Program CID CMD26 R1 x + Program CSD CMD27 R1 x x + Set write protection CMD28 R1b x x + Clear write protection CMD29 R1b x x + Send write protection CMD30 R1 x x + Erase block start CMD32 R1 x + Erase block end CMD33 R1 x + Erase block start CMD35 R1 x + Erase block end CMD36 R1 x + Erase blocks CMD38 R1b x + Fast IO CMD39 R4 x + Go IRQ state CMD40 R5 x + Lock/unlock CMD42 R1b x + Application command CMD55 R1 x + General command CMD56 R1b x + + *** SD card application commands - these must be preceded with *** + *** MMC CMD55 application specific command first *** + Set bus width ACMD6 R1 x + Send SD status ACMD13 R1 x + Send number WR blocks ACMD22 R1 x + Set WR block erase cnt ACMD23 R1 x + Send op condition ACMD41 R3 x + Set clear card detect ACMD42 R1 x + Send CSR ACMD51 R1 x */ + +/** @brief SD/MMC command enumeration value. + */ +typedef enum { + SDMMC_IDLE, /*!< Put card in idle mode */ + MMC_SENDOP_COND, /*!< Send operating condition */ + SDMMC_ALL_SEND_CID, /*!< All cards send CID */ + SDMMC_SRA, /*!< Set relative address */ + MMC_PROGRAM_DSR, /*!< Program DSR */ + SDMMC_SELECT_CARD, /*!< Select card */ + SDMMC_SEND_CSD, /*!< Send CSD data */ + SDMMC_SEND_CID, /*!< Send CID register data (with rel. addr) */ + SDMMC_READ_UNTIL_STOP, /*!< Read data until stop */ + SDMMC_STOP_XFER, /*!< Stop current transmission */ + SDMMC_SSTAT, /*!< Send status */ + SDMMC_INACTIVE, /*!< Put card in inactive state */ + SDMMC_SET_BLEN, /*!< Set block transfer length */ + SDMMC_READ_SINGLE, /*!< Read single block */ + SDMMC_READ_MULTIPLE, /*!< Read multiple blocks */ + SDMMC_WRITE_UNTIL_STOP, /*!< Write data until stop */ + SDMMC_SET_BLOCK_COUNT, /*!< Set block count */ + SDMMC_WRITE_SINGLE, /*!< Write single block */ + SDMMC_WRITE_MULTIPLE, /*!< Write multiple blocks */ + MMC_PROGRAM_CID, /*!< Program CID */ + SDMMC_PROGRAM_CSD, /*!< Program CSD */ + SDMMC_SET_WR_PROT, /*!< Set write protection */ + SDMMC_CLEAR_WR_PROT, /*!< Clear write protection */ + SDMMC_SEND_WR_PROT, /*!< Send write protection */ + SD_ERASE_BLOCK_START, /*!< Set starting erase block */ + SD_ERASE_BLOCK_END, /*!< Set ending erase block */ + MMC_ERASE_BLOCK_START, /*!< Set starting erase block */ + MMC_ERASE_BLOCK_END, /*!< Set ending erase block */ + MMC_ERASE_BLOCKS, /*!< Erase blocks */ + MMC_FAST_IO, /*!< Fast IO */ + MMC_GO_IRQ_STATE, /*!< Go into IRQ state */ + MMC_LOCK_UNLOCK, /*!< Lock/unlock */ + SDMMC_APP_CMD, /*!< Application specific command */ + SDMMC_GEN_CMD, /*!< General purpose command */ + SDMMC_INVALID_CMD /*!< Invalid SDMMC command */ +} SDMMC_COMMAND_T; + +/** @brief SDMMC application specific commands for SD cards only - these + must be preceded by the SDMMC CMD55 to work correctly. + */ +typedef enum { + SD_SET_BUS_WIDTH, /*!< Set the SD bus width */ + SD_SEND_STATUS, /*!< Send the SD card status */ + SD_SEND_WR_BLOCKS, /*!< Send the number of written clocks */ + SD_SET_ERASE_COUNT, /*!< Set the number of blocks to pre-erase */ + SD_SENDOP_COND, /*!< Send the OCR register (init) */ + SD_CLEAR_CARD_DET, /*!< Set or clear the 50K detect pullup */ + SD_SEND_SCR, /*!< Send the SD configuration register */ + SD_INVALID_APP_CMD /*!< Invalid SD application command */ +} SD_APP_CMD_T; + +/** @brief Possible SDMMC response types + */ +typedef enum { + SDMMC_RESPONSE_R1, /*!< Typical status */ + SDMMC_RESPONSE_R1B, /*!< Typical status with busy */ + SDMMC_RESPONSE_R2, /*!< CID/CSD registers (CMD2 and CMD10) */ + SDMMC_RESPONSE_R3, /*!< OCR register (CMD1, ACMD41) */ + SDMMC_RESPONSE_R4, /*!< Fast IO response word */ + SDMMC_RESPONSE_R5, /*!< Go IRQ state response word */ + SDMMC_RESPONSE_R6, /*!< Published RCA response */ + SDMMC_RESPONSE_NONE /*!< No response expected */ +} SDMMC_RESPONSE_T; + +/** @brief Possible SDMMC card state types + */ +typedef enum { + SDMMC_IDLE_ST = 0, /*!< Idle state */ + SDMMC_READY_ST, /*!< Ready state */ + SDMMC_IDENT_ST, /*!< Identification State */ + SDMMC_STBY_ST, /*!< standby state */ + SDMMC_TRAN_ST, /*!< transfer state */ + SDMMC_DATA_ST, /*!< Sending-data State */ + SDMMC_RCV_ST, /*!< Receive-data State */ + SDMMC_PRG_ST, /*!< Programming State */ + SDMMC_DIS_ST /*!< Disconnect State */ +} SDMMC_STATE_T; + +/* Standard MMC commands (3.1) type argument response */ +/* class 1 */ +#define MMC_GO_IDLE_STATE 0 /* bc */ +#define MMC_SEND_OP_COND 1 /* bcr [31:0] OCR R3 */ +#define MMC_ALL_SEND_CID 2 /* bcr R2 */ +#define MMC_SET_RELATIVE_ADDR 3 /* ac [31:16] RCA R1 */ +#define MMC_SET_DSR 4 /* bc [31:16] RCA */ +#define MMC_SELECT_CARD 7 /* ac [31:16] RCA R1 */ +#define MMC_SEND_EXT_CSD 8 /* bc R1 */ +#define MMC_SEND_CSD 9 /* ac [31:16] RCA R2 */ +#define MMC_SEND_CID 10 /* ac [31:16] RCA R2 */ +#define MMC_STOP_TRANSMISSION 12 /* ac R1b */ +#define MMC_SEND_STATUS 13 /* ac [31:16] RCA R1 */ +#define MMC_GO_INACTIVE_STATE 15 /* ac [31:16] RCA */ + +/* class 2 */ +#define MMC_SET_BLOCKLEN 16 /* ac [31:0] block len R1 */ +#define MMC_READ_SINGLE_BLOCK 17 /* adtc [31:0] data addr R1 */ +#define MMC_READ_MULTIPLE_BLOCK 18 /* adtc [31:0] data addr R1 */ + +/* class 3 */ +#define MMC_WRITE_DAT_UNTIL_STOP 20 /* adtc [31:0] data addr R1 */ + +/* class 4 */ +#define MMC_SET_BLOCK_COUNT 23 /* adtc [31:0] data addr R1 */ +#define MMC_WRITE_BLOCK 24 /* adtc [31:0] data addr R1 */ +#define MMC_WRITE_MULTIPLE_BLOCK 25 /* adtc R1 */ +#define MMC_PROGRAM_CID 26 /* adtc R1 */ +#define MMC_PROGRAM_CSD 27 /* adtc R1 */ + +/* class 6 */ +#define MMC_SET_WRITE_PROT 28 /* ac [31:0] data addr R1b */ +#define MMC_CLR_WRITE_PROT 29 /* ac [31:0] data addr R1b */ +#define MMC_SEND_WRITE_PROT 30 /* adtc [31:0] wpdata addr R1 */ + +/* class 5 */ +#define MMC_ERASE_GROUP_START 35 /* ac [31:0] data addr R1 */ +#define MMC_ERASE_GROUP_END 36 /* ac [31:0] data addr R1 */ +#define MMC_ERASE 37 /* ac R1b */ + +/* class 9 */ +#define MMC_FAST_IO 39 /* ac R4 */ +#define MMC_GO_IRQ_STATE 40 /* bcr R5 */ + +/* class 7 */ +#define MMC_LOCK_UNLOCK 42 /* adtc R1b */ + +/* class 8 */ +#define MMC_APP_CMD 55 /* ac [31:16] RCA R1 */ +#define MMC_GEN_CMD 56 /* adtc [0] RD/WR R1b */ + +/* SD commands type argument response */ +/* class 8 */ +/* This is basically the same command as for MMC with some quirks. */ +#define SD_SEND_RELATIVE_ADDR 3 /* ac R6 */ +#define SD_CMD8 8 /* bcr [31:0] OCR R3 */ + +/* Application commands */ +#define SD_APP_SET_BUS_WIDTH 6 /* ac [1:0] bus width R1 */ +#define SD_APP_OP_COND 41 /* bcr [31:0] OCR R1 (R4) */ +#define SD_APP_SEND_SCR 51 /* adtc R1 */ + +/* + MMC status in R1 + Type + e : error bit + s : status bit + r : detected and set for the actual command response + x : detected and set during command execution. the host must poll + the card by sending status command in order to read these bits. + Clear condition + a : according to the card state + b : always related to the previous command. Reception of + a valid command will clear it (with a delay of one command) + c : clear by read + */ + +#define R1_OUT_OF_RANGE (1UL << 31) /* er, c */ +#define R1_ADDRESS_ERROR (1 << 30) /* erx, c */ +#define R1_BLOCK_LEN_ERROR (1 << 29) /* er, c */ +#define R1_ERASE_SEQ_ERROR (1 << 28) /* er, c */ +#define R1_ERASE_PARAM (1 << 27) /* ex, c */ +#define R1_WP_VIOLATION (1 << 26) /* erx, c */ +#define R1_CARD_IS_LOCKED (1 << 25) /* sx, a */ +#define R1_LOCK_UNLOCK_FAILED (1 << 24) /* erx, c */ +#define R1_COM_CRC_ERROR (1 << 23) /* er, b */ +#define R1_ILLEGAL_COMMAND (1 << 22) /* er, b */ +#define R1_CARD_ECC_FAILED (1 << 21) /* ex, c */ +#define R1_CC_ERROR (1 << 20) /* erx, c */ +#define R1_ERROR (1 << 19) /* erx, c */ +#define R1_UNDERRUN (1 << 18) /* ex, c */ +#define R1_OVERRUN (1 << 17) /* ex, c */ +#define R1_CID_CSD_OVERWRITE (1 << 16) /* erx, c, CID/CSD overwrite */ +#define R1_WP_ERASE_SKIP (1 << 15) /* sx, c */ +#define R1_CARD_ECC_DISABLED (1 << 14) /* sx, a */ +#define R1_ERASE_RESET (1 << 13) /* sr, c */ +#define R1_STATUS(x) (x & 0xFFFFE000) +#define R1_CURRENT_STATE(x) ((x & 0x00001E00) >> 9) /* sx, b (4 bits) */ +#define R1_READY_FOR_DATA (1 << 8)/* sx, a */ +#define R1_APP_CMD (1 << 5)/* sr, c */ + +#define OCR_ALL_READY (1UL << 31) /* Card Power up status bit */ +#define OCR_HC_CCS (1 << 30) /* High capacity card */ +#define OCR_VOLTAGE_RANGE_MSK 0x00ff8000 + +#define SD_SEND_IF_ARG 0x000001AA +#define SD_SEND_IF_ECHO_MSK 0x000000FF +#define SD_SEND_IF_RESP 0x000000AA + +#define CMD_MASK_RESP (0x3UL << 28) +#define CMD_RESP(r) (((r) & 0x3) << 28) +#define CMD_RESP_R0 (0 << 28) +#define CMD_RESP_R1 (1 << 28) +#define CMD_RESP_R2 (2 << 28) +#define CMD_RESP_R3 (3 << 28) +#define CMD_BIT_AUTO_STOP (1 << 24) +#define CMD_BIT_APP (1 << 23) +#define CMD_BIT_INIT (1 << 22) +#define CMD_BIT_BUSY (1 << 21) +#define CMD_BIT_LS (1 << 20) /* Low speed, used during acquire */ +#define CMD_BIT_DATA (1 << 19) +#define CMD_BIT_WRITE (1 << 18) +#define CMD_BIT_STREAM (1 << 17) +#define CMD_MASK_CMD (0xff) +#define CMD_SHIFT_CMD (0) + +#define CMD(c, r) ( ((c) & CMD_MASK_CMD) | CMD_RESP((r)) ) + +#define CMD_IDLE CMD(MMC_GO_IDLE_STATE, 0) | CMD_BIT_LS | CMD_BIT_INIT +#define CMD_SD_OP_COND CMD(SD_APP_OP_COND, 1) | CMD_BIT_LS | CMD_BIT_APP +#define CMD_SD_SEND_IF_COND CMD(SD_CMD8, 1) | CMD_BIT_LS +#define CMD_MMC_OP_COND CMD(MMC_SEND_OP_COND, 3) | CMD_BIT_LS | CMD_BIT_INIT +#define CMD_ALL_SEND_CID CMD(MMC_ALL_SEND_CID, 2) | CMD_BIT_LS +#define CMD_MMC_SET_RCA CMD(MMC_SET_RELATIVE_ADDR, 1) | CMD_BIT_LS +#define CMD_SD_SEND_RCA CMD(SD_SEND_RELATIVE_ADDR, 1) | CMD_BIT_LS +#define CMD_SEND_CSD CMD(MMC_SEND_CSD, 2) | CMD_BIT_LS +#define CMD_SEND_EXT_CSD CMD(MMC_SEND_EXT_CSD, 1) | CMD_BIT_LS | CMD_BIT_DATA +#define CMD_DESELECT_CARD CMD(MMC_SELECT_CARD, 0) +#define CMD_SELECT_CARD CMD(MMC_SELECT_CARD, 1) +#define CMD_SET_BLOCKLEN CMD(MMC_SET_BLOCKLEN, 1) +#define CMD_SEND_STATUS CMD(MMC_SEND_STATUS, 1) +#define CMD_READ_SINGLE CMD(MMC_READ_SINGLE_BLOCK, 1) | CMD_BIT_DATA +#define CMD_READ_MULTIPLE CMD(MMC_READ_MULTIPLE_BLOCK, 1) | CMD_BIT_DATA | CMD_BIT_AUTO_STOP +#define CMD_SD_SET_WIDTH CMD(SD_APP_SET_BUS_WIDTH, 1) | CMD_BIT_APP +#define CMD_STOP CMD(MMC_STOP_TRANSMISSION, 1) | CMD_BIT_BUSY +#define CMD_WRITE_SINGLE CMD(MMC_WRITE_BLOCK, 1) | CMD_BIT_DATA | CMD_BIT_WRITE +#define CMD_WRITE_MULTIPLE CMD(MMC_WRITE_MULTIPLE_BLOCK, 1) | CMD_BIT_DATA | CMD_BIT_WRITE | CMD_BIT_AUTO_STOP + +/** @brief card type defines + */ +#define CARD_TYPE_SD (1 << 0) +#define CARD_TYPE_4BIT (1 << 1) +#define CARD_TYPE_8BIT (1 << 2) +#define CARD_TYPE_HC (OCR_HC_CCS)/*!< high capacity card > 2GB */ + +#define MMC_SECTOR_SIZE 512 + +/** @brief Setup options for the SDIO driver + */ +#define US_TIMEOUT 1000000 /*!< give 1 atleast 1 sec for the card to respond */ +#define MS_ACQUIRE_DELAY (10) /*!< inter-command acquire oper condition delay in msec*/ +#define INIT_OP_RETRIES 50 /*!< initial OP_COND retries */ +#define SET_OP_RETRIES 1000 /*!< set OP_COND retries */ +#define SDIO_BUS_WIDTH 4 /*!< Max bus width supported */ +#define SD_MMC_ENUM_CLOCK 400000 /*!< Typical enumeration clock rate */ +#define MMC_MAX_CLOCK 20000000 /*!< Max MMC clock rate */ +#define MMC_LOW_BUS_MAX_CLOCK 26000000 /*!< Type 0 MMC card max clock rate */ +#define MMC_HIGH_BUS_MAX_CLOCK 52000000 /*!< Type 1 MMC card max clock rate */ +#define SD_MAX_CLOCK 25000000 /*!< Max SD clock rate */ + +/* Function prototype for event setup function */ +typedef void (*MCI_EVSETUP_FUNC_T)(uint32_t); + +/* Function prototype for wait (for IRQ) function */ +typedef uint32_t (*MCI_WAIT_CB_FUNC_T)(void); + +/* Function prototype for milliSecond delay function */ +typedef void (*MCI_MSDELAY_FUNC_T)(uint32_t); + +/* Card specific setup data */ +typedef struct _mci_card_struct { + uint32_t response[4]; /*!< Most recent response */ + uint32_t cid[4]; /*!< CID of acquired card */ + uint32_t csd[4]; /*!< CSD of acquired card */ + uint32_t ext_csd[512 / 4]; + uint32_t card_type; + uint32_t rca; /*!< Relative address assigned to card */ + uint32_t speed; + uint32_t block_len; /*!< Card sector size*/ + uint32_t device_size; + uint32_t blocknr; + uint32_t clk_rate; + sdif_device sdif_dev; + MCI_EVSETUP_FUNC_T evsetup_cb; + MCI_WAIT_CB_FUNC_T waitfunc_cb; + MCI_MSDELAY_FUNC_T msdelay_func; +} mci_card_struct; + +/** + * @brief Detect if an SD card is inserted + * @return Returns 0 if a card is detected, otherwise 1 + * Detect if an SD card is inserted + * (uses SD_CD pin, returns 0 on card detect) + */ +STATIC INLINE int32_t Chip_SDMMC_CardNDetect(void) +{ + return IP_SDMMC_CardNDetect(LPC_SDMMC); +} + +/** + * @brief Detect if write protect is enabled + * @return Returns 1 if card is write protected, otherwise 0 + * Detect if write protect is enabled + * (uses SD_WP pin, returns 1 if card is write protected) + */ +STATIC INLINE int32_t Chip_CardWpOn(void) +{ + return IP_SDMMC_CardWpOn(LPC_SDMMC); +} + +/** + * @brief Initializes the MCI card controller + * @return None + */ +STATIC INLINE void Chip_SDMMC_Init(void) +{ + IP_SDMMC_Init(LPC_SDMMC); +} + +/** + * @brief Enable or disable slot power + * @param enable : !0 to enable, or 0 to disable + * @return None + * Enable or disable slot power, !0 = enable slot power + * (Uses SD_POW pin, set to high or low based on enable parameter state) + */ +STATIC INLINE void Chip_SDMMC_PowerOnOff(int32_t enable) +{ + IP_SDMMC_PowerOnOff(LPC_SDMMC, enable); +} + +/** + * @brief Sets the SD interface interrupt mask + * @param iVal : Interrupts to enable, Or'ed values MCI_INT_* + * @return None + */ +STATIC INLINE void Chip_SDMMC_SetIntMask(uint32_t iVal) +{ + IP_SDMMC_SetIntMask(LPC_SDMMC, iVal); +} + +/** + * @brief Returns the current SD status, clears pending ints, and disables all ints + * @return Current pending interrupt status of Or'ed values MCI_INT_* + */ +uint32_t Chip_SDMMC_GetIntStatus(void); + +/** + * @brief Get card's current state (idle, transfer, program, etc.) + * @return Current SD card transfer state + */ +int32_t Chip_SDMMC_GetState(void); + +/** + * @brief Function to enumerate the SD/MMC/SDHC/MMC+ cards + * @param pcardinfo : Pointer to pre-allocated card info structure + * @return 1 if a card is acquired, otherwise 0 + */ +uint32_t Chip_SDMMC_Acquire(mci_card_struct *pcardinfo); + +/** + * @brief Get the device size of SD/MMC card (after enumeration) + * @return Card size (capacity) + */ +int32_t Chip_SDMMC_GetDeviceSize(void); + +/** + * @brief Performs the read of data from the SD/MMC card + * @param buffer : Pointer to data buffer to copy to + * @param start_block : Start block number + * @param num_blocks : Number of block to read + * @return Bytes read, or 0 on error + */ +int32_t Chip_SDMMC_ReadBlocks(void *buffer, int32_t start_block, int32_t num_blocks); + +/** + * @brief Performs write of data to the SD/MMC card + * @param buffer : Pointer to data buffer to copy to + * @param start_block : Start block number + * @param num_blocks : Number of block to write + * @return Number of bytes actually written, or 0 on error + */ +int32_t Chip_SDMMC_WriteBlocks(void *buffer, int32_t start_block, int32_t num_blocks); + +/** + * @} + */ + +#ifdef __cplusplus +} +#endif + +#endif /* __SDMMC_18XX_43XX_H_ */ diff --git a/bsp/xplorer4330/libraries/lpc_chip/chip_18xx_43xx/spifi_rom_api.h b/bsp/xplorer4330/libraries/lpc_chip/chip_18xx_43xx/spifi_rom_api.h new file mode 100644 index 0000000000..c620feae80 --- /dev/null +++ b/bsp/xplorer4330/libraries/lpc_chip/chip_18xx_43xx/spifi_rom_api.h @@ -0,0 +1,356 @@ +/* + * @brief SPIFI ROM driver functions + * + * @note + * Copyright(C) NXP Semiconductors, 2012 + * All rights reserved. + * + * @par + * Software that is described herein is for illustrative purposes only + * which provides customers with programming information regarding the + * LPC products. This software is supplied "AS IS" without any warranties of + * any kind, and NXP Semiconductors and its licensor disclaim any and + * all warranties, express or implied, including all implied warranties of + * merchantability, fitness for a particular purpose and non-infringement of + * intellectual property rights. NXP Semiconductors assumes no responsibility + * or liability for the use of the software, conveys no license or rights under any + * patent, copyright, mask work right, or any other intellectual property rights in + * or to any products. NXP Semiconductors reserves the right to make changes + * in the software without notification. NXP Semiconductors also makes no + * representation or warranty that such application will be suitable for the + * specified use without further testing or modification. + * + * @par + * Permission to use, copy, modify, and distribute this software and its + * documentation is hereby granted, under NXP Semiconductors' and its + * licensor's relevant copyrights in the software, without fee, provided that it + * is used in conjunction with NXP Semiconductors microcontrollers. This + * copyright, permission, and disclaimer notice must appear in all copies of + * this code. + */ + +#ifndef __SPIFI_ROM_API_H_ +#define __SPIFI_ROM_API_H_ + +#include "chip.h" +#include + +#ifdef __cplusplus +extern "C" { +#endif + +/* define the symbol TESTING in the environment if test output desired */ + +/** @ingroup IP_SPIFI_001 + * @{ + */ + +/* maintain LONGEST_PROT >= the length (in bytes) of the largest + protection block of any serial flash that this driver handles */ +#define LONGEST_PROT 68 + +typedef uint8_t uc; + +#ifndef NULL +#define NULL ((void *) 0) +#endif + +/** Protection/sector descriptors */ +typedef struct { + uint32_t base; + uc flags; + int8_t log2; + uint16_t rept; +} protEnt; +/* bits in the flags byte */ +enum {RWPROT = 1}; + +#if 0 + +/* overall data structure includes # sectors, length of protection reg, + array of descriptors */ +typedef struct { + uint16_t sectors; + uint16_t protBytes; + protEnt *entries; +} protDesc; +#endif + +typedef union { + uint16_t hw; + uc byte[2]; +} stat_t; +/** The object that spifi_init returns, and other routines use as an operand */ +typedef struct { + uint32_t base, regbase, devSize, memSize; + uc mfger, devType, devID, busy; + stat_t stat; + uint16_t reserved; + uint16_t set_prot, write_prot; + uint32_t mem_cmd, prog_cmd; + uint16_t sectors, protBytes; + uint32_t opts, errCheck; + uc erase_shifts[4], erase_ops[4]; + protEnt *protEnts; + char prot[LONGEST_PROT]; +} SPIFIobj; + +/** operands of program and erase */ +typedef struct { + char *dest; + uint32_t length; + char *scratch; + int32_t protect; + uint32_t options; +} SPIFIopers; + +/** instruction classes for wait_busy */ +typedef enum {stat_inst, block_erase, prog_inst, chip_erase} inst_type; + +/** @defgroup IP_SPIFI_OPTIONS IP: SPIFI configuration options + * @ingroup IP_SPIFI_001 + * Options used to configure SPIFI + * @{ + */ + +/** The SCL output is high when a frame/command is not in progress. + Note that S_MODE3+S_FULLCLK+S_RCVCLK will not work. Use S_MODE0 + or S_INTCLK. */ +#define S_MODE3 1 + +/** SCL is low when a frame/command is not in progress. (default) */ +#define S_MODE0 0 + +/** SPI mode and the slowest, most basic/compatible read operation will be used. */ +#define S_MINIMAL 2 + +/** The fastest read operation provided by the device will be used. (default) */ +#define S_MAXIMAL 0 + +/** Data is sampled using the SCL clock fed back from the pin. This allows + more time for the serial flash to present each bit or group of bits, + but when used with S_FULLCLK can endanger hold time for data from the + flash. */ +#define S_RCVCLK 0x80 + +/** Data is sampled using the internal clock from which the SCL pin is driven. (default) */ +#define S_INTCLK 0 + +/** Data from the serial flash is sampled on falling edges on the SCL + output, allowing a full clock period for the serial flash to present + each bit or group of bits. */ +#define S_FULLCLK 0x40 + +/** Data from the serial flash is sampled on rising edges of the SCL + output, as in classic SPI applications. Suitable for slower clock rates. (default) */ +#define S_HALFCLK 0 + +/** If the connected device can operate in dual mode (2 bits per clock), + dual mode will be used, else SPI mode. */ +#define S_DUAL 0x100 + +/** + * @} + */ + +/** @defgroup IP_SPIFI_OPTIONS_PROGRAM IP: SPIFI programming options + * @ingroup IP_SPIFI_001 + * Options used to configure SPIFI programming + * @{ + */ + +/** All sectors in dest to dest+length will be erased */ +#define S_FORCE_ERASE 4 + +/** Erasing is handled by the caller not by the driver */ +#define S_ERASE_NOT_REQD 8 + +/** Erasing is handled by the caller not by the driver */ +#define S_CALLER_ERASE 8 + +/** Erasing is done when necessary. (default) */ +#define S_ERASE_AS_REQD 0 + +/** Data will be read back and checked after programming. */ +#define S_VERIFY_PROG 0x10 + +/** Sectors will be read back and checked for 0xFF after erasing. */ +#define S_VERIFY_ERASE 0x20 + +/** No reading or checking will be done. (default) */ +#define S_NO_VERIFY 0 + +/** Write protection is handled by the caller not by the driver. */ +#define S_CALLER_PROT 0x200 + +/** The driver removes protection before the operation, and sets it as specified thereafter. (default) */ +#define S_DRIVER_PROT 0 + +/** + * @} + */ + +/* the following values in the first post-address memory command byte work + for all known quad devices that support "no opcode" operation */ +#define NO_OPCODE_FOLLOWS 0xA5 +#define OPCODE_FOLLOWS 0xFF + +/* basic SPI commands for serial flash */ +#define BASE_READ_CMD (CMD_RD << OPCODE_SHIFT | 4 << FRAMEFORM_SHIFT | UNL_DATA) +#define FAST_READ_CMD (CMD_READ_FAST << OPCODE_SHIFT | 4 << FRAMEFORM_SHIFT | 1 << INTLEN_SHIFT | UNL_DATA) +#define BASE_PROG_CMD (CMD_PROG << OPCODE_SHIFT | 4 << FRAMEFORM_SHIFT | DOUT) + +/* the length of a standard program command is 256 on all devices */ +#define PROG_SIZE 256 + +/* options in obj->opts (mostly for setMulti) */ +/* used by Winbond: send 0xA3 command so hardware can read faster */ +#define OPT_SEND_A3 1 +/* used by SST: send 0x38 command to enable quad and allow full command set */ +#define OPT_SEND_38 2 +/* used by Winbond and others: read status reg 2, check it, + if necessary write it back with Quad Enable set */ +#define OPT_35_OR02_01 4 +/* used by Atmel: read Configuration register, if necessary set Quad Enable */ +#define OPT_3F_OR80_3E 8 +/* used by Numonyx to set all-quad mode: only for parts that include RSTQIO */ +#define OPT_65_CLR_C0_61 0x10 +/* used by Numonyx: send 0x81 command to write Volatile Configuration Register + to set # dummy bytes and allow XIP mode */ +#define OPT_81 0x20 +/* set for devices without full device erase command (Numonyx type 0x40) */ +#define OPT_NO_DEV_ERASE 0x40 +/* used by Macronix: status reg 2 includes selection between write-protect + in status reg and command-based */ +#define OPT_WPSEL 0x80 +/* set when protection data has been read into the SPIFI object */ +#define OPT_PROT_READ 0x100 +/* set if device needs 4-byte address (and maybe 0x4B command = use 4-byte address) */ +#define OPT_4BAD 0x200 +/* set if setMulti should set the Dual bit in Control reg */ +#define OPT_DUAL 0x400 +/* send "# dummy bits" in C0 command to Winbond */ +#define OPT_C0 0x800 +/* set QE for Chingis */ +#define OPT_05_OR40_01 0x1000 +/* write status does not go busy */ +#define OPT_01_NO_BUSY 0x2000 +/* protection mode bits moved from protMode byte to opts Fri May 13 2011 */ +#define OPT_PROT_STAT 0x4000 +#define OPT_PROT_REG 0x8000 +#define OPT_PROT_CMD3 0x10000 +#define OPT_PROT_CMDE 0x20000 +#define OPT_PROT_MASK 0x3C000 + +#define OPT_ALL_QUAD 0x40000 + +#ifndef OMIT_ROM_TABLE +/* interface to ROM API */ +typedef struct { + int32_t (*spifi_init)(SPIFIobj *obj, uint32_t csHigh, uint32_t options, + uint32_t mhz); + int32_t (*spifi_program)(SPIFIobj *obj, char *source, SPIFIopers *opers); + int32_t (*spifi_erase)(SPIFIobj *obj, SPIFIopers *opers); + /* mode switching */ + void (*cancel_mem_mode)(SPIFIobj *obj); + void (*set_mem_mode)(SPIFIobj *obj); + + /* mid level functions */ + int32_t (*checkAd)(SPIFIobj *obj, SPIFIopers *opers); + int32_t (*setProt)(SPIFIobj *obj, SPIFIopers *opers, char *change, + char *saveProt); + int32_t (*check_block)(SPIFIobj *obj, char *source, SPIFIopers *opers, + uint32_t check_program); + int32_t (*send_erase_cmd)(SPIFIobj *obj, uint8_t op, uint32_t addr); + uint32_t (*ck_erase)(SPIFIobj *obj, uint32_t *addr, uint32_t length); + int32_t (*prog_block)(SPIFIobj *obj, char *source, SPIFIopers *opers, + uint32_t *left_in_page); + uint32_t (*ck_prog)(SPIFIobj *obj, char *source, char *dest, uint32_t length); + + /* low level functions */ + void (*setSize)(SPIFIobj *obj, int32_t value); + int32_t (*setDev)(SPIFIobj *obj, uint32_t opts, uint32_t mem_cmd, + uint32_t prog_cmd); + uint32_t (*cmd)(uc op, uc addrLen, uc intLen, uint16_t len); + uint32_t (*readAd)(SPIFIobj *obj, uint32_t cmd, uint32_t addr); + void (*send04)(SPIFIobj *obj, uc op, uc len, uint32_t value); + void (*wren_sendAd)(SPIFIobj *obj, uint32_t cmd, uint32_t addr, uint32_t value); + int32_t (*write_stat)(SPIFIobj *obj, uc len, uint16_t value); + int32_t (*wait_busy)(SPIFIobj *obj, uc prog_or_erase); +} SPIFI_RTNS; + +#define SPIFI_ROM_PTR 0x10400118 + +#define define_spifi_romPtr(name) const SPIFI_RTNS * name = *((SPIFI_RTNS * *) SPIFI_ROM_PTR) +#endif /* OMIT_ROM_TABLE */ + +#ifdef USE_SPIFI_LIB +extern SPIFI_RTNS spifi_table; +#endif /* USE_SPIFI_LIB */ + +/* example of using this interface: + #include "spifi_rom_api.h" + #define CSHIGH 4 + #define SPIFI_MHZ 80 + #define source_data_ad (char *)1234 + + int32_t rc; + SPIFIopers opers; + + define_spifi_romPtr(spifi); + SPIFIobj *obj = malloc(sizeof(SPIFIobj)); + if (!obj) { can't allocate memory } + + rc = spifi->spifi_init (obj, CSHIGH, S_FULLCLK+S_RCVCLK, SPIFI_MHZ); + if (rc) { investigate init error rc } + printf ("the serial flash contains %d bytes\n", obj->devSize); + + opers.dest = where_to_program; + opers.length = how_many_bytes; + opers.scratch = NULL; // unprogrammed data is not saved/restored + opers.protect = -1; // save & restore protection + opers.options = S_VERIFY_PROG; + + rc = spifi->spifi_program (obj, source_data_ad, &opers); + if (rc) { investigate program error rc } + */ + +/* these are for normal users, including boot code */ +int32_t spifi_init (SPIFIobj *obj, uint32_t csHigh, uint32_t options, uint32_t mhz); + +int32_t spifi_program (SPIFIobj *obj, char *source, SPIFIopers *opers); + +int32_t spifi_erase (SPIFIobj *obj, SPIFIopers *opers); + +/* these are used by the manufacturer-specific init functions */ +void setSize (SPIFIobj *obj, int32_t value); + +int32_t setDev (SPIFIobj *obj, uint32_t opts, uint32_t mem_cmd, uint32_t prog_cmd); + +uint32_t read04(SPIFIobj *obj, uc op, uc len); + +int32_t write_stat (SPIFIobj *obj, uc len, uint16_t value); + +void setProtEnts(SPIFIobj *obj, const protEnt *p, uint32_t protTabLen); + +/* needs to be defined for each platform */ +void pullMISO(int high); + +#ifdef TESTING +/* used by testing code */ +unsigned short getProtBytes (SPIFIobj *obj, unsigned short *sectors); + +/* predeclare a debug routine */ +void wait_sample (volatile unsigned *addr, unsigned mask, unsigned value); + +#endif + +/** + * @} + */ + + #ifdef __cplusplus +} +#endif + +#endif /* __SPIFI_ROM_API_H_ */ diff --git a/bsp/xplorer4330/libraries/lpc_chip/chip_18xx_43xx/ssp_18xx_43xx.c b/bsp/xplorer4330/libraries/lpc_chip/chip_18xx_43xx/ssp_18xx_43xx.c new file mode 100644 index 0000000000..b872389532 --- /dev/null +++ b/bsp/xplorer4330/libraries/lpc_chip/chip_18xx_43xx/ssp_18xx_43xx.c @@ -0,0 +1,434 @@ +/* + * @brief LPC18xx/43xx SSP driver + * + * @note + * Copyright(C) NXP Semiconductors, 2012 + * All rights reserved. + * + * @par + * Software that is described herein is for illustrative purposes only + * which provides customers with programming information regarding the + * LPC products. This software is supplied "AS IS" without any warranties of + * any kind, and NXP Semiconductors and its licensor disclaim any and + * all warranties, express or implied, including all implied warranties of + * merchantability, fitness for a particular purpose and non-infringement of + * intellectual property rights. NXP Semiconductors assumes no responsibility + * or liability for the use of the software, conveys no license or rights under any + * patent, copyright, mask work right, or any other intellectual property rights in + * or to any products. NXP Semiconductors reserves the right to make changes + * in the software without notification. NXP Semiconductors also makes no + * representation or warranty that such application will be suitable for the + * specified use without further testing or modification. + * + * @par + * Permission to use, copy, modify, and distribute this software and its + * documentation is hereby granted, under NXP Semiconductors' and its + * licensor's relevant copyrights in the software, without fee, provided that it + * is used in conjunction with NXP Semiconductors microcontrollers. This + * copyright, permission, and disclaimer notice must appear in all copies of + * this code. + */ + +#include "ssp_18xx_43xx.h" + +/***************************************************************************** + * Private types/enumerations/variables + ****************************************************************************/ +/** SSP macro: write 2 bytes to FIFO buffer */ +#define SSP_Write2BFifo(pSSP, \ + xf_setup) if (xf_setup->tx_data) {IP_SSP_SendFrame(pSSP, \ + (*(uint16_t *) ((uint32_t) xf_setup->tx_data \ + + xf_setup->tx_cnt))); } \ + else {IP_SSP_SendFrame(pSSP, 0xFFFF); } \ + xf_setup->tx_cnt += 2; + +/** SSP macro: write 1 bytes to FIFO buffer */ +#define SSP_Write1BFifo(pSSP, \ + xf_setup) if (xf_setup->tx_data) {IP_SSP_SendFrame(pSSP, \ + (*(uint8_t *) ((uint32_t) xf_setup->tx_data \ + + xf_setup->tx_cnt))); } \ + else {IP_SSP_SendFrame(pSSP, 0xFF); } \ + xf_setup->tx_cnt++; + +/** SSP macro: read 1 bytes from FIFO buffer */ +#define SSP_Read2BFifo(pSSP, xf_setup, \ + rDat) while (IP_SSP_GetStatus(pSSP, \ + SSP_STAT_RNE) == SET && xf_setup->rx_cnt < xf_setup->length) { \ + rDat = IP_SSP_ReceiveFrame(pSSP); \ + if (xf_setup->rx_data) { \ + *(uint16_t *) ((uint32_t) xf_setup->rx_data + xf_setup->rx_cnt) = rDat; \ + } \ + xf_setup->rx_cnt += 2; \ +} + +/** SSP macro: read 2 bytes from FIFO buffer */ +#define SSP_Read1BFifo(pSSP, xf_setup, \ + rDat) while (IP_SSP_GetStatus(pSSP, \ + SSP_STAT_RNE) == SET && xf_setup->rx_cnt < xf_setup->length) { \ + rDat = IP_SSP_ReceiveFrame(pSSP); \ + if (xf_setup->rx_data) { \ + *(uint8_t *) ((uint32_t) xf_setup->rx_data + xf_setup->rx_cnt) = rDat; \ + } \ + xf_setup->rx_cnt++; \ +} + +/***************************************************************************** + * Public types/enumerations/variables + ****************************************************************************/ + +/***************************************************************************** + * Private functions + ****************************************************************************/ + +/***************************************************************************** + * Public functions + ****************************************************************************/ + +/* SSP Polling Read/Write in blocking mode */ +uint32_t Chip_SSP_RWFrames_Blocking(LPC_SSP_Type *pSSP, Chip_SSP_DATA_SETUP_Type *xf_setup) +{ + uint16_t rDat; + + /* Clear all remaining frames in RX FIFO */ + while (IP_SSP_GetStatus(pSSP, SSP_STAT_RNE)) { + IP_SSP_ReceiveFrame(pSSP); + } + + /* Clear status */ + IP_SSP_ClearIntPending(pSSP, SSP_INT_CLEAR_BITMASK); + + if (IP_SSP_GetDataSize(pSSP) > SSP_BITS_8) { + while (xf_setup->rx_cnt < xf_setup->length || xf_setup->tx_cnt < xf_setup->length) { + /* write data to buffer */ + if (( IP_SSP_GetStatus(pSSP, SSP_STAT_TNF) == SET) && ( xf_setup->tx_cnt < xf_setup->length) ) { + SSP_Write2BFifo(pSSP, xf_setup) + } + + /* Check overrun error */ + if (IP_SSP_GetRawIntStatus(pSSP, SSP_RORRIS) == SET) { + return ERROR; + } + + /* Check for any data available in RX FIFO */ + SSP_Read2BFifo(pSSP, xf_setup, rDat) + } + + if (xf_setup->tx_data) { + return xf_setup->tx_cnt; + } + else if (xf_setup->rx_data) { + return xf_setup->rx_cnt; + } + return 0; + } + else { + while (xf_setup->rx_cnt < xf_setup->length || xf_setup->tx_cnt < xf_setup->length) { + /* write data to buffer */ + if (( IP_SSP_GetStatus(pSSP, SSP_STAT_TNF) == SET) && ( xf_setup->tx_cnt < xf_setup->length) ) { + SSP_Write1BFifo(pSSP, xf_setup) + } + + /* Check overrun error */ + if (IP_SSP_GetRawIntStatus(pSSP, SSP_RORRIS) == SET) { + return ERROR; + } + + /* Check for any data available in RX FIFO */ + SSP_Read1BFifo(pSSP, xf_setup, rDat) + } + + if (xf_setup->tx_data) { + return xf_setup->tx_cnt; + } + else if (xf_setup->rx_data) { + return xf_setup->rx_cnt; + } + return 0; + } +} + +/* SSP Polling Write in blocking mode */ +uint32_t Chip_SSP_WriteFrames_Blocking(LPC_SSP_Type *pSSP, uint8_t *buffer, uint32_t buffer_len) +{ + uint32_t tx_cnt = 0, rx_cnt = 0; + + /* Clear all remaining frames in RX FIFO */ + while (IP_SSP_GetStatus(pSSP, SSP_STAT_RNE)) { + IP_SSP_ReceiveFrame(pSSP); + } + + /* Clear status */ + IP_SSP_ClearIntPending(pSSP, SSP_INT_CLEAR_BITMASK); + + if (IP_SSP_GetDataSize(pSSP) > SSP_BITS_8) { + uint16_t *wdata16; + + wdata16 = (uint16_t *) buffer; + + while (tx_cnt < buffer_len || rx_cnt < buffer_len) { + /* write data to buffer */ + if ((IP_SSP_GetStatus(pSSP, SSP_STAT_TNF) == SET) && (tx_cnt < buffer_len)) { + IP_SSP_SendFrame(pSSP, *wdata16); + wdata16++; + tx_cnt += 2; + } + + /* Check overrun error */ + if (IP_SSP_GetRawIntStatus(pSSP, SSP_RORRIS) == SET) { + return ERROR; + } + + /* Check for any data available in RX FIFO */ + while (IP_SSP_GetStatus(pSSP, SSP_STAT_RNE) == SET) { + IP_SSP_ReceiveFrame(pSSP); /* read dummy data */ + rx_cnt += 2; + } + } + + return tx_cnt; + } + else { + uint8_t *wdata8; + + wdata8 = buffer; + + while (tx_cnt < buffer_len || rx_cnt < buffer_len) { + /* write data to buffer */ + if ((IP_SSP_GetStatus(pSSP, SSP_STAT_TNF) == SET) && (tx_cnt < buffer_len)) { + IP_SSP_SendFrame(pSSP, *wdata8); + wdata8++; + tx_cnt++; + } + + /* Check overrun error */ + if (IP_SSP_GetRawIntStatus(pSSP, SSP_RORRIS) == SET) { + return ERROR; + } + + /* Check for any data available in RX FIFO */ + while (IP_SSP_GetStatus(pSSP, SSP_STAT_RNE) == SET && rx_cnt < buffer_len) { + IP_SSP_ReceiveFrame(pSSP); /* read dummy data */ + rx_cnt++; + } + } + + return tx_cnt; + } +} + +/* SSP Polling Read in blocking mode */ +uint32_t Chip_SSP_ReadFrames_Blocking(LPC_SSP_Type *pSSP, uint8_t *buffer, uint32_t buffer_len) +{ + uint32_t rx_cnt = 0, tx_cnt = 0; + + /* Clear all remaining frames in RX FIFO */ + while (IP_SSP_GetStatus(pSSP, SSP_STAT_RNE)) { + IP_SSP_ReceiveFrame(pSSP); + } + + /* Clear status */ + IP_SSP_ClearIntPending(pSSP, SSP_INT_CLEAR_BITMASK); + + if (IP_SSP_GetDataSize(pSSP) > SSP_BITS_8) { + uint16_t *rdata16; + + rdata16 = (uint16_t *) buffer; + + while (tx_cnt < buffer_len || rx_cnt < buffer_len) { + /* write data to buffer */ + if ((IP_SSP_GetStatus(pSSP, SSP_STAT_TNF) == SET) && (tx_cnt < buffer_len)) { + IP_SSP_SendFrame(pSSP, 0xFFFF); /* just send dummy data */ + tx_cnt += 2; + } + + /* Check overrun error */ + if (IP_SSP_GetRawIntStatus(pSSP, SSP_RORRIS) == SET) { + return ERROR; + } + + /* Check for any data available in RX FIFO */ + while (IP_SSP_GetStatus(pSSP, SSP_STAT_RNE) == SET && rx_cnt < buffer_len) { + *rdata16 = IP_SSP_ReceiveFrame(pSSP); + rdata16++; + rx_cnt += 2; + } + } + + return rx_cnt; + } + else { + uint8_t *rdata8; + + rdata8 = buffer; + + while (tx_cnt < buffer_len || rx_cnt < buffer_len) { + /* write data to buffer */ + if ((IP_SSP_GetStatus(pSSP, SSP_STAT_TNF) == SET) && (tx_cnt < buffer_len)) { + IP_SSP_SendFrame(pSSP, 0xFF); /* just send dummy data */ + tx_cnt++; + } + + /* Check overrun error */ + if (IP_SSP_GetRawIntStatus(pSSP, SSP_RORRIS) == SET) { + return ERROR; + } + + /* Check for any data available in RX FIFO */ + while (IP_SSP_GetStatus(pSSP, SSP_STAT_RNE) == SET && rx_cnt < buffer_len) { + *rdata8 = IP_SSP_ReceiveFrame(pSSP); + rdata8++; + rx_cnt++; + } + } + + return rx_cnt; + } +} + +/* Clean all data in RX FIFO of SSP */ +void Chip_SSP_Int_FlushData(LPC_SSP_Type *pSSP) +{ + if (IP_SSP_GetStatus(pSSP, SSP_STAT_BSY)) { + while (IP_SSP_GetStatus(pSSP, SSP_STAT_BSY)) ; + } + + /* Clear all remaining frames in RX FIFO */ + while (IP_SSP_GetStatus(pSSP, SSP_STAT_RNE)) { + IP_SSP_ReceiveFrame(pSSP); + } + + /* Clear status */ + IP_SSP_ClearIntPending(pSSP, SSP_INT_CLEAR_BITMASK); +} + +/* SSP Interrupt Read/Write with 8-bit frame width */ +Status Chip_SSP_Int_RWFrames8Bits(LPC_SSP_Type *pSSP, Chip_SSP_DATA_SETUP_Type *xf_setup) +{ + uint16_t rDat; + + /* Check overrun error in RIS register */ + if (IP_SSP_GetRawIntStatus(pSSP, SSP_RORRIS) == SET) { + return ERROR; + } + + if ((xf_setup->tx_cnt != xf_setup->length) || (xf_setup->rx_cnt != xf_setup->length)) { + /* check if RX FIFO contains data */ + SSP_Read1BFifo(pSSP, xf_setup, rDat) + + while ((IP_SSP_GetStatus(pSSP, SSP_STAT_TNF)) && (xf_setup->tx_cnt != xf_setup->length)) { + /* Write data to buffer */ + SSP_Write1BFifo(pSSP, xf_setup) + + /* Check overrun error in RIS register */ + if (IP_SSP_GetRawIntStatus(pSSP, SSP_RORRIS) == SET) { + return ERROR; + } + + /* Check for any data available in RX FIFO */ + SSP_Read1BFifo(pSSP, xf_setup, rDat) + } + return SUCCESS; + } + + return ERROR; +} + +/* SSP Interrupt Read/Write with 16-bit frame width */ +Status Chip_SSP_Int_RWFrames16Bits(LPC_SSP_Type *pSSP, Chip_SSP_DATA_SETUP_Type *xf_setup) +{ + uint16_t rDat; + + /* Check overrun error in RIS register */ + if (IP_SSP_GetRawIntStatus(pSSP, SSP_RORRIS) == SET) { + return ERROR; + } + + if ((xf_setup->tx_cnt != xf_setup->length) || (xf_setup->rx_cnt != xf_setup->length)) { + /* check if RX FIFO contains data */ + SSP_Read2BFifo(pSSP, xf_setup, rDat) + + while ((IP_SSP_GetStatus(pSSP, SSP_STAT_TNF)) && (xf_setup->tx_cnt != xf_setup->length)) { + /* Write data to buffer */ + SSP_Write2BFifo(pSSP, xf_setup) + + /* Check overrun error in RIS register */ + if (IP_SSP_GetRawIntStatus(pSSP, SSP_RORRIS) == SET) { + return ERROR; + } + + /* Check for any data available in RX FIFO */ + SSP_Read2BFifo(pSSP, xf_setup, rDat) + } + return SUCCESS; + } + + return ERROR; +} + +/* Set the SSP operating modes, master or slave */ +void Chip_SSP_Set_Master(LPC_SSP_Type *pSSP, bool master) +{ + if (master) { + IP_SSP_Set_Mode(pSSP, SSP_MODE_MASTER); + } + else { + IP_SSP_Set_Mode(pSSP, SSP_MODE_SLAVE); + } +} + +/* Set the clock frequency for SSP interface */ +void Chip_SSP_Set_BitRate(LPC_SSP_Type *pSSP, uint32_t bit_rate) +{ + uint32_t ssp_clk, cr0_div, cmp_clk, prescale; + + if (pSSP == LPC_SSP0) { + ssp_clk = Chip_Clock_GetBaseClocktHz(CLK_BASE_SSP0); + } + else { + ssp_clk = Chip_Clock_GetBaseClocktHz(CLK_BASE_SSP1); + } + + cr0_div = 0; + cmp_clk = 0xFFFFFFFF; + prescale = 2; + + while (cmp_clk > bit_rate) { + cmp_clk = ssp_clk / ((cr0_div + 1) * prescale); + if (cmp_clk > bit_rate) { + cr0_div++; + if (cr0_div > 0xFF) { + cr0_div = 0; + prescale += 2; + } + } + } + + IP_SSP_Set_ClockRate(pSSP, cr0_div, prescale); +} + +/* Set up the SSP frame format */ +void Chip_SSP_Set_Format(LPC_SSP_Type *pSSP, SSP_ConfigFormat *format) +{ + IP_SSP_Set_Format(pSSP, format->bits, format->frameFormat, format->clockFormat); +} + +/* Enable/Disable SSP interrupt */ +void Chip_SSP_Int_Cmd(LPC_SSP_Type *pSSP, FunctionalState NewState) +{ + IP_SSP_Int_Enable(pSSP, SSP_TXIM, NewState); +} + +/* Enable/Disable DMA */ +void Chip_SSP_DMA_Cmd(LPC_SSP_Type *pSSP, FunctionalState NewState) +{ + IP_SSP_DMA_Cmd(pSSP, SSP_DMA_RX, NewState); + IP_SSP_DMA_Cmd(pSSP, SSP_DMA_TX, NewState); +} + +/* Initialize the SSP */ +void Chip_SSP_Init(LPC_SSP_Type *pSSP) +{ + IP_SSP_Set_Mode(pSSP, SSP_MODE_MASTER); + IP_SSP_Set_Format(pSSP, SSP_BITS_8, SSP_FRAMEFORMAT_SPI, SSP_CLOCK_CPHA0_CPOL0); + Chip_SSP_Set_BitRate(pSSP, 100000); +} diff --git a/bsp/xplorer4330/libraries/lpc_chip/chip_18xx_43xx/ssp_18xx_43xx.h b/bsp/xplorer4330/libraries/lpc_chip/chip_18xx_43xx/ssp_18xx_43xx.h new file mode 100644 index 0000000000..bddb50eab4 --- /dev/null +++ b/bsp/xplorer4330/libraries/lpc_chip/chip_18xx_43xx/ssp_18xx_43xx.h @@ -0,0 +1,311 @@ +/* + * @brief LPC18xx/43xx SSP driver + * + * @note + * Copyright(C) NXP Semiconductors, 2012 + * All rights reserved. + * + * @par + * Software that is described herein is for illustrative purposes only + * which provides customers with programming information regarding the + * LPC products. This software is supplied "AS IS" without any warranties of + * any kind, and NXP Semiconductors and its licensor disclaim any and + * all warranties, express or implied, including all implied warranties of + * merchantability, fitness for a particular purpose and non-infringement of + * intellectual property rights. NXP Semiconductors assumes no responsibility + * or liability for the use of the software, conveys no license or rights under any + * patent, copyright, mask work right, or any other intellectual property rights in + * or to any products. NXP Semiconductors reserves the right to make changes + * in the software without notification. NXP Semiconductors also makes no + * representation or warranty that such application will be suitable for the + * specified use without further testing or modification. + * + * @par + * Permission to use, copy, modify, and distribute this software and its + * documentation is hereby granted, under NXP Semiconductors' and its + * licensor's relevant copyrights in the software, without fee, provided that it + * is used in conjunction with NXP Semiconductors microcontrollers. This + * copyright, permission, and disclaimer notice must appear in all copies of + * this code. + */ + +#ifndef __SSP_18XX_43XX_H_ +#define __SSP_18XX_43XX_H_ + +#include "chip.h" + +#ifdef __cplusplus +extern "C" { +#endif + +/** @defgroup SSP_18XX_43XX CHIP: LPC18xx/43xx SSP driver + * @ingroup CHIP_18XX_43XX_Drivers + * @{ + */ + +/* + * @brief SSP clock format + */ +typedef enum SSP_ClockFormat { + SSP_CLOCK_CPHA0_CPOL0 = (0 << 6), /**< CPHA = 0, CPOL = 0 */ + SSP_CLOCK_CPHA0_CPOL1 = (1u << 6), /**< CPHA = 0, CPOL = 1 */ + SSP_CLOCK_CPHA1_CPOL0 = (2u << 6), /**< CPHA = 1, CPOL = 0 */ + SSP_CLOCK_CPHA1_CPOL1 = (3u << 6), /**< CPHA = 1, CPOL = 1 */ + SSP_CLOCK_MODE0 = SSP_CLOCK_CPHA0_CPOL0,/**< alias */ + SSP_CLOCK_MODE1 = SSP_CLOCK_CPHA1_CPOL0,/**< alias */ + SSP_CLOCK_MODE2 = SSP_CLOCK_CPHA0_CPOL1,/**< alias */ + SSP_CLOCK_MODE3 = SSP_CLOCK_CPHA1_CPOL1,/**< alias */ +} SSP_ClockFormat; + +/* + * @brief SSP frame format + */ +typedef enum SSP_FrameFormat { + SSP_FRAMEFORMAT_SPI = (0 << 4), /**< Frame format: SPI */ + SSP_FRAMEFORMAT_TI = (1u << 4), /**< Frame format: TI SSI */ + SSP_FRAMEFORMAT_MICROWIRE = (2u << 4), /**< Frame format: Microwire */ +} SSP_FrameFormat; + +/* + * @brief Number of bits per frame + */ +typedef enum SSP_Bits { + SSP_BITS_4 = (3u << 0), /**< 4 bits/frame */ + SSP_BITS_5 = (4u << 0), /**< 5 bits/frame */ + SSP_BITS_6 = (5u << 0), /**< 6 bits/frame */ + SSP_BITS_7 = (6u << 0), /**< 7 bits/frame */ + SSP_BITS_8 = (7u << 0), /**< 8 bits/frame */ + SSP_BITS_9 = (8u << 0), /**< 9 bits/frame */ + SSP_BITS_10 = (9u << 0), /**< 10 bits/frame */ + SSP_BITS_11 = (10u << 0), /**< 11 bits/frame */ + SSP_BITS_12 = (11u << 0), /**< 12 bits/frame */ + SSP_BITS_13 = (12u << 0), /**< 13 bits/frame */ + SSP_BITS_14 = (13u << 0), /**< 14 bits/frame */ + SSP_BITS_15 = (14u << 0), /**< 15 bits/frame */ + SSP_BITS_16 = (15u << 0), /**< 16 bits/frame */ +} SSP_Bits; + +/* + * @brief SSP config format + */ +typedef struct SSP_ConfigFormat { + SSP_Bits bits; /**< Format config: bits/frame */ + SSP_ClockFormat clockFormat;/**< Format config: clock phase/polarity */ + SSP_FrameFormat frameFormat;/**< Format config: SPI/TI/Microwire */ +} SSP_ConfigFormat; + +/* + * @brief SSP mode + */ +typedef enum SSP_Mode { + SSP_MODE_MASTER = (0 << 2), /**< Master mode */ + SSP_MODE_SLAVE = (1u << 2), /**< Slave mode */ +} SSP_Mode; + +/* + * @brief SPI address + */ +typedef struct { + uint8_t port; + uint8_t pin; +} SPI_Address_t; + +/* + * @brief SSP data setup structure + */ +typedef struct { + void *tx_data; /**< Pointer to transmit data */ + uint32_t tx_cnt; /**< Transmit counter */ + void *rx_data; /**< Pointer to transmit data */ + uint32_t rx_cnt; /**< Receive counter */ + uint32_t length; /**< Length of transfer data */ +} Chip_SSP_DATA_SETUP_Type; + +/** SSP configuration parameter defines */ +/** Clock phase control bit */ +#define SSP_CPHA_FIRST SSP_CR0_CPHA_FIRST +#define SSP_CPHA_SECOND SSP_CR0_CPHA_SECOND + +/** Clock polarity control bit */ +/* There's no bug here!!! + * - If bit[6] in SSPnCR0 is 0: SSP controller maintains the bus clock low between frames. + * That means the active clock is in HI state. + * - If bit[6] in SSPnCR0 is 1 (SSP_CR0_CPOL_HI): SSP controller maintains the bus clock + * high between frames. That means the active clock is in LO state. + */ +#define SSP_CPOL_HI SSP_CR0_CPOL_LO +#define SSP_CPOL_LO SSP_CR0_CPOL_HI + +/** SSP master mode enable */ +#define SSP_SLAVE_MODE SSP_CR1_SLAVE_EN +#define SSP_MASTER_MODE SSP_CR1_MASTER_EN + +/** + * @brief Get the current status of SSP controller + * @param pSSP : The base of SSP peripheral on the chip + * @param Stat : Type of status, should be : + * - SSP_STAT_TFE + * - SSP_STAT_TNF + * - SSP_STAT_RNE + * - SSP_STAT_RFF + * - SSP_STAT_BSY + * @return SSP controller status, SET or RESET + */ +STATIC INLINE FlagStatus Chip_SSP_GetStatus(LPC_SSP_Type *pSSP, SSP_Status_Type Stat) +{ + return IP_SSP_GetStatus(pSSP, Stat); +} + +/** + * @brief Enable/Disable SSP operation + * @param pSSP : The base of SSP peripheral on the chip + * @param NewState : New state, ENABLE or DISABLE + * @return Nothing + */ +STATIC INLINE void Chip_SSP_Cmd(LPC_SSP_Type *pSSP, FunctionalState NewState) +{ + IP_SSP_Cmd(pSSP, NewState); +} + +/** + * @brief Disable SSP operation + * @param pSSP : The base of SSP peripheral on the chip + * @return Nothing + * The SSP controller is disabled + */ +STATIC INLINE void Chip_SSP_DeInit(LPC_SSP_Type *pSSP) +{ + IP_SSP_DeInit(pSSP); +} + +/** + * @brief Enable/Disable loopback mode + * @param pSSP : The base of SSP peripheral on the chip + * @param NewState : New state, ENABLE or DISABLE + * @return Nothing + * Serial input is taken from the serial output (MOSI or MISO) rather + * than the serial input pin + */ +STATIC INLINE void Chip_SSP_LoopBackCmd(LPC_SSP_Type *pSSP, FunctionalState NewState) +{ + IP_SSP_LoopBackCmd(pSSP, NewState); +} + +/** + * @brief Clean all data in RX FIFO of SSP + * @param pSSP : The base SSP peripheral on the chip + * @return Nothing + */ +void Chip_SSP_Int_FlushData(LPC_SSP_Type *pSSP); + +/** + * @brief SSP Interrupt Read/Write with 8-bit frame width + * @param pSSP : The base SSP peripheral on the chip + * @param xf_setup : Pointer to a SSP_DATA_SETUP_Type structure that contains specified + * information about transmit/receive data configuration + * @return SUCCESS or ERROR + */ +Status Chip_SSP_Int_RWFrames8Bits(LPC_SSP_Type *pSSP, Chip_SSP_DATA_SETUP_Type *xf_setup); + +/** + * @brief SSP Interrupt Read/Write with 16-bit frame width + * @param pSSP : The base SSP peripheral on the chip + * @param xf_setup : Pointer to a SSP_DATA_SETUP_Type structure that contains specified + * information about transmit/receive data configuration + * @return SUCCESS or ERROR + */ +Status Chip_SSP_Int_RWFrames16Bits(LPC_SSP_Type *pSSP, Chip_SSP_DATA_SETUP_Type *xf_setup); + +/** + * @brief SSP Polling Read/Write in blocking mode + * @param pSSP : The base SSP peripheral on the chip + * @param xf_setup : Pointer to a SSP_DATA_SETUP_Type structure that contains specified + * information about transmit/receive data configuration + * @return Actual data length has been transferred + * + * This function can be used in both master and slave mode. It starts with writing phase and after that, + * a reading phase is generated to read any data available in RX_FIFO. All needed information is prepared + * through xf_setup param. + */ +uint32_t Chip_SSP_RWFrames_Blocking(LPC_SSP_Type *pSSP, Chip_SSP_DATA_SETUP_Type *xf_setup); + +/** + * @brief SSP Polling Write in blocking mode + * @param pSSP : The base SSP peripheral on the chip + * @param buffer : Buffer address + * @param buffer_len : Buffer length + * @return Actual data length has been transferred + * + * This function can be used in both master and slave mode. First, a writing operation will send + * the needed data. After that, a dummy reading operation is generated to clear data buffer + */ +uint32_t Chip_SSP_WriteFrames_Blocking(LPC_SSP_Type *pSSP, uint8_t *buffer, uint32_t buffer_len); + +/** + * @brief Note here + * @param pSSP : The base SSP peripheral on the chip + * @param buffer : Buffer address + * @param buffer_len : The length of buffer + * @return Actual data length has been transferred + * + * This function can be used in both master and slave mode. First, a dummy writing operation is generated + * to clear data buffer. After that, a reading operation will receive the needed data + */ +uint32_t Chip_SSP_ReadFrames_Blocking(LPC_SSP_Type *pSSP, uint8_t *buffer, uint32_t buffer_len); + +/** + * @brief Initialize the SSP + * @param pSSP : The base SSP peripheral on the chip + * @return Nothing + */ +void Chip_SSP_Init(LPC_SSP_Type *pSSP); + +/** + * @brief Set the SSP operating modes, master or slave + * @param pSSP : The base SSP peripheral on the chip + * @param master : 1 to set master, 0 to set slave + * @return Nothing + */ +void Chip_SSP_Set_Master(LPC_SSP_Type *pSSP, bool master); + +/** + * @brief Set the clock frequency for SSP interface + * @param pSSP : The base SSP peripheral on the chip + * @param bit_rate : The SSP bit rate + * @return Nothing + */ +void Chip_SSP_Set_BitRate(LPC_SSP_Type *pSSP, uint32_t bit_rate); + +/** + * @brief Set up the SSP frame format + * @param pSSP : The base SSP peripheral on the chip + * @param format : Structure used to format frame + * @return Nothing + */ +void Chip_SSP_Set_Format(LPC_SSP_Type *pSSP, SSP_ConfigFormat *format); + +/** + * @brief Enable/Disable SSP interrupt + * @param pSSP : The base SSP peripheral on the chip + * @param NewState : ENABLE or DISABLE interrupt + * @return Nothing + */ +void Chip_SSP_Int_Cmd(LPC_SSP_Type *pSSP, FunctionalState NewState); + +/** + * @brief Enable/Disable DMA + * @param pSSP : The base SSP peripheral on the chip + * @param NewState : ENABLE or DISABLE DMA + * @return Nothing + */ +void Chip_SSP_DMA_Cmd(LPC_SSP_Type *pSSP, FunctionalState NewState); + +/** + * @} + */ + +#ifdef __cplusplus +} +#endif + +#endif /* __SSP_18XX_43XX_H_ */ diff --git a/bsp/xplorer4330/libraries/lpc_chip/chip_18xx_43xx/timer_18xx_43xx.h b/bsp/xplorer4330/libraries/lpc_chip/chip_18xx_43xx/timer_18xx_43xx.h new file mode 100644 index 0000000000..99d8cf1320 --- /dev/null +++ b/bsp/xplorer4330/libraries/lpc_chip/chip_18xx_43xx/timer_18xx_43xx.h @@ -0,0 +1,371 @@ +/* + * @brief Timer/PWM control functions + * + * @note + * Copyright(C) NXP Semiconductors, 2012 + * All rights reserved. + * + * @par + * Software that is described herein is for illustrative purposes only + * which provides customers with programming information regarding the + * LPC products. This software is supplied "AS IS" without any warranties of + * any kind, and NXP Semiconductors and its licensor disclaim any and + * all warranties, express or implied, including all implied warranties of + * merchantability, fitness for a particular purpose and non-infringement of + * intellectual property rights. NXP Semiconductors assumes no responsibility + * or liability for the use of the software, conveys no license or rights under any + * patent, copyright, mask work right, or any other intellectual property rights in + * or to any products. NXP Semiconductors reserves the right to make changes + * in the software without notification. NXP Semiconductors also makes no + * representation or warranty that such application will be suitable for the + * specified use without further testing or modification. + * + * @par + * Permission to use, copy, modify, and distribute this software and its + * documentation is hereby granted, under NXP Semiconductors' and its + * licensor's relevant copyrights in the software, without fee, provided that it + * is used in conjunction with NXP Semiconductors microcontrollers. This + * copyright, permission, and disclaimer notice must appear in all copies of + * this code. + */ + +#ifndef __TIMER_18XX_43XX_H_ +#define __TIMER_18XX_43XX_H_ + +#include "chip.h" + +#ifdef __cplusplus +extern "C" { +#endif + +/** @defgroup TIMER_18XX_43XX CHIP: LPC18xx/43xx Timer driver + * @ingroup CHIP_18XX_43XX_Drivers + * @{ + */ + +/** + * @brief Determine if a match interrupt is pending + * @param TMRx : Pointer to timer IP register address + * @param matchnum : Match interrupt number to check + * @return false if the interrupt is not pending, otherwise true + * Determine if the match interrupt for the passed timer and match + * counter is pending. + */ +STATIC INLINE bool Chip_TIMER_MatchPending(LPC_TIMER_Type *TMRx, int8_t matchnum) +{ + return IP_TIMER_MatchPending(TMRx, matchnum); +} + +/** + * @brief Determine if a capture interrupt is pending + * @param TMRx : Pointer to timer IP register address + * @param capnum : Capture interrupt number to check + * @return false if the interrupt is not pending, otherwise true + * Determine if the capture interrupt for the passed capture pin is + * pending. + */ +STATIC INLINE bool Chip_TIMER_CapturePending(LPC_TIMER_Type *TMRx, int8_t capnum) +{ + return IP_TIMER_CapturePending(TMRx, capnum); +} + +/** + * @brief Clears a (pending) match interrupt + * @param TMRx : Pointer to timer IP register address + * @param matchnum : Match interrupt number to clear + * @return Nothing + * Clears a pending timer match interrupt. + */ +STATIC INLINE void Chip_TIMER_ClearMatch(LPC_TIMER_Type *TMRx, int8_t matchnum) +{ + IP_TIMER_ClearMatch(TMRx, matchnum); +} + +/** + * @brief Clears a (pending) capture interrupt + * @param TMRx : Pointer to timer IP register address + * @param capnum : Capture interrupt number to clear + * @return Nothing + * Clears a pending timer capture interrupt. + */ +STATIC INLINE void Chip_TIMER_ClearCapture(LPC_TIMER_Type *TMRx, int8_t capnum) +{ + IP_TIMER_ClearCapture(TMRx, capnum); +} + +/** + * @brief Enables the timer (starts count) + * @param TMRx : Pointer to timer IP register address + * @return Nothing + * Enables the timer to start counting. + */ +STATIC INLINE void Chip_TIMER_Enable(LPC_TIMER_Type *TMRx) +{ + IP_TIMER_Enable(TMRx); +} + +/** + * @brief Disables the timer (stops count) + * @param TMRx : Pointer to timer IP register address + * @return Nothing + * Disables the timer to stop counting. + */ +STATIC INLINE void Chip_TIMER_Disable(LPC_TIMER_Type *TMRx) +{ + IP_TIMER_Disable(TMRx); +} + +/** + * @brief Returns the current timer count + * @param TMRx : Pointer to timer IP register address + * @return Current timer terminal count value + * Returns the current timer terminal count. + */ +STATIC INLINE uint32_t Chip_TIMER_ReadCount(LPC_TIMER_Type *TMRx) +{ + return IP_TIMER_ReadCount(TMRx); +} + +/** + * @brief Returns the current prescale count + * @param TMRx : Pointer to timer IP register address + * @return Current timer prescale count value + * Returns the current prescale count. + */ +STATIC INLINE uint32_t Chip_TIMER_ReadPrescale(LPC_TIMER_Type *TMRx) +{ + return IP_TIMER_ReadPrescale(TMRx); +} + +/** + * @brief Sets the prescaler value + * @param TMRx : Pointer to timer IP register address + * @param prescale : Prescale value to set the prescale register to + * @return Nothing + * Sets the prescale count value. + */ +STATIC INLINE void Chip_TIMER_PrescaleSet(LPC_TIMER_Type *TMRx, uint32_t prescale) +{ + IP_TIMER_PrescaleSet(TMRx, prescale); +} + +/** + * @brief Sets a timer match value + * @param TMRx : Pointer to timer IP register address + * @param matchnum : Match timer to set match count for + * @param matchval : Match value for the selected match count + * @return Nothing + * Sets ones of the timer match values. + */ +STATIC INLINE void Chip_TIMER_SetMatch(LPC_TIMER_Type *TMRx, int8_t matchnum, uint32_t matchval) +{ + IP_TIMER_SetMatch(TMRx, matchnum, matchval); +} + +/** + * @brief Reads a capture register + * @param TMRx : Pointer to timer IP register address + * @param capnum : Capture register to read + * @return The selected capture register value + * Returns the selected capture register value. + */ +STATIC INLINE uint32_t Chip_TIMER_ReadCapture(LPC_TIMER_Type *TMRx, int8_t capnum) +{ + return IP_TIMER_ReadCapture(TMRx, capnum); +} + +/** + * @brief Resets the timer terminal and prescale counts to 0 + * @param TMRx : Pointer to timer IP register address + * @return Nothing + */ +STATIC INLINE void Chip_TIMER_Reset(LPC_TIMER_Type *TMRx) +{ + IP_TIMER_Reset(TMRx); +} + +/** + * @brief Enables a match interrupt that fires when the terminal count + * matches the match counter value. + * @param TMRx : Pointer to timer IP register address + * @param matchnum : Match timer, 0 to 3 + * @return Nothing + */ +STATIC INLINE void Chip_TIMER_MatchEnableInt(LPC_TIMER_Type *TMRx, int8_t matchnum) +{ + IP_TIMER_MatchEnableInt(TMRx, matchnum); +} + +/** + * @brief Disables a match interrupt for a match counter. + * @param TMRx : Pointer to timer IP register address + * @param matchnum : Match timer, 0 to 3 + * @return Nothing + */ +STATIC INLINE void Chip_TIMER_MatchDisableInt(LPC_TIMER_Type *TMRx, int8_t matchnum) +{ + IP_TIMER_MatchDisableInt(TMRx, matchnum); +} + +/** + * @brief For the specific match counter, enables reset of the terminal count register when a match occurs + * @param TMRx : Pointer to timer IP register address + * @param matchnum : Match timer, 0 to 3 + * @return Nothing + */ +STATIC INLINE void Chip_TIMER_ResetOnMatchEnable(LPC_TIMER_Type *TMRx, int8_t matchnum) +{ + IP_TIMER_ResetOnMatchEnable(TMRx, matchnum); +} + +/** + * @brief For the specific match counter, disables reset of the terminal count register when a match occurs + * @param TMRx : Pointer to timer IP register address + * @param matchnum : Match timer, 0 to 3 + * @return Nothing + */ +STATIC INLINE void Chip_TIMER_ResetOnMatchDisable(LPC_TIMER_Type *TMRx, int8_t matchnum) +{ + IP_TIMER_ResetOnMatchDisable(TMRx, matchnum); +} + +/** + * @brief Enable a match timer to stop the terminal count when a + * match count equals the terminal count. + * @param TMRx : Pointer to timer IP register address + * @param matchnum : Match timer, 0 to 3 + * @return Nothing + */ +STATIC INLINE void Chip_TIMER_StopOnMatchEnable(LPC_TIMER_Type *TMRx, int8_t matchnum) +{ + IP_TIMER_StopOnMatchEnable(TMRx, matchnum); +} + +/** + * @brief Disable stop on match for a match timer. Disables a match timer + * to stop the terminal count when a match count equals the terminal count. + * @param TMRx : Pointer to timer IP register address + * @param matchnum : Match timer, 0 to 3 + * @return Nothing + */ +STATIC INLINE void Chip_TIMER_StopOnMatchDisable(LPC_TIMER_Type *TMRx, int8_t matchnum) +{ + IP_TIMER_StopOnMatchDisable(TMRx, matchnum); +} + +/** + * @brief Enables capture on on rising edge of selected CAP signal for the + * selected capture register, enables the selected CAPn.capnum signal to load + * the capture register with the terminal coount on a rising edge. + * @param TMRx : Pointer to timer IP register address + * @param capnum : Capture signal/register to use + * @return Nothing + */ +STATIC INLINE void Chip_TIMER_CaptureRisingEdgeEnable(LPC_TIMER_Type *TMRx, int8_t capnum) +{ + IP_TIMER_CaptureRisingEdgeEnable(TMRx, capnum); +} + +/** + * @brief Disables capture on on rising edge of selected CAP signal. For the + * selected capture register, disables the selected CAPn.capnum signal to load + * the capture register with the terminal coount on a rising edge. + * @param TMRx : Pointer to timer IP register address + * @param capnum : Capture signal/register to use + * @return Nothing + */ +STATIC INLINE void Chip_TIMER_CaptureRisingEdgeDisable(LPC_TIMER_Type *TMRx, int8_t capnum) +{ + IP_TIMER_CaptureRisingEdgeDisable(TMRx, capnum); +} + +/** + * @brief Enables capture on on falling edge of selected CAP signal. For the + * selected capture register, enables the selected CAPn.capnum signal to load + * the capture register with the terminal coount on a falling edge. + * @param TMRx : Pointer to timer IP register address + * @param capnum : Capture signal/register to use + * @return Nothing + */ +STATIC INLINE void Chip_TIMER_CaptureFallingEdgeEnable(LPC_TIMER_Type *TMRx, int8_t capnum) +{ + IP_TIMER_CaptureFallingEdgeEnable(TMRx, capnum); +} + +/** + * @brief Disables capture on on falling edge of selected CAP signal. For the + * selected capture register, disables the selected CAPn.capnum signal to load + * the capture register with the terminal coount on a falling edge. + * @param TMRx : Pointer to timer IP register address + * @param capnum : Capture signal/register to use + * @return Nothing + */ +STATIC INLINE void Chip_TIMER_CaptureFallingEdgeDisable(LPC_TIMER_Type *TMRx, int8_t capnum) +{ + IP_TIMER_CaptureFallingEdgeDisable(TMRx, capnum); +} + +/** + * @brief Enables interrupt on capture of selected CAP signal. For the + * selected capture register, an interrupt will be generated when the enabled + * rising or falling edge on CAPn.capnum is detected. + * @param TMRx : Pointer to timer IP register address + * @param capnum : Capture signal/register to use + * @return Nothing + */ +STATIC INLINE void Chip_TIMER_CaptureEnableInt(LPC_TIMER_Type *TMRx, int8_t capnum) +{ + IP_TIMER_CaptureEnableInt(TMRx, capnum); +} + +/** + * @brief Disables interrupt on capture of selected CAP signal + * @param TMRx : Pointer to timer IP register address + * @param capnum : Capture signal/register to use + * @return Nothing + */ +STATIC INLINE void Chip_TIMER_CaptureDisableInt(LPC_TIMER_Type *TMRx, int8_t capnum) +{ + IP_TIMER_CaptureDisableInt(TMRx, capnum); +} + +/** + * @brief Sets external match control (MATn.matchnum) pin control + * @param TMRx : Pointer to timer IP register address + * @param initial_state : Initial state of the pin, high(1) or low(0) + * @param matchState : Selects the match state for the pin + * @param matchnum : MATn.matchnum signal to use + * @return Nothing + * For the pin selected with matchnum, sets the function of the pin that occurs on + * a terminal count match for the match count. + */ +STATIC INLINE void Chip_TIMER_ExtMatchControlSet(LPC_TIMER_Type *TMRx, int8_t initial_state, + IP_TIMER_PIN_MATCH_STATE_Type matchState, int8_t matchnum) +{ + IP_TIMER_ExtMatchControlSet(TMRx, initial_state, matchState, matchnum); +} + +/** + * @brief Sets timer count source and edge with the selected passed from CapSrc + * @param TMRx : Pointer to timer IP register address + * @param capSrc : timer clock source and edge + * @param capnum : CAPn.capnum pin to use (if used) + * @return Nothing + * If CapSrc selected a CAPn pin, select the specific CAPn pin with the capnum value. + */ +STATIC INLINE void Chip_TIMER_TIMER_SetCountClockSrc(LPC_TIMER_Type *TMRx, + IP_TIMER_CAP_SRC_STATE_Type capSrc, + int8_t capnum) +{ + IP_TIMER_SetCountClockSrc(TMRx, capSrc, capnum); +} + +/** + * @} + */ + +#ifdef __cplusplus +} +#endif + +#endif /* __TIMER_18XX_43XX_H_ */ diff --git a/bsp/xplorer4330/libraries/lpc_chip/chip_18xx_43xx/uart_18xx_43xx.c b/bsp/xplorer4330/libraries/lpc_chip/chip_18xx_43xx/uart_18xx_43xx.c new file mode 100644 index 0000000000..750e47e110 --- /dev/null +++ b/bsp/xplorer4330/libraries/lpc_chip/chip_18xx_43xx/uart_18xx_43xx.c @@ -0,0 +1,353 @@ +/* + * @brief LPC18xx/43xx UART chip driver + * + * @note + * Copyright(C) NXP Semiconductors, 2012 + * All rights reserved. + * + * @par + * Software that is described herein is for illustrative purposes only + * which provides customers with programming information regarding the + * LPC products. This software is supplied "AS IS" without any warranties of + * any kind, and NXP Semiconductors and its licensor disclaim any and + * all warranties, express or implied, including all implied warranties of + * merchantability, fitness for a particular purpose and non-infringement of + * intellectual property rights. NXP Semiconductors assumes no responsibility + * or liability for the use of the software, conveys no license or rights under any + * patent, copyright, mask work right, or any other intellectual property rights in + * or to any products. NXP Semiconductors reserves the right to make changes + * in the software without notification. NXP Semiconductors also makes no + * representation or warranty that such application will be suitable for the + * specified use without further testing or modification. + * + * @par + * Permission to use, copy, modify, and distribute this software and its + * documentation is hereby granted, under NXP Semiconductors' and its + * licensor's relevant copyrights in the software, without fee, provided that it + * is used in conjunction with NXP Semiconductors microcontrollers. This + * copyright, permission, and disclaimer notice must appear in all copies of + * this code. + */ + +#include "uart_18xx_43xx.h" + +/***************************************************************************** + * Private types/enumerations/variables + ****************************************************************************/ + +/** UART Ring buffer declaration*/ +static UART_RingBuffer_Type rb; + +/** Current Tx Interrupt enable state */ +static __IO FlagStatus TxIntStat; + +/***************************************************************************** + * Public types/enumerations/variables + ****************************************************************************/ + +/***************************************************************************** + * Private functions + ****************************************************************************/ + +/* Get UART number based on selected UART */ +static UART_ID_Type Chip_UART_Get_UARTNum(LPC_USART_Type *UARTx) +{ + if (UARTx == LPC_USART0) { + return UART_0; + } + else if (UARTx == LPC_UART1) { + return UART_1; + } + else if (UARTx == LPC_USART2) { + return UART_2; + } + + return UART_3; +} + +/* Determine UART clock based in selected UART */ +static CCU_CLK_T Chip_UART_DetermineClk(LPC_USART_Type *UARTx) { + CCU_CLK_T uartclk; + + /* Pick clock for uart BASED ON SELECTED uart */ + if (UARTx == LPC_UART1) { + uartclk = CLK_MX_UART1; + } + if (UARTx == LPC_USART2) { + uartclk = CLK_MX_UART2; + } + if (UARTx == LPC_USART3) { + uartclk = CLK_MX_UART3; + } + else { + uartclk = CLK_MX_UART0; + } + + return uartclk; +} + +/***************************************************************************** + * Public functions + ****************************************************************************/ + +/* Initializes the UARTx peripheral */ +void Chip_UART_Init(LPC_USART_Type *UARTx) +{ + UART_ID_Type UARTPort = Chip_UART_Get_UARTNum(UARTx); + + /* Enable UART clocking. UART base clock(s) must already be enabled */ + Chip_Clock_EnableOpts(Chip_UART_DetermineClk(UARTx), true, true, 1); + + IP_UART_Init(UARTx, UARTPort); +} + +/* De-initializes the UARTx peripheral */ +void Chip_UART_DeInit(LPC_USART_Type *UARTx) +{ + UART_ID_Type UARTPort = Chip_UART_Get_UARTNum(UARTx); + + IP_UART_DeInit(UARTx, UARTPort); + + /* Disable UART clocking */ + Chip_Clock_Disable(Chip_UART_DetermineClk(UARTx)); +} + +/* Determines best dividers to get a target baud rate */ +Status Chip_UART_SetBaud(LPC_USART_Type *UARTx, uint32_t baudrate) +{ + uint32_t uClk; + + /* Get UART clock rate */ + uClk = Chip_Clock_GetRate(Chip_UART_DetermineClk(UARTx)); + + return IP_UART_SetBaud(UARTx, baudrate, uClk); +} + +/* Enable/Disable transmission on UART TxD pin */ +void Chip_UART_TxCmd(LPC_USART_Type *UARTx, FunctionalState NewState) +{ + UART_ID_Type UARTPort = Chip_UART_Get_UARTNum(UARTx); + + IP_UART_TxCmd(UARTx, UARTPort, NewState); +} + +/* Get Interrupt Stream Status */ +UART_Int_Status Chip_UART_GetIntStatus(LPC_USART_Type *UARTx) +{ + uint32_t intsrc, tmp, tmp1; + UART_Int_Status ret = UART_ERROR; + + /* Determine the interrupt source */ + intsrc = Chip_UART_IntGetStatus(UARTx); + + tmp = intsrc & UART_IIR_INTID_MASK; + + /* Receive Line Status */ + if (tmp == UART_IIR_INTID_RLS) { + /* Check line status */ + tmp1 = (uint32_t) Chip_UART_GetLineStatus(UARTx); + /* Mask out the Receive Ready and Transmit Holding empty status */ + tmp1 &= (UART_LSR_OE | UART_LSR_PE | UART_LSR_FE \ + | UART_LSR_BI | UART_LSR_RXFE); + /* If any error exist */ + if (tmp1) { + return UART_ERROR; + } + } + + /* Receive Data Available or Character time-out */ + if ((tmp == UART_IIR_INTID_RDA) || (tmp == UART_IIR_INTID_CTI)) { + ret |= READY_TO_RECEIVE; + } + + /* Transmit Holding Empty */ + if (tmp == UART_IIR_INTID_THRE) { + ret |= READY_TO_SEND; + } + return ret; +} + +/* UART interrupt service routine */ +void Chip_UART_Interrupt_Handler(LPC_USART_Type *UARTx) +{ + uint8_t tmpc; + uint32_t rLen; + UART_Int_Status Sts = Chip_UART_GetIntStatus(UARTx); + if (Sts == UART_ERROR) { + return; /* error */ + + } + if (Sts & READY_TO_RECEIVE) { /* ready for Read Data */ + while (1) { + /* Call UART read function in UART driver */ + rLen = Chip_UART_Receive(UARTx, &tmpc, 1, NONE_BLOCKING); + /* If data received */ + if (rLen) { + /* Check if buffer is more space + * If no more space, remaining character will be trimmed out + */ + if (!__BUF_IS_FULL(rb.rx_head, rb.rx_tail)) { + rb.rx[rb.rx_head] = tmpc; + __BUF_INCR(rb.rx_head); + } + } + /* no more data */ + else { + break; + } + } + } + + if (Sts & READY_TO_SEND) { /* ready for Write Data */ + /* Disable THRE interrupt */ + Chip_UART_IntConfig(UARTx, UART_INTCFG_THRE, DISABLE); + + /* Wait for FIFO buffer empty, transfer UART_TX_FIFO_SIZE bytes + * of data or break whenever ring buffers are empty */ + /* Wait until THR empty */ + while (Chip_UART_CheckBusy(UARTx) == SET) ; + + while (!__BUF_IS_EMPTY(rb.tx_head, rb.tx_tail)) { + /* Move a piece of data into the transmit FIFO */ + if (Chip_UART_Send(UARTx, (uint8_t *) &rb.tx[rb.tx_tail], 1, NONE_BLOCKING)) { + /* Update transmit ring FIFO tail pointer */ + __BUF_INCR(rb.tx_tail); + } + else { + break; + } + } + + /* If there is no more data to send, disable the transmit + interrupt - else enable it or keep it enabled */ + if (__BUF_IS_EMPTY(rb.tx_head, rb.tx_tail)) { + Chip_UART_IntConfig(UARTx, UART_INTCFG_THRE, DISABLE); + // Reset Tx Interrupt state + TxIntStat = RESET; + } + else { + /* Set Tx Interrupt state */ + TxIntStat = SET; + Chip_UART_IntConfig(UARTx, UART_INTCFG_THRE, ENABLE); + } + } +} + +/* UART transmit function for interrupt mode (using ring buffers) */ +uint32_t Chip_UART_Interrupt_Transmit(LPC_USART_Type *UARTx, uint8_t *txbuf, uint8_t buflen) +{ + uint8_t *data = (uint8_t *) txbuf; + uint32_t bytes = 0; + + /* Temporarily lock out UART transmit interrupts during this + read so the UART transmit interrupt won't cause problems + with the index values */ + Chip_UART_IntConfig(UARTx, UART_INTCFG_THRE, DISABLE); + + /* Loop until transmit run buffer is full or until n_bytes + expires */ + while ((buflen > 0) && (!__BUF_IS_FULL(rb.tx_head, rb.tx_tail))) { + /* Write data from buffer into ring buffer */ + rb.tx[rb.tx_head] = *data; + data++; + + /* Increment head pointer */ + __BUF_INCR(rb.tx_head); + + /* Increment data count and decrement buffer size count */ + bytes++; + buflen--; + } + + /* + * Check if current Tx interrupt enable is reset, + * that means the Tx interrupt must be re-enabled + * due to call UART_IntTransmit() function to trigger + * this interrupt type + */ + if (TxIntStat == RESET) { + // Disable THRE interrupt + Chip_UART_IntConfig(UARTx, UART_INTCFG_THRE, DISABLE); + + /* Wait for FIFO buffer empty, transfer UART_TX_FIFO_SIZE bytes + * of data or break whenever ring buffers are empty */ + /* Wait until THR empty */ + while (Chip_UART_CheckBusy(UARTx) == SET) ; + + while (!__BUF_IS_EMPTY(rb.tx_head, rb.tx_tail)) { + /* Move a piece of data into the transmit FIFO */ + if (Chip_UART_Send(UARTx, (uint8_t *) &rb.tx[rb.tx_tail], 1, NONE_BLOCKING)) { + /* Update transmit ring FIFO tail pointer */ + __BUF_INCR(rb.tx_tail); + } + else { + break; + } + } + + /* If there is no more data to send, disable the transmit + interrupt - else enable it or keep it enabled */ + if (__BUF_IS_EMPTY(rb.tx_head, rb.tx_tail)) { + Chip_UART_IntConfig(UARTx, UART_INTCFG_THRE, DISABLE); + /* Reset Tx Interrupt state */ + TxIntStat = RESET; + } + else { + /* Set Tx Interrupt state */ + TxIntStat = SET; + Chip_UART_IntConfig(UARTx, UART_INTCFG_THRE, ENABLE); + } + } + /* + * Otherwise, re-enables Tx Interrupt + */ + else { + Chip_UART_IntConfig(UARTx, UART_INTCFG_THRE, ENABLE); + } + + return bytes; +} + +/* UART read function for interrupt mode (using ring buffers) */ +uint32_t Chip_UART_Interrupt_Receive(LPC_USART_Type *UARTx, uint8_t *rxbuf, uint8_t buflen) +{ + uint8_t *data = (uint8_t *) rxbuf; + uint32_t bytes = 0; + + /* Temporarily lock out UART receive interrupts during this + read so the UART receive interrupt won't cause problems + with the index values */ + Chip_UART_IntConfig(UARTx, UART_INTCFG_RBR, DISABLE); + + /* Loop until receive buffer ring is empty or + until max_bytes expires */ + while ((buflen > 0) && (!(__BUF_IS_EMPTY(rb.rx_head, rb.rx_tail)))) { + /* Read data from ring buffer into user buffer */ + *data = rb.rx[rb.rx_tail]; + data++; + + /* Update tail pointer */ + __BUF_INCR(rb.rx_tail); + + /* Increment data count and decrement buffer size count */ + bytes++; + buflen--; + } + + /* Re-enable UART interrupts */ + Chip_UART_IntConfig(UARTx, UART_INTCFG_RBR, ENABLE); + + return bytes; +} + +/* Reset Tx and Rx ring buffer (head and tail) */ +void Chip_UART_InitRingBuffer(void) +{ + TxIntStat = RESET; + + /* Reset ring buf head and tail idx */ + __BUF_RESET(rb.rx_head); + __BUF_RESET(rb.rx_tail); + __BUF_RESET(rb.tx_head); + __BUF_RESET(rb.tx_tail); +} diff --git a/bsp/xplorer4330/libraries/lpc_chip/chip_18xx_43xx/uart_18xx_43xx.h b/bsp/xplorer4330/libraries/lpc_chip/chip_18xx_43xx/uart_18xx_43xx.h new file mode 100644 index 0000000000..4f8b886259 --- /dev/null +++ b/bsp/xplorer4330/libraries/lpc_chip/chip_18xx_43xx/uart_18xx_43xx.h @@ -0,0 +1,288 @@ +/* + * @brief LPC18xx/43xx UART chip driver + * + * @note + * Copyright(C) NXP Semiconductors, 2012 + * All rights reserved. + * + * @par + * Software that is described herein is for illustrative purposes only + * which provides customers with programming information regarding the + * LPC products. This software is supplied "AS IS" without any warranties of + * any kind, and NXP Semiconductors and its licensor disclaim any and + * all warranties, express or implied, including all implied warranties of + * merchantability, fitness for a particular purpose and non-infringement of + * intellectual property rights. NXP Semiconductors assumes no responsibility + * or liability for the use of the software, conveys no license or rights under any + * patent, copyright, mask work right, or any other intellectual property rights in + * or to any products. NXP Semiconductors reserves the right to make changes + * in the software without notification. NXP Semiconductors also makes no + * representation or warranty that such application will be suitable for the + * specified use without further testing or modification. + * + * @par + * Permission to use, copy, modify, and distribute this software and its + * documentation is hereby granted, under NXP Semiconductors' and its + * licensor's relevant copyrights in the software, without fee, provided that it + * is used in conjunction with NXP Semiconductors microcontrollers. This + * copyright, permission, and disclaimer notice must appear in all copies of + * this code. + */ + +#ifndef __UART_18XX_43XX_H_ +#define __UART_18XX_43XX_H_ + +#include "chip.h" + +#ifdef __cplusplus +extern "C" { +#endif + +/** @defgroup 18XX_43XX CHIP: LPC18xx/43xx UART Driver + * @ingroup CHIP_18XX_43XX_Drivers + * @{ + */ + +/** + * @brief Configure data width, parity mode and stop bits + * @param UARTx : Pointer to selected UARTx peripheral + * @param Databits : UART Data width, should be: + * UART_DATABIT_5: UART 5 bit data mode + * UART_DATABIT_6: UART 6 bit data mode + * UART_DATABIT_7: UART 7 bit data mode + * UART_DATABIT_8: UART 8 bit data mode + * @param Parity : UART Parity mode, should be: + * UART_PARITY_NONE: No parity + * UART_PARITY_ODD: Odd parity + * UART_PARITY_EVEN: Even parity + * UART_PARITY_SP_1: Forced "1" stick parity + * UART_PARITY_SP_0: Forced "0" stick parity + * @param Stopbits : Number of stop bits, should be: + * UART_STOPBIT_1: One Stop Bit Select + * UART_STOPBIT_2: Two Stop Bits Select + * @return Nothing + */ +STATIC INLINE void Chip_UART_ConfigData(LPC_USART_Type *UARTx, + UART_DATABIT_Type Databits, + UART_PARITY_Type Parity, + UART_STOPBIT_Type Stopbits) +{ + IP_UART_ConfigData(UARTx, Databits, Parity, Stopbits); +} + +/** + * @brief Send a block of data via UART peripheral + * @param UARTx : Pointer to selected UARTx peripheral + * @param txbuf : Pointer to Transmit buffer + * @param buflen : Length of Transmit buffer + * @param flag : Flag used in UART transfer, should be NONE_BLOCKING or BLOCKING + * @return Number of bytes sent + */ +STATIC INLINE uint32_t Chip_UART_Send(LPC_USART_Type *UARTx, uint8_t *txbuf, uint32_t buflen, TRANSFER_BLOCK_Type flag) +{ + return IP_UART_Send(UARTx, txbuf, buflen, flag); +} + +/** + * @brief Receive a block of data via UART peripheral + * @param UARTx : Pointer to selected UARTx peripheral + * @param rxbuf : Pointer to Received buffer + * @param buflen : Length of Received buffer + * @param flag : Flag mode, should be NONE_BLOCKING or BLOCKING + * @return Number of bytes received + */ +STATIC INLINE uint32_t Chip_UART_Receive(LPC_USART_Type *UARTx, + uint8_t *rxbuf, + uint32_t buflen, + TRANSFER_BLOCK_Type flag) +{ + return IP_UART_Receive(UARTx, rxbuf, buflen, flag); +} + +/* UART FIFO functions ----------------------------------------------------------*/ +/** + * @brief Configure FIFO function on selected UART peripheral + * @param UARTx : Pointer to selected UARTx peripheral + * @param FIFOCfg : Pointer to a UART_FIFO_CFG_Type Structure that contains specified information about FIFO configuration + * @return Nothing + */ +STATIC INLINE void Chip_UART_FIFOConfig(LPC_USART_Type *UARTx, UART_FIFO_CFG_Type *FIFOCfg) +{ + IP_UART_FIFOConfig(UARTx, FIFOCfg); +} + +/** + * @brief Fills each UART_FIFOInitStruct member with its default value: + * - FIFO_DMAMode = DISABLE + * - FIFO_Level = UART_FIFO_TRGLEV0 + * - FIFO_ResetRxBuf = ENABLE + * - FIFO_ResetTxBuf = ENABLE + * - FIFO_State = ENABLE + * @param UART_FIFOInitStruct : Pointer to a UART_FIFO_CFG_Type structure which will be initialized. + * @return Nothing + */ +STATIC INLINE void Chip_UART_FIFOConfigStructInit(UART_FIFO_CFG_Type *UART_FIFOInitStruct) +{ + IP_UART_FIFOConfigStructInit(UART_FIFOInitStruct); +} + +/* UART operate functions -------------------------------------------------------*/ +/** + * @brief Enable or disable specified UART interrupt. + * @param UARTx : Pointer to selected UARTx peripheral + * @param UARTIntCfg : Specifies the interrupt flag, should be one of the following: + * - UART_INTCFG_RBR : RBR Interrupt enable + * - UART_INTCFG_THRE : THR Interrupt enable + * - UART_INTCFG_RLS : RX line status interrupt enable + * - UART1_INTCFG_MS : Modem status interrupt enable (UART1 only) + * - UART1_INTCFG_CTS : CTS1 signal transition interrupt enable (UART1 only) + * - UART_INTCFG_ABEO : Enables the end of auto-baud interrupt + * - UART_INTCFG_ABTO : Enables the auto-baud time-out interrupt + * @param NewState : New state of specified UART interrupt type, should be ENALBE or DISALBE + * @return Nothing + */ +STATIC INLINE void Chip_UART_IntConfig(LPC_USART_Type *UARTx, UART_INT_Type UARTIntCfg, FunctionalState NewState) +{ + IP_UART_IntConfig(UARTx, UARTIntCfg, NewState); +} + +/** + * @brief Get Source Interrupt + * @param UARTx : Pointer to selected UARTx peripheral + * @return Return the value of IIR register + */ +STATIC INLINE uint32_t Chip_UART_IntGetStatus(LPC_USART_Type *UARTx) +{ + return IP_UART_IntGetStatus(UARTx); +} + +/** + * @brief Get current value of Line Status register in UART peripheral. + * @param UARTx : Pointer to selected UARTx peripheral + * @return Current value of Line Status register in UART peripheral + */ +STATIC INLINE uint8_t Chip_UART_GetLineStatus(LPC_USART_Type *UARTx) +{ + return IP_UART_GetLineStatus(UARTx); +} + +/** + * @brief Check whether if UART is busy or not + * @param UARTx : Pointer to selected UARTx peripheral + * @return RESET if UART is not busy, otherwise return SET. + */ +STATIC INLINE FlagStatus Chip_UART_CheckBusy(LPC_USART_Type *UARTx) +{ + return IP_UART_CheckBusy(UARTx); +} + +/** + * @brief Force BREAK character on UART line, output pin UARTx TXD is forced to logic 0 + * @param UARTx : Pointer to selected UARTx peripheral + * @return Nothing + */ +STATIC INLINE void Chip_UART_ForceBreak(LPC_USART_Type *UARTx) +{ + IP_UART_ForceBreak(UARTx); +} + +/** + * @brief Transmit a single data through UART peripheral + * @param UARTx : Pointer to selected UARTx peripheral + * @param Data : Data to transmit (must be 8-bit long) + * @return Status, should be ERROR (THR is empty, ready to send) or SUCCESS (THR is not empty) + */ +STATIC INLINE Status Chip_UART_SendByte(LPC_USART_Type *UARTx, uint8_t Data) +{ + return IP_UART_SendByte(UARTx, Data); +} + +/** + * @brief Receive a single data from UART peripheral + * @param UARTx : Pointer to selected UARTx peripheral + * @param *Data : Pointer to Data to receive (must be 8-bit long) + * @return Status, should be ERROR or (Receive data is ready) or SUCCESS (Receive data is not ready yet) + */ +STATIC INLINE Status Chip_UART_ReceiveByte(LPC_USART_Type *UARTx, uint8_t *Data) +{ + return IP_UART_ReceiveByte(UARTx, Data); +} + +/** + * @brief Initializes the UARTx peripheral. + * @param UARTx : Pointer to selected UARTx peripheral + * @return Nothing + */ +void Chip_UART_Init(LPC_USART_Type *UARTx); + +/** + * @brief De-initializes the UARTx peripheral. + * @param UARTx : Pointer to selected UARTx peripheral + * @return Nothing + */ +void Chip_UART_DeInit(LPC_USART_Type *UARTx); + +/** + * @brief Determines best dividers to get a target baud rate + * @param UARTx : Pointer to selected UARTx peripheral + * @param baudrate : Desired UART baud rate. + * @return Error status, could be SUCCESS or ERROR + */ +Status Chip_UART_SetBaud(LPC_USART_Type *UARTx, uint32_t baudrate); + +/** + * @brief Enable/Disable transmission on UART TxD pin + * @param UARTx : Pointer to selected UARTx peripheral + * @param NewState : New State of Tx transmission function, should be ENABLE or DISABLE + * @return Nothing + */ +void Chip_UART_TxCmd(LPC_USART_Type *UARTx, FunctionalState NewState); + +/** + * @brief Get Interrupt Stream Status + * @param UARTx : Pointer to selected UARTx peripheral + * @return Return the interrupt status, should be: + * - UART_ERROR + * - READY_TO_RECEIVE + * - READY_TO_SEND + */ +UART_Int_Status Chip_UART_GetIntStatus(LPC_USART_Type *UARTx); + +/** + * @brief Uart interrupt service routine (chip layer) + * @param UARTx : Pointer to selected UARTx peripheral + * @return Nothing + */ +void Chip_UART_Interrupt_Handler (LPC_USART_Type *UARTx); + +/** + * @brief UART transmit function for interrupt mode (using ring buffers) + * @param UARTx : Selected UART peripheral used to send data, should be UART0 + * @param txbuf : Pointer to Transmit buffer + * @param buflen : Length of Transmit buffer + * @return Number of bytes actually sent to the ring buffer + */ +uint32_t Chip_UART_Interrupt_Transmit(LPC_USART_Type *UARTx, uint8_t *txbuf, uint8_t buflen); + +/** + * @brief UART read function for interrupt mode (using ring buffers) + * @param UARTx : Selected UART peripheral used to send data, should be UART0 + * @param rxbuf : Pointer to Received buffer + * @param buflen : Length of Received buffer + * @return Number of bytes actually read from the ring buffer + */ +uint32_t Chip_UART_Interrupt_Receive(LPC_USART_Type *UARTx, uint8_t *rxbuf, uint8_t buflen); + +/** + * @brief Reset Tx and Rx ring buffer (head and tail) + * @return Nothing + */ +void Chip_UART_InitRingBuffer(void); + +/** + * @} + */ +#ifdef __cplusplus +} +#endif +#endif /* __UART_18XX_43XX_H_ */ diff --git a/bsp/xplorer4330/libraries/lpc_chip/chip_18xx_43xx/wwdt_18xx_43xx.c b/bsp/xplorer4330/libraries/lpc_chip/chip_18xx_43xx/wwdt_18xx_43xx.c new file mode 100644 index 0000000000..8b7ccdf3c2 --- /dev/null +++ b/bsp/xplorer4330/libraries/lpc_chip/chip_18xx_43xx/wwdt_18xx_43xx.c @@ -0,0 +1,70 @@ +/* + * @brief LPC18xx/43xx WWDT chip driver + * + * @note + * Copyright(C) NXP Semiconductors, 2012 + * All rights reserved. + * + * @par + * Software that is described herein is for illustrative purposes only + * which provides customers with programming information regarding the + * LPC products. This software is supplied "AS IS" without any warranties of + * any kind, and NXP Semiconductors and its licensor disclaim any and + * all warranties, express or implied, including all implied warranties of + * merchantability, fitness for a particular purpose and non-infringement of + * intellectual property rights. NXP Semiconductors assumes no responsibility + * or liability for the use of the software, conveys no license or rights under any + * patent, copyright, mask work right, or any other intellectual property rights in + * or to any products. NXP Semiconductors reserves the right to make changes + * in the software without notification. NXP Semiconductors also makes no + * representation or warranty that such application will be suitable for the + * specified use without further testing or modification. + * + * @par + * Permission to use, copy, modify, and distribute this software and its + * documentation is hereby granted, under NXP Semiconductors' and its + * licensor's relevant copyrights in the software, without fee, provided that it + * is used in conjunction with NXP Semiconductors microcontrollers. This + * copyright, permission, and disclaimer notice must appear in all copies of + * this code. + */ + +#include "wwdt_18xx_43xx.h" + +/***************************************************************************** + * Private types/enumerations/variables + ****************************************************************************/ + +/***************************************************************************** + * Public types/enumerations/variables + ****************************************************************************/ + +/***************************************************************************** + * Private functions + ****************************************************************************/ + +/***************************************************************************** + * Public functions + ****************************************************************************/ + +/* Initialize the Watchdog timer */ +void Chip_WWDT_Init(void) +{ + /* Disable watchdog */ + LPC_WWDT->MOD = 0; + LPC_WWDT->TC = 0xFF; + LPC_WWDT->WARNINT = 0xFFFF; + LPC_WWDT->WINDOW = 0xFFFFFF; +} + +/* Clear WWDT interrupt status flags */ +void Chip_WWDT_ClearStatusFlag(uint32_t status) +{ + if (status & WWDT_WDMOD_WDTOF) { + LPC_WWDT->MOD &= ~WWDT_WDMOD_WDTOF; + } + + if (status & WWDT_WDMOD_WDINT) { + LPC_WWDT->MOD |= WWDT_WDMOD_WDINT; + } +} diff --git a/bsp/xplorer4330/libraries/lpc_chip/chip_18xx_43xx/wwdt_18xx_43xx.h b/bsp/xplorer4330/libraries/lpc_chip/chip_18xx_43xx/wwdt_18xx_43xx.h new file mode 100644 index 0000000000..a37c35b17f --- /dev/null +++ b/bsp/xplorer4330/libraries/lpc_chip/chip_18xx_43xx/wwdt_18xx_43xx.h @@ -0,0 +1,191 @@ +/* + * @brief LPC18xx/43xx WWDT chip driver + * + * @note + * Copyright(C) NXP Semiconductors, 2012 + * All rights reserved. + * + * @par + * Software that is described herein is for illustrative purposes only + * which provides customers with programming information regarding the + * LPC products. This software is supplied "AS IS" without any warranties of + * any kind, and NXP Semiconductors and its licensor disclaim any and + * all warranties, express or implied, including all implied warranties of + * merchantability, fitness for a particular purpose and non-infringement of + * intellectual property rights. NXP Semiconductors assumes no responsibility + * or liability for the use of the software, conveys no license or rights under any + * patent, copyright, mask work right, or any other intellectual property rights in + * or to any products. NXP Semiconductors reserves the right to make changes + * in the software without notification. NXP Semiconductors also makes no + * representation or warranty that such application will be suitable for the + * specified use without further testing or modification. + * + * @par + * Permission to use, copy, modify, and distribute this software and its + * documentation is hereby granted, under NXP Semiconductors' and its + * licensor's relevant copyrights in the software, without fee, provided that it + * is used in conjunction with NXP Semiconductors microcontrollers. This + * copyright, permission, and disclaimer notice must appear in all copies of + * this code. + */ + +#ifndef __WWDT_18XX_43XX_H_ +#define __WWDT_18XX_43XX_H_ + +#include "chip.h" + +#ifdef __cplusplus +extern "C" { +#endif + +/** @defgroup WWDT_18XX_43XX CHIP: LPC18xx/43xx WWDT driver + * @ingroup CHIP_18XX_43XX_Drivers + * @{ + */ + +/** WDT oscillator frequency value */ +#define WDT_OSC (CGU_IRC_FREQ) + +/** WWDT interrupt enable bit */ +#define WWDT_WDMOD_WDEN ((uint32_t) (1 << 0)) +/** WWDT interrupt enable bit */ +#define WWDT_WDMOD_WDRESET ((uint32_t) (1 << 1)) +/** WWDT time out flag bit */ +#define WWDT_WDMOD_WDTOF ((uint32_t) (1 << 2)) +/** WDT Time Out flag bit */ +#define WWDT_WDMOD_WDINT ((uint32_t) (1 << 3)) +/** WWDT Protect flag bit */ +#define WWDT_WDMOD_WDPROTECT ((uint32_t) (1 << 4)) + +/** Minimum tick count for timer value and window value */ +#define WWDT_TICKS_MIN 0xFF + +/** Maximum tick count for timer value and window value */ +#define WWDT_TICKS_MAX 0xFFFFFF + +/** + * @brief Initialize the Watchdog timer + * @return None + */ +void Chip_WWDT_Init(void); + +/** + * @brief Set WDT timeout constant value used for feed + * @param timeout : WDT timeout in ticks, between WWDT_TICKS_MIN and WWDT_TICKS_MAX + * @return none + */ +STATIC INLINE void Chip_WWDT_SetTimeOut(uint32_t timeout) +{ + LPC_WWDT->TC = timeout; +} + +/** + * @brief Feed watchdog timer + * @return None + * If this function isn't called, a watchdog timer warning will occur. + * After the warning, a timeout will occur if a feed has happened. + */ +STATIC INLINE void Chip_WWDT_Feed(void) +{ + LPC_WWDT->FEED = 0xAA; + LPC_WWDT->FEED = 0x55; +} + +/** + * @brief Set WWDT warning interrupt + * @param timeout : WDT warning in ticks, between 0 and 1023 + * @return None + * This is the number of ticks after the watchdog interrupt that the + * warning interrupt will be generated. + */ +STATIC INLINE void Chip_WWDT_SetWarning(uint32_t timeout) +{ + LPC_WWDT->WARNINT = timeout; +} + +/** + * @brief Set WWDT window time + * @param timeout : WDT timeout in ticks, between WWDT_TICKS_MIN and WWDT_TICKS_MAX + * @return none + * The watchdog timer must be fed between the timeout from the Chip_WWDT_SetTimeOut() + * function and this function, with this function defining the last tick before the + * watchdog window interrupt occurs. + */ +STATIC INLINE void Chip_WWDT_SetWindow(uint32_t timeout) +{ + LPC_WWDT->WINDOW = timeout; +} + +/** + * @brief Enable watchdog timer options + * @param options : An or'ed set of options of values + * WWDT_WDMOD_WDEN, WWDT_WDMOD_WDRESET, and WWDT_WDMOD_WDPROTECT + * @return None + * You can enable more than one option at once (ie, WWDT_WDMOD_WDRESET | + * WWDT_WDMOD_WDPROTECT), but use the WWDT_WDMOD_WDEN after all other options + * are set (or unset) with no other options. + */ +STATIC INLINE void Chip_WWDT_SetOption(uint32_t options) +{ + LPC_WWDT->MOD |= options; +} + +/** + * @brief Disable/clear watchdog timer options + * @param options : An or'ed set of options of values + * WWDT_WDMOD_WDEN, WWDT_WDMOD_WDRESET, and WWDT_WDMOD_WDPROTECT + * @return None + * You can disable more than one option at once (ie, WWDT_WDMOD_WDRESET | + * WWDT_WDMOD_WDTOF). + */ +STATIC INLINE void Chip_WWDT_UnsetOption(uint32_t options) +{ + LPC_WWDT->MOD &= ~options; +} + +/** + * @brief Enable WWDT activity + * @return None + */ +STATIC INLINE void Chip_WWDT_Start(void) +{ + Chip_WWDT_SetOption(WWDT_WDMOD_WDEN); + Chip_WWDT_Feed(); +} + +/** + * @brief Read WWDT status flag + * @return Watchdog status, an Or'ed value of WWDT_WDMOD_* + */ +STATIC INLINE uint32_t Chip_WWDT_GetStatus(void) +{ + return LPC_WWDT->MOD; +} + +/** + * @brief Clear WWDT interrupt status flags + * @param flag : Or'ed value of status flag(s) that you want to clear, should be: + * - WWDT_WDMOD_WDTOF: Clear watchdog timeout flag + * - WWDT_WDMOD_WDINT: Clear watchdog warning flag + * @return None + */ +void Chip_WWDT_ClearStatusFlag(uint32_t status); + +/** + * @brief Get the current value of WDT + * @return current value of WDT + */ +STATIC INLINE uint32_t WWDT_GetCurrentCount(void) +{ + return LPC_WWDT->TV; +} + +/** + * @} + */ + +#ifdef __cplusplus +} +#endif + +#endif /* __WWDT_18XX_43XX_H_ */ diff --git a/bsp/xplorer4330/libraries/lpc_chip/chip_common/mem_tests.c b/bsp/xplorer4330/libraries/lpc_chip/chip_common/mem_tests.c new file mode 100644 index 0000000000..a1386feb91 --- /dev/null +++ b/bsp/xplorer4330/libraries/lpc_chip/chip_common/mem_tests.c @@ -0,0 +1,294 @@ +/* + * @brief Generic memory tests + * Various memory tests for testing external memory integrity. Includes + * inverse address, walking bit, and pattern tests. + * + * @note + * Copyright(C) NXP Semiconductors, 2012 + * All rights reserved. + * + * @par + * Software that is described herein is for illustrative purposes only + * which provides customers with programming information regarding the + * LPC products. This software is supplied "AS IS" without any warranties of + * any kind, and NXP Semiconductors and its licensor disclaim any and + * all warranties, express or implied, including all implied warranties of + * merchantability, fitness for a particular purpose and non-infringement of + * intellectual property rights. NXP Semiconductors assumes no responsibility + * or liability for the use of the software, conveys no license or rights under any + * patent, copyright, mask work right, or any other intellectual property rights in + * or to any products. NXP Semiconductors reserves the right to make changes + * in the software without notification. NXP Semiconductors also makes no + * representation or warranty that such application will be suitable for the + * specified use without further testing or modification. + * + * @par + * Permission to use, copy, modify, and distribute this software and its + * documentation is hereby granted, under NXP Semiconductors' and its + * licensor's relevant copyrights in the software, without fee, provided that it + * is used in conjunction with NXP Semiconductors microcontrollers. This + * copyright, permission, and disclaimer notice must appear in all copies of + * this code. + */ + +#include "mem_tests.h" + +/***************************************************************************** + * Private types/enumerations/variables + ****************************************************************************/ + +/***************************************************************************** + * Public types/enumerations/variables + ****************************************************************************/ + +/***************************************************************************** + * Private functions + ****************************************************************************/ + +/***************************************************************************** + * Public functions + ****************************************************************************/ + +/* Walking 0 memory test */ +bool mem_test_walking0(MEM_TEST_SETUP_T *pMemSetup) +{ + int i = 0; + uint32_t fbytes = pMemSetup->bytes, *addr = pMemSetup->start_addr; + + /* Must be 32-bit algined */ + if ((((uint32_t) addr & 0x3) != 0) || ((fbytes & 0x3) != 0)) { + return false; + } + + /* Write walking 0 pattern */ + while (fbytes > 0) { + *addr = ~(1 << i); + + addr++; + fbytes -= 4; + i++; + if (i >= 32) { + i = 0; + } + } + + /* Verify walking 0 pattern */ + i = 0; + fbytes = pMemSetup->bytes; + addr = pMemSetup->start_addr; + while (fbytes > 0) { + if (*addr != ~(1 << i)) { + pMemSetup->fail_addr = addr; + pMemSetup->is_val = *addr; + pMemSetup->ex_val = ~(1 << i); + return false; + } + + addr++; + fbytes -= 4; + i++; + if (i >= 32) { + i = 0; + } + } + + return true; +} + +/* Walking 1 memory test */ +bool mem_test_walking1(MEM_TEST_SETUP_T *pMemSetup) +{ + int i = 0; + uint32_t fbytes = pMemSetup->bytes, *addr = pMemSetup->start_addr; + + /* Must be 32-bit algined */ + if ((((uint32_t) addr & 0x3) != 0) || ((fbytes & 0x3) != 0)) { + return false; + } + + /* Write walking 1 pattern */ + while (fbytes > 0) { + *addr = (1 << i); + + addr++; + fbytes -= 4; + i++; + if (i >= 32) { + i = 0; + } + } + + /* Verify walking 1 pattern */ + i = 0; + fbytes = pMemSetup->bytes; + addr = pMemSetup->start_addr; + while (fbytes > 0) { + if (*addr != (1 << i)) { + pMemSetup->fail_addr = addr; + pMemSetup->is_val = *addr; + pMemSetup->ex_val = (1 << i); + return false; + } + + addr++; + fbytes -= 4; + i++; + if (i >= 32) { + i = 0; + } + } + + return true; +} + +/* Address memory test */ +bool mem_test_address(MEM_TEST_SETUP_T *pMemSetup) +{ + uint32_t fbytes = pMemSetup->bytes, *addr = pMemSetup->start_addr; + + /* Must be 32-bit algined */ + if ((((uint32_t) addr & 0x3) != 0) || ((fbytes & 0x3) != 0)) { + return false; + } + + /* Write address for memory location */ + while (fbytes > 0) { + *addr = (uint32_t) addr; + + addr++; + fbytes -= 4; + } + + /* Verify address for memory location */ + fbytes = pMemSetup->bytes; + addr = pMemSetup->start_addr; + while (fbytes > 0) { + if (*addr != (uint32_t) addr) { + pMemSetup->fail_addr = addr; + pMemSetup->is_val = *addr; + pMemSetup->ex_val = (uint32_t) addr; + return false; + } + + addr++; + fbytes -= 4; + } + + return true; +} + +/* Inverse address memory test */ +bool mem_test_invaddress(MEM_TEST_SETUP_T *pMemSetup) +{ + uint32_t fbytes = pMemSetup->bytes, *addr = pMemSetup->start_addr; + + /* Must be 32-bit algined */ + if ((((uint32_t) addr & 0x3) != 0) || ((fbytes & 0x3) != 0)) { + return false; + } + + /* Write inverse address for memory location */ + while (fbytes > 0) { + *addr = ~(uint32_t) addr; + + addr++; + fbytes -= 4; + } + + /* Verify inverse address for memory location */ + fbytes = pMemSetup->bytes; + addr = pMemSetup->start_addr; + while (fbytes > 0) { + if (*addr != ~(uint32_t) addr) { + pMemSetup->fail_addr = addr; + pMemSetup->is_val = *addr; + pMemSetup->ex_val = ~(uint32_t) addr; + return false; + } + + addr++; + fbytes -= 4; + } + + return true; +} + +/* Pattern memory test */ +bool mem_test_pattern(MEM_TEST_SETUP_T *pMemSetup) +{ + uint32_t fbytes = pMemSetup->bytes, *addr = pMemSetup->start_addr; + uint32_t pattern = 0x55AA55AA; + + /* Must be 32-bit algined */ + if ((((uint32_t) addr & 0x3) != 0) || ((fbytes & 0x3) != 0)) { + return false; + } + + /* Write pattern for memory location */ + while (fbytes > 0) { + *addr = pattern; + + pattern = ~pattern; + addr++; + fbytes -= 4; + } + + /* Verify pattern for memory location */ + pattern = 0x55AA55AA; + fbytes = pMemSetup->bytes; + addr = pMemSetup->start_addr; + while (fbytes > 0) { + if (*addr != pattern) { + pMemSetup->fail_addr = addr; + pMemSetup->is_val = *addr; + pMemSetup->ex_val = pattern; + return false; + } + + pattern = ~pattern; + addr++; + fbytes -= 4; + } + + return true; +} + +/* Pattern memory test with seed and increment value */ +bool mem_test_pattern_seed(MEM_TEST_SETUP_T *pMemSetup, uint32_t seed, uint32_t incr) +{ + uint32_t fbytes = pMemSetup->bytes, *addr = pMemSetup->start_addr; + uint32_t pattern = seed; + + /* Must be 32-bit algined */ + if ((((uint32_t) addr & 0x3) != 0) || ((fbytes & 0x3) != 0)) { + return false; + } + + /* Write pattern for memory location */ + while (fbytes > 0) { + *addr = pattern; + + pattern += incr; + addr++; + fbytes -= 4; + } + + /* Verify pattern for memory location */ + pattern = seed; + fbytes = pMemSetup->bytes; + addr = pMemSetup->start_addr; + while (fbytes > 0) { + if (*addr != pattern) { + pMemSetup->fail_addr = addr; + pMemSetup->is_val = *addr; + pMemSetup->ex_val = pattern; + return false; + } + + pattern += incr; + addr++; + fbytes -= 4; + } + + return true; +} diff --git a/bsp/xplorer4330/libraries/lpc_chip/chip_common/mem_tests.h b/bsp/xplorer4330/libraries/lpc_chip/chip_common/mem_tests.h new file mode 100644 index 0000000000..9136fc0493 --- /dev/null +++ b/bsp/xplorer4330/libraries/lpc_chip/chip_common/mem_tests.h @@ -0,0 +1,116 @@ +/* + * @brief Generic memory tests + * Various memory tests for testing external memory integrity. Includes + * inverse address, walking bit, and pattern tests. + * + * @note + * Copyright(C) NXP Semiconductors, 2012 + * All rights reserved. + * + * @par + * Software that is described herein is for illustrative purposes only + * which provides customers with programming information regarding the + * LPC products. This software is supplied "AS IS" without any warranties of + * any kind, and NXP Semiconductors and its licensor disclaim any and + * all warranties, express or implied, including all implied warranties of + * merchantability, fitness for a particular purpose and non-infringement of + * intellectual property rights. NXP Semiconductors assumes no responsibility + * or liability for the use of the software, conveys no license or rights under any + * patent, copyright, mask work right, or any other intellectual property rights in + * or to any products. NXP Semiconductors reserves the right to make changes + * in the software without notification. NXP Semiconductors also makes no + * representation or warranty that such application will be suitable for the + * specified use without further testing or modification. + * + * @par + * Permission to use, copy, modify, and distribute this software and its + * documentation is hereby granted, under NXP Semiconductors' and its + * licensor's relevant copyrights in the software, without fee, provided that it + * is used in conjunction with NXP Semiconductors microcontrollers. This + * copyright, permission, and disclaimer notice must appear in all copies of + * this code. + */ + +#ifndef __MEM_TESTS_H_ +#define __MEM_TESTS_H_ + +#include "lpc_types.h" + +/** @defgroup CHIP_Memory_Tests CHIP: Various RAM memory tests + * @ingroup CHIP_Common + * @{ + */ + +/** + * @brief Memory test address/size and result structure + */ +typedef struct { + uint32_t *start_addr; /*!< Starting address for memory test */ + uint32_t bytes; /*!< Size in bytes for memory test */ + uint32_t *fail_addr; /*!< Failed address of test (returned only if failed) */ + uint32_t is_val; /*!< Failed value of test (returned only if failed) */ + uint32_t ex_val; /*!< Expected value of test (returned only if failed) */ +} MEM_TEST_SETUP_T; + +/** + * @brief Walking 0 memory test + * @param pMemSetup : Memory test setup (and returned results) + * @return true if the test passed, or false on failure + * Writes a shifting 0 bit pattern to the entire memory range and + * verifies the result after all memory locations are written + */ +bool mem_test_walking0(MEM_TEST_SETUP_T *pMemSetup); + +/** + * @brief Walking 1 memory test + * @param pMemSetup : Memory test setup (and returned results) + * @return true if the test passed, or false on failure + * Writes a shifting 1 bit pattern to the entire memory range and + * verifies the result after all memory locations are written + */ +bool mem_test_walking1(MEM_TEST_SETUP_T *pMemSetup); + +/** + * @brief Address memory test + * @param pMemSetup : Memory test setup (and returned results) + * @return true if the test passed, or false on failure + * Writes the address to each memory location and verifies the + * result after all memory locations are written + */ +bool mem_test_address(MEM_TEST_SETUP_T *pMemSetup); + +/** + * @brief Inverse address memory test + * @param pMemSetup : Memory test setup (and returned results) + * @return true if the test passed, or false on failure + * Writes the inverse address to each memory location and verifies the + * result after all memory locations are written + */ +bool mem_test_invaddress(MEM_TEST_SETUP_T *pMemSetup); + +/** + * @brief Pattern memory test + * @param pMemSetup : Memory test setup (and returned results) + * @return true if the test passed, or false on failure + * Writes the an alternating 0x55/0xAA pattern to each memory location + * and verifies the result after all memory locations are written + */ +bool mem_test_pattern(MEM_TEST_SETUP_T *pMemSetup); + +/** + * @brief Pattern memory test with seed and increment value + * @param pMemSetup : Memory test setup (and returned results) + * @param seed : Initial seed value for test + * @param incr : Increment value for each memory location + * @return true if the test passed, or false on failure + * Writes the an alternating pattern to each memory location based on a + * passed seedn and increment value and verifies the result after all + * memory locations are written + */ +bool mem_test_pattern_seed(MEM_TEST_SETUP_T *pMemSetup, uint32_t seed, uint32_t incr); + +/** + * @} + */ + +#endif /* __MEM_TESTS_H_ */ diff --git a/bsp/xplorer4330/libraries/lpc_chip/chip_common/ring_buffer.c b/bsp/xplorer4330/libraries/lpc_chip/chip_common/ring_buffer.c new file mode 100644 index 0000000000..efe87864bc --- /dev/null +++ b/bsp/xplorer4330/libraries/lpc_chip/chip_common/ring_buffer.c @@ -0,0 +1,168 @@ +/* + * @brief Common ring buffer support functions + * + * @note + * Copyright(C) NXP Semiconductors, 2012 + * All rights reserved. + * + * @par + * Software that is described herein is for illustrative purposes only + * which provides customers with programming information regarding the + * LPC products. This software is supplied "AS IS" without any warranties of + * any kind, and NXP Semiconductors and its licensor disclaim any and + * all warranties, express or implied, including all implied warranties of + * merchantability, fitness for a particular purpose and non-infringement of + * intellectual property rights. NXP Semiconductors assumes no responsibility + * or liability for the use of the software, conveys no license or rights under any + * patent, copyright, mask work right, or any other intellectual property rights in + * or to any products. NXP Semiconductors reserves the right to make changes + * in the software without notification. NXP Semiconductors also makes no + * representation or warranty that such application will be suitable for the + * specified use without further testing or modification. + * + * @par + * Permission to use, copy, modify, and distribute this software and its + * documentation is hereby granted, under NXP Semiconductors' and its + * licensor's relevant copyrights in the software, without fee, provided that it + * is used in conjunction with NXP Semiconductors microcontrollers. This + * copyright, permission, and disclaimer notice must appear in all copies of + * this code. + */ + +#include "ring_buffer.h" + +/***************************************************************************** + * Private types/enumerations/variables + ****************************************************************************/ + +/***************************************************************************** + * Public types/enumerations/variables + ****************************************************************************/ + +/***************************************************************************** + * Private functions + ****************************************************************************/ + +/***************************************************************************** + * Public functions + ****************************************************************************/ + +/* Initialize ring buffer */ +void RingBuffer_Init(RINGBUFF_T *RingBuff, void *buffer, int itemSize, int count) +{ + RingBuff->bufferBase = RingBuff->bufferIn = RingBuff->bufferOut = buffer; + RingBuff->bufferLast = RingBuff->bufferBase + (itemSize * count); + RingBuff->count = count; + RingBuff->itemSize = itemSize; + RingBuff->used = 0; +} + +/* Return empty status of ring buffer */ +bool RingBuffer_Insert8(RINGBUFF_T *RingBuff, uint8_t data8) +{ + bool full = RingBuffer_IsFull(RingBuff); + + if (!full) { + *RingBuff->bufferIn = data8; + RingBuff->used++; + RingBuff->bufferIn++; + if (RingBuff->bufferIn >= RingBuff->bufferLast) { + RingBuff->bufferIn = RingBuff->bufferBase; + } + } + + return (bool) !full; +} + +/* Insert 16-bit value in ring buffer */ +bool RingBuffer_Insert16(RINGBUFF_T *RingBuff, uint16_t data16) +{ + bool full = RingBuffer_IsFull(RingBuff); + + if (!full) { + uint16_t *buff16 = (uint16_t *) RingBuff->bufferIn; + *buff16 = data16; + RingBuff->used++; + buff16++; + RingBuff->bufferIn = (uint8_t *) buff16; + if (RingBuff->bufferIn >= RingBuff->bufferLast) { + RingBuff->bufferIn = RingBuff->bufferBase; + } + } + + return (bool) !full; +} + +/* Insert 32-bit value in ring buffer */ +bool RingBuffer_Insert32(RINGBUFF_T *RingBuff, uint32_t data32) +{ + bool full = RingBuffer_IsFull(RingBuff); + + if (!full) { + uint32_t *buff32 = (uint32_t *) RingBuff->bufferIn; + *buff32 = data32; + RingBuff->used++; + buff32++; + RingBuff->bufferIn = (uint8_t *) buff32; + if (RingBuff->bufferIn >= RingBuff->bufferLast) { + RingBuff->bufferIn = RingBuff->bufferBase; + } + } + + return (bool) !full; +} + +/* Pop a 8-bit value from the ring buffer */ +bool RingBuffer_Pop8(RINGBUFF_T *RingBuff, uint8_t *data8) +{ + bool empty = RingBuffer_IsEmpty(RingBuff); + + if (!empty) { + *data8 = *RingBuff->bufferOut; + RingBuff->used--; + RingBuff->bufferOut++; + if (RingBuff->bufferOut >= RingBuff->bufferLast) { + RingBuff->bufferOut = RingBuff->bufferBase; + } + } + + return (bool) !empty; +} + +/* Pop a 16-bit value from the ring buffer */ +bool RingBuffer_Pop16(RINGBUFF_T *RingBuff, uint16_t *data16) +{ + bool empty = RingBuffer_IsEmpty(RingBuff); + + if (!empty) { + uint16_t *buff16 = (uint16_t *) RingBuff->bufferOut; + *data16 = *buff16; + RingBuff->used--; + buff16++; + RingBuff->bufferOut = (uint8_t *) buff16; + if (RingBuff->bufferOut >= RingBuff->bufferLast) { + RingBuff->bufferOut = RingBuff->bufferBase; + } + } + + return (bool) !empty; +} + +/* Pop a 32-bit value from the ring buffer */ +bool RingBuffer_Pop32(RINGBUFF_T *RingBuff, uint32_t *data32) +{ + bool empty = RingBuffer_IsEmpty(RingBuff); + + if (!empty) { + uint32_t *buff32 = (uint32_t *) RingBuff->bufferOut; + *data32 = *buff32; + RingBuff->used--; + data32++; + RingBuff->bufferOut = (uint8_t *) data32; + if (RingBuff->bufferOut >= RingBuff->bufferLast) { + RingBuff->bufferOut = RingBuff->bufferBase; + } + } + + return (bool) !empty; +} diff --git a/bsp/xplorer4330/libraries/lpc_chip/chip_common/ring_buffer.h b/bsp/xplorer4330/libraries/lpc_chip/chip_common/ring_buffer.h new file mode 100644 index 0000000000..3d4c506012 --- /dev/null +++ b/bsp/xplorer4330/libraries/lpc_chip/chip_common/ring_buffer.h @@ -0,0 +1,143 @@ +/* + * @brief Common ring buffer support functions + * + * @note + * Copyright(C) NXP Semiconductors, 2012 + * All rights reserved. + * + * @par + * Software that is described herein is for illustrative purposes only + * which provides customers with programming information regarding the + * LPC products. This software is supplied "AS IS" without any warranties of + * any kind, and NXP Semiconductors and its licensor disclaim any and + * all warranties, express or implied, including all implied warranties of + * merchantability, fitness for a particular purpose and non-infringement of + * intellectual property rights. NXP Semiconductors assumes no responsibility + * or liability for the use of the software, conveys no license or rights under any + * patent, copyright, mask work right, or any other intellectual property rights in + * or to any products. NXP Semiconductors reserves the right to make changes + * in the software without notification. NXP Semiconductors also makes no + * representation or warranty that such application will be suitable for the + * specified use without further testing or modification. + * + * @par + * Permission to use, copy, modify, and distribute this software and its + * documentation is hereby granted, under NXP Semiconductors' and its + * licensor's relevant copyrights in the software, without fee, provided that it + * is used in conjunction with NXP Semiconductors microcontrollers. This + * copyright, permission, and disclaimer notice must appear in all copies of + * this code. + */ + +#ifndef __RING_BUFFER_H_ +#define __RING_BUFFER_H_ + +#include "lpc_types.h" + +/** @defgroup Ring_Buffer CHIP: Simple ring buffer implementation + * @ingroup CHIP_Common + * @{ + */ + +/** + * @brief Ring buffer structure + */ +typedef struct { + uint8_t *bufferBase, *bufferLast; + uint8_t *bufferIn, *bufferOut; + int count, used, itemSize; +} RINGBUFF_T; + +/** + * @brief Initialize ring buffer + * @param RingBuff : Pointer to ring buffer to initialize + * @param buffer : Pointer to buffer to associate with RingBuff + * @param itemSize : Size of each buffer item size (1, 2 or 4 bytes) + * @param count : Size of ring buffer + * @return Nothing + */ +void RingBuffer_Init(RINGBUFF_T *RingBuff, void *buffer, int itemSize, int count); + +/** + * @brief Return number of items in the ring buffer + * @param RingBuff : Pointer to ring buffer + * @return Number of items in the ring buffer + */ +STATIC INLINE int RingBuffer_GetCount(RINGBUFF_T *RingBuff) +{ + return RingBuff->used; +} + +/** + * @brief Return number of items in the ring buffer + * @param RingBuff : Pointer to ring buffer + * @return true if the ring buffer is full, otherwise false + */ +STATIC INLINE bool RingBuffer_IsFull(RINGBUFF_T *RingBuff) +{ + return (bool) (RingBuff->used >= RingBuff->count); +} + +/** + * @brief Return empty status of ring buffer + * @param RingBuff : Pointer to ring buffer + * @return true if the ring buffer is empty, otherwise false + */ +STATIC INLINE bool RingBuffer_IsEmpty(RINGBUFF_T *RingBuff) +{ + return (bool) (RingBuff->used == 0); +} + +/** + * @brief Insert 8-bit value in ring buffer + * @param RingBuff : Pointer to ring buffer + * @param data8 : Byte to insert in ring buffer + * @return true if a valid byte was inserted, or false if the ring buffer was full + */ +bool RingBuffer_Insert8(RINGBUFF_T *RingBuff, uint8_t data8); + +/** + * @brief Insert 16-bit value in ring buffer + * @param RingBuff : Pointer to ring buffer + * @param data16 : 16-bit value to insert in ring buffer + * @return true if valid data was inserted, or false if the ring buffer was full + */ +bool RingBuffer_Insert16(RINGBUFF_T *RingBuff, uint16_t data16); + +/** + * @brief Insert 32-bit value in ring buffer + * @param RingBuff : Pointer to ring buffer + * @param data32 : 32-bit value to insert in ring buffer + * @return true if valid data was inserted, or false if the ring buffer was full + */ +bool RingBuffer_Insert32(RINGBUFF_T *RingBuff, uint32_t data32); + +/** + * @brief Pop a 8-bit value from the ring buffer + * @param RingBuff : Pointer to ring buffer + * @param data8 : Pointer to where to place value + * @return true if a valid byte was popped, or false if the ring buffer was empty + */ +bool RingBuffer_Pop8(RINGBUFF_T *RingBuff, uint8_t *data8); + +/** + * @brief Pop a 16-bit value from the ring buffer + * @param RingBuff : Pointer to ring buffer + * @param data16 : Pointer to where to place value + * @return true if a valid byte was popped, or false if the ring buffer was empty + */ +bool RingBuffer_Pop16(RINGBUFF_T *RingBuff, uint16_t *data16); + +/** + * @brief Pop a 32-bit value from the ring buffer + * @param RingBuff : Pointer to ring buffer + * @param data32 : Pointer to where to place value + * @return true if a valid byte was popped, or false if the ring buffer was empty + */ +bool RingBuffer_Pop32(RINGBUFF_T *RingBuff, uint32_t *data32); + +/** + * @} + */ + +#endif /* __RING_BUFFER_H_ */ diff --git a/bsp/xplorer4330/libraries/lpc_ip/SConscript b/bsp/xplorer4330/libraries/lpc_ip/SConscript new file mode 100644 index 0000000000..ae57400ecb --- /dev/null +++ b/bsp/xplorer4330/libraries/lpc_ip/SConscript @@ -0,0 +1,9 @@ +from building import * + +cwd = GetCurrentDir() +src = Glob('*.c') +CPPPATH = [cwd] + +group = DefineGroup('lpc_ip', src, depend = [], CPPPATH = CPPPATH) + +Return('group') diff --git a/bsp/xplorer4330/libraries/lpc_ip/adc_001.c b/bsp/xplorer4330/libraries/lpc_ip/adc_001.c new file mode 100644 index 0000000000..8a095b72a3 --- /dev/null +++ b/bsp/xplorer4330/libraries/lpc_ip/adc_001.c @@ -0,0 +1,170 @@ +/* + * @brief ADC Registers and control functions + * + * @note + * Copyright(C) NXP Semiconductors, 2012 + * All rights reserved. + * + * @par + * Software that is described herein is for illustrative purposes only + * which provides customers with programming information regarding the + * LPC products. This software is supplied "AS IS" without any warranties of + * any kind, and NXP Semiconductors and its licensor disclaim any and + * all warranties, express or implied, including all implied warranties of + * merchantability, fitness for a particular purpose and non-infringement of + * intellectual property rights. NXP Semiconductors assumes no responsibility + * or liability for the use of the software, conveys no license or rights under any + * patent, copyright, mask work right, or any other intellectual property rights in + * or to any products. NXP Semiconductors reserves the right to make changes + * in the software without notification. NXP Semiconductors also makes no + * representation or warranty that such application will be suitable for the + * specified use without further testing or modification. + * + * @par + * Permission to use, copy, modify, and distribute this software and its + * documentation is hereby granted, under NXP Semiconductors' and its + * licensor's relevant copyrights in the software, without fee, provided that it + * is used in conjunction with NXP Semiconductors microcontrollers. This + * copyright, permission, and disclaimer notice must appear in all copies of + * this code. + */ + +#include "adc_001.h" + +/***************************************************************************** + * Private types/enumerations/variables + ****************************************************************************/ + +/***************************************************************************** + * Public types/enumerations/variables + ****************************************************************************/ + +/***************************************************************************** + * Private functions + ****************************************************************************/ + +/* Configure clock for ADC */ +static void SetClock(IP_ADC_001_Type *pADC, uint32_t adcRate, uint32_t adcPerClock, uint8_t bitsAccuracy) +{ + uint32_t temp, adcBitRate; + + /* The APB clock (PCLK_ADC0) is divided by (CLKDIV+1) to produce the clock for + A/D converter, which should be less than or equal to 4.5MHz. + A fully conversion requires (bits_accuracy+1) of these clocks. + ADC clock = PCLK_ADC0 / (CLKDIV + 1); + ADC rate = ADC clock / (bits_accuracy+1); + */ + adcBitRate = (adcRate * (11 - bitsAccuracy)); + + /* Get the round value by fomular: (2*A + B)/(2*B) */ + temp = ((adcPerClock * 2 + adcBitRate) / (adcBitRate * 2)) - 1; + + /* Enable PDN bit and clock bits */ + pADC->CR &= ~(ADC_CR_CLKDIV(0xFF) | ADC_CR_BITACC(0x07)); + pADC->CR |= ADC_CR_CLKDIV(temp) | ADC_CR_BITACC(bitsAccuracy); +} + +/***************************************************************************** + * Public functions + ****************************************************************************/ + +/* Initialize the ADC */ +void IP_ADC_Init(IP_ADC_001_Type *pADC, uint32_t adcRate, uint32_t adcPerClock, uint8_t bitsAccuracy) +{ + pADC->INTEN = 0; /* Disable all interrupts */ + pADC->CR |= ADC_CR_PDN; /* Set PDN bit for ADC*/ + SetClock(pADC, adcRate, adcPerClock, bitsAccuracy); +} + +/* Shutdown ADC */ +void IP_ADC_DeInit(IP_ADC_001_Type *pADC) +{ + pADC->INTEN = 0x00000100; + pADC->CR = 0; +} + +/* Set burst mode for ADC */ +void IP_ADC_SetBurstMode(IP_ADC_001_Type *pADC, FunctionalState NewState) +{ + if (NewState == DISABLE) { + pADC->CR &= ~ADC_CR_BURST; + } + else { + pADC->CR |= ADC_CR_BURST; + } +} + +/* Get the ADC value */ +Status IP_ADC_Get_Val(IP_ADC_001_Type *pADC, uint8_t channel, uint16_t *data) +{ + uint32_t temp; + temp = pADC->DR[channel]; + if (!ADC_DR_DONE(temp)) { + return ERROR; + } + // if(ADC_DR_OVERRUN(temp) && (pADC->CR & ADC_CR_BURST)) + // return ERROR; + *data = (uint16_t) ADC_DR_RESULT(temp); + return SUCCESS; +} + +/* Get ADC Channel status from ADC data register */ +FlagStatus IP_ADC_GetStatus(IP_ADC_001_Type *pADC, uint8_t channel, uint32_t StatusType) +{ + switch (StatusType) { + case ADC_DR_DONE_STAT: + return (pADC->STAT & (1UL << channel)) ? SET : RESET; + + case ADC_DR_OVERRUN_STAT: + channel += 8; + return (pADC->STAT & (1UL << channel)) ? SET : RESET; + + case ADC_DR_ADINT_STAT: + return pADC->STAT >> 16 ? SET : RESET; + + default: + break; + } + return RESET; +} + +/* Set the edge start condition */ +void IP_ADC_EdgeStartConfig(IP_ADC_001_Type *pADC, uint8_t edge_mode) +{ + if (edge_mode) { + pADC->CR |= ADC_CR_EDGE; + } + else { + pADC->CR &= ~ADC_CR_EDGE; + } +} + +/* Enable/Disable ADC channel number */ +void IP_ADC_SetChannelNumber(IP_ADC_001_Type *pADC, uint8_t channel, FunctionalState NewState) +{ + if (NewState == ENABLE) { + pADC->CR |= ADC_CR_CH_SEL(channel); + } + else { + pADC->CR &= ~ADC_CR_START_MASK; + pADC->CR &= ~ADC_CR_CH_SEL(channel); + } +} + +/* Set start mode for ADC */ +void IP_ADC_SetStartMode(IP_ADC_001_Type *pADC, uint8_t start_mode) +{ + pADC->CR &= ~ADC_CR_START_MASK; + pADC->CR |= ADC_CR_START_MODE_SEL((uint32_t) start_mode); +} + +/* Enable/Disable interrupt for ADC channel */ +void IP_ADC_Int_Enable(IP_ADC_001_Type *pADC, uint8_t channel, FunctionalState NewState) +{ + if (NewState == ENABLE) { + pADC->INTEN |= (1UL << channel); + } + else { + pADC->INTEN &= (~(1UL << channel)); + } +} diff --git a/bsp/xplorer4330/libraries/lpc_ip/adc_001.h b/bsp/xplorer4330/libraries/lpc_ip/adc_001.h new file mode 100644 index 0000000000..d59e330a92 --- /dev/null +++ b/bsp/xplorer4330/libraries/lpc_ip/adc_001.h @@ -0,0 +1,182 @@ +/* + * @brief ADC Registers and control functions + * + * @note + * Copyright(C) NXP Semiconductors, 2012 + * All rights reserved. + * + * @par + * Software that is described herein is for illustrative purposes only + * which provides customers with programming information regarding the + * LPC products. This software is supplied "AS IS" without any warranties of + * any kind, and NXP Semiconductors and its licensor disclaim any and + * all warranties, express or implied, including all implied warranties of + * merchantability, fitness for a particular purpose and non-infringement of + * intellectual property rights. NXP Semiconductors assumes no responsibility + * or liability for the use of the software, conveys no license or rights under any + * patent, copyright, mask work right, or any other intellectual property rights in + * or to any products. NXP Semiconductors reserves the right to make changes + * in the software without notification. NXP Semiconductors also makes no + * representation or warranty that such application will be suitable for the + * specified use without further testing or modification. + * + * @par + * Permission to use, copy, modify, and distribute this software and its + * documentation is hereby granted, under NXP Semiconductors' and its + * licensor's relevant copyrights in the software, without fee, provided that it + * is used in conjunction with NXP Semiconductors microcontrollers. This + * copyright, permission, and disclaimer notice must appear in all copies of + * this code. + */ + +#ifndef __ADC_001_H_ +#define __ADC_001_H_ + +#include "sys_config.h" +#include "cmsis.h" + +#ifdef __cplusplus +extern "C" { +#endif + +/** @defgroup IP_ADC_001 IP: 10 or 12-bit ADC register block and driver + * @ingroup IP_Drivers + * @{ + */ + +/** + * @brief 10 or 12-bit ADC register block structure + */ +typedef struct { /*!< ADCn Structure */ + __IO uint32_t CR; /*!< A/D Control Register. The AD0CR register must be written to select the operating mode before A/D conversion can occur. */ + __I uint32_t GDR; /*!< A/D Global Data Register. Contains the result of the most recent A/D conversion. */ + __I uint32_t RESERVED0; + __IO uint32_t INTEN; /*!< A/D Interrupt Enable Register. This register contains enable bits that allow the DONE flag of each A/D channel to be included or excluded from contributing to the generation of an A/D interrupt. */ + __I uint32_t DR[8]; /*!< A/D Channel Data Register. This register contains the result of the most recent conversion completed on channel n. */ + __I uint32_t STAT; /*!< A/D Status Register. This register contains DONE and OVERRUN flags for all of the A/D channels, as well as the A/D interrupt flag. */ +#if !defined(CHIP_LPC18XX) && !defined(CHIP_LPC43XX) + __IO uint32_t ADTRM; +#endif +} IP_ADC_001_Type; + +/** + * @brief ADC register support bitfields and mask + */ +#define ADC_DR_RESULT(n) ((((n) >> 6) & 0x3FF)) /*!< Mask for getting the ADC data read value */ +#define ADC_DR_DONE(n) (((n) >> 31)) /*!< Mask for reading the ADC done status */ +#define ADC_DR_OVERRUN(n) ((((n) >> 30) & (1UL))) /*!< Mask for reading the ADC overrun status */ +#define ADC_CR_CH_SEL(n) ((1UL << (n))) /*!< Selects which of the AD0.0:7 pins is (are) to be sampled and converted */ +#define ADC_CR_CLKDIV(n) ((((n) & 0xFF) << 8)) /*!< The APB clock (PCLK) is divided by (this value plus one) to produce the clock for the A/D */ +#define ADC_CR_BURST ((1UL << 16)) /*!< Repeated conversions A/D enable bit */ +#define ADC_CR_BITACC(n) ((((n) & 0x7) << 17)) /*!< Number of ADC accuracy bits */ +#define ADC_CR_PDN ((1UL << 21)) /*!< ADC convert in power down mode */ +#define ADC_CR_START_MASK ((7UL << 24)) /*!< ADC start mask bits */ +#define ADC_CR_START_MODE_SEL(SEL) ((SEL << 24)) /*!< Select Start Mode */ +#define ADC_CR_START_NOW ((1UL << 24)) /*!< Start conversion now */ +#define ADC_CR_START_CTOUT15 ((2UL << 24)) /*!< Start conversion when the edge selected by bit 27 occurs on CTOUT_15 */ +#define ADC_CR_START_CTOUT8 ((3UL << 24)) /*!< Start conversion when the edge selected by bit 27 occurs on CTOUT_8 */ +#define ADC_CR_START_ADCTRIG0 ((4UL << 24)) /*!< Start conversion when the edge selected by bit 27 occurs on ADCTRIG0 */ +#define ADC_CR_START_ADCTRIG1 ((5UL << 24)) /*!< Start conversion when the edge selected by bit 27 occurs on ADCTRIG1 */ +#define ADC_CR_START_MCOA2 ((6UL << 24)) /*!< Start conversion when the edge selected by bit 27 occurs on Motocon PWM output MCOA2 */ +#define ADC_CR_EDGE ((1UL << 27)) /*!< Start conversion on a falling edge on the selected CAP/MAT signal */ + +/** + * @brief ADC status register used for IP drivers + */ +typedef enum { + ADC_DR_DONE_STAT, /*!< ADC data register staus */ + ADC_DR_OVERRUN_STAT,/*!< ADC data overrun staus */ + ADC_DR_ADINT_STAT /*!< ADC interrupt status */ +} IP_ADC_Status; + +/** + * @brief Initialize for ADC + * @param pADC : The base of ADC peripheral on the chip + * @param adcRate : Sample rate of A/D converter + * @param adcPerClock : The APB clock + * @param bitsAccuracy : The accuracy of LSB value, should be ADC_10BITS -> ADC_3BITS + * @return Nothing + * Disable all ADC interrupts, set bit PDN, set ADC clock frequency + * This is not the sample rate, but the clock for the ADC machine, and is usually set to + * maximum. Applications may choose a lower frequency if they have high-impedance sources. + * This is because a lower clock frequency produces a longer sampling time. + */ +void IP_ADC_Init(IP_ADC_001_Type *pADC, uint32_t adcRate, uint32_t adcPerClock, uint8_t bitsAccuracy); + +/** + * @brief Shutdown ADC + * @param pADC : The base of ADC peripheral on the chip + * @return Nothing + * Reset the ADC control and INTEN Register to reset values (disabled) + */ +void IP_ADC_DeInit(IP_ADC_001_Type *pADC); + +/** + * @brief Set burst mode for ADC + * @param pADC : The base of ADC peripheral on the chip + * @param NewState : ENABLE for burst mode, or DISABLE for normal mode + * @return Nothing + */ +void IP_ADC_SetBurstMode(IP_ADC_001_Type *pADC, FunctionalState NewState); + +/** + * @brief Get the ADC value + * @param pADC : The base of ADC peripheral on the chip + * @param channel : Channel to be read value, should be 0..7 + * @param data : Data buffer to store the A/D value + * @return Status : SUCCESS or ERROR + */ +Status IP_ADC_Get_Val(IP_ADC_001_Type *pADC, uint8_t channel, uint16_t *data); + +/** + * @brief Get ADC Channel status from ADC data register + * @param pADC : The base of ADC peripheral on the chip + * @param channel : Channel number, should be 0..7 + * @param StatusType : Register to read, ADC_DR_DONE_STAT, ADC_DR_OVERRUN_STAT, or ADC_DR_ADINT_STAT + * @return Channel status, SET or RESET + */ +FlagStatus IP_ADC_GetStatus(IP_ADC_001_Type *pADC, uint8_t channel, uint32_t StatusType); + +/** + * @brief Set the edge start condition + * @param pADC : The base of ADC peripheral on the chip + * @param edge_mode : 0 = rising, != = falling + * @return Nothing + */ +void IP_ADC_EdgeStartConfig(IP_ADC_001_Type *pADC, uint8_t edge_mode); + +/** + * @brief Enable/Disable ADC channel number + * @param pADC : The base of ADC peripheral on the chip + * @param channel : Channel number + * @param NewState : New state, ENABLE or DISABLE + * @return Nothing + */ +void IP_ADC_SetChannelNumber(IP_ADC_001_Type *pADC, uint8_t channel, FunctionalState NewState); + +/** + * @brief Set start mode for ADC + * @param pADC : The base of ADC peripheral on the chip + * @param start_mode : Start mode choose one of modes in 'ADC_START_*' enumeration type definitions + * @return Nothing + */ +void IP_ADC_SetStartMode(IP_ADC_001_Type *pADC, uint8_t start_mode); + +/** + * @brief Enable/Disable interrupt for ADC channel + * @param pADC : The base of ADC peripheral on the chip + * @param channel : Channel assert the interrupt + * @param NewState : New state, ENABLE or DISABLE + * @return Nothing + */ +void IP_ADC_Int_Enable(IP_ADC_001_Type *pADC, uint8_t channel, FunctionalState NewState); + +/** + * @} + */ + +#ifdef __cplusplus +} +#endif + +#endif /* __ADC_001_H_ */ diff --git a/bsp/xplorer4330/libraries/lpc_ip/atimer_001.c b/bsp/xplorer4330/libraries/lpc_ip/atimer_001.c new file mode 100644 index 0000000000..dc02dba974 --- /dev/null +++ b/bsp/xplorer4330/libraries/lpc_ip/atimer_001.c @@ -0,0 +1,55 @@ +/* + * @brief Alarm Timer Registers and control functions + * + * @note + * Copyright(C) NXP Semiconductors, 2012 + * All rights reserved. + * + * @par + * Software that is described herein is for illustrative purposes only + * which provides customers with programming information regarding the + * LPC products. This software is supplied "AS IS" without any warranties of + * any kind, and NXP Semiconductors and its licensor disclaim any and + * all warranties, express or implied, including all implied warranties of + * merchantability, fitness for a particular purpose and non-infringement of + * intellectual property rights. NXP Semiconductors assumes no responsibility + * or liability for the use of the software, conveys no license or rights under any + * patent, copyright, mask work right, or any other intellectual property rights in + * or to any products. NXP Semiconductors reserves the right to make changes + * in the software without notification. NXP Semiconductors also makes no + * representation or warranty that such application will be suitable for the + * specified use without further testing or modification. + * + * @par + * Permission to use, copy, modify, and distribute this software and its + * documentation is hereby granted, under NXP Semiconductors' and its + * licensor's relevant copyrights in the software, without fee, provided that it + * is used in conjunction with NXP Semiconductors microcontrollers. This + * copyright, permission, and disclaimer notice must appear in all copies of + * this code. + */ + +#include "atimer_001.h" + +/***************************************************************************** + * Private types/enumerations/variables + ****************************************************************************/ + +/***************************************************************************** + * Public types/enumerations/variables + ****************************************************************************/ + +/***************************************************************************** + * Private functions + ****************************************************************************/ + +/***************************************************************************** + * Public functions + ****************************************************************************/ + +/* Close ATIMER device */ +void IP_ATIMER_DeInit(IP_ATIMER_001_Type *pATimer) +{ + IP_ATIMER_ClearIntStatus(pATimer); + IP_ATIMER_IntDisable(pATimer); +} diff --git a/bsp/xplorer4330/libraries/lpc_ip/atimer_001.h b/bsp/xplorer4330/libraries/lpc_ip/atimer_001.h new file mode 100644 index 0000000000..e2bf21a69d --- /dev/null +++ b/bsp/xplorer4330/libraries/lpc_ip/atimer_001.h @@ -0,0 +1,160 @@ +/* + * @brief Alarm Timer Registers and control functions + * + * @note + * Copyright(C) NXP Semiconductors, 2012 + * All rights reserved. + * + * @par + * Software that is described herein is for illustrative purposes only + * which provides customers with programming information regarding the + * LPC products. This software is supplied "AS IS" without any warranties of + * any kind, and NXP Semiconductors and its licensor disclaim any and + * all warranties, express or implied, including all implied warranties of + * merchantability, fitness for a particular purpose and non-infringement of + * intellectual property rights. NXP Semiconductors assumes no responsibility + * or liability for the use of the software, conveys no license or rights under any + * patent, copyright, mask work right, or any other intellectual property rights in + * or to any products. NXP Semiconductors reserves the right to make changes + * in the software without notification. NXP Semiconductors also makes no + * representation or warranty that such application will be suitable for the + * specified use without further testing or modification. + * + * @par + * Permission to use, copy, modify, and distribute this software and its + * documentation is hereby granted, under NXP Semiconductors' and its + * licensor's relevant copyrights in the software, without fee, provided that it + * is used in conjunction with NXP Semiconductors microcontrollers. This + * copyright, permission, and disclaimer notice must appear in all copies of + * this code. + */ + +#ifndef __ATIMER_001_H_ +#define __ATIMER_001_H_ + +#include "sys_config.h" +#include "cmsis.h" + +#ifdef __cplusplus +extern "C" { +#endif + +/** @defgroup IP_ATIMER_001 IP: ATimer register block and driver + * @ingroup IP_Drivers + * Alarm timer + * @{ + */ + +/** + * @brief Alarm Timer register block structure + */ +typedef struct { /*!< ATIMER Structure */ + __IO uint32_t DOWNCOUNTER; /*!< Downcounter register */ + __IO uint32_t PRESET; /*!< Preset value register */ + __I uint32_t RESERVED0[1012]; + __O uint32_t CLR_EN; /*!< Interrupt clear enable register */ + __O uint32_t SET_EN; /*!< Interrupt set enable register */ + __I uint32_t STATUS; /*!< Status register */ + __I uint32_t ENABLE; /*!< Enable register */ + __O uint32_t CLR_STAT; /*!< Clear register */ + __O uint32_t SET_STAT; /*!< Set register */ +} IP_ATIMER_001_Type; + +/** + * @brief Close ATIMER device + * @param pATimer : Pointer to timer device + * @return None + * Important: 32KHz clock must be enabled in CREG prior to this call. See + * the User Manual for more information. + */ +void IP_ATIMER_DeInit(IP_ATIMER_001_Type *pATimer); + +/** + * @brief Clear ATIMER Interrupt Status + * @param pATimer : Pointer to timer device + * @return None + */ +STATIC INLINE void IP_ATIMER_ClearIntStatus(IP_ATIMER_001_Type *pATimer) +{ + pATimer->CLR_STAT = 1; +} + +/** + * @brief Set ATIMER Interrupt Status + * @param pATimer : Pointer to timer device + * @return None + */ +STATIC INLINE void IP_ATIMER_SetIntStatus(IP_ATIMER_001_Type *pATimer) +{ + pATimer->SET_STAT = 1; +} +/** + * @brief Enable ATIMER Interrupt + * @param pATimer : Pointer to timer device + * @return None + */ +STATIC INLINE void IP_ATIMER_IntEnable(IP_ATIMER_001_Type *pATimer) +{ + pATimer->SET_EN = 1; +} + +/** + * @brief Disable ATIMER Interrupt + * @param pATimer : Pointer to timer device + * @return None + */ +STATIC INLINE void IP_ATIMER_IntDisable(IP_ATIMER_001_Type *pATimer) +{ + pATimer->CLR_EN = 1; +} + +/** + * @brief Update Preset value + * @param pATimer : Pointer to timer device + * @param PresetValue updated preset value + * @return Nothing + */ +STATIC INLINE void IP_ATIMER_UpdatePresetValue(IP_ATIMER_001_Type *pATimer, uint32_t PresetValue) +{ + pATimer->PRESET = PresetValue; +} + +/** + * @brief Read value of preset register + * @param pATimer : Pointer to timer/counter device + * @return Value of capture register + */ +STATIC INLINE uint32_t IP_ATIMER_GetPresetValue(IP_ATIMER_001_Type *pATimer) +{ + return pATimer->PRESET; +} + +/** + * @brief Returns enable state of ATimer interrupt + * @param pATimer : Pointer to timer/counter device + * @return !0 if the ATimer interrupt is enabled, otherwise 0 + */ +STATIC INLINE uint32_t IP_ATIMER_GetIntEnableState(IP_ATIMER_001_Type *pATimer) +{ + return pATimer->ENABLE; +} + +/** + * @brief Returns current pending state of ATimer interrupt + * @param pATimer : Pointer to timer/counter device + * @return !0 if the ATimer interrupt is asserted, otherwise 0 + */ +STATIC INLINE uint32_t IP_ATIMER_GetIntPendingState(IP_ATIMER_001_Type *pATimer) +{ + return pATimer->STATUS; +} + +/** + * @} + */ + +#ifdef __cplusplus +} +#endif + +#endif /* __ATIMER_001_H_ */ diff --git a/bsp/xplorer4330/libraries/lpc_ip/ccan_001.h b/bsp/xplorer4330/libraries/lpc_ip/ccan_001.h new file mode 100644 index 0000000000..09eb7b6268 --- /dev/null +++ b/bsp/xplorer4330/libraries/lpc_ip/ccan_001.h @@ -0,0 +1,114 @@ +/* + * @brief CCAN registers and control functions + * + * @note + * Copyright(C) NXP Semiconductors, 2012 + * All rights reserved. + * + * @par + * Software that is described herein is for illustrative purposes only + * which provides customers with programming information regarding the + * LPC products. This software is supplied "AS IS" without any warranties of + * any kind, and NXP Semiconductors and its licensor disclaim any and + * all warranties, express or implied, including all implied warranties of + * merchantability, fitness for a particular purpose and non-infringement of + * intellectual property rights. NXP Semiconductors assumes no responsibility + * or liability for the use of the software, conveys no license or rights under any + * patent, copyright, mask work right, or any other intellectual property rights in + * or to any products. NXP Semiconductors reserves the right to make changes + * in the software without notification. NXP Semiconductors also makes no + * representation or warranty that such application will be suitable for the + * specified use without further testing or modification. + * + * @par + * Permission to use, copy, modify, and distribute this software and its + * documentation is hereby granted, under NXP Semiconductors' and its + * licensor's relevant copyrights in the software, without fee, provided that it + * is used in conjunction with NXP Semiconductors microcontrollers. This + * copyright, permission, and disclaimer notice must appear in all copies of + * this code. + */ + +#ifndef __CCAN_001_H_ +#define __CCAN_001_H_ + +#include "sys_config.h" +#include "cmsis.h" + +#ifdef __cplusplus +extern "C" { +#endif + +/** @defgroup IP_CCAN_001 IP: CCAN register block and driver + * @ingroup IP_Drivers + * @{ + */ + +/** + * @brief CCAN Controller Area Network register block structure + */ +typedef struct { /*!< C_CAN Structure */ + __IO uint32_t CNTL; /*!< CAN control */ + __IO uint32_t STAT; /*!< Status register */ + __I uint32_t EC; /*!< Error counter */ + __IO uint32_t BT; /*!< Bit timing register */ + __I uint32_t INT; /*!< Interrupt register */ + __IO uint32_t TEST; /*!< Test register */ + __IO uint32_t BRPE; /*!< Baud rate prescaler extension register */ + __I uint32_t RESERVED0; + __IO uint32_t IF1_CMDREQ; /*!< Message interface command request */ + union { + __IO uint32_t IF1_CMDMSK_R; /*!< Message interface command mask (read direction) */ + __IO uint32_t IF1_CMDMSK_W; /*!< Message interface command mask (write direction) */ + }; + + __IO uint32_t IF1_MSK1; /*!< Message interface mask 1 */ + __IO uint32_t IF1_MSK2; /*!< Message interface 1 mask 2 */ + __IO uint32_t IF1_ARB1; /*!< Message interface 1 arbitration 1 */ + __IO uint32_t IF1_ARB2; /*!< Message interface 1 arbitration 2 */ + __IO uint32_t IF1_MCTRL; /*!< Message interface 1 message control */ + __IO uint32_t IF1_DA1; /*!< Message interface data A1 */ + __IO uint32_t IF1_DA2; /*!< Message interface 1 data A2 */ + __IO uint32_t IF1_DB1; /*!< Message interface 1 data B1 */ + __IO uint32_t IF1_DB2; /*!< Message interface 1 data B2 */ + __I uint32_t RESERVED1[13]; + __IO uint32_t IF2_CMDREQ; /*!< Message interface command request */ + union { + __IO uint32_t IF2_CMDMSK_R; /*!< Message interface command mask (read direction) */ + __IO uint32_t IF2_CMDMSK_W; /*!< Message interface command mask (write direction) */ + }; + + __IO uint32_t IF2_MSK1; /*!< Message interface mask 1 */ + __IO uint32_t IF2_MSK2; /*!< Message interface 1 mask 2 */ + __IO uint32_t IF2_ARB1; /*!< Message interface 1 arbitration 1 */ + __IO uint32_t IF2_ARB2; /*!< Message interface 1 arbitration 2 */ + __IO uint32_t IF2_MCTRL; /*!< Message interface 1 message control */ + __IO uint32_t IF2_DA1; /*!< Message interface data A1 */ + __IO uint32_t IF2_DA2; /*!< Message interface 1 data A2 */ + __IO uint32_t IF2_DB1; /*!< Message interface 1 data B1 */ + __IO uint32_t IF2_DB2; /*!< Message interface 1 data B2 */ + __I uint32_t RESERVED2[21]; + __I uint32_t TXREQ1; /*!< Transmission request 1 */ + __I uint32_t TXREQ2; /*!< Transmission request 2 */ + __I uint32_t RESERVED3[6]; + __I uint32_t ND1; /*!< New data 1 */ + __I uint32_t ND2; /*!< New data 2 */ + __I uint32_t RESERVED4[6]; + __I uint32_t IR1; /*!< Interrupt pending 1 */ + __I uint32_t IR2; /*!< Interrupt pending 2 */ + __I uint32_t RESERVED5[6]; + __I uint32_t MSGV1; /*!< Message valid 1 */ + __I uint32_t MSGV2; /*!< Message valid 2 */ + __I uint32_t RESERVED6[6]; + __IO uint32_t CLKDIV; /*!< CAN clock divider register */ +} IP_CCAN_001_Type; + +/** + * @} + */ + +#ifdef __cplusplus +} +#endif + +#endif /* __CCAN_001_H_ */ diff --git a/bsp/xplorer4330/libraries/lpc_ip/dac_001.h b/bsp/xplorer4330/libraries/lpc_ip/dac_001.h new file mode 100644 index 0000000000..f176f100e9 --- /dev/null +++ b/bsp/xplorer4330/libraries/lpc_ip/dac_001.h @@ -0,0 +1,64 @@ +/* + * @brief DAC Registers and control functions + * + * @note + * Copyright(C) NXP Semiconductors, 2012 + * All rights reserved. + * + * @par + * Software that is described herein is for illustrative purposes only + * which provides customers with programming information regarding the + * LPC products. This software is supplied "AS IS" without any warranties of + * any kind, and NXP Semiconductors and its licensor disclaim any and + * all warranties, express or implied, including all implied warranties of + * merchantability, fitness for a particular purpose and non-infringement of + * intellectual property rights. NXP Semiconductors assumes no responsibility + * or liability for the use of the software, conveys no license or rights under any + * patent, copyright, mask work right, or any other intellectual property rights in + * or to any products. NXP Semiconductors reserves the right to make changes + * in the software without notification. NXP Semiconductors also makes no + * representation or warranty that such application will be suitable for the + * specified use without further testing or modification. + * + * @par + * Permission to use, copy, modify, and distribute this software and its + * documentation is hereby granted, under NXP Semiconductors' and its + * licensor's relevant copyrights in the software, without fee, provided that it + * is used in conjunction with NXP Semiconductors microcontrollers. This + * copyright, permission, and disclaimer notice must appear in all copies of + * this code. + */ + +#ifndef __DAC_001_H_ +#define __DAC_001_H_ + +#include "sys_config.h" +#include "cmsis.h" + +#ifdef __cplusplus +extern "C" { +#endif + +/** @defgroup IP_DAC_001 IP: DAC register block and driver + * @ingroup IP_Drivers + * @{ + */ + +/** + * @brief DAC register block structure + */ +typedef struct { /*!< DAC Structure */ + __IO uint32_t CR; /*!< DAC register. Holds the conversion data. */ + __IO uint32_t CTRL; /*!< DAC control register. */ + __IO uint32_t CNTVAL; /*!< DAC counter value register. */ +} IP_DAC_001_Type; + +/** + * @} + */ + +#ifdef __cplusplus +} +#endif + +#endif /* __DAC_001_H_ */ diff --git a/bsp/xplorer4330/libraries/lpc_ip/emc_001.c b/bsp/xplorer4330/libraries/lpc_ip/emc_001.c new file mode 100644 index 0000000000..a31c6ba5a5 --- /dev/null +++ b/bsp/xplorer4330/libraries/lpc_ip/emc_001.c @@ -0,0 +1,274 @@ +/* + * @brief EMC Registers and control functions + * + * @note + * Copyright(C) NXP Semiconductors, 2012 + * All rights reserved. + * + * @par + * Software that is described herein is for illustrative purposes only + * which provides customers with programming information regarding the + * LPC products. This software is supplied "AS IS" without any warranties of + * any kind, and NXP Semiconductors and its licensor disclaim any and + * all warranties, express or implied, including all implied warranties of + * merchantability, fitness for a particular purpose and non-infringement of + * intellectual property rights. NXP Semiconductors assumes no responsibility + * or liability for the use of the software, conveys no license or rights under any + * patent, copyright, mask work right, or any other intellectual property rights in + * or to any products. NXP Semiconductors reserves the right to make changes + * in the software without notification. NXP Semiconductors also makes no + * representation or warranty that such application will be suitable for the + * specified use without further testing or modification. + * + * @par + * Permission to use, copy, modify, and distribute this software and its + * documentation is hereby granted, under NXP Semiconductors' and its + * licensor's relevant copyrights in the software, without fee, provided that it + * is used in conjunction with NXP Semiconductors microcontrollers. This + * copyright, permission, and disclaimer notice must appear in all copies of + * this code. + */ + +#include "emc_001.h" + +/***************************************************************************** + * Private types/enumerations/variables + ****************************************************************************/ + +/***************************************************************************** + * Public types/enumerations/variables + ****************************************************************************/ + +/***************************************************************************** + * Private functions + ****************************************************************************/ + +/* DIV function with result rounded up */ +#define EMC_DIV_ROUND_UP(x, y) ((x + y - 1) / y) + +#ifndef EMC_SUPPORT_ONLY_PL172 +/* Get ARM External Memory Controller Version */ +static uint32_t EMC_GetARMPeripheralID(IP_EMC_001_Type *pEMC) +{ + uint32_t *RegAdd; + RegAdd = (uint32_t *) ((uint32_t) pEMC + 0xFE0); + return (RegAdd[0] & 0xFF) | ((RegAdd[1] & 0xFF) << 8) | + ((RegAdd[2] & 0xFF) << 16) | (RegAdd[3] << 24); +} + +#endif + +/* Calculate Clock Count from Timing Unit(nanoseconds) */ +static uint32_t EMC_TimingParamConvert(uint32_t EMC_Clock, int32_t input_ns, uint32_t adjust) +{ + uint32_t temp; + if (input_ns < 0) { + return (-input_ns) >> 8; + } + temp = EMC_Clock / 1000000; /* MHz calculation */ + temp = temp * input_ns / 1000; + + /* round up */ + temp += 0xFF; + + /* convert to simple integer number format */ + temp >>= 8; + if (temp > adjust) { + return temp - adjust; + } + + return 0; +} + +/* Get Dynamic Memory Device Colum len */ +static uint32_t EMC_GetColsLen(uint32_t DynConfig) +{ + uint32_t DevBusWidth; + DevBusWidth = (DynConfig >> EMC_DYN_CONFIG_DEV_BUS_BIT) & 0x03; + if (DevBusWidth == 2) { + return 8; + } + else if (DevBusWidth == 1) { + return ((DynConfig >> (EMC_DYN_CONFIG_DEV_SIZE_BIT + 1)) & 0x03) + 8; + } + else if (DevBusWidth == 0) { + return ((DynConfig >> (EMC_DYN_CONFIG_DEV_SIZE_BIT + 1)) & 0x03) + 9; + } + + return 0; +} + +/***************************************************************************** + * Public functions + ****************************************************************************/ + +/* Initializes the Dynamic Controller according to the specified parameters + in the IP_EMC_DYN_CONFIG_Type */ +void IP_EMC_Dynamic_Init(IP_EMC_001_Type *pEMC, IP_EMC_DYN_CONFIG_Type *Dynamic_Config, uint32_t EMC_Clock) +{ + uint32_t ChipSelect, tmpclk; + int i; + + for (ChipSelect = 0; ChipSelect < 4; ChipSelect++) { + IP_EMC_001_Type *EMC_Reg_add = (IP_EMC_001_Type *) ((uint32_t) pEMC + (ChipSelect << 5)); + + EMC_Reg_add->DYNAMICRASCAS0 = Dynamic_Config->DevConfig[ChipSelect].RAS | + ((Dynamic_Config->DevConfig[ChipSelect].ModeRegister << + (8 - EMC_DYN_MODE_CAS_BIT)) & 0xF00); + EMC_Reg_add->DYNAMICCONFIG0 = Dynamic_Config->DevConfig[ChipSelect].DynConfig; + } + pEMC->DYNAMICREADCONFIG = Dynamic_Config->ReadConfig; /* Read strategy */ + + pEMC->DYNAMICRP = EMC_TimingParamConvert(EMC_Clock, Dynamic_Config->tRP, 1); + pEMC->DYNAMICRAS = EMC_TimingParamConvert(EMC_Clock, Dynamic_Config->tRAS, 1); + pEMC->DYNAMICSREX = EMC_TimingParamConvert(EMC_Clock, Dynamic_Config->tSREX, 1); + pEMC->DYNAMICAPR = EMC_TimingParamConvert(EMC_Clock, Dynamic_Config->tAPR, 1); + pEMC->DYNAMICDAL = EMC_TimingParamConvert(EMC_Clock, Dynamic_Config->tDAL, 0); + pEMC->DYNAMICWR = EMC_TimingParamConvert(EMC_Clock, Dynamic_Config->tWR, 1); + pEMC->DYNAMICRC = EMC_TimingParamConvert(EMC_Clock, Dynamic_Config->tRC, 1); + pEMC->DYNAMICRFC = EMC_TimingParamConvert(EMC_Clock, Dynamic_Config->tRFC, 1); + pEMC->DYNAMICXSR = EMC_TimingParamConvert(EMC_Clock, Dynamic_Config->tXSR, 1); + pEMC->DYNAMICRRD = EMC_TimingParamConvert(EMC_Clock, Dynamic_Config->tRRD, 1); + pEMC->DYNAMICMRD = EMC_TimingParamConvert(EMC_Clock, Dynamic_Config->tMRD, 1); + + /* TIM_Waitus(100); */ + /*TODO: if Timer driver is ready, it should replace below "for" delay technic */ + for (i = 0; i < 1000; i++) { /* wait 100us */ + } + pEMC->DYNAMICCONTROL = 0x00000183; /* Issue NOP command */ + + /* TIM_Waitus(200); */ /* wait 200us */ + /*TODO: if Timer driver is ready, it should replace below "for" delay technic */ + for (i = 0; i < 1000; i++) {} + pEMC->DYNAMICCONTROL = 0x00000103; /* Issue PALL command */ + + pEMC->DYNAMICREFRESH = 2; /* ( 2 * 16 ) -> 32 clock cycles */ + + /* TIM_Waitus(200); */ /* wait 200us */ + for (i = 0; i < 80; i++) {} + + tmpclk = EMC_DIV_ROUND_UP(EMC_TimingParamConvert(EMC_Clock, Dynamic_Config->RefreshPeriod, 0), 16); + pEMC->DYNAMICREFRESH = tmpclk; + + pEMC->DYNAMICCONTROL = 0x00000083; /* Issue MODE command */ + + for (ChipSelect = 0; ChipSelect < 4; ChipSelect++) { + /*uint32_t burst_length;*/ + uint32_t DynAddr; + uint8_t Col_len; + + Col_len = EMC_GetColsLen(Dynamic_Config->DevConfig[ChipSelect].DynConfig); + /* get bus wide: if 32bit, len is 4 else if 16bit len is 2 */ + /* burst_length = 1 << ((((Dynamic_Config->DynConfig[ChipSelect] >> 14) & 1)^1) +1); */ + if (Dynamic_Config->DevConfig[ChipSelect].DynConfig & (1 << EMC_DYN_CONFIG_DATA_BUS_WIDTH_BIT)) { + /*32bit bus */ + /*burst_length = 2;*/ + Col_len += 2; + } + else { + /*burst_length = 4;*/ + Col_len += 1; + } + DynAddr = Dynamic_Config->DevConfig[ChipSelect].BaseAddr; + + if (DynAddr != 0) { + uint32_t temp; + uint32_t ModeRegister; + ModeRegister = Dynamic_Config->DevConfig[ChipSelect].ModeRegister; + temp = *((volatile uint32_t *) (DynAddr | (ModeRegister << Col_len))); + temp = temp; + } + } + pEMC->DYNAMICCONTROL = 0x00000000; /* Issue NORMAL command */ + + /* enable buffers */ + pEMC->DYNAMICCONFIG0 |= 1 << 19; + pEMC->DYNAMICCONFIG1 |= 1 << 19; + pEMC->DYNAMICCONFIG2 |= 1 << 19; + pEMC->DYNAMICCONFIG3 |= 1 << 19; +} + +/* Set Deep Sleep Mode for Dynamic Memory Controller */ +void IP_EMC_Dynamic_DeepSleepMode(IP_EMC_001_Type *pEMC, uint32_t Enable) +{ + if (Enable) { + pEMC->DYNAMICCONTROL |= 1 << EMC_DYN_CONTROL_DEEPSLEEP_BIT; + } + else { + pEMC->DYNAMICCONTROL &= ~(1 << EMC_DYN_CONTROL_DEEPSLEEP_BIT); + } +} + +/* Enable Dynamic Memory Controller */ +void IP_EMC_Dynamic_Enable(IP_EMC_001_Type *pEMC, uint8_t Enable) +{ + if (Enable) { + pEMC->DYNAMICCONTROL |= EMC_DYN_CONTROL_ENABLE; + } + else { + pEMC->DYNAMICCONTROL &= ~EMC_DYN_CONTROL_ENABLE; + } +} + +/* Initializes the Static Controller according to the specified parameters + * in the IP_EMC_STATIC_CONFIG_Type + */ +void IP_EMC_Static_Init(IP_EMC_001_Type *pEMC, IP_EMC_STATIC_CONFIG_Type *Static_Config, uint32_t EMC_Clock) +{ + IP_EMC_001_Type *EMC_Reg_add = (IP_EMC_001_Type *) ((uint32_t) pEMC + ((Static_Config->ChipSelect) << 5)); + EMC_Reg_add->STATICCONFIG0 = Static_Config->Config; + EMC_Reg_add->STATICWAITWEN0 = EMC_TimingParamConvert(EMC_Clock, Static_Config->WaitWen, 1); + EMC_Reg_add->STATICWAITOEN0 = EMC_TimingParamConvert(EMC_Clock, Static_Config->WaitOen, 0); + EMC_Reg_add->STATICWAITRD0 = EMC_TimingParamConvert(EMC_Clock, Static_Config->WaitRd, 1); + EMC_Reg_add->STATICWAITPAG0 = EMC_TimingParamConvert(EMC_Clock, Static_Config->WaitPage, 1); + EMC_Reg_add->STATICWAITWR0 = EMC_TimingParamConvert(EMC_Clock, Static_Config->WaitWr, 2); + EMC_Reg_add->STATICWAITTURN0 = EMC_TimingParamConvert(EMC_Clock, Static_Config->WaitTurn, 1); +} + +/* Mirror CS1 to CS0 and DYCS0 */ +void IP_EMC_Mirror(IP_EMC_001_Type *pEMC, uint32_t Enable) +{ + if (Enable) { + pEMC->CONTROL |= 1 << 1; + } + else { + pEMC->CONTROL &= ~(1 << 1); + } +} + +/* Enable EMC */ +void IP_EMC_Enable(IP_EMC_001_Type *pEMC, uint32_t Enable) +{ + if (Enable) { + pEMC->CONTROL |= 1; + } + else { + pEMC->CONTROL &= ~(1); + } +} + +/* Set EMC LowPower Mode */ +void IP_EMC_LowPowerMode(IP_EMC_001_Type *pEMC, uint32_t Enable) +{ + if (Enable) { + pEMC->CONTROL |= 1 << 2; + } + else { + pEMC->CONTROL &= ~(1 << 2); + } +} + +/* Initialize EMC */ +void IP_EMC_Init(IP_EMC_001_Type *pEMC, uint32_t Enable, uint32_t ClockRatio, uint32_t EndianMode) +{ + pEMC->CONFIG = (EndianMode ? 1 : 0) | ((ClockRatio ? 1 : 0) << 8); + + /* Enable EMC 001 Normal Memory Map, No low power mode */ + pEMC->CONTROL = (Enable ? 1 : 0); +} + +/* Set Static Memory Extended Wait in Clock */ +void IP_EMC_SetStaticExtendedWait(IP_EMC_001_Type *pEMC, uint32_t Wait16Clks) +{ + pEMC->STATICEXTENDEDWAIT = Wait16Clks; +} diff --git a/bsp/xplorer4330/libraries/lpc_ip/emc_001.h b/bsp/xplorer4330/libraries/lpc_ip/emc_001.h new file mode 100644 index 0000000000..2ba9223c0e --- /dev/null +++ b/bsp/xplorer4330/libraries/lpc_ip/emc_001.h @@ -0,0 +1,357 @@ +/* + * @brief EMC Registers and control functions + * + * @note + * Copyright(C) NXP Semiconductors, 2012 + * All rights reserved. + * + * @par + * Software that is described herein is for illustrative purposes only + * which provides customers with programming information regarding the + * LPC products. This software is supplied "AS IS" without any warranties of + * any kind, and NXP Semiconductors and its licensor disclaim any and + * all warranties, express or implied, including all implied warranties of + * merchantability, fitness for a particular purpose and non-infringement of + * intellectual property rights. NXP Semiconductors assumes no responsibility + * or liability for the use of the software, conveys no license or rights under any + * patent, copyright, mask work right, or any other intellectual property rights in + * or to any products. NXP Semiconductors reserves the right to make changes + * in the software without notification. NXP Semiconductors also makes no + * representation or warranty that such application will be suitable for the + * specified use without further testing or modification. + * + * @par + * Permission to use, copy, modify, and distribute this software and its + * documentation is hereby granted, under NXP Semiconductors' and its + * licensor's relevant copyrights in the software, without fee, provided that it + * is used in conjunction with NXP Semiconductors microcontrollers. This + * copyright, permission, and disclaimer notice must appear in all copies of + * this code. + */ + +#ifndef __EMC_001_H_ +#define __EMC_001_H_ + +#include "sys_config.h" +#include "cmsis.h" + +#ifdef __cplusplus +extern "C" { +#endif + +/** @defgroup IP_EMC_001 IP: EMC register block and driver + * @ingroup IP_Drivers + * External Memory Controller + * @{ + */ + +/** + * @brief External Memory Controller (EMC) register block structure + */ +typedef struct { /*!< EMC Structure */ + __IO uint32_t CONTROL; /*!< Controls operation of the memory controller. */ + __I uint32_t STATUS; /*!< Provides EMC status information. */ + __IO uint32_t CONFIG; /*!< Configures operation of the memory controller. */ + __I uint32_t RESERVED0[5]; + __IO uint32_t DYNAMICCONTROL; /*!< Controls dynamic memory operation. */ + __IO uint32_t DYNAMICREFRESH; /*!< Configures dynamic memory refresh operation. */ + __IO uint32_t DYNAMICREADCONFIG; /*!< Configures the dynamic memory read strategy. */ + __I uint32_t RESERVED1; + __IO uint32_t DYNAMICRP; /*!< Selects the precharge command period. */ + __IO uint32_t DYNAMICRAS; /*!< Selects the active to precharge command period. */ + __IO uint32_t DYNAMICSREX; /*!< Selects the self-refresh exit time. */ + __IO uint32_t DYNAMICAPR; /*!< Selects the last-data-out to active command time. */ + __IO uint32_t DYNAMICDAL; /*!< Selects the data-in to active command time. */ + __IO uint32_t DYNAMICWR; /*!< Selects the write recovery time. */ + __IO uint32_t DYNAMICRC; /*!< Selects the active to active command period. */ + __IO uint32_t DYNAMICRFC; /*!< Selects the auto-refresh period. */ + __IO uint32_t DYNAMICXSR; /*!< Selects the exit self-refresh to active command time. */ + __IO uint32_t DYNAMICRRD; /*!< Selects the active bank A to active bank B latency. */ + __IO uint32_t DYNAMICMRD; /*!< Selects the load mode register to active command time. */ + __I uint32_t RESERVED2[9]; + __IO uint32_t STATICEXTENDEDWAIT; /*!< Selects time for long static memory read and write transfers. */ + __I uint32_t RESERVED3[31]; + __IO uint32_t DYNAMICCONFIG0; /*!< Selects the configuration information for dynamic memory chip select n. */ + __IO uint32_t DYNAMICRASCAS0; /*!< Selects the RAS and CAS latencies for dynamic memory chip select n. */ + __I uint32_t RESERVED4[6]; + __IO uint32_t DYNAMICCONFIG1; /*!< Selects the configuration information for dynamic memory chip select n. */ + __IO uint32_t DYNAMICRASCAS1; /*!< Selects the RAS and CAS latencies for dynamic memory chip select n. */ + __I uint32_t RESERVED5[6]; + __IO uint32_t DYNAMICCONFIG2; /*!< Selects the configuration information for dynamic memory chip select n. */ + __IO uint32_t DYNAMICRASCAS2; /*!< Selects the RAS and CAS latencies for dynamic memory chip select n. */ + __I uint32_t RESERVED6[6]; + __IO uint32_t DYNAMICCONFIG3; /*!< Selects the configuration information for dynamic memory chip select n. */ + __IO uint32_t DYNAMICRASCAS3; /*!< Selects the RAS and CAS latencies for dynamic memory chip select n. */ + __I uint32_t RESERVED7[38]; + __IO uint32_t STATICCONFIG0; /*!< Selects the memory configuration for static chip select n. */ + __IO uint32_t STATICWAITWEN0; /*!< Selects the delay from chip select n to write enable. */ + __IO uint32_t STATICWAITOEN0; /*!< Selects the delay from chip select n or address change, whichever is later, to output enable. */ + __IO uint32_t STATICWAITRD0; /*!< Selects the delay from chip select n to a read access. */ + __IO uint32_t STATICWAITPAG0; /*!< Selects the delay for asynchronous page mode sequential accesses for chip select n. */ + __IO uint32_t STATICWAITWR0; /*!< Selects the delay from chip select n to a write access. */ + __IO uint32_t STATICWAITTURN0; /*!< Selects bus turnaround cycles */ + __I uint32_t RESERVED8; + __IO uint32_t STATICCONFIG1; /*!< Selects the memory configuration for static chip select n. */ + __IO uint32_t STATICWAITWEN1; /*!< Selects the delay from chip select n to write enable. */ + __IO uint32_t STATICWAITOEN1; /*!< Selects the delay from chip select n or address change, whichever is later, to output enable. */ + __IO uint32_t STATICWAITRD1; /*!< Selects the delay from chip select n to a read access. */ + __IO uint32_t STATICWAITPAG1; /*!< Selects the delay for asynchronous page mode sequential accesses for chip select n. */ + __IO uint32_t STATICWAITWR1; /*!< Selects the delay from chip select n to a write access. */ + __IO uint32_t STATICWAITTURN1; /*!< Selects bus turnaround cycles */ + __I uint32_t RESERVED9; + __IO uint32_t STATICCONFIG2; /*!< Selects the memory configuration for static chip select n. */ + __IO uint32_t STATICWAITWEN2; /*!< Selects the delay from chip select n to write enable. */ + __IO uint32_t STATICWAITOEN2; /*!< Selects the delay from chip select n or address change, whichever is later, to output enable. */ + __IO uint32_t STATICWAITRD2; /*!< Selects the delay from chip select n to a read access. */ + __IO uint32_t STATICWAITPAG2; /*!< Selects the delay for asynchronous page mode sequential accesses for chip select n. */ + __IO uint32_t STATICWAITWR2; /*!< Selects the delay from chip select n to a write access. */ + __IO uint32_t STATICWAITTURN2; /*!< Selects bus turnaround cycles */ + __I uint32_t RESERVED10; + __IO uint32_t STATICCONFIG3; /*!< Selects the memory configuration for static chip select n. */ + __IO uint32_t STATICWAITWEN3; /*!< Selects the delay from chip select n to write enable. */ + __IO uint32_t STATICWAITOEN3; /*!< Selects the delay from chip select n or address change, whichever is later, to output enable. */ + __IO uint32_t STATICWAITRD3; /*!< Selects the delay from chip select n to a read access. */ + __IO uint32_t STATICWAITPAG3; /*!< Selects the delay for asynchronous page mode sequential accesses for chip select n. */ + __IO uint32_t STATICWAITWR3; /*!< Selects the delay from chip select n to a write access. */ + __IO uint32_t STATICWAITTURN3; /*!< Selects bus turnaround cycles */ +} IP_EMC_001_Type; + +/** + * @brief EMC register support bitfields and mask + */ +/* Reserve for extending support to ARM9 or nextgen LPC */ +#define EMC_SUPPORT_ONLY_PL172 /*!< Reserve for extending support to ARM9 or nextgen LPC */ + +#define EMC_CONFIG_ENDIAN_LITTLE (0) /*!< Value for EMC to operate in Little Endian Mode */ +#define EMC_CONFIG_ENDIAN_BIG (1) /*!< Value for EMC to operate in Big Endian Mode */ + +#define EMC_CONFIG_BUFFER_ENABLE (1 << 19) /*!< EMC Buffer enable bit in EMC Dynamic Configuration register */ +#define EMC_CONFIG_WRITE_PROTECT (1 << 20) /*!< EMC Write protect bit in EMC Dynamic Configuration register */ + +/* Dynamic Memory Configuration Register Bit Definitions */ +#define EMC_DYN_CONFIG_MD_BIT (3) /*!< Memory device bit in EMC Dynamic Configuration register */ +#define EMC_DYN_CONFIG_MD_SDRAM (0 << EMC_DYN_CONFIG_MD_BIT) /*!< Select device as SDRAM in EMC Dynamic Configuration register */ +#define EMC_DYN_CONFIG_MD_LPSDRAM (1 << EMC_DYN_CONFIG_MD_BIT) /*!< Select device as LPSDRAM in EMC Dynamic Configuration register */ + +#define EMC_DYN_CONFIG_LPSDRAM_BIT (12) /*!< LPSDRAM bit in EMC Dynamic Configuration register */ +#define EMC_DYN_CONFIG_LPSDRAM (1 << EMC_DYN_CONFIG_LPSDRAM_BIT) /*!< LPSDRAM value in EMC Dynamic Configuration register */ + +#define EMC_DYN_CONFIG_DEV_SIZE_BIT (9) /*!< Device Size starting bit in EMC Dynamic Configuration register */ +#define EMC_DYN_CONFIG_DEV_SIZE_16Mb (0x00 << EMC_DYN_CONFIG_DEV_SIZE_BIT) /*!< 16Mb Device Size value in EMC Dynamic Configuration register */ +#define EMC_DYN_CONFIG_DEV_SIZE_64Mb (0x01 << EMC_DYN_CONFIG_DEV_SIZE_BIT) /*!< 64Mb Device Size value in EMC Dynamic Configuration register */ +#define EMC_DYN_CONFIG_DEV_SIZE_128Mb (0x02 << EMC_DYN_CONFIG_DEV_SIZE_BIT) /*!< 128Mb Device Size value in EMC Dynamic Configuration register */ +#define EMC_DYN_CONFIG_DEV_SIZE_256Mb (0x03 << EMC_DYN_CONFIG_DEV_SIZE_BIT) /*!< 256Mb Device Size value in EMC Dynamic Configuration register */ +#define EMC_DYN_CONFIG_DEV_SIZE_512Mb (0x04 << EMC_DYN_CONFIG_DEV_SIZE_BIT) /*!< 512Mb Device Size value in EMC Dynamic Configuration register */ + +#define EMC_DYN_CONFIG_DEV_BUS_BIT (7) /*!< Device bus width starting bit in EMC Dynamic Configuration register */ +#define EMC_DYN_CONFIG_DEV_BUS_8 (0x00 << EMC_DYN_CONFIG_DEV_BUS_BIT) /*!< Device 8-bit bus width value in EMC Dynamic Configuration register */ +#define EMC_DYN_CONFIG_DEV_BUS_16 (0x01 << EMC_DYN_CONFIG_DEV_BUS_BIT) /*!< Device 16-bit bus width value in EMC Dynamic Configuration register */ +#define EMC_DYN_CONFIG_DEV_BUS_32 (0x02 << EMC_DYN_CONFIG_DEV_BUS_BIT) /*!< Device 32-bit bus width value in EMC Dynamic Configuration register */ + +#define EMC_DYN_CONFIG_DATA_BUS_WIDTH_BIT (14) /*!< Device data bus width starting bit in EMC Dynamic Configuration register */ +#define EMC_DYN_CONFIG_DATA_BUS_16 (0x00 << EMC_DYN_CONFIG_DATA_BUS_WIDTH_BIT) /*!< Device 16-bit data bus width value in EMC Dynamic Configuration register */ +#define EMC_DYN_CONFIG_DATA_BUS_32 (0x01 << EMC_DYN_CONFIG_DATA_BUS_WIDTH_BIT) /*!< Device 32-bit bus width value in EMC Dynamic Configuration register */ + +/*!< Memory configuration values in EMC Dynamic Configuration Register */ +#define EMC_DYN_CONFIG_2Mx8_2BANKS_11ROWS_9COLS ((0x0 << 9) | (0x0 << 7)) /*!< Value for Memory configuration - 2Mx8 2 Banks 11 Rows 9 Columns */ +#define EMC_DYN_CONFIG_1Mx16_2BANKS_11ROWS_8COLS ((0x0 << 9) | (0x1 << 7)) /*!< Value for Memory configuration - 1Mx16 2 Banks 11 Rows 8 Columns */ +#define EMC_DYN_CONFIG_8Mx8_4BANKS_12ROWS_9COLS ((0x1 << 9) | (0x0 << 7)) /*!< Value for Memory configuration - 8Mx8 4 Banks 12 Rows 9 Columns */ +#define EMC_DYN_CONFIG_4Mx16_4BANKS_12ROWS_8COLS ((0x1 << 9) | (0x1 << 7)) /*!< Value for Memory configuration - 4Mx16 4 Banks 12 Rows 8 Columns */ +#define EMC_DYN_CONFIG_2Mx32_4BANKS_11ROWS_8COLS ((0x1 << 9) | (0x2 << 7)) /*!< Value for Memory configuration - 2Mx32 4 Banks 11 Rows 8 Columns */ +#define EMC_DYN_CONFIG_16Mx8_4BANKS_12ROWS_10COLS ((0x2 << 9) | (0x0 << 7)) /*!< Value for Memory configuration - 16Mx8 4 Banks 12 Rows 10 Columns */ +#define EMC_DYN_CONFIG_8Mx16_4BANKS_12ROWS_9COLS ((0x2 << 9) | (0x1 << 7)) /*!< Value for Memory configuration - 8Mx16 4 Banks 12 Rows 9 Columns */ +#define EMC_DYN_CONFIG_4Mx32_4BANKS_12ROWS_8COLS ((0x2 << 9) | (0x2 << 7)) /*!< Value for Memory configuration - 4Mx32 4 Banks 12 Rows 8 Columns */ +#define EMC_DYN_CONFIG_32Mx8_4BANKS_13ROWS_10COLS ((0x3 << 9) | (0x0 << 7)) /*!< Value for Memory configuration - 32Mx8 4 Banks 13 Rows 10 Columns */ +#define EMC_DYN_CONFIG_16Mx16_4BANKS_13ROWS_9COLS ((0x3 << 9) | (0x1 << 7)) /*!< Value for Memory configuration - 16Mx16 4 Banks 13 Rows 8 Columns */ +#define EMC_DYN_CONFIG_8Mx32_4BANKS_13ROWS_8COLS ((0x3 << 9) | (0x2 << 7)) /*!< Value for Memory configuration - 8Mx32 4 Banks 13 Rows 8 Columns */ +#define EMC_DYN_CONFIG_64Mx8_4BANKS_13ROWS_11COLS ((0x4 << 9) | (0x0 << 7)) /*!< Value for Memory configuration - 64Mx8 4 Banks 13 Rows 11 Columns */ +#define EMC_DYN_CONFIG_32Mx16_4BANKS_13ROWS_10COLS ((0x4 << 9) | (0x1 << 7)) /*!< Value for Memory configuration - 32Mx16 4 Banks 13 Rows 10 Columns */ + +/*!< Dynamic Memory Mode Register Bit Definition */ +#define EMC_DYN_MODE_BURST_LEN_BIT (0) /*!< Starting bit No. of Burst Length in Dynamic Memory Mode Register */ +#define EMC_DYN_MODE_BURST_LEN_1 (0) /*!< Value to set Burst Length to 1 in Dynamic Memory Mode Register */ +#define EMC_DYN_MODE_BURST_LEN_2 (1) /*!< Value to set Burst Length to 2 in Dynamic Memory Mode Register */ +#define EMC_DYN_MODE_BURST_LEN_4 (2) /*!< Value to set Burst Length to 4 in Dynamic Memory Mode Register */ +#define EMC_DYN_MODE_BURST_LEN_8 (3) /*!< Value to set Burst Length to 8 in Dynamic Memory Mode Register */ +#define EMC_DYN_MODE_BURST_LEN_FULL (7) /*!< Value to set Burst Length to Full in Dynamic Memory Mode Register */ + +#define EMC_DYN_MODE_BURST_TYPE_BIT (3) /*!< Burst Type bit in Dynamic Memory Mode Register */ +#define EMC_DYN_MODE_BURST_TYPE_SEQUENTIAL (0 << EMC_DYN_MODE_BURST_TYPE_BIT) /*!< Burst Type Sequential in Dynamic Memory Mode Register */ +#define EMC_DYN_MODE_BURST_TYPE_INTERLEAVE (1 << EMC_DYN_MODE_BURST_TYPE_BIT) /*!< Burst Type Interleaved in Dynamic Memory Mode Register */ + +/*!< CAS Latency in Dynamic Mode Register */ +#define EMC_DYN_MODE_CAS_BIT (4) /*!< CAS latency starting bit in Dynamic Memory Mode register */ +#define EMC_DYN_MODE_CAS_1 (1 << EMC_DYN_MODE_CAS_BIT) /*!< value for CAS latency of 1 cycle */ +#define EMC_DYN_MODE_CAS_2 (2 << EMC_DYN_MODE_CAS_BIT) /*!< value for CAS latency of 2 cycle */ +#define EMC_DYN_MODE_CAS_3 (3 << EMC_DYN_MODE_CAS_BIT) /*!< value for CAS latency of 3 cycle */ + +/*!< Operation Mode in Dynamic Mode register */ +#define EMC_DYN_MODE_OPMODE_BIT (7) /*!< Dynamic Mode Operation bit */ +#define EMC_DYN_MODE_OPMODE_STANDARD (0 << EMC_DYN_MODE_OPMODE_BIT) /*!< Value for Dynamic standard operation Mode */ + +/*!< Write Burst Mode in Dynamic Mode register */ +#define EMC_DYN_MODE_WBMODE_BIT (9) /*!< Write Burst Mode bit */ +#define EMC_DYN_MODE_WBMODE_PROGRAMMED (0 << EMC_DYN_MODE_WBMODE_BIT) /*!< Write Burst Mode programmed */ +#define EMC_DYN_MODE_WBMODE_SINGLE_LOC (1 << EMC_DYN_MODE_WBMODE_BIT) /*!< Write Burst Mode Single LOC */ + +/*!< Dynamic Memory Control Register Bit Definitions */ +#define EMC_DYN_CONTROL_DEEPSLEEP_BIT (13) /*!< Deep sleep Mode bit */ +#define EMC_DYN_CONTROL_ENABLE (0x03) /*!< Control Enable value */ + +/*!< Static Memory Configuration Register Bit Definitions */ +#define EMC_STATIC_CONFIG_MEM_WIDTH_8 (0) /*!< Static Memory Configuration - 8-bit width */ +#define EMC_STATIC_CONFIG_MEM_WIDTH_16 (1) /*!< Static Memory Configuration - 16-bit width */ +#define EMC_STATIC_CONFIG_MEM_WIDTH_32 (2) /*!< Static Memory Configuration - 32-bit width */ + +#define EMC_STATIC_CONFIG_PAGE_MODE_BIT (3) /*!< Page Mode bit No */ +#define EMC_STATIC_CONFIG_PAGE_MODE_ENABLE (1 << EMC_STATIC_CONFIG_PAGE_MODE_BIT) /*!< Value to enable Page Mode */ + +#define EMC_STATIC_CONFIG_CS_POL_BIT (6) /*!< Chip Select bit No */ +#define EMC_STATIC_CONFIG_CS_POL_ACTIVE_HIGH (1 << EMC_STATIC_CONFIG_CS_POL_BIT) /*!< Chip Select polarity - Active High */ +#define EMC_STATIC_CONFIG_CS_POL_ACTIVE_LOW (0 << EMC_STATIC_CONFIG_CS_POL_BIT) /*!< Chip Select polarity - Active Low */ + +#define EMC_STATIC_CONFIG_BLS_BIT (7) /*!< BLS Configuration bit No */ +#define EMC_STATIC_CONFIG_BLS_HIGH (1 << EMC_STATIC_CONFIG_BLS_BIT) /*!< BLS High Configuration value */ +#define EMC_STATIC_CONFIG_BLS_LOW (0 << EMC_STATIC_CONFIG_BLS_BIT) /*!< BLS Low Configuration value */ + +#define EMC_STATIC_CONFIG_EW_BIT (8) /*!< Ext Wait bit No */ +#define EMC_STATIC_CONFIG_EW_ENABLE (1 << EMC_STATIC_CONFIG_EW_BIT) /*!< Ext Wait Enabled value */ +#define EMC_STATIC_CONFIG_EW_DISABLE (0 << EMC_STATIC_CONFIG_EW_BIT) /*!< Ext Wait Diabled value */ + +/*!< Q24.8 Fixed Point Helper */ +#define Q24_8_FP(x) ((x) * 256) +#define EMC_NANOSECOND(x) Q24_8_FP(x) +#define EMC_CLOCK(x) Q24_8_FP(-(x)) + +/** + * @brief EMC Dynamic Device Configuration structure used for IP drivers + */ +typedef struct { + uint32_t BaseAddr; /*!< Base Address */ + uint8_t RAS; /*!< RAS value */ + uint32_t ModeRegister; /*!< Mode Register value */ + uint32_t DynConfig; /*!< Dynamic Configuration value */ +} IP_EMC_DYN_DEVICE_CONFIG_Type; + +/** + * @brief EMC Dynamic Configure Struct + */ +typedef struct { + int32_t RefreshPeriod; /*!< Refresh period */ + uint32_t ReadConfig; /*!< Clock*/ + int32_t tRP; /*!< Precharge Command Period */ + int32_t tRAS; /*!< Active to Precharge Command Period */ + int32_t tSREX; /*!< Self Refresh Exit Time */ + int32_t tAPR; /*!< Last Data Out to Active Time */ + int32_t tDAL; /*!< Data In to Active Command Time */ + int32_t tWR; /*!< Write Recovery Time */ + int32_t tRC; /*!< Active to Active Command Period */ + int32_t tRFC; /*!< Auto-refresh Period */ + int32_t tXSR; /*!< Exit Selt Refresh */ + int32_t tRRD; /*!< Active Bank A to Active Bank B Time */ + int32_t tMRD; /*!< Load Mode register command to Active Command */ + IP_EMC_DYN_DEVICE_CONFIG_Type DevConfig[4]; /*!< Device Configuration array */ +} IP_EMC_DYN_CONFIG_Type; + +/** + * @brief EMC Static Configure Structure + */ +typedef struct { + uint8_t ChipSelect; /*!< Chip select */ + uint32_t Config; /*!< Configuration value */ + int32_t WaitWen; /*!< Write Enable Wait */ + int32_t WaitOen; /*!< Output Enable Wait */ + int32_t WaitRd; /*!< Read Wait */ + int32_t WaitPage; /*!< Page Access Wait */ + int32_t WaitWr; /*!< Write Wait */ + int32_t WaitTurn; /*!< Turn around wait */ +} IP_EMC_STATIC_CONFIG_Type; + +/** + * @brief Initializes the Dynamic Controller + * @param pEMC : Pointer to EMC peripheral + * @param Dynamic_Config : Dynamic Memory Configure Struct + * @param EMC_Clock : Frequency of EMC Clock Out + * @return None + * Initializes the Dynamic Controller according to the specified parameters + * in the IP_EMC_DYN_CONFIG_Type + */ +void IP_EMC_Dynamic_Init(IP_EMC_001_Type *pEMC, IP_EMC_DYN_CONFIG_Type *Dynamic_Config, uint32_t EMC_Clock); + +/** + * @brief Set Deep Sleep Mode for Dynamic Memory Controller + * @param pEMC : Pointer to EMC peripheral + * @param Enable : 1 = enter DeepSleep Mode, 0 = Normal Mode + * @return None + */ +void IP_EMC_Dynamic_DeepSleepMode(IP_EMC_001_Type *pEMC, uint32_t Enable); + +/** + * @brief Enable Dynamic Memory Controller + * @param pEMC : Pointer to EMC peripheral + * @param Enable : 1 = Enable Dynamic Memory Controller, 0 = Disable + * @return None + */ +void IP_EMC_Dynamic_Enable(IP_EMC_001_Type *pEMC, uint8_t Enable); + +/** + * @brief Initializes the Static Controller according to the specified + * parameters in the IP_EMC_STATIC_CONFIG_Type + * @param pEMC : Pointer to EMC peripheral + * @param Static_Config : Static Memory Configure Struct + * @param EMC_Clock : Frequency of EMC Clock Out + * @return None + */ +void IP_EMC_Static_Init(IP_EMC_001_Type *pEMC, IP_EMC_STATIC_CONFIG_Type *Static_Config, uint32_t EMC_Clock); + +/** + * @brief Mirror CS1 to CS0 and DYCS0 + * @param pEMC : Pointer to EMC peripheral + * @param Enable : 1 = Mirror, 0 = Normal Memory Map + * @return None + */ +void IP_EMC_Mirror(IP_EMC_001_Type *pEMC, uint32_t Enable); + +/** + * @brief Enable EMC + * @param pEMC : Pointer to EMC peripheral + * @param Enable : 1 = Enable, 0 = Disable + * @return None + */ +void IP_EMC_Enable(IP_EMC_001_Type *pEMC, uint32_t Enable); + +/** + * @brief Set EMC LowPower Mode + * @param pEMC : Pointer to EMC peripheral + * @param Enable : 1 = Enable, 0 = Disable + * @return None + */ +void IP_EMC_LowPowerMode(IP_EMC_001_Type *pEMC, uint32_t Enable); + +/** + * @brief Initialize EMC + * @param pEMC : Pointer to EMC peripheral + * @param Enable : 1 = Enable, 0 = Disable + * @param ClockRatio : clock out ratio, 0 = 1:1, 1 = 1:2 + * @param EndianMode : Endian Mode, 0 = Little, 1 = Big + * @return None + */ +void IP_EMC_Init(IP_EMC_001_Type *pEMC, uint32_t Enable, uint32_t ClockRatio, uint32_t EndianMode); + +/** + * @brief Set Static Memory Extended Wait in Clock + * @param pEMC : Pointer to EMC peripheral + * @param Wait16Clks : Number of '16 clock' delay cycles + * @return None + */ +void IP_EMC_SetStaticExtendedWait(IP_EMC_001_Type *pEMC, uint32_t Wait16Clks); + +/** + * @} + */ + +#ifdef __cplusplus +} +#endif + +#endif /* __EMC_001_H_ */ diff --git a/bsp/xplorer4330/libraries/lpc_ip/enet_001.c b/bsp/xplorer4330/libraries/lpc_ip/enet_001.c new file mode 100644 index 0000000000..246e2640a4 --- /dev/null +++ b/bsp/xplorer4330/libraries/lpc_ip/enet_001.c @@ -0,0 +1,204 @@ +/* + * @brief Ethernet control functions + * + * @note + * Copyright(C) NXP Semiconductors, 2012 + * All rights reserved. + * + * @par + * Software that is described herein is for illustrative purposes only + * which provides customers with programming information regarding the + * LPC products. This software is supplied "AS IS" without any warranties of + * any kind, and NXP Semiconductors and its licensor disclaim any and + * all warranties, express or implied, including all implied warranties of + * merchantability, fitness for a particular purpose and non-infringement of + * intellectual property rights. NXP Semiconductors assumes no responsibility + * or liability for the use of the software, conveys no license or rights under any + * patent, copyright, mask work right, or any other intellectual property rights in + * or to any products. NXP Semiconductors reserves the right to make changes + * in the software without notification. NXP Semiconductors also makes no + * representation or warranty that such application will be suitable for the + * specified use without further testing or modification. + * + * @par + * Permission to use, copy, modify, and distribute this software and its + * documentation is hereby granted, under NXP Semiconductors' and its + * licensor's relevant copyrights in the software, without fee, provided that it + * is used in conjunction with NXP Semiconductors microcontrollers. This + * copyright, permission, and disclaimer notice must appear in all copies of + * this code. + */ + +#include "enet_001.h" + +/***************************************************************************** + * Private types/enumerations/variables + ****************************************************************************/ + +/* Saved address for PHY and clock divider */ +STATIC uint32_t phyCfg; + +/***************************************************************************** + * Public types/enumerations/variables + ****************************************************************************/ + +/***************************************************************************** + * Private functions + ****************************************************************************/ + +/***************************************************************************** + * Public functions + ****************************************************************************/ + +/* Resets ethernet interface */ +void IP_ENET_Reset(IP_ENET_001_Type *LPC_ENET) +{ + /* This should be called prior to IP_ENET_Init. The MAC controller may + not be ready for a call to init right away so a small delay should + occur after this call. */ + LPC_ENET->DMA_BUS_MODE |= DMA_BM_SWR; +} + +/* Sets the address of the interface */ +void IP_ENET_SetADDR(IP_ENET_001_Type *LPC_ENET, const uint8_t *macAddr) +{ + /* Save MAC address */ + LPC_ENET->MAC_ADDR0_LOW = ((uint32_t) macAddr[3] << 24) | + ((uint32_t) macAddr[2] << 16) | ((uint32_t) macAddr[1] << 8) | + ((uint32_t) macAddr[0]); + LPC_ENET->MAC_ADDR0_HIGH = ((uint32_t) macAddr[5] << 8) | + ((uint32_t) macAddr[4]); +} + +/* Initialize ethernet interface */ +void IP_ENET_Init(IP_ENET_001_Type *LPC_ENET) +{ + /* Enhanced descriptors, burst length = 1 */ + LPC_ENET->DMA_BUS_MODE = DMA_BM_ATDS | DMA_BM_PBL(1) | DMA_BM_RPBL(1); + + /* Initial MAC configuration for checksum offload, full duplex, + 100Mbps, disable receive own in half duplex, inter-frame gap + of 64-bits */ + LPC_ENET->MAC_CONFIG = MAC_CFG_BL(0) | MAC_CFG_IPC | MAC_CFG_DM | + MAC_CFG_DO | MAC_CFG_FES | MAC_CFG_PS | MAC_CFG_IFG(3); + + /* Setup default filter */ + LPC_ENET->MAC_FRAME_FILTER = MAC_FF_PR | MAC_FF_RA; + + /* Flush transmit FIFO */ + LPC_ENET->DMA_OP_MODE = DMA_OM_FTF; + + /* Setup DMA to flush receive FIFOs at 32 bytes, service TX FIFOs at + 64 bytes */ + LPC_ENET->DMA_OP_MODE |= DMA_OM_RTC(1) | DMA_OM_TTC(0); + + /* Clear all MAC interrupts */ + LPC_ENET->DMA_STAT = DMA_ST_ALL; + + /* Enable MAC interrupts */ + LPC_ENET->DMA_INT_EN = 0; +} + +/* Sets up the PHY link clock divider and PHY address */ +void IP_ENET_SetupMII(IP_ENET_001_Type *LPC_ENET, uint32_t div, uint8_t addr) +{ + /* Save clock divider and PHY address in MII address register */ + phyCfg = MAC_MIIA_PA(addr) | MAC_MIIA_CR(div); +} + +/*De-initialize the ethernet interface */ +void IP_ENET_DeInit(IP_ENET_001_Type *LPC_ENET) +{ + /* Disable packet reception */ + LPC_ENET->MAC_CONFIG = 0; + + /* Flush transmit FIFO */ + LPC_ENET->DMA_OP_MODE = DMA_OM_FTF; + + /* Disable receive and transmit DMA processes */ + LPC_ENET->DMA_OP_MODE = 0; +} + +/* Starts a PHY write via the MII */ +void IP_ENET_StartMIIWrite(IP_ENET_001_Type *LPC_ENET, uint8_t reg, uint16_t data) +{ + /* Write value at PHY address and register */ + LPC_ENET->MAC_MII_ADDR = phyCfg | MAC_MIIA_GR(reg) | MAC_MIIA_W; + LPC_ENET->MAC_MII_DATA = (uint32_t) data; + LPC_ENET->MAC_MII_ADDR |= MAC_MIIA_GB; +} + +/*Starts a PHY read via the MII */ +void IP_ENET_StartMIIRead(IP_ENET_001_Type *LPC_ENET, uint8_t reg) +{ + /* Read value at PHY address and register */ + LPC_ENET->MAC_MII_ADDR = phyCfg | MAC_MIIA_GR(reg); + LPC_ENET->MAC_MII_ADDR |= MAC_MIIA_GB; +} + +/* Returns MII link (PHY) busy status */ +bool IP_ENET_IsMIIBusy(IP_ENET_001_Type *LPC_ENET) +{ + if (LPC_ENET->MAC_MII_ADDR & MAC_MIIA_GB) { + return true; + } + + return false; +} + +/* Enables or disables ethernet transmit */ +void IP_ENET_TXEnable(IP_ENET_001_Type *LPC_ENET, bool Enable) +{ + if (Enable) { + /* Descriptor list head pointers must be setup prior to enable */ + LPC_ENET->MAC_CONFIG |= MAC_CFG_TE; + LPC_ENET->DMA_OP_MODE |= DMA_OM_ST; + } + else { + LPC_ENET->MAC_CONFIG &= ~MAC_CFG_TE; + } +} + +/* Enables or disables ethernet packet reception */ +void IP_ENET_RXEnable(IP_ENET_001_Type *LPC_ENET, bool Enable) +{ + if (Enable) { + /* Descriptor list head pointers must be setup prior to enable */ + LPC_ENET->MAC_CONFIG |= MAC_CFG_RE; + LPC_ENET->DMA_OP_MODE |= DMA_OM_SR; + } + else { + LPC_ENET->MAC_CONFIG &= ~MAC_CFG_RE; + } +} + +/* Sets full or half duplex for the interface */ +void IP_ENET_SetDuplex(IP_ENET_001_Type *LPC_ENET, bool full) +{ + if (full) { + LPC_ENET->MAC_CONFIG |= MAC_CFG_DM; + } + else { + LPC_ENET->MAC_CONFIG &= ~MAC_CFG_DM; + } +} + +/* Sets speed for the interface */ +void IP_ENET_SetSpeed(IP_ENET_001_Type *LPC_ENET, bool speed100) +{ + if (speed100) { + LPC_ENET->MAC_CONFIG |= MAC_CFG_FES; + } + else { + LPC_ENET->MAC_CONFIG &= ~MAC_CFG_FES; + } +} + +/* Configures the initial ethernet descriptors */ +void IP_ENET_InitDescriptors(IP_ENET_001_Type *LPC_ENET, + IP_ENET_001_ENHTXDESC_Type *pTXDescs, IP_ENET_001_ENHRXDESC_Type *pRXDescs) +{ + /* Setup descriptor list base addresses */ + LPC_ENET->DMA_TRANS_DES_ADDR = (uint32_t) pTXDescs; + LPC_ENET->DMA_REC_DES_ADDR = (uint32_t) pRXDescs; +} diff --git a/bsp/xplorer4330/libraries/lpc_ip/enet_001.h b/bsp/xplorer4330/libraries/lpc_ip/enet_001.h new file mode 100644 index 0000000000..61917f7e90 --- /dev/null +++ b/bsp/xplorer4330/libraries/lpc_ip/enet_001.h @@ -0,0 +1,608 @@ +/* + * @brief Ethernet control functions + * + * @note + * Copyright(C) NXP Semiconductors, 2012 + * All rights reserved. + * + * @par + * Software that is described herein is for illustrative purposes only + * which provides customers with programming information regarding the + * LPC products. This software is supplied "AS IS" without any warranties of + * any kind, and NXP Semiconductors and its licensor disclaim any and + * all warranties, express or implied, including all implied warranties of + * merchantability, fitness for a particular purpose and non-infringement of + * intellectual property rights. NXP Semiconductors assumes no responsibility + * or liability for the use of the software, conveys no license or rights under any + * patent, copyright, mask work right, or any other intellectual property rights in + * or to any products. NXP Semiconductors reserves the right to make changes + * in the software without notification. NXP Semiconductors also makes no + * representation or warranty that such application will be suitable for the + * specified use without further testing or modification. + * + * @par + * Permission to use, copy, modify, and distribute this software and its + * documentation is hereby granted, under NXP Semiconductors' and its + * licensor's relevant copyrights in the software, without fee, provided that it + * is used in conjunction with NXP Semiconductors microcontrollers. This + * copyright, permission, and disclaimer notice must appear in all copies of + * this code. + */ + +#ifndef __ENET_001_H_ +#define __ENET_001_H_ + +#include "sys_config.h" +#include "cmsis.h" + +#ifdef __cplusplus +extern "C" { +#endif + +/** @defgroup IP_ENET_001 IP: Ethernet register block and driver + * @ingroup IP_Drivers + * @{ + */ + +/** + * @brief 10/100 MII & RMII Ethernet with timestamping register block structure + */ +typedef struct { /*!< ETHERNET Structure */ + __IO uint32_t MAC_CONFIG; /*!< MAC configuration register */ + __IO uint32_t MAC_FRAME_FILTER; /*!< MAC frame filter */ + __IO uint32_t MAC_HASHTABLE_HIGH; /*!< Hash table high register */ + __IO uint32_t MAC_HASHTABLE_LOW; /*!< Hash table low register */ + __IO uint32_t MAC_MII_ADDR; /*!< MII address register */ + __IO uint32_t MAC_MII_DATA; /*!< MII data register */ + __IO uint32_t MAC_FLOW_CTRL; /*!< Flow control register */ + __IO uint32_t MAC_VLAN_TAG; /*!< VLAN tag register */ + __I uint32_t RESERVED0; + __I uint32_t MAC_DEBUG; /*!< Debug register */ + __IO uint32_t MAC_RWAKE_FRFLT; /*!< Remote wake-up frame filter */ + __IO uint32_t MAC_PMT_CTRL_STAT; /*!< PMT control and status */ + __I uint32_t RESERVED1[2]; + __I uint32_t MAC_INTR; /*!< Interrupt status register */ + __IO uint32_t MAC_INTR_MASK; /*!< Interrupt mask register */ + __IO uint32_t MAC_ADDR0_HIGH; /*!< MAC address 0 high register */ + __IO uint32_t MAC_ADDR0_LOW; /*!< MAC address 0 low register */ + __I uint32_t RESERVED2[430]; + __IO uint32_t MAC_TIMESTP_CTRL; /*!< Time stamp control register */ + __IO uint32_t SUBSECOND_INCR; /*!< Sub-second increment register */ + __I uint32_t SECONDS; /*!< System time seconds register */ + __I uint32_t NANOSECONDS; /*!< System time nanoseconds register */ + __IO uint32_t SECONDSUPDATE; /*!< System time seconds update register */ + __IO uint32_t NANOSECONDSUPDATE; /*!< System time nanoseconds update register */ + __IO uint32_t ADDEND; /*!< Time stamp addend register */ + __IO uint32_t TARGETSECONDS; /*!< Target time seconds register */ + __IO uint32_t TARGETNANOSECONDS; /*!< Target time nanoseconds register */ + __IO uint32_t HIGHWORD; /*!< System time higher word seconds register */ + __I uint32_t TIMESTAMPSTAT; /*!< Time stamp status register */ + __IO uint32_t PPSCTRL; /*!< PPS control register */ + __I uint32_t AUXNANOSECONDS; /*!< Auxiliary time stamp nanoseconds register */ + __I uint32_t AUXSECONDS; /*!< Auxiliary time stamp seconds register */ + __I uint32_t RESERVED3[562]; + __IO uint32_t DMA_BUS_MODE; /*!< Bus Mode Register */ + __IO uint32_t DMA_TRANS_POLL_DEMAND; /*!< Transmit poll demand register */ + __IO uint32_t DMA_REC_POLL_DEMAND; /*!< Receive poll demand register */ + __IO uint32_t DMA_REC_DES_ADDR; /*!< Receive descriptor list address register */ + __IO uint32_t DMA_TRANS_DES_ADDR; /*!< Transmit descriptor list address register */ + __IO uint32_t DMA_STAT; /*!< Status register */ + __IO uint32_t DMA_OP_MODE; /*!< Operation mode register */ + __IO uint32_t DMA_INT_EN; /*!< Interrupt enable register */ + __I uint32_t DMA_MFRM_BUFOF; /*!< Missed frame and buffer overflow register */ + __IO uint32_t DMA_REC_INT_WDT; /*!< Receive interrupt watchdog timer register */ + __I uint32_t RESERVED4[8]; + __I uint32_t DMA_CURHOST_TRANS_DES; /*!< Current host transmit descriptor register */ + __I uint32_t DMA_CURHOST_REC_DES; /*!< Current host receive descriptor register */ + __I uint32_t DMA_CURHOST_TRANS_BUF; /*!< Current host transmit buffer address register */ + __I uint32_t DMA_CURHOST_REC_BUF; /*!< Current host receive buffer address register */ +} IP_ENET_001_Type; + +/** + * @brief MAC_CONFIG register bit defines + */ +#define MAC_CFG_RE (1 << 2) /*!< Receiver enable */ +#define MAC_CFG_TE (1 << 3) /*!< Transmitter Enable */ +#define MAC_CFG_DF (1 << 4) /*!< Deferral Check */ +#define MAC_CFG_BL(n) ((n) << 5) /*!< Back-Off Limit */ +#define MAC_CFG_ACS (1 << 7) /*!< Automatic Pad/CRC Stripping */ +#define MAC_CFG_LUD (1 << 8) /*!< Link Up/Down, 1 = up */ +#define MAC_CFG_DR (1 << 9) /*!< Disable Retry */ +#define MAC_CFG_IPC (1 << 10) /*!< Checksum Offload */ +#define MAC_CFG_DM (1 << 11) /*!< Duplex Mode, 1 = full, 0 = half */ +#define MAC_CFG_LM (1 << 12) /*!< Loopback Mode */ +#define MAC_CFG_DO (1 << 13) /*!< Disable Receive Own */ +#define MAC_CFG_FES (1 << 14) /*!< Speed, 1 = 100Mbps, 0 = 10Mbos */ +#define MAC_CFG_PS (1 << 15) /*!< Port select, must always be 1 */ +#define MAC_CFG_DCRS (1 << 16) /*!< Disable carrier sense during transmission */ +#define MAC_CFG_IFG(n) ((n) << 17) /*!< Inter-frame gap, 40..96, n incs by 8 */ +#define MAC_CFG_JE (1 << 20) /*!< Jumbo Frame Enable */ +#define MAC_CFG_JD (1 << 22) /*!< Jabber Disable */ +#define MAC_CFG_WD (1 << 23) /*!< Watchdog Disable */ + +/** + * @brief MAC_FRAME_FILTER register bit defines + */ +#define MAC_FF_PR (1 << 0) /*!< Promiscuous Mode */ +#define MAC_FF_DAIF (1 << 3) /*!< DA Inverse Filtering */ +#define MAC_FF_PM (1 << 4) /*!< Pass All Multicast */ +#define MAC_FF_DBF (1 << 5) /*!< Disable Broadcast Frames */ +#define MAC_FF_PCF(n) ((n) << 6) /*!< Pass Control Frames, n = see user manual */ +#define MAC_FF_SAIF (1 << 8) /*!< SA Inverse Filtering */ +#define MAC_FF_SAF (1 << 9) /*!< Source Address Filter Enable */ +#define MAC_FF_RA (1UL << 31) /*!< Receive all */ + +/** + * @brief MAC_MII_ADDR register bit defines + */ +#define MAC_MIIA_GB (1 << 0) /*!< MII busy */ +#define MAC_MIIA_W (1 << 1) /*!< MII write */ +#define MAC_MIIA_CR(n) ((n) << 2) /*!< CSR clock range, n = see manual */ +#define MAC_MIIA_GR(n) ((n) << 6) /*!< MII register. n = 0..31 */ +#define MAC_MIIA_PA(n) ((n) << 11) /*!< Physical layer address, n = 0..31 */ + +/** + * @brief MAC_MII_DATA register bit defines + */ +#define MAC_MIID_GDMSK (0xFFFF) /*!< MII data mask */ + +/** + * @brief MAC_FLOW_CONTROL register bit defines + */ +#define MAC_FC_FCB (1 << 0) /*!< Flow Control Busy/Backpressure Activate */ +#define MAC_FC_TFE (1 << 1) /*!< Transmit Flow Control Enable */ +#define MAC_FC_RFE (1 << 2) /*!< Receive Flow Control Enable */ +#define MAC_FC_UP (1 << 3) /*!< Unicast Pause Frame Detect */ +#define MAC_FC_PLT(n) ((n) << 4) /*!< Pause Low Threshold, n = see manual */ +#define MAC_FC_DZPQ (1 << 7) /*!< Disable Zero-Quanta Pause */ +#define MAC_FC_PT(n) ((n) << 16) /*!< Pause time */ + +/** + * @brief MAC_VLAN_TAG register bit defines + */ +#define MAC_VT_VL(n) ((n) << 0) /*!< VLAN Tag Identifier for Receive Frames */ +#define MAC_VT_ETC (1 << 7) /*!< Enable 12-Bit VLAN Tag Comparison */ + +/** + * @brief MAC_PMT_CTRL_STAT register bit defines + */ +#define MAC_PMT_PD (1 << 0) /*!< Power-down */ +#define MAC_PMT_MPE (1 << 1) /*!< Magic packet enable */ +#define MAC_PMT_WFE (1 << 2) /*!< Wake-up frame enable */ +#define MAC_PMT_MPR (1 << 5) /*!< Magic Packet Received */ +#define MAC_PMT_WFR (1 << 6) /*!< Wake-up Frame Received */ +#define MAC_PMT_GU (1 << 9) /*!< Global Unicast */ +#define MAC_PMT_WFFRPR (1UL << 31) /*!< Wake-up Frame Filter Register Pointer Reset */ + +/** + * @brief MAC_INTR_MASK register bit defines + */ +#define MAC_IM_PMT (1 << 3) /*!< PMT Interrupt Mask */ + +/** + * @brief MAC_ADDR0_HIGH register bit defines + */ +#define MAC_ADRH_MO (1UL << 31) /*!< Always 1 when writing register */ + +/** + * @brief MAC_ADDR0_HIGH register bit defines + */ +#define MAC_ADRH_MO (1UL << 31) /*!< Always 1 when writing register */ + +/** + * @brief MAC_TIMESTAMP register bit defines + */ +#define MAC_TS_TSENA (1 << 0) /*!< Time Stamp Enable */ +#define MAC_TS_TSCFUP (1 << 1) /*!< Time Stamp Fine or Coarse Update */ +#define MAC_TS_TSINIT (1 << 2) /*!< Time Stamp Initialize */ +#define MAC_TS_TSUPDT (1 << 3) /*!< Time Stamp Update */ +#define MAC_TS_TSTRIG (1 << 4) /*!< Time Stamp Interrupt Trigger Enable */ +#define MAC_TS_TSADDR (1 << 5) /*!< Addend Reg Update */ +#define MAC_TS_TSENAL (1 << 8) /*!< Enable Time Stamp for All Frames */ +#define MAC_TS_TSCTRL (1 << 9) /*!< Time Stamp Digital or Binary rollover control */ +#define MAC_TS_TSVER2 (1 << 10) /*!< Enable PTP packet snooping for version 2 format */ +#define MAC_TS_TSIPENA (1 << 11) /*!< Enable Time Stamp Snapshot for PTP over Ethernet frames */ +#define MAC_TS_TSIPV6E (1 << 12) /*!< Enable Time Stamp Snapshot for IPv6 frames */ +#define MAC_TS_TSIPV4E (1 << 13) /*!< Enable Time Stamp Snapshot for IPv4 frames */ +#define MAC_TS_TSEVNT (1 << 14) /*!< Enable Time Stamp Snapshot for Event Messages */ +#define MAC_TS_TSMSTR (1 << 15) /*!< Enable Snapshot for Messages Relevant to Master */ +#define MAC_TS_TSCLKT(n) ((n) << 16) /*!< Select the type of clock node, n = see menual */ +#define MAC_TS_TSENMA (1 << 18) /*!< Enable MAC address for PTP frame filtering */ + +/** + * @brief DMA_BUS_MODE register bit defines + */ +#define DMA_BM_SWR (1 << 0) /*!< Software reset */ +#define DMA_BM_DA (1 << 1) /*!< DMA arbitration scheme, 1 = TX has priority over TX */ +#define DMA_BM_DSL(n) ((n) << 2) /*!< Descriptor skip length, n = see manual */ +#define DMA_BM_ATDS (1 << 7) /*!< Alternate (Enhanced) descriptor size */ +#define DMA_BM_PBL(n) ((n) << 8) /*!< Programmable burst length, n = see manual */ +#define DMA_BM_PR(n) ((n) << 14) /*!< Rx-to-Tx priority ratio, n = see manual */ +#define DMA_BM_FB (1 << 16) /*!< Fixed burst */ +#define DMA_BM_RPBL(n) ((n) << 17) /*!< RxDMA PBL, n = see manual */ +#define DMA_BM_USP (1 << 23) /*!< Use separate PBL */ +#define DMA_BM_PBL8X (1 << 24) /*!< 8 x PBL mode */ +#define DMA_BM_AAL (1 << 25) /*!< Address-aligned beats */ +#define DMA_BM_MB (1 << 26) /*!< Mixed burst */ +#define DMA_BM_TXPR (1 << 27) /*!< Transmit DMA has higher priority than receive DMA */ + +/** + * @brief DMA_STAT register bit defines + */ +#define DMA_ST_TI (1 << 0) /*!< Transmit interrupt */ +#define DMA_ST_TPS (1 << 1) /*!< Transmit process stopped */ +#define DMA_ST_TU (1 << 2) /*!< Transmit buffer unavailable */ +#define DMA_ST_TJT (1 << 3) /*!< Transmit jabber timeout */ +#define DMA_ST_OVF (1 << 4) /*!< Receive overflow */ +#define DMA_ST_UNF (1 << 5) /*!< Transmit underflow */ +#define DMA_ST_RI (1 << 6) /*!< Receive interrupt */ +#define DMA_ST_RU (1 << 7) /*!< Receive buffer unavailable */ +#define DMA_ST_RPS (1 << 8) /*!< Received process stopped */ +#define DMA_ST_RWT (1 << 9) /*!< Receive watchdog timeout */ +#define DMA_ST_ETI (1 << 10) /*!< Early transmit interrupt */ +#define DMA_ST_FBI (1 << 13) /*!< Fatal bus error interrupt */ +#define DMA_ST_ERI (1 << 14) /*!< Early receive interrupt */ +#define DMA_ST_AIE (1 << 15) /*!< Abnormal interrupt summary */ +#define DMA_ST_NIS (1 << 16) /*!< Normal interrupt summary */ +#define DMA_ST_ALL (0x1E7FF) /*!< All interrupts */ + +/** + * @brief DMA_OP_MODE register bit defines + */ +#define DMA_OM_SR (1 << 1) /*!< Start/stop receive */ +#define DMA_OM_OSF (1 << 2) /*!< Operate on second frame */ +#define DMA_OM_RTC(n) ((n) << 3) /*!< Receive threshold control, n = see manual */ +#define DMA_OM_FUF (1 << 6) /*!< Forward undersized good frames */ +#define DMA_OM_FEF (1 << 7) /*!< Forward error frames */ +#define DMA_OM_ST (1 << 13) /*!< Start/Stop Transmission Command */ +#define DMA_OM_TTC(n) ((n) << 14) /*!< Transmit threshold control, n = see manual */ +#define DMA_OM_FTF (1 << 20) /*!< Flush transmit FIFO */ +#define DMA_OM_TSF (1 << 21) /*!< Transmit store and forward */ +#define DMA_OM_DFF (1 << 24) /*!< Disable flushing of received frames */ +#define DMA_OM_RSF (1 << 25) /*!< Receive store and forward */ +#define DMA_OM_DT (1 << 26) /*!< Disable Dropping of TCP/IP Checksum Error Frames */ + +/** + * @brief DMA_INT_EN register bit defines + */ +#define DMA_IE_TIE (1 << 0) /*!< Transmit interrupt enable */ +#define DMA_IE_TSE (1 << 1) /*!< Transmit stopped enable */ +#define DMA_IE_TUE (1 << 2) /*!< Transmit buffer unavailable enable */ +#define DMA_IE_TJE (1 << 3) /*!< Transmit jabber timeout enable */ +#define DMA_IE_OVE (1 << 4) /*!< Overflow interrupt enable */ +#define DMA_IE_UNE (1 << 5) /*!< Underflow interrupt enable */ +#define DMA_IE_RIE (1 << 6) /*!< Receive interrupt enable */ +#define DMA_IE_RUE (1 << 7) /*!< Receive buffer unavailable enable */ +#define DMA_IE_RSE (1 << 8) /*!< Received stopped enable */ +#define DMA_IE_RWE (1 << 9) /*!< Receive watchdog timeout enable */ +#define DMA_IE_ETE (1 << 10) /*!< Early transmit interrupt enable */ +#define DMA_IE_FBE (1 << 13) /*!< Fatal bus error enable */ +#define DMA_IE_ERE (1 << 14) /*!< Early receive interrupt enable */ +#define DMA_IE_AIE (1 << 15) /*!< Abnormal interrupt summary enable */ +#define DMA_IE_NIE (1 << 16) /*!< Normal interrupt summary enable */ + +/** + * @brief DMA_MFRM_BUFOF register bit defines + */ +#define DMA_MFRM_FMCMSK (0xFFFF) /*!< Number of frames missed mask */ +#define DMA_MFRM_OC (1 << 16) /*!< Overflow bit for missed frame counter */ +#define DMA_MFRM_FMA(n) (((n) & 0x0FFE0000) >> 17) /*!< Number of frames missed by the application mask/shift */ +#define DMA_MFRM_OF (1 << 28) /*!< Overflow bit for FIFO overflow counter */ + +/** + * @brief Common TRAN_DESC_T and TRAN_DESC_ENH_T CTRLSTAT field bit defines + */ +#define TDES_DB (1 << 0) /*!< Deferred Bit */ +#define TDES_UF (1 << 1) /*!< Underflow Error */ +#define TDES_ED (1 << 2) /*!< Excessive Deferral */ +#define TDES_CCMSK(n) (((n) & 0x000000F0) >> 3)/*!< CC: Collision Count (Status field) mask and shift */ +#define TDES_VF (1 << 7) /*!< VLAN Frame */ +#define TDES_EC (1 << 8) /*!< Excessive Collision */ +#define TDES_LC (1 << 9) /*!< Late Collision */ +#define TDES_NC (1 << 10) /*!< No Carrier */ +#define TDES_LCAR (1 << 11) /*!< Loss of Carrier */ +#define TDES_IPE (1 << 12) /*!< IP Payload Error */ +#define TDES_FF (1 << 13) /*!< Frame Flushed */ +#define TDES_JT (1 << 14) /*!< Jabber Timeout */ +#define TDES_ES (1 << 15) /*!< Error Summary */ +#define TDES_IHE (1 << 16) /*!< IP Header Error */ +#define TDES_TTSS (1 << 17) /*!< Transmit Timestamp Status */ +#define TDES_OWN (1UL << 31) /*!< Own Bit */ + +/** + * @brief TRAN_DESC_ENH_T only CTRLSTAT field bit defines + */ +#define TDES_ENH_IC (1UL << 30) /*!< Interrupt on Completion, enhanced descriptor */ +#define TDES_ENH_LS (1 << 29) /*!< Last Segment, enhanced descriptor */ +#define TDES_ENH_FS (1 << 28) /*!< First Segment, enhanced descriptor */ +#define TDES_ENH_DC (1 << 27) /*!< Disable CRC, enhanced descriptor */ +#define TDES_ENH_DP (1 << 26) /*!< Disable Pad, enhanced descriptor */ +#define TDES_ENH_TTSE (1 << 25) /*!< Transmit Timestamp Enable, enhanced descriptor */ +#define TDES_ENH_CIC(n) ((n) << 22) /*!< Checksum Insertion Control, enhanced descriptor */ +#define TDES_ENH_TER (1 << 21) /*!< Transmit End of Ring, enhanced descriptor */ +#define TDES_ENH_TCH (1 << 20) /*!< Second Address Chained, enhanced descriptor */ + +/** + * @brief TRAN_DESC_T only BSIZE field bit defines + */ +#define TDES_NORM_IC (1UL << 31) /*!< Interrupt on Completion, normal descriptor */ +#define TDES_NORM_FS (1 << 30) /*!< First Segment, normal descriptor */ +#define TDES_NORM_LS (1 << 29) /*!< Last Segment, normal descriptor */ +#define TDES_NORM_CIC(n) ((n) << 27) /*!< Checksum Insertion Control, normal descriptor */ +#define TDES_NORM_DC (1 << 26) /*!< Disable CRC, normal descriptor */ +#define TDES_NORM_TER (1 << 25) /*!< Transmit End of Ring, normal descriptor */ +#define TDES_NORM_TCH (1 << 24) /*!< Second Address Chained, normal descriptor */ +#define TDES_NORM_DP (1 << 23) /*!< Disable Pad, normal descriptor */ +#define TDES_NORM_TTSE (1 << 22) /*!< Transmit Timestamp Enable, normal descriptor */ +#define TDES_NORM_BS2(n) (((n) & 0x3FF) << 11) /*!< Buffer 2 size, normal descriptor */ +#define TDES_NORM_BS1(n) (((n) & 0x3FF) << 0) /*!< Buffer 1 size, normal descriptor */ + +/** + * @brief TRAN_DESC_ENH_T only BSIZE field bit defines + */ +#define TDES_ENH_BS2(n) (((n) & 0xFFF) << 16) /*!< Buffer 2 size, enhanced descriptor */ +#define TDES_ENH_BS1(n) (((n) & 0xFFF) << 0) /*!< Buffer 1 size, enhanced descriptor */ + +/** + * @brief Common REC_DESC_T and REC_DESC_ENH_T STATUS field bit defines + */ +#define RDES_ESA (1 << 0) /*!< Extended Status Available/Rx MAC Address */ +#define RDES_CE (1 << 1) /*!< CRC Error */ +#define RDES_DRE (1 << 2) /*!< Dribble Bit Error */ +#define RDES_RE (1 << 3) /*!< Receive Error */ +#define RDES_RWT (1 << 4) /*!< Receive Watchdog Timeout */ +#define RDES_FT (1 << 5) /*!< Frame Type */ +#define RDES_LC (1 << 6) /*!< Late Collision */ +#define RDES_TSA (1 << 7) /*!< Timestamp Available/IP Checksum Error (Type1) /Giant Frame */ +#define RDES_LS (1 << 8) /*!< Last Descriptor */ +#define RDES_FS (1 << 9) /*!< First Descriptor */ +#define RDES_VLAN (1 << 10) /*!< VLAN Tag */ +#define RDES_OE (1 << 11) /*!< Overflow Error */ +#define RDES_LE (1 << 12) /*!< Length Error */ +#define RDES_SAF (1 << 13) /*!< Source Address Filter Fail */ +#define RDES_DE (1 << 14) /*!< Descriptor Error */ +#define RDES_ES (1 << 15) /*!< ES: Error Summary */ +#define RDES_FLMSK(n) (((n) & 0x3FFF0000) >> 16)/*!< Frame Length mask and shift */ +#define RDES_AFM (1 << 30) /*!< Destination Address Filter Fail */ +#define RDES_OWN (1UL << 31) /*!< Own Bit */ + +/** + * @brief Common REC_DESC_T and REC_DESC_ENH_T CTRL field bit defines + */ +#define RDES_DINT (1UL << 31) /*!< Disable interrupt on completion */ + +/** + * @brief REC_DESC_T pnly CTRL field bit defines + */ +#define RDES_NORM_RER (1 << 25) /*!< Receive End of Ring, normal descriptor */ +#define RDES_NORM_RCH (1 << 24) /*!< Second Address Chained, normal descriptor */ +#define RDES_NORM_BS2(n) (((n) & 0x3FF) << 11) /*!< Buffer 2 size, normal descriptor */ +#define RDES_NORM_BS1(n) (((n) & 0x3FF) << 0) /*!< Buffer 1 size, normal descriptor */ + +/** + * @brief REC_DESC_ENH_T only CTRL field bit defines + */ +#define RDES_ENH_RER (1 << 15) /*!< Receive End of Ring, enhanced descriptor */ +#define RDES_ENH_RCH (1 << 14) /*!< Second Address Chained, enhanced descriptor */ +#define RDES_ENH_BS2(n) (((n) & 0xFFF) << 16) /*!< Buffer 2 size, enhanced descriptor */ +#define RDES_ENH_BS1(n) (((n) & 0xFFF) << 0) /*!< Buffer 1 size, enhanced descriptor */ + +/** + * @brief REC_DESC_ENH_T only EXTSTAT field bit defines + */ +#define RDES_ENH_IPPL(n) (((n) & 0x7) >> 2) /*!< IP Payload Type mask and shift, enhanced descripto */ +#define RDES_ENH_IPHE (1 << 3) /*!< IP Header Error, enhanced descripto */ +#define RDES_ENH_IPPLE (1 << 4) /*!< IP Payload Error, enhanced descripto */ +#define RDES_ENH_IPCSB (1 << 5) /*!< IP Checksum Bypassed, enhanced descripto */ +#define RDES_ENH_IPV4 (1 << 6) /*!< IPv4 Packet Received, enhanced descripto */ +#define RDES_ENH_IPV6 (1 << 7) /*!< IPv6 Packet Received, enhanced descripto */ +#define RDES_ENH_MTMSK(n) (((n) & 0xF) >> 8) /*!< Message Type mask and shift, enhanced descripto */ + +/** + * @brief Maximum size of an ethernet buffer + */ +#define EMAC_ETH_MAX_FLEN (1536) + +/** + * @brief Structure of a transmit descriptor (without timestamp) + */ +typedef struct { + __IO uint32_t CTRLSTAT; /*!< TDES control and status word */ + __IO uint32_t BSIZE; /*!< Buffer 1/2 byte counts */ + __IO uint32_t B1ADD; /*!< Buffer 1 address */ + __IO uint32_t B2ADD; /*!< Buffer 2 or next descriptor address */ +} IP_ENET_001_TXDESC_Type; + +/** + * @brief Structure of a enhanced transmit descriptor (with timestamp) + */ +typedef struct { + __IO uint32_t CTRLSTAT; /*!< TDES control and status word */ + __IO uint32_t BSIZE; /*!< Buffer 1/2 byte counts */ + __IO uint32_t B1ADD; /*!< Buffer 1 address */ + __IO uint32_t B2ADD; /*!< Buffer 2 or next descriptor address */ + __IO uint32_t TDES4; /*!< Reserved */ + __IO uint32_t TDES5; /*!< Reserved */ + __IO uint32_t TTSL; /*!< Timestamp value low */ + __IO uint32_t TTSH; /*!< Timestamp value high */ +} IP_ENET_001_ENHTXDESC_Type; + +/** + * @brief Structure of a receive descriptor (without timestamp) + */ +typedef struct { + __IO uint32_t STATUS; /*!< RDES status word */ + __IO uint32_t CTRL; /*!< Buffer 1/2 byte counts and control */ + __IO uint32_t B1ADD; /*!< Buffer 1 address */ + __IO uint32_t B2ADD; /*!< Buffer 2 or next descriptor address */ +} IP_ENET_001_RXDESC_Type; + +/** + * @brief Structure of a enhanced receive descriptor (with timestamp) + */ +typedef struct { + __IO uint32_t STATUS; /*!< RDES status word */ + __IO uint32_t CTRL; /*!< Buffer 1/2 byte counts */ + __IO uint32_t B1ADD; /*!< Buffer 1 address */ + __IO uint32_t B2ADD; /*!< Buffer 2 or next descriptor address */ + __IO uint32_t EXTSTAT; /*!< Extended Status */ + __IO uint32_t RDES5; /*!< Reserved */ + __IO uint32_t RTSL; /*!< Timestamp value low */ + __IO uint32_t RTSH; /*!< Timestamp value high */ +} IP_ENET_001_ENHRXDESC_Type; + +/** + * @brief Resets the ethernet interface + * @param LPC_ENET : Pointer to selected ENET peripheral + * @return Nothing + * Resets the ethernet interface. This should be called prior to + * IP_ENET_Init with a small delay after this call. + */ +void IP_ENET_Reset(IP_ENET_001_Type *LPC_ENET); + +/** + * @brief Sets the address of the interface + * @param LPC_ENET : Pointer to selected ENET peripheral + * @param macAddr : Pointer to the 6 bytes used for the MAC address + * @return Nothing + */ +void IP_ENET_SetADDR(IP_ENET_001_Type *LPC_ENET, const uint8_t *macAddr); + +/** + * @brief Initialize ethernet interface + * @param LPC_ENET : Pointer to selected ENET peripheral + * @return Nothing + * Performs basic initialization of the ethernet interface in a default + * state. This is enough to place the interface in a usable state, but + * may require more setup outside this function. + */ +void IP_ENET_Init(IP_ENET_001_Type *LPC_ENET); + +/** + * @brief Sets up the PHY link clock divider and PHY address + * @param LPC_ENET : Pointer to selected ENET peripheral + * @param div : Divider value, may vary per chip + * @param addr : PHY address, used with MII read and write + * @return Nothing + */ +void IP_ENET_SetupMII(IP_ENET_001_Type *LPC_ENET, uint32_t div, uint8_t addr); + +/** + * @brief De-initialize the ethernet interface + * @param LPC_ENET : Pointer to selected ENET peripheral + * @return Nothing + */ +void IP_ENET_DeInit(IP_ENET_001_Type *LPC_ENET); + +/** + * @brief Starts a PHY write via the MII + * @param LPC_ENET : Pointer to selected ENET peripheral + * @param reg : PHY register to write + * @param data : Data to write to PHY register + * @return Nothing + * Start a PHY write operation. Does not block, requires calling + * IP_ENET_IsMIIBusy to determine when write is complete. + */ +void IP_ENET_StartMIIWrite(IP_ENET_001_Type *LPC_ENET, uint8_t reg, uint16_t data); + +/** + * @brief Starts a PHY read via the MII + * @param LPC_ENET : Pointer to selected ENET peripheral + * @param reg : PHY register to read + * @return Nothing + * Start a PHY read operation. Does not block, requires calling + * IP_ENET_IsMIIBusy to determine when read is complete and calling + * IP_ENET_ReadMIIData to get the data. + */ +void IP_ENET_StartMIIRead(IP_ENET_001_Type *LPC_ENET, uint8_t reg); + +/** + * @brief Returns MII link (PHY) busy status + * @param LPC_ENET : Pointer to selected ENET peripheral + * @return Returns true if busy, otherwise false + */ +bool IP_ENET_IsMIIBusy(IP_ENET_001_Type *LPC_ENET); + +/** + * @brief Returns the value read from the PHY + * @param LPC_ENET : Pointer to selected ENET peripheral + * @return Read value from PHY + */ +STATIC INLINE uint16_t IP_ENET_ReadMIIData(IP_ENET_001_Type *LPC_ENET) +{ + return LPC_ENET->MAC_MII_DATA; +} + +/** + * @brief Enables or disables ethernet transmit + * @param LPC_ENET : Pointer to selected ENET peripheral + * @param Enable : true to enable transmit, false to disable + * @return Nothing + */ +void IP_ENET_TXEnable(IP_ENET_001_Type *LPC_ENET, bool Enable); + +/** + * @brief Enables or disables ethernet packet reception + * @param LPC_ENET : Pointer to selected ENET peripheral + * @param Enable : true to enable receive, false to disable + * @return Nothing + */ +void IP_ENET_RXEnable(IP_ENET_001_Type *LPC_ENET, bool Enable); + +/** + * @brief Sets full or half duplex for the interface + * @param LPC_ENET : Pointer to selected ENET peripheral + * @param full : true to selected full duplex, false for half + * @return Nothing + */ +void IP_ENET_SetDuplex(IP_ENET_001_Type *LPC_ENET, bool full); + +/** + * @brief Sets speed for the interface + * @param LPC_ENET : Pointer to selected ENET peripheral + * @param speed100 : true to select 100Mbps mode, false for 10Mbps + * @return Nothing + */ +void IP_ENET_SetSpeed(IP_ENET_001_Type *LPC_ENET, bool speed100); + +/** + * @brief Configures the initial ethernet descriptors + * @param LPC_ENET : Pointer to selected ENET peripheral + * @param pTXDescs : Pointer to TX descriptor list + * @param pRXDescs : Pointer to RX descriptor list + * @return Nothing + */ +void IP_ENET_InitDescriptors(IP_ENET_001_Type *LPC_ENET, + IP_ENET_001_ENHTXDESC_Type *pTXDescs, IP_ENET_001_ENHRXDESC_Type *pRXDescs); + +/** + * @brief Starts receive polling of RX descriptors + * @param LPC_ENET : Pointer to selected ENET peripheral + * @return Nothing + */ +STATIC INLINE void IP_ENET_RXStart(IP_ENET_001_Type *LPC_ENET) +{ + /* Start receive polling */ + LPC_ENET->DMA_REC_POLL_DEMAND = 1; +} + +/** + * @brief Starts transmit polling of TX descriptors + * @param LPC_ENET : Pointer to selected ENET peripheral + * @return Nothing + */ +STATIC INLINE void IP_ENET_TXStart(IP_ENET_001_Type *LPC_ENET) +{ + /* Start transmit polling */ + LPC_ENET->DMA_TRANS_POLL_DEMAND = 1; +} + +/** + * @} + */ + +#ifdef __cplusplus +} +#endif + +#endif /* __ENET_001_H_ */ diff --git a/bsp/xplorer4330/libraries/lpc_ip/fpu_init.c b/bsp/xplorer4330/libraries/lpc_ip/fpu_init.c new file mode 100644 index 0000000000..9f44027240 --- /dev/null +++ b/bsp/xplorer4330/libraries/lpc_ip/fpu_init.c @@ -0,0 +1,94 @@ +/* + * @brief FPU init code + * + * @note + * Copyright(C) NXP Semiconductors, 2012 + * All rights reserved. + * + * @par + * Software that is described herein is for illustrative purposes only + * which provides customers with programming information regarding the + * LPC products. This software is supplied "AS IS" without any warranties of + * any kind, and NXP Semiconductors and its licensor disclaim any and + * all warranties, express or implied, including all implied warranties of + * merchantability, fitness for a particular purpose and non-infringement of + * intellectual property rights. NXP Semiconductors assumes no responsibility + * or liability for the use of the software, conveys no license or rights under any + * patent, copyright, mask work right, or any other intellectual property rights in + * or to any products. NXP Semiconductors reserves the right to make changes + * in the software without notification. NXP Semiconductors also makes no + * representation or warranty that such application will be suitable for the + * specified use without further testing or modification. + * + * @par + * Permission to use, copy, modify, and distribute this software and its + * documentation is hereby granted, under NXP Semiconductors' and its + * licensor's relevant copyrights in the software, without fee, provided that it + * is used in conjunction with NXP Semiconductors microcontrollers. This + * copyright, permission, and disclaimer notice must appear in all copies of + * this code. + */ + +#if defined(CORE_M4) + +#include "stdint.h" + +/***************************************************************************** + * Private types/enumerations/variables + ****************************************************************************/ + +#define LPC_CPACR 0xE000ED88 + +#define SCB_MVFR0 0xE000EF40 +#define SCB_MVFR0_RESET 0x10110021 + +#define SCB_MVFR1 0xE000EF44 +#define SCB_MVFR1_RESET 0x11000011 + +/***************************************************************************** + * Public types/enumerations/variables + ****************************************************************************/ + +/***************************************************************************** + * Private functions + ****************************************************************************/ + +/***************************************************************************** + * Public functions + ****************************************************************************/ + +/* Early initialization of the FPU */ +void fpuInit(void) +{ + // from arm trm manual: + // ; CPACR is located at address 0xE000ED88 + // LDR.W R0, =0xE000ED88 + // ; Read CPACR + // LDR R1, [R0] + // ; Set bits 20-23 to enable CP10 and CP11 coprocessors + // ORR R1, R1, #(0xF << 20) + // ; Write back the modified value to the CPACR + // STR R1, [R0] + + volatile uint32_t *regCpacr = (uint32_t *) LPC_CPACR; + volatile uint32_t *regMvfr0 = (uint32_t *) SCB_MVFR0; + volatile uint32_t *regMvfr1 = (uint32_t *) SCB_MVFR1; + volatile uint32_t Cpacr; + volatile uint32_t Mvfr0; + volatile uint32_t Mvfr1; + char vfpPresent = 0; + + Mvfr0 = *regMvfr0; + Mvfr1 = *regMvfr1; + + vfpPresent = ((SCB_MVFR0_RESET == Mvfr0) && (SCB_MVFR1_RESET == Mvfr1)); + + if (vfpPresent) { + Cpacr = *regCpacr; + Cpacr |= (0xF << 20); + *regCpacr = Cpacr; // enable CP10 and CP11 for full access + } + +} + +#endif /* defined(CORE_M4 */ diff --git a/bsp/xplorer4330/libraries/lpc_ip/fpu_init.h b/bsp/xplorer4330/libraries/lpc_ip/fpu_init.h new file mode 100644 index 0000000000..02fe935a7c --- /dev/null +++ b/bsp/xplorer4330/libraries/lpc_ip/fpu_init.h @@ -0,0 +1,56 @@ +/* + * @brief FPU init code + * + * @note + * Copyright(C) NXP Semiconductors, 2012 + * All rights reserved. + * + * @par + * Software that is described herein is for illustrative purposes only + * which provides customers with programming information regarding the + * LPC products. This software is supplied "AS IS" without any warranties of + * any kind, and NXP Semiconductors and its licensor disclaim any and + * all warranties, express or implied, including all implied warranties of + * merchantability, fitness for a particular purpose and non-infringement of + * intellectual property rights. NXP Semiconductors assumes no responsibility + * or liability for the use of the software, conveys no license or rights under any + * patent, copyright, mask work right, or any other intellectual property rights in + * or to any products. NXP Semiconductors reserves the right to make changes + * in the software without notification. NXP Semiconductors also makes no + * representation or warranty that such application will be suitable for the + * specified use without further testing or modification. + * + * @par + * Permission to use, copy, modify, and distribute this software and its + * documentation is hereby granted, under NXP Semiconductors' and its + * licensor's relevant copyrights in the software, without fee, provided that it + * is used in conjunction with NXP Semiconductors microcontrollers. This + * copyright, permission, and disclaimer notice must appear in all copies of + * this code. + */ + +#ifndef __FPU_INIT_H_ +#define __FPU_INIT_H_ + +#if defined(CORE_M4) + +/** + * @defgroup IP_FPU_CMX_001 IP: FPU initialization + * @ingroup IP_Drivers + * Cortex FPU initialization + * @{ + */ + +/** + * @brief Early initialization of the FPU + * @return Nothing + */ +void fpuInit(void); + +/** + * @} + */ + +#endif /* #if defined */ + +#endif /* __FPU_INIT_H_ */ diff --git a/bsp/xplorer4330/libraries/lpc_ip/gima_001.h b/bsp/xplorer4330/libraries/lpc_ip/gima_001.h new file mode 100644 index 0000000000..be745011ac --- /dev/null +++ b/bsp/xplorer4330/libraries/lpc_ip/gima_001.h @@ -0,0 +1,70 @@ +/* + * @brief Global Input Multiplexer Array control functions + * + * @note + * Copyright(C) NXP Semiconductors, 2012 + * All rights reserved. + * + * @par + * Software that is described herein is for illustrative purposes only + * which provides customers with programming information regarding the + * LPC products. This software is supplied "AS IS" without any warranties of + * any kind, and NXP Semiconductors and its licensor disclaim any and + * all warranties, express or implied, including all implied warranties of + * merchantability, fitness for a particular purpose and non-infringement of + * intellectual property rights. NXP Semiconductors assumes no responsibility + * or liability for the use of the software, conveys no license or rights under any + * patent, copyright, mask work right, or any other intellectual property rights in + * or to any products. NXP Semiconductors reserves the right to make changes + * in the software without notification. NXP Semiconductors also makes no + * representation or warranty that such application will be suitable for the + * specified use without further testing or modification. + * + * @par + * Permission to use, copy, modify, and distribute this software and its + * documentation is hereby granted, under NXP Semiconductors' and its + * licensor's relevant copyrights in the software, without fee, provided that it + * is used in conjunction with NXP Semiconductors microcontrollers. This + * copyright, permission, and disclaimer notice must appear in all copies of + * this code. + */ + +#ifndef __GIMA_001_H_ +#define __GIMA_001_H_ + +#include "sys_config.h" +#include "cmsis.h" + +#ifdef __cplusplus +extern "C" { +#endif + +/** @defgroup IP_GIMA_001 IP: GIMA register block and driver + * @ingroup IP_Drivers + * Global Input Multiplexer Array + * @{ + */ + +/** + * @brief Global Input Multiplexer Array (GIMA) register block structure + */ +typedef struct { /*!< GIMA Structure */ + __IO uint32_t CAP0_IN[4][4]; /*!< Timer x CAP0_y capture input multiplexer (GIMA output ((x*4)+y)) */ + __IO uint32_t CTIN_IN[8]; /*!< SCT CTIN_x capture input multiplexer (GIMA output (16+x)) */ + __IO uint32_t VADC_TRIGGER_IN; /*!< VADC trigger input multiplexer (GIMA output 24) */ + __IO uint32_t EVENTROUTER_13_IN; /*!< Event router input 13 multiplexer (GIMA output 25) */ + __IO uint32_t EVENTROUTER_14_IN; /*!< Event router input 14 multiplexer (GIMA output 26) */ + __IO uint32_t EVENTROUTER_16_IN; /*!< Event router input 16 multiplexer (GIMA output 27) */ + __IO uint32_t ADCSTART0_IN; /*!< ADC start0 input multiplexer (GIMA output 28) */ + __IO uint32_t ADCSTART1_IN; /*!< ADC start1 input multiplexer (GIMA output 29) */ +} IP_GIMA_001_Type; + +/** + * @} + */ + +#ifdef __cplusplus +} +#endif + +#endif /* __GIMA_001_H_ */ diff --git a/bsp/xplorer4330/libraries/lpc_ip/gpdma_001.c b/bsp/xplorer4330/libraries/lpc_ip/gpdma_001.c new file mode 100644 index 0000000000..4626a0ef8e --- /dev/null +++ b/bsp/xplorer4330/libraries/lpc_ip/gpdma_001.c @@ -0,0 +1,216 @@ +/* + * @brief GPDMA Registers and control functions + * + * @note + * Copyright(C) NXP Semiconductors, 2012 + * All rights reserved. + * + * @par + * Software that is described herein is for illustrative purposes only + * which provides customers with programming information regarding the + * LPC products. This software is supplied "AS IS" without any warranties of + * any kind, and NXP Semiconductors and its licensor disclaim any and + * all warranties, express or implied, including all implied warranties of + * merchantability, fitness for a particular purpose and non-infringement of + * intellectual property rights. NXP Semiconductors assumes no responsibility + * or liability for the use of the software, conveys no license or rights under any + * patent, copyright, mask work right, or any other intellectual property rights in + * or to any products. NXP Semiconductors reserves the right to make changes + * in the software without notification. NXP Semiconductors also makes no + * representation or warranty that such application will be suitable for the + * specified use without further testing or modification. + * + * @par + * Permission to use, copy, modify, and distribute this software and its + * documentation is hereby granted, under NXP Semiconductors' and its + * licensor's relevant copyrights in the software, without fee, provided that it + * is used in conjunction with NXP Semiconductors microcontrollers. This + * copyright, permission, and disclaimer notice must appear in all copies of + * this code. + */ + +#include "gpdma_001.h" + +/***************************************************************************** + * Private types/enumerations/variables + ****************************************************************************/ + +/***************************************************************************** + * Public types/enumerations/variables + ****************************************************************************/ + +/***************************************************************************** + * Private functions + ****************************************************************************/ + +/***************************************************************************** + * Public functions + ****************************************************************************/ + +/* Initialize the GPDMA */ +void IP_GPDMA_Init(IP_GPDMA_001_Type *pGPDMA) { + uint8_t i; + /* Reset all channel configuration register */ + for (i = 8; i > 0; i--) { + pGPDMA->CH[i - 1].CONFIG = 0; + } + + /* Clear all DMA interrupt and error flag */ + pGPDMA->INTTCCLEAR = 0xFF; + pGPDMA->INTERRCLR = 0xFF; +} + +/* Read the status from different registers according to the type */ +IntStatus IP_GPDMA_IntGetStatus(IP_GPDMA_001_Type *pGPDMA, GPDMA_Status_Type type, uint8_t channel) { + /** + * TODO check the channel <=8 type is esxited + */ + switch (type) { + case GPDMA_STAT_INT:/* check status of DMA channel interrupts */ + return (IntStatus) (pGPDMA->INTSTAT & (((1UL << channel) & 0xFF))); + + case GPDMA_STAT_INTTC: /* check terminal count interrupt request status for DMA */ + return (IntStatus) (pGPDMA->INTTCSTAT & (((1UL << channel) & 0xFF))); + + case GPDMA_STAT_INTERR: /* check interrupt status for DMA channels */ + return (IntStatus) (pGPDMA->INTERRSTAT & (((1UL << channel) & 0xFF))); + + case GPDMA_STAT_RAWINTTC: /* check status of the terminal count interrupt for DMA channels */ + return (IntStatus) (pGPDMA->RAWINTTCSTAT & (((1UL << channel) & 0xFF))); + + case GPDMA_STAT_RAWINTERR: /* check status of the error interrupt for DMA channels */ + return (IntStatus) (pGPDMA->RAWINTERRSTAT & (((1UL << channel) & 0xFF))); + + default:/* check enable status for DMA channels */ + return (IntStatus) (pGPDMA->ENBLDCHNS & (((1UL << channel) & 0xFF))); + } +} + +/* Clear the Interrupt Flag from different registers according to the type */ +void IP_GPDMA_ClearIntPending(IP_GPDMA_001_Type *pGPDMA, GPDMA_StateClear_Type type, uint8_t channel) { + if (type == GPDMA_STATCLR_INTTC) { + /* clears the terminal count interrupt request on DMA channel */ + pGPDMA->INTTCCLEAR = (((1UL << (channel)) & 0xFF)); + } + else { + /* clear the error interrupt request */ + pGPDMA->INTERRCLR = (((1UL << (channel)) & 0xFF)); + } +} + +/* Enable or Disable the GPDMA Channel */ +void IP_GPDMA_ChannelCmd(IP_GPDMA_001_Type *pGPDMA, uint8_t channelNum, FunctionalState NewState) { + IP_GPDMA_001_CH_Type *pDMAch; + + /* Get Channel pointer */ + pDMAch = (IP_GPDMA_001_CH_Type *) &(pGPDMA->CH[channelNum]); + + if (NewState == ENABLE) { + pDMAch->CONFIG |= GPDMA_DMACCxConfig_E; + } + else { + pDMAch->CONFIG &= ~GPDMA_DMACCxConfig_E; + } +} + +/* Set up the DPDMA according to the specification configuration details */ +Status IP_GPDMA_Setup(IP_GPDMA_001_Type *pGPDMA, + GPDMA_Channel_CFG_Type *GPDMAChannelConfig, + uint32_t GPDMA_LUTPerBurstSrcConn, + uint32_t GPDMA_LUTPerBurstDstConn, + uint32_t GPDMA_LUTPerWidSrcConn, + uint32_t GPDMA_LUTPerWidDstConn, + uint32_t GPDMA_LUTPerAddrSrcConn, + uint32_t GPDMA_LUTPerAddrDstConn, + uint8_t SrcPeripheral, + uint8_t DstPeripheral) +{ + IP_GPDMA_001_CH_Type *pDMAch; + + if (pGPDMA->ENBLDCHNS & ((((1UL << (GPDMAChannelConfig->ChannelNum)) & 0xFF)))) { + /* This channel is enabled, return ERROR, need to release this channel first */ + return ERROR; + } + + /* Get Channel pointer */ + pDMAch = (IP_GPDMA_001_CH_Type *) &(pGPDMA->CH[GPDMAChannelConfig->ChannelNum]); + + /* Reset the Interrupt status */ + pGPDMA->INTTCCLEAR = (((1UL << (GPDMAChannelConfig->ChannelNum)) & 0xFF)); + pGPDMA->INTERRCLR = (((1UL << (GPDMAChannelConfig->ChannelNum)) & 0xFF)); + + /* Assign Linker List Item value */ + pDMAch->LLI = 0;/* Fixed to 0 (no link list) */ + + /* Enable DMA channels, little endian */ + pGPDMA->CONFIG = GPDMA_DMACConfig_E; + while (!(pGPDMA->CONFIG & GPDMA_DMACConfig_E)) {} + + pDMAch->SRCADDR = GPDMAChannelConfig->SrcAddr; + pDMAch->DESTADDR = GPDMAChannelConfig->DstAddr; + + /* Configure DMA Channel, enable Error Counter and Terminate counter */ + pDMAch->CONFIG = GPDMA_DMACCxConfig_IE + | GPDMA_DMACCxConfig_ITC /*| GPDMA_DMACCxConfig_E*/ + | GPDMA_DMACCxConfig_TransferType((uint32_t) GPDMAChannelConfig->TransferType) + | GPDMA_DMACCxConfig_SrcPeripheral(SrcPeripheral) + | GPDMA_DMACCxConfig_DestPeripheral(DstPeripheral); + + switch (GPDMAChannelConfig->TransferType) { + /* Memory to memory */ + case GPDMA_TRANSFERTYPE_M2M_CONTROLLER_DMA: + pDMAch->CONTROL = GPDMA_DMACCxControl_TransferSize(GPDMAChannelConfig->TransferSize) + | GPDMA_DMACCxControl_SBSize((4UL)) /**< Burst size = 32 */ + | GPDMA_DMACCxControl_DBSize((4UL)) /**< Burst size = 32 */ + | GPDMA_DMACCxControl_SWidth(GPDMAChannelConfig->TransferWidth) + | GPDMA_DMACCxControl_DWidth(GPDMAChannelConfig->TransferWidth) + | GPDMA_DMACCxControl_SI + | GPDMA_DMACCxControl_DI + | GPDMA_DMACCxControl_I; + break; + + case GPDMA_TRANSFERTYPE_M2P_CONTROLLER_DMA: + case GPDMA_TRANSFERTYPE_M2P_CONTROLLER_PERIPHERAL: + pDMAch->CONTROL = GPDMA_DMACCxControl_TransferSize((uint32_t) GPDMAChannelConfig->TransferSize) + | GPDMA_DMACCxControl_SBSize(GPDMA_LUTPerBurstDstConn) + | GPDMA_DMACCxControl_DBSize(GPDMA_LUTPerBurstDstConn) + | GPDMA_DMACCxControl_SWidth(GPDMA_LUTPerWidDstConn) + | GPDMA_DMACCxControl_DWidth(GPDMA_LUTPerWidDstConn) + | GPDMA_DMACCxControl_DestTransUseAHBMaster1 + | GPDMA_DMACCxControl_SI + | GPDMA_DMACCxControl_I; + break; + + case GPDMA_TRANSFERTYPE_P2M_CONTROLLER_DMA: + case GPDMA_TRANSFERTYPE_P2M_CONTROLLER_PERIPHERAL: + pDMAch->CONTROL = GPDMA_DMACCxControl_TransferSize((uint32_t) GPDMAChannelConfig->TransferSize) + | GPDMA_DMACCxControl_SBSize(GPDMA_LUTPerBurstSrcConn) + | GPDMA_DMACCxControl_DBSize(GPDMA_LUTPerBurstSrcConn) + | GPDMA_DMACCxControl_SWidth(GPDMA_LUTPerWidSrcConn) + | GPDMA_DMACCxControl_DWidth(GPDMA_LUTPerWidSrcConn) + | GPDMA_DMACCxControl_SrcTransUseAHBMaster1 + | GPDMA_DMACCxControl_DI + | GPDMA_DMACCxControl_I; + break; + + case GPDMA_TRANSFERTYPE_P2P_CONTROLLER_DMA: + case GPDMA_TRANSFERTYPE_P2P_CONTROLLER_DestPERIPHERAL: + case GPDMA_TRANSFERTYPE_P2P_CONTROLLER_SrcPERIPHERAL: + pDMAch->CONTROL = GPDMA_DMACCxControl_TransferSize((uint32_t) GPDMAChannelConfig->TransferSize) + | GPDMA_DMACCxControl_SBSize(GPDMA_LUTPerBurstSrcConn) + | GPDMA_DMACCxControl_DBSize(GPDMA_LUTPerBurstDstConn) + | GPDMA_DMACCxControl_SWidth(GPDMA_LUTPerWidSrcConn) + | GPDMA_DMACCxControl_DWidth(GPDMA_LUTPerWidDstConn) + | GPDMA_DMACCxControl_SrcTransUseAHBMaster1 + | GPDMA_DMACCxControl_DestTransUseAHBMaster1 + | GPDMA_DMACCxControl_I; + + break; + + /* Do not support any more transfer type, return ERROR */ + default: + return ERROR; + } + + return SUCCESS; +} diff --git a/bsp/xplorer4330/libraries/lpc_ip/gpdma_001.h b/bsp/xplorer4330/libraries/lpc_ip/gpdma_001.h new file mode 100644 index 0000000000..b22c950397 --- /dev/null +++ b/bsp/xplorer4330/libraries/lpc_ip/gpdma_001.h @@ -0,0 +1,258 @@ +/* + * @brief GPDMA Registers and control functions + * + * @note + * Copyright(C) NXP Semiconductors, 2012 + * All rights reserved. + * + * @par + * Software that is described herein is for illustrative purposes only + * which provides customers with programming information regarding the + * LPC products. This software is supplied "AS IS" without any warranties of + * any kind, and NXP Semiconductors and its licensor disclaim any and + * all warranties, express or implied, including all implied warranties of + * merchantability, fitness for a particular purpose and non-infringement of + * intellectual property rights. NXP Semiconductors assumes no responsibility + * or liability for the use of the software, conveys no license or rights under any + * patent, copyright, mask work right, or any other intellectual property rights in + * or to any products. NXP Semiconductors reserves the right to make changes + * in the software without notification. NXP Semiconductors also makes no + * representation or warranty that such application will be suitable for the + * specified use without further testing or modification. + * + * @par + * Permission to use, copy, modify, and distribute this software and its + * documentation is hereby granted, under NXP Semiconductors' and its + * licensor's relevant copyrights in the software, without fee, provided that it + * is used in conjunction with NXP Semiconductors microcontrollers. This + * copyright, permission, and disclaimer notice must appear in all copies of + * this code. + */ + +#ifndef __GPDMA_001_H_ +#define __GPDMA_001_H_ + +#include "sys_config.h" +#include "cmsis.h" + +#ifdef __cplusplus +extern "C" { +#endif + +/** @defgroup IP_GPDMA_001 IP: GPDMA register block and driver + * @ingroup IP_Drivers + * General Purpose DMA + * @{ + */ + +/** + * @brief GPDMA Channel register block structure + */ +typedef struct { + __IO uint32_t SRCADDR; /*!< DMA Channel Source Address Register */ + __IO uint32_t DESTADDR; /*!< DMA Channel Destination Address Register */ + __IO uint32_t LLI; /*!< DMA Channel Linked List Item Register */ + __IO uint32_t CONTROL; /*!< DMA Channel Control Register */ + __IO uint32_t CONFIG; /*!< DMA Channel Configuration Register */ + __I uint32_t RESERVED1[3]; +} IP_GPDMA_001_CH_Type; + +#define GPDMA_CHANNELS 8 + +/** + * @brief GPDMA register block + */ +typedef struct { /*!< GPDMA Structure */ + __I uint32_t INTSTAT; /*!< DMA Interrupt Status Register */ + __I uint32_t INTTCSTAT; /*!< DMA Interrupt Terminal Count Request Status Register */ + __O uint32_t INTTCCLEAR; /*!< DMA Interrupt Terminal Count Request Clear Register */ + __I uint32_t INTERRSTAT; /*!< DMA Interrupt Error Status Register */ + __O uint32_t INTERRCLR; /*!< DMA Interrupt Error Clear Register */ + __I uint32_t RAWINTTCSTAT; /*!< DMA Raw Interrupt Terminal Count Status Register */ + __I uint32_t RAWINTERRSTAT; /*!< DMA Raw Error Interrupt Status Register */ + __I uint32_t ENBLDCHNS; /*!< DMA Enabled Channel Register */ + __IO uint32_t SOFTBREQ; /*!< DMA Software Burst Request Register */ + __IO uint32_t SOFTSREQ; /*!< DMA Software Single Request Register */ + __IO uint32_t SOFTLBREQ; /*!< DMA Software Last Burst Request Register */ + __IO uint32_t SOFTLSREQ; /*!< DMA Software Last Single Request Register */ + __IO uint32_t CONFIG; /*!< DMA Configuration Register */ + __IO uint32_t SYNC; /*!< DMA Synchronization Register */ + __I uint32_t RESERVED0[50]; + IP_GPDMA_001_CH_Type CH[GPDMA_CHANNELS]; +} IP_GPDMA_001_Type; + +/** + * @brief Macro defines for DMA channel control registers + */ +#define GPDMA_DMACCxControl_TransferSize(n) (((n & 0xFFF) << 0)) /**< Transfer size*/ +#define GPDMA_DMACCxControl_SBSize(n) (((n & 0x07) << 12)) /**< Source burst size*/ +#define GPDMA_DMACCxControl_DBSize(n) (((n & 0x07) << 15)) /**< Destination burst size*/ +#define GPDMA_DMACCxControl_SWidth(n) (((n & 0x07) << 18)) /**< Source transfer width*/ +#define GPDMA_DMACCxControl_DWidth(n) (((n & 0x07) << 21)) /**< Destination transfer width*/ +#define GPDMA_DMACCxControl_SI ((1UL << 26)) /**< Source increment*/ +#define GPDMA_DMACCxControl_DI ((1UL << 27)) /**< Destination increment*/ +#if defined(CHIP_LPC43XX) || defined(CHIP_LPC18XX) +#define GPDMA_DMACCxControl_SrcTransUseAHBMaster1 ((1UL << 24)) /**< Source AHB master select in 18xx43xx*/ +#define GPDMA_DMACCxControl_DestTransUseAHBMaster1 ((1UL << 25)) /**< Destination AHB master select in 18xx43xx*/ +#else +#define GPDMA_DMACCxControl_SrcTransUseAHBMaster1 0 +#define GPDMA_DMACCxControl_DestTransUseAHBMaster1 0 +#endif +#define GPDMA_DMACCxControl_Prot1 ((1UL << 28)) /**< Indicates that the access is in user mode or privileged mode*/ +#define GPDMA_DMACCxControl_Prot2 ((1UL << 29)) /**< Indicates that the access is bufferable or not bufferable*/ +#define GPDMA_DMACCxControl_Prot3 ((1UL << 30)) /**< Indicates that the access is cacheable or not cacheable*/ +#define GPDMA_DMACCxControl_I ((1UL << 31)) /**< Terminal count interrupt enable bit */ + +/** + * @brief Macro defines for DMA Configuration register + */ +#define GPDMA_DMACConfig_E ((0x01)) /**< DMA Controller enable*/ +#define GPDMA_DMACConfig_M ((0x02)) /**< AHB Master endianness configuration*/ +#define GPDMA_DMACConfig_BITMASK ((0x03)) + +/** + * @brief Macro defines for DMA Channel Configuration registers + */ +#define GPDMA_DMACCxConfig_E ((1UL << 0)) /**< DMA control enable*/ +#define GPDMA_DMACCxConfig_SrcPeripheral(n) (((n & 0x1F) << 1)) /**< Source peripheral*/ +#define GPDMA_DMACCxConfig_DestPeripheral(n) (((n & 0x1F) << 6)) /**< Destination peripheral*/ +#define GPDMA_DMACCxConfig_TransferType(n) (((n & 0x7) << 11)) /**< This value indicates the type of transfer*/ +#define GPDMA_DMACCxConfig_IE ((1UL << 14)) /**< Interrupt error mask*/ +#define GPDMA_DMACCxConfig_ITC ((1UL << 15)) /**< Terminal count interrupt mask*/ +#define GPDMA_DMACCxConfig_L ((1UL << 16)) /**< Lock*/ +#define GPDMA_DMACCxConfig_A ((1UL << 17)) /**< Active*/ +#define GPDMA_DMACCxConfig_H ((1UL << 18)) /**< Halt*/ + +/** + * @brief GPDMA Interrupt Clear Status + */ +typedef enum { + GPDMA_STATCLR_INTTC, /**< GPDMA Interrupt Terminal Count Request Clear */ + GPDMA_STATCLR_INTERR /**< GPDMA Interrupt Error Clear */ +} GPDMA_StateClear_Type; + +/** + * @brief GPDMA Type of Interrupt Status + */ +typedef enum { + GPDMA_STAT_INT, /**< GPDMA Interrupt Status */ + GPDMA_STAT_INTTC, /**< GPDMA Interrupt Terminal Count Request Status */ + GPDMA_STAT_INTERR, /**< GPDMA Interrupt Error Status */ + GPDMA_STAT_RAWINTTC, /**< GPDMA Raw Interrupt Terminal Count Status */ + GPDMA_STAT_RAWINTERR, /**< GPDMA Raw Error Interrupt Status */ + GPDMA_STAT_ENABLED_CH /**< GPDMA Enabled Channel Status */ +} GPDMA_Status_Type; + +/** + * @brief GPDMA Type of DMA controller + */ +typedef enum { + GPDMA_TRANSFERTYPE_M2M_CONTROLLER_DMA = ((0UL)), /**< Memory to memory - DMA control */ + GPDMA_TRANSFERTYPE_M2P_CONTROLLER_DMA = ((1UL)), /**< Memory to peripheral - DMA control */ + GPDMA_TRANSFERTYPE_P2M_CONTROLLER_DMA = ((2UL)), /**< Peripheral to memory - DMA control */ + GPDMA_TRANSFERTYPE_P2P_CONTROLLER_DMA = ((3UL)), /**< Source peripheral to destination peripheral - DMA control */ + GPDMA_TRANSFERTYPE_P2P_CONTROLLER_DestPERIPHERAL = ((4UL)), /**< Source peripheral to destination peripheral - destination peripheral control */ + GPDMA_TRANSFERTYPE_M2P_CONTROLLER_PERIPHERAL = ((5UL)), /**< Memory to peripheral - peripheral control */ + GPDMA_TRANSFERTYPE_P2M_CONTROLLER_PERIPHERAL = ((6UL)), /**< Peripheral to memory - peripheral control */ + GPDMA_TRANSFERTYPE_P2P_CONTROLLER_SrcPERIPHERAL = ((7UL)) /**< Source peripheral to destination peripheral - source peripheral control */ +} FlowControlType; + +/** + * @brief GPDMA structure using for DMA configuration + */ +typedef struct { + uint32_t ChannelNum; /**< DMA channel number, should be in + * range from 0 to 7. + * Note: DMA channel 0 has the highest priority + * and DMA channel 7 the lowest priority. + */ + uint32_t TransferSize; /**< Length/Size of transfer */ + uint32_t TransferWidth; /**< Transfer width - used for TransferType is GPDMA_TRANSFERTYPE_M2M only */ + uint32_t SrcAddr; /**< Physical Source Address, used in case TransferType is chosen as + * GPDMA_TRANSFERTYPE_M2M or GPDMA_TRANSFERTYPE_M2P */ + uint32_t DstAddr; /**< Physical Destination Address, used in case TransferType is chosen as + * GPDMA_TRANSFERTYPE_M2M or GPDMA_TRANSFERTYPE_P2M */ + uint32_t TransferType; /**< Transfer Type, should be one of the following: + * - GPDMA_TRANSFERTYPE_M2M: Memory to memory - DMA control + * - GPDMA_TRANSFERTYPE_M2P: Memory to peripheral - DMA control + * - GPDMA_TRANSFERTYPE_P2M: Peripheral to memory - DMA control + * - GPDMA_TRANSFERTYPE_P2P: Source peripheral to destination peripheral - DMA control + */ +} GPDMA_Channel_CFG_Type; + +/** + * @brief Initialize the GPDMA + * @param pGPDMA : The Base Address of GPDMA on the chip + * @return Nothing + */ +void IP_GPDMA_Init(IP_GPDMA_001_Type *pGPDMA); + +/** + * @brief Set up the DPDMA according to the specification configuration details + * @param pGPDMA : The Base Address of GPDMA on the chip + * @param GPDMAChannelConfig : Configuration struct + * @param GPDMA_LUTPerBurstSrcConn : Peripheral Source burst size + * @param GPDMA_LUTPerBurstDstConn : Peripheral Destination burst size + * @param GPDMA_LUTPerWidSrcConn : Peripheral Source transfer width + * @param GPDMA_LUTPerWidDstConn : Peripheral Destination transfer width + * @param GPDMA_LUTPerAddrSrcConn : Peripheral Source Address + * @param GPDMA_LUTPerAddrDstConn : Peripheral Destination Address + * @param SrcPeripheral : Peripheral Source ID + * @param DstPeripheral : Peripheral Destination ID + * @return SUCCESS or ERROR on setup failure + */ +Status IP_GPDMA_Setup(IP_GPDMA_001_Type *pGPDMA, + GPDMA_Channel_CFG_Type *GPDMAChannelConfig, + uint32_t GPDMA_LUTPerBurstSrcConn, + uint32_t GPDMA_LUTPerBurstDstConn, + uint32_t GPDMA_LUTPerWidSrcConn, + uint32_t GPDMA_LUTPerWidDstConn, + uint32_t GPDMA_LUTPerAddrSrcConn, + uint32_t GPDMA_LUTPerAddrDstConn, + uint8_t SrcPeripheral, + uint8_t DstPeripheral); + +/** + * @brief Read the status from different registers according to the type + * @param pGPDMA : The Base Address of GPDMA on the chip + * @param type : Status mode, should be: + * - GPDMA_STAT_INT : GPDMA Interrupt Status + * - GPDMA_STAT_INTTC : GPDMA Interrupt Terminal Count Request Status + * - GPDMA_STAT_INTERR : GPDMA Interrupt Error Status + * - GPDMA_STAT_RAWINTTC : GPDMA Raw Interrupt Terminal Count Status + * - GPDMA_STAT_RAWINTERR : GPDMA Raw Error Interrupt Status + * - GPDMA_STAT_ENABLED_CH : GPDMA Enabled Channel Status + * @param channel : The GPDMA channel : 0 - 7 + * @return SET is interrupt is pending or RESET if not pending + */ +IntStatus IP_GPDMA_IntGetStatus(IP_GPDMA_001_Type *pGPDMA, GPDMA_Status_Type type, uint8_t channel); + +/** + * @brief Clear the Interrupt Flag from different registers according to the type + * @param pGPDMA : The Base Address of GPDMA on the chip + * @param type : Flag mode, should be: + * - GPDMA_STATCLR_INTTC : GPDMA Interrupt Terminal Count Request + * - GPDMA_STATCLR_INTERR : GPDMA Interrupt Error + * @param channel : The GPDMA channel : 0 - 7 + * @return Nothing + */ +void IP_GPDMA_ClearIntPending(IP_GPDMA_001_Type *pGPDMA, GPDMA_StateClear_Type type, uint8_t channel); + +/** + * @brief Enable or Disable the GPDMA Channel + * @param pGPDMA : The Base Address of GPDMA on the chip + * @param channelNum : The GPDMA channel : 0 - 7 + * @param NewState : ENABLE to enable GPDMA or DISABLE to disable GPDMA + * @return Nothing + */ +void IP_GPDMA_ChannelCmd(IP_GPDMA_001_Type *pGPDMA, uint8_t channelNum, FunctionalState NewState); + +/** + * @} + */ + +#ifdef __cplusplus +} +#endif + +#endif /* __GPDMA_001_H_ */ diff --git a/bsp/xplorer4330/libraries/lpc_ip/gpio_001.h b/bsp/xplorer4330/libraries/lpc_ip/gpio_001.h new file mode 100644 index 0000000000..da955518b4 --- /dev/null +++ b/bsp/xplorer4330/libraries/lpc_ip/gpio_001.h @@ -0,0 +1,151 @@ +/* + * @brief GPIO Registers and Functions + * + * @note + * Copyright(C) NXP Semiconductors, 2012 + * All rights reserved. + * + * @par + * Software that is described herein is for illustrative purposes only + * which provides customers with programming information regarding the + * LPC products. This software is supplied "AS IS" without any warranties of + * any kind, and NXP Semiconductors and its licensor disclaim any and + * all warranties, express or implied, including all implied warranties of + * merchantability, fitness for a particular purpose and non-infringement of + * intellectual property rights. NXP Semiconductors assumes no responsibility + * or liability for the use of the software, conveys no license or rights under any + * patent, copyright, mask work right, or any other intellectual property rights in + * or to any products. NXP Semiconductors reserves the right to make changes + * in the software without notification. NXP Semiconductors also makes no + * representation or warranty that such application will be suitable for the + * specified use without further testing or modification. + * + * @par + * Permission to use, copy, modify, and distribute this software and its + * documentation is hereby granted, under NXP Semiconductors' and its + * licensor's relevant copyrights in the software, without fee, provided that it + * is used in conjunction with NXP Semiconductors microcontrollers. This + * copyright, permission, and disclaimer notice must appear in all copies of + * this code. + */ + +#ifndef __GPIO_001_H_ +#define __GPIO_001_H_ + +#include "sys_config.h" +#include "cmsis.h" + +#ifdef __cplusplus +extern "C" { +#endif + +/** @defgroup GPIO_ADC_001 IP: GPIO register block and driver + * @ingroup IP_Drivers + * @{ + */ + +#define GPIO_PORT_BITS 32 + +#if defined(CHIP_LPC11UXX) +#define GPIO_PORT_COUNT 2 +#endif + +#if defined(CHIP_LPC18XX) || defined(CHIP_LPC43XX) +#define GPIO_PORT_COUNT 6 +#endif + +/** + * @brief GPIO port register block structure + */ +typedef struct { /*!< GPIO_PORT Structure */ + __IO uint8_t B[GPIO_PORT_COUNT][32]; /*!< Byte pin registers port 0 to 5; pins PIOn_0 to PIOn_31 */ + __I uint8_t RESERVED0[4096 - (GPIO_PORT_COUNT * 32 * sizeof(uint8_t))]; + __IO uint32_t W[GPIO_PORT_COUNT][32]; /*!< Word pin registers port 0 to 5 */ + __I uint8_t RESERVED1[4096 - (GPIO_PORT_COUNT * 32 * sizeof(uint32_t))]; + __IO uint32_t DIR[GPIO_PORT_COUNT]; /*!< Direction registers port n */ + __I uint32_t RESERVED2[32 - GPIO_PORT_COUNT]; + __IO uint32_t MASK[GPIO_PORT_COUNT]; /*!< Mask register port n */ + __I uint32_t RESERVED3[32 - GPIO_PORT_COUNT]; + __IO uint32_t PIN[GPIO_PORT_COUNT]; /*!< Portpin register port n */ + __I uint32_t RESERVED4[32 - GPIO_PORT_COUNT]; + __IO uint32_t MPIN[GPIO_PORT_COUNT]; /*!< Masked port register port n */ + __I uint32_t RESERVED5[32 - GPIO_PORT_COUNT]; + __IO uint32_t SET[GPIO_PORT_COUNT]; /*!< Write: Set register for port n Read: output bits for port n */ + __I uint32_t RESERVED6[32 - GPIO_PORT_COUNT]; + __O uint32_t CLR[GPIO_PORT_COUNT]; /*!< Clear port n */ + __I uint32_t RESERVED7[32 - GPIO_PORT_COUNT]; + __O uint32_t NOT[GPIO_PORT_COUNT]; /*!< Toggle port n */ +} IP_GPIO_001_Type; + +/** + * @brief Initialize GPIO block + * @param pGPIO : The Base Address of the GPIO block + * @return Nothing + */ +STATIC INLINE void IP_GPIO_Init(IP_GPIO_001_Type *pGPIO) +{} + +/** + * @brief Set a GPIO port/bit state + * @param pGPIO : The Base Address of the GPIO block + * @param Port : GPIO port to set + * @param Bit : GPIO bit to set + * @param Setting : true for high, false for low + * @return Nothing + */ +STATIC INLINE void IP_GPIO_WritePortBit(IP_GPIO_001_Type *pGPIO, uint32_t Port, uint8_t Bit, bool Setting) +{ + pGPIO->B[Port][Bit] = Setting; +} + +/** + * @brief Seta GPIO direction + * @param pGPIO : The Base Address of the GPIO block + * @param Port : GPIO port to set + * @param Bit : GPIO bit to set + * @param Setting : true for output, false for input + * @return Nothing + */ +STATIC INLINE void IP_GPIO_WriteDirBit(IP_GPIO_001_Type *pGPIO, uint32_t Port, uint8_t Bit, bool Setting) +{ + if (Setting) { + pGPIO->DIR[Port] |= 1UL << Bit; + } + else { + pGPIO->DIR[Port] &= ~(1UL << Bit); + } +} + +/** + * @brief Read a GPIO state + * @param pGPIO : The Base Address of the GPIO block + * @param Port : GPIO port to read + * @param Bit : GPIO bit to read + * @return true of the GPIO is high, false if low + */ +STATIC INLINE bool IP_GPIO_ReadPortBit(IP_GPIO_001_Type *pGPIO, uint32_t Port, uint8_t Bit) +{ + return (bool) pGPIO->B[Port][Bit]; +} + +/** + * @brief Read a GPIO direction (out ot in) + * @param pGPIO : The Base Address of the GPIO block + * @param Port : GPIO port to read + * @param Bit : GPIO bit to read + * @return true of the GPIO is an output, false if input + */ +STATIC INLINE bool IP_GPIO_ReadDirBit(IP_GPIO_001_Type *pGPIO, uint32_t Port, uint8_t Bit) +{ + return (bool) (((pGPIO->DIR[Port]) >> Bit) & 1); +} + +/** + * @} + */ + +#ifdef __cplusplus +} +#endif + +#endif /* __GPIO_001_H_ */ diff --git a/bsp/xplorer4330/libraries/lpc_ip/gpiogrpint_001.c b/bsp/xplorer4330/libraries/lpc_ip/gpiogrpint_001.c new file mode 100644 index 0000000000..45c5080244 --- /dev/null +++ b/bsp/xplorer4330/libraries/lpc_ip/gpiogrpint_001.c @@ -0,0 +1,70 @@ +/* +* @brief GPIO Group Interrupt Registers and control functions +* +* @note +* Copyright(C) NXP Semiconductors, 2012 +* All rights reserved. +* +* @par +* Software that is described herein is for illustrative purposes only +* which provides customers with programming information regarding the +* LPC products. This software is supplied "AS IS" without any warranties of +* any kind, and NXP Semiconductors and its licensor disclaim any and +* all warranties, express or implied, including all implied warranties of +* merchantability, fitness for a particular purpose and non-infringement of +* intellectual property rights. NXP Semiconductors assumes no responsibility +* or liability for the use of the software, conveys no license or rights under any +* patent, copyright, mask work right, or any other intellectual property rights in +* or to any products. NXP Semiconductors reserves the right to make changes +* in the software without notification. NXP Semiconductors also makes no +* representation or warranty that such application will be suitable for the +* specified use without further testing or modification. +* +* @par +* Permission to use, copy, modify, and distribute this software and its +* documentation is hereby granted, under NXP Semiconductors' and its +* licensor's relevant copyrights in the software, without fee, provided that it +* is used in conjunction with NXP Semiconductors microcontrollers. This +* copyright, permission, and disclaimer notice must appear in all copies of +* this code. +*/ + +#include "gpiogrpint_001.h" + +/***************************************************************************** + * Private types/enumerations/variables + ****************************************************************************/ + +/***************************************************************************** + * Public types/enumerations/variables + ****************************************************************************/ + +/***************************************************************************** + * Private functions + ****************************************************************************/ + +/***************************************************************************** + * Public functions + ****************************************************************************/ + +/* GPIO Group Interrupt Pin Add to Group */ +void IP_GPIOGP_IntPinAdd(IP_GPIOGROUPINT_001_Type *pGPIOGPINT, uint8_t PortNum, uint8_t PinNum, bool ActiveMode) +{ + volatile uint32_t wordDat; + bool pinstate; + + /* configure to PORT_ENA register */ + pGPIOGPINT->PORT_ENA[PortNum] |= (1<PORT_POL[PortNum]; + pinstate = (bool) (((wordDat>>PinNum)&0x01) != 0); + if (pinstate != ActiveMode) { + if (ActiveMode == true) { /* active HIGH */ + wordDat |= (1<PORT_POL[PortNum] = wordDat; + } +} diff --git a/bsp/xplorer4330/libraries/lpc_ip/gpiogrpint_001.h b/bsp/xplorer4330/libraries/lpc_ip/gpiogrpint_001.h new file mode 100644 index 0000000000..b96059e693 --- /dev/null +++ b/bsp/xplorer4330/libraries/lpc_ip/gpiogrpint_001.h @@ -0,0 +1,120 @@ +/* + * @brief GPIO Group Interrupt Registers and control functions + * + * @note + * Copyright(C) NXP Semiconductors, 2012 + * All rights reserved. + * + * @par + * Software that is described herein is for illustrative purposes only + * which provides customers with programming information regarding the + * LPC products. This software is supplied "AS IS" without any warranties of + * any kind, and NXP Semiconductors and its licensor disclaim any and + * all warranties, express or implied, including all implied warranties of + * merchantability, fitness for a particular purpose and non-infringement of + * intellectual property rights. NXP Semiconductors assumes no responsibility + * or liability for the use of the software, conveys no license or rights under any + * patent, copyright, mask work right, or any other intellectual property rights in + * or to any products. NXP Semiconductors reserves the right to make changes + * in the software without notification. NXP Semiconductors also makes no + * representation or warranty that such application will be suitable for the + * specified use without further testing or modification. + * + * @par + * Permission to use, copy, modify, and distribute this software and its + * documentation is hereby granted, under NXP Semiconductors' and its + * licensor's relevant copyrights in the software, without fee, provided that it + * is used in conjunction with NXP Semiconductors microcontrollers. This + * copyright, permission, and disclaimer notice must appear in all copies of + * this code. + */ + +#ifndef __GPIOGRPINT_001_H_ +#define __GPIOGRPINT_001_H_ + +#include "sys_config.h" +#include "cmsis.h" + +#ifdef __cplusplus +extern "C" { +#endif + +/** @defgroup IP_GPIOGRPINT_001 IP: GPIO Grouped Interrupts register block and driver + * @ingroup IP_Drivers + * @{ + */ + +/** + * @brief GPIO grouped interrupt register block structure + */ +typedef struct { /*!< GPIO_GROUP_INTn Structure */ + __IO uint32_t CTRL; /*!< GPIO grouped interrupt control register */ + __I uint32_t RESERVED0[7]; + __IO uint32_t PORT_POL[8]; /*!< GPIO grouped interrupt port polarity register */ + __IO uint32_t PORT_ENA[8]; /*!< GPIO grouped interrupt port m enable register */ +} IP_GPIOGROUPINT_001_Type; + +/** + * @brief GPIO Group Interrupt Pin Initialization + * @param pGPIOGPINT : Pointer to GPIOIR register block + * @param PortComb : GPIO group combined enable, should be: 0 (OR functionality) and 1 (AND functionality) + * @param PortTrigger : GPIO group interrupt trigger, should be: 0 (Edge-triggered) 1 (Level triggered) + * @return None + */ +STATIC INLINE void IP_GPIOGP_IntInit(IP_GPIOGROUPINT_001_Type *pGPIOGPINT, uint8_t PortComb, uint8_t PortTrigger) +{ + pGPIOGPINT->CTRL = ((PortTrigger & 0x1) << 2) | ((PortComb & 0x1) << 1); +} + +/** + * @brief GPIO Group Interrupt Pin Add to Group + * @param pGPIOGPINT : Pointer to GPIOIR register block + * @param PortNum : GPIO port number, should be 0 to 7 + * @param PinNum : GPIO pin number, should be 0 to 31 + * @param ActiveMode : GPIO active mode, should be 0 (active LOW) and 1 (active HIGH) + * @return None + */ +void IP_GPIOGP_IntPinAdd(IP_GPIOGROUPINT_001_Type *pGPIOGPINT, uint8_t PortNum, uint8_t PinNum, bool ActiveMode); + +/** + * @brief GPIO Group Interrupt Pin Remove from Group + * @param pGPIOGPINT : Pointer to GPIOIR register block + * @param PortNum : GPIO port number, should be 0 to 7 + * @param PinNum : GPIO pin number, should be 0 to 31 + * @return None + */ +STATIC INLINE void IP_GPIOGP_IntPinRemove(IP_GPIOGROUPINT_001_Type *pGPIOGPINT, uint8_t PortNum, uint8_t PinNum) +{ + /* configure to PORT_ENA register */ + pGPIOGPINT->PORT_ENA[PortNum] &= ~(1 << PinNum); +} + +/** + * @brief Get GPIO Group Interrupt Get Status + * @param pGPIOGPINT : Pointer to GPIOIR register block + * @return true if interrupt is pending, otherwise false + */ +STATIC INLINE bool IP_GPIOGP_IntGetStatus(IP_GPIOGROUPINT_001_Type *pGPIOGPINT) +{ + return (bool) (pGPIOGPINT->CTRL & 0x01); +} + +/** + * @brief Clear GPIO Group Interrupt + * @param pGPIOGPINT : Pointer to GPIOIR register block + * @return None + */ +STATIC INLINE void IP_GPIOGP_IntClear(IP_GPIOGROUPINT_001_Type *pGPIOGPINT) +{ + pGPIOGPINT->CTRL |= 0x01; +} + +/** + * @} + */ + +#ifdef __cplusplus +} +#endif + +#endif /* __GPIOGRPINT_001_H_ */ diff --git a/bsp/xplorer4330/libraries/lpc_ip/gpioint_001.c b/bsp/xplorer4330/libraries/lpc_ip/gpioint_001.c new file mode 100644 index 0000000000..21bd76ef68 --- /dev/null +++ b/bsp/xplorer4330/libraries/lpc_ip/gpioint_001.c @@ -0,0 +1,111 @@ +/* + * @brief GPIO Interrupt Registers and control functions + * + * @note + * Copyright(C) NXP Semiconductors, 2012 + * All rights reserved. + * + * @par + * Software that is described herein is for illustrative purposes only + * which provides customers with programming information regarding the + * LPC products. This software is supplied "AS IS" without any warranties of + * any kind, and NXP Semiconductors and its licensor disclaim any and + * all warranties, express or implied, including all implied warranties of + * merchantability, fitness for a particular purpose and non-infringement of + * intellectual property rights. NXP Semiconductors assumes no responsibility + * or liability for the use of the software, conveys no license or rights under any + * patent, copyright, mask work right, or any other intellectual property rights in + * or to any products. NXP Semiconductors reserves the right to make changes + * in the software without notification. NXP Semiconductors also makes no + * representation or warranty that such application will be suitable for the + * specified use without further testing or modification. + * + * @par + * Permission to use, copy, modify, and distribute this software and its + * documentation is hereby granted, under NXP Semiconductors' and its + * licensor's relevant copyrights in the software, without fee, provided that it + * is used in conjunction with NXP Semiconductors microcontrollers. This + * copyright, permission, and disclaimer notice must appear in all copies of + * this code. + */ + +#include "gpioint_001.h" + +/***************************************************************************** + * Private types/enumerations/variables + ****************************************************************************/ + +/***************************************************************************** + * Public types/enumerations/variables + ****************************************************************************/ + +/***************************************************************************** + * Private functions + ****************************************************************************/ + +/***************************************************************************** + * Public functions + ****************************************************************************/ + +/* Enable GPIO Interrupt */ +void IP_GPIOINT_IntCmd(IP_GPIOINT_001_Type *pGPIOPININT, uint8_t PortNum, uint32_t BitValue, Gpio_Int_Mode_Enum IntMode) +{ + if (PortNum == 0) { + if (IntMode == IP_GPIOINT_RISING_EDGE) { + pGPIOPININT->EnR0 = BitValue; + } + else { + pGPIOPININT->EnF0 = BitValue; + } + } + else if (PortNum == 2) { + if (IntMode == IP_GPIOINT_RISING_EDGE) { + pGPIOPININT->EnR2 = BitValue; + } + else { + pGPIOPININT->EnF2 = BitValue; + } + } +} + +/*Get GPIO Interrupt Status */ +bool IP_GPIOINT_IntGetStatus(IP_GPIOINT_001_Type *pGPIOPININT, + uint8_t PortNum, + uint32_t PinNum, + Gpio_Int_Mode_Enum IntMode) +{ + if (PortNum == 0) { + if (IntMode == IP_GPIOINT_RISING_EDGE) { + return (bool) ((pGPIOPININT->StatR0 >> PinNum) & 0x1); + } + else { + return (bool) ((pGPIOPININT->StatF0 >> PinNum) & 0x1); + } + } + else if (PortNum == 2) { + if (IntMode == IP_GPIOINT_RISING_EDGE) { + return (bool) ((pGPIOPININT->StatR2 >> PinNum) & 0x1); + } + else { + return (bool) ((pGPIOPININT->StatF2 >> PinNum) & 0x1); + } + } + + return false; +} + +/** + * @brief Clear GPIO Interrupt (Edge interrupt cases only) + * @param PortNum : GPIO port number interrupt, should be: 0 (port 0) or 2 (port 2) + * @param BitValue : GPIO Bit value that contains all bits on GPIO to enable, should be 0 to 0xFFFFFFFF + * @return None + */ +void IP_GPIOINT_IntClear(IP_GPIOINT_001_Type *pGPIOPININT, uint8_t PortNum, uint32_t BitValue) +{ + if (PortNum == 0) { + pGPIOPININT->Clr0 = BitValue; + } + else if (PortNum == 2) { + pGPIOPININT->Clr2 = BitValue; + } +} diff --git a/bsp/xplorer4330/libraries/lpc_ip/gpioint_001.h b/bsp/xplorer4330/libraries/lpc_ip/gpioint_001.h new file mode 100644 index 0000000000..fd4ed022ca --- /dev/null +++ b/bsp/xplorer4330/libraries/lpc_ip/gpioint_001.h @@ -0,0 +1,110 @@ +/* + * @brief GPIO Interrupt Registers and control functions + * + * @note + * Copyright(C) NXP Semiconductors, 2012 + * All rights reserved. + * + * @par + * Software that is described herein is for illustrative purposes only + * which provides customers with programming information regarding the + * LPC products. This software is supplied "AS IS" without any warranties of + * any kind, and NXP Semiconductors and its licensor disclaim any and + * all warranties, express or implied, including all implied warranties of + * merchantability, fitness for a particular purpose and non-infringement of + * intellectual property rights. NXP Semiconductors assumes no responsibility + * or liability for the use of the software, conveys no license or rights under any + * patent, copyright, mask work right, or any other intellectual property rights in + * or to any products. NXP Semiconductors reserves the right to make changes + * in the software without notification. NXP Semiconductors also makes no + * representation or warranty that such application will be suitable for the + * specified use without further testing or modification. + * + * @par + * Permission to use, copy, modify, and distribute this software and its + * documentation is hereby granted, under NXP Semiconductors' and its + * licensor's relevant copyrights in the software, without fee, provided that it + * is used in conjunction with NXP Semiconductors microcontrollers. This + * copyright, permission, and disclaimer notice must appear in all copies of + * this code. + */ + +#ifndef __GPIOINT_001_H_ +#define __GPIOINT_001_H_ + +#include "sys_config.h" +#include "cmsis.h" + +#ifdef __cplusplus +extern "C" { +#endif + +/** @defgroup IP_GPIOINT_001 IP: GPIO Interrupt register block and driver + * @ingroup IP_Drivers + * @{ + */ + +/** + * @brief GPIO Interrupt register block structure + */ +typedef struct { + __I uint32_t Status; /*!< GPIO overall Interrupt Status Register */ + __I uint32_t StatR0; /*!< GPIO Interrupt Status Register 0 for Rising edge */ + __I uint32_t StatF0; /*!< GPIO Interrupt Status Register 0 for Falling edge */ + __O uint32_t Clr0; /*!< GPIO Interrupt Clear Register 0 */ + __IO uint32_t EnR0; /*!< GPIO Interrupt Enable Register 0 for Rising edge */ + __IO uint32_t EnF0; /*!< GPIO Interrupt Enable Register 0 for Falling edge */ + uint32_t RESERVED0[3]; + __I uint32_t StatR2; /*!< GPIO Interrupt Status Register 2 for Rising edge */ + __I uint32_t StatF2; /*!< GPIO Interrupt Status Register 2 for Falling edge */ + __O uint32_t Clr2; /*!< GPIO Interrupt Clear Register 2 */ + __IO uint32_t EnR2; /*!< GPIO Interrupt Enable Register 2 for Rising edge */ + __IO uint32_t EnF2; /*!< GPIO Interrupt Enable Register 2 for Falling edge */ +} IP_GPIOINT_001_Type; + +typedef enum { + IP_GPIOINT_RISING_EDGE = 0x01, + IP_GPIOINT_FALLING_EDGE = 0x02 +} Gpio_Int_Mode_Enum; + +/** + * @brief Enable GPIO Interrupt + * @param pGPIOPININT : Pointer to GPIO interrupt register block + * @param PortNum : GPIO port number interrupt, should be: 0 (port 0) or 2 (port 2) + * @param BitValue : GPIO Bit value that contains all bits on GPIO to enable, should be 0 to 0xFFFFFFFF + * @param IntMode : Interrupt mode, 0 = rising edge, 1 = falling edge + * @return None + */ +void IP_GPIOINT_IntCmd(IP_GPIOINT_001_Type *pGPIOPININT, uint8_t PortNum, uint32_t BitValue, Gpio_Int_Mode_Enum IntMode); + +/** + * @brief Get GPIO Interrupt Status + * @param pGPIOPININT : Pointer to GPIO interrupt register block + * @param PortNum : GPIO port number interrupt, should be: 0 (port 0) or 2 (port 2) + * @param PinNum : Pin number, should be: 0..30(with port 0) and 0..13 (with port 2) + * @param IntMode : Interrupt mode, 0 = rising edge, 1 = falling edge + * @return true if interrupt is pending, otherwise false + */ +bool IP_GPIOINT_IntGetStatus(IP_GPIOINT_001_Type *pGPIOPININT, + uint8_t PortNum, + uint32_t PinNum, + Gpio_Int_Mode_Enum IntMode); + +/** + * @brief Clear GPIO Interrupt (Edge interrupt cases only) + * @param pGPIOPININT : Pointer to GPIO interrupt register block + * @param PortNum : GPIO port number interrupt, should be: 0 (port 0) or 2 (port 2) + * @param BitValue : GPIO Bit value that contains all bits on GPIO to enable, should be 0 to 0xFFFFFFFF + * @return None + */ +void IP_GPIOINT_IntClear(IP_GPIOINT_001_Type *pGPIOPININT, uint8_t PortNum, uint32_t BitValue); + +/** + * @} + */ + +#ifdef __cplusplus +} +#endif + +#endif /* __GPIOINT_001_H_ */ diff --git a/bsp/xplorer4330/libraries/lpc_ip/gpiopinint_001.c b/bsp/xplorer4330/libraries/lpc_ip/gpiopinint_001.c new file mode 100644 index 0000000000..6d73c3822c --- /dev/null +++ b/bsp/xplorer4330/libraries/lpc_ip/gpiopinint_001.c @@ -0,0 +1,71 @@ +/* + * @brief GPIO Pin Interrupt Registers and control functions + * + * @note + * Copyright(C) NXP Semiconductors, 2012 + * All rights reserved. + * + * @par + * Software that is described herein is for illustrative purposes only + * which provides customers with programming information regarding the + * LPC products. This software is supplied "AS IS" without any warranties of + * any kind, and NXP Semiconductors and its licensor disclaim any and + * all warranties, express or implied, including all implied warranties of + * merchantability, fitness for a particular purpose and non-infringement of + * intellectual property rights. NXP Semiconductors assumes no responsibility + * or liability for the use of the software, conveys no license or rights under any + * patent, copyright, mask work right, or any other intellectual property rights in + * or to any products. NXP Semiconductors reserves the right to make changes + * in the software without notification. NXP Semiconductors also makes no + * representation or warranty that such application will be suitable for the + * specified use without further testing or modification. + * + * @par + * Permission to use, copy, modify, and distribute this software and its + * documentation is hereby granted, under NXP Semiconductors' and its + * licensor's relevant copyrights in the software, without fee, provided that it + * is used in conjunction with NXP Semiconductors microcontrollers. This + * copyright, permission, and disclaimer notice must appear in all copies of + * this code. + */ + +#include "gpiopinint_001.h" + +/***************************************************************************** + * Private types/enumerations/variables + ****************************************************************************/ + +/***************************************************************************** + * Public types/enumerations/variables + ****************************************************************************/ + +/***************************************************************************** + * Private functions + ****************************************************************************/ + +/***************************************************************************** + * Public functions + ****************************************************************************/ + +/* Enable GPIO Interrupt */ +void IP_GPIOPININT_IntCmd(IP_GPIOPININT_001_Type *pGPIOPININT, uint8_t PortNum, Gpio_PinInt_Mode_Enum IntMode) +{ + if (IntMode == IP_GPIOPININT_RISING_EDGE) { + pGPIOPININT->ISEL &= ~(1 << PortNum); + pGPIOPININT->IENR |= (1 << PortNum); + } + else if (IntMode == IP_GPIOPININT_FALLING_EDGE) { + pGPIOPININT->ISEL &= ~(1 << PortNum); + pGPIOPININT->IENF |= (1 << PortNum); + } + else if (IntMode == IP_GPIOPININT_ACTIVE_HIGH_LEVEL) { + pGPIOPININT->ISEL |= (1 << PortNum); + pGPIOPININT->IENR |= (1 << PortNum); + pGPIOPININT->SIENF |= (1 << PortNum); + } + else { + pGPIOPININT->ISEL |= (1 << PortNum); + pGPIOPININT->IENR |= (1 << PortNum); + pGPIOPININT->CIENF |= (1 << PortNum); + } +} diff --git a/bsp/xplorer4330/libraries/lpc_ip/gpiopinint_001.h b/bsp/xplorer4330/libraries/lpc_ip/gpiopinint_001.h new file mode 100644 index 0000000000..8a6e165cb7 --- /dev/null +++ b/bsp/xplorer4330/libraries/lpc_ip/gpiopinint_001.h @@ -0,0 +1,115 @@ +/* + * @brief GPIO Pin Interrupt Registers and control functions + * + * @note + * Copyright(C) NXP Semiconductors, 2012 + * All rights reserved. + * + * @par + * Software that is described herein is for illustrative purposes only + * which provides customers with programming information regarding the + * LPC products. This software is supplied "AS IS" without any warranties of + * any kind, and NXP Semiconductors and its licensor disclaim any and + * all warranties, express or implied, including all implied warranties of + * merchantability, fitness for a particular purpose and non-infringement of + * intellectual property rights. NXP Semiconductors assumes no responsibility + * or liability for the use of the software, conveys no license or rights under any + * patent, copyright, mask work right, or any other intellectual property rights in + * or to any products. NXP Semiconductors reserves the right to make changes + * in the software without notification. NXP Semiconductors also makes no + * representation or warranty that such application will be suitable for the + * specified use without further testing or modification. + * + * @par + * Permission to use, copy, modify, and distribute this software and its + * documentation is hereby granted, under NXP Semiconductors' and its + * licensor's relevant copyrights in the software, without fee, provided that it + * is used in conjunction with NXP Semiconductors microcontrollers. This + * copyright, permission, and disclaimer notice must appear in all copies of + * this code. + */ + +#ifndef __GPIOPININT_001_H_ +#define __GPIOPININT_001_H_ + +#include "sys_config.h" +#include "cmsis.h" + +#ifdef __cplusplus +extern "C" { +#endif + +/** @defgroup IP_GPIOPININT_001 IP: GPIO Pin Interrupt register block and driver + * @ingroup IP_Drivers + * @{ + */ + +/** + * @brief GPIO pin interrupt register block structure + */ +typedef struct { /*!< GPIO_PIN_INT Structure */ + __IO uint32_t ISEL; /*!< Pin Interrupt Mode register */ + __IO uint32_t IENR; /*!< Pin Interrupt Enable (Rising) register */ + __O uint32_t SIENR; /*!< Set Pin Interrupt Enable (Rising) register */ + __O uint32_t CIENR; /*!< Clear Pin Interrupt Enable (Rising) register */ + __IO uint32_t IENF; /*!< Pin Interrupt Enable Falling Edge / Active Level register */ + __O uint32_t SIENF; /*!< Set Pin Interrupt Enable Falling Edge / Active Level register */ + __O uint32_t CIENF; /*!< Clear Pin Interrupt Enable Falling Edge / Active Level address */ + __IO uint32_t RISE; /*!< Pin Interrupt Rising Edge register */ + __IO uint32_t FALL; /*!< Pin Interrupt Falling Edge register */ + __IO uint32_t IST; /*!< Pin Interrupt Status register */ +} IP_GPIOPININT_001_Type; + +typedef enum { + IP_GPIOPININT_RISING_EDGE = 0x01, + IP_GPIOPININT_FALLING_EDGE = 0x02, + IP_GPIOPININT_ACTIVE_HIGH_LEVEL = 0x04, + IP_GPIOPININT_ACTIVE_LOW_LEVEL = 0x08 +} Gpio_PinInt_Mode_Enum; + +/** + * @brief Enable GPIO Interrupt + * @param pGPIOPININT : Pointer to GPIO interrupt register block + * @param PortNum : GPIO port number interrupt + * @param IntMode : Interrupt mode, should be: + * 0: Rising edge interrupt mode + * 1: Falling edge interrupt mode + * 2: Active-High interrupt mode + * 3: Active-Low interrupt mode + * @return None + */ +void IP_GPIOPININT_IntCmd(IP_GPIOPININT_001_Type *pGPIOPININT, uint8_t PortNum, Gpio_PinInt_Mode_Enum IntMode); + +/** + * @brief Get GPIO Interrupt Status + * @param pGPIOPININT : Pointer to GPIO interrupt register block + * @param PortNum : GPIO port number interrupt + * @return true if interrupt is pending, otherwise false + */ +STATIC INLINE bool IP_GPIOPININT_IntGetStatus(IP_GPIOPININT_001_Type *pGPIOPININT, uint8_t PortNum) +{ + return (bool) (((pGPIOPININT->IST) >> PortNum) & 0x01); +} + +/** + * @brief Clear GPIO Interrupt (Edge interrupt cases only) + * @param pGPIOPININT : Pointer to GPIO interrupt register block + * @param PortNum : GPIO port number interrupt + * @return None + */ +STATIC INLINE void IP_GPIOPININT_IntClear(IP_GPIOPININT_001_Type *pGPIOPININT, uint8_t PortNum) +{ + if (!(pGPIOPININT->ISEL & (1 << PortNum))) { + pGPIOPININT->IST |= (1 << PortNum); + } +} + +/** + * @} + */ + +#ifdef __cplusplus +} +#endif + +#endif /* __GPIOPININT_001_H_ */ diff --git a/bsp/xplorer4330/libraries/lpc_ip/i2c_001.c b/bsp/xplorer4330/libraries/lpc_ip/i2c_001.c new file mode 100644 index 0000000000..b3619b1768 --- /dev/null +++ b/bsp/xplorer4330/libraries/lpc_ip/i2c_001.c @@ -0,0 +1,786 @@ +/* + * @brief I2C driver functions + * + * @note + * Copyright(C) NXP Semiconductors, 2012 + * All rights reserved. + * + * @par + * Software that is described herein is for illustrative purposes only + * which provides customers with programming information regarding the + * LPC products. This software is supplied "AS IS" without any warranties of + * any kind, and NXP Semiconductors and its licensor disclaim any and + * all warranties, express or implied, including all implied warranties of + * merchantability, fitness for a particular purpose and non-infringement of + * intellectual property rights. NXP Semiconductors assumes no responsibility + * or liability for the use of the software, conveys no license or rights under any + * patent, copyright, mask work right, or any other intellectual property rights in + * or to any products. NXP Semiconductors reserves the right to make changes + * in the software without notification. NXP Semiconductors also makes no + * representation or warranty that such application will be suitable for the + * specified use without further testing or modification. + * + * @par + * Permission to use, copy, modify, and distribute this software and its + * documentation is hereby granted, under NXP Semiconductors' and its + * licensor's relevant copyrights in the software, without fee, provided that it + * is used in conjunction with NXP Semiconductors microcontrollers. This + * copyright, permission, and disclaimer notice must appear in all copies of + * this code. + */ + +#include "i2c_001.h" + +/***************************************************************************** + * Private types/enumerations/variables + ****************************************************************************/ + +/* I2C device configuration structure type */ +typedef struct { + union { + I2C_M_SETUP_Type txrx_setup_master; /* Transmission setup */ + I2C_S_SETUP_Type txrx_setup_slave; /* Transmission setup */ + }; + + int32_t dir; /* Current direction phase, 0 - write, 1 - read */ +} I2C_CFG_T; + +#define BLOCKING_TIMEOUT (0x000FFFFFUL) +#define RESTRANSMISSION_MAX (0x000000FFUL) + +/* I2C driver data for I2C0, I2C1 */ +static I2C_CFG_T i2cdat[3]; + +static bool I2C_MasterComplete[3]; +static bool I2C_SlaveComplete[3]; + +/***************************************************************************** + * Public types/enumerations/variables + ****************************************************************************/ + +/***************************************************************************** + * Private functions + ****************************************************************************/ + +/* Generate a start condition on I2C bus (in master mode only) */ +static uint32_t IP_I2C_Start(IP_I2C_001_Type *LPC_I2C, I2C_TRANSFER_OPT_Type Opt) +{ + uint32_t cnt = 0; + /* Reset STA, STO, SI */ + LPC_I2C->CONCLR = I2C_I2CONCLR_SIC | I2C_I2CONCLR_STOC | I2C_I2CONCLR_STAC; + + /* Enter to Master Transmitter mode */ + LPC_I2C->CONSET = I2C_I2CONSET_STA; + + if (Opt == I2C_TRANSFER_POLLING) { + /* Wait for complete */ + while (!(LPC_I2C->CONSET & I2C_I2CONSET_SI)) { + if (++cnt > BLOCKING_TIMEOUT) { + return I2C_STAT_CODE_ERROR; + } + } + } + + return LPC_I2C->STAT & I2C_STAT_CODE_BITMASK; +} + +/* Generate a stop condition on I2C bus (in master mode only) */ +static Status IP_I2C_Stop(IP_I2C_001_Type *LPC_I2C, I2C_TRANSFER_OPT_Type Opt) +{ + uint32_t cnt = 0; + /* Make sure start bit is not active */ + if (LPC_I2C->CONSET & I2C_I2CONSET_STA) { + LPC_I2C->CONCLR = I2C_I2CONCLR_STAC; + } + + LPC_I2C->CONSET = I2C_I2CONSET_STO; + + LPC_I2C->CONCLR = I2C_I2CONCLR_SIC; + + if (Opt == I2C_TRANSFER_POLLING) { + /* wait for stop is sent */ + while (LPC_I2C->CONSET & I2C_I2CONSET_STO) { + if (LPC_I2C->CONSET & I2C_I2CONSET_SI) { + LPC_I2C->CONCLR = I2C_I2CONCLR_SIC; + } + if (++cnt > BLOCKING_TIMEOUT) { + return ERROR; + } + } + } + + return SUCCESS; +} + +/* I2C send byte subroutine */ +static uint32_t IP_I2C_SendByte(IP_I2C_001_Type *LPC_I2C, uint8_t databyte) +{ + uint32_t CodeStatus = LPC_I2C->STAT & I2C_STAT_CODE_BITMASK; + + if ((CodeStatus != I2C_I2STAT_M_TX_START) && + (CodeStatus != I2C_I2STAT_M_TX_RESTART) && + (CodeStatus != I2C_I2STAT_M_TX_SLAW_ACK) && + (CodeStatus != I2C_I2STAT_M_TX_DAT_ACK) ) { + return CodeStatus; + } + + LPC_I2C->DAT = databyte & I2C_I2DAT_BITMASK; + + LPC_I2C->CONSET = I2C_I2CONSET_AA; + + LPC_I2C->CONCLR = I2C_I2CONCLR_SIC; + + return LPC_I2C->STAT & I2C_STAT_CODE_BITMASK; +} + +/* I2C get byte subroutine */ +static uint32_t IP_I2C_GetByte(IP_I2C_001_Type *LPC_I2C, uint8_t *retdat, bool ack) +{ + *retdat = (uint8_t) (LPC_I2C->DAT & I2C_I2DAT_BITMASK); + + if (ack == true) { + LPC_I2C->CONSET = I2C_I2CONSET_AA; + } + else { + LPC_I2C->CONCLR = I2C_I2CONCLR_AAC; + } + + LPC_I2C->CONCLR = I2C_I2CONCLR_SIC; + + return LPC_I2C->STAT & I2C_STAT_CODE_BITMASK; +} + +/* Handle I2C Master states */ +static int32_t IP_I2C_MasterHanleStates(IP_I2C_001_Type *LPC_I2C, + uint32_t CodeStatus, + I2C_M_SETUP_Type *TransferCfg, + I2C_TRANSFER_OPT_Type Opt) +{ + uint8_t *txdat; + uint8_t *rxdat; + uint8_t tmp; + int32_t Ret = I2C_OK; + + /* get buffer to send/receive */ + txdat = (uint8_t *) &TransferCfg->tx_data[TransferCfg->tx_count]; + rxdat = (uint8_t *) &TransferCfg->rx_data[TransferCfg->rx_count]; + + switch (CodeStatus) { + case I2C_I2STAT_M_TX_START: + case I2C_I2STAT_M_TX_RESTART: + // case I2C_I2STAT_M_RX_START: + // case I2C_I2STAT_M_RX_RESTART + /* Send data first */ + if (TransferCfg->tx_count < TransferCfg->tx_length) { + /* Send slave address + WR direction bit = 0 ----------------------------------- */ + IP_I2C_SendByte(LPC_I2C, (TransferCfg->sl_addr7bit << 1)); + Ret = I2C_BYTE_SENT; + } + else if (TransferCfg->rx_count < TransferCfg->rx_length) { + /* Send slave address + RD direction bit = 1 ----------------------------------- */ + IP_I2C_SendByte(LPC_I2C, ((TransferCfg->sl_addr7bit << 1) | 0x01)); + Ret = I2C_BYTE_SENT; + } + /* Clear STA bit after the slave address is sent */ + LPC_I2C->CONCLR = I2C_I2CONCLR_STAC; + break; + + case I2C_I2STAT_M_TX_SLAW_ACK: + case I2C_I2STAT_M_TX_DAT_ACK: + + if (TransferCfg->tx_count < TransferCfg->tx_length) { + IP_I2C_SendByte(LPC_I2C, *txdat); + txdat++; + TransferCfg->tx_count++; + Ret = I2C_BYTE_SENT; + } + else { + if (TransferCfg->rx_count >= TransferCfg->rx_length) { + IP_I2C_Stop(LPC_I2C, Opt); + } + Ret = I2C_SEND_END; + + } + break; + + case I2C_I2STAT_M_TX_DAT_NACK: + if (TransferCfg->rx_count >= TransferCfg->rx_length) { + IP_I2C_Stop(LPC_I2C, Opt); + } + Ret = I2C_SEND_END; + break; + + case I2C_I2STAT_M_RX_ARB_LOST: + case I2C_I2STAT_S_RX_ARB_LOST_M_GENCALL: + case I2C_I2STAT_S_TX_ARB_LOST_M_SLA: + // case I2C_I2STAT_M_TX_ARB_LOST: + IP_I2C_Stop(LPC_I2C, Opt); + Ret = I2C_ERR; + break; + + case I2C_I2STAT_M_RX_SLAR_ACK: + if (TransferCfg->rx_length > 1) { + LPC_I2C->CONSET = I2C_I2CONSET_AA; + } + else { + LPC_I2C->CONCLR = I2C_I2CONCLR_AAC; + } + LPC_I2C->CONCLR = I2C_I2CONCLR_SIC; + + Ret = I2C_BYTE_RECV; + break; + + case I2C_I2STAT_M_RX_DAT_ACK: + if (TransferCfg->rx_count < TransferCfg->rx_length) { + if ((TransferCfg->rx_length > 1) && (TransferCfg->rx_count < (TransferCfg->rx_length - 2))) { + IP_I2C_GetByte(LPC_I2C, &tmp, true); + Ret = I2C_BYTE_RECV; + + } + else { /* the next byte is the last byte, send NACK instead */ + IP_I2C_GetByte(LPC_I2C, &tmp, false); + Ret = I2C_BYTE_RECV; + } + *rxdat++ = tmp; + + TransferCfg->rx_count++; + } + else { + IP_I2C_Stop(LPC_I2C, Opt); + Ret = I2C_RECV_END; + } + break; + + case I2C_I2STAT_M_RX_DAT_NACK: + IP_I2C_GetByte(LPC_I2C, &tmp, false); + if (TransferCfg->rx_count < TransferCfg->rx_length) { + *rxdat++ = tmp; + TransferCfg->rx_count++; + } + IP_I2C_Stop(LPC_I2C, Opt); + Ret = I2C_RECV_END; + break; + + case I2C_I2STAT_M_RX_SLAR_NACK: + case I2C_I2STAT_M_TX_SLAW_NACK: + case I2C_I2STAT_BUS_ERROR: + /* Send STOP condition */ + IP_I2C_Stop(LPC_I2C, Opt); + Ret = I2C_ERR; + break; + + /* No status information */ + case I2C_I2STAT_NO_INF: + if ((TransferCfg->tx_count < TransferCfg->tx_length) || + (TransferCfg->rx_count < TransferCfg->rx_length)) { + IP_I2C_Stop(LPC_I2C, Opt); + Ret = I2C_ERR; + } + else { + Ret = I2C_RECV_END; + } + break; + + default: + LPC_I2C->CONCLR = I2C_I2CONCLR_SIC; + break; + } + + return Ret; +} + +/* Handle I2C Master states */ +static int32_t IP_I2C_SlaveHanleStates(IP_I2C_001_Type *LPC_I2C, uint32_t CodeStatus, I2C_S_SETUP_Type *TransferCfg) +{ + int32_t Ret = I2C_OK; + uint8_t *txdat; + uint8_t *rxdat; + + /* get buffer to send/receive */ + txdat = (uint8_t *) &TransferCfg->tx_data[TransferCfg->tx_count]; + rxdat = (uint8_t *) &TransferCfg->rx_data[TransferCfg->rx_count]; + + switch (CodeStatus) { + /* Reading phase -------------------------------------------------------- */ + /* Own SLA+R has been received, ACK has been returned */ + case I2C_I2STAT_S_RX_SLAW_ACK: + + /* General call address has been received, ACK has been returned */ + case I2C_I2STAT_S_RX_GENCALL_ACK: + LPC_I2C->CONSET = I2C_I2CONSET_AA; + LPC_I2C->CONCLR = I2C_I2CONCLR_SIC; + break; + + /* Arbitration has been lost in Slave Address + R/W bit as bus Master. General Call has + been received and ACK has been returned.*/ + case I2C_I2STAT_S_RX_ARB_LOST_M_GENCALL: + LPC_I2C->CONSET = I2C_I2CONSET_AA | I2C_I2CONSET_STA; + LPC_I2C->CONCLR = I2C_I2CONCLR_SIC; + break; + + /* Previously addressed with own SLA; + * DATA byte has been received; + * ACK has been returned */ + case I2C_I2STAT_S_RX_ARB_LOST_M_SLA: + case I2C_I2STAT_S_RX_PRE_SLA_DAT_ACK: + /* + * All data bytes that over-flow the specified receive + * data length, just ignore them. + */ + if ((TransferCfg->rx_count < TransferCfg->rx_length) && (TransferCfg->rx_data != NULL)) { + *rxdat++ = (uint8_t) LPC_I2C->DAT; + + TransferCfg->rx_count++; + + Ret = I2C_BYTE_RECV; + } + if (TransferCfg->rx_count == (TransferCfg->rx_length) ) { + LPC_I2C->CONCLR = I2C_I2CONCLR_AAC | I2C_I2CONCLR_SIC; + Ret = I2C_BYTE_RECV; + } + else { + LPC_I2C->CONSET = I2C_I2CONSET_AA; + LPC_I2C->CONCLR = I2C_I2CONCLR_SIC; + } + + break; + + /* DATA has been received, Only the first data byte will be received with ACK. + * Additional data will be received with NOT ACK. */ + case I2C_I2STAT_S_RX_PRE_GENCALL_DAT_ACK: + if ((TransferCfg->rx_count < TransferCfg->rx_length) && (TransferCfg->rx_data != NULL)) { + *rxdat++ = (uint8_t) LPC_I2C->DAT; + + TransferCfg->rx_count++; + + Ret = I2C_BYTE_RECV; + } + LPC_I2C->CONCLR = I2C_I2CONCLR_AAC | I2C_I2CONCLR_SIC; + break; + + /* Writing phase -------------------------------------------------------- */ + /* Own SLA+R has been received, ACK has been returned */ + case I2C_I2STAT_S_TX_SLAR_ACK: + + /* Data has been transmitted, ACK has been received */ + case I2C_I2STAT_S_TX_DAT_ACK: + /* + * All data bytes that over-flow the specified receive + * data length, just ignore them. + */ + if ((TransferCfg->tx_count < TransferCfg->tx_length) && (TransferCfg->tx_data != NULL)) { + LPC_I2C->DAT = *txdat++; + + TransferCfg->tx_count++; + + Ret = I2C_BYTE_SENT; + } + + LPC_I2C->CONSET = I2C_I2CONSET_AA; + LPC_I2C->CONCLR = I2C_I2CONCLR_SIC; + break; + + /* Arbitration lost in Slave Address and R/W bit as bus Master. + * Own Slave Address + Read has been received, ACK has been returned. */ + case I2C_I2STAT_S_TX_ARB_LOST_M_SLA: + if ((TransferCfg->tx_count < TransferCfg->tx_length) && (TransferCfg->tx_data != NULL)) { + LPC_I2C->DAT = *txdat++; + + TransferCfg->tx_count++; + + Ret = I2C_BYTE_SENT; + } + LPC_I2C->CONSET = I2C_I2CONSET_AA | I2C_I2CONSET_STA; + LPC_I2C->CONCLR = I2C_I2CONCLR_SIC; + break; + + case I2C_I2STAT_S_TX_LAST_DAT_ACK: + /* Data has been transmitted, NACK has been received, + * that means there's no more data to send, exit now */ + /* + * Note: Don't wait for stop event since in slave transmit mode, + * since there no proof lets us know when a stop signal has been received + * on slave side. + */ + case I2C_I2STAT_S_TX_DAT_NACK: + LPC_I2C->CONSET = I2C_I2CONSET_AA; + LPC_I2C->CONCLR = I2C_I2CONCLR_SIC; + Ret = I2C_SEND_END; + break; + + /* Previously addressed with own SLA; + * DATA byte has been received; + * NOT ACK has been returned */ + case I2C_I2STAT_S_RX_PRE_SLA_DAT_NACK: + + /* DATA has been received, NOT ACK has been returned */ + case I2C_I2STAT_S_RX_PRE_GENCALL_DAT_NACK: + LPC_I2C->CONSET = I2C_I2CONSET_AA; + LPC_I2C->CONCLR = I2C_I2CONCLR_SIC; + Ret = I2C_RECV_END; + break; + + /* + * Note that: Return code only let us know a stop condition mixed + * with a repeat start condition in the same code value. + * So we should provide a time-out. In case this is really a stop + * condition, this will return back after time out condition. Otherwise, + * next session that is slave receive data will be completed. + */ + + /* A Stop or a repeat start condition */ + case I2C_I2STAT_S_RX_STA_STO_SLVREC_SLVTRX: + LPC_I2C->CONSET = I2C_I2CONSET_AA; + LPC_I2C->CONCLR = I2C_I2CONCLR_SIC; + Ret = I2C_STA_STO_RECV; + break; + + /* No status information */ + case I2C_I2STAT_NO_INF: + /* Other status must be captured */ + default: + LPC_I2C->CONSET = I2C_I2CONSET_AA; + LPC_I2C->CONCLR = I2C_I2CONCLR_SIC; + break; + + } + + return Ret; +} + +/***************************************************************************** + * Public functions + ****************************************************************************/ + +/* Initializes the LPC_I2C peripheral */ +void IP_I2C_Init(IP_I2C_001_Type *LPC_I2C) +{ + /* Set I2C operation to default */ + LPC_I2C->CONCLR = (I2C_I2CONCLR_AAC | I2C_I2CONCLR_SIC | I2C_I2CONCLR_STAC | I2C_I2CONCLR_I2ENC); +} + +/* De-initializes the I2C peripheral registers to their default reset values */ +void IP_I2C_DeInit(IP_I2C_001_Type *LPC_I2C) +{ + /* Disable I2C control */ + LPC_I2C->CONCLR = I2C_I2CONCLR_I2ENC; +} + +/* Set up clock rate for I2Cx */ +void IP_I2C_SetClockRate(IP_I2C_001_Type *LPC_I2C, uint32_t SCLValue) +{ + LPC_I2C->SCLH = (uint32_t) (SCLValue / 2); + LPC_I2C->SCLL = (uint32_t) (SCLValue - LPC_I2C->SCLH); +} + +/* Enable or disable I2C peripheral's operation */ +void IP_I2C_Cmd(IP_I2C_001_Type *LPC_I2C, I2C_Mode Mode, FunctionalState NewState) +{ + if (NewState == ENABLE) { + if (Mode != I2C_SLAVE_MODE) { + LPC_I2C->CONSET = I2C_I2CONSET_I2EN; + } + else { + LPC_I2C->CONSET = I2C_I2CONSET_I2EN | I2C_I2CONSET_AA; + } + } + else { + LPC_I2C->CONCLR = I2C_I2CONCLR_I2ENC; + } +} + +/* General Master Interrupt handler for I2C peripheral */ +void IP_I2C_Interrupt_MasterHandler(IP_I2C_001_Type *LPC_I2C, I2C_ID_Type I2C_Num) +{ + uint32_t returnCode; + I2C_M_SETUP_Type *txrx_setup; + int32_t Ret = I2C_OK; + + txrx_setup = (I2C_M_SETUP_Type *) &i2cdat[I2C_Num].txrx_setup_master; + + while (!(LPC_I2C->CONSET & I2C_I2CONSET_SI)) {} + + returnCode = (uint32_t) (LPC_I2C->STAT & I2C_STAT_CODE_BITMASK); + + /* Save current status */ + txrx_setup->status = returnCode; + + Ret = IP_I2C_MasterHanleStates(LPC_I2C, returnCode, txrx_setup, I2C_TRANSFER_INTERRUPT); + + if (I2C_CheckError(Ret)) { + if (txrx_setup->retransmissions_count < txrx_setup->retransmissions_max) { + /* Retry */ + txrx_setup->retransmissions_count++; + txrx_setup->tx_count = 0; + txrx_setup->rx_count = 0; + /* Reset STA, STO, SI */ + IP_I2C_Start(LPC_I2C, I2C_TRANSFER_INTERRUPT); + return; + } + else { + goto s_int_end; + } + } + else if (Ret & I2C_SEND_END) { + /* If no need to wait for data from Slave */ + if (txrx_setup->rx_count >= (txrx_setup->rx_length)) { + goto s_int_end; + } + else { /* Start to wait for data from Slave */ + /* Reset STA, STO, SI */ + IP_I2C_Start(LPC_I2C, I2C_TRANSFER_INTERRUPT); + return; + } + } + else if (Ret & I2C_RECV_END) { + goto s_int_end; + } + else { + return; + } + +s_int_end: + + LPC_I2C->CONCLR = I2C_I2CONCLR_AAC | I2C_I2CONCLR_SIC | I2C_I2CONCLR_STAC; + + I2C_MasterComplete[I2C_Num] = true; +} + +/* General Slave Interrupt handler for I2C peripheral */ +void IP_I2C_Interrupt_SlaveHandler(IP_I2C_001_Type *LPC_I2C, I2C_ID_Type I2C_Num) +{ + uint32_t returnCode; + I2C_S_SETUP_Type *txrx_setup; + int32_t Ret = I2C_OK; + + txrx_setup = (I2C_S_SETUP_Type *) &i2cdat[I2C_Num].txrx_setup_slave; + + while (!(LPC_I2C->CONSET & I2C_I2CONSET_SI)) {} + + returnCode = (uint32_t) (LPC_I2C->STAT & I2C_STAT_CODE_BITMASK); + /* Save current status */ + txrx_setup->status = returnCode; + + Ret = IP_I2C_SlaveHanleStates(LPC_I2C, returnCode, txrx_setup); + + if ((I2C_CheckError(Ret)) || (Ret & I2C_STA_STO_RECV) || (Ret & I2C_SEND_END)) { + goto s_int_end; + } + else { + return; + } + +s_int_end: + LPC_I2C->CONCLR = I2C_I2CONCLR_AAC | I2C_I2CONCLR_SIC | I2C_I2CONCLR_STAC; + + I2C_SlaveComplete[I2C_Num] = true; +} + +/* Transmit and Receive data in master mode */ +Status IP_I2C_MasterTransferData(IP_I2C_001_Type *LPC_I2C, + I2C_ID_Type I2C_Num, + I2C_M_SETUP_Type *TransferCfg, + I2C_TRANSFER_OPT_Type Opt) +{ + uint32_t CodeStatus; + int32_t Ret = I2C_OK; + + /* Reset I2C setup value to default state */ + TransferCfg->tx_count = 0; + TransferCfg->rx_count = 0; + TransferCfg->status = 0; + + if (Opt == I2C_TRANSFER_POLLING) { + /* First Start condition -------------------------------------------------------------- */ + TransferCfg->retransmissions_count = 0; +retry: + /* Reset I2C setup value to default state */ + TransferCfg->tx_count = 0; + TransferCfg->rx_count = 0; + + /* Start command */ + CodeStatus = IP_I2C_Start(LPC_I2C, I2C_TRANSFER_POLLING); + + while (1) { /* send data first and then receive data from Slave */ + Ret = IP_I2C_MasterHanleStates(LPC_I2C, CodeStatus, TransferCfg, I2C_TRANSFER_POLLING); + if (I2C_CheckError(Ret)) { + TransferCfg->retransmissions_count++; + if (TransferCfg->retransmissions_count > TransferCfg->retransmissions_max) { + /* save status */ + TransferCfg->status = CodeStatus | I2C_SETUP_STATUS_NOACKF; + goto error; + } + else { + goto retry; + } + } + else if ( (Ret & I2C_BYTE_SENT) || + (Ret & I2C_BYTE_RECV)) { + /* Wait for sending ends/ Wait for next byte */ + while (!(LPC_I2C->CONSET & I2C_I2CONSET_SI)) {} + } + else if (Ret & I2C_SEND_END) { /* already send all data */ + /* If no need to wait for data from Slave */ + if (TransferCfg->rx_count >= (TransferCfg->rx_length)) { + break; + } + else { + IP_I2C_Start(LPC_I2C, I2C_TRANSFER_POLLING); + } + } + else if (Ret & I2C_RECV_END) { /* already receive all data */ + break; + } + CodeStatus = LPC_I2C->STAT & I2C_STAT_CODE_BITMASK; + } + return SUCCESS; +error: + return ERROR; + } + else if (Opt == I2C_TRANSFER_INTERRUPT) { + I2C_MasterComplete[I2C_Num] = false; + /* Setup tx_rx data, callback and interrupt handler */ + i2cdat[I2C_Num].txrx_setup_master = *TransferCfg; + + /* Set direction phase, write first */ + i2cdat[I2C_Num].dir = 0; + + /* First Start condition -------------------------------------------------------------- */ + /* Reset STA, STO, SI */ + LPC_I2C->CONCLR = I2C_I2CONCLR_SIC | I2C_I2CONCLR_STOC | I2C_I2CONCLR_STAC; + LPC_I2C->CONSET = I2C_I2CONSET_STA; + + return SUCCESS; + } + + return ERROR; +} + +/* Receive and Transmit data in slave mode */ +Status IP_I2C_SlaveTransferData(IP_I2C_001_Type *LPC_I2C, + I2C_ID_Type I2C_Num, + I2C_S_SETUP_Type *TransferCfg, + I2C_TRANSFER_OPT_Type Opt) +{ + int32_t Ret = I2C_OK; + uint32_t CodeStatus = 0; + + /* Reset I2C setup value to default state */ + TransferCfg->tx_count = 0; + TransferCfg->rx_count = 0; + TransferCfg->status = 0; + + /* Polling option */ + if (Opt == I2C_TRANSFER_POLLING) { + /* Set AA bit to ACK command on I2C bus */ + LPC_I2C->CONSET = I2C_I2CONSET_AA; + + /* Clear SI bit to be ready ... */ + LPC_I2C->CONCLR = (I2C_I2CONCLR_SIC | I2C_I2CONCLR_STAC | I2C_I2CONCLR_STOC); + + while (1) { + /* Check SI flag ready */ + if (LPC_I2C->CONSET & I2C_I2CONSET_SI) { + CodeStatus = (LPC_I2C->STAT & I2C_STAT_CODE_BITMASK); + + Ret = IP_I2C_SlaveHanleStates(LPC_I2C, CodeStatus, TransferCfg); + if (I2C_CheckError(Ret)) { + goto s_error; + } + else if ((Ret & I2C_STA_STO_RECV) || (Ret & I2C_SEND_END)) { + goto s_end_stage; + } + } + } + +s_end_stage: + /* Clear AA bit to disable ACK on I2C bus */ + LPC_I2C->CONCLR = I2C_I2CONCLR_AAC; + + /* Check if there's no error during operation + * Update status + */ + TransferCfg->status = CodeStatus | I2C_SETUP_STATUS_DONE; + return SUCCESS; + +s_error: + /* Clear AA bit to disable ACK on I2C bus */ + LPC_I2C->CONCLR = I2C_I2CONCLR_AAC; + + /* Update status */ + TransferCfg->status = CodeStatus; + return ERROR; + } + + else if (Opt == I2C_TRANSFER_INTERRUPT) { + I2C_SlaveComplete[I2C_Num] = false; + /* Setup tx_rx data, callback and interrupt handler */ + i2cdat[I2C_Num].txrx_setup_slave = *TransferCfg; + + /* Set direction phase, read first */ + i2cdat[I2C_Num].dir = 1; + + /* Enable AA */ + LPC_I2C->CONSET = I2C_I2CONSET_AA; + LPC_I2C->CONCLR = I2C_I2CONCLR_SIC | I2C_I2CONCLR_STAC; + + return SUCCESS; + } + + return ERROR; +} + +/* Get status of Master Transfer */ +bool IP_I2C_Interrupt_MasterTransferComplete(I2C_ID_Type I2C_Num) +{ + bool retval; + + retval = I2C_MasterComplete[I2C_Num]; + + I2C_MasterComplete[I2C_Num] = false; + + return retval; +} + +/* Get status of Slave Transfer */ +bool IP_I2C_Interrupt_SlaveTransferComplete(I2C_ID_Type I2C_Num) +{ + bool retval; + + retval = I2C_SlaveComplete[I2C_Num]; + + I2C_SlaveComplete[I2C_Num] = false; + + return retval; +} + +/* Set Own slave address in I2C peripheral corresponding to parameter specified in OwnSlaveAddrConfigStruct */ +void IP_I2C_SetOwnSlaveAddr(IP_I2C_001_Type *LPC_I2C, I2C_OWNSLAVEADDR_CFG_Type *OwnSlaveAddrConfigStruct) +{ + uint32_t tmp; + + tmp = (((uint32_t) (OwnSlaveAddrConfigStruct->SlaveAddr_7bit << 1)) \ + | ((OwnSlaveAddrConfigStruct->GeneralCallState == ENABLE) ? 0x01 : 0x00)) & I2C_I2ADR_BITMASK; + switch (OwnSlaveAddrConfigStruct->SlaveAddrChannel) { + case 0: + LPC_I2C->ADR0 = tmp; + LPC_I2C->MASK[0] = + I2C_I2MASK_MASK((uint32_t) (OwnSlaveAddrConfigStruct->SlaveAddrMaskValue)); + break; + + case 1: + LPC_I2C->ADR1 = tmp; + LPC_I2C->MASK[1] = I2C_I2MASK_MASK((uint32_t) (OwnSlaveAddrConfigStruct->SlaveAddrMaskValue)); + break; + + case 2: + LPC_I2C->ADR2 = tmp; + LPC_I2C->MASK[2] = I2C_I2MASK_MASK((uint32_t) (OwnSlaveAddrConfigStruct->SlaveAddrMaskValue)); + break; + + case 3: + LPC_I2C->ADR3 = tmp; + LPC_I2C->MASK[3] = I2C_I2MASK_MASK((uint32_t) (OwnSlaveAddrConfigStruct->SlaveAddrMaskValue)); + break; + } +} diff --git a/bsp/xplorer4330/libraries/lpc_ip/i2c_001.h b/bsp/xplorer4330/libraries/lpc_ip/i2c_001.h new file mode 100644 index 0000000000..a3928cb459 --- /dev/null +++ b/bsp/xplorer4330/libraries/lpc_ip/i2c_001.h @@ -0,0 +1,412 @@ +/* + * @brief I2C registers and driver functions + * + * @note + * Copyright(C) NXP Semiconductors, 2012 + * All rights reserved. + * + * @par + * Software that is described herein is for illustrative purposes only + * which provides customers with programming information regarding the + * LPC products. This software is supplied "AS IS" without any warranties of + * any kind, and NXP Semiconductors and its licensor disclaim any and + * all warranties, express or implied, including all implied warranties of + * merchantability, fitness for a particular purpose and non-infringement of + * intellectual property rights. NXP Semiconductors assumes no responsibility + * or liability for the use of the software, conveys no license or rights under any + * patent, copyright, mask work right, or any other intellectual property rights in + * or to any products. NXP Semiconductors reserves the right to make changes + * in the software without notification. NXP Semiconductors also makes no + * representation or warranty that such application will be suitable for the + * specified use without further testing or modification. + * + * @par + * Permission to use, copy, modify, and distribute this software and its + * documentation is hereby granted, under NXP Semiconductors' and its + * licensor's relevant copyrights in the software, without fee, provided that it + * is used in conjunction with NXP Semiconductors microcontrollers. This + * copyright, permission, and disclaimer notice must appear in all copies of + * this code. + */ + +#ifndef __I2C_001_H_ +#define __I2C_001_H_ + +#include "sys_config.h" +#include "cmsis.h" + +#ifdef __cplusplus +extern "C" { +#endif + +/** @defgroup IP_I2C_001 IP: I2C register block and driver + * @ingroup IP_Drivers + * @{ + */ + +/** + * @brief I2C register block structure + */ +typedef struct { /*!< I2C0 Structure */ + __IO uint32_t CONSET; /*!< I2C Control Set Register. When a one is written to a bit of this register, the corresponding bit in the I2C control register is set. Writing a zero has no effect on the corresponding bit in the I2C control register. */ + __I uint32_t STAT; /*!< I2C Status Register. During I2C operation, this register provides detailed status codes that allow software to determine the next action needed. */ + __IO uint32_t DAT; /*!< I2C Data Register. During master or slave transmit mode, data to be transmitted is written to this register. During master or slave receive mode, data that has been received may be read from this register. */ + __IO uint32_t ADR0; /*!< I2C Slave Address Register 0. Contains the 7-bit slave address for operation of the I2C interface in slave mode, and is not used in master mode. The least significant bit determines whether a slave responds to the General Call address. */ + __IO uint32_t SCLH; /*!< SCH Duty Cycle Register High Half Word. Determines the high time of the I2C clock. */ + __IO uint32_t SCLL; /*!< SCL Duty Cycle Register Low Half Word. Determines the low time of the I2C clock. SCLL and SCLH together determine the clock frequency generated by an I2C master and certain times used in slave mode. */ + __O uint32_t CONCLR; /*!< I2C Control Clear Register. When a one is written to a bit of this register, the corresponding bit in the I2C control register is cleared. Writing a zero has no effect on the corresponding bit in the I2C control register. */ + __IO uint32_t MMCTRL; /*!< Monitor mode control register. */ + __IO uint32_t ADR1; /*!< I2C Slave Address Register. Contains the 7-bit slave address for operation of the I2C interface in slave mode, and is not used in master mode. The least significant bit determines whether a slave responds to the General Call address. */ + __IO uint32_t ADR2; /*!< I2C Slave Address Register. Contains the 7-bit slave address for operation of the I2C interface in slave mode, and is not used in master mode. The least significant bit determines whether a slave responds to the General Call address. */ + __IO uint32_t ADR3; /*!< I2C Slave Address Register. Contains the 7-bit slave address for operation of the I2C interface in slave mode, and is not used in master mode. The least significant bit determines whether a slave responds to the General Call address. */ + __I uint32_t DATA_BUFFER; /*!< Data buffer register. The contents of the 8 MSBs of the DAT shift register will be transferred to the DATA_BUFFER automatically after every nine bits (8 bits of data plus ACK or NACK) has been received on the bus. */ + __IO uint32_t MASK[4]; /*!< I2C Slave address mask register */ +} IP_I2C_001_Type; + +/** + * @brief I2C state handle return values + */ +#define I2C_STA_STO_RECV 0x20 + +/** + * @brief I2C Control Set register description + */ +#define I2C_I2CONSET_AA ((0x04))/*!< Assert acknowledge flag */ +#define I2C_I2CONSET_SI ((0x08))/*!< I2C interrupt flag */ +#define I2C_I2CONSET_STO ((0x10))/*!< STOP flag */ +#define I2C_I2CONSET_STA ((0x20))/*!< START flag */ +#define I2C_I2CONSET_I2EN ((0x40))/*!< I2C interface enable */ + +/** + * @brief I2C Control Clear register description + */ +#define I2C_I2CONCLR_AAC ((1 << 2)) /*!< Assert acknowledge Clear bit */ +#define I2C_I2CONCLR_SIC ((1 << 3)) /*!< I2C interrupt Clear bit */ +#define I2C_I2CONCLR_STOC ((1 << 4)) /*!< I2C STOP Clear bit */ +#define I2C_I2CONCLR_STAC ((1 << 5)) /*!< START flag Clear bit */ +#define I2C_I2CONCLR_I2ENC ((1 << 6)) /*!< I2C interface Disable bit */ + +/** + * @brief I2C Status Code definition (I2C Status register) + */ +#define I2C_STAT_CODE_BITMASK ((0xF8))/*!< Return Code mask in I2C status register */ +#define I2C_STAT_CODE_ERROR ((0xFF))/*!< Return Code error mask in I2C status register */ + +/** + * @brief I2C return status code definitions + */ +#define I2C_I2STAT_NO_INF ((0xF8))/*!< No relevant information */ +#define I2C_I2STAT_BUS_ERROR ((0x00))/*!< Bus Error */ + +/** + * @brief I2C Master transmit mode + */ +#define I2C_I2STAT_M_TX_START ((0x08))/*!< A start condition has been transmitted */ +#define I2C_I2STAT_M_TX_RESTART ((0x10))/*!< A repeat start condition has been transmitted */ +#define I2C_I2STAT_M_TX_SLAW_ACK ((0x18))/*!< SLA+W has been transmitted, ACK has been received */ +#define I2C_I2STAT_M_TX_SLAW_NACK ((0x20))/*!< SLA+W has been transmitted, NACK has been received */ +#define I2C_I2STAT_M_TX_DAT_ACK ((0x28))/*!< Data has been transmitted, ACK has been received */ +#define I2C_I2STAT_M_TX_DAT_NACK ((0x30))/*!< Data has been transmitted, NACK has been received */ +#define I2C_I2STAT_M_TX_ARB_LOST ((0x38))/*!< Arbitration lost in SLA+R/W or Data bytes */ + +/** + * @brief I2C Master receive mode + */ +#define I2C_I2STAT_M_RX_START ((0x08))/*!< A start condition has been transmitted */ +#define I2C_I2STAT_M_RX_RESTART ((0x10))/*!< A repeat start condition has been transmitted */ +#define I2C_I2STAT_M_RX_ARB_LOST ((0x38))/*!< Arbitration lost */ +#define I2C_I2STAT_M_RX_SLAR_ACK ((0x40))/*!< SLA+R has been transmitted, ACK has been received */ +#define I2C_I2STAT_M_RX_SLAR_NACK ((0x48))/*!< SLA+R has been transmitted, NACK has been received */ +#define I2C_I2STAT_M_RX_DAT_ACK ((0x50))/*!< Data has been received, ACK has been returned */ +#define I2C_I2STAT_M_RX_DAT_NACK ((0x58))/*!< Data has been received, NACK has been returned */ + +/** + * @brief I2C Slave receive mode + */ +#define I2C_I2STAT_S_RX_SLAW_ACK ((0x60))/*!< Own slave address has been received, ACK has been returned */ +#define I2C_I2STAT_S_RX_ARB_LOST_M_SLA ((0x68))/*!< Arbitration lost in SLA+R/W as master */ +// #define I2C_I2STAT_S_RX_SLAW_ACK ((0x68)) /*!< Own SLA+W has been received, ACK returned */ +#define I2C_I2STAT_S_RX_GENCALL_ACK ((0x70))/*!< General call address has been received, ACK has been returned */ +#define I2C_I2STAT_S_RX_ARB_LOST_M_GENCALL ((0x78))/*!< Arbitration lost in SLA+R/W (GENERAL CALL) as master */ +// #define I2C_I2STAT_S_RX_GENCALL_ACK ((0x78)) /*!< General call address has been received, ACK has been returned */ +#define I2C_I2STAT_S_RX_PRE_SLA_DAT_ACK ((0x80))/*!< Previously addressed with own SLA; Data has been received, ACK has been returned */ +#define I2C_I2STAT_S_RX_PRE_SLA_DAT_NACK ((0x88))/*!< Previously addressed with own SLA;Data has been received and NOT ACK has been returned */ +#define I2C_I2STAT_S_RX_PRE_GENCALL_DAT_ACK ((0x90))/*!< Previously addressed with General Call; Data has been received and ACK has been returned */ +#define I2C_I2STAT_S_RX_PRE_GENCALL_DAT_NACK ((0x98))/*!< Previously addressed with General Call; Data has been received and NOT ACK has been returned */ +#define I2C_I2STAT_S_RX_STA_STO_SLVREC_SLVTRX ((0xA0))/*!< A STOP condition or repeated START condition has been received while still addressed as SLV/REC (Slave Receive) or + SLV/TRX (Slave Transmit) */ + +/** + * @brief I2C Slave transmit mode + */ +#define I2C_I2STAT_S_TX_SLAR_ACK ((0xA8))/*!< Own SLA+R has been received, ACK has been returned */ +#define I2C_I2STAT_S_TX_ARB_LOST_M_SLA ((0xB0))/*!< Arbitration lost in SLA+R/W as master */ +// #define I2C_I2STAT_S_TX_SLAR_ACK ((0xB0)) /*!< Own SLA+R has been received, ACK has been returned */ +#define I2C_I2STAT_S_TX_DAT_ACK ((0xB8))/*!< Data has been transmitted, ACK has been received */ +#define I2C_I2STAT_S_TX_DAT_NACK ((0xC0))/*!< Data has been transmitted, NACK has been received */ +#define I2C_I2STAT_S_TX_LAST_DAT_ACK ((0xC8))/*!< Last data byte in I2DAT has been transmitted (AA = 0); ACK has been received */ +#define I2C_SLAVE_TIME_OUT 0x10000000UL/*!< Time out in case of using I2C slave mode */ + +/** + * @brief I2C Data register definition + */ +#define I2C_I2DAT_BITMASK ((0xFF))/*!< Mask for I2DAT register */ +#define I2C_I2DAT_IDLE_CHAR (0xFF) /*!< Idle data value will be send out in slave mode in case of the actual expecting data requested from the master is greater than + its sending data length that can be supported */ + +/** + * @brief I2C Monitor mode control register description + */ +#define I2C_I2MMCTRL_MM_ENA ((1 << 0)) /**< Monitor mode enable */ +#define I2C_I2MMCTRL_ENA_SCL ((1 << 1)) /**< SCL output enable */ +#define I2C_I2MMCTRL_MATCH_ALL ((1 << 2)) /**< Select interrupt register match */ +#define I2C_I2MMCTRL_BITMASK ((0x07)) /**< Mask for I2MMCTRL register */ + +/** + * @brief I2C Data buffer register description + */ +#define I2DATA_BUFFER_BITMASK ((0xFF))/*!< I2C Data buffer register bit mask */ + +/** + * @brief I2C Slave Address registers definition + */ +#define I2C_I2ADR_GC ((1 << 0)) /*!< General Call enable bit */ +#define I2C_I2ADR_BITMASK ((0xFF))/*!< I2C Slave Address registers bit mask */ + +/** + * @brief I2C Mask Register definition + */ +#define I2C_I2MASK_MASK(n) ((n & 0xFE))/*!< I2C Mask Register mask field */ + +/** + * @brief I2C SCL HIGH duty cycle Register definition + */ +#define I2C_I2SCLH_BITMASK ((0xFFFF)) /*!< I2C SCL HIGH duty cycle Register bit mask */ + +/** + * @brief I2C SCL LOW duty cycle Register definition + */ +#define I2C_I2SCLL_BITMASK ((0xFFFF)) /*!< I2C SCL LOW duty cycle Register bit mask */ + +/** + * @brief I2C status values + */ +#define I2C_SETUP_STATUS_ARBF (1 << 8) /**< Arbitration false */ +#define I2C_SETUP_STATUS_NOACKF (1 << 9) /**< No ACK returned */ +#define I2C_SETUP_STATUS_DONE (1 << 10) /**< Status DONE */ + +/** + * @brief I2C state handle return values + */ +#define I2C_OK 0x00 +#define I2C_BYTE_SENT 0x01 +#define I2C_BYTE_RECV 0x02 +#define I2C_LAST_BYTE_RECV 0x04 +#define I2C_SEND_END 0x08 +#define I2C_RECV_END 0x10 +#define I2C_STA_STO_RECV 0x20 + +#define I2C_ERR (0x10000000) +#define I2C_NAK_RECV (0x10000000 | 0x01) + +#define I2C_CheckError(ErrorCode) (ErrorCode & 0x10000000) + +/** + * @brief I2C monitor control configuration defines + */ +#define I2C_MONITOR_CFG_SCL_OUTPUT I2C_I2MMCTRL_ENA_SCL /**< SCL output enable */ +#define I2C_MONITOR_CFG_MATCHALL I2C_I2MMCTRL_MATCH_ALL /**< Select interrupt register match */ + +/** + * @brief Master transfer setup data structure definitions + */ +typedef struct { + uint32_t sl_addr7bit; /**< Slave address in 7bit mode */ + uint8_t *tx_data; /**< Pointer to Transmit data - NULL if data transmit is not used */ + uint32_t tx_length; /**< Transmit data length - 0 if data transmit is not used*/ + uint32_t tx_count; /**< Current Transmit data counter */ + uint8_t *rx_data; /**< Pointer to Receive data - NULL if data receive is not used */ + uint32_t rx_length; /**< Receive data length - 0 if data receive is not used */ + uint32_t rx_count; /**< Current Receive data counter */ + uint32_t retransmissions_max; /**< Max Re-Transmission value */ + uint32_t retransmissions_count;/**< Current Re-Transmission counter */ + uint32_t status; /**< Current status of I2C activity */ +} I2C_M_SETUP_Type; + +/** + * @brief Slave transfer setup data structure definitions + */ +typedef struct { + uint8_t *tx_data; /**< Pointer to transmit data - NULL if data transmit is not used */ + uint32_t tx_length; /**< Transmit data length - 0 if data transmit is not used */ + uint32_t tx_count; /**< Current transmit data counter */ + uint8_t *rx_data; /**< Pointer to receive data - NULL if data received is not used */ + uint32_t rx_length; /**< Receive data length - 0 if data receive is not used */ + uint32_t rx_count; /**< Current receive data counter */ + uint32_t status; /**< Current status of I2C activity */ +} I2C_S_SETUP_Type; + +/** + * @brief Transfer option type definitions + */ +typedef enum { + I2C_TRANSFER_POLLING = 0, /**< Transfer in polling mode */ + I2C_TRANSFER_INTERRUPT /**< Transfer in interrupt mode */ +} I2C_TRANSFER_OPT_Type; + +/** + * @brief I2C Own slave address setting structure + */ +typedef struct { + uint8_t SlaveAddrChannel; /**< Slave Address channel in I2C control, should be in range from 0..3 */ + uint8_t SlaveAddr_7bit; /**< Value of 7-bit slave address */ + uint8_t GeneralCallState; /**< Enable/Disable General Call Functionality when I2C control being in Slave mode, should be: + - ENABLE: Enable General Call function. + - DISABLE: Disable General Call function. */ + uint8_t SlaveAddrMaskValue; /**< Any bit in this 8-bit value (bit 7:1) which is set to '1' will cause an automatic compare on + the corresponding bit of the received address when it is compared to the SlaveAddr_7bit value associated with this + mask register. In other words, bits in SlaveAddr_7bit value which are masked are not taken into account in determining + an address match */ +} I2C_OWNSLAVEADDR_CFG_Type; + +typedef enum { + I2C_MASTER_MODE, + I2C_SLAVE_MODE, + I2C_GENERAL_MODE, +} I2C_Mode; + +typedef enum { + I2C0 = 0, +#if defined(CHIP_LPC175X_6X) || defined(CHIP_LPC177X_8X) || defined(CHIP_LPC18XX) || defined(CHIP_LPC43XX) + I2C1, +#if defined(CHIP_LPC175X_6X) || defined(CHIP_LPC177X_8X) + I2C2, +#endif +#endif +} I2C_ID_Type; + +/** + * @brief Initializes the LPC_I2C peripheral. + * @param LPC_I2C : Pointer to selected I2Cx peripheral + * @return Nothing + */ +void IP_I2C_Init(IP_I2C_001_Type *LPC_I2C); + +/** + * @brief De-initializes the I2C peripheral registers to their default reset values. + * @param LPC_I2C : Pointer to selected I2Cx peripheral + * @return Nothing + */ +void IP_I2C_DeInit(IP_I2C_001_Type *LPC_I2C); + +/** + * @brief Set up clock rate for I2Cx. + * @param LPC_I2C : Pointer to selected I2Cx peripheral + * @param SCLValue : Value of I2CSCL register + * @return Nothing + */ +void IP_I2C_SetClockRate(IP_I2C_001_Type *LPC_I2C, uint32_t SCLValue); + +/** + * @brief Enable or disable I2C peripheral's operation + * @param LPC_I2C : Pointer to selected I2Cx peripheral + * @param Mode : I2C mode, should be I2C_MASTER_MODE, I2C_SLAVE_MODE or I2C_GENERAL_MODE + * @param NewState : New State of LPC_I2C peripheral's operation, should be ENABLE or DISABLE + * @return Nothing + */ +void IP_I2C_Cmd(IP_I2C_001_Type *LPC_I2C, I2C_Mode Mode, FunctionalState NewState); + +/** + * @brief General Master Interrupt handler for I2C peripheral + * @param LPC_I2C : Pointer to selected I2Cx peripheral + * @param I2C_Num : I2C port number, should be I2C0, I2C1 or I2C2 + * @return Nothing + */ +void IP_I2C_Interrupt_MasterHandler(IP_I2C_001_Type *LPC_I2C, I2C_ID_Type I2C_Num); + +/** + * @brief General Slave Interrupt handler for I2C peripheral + * @param LPC_I2C : Pointer to selected I2Cx peripheral + * @param I2C_Num : I2C port number, should be I2C0, I2C1 or I2C2 + * @return Nothing + */ +void IP_I2C_Interrupt_SlaveHandler (IP_I2C_001_Type *LPC_I2C, I2C_ID_Type I2C_Num); + +/** + * @brief Transmit and Receive data in master mode + * @param LPC_I2C : Pointer to selected I2Cx peripheral + * @param I2C_Num : I2C port number, should be I2C0, I2C1 or I2C2 + * @param TransferCfg : Pointer to a I2C_M_SETUP_Type structure that contains specified + * information about the configuration for master transfer. + * @param Opt : a I2C_TRANSFER_OPT_Type type that selected for interrupt or polling mode. + * @return SUCCESS or ERROR + * + * Note: + * - In case of using I2C to transmit/receive data only, either transmit/receive length set to 0 + * or transmit/receive data pointer set to NULL. + * - In case of using I2C to transmit followed by receive data, transmit length, transmit data + * pointer, receive length and receive data pointer should be set corresponding. + */ +Status IP_I2C_MasterTransferData(IP_I2C_001_Type *LPC_I2C, + I2C_ID_Type I2C_Num, + I2C_M_SETUP_Type *TransferCfg, + I2C_TRANSFER_OPT_Type Opt); + +/** + * @brief Receive and Transmit data in slave mode + * @param LPC_I2C : Pointer to selected I2Cx peripheral + * @param I2C_Num : I2C port number, should be I2C0, I2C1 or I2C2 + * @param TransferCfg : Pointer to a I2C_S_SETUP_Type structure that contains specified information + * about the configuration for master transfer. + * @param Opt : I2C_TRANSFER_OPT_Type type that selected for interrupt or polling mode. + * @return SUCCESS or ERROR + * + * Note: + * The mode of slave's operation depends on the command sent from master on the I2C bus. If the master + * send a SLA+W command, this sub-routine will use receive data length and receive data pointer. If the + * master send a SLA+R command, this sub-routine will use transmit data length and transmit data pointer. + * If the master issue an repeat start command or a stop command, the slave will enable an time out condition, + * during time out condition, if there's no activity on I2C bus, the slave will exit, otherwise (i.e. the master + * send a SLA+R/W), the slave then switch to relevant operation mode. The time out should be used because the + * return status code can not show difference from stop and repeat start command in slave operation. + * In case of the expected data length from master is greater than data length that slave can support: + * - In case of reading operation (from master): slave will return I2C_I2DAT_IDLE_CHAR value. + * - In case of writing operation (from master): slave will ignore remain data from master. + */ +Status IP_I2C_SlaveTransferData(IP_I2C_001_Type *LPC_I2C, + I2C_ID_Type I2C_Num, + I2C_S_SETUP_Type *TransferCfg, + I2C_TRANSFER_OPT_Type Opt); + +/** + * @brief Get status of Master Transfer + * @param I2C_Num : I2C port number, should be I2C0, I2C1 or I2C2 + * @return Master transfer status, could be TRUE (completed) or FALSE (not completed yet) + */ +bool IP_I2C_Interrupt_MasterTransferComplete(I2C_ID_Type I2C_Num); + +/** + * @brief Get status of Slave Transfer + * @param I2C_Num : I2C port number, should be I2C0, I2C1 or I2C2 + * @return Slave transfer status, could be TRUE (completed) or FALSE (not completed yet) + */ +bool IP_I2C_Interrupt_SlaveTransferComplete(I2C_ID_Type I2C_Num); + +/** + * @brief Set Own slave address in I2C peripheral corresponding to parameter specified in OwnSlaveAddrConfigStruct. + * @param LPC_I2C : I2C peripheral selected + * @param OwnSlaveAddrConfigStruct : Pointer to a I2C_OWNSLAVEADDR_CFG_Type structure that contains the + * configuration information for the specified I2C slave address. + * @return Nothing + */ +void IP_I2C_SetOwnSlaveAddr(IP_I2C_001_Type *LPC_I2C, I2C_OWNSLAVEADDR_CFG_Type *OwnSlaveAddrConfigStruct); + +/** + * @} + */ + +#ifdef __cplusplus +} +#endif + +#endif /* __I2C_001_H_ */ diff --git a/bsp/xplorer4330/libraries/lpc_ip/i2s_001.c b/bsp/xplorer4330/libraries/lpc_ip/i2s_001.c new file mode 100644 index 0000000000..bdfa248e40 --- /dev/null +++ b/bsp/xplorer4330/libraries/lpc_ip/i2s_001.c @@ -0,0 +1,327 @@ +/* + * @brief I2S Registers and control functions + * + * @note + * Copyright(C) NXP Semiconductors, 2012 + * All rights reserved. + * + * @par + * Software that is described herein is for illustrative purposes only + * which provides customers with programming information regarding the + * LPC products. This software is supplied "AS IS" without any warranties of + * any kind, and NXP Semiconductors and its licensor disclaim any and + * all warranties, express or implied, including all implied warranties of + * merchantability, fitness for a particular purpose and non-infringement of + * intellectual property rights. NXP Semiconductors assumes no responsibility + * or liability for the use of the software, conveys no license or rights under any + * patent, copyright, mask work right, or any other intellectual property rights in + * or to any products. NXP Semiconductors reserves the right to make changes + * in the software without notification. NXP Semiconductors also makes no + * representation or warranty that such application will be suitable for the + * specified use without further testing or modification. + * + * @par + * Permission to use, copy, modify, and distribute this software and its + * documentation is hereby granted, under NXP Semiconductors' and its + * licensor's relevant copyrights in the software, without fee, provided that it + * is used in conjunction with NXP Semiconductors microcontrollers. This + * copyright, permission, and disclaimer notice must appear in all copies of + * this code. + */ + +#include "i2s_001.h" + +/***************************************************************************** + * Private types/enumerations/variables + ****************************************************************************/ + +/***************************************************************************** + * Public types/enumerations/variables + ****************************************************************************/ + +/***************************************************************************** + * Private functions + ****************************************************************************/ + +/***************************************************************************** + * Public functions + ****************************************************************************/ + +/* Initialize for I2S */ +void IP_I2S_Init(IP_I2S_001_Type *pI2S) +{} + +/* Shutdown I2S */ +void IP_I2S_DeInit(IP_I2S_001_Type *pI2S) +{ + pI2S->DAI = 0x07E1; + pI2S->DAO = 0x87E1; + pI2S->IRQ = 0; + pI2S->TXMODE = 0; + pI2S->RXMODE = 0; + pI2S->DMA1 = 0; + pI2S->DMA2 = 0; +} + +/* I2S configuration functions --------*/ + +/* Selects the number of bytes in data */ +void IP_I2S_SetWordWidth(IP_I2S_001_Type *pI2S, uint8_t TRMode, uint32_t wordwidth) +{ + if (TRMode == I2S_TX_MODE) { + pI2S->DAO &= ~I2S_DAO_WORDWIDTH_MASK; + pI2S->DAO |= wordwidth; + } + else { + pI2S->DAI &= ~I2S_DAI_WORDWIDTH_MASK; + pI2S->DAI |= wordwidth; + } +} + +/* Set I2S data format is monaural or stereo */ +void IP_I2S_SetMono(IP_I2S_001_Type *pI2S, uint8_t TRMode, uint32_t mono) +{ + if (TRMode == I2S_TX_MODE) { + pI2S->DAO &= ~I2S_DAO_MONO; + pI2S->DAO |= mono; + } + else { + pI2S->DAI &= ~I2S_DAI_MONO; + pI2S->DAI |= mono; + } +} + +/* Set I2S interface in master/slave mode */ +void IP_I2S_SetMasterSlaveMode(IP_I2S_001_Type *pI2S, uint8_t TRMode, uint32_t mode) +{ + if (TRMode == I2S_TX_MODE) { + pI2S->DAO &= ~I2S_DAO_SLAVE; + pI2S->DAO |= mode; + } + else { + pI2S->DAI &= ~I2S_DAI_SLAVE; + pI2S->DAI |= mode; + } +} + +/* Set the clock frequency for I2S interface */ +void IP_I2S_SetBitRate(IP_I2S_001_Type *pI2S, uint8_t TRMode, uint32_t mclk_divider) +{ + if (TRMode == I2S_TX_MODE) { + pI2S->TXBITRATE = mclk_divider; + } + else { + pI2S->RXBITRATE = mclk_divider; + } +} + +/* Set the MCLK rate by using a fractional rate generator, dividing down the frequency of PCLK */ +void IP_I2S_SetXYDivider(IP_I2S_001_Type *pI2S, uint8_t TRMode, uint8_t x_divider, uint8_t y_divider) +{ + if (TRMode == I2S_TX_MODE) { + pI2S->TXRATE = y_divider | (x_divider << 8); + } + else { + pI2S->RXRATE = y_divider | (x_divider << 8); + } +} + +/* Set word select (WS) half period */ +void IP_I2S_SetWS_Halfperiod(IP_I2S_001_Type *pI2S, uint8_t TRMode, uint32_t ws_halfperiod) +{ + if (TRMode == I2S_TX_MODE) { + pI2S->DAO &= ~I2S_DAO_WS_HALFPERIOD_MASK; + pI2S->DAO |= I2S_DAO_WS_HALFPERIOD(ws_halfperiod); + } + else { + pI2S->DAI &= ~I2S_DAI_WS_HALFPERIOD_MASK; + pI2S->DAI |= I2S_DAI_WS_HALFPERIOD(ws_halfperiod); + } +} + +/* Set the I2S operating modes */ +void IP_I2S_ModeConfig(IP_I2S_001_Type *pI2S, uint8_t TRMode, uint32_t clksel, uint32_t fpin, uint32_t mcena) +{ + if (TRMode == I2S_TX_MODE) { + pI2S->TXMODE = clksel | fpin | mcena; + } + else { + pI2S->RXMODE = clksel | fpin | mcena; + } +} + +/* Get the current level of the Transmit/Receive FIFO */ +uint8_t IP_I2S_GetLevel(IP_I2S_001_Type *pI2S, uint8_t TRMode) +{ + if (TRMode == I2S_TX_MODE) { + return (pI2S->STATE >> 16) & 0xF; + } + else { + return (pI2S->STATE >> 8) & 0xF; + } +} + +/* I2S operate functions -------------*/ + +/* Send a 32-bit data to TXFIFO for transmition */ +void IP_I2S_Send(IP_I2S_001_Type *pI2S, uint32_t data) +{ + pI2S->TXFIFO = data; +} + +/* Get received data from RXFIFO */ +uint32_t IP_I2S_Receive(IP_I2S_001_Type *pI2S) +{ + return pI2S->RXFIFO; +} + +/* Start the I2S */ +void IP_I2S_Start(IP_I2S_001_Type *pI2S, uint8_t TRMode) +{ + if (TRMode == I2S_TX_MODE) { + pI2S->DAO &= ~(I2S_DAO_RESET | I2S_DAO_STOP | I2S_DAO_MUTE); + } + else { + pI2S->DAI &= ~(I2S_DAI_RESET | I2S_DAI_STOP); + } +} + +/* Disables accesses on FIFOs, places the transmit channel in mute mode */ +void IP_I2S_Pause(IP_I2S_001_Type *pI2S, uint8_t TRMode) +{ + if (TRMode == I2S_TX_MODE) { + pI2S->DAO |= I2S_DAO_STOP; + } + else { + pI2S->DAI |= I2S_DAI_STOP; + } +} + +/* Transmit channel sends only zeroes */ +void IP_I2S_Mute(IP_I2S_001_Type *pI2S, FunctionalState NewState) +{ + if (NewState == ENABLE) { + pI2S->DAO |= I2S_DAO_MUTE; + } + else { + pI2S->DAO &= ~I2S_DAO_MUTE; + } +} + +/* Pause, resets the transmit channel and FIFO asynchronously */ +void IP_I2S_Stop(IP_I2S_001_Type *pI2S, uint8_t TRMode) +{ + if (TRMode == I2S_TX_MODE) { + pI2S->DAO &= ~I2S_DAO_MUTE; + pI2S->DAO |= I2S_DAO_STOP | I2S_DAO_RESET; + } + else { + pI2S->DAI |= I2S_DAI_STOP | I2S_DAI_RESET; + } +} + +/* I2S DMA functions ----------------*/ + +/* Set the FIFO level on which to create an DMA request */ +void IP_I2S_DMACmd(IP_I2S_001_Type *pI2S, IP_I2S_DMARequestNumber_Type DMANum, uint8_t TRMode, FunctionalState NewState) +{ + if (TRMode == I2S_RX_MODE) { + if (DMANum == IP_I2S_DMA_REQUEST_NUMBER_1) { + if (NewState == ENABLE) { + pI2S->DMA1 |= 0x01; + } + else { + pI2S->DMA1 &= ~0x01; + } + } + else { + if (NewState == ENABLE) { + pI2S->DMA2 |= 0x01; + } + else { + pI2S->DMA2 &= ~0x01; + } + } + } + else { + if (DMANum == IP_I2S_DMA_REQUEST_NUMBER_1) { + if (NewState == ENABLE) { + pI2S->DMA1 |= 0x02; + } + else { + pI2S->DMA1 &= ~0x02; + } + } + else { + if (NewState == ENABLE) { + pI2S->DMA2 |= 0x02; + } + else { + pI2S->DMA2 &= ~0x02; + } + } + } +} + +/* Enable/Disable DMA for the I2S */ +void IP_I2S_SetFIFODepthDMA(IP_I2S_001_Type *pI2S, uint8_t TRMode, IP_I2S_DMARequestNumber_Type DMANum, uint32_t depth) +{ + if (TRMode == I2S_RX_MODE) { + if (DMANum == IP_I2S_DMA_REQUEST_NUMBER_1) { + pI2S->DMA1 &= ~(0x0F << 8); + pI2S->DMA1 |= depth << 8; + } + else { + pI2S->DMA2 &= ~(0x0F << 8); + pI2S->DMA2 |= depth << 8; + } + } + else { + if (DMANum == IP_I2S_DMA_REQUEST_NUMBER_1) { + pI2S->DMA1 &= ~(0x0F << 16); + pI2S->DMA1 |= depth << 16; + } + else { + pI2S->DMA2 &= ~(0x0F << 16); + pI2S->DMA2 |= depth << 16; + } + } +} + +/* I2S IRQ functions ----------------*/ + +/* Enable/Disable interrupt for the I2S */ +void IP_I2S_InterruptCmd(IP_I2S_001_Type *pI2S, uint8_t TRMode, FunctionalState NewState) +{ + if (NewState == ENABLE) { + pI2S->IRQ |= (TRMode == I2S_RX_MODE) ? 0x01 : 0x02; + } + else { + pI2S->IRQ &= (TRMode == I2S_RX_MODE) ? (~0x01) : (~0x02); + } +} + +/* Set the FIFO level on which to create an irq request */ +void IP_I2S_SetFIFODepthIRQ(IP_I2S_001_Type *pI2S, uint8_t TRMode, uint32_t depth) +{ + depth &= 0x0F; + if (TRMode == I2S_RX_MODE) { + pI2S->IRQ &= ~I2S_IRQ_RX_DEPTH_MASK; + pI2S->IRQ |= I2S_IRQ_RX_DEPTH(depth); + } + else { + pI2S->IRQ &= ~I2S_IRQ_TX_DEPTH_MASK; + pI2S->IRQ |= I2S_IRQ_TX_DEPTH(depth); + } +} + +/* Get the status of I2S interrupt */ +Status IP_I2S_GetIntStatus(IP_I2S_001_Type *pI2S, uint8_t TRMode) +{ + if (TRMode == I2S_TX_MODE) { + return (Status) (((pI2S->IRQ >> 1) & 0x01) & ((pI2S->STATE) & 0x01)); + } + else { + return (Status) (((pI2S->IRQ) & 0x01) & ((pI2S->STATE) & 0x01)); + } +} diff --git a/bsp/xplorer4330/libraries/lpc_ip/i2s_001.h b/bsp/xplorer4330/libraries/lpc_ip/i2s_001.h new file mode 100644 index 0000000000..55bfcfd710 --- /dev/null +++ b/bsp/xplorer4330/libraries/lpc_ip/i2s_001.h @@ -0,0 +1,485 @@ +/* + * @brief I2S Registers and control functions + * + * @note + * Copyright(C) NXP Semiconductors, 2012 + * All rights reserved. + * + * @par + * Software that is described herein is for illustrative purposes only + * which provides customers with programming information regarding the + * LPC products. This software is supplied "AS IS" without any warranties of + * any kind, and NXP Semiconductors and its licensor disclaim any and + * all warranties, express or implied, including all implied warranties of + * merchantability, fitness for a particular purpose and non-infringement of + * intellectual property rights. NXP Semiconductors assumes no responsibility + * or liability for the use of the software, conveys no license or rights under any + * patent, copyright, mask work right, or any other intellectual property rights in + * or to any products. NXP Semiconductors reserves the right to make changes + * in the software without notification. NXP Semiconductors also makes no + * representation or warranty that such application will be suitable for the + * specified use without further testing or modification. + * + * @par + * Permission to use, copy, modify, and distribute this software and its + * documentation is hereby granted, under NXP Semiconductors' and its + * licensor's relevant copyrights in the software, without fee, provided that it + * is used in conjunction with NXP Semiconductors microcontrollers. This + * copyright, permission, and disclaimer notice must appear in all copies of + * this code. + */ + +#ifndef __I2S_001_H_ +#define __I2S_001_H_ + +#include "sys_config.h" +#include "cmsis.h" + +#ifdef __cplusplus +extern "C" { +#endif + +/** @defgroup IP_I2S_001 IP: I2S register block and driver + * @ingroup IP_Drivers + * @{ + */ + +/** + * @brief I2S register block structure + */ +typedef struct { /*!< I2S Structure */ + __IO uint32_t DAO; /*!< I2S Digital Audio Output Register. Contains control bits for the I2S transmit channel */ + __IO uint32_t DAI; /*!< I2S Digital Audio Input Register. Contains control bits for the I2S receive channel */ + __O uint32_t TXFIFO; /*!< I2S Transmit FIFO. Access register for the 8 x 32-bit transmitter FIFO */ + __I uint32_t RXFIFO; /*!< I2S Receive FIFO. Access register for the 8 x 32-bit receiver FIFO */ + __I uint32_t STATE; /*!< I2S Status Feedback Register. Contains status information about the I2S interface */ + __IO uint32_t DMA1; /*!< I2S DMA Configuration Register 1. Contains control information for DMA request 1 */ + __IO uint32_t DMA2; /*!< I2S DMA Configuration Register 2. Contains control information for DMA request 2 */ + __IO uint32_t IRQ; /*!< I2S Interrupt Request Control Register. Contains bits that control how the I2S interrupt request is generated */ + __IO uint32_t TXRATE; /*!< I2S Transmit MCLK divider. This register determines the I2S TX MCLK rate by specifying the value to divide PCLK by in order to produce MCLK */ + __IO uint32_t RXRATE; /*!< I2S Receive MCLK divider. This register determines the I2S RX MCLK rate by specifying the value to divide PCLK by in order to produce MCLK */ + __IO uint32_t TXBITRATE; /*!< I2S Transmit bit rate divider. This register determines the I2S transmit bit rate by specifying the value to divide TX_MCLK by in order to produce the transmit bit clock */ + __IO uint32_t RXBITRATE; /*!< I2S Receive bit rate divider. This register determines the I2S receive bit rate by specifying the value to divide RX_MCLK by in order to produce the receive bit clock */ + __IO uint32_t TXMODE; /*!< I2S Transmit mode control */ + __IO uint32_t RXMODE; /*!< I2S Receive mode control */ +} IP_I2S_001_Type; + +/** + * @brief I2S configuration parameter defines + */ +/** I2S Wordwidth bit */ +#define I2S_WORDWIDTH_8 (0UL << 0) +#define I2S_WORDWIDTH_16 (1UL << 0) +#define I2S_WORDWIDTH_32 (3UL << 0) +/** I2S Channel bit */ +#define I2S_STEREO (0UL << 2) +#define I2S_MONO (1UL << 2) +/** I2S Master/Slave mode bit */ +#define I2S_MASTER_MODE (0UL << 5) +#define I2S_SLAVE_MODE (1UL << 5) +/** I2S Stop bit */ +#define I2S_STOP_ENABLE (0UL << 3) +#define I2S_STOP_DISABLE (1UL << 3) +/** I2S Reset bit */ +#define I2S_RESET_ENABLE (1UL << 4) +#define I2S_RESET_DISABLE (0UL << 4) +/** I2S Mute bit */ +#define I2S_MUTE_ENABLE (1UL << 15) +#define I2S_MUTE_DISABLE (0UL << 15) + +/** + * @brief Macro defines for DAO-Digital Audio Output register + */ + +/** I2S wordwide - the number of bytes in data*/ +#define I2S_DAO_WORDWIDTH_8 ((uint32_t) (0)) /** 8 bit */ +#define I2S_DAO_WORDWIDTH_16 ((uint32_t) (1)) /** 16 bit */ +#define I2S_DAO_WORDWIDTH_32 ((uint32_t) (3)) /** 32 bit */ +#define I2S_DAO_WORDWIDTH_MASK ((uint32_t) (3)) +/** I2S control mono or stereo format */ +#define I2S_DAO_MONO ((uint32_t) (1 << 2)) +/** I2S control stop mode */ +#define I2S_DAO_STOP ((uint32_t) (1 << 3)) +/** I2S control reset mode */ +#define I2S_DAO_RESET ((uint32_t) (1 << 4)) +/** I2S control master/slave mode */ +#define I2S_DAO_SLAVE ((uint32_t) (1 << 5)) +/** I2S word select half period minus one */ +#define I2S_DAO_WS_HALFPERIOD(n) ((uint32_t) ((n & 0x1FF) << 6)) +#define I2S_DAO_WS_HALFPERIOD_MASK ((uint32_t) ((0x1FF) << 6)) +/** I2S control mute mode */ +#define I2S_DAO_MUTE ((uint32_t) (1 << 15)) + +/** + * @brief Macro defines for DAI-Digital Audio Input register + */ + +/** I2S wordwide - the number of bytes in data*/ +#define I2S_DAI_WORDWIDTH_8 ((uint32_t) (0)) /** 8 bit */ +#define I2S_DAI_WORDWIDTH_16 ((uint32_t) (1)) /** 16 bit */ +#define I2S_DAI_WORDWIDTH_32 ((uint32_t) (3)) /** 32 bit */ +#define I2S_DAI_WORDWIDTH_MASK ((uint32_t) (3)) +/** I2S control mono or stereo format */ +#define I2S_DAI_MONO ((uint32_t) (1 << 2)) +/** I2S control stop mode */ +#define I2S_DAI_STOP ((uint32_t) (1 << 3)) +/** I2S control reset mode */ +#define I2S_DAI_RESET ((uint32_t) (1 << 4)) +/** I2S control master/slave mode */ +#define I2S_DAI_SLAVE ((uint32_t) (1 << 5)) +/** I2S word select half period minus one (9 bits)*/ +#define I2S_DAI_WS_HALFPERIOD(n) ((uint32_t) ((n & 0x1FF) << 6)) +#define I2S_DAI_WS_HALFPERIOD_MASK ((uint32_t) ((0x1FF) << 6)) + +/** + * @brief Macro defines for STAT register (Status Feedback register) + */ + +/** I2S Status Receive or Transmit Interrupt */ +#define I2S_STATE_IRQ ((uint32_t) (1)) +/** I2S Status Receive or Transmit DMA1 */ +#define I2S_STATE_DMA1 ((uint32_t) (1 << 1)) +/** I2S Status Receive or Transmit DMA2 */ +#define I2S_STATE_DMA2 ((uint32_t) (1 << 2)) +/** I2S Status Current level of the Receive FIFO (5 bits)*/ +#define I2S_STATE_RX_LEVEL(n) ((uint32_t) ((n & 1F) << 8)) +/** I2S Status Current level of the Transmit FIFO (5 bits)*/ +#define I2S_STATE_TX_LEVEL(n) ((uint32_t) ((n & 1F) << 16)) + +/** + * @brief Macro defines for DMA1 register (DMA1 Configuration register) + */ + +/** I2S control DMA1 for I2S receive */ +#define I2S_DMA1_RX_ENABLE ((uint32_t) (1)) +/** I2S control DMA1 for I2S transmit */ +#define I2S_DMA1_TX_ENABLE ((uint32_t) (1 << 1)) +/** I2S set FIFO level that trigger a receive DMA request on DMA1 */ +#define I2S_DMA1_RX_DEPTH(n) ((uint32_t) ((n & 0x1F) << 8)) +/** I2S set FIFO level that trigger a transmit DMA request on DMA1 */ +#define I2S_DMA1_TX_DEPTH(n) ((uint32_t) ((n & 0x1F) << 16)) + +/** + * @brief Macro defines for DMA2 register (DMA2 Configuration register) + */ + +/** I2S control DMA2 for I2S receive */ +#define I2S_DMA2_RX_ENABLE ((uint32_t) (1)) +/** I2S control DMA1 for I2S transmit */ +#define I2S_DMA2_TX_ENABLE ((uint32_t) (1 << 1)) +/** I2S set FIFO level that trigger a receive DMA request on DMA1 */ +#define I2S_DMA2_RX_DEPTH(n) ((uint32_t) ((n & 0x1F) << 8)) +/** I2S set FIFO level that trigger a transmit DMA request on DMA1 */ +#define I2S_DMA2_TX_DEPTH(n) ((uint32_t) ((n & 0x1F) << 16)) + +/** + * @brief Macro defines for IRQ register (Interrupt Request Control register) + */ + +/** I2S control I2S receive interrupt */ +#define I2S_IRQ_RX_ENABLE ((uint32_t) (1)) +/** I2S control I2S transmit interrupt */ +#define I2S_IRQ_TX_ENABLE ((uint32_t) (1 << 1)) +/** I2S set the FIFO level on which to create an irq request */ +#define I2S_IRQ_RX_DEPTH(n) ((uint32_t) ((n & 0x0F) << 8)) +#define I2S_IRQ_RX_DEPTH_MASK ((uint32_t) ((0x0F) << 8)) +/** I2S set the FIFO level on which to create an irq request */ +#define I2S_IRQ_TX_DEPTH(n) ((uint32_t) ((n & 0x0F) << 16)) +#define I2S_IRQ_TX_DEPTH_MASK ((uint32_t) ((0x0F) << 16)) + +/** + * @brief Macro defines for TXRATE/RXRATE register (Transmit/Receive Clock Rate register) + */ + +/** I2S Transmit MCLK rate denominator */ +#define I2S_TXRATE_Y_DIVIDER(n) ((uint32_t) (n & 0xFF)) +/** I2S Transmit MCLK rate denominator */ +#define I2S_TXRATE_X_DIVIDER(n) ((uint32_t) ((n & 0xFF) << 8)) +/** I2S Receive MCLK rate denominator */ +#define I2S_RXRATE_Y_DIVIDER(n) ((uint32_t) (n & 0xFF)) +/** I2S Receive MCLK rate denominator */ +#define I2S_RXRATE_X_DIVIDER(n) ((uint32_t) ((n & 0xFF) << 8)) + +/** + * @brief Macro defines for TXBITRATE & RXBITRATE register (Transmit/Receive Bit Rate register) + */ + +#define I2S_TXBITRATE(n) ((uint32_t) (n & 0x3F)) +#define I2S_RXBITRATE(n) ((uint32_t) (n & 0x3F)) + +/** + * @brief Macro defines for TXMODE/RXMODE register (Transmit/Receive Mode Control register) + */ + +/** I2S Transmit select clock source (2 bits)*/ +#define I2S_TXMODE_CLKSEL(n) ((uint32_t) (n & 0x03)) +/** I2S Transmit control 4-pin mode */ +#define I2S_TXMODE_4PIN_ENABLE ((uint32_t) (1 << 2)) +/** I2S Transmit control the TX_MCLK output */ +#define I2S_TXMODE_MCENA ((uint32_t) (1 << 3)) +/** I2S Receive select clock source */ +#define I2S_RXMODE_CLKSEL(n) ((uint32_t) (n & 0x03)) +/** I2S Receive control 4-pin mode */ +#define I2S_RXMODE_4PIN_ENABLE ((uint32_t) (1 << 2)) +/** I2S Receive control the TX_MCLK output */ +#define I2S_RXMODE_MCENA ((uint32_t) (1 << 3)) + +/** + * @brief I2S transmit/receive mode for configuration + */ +typedef enum { + I2S_TX_MODE, + I2S_RX_MODE, +} IP_I2S_TRxMode_Type; + +/** + * @brief I2S DMA request channel define + */ +typedef enum { + IP_I2S_DMA_REQUEST_NUMBER_1, + IP_I2S_DMA_REQUEST_NUMBER_2, +} IP_I2S_DMARequestNumber_Type; + +/********************************************************************************** + * I2S Init/DeInit functions + *********************************************************************************/ + +/** + * @brief Initialize for I2S + * @param pI2S : The base of I2S peripheral on the chip + * @return Nothing + */ +void IP_I2S_Init(IP_I2S_001_Type *pI2S); + +/** + * @brief Shutdown I2S + * @param pI2S : The base of I2S peripheral on the chip + * @return Nothing + * Reset all relative registers (DMA, transmit/receive control, interrupt) to default value + */ +void IP_I2S_DeInit(IP_I2S_001_Type *pI2S); + +/********************************************************************************** + * I2S configuration functions + *********************************************************************************/ + +/** + * @brief Selects the number of bytes in data + * @param pI2S : The base of I2S peripheral on the chip + * @param TRMode : Transmit/Receive mode, should be I2S_RX_MODE or I2S_TX_MODE + * @param wordwidth : Data width, should be : + * - I2S_WORDWIDTH_8 + * - I2S_WORDWIDTH_16 + * - I2S_WORDWIDTH_32 + * @return Nothing + */ +void IP_I2S_SetWordWidth(IP_I2S_001_Type *pI2S, uint8_t TRMode, uint32_t wordwidth); + +/** + * @brief Set I2S data format is monaural or stereo + * @param pI2S : The base of I2S peripheral on the chip + * @param TRMode : Transmit/Receive mode, should be I2S_RX_MODE or I2S_TX_MODE + * @param mono : Data channel, should be + * - I2S_STEREO + * - I2S_MONO + * @return Nothing + */ +void IP_I2S_SetMono(IP_I2S_001_Type *pI2S, uint8_t TRMode, uint32_t mono); + +/** + * @brief Set I2S interface in master/slave mode + * @param pI2S : The base of I2S peripheral on the chip + * @param TRMode : Transmit/Receive mode, should be I2S_RX_MODE or I2S_TX_MODE + * @param mode : Interface mode, should be + * - I2S_MASTER_MODE + * - I2S_SLAVE_MODE + * @return Nothing + */ +void IP_I2S_SetMasterSlaveMode(IP_I2S_001_Type *pI2S, uint8_t TRMode, uint32_t mode); + +/** + * @brief Set the clock frequency for I2S interface + * @param pI2S : The base of I2S peripheral on the chip + * @param TRMode : Transmit/Receive mode, should be I2S_RX_MODE or I2S_TX_MODE + * @param mclk_divider : Clock divider. This value plus one is used to divide MCLK to produce the clock frequency for I2S interface + * @return Nothing + * The value depends on the audio sample rate desired and the data size and format(stereo/mono) used. + * For example, a 48 kHz sample rate for 16-bit stereo data requires a bit rate of 48 000 x 16 x 2 = 1.536 MHz. So the mclk_divider should be MCLK/1.536 MHz + */ +void IP_I2S_SetBitRate(IP_I2S_001_Type *pI2S, uint8_t TRMode, uint32_t mclk_divider); + +/** + * @brief Set the MCLK rate by using a fractional rate generator, dividing down the frequency of PCLK + * @param pI2S : The base of I2S peripheral on the chip + * @param TRMode : Transmit/Receive mode, should be I2S_RX_MODE or I2S_TX_MODE + * @param x_divider : I2S transmit MCLK rate numerator + * @param y_devider : I2S transmit MCLK rate denominator + * @return Nothing + * Values of the numerator (X) and the denominator (Y) must be chosen to + * produce a frequency twice that desired for the transmitter MCLK, which + * must be an integer multiple of the transmitter bit clock rate. + * The equation for the fractional rate generator is: + * MCLK = PCLK * (X/Y) /2 + * Note: If the value of X or Y is 0, then no clock is generated. Also, the value of Y must be + * greater than or equal to X. + */ +void IP_I2S_SetXYDivider(IP_I2S_001_Type *pI2S, uint8_t TRMode, uint8_t x_divider, uint8_t y_devider); + +/** + * @brief Set word select (WS) half period + * @param pI2S : The base of I2S peripheral on the chip + * @param TRMode : Transmit/Receive mode, should be I2S_RX_MODE or I2S_TX_MODE + * @param ws_halfperiod : I2S word select half period minus one + * @return Nothing + * The Word Select period is configured separately for I2S input and I2S output. + * For example: if the WS is 64clk period -> ws_halfperiod = 31 + */ +void IP_I2S_SetWS_Halfperiod(IP_I2S_001_Type *pI2S, uint8_t TRMode, uint32_t ws_halfperiod); + +/** + * @brief Set the I2S operating modes + * @param pI2S : The base of I2S peripheral on the chip + * @param TRMode : Transmit/Receive mode, should be I2S_RX_MODE or I2S_TX_MODE + * @param clksel : Clock source selection for the receive bit clock divider + * @param fpin : Receive 4-pin mode selection + * @param mcena : Enable for the RX_MCLK output + * @return Nothing + * In addition to master and slave modes, which are independently configurable for + * the transmitter and the receiver, several different clock sources are possible, + * including variations that share the clock and/or WS between the transmitter and + * receiver. It also allows using I2S with fewer pins, typically four. + */ +void IP_I2S_ModeConfig(IP_I2S_001_Type *pI2S, uint8_t TRMode, uint32_t clksel, uint32_t fpin, uint32_t mcena); + +/** + * @brief Get the current level of the Transmit/Receive FIFO + * @param pI2S : The base of I2S peripheral on the chip + * @param TRMode : Transmit/Receive mode, should be I2S_RX_MODE or I2S_TX_MODE + * @return Current level of the Transmit/Receive FIFO + */ +uint8_t IP_I2S_GetLevel(IP_I2S_001_Type *pI2S, uint8_t TRMode); + +/********************************************************************************** + * I2S operate functions + *********************************************************************************/ + +/** + * @brief Send a 32-bit data to TXFIFO for transmition + * @param pI2S : The base of I2S peripheral on the chip + * @param data : Data to be transmited + * @return Nothing + * The function writes to TXFIFO without checking any condition. + */ +void IP_I2S_Send(IP_I2S_001_Type *pI2S, uint32_t data); + +/** + * @brief Get received data from RXFIFO + * @param pI2S : The base of I2S peripheral on the chip + * @return Data received in RXFIFO + * The function reads from RXFIFO without checking any condition. + */ +uint32_t IP_I2S_Receive(IP_I2S_001_Type *pI2S); + +/** + * @brief Start the I2S + * @param pI2S : The base of I2S peripheral on the chip + * @param TRMode : Transmit/Receive mode, should be I2S_RX_MODE or I2S_TX_MODE + * @return Nothing + */ +void IP_I2S_Start(IP_I2S_001_Type *pI2S, uint8_t TRMode); + +/** + * @brief Disables accesses on FIFOs, places the transmit channel in mute mode + * @param pI2S : The base of I2S peripheral on the chip + * @param TRMode : Transmit/Receive mode, should be I2S_RX_MODE or I2S_TX_MODE + * @return Nothing + */ +void IP_I2S_Pause(IP_I2S_001_Type *pI2S, uint8_t TRMode); + +/** + * @brief Transmit channel sends only zeroes + * @param pI2S : The base of I2S peripheral on the chip + * @param NewState : Transmit/Receive mode, should be I2S_RX_MODE or I2S_TX_MODE + * @return Nothing + * The data output from I2S transmit channel is always zeroes + */ +void IP_I2S_Mute(IP_I2S_001_Type *pI2S, FunctionalState NewState); + +/** + * @brief Stop I2S asynchronously + * @param pI2S : The base of I2S peripheral on the chip + * @param TRMode : Transmit/Receive mode, should be I2S_RX_MODE or I2S_TX_MODE + * @return Nothing + * Pause, resets the transmit channel and FIFO asynchronously + */ +void IP_I2S_Stop(IP_I2S_001_Type *pI2S, uint8_t TRMode); + +/********************************************************************************** + * I2S DMA functions + *********************************************************************************/ + +/** + * @brief Set the FIFO level on which to create an DMA request + * @param pI2S : The base of I2S peripheral on the chip + * @param TRMode : Transmit/Receive mode, should be I2S_RX_MODE or I2S_TX_MODE + * @param DMANum : I2S DMA request number, should be + * - IP_I2S_DMA_REQUEST_NUMBER_1 + * - IP_I2S_DMA_REQUEST_NUMBER_2 + * @param depth : FIFO level on which to create an DMA request + * @return Nothing + * DMA request is generated when rx_depth_dma <= rx_level or tx_depth_dma >= tx_level + */ +void IP_I2S_SetFIFODepthDMA(IP_I2S_001_Type *pI2S, uint8_t TRMode, IP_I2S_DMARequestNumber_Type DMANum, uint32_t depth); + +/** + * @brief Enable/Disable DMA for the I2S + * @param pI2S : The base of I2S peripheral on the chip + * @param TRMode : Transmit/Receive mode, should be I2S_RX_MODE or I2S_TX_MODE + * @param DMANum : I2S DMA request number, should be + * - IP_I2S_DMA_REQUEST_NUMBER_1 + * - IP_I2S_DMA_REQUEST_NUMBER_2 + * @param NewState : ENABLE or DISABLE DMA + * @return Nothing + */ +void IP_I2S_DMACmd(IP_I2S_001_Type *pI2S, IP_I2S_DMARequestNumber_Type DMANum, uint8_t TRMode, FunctionalState NewState); + +/********************************************************************************** + * I2S IRQ functions + *********************************************************************************/ + +/** + * @brief Enable/Disable interrupt for the I2S + * @param pI2S : The base of I2S peripheral on the chip + * @param TRMode : Transmit/Receive mode, should be I2S_RX_MODE or I2S_TX_MODE + * @param NewState : ENABLE or DISABLE Interrupt + * @return Nothing + * Interrupt request is generated when rx_depth_irq <= rx_level or tx_depth_irq >= tx_level + */ +void IP_I2S_InterruptCmd(IP_I2S_001_Type *pI2S, uint8_t TRMode, FunctionalState NewState); + +/** + * @brief Set the FIFO level on which to create an irq request + * @param pI2S : The base of I2S peripheral on the chip + * @param TRMode : Transmit/Receive mode, should be I2S_RX_MODE or I2S_TX_MODE + * @param depth : FIFO level on which to create an irq request + * @return Nothing + */ +void IP_I2S_SetFIFODepthIRQ(IP_I2S_001_Type *pI2S, uint8_t TRMode, uint32_t depth); + +/** + * @brief Get the status of I2S interrupt + * @param pI2S : The base of I2S peripheral on the chip + * @param TRMode : Transmit/Receive mode, should be I2S_RX_MODE or I2S_TX_MODE + * @return I2S interrupt status, SET or RESET + */ +Status IP_I2S_GetIntStatus(IP_I2S_001_Type *pI2S, uint8_t TRMode); + +/** + * @} + */ + +#ifdef __cplusplus +} +#endif + +#endif /* __I2S_001_H_ */ diff --git a/bsp/xplorer4330/libraries/lpc_ip/lcd_001.c b/bsp/xplorer4330/libraries/lpc_ip/lcd_001.c new file mode 100644 index 0000000000..1c7701cb2a --- /dev/null +++ b/bsp/xplorer4330/libraries/lpc_ip/lcd_001.c @@ -0,0 +1,214 @@ +/* + * @brief LCD controller Registers and control functions + * + * @note + * Copyright(C) NXP Semiconductors, 2012 + * All rights reserved. + * + * @par + * Software that is described herein is for illustrative purposes only + * which provides customers with programming information regarding the + * LPC products. This software is supplied "AS IS" without any warranties of + * any kind, and NXP Semiconductors and its licensor disclaim any and + * all warranties, express or implied, including all implied warranties of + * merchantability, fitness for a particular purpose and non-infringement of + * intellectual property rights. NXP Semiconductors assumes no responsibility + * or liability for the use of the software, conveys no license or rights under any + * patent, copyright, mask work right, or any other intellectual property rights in + * or to any products. NXP Semiconductors reserves the right to make changes + * in the software without notification. NXP Semiconductors also makes no + * representation or warranty that such application will be suitable for the + * specified use without further testing or modification. + * + * @par + * Permission to use, copy, modify, and distribute this software and its + * documentation is hereby granted, under NXP Semiconductors' and its + * licensor's relevant copyrights in the software, without fee, provided that it + * is used in conjunction with NXP Semiconductors microcontrollers. This + * copyright, permission, and disclaimer notice must appear in all copies of + * this code. + */ + +#include "lcd_001.h" + +/***************************************************************************** + * Private types/enumerations/variables + ****************************************************************************/ + +/***************************************************************************** + * Public types/enumerations/variables + ****************************************************************************/ + +/***************************************************************************** + * Private functions + ****************************************************************************/ + +/***************************************************************************** + * Public functions + ****************************************************************************/ + +/* Initialize the LCD controller */ +void IP_LCD_Init(IP_LCD_001_Type *LCDx, LCD_Config_Type *LCD_ConfigStruct) +{ + uint32_t i, regValue, *pPal; + uint32_t pcd; + + /* disable the display */ + LCDx->CTRL &= ~CLCDC_LCDCTRL_ENABLE; + + /* Setting LCD_TIMH register */ + regValue = ( ((((LCD_ConfigStruct->PPL / 16) - 1) & 0x3F) << 2) + | (( (LCD_ConfigStruct->HSW - 1) & 0xFF) << 8) + | (( (LCD_ConfigStruct->HFP - 1) & 0xFF) << 16) + | (( (LCD_ConfigStruct->HBP - 1) & 0xFF) << 24) ); + LCDx->TIMH = regValue; + + /* Setting LCD_TIMV register */ + regValue = ((((LCD_ConfigStruct->LPP - 1) & 0x3FF) << 0) + | (((LCD_ConfigStruct->VSW - 1) & 0x03F) << 10) + | (((LCD_ConfigStruct->VFP - 1) & 0x0FF) << 16) + | (((LCD_ConfigStruct->VBP - 1) & 0x0FF) << 24) ); + LCDx->TIMV = regValue; + + /* Generate the clock and signal polarity control word */ + regValue = 0; + regValue = (((LCD_ConfigStruct->ACB - 1) & 0x1F) << 6); + regValue |= (LCD_ConfigStruct->IOE & 1) << 14; + regValue |= (LCD_ConfigStruct->IPC & 1) << 13; + regValue |= (LCD_ConfigStruct->IHS & 1) << 12; + regValue |= (LCD_ConfigStruct->IVS & 1) << 11; + + /* Compute clocks per line based on panel type */ + switch (LCD_ConfigStruct->LCD) { + case LCD_MONO_4: + regValue |= ((((LCD_ConfigStruct->PPL / 4) - 1) & 0x3FF) << 16); + break; + + case LCD_MONO_8: + regValue |= ((((LCD_ConfigStruct->PPL / 8) - 1) & 0x3FF) << 16); + break; + + case LCD_CSTN: + regValue |= (((((LCD_ConfigStruct->PPL * 3) / 8) - 1) & 0x3FF) << 16); + break; + + case LCD_TFT: + default: + regValue |= /*1<<26 |*/ (((LCD_ConfigStruct->PPL - 1) & 0x3FF) << 16); + } + + /* panel clock divisor */ + pcd = 5;// LCD_ConfigStruct->pcd; // TODO: should be calculated from LCDDCLK + pcd &= 0x3FF; + regValue |= ((pcd >> 5) << 27) | ((pcd) & 0x1F); + LCDx->POL = regValue; + + /* disable interrupts */ + LCDx->INTMSK = 0; + + /* set bits per pixel */ + regValue = LCD_ConfigStruct->BPP << 1; + + /* set color format RGB */ + regValue |= LCD_ConfigStruct->color_format << 8; + regValue |= LCD_ConfigStruct->LCD << 4; + if (LCD_ConfigStruct->Dual == 1) { + regValue |= 1 << 7; + } + LCDx->CTRL = regValue; + + /* clear palette */ + pPal = (uint32_t *) (&(LCDx->PAL)); + for (i = 0; i < 128; i++) { + *pPal = 0; + pPal++; + } +} + +/* Power the LCD Panel (power pin) */ +void IP_LCD_Power(IP_LCD_001_Type *LCDx, FunctionalState OnOff) { + volatile int i; + if (OnOff) { + LCDx->CTRL |= CLCDC_LCDCTRL_PWR; + for (i = 0; i < 1000000; i++) {} + LCDx->CTRL |= CLCDC_LCDCTRL_ENABLE; + } + else { + LCDx->CTRL &= ~CLCDC_LCDCTRL_PWR; + for (i = 0; i < 1000000; i++) {} + LCDx->CTRL &= ~CLCDC_LCDCTRL_ENABLE; + } +} + +/* Enable/Disable the LCD Controller */ +void IP_LCD_Enable(IP_LCD_001_Type *LCDx, FunctionalState EnDis) { + if (EnDis) { + LCDx->CTRL |= CLCDC_LCDCTRL_ENABLE; + } + else { + LCDx->CTRL &= ~CLCDC_LCDCTRL_ENABLE; + } +} + +/* Set LCD Upper Panel Frame Buffer for Single Panel or Upper Panel Frame Buffer for Dual Panel */ +void IP_LCD_SetUPFrameBuffer(IP_LCD_001_Type *LCDx, void *buffer) { + LCDx->UPBASE = (uint32_t) buffer; +} + +/* Set LCD Lower Panel Frame Buffer for Dual Panel */ +void IP_LCD_SetLPFrameBuffer(IP_LCD_001_Type *LCDx, void *buffer) { + LCDx->LPBASE = (uint32_t) buffer; +} + +/* Configure Cursor */ +void IP_LCD_Cursor_Config(IP_LCD_001_Type *LCDx, LCD_CURSOR_SIZE_OPT cursor_size, bool sync) { + LCDx->CRSR_CFG = ((sync ? 1 : 0) << 1) | cursor_size; +} + +/* Get Internal Cursor Image Buffer Address */ +void *IP_LCD_Cursor_GetImageBufferAddress(IP_LCD_001_Type *LCDx, uint8_t cursor_num) { + return (void *) &(LCDx->CRSR_IMG[cursor_num * 64]); +} + +/* Enable Cursor */ +void IP_LCD_Cursor_Enable(IP_LCD_001_Type *LCDx, uint8_t cursor_num, FunctionalState OnOff) { + if (OnOff) { + LCDx->CRSR_CTRL = (cursor_num << 4) | 1; + } + else { + LCDx->CRSR_CTRL = (cursor_num << 4); + } +} + +/* Load Cursor Palette 0 */ +void IP_LCD_Cursor_LoadPalette0(IP_LCD_001_Type *LCDx, uint32_t palette_color) { + /* 7:0 - Red + 15:8 - Green + 23:16 - Blue + 31:24 - Not used*/ + LCDx->CRSR_PAL0 = (uint32_t) palette_color; +} + +/* Load Cursor Palette 1 */ +void IP_LCD_Cursor_LoadPalette1(IP_LCD_001_Type *LCDx, uint32_t palette_color) { + /* 7:0 - Red + 15:8 - Green + 23:16 - Blue + 31:24 - Not used*/ + LCDx->CRSR_PAL1 = (uint32_t) palette_color; +} + +/* Set Cursor Position */ +void IP_LCD_Cursor_SetPos(IP_LCD_001_Type *LCDx, uint16_t x, uint16_t y) { + LCDx->CRSR_XY = (x & 0x3FF) | ((y & 0x3FF) << 16); +} + +/* Set Cursor Clipping Position */ +void IP_LCD_Cursor_SetClip(IP_LCD_001_Type *LCDx, uint16_t x, uint16_t y) { + LCDx->CRSR_CLIP = (x & 0x3F) | ((y & 0x3F) << 8); +} + +/* Load Color Palette */ +void IP_LCD_Color_LoadPalette(IP_LCD_001_Type *LCDx, uint32_t *palette_addr, uint32_t index) { + LCDx->PAL[index] = *(uint32_t *) palette_addr; +} diff --git a/bsp/xplorer4330/libraries/lpc_ip/lcd_001.h b/bsp/xplorer4330/libraries/lpc_ip/lcd_001.h new file mode 100644 index 0000000000..457d6bb5e3 --- /dev/null +++ b/bsp/xplorer4330/libraries/lpc_ip/lcd_001.h @@ -0,0 +1,310 @@ +/* + * @brief LCD controller Registers and control functions + * + * @note + * Copyright(C) NXP Semiconductors, 2012 + * All rights reserved. + * + * @par + * Software that is described herein is for illustrative purposes only + * which provides customers with programming information regarding the + * LPC products. This software is supplied "AS IS" without any warranties of + * any kind, and NXP Semiconductors and its licensor disclaim any and + * all warranties, express or implied, including all implied warranties of + * merchantability, fitness for a particular purpose and non-infringement of + * intellectual property rights. NXP Semiconductors assumes no responsibility + * or liability for the use of the software, conveys no license or rights under any + * patent, copyright, mask work right, or any other intellectual property rights in + * or to any products. NXP Semiconductors reserves the right to make changes + * in the software without notification. NXP Semiconductors also makes no + * representation or warranty that such application will be suitable for the + * specified use without further testing or modification. + * + * @par + * Permission to use, copy, modify, and distribute this software and its + * documentation is hereby granted, under NXP Semiconductors' and its + * licensor's relevant copyrights in the software, without fee, provided that it + * is used in conjunction with NXP Semiconductors microcontrollers. This + * copyright, permission, and disclaimer notice must appear in all copies of + * this code. + */ + +#ifndef __LCD_001_H_ +#define __LCD_001_H_ + +#include "sys_config.h" +#include "cmsis.h" + +#ifdef __cplusplus +extern "C" { +#endif + +/** @defgroup IP_LCD_001 IP: LCD register block and driver + * @ingroup IP_Drivers + * @{ + */ + +/** + * @brief LCD Controller register block structure + */ +typedef struct { /*!< LCD Structure */ + __IO uint32_t TIMH; /*!< Horizontal Timing Control register */ + __IO uint32_t TIMV; /*!< Vertical Timing Control register */ + __IO uint32_t POL; /*!< Clock and Signal Polarity Control register */ + __IO uint32_t LE; /*!< Line End Control register */ + __IO uint32_t UPBASE; /*!< Upper Panel Frame Base Address register */ + __IO uint32_t LPBASE; /*!< Lower Panel Frame Base Address register */ + __IO uint32_t CTRL; /*!< LCD Control register */ + __IO uint32_t INTMSK; /*!< Interrupt Mask register */ + __I uint32_t INTRAW; /*!< Raw Interrupt Status register */ + __I uint32_t INTSTAT; /*!< Masked Interrupt Status register */ + __O uint32_t INTCLR; /*!< Interrupt Clear register */ + __I uint32_t UPCURR; /*!< Upper Panel Current Address Value register */ + __I uint32_t LPCURR; /*!< Lower Panel Current Address Value register */ + __I uint32_t RESERVED0[115]; + __IO uint16_t PAL[256]; /*!< 256x16-bit Color Palette registers */ + __I uint32_t RESERVED1[256]; + __IO uint32_t CRSR_IMG[256];/*!< Cursor Image registers */ + __IO uint32_t CRSR_CTRL; /*!< Cursor Control register */ + __IO uint32_t CRSR_CFG; /*!< Cursor Configuration register */ + __IO uint32_t CRSR_PAL0; /*!< Cursor Palette register 0 */ + __IO uint32_t CRSR_PAL1; /*!< Cursor Palette register 1 */ + __IO uint32_t CRSR_XY; /*!< Cursor XY Position register */ + __IO uint32_t CRSR_CLIP; /*!< Cursor Clip Position register */ + __I uint32_t RESERVED2[2]; + __IO uint32_t CRSR_INTMSK; /*!< Cursor Interrupt Mask register */ + __O uint32_t CRSR_INTCLR; /*!< Cursor Interrupt Clear register */ + __I uint32_t CRSR_INTRAW; /*!< Cursor Raw Interrupt Status register */ + __I uint32_t CRSR_INTSTAT;/*!< Cursor Masked Interrupt Status register */ +} IP_LCD_001_Type; + +/** + * @brief LCD Palette entry format + */ +typedef struct { + uint32_t Rl : 5; + uint32_t Gl : 5; + uint32_t Bl : 5; + uint32_t Il : 1; + uint32_t Ru : 5; + uint32_t Gu : 5; + uint32_t Bu : 5; + uint32_t Iu : 1; +} LCD_PALETTE_ENTRY_Type; + +/** + * @brief LCD Panel type + */ +typedef enum { + LCD_TFT = 0x02, /*!< standard TFT */ + LCD_MONO_4 = 0x01, /*!< 4-bit STN mono */ + LCD_MONO_8 = 0x05, /*!< 8-bit STN mono */ + LCD_CSTN = 0x00 /*!< color STN */ +} LCD_PANEL_OPT; + +/** + * @brief LCD Color Format + */ +typedef enum { + LCD_COLOR_FORMAT_RGB = 0, + LCD_COLOR_FORMAT_BGR +} LCD_COLOR_FORMAT_OPT; + +/** LCD Interrupt control mask register bits */ +#define LCD_INTMSK_FUFIM 0x2 /*!< FIFO underflow interrupt enable */ +#define LCD_INTMSK_LNBUIM 0x4 /*!< LCD next base address update interrupt enable */ +#define LCD_INTMSK_VCOMPIM 0x8 /*!< Vertical compare interrupt enable */ +#define LCD_INTMSK_BERIM 0x10 /*!< AHB master error interrupt enable */ + +#define CLCDC_LCDCTRL_ENABLE _BIT(0) /*!< LCD control enable bit */ +#define CLCDC_LCDCTRL_PWR _BIT(11) /*!< LCD control power enable bit */ + +/** + * @brief A structure for LCD Configuration + */ +typedef struct { + uint8_t HBP; /*!< Horizontal back porch in clocks */ + uint8_t HFP; /*!< Horizontal front porch in clocks */ + uint8_t HSW; /*!< HSYNC pulse width in clocks */ + uint16_t PPL; /*!< Pixels per line */ + uint8_t VBP; /*!< Vertical back porch in clocks */ + uint8_t VFP; /*!< Vertical front porch in clocks */ + uint8_t VSW; /*!< VSYNC pulse width in clocks */ + uint16_t LPP; /*!< Lines per panel */ + uint8_t IOE; /*!< Invert output enable, 1 = invert */ + uint8_t IPC; /*!< Invert panel clock, 1 = invert */ + uint8_t IHS; /*!< Invert HSYNC, 1 = invert */ + uint8_t IVS; /*!< Invert VSYNC, 1 = invert */ + uint8_t ACB; /*!< AC bias frequency in clocks (not used) */ + uint8_t BPP; /*!< Maximum bits per pixel the display supports */ + LCD_PANEL_OPT LCD; /*!< LCD panel type */ + LCD_COLOR_FORMAT_OPT color_format; /*!INTMSK = ints; +} + +/** + * @brief Disable Controller Interrupt + * @param LCDx : pointer to LCD Controller Reg Struct + * @param ints : OR'ed interrupt bits to disable + * @return None + */ +STATIC INLINE void IP_LCD_DisableInts(IP_LCD_001_Type *LCDx, uint32_t ints) +{ + LCDx->INTMSK = LCDx->INTMSK & ~(ints); +} + +/** + * @brief Clear Controller Interrupt + * @param LCDx : pointer to LCD Controller Reg Struct + * @param ints : OR'ed interrupt bits to clear + * @return None + */ +STATIC INLINE void IP_LCD_ClearInts(IP_LCD_001_Type *LCDx, uint32_t ints) +{ + LCDx->INTCLR = LCDx->INTMSK & (ints); +} + +/** + * @brief Initialize the LCD controller + * @param LCDx : pointer to LCD Controller Reg Struct + * @param LCD_ConfigStruct : Pointer to LCD configuration + * @return LCD_FUNC_OK is executed successfully or LCD_FUNC_ERR on error + */ +void IP_LCD_Init(IP_LCD_001_Type *LCDx, LCD_Config_Type *LCD_ConfigStruct); + +/** + * @brief Power the LCD Panel (power pin) + * @param LCDx : pointer to LCD Controller Reg Struct + * @param OnOff : true to power on, false to power off + * @return None + */ +void IP_LCD_Power(IP_LCD_001_Type *LCDx, FunctionalState OnOff); + +/** + * @brief Enable/Disable the LCD Controller + * @param LCDx : pointer to LCD Controller Reg Struct + * @param EnDis : true to enable, false to disable + * @return None + */ +void IP_LCD_Enable(IP_LCD_001_Type *LCDx, FunctionalState EnDis); + +/** + * @brief Set LCD Upper Panel Frame Buffer for Single Panel or Upper Panel Frame + * Buffer for Dual Panel + * @param LCDx : pointer to LCD Controller Reg Struct + * @param buffer : address of buffer + * @return None + */ +void IP_LCD_SetUPFrameBuffer(IP_LCD_001_Type *LCDx, void *buffer); + +/** + * @brief Set LCD Lower Panel Frame Buffer for Dual Panel + * @param LCDx : pointer to LCD Controller Reg Struct + * @param buffer : address of buffer + * @return None + */ +void IP_LCD_SetLPFrameBuffer(IP_LCD_001_Type *LCDx, void *buffer); + +/** + * @brief Configure Cursor + * @param LCDx : pointer to LCD Controller Reg Struct + * @param cursor_size : specify size of cursor + * - LCD_CURSOR_32x32 :cursor size is 32x32 pixels + * - LCD_CURSOR_64x64 :cursor size is 64x64 pixels + * @param sync : cursor sync mode + * - TRUE :cursor sync to the frame sync pulse + * - FALSE :cursor async mode + * @return None + */ +void IP_LCD_Cursor_Config(IP_LCD_001_Type *LCDx, LCD_CURSOR_SIZE_OPT cursor_size, bool sync); + +/** + * @brief Get Internal Cursor Image Buffer Address + * @param LCDx : pointer to LCD Controller Reg Struct + * @param cursor_num : specify number of cursor is going to be written + * this param must < 4 + * @return Cursor Image Buffer Address + */ +void *IP_LCD_Cursor_GetImageBufferAddress(IP_LCD_001_Type *LCDx, uint8_t cursor_num); + +/** + * @brief Enable Cursor + * @param LCDx : pointer to LCD Controller Reg Struct + * @param cursor_num : specify number of cursor is going to be written + * this param must < 4 + * @param OnOff : true to turn on LCD, false to turn off + * @return None + */ +void IP_LCD_Cursor_Enable(IP_LCD_001_Type *LCDx, uint8_t cursor_num, FunctionalState OnOff); + +/** + * @brief Load Cursor Palette + * @param LCDx : pointer to LCD Controller Reg Struct + * @param palette_color : cursor palette 0 value + * @return None + */ +void IP_LCD_Cursor_LoadPalette0(IP_LCD_001_Type *LCDx, uint32_t palette_color); + +/** + * @brief Load Cursor Palette + * @param LCDx : pointer to LCD Controller Reg Struct + * @param palette_color : cursor palette 1 value + * @return None + */ +void IP_LCD_Cursor_LoadPalette1(IP_LCD_001_Type *LCDx, uint32_t palette_color); + +/** + * @brief Set Cursor Position + * @param LCDx : pointer to LCD Controller Reg Struct + * @param x : horizontal position + * @param y : vertical position + * @return None + */ +void IP_LCD_Cursor_SetPos(IP_LCD_001_Type *LCDx, uint16_t x, uint16_t y); + +/** + * @brief Set Cursor Clipping Position + * @param LCDx : pointer to LCD Controller Reg Struct + * @param x : horizontal position, should be in range: 0..63 + * @param y : vertical position, should be in range: 0..63 + * @return None + */ +void IP_LCD_Cursor_SetClip(IP_LCD_001_Type *LCDx, uint16_t x, uint16_t y); + +/** + * @brief Load a color Palette entry + * @param LCDx : pointer to LCD Controller Reg Struct + * @param palette_addr : Address of palette table to load from + * @param index : palette entry index to load + * @return None + */ +void IP_LCD_Color_LoadPalette(IP_LCD_001_Type *LCDx, uint32_t *palette_addr, uint32_t index); + +/** + * @} + */ + +#ifdef __cplusplus +} +#endif + +#endif /* __LCD_001_H_ */ diff --git a/bsp/xplorer4330/libraries/lpc_ip/lpc_types.h b/bsp/xplorer4330/libraries/lpc_ip/lpc_types.h new file mode 100644 index 0000000000..cedd6f2902 --- /dev/null +++ b/bsp/xplorer4330/libraries/lpc_ip/lpc_types.h @@ -0,0 +1,216 @@ +/* + * @brief Common types used in LPC functions + * + * @note + * Copyright(C) NXP Semiconductors, 2012 + * All rights reserved. + * + * @par + * Software that is described herein is for illustrative purposes only + * which provides customers with programming information regarding the + * LPC products. This software is supplied "AS IS" without any warranties of + * any kind, and NXP Semiconductors and its licensor disclaim any and + * all warranties, express or implied, including all implied warranties of + * merchantability, fitness for a particular purpose and non-infringement of + * intellectual property rights. NXP Semiconductors assumes no responsibility + * or liability for the use of the software, conveys no license or rights under any + * patent, copyright, mask work right, or any other intellectual property rights in + * or to any products. NXP Semiconductors reserves the right to make changes + * in the software without notification. NXP Semiconductors also makes no + * representation or warranty that such application will be suitable for the + * specified use without further testing or modification. + * + * @par + * Permission to use, copy, modify, and distribute this software and its + * documentation is hereby granted, under NXP Semiconductors' and its + * licensor's relevant copyrights in the software, without fee, provided that it + * is used in conjunction with NXP Semiconductors microcontrollers. This + * copyright, permission, and disclaimer notice must appear in all copies of + * this code. + */ + +#ifndef __LPC_TYPES_H_ +#define __LPC_TYPES_H_ + +#include +#include + +/** @defgroup LPC_Types IP: LPC Common Types + * @ingroup IP_Drivers + * @{ + */ + +/** @defgroup LPC_Types_Public_Types LPC Public Types + * @{ + */ + +/** + * @brief Boolean Type definition + */ +typedef enum {FALSE = 0, TRUE = !FALSE} Bool; + +/** + * @brief Boolean Type definition + */ +#if !defined(__cplusplus) +// typedef enum {false = 0, true = !false} bool; +#endif + +/** + * @brief Flag Status and Interrupt Flag Status type definition + */ +typedef enum {RESET = 0, SET = !RESET} FlagStatus, IntStatus, SetState; +#define PARAM_SETSTATE(State) ((State == RESET) || (State == SET)) + +/** + * @brief Functional State Definition + */ +typedef enum {DISABLE = 0, ENABLE = !DISABLE} FunctionalState; +#define PARAM_FUNCTIONALSTATE(State) ((State == DISABLE) || (State == ENABLE)) + +/** + * @ Status type definition + */ +typedef enum {ERROR = 0, SUCCESS = !ERROR} Status; + +/** + * Read/Write transfer type mode (Block or non-block) + */ +typedef enum { + NONE_BLOCKING = 0, /**< None Blocking type */ + BLOCKING, /**< Blocking type */ +} TRANSFER_BLOCK_Type; + +/** Pointer to Function returning Void (any number of parameters) */ +typedef void (*PFV)(); + +/** Pointer to Function returning int32_t (any number of parameters) */ +typedef int32_t (*PFI)(); + +/** + * @} + */ + +/** @defgroup LPC_Types_Public_Macros LPC Public Macros + * @{ + */ + +/* _BIT(n) sets the bit at position "n" + * _BIT(n) is intended to be used in "OR" and "AND" expressions: + * e.g., "(_BIT(3) | _BIT(7))". + */ +#undef _BIT +/* Set bit macro */ +#define _BIT(n) (1 << (n)) + +/* _SBF(f,v) sets the bit field starting at position "f" to value "v". + * _SBF(f,v) is intended to be used in "OR" and "AND" expressions: + * e.g., "((_SBF(5,7) | _SBF(12,0xF)) & 0xFFFF)" + */ +#undef _SBF +/* Set bit field macro */ +#define _SBF(f, v) ((v) << (f)) + +/* _BITMASK constructs a symbol with 'field_width' least significant + * bits set. + * e.g., _BITMASK(5) constructs '0x1F', _BITMASK(16) == 0xFFFF + * The symbol is intended to be used to limit the bit field width + * thusly: + * = (any_expression) & _BITMASK(x), where 0 < x <= 32. + * If "any_expression" results in a value that is larger than can be + * contained in 'x' bits, the bits above 'x - 1' are masked off. When + * used with the _SBF example above, the example would be written: + * a_reg = ((_SBF(5,7) | _SBF(12,0xF)) & _BITMASK(16)) + * This ensures that the value written to a_reg is no wider than + * 16 bits, and makes the code easier to read and understand. + */ +#undef _BITMASK +/* Bitmask creation macro */ +#define _BITMASK(field_width) ( _BIT(field_width) - 1) + +/* NULL pointer */ +#ifndef NULL +#define NULL ((void *) 0) +#endif + +/* Number of elements in an array */ +#define NELEMENTS(array) (sizeof(array) / sizeof(array[0])) + +/* Static data/function define */ +#define STATIC static +/* External data/function define */ +#define EXTERN extern + +#if !defined(MAX) +#define MAX(a, b) (((a) > (b)) ? (a) : (b)) +#endif +#if !defined(MIN) +#define MIN(a, b) (((a) < (b)) ? (a) : (b)) +#endif + +/** + * @} + */ + +/* Old Type Definition compatibility */ +/** @addtogroup LPC_Types_Public_Types + * @{ + */ + +/** LPC type for character type */ +typedef char CHAR; + +/** LPC type for 8 bit unsigned value */ +typedef uint8_t UNS_8; + +/** LPC type for 8 bit signed value */ +typedef int8_t INT_8; + +/** LPC type for 16 bit unsigned value */ +typedef uint16_t UNS_16; + +/** LPC type for 16 bit signed value */ +typedef int16_t INT_16; + +/** LPC type for 32 bit unsigned value */ +typedef uint32_t UNS_32; + +/** LPC type for 32 bit signed value */ +typedef int32_t INT_32; + +/** LPC type for 64 bit signed value */ +typedef int64_t INT_64; + +/** LPC type for 64 bit unsigned value */ +typedef uint64_t UNS_64; + +#ifdef __CODE_RED +#define BOOL_32 bool +#define BOOL_16 bool +#define BOOL_8 bool +#else +/** 32 bit boolean type */ +typedef bool BOOL_32; + +/** 16 bit boolean type */ +typedef bool BOOL_16; + +/** 8 bit boolean type */ +typedef bool BOOL_8; +#endif + +#ifdef __CC_ARM +#define INLINE __inline +#else +#define INLINE inline +#endif + +/** + * @} + */ + +/** + * @} + */ + +#endif /* __LPC_TYPES_H_ */ diff --git a/bsp/xplorer4330/libraries/lpc_ip/mcpwm_001.h b/bsp/xplorer4330/libraries/lpc_ip/mcpwm_001.h new file mode 100644 index 0000000000..22c3eea0f3 --- /dev/null +++ b/bsp/xplorer4330/libraries/lpc_ip/mcpwm_001.h @@ -0,0 +1,84 @@ +/* + * @brief Motor Control PWM registers and control functions + * + * @note + * Copyright(C) NXP Semiconductors, 2012 + * All rights reserved. + * + * @par + * Software that is described herein is for illustrative purposes only + * which provides customers with programming information regarding the + * LPC products. This software is supplied "AS IS" without any warranties of + * any kind, and NXP Semiconductors and its licensor disclaim any and + * all warranties, express or implied, including all implied warranties of + * merchantability, fitness for a particular purpose and non-infringement of + * intellectual property rights. NXP Semiconductors assumes no responsibility + * or liability for the use of the software, conveys no license or rights under any + * patent, copyright, mask work right, or any other intellectual property rights in + * or to any products. NXP Semiconductors reserves the right to make changes + * in the software without notification. NXP Semiconductors also makes no + * representation or warranty that such application will be suitable for the + * specified use without further testing or modification. + * + * @par + * Permission to use, copy, modify, and distribute this software and its + * documentation is hereby granted, under NXP Semiconductors' and its + * licensor's relevant copyrights in the software, without fee, provided that it + * is used in conjunction with NXP Semiconductors microcontrollers. This + * copyright, permission, and disclaimer notice must appear in all copies of + * this code. + */ + +#ifndef __MCPWM_001_H_ +#define __MCPWM_001_H_ + +#include "sys_config.h" +#include "cmsis.h" + +#ifdef __cplusplus +extern "C" { +#endif + +/** @defgroup IP_MCPWM_001 IP: MCPWM register block and driver + * @ingroup IP_Drivers + * Motor Control PWM + * @{ + */ + +/** + * @brief Motor Control PWM register block structure + */ +typedef struct { /*!< MCPWM Structure */ + __I uint32_t CON; /*!< PWM Control read address */ + __O uint32_t CON_SET; /*!< PWM Control set address */ + __O uint32_t CON_CLR; /*!< PWM Control clear address */ + __I uint32_t CAPCON; /*!< Capture Control read address */ + __O uint32_t CAPCON_SET; /*!< Capture Control set address */ + __O uint32_t CAPCON_CLR; /*!< Event Control clear address */ + __IO uint32_t TC[3]; /*!< Timer Counter register */ + __IO uint32_t LIM[3]; /*!< Limit register */ + __IO uint32_t MAT[3]; /*!< Match register */ + __IO uint32_t DT; /*!< Dead time register */ + __IO uint32_t CCP; /*!< Communication Pattern register */ + __I uint32_t CAP[3]; /*!< Capture register */ + __I uint32_t INTEN; /*!< Interrupt Enable read address */ + __O uint32_t INTEN_SET; /*!< Interrupt Enable set address */ + __O uint32_t INTEN_CLR; /*!< Interrupt Enable clear address */ + __I uint32_t CNTCON; /*!< Count Control read address */ + __O uint32_t CNTCON_SET; /*!< Count Control set address */ + __O uint32_t CNTCON_CLR; /*!< Count Control clear address */ + __I uint32_t INTF; /*!< Interrupt flags read address */ + __O uint32_t INTF_SET; /*!< Interrupt flags set address */ + __O uint32_t INTF_CLR; /*!< Interrupt flags clear address */ + __O uint32_t CAP_CLR; /*!< Capture clear address */ +} IP_MCPWM_001_Type; + +/** + * @} + */ + +#ifdef __cplusplus +} +#endif + +#endif /* __MCPWM_001_H_ */ diff --git a/bsp/xplorer4330/libraries/lpc_ip/pmc_001.h b/bsp/xplorer4330/libraries/lpc_ip/pmc_001.h new file mode 100644 index 0000000000..08dcaf84bf --- /dev/null +++ b/bsp/xplorer4330/libraries/lpc_ip/pmc_001.h @@ -0,0 +1,65 @@ +/* + * @brief Power Management Controller registers and control functions + * + * @note + * Copyright(C) NXP Semiconductors, 2012 + * All rights reserved. + * + * @par + * Software that is described herein is for illustrative purposes only + * which provides customers with programming information regarding the + * LPC products. This software is supplied "AS IS" without any warranties of + * any kind, and NXP Semiconductors and its licensor disclaim any and + * all warranties, express or implied, including all implied warranties of + * merchantability, fitness for a particular purpose and non-infringement of + * intellectual property rights. NXP Semiconductors assumes no responsibility + * or liability for the use of the software, conveys no license or rights under any + * patent, copyright, mask work right, or any other intellectual property rights in + * or to any products. NXP Semiconductors reserves the right to make changes + * in the software without notification. NXP Semiconductors also makes no + * representation or warranty that such application will be suitable for the + * specified use without further testing or modification. + * + * @par + * Permission to use, copy, modify, and distribute this software and its + * documentation is hereby granted, under NXP Semiconductors' and its + * licensor's relevant copyrights in the software, without fee, provided that it + * is used in conjunction with NXP Semiconductors microcontrollers. This + * copyright, permission, and disclaimer notice must appear in all copies of + * this code. + */ + +#ifndef __PMC_001_H_ +#define __PMC_001_H_ + +#include "sys_config.h" +#include "cmsis.h" + +#ifdef __cplusplus +extern "C" { +#endif + +/** @defgroup IP_PMC_001 IP: PMC register block and driver + * @ingroup IP_Drivers + * Power Management Controller + * @{ + */ + +/** + * @brief Power Management Controller register block structure + */ +typedef struct { /*!< PMC Structure */ + __IO uint32_t PD0_SLEEP0_HW_ENA; /*!< Hardware sleep event enable register */ + __I uint32_t RESERVED0[6]; + __IO uint32_t PD0_SLEEP0_MODE; /*!< Sleep power mode register */ +} IP_PMC_001_Type; + +/** + * @} + */ + +#ifdef __cplusplus +} +#endif + +#endif /* __PMC_001_H_ */ diff --git a/bsp/xplorer4330/libraries/lpc_ip/qei_001.h b/bsp/xplorer4330/libraries/lpc_ip/qei_001.h new file mode 100644 index 0000000000..2bf0be7690 --- /dev/null +++ b/bsp/xplorer4330/libraries/lpc_ip/qei_001.h @@ -0,0 +1,90 @@ +/* + * @brief Quadrature Encoder Interface Registers and control functions + * + * @note + * Copyright(C) NXP Semiconductors, 2012 + * All rights reserved. + * + * @par + * Software that is described herein is for illustrative purposes only + * which provides customers with programming information regarding the + * LPC products. This software is supplied "AS IS" without any warranties of + * any kind, and NXP Semiconductors and its licensor disclaim any and + * all warranties, express or implied, including all implied warranties of + * merchantability, fitness for a particular purpose and non-infringement of + * intellectual property rights. NXP Semiconductors assumes no responsibility + * or liability for the use of the software, conveys no license or rights under any + * patent, copyright, mask work right, or any other intellectual property rights in + * or to any products. NXP Semiconductors reserves the right to make changes + * in the software without notification. NXP Semiconductors also makes no + * representation or warranty that such application will be suitable for the + * specified use without further testing or modification. + * + * @par + * Permission to use, copy, modify, and distribute this software and its + * documentation is hereby granted, under NXP Semiconductors' and its + * licensor's relevant copyrights in the software, without fee, provided that it + * is used in conjunction with NXP Semiconductors microcontrollers. This + * copyright, permission, and disclaimer notice must appear in all copies of + * this code. + */ + +#ifndef __QEI_001_H_ +#define __QEI_001_H_ + +#include "sys_config.h" +#include "cmsis.h" + +#ifdef __cplusplus +extern "C" { +#endif + +/** @defgroup IP_QEI_001 IP: QEI register block and driver + * @ingroup IP_Drivers + * Quadrature Encoder Interface + * @{ + */ + +/** + * @brief Quadrature Encoder Interface register block structure + */ +typedef struct { /*!< QEI Structure */ + __O uint32_t CON; /*!< Control register */ + __I uint32_t STAT; /*!< Encoder status register */ + __IO uint32_t CONF; /*!< Configuration register */ + __I uint32_t POS; /*!< Position register */ + __IO uint32_t MAXPOS; /*!< Maximum position register */ + __IO uint32_t CMPOS0; /*!< position compare register 0 */ + __IO uint32_t CMPOS1; /*!< position compare register 1 */ + __IO uint32_t CMPOS2; /*!< position compare register 2 */ + __I uint32_t INXCNT; /*!< Index count register */ + __IO uint32_t INXCMP0; /*!< Index compare register 0 */ + __IO uint32_t LOAD; /*!< Velocity timer reload register */ + __I uint32_t TIME; /*!< Velocity timer register */ + __I uint32_t VEL; /*!< Velocity counter register */ + __I uint32_t CAP; /*!< Velocity capture register */ + __IO uint32_t VELCOMP; /*!< Velocity compare register */ + __IO uint32_t FILTERPHA; /*!< Digital filter register on input phase A (QEI_A) */ + __IO uint32_t FILTERPHB; /*!< Digital filter register on input phase B (QEI_B) */ + __IO uint32_t FILTERINX; /*!< Digital filter register on input index (QEI_IDX) */ + __IO uint32_t WINDOW; /*!< Index acceptance window register */ + __IO uint32_t INXCMP1; /*!< Index compare register 1 */ + __IO uint32_t INXCMP2; /*!< Index compare register 2 */ + __I uint32_t RESERVED0[993]; + __O uint32_t IEC; /*!< Interrupt enable clear register */ + __O uint32_t IES; /*!< Interrupt enable set register */ + __I uint32_t INTSTAT; /*!< Interrupt status register */ + __I uint32_t IE; /*!< Interrupt enable register */ + __O uint32_t CLR; /*!< Interrupt status clear register */ + __O uint32_t SET; /*!< Interrupt status set register */ +} IP_QEI_001_Type; + +/** + * @} + */ + +#ifdef __cplusplus +} +#endif + +#endif /* __QEI_001_H_ */ diff --git a/bsp/xplorer4330/libraries/lpc_ip/regfile_001.h b/bsp/xplorer4330/libraries/lpc_ip/regfile_001.h new file mode 100644 index 0000000000..b9b2bfcbc4 --- /dev/null +++ b/bsp/xplorer4330/libraries/lpc_ip/regfile_001.h @@ -0,0 +1,94 @@ +/* + * @brief Register File registers and control functions + * + * @note + * Copyright(C) NXP Semiconductors, 2012 + * All rights reserved. + * + * @par + * Software that is described herein is for illustrative purposes only + * which provides customers with programming information regarding the + * LPC products. This software is supplied "AS IS" without any warranties of + * any kind, and NXP Semiconductors and its licensor disclaim any and + * all warranties, express or implied, including all implied warranties of + * merchantability, fitness for a particular purpose and non-infringement of + * intellectual property rights. NXP Semiconductors assumes no responsibility + * or liability for the use of the software, conveys no license or rights under any + * patent, copyright, mask work right, or any other intellectual property rights in + * or to any products. NXP Semiconductors reserves the right to make changes + * in the software without notification. NXP Semiconductors also makes no + * representation or warranty that such application will be suitable for the + * specified use without further testing or modification. + * + * @par + * Permission to use, copy, modify, and distribute this software and its + * documentation is hereby granted, under NXP Semiconductors' and its + * licensor's relevant copyrights in the software, without fee, provided that it + * is used in conjunction with NXP Semiconductors microcontrollers. This + * copyright, permission, and disclaimer notice must appear in all copies of + * this code. + */ + +#ifndef __REGFILE_001_H_ +#define __REGFILE_001_H_ + +#include "sys_config.h" +#include "cmsis.h" + +#ifdef __cplusplus +extern "C" { +#endif + +/** @defgroup IP_REGFILE_001 IP: REGFILE register block and driver + * @ingroup IP_Drivers + * Register File + * @{ + */ + +/** + * @brief Register File register block structure + */ +typedef struct { + __IO uint32_t REGFILE[64]; /*!< General purpose storage register */ +} IP_REGFILE_001_T; + +/** + * @brief Write value to General purpose registers + * @param pREG : Pointer to regfile block + * @param index : General purpose register index + * @param value : Value to write + * @return None + * Note: These General purpose registers can be used to store important + * information when the main power supply is off. The value in these + * registers is not affected by chip reset. These registers are usually + * powered in the RTC power domain. + */ +STATIC INLINE void IP_REGFILE_Write(IP_REGFILE_001_T *pREG, int index, uint32_t value) +{ + pREG->REGFILE[index] = value; +} + +/** + * @brief Read value from General purpose registers + * @param pREG : Pointer to regfile block + * @param index : General purpose register index + * @return Read value + * These General purpose registers can be used to store important + * information when the main power supply is off. The value in these + * registers is not affected by chip reset. These registers are usually + * powered in the RTC power domain. + */ +STATIC INLINE uint32_t IP_REGFILE_Read(IP_REGFILE_001_T *pREG, int index) +{ + return pREG->REGFILE[index]; +} + +/** + * @} + */ + +#ifdef __cplusplus +} +#endif + +#endif /* __REGFILE_001_H_ */ diff --git a/bsp/xplorer4330/libraries/lpc_ip/ritimer_001.c b/bsp/xplorer4330/libraries/lpc_ip/ritimer_001.c new file mode 100644 index 0000000000..08363364d4 --- /dev/null +++ b/bsp/xplorer4330/libraries/lpc_ip/ritimer_001.c @@ -0,0 +1,100 @@ +/* + * @brief Repetitive Interrupt Timer registers and control functions + * + * @note + * Copyright(C) NXP Semiconductors, 2012 + * All rights reserved. + * + * @par + * Software that is described herein is for illustrative purposes only + * which provides customers with programming information regarding the + * LPC products. This software is supplied "AS IS" without any warranties of + * any kind, and NXP Semiconductors and its licensor disclaim any and + * all warranties, express or implied, including all implied warranties of + * merchantability, fitness for a particular purpose and non-infringement of + * intellectual property rights. NXP Semiconductors assumes no responsibility + * or liability for the use of the software, conveys no license or rights under any + * patent, copyright, mask work right, or any other intellectual property rights in + * or to any products. NXP Semiconductors reserves the right to make changes + * in the software without notification. NXP Semiconductors also makes no + * representation or warranty that such application will be suitable for the + * specified use without further testing or modification. + * + * @par + * Permission to use, copy, modify, and distribute this software and its + * documentation is hereby granted, under NXP Semiconductors' and its + * licensor's relevant copyrights in the software, without fee, provided that it + * is used in conjunction with NXP Semiconductors microcontrollers. This + * copyright, permission, and disclaimer notice must appear in all copies of + * this code. + */ + +#include "ritimer_001.h" + +/***************************************************************************** + * Private types/enumerations/variables + ****************************************************************************/ + +/***************************************************************************** + * Public types/enumerations/variables + ****************************************************************************/ + +/***************************************************************************** + * Private functions + ****************************************************************************/ + +/***************************************************************************** + * Public functions + ****************************************************************************/ + +/* Initialize the RIT */ +void IP_RIT_Init(IP_RITIMER_001_Type *RITx) +{ + RITx->COMPVAL = 0xFFFFFFFF; + RITx->MASK = 0x00000000; + RITx->CTRL = 0x0C; + RITx->COUNTER = 0x00000000; +} + +/* DeInitialize the RIT */ +void IP_RIT_DeInit(IP_RITIMER_001_Type *RITx) +{ + IP_RIT_Init(RITx); +} + +/* Enable/Disable Timer */ +void IP_RIT_Enable(IP_RITIMER_001_Type *RITx, FunctionalState NewState) +{ + if (NewState == ENABLE) { + RITx->CTRL |= RIT_CTRL_TEN; + } + else { + RITx->CTRL &= ~RIT_CTRL_TEN; + } +} + +/* Enable or disable timer debug */ +void IP_RIT_TimerDebugCmd(IP_RITIMER_001_Type *RITx, FunctionalState NewState) +{ + if (NewState == ENABLE) { + RITx->CTRL |= RIT_CTRL_ENBR; + } + else { + RITx->CTRL &= ~RIT_CTRL_ENBR; + } +} + +/* Check whether interrupt is pending */ +IntStatus IP_RIT_GetIntStatus(IP_RITIMER_001_Type *RITx) +{ + uint8_t result; + + if ((RITx->CTRL & RIT_CTRL_INT) == 1) { + result = SET; + } + else { + return RESET; + } + + return (IntStatus) result; +} diff --git a/bsp/xplorer4330/libraries/lpc_ip/ritimer_001.h b/bsp/xplorer4330/libraries/lpc_ip/ritimer_001.h new file mode 100644 index 0000000000..d6c249fe82 --- /dev/null +++ b/bsp/xplorer4330/libraries/lpc_ip/ritimer_001.h @@ -0,0 +1,151 @@ +/* + * @brief Repetitive Interrupt Timer registers and control functions + * + * @note + * Copyright(C) NXP Semiconductors, 2012 + * All rights reserved. + * + * @par + * Software that is described herein is for illustrative purposes only + * which provides customers with programming information regarding the + * LPC products. This software is supplied "AS IS" without any warranties of + * any kind, and NXP Semiconductors and its licensor disclaim any and + * all warranties, express or implied, including all implied warranties of + * merchantability, fitness for a particular purpose and non-infringement of + * intellectual property rights. NXP Semiconductors assumes no responsibility + * or liability for the use of the software, conveys no license or rights under any + * patent, copyright, mask work right, or any other intellectual property rights in + * or to any products. NXP Semiconductors reserves the right to make changes + * in the software without notification. NXP Semiconductors also makes no + * representation or warranty that such application will be suitable for the + * specified use without further testing or modification. + * + * @par + * Permission to use, copy, modify, and distribute this software and its + * documentation is hereby granted, under NXP Semiconductors' and its + * licensor's relevant copyrights in the software, without fee, provided that it + * is used in conjunction with NXP Semiconductors microcontrollers. This + * copyright, permission, and disclaimer notice must appear in all copies of + * this code. + */ + +#ifndef __RITIMER_001_H_ +#define __RITIMER_001_H_ + +#include "sys_config.h" +#include "cmsis.h" + +#ifdef __cplusplus +extern "C" { +#endif + +/** @defgroup IP_RITIMER_001 IP: RITimer register block and driver + * @ingroup IP_Drivers + * Repetitive Interrupt Timer + * @{ + */ + +/** + * @brief Repetitive Interrupt Timer register block structure + */ +typedef struct { /*!< RITIMER Structure */ + __IO uint32_t COMPVAL; /*!< Compare register */ + __IO uint32_t MASK; /*!< Mask register. This register holds the 32-bit mask value. A 1 written to any bit will force a compare on the corresponding bit of the counter and compare register. */ + __IO uint32_t CTRL; /*!< Control register. */ + __IO uint32_t COUNTER; /*!< 32-bit counter */ +} IP_RITIMER_001_Type; + +/** + * @brief RITIMER register support bitfields and mask + */ + +/* + * RIT control register + */ +/** Set by H/W when the counter value equals the masked compare value */ +#define RIT_CTRL_INT ((uint32_t) (1)) +/** Set timer enable clear to 0 when the counter value equals the masked compare value */ +#define RIT_CTRL_ENCLR ((uint32_t) _BIT(1)) +/** Set timer enable on debug */ +#define RIT_CTRL_ENBR ((uint32_t) _BIT(2)) +/** Set timer enable */ +#define RIT_CTRL_TEN ((uint32_t) _BIT(3)) + +/** + * @brief Initialize the RIT + * @param RITx : RIT peripheral selected + * @return None + */ +void IP_RIT_Init(IP_RITIMER_001_Type *RITx); + +/** + * @brief DeInitialize the RIT + * @param RITx : RIT peripheral selected + * @return None + */ +void IP_RIT_DeInit(IP_RITIMER_001_Type *RITx); + +/** + * @brief Enable/Disable Timer + * @param RITx : RIT peripheral selected + * @param NewState : ENABLE to enable RITimer, DISABLE to disable + * @return None + */ +void IP_RIT_Enable(IP_RITIMER_001_Type *RITx, FunctionalState NewState); + +/** + * @brief Timer Enable/Disable on debug + * @param RITx : RIT peripheral selected + * @param NewState : ENABLE to halt timer whenever a hardware break condition occurs + * @return None + */ +void IP_RIT_TimerDebugCmd(IP_RITIMER_001_Type *RITx, FunctionalState NewState); + +/** + * @brief Check whether interrupt flag is set or not + * @param RITx : RIT peripheral selected + * @return Current interrupt status, could be SET or UNSET + */ +IntStatus IP_RIT_GetIntStatus(IP_RITIMER_001_Type *RITx); + +/** + * @brief Set a tick value for the interrupt to time out + * @param RITx : RIT peripheral selected + * @param val : value (in ticks) of the interrupt to be set + * @return None + */ +STATIC INLINE void IP_RIT_SetCOMPVAL(IP_RITIMER_001_Type *RITx, uint32_t val) +{ + RITx->COMPVAL = val; +} + +/** + * @brief Enables or clears the RIT or interrupt + * @param RITx : RIT peripheral selected + * @param val : RIT to be set, one or more RIT_CTRL_* values + * @return None + */ +STATIC INLINE void IP_RIT_EnableCTRL(IP_RITIMER_001_Type *RITx, uint32_t val) +{ + RITx->CTRL |= val; +} + +/** + * @brief Get the RIT Counter value + * @param RITx : RIT peripheral selected + * @return the counter value + */ +STATIC INLINE uint32_t IP_RIT_GetCounter(IP_RITIMER_001_Type *RITx) +{ + return RITx->COUNTER; +} + +/** + * @} + */ + +#ifdef __cplusplus +} +#endif + +#endif /* __RITIMER_001_H_ */ diff --git a/bsp/xplorer4330/libraries/lpc_ip/rtc_001.c b/bsp/xplorer4330/libraries/lpc_ip/rtc_001.c new file mode 100644 index 0000000000..3a60d3b1e9 --- /dev/null +++ b/bsp/xplorer4330/libraries/lpc_ip/rtc_001.c @@ -0,0 +1,217 @@ +/* + * @brief Real Time Clock registers and control functions + * + * @note + * Copyright(C) NXP Semiconductors, 2012 + * All rights reserved. + * + * @par + * Software that is described herein is for illustrative purposes only + * which provides customers with programming information regarding the + * LPC products. This software is supplied "AS IS" without any warranties of + * any kind, and NXP Semiconductors and its licensor disclaim any and + * all warranties, express or implied, including all implied warranties of + * merchantability, fitness for a particular purpose and non-infringement of + * intellectual property rights. NXP Semiconductors assumes no responsibility + * or liability for the use of the software, conveys no license or rights under any + * patent, copyright, mask work right, or any other intellectual property rights in + * or to any products. NXP Semiconductors reserves the right to make changes + * in the software without notification. NXP Semiconductors also makes no + * representation or warranty that such application will be suitable for the + * specified use without further testing or modification. + * + * @par + * Permission to use, copy, modify, and distribute this software and its + * documentation is hereby granted, under NXP Semiconductors' and its + * licensor's relevant copyrights in the software, without fee, provided that it + * is used in conjunction with NXP Semiconductors microcontrollers. This + * copyright, permission, and disclaimer notice must appear in all copies of + * this code. + */ + +#include "rtc_001.h" + +/***************************************************************************** + * Private types/enumerations/variables + ****************************************************************************/ + +/***************************************************************************** + * Public types/enumerations/variables + ****************************************************************************/ + +/***************************************************************************** + * Private functions + ****************************************************************************/ + +/***************************************************************************** + * Public functions + ****************************************************************************/ + +/* Initialize the the RTC peripheral */ +void IP_RTC_Init(IP_RTC_001_T *pRTC) +{ + do { + /* Reset RTC clock*/ + pRTC->CCR = RTC_CCR_CTCRST | RTC_CCR_CCALEN; + } while (pRTC->CCR != (RTC_CCR_CTCRST | RTC_CCR_CCALEN)); + do { + /* Finish resetting RTC clock */ + pRTC->CCR = RTC_CCR_CCALEN; + } while (pRTC->CCR != RTC_CCR_CCALEN); + + /* Clear counter increment and alarm interrupt */ + pRTC->ILR = RTC_IRL_RTCCIF | RTC_IRL_RTCALF; + while (pRTC->ILR != 0) {} + + /* Clear all register to be default */ + pRTC->CIIR = 0x00; + pRTC->AMR = 0xFF; + pRTC->CALIBRATION = 0x00; +} + +/* Reset clock tick counter in the RTC peripheral */ +void IP_RTC_ResetClockTickCounter(IP_RTC_001_T *pRTC) +{ + pRTC->CCR |= RTC_CCR_CTCRST; + pRTC->CCR &= (~RTC_CCR_CTCRST) & RTC_CCR_BITMASK; +} + +/* Start/Stop RTC peripheral */ +void IP_RTC_Enable(IP_RTC_001_T *pRTC, FunctionalState NewState) +{ + if (NewState == ENABLE) { + do { + pRTC->CCR |= RTC_CCR_CLKEN; + } while ((pRTC->CCR & RTC_CCR_CLKEN) == 0); + } + else { + pRTC->CCR &= (~RTC_CCR_CLKEN) & RTC_CCR_BITMASK; + } +} + +/* Enable/Disable Counter increment interrupt for a time type in the RTC peripheral */ +void IP_RTC_CntIncrIntConfig(IP_RTC_001_T *pRTC, uint32_t cntrMask, + FunctionalState NewState) +{ + if (NewState == ENABLE) { + pRTC->CIIR |= cntrMask; + } + + else { + pRTC->CIIR &= (~cntrMask) & RTC_AMR_CIIR_BITMASK; + while (pRTC->CIIR & cntrMask) {} + } + +} + +/* Enable/Disable Alarm interrupt for a time type in the RTC peripheral */ +void IP_RTC_AlarmIntConfig(IP_RTC_001_T *pRTC, uint32_t alarmMask, + FunctionalState NewState) +{ + if (NewState == ENABLE) { + pRTC->AMR &= (~alarmMask) & RTC_AMR_CIIR_BITMASK; + } + else { + pRTC->AMR |= (alarmMask); + while ((pRTC->AMR & alarmMask) == 0) {} + } +} + +/* Set current time value for a time type in the RTC peripheral */ +void IP_RTC_SetTime(IP_RTC_001_T *pRTC, IP_RTC_TIMEINDEX_T Timetype, uint32_t TimeValue) +{ + pRTC->TIME[Timetype] = TimeValue; +} + +/* Get current time value for a type time type */ +uint32_t IP_RTC_GetTime(IP_RTC_001_T *pRTC, IP_RTC_TIMEINDEX_T Timetype) +{ + return pRTC->TIME[Timetype]; +} + +/* Set full time in the RTC peripheral */ +void IP_RTC_SetFullTime(IP_RTC_001_T *pRTC, IP_RTC_TIME_T *pFullTime) +{ + IP_RTC_TIMEINDEX_T i; + uint32_t secs = 0xFF; + + /* Write time to registers and verify second tick didn't update during the + write cycle. If it did, the time may not be consistent across all fields, + so write the time again */ + while (secs != pRTC->TIME[RTC_TIMETYPE_SECOND]) { + /* Write seconds first */ + for (i = RTC_TIMETYPE_SECOND; i < RTC_TIMETYPE_LAST; i++) { + pRTC->TIME[i] = pFullTime->time[i]; + } + + secs = pRTC->TIME[RTC_TIMETYPE_SECOND]; + } +} + +/* Get full time from the RTC peripheral */ +void IP_RTC_GetFullTime(IP_RTC_001_T *pRTC, IP_RTC_TIME_T *pFullTime) +{ + IP_RTC_TIMEINDEX_T i; + uint32_t secs = 0xFF; + + /* Read full time, but verify second tick didn't change during the read. If + it did, re-read the time again so it will be consistent across all fields. */ + while (secs != pRTC->TIME[RTC_TIMETYPE_SECOND]) { + secs = pFullTime->time[RTC_TIMETYPE_SECOND] = pRTC->TIME[RTC_TIMETYPE_SECOND]; + for (i = RTC_TIMETYPE_MINUTE; i < RTC_TIMETYPE_LAST; i++) { + pFullTime->time[i] = pRTC->TIME[i]; + } + } +} + +/* Set alarm time value for a time type */ +void IP_RTC_SetAlarmTime(IP_RTC_001_T *pRTC, IP_RTC_TIMEINDEX_T Timetype, uint32_t ALValue) +{ + pRTC->ALRM[Timetype] = ALValue; +} + +/* Get alarm time value for a time */ +uint32_t IP_RTC_GetAlarmTime(IP_RTC_001_T *pRTC, IP_RTC_TIMEINDEX_T Timetype) +{ + return pRTC->ALRM[Timetype]; +} + +/* Set full alarm time in the RTC peripheral */ +void IP_RTC_SetFullAlarmTime(IP_RTC_001_T *pRTC, IP_RTC_TIME_T *pFullTime) +{ + IP_RTC_TIMEINDEX_T i; + + for (i = RTC_TIMETYPE_SECOND; i < RTC_TIMETYPE_LAST; i++) { + pRTC->ALRM[i] = pFullTime->time[i]; + } +} + +/* Get full alarm time in the RTC peripheral */ +void IP_RTC_GetFullAlarmTime(IP_RTC_001_T *pRTC, IP_RTC_TIME_T *pFullTime) +{ + IP_RTC_TIMEINDEX_T i; + + for (i = RTC_TIMETYPE_SECOND; i < RTC_TIMETYPE_LAST; i++) { + pFullTime->time[i] = pRTC->ALRM[i]; + } +} + +/* Enable/Disable calibration counter in the RTC peripheral */ +void IP_RTC_CalibCounterCmd(IP_RTC_001_T *pRTC, FunctionalState NewState) +{ + if (NewState == ENABLE) { + do { + pRTC->CCR &= (~RTC_CCR_CCALEN) & RTC_CCR_BITMASK; + } while (pRTC->CCR & RTC_CCR_CCALEN); + } + else { + pRTC->CCR |= RTC_CCR_CCALEN; + } +} + +/* Configures Calibration in the RTC peripheral */ +void IP_RTC_CalibConfig(IP_RTC_001_T *pRTC, uint32_t CalibValue, uint8_t CalibDir) +{ + pRTC->CALIBRATION = ((CalibValue - 1) & RTC_CALIBRATION_CALVAL_MASK) + | ((CalibDir == RTC_CALIB_DIR_BACKWARD) ? RTC_CALIBRATION_LIBDIR : 0); +} diff --git a/bsp/xplorer4330/libraries/lpc_ip/rtc_001.h b/bsp/xplorer4330/libraries/lpc_ip/rtc_001.h new file mode 100644 index 0000000000..4478658d75 --- /dev/null +++ b/bsp/xplorer4330/libraries/lpc_ip/rtc_001.h @@ -0,0 +1,405 @@ +/* + * @brief Real Time Clock registers and control functions + * + * @note + * Copyright(C) NXP Semiconductors, 2012 + * All rights reserved. + * + * @par + * Software that is described herein is for illustrative purposes only + * which provides customers with programming information regarding the + * LPC products. This software is supplied "AS IS" without any warranties of + * any kind, and NXP Semiconductors and its licensor disclaim any and + * all warranties, express or implied, including all implied warranties of + * merchantability, fitness for a particular purpose and non-infringement of + * intellectual property rights. NXP Semiconductors assumes no responsibility + * or liability for the use of the software, conveys no license or rights under any + * patent, copyright, mask work right, or any other intellectual property rights in + * or to any products. NXP Semiconductors reserves the right to make changes + * in the software without notification. NXP Semiconductors also makes no + * representation or warranty that such application will be suitable for the + * specified use without further testing or modification. + * + * @par + * Permission to use, copy, modify, and distribute this software and its + * documentation is hereby granted, under NXP Semiconductors' and its + * licensor's relevant copyrights in the software, without fee, provided that it + * is used in conjunction with NXP Semiconductors microcontrollers. This + * copyright, permission, and disclaimer notice must appear in all copies of + * this code. + */ + +#ifndef __RTC_001_H_ +#define __RTC_001_H_ + +#include "sys_config.h" +#include "cmsis.h" + +#ifdef __cplusplus +extern "C" { +#endif + +/** @defgroup IP_RTC_001 IP: RTC register block and driver + * @ingroup IP_Drivers + * Real Time Clock + * @{ + */ + +/** + * @brief RTC time type option + */ +typedef enum { + RTC_TIMETYPE_SECOND, /*!< Second */ + RTC_TIMETYPE_MINUTE, /*!< Month */ + RTC_TIMETYPE_HOUR, /*!< Hour */ + RTC_TIMETYPE_DAYOFMONTH, /*!< Day of month */ + RTC_TIMETYPE_DAYOFWEEK, /*!< Day of week */ + RTC_TIMETYPE_DAYOFYEAR, /*!< Day of year */ + RTC_TIMETYPE_MONTH, /*!< Month */ + RTC_TIMETYPE_YEAR, /*!< Year */ + RTC_TIMETYPE_LAST +} IP_RTC_TIMEINDEX_T; + +/** + * @brief Real Time Clock register block structure + */ +typedef struct { /*!< RTC Structure */ + __O uint32_t ILR; /*!< Interrupt Location Register */ + __I uint32_t RESERVED0; + __IO uint32_t CCR; /*!< Clock Control Register */ + __IO uint32_t CIIR; /*!< Counter Increment Interrupt Register */ + __IO uint32_t AMR; /*!< Alarm Mask Register */ + __I uint32_t CTIME[3]; /*!< Consolidated Time Register 0,1,2 */ + __IO uint32_t TIME[RTC_TIMETYPE_LAST]; /*!< Timer field registers */ + __IO uint32_t CALIBRATION; /*!< Calibration Value Register */ +#if defined(CHIP_LPC177X_8X) + __IO uint32_t GPREG[5]; /*!< General Purpose Storage Registers */ + __IO uint32_t RTC_AUXEN; /*!< */ + __IO uint32_t RTC_AUX; /*!< */ +#else + __I uint32_t RESERVED1[7]; +#endif + __IO uint32_t ALRM[RTC_TIMETYPE_LAST]; /*!< Alarm field registers */ +#if defined(CHIP_LPC177X_8X) + __IO uint32_t ERSTATUS; +#endif +} IP_RTC_001_T; + +/** + * @brief ILR register definitions + */ +/** ILR register mask */ +#define RTC_ILR_BITMASK ((0x00000003)) +/** Bit inform the source interrupt is counter increment*/ +#define RTC_IRL_RTCCIF ((1 << 0)) +/** Bit inform the source interrupt is alarm match*/ +#define RTC_IRL_RTCALF ((1 << 1)) + +/** + * @brief CCR register definitions + */ +/** CCR register mask */ +#define RTC_CCR_BITMASK ((0x00000013)) +/** Clock enable */ +#define RTC_CCR_CLKEN ((1 << 0)) +/** Clock reset */ +#define RTC_CCR_CTCRST ((1 << 1)) +/** Calibration counter enable */ +#define RTC_CCR_CCALEN ((1 << 4)) + +/** + * @brief CIIR and AMR register definitions + */ +/** Counter Increment Interrupt bit for second */ +#define RTC_AMR_CIIR_IMSEC ((1 << 0)) +/** Counter Increment Interrupt bit for minute */ +#define RTC_AMR_CIIR_IMMIN ((1 << 1)) +/** Counter Increment Interrupt bit for hour */ +#define RTC_AMR_CIIR_IMHOUR ((1 << 2)) +/** Counter Increment Interrupt bit for day of month */ +#define RTC_AMR_CIIR_IMDOM ((1 << 3)) +/** Counter Increment Interrupt bit for day of week */ +#define RTC_AMR_CIIR_IMDOW ((1 << 4)) +/** Counter Increment Interrupt bit for day of year */ +#define RTC_AMR_CIIR_IMDOY ((1 << 5)) +/** Counter Increment Interrupt bit for month */ +#define RTC_AMR_CIIR_IMMON ((1 << 6)) +/** Counter Increment Interrupt bit for year */ +#define RTC_AMR_CIIR_IMYEAR ((1 << 7)) +/** CIIR bit mask */ +#define RTC_AMR_CIIR_BITMASK ((0xFF)) + +/** + * @brief RTC_AUX register definitions + */ +/** RTC Oscillator Fail detect flag */ +#define RTC_AUX_RTC_OSCF ((1 << 4)) + +/** + * @brief RTC_AUXEN register definitions + */ +/** Oscillator Fail Detect interrupt enable*/ +#define RTC_AUXEN_RTC_OSCFEN ((1 << 4)) + +/** + * @brief Consolidated Time Register 0 definitions + */ +#define RTC_CTIME0_SECONDS_MASK ((0x3F)) +#define RTC_CTIME0_MINUTES_MASK ((0x3F00)) +#define RTC_CTIME0_HOURS_MASK ((0x1F0000)) +#define RTC_CTIME0_DOW_MASK ((0x7000000)) + +/** + * @brief Consolidated Time Register 1 definitions + */ +#define RTC_CTIME1_DOM_MASK ((0x1F)) +#define RTC_CTIME1_MONTH_MASK ((0xF00)) +#define RTC_CTIME1_YEAR_MASK ((0xFFF0000)) + +/** + * @brief Consolidated Time Register 2 definitions + */ +#define RTC_CTIME2_DOY_MASK ((0xFFF)) + +/** + * @brief Time Counter Group and Alarm register group + */ +/** SEC register mask */ +#define RTC_SEC_MASK (0x0000003F) +/** MIN register mask */ +#define RTC_MIN_MASK (0x0000003F) +/** HOUR register mask */ +#define RTC_HOUR_MASK (0x0000001F) +/** DOM register mask */ +#define RTC_DOM_MASK (0x0000001F) +/** DOW register mask */ +#define RTC_DOW_MASK (0x00000007) +/** DOY register mask */ +#define RTC_DOY_MASK (0x000001FF) +/** MONTH register mask */ +#define RTC_MONTH_MASK (0x0000000F) +/** YEAR register mask */ +#define RTC_YEAR_MASK (0x00000FFF) + +#define RTC_SECOND_MAX 59 /*!< Maximum value of second */ +#define RTC_MINUTE_MAX 59 /*!< Maximum value of minute*/ +#define RTC_HOUR_MAX 23 /*!< Maximum value of hour*/ +#define RTC_MONTH_MIN 1 /*!< Minimum value of month*/ +#define RTC_MONTH_MAX 12 /*!< Maximum value of month*/ +#define RTC_DAYOFMONTH_MIN 1 /*!< Minimum value of day of month*/ +#define RTC_DAYOFMONTH_MAX 31 /*!< Maximum value of day of month*/ +#define RTC_DAYOFWEEK_MAX 6 /*!< Maximum value of day of week*/ +#define RTC_DAYOFYEAR_MIN 1 /*!< Minimum value of day of year*/ +#define RTC_DAYOFYEAR_MAX 366 /*!< Maximum value of day of year*/ +#define RTC_YEAR_MAX 4095/*!< Maximum value of year*/ + +/** + * @brief Calibration register + */ +/** Calibration value */ +#define RTC_CALIBRATION_CALVAL_MASK ((0x1FFFF)) +/** Calibration direction */ +#define RTC_CALIBRATION_LIBDIR ((1 << 17)) +/** Calibration max value */ +#define RTC_CALIBRATION_MAX ((0x20000)) +/** Calibration definitions */ +#define RTC_CALIB_DIR_FORWARD ((uint8_t) (0)) +#define RTC_CALIB_DIR_BACKWARD ((uint8_t) (1)) + +/* Check Parameter Definitions */ +/** Macro to determine if it is valid RTC peripheral */ +#define PARAM_pRTC(x) (((uint32_t *) x) == ((uint32_t *) LPC_RTC)) + +/* Macro check RTC interrupt type */ +#define PARAM_RTC_INT(n) ((n == RTC_INT_COUNTER_INCREASE) || (n == RTC_INT_ALARM)) + +/* Macro check RTC calibration type */ +#define PARAM_RTC_CALIB_DIR(n) ((n == RTC_CALIB_DIR_FORWARD) || (n == RTC_CALIB_DIR_BACKWARD)) + +/** + * @brief RTC enumeration + */ + +/** @brief RTC interrupt source */ +typedef enum { + RTC_INT_COUNTER_INCREASE = RTC_IRL_RTCCIF, /*!< Counter Increment Interrupt */ + RTC_INT_ALARM = RTC_IRL_RTCALF /*!< The alarm interrupt */ +} IP_RTC_INT_OPT; + +typedef struct { + uint32_t time[RTC_TIMETYPE_LAST]; +} IP_RTC_TIME_T; + +/** + * @brief Initialize the RTC peripheral + * @param pRTC : pointer to RTC peripheral block + * @return None + */ +void IP_RTC_Init(IP_RTC_001_T *pRTC); + +/** + * @brief De-initialize the RTC peripheral + * @param pRTC : pointer to RTC peripheral block + * @return None + */ +STATIC INLINE void IP_RTC_DeInit(IP_RTC_001_T *pRTC) +{ + pRTC->CCR = 0x00; +} + +/** + * @brief Reset clock tick counter in the RTC peripheral + * @param pRTC : pointer to RTC peripheral block + * @return None + */ +void IP_RTC_ResetClockTickCounter(IP_RTC_001_T *pRTC); + +/** + * @brief Start/Stop RTC peripheral + * @param pRTC : pointer to RTC peripheral block + * @param NewState : ENABLE or DISABLE + * @return None + */ +void IP_RTC_Enable(IP_RTC_001_T *pRTC, FunctionalState NewState); + +/** + * @brief Enable/Disable Counter increment interrupt for a time type in the RTC peripheral + * @param pRTC : pointer to RTC peripheral block + * @param cntrMask : Or'ed bit values for time types (RTC_AMR_CIIR_IM*) + * @param NewState : ENABLE or DISABLE + * @return None + */ +void IP_RTC_CntIncrIntConfig(IP_RTC_001_T *pRTC, uint32_t cntrMask, FunctionalState NewState); + +/** + * @brief Enable/Disable Alarm interrupt for a time type in the RTC peripheral + * @param pRTC : pointer to RTC peripheral block + * @param alarmMask : Or'ed bit values for ALARM types (RTC_AMR_CIIR_IM*) + * @param NewState : ENABLE or DISABLE + * @return None + */ +void IP_RTC_AlarmIntConfig(IP_RTC_001_T *pRTC, uint32_t alarmMask, FunctionalState NewState); + +/** + * @brief Set current time value for a time type in the RTC peripheral + * @param pRTC : pointer to RTC peripheral block + * @param Timetype : time field index type to set + * @param TimeValue : Value to palce in time field + * @return None + */ +void IP_RTC_SetTime(IP_RTC_001_T *pRTC, IP_RTC_TIMEINDEX_T Timetype, uint32_t TimeValue); + +/** + * @brief Get current time value for a type time type + * @param pRTC : pointer to RTC peripheral block + * @param Timetype : Time field index type to get + * @return Value of time field according to specified time type + */ +uint32_t IP_RTC_GetTime(IP_RTC_001_T *pRTC, IP_RTC_TIMEINDEX_T Timetype); + +/** + * @brief Set full time in the RTC peripheral + * @param pRTC : pointer to RTC peripheral block + * @param pFullTime : Pointer to full time data + * @return None + */ +void IP_RTC_SetFullTime(IP_RTC_001_T *pRTC, IP_RTC_TIME_T *pFullTime); + +/** + * @brief Get full time from the RTC peripheral + * @param pRTC : pointer to RTC peripheral block + * @param pFullTime : Pointer to full time record to fill + * @return None + */ +void IP_RTC_GetFullTime(IP_RTC_001_T *pRTC, IP_RTC_TIME_T *pFullTime); + +/** + * @brief Set alarm time value for a time type + * @param pRTC : pointer to RTC peripheral block + * @param Timetype : Time index field to set + * @param ALValue : Alarm time value to set + * @return None + */ +void IP_RTC_SetAlarmTime(IP_RTC_001_T *pRTC, IP_RTC_TIMEINDEX_T Timetype, uint32_t ALValue); + +/** + * @brief Get alarm time value for a time type + * @param pRTC : pointer to RTC peripheral block + * @param Timetype : Time index field to get + * @return Value of Alarm time according to specified time type + */ +uint32_t IP_RTC_GetAlarmTime(IP_RTC_001_T *pRTC, IP_RTC_TIMEINDEX_T Timetype); + +/** + * @brief Set full alarm time in the RTC peripheral + * @param pRTC : pointer to RTC peripheral block + * @param pFullTime : Pointer to full time record to set alarm + * @return None + */ +void IP_RTC_SetFullAlarmTime(IP_RTC_001_T *pRTC, IP_RTC_TIME_T *pFullTime); + +/** + * @brief Get full alarm time in the RTC peripheral + * @param pRTC : pointer to RTC peripheral block + * @param pFullTime : Pointer to full time record to fill + * @return None + */ +void IP_RTC_GetFullAlarmTime(IP_RTC_001_T *pRTC, IP_RTC_TIME_T *pFullTime); + +/** + * @brief Enable/Disable calibration counter in the RTC peripheral + * @param pRTC : pointer to RTC peripheral block + * @param NewState : New State of this function, should be: + * - ENABLE :The calibration counter is enabled and counting + * - DISABLE :The calibration counter is disabled and reset to zero + * @return None + */ +void IP_RTC_CalibCounterCmd(IP_RTC_001_T *pRTC, FunctionalState NewState); + +/** + * @brief Configures Calibration in the RTC peripheral + * @param pRTC : pointer to RTC peripheral block + * @param CalibValue : Calibration value, should be in range from 0 to 131,072 + * @param CalibDir : Calibration Direction, should be: + * - RTC_CALIB_DIR_FORWARD :Forward calibration + * - RTC_CALIB_DIR_BACKWARD :Backward calibration + * @return None + */ +void IP_RTC_CalibConfig(IP_RTC_001_T *pRTC, uint32_t CalibValue, uint8_t CalibDir); + +/** + * @brief Clear specified Location interrupt pending in the RTC peripheral + * @param pRTC : pointer to RTC peripheral block + * @param IntType : Interrupt location type, should be: + * - RTC_INT_COUNTER_INCREASE :Clear Counter Increment Interrupt pending. + * - RTC_INT_ALARM :Clear alarm interrupt pending + * @return None + */ +STATIC INLINE void IP_RTC_ClearIntPending(IP_RTC_001_T *pRTC, uint32_t IntType) +{ + pRTC->ILR = IntType; +} + +/** + * @brief Check whether if specified location interrupt in the + * RTC peripheral is set or not + * @param pRTC : pointer to RTC peripheral block + * @param IntType : Interrupt location type, should be: + * - RTC_INT_COUNTER_INCREASE: Counter Increment Interrupt block generated an interrupt. + * - RTC_INT_ALARM: Alarm generated an interrupt. + * @return Current state of specified interrupt in RTC peripheral, SET or RESET + */ +STATIC INLINE IntStatus IP_RTC_GetIntPending(IP_RTC_001_T *pRTC, uint32_t IntType) +{ + return (pRTC->ILR & IntType) ? SET : RESET; +} + +/** + * @} + */ + +#ifdef __cplusplus +} +#endif + +#endif /* __RTC_001_H_ */ diff --git a/bsp/xplorer4330/libraries/lpc_ip/sct_001.h b/bsp/xplorer4330/libraries/lpc_ip/sct_001.h new file mode 100644 index 0000000000..0ee0dd1e80 --- /dev/null +++ b/bsp/xplorer4330/libraries/lpc_ip/sct_001.h @@ -0,0 +1,171 @@ +/* +* @brief State Configurable Timer registers and control functions +* +* @note +* Copyright(C) NXP Semiconductors, 2012 +* All rights reserved. +* +* @par +* Software that is described herein is for illustrative purposes only +* which provides customers with programming information regarding the +* LPC products. This software is supplied "AS IS" without any warranties of +* any kind, and NXP Semiconductors and its licensor disclaim any and +* all warranties, express or implied, including all implied warranties of +* merchantability, fitness for a particular purpose and non-infringement of +* intellectual property rights. NXP Semiconductors assumes no responsibility +* or liability for the use of the software, conveys no license or rights under any +* patent, copyright, mask work right, or any other intellectual property rights in +* or to any products. NXP Semiconductors reserves the right to make changes +* in the software without notification. NXP Semiconductors also makes no +* representation or warranty that such application will be suitable for the +* specified use without further testing or modification. +* +* @par +* Permission to use, copy, modify, and distribute this software and its +* documentation is hereby granted, under NXP Semiconductors' and its +* licensor's relevant copyrights in the software, without fee, provided that it +* is used in conjunction with NXP Semiconductors microcontrollers. This +* copyright, permission, and disclaimer notice must appear in all copies of +* this code. +*/ + +#ifndef __SCT_001_H_ +#define __SCT_001_H_ + +#include "sys_config.h" +#include "cmsis.h" + +#ifdef __cplusplus +extern "C" { +#endif + +/** @defgroup IP_SCT_001 IP: SCT register block and driver + * @ingroup IP_Drivers + * State Configurable Timer + * @{ + */ + +#define CONFIG_SCT_nEV (16) /* Number of events */ +#define CONFIG_SCT_nRG (16) /* Number of match/compare registers */ +#define CONFIG_SCT_nOU (16) /* Number of outputs */ + +/** + * @brief State Configurable Timer register block structure + */ +typedef struct +{ + __IO uint32_t CONFIG; /* Configuration Register */ + union { + __IO uint32_t CTRL_U; /* Control Register */ + struct { + __IO uint16_t CTRL_L; /* low control register */ + __IO uint16_t CTRL_H; /* high control register */ + }; + }; + __IO uint16_t LIMIT_L; /* limit register for counter L */ + __IO uint16_t LIMIT_H; /* limit register for counter H */ + __IO uint16_t HALT_L; /* halt register for counter L */ + __IO uint16_t HALT_H; /* halt register for counter H */ + __IO uint16_t STOP_L; /* stop register for counter L */ + __IO uint16_t STOP_H; /* stop register for counter H */ + __IO uint16_t START_L; /* start register for counter L */ + __IO uint16_t START_H; /* start register for counter H */ + uint32_t RESERVED1[10]; /* 0x03C reserved */ + union { + __IO uint32_t COUNT_U; /* counter register */ + struct { + __IO uint16_t COUNT_L; /* counter register for counter L */ + __IO uint16_t COUNT_H; /* counter register for counter H */ + }; + }; + __IO uint16_t STATE_L; /* state register for counter L */ + __IO uint16_t STATE_H; /* state register for counter H */ + __I uint32_t INPUT; /* input register */ + __IO uint16_t REGMODE_L; /* match - capture registers mode register L */ + __IO uint16_t REGMODE_H; /* match - capture registers mode register H */ + __IO uint32_t OUTPUT; /* output register */ + __IO uint32_t OUTPUTDIRCTRL; /* output counter direction Control Register */ + __IO uint32_t RES; /* conflict resolution register */ + __IO uint32_t DMA0REQUEST; /* DMA0 Request Register */ + __IO uint32_t DMA1REQUEST; /* DMA1 Request Register */ + uint32_t RESERVED2[35]; + __IO uint32_t EVEN; /* event enable register */ + __IO uint32_t EVFLAG; /* event flag register */ + __IO uint32_t CONEN; /* conflict enable register */ + __IO uint32_t CONFLAG; /* conflict flag register */ + union { + __IO union { /* ... Match / Capture value */ + uint32_t U; /* SCTMATCH[i].U Unified 32-bit register */ + struct { + uint16_t L; /* SCTMATCH[i].L Access to L value */ + uint16_t H; /* SCTMATCH[i].H Access to H value */ + }; + } MATCH[CONFIG_SCT_nRG]; + __I union { + uint32_t U; /* SCTCAP[i].U Unified 32-bit register */ + struct { + uint16_t L; /* SCTCAP[i].L Access to H value */ + uint16_t H; /* SCTCAP[i].H Access to H value */ + }; + } CAP[CONFIG_SCT_nRG]; + }; + uint32_t RESERVED3[32-CONFIG_SCT_nRG]; /* ...-0x17C reserved */ + union { + __IO uint16_t MATCH_L[CONFIG_SCT_nRG]; /* 0x180-... Match Value L counter */ + __I uint16_t CAP_L[CONFIG_SCT_nRG]; /* 0x180-... Capture Value L counter */ + }; + uint16_t RESERVED4[32-CONFIG_SCT_nRG]; /* ...-0x1BE reserved */ + union { + __IO uint16_t MATCH_H[CONFIG_SCT_nRG]; /* 0x1C0-... Match Value H counter */ + __I uint16_t CAP_H[CONFIG_SCT_nRG]; /* 0x1C0-... Capture Value H counter */ + }; + uint16_t RESERVED5[32-CONFIG_SCT_nRG]; /* ...-0x1FE reserved */ + union { + __IO union { /* 0x200-... Match Reload / Capture Control value */ + uint32_t U; /* SCTMATCHREL[i].U Unified 32-bit register */ + struct { + uint16_t L; /* SCTMATCHREL[i].L Access to L value */ + uint16_t H; /* SCTMATCHREL[i].H Access to H value */ + }; + } MATCHREL[CONFIG_SCT_nRG]; + __IO union { + uint32_t U; /* SCTCAPCTRL[i].U Unified 32-bit register */ + struct { + uint16_t L; /* SCTCAPCTRL[i].L Access to H value */ + uint16_t H; /* SCTCAPCTRL[i].H Access to H value */ + }; + } CAPCTRL[CONFIG_SCT_nRG]; + }; + uint32_t RESERVED6[32-CONFIG_SCT_nRG]; /* ...-0x27C reserved */ + union { + __IO uint16_t MATCHREL_L[CONFIG_SCT_nRG]; /* 0x280-... Match Reload value L counter */ + __IO uint16_t CAPCTRL_L[CONFIG_SCT_nRG]; /* 0x280-... Capture Control value L counter */ + }; + uint16_t RESERVED7[32-CONFIG_SCT_nRG]; /* ...-0x2BE reserved */ + union { + __IO uint16_t MATCHREL_H[CONFIG_SCT_nRG]; /* 0x2C0-... Match Reload value H counter */ + __IO uint16_t CAPCTRL_H[CONFIG_SCT_nRG]; /* 0x2C0-... Capture Control value H counter */ + }; + uint16_t RESERVED8[32-CONFIG_SCT_nRG]; /* ...-0x2FE reserved */ + __IO struct { /* 0x300-0x3FC SCTEVENT[i].STATE / SCTEVENT[i].CTRL*/ + uint32_t STATE; /* Event State Register */ + uint32_t CTRL; /* Event Control Register */ + } EVENT[CONFIG_SCT_nEV]; + uint32_t RESERVED9[128-2*CONFIG_SCT_nEV]; /* ...-0x4FC reserved */ + __IO struct { /* 0x500-0x57C SCTOUT[i].SET / SCTOUT[i].CLR */ + uint32_t SET; /* Output n Set Register */ + uint32_t CLR; /* Output n Clear Register */ + } OUT[CONFIG_SCT_nOU]; + uint32_t RESERVED10[191-2*CONFIG_SCT_nOU]; /* ...-0x7F8 reserved */ + __I uint32_t MODULECONTENT; /* 0x7FC Module Content */ +} IP_SCT_001_Type; + +/** + * @} + */ + +#ifdef __cplusplus +} +#endif + +#endif /* __SCT_001_H_ */ diff --git a/bsp/xplorer4330/libraries/lpc_ip/sdmmc_001.c b/bsp/xplorer4330/libraries/lpc_ip/sdmmc_001.c new file mode 100644 index 0000000000..356559a71a --- /dev/null +++ b/bsp/xplorer4330/libraries/lpc_ip/sdmmc_001.c @@ -0,0 +1,300 @@ +/* + * @brief SD/SDIO (MCI) registers and control functions + * + * @note + * Copyright(C) NXP Semiconductors, 2012 + * All rights reserved. + * + * @par + * Software that is described herein is for illustrative purposes only + * which provides customers with programming information regarding the + * LPC products. This software is supplied "AS IS" without any warranties of + * any kind, and NXP Semiconductors and its licensor disclaim any and + * all warranties, express or implied, including all implied warranties of + * merchantability, fitness for a particular purpose and non-infringement of + * intellectual property rights. NXP Semiconductors assumes no responsibility + * or liability for the use of the software, conveys no license or rights under any + * patent, copyright, mask work right, or any other intellectual property rights in + * or to any products. NXP Semiconductors reserves the right to make changes + * in the software without notification. NXP Semiconductors also makes no + * representation or warranty that such application will be suitable for the + * specified use without further testing or modification. + * + * @par + * Permission to use, copy, modify, and distribute this software and its + * documentation is hereby granted, under NXP Semiconductors' and its + * licensor's relevant copyrights in the software, without fee, provided that it + * is used in conjunction with NXP Semiconductors microcontrollers. This + * copyright, permission, and disclaimer notice must appear in all copies of + * this code. + */ + +#include "sdmmc_001.h" + +/***************************************************************************** + * Private types/enumerations/variables + ****************************************************************************/ + +/***************************************************************************** + * Public types/enumerations/variables + ****************************************************************************/ + +/***************************************************************************** + * Private functions + ****************************************************************************/ + +/***************************************************************************** + * Public functions + ****************************************************************************/ + +/* Initializes the MCI card controller */ +void IP_SDMMC_Init(IP_SDMMC_001_Type *pSDMMC) +{ + /* Software reset */ + pSDMMC->BMOD = MCI_BMOD_SWR; + + /* reset all blocks */ + pSDMMC->CTRL = MCI_CTRL_RESET | MCI_CTRL_FIFO_RESET | MCI_CTRL_DMA_RESET; + while (pSDMMC->CTRL & (MCI_CTRL_RESET | MCI_CTRL_FIFO_RESET | MCI_CTRL_DMA_RESET)) {} + + /* Internal DMA setup for control register */ + pSDMMC->CTRL = MCI_CTRL_USE_INT_DMAC | MCI_CTRL_INT_ENABLE; + pSDMMC->INTMASK = 0; + + /* Clear the interrupts for the host controller */ + pSDMMC->RINTSTS = 0xFFFFFFFF; + + /* Put in max timeout */ + pSDMMC->TMOUT = 0xFFFFFFFF; + + /* FIFO threshold settings for DMA, DMA burst of 4, FIFO watermark at 16 */ + pSDMMC->FIFOTH = MCI_FIFOTH_DMA_MTS_4 | MCI_FIFOTH_RX_WM((SD_FIFO_SZ / 2) - 1) | MCI_FIFOTH_TX_WM(SD_FIFO_SZ / 2); + + /* Enable internal DMA, burst size of 4, fixed burst */ + pSDMMC->BMOD = MCI_BMOD_DE | MCI_BMOD_PBL4 | MCI_BMOD_DSL(4); + + /* disable clock to CIU (needs latch) */ + pSDMMC->CLKENA = 0; + pSDMMC->CLKSRC = 0; +} + +/* Close the MCI */ +void IP_SDMMC_DeInit(IP_SDMMC_001_Type *pSDMMC) +{} + +/* Set block size for transfer */ +void IP_SDMMC_SetBlkSize(IP_SDMMC_001_Type *pSDMMC, uint32_t bytes) +{ + pSDMMC->BLKSIZ = bytes; +} + +/* Reset card in slot */ +void IP_SDMMC_Reset(IP_SDMMC_001_Type *pSDMMC, int32_t reset) +{ + if (reset) { + pSDMMC->RST_N = 1; + } + else { + pSDMMC->RST_N = 0; + } +} + +/* Enable or disable slot power */ +void IP_SDMMC_PowerOnOff(IP_SDMMC_001_Type *pSDMMC, int32_t enable) +{ + if (enable) { + pSDMMC->PWREN = 1; + } + else { + pSDMMC->PWREN = 0; + } +} + +/* Detect if write protect is enabled */ +int32_t IP_SDMMC_CardWpOn(IP_SDMMC_001_Type *pSDMMC) +{ + if (pSDMMC->WRTPRT & 1) { + return 1; + } + return 0; +} + +/* Detect if an SD card is inserted */ +int32_t IP_SDMMC_CardNDetect(IP_SDMMC_001_Type *pSDMMC) +{ + /* No card = high state in regsiter */ + if (pSDMMC->CDETECT & 1) { + return 0; + } + + return 1; +} + +/* Function to send command to Card interface unit (CIU) */ +int32_t IP_SDMMC_SendCmd(IP_SDMMC_001_Type *pSDMMC, uint32_t cmd, uint32_t arg) +{ + volatile int32_t tmo = 50; + volatile int delay; + + /* set command arg reg*/ + pSDMMC->CMDARG = arg; + pSDMMC->CMD = MCI_CMD_START | cmd; + + /* poll untill command is accepted by the CIU */ + while (--tmo && (pSDMMC->CMD & MCI_CMD_START)) { + if (tmo & 1) { + delay = 50; + } + else { + delay = 18000; + } + + while (--delay > 1) {} + } + + return (tmo < 1) ? 1 : 0; +} + +/* Read the response from the last command */ +void IP_SDMMC_GetResponse(IP_SDMMC_001_Type *pSDMMC, uint32_t *resp) +{ + /* on this chip response is not a fifo so read all 4 regs */ + resp[0] = pSDMMC->RESP0; + resp[1] = pSDMMC->RESP1; + resp[2] = pSDMMC->RESP2; + resp[3] = pSDMMC->RESP3; +} + +/* Sets the SD bus clock speed */ +void IP_SDMMC_SetClock(IP_SDMMC_001_Type *pSDMMC, uint32_t clk_rate, uint32_t speed) +{ + /* compute SD/MMC clock dividers */ + uint32_t div; + + div = ((clk_rate / speed) + 2) >> 1; + + if ((div == pSDMMC->CLKDIV) && pSDMMC->CLKENA) { + return; /* Closest speed is already set */ + + } + /* disable clock */ + pSDMMC->CLKENA = 0; + + /* User divider 0 */ + pSDMMC->CLKSRC = MCI_CLKSRC_CLKDIV0; + + /* inform CIU */ + IP_SDMMC_SendCmd(pSDMMC, MCI_CMD_UPD_CLK | MCI_CMD_PRV_DAT_WAIT, 0); + + /* set divider 0 to desired value */ + pSDMMC->CLKDIV = MCI_CLOCK_DIVIDER(0, div); + + /* inform CIU */ + IP_SDMMC_SendCmd(pSDMMC, MCI_CMD_UPD_CLK | MCI_CMD_PRV_DAT_WAIT, 0); + + /* enable clock */ + pSDMMC->CLKENA = MCI_CLKEN_ENABLE; + + /* inform CIU */ + IP_SDMMC_SendCmd(pSDMMC, MCI_CMD_UPD_CLK | MCI_CMD_PRV_DAT_WAIT, 0); +} + +/* Function to set card type */ +void IP_SDMMC_SetCardType(IP_SDMMC_001_Type *pSDMMC, uint32_t ctype) +{ + pSDMMC->CTYPE = ctype; +} + +/* Function to clear interrupt & FIFOs */ +void IP_SDMMC_SetClearIntFifo(IP_SDMMC_001_Type *pSDMMC) +{ + /* reset all blocks */ + pSDMMC->CTRL |= MCI_CTRL_FIFO_RESET; + + /* wait till resets clear */ + while (pSDMMC->CTRL & MCI_CTRL_FIFO_RESET) {} + + /* Clear interrupt status */ + pSDMMC->RINTSTS = 0xFFFFFFFF; +} + +/* Returns the raw SD interface interrupt status */ +uint32_t IP_SDMMC_GetRawIntStatus(IP_SDMMC_001_Type *pSDMMC) +{ + return pSDMMC->RINTSTS; +} + +/* Sets the raw SD interface interrupt status */ +void IP_SDMMC_SetRawIntStatus(IP_SDMMC_001_Type *pSDMMC, uint32_t iVal) +{ + pSDMMC->RINTSTS = iVal; +} + +/* Sets the SD interface interrupt mask */ +void IP_SDMMC_SetIntMask(IP_SDMMC_001_Type *pSDMMC, uint32_t iVal) +{ + pSDMMC->INTMASK = iVal; +} + +/* Setup DMA descriptors */ +void IP_SDMMC_DmaSetup(IP_SDMMC_001_Type *pSDMMC, sdif_device *psdif_dev, uint32_t addr, uint32_t size) +{ + int i = 0; + uint32_t ctrl, maxs; + + /* Reset DMA */ + pSDMMC->CTRL |= MCI_CTRL_DMA_RESET | MCI_CTRL_FIFO_RESET; + while (pSDMMC->CTRL & MCI_CTRL_DMA_RESET) {} + + /* Build a descriptor list using the chained DMA method */ + while (size > 0) { + /* Limit size of the transfer to maximum buffer size */ + maxs = size; + if (maxs > MCI_DMADES1_MAXTR) { + maxs = MCI_DMADES1_MAXTR; + } + size -= maxs; + + /* Set buffer size */ + psdif_dev->mci_dma_dd[i].des1 = MCI_DMADES1_BS1(maxs); + + /* Setup buffer address (chained) */ + psdif_dev->mci_dma_dd[i].des2 = addr + (i * MCI_DMADES1_MAXTR); + + /* Setup basic control */ + ctrl = MCI_DMADES0_OWN | MCI_DMADES0_CH; + if (i == 0) { + ctrl |= MCI_DMADES0_FS; /* First DMA buffer */ + + } + /* No more data? Then this is the last descriptor */ + if (!size) { + ctrl |= MCI_DMADES0_LD; + } + else { + ctrl |= MCI_DMADES0_DIC; + } + + /* Another descriptor is needed */ + psdif_dev->mci_dma_dd[i].des3 = (uint32_t) &psdif_dev->mci_dma_dd[i + 1]; + psdif_dev->mci_dma_dd[i].des0 = ctrl; + + i++; + } + + /* Set DMA derscriptor base address */ + pSDMMC->DBADDR = (uint32_t) &psdif_dev->mci_dma_dd[0]; +} + +/** + * @brief Sets the transfer block size + * @param pSDMMC : Pointer to IP_SDMMC_001_Type structure + * @param blk_size : Block Size value + * @return None + */ +void IP_SDMMC_SetBlockSize(IP_SDMMC_001_Type *pSDMMC, uint32_t blk_size) +{ + /* set block size and byte count */ + pSDMMC->BLKSIZ = blk_size; + pSDMMC->BYTCNT = blk_size; +} diff --git a/bsp/xplorer4330/libraries/lpc_ip/sdmmc_001.h b/bsp/xplorer4330/libraries/lpc_ip/sdmmc_001.h new file mode 100644 index 0000000000..70d754c244 --- /dev/null +++ b/bsp/xplorer4330/libraries/lpc_ip/sdmmc_001.h @@ -0,0 +1,408 @@ +/* + * @brief SD/SDIO (MCI) registers and control functions + * + * @note + * Copyright(C) NXP Semiconductors, 2012 + * All rights reserved. + * + * @par + * Software that is described herein is for illustrative purposes only + * which provides customers with programming information regarding the + * LPC products. This software is supplied "AS IS" without any warranties of + * any kind, and NXP Semiconductors and its licensor disclaim any and + * all warranties, express or implied, including all implied warranties of + * merchantability, fitness for a particular purpose and non-infringement of + * intellectual property rights. NXP Semiconductors assumes no responsibility + * or liability for the use of the software, conveys no license or rights under any + * patent, copyright, mask work right, or any other intellectual property rights in + * or to any products. NXP Semiconductors reserves the right to make changes + * in the software without notification. NXP Semiconductors also makes no + * representation or warranty that such application will be suitable for the + * specified use without further testing or modification. + * + * @par + * Permission to use, copy, modify, and distribute this software and its + * documentation is hereby granted, under NXP Semiconductors' and its + * licensor's relevant copyrights in the software, without fee, provided that it + * is used in conjunction with NXP Semiconductors microcontrollers. This + * copyright, permission, and disclaimer notice must appear in all copies of + * this code. + */ + +#ifndef __SDMMC_001_H_ +#define __SDMMC_001_H_ + +#include "sys_config.h" +#include "cmsis.h" + +#ifdef __cplusplus +extern "C" { +#endif + +/** @defgroup IP_SDMMC_001 IP: SDMMC register block and driver + * @ingroup IP_Drivers + * @{ + */ + +/** + * @brief SD/MMC & SDIO register block structure + */ +typedef struct { /*!< SDMMC Structure */ + __IO uint32_t CTRL; /*!< Control Register */ + __IO uint32_t PWREN; /*!< Power Enable Register */ + __IO uint32_t CLKDIV; /*!< Clock Divider Register */ + __IO uint32_t CLKSRC; /*!< SD Clock Source Register */ + __IO uint32_t CLKENA; /*!< Clock Enable Register */ + __IO uint32_t TMOUT; /*!< Timeout Register */ + __IO uint32_t CTYPE; /*!< Card Type Register */ + __IO uint32_t BLKSIZ; /*!< Block Size Register */ + __IO uint32_t BYTCNT; /*!< Byte Count Register */ + __IO uint32_t INTMASK; /*!< Interrupt Mask Register */ + __IO uint32_t CMDARG; /*!< Command Argument Register */ + __IO uint32_t CMD; /*!< Command Register */ + __I uint32_t RESP0; /*!< Response Register 0 */ + __I uint32_t RESP1; /*!< Response Register 1 */ + __I uint32_t RESP2; /*!< Response Register 2 */ + __I uint32_t RESP3; /*!< Response Register 3 */ + __I uint32_t MINTSTS; /*!< Masked Interrupt Status Register */ + __IO uint32_t RINTSTS; /*!< Raw Interrupt Status Register */ + __I uint32_t STATUS; /*!< Status Register */ + __IO uint32_t FIFOTH; /*!< FIFO Threshold Watermark Register */ + __I uint32_t CDETECT; /*!< Card Detect Register */ + __I uint32_t WRTPRT; /*!< Write Protect Register */ + __IO uint32_t GPIO; /*!< General Purpose Input/Output Register */ + __I uint32_t TCBCNT; /*!< Transferred CIU Card Byte Count Register */ + __I uint32_t TBBCNT; /*!< Transferred Host to BIU-FIFO Byte Count Register */ + __IO uint32_t DEBNCE; /*!< Debounce Count Register */ + __IO uint32_t USRID; /*!< User ID Register */ + __I uint32_t VERID; /*!< Version ID Register */ + __I uint32_t RESERVED0; + __IO uint32_t UHS_REG; /*!< UHS-1 Register */ + __IO uint32_t RST_N; /*!< Hardware Reset */ + __I uint32_t RESERVED1; + __IO uint32_t BMOD; /*!< Bus Mode Register */ + __O uint32_t PLDMND; /*!< Poll Demand Register */ + __IO uint32_t DBADDR; /*!< Descriptor List Base Address Register */ + __IO uint32_t IDSTS; /*!< Internal DMAC Status Register */ + __IO uint32_t IDINTEN; /*!< Internal DMAC Interrupt Enable Register */ + __I uint32_t DSCADDR; /*!< Current Host Descriptor Address Register */ + __I uint32_t BUFADDR; /*!< Current Buffer Descriptor Address Register */ +} IP_SDMMC_001_Type; + +/** @brief SDIO DMA descriptor control (des0) register defines + */ +#define MCI_DMADES0_OWN (1UL << 31) /*!< DMA owns descriptor bit */ +#define MCI_DMADES0_CES (1 << 30) /*!< Card Error Summary bit */ +#define MCI_DMADES0_ER (1 << 5) /*!< End of descriptopr ring bit */ +#define MCI_DMADES0_CH (1 << 4) /*!< Second address chained bit */ +#define MCI_DMADES0_FS (1 << 3) /*!< First descriptor bit */ +#define MCI_DMADES0_LD (1 << 2) /*!< Last descriptor bit */ +#define MCI_DMADES0_DIC (1 << 1) /*!< Disable interrupt on completion bit */ + +/** @brief SDIO DMA descriptor size (des1) register defines + */ +#define MCI_DMADES1_BS1(x) (x) /*!< Size of buffer 1 */ +#define MCI_DMADES1_BS2(x) ((x) << 13) /*!< Size of buffer 2 */ +#define MCI_DMADES1_MAXTR 4096 /*!< Max transfer size per buffer */ + +/** @brief SDIO control register defines + */ +#define MCI_CTRL_USE_INT_DMAC (1 << 25) /*!< Use internal DMA */ +#define MCI_CTRL_CARDV_MASK (0x7 << 16) /*!< SD_VOLT[2:0} pins output state mask */ +#define MCI_CTRL_CEATA_INT_EN (1 << 11) /*!< Enable CE-ATA interrupts */ +#define MCI_CTRL_SEND_AS_CCSD (1 << 10) /*!< Send auto-stop */ +#define MCI_CTRL_SEND_CCSD (1 << 9) /*!< Send CCSD */ +#define MCI_CTRL_ABRT_READ_DATA (1 << 8) /*!< Abort read data */ +#define MCI_CTRL_SEND_IRQ_RESP (1 << 7) /*!< Send auto-IRQ response */ +#define MCI_CTRL_READ_WAIT (1 << 6) /*!< Assert read-wait for SDIO */ +#define MCI_CTRL_INT_ENABLE (1 << 4) /*!< Global interrupt enable */ +#define MCI_CTRL_DMA_RESET (1 << 2) /*!< Reset internal DMA */ +#define MCI_CTRL_FIFO_RESET (1 << 1) /*!< Reset data FIFO pointers */ +#define MCI_CTRL_RESET (1 << 0) /*!< Reset controller */ + +/** @brief SDIO Power Enable register defines + */ +#define MCI_POWER_ENABLE 0x1 /*!< Enable slot power signal (SD_POW) */ + +/** @brief SDIO Clock divider register defines + */ +#define MCI_CLOCK_DIVIDER(dn, d2) ((d2) << ((dn) * 8)) /*!< Set cklock divider */ + +/** @brief SDIO Clock source register defines + */ +#define MCI_CLKSRC_CLKDIV0 0 +#define MCI_CLKSRC_CLKDIV1 1 +#define MCI_CLKSRC_CLKDIV2 2 +#define MCI_CLKSRC_CLKDIV3 3 +#define MCI_CLK_SOURCE(clksrc) (clksrc) /*!< Set cklock divider source */ + +/** @brief SDIO Clock Enable register defines + */ +#define MCI_CLKEN_LOW_PWR (1 << 16) /*!< Enable clock idle for slot */ +#define MCI_CLKEN_ENABLE (1 << 0) /*!< Enable slot clock */ + +/** @brief SDIO time-out register defines + */ +#define MCI_TMOUT_DATA(clks) ((clks) << 8) /*!< Data timeout clocks */ +#define MCI_TMOUT_DATA_MSK 0xFFFFFF00 +#define MCI_TMOUT_RESP(clks) ((clks) & 0xFF) /*!< Response timeout clocks */ +#define MCI_TMOUT_RESP_MSK 0xFF + +/** @brief SDIO card-type register defines + */ +#define MCI_CTYPE_8BIT (1 << 16) /*!< Enable 4-bit mode */ +#define MCI_CTYPE_4BIT (1 << 0) /*!< Enable 8-bit mode */ + +/** @brief SDIO Interrupt status & mask register defines + */ +#define MCI_INT_SDIO (1 << 16) /*!< SDIO interrupt */ +#define MCI_INT_EBE (1 << 15) /*!< End-bit error */ +#define MCI_INT_ACD (1 << 14) /*!< Auto command done */ +#define MCI_INT_SBE (1 << 13) /*!< Start bit error */ +#define MCI_INT_HLE (1 << 12) /*!< Hardware locked error */ +#define MCI_INT_FRUN (1 << 11) /*!< FIFO overrun/underrun error */ +#define MCI_INT_HTO (1 << 10) /*!< Host data starvation error */ +#define MCI_INT_DTO (1 << 9) /*!< Data timeout error */ +#define MCI_INT_RTO (1 << 8) /*!< Response timeout error */ +#define MCI_INT_DCRC (1 << 7) /*!< Data CRC error */ +#define MCI_INT_RCRC (1 << 6) /*!< Response CRC error */ +#define MCI_INT_RXDR (1 << 5) /*!< RX data ready */ +#define MCI_INT_TXDR (1 << 4) /*!< TX data needed */ +#define MCI_INT_DATA_OVER (1 << 3) /*!< Data transfer over */ +#define MCI_INT_CMD_DONE (1 << 2) /*!< Command done */ +#define MCI_INT_RESP_ERR (1 << 1) /*!< Command response error */ +#define MCI_INT_CD (1 << 0) /*!< Card detect */ + +/** @brief SDIO Command register defines + */ +#define MCI_CMD_START (1UL << 31) /*!< Start command */ +#define MCI_CMD_VOLT_SWITCH (1 << 28) /*!< Voltage switch bit */ +#define MCI_CMD_BOOT_MODE (1 << 27) /*!< Boot mode */ +#define MCI_CMD_DISABLE_BOOT (1 << 26) /*!< Disable boot */ +#define MCI_CMD_EXPECT_BOOT_ACK (1 << 25) /*!< Expect boot ack */ +#define MCI_CMD_ENABLE_BOOT (1 << 24) /*!< Enable boot */ +#define MCI_CMD_CCS_EXP (1 << 23) /*!< CCS expected */ +#define MCI_CMD_CEATA_RD (1 << 22) /*!< CE-ATA read in progress */ +#define MCI_CMD_UPD_CLK (1 << 21) /*!< Update clock register only */ +#define MCI_CMD_INIT (1 << 15) /*!< Send init sequence */ +#define MCI_CMD_STOP (1 << 14) /*!< Stop/abort command */ +#define MCI_CMD_PRV_DAT_WAIT (1 << 13) /*!< Wait before send */ +#define MCI_CMD_SEND_STOP (1 << 12) /*!< Send auto-stop */ +#define MCI_CMD_STRM_MODE (1 << 11) /*!< Stream transfer mode */ +#define MCI_CMD_DAT_WR (1 << 10) /*!< Read(0)/Write(1) selection */ +#define MCI_CMD_DAT_EXP (1 << 9) /*!< Data expected */ +#define MCI_CMD_RESP_CRC (1 << 8) /*!< Check response CRC */ +#define MCI_CMD_RESP_LONG (1 << 7) /*!< Response length */ +#define MCI_CMD_RESP_EXP (1 << 6) /*!< Response expected */ +#define MCI_CMD_INDX(n) ((n) & 0x1F) + +/** @brief SDIO status register definess + */ +#define MCI_STS_GET_FCNT(x) (((x) >> 17) & 0x1FF) + +/** @brief SDIO FIFO threshold defines + */ +#define MCI_FIFOTH_TX_WM(x) ((x) & 0xFFF) +#define MCI_FIFOTH_RX_WM(x) (((x) & 0xFFF) << 16) +#define MCI_FIFOTH_DMA_MTS_1 (0UL << 28) +#define MCI_FIFOTH_DMA_MTS_4 (1UL << 28) +#define MCI_FIFOTH_DMA_MTS_8 (2UL << 28) +#define MCI_FIFOTH_DMA_MTS_16 (3UL << 28) +#define MCI_FIFOTH_DMA_MTS_32 (4UL << 28) +#define MCI_FIFOTH_DMA_MTS_64 (5UL << 28) +#define MCI_FIFOTH_DMA_MTS_128 (6UL << 28) +#define MCI_FIFOTH_DMA_MTS_256 (7UL << 28) + +/** @brief Bus mode register defines + */ +#define MCI_BMOD_PBL1 (0 << 8) /*!< Burst length = 1 */ +#define MCI_BMOD_PBL4 (1 << 8) /*!< Burst length = 4 */ +#define MCI_BMOD_PBL8 (2 << 8) /*!< Burst length = 8 */ +#define MCI_BMOD_PBL16 (3 << 8) /*!< Burst length = 16 */ +#define MCI_BMOD_PBL32 (4 << 8) /*!< Burst length = 32 */ +#define MCI_BMOD_PBL64 (5 << 8) /*!< Burst length = 64 */ +#define MCI_BMOD_PBL128 (6 << 8) /*!< Burst length = 128 */ +#define MCI_BMOD_PBL256 (7 << 8) /*!< Burst length = 256 */ +#define MCI_BMOD_DE (1 << 7) /*!< Enable internal DMAC */ +#define MCI_BMOD_DSL(len) ((len) << 2) /*!< Descriptor skip length */ +#define MCI_BMOD_FB (1 << 1) /*!< Fixed bursts */ +#define MCI_BMOD_SWR (1 << 0) /*!< Software reset of internal registers */ + +/** @brief Commonly used definitions + */ +#define SD_FIFO_SZ 32 /*!< Size of SDIO FIFOs (32-bit wide) */ + +/** Function prototype for SD interface IRQ callback */ +typedef uint32_t (*MCI_IRQ_CB_FUNC_T)(uint32_t); + +/** Function prototype for SD detect and write protect status check */ +typedef int32_t (*PSCHECK_FUNC_T)(void); + +/** Function prototype for SD slot power enable or slot reset */ +typedef void (*PS_POWER_FUNC_T)(int32_t enable); + +/** @brief SDIO chained DMA descriptor + */ +typedef struct { + volatile uint32_t des0; /*!< Control and status */ + volatile uint32_t des1; /*!< Buffer size(s) */ + volatile uint32_t des2; /*!< Buffer address pointer 1 */ + volatile uint32_t des3; /*!< Buffer address pointer 2 */ +} pSDMMC_DMA_Type; + +/** @brief SDIO device type + */ +typedef struct _sdif_device { + // MCI_IRQ_CB_FUNC_T irq_cb; + pSDMMC_DMA_Type mci_dma_dd[1 + (0x10000 / MCI_DMADES1_MAXTR)]; + // uint32_t sdio_clk_rate; + // uint32_t sdif_slot_clk_rate; + // int32_t clock_enabled; +} sdif_device; + +/** + * @brief Initializes the MCI card controller + * @param pSDMMC Pointer to IP_SDMMC_001_Type structure + * @return None + */ +void IP_SDMMC_Init(IP_SDMMC_001_Type *pSDMMC); + +/** + * @brief Close the MCI + * @param pSDMMC : Pointer to IP_SDMMC_001_Type structure + * @return None + */ +void IP_SDMMC_DeInit(IP_SDMMC_001_Type *pSDMMC); + +/** + * @brief Set block size for transfer + * @param pSDMMC : Pointer to IP_SDMMC_001_Type structure + * @param bytes : block size in bytes + * @return None + */ +void IP_SDMMC_SetBlkSize(IP_SDMMC_001_Type *pSDMMC, uint32_t bytes); + +/** + * @brief Reset card in slot + * @param pSDMMC : Pointer to IP_SDMMC_001_Type structure + * @param reset : Sets SD_RST to passed state + * @return None + * Reset card in slot, must manually de-assert reset after assertion + * (Uses SD_RST pin, set per reset parameter state) + */ +void IP_SDMMC_Reset(IP_SDMMC_001_Type *pSDMMC, int32_t reset); + +/** + * @brief Enable or disable slot power + * @param pSDMMC : Pointer to IP_SDMMC_001_Type structure + * @param enable : !0 to enable, or 0 to disable + * @return None + * Enable or disable slot power, !0 = enable slot power + * (Uses SD_POW pin, set to high or low based on enable parameter state) + */ +void IP_SDMMC_PowerOnOff(IP_SDMMC_001_Type *pSDMMC, int32_t enable); + +/** + * @brief Detect if write protect is enabled + * @param pSDMMC : Pointer to IP_SDMMC_001_Type structure + * @return Returns 1 if card is write protected, otherwise 0 + * Detect if write protect is enabled + * (uses SD_WP pin, returns 1 if card is write protected) + */ +int32_t IP_SDMMC_CardWpOn(IP_SDMMC_001_Type *pSDMMC); + +/** + * @brief Detect if an SD card is inserted + * @param pSDMMC : Pointer to IP_SDMMC_001_Type structure + * @return Returns 0 if a card is detected, otherwise 1 + * Detect if an SD card is inserted + * (uses SD_CD pin, returns 0 on card detect) + */ +int32_t IP_SDMMC_CardNDetect(IP_SDMMC_001_Type *pSDMMC); + +/** + * @brief Function to send command to Card interface unit (CIU) + * @param pSDMMC : Pointer to IP_SDMMC_001_Type structure + * @param cmd : Command with all flags set + * @param arg : Argument for the command + * @return TRUE on times-out, otherwise FALSE + */ +int32_t IP_SDMMC_SendCmd(IP_SDMMC_001_Type *pSDMMC, uint32_t cmd, uint32_t arg); + +/** + * @brief Read the response from the last command + * @param pSDMMC : Pointer to IP_SDMMC_001_Type structure + * @param resp : Pointer to response array to fill + * @return None + */ +void IP_SDMMC_GetResponse(IP_SDMMC_001_Type *pSDMMC, uint32_t *resp); + +/** + * @brief Sets the SD bus clock speed + * @param pSDMMC : Pointer to IP_SDMMC_001_Type structure + * @param clk_rate : Input clock rate into the IP block + * @param speed : Desired clock speed to the card + * @return None + */ +void IP_SDMMC_SetClock(IP_SDMMC_001_Type *pSDMMC, uint32_t clk_rate, uint32_t speed); + +/** + * @brief Function to set card type + * @param pSDMMC : Pointer to IP_SDMMC_001_Type structure + * @param ctype : card type + * @return None + */ +void IP_SDMMC_SetCardType(IP_SDMMC_001_Type *pSDMMC, uint32_t ctype); + +/** + * @brief Function to clear interrupt & FIFOs + * @param pSDMMC : Pointer to IP_SDMMC_001_Type structure + * @return None + */ +void IP_SDMMC_SetClearIntFifo(IP_SDMMC_001_Type *pSDMMC); + +/** + * @brief Returns the raw SD interface interrupt status + * @param pSDMMC : Pointer to IP_SDMMC_001_Type structure + * @return Raw interrupt status of Or'ed values MCI_INT_* + */ +uint32_t IP_SDMMC_GetRawIntStatus(IP_SDMMC_001_Type *pSDMMC); + +/** + * @brief Sets the raw SD interface interrupt status + * @param pSDMMC : Pointer to IP_SDMMC_001_Type structure + * @param iVal : Raw interrupts to set, Or'ed values MCI_INT_* + * @return None + */ +void IP_SDMMC_SetRawIntStatus(IP_SDMMC_001_Type *pSDMMC, uint32_t iVal); + +/** + * @brief Sets the SD interface interrupt mask + * @param pSDMMC : Pointer to IP_SDMMC_001_Type structure + * @param iVal : Interrupts to enable, Or'ed values MCI_INT_* + * @return None + */ +void IP_SDMMC_SetIntMask(IP_SDMMC_001_Type *pSDMMC, uint32_t iVal); + +/** + * @brief Setup DMA descriptors + * @param pSDMMC : Pointer to IP_SDMMC_001_Type structure + * @param psdif_dev : SD interface device + * @param addr : Address of buffer (source or destination) + * @param size : size of buffer in bytes (64K max) + * @return None + */ +void IP_SDMMC_DmaSetup(IP_SDMMC_001_Type *pSDMMC, sdif_device *psdif_dev, uint32_t addr, uint32_t size); + +/* Sets the transfer block size */ +void IP_SDMMC_SetBlockSize(IP_SDMMC_001_Type *pSDMMC, uint32_t blk_size); + +/** + * @} + */ + +#ifdef __cplusplus +} +#endif + +#endif /* __SDMMC_001_H_ */ diff --git a/bsp/xplorer4330/libraries/lpc_ip/sgpio_001.h b/bsp/xplorer4330/libraries/lpc_ip/sgpio_001.h new file mode 100644 index 0000000000..f84b8e0c08 --- /dev/null +++ b/bsp/xplorer4330/libraries/lpc_ip/sgpio_001.h @@ -0,0 +1,107 @@ +/* + * @brief Serial GPIO registers and control functions + * + * @note + * Copyright(C) NXP Semiconductors, 2012 + * All rights reserved. + * + * @par + * Software that is described herein is for illustrative purposes only + * which provides customers with programming information regarding the + * LPC products. This software is supplied "AS IS" without any warranties of + * any kind, and NXP Semiconductors and its licensor disclaim any and + * all warranties, express or implied, including all implied warranties of + * merchantability, fitness for a particular purpose and non-infringement of + * intellectual property rights. NXP Semiconductors assumes no responsibility + * or liability for the use of the software, conveys no license or rights under any + * patent, copyright, mask work right, or any other intellectual property rights in + * or to any products. NXP Semiconductors reserves the right to make changes + * in the software without notification. NXP Semiconductors also makes no + * representation or warranty that such application will be suitable for the + * specified use without further testing or modification. + * + * @par + * Permission to use, copy, modify, and distribute this software and its + * documentation is hereby granted, under NXP Semiconductors' and its + * licensor's relevant copyrights in the software, without fee, provided that it + * is used in conjunction with NXP Semiconductors microcontrollers. This + * copyright, permission, and disclaimer notice must appear in all copies of + * this code. + */ + +#ifndef __SGPIO_001_H_ +#define __SGPIO_001_H_ + +#include "sys_config.h" +#include "cmsis.h" + +#ifdef __cplusplus +extern "C" { +#endif + +/** @defgroup IP_SGPIO_001 IP: SGPIO register block and driver + * @ingroup IP_Drivers + * Serial GPIO + * @{ + */ + +/** + * @brief Serial GPIO register block structure + */ +typedef struct { /*!< SGPIO Structure */ + __IO uint32_t OUT_MUX_CFG[16]; /*!< Pin multiplexer configurationregisters. */ + __IO uint32_t SGPIO_MUX_CFG[16]; /*!< SGPIO multiplexer configuration registers. */ + __IO uint32_t SLICE_MUX_CFG[16]; /*!< Slice multiplexer configuration registers. */ + __IO uint32_t REG[16]; /*!< Slice data registers. Eachtime COUNT0 reaches 0x0 the register shifts loading bit 31 withdata captured from DIN(n). DOUT(n) is set to REG(0) */ + __IO uint32_t REG_SS[16]; /*!< Slice data shadow registers. Each time POSreaches 0x0 the contents of REG_SS is exchanged with the contentof REG */ + __IO uint32_t PRESET[16]; /*!< Reload valueof COUNT0, loaded when COUNT0 reaches 0x0 */ + __IO uint32_t COUNT[16]; /*!< Down counter, counts down each clock cycle. */ + __IO uint32_t POS[16]; /*!< Each time COUNT0 reaches 0x0 */ + __IO uint32_t MASK_A; /*!< Mask for pattern match function of slice A */ + __IO uint32_t MASK_H; /*!< Mask for pattern match function of slice H */ + __IO uint32_t MASK_I; /*!< Mask for pattern match function of slice I */ + __IO uint32_t MASK_P; /*!< Mask for pattern match function of slice P */ + __I uint32_t GPIO_INREG; /*!< GPIO input status register */ + __IO uint32_t GPIO_OUTREG; /*!< GPIO output control register */ + __IO uint32_t GPIO_OENREG; /*!< GPIO OE control register */ + __IO uint32_t CTRL_ENABLED; /*!< Enables the slice COUNT counter */ + __IO uint32_t CTRL_DISABLED; /*!< Disables the slice COUNT counter */ + __I uint32_t RESERVED0[823]; + __O uint32_t CLR_EN_0; /*!< Shift clock interrupt clear mask */ + __O uint32_t SET_EN_0; /*!< Shift clock interrupt set mask */ + __I uint32_t ENABLE_0; /*!< Shift clock interrupt enable */ + __I uint32_t STATUS_0; /*!< Shift clock interrupt status */ + __O uint32_t CTR_STATUS_0; /*!< Shift clock interrupt clear status */ + __O uint32_t SET_STATUS_0; /*!< Shift clock interrupt set status */ + __I uint32_t RESERVED1[2]; + __O uint32_t CLR_EN_1; /*!< Capture clock interrupt clear mask */ + __O uint32_t SET_EN_1; /*!< Capture clock interrupt set mask */ + __I uint32_t ENABLE_1; /*!< Capture clock interrupt enable */ + __I uint32_t STATUS_1; /*!< Capture clock interrupt status */ + __O uint32_t CTR_STATUS_1; /*!< Capture clock interrupt clear status */ + __O uint32_t SET_STATUS_1; /*!< Capture clock interrupt set status */ + __I uint32_t RESERVED2[2]; + __O uint32_t CLR_EN_2; /*!< Pattern match interrupt clear mask */ + __O uint32_t SET_EN_2; /*!< Pattern match interrupt set mask */ + __I uint32_t ENABLE_2; /*!< Pattern match interrupt enable */ + __I uint32_t STATUS_2; /*!< Pattern match interrupt status */ + __O uint32_t CTR_STATUS_2; /*!< Pattern match interrupt clear status */ + __O uint32_t SET_STATUS_2; /*!< Pattern match interrupt set status */ + __I uint32_t RESERVED3[2]; + __O uint32_t CLR_EN_3; /*!< Input interrupt clear mask */ + __O uint32_t SET_EN_3; /*!< Input bit match interrupt set mask */ + __I uint32_t ENABLE_3; /*!< Input bit match interrupt enable */ + __I uint32_t STATUS_3; /*!< Input bit match interrupt status */ + __O uint32_t CTR_STATUS_3; /*!< Input bit match interrupt clear status */ + __O uint32_t SET_STATUS_3; /*!< Shift clock interrupt set status */ +} IP_SGPIO_001_Type; + +/** + * @} + */ + +#ifdef __cplusplus +} +#endif + +#endif /* __SGPIO_001_H_ */ diff --git a/bsp/xplorer4330/libraries/lpc_ip/spi_001.h b/bsp/xplorer4330/libraries/lpc_ip/spi_001.h new file mode 100644 index 0000000000..40395385c1 --- /dev/null +++ b/bsp/xplorer4330/libraries/lpc_ip/spi_001.h @@ -0,0 +1,67 @@ +/* + * @brief SPI registers and control functions + * + * @note + * Copyright(C) NXP Semiconductors, 2012 + * All rights reserved. + * + * @par + * Software that is described herein is for illustrative purposes only + * which provides customers with programming information regarding the + * LPC products. This software is supplied "AS IS" without any warranties of + * any kind, and NXP Semiconductors and its licensor disclaim any and + * all warranties, express or implied, including all implied warranties of + * merchantability, fitness for a particular purpose and non-infringement of + * intellectual property rights. NXP Semiconductors assumes no responsibility + * or liability for the use of the software, conveys no license or rights under any + * patent, copyright, mask work right, or any other intellectual property rights in + * or to any products. NXP Semiconductors reserves the right to make changes + * in the software without notification. NXP Semiconductors also makes no + * representation or warranty that such application will be suitable for the + * specified use without further testing or modification. + * + * @par + * Permission to use, copy, modify, and distribute this software and its + * documentation is hereby granted, under NXP Semiconductors' and its + * licensor's relevant copyrights in the software, without fee, provided that it + * is used in conjunction with NXP Semiconductors microcontrollers. This + * copyright, permission, and disclaimer notice must appear in all copies of + * this code. + */ + +#ifndef __SPI_001_H_ +#define __SPI_001_H_ + +#include "sys_config.h" +#include "cmsis.h" + +#ifdef __cplusplus +extern "C" { +#endif + +/** @defgroup IP_SPI_001 IP: SPI register block and driver + * @ingroup IP_Drivers + * @{ + */ + +/** + * @brief SPI register block structure + */ +typedef struct { /*!< SPI Structure */ + __IO uint32_t CR; /*!< SPI Control Register. This register controls the operation of the SPI. */ + __I uint32_t SR; /*!< SPI Status Register. This register shows the status of the SPI. */ + __IO uint32_t DR; /*!< SPI Data Register. This bi-directional register provides the transmit and receive data for the SPI. Transmit data is provided to the SPI0 by writing to this register. Data received by the SPI0 can be read from this register. */ + __IO uint32_t CCR; /*!< SPI Clock Counter Register. This register controls the frequency of a master's SCK0. */ + __I uint32_t RESERVED0[3]; + __IO uint32_t INT; /*!< SPI Interrupt Flag. This register contains the interrupt flag for the SPI interface. */ +} IP_SPI_001_Type; + +/** + * @} + */ + +#ifdef __cplusplus +} +#endif + +#endif /* __SPI_001_H_ */ diff --git a/bsp/xplorer4330/libraries/lpc_ip/spifi_001.h b/bsp/xplorer4330/libraries/lpc_ip/spifi_001.h new file mode 100644 index 0000000000..b1a057ccc7 --- /dev/null +++ b/bsp/xplorer4330/libraries/lpc_ip/spifi_001.h @@ -0,0 +1,226 @@ +/* +* @brief SPIFI registers and control functions +* +* @note +* Copyright(C) NXP Semiconductors, 2012 +* All rights reserved. +* +* @par +* Software that is described herein is for illustrative purposes only +* which provides customers with programming information regarding the +* LPC products. This software is supplied "AS IS" without any warranties of +* any kind, and NXP Semiconductors and its licensor disclaim any and +* all warranties, express or implied, including all implied warranties of +* merchantability, fitness for a particular purpose and non-infringement of +* intellectual property rights. NXP Semiconductors assumes no responsibility +* or liability for the use of the software, conveys no license or rights under any +* patent, copyright, mask work right, or any other intellectual property rights in +* or to any products. NXP Semiconductors reserves the right to make changes +* in the software without notification. NXP Semiconductors also makes no +* representation or warranty that such application will be suitable for the +* specified use without further testing or modification. +* +* @par +* Permission to use, copy, modify, and distribute this software and its +* documentation is hereby granted, under NXP Semiconductors' and its +* licensor's relevant copyrights in the software, without fee, provided that it +* is used in conjunction with NXP Semiconductors microcontrollers. This +* copyright, permission, and disclaimer notice must appear in all copies of +* this code. +*/ + +#ifndef __SPIFI_001_H_ +#define __SPIFI_001_H_ + +#include "sys_config.h" +#include "cmsis.h" +#include "spifi_rom_api.h" + +#ifdef __cplusplus +extern "C" { +#endif + +// FIXME this file needs work and better explanations + +/** @defgroup IP_SPIFI_001 IP: SPIFI register block and driver + * @ingroup IP_Drivers + * @{ + */ + +extern void cancel_mem_mode(SPIFIobj *obj); +extern void (*set_mem_mode) (SPIFIobj *obj); + + /* mid level functions */ +extern int32_t checkAd(SPIFIobj *obj, SPIFIopers *opers); +extern int32_t setProt(SPIFIobj *obj, SPIFIopers *opers, char *change, + char *saveProt); +extern int32_t check_block(SPIFIobj *obj, char *source, SPIFIopers *opers, + uint32_t check_program); +extern int32_t send_erase_cmd(SPIFIobj *obj, uint8_t op, uint32_t addr); +extern uint32_t ck_erase(SPIFIobj *obj, uint32_t *addr, uint32_t length); +extern int32_t prog_block(SPIFIobj *obj, char *source, SPIFIopers *opers, + uint32_t *left_in_page); +extern uint32_t ck_prog(SPIFIobj *obj, char *source, char *dest, uint32_t length); + + /* low level functions */ +extern void setSize(SPIFIobj *obj, int32_t value); +extern int32_t setDev(SPIFIobj *obj, uint32_t opts, uint32_t mem_cmd, + uint32_t prog_cmd); +extern uint32_t cmd(uc op, uc addrLen, uc intLen, uint16_t len); +extern uint32_t readAd(SPIFIobj *obj, uint32_t cmd, uint32_t addr); +extern void send04(SPIFIobj *obj, uc op, uc len, uint32_t value); +extern void wren_sendAd(SPIFIobj *obj, uint32_t cmd, uint32_t addr, uint32_t value); +extern int32_t write_stat(SPIFIobj *obj, uc len, uint16_t value); +extern int32_t wait_busy(SPIFIobj *obj, uc prog_or_erase); + +/** + * @brief This call sends the standardized Read JEDEC ID command to the + * attached serial Flash device. If it responds, it is set up for reading + * in ARM memory space. + * @param obj : Pointer to uninitialized SPIFIobj structure + * @param csHigh : Value that is one less than the minimum number of clock + * cycles with the CS pin high, that the SPIFI should maintain between + * commands. Compute this from the SPIFI clock period and the minimum high + * time of CS from the serial flash data sheet: + * csHigh = ceiling( min CS high / SPIFI clock period) - 1 + * @param options : contains bits controlling the SPIFI behavior. See @ref IP_SPIFI_OPTIONS + * @param mhz : should be the serial clock divided by 1000000. + * @return A return value of zero indicates success. Non-zero error codes indicate various error states. + */ +STATIC INLINE int32_t IP_SPIFI_Init(SPIFIobj *obj, uint32_t csHigh, uint32_t options, uint32_t mhz) +{ + return spifi_init(obj, csHigh, options, mhz); +} + +/** + * @brief This call programs opers.length bytes in the serial flash. An + * IP_SPIFI_Program call with source equal to opers.dest and opers.options + * not including S_FORCE_ERASE can be used to protect or unprotect sectors + * depending on the value of opers.protect. + * @param obj : Pointer to initialized SPIFIobj structure (from IP_SPIFI_Init) + * @param source : is the address of the data to be programmed + * @param opers : specifies programming and erasing options + * @return A return value of zero indicates success. Non-zero error codes + * indicate various error states. + */ +STATIC INLINE int32_t IP_SPIFI_Program(SPIFIobj *obj, char *source, SPIFIopers *opers) +{ + return spifi_program(obj, source, opers); +} + +/** + * @brief This call erases opers.length bytes in the serial flash. + * @param obj : Pointer to initialized SPIFIobj structure (from IP_SPIFI_Init) + * @param opers : specifies erasing options + * @return A return value of zero indicates success. Non-zero error codes + * indicate various error states. + */ +STATIC INLINE int32_t IP_SPIFI_Erase(SPIFIobj *obj, SPIFIopers *opers) +{ + return spifi_erase(obj, opers); +} + +/** + * @brief : This function disables the memory mapping of the external QSPI flash. + * @param obj : Pointer to initialized SPIFIobj structure (from IP_SPIFI_Init) + * @return No return value + */ +STATIC INLINE void IP_SPIFI_CancelMemMode(SPIFIobj *obj) +{ + cancel_mem_mode(obj); +} + +STATIC INLINE void IP_SPIFI_SetMemMode(SPIFIobj *obj) +{ + set_mem_mode(obj); +} + + /* mid level functions */ +STATIC INLINE int32_t IP_SPIFI_checkAd(SPIFIobj *obj, SPIFIopers *opers) +{ + return checkAd(obj, opers); +} + +STATIC INLINE int32_t IP_SPIFI_setProt(SPIFIobj *obj, SPIFIopers *opers, char *change, char *saveProt) +{ + return setProt(obj, opers, change, saveProt); +} + +STATIC INLINE int32_t IP_SPIFI_CheckBlock(SPIFIobj *obj, char *source, SPIFIopers *opers, + uint32_t check_program) +{ + return check_block(obj, source, opers, check_program); +} + +STATIC INLINE int32_t IP_SPIFI_SendEraseCmd(SPIFIobj *obj, uint8_t op, uint32_t addr) +{ + return send_erase_cmd(obj, op, addr); +} + +STATIC INLINE uint32_t IP_SPIFI_CkErase(SPIFIobj *obj, uint32_t *addr, uint32_t length) +{ + return ck_erase(obj, addr, length); +} + +STATIC INLINE int32_t IP_SPIFI_ProgBlock(SPIFIobj *obj, char *source, SPIFIopers *opers, + uint32_t *left_in_page) +{ + return prog_block(obj, source, opers, left_in_page); +} + +STATIC INLINE uint32_t IP_SPIFI_CkProg(SPIFIobj *obj, char *source, char *dest, uint32_t length) +{ + return ck_prog(obj, source, dest, length); +} + + /* low level functions */ +STATIC INLINE void IP_SPIFI_SetSize(SPIFIobj *obj, int32_t value) +{ + setSize(obj, value); +} + +STATIC INLINE int32_t IP_SPIFI_SetDev(SPIFIobj *obj, uint32_t opts, uint32_t mem_cmd, + uint32_t prog_cmd) +{ + return setDev(obj, opts, mem_cmd, prog_cmd); +} + +STATIC INLINE uint32_t IP_SPIFI_Cmd(uc op, uc addrLen, uc intLen, uint16_t len) +{ + return cmd(op, addrLen, intLen, len); +} + +STATIC INLINE uint32_t IP_SPIFI_ReadAd(SPIFIobj *obj, uint32_t cmd, uint32_t addr) +{ + return readAd(obj, cmd, addr); +} + +STATIC INLINE void IP_SPIFI_Send04(SPIFIobj *obj, uc op, uc len, uint32_t value) +{ + send04(obj, op, len, value); +} + +STATIC INLINE void IP_SPIFI_WrEnSendAd(SPIFIobj *obj, uint32_t cmd, uint32_t addr, uint32_t value) +{ + wren_sendAd(obj, cmd, addr, value); +} + +STATIC INLINE int32_t IP_SPIFI_WriteStat(SPIFIobj *obj, uc len, uint16_t value) +{ + return write_stat(obj, len, value); +} + +STATIC INLINE int32_t IP_SPIFI_WaitBusy(SPIFIobj *obj, uc prog_or_erase) +{ + return wait_busy(obj, prog_or_erase); +} + +/** + * @} + */ + +#ifdef __cplusplus +} +#endif + +#endif /* __SPIFI_001_H_ */ diff --git a/bsp/xplorer4330/libraries/lpc_ip/ssp_001.c b/bsp/xplorer4330/libraries/lpc_ip/ssp_001.c new file mode 100644 index 0000000000..1d9873f901 --- /dev/null +++ b/bsp/xplorer4330/libraries/lpc_ip/ssp_001.c @@ -0,0 +1,163 @@ +/* + * @brief SSP Registers and control functions + * + * @note + * Copyright(C) NXP Semiconductors, 2012 + * All rights reserved. + * + * @par + * Software that is described herein is for illustrative purposes only + * which provides customers with programming information regarding the + * LPC products. This software is supplied "AS IS" without any warranties of + * any kind, and NXP Semiconductors and its licensor disclaim any and + * all warranties, express or implied, including all implied warranties of + * merchantability, fitness for a particular purpose and non-infringement of + * intellectual property rights. NXP Semiconductors assumes no responsibility + * or liability for the use of the software, conveys no license or rights under any + * patent, copyright, mask work right, or any other intellectual property rights in + * or to any products. NXP Semiconductors reserves the right to make changes + * in the software without notification. NXP Semiconductors also makes no + * representation or warranty that such application will be suitable for the + * specified use without further testing or modification. + * + * @par + * Permission to use, copy, modify, and distribute this software and its + * documentation is hereby granted, under NXP Semiconductors' and its + * licensor's relevant copyrights in the software, without fee, provided that it + * is used in conjunction with NXP Semiconductors microcontrollers. This + * copyright, permission, and disclaimer notice must appear in all copies of + * this code. + */ + +#include "ssp_001.h" + +/***************************************************************************** + * Private types/enumerations/variables + ****************************************************************************/ + +/***************************************************************************** + * Public types/enumerations/variables + ****************************************************************************/ + +/***************************************************************************** + * Private functions + ****************************************************************************/ + +/***************************************************************************** + * Public functions + ****************************************************************************/ + +/*Set up output clocks per bit for SSP bus*/ +void IP_SSP_Set_ClockRate(IP_SSP_001_Type *pSSP, uint32_t clk_rate, uint32_t prescale) +{ + pSSP->CR0 &= ~(SSP_CR0_SCR(0xFF)); + pSSP->CR0 |= SSP_CR0_SCR(clk_rate); + pSSP->CPSR = prescale; +} + +/* Set up the SSP frame format */ +void IP_SSP_Set_Format(IP_SSP_001_Type *pSSP, uint32_t bits, uint32_t frameFormat, uint32_t clockFormat) +{ + pSSP->CR0 = (pSSP->CR0 & ~0xFF) | bits | frameFormat | clockFormat; +} + +/* Set the SSP working as master or slave mode */ +void IP_SSP_Set_Mode(IP_SSP_001_Type *pSSP, uint32_t mode) +{ + pSSP->CR1 = (pSSP->CR1 & ~(1 << 2)) | mode; +} + +/* Disable SSP operation */ +void IP_SSP_DeInit(IP_SSP_001_Type *pSSP) +{ + pSSP->CR1 &= (~SSP_CR1_SSP_EN) & SSP_CR1_BITMASK; +} + +/* Enable/Disable SSP operation */ +void IP_SSP_Cmd(IP_SSP_001_Type *pSSP, FunctionalState NewState) +{ + if (NewState == ENABLE) { + pSSP->CR1 |= SSP_CR1_SSP_EN; + } + else { + pSSP->CR1 &= (~SSP_CR1_SSP_EN) & SSP_CR1_BITMASK; + } +} + +/* Send SSP 16-bit data */ +void IP_SSP_SendFrame(IP_SSP_001_Type *pSSP, uint16_t tx_data) +{ + pSSP->DR = SSP_DR_BITMASK(tx_data); +} + +/* Get received SSP data */ +uint16_t IP_SSP_ReceiveFrame(IP_SSP_001_Type *pSSP) +{ + return (uint16_t) (SSP_DR_BITMASK(pSSP->DR)); +} + +/* Enable/Disable loopback mode */ +void IP_SSP_LoopBackCmd(IP_SSP_001_Type *pSSP, FunctionalState NewState) +{ + + if (NewState == ENABLE) { + pSSP->CR1 |= SSP_CR1_LBM_EN; + } + else { + pSSP->CR1 &= (~SSP_CR1_LBM_EN) & SSP_CR1_BITMASK; + } +} + +/* Get the raw interrupt status */ +IntStatus IP_SSP_GetRawIntStatus(IP_SSP_001_Type *pSSP, SSP_Raw_Int_Status_Type RawInt) +{ + return (pSSP->RIS & RawInt) ? SET : RESET; +} + +/* Get the masked interrupt status */ +uint32_t IP_SSP_GetIntStatus(IP_SSP_001_Type *pSSP) +{ + return pSSP->MIS; +} + +/* Clear the corresponding interrupt condition(s) in the SSP controller */ +void IP_SSP_ClearIntPending(IP_SSP_001_Type *pSSP, SSP_Int_Clear_Type IntClear) +{ + pSSP->ICR = IntClear; +} + +/* Get the current status of SSP controller */ +FlagStatus IP_SSP_GetStatus(IP_SSP_001_Type *pSSP, SSP_Status_Type Stat) +{ + return (pSSP->SR & Stat) ? SET : RESET; +} + +/* Get the number of bits transferred in each frame */ +uint8_t IP_SSP_GetDataSize(IP_SSP_001_Type *pSSP) +{ + return SSP_CR0_DSS(pSSP->CR0); +} + +/* Enable/Disable interrupt for the SSP */ +void IP_SSP_Int_Enable(IP_SSP_001_Type *pSSP, SSP_Int_Mask_Type IntType, FunctionalState NewState) +{ + if (NewState == ENABLE) { + pSSP->IMSC |= IntType; + } + else { + pSSP->IMSC &= (~IntType); + } +} + +/* Enable/Disable DMA for SSP */ +void IP_SSP_DMA_Cmd(IP_SSP_001_Type *pSSP, SSP_DMA_Type ssp_dma_t, FunctionalState NewState) +{ +#if !defined(CHIP_LPC111X_CXX) && !defined(CHIP_LPC11UXX) + if (NewState == ENABLE) { + pSSP->DMACR |= ssp_dma_t; + } + else { + pSSP->DMACR &= (~ssp_dma_t); + } +#endif +} diff --git a/bsp/xplorer4330/libraries/lpc_ip/ssp_001.h b/bsp/xplorer4330/libraries/lpc_ip/ssp_001.h new file mode 100644 index 0000000000..ed9573e380 --- /dev/null +++ b/bsp/xplorer4330/libraries/lpc_ip/ssp_001.h @@ -0,0 +1,351 @@ +/* + * @brief SSP Registers and control functions + * + * @note + * Copyright(C) NXP Semiconductors, 2012 + * All rights reserved. + * + * @par + * Software that is described herein is for illustrative purposes only + * which provides customers with programming information regarding the + * LPC products. This software is supplied "AS IS" without any warranties of + * any kind, and NXP Semiconductors and its licensor disclaim any and + * all warranties, express or implied, including all implied warranties of + * merchantability, fitness for a particular purpose and non-infringement of + * intellectual property rights. NXP Semiconductors assumes no responsibility + * or liability for the use of the software, conveys no license or rights under any + * patent, copyright, mask work right, or any other intellectual property rights in + * or to any products. NXP Semiconductors reserves the right to make changes + * in the software without notification. NXP Semiconductors also makes no + * representation or warranty that such application will be suitable for the + * specified use without further testing or modification. + * + * @par + * Permission to use, copy, modify, and distribute this software and its + * documentation is hereby granted, under NXP Semiconductors' and its + * licensor's relevant copyrights in the software, without fee, provided that it + * is used in conjunction with NXP Semiconductors microcontrollers. This + * copyright, permission, and disclaimer notice must appear in all copies of + * this code. + */ + +#ifndef __SSP_001_H_ +#define __SSP_001_H_ + +#include "sys_config.h" +#include "cmsis.h" + +#ifdef __cplusplus +extern "C" { +#endif + +/** @defgroup IP_SSP_001 IP: SSP register block and driver + * @ingroup IP_Drivers + * @{ + */ + +/** + * @brief SSP register block structure + */ +typedef struct { /*!< SSPn Structure */ + __IO uint32_t CR0; /*!< Control Register 0. Selects the serial clock rate, bus type, and data size. */ + __IO uint32_t CR1; /*!< Control Register 1. Selects master/slave and other modes. */ + __IO uint32_t DR; /*!< Data Register. Writes fill the transmit FIFO, and reads empty the receive FIFO. */ + __I uint32_t SR; /*!< Status Register */ + __IO uint32_t CPSR; /*!< Clock Prescale Register */ + __IO uint32_t IMSC; /*!< Interrupt Mask Set and Clear Register */ + __I uint32_t RIS; /*!< Raw Interrupt Status Register */ + __I uint32_t MIS; /*!< Masked Interrupt Status Register */ + __O uint32_t ICR; /*!< SSPICR Interrupt Clear Register */ +#if !defined(CHIP_LPC111X_CXX) && !defined(CHIP_LPC11UXX) /* no DMA on LPC11xx or LPC11Uxx */ + __IO uint32_t DMACR; /*!< SSPn DMA control register */ +#endif +} IP_SSP_001_Type; + +/** + * Macro defines for CR0 register + */ + +/** SSP data size select, must be 4 bits to 16 bits */ +#define SSP_CR0_DSS(n) ((uint32_t) ((n) & 0xF)) +/** SSP control 0 Motorola SPI mode */ +#define SSP_CR0_FRF_SPI ((uint32_t) (0 << 4)) +/** SSP control 0 TI synchronous serial mode */ +#define SSP_CR0_FRF_TI ((uint32_t) (1 << 4)) +/** SSP control 0 National Micro-wire mode */ +#define SSP_CR0_FRF_MICROWIRE ((uint32_t) (2 << 4)) +/** SPI clock polarity bit (used in SPI mode only), (1) = maintains the + bus clock high between frames, (0) = low */ +#define SSP_CR0_CPOL_LO ((uint32_t) (0)) +#define SSP_CR0_CPOL_HI ((uint32_t) (1 << 6)) +/** SPI clock out phase bit (used in SPI mode only), (1) = captures data + on the second clock transition of the frame, (0) = first */ +#define SSP_CR0_CPHA_FIRST ((uint32_t) (0)) +#define SSP_CR0_CPHA_SECOND ((uint32_t) (1 << 7)) +/** SSP serial clock rate value load macro, divider rate is + PERIPH_CLK / (cpsr * (SCR + 1)) */ +#define SSP_CR0_SCR(n) ((uint32_t) ((n & 0xFF) << 8)) +/** SSP CR0 bit mask */ +#define SSP_CR0_BITMASK ((uint32_t) (0xFFFF)) +/** SSP CR0 bit mask */ +#define SSP_CR0_BITMASK ((uint32_t) (0xFFFF)) +/** SSP serial clock rate value load macro, divider rate is + PERIPH_CLK / (cpsr * (SCR + 1)) */ +#define SSP_CR0_SCR(n) ((uint32_t) ((n & 0xFF) << 8)) + +/** + * Macro defines for CR1 register + */ + +/** SSP control 1 loopback mode enable bit */ +#define SSP_CR1_LBM_EN ((uint32_t) (1 << 0)) +/** SSP control 1 enable bit */ +#define SSP_CR1_SSP_EN ((uint32_t) (1 << 1)) +/** SSP control 1 slave enable */ +#define SSP_CR1_SLAVE_EN ((uint32_t) (1 << 2)) +#define SSP_CR1_MASTER_EN ((uint32_t) (0)) +/** SSP control 1 slave out disable bit, disables transmit line in slave + mode */ +#define SSP_CR1_SO_DISABLE ((uint32_t) (1 << 3)) +/** SSP CR1 bit mask */ +#define SSP_CR1_BITMASK ((uint32_t) (0x0F)) + +/** SSP CPSR bit mask */ +#define SSP_CPSR_BITMASK ((uint32_t) (0xFF)) +/** + * Macro defines for DR register + */ + +/** SSP data bit mask */ +#define SSP_DR_BITMASK(n) ((n) & 0xFFFF) + +/** + * Macro defines for SR register + */ + +/** SSP SR bit mask */ +#define SSP_SR_BITMASK ((uint32_t) (0x1F)) + +/** ICR bit mask */ +#define SSP_ICR_BITMASK ((uint32_t) (0x03)) + +/** + * @brief SSP Type of Status + */ +typedef enum { + SSP_STAT_TFE = ((uint32_t)(1 << 0)),/**< TX FIFO Empty */ + SSP_STAT_TNF = ((uint32_t)(1 << 1)),/**< TX FIFO not full */ + SSP_STAT_RNE = ((uint32_t)(1 << 2)),/**< RX FIFO not empty */ + SSP_STAT_RFF = ((uint32_t)(1 << 3)),/**< RX FIFO full */ + SSP_STAT_BSY = ((uint32_t)(1 << 4)),/**< SSP Busy */ +} SSP_Status_Type; + +/** + * @brief SSP Type of Interrupt Mask + */ +typedef enum { + SSP_RORIM = ((uint32_t)(1 << 0)), /**< Overun */ + SSP_RTIM = ((uint32_t)(1 << 1)),/**< TimeOut */ + SSP_RXIM = ((uint32_t)(1 << 2)),/**< Rx FIFO is at least half full */ + SSP_TXIM = ((uint32_t)(1 << 3)),/**< Tx FIFO is at least half empty */ + SSP_INT_MASK_BITMASK = ((uint32_t)(0xF)), +} SSP_Int_Mask_Type; + +/** + * @brief SSP Type of Mask Interrupt Status + */ +typedef enum { + SSP_RORMIS = ((uint32_t)(1 << 0)), /**< Overun */ + SSP_RTMIS = ((uint32_t)(1 << 1)), /**< TimeOut */ + SSP_RXMIS = ((uint32_t)(1 << 2)), /**< Rx FIFO is at least half full */ + SSP_TXMIS = ((uint32_t)(1 << 3)), /**< Tx FIFO is at least half empty */ + SSP_MASK_INT_STAT_BITMASK = ((uint32_t)(0xF)), +} SSP_Mask_Int_Status_Type; + +/** + * @brief SSP Type of Raw Interrupt Status + */ +typedef enum { + SSP_RORRIS = ((uint32_t)(1 << 0)), /**< Overun */ + SSP_RTRIS = ((uint32_t)(1 << 1)), /**< TimeOut */ + SSP_RXRIS = ((uint32_t)(1 << 2)), /**< Rx FIFO is at least half full */ + SSP_TXRIS = ((uint32_t)(1 << 3)), /**< Tx FIFO is at least half empty */ + SSP_RAW_INT_STAT_BITMASK = ((uint32_t)(0xF)), +} SSP_Raw_Int_Status_Type; + +typedef enum { + SSP_RORIC = 0x0, + SSP_RTIC = 0x1, + SSP_INT_CLEAR_BITMASK = 0x3, +} SSP_Int_Clear_Type; + +typedef enum SSP_DMA_Type { + SSP_DMA_RX = (1u), /**< DMA RX Enable */ + SSP_DMA_TX = (1u << 1), /**< DMA TX Enable */ +} SSP_DMA_Type; + +/** + * @brief Disable SSP operation + * @param pSSP : The base of SSP peripheral on the chip + * @return Nothing + * The SSP controller is disabled + */ +void IP_SSP_DeInit(IP_SSP_001_Type *pSSP); + +/** + * @brief Enable/Disable SSP operation + * @param pSSP : The base of SSP peripheral on the chip + * @param NewState : New state, ENABLE or DISABLE + * @return Nothing + */ +void IP_SSP_Cmd(IP_SSP_001_Type *pSSP, FunctionalState NewState); + +/** + * @brief Enable/Disable loopback mode + * @param pSSP : The base of SSP peripheral on the chip + * @param NewState : New state, ENABLE or DISABLE + * @return Nothing + * Serial input is taken from the serial output (MOSI or MISO) rather + * than the serial input pin + */ +void IP_SSP_LoopBackCmd(IP_SSP_001_Type *pSSP, FunctionalState NewState); + +/** + * @brief Get the current status of SSP controller + * @param pSSP : The base of SSP peripheral on the chip + * @param Stat : Type of status, should be : + * - SSP_STAT_TFE + * - SSP_STAT_TNF + * - SSP_STAT_RNE + * - SSP_STAT_RFF + * - SSP_STAT_BSY + * @return SSP controller status, SET or RESET + */ +FlagStatus IP_SSP_GetStatus(IP_SSP_001_Type *pSSP, SSP_Status_Type Stat); + +/** + * @brief Get the masked interrupt status + * @param pSSP : The base of SSP peripheral on the chip + * @return SSP Masked Interrupt Status Register value + * The return value contains a 1 for each interrupt condition that is asserted and enabled (masked) + */ +uint32_t IP_SSP_GetIntStatus(IP_SSP_001_Type *pSSP); + +/** + * @brief Get the raw interrupt status + * @param pSSP : The base of SSP peripheral on the chip + * @param RawInt : Interrupt condition to be get status, shoud be : + * - SSP_RORRIS + * - SSP_RTRIS + * - SSP_RXRIS + * - SSP_TXRIS + * @return Raw interrupt status corresponding to interrupt condition , SET or RESET + * Get the status of each interrupt condition ,regardless of whether or not the interrupt is enabled + */ +IntStatus IP_SSP_GetRawIntStatus(IP_SSP_001_Type *pSSP, SSP_Raw_Int_Status_Type RawInt); + +/** + * @brief Get the number of bits transferred in each frame + * @param pSSP : The base of SSP peripheral on the chip + * @return the number of bits transferred in each frame minus one + * The return value is 0x03 -> 0xF corresponding to 4bit -> 16bit transfer + */ +uint8_t IP_SSP_GetDataSize(IP_SSP_001_Type *pSSP); + +/** + * @brief Clear the corresponding interrupt condition(s) in the SSP controller + * @param pSSP : The base of SSP peripheral on the chip + * @param IntClear: Type of cleared interrupt, should be : + * - SSP_RORIC + * - SSP_RTIC + * @return Nothing + * Software can clear one or more interrupt condition(s) in the SSP controller + */ +void IP_SSP_ClearIntPending(IP_SSP_001_Type *pSSP, SSP_Int_Clear_Type IntClear); + +/** + * @brief Enable/Disable interrupt for the SSP + * @param pSSP : The base of SSP peripheral on the chip + * @param IntType : Type of interrupt condition to be enable/disable, should be : + * - SSP_RORIM + * - SSP_RTIM + * - SSP_RXIM + * - SSP_TXIM + * @param NewState : New state, ENABLE or DISABLE + * @return Nothing + */ +void IP_SSP_Int_Enable(IP_SSP_001_Type *pSSP, SSP_Int_Mask_Type IntType, FunctionalState NewState); + +/** + * @brief Get received SSP data + * @param pSSP : The base of SSP peripheral on the chip + * @return SSP 16-bit data received + */ +uint16_t IP_SSP_ReceiveFrame(IP_SSP_001_Type *pSSP); + +/** + * @brief Send SSP 16-bit data + * @param pSSP : The base of SSP peripheral on the chip + * @param tx_data : SSP 16-bit data to be transmited + * @return Nothing + */ +void IP_SSP_SendFrame(IP_SSP_001_Type *pSSP, uint16_t tx_data); + +/** + * @brief Set up output clocks per bit for SSP bus + * @param pSSP : The base of SSP peripheral on the chip + * @param clk_rate fs: The number of prescaler-output clocks per bit on the bus, minus one + * @param prescale : The factor by which the Prescaler divides the SSP peripheral clock PCLK + * @return Nothing + * The bit frequency is PCLK / (prescale x[clk_rate+1]) + */ +void IP_SSP_Set_ClockRate(IP_SSP_001_Type *pSSP, uint32_t clk_rate, uint32_t prescale); + +/** + * @brief Set up the SSP frame format + * @param pSSP : The base of SSP peripheral on the chip + * @param bits : The number of bits transferred in each frame, should be SSP_BITS_4 to SSP_BITS_16 + * @param frameFormat : Frame format, should be : + * - SSP_FRAMEFORMAT_SPI + * - SSP_FRAMEFORMAT_TI + * - SSP_FRAMEFORMAT_MICROWIRE + * @param clockFormat : Select Clock polarity and Clock phase, should be : + * - SSP_CLOCK_CPHA0_CPOL0 + * - SSP_CLOCK_CPHA0_CPOL1 + * - SSP_CLOCK_CPHA1_CPOL0 + * - SSP_CLOCK_CPHA1_CPOL1 + * @return Nothing + * Note: The clockFormat is only used in SPI mode + */ +void IP_SSP_Set_Format(IP_SSP_001_Type *pSSP, uint32_t bits, uint32_t frameFormat, uint32_t clockFormat); + +/** + * @brief Set the SSP working as master or slave mode + * @param pSSP : The base of SSP peripheral on the chip + * @param mode : Operating mode, should be + * - SSP_MODE_MASTER + * - SSP_MODE_SLAVE + * @return Nothing + */ +void IP_SSP_Set_Mode(IP_SSP_001_Type *pSSP, uint32_t mode); + +/** + * @brief Enable/Disable DMA for SSP + * @param pSSP : The base of SSP peripheral on the chip + * @param ssp_dma_t : DMA set up for transmit/receive SSP, should be + * - SSP_DMA_RX + * - SSP_DMA_TX + * @param NewState : New state, ENABLE or DISABLE + * @return Nothing + */ +void IP_SSP_DMA_Cmd(IP_SSP_001_Type *pSSP, SSP_DMA_Type ssp_dma_t, FunctionalState NewState); + +/** + * @} + */ + +#ifdef __cplusplus +} +#endif + +#endif /* __SSP_001_H_ */ diff --git a/bsp/xplorer4330/libraries/lpc_ip/timer_001.c b/bsp/xplorer4330/libraries/lpc_ip/timer_001.c new file mode 100644 index 0000000000..9af7ca15aa --- /dev/null +++ b/bsp/xplorer4330/libraries/lpc_ip/timer_001.c @@ -0,0 +1,83 @@ +/* + * @brief 32-bit Timer/PWM control functions + * + * @note + * Copyright(C) NXP Semiconductors, 2012 + * All rights reserved. + * + * @par + * Software that is described herein is for illustrative purposes only + * which provides customers with programming information regarding the + * LPC products. This software is supplied "AS IS" without any warranties of + * any kind, and NXP Semiconductors and its licensor disclaim any and + * all warranties, express or implied, including all implied warranties of + * merchantability, fitness for a particular purpose and non-infringement of + * intellectual property rights. NXP Semiconductors assumes no responsibility + * or liability for the use of the software, conveys no license or rights under any + * patent, copyright, mask work right, or any other intellectual property rights in + * or to any products. NXP Semiconductors reserves the right to make changes + * in the software without notification. NXP Semiconductors also makes no + * representation or warranty that such application will be suitable for the + * specified use without further testing or modification. + * + * @par + * Permission to use, copy, modify, and distribute this software and its + * documentation is hereby granted, under NXP Semiconductors' and its + * licensor's relevant copyrights in the software, without fee, provided that it + * is used in conjunction with NXP Semiconductors microcontrollers. This + * copyright, permission, and disclaimer notice must appear in all copies of + * this code. + */ + +#include "timer_001.h" + +/***************************************************************************** + * Private types/enumerations/variables + ****************************************************************************/ + +/***************************************************************************** + * Public types/enumerations/variables + ****************************************************************************/ + +/***************************************************************************** + * Private functions + ****************************************************************************/ + +/***************************************************************************** + * Public functions + ****************************************************************************/ + +/* Resets the timer terminal and prescale counts to 0 */ +void IP_TIMER_Reset(IP_TIMER_001_Type *timer) +{ + uint32_t reg; + + /* Disable timer, set terminal count to non-0 */ + reg = timer->TCR; + timer->TCR = 0; + timer->TC = 1; + + /* Reset timer counter */ + timer->TCR = TIMER_RESET; + + /* Wait for terminal count to clear */ + while (timer->TC != 0) {} + + /* Restore timer state */ + timer->TCR = reg; +} + +/* Sets external match control (MATn.matchnum) pin control */ +void IP_TIMER_ExtMatchControlSet(IP_TIMER_001_Type *timer, int8_t initial_state, + IP_TIMER_PIN_MATCH_STATE_Type matchState, int8_t matchnum) +{ + timer->EMR = (((uint32_t) initial_state) << matchnum) | + (((uint32_t) matchState) << (4 + (matchnum * 2))); +} + +/* Sets timer count source and edge with the selected passed from CapSrc */ +void IP_TIMER_SetTimerClockSrc(IP_TIMER_001_Type *timer, + IP_TIMER_CAP_SRC_STATE_Type capSrc, int8_t capnum) +{ + timer->CTCR = (uint32_t) capSrc | ((uint32_t) capnum) << 2; +} diff --git a/bsp/xplorer4330/libraries/lpc_ip/timer_001.h b/bsp/xplorer4330/libraries/lpc_ip/timer_001.h new file mode 100644 index 0000000000..ccf18de65d --- /dev/null +++ b/bsp/xplorer4330/libraries/lpc_ip/timer_001.h @@ -0,0 +1,426 @@ +/* + * @brief 32-bit Timer/PWM registers and control functions + * + * @note + * Copyright(C) NXP Semiconductors, 2012 + * All rights reserved. + * + * @par + * Software that is described herein is for illustrative purposes only + * which provides customers with programming information regarding the + * LPC products. This software is supplied "AS IS" without any warranties of + * any kind, and NXP Semiconductors and its licensor disclaim any and + * all warranties, express or implied, including all implied warranties of + * merchantability, fitness for a particular purpose and non-infringement of + * intellectual property rights. NXP Semiconductors assumes no responsibility + * or liability for the use of the software, conveys no license or rights under any + * patent, copyright, mask work right, or any other intellectual property rights in + * or to any products. NXP Semiconductors reserves the right to make changes + * in the software without notification. NXP Semiconductors also makes no + * representation or warranty that such application will be suitable for the + * specified use without further testing or modification. + * + * @par + * Permission to use, copy, modify, and distribute this software and its + * documentation is hereby granted, under NXP Semiconductors' and its + * licensor's relevant copyrights in the software, without fee, provided that it + * is used in conjunction with NXP Semiconductors microcontrollers. This + * copyright, permission, and disclaimer notice must appear in all copies of + * this code. + */ + +#ifndef __TIMER_001_H_ +#define __TIMER_001_H_ + +#include "sys_config.h" +#include "cmsis.h" + +#ifdef __cplusplus +extern "C" { +#endif + +/** @defgroup IP_TIMER_001 IP: Timer register block and driver + * @ingroup IP_Drivers + * @{ + */ + +/** + * @brief 32-bit Standard timer register block structure + */ +typedef struct { /*!< TIMERn Structure */ + __IO uint32_t IR; /*!< Interrupt Register. The IR can be written to clear interrupts. The IR can be read to identify which of eight possible interrupt sources are pending. */ + __IO uint32_t TCR; /*!< Timer Control Register. The TCR is used to control the Timer Counter functions. The Timer Counter can be disabled or reset through the TCR. */ + __IO uint32_t TC; /*!< Timer Counter. The 32 bit TC is incremented every PR+1 cycles of PCLK. The TC is controlled through the TCR. */ + __IO uint32_t PR; /*!< Prescale Register. The Prescale Counter (below) is equal to this value, the next clock increments the TC and clears the PC. */ + __IO uint32_t PC; /*!< Prescale Counter. The 32 bit PC is a counter which is incremented to the value stored in PR. When the value in PR is reached, the TC is incremented and the PC is cleared. The PC is observable and controllable through the bus interface. */ + __IO uint32_t MCR; /*!< Match Control Register. The MCR is used to control if an interrupt is generated and if the TC is reset when a Match occurs. */ + __IO uint32_t MR[4]; /*!< Match Register. MR can be enabled through the MCR to reset the TC, stop both the TC and PC, and/or generate an interrupt every time MR matches the TC. */ + __IO uint32_t CCR; /*!< Capture Control Register. The CCR controls which edges of the capture inputs are used to load the Capture Registers and whether or not an interrupt is generated when a capture takes place. */ + __IO uint32_t CR[4]; /*!< Capture Register. CR is loaded with the value of TC when there is an event on the CAPn.0 input. */ + __IO uint32_t EMR; /*!< External Match Register. The EMR controls the external match pins MATn.0-3 (MAT0.0-3 and MAT1.0-3 respectively). */ + __I uint32_t RESERVED0[12]; + __IO uint32_t CTCR; /*!< Count Control Register. The CTCR selects between Timer and Counter mode, and in Counter mode selects the signal and edge(s) for counting. */ +} IP_TIMER_001_Type; + +/** Macro to clear interrupt pending */ +#define TIMER_IR_CLR(n) _BIT(n) + +/** Macro for getting a timer match interrupt bit */ +#define TIMER_MATCH_INT(n) (_BIT((n) & 0x0F)) +/** Macro for getting a capture event interrupt bit */ +#define TIMER_CAP_INT(n) (_BIT((((n) & 0x0F) + 4))) + +/** Timer/counter enable bit */ +#define TIMER_ENABLE ((uint32_t) (1 << 0)) +/** Timer/counter reset bit */ +#define TIMER_RESET ((uint32_t) (1 << 1)) + +/** Bit location for interrupt on MRx match, n = 0 to 3 */ +#define TIMER_INT_ON_MATCH(n) (_BIT(((n) * 3))) +/** Bit location for reset on MRx match, n = 0 to 3 */ +#define TIMER_RESET_ON_MATCH(n) (_BIT((((n) * 3) + 1))) +/** Bit location for stop on MRx match, n = 0 to 3 */ +#define TIMER_STOP_ON_MATCH(n) (_BIT((((n) * 3) + 2))) + +/** Bit location for CAP.n on CRx rising edge, n = 0 to 3 */ +#define TIMER_CAP_RISING(n) (_BIT(((n) * 3))) +/** Bit location for CAP.n on CRx falling edge, n = 0 to 3 */ +#define TIMER_CAP_FALLING(n) (_BIT((((n) * 3) + 1))) +/** Bit location for CAP.n on CRx interrupt enable, n = 0 to 3 */ +#define TIMER_INT_ON_CAP(n) (_BIT((((n) * 3) + 2))) + +/** + * @brief Determine if a match interrupt is pending + * @param timer : Pointer to timer IP register address + * @param matchnum : Match interrupt number to check + * @return false if the interrupt is not pending, otherwise true + * Determine if the match interrupt for the passed timer and match + * counter is pending. + */ +STATIC INLINE bool IP_TIMER_MatchPending(IP_TIMER_001_Type *timer, int8_t matchnum) +{ + return (bool) ((timer->IR & TIMER_MATCH_INT(matchnum)) != 0); +} + +/** + * @brief Determine if a capture interrupt is pending + * @param timer : Pointer to timer IP register address + * @param capnum : Capture interrupt number to check + * @return false if the interrupt is not pending, otherwise true + * Determine if the capture interrupt for the passed capture pin is + * pending. + */ +STATIC INLINE bool IP_TIMER_CapturePending(IP_TIMER_001_Type *timer, int8_t capnum) +{ + return (bool) ((timer->IR & TIMER_CAP_INT(capnum)) != 0); +} + +/** + * @brief Clears a (pending) match interrupt + * @param timer : Pointer to timer IP register address + * @param matchnum : Match interrupt number to clear + * @return Nothing + * Clears a pending timer match interrupt. + */ +STATIC INLINE void IP_TIMER_ClearMatch(IP_TIMER_001_Type *timer, int8_t matchnum) +{ + timer->IR = TIMER_IR_CLR(matchnum); +} + +/** + * @brief Clears a (pending) capture interrupt + * @param timer : Pointer to timer IP register address + * @param capnum : Capture interrupt number to clear + * @return Nothing + * Clears a pending timer capture interrupt. + */ +STATIC INLINE void IP_TIMER_ClearCapture(IP_TIMER_001_Type *timer, int8_t capnum) +{ + timer->IR = (0x10 << capnum); +} + +/** + * @brief Enables the timer (starts count) + * @param timer : Pointer to timer IP register address + * @return Nothing + * Enables the timer to start counting. + */ +STATIC INLINE void IP_TIMER_Enable(IP_TIMER_001_Type *timer) +{ + timer->TCR |= TIMER_ENABLE; +} + +/** + * @brief Disables the timer (stops count) + * @param timer : Pointer to timer IP register address + * @return Nothing + * Disables the timer to stop counting. + */ +STATIC INLINE void IP_TIMER_Disable(IP_TIMER_001_Type *timer) +{ + timer->TCR &= ~TIMER_ENABLE; +} + +/** + * @brief Returns the current timer count + * @param timer : Pointer to timer IP register address + * @return Current timer terminal count value + * Returns the current timer terminal count. + */ +STATIC INLINE uint32_t IP_TIMER_ReadCount(IP_TIMER_001_Type *timer) +{ + return timer->TC; +} + +/** + * @brief Returns the current prescale count + * @param timer : Pointer to timer IP register address + * @return Current timer prescale count value + * Returns the current prescale count. + */ +STATIC INLINE uint32_t IP_TIMER_ReadPrescale(IP_TIMER_001_Type *timer) +{ + return timer->PC; +} + +/** + * @brief Sets the prescaler value + * @param timer : Pointer to timer IP register address + * @param prescale : Prescale value to set the prescale register to + * @return Nothing + * Sets the prescale count value. + */ +STATIC INLINE void IP_TIMER_PrescaleSet(IP_TIMER_001_Type *timer, uint32_t prescale) +{ + timer->PR = prescale; +} + +/** + * @brief Sets a timer match value + * @param timer : Pointer to timer IP register address + * @param matchnum : Match timer to set match count for + * @param matchval : Match value for the selected match count + * @return Nothing + * Sets ones of the timer match values. + */ +STATIC INLINE void IP_TIMER_SetMatch(IP_TIMER_001_Type *timer, int8_t matchnum, uint32_t matchval) +{ + timer->MR[matchnum] = matchval; +} + +/** + * @brief Reads a capture register + * @param timer : Pointer to timer IP register address + * @param capnum : Capture register to read + * @return The selected capture register value + * Returns the selected capture register value. + */ +STATIC INLINE uint32_t IP_TIMER_ReadCapture(IP_TIMER_001_Type *timer, int8_t capnum) +{ + return timer->CR[capnum]; +} + +/** + * @brief Resets the timer terminal and prescale counts to 0 + * @param timer : Pointer to timer IP register address + * @return Nothing + */ +void IP_TIMER_Reset(IP_TIMER_001_Type *timer); + +/** + * @brief Enables a match interrupt that fires when the terminal count + * matches the match counter value. + * @param timer : Pointer to timer IP register address + * @param matchnum : Match timer, 0 to 3 + * @return Nothing + */ +STATIC INLINE void IP_TIMER_MatchEnableInt(IP_TIMER_001_Type *timer, int8_t matchnum) +{ + timer->MCR |= TIMER_INT_ON_MATCH(matchnum); +} + +/** + * @brief Disables a match interrupt for a match counter. + * @param timer : Pointer to timer IP register address + * @param matchnum : Match timer, 0 to 3 + * @return Nothing + */ +STATIC INLINE void IP_TIMER_MatchDisableInt(IP_TIMER_001_Type *timer, int8_t matchnum) +{ + timer->MCR &= ~TIMER_INT_ON_MATCH(matchnum); +} + +/** + * @brief For the specific match counter, enables reset of the terminal count register when a match occurs + * @param timer : Pointer to timer IP register address + * @param matchnum : Match timer, 0 to 3 + * @return Nothing + */ +STATIC INLINE void IP_TIMER_ResetOnMatchEnable(IP_TIMER_001_Type *timer, int8_t matchnum) +{ + timer->MCR |= TIMER_RESET_ON_MATCH(matchnum); +} + +/** + * @brief For the specific match counter, disables reset of the terminal count register when a match occurs + * @param timer : Pointer to timer IP register address + * @param matchnum : Match timer, 0 to 3 + * @return Nothing + */ +STATIC INLINE void IP_TIMER_ResetOnMatchDisable(IP_TIMER_001_Type *timer, int8_t matchnum) +{ + timer->MCR &= ~TIMER_RESET_ON_MATCH(matchnum); +} + +/** + * @brief Enable a match timer to stop the terminal count when a + * match count equals the terminal count. + * @param timer : Pointer to timer IP register address + * @param matchnum : Match timer, 0 to 3 + * @return Nothing + */ +STATIC INLINE void IP_TIMER_StopOnMatchEnable(IP_TIMER_001_Type *timer, int8_t matchnum) +{ + timer->MCR |= TIMER_STOP_ON_MATCH(matchnum); +} + +/** + * @brief Disable stop on match for a match timer. Disables a match timer + * to stop the terminal count when a match count equals the terminal count. + * @param timer : Pointer to timer IP register address + * @param matchnum : Match timer, 0 to 3 + * @return Nothing + */ +STATIC INLINE void IP_TIMER_StopOnMatchDisable(IP_TIMER_001_Type *timer, int8_t matchnum) +{ + timer->MCR &= ~TIMER_STOP_ON_MATCH(matchnum); +} + +/** + * @brief Enables capture on on rising edge of selected CAP signal for the + * selected capture register, enables the selected CAPn.capnum signal to load + * the capture register with the terminal coount on a rising edge. + * @param timer : Pointer to timer IP register address + * @param capnum : Capture signal/register to use + * @return Nothing + */ +STATIC INLINE void IP_TIMER_CaptureRisingEdgeEnable(IP_TIMER_001_Type *timer, int8_t capnum) +{ + timer->CCR |= TIMER_CAP_RISING(capnum); +} + +/** + * @brief Disables capture on on rising edge of selected CAP signal. For the + * selected capture register, disables the selected CAPn.capnum signal to load + * the capture register with the terminal coount on a rising edge. + * @param timer : Pointer to timer IP register address + * @param capnum : Capture signal/register to use + * @return Nothing + */ +STATIC INLINE void IP_TIMER_CaptureRisingEdgeDisable(IP_TIMER_001_Type *timer, int8_t capnum) +{ + timer->CCR &= ~TIMER_CAP_RISING(capnum); +} + +/** + * @brief Enables capture on on falling edge of selected CAP signal. For the + * selected capture register, enables the selected CAPn.capnum signal to load + * the capture register with the terminal coount on a falling edge. + * @param timer : Pointer to timer IP register address + * @param capnum : Capture signal/register to use + * @return Nothing + */ +STATIC INLINE void IP_TIMER_CaptureFallingEdgeEnable(IP_TIMER_001_Type *timer, int8_t capnum) +{ + timer->CCR |= TIMER_CAP_FALLING(capnum); +} + +/** + * @brief Disables capture on on falling edge of selected CAP signal. For the + * selected capture register, disables the selected CAPn.capnum signal to load + * the capture register with the terminal coount on a falling edge. + * @param timer : Pointer to timer IP register address + * @param capnum : Capture signal/register to use + * @return Nothing + */ +STATIC INLINE void IP_TIMER_CaptureFallingEdgeDisable(IP_TIMER_001_Type *timer, int8_t capnum) +{ + timer->CCR &= ~TIMER_CAP_FALLING(capnum); +} + +/** + * @brief Enables interrupt on capture of selected CAP signal. For the + * selected capture register, an interrupt will be generated when the enabled + * rising or falling edge on CAPn.capnum is detected. + * @param timer : Pointer to timer IP register address + * @param capnum : Capture signal/register to use + * @return Nothing + */ +STATIC INLINE void IP_TIMER_CaptureEnableInt(IP_TIMER_001_Type *timer, int8_t capnum) +{ + timer->CCR |= TIMER_INT_ON_CAP(capnum); +} + +/** + * @brief Disables interrupt on capture of selected CAP signal + * @param timer : Pointer to timer IP register address + * @param capnum : Capture signal/register to use + * @return Nothing + */ +STATIC INLINE void IP_TIMER_CaptureDisableInt(IP_TIMER_001_Type *timer, int8_t capnum) +{ + timer->CCR &= ~TIMER_INT_ON_CAP(capnum); +} + +/** + * @brief Standard timer initial match pin state and change state + */ +typedef enum { + TIMER_EXTMATCH_DO_NOTHING = 0, /*!< Timer match state does nothing on match pin */ + TIMER_EXTMATCH_CLEAR = 1, /*!< Timer match state sets match pin low */ + TIMER_EXTMATCH_SET = 2, /*!< Timer match state sets match pin high */ + TIMER_EXTMATCH_TOGGLE = 3 /*!< Timer match state toggles match pin */ +} IP_TIMER_PIN_MATCH_STATE_Type; + +/** + * @brief Sets external match control (MATn.matchnum) pin control + * @param timer : Pointer to timer IP register address + * @param initial_state : Initial state of the pin, high(1) or low(0) + * @param matchState : Selects the match state for the pin + * @param matchnum : MATn.matchnum signal to use + * @return Nothing + * For the pin selected with matchnum, sets the function of the pin that occurs on + * a terminal count match for the match count. + */ +void IP_TIMER_ExtMatchControlSet(IP_TIMER_001_Type *timer, int8_t initial_state, + IP_TIMER_PIN_MATCH_STATE_Type matchState, int8_t matchnum); + +/** + * @brief Standard timer clock and edge for count source + */ +typedef enum { + TIMER_CAPSRC_RISING_PCLK = 0, /*!< Timer ticks on PCLK rising edge */ + TIMER_CAPSRC_RISING_CAPN = 1, /*!< Timer ticks on CAPn.x rising edge */ + TIMER_CAPSRC_FALLING_CAPN = 2, /*!< Timer ticks on CAPn.x falling edge */ + TIMER_CAPSRC_BOTH_CAPN = 3 /*!< Timer ticks on CAPn.x both edges */ +} IP_TIMER_CAP_SRC_STATE_Type; + +/** + * @brief Sets timer count source and edge with the selected passed from CapSrc + * @param timer : Pointer to timer IP register address + * @param capSrc : timer clock source and edge + * @param capnum : CAPn.capnum pin to use (if used) + * @return Nothing + * If CapSrc selected a CAPn pin, select the specific CAPn pin with the capnum value. + */ +void IP_TIMER_SetCountClockSrc(IP_TIMER_001_Type *timer, + IP_TIMER_CAP_SRC_STATE_Type capSrc, int8_t capnum); +/** + * @} + */ + +#ifdef __cplusplus +} +#endif + +#endif /* __TIMER_001_H_ */ diff --git a/bsp/xplorer4330/libraries/lpc_ip/usart_001.c b/bsp/xplorer4330/libraries/lpc_ip/usart_001.c new file mode 100644 index 0000000000..f7333acfd5 --- /dev/null +++ b/bsp/xplorer4330/libraries/lpc_ip/usart_001.c @@ -0,0 +1,516 @@ +/* + * @brief usart registers and control functions + * + * @note + * Copyright(C) NXP Semiconductors, 2012 + * All rights reserved. + * + * @par + * Software that is described herein is for illustrative purposes only + * which provides customers with programming information regarding the + * LPC products. This software is supplied "AS IS" without any warranties of + * any kind, and NXP Semiconductors and its licensor disclaim any and + * all warranties, express or implied, including all implied warranties of + * merchantability, fitness for a particular purpose and non-infringement of + * intellectual property rights. NXP Semiconductors assumes no responsibility + * or liability for the use of the software, conveys no license or rights under any + * patent, copyright, mask work right, or any other intellectual property rights in + * or to any products. NXP Semiconductors reserves the right to make changes + * in the software without notification. NXP Semiconductors also makes no + * representation or warranty that such application will be suitable for the + * specified use without further testing or modification. + * + * @par + * Permission to use, copy, modify, and distribute this software and its + * documentation is hereby granted, under NXP Semiconductors' and its + * licensor's relevant copyrights in the software, without fee, provided that it + * is used in conjunction with NXP Semiconductors microcontrollers. This + * copyright, permission, and disclaimer notice must appear in all copies of + * this code. + */ + +#include "usart_001.h" + +/***************************************************************************** + * Private types/enumerations/variables + ****************************************************************************/ + +/***************************************************************************** + * Public types/enumerations/variables + ****************************************************************************/ + +/***************************************************************************** + * Private functions + ****************************************************************************/ + +/***************************************************************************** + * Public functions + ****************************************************************************/ + +/* Initializes the UARTx peripheral according to the specified parameters in + the UART_ConfigStruct */ +void IP_UART_Init(IP_USART_001_Type *LPC_UART, UART_ID_Type UARTPort) +{ + volatile uint32_t tmp; + /* FIFOs are empty */ + LPC_UART->FCR = ( UART_FCR_FIFO_EN | UART_FCR_RX_RS | UART_FCR_TX_RS); + /* Disable FIFO */ + // LPC_UART->FCR = 0; + /* Dummy reading */ + while (LPC_UART->LSR & UART_LSR_RDR) { + tmp = LPC_UART->RBR; + } +#if defined(CHIP_LPC177X_8X) || defined(CHIP_LPC18XX) || defined(CHIP_LPC43XX) + switch (UARTPort) { +#if defined(CHIP_LPC177X_8X) + case 4: +#else + case 0: + case 2: + case 3: +#endif + LPC_UART->TER2 = UART_TER2_TXEN; + /* Wait for current transmit complete */ + while (!(LPC_UART->LSR & UART_LSR_THRE)) {} + /* Disable Tx */ + LPC_UART->TER2 = 0; + break; + + default: + break; + } +#else + LPC_UART->TER1 = UART_TER1_TXEN; + /* Wait for current transmit complete */ + while (!(LPC_UART->LSR & UART_LSR_THRE)) {} + /* Disable Tx */ + LPC_UART->TER1 = 0; +#endif + /* Disable interrupt */ + LPC_UART->IER = 0; + /* Set LCR to default state */ + LPC_UART->LCR = 0; + /* Set ACR to default state */ + LPC_UART->ACR = 0; +#if defined(CHIP_LPC175X_6X) || defined(CHIP_LPC177X_8X) + if ((UARTPort == 1) || (UARTPort == 4)) { + /* Set RS485 control to default state */ + LPC_UART->RS485CTRL = 0; + /* Set RS485 delay timer to default state */ + LPC_UART->RS485DLY = 0; + /* Set RS485 addr match to default state */ + LPC_UART->RS485ADRMATCH = 0; + } +#else + /* Set RS485 control to default state */ + LPC_UART->RS485CTRL = 0; + /* Set RS485 delay timer to default state */ + LPC_UART->RS485DLY = 0; + /* Set RS485 addr match to default state */ + LPC_UART->RS485ADRMATCH = 0; +#endif + +#if defined(CHIP_LPC175X_6X) || defined(CHIP_LPC177X_8X) || defined(CHIP_LPC18XX) || defined(CHIP_LPC43XX) + if (UARTPort == 1) { +#endif + /* Set Modem Control to default state */ + LPC_UART->MCR = 0; + /*Dummy Reading to Clear Status */ + tmp = LPC_UART->MSR; +#if defined(CHIP_LPC175X_6X) || defined(CHIP_LPC177X_8X) || defined(CHIP_LPC18XX) || defined(CHIP_LPC43XX) +} + +#endif + + /* Dummy reading */ + tmp = LPC_UART->LSR; + /* Set Line Control register ---------------------------- */ + // LPC_UART->LCR = UART_DATABIT_8 | /* Default: 8N1 */ + // UART_STOPBIT_1 | + // UART_PARITY_NONE; + LPC_UART->FDR = 0x10; /* No fractional divider */ +} + +/* De-initializes the UARTx peripheral registers to their default reset values */ +void IP_UART_DeInit(IP_USART_001_Type *LPC_UART, UART_ID_Type UARTPort) +{ + /* For debug mode */ + + IP_UART_TxCmd(LPC_UART, UARTPort, DISABLE); + + switch (UARTPort) { + default: + break; + } +} + +/* Determines best dividers to get a target clock rate */ +Status IP_UART_SetBaud(IP_USART_001_Type *LPC_UART, uint32_t baudrate, uint32_t uClk) +{ + Status errorStatus = ERROR; + + uint32_t d, m, bestd, bestm, tmp; + uint64_t best_divisor, divisor; + uint32_t current_error, best_error; + uint32_t recalcbaud; + + /* In the Uart IP block, baud rate is calculated using FDR and DLL-DLM registers + * The formula is : + * BaudRate= uClk * (mulFracDiv/(mulFracDiv+dividerAddFracDiv) / (16 * (DLL) + * It involves floating point calculations. That's the reason the formulae are adjusted with + * Multiply and divide method.*/ + /* The value of mulFracDiv and dividerAddFracDiv should comply to the following expressions: + * 0 < mulFracDiv <= 15, 0 <= dividerAddFracDiv <= 15 */ + best_error = 0xFFFFFFFF;/* Worst case */ + bestd = 0; + bestm = 0; + best_divisor = 0; + for (m = 1; m <= 15; m++) { + for (d = 0; d < m; d++) { + divisor = ((uint64_t) uClk << 28) * m / (baudrate * (m + d)); + current_error = divisor & 0xFFFFFFFF; + + tmp = divisor >> 32; + + /* Adjust error */ + if (current_error > ((uint32_t) 1 << 31)) { + current_error = -current_error; + tmp++; + } + + if (( tmp < 1) || ( tmp > 65536) ) {/* Out of range */ + continue; + } + + if ( current_error < best_error) { + best_error = current_error; + best_divisor = tmp; + bestd = d; + bestm = m; + if (best_error == 0) { + break; + } + } + } /* end of inner for loop */ + + if (best_error == 0) { + break; + } + } /* end of outer for loop */ + + if (best_divisor == 0) { + return ERROR; /* can not find best match */ + + } + recalcbaud = (uClk >> 4) * bestm / (best_divisor * (bestm + bestd)); + + /* reuse best_error to evaluate baud error */ + if (baudrate > recalcbaud) { + best_error = baudrate - recalcbaud; + } + else {best_error = recalcbaud - baudrate; } + + best_error = best_error * 100 / baudrate; + + if (best_error < UART_ACCEPTED_BAUDRATE_ERROR) { + LPC_UART->LCR |= UART_LCR_DLAB_EN; + LPC_UART->DLM = UART_LOAD_DLM(best_divisor); + LPC_UART->DLL = UART_LOAD_DLL(best_divisor); + /* Then reset DLAB bit */ + LPC_UART->LCR &= (~UART_LCR_DLAB_EN) & UART_LCR_BITMASK; + LPC_UART->FDR = (UART_FDR_MULVAL(bestm) \ + | UART_FDR_DIVADDVAL(bestd)) & UART_FDR_BITMASK; + errorStatus = SUCCESS; + } + + return errorStatus; +} + +/* Configure data width, parity mode and stop bits */ +void IP_UART_ConfigData(IP_USART_001_Type *LPC_UART, + UART_DATABIT_Type Databits, + UART_PARITY_Type Parity, + UART_STOPBIT_Type Stopbits) +{ + uint32_t tmp = (LPC_UART->LCR & (UART_LCR_DLAB_EN | UART_LCR_BREAK_EN)) & UART_LCR_BITMASK; + tmp |= (uint32_t) Databits | (uint32_t) Parity | (uint32_t) Stopbits; + LPC_UART->LCR = (uint8_t) (tmp & UART_LCR_BITMASK); +} + +/* UART Send/Recieve functions -------------------------------------------------*/ +/* Transmit a single data through UART peripheral */ +Status IP_UART_SendByte(IP_USART_001_Type *LPC_UART, uint8_t Data) +{ + if (!(LPC_UART->LSR & UART_LSR_THRE)) { + return ERROR; + } + LPC_UART->THR = Data & UART_THR_MASKBIT; + return SUCCESS; +} + +/* Receive a single data from UART peripheral */ +Status IP_UART_ReceiveByte(IP_USART_001_Type *LPC_UART, uint8_t *Data) +{ + if (!(LPC_UART->LSR & UART_LSR_RDR)) { + return ERROR; + } + *Data = (uint8_t) (LPC_UART->RBR & UART_RBR_MASKBIT); + return SUCCESS; +} + +/* Send a block of data via UART peripheral */ +uint32_t IP_UART_Send(IP_USART_001_Type *LPC_UART, uint8_t *txbuf, uint32_t buflen, TRANSFER_BLOCK_Type flag) +{ + uint32_t bToSend, bSent, timeOut; // , fifo_cnt; + uint8_t *pChar = txbuf; + + bToSend = buflen; + + /* blocking mode */ + if (flag == BLOCKING) { + bSent = 0; + while (bToSend) { + timeOut = UART_BLOCKING_TIMEOUT; + /* Wait for THR empty with timeout */ + while (!(IP_UART_SendByte(LPC_UART, *pChar))) { + if (timeOut == 0) { + break; + } + timeOut--; + } + /* Time out! */ + if (timeOut == 0) { + break; + } + pChar++; + bToSend--; + bSent++; + } + } + /* None blocking mode */ + else { + bSent = 0; + while (bToSend) { + if (!(IP_UART_SendByte(LPC_UART, *pChar))) { + break; + } + pChar++; + bToSend--; + bSent++; + } + } + return bSent; +} + +/* Receive a block of data via UART peripheral */ +uint32_t IP_UART_Receive(IP_USART_001_Type *LPC_UART, uint8_t *rxbuf, uint32_t buflen, TRANSFER_BLOCK_Type flag) +{ + uint32_t bToRecv, bRecv, timeOut; + uint8_t *pChar = rxbuf; + + bToRecv = buflen; + + /* Blocking mode */ + if (flag == BLOCKING) { + bRecv = 0; + while (bToRecv) { + timeOut = UART_BLOCKING_TIMEOUT; + while (!(IP_UART_ReceiveByte(LPC_UART, pChar))) { + if (timeOut == 0) { + break; + } + timeOut--; + } + /* Time out! */ + if (timeOut == 0) { + break; + } + pChar++; + bToRecv--; + bRecv++; + } + } + /* None blocking mode */ + else { + bRecv = 0; + while (bToRecv) { + if (!(IP_UART_ReceiveByte(LPC_UART, pChar))) { + break; + } + else { + pChar++; + bRecv++; + bToRecv--; + } + } + } + return bRecv; +} + +/* Enable or disable specified UART interrupt */ +void IP_UART_IntConfig(IP_USART_001_Type *LPC_UART, UART_INT_Type UARTIntCfg, FunctionalState NewState) +{ + uint32_t tmp = 0; + + switch (UARTIntCfg) { + case UART_INTCFG_RBR: + tmp = UART_IER_RBRINT_EN; + break; + + case UART_INTCFG_THRE: + tmp = UART_IER_THREINT_EN; + break; + + case UART_INTCFG_RLS: + tmp = UART_IER_RLSINT_EN; + break; + + case UART_INTCFG_MS: + tmp = UART_IER_MSINT_EN; + break; + + case UART_INTCFG_CTS: + tmp = UART_IER_CTSINT_EN; + break; + + case UART_INTCFG_ABEO: + tmp = UART_IER_ABEOINT_EN; + break; + + case UART_INTCFG_ABTO: + tmp = UART_IER_ABTOINT_EN; + break; + } + + if (NewState == ENABLE) { + LPC_UART->IER |= tmp; + } + else { + + LPC_UART->IER &= (~tmp) & UART_IER_BITMASK; + + } +} + +/* Get Source Interrupt */ +uint32_t IP_UART_IntGetStatus(IP_USART_001_Type *LPC_UART) +{ + return (LPC_UART->IIR) & UART_IIR_BITMASK; +} + +/* Force BREAK character on UART line, output pin UARTx TXD is forced to logic 0 */ +void IP_UART_ForceBreak(IP_USART_001_Type *LPC_UART) +{ + LPC_UART->LCR |= UART_LCR_BREAK_EN; +} + +/* Get current value of Line Status register in UART peripheral */ +uint8_t IP_UART_GetLineStatus(IP_USART_001_Type *LPC_UART) +{ + return (LPC_UART->LSR) & UART_LSR_BITMASK; +} + +/* Check whether if UART is busy or not */ +FlagStatus IP_UART_CheckBusy(IP_USART_001_Type *LPC_UART) +{ + if (LPC_UART->LSR & UART_LSR_TEMT) { + return RESET; + } + else { + return SET; + } +} + +/* Enable/Disable transmission on UART TxD pin */ +void IP_UART_TxCmd(IP_USART_001_Type *LPC_UART, UART_ID_Type UARTPort, FunctionalState NewState) +{ + if (NewState == ENABLE) { +#if defined(CHIP_LPC177X_8X) || defined(CHIP_LPC18XX) || defined(CHIP_LPC43XX) + switch (UARTPort) { +#if defined(CHIP_LPC177X_8X) + case 4: +#else + case 0: + case 2: + case 3: +#endif + LPC_UART->TER2 = UART_TER2_TXEN; + break; + + default: + break; + } +#else + LPC_UART->TER1 = UART_TER1_TXEN; +#endif + } + else { +#if defined(CHIP_LPC177X_8X) || defined(CHIP_LPC18XX) || defined(CHIP_LPC43XX) + switch (UARTPort) { +#if defined(CHIP_LPC177X_8X) + case 4: +#else + case 0: + case 2: + case 3: +#endif + LPC_UART->TER2 &= (~UART_TER2_TXEN) & UART_TER2_BITMASK; + break; + + default: + break; + } +#else + LPC_UART->TER1 &= (~UART_TER1_TXEN) & UART_TER1_BITMASK; +#endif + } +} + +/* UART FIFO functions ----------------------------------------------------------*/ +/* Configure FIFO function on selected UART peripheral */ +void IP_UART_FIFOConfig(IP_USART_001_Type *LPC_UART, UART_FIFO_CFG_Type *FIFOCfg) +{ + uint8_t tmp = 0; + + tmp |= UART_FCR_FIFO_EN; + switch (FIFOCfg->FIFO_Level) { + case UART_FIFO_TRGLEV0: + tmp |= UART_FCR_TRG_LEV0; + break; + + case UART_FIFO_TRGLEV1: + tmp |= UART_FCR_TRG_LEV1; + break; + + case UART_FIFO_TRGLEV2: + tmp |= UART_FCR_TRG_LEV2; + break; + + case UART_FIFO_TRGLEV3: + default: + tmp |= UART_FCR_TRG_LEV3; + break; + } + + if (FIFOCfg->FIFO_ResetTxBuf == ENABLE) { + tmp |= UART_FCR_TX_RS; + } + if (FIFOCfg->FIFO_ResetRxBuf == ENABLE) { + tmp |= UART_FCR_RX_RS; + } + if (FIFOCfg->FIFO_DMAMode == ENABLE) { + tmp |= UART_FCR_DMAMODE_SEL; + } + + /* write to FIFO control register */ + LPC_UART->FCR = tmp & UART_FCR_BITMASK; +} + +/* Fills each UART_FIFOInitStruct member with its default value */ +void IP_UART_FIFOConfigStructInit(UART_FIFO_CFG_Type *UART_FIFOInitStruct) +{ + UART_FIFOInitStruct->FIFO_DMAMode = DISABLE; + UART_FIFOInitStruct->FIFO_Level = UART_FIFO_TRGLEV0; + UART_FIFOInitStruct->FIFO_ResetRxBuf = ENABLE; + UART_FIFOInitStruct->FIFO_ResetTxBuf = ENABLE; +} diff --git a/bsp/xplorer4330/libraries/lpc_ip/usart_001.h b/bsp/xplorer4330/libraries/lpc_ip/usart_001.h new file mode 100644 index 0000000000..1af6612014 --- /dev/null +++ b/bsp/xplorer4330/libraries/lpc_ip/usart_001.h @@ -0,0 +1,675 @@ +/* + * @brief Usart Registers and control functions + * + * @note + * Copyright(C) NXP Semiconductors, 2012 + * All rights reserved. + * + * @par + * Software that is described herein is for illustrative purposes only + * which provides customers with programming information regarding the + * LPC products. This software is supplied "AS IS" without any warranties of + * any kind, and NXP Semiconductors and its licensor disclaim any and + * all warranties, express or implied, including all implied warranties of + * merchantability, fitness for a particular purpose and non-infringement of + * intellectual property rights. NXP Semiconductors assumes no responsibility + * or liability for the use of the software, conveys no license or rights under any + * patent, copyright, mask work right, or any other intellectual property rights in + * or to any products. NXP Semiconductors reserves the right to make changes + * in the software without notification. NXP Semiconductors also makes no + * representation or warranty that such application will be suitable for the + * specified use without further testing or modification. + * + * @par + * Permission to use, copy, modify, and distribute this software and its + * documentation is hereby granted, under NXP Semiconductors' and its + * licensor's relevant copyrights in the software, without fee, provided that it + * is used in conjunction with NXP Semiconductors microcontrollers. This + * copyright, permission, and disclaimer notice must appear in all copies of + * this code. + */ + +#ifndef __USART_001_H_ +#define __USART_001_H_ + +#include "sys_config.h" +#include "cmsis.h" + +#ifdef __cplusplus +extern "C" { +#endif + +/** @defgroup IP_USART_001 IP: USART register block and driver + * @ingroup IP_Drivers + * @{ + */ + +/** + * @brief USART register block structure + */ +typedef struct { /*!< USARTn Structure */ + + union { + __IO uint32_t DLL; /*!< Divisor Latch LSB. Least significant byte of the baud rate divisor value. The full divisor is used to generate a baud rate from the fractional rate divider (DLAB = 1). */ + __O uint32_t THR; /*!< Transmit Holding Register. The next character to be transmitted is written here (DLAB = 0). */ + __I uint32_t RBR; /*!< Receiver Buffer Register. Contains the next received character to be read (DLAB = 0). */ + }; + + union { + __IO uint32_t IER; /*!< Interrupt Enable Register. Contains individual interrupt enable bits for the 7 potential UART interrupts (DLAB = 0). */ + __IO uint32_t DLM; /*!< Divisor Latch MSB. Most significant byte of the baud rate divisor value. The full divisor is used to generate a baud rate from the fractional rate divider (DLAB = 1). */ + }; + + union { + __O uint32_t FCR; /*!< FIFO Control Register. Controls UART FIFO usage and modes. */ + __I uint32_t IIR; /*!< Interrupt ID Register. Identifies which interrupt(s) are pending. */ + }; + + __IO uint32_t LCR; /*!< Line Control Register. Contains controls for frame formatting and break generation. */ + __IO uint32_t MCR; /*!< Modem Control Register. Only present on USART ports with full modem support. */ + __I uint32_t LSR; /*!< Line Status Register. Contains flags for transmit and receive status, including line errors. */ + __I uint32_t MSR; /*!< Modem Status Register. Only present on USART ports with full modem support. */ + __IO uint32_t SCR; /*!< Scratch Pad Register. Eight-bit temporary storage for software. */ + __IO uint32_t ACR; /*!< Auto-baud Control Register. Contains controls for the auto-baud feature. */ + __IO uint32_t ICR; /*!< IrDA control register (not all UARTS) */ + __IO uint32_t FDR; /*!< Fractional Divider Register. Generates a clock input for the baud rate divider. */ + __IO uint32_t OSR; /*!< Oversampling Register. Controls the degree of oversampling during each bit time. Only on some UARTS. */ + __IO uint32_t TER1; /*!< Transmit Enable Register. Turns off USART transmitter for use with software flow control. */ + uint32_t RESERVED0[3]; + __IO uint32_t HDEN; /*!< Half-duplex enable Register- only on some UARTs */ + __I uint32_t RESERVED1[1]; + __IO uint32_t SCICTRL; /*!< Smart card interface control register- only on some UARTs */ + __IO uint32_t RS485CTRL; /*!< RS-485/EIA-485 Control. Contains controls to configure various aspects of RS-485/EIA-485 modes. */ + __IO uint32_t RS485ADRMATCH; /*!< RS-485/EIA-485 address match. Contains the address match value for RS-485/EIA-485 mode. */ + __IO uint32_t RS485DLY; /*!< RS-485/EIA-485 direction control delay. */ + union { + __IO uint32_t SYNCCTRL; /*!< Synchronous mode control register. Only on USARTs. */ + __I uint32_t FIFOLVL; /*!< FIFO Level register. Provides the current fill levels of the transmit and receive FIFOs. */ + }; + + __IO uint32_t TER2; /*!< Transmit Enable Register. Only on LPC177X_8X UART4 and LPC18XX/43XX USART0/2/3. */ +} IP_USART_001_Type; + +#define UART_BLOCKING_TIMEOUT (0xFFFFFFFFUL) /*!< UART time-out definitions in case of using Read/Write function with Blocking Flag mode */ + +#define UART_ACCEPTED_BAUDRATE_ERROR (3) /*!< Acceptable UART baudrate error */ + +/* --------------------- BIT DEFINITIONS -------------------------------------- */ +/** + * @brief Macro defines for UARTn Receiver Buffer Register + */ +#define UART_RBR_MASKBIT ((uint8_t) 0xFF) /*!< UART Received Buffer mask bit (8 bits) */ + +/** + * @brief Macro defines for UARTn Transmit Holding Register + */ +#define UART_THR_MASKBIT ((uint8_t) 0xFF) /*!< UART Transmit Holding mask bit (8 bits) */ + +/** + * @brief Macro defines for UARTn Divisor Latch LSB register + */ +#define UART_LOAD_DLL(div) ((div) & 0xFF) /*!< Macro for loading least significant halfs of divisors */ +#define UART_DLL_MASKBIT ((uint8_t) 0xFF) /*!< Divisor latch LSB bit mask */ + +/** + * @brief Macro defines for UARTn Divisor Latch MSB register + */ +#define UART_DLM_MASKBIT ((uint8_t) 0xFF) /*!< Divisor latch MSB bit mask */ +#define UART_LOAD_DLM(div) (((div) >> 8) & 0xFF) /*!< Macro for loading most significant halfs of divisors */ + +/** + * @brief Macro defines for UART interrupt enable register + */ +#define UART_IER_RBRINT_EN ((uint32_t) (1 << 0)) /*!< RBR Interrupt enable*/ +#define UART_IER_THREINT_EN ((uint32_t) (1 << 1)) /*!< THR Interrupt enable*/ +#define UART_IER_RLSINT_EN ((uint32_t) (1 << 2)) /*!< RX line status interrupt enable*/ +#define UART_IER_MSINT_EN ((uint32_t) (1 << 3)) /*!< Modem status interrupt enable */ +#define UART_IER_CTSINT_EN ((uint32_t) (1 << 7)) /*!< CTS1 signal transition interrupt enable */ +#define UART_IER_ABEOINT_EN ((uint32_t) (1 << 8)) /*!< Enables the end of auto-baud interrupt */ +#define UART_IER_ABTOINT_EN ((uint32_t) (1 << 9)) /*!< Enables the auto-baud time-out interrupt */ +#define UART_IER_BITMASK ((uint32_t) (0x307)) /*!< UART interrupt enable register bit mask */ +#define UART1_IER_BITMASK ((uint32_t) (0x38F)) /*!< UART1 interrupt enable register bit mask */ + +/** + * @brief Macro defines for UART interrupt identification register + */ +#define UART_IIR_INTSTAT_PEND ((uint32_t) (1 << 0)) /*!> 8) & 0x0F)) /*!< Reflects the current level of the UART transmitter FIFO */ +#define UART_FIFOLVL_BITMASK ((uint32_t) (0x0F0F)) /*!< UART FIFO Level Register bit mask */ + +/** + * @brief Macro defines for Ring Buffer + */ +#define UART_RING_BUFSIZE 256 /*!< buffer size definition */ +#define __BUF_MASK (UART_RING_BUFSIZE - 1) /*!< Buf mask */ +#define __BUF_IS_FULL(head, tail) ((tail & __BUF_MASK) == ((head + 1) & __BUF_MASK)) /*!< Check buf is full or not */ +#define __BUF_WILL_FULL(head, tail) ((tail & __BUF_MASK) == ((head + 2) & __BUF_MASK)) /*!< Check buf will be full in next receiving or not */ +#define __BUF_IS_EMPTY(head, tail) ((head & __BUF_MASK) == (tail & __BUF_MASK)) /*!< Check buf is empty */ +#define __BUF_RESET(bufidx) (bufidx = 0) /*!< Reset buf */ +#define __BUF_INCR(bufidx) (bufidx = (bufidx + 1) & __BUF_MASK) /*!< Increase buf */ + +/** + * @brief UART Ring buffer structure + */ +typedef struct { + __IO uint32_t tx_head; /*!< UART Tx ring buffer head index */ + __IO uint32_t tx_tail; /*!< UART Tx ring buffer tail index */ + __IO uint32_t rx_head; /*!< UART Rx ring buffer head index */ + __IO uint32_t rx_tail; /*!< UART Rx ring buffer tail index */ + __IO uint8_t tx[UART_RING_BUFSIZE]; /*!< UART Tx data ring buffer */ + __IO uint8_t rx[UART_RING_BUFSIZE]; /*!< UART Rx data ring buffer */ +} UART_RingBuffer_Type; + +/** + * @brief UART Line Status Type definition + */ +typedef enum { + UART_LINESTAT_RDR = UART_LSR_RDR, /*!< Line status register: Receive data ready*/ + UART_LINESTAT_OE = UART_LSR_OE, /*!< Line status register: Overrun error*/ + UART_LINESTAT_PE = UART_LSR_PE, /*!< Line status register: Parity error*/ + UART_LINESTAT_FE = UART_LSR_FE, /*!< Line status register: Framing error*/ + UART_LINESTAT_BI = UART_LSR_BI, /*!< Line status register: Break interrupt*/ + UART_LINESTAT_THRE = UART_LSR_THRE, /*!< Line status register: Transmit holding register empty*/ + UART_LINESTAT_TEMT = UART_LSR_TEMT, /*!< Line status register: Transmitter empty*/ + UART_LINESTAT_RXFE = UART_LSR_RXFE /*!< Error in RX FIFO*/ +} IP_UART_LS_Type; + +/** + * @brief UART End of Auto-baudrate type definition + */ +typedef enum { + UART_AUTOBAUD_INTSTAT_ABEO = UART_IIR_ABEO_INT, /*!< UART End of auto-baud interrupt */ + UART_AUTOBAUD_INTSTAT_ABTO = UART_IIR_ABTO_INT /*!< UART Auto-baud time-out interrupt */ +} IP_UART_ABEO_Type; + +/** + * @brief UART Full modem - Signal states definition + */ +typedef enum { + INACTIVE = 0, /*!< In-active state */ + ACTIVE = !INACTIVE /*!< Active state */ +} IP_UART_SignalState; + +/** + * @brief UART modem status type definition + */ +typedef enum { + UART_MODEM_STAT_DELTA_CTS = UART_MSR_DELTA_CTS, /*!< Set upon state change of input CTS */ + UART_MODEM_STAT_DELTA_DSR = UART_MSR_DELTA_DSR, /*!< Set upon state change of input DSR */ + UART_MODEM_STAT_LO2HI_RI = UART_MSR_LO2HI_RI, /*!< Set upon low to high transition of input RI */ + UART_MODEM_STAT_DELTA_DCD = UART_MSR_DELTA_DCD, /*!< Set upon state change of input DCD */ + UART_MODEM_STAT_CTS = UART_MSR_CTS, /*!< Clear To Send State */ + UART_MODEM_STAT_DSR = UART_MSR_DSR, /*!< Data Set Ready State */ + UART_MODEM_STAT_RI = UART_MSR_RI, /*!< Ring Indicator State */ + UART_MODEM_STAT_DCD = UART_MSR_DCD /*!< Data Carrier Detect State */ +} IP_UART_MODEM_STAT_type; + +/** + * @brief Modem output pin type definition + */ +typedef enum { + UART_MODEM_PIN_DTR = 0, /*!< Source for modem output pin DTR */ + UART_MODEM_PIN_RTS /*!< Source for modem output pin RTS */ +} IP_UART_MODEM_PIN_Type; + +/** + * @brief UART Modem mode type definition + */ +typedef enum { + UART_MODEM_MODE_LOOPBACK = 0, /*!< Loop back mode select */ + UART_MODEM_MODE_AUTO_RTS, /*!< Enable Auto RTS flow-control */ + UART_MODEM_MODE_AUTO_CTS /*!< Enable Auto CTS flow-control */ +} IP_UART_MODEM_MODE_Type; + +/** + * @brief UART Interrupt Type definitions + */ +typedef enum { + UART_INTCFG_RBR = 0, /*!< RBR Interrupt enable*/ + UART_INTCFG_THRE, /*!< THR Interrupt enable*/ + UART_INTCFG_RLS, /*!< RX line status interrupt enable*/ + UART_INTCFG_MS, /*!< Modem status interrupt enable */ + UART_INTCFG_CTS, /*!< CTS1 signal transition interrupt enable */ + UART_INTCFG_ABEO, /*!< Enables the end of auto-baud interrupt */ + UART_INTCFG_ABTO /*!< Enables the auto-baud time-out interrupt */ +} UART_INT_Type; + +/** + * @brief UART Parity type definitions + */ +typedef enum { + UART_PARITY_NONE = 0, /*!< No parity */ + UART_PARITY_ODD = (4 << 3), /*!< Odd parity */ + UART_PARITY_EVEN = (5 << 3), /*!< Even parity */ + UART_PARITY_SP_1 = (6 << 3), /*!< Forced "1" stick parity */ + UART_PARITY_SP_0 = (7 << 3) /*!< Forced "0" stick parity */ +} UART_PARITY_Type; + +/** + * @brief FIFO Level type definitions + */ +typedef enum { + UART_FIFO_TRGLEV0 = 0, /*!< UART FIFO trigger level 0: 1 character */ + UART_FIFO_TRGLEV1, /*!< UART FIFO trigger level 1: 4 character */ + UART_FIFO_TRGLEV2, /*!< UART FIFO trigger level 2: 8 character */ + UART_FIFO_TRGLEV3 /*!< UART FIFO trigger level 3: 14 character */ +} UART_FITO_LEVEL_Type; + +/** + * @brief UART Stop bit type definitions + */ +typedef enum { + UART_STOPBIT_1 = 0, /*!< UART One Stop Bit Select */ + UART_STOPBIT_2 = (1 << 2) /*!< UART Two Stop Bits Select */ +} UART_STOPBIT_Type; + +/** + * @brief UART Databit type definitions + */ +typedef enum { + UART_DATABIT_5 = 0, /*!< UART 5 bit data mode */ + UART_DATABIT_6, /*!< UART 6 bit data mode */ + UART_DATABIT_7, /*!< UART 7 bit data mode */ + UART_DATABIT_8 /*!< UART 8 bit data mode */ +} UART_DATABIT_Type; + +/** + * @brief UART ID + */ +typedef enum { + UART_0 = 0, + UART_1, + UART_2, + UART_3, + UART_4, +} UART_ID_Type; + +/** + * @brief UART Interrupt Status + */ +typedef enum { + UART_ERROR = 1, + READY_TO_SEND, + READY_TO_RECEIVE = 4, +} UART_Int_Status; + +/** + * @brief UART FIFO Configuration Structure definition + */ +typedef struct { + FunctionalState FIFO_ResetRxBuf; /*!< Reset Rx FIFO command state , should be: + - ENABLE: Reset Rx FIFO in UART + - DISABLE: Do not reset Rx FIFO in UART + */ + FunctionalState FIFO_ResetTxBuf; /*!< Reset Tx FIFO command state , should be: + - ENABLE: Reset Tx FIFO in UART + - DISABLE: Do not reset Tx FIFO in UART + */ + FunctionalState FIFO_DMAMode; /*!< DMA mode, should be: + - ENABLE: Enable DMA mode in UART + - DISABLE: Disable DMA mode in UART + */ + UART_FITO_LEVEL_Type FIFO_Level; /*!< Rx FIFO trigger level, should be: + - UART_FIFO_TRGLEV0: UART FIFO trigger level 0: 1 character + - UART_FIFO_TRGLEV1: UART FIFO trigger level 1: 4 character + - UART_FIFO_TRGLEV2: UART FIFO trigger level 2: 8 character + - UART_FIFO_TRGLEV3: UART FIFO trigger level 3: 14 character + */ +} UART_FIFO_CFG_Type; + +/** + * @brief Initializes the UARTx peripheral according to the specified parameters in the UART_ConfigStruct. + * @param LPC_UART : Pointer to selected UARTx peripheral + * @param UARTPort : UART ID type + * @return Nothing + */ +void IP_UART_Init(IP_USART_001_Type *LPC_UART, UART_ID_Type UARTPort); + +/** + * @brief De-initializes the UARTx peripheral registers to their default reset values. + * @param LPC_UART : Pointer to selected UARTx peripheral + * @param UARTPort : UART ID type + * @return Nothing + */ +void IP_UART_DeInit(IP_USART_001_Type *LPC_UART, UART_ID_Type UARTPort); + +/** + * @brief Determines best dividers to get a target clock rate + * @param LPC_UART : Pointer to selected UARTx peripheral + * @param baudrate : Desired UART baud rate. + * @param uClk : Current Uart Block Clock. + * @return Error status, could be SUCCESS or ERROR + */ +Status IP_UART_SetBaud(IP_USART_001_Type *LPC_UART, uint32_t baudrate, uint32_t uClk); + +/** + * @brief Configure data width, parity mode and stop bits + * @param LPC_UART : Pointer to selected UARTx peripheral + * @param Databits : UART Data width, should be: + * UART_DATABIT_5: UART 5 bit data mode + * UART_DATABIT_6: UART 6 bit data mode + * UART_DATABIT_7: UART 7 bit data mode + * UART_DATABIT_8: UART 8 bit data mode + * @param Parity : UART Parity mode, should be: + * UART_PARITY_NONE: No parity + * UART_PARITY_ODD: Odd parity + * UART_PARITY_EVEN: Even parity + * UART_PARITY_SP_1: Forced "1" stick parity + * UART_PARITY_SP_0: Forced "0" stick parity + * @param Stopbits : Number of stop bits, should be: + * UART_STOPBIT_1: One Stop Bit Select + * UART_STOPBIT_2: Two Stop Bits Select + * @return Nothing + */ +void IP_UART_ConfigData(IP_USART_001_Type *LPC_UART, + UART_DATABIT_Type Databits, + UART_PARITY_Type Parity, + UART_STOPBIT_Type Stopbits); + +/* UART Send/Receive functions -------------------------------------------------*/ +/** + * @brief Transmit a single data through UART peripheral + * @param LPC_UART : Pointer to selected UARTx peripheral + * @param Data : Data to transmit (must be 8-bit long) + * @return Status, should be ERROR (THR is empty, ready to send) or SUCCESS (THR is not empty) + */ +Status IP_UART_SendByte(IP_USART_001_Type *LPC_UART, uint8_t Data); + +/** + * @brief Receive a single data from UART peripheral + * @param LPC_UART : Pointer to selected UARTx peripheral + * @param *Data : Pointer to Data to receive (must be 8-bit long) + * @return Status, should be ERROR or (Receive data is ready) or SUCCESS (Receive data is not ready yet) + */ +Status IP_UART_ReceiveByte(IP_USART_001_Type *LPC_UART, uint8_t *Data); + +/** + * @brief Send a block of data via UART peripheral + * @param LPC_UART : Pointer to selected UARTx peripheral + * @param txbuf : Pointer to Transmit buffer + * @param buflen : Length of Transmit buffer + * @param flag : Flag used in UART transfer, should be NONE_BLOCKING or BLOCKING + * @return Number of bytes sent + * + * Note: when using UART in BLOCKING mode, a time-out condition is used + * via defined symbol UART_BLOCKING_TIMEOUT. + */ +uint32_t IP_UART_Send(IP_USART_001_Type *LPC_UART, uint8_t *txbuf, uint32_t buflen, TRANSFER_BLOCK_Type flag); + +/** + * @brief Receive a block of data via UART peripheral + * @param LPC_UART : Pointer to selected UARTx peripheral + * @param rxbuf : Pointer to Received buffer + * @param buflen : Length of Received buffer + * @param flag : Flag mode, should be NONE_BLOCKING or BLOCKING + * @return Number of bytes received + * + * Note: when using UART in BLOCKING mode, a time-out condition is used + * via defined symbol UART_BLOCKING_TIMEOUT. + */ +uint32_t IP_UART_Receive(IP_USART_001_Type *LPC_UART, uint8_t *rxbuf, uint32_t buflen, TRANSFER_BLOCK_Type flag); + +/* UART operate functions -------------------------------------------------------*/ +/** + * @brief Enable or disable specified UART interrupt. + * @param LPC_UART : Pointer to selected UARTx peripheral + * @param UARTIntCfg : Specifies the interrupt flag, should be one of the following: + * - UART_INTCFG_RBR : RBR Interrupt enable + * - UART_INTCFG_THRE : THR Interrupt enable + * - UART_INTCFG_RLS : RX line status interrupt enable + * - UART1_INTCFG_MS : Modem status interrupt enable (UART1 only) + * - UART1_INTCFG_CTS : CTS1 signal transition interrupt enable (UART1 only) + * - UART_INTCFG_ABEO : Enables the end of auto-baud interrupt + * - UART_INTCFG_ABTO : Enables the auto-baud time-out interrupt + * @param NewState : New state of specified UART interrupt type, should be: + * - ENALBE : Enable this UART interrupt type + * - DISALBE : Disable this UART interrupt type + * @return Nothing + */ +void IP_UART_IntConfig(IP_USART_001_Type *LPC_UART, UART_INT_Type UARTIntCfg, FunctionalState NewState); + +/** + * @brief Get Source Interrupt + * @param LPC_UART : Pointer to selected UARTx peripheral + * @return Return the value of IIR register +*/ +uint32_t IP_UART_IntGetStatus(IP_USART_001_Type *LPC_UART); + +/** + * @brief Force BREAK character on UART line, output pin UARTx TXD is forced to logic 0 + * @param LPC_UART : Pointer to selected UARTx peripheral + * @return Nothing + */ +void IP_UART_ForceBreak(IP_USART_001_Type *LPC_UART); + +/** + * @brief Get current value of Line Status register in UART peripheral. + * @param LPC_UART : Pointer to selected UARTx peripheral + * @return Current value of Line Status register in UART peripheral + * + * Note: The return value of this function must be ANDed with each member in UART_LS_Type + * enumeration to determine current flag status corresponding to each Line status type. Because + * some flags in Line Status register will be cleared after reading, the next reading Line + * Status register could not be correct. So this function used to read Line status register + * in one time only, then the return value used to check all flags. + */ +uint8_t IP_UART_GetLineStatus(IP_USART_001_Type *LPC_UART); + +/** + * @brief Check whether if UART is busy or not + * @param LPC_UART : Pointer to selected UARTx peripheral + * @return RESET if UART is not busy, otherwise return SET. + */ +FlagStatus IP_UART_CheckBusy(IP_USART_001_Type *LPC_UART); + +/** + * @brief Enable/Disable transmission on UART TxD pin + * @param LPC_UART : Pointer to selected UARTx peripheral + * @param UARTPort : UART ID type + * @param NewState : New State of Tx transmission function, should be ENABLE or DISABLE + * @return Nothing + */ +void IP_UART_TxCmd(IP_USART_001_Type *LPC_UART, UART_ID_Type UARTPort, FunctionalState NewState); + +/* UART FIFO functions ----------------------------------------------------------*/ +/** + * @brief Configure FIFO function on selected UART peripheral + * @param LPC_UART : Pointer to selected UARTx peripheral + * @param FIFOCfg : Pointer to a UART_FIFO_CFG_Type Structure that contains specified information about FIFO configuration + * @return Nothing + */ +void IP_UART_FIFOConfig(IP_USART_001_Type *LPC_UART, UART_FIFO_CFG_Type *FIFOCfg); + +/** + * @brief Fills each UART_FIFOInitStruct member with its default value: + * - FIFO_DMAMode = DISABLE + * - FIFO_Level = UART_FIFO_TRGLEV0 + * - FIFO_ResetRxBuf = ENABLE + * - FIFO_ResetTxBuf = ENABLE + * - FIFO_State = ENABLE + * @param UART_FIFOInitStruct : Pointer to a UART_FIFO_CFG_Type structure which will be initialized. + * @return Nothing +*/ +void IP_UART_FIFOConfigStructInit(UART_FIFO_CFG_Type *UART_FIFOInitStruct); + +/** + * @} + */ + +#ifdef __cplusplus +} +#endif + +#endif /* __USART_001_H_ */ diff --git a/bsp/xplorer4330/libraries/lpc_ip/usbhs_001.h b/bsp/xplorer4330/libraries/lpc_ip/usbhs_001.h new file mode 100644 index 0000000000..e37a90a6c8 --- /dev/null +++ b/bsp/xplorer4330/libraries/lpc_ip/usbhs_001.h @@ -0,0 +1,128 @@ +/* + * @brief High-Speed USB registers and control functions + * + * @note + * Copyright(C) NXP Semiconductors, 2012 + * All rights reserved. + * + * @par + * Software that is described herein is for illustrative purposes only + * which provides customers with programming information regarding the + * LPC products. This software is supplied "AS IS" without any warranties of + * any kind, and NXP Semiconductors and its licensor disclaim any and + * all warranties, express or implied, including all implied warranties of + * merchantability, fitness for a particular purpose and non-infringement of + * intellectual property rights. NXP Semiconductors assumes no responsibility + * or liability for the use of the software, conveys no license or rights under any + * patent, copyright, mask work right, or any other intellectual property rights in + * or to any products. NXP Semiconductors reserves the right to make changes + * in the software without notification. NXP Semiconductors also makes no + * representation or warranty that such application will be suitable for the + * specified use without further testing or modification. + * + * @par + * Permission to use, copy, modify, and distribute this software and its + * documentation is hereby granted, under NXP Semiconductors' and its + * licensor's relevant copyrights in the software, without fee, provided that it + * is used in conjunction with NXP Semiconductors microcontrollers. This + * copyright, permission, and disclaimer notice must appear in all copies of + * this code. + */ + +#ifndef __USBHS_001_H_ +#define __USBHS_001_H_ + +#include "sys_config.h" +#include "cmsis.h" + +#ifdef __cplusplus +extern "C" { +#endif + +/** @defgroup IP_USBHS_001 IP: USBHS Device, Host, & OTG register block and driver + * @ingroup IP_Drivers + * USB High-Speed Device, Host, & OTG + * Note: On the LPC18xx and LPC43xx, only USB0 supports OTG + * @{ + */ + +/** + * @brief USB High-Speed register block structure + */ +typedef struct { /*!< USB Structure */ + __I uint32_t RESERVED0[64]; + __I uint32_t CAPLENGTH; /*!< Capability register length */ + __I uint32_t HCSPARAMS; /*!< Host controller structural parameters */ + __I uint32_t HCCPARAMS; /*!< Host controller capability parameters */ + __I uint32_t RESERVED1[5]; + __I uint32_t DCIVERSION; /*!< Device interface version number */ + __I uint32_t RESERVED2[7]; + union { + __IO uint32_t USBCMD_H; /*!< USB command (host mode) */ + __IO uint32_t USBCMD_D; /*!< USB command (device mode) */ + }; + + union { + __IO uint32_t USBSTS_H; /*!< USB status (host mode) */ + __IO uint32_t USBSTS_D; /*!< USB status (device mode) */ + }; + + union { + __IO uint32_t USBINTR_H; /*!< USB interrupt enable (host mode) */ + __IO uint32_t USBINTR_D; /*!< USB interrupt enable (device mode) */ + }; + + union { + __IO uint32_t FRINDEX_H; /*!< USB frame index (host mode) */ + __I uint32_t FRINDEX_D; /*!< USB frame index (device mode) */ + }; + + __I uint32_t RESERVED3; + union { + __IO uint32_t PERIODICLISTBASE; /*!< Frame list base address */ + __IO uint32_t DEVICEADDR; /*!< USB device address */ + }; + + union { + __IO uint32_t ASYNCLISTADDR; /*!< Address of endpoint list in memory (host mode) */ + __IO uint32_t ENDPOINTLISTADDR; /*!< Address of endpoint list in memory (device mode) */ + }; + + __IO uint32_t TTCTRL; /*!< Asynchronous buffer status for embedded TT (host mode) */ + __IO uint32_t BURSTSIZE; /*!< Programmable burst size */ + __IO uint32_t TXFILLTUNING; /*!< Host transmit pre-buffer packet tuning (host mode) */ + __I uint32_t RESERVED4[2]; + __IO uint32_t ULPIVIEWPORT; /*!< ULPI viewport */ + __IO uint32_t BINTERVAL; /*!< Length of virtual frame */ + __IO uint32_t ENDPTNAK; /*!< Endpoint NAK (device mode) */ + __IO uint32_t ENDPTNAKEN; /*!< Endpoint NAK Enable (device mode) */ + __I uint32_t RESERVED5; + union { + __IO uint32_t PORTSC1_H; /*!< Port 1 status/control (host mode) */ + __IO uint32_t PORTSC1_D; /*!< Port 1 status/control (device mode) */ + }; + + __I uint32_t RESERVED6[7]; + __IO uint32_t OTGSC; /*!< OTG status and control */ + union { + __IO uint32_t USBMODE_H; /*!< USB mode (host mode) */ + __IO uint32_t USBMODE_D; /*!< USB mode (device mode) */ + }; + + __IO uint32_t ENDPTSETUPSTAT; /*!< Endpoint setup status */ + __IO uint32_t ENDPTPRIME; /*!< Endpoint initialization */ + __IO uint32_t ENDPTFLUSH; /*!< Endpoint de-initialization */ + __I uint32_t ENDPTSTAT; /*!< Endpoint status */ + __IO uint32_t ENDPTCOMPLETE; /*!< Endpoint complete */ + __IO uint32_t ENDPTCTRL[6]; /*!< Endpoint control 0 */ +} IP_USBHS_001_Type; + +/** + * @} + */ + +#ifdef __cplusplus +} +#endif + +#endif /* __USBHS_001_H_ */ diff --git a/bsp/xplorer4330/libraries/lpc_ip/wwdt_001.h b/bsp/xplorer4330/libraries/lpc_ip/wwdt_001.h new file mode 100644 index 0000000000..55cd5999f4 --- /dev/null +++ b/bsp/xplorer4330/libraries/lpc_ip/wwdt_001.h @@ -0,0 +1,75 @@ +/* + * @brief WWDT Registers and functions + * + * @note + * Copyright(C) NXP Semiconductors, 2012 + * All rights reserved. + * + * @par + * Software that is described herein is for illustrative purposes only + * which provides customers with programming information regarding the + * LPC products. This software is supplied "AS IS" without any warranties of + * any kind, and NXP Semiconductors and its licensor disclaim any and + * all warranties, express or implied, including all implied warranties of + * merchantability, fitness for a particular purpose and non-infringement of + * intellectual property rights. NXP Semiconductors assumes no responsibility + * or liability for the use of the software, conveys no license or rights under any + * patent, copyright, mask work right, or any other intellectual property rights in + * or to any products. NXP Semiconductors reserves the right to make changes + * in the software without notification. NXP Semiconductors also makes no + * representation or warranty that such application will be suitable for the + * specified use without further testing or modification. + * + * @par + * Permission to use, copy, modify, and distribute this software and its + * documentation is hereby granted, under NXP Semiconductors' and its + * licensor's relevant copyrights in the software, without fee, provided that it + * is used in conjunction with NXP Semiconductors microcontrollers. This + * copyright, permission, and disclaimer notice must appear in all copies of + * this code. + */ + +#ifndef __WWDT_001_H_ +#define __WWDT_001_H_ + +#include "sys_config.h" +#include "cmsis.h" + +#ifdef __cplusplus +extern "C" { +#endif + +/** @defgroup IP_WWDT_001 IP: WWDT register block and driver + * @ingroup IP_Drivers + * Windowed Watchdog + * @{ + */ + +/** + * @brief Windowed Watchdog register block structure + */ +typedef struct { /*!< WWDT Structure */ + __IO uint32_t MOD; /*!< Watchdog mode register. This register contains the basic mode and status of the Watchdog Timer. */ + __IO uint32_t TC; /*!< Watchdog timer constant register. This register determines the time-out value. */ + __O uint32_t FEED; /*!< Watchdog feed sequence register. Writing 0xAA followed by 0x55 to this register reloads the Watchdog timer with the value contained in WDTC. */ + __I uint32_t TV; /*!< Watchdog timer value register. This register reads out the current value of the Watchdog timer. */ +#if defined(CHIP_LPC11UXX) || defined(CHIP_LPC175X_6X) + __IO uint32_t CLKSEL; /*!< Watchdog clock select register. */ +#else + __I uint32_t RESERVED0; +#endif +#if !defined(CHIP_LPC175X_6X) + __IO uint32_t WARNINT; /*!< Watchdog warning interrupt register. This register contains the Watchdog warning interrupt compare value. */ + __IO uint32_t WINDOW; /*!< Watchdog timer window register. This register contains the Watchdog window value. */ +#endif +} IP_WWDT_001_Type; + +/** + * @} + */ + +#ifdef __cplusplus +} +#endif + +#endif /* __WWDT_001_H_ */ diff --git a/bsp/xplorer4330/libraries/startup_code/SConscript b/bsp/xplorer4330/libraries/startup_code/SConscript new file mode 100644 index 0000000000..fc89cc270d --- /dev/null +++ b/bsp/xplorer4330/libraries/startup_code/SConscript @@ -0,0 +1,22 @@ +Import('RTT_ROOT') +Import('rtconfig') +from building import * + +# add for startup code +if rtconfig.CROSS_TOOL == 'gcc': + src = ['gcc_startup_lpc18xx43xx.s'] +elif rtconfig.CROSS_TOOL == 'keil': + src = ['keil_startup_lpc18xx43xx.s'] +elif rtconfig.CROSS_TOOL == 'iar': + src = ['iar_startup_lpc18xx43xx.s'] + +if GetDepend(['RT_USING_BSP_CMSIS']): + path = [cwd + '/CM3/CoreSupport'] + src += ['CM3/CoreSupport/core_cm3.c'] +elif GetDepend(['RT_USING_RTT_CMSIS']): + path = [RTT_ROOT + '/components/CMSIS/Include'] + +CPPDEFINES = ['CORE_M4'] +group = DefineGroup('startup', src, depend = [''], CPPPATH = path, CPPDEFINES = CPPDEFINES) + +Return('group') diff --git a/bsp/xplorer4330/libraries/startup_code/gcc_startup_lpc18xx43xx.s b/bsp/xplorer4330/libraries/startup_code/gcc_startup_lpc18xx43xx.s new file mode 100644 index 0000000000..5ac832d1c8 --- /dev/null +++ b/bsp/xplorer4330/libraries/startup_code/gcc_startup_lpc18xx43xx.s @@ -0,0 +1,221 @@ +/* File: startup_ARMCM4.S + * Purpose: startup file for Cortex-M4 devices. Should use with + * GCC for ARM Embedded Processors + * Version: V1.3 + * Date: 08 Feb 2012 + * + * Copyright (c) 2012, ARM Limited + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * Redistributions of source code must retain the above copyright + notice, this list of conditions and the following disclaimer. + * Redistributions in binary form must reproduce the above copyright + notice, this list of conditions and the following disclaimer in the + documentation and/or other materials provided with the distribution. + * Neither the name of the ARM Limited nor the + names of its contributors may be used to endorse or promote products + derived from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL ARM LIMITED BE LIABLE FOR ANY + * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND + * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + .syntax unified + .arch armv7-m + + .section .stack + .align 3 +#ifdef __STACK_SIZE + .equ Stack_Size, __STACK_SIZE +#else + .equ Stack_Size, 0x400 +#endif + .globl __StackTop + .globl __StackLimit +__StackLimit: + .space Stack_Size + .size __StackLimit, . - __StackLimit +__StackTop: + .size __StackTop, . - __StackTop + + .section .heap + .align 3 +#ifdef __HEAP_SIZE + .equ Heap_Size, __HEAP_SIZE +#else + .equ Heap_Size, 0xC00 +#endif + .globl __HeapBase + .globl __HeapLimit +__HeapBase: + .if Heap_Size + .space Heap_Size + .endif + .size __HeapBase, . - __HeapBase +__HeapLimit: + .size __HeapLimit, . - __HeapLimit + + .section .isr_vector + .align 2 + .globl __isr_vector +__isr_vector: + .long __StackTop /* Top of Stack */ + .long Reset_Handler /* Reset Handler */ + .long NMI_Handler /* NMI Handler */ + .long HardFault_Handler /* Hard Fault Handler */ + .long MemManage_Handler /* MPU Fault Handler */ + .long BusFault_Handler /* Bus Fault Handler */ + .long UsageFault_Handler /* Usage Fault Handler */ + .long 0 /* Reserved */ + .long 0 /* Reserved */ + .long 0 /* Reserved */ + .long 0 /* Reserved */ + .long SVC_Handler /* SVCall Handler */ + .long DebugMon_Handler /* Debug Monitor Handler */ + .long 0 /* Reserved */ + .long PendSV_Handler /* PendSV Handler */ + .long SysTick_Handler /* SysTick Handler */ + + /* External interrupts */ + .long WDT_IRQHandler /* 0: Watchdog Timer */ + .long RTC_IRQHandler /* 1: Real Time Clock */ + .long TIM0_IRQHandler /* 2: Timer0 / Timer1 */ + .long TIM2_IRQHandler /* 3: Timer2 / Timer3 */ + .long MCIA_IRQHandler /* 4: MCIa */ + .long MCIB_IRQHandler /* 5: MCIb */ + .long UART0_IRQHandler /* 6: UART0 - DUT FPGA */ + .long UART1_IRQHandler /* 7: UART1 - DUT FPGA */ + .long UART2_IRQHandler /* 8: UART2 - DUT FPGA */ + .long UART4_IRQHandler /* 9: UART4 - not connected */ + .long AACI_IRQHandler /* 10: AACI / AC97 */ + .long CLCD_IRQHandler /* 11: CLCD Combined Interrupt */ + .long ENET_IRQHandler /* 12: Ethernet */ + .long USBDC_IRQHandler /* 13: USB Device */ + .long USBHC_IRQHandler /* 14: USB Host Controller */ + .long CHLCD_IRQHandler /* 15: Character LCD */ + .long FLEXRAY_IRQHandler /* 16: Flexray */ + .long CAN_IRQHandler /* 17: CAN */ + .long LIN_IRQHandler /* 18: LIN */ + .long I2C_IRQHandler /* 19: I2C ADC/DAC */ + .long 0 /* 20: Reserved */ + .long 0 /* 21: Reserved */ + .long 0 /* 22: Reserved */ + .long 0 /* 23: Reserved */ + .long 0 /* 24: Reserved */ + .long 0 /* 25: Reserved */ + .long 0 /* 26: Reserved */ + .long 0 /* 27: Reserved */ + .long CPU_CLCD_IRQHandler /* 28: Reserved - CPU FPGA CLCD */ + .long 0 /* 29: Reserved - CPU FPGA */ + .long UART3_IRQHandler /* 30: UART3 - CPU FPGA */ + .long SPI_IRQHandler /* 31: SPI Touchscreen - CPU FPGA */ + + .size __isr_vector, . - __isr_vector + + .text + .thumb + .thumb_func + .align 2 + .globl Reset_Handler + .type Reset_Handler, %function +Reset_Handler: +/* Loop to copy data from read only memory to RAM. The ranges + * of copy from/to are specified by following symbols evaluated in + * linker script. + * __etext: End of code section, i.e., begin of data sections to copy from. + * __data_start__/__data_end__: RAM address range that data should be + * copied to. Both must be aligned to 4 bytes boundary. */ + + ldr r1, =__etext + ldr r2, =__data_start__ + ldr r3, =__data_end__ + +#if 1 +/* Here are two copies of loop implemenations. First one favors code size + * and the second one favors performance. Default uses the first one. + * Change to "#if 0" to use the second one */ +.flash_to_ram_loop: + cmp r2, r3 + ittt lt + ldrlt r0, [r1], #4 + strlt r0, [r2], #4 + blt .flash_to_ram_loop +#else + subs r3, r2 + ble .flash_to_ram_loop_end +.flash_to_ram_loop: + subs r3, #4 + ldr r0, [r1, r3] + str r0, [r2, r3] + bgt .flash_to_ram_loop +.flash_to_ram_loop_end: +#endif + +#ifndef __NO_SYSTEM_INIT + ldr r0, =SystemInit + blx r0 +#endif + + ldr r0, =_start + bx r0 + .pool + .size Reset_Handler, . - Reset_Handler + +/* Macro to define default handlers. Default handler + * will be weak symbol and just dead loops. They can be + * overwritten by other handlers */ + .macro def_irq_handler handler_name + .align 1 + .thumb_func + .weak \handler_name + .type \handler_name, %function +\handler_name : + b . + .size \handler_name, . - \handler_name + .endm + + def_irq_handler NMI_Handler + def_irq_handler HardFault_Handler + def_irq_handler MemManage_Handler + def_irq_handler BusFault_Handler + def_irq_handler UsageFault_Handler + def_irq_handler SVC_Handler + def_irq_handler DebugMon_Handler + def_irq_handler PendSV_Handler + def_irq_handler SysTick_Handler + def_irq_handler Default_Handler + + def_irq_handler WDT_IRQHandler + def_irq_handler RTC_IRQHandler + def_irq_handler TIM0_IRQHandler + def_irq_handler TIM2_IRQHandler + def_irq_handler MCIA_IRQHandler + def_irq_handler MCIB_IRQHandler + def_irq_handler UART0_IRQHandler + def_irq_handler UART1_IRQHandler + def_irq_handler UART2_IRQHandler + def_irq_handler UART3_IRQHandler + def_irq_handler UART4_IRQHandler + def_irq_handler AACI_IRQHandler + def_irq_handler CLCD_IRQHandler + def_irq_handler ENET_IRQHandler + def_irq_handler USBDC_IRQHandler + def_irq_handler USBHC_IRQHandler + def_irq_handler CHLCD_IRQHandler + def_irq_handler FLEXRAY_IRQHandler + def_irq_handler CAN_IRQHandler + def_irq_handler LIN_IRQHandler + def_irq_handler I2C_IRQHandler + def_irq_handler CPU_CLCD_IRQHandler + def_irq_handler SPI_IRQHandler + + .end diff --git a/bsp/xplorer4330/libraries/startup_code/keil_startup_lpc18xx43xx.s b/bsp/xplorer4330/libraries/startup_code/keil_startup_lpc18xx43xx.s new file mode 100644 index 0000000000..4c97d32c45 --- /dev/null +++ b/bsp/xplorer4330/libraries/startup_code/keil_startup_lpc18xx43xx.s @@ -0,0 +1,326 @@ +;/*********************************************************************** +; * Project: LPC18xx/43xx startup code +; * +; * Description: LPC18xx/43xx startup code +; * +; * Copyright(C) 2011, NXP Semiconductor +; * All rights reserved. +; * +; *********************************************************************** +; * Software that is described herein is for illustrative purposes only +; * which provides customers with programming information regarding the +; * products. This software is supplied "AS IS" without any warranties. +; * NXP Semiconductors assumes no responsibility or liability for the +; * use of the software, conveys no license or title under any patent, +; * copyright, or mask work right to the product. NXP Semiconductors +; * reserves the right to make changes in the software without +; * notification. NXP Semiconductors also make no representation or +; * warranty that such application will be suitable for the specified +; * use without further testing or modification. +; **********************************************************************/ + +; Stack Configuration +; Stack Size (in Bytes) <0x0-0xFFFFFFFF:8> +; + +Stack_Size EQU 0x00000200 + + AREA STACK, NOINIT, READWRITE, ALIGN=3 +Stack_Mem SPACE Stack_Size +__initial_sp + +; Heap Configuration +; Heap Size (in Bytes) <0x0-0xFFFFFFFF:8> +; + +Heap_Size EQU 0x00000000 + + AREA HEAP, NOINIT, READWRITE, ALIGN=3 +__heap_base +Heap_Mem SPACE Heap_Size +__heap_limit + + PRESERVE8 + THUMB + +; Vector Table Mapped to Address 0 at Reset + + AREA RESET, DATA, READONLY + EXPORT __Vectors + +Sign_Value EQU 0x5A5A5A5A + +__Vectors DCD __initial_sp ; 0 Top of Stack + DCD Reset_Handler ; 1 Reset Handler + DCD NMI_Handler ; 2 NMI Handler + DCD HardFault_Handler ; 3 Hard Fault Handler + DCD MemManage_Handler ; 4 MPU Fault Handler + DCD BusFault_Handler ; 5 Bus Fault Handler + DCD UsageFault_Handler ; 6 Usage Fault Handler + DCD Sign_Value ; 7 Reserved + DCD UnHandled_Vector ; 8 Reserved + DCD UnHandled_Vector ; 9 Reserved + DCD UnHandled_Vector ; 10 Reserved + DCD SVC_Handler ; 11 SVCall Handler + DCD DebugMon_Handler ; 12 Debug Monitor Handler + DCD UnHandled_Vector ; 13 Reserved + DCD PendSV_Handler ; 14 PendSV Handler + DCD SysTick_Handler ; 15 SysTick Handler + + ; External Interrupts + DCD DAC_IRQHandler ; 16 D/A Converter + DCD MX_CORE_IRQHandler ; 17 M0/M4 IRQ handler (LPC43XX ONLY) + DCD DMA_IRQHandler ; 18 General Purpose DMA + DCD UnHandled_Vector ; 19 Reserved + DCD FLASHEEPROM_IRQHandler ; 20 ORed flash bank A, flash bank B, EEPROM interrupts + DCD ETH_IRQHandler ; 21 Ethernet + DCD SDIO_IRQHandler ; 22 SD/MMC + DCD LCD_IRQHandler ; 23 LCD + DCD USB0_IRQHandler ; 24 USB0 + DCD USB1_IRQHandler ; 25 USB1 + DCD SCT_IRQHandler ; 26 State Configurable Timer + DCD RIT_IRQHandler ; 27 Repetitive Interrupt Timer + DCD TIMER0_IRQHandler ; 28 Timer0 + DCD TIMER1_IRQHandler ; 29 Timer1 + DCD TIMER2_IRQHandler ; 30 Timer2 + DCD TIMER3_IRQHandler ; 31 Timer3 + DCD MCPWM_IRQHandler ; 32 Motor Control PWM + DCD ADC0_IRQHandler ; 33 A/D Converter 0 + DCD I2C0_IRQHandler ; 34 I2C0 + DCD I2C1_IRQHandler ; 35 I2C1 + DCD SPI_IRQHandler ; 36 SPI (LPC43XX ONLY) + DCD ADC1_IRQHandler ; 37 A/D Converter 1 + DCD SSP0_IRQHandler ; 38 SSP0 + DCD SSP1_IRQHandler ; 39 SSP1 + DCD UART0_IRQHandler ; 40 UART0 + DCD UART1_IRQHandler ; 41 UART1 + DCD UART2_IRQHandler ; 42 UART2 + DCD UART3_IRQHandler ; 43 UART3 + DCD I2S0_IRQHandler ; 44 I2S0 + DCD I2S1_IRQHandler ; 45 I2S1 + DCD SPIFI_IRQHandler ; 46 SPI Flash Interface + DCD SGPIO_IRQHandler ; 47 SGPIO (LPC43XX ONLY) + DCD GPIO0_IRQHandler ; 48 GPIO0 + DCD GPIO1_IRQHandler ; 49 GPIO1 + DCD GPIO2_IRQHandler ; 50 GPIO2 + DCD GPIO3_IRQHandler ; 51 GPIO3 + DCD GPIO4_IRQHandler ; 52 GPIO4 + DCD GPIO5_IRQHandler ; 53 GPIO5 + DCD GPIO6_IRQHandler ; 54 GPIO6 + DCD GPIO7_IRQHandler ; 55 GPIO7 + DCD GINT0_IRQHandler ; 56 GINT0 + DCD GINT1_IRQHandler ; 57 GINT1 + DCD EVRT_IRQHandler ; 58 Event Router + DCD CAN1_IRQHandler ; 59 C_CAN1 + DCD UnHandled_Vector ; 60 Reserved + DCD VADC_IRQHandler ; 61 VADC + DCD ATIMER_IRQHandler ; 62 ATIMER + DCD RTC_IRQHandler ; 63 RTC + DCD UnHandled_Vector ; 64 Reserved + DCD WDT_IRQHandler ; 65 WDT + DCD UnHandled_Vector ; 66 M0s + DCD CAN0_IRQHandler ; 67 C_CAN0 + DCD QEI_IRQHandler ; 68 QEI + + +; IF :LNOT::DEF:NO_CRP +; AREA |.ARM.__at_0x02FC|, CODE, READONLY +;CRP_Key DCD 0xFFFFFFFF +; ENDIF + + AREA |.text|, CODE, READONLY + +; Reset Handler + +Reset_Handler PROC + EXPORT Reset_Handler [WEAK] + IMPORT __main + IMPORT SystemInit + LDR R0, =SystemInit + BLX R0 + LDR R0, =__main + BX R0 + ENDP + +; Dummy Exception Handlers (infinite loops which can be modified) + +NMI_Handler PROC + EXPORT NMI_Handler [WEAK] + B . + ENDP +HardFault_Handler\ + PROC + EXPORT HardFault_Handler [WEAK] + B . + ENDP +MemManage_Handler\ + PROC + EXPORT MemManage_Handler [WEAK] + B . + ENDP +BusFault_Handler\ + PROC + EXPORT BusFault_Handler [WEAK] + B . + ENDP +UsageFault_Handler\ + PROC + EXPORT UsageFault_Handler [WEAK] + B . + ENDP +SVC_Handler PROC + EXPORT SVC_Handler [WEAK] + B . + ENDP +DebugMon_Handler\ + PROC + EXPORT DebugMon_Handler [WEAK] + B . + ENDP +PendSV_Handler PROC + EXPORT PendSV_Handler [WEAK] + B . + ENDP +SysTick_Handler PROC + EXPORT SysTick_Handler [WEAK] + B . + ENDP +UnHandled_Vector PROC + EXPORT UnHandled_Vector [WEAK] + B . + ENDP + +Default_Handler PROC + + EXPORT DAC_IRQHandler [WEAK] + EXPORT MX_CORE_IRQHandler [WEAK] + EXPORT DMA_IRQHandler [WEAK] + EXPORT FLASHEEPROM_IRQHandler [WEAK] + EXPORT ETH_IRQHandler [WEAK] + EXPORT SDIO_IRQHandler [WEAK] + EXPORT LCD_IRQHandler [WEAK] + EXPORT USB0_IRQHandler [WEAK] + EXPORT USB1_IRQHandler [WEAK] + EXPORT SCT_IRQHandler [WEAK] + EXPORT RIT_IRQHandler [WEAK] + EXPORT TIMER0_IRQHandler [WEAK] + EXPORT TIMER1_IRQHandler [WEAK] + EXPORT TIMER2_IRQHandler [WEAK] + EXPORT TIMER3_IRQHandler [WEAK] + EXPORT MCPWM_IRQHandler [WEAK] + EXPORT ADC0_IRQHandler [WEAK] + EXPORT I2C0_IRQHandler [WEAK] + EXPORT I2C1_IRQHandler [WEAK] + EXPORT SPI_IRQHandler [WEAK] + EXPORT ADC1_IRQHandler [WEAK] + EXPORT SSP0_IRQHandler [WEAK] + EXPORT SSP1_IRQHandler [WEAK] + EXPORT UART0_IRQHandler [WEAK] + EXPORT UART1_IRQHandler [WEAK] + EXPORT UART2_IRQHandler [WEAK] + EXPORT UART3_IRQHandler [WEAK] + EXPORT I2S0_IRQHandler [WEAK] + EXPORT I2S1_IRQHandler [WEAK] + EXPORT SPIFI_IRQHandler [WEAK] + EXPORT SGPIO_IRQHandler [WEAK] + EXPORT GPIO0_IRQHandler [WEAK] + EXPORT GPIO1_IRQHandler [WEAK] + EXPORT GPIO2_IRQHandler [WEAK] + EXPORT GPIO3_IRQHandler [WEAK] + EXPORT GPIO4_IRQHandler [WEAK] + EXPORT GPIO5_IRQHandler [WEAK] + EXPORT GPIO6_IRQHandler [WEAK] + EXPORT GPIO7_IRQHandler [WEAK] + EXPORT GINT0_IRQHandler [WEAK] + EXPORT GINT1_IRQHandler [WEAK] + EXPORT EVRT_IRQHandler [WEAK] + EXPORT CAN1_IRQHandler [WEAK] + EXPORT VADC_IRQHandler [WEAK] + EXPORT ATIMER_IRQHandler [WEAK] + EXPORT RTC_IRQHandler [WEAK] + EXPORT WDT_IRQHandler [WEAK] + EXPORT CAN0_IRQHandler [WEAK] + EXPORT QEI_IRQHandler [WEAK] + +DAC_IRQHandler +MX_CORE_IRQHandler +DMA_IRQHandler +FLASHEEPROM_IRQHandler +ETH_IRQHandler +SDIO_IRQHandler +LCD_IRQHandler +USB0_IRQHandler +USB1_IRQHandler +SCT_IRQHandler +RIT_IRQHandler +TIMER0_IRQHandler +TIMER1_IRQHandler +TIMER2_IRQHandler +TIMER3_IRQHandler +MCPWM_IRQHandler +ADC0_IRQHandler +I2C0_IRQHandler +I2C1_IRQHandler +SPI_IRQHandler +ADC1_IRQHandler +SSP0_IRQHandler +SSP1_IRQHandler +UART0_IRQHandler +UART1_IRQHandler +UART2_IRQHandler +UART3_IRQHandler +I2S0_IRQHandler +I2S1_IRQHandler +SPIFI_IRQHandler +SGPIO_IRQHandler +GPIO0_IRQHandler +GPIO1_IRQHandler +GPIO2_IRQHandler +GPIO3_IRQHandler +GPIO4_IRQHandler +GPIO5_IRQHandler +GPIO6_IRQHandler +GPIO7_IRQHandler +GINT0_IRQHandler +GINT1_IRQHandler +EVRT_IRQHandler +CAN1_IRQHandler +VADC_IRQHandler +ATIMER_IRQHandler +RTC_IRQHandler +WDT_IRQHandler +CAN0_IRQHandler +QEI_IRQHandler + + B . + + ENDP + + ALIGN + +; User Initial Stack & Heap + + IF :DEF:__MICROLIB + + EXPORT __initial_sp + EXPORT __heap_base + EXPORT __heap_limit + + ELSE + + IMPORT __use_two_region_memory + EXPORT __user_initial_stackheap +__user_initial_stackheap + + LDR R0, = Heap_Mem + LDR R1, =(Stack_Mem + Stack_Size) + LDR R2, = (Heap_Mem + Heap_Size) + LDR R3, = Stack_Mem + BX LR + + ALIGN + + ENDIF + + END + diff --git a/bsp/xplorer4330/m4/Internal SRAM.ini b/bsp/xplorer4330/m4/Internal SRAM.ini new file mode 100644 index 0000000000..34b8613392 --- /dev/null +++ b/bsp/xplorer4330/m4/Internal SRAM.ini @@ -0,0 +1,10 @@ + +FUNC void Setup (unsigned int region) { + region &= 0xFFFF0000; + SP = _RDWORD(region); // Setup Stack Pointer + PC = _RDWORD(region + 4); // Setup Program Counter + _WDWORD(0xE000ED08, region); // Setup Vector Table Offset Register +} + +LOAD "build\\project.axf" INCREMENTAL +Setup(__scatterload); // Get ready to execute image in SRAM or whatever region it is in g,main diff --git a/bsp/xplorer4330/m4/SConscript b/bsp/xplorer4330/m4/SConscript new file mode 100644 index 0000000000..543bd56bbb --- /dev/null +++ b/bsp/xplorer4330/m4/SConscript @@ -0,0 +1,13 @@ +from building import * + +cwd = GetCurrentDir() +objs = [] +list = os.listdir(cwd+'\\..') + +for d in list: + if d!='m4': + path = os.path.join(cwd+'\\..', d) + if os.path.isfile(os.path.join(path, 'SConscript')): + objs = objs + SConscript(os.path.join(path, 'SConscript')) + +Return('objs') diff --git a/bsp/xplorer4330/m4/SConstruct b/bsp/xplorer4330/m4/SConstruct new file mode 100644 index 0000000000..8b788ed9fd --- /dev/null +++ b/bsp/xplorer4330/m4/SConstruct @@ -0,0 +1,37 @@ +import os +import sys +import rtconfig + +if os.getenv('RTT_ROOT'): + RTT_ROOT = os.getenv('RTT_ROOT') +else: + RTT_ROOT = os.path.normpath(os.getcwd() + '/../../..') + +sys.path = sys.path + [os.path.join(RTT_ROOT, 'tools')] +from building import * + +TARGET = 'rtthread.' + rtconfig.TARGET_EXT + +env = Environment(tools = ['mingw'], + AS = rtconfig.AS, ASFLAGS = rtconfig.AFLAGS, + CC = rtconfig.CC, CCFLAGS = rtconfig.CFLAGS, + AR = rtconfig.AR, ARFLAGS = '-rc', + LINK = rtconfig.LINK, LINKFLAGS = rtconfig.LFLAGS) +env.PrependENVPath('PATH', rtconfig.EXEC_PATH) + +if rtconfig.PLATFORM == 'iar': + env.Replace(CCCOM = ['$CC $CCFLAGS $CPPFLAGS $_CPPDEFFLAGS $_CPPINCFLAGS -o $TARGET $SOURCES']) + env.Replace(ARFLAGS = ['']) + env.Replace(LINKCOM = ['$LINK $SOURCES $LINKFLAGS -o $TARGET --map project.map']) + +Export('RTT_ROOT') +Export('rtconfig') + +# prepare building environment +objs = PrepareBuilding(env, RTT_ROOT, has_libcpu=False) + +# build program +env.Program(TARGET, objs) + +# end building +EndBuilding(TARGET) diff --git a/bsp/xplorer4330/m4/SPIFI 32MB Debug.ini b/bsp/xplorer4330/m4/SPIFI 32MB Debug.ini new file mode 100644 index 0000000000..34b8613392 --- /dev/null +++ b/bsp/xplorer4330/m4/SPIFI 32MB Debug.ini @@ -0,0 +1,10 @@ + +FUNC void Setup (unsigned int region) { + region &= 0xFFFF0000; + SP = _RDWORD(region); // Setup Stack Pointer + PC = _RDWORD(region + 4); // Setup Program Counter + _WDWORD(0xE000ED08, region); // Setup Vector Table Offset Register +} + +LOAD "build\\project.axf" INCREMENTAL +Setup(__scatterload); // Get ready to execute image in SRAM or whatever region it is in g,main diff --git a/bsp/xplorer4330/m4/lpc4330_xplorer_spifi32mb.ld b/bsp/xplorer4330/m4/lpc4330_xplorer_spifi32mb.ld new file mode 100644 index 0000000000..c852e75f92 --- /dev/null +++ b/bsp/xplorer4330/m4/lpc4330_xplorer_spifi32mb.ld @@ -0,0 +1,133 @@ +/* + * linker script for LPC4330 (32MB SPI Flash, 264kB SRAM ) with GNU ld + * lgnq 2012-12-12 + */ + +/* Program Entry, set to mark it as "used" and avoid gc */ +MEMORY +{ + CODE (rx) : ORIGIN = 0x14000000, LENGTH = 0x00100000 + DATA (rw) : ORIGIN = 0x10000000, LENGTH = 0x00020000 +} +ENTRY(Reset_Handler) +_system_stack_size = 0x200; + +SECTIONS +{ + .text : + { + . = ALIGN(4); + KEEP(*(.interrupt_vector)) /* Startup code */ + . = ALIGN(4); + *(.text) /* remaining code */ + *(.text.*) /* remaining code */ + *(.rodata) /* read-only data (constants) */ + *(.rodata*) + *(.glue_7) + *(.glue_7t) + *(.gnu.linkonce.t*) + + /* section information for finsh shell */ + . = ALIGN(4); + __fsymtab_start = .; + KEEP(*(FSymTab)) + __fsymtab_end = .; + . = ALIGN(4); + __vsymtab_start = .; + KEEP(*(VSymTab)) + __vsymtab_end = .; + . = ALIGN(4); + + . = ALIGN(4); + _etext = .; + } > CODE = 0 + + /* .ARM.exidx is sorted, so has to go in its own output section. */ + __exidx_start = .; + .ARM.exidx : + { + *(.ARM.exidx* .gnu.linkonce.armexidx.*) + + /* This is used by the startup in order to initialize the .data secion */ + _sidata = .; + } > CODE + __exidx_end = .; + + /* .data section which is used for initialized data */ + + .data : AT (_sidata) + { + . = ALIGN(4); + /* This is used by the startup in order to initialize the .data secion */ + _sdata = . ; + + *(.data) + *(.data.*) + *(.gnu.linkonce.d*) + + . = ALIGN(4); + /* This is used by the startup in order to initialize the .data secion */ + _edata = . ; + } >DATA + + .stack : + { + . = . + _system_stack_size; + . = ALIGN(4); + _estack = .; + } >DATA + + __bss_start = .; + .bss : + { + . = ALIGN(4); + /* This is used by the startup in order to initialize the .bss secion */ + _sbss = .; + + *(.bss) + *(.bss.*) + *(COMMON) + + . = ALIGN(4); + /* This is used by the startup in order to initialize the .bss secion */ + _ebss = . ; + *(.bss.init) + } > DATA + __bss_end = .; + + _end = .; + + /* Stabs debugging sections. */ + .stab 0 : { *(.stab) } + .stabstr 0 : { *(.stabstr) } + .stab.excl 0 : { *(.stab.excl) } + .stab.exclstr 0 : { *(.stab.exclstr) } + .stab.index 0 : { *(.stab.index) } + .stab.indexstr 0 : { *(.stab.indexstr) } + .comment 0 : { *(.comment) } + /* DWARF debug sections. + * Symbols in the DWARF debugging sections are relative to the beginning + * of the section so we begin them at 0. */ + /* DWARF 1 */ + .debug 0 : { *(.debug) } + .line 0 : { *(.line) } + /* GNU DWARF 1 extensions */ + .debug_srcinfo 0 : { *(.debug_srcinfo) } + .debug_sfnames 0 : { *(.debug_sfnames) } + /* DWARF 1.1 and DWARF 2 */ + .debug_aranges 0 : { *(.debug_aranges) } + .debug_pubnames 0 : { *(.debug_pubnames) } + /* DWARF 2 */ + .debug_info 0 : { *(.debug_info .gnu.linkonce.wi.*) } + .debug_abbrev 0 : { *(.debug_abbrev) } + .debug_line 0 : { *(.debug_line) } + .debug_frame 0 : { *(.debug_frame) } + .debug_str 0 : { *(.debug_str) } + .debug_loc 0 : { *(.debug_loc) } + .debug_macinfo 0 : { *(.debug_macinfo) } + /* SGI/MIPS DWARF 2 extensions */ + .debug_weaknames 0 : { *(.debug_weaknames) } + .debug_funcnames 0 : { *(.debug_funcnames) } + .debug_typenames 0 : { *(.debug_typenames) } + .debug_varnames 0 : { *(.debug_varnames) } +} diff --git a/bsp/xplorer4330/m4/lpc4330_xplorer_spifi32mb.sct b/bsp/xplorer4330/m4/lpc4330_xplorer_spifi32mb.sct new file mode 100644 index 0000000000..079d63c6e9 --- /dev/null +++ b/bsp/xplorer4330/m4/lpc4330_xplorer_spifi32mb.sct @@ -0,0 +1,15 @@ +; ************************************************************* +; *** Scatter-Loading Description File generated by uVision *** +; ************************************************************* + +LR_IROM1 0x14000000 0x00100000 { ; load region size_region + ER_IROM1 0x14000000 0x00100000 { ; load address = execution address + *.o (RESET, +First) + *(InRoot$$Sections) + .ANY (+RO) + } + RW_IRAM1 0x10000000 0x00020000 { ; RW data + .ANY (+RW +ZI) + } +} + diff --git a/bsp/xplorer4330/m4/lpc4330_xplorer_sram.sct b/bsp/xplorer4330/m4/lpc4330_xplorer_sram.sct new file mode 100644 index 0000000000..973b81ba93 --- /dev/null +++ b/bsp/xplorer4330/m4/lpc4330_xplorer_sram.sct @@ -0,0 +1,15 @@ +; ************************************************************* +; *** Scatter-Loading Description File generated by uVision *** +; ************************************************************* + +LR_IROM1 0x10000000 0x00018000 { ; load region size_region + ER_IROM1 0x10000000 0x00018000 { ; load address = execution address + *.o (RESET, +First) + *(InRoot$$Sections) + .ANY (+RO) + } + RW_IRAM1 0x10080000 0x0000A000 { ; RW data + .ANY (+RW +ZI) + } +} + diff --git a/bsp/xplorer4330/m4/project.uvopt b/bsp/xplorer4330/m4/project.uvopt new file mode 100644 index 0000000000..b3bc134391 --- /dev/null +++ b/bsp/xplorer4330/m4/project.uvopt @@ -0,0 +1,2148 @@ + + + + 1.0 + +

### uVision Project, (C) Keil Software
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0 + 0 + 0 + ..\..\..\components\net\lwip\src\core\timers.c + timers.c + 0 + 0 + + + 12 + 107 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + ..\..\..\components\net\lwip\src\core\udp.c + udp.c + 0 + 0 + + + 12 + 108 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + ..\..\..\components\net\lwip\src\core\ipv4\autoip.c + autoip.c + 0 + 0 + + + 12 + 109 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + ..\..\..\components\net\lwip\src\core\ipv4\icmp.c + icmp.c + 0 + 0 + + + 12 + 110 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + ..\..\..\components\net\lwip\src\core\ipv4\igmp.c + igmp.c + 0 + 0 + + + 12 + 111 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + ..\..\..\components\net\lwip\src\core\ipv4\inet.c + inet.c + 0 + 0 + + + 12 + 112 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + ..\..\..\components\net\lwip\src\core\ipv4\inet_chksum.c + inet_chksum.c + 0 + 0 + + + 12 + 113 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + ..\..\..\components\net\lwip\src\core\ipv4\ip.c + ip.c + 0 + 0 + + + 12 + 114 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + ..\..\..\components\net\lwip\src\core\ipv4\ip_addr.c + ip_addr.c + 0 + 0 + + + 12 + 115 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + ..\..\..\components\net\lwip\src\core\ipv4\ip_frag.c + ip_frag.c + 0 + 0 + + + 12 + 116 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + ..\..\..\components\net\lwip\src\netif\etharp.c + etharp.c + 0 + 0 + + + 12 + 117 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + ..\..\..\components\net\lwip\src\netif\ethernetif.c + ethernetif.c + 0 + 0 + + + 12 + 118 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + ..\..\..\components\net\lwip\src\netif\slipif.c + slipif.c + 0 + 0 + + + + diff --git a/bsp/xplorer4330/m4/project.uvproj b/bsp/xplorer4330/m4/project.uvproj new file mode 100644 index 0000000000..cf6a4b4e74 --- /dev/null +++ b/bsp/xplorer4330/m4/project.uvproj @@ -0,0 +1,1005 @@ + + + 1.1 +
### uVision Project, (C) Keil Software
+ + + project + 0x4 + ARM-ADS + + + LPC4330 + NXP (founded by Philips) + IRAM(0x10000000-0x1001FFFF) IRAM2(0x20000000-0x2000FFFF) CLOCK(12000000) CPUTYPE("Cortex-M4") FPU2 + + "STARTUP\NXP\LPC43xx\startup_LPC43xx.s" ("NXP LPC43xx Startup Code") + UL2CM3(-O975 -S0 -C0) + 6193 + LPC43xx.H + + + + + + + + + + SFD\NXP\LPC43xx\LPC43xx.SFR + 0 + + + + NXP\LPC43xx\ + NXP\LPC43xx\ + + 0 + 0 + 0 + 0 + 1 + + .\build\ + project + 1 + 0 + 0 + 1 + 1 + .\ + 1 + 0 + 0 + + 0 + 0 + + + 0 + 0 + 0 + 0 + + + 0 + 0 + + + 0 + 0 + + + 1 + 0 + fromelf --bin -o "$L@L.bin" "$L@L.axf" + + 0 + 0 + + 0 + + + + 0 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 3 + + + + + SARMCM3.DLL + -MPU + DCM.DLL + -pCM4 + SARMCM3.DLL + -MPU + TCM.DLL + -pCM4 + + + + 1 + 0 + 0 + 0 + 16 + + + 0 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + + + 1 + 1 + 0 + 1 + 1 + 1 + 0 + 1 + 0 + + 0 + 1 + + + + + + + + + + + + + .\SPIFI 32MB Debug.ini + BIN\UL2CM3.DLL + + + + + 1 + 0 + 0 + 1 + 1 + 4096 + + BIN\UL2CM3.DLL + "" () + + + + + 0 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 1 + 1 + 0 + 1 + 1 + 0 + 0 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 0 + "Cortex-M4" + + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 1 + 1 + 0 + 0 + 1 + 0 + 0 + 0 + 3 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 1 + 0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x10000000 + 0x20000 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 1 + 0x0 + 0x0 + + + 1 + 0x0 + 0x0 + + + 1 + 0x0 + 0x0 + + + 1 + 0x0 + 0x0 + + + 1 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x10000000 + 0x20000 + + + 0 + 0x20000000 + 0x10000 + + + + + + 1 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + + + CORE_M4 + + .;..\..\..\components\CMSIS\Include;..\..\..\components\drivers\include;..\..\..\components\finsh;..\..\..\components\init;..\..\..\include;..\..\..\libcpu\arm\common;..\..\..\libcpu\arm\cortex-m4;..\applications;..\drivers;..\libraries\lpc_board\board_common;..\libraries\lpc_board\boards_18xx_43xx\ngx_xplorer_18304330;..\libraries\lpc_board\boards_18xx_43xx\ngx_xplorer_18304330\ngx_xplorer_4330;..\libraries\lpc_chip\chip_18xx_43xx;..\libraries\lpc_chip\chip_common;..\libraries\lpc_ip + + + + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + + + NO_CRP + + + + + + 0 + 0 + 0 + 0 + 1 + 0 + 0x00000000 + 0x10000000 + .\lpc4330_xplorer_spifi32mb.sct + + + --keep __fsym_* --keep __vsym_* + + + + + + + + applications + + + application.c + 1 + ..\applications\application.c + + + + + startup.c + 1 + ..\applications\startup.c + + + + + drivers + + + platform.c + 1 + ..\drivers\platform.c + + + + + usart.c + 1 + ..\drivers\usart.c + + + + + lpc_board + + + board_ngx_xplorer_18304330.c + 1 + ..\libraries\lpc_board\boards_18xx_43xx\ngx_xplorer_18304330\board_ngx_xplorer_18304330.c + + + + + sysinit_ngx_xplorer_18304330.c + 1 + ..\libraries\lpc_board\boards_18xx_43xx\ngx_xplorer_18304330\sysinit_ngx_xplorer_18304330.c + + + + + lpc_chip + + + adc_18xx_43xx.c + 1 + ..\libraries\lpc_chip\chip_18xx_43xx\adc_18xx_43xx.c + + + + + atimer_18xx_43xx.c + 1 + ..\libraries\lpc_chip\chip_18xx_43xx\atimer_18xx_43xx.c + + + + + clock_18xx_43xx.c + 1 + ..\libraries\lpc_chip\chip_18xx_43xx\clock_18xx_43xx.c + + + + + emc_18xx_43xx.c + 1 + ..\libraries\lpc_chip\chip_18xx_43xx\emc_18xx_43xx.c + + + + + enet_18xx_43xx.c + 1 + ..\libraries\lpc_chip\chip_18xx_43xx\enet_18xx_43xx.c + + + + + evrt_18xx_43xx.c + 1 + ..\libraries\lpc_chip\chip_18xx_43xx\evrt_18xx_43xx.c + + + + + gpdma_18xx_43xx.c + 1 + ..\libraries\lpc_chip\chip_18xx_43xx\gpdma_18xx_43xx.c + + + + + gpio_18xx_43xx.c + 1 + ..\libraries\lpc_chip\chip_18xx_43xx\gpio_18xx_43xx.c + + + + + i2c_18xx_43xx.c + 1 + ..\libraries\lpc_chip\chip_18xx_43xx\i2c_18xx_43xx.c + + + + + i2s_18xx_43xx.c + 1 + ..\libraries\lpc_chip\chip_18xx_43xx\i2s_18xx_43xx.c + + + + + lcd_18xx_43xx.c + 1 + ..\libraries\lpc_chip\chip_18xx_43xx\lcd_18xx_43xx.c + + + + + rgu_18xx_43xx.c + 1 + ..\libraries\lpc_chip\chip_18xx_43xx\rgu_18xx_43xx.c + + + + + ritimer_18xx_43xx.c + 1 + ..\libraries\lpc_chip\chip_18xx_43xx\ritimer_18xx_43xx.c + + + + + rtc_18xx_43xx.c + 1 + ..\libraries\lpc_chip\chip_18xx_43xx\rtc_18xx_43xx.c + + + + + scu_18xx_43xx.c + 1 + ..\libraries\lpc_chip\chip_18xx_43xx\scu_18xx_43xx.c + + + + + sdmmc_18xx_43xx.c + 1 + ..\libraries\lpc_chip\chip_18xx_43xx\sdmmc_18xx_43xx.c + + + + + ssp_18xx_43xx.c + 1 + ..\libraries\lpc_chip\chip_18xx_43xx\ssp_18xx_43xx.c + + + + + uart_18xx_43xx.c + 1 + ..\libraries\lpc_chip\chip_18xx_43xx\uart_18xx_43xx.c + + + + + wwdt_18xx_43xx.c + 1 + ..\libraries\lpc_chip\chip_18xx_43xx\wwdt_18xx_43xx.c + + + + + mem_tests.c + 1 + ..\libraries\lpc_chip\chip_common\mem_tests.c + + + + + ring_buffer.c + 1 + ..\libraries\lpc_chip\chip_common\ring_buffer.c + + + + + lpc_ip + + + adc_001.c + 1 + ..\libraries\lpc_ip\adc_001.c + + + + + atimer_001.c + 1 + ..\libraries\lpc_ip\atimer_001.c + + + + + emc_001.c + 1 + ..\libraries\lpc_ip\emc_001.c + + + + + enet_001.c + 1 + ..\libraries\lpc_ip\enet_001.c + + + + + fpu_init.c + 1 + ..\libraries\lpc_ip\fpu_init.c + + + + + gpdma_001.c + 1 + ..\libraries\lpc_ip\gpdma_001.c + + + + + gpiogrpint_001.c + 1 + ..\libraries\lpc_ip\gpiogrpint_001.c + + + + + gpioint_001.c + 1 + ..\libraries\lpc_ip\gpioint_001.c + + + + + gpiopinint_001.c + 1 + ..\libraries\lpc_ip\gpiopinint_001.c + + + + + i2c_001.c + 1 + ..\libraries\lpc_ip\i2c_001.c + + + + + i2s_001.c + 1 + ..\libraries\lpc_ip\i2s_001.c + + + + + lcd_001.c + 1 + ..\libraries\lpc_ip\lcd_001.c + + + + + ritimer_001.c + 1 + ..\libraries\lpc_ip\ritimer_001.c + + + + + rtc_001.c + 1 + ..\libraries\lpc_ip\rtc_001.c + + + + + sdmmc_001.c + 1 + ..\libraries\lpc_ip\sdmmc_001.c + + + + + ssp_001.c + 1 + ..\libraries\lpc_ip\ssp_001.c + + + + + timer_001.c + 1 + ..\libraries\lpc_ip\timer_001.c + + + + + usart_001.c + 1 + ..\libraries\lpc_ip\usart_001.c + + + + + startup + + + keil_startup_lpc18xx43xx.s + 2 + ..\libraries\startup_code\keil_startup_lpc18xx43xx.s + + + + + Kernel + + + clock.c + 1 + ..\..\..\src\clock.c + + + + + device.c + 1 + ..\..\..\src\device.c + + + + + idle.c + 1 + ..\..\..\src\idle.c + + + + + ipc.c + 1 + ..\..\..\src\ipc.c + + + + + irq.c + 1 + ..\..\..\src\irq.c + + + + + kservice.c + 1 + ..\..\..\src\kservice.c + + + + + mem.c + 1 + ..\..\..\src\mem.c + + + + + memheap.c + 1 + ..\..\..\src\memheap.c + + + + + mempool.c + 1 + ..\..\..\src\mempool.c + + + + + object.c + 1 + ..\..\..\src\object.c + + + + + scheduler.c + 1 + ..\..\..\src\scheduler.c + + + + + thread.c + 1 + ..\..\..\src\thread.c + + + + + timer.c + 1 + ..\..\..\src\timer.c + + + + + CORTEX-M4 + + + cpuport.c + 1 + ..\..\..\libcpu\arm\cortex-m4\cpuport.c + + + + + context_rvds.S + 2 + ..\..\..\libcpu\arm\cortex-m4\context_rvds.S + + + + + backtrace.c + 1 + ..\..\..\libcpu\arm\common\backtrace.c + + + + + div0.c + 1 + ..\..\..\libcpu\arm\common\div0.c + + + + + showmem.c + 1 + ..\..\..\libcpu\arm\common\showmem.c + + + + + DeviceDrivers + + + serial.c + 1 + ..\..\..\components\drivers\serial\serial.c + + + + + completion.c + 1 + ..\..\..\components\drivers\src\completion.c + + + + + dataqueue.c + 1 + ..\..\..\components\drivers\src\dataqueue.c + + + + + pipe.c + 1 + ..\..\..\components\drivers\src\pipe.c + + + + + ringbuffer.c + 1 + ..\..\..\components\drivers\src\ringbuffer.c + + + + + finsh + + + cmd.c + 1 + ..\..\..\components\finsh\cmd.c + + + + + finsh_compiler.c + 1 + ..\..\..\components\finsh\finsh_compiler.c + + + + + finsh_error.c + 1 + ..\..\..\components\finsh\finsh_error.c + + + + + finsh_heap.c + 1 + ..\..\..\components\finsh\finsh_heap.c + + + + + finsh_init.c + 1 + ..\..\..\components\finsh\finsh_init.c + + + + + finsh_node.c + 1 + ..\..\..\components\finsh\finsh_node.c + + + + + finsh_ops.c + 1 + ..\..\..\components\finsh\finsh_ops.c + + + + + finsh_parser.c + 1 + ..\..\..\components\finsh\finsh_parser.c + + + + + finsh_token.c + 1 + ..\..\..\components\finsh\finsh_token.c + + + + + finsh_var.c + 1 + ..\..\..\components\finsh\finsh_var.c + + + + + finsh_vm.c + 1 + ..\..\..\components\finsh\finsh_vm.c + + + + + shell.c + 1 + ..\..\..\components\finsh\shell.c + + + + + symbol.c + 1 + ..\..\..\components\finsh\symbol.c + + + + + Components + + + components.c + 1 + ..\..\..\components\init\components.c + + + + + + + diff --git a/bsp/xplorer4330/m4/rtconfig.h b/bsp/xplorer4330/m4/rtconfig.h new file mode 100644 index 0000000000..e95982de89 --- /dev/null +++ b/bsp/xplorer4330/m4/rtconfig.h @@ -0,0 +1,201 @@ +#ifndef __RTTHREAD_CFG_H__ +#define __RTTHREAD_CFG_H__ + +// + +// +#define RT_NAME_MAX 8 +// +#define RT_ALIGN_SIZE 4 +// +// 8 +// 32 +// 256 +// +#define RT_THREAD_PRIORITY_MAX 32 +// +#define RT_TICK_PER_SECOND 100 +//
+#define RT_DEBUG +// +// #define RT_THREAD_DEBUG +// +#define RT_USING_OVERFLOW_CHECK +//
+ +// +#define RT_USING_HOOK + +//
+// #define RT_USING_TIMER_SOFT +// +#define RT_TIMER_THREAD_PRIO 4 +// +#define RT_TIMER_THREAD_STACK_SIZE 512 +// +#define RT_TIMER_TICK_PER_SECOND 10 +//
+ +//
+// +#define RT_USING_SEMAPHORE +// +#define RT_USING_MUTEX +// +#define RT_USING_EVENT +// +#define RT_USING_MAILBOX +// +#define RT_USING_MESSAGEQUEUE +//
+ +//
+// +#define RT_USING_MEMPOOL +// +#define RT_USING_MEMHEAP +// +#define RT_USING_HEAP +// +#define RT_USING_SMALL_MEM +// +// #define RT_USING_SLAB +//
+ +//
+#define RT_USING_DEVICE +// +#define RT_USING_SERIAL +#define RT_USING_DEVICE_IPC + +// +#define RT_USING_UART0 + +// +// #define RT_USING_UART3 +// +#define RT_UART_RX_BUFFER_SIZE 64 +//
+ +//
+#define RT_USING_CONSOLE +// +#define RT_CONSOLEBUF_SIZE 128 +// +#define RT_CONSOLE_DEVICE_NAME "uart0" +//
+ +// +#define RT_USING_COMPONENTS_INIT + +//
+#define RT_USING_FINSH +// +#define FINSH_USING_SYMTAB +// +#define FINSH_USING_DESCRIPTION +// +#define FINSH_THREAD_STACK_SIZE 4096 +//
+ +//
+// +// #define RT_USING_NEWLIB +// +// #define RT_USING_PTHREADS +//
+ +//
+// #define RT_USING_DFS +// +// #define DFS_USING_WORKDIR +// +#define DFS_FILESYSTEMS_MAX 2 +// +#define DFS_FD_MAX 4 +// +#define RT_USING_DFS_ELMFAT +// +// 1 +// 2 +// +#define RT_DFS_ELM_USE_LFN 1 +// +#define RT_DFS_ELM_MAX_LFN 64 +// +// #define RT_USING_DFS_YAFFS2 +// +// #define RT_USING_DFS_UFFS +// +// #define RT_USING_DFS_DEVFS +// +// #define RT_USING_DFS_NFS +// +#define RT_NFS_HOST_EXPORT "192.168.1.5:/" +//
+ +//
+// #define RT_USING_LWIP +// +#define RT_LWIP_ICMP +// +// #define RT_LWIP_IGMP +// +#define RT_LWIP_UDP +// +#define RT_LWIP_TCP +// +#define RT_LWIP_DNS +// +#define RT_LWIP_PBUF_NUM 4 +// +#define RT_LWIP_TCP_PCB_NUM 3 +// +#define RT_LWIP_TCP_SND_BUF 2048 +// +#define RT_LWIP_TCP_WND 2048 +// +// #define RT_LWIP_SNMP +// +// #define RT_LWIP_DHCP +// +#define RT_LWIP_TCP_SEG_NUM 4 +// +#define RT_LWIP_TCPTHREAD_PRIORITY 12 +// +#define RT_LWIP_TCPTHREAD_MBOX_SIZE 8 +// +#define RT_LWIP_TCPTHREAD_STACKSIZE 4096 +// +#define RT_LWIP_ETHTHREAD_PRIORITY 14 +// +#define RT_LWIP_ETHTHREAD_MBOX_SIZE 8 +// +#define RT_LWIP_ETHTHREAD_STACKSIZE 512 +// +#define RT_LWIP_IPADDR0 192 +#define RT_LWIP_IPADDR1 168 +#define RT_LWIP_IPADDR2 1 +#define RT_LWIP_IPADDR3 30 +// +#define RT_LWIP_GWADDR0 192 +#define RT_LWIP_GWADDR1 168 +#define RT_LWIP_GWADDR2 1 +#define RT_LWIP_GWADDR3 1 +// +#define RT_LWIP_MSKADDR0 255 +#define RT_LWIP_MSKADDR1 255 +#define RT_LWIP_MSKADDR2 255 +#define RT_LWIP_MSKADDR3 0 +//
+ +// +// #define RT_USING_CMSIS_OS +// +#define RT_USING_RTT_CMSIS +// +// #define RT_USING_BSP_CMSIS + +// + +#endif diff --git a/bsp/xplorer4330/m4/rtconfig.py b/bsp/xplorer4330/m4/rtconfig.py new file mode 100644 index 0000000000..7dc74d6b7d --- /dev/null +++ b/bsp/xplorer4330/m4/rtconfig.py @@ -0,0 +1,132 @@ +import os + +# toolchains options +ARCH='arm' +CPU='cortex-m4' +CROSS_TOOL='keil' + +if os.getenv('RTT_CC'): + CROSS_TOOL = os.getenv('RTT_CC') + +# cross_tool provides the cross compiler +# EXEC_PATH is the compiler execute path, for example, CodeSourcery, Keil MDK, IAR +if CROSS_TOOL == 'gcc': + PLATFORM = 'gcc' + EXEC_PATH = 'E:/Program Files/CodeSourcery/Sourcery G++ Lite/bin' +elif CROSS_TOOL == 'keil': + PLATFORM = 'armcc' + EXEC_PATH = 'C:/Keil' +elif CROSS_TOOL == 'iar': + print '================ERROR============================' + print 'Not support iar yet!' + print '=================================================' + exit(0) + +if os.getenv('RTT_EXEC_PATH'): + EXEC_PATH = os.getenv('RTT_EXEC_PATH') + +BUILD = 'debug' + +LPC43xx_BOARD = 'NGX_XPLORER_4330' +#LPC43xx_BOARD = 'NGX_XPLORER_1830' +#LPC43xx_BOARD = 'KEIL_MCB_4357' +#LPC43xx_BOARD = 'KEIL_MCB_1857' +#LPC43xx_BOARD = 'HITEX_EVA_4350' +#LPC43xx_BOARD = 'HITEX_EVA_1850' + +if PLATFORM == 'gcc': + # toolchains + PREFIX = 'arm-none-eabi-' + CC = PREFIX + 'gcc' + AS = PREFIX + 'gcc' + AR = PREFIX + 'ar' + LINK = PREFIX + 'gcc' + TARGET_EXT = 'axf' + SIZE = PREFIX + 'size' + OBJDUMP = PREFIX + 'objdump' + OBJCPY = PREFIX + 'objcopy' + + DEVICE = ' -mcpu=cortex-m4 -mthumb -mfpu=fpv4-sp-d16 -mfloat-abi=softfp -ffunction-sections -fdata-sections' + CFLAGS = DEVICE + AFLAGS = ' -c' + DEVICE + ' -x assembler-with-cpp' + LFLAGS = DEVICE + ' -Wl,--gc-sections,-Map=rtthread-lpc4330.map,-cref,-u,Reset_Handler -T lpc4330_xplorer_spifi32mb.ld' + + CPATH = '' + LPATH = '' + + if BUILD == 'debug': + CFLAGS += ' -O0 -gdwarf-2' + AFLAGS += ' -gdwarf-2' + else: + CFLAGS += ' -O2' + + POST_ACTION = OBJCPY + ' -O binary $TARGET rtthread.bin\n' + SIZE + ' $TARGET \n' + +elif PLATFORM == 'armcc': + # toolchains + CC = 'armcc' + AS = 'armasm' + AR = 'armar' + LINK = 'armlink' + TARGET_EXT = 'axf' + + DEVICE = ' --cpu Cortex-M4' + CFLAGS = DEVICE + ' --apcs=interwork' + AFLAGS = DEVICE + ' --apcs=interwork' + LFLAGS = DEVICE + ' --info sizes --info totals --info unused --info veneers --list rtthread.map --scatter lpc4330_xplorer_sram.sct' + +# CFLAGS += ' -I' + EXEC_PATH + '/ARM/RV31/INC' +# LFLAGS += ' --libpath ' + EXEC_PATH + '/ARM/RV31/LIB' + + EXEC_PATH += '/ARM/ARMCC/bin' + + if BUILD == 'debug': + CFLAGS += ' -g -O0' + AFLAGS += ' -g' + else: + CFLAGS += ' -O2' + + POST_ACTION = 'fromelf --bin $TARGET --output rtthread.bin \nfromelf -z $TARGET' + +elif PLATFORM == 'iar': + # toolchains + CC = 'iccarm' + AS = 'iasmarm' + AR = 'iarchive' + LINK = 'ilinkarm' + TARGET_EXT = 'out' + + DEVICE = ' -D USE_STDPERIPH_DRIVER' + ' -D STM32F10X_HD' + + CFLAGS = DEVICE + CFLAGS += ' --diag_suppress Pa050' + CFLAGS += ' --no_cse' + CFLAGS += ' --no_unroll' + CFLAGS += ' --no_inline' + CFLAGS += ' --no_code_motion' + CFLAGS += ' --no_tbaa' + CFLAGS += ' --no_clustering' + CFLAGS += ' --no_scheduling' + CFLAGS += ' --debug' + CFLAGS += ' --endian=little' + CFLAGS += ' --cpu=Cortex-M4' + CFLAGS += ' -e' + CFLAGS += ' --fpu=None' + CFLAGS += ' --dlib_config "' + IAR_PATH + '/arm/INC/c/DLib_Config_Normal.h"' + CFLAGS += ' -Ol' + CFLAGS += ' --use_c++_inline' + + AFLAGS = '' + AFLAGS += ' -s+' + AFLAGS += ' -w+' + AFLAGS += ' -r' + AFLAGS += ' --cpu Cortex-M4' + AFLAGS += ' --fpu None' + + LFLAGS = ' --config stm32f10x_flash.icf' + LFLAGS += ' --redirect _Printf=_PrintfTiny' + LFLAGS += ' --redirect _Scanf=_ScanfSmall' + LFLAGS += ' --entry __iar_program_start' + + EXEC_PATH = IAR_PATH + '/arm/bin/' + POST_ACTION = '' diff --git a/bsp/xplorer4330/m4/template.uvproj b/bsp/xplorer4330/m4/template.uvproj new file mode 100644 index 0000000000..b55a288d4c --- /dev/null +++ b/bsp/xplorer4330/m4/template.uvproj @@ -0,0 +1,393 @@ + + + + 1.1 + +
### uVision Project, (C) Keil Software
+ + + + project + 0x4 + ARM-ADS + + + LPC4330 + NXP (founded by Philips) + IRAM(0x10000000-0x1001FFFF) IRAM2(0x20000000-0x2000FFFF) CLOCK(12000000) CPUTYPE("Cortex-M4") FPU2 + + "STARTUP\NXP\LPC43xx\startup_LPC43xx.s" ("NXP LPC43xx Startup Code") + UL2CM3(-O975 -S0 -C0) + 6193 + LPC43xx.H + + + + + + + + + + SFD\NXP\LPC43xx\LPC43xx.SFR + 0 + + + + NXP\LPC43xx\ + NXP\LPC43xx\ + + 0 + 0 + 0 + 0 + 1 + + .\build\ + project + 1 + 0 + 0 + 1 + 1 + .\ + 1 + 0 + 0 + + 0 + 0 + + + 0 + 0 + 0 + 0 + + + 0 + 0 + + + 0 + 0 + + + 1 + 0 + fromelf --bin -o "$L@L.bin" "$L@L.axf" + + 0 + 0 + + 0 + + + + 0 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 3 + + + + + SARMCM3.DLL + -MPU + DCM.DLL + -pCM4 + SARMCM3.DLL + -MPU + TCM.DLL + -pCM4 + + + + 1 + 0 + 0 + 0 + 16 + + + 0 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + + + 1 + 1 + 0 + 1 + 1 + 1 + 0 + 1 + 0 + + 0 + 1 + + + + + + + + + + + + + .\SPIFI 32MB Debug.ini + BIN\UL2CM3.DLL + + + + + 1 + 0 + 0 + 1 + 1 + 4096 + + BIN\UL2CM3.DLL + "" () + + + + + 0 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 1 + 1 + 0 + 1 + 1 + 0 + 0 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 0 + "Cortex-M4" + + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 1 + 1 + 0 + 0 + 1 + 0 + 0 + 0 + 3 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 1 + 0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x10000000 + 0x20000 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 1 + 0x0 + 0x0 + + + 1 + 0x0 + 0x0 + + + 1 + 0x0 + 0x0 + + + 1 + 0x0 + 0x0 + + + 1 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x10000000 + 0x20000 + + + 0 + 0x20000000 + 0x10000 + + + + + + 1 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + + + + + + + + + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + + + NO_CRP + + + + + + 0 + 0 + 0 + 0 + 1 + 0 + 0x00000000 + 0x10000000 + .\lpc4330_xplorer_spifi32mb.sct + + + + + + + + + + + + diff --git a/libcpu/arm/cortex-m4/cpuport.c b/libcpu/arm/cortex-m4/cpuport.c index b8f00a7675..d320dccbb0 100644 --- a/libcpu/arm/cortex-m4/cpuport.c +++ b/libcpu/arm/cortex-m4/cpuport.c @@ -1,153 +1,160 @@ -/* - * File : cpuport.c - * This file is part of RT-Thread RTOS - * COPYRIGHT (C) 2006 - 2011, RT-Thread Development Team - * - * The license and distribution terms for this file may be - * found in the file LICENSE in this distribution or at - * http://www.rt-thread.org/license/LICENSE - * - * Change Logs: - * Date Author Notes - * 2011-10-21 Bernard the first version. - * 2011-10-27 aozima update for cortex-M4 FPU. - * 2011-12-31 aozima fixed stack align issues. - * 2012-01-01 aozima support context switch load/store FPU register. -*/ -#include - -#define USE_FPU /* ARMCC */ ( (defined ( __CC_ARM ) && defined ( __TARGET_FPU_VFP )) \ - /* IAR */ || (defined ( __ICCARM__ ) && defined ( __ARMVFP__ )) \ - /* GNU */ || (defined ( __GNUC__ ) && defined ( __VFP_FP__ ) && !defined(__SOFTFP__)) ) - -/* exception and interrupt handler table */ -rt_uint32_t rt_interrupt_from_thread, rt_interrupt_to_thread; -rt_uint32_t rt_thread_switch_interrupt_flag; - -struct exception_stack_frame -{ - rt_uint32_t r0; - rt_uint32_t r1; - rt_uint32_t r2; - rt_uint32_t r3; - rt_uint32_t r12; - rt_uint32_t lr; - rt_uint32_t pc; - rt_uint32_t psr; - -#if USE_FPU - /* FPU register */ - rt_uint32_t S0; - rt_uint32_t S1; - rt_uint32_t S2; - rt_uint32_t S3; - rt_uint32_t S4; - rt_uint32_t S5; - rt_uint32_t S6; - rt_uint32_t S7; - rt_uint32_t S8; - rt_uint32_t S9; - rt_uint32_t S10; - rt_uint32_t S11; - rt_uint32_t S12; - rt_uint32_t S13; - rt_uint32_t S14; - rt_uint32_t S15; - rt_uint32_t FPSCR; - rt_uint32_t NO_NAME; -#endif -}; - -struct stack_frame -{ - /* r4 ~ r11 register */ - rt_uint32_t r4; - rt_uint32_t r5; - rt_uint32_t r6; - rt_uint32_t r7; - rt_uint32_t r8; - rt_uint32_t r9; - rt_uint32_t r10; - rt_uint32_t r11; - -#if USE_FPU - /* FPU register s16 ~ s31 */ - rt_uint32_t s16; - rt_uint32_t s17; - rt_uint32_t s18; - rt_uint32_t s19; - rt_uint32_t s20; - rt_uint32_t s21; - rt_uint32_t s22; - rt_uint32_t s23; - rt_uint32_t s24; - rt_uint32_t s25; - rt_uint32_t s26; - rt_uint32_t s27; - rt_uint32_t s28; - rt_uint32_t s29; - rt_uint32_t s30; - rt_uint32_t s31; -#endif - - struct exception_stack_frame exception_stack_frame; -}; - -rt_uint8_t *rt_hw_stack_init(void *tentry, void *parameter, - rt_uint8_t *stack_addr, void *texit) -{ - struct stack_frame * stack_frame; - rt_uint8_t * stk; - unsigned long i; - - stk = stack_addr + sizeof(rt_uint32_t); - - stk -= sizeof(struct stack_frame); - stack_frame = (struct stack_frame *)stk; - - /* init all register */ - for(i=0; iexception_stack_frame.r0 = (unsigned long)parameter; /* r0 : argument */ - stack_frame->exception_stack_frame.r1 = 0; /* r1 */ - stack_frame->exception_stack_frame.r2 = 0; /* r2 */ - stack_frame->exception_stack_frame.r3 = 0; /* r3 */ - stack_frame->exception_stack_frame.r12 = 0; /* r12 */ - stack_frame->exception_stack_frame.lr = (unsigned long)texit; /* lr */ - stack_frame->exception_stack_frame.pc = (unsigned long)tentry; /* entry point, pc */ - stack_frame->exception_stack_frame.psr = 0x01000000L; /* PSR */ - - /* return task's current stack address */ - return stk; -} - -extern void rt_hw_interrupt_thread_switch(void); -extern long list_thread(void); -extern rt_thread_t rt_current_thread; -void rt_hw_hard_fault_exception(struct exception_stack_frame * exception_stack) -{ - rt_kprintf("psr: 0x%08x\n", exception_stack->psr); - rt_kprintf(" pc: 0x%08x\n", exception_stack->pc); - rt_kprintf(" lr: 0x%08x\n", exception_stack->lr); - rt_kprintf("r12: 0x%08x\n", exception_stack->r12); - rt_kprintf("r03: 0x%08x\n", exception_stack->r3); - rt_kprintf("r02: 0x%08x\n", exception_stack->r2); - rt_kprintf("r01: 0x%08x\n", exception_stack->r1); - rt_kprintf("r00: 0x%08x\n", exception_stack->r0); - - rt_kprintf("hard fault on thread: %s\n", rt_current_thread->name); -#ifdef RT_USING_FINSH - list_thread(); -#endif - while (1); -} - -void rt_hw_cpu_shutdown() -{ - rt_kprintf("shutdown...\n"); - - RT_ASSERT(0); -} +/* + * File : cpuport.c + * This file is part of RT-Thread RTOS + * COPYRIGHT (C) 2006 - 2012, RT-Thread Development Team + * + * The license and distribution terms for this file may be + * found in the file LICENSE in this distribution or at + * http://www.rt-thread.org/license/LICENSE + * + * Change Logs: + * Date Author Notes + * 2011-10-21 Bernard the first version. + * 2011-10-27 aozima update for cortex-M4 FPU. + * 2011-12-31 aozima fixed stack align issues. + * 2012-01-01 aozima support context switch load/store FPU register. + * 2012-12-11 lgnq fixed the coding style. + */ + +#include + +#define USE_FPU /* ARMCC */ ( (defined ( __CC_ARM ) && defined ( __TARGET_FPU_VFP )) \ + /* IAR */ || (defined ( __ICCARM__ ) && defined ( __ARMVFP__ )) \ + /* GNU */ || (defined ( __GNUC__ ) && defined ( __VFP_FP__ ) && !defined(__SOFTFP__)) ) + +/* exception and interrupt handler table */ +rt_uint32_t rt_interrupt_from_thread; +rt_uint32_t rt_interrupt_to_thread; +rt_uint32_t rt_thread_switch_interrupt_flag; + +struct exception_stack_frame +{ + rt_uint32_t r0; + rt_uint32_t r1; + rt_uint32_t r2; + rt_uint32_t r3; + rt_uint32_t r12; + rt_uint32_t lr; + rt_uint32_t pc; + rt_uint32_t psr; + +#if USE_FPU + /* FPU register */ + rt_uint32_t S0; + rt_uint32_t S1; + rt_uint32_t S2; + rt_uint32_t S3; + rt_uint32_t S4; + rt_uint32_t S5; + rt_uint32_t S6; + rt_uint32_t S7; + rt_uint32_t S8; + rt_uint32_t S9; + rt_uint32_t S10; + rt_uint32_t S11; + rt_uint32_t S12; + rt_uint32_t S13; + rt_uint32_t S14; + rt_uint32_t S15; + rt_uint32_t FPSCR; + rt_uint32_t NO_NAME; +#endif +}; + +struct stack_frame +{ + /* r4 ~ r11 register */ + rt_uint32_t r4; + rt_uint32_t r5; + rt_uint32_t r6; + rt_uint32_t r7; + rt_uint32_t r8; + rt_uint32_t r9; + rt_uint32_t r10; + rt_uint32_t r11; + +#if USE_FPU + /* FPU register s16 ~ s31 */ + rt_uint32_t s16; + rt_uint32_t s17; + rt_uint32_t s18; + rt_uint32_t s19; + rt_uint32_t s20; + rt_uint32_t s21; + rt_uint32_t s22; + rt_uint32_t s23; + rt_uint32_t s24; + rt_uint32_t s25; + rt_uint32_t s26; + rt_uint32_t s27; + rt_uint32_t s28; + rt_uint32_t s29; + rt_uint32_t s30; + rt_uint32_t s31; +#endif + + struct exception_stack_frame exception_stack_frame; +}; + +rt_uint8_t *rt_hw_stack_init(void *tentry, + void *parameter, + rt_uint8_t *stack_addr, + void *texit) +{ + struct stack_frame *stack_frame; + rt_uint8_t *stk; + unsigned long i; + + stk = stack_addr + sizeof(rt_uint32_t); + stk -= sizeof(struct stack_frame); + + stack_frame = (struct stack_frame *)stk; + + /* init all register */ + for (i = 0; i < sizeof(struct stack_frame) / sizeof(rt_uint32_t); i ++) + { + ((rt_uint32_t *)stack_frame)[i] = 0xdeadbeef; + } + + stack_frame->exception_stack_frame.r0 = (unsigned long)parameter; /* r0 : argument */ + stack_frame->exception_stack_frame.r1 = 0; /* r1 */ + stack_frame->exception_stack_frame.r2 = 0; /* r2 */ + stack_frame->exception_stack_frame.r3 = 0; /* r3 */ + stack_frame->exception_stack_frame.r12 = 0; /* r12 */ + stack_frame->exception_stack_frame.lr = (unsigned long)texit; /* lr */ + stack_frame->exception_stack_frame.pc = (unsigned long)tentry; /* entry point, pc */ + stack_frame->exception_stack_frame.psr = 0x01000000L; /* PSR */ + + /* return task's current stack address */ + return stk; +} + +extern void rt_hw_interrupt_thread_switch(void); +extern long list_thread(void); +extern rt_thread_t rt_current_thread; +void rt_hw_hard_fault_exception(struct exception_stack_frame *exception_stack) +{ + rt_kprintf("psr: 0x%08x\n", exception_stack->psr); + rt_kprintf(" pc: 0x%08x\n", exception_stack->pc); + rt_kprintf(" lr: 0x%08x\n", exception_stack->lr); + rt_kprintf("r12: 0x%08x\n", exception_stack->r12); + rt_kprintf("r03: 0x%08x\n", exception_stack->r3); + rt_kprintf("r02: 0x%08x\n", exception_stack->r2); + rt_kprintf("r01: 0x%08x\n", exception_stack->r1); + rt_kprintf("r00: 0x%08x\n", exception_stack->r0); + + rt_kprintf("hard fault on thread: %s\n", rt_current_thread->name); + +#ifdef RT_USING_FINSH + list_thread(); +#endif + + while (1); +} + +void rt_hw_cpu_shutdown(void) +{ + rt_kprintf("shutdown...\n"); + + RT_ASSERT(0); +}