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[gd32][drivers] auto formatted

This commit is contained in:
Meco Man 2021-03-12 00:03:36 +08:00
parent 849c99d2fa
commit 2e99d2855b
43 changed files with 559 additions and 559 deletions
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2
bsp/gd32103c-eval/drivers/drv_gpio.h
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@ -1,5 +1,5 @@
/* /*
* Copyright (c) 2006-2020, RT-Thread Development Team * Copyright (c) 2006-2021, RT-Thread Development Team
* *
* SPDX-License-Identifier: Apache-2.0 * SPDX-License-Identifier: Apache-2.0
* *

2
bsp/gd32303e-eval/drivers/board.h
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@ -19,7 +19,7 @@
#include <gd32f30x.h> #include <gd32f30x.h>
// <o> Internal SRAM memory size[Kbytes] <8-64> // <o> Internal SRAM memory size[Kbytes] <8-64>
// <i>Default: 64 // <i>Default: 64
#ifdef __ICCARM__ #ifdef __ICCARM__
// Use *.icf ram symbal, to avoid hardcode. // Use *.icf ram symbal, to avoid hardcode.
extern char __ICFEDIT_region_RAM_end__; extern char __ICFEDIT_region_RAM_end__;

2
bsp/gd32450z-eval/drivers/board.h
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@ -22,7 +22,7 @@
#define EXT_SDRAM_END (EXT_SDRAM_BEGIN + (32U * 1024 * 1024)) /* the end address of external SDRAM */ #define EXT_SDRAM_END (EXT_SDRAM_BEGIN + (32U * 1024 * 1024)) /* the end address of external SDRAM */
// <o> Internal SRAM memory size[Kbytes] <8-64> // <o> Internal SRAM memory size[Kbytes] <8-64>
// <i>Default: 64 // <i>Default: 64
#ifdef __ICCARM__ #ifdef __ICCARM__
// Use *.icf ram symbal, to avoid hardcode. // Use *.icf ram symbal, to avoid hardcode.
extern char __ICFEDIT_region_RAM_end__; extern char __ICFEDIT_region_RAM_end__;

28
bsp/gd32450z-eval/drivers/drv_enet.c
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@ -35,16 +35,16 @@
//#define EMAC_TX_DUMP //#define EMAC_TX_DUMP
#ifdef EMAC_DEBUG #ifdef EMAC_DEBUG
#define EMAC_TRACE rt_kprintf #define EMAC_TRACE rt_kprintf
#else #else
#define EMAC_TRACE(...) #define EMAC_TRACE(...)
#endif #endif
#define EMAC_RXBUFNB 4 #define EMAC_RXBUFNB 4
#define EMAC_TXBUFNB 2 #define EMAC_TXBUFNB 2
#define EMAC_PHY_AUTO 0 #define EMAC_PHY_AUTO 0
#define EMAC_PHY_10MBIT 1 #define EMAC_PHY_10MBIT 1
#define EMAC_PHY_100MBIT 2 #define EMAC_PHY_100MBIT 2
#define MAX_ADDR_LEN 6 #define MAX_ADDR_LEN 6
@ -55,7 +55,7 @@ struct gd32_emac
rt_uint8_t phy_mode; rt_uint8_t phy_mode;
/* interface address info. */ /* interface address info. */
rt_uint8_t dev_addr[MAX_ADDR_LEN]; /* hw address */ rt_uint8_t dev_addr[MAX_ADDR_LEN]; /* hw address */
struct rt_synopsys_eth * ETHERNET_MAC; struct rt_synopsys_eth * ETHERNET_MAC;
IRQn_Type ETHER_MAC_IRQ; IRQn_Type ETHER_MAC_IRQ;
@ -638,16 +638,16 @@ int rt_hw_gd32_eth_init(void)
gd32_emac_device0.dev_addr[4] = 0x34; gd32_emac_device0.dev_addr[4] = 0x34;
gd32_emac_device0.dev_addr[5] = 0x56; gd32_emac_device0.dev_addr[5] = 0x56;
gd32_emac_device0.parent.parent.init = gd32_emac_init; gd32_emac_device0.parent.parent.init = gd32_emac_init;
gd32_emac_device0.parent.parent.open = gd32_emac_open; gd32_emac_device0.parent.parent.open = gd32_emac_open;
gd32_emac_device0.parent.parent.close = gd32_emac_close; gd32_emac_device0.parent.parent.close = gd32_emac_close;
gd32_emac_device0.parent.parent.read = gd32_emac_read; gd32_emac_device0.parent.parent.read = gd32_emac_read;
gd32_emac_device0.parent.parent.write = gd32_emac_write; gd32_emac_device0.parent.parent.write = gd32_emac_write;
gd32_emac_device0.parent.parent.control = gd32_emac_control; gd32_emac_device0.parent.parent.control = gd32_emac_control;
gd32_emac_device0.parent.parent.user_data = RT_NULL; gd32_emac_device0.parent.parent.user_data = RT_NULL;
gd32_emac_device0.parent.eth_rx = gd32_emac_rx; gd32_emac_device0.parent.eth_rx = gd32_emac_rx;
gd32_emac_device0.parent.eth_tx = gd32_emac_tx; gd32_emac_device0.parent.eth_tx = gd32_emac_tx;
/* init tx buffer free semaphore */ /* init tx buffer free semaphore */
rt_sem_init(&gd32_emac_device0.tx_buf_free, "tx_buf0", EMAC_TXBUFNB, RT_IPC_FLAG_FIFO); rt_sem_init(&gd32_emac_device0.tx_buf_free, "tx_buf0", EMAC_TXBUFNB, RT_IPC_FLAG_FIFO);

2
bsp/gd32450z-eval/drivers/drv_lcd.c
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@ -131,7 +131,7 @@ static void lcd_config(void)
/* power on the LCD */ /* power on the LCD */
//lcd_power_on(); //lcd_power_on();
lcd_power_on3(); //New Version 3.5" TFT RGB Hardware needs use this initilize funtion ---By xufei 2016.10.21 lcd_power_on3(); //New Version 3.5" TFT RGB Hardware needs use this initilize funtion ---By xufei 2016.10.21
} }
/*! /*!

16
bsp/gd32450z-eval/drivers/drv_spi.c
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@ -56,8 +56,8 @@ static rt_err_t configure(struct rt_spi_device* device,
uint32_t spi_periph = f4_spi->spi_periph; uint32_t spi_periph = f4_spi->spi_periph;
RT_ASSERT(device != RT_NULL); RT_ASSERT(device != RT_NULL);
RT_ASSERT(configuration != RT_NULL); RT_ASSERT(configuration != RT_NULL);
/* data_width */ /* data_width */
if(configuration->data_width <= 8) if(configuration->data_width <= 8)
@ -165,7 +165,7 @@ static rt_err_t configure(struct rt_spi_device* device,
/* init SPI */ /* init SPI */
spi_init(spi_periph, &spi_init_struct); spi_init(spi_periph, &spi_init_struct);
/* Enable SPI_MASTER */ /* Enable SPI_MASTER */
spi_enable(spi_periph); spi_enable(spi_periph);
return RT_EOK; return RT_EOK;
}; };
@ -178,8 +178,8 @@ static rt_uint32_t xfer(struct rt_spi_device* device, struct rt_spi_message* mes
struct gd32_spi_cs * gd32_spi_cs = device->parent.user_data; struct gd32_spi_cs * gd32_spi_cs = device->parent.user_data;
uint32_t spi_periph = f4_spi->spi_periph; uint32_t spi_periph = f4_spi->spi_periph;
RT_ASSERT(device != NULL); RT_ASSERT(device != NULL);
RT_ASSERT(message != NULL); RT_ASSERT(message != NULL);
/* take CS */ /* take CS */
if(message->cs_take) if(message->cs_take)
@ -210,7 +210,7 @@ static rt_uint32_t xfer(struct rt_spi_device* device, struct rt_spi_message* mes
//Wait until the transmit buffer is empty //Wait until the transmit buffer is empty
while(RESET == spi_i2s_flag_get(spi_periph, SPI_FLAG_TBE)); while(RESET == spi_i2s_flag_get(spi_periph, SPI_FLAG_TBE));
// Send the byte // Send the byte
spi_i2s_data_transmit(spi_periph, data); spi_i2s_data_transmit(spi_periph, data);
//Wait until a data is received //Wait until a data is received
while(RESET == spi_i2s_flag_get(spi_periph, SPI_FLAG_RBNE)); while(RESET == spi_i2s_flag_get(spi_periph, SPI_FLAG_RBNE));
@ -242,7 +242,7 @@ static rt_uint32_t xfer(struct rt_spi_device* device, struct rt_spi_message* mes
//Wait until the transmit buffer is empty //Wait until the transmit buffer is empty
while(RESET == spi_i2s_flag_get(spi_periph, SPI_FLAG_TBE)); while(RESET == spi_i2s_flag_get(spi_periph, SPI_FLAG_TBE));
// Send the byte // Send the byte
spi_i2s_data_transmit(spi_periph, data); spi_i2s_data_transmit(spi_periph, data);
//Wait until a data is received //Wait until a data is received
while(RESET == spi_i2s_flag_get(spi_periph, SPI_FLAG_RBNE)); while(RESET == spi_i2s_flag_get(spi_periph, SPI_FLAG_RBNE));
@ -260,7 +260,7 @@ static rt_uint32_t xfer(struct rt_spi_device* device, struct rt_spi_message* mes
/* release CS */ /* release CS */
if(message->cs_release) if(message->cs_release)
{ {
gpio_bit_set(gd32_spi_cs->GPIOx, gd32_spi_cs->GPIO_Pin); gpio_bit_set(gd32_spi_cs->GPIOx, gd32_spi_cs->GPIO_Pin);
DEBUG_PRINTF("spi release cs\n"); DEBUG_PRINTF("spi release cs\n");
} }

4
bsp/gd32450z-eval/drivers/drv_spi.h
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@ -36,7 +36,7 @@ struct gd32_spi_cs
/* public function */ /* public function */
rt_err_t gd32_spi_bus_register(uint32_t spi_periph, rt_err_t gd32_spi_bus_register(uint32_t spi_periph,
//struct gd32_spi_bus * gd32_spi, //struct gd32_spi_bus * gd32_spi,
const char * spi_bus_name); const char * spi_bus_name);
#endif // gd32F20X_40X_SPI_H_INCLUDED #endif // gd32F20X_40X_SPI_H_INCLUDED

24
bsp/gd32450z-eval/drivers/drv_spi_flash.c
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@ -32,7 +32,7 @@ static int rt_hw_spi5_init(void)
{ {
/* register spi bus */ /* register spi bus */
{ {
rt_err_t result; rt_err_t result;
rcu_periph_clock_enable(RCU_GPIOG); rcu_periph_clock_enable(RCU_GPIOG);
rcu_periph_clock_enable(RCU_SPI5); rcu_periph_clock_enable(RCU_SPI5);
@ -42,18 +42,18 @@ static int rt_hw_spi5_init(void)
gpio_mode_set(GPIOG, GPIO_MODE_AF, GPIO_PUPD_NONE, GPIO_PIN_10|GPIO_PIN_11| GPIO_PIN_12|GPIO_PIN_13| GPIO_PIN_14); gpio_mode_set(GPIOG, GPIO_MODE_AF, GPIO_PUPD_NONE, GPIO_PIN_10|GPIO_PIN_11| GPIO_PIN_12|GPIO_PIN_13| GPIO_PIN_14);
gpio_output_options_set(GPIOG, GPIO_OTYPE_PP, GPIO_OSPEED_200MHZ, GPIO_PIN_10|GPIO_PIN_11| GPIO_PIN_12|GPIO_PIN_13| GPIO_PIN_14); gpio_output_options_set(GPIOG, GPIO_OTYPE_PP, GPIO_OSPEED_200MHZ, GPIO_PIN_10|GPIO_PIN_11| GPIO_PIN_12|GPIO_PIN_13| GPIO_PIN_14);
result = gd32_spi_bus_register(SPI5, SPI_BUS_NAME); result = gd32_spi_bus_register(SPI5, SPI_BUS_NAME);
if (result != RT_EOK) if (result != RT_EOK)
{ {
return result; return result;
} }
} }
/* attach cs */ /* attach cs */
{ {
static struct rt_spi_device spi_device; static struct rt_spi_device spi_device;
static struct gd32_spi_cs spi_cs; static struct gd32_spi_cs spi_cs;
rt_err_t result; rt_err_t result;
spi_cs.GPIOx = GPIOG; spi_cs.GPIOx = GPIOG;
spi_cs.GPIO_Pin = GPIO_PIN_9; spi_cs.GPIO_Pin = GPIO_PIN_9;
@ -65,13 +65,13 @@ static int rt_hw_spi5_init(void)
gpio_bit_set(GPIOG,GPIO_PIN_9); gpio_bit_set(GPIOG,GPIO_PIN_9);
result = rt_spi_bus_attach_device(&spi_device, SPI_FLASH_DEVICE_NAME, SPI_BUS_NAME, (void*)&spi_cs); result = rt_spi_bus_attach_device(&spi_device, SPI_FLASH_DEVICE_NAME, SPI_BUS_NAME, (void*)&spi_cs);
if (result != RT_EOK) if (result != RT_EOK)
{ {
return result; return result;
} }
} }
return RT_EOK; return RT_EOK;
} }
INIT_DEVICE_EXPORT(rt_hw_spi5_init); INIT_DEVICE_EXPORT(rt_hw_spi5_init);
@ -83,7 +83,7 @@ static int rt_hw_spi_flash_with_sfud_init(void)
return RT_ERROR; return RT_ERROR;
}; };
return RT_EOK; return RT_EOK;
} }
INIT_COMPONENT_EXPORT(rt_hw_spi_flash_with_sfud_init) INIT_COMPONENT_EXPORT(rt_hw_spi_flash_with_sfud_init)
#endif #endif

136
bsp/gd32450z-eval/drivers/gd32f450z_lcd_eval.c
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@ -228,80 +228,80 @@ void lcd_power_on(void)
} }
/** /**
* @brief New Version 3.5" TFT RGB Hardware needs add this initilize funtion ---By xufei 2016.10.21 * @brief New Version 3.5" TFT RGB Hardware needs add this initilize funtion ---By xufei 2016.10.21
Modified by GAO HAIYANG, test pass, 17, Nov, 2016 Modified by GAO HAIYANG, test pass, 17, Nov, 2016
* @param None * @param None
* @retval None * @retval None
*/ */
void lcd_power_on3(void) void lcd_power_on3(void)
{ {
lcd_command_write(0xC0);//power control1 command/w/ lcd_command_write(0xC0);//power control1 command/w/
lcd_data_write(0x0A); // P-Gamma level//4.1875v lcd_data_write(0x0A); // P-Gamma level//4.1875v
lcd_data_write(0x0A); // N-Gamma level lcd_data_write(0x0A); // N-Gamma level
lcd_command_write(0xC1); // BT & VC Setting//power contrl2 command/w/ lcd_command_write(0xC1); // BT & VC Setting//power contrl2 command/w/
lcd_data_write(0x41); lcd_data_write(0x41);
lcd_data_write(0x07); // VCI1 = 2.5V lcd_data_write(0x07); // VCI1 = 2.5V
lcd_command_write(0xC2); // DC1.DC0 Setting//power control3 for normal mode lcd_command_write(0xC2); // DC1.DC0 Setting//power control3 for normal mode
lcd_data_write(0x33); lcd_data_write(0x33);
lcd_command_write(0xC5);//VCOM control lcd_command_write(0xC5);//VCOM control
lcd_data_write(0x00); //NV memory is not programmed lcd_data_write(0x00); //NV memory is not programmed
lcd_data_write(0x42); // VCM Setting lcd_data_write(0x42); // VCM Setting
lcd_data_write(0x80); // VCM Register Enable lcd_data_write(0x80); // VCM Register Enable
lcd_command_write(0xB0); //interface mode control //Polarity Setting lcd_command_write(0xB0); //interface mode control //Polarity Setting
lcd_data_write(0x02); lcd_data_write(0x02);
lcd_command_write(0xB1);//frame rate control for normal mode lcd_command_write(0xB1);//frame rate control for normal mode
lcd_data_write(0xB0); // Frame Rate Setting//70 frame per second//no division for internal clocks lcd_data_write(0xB0); // Frame Rate Setting//70 frame per second//no division for internal clocks
lcd_data_write(0x11);//17 clocks per line period for idle mode at cpu interface lcd_data_write(0x11);//17 clocks per line period for idle mode at cpu interface
lcd_command_write(0xB4);//dispaly inversion control lcd_command_write(0xB4);//dispaly inversion control
lcd_data_write(0x00); // disable Z-inversion , column inversion lcd_data_write(0x00); // disable Z-inversion , column inversion
lcd_command_write(0xB6); //display function control// RM.DM Setting lcd_command_write(0xB6); //display function control// RM.DM Setting
lcd_data_write(0x70);////0xF0 lcd_data_write(0x70);////0xF0
lcd_data_write(0x02);//direction of gate scan: G1->G480 one by one, source scan: S1->S960, scan cycle if interval scan in non-display area lcd_data_write(0x02);//direction of gate scan: G1->G480 one by one, source scan: S1->S960, scan cycle if interval scan in non-display area
lcd_data_write(0x3B); // number of lines to drive LCD: 8*(0x3C) = 480 lcd_data_write(0x3B); // number of lines to drive LCD: 8*(0x3C) = 480
lcd_command_write(0xB7); // Entry Mode lcd_command_write(0xB7); // Entry Mode
lcd_data_write(0x07); // disable low voltage detection, normal display, lcd_data_write(0x07); // disable low voltage detection, normal display,
lcd_command_write(0xF0); // Enter ENG , must be set before gamma setting lcd_command_write(0xF0); // Enter ENG , must be set before gamma setting
lcd_data_write(0x36); lcd_data_write(0x36);
lcd_data_write(0xA5); lcd_data_write(0xA5);
lcd_data_write(0xD3); lcd_data_write(0xD3);
lcd_command_write(0xE5); // Open gamma function , must be set before gamma setting lcd_command_write(0xE5); // Open gamma function , must be set before gamma setting
lcd_data_write(0x80); lcd_data_write(0x80);
lcd_command_write(0xE5); // Page 1 lcd_command_write(0xE5); // Page 1
lcd_data_write(0x01); lcd_data_write(0x01);
lcd_command_write(0XB3); // WEMODE=0(Page 1) , pixels over window setting will be ignored.//frame rate control in partial mode/full colors lcd_command_write(0XB3); // WEMODE=0(Page 1) , pixels over window setting will be ignored.//frame rate control in partial mode/full colors
lcd_data_write(0x00); lcd_data_write(0x00);
lcd_command_write(0xE5); // Page 0 lcd_command_write(0xE5); // Page 0
lcd_data_write(0x00); lcd_data_write(0x00);
lcd_command_write(0xF0); // Exit ENG , must be set before gamma setting lcd_command_write(0xF0); // Exit ENG , must be set before gamma setting
lcd_data_write(0x36); lcd_data_write(0x36);
lcd_data_write(0xA5); lcd_data_write(0xA5);
lcd_data_write(0x53); lcd_data_write(0x53);
lcd_command_write(0xE0); // Gamma setting lcd_command_write(0xE0); // Gamma setting
//y fine adjustment register for positive polarity //y fine adjustment register for positive polarity
lcd_data_write(0x00); lcd_data_write(0x00);
lcd_data_write(0x35); lcd_data_write(0x35);
lcd_data_write(0x33); lcd_data_write(0x33);
//y gradient adjustment register for positive polarity //y gradient adjustment register for positive polarity
lcd_data_write(0x00); lcd_data_write(0x00);
//y amplitude adjustment register for positive polarity //y amplitude adjustment register for positive polarity
lcd_data_write(0x00); lcd_data_write(0x00);
lcd_data_write(0x00); lcd_data_write(0x00);
//y fine adjustment register for negative polarity //y fine adjustment register for negative polarity
lcd_data_write(0x00); lcd_data_write(0x00);
lcd_data_write(0x35); lcd_data_write(0x35);
lcd_data_write(0x33); lcd_data_write(0x33);
//y gradient adjustment register for negative polarity //y gradient adjustment register for negative polarity
lcd_data_write(0x00); lcd_data_write(0x00);
//y amplitude adjustment register for negative polarity //y amplitude adjustment register for negative polarity
lcd_data_write(0x00); lcd_data_write(0x00);
lcd_data_write(0x00); lcd_data_write(0x00);
lcd_command_write(0x36); // memory data access control // lcd_command_write(0x36); // memory data access control //
lcd_data_write(0x48);// lcd_data_write(0x48);//
lcd_command_write(0x3A); // interface pixel format setting lcd_command_write(0x3A); // interface pixel format setting
lcd_data_write(0x55);//16-bits lcd_data_write(0x55);//16-bits
lcd_command_write(0x11); // Exit sleep mode lcd_command_write(0x11); // Exit sleep mode
lcd_command_write(0x29); // Display on lcd_command_write(0x29); // Display on
delay(10); delay(10);
} }
/*! /*!
\brief insert a delay time \brief insert a delay time

286
bsp/gd32450z-eval/drivers/synopsys_emac.h
View File

@ -48,8 +48,8 @@
#define EMAC_MACCR_RD ((rt_uint32_t)0x00000200) /* Retry disable */ #define EMAC_MACCR_RD ((rt_uint32_t)0x00000200) /* Retry disable */
#define EMAC_MACCR_APCS ((rt_uint32_t)0x00000080) /* Automatic Pad/CRC stripping */ #define EMAC_MACCR_APCS ((rt_uint32_t)0x00000080) /* Automatic Pad/CRC stripping */
#define EMAC_MACCR_BL ((rt_uint32_t)0x00000060) /* Back-off limit: random integer number (r) of slot time delays before rescheduling #define EMAC_MACCR_BL ((rt_uint32_t)0x00000060) /* Back-off limit: random integer number (r) of slot time delays before rescheduling
a transmission attempt during retries after a collision: 0 =< r <2^k */ a transmission attempt during retries after a collision: 0 =< r <2^k */
#define EMAC_MACCR_BL_10 ((rt_uint32_t)0x00000000) /* k = min (n, 10) */ #define EMAC_MACCR_BL_10 ((rt_uint32_t)0x00000000) /* k = min (n, 10) */
#define EMAC_MACCR_BL_8 ((rt_uint32_t)0x00000020) /* k = min (n, 8) */ #define EMAC_MACCR_BL_8 ((rt_uint32_t)0x00000020) /* k = min (n, 8) */
#define EMAC_MACCR_BL_4 ((rt_uint32_t)0x00000040) /* k = min (n, 4) */ #define EMAC_MACCR_BL_4 ((rt_uint32_t)0x00000040) /* k = min (n, 4) */
#define EMAC_MACCR_BL_1 ((rt_uint32_t)0x00000060) /* k = min (n, 1) */ #define EMAC_MACCR_BL_1 ((rt_uint32_t)0x00000060) /* k = min (n, 1) */
@ -60,45 +60,45 @@
/* Bit definition for Ethernet MAC Frame Filter Register */ /* Bit definition for Ethernet MAC Frame Filter Register */
#define EMAC_MACFFR_RA ((rt_uint32_t)0x80000000) /* Receive all */ #define EMAC_MACFFR_RA ((rt_uint32_t)0x80000000) /* Receive all */
#define EMAC_MACFFR_HPF ((rt_uint32_t)0x00000400) /* Hash or perfect filter */ #define EMAC_MACFFR_HPF ((rt_uint32_t)0x00000400) /* Hash or perfect filter */
#define EMAC_MACFFR_SAF ((rt_uint32_t)0x00000200) /* Source address filter enable */ #define EMAC_MACFFR_SAF ((rt_uint32_t)0x00000200) /* Source address filter enable */
#define EMAC_MACFFR_SAIF ((rt_uint32_t)0x00000100) /* SA inverse filtering */ #define EMAC_MACFFR_SAIF ((rt_uint32_t)0x00000100) /* SA inverse filtering */
#define EMAC_MACFFR_PCF ((rt_uint32_t)0x000000C0) /* Pass control frames: 3 cases */ #define EMAC_MACFFR_PCF ((rt_uint32_t)0x000000C0) /* Pass control frames: 3 cases */
#define EMAC_MACFFR_PCF_BlockAll ((rt_uint32_t)0x00000040) /* MAC filters all control frames from reaching the application */ #define EMAC_MACFFR_PCF_BlockAll ((rt_uint32_t)0x00000040) /* MAC filters all control frames from reaching the application */
#define EMAC_MACFFR_PCF_ForwardAll ((rt_uint32_t)0x00000080) /* MAC forwards all control frames to application even if they fail the Address Filter */ #define EMAC_MACFFR_PCF_ForwardAll ((rt_uint32_t)0x00000080) /* MAC forwards all control frames to application even if they fail the Address Filter */
#define EMAC_MACFFR_PCF_ForwardPassedAddrFilter ((rt_uint32_t)0x000000C0) /* MAC forwards control frames that pass the Address Filter. */ #define EMAC_MACFFR_PCF_ForwardPassedAddrFilter ((rt_uint32_t)0x000000C0) /* MAC forwards control frames that pass the Address Filter. */
#define EMAC_MACFFR_BFD ((rt_uint32_t)0x00000020) /* Broadcast frame disable */ #define EMAC_MACFFR_BFD ((rt_uint32_t)0x00000020) /* Broadcast frame disable */
#define EMAC_MACFFR_PAM ((rt_uint32_t)0x00000010) /* Pass all mutlicast */ #define EMAC_MACFFR_PAM ((rt_uint32_t)0x00000010) /* Pass all mutlicast */
#define EMAC_MACFFR_DAIF ((rt_uint32_t)0x00000008) /* DA Inverse filtering */ #define EMAC_MACFFR_DAIF ((rt_uint32_t)0x00000008) /* DA Inverse filtering */
#define EMAC_MACFFR_HM ((rt_uint32_t)0x00000004) /* Hash multicast */ #define EMAC_MACFFR_HM ((rt_uint32_t)0x00000004) /* Hash multicast */
#define EMAC_MACFFR_HU ((rt_uint32_t)0x00000002) /* Hash unicast */ #define EMAC_MACFFR_HU ((rt_uint32_t)0x00000002) /* Hash unicast */
#define EMAC_MACFFR_PM ((rt_uint32_t)0x00000001) /* Promiscuous mode */ #define EMAC_MACFFR_PM ((rt_uint32_t)0x00000001) /* Promiscuous mode */
/* Bit definition for Ethernet MAC Hash Table High Register */ /* Bit definition for Ethernet MAC Hash Table High Register */
#define EMAC_MACHTHR_HTH ((rt_uint32_t)0xFFFFFFFF) /* Hash table high */ #define EMAC_MACHTHR_HTH ((rt_uint32_t)0xFFFFFFFF) /* Hash table high */
/* Bit definition for Ethernet MAC Hash Table Low Register */ /* Bit definition for Ethernet MAC Hash Table Low Register */
#define EMAC_MACHTLR_HTL ((rt_uint32_t)0xFFFFFFFF) /* Hash table low */ #define EMAC_MACHTLR_HTL ((rt_uint32_t)0xFFFFFFFF) /* Hash table low */
/* Bit definition for Ethernet MAC MII Address Register */ /* Bit definition for Ethernet MAC MII Address Register */
#define EMAC_MACMIIAR_PA ((rt_uint32_t)0x0000F800) /* Physical layer address */ #define EMAC_MACMIIAR_PA ((rt_uint32_t)0x0000F800) /* Physical layer address */
#define EMAC_MACMIIAR_MR ((rt_uint32_t)0x000007C0) /* MII register in the selected PHY */ #define EMAC_MACMIIAR_MR ((rt_uint32_t)0x000007C0) /* MII register in the selected PHY */
#define EMAC_MACMIIAR_CR ((rt_uint32_t)0x0000001C) /* CR clock range: 6 cases */ #define EMAC_MACMIIAR_CR ((rt_uint32_t)0x0000001C) /* CR clock range: 6 cases */
#define EMAC_MACMIIAR_CR_Div42 ((rt_uint32_t)0x00000000) /* HCLK:60-100 MHz; MDC clock= HCLK/42 */ #define EMAC_MACMIIAR_CR_Div42 ((rt_uint32_t)0x00000000) /* HCLK:60-100 MHz; MDC clock= HCLK/42 */
#define EMAC_MACMIIAR_CR_Div62 ((rt_uint32_t)0x00000004) /* HCLK:100-150 MHz; MDC clock= HCLK/62 */ #define EMAC_MACMIIAR_CR_Div62 ((rt_uint32_t)0x00000004) /* HCLK:100-150 MHz; MDC clock= HCLK/62 */
#define EMAC_MACMIIAR_CR_Div16 ((rt_uint32_t)0x00000008) /* HCLK:20-35 MHz; MDC clock= HCLK/16 */ #define EMAC_MACMIIAR_CR_Div16 ((rt_uint32_t)0x00000008) /* HCLK:20-35 MHz; MDC clock= HCLK/16 */
#define EMAC_MACMIIAR_CR_Div26 ((rt_uint32_t)0x0000000C) /* HCLK:35-60 MHz; MDC clock= HCLK/26 */ #define EMAC_MACMIIAR_CR_Div26 ((rt_uint32_t)0x0000000C) /* HCLK:35-60 MHz; MDC clock= HCLK/26 */
#define EMAC_MACMIIAR_CR_Div102 ((rt_uint32_t)0x00000010) /* HCLK:150-250 MHz; MDC clock= HCLK/102 */ #define EMAC_MACMIIAR_CR_Div102 ((rt_uint32_t)0x00000010) /* HCLK:150-250 MHz; MDC clock= HCLK/102 */
#define EMAC_MACMIIAR_CR_Div122 ((rt_uint32_t)0x00000014) /* HCLK:250-300 MHz; MDC clock= HCLK/122*/ #define EMAC_MACMIIAR_CR_Div122 ((rt_uint32_t)0x00000014) /* HCLK:250-300 MHz; MDC clock= HCLK/122*/
#define EMAC_MACMIIAR_MW ((rt_uint32_t)0x00000002) /* MII write */ #define EMAC_MACMIIAR_MW ((rt_uint32_t)0x00000002) /* MII write */
#define EMAC_MACMIIAR_MB ((rt_uint32_t)0x00000001) /* MII busy */ #define EMAC_MACMIIAR_MB ((rt_uint32_t)0x00000001) /* MII busy */
/* Bit definition for Ethernet MAC MII Data Register */ /* Bit definition for Ethernet MAC MII Data Register */
#define EMAC_MACMIIDR_MD ((rt_uint32_t)0x0000FFFF) /* MII data: read/write data from/to PHY */ #define EMAC_MACMIIDR_MD ((rt_uint32_t)0x0000FFFF) /* MII data: read/write data from/to PHY */
/* Bit definition for Ethernet MAC Flow Control Register */ /* Bit definition for Ethernet MAC Flow Control Register */
#define EMAC_MACFCR_PT ((rt_uint32_t)0xFFFF0000) /* Pause time */ #define EMAC_MACFCR_PT ((rt_uint32_t)0xFFFF0000) /* Pause time */
#define EMAC_MACFCR_ZQPD ((rt_uint32_t)0x00000080) /* Zero-quanta pause disable */ #define EMAC_MACFCR_ZQPD ((rt_uint32_t)0x00000080) /* Zero-quanta pause disable */
#define EMAC_MACFCR_PLT ((rt_uint32_t)0x00000030) /* Pause low threshold: 4 cases */ #define EMAC_MACFCR_PLT ((rt_uint32_t)0x00000030) /* Pause low threshold: 4 cases */
#define EMAC_MACFCR_PLT_Minus4 ((rt_uint32_t)0x00000000) /* Pause time minus 4 slot times */ #define EMAC_MACFCR_PLT_Minus4 ((rt_uint32_t)0x00000000) /* Pause time minus 4 slot times */
#define EMAC_MACFCR_PLT_Minus28 ((rt_uint32_t)0x00000010) /* Pause time minus 28 slot times */ #define EMAC_MACFCR_PLT_Minus28 ((rt_uint32_t)0x00000010) /* Pause time minus 28 slot times */
#define EMAC_MACFCR_PLT_Minus144 ((rt_uint32_t)0x00000020) /* Pause time minus 144 slot times */ #define EMAC_MACFCR_PLT_Minus144 ((rt_uint32_t)0x00000020) /* Pause time minus 144 slot times */
@ -441,7 +441,7 @@
#define EMAC_DMACHRBAR_HRBAP ((rt_uint32_t)0xFFFFFFFF) /* Host receive buffer address pointer */ #define EMAC_DMACHRBAR_HRBAP ((rt_uint32_t)0xFFFFFFFF) /* Host receive buffer address pointer */
//typedef enum { //typedef enum {
// RESET = 0, SET = !RESET // RESET = 0, SET = !RESET
//} FlagStatus, ITStatus; //} FlagStatus, ITStatus;
//typedef enum {DISABLE = 0, ENABLE = !DISABLE} FunctionalState; //typedef enum {DISABLE = 0, ENABLE = !DISABLE} FunctionalState;
@ -450,165 +450,165 @@
*/ */
typedef struct typedef struct
{ {
/** /**
* MAC * MAC
*/ */
rt_uint32_t EMAC_AutoNegotiation; /* Selects or not the AutoNegotiation mode for the external PHY rt_uint32_t EMAC_AutoNegotiation; /* Selects or not the AutoNegotiation mode for the external PHY
The AutoNegotiation allows an automatic setting of the Speed (10/100Mbps) The AutoNegotiation allows an automatic setting of the Speed (10/100Mbps)
and the mode (half/full-duplex). and the mode (half/full-duplex).
This parameter can be a value of @ref EMAC_AutoNegotiation */ This parameter can be a value of @ref EMAC_AutoNegotiation */
rt_uint32_t EMAC_Watchdog; /* Selects or not the Watchdog timer rt_uint32_t EMAC_Watchdog; /* Selects or not the Watchdog timer
When enabled, the MAC allows no more then 2048 bytes to be received. When enabled, the MAC allows no more then 2048 bytes to be received.
When disabled, the MAC can receive up to 16384 bytes. When disabled, the MAC can receive up to 16384 bytes.
This parameter can be a value of @ref EMAC_watchdog */ This parameter can be a value of @ref EMAC_watchdog */
rt_uint32_t EMAC_Jabber; /* Selects or not Jabber timer rt_uint32_t EMAC_Jabber; /* Selects or not Jabber timer
When enabled, the MAC allows no more then 2048 bytes to be sent. When enabled, the MAC allows no more then 2048 bytes to be sent.
When disabled, the MAC can send up to 16384 bytes. When disabled, the MAC can send up to 16384 bytes.
This parameter can be a value of @ref EMAC_Jabber */ This parameter can be a value of @ref EMAC_Jabber */
rt_uint32_t EMAC_InterFrameGap; /* Selects the minimum IFG between frames during transmission rt_uint32_t EMAC_InterFrameGap; /* Selects the minimum IFG between frames during transmission
This parameter can be a value of @ref EMAC_Inter_Frame_Gap */ This parameter can be a value of @ref EMAC_Inter_Frame_Gap */
rt_uint32_t EMAC_CarrierSense; /* Selects or not the Carrier Sense rt_uint32_t EMAC_CarrierSense; /* Selects or not the Carrier Sense
This parameter can be a value of @ref EMAC_Carrier_Sense */ This parameter can be a value of @ref EMAC_Carrier_Sense */
rt_uint32_t EMAC_Speed; /* Sets the Ethernet speed: 10/100 Mbps rt_uint32_t EMAC_Speed; /* Sets the Ethernet speed: 10/100 Mbps
This parameter can be a value of @ref EMAC_Speed */ This parameter can be a value of @ref EMAC_Speed */
rt_uint32_t EMAC_ReceiveOwn; /* Selects or not the ReceiveOwn rt_uint32_t EMAC_ReceiveOwn; /* Selects or not the ReceiveOwn
ReceiveOwn allows the reception of frames when the TX_EN signal is asserted ReceiveOwn allows the reception of frames when the TX_EN signal is asserted
in Half-Duplex mode in Half-Duplex mode
This parameter can be a value of @ref EMAC_Receive_Own */ This parameter can be a value of @ref EMAC_Receive_Own */
rt_uint32_t EMAC_LoopbackMode; /* Selects or not the internal MAC MII Loopback mode rt_uint32_t EMAC_LoopbackMode; /* Selects or not the internal MAC MII Loopback mode
This parameter can be a value of @ref EMAC_Loop_Back_Mode */ This parameter can be a value of @ref EMAC_Loop_Back_Mode */
rt_uint32_t EMAC_Mode; /* Selects the MAC duplex mode: Half-Duplex or Full-Duplex mode rt_uint32_t EMAC_Mode; /* Selects the MAC duplex mode: Half-Duplex or Full-Duplex mode
This parameter can be a value of @ref EMAC_Duplex_Mode */ This parameter can be a value of @ref EMAC_Duplex_Mode */
rt_uint32_t EMAC_ChecksumOffload; /* Selects or not the IPv4 checksum checking for received frame payloads' TCP/UDP/ICMP headers. rt_uint32_t EMAC_ChecksumOffload; /* Selects or not the IPv4 checksum checking for received frame payloads' TCP/UDP/ICMP headers.
This parameter can be a value of @ref EMAC_Checksum_Offload */ This parameter can be a value of @ref EMAC_Checksum_Offload */
rt_uint32_t EMAC_RetryTransmission; /* Selects or not the MAC attempt retries transmission, based on the settings of BL, rt_uint32_t EMAC_RetryTransmission; /* Selects or not the MAC attempt retries transmission, based on the settings of BL,
when a colision occurs (Half-Duplex mode) when a colision occurs (Half-Duplex mode)
This parameter can be a value of @ref EMAC_Retry_Transmission */ This parameter can be a value of @ref EMAC_Retry_Transmission */
rt_uint32_t EMAC_AutomaticPadCRCStrip; /* Selects or not the Automatic MAC Pad/CRC Stripping rt_uint32_t EMAC_AutomaticPadCRCStrip; /* Selects or not the Automatic MAC Pad/CRC Stripping
This parameter can be a value of @ref EMAC_Automatic_Pad_CRC_Strip */ This parameter can be a value of @ref EMAC_Automatic_Pad_CRC_Strip */
rt_uint32_t EMAC_BackOffLimit; /* Selects the BackOff limit value rt_uint32_t EMAC_BackOffLimit; /* Selects the BackOff limit value
This parameter can be a value of @ref EMAC_Back_Off_Limit */ This parameter can be a value of @ref EMAC_Back_Off_Limit */
rt_uint32_t EMAC_DeferralCheck; /* Selects or not the deferral check function (Half-Duplex mode) rt_uint32_t EMAC_DeferralCheck; /* Selects or not the deferral check function (Half-Duplex mode)
This parameter can be a value of @ref EMAC_Deferral_Check */ This parameter can be a value of @ref EMAC_Deferral_Check */
rt_uint32_t EMAC_ReceiveAll; /* Selects or not all frames reception by the MAC (No fitering) rt_uint32_t EMAC_ReceiveAll; /* Selects or not all frames reception by the MAC (No fitering)
This parameter can be a value of @ref EMAC_Receive_All */ This parameter can be a value of @ref EMAC_Receive_All */
rt_uint32_t EMAC_SourceAddrFilter; /* Selects the Source Address Filter mode rt_uint32_t EMAC_SourceAddrFilter; /* Selects the Source Address Filter mode
This parameter can be a value of @ref EMAC_Source_Addr_Filter */ This parameter can be a value of @ref EMAC_Source_Addr_Filter */
rt_uint32_t EMAC_PassControlFrames; /* Sets the forwarding mode of the control frames (including unicast and multicast PAUSE frames) rt_uint32_t EMAC_PassControlFrames; /* Sets the forwarding mode of the control frames (including unicast and multicast PAUSE frames)
This parameter can be a value of @ref EMAC_Pass_Control_Frames */ This parameter can be a value of @ref EMAC_Pass_Control_Frames */
rt_uint32_t EMAC_BroadcastFramesReception; /* Selects or not the reception of Broadcast Frames rt_uint32_t EMAC_BroadcastFramesReception; /* Selects or not the reception of Broadcast Frames
This parameter can be a value of @ref EMAC_Broadcast_Frames_Reception */ This parameter can be a value of @ref EMAC_Broadcast_Frames_Reception */
rt_uint32_t EMAC_DestinationAddrFilter; /* Sets the destination filter mode for both unicast and multicast frames rt_uint32_t EMAC_DestinationAddrFilter; /* Sets the destination filter mode for both unicast and multicast frames
This parameter can be a value of @ref EMAC_Destination_Addr_Filter */ This parameter can be a value of @ref EMAC_Destination_Addr_Filter */
rt_uint32_t EMAC_PromiscuousMode; /* Selects or not the Promiscuous Mode rt_uint32_t EMAC_PromiscuousMode; /* Selects or not the Promiscuous Mode
This parameter can be a value of @ref EMAC_Promiscuous_Mode */ This parameter can be a value of @ref EMAC_Promiscuous_Mode */
rt_uint32_t EMAC_MulticastFramesFilter; /* Selects the Multicast Frames filter mode: None/HashTableFilter/PerfectFilter/PerfectHashTableFilter rt_uint32_t EMAC_MulticastFramesFilter; /* Selects the Multicast Frames filter mode: None/HashTableFilter/PerfectFilter/PerfectHashTableFilter
This parameter can be a value of @ref EMAC_Multicast_Frames_Filter */ This parameter can be a value of @ref EMAC_Multicast_Frames_Filter */
rt_uint32_t EMAC_UnicastFramesFilter; /* Selects the Unicast Frames filter mode: HashTableFilter/PerfectFilter/PerfectHashTableFilter rt_uint32_t EMAC_UnicastFramesFilter; /* Selects the Unicast Frames filter mode: HashTableFilter/PerfectFilter/PerfectHashTableFilter
This parameter can be a value of @ref EMAC_Unicast_Frames_Filter */ This parameter can be a value of @ref EMAC_Unicast_Frames_Filter */
rt_uint32_t EMAC_HashTableHigh; /* This field holds the higher 32 bits of Hash table. */ rt_uint32_t EMAC_HashTableHigh; /* This field holds the higher 32 bits of Hash table. */
rt_uint32_t EMAC_HashTableLow; /* This field holds the lower 32 bits of Hash table. */ rt_uint32_t EMAC_HashTableLow; /* This field holds the lower 32 bits of Hash table. */
rt_uint32_t EMAC_PauseTime; /* This field holds the value to be used in the Pause Time field in the rt_uint32_t EMAC_PauseTime; /* This field holds the value to be used in the Pause Time field in the
transmit control frame */ transmit control frame */
rt_uint32_t EMAC_ZeroQuantaPause; /* Selects or not the automatic generation of Zero-Quanta Pause Control frames rt_uint32_t EMAC_ZeroQuantaPause; /* Selects or not the automatic generation of Zero-Quanta Pause Control frames
This parameter can be a value of @ref EMAC_Zero_Quanta_Pause */ This parameter can be a value of @ref EMAC_Zero_Quanta_Pause */
rt_uint32_t EMAC_PauseLowThreshold; /* This field configures the threshold of the PAUSE to be checked for rt_uint32_t EMAC_PauseLowThreshold; /* This field configures the threshold of the PAUSE to be checked for
automatic retransmission of PAUSE Frame automatic retransmission of PAUSE Frame
This parameter can be a value of @ref EMAC_Pause_Low_Threshold */ This parameter can be a value of @ref EMAC_Pause_Low_Threshold */
rt_uint32_t EMAC_UnicastPauseFrameDetect; /* Selects or not the MAC detection of the Pause frames (with MAC Address0 rt_uint32_t EMAC_UnicastPauseFrameDetect; /* Selects or not the MAC detection of the Pause frames (with MAC Address0
unicast address and unique multicast address) unicast address and unique multicast address)
This parameter can be a value of @ref EMAC_Unicast_Pause_Frame_Detect */ This parameter can be a value of @ref EMAC_Unicast_Pause_Frame_Detect */
rt_uint32_t EMAC_ReceiveFlowControl; /* Enables or disables the MAC to decode the received Pause frame and rt_uint32_t EMAC_ReceiveFlowControl; /* Enables or disables the MAC to decode the received Pause frame and
disable its transmitter for a specified time (Pause Time) disable its transmitter for a specified time (Pause Time)
This parameter can be a value of @ref EMAC_Receive_Flow_Control */ This parameter can be a value of @ref EMAC_Receive_Flow_Control */
rt_uint32_t EMAC_TransmitFlowControl; /* Enables or disables the MAC to transmit Pause frames (Full-Duplex mode) rt_uint32_t EMAC_TransmitFlowControl; /* Enables or disables the MAC to transmit Pause frames (Full-Duplex mode)
or the MAC back-pressure operation (Half-Duplex mode) or the MAC back-pressure operation (Half-Duplex mode)
This parameter can be a value of @ref EMAC_Transmit_Flow_Control */ This parameter can be a value of @ref EMAC_Transmit_Flow_Control */
rt_uint32_t EMAC_VLANTagComparison; /* Selects the 12-bit VLAN identifier or the complete 16-bit VLAN tag for rt_uint32_t EMAC_VLANTagComparison; /* Selects the 12-bit VLAN identifier or the complete 16-bit VLAN tag for
comparison and filtering comparison and filtering
This parameter can be a value of @ref EMAC_VLAN_Tag_Comparison */ This parameter can be a value of @ref EMAC_VLAN_Tag_Comparison */
rt_uint32_t EMAC_VLANTagIdentifier; /* Holds the VLAN tag identifier for receive frames */ rt_uint32_t EMAC_VLANTagIdentifier; /* Holds the VLAN tag identifier for receive frames */
/** /**
* DMA * DMA
*/ */
rt_uint32_t EMAC_DropTCPIPChecksumErrorFrame; /* Selects or not the Dropping of TCP/IP Checksum Error Frames rt_uint32_t EMAC_DropTCPIPChecksumErrorFrame; /* Selects or not the Dropping of TCP/IP Checksum Error Frames
This parameter can be a value of @ref EMAC_Drop_TCP_IP_Checksum_Error_Frame */ This parameter can be a value of @ref EMAC_Drop_TCP_IP_Checksum_Error_Frame */
rt_uint32_t EMAC_ReceiveStoreForward; /* Enables or disables the Receive store and forward mode rt_uint32_t EMAC_ReceiveStoreForward; /* Enables or disables the Receive store and forward mode
This parameter can be a value of @ref EMAC_Receive_Store_Forward */ This parameter can be a value of @ref EMAC_Receive_Store_Forward */
rt_uint32_t EMAC_FlushReceivedFrame; /* Enables or disables the flushing of received frames rt_uint32_t EMAC_FlushReceivedFrame; /* Enables or disables the flushing of received frames
This parameter can be a value of @ref EMAC_Flush_Received_Frame */ This parameter can be a value of @ref EMAC_Flush_Received_Frame */
rt_uint32_t EMAC_TransmitStoreForward; /* Enables or disables Transmit store and forward mode rt_uint32_t EMAC_TransmitStoreForward; /* Enables or disables Transmit store and forward mode
This parameter can be a value of @ref EMAC_Transmit_Store_Forward */ This parameter can be a value of @ref EMAC_Transmit_Store_Forward */
rt_uint32_t EMAC_TransmitThresholdControl; /* Selects or not the Transmit Threshold Control rt_uint32_t EMAC_TransmitThresholdControl; /* Selects or not the Transmit Threshold Control
This parameter can be a value of @ref EMAC_Transmit_Threshold_Control */ This parameter can be a value of @ref EMAC_Transmit_Threshold_Control */
rt_uint32_t EMAC_ForwardErrorFrames; /* Selects or not the forward to the DMA of erroneous frames rt_uint32_t EMAC_ForwardErrorFrames; /* Selects or not the forward to the DMA of erroneous frames
This parameter can be a value of @ref EMAC_Forward_Error_Frames */ This parameter can be a value of @ref EMAC_Forward_Error_Frames */
rt_uint32_t EMAC_ForwardUndersizedGoodFrames; /* Enables or disables the Rx FIFO to forward Undersized frames (frames with no Error rt_uint32_t EMAC_ForwardUndersizedGoodFrames; /* Enables or disables the Rx FIFO to forward Undersized frames (frames with no Error
and length less than 64 bytes) including pad-bytes and CRC) and length less than 64 bytes) including pad-bytes and CRC)
This parameter can be a value of @ref EMAC_Forward_Undersized_Good_Frames */ This parameter can be a value of @ref EMAC_Forward_Undersized_Good_Frames */
rt_uint32_t EMAC_ReceiveThresholdControl; /* Selects the threshold level of the Receive FIFO rt_uint32_t EMAC_ReceiveThresholdControl; /* Selects the threshold level of the Receive FIFO
This parameter can be a value of @ref EMAC_Receive_Threshold_Control */ This parameter can be a value of @ref EMAC_Receive_Threshold_Control */
rt_uint32_t EMAC_SecondFrameOperate; /* Selects or not the Operate on second frame mode, which allows the DMA to process a second rt_uint32_t EMAC_SecondFrameOperate; /* Selects or not the Operate on second frame mode, which allows the DMA to process a second
frame of Transmit data even before obtaining the status for the first frame. frame of Transmit data even before obtaining the status for the first frame.
This parameter can be a value of @ref EMAC_Second_Frame_Operate */ This parameter can be a value of @ref EMAC_Second_Frame_Operate */
rt_uint32_t EMAC_AddressAlignedBeats; /* Enables or disables the Address Aligned Beats rt_uint32_t EMAC_AddressAlignedBeats; /* Enables or disables the Address Aligned Beats
This parameter can be a value of @ref EMAC_Address_Aligned_Beats */ This parameter can be a value of @ref EMAC_Address_Aligned_Beats */
rt_uint32_t EMAC_FixedBurst; /* Enables or disables the AHB Master interface fixed burst transfers rt_uint32_t EMAC_FixedBurst; /* Enables or disables the AHB Master interface fixed burst transfers
This parameter can be a value of @ref EMAC_Fixed_Burst */ This parameter can be a value of @ref EMAC_Fixed_Burst */
rt_uint32_t EMAC_RxDMABurstLength; /* Indicates the maximum number of beats to be transferred in one Rx DMA transaction rt_uint32_t EMAC_RxDMABurstLength; /* Indicates the maximum number of beats to be transferred in one Rx DMA transaction
This parameter can be a value of @ref EMAC_Rx_DMA_Burst_Length */ This parameter can be a value of @ref EMAC_Rx_DMA_Burst_Length */
rt_uint32_t EMAC_TxDMABurstLength; /* Indicates sthe maximum number of beats to be transferred in one Tx DMA transaction rt_uint32_t EMAC_TxDMABurstLength; /* Indicates sthe maximum number of beats to be transferred in one Tx DMA transaction
This parameter can be a value of @ref EMAC_Tx_DMA_Burst_Length */ This parameter can be a value of @ref EMAC_Tx_DMA_Burst_Length */
rt_uint32_t EMAC_DescriptorSkipLength; /* Specifies the number of word to skip between two unchained int (Ring mode) */ rt_uint32_t EMAC_DescriptorSkipLength; /* Specifies the number of word to skip between two unchained int (Ring mode) */
rt_uint32_t EMAC_DMAArbitration; /* Selects the DMA Tx/Rx arbitration rt_uint32_t EMAC_DMAArbitration; /* Selects the DMA Tx/Rx arbitration
This parameter can be a value of @ref EMAC_DMA_Arbitration */ This parameter can be a value of @ref EMAC_DMA_Arbitration */
} EMAC_InitTypeDef; } EMAC_InitTypeDef;
/**--------------------------------------------------------------------------**/ /**--------------------------------------------------------------------------**/
@ -622,10 +622,10 @@ typedef struct
*/ */
typedef struct typedef struct
{ {
rt_uint32_t Status; /* Status */ rt_uint32_t Status; /* Status */
rt_uint32_t ControlBufferSize; /* Control and Buffer1, Buffer2 lengths */ rt_uint32_t ControlBufferSize; /* Control and Buffer1, Buffer2 lengths */
rt_uint32_t Buffer1Addr; /* Buffer1 address pointer */ rt_uint32_t Buffer1Addr; /* Buffer1 address pointer */
rt_uint32_t Buffer2NextDescAddr; /* Buffer2 or next descriptor address pointer */ rt_uint32_t Buffer2NextDescAddr; /* Buffer2 or next descriptor address pointer */
} EMAC_DMADESCTypeDef; } EMAC_DMADESCTypeDef;
/**--------------------------------------------------------------------------**/ /**--------------------------------------------------------------------------**/
@ -634,14 +634,14 @@ typedef struct
*/ */
/**--------------------------------------------------------------------------**/ /**--------------------------------------------------------------------------**/
#define EMAC_MAX_PACKET_SIZE 1520 /* EMAC_HEADER + EMAC_EXTRA + MAX_EMAC_PAYLOAD + EMAC_CRC */ #define EMAC_MAX_PACKET_SIZE 1520 /* EMAC_HEADER + EMAC_EXTRA + MAX_EMAC_PAYLOAD + EMAC_CRC */
#define EMAC_HEADER 14 /* 6 byte Dest addr, 6 byte Src addr, 2 byte length/type */ #define EMAC_HEADER 14 /* 6 byte Dest addr, 6 byte Src addr, 2 byte length/type */
#define EMAC_CRC 4 /* Ethernet CRC */ #define EMAC_CRC 4 /* Ethernet CRC */
#define EMAC_EXTRA 2 /* Extra bytes in some cases */ #define EMAC_EXTRA 2 /* Extra bytes in some cases */
#define VLAN_TAG 4 /* optional 802.1q VLAN Tag */ #define VLAN_TAG 4 /* optional 802.1q VLAN Tag */
#define MIN_EMAC_PAYLOAD 46 /* Minimum Ethernet payload size */ #define MIN_EMAC_PAYLOAD 46 /* Minimum Ethernet payload size */
#define MAX_EMAC_PAYLOAD 1500 /* Maximum Ethernet payload size */ #define MAX_EMAC_PAYLOAD 1500 /* Maximum Ethernet payload size */
#define JUMBO_FRAME_PAYLOAD 9000 /* Jumbo frame payload size */ #define JUMBO_FRAME_PAYLOAD 9000 /* Jumbo frame payload size */
/**--------------------------------------------------------------------------**/ /**--------------------------------------------------------------------------**/
/** /**

2
bsp/gd32e230k-start/applications/main.c
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@ -1,5 +1,5 @@
/* /*
* Copyright (c) 2006-2019, RT-Thread Development Team * Copyright (c) 2006-2021, RT-Thread Development Team
* *
* SPDX-License-Identifier: Apache-2.0 * SPDX-License-Identifier: Apache-2.0
* *

2
bsp/gd32e230k-start/drivers/board.c
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@ -1,5 +1,5 @@
/* /*
* Copyright (c) 2006-2019, RT-Thread Development Team * Copyright (c) 2006-2021, RT-Thread Development Team
* *
* SPDX-License-Identifier: Apache-2.0 * SPDX-License-Identifier: Apache-2.0
* *

4
bsp/gd32e230k-start/drivers/board.h
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@ -1,5 +1,5 @@
/* /*
* Copyright (c) 2006-2019, RT-Thread Development Team * Copyright (c) 2006-2021, RT-Thread Development Team
* *
* SPDX-License-Identifier: Apache-2.0 * SPDX-License-Identifier: Apache-2.0
* *
@ -15,7 +15,7 @@
#include <gd32e230.h> #include <gd32e230.h>
// <o> Internal SRAM memory size[Kbytes] <8-64> // <o> Internal SRAM memory size[Kbytes] <8-64>
// <i>Default: 64 // <i>Default: 64
#ifdef __ICCARM__ #ifdef __ICCARM__
// Use *.icf ram symbal, to avoid hardcode. // Use *.icf ram symbal, to avoid hardcode.
extern char __ICFEDIT_region_RAM_end__; extern char __ICFEDIT_region_RAM_end__;

32
bsp/gd32e230k-start/drivers/drv_gpio.c
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@ -1,5 +1,5 @@
/* /*
* Copyright (c) 2006-2019, RT-Thread Development Team * Copyright (c) 2006-2021, RT-Thread Development Team
* *
* SPDX-License-Identifier: Apache-2.0 * SPDX-License-Identifier: Apache-2.0
* *
@ -29,8 +29,8 @@ struct pin_index
rcu_periph_enum clk; rcu_periph_enum clk;
rt_uint32_t gpio_periph; rt_uint32_t gpio_periph;
rt_uint32_t pin; rt_uint32_t pin;
rt_uint32_t port_src; rt_uint32_t port_src;
rt_uint32_t pin_src; rt_uint32_t pin_src;
}; };
static const struct pin_index pins[] = static const struct pin_index pins[] =
@ -38,8 +38,8 @@ static const struct pin_index pins[] =
__GD32_PIN_DEFAULT, __GD32_PIN_DEFAULT,
__GD32_PIN(2, F, 0), __GD32_PIN(2, F, 0),
__GD32_PIN(3, F, 1), __GD32_PIN(3, F, 1),
__GD32_PIN_DEFAULT, __GD32_PIN_DEFAULT,
__GD32_PIN_DEFAULT, __GD32_PIN_DEFAULT,
__GD32_PIN(6, A, 0), __GD32_PIN(6, A, 0),
__GD32_PIN(7, A, 1), __GD32_PIN(7, A, 1),
__GD32_PIN(8, A, 2), __GD32_PIN(8, A, 2),
@ -51,7 +51,7 @@ static const struct pin_index pins[] =
__GD32_PIN(14, B, 0), __GD32_PIN(14, B, 0),
__GD32_PIN(15, B, 1), __GD32_PIN(15, B, 1),
__GD32_PIN(16, B, 2), __GD32_PIN(16, B, 2),
__GD32_PIN_DEFAULT, __GD32_PIN_DEFAULT,
__GD32_PIN(18, A, 8), __GD32_PIN(18, A, 8),
__GD32_PIN(19, A, 9), __GD32_PIN(19, A, 9),
__GD32_PIN(20, A, 10), __GD32_PIN(20, A, 10),
@ -136,8 +136,8 @@ void gd32_pin_mode(rt_device_t dev, rt_base_t pin, rt_base_t mode)
{ {
const struct pin_index *index; const struct pin_index *index;
rt_uint32_t pin_mode; rt_uint32_t pin_mode;
rt_uint32_t otype; rt_uint32_t otype;
rt_uint32_t pull_up_down; rt_uint32_t pull_up_down;
index = get_pin(pin); index = get_pin(pin);
if (index == RT_NULL) if (index == RT_NULL)
{ {
@ -147,8 +147,8 @@ void gd32_pin_mode(rt_device_t dev, rt_base_t pin, rt_base_t mode)
/* GPIO Periph clock enable */ /* GPIO Periph clock enable */
rcu_periph_clock_enable(index->clk); rcu_periph_clock_enable(index->clk);
pin_mode = GPIO_MODE_OUTPUT; pin_mode = GPIO_MODE_OUTPUT;
otype = GPIO_OTYPE_PP; otype = GPIO_OTYPE_PP;
pull_up_down = GPIO_PUPD_NONE; pull_up_down = GPIO_PUPD_NONE;
switch(mode) switch(mode)
{ {
@ -157,7 +157,7 @@ void gd32_pin_mode(rt_device_t dev, rt_base_t pin, rt_base_t mode)
break; break;
case PIN_MODE_OUTPUT_OD: case PIN_MODE_OUTPUT_OD:
/* output setting: od. */ /* output setting: od. */
otype = GPIO_OTYPE_OD; otype = GPIO_OTYPE_OD;
break; break;
case PIN_MODE_INPUT: case PIN_MODE_INPUT:
/* input setting: not pull. */ /* input setting: not pull. */
@ -166,18 +166,18 @@ void gd32_pin_mode(rt_device_t dev, rt_base_t pin, rt_base_t mode)
case PIN_MODE_INPUT_PULLUP: case PIN_MODE_INPUT_PULLUP:
/* input setting: pull up. */ /* input setting: pull up. */
pin_mode = GPIO_MODE_INPUT; pin_mode = GPIO_MODE_INPUT;
pull_up_down = GPIO_PUPD_PULLUP; pull_up_down = GPIO_PUPD_PULLUP;
break; break;
case PIN_MODE_INPUT_PULLDOWN: case PIN_MODE_INPUT_PULLDOWN:
/* input setting: pull down. */ /* input setting: pull down. */
pin_mode = GPIO_MODE_INPUT; pin_mode = GPIO_MODE_INPUT;
pull_up_down = GPIO_PUPD_PULLDOWN; pull_up_down = GPIO_PUPD_PULLDOWN;
break; break;
default: default:
break; break;
} }
gpio_mode_set(index->gpio_periph, pin_mode, pull_up_down, index->pin); gpio_mode_set(index->gpio_periph, pin_mode, pull_up_down, index->pin);
gpio_output_options_set(index->gpio_periph, otype, GPIO_OSPEED_50MHZ, index->pin); gpio_output_options_set(index->gpio_periph, otype, GPIO_OSPEED_50MHZ, index->pin);
} }
@ -356,7 +356,7 @@ rt_err_t gd32_pin_irq_enable(struct rt_device *device, rt_base_t pin, rt_uint32_
nvic_irq_enable(irqmap->irqno, 5U); nvic_irq_enable(irqmap->irqno, 5U);
/* connect EXTI line to GPIO pin */ /* connect EXTI line to GPIO pin */
syscfg_exti_line_config(index->port_src, index->pin_src); syscfg_exti_line_config(index->port_src, index->pin_src);
/* configure EXTI line */ /* configure EXTI line */
exti_init((exti_line_enum)(index->pin), EXTI_INTERRUPT, trigger_mode); exti_init((exti_line_enum)(index->pin), EXTI_INTERRUPT, trigger_mode);

2
bsp/gd32e230k-start/drivers/drv_gpio.h
View File

@ -1,5 +1,5 @@
/* /*
* Copyright (c) 2006-2019, RT-Thread Development Team * Copyright (c) 2006-2021, RT-Thread Development Team
* *
* SPDX-License-Identifier: Apache-2.0 * SPDX-License-Identifier: Apache-2.0
* *

2
bsp/gd32e230k-start/drivers/drv_i2c.c
View File

@ -1,5 +1,5 @@
/* /*
* Copyright (c) 2006-2019, RT-Thread Development Team * Copyright (c) 2006-2021, RT-Thread Development Team
* *
* SPDX-License-Identifier: Apache-2.0 * SPDX-License-Identifier: Apache-2.0
* *

2
bsp/gd32e230k-start/drivers/drv_i2c.h
View File

@ -1,5 +1,5 @@
/* /*
* Copyright (c) 2006-2019, RT-Thread Development Team * Copyright (c) 2006-2021, RT-Thread Development Team
* *
* SPDX-License-Identifier: Apache-2.0 * SPDX-License-Identifier: Apache-2.0
* *

2
bsp/gd32e230k-start/drivers/drv_spi.c
View File

@ -1,5 +1,5 @@
/* /*
* Copyright (c) 2006-2019, RT-Thread Development Team * Copyright (c) 2006-2021, RT-Thread Development Team
* *
* SPDX-License-Identifier: Apache-2.0 * SPDX-License-Identifier: Apache-2.0
* *

2
bsp/gd32e230k-start/drivers/drv_spi.h
View File

@ -1,5 +1,5 @@
/* /*
* Copyright (c) 2006-2019, RT-Thread Development Team * Copyright (c) 2006-2021, RT-Thread Development Team
* *
* SPDX-License-Identifier: Apache-2.0 * SPDX-License-Identifier: Apache-2.0
* *

2
bsp/gd32e230k-start/drivers/drv_usart.c
View File

@ -1,5 +1,5 @@
/* /*
* Copyright (c) 2006-2019, RT-Thread Development Team * Copyright (c) 2006-2021, RT-Thread Development Team
* *
* SPDX-License-Identifier: Apache-2.0 * SPDX-License-Identifier: Apache-2.0
* *

2
bsp/gd32e230k-start/drivers/drv_usart.h
View File

@ -1,5 +1,5 @@
/* /*
* Copyright (c) 2006-2019, RT-Thread Development Team * Copyright (c) 2006-2021, RT-Thread Development Team
* *
* SPDX-License-Identifier: Apache-2.0 * SPDX-License-Identifier: Apache-2.0
* *

2
bsp/gd32vf103v-eval/applications/main.c
View File

@ -1,5 +1,5 @@
/* /*
* Copyright (c) 2006-2018, RT-Thread Development Team * Copyright (c) 2006-2021, RT-Thread Development Team
* *
* SPDX-License-Identifier: Apache-2.0 * SPDX-License-Identifier: Apache-2.0
* *

2
bsp/gd32vf103v-eval/board/board.c
View File

@ -1,5 +1,5 @@
/* /*
* Copyright (c) 2006-2018, RT-Thread Development Team * Copyright (c) 2006-2021, RT-Thread Development Team
* *
* SPDX-License-Identifier: Apache-2.0 * SPDX-License-Identifier: Apache-2.0
* *

2
bsp/gd32vf103v-eval/board/board.h
View File

@ -1,5 +1,5 @@
/* /*
* Copyright (c) 2006-2018, RT-Thread Development Team * Copyright (c) 2006-2021, RT-Thread Development Team
* *
* SPDX-License-Identifier: Apache-2.0 * SPDX-License-Identifier: Apache-2.0
* *

2
bsp/gd32vf103v-eval/drivers/drv_gpio.c
View File

@ -1,5 +1,5 @@
/* /*
* Copyright (c) 2006-2018, RT-Thread Development Team * Copyright (c) 2006-2021, RT-Thread Development Team
* *
* SPDX-License-Identifier: Apache-2.0 * SPDX-License-Identifier: Apache-2.0
* *

2
bsp/gd32vf103v-eval/drivers/drv_gpio.h
View File

@ -1,5 +1,5 @@
/* /*
* Copyright (c) 2006-2018, RT-Thread Development Team * Copyright (c) 2006-2021, RT-Thread Development Team
* *
* SPDX-License-Identifier: Apache-2.0 * SPDX-License-Identifier: Apache-2.0
* *

4
bsp/gd32vf103v-eval/drivers/drv_usart.c
View File

@ -1,5 +1,5 @@
/* /*
* Copyright (c) 2006-2018, RT-Thread Development Team * Copyright (c) 2006-2021, RT-Thread Development Team
* *
* SPDX-License-Identifier: Apache-2.0 * SPDX-License-Identifier: Apache-2.0
* *
@ -15,7 +15,7 @@
#if !defined(BSP_USING_UART0) && !defined(BSP_USING_UART1) && !defined(BSP_USING_UART2) \ #if !defined(BSP_USING_UART0) && !defined(BSP_USING_UART1) && !defined(BSP_USING_UART2) \
&& !defined(BSP_USING_UART3) && !defined(BSP_USING_UART4) && !defined(BSP_USING_UART5) && !defined(BSP_USING_UART3) && !defined(BSP_USING_UART4) && !defined(BSP_USING_UART5)
#error "Please define at least one BSP_USING_UARTx" #error "Please define at least one BSP_USING_UARTx"
/* this driver can be disabled at menuconfig ¡ú RT-Thread Components ¡ú Device Drivers */ /* this driver can be disabled at menuconfig → RT-Thread Components → Device Drivers */
#endif #endif
struct gd32_usart { struct gd32_usart {