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[bsp] phytium e2000 update (#7900) 

Co-authored-by: zhugengyu <zhugengyu@phytium.com.cn>
This commit is contained in:
zhangyan 2023-08-02 13:27:09 +08:00 committed by GitHub
parent d3417aa0d7
commit 31fec3bb70
No known key found for this signature in database
GPG Key ID: 4AEE18F83AFDEB23
210 changed files with 20325 additions and 7125 deletions
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1
.github/workflows/action.yml vendored
View File

@ -285,6 +285,7 @@ jobs:
- "raspberry-pi/raspi3-64"
- "raspberry-pi/raspi4-64"
- "rockchip/rk3568"
- "phytium/aarch64"
- RTT_BSP: "riscv-none"
RTT_TOOL_CHAIN: "sourcery-riscv-none-embed"
SUB_RTT_BSP:

4
.github/workflows/manual_trigger_scons_except_STM32_all.yml vendored
View File

@ -210,8 +210,8 @@ jobs:
- {RTT_BSP_NAME: "nuclei_gd32vf103_rvstar", RTT_TOOL_CHAIN: "sourcery-arm", RTT_BSP: "nuclei/gd32vf103_rvstar"}
#- {RTT_BSP_NAME: "nuclei_nuclei_fpga_eval", RTT_TOOL_CHAIN: "sourcery-arm", RTT_BSP: "nuclei/nuclei_fpga_eval"} #riscv-nuclei-elf-gcc toolchain不支持
#- {RTT_BSP_NAME: "nv32f100x", RTT_TOOL_CHAIN: "sourcery-arm", RTT_BSP: "nv32f100x"} #编译错误
#- {RTT_BSP_NAME: "phytium_aarch32", RTT_TOOL_CHAIN: "sourcery-arm", RTT_BSP: "phytium/aarch32"} #编译错误
# - {RTT_BSP_NAME: "phytium_aarch64", RTT_TOOL_CHAIN: "sourcery-arm", RTT_BSP: "phytium/aarch64"} #编译错误
# - {RTT_BSP_NAME: "phytium_aarch32", RTT_TOOL_CHAIN: "sourcery-arm", RTT_BSP: "phytium/aarch32"}
- {RTT_BSP_NAME: "phytium_aarch64", RTT_TOOL_CHAIN: "sourcery-aarch64", RTT_BSP: "phytium/aarch64"}
#- {RTT_BSP_NAME: "pic32ethernet", RTT_TOOL_CHAIN: "sourcery-arm", RTT_BSP: "pic32ethernet"} #编译错误
- {RTT_BSP_NAME: "qemu-vexpress-a9", RTT_TOOL_CHAIN: "sourcery-arm", RTT_BSP: "qemu-vexpress-a9"}
- {RTT_BSP_NAME: "qemu-virt64-aarch64", RTT_TOOL_CHAIN: "sourcery-aarch64", RTT_BSP: "qemu-virt64-aarch64"}

5
bsp/phytium/.gitignore vendored
View File

@ -4,8 +4,11 @@
/aarch32/tools/ci.py
/aarch32/tools/get_toolchain.py
/aarch32/smart-env.sh
/aarch32/smart-env.bat
/aarch64/tools/gnu_gcc/*
/aarch64/tools/ci.py
/aarch64/tools/get_toolchain.py
/aarch64/smart-env.sh
**/**/makefile
/aarch64/smart-env.bat
**/**/makefile
/libraries/tests/*

212
bsp/phytium/aarch32/.config
View File

@ -9,6 +9,7 @@
CONFIG_RT_NAME_MAX=16
# CONFIG_RT_USING_ARCH_DATA_TYPE is not set
CONFIG_RT_USING_SMART=y
# CONFIG_RT_USING_AMP is not set
CONFIG_RT_USING_SMP=y
CONFIG_RT_CPUS_NR=2
CONFIG_RT_ALIGN_SIZE=4
@ -36,19 +37,11 @@ CONFIG_RT_KSERVICE_USING_STDLIB=y
# CONFIG_RT_KSERVICE_USING_TINY_SIZE is not set
# CONFIG_RT_USING_TINY_FFS is not set
CONFIG_RT_KPRINTF_USING_LONGLONG=y
CONFIG_RT_DEBUG=y
# CONFIG_RT_DEBUG_COLOR is not set
# CONFIG_RT_DEBUG_INIT_CONFIG is not set
# CONFIG_RT_DEBUG_THREAD_CONFIG is not set
# CONFIG_RT_DEBUG_SCHEDULER_CONFIG is not set
# CONFIG_RT_DEBUG_IPC_CONFIG is not set
# CONFIG_RT_DEBUG_TIMER_CONFIG is not set
# CONFIG_RT_DEBUG_IRQ_CONFIG is not set
# CONFIG_RT_DEBUG_MEM_CONFIG is not set
# CONFIG_RT_DEBUG_SLAB_CONFIG is not set
# CONFIG_RT_DEBUG_MEMHEAP_CONFIG is not set
# CONFIG_RT_DEBUG_PAGE_LEAK is not set
# CONFIG_RT_DEBUG_MODULE_CONFIG is not set
CONFIG_RT_USING_DEBUG=y
CONFIG_RT_DEBUGING_COLOR=y
CONFIG_RT_DEBUGING_CONTEXT=y
CONFIG_RT_DEBUGING_INIT=y
# CONFIG_RT_DEBUGING_PAGE_LEAK is not set
#
# Inter-Thread communication
@ -58,25 +51,26 @@ CONFIG_RT_USING_MUTEX=y
CONFIG_RT_USING_EVENT=y
CONFIG_RT_USING_MAILBOX=y
CONFIG_RT_USING_MESSAGEQUEUE=y
CONFIG_RT_USING_MESSAGEQUEUE_PRIORITY=y
# CONFIG_RT_USING_SIGNALS is not set
#
# Memory Management
#
CONFIG_RT_PAGE_MAX_ORDER=11
CONFIG_RT_USING_MEMPOOL=y
CONFIG_RT_USING_SMALL_MEM=y
# CONFIG_RT_USING_SLAB is not set
# CONFIG_RT_USING_MEMPOOL is not set
# CONFIG_RT_USING_SMALL_MEM is not set
CONFIG_RT_USING_SLAB=y
CONFIG_RT_USING_MEMHEAP=y
CONFIG_RT_MEMHEAP_FAST_MODE=y
# CONFIG_RT_MEMHEAP_BEST_MODE is not set
CONFIG_RT_USING_SMALL_MEM_AS_HEAP=y
# CONFIG_RT_USING_SMALL_MEM_AS_HEAP is not set
# CONFIG_RT_USING_MEMHEAP_AS_HEAP is not set
# CONFIG_RT_USING_SLAB_AS_HEAP is not set
CONFIG_RT_USING_SLAB_AS_HEAP=y
# CONFIG_RT_USING_USERHEAP is not set
# CONFIG_RT_USING_NOHEAP is not set
# CONFIG_RT_USING_MEMTRACE is not set
# CONFIG_RT_USING_HEAP_ISR is not set
CONFIG_RT_USING_HEAP_ISR=y
CONFIG_RT_USING_HEAP=y
#
@ -91,6 +85,10 @@ CONFIG_RT_CONSOLEBUF_SIZE=256
CONFIG_RT_CONSOLE_DEVICE_NAME="uart1"
CONFIG_RT_VER_NUM=0x50001
# CONFIG_RT_USING_STDC_ATOMIC is not set
#
# RT-Thread Architecture
#
CONFIG_RT_USING_CACHE=y
CONFIG_RT_USING_HW_ATOMIC=y
# CONFIG_ARCH_ARM_BOOTWITH_FLUSH_CACHE is not set
@ -144,12 +142,36 @@ CONFIG_RT_USING_DFS_V1=y
# CONFIG_RT_USING_DFS_V2 is not set
CONFIG_DFS_FILESYSTEMS_MAX=4
CONFIG_DFS_FILESYSTEM_TYPES_MAX=4
# CONFIG_RT_USING_DFS_ELMFAT is not set
CONFIG_RT_USING_DFS_ELMFAT=y
#
# elm-chan's FatFs, Generic FAT Filesystem Module
#
CONFIG_RT_DFS_ELM_CODE_PAGE=437
CONFIG_RT_DFS_ELM_WORD_ACCESS=y
# CONFIG_RT_DFS_ELM_USE_LFN_0 is not set
# CONFIG_RT_DFS_ELM_USE_LFN_1 is not set
# CONFIG_RT_DFS_ELM_USE_LFN_2 is not set
CONFIG_RT_DFS_ELM_USE_LFN_3=y
CONFIG_RT_DFS_ELM_USE_LFN=3
CONFIG_RT_DFS_ELM_LFN_UNICODE_0=y
# CONFIG_RT_DFS_ELM_LFN_UNICODE_1 is not set
# CONFIG_RT_DFS_ELM_LFN_UNICODE_2 is not set
# CONFIG_RT_DFS_ELM_LFN_UNICODE_3 is not set
CONFIG_RT_DFS_ELM_LFN_UNICODE=0
CONFIG_RT_DFS_ELM_MAX_LFN=255
CONFIG_RT_DFS_ELM_DRIVES=2
CONFIG_RT_DFS_ELM_MAX_SECTOR_SIZE=512
# CONFIG_RT_DFS_ELM_USE_ERASE is not set
CONFIG_RT_DFS_ELM_REENTRANT=y
CONFIG_RT_DFS_ELM_MUTEX_TIMEOUT=3000
CONFIG_RT_USING_DFS_DEVFS=y
# CONFIG_RT_USING_DFS_ROMFS is not set
# CONFIG_RT_USING_DFS_CROMFS is not set
CONFIG_RT_USING_DFS_RAMFS=y
# CONFIG_RT_USING_DFS_TMPFS is not set
CONFIG_RT_USING_DFS_MQUEUE=y
# CONFIG_RT_USING_DFS_NFS is not set
# CONFIG_RT_USING_FAL is not set
CONFIG_RT_USING_LWP=y
CONFIG_RT_LWP_MAX_NR=30
@ -195,7 +217,13 @@ CONFIG_RT_USING_RANDOM=y
CONFIG_RT_USING_RTC=y
# CONFIG_RT_USING_ALARM is not set
# CONFIG_RT_USING_SOFT_RTC is not set
# CONFIG_RT_USING_SDIO is not set
CONFIG_RT_USING_SDIO=y
CONFIG_RT_SDIO_STACK_SIZE=4096
CONFIG_RT_SDIO_THREAD_PRIORITY=15
CONFIG_RT_MMCSD_STACK_SIZE=4096
CONFIG_RT_MMCSD_THREAD_PREORITY=22
CONFIG_RT_MMCSD_MAX_PARTITION=16
# CONFIG_RT_SDIO_DEBUG is not set
# CONFIG_RT_USING_SPI is not set
# CONFIG_RT_USING_WDT is not set
# CONFIG_RT_USING_AUDIO is not set
@ -205,7 +233,7 @@ CONFIG_RT_USING_RTC=y
# CONFIG_RT_USING_HWCRYPTO is not set
# CONFIG_RT_USING_PULSE_ENCODER is not set
# CONFIG_RT_USING_INPUT_CAPTURE is not set
# CONFIG_RT_USING_DEV_BUS is not set
CONFIG_RT_USING_DEV_BUS=y
# CONFIG_RT_USING_WIFI is not set
# CONFIG_RT_USING_VIRTIO is not set
@ -229,6 +257,7 @@ CONFIG_RT_USING_POSIX_DEVIO=y
CONFIG_RT_USING_POSIX_STDIO=y
CONFIG_RT_USING_POSIX_POLL=y
CONFIG_RT_USING_POSIX_SELECT=y
# CONFIG_RT_USING_POSIX_EVENTFD is not set
# CONFIG_RT_USING_POSIX_SOCKET is not set
CONFIG_RT_USING_POSIX_TERMIOS=y
CONFIG_RT_USING_POSIX_AIO=y
@ -255,9 +284,82 @@ CONFIG_RT_USING_POSIX_MESSAGE_SEMAPHORE=y
#
# Network
#
# CONFIG_RT_USING_SAL is not set
# CONFIG_RT_USING_NETDEV is not set
# CONFIG_RT_USING_LWIP is not set
CONFIG_RT_USING_SAL=y
CONFIG_SAL_INTERNET_CHECK=y
#
# Docking with protocol stacks
#
CONFIG_SAL_USING_LWIP=y
# CONFIG_SAL_USING_AT is not set
# CONFIG_SAL_USING_TLS is not set
CONFIG_SAL_USING_POSIX=y
# CONFIG_SAL_USING_AF_UNIX is not set
CONFIG_RT_USING_NETDEV=y
CONFIG_NETDEV_USING_IFCONFIG=y
CONFIG_NETDEV_USING_PING=y
CONFIG_NETDEV_USING_NETSTAT=y
CONFIG_NETDEV_USING_AUTO_DEFAULT=y
# CONFIG_NETDEV_USING_IPV6 is not set
CONFIG_NETDEV_IPV4=1
CONFIG_NETDEV_IPV6=0
# CONFIG_NETDEV_IPV6_SCOPES is not set
CONFIG_RT_USING_LWIP=y
# CONFIG_RT_USING_LWIP_LOCAL_VERSION is not set
# CONFIG_RT_USING_LWIP141 is not set
# CONFIG_RT_USING_LWIP203 is not set
CONFIG_RT_USING_LWIP212=y
# CONFIG_RT_USING_LWIP_LATEST is not set
CONFIG_RT_USING_LWIP_VER_NUM=0x20102
# CONFIG_RT_USING_LWIP_IPV6 is not set
CONFIG_RT_LWIP_MEM_ALIGNMENT=64
CONFIG_RT_LWIP_IGMP=y
CONFIG_RT_LWIP_ICMP=y
# CONFIG_RT_LWIP_SNMP is not set
CONFIG_RT_LWIP_DNS=y
# CONFIG_RT_LWIP_DHCP is not set
#
# Static IPv4 Address
#
CONFIG_RT_LWIP_IPADDR="192.168.4.10"
CONFIG_RT_LWIP_GWADDR="192.168.4.1"
CONFIG_RT_LWIP_MSKADDR="255.255.255.0"
CONFIG_RT_LWIP_UDP=y
CONFIG_RT_LWIP_TCP=y
CONFIG_RT_LWIP_RAW=y
# CONFIG_RT_LWIP_PPP is not set
CONFIG_RT_MEMP_NUM_NETCONN=8
CONFIG_RT_LWIP_PBUF_NUM=512
CONFIG_RT_LWIP_RAW_PCB_NUM=4
CONFIG_RT_LWIP_UDP_PCB_NUM=4
CONFIG_RT_LWIP_TCP_PCB_NUM=4
CONFIG_RT_LWIP_TCP_SEG_NUM=40
CONFIG_RT_LWIP_TCP_SND_BUF=8196
CONFIG_RT_LWIP_TCP_WND=8196
CONFIG_RT_LWIP_TCPTHREAD_PRIORITY=12
CONFIG_RT_LWIP_TCPTHREAD_MBOX_SIZE=8
CONFIG_RT_LWIP_TCPTHREAD_STACKSIZE=16184
# CONFIG_LWIP_NO_RX_THREAD is not set
# CONFIG_LWIP_NO_TX_THREAD is not set
CONFIG_RT_LWIP_ETHTHREAD_PRIORITY=12
CONFIG_RT_LWIP_ETHTHREAD_STACKSIZE=2048
CONFIG_RT_LWIP_ETHTHREAD_MBOX_SIZE=8
# CONFIG_RT_LWIP_REASSEMBLY_FRAG is not set
CONFIG_LWIP_NETIF_STATUS_CALLBACK=1
CONFIG_LWIP_NETIF_LINK_CALLBACK=1
CONFIG_SO_REUSE=1
CONFIG_LWIP_SO_RCVTIMEO=1
CONFIG_LWIP_SO_SNDTIMEO=1
CONFIG_LWIP_SO_RCVBUF=1
CONFIG_LWIP_SO_LINGER=0
# CONFIG_RT_LWIP_NETIF_LOOPBACK is not set
CONFIG_LWIP_NETIF_LOOPBACK=0
# CONFIG_RT_LWIP_STATS is not set
# CONFIG_RT_LWIP_USING_HW_CHECKSUM is not set
CONFIG_RT_LWIP_USING_PING=y
# CONFIG_LWIP_USING_DHCPD is not set
# CONFIG_RT_LWIP_DEBUG is not set
# CONFIG_RT_USING_AT is not set
#
@ -271,10 +373,15 @@ CONFIG_RT_USING_UTEST=y
CONFIG_UTEST_THR_STACK_SIZE=4096
CONFIG_UTEST_THR_PRIORITY=20
# CONFIG_RT_USING_VAR_EXPORT is not set
CONFIG_RT_USING_RESOURCE_ID=y
CONFIG_RT_USING_ADT=y
CONFIG_RT_USING_ADT_AVL=y
CONFIG_RT_USING_ADT_BITMAP=y
CONFIG_RT_USING_ADT_HASHMAP=y
CONFIG_RT_USING_ADT_REF=y
# CONFIG_RT_USING_RT_LINK is not set
# CONFIG_RT_USING_VBUS is not set
CONFIG_RT_USING_KTIME=y
#
# RT-Thread Utestcases
@ -299,7 +406,6 @@ CONFIG_RT_USING_ADT_AVL=y
# CONFIG_PKG_USING_KAWAII_MQTT is not set
# CONFIG_PKG_USING_BC28_MQTT is not set
# CONFIG_PKG_USING_WEBTERMINAL is not set
# CONFIG_PKG_USING_LIBMODBUS is not set
# CONFIG_PKG_USING_FREEMODBUS is not set
# CONFIG_PKG_USING_NANOPB is not set
@ -571,6 +677,7 @@ CONFIG_RT_USING_ADT_AVL=y
# CONFIG_PKG_USING_QPC is not set
# CONFIG_PKG_USING_AGILE_UPGRADE is not set
# CONFIG_PKG_USING_FLASH_BLOB is not set
# CONFIG_PKG_USING_MLIBC is not set
#
# peripheral libraries and drivers
@ -635,6 +742,7 @@ CONFIG_RT_USING_ADT_AVL=y
# CONFIG_PKG_USING_BALANCE is not set
# CONFIG_PKG_USING_SHT2X is not set
# CONFIG_PKG_USING_SHT3X is not set
# CONFIG_PKG_USING_SHT4X is not set
# CONFIG_PKG_USING_AD7746 is not set
# CONFIG_PKG_USING_ADT74XX is not set
# CONFIG_PKG_USING_MAX17048 is not set
@ -655,6 +763,7 @@ CONFIG_RT_USING_ADT_AVL=y
# CONFIG_PKG_USING_FT5426 is not set
# CONFIG_PKG_USING_FT6236 is not set
# CONFIG_PKG_USING_XPT2046_TOUCH is not set
# CONFIG_PKG_USING_CST816X is not set
# CONFIG_PKG_USING_REALTEK_AMEBA is not set
# CONFIG_PKG_USING_STM32_SDIO is not set
# CONFIG_PKG_USING_ESP_IDF is not set
@ -730,7 +839,12 @@ CONFIG_RT_USING_ADT_AVL=y
# CONFIG_PKG_USING_IO_INPUT_FILTER is not set
# CONFIG_PKG_USING_RASPBERRYPI_PICO_SDK is not set
# CONFIG_PKG_USING_LRF_NV7LIDAR is not set
# CONFIG_PKG_USING_AIP650 is not set
# CONFIG_PKG_USING_FINGERPRINT is not set
# CONFIG_PKG_USING_BT_ECB02C is not set
# CONFIG_PKG_USING_UAT is not set
# CONFIG_PKG_USING_ST7789 is not set
# CONFIG_PKG_USING_SPI_TOOLS is not set
#
# AI packages
@ -749,7 +863,10 @@ CONFIG_RT_USING_ADT_AVL=y
# Signal Processing and Control Algorithm Packages
#
# CONFIG_PKG_USING_FIRE_PID_CURVE is not set
# CONFIG_PKG_USING_QPID is not set
# CONFIG_PKG_USING_UKAL is not set
# CONFIG_PKG_USING_DIGITALCTRL is not set
# CONFIG_PKG_USING_KISSFFT is not set
#
# miscellaneous packages
@ -796,7 +913,6 @@ CONFIG_RT_USING_ADT_AVL=y
# CONFIG_PKG_USING_DSTR is not set
# CONFIG_PKG_USING_TINYFRAME is not set
# CONFIG_PKG_USING_KENDRYTE_DEMO is not set
# CONFIG_PKG_USING_DIGITALCTRL is not set
# CONFIG_PKG_USING_UPACKER is not set
# CONFIG_PKG_USING_UPARAM is not set
# CONFIG_PKG_USING_HELLO is not set
@ -821,8 +937,9 @@ CONFIG_RT_USING_ADT_AVL=y
# CONFIG_PKG_USING_RTDUINO is not set
#
# Projects
# Projects and Demos
#
# CONFIG_PKG_USING_ARDUINO_MSGQ_C_CPP_DEMO is not set
# CONFIG_PKG_USING_ARDUINO_ULTRASOUND_RADAR is not set
# CONFIG_PKG_USING_ARDUINO_SENSOR_KIT is not set
# CONFIG_PKG_USING_ARDUINO_MATLAB_SUPPORT is not set
@ -969,14 +1086,20 @@ CONFIG_RT_USING_ADT_AVL=y
#
# Display
#
# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_GFX_LIBRARY is not set
# CONFIG_PKG_USING_ARDUINO_U8G2 is not set
# CONFIG_PKG_USING_ARDUINO_U8GLIB_ARDUINO is not set
# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_ST7735 is not set
# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_SSD1306 is not set
# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_ILI9341 is not set
# CONFIG_PKG_USING_SEEED_TM1637 is not set
#
# Timing
#
# CONFIG_PKG_USING_ARDUINO_RTCLIB is not set
# CONFIG_PKG_USING_ARDUINO_MSTIMER2 is not set
# CONFIG_PKG_USING_ARDUINO_TICKER is not set
# CONFIG_PKG_USING_ARDUINO_TASKSCHEDULER is not set
#
# Data Processing
@ -1010,7 +1133,6 @@ CONFIG_RT_USING_ADT_AVL=y
#
# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MFRC630 is not set
# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_SI5351 is not set
# CONFIG_PKG_USING_ARDUINO_RTCLIB is not set
#
# Signal IO
@ -1040,7 +1162,15 @@ CONFIG_RT_USING_UART1=y
# CONFIG_RT_USING_UART0 is not set
# CONFIG_BSP_USING_SPI is not set
# CONFIG_BSP_USING_CAN is not set
# CONFIG_BSP_USING_GPIO is not set
# CONFIG_BSP_USING_QSPI is not set
CONFIG_BSP_USING_ETH=y
CONFIG_RT_LWIP_PBUF_POOL_BUFSIZE=1700
CONFIG_BSP_USING_SDIO=y
CONFIG_BSP_USING_SDCARD_FATFS=y
# CONFIG_USING_SDIO0 is not set
CONFIG_USING_SDIO1=y
# CONFIG_USING_EMMC is not set
#
# Board extended module Drivers
@ -1073,6 +1203,8 @@ CONFIG_DEFAULT_DEBUG_PRINT_UART1=y
# CONFIG_USE_QSPI is not set
CONFIG_USE_GIC=y
CONFIG_ENABLE_GICV3=y
CONFIG_USE_IOPAD=y
CONFIG_ENABLE_IOPAD=y
CONFIG_USE_SERIAL=y
#
@ -1080,7 +1212,15 @@ CONFIG_USE_SERIAL=y
#
CONFIG_ENABLE_Pl011_UART=y
# CONFIG_USE_GPIO is not set
# CONFIG_USE_ETH is not set
CONFIG_USE_ETH=y
#
# Eth Configuration
#
CONFIG_ENABLE_FXMAC=y
# CONFIG_ENABLE_FGMAC is not set
CONFIG_FXMAC_PHY_COMMON=y
# CONFIG_FXMAC_PHY_YT is not set
# CONFIG_USE_CAN is not set
# CONFIG_USE_I2C is not set
# CONFIG_USE_TIMER is not set
@ -1098,15 +1238,19 @@ CONFIG_ENABLE_Pl011_UART=y
# CONFIG_USE_IPC is not set
# CONFIG_USE_MEDIA is not set
# CONFIG_USE_SCMI_MHU is not set
#
# Sdk common configuration
#
# CONFIG_LOG_VERBOS is not set
# CONFIG_LOG_DEBUG is not set
# CONFIG_LOG_INFO is not set
# CONFIG_LOG_WARN is not set
CONFIG_LOG_ERROR=y
# CONFIG_LOG_NONE is not set
CONFIG_USE_DEFAULT_INTERRUPT_CONFIG=y
CONFIG_INTERRUPT_ROLE_MASTER=y
# CONFIG_INTERRUPT_ROLE_SLAVE is not set
# CONFIG_LOG_EXTRA_INFO is not set
# CONFIG_LOG_DISPALY_CORE_NUM is not set
# CONFIG_BOOTUP_DEBUG_PRINTS is not set
CONFIG_USE_DEFAULT_INTERRUPT_CONFIG=y
CONFIG_INTERRUPT_ROLE_MASTER=y
# CONFIG_INTERRUPT_ROLE_SLAVE is not set

2
bsp/phytium/aarch32/Kconfig
View File

@ -49,6 +49,4 @@ menu "Standalone Setting"
source "$STANDALONE_DIR/board/Kconfig"
source "$STANDALONE_DIR/drivers/Kconfig"
source "$STANDALONE_DIR/common/Kconfig"
endmenu

6
bsp/phytium/aarch32/README.md
View File

@ -113,6 +113,12 @@ rtthread_a32.map
- 可以用串口通过 XMODEM 协议将 bin/elf 文件上传到开发板，然后启动，
- 如果使用 SD-1 控制器
```
mw.l 0x32b31178 0x1f
```
- 首先在 Phytium 开发板上输入，上传 bin 文件
```

99
bsp/phytium/aarch32/applications/mnt.c
View File

@ -8,56 +8,89 @@
* Change Logs:
* Date Author Notes
* 2023-04-27 huanghe first version
* 2023-07-14 liqiaozhong add SD file sys mount func
*
*/
#include <rtthread.h>
#ifdef RT_USING_DFS_RAMFS
#include <dfs_fs.h>
#if defined(RT_USING_DFS)
#include <rtdbg.h>
extern struct dfs_ramfs *dfs_ramfs_create(rt_uint8_t *pool, rt_size_t size);
int mnt_init(void)
{
rt_uint8_t *pool = RT_NULL;
rt_size_t size = 8*1024*1024;
pool = rt_malloc(size);
if (pool == RT_NULL)
return 0;
if (dfs_mount(RT_NULL, "/", "ram", 0, (const void *)dfs_ramfs_create(pool, size)) == 0)
rt_kprintf("RAM file system initializated!\n");
else
rt_kprintf("RAM file system initializate failed!\n");
return 0;
}
INIT_ENV_EXPORT(mnt_init);
#endif
#ifdef BSP_USING_SDCARD_FATFS
#include <dfs_fs.h>
#include <dfs_file.h>
#define DBG_TAG "app.filesystem"
#define DBG_LVL DBG_INFO
#include <rtdbg.h>
#ifdef BSP_USING_SDCARD_FATFS
#define SD_DEIVCE_NAME "sd"
static int filesystem_mount(void)
{
while(rt_device_find("sd0") == RT_NULL)
while (rt_device_find(SD_DEIVCE_NAME) == RT_NULL)
{
rt_thread_mdelay(1);
}
int ret = dfs_mount("sd0", "/", "elm", 0, 0);
if (ret != 0)
if (dfs_mount(SD_DEIVCE_NAME, "/", "elm", 0, 0) == 0)
{
rt_kprintf("ret: %d\n",ret);
LOG_E("sd0 mount to '/' failed!");
return ret;
LOG_I("file system initialization done!\n");
}
else
{
LOG_W("[sd] File System on SD initialization failed!");
LOG_W("[sd] Try to format and re-mount...");
if (dfs_mkfs("elm", SD_DEIVCE_NAME) == 0)
{
if (dfs_mount(SD_DEIVCE_NAME, "/", "elm", 0, 0) == 0)
{
LOG_I("[sd] File System on SD initialized!");
}
}
LOG_E("[sd] File System on SD initialization failed!");
return -1;
}
mkdir("/ram", 0x777);
#ifdef RT_USING_DFS_RAMFS
extern struct dfs_ramfs *dfs_ramfs_create(rt_uint8_t *pool, rt_size_t size);
rt_uint8_t *pool = RT_NULL;
rt_size_t size = 8 * 1024 * 1024;
pool = rt_malloc(size);
if (pool == RT_NULL)
LOG_E("Malloc fail!");
if (dfs_mount(RT_NULL, "/ram", "ram", 0, (const void *)dfs_ramfs_create(pool, size)) == 0)
LOG_I("RAM file system initializated!");
else
LOG_E("RAM file system initializate failed!");
#endif
return RT_EOK;
}
INIT_ENV_EXPORT(filesystem_mount);
#else
static int filesystem_mount(void)
{
#ifdef RT_USING_DFS_RAMFS
extern struct dfs_ramfs *dfs_ramfs_create(rt_uint8_t *pool, rt_size_t size);
rt_uint8_t *pool = RT_NULL;
rt_size_t size = 8 * 1024 * 1024;
pool = rt_malloc(size);
if (pool == RT_NULL)
LOG_E("Malloc fail!");
if (dfs_mount(RT_NULL, "/", "ram", 0, (const void *)dfs_ramfs_create(pool, size)) == 0)
LOG_I("RAM file system initializated!");
else
LOG_E("RAM file system initializate failed!");
#endif
return RT_EOK;
}
INIT_ENV_EXPORT(filesystem_mount);
#endif
#endif // #ifdef BSP_USING_SDCARD_FATFS
#endif // #if defined(RT_USING_DFS)

72
bsp/phytium/aarch32/boot/aarch32_boot.S
View File

@ -7,7 +7,8 @@
*
* Change Logs:
* Date Author Notes
* 2022-10-26 huanghe first commit
* 2022-10-26 huanghe first commit
* 2023-07-27 zhugengyu flush cache in aarch64-el2
*
*/
@ -18,8 +19,75 @@
.section .boot,"ax"
/* switch from aarch64-el2 to aarch32-el1 */
_boot:
/* hard code aarch64 instruction to flush dcache, refer to rt-thread __asm_flush_dcache_all */
.long 0xd2800000 /* mov x0, #0x0 // clean and invaildate d-cache */
.long 0x1400001a /* b <InvalidateFlushDcaches> */
InvalidateFlushDcacheLevel:
.long 0xd37ff80c /* lsl x12, x0, #1 */
.long 0xd51a000c /* msr csselr_el1, x12 */
.long 0xd5033fdf /* isb */
.long 0xd5390006 /* mrs x6, ccsidr_el1 */
.long 0x924008c2 /* and x2, x6, #0x7 */
.long 0x91001042 /* add x2, x2, #0x4 */
.long 0xd2807fe3 /* mov x3, #0x3ff */
.long 0x8a460c63 /* and x3, x3, x6, lsr #3 */
.long 0x5ac01065 /* clz w5, w3 */
.long 0xd28fffe4 /* mov x4, #0x7fff */
.long 0x8a463484 /* and x4, x4, x6, lsr #13 */
InvalidateFlushCacheSet:
.long 0xaa0303e6 /* mov x6, x3 */
InvalidateFlushCacheWay:
.long 0x9ac520c7 /* lsl x7, x6, x5 */
.long 0xaa070189 /* orr x9, x12, x7 */
.long 0x9ac22087 /* lsl x7, x4, x2 */
.long 0xaa070129 /* orr x9, x9, x7 */
.long 0x36000061 /* tbz w1, #0, <InvalidateFlushCacheWay+0x1c> */
.long 0xd5087649 /* dc isw, x9 */
.long 0x14000002 /* b <InvalidateFlushCacheWay+0x20> */
.long 0xd5087e49 /* dc cisw, x9 */
.long 0xf10004c6 /* subs x6, x6, #0x1 */
.long 0x54fffeea /* b.ge <InvalidateFlushCacheWay> */
.long 0xf1000484 /* subs x4, x4, #0x1 */
.long 0x54fffe8a /* b.ge <InvalidateFlushCacheSet> */
.long 0xd65f03c0 /* ret */
InvalidateFlushDcaches:
.long 0xaa0003e1 /* mov x1, x0 */
.long 0xd5033f9f /* dsb sy */
.long 0xd539002a /* mrs x10, clidr_el1 */
.long 0xd358fd4b /* lsr x11, x10, #24 */
.long 0x9240096b /* and x11, x11, #0x7 */
.long 0xb400024b /* cbz x11, <InvalidateFlushDcacheEnd> */
.long 0xaa1e03ef /* mov x15, x30 */
.long 0xd2800000 /* mov x0, #0x0 */
InvalidateFlushCachesLoopLevel:
.long 0xd37ff80c /* lsl x12, x0, #1 */
.long 0x8b00018c /* add x12, x12, x0 */
.long 0x9acc254c /* lsr x12, x10, x12 */
.long 0x9240098c /* and x12, x12, #0x7 */
.long 0xf100099f /* cmp x12, #0x2 */
.long 0x5400004b /* b.lt <InvalidateFlushCachesSkipLevel> */
.long 0x97ffffd9 /* bl <InvalidateFlushDcacheLevel> */
InvalidateFlushCachesSkipLevel:
.long 0x91000400 /* add x0, x0, #0x1 */
.long 0xeb00017f /* cmp x11, x0 */
.long 0x54fffeec /* b.gt <InvalidateFlushCachesLoopLevel> */
.long 0xd2800000 /* mov x0, #0x0 */
.long 0xd51a0000 /* msr csselr_el1, x0 */
.long 0xd5033f9f /* dsb sy */
.long 0xd5033fdf /* isb */
.long 0xaa0f03fe /* mov x30, x15 */
InvalidateFlushDcacheEnd:
/***************************************************************/
/* switch from aarch64-el2 to aarch32-el1 */
Startup_Aarch32:
.long 0xd5384240 /* mrs x0, currentel */
.long 0xd342fc00 /* lsr x0, x0, #2 */

187
bsp/phytium/aarch32/configs/e2000d_rtsmart
View File

@ -9,6 +9,7 @@
CONFIG_RT_NAME_MAX=16
# CONFIG_RT_USING_ARCH_DATA_TYPE is not set
CONFIG_RT_USING_SMART=y
# CONFIG_RT_USING_AMP is not set
CONFIG_RT_USING_SMP=y
CONFIG_RT_CPUS_NR=2
CONFIG_RT_ALIGN_SIZE=4
@ -36,19 +37,11 @@ CONFIG_RT_KSERVICE_USING_STDLIB=y
# CONFIG_RT_KSERVICE_USING_TINY_SIZE is not set
# CONFIG_RT_USING_TINY_FFS is not set
CONFIG_RT_KPRINTF_USING_LONGLONG=y
CONFIG_RT_DEBUG=y
# CONFIG_RT_DEBUG_COLOR is not set
# CONFIG_RT_DEBUG_INIT_CONFIG is not set
# CONFIG_RT_DEBUG_THREAD_CONFIG is not set
# CONFIG_RT_DEBUG_SCHEDULER_CONFIG is not set
# CONFIG_RT_DEBUG_IPC_CONFIG is not set
# CONFIG_RT_DEBUG_TIMER_CONFIG is not set
# CONFIG_RT_DEBUG_IRQ_CONFIG is not set
# CONFIG_RT_DEBUG_MEM_CONFIG is not set
# CONFIG_RT_DEBUG_SLAB_CONFIG is not set
# CONFIG_RT_DEBUG_MEMHEAP_CONFIG is not set
# CONFIG_RT_DEBUG_PAGE_LEAK is not set
# CONFIG_RT_DEBUG_MODULE_CONFIG is not set
CONFIG_RT_USING_DEBUG=y
CONFIG_RT_DEBUGING_COLOR=y
CONFIG_RT_DEBUGING_CONTEXT=y
CONFIG_RT_DEBUGING_INIT=y
# CONFIG_RT_DEBUGING_PAGE_LEAK is not set
#
# Inter-Thread communication
@ -58,25 +51,26 @@ CONFIG_RT_USING_MUTEX=y
CONFIG_RT_USING_EVENT=y
CONFIG_RT_USING_MAILBOX=y
CONFIG_RT_USING_MESSAGEQUEUE=y
CONFIG_RT_USING_MESSAGEQUEUE_PRIORITY=y
# CONFIG_RT_USING_SIGNALS is not set
#
# Memory Management
#
CONFIG_RT_PAGE_MAX_ORDER=11
CONFIG_RT_USING_MEMPOOL=y
CONFIG_RT_USING_SMALL_MEM=y
# CONFIG_RT_USING_SLAB is not set
# CONFIG_RT_USING_MEMPOOL is not set
# CONFIG_RT_USING_SMALL_MEM is not set
CONFIG_RT_USING_SLAB=y
CONFIG_RT_USING_MEMHEAP=y
CONFIG_RT_MEMHEAP_FAST_MODE=y
# CONFIG_RT_MEMHEAP_BEST_MODE is not set
CONFIG_RT_USING_SMALL_MEM_AS_HEAP=y
# CONFIG_RT_USING_SMALL_MEM_AS_HEAP is not set
# CONFIG_RT_USING_MEMHEAP_AS_HEAP is not set
# CONFIG_RT_USING_SLAB_AS_HEAP is not set
CONFIG_RT_USING_SLAB_AS_HEAP=y
# CONFIG_RT_USING_USERHEAP is not set
# CONFIG_RT_USING_NOHEAP is not set
# CONFIG_RT_USING_MEMTRACE is not set
# CONFIG_RT_USING_HEAP_ISR is not set
CONFIG_RT_USING_HEAP_ISR=y
CONFIG_RT_USING_HEAP=y
#
@ -91,6 +85,10 @@ CONFIG_RT_CONSOLEBUF_SIZE=256
CONFIG_RT_CONSOLE_DEVICE_NAME="uart1"
CONFIG_RT_VER_NUM=0x50001
# CONFIG_RT_USING_STDC_ATOMIC is not set
#
# RT-Thread Architecture
#
CONFIG_RT_USING_CACHE=y
CONFIG_RT_USING_HW_ATOMIC=y
# CONFIG_ARCH_ARM_BOOTWITH_FLUSH_CACHE is not set
@ -144,12 +142,36 @@ CONFIG_RT_USING_DFS_V1=y
# CONFIG_RT_USING_DFS_V2 is not set
CONFIG_DFS_FILESYSTEMS_MAX=4
CONFIG_DFS_FILESYSTEM_TYPES_MAX=4
# CONFIG_RT_USING_DFS_ELMFAT is not set
CONFIG_RT_USING_DFS_ELMFAT=y
#
# elm-chan's FatFs, Generic FAT Filesystem Module
#
CONFIG_RT_DFS_ELM_CODE_PAGE=437
CONFIG_RT_DFS_ELM_WORD_ACCESS=y
# CONFIG_RT_DFS_ELM_USE_LFN_0 is not set
# CONFIG_RT_DFS_ELM_USE_LFN_1 is not set
# CONFIG_RT_DFS_ELM_USE_LFN_2 is not set
CONFIG_RT_DFS_ELM_USE_LFN_3=y
CONFIG_RT_DFS_ELM_USE_LFN=3
CONFIG_RT_DFS_ELM_LFN_UNICODE_0=y
# CONFIG_RT_DFS_ELM_LFN_UNICODE_1 is not set
# CONFIG_RT_DFS_ELM_LFN_UNICODE_2 is not set
# CONFIG_RT_DFS_ELM_LFN_UNICODE_3 is not set
CONFIG_RT_DFS_ELM_LFN_UNICODE=0
CONFIG_RT_DFS_ELM_MAX_LFN=255
CONFIG_RT_DFS_ELM_DRIVES=2
CONFIG_RT_DFS_ELM_MAX_SECTOR_SIZE=512
# CONFIG_RT_DFS_ELM_USE_ERASE is not set
CONFIG_RT_DFS_ELM_REENTRANT=y
CONFIG_RT_DFS_ELM_MUTEX_TIMEOUT=3000
CONFIG_RT_USING_DFS_DEVFS=y
# CONFIG_RT_USING_DFS_ROMFS is not set
# CONFIG_RT_USING_DFS_CROMFS is not set
CONFIG_RT_USING_DFS_RAMFS=y
# CONFIG_RT_USING_DFS_TMPFS is not set
CONFIG_RT_USING_DFS_MQUEUE=y
# CONFIG_RT_USING_DFS_NFS is not set
# CONFIG_RT_USING_FAL is not set
CONFIG_RT_USING_LWP=y
CONFIG_RT_LWP_MAX_NR=30
@ -195,7 +217,13 @@ CONFIG_RT_USING_RANDOM=y
CONFIG_RT_USING_RTC=y
# CONFIG_RT_USING_ALARM is not set
# CONFIG_RT_USING_SOFT_RTC is not set
# CONFIG_RT_USING_SDIO is not set
CONFIG_RT_USING_SDIO=y
CONFIG_RT_SDIO_STACK_SIZE=4096
CONFIG_RT_SDIO_THREAD_PRIORITY=15
CONFIG_RT_MMCSD_STACK_SIZE=4096
CONFIG_RT_MMCSD_THREAD_PREORITY=22
CONFIG_RT_MMCSD_MAX_PARTITION=16
# CONFIG_RT_SDIO_DEBUG is not set
# CONFIG_RT_USING_SPI is not set
# CONFIG_RT_USING_WDT is not set
# CONFIG_RT_USING_AUDIO is not set
@ -205,7 +233,7 @@ CONFIG_RT_USING_RTC=y
# CONFIG_RT_USING_HWCRYPTO is not set
# CONFIG_RT_USING_PULSE_ENCODER is not set
# CONFIG_RT_USING_INPUT_CAPTURE is not set
# CONFIG_RT_USING_DEV_BUS is not set
CONFIG_RT_USING_DEV_BUS=y
# CONFIG_RT_USING_WIFI is not set
# CONFIG_RT_USING_VIRTIO is not set
@ -255,9 +283,82 @@ CONFIG_RT_USING_POSIX_MESSAGE_SEMAPHORE=y
#
# Network
#
# CONFIG_RT_USING_SAL is not set
# CONFIG_RT_USING_NETDEV is not set
# CONFIG_RT_USING_LWIP is not set
CONFIG_RT_USING_SAL=y
CONFIG_SAL_INTERNET_CHECK=y
#
# Docking with protocol stacks
#
CONFIG_SAL_USING_LWIP=y
# CONFIG_SAL_USING_AT is not set
# CONFIG_SAL_USING_TLS is not set
CONFIG_SAL_USING_POSIX=y
# CONFIG_SAL_USING_AF_UNIX is not set
CONFIG_RT_USING_NETDEV=y
CONFIG_NETDEV_USING_IFCONFIG=y
CONFIG_NETDEV_USING_PING=y
CONFIG_NETDEV_USING_NETSTAT=y
CONFIG_NETDEV_USING_AUTO_DEFAULT=y
# CONFIG_NETDEV_USING_IPV6 is not set
CONFIG_NETDEV_IPV4=1
CONFIG_NETDEV_IPV6=0
# CONFIG_NETDEV_IPV6_SCOPES is not set
CONFIG_RT_USING_LWIP=y
# CONFIG_RT_USING_LWIP_LOCAL_VERSION is not set
# CONFIG_RT_USING_LWIP141 is not set
# CONFIG_RT_USING_LWIP203 is not set
CONFIG_RT_USING_LWIP212=y
# CONFIG_RT_USING_LWIP_LATEST is not set
CONFIG_RT_USING_LWIP_VER_NUM=0x20102
# CONFIG_RT_USING_LWIP_IPV6 is not set
CONFIG_RT_LWIP_MEM_ALIGNMENT=64
CONFIG_RT_LWIP_IGMP=y
CONFIG_RT_LWIP_ICMP=y
# CONFIG_RT_LWIP_SNMP is not set
CONFIG_RT_LWIP_DNS=y
# CONFIG_RT_LWIP_DHCP is not set
#
# Static IPv4 Address
#
CONFIG_RT_LWIP_IPADDR="192.168.4.10"
CONFIG_RT_LWIP_GWADDR="192.168.4.1"
CONFIG_RT_LWIP_MSKADDR="255.255.255.0"
CONFIG_RT_LWIP_UDP=y
CONFIG_RT_LWIP_TCP=y
CONFIG_RT_LWIP_RAW=y
# CONFIG_RT_LWIP_PPP is not set
CONFIG_RT_MEMP_NUM_NETCONN=8
CONFIG_RT_LWIP_PBUF_NUM=512
CONFIG_RT_LWIP_RAW_PCB_NUM=4
CONFIG_RT_LWIP_UDP_PCB_NUM=4
CONFIG_RT_LWIP_TCP_PCB_NUM=4
CONFIG_RT_LWIP_TCP_SEG_NUM=40
CONFIG_RT_LWIP_TCP_SND_BUF=8196
CONFIG_RT_LWIP_TCP_WND=8196
CONFIG_RT_LWIP_TCPTHREAD_PRIORITY=12
CONFIG_RT_LWIP_TCPTHREAD_MBOX_SIZE=8
CONFIG_RT_LWIP_TCPTHREAD_STACKSIZE=16184
# CONFIG_LWIP_NO_RX_THREAD is not set
# CONFIG_LWIP_NO_TX_THREAD is not set
CONFIG_RT_LWIP_ETHTHREAD_PRIORITY=12
CONFIG_RT_LWIP_ETHTHREAD_STACKSIZE=2048
CONFIG_RT_LWIP_ETHTHREAD_MBOX_SIZE=8
# CONFIG_RT_LWIP_REASSEMBLY_FRAG is not set
CONFIG_LWIP_NETIF_STATUS_CALLBACK=1
CONFIG_LWIP_NETIF_LINK_CALLBACK=1
CONFIG_SO_REUSE=1
CONFIG_LWIP_SO_RCVTIMEO=1
CONFIG_LWIP_SO_SNDTIMEO=1
CONFIG_LWIP_SO_RCVBUF=1
CONFIG_LWIP_SO_LINGER=0
# CONFIG_RT_LWIP_NETIF_LOOPBACK is not set
CONFIG_LWIP_NETIF_LOOPBACK=0
# CONFIG_RT_LWIP_STATS is not set
# CONFIG_RT_LWIP_USING_HW_CHECKSUM is not set
CONFIG_RT_LWIP_USING_PING=y
# CONFIG_LWIP_USING_DHCPD is not set
# CONFIG_RT_LWIP_DEBUG is not set
# CONFIG_RT_USING_AT is not set
#
@ -271,9 +372,15 @@ CONFIG_RT_USING_UTEST=y
CONFIG_UTEST_THR_STACK_SIZE=4096
CONFIG_UTEST_THR_PRIORITY=20
# CONFIG_RT_USING_VAR_EXPORT is not set
CONFIG_RT_USING_RESOURCE_ID=y
CONFIG_RT_USING_ADT=y
CONFIG_RT_USING_ADT_AVL=y
CONFIG_RT_USING_ADT_BITMAP=y
CONFIG_RT_USING_ADT_HASHMAP=y
CONFIG_RT_USING_ADT_REF=y
# CONFIG_RT_USING_RT_LINK is not set
# CONFIG_RT_USING_VBUS is not set
CONFIG_RT_USING_KTIME=y
#
# RT-Thread Utestcases
@ -1039,7 +1146,15 @@ CONFIG_RT_USING_UART1=y
# CONFIG_RT_USING_UART0 is not set
# CONFIG_BSP_USING_SPI is not set
# CONFIG_BSP_USING_CAN is not set
# CONFIG_BSP_USING_GPIO is not set
# CONFIG_BSP_USING_QSPI is not set
CONFIG_BSP_USING_ETH=y
CONFIG_RT_LWIP_PBUF_POOL_BUFSIZE=1700
CONFIG_BSP_USING_SDIO=y
CONFIG_BSP_USING_SDCARD_FATFS=y
# CONFIG_USING_SDIO0 is not set
CONFIG_USING_SDIO1=y
# CONFIG_USING_EMMC is not set
#
# Board extended module Drivers
@ -1072,6 +1187,8 @@ CONFIG_DEFAULT_DEBUG_PRINT_UART1=y
# CONFIG_USE_QSPI is not set
CONFIG_USE_GIC=y
CONFIG_ENABLE_GICV3=y
CONFIG_USE_IOPAD=y
CONFIG_ENABLE_IOPAD=y
CONFIG_USE_SERIAL=y
#
@ -1079,7 +1196,15 @@ CONFIG_USE_SERIAL=y
#
CONFIG_ENABLE_Pl011_UART=y
# CONFIG_USE_GPIO is not set
# CONFIG_USE_ETH is not set
CONFIG_USE_ETH=y
#
# Eth Configuration
#
CONFIG_ENABLE_FXMAC=y
# CONFIG_ENABLE_FGMAC is not set
CONFIG_FXMAC_PHY_COMMON=y
# CONFIG_FXMAC_PHY_YT is not set
# CONFIG_USE_CAN is not set
# CONFIG_USE_I2C is not set
# CONFIG_USE_TIMER is not set
@ -1097,15 +1222,19 @@ CONFIG_ENABLE_Pl011_UART=y
# CONFIG_USE_IPC is not set
# CONFIG_USE_MEDIA is not set
# CONFIG_USE_SCMI_MHU is not set
#
# Sdk common configuration
#
# CONFIG_LOG_VERBOS is not set
# CONFIG_LOG_DEBUG is not set
# CONFIG_LOG_INFO is not set
# CONFIG_LOG_WARN is not set
CONFIG_LOG_ERROR=y
# CONFIG_LOG_NONE is not set
CONFIG_USE_DEFAULT_INTERRUPT_CONFIG=y
CONFIG_INTERRUPT_ROLE_MASTER=y
# CONFIG_INTERRUPT_ROLE_SLAVE is not set
# CONFIG_LOG_EXTRA_INFO is not set
# CONFIG_LOG_DISPALY_CORE_NUM is not set
# CONFIG_BOOTUP_DEBUG_PRINTS is not set
CONFIG_USE_DEFAULT_INTERRUPT_CONFIG=y
CONFIG_INTERRUPT_ROLE_MASTER=y
# CONFIG_INTERRUPT_ROLE_SLAVE is not set

111
bsp/phytium/aarch32/configs/e2000d_rtsmart.h
View File

@ -30,6 +30,9 @@
#define RT_KSERVICE_USING_STDLIB
#define RT_KPRINTF_USING_LONGLONG
#define RT_USING_DEBUG
#define RT_DEBUGING_COLOR
#define RT_DEBUGING_CONTEXT
#define RT_DEBUGING_INIT
/* Inter-Thread communication */
@ -38,15 +41,16 @@
#define RT_USING_EVENT
#define RT_USING_MAILBOX
#define RT_USING_MESSAGEQUEUE
#define RT_USING_MESSAGEQUEUE_PRIORITY
/* Memory Management */
#define RT_PAGE_MAX_ORDER 11
#define RT_USING_MEMPOOL
#define RT_USING_SMALL_MEM
#define RT_USING_SLAB
#define RT_USING_MEMHEAP
#define RT_MEMHEAP_FAST_MODE
#define RT_USING_SMALL_MEM_AS_HEAP
#define RT_USING_SLAB_AS_HEAP
#define RT_USING_HEAP_ISR
#define RT_USING_HEAP
/* Kernel Device Object */
@ -56,6 +60,9 @@
#define RT_CONSOLEBUF_SIZE 256
#define RT_CONSOLE_DEVICE_NAME "uart1"
#define RT_VER_NUM 0x50001
/* RT-Thread Architecture */
#define RT_USING_CACHE
#define RT_USING_HW_ATOMIC
#define RT_USING_CPU_FFS
@ -95,8 +102,24 @@
#define RT_USING_DFS_V1
#define DFS_FILESYSTEMS_MAX 4
#define DFS_FILESYSTEM_TYPES_MAX 4
#define RT_USING_DFS_ELMFAT
/* elm-chan's FatFs, Generic FAT Filesystem Module */
#define RT_DFS_ELM_CODE_PAGE 437
#define RT_DFS_ELM_WORD_ACCESS
#define RT_DFS_ELM_USE_LFN_3
#define RT_DFS_ELM_USE_LFN 3
#define RT_DFS_ELM_LFN_UNICODE_0
#define RT_DFS_ELM_LFN_UNICODE 0
#define RT_DFS_ELM_MAX_LFN 255
#define RT_DFS_ELM_DRIVES 2
#define RT_DFS_ELM_MAX_SECTOR_SIZE 512
#define RT_DFS_ELM_REENTRANT
#define RT_DFS_ELM_MUTEX_TIMEOUT 3000
#define RT_USING_DFS_DEVFS
#define RT_USING_DFS_RAMFS
#define RT_USING_DFS_MQUEUE
#define RT_USING_LWP
#define RT_LWP_MAX_NR 30
#define LWP_TASK_STACK_SIZE 16384
@ -122,6 +145,13 @@
#define RT_USING_ZERO
#define RT_USING_RANDOM
#define RT_USING_RTC
#define RT_USING_SDIO
#define RT_SDIO_STACK_SIZE 4096
#define RT_SDIO_THREAD_PRIORITY 15
#define RT_MMCSD_STACK_SIZE 4096
#define RT_MMCSD_THREAD_PREORITY 22
#define RT_MMCSD_MAX_PARTITION 16
#define RT_USING_DEV_BUS
/* Using USB */
@ -155,6 +185,59 @@
/* Network */
#define RT_USING_SAL
#define SAL_INTERNET_CHECK
/* Docking with protocol stacks */
#define SAL_USING_LWIP
#define SAL_USING_POSIX
#define RT_USING_NETDEV
#define NETDEV_USING_IFCONFIG
#define NETDEV_USING_PING
#define NETDEV_USING_NETSTAT
#define NETDEV_USING_AUTO_DEFAULT
#define NETDEV_IPV4 1
#define NETDEV_IPV6 0
#define RT_USING_LWIP
#define RT_USING_LWIP212
#define RT_USING_LWIP_VER_NUM 0x20102
#define RT_LWIP_MEM_ALIGNMENT 64
#define RT_LWIP_IGMP
#define RT_LWIP_ICMP
#define RT_LWIP_DNS
/* Static IPv4 Address */
#define RT_LWIP_IPADDR "192.168.4.10"
#define RT_LWIP_GWADDR "192.168.4.1"
#define RT_LWIP_MSKADDR "255.255.255.0"
#define RT_LWIP_UDP
#define RT_LWIP_TCP
#define RT_LWIP_RAW
#define RT_MEMP_NUM_NETCONN 8
#define RT_LWIP_PBUF_NUM 512
#define RT_LWIP_RAW_PCB_NUM 4
#define RT_LWIP_UDP_PCB_NUM 4
#define RT_LWIP_TCP_PCB_NUM 4
#define RT_LWIP_TCP_SEG_NUM 40
#define RT_LWIP_TCP_SND_BUF 8196
#define RT_LWIP_TCP_WND 8196
#define RT_LWIP_TCPTHREAD_PRIORITY 12
#define RT_LWIP_TCPTHREAD_MBOX_SIZE 8
#define RT_LWIP_TCPTHREAD_STACKSIZE 16184
#define RT_LWIP_ETHTHREAD_PRIORITY 12
#define RT_LWIP_ETHTHREAD_STACKSIZE 2048
#define RT_LWIP_ETHTHREAD_MBOX_SIZE 8
#define LWIP_NETIF_STATUS_CALLBACK 1
#define LWIP_NETIF_LINK_CALLBACK 1
#define SO_REUSE 1
#define LWIP_SO_RCVTIMEO 1
#define LWIP_SO_SNDTIMEO 1
#define LWIP_SO_RCVBUF 1
#define LWIP_SO_LINGER 0
#define LWIP_NETIF_LOOPBACK 0
#define RT_LWIP_USING_PING
/* Utilities */
@ -163,7 +246,13 @@
#define RT_USING_UTEST
#define UTEST_THR_STACK_SIZE 4096
#define UTEST_THR_PRIORITY 20
#define RT_USING_RESOURCE_ID
#define RT_USING_ADT
#define RT_USING_ADT_AVL
#define RT_USING_ADT_BITMAP
#define RT_USING_ADT_HASHMAP
#define RT_USING_ADT_REF
#define RT_USING_KTIME
/* RT-Thread Utestcases */
@ -287,6 +376,11 @@
#define BSP_USING_UART
#define RT_USING_UART1
#define BSP_USING_ETH
#define RT_LWIP_PBUF_POOL_BUFSIZE 1700
#define BSP_USING_SDIO
#define BSP_USING_SDCARD_FATFS
#define USING_SDIO1
/* Board extended module Drivers */
@ -307,11 +401,22 @@
#define USE_GIC
#define ENABLE_GICV3
#define USE_IOPAD
#define ENABLE_IOPAD
#define USE_SERIAL
/* Usart Configuration */
#define ENABLE_Pl011_UART
#define USE_ETH
/* Eth Configuration */
#define ENABLE_FXMAC
#define FXMAC_PHY_COMMON
/* Sdk common configuration */
#define LOG_ERROR
#define USE_DEFAULT_INTERRUPT_CONFIG
#define INTERRUPT_ROLE_MASTER

187
bsp/phytium/aarch32/configs/e2000d_rtthread
View File

@ -9,6 +9,7 @@
CONFIG_RT_NAME_MAX=16
# CONFIG_RT_USING_ARCH_DATA_TYPE is not set
# CONFIG_RT_USING_SMART is not set
# CONFIG_RT_USING_AMP is not set
CONFIG_RT_USING_SMP=y
CONFIG_RT_CPUS_NR=2
CONFIG_RT_ALIGN_SIZE=4
@ -36,19 +37,11 @@ CONFIG_RT_KSERVICE_USING_STDLIB=y
# CONFIG_RT_KSERVICE_USING_TINY_SIZE is not set
# CONFIG_RT_USING_TINY_FFS is not set
CONFIG_RT_KPRINTF_USING_LONGLONG=y
CONFIG_RT_DEBUG=y
# CONFIG_RT_DEBUG_COLOR is not set
# CONFIG_RT_DEBUG_INIT_CONFIG is not set
# CONFIG_RT_DEBUG_THREAD_CONFIG is not set
# CONFIG_RT_DEBUG_SCHEDULER_CONFIG is not set
# CONFIG_RT_DEBUG_IPC_CONFIG is not set
# CONFIG_RT_DEBUG_TIMER_CONFIG is not set
# CONFIG_RT_DEBUG_IRQ_CONFIG is not set
# CONFIG_RT_DEBUG_MEM_CONFIG is not set
# CONFIG_RT_DEBUG_SLAB_CONFIG is not set
# CONFIG_RT_DEBUG_MEMHEAP_CONFIG is not set
# CONFIG_RT_DEBUG_PAGE_LEAK is not set
# CONFIG_RT_DEBUG_MODULE_CONFIG is not set
CONFIG_RT_USING_DEBUG=y
CONFIG_RT_DEBUGING_COLOR=y
CONFIG_RT_DEBUGING_CONTEXT=y
CONFIG_RT_DEBUGING_INIT=y
# CONFIG_RT_DEBUGING_PAGE_LEAK is not set
#
# Inter-Thread communication
@ -58,25 +51,26 @@ CONFIG_RT_USING_MUTEX=y
CONFIG_RT_USING_EVENT=y
CONFIG_RT_USING_MAILBOX=y
CONFIG_RT_USING_MESSAGEQUEUE=y
CONFIG_RT_USING_MESSAGEQUEUE_PRIORITY=y
# CONFIG_RT_USING_SIGNALS is not set
#
# Memory Management
#
CONFIG_RT_PAGE_MAX_ORDER=11
CONFIG_RT_USING_MEMPOOL=y
CONFIG_RT_USING_SMALL_MEM=y
# CONFIG_RT_USING_SLAB is not set
# CONFIG_RT_USING_MEMPOOL is not set
# CONFIG_RT_USING_SMALL_MEM is not set
CONFIG_RT_USING_SLAB=y
CONFIG_RT_USING_MEMHEAP=y
CONFIG_RT_MEMHEAP_FAST_MODE=y
# CONFIG_RT_MEMHEAP_BEST_MODE is not set
CONFIG_RT_USING_SMALL_MEM_AS_HEAP=y
# CONFIG_RT_USING_SMALL_MEM_AS_HEAP is not set
# CONFIG_RT_USING_MEMHEAP_AS_HEAP is not set
# CONFIG_RT_USING_SLAB_AS_HEAP is not set
CONFIG_RT_USING_SLAB_AS_HEAP=y
# CONFIG_RT_USING_USERHEAP is not set
# CONFIG_RT_USING_NOHEAP is not set
# CONFIG_RT_USING_MEMTRACE is not set
# CONFIG_RT_USING_HEAP_ISR is not set
CONFIG_RT_USING_HEAP_ISR=y
CONFIG_RT_USING_HEAP=y
#
@ -91,6 +85,10 @@ CONFIG_RT_CONSOLEBUF_SIZE=256
CONFIG_RT_CONSOLE_DEVICE_NAME="uart1"
CONFIG_RT_VER_NUM=0x50001
# CONFIG_RT_USING_STDC_ATOMIC is not set
#
# RT-Thread Architecture
#
CONFIG_RT_USING_CACHE=y
CONFIG_RT_USING_HW_ATOMIC=y
# CONFIG_ARCH_ARM_BOOTWITH_FLUSH_CACHE is not set
@ -142,12 +140,36 @@ CONFIG_RT_USING_DFS_V1=y
# CONFIG_RT_USING_DFS_V2 is not set
CONFIG_DFS_FILESYSTEMS_MAX=4
CONFIG_DFS_FILESYSTEM_TYPES_MAX=4
# CONFIG_RT_USING_DFS_ELMFAT is not set
CONFIG_RT_USING_DFS_ELMFAT=y
#
# elm-chan's FatFs, Generic FAT Filesystem Module
#
CONFIG_RT_DFS_ELM_CODE_PAGE=437
CONFIG_RT_DFS_ELM_WORD_ACCESS=y
# CONFIG_RT_DFS_ELM_USE_LFN_0 is not set
# CONFIG_RT_DFS_ELM_USE_LFN_1 is not set
# CONFIG_RT_DFS_ELM_USE_LFN_2 is not set
CONFIG_RT_DFS_ELM_USE_LFN_3=y
CONFIG_RT_DFS_ELM_USE_LFN=3
CONFIG_RT_DFS_ELM_LFN_UNICODE_0=y
# CONFIG_RT_DFS_ELM_LFN_UNICODE_1 is not set
# CONFIG_RT_DFS_ELM_LFN_UNICODE_2 is not set
# CONFIG_RT_DFS_ELM_LFN_UNICODE_3 is not set
CONFIG_RT_DFS_ELM_LFN_UNICODE=0
CONFIG_RT_DFS_ELM_MAX_LFN=255
CONFIG_RT_DFS_ELM_DRIVES=2
CONFIG_RT_DFS_ELM_MAX_SECTOR_SIZE=512
# CONFIG_RT_DFS_ELM_USE_ERASE is not set
CONFIG_RT_DFS_ELM_REENTRANT=y
CONFIG_RT_DFS_ELM_MUTEX_TIMEOUT=3000
CONFIG_RT_USING_DFS_DEVFS=y
# CONFIG_RT_USING_DFS_ROMFS is not set
# CONFIG_RT_USING_DFS_CROMFS is not set
CONFIG_RT_USING_DFS_RAMFS=y
# CONFIG_RT_USING_DFS_TMPFS is not set
CONFIG_RT_USING_DFS_MQUEUE=y
# CONFIG_RT_USING_DFS_NFS is not set
# CONFIG_RT_USING_FAL is not set
#
@ -182,7 +204,13 @@ CONFIG_RT_USING_RANDOM=y
CONFIG_RT_USING_RTC=y
# CONFIG_RT_USING_ALARM is not set
# CONFIG_RT_USING_SOFT_RTC is not set
# CONFIG_RT_USING_SDIO is not set
CONFIG_RT_USING_SDIO=y
CONFIG_RT_SDIO_STACK_SIZE=4096
CONFIG_RT_SDIO_THREAD_PRIORITY=15
CONFIG_RT_MMCSD_STACK_SIZE=4096
CONFIG_RT_MMCSD_THREAD_PREORITY=22
CONFIG_RT_MMCSD_MAX_PARTITION=16
# CONFIG_RT_SDIO_DEBUG is not set
# CONFIG_RT_USING_SPI is not set
# CONFIG_RT_USING_WDT is not set
# CONFIG_RT_USING_AUDIO is not set
@ -192,7 +220,7 @@ CONFIG_RT_USING_RTC=y
# CONFIG_RT_USING_HWCRYPTO is not set
# CONFIG_RT_USING_PULSE_ENCODER is not set
# CONFIG_RT_USING_INPUT_CAPTURE is not set
# CONFIG_RT_USING_DEV_BUS is not set
CONFIG_RT_USING_DEV_BUS=y
# CONFIG_RT_USING_WIFI is not set
# CONFIG_RT_USING_VIRTIO is not set
@ -242,9 +270,82 @@ CONFIG_RT_USING_POSIX_MESSAGE_SEMAPHORE=y
#
# Network
#
# CONFIG_RT_USING_SAL is not set
# CONFIG_RT_USING_NETDEV is not set
# CONFIG_RT_USING_LWIP is not set
CONFIG_RT_USING_SAL=y
CONFIG_SAL_INTERNET_CHECK=y
#
# Docking with protocol stacks
#
CONFIG_SAL_USING_LWIP=y
# CONFIG_SAL_USING_AT is not set
# CONFIG_SAL_USING_TLS is not set
CONFIG_SAL_USING_POSIX=y
# CONFIG_SAL_USING_AF_UNIX is not set
CONFIG_RT_USING_NETDEV=y
CONFIG_NETDEV_USING_IFCONFIG=y
CONFIG_NETDEV_USING_PING=y
CONFIG_NETDEV_USING_NETSTAT=y
CONFIG_NETDEV_USING_AUTO_DEFAULT=y
# CONFIG_NETDEV_USING_IPV6 is not set
CONFIG_NETDEV_IPV4=1
CONFIG_NETDEV_IPV6=0
# CONFIG_NETDEV_IPV6_SCOPES is not set
CONFIG_RT_USING_LWIP=y
# CONFIG_RT_USING_LWIP_LOCAL_VERSION is not set
# CONFIG_RT_USING_LWIP141 is not set
# CONFIG_RT_USING_LWIP203 is not set
CONFIG_RT_USING_LWIP212=y
# CONFIG_RT_USING_LWIP_LATEST is not set
CONFIG_RT_USING_LWIP_VER_NUM=0x20102
# CONFIG_RT_USING_LWIP_IPV6 is not set
CONFIG_RT_LWIP_MEM_ALIGNMENT=64
CONFIG_RT_LWIP_IGMP=y
CONFIG_RT_LWIP_ICMP=y
# CONFIG_RT_LWIP_SNMP is not set
CONFIG_RT_LWIP_DNS=y
# CONFIG_RT_LWIP_DHCP is not set
#
# Static IPv4 Address
#
CONFIG_RT_LWIP_IPADDR="192.168.4.10"
CONFIG_RT_LWIP_GWADDR="192.168.4.1"
CONFIG_RT_LWIP_MSKADDR="255.255.255.0"
CONFIG_RT_LWIP_UDP=y
CONFIG_RT_LWIP_TCP=y
CONFIG_RT_LWIP_RAW=y
# CONFIG_RT_LWIP_PPP is not set
CONFIG_RT_MEMP_NUM_NETCONN=8
CONFIG_RT_LWIP_PBUF_NUM=512
CONFIG_RT_LWIP_RAW_PCB_NUM=4
CONFIG_RT_LWIP_UDP_PCB_NUM=4
CONFIG_RT_LWIP_TCP_PCB_NUM=4
CONFIG_RT_LWIP_TCP_SEG_NUM=40
CONFIG_RT_LWIP_TCP_SND_BUF=8196
CONFIG_RT_LWIP_TCP_WND=8196
CONFIG_RT_LWIP_TCPTHREAD_PRIORITY=12
CONFIG_RT_LWIP_TCPTHREAD_MBOX_SIZE=8
CONFIG_RT_LWIP_TCPTHREAD_STACKSIZE=16184
# CONFIG_LWIP_NO_RX_THREAD is not set
# CONFIG_LWIP_NO_TX_THREAD is not set
CONFIG_RT_LWIP_ETHTHREAD_PRIORITY=12
CONFIG_RT_LWIP_ETHTHREAD_STACKSIZE=2048
CONFIG_RT_LWIP_ETHTHREAD_MBOX_SIZE=8
# CONFIG_RT_LWIP_REASSEMBLY_FRAG is not set
CONFIG_LWIP_NETIF_STATUS_CALLBACK=1
CONFIG_LWIP_NETIF_LINK_CALLBACK=1
CONFIG_SO_REUSE=1
CONFIG_LWIP_SO_RCVTIMEO=1
CONFIG_LWIP_SO_SNDTIMEO=1
CONFIG_LWIP_SO_RCVBUF=1
CONFIG_LWIP_SO_LINGER=0
# CONFIG_RT_LWIP_NETIF_LOOPBACK is not set
CONFIG_LWIP_NETIF_LOOPBACK=0
# CONFIG_RT_LWIP_STATS is not set
# CONFIG_RT_LWIP_USING_HW_CHECKSUM is not set
CONFIG_RT_LWIP_USING_PING=y
# CONFIG_LWIP_USING_DHCPD is not set
# CONFIG_RT_LWIP_DEBUG is not set
# CONFIG_RT_USING_AT is not set
#
@ -258,9 +359,15 @@ CONFIG_RT_USING_UTEST=y
CONFIG_UTEST_THR_STACK_SIZE=4096
CONFIG_UTEST_THR_PRIORITY=20
# CONFIG_RT_USING_VAR_EXPORT is not set
CONFIG_RT_USING_RESOURCE_ID=y
CONFIG_RT_USING_ADT=y
CONFIG_RT_USING_ADT_AVL=y
CONFIG_RT_USING_ADT_BITMAP=y
CONFIG_RT_USING_ADT_HASHMAP=y
CONFIG_RT_USING_ADT_REF=y
# CONFIG_RT_USING_RT_LINK is not set
# CONFIG_RT_USING_VBUS is not set
CONFIG_RT_USING_KTIME=y
#
# RT-Thread Utestcases
@ -1026,7 +1133,15 @@ CONFIG_RT_USING_UART1=y
# CONFIG_RT_USING_UART0 is not set
# CONFIG_BSP_USING_SPI is not set
# CONFIG_BSP_USING_CAN is not set
# CONFIG_BSP_USING_GPIO is not set
# CONFIG_BSP_USING_QSPI is not set
CONFIG_BSP_USING_ETH=y
CONFIG_RT_LWIP_PBUF_POOL_BUFSIZE=1700
CONFIG_BSP_USING_SDIO=y
CONFIG_BSP_USING_SDCARD_FATFS=y
# CONFIG_USING_SDIO0 is not set
CONFIG_USING_SDIO1=y
# CONFIG_USING_EMMC is not set
#
# Board extended module Drivers
@ -1059,6 +1174,8 @@ CONFIG_DEFAULT_DEBUG_PRINT_UART1=y
# CONFIG_USE_QSPI is not set
CONFIG_USE_GIC=y
CONFIG_ENABLE_GICV3=y
CONFIG_USE_IOPAD=y
CONFIG_ENABLE_IOPAD=y
CONFIG_USE_SERIAL=y
#
@ -1066,7 +1183,15 @@ CONFIG_USE_SERIAL=y
#
CONFIG_ENABLE_Pl011_UART=y
# CONFIG_USE_GPIO is not set
# CONFIG_USE_ETH is not set
CONFIG_USE_ETH=y
#
# Eth Configuration
#
CONFIG_ENABLE_FXMAC=y
# CONFIG_ENABLE_FGMAC is not set
CONFIG_FXMAC_PHY_COMMON=y
# CONFIG_FXMAC_PHY_YT is not set
# CONFIG_USE_CAN is not set
# CONFIG_USE_I2C is not set
# CONFIG_USE_TIMER is not set
@ -1084,15 +1209,19 @@ CONFIG_ENABLE_Pl011_UART=y
# CONFIG_USE_IPC is not set
# CONFIG_USE_MEDIA is not set
# CONFIG_USE_SCMI_MHU is not set
#
# Sdk common configuration
#
# CONFIG_LOG_VERBOS is not set
# CONFIG_LOG_DEBUG is not set
# CONFIG_LOG_INFO is not set
# CONFIG_LOG_WARN is not set
CONFIG_LOG_ERROR=y
# CONFIG_LOG_NONE is not set
CONFIG_USE_DEFAULT_INTERRUPT_CONFIG=y
CONFIG_INTERRUPT_ROLE_MASTER=y
# CONFIG_INTERRUPT_ROLE_SLAVE is not set
# CONFIG_LOG_EXTRA_INFO is not set
# CONFIG_LOG_DISPALY_CORE_NUM is not set
# CONFIG_BOOTUP_DEBUG_PRINTS is not set
CONFIG_USE_DEFAULT_INTERRUPT_CONFIG=y
CONFIG_INTERRUPT_ROLE_MASTER=y
# CONFIG_INTERRUPT_ROLE_SLAVE is not set

111
bsp/phytium/aarch32/configs/e2000d_rtthread.h
View File

@ -29,6 +29,9 @@
#define RT_KSERVICE_USING_STDLIB
#define RT_KPRINTF_USING_LONGLONG
#define RT_USING_DEBUG
#define RT_DEBUGING_COLOR
#define RT_DEBUGING_CONTEXT
#define RT_DEBUGING_INIT
/* Inter-Thread communication */
@ -37,15 +40,16 @@
#define RT_USING_EVENT
#define RT_USING_MAILBOX
#define RT_USING_MESSAGEQUEUE
#define RT_USING_MESSAGEQUEUE_PRIORITY
/* Memory Management */
#define RT_PAGE_MAX_ORDER 11
#define RT_USING_MEMPOOL
#define RT_USING_SMALL_MEM
#define RT_USING_SLAB
#define RT_USING_MEMHEAP
#define RT_MEMHEAP_FAST_MODE
#define RT_USING_SMALL_MEM_AS_HEAP
#define RT_USING_SLAB_AS_HEAP
#define RT_USING_HEAP_ISR
#define RT_USING_HEAP
/* Kernel Device Object */
@ -55,6 +59,9 @@
#define RT_CONSOLEBUF_SIZE 256
#define RT_CONSOLE_DEVICE_NAME "uart1"
#define RT_VER_NUM 0x50001
/* RT-Thread Architecture */
#define RT_USING_CACHE
#define RT_USING_HW_ATOMIC
#define RT_USING_CPU_FFS
@ -93,8 +100,24 @@
#define RT_USING_DFS_V1
#define DFS_FILESYSTEMS_MAX 4
#define DFS_FILESYSTEM_TYPES_MAX 4
#define RT_USING_DFS_ELMFAT
/* elm-chan's FatFs, Generic FAT Filesystem Module */
#define RT_DFS_ELM_CODE_PAGE 437
#define RT_DFS_ELM_WORD_ACCESS
#define RT_DFS_ELM_USE_LFN_3
#define RT_DFS_ELM_USE_LFN 3
#define RT_DFS_ELM_LFN_UNICODE_0
#define RT_DFS_ELM_LFN_UNICODE 0
#define RT_DFS_ELM_MAX_LFN 255
#define RT_DFS_ELM_DRIVES 2
#define RT_DFS_ELM_MAX_SECTOR_SIZE 512
#define RT_DFS_ELM_REENTRANT
#define RT_DFS_ELM_MUTEX_TIMEOUT 3000
#define RT_USING_DFS_DEVFS
#define RT_USING_DFS_RAMFS
#define RT_USING_DFS_MQUEUE
/* Device Drivers */
@ -111,6 +134,13 @@
#define RT_USING_ZERO
#define RT_USING_RANDOM
#define RT_USING_RTC
#define RT_USING_SDIO
#define RT_SDIO_STACK_SIZE 4096
#define RT_SDIO_THREAD_PRIORITY 15
#define RT_MMCSD_STACK_SIZE 4096
#define RT_MMCSD_THREAD_PREORITY 22
#define RT_MMCSD_MAX_PARTITION 16
#define RT_USING_DEV_BUS
/* Using USB */
@ -144,6 +174,59 @@
/* Network */
#define RT_USING_SAL
#define SAL_INTERNET_CHECK
/* Docking with protocol stacks */
#define SAL_USING_LWIP
#define SAL_USING_POSIX
#define RT_USING_NETDEV
#define NETDEV_USING_IFCONFIG
#define NETDEV_USING_PING
#define NETDEV_USING_NETSTAT
#define NETDEV_USING_AUTO_DEFAULT
#define NETDEV_IPV4 1
#define NETDEV_IPV6 0
#define RT_USING_LWIP
#define RT_USING_LWIP212
#define RT_USING_LWIP_VER_NUM 0x20102
#define RT_LWIP_MEM_ALIGNMENT 64
#define RT_LWIP_IGMP
#define RT_LWIP_ICMP
#define RT_LWIP_DNS
/* Static IPv4 Address */
#define RT_LWIP_IPADDR "192.168.4.10"
#define RT_LWIP_GWADDR "192.168.4.1"
#define RT_LWIP_MSKADDR "255.255.255.0"
#define RT_LWIP_UDP
#define RT_LWIP_TCP
#define RT_LWIP_RAW
#define RT_MEMP_NUM_NETCONN 8
#define RT_LWIP_PBUF_NUM 512
#define RT_LWIP_RAW_PCB_NUM 4
#define RT_LWIP_UDP_PCB_NUM 4
#define RT_LWIP_TCP_PCB_NUM 4
#define RT_LWIP_TCP_SEG_NUM 40
#define RT_LWIP_TCP_SND_BUF 8196
#define RT_LWIP_TCP_WND 8196
#define RT_LWIP_TCPTHREAD_PRIORITY 12
#define RT_LWIP_TCPTHREAD_MBOX_SIZE 8
#define RT_LWIP_TCPTHREAD_STACKSIZE 16184
#define RT_LWIP_ETHTHREAD_PRIORITY 12
#define RT_LWIP_ETHTHREAD_STACKSIZE 2048
#define RT_LWIP_ETHTHREAD_MBOX_SIZE 8
#define LWIP_NETIF_STATUS_CALLBACK 1
#define LWIP_NETIF_LINK_CALLBACK 1
#define SO_REUSE 1
#define LWIP_SO_RCVTIMEO 1
#define LWIP_SO_SNDTIMEO 1
#define LWIP_SO_RCVBUF 1
#define LWIP_SO_LINGER 0
#define LWIP_NETIF_LOOPBACK 0
#define RT_LWIP_USING_PING
/* Utilities */
@ -152,7 +235,13 @@
#define RT_USING_UTEST
#define UTEST_THR_STACK_SIZE 4096
#define UTEST_THR_PRIORITY 20
#define RT_USING_RESOURCE_ID
#define RT_USING_ADT
#define RT_USING_ADT_AVL
#define RT_USING_ADT_BITMAP
#define RT_USING_ADT_HASHMAP
#define RT_USING_ADT_REF
#define RT_USING_KTIME
/* RT-Thread Utestcases */
@ -276,6 +365,11 @@
#define BSP_USING_UART
#define RT_USING_UART1
#define BSP_USING_ETH
#define RT_LWIP_PBUF_POOL_BUFSIZE 1700
#define BSP_USING_SDIO
#define BSP_USING_SDCARD_FATFS
#define USING_SDIO1
/* Board extended module Drivers */
@ -296,11 +390,22 @@
#define USE_GIC
#define ENABLE_GICV3
#define USE_IOPAD
#define ENABLE_IOPAD
#define USE_SERIAL
/* Usart Configuration */
#define ENABLE_Pl011_UART
#define USE_ETH
/* Eth Configuration */
#define ENABLE_FXMAC
#define FXMAC_PHY_COMMON
/* Sdk common configuration */
#define LOG_ERROR
#define USE_DEFAULT_INTERRUPT_CONFIG
#define INTERRUPT_ROLE_MASTER

1344
bsp/phytium/aarch32/configs/e2000d_rtthread_test Normal file
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File diff suppressed because it is too large Load Diff

447
bsp/phytium/aarch32/configs/e2000d_rtthread_test.h Normal file
View File

@ -0,0 +1,447 @@
#ifndef RT_CONFIG_H__
#define RT_CONFIG_H__
/* Automatically generated file; DO NOT EDIT. */
/* RT-Thread Project Configuration */
/* RT-Thread Kernel */
#define RT_NAME_MAX 16
#define RT_USING_SMP
#define RT_CPUS_NR 2
#define RT_ALIGN_SIZE 4
#define RT_THREAD_PRIORITY_32
#define RT_THREAD_PRIORITY_MAX 32
#define RT_TICK_PER_SECOND 1000
#define RT_USING_OVERFLOW_CHECK
#define RT_USING_HOOK
#define RT_HOOK_USING_FUNC_PTR
#define RT_USING_IDLE_HOOK
#define RT_IDLE_HOOK_LIST_SIZE 4
#define IDLE_THREAD_STACK_SIZE 4096
#define SYSTEM_THREAD_STACK_SIZE 4096
#define RT_USING_TIMER_SOFT
#define RT_TIMER_THREAD_PRIO 4
#define RT_TIMER_THREAD_STACK_SIZE 4096
/* kservice optimization */
#define RT_KSERVICE_USING_STDLIB
#define RT_KPRINTF_USING_LONGLONG
#define RT_DEBUG
/* Inter-Thread communication */
#define RT_USING_SEMAPHORE
#define RT_USING_MUTEX
#define RT_USING_EVENT
#define RT_USING_MAILBOX
#define RT_USING_MESSAGEQUEUE
/* Memory Management */
#define RT_PAGE_MAX_ORDER 11
#define RT_USING_SLAB
#define RT_USING_MEMHEAP
#define RT_MEMHEAP_FAST_MODE
#define RT_USING_SLAB_AS_HEAP
#define RT_USING_HEAP_ISR
#define RT_USING_HEAP
/* Kernel Device Object */
#define RT_USING_DEVICE
#define RT_USING_CONSOLE
#define RT_CONSOLEBUF_SIZE 256
#define RT_CONSOLE_DEVICE_NAME "uart1"
#define RT_VER_NUM 0x50001
#define RT_USING_CACHE
#define RT_USING_HW_ATOMIC
#define RT_USING_CPU_FFS
#define ARCH_MM_MMU
#define ARCH_ARM
#define ARCH_ARM_MMU
#define ARCH_ARM_CORTEX_A
#define RT_USING_GIC_V3
/* RT-Thread Components */
#define RT_USING_COMPONENTS_INIT
#define RT_USING_USER_MAIN
#define RT_MAIN_THREAD_STACK_SIZE 8192
#define RT_MAIN_THREAD_PRIORITY 10
#define RT_USING_MSH
#define RT_USING_FINSH
#define FINSH_USING_MSH
#define FINSH_THREAD_NAME "tshell"
#define FINSH_THREAD_PRIORITY 20
#define FINSH_THREAD_STACK_SIZE 4096
#define FINSH_USING_HISTORY
#define FINSH_HISTORY_LINES 5
#define FINSH_USING_SYMTAB
#define FINSH_CMD_SIZE 80
#define MSH_USING_BUILT_IN_COMMANDS
#define FINSH_USING_DESCRIPTION
#define FINSH_ARG_MAX 10
/* DFS: device virtual file system */
#define RT_USING_DFS
#define DFS_USING_POSIX
#define DFS_USING_WORKDIR
#define DFS_FD_MAX 16
#define RT_USING_DFS_V1
#define DFS_FILESYSTEMS_MAX 4
#define DFS_FILESYSTEM_TYPES_MAX 4
#define RT_USING_DFS_ELMFAT
/* elm-chan's FatFs, Generic FAT Filesystem Module */
#define RT_DFS_ELM_CODE_PAGE 437
#define RT_DFS_ELM_WORD_ACCESS
#define RT_DFS_ELM_USE_LFN_3
#define RT_DFS_ELM_USE_LFN 3
#define RT_DFS_ELM_LFN_UNICODE_0
#define RT_DFS_ELM_LFN_UNICODE 0
#define RT_DFS_ELM_MAX_LFN 255
#define RT_DFS_ELM_DRIVES 2
#define RT_DFS_ELM_MAX_SECTOR_SIZE 512
#define RT_DFS_ELM_REENTRANT
#define RT_DFS_ELM_MUTEX_TIMEOUT 3000
#define RT_USING_DFS_DEVFS
#define RT_USING_DFS_RAMFS
/* Device Drivers */
#define RT_USING_DEVICE_IPC
#define RT_UNAMED_PIPE_NUMBER 64
#define RT_USING_SYSTEM_WORKQUEUE
#define RT_SYSTEM_WORKQUEUE_STACKSIZE 4096
#define RT_SYSTEM_WORKQUEUE_PRIORITY 23
#define RT_USING_SERIAL
#define RT_USING_SERIAL_V1
#define RT_SERIAL_USING_DMA
#define RT_SERIAL_RB_BUFSZ 1024
#define RT_USING_NULL
#define RT_USING_ZERO
#define RT_USING_RANDOM
#define RT_USING_RTC
#define RT_USING_SDIO
#define RT_SDIO_STACK_SIZE 4096
#define RT_SDIO_THREAD_PRIORITY 15
#define RT_MMCSD_STACK_SIZE 4096
#define RT_MMCSD_THREAD_PREORITY 22
#define RT_MMCSD_MAX_PARTITION 16
/* Using USB */
/* C/C++ and POSIX layer */
#define RT_LIBC_DEFAULT_TIMEZONE 8
/* POSIX (Portable Operating System Interface) layer */
#define RT_USING_POSIX_FS
#define RT_USING_POSIX_DEVIO
#define RT_USING_POSIX_STDIO
#define RT_USING_POSIX_POLL
#define RT_USING_POSIX_SELECT
#define RT_USING_POSIX_TERMIOS
#define RT_USING_POSIX_AIO
#define RT_USING_POSIX_DELAY
#define RT_USING_POSIX_CLOCK
#define RT_USING_POSIX_TIMER
/* Interprocess Communication (IPC) */
#define RT_USING_POSIX_PIPE
#define RT_USING_POSIX_PIPE_SIZE 512
#define RT_USING_POSIX_MESSAGE_QUEUE
#define RT_USING_POSIX_MESSAGE_SEMAPHORE
/* Socket is in the 'Network' category */
/* Network */
#define RT_USING_SAL
#define SAL_INTERNET_CHECK
/* Docking with protocol stacks */
#define SAL_USING_LWIP
#define SAL_USING_POSIX
#define RT_USING_NETDEV
#define NETDEV_USING_IFCONFIG
#define NETDEV_USING_PING
#define NETDEV_USING_NETSTAT
#define NETDEV_USING_AUTO_DEFAULT
#define NETDEV_IPV4 1
#define NETDEV_IPV6 0
#define RT_USING_LWIP
#define RT_USING_LWIP212
#define RT_USING_LWIP_VER_NUM 0x20102
#define RT_LWIP_MEM_ALIGNMENT 64
#define RT_LWIP_IGMP
#define RT_LWIP_ICMP
#define RT_LWIP_DNS
/* Static IPv4 Address */
#define RT_LWIP_IPADDR "192.168.4.10"
#define RT_LWIP_GWADDR "192.168.4.1"
#define RT_LWIP_MSKADDR "255.255.255.0"
#define RT_LWIP_UDP
#define RT_LWIP_TCP
#define RT_LWIP_RAW
#define RT_MEMP_NUM_NETCONN 8
#define RT_LWIP_PBUF_NUM 512
#define RT_LWIP_RAW_PCB_NUM 4
#define RT_LWIP_UDP_PCB_NUM 4
#define RT_LWIP_TCP_PCB_NUM 4
#define RT_LWIP_TCP_SEG_NUM 40
#define RT_LWIP_TCP_SND_BUF 8196
#define RT_LWIP_TCP_WND 8196
#define RT_LWIP_TCPTHREAD_PRIORITY 12
#define RT_LWIP_TCPTHREAD_MBOX_SIZE 8
#define RT_LWIP_TCPTHREAD_STACKSIZE 16184
#define RT_LWIP_ETHTHREAD_PRIORITY 12
#define RT_LWIP_ETHTHREAD_STACKSIZE 2048
#define RT_LWIP_ETHTHREAD_MBOX_SIZE 8
#define LWIP_NETIF_STATUS_CALLBACK 1
#define LWIP_NETIF_LINK_CALLBACK 1
#define SO_REUSE 1
#define LWIP_SO_RCVTIMEO 1
#define LWIP_SO_SNDTIMEO 1
#define LWIP_SO_RCVBUF 1
#define LWIP_SO_LINGER 0
#define LWIP_NETIF_LOOPBACK 0
#define RT_LWIP_USING_PING
/* Utilities */
#define RT_USING_RYM
#define YMODEM_USING_FILE_TRANSFER
#define RT_USING_UTEST
#define UTEST_THR_STACK_SIZE 4096
#define UTEST_THR_PRIORITY 20
#define RT_USING_ADT
/* RT-Thread Utestcases */
#define RT_USING_UTESTCASES
/* Utest Self Testcase */
#define UTEST_SELF_PASS_TC
/* Kernel Testcase */
#define UTEST_MEMHEAP_TC
#define UTEST_SLAB_TC
#define UTEST_IRQ_TC
#define UTEST_SEMAPHORE_TC
#define UTEST_EVENT_TC
#define UTEST_TIMER_TC
#define UTEST_MUTEX_TC
#define UTEST_MAILBOX_TC
#define UTEST_THREAD_TC
#define UTEST_ATOMIC_TC
/* CPP11 Testcase */
/* Utest Serial Testcase */
/* RTT Posix Testcase */
#define RTT_POSIX_TESTCASE
#define RTT_POSIX_TESTCASE_STDIO_H
#define RTT_POSIX_TESTCASE_STDLIB_H
#define RTT_POSIX_TESTCASE_UNISTD_H
/* Memory Management Subsytem Testcase */
/* RT-Thread online packages */
/* IoT - internet of things */
/* Wi-Fi */
/* Marvell WiFi */
/* Wiced WiFi */
/* IoT Cloud */
/* security packages */
/* language packages */
/* JSON: JavaScript Object Notation, a lightweight data-interchange format */
/* XML: Extensible Markup Language */
/* multimedia packages */
/* LVGL: powerful and easy-to-use embedded GUI library */
/* u8g2: a monochrome graphic library */
/* tools packages */
/* system packages */
/* enhanced kernel services */
/* acceleration: Assembly language or algorithmic acceleration packages */
/* CMSIS: ARM Cortex-M Microcontroller Software Interface Standard */
/* Micrium: Micrium software products porting for RT-Thread */
/* peripheral libraries and drivers */
/* sensors drivers */
/* touch drivers */
/* Kendryte SDK */
/* AI packages */
/* Signal Processing and Control Algorithm Packages */
/* miscellaneous packages */
/* project laboratory */
/* samples: kernel and components samples */
/* entertainment: terminal games and other interesting software packages */
/* Arduino libraries */
/* Projects */
/* Sensors */
/* Display */
/* Timing */
/* Data Processing */
/* Data Storage */
/* Communication */
/* Device Control */
/* Other */
/* Signal IO */
/* Uncategorized */
/* Hardware Drivers */
/* On-chip Peripheral Drivers */
#define BSP_USING_UART
#define RT_USING_UART1
#define BSP_USING_ETH
#define RT_LWIP_PBUF_POOL_BUFSIZE 1700
#define BSP_USING_SDIO
#define BSP_USING_SDCARD_FATFS
#define USING_SDIO1
/* Board extended module Drivers */
#define PHYTIUM_ARCH_AARCH32
/* Standalone Setting */
#define TARGET_ARMV8_AARCH32
#define USE_AARCH64_L1_TO_AARCH32
/* Board Configuration */
#define TARGET_E2000D
#define TARGET_E2000
#define DEFAULT_DEBUG_PRINT_UART1
/* Components Configuration */
#define USE_GIC
#define ENABLE_GICV3
#define USE_IOPAD
#define ENABLE_IOPAD
#define USE_SERIAL
/* Usart Configuration */
#define ENABLE_Pl011_UART
#define USE_ETH
/* Eth Configuration */
#define ENABLE_FXMAC
#define FXMAC_PHY_COMMON
/* Sdk common configuration */
#define LOG_ERROR
#define USE_DEFAULT_INTERRUPT_CONFIG
#define INTERRUPT_ROLE_MASTER
#define PHYTIUM_RTT_TEST
#define ENABLE_RTT_UTEST
/* RT-Thread Utestcases */
/* Kernel Testcase */
/* CPP11 Testcase */
/* Utest Serial Testcase */
/* RTT Posix Testcase */
/* Memory Management Subsytem Testcase */
#endif

125
bsp/phytium/aarch32/configs/e2000q_rtsmart
View File

@ -64,19 +64,19 @@ CONFIG_RT_USING_MESSAGEQUEUE=y
# Memory Management
#
CONFIG_RT_PAGE_MAX_ORDER=11
CONFIG_RT_USING_MEMPOOL=y
CONFIG_RT_USING_SMALL_MEM=y
# CONFIG_RT_USING_SLAB is not set
# CONFIG_RT_USING_MEMPOOL is not set
# CONFIG_RT_USING_SMALL_MEM is not set
CONFIG_RT_USING_SLAB=y
CONFIG_RT_USING_MEMHEAP=y
CONFIG_RT_MEMHEAP_FAST_MODE=y
# CONFIG_RT_MEMHEAP_BEST_MODE is not set
CONFIG_RT_USING_SMALL_MEM_AS_HEAP=y
# CONFIG_RT_USING_SMALL_MEM_AS_HEAP is not set
# CONFIG_RT_USING_MEMHEAP_AS_HEAP is not set
# CONFIG_RT_USING_SLAB_AS_HEAP is not set
CONFIG_RT_USING_SLAB_AS_HEAP=y
# CONFIG_RT_USING_USERHEAP is not set
# CONFIG_RT_USING_NOHEAP is not set
# CONFIG_RT_USING_MEMTRACE is not set
# CONFIG_RT_USING_HEAP_ISR is not set
CONFIG_RT_USING_HEAP_ISR=y
CONFIG_RT_USING_HEAP=y
#
@ -150,6 +150,7 @@ CONFIG_RT_USING_DFS_DEVFS=y
# CONFIG_RT_USING_DFS_CROMFS is not set
CONFIG_RT_USING_DFS_RAMFS=y
# CONFIG_RT_USING_DFS_TMPFS is not set
# CONFIG_RT_USING_DFS_NFS is not set
# CONFIG_RT_USING_FAL is not set
CONFIG_RT_USING_LWP=y
CONFIG_RT_LWP_MAX_NR=30
@ -255,9 +256,82 @@ CONFIG_RT_USING_POSIX_MESSAGE_SEMAPHORE=y
#
# Network
#
# CONFIG_RT_USING_SAL is not set
# CONFIG_RT_USING_NETDEV is not set
# CONFIG_RT_USING_LWIP is not set
CONFIG_RT_USING_SAL=y
CONFIG_SAL_INTERNET_CHECK=y
#
# Docking with protocol stacks
#
CONFIG_SAL_USING_LWIP=y
# CONFIG_SAL_USING_AT is not set
# CONFIG_SAL_USING_TLS is not set
CONFIG_SAL_USING_POSIX=y
# CONFIG_SAL_USING_AF_UNIX is not set
CONFIG_RT_USING_NETDEV=y
CONFIG_NETDEV_USING_IFCONFIG=y
CONFIG_NETDEV_USING_PING=y
CONFIG_NETDEV_USING_NETSTAT=y
CONFIG_NETDEV_USING_AUTO_DEFAULT=y
# CONFIG_NETDEV_USING_IPV6 is not set
CONFIG_NETDEV_IPV4=1
CONFIG_NETDEV_IPV6=0
# CONFIG_NETDEV_IPV6_SCOPES is not set
CONFIG_RT_USING_LWIP=y
# CONFIG_RT_USING_LWIP_LOCAL_VERSION is not set
# CONFIG_RT_USING_LWIP141 is not set
# CONFIG_RT_USING_LWIP203 is not set
CONFIG_RT_USING_LWIP212=y
# CONFIG_RT_USING_LWIP_LATEST is not set
CONFIG_RT_USING_LWIP_VER_NUM=0x20102
# CONFIG_RT_USING_LWIP_IPV6 is not set
CONFIG_RT_LWIP_MEM_ALIGNMENT=64
CONFIG_RT_LWIP_IGMP=y
CONFIG_RT_LWIP_ICMP=y
# CONFIG_RT_LWIP_SNMP is not set
CONFIG_RT_LWIP_DNS=y
# CONFIG_RT_LWIP_DHCP is not set
#
# Static IPv4 Address
#
CONFIG_RT_LWIP_IPADDR="192.168.4.10"
CONFIG_RT_LWIP_GWADDR="192.168.4.1"
CONFIG_RT_LWIP_MSKADDR="255.255.255.0"
CONFIG_RT_LWIP_UDP=y
CONFIG_RT_LWIP_TCP=y
CONFIG_RT_LWIP_RAW=y
# CONFIG_RT_LWIP_PPP is not set
CONFIG_RT_MEMP_NUM_NETCONN=8
CONFIG_RT_LWIP_PBUF_NUM=512
CONFIG_RT_LWIP_RAW_PCB_NUM=4
CONFIG_RT_LWIP_UDP_PCB_NUM=4
CONFIG_RT_LWIP_TCP_PCB_NUM=4
CONFIG_RT_LWIP_TCP_SEG_NUM=40
CONFIG_RT_LWIP_TCP_SND_BUF=8196
CONFIG_RT_LWIP_TCP_WND=8196
CONFIG_RT_LWIP_TCPTHREAD_PRIORITY=12
CONFIG_RT_LWIP_TCPTHREAD_MBOX_SIZE=8
CONFIG_RT_LWIP_TCPTHREAD_STACKSIZE=16184
# CONFIG_LWIP_NO_RX_THREAD is not set
# CONFIG_LWIP_NO_TX_THREAD is not set
CONFIG_RT_LWIP_ETHTHREAD_PRIORITY=12
CONFIG_RT_LWIP_ETHTHREAD_STACKSIZE=2048
CONFIG_RT_LWIP_ETHTHREAD_MBOX_SIZE=8
# CONFIG_RT_LWIP_REASSEMBLY_FRAG is not set
CONFIG_LWIP_NETIF_STATUS_CALLBACK=1
CONFIG_LWIP_NETIF_LINK_CALLBACK=1
CONFIG_SO_REUSE=1
CONFIG_LWIP_SO_RCVTIMEO=1
CONFIG_LWIP_SO_SNDTIMEO=1
CONFIG_LWIP_SO_RCVBUF=1
CONFIG_LWIP_SO_LINGER=0
# CONFIG_RT_LWIP_NETIF_LOOPBACK is not set
CONFIG_LWIP_NETIF_LOOPBACK=0
# CONFIG_RT_LWIP_STATS is not set
# CONFIG_RT_LWIP_USING_HW_CHECKSUM is not set
CONFIG_RT_LWIP_USING_PING=y
# CONFIG_LWIP_USING_DHCPD is not set
# CONFIG_RT_LWIP_DEBUG is not set
# CONFIG_RT_USING_AT is not set
#
@ -298,7 +372,6 @@ CONFIG_RT_USING_ADT=y
# CONFIG_PKG_USING_KAWAII_MQTT is not set
# CONFIG_PKG_USING_BC28_MQTT is not set
# CONFIG_PKG_USING_WEBTERMINAL is not set
# CONFIG_PKG_USING_LIBMODBUS is not set
# CONFIG_PKG_USING_FREEMODBUS is not set
# CONFIG_PKG_USING_NANOPB is not set
@ -570,6 +643,7 @@ CONFIG_RT_USING_ADT=y
# CONFIG_PKG_USING_QPC is not set
# CONFIG_PKG_USING_AGILE_UPGRADE is not set
# CONFIG_PKG_USING_FLASH_BLOB is not set
# CONFIG_PKG_USING_MLIBC is not set
#
# peripheral libraries and drivers
@ -654,6 +728,7 @@ CONFIG_RT_USING_ADT=y
# CONFIG_PKG_USING_FT5426 is not set
# CONFIG_PKG_USING_FT6236 is not set
# CONFIG_PKG_USING_XPT2046_TOUCH is not set
# CONFIG_PKG_USING_CST816X is not set
# CONFIG_PKG_USING_REALTEK_AMEBA is not set
# CONFIG_PKG_USING_STM32_SDIO is not set
# CONFIG_PKG_USING_ESP_IDF is not set
@ -729,7 +804,11 @@ CONFIG_RT_USING_ADT=y
# CONFIG_PKG_USING_IO_INPUT_FILTER is not set
# CONFIG_PKG_USING_RASPBERRYPI_PICO_SDK is not set
# CONFIG_PKG_USING_LRF_NV7LIDAR is not set
# CONFIG_PKG_USING_AIP650 is not set
# CONFIG_PKG_USING_FINGERPRINT is not set
# CONFIG_PKG_USING_BT_ECB02C is not set
# CONFIG_PKG_USING_UAT is not set
# CONFIG_PKG_USING_SPI_TOOLS is not set
#
# AI packages
@ -748,7 +827,10 @@ CONFIG_RT_USING_ADT=y
# Signal Processing and Control Algorithm Packages
#
# CONFIG_PKG_USING_FIRE_PID_CURVE is not set
# CONFIG_PKG_USING_QPID is not set
# CONFIG_PKG_USING_UKAL is not set
# CONFIG_PKG_USING_DIGITALCTRL is not set
# CONFIG_PKG_USING_KISSFFT is not set
#
# miscellaneous packages
@ -795,7 +877,6 @@ CONFIG_RT_USING_ADT=y
# CONFIG_PKG_USING_DSTR is not set
# CONFIG_PKG_USING_TINYFRAME is not set
# CONFIG_PKG_USING_KENDRYTE_DEMO is not set
# CONFIG_PKG_USING_DIGITALCTRL is not set
# CONFIG_PKG_USING_UPACKER is not set
# CONFIG_PKG_USING_UPARAM is not set
# CONFIG_PKG_USING_HELLO is not set
@ -820,8 +901,9 @@ CONFIG_RT_USING_ADT=y
# CONFIG_PKG_USING_RTDUINO is not set
#
# Projects
# Projects and Demos
#
# CONFIG_PKG_USING_ARDUINO_MSGQ_C_CPP_DEMO is not set
# CONFIG_PKG_USING_ARDUINO_ULTRASOUND_RADAR is not set
# CONFIG_PKG_USING_ARDUINO_SENSOR_KIT is not set
# CONFIG_PKG_USING_ARDUINO_MATLAB_SUPPORT is not set
@ -968,14 +1050,19 @@ CONFIG_RT_USING_ADT=y
#
# Display
#
# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_GFX_LIBRARY is not set
# CONFIG_PKG_USING_ARDUINO_U8G2 is not set
# CONFIG_PKG_USING_ARDUINO_U8GLIB_ARDUINO is not set
# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_ST7735 is not set
# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_SSD1306 is not set
# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_ILI9341 is not set
# CONFIG_PKG_USING_SEEED_TM1637 is not set
#
# Timing
#
# CONFIG_PKG_USING_ARDUINO_MSTIMER2 is not set
# CONFIG_PKG_USING_ARDUINO_TICKER is not set
# CONFIG_PKG_USING_ARDUINO_TASKSCHEDULER is not set
#
# Data Processing
@ -1040,6 +1127,8 @@ CONFIG_RT_USING_UART1=y
# CONFIG_BSP_USING_SPI is not set
# CONFIG_BSP_USING_CAN is not set
# CONFIG_BSP_USING_QSPI is not set
CONFIG_BSP_USING_ETH=y
CONFIG_RT_LWIP_PBUF_POOL_BUFSIZE=1700
#
# Board extended module Drivers
@ -1079,7 +1168,15 @@ CONFIG_USE_SERIAL=y
#
CONFIG_ENABLE_Pl011_UART=y
# CONFIG_USE_GPIO is not set
# CONFIG_USE_ETH is not set
CONFIG_USE_ETH=y
#
# Eth Configuration
#
CONFIG_ENABLE_FXMAC=y
# CONFIG_ENABLE_FGMAC is not set
CONFIG_FXMAC_PHY_COMMON=y
# CONFIG_FXMAC_PHY_YT is not set
# CONFIG_USE_CAN is not set
# CONFIG_USE_I2C is not set
# CONFIG_USE_TIMER is not set

71
bsp/phytium/aarch32/configs/e2000q_rtsmart.h
View File

@ -29,7 +29,7 @@
#define RT_KSERVICE_USING_STDLIB
#define RT_KPRINTF_USING_LONGLONG
#define RT_USING_DEBUG
#define RT_DEBUG
/* Inter-Thread communication */
@ -42,11 +42,11 @@
/* Memory Management */
#define RT_PAGE_MAX_ORDER 11
#define RT_USING_MEMPOOL
#define RT_USING_SMALL_MEM
#define RT_USING_SLAB
#define RT_USING_MEMHEAP
#define RT_MEMHEAP_FAST_MODE
#define RT_USING_SMALL_MEM_AS_HEAP
#define RT_USING_SLAB_AS_HEAP
#define RT_USING_HEAP_ISR
#define RT_USING_HEAP
/* Kernel Device Object */
@ -155,6 +155,59 @@
/* Network */
#define RT_USING_SAL
#define SAL_INTERNET_CHECK
/* Docking with protocol stacks */
#define SAL_USING_LWIP
#define SAL_USING_POSIX
#define RT_USING_NETDEV
#define NETDEV_USING_IFCONFIG
#define NETDEV_USING_PING
#define NETDEV_USING_NETSTAT
#define NETDEV_USING_AUTO_DEFAULT
#define NETDEV_IPV4 1
#define NETDEV_IPV6 0
#define RT_USING_LWIP
#define RT_USING_LWIP212
#define RT_USING_LWIP_VER_NUM 0x20102
#define RT_LWIP_MEM_ALIGNMENT 64
#define RT_LWIP_IGMP
#define RT_LWIP_ICMP
#define RT_LWIP_DNS
/* Static IPv4 Address */
#define RT_LWIP_IPADDR "192.168.4.10"
#define RT_LWIP_GWADDR "192.168.4.1"
#define RT_LWIP_MSKADDR "255.255.255.0"
#define RT_LWIP_UDP
#define RT_LWIP_TCP
#define RT_LWIP_RAW
#define RT_MEMP_NUM_NETCONN 8
#define RT_LWIP_PBUF_NUM 512
#define RT_LWIP_RAW_PCB_NUM 4
#define RT_LWIP_UDP_PCB_NUM 4
#define RT_LWIP_TCP_PCB_NUM 4
#define RT_LWIP_TCP_SEG_NUM 40
#define RT_LWIP_TCP_SND_BUF 8196
#define RT_LWIP_TCP_WND 8196
#define RT_LWIP_TCPTHREAD_PRIORITY 12
#define RT_LWIP_TCPTHREAD_MBOX_SIZE 8
#define RT_LWIP_TCPTHREAD_STACKSIZE 16184
#define RT_LWIP_ETHTHREAD_PRIORITY 12
#define RT_LWIP_ETHTHREAD_STACKSIZE 2048
#define RT_LWIP_ETHTHREAD_MBOX_SIZE 8
#define LWIP_NETIF_STATUS_CALLBACK 1
#define LWIP_NETIF_LINK_CALLBACK 1
#define SO_REUSE 1
#define LWIP_SO_RCVTIMEO 1
#define LWIP_SO_SNDTIMEO 1
#define LWIP_SO_RCVBUF 1
#define LWIP_SO_LINGER 0
#define LWIP_NETIF_LOOPBACK 0
#define RT_LWIP_USING_PING
/* Utilities */
@ -250,7 +303,7 @@
/* Arduino libraries */
/* Projects */
/* Projects and Demos */
/* Sensors */
@ -287,6 +340,8 @@
#define BSP_USING_UART
#define RT_USING_UART1
#define BSP_USING_ETH
#define RT_LWIP_PBUF_POOL_BUFSIZE 1700
/* Board extended module Drivers */
@ -312,6 +367,12 @@
/* Usart Configuration */
#define ENABLE_Pl011_UART
#define USE_ETH
/* Eth Configuration */
#define ENABLE_FXMAC
#define FXMAC_PHY_COMMON
#define LOG_ERROR
#define USE_DEFAULT_INTERRUPT_CONFIG
#define INTERRUPT_ROLE_MASTER

125
bsp/phytium/aarch32/configs/e2000q_rtthread
View File

@ -64,19 +64,19 @@ CONFIG_RT_USING_MESSAGEQUEUE=y
# Memory Management
#
CONFIG_RT_PAGE_MAX_ORDER=11
CONFIG_RT_USING_MEMPOOL=y
CONFIG_RT_USING_SMALL_MEM=y
# CONFIG_RT_USING_SLAB is not set
# CONFIG_RT_USING_MEMPOOL is not set
# CONFIG_RT_USING_SMALL_MEM is not set
CONFIG_RT_USING_SLAB=y
CONFIG_RT_USING_MEMHEAP=y
CONFIG_RT_MEMHEAP_FAST_MODE=y
# CONFIG_RT_MEMHEAP_BEST_MODE is not set
CONFIG_RT_USING_SMALL_MEM_AS_HEAP=y
# CONFIG_RT_USING_SMALL_MEM_AS_HEAP is not set
# CONFIG_RT_USING_MEMHEAP_AS_HEAP is not set
# CONFIG_RT_USING_SLAB_AS_HEAP is not set
CONFIG_RT_USING_SLAB_AS_HEAP=y
# CONFIG_RT_USING_USERHEAP is not set
# CONFIG_RT_USING_NOHEAP is not set
# CONFIG_RT_USING_MEMTRACE is not set
# CONFIG_RT_USING_HEAP_ISR is not set
CONFIG_RT_USING_HEAP_ISR=y
CONFIG_RT_USING_HEAP=y
#
@ -148,6 +148,7 @@ CONFIG_RT_USING_DFS_DEVFS=y
# CONFIG_RT_USING_DFS_CROMFS is not set
CONFIG_RT_USING_DFS_RAMFS=y
# CONFIG_RT_USING_DFS_TMPFS is not set
# CONFIG_RT_USING_DFS_NFS is not set
# CONFIG_RT_USING_FAL is not set
#
@ -242,9 +243,82 @@ CONFIG_RT_USING_POSIX_MESSAGE_SEMAPHORE=y
#
# Network
#
# CONFIG_RT_USING_SAL is not set
# CONFIG_RT_USING_NETDEV is not set
# CONFIG_RT_USING_LWIP is not set
CONFIG_RT_USING_SAL=y
CONFIG_SAL_INTERNET_CHECK=y
#
# Docking with protocol stacks
#
CONFIG_SAL_USING_LWIP=y
# CONFIG_SAL_USING_AT is not set
# CONFIG_SAL_USING_TLS is not set
CONFIG_SAL_USING_POSIX=y
# CONFIG_SAL_USING_AF_UNIX is not set
CONFIG_RT_USING_NETDEV=y
CONFIG_NETDEV_USING_IFCONFIG=y
CONFIG_NETDEV_USING_PING=y
CONFIG_NETDEV_USING_NETSTAT=y
CONFIG_NETDEV_USING_AUTO_DEFAULT=y
# CONFIG_NETDEV_USING_IPV6 is not set
CONFIG_NETDEV_IPV4=1
CONFIG_NETDEV_IPV6=0
# CONFIG_NETDEV_IPV6_SCOPES is not set
CONFIG_RT_USING_LWIP=y
# CONFIG_RT_USING_LWIP_LOCAL_VERSION is not set
# CONFIG_RT_USING_LWIP141 is not set
# CONFIG_RT_USING_LWIP203 is not set
CONFIG_RT_USING_LWIP212=y
# CONFIG_RT_USING_LWIP_LATEST is not set
CONFIG_RT_USING_LWIP_VER_NUM=0x20102
# CONFIG_RT_USING_LWIP_IPV6 is not set
CONFIG_RT_LWIP_MEM_ALIGNMENT=64
CONFIG_RT_LWIP_IGMP=y
CONFIG_RT_LWIP_ICMP=y
# CONFIG_RT_LWIP_SNMP is not set
CONFIG_RT_LWIP_DNS=y
# CONFIG_RT_LWIP_DHCP is not set
#
# Static IPv4 Address
#
CONFIG_RT_LWIP_IPADDR="192.168.4.10"
CONFIG_RT_LWIP_GWADDR="192.168.4.1"
CONFIG_RT_LWIP_MSKADDR="255.255.255.0"
CONFIG_RT_LWIP_UDP=y
CONFIG_RT_LWIP_TCP=y
CONFIG_RT_LWIP_RAW=y
# CONFIG_RT_LWIP_PPP is not set
CONFIG_RT_MEMP_NUM_NETCONN=8
CONFIG_RT_LWIP_PBUF_NUM=512
CONFIG_RT_LWIP_RAW_PCB_NUM=4
CONFIG_RT_LWIP_UDP_PCB_NUM=4
CONFIG_RT_LWIP_TCP_PCB_NUM=4
CONFIG_RT_LWIP_TCP_SEG_NUM=40
CONFIG_RT_LWIP_TCP_SND_BUF=8196
CONFIG_RT_LWIP_TCP_WND=8196
CONFIG_RT_LWIP_TCPTHREAD_PRIORITY=12
CONFIG_RT_LWIP_TCPTHREAD_MBOX_SIZE=8
CONFIG_RT_LWIP_TCPTHREAD_STACKSIZE=16184
# CONFIG_LWIP_NO_RX_THREAD is not set
# CONFIG_LWIP_NO_TX_THREAD is not set
CONFIG_RT_LWIP_ETHTHREAD_PRIORITY=12
CONFIG_RT_LWIP_ETHTHREAD_STACKSIZE=2048
CONFIG_RT_LWIP_ETHTHREAD_MBOX_SIZE=8
# CONFIG_RT_LWIP_REASSEMBLY_FRAG is not set
CONFIG_LWIP_NETIF_STATUS_CALLBACK=1
CONFIG_LWIP_NETIF_LINK_CALLBACK=1
CONFIG_SO_REUSE=1
CONFIG_LWIP_SO_RCVTIMEO=1
CONFIG_LWIP_SO_SNDTIMEO=1
CONFIG_LWIP_SO_RCVBUF=1
CONFIG_LWIP_SO_LINGER=0
# CONFIG_RT_LWIP_NETIF_LOOPBACK is not set
CONFIG_LWIP_NETIF_LOOPBACK=0
# CONFIG_RT_LWIP_STATS is not set
# CONFIG_RT_LWIP_USING_HW_CHECKSUM is not set
CONFIG_RT_LWIP_USING_PING=y
# CONFIG_LWIP_USING_DHCPD is not set
# CONFIG_RT_LWIP_DEBUG is not set
# CONFIG_RT_USING_AT is not set
#
@ -285,7 +359,6 @@ CONFIG_RT_USING_ADT=y
# CONFIG_PKG_USING_KAWAII_MQTT is not set
# CONFIG_PKG_USING_BC28_MQTT is not set
# CONFIG_PKG_USING_WEBTERMINAL is not set
# CONFIG_PKG_USING_LIBMODBUS is not set
# CONFIG_PKG_USING_FREEMODBUS is not set
# CONFIG_PKG_USING_NANOPB is not set
@ -557,6 +630,7 @@ CONFIG_RT_USING_ADT=y
# CONFIG_PKG_USING_QPC is not set
# CONFIG_PKG_USING_AGILE_UPGRADE is not set
# CONFIG_PKG_USING_FLASH_BLOB is not set
# CONFIG_PKG_USING_MLIBC is not set
#
# peripheral libraries and drivers
@ -641,6 +715,7 @@ CONFIG_RT_USING_ADT=y
# CONFIG_PKG_USING_FT5426 is not set
# CONFIG_PKG_USING_FT6236 is not set
# CONFIG_PKG_USING_XPT2046_TOUCH is not set
# CONFIG_PKG_USING_CST816X is not set
# CONFIG_PKG_USING_REALTEK_AMEBA is not set
# CONFIG_PKG_USING_STM32_SDIO is not set
# CONFIG_PKG_USING_ESP_IDF is not set
@ -716,7 +791,11 @@ CONFIG_RT_USING_ADT=y
# CONFIG_PKG_USING_IO_INPUT_FILTER is not set
# CONFIG_PKG_USING_RASPBERRYPI_PICO_SDK is not set
# CONFIG_PKG_USING_LRF_NV7LIDAR is not set
# CONFIG_PKG_USING_AIP650 is not set
# CONFIG_PKG_USING_FINGERPRINT is not set
# CONFIG_PKG_USING_BT_ECB02C is not set
# CONFIG_PKG_USING_UAT is not set
# CONFIG_PKG_USING_SPI_TOOLS is not set
#
# AI packages
@ -735,7 +814,10 @@ CONFIG_RT_USING_ADT=y
# Signal Processing and Control Algorithm Packages
#
# CONFIG_PKG_USING_FIRE_PID_CURVE is not set
# CONFIG_PKG_USING_QPID is not set
# CONFIG_PKG_USING_UKAL is not set
# CONFIG_PKG_USING_DIGITALCTRL is not set
# CONFIG_PKG_USING_KISSFFT is not set
#
# miscellaneous packages
@ -782,7 +864,6 @@ CONFIG_RT_USING_ADT=y
# CONFIG_PKG_USING_DSTR is not set
# CONFIG_PKG_USING_TINYFRAME is not set
# CONFIG_PKG_USING_KENDRYTE_DEMO is not set
# CONFIG_PKG_USING_DIGITALCTRL is not set
# CONFIG_PKG_USING_UPACKER is not set
# CONFIG_PKG_USING_UPARAM is not set
# CONFIG_PKG_USING_HELLO is not set
@ -807,8 +888,9 @@ CONFIG_RT_USING_ADT=y
# CONFIG_PKG_USING_RTDUINO is not set
#
# Projects
# Projects and Demos
#
# CONFIG_PKG_USING_ARDUINO_MSGQ_C_CPP_DEMO is not set
# CONFIG_PKG_USING_ARDUINO_ULTRASOUND_RADAR is not set
# CONFIG_PKG_USING_ARDUINO_SENSOR_KIT is not set
# CONFIG_PKG_USING_ARDUINO_MATLAB_SUPPORT is not set
@ -955,14 +1037,19 @@ CONFIG_RT_USING_ADT=y
#
# Display
#
# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_GFX_LIBRARY is not set
# CONFIG_PKG_USING_ARDUINO_U8G2 is not set
# CONFIG_PKG_USING_ARDUINO_U8GLIB_ARDUINO is not set
# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_ST7735 is not set
# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_SSD1306 is not set
# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_ILI9341 is not set
# CONFIG_PKG_USING_SEEED_TM1637 is not set
#
# Timing
#
# CONFIG_PKG_USING_ARDUINO_MSTIMER2 is not set
# CONFIG_PKG_USING_ARDUINO_TICKER is not set
# CONFIG_PKG_USING_ARDUINO_TASKSCHEDULER is not set
#
# Data Processing
@ -1027,6 +1114,8 @@ CONFIG_RT_USING_UART1=y
# CONFIG_BSP_USING_SPI is not set
# CONFIG_BSP_USING_CAN is not set
# CONFIG_BSP_USING_QSPI is not set
CONFIG_BSP_USING_ETH=y
CONFIG_RT_LWIP_PBUF_POOL_BUFSIZE=1700
#
# Board extended module Drivers
@ -1066,7 +1155,15 @@ CONFIG_USE_SERIAL=y
#
CONFIG_ENABLE_Pl011_UART=y
# CONFIG_USE_GPIO is not set
# CONFIG_USE_ETH is not set
CONFIG_USE_ETH=y
#
# Eth Configuration
#
CONFIG_ENABLE_FXMAC=y
# CONFIG_ENABLE_FGMAC is not set
CONFIG_FXMAC_PHY_COMMON=y
# CONFIG_FXMAC_PHY_YT is not set
# CONFIG_USE_CAN is not set
# CONFIG_USE_I2C is not set
# CONFIG_USE_TIMER is not set

71
bsp/phytium/aarch32/configs/e2000q_rtthread.h
View File

@ -28,7 +28,7 @@
#define RT_KSERVICE_USING_STDLIB
#define RT_KPRINTF_USING_LONGLONG
#define RT_USING_DEBUG
#define RT_DEBUG
/* Inter-Thread communication */
@ -41,11 +41,11 @@
/* Memory Management */
#define RT_PAGE_MAX_ORDER 11
#define RT_USING_MEMPOOL
#define RT_USING_SMALL_MEM
#define RT_USING_SLAB
#define RT_USING_MEMHEAP
#define RT_MEMHEAP_FAST_MODE
#define RT_USING_SMALL_MEM_AS_HEAP
#define RT_USING_SLAB_AS_HEAP
#define RT_USING_HEAP_ISR
#define RT_USING_HEAP
/* Kernel Device Object */
@ -144,6 +144,59 @@
/* Network */
#define RT_USING_SAL
#define SAL_INTERNET_CHECK
/* Docking with protocol stacks */
#define SAL_USING_LWIP
#define SAL_USING_POSIX
#define RT_USING_NETDEV
#define NETDEV_USING_IFCONFIG
#define NETDEV_USING_PING
#define NETDEV_USING_NETSTAT
#define NETDEV_USING_AUTO_DEFAULT
#define NETDEV_IPV4 1
#define NETDEV_IPV6 0
#define RT_USING_LWIP
#define RT_USING_LWIP212
#define RT_USING_LWIP_VER_NUM 0x20102
#define RT_LWIP_MEM_ALIGNMENT 64
#define RT_LWIP_IGMP
#define RT_LWIP_ICMP
#define RT_LWIP_DNS
/* Static IPv4 Address */
#define RT_LWIP_IPADDR "192.168.4.10"
#define RT_LWIP_GWADDR "192.168.4.1"
#define RT_LWIP_MSKADDR "255.255.255.0"
#define RT_LWIP_UDP
#define RT_LWIP_TCP
#define RT_LWIP_RAW
#define RT_MEMP_NUM_NETCONN 8
#define RT_LWIP_PBUF_NUM 512
#define RT_LWIP_RAW_PCB_NUM 4
#define RT_LWIP_UDP_PCB_NUM 4
#define RT_LWIP_TCP_PCB_NUM 4
#define RT_LWIP_TCP_SEG_NUM 40
#define RT_LWIP_TCP_SND_BUF 8196
#define RT_LWIP_TCP_WND 8196
#define RT_LWIP_TCPTHREAD_PRIORITY 12
#define RT_LWIP_TCPTHREAD_MBOX_SIZE 8
#define RT_LWIP_TCPTHREAD_STACKSIZE 16184
#define RT_LWIP_ETHTHREAD_PRIORITY 12
#define RT_LWIP_ETHTHREAD_STACKSIZE 2048
#define RT_LWIP_ETHTHREAD_MBOX_SIZE 8
#define LWIP_NETIF_STATUS_CALLBACK 1
#define LWIP_NETIF_LINK_CALLBACK 1
#define SO_REUSE 1
#define LWIP_SO_RCVTIMEO 1
#define LWIP_SO_SNDTIMEO 1
#define LWIP_SO_RCVBUF 1
#define LWIP_SO_LINGER 0
#define LWIP_NETIF_LOOPBACK 0
#define RT_LWIP_USING_PING
/* Utilities */
@ -239,7 +292,7 @@
/* Arduino libraries */
/* Projects */
/* Projects and Demos */
/* Sensors */
@ -276,6 +329,8 @@
#define BSP_USING_UART
#define RT_USING_UART1
#define BSP_USING_ETH
#define RT_LWIP_PBUF_POOL_BUFSIZE 1700
/* Board extended module Drivers */
@ -301,6 +356,12 @@
/* Usart Configuration */
#define ENABLE_Pl011_UART
#define USE_ETH
/* Eth Configuration */
#define ENABLE_FXMAC
#define FXMAC_PHY_COMMON
#define LOG_ERROR
#define USE_DEFAULT_INTERRUPT_CONFIG
#define INTERRUPT_ROLE_MASTER

28
bsp/phytium/aarch32/makefile
View File

@ -27,6 +27,10 @@ else
RTCONFIG := $(RTCONFIG)_rtthread
endif
ifdef CONFIG_PHYTIUM_RTT_TEST
RTCONFIG := $(RTCONFIG)_test
endif
boot:
make all
cp rtthread_a32.elf /mnt/d/tftboot
@ -59,20 +63,44 @@ load_e2000q_rtsmart:
@cp ./configs/e2000q_rtsmart.h ./rtconfig.h -f
@scons -c
load_e2000q_rtsmart_test:
@echo "Load configs from ./configs/e2000q_rtsmart_test"
@cp ./configs/e2000q_rtsmart_test ./.config -f
@cp ./configs/e2000q_rtsmart_test.h ./rtconfig.h -f
@scons -c
load_e2000q_rtthread:
@echo "Load configs from ./configs/e2000q_rtthread"
@cp ./configs/e2000q_rtthread ./.config -f
@cp ./configs/e2000q_rtthread.h ./rtconfig.h -f
@scons -c
load_e2000q_rtthread_test:
@echo "Load configs from ./configs/e2000q_rtthread_test"
@cp ./configs/e2000q_rtthread_test ./.config -f
@cp ./configs/e2000q_rtthread_test.h ./rtconfig.h -f
@scons -c
load_e2000d_rtsmart:
@echo "Load configs from ./configs/e2000d_rtsmart"
@cp ./configs/e2000d_rtsmart ./.config -f
@cp ./configs/e2000d_rtsmart.h ./rtconfig.h -f
@scons -c
load_e2000d_rtsmart_test:
@echo "Load configs from ./configs/e2000d_rtsmart_test"
@cp ./configs/e2000d_rtsmart_test ./.config -f
@cp ./configs/e2000d_rtsmart_test.h ./rtconfig.h -f
@scons -c
load_e2000d_rtthread:
@echo "Load configs from ./configs/e2000d_rtthread"
@cp ./configs/e2000d_rtthread ./.config -f
@cp ./configs/e2000d_rtthread.h ./rtconfig.h -f
scons -c
load_e2000d_rtthread_test:
@echo "Load configs from ./configs/e2000d_rtthread_test"
@cp ./configs/e2000d_rtthread_test ./.config -f
@cp ./configs/e2000d_rtthread_test.h ./rtconfig.h -f
scons -c

114
bsp/phytium/aarch32/rtconfig.h
View File

@ -29,7 +29,10 @@
#define RT_KSERVICE_USING_STDLIB
#define RT_KPRINTF_USING_LONGLONG
#define RT_DEBUG
#define RT_USING_DEBUG
#define RT_DEBUGING_COLOR
#define RT_DEBUGING_CONTEXT
#define RT_DEBUGING_INIT
/* Inter-Thread communication */
@ -38,15 +41,16 @@
#define RT_USING_EVENT
#define RT_USING_MAILBOX
#define RT_USING_MESSAGEQUEUE
#define RT_USING_MESSAGEQUEUE_PRIORITY
/* Memory Management */
#define RT_PAGE_MAX_ORDER 11
#define RT_USING_MEMPOOL
#define RT_USING_SMALL_MEM
#define RT_USING_SLAB
#define RT_USING_MEMHEAP
#define RT_MEMHEAP_FAST_MODE
#define RT_USING_SMALL_MEM_AS_HEAP
#define RT_USING_SLAB_AS_HEAP
#define RT_USING_HEAP_ISR
#define RT_USING_HEAP
/* Kernel Device Object */
@ -56,6 +60,9 @@
#define RT_CONSOLEBUF_SIZE 256
#define RT_CONSOLE_DEVICE_NAME "uart1"
#define RT_VER_NUM 0x50001
/* RT-Thread Architecture */
#define RT_USING_CACHE
#define RT_USING_HW_ATOMIC
#define RT_USING_CPU_FFS
@ -95,8 +102,24 @@
#define RT_USING_DFS_V1
#define DFS_FILESYSTEMS_MAX 4
#define DFS_FILESYSTEM_TYPES_MAX 4
#define RT_USING_DFS_ELMFAT
/* elm-chan's FatFs, Generic FAT Filesystem Module */
#define RT_DFS_ELM_CODE_PAGE 437
#define RT_DFS_ELM_WORD_ACCESS
#define RT_DFS_ELM_USE_LFN_3
#define RT_DFS_ELM_USE_LFN 3
#define RT_DFS_ELM_LFN_UNICODE_0
#define RT_DFS_ELM_LFN_UNICODE 0
#define RT_DFS_ELM_MAX_LFN 255
#define RT_DFS_ELM_DRIVES 2
#define RT_DFS_ELM_MAX_SECTOR_SIZE 512
#define RT_DFS_ELM_REENTRANT
#define RT_DFS_ELM_MUTEX_TIMEOUT 3000
#define RT_USING_DFS_DEVFS
#define RT_USING_DFS_RAMFS
#define RT_USING_DFS_MQUEUE
#define RT_USING_LWP
#define RT_LWP_MAX_NR 30
#define LWP_TASK_STACK_SIZE 16384
@ -122,6 +145,13 @@
#define RT_USING_ZERO
#define RT_USING_RANDOM
#define RT_USING_RTC
#define RT_USING_SDIO
#define RT_SDIO_STACK_SIZE 4096
#define RT_SDIO_THREAD_PRIORITY 15
#define RT_MMCSD_STACK_SIZE 4096
#define RT_MMCSD_THREAD_PREORITY 22
#define RT_MMCSD_MAX_PARTITION 16
#define RT_USING_DEV_BUS
/* Using USB */
@ -155,6 +185,59 @@
/* Network */
#define RT_USING_SAL
#define SAL_INTERNET_CHECK
/* Docking with protocol stacks */
#define SAL_USING_LWIP
#define SAL_USING_POSIX
#define RT_USING_NETDEV
#define NETDEV_USING_IFCONFIG
#define NETDEV_USING_PING
#define NETDEV_USING_NETSTAT
#define NETDEV_USING_AUTO_DEFAULT
#define NETDEV_IPV4 1
#define NETDEV_IPV6 0
#define RT_USING_LWIP
#define RT_USING_LWIP212
#define RT_USING_LWIP_VER_NUM 0x20102
#define RT_LWIP_MEM_ALIGNMENT 64
#define RT_LWIP_IGMP
#define RT_LWIP_ICMP
#define RT_LWIP_DNS
/* Static IPv4 Address */
#define RT_LWIP_IPADDR "192.168.4.10"
#define RT_LWIP_GWADDR "192.168.4.1"
#define RT_LWIP_MSKADDR "255.255.255.0"
#define RT_LWIP_UDP
#define RT_LWIP_TCP
#define RT_LWIP_RAW
#define RT_MEMP_NUM_NETCONN 8
#define RT_LWIP_PBUF_NUM 512
#define RT_LWIP_RAW_PCB_NUM 4
#define RT_LWIP_UDP_PCB_NUM 4
#define RT_LWIP_TCP_PCB_NUM 4
#define RT_LWIP_TCP_SEG_NUM 40
#define RT_LWIP_TCP_SND_BUF 8196
#define RT_LWIP_TCP_WND 8196
#define RT_LWIP_TCPTHREAD_PRIORITY 12
#define RT_LWIP_TCPTHREAD_MBOX_SIZE 8
#define RT_LWIP_TCPTHREAD_STACKSIZE 16184
#define RT_LWIP_ETHTHREAD_PRIORITY 12
#define RT_LWIP_ETHTHREAD_STACKSIZE 2048
#define RT_LWIP_ETHTHREAD_MBOX_SIZE 8
#define LWIP_NETIF_STATUS_CALLBACK 1
#define LWIP_NETIF_LINK_CALLBACK 1
#define SO_REUSE 1
#define LWIP_SO_RCVTIMEO 1
#define LWIP_SO_SNDTIMEO 1
#define LWIP_SO_RCVBUF 1
#define LWIP_SO_LINGER 0
#define LWIP_NETIF_LOOPBACK 0
#define RT_LWIP_USING_PING
/* Utilities */
@ -163,8 +246,13 @@
#define RT_USING_UTEST
#define UTEST_THR_STACK_SIZE 4096
#define UTEST_THR_PRIORITY 20
#define RT_USING_RESOURCE_ID
#define RT_USING_ADT
#define RT_USING_ADT_AVL
#define RT_USING_ADT_BITMAP
#define RT_USING_ADT_HASHMAP
#define RT_USING_ADT_REF
#define RT_USING_KTIME
/* RT-Thread Utestcases */
@ -251,7 +339,7 @@
/* Arduino libraries */
/* Projects */
/* Projects and Demos */
/* Sensors */
@ -288,6 +376,11 @@
#define BSP_USING_UART
#define RT_USING_UART1
#define BSP_USING_ETH
#define RT_LWIP_PBUF_POOL_BUFSIZE 1700
#define BSP_USING_SDIO
#define BSP_USING_SDCARD_FATFS
#define USING_SDIO1
/* Board extended module Drivers */
@ -308,11 +401,22 @@
#define USE_GIC
#define ENABLE_GICV3
#define USE_IOPAD
#define ENABLE_IOPAD
#define USE_SERIAL
/* Usart Configuration */
#define ENABLE_Pl011_UART
#define USE_ETH
/* Eth Configuration */
#define ENABLE_FXMAC
#define FXMAC_PHY_COMMON
/* Sdk common configuration */
#define LOG_ERROR
#define USE_DEFAULT_INTERRUPT_CONFIG
#define INTERRUPT_ROLE_MASTER

2
bsp/phytium/aarch32/rtconfig.py
View File

@ -16,6 +16,7 @@ if PLATFORM == 'gcc':
PREFIX = os.getenv('RTT_CC_PREFIX') or 'arm-none-eabi-'
CC = PREFIX + 'gcc'
CXX = PREFIX + 'g++'
CPP = PREFIX + 'cpp'
AS = PREFIX + 'gcc'
AR = PREFIX + 'ar'
LINK = PREFIX + 'gcc'
@ -28,6 +29,7 @@ if PLATFORM == 'gcc':
AFPFLAGS = ' -mfloat-abi=softfp -mfpu=neon'
DEVICE = ' -march=armv8-a -ftree-vectorize -ffast-math -funwind-tables -fno-strict-aliasing'
CPPFLAGS= ' -E -P -x assembler-with-cpp'
CXXFLAGS= DEVICE + CFPFLAGS + ' -Wall -fdiagnostics-color=always'
CFLAGS = DEVICE + CFPFLAGS + ' -Wall -Wno-cpp -std=gnu99 -D_POSIX_SOURCE -fdiagnostics-color=always'
AFLAGS = DEVICE + ' -c' + AFPFLAGS + ' -x assembler-with-cpp'

222
bsp/phytium/aarch64/.config
View File

@ -9,6 +9,7 @@
CONFIG_RT_NAME_MAX=16
# CONFIG_RT_USING_ARCH_DATA_TYPE is not set
# CONFIG_RT_USING_SMART is not set
# CONFIG_RT_USING_AMP is not set
CONFIG_RT_USING_SMP=y
CONFIG_RT_CPUS_NR=2
CONFIG_RT_ALIGN_SIZE=4
@ -22,11 +23,11 @@ CONFIG_RT_USING_HOOK=y
CONFIG_RT_HOOK_USING_FUNC_PTR=y
CONFIG_RT_USING_IDLE_HOOK=y
CONFIG_RT_IDLE_HOOK_LIST_SIZE=4
CONFIG_IDLE_THREAD_STACK_SIZE=40960
CONFIG_SYSTEM_THREAD_STACK_SIZE=40960
CONFIG_IDLE_THREAD_STACK_SIZE=8192
CONFIG_SYSTEM_THREAD_STACK_SIZE=8192
CONFIG_RT_USING_TIMER_SOFT=y
CONFIG_RT_TIMER_THREAD_PRIO=4
CONFIG_RT_TIMER_THREAD_STACK_SIZE=4096
CONFIG_RT_TIMER_THREAD_STACK_SIZE=8192
#
# kservice optimization
@ -36,19 +37,11 @@ CONFIG_RT_KSERVICE_USING_STDLIB=y
# CONFIG_RT_KSERVICE_USING_TINY_SIZE is not set
# CONFIG_RT_USING_TINY_FFS is not set
CONFIG_RT_KPRINTF_USING_LONGLONG=y
CONFIG_RT_DEBUG=y
# CONFIG_RT_DEBUG_COLOR is not set
# CONFIG_RT_DEBUG_INIT_CONFIG is not set
# CONFIG_RT_DEBUG_THREAD_CONFIG is not set
# CONFIG_RT_DEBUG_SCHEDULER_CONFIG is not set
# CONFIG_RT_DEBUG_IPC_CONFIG is not set
# CONFIG_RT_DEBUG_TIMER_CONFIG is not set
# CONFIG_RT_DEBUG_IRQ_CONFIG is not set
# CONFIG_RT_DEBUG_MEM_CONFIG is not set
# CONFIG_RT_DEBUG_SLAB_CONFIG is not set
# CONFIG_RT_DEBUG_MEMHEAP_CONFIG is not set
# CONFIG_RT_DEBUG_PAGE_LEAK is not set
# CONFIG_RT_DEBUG_MODULE_CONFIG is not set
CONFIG_RT_USING_DEBUG=y
CONFIG_RT_DEBUGING_COLOR=y
CONFIG_RT_DEBUGING_CONTEXT=y
CONFIG_RT_DEBUGING_INIT=y
# CONFIG_RT_DEBUGING_PAGE_LEAK is not set
#
# Inter-Thread communication
@ -58,25 +51,26 @@ CONFIG_RT_USING_MUTEX=y
CONFIG_RT_USING_EVENT=y
CONFIG_RT_USING_MAILBOX=y
CONFIG_RT_USING_MESSAGEQUEUE=y
# CONFIG_RT_USING_MESSAGEQUEUE_PRIORITY is not set
# CONFIG_RT_USING_SIGNALS is not set
#
# Memory Management
#
CONFIG_RT_PAGE_MAX_ORDER=11
CONFIG_RT_USING_MEMPOOL=y
CONFIG_RT_USING_SMALL_MEM=y
# CONFIG_RT_USING_SLAB is not set
CONFIG_RT_PAGE_MAX_ORDER=16
# CONFIG_RT_USING_MEMPOOL is not set
# CONFIG_RT_USING_SMALL_MEM is not set
CONFIG_RT_USING_SLAB=y
CONFIG_RT_USING_MEMHEAP=y
CONFIG_RT_MEMHEAP_FAST_MODE=y
# CONFIG_RT_MEMHEAP_BEST_MODE is not set
CONFIG_RT_USING_SMALL_MEM_AS_HEAP=y
# CONFIG_RT_USING_SMALL_MEM_AS_HEAP is not set
# CONFIG_RT_USING_MEMHEAP_AS_HEAP is not set
# CONFIG_RT_USING_SLAB_AS_HEAP is not set
CONFIG_RT_USING_SLAB_AS_HEAP=y
# CONFIG_RT_USING_USERHEAP is not set
# CONFIG_RT_USING_NOHEAP is not set
# CONFIG_RT_USING_MEMTRACE is not set
# CONFIG_RT_USING_HEAP_ISR is not set
CONFIG_RT_USING_HEAP_ISR=y
CONFIG_RT_USING_HEAP=y
#
@ -91,9 +85,13 @@ CONFIG_RT_CONSOLEBUF_SIZE=128
CONFIG_RT_CONSOLE_DEVICE_NAME="uart1"
CONFIG_RT_VER_NUM=0x50001
# CONFIG_RT_USING_STDC_ATOMIC is not set
#
# RT-Thread Architecture
#
CONFIG_ARCH_CPU_64BIT=y
CONFIG_RT_USING_CACHE=y
CONFIG_RT_USING_HW_ATOMIC=y
# CONFIG_RT_USING_HW_ATOMIC is not set
CONFIG_ARCH_ARM_BOOTWITH_FLUSH_CACHE=y
# CONFIG_ARCH_CPU_STACK_GROWS_UPWARD is not set
# CONFIG_RT_USING_CPU_FFS is not set
@ -101,6 +99,10 @@ CONFIG_ARCH_MM_MMU=y
CONFIG_ARCH_ARM=y
CONFIG_ARCH_ARM_MMU=y
CONFIG_ARCH_ARMV8=y
CONFIG_ARCH_TEXT_OFFSET=0x80000
CONFIG_ARCH_RAM_OFFSET=0x80000000
CONFIG_ARCH_SECONDARY_CPU_STACK_SIZE=4096
CONFIG_ARCH_HAVE_EFFICIENT_UNALIGNED_ACCESS=y
#
# RT-Thread Components
@ -138,12 +140,36 @@ CONFIG_RT_USING_DFS_V1=y
# CONFIG_RT_USING_DFS_V2 is not set
CONFIG_DFS_FILESYSTEMS_MAX=4
CONFIG_DFS_FILESYSTEM_TYPES_MAX=4
# CONFIG_RT_USING_DFS_ELMFAT is not set
CONFIG_RT_USING_DFS_ELMFAT=y
#
# elm-chan's FatFs, Generic FAT Filesystem Module
#
CONFIG_RT_DFS_ELM_CODE_PAGE=437
CONFIG_RT_DFS_ELM_WORD_ACCESS=y
# CONFIG_RT_DFS_ELM_USE_LFN_0 is not set
# CONFIG_RT_DFS_ELM_USE_LFN_1 is not set
# CONFIG_RT_DFS_ELM_USE_LFN_2 is not set
CONFIG_RT_DFS_ELM_USE_LFN_3=y
CONFIG_RT_DFS_ELM_USE_LFN=3
CONFIG_RT_DFS_ELM_LFN_UNICODE_0=y
# CONFIG_RT_DFS_ELM_LFN_UNICODE_1 is not set
# CONFIG_RT_DFS_ELM_LFN_UNICODE_2 is not set
# CONFIG_RT_DFS_ELM_LFN_UNICODE_3 is not set
CONFIG_RT_DFS_ELM_LFN_UNICODE=0
CONFIG_RT_DFS_ELM_MAX_LFN=255
CONFIG_RT_DFS_ELM_DRIVES=2
CONFIG_RT_DFS_ELM_MAX_SECTOR_SIZE=512
# CONFIG_RT_DFS_ELM_USE_ERASE is not set
CONFIG_RT_DFS_ELM_REENTRANT=y
CONFIG_RT_DFS_ELM_MUTEX_TIMEOUT=3000
CONFIG_RT_USING_DFS_DEVFS=y
# CONFIG_RT_USING_DFS_ROMFS is not set
# CONFIG_RT_USING_DFS_CROMFS is not set
CONFIG_RT_USING_DFS_RAMFS=y
# CONFIG_RT_USING_DFS_TMPFS is not set
# CONFIG_RT_USING_DFS_MQUEUE is not set
# CONFIG_RT_USING_DFS_NFS is not set
# CONFIG_RT_USING_FAL is not set
#
@ -178,7 +204,13 @@ CONFIG_RT_USING_RANDOM=y
CONFIG_RT_USING_RTC=y
# CONFIG_RT_USING_ALARM is not set
# CONFIG_RT_USING_SOFT_RTC is not set
# CONFIG_RT_USING_SDIO is not set
CONFIG_RT_USING_SDIO=y
CONFIG_RT_SDIO_STACK_SIZE=4096
CONFIG_RT_SDIO_THREAD_PRIORITY=15
CONFIG_RT_MMCSD_STACK_SIZE=4096
CONFIG_RT_MMCSD_THREAD_PREORITY=22
CONFIG_RT_MMCSD_MAX_PARTITION=16
# CONFIG_RT_SDIO_DEBUG is not set
# CONFIG_RT_USING_SPI is not set
# CONFIG_RT_USING_WDT is not set
# CONFIG_RT_USING_AUDIO is not set
@ -237,9 +269,110 @@ CONFIG_RT_USING_POSIX_TIMER=y
#
# Network
#
# CONFIG_RT_USING_SAL is not set
# CONFIG_RT_USING_NETDEV is not set
# CONFIG_RT_USING_LWIP is not set
CONFIG_RT_USING_SAL=y
CONFIG_SAL_INTERNET_CHECK=y
#
# Docking with protocol stacks
#
CONFIG_SAL_USING_LWIP=y
# CONFIG_SAL_USING_AT is not set
# CONFIG_SAL_USING_TLS is not set
CONFIG_SAL_USING_POSIX=y
# CONFIG_SAL_USING_AF_UNIX is not set
CONFIG_RT_USING_NETDEV=y
CONFIG_NETDEV_USING_IFCONFIG=y
CONFIG_NETDEV_USING_PING=y
CONFIG_NETDEV_USING_NETSTAT=y
CONFIG_NETDEV_USING_AUTO_DEFAULT=y
# CONFIG_NETDEV_USING_IPV6 is not set
CONFIG_NETDEV_IPV4=1
CONFIG_NETDEV_IPV6=0
# CONFIG_NETDEV_IPV6_SCOPES is not set
CONFIG_RT_USING_LWIP=y
# CONFIG_RT_USING_LWIP_LOCAL_VERSION is not set
# CONFIG_RT_USING_LWIP141 is not set
# CONFIG_RT_USING_LWIP203 is not set
CONFIG_RT_USING_LWIP212=y
# CONFIG_RT_USING_LWIP_LATEST is not set
CONFIG_RT_USING_LWIP_VER_NUM=0x20102
# CONFIG_RT_USING_LWIP_IPV6 is not set
CONFIG_RT_LWIP_MEM_ALIGNMENT=64
CONFIG_RT_LWIP_IGMP=y
CONFIG_RT_LWIP_ICMP=y
# CONFIG_RT_LWIP_SNMP is not set
CONFIG_RT_LWIP_DNS=y
# CONFIG_RT_LWIP_DHCP is not set
#
# Static IPv4 Address
#
CONFIG_RT_LWIP_IPADDR="192.168.4.10"
CONFIG_RT_LWIP_GWADDR="192.168.4.1"
CONFIG_RT_LWIP_MSKADDR="255.255.255.0"
CONFIG_RT_LWIP_UDP=y
CONFIG_RT_LWIP_TCP=y
CONFIG_RT_LWIP_RAW=y
# CONFIG_RT_LWIP_PPP is not set
CONFIG_RT_MEMP_NUM_NETCONN=8
CONFIG_RT_LWIP_PBUF_NUM=512
CONFIG_RT_LWIP_RAW_PCB_NUM=4
CONFIG_RT_LWIP_UDP_PCB_NUM=4
CONFIG_RT_LWIP_TCP_PCB_NUM=4
CONFIG_RT_LWIP_TCP_SEG_NUM=40
CONFIG_RT_LWIP_TCP_SND_BUF=8196
CONFIG_RT_LWIP_TCP_WND=8196
CONFIG_RT_LWIP_TCPTHREAD_PRIORITY=12
CONFIG_RT_LWIP_TCPTHREAD_MBOX_SIZE=8
CONFIG_RT_LWIP_TCPTHREAD_STACKSIZE=16184
# CONFIG_LWIP_NO_RX_THREAD is not set
# CONFIG_LWIP_NO_TX_THREAD is not set
CONFIG_RT_LWIP_ETHTHREAD_PRIORITY=12
CONFIG_RT_LWIP_ETHTHREAD_STACKSIZE=2048
CONFIG_RT_LWIP_ETHTHREAD_MBOX_SIZE=8
# CONFIG_RT_LWIP_REASSEMBLY_FRAG is not set
CONFIG_LWIP_NETIF_STATUS_CALLBACK=1
CONFIG_LWIP_NETIF_LINK_CALLBACK=1
CONFIG_SO_REUSE=1
CONFIG_LWIP_SO_RCVTIMEO=1
CONFIG_LWIP_SO_SNDTIMEO=1
CONFIG_LWIP_SO_RCVBUF=1
CONFIG_LWIP_SO_LINGER=0
# CONFIG_RT_LWIP_NETIF_LOOPBACK is not set
CONFIG_LWIP_NETIF_LOOPBACK=0
# CONFIG_RT_LWIP_STATS is not set
# CONFIG_RT_LWIP_USING_HW_CHECKSUM is not set
CONFIG_RT_LWIP_USING_PING=y
# CONFIG_LWIP_USING_DHCPD is not set
CONFIG_RT_LWIP_DEBUG=y
# CONFIG_RT_LWIP_SYS_DEBUG is not set
# CONFIG_RT_LWIP_ETHARP_DEBUG is not set
# CONFIG_RT_LWIP_PPP_DEBUG is not set
# CONFIG_RT_LWIP_MEM_DEBUG is not set
# CONFIG_RT_LWIP_MEMP_DEBUG is not set
# CONFIG_RT_LWIP_PBUF_DEBUG is not set
# CONFIG_RT_LWIP_API_LIB_DEBUG is not set
# CONFIG_RT_LWIP_API_MSG_DEBUG is not set
# CONFIG_RT_LWIP_TCPIP_DEBUG is not set
CONFIG_RT_LWIP_NETIF_DEBUG=y
# CONFIG_RT_LWIP_SOCKETS_DEBUG is not set
# CONFIG_RT_LWIP_DNS_DEBUG is not set
# CONFIG_RT_LWIP_AUTOIP_DEBUG is not set
# CONFIG_RT_LWIP_DHCP_DEBUG is not set
# CONFIG_RT_LWIP_IP_DEBUG is not set
# CONFIG_RT_LWIP_IP_REASS_DEBUG is not set
# CONFIG_RT_LWIP_ICMP_DEBUG is not set
# CONFIG_RT_LWIP_IGMP_DEBUG is not set
# CONFIG_RT_LWIP_UDP_DEBUG is not set
# CONFIG_RT_LWIP_TCP_DEBUG is not set
# CONFIG_RT_LWIP_TCP_INPUT_DEBUG is not set
# CONFIG_RT_LWIP_TCP_OUTPUT_DEBUG is not set
# CONFIG_RT_LWIP_TCP_RTO_DEBUG is not set
# CONFIG_RT_LWIP_TCP_CWND_DEBUG is not set
# CONFIG_RT_LWIP_TCP_WND_DEBUG is not set
# CONFIG_RT_LWIP_TCP_FR_DEBUG is not set
# CONFIG_RT_LWIP_TCP_QLEN_DEBUG is not set
# CONFIG_RT_LWIP_TCP_RST_DEBUG is not set
# CONFIG_RT_USING_AT is not set
#
@ -251,10 +384,15 @@ CONFIG_YMODEM_USING_FILE_TRANSFER=y
# CONFIG_RT_USING_ULOG is not set
# CONFIG_RT_USING_UTEST is not set
# CONFIG_RT_USING_VAR_EXPORT is not set
CONFIG_RT_USING_RESOURCE_ID=y
CONFIG_RT_USING_ADT=y
CONFIG_RT_USING_ADT_AVL=y
CONFIG_RT_USING_ADT_BITMAP=y
CONFIG_RT_USING_ADT_HASHMAP=y
CONFIG_RT_USING_ADT_REF=y
# CONFIG_RT_USING_RT_LINK is not set
# CONFIG_RT_USING_VBUS is not set
CONFIG_RT_USING_KTIME=y
#
# RT-Thread Utestcases
@ -1043,7 +1181,15 @@ CONFIG_RT_USING_UART1=y
# CONFIG_RT_USING_UART0 is not set
# CONFIG_BSP_USING_SPI is not set
# CONFIG_BSP_USING_CAN is not set
# CONFIG_BSP_USING_GPIO is not set
# CONFIG_BSP_USING_QSPI is not set
CONFIG_BSP_USING_ETH=y
CONFIG_RT_LWIP_PBUF_POOL_BUFSIZE=1700
CONFIG_BSP_USING_SDIO=y
CONFIG_BSP_USING_SDCARD_FATFS=y
# CONFIG_USING_SDIO0 is not set
CONFIG_USING_SDIO1=y
# CONFIG_USING_EMMC is not set
#
# Board extended module Drivers
@ -1083,6 +1229,8 @@ CONFIG_USE_QSPI=y
#
CONFIG_USE_FQSPI=y
# CONFIG_USE_GIC is not set
CONFIG_USE_IOPAD=y
CONFIG_ENABLE_IOPAD=y
CONFIG_USE_SERIAL=y
#
@ -1090,7 +1238,15 @@ CONFIG_USE_SERIAL=y
#
CONFIG_ENABLE_Pl011_UART=y
# CONFIG_USE_GPIO is not set
# CONFIG_USE_ETH is not set
CONFIG_USE_ETH=y
#
# Eth Configuration
#
CONFIG_ENABLE_FXMAC=y
# CONFIG_ENABLE_FGMAC is not set
CONFIG_FXMAC_PHY_COMMON=y
# CONFIG_FXMAC_PHY_YT is not set
# CONFIG_USE_CAN is not set
# CONFIG_USE_I2C is not set
# CONFIG_USE_TIMER is not set
@ -1108,13 +1264,17 @@ CONFIG_ENABLE_Pl011_UART=y
# CONFIG_USE_IPC is not set
# CONFIG_USE_MEDIA is not set
# CONFIG_USE_SCMI_MHU is not set
#
# Sdk common configuration
#
# CONFIG_LOG_VERBOS is not set
# CONFIG_LOG_DEBUG is not set
# CONFIG_LOG_INFO is not set
# CONFIG_LOG_WARN is not set
CONFIG_LOG_ERROR=y
# CONFIG_LOG_NONE is not set
# CONFIG_USE_DEFAULT_INTERRUPT_CONFIG is not set
# CONFIG_LOG_EXTRA_INFO is not set
# CONFIG_LOG_DISPALY_CORE_NUM is not set
# CONFIG_BOOTUP_DEBUG_PRINTS is not set
# CONFIG_USE_DEFAULT_INTERRUPT_CONFIG is not set

2
bsp/phytium/aarch64/Kconfig
View File

@ -65,5 +65,3 @@ menu "Standalone Setting"
endmenu

6
bsp/phytium/aarch64/README.md
View File

@ -114,6 +114,12 @@ rtthread_a64.map
- 可以用串口通过 XMODEM 协议将 bin/elf 文件上传到开发板，然后启动，
- 如果使用 SD-1 控制器
```
mw.l 0x32b31178 0x1f
```
- 首先在 Phytium 开发板上输入，上传 bin 文件
```

4
bsp/phytium/aarch64/SConstruct
View File

@ -53,10 +53,6 @@ if not IS_EXPORTED: # if project is not exported, libraries and board need to ma
# include board
objs.extend(SConscript(os.path.join(BSP_ROOT + '/board', 'SConscript')))
if GetDepend('RT_USING_SMART'):
# use smart link.lds
env['LINKFLAGS'] = env['LINKFLAGS'].replace('link.lds', 'link_smart.lds')
# make a building
DoBuilding(TARGET, objs)

98
bsp/phytium/aarch64/applications/mnt.c
View File

@ -8,56 +8,88 @@
* Change Logs:
* Date Author Notes
* 2023-04-27 huanghe first version
* 2023-07-14 liqiaozhong add SD file sys mount func
*
*/
#include <rtthread.h>
#ifdef RT_USING_DFS_RAMFS
#include <dfs_fs.h>
#if defined(RT_USING_DFS)
#include <rtdbg.h>
extern struct dfs_ramfs *dfs_ramfs_create(rt_uint8_t *pool, rt_size_t size);
int mnt_init(void)
{
rt_uint8_t *pool = RT_NULL;
rt_size_t size = 8*1024*1024;
pool = rt_malloc(size);
if (pool == RT_NULL)
return 0;
if (dfs_mount(RT_NULL, "/", "ram", 0, (const void *)dfs_ramfs_create(pool, size)) == 0)
rt_kprintf("RAM file system initializated!\n");
else
rt_kprintf("RAM file system initializate failed!\n");
return 0;
}
INIT_ENV_EXPORT(mnt_init);
#endif
#ifdef BSP_USING_SDCARD_FATFS
#include <dfs_fs.h>
#include <dfs_file.h>
#define DBG_TAG "app.filesystem"
#define DBG_LVL DBG_INFO
#include <rtdbg.h>
#ifdef BSP_USING_SDCARD_FATFS
#define SD_DEIVCE_NAME "sd"
static int filesystem_mount(void)
{
while(rt_device_find("sd0") == RT_NULL)
while (rt_device_find(SD_DEIVCE_NAME) == RT_NULL)
{
rt_thread_mdelay(1);
}
int ret = dfs_mount("sd0", "/", "elm", 0, 0);
if (ret != 0)
if (dfs_mount(SD_DEIVCE_NAME, "/", "elm", 0, 0) == 0)
{
rt_kprintf("ret: %d\n",ret);
LOG_E("sd0 mount to '/' failed!");
return ret;
LOG_I("file system initialization done!\n");
}
else
{
LOG_W("[sd] File System on SD initialization failed!");
LOG_W("[sd] Try to format and re-mount...");
if (dfs_mkfs("elm", SD_DEIVCE_NAME) == 0)
{
if (dfs_mount(SD_DEIVCE_NAME, "/", "elm", 0, 0) == 0)
{
LOG_I("[sd] File System on SD initialized!");
}
}
LOG_E("[sd] File System on SD initialization failed!");
return -1;
}
mkdir("/ram", 0x777);
#ifdef RT_USING_DFS_RAMFS
extern struct dfs_ramfs *dfs_ramfs_create(rt_uint8_t *pool, rt_size_t size);
rt_uint8_t *pool = RT_NULL;
rt_size_t size = 8 * 1024 * 1024;
pool = rt_malloc(size);
if (pool == RT_NULL)
LOG_E("Malloc fail!");
if (dfs_mount(RT_NULL, "/ram", "ram", 0, (const void *)dfs_ramfs_create(pool, size)) == 0)
LOG_I("RAM file system initializated!");
else
LOG_E("RAM file system initializate failed!");
#endif
return RT_EOK;
}
INIT_ENV_EXPORT(filesystem_mount);
#else
static int filesystem_mount(void)
{
#ifdef RT_USING_DFS_RAMFS
extern struct dfs_ramfs *dfs_ramfs_create(rt_uint8_t *pool, rt_size_t size);
rt_uint8_t *pool = RT_NULL;
rt_size_t size = 8 * 1024 * 1024;
pool = rt_malloc(size);
if (pool == RT_NULL)
LOG_E("Malloc fail!");
if (dfs_mount(RT_NULL, "/", "ram", 0, (const void *)dfs_ramfs_create(pool, size)) == 0)
LOG_I("RAM file system initializated!");
else
LOG_E("RAM file system initializate failed!");
#endif
return RT_EOK;
}
INIT_ENV_EXPORT(filesystem_mount);
#endif
#endif // #ifdef BSP_USING_SDCARD_FATFS
#endif // #if defined(RT_USING_DFS)

222
bsp/phytium/aarch64/configs/e2000d_rtsmart
View File

@ -9,6 +9,7 @@
CONFIG_RT_NAME_MAX=16
# CONFIG_RT_USING_ARCH_DATA_TYPE is not set
CONFIG_RT_USING_SMART=y
# CONFIG_RT_USING_AMP is not set
CONFIG_RT_USING_SMP=y
CONFIG_RT_CPUS_NR=2
CONFIG_RT_ALIGN_SIZE=4
@ -22,11 +23,11 @@ CONFIG_RT_USING_HOOK=y
CONFIG_RT_HOOK_USING_FUNC_PTR=y
CONFIG_RT_USING_IDLE_HOOK=y
CONFIG_RT_IDLE_HOOK_LIST_SIZE=4
CONFIG_IDLE_THREAD_STACK_SIZE=40960
CONFIG_SYSTEM_THREAD_STACK_SIZE=40960
CONFIG_IDLE_THREAD_STACK_SIZE=8192
CONFIG_SYSTEM_THREAD_STACK_SIZE=8192
CONFIG_RT_USING_TIMER_SOFT=y
CONFIG_RT_TIMER_THREAD_PRIO=4
CONFIG_RT_TIMER_THREAD_STACK_SIZE=4096
CONFIG_RT_TIMER_THREAD_STACK_SIZE=8192
#
# kservice optimization
@ -36,18 +37,11 @@ CONFIG_RT_KSERVICE_USING_STDLIB=y
# CONFIG_RT_KSERVICE_USING_TINY_SIZE is not set
# CONFIG_RT_USING_TINY_FFS is not set
CONFIG_RT_KPRINTF_USING_LONGLONG=y
CONFIG_RT_DEBUG=y
# CONFIG_RT_DEBUG_COLOR is not set
# CONFIG_RT_DEBUG_INIT_CONFIG is not set
# CONFIG_RT_DEBUG_THREAD_CONFIG is not set
# CONFIG_RT_DEBUG_SCHEDULER_CONFIG is not set
# CONFIG_RT_DEBUG_IPC_CONFIG is not set
# CONFIG_RT_DEBUG_TIMER_CONFIG is not set
# CONFIG_RT_DEBUG_IRQ_CONFIG is not set
# CONFIG_RT_DEBUG_MEM_CONFIG is not set
# CONFIG_RT_DEBUG_SLAB_CONFIG is not set
# CONFIG_RT_DEBUG_MEMHEAP_CONFIG is not set
# CONFIG_RT_DEBUG_MODULE_CONFIG is not set
CONFIG_RT_USING_DEBUG=y
CONFIG_RT_DEBUGING_COLOR=y
CONFIG_RT_DEBUGING_CONTEXT=y
CONFIG_RT_DEBUGING_INIT=y
# CONFIG_RT_DEBUGING_PAGE_LEAK is not set
#
# Inter-Thread communication
@ -57,25 +51,26 @@ CONFIG_RT_USING_MUTEX=y
CONFIG_RT_USING_EVENT=y
CONFIG_RT_USING_MAILBOX=y
CONFIG_RT_USING_MESSAGEQUEUE=y
# CONFIG_RT_USING_MESSAGEQUEUE_PRIORITY is not set
# CONFIG_RT_USING_SIGNALS is not set
#
# Memory Management
#
CONFIG_RT_PAGE_MAX_ORDER=11
CONFIG_RT_USING_MEMPOOL=y
CONFIG_RT_USING_SMALL_MEM=y
# CONFIG_RT_USING_SLAB is not set
CONFIG_RT_PAGE_MAX_ORDER=16
# CONFIG_RT_USING_MEMPOOL is not set
# CONFIG_RT_USING_SMALL_MEM is not set
CONFIG_RT_USING_SLAB=y
CONFIG_RT_USING_MEMHEAP=y
CONFIG_RT_MEMHEAP_FAST_MODE=y
# CONFIG_RT_MEMHEAP_BEST_MODE is not set
CONFIG_RT_USING_SMALL_MEM_AS_HEAP=y
# CONFIG_RT_USING_SMALL_MEM_AS_HEAP is not set
# CONFIG_RT_USING_MEMHEAP_AS_HEAP is not set
# CONFIG_RT_USING_SLAB_AS_HEAP is not set
CONFIG_RT_USING_SLAB_AS_HEAP=y
# CONFIG_RT_USING_USERHEAP is not set
# CONFIG_RT_USING_NOHEAP is not set
# CONFIG_RT_USING_MEMTRACE is not set
# CONFIG_RT_USING_HEAP_ISR is not set
CONFIG_RT_USING_HEAP_ISR=y
CONFIG_RT_USING_HEAP=y
#
@ -90,9 +85,13 @@ CONFIG_RT_CONSOLEBUF_SIZE=128
CONFIG_RT_CONSOLE_DEVICE_NAME="uart1"
CONFIG_RT_VER_NUM=0x50001
# CONFIG_RT_USING_STDC_ATOMIC is not set
#
# RT-Thread Architecture
#
CONFIG_ARCH_CPU_64BIT=y
CONFIG_RT_USING_CACHE=y
CONFIG_RT_USING_HW_ATOMIC=y
# CONFIG_RT_USING_HW_ATOMIC is not set
CONFIG_ARCH_ARM_BOOTWITH_FLUSH_CACHE=y
# CONFIG_ARCH_CPU_STACK_GROWS_UPWARD is not set
# CONFIG_RT_USING_CPU_FFS is not set
@ -101,6 +100,10 @@ CONFIG_ARCH_ARM=y
CONFIG_ARCH_ARM_MMU=y
CONFIG_KERNEL_VADDR_START=0xffff000000000000
CONFIG_ARCH_ARMV8=y
CONFIG_ARCH_TEXT_OFFSET=0x80000
CONFIG_ARCH_RAM_OFFSET=0x80000000
CONFIG_ARCH_SECONDARY_CPU_STACK_SIZE=4096
CONFIG_ARCH_HAVE_EFFICIENT_UNALIGNED_ACCESS=y
#
# RT-Thread Components
@ -138,12 +141,36 @@ CONFIG_RT_USING_DFS_V1=y
# CONFIG_RT_USING_DFS_V2 is not set
CONFIG_DFS_FILESYSTEMS_MAX=4
CONFIG_DFS_FILESYSTEM_TYPES_MAX=4
# CONFIG_RT_USING_DFS_ELMFAT is not set
CONFIG_RT_USING_DFS_ELMFAT=y
#
# elm-chan's FatFs, Generic FAT Filesystem Module
#
CONFIG_RT_DFS_ELM_CODE_PAGE=437
CONFIG_RT_DFS_ELM_WORD_ACCESS=y
# CONFIG_RT_DFS_ELM_USE_LFN_0 is not set
# CONFIG_RT_DFS_ELM_USE_LFN_1 is not set
# CONFIG_RT_DFS_ELM_USE_LFN_2 is not set
CONFIG_RT_DFS_ELM_USE_LFN_3=y
CONFIG_RT_DFS_ELM_USE_LFN=3
CONFIG_RT_DFS_ELM_LFN_UNICODE_0=y
# CONFIG_RT_DFS_ELM_LFN_UNICODE_1 is not set
# CONFIG_RT_DFS_ELM_LFN_UNICODE_2 is not set
# CONFIG_RT_DFS_ELM_LFN_UNICODE_3 is not set
CONFIG_RT_DFS_ELM_LFN_UNICODE=0
CONFIG_RT_DFS_ELM_MAX_LFN=255
CONFIG_RT_DFS_ELM_DRIVES=2
CONFIG_RT_DFS_ELM_MAX_SECTOR_SIZE=512
# CONFIG_RT_DFS_ELM_USE_ERASE is not set
CONFIG_RT_DFS_ELM_REENTRANT=y
CONFIG_RT_DFS_ELM_MUTEX_TIMEOUT=3000
CONFIG_RT_USING_DFS_DEVFS=y
# CONFIG_RT_USING_DFS_ROMFS is not set
# CONFIG_RT_USING_DFS_CROMFS is not set
CONFIG_RT_USING_DFS_RAMFS=y
# CONFIG_RT_USING_DFS_TMPFS is not set
# CONFIG_RT_USING_DFS_MQUEUE is not set
# CONFIG_RT_USING_DFS_NFS is not set
# CONFIG_RT_USING_FAL is not set
CONFIG_RT_USING_LWP=y
CONFIG_RT_LWP_MAX_NR=30
@ -188,7 +215,13 @@ CONFIG_RT_USING_RANDOM=y
CONFIG_RT_USING_RTC=y
# CONFIG_RT_USING_ALARM is not set
# CONFIG_RT_USING_SOFT_RTC is not set
# CONFIG_RT_USING_SDIO is not set
CONFIG_RT_USING_SDIO=y
CONFIG_RT_SDIO_STACK_SIZE=4096
CONFIG_RT_SDIO_THREAD_PRIORITY=15
CONFIG_RT_MMCSD_STACK_SIZE=4096
CONFIG_RT_MMCSD_THREAD_PREORITY=22
CONFIG_RT_MMCSD_MAX_PARTITION=16
# CONFIG_RT_SDIO_DEBUG is not set
# CONFIG_RT_USING_SPI is not set
# CONFIG_RT_USING_WDT is not set
# CONFIG_RT_USING_AUDIO is not set
@ -247,9 +280,110 @@ CONFIG_RT_USING_POSIX_TIMER=y
#
# Network
#
# CONFIG_RT_USING_SAL is not set
# CONFIG_RT_USING_NETDEV is not set
# CONFIG_RT_USING_LWIP is not set
CONFIG_RT_USING_SAL=y
CONFIG_SAL_INTERNET_CHECK=y
#
# Docking with protocol stacks
#
CONFIG_SAL_USING_LWIP=y
# CONFIG_SAL_USING_AT is not set
# CONFIG_SAL_USING_TLS is not set
CONFIG_SAL_USING_POSIX=y
# CONFIG_SAL_USING_AF_UNIX is not set
CONFIG_RT_USING_NETDEV=y
CONFIG_NETDEV_USING_IFCONFIG=y
CONFIG_NETDEV_USING_PING=y
CONFIG_NETDEV_USING_NETSTAT=y
CONFIG_NETDEV_USING_AUTO_DEFAULT=y
# CONFIG_NETDEV_USING_IPV6 is not set
CONFIG_NETDEV_IPV4=1
CONFIG_NETDEV_IPV6=0
# CONFIG_NETDEV_IPV6_SCOPES is not set
CONFIG_RT_USING_LWIP=y
# CONFIG_RT_USING_LWIP_LOCAL_VERSION is not set
# CONFIG_RT_USING_LWIP141 is not set
# CONFIG_RT_USING_LWIP203 is not set
CONFIG_RT_USING_LWIP212=y
# CONFIG_RT_USING_LWIP_LATEST is not set
CONFIG_RT_USING_LWIP_VER_NUM=0x20102
# CONFIG_RT_USING_LWIP_IPV6 is not set
CONFIG_RT_LWIP_MEM_ALIGNMENT=64
CONFIG_RT_LWIP_IGMP=y
CONFIG_RT_LWIP_ICMP=y
# CONFIG_RT_LWIP_SNMP is not set
CONFIG_RT_LWIP_DNS=y
# CONFIG_RT_LWIP_DHCP is not set
#
# Static IPv4 Address
#
CONFIG_RT_LWIP_IPADDR="192.168.4.10"
CONFIG_RT_LWIP_GWADDR="192.168.4.1"
CONFIG_RT_LWIP_MSKADDR="255.255.255.0"
CONFIG_RT_LWIP_UDP=y
CONFIG_RT_LWIP_TCP=y
CONFIG_RT_LWIP_RAW=y
# CONFIG_RT_LWIP_PPP is not set
CONFIG_RT_MEMP_NUM_NETCONN=8
CONFIG_RT_LWIP_PBUF_NUM=512
CONFIG_RT_LWIP_RAW_PCB_NUM=4
CONFIG_RT_LWIP_UDP_PCB_NUM=4
CONFIG_RT_LWIP_TCP_PCB_NUM=4
CONFIG_RT_LWIP_TCP_SEG_NUM=40
CONFIG_RT_LWIP_TCP_SND_BUF=8196
CONFIG_RT_LWIP_TCP_WND=8196
CONFIG_RT_LWIP_TCPTHREAD_PRIORITY=12
CONFIG_RT_LWIP_TCPTHREAD_MBOX_SIZE=8
CONFIG_RT_LWIP_TCPTHREAD_STACKSIZE=16184
# CONFIG_LWIP_NO_RX_THREAD is not set
# CONFIG_LWIP_NO_TX_THREAD is not set
CONFIG_RT_LWIP_ETHTHREAD_PRIORITY=12
CONFIG_RT_LWIP_ETHTHREAD_STACKSIZE=2048
CONFIG_RT_LWIP_ETHTHREAD_MBOX_SIZE=8
# CONFIG_RT_LWIP_REASSEMBLY_FRAG is not set
CONFIG_LWIP_NETIF_STATUS_CALLBACK=1
CONFIG_LWIP_NETIF_LINK_CALLBACK=1
CONFIG_SO_REUSE=1
CONFIG_LWIP_SO_RCVTIMEO=1
CONFIG_LWIP_SO_SNDTIMEO=1
CONFIG_LWIP_SO_RCVBUF=1
CONFIG_LWIP_SO_LINGER=0
# CONFIG_RT_LWIP_NETIF_LOOPBACK is not set
CONFIG_LWIP_NETIF_LOOPBACK=0
# CONFIG_RT_LWIP_STATS is not set
# CONFIG_RT_LWIP_USING_HW_CHECKSUM is not set
CONFIG_RT_LWIP_USING_PING=y
# CONFIG_LWIP_USING_DHCPD is not set
CONFIG_RT_LWIP_DEBUG=y
# CONFIG_RT_LWIP_SYS_DEBUG is not set
# CONFIG_RT_LWIP_ETHARP_DEBUG is not set
# CONFIG_RT_LWIP_PPP_DEBUG is not set
# CONFIG_RT_LWIP_MEM_DEBUG is not set
# CONFIG_RT_LWIP_MEMP_DEBUG is not set
# CONFIG_RT_LWIP_PBUF_DEBUG is not set
# CONFIG_RT_LWIP_API_LIB_DEBUG is not set
# CONFIG_RT_LWIP_API_MSG_DEBUG is not set
# CONFIG_RT_LWIP_TCPIP_DEBUG is not set
CONFIG_RT_LWIP_NETIF_DEBUG=y
# CONFIG_RT_LWIP_SOCKETS_DEBUG is not set
# CONFIG_RT_LWIP_DNS_DEBUG is not set
# CONFIG_RT_LWIP_AUTOIP_DEBUG is not set
# CONFIG_RT_LWIP_DHCP_DEBUG is not set
# CONFIG_RT_LWIP_IP_DEBUG is not set
# CONFIG_RT_LWIP_IP_REASS_DEBUG is not set
# CONFIG_RT_LWIP_ICMP_DEBUG is not set
# CONFIG_RT_LWIP_IGMP_DEBUG is not set
# CONFIG_RT_LWIP_UDP_DEBUG is not set
# CONFIG_RT_LWIP_TCP_DEBUG is not set
# CONFIG_RT_LWIP_TCP_INPUT_DEBUG is not set
# CONFIG_RT_LWIP_TCP_OUTPUT_DEBUG is not set
# CONFIG_RT_LWIP_TCP_RTO_DEBUG is not set
# CONFIG_RT_LWIP_TCP_CWND_DEBUG is not set
# CONFIG_RT_LWIP_TCP_WND_DEBUG is not set
# CONFIG_RT_LWIP_TCP_FR_DEBUG is not set
# CONFIG_RT_LWIP_TCP_QLEN_DEBUG is not set
# CONFIG_RT_LWIP_TCP_RST_DEBUG is not set
# CONFIG_RT_USING_AT is not set
#
@ -261,9 +395,15 @@ CONFIG_YMODEM_USING_FILE_TRANSFER=y
# CONFIG_RT_USING_ULOG is not set
# CONFIG_RT_USING_UTEST is not set
# CONFIG_RT_USING_VAR_EXPORT is not set
CONFIG_RT_USING_RESOURCE_ID=y
CONFIG_RT_USING_ADT=y
CONFIG_RT_USING_ADT_AVL=y
CONFIG_RT_USING_ADT_BITMAP=y
CONFIG_RT_USING_ADT_HASHMAP=y
CONFIG_RT_USING_ADT_REF=y
# CONFIG_RT_USING_RT_LINK is not set
# CONFIG_RT_USING_VBUS is not set
CONFIG_RT_USING_KTIME=y
#
# RT-Thread Utestcases
@ -1052,7 +1192,15 @@ CONFIG_RT_USING_UART1=y
# CONFIG_RT_USING_UART0 is not set
# CONFIG_BSP_USING_SPI is not set
# CONFIG_BSP_USING_CAN is not set
# CONFIG_BSP_USING_GPIO is not set
# CONFIG_BSP_USING_QSPI is not set
CONFIG_BSP_USING_ETH=y
CONFIG_RT_LWIP_PBUF_POOL_BUFSIZE=1700
CONFIG_BSP_USING_SDIO=y
CONFIG_BSP_USING_SDCARD_FATFS=y
# CONFIG_USING_SDIO0 is not set
CONFIG_USING_SDIO1=y
# CONFIG_USING_EMMC is not set
#
# Board extended module Drivers
@ -1092,6 +1240,8 @@ CONFIG_USE_QSPI=y
#
CONFIG_USE_FQSPI=y
# CONFIG_USE_GIC is not set
CONFIG_USE_IOPAD=y
CONFIG_ENABLE_IOPAD=y
CONFIG_USE_SERIAL=y
#
@ -1099,7 +1249,15 @@ CONFIG_USE_SERIAL=y
#
CONFIG_ENABLE_Pl011_UART=y
# CONFIG_USE_GPIO is not set
# CONFIG_USE_ETH is not set
CONFIG_USE_ETH=y
#
# Eth Configuration
#
CONFIG_ENABLE_FXMAC=y
# CONFIG_ENABLE_FGMAC is not set
CONFIG_FXMAC_PHY_COMMON=y
# CONFIG_FXMAC_PHY_YT is not set
# CONFIG_USE_CAN is not set
# CONFIG_USE_I2C is not set
# CONFIG_USE_TIMER is not set
@ -1117,13 +1275,17 @@ CONFIG_ENABLE_Pl011_UART=y
# CONFIG_USE_IPC is not set
# CONFIG_USE_MEDIA is not set
# CONFIG_USE_SCMI_MHU is not set
#
# Sdk common configuration
#
# CONFIG_LOG_VERBOS is not set
# CONFIG_LOG_DEBUG is not set
# CONFIG_LOG_INFO is not set
# CONFIG_LOG_WARN is not set
CONFIG_LOG_ERROR=y
# CONFIG_LOG_NONE is not set
# CONFIG_USE_DEFAULT_INTERRUPT_CONFIG is not set
# CONFIG_LOG_EXTRA_INFO is not set
# CONFIG_LOG_DISPALY_CORE_NUM is not set
# CONFIG_BOOTUP_DEBUG_PRINTS is not set
# CONFIG_USE_DEFAULT_INTERRUPT_CONFIG is not set

123
bsp/phytium/aarch64/configs/e2000d_rtsmart.h
View File

@ -19,17 +19,20 @@
#define RT_HOOK_USING_FUNC_PTR
#define RT_USING_IDLE_HOOK
#define RT_IDLE_HOOK_LIST_SIZE 4
#define IDLE_THREAD_STACK_SIZE 40960
#define SYSTEM_THREAD_STACK_SIZE 40960
#define IDLE_THREAD_STACK_SIZE 8192
#define SYSTEM_THREAD_STACK_SIZE 8192
#define RT_USING_TIMER_SOFT
#define RT_TIMER_THREAD_PRIO 4
#define RT_TIMER_THREAD_STACK_SIZE 4096
#define RT_TIMER_THREAD_STACK_SIZE 8192
/* kservice optimization */
#define RT_KSERVICE_USING_STDLIB
#define RT_KPRINTF_USING_LONGLONG
#define RT_USING_DEBUG
#define RT_DEBUGING_COLOR
#define RT_DEBUGING_CONTEXT
#define RT_DEBUGING_INIT
/* Inter-Thread communication */
@ -41,12 +44,12 @@
/* Memory Management */
#define RT_PAGE_MAX_ORDER 11
#define RT_USING_MEMPOOL
#define RT_USING_SMALL_MEM
#define RT_PAGE_MAX_ORDER 16
#define RT_USING_SLAB
#define RT_USING_MEMHEAP
#define RT_MEMHEAP_FAST_MODE
#define RT_USING_SMALL_MEM_AS_HEAP
#define RT_USING_SLAB_AS_HEAP
#define RT_USING_HEAP_ISR
#define RT_USING_HEAP
/* Kernel Device Object */
@ -56,15 +59,21 @@
#define RT_CONSOLEBUF_SIZE 128
#define RT_CONSOLE_DEVICE_NAME "uart1"
#define RT_VER_NUM 0x50001
/* RT-Thread Architecture */
#define ARCH_CPU_64BIT
#define RT_USING_CACHE
#define RT_USING_HW_ATOMIC
#define ARCH_ARM_BOOTWITH_FLUSH_CACHE
#define ARCH_MM_MMU
#define ARCH_ARM
#define ARCH_ARM_MMU
#define KERNEL_VADDR_START 0xffff000000000000
#define ARCH_ARMV8
#define ARCH_TEXT_OFFSET 0x80000
#define ARCH_RAM_OFFSET 0x80000000
#define ARCH_SECONDARY_CPU_STACK_SIZE 4096
#define ARCH_HAVE_EFFICIENT_UNALIGNED_ACCESS
/* RT-Thread Components */
@ -95,6 +104,21 @@
#define RT_USING_DFS_V1
#define DFS_FILESYSTEMS_MAX 4
#define DFS_FILESYSTEM_TYPES_MAX 4
#define RT_USING_DFS_ELMFAT
/* elm-chan's FatFs, Generic FAT Filesystem Module */
#define RT_DFS_ELM_CODE_PAGE 437
#define RT_DFS_ELM_WORD_ACCESS
#define RT_DFS_ELM_USE_LFN_3
#define RT_DFS_ELM_USE_LFN 3
#define RT_DFS_ELM_LFN_UNICODE_0
#define RT_DFS_ELM_LFN_UNICODE 0
#define RT_DFS_ELM_MAX_LFN 255
#define RT_DFS_ELM_DRIVES 2
#define RT_DFS_ELM_MAX_SECTOR_SIZE 512
#define RT_DFS_ELM_REENTRANT
#define RT_DFS_ELM_MUTEX_TIMEOUT 3000
#define RT_USING_DFS_DEVFS
#define RT_USING_DFS_RAMFS
#define RT_USING_LWP
@ -121,6 +145,12 @@
#define RT_USING_ZERO
#define RT_USING_RANDOM
#define RT_USING_RTC
#define RT_USING_SDIO
#define RT_SDIO_STACK_SIZE 4096
#define RT_SDIO_THREAD_PRIORITY 15
#define RT_MMCSD_STACK_SIZE 4096
#define RT_MMCSD_THREAD_PREORITY 22
#define RT_MMCSD_MAX_PARTITION 16
/* Using USB */
@ -147,12 +177,73 @@
/* Network */
#define RT_USING_SAL
#define SAL_INTERNET_CHECK
/* Docking with protocol stacks */
#define SAL_USING_LWIP
#define SAL_USING_POSIX
#define RT_USING_NETDEV
#define NETDEV_USING_IFCONFIG
#define NETDEV_USING_PING
#define NETDEV_USING_NETSTAT
#define NETDEV_USING_AUTO_DEFAULT
#define NETDEV_IPV4 1
#define NETDEV_IPV6 0
#define RT_USING_LWIP
#define RT_USING_LWIP212
#define RT_USING_LWIP_VER_NUM 0x20102
#define RT_LWIP_MEM_ALIGNMENT 64
#define RT_LWIP_IGMP
#define RT_LWIP_ICMP
#define RT_LWIP_DNS
/* Static IPv4 Address */
#define RT_LWIP_IPADDR "192.168.4.10"
#define RT_LWIP_GWADDR "192.168.4.1"
#define RT_LWIP_MSKADDR "255.255.255.0"
#define RT_LWIP_UDP
#define RT_LWIP_TCP
#define RT_LWIP_RAW
#define RT_MEMP_NUM_NETCONN 8
#define RT_LWIP_PBUF_NUM 512
#define RT_LWIP_RAW_PCB_NUM 4
#define RT_LWIP_UDP_PCB_NUM 4
#define RT_LWIP_TCP_PCB_NUM 4
#define RT_LWIP_TCP_SEG_NUM 40
#define RT_LWIP_TCP_SND_BUF 8196
#define RT_LWIP_TCP_WND 8196
#define RT_LWIP_TCPTHREAD_PRIORITY 12
#define RT_LWIP_TCPTHREAD_MBOX_SIZE 8
#define RT_LWIP_TCPTHREAD_STACKSIZE 16184
#define RT_LWIP_ETHTHREAD_PRIORITY 12
#define RT_LWIP_ETHTHREAD_STACKSIZE 2048
#define RT_LWIP_ETHTHREAD_MBOX_SIZE 8
#define LWIP_NETIF_STATUS_CALLBACK 1
#define LWIP_NETIF_LINK_CALLBACK 1
#define SO_REUSE 1
#define LWIP_SO_RCVTIMEO 1
#define LWIP_SO_SNDTIMEO 1
#define LWIP_SO_RCVBUF 1
#define LWIP_SO_LINGER 0
#define LWIP_NETIF_LOOPBACK 0
#define RT_LWIP_USING_PING
#define RT_LWIP_DEBUG
#define RT_LWIP_NETIF_DEBUG
/* Utilities */
#define RT_USING_RYM
#define YMODEM_USING_FILE_TRANSFER
#define RT_USING_RESOURCE_ID
#define RT_USING_ADT
#define RT_USING_ADT_AVL
#define RT_USING_ADT_BITMAP
#define RT_USING_ADT_HASHMAP
#define RT_USING_ADT_REF
#define RT_USING_KTIME
/* RT-Thread Utestcases */
@ -279,6 +370,11 @@
#define BSP_USING_UART
#define RT_USING_UART1
#define BSP_USING_ETH
#define RT_LWIP_PBUF_POOL_BUFSIZE 1700
#define BSP_USING_SDIO
#define BSP_USING_SDCARD_FATFS
#define USING_SDIO1
/* Board extended module Drivers */
@ -306,11 +402,22 @@
/* Qspi Configuration */
#define USE_FQSPI
#define USE_IOPAD
#define ENABLE_IOPAD
#define USE_SERIAL
/* Usart Configuration */
#define ENABLE_Pl011_UART
#define USE_ETH
/* Eth Configuration */
#define ENABLE_FXMAC
#define FXMAC_PHY_COMMON
/* Sdk common configuration */
#define LOG_ERROR
#endif

1284
bsp/phytium/aarch64/configs/e2000d_rtsmart_test Normal file
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File diff suppressed because it is too large Load Diff

405
bsp/phytium/aarch64/configs/e2000d_rtsmart_test.h Normal file
View File

@ -0,0 +1,405 @@
#ifndef RT_CONFIG_H__
#define RT_CONFIG_H__
/* Automatically generated file; DO NOT EDIT. */
/* RT-Thread Project Configuration */
/* RT-Thread Kernel */
#define RT_NAME_MAX 16
#define RT_USING_SMART
#define RT_USING_SMP
#define RT_CPUS_NR 2
#define RT_ALIGN_SIZE 4
#define RT_THREAD_PRIORITY_32
#define RT_THREAD_PRIORITY_MAX 32
#define RT_TICK_PER_SECOND 1000
#define RT_USING_OVERFLOW_CHECK
#define RT_USING_HOOK
#define RT_HOOK_USING_FUNC_PTR
#define RT_USING_IDLE_HOOK
#define RT_IDLE_HOOK_LIST_SIZE 4
#define IDLE_THREAD_STACK_SIZE 40960
#define SYSTEM_THREAD_STACK_SIZE 40960
#define RT_USING_TIMER_SOFT
#define RT_TIMER_THREAD_PRIO 4
#define RT_TIMER_THREAD_STACK_SIZE 4096
/* kservice optimization */
#define RT_KSERVICE_USING_STDLIB
#define RT_KPRINTF_USING_LONGLONG
#define RT_DEBUG
/* Inter-Thread communication */
#define RT_USING_SEMAPHORE
#define RT_USING_MUTEX
#define RT_USING_EVENT
#define RT_USING_MAILBOX
#define RT_USING_MESSAGEQUEUE
/* Memory Management */
#define RT_PAGE_MAX_ORDER 16
#define RT_USING_SLAB
#define RT_USING_MEMHEAP
#define RT_MEMHEAP_FAST_MODE
#define RT_USING_SLAB_AS_HEAP
#define RT_USING_HEAP_ISR
#define RT_USING_HEAP
/* Kernel Device Object */
#define RT_USING_DEVICE
#define RT_USING_CONSOLE
#define RT_CONSOLEBUF_SIZE 128
#define RT_CONSOLE_DEVICE_NAME "uart1"
#define RT_VER_NUM 0x50001
#define ARCH_CPU_64BIT
#define RT_USING_CACHE
#define ARCH_ARM_BOOTWITH_FLUSH_CACHE
#define ARCH_MM_MMU
#define ARCH_ARM
#define ARCH_ARM_MMU
#define KERNEL_VADDR_START 0xffff000000000000
#define ARCH_ARMV8
/* RT-Thread Components */
#define RT_USING_COMPONENTS_INIT
#define RT_USING_USER_MAIN
#define RT_MAIN_THREAD_STACK_SIZE 8192
#define RT_MAIN_THREAD_PRIORITY 10
#define RT_USING_MSH
#define RT_USING_FINSH
#define FINSH_USING_MSH
#define FINSH_THREAD_NAME "tshell"
#define FINSH_THREAD_PRIORITY 20
#define FINSH_THREAD_STACK_SIZE 4096
#define FINSH_USING_HISTORY
#define FINSH_HISTORY_LINES 5
#define FINSH_USING_SYMTAB
#define FINSH_CMD_SIZE 80
#define MSH_USING_BUILT_IN_COMMANDS
#define FINSH_USING_DESCRIPTION
#define FINSH_ARG_MAX 10
/* DFS: device virtual file system */
#define RT_USING_DFS
#define DFS_USING_POSIX
#define DFS_USING_WORKDIR
#define DFS_FD_MAX 16
#define RT_USING_DFS_V1
#define DFS_FILESYSTEMS_MAX 4
#define DFS_FILESYSTEM_TYPES_MAX 4
#define RT_USING_DFS_ELMFAT
/* elm-chan's FatFs, Generic FAT Filesystem Module */
#define RT_DFS_ELM_CODE_PAGE 437
#define RT_DFS_ELM_WORD_ACCESS
#define RT_DFS_ELM_USE_LFN_3
#define RT_DFS_ELM_USE_LFN 3
#define RT_DFS_ELM_LFN_UNICODE_0
#define RT_DFS_ELM_LFN_UNICODE 0
#define RT_DFS_ELM_MAX_LFN 255
#define RT_DFS_ELM_DRIVES 2
#define RT_DFS_ELM_MAX_SECTOR_SIZE 512
#define RT_DFS_ELM_REENTRANT
#define RT_DFS_ELM_MUTEX_TIMEOUT 3000
#define RT_USING_DFS_DEVFS
#define RT_USING_DFS_RAMFS
#define RT_USING_LWP
#define RT_LWP_MAX_NR 30
#define LWP_TASK_STACK_SIZE 16384
#define RT_CH_MSG_MAX_NR 1024
#define LWP_CONSOLE_INPUT_BUFFER_SIZE 1024
#define LWP_TID_MAX_NR 64
#define RT_LWP_SHM_MAX_NR 64
/* Device Drivers */
#define RT_USING_DEVICE_IPC
#define RT_UNAMED_PIPE_NUMBER 64
#define RT_USING_SYSTEM_WORKQUEUE
#define RT_SYSTEM_WORKQUEUE_STACKSIZE 8192
#define RT_SYSTEM_WORKQUEUE_PRIORITY 23
#define RT_USING_SERIAL
#define RT_USING_SERIAL_V1
#define RT_SERIAL_USING_DMA
#define RT_SERIAL_RB_BUFSZ 64
#define RT_USING_TTY
#define RT_USING_NULL
#define RT_USING_ZERO
#define RT_USING_RANDOM
#define RT_USING_RTC
#define RT_USING_SDIO
#define RT_SDIO_STACK_SIZE 4096
#define RT_SDIO_THREAD_PRIORITY 15
#define RT_MMCSD_STACK_SIZE 4096
#define RT_MMCSD_THREAD_PREORITY 22
#define RT_MMCSD_MAX_PARTITION 16
/* Using USB */
/* C/C++ and POSIX layer */
#define RT_LIBC_DEFAULT_TIMEZONE 8
/* POSIX (Portable Operating System Interface) layer */
#define RT_USING_POSIX_FS
#define RT_USING_POSIX_DEVIO
#define RT_USING_POSIX_STDIO
#define RT_USING_POSIX_TERMIOS
#define RT_USING_POSIX_DELAY
#define RT_USING_POSIX_CLOCK
#define RT_USING_POSIX_TIMER
/* Interprocess Communication (IPC) */
/* Socket is in the 'Network' category */
/* Network */
#define RT_USING_SAL
#define SAL_INTERNET_CHECK
/* Docking with protocol stacks */
#define SAL_USING_LWIP
#define SAL_USING_POSIX
#define RT_USING_NETDEV
#define NETDEV_USING_IFCONFIG
#define NETDEV_USING_PING
#define NETDEV_USING_NETSTAT
#define NETDEV_USING_AUTO_DEFAULT
#define NETDEV_IPV4 1
#define NETDEV_IPV6 0
#define RT_USING_LWIP
#define RT_USING_LWIP212
#define RT_USING_LWIP_VER_NUM 0x20102
#define RT_LWIP_MEM_ALIGNMENT 64
#define RT_LWIP_IGMP
#define RT_LWIP_ICMP
#define RT_LWIP_DNS
/* Static IPv4 Address */
#define RT_LWIP_IPADDR "192.168.4.10"
#define RT_LWIP_GWADDR "192.168.4.1"
#define RT_LWIP_MSKADDR "255.255.255.0"
#define RT_LWIP_UDP
#define RT_LWIP_TCP
#define RT_LWIP_RAW
#define RT_MEMP_NUM_NETCONN 8
#define RT_LWIP_PBUF_NUM 512
#define RT_LWIP_RAW_PCB_NUM 4
#define RT_LWIP_UDP_PCB_NUM 4
#define RT_LWIP_TCP_PCB_NUM 4
#define RT_LWIP_TCP_SEG_NUM 40
#define RT_LWIP_TCP_SND_BUF 8196
#define RT_LWIP_TCP_WND 8196
#define RT_LWIP_TCPTHREAD_PRIORITY 12
#define RT_LWIP_TCPTHREAD_MBOX_SIZE 8
#define RT_LWIP_TCPTHREAD_STACKSIZE 16184
#define RT_LWIP_ETHTHREAD_PRIORITY 12
#define RT_LWIP_ETHTHREAD_STACKSIZE 2048
#define RT_LWIP_ETHTHREAD_MBOX_SIZE 8
#define LWIP_NETIF_STATUS_CALLBACK 1
#define LWIP_NETIF_LINK_CALLBACK 1
#define SO_REUSE 1
#define LWIP_SO_RCVTIMEO 1
#define LWIP_SO_SNDTIMEO 1
#define LWIP_SO_RCVBUF 1
#define LWIP_SO_LINGER 0
#define LWIP_NETIF_LOOPBACK 0
#define RT_LWIP_USING_PING
#define RT_LWIP_DEBUG
#define RT_LWIP_NETIF_DEBUG
/* Utilities */
#define RT_USING_RYM
#define YMODEM_USING_FILE_TRANSFER
#define RT_USING_ADT
/* RT-Thread Utestcases */
/* RT-Thread online packages */
/* IoT - internet of things */
/* Wi-Fi */
/* Marvell WiFi */
/* Wiced WiFi */
/* IoT Cloud */
/* security packages */
/* language packages */
/* JSON: JavaScript Object Notation, a lightweight data-interchange format */
/* XML: Extensible Markup Language */
/* multimedia packages */
/* LVGL: powerful and easy-to-use embedded GUI library */
/* u8g2: a monochrome graphic library */
/* tools packages */
/* system packages */
/* enhanced kernel services */
/* acceleration: Assembly language or algorithmic acceleration packages */
/* CMSIS: ARM Cortex-M Microcontroller Software Interface Standard */
/* Micrium: Micrium software products porting for RT-Thread */
/* peripheral libraries and drivers */
/* sensors drivers */
/* touch drivers */
/* Kendryte SDK */
/* AI packages */
/* Signal Processing and Control Algorithm Packages */
/* miscellaneous packages */
/* project laboratory */
/* samples: kernel and components samples */
#define PKG_USING_KERNEL_SAMPLES
#define PKG_USING_KERNEL_SAMPLES_LATEST_VERSION
#define PKG_USING_KERNEL_SAMPLES_EN
/* entertainment: terminal games and other interesting software packages */
/* Arduino libraries */
/* Projects */
/* Sensors */
/* Display */
/* Timing */
/* Data Processing */
/* Data Storage */
/* Communication */
/* Device Control */
/* Other */
/* Signal IO */
/* Uncategorized */
/* Hardware Drivers */
/* On-chip Peripheral Drivers */
#define BSP_USING_UART
#define RT_USING_UART1
#define BSP_USING_ETH
#define RT_LWIP_PBUF_POOL_BUFSIZE 1700
#define BSP_USING_SDIO
#define BSP_USING_SDCARD_FATFS
#define USING_SDIO1
/* Board extended module Drivers */
#define BSP_USING_GIC
#define BSP_USING_GICV3
#define PHYTIUM_ARCH_AARCH64
#define ARM_SPI_BIND_CPU_ID 0
/* Standalone Setting */
#define TARGET_ARMV8_AARCH64
/* Board Configuration */
#define TARGET_E2000D
#define TARGET_E2000
#define DEFAULT_DEBUG_PRINT_UART1
/* Components Configuration */
#define USE_SPI
#define USE_FSPIM
#define USE_QSPI
/* Qspi Configuration */
#define USE_FQSPI
#define USE_IOPAD
#define ENABLE_IOPAD
#define USE_SERIAL
/* Usart Configuration */
#define ENABLE_Pl011_UART
#define USE_ETH
/* Eth Configuration */
#define ENABLE_FXMAC
#define FXMAC_PHY_COMMON
#define LOG_ERROR
#define PHYTIUM_RTT_TEST
#endif

222
bsp/phytium/aarch64/configs/e2000d_rtthread
View File

@ -9,6 +9,7 @@
CONFIG_RT_NAME_MAX=16
# CONFIG_RT_USING_ARCH_DATA_TYPE is not set
# CONFIG_RT_USING_SMART is not set
# CONFIG_RT_USING_AMP is not set
CONFIG_RT_USING_SMP=y
CONFIG_RT_CPUS_NR=2
CONFIG_RT_ALIGN_SIZE=4
@ -22,11 +23,11 @@ CONFIG_RT_USING_HOOK=y
CONFIG_RT_HOOK_USING_FUNC_PTR=y
CONFIG_RT_USING_IDLE_HOOK=y
CONFIG_RT_IDLE_HOOK_LIST_SIZE=4
CONFIG_IDLE_THREAD_STACK_SIZE=40960
CONFIG_SYSTEM_THREAD_STACK_SIZE=40960
CONFIG_IDLE_THREAD_STACK_SIZE=8192
CONFIG_SYSTEM_THREAD_STACK_SIZE=8192
CONFIG_RT_USING_TIMER_SOFT=y
CONFIG_RT_TIMER_THREAD_PRIO=4
CONFIG_RT_TIMER_THREAD_STACK_SIZE=4096
CONFIG_RT_TIMER_THREAD_STACK_SIZE=8192
#
# kservice optimization
@ -36,18 +37,11 @@ CONFIG_RT_KSERVICE_USING_STDLIB=y
# CONFIG_RT_KSERVICE_USING_TINY_SIZE is not set
# CONFIG_RT_USING_TINY_FFS is not set
CONFIG_RT_KPRINTF_USING_LONGLONG=y
CONFIG_RT_DEBUG=y
# CONFIG_RT_DEBUG_COLOR is not set
# CONFIG_RT_DEBUG_INIT_CONFIG is not set
# CONFIG_RT_DEBUG_THREAD_CONFIG is not set
# CONFIG_RT_DEBUG_SCHEDULER_CONFIG is not set
# CONFIG_RT_DEBUG_IPC_CONFIG is not set
# CONFIG_RT_DEBUG_TIMER_CONFIG is not set
# CONFIG_RT_DEBUG_IRQ_CONFIG is not set
# CONFIG_RT_DEBUG_MEM_CONFIG is not set
# CONFIG_RT_DEBUG_SLAB_CONFIG is not set
# CONFIG_RT_DEBUG_MEMHEAP_CONFIG is not set
# CONFIG_RT_DEBUG_MODULE_CONFIG is not set
CONFIG_RT_USING_DEBUG=y
CONFIG_RT_DEBUGING_COLOR=y
CONFIG_RT_DEBUGING_CONTEXT=y
CONFIG_RT_DEBUGING_INIT=y
# CONFIG_RT_DEBUGING_PAGE_LEAK is not set
#
# Inter-Thread communication
@ -57,25 +51,26 @@ CONFIG_RT_USING_MUTEX=y
CONFIG_RT_USING_EVENT=y
CONFIG_RT_USING_MAILBOX=y
CONFIG_RT_USING_MESSAGEQUEUE=y
# CONFIG_RT_USING_MESSAGEQUEUE_PRIORITY is not set
# CONFIG_RT_USING_SIGNALS is not set
#
# Memory Management
#
CONFIG_RT_PAGE_MAX_ORDER=11
CONFIG_RT_USING_MEMPOOL=y
CONFIG_RT_USING_SMALL_MEM=y
# CONFIG_RT_USING_SLAB is not set
CONFIG_RT_PAGE_MAX_ORDER=16
# CONFIG_RT_USING_MEMPOOL is not set
# CONFIG_RT_USING_SMALL_MEM is not set
CONFIG_RT_USING_SLAB=y
CONFIG_RT_USING_MEMHEAP=y
CONFIG_RT_MEMHEAP_FAST_MODE=y
# CONFIG_RT_MEMHEAP_BEST_MODE is not set
CONFIG_RT_USING_SMALL_MEM_AS_HEAP=y
# CONFIG_RT_USING_SMALL_MEM_AS_HEAP is not set
# CONFIG_RT_USING_MEMHEAP_AS_HEAP is not set
# CONFIG_RT_USING_SLAB_AS_HEAP is not set
CONFIG_RT_USING_SLAB_AS_HEAP=y
# CONFIG_RT_USING_USERHEAP is not set
# CONFIG_RT_USING_NOHEAP is not set
# CONFIG_RT_USING_MEMTRACE is not set
# CONFIG_RT_USING_HEAP_ISR is not set
CONFIG_RT_USING_HEAP_ISR=y
CONFIG_RT_USING_HEAP=y
#
@ -90,9 +85,13 @@ CONFIG_RT_CONSOLEBUF_SIZE=128
CONFIG_RT_CONSOLE_DEVICE_NAME="uart1"
CONFIG_RT_VER_NUM=0x50001
# CONFIG_RT_USING_STDC_ATOMIC is not set
#
# RT-Thread Architecture
#
CONFIG_ARCH_CPU_64BIT=y
CONFIG_RT_USING_CACHE=y
CONFIG_RT_USING_HW_ATOMIC=y
# CONFIG_RT_USING_HW_ATOMIC is not set
CONFIG_ARCH_ARM_BOOTWITH_FLUSH_CACHE=y
# CONFIG_ARCH_CPU_STACK_GROWS_UPWARD is not set
# CONFIG_RT_USING_CPU_FFS is not set
@ -100,6 +99,10 @@ CONFIG_ARCH_MM_MMU=y
CONFIG_ARCH_ARM=y
CONFIG_ARCH_ARM_MMU=y
CONFIG_ARCH_ARMV8=y
CONFIG_ARCH_TEXT_OFFSET=0x80000
CONFIG_ARCH_RAM_OFFSET=0x80000000
CONFIG_ARCH_SECONDARY_CPU_STACK_SIZE=4096
CONFIG_ARCH_HAVE_EFFICIENT_UNALIGNED_ACCESS=y
#
# RT-Thread Components
@ -137,12 +140,36 @@ CONFIG_RT_USING_DFS_V1=y
# CONFIG_RT_USING_DFS_V2 is not set
CONFIG_DFS_FILESYSTEMS_MAX=4
CONFIG_DFS_FILESYSTEM_TYPES_MAX=4
# CONFIG_RT_USING_DFS_ELMFAT is not set
CONFIG_RT_USING_DFS_ELMFAT=y
#
# elm-chan's FatFs, Generic FAT Filesystem Module
#
CONFIG_RT_DFS_ELM_CODE_PAGE=437
CONFIG_RT_DFS_ELM_WORD_ACCESS=y
# CONFIG_RT_DFS_ELM_USE_LFN_0 is not set
# CONFIG_RT_DFS_ELM_USE_LFN_1 is not set
# CONFIG_RT_DFS_ELM_USE_LFN_2 is not set
CONFIG_RT_DFS_ELM_USE_LFN_3=y
CONFIG_RT_DFS_ELM_USE_LFN=3
CONFIG_RT_DFS_ELM_LFN_UNICODE_0=y
# CONFIG_RT_DFS_ELM_LFN_UNICODE_1 is not set
# CONFIG_RT_DFS_ELM_LFN_UNICODE_2 is not set
# CONFIG_RT_DFS_ELM_LFN_UNICODE_3 is not set
CONFIG_RT_DFS_ELM_LFN_UNICODE=0
CONFIG_RT_DFS_ELM_MAX_LFN=255
CONFIG_RT_DFS_ELM_DRIVES=2
CONFIG_RT_DFS_ELM_MAX_SECTOR_SIZE=512
# CONFIG_RT_DFS_ELM_USE_ERASE is not set
CONFIG_RT_DFS_ELM_REENTRANT=y
CONFIG_RT_DFS_ELM_MUTEX_TIMEOUT=3000
CONFIG_RT_USING_DFS_DEVFS=y
# CONFIG_RT_USING_DFS_ROMFS is not set
# CONFIG_RT_USING_DFS_CROMFS is not set
CONFIG_RT_USING_DFS_RAMFS=y
# CONFIG_RT_USING_DFS_TMPFS is not set
# CONFIG_RT_USING_DFS_MQUEUE is not set
# CONFIG_RT_USING_DFS_NFS is not set
# CONFIG_RT_USING_FAL is not set
#
@ -177,7 +204,13 @@ CONFIG_RT_USING_RANDOM=y
CONFIG_RT_USING_RTC=y
# CONFIG_RT_USING_ALARM is not set
# CONFIG_RT_USING_SOFT_RTC is not set
# CONFIG_RT_USING_SDIO is not set
CONFIG_RT_USING_SDIO=y
CONFIG_RT_SDIO_STACK_SIZE=4096
CONFIG_RT_SDIO_THREAD_PRIORITY=15
CONFIG_RT_MMCSD_STACK_SIZE=4096
CONFIG_RT_MMCSD_THREAD_PREORITY=22
CONFIG_RT_MMCSD_MAX_PARTITION=16
# CONFIG_RT_SDIO_DEBUG is not set
# CONFIG_RT_USING_SPI is not set
# CONFIG_RT_USING_WDT is not set
# CONFIG_RT_USING_AUDIO is not set
@ -236,9 +269,110 @@ CONFIG_RT_USING_POSIX_TIMER=y
#
# Network
#
# CONFIG_RT_USING_SAL is not set
# CONFIG_RT_USING_NETDEV is not set
# CONFIG_RT_USING_LWIP is not set
CONFIG_RT_USING_SAL=y
CONFIG_SAL_INTERNET_CHECK=y
#
# Docking with protocol stacks
#
CONFIG_SAL_USING_LWIP=y
# CONFIG_SAL_USING_AT is not set
# CONFIG_SAL_USING_TLS is not set
CONFIG_SAL_USING_POSIX=y
# CONFIG_SAL_USING_AF_UNIX is not set
CONFIG_RT_USING_NETDEV=y
CONFIG_NETDEV_USING_IFCONFIG=y
CONFIG_NETDEV_USING_PING=y
CONFIG_NETDEV_USING_NETSTAT=y
CONFIG_NETDEV_USING_AUTO_DEFAULT=y
# CONFIG_NETDEV_USING_IPV6 is not set
CONFIG_NETDEV_IPV4=1
CONFIG_NETDEV_IPV6=0
# CONFIG_NETDEV_IPV6_SCOPES is not set
CONFIG_RT_USING_LWIP=y
# CONFIG_RT_USING_LWIP_LOCAL_VERSION is not set
# CONFIG_RT_USING_LWIP141 is not set
# CONFIG_RT_USING_LWIP203 is not set
CONFIG_RT_USING_LWIP212=y
# CONFIG_RT_USING_LWIP_LATEST is not set
CONFIG_RT_USING_LWIP_VER_NUM=0x20102
# CONFIG_RT_USING_LWIP_IPV6 is not set
CONFIG_RT_LWIP_MEM_ALIGNMENT=64
CONFIG_RT_LWIP_IGMP=y
CONFIG_RT_LWIP_ICMP=y
# CONFIG_RT_LWIP_SNMP is not set
CONFIG_RT_LWIP_DNS=y
# CONFIG_RT_LWIP_DHCP is not set
#
# Static IPv4 Address
#
CONFIG_RT_LWIP_IPADDR="192.168.4.10"
CONFIG_RT_LWIP_GWADDR="192.168.4.1"
CONFIG_RT_LWIP_MSKADDR="255.255.255.0"
CONFIG_RT_LWIP_UDP=y
CONFIG_RT_LWIP_TCP=y
CONFIG_RT_LWIP_RAW=y
# CONFIG_RT_LWIP_PPP is not set
CONFIG_RT_MEMP_NUM_NETCONN=8
CONFIG_RT_LWIP_PBUF_NUM=512
CONFIG_RT_LWIP_RAW_PCB_NUM=4
CONFIG_RT_LWIP_UDP_PCB_NUM=4
CONFIG_RT_LWIP_TCP_PCB_NUM=4
CONFIG_RT_LWIP_TCP_SEG_NUM=40
CONFIG_RT_LWIP_TCP_SND_BUF=8196
CONFIG_RT_LWIP_TCP_WND=8196
CONFIG_RT_LWIP_TCPTHREAD_PRIORITY=12
CONFIG_RT_LWIP_TCPTHREAD_MBOX_SIZE=8
CONFIG_RT_LWIP_TCPTHREAD_STACKSIZE=16184
# CONFIG_LWIP_NO_RX_THREAD is not set
# CONFIG_LWIP_NO_TX_THREAD is not set
CONFIG_RT_LWIP_ETHTHREAD_PRIORITY=12
CONFIG_RT_LWIP_ETHTHREAD_STACKSIZE=2048
CONFIG_RT_LWIP_ETHTHREAD_MBOX_SIZE=8
# CONFIG_RT_LWIP_REASSEMBLY_FRAG is not set
CONFIG_LWIP_NETIF_STATUS_CALLBACK=1
CONFIG_LWIP_NETIF_LINK_CALLBACK=1
CONFIG_SO_REUSE=1
CONFIG_LWIP_SO_RCVTIMEO=1
CONFIG_LWIP_SO_SNDTIMEO=1
CONFIG_LWIP_SO_RCVBUF=1
CONFIG_LWIP_SO_LINGER=0
# CONFIG_RT_LWIP_NETIF_LOOPBACK is not set
CONFIG_LWIP_NETIF_LOOPBACK=0
# CONFIG_RT_LWIP_STATS is not set
# CONFIG_RT_LWIP_USING_HW_CHECKSUM is not set
CONFIG_RT_LWIP_USING_PING=y
# CONFIG_LWIP_USING_DHCPD is not set
CONFIG_RT_LWIP_DEBUG=y
# CONFIG_RT_LWIP_SYS_DEBUG is not set
# CONFIG_RT_LWIP_ETHARP_DEBUG is not set
# CONFIG_RT_LWIP_PPP_DEBUG is not set
# CONFIG_RT_LWIP_MEM_DEBUG is not set
# CONFIG_RT_LWIP_MEMP_DEBUG is not set
# CONFIG_RT_LWIP_PBUF_DEBUG is not set
# CONFIG_RT_LWIP_API_LIB_DEBUG is not set
# CONFIG_RT_LWIP_API_MSG_DEBUG is not set
# CONFIG_RT_LWIP_TCPIP_DEBUG is not set
CONFIG_RT_LWIP_NETIF_DEBUG=y
# CONFIG_RT_LWIP_SOCKETS_DEBUG is not set
# CONFIG_RT_LWIP_DNS_DEBUG is not set
# CONFIG_RT_LWIP_AUTOIP_DEBUG is not set
# CONFIG_RT_LWIP_DHCP_DEBUG is not set
# CONFIG_RT_LWIP_IP_DEBUG is not set
# CONFIG_RT_LWIP_IP_REASS_DEBUG is not set
# CONFIG_RT_LWIP_ICMP_DEBUG is not set
# CONFIG_RT_LWIP_IGMP_DEBUG is not set
# CONFIG_RT_LWIP_UDP_DEBUG is not set
# CONFIG_RT_LWIP_TCP_DEBUG is not set
# CONFIG_RT_LWIP_TCP_INPUT_DEBUG is not set
# CONFIG_RT_LWIP_TCP_OUTPUT_DEBUG is not set
# CONFIG_RT_LWIP_TCP_RTO_DEBUG is not set
# CONFIG_RT_LWIP_TCP_CWND_DEBUG is not set
# CONFIG_RT_LWIP_TCP_WND_DEBUG is not set
# CONFIG_RT_LWIP_TCP_FR_DEBUG is not set
# CONFIG_RT_LWIP_TCP_QLEN_DEBUG is not set
# CONFIG_RT_LWIP_TCP_RST_DEBUG is not set
# CONFIG_RT_USING_AT is not set
#
@ -250,9 +384,15 @@ CONFIG_YMODEM_USING_FILE_TRANSFER=y
# CONFIG_RT_USING_ULOG is not set
# CONFIG_RT_USING_UTEST is not set
# CONFIG_RT_USING_VAR_EXPORT is not set
CONFIG_RT_USING_RESOURCE_ID=y
CONFIG_RT_USING_ADT=y
CONFIG_RT_USING_ADT_AVL=y
CONFIG_RT_USING_ADT_BITMAP=y
CONFIG_RT_USING_ADT_HASHMAP=y
CONFIG_RT_USING_ADT_REF=y
# CONFIG_RT_USING_RT_LINK is not set
# CONFIG_RT_USING_VBUS is not set
CONFIG_RT_USING_KTIME=y
#
# RT-Thread Utestcases
@ -1041,7 +1181,15 @@ CONFIG_RT_USING_UART1=y
# CONFIG_RT_USING_UART0 is not set
# CONFIG_BSP_USING_SPI is not set
# CONFIG_BSP_USING_CAN is not set
# CONFIG_BSP_USING_GPIO is not set
# CONFIG_BSP_USING_QSPI is not set
CONFIG_BSP_USING_ETH=y
CONFIG_RT_LWIP_PBUF_POOL_BUFSIZE=1700
CONFIG_BSP_USING_SDIO=y
CONFIG_BSP_USING_SDCARD_FATFS=y
# CONFIG_USING_SDIO0 is not set
CONFIG_USING_SDIO1=y
# CONFIG_USING_EMMC is not set
#
# Board extended module Drivers
@ -1081,6 +1229,8 @@ CONFIG_USE_QSPI=y
#
CONFIG_USE_FQSPI=y
# CONFIG_USE_GIC is not set
CONFIG_USE_IOPAD=y
CONFIG_ENABLE_IOPAD=y
CONFIG_USE_SERIAL=y
#
@ -1088,7 +1238,15 @@ CONFIG_USE_SERIAL=y
#
CONFIG_ENABLE_Pl011_UART=y
# CONFIG_USE_GPIO is not set
# CONFIG_USE_ETH is not set
CONFIG_USE_ETH=y
#
# Eth Configuration
#
CONFIG_ENABLE_FXMAC=y
# CONFIG_ENABLE_FGMAC is not set
CONFIG_FXMAC_PHY_COMMON=y
# CONFIG_FXMAC_PHY_YT is not set
# CONFIG_USE_CAN is not set
# CONFIG_USE_I2C is not set
# CONFIG_USE_TIMER is not set
@ -1106,13 +1264,17 @@ CONFIG_ENABLE_Pl011_UART=y
# CONFIG_USE_IPC is not set
# CONFIG_USE_MEDIA is not set
# CONFIG_USE_SCMI_MHU is not set
#
# Sdk common configuration
#
# CONFIG_LOG_VERBOS is not set
# CONFIG_LOG_DEBUG is not set
# CONFIG_LOG_INFO is not set
# CONFIG_LOG_WARN is not set
CONFIG_LOG_ERROR=y
# CONFIG_LOG_NONE is not set
# CONFIG_USE_DEFAULT_INTERRUPT_CONFIG is not set
# CONFIG_LOG_EXTRA_INFO is not set
# CONFIG_LOG_DISPALY_CORE_NUM is not set
# CONFIG_BOOTUP_DEBUG_PRINTS is not set
# CONFIG_USE_DEFAULT_INTERRUPT_CONFIG is not set

123
bsp/phytium/aarch64/configs/e2000d_rtthread.h
View File

@ -18,17 +18,20 @@
#define RT_HOOK_USING_FUNC_PTR
#define RT_USING_IDLE_HOOK
#define RT_IDLE_HOOK_LIST_SIZE 4
#define IDLE_THREAD_STACK_SIZE 40960
#define SYSTEM_THREAD_STACK_SIZE 40960
#define IDLE_THREAD_STACK_SIZE 8192
#define SYSTEM_THREAD_STACK_SIZE 8192
#define RT_USING_TIMER_SOFT
#define RT_TIMER_THREAD_PRIO 4
#define RT_TIMER_THREAD_STACK_SIZE 4096
#define RT_TIMER_THREAD_STACK_SIZE 8192
/* kservice optimization */
#define RT_KSERVICE_USING_STDLIB
#define RT_KPRINTF_USING_LONGLONG
#define RT_USING_DEBUG
#define RT_DEBUGING_COLOR
#define RT_DEBUGING_CONTEXT
#define RT_DEBUGING_INIT
/* Inter-Thread communication */
@ -40,12 +43,12 @@
/* Memory Management */
#define RT_PAGE_MAX_ORDER 11
#define RT_USING_MEMPOOL
#define RT_USING_SMALL_MEM
#define RT_PAGE_MAX_ORDER 16
#define RT_USING_SLAB
#define RT_USING_MEMHEAP
#define RT_MEMHEAP_FAST_MODE
#define RT_USING_SMALL_MEM_AS_HEAP
#define RT_USING_SLAB_AS_HEAP
#define RT_USING_HEAP_ISR
#define RT_USING_HEAP
/* Kernel Device Object */
@ -55,14 +58,20 @@
#define RT_CONSOLEBUF_SIZE 128
#define RT_CONSOLE_DEVICE_NAME "uart1"
#define RT_VER_NUM 0x50001
/* RT-Thread Architecture */
#define ARCH_CPU_64BIT
#define RT_USING_CACHE
#define RT_USING_HW_ATOMIC
#define ARCH_ARM_BOOTWITH_FLUSH_CACHE
#define ARCH_MM_MMU
#define ARCH_ARM
#define ARCH_ARM_MMU
#define ARCH_ARMV8
#define ARCH_TEXT_OFFSET 0x80000
#define ARCH_RAM_OFFSET 0x80000000
#define ARCH_SECONDARY_CPU_STACK_SIZE 4096
#define ARCH_HAVE_EFFICIENT_UNALIGNED_ACCESS
/* RT-Thread Components */
@ -93,6 +102,21 @@
#define RT_USING_DFS_V1
#define DFS_FILESYSTEMS_MAX 4
#define DFS_FILESYSTEM_TYPES_MAX 4
#define RT_USING_DFS_ELMFAT
/* elm-chan's FatFs, Generic FAT Filesystem Module */
#define RT_DFS_ELM_CODE_PAGE 437
#define RT_DFS_ELM_WORD_ACCESS
#define RT_DFS_ELM_USE_LFN_3
#define RT_DFS_ELM_USE_LFN 3
#define RT_DFS_ELM_LFN_UNICODE_0
#define RT_DFS_ELM_LFN_UNICODE 0
#define RT_DFS_ELM_MAX_LFN 255
#define RT_DFS_ELM_DRIVES 2
#define RT_DFS_ELM_MAX_SECTOR_SIZE 512
#define RT_DFS_ELM_REENTRANT
#define RT_DFS_ELM_MUTEX_TIMEOUT 3000
#define RT_USING_DFS_DEVFS
#define RT_USING_DFS_RAMFS
@ -111,6 +135,12 @@
#define RT_USING_ZERO
#define RT_USING_RANDOM
#define RT_USING_RTC
#define RT_USING_SDIO
#define RT_SDIO_STACK_SIZE 4096
#define RT_SDIO_THREAD_PRIORITY 15
#define RT_MMCSD_STACK_SIZE 4096
#define RT_MMCSD_THREAD_PREORITY 22
#define RT_MMCSD_MAX_PARTITION 16
/* Using USB */
@ -137,12 +167,73 @@
/* Network */
#define RT_USING_SAL
#define SAL_INTERNET_CHECK
/* Docking with protocol stacks */
#define SAL_USING_LWIP
#define SAL_USING_POSIX
#define RT_USING_NETDEV
#define NETDEV_USING_IFCONFIG
#define NETDEV_USING_PING
#define NETDEV_USING_NETSTAT
#define NETDEV_USING_AUTO_DEFAULT
#define NETDEV_IPV4 1
#define NETDEV_IPV6 0
#define RT_USING_LWIP
#define RT_USING_LWIP212
#define RT_USING_LWIP_VER_NUM 0x20102
#define RT_LWIP_MEM_ALIGNMENT 64
#define RT_LWIP_IGMP
#define RT_LWIP_ICMP
#define RT_LWIP_DNS
/* Static IPv4 Address */
#define RT_LWIP_IPADDR "192.168.4.10"
#define RT_LWIP_GWADDR "192.168.4.1"
#define RT_LWIP_MSKADDR "255.255.255.0"
#define RT_LWIP_UDP
#define RT_LWIP_TCP
#define RT_LWIP_RAW
#define RT_MEMP_NUM_NETCONN 8
#define RT_LWIP_PBUF_NUM 512
#define RT_LWIP_RAW_PCB_NUM 4
#define RT_LWIP_UDP_PCB_NUM 4
#define RT_LWIP_TCP_PCB_NUM 4
#define RT_LWIP_TCP_SEG_NUM 40
#define RT_LWIP_TCP_SND_BUF 8196
#define RT_LWIP_TCP_WND 8196
#define RT_LWIP_TCPTHREAD_PRIORITY 12
#define RT_LWIP_TCPTHREAD_MBOX_SIZE 8
#define RT_LWIP_TCPTHREAD_STACKSIZE 16184
#define RT_LWIP_ETHTHREAD_PRIORITY 12
#define RT_LWIP_ETHTHREAD_STACKSIZE 2048
#define RT_LWIP_ETHTHREAD_MBOX_SIZE 8
#define LWIP_NETIF_STATUS_CALLBACK 1
#define LWIP_NETIF_LINK_CALLBACK 1
#define SO_REUSE 1
#define LWIP_SO_RCVTIMEO 1
#define LWIP_SO_SNDTIMEO 1
#define LWIP_SO_RCVBUF 1
#define LWIP_SO_LINGER 0
#define LWIP_NETIF_LOOPBACK 0
#define RT_LWIP_USING_PING
#define RT_LWIP_DEBUG
#define RT_LWIP_NETIF_DEBUG
/* Utilities */
#define RT_USING_RYM
#define YMODEM_USING_FILE_TRANSFER
#define RT_USING_RESOURCE_ID
#define RT_USING_ADT
#define RT_USING_ADT_AVL
#define RT_USING_ADT_BITMAP
#define RT_USING_ADT_HASHMAP
#define RT_USING_ADT_REF
#define RT_USING_KTIME
/* RT-Thread Utestcases */
@ -269,6 +360,11 @@
#define BSP_USING_UART
#define RT_USING_UART1
#define BSP_USING_ETH
#define RT_LWIP_PBUF_POOL_BUFSIZE 1700
#define BSP_USING_SDIO
#define BSP_USING_SDCARD_FATFS
#define USING_SDIO1
/* Board extended module Drivers */
@ -296,11 +392,22 @@
/* Qspi Configuration */
#define USE_FQSPI
#define USE_IOPAD
#define ENABLE_IOPAD
#define USE_SERIAL
/* Usart Configuration */
#define ENABLE_Pl011_UART
#define USE_ETH
/* Eth Configuration */
#define ENABLE_FXMAC
#define FXMAC_PHY_COMMON
/* Sdk common configuration */
#define LOG_ERROR
#endif

1273
bsp/phytium/aarch64/configs/e2000d_rtthread_test Normal file
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File diff suppressed because it is too large Load Diff

395
bsp/phytium/aarch64/configs/e2000d_rtthread_test.h Normal file
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@ -0,0 +1,395 @@
#ifndef RT_CONFIG_H__
#define RT_CONFIG_H__
/* Automatically generated file; DO NOT EDIT. */
/* RT-Thread Project Configuration */
/* RT-Thread Kernel */
#define RT_NAME_MAX 16
#define RT_USING_SMP
#define RT_CPUS_NR 2
#define RT_ALIGN_SIZE 4
#define RT_THREAD_PRIORITY_32
#define RT_THREAD_PRIORITY_MAX 32
#define RT_TICK_PER_SECOND 1000
#define RT_USING_OVERFLOW_CHECK
#define RT_USING_HOOK
#define RT_HOOK_USING_FUNC_PTR
#define RT_USING_IDLE_HOOK
#define RT_IDLE_HOOK_LIST_SIZE 4
#define IDLE_THREAD_STACK_SIZE 40960
#define SYSTEM_THREAD_STACK_SIZE 40960
#define RT_USING_TIMER_SOFT
#define RT_TIMER_THREAD_PRIO 4
#define RT_TIMER_THREAD_STACK_SIZE 4096
/* kservice optimization */
#define RT_KSERVICE_USING_STDLIB
#define RT_KPRINTF_USING_LONGLONG
#define RT_DEBUG
/* Inter-Thread communication */
#define RT_USING_SEMAPHORE
#define RT_USING_MUTEX
#define RT_USING_EVENT
#define RT_USING_MAILBOX
#define RT_USING_MESSAGEQUEUE
/* Memory Management */
#define RT_PAGE_MAX_ORDER 16
#define RT_USING_SLAB
#define RT_USING_MEMHEAP
#define RT_MEMHEAP_FAST_MODE
#define RT_USING_SLAB_AS_HEAP
#define RT_USING_HEAP_ISR
#define RT_USING_HEAP
/* Kernel Device Object */
#define RT_USING_DEVICE
#define RT_USING_CONSOLE
#define RT_CONSOLEBUF_SIZE 128
#define RT_CONSOLE_DEVICE_NAME "uart1"
#define RT_VER_NUM 0x50001
#define ARCH_CPU_64BIT
#define RT_USING_CACHE
#define ARCH_ARM_BOOTWITH_FLUSH_CACHE
#define ARCH_MM_MMU
#define ARCH_ARM
#define ARCH_ARM_MMU
#define ARCH_ARMV8
/* RT-Thread Components */
#define RT_USING_COMPONENTS_INIT
#define RT_USING_USER_MAIN
#define RT_MAIN_THREAD_STACK_SIZE 8192
#define RT_MAIN_THREAD_PRIORITY 10
#define RT_USING_MSH
#define RT_USING_FINSH
#define FINSH_USING_MSH
#define FINSH_THREAD_NAME "tshell"
#define FINSH_THREAD_PRIORITY 20
#define FINSH_THREAD_STACK_SIZE 4096
#define FINSH_USING_HISTORY
#define FINSH_HISTORY_LINES 5
#define FINSH_USING_SYMTAB
#define FINSH_CMD_SIZE 80
#define MSH_USING_BUILT_IN_COMMANDS
#define FINSH_USING_DESCRIPTION
#define FINSH_ARG_MAX 10
/* DFS: device virtual file system */
#define RT_USING_DFS
#define DFS_USING_POSIX
#define DFS_USING_WORKDIR
#define DFS_FD_MAX 16
#define RT_USING_DFS_V1
#define DFS_FILESYSTEMS_MAX 4
#define DFS_FILESYSTEM_TYPES_MAX 4
#define RT_USING_DFS_ELMFAT
/* elm-chan's FatFs, Generic FAT Filesystem Module */
#define RT_DFS_ELM_CODE_PAGE 437
#define RT_DFS_ELM_WORD_ACCESS
#define RT_DFS_ELM_USE_LFN_3
#define RT_DFS_ELM_USE_LFN 3
#define RT_DFS_ELM_LFN_UNICODE_0
#define RT_DFS_ELM_LFN_UNICODE 0
#define RT_DFS_ELM_MAX_LFN 255
#define RT_DFS_ELM_DRIVES 2
#define RT_DFS_ELM_MAX_SECTOR_SIZE 512
#define RT_DFS_ELM_REENTRANT
#define RT_DFS_ELM_MUTEX_TIMEOUT 3000
#define RT_USING_DFS_DEVFS
#define RT_USING_DFS_RAMFS
/* Device Drivers */
#define RT_USING_DEVICE_IPC
#define RT_UNAMED_PIPE_NUMBER 64
#define RT_USING_SYSTEM_WORKQUEUE
#define RT_SYSTEM_WORKQUEUE_STACKSIZE 8192
#define RT_SYSTEM_WORKQUEUE_PRIORITY 23
#define RT_USING_SERIAL
#define RT_USING_SERIAL_V1
#define RT_SERIAL_USING_DMA
#define RT_SERIAL_RB_BUFSZ 64
#define RT_USING_NULL
#define RT_USING_ZERO
#define RT_USING_RANDOM
#define RT_USING_RTC
#define RT_USING_SDIO
#define RT_SDIO_STACK_SIZE 4096
#define RT_SDIO_THREAD_PRIORITY 15
#define RT_MMCSD_STACK_SIZE 4096
#define RT_MMCSD_THREAD_PREORITY 22
#define RT_MMCSD_MAX_PARTITION 16
/* Using USB */
/* C/C++ and POSIX layer */
#define RT_LIBC_DEFAULT_TIMEZONE 8
/* POSIX (Portable Operating System Interface) layer */
#define RT_USING_POSIX_FS
#define RT_USING_POSIX_DEVIO
#define RT_USING_POSIX_STDIO
#define RT_USING_POSIX_TERMIOS
#define RT_USING_POSIX_DELAY
#define RT_USING_POSIX_CLOCK
#define RT_USING_POSIX_TIMER
/* Interprocess Communication (IPC) */
/* Socket is in the 'Network' category */
/* Network */
#define RT_USING_SAL
#define SAL_INTERNET_CHECK
/* Docking with protocol stacks */
#define SAL_USING_LWIP
#define SAL_USING_POSIX
#define RT_USING_NETDEV
#define NETDEV_USING_IFCONFIG
#define NETDEV_USING_PING
#define NETDEV_USING_NETSTAT
#define NETDEV_USING_AUTO_DEFAULT
#define NETDEV_IPV4 1
#define NETDEV_IPV6 0
#define RT_USING_LWIP
#define RT_USING_LWIP212
#define RT_USING_LWIP_VER_NUM 0x20102
#define RT_LWIP_MEM_ALIGNMENT 64
#define RT_LWIP_IGMP
#define RT_LWIP_ICMP
#define RT_LWIP_DNS
/* Static IPv4 Address */
#define RT_LWIP_IPADDR "192.168.4.10"
#define RT_LWIP_GWADDR "192.168.4.1"
#define RT_LWIP_MSKADDR "255.255.255.0"
#define RT_LWIP_UDP
#define RT_LWIP_TCP
#define RT_LWIP_RAW
#define RT_MEMP_NUM_NETCONN 8
#define RT_LWIP_PBUF_NUM 512
#define RT_LWIP_RAW_PCB_NUM 4
#define RT_LWIP_UDP_PCB_NUM 4
#define RT_LWIP_TCP_PCB_NUM 4
#define RT_LWIP_TCP_SEG_NUM 40
#define RT_LWIP_TCP_SND_BUF 8196
#define RT_LWIP_TCP_WND 8196
#define RT_LWIP_TCPTHREAD_PRIORITY 12
#define RT_LWIP_TCPTHREAD_MBOX_SIZE 8
#define RT_LWIP_TCPTHREAD_STACKSIZE 16184
#define RT_LWIP_ETHTHREAD_PRIORITY 12
#define RT_LWIP_ETHTHREAD_STACKSIZE 2048
#define RT_LWIP_ETHTHREAD_MBOX_SIZE 8
#define LWIP_NETIF_STATUS_CALLBACK 1
#define LWIP_NETIF_LINK_CALLBACK 1
#define SO_REUSE 1
#define LWIP_SO_RCVTIMEO 1
#define LWIP_SO_SNDTIMEO 1
#define LWIP_SO_RCVBUF 1
#define LWIP_SO_LINGER 0
#define LWIP_NETIF_LOOPBACK 0
#define RT_LWIP_USING_PING
#define RT_LWIP_DEBUG
#define RT_LWIP_NETIF_DEBUG
/* Utilities */
#define RT_USING_RYM
#define YMODEM_USING_FILE_TRANSFER
#define RT_USING_ADT
/* RT-Thread Utestcases */
/* RT-Thread online packages */
/* IoT - internet of things */
/* Wi-Fi */
/* Marvell WiFi */
/* Wiced WiFi */
/* IoT Cloud */
/* security packages */
/* language packages */
/* JSON: JavaScript Object Notation, a lightweight data-interchange format */
/* XML: Extensible Markup Language */
/* multimedia packages */
/* LVGL: powerful and easy-to-use embedded GUI library */
/* u8g2: a monochrome graphic library */
/* tools packages */
/* system packages */
/* enhanced kernel services */
/* acceleration: Assembly language or algorithmic acceleration packages */
/* CMSIS: ARM Cortex-M Microcontroller Software Interface Standard */
/* Micrium: Micrium software products porting for RT-Thread */
/* peripheral libraries and drivers */
/* sensors drivers */
/* touch drivers */
/* Kendryte SDK */
/* AI packages */
/* Signal Processing and Control Algorithm Packages */
/* miscellaneous packages */
/* project laboratory */
/* samples: kernel and components samples */
#define PKG_USING_KERNEL_SAMPLES
#define PKG_USING_KERNEL_SAMPLES_LATEST_VERSION
#define PKG_USING_KERNEL_SAMPLES_EN
/* entertainment: terminal games and other interesting software packages */
/* Arduino libraries */
/* Projects */
/* Sensors */
/* Display */
/* Timing */
/* Data Processing */
/* Data Storage */
/* Communication */
/* Device Control */
/* Other */
/* Signal IO */
/* Uncategorized */
/* Hardware Drivers */
/* On-chip Peripheral Drivers */
#define BSP_USING_UART
#define RT_USING_UART1
#define BSP_USING_ETH
#define RT_LWIP_PBUF_POOL_BUFSIZE 1700
#define BSP_USING_SDIO
#define BSP_USING_SDCARD_FATFS
#define USING_SDIO1
/* Board extended module Drivers */
#define BSP_USING_GIC
#define BSP_USING_GICV3
#define PHYTIUM_ARCH_AARCH64
#define ARM_SPI_BIND_CPU_ID 0
/* Standalone Setting */
#define TARGET_ARMV8_AARCH64
/* Board Configuration */
#define TARGET_E2000D
#define TARGET_E2000
#define DEFAULT_DEBUG_PRINT_UART1
/* Components Configuration */
#define USE_SPI
#define USE_FSPIM
#define USE_QSPI
/* Qspi Configuration */
#define USE_FQSPI
#define USE_IOPAD
#define ENABLE_IOPAD
#define USE_SERIAL
/* Usart Configuration */
#define ENABLE_Pl011_UART
#define USE_ETH
/* Eth Configuration */
#define ENABLE_FXMAC
#define FXMAC_PHY_COMMON
#define LOG_ERROR
#define PHYTIUM_RTT_TEST
#endif

178
bsp/phytium/aarch64/configs/e2000q_rtsmart
View File

@ -47,6 +47,7 @@ CONFIG_RT_DEBUG=y
# CONFIG_RT_DEBUG_MEM_CONFIG is not set
# CONFIG_RT_DEBUG_SLAB_CONFIG is not set
# CONFIG_RT_DEBUG_MEMHEAP_CONFIG is not set
# CONFIG_RT_DEBUG_PAGE_LEAK is not set
# CONFIG_RT_DEBUG_MODULE_CONFIG is not set
#
@ -62,20 +63,20 @@ CONFIG_RT_USING_MESSAGEQUEUE=y
#
# Memory Management
#
CONFIG_RT_PAGE_MAX_ORDER=11
CONFIG_RT_USING_MEMPOOL=y
CONFIG_RT_USING_SMALL_MEM=y
# CONFIG_RT_USING_SLAB is not set
CONFIG_RT_PAGE_MAX_ORDER=16
# CONFIG_RT_USING_MEMPOOL is not set
# CONFIG_RT_USING_SMALL_MEM is not set
CONFIG_RT_USING_SLAB=y
CONFIG_RT_USING_MEMHEAP=y
CONFIG_RT_MEMHEAP_FAST_MODE=y
# CONFIG_RT_MEMHEAP_BEST_MODE is not set
CONFIG_RT_USING_SMALL_MEM_AS_HEAP=y
# CONFIG_RT_USING_SMALL_MEM_AS_HEAP is not set
# CONFIG_RT_USING_MEMHEAP_AS_HEAP is not set
# CONFIG_RT_USING_SLAB_AS_HEAP is not set
CONFIG_RT_USING_SLAB_AS_HEAP=y
# CONFIG_RT_USING_USERHEAP is not set
# CONFIG_RT_USING_NOHEAP is not set
# CONFIG_RT_USING_MEMTRACE is not set
# CONFIG_RT_USING_HEAP_ISR is not set
CONFIG_RT_USING_HEAP_ISR=y
CONFIG_RT_USING_HEAP=y
#
@ -92,7 +93,7 @@ CONFIG_RT_VER_NUM=0x50001
# CONFIG_RT_USING_STDC_ATOMIC is not set
CONFIG_ARCH_CPU_64BIT=y
CONFIG_RT_USING_CACHE=y
CONFIG_RT_USING_HW_ATOMIC=y
# CONFIG_RT_USING_HW_ATOMIC is not set
CONFIG_ARCH_ARM_BOOTWITH_FLUSH_CACHE=y
# CONFIG_ARCH_CPU_STACK_GROWS_UPWARD is not set
# CONFIG_RT_USING_CPU_FFS is not set
@ -138,12 +139,35 @@ CONFIG_RT_USING_DFS_V1=y
# CONFIG_RT_USING_DFS_V2 is not set
CONFIG_DFS_FILESYSTEMS_MAX=4
CONFIG_DFS_FILESYSTEM_TYPES_MAX=4
# CONFIG_RT_USING_DFS_ELMFAT is not set
CONFIG_RT_USING_DFS_ELMFAT=y
#
# elm-chan's FatFs, Generic FAT Filesystem Module
#
CONFIG_RT_DFS_ELM_CODE_PAGE=437
CONFIG_RT_DFS_ELM_WORD_ACCESS=y
# CONFIG_RT_DFS_ELM_USE_LFN_0 is not set
# CONFIG_RT_DFS_ELM_USE_LFN_1 is not set
# CONFIG_RT_DFS_ELM_USE_LFN_2 is not set
CONFIG_RT_DFS_ELM_USE_LFN_3=y
CONFIG_RT_DFS_ELM_USE_LFN=3
CONFIG_RT_DFS_ELM_LFN_UNICODE_0=y
# CONFIG_RT_DFS_ELM_LFN_UNICODE_1 is not set
# CONFIG_RT_DFS_ELM_LFN_UNICODE_2 is not set
# CONFIG_RT_DFS_ELM_LFN_UNICODE_3 is not set
CONFIG_RT_DFS_ELM_LFN_UNICODE=0
CONFIG_RT_DFS_ELM_MAX_LFN=255
CONFIG_RT_DFS_ELM_DRIVES=2
CONFIG_RT_DFS_ELM_MAX_SECTOR_SIZE=512
# CONFIG_RT_DFS_ELM_USE_ERASE is not set
CONFIG_RT_DFS_ELM_REENTRANT=y
CONFIG_RT_DFS_ELM_MUTEX_TIMEOUT=3000
CONFIG_RT_USING_DFS_DEVFS=y
# CONFIG_RT_USING_DFS_ROMFS is not set
# CONFIG_RT_USING_DFS_CROMFS is not set
CONFIG_RT_USING_DFS_RAMFS=y
# CONFIG_RT_USING_DFS_TMPFS is not set
# CONFIG_RT_USING_DFS_NFS is not set
# CONFIG_RT_USING_FAL is not set
CONFIG_RT_USING_LWP=y
CONFIG_RT_LWP_MAX_NR=30
@ -188,7 +212,13 @@ CONFIG_RT_USING_RANDOM=y
CONFIG_RT_USING_RTC=y
# CONFIG_RT_USING_ALARM is not set
# CONFIG_RT_USING_SOFT_RTC is not set
# CONFIG_RT_USING_SDIO is not set
CONFIG_RT_USING_SDIO=y
CONFIG_RT_SDIO_STACK_SIZE=512
CONFIG_RT_SDIO_THREAD_PRIORITY=15
CONFIG_RT_MMCSD_STACK_SIZE=1024
CONFIG_RT_MMCSD_THREAD_PREORITY=22
CONFIG_RT_MMCSD_MAX_PARTITION=16
# CONFIG_RT_SDIO_DEBUG is not set
# CONFIG_RT_USING_SPI is not set
# CONFIG_RT_USING_WDT is not set
# CONFIG_RT_USING_AUDIO is not set
@ -247,9 +277,110 @@ CONFIG_RT_USING_POSIX_TIMER=y
#
# Network
#
# CONFIG_RT_USING_SAL is not set
# CONFIG_RT_USING_NETDEV is not set
# CONFIG_RT_USING_LWIP is not set
CONFIG_RT_USING_SAL=y
CONFIG_SAL_INTERNET_CHECK=y
#
# Docking with protocol stacks
#
CONFIG_SAL_USING_LWIP=y
# CONFIG_SAL_USING_AT is not set
# CONFIG_SAL_USING_TLS is not set
CONFIG_SAL_USING_POSIX=y
# CONFIG_SAL_USING_AF_UNIX is not set
CONFIG_RT_USING_NETDEV=y
CONFIG_NETDEV_USING_IFCONFIG=y
CONFIG_NETDEV_USING_PING=y
CONFIG_NETDEV_USING_NETSTAT=y
CONFIG_NETDEV_USING_AUTO_DEFAULT=y
# CONFIG_NETDEV_USING_IPV6 is not set
CONFIG_NETDEV_IPV4=1
CONFIG_NETDEV_IPV6=0
# CONFIG_NETDEV_IPV6_SCOPES is not set
CONFIG_RT_USING_LWIP=y
# CONFIG_RT_USING_LWIP_LOCAL_VERSION is not set
# CONFIG_RT_USING_LWIP141 is not set
# CONFIG_RT_USING_LWIP203 is not set
CONFIG_RT_USING_LWIP212=y
# CONFIG_RT_USING_LWIP_LATEST is not set
CONFIG_RT_USING_LWIP_VER_NUM=0x20102
# CONFIG_RT_USING_LWIP_IPV6 is not set
CONFIG_RT_LWIP_MEM_ALIGNMENT=64
CONFIG_RT_LWIP_IGMP=y
CONFIG_RT_LWIP_ICMP=y
# CONFIG_RT_LWIP_SNMP is not set
CONFIG_RT_LWIP_DNS=y
# CONFIG_RT_LWIP_DHCP is not set
#
# Static IPv4 Address
#
CONFIG_RT_LWIP_IPADDR="192.168.4.10"
CONFIG_RT_LWIP_GWADDR="192.168.4.1"
CONFIG_RT_LWIP_MSKADDR="255.255.255.0"
CONFIG_RT_LWIP_UDP=y
CONFIG_RT_LWIP_TCP=y
CONFIG_RT_LWIP_RAW=y
# CONFIG_RT_LWIP_PPP is not set
CONFIG_RT_MEMP_NUM_NETCONN=8
CONFIG_RT_LWIP_PBUF_NUM=512
CONFIG_RT_LWIP_RAW_PCB_NUM=4
CONFIG_RT_LWIP_UDP_PCB_NUM=4
CONFIG_RT_LWIP_TCP_PCB_NUM=4
CONFIG_RT_LWIP_TCP_SEG_NUM=40
CONFIG_RT_LWIP_TCP_SND_BUF=8196
CONFIG_RT_LWIP_TCP_WND=8196
CONFIG_RT_LWIP_TCPTHREAD_PRIORITY=12
CONFIG_RT_LWIP_TCPTHREAD_MBOX_SIZE=8
CONFIG_RT_LWIP_TCPTHREAD_STACKSIZE=16184
# CONFIG_LWIP_NO_RX_THREAD is not set
# CONFIG_LWIP_NO_TX_THREAD is not set
CONFIG_RT_LWIP_ETHTHREAD_PRIORITY=12
CONFIG_RT_LWIP_ETHTHREAD_STACKSIZE=2048
CONFIG_RT_LWIP_ETHTHREAD_MBOX_SIZE=8
# CONFIG_RT_LWIP_REASSEMBLY_FRAG is not set
CONFIG_LWIP_NETIF_STATUS_CALLBACK=1
CONFIG_LWIP_NETIF_LINK_CALLBACK=1
CONFIG_SO_REUSE=1
CONFIG_LWIP_SO_RCVTIMEO=1
CONFIG_LWIP_SO_SNDTIMEO=1
CONFIG_LWIP_SO_RCVBUF=1
CONFIG_LWIP_SO_LINGER=0
# CONFIG_RT_LWIP_NETIF_LOOPBACK is not set
CONFIG_LWIP_NETIF_LOOPBACK=0
# CONFIG_RT_LWIP_STATS is not set
# CONFIG_RT_LWIP_USING_HW_CHECKSUM is not set
CONFIG_RT_LWIP_USING_PING=y
# CONFIG_LWIP_USING_DHCPD is not set
CONFIG_RT_LWIP_DEBUG=y
# CONFIG_RT_LWIP_SYS_DEBUG is not set
# CONFIG_RT_LWIP_ETHARP_DEBUG is not set
# CONFIG_RT_LWIP_PPP_DEBUG is not set
# CONFIG_RT_LWIP_MEM_DEBUG is not set
# CONFIG_RT_LWIP_MEMP_DEBUG is not set
# CONFIG_RT_LWIP_PBUF_DEBUG is not set
# CONFIG_RT_LWIP_API_LIB_DEBUG is not set
# CONFIG_RT_LWIP_API_MSG_DEBUG is not set
# CONFIG_RT_LWIP_TCPIP_DEBUG is not set
CONFIG_RT_LWIP_NETIF_DEBUG=y
# CONFIG_RT_LWIP_SOCKETS_DEBUG is not set
# CONFIG_RT_LWIP_DNS_DEBUG is not set
# CONFIG_RT_LWIP_AUTOIP_DEBUG is not set
# CONFIG_RT_LWIP_DHCP_DEBUG is not set
# CONFIG_RT_LWIP_IP_DEBUG is not set
# CONFIG_RT_LWIP_IP_REASS_DEBUG is not set
# CONFIG_RT_LWIP_ICMP_DEBUG is not set
# CONFIG_RT_LWIP_IGMP_DEBUG is not set
# CONFIG_RT_LWIP_UDP_DEBUG is not set
# CONFIG_RT_LWIP_TCP_DEBUG is not set
# CONFIG_RT_LWIP_TCP_INPUT_DEBUG is not set
# CONFIG_RT_LWIP_TCP_OUTPUT_DEBUG is not set
# CONFIG_RT_LWIP_TCP_RTO_DEBUG is not set
# CONFIG_RT_LWIP_TCP_CWND_DEBUG is not set
# CONFIG_RT_LWIP_TCP_WND_DEBUG is not set
# CONFIG_RT_LWIP_TCP_FR_DEBUG is not set
# CONFIG_RT_LWIP_TCP_QLEN_DEBUG is not set
# CONFIG_RT_LWIP_TCP_RST_DEBUG is not set
# CONFIG_RT_USING_AT is not set
#
@ -1052,7 +1183,15 @@ CONFIG_RT_USING_UART1=y
# CONFIG_RT_USING_UART0 is not set
# CONFIG_BSP_USING_SPI is not set
# CONFIG_BSP_USING_CAN is not set
# CONFIG_BSP_USING_GPIO is not set
# CONFIG_BSP_USING_QSPI is not set
CONFIG_BSP_USING_ETH=y
CONFIG_RT_LWIP_PBUF_POOL_BUFSIZE=1700
CONFIG_BSP_USING_SDIO=y
CONFIG_BSP_USING_SDCARD_FATFS=y
# CONFIG_USING_SDIO0 is not set
CONFIG_USING_SDIO1=y
# CONFIG_USING_EMMC is not set
#
# Board extended module Drivers
@ -1092,6 +1231,8 @@ CONFIG_USE_QSPI=y
#
CONFIG_USE_FQSPI=y
# CONFIG_USE_GIC is not set
CONFIG_USE_IOPAD=y
CONFIG_ENABLE_IOPAD=y
CONFIG_USE_SERIAL=y
#
@ -1099,7 +1240,15 @@ CONFIG_USE_SERIAL=y
#
CONFIG_ENABLE_Pl011_UART=y
# CONFIG_USE_GPIO is not set
# CONFIG_USE_ETH is not set
CONFIG_USE_ETH=y
#
# Eth Configuration
#
CONFIG_ENABLE_FXMAC=y
# CONFIG_ENABLE_FGMAC is not set
CONFIG_FXMAC_PHY_COMMON=y
# CONFIG_FXMAC_PHY_YT is not set
# CONFIG_USE_CAN is not set
# CONFIG_USE_I2C is not set
# CONFIG_USE_TIMER is not set
@ -1127,3 +1276,4 @@ CONFIG_LOG_ERROR=y
# CONFIG_LOG_EXTRA_INFO is not set
# CONFIG_LOG_DISPALY_CORE_NUM is not set
# CONFIG_BOOTUP_DEBUG_PRINTS is not set
# CONFIG_PHYTIUM_RTT_TEST is not set

100
bsp/phytium/aarch64/configs/e2000q_rtsmart.h
View File

@ -29,7 +29,7 @@
#define RT_KSERVICE_USING_STDLIB
#define RT_KPRINTF_USING_LONGLONG
#define RT_USING_DEBUG
#define RT_DEBUG
/* Inter-Thread communication */
@ -41,12 +41,12 @@
/* Memory Management */
#define RT_PAGE_MAX_ORDER 11
#define RT_USING_MEMPOOL
#define RT_USING_SMALL_MEM
#define RT_PAGE_MAX_ORDER 16
#define RT_USING_SLAB
#define RT_USING_MEMHEAP
#define RT_MEMHEAP_FAST_MODE
#define RT_USING_SMALL_MEM_AS_HEAP
#define RT_USING_SLAB_AS_HEAP
#define RT_USING_HEAP_ISR
#define RT_USING_HEAP
/* Kernel Device Object */
@ -58,7 +58,6 @@
#define RT_VER_NUM 0x50001
#define ARCH_CPU_64BIT
#define RT_USING_CACHE
#define RT_USING_HW_ATOMIC
#define ARCH_ARM_BOOTWITH_FLUSH_CACHE
#define ARCH_MM_MMU
#define ARCH_ARM
@ -95,6 +94,21 @@
#define RT_USING_DFS_V1
#define DFS_FILESYSTEMS_MAX 4
#define DFS_FILESYSTEM_TYPES_MAX 4
#define RT_USING_DFS_ELMFAT
/* elm-chan's FatFs, Generic FAT Filesystem Module */
#define RT_DFS_ELM_CODE_PAGE 437
#define RT_DFS_ELM_WORD_ACCESS
#define RT_DFS_ELM_USE_LFN_3
#define RT_DFS_ELM_USE_LFN 3
#define RT_DFS_ELM_LFN_UNICODE_0
#define RT_DFS_ELM_LFN_UNICODE 0
#define RT_DFS_ELM_MAX_LFN 255
#define RT_DFS_ELM_DRIVES 2
#define RT_DFS_ELM_MAX_SECTOR_SIZE 512
#define RT_DFS_ELM_REENTRANT
#define RT_DFS_ELM_MUTEX_TIMEOUT 3000
#define RT_USING_DFS_DEVFS
#define RT_USING_DFS_RAMFS
#define RT_USING_LWP
@ -121,6 +135,12 @@
#define RT_USING_ZERO
#define RT_USING_RANDOM
#define RT_USING_RTC
#define RT_USING_SDIO
#define RT_SDIO_STACK_SIZE 512
#define RT_SDIO_THREAD_PRIORITY 15
#define RT_MMCSD_STACK_SIZE 1024
#define RT_MMCSD_THREAD_PREORITY 22
#define RT_MMCSD_MAX_PARTITION 16
/* Using USB */
@ -147,6 +167,61 @@
/* Network */
#define RT_USING_SAL
#define SAL_INTERNET_CHECK
/* Docking with protocol stacks */
#define SAL_USING_LWIP
#define SAL_USING_POSIX
#define RT_USING_NETDEV
#define NETDEV_USING_IFCONFIG
#define NETDEV_USING_PING
#define NETDEV_USING_NETSTAT
#define NETDEV_USING_AUTO_DEFAULT
#define NETDEV_IPV4 1
#define NETDEV_IPV6 0
#define RT_USING_LWIP
#define RT_USING_LWIP212
#define RT_USING_LWIP_VER_NUM 0x20102
#define RT_LWIP_MEM_ALIGNMENT 64
#define RT_LWIP_IGMP
#define RT_LWIP_ICMP
#define RT_LWIP_DNS
/* Static IPv4 Address */
#define RT_LWIP_IPADDR "192.168.4.10"
#define RT_LWIP_GWADDR "192.168.4.1"
#define RT_LWIP_MSKADDR "255.255.255.0"
#define RT_LWIP_UDP
#define RT_LWIP_TCP
#define RT_LWIP_RAW
#define RT_MEMP_NUM_NETCONN 8
#define RT_LWIP_PBUF_NUM 512
#define RT_LWIP_RAW_PCB_NUM 4
#define RT_LWIP_UDP_PCB_NUM 4
#define RT_LWIP_TCP_PCB_NUM 4
#define RT_LWIP_TCP_SEG_NUM 40
#define RT_LWIP_TCP_SND_BUF 8196
#define RT_LWIP_TCP_WND 8196
#define RT_LWIP_TCPTHREAD_PRIORITY 12
#define RT_LWIP_TCPTHREAD_MBOX_SIZE 8
#define RT_LWIP_TCPTHREAD_STACKSIZE 16184
#define RT_LWIP_ETHTHREAD_PRIORITY 12
#define RT_LWIP_ETHTHREAD_STACKSIZE 2048
#define RT_LWIP_ETHTHREAD_MBOX_SIZE 8
#define LWIP_NETIF_STATUS_CALLBACK 1
#define LWIP_NETIF_LINK_CALLBACK 1
#define SO_REUSE 1
#define LWIP_SO_RCVTIMEO 1
#define LWIP_SO_SNDTIMEO 1
#define LWIP_SO_RCVBUF 1
#define LWIP_SO_LINGER 0
#define LWIP_NETIF_LOOPBACK 0
#define RT_LWIP_USING_PING
#define RT_LWIP_DEBUG
#define RT_LWIP_NETIF_DEBUG
/* Utilities */
@ -279,6 +354,11 @@
#define BSP_USING_UART
#define RT_USING_UART1
#define BSP_USING_ETH
#define RT_LWIP_PBUF_POOL_BUFSIZE 1700
#define BSP_USING_SDIO
#define BSP_USING_SDCARD_FATFS
#define USING_SDIO1
/* Board extended module Drivers */
@ -306,11 +386,19 @@
/* Qspi Configuration */
#define USE_FQSPI
#define USE_IOPAD
#define ENABLE_IOPAD
#define USE_SERIAL
/* Usart Configuration */
#define ENABLE_Pl011_UART
#define USE_ETH
/* Eth Configuration */
#define ENABLE_FXMAC
#define FXMAC_PHY_COMMON
#define LOG_ERROR
#endif

1284
bsp/phytium/aarch64/configs/e2000q_rtsmart_test Normal file
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File diff suppressed because it is too large Load Diff

405
bsp/phytium/aarch64/configs/e2000q_rtsmart_test.h Normal file
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@ -0,0 +1,405 @@
#ifndef RT_CONFIG_H__
#define RT_CONFIG_H__
/* Automatically generated file; DO NOT EDIT. */
/* RT-Thread Project Configuration */
/* RT-Thread Kernel */
#define RT_NAME_MAX 16
#define RT_USING_SMART
#define RT_USING_SMP
#define RT_CPUS_NR 4
#define RT_ALIGN_SIZE 4
#define RT_THREAD_PRIORITY_32
#define RT_THREAD_PRIORITY_MAX 32
#define RT_TICK_PER_SECOND 1000
#define RT_USING_OVERFLOW_CHECK
#define RT_USING_HOOK
#define RT_HOOK_USING_FUNC_PTR
#define RT_USING_IDLE_HOOK
#define RT_IDLE_HOOK_LIST_SIZE 4
#define IDLE_THREAD_STACK_SIZE 40960
#define SYSTEM_THREAD_STACK_SIZE 40960
#define RT_USING_TIMER_SOFT
#define RT_TIMER_THREAD_PRIO 4
#define RT_TIMER_THREAD_STACK_SIZE 4096
/* kservice optimization */
#define RT_KSERVICE_USING_STDLIB
#define RT_KPRINTF_USING_LONGLONG
#define RT_DEBUG
/* Inter-Thread communication */
#define RT_USING_SEMAPHORE
#define RT_USING_MUTEX
#define RT_USING_EVENT
#define RT_USING_MAILBOX
#define RT_USING_MESSAGEQUEUE
/* Memory Management */
#define RT_PAGE_MAX_ORDER 16
#define RT_USING_SLAB
#define RT_USING_MEMHEAP
#define RT_MEMHEAP_FAST_MODE
#define RT_USING_SLAB_AS_HEAP
#define RT_USING_HEAP_ISR
#define RT_USING_HEAP
/* Kernel Device Object */
#define RT_USING_DEVICE
#define RT_USING_CONSOLE
#define RT_CONSOLEBUF_SIZE 128
#define RT_CONSOLE_DEVICE_NAME "uart1"
#define RT_VER_NUM 0x50001
#define ARCH_CPU_64BIT
#define RT_USING_CACHE
#define ARCH_ARM_BOOTWITH_FLUSH_CACHE
#define ARCH_MM_MMU
#define ARCH_ARM
#define ARCH_ARM_MMU
#define KERNEL_VADDR_START 0xffff000000000000
#define ARCH_ARMV8
/* RT-Thread Components */
#define RT_USING_COMPONENTS_INIT
#define RT_USING_USER_MAIN
#define RT_MAIN_THREAD_STACK_SIZE 8192
#define RT_MAIN_THREAD_PRIORITY 10
#define RT_USING_MSH
#define RT_USING_FINSH
#define FINSH_USING_MSH
#define FINSH_THREAD_NAME "tshell"
#define FINSH_THREAD_PRIORITY 20
#define FINSH_THREAD_STACK_SIZE 4096
#define FINSH_USING_HISTORY
#define FINSH_HISTORY_LINES 5
#define FINSH_USING_SYMTAB
#define FINSH_CMD_SIZE 80
#define MSH_USING_BUILT_IN_COMMANDS
#define FINSH_USING_DESCRIPTION
#define FINSH_ARG_MAX 10
/* DFS: device virtual file system */
#define RT_USING_DFS
#define DFS_USING_POSIX
#define DFS_USING_WORKDIR
#define DFS_FD_MAX 16
#define RT_USING_DFS_V1
#define DFS_FILESYSTEMS_MAX 4
#define DFS_FILESYSTEM_TYPES_MAX 4
#define RT_USING_DFS_ELMFAT
/* elm-chan's FatFs, Generic FAT Filesystem Module */
#define RT_DFS_ELM_CODE_PAGE 437
#define RT_DFS_ELM_WORD_ACCESS
#define RT_DFS_ELM_USE_LFN_3
#define RT_DFS_ELM_USE_LFN 3
#define RT_DFS_ELM_LFN_UNICODE_0
#define RT_DFS_ELM_LFN_UNICODE 0
#define RT_DFS_ELM_MAX_LFN 255
#define RT_DFS_ELM_DRIVES 2
#define RT_DFS_ELM_MAX_SECTOR_SIZE 512
#define RT_DFS_ELM_REENTRANT
#define RT_DFS_ELM_MUTEX_TIMEOUT 3000
#define RT_USING_DFS_DEVFS
#define RT_USING_DFS_RAMFS
#define RT_USING_LWP
#define RT_LWP_MAX_NR 30
#define LWP_TASK_STACK_SIZE 16384
#define RT_CH_MSG_MAX_NR 1024
#define LWP_CONSOLE_INPUT_BUFFER_SIZE 1024
#define LWP_TID_MAX_NR 64
#define RT_LWP_SHM_MAX_NR 64
/* Device Drivers */
#define RT_USING_DEVICE_IPC
#define RT_UNAMED_PIPE_NUMBER 64
#define RT_USING_SYSTEM_WORKQUEUE
#define RT_SYSTEM_WORKQUEUE_STACKSIZE 8192
#define RT_SYSTEM_WORKQUEUE_PRIORITY 23
#define RT_USING_SERIAL
#define RT_USING_SERIAL_V1
#define RT_SERIAL_USING_DMA
#define RT_SERIAL_RB_BUFSZ 64
#define RT_USING_TTY
#define RT_USING_NULL
#define RT_USING_ZERO
#define RT_USING_RANDOM
#define RT_USING_RTC
#define RT_USING_SDIO
#define RT_SDIO_STACK_SIZE 512
#define RT_SDIO_THREAD_PRIORITY 15
#define RT_MMCSD_STACK_SIZE 1024
#define RT_MMCSD_THREAD_PREORITY 22
#define RT_MMCSD_MAX_PARTITION 16
/* Using USB */
/* C/C++ and POSIX layer */
#define RT_LIBC_DEFAULT_TIMEZONE 8
/* POSIX (Portable Operating System Interface) layer */
#define RT_USING_POSIX_FS
#define RT_USING_POSIX_DEVIO
#define RT_USING_POSIX_STDIO
#define RT_USING_POSIX_TERMIOS
#define RT_USING_POSIX_DELAY
#define RT_USING_POSIX_CLOCK
#define RT_USING_POSIX_TIMER
/* Interprocess Communication (IPC) */
/* Socket is in the 'Network' category */
/* Network */
#define RT_USING_SAL
#define SAL_INTERNET_CHECK
/* Docking with protocol stacks */
#define SAL_USING_LWIP
#define SAL_USING_POSIX
#define RT_USING_NETDEV
#define NETDEV_USING_IFCONFIG
#define NETDEV_USING_PING
#define NETDEV_USING_NETSTAT
#define NETDEV_USING_AUTO_DEFAULT
#define NETDEV_IPV4 1
#define NETDEV_IPV6 0
#define RT_USING_LWIP
#define RT_USING_LWIP212
#define RT_USING_LWIP_VER_NUM 0x20102
#define RT_LWIP_MEM_ALIGNMENT 64
#define RT_LWIP_IGMP
#define RT_LWIP_ICMP
#define RT_LWIP_DNS
/* Static IPv4 Address */
#define RT_LWIP_IPADDR "192.168.4.10"
#define RT_LWIP_GWADDR "192.168.4.1"
#define RT_LWIP_MSKADDR "255.255.255.0"
#define RT_LWIP_UDP
#define RT_LWIP_TCP
#define RT_LWIP_RAW
#define RT_MEMP_NUM_NETCONN 8
#define RT_LWIP_PBUF_NUM 512
#define RT_LWIP_RAW_PCB_NUM 4
#define RT_LWIP_UDP_PCB_NUM 4
#define RT_LWIP_TCP_PCB_NUM 4
#define RT_LWIP_TCP_SEG_NUM 40
#define RT_LWIP_TCP_SND_BUF 8196
#define RT_LWIP_TCP_WND 8196
#define RT_LWIP_TCPTHREAD_PRIORITY 12
#define RT_LWIP_TCPTHREAD_MBOX_SIZE 8
#define RT_LWIP_TCPTHREAD_STACKSIZE 16184
#define RT_LWIP_ETHTHREAD_PRIORITY 12
#define RT_LWIP_ETHTHREAD_STACKSIZE 2048
#define RT_LWIP_ETHTHREAD_MBOX_SIZE 8
#define LWIP_NETIF_STATUS_CALLBACK 1
#define LWIP_NETIF_LINK_CALLBACK 1
#define SO_REUSE 1
#define LWIP_SO_RCVTIMEO 1
#define LWIP_SO_SNDTIMEO 1
#define LWIP_SO_RCVBUF 1
#define LWIP_SO_LINGER 0
#define LWIP_NETIF_LOOPBACK 0
#define RT_LWIP_USING_PING
#define RT_LWIP_DEBUG
#define RT_LWIP_NETIF_DEBUG
/* Utilities */
#define RT_USING_RYM
#define YMODEM_USING_FILE_TRANSFER
#define RT_USING_ADT
/* RT-Thread Utestcases */
/* RT-Thread online packages */
/* IoT - internet of things */
/* Wi-Fi */
/* Marvell WiFi */
/* Wiced WiFi */
/* IoT Cloud */
/* security packages */
/* language packages */
/* JSON: JavaScript Object Notation, a lightweight data-interchange format */
/* XML: Extensible Markup Language */
/* multimedia packages */
/* LVGL: powerful and easy-to-use embedded GUI library */
/* u8g2: a monochrome graphic library */
/* tools packages */
/* system packages */
/* enhanced kernel services */
/* acceleration: Assembly language or algorithmic acceleration packages */
/* CMSIS: ARM Cortex-M Microcontroller Software Interface Standard */
/* Micrium: Micrium software products porting for RT-Thread */
/* peripheral libraries and drivers */
/* sensors drivers */
/* touch drivers */
/* Kendryte SDK */
/* AI packages */
/* Signal Processing and Control Algorithm Packages */
/* miscellaneous packages */
/* project laboratory */
/* samples: kernel and components samples */
#define PKG_USING_KERNEL_SAMPLES
#define PKG_USING_KERNEL_SAMPLES_LATEST_VERSION
#define PKG_USING_KERNEL_SAMPLES_EN
/* entertainment: terminal games and other interesting software packages */
/* Arduino libraries */
/* Projects */
/* Sensors */
/* Display */
/* Timing */
/* Data Processing */
/* Data Storage */
/* Communication */
/* Device Control */
/* Other */
/* Signal IO */
/* Uncategorized */
/* Hardware Drivers */
/* On-chip Peripheral Drivers */
#define BSP_USING_UART
#define RT_USING_UART1
#define BSP_USING_ETH
#define RT_LWIP_PBUF_POOL_BUFSIZE 1700
#define BSP_USING_SDIO
#define BSP_USING_SDCARD_FATFS
#define USING_SDIO1
/* Board extended module Drivers */
#define BSP_USING_GIC
#define BSP_USING_GICV3
#define PHYTIUM_ARCH_AARCH64
#define ARM_SPI_BIND_CPU_ID 2
/* Standalone Setting */
#define TARGET_ARMV8_AARCH64
/* Board Configuration */
#define TARGET_E2000Q
#define TARGET_E2000
#define DEFAULT_DEBUG_PRINT_UART1
/* Components Configuration */
#define USE_SPI
#define USE_FSPIM
#define USE_QSPI
/* Qspi Configuration */
#define USE_FQSPI
#define USE_IOPAD
#define ENABLE_IOPAD
#define USE_SERIAL
/* Usart Configuration */
#define ENABLE_Pl011_UART
#define USE_ETH
/* Eth Configuration */
#define ENABLE_FXMAC
#define FXMAC_PHY_COMMON
#define LOG_ERROR
#define PHYTIUM_RTT_TEST
#endif

167
bsp/phytium/aarch64/configs/e2000q_rtthread
View File

@ -10,7 +10,7 @@ CONFIG_RT_NAME_MAX=16
# CONFIG_RT_USING_ARCH_DATA_TYPE is not set
# CONFIG_RT_USING_SMART is not set
CONFIG_RT_USING_SMP=y
CONFIG_RT_CPUS_NR=4
CONFIG_RT_CPUS_NR=2
CONFIG_RT_ALIGN_SIZE=4
# CONFIG_RT_THREAD_PRIORITY_8 is not set
CONFIG_RT_THREAD_PRIORITY_32=y
@ -47,6 +47,7 @@ CONFIG_RT_DEBUG=y
# CONFIG_RT_DEBUG_MEM_CONFIG is not set
# CONFIG_RT_DEBUG_SLAB_CONFIG is not set
# CONFIG_RT_DEBUG_MEMHEAP_CONFIG is not set
# CONFIG_RT_DEBUG_PAGE_LEAK is not set
# CONFIG_RT_DEBUG_MODULE_CONFIG is not set
#
@ -62,20 +63,20 @@ CONFIG_RT_USING_MESSAGEQUEUE=y
#
# Memory Management
#
CONFIG_RT_PAGE_MAX_ORDER=11
CONFIG_RT_USING_MEMPOOL=y
CONFIG_RT_USING_SMALL_MEM=y
# CONFIG_RT_USING_SLAB is not set
CONFIG_RT_PAGE_MAX_ORDER=16
# CONFIG_RT_USING_MEMPOOL is not set
# CONFIG_RT_USING_SMALL_MEM is not set
CONFIG_RT_USING_SLAB=y
CONFIG_RT_USING_MEMHEAP=y
CONFIG_RT_MEMHEAP_FAST_MODE=y
# CONFIG_RT_MEMHEAP_BEST_MODE is not set
CONFIG_RT_USING_SMALL_MEM_AS_HEAP=y
# CONFIG_RT_USING_SMALL_MEM_AS_HEAP is not set
# CONFIG_RT_USING_MEMHEAP_AS_HEAP is not set
# CONFIG_RT_USING_SLAB_AS_HEAP is not set
CONFIG_RT_USING_SLAB_AS_HEAP=y
# CONFIG_RT_USING_USERHEAP is not set
# CONFIG_RT_USING_NOHEAP is not set
# CONFIG_RT_USING_MEMTRACE is not set
# CONFIG_RT_USING_HEAP_ISR is not set
CONFIG_RT_USING_HEAP_ISR=y
CONFIG_RT_USING_HEAP=y
#
@ -92,7 +93,7 @@ CONFIG_RT_VER_NUM=0x50001
# CONFIG_RT_USING_STDC_ATOMIC is not set
CONFIG_ARCH_CPU_64BIT=y
CONFIG_RT_USING_CACHE=y
CONFIG_RT_USING_HW_ATOMIC=y
# CONFIG_RT_USING_HW_ATOMIC is not set
CONFIG_ARCH_ARM_BOOTWITH_FLUSH_CACHE=y
# CONFIG_ARCH_CPU_STACK_GROWS_UPWARD is not set
# CONFIG_RT_USING_CPU_FFS is not set
@ -137,12 +138,35 @@ CONFIG_RT_USING_DFS_V1=y
# CONFIG_RT_USING_DFS_V2 is not set
CONFIG_DFS_FILESYSTEMS_MAX=4
CONFIG_DFS_FILESYSTEM_TYPES_MAX=4
# CONFIG_RT_USING_DFS_ELMFAT is not set
CONFIG_RT_USING_DFS_ELMFAT=y
#
# elm-chan's FatFs, Generic FAT Filesystem Module
#
CONFIG_RT_DFS_ELM_CODE_PAGE=437
CONFIG_RT_DFS_ELM_WORD_ACCESS=y
# CONFIG_RT_DFS_ELM_USE_LFN_0 is not set
# CONFIG_RT_DFS_ELM_USE_LFN_1 is not set
# CONFIG_RT_DFS_ELM_USE_LFN_2 is not set
CONFIG_RT_DFS_ELM_USE_LFN_3=y
CONFIG_RT_DFS_ELM_USE_LFN=3
CONFIG_RT_DFS_ELM_LFN_UNICODE_0=y
# CONFIG_RT_DFS_ELM_LFN_UNICODE_1 is not set
# CONFIG_RT_DFS_ELM_LFN_UNICODE_2 is not set
# CONFIG_RT_DFS_ELM_LFN_UNICODE_3 is not set
CONFIG_RT_DFS_ELM_LFN_UNICODE=0
CONFIG_RT_DFS_ELM_MAX_LFN=255
CONFIG_RT_DFS_ELM_DRIVES=2
CONFIG_RT_DFS_ELM_MAX_SECTOR_SIZE=512
# CONFIG_RT_DFS_ELM_USE_ERASE is not set
CONFIG_RT_DFS_ELM_REENTRANT=y
CONFIG_RT_DFS_ELM_MUTEX_TIMEOUT=3000
CONFIG_RT_USING_DFS_DEVFS=y
# CONFIG_RT_USING_DFS_ROMFS is not set
# CONFIG_RT_USING_DFS_CROMFS is not set
CONFIG_RT_USING_DFS_RAMFS=y
# CONFIG_RT_USING_DFS_TMPFS is not set
# CONFIG_RT_USING_DFS_NFS is not set
# CONFIG_RT_USING_FAL is not set
#
@ -236,9 +260,110 @@ CONFIG_RT_USING_POSIX_TIMER=y
#
# Network
#
# CONFIG_RT_USING_SAL is not set
# CONFIG_RT_USING_NETDEV is not set
# CONFIG_RT_USING_LWIP is not set
CONFIG_RT_USING_SAL=y
CONFIG_SAL_INTERNET_CHECK=y
#
# Docking with protocol stacks
#
CONFIG_SAL_USING_LWIP=y
# CONFIG_SAL_USING_AT is not set
# CONFIG_SAL_USING_TLS is not set
CONFIG_SAL_USING_POSIX=y
# CONFIG_SAL_USING_AF_UNIX is not set
CONFIG_RT_USING_NETDEV=y
CONFIG_NETDEV_USING_IFCONFIG=y
CONFIG_NETDEV_USING_PING=y
CONFIG_NETDEV_USING_NETSTAT=y
CONFIG_NETDEV_USING_AUTO_DEFAULT=y
# CONFIG_NETDEV_USING_IPV6 is not set
CONFIG_NETDEV_IPV4=1
CONFIG_NETDEV_IPV6=0
# CONFIG_NETDEV_IPV6_SCOPES is not set
CONFIG_RT_USING_LWIP=y
# CONFIG_RT_USING_LWIP_LOCAL_VERSION is not set
# CONFIG_RT_USING_LWIP141 is not set
# CONFIG_RT_USING_LWIP203 is not set
CONFIG_RT_USING_LWIP212=y
# CONFIG_RT_USING_LWIP_LATEST is not set
CONFIG_RT_USING_LWIP_VER_NUM=0x20102
# CONFIG_RT_USING_LWIP_IPV6 is not set
CONFIG_RT_LWIP_MEM_ALIGNMENT=64
CONFIG_RT_LWIP_IGMP=y
CONFIG_RT_LWIP_ICMP=y
# CONFIG_RT_LWIP_SNMP is not set
CONFIG_RT_LWIP_DNS=y
# CONFIG_RT_LWIP_DHCP is not set
#
# Static IPv4 Address
#
CONFIG_RT_LWIP_IPADDR="192.168.4.10"
CONFIG_RT_LWIP_GWADDR="192.168.4.1"
CONFIG_RT_LWIP_MSKADDR="255.255.255.0"
CONFIG_RT_LWIP_UDP=y
CONFIG_RT_LWIP_TCP=y
CONFIG_RT_LWIP_RAW=y
# CONFIG_RT_LWIP_PPP is not set
CONFIG_RT_MEMP_NUM_NETCONN=8
CONFIG_RT_LWIP_PBUF_NUM=512
CONFIG_RT_LWIP_RAW_PCB_NUM=4
CONFIG_RT_LWIP_UDP_PCB_NUM=4
CONFIG_RT_LWIP_TCP_PCB_NUM=4
CONFIG_RT_LWIP_TCP_SEG_NUM=40
CONFIG_RT_LWIP_TCP_SND_BUF=8196
CONFIG_RT_LWIP_TCP_WND=8196
CONFIG_RT_LWIP_TCPTHREAD_PRIORITY=12
CONFIG_RT_LWIP_TCPTHREAD_MBOX_SIZE=8
CONFIG_RT_LWIP_TCPTHREAD_STACKSIZE=16184
# CONFIG_LWIP_NO_RX_THREAD is not set
# CONFIG_LWIP_NO_TX_THREAD is not set
CONFIG_RT_LWIP_ETHTHREAD_PRIORITY=12
CONFIG_RT_LWIP_ETHTHREAD_STACKSIZE=2048
CONFIG_RT_LWIP_ETHTHREAD_MBOX_SIZE=8
# CONFIG_RT_LWIP_REASSEMBLY_FRAG is not set
CONFIG_LWIP_NETIF_STATUS_CALLBACK=1
CONFIG_LWIP_NETIF_LINK_CALLBACK=1
CONFIG_SO_REUSE=1
CONFIG_LWIP_SO_RCVTIMEO=1
CONFIG_LWIP_SO_SNDTIMEO=1
CONFIG_LWIP_SO_RCVBUF=1
CONFIG_LWIP_SO_LINGER=0
# CONFIG_RT_LWIP_NETIF_LOOPBACK is not set
CONFIG_LWIP_NETIF_LOOPBACK=0
# CONFIG_RT_LWIP_STATS is not set
# CONFIG_RT_LWIP_USING_HW_CHECKSUM is not set
CONFIG_RT_LWIP_USING_PING=y
# CONFIG_LWIP_USING_DHCPD is not set
CONFIG_RT_LWIP_DEBUG=y
# CONFIG_RT_LWIP_SYS_DEBUG is not set
# CONFIG_RT_LWIP_ETHARP_DEBUG is not set
# CONFIG_RT_LWIP_PPP_DEBUG is not set
# CONFIG_RT_LWIP_MEM_DEBUG is not set
# CONFIG_RT_LWIP_MEMP_DEBUG is not set
# CONFIG_RT_LWIP_PBUF_DEBUG is not set
# CONFIG_RT_LWIP_API_LIB_DEBUG is not set
# CONFIG_RT_LWIP_API_MSG_DEBUG is not set
# CONFIG_RT_LWIP_TCPIP_DEBUG is not set
CONFIG_RT_LWIP_NETIF_DEBUG=y
# CONFIG_RT_LWIP_SOCKETS_DEBUG is not set
# CONFIG_RT_LWIP_DNS_DEBUG is not set
# CONFIG_RT_LWIP_AUTOIP_DEBUG is not set
# CONFIG_RT_LWIP_DHCP_DEBUG is not set
# CONFIG_RT_LWIP_IP_DEBUG is not set
# CONFIG_RT_LWIP_IP_REASS_DEBUG is not set
# CONFIG_RT_LWIP_ICMP_DEBUG is not set
# CONFIG_RT_LWIP_IGMP_DEBUG is not set
# CONFIG_RT_LWIP_UDP_DEBUG is not set
# CONFIG_RT_LWIP_TCP_DEBUG is not set
# CONFIG_RT_LWIP_TCP_INPUT_DEBUG is not set
# CONFIG_RT_LWIP_TCP_OUTPUT_DEBUG is not set
# CONFIG_RT_LWIP_TCP_RTO_DEBUG is not set
# CONFIG_RT_LWIP_TCP_CWND_DEBUG is not set
# CONFIG_RT_LWIP_TCP_WND_DEBUG is not set
# CONFIG_RT_LWIP_TCP_FR_DEBUG is not set
# CONFIG_RT_LWIP_TCP_QLEN_DEBUG is not set
# CONFIG_RT_LWIP_TCP_RST_DEBUG is not set
# CONFIG_RT_USING_AT is not set
#
@ -1041,7 +1166,11 @@ CONFIG_RT_USING_UART1=y
# CONFIG_RT_USING_UART0 is not set
# CONFIG_BSP_USING_SPI is not set
# CONFIG_BSP_USING_CAN is not set
# CONFIG_BSP_USING_GPIO is not set
# CONFIG_BSP_USING_QSPI is not set
CONFIG_BSP_USING_ETH=y
CONFIG_RT_LWIP_PBUF_POOL_BUFSIZE=1700
# CONFIG_BSP_USING_SDIO is not set
#
# Board extended module Drivers
@ -1081,6 +1210,8 @@ CONFIG_USE_QSPI=y
#
CONFIG_USE_FQSPI=y
# CONFIG_USE_GIC is not set
CONFIG_USE_IOPAD=y
CONFIG_ENABLE_IOPAD=y
CONFIG_USE_SERIAL=y
#
@ -1088,7 +1219,15 @@ CONFIG_USE_SERIAL=y
#
CONFIG_ENABLE_Pl011_UART=y
# CONFIG_USE_GPIO is not set
# CONFIG_USE_ETH is not set
CONFIG_USE_ETH=y
#
# Eth Configuration
#
CONFIG_ENABLE_FXMAC=y
# CONFIG_ENABLE_FGMAC is not set
CONFIG_FXMAC_PHY_COMMON=y
# CONFIG_FXMAC_PHY_YT is not set
# CONFIG_USE_CAN is not set
# CONFIG_USE_I2C is not set
# CONFIG_USE_TIMER is not set

93
bsp/phytium/aarch64/configs/e2000q_rtthread.h
View File

@ -8,7 +8,7 @@
#define RT_NAME_MAX 16
#define RT_USING_SMP
#define RT_CPUS_NR 4
#define RT_CPUS_NR 2
#define RT_ALIGN_SIZE 4
#define RT_THREAD_PRIORITY_32
#define RT_THREAD_PRIORITY_MAX 32
@ -28,7 +28,7 @@
#define RT_KSERVICE_USING_STDLIB
#define RT_KPRINTF_USING_LONGLONG
#define RT_USING_DEBUG
#define RT_DEBUG
/* Inter-Thread communication */
@ -40,12 +40,12 @@
/* Memory Management */
#define RT_PAGE_MAX_ORDER 11
#define RT_USING_MEMPOOL
#define RT_USING_SMALL_MEM
#define RT_PAGE_MAX_ORDER 16
#define RT_USING_SLAB
#define RT_USING_MEMHEAP
#define RT_MEMHEAP_FAST_MODE
#define RT_USING_SMALL_MEM_AS_HEAP
#define RT_USING_SLAB_AS_HEAP
#define RT_USING_HEAP_ISR
#define RT_USING_HEAP
/* Kernel Device Object */
@ -57,7 +57,6 @@
#define RT_VER_NUM 0x50001
#define ARCH_CPU_64BIT
#define RT_USING_CACHE
#define RT_USING_HW_ATOMIC
#define ARCH_ARM_BOOTWITH_FLUSH_CACHE
#define ARCH_MM_MMU
#define ARCH_ARM
@ -93,6 +92,21 @@
#define RT_USING_DFS_V1
#define DFS_FILESYSTEMS_MAX 4
#define DFS_FILESYSTEM_TYPES_MAX 4
#define RT_USING_DFS_ELMFAT
/* elm-chan's FatFs, Generic FAT Filesystem Module */
#define RT_DFS_ELM_CODE_PAGE 437
#define RT_DFS_ELM_WORD_ACCESS
#define RT_DFS_ELM_USE_LFN_3
#define RT_DFS_ELM_USE_LFN 3
#define RT_DFS_ELM_LFN_UNICODE_0
#define RT_DFS_ELM_LFN_UNICODE 0
#define RT_DFS_ELM_MAX_LFN 255
#define RT_DFS_ELM_DRIVES 2
#define RT_DFS_ELM_MAX_SECTOR_SIZE 512
#define RT_DFS_ELM_REENTRANT
#define RT_DFS_ELM_MUTEX_TIMEOUT 3000
#define RT_USING_DFS_DEVFS
#define RT_USING_DFS_RAMFS
@ -137,6 +151,61 @@
/* Network */
#define RT_USING_SAL
#define SAL_INTERNET_CHECK
/* Docking with protocol stacks */
#define SAL_USING_LWIP
#define SAL_USING_POSIX
#define RT_USING_NETDEV
#define NETDEV_USING_IFCONFIG
#define NETDEV_USING_PING
#define NETDEV_USING_NETSTAT
#define NETDEV_USING_AUTO_DEFAULT
#define NETDEV_IPV4 1
#define NETDEV_IPV6 0
#define RT_USING_LWIP
#define RT_USING_LWIP212
#define RT_USING_LWIP_VER_NUM 0x20102
#define RT_LWIP_MEM_ALIGNMENT 64
#define RT_LWIP_IGMP
#define RT_LWIP_ICMP
#define RT_LWIP_DNS
/* Static IPv4 Address */
#define RT_LWIP_IPADDR "192.168.4.10"
#define RT_LWIP_GWADDR "192.168.4.1"
#define RT_LWIP_MSKADDR "255.255.255.0"
#define RT_LWIP_UDP
#define RT_LWIP_TCP
#define RT_LWIP_RAW
#define RT_MEMP_NUM_NETCONN 8
#define RT_LWIP_PBUF_NUM 512
#define RT_LWIP_RAW_PCB_NUM 4
#define RT_LWIP_UDP_PCB_NUM 4
#define RT_LWIP_TCP_PCB_NUM 4
#define RT_LWIP_TCP_SEG_NUM 40
#define RT_LWIP_TCP_SND_BUF 8196
#define RT_LWIP_TCP_WND 8196
#define RT_LWIP_TCPTHREAD_PRIORITY 12
#define RT_LWIP_TCPTHREAD_MBOX_SIZE 8
#define RT_LWIP_TCPTHREAD_STACKSIZE 16184
#define RT_LWIP_ETHTHREAD_PRIORITY 12
#define RT_LWIP_ETHTHREAD_STACKSIZE 2048
#define RT_LWIP_ETHTHREAD_MBOX_SIZE 8
#define LWIP_NETIF_STATUS_CALLBACK 1
#define LWIP_NETIF_LINK_CALLBACK 1
#define SO_REUSE 1
#define LWIP_SO_RCVTIMEO 1
#define LWIP_SO_SNDTIMEO 1
#define LWIP_SO_RCVBUF 1
#define LWIP_SO_LINGER 0
#define LWIP_NETIF_LOOPBACK 0
#define RT_LWIP_USING_PING
#define RT_LWIP_DEBUG
#define RT_LWIP_NETIF_DEBUG
/* Utilities */
@ -269,6 +338,8 @@
#define BSP_USING_UART
#define RT_USING_UART1
#define BSP_USING_ETH
#define RT_LWIP_PBUF_POOL_BUFSIZE 1700
/* Board extended module Drivers */
@ -296,11 +367,19 @@
/* Qspi Configuration */
#define USE_FQSPI
#define USE_IOPAD
#define ENABLE_IOPAD
#define USE_SERIAL
/* Usart Configuration */
#define ENABLE_Pl011_UART
#define USE_ETH
/* Eth Configuration */
#define ENABLE_FXMAC
#define FXMAC_PHY_COMMON
#define LOG_ERROR
#endif

1263
bsp/phytium/aarch64/configs/e2000q_rtthread_test Normal file
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File diff suppressed because it is too large Load Diff

386
bsp/phytium/aarch64/configs/e2000q_rtthread_test.h Normal file
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@ -0,0 +1,386 @@
#ifndef RT_CONFIG_H__
#define RT_CONFIG_H__
/* Automatically generated file; DO NOT EDIT. */
/* RT-Thread Project Configuration */
/* RT-Thread Kernel */
#define RT_NAME_MAX 16
#define RT_USING_SMP
#define RT_CPUS_NR 2
#define RT_ALIGN_SIZE 4
#define RT_THREAD_PRIORITY_32
#define RT_THREAD_PRIORITY_MAX 32
#define RT_TICK_PER_SECOND 1000
#define RT_USING_OVERFLOW_CHECK
#define RT_USING_HOOK
#define RT_HOOK_USING_FUNC_PTR
#define RT_USING_IDLE_HOOK
#define RT_IDLE_HOOK_LIST_SIZE 4
#define IDLE_THREAD_STACK_SIZE 40960
#define SYSTEM_THREAD_STACK_SIZE 40960
#define RT_USING_TIMER_SOFT
#define RT_TIMER_THREAD_PRIO 4
#define RT_TIMER_THREAD_STACK_SIZE 4096
/* kservice optimization */
#define RT_KSERVICE_USING_STDLIB
#define RT_KPRINTF_USING_LONGLONG
#define RT_DEBUG
/* Inter-Thread communication */
#define RT_USING_SEMAPHORE
#define RT_USING_MUTEX
#define RT_USING_EVENT
#define RT_USING_MAILBOX
#define RT_USING_MESSAGEQUEUE
/* Memory Management */
#define RT_PAGE_MAX_ORDER 16
#define RT_USING_SLAB
#define RT_USING_MEMHEAP
#define RT_MEMHEAP_FAST_MODE
#define RT_USING_SLAB_AS_HEAP
#define RT_USING_HEAP_ISR
#define RT_USING_HEAP
/* Kernel Device Object */
#define RT_USING_DEVICE
#define RT_USING_CONSOLE
#define RT_CONSOLEBUF_SIZE 128
#define RT_CONSOLE_DEVICE_NAME "uart1"
#define RT_VER_NUM 0x50001
#define ARCH_CPU_64BIT
#define RT_USING_CACHE
#define ARCH_ARM_BOOTWITH_FLUSH_CACHE
#define ARCH_MM_MMU
#define ARCH_ARM
#define ARCH_ARM_MMU
#define ARCH_ARMV8
/* RT-Thread Components */
#define RT_USING_COMPONENTS_INIT
#define RT_USING_USER_MAIN
#define RT_MAIN_THREAD_STACK_SIZE 8192
#define RT_MAIN_THREAD_PRIORITY 10
#define RT_USING_MSH
#define RT_USING_FINSH
#define FINSH_USING_MSH
#define FINSH_THREAD_NAME "tshell"
#define FINSH_THREAD_PRIORITY 20
#define FINSH_THREAD_STACK_SIZE 4096
#define FINSH_USING_HISTORY
#define FINSH_HISTORY_LINES 5
#define FINSH_USING_SYMTAB
#define FINSH_CMD_SIZE 80
#define MSH_USING_BUILT_IN_COMMANDS
#define FINSH_USING_DESCRIPTION
#define FINSH_ARG_MAX 10
/* DFS: device virtual file system */
#define RT_USING_DFS
#define DFS_USING_POSIX
#define DFS_USING_WORKDIR
#define DFS_FD_MAX 16
#define RT_USING_DFS_V1
#define DFS_FILESYSTEMS_MAX 4
#define DFS_FILESYSTEM_TYPES_MAX 4
#define RT_USING_DFS_ELMFAT
/* elm-chan's FatFs, Generic FAT Filesystem Module */
#define RT_DFS_ELM_CODE_PAGE 437
#define RT_DFS_ELM_WORD_ACCESS
#define RT_DFS_ELM_USE_LFN_3
#define RT_DFS_ELM_USE_LFN 3
#define RT_DFS_ELM_LFN_UNICODE_0
#define RT_DFS_ELM_LFN_UNICODE 0
#define RT_DFS_ELM_MAX_LFN 255
#define RT_DFS_ELM_DRIVES 2
#define RT_DFS_ELM_MAX_SECTOR_SIZE 512
#define RT_DFS_ELM_REENTRANT
#define RT_DFS_ELM_MUTEX_TIMEOUT 3000
#define RT_USING_DFS_DEVFS
#define RT_USING_DFS_RAMFS
/* Device Drivers */
#define RT_USING_DEVICE_IPC
#define RT_UNAMED_PIPE_NUMBER 64
#define RT_USING_SYSTEM_WORKQUEUE
#define RT_SYSTEM_WORKQUEUE_STACKSIZE 8192
#define RT_SYSTEM_WORKQUEUE_PRIORITY 23
#define RT_USING_SERIAL
#define RT_USING_SERIAL_V1
#define RT_SERIAL_USING_DMA
#define RT_SERIAL_RB_BUFSZ 64
#define RT_USING_NULL
#define RT_USING_ZERO
#define RT_USING_RANDOM
#define RT_USING_RTC
/* Using USB */
/* C/C++ and POSIX layer */
#define RT_LIBC_DEFAULT_TIMEZONE 8
/* POSIX (Portable Operating System Interface) layer */
#define RT_USING_POSIX_FS
#define RT_USING_POSIX_DEVIO
#define RT_USING_POSIX_STDIO
#define RT_USING_POSIX_TERMIOS
#define RT_USING_POSIX_DELAY
#define RT_USING_POSIX_CLOCK
#define RT_USING_POSIX_TIMER
/* Interprocess Communication (IPC) */
/* Socket is in the 'Network' category */
/* Network */
#define RT_USING_SAL
#define SAL_INTERNET_CHECK
/* Docking with protocol stacks */
#define SAL_USING_LWIP
#define SAL_USING_POSIX
#define RT_USING_NETDEV
#define NETDEV_USING_IFCONFIG
#define NETDEV_USING_PING
#define NETDEV_USING_NETSTAT
#define NETDEV_USING_AUTO_DEFAULT
#define NETDEV_IPV4 1
#define NETDEV_IPV6 0
#define RT_USING_LWIP
#define RT_USING_LWIP212
#define RT_USING_LWIP_VER_NUM 0x20102
#define RT_LWIP_MEM_ALIGNMENT 64
#define RT_LWIP_IGMP
#define RT_LWIP_ICMP
#define RT_LWIP_DNS
/* Static IPv4 Address */
#define RT_LWIP_IPADDR "192.168.4.10"
#define RT_LWIP_GWADDR "192.168.4.1"
#define RT_LWIP_MSKADDR "255.255.255.0"
#define RT_LWIP_UDP
#define RT_LWIP_TCP
#define RT_LWIP_RAW
#define RT_MEMP_NUM_NETCONN 8
#define RT_LWIP_PBUF_NUM 512
#define RT_LWIP_RAW_PCB_NUM 4
#define RT_LWIP_UDP_PCB_NUM 4
#define RT_LWIP_TCP_PCB_NUM 4
#define RT_LWIP_TCP_SEG_NUM 40
#define RT_LWIP_TCP_SND_BUF 8196
#define RT_LWIP_TCP_WND 8196
#define RT_LWIP_TCPTHREAD_PRIORITY 12
#define RT_LWIP_TCPTHREAD_MBOX_SIZE 8
#define RT_LWIP_TCPTHREAD_STACKSIZE 16184
#define RT_LWIP_ETHTHREAD_PRIORITY 12
#define RT_LWIP_ETHTHREAD_STACKSIZE 2048
#define RT_LWIP_ETHTHREAD_MBOX_SIZE 8
#define LWIP_NETIF_STATUS_CALLBACK 1
#define LWIP_NETIF_LINK_CALLBACK 1
#define SO_REUSE 1
#define LWIP_SO_RCVTIMEO 1
#define LWIP_SO_SNDTIMEO 1
#define LWIP_SO_RCVBUF 1
#define LWIP_SO_LINGER 0
#define LWIP_NETIF_LOOPBACK 0
#define RT_LWIP_USING_PING
#define RT_LWIP_DEBUG
#define RT_LWIP_NETIF_DEBUG
/* Utilities */
#define RT_USING_RYM
#define YMODEM_USING_FILE_TRANSFER
#define RT_USING_ADT
/* RT-Thread Utestcases */
/* RT-Thread online packages */
/* IoT - internet of things */
/* Wi-Fi */
/* Marvell WiFi */
/* Wiced WiFi */
/* IoT Cloud */
/* security packages */
/* language packages */
/* JSON: JavaScript Object Notation, a lightweight data-interchange format */
/* XML: Extensible Markup Language */
/* multimedia packages */
/* LVGL: powerful and easy-to-use embedded GUI library */
/* u8g2: a monochrome graphic library */
/* tools packages */
/* system packages */
/* enhanced kernel services */
/* acceleration: Assembly language or algorithmic acceleration packages */
/* CMSIS: ARM Cortex-M Microcontroller Software Interface Standard */
/* Micrium: Micrium software products porting for RT-Thread */
/* peripheral libraries and drivers */
/* sensors drivers */
/* touch drivers */
/* Kendryte SDK */
/* AI packages */
/* Signal Processing and Control Algorithm Packages */
/* miscellaneous packages */
/* project laboratory */
/* samples: kernel and components samples */
#define PKG_USING_KERNEL_SAMPLES
#define PKG_USING_KERNEL_SAMPLES_LATEST_VERSION
#define PKG_USING_KERNEL_SAMPLES_EN
/* entertainment: terminal games and other interesting software packages */
/* Arduino libraries */
/* Projects */
/* Sensors */
/* Display */
/* Timing */
/* Data Processing */
/* Data Storage */
/* Communication */
/* Device Control */
/* Other */
/* Signal IO */
/* Uncategorized */
/* Hardware Drivers */
/* On-chip Peripheral Drivers */
#define BSP_USING_UART
#define RT_USING_UART1
#define BSP_USING_ETH
#define RT_LWIP_PBUF_POOL_BUFSIZE 1700
/* Board extended module Drivers */
#define BSP_USING_GIC
#define BSP_USING_GICV3
#define PHYTIUM_ARCH_AARCH64
#define ARM_SPI_BIND_CPU_ID 2
/* Standalone Setting */
#define TARGET_ARMV8_AARCH64
/* Board Configuration */
#define TARGET_E2000Q
#define TARGET_E2000
#define DEFAULT_DEBUG_PRINT_UART1
/* Components Configuration */
#define USE_SPI
#define USE_FSPIM
#define USE_QSPI
/* Qspi Configuration */
#define USE_FQSPI
#define USE_IOPAD
#define ENABLE_IOPAD
#define USE_SERIAL
/* Usart Configuration */
#define ENABLE_Pl011_UART
#define USE_ETH
/* Eth Configuration */
#define ENABLE_FXMAC
#define FXMAC_PHY_COMMON
#define LOG_ERROR
#define PHYTIUM_RTT_TEST
#endif

148
bsp/phytium/aarch64/link.lds
View File

@ -1,148 +0,0 @@
/*
* Copyright (c) 2006-2021, RT-Thread Development Team
*
* SPDX-License-Identifier: Apache-2.0
*
* Change Logs:
* 2017-5-30 bernard first version
*/
/* _EL1_STACK_SIZE = DEFINED(_EL1_STACK_SIZE) ? _EL1_STACK_SIZE : 0x20000; */
SECTIONS
{
. = 0x80080000 ;
. = ALIGN(4096);
.text :
{
KEEP(*(.text.entrypoint)) /* The entry point */
*(.vectors)
*(.text) /* remaining code */
*(.text.*) /* remaining code */
*(.rodata) /* read-only data (constants) */
*(.rodata*)
*(.glue_7)
*(.glue_7t)
*(.gnu.linkonce.t*)
*(COMMON)
/* section information for utest */
. = ALIGN(8);
__rt_utest_tc_tab_start = .;
KEEP(*(UtestTcTab))
__rt_utest_tc_tab_end = .;
/* section information for finsh shell */
. = ALIGN(16);
__fsymtab_start = .;
KEEP(*(FSymTab))
__fsymtab_end = .;
. = ALIGN(16);
__vsymtab_start = .;
KEEP(*(VSymTab))
__vsymtab_end = .;
. = ALIGN(16);
/* section information for initial. */
. = ALIGN(16);
__rt_init_start = .;
KEEP(*(SORT(.rti_fn*)))
__rt_init_end = .;
. = ALIGN(16);
. = ALIGN(16);
_etext = .;
}
. = ALIGN(4);
.eh_frame_hdr :
{
*(.eh_frame_hdr)
*(.eh_frame_entry)
}
.eh_frame : ONLY_IF_RO { KEEP (*(.eh_frame)) }
. = ALIGN(16);
.data :
{
*(.data)
*(.data.*)
*(.data1)
*(.data1.*)
. = ALIGN(16);
_gp = ABSOLUTE(.); /* Base of small data */
*(.sdata)
*(.sdata.*)
}
. = ALIGN(16);
.ctors :
{
PROVIDE(__ctors_start__ = .);
/* new GCC version uses .init_array */
KEEP(*(SORT(.init_array.*)))
KEEP(*(.init_array))
PROVIDE(__ctors_end__ = .);
}
. = ALIGN(4);
.dtors :
{
PROVIDE(__dtors_start__ = .);
KEEP(*(SORT(.dtors.*)))
KEEP(*(.dtors))
PROVIDE(__dtors_end__ = .);
}
. = ALIGN(16);
.bss :
{
PROVIDE(__bss_start = .);
*(.bss)
*(.bss.*)
*(.dynbss)
. = ALIGN(32);
PROVIDE(__bss_end = .);
}
_end = .;
/* Stabs debugging sections. */
.stab 0 : { *(.stab) }
.stabstr 0 : { *(.stabstr) }
.stab.excl 0 : { *(.stab.excl) }
.stab.exclstr 0 : { *(.stab.exclstr) }
.stab.index 0 : { *(.stab.index) }
.stab.indexstr 0 : { *(.stab.indexstr) }
.comment 0 : { *(.comment) }
/* DWARF debug sections.
* Symbols in the DWARF debugging sections are relative to the beginning
* of the section so we begin them at 0. */
/* DWARF 1 */
.debug 0 : { *(.debug) }
.line 0 : { *(.line) }
/* GNU DWARF 1 extensions */
.debug_srcinfo 0 : { *(.debug_srcinfo) }
.debug_sfnames 0 : { *(.debug_sfnames) }
/* DWARF 1.1 and DWARF 2 */
.debug_aranges 0 : { *(.debug_aranges) }
.debug_pubnames 0 : { *(.debug_pubnames) }
/* DWARF 2 */
.debug_info 0 : { *(.debug_info .gnu.linkonce.wi.*) }
.debug_abbrev 0 : { *(.debug_abbrev) }
.debug_line 0 : { *(.debug_line) }
.debug_frame 0 : { *(.debug_frame) }
.debug_str 0 : { *(.debug_str) }
.debug_loc 0 : { *(.debug_loc) }
.debug_macinfo 0 : { *(.debug_macinfo) }
/* SGI/MIPS DWARF 2 extensions */
.debug_weaknames 0 : { *(.debug_weaknames) }
.debug_funcnames 0 : { *(.debug_funcnames) }
.debug_typenames 0 : { *(.debug_typenames) }
.debug_varnames 0 : { *(.debug_varnames) }
}
__bss_size = SIZEOF(.bss);

149
bsp/phytium/aarch64/link_smart.lds
View File

@ -1,149 +0,0 @@
/*
* Copyright (c) 2006-2023, RT-Thread Development Team
*
* SPDX-License-Identifier: Apache-2.0
*
* Change Logs:
* 2017-5-30 bernard first version
*/
/* _EL1_STACK_SIZE = DEFINED(_EL1_STACK_SIZE) ? _EL1_STACK_SIZE : 0x20000; */
SECTIONS
{
/* . = 0x80080000 ; */
. = 0xffff000000080000 ;
. = ALIGN(4096);
.text :
{
KEEP(*(.text.entrypoint)) /* The entry point */
*(.vectors)
*(.text) /* remaining code */
*(.text.*) /* remaining code */
*(.rodata) /* read-only data (constants) */
*(.rodata*)
*(.glue_7)
*(.glue_7t)
*(.gnu.linkonce.t*)
*(COMMON)
/* section information for utest */
. = ALIGN(8);
__rt_utest_tc_tab_start = .;
KEEP(*(UtestTcTab))
__rt_utest_tc_tab_end = .;
/* section information for finsh shell */
. = ALIGN(16);
__fsymtab_start = .;
KEEP(*(FSymTab))
__fsymtab_end = .;
. = ALIGN(16);
__vsymtab_start = .;
KEEP(*(VSymTab))
__vsymtab_end = .;
. = ALIGN(16);
/* section information for initial. */
. = ALIGN(16);
__rt_init_start = .;
KEEP(*(SORT(.rti_fn*)))
__rt_init_end = .;
. = ALIGN(16);
. = ALIGN(16);
_etext = .;
}
. = ALIGN(4);
.eh_frame_hdr :
{
*(.eh_frame_hdr)
*(.eh_frame_entry)
}
.eh_frame : ONLY_IF_RO { KEEP (*(.eh_frame)) }
. = ALIGN(16);
.data :
{
*(.data)
*(.data.*)
*(.data1)
*(.data1.*)
. = ALIGN(16);
_gp = ABSOLUTE(.); /* Base of small data */
*(.sdata)
*(.sdata.*)
}
. = ALIGN(16);
.ctors :
{
PROVIDE(__ctors_start__ = .);
/* new GCC version uses .init_array */
KEEP(*(SORT(.init_array.*)))
KEEP(*(.init_array))
PROVIDE(__ctors_end__ = .);
}
. = ALIGN(4);
.dtors :
{
PROVIDE(__dtors_start__ = .);
KEEP(*(SORT(.dtors.*)))
KEEP(*(.dtors))
PROVIDE(__dtors_end__ = .);
}
. = ALIGN(16);
.bss :
{
PROVIDE(__bss_start = .);
*(.bss)
*(.bss.*)
*(.dynbss)
. = ALIGN(32);
PROVIDE(__bss_end = .);
}
_end = .;
/* Stabs debugging sections. */
.stab 0 : { *(.stab) }
.stabstr 0 : { *(.stabstr) }
.stab.excl 0 : { *(.stab.excl) }
.stab.exclstr 0 : { *(.stab.exclstr) }
.stab.index 0 : { *(.stab.index) }
.stab.indexstr 0 : { *(.stab.indexstr) }
.comment 0 : { *(.comment) }
/* DWARF debug sections.
* Symbols in the DWARF debugging sections are relative to the beginning
* of the section so we begin them at 0. */
/* DWARF 1 */
.debug 0 : { *(.debug) }
.line 0 : { *(.line) }
/* GNU DWARF 1 extensions */
.debug_srcinfo 0 : { *(.debug_srcinfo) }
.debug_sfnames 0 : { *(.debug_sfnames) }
/* DWARF 1.1 and DWARF 2 */
.debug_aranges 0 : { *(.debug_aranges) }
.debug_pubnames 0 : { *(.debug_pubnames) }
/* DWARF 2 */
.debug_info 0 : { *(.debug_info .gnu.linkonce.wi.*) }
.debug_abbrev 0 : { *(.debug_abbrev) }
.debug_line 0 : { *(.debug_line) }
.debug_frame 0 : { *(.debug_frame) }
.debug_str 0 : { *(.debug_str) }
.debug_loc 0 : { *(.debug_loc) }
.debug_macinfo 0 : { *(.debug_macinfo) }
/* SGI/MIPS DWARF 2 extensions */
.debug_weaknames 0 : { *(.debug_weaknames) }
.debug_funcnames 0 : { *(.debug_funcnames) }
.debug_typenames 0 : { *(.debug_typenames) }
.debug_varnames 0 : { *(.debug_varnames) }
}
__bss_size = SIZEOF(.bss);

28
bsp/phytium/aarch64/makefile
View File

@ -28,6 +28,10 @@ else
RTCONFIG := $(RTCONFIG)_rtthread
endif
ifdef CONFIG_PHYTIUM_RTT_TEST
RTCONFIG := $(RTCONFIG)_test
endif
boot:
make all
cp rtthread_a64.elf /mnt/d/tftboot
@ -60,20 +64,44 @@ load_e2000q_rtsmart:
@cp ./configs/e2000q_rtsmart.h ./rtconfig.h -f
@scons -c
load_e2000q_rtsmart_test:
@echo "Load configs from ./configs/e2000q_rtsmart"
@cp ./configs/e2000q_rtsmart_test ./.config -f
@cp ./configs/e2000q_rtsmart_test.h ./rtconfig.h -f
@scons -c
load_e2000q_rtthread:
@echo "Load configs from ./configs/e2000q_rtthread"
@cp ./configs/e2000q_rtthread ./.config -f
@cp ./configs/e2000q_rtthread.h ./rtconfig.h -f
@scons -c
load_e2000q_rtthread_test:
@echo "Load configs from ./configs/e2000q_rtthread"
@cp ./configs/e2000q_rtthread_test ./.config -f
@cp ./configs/e2000q_rtthread_test.h ./rtconfig.h -f
@scons -c
load_e2000d_rtsmart:
@echo "Load configs from ./configs/e2000d_rtsmart"
@cp ./configs/e2000d_rtsmart ./.config -f
@cp ./configs/e2000d_rtsmart.h ./rtconfig.h -f
@scons -c
load_e2000d_rtsmart_test:
@echo "Load configs from ./configs/e2000d_rtsmart"
@cp ./configs/e2000d_rtsmart_test ./.config -f
@cp ./configs/e2000d_rtsmart_test.h ./rtconfig.h -f
@scons -c
load_e2000d_rtthread:
@echo "Load configs from ./configs/e2000d_rtthread"
@cp ./configs/e2000d_rtthread ./.config -f
@cp ./configs/e2000d_rtthread.h ./rtconfig.h -f
@scons -c
load_e2000d_rtthread_test:
@echo "Load configs from ./configs/e2000d_rtthread"
@cp ./configs/e2000d_rtthread_test ./.config -f
@cp ./configs/e2000d_rtthread_test.h ./rtconfig.h -f
@scons -c

124
bsp/phytium/aarch64/rtconfig.h
View File

@ -18,17 +18,20 @@
#define RT_HOOK_USING_FUNC_PTR
#define RT_USING_IDLE_HOOK
#define RT_IDLE_HOOK_LIST_SIZE 4
#define IDLE_THREAD_STACK_SIZE 40960
#define SYSTEM_THREAD_STACK_SIZE 40960
#define IDLE_THREAD_STACK_SIZE 8192
#define SYSTEM_THREAD_STACK_SIZE 8192
#define RT_USING_TIMER_SOFT
#define RT_TIMER_THREAD_PRIO 4
#define RT_TIMER_THREAD_STACK_SIZE 4096
#define RT_TIMER_THREAD_STACK_SIZE 8192
/* kservice optimization */
#define RT_KSERVICE_USING_STDLIB
#define RT_KPRINTF_USING_LONGLONG
#define RT_DEBUG
#define RT_USING_DEBUG
#define RT_DEBUGING_COLOR
#define RT_DEBUGING_CONTEXT
#define RT_DEBUGING_INIT
/* Inter-Thread communication */
@ -40,12 +43,12 @@
/* Memory Management */
#define RT_PAGE_MAX_ORDER 11
#define RT_USING_MEMPOOL
#define RT_USING_SMALL_MEM
#define RT_PAGE_MAX_ORDER 16
#define RT_USING_SLAB
#define RT_USING_MEMHEAP
#define RT_MEMHEAP_FAST_MODE
#define RT_USING_SMALL_MEM_AS_HEAP
#define RT_USING_SLAB_AS_HEAP
#define RT_USING_HEAP_ISR
#define RT_USING_HEAP
/* Kernel Device Object */
@ -55,14 +58,20 @@
#define RT_CONSOLEBUF_SIZE 128
#define RT_CONSOLE_DEVICE_NAME "uart1"
#define RT_VER_NUM 0x50001
/* RT-Thread Architecture */
#define ARCH_CPU_64BIT
#define RT_USING_CACHE
#define RT_USING_HW_ATOMIC
#define ARCH_ARM_BOOTWITH_FLUSH_CACHE
#define ARCH_MM_MMU
#define ARCH_ARM
#define ARCH_ARM_MMU
#define ARCH_ARMV8
#define ARCH_TEXT_OFFSET 0x80000
#define ARCH_RAM_OFFSET 0x80000000
#define ARCH_SECONDARY_CPU_STACK_SIZE 4096
#define ARCH_HAVE_EFFICIENT_UNALIGNED_ACCESS
/* RT-Thread Components */
@ -93,6 +102,21 @@
#define RT_USING_DFS_V1
#define DFS_FILESYSTEMS_MAX 4
#define DFS_FILESYSTEM_TYPES_MAX 4
#define RT_USING_DFS_ELMFAT
/* elm-chan's FatFs, Generic FAT Filesystem Module */
#define RT_DFS_ELM_CODE_PAGE 437
#define RT_DFS_ELM_WORD_ACCESS
#define RT_DFS_ELM_USE_LFN_3
#define RT_DFS_ELM_USE_LFN 3
#define RT_DFS_ELM_LFN_UNICODE_0
#define RT_DFS_ELM_LFN_UNICODE 0
#define RT_DFS_ELM_MAX_LFN 255
#define RT_DFS_ELM_DRIVES 2
#define RT_DFS_ELM_MAX_SECTOR_SIZE 512
#define RT_DFS_ELM_REENTRANT
#define RT_DFS_ELM_MUTEX_TIMEOUT 3000
#define RT_USING_DFS_DEVFS
#define RT_USING_DFS_RAMFS
@ -111,6 +135,12 @@
#define RT_USING_ZERO
#define RT_USING_RANDOM
#define RT_USING_RTC
#define RT_USING_SDIO
#define RT_SDIO_STACK_SIZE 4096
#define RT_SDIO_THREAD_PRIORITY 15
#define RT_MMCSD_STACK_SIZE 4096
#define RT_MMCSD_THREAD_PREORITY 22
#define RT_MMCSD_MAX_PARTITION 16
/* Using USB */
@ -137,13 +167,73 @@
/* Network */
#define RT_USING_SAL
#define SAL_INTERNET_CHECK
/* Docking with protocol stacks */
#define SAL_USING_LWIP
#define SAL_USING_POSIX
#define RT_USING_NETDEV
#define NETDEV_USING_IFCONFIG
#define NETDEV_USING_PING
#define NETDEV_USING_NETSTAT
#define NETDEV_USING_AUTO_DEFAULT
#define NETDEV_IPV4 1
#define NETDEV_IPV6 0
#define RT_USING_LWIP
#define RT_USING_LWIP212
#define RT_USING_LWIP_VER_NUM 0x20102
#define RT_LWIP_MEM_ALIGNMENT 64
#define RT_LWIP_IGMP
#define RT_LWIP_ICMP
#define RT_LWIP_DNS
/* Static IPv4 Address */
#define RT_LWIP_IPADDR "192.168.4.10"
#define RT_LWIP_GWADDR "192.168.4.1"
#define RT_LWIP_MSKADDR "255.255.255.0"
#define RT_LWIP_UDP
#define RT_LWIP_TCP
#define RT_LWIP_RAW
#define RT_MEMP_NUM_NETCONN 8
#define RT_LWIP_PBUF_NUM 512
#define RT_LWIP_RAW_PCB_NUM 4
#define RT_LWIP_UDP_PCB_NUM 4
#define RT_LWIP_TCP_PCB_NUM 4
#define RT_LWIP_TCP_SEG_NUM 40
#define RT_LWIP_TCP_SND_BUF 8196
#define RT_LWIP_TCP_WND 8196
#define RT_LWIP_TCPTHREAD_PRIORITY 12
#define RT_LWIP_TCPTHREAD_MBOX_SIZE 8
#define RT_LWIP_TCPTHREAD_STACKSIZE 16184
#define RT_LWIP_ETHTHREAD_PRIORITY 12
#define RT_LWIP_ETHTHREAD_STACKSIZE 2048
#define RT_LWIP_ETHTHREAD_MBOX_SIZE 8
#define LWIP_NETIF_STATUS_CALLBACK 1
#define LWIP_NETIF_LINK_CALLBACK 1
#define SO_REUSE 1
#define LWIP_SO_RCVTIMEO 1
#define LWIP_SO_SNDTIMEO 1
#define LWIP_SO_RCVBUF 1
#define LWIP_SO_LINGER 0
#define LWIP_NETIF_LOOPBACK 0
#define RT_LWIP_USING_PING
#define RT_LWIP_DEBUG
#define RT_LWIP_NETIF_DEBUG
/* Utilities */
#define RT_USING_RYM
#define YMODEM_USING_FILE_TRANSFER
#define RT_USING_RESOURCE_ID
#define RT_USING_ADT
#define RT_USING_ADT_AVL
#define RT_USING_ADT_BITMAP
#define RT_USING_ADT_HASHMAP
#define RT_USING_ADT_REF
#define RT_USING_KTIME
/* RT-Thread Utestcases */
@ -270,6 +360,11 @@
#define BSP_USING_UART
#define RT_USING_UART1
#define BSP_USING_ETH
#define RT_LWIP_PBUF_POOL_BUFSIZE 1700
#define BSP_USING_SDIO
#define BSP_USING_SDCARD_FATFS
#define USING_SDIO1
/* Board extended module Drivers */
@ -297,11 +392,22 @@
/* Qspi Configuration */
#define USE_FQSPI
#define USE_IOPAD
#define ENABLE_IOPAD
#define USE_SERIAL
/* Usart Configuration */
#define ENABLE_Pl011_UART
#define USE_ETH
/* Eth Configuration */
#define ENABLE_FXMAC
#define FXMAC_PHY_COMMON
/* Sdk common configuration */
#define LOG_ERROR
#endif

6
bsp/phytium/aarch64/rtconfig.py
View File

@ -13,6 +13,7 @@ if PLATFORM == 'gcc':
PREFIX = os.getenv('RTT_CC_PREFIX') or 'aarch64-none-elf-'
CC = PREFIX + 'gcc'
CXX = PREFIX + 'g++'
CPP = PREFIX + 'cpp'
AS = PREFIX + 'gcc'
AR = PREFIX + 'ar'
LINK = PREFIX + 'gcc'
@ -25,10 +26,11 @@ if PLATFORM == 'gcc':
AFPFLAGS = ' '
DEVICE = ' -march=armv8-a -ftree-vectorize -ffast-math -funwind-tables -fno-strict-aliasing'
CXXFLAGS= DEVICE + CFPFLAGS + ' -Wall -fdiagnostics-color=always'
CPPFLAGS = ' -E -P -x assembler-with-cpp'
CXXFLAGS = DEVICE + CFPFLAGS + ' -Wall -fdiagnostics-color=always'
CFLAGS = DEVICE + CFPFLAGS + ' -Wall -Wno-cpp -std=gnu99 -fdiagnostics-color=always'
AFLAGS = ' -c' + AFPFLAGS + ' -x assembler-with-cpp'
LFLAGS = DEVICE + ' -Wl,--gc-sections,-Map=rtthread_a64.map,-cref,-u,system_vectors -T link.lds' + ' -lsupc++ -lgcc -static'
LFLAGS = DEVICE + ' -nostartfiles -Wl,--gc-sections,-Map=rtthread_a64.map,-cref,-u,system_vectors -T link.lds' + ' -lsupc++ -lgcc -static'
CPATH = ''
LPATH = ''

67
bsp/phytium/board/board.c
View File

@ -1,5 +1,5 @@
/*
* Copyright (c) 2006-2023, RT-Thread Development Team
* Copyright (c) 2006-2021, RT-Thread Development Team
*
* SPDX-License-Identifier: Apache-2.0
*
@ -10,6 +10,7 @@
* 2022-10-26 huanghe first commit
* 2022-10-26 zhugengyu support aarch64
* 2023-04-13 zhugengyu support RT-Smart
* 2023-07-27 zhugengyu update aarch32 gtimer usage
*
*/
@ -22,8 +23,8 @@
#include <mm_page.h>
#ifdef RT_USING_SMART
#include <page.h>
#include <lwp_arch.h>
#include <page.h>
#include <lwp_arch.h>
#endif
#include <gicv3.h>
@ -41,6 +42,11 @@
#include "fprintk.h"
#include "fearly_uart.h"
#include "fcpu_info.h"
#include "fiopad.h"
#ifdef RT_USING_SMP
#include "fpsci.h"
#endif
#define LOG_DEBUG_TAG "BOARD"
#define BSP_LOG_ERROR(format, ...) FT_DEBUG_PRINT_E(LOG_DEBUG_TAG, format, ##__VA_ARGS__)
@ -48,6 +54,7 @@
#define BSP_LOG_INFO(format, ...) FT_DEBUG_PRINT_I(LOG_DEBUG_TAG, format, ##__VA_ARGS__)
#define BSP_LOG_DEBUG(format, ...) FT_DEBUG_PRINT_D(LOG_DEBUG_TAG, format, ##__VA_ARGS__)
FIOPadCtrl iopad_ctrl;
/* mmu config */
extern struct mem_desc platform_mem_desc[];
extern const rt_uint32_t platform_mem_desc_size;
@ -62,7 +69,8 @@ void idle_wfi(void)
*/
extern size_t MMUTable[];
rt_region_t init_page_region = {
rt_region_t init_page_region =
{
PAGE_START,
PAGE_END
};
@ -78,7 +86,7 @@ static rt_uint32_t timer_step;
void rt_hw_timer_isr(int vector, void *parameter)
{
GenericTimerCompare(timer_step);
GenericTimerSetTimerCompareValue(GENERIC_TIMER_ID0, timer_step);
rt_tick_increase();
}
@ -89,9 +97,9 @@ int rt_hw_timer_init(void)
timer_step = GenericTimerFrequecy();
timer_step /= RT_TICK_PER_SECOND;
GenericTimerCompare(timer_step);
GenericTimerInterruptEnable();
GenericTimerStart();
GenericTimerSetTimerCompareValue(GENERIC_TIMER_ID0, timer_step);
GenericTimerInterruptEnable(GENERIC_TIMER_ID0);
GenericTimerStart(GENERIC_TIMER_ID0);
return 0;
}
INIT_BOARD_EXPORT(rt_hw_timer_init);
@ -106,17 +114,17 @@ INIT_BOARD_EXPORT(rt_hw_timer_init);
void rt_hw_board_aarch64_init(void)
{
/* AARCH64 */
#if defined(RT_USING_SMART)
/* 1. init rt_kernel_space table (aspace.start = KERNEL_VADDR_START , aspace.size = ), 2. init io map range (rt_ioremap_start \ rt_ioremap_size) 3. */
rt_hw_mmu_map_init(&rt_kernel_space, (void*)0xfffffffff0000000, 0x10000000, MMUTable, PV_OFFSET);
#else
rt_hw_mmu_map_init(&rt_kernel_space, (void*)0x80000000, 0x10000000, MMUTable, 0);
#endif
#if defined(RT_USING_SMART)
/* 1. init rt_kernel_space table (aspace.start = KERNEL_VADDR_START , aspace.size = ), 2. init io map range (rt_ioremap_start \ rt_ioremap_size) 3. */
rt_hw_mmu_map_init(&rt_kernel_space, (void *)0xfffffffff0000000, 0x10000000, MMUTable, PV_OFFSET);
#else
rt_hw_mmu_map_init(&rt_kernel_space, (void *)0x80000000, 0x10000000, MMUTable, 0);
#endif
rt_page_init(init_page_region);
rt_hw_mmu_setup(&rt_kernel_space, platform_mem_desc, platform_mem_desc_size);
/* init memory pool */
/* init memory pool */
#ifdef RT_USING_HEAP
rt_system_heap_init((void *)HEAP_BEGIN, (void *)HEAP_END);
#endif
@ -125,7 +133,13 @@ void rt_hw_board_aarch64_init(void)
rt_hw_gtimer_init();
FEarlyUartProbe();
FIOPadCfgInitialize(&iopad_ctrl, FIOPadLookupConfig(FIOPAD0_ID));
#ifdef RT_USING_SMART
iopad_ctrl.config.base_address = (uintptr)rt_ioremap((void *)iopad_ctrl.config.base_address, 0x2000);
#endif
/* compoent init */
#ifdef RT_USING_COMPONENTS_INIT
@ -141,12 +155,15 @@ void rt_hw_board_aarch64_init(void)
rt_thread_idle_sethook(idle_wfi);
#ifdef RT_USING_SMP
FPsciInit();
/* install IPI handle */
rt_hw_interrupt_set_priority(RT_SCHEDULE_IPI, 16);
rt_hw_ipi_handler_install(RT_SCHEDULE_IPI, rt_scheduler_ipi_handler);
rt_hw_interrupt_umask(RT_SCHEDULE_IPI);
#endif
}
#else
@ -156,25 +173,25 @@ void rt_hw_board_aarch32_init(void)
#if defined(RT_USING_SMART)
/* set io map range is 0xf0000000 ~ 0x10000000 , Memory Protection start address is 0xf0000000 - rt_mpr_size */
rt_hw_mmu_map_init(&rt_kernel_space, (void*)0xf0000000, 0x10000000, MMUTable, PV_OFFSET);
rt_hw_mmu_map_init(&rt_kernel_space, (void *)0xf0000000, 0x10000000, MMUTable, PV_OFFSET);
rt_page_init(init_page_region);
/* rt_kernel_space 在start_gcc.S 中被初始化，此函数将iomap 空间放置在kernel space 上 */
rt_hw_mmu_ioremap_init(&rt_kernel_space, (void*)0xf0000000, 0x10000000);
rt_hw_mmu_ioremap_init(&rt_kernel_space, (void *)0xf0000000, 0x10000000);
/* */
arch_kuser_init(&rt_kernel_space, (void*)0xffff0000);
arch_kuser_init(&rt_kernel_space, (void *)0xffff0000);
#else
/*
map kernel space memory (totally 1GB = 0x10000000), pv_offset = 0 if not RT_SMART:
0x80000000 ~ 0x80100000: kernel stack
0x80100000 ~ __bss_end: kernel code and data
*/
rt_hw_mmu_map_init(&rt_kernel_space, (void*)0x80000000, 0x10000000, MMUTable, 0);
rt_hw_mmu_ioremap_init(&rt_kernel_space, (void*)0x80000000, 0x10000000);
rt_hw_mmu_map_init(&rt_kernel_space, (void *)0x80000000, 0x10000000, MMUTable, 0);
rt_hw_mmu_ioremap_init(&rt_kernel_space, (void *)0x80000000, 0x10000000);
#endif
/* init memory pool */
/* init memory pool */
#ifdef RT_USING_HEAP
rt_system_heap_init((void *)HEAP_BEGIN, (void *)HEAP_END);
#endif
@ -189,8 +206,13 @@ void rt_hw_board_aarch32_init(void)
#endif
rt_uint32_t redist_addr = 0;
FEarlyUartProbe();
FIOPadCfgInitialize(&iopad_ctrl, FIOPadLookupConfig(FIOPAD0_ID));
#if defined(RT_USING_SMART)
redist_addr = (uint32_t)rt_ioremap(GICV3_RD_BASE_ADDR, 4 * 128*1024);
redist_addr = (uint32_t)rt_ioremap(GICV3_RD_BASE_ADDR, 4 * 128 * 1024);
iopad_ctrl.config.base_address = (uintptr)rt_ioremap((void *)iopad_ctrl.config.base_address, 0x2000);
#else
redist_addr = GICV3_RD_BASE_ADDR;
#endif
@ -242,6 +264,7 @@ void rt_hw_board_aarch32_init(void)
rt_thread_idle_sethook(idle_wfi);
#ifdef RT_USING_SMP
FPsciInit();
/* install IPI handle */
rt_hw_interrupt_set_priority(RT_SCHEDULE_IPI, 16);
rt_hw_ipi_handler_install(RT_SCHEDULE_IPI, rt_scheduler_ipi_handler);

12
bsp/phytium/board/board.h
View File

@ -9,6 +9,7 @@
* Date Author Notes
* 2022-10-26 huanghe first commit
* 2022-04-13 zhugengyu support RT-Smart
* 2023-07-27 liqiaozhong add gpio pin definition
*
*/
@ -17,6 +18,7 @@
#include "fparameters.h"
#include "phytium_cpu.h"
#include "fkernel.h"
#include "mmu.h"
#ifdef RT_USING_SMART
@ -44,6 +46,16 @@
#define PAGE_END (PAGE_START +PAGE_POOL_SIZE)
#endif
#ifdef RT_USING_PIN
/* gpio pin_index handle */
#define FGPIO_OPS_PIN_INDEX(ctrl, port, pin) SET_REG32_BITS(ctrl, 19, 12) | \
SET_REG32_BITS(port, 11, 8) | \
SET_REG32_BITS(pin, 7, 0)
#define FGPIO_OPS_PIN_CTRL_ID(pin_idx) GET_REG32_BITS(pin_idx, 19, 12)
#define FGPIO_OPS_PIN_PORT_ID(pin_idx) GET_REG32_BITS(pin_idx, 11, 8)
#define FGPIO_OPS_PIN_ID(pin_idx) GET_REG32_BITS(pin_idx, 7, 0)
#endif
void rt_hw_board_init(void);
#endif

7
bsp/phytium/board/e2000/memory_map.c
View File

@ -8,6 +8,7 @@
* Change Logs:
* Date Author Notes
* 2023-04-27 huanghe first version
* 2023-07-27 zhangyan add qspi io space
*
*/
@ -48,6 +49,12 @@ struct mem_desc platform_mem_desc[] = {
0x28000000U,
DEVICE_MEM
},
{
0x00001000U,
0x0FFFFFFFU,
0x00001000U,
DEVICE_MEM
},
};
#else
struct mem_desc platform_mem_desc[] =

13
bsp/phytium/board/phytium_cpu_id.S
View File

@ -1,3 +1,16 @@
/*
* Copyright (c) 2006-2021, RT-Thread Development Team
*
* SPDX-License-Identifier: Apache-2.0
*
* Email: opensource_embedded@phytium.com.cn
*
* Change Logs:
* Date Author Notes
* 2023-07-26 huanghe first commit
*
*/
#include "fparameters.h"
#include "sdkconfig.h"

6
bsp/phytium/board/secondary_cpu.c
View File

@ -9,6 +9,7 @@
* Date Author Notes
* 2022-10-26 huanghe first commit
* 2022-10-26 zhugengyu support aarch64
* 2023-07-26 huanghe update psci uage
*
*/
@ -82,13 +83,14 @@ void rt_hw_secondary_cpu_up(void)
#if defined(TARGET_ARMV8_AARCH64)
/* code */
rt_kprintf("cpu_mask = 0x%x \n", cpu_mask);
char *entry = (char *)_secondary_cpu_entry;
entry += PV_OFFSET;
PsciCpuOn(cpu_mask, (uintptr)entry);
FPsciCpuMaskOn(cpu_mask, (uintptr)entry);
__DSB();
#else
/* code */
PsciCpuOn(cpu_mask, (uintptr)rt_secondary_cpu_entry);
FPsciCpuMaskOn(cpu_mask, (uintptr)rt_secondary_cpu_entry);
__asm__ volatile("dsb" ::: "memory");
#endif

25
bsp/phytium/libraries/SConscript
View File

@ -19,7 +19,10 @@ if GetDepend(['TARGET_ARMV8_AARCH32']):
path += [STANDALONE_DIR + '/port/arch/armv8/aarch32']
elif GetDepend(['TARGET_ARMV8_AARCH64']):
src += Glob(STANDALONE_DIR+'/port/arch/armv8/aarch64/*.c') + Glob(STANDALONE_DIR+'/port/arch/armv8/aarch64/*.S')
path += [STANDALONE_DIR + '/port/arch/armv8/aarch64']
path += [STANDALONE_DIR + '/port/arch/armv8/aarch64']
src += Glob(STANDALONE_DIR+'/port/*.c')
path += [STANDALONE_DIR + '/port/*.h']
# board
src += Glob(STANDALONE_DIR+'/board/common/*.c') + Glob(STANDALONE_DIR+'/board/common/*.S')
@ -70,6 +73,26 @@ if GetDepend(['BSP_USING_QSPI']):
src += Glob(STANDALONE_DIR+'/drivers/qspi/fqspi/*.c') + Glob(STANDALONE_DIR+'/drivers/qspi/fqspi/*.S')
path += [STANDALONE_DIR + '/drivers/qspi/fqspi/']
## eth
if GetDepend(['BSP_USING_ETH']):
src += Glob(STANDALONE_DIR+'/drivers/eth/fxmac/*.c') + Glob(STANDALONE_DIR+'/drivers/eth/fxmac/*.S')
path += [STANDALONE_DIR + '/drivers/eth/fxmac/'] + [STANDALONE_DIR + '/drivers/eth/fxmac/phy/']
## sdio
if GetDepend(['BSP_USING_SDIO']):
src += Glob(STANDALONE_DIR+'/drivers/mmc/fsdio/*.c') + Glob(STANDALONE_DIR+'/drivers/mmc/fsdio/*.S')
path += [STANDALONE_DIR + '/drivers/mmc/fsdio/']
## gpio
if GetDepend(['BSP_USING_GPIO']):
src += Glob(STANDALONE_DIR+'/drivers/pin/fgpio/*.c') + Glob(STANDALONE_DIR+'/drivers/pin/fgpio/*.S')
path += [STANDALONE_DIR + '/drivers/pin/fgpio/']
## iopad
if GetDepend(['ENABLE_IOPAD']):
src += Glob(STANDALONE_DIR+'/drivers/iopad/fiopad/*.c') + Glob(STANDALONE_DIR+'/drivers/iopad/fiopad/*.S')
path += [STANDALONE_DIR + '/drivers/iopad/fiopad/']
# phytium ports rt-thread drivers
PORT_DRV_DIR = cwd + '/drivers'

58
bsp/phytium/libraries/drivers/Kconfig
View File

@ -19,7 +19,7 @@ menu "On-chip Peripheral Drivers"
menuconfig BSP_USING_SPI
bool "Enable Spi"
default y
default n
select USE_SPI # sdk spi component
select RT_USING_SPI
if BSP_USING_SPI
@ -42,17 +42,69 @@ menu "On-chip Peripheral Drivers"
menuconfig BSP_USING_CAN
bool "Enable CAN"
default y
default n
select RT_USING_CAN
select RT_CAN_USING_HDR
select RT_CAN_USING_CANFD
menuconfig BSP_USING_GPIO
bool "Enable GPIO"
default n
select RT_USING_PIN
menuconfig BSP_USING_QSPI
bool "Enable QSPI"
default y
default n
select RT_USING_QSPI
select RT_USING_SPI
if BSP_USING_QSPI
config USING_QSPI_CHANNEL0
bool "using qspi channel_0"
default n
config USING_QSPI_CHANNEL1
bool "using qspi channel_1"
default n
endif
menuconfig BSP_USING_ETH
bool "Enable ETH"
default y
select USE_ETH
if BSP_USING_ETH
config RT_LWIP_PBUF_POOL_BUFSIZE
int "The size of each pbuf in the pbuf pool"
range 1500 2000
default 1700
endif
menuconfig BSP_USING_SDIO
bool "Enable SDIO"
default y
select RT_USING_SDIO
if BSP_USING_SDIO
config BSP_USING_SDCARD_FATFS
bool "Enable SDCARD (FATFS)"
select RT_USING_DFS_ELMFAT
default y
choice
prompt "Choose a card to mount"
default USING_SDIO1
config USING_SDIO0
bool "Use SDIO0"
config USING_SDIO1
bool "Use SDIO1"
config USING_EMMC
bool "Use EMMC"
endchoice
endif
endmenu
menu "Board extended module Drivers"

394
bsp/phytium/libraries/drivers/drv_gpio.c Normal file
View File

@ -0,0 +1,394 @@
/*
* Copyright (c) 2006-2023, RT-Thread Development Team
*
* SPDX-License-Identifier: Apache-2.0
*
* Email: opensource_embedded@phytium.com.cn
*
* Change Logs:
* Date Author Notes
* 2023/7/24 liqiaozhong first add, support intr
*
*/
#include <rtthread.h>
#include <rtdevice.h>
#include "interrupt.h"
#include "rtdbg.h"
#ifdef RT_USING_SMART
#include "ioremap.h"
#endif
#include <string.h>
#if defined(TARGET_E2000)
#include "fparameters.h"
#endif
#include "fkernel.h"
#include "fpinctrl.h"
#include "fcpu_info.h"
#include "ftypes.h"
#include "board.h"
#ifdef RT_USING_PIN
#include "fiopad.h"
#include "fgpio.h"
#include "drv_gpio.h"
/**************************** Type Definitions *******************************/
typedef void (*FGpioOpsIrqHandler)(s32 vector, void *param);
typedef struct
{
FGpioDirection direction;
boolean en_irq;
FGpioIrqType irq_type;
FGpioOpsIrqHandler irq_handler;
void *irq_args;
} FGpioOpsPinConfig;
typedef struct
{
FGpio ctrl;
FGpioPin pins[FGPIO_PORT_NUM][FGPIO_PIN_NUM];
FGpioOpsPinConfig pin_config[FGPIO_PORT_NUM][FGPIO_PIN_NUM];
boolean init_ok;
} FGpioOps;
/***************** Macros (Inline Functions) Definitions *********************/
#if defined(TARGET_E2000)
#define FGPIO_VERSION_2
#endif
/************************** Variable Definitions *****************************/
static FGpioOps gpio[FGPIO_NUM];
extern FIOPadCtrl iopad_ctrl;
/*******************************Api Functions*********************************/
static void FGpioOpsSetupCtrlIRQ(FGpio *ctrl)
{
u32 cpu_id;
u32 irq_num = ctrl->config.irq_num[0];
GetCpuId(&cpu_id);
LOG_D("In FGpioOpsSetupCtrlIRQ() -> cpu_id %d, irq_num %d\r\n", cpu_id, irq_num);
rt_hw_interrupt_set_target_cpus(irq_num, cpu_id);
rt_hw_interrupt_set_priority(irq_num, ctrl->config.irq_priority); /* setup interrupt */
rt_hw_interrupt_install(irq_num, FGpioInterruptHandler, ctrl, NULL); /* register intr handler */
rt_hw_interrupt_umask(irq_num);
return;
}
/* setup gpio pin interrupt */
static void FGpioOpsSetupPinIRQ(FGpio *ctrl, FGpioPin *const pin, FGpioOpsPinConfig *config)
{
u32 cpu_id;
u32 irq_num = ctrl->config.irq_num[pin->index.pin];
GetCpuId(&cpu_id);
LOG_D("in FGpioOpsSetupPinIRQ() -> cpu_id %d, irq_num %d", cpu_id, irq_num);
rt_hw_interrupt_set_target_cpus(irq_num, cpu_id);
rt_hw_interrupt_set_priority(irq_num, ctrl->config.irq_priority); /* setup interrupt */
rt_hw_interrupt_install(irq_num, FGpioInterruptHandler, config->irq_args, NULL); /* register intr handler */
rt_hw_interrupt_umask(irq_num);
return;
}
void FIOPadSetGpioMux(u32 ctrl_id_p, u32 pin_id_p)
{
#if defined(TARGET_E2000D)
if (ctrl_id_p == FGPIO4_ID)
{
switch (pin_id_p)
{
case 11: /* gpio 4-a-11 */
FIOPadSetFunc(&iopad_ctrl, FIOPAD_AC45_REG0_OFFSET, FIOPAD_FUNC6);
break;
case 12: /* gpio 4-a-12 */
FIOPadSetFunc(&iopad_ctrl, FIOPAD_AE43_REG0_OFFSET, FIOPAD_FUNC6);
break;
default:
LOG_E("Unsupported ctrl pin.");
RT_ASSERT(0);
break;
}
}
else
{
LOG_E("Unsupported ctrl.");
RT_ASSERT(0);
}
#endif
#if defined(TARGET_E2000Q)
if (ctrl_id_p == FGPIO4_ID)
{
switch (pin_id_p)
{
case 11: /* gpio 4-a-11 */
FIOPadSetFunc(&iopad_ctrl, FIOPAD_AC49_REG0_OFFSET, FIOPAD_FUNC6);
break;
case 12: /* gpio 4-a-12 */
FIOPadSetFunc(&iopad_ctrl, FIOPAD_AE47_REG0_OFFSET, FIOPAD_FUNC6);
break;
default:
LOG_E("Unsupported ctrl pin.");
RT_ASSERT(0);
break;
}
}
else
{
LOG_E("Unsupported ctrl.");
RT_ASSERT(0);
}
#endif
}
/* on E2000, if u want use GPIO-4-11, set pin = FGPIO_OPS_PIN_INDEX(4, 0, 11) */
static void drv_pin_mode(struct rt_device *device, rt_base_t pin, rt_uint8_t mode)
{
u32 ctrl_id = FGPIO_OPS_PIN_CTRL_ID(pin);
u32 port_id = FGPIO_OPS_PIN_PORT_ID(pin);
u32 pin_id = FGPIO_OPS_PIN_ID(pin);
FGpioPinId gpio_pin_id;
FError err = FGPIO_SUCCESS;
FGpio *instance = &gpio[ctrl_id].ctrl;
FGpioPin *pin_instance = &gpio[ctrl_id].pins[port_id][pin_id];
FGpioOpsPinConfig *pin_config = &gpio[ctrl_id].pin_config[port_id][pin_id];
if (ctrl_id >= FGPIO_NUM)
{
LOG_E("ctrl_id too large!!!");
return;
}
if (FALSE == gpio[ctrl_id].init_ok) /* init ctrl if needed */
{
FGpioConfig input_cfg = *FGpioLookupConfig(ctrl_id);
memset(instance, 0, sizeof(*instance));
#ifdef RT_USING_SMART
input_cfg.base_addr = (uintptr)rt_ioremap((void *)input_cfg.base_addr, 0x1000);
#endif
err = FGpioCfgInitialize(instance, &input_cfg);
if (FGPIO_SUCCESS != err)
{
LOG_E("Ctrl: %d init fail!!!\n", ctrl_id);
return;
}
gpio[ctrl_id].init_ok = TRUE;
}
FIOPadSetGpioMux(ctrl_id, pin_id);
if (FT_COMPONENT_IS_READY == pin_instance->is_ready)
{
FGpioPinDeInitialize(pin_instance);
}
gpio_pin_id.ctrl = ctrl_id;
gpio_pin_id.port = port_id;
gpio_pin_id.pin = pin_id;
err = FGpioPinInitialize(instance, pin_instance, gpio_pin_id);
if (FGPIO_SUCCESS != err)
{
LOG_E("Pin %d-%c-%d init fail!!!\n",
ctrl_id,
port_id == 0 ? 'a' : 'b',
pin_id);
return;
}
switch (mode)
{
case PIN_MODE_OUTPUT:
pin_config->direction = FGPIO_DIR_OUTPUT;
pin_config->en_irq = FALSE;
break;
case PIN_MODE_INPUT:
pin_config->direction = FGPIO_DIR_INPUT;
pin_config->en_irq = TRUE;
pin_config->irq_type = FGPIO_IRQ_TYPE_EDGE_RISING;
break;
default:
rt_kprintf("Not support mode %d!!!\n", mode);
break;
}
FGpioSetDirection(pin_instance, pin_config->direction);
rt_kprintf("Init GPIO-%d-%c-%d as an %sput pin\r\n",
ctrl_id,
port_id,
pin_id, pin_config->direction == FGPIO_DIR_OUTPUT ? "out" : "in");
}
void drv_pin_write(struct rt_device *device, rt_base_t pin, rt_uint8_t value)
{
u32 ctrl_id = FGPIO_OPS_PIN_CTRL_ID(pin);
u32 port_id = FGPIO_OPS_PIN_PORT_ID(pin);
u32 pin_id = FGPIO_OPS_PIN_ID(pin);
FGpioPin *pin_instance = &gpio[ctrl_id].pins[port_id][pin_id];
if (pin_instance == RT_NULL)
{
rt_kprintf("Pin %d-%c-%d not set mode\n",
ctrl_id,
port_id == 0 ? 'a' : 'b',
pin_id);
return;
}
FGpioSetOutputValue(pin_instance, (value == PIN_HIGH) ? FGPIO_PIN_HIGH : FGPIO_PIN_LOW);
}
rt_int8_t drv_pin_read(struct rt_device *device, rt_base_t pin)
{
u32 ctrl_id = FGPIO_OPS_PIN_CTRL_ID(pin);
u32 port_id = FGPIO_OPS_PIN_PORT_ID(pin);
u32 pin_id = FGPIO_OPS_PIN_ID(pin);
FGpioPin *pin_instance = &gpio[ctrl_id].pins[port_id][pin_id];
if (pin_instance == RT_NULL)
{
rt_kprintf("Pin %d-%c-%d not set mode\n",
ctrl_id,
port_id == 0 ? 'a' : 'b',
pin_id);
return RT_ERROR;
}
return FGpioGetInputValue(pin_instance) == FGPIO_PIN_HIGH ? PIN_HIGH : PIN_LOW;
}
rt_err_t drv_pin_attach_irq(struct rt_device *device, rt_base_t pin,
rt_uint8_t mode, void (*hdr)(void *args), void *args)
{
u32 ctrl_id = FGPIO_OPS_PIN_CTRL_ID(pin);
u32 port_id = FGPIO_OPS_PIN_PORT_ID(pin);
u32 pin_id = FGPIO_OPS_PIN_ID(pin);
rt_base_t level;
FGpio *instance = &gpio[ctrl_id].ctrl;
FGpioPin *pin_instance = &gpio[ctrl_id].pins[port_id][pin_id];
FGpioOpsPinConfig *pin_config = &gpio[ctrl_id].pin_config[port_id][pin_id];
level = rt_hw_interrupt_disable();
pin_config->irq_handler = (FGpioOpsIrqHandler)hdr;
pin_config->irq_args = args;
if (pin_instance == RT_NULL)
{
LOG_E("GPIO%d-%c-%d not init yet.\n", ctrl_id, port_id == 0 ? 'a' : 'b', pin_id);
return RT_ERROR;
}
if (pin_config->en_irq)
{
FGpioSetInterruptMask(pin_instance, FALSE);
FGpioPinId pin_of_ctrl =
{
.ctrl = ctrl_id,
.port = FGPIO_PORT_A,
.pin = FGPIO_PIN_0
};
if (FGPIO_IRQ_BY_CONTROLLER == FGpioGetPinIrqSourceType(pin_of_ctrl)) /* setup for ctrl report interrupt */
{
FGpioOpsSetupCtrlIRQ(instance);
LOG_I("GPIO-%d report irq by controller", ctrl_id);
}
else if (FGPIO_IRQ_BY_PIN == FGpioGetPinIrqSourceType(pin_of_ctrl))
{
FGpioOpsSetupPinIRQ(instance, pin_instance, pin_config);
LOG_I("GPIO-%d report irq by pin", ctrl_id);
}
switch (mode)
{
case PIN_IRQ_MODE_RISING:
pin_config->irq_type = FGPIO_IRQ_TYPE_EDGE_RISING;
break;
case PIN_IRQ_MODE_FALLING:
pin_config->irq_type = FGPIO_IRQ_TYPE_EDGE_FALLING;
break;
case PIN_IRQ_MODE_LOW_LEVEL:
pin_config->irq_type = FGPIO_IRQ_TYPE_LEVEL_LOW;
break;
case PIN_IRQ_MODE_HIGH_LEVEL:
pin_config->irq_type = FGPIO_IRQ_TYPE_LEVEL_HIGH;
break;
default:
LOG_E("Do not spport irq_mode: %d\n", mode);
break;
}
FGpioSetInterruptType(pin_instance, pin_config->irq_type);
FGpioRegisterInterruptCB(pin_instance, pin_config->irq_handler,
pin_config->irq_args, TRUE); /* register intr callback */
}
rt_hw_interrupt_enable(level);
return RT_EOK;
}
rt_err_t drv_pin_detach_irq(struct rt_device *device, rt_base_t pin)
{
u32 ctrl_id = FGPIO_OPS_PIN_CTRL_ID(pin);
u32 port_id = FGPIO_OPS_PIN_PORT_ID(pin);
u32 pin_id = FGPIO_OPS_PIN_ID(pin);
rt_base_t level;
FGpioPin *pin_instance = &gpio[ctrl_id].pins[port_id][pin_id];
FGpioOpsPinConfig *pin_config = &gpio[ctrl_id].pin_config[port_id][pin_id];
if (pin_instance == RT_NULL)
{
rt_kprintf("pin %d-%c-%d not set mode\n",
ctrl_id,
port_id == 0 ? 'a' : 'b',
pin_id);
return RT_ERROR;
}
level = rt_hw_interrupt_disable();
pin_config->irq_handler = RT_NULL;
pin_config->irq_args = RT_NULL;
rt_hw_interrupt_enable(level);
return RT_EOK;
}
rt_err_t drv_pin_irq_enable(struct rt_device *device, rt_base_t pin, rt_uint8_t enabled)
{
u32 ctrl_id = FGPIO_OPS_PIN_CTRL_ID(pin);
u32 port_id = FGPIO_OPS_PIN_PORT_ID(pin);
u32 pin_id = FGPIO_OPS_PIN_ID(pin);
FGpioPin *pin_instance = &gpio[ctrl_id].pins[port_id][pin_id];
if (pin_instance == RT_NULL)
{
rt_kprintf("Pin %d-%c-%d not set mode\n",
ctrl_id,
port_id == 0 ? 'a' : 'b',
pin_id);
return RT_ERROR;
}
FGpioSetInterruptMask(pin_instance, enabled);
return RT_EOK;
}
const struct rt_pin_ops drv_pin_ops =
{
.pin_mode = drv_pin_mode,
.pin_write = drv_pin_write,
.pin_read = drv_pin_read,
.pin_attach_irq = drv_pin_attach_irq,
.pin_detach_irq = drv_pin_detach_irq,
.pin_irq_enable = drv_pin_irq_enable,
.pin_get = RT_NULL
};
int ft_pin_init(void)
{
rt_err_t ret = RT_EOK;
ret = rt_device_pin_register("pin", &drv_pin_ops, RT_NULL);
rt_kprintf("Register pin with return: %d\n", ret);
return ret;
}
INIT_DEVICE_EXPORT(ft_pin_init);
#endif /* RT_USING_PIN */

20
bsp/phytium/libraries/drivers/drv_gpio.h Normal file
View File

@ -0,0 +1,20 @@
/*
* Copyright (c) 2006-2023, RT-Thread Development Team
*
* SPDX-License-Identifier: Apache-2.0
*
* Email: opensource_embedded@phytium.com.cn
*
* Change Logs:
* Date Author Notes
* 2023/7/24 liqiaozhong first add, support intr
*
*/
#ifndef __DRV_GPIO_H__
#define __DRV_GPIO_H__
/**************************** Type Definitions *******************************/
/************************** Function Prototypes ******************************/
#endif

151
bsp/phytium/libraries/drivers/drv_qspi.c
View File

@ -10,72 +10,72 @@
* 2023-03-20 zhangyan first version
*
*/
#include "drv_qspi.h"
#include "sdkconfig.h"
#include "rtconfig.h"
#ifdef RT_USING_QSPI
#include <rtthread.h>
#include "rtdevice.h"
#include "drv_qspi.h"
#include "fqspi_flash.h"
#include "fdebug.h"
#include "fpinctrl.h"
#define FQSPI_DEBUG_TAG "FQSPI"
#define FQSPI_ERROR(format, ...) FT_DEBUG_PRINT_E(FQSPI_DEBUG_TAG, format, ##__VA_ARGS__)
#define FQSPI_WARN(format, ...) FT_DEBUG_PRINT_W(FQSPI_DEBUG_TAG, format, ##__VA_ARGS__)
#define FQSPI_INFO(format, ...) FT_DEBUG_PRINT_I(FQSPI_DEBUG_TAG, format, ##__VA_ARGS__)
#define FQSPI_DEBUG(format, ...) FT_DEBUG_PRINT_D(FQSPI_DEBUG_TAG, format, ##__VA_ARGS__)
#include "rtdbg.h"
#include "fiopad.h"
#define DAT_LENGTH 128
struct phytium_qspi_bus
static phytium_qspi_bus phytium_qspi =
{
char *name;
rt_uint32_t init; /* 0 is init already */
FQspiCtrl fqspi;
struct rt_spi_bus qspi_bus;
.fqspi_id = FQSPI0_ID,
};
static struct phytium_qspi_bus phytium_qspi; /* phytium qspi bus handle */
static struct rt_qspi_device *qspi_device; /* phytium device bus handle */
static char qspi_bus_name[RT_NAME_MAX] = "QSPIBUS";
static char qspi_dev_name[RT_NAME_MAX] = "QSPIDEV";
extern FIOPadCtrl iopad_ctrl;
rt_err_t FQspiInit(FQspiCtrl *fqspi)
rt_err_t FQspiInit(phytium_qspi_bus *phytium_qspi_bus)
{
u32 qspi_id = FQSPI0_ID;
FError ret = FT_SUCCESS;
rt_uint32_t qspi_id = phytium_qspi_bus->fqspi_id;
#if defined(CONFIG_TARGET_E2000)
FIOPadSetQspiMux(qspi_id, FQSPI_CS_0);
FIOPadSetQspiMux(qspi_id, FQSPI_CS_1);
#ifdef USING_QSPI_CHANNEL0
FIOPadSetFunc(&iopad_ctrl, FIOPAD_AR51_REG0_OFFSET, FIOPAD_FUNC0);
FIOPadSetFunc(&iopad_ctrl, FIOPAD_AR45_REG0_OFFSET, FIOPAD_FUNC0);
#endif
FQspiDeInitialize(fqspi);
#ifdef USING_QSPI_CHANNEL1
FIOPadSetFunc(&iopad_ctrl, FIOPAD_AR55_REG0_OFFSET, FIOPAD_FUNC0);
FIOPadSetFunc(&iopad_ctrl, FIOPAD_AR49_REG0_OFFSET, FIOPAD_FUNC0);
#endif
FQspiDeInitialize(&(phytium_qspi_bus->fqspi));
FQspiConfig pconfig = *FQspiLookupConfig(qspi_id);
#ifdef RT_USING_SMART
pconfig.base_addr = (uintptr)rt_ioremap((void *)pconfig.base_addr, 0x1000);
#endif
/* Norflash init, include reset and read flash_size */
ret = FQspiCfgInitialize(fqspi, &pconfig);
ret = FQspiCfgInitialize(&(phytium_qspi_bus->fqspi), &pconfig);
if (FT_SUCCESS != ret)
{
FQSPI_DEBUG("Qspi init failed.\n");
LOG_E("Qspi init failed.\n");
return RT_ERROR;
}
else
{
FQSPI_DEBUG("Qspi init successfully.\n");
rt_kprintf("Qspi init successfully.\n");
}
/* Detect connected flash infomation */
ret = FQspiFlashDetect(fqspi);
ret = FQspiFlashDetect(&(phytium_qspi_bus->fqspi));
if (FT_SUCCESS != ret)
{
FQSPI_DEBUG("Qspi flash detect failed.\n");
LOG_E("Qspi flash detect failed.\n");
return RT_ERROR;
}
else
{
FQSPI_DEBUG("Qspi flash detect successfully.\n");
rt_kprintf("Qspi flash detect successfully.\n");
}
return RT_EOK;
@ -85,15 +85,15 @@ static rt_err_t phytium_qspi_configure(struct rt_spi_device *device, struct rt_s
{
RT_ASSERT(device != RT_NULL);
RT_ASSERT(configuration != RT_NULL);
struct phytium_qspi_bus *qspi_bus;
phytium_qspi_bus *qspi_bus;
qspi_bus = (struct phytium_qspi_bus *) device->bus->parent.user_data;
rt_err_t ret = RT_EOK;
ret = FQspiInit(&(qspi_bus->fqspi));
ret = FQspiInit(qspi_bus);
if (RT_EOK != ret)
{
qspi_bus->init = RT_FALSE;
FQSPI_DEBUG("Qspi init failed!!!\n");
rt_kprintf("Qspi init failed!!!\n");
return RT_ERROR;
}
qspi_bus->init = RT_EOK;
@ -105,38 +105,47 @@ static rt_uint32_t phytium_qspi_xfer(struct rt_spi_device *device, struct rt_spi
{
RT_ASSERT(device != RT_NULL);
RT_ASSERT(message != RT_NULL);
struct phytium_qspi_bus *qspi_bus;
phytium_qspi_bus *qspi_bus;
struct rt_qspi_message *qspi_message = (struct rt_qspi_message *)message;
rt_uint32_t cmd = qspi_message->instruction.content;
rt_uint32_t flash_addr = qspi_message->address.content;
rt_uint8_t *rcvb = message->recv_buf;
rt_uint8_t *sndb = message->send_buf;
FError ret = FT_SUCCESS;
qspi_bus = (struct phytium_qspi_bus *) device->bus->parent.user_data;
#ifdef USING_QSPI_CHANNEL0
qspi_bus->fqspi.config.channel = 0;
#endif
#ifdef USING_QSPI_CHANNEL1
qspi_bus->fqspi.config.channel = 1;
#endif
uintptr addr = qspi_bus->fqspi.config.mem_start + qspi_bus->fqspi.config.channel * qspi_bus->fqspi.flash_size + flash_addr;
#ifdef RT_USING_SMART
addr = (uintptr)rt_ioremap((void *)addr, 0x2000);
#endif
/*Distinguish the write mode according to different commands*/
if (cmd == FQSPI_FLASH_CMD_PP||cmd == FQSPI_FLASH_CMD_QPP||cmd ==FQSPI_FLASH_CMD_4PP||cmd ==FQSPI_FLASH_CMD_4QPP )
if (cmd == FQSPI_FLASH_CMD_PP || cmd == FQSPI_FLASH_CMD_QPP || cmd == FQSPI_FLASH_CMD_4PP || cmd == FQSPI_FLASH_CMD_4QPP)
{
char *strs = (char *)message->send_buf;
rt_uint8_t len = strlen(strs) + 1;
rt_uint8_t *wr_buf = NULL;
wr_buf = (rt_uint8_t *)rt_malloc(DAT_LENGTH * sizeof(rt_uint8_t));
rt_memcpy(wr_buf, strs, len);
message->length = len;
rt_uint8_t len = message->length;
rt_memcpy(wr_buf, (char *)message->send_buf, len);
ret = FQspiFlashErase(&(qspi_bus->fqspi), FQSPI_FLASH_CMD_SE, flash_addr);
if (FT_SUCCESS != ret)
{
FQSPI_DEBUG("Failed to erase mem, test result 0x%x.\r\n", ret);
LOG_E("Failed to erase mem, test result 0x%x.\r\n", ret);
return RT_ERROR;
}
/* write norflash data */
ret = FQspiFlashWriteData(&(qspi_bus->fqspi), cmd, flash_addr, wr_buf, len);
ret = FQspiFlashWriteData(&(qspi_bus->fqspi), cmd, addr, wr_buf, len);
if (FT_SUCCESS != ret)
{
FQSPI_DEBUG("Failed to write mem, test result 0x%x.\r\n", ret);
LOG_E("Failed to write mem, test result 0x%x.\r\n", ret);
return RT_ERROR;
}
else
@ -149,8 +158,8 @@ static rt_uint32_t phytium_qspi_xfer(struct rt_spi_device *device, struct rt_spi
}
/*Distinguish the read mode according to different commands*/
if (cmd == FQSPI_FLASH_CMD_READ||cmd == FQSPI_FLASH_CMD_4READ||cmd == FQSPI_FLASH_CMD_FAST_READ||cmd == FQSPI_FLASH_CMD_4FAST_READ||
cmd == FQSPI_FLASH_CMD_DUAL_READ||cmd == FQSPI_FLASH_CMD_QIOR||cmd == FQSPI_FLASH_CMD_4QIOR)
if (cmd == FQSPI_FLASH_CMD_READ || cmd == FQSPI_FLASH_CMD_4READ || cmd == FQSPI_FLASH_CMD_FAST_READ || cmd == FQSPI_FLASH_CMD_4FAST_READ ||
cmd == FQSPI_FLASH_CMD_DUAL_READ || cmd == FQSPI_FLASH_CMD_QIOR || cmd == FQSPI_FLASH_CMD_4QIOR)
{
rt_uint8_t *rd_buf = NULL;
rd_buf = (rt_uint8_t *)rt_malloc(DAT_LENGTH * sizeof(rt_uint8_t));
@ -159,15 +168,15 @@ static rt_uint32_t phytium_qspi_xfer(struct rt_spi_device *device, struct rt_spi
if (FT_SUCCESS != ret)
{
FQSPI_DEBUG("Failed to config read, test result 0x%x.\r\n", ret);
rt_kprintf("Failed to config read, test result 0x%x.\r\n", ret);
return RT_ERROR;
}
/* read norflash data */
size_t read_len = FQspiFlashReadData(&(qspi_bus->fqspi), flash_addr, rd_buf, DAT_LENGTH);
size_t read_len = FQspiFlashReadData(&(qspi_bus->fqspi), addr, rd_buf, DAT_LENGTH);
message->length = read_len;
if (read_len != DAT_LENGTH)
{
FQSPI_DEBUG("Failed to read mem, read len = %d.\r\n", read_len);
rt_kprintf("Failed to read mem, read len = %d.\r\n", read_len);
return RT_ERROR;
}
else
@ -176,19 +185,19 @@ static rt_uint32_t phytium_qspi_xfer(struct rt_spi_device *device, struct rt_spi
message->recv_buf = rd_buf;
rt_free(rd_buf);
}
FtDumpHexByte(message->recv_buf, DAT_LENGTH);
FtDumpHexByte(message->recv_buf, read_len);
return RT_EOK;
return RT_EOK;
}
if (rcvb)
{
if (cmd == FQSPI_FLASH_CMD_RDID||cmd == FQSPI_FLASH_CMD_RDSR1||cmd == FQSPI_FLASH_CMD_RDSR2 ||cmd == FQSPI_FLASH_CMD_RDSR3)
if (cmd == FQSPI_FLASH_CMD_RDID || cmd == FQSPI_FLASH_CMD_RDSR1 || cmd == FQSPI_FLASH_CMD_RDSR2 || cmd == FQSPI_FLASH_CMD_RDSR3)
{
ret |= FQspiFlashSpecialInstruction(&(qspi_bus->fqspi), cmd, rcvb, sizeof(rcvb));
if (FT_SUCCESS != ret)
{
FQSPI_DEBUG("Failed to read flash information.\n");
LOG_E("Failed to read flash information.\n");
return RT_ERROR;
}
}
@ -201,14 +210,14 @@ static rt_uint32_t phytium_qspi_xfer(struct rt_spi_device *device, struct rt_spi
ret |= FQspiFlashEnableWrite(&(qspi_bus->fqspi));
if (FT_SUCCESS != ret)
{
FQSPI_DEBUG("Failed to enable flash reg write.\n");
LOG_E("Failed to enable flash reg write.\n");
return RT_ERROR;
}
ret |= FQspiFlashWriteReg(&(qspi_bus->fqspi), cmd, sndb, 1);
if (FT_SUCCESS != ret)
{
FQSPI_DEBUG("Failed to write flash reg.\n");
LOG_E("Failed to write flash reg.\n");
return RT_ERROR;
}
@ -232,7 +241,7 @@ rt_err_t phytium_qspi_bus_attach_device(const char *bus_name, const char *device
qspi_device = (struct rt_qspi_device *)rt_malloc(sizeof(struct rt_qspi_device));
if (qspi_device == RT_NULL)
{
FQSPI_DEBUG("Qspi bus attach device failed.");
LOG_E("Qspi bus attach device failed.");
result = RT_ENOMEM;
goto __exit;
}
@ -247,23 +256,23 @@ __exit:
}
return result;
}
return result;
}
}
int rt_hw_qspi_init(void)
{
int i = 0;
int result = RT_EOK;
phytium_qspi.qspi_bus.parent.user_data = &phytium_qspi;
if(rt_qspi_bus_register(&phytium_qspi.qspi_bus, qspi_bus_name , &phytium_qspi_ops) == RT_EOK)
if (rt_qspi_bus_register(&phytium_qspi.qspi_bus, qspi_bus_name, &phytium_qspi_ops) == RT_EOK)
{
rt_kprintf("Qspi bus register successfully!!!\n");
}
else
{
FQSPI_DEBUG("Qspi bus register Failed!!!\n");
LOG_E("Qspi bus register Failed!!!\n");
result = -RT_ERROR;
}
@ -288,16 +297,17 @@ rt_err_t qspi_init()
/*read cmd example message improvement*/
void ReadCmd(struct rt_spi_message *spi_message)
{
struct rt_qspi_message *message = (struct rt_qspi_message*) spi_message;
struct rt_qspi_message *message = (struct rt_qspi_message *) spi_message;
message->address.content = 0x360000 ;/*Flash address*/
message->instruction.content = 0x03 ;/*read cmd*/
rt_qspi_transfer_message(qspi_device, message);
}
/*write cmd example message improvement*/
void WriteCmd(struct rt_spi_message *spi_message)
{
struct rt_qspi_message *message = (struct rt_qspi_message*) spi_message;
struct rt_qspi_message *message = (struct rt_qspi_message *) spi_message;
message->address.content = 0x360000 ;/*Flash address*/
message->instruction.content = 0x02 ;/*write cmd*/
rt_qspi_transfer_message(qspi_device, message);
@ -310,24 +320,27 @@ void qspi_thread(void *parameter)
qspi_init();
/*Read and write flash chip fixed area repeatedly*/
write_message.send_buf = "111111111111111111111111";
write_message.send_buf = "phytium";
write_message.length = strlen((char *)write_message.send_buf) + 1;
WriteCmd(&write_message);
ReadCmd(&read_message);
write_message.send_buf = "222222222222222222222222";
write_message.send_buf = "phytium hello world!";
write_message.length = strlen((char *)write_message.send_buf) + 1;
WriteCmd(&write_message);
ReadCmd(&read_message);
write_message.send_buf = "333333333333333333333333";
write_message.send_buf = "Welcome to phytium chip";
write_message.length = strlen((char *)write_message.send_buf) + 1;
WriteCmd(&write_message);
ReadCmd(&read_message);
rt_uint8_t recv;
rt_uint8_t cmd = 0x9F;/*read the flash status reg2*/
res = rt_qspi_send_then_recv(qspi_device, &cmd, sizeof(cmd), &recv, sizeof(recv));
RT_ASSERT(res!=RT_EOK);
RT_ASSERT(res != RT_EOK);
rt_kprintf("The status reg = %x \n" ,recv);
rt_kprintf("The status reg = %x \n", recv);
return 0;
}
@ -336,13 +349,13 @@ rt_err_t qspi_sample(int argc, char *argv[])
{
rt_thread_t thread;
rt_err_t res;
thread = rt_thread_create("qspi_thread", qspi_thread, RT_NULL, 1024, 25, 10);
thread = rt_thread_create("qspi_thread", qspi_thread, RT_NULL, 2048, 25, 10);
res = rt_thread_startup(thread);
RT_ASSERT(res==RT_EOK);
RT_ASSERT(res == RT_EOK);
return res;
}
/* Enter qspi_sample command for testing */
MSH_CMD_EXPORT(qspi_sample, qspi sample);
#endif

14
bsp/phytium/libraries/drivers/drv_qspi.h
View File

@ -14,8 +14,12 @@
#ifndef __DRT_QSPI_H__
#define __DRT_QSPI_H__
#include <rtthread.h>
#include "rtconfig.h"
#ifdef RT_USING_QSPI
#include <rtthread.h>
#include "rtdevice.h"
#include "fqspi_flash.h"
#define PHYTIUM_QSPI_NAME "qspi"
#ifdef __cplusplus
@ -23,6 +27,14 @@ extern "C"
{
#endif
typedef struct
{
rt_uint32_t fqspi_id;
rt_uint32_t init; /* 0 is init already */
FQspiCtrl fqspi;
struct rt_spi_bus qspi_bus;
} phytium_qspi_bus;
rt_err_t phytium_qspi_bus_attach_device(const char *bus_name, const char *device_name);
#ifdef __cplusplus

393
bsp/phytium/libraries/drivers/drv_sdio.c Normal file
View File

@ -0,0 +1,393 @@
/*
* Copyright (c) 2006-2023, RT-Thread Development Team
*
* SPDX-License-Identifier: Apache-2.0
*
* Email: opensource_embedded@phytium.com.cn
*
* Change Logs:
* Date Author Notes
* 2023/7/11 liqiaozhong init SD card and mount file system
*/
/***************************** Include Files *********************************/
#include <rthw.h>
#include <rtthread.h>
#ifdef BSP_USING_SDIO
#include <rtdevice.h>
#include <rtdbg.h>
#include <drivers/mmcsd_core.h>
#ifdef RT_USING_SMART
#include "ioremap.h"
#endif
#include "mm_aspace.h"
#include "ftypes.h"
#if defined(TARGET_E2000)
#include "fparameters.h"
#endif
#include "fparameters_comm.h"
#include "fsdio.h"
#include "fsdio_hw.h"
#include "drv_sdio.h"
/************************** Constant Definitions *****************************/
#ifdef USING_SDIO0
#define SDIO_CONTROLLER_ID FSDIO0_ID
#elif defined (USING_SDIO1)
#define SDIO_CONTROLLER_ID FSDIO1_ID
#elif defined (USING_EMMC)
#define SDIO_CONTROLLER_ID FSDIO0_ID
#endif
#define SDIO_TF_CARD_HOST_ID 0x1
#define SDIO_MALLOC_CAP_DESC 256U
#define SDIO_DMA_ALIGN 512U
#define SDIO_DMA_BLK_SZ 512U
#define SDIO_VALID_OCR 0x00FFFF80 /* supported voltage range is 1.65v-3.6v (VDD_165_195-VDD_35_36) */
#define SDIO_MAX_BLK_TRANS 20U
/**************************** Type Definitions *******************************/
typedef struct
{
FSdio *mmcsd_instance;
FSdioIDmaDesc *rw_desc;
rt_err_t (*transfer)(struct rt_mmcsd_host *host, struct rt_mmcsd_req *req, FSdioCmdData *cmd_data_p);
} mmcsd_info_t;
/************************** Variable Definitions *****************************/
/***************** Macros (Inline Functions) Definitions *********************/
/*******************************Api Functions*********************************/
static void fsdio_host_relax(void)
{
rt_thread_mdelay(1);
}
static rt_err_t fsdio_ctrl_init(struct rt_mmcsd_host *host)
{
mmcsd_info_t *private_data_t = (mmcsd_info_t *)host->private_data;
FSdio *mmcsd_instance = RT_NULL;
const FSdioConfig *default_mmcsd_config = RT_NULL;
FSdioConfig mmcsd_config;
FSdioIDmaDesc *rw_desc = RT_NULL;
mmcsd_instance = rt_malloc(sizeof(FSdio));
if (!mmcsd_instance)
{
LOG_E("Malloc mmcsd_instance failed");
return RT_ERROR;
}
rw_desc = rt_malloc_align(SDIO_MAX_BLK_TRANS * sizeof(FSdioIDmaDesc), SDIO_MALLOC_CAP_DESC);
if (!rw_desc)
{
LOG_E("Malloc rw_desc failed");
return RT_ERROR;
}
rt_memset(mmcsd_instance, 0, sizeof(FSdio));
rt_memset(rw_desc, 0, SDIO_MAX_BLK_TRANS * sizeof(FSdioIDmaDesc));
/* SDIO controller init */
RT_ASSERT((default_mmcsd_config = FSdioLookupConfig(SDIO_CONTROLLER_ID)) != RT_NULL);
mmcsd_config = *default_mmcsd_config; /* load default config */
#ifdef RT_USING_SMART
mmcsd_config.base_addr = (uintptr)rt_ioremap((void *)mmcsd_config.base_addr, 0x1000);
#endif
mmcsd_config.trans_mode = FSDIO_IDMA_TRANS_MODE;
#ifdef USING_EMMC
mmcsd_config.non_removable = TRUE; /* eMMC is unremovable on board */
#else
mmcsd_config.non_removable = FALSE; /* TF card is removable on board */
#endif
if (FSDIO_SUCCESS != FSdioCfgInitialize(mmcsd_instance, &mmcsd_config))
{
LOG_E("SDIO controller init failed.");
return RT_ERROR;
}
if (FSDIO_SUCCESS != FSdioSetIDMAList(mmcsd_instance, rw_desc, SDIO_MAX_BLK_TRANS))
{
LOG_E("SDIO controller setup DMA failed.");
return RT_ERROR;
}
mmcsd_instance->desc_list.first_desc_p = (uintptr)rw_desc + PV_OFFSET;
FSdioRegisterRelaxHandler(mmcsd_instance, fsdio_host_relax); /* SDIO delay for a while */
private_data_t->mmcsd_instance = mmcsd_instance;
private_data_t->rw_desc = rw_desc;
rt_kprintf("SDIO controller init success!\r\n");
return RT_EOK;
}
rt_inline rt_err_t sdio_dma_transfer(struct rt_mmcsd_host *host, struct rt_mmcsd_req *req, FSdioCmdData *req_cmd)
{
FError ret = FT_SUCCESS;
mmcsd_info_t *private_data_t = (mmcsd_info_t *)host->private_data;
FSdio *mmcsd_instance = private_data_t->mmcsd_instance;
ret = FSdioDMATransfer(mmcsd_instance, req_cmd);
if (ret != FT_SUCCESS)
{
LOG_E("FSdioDMATransfer() fail.");
return -RT_ERROR;
}
ret = FSdioPollWaitDMAEnd(mmcsd_instance, req_cmd);
if (ret != FT_SUCCESS)
{
LOG_E("FSdioPollWaitDMAEnd() fail.");
return -RT_ERROR;
}
if (resp_type(req->cmd) & RESP_MASK)
{
if (resp_type(req->cmd) == RESP_R2)
{
req->cmd->resp[3] = req_cmd->response[0];
req->cmd->resp[2] = req_cmd->response[1];
req->cmd->resp[1] = req_cmd->response[2];
req->cmd->resp[0] = req_cmd->response[3];
}
else
{
req->cmd->resp[0] = req_cmd->response[0];
}
}
return RT_EOK;
}
static void mmc_request_send(struct rt_mmcsd_host *host, struct rt_mmcsd_req *req)
{
/* ignore some SDIO-ONIY cmd */
if ((req->cmd->cmd_code == SD_IO_SEND_OP_COND) || (req->cmd->cmd_code == SD_IO_RW_DIRECT))
{
req->cmd->err = -1;
goto skip_cmd;
}
mmcsd_info_t *private_data_t = (mmcsd_info_t *)host->private_data;
FSdioCmdData req_cmd;
FSdioCmdData req_stop;
FSdioData req_data;
rt_uint32_t *data_buf_aligned = RT_NULL;
rt_uint32_t cmd_flag = resp_type(req->cmd);
rt_memset(&req_cmd, 0, sizeof(FSdioCmdData));
rt_memset(&req_stop, 0, sizeof(FSdioCmdData));
rt_memset(&req_data, 0, sizeof(FSdioData));
/* convert req into ft driver type */
if (req->cmd->cmd_code == GO_IDLE_STATE)
{
req_cmd.flag |= FSDIO_CMD_FLAG_NEED_INIT;
}
if (req->cmd->cmd_code == GO_INACTIVE_STATE)
{
req_cmd.flag |= FSDIO_CMD_FLAG_NEED_AUTO_STOP;
}
if ((cmd_flag != RESP_R3) && (cmd_flag != RESP_R4) && (cmd_flag != RESP_NONE))
{
req_cmd.flag |= FSDIO_CMD_FLAG_NEED_RESP_CRC;
}
if (cmd_flag & RESP_MASK)
{
req_cmd.flag |= FSDIO_CMD_FLAG_EXP_RESP;
if (cmd_flag == RESP_R2)
{
req_cmd.flag |= FSDIO_CMD_FLAG_EXP_LONG_RESP;
}
}
if (req->data) /* transfer command with data */
{
data_buf_aligned = rt_malloc_align(SDIO_DMA_BLK_SZ * req->data->blks, SDIO_DMA_ALIGN);
if (!data_buf_aligned)
{
LOG_E("Malloc data_buf_aligned failed");
return;
}
rt_memset(data_buf_aligned, 0, SDIO_DMA_BLK_SZ * req->data->blks);
req_cmd.flag |= FSDIO_CMD_FLAG_EXP_DATA;
req_data.blksz = req->data->blksize;
req_data.blkcnt = req->data->blks;
req_data.datalen = req->data->blksize * req->data->blks;
if ((uintptr)req->data->buf % SDIO_DMA_ALIGN) /* data buffer should be 512-aligned */
{
if (req->data->flags & DATA_DIR_WRITE)
{
rt_memcpy((void *)data_buf_aligned, (void *)req->data->buf, req_data.datalen);
}
req_data.buf = (rt_uint8_t *)data_buf_aligned;
req_data.buf_p = (uintptr)data_buf_aligned + PV_OFFSET;
}
else
{
req_data.buf = (rt_uint8_t *)req->data->buf;
req_data.buf_p = (uintptr)req->data->buf + PV_OFFSET;
}
req_cmd.data_p = &req_data;
if (req->data->flags & DATA_DIR_READ)
{
req_cmd.flag |= FSDIO_CMD_FLAG_READ_DATA;
}
else if (req->data->flags & DATA_DIR_WRITE)
{
req_cmd.flag |= FSDIO_CMD_FLAG_WRITE_DATA;
}
}
req_cmd.cmdidx = req->cmd->cmd_code;
req_cmd.cmdarg = req->cmd->arg;
/* do cmd and data transfer */
req->cmd->err = (private_data_t->transfer)(host, req, &req_cmd);
if (req->cmd->err != RT_EOK)
{
LOG_E("transfer failed in %s", __func__);
}
if (req->data && (req->data->flags & DATA_DIR_READ))
{
if ((uintptr)req->data->buf % SDIO_DMA_ALIGN) /* data buffer should be 512-aligned */
{
rt_memcpy((void *)req->data->buf, (void *)data_buf_aligned, req_data.datalen);
}
}
/* stop cmd */
if (req->stop)
{
req_stop.cmdidx = req->stop->cmd_code;
req_stop.cmdarg = req->stop->arg;
if (req->stop->flags & RESP_MASK)
{
req_stop.flag |= FSDIO_CMD_FLAG_READ_DATA;
if (resp_type(req->stop) == RESP_R2)
req_stop.flag |= FSDIO_CMD_FLAG_EXP_LONG_RESP;
}
req->stop->err = (private_data_t->transfer)(host, req, &req_stop);
}
if (data_buf_aligned)
rt_free_align(data_buf_aligned);
skip_cmd:
mmcsd_req_complete(host);
}
static void mmc_set_iocfg(struct rt_mmcsd_host *host, struct rt_mmcsd_io_cfg *io_cfg)
{
FError ret = FT_SUCCESS;
mmcsd_info_t *private_data_t = (mmcsd_info_t *)host->private_data;
FSdio *mmcsd_instance = private_data_t->mmcsd_instance;
uintptr base_addr = mmcsd_instance->config.base_addr;
if (0 != io_cfg->clock)
{
ret = FSdioSetClkFreq(mmcsd_instance, io_cfg->clock);
if (ret != FT_SUCCESS)
{
LOG_E("FSdioSetClkFreq fail.");
}
}
switch (io_cfg->bus_width)
{
case MMCSD_BUS_WIDTH_1:
FSdioSetBusWidth(base_addr, 1U);
break;
case MMCSD_BUS_WIDTH_4:
FSdioSetBusWidth(base_addr, 4U);
break;
case MMCSD_BUS_WIDTH_8:
FSdioSetBusWidth(base_addr, 8U);
break;
default:
LOG_E("Invalid bus width %d", io_cfg->bus_width);
break;
}
}
static const struct rt_mmcsd_host_ops ops =
{
mmc_request_send,
mmc_set_iocfg,
RT_NULL,
RT_NULL,
RT_NULL,
};
int ft_mmcsd_init(void)
{
/* variables init */
struct rt_mmcsd_host *host = RT_NULL;
mmcsd_info_t *private_data = RT_NULL;
host = mmcsd_alloc_host();
if (!host)
{
LOG_E("Alloc host failed");
goto err_free;
}
private_data = rt_malloc(sizeof(mmcsd_info_t));
if (!private_data)
{
LOG_E("Malloc private_data failed");
goto err_free;
}
rt_memset(private_data, 0, sizeof(mmcsd_info_t));
private_data->transfer = sdio_dma_transfer;
/* host data init */
host->ops = &ops;
host->freq_min = 400000;
host->freq_max = 50000000;
host->valid_ocr = SDIO_VALID_OCR; /* the voltage range supported is 1.65v-3.6v */
host->flags = MMCSD_MUTBLKWRITE | MMCSD_BUSWIDTH_4;
host->max_seg_size = SDIO_DMA_BLK_SZ; /* used in block_dev.c */
host->max_dma_segs = SDIO_MAX_BLK_TRANS; /* physical segment number */
host->max_blk_size = SDIO_DMA_BLK_SZ; /* all the 4 para limits size of one blk tran */
host->max_blk_count = SDIO_MAX_BLK_TRANS;
host->private_data = private_data;
if (RT_EOK != fsdio_ctrl_init(host))
{
LOG_E("fsdio_ctrl_init() failed");
goto err_free;
}
mmcsd_change(host);
return RT_EOK;
err_free:
if (host)
rt_free(host);
if (private_data->mmcsd_instance)
rt_free(private_data->mmcsd_instance);
if (private_data->rw_desc)
rt_free_align(private_data->rw_desc);
if (private_data)
rt_free(private_data);
return -RT_EOK;
}
INIT_DEVICE_EXPORT(ft_mmcsd_init);
#endif // #ifdef RT_USING_SDIO

28
bsp/phytium/libraries/drivers/drv_sdio.h Normal file
View File

@ -0,0 +1,28 @@
/*
* Copyright (c) 2006-2023, RT-Thread Development Team
*
* SPDX-License-Identifier: Apache-2.0
*
* Email: opensource_embedded@phytium.com.cn
*
* Change Logs:
* Date Author Notes
* 2023/7/11 liqiaozhong init SD card and mount file system
*
*/
#ifndef __DRV_SDIO_H__
#define __DRV_SDIO_H__
/***************************** Include Files *********************************/
#include <rtthread.h>
/************************** Constant Definitions *****************************/
/**************************** Type Definitions *******************************/
/************************** Variable Definitions *****************************/
/***************** Macros (Inline Functions) Definitions *********************/
/*******************************Api Functions*********************************/
#endif

3
bsp/phytium/libraries/drivers/drv_spi.c
View File

@ -116,6 +116,9 @@ static rt_err_t spim_configure(struct rt_spi_device *device,
RT_ASSERT(configuration != RT_NULL);
struct drv_spi *user_data_cfg = device->parent.user_data;
FSpimConfig input_cfg = *FSpimLookupConfig(user_data_cfg->spi_id);
#ifdef RT_USING_SMART
input_cfg.base_addr = (uintptr)rt_ioremap((void*)input_cfg.base_addr, 0x1000);
#endif
FSpimConfig *set_input_cfg = &input_cfg;
/* set fspim device according to configuration */

1663
bsp/phytium/libraries/drivers/drv_xmac.c
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File diff suppressed because it is too large Load Diff

154
bsp/phytium/libraries/drivers/drv_xmac.h
View File

@ -1,22 +1,142 @@
/*
* @Copyright : (C) 2022 Phytium Information Technology, Inc.
* All Rights Reserved.
* Copyright (c) 2006-2023, RT-Thread Development Team
*
* This program is OPEN SOURCE software: you can redistribute it and/or modify it
* under the terms of the Phytium Public License as published by the Phytium Technology Co.,Ltd,
* either version 1.0 of the License, or (at your option) any later version.
* SPDX-License-Identifier: Apache-2.0
*
* This program is distributed in the hope that it will be useful,but WITHOUT ANY WARRANTY;
* without even the implied warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.
* See the Phytium Public License for more details.
* Email: opensource_embedded@phytium.com.cn
*
*
* @FilePath: drv_xmac.h
* @Date: 2023-04-19 15:19:39
* @LastEditTime: 2023-04-19 15:19:40
* @Description: This file is for
*
* @Modify History:
* Ver Who Date Changes
* ----- ------ -------- --------------------------------------
* Change Logs:
* Date Author Notes
* 2022-07-07 liuzhihong first commit
* 2023-07-14 liuzhihong support RT-Smart
*/
#ifndef __DRV_XMAC_H__
#define __DRV_XMAC_H__
#include <rtthread.h>
#include <rtdevice.h>
#include <netif/ethernetif.h>
#include "fxmac.h"
#include "fkernel.h"
#include "ferror_code.h"
#include "fassert.h"
#include "fcache.h"
#include "fxmac_bdring.h"
#include "eth_ieee_reg.h"
#include "fcpu_info.h"
#include "fdebug.h"
#ifdef __cplusplus
extern "C" {
#endif
#define FREERTOS_XMAC_INIT_ERROR FT_CODE_ERR(ErrModPort, 0, 0x1)
#define FREERTOS_XMAC_PARAM_ERROR FT_CODE_ERR(ErrModPort, 0, 0x2)
#define FREERTOS_XMAC_NO_VALID_SPACE FT_CODE_ERR(ErrModPort, 0, 0x3)
#define FXMAX_RX_BDSPACE_LENGTH 0x20000 /* default set 128KB*/
#define FXMAX_TX_BDSPACE_LENGTH 0x20000 /* default set 128KB*/
#define FXMAX_RX_PBUFS_LENGTH 16
#define FXMAX_TX_PBUFS_LENGTH 16
#define FXMAX_MAX_HARDWARE_ADDRESS_LENGTH 6
/* configuration */
#define FXMAC_OS_CONFIG_JUMBO BIT(0)
#define FXMAC_OS_CONFIG_MULTICAST_ADDRESS_FILITER BIT(1) /* Allow multicast address filtering */
#define FXMAC_OS_CONFIG_COPY_ALL_FRAMES BIT(2) /* enable copy all frames */
#define FXMAC_OS_CONFIG_CLOSE_FCS_CHECK BIT(3) /* close fcs check */
#define FXMAC_OS_CONFIG_RX_POLL_RECV BIT(4) /* select poll mode */
/* Phy */
#define FXMAC_PHY_SPEED_10M 10
#define FXMAC_PHY_SPEED_100M 100
#define FXMAC_PHY_SPEED_1000M 1000
#define FXMAC_PHY_HALF_DUPLEX 0
#define FXMAC_PHY_FULL_DUPLEX 1
#define MAX_FRAME_SIZE_JUMBO (FXMAC_MTU_JUMBO + FXMAC_HDR_SIZE + FXMAC_TRL_SIZE)
/* Byte alignment of BDs */
#define BD_ALIGNMENT (FXMAC_DMABD_MINIMUM_ALIGNMENT*2)
/* frame queue */
#define PQ_QUEUE_SIZE 4096
#define LINK_THREAD_STACK_LENGTH 0x20400
typedef struct
{
uintptr data[PQ_QUEUE_SIZE];
int head, tail, len;
} PqQueue;
typedef enum
{
FXMAC_OS_INTERFACE_SGMII = 0,
FXMAC_OS_INTERFACE_RMII,
FXMAC_OS_INTERFACE_RGMII,
FXMAC_OS_INTERFACE_LENGTH
} FXmacRtThreadInterface;
typedef struct
{
u8 rx_bdspace[FXMAX_RX_BDSPACE_LENGTH] __attribute__((aligned(128))); /* 接收bd 缓冲区 */
u8 tx_bdspace[FXMAX_RX_BDSPACE_LENGTH] __attribute__((aligned(128))); /* 发送bd 缓冲区 */
uintptr rx_pbufs_storage[FXMAX_RX_PBUFS_LENGTH];
uintptr tx_pbufs_storage[FXMAX_TX_PBUFS_LENGTH];
} FXmacNetifBuffer;
typedef struct
{
u32 instance_id;
FXmacRtThreadInterface interface;
u32 autonegotiation; /* 1 is autonegotiation ,0 is manually set */
u32 phy_speed; /* FXMAC_PHY_SPEED_XXX */
u32 phy_duplex; /* FXMAC_PHY_XXX_DUPLEX */
} FXmacOsControl;
typedef struct
{
struct eth_device parent; /* inherit from ethernet device */
FXmac instance; /* Xmac controller */
FXmacOsControl mac_config;
FXmacNetifBuffer buffer; /* DMA buffer */
/* queue to store overflow packets */
PqQueue recv_q;
PqQueue send_q;
/* configuration */
u32 config;
rt_uint8_t hwaddr[FXMAX_MAX_HARDWARE_ADDRESS_LENGTH]; /* MAC address */
struct rt_thread _link_thread; /* link detect thread */
rt_uint8_t _link_thread_stack[LINK_THREAD_STACK_LENGTH];/* link detect thread stack*/
} FXmacOs;
enum lwip_port_link_status
{
ETH_LINK_UNDEFINED = 0,
ETH_LINK_UP,
ETH_LINK_DOWN,
ETH_LINK_NEGOTIATING
};
#ifdef __cplusplus
}
#endif
#endif // !

79
bsp/phytium/libraries/examples/spi_sfud_sample.c
View File

@ -1,79 +0,0 @@
/*
* Copyright (c) 2006-2023, RT-Thread Development Team
*
* SPDX-License-Identifier: Apache-2.0
*
* Email: opensource_embedded@phytium.com.cn
*
* Change Logs:
* Date Author Notes
* 2022-11-20 liqiaozhong first commit
* 2022-03-08 liqiaozhong add format function and mount table
*/
#include <rtthread.h>
#include <string.h>
#if defined (RT_USING_SFUD) && defined(RT_USING_DFS)
#include <dfs_fs.h>
#include <dfs_file.h>
#include <unistd.h>
#include <stdio.h>
#include <sys/stat.h>
#include <sys/statfs.h>
#include "spi_flash.h"
#include "spi_flash_sfud.h"
#include "fdebug.h"
#include "fparameters_comm.h"
#include "fspim.h"
/************************** Variable Definitions *****************************/
sfud_flash_t spim_flash = RT_NULL;
const struct dfs_mount_tbl mount_table[] =
{
{ "flash2", "/", "elm", 0, RT_NULL },
{0},
};
/***************** Macros (Inline Fungoctions) Definitions *********************/
#define FSPIM_DEBUG_TAG "SPIM"
#define FSPIM_ERROR(format, ...) FT_DEBUG_PRINT_E(FSPIM_DEBUG_TAG, format, ##__VA_ARGS__)
#define FSPIM_WARN(format, ...) FT_DEBUG_PRINT_W(FSPIM_DEBUG_TAG, format, ##__VA_ARGS__)
#define FSPIM_INFO(format, ...) FT_DEBUG_PRINT_I(FSPIM_DEBUG_TAG, format, ##__VA_ARGS__)
#define FSPIM_DEBUG(format, ...) FT_DEBUG_PRINT_D(FSPIM_DEBUG_TAG, format, ##__VA_ARGS__)
/*******************************Api Functions*********************************/
static int spi_flash_sfud_init(void)
{
if (RT_NULL == rt_sfud_flash_probe("flash2", "spi02"))
{
rt_kprintf("rt_sfud_flash_probe failed\n");
return RT_ERROR;
}
spim_flash = rt_sfud_flash_find_by_dev_name("flash2");
if (RT_NULL == spim_flash)
{
rt_kprintf("Flash init failed -> can't find flash2 device!\n");
return RT_ERROR;
}
rt_kprintf("Spi flash device flash2 init\n");
rt_kprintf("Flash device: flash2 info\nmf_id: 0x%x\ntype_id: 0x%x\ncapacity_id: 0x%x\nerase granularity: %lu\n",
spim_flash->chip.mf_id,
spim_flash->chip.type_id,
spim_flash->chip.capacity_id,
spim_flash->chip.erase_gran);
return RT_EOK;
}
INIT_DEVICE_EXPORT(spi_flash_sfud_init);
/* format the flash with elm environment */
static int flash_format_operation(void)
{
int result = RT_EOK;
result = dfs_mkfs("elm", "flash2");
return result;
}
INIT_ENV_EXPORT(flash_format_operation);
#endif /* RT_USING_SFUD || RT_USING_DFS */

112
bsp/phytium/libraries/standalone/README.md
View File

@ -1,6 +1,6 @@
# Phytium-Standalone-SDK
**v1.0.0** [ReleaseNote](./doc/ChangeLog.md)
**v1.1.1** [ReleaseNote](./doc/ChangeLog.md)
## 1. 项目概要
@ -16,20 +16,15 @@ release 分支：发布分支，包含核心启动代码、芯片外设驱动、
![LetterShell](./doc/fig/letter_shell.png)
### 1.3 系统架构
本项目的整体设计如下所示，自下而上可以分为平台层、组件层、框架层和应用层。
![Framework](./doc/design/system_2.png)
- 平台层（Platform）在整个软件框架中位于最底层，提供了基本数据结构类型定义、驱动参数标定、硬件平台耦合的寄存器自检、板级启动、CPU 内存虚拟等功能
- 组件层（Component）在整个软件框架中位于中间位置，向下依赖于平台层提供的参数配置与内存方案，向上提供应用开发与模块测试的支持
- 框架层（Framework）为开发主机提供了开发环境，支持SDK安装，应用工程配置和二进制文件构建及烧录等工具。
- 应用层（Application）提供了应用开发模板和例程，帮助开发者迅速熟悉SDK的使用，进行不同类型的应用程序开发
### 1.4 源代码结构
@ -39,15 +34,15 @@ release 分支：发布分支，包含核心启动代码、芯片外设驱动、
├── Kconfig --> 配置定义
├── LICENSE --> 版权声明
├── README.md --> 使用说明
├── arch
├── arch
│   └── armv8 --> 架构相关
├── baremetal
│   └── example --> 裸机例程
├── board
├── board
│   ├── d2000
│   ├── e2000
│   └── ft2004 --> 平台相关
├── common
├── common
│   ├── fprintf.c
│   ├── fprintf.h
│   ├── fsleep.c
@ -63,7 +58,7 @@ release 分支：发布分支，包含核心启动代码、芯片外设驱动、
│   ├── dma
│   └── watchdog --> 外设驱动
├── install.py --> 安装脚本
├── lib
├── lib
│   ├── Kconfiglib
│   ├── lib.mk
│   ├── libc
@ -77,7 +72,7 @@ release 分支：发布分支，包含核心启动代码、芯片外设驱动、
├── scripts
├── standalone.mk
├── third-party
│   └── letter-shell-3.1 --> 第三方库
│   └── letter-shell-3.1 --> 第三方库
├── tools
```
@ -89,12 +84,10 @@ release 分支：发布分支，包含核心启动代码、芯片外设驱动、
![windows](./doc/fig/windows.png)![linux](./doc/fig/linux.png)![输入图片说明](./doc/fig/kylin.png)
- 参考[Windows10 快速入门](./doc/reference/usr/install_windows.md), [Linux x86_64 快速入门](./doc/reference/usr/install_linux_x86_64.md)
- 参考[使用说明](./doc/reference/usr/usage.md), 新建Phytium Standalone SDK的应用工程，与开发板建立连接
- 参考[例程](./baremetal/example)，开始使用SDK
- 参考[系统测试](./example)，开始使用重构后的系统测试用例(v1.1.0版本开始，测试用例将逐步进行重构)
---
@ -134,7 +127,6 @@ D2000 是一款面向桌面应用的高性能通用 8 核处理器。每 2 个
### 3.3 E2000Q
- E2000Q 集成2个FTC664核和2个FTC310核。主要技术特征如下：
- 兼容ARM v8 64 位指令系统，兼容32 位指令
- 集成 1 路 16 通道 General DMA 和 1 路 8 通道 Device DMA
- 支持单精度、双精度浮点运算指令
@ -150,7 +142,6 @@ D2000 是一款面向桌面应用的高性能通用 8 核处理器。每 2 个
### 3.4 E2000D
- E2000D 集成 2 个 FTC310 核。主要技术特征如下：
- 兼容ARM v8 64 位指令系统，兼容32 位指令
- 集成 1 路 16 通道 General DMA 和 1 路 8 通道 Device DMA
- 支持单精度、双精度浮点运算指令
@ -166,7 +157,6 @@ D2000 是一款面向桌面应用的高性能通用 8 核处理器。每 2 个
### 3.5 E2000S
- E2000S 集成 1 个 FTC310 核，单核结构。主要技术特征如下：
- 兼容ARM v8 64 位指令系统，兼容32 位指令
- 集成 1 路 16 通道 General DMA 和 1 路 8 通道 Device DMA
- 支持单精度、双精度浮点运算指令
@ -178,50 +168,48 @@ D2000 是一款面向桌面应用的高性能通用 8 核处理器。每 2 个
- 2路 DisplayPort1.4 接口
- 集成常用低速接口：WDT、DMAC、PWM、QSPI、SD/SDIO/eMMC、SPI Master、UART、I2C、MIO、I3C、PMBUS、GPIO、SGPIO、One-Wire、Timer、One-Wire
## 4 外设驱动支持情况
| Hardware Interface | Platform Supported | Platform Developing | Component |
| ------------------------------ | -------------------------- | --------------------------- | ------------------------- |
| Generic Intrrupt Controller v3 | FT2000/4<br>E2000<br>D2000 | | gic/fgic |
| Generic Timer | FT2000/4<br>E2000<br>D2000 | | generic_timer |
| UART (PrimeCell PL011) | FT2000/4<br>E2000<br>D2000 | | usart/pl011_uart |
| 10/100/1000MB-ETHERNET | FT2000/4<br>E2000<br>D2000 | | eth/fgmac<br>eth/fxmac |
| ADC | E2000 | | adc/fadc |
| CAN | FT2000/4<br>E2000<br>D2000 | | can/fcan |
| DDMA | | E2000 | dma/fddma |
| GDMA | E2000 | | dma/gdma |
| GPIO | FT2000/4<br>E2000<br>D2000 | | gpio/fgpio |
| I2C | FT2000/4<br>E2000<br>D2000 | | i2c/fi2c |
| QSPI (Nor Flash) | FT2000/4<br>E2000<br>D2000 | | qspi/fqspi |
| SPI | FT2000/4<br>E2000<br>D2000 | | spi/fspim |
| TIMER & TACHO | E2000 | | timer/ftimer_tacho |
| MIO | E2000 | | mio/fmio |
| SDMMC | | FT2000/4<br>D2000 | mmc/fsdmmc |
| SDIO | E2000 | | mmc/fsdio |
| PCIE | FT2000/4<br>D2000<br>E2000 | | pcie/fpcie |
| NAND | E2000 | | nand/fnand |
| RTC | FT2000/4<br>D2000 | | rtc/frtc |
| SATA | FT2000/4<br>D2000<br>E2000 | | sata/fsata |
| USB-PCI | | FT2000/4<br>E2000<br>D2000 | usb/fxhci |
| PWM | E2000 | | pwm/fpwm |
| WDT | FT2000/4<br>D2000<br>E2000 | | watchdog/fwdt |
| Hardware Interface | Platform Supported | Platform Developing | Component |
| ------------------------------ | ---------------------------------- | ---------------------------------- | -------------------------- |
| Generic Intrrupt Controller v3 | FT2000/4`<br>`E2000`<br>`D2000 | | gic/fgic |
| Generic Timer | FT2000/4`<br>`E2000`<br>`D2000 | | generic_timer |
| UART (PrimeCell PL011) | FT2000/4`<br>`E2000`<br>`D2000 | | usart/pl011_uart |
| 10/100/1000MB-ETHERNET | FT2000/4`<br>`E2000`<br>`D2000 | | eth/fgmac`<br>`eth/fxmac |
| ADC | E2000 | | adc/fadc |
| CAN | FT2000/4`<br>`E2000`<br>`D2000 | | can/fcan |
| DDMA | | E2000 | dma/fddma |
| GDMA | E2000 | | dma/gdma |
| GPIO | FT2000/4`<br>`E2000`<br>`D2000 | | gpio/fgpio |
| I2C | FT2000/4`<br>`E2000`<br>`D2000 | | i2c/fi2c |
| QSPI (Nor Flash) | FT2000/4`<br>`E2000`<br>`D2000 | | qspi/fqspi |
| SPI | FT2000/4`<br>`E2000`<br>`D2000 | | spi/fspim |
| TIMER & TACHO | E2000 | | timer/ftimer_tacho |
| MIO | E2000 | | mio/fmio |
| SDMMC | | FT2000/4`<br>`D2000 | mmc/fsdmmc |
| SDIO | E2000 | | mmc/fsdio |
| PCIE | FT2000/4`<br>`D2000`<br>`E2000 | | pcie/fpcie |
| NAND | E2000 | | nand/fnand |
| RTC | FT2000/4`<br>`D2000 | | rtc/frtc |
| SATA | FT2000/4`<br>`D2000`<br>`E2000 | | sata/fsata |
| USB-PCI | | FT2000/4`<br>`E2000`<br>`D2000 | usb/fxhci |
| PWM | E2000 | | pwm/fpwm |
| WDT | FT2000/4`<br>`D2000`<br>`E2000 | | watchdog/fwdt |
| Third-Party | Platform Supported | Platform Developing | Component |
| ------------------------------ | -------------------------- | --------------------------- | ------------------------- |
| LWIP 2.1.2 | FT2000/4<br>D2000<br>E2000 | | lwip-2.1.2 |
| Letter shell 3.1 | FT2000/4<br>D2000<br>E2000 | | letter-shell-3.1 |
| Sdmmc | FT2000/4<br>D2000 | | sdmmc |
| Sfud 1.1.0 | FT2000/4<br>D2000<br>E2000 | | sfud-1.1.0 |
| Backtrace | FT2000/4<br>D2000<br>E2000 | | backtrace |
| Tlsf | FT2000/4<br>D2000<br>E2000 | | tlsf-3.1.0 |
| Fatfs (RAM/Sd/SATA) | FT2000/4<br>D2000<br>E2000 | | fatfs-0.1.3 |
| Ymodem | FT2000/4<br>D2000<br>E2000 | | |
| OpenAMP | FT2000/4<br>D2000<br>E2000 | | openamp |
| LittleFS-2.4.2 | | FT2000/4<br>E2000<br>D2000 | littlefs-2.4.2 |
| SPIFFS-0.3.7 | FT2000/4<br>D2000<br>E2000 | | spiffs-0.3.7 |
| freemodbus-v1.6 | E2000 | | protocols/fmodbus_test |
| Third-Party | Platform Supported | Platform Developing | Component |
| ------------------- | ---------------------------------- | ---------------------------------- | ---------------------- |
| LWIP 2.1.2 | FT2000/4`<br>`D2000`<br>`E2000 | | lwip-2.1.2 |
| Letter shell 3.1 | FT2000/4`<br>`D2000`<br>`E2000 | | letter-shell-3.1 |
| Sdmmc | FT2000/4`<br>`D2000 | | sdmmc |
| Sfud 1.1.0 | FT2000/4`<br>`D2000`<br>`E2000 | | sfud-1.1.0 |
| Backtrace | FT2000/4`<br>`D2000`<br>`E2000 | | backtrace |
| Tlsf | FT2000/4`<br>`D2000`<br>`E2000 | | tlsf-3.1.0 |
| Fatfs (RAM/Sd/SATA) | FT2000/4`<br>`D2000`<br>`E2000 | | fatfs-0.1.3 |
| Ymodem | FT2000/4`<br>`D2000`<br>`E2000 | | |
| OpenAMP | FT2000/4`<br>`D2000`<br>`E2000 | | openamp |
| LittleFS-2.4.2 | | FT2000/4`<br>`E2000`<br>`D2000 | littlefs-2.4.2 |
| SPIFFS-0.3.7 | FT2000/4`<br>`D2000`<br>`E2000 | | spiffs-0.3.7 |
| freemodbus-v1.6 | E2000 | | protocols/fmodbus_test |
---
@ -266,15 +254,18 @@ D2000 是一款面向桌面应用的高性能通用 8 核处理器。每 2 个
#### 5.1.18 [FMEDIA](doc/reference/driver/fmedia.md)
### 5.2 MEMORY
#### 5.2.1 [FMEMORY_POOL](./doc/reference/sdk/fmemory_pool.md)
### 5.3 CPU
#### 5.3.1 [MMU](./doc/reference/processor/mmu.md)
#### 5.3.1 [MMU](./doc/reference/cpu/mmu.md)
#### 5.3.2 [FPINCTRL](./doc/reference/sdk/fpinctrl.md)
#### 5.3.2 [INTERRUPT](./doc/reference/processor/interrupt.md)
#### 5.3.2 [FINTERRUPT](./doc/reference/cpu/finterrupt.md)
#### 5.3.3 [FPSCI](./doc/reference/cpu/psci.md)
---
@ -302,7 +293,6 @@ zhangyan1491@phytium.com.cn
## 6. 相关资源
- ARM Architecture Reference Manual
- ARM Cortex-A Series Programmer’s Guide
- Programmer Guide for ARMv8-A

10
bsp/phytium/libraries/standalone/board/Kconfig
View File

@ -8,21 +8,31 @@ menu "Board Configuration"
config TARGET_F2000_4
bool "FT2000-4"
select USE_SERIAL
select ENABLE_Pl011_UART
config TARGET_D2000
bool "D2000"
select USE_SERIAL
select ENABLE_Pl011_UART
config TARGET_E2000Q
bool "E2000Q"
select TARGET_E2000
select USE_SERIAL
select ENABLE_Pl011_UART
config TARGET_E2000D
bool "E2000D"
select TARGET_E2000
select USE_SERIAL
select ENABLE_Pl011_UART
config TARGET_E2000S
bool "E2000S"
select TARGET_E2000
select USE_SERIAL
select ENABLE_Pl011_UART
# config TARGET_TARDIGRADE
# bool "TARDIGRADE"

68
bsp/phytium/libraries/standalone/board/common/fsmp.c Normal file
View File

@ -0,0 +1,68 @@
/*
* Copyright : (C) 2022 Phytium Information Technology, Inc.
* All Rights Reserved.
*
* This program is OPEN SOURCE software: you can redistribute it and/or modify it
* under the terms of the Phytium Public License as published by the Phytium Technology Co.,Ltd,
* either version 1.0 of the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,but WITHOUT ANY WARRANTY;
* without even the implied warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.
* See the Phytium Public License for more details.
*
*
* FilePath: fsmp.c
* Date: 2022-02-10 14:53:42
* LastEditTime: 2022-02-17 17:58:14
* Description:  This files is for a way to provide spinlocks for multicore operations
*
* Modify History:
* Ver   Who        Date         Changes
* ----- ------     --------    --------------------------------------
* v1.1 carl 2022-12-30 add init function
* v1.2 cark 2023-02-28 Use GCC built-in functions to implement spinlock
*/
#if 0
#include "fsmp.h"
#include "sdkconfig.h"
#include "ftypes.h"
#include "fatomic.h"
typedef struct
{
int v;
}FCpuLock;
#ifdef CONFIG_SPIN_MEM
FCpuLock *_lock = (FCpuLock *)CONFIG_SPIN_MEM;
#else
FCpuLock _static_lock ;
FCpuLock *_lock = &_static_lock ;
#endif
void SpinUnlock(void)
{
FATOMIC_UNLOCK(_lock->v);
}
void SpinLock(void)
{
while(FATOMIC_LOCK(_lock->v,1))
{
}
}
void SpinInit(void)
{
FATOMIC_UNLOCK(_lock->v);
}
#endif

28
bsp/phytium/libraries/standalone/port/arch/armv8/aarch32/fpsci.h → bsp/phytium/libraries/standalone/board/common/fsmp.h
View File

@ -11,34 +11,36 @@
* See the Phytium Public License for more details.
*
*
* FilePath: fpsci.h
* Date: 2022-02-10 14:53:41
* LastEditTime: 2022-02-17 17:30:40
* Description:  This file is for cpu energy management
* FilePath: fsmp.h
* Date: 2022-02-10 14:53:42
* LastEditTime: 2022-02-17 17:58:18
* Description:  This file is for spinlock function
*
* Modify History:
* Ver   Who        Date         Changes
* ----- ------     --------    --------------------------------------
* 1.0 huanghe 2021/7/3 first release
* 1.0 carl 2023-02-28 Use GCC built-in functions to implement spinlock
*/
#ifndef ARCH_ARMV8_AARCH32_PSCI_H
#define ARCH_ARMV8_AARCH32_PSCI_H
#ifndef BSP_BOARD_COMMON_SMP_H
#define BSP_BOARD_COMMON_SMP_H
#include "ftypes.h"
#ifdef __cplusplus
extern "C"
{
#endif
#include "ftypes.h"
#include "ferror_code.h"
FError PsciCpuOn(s32 cpu_id_mask, uintptr bootaddr);
void PsciCpuReset(void);
void SpinInit(void);
void SpinLock(void);
void SpinUnlock(void);
#ifdef __cplusplus
}
#endif
#endif // !
#endif // DEBUG

406
bsp/phytium/libraries/standalone/board/d2000/fioctrl.c
View File

@ -1,406 +0,0 @@
/*
* Copyright : (C) 2022 Phytium Information Technology, Inc.
* All Rights Reserved.
*
* This program is OPEN SOURCE software: you can redistribute it and/or modify it
* under the terms of the Phytium Public License as published by the Phytium Technology Co.,Ltd,
* either version 1.0 of the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,but WITHOUT ANY WARRANTY;
* without even the implied warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.
* See the Phytium Public License for more details.
*
*
* FilePath: fioctrl.c
* Date: 2022-02-10 14:53:42
* LastEditTime: 2022-02-18 08:25:29
* Description:  This files is for io-ctrl function implementation (io-mux/io-config/io-delay)
*
* Modify History:
* Ver   Who        Date         Changes
* ----- ------     --------    --------------------------------------
* 1.0 zhugengyu 2022/2/22 init commit
*/
/***************************** Include Files *********************************/
#include "fparameters.h"
#include "fio.h"
#include "fkernel.h"
#include "fassert.h"
#include "fdebug.h"
#include "fioctrl.h"
#include "fpinctrl.h"
/************************** Constant Definitions *****************************/
/* Bit[0] : 输入延迟功能使能 */
#define FIOCTRL_DELAY_EN(delay_beg) BIT(delay_beg)
#define FIOCTRL_INPUT_DELAY_OFF 0
/* Bit[3:1] : 输入延迟精调档位选择 */
#define FIOCTRL_DELICATE_DELAY_MASK(delay_beg) GENMASK((delay_beg + 3), (delay_beg + 1))
#define FIOCTRL_DELICATE_DELAY_GET(reg_val, delay_beg) GET_REG32_BITS((reg_val), (delay_beg + 3), (delay_beg + 1))
#define FIOCTRL_DELICATE_DELAY_SET(val, delay_beg) SET_REG32_BITS((val), (delay_beg + 3), (delay_beg + 1))
/* Bit[6:4] : 输入延迟粗调档位选择 */
#define FIOCTRL_ROUGH_DELAY_MASK(delay_beg) GENMASK((delay_beg + 6), (delay_beg + 4))
#define FIOCTRL_ROUGH_DELAY_GET(reg_val, delay_beg) GET_REG32_BITS((reg_val), (delay_beg + 6), (delay_beg + 4))
#define FIOCTRL_ROUGH_DELAY_SET(val, delay_beg) SET_REG32_BITS((val), (delay_beg + 6), (delay_beg + 4))
/* Bit[7] : 保留 */
/* Bit[8] : 输出延迟功能使能 */
/* Bit[11:9] : 输出延迟精调档位选择 */
/* Bit [14:12] : 输出延迟粗调档位选择 */
/* Bit [15] : 保留 */
#define FIOCTRL_FUNC_BEG_OFF(reg_bit) ((reg_bit) + 0)
#define FIOCTRL_FUNC_END_OFF(reg_bit) ((reg_bit) + 1) /* bit[1:0] 复用功能占2个位 */
#define FIOCTRL_PULL_BEG_OFF(reg_bit) ((reg_bit) + 2)
#define FIOCTRL_PULL_END_OFF(reg_bit) ((reg_bit) + 3) /* bit[3:2] 上下拉功能占2个位 */
#define FIOCTRL_DELAY_IN_BEG_OFF(reg_bit) ((reg_bit) + 0)
#define FIOCTRL_DELAY_IN_END_OFF(reg_bit) ((reg_bit) + 7) /* bit[8:1] 输入延时占7个位 */
#define FIOCTRL_DELAY_OUT_BEG_OFF(reg_bit) ((reg_bit) + 8)
#define FIOCTRL_DELAY_OUT_END_OFF(reg_bit) ((reg_bit) + 15) /* bit[15:9] 输出延时占7个位 */
/* 芯片引脚控制寄存器的起止位置 */
#define FIOCTRL_REG_OFFSET_MIN 0x200
#define FIOCTRL_REG_OFFSET_MAX 0x22c
/* 芯片引脚延时寄存器的起止位置 */
#define FIOCTRL_DELAY_REG_OFFSET_MIN 0x400
#define FIOCTRL_DELAY_REG_OFFSET_MAX 0x404
/**************************** Type Definitions *******************************/
/***************** Macros (Inline Functions) Definitions *********************/
#define FIOCTRL_DEBUG_TAG "FIOCTRL"
#define FIOCTRL_ERROR(format, ...) FT_DEBUG_PRINT_E(FIOCTRL_DEBUG_TAG, format, ##__VA_ARGS__)
#define FIOCTRL_WARN(format, ...) FT_DEBUG_PRINT_W(FIOCTRL_DEBUG_TAG, format, ##__VA_ARGS__)
#define FIOCTRL_INFO(format, ...) FT_DEBUG_PRINT_I(FIOCTRL_DEBUG_TAG, format, ##__VA_ARGS__)
#define FIOCTRL_DEBUG(format, ...) FT_DEBUG_PRINT_D(FIOCTRL_DEBUG_TAG, format, ##__VA_ARGS__)
#define FIOCTRL_ASSERT_REG_OFF(pin) FASSERT_MSG(((pin.reg_off >= FIOCTRL_REG_OFFSET_MIN) && (pin.reg_off <= FIOCTRL_REG_OFFSET_MAX)), "invalid pin register off @%d", (pin.reg_off))
#define FIOCTRL_ASSERT_FUNC(func) FASSERT_MSG((func < FPIN_NUM_OF_FUNC), "invalid func as %d", (func))
#define FIOCTRL_ASSERT_PULL(pull) FASSERT_MSG((pull < FPIN_NUM_OF_PULL), "invalid pull as %d", (pull))
#define FIOCTRL_ASSERT_DELAY_REG_OFF(pin) FASSERT_MSG(((pin.reg_off >= FIOCTRL_DELAY_REG_OFFSET_MIN) && (pin.reg_off <= FIOCTRL_DELAY_REG_OFFSET_MAX)), "invalid delay pin register off @%d", (pin.reg_off))
#define FIOCTRL_ASSERT_DELAY(delay) FASSERT_MSG(((delay) < FPIN_NUM_OF_DELAY), "invalid delay as %d", (delay));
/************************** Function Prototypes ******************************/
/************************** Variable Definitions *****************************/
/*****************************************************************************/
/**
* @name: FPinGetFunc
* @msg: 获取IO引脚当前的复用功能
* @return {FPinFunc} 当前的复用功能
* @param {FPinIndex} pin IO引脚索引
* @note 参考编程手册，使用 FIOCTRL_INDEX 宏定义index的值
*/
FPinFunc FPinGetFunc(const FPinIndex pin)
{
FIOCTRL_ASSERT_REG_OFF(pin);
u32 func_beg = FIOCTRL_FUNC_BEG_OFF(pin.reg_bit);
u32 func_end = FIOCTRL_FUNC_END_OFF(pin.reg_bit);
u32 reg_val = FtIn32(FIOCTRL_REG_BASE_ADDR + pin.reg_off);
u32 func = GET_REG32_BITS(reg_val, func_end, func_beg);
FIOCTRL_ASSERT_FUNC(func);
return (FPinFunc)GET_REG32_BITS(reg_val, func_end, func_beg);
}
/**
* @name: FPinSetFunc
* @msg: 设置IO引脚复用功能
* @return {*}
* @param {FPinIndex} pin IO引脚索引
* @param {FPinFunc} func IO复用功能
* @note 参考编程手册，使用 FIOCTRL_INDEX 宏定义index的值
*/
void FPinSetFunc(const FPinIndex pin, FPinFunc func)
{
FIOCTRL_ASSERT_REG_OFF(pin);
FIOCTRL_ASSERT_FUNC(func);
u32 func_beg = FIOCTRL_FUNC_BEG_OFF(pin.reg_bit);
u32 func_end = FIOCTRL_FUNC_END_OFF(pin.reg_bit);
u32 reg_val = FtIn32(FIOCTRL_REG_BASE_ADDR + pin.reg_off);
reg_val &= ~GENMASK(func_end, func_beg);
reg_val |= SET_REG32_BITS(func, func_end, func_beg);
FtOut32(FIOCTRL_REG_BASE_ADDR + pin.reg_off, reg_val);
return;
}
/**
* @name: FPinGetPull
* @msg: 获取IO引脚当前的上下拉设置
* @return {*}
* @param {FPinIndex} pin IO引脚索引
* @note 参考编程手册，使用 FIOCTRL_INDEX 宏定义index的值
*/
FPinPull FPinGetPull(const FPinIndex pin)
{
FIOCTRL_ASSERT_REG_OFF(pin);
u32 pull_beg = FIOCTRL_PULL_BEG_OFF(pin.reg_bit);
u32 pull_end = FIOCTRL_PULL_END_OFF(pin.reg_bit);
u32 reg_val = FtIn32(FIOCTRL_REG_BASE_ADDR + pin.reg_off);
u32 pull = GET_REG32_BITS(reg_val, pull_end, pull_beg);
FIOCTRL_ASSERT_PULL(pull);
return (FPinPull)pull;
}
/**
* @name: FPinSetPull
* @msg: 设置IO引脚当前的上下拉
* @return {*}
* @param {FPinIndex} pin IO引脚索引
* @param {FPinPull} pull 上下拉设置
*/
void FPinSetPull(const FPinIndex pin, FPinPull pull)
{
FIOCTRL_ASSERT_REG_OFF(pin);
FIOCTRL_ASSERT_PULL(pull);
u32 pull_beg = FIOCTRL_PULL_BEG_OFF(pin.reg_bit);
u32 pull_end = FIOCTRL_PULL_END_OFF(pin.reg_bit);
u32 reg_val = FtIn32(FIOCTRL_REG_BASE_ADDR + pin.reg_off);
reg_val &= ~GENMASK(pull_end, pull_beg);
reg_val |= SET_REG32_BITS(pull, pull_end, pull_beg);
FtOut32(FIOCTRL_REG_BASE_ADDR + pin.reg_off, reg_val);
return;
}
/**
* @name: FPinGetConfig
* @msg: 获取IO引脚的复用、上下拉和驱动能力设置
* @return {*}
* @param {FPinIndex} pin IO引脚索引
* @param {FPinFunc} *func IO复用功能
* @param {FPinPull} *pull pull 上下拉设置
*/
void FPinGetConfig(const FPinIndex pin, FPinFunc *func, FPinPull *pull)
{
FIOCTRL_ASSERT_REG_OFF(pin);
u32 func_beg = FIOCTRL_FUNC_BEG_OFF(pin.reg_bit);
u32 func_end = FIOCTRL_FUNC_END_OFF(pin.reg_bit);
u32 pull_beg = FIOCTRL_PULL_BEG_OFF(pin.reg_bit);
u32 pull_end = FIOCTRL_PULL_END_OFF(pin.reg_bit);
u32 reg_val = FtIn32(FIOCTRL_REG_BASE_ADDR + pin.reg_off);
if (func)
{
*func = GET_REG32_BITS(reg_val, func_end, func_beg);
}
if (pull)
{
*pull = GET_REG32_BITS(reg_val, pull_end, pull_beg);
}
return;
}
/**
* @name: FPinSetConfig
* @msg: 设置IO引脚的复用、上下拉和驱动能力
* @return {*}
* @param {FPinIndex} pin IO引脚索引
* @param {FPinFunc} func IO复用功能
* @param {FPinPull} pull pull 上下拉设置
*/
void FPinSetConfig(const FPinIndex pin, FPinFunc func, FPinPull pull)
{
FIOCTRL_ASSERT_REG_OFF(pin);
u32 func_beg = FIOCTRL_FUNC_BEG_OFF(pin.reg_bit);
u32 func_end = FIOCTRL_FUNC_END_OFF(pin.reg_bit);
u32 pull_beg = FIOCTRL_PULL_BEG_OFF(pin.reg_bit);
u32 pull_end = FIOCTRL_PULL_END_OFF(pin.reg_bit);
u32 reg_val = FtIn32(FIOCTRL_REG_BASE_ADDR + pin.reg_off);
reg_val &= ~GENMASK(func_end, func_beg);
reg_val |= SET_REG32_BITS(func, func_end, func_beg);
reg_val &= ~GENMASK(pull_end, pull_beg);
reg_val |= SET_REG32_BITS(pull, pull_end, pull_beg);
FtOut32(FIOCTRL_REG_BASE_ADDR + pin.reg_off, reg_val);
return;
}
/**
* @name: FPinGetDelay
* @msg: 获取IO引脚当前的延时设置
* @return {FPinDelay} 当前的延时设置
* @param {FPinIndex} pin IO引脚延时设置索引
* @param {FPinDelayDir} dir 输入/输出延时
* @param {FPinDelayType} type 精调/粗调延时
*/
FPinDelay FPinGetDelay(const FPinIndex pin, FPinDelayDir dir, FPinDelayType type)
{
FIOCTRL_ASSERT_DELAY_REG_OFF(pin);
u8 delay = 0;
const u32 reg_val = FtIn32(FIOCTRL_REG_BASE_ADDR + pin.reg_off);
u32 delay_beg = 0, delay_end = 0;
if (FPIN_OUTPUT_DELAY == dir)
{
delay_beg = FIOCTRL_DELAY_OUT_BEG_OFF(pin.reg_off);
}
else if (FPIN_INPUT_DELAY == dir)
{
delay_beg = FIOCTRL_DELAY_IN_BEG_OFF(pin.reg_off);
}
else
{
FASSERT(0);
}
if (FPIN_DELAY_FINE_TUNING == type)
{
delay = FIOCTRL_DELICATE_DELAY_GET(reg_val, delay_beg);
}
else if (FPIN_DELAY_COARSE_TUNING == type)
{
delay = FIOCTRL_ROUGH_DELAY_GET(reg_val, delay_beg);
}
else
{
FASSERT(0);
}
FIOCTRL_ASSERT_DELAY(delay);
return (FPinDelay)delay;
}
/**
* @name: FPinGetDelayEn
* @msg: 获取IO引脚当前的延时使能标志位
* @return {*}
* @param {FPinIndex} pin IO引脚延时设置索引
* @param {FPinDelayDir} dir 输入/输出延时
*/
boolean FPinGetDelayEn(const FPinIndex pin, FPinDelayDir dir)
{
FIOCTRL_ASSERT_DELAY_REG_OFF(pin);
boolean enabled = FALSE;
const u32 reg_val = FtIn32(FIOCTRL_REG_BASE_ADDR + pin.reg_off);
u32 delay_beg = 0, delay_end = 0;
if (FPIN_OUTPUT_DELAY == dir)
{
delay_beg = FIOCTRL_DELAY_OUT_BEG_OFF(pin.reg_off);
}
else if (FPIN_INPUT_DELAY == dir)
{
delay_beg = FIOCTRL_DELAY_IN_BEG_OFF(pin.reg_off);
}
else
{
FASSERT(0);
}
if (FIOCTRL_DELAY_EN(delay_beg) & reg_val)
{
enabled = TRUE;
}
return enabled;
}
/**
* @name: FPinSetDelay
* @msg: 设置IO引脚延时
* @return {*}
* @param {FPinIndex} pin IO引脚延时设置索引
* @param {FPinDelayDir} dir 输入/输出延时
* @param {FPinDelayType} type 精调/粗调延时
* @param {FPinDelay} delay 延时档位设置 0 ~ 8 档可用
*/
void FPinSetDelay(const FPinIndex pin, FPinDelayDir dir, FPinDelayType type, FPinDelay delay)
{
FIOCTRL_ASSERT_DELAY_REG_OFF(pin);
FIOCTRL_ASSERT_DELAY(delay);
u32 reg_val = FtIn32(FIOCTRL_REG_BASE_ADDR + pin.reg_off);
u32 delay_beg = 0, delay_end = 0;
if (FPIN_OUTPUT_DELAY == dir)
{
delay_beg = FIOCTRL_DELAY_OUT_BEG_OFF(pin.reg_off);
}
else if (FPIN_INPUT_DELAY == dir)
{
delay_beg = FIOCTRL_DELAY_IN_BEG_OFF(pin.reg_off);
}
else
{
FASSERT(0);
}
if (FPIN_DELAY_FINE_TUNING == type)
{
reg_val &= ~FIOCTRL_DELICATE_DELAY_MASK(delay_beg);
delay = FIOCTRL_DELICATE_DELAY_GET(reg_val, delay_beg);
}
else if (FPIN_DELAY_COARSE_TUNING == type)
{
reg_val &= ~FIOCTRL_ROUGH_DELAY_MASK(delay_beg);
delay = FIOCTRL_ROUGH_DELAY_GET(reg_val, delay_beg);
}
else
{
FASSERT(0);
}
FtOut32(FIOCTRL_REG_BASE_ADDR + pin.reg_off, reg_val);
return;
}
/**
* @name: FPinSetDelayEn
* @msg: 使能/去使能IO引脚延时
* @return {*}
* @param {FPinIndex} pin IO引脚延时设置索引
* @param {FPinDelayDir} dir 输入/输出延时
* @param {boolean} enable TRUE: 使能, FALSE: 去使能
*/
void FPinSetDelayEn(const FPinIndex pin, FPinDelayDir dir, boolean enable)
{
FIOCTRL_ASSERT_DELAY_REG_OFF(pin);
u32 reg_val = FtIn32(FIOCTRL_REG_BASE_ADDR + pin.reg_off);
u32 delay_beg = 0, delay_end = 0;
if (FPIN_OUTPUT_DELAY == dir)
{
delay_beg = FIOCTRL_DELAY_OUT_BEG_OFF(pin.reg_off);
}
else if (FPIN_INPUT_DELAY == dir)
{
delay_beg = FIOCTRL_DELAY_IN_BEG_OFF(pin.reg_off);
}
else
{
FASSERT(0);
}
reg_val &= ~FIOCTRL_DELAY_EN(delay_beg);
if (enable)
{
reg_val |= FIOCTRL_DELAY_EN(delay_beg);
}
FtOut32(FIOCTRL_REG_BASE_ADDR + pin.reg_off, reg_val);
return;
}

83
bsp/phytium/libraries/standalone/board/d2000/fioctrl.h
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@ -1,83 +0,0 @@
/*
* Copyright : (C) 2022 Phytium Information Technology, Inc.
* All Rights Reserved.
*
* This program is OPEN SOURCE software: you can redistribute it and/or modify it
* under the terms of the Phytium Public License as published by the Phytium Technology Co.,Ltd,
* either version 1.0 of the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,but WITHOUT ANY WARRANTY;
* without even the implied warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.
* See the Phytium Public License for more details.
*
*
* FilePath: fioctrl.h
* Date: 2022-02-10 14:53:42
* LastEditTime: 2022-02-18 08:25:35
* Description:  This files is for io-ctrl function definition (io-mux/io-config/io-delay)
*
* Modify History:
* Ver   Who        Date         Changes
* ----- ------     --------    --------------------------------------
* 1.0 zhugengyu 2022/2/22 init commit
*/
#ifndef BOARD_D2000_FIOCTRL_H
#define BOARD_D2000_FIOCTRL_H
#ifdef __cplusplus
extern "C"
{
#endif
/***************************** Include Files *********************************/
#include "ftypes.h"
/************************** Constant Definitions *****************************/
/**************************** Type Definitions *******************************/
/***************** Macros (Inline Functions) Definitions *********************/
#define FIOCTRL_INDEX(offset, func_beg) \
{ \
/* reg_off */ (offset), \
/* reg_bit */ (func_beg) \
}
/************************** Variable Definitions *****************************/
#define FIOCTRL_CRU_CLK_OBV_PAD (FPinIndex)FIOCTRL_INDEX(0x200, 24)
#define FIOCTRL_SPI0_CSN0_PAD (FPinIndex)FIOCTRL_INDEX(0x208, 16)
#define FIOCTRL_SPI0_SCK_PAD (FPinIndex)FIOCTRL_INDEX(0x208, 12)
#define FIOCTRL_SPI0_SO_PAD (FPinIndex)FIOCTRL_INDEX(0x208, 8)
#define FIOCTRL_SPI0_SI_PAD (FPinIndex)FIOCTRL_INDEX(0x208, 4)
#define FIOCTRL_TJTAG_TDI_PAD (FPinIndex)FIOCTRL_INDEX(0x204, 24) /* can0-tx: func 1 */
#define FIOCTRL_SWDITMS_SWJ_PAD (FPinIndex)FIOCTRL_INDEX(0x204, 12) /* can0-rx: func 1 */
#define FIOCTRL_NTRST_SWJ_PAD (FPinIndex)FIOCTRL_INDEX(0x204, 20) /* can1-tx: func 1 */
#define FIOCTRL_SWDO_SWJ_PAD (FPinIndex)FIOCTRL_INDEX(0x204, 8) /* can1-rx: func 1 */
#define FIOCTRL_I2C0_SCL_PAD (FPinIndex)FIOCTRL_INDEX(0x208, 24) /* i2c0-scl: func 0 */
#define FIOCTRL_I2C0_SDA_PAD (FPinIndex)FIOCTRL_INDEX(0x208, 20) /* i2c0-sda: func 0 */
#define FIOCTRL_ALL_PLL_LOCK_PAD (FPinIndex)FIOCTRL_INDEX(0x200, 28) /* i2c1-scl: func 2 */
#define FIOCTRL_CRU_CLK_OBV_PAD (FPinIndex)FIOCTRL_INDEX(0x200, 24) /* i2c1-sda: func 2 */
#define FIOCTRL_SWDO_SWJ_PAD (FPinIndex)FIOCTRL_INDEX(0x204, 8) /* i2c2-scl: func 2 */
#define FIOCTRL_TDO_SWJ_IN_PAD (FPinIndex)FIOCTRL_INDEX(0x204, 4) /* i2c2-sda: func 2 */
#define FIOCTRL_HDT_MB_DONE_STATE_PAD (FPinIndex)FIOCTRL_INDEX(0x204, 0) /* i2c3-scl: func 2 */
#define FIOCTRL_HDT_MB_FAIL_STATE_PAD (FPinIndex)FIOCTRL_INDEX(0x208, 28) /* i2c3-sda: func 2 */
#define FIOCTRL_UART_2_RXD_PAD (FPinIndex)FIOCTRL_INDEX(0x210, 0) /* spi1_csn0: func 1 */
#define FIOCTRL_UART_2_TXD_PAD (FPinIndex)FIOCTRL_INDEX(0x214, 28) /* spi1_sck: func 1 */
#define FIOCTRL_UART_3_RXD_PAD (FPinIndex)FIOCTRL_INDEX(0x214, 24) /* spi1_so: func 1 */
#define FIOCTRL_UART_3_TXD_PAD (FPinIndex)FIOCTRL_INDEX(0x214, 20) /* spi1_si: func 1 */
#define FIOCTRL_QSPI_CSN2_PAD (FPinIndex)FIOCTRL_INDEX(0x214, 8) /* spi1_csn1: func 1 */
#define FIOCTRL_QSPI_CSN3_PAD (FPinIndex)FIOCTRL_INDEX(0x214, 4) /* spi1_csn2: func 1 */
#ifdef __cplusplus
}
#endif
#endif

347
bsp/phytium/libraries/standalone/board/d2000/fparameters.h
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@ -1,347 +0,0 @@
/*
* Copyright : (C) 2022 Phytium Information Technology, Inc.
* All Rights Reserved.
*
* This program is OPEN SOURCE software: you can redistribute it and/or modify it
* under the terms of the Phytium Public License as published by the Phytium Technology Co.,Ltd,
* either version 1.0 of the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,but WITHOUT ANY WARRANTY;
* without even the implied warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.
* See the Phytium Public License for more details.
*
*
* FilePath: fparameters.h
* Date: 2022-02-10 14:53:42
* LastEditTime: 2022-02-17 17:58:51
* Description:  This file is for
*
* Modify History:
* Ver   Who        Date         Changes
* ----- ------     --------    --------------------------------------
*/
#ifndef BSP_BOARD_D2000_PARAMETERS_H
#define BSP_BOARD_D2000_PARAMETERS_H
#ifdef __cplusplus
extern "C"
{
#endif
#if !defined(__ASSEMBLER__)
#include "ftypes.h"
#endif
#define CORE0_AFF 0x0
#define CORE1_AFF 0x1
#define CORE2_AFF 0x100
#define CORE3_AFF 0x101
#define CORE4_AFF 0x200
#define CORE5_AFF 0x201
#define CORE6_AFF 0x300
#define CORE7_AFF 0x301
/* cache */
#define CACHE_LINE_ADDR_MASK 0x3F
#define CACHE_LINE 64U
/* Device register address */
#define FDEV_BASE_ADDR 0x28000000
#define FDEV_END_ADDR 0x2FFFFFFF
/* Generic Timer */
#define GENERIC_TIMER_NS_IRQ_NUM 30
/* PCI */
#define FPCIE_NUM 1
#define FPCIE0_ID 0
#define FPCIE0_MISC_IRQ_NUM 59
#define FPCIE_CFG_MAX_NUM_OF_BUS 256
#define FPCIE_CFG_MAX_NUM_OF_DEV 32
#define FPCIE_CFG_MAX_NUM_OF_FUN 8
#define FPCI_CONFIG_BASE_ADDR 0x40000000
#define FPCI_CONFIG_REG_LENGTH 0x10000000
#define FPCI_IO_CONFIG_BASE_ADDR 0x50000000
#define FPCI_IO_CONFIG_REG_LENGTH 0x08000000
#define FPCI_MEM32_BASE_ADDR 0x58000000
#define FPCI_MEM32_REG_LENGTH 0x27ffffff
#define FPCI_MEM64_BASE_ADDR 0x1000000000
#define FPCI_MEM64_REG_LENGTH 0x1000000000
#define FPCI_EU0_C0_CONTROL_BASE_ADDR 0x29900000
#define FPCI_EU0_C1_CONTROL_BASE_ADDR 0x29910000
#define FPCI_EU0_C2_CONTROL_BASE_ADDR 0x29920000
#define FPCI_EU1_C0_CONTROL_BASE_ADDR 0x29930000
#define FPCI_EU1_C1_CONTROL_BASE_ADDR 0x29940000
#define FPCI_EU1_C2_CONTROL_BASE_ADDR 0x29950000
#define FPCI_EU0_CONFIG_BASE_ADDR 0x29900000
#define FPCI_EU1_CONFIG_BASE_ADDR 0x299A0000
#define FPCI_INTA_IRQ_NUM 60
#define FPCI_INTB_IRQ_NUM 61
#define FPCI_INTC_IRQ_NUM 62
#define FPCI_INTD_IRQ_NUM 63
#define FPCI_NEED_SKIP 0
#define FPCI_INTX_EOI
#define FPCI_INTX_PEU0_STAT 0x29100000
#define FPCI_INTX_PEU1_STAT 0x29101000
#define FPCI_INTX_EU0_C0_CONTROL 0x29000184
#define FPCI_INTX_EU0_C1_CONTROL 0x29010184
#define FPCI_INTX_EU0_C2_CONTROL 0x29020184
#define FPCI_INTX_EU1_C0_CONTROL 0x29030184
#define FPCI_INTX_EU1_C1_CONTROL 0x29040184
#define FPCI_INTX_EU1_C2_CONTROL 0x29050184
#define FPCI_INTX_CONTROL_NUM 6 /* Total number of controllers */
#define FPCI_INTX_SATA_NUM 2 /* Total number of controllers */
/* platform ahci host */
#define PLAT_AHCI_HOST_MAX_COUNT 5
#define AHCI_BASE_0 0
#define AHCI_BASE_1 0
#define AHCI_BASE_2 0
#define AHCI_BASE_3 0
#define AHCI_BASE_4 0
#define AHCI_IRQ_0 0
#define AHCI_IRQ_1 0
#define AHCI_IRQ_2 0
#define AHCI_IRQ_3 0
#define AHCI_IRQ_4 0
/* UART */
#if !defined(__ASSEMBLER__)
enum
{
FUART0_ID = 0,
FUART1_ID,
FUART2_ID,
FUART3_ID,
FUART_NUM
};
#endif
#define FUART0_IRQ_NUM 38
#define FUART0_BASE_ADDR 0x28000000
#define FUART0_CLK_FREQ_HZ 48000000
#define FUART1_IRQ_NUM 39
#define FUART1_BASE_ADDR 0x28001000
#define FUART1_CLK_FREQ_HZ 48000000
#define FUART2_IRQ_NUM 40
#define FUART2_BASE_ADDR 0x28002000
#define FUART2_CLK_FREQ_HZ 48000000
#define FUART3_IRQ_NUM 41
#define FUART3_BASE_ADDR 0x28003000
#define FUART3_CLK_FREQ_HZ 48000000
#define FT_STDOUT_BASE_ADDR FUART1_BASE_ADDR
#define FT_STDIN_BASE_ADDR FUART1_BASE_ADDR
/* QSPI */
#if !defined(__ASSEMBLER__)
enum
{
FQSPI0_ID = 0,
FQSPI_NUM
};
/* FQSPI cs 0_3, chip number */
enum
{
FQSPI_CS_0 = 0,
FQSPI_CS_1 = 1,
FQSPI_CS_2 = 2,
FQSPI_CS_3 = 3,
FQSPI_CS_NUM
};
#endif
#define FQSPI_BASE_ADDR 0x28014000
#define FQSPI_MEM_START_ADDR 0x0
#define FQSPI_MEM_END_ADDR 0x1FFFFFFF
/* GIC v3 */
#define ARM_GIC_NR_IRQS 1024
#define ARM_GIC_IRQ_START 0
#define FGIC_NUM 1
#define GICV3_BASE_ADDR 0x29a00000U
#define GICV3_DISTRIBUTOR_BASE_ADDR (GICV3_BASE_ADDR + 0)
#define GICV3_RD_BASE_ADDR (GICV3_BASE_ADDR + 0x100000U)
#define GICV3_RD_OFFSET (2U << 16)
#define FT_GICV3_VECTORTABLE_NUM GIC_INT_MAX_NUM
/*
* The maximum priority value that can be used in the GIC.
*/
#define GICV3_MAX_INTR_PRIO_VAL 240U
#define GICV3_INTR_PRIO_MASK 0x000000f0U
#define ARM_GIC_IPI_COUNT 16 /* MPCore IPI count */
#define SGI_INT_MAX 16
#define SPI_START_INT_NUM 32 /* SPI start at ID32 */
#define PPI_START_INT_NUM 16 /* PPI start at ID16 */
#define GIC_INT_MAX_NUM 1020 /* GIC max interrupts count */
/* GPIO */
#define FGPIO0_BASE_ADDR (0x28004000)
#define FGPIO1_BASE_ADDR (0x28005000)
#define FGPIO0_ID 0
#define FGPIO1_ID 1
#define FGPIO_NUM 2
#define FGPIO0_IRQ_NUM (42) /* gpio0 irq number */
#define FGPIO1_IRQ_NUM (43) /* gpio1 irq number */
/* IOMUX */
#define FIOCTRL_REG_BASE_ADDR 0x28180000
/* SPI */
#define FSPI0_BASE_ADDR 0x2800c000
#define FSPI1_BASE_ADDR 0x28013000
#define FSPI0_ID 0
#define FSPI1_ID 1
#define FSPI_CLK_FREQ_HZ 48000000
#define FSPI_NUM 2
#define FSPI0_IRQ_NUM 50
#define FSPI1_IRQ_NUM 51
/* I2C */
#if !defined(__ASSEMBLER__)
enum
{
FI2C0_ID = 0,
FI2C1_ID = 1,
FI2C2_ID,
FI2C3_ID,
FI2C_NUM
};
#endif
#define FI2C0_BASE_ADDR 0x28006000
#define FI2C1_BASE_ADDR 0x28007000
#define FI2C2_BASE_ADDR 0x28008000
#define FI2C3_BASE_ADDR 0x28009000
#define FI2C0_IRQ_NUM 44
#define FI2C1_IRQ_NUM 45
#define FI2C2_IRQ_NUM 46
#define FI2C3_IRQ_NUM 47
#define FI2C_CLK_FREQ_HZ 48000000 /* 48MHz */
/* WDT */
#if !defined(__ASSEMBLER__)
enum
{
FWDT0_ID = 0,
FWDT1_ID = 1,
FWDT_NUM
};
#endif
#define FWDT0_REFRESH_BASE_ADDR 0x2800a000
#define FWDT1_REFRESH_BASE_ADDR 0x28016000
#define FWDT_CONTROL_BASE_ADDR(x) ((x)+0x1000)
#define FWDT0_IRQ_NUM 48
#define FWDT1_IRQ_NUM 49
#define FWDT_CLK_FREQ_HZ 48000000 /* 48MHz */
/* SDCI */
#if !defined(__ASSEMBLER__)
enum
{
FSDMMC0_ID = 0,
FSDMMC_NUM
};
#endif
#define FSDMMC0_BASE_ADDR 0x28207C00
#define FSDMMC0_DMA_IRQ_NUM 52
#define FSDMMC0_CMD_IRQ_NUM 53
#define FSDMMC0_ERR_IRQ_NUM 54
#define FSDMMC_CLK_FREQ_HZ 600000000 /* 600 MHz */
/* GMAC */
#define FGMAC_PUB_REG_BASE_ADDR 0x2820B000 /* 公共寄存器基地址 */
#if !defined(__ASSEMBLER__)
enum
{
FGMAC0_ID = 0,
FGMAC1_ID,
FGMAC_NUM
};
#endif
#define FGMAC0_BASE_ADDR 0x2820C000
#define FGMAC1_BASE_ADDR 0x28210000
#define FGMAC0_IRQ_NUM 81
#define FGMAC1_IRQ_NUM 82
#define FGMAC_DMA_MIN_ALIGN 128
#define FGMAC_MAX_PACKET_SIZE 1600
/* rtc base address */
#define RTC_CONTROL_BASE 0x2800D000
#define FT_CPUS_NR CORE_NUM
/* can */
#define FCAN_CLK_FREQ_HZ 600000000
#define FCAN_REG_LENGTH 0x1000
#define FCAN0_BASE_ADDR 0x28207000
#define FCAN1_BASE_ADDR 0x28207400
#define FCAN2_BASE_ADDR 0x28207800
#define FCAN0_IRQ_NUM 119
#define FCAN1_IRQ_NUM 123
#define FCAN2_IRQNUM 124
#if !defined(__ASSEMBLER__)
enum
{
FCAN0_ID = 0,
FCAN1_ID = 1,
FCAN2_ID = 2,
FCAN_NUM
};
#endif
#ifdef __cplusplus
}
#endif
#endif // !

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bsp/phytium/libraries/standalone/board/e2000/d/fiopad.h
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#ifndef BOARD_E2000D_FIOPAD_H
#define BOARD_E2000D_FIOPAD_H
#ifdef __cplusplus
extern "C"
{
#endif
/***************************** Include Files *********************************/
#include "fiopad_comm.h"
/************************** Constant Definitions *****************************/
/* register offset of iopad function / pull / driver strength */
#define FIOPAD_AN55 (FPinIndex)FIOPAD_INDEX(FIOPAD_0_FUNC_OFFSET)
#define FIOPAD_AW43 (FPinIndex)FIOPAD_INDEX(FIOPAD_2_FUNC_OFFSET)
#define FIOPAD_AR51 (FPinIndex)FIOPAD_INDEX(FIOPAD_9_FUNC_OFFSET)
#define FIOPAD_AJ51 (FPinIndex)FIOPAD_INDEX(FIOPAD_10_FUNC_OFFSET)
#define FIOPAD_AL51 (FPinIndex)FIOPAD_INDEX(FIOPAD_11_FUNC_OFFSET)
#define FIOPAD_AL49 (FPinIndex)FIOPAD_INDEX(FIOPAD_12_FUNC_OFFSET)
#define FIOPAD_AN47 (FPinIndex)FIOPAD_INDEX(FIOPAD_13_FUNC_OFFSET)
#define FIOPAD_AR47 (FPinIndex)FIOPAD_INDEX(FIOPAD_14_FUNC_OFFSET)
#define FIOPAD_BA53 (FPinIndex)FIOPAD_INDEX(FIOPAD_15_FUNC_OFFSET)
#define FIOPAD_BA55 (FPinIndex)FIOPAD_INDEX(FIOPAD_16_FUNC_OFFSET)
#define FIOPAD_AW53 (FPinIndex)FIOPAD_INDEX(FIOPAD_17_FUNC_OFFSET)
#define FIOPAD_AW55 (FPinIndex)FIOPAD_INDEX(FIOPAD_18_FUNC_OFFSET)
#define FIOPAD_AU51 (FPinIndex)FIOPAD_INDEX(FIOPAD_19_FUNC_OFFSET)
#define FIOPAD_AN53 (FPinIndex)FIOPAD_INDEX(FIOPAD_20_FUNC_OFFSET)
#define FIOPAD_AL55 (FPinIndex)FIOPAD_INDEX(FIOPAD_21_FUNC_OFFSET)
#define FIOPAD_AJ55 (FPinIndex)FIOPAD_INDEX(FIOPAD_22_FUNC_OFFSET)
#define FIOPAD_AJ53 (FPinIndex)FIOPAD_INDEX(FIOPAD_23_FUNC_OFFSET)
#define FIOPAD_AG55 (FPinIndex)FIOPAD_INDEX(FIOPAD_24_FUNC_OFFSET)
#define FIOPAD_AG53 (FPinIndex)FIOPAD_INDEX(FIOPAD_25_FUNC_OFFSET)
#define FIOPAD_AE55 (FPinIndex)FIOPAD_INDEX(FIOPAD_26_FUNC_OFFSET)
#define FIOPAD_AC55 (FPinIndex)FIOPAD_INDEX(FIOPAD_27_FUNC_OFFSET)
#define FIOPAD_AC53 (FPinIndex)FIOPAD_INDEX(FIOPAD_28_FUNC_OFFSET)
#define FIOPAD_AR45 (FPinIndex)FIOPAD_INDEX(FIOPAD_31_FUNC_OFFSET)
#define FIOPAD_BA51 (FPinIndex)FIOPAD_INDEX(FIOPAD_32_FUNC_OFFSET)
#define FIOPAD_BA49 (FPinIndex)FIOPAD_INDEX(FIOPAD_33_FUNC_OFFSET)
#define FIOPAD_AR55 (FPinIndex)FIOPAD_INDEX(FIOPAD_34_FUNC_OFFSET)
#define FIOPAD_AU55 (FPinIndex)FIOPAD_INDEX(FIOPAD_35_FUNC_OFFSET)
#define FIOPAD_AR53 (FPinIndex)FIOPAD_INDEX(FIOPAD_36_FUNC_OFFSET)
#define FIOPAD_BA45 (FPinIndex)FIOPAD_INDEX(FIOPAD_37_FUNC_OFFSET)
#define FIOPAD_AW51 (FPinIndex)FIOPAD_INDEX(FIOPAD_38_FUNC_OFFSET)
#define FIOPAD_A31 (FPinIndex)FIOPAD_INDEX(FIOPAD_39_FUNC_OFFSET)
#define FIOPAD_R53 (FPinIndex)FIOPAD_INDEX(FIOPAD_40_FUNC_OFFSET)
#define FIOPAD_R55 (FPinIndex)FIOPAD_INDEX(FIOPAD_41_FUNC_OFFSET)
#define FIOPAD_U55 (FPinIndex)FIOPAD_INDEX(FIOPAD_42_FUNC_OFFSET)
#define FIOPAD_W55 (FPinIndex)FIOPAD_INDEX(FIOPAD_43_FUNC_OFFSET)
#define FIOPAD_U53 (FPinIndex)FIOPAD_INDEX(FIOPAD_44_FUNC_OFFSET)
#define FIOPAD_AA53 (FPinIndex)FIOPAD_INDEX(FIOPAD_45_FUNC_OFFSET)
#define FIOPAD_AA55 (FPinIndex)FIOPAD_INDEX(FIOPAD_46_FUNC_OFFSET)
#define FIOPAD_AW47 (FPinIndex)FIOPAD_INDEX(FIOPAD_47_FUNC_OFFSET)
#define FIOPAD_AU47 (FPinIndex)FIOPAD_INDEX(FIOPAD_48_FUNC_OFFSET)
#define FIOPAD_A35 (FPinIndex)FIOPAD_INDEX(FIOPAD_49_FUNC_OFFSET)
#define FIOPAD_C35 (FPinIndex)FIOPAD_INDEX(FIOPAD_50_FUNC_OFFSET)
#define FIOPAD_C33 (FPinIndex)FIOPAD_INDEX(FIOPAD_51_FUNC_OFFSET)
#define FIOPAD_A33 (FPinIndex)FIOPAD_INDEX(FIOPAD_52_FUNC_OFFSET)
#define FIOPAD_A37 (FPinIndex)FIOPAD_INDEX(FIOPAD_53_FUNC_OFFSET)
#define FIOPAD_A39 (FPinIndex)FIOPAD_INDEX(FIOPAD_54_FUNC_OFFSET)
#define FIOPAD_A41 (FPinIndex)FIOPAD_INDEX(FIOPAD_55_FUNC_OFFSET)
#define FIOPAD_C41 (FPinIndex)FIOPAD_INDEX(FIOPAD_56_FUNC_OFFSET)
#define FIOPAD_A43 (FPinIndex)FIOPAD_INDEX(FIOPAD_57_FUNC_OFFSET)
#define FIOPAD_A45 (FPinIndex)FIOPAD_INDEX(FIOPAD_58_FUNC_OFFSET)
#define FIOPAD_C45 (FPinIndex)FIOPAD_INDEX(FIOPAD_59_FUNC_OFFSET)
#define FIOPAD_A47 (FPinIndex)FIOPAD_INDEX(FIOPAD_60_FUNC_OFFSET)
#define FIOPAD_A29 (FPinIndex)FIOPAD_INDEX(FIOPAD_61_FUNC_OFFSET)
#define FIOPAD_C29 (FPinIndex)FIOPAD_INDEX(FIOPAD_62_FUNC_OFFSET)
#define FIOPAD_C27 (FPinIndex)FIOPAD_INDEX(FIOPAD_63_FUNC_OFFSET)
#define FIOPAD_A27 (FPinIndex)FIOPAD_INDEX(FIOPAD_64_FUNC_OFFSET)
#define FIOPAD_AJ49 (FPinIndex)FIOPAD_INDEX(FIOPAD_65_FUNC_OFFSET)
#define FIOPAD_AL45 (FPinIndex)FIOPAD_INDEX(FIOPAD_66_FUNC_OFFSET)
#define FIOPAD_AL43 (FPinIndex)FIOPAD_INDEX(FIOPAD_67_FUNC_OFFSET)
#define FIOPAD_AN45 (FPinIndex)FIOPAD_INDEX(FIOPAD_68_FUNC_OFFSET)
#define FIOPAD_AG47 (FPinIndex)FIOPAD_INDEX(FIOPAD_148_FUNC_OFFSET)
#define FIOPAD_AJ47 (FPinIndex)FIOPAD_INDEX(FIOPAD_69_FUNC_OFFSET)
#define FIOPAD_AG45 (FPinIndex)FIOPAD_INDEX(FIOPAD_70_FUNC_OFFSET)
#define FIOPAD_AE51 (FPinIndex)FIOPAD_INDEX(FIOPAD_71_FUNC_OFFSET)
#define FIOPAD_AE49 (FPinIndex)FIOPAD_INDEX(FIOPAD_72_FUNC_OFFSET)
#define FIOPAD_AG51 (FPinIndex)FIOPAD_INDEX(FIOPAD_73_FUNC_OFFSET)
#define FIOPAD_AJ45 (FPinIndex)FIOPAD_INDEX(FIOPAD_74_FUNC_OFFSET)
#define FIOPAD_AC51 (FPinIndex)FIOPAD_INDEX(FIOPAD_75_FUNC_OFFSET)
#define FIOPAD_AC49 (FPinIndex)FIOPAD_INDEX(FIOPAD_76_FUNC_OFFSET)
#define FIOPAD_AE47 (FPinIndex)FIOPAD_INDEX(FIOPAD_77_FUNC_OFFSET)
#define FIOPAD_W47 (FPinIndex)FIOPAD_INDEX(FIOPAD_78_FUNC_OFFSET)
#define FIOPAD_W51 (FPinIndex)FIOPAD_INDEX(FIOPAD_79_FUNC_OFFSET)
#define FIOPAD_W49 (FPinIndex)FIOPAD_INDEX(FIOPAD_80_FUNC_OFFSET)
#define FIOPAD_U51 (FPinIndex)FIOPAD_INDEX(FIOPAD_81_FUNC_OFFSET)
#define FIOPAD_U49 (FPinIndex)FIOPAD_INDEX(FIOPAD_82_FUNC_OFFSET)
#define FIOPAD_AE45 (FPinIndex)FIOPAD_INDEX(FIOPAD_83_FUNC_OFFSET)
#define FIOPAD_AC45 (FPinIndex)FIOPAD_INDEX(FIOPAD_84_FUNC_OFFSET)
#define FIOPAD_AE43 (FPinIndex)FIOPAD_INDEX(FIOPAD_85_FUNC_OFFSET)
#define FIOPAD_AA43 (FPinIndex)FIOPAD_INDEX(FIOPAD_86_FUNC_OFFSET)
#define FIOPAD_AA45 (FPinIndex)FIOPAD_INDEX(FIOPAD_87_FUNC_OFFSET)
#define FIOPAD_W45 (FPinIndex)FIOPAD_INDEX(FIOPAD_88_FUNC_OFFSET)
#define FIOPAD_AA47 (FPinIndex)FIOPAD_INDEX(FIOPAD_89_FUNC_OFFSET)
#define FIOPAD_U45 (FPinIndex)FIOPAD_INDEX(FIOPAD_90_FUNC_OFFSET)
#define FIOPAD_G55 (FPinIndex)FIOPAD_INDEX(FIOPAD_91_FUNC_OFFSET)
#define FIOPAD_J55 (FPinIndex)FIOPAD_INDEX(FIOPAD_92_FUNC_OFFSET)
#define FIOPAD_L53 (FPinIndex)FIOPAD_INDEX(FIOPAD_93_FUNC_OFFSET)
#define FIOPAD_C55 (FPinIndex)FIOPAD_INDEX(FIOPAD_94_FUNC_OFFSET)
#define FIOPAD_E55 (FPinIndex)FIOPAD_INDEX(FIOPAD_95_FUNC_OFFSET)
#define FIOPAD_J53 (FPinIndex)FIOPAD_INDEX(FIOPAD_96_FUNC_OFFSET)
#define FIOPAD_L55 (FPinIndex)FIOPAD_INDEX(FIOPAD_97_FUNC_OFFSET)
#define FIOPAD_N55 (FPinIndex)FIOPAD_INDEX(FIOPAD_98_FUNC_OFFSET)
#define FIOPAD_C53 (FPinIndex)FIOPAD_INDEX(FIOPAD_29_FUNC_OFFSET)
#define FIOPAD_E53 (FPinIndex)FIOPAD_INDEX(FIOPAD_30_FUNC_OFFSET)
#define FIOPAD_E27 (FPinIndex)FIOPAD_INDEX(FIOPAD_99_FUNC_OFFSET)
#define FIOPAD_G27 (FPinIndex)FIOPAD_INDEX(FIOPAD_100_FUNC_OFFSET)
#define FIOPAD_N37 (FPinIndex)FIOPAD_INDEX(FIOPAD_101_FUNC_OFFSET)
#define FIOPAD_N35 (FPinIndex)FIOPAD_INDEX(FIOPAD_102_FUNC_OFFSET)
#define FIOPAD_J29 (FPinIndex)FIOPAD_INDEX(FIOPAD_103_FUNC_OFFSET)
#define FIOPAD_N29 (FPinIndex)FIOPAD_INDEX(FIOPAD_104_FUNC_OFFSET)
#define FIOPAD_L29 (FPinIndex)FIOPAD_INDEX(FIOPAD_105_FUNC_OFFSET)
#define FIOPAD_N41 (FPinIndex)FIOPAD_INDEX(FIOPAD_106_FUNC_OFFSET)
#define FIOPAD_N39 (FPinIndex)FIOPAD_INDEX(FIOPAD_107_FUNC_OFFSET)
#define FIOPAD_L27 (FPinIndex)FIOPAD_INDEX(FIOPAD_108_FUNC_OFFSET)
#define FIOPAD_J27 (FPinIndex)FIOPAD_INDEX(FIOPAD_109_FUNC_OFFSET)
#define FIOPAD_J25 (FPinIndex)FIOPAD_INDEX(FIOPAD_110_FUNC_OFFSET)
#define FIOPAD_E25 (FPinIndex)FIOPAD_INDEX(FIOPAD_111_FUNC_OFFSET)
#define FIOPAD_G25 (FPinIndex)FIOPAD_INDEX(FIOPAD_112_FUNC_OFFSET)
#define FIOPAD_N23 (FPinIndex)FIOPAD_INDEX(FIOPAD_113_FUNC_OFFSET)
#define FIOPAD_L25 (FPinIndex)FIOPAD_INDEX(FIOPAD_114_FUNC_OFFSET)
#define FIOPAD_J33 (FPinIndex)FIOPAD_INDEX(FIOPAD_115_FUNC_OFFSET)
#define FIOPAD_J35 (FPinIndex)FIOPAD_INDEX(FIOPAD_116_FUNC_OFFSET)
#define FIOPAD_G37 (FPinIndex)FIOPAD_INDEX(FIOPAD_117_FUNC_OFFSET)
#define FIOPAD_E39 (FPinIndex)FIOPAD_INDEX(FIOPAD_118_FUNC_OFFSET)
#define FIOPAD_L39 (FPinIndex)FIOPAD_INDEX(FIOPAD_119_FUNC_OFFSET)
#define FIOPAD_C39 (FPinIndex)FIOPAD_INDEX(FIOPAD_120_FUNC_OFFSET)
#define FIOPAD_E37 (FPinIndex)FIOPAD_INDEX(FIOPAD_121_FUNC_OFFSET)
#define FIOPAD_L41 (FPinIndex)FIOPAD_INDEX(FIOPAD_122_FUNC_OFFSET)
#define FIOPAD_J39 (FPinIndex)FIOPAD_INDEX(FIOPAD_123_FUNC_OFFSET)
#define FIOPAD_J37 (FPinIndex)FIOPAD_INDEX(FIOPAD_124_FUNC_OFFSET)
#define FIOPAD_L35 (FPinIndex)FIOPAD_INDEX(FIOPAD_125_FUNC_OFFSET)
#define FIOPAD_E33 (FPinIndex)FIOPAD_INDEX(FIOPAD_126_FUNC_OFFSET)
#define FIOPAD_E31 (FPinIndex)FIOPAD_INDEX(FIOPAD_127_FUNC_OFFSET)
#define FIOPAD_G31 (FPinIndex)FIOPAD_INDEX(FIOPAD_128_FUNC_OFFSET)
#define FIOPAD_J31 (FPinIndex)FIOPAD_INDEX(FIOPAD_129_FUNC_OFFSET)
#define FIOPAD_L33 (FPinIndex)FIOPAD_INDEX(FIOPAD_130_FUNC_OFFSET)
#define FIOPAD_N31 (FPinIndex)FIOPAD_INDEX(FIOPAD_131_FUNC_OFFSET)
#define FIOPAD_R47 (FPinIndex)FIOPAD_INDEX(FIOPAD_132_FUNC_OFFSET)
#define FIOPAD_R45 (FPinIndex)FIOPAD_INDEX(FIOPAD_133_FUNC_OFFSET)
#define FIOPAD_N47 (FPinIndex)FIOPAD_INDEX(FIOPAD_134_FUNC_OFFSET)
#define FIOPAD_N51 (FPinIndex)FIOPAD_INDEX(FIOPAD_135_FUNC_OFFSET)
#define FIOPAD_L51 (FPinIndex)FIOPAD_INDEX(FIOPAD_136_FUNC_OFFSET)
#define FIOPAD_J51 (FPinIndex)FIOPAD_INDEX(FIOPAD_137_FUNC_OFFSET)
#define FIOPAD_J41 (FPinIndex)FIOPAD_INDEX(FIOPAD_138_FUNC_OFFSET)
#define FIOPAD_E43 (FPinIndex)FIOPAD_INDEX(FIOPAD_139_FUNC_OFFSET)
#define FIOPAD_G43 (FPinIndex)FIOPAD_INDEX(FIOPAD_140_FUNC_OFFSET)
#define FIOPAD_J43 (FPinIndex)FIOPAD_INDEX(FIOPAD_141_FUNC_OFFSET)
#define FIOPAD_J45 (FPinIndex)FIOPAD_INDEX(FIOPAD_142_FUNC_OFFSET)
#define FIOPAD_N45 (FPinIndex)FIOPAD_INDEX(FIOPAD_143_FUNC_OFFSET)
#define FIOPAD_L47 (FPinIndex)FIOPAD_INDEX(FIOPAD_144_FUNC_OFFSET)
#define FIOPAD_L45 (FPinIndex)FIOPAD_INDEX(FIOPAD_145_FUNC_OFFSET)
#define FIOPAD_N49 (FPinIndex)FIOPAD_INDEX(FIOPAD_146_FUNC_OFFSET)
#define FIOPAD_J49 (FPinIndex)FIOPAD_INDEX(FIOPAD_147_FUNC_OFFSET)
/* register offset of iopad delay */
#define FIOPAD_AJ51_DELAY (FPinIndex)FIOPAD_INDEX(FIOPAD_10_DELAY_OFFSET)
#define FIOPAD_AL51_DELAY (FPinIndex)FIOPAD_INDEX(FIOPAD_11_DELAY_OFFSET)
#define FIOPAD_AL49_DELAY (FPinIndex)FIOPAD_INDEX(FIOPAD_12_DELAY_OFFSET)
#define FIOPAD_AN47_DELAY (FPinIndex)FIOPAD_INDEX(FIOPAD_13_DELAY_OFFSET)
#define FIOPAD_AR47_DELAY (FPinIndex)FIOPAD_INDEX(FIOPAD_14_DELAY_OFFSET)
#define FIOPAD_AJ53_DELAY (FPinIndex)FIOPAD_INDEX(FIOPAD_23_DELAY_OFFSET)
#define FIOPAD_AG55_DELAY (FPinIndex)FIOPAD_INDEX(FIOPAD_24_DELAY_OFFSET)
#define FIOPAD_AG53_DELAY (FPinIndex)FIOPAD_INDEX(FIOPAD_25_DELAY_OFFSET)
#define FIOPAD_AE55_DELAY (FPinIndex)FIOPAD_INDEX(FIOPAD_26_DELAY_OFFSET)
#define FIOPAD_BA51_DELAY (FPinIndex)FIOPAD_INDEX(FIOPAD_32_DELAY_OFFSET)
#define FIOPAD_BA49_DELAY (FPinIndex)FIOPAD_INDEX(FIOPAD_33_DELAY_OFFSET)
#define FIOPAD_AR55_DELAY (FPinIndex)FIOPAD_INDEX(FIOPAD_34_DELAY_OFFSET)
#define FIOPAD_AU55_DELAY (FPinIndex)FIOPAD_INDEX(FIOPAD_35_DELAY_OFFSET)
#define FIOPAD_A41_DELAY (FPinIndex)FIOPAD_INDEX(FIOPAD_55_DELAY_OFFSET)
#define FIOPAD_C41_DELAY (FPinIndex)FIOPAD_INDEX(FIOPAD_56_DELAY_OFFSET)
#define FIOPAD_A43_DELAY (FPinIndex)FIOPAD_INDEX(FIOPAD_57_DELAY_OFFSET)
#define FIOPAD_A45_DELAY (FPinIndex)FIOPAD_INDEX(FIOPAD_58_DELAY_OFFSET)
#define FIOPAD_C45_DELAY (FPinIndex)FIOPAD_INDEX(FIOPAD_59_DELAY_OFFSET)
#define FIOPAD_A47_DELAY (FPinIndex)FIOPAD_INDEX(FIOPAD_60_DELAY_OFFSET)
#define FIOPAD_A29_DELAY (FPinIndex)FIOPAD_INDEX(FIOPAD_61_DELAY_OFFSET)
#define FIOPAD_C29_DELAY (FPinIndex)FIOPAD_INDEX(FIOPAD_62_DELAY_OFFSET)
#define FIOPAD_C27_DELAY (FPinIndex)FIOPAD_INDEX(FIOPAD_63_DELAY_OFFSET)
#define FIOPAD_A27_DELAY (FPinIndex)FIOPAD_INDEX(FIOPAD_64_DELAY_OFFSET)
#define FIOPAD_AJ49_DELAY (FPinIndex)FIOPAD_INDEX(FIOPAD_65_DELAY_OFFSET)
#define FIOPAD_AL45_DELAY (FPinIndex)FIOPAD_INDEX(FIOPAD_66_DELAY_OFFSET)
#define FIOPAD_AL43_DELAY (FPinIndex)FIOPAD_INDEX(FIOPAD_67_DELAY_OFFSET)
#define FIOPAD_AN45_DELAY (FPinIndex)FIOPAD_INDEX(FIOPAD_68_DELAY_OFFSET)
#define FIOPAD_AG47_DELAY (FPinIndex)FIOPAD_INDEX(FIOPAD_148_DELAY_OFFSET)
#define FIOPAD_AJ47_DELAY (FPinIndex)FIOPAD_INDEX(FIOPAD_69_DELAY_OFFSET)
#define FIOPAD_AG45_DELAY (FPinIndex)FIOPAD_INDEX(FIOPAD_70_DELAY_OFFSET)
#define FIOPAD_AE51_DELAY (FPinIndex)FIOPAD_INDEX(FIOPAD_71_DELAY_OFFSET)
#define FIOPAD_AE49_DELAY (FPinIndex)FIOPAD_INDEX(FIOPAD_72_DELAY_OFFSET)
#define FIOPAD_AG51_DELAY (FPinIndex)FIOPAD_INDEX(FIOPAD_73_DELAY_OFFSET)
#define FIOPAD_AJ45_DELAY (FPinIndex)FIOPAD_INDEX(FIOPAD_74_DELAY_OFFSET)
#define FIOPAD_AC51_DELAY (FPinIndex)FIOPAD_INDEX(FIOPAD_75_DELAY_OFFSET)
#define FIOPAD_AC49_DELAY (FPinIndex)FIOPAD_INDEX(FIOPAD_76_DELAY_OFFSET)
#define FIOPAD_AE47_DELAY (FPinIndex)FIOPAD_INDEX(FIOPAD_77_DELAY_OFFSET)
#define FIOPAD_W47_DELAY (FPinIndex)FIOPAD_INDEX(FIOPAD_78_DELAY_OFFSET)
#define FIOPAD_W49_DELAY (FPinIndex)FIOPAD_INDEX(FIOPAD_80_DELAY_OFFSET)
#define FIOPAD_U51_DELAY (FPinIndex)FIOPAD_INDEX(FIOPAD_81_DELAY_OFFSET)
#define FIOPAD_U49_DELAY (FPinIndex)FIOPAD_INDEX(FIOPAD_82_DELAY_OFFSET)
#define FIOPAD_AE45_DELAY (FPinIndex)FIOPAD_INDEX(FIOPAD_83_DELAY_OFFSET)
#define FIOPAD_AC45_DELAY (FPinIndex)FIOPAD_INDEX(FIOPAD_84_DELAY_OFFSET)
#define FIOPAD_AE43_DELAY (FPinIndex)FIOPAD_INDEX(FIOPAD_85_DELAY_OFFSET)
#define FIOPAD_AA43_DELAY (FPinIndex)FIOPAD_INDEX(FIOPAD_86_DELAY_OFFSET)
#define FIOPAD_AA45_DELAY (FPinIndex)FIOPAD_INDEX(FIOPAD_87_DELAY_OFFSET)
#define FIOPAD_W45_DELAY (FPinIndex)FIOPAD_INDEX(FIOPAD_88_DELAY_OFFSET)
#define FIOPAD_AA47_DELAY (FPinIndex)FIOPAD_INDEX(FIOPAD_89_DELAY_OFFSET)
#define FIOPAD_U45_DELAY (FPinIndex)FIOPAD_INDEX(FIOPAD_90_DELAY_OFFSET)
#define FIOPAD_J55_DELAY (FPinIndex)FIOPAD_INDEX(FIOPAD_92_DELAY_OFFSET)
#define FIOPAD_L53_DELAY (FPinIndex)FIOPAD_INDEX(FIOPAD_93_DELAY_OFFSET)
#define FIOPAD_C55_DELAY (FPinIndex)FIOPAD_INDEX(FIOPAD_94_DELAY_OFFSET)
#define FIOPAD_E55_DELAY (FPinIndex)FIOPAD_INDEX(FIOPAD_95_DELAY_OFFSET)
#define FIOPAD_J53_DELAY (FPinIndex)FIOPAD_INDEX(FIOPAD_96_DELAY_OFFSET)
#define FIOPAD_L55_DELAY (FPinIndex)FIOPAD_INDEX(FIOPAD_97_DELAY_OFFSET)
#define FIOPAD_N55_DELAY (FPinIndex)FIOPAD_INDEX(FIOPAD_98_DELAY_OFFSET)
#define FIOPAD_E27_DELAY (FPinIndex)FIOPAD_INDEX(FIOPAD_99_DELAY_OFFSET)
#define FIOPAD_G27_DELAY (FPinIndex)FIOPAD_INDEX(FIOPAD_100_DELAY_OFFSET)
#define FIOPAD_N37_DELAY (FPinIndex)FIOPAD_INDEX(FIOPAD_101_DELAY_OFFSET)
#define FIOPAD_N35_DELAY (FPinIndex)FIOPAD_INDEX(FIOPAD_102_DELAY_OFFSET)
#define FIOPAD_J29_DELAY (FPinIndex)FIOPAD_INDEX(FIOPAD_103_DELAY_OFFSET)
#define FIOPAD_N29_DELAY (FPinIndex)FIOPAD_INDEX(FIOPAD_104_DELAY_OFFSET)
#define FIOPAD_L29_DELAY (FPinIndex)FIOPAD_INDEX(FIOPAD_105_DELAY_OFFSET)
#define FIOPAD_N41_DELAY (FPinIndex)FIOPAD_INDEX(FIOPAD_106_DELAY_OFFSET)
#define FIOPAD_N39_DELAY (FPinIndex)FIOPAD_INDEX(FIOPAD_107_DELAY_OFFSET)
#define FIOPAD_L27_DELAY (FPinIndex)FIOPAD_INDEX(FIOPAD_108_DELAY_OFFSET)
#define FIOPAD_J27_DELAY (FPinIndex)FIOPAD_INDEX(FIOPAD_109_DELAY_OFFSET)
#define FIOPAD_J25_DELAY (FPinIndex)FIOPAD_INDEX(FIOPAD_110_DELAY_OFFSET)
#define FIOPAD_E25_DELAY (FPinIndex)FIOPAD_INDEX(FIOPAD_111_DELAY_OFFSET)
#define FIOPAD_G25_DELAY (FPinIndex)FIOPAD_INDEX(FIOPAD_112_DELAY_OFFSET)
#define FIOPAD_J33_DELAY (FPinIndex)FIOPAD_INDEX(FIOPAD_115_DELAY_OFFSET)
#define FIOPAD_J35_DELAY (FPinIndex)FIOPAD_INDEX(FIOPAD_116_DELAY_OFFSET)
#define FIOPAD_G37_DELAY (FPinIndex)FIOPAD_INDEX(FIOPAD_117_DELAY_OFFSET)
#define FIOPAD_E39_DELAY (FPinIndex)FIOPAD_INDEX(FIOPAD_118_DELAY_OFFSET)
#define FIOPAD_L39_DELAY (FPinIndex)FIOPAD_INDEX(FIOPAD_119_DELAY_OFFSET)
#define FIOPAD_C39_DELAY (FPinIndex)FIOPAD_INDEX(FIOPAD_120_DELAY_OFFSET)
#define FIOPAD_E37_DELAY (FPinIndex)FIOPAD_INDEX(FIOPAD_121_DELAY_OFFSET)
#define FIOPAD_L41_DELAY (FPinIndex)FIOPAD_INDEX(FIOPAD_122_DELAY_OFFSET)
#define FIOPAD_J39_DELAY (FPinIndex)FIOPAD_INDEX(FIOPAD_123_DELAY_OFFSET)
#define FIOPAD_J37_DELAY (FPinIndex)FIOPAD_INDEX(FIOPAD_124_DELAY_OFFSET)
#define FIOPAD_L35_DELAY (FPinIndex)FIOPAD_INDEX(FIOPAD_125_DELAY_OFFSET)
#define FIOPAD_E33_DELAY (FPinIndex)FIOPAD_INDEX(FIOPAD_126_DELAY_OFFSET)
#define FIOPAD_E31_DELAY (FPinIndex)FIOPAD_INDEX(FIOPAD_127_DELAY_OFFSET)
#define FIOPAD_G31_DELAY (FPinIndex)FIOPAD_INDEX(FIOPAD_128_DELAY_OFFSET)
#define FIOPAD_L51_DELAY (FPinIndex)FIOPAD_INDEX(FIOPAD_136_DELAY_OFFSET)
#define FIOPAD_J51_DELAY (FPinIndex)FIOPAD_INDEX(FIOPAD_137_DELAY_OFFSET)
#define FIOPAD_J41_DELAY (FPinIndex)FIOPAD_INDEX(FIOPAD_138_DELAY_OFFSET)
#define FIOPAD_E43_DELAY (FPinIndex)FIOPAD_INDEX(FIOPAD_139_DELAY_OFFSET)
#define FIOPAD_G43_DELAY (FPinIndex)FIOPAD_INDEX(FIOPAD_140_DELAY_OFFSET)
#define FIOPAD_J43_DELAY (FPinIndex)FIOPAD_INDEX(FIOPAD_141_DELAY_OFFSET)
#define FIOPAD_J45_DELAY (FPinIndex)FIOPAD_INDEX(FIOPAD_142_DELAY_OFFSET)
#define FIOPAD_N45_DELAY (FPinIndex)FIOPAD_INDEX(FIOPAD_143_DELAY_OFFSET)
#define FIOPAD_L47_DELAY (FPinIndex)FIOPAD_INDEX(FIOPAD_144_DELAY_OFFSET)
#define FIOPAD_L45_DELAY (FPinIndex)FIOPAD_INDEX(FIOPAD_145_DELAY_OFFSET)
#define FIOPAD_N49_DELAY (FPinIndex)FIOPAD_INDEX(FIOPAD_146_DELAY_OFFSET)
#define FIOPAD_J49_DELAY (FPinIndex)FIOPAD_INDEX(FIOPAD_147_DELAY_OFFSET)
/***************** Macros (Inline Functions) Definitions *********************/
/************************** Function Prototypes ******************************/
/*****************************************************************************/
#ifdef __cplusplus
}
#endif
#endif

555
bsp/phytium/libraries/standalone/board/e2000/d/fiopad_config.c
View File

@ -1,555 +0,0 @@
/*
* Copyright : (C) 2022 Phytium Information Technology, Inc.
* All Rights Reserved.
*
* This program is OPEN SOURCE software: you can redistribute it and/or modify it
* under the terms of the Phytium Public License as published by the Phytium Technology Co.,Ltd,
* either version 1.0 of the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,but WITHOUT ANY WARRANTY;
* without even the implied warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.
* See the Phytium Public License for more details.
*
*
* FilePath: fiopad_config.c
* Date: 2022-02-10 14:53:42
* LastEditTime: 2022-02-18 08:25:29
* Description:  This file is for io-pad function definition
*
* Modify History:
* Ver   Who        Date         Changes
* ----- ------     --------    --------------------------------------
* 1.0 huanghe 2021/11/5 init commit
* 1.1 zhugengyu 2022/3/21 adopt to lastest tech spec.
*/
/***************************** Include Files *********************************/
#include "fiopad.h"
#include "fparameters.h"
#include "fdebug.h"
#include "fpinctrl.h"
#include "fassert.h"
/************************** Constant Definitions *****************************/
/**************************** Type Definitions *******************************/
/***************** Macros (Inline Functions) Definitions *********************/
#define FIOPAD_DEBUG_TAG "FIOPAD-CFG"
#define FIOPAD_ERROR(format, ...) FT_DEBUG_PRINT_E(FIOPAD_DEBUG_TAG, format, ##__VA_ARGS__)
#define FIOPAD_WARN(format, ...) FT_DEBUG_PRINT_W(FIOPAD_DEBUG_TAG, format, ##__VA_ARGS__)
#define FIOPAD_INFO(format, ...) FT_DEBUG_PRINT_I(FIOPAD_DEBUG_TAG, format, ##__VA_ARGS__)
#define FIOPAD_DEBUG(format, ...) FT_DEBUG_PRINT_D(FIOPAD_DEBUG_TAG, format, ##__VA_ARGS__)
/************************** Function Prototypes ******************************/
/*****************************************************************************/
/**
* @name: FIOPadSetSpimMux
* @msg: set iopad mux for spim
* @return {*}
* @param {u32} spim_id, instance id of spi
*/
void FIOPadSetSpimMux(u32 spim_id)
{
if (FSPI2_ID == spim_id)
{
FPinSetFunc(FIOPAD_A29, FPIN_FUNC0); /* sclk */
FPinSetFunc(FIOPAD_C29, FPIN_FUNC0); /* txd */
FPinSetFunc(FIOPAD_C27, FPIN_FUNC0); /* rxd */
FPinSetFunc(FIOPAD_A27, FPIN_FUNC0); /* csn0 */
}
}
/**
* @name: FIOPadSetGpioMux
* @msg: set iopad mux for gpio
* @return {*}
* @param {u32} gpio_id, instance id of gpio
* @param {u32} pin_id, index of pin
*/
void FIOPadSetGpioMux(u32 gpio_id, u32 pin_id)
{
if (FGPIO3_ID == gpio_id)
{
switch (pin_id)
{
case 3: /* gpio 3-a-3 */
FPinSetFunc(FIOPAD_A29, FPIN_FUNC6);
break;
case 4: /* gpio 3-a-4 */
FPinSetFunc(FIOPAD_C29, FPIN_FUNC6);
break;
case 5: /* gpio 3-a-5 */
FPinSetFunc(FIOPAD_C27, FPIN_FUNC6);
break;
case 6: /* gpio 3-a-6 */
FPinSetFunc(FIOPAD_A27, FPIN_FUNC6);
break;
case 7: /* gpio 3-a-7 */ /*cannot use this pin*/
FPinSetFunc(FIOPAD_AJ49, FPIN_FUNC6);
break;
case 8: /* gpio 3-a-8 */
FPinSetFunc(FIOPAD_AL45, FPIN_FUNC6);
break;
case 9: /* gpio 3-a-9 */
FPinSetFunc(FIOPAD_AL43, FPIN_FUNC6);
break;
default:
break;
}
}
else if (FGPIO4_ID == gpio_id)
{
switch (pin_id)
{
case 5: /* gpio 4-a-5 */
FPinSetFunc(FIOPAD_W47, FPIN_FUNC6);
break;
case 9: /* gpio 4-a-9 */
FPinSetFunc(FIOPAD_U49, FPIN_FUNC6);
break;
case 10: /* gpio 4-a-10 */
FPinSetFunc(FIOPAD_AE45, FPIN_FUNC6);
break;
case 11: /* gpio 4-a-11 */
FPinSetFunc(FIOPAD_AC45, FPIN_FUNC6);
break;
case 12: /* gpio 4-a-12 */
FPinSetFunc(FIOPAD_AE43, FPIN_FUNC6);
break;
case 13: /* gpio 4-a-13 */
FPinSetFunc(FIOPAD_AA43, FPIN_FUNC6);
break;
default:
break;
}
}
}
/**
* @name: FIOPadSetCanMux
* @msg: set iopad mux for can
* @return {*}
* @param {u32} can_id, instance id of can
*/
void FIOPadSetCanMux(u32 can_id)
{
if (can_id == FCAN0_ID)
{
/* can0 */
FPinSetFunc(FIOPAD_A37, FPIN_FUNC0); /* can0-tx: func 0 */
FPinSetFunc(FIOPAD_A39, FPIN_FUNC0); /* can0-rx: func 0 */
}
else if (can_id == FCAN1_ID)
{
/* can1 */
FPinSetFunc(FIOPAD_A41, FPIN_FUNC0); /* can1-tx: func 0 */
FPinSetFunc(FIOPAD_C41, FPIN_FUNC0); /* can1-rx: func 0 */
}
else
{
FIOPAD_ERROR("can id is error.\r\n");
}
}
/**
* @name: FIOPadSetQspiMux
* @msg: set iopad mux for qspi
* @return {*}
* @param {u32} qspi_id, id of qspi instance
* @param {u32} cs_id, id of qspi cs
*/
void FIOPadSetQspiMux(u32 qspi_id, u32 cs_id)
{
if (qspi_id == FQSPI0_ID)
{
/* add sck, io0-io3 iopad multiplex */
}
if (cs_id == FQSPI_CS_0)
{
FPinSetFunc(FIOPAD_AR51, FPIN_FUNC0);
}
else if (cs_id == FQSPI_CS_1)
{
FPinSetFunc(FIOPAD_AR45, FPIN_FUNC0);
}
else if (cs_id == FQSPI_CS_2)
{
FPinSetFunc(FIOPAD_C33, FPIN_FUNC5);
}
else if (cs_id == FQSPI_CS_3)
{
FPinSetFunc(FIOPAD_A33, FPIN_FUNC5);
}
else
{
FIOPAD_ERROR("can id is error.\r\n");
}
}
/**
* @name: FIOPadSetPwmMux
* @msg: set iopad mux for pwm
* @return {*}
* @param {u32} pwm_id, id of pwm instance
* @param {u32} pwm_channel, channel of pwm instance
*/
void FIOPadSetPwmMux(u32 pwm_id, u32 pwm_channel)
{
FASSERT(pwm_id < FPWM_NUM);
FASSERT(pwm_channel < FPWM_CHANNEL_NUM);
switch (pwm_id)
{
case FPWM0_ID:
if (pwm_channel == 0)
{
FPinSetFunc(FIOPAD_AL55, FPIN_FUNC1); /* PWM0_OUT: func 1 */
}
if (pwm_channel == 1)
{
FPinSetFunc(FIOPAD_AJ53, FPIN_FUNC1); /* PWM1_OUT: func 1 */
}
break;
case FPWM1_ID:
if (pwm_channel == 0)
{
FPinSetFunc(FIOPAD_AG53, FPIN_FUNC1); /* PWM2_OUT: func 1 */
}
if (pwm_channel == 1)
{
FPinSetFunc(FIOPAD_AC55, FPIN_FUNC1); /* PWM3_OUT: func 1 */
}
break;
case FPWM2_ID:
if (pwm_channel == 0)
{
FPinSetFunc(FIOPAD_BA51, FPIN_FUNC1); /* PWM4_OUT: func 1 */
}
if (pwm_channel == 1)
{
FPinSetFunc(FIOPAD_C35, FPIN_FUNC2); /* PWM5_OUT: func 2 */
}
break;
case FPWM3_ID:
if (pwm_channel == 0)
{
FPinSetFunc(FIOPAD_A33, FPIN_FUNC2); /* PWM6_OUT: func 2 */
}
if (pwm_channel == 1)
{
FPinSetFunc(FIOPAD_A39, FPIN_FUNC2); /* PWM7_OUT: func 2 */
}
break;
case FPWM4_ID:
if (pwm_channel == 0)
{
FPinSetFunc(FIOPAD_C41, FPIN_FUNC2); /* PWM8_OUT: func 2 */
}
if (pwm_channel == 1)
{
FPinSetFunc(FIOPAD_A45, FPIN_FUNC2); /* PWM9_OUT: func 2 */
}
break;
case FPWM5_ID:
if (pwm_channel == 0)
{
FPinSetFunc(FIOPAD_A47, FPIN_FUNC2); /* PWM10_OUT: func 2 */
}
if (pwm_channel == 1)
{
FPinSetFunc(FIOPAD_C29, FPIN_FUNC2); /* PWM11_OUT: func 2 */
}
break;
case FPWM6_ID:
if (pwm_channel == 0)
{
FPinSetFunc(FIOPAD_A27, FPIN_FUNC2); /* PWM12_OUT: func 2 */
}
if (pwm_channel == 1)
{
FPinSetFunc(FIOPAD_J35, FPIN_FUNC3); /* PWM13_OUT: func 3 */
}
break;
case FPWM7_ID:
if (pwm_channel == 0)
{
FPinSetFunc(FIOPAD_E39, FPIN_FUNC3); /* PWM14_OUT: func 3 */
}
if (pwm_channel == 1)
{
FPinSetFunc(FIOPAD_C39, FPIN_FUNC3); /* PWM15_OUT: func 3 */
}
break;
default:
FIOPAD_ERROR("pwm id is error.\r\n");
break;
}
}
/**
* @name: FIOPadSetAdcMux
* @msg: set iopad mux for adc
* @return {*}
* @param {u32} adc_id, id of adc instance
* @param {u32} adc_channel, id of adc channel
*/
void FIOPadSetAdcMux(u32 adc_id, u32 adc_channel)
{
if (adc_id == FADC0_ID)
{
switch (adc_channel)
{
case FADC_CHANNEL_0:
FPinSetFunc(FIOPAD_R47, FPIN_FUNC7); /* adc0-0: func 7 */
break;
case FADC_CHANNEL_1:
FPinSetFunc(FIOPAD_R45, FPIN_FUNC7); /* adc0-1: func 7 */
break;
case FADC_CHANNEL_2:
FPinSetFunc(FIOPAD_N47, FPIN_FUNC7); /* adc0-2: func 7 */
break;
case FADC_CHANNEL_3:
FPinSetFunc(FIOPAD_N51, FPIN_FUNC7); /* adc0-3: func 7 */
break;
case FADC_CHANNEL_4:
FPinSetFunc(FIOPAD_L51, FPIN_FUNC7); /* adc0-4: func 7 */
break;
case FADC_CHANNEL_5:
FPinSetFunc(FIOPAD_J51, FPIN_FUNC7); /* adc0-5: func 7 */
break;
case FADC_CHANNEL_6:
FPinSetFunc(FIOPAD_J41, FPIN_FUNC7); /* adc0-6: func 7 */
break;
case FADC_CHANNEL_7:
FPinSetFunc(FIOPAD_E43, FPIN_FUNC7); /* adc0-7: func 7 */
break;
default:
FIOPAD_ERROR("adc %d channel %d is error.\r\n", adc_id, adc_channel);
break;
}
}
else
{
FIOPAD_ERROR("adc %d channel %d is error.\r\n", adc_id, adc_channel);
}
}
/**
* @name: FIOPadSetMioMux
* @msg: set iopad mux for mio
* @return {*}
* @param {u32} mio_id, instance id of i2c
*/
void FIOPadSetMioMux(u32 mio_id)
{
switch (mio_id)
{
case FMIO0_ID:
{
FPinSetFunc(FIOPAD_A37, FPIN_FUNC5); /* scl */
FPinSetFunc(FIOPAD_A39, FPIN_FUNC5); /* sda */
}
break;
case FMIO1_ID:
{
FPinSetFunc(FIOPAD_A41, FPIN_FUNC5); /* scl */
FPinSetFunc(FIOPAD_C41, FPIN_FUNC5); /* sda */
}
break;
case FMIO2_ID:
{
FPinSetFunc(FIOPAD_A43, FPIN_FUNC5); /* scl */
FPinSetFunc(FIOPAD_A45, FPIN_FUNC5); /* sda */
}
break;
case FMIO3_ID:
{
FPinSetFunc(FIOPAD_BA51, FPIN_FUNC4); /* scl */
FPinSetFunc(FIOPAD_BA49, FPIN_FUNC4); /* sda */
}
break;
case FMIO4_ID:
{
FPinSetFunc(FIOPAD_R55, FPIN_FUNC4); /* scl */
FPinSetFunc(FIOPAD_U55, FPIN_FUNC4); /* sda */
}
break;
case FMIO5_ID:
{
FPinSetFunc(FIOPAD_W45, FPIN_FUNC4); /* scl */
FPinSetFunc(FIOPAD_U53, FPIN_FUNC4); /* sda */
}
break;
case FMIO6_ID:
{
FPinSetFunc(FIOPAD_AA53, FPIN_FUNC4); /* scl */
FPinSetFunc(FIOPAD_AA55, FPIN_FUNC4); /* sda */
}
break;
case FMIO7_ID:
{
FPinSetFunc(FIOPAD_A35, FPIN_FUNC4); /* scl */
FPinSetFunc(FIOPAD_C35, FPIN_FUNC4); /* sda */
}
break;
case FMIO8_ID:
{
FPinSetFunc(FIOPAD_AA45, FPIN_FUNC4); /* scl */
FPinSetFunc(FIOPAD_W45, FPIN_FUNC4); /* sda */
}
break;
case FMIO9_ID:
{
FPinSetFunc(FIOPAD_AA47, FPIN_FUNC4); /* scl */
FPinSetFunc(FIOPAD_U45, FPIN_FUNC4); /* sda */
}
break;
case FMIO10_ID:
{
FPinSetFunc(FIOPAD_C45, FPIN_FUNC5); /* scl */
FPinSetFunc(FIOPAD_A47, FPIN_FUNC5); /* sda */
}
break;
case FMIO11_ID:
{
FPinSetFunc(FIOPAD_N23, FPIN_FUNC3); /* scl */
FPinSetFunc(FIOPAD_L25, FPIN_FUNC3); /* sda */
}
break;
case FMIO12_ID:
{
FPinSetFunc(FIOPAD_E37, FPIN_FUNC3); /* scl */
FPinSetFunc(FIOPAD_L41, FPIN_FUNC3); /* sda */
}
break;
case FMIO13_ID:
{
FPinSetFunc(FIOPAD_J45, FPIN_FUNC6); /* scl */
FPinSetFunc(FIOPAD_N45, FPIN_FUNC6); /* sda */
}
break;
case FMIO14_ID:
{
FPinSetFunc(FIOPAD_L47, FPIN_FUNC6); /* scl */
FPinSetFunc(FIOPAD_L45, FPIN_FUNC6); /* sda */
}
break;
case FMIO15_ID:
{
FPinSetFunc(FIOPAD_N49, FPIN_FUNC6); /* scl */
FPinSetFunc(FIOPAD_J49, FPIN_FUNC6); /* sda */
}
break;
default:
break;
}
}
/**
* @name: FIOPadSetTachoMux
* @msg: set iopad mux for pwm_in
* @return {*}
* @param {u32} pwm_in_id, instance id of tacho
*/
void FIOPadSetTachoMux(u32 pwm_in_id)
{
switch (pwm_in_id)
{
case FTACHO0_ID:
FPinSetFunc(FIOPAD_AN53, FPIN_FUNC1);
break;
case FTACHO1_ID:
FPinSetFunc(FIOPAD_AJ55, FPIN_FUNC1);
break;
case FTACHO2_ID:
FPinSetFunc(FIOPAD_AG55, FPIN_FUNC1);
break;
case FTACHO3_ID:
FPinSetFunc(FIOPAD_AE55, FPIN_FUNC1);
break;
case FTACHO4_ID:
FPinSetFunc(FIOPAD_AC53, FPIN_FUNC1);
break;
case FTACHO5_ID:
FPinSetFunc(FIOPAD_BA49, FPIN_FUNC1);
break;
case FTACHO6_ID:
FPinSetFunc(FIOPAD_C33, FPIN_FUNC2);
break;
case FTACHO7_ID:
FPinSetFunc(FIOPAD_A37, FPIN_FUNC2);
break;
case FTACHO8_ID:
FPinSetFunc(FIOPAD_A41, FPIN_FUNC2);
break;
case FTACHO9_ID:
FPinSetFunc(FIOPAD_A43, FPIN_FUNC2);
break;
case FTACHO10_ID:
FPinSetFunc(FIOPAD_C45, FPIN_FUNC2);
break;
case FTACHO11_ID:
FPinSetFunc(FIOPAD_A29, FPIN_FUNC2);
break;
case FTACHO12_ID:
FPinSetFunc(FIOPAD_C27, FPIN_FUNC2);
break;
case FTACHO13_ID:
FPinSetFunc(FIOPAD_AA45, FPIN_FUNC2);
break;
case FTACHO14_ID:
FPinSetFunc(FIOPAD_AA47, FPIN_FUNC2);
break;
case FTACHO15_ID:
FPinSetFunc(FIOPAD_G55, FPIN_FUNC2);
break;
default:
break;
}
}
/**
* @name: FIOPadSetUartMux
* @msg: set iopad mux for uart
* @return {*}
* @param {u32} uart_id, instance id of uart
*/
void FIOPadSetUartMux(u32 uart_id)
{
switch (uart_id)
{
case FUART0_ID:
FPinSetFunc(FIOPAD_J33, FPIN_FUNC4);
FPinSetFunc(FIOPAD_J35, FPIN_FUNC4);
break;
case FUART1_ID:
FPinSetFunc(FIOPAD_AW47, FPIN_FUNC0);
FPinSetFunc(FIOPAD_AU47, FPIN_FUNC0);
break;
case FUART2_ID:
FPinSetFunc(FIOPAD_A43, FPIN_FUNC0);
FPinSetFunc(FIOPAD_A45, FPIN_FUNC0);
break;
case FUART3_ID:
FPinSetFunc(FIOPAD_L33, FPIN_FUNC2);
FPinSetFunc(FIOPAD_N31, FPIN_FUNC2);
break;
default:
break;
}
}

247
bsp/phytium/libraries/standalone/board/e2000/d/fparameters.h
View File

@ -35,17 +35,260 @@ extern "C"
/************************** Constant Definitions *****************************/
#define CORE0_AFF 0x200U
#define CORE1_AFF 0x201U
#define FCORE_NUM 2
#define FT_CPUS_NR 2U
/* GIC offset */
#define FT_GIC_REDISTRUBUTIOR_OFFSET 2
/*****************************************************************************/
/* register offset of iopad function / pull / driver strength */
#define FIOPAD_AN55_REG0_OFFSET 0x0000U
#define FIOPAD_AW43_REG0_OFFSET 0x0004U
#define FIOPAD_AR51_REG0_OFFSET 0x0020U
#define FIOPAD_AJ51_REG0_OFFSET 0x0024U
#define FIOPAD_AL51_REG0_OFFSET 0x0028U
#define FIOPAD_AL49_REG0_OFFSET 0x002CU
#define FIOPAD_AN47_REG0_OFFSET 0x0030U
#define FIOPAD_AR47_REG0_OFFSET 0x0034U
#define FIOPAD_BA53_REG0_OFFSET 0x0038U
#define FIOPAD_BA55_REG0_OFFSET 0x003CU
#define FIOPAD_AW53_REG0_OFFSET 0x0040U
#define FIOPAD_AW55_REG0_OFFSET 0x0044U
#define FIOPAD_AU51_REG0_OFFSET 0x0048U
#define FIOPAD_AN53_REG0_OFFSET 0x004CU
#define FIOPAD_AL55_REG0_OFFSET 0x0050U
#define FIOPAD_AJ55_REG0_OFFSET 0x0054U
#define FIOPAD_AJ53_REG0_OFFSET 0x0058U
#define FIOPAD_AG55_REG0_OFFSET 0x005CU
#define FIOPAD_AG53_REG0_OFFSET 0x0060U
#define FIOPAD_AE55_REG0_OFFSET 0x0064U
#define FIOPAD_AC55_REG0_OFFSET 0x0068U
#define FIOPAD_AC53_REG0_OFFSET 0x006CU
#define FIOPAD_AR45_REG0_OFFSET 0x0070U
#define FIOPAD_BA51_REG0_OFFSET 0x0074U
#define FIOPAD_BA49_REG0_OFFSET 0x0078U
#define FIOPAD_AR55_REG0_OFFSET 0x007CU
#define FIOPAD_AU55_REG0_OFFSET 0x0080U
#define FIOPAD_AR53_REG0_OFFSET 0x0084U
#define FIOPAD_BA45_REG0_OFFSET 0x0088U
#define FIOPAD_AW51_REG0_OFFSET 0x008CU
#define FIOPAD_A31_REG0_OFFSET 0x0090U
#define FIOPAD_R53_REG0_OFFSET 0x0094U
#define FIOPAD_R55_REG0_OFFSET 0x0098U
#define FIOPAD_U55_REG0_OFFSET 0x009CU
#define FIOPAD_W55_REG0_OFFSET 0x00A0U
#define FIOPAD_U53_REG0_OFFSET 0x00A4U
#define FIOPAD_AA53_REG0_OFFSET 0x00A8U
#define FIOPAD_AA55_REG0_OFFSET 0x00ACU
#define FIOPAD_AW47_REG0_OFFSET 0x00B0U
#define FIOPAD_AU47_REG0_OFFSET 0x00B4U
#define FIOPAD_A35_REG0_OFFSET 0x00B8U
#define FIOPAD_C35_REG0_OFFSET 0x00BCU
#define FIOPAD_C33_REG0_OFFSET 0x00C0U
#define FIOPAD_A33_REG0_OFFSET 0x00C4U
#define FIOPAD_A37_REG0_OFFSET 0x00C8U
#define FIOPAD_A39_REG0_OFFSET 0x00CCU
#define FIOPAD_A41_REG0_OFFSET 0x00D0U
#define FIOPAD_C41_REG0_OFFSET 0x00D4U
#define FIOPAD_A43_REG0_OFFSET 0x00D8U
#define FIOPAD_A45_REG0_OFFSET 0x00DCU
#define FIOPAD_C45_REG0_OFFSET 0x00E0U
#define FIOPAD_A47_REG0_OFFSET 0x00E4U
#define FIOPAD_A29_REG0_OFFSET 0x00E8U
#define FIOPAD_C29_REG0_OFFSET 0x00ECU
#define FIOPAD_C27_REG0_OFFSET 0x00F0U
#define FIOPAD_A27_REG0_OFFSET 0x00F4U
#define FIOPAD_AJ49_REG0_OFFSET 0x00F8U
#define FIOPAD_AL45_REG0_OFFSET 0x00FCU
#define FIOPAD_AL43_REG0_OFFSET 0x0100U
#define FIOPAD_AN45_REG0_OFFSET 0x0104U
#define FIOPAD_AG47_REG0_OFFSET 0x0108U
#define FIOPAD_AJ47_REG0_OFFSET 0x010CU
#define FIOPAD_AG45_REG0_OFFSET 0x0110U
#define FIOPAD_AE51_REG0_OFFSET 0x0114U
#define FIOPAD_AE49_REG0_OFFSET 0x0118U
#define FIOPAD_AG51_REG0_OFFSET 0x011CU
#define FIOPAD_AJ45_REG0_OFFSET 0x0120U
#define FIOPAD_AC51_REG0_OFFSET 0x0124U
#define FIOPAD_AC49_REG0_OFFSET 0x0128U
#define FIOPAD_AE47_REG0_OFFSET 0x012CU
#define FIOPAD_W47_REG0_OFFSET 0x0130U
#define FIOPAD_W51_REG0_OFFSET 0x0134U
#define FIOPAD_W49_REG0_OFFSET 0x0138U
#define FIOPAD_U51_REG0_OFFSET 0x013CU
#define FIOPAD_U49_REG0_OFFSET 0x0140U
#define FIOPAD_AE45_REG0_OFFSET 0x0144U
#define FIOPAD_AC45_REG0_OFFSET 0x0148U
#define FIOPAD_AE43_REG0_OFFSET 0x014CU
#define FIOPAD_AA43_REG0_OFFSET 0x0150U
#define FIOPAD_AA45_REG0_OFFSET 0x0154U
#define FIOPAD_W45_REG0_OFFSET 0x0158U
#define FIOPAD_AA47_REG0_OFFSET 0x015CU
#define FIOPAD_U45_REG0_OFFSET 0x0160U
#define FIOPAD_G55_REG0_OFFSET 0x0164U
#define FIOPAD_J55_REG0_OFFSET 0x0168U
#define FIOPAD_L53_REG0_OFFSET 0x016CU
#define FIOPAD_C55_REG0_OFFSET 0x0170U
#define FIOPAD_E55_REG0_OFFSET 0x0174U
#define FIOPAD_J53_REG0_OFFSET 0x0178U
#define FIOPAD_L55_REG0_OFFSET 0x017CU
#define FIOPAD_N55_REG0_OFFSET 0x0180U
#define FIOPAD_C53_REG0_OFFSET 0x0184U
#define FIOPAD_E53_REG0_OFFSET 0x0188U
#define FIOPAD_E27_REG0_OFFSET 0x018CU
#define FIOPAD_G27_REG0_OFFSET 0x0190U
#define FIOPAD_N37_REG0_OFFSET 0x0194U
#define FIOPAD_N35_REG0_OFFSET 0x0198U
#define FIOPAD_J29_REG0_OFFSET 0x019CU
#define FIOPAD_N29_REG0_OFFSET 0x01A0U
#define FIOPAD_L29_REG0_OFFSET 0x01A4U
#define FIOPAD_N41_REG0_OFFSET 0x01A8U
#define FIOPAD_N39_REG0_OFFSET 0x01ACU
#define FIOPAD_L27_REG0_OFFSET 0x01B0U
#define FIOPAD_J27_REG0_OFFSET 0x01B4U
#define FIOPAD_J25_REG0_OFFSET 0x01B8U
#define FIOPAD_E25_REG0_OFFSET 0x01BCU
#define FIOPAD_G25_REG0_OFFSET 0x01C0U
#define FIOPAD_N23_REG0_OFFSET 0x01C4U
#define FIOPAD_L25_REG0_OFFSET 0x01C8U
#define FIOPAD_J33_REG0_OFFSET 0x01CCU
#define FIOPAD_J35_REG0_OFFSET 0x01D0U
#define FIOPAD_G37_REG0_OFFSET 0x01D4U
#define FIOPAD_E39_REG0_OFFSET 0x01D8U
#define FIOPAD_L39_REG0_OFFSET 0x01DCU
#define FIOPAD_C39_REG0_OFFSET 0x01E0U
#define FIOPAD_E37_REG0_OFFSET 0x01E4U
#define FIOPAD_L41_REG0_OFFSET 0x01E8U
#define FIOPAD_J39_REG0_OFFSET 0x01ECU
#define FIOPAD_J37_REG0_OFFSET 0x01F0U
#define FIOPAD_L35_REG0_OFFSET 0x01F4U
#define FIOPAD_E33_REG0_OFFSET 0x01F8U
#define FIOPAD_E31_REG0_OFFSET 0x01FCU
#define FIOPAD_G31_REG0_OFFSET 0x0200U
#define FIOPAD_J31_REG0_OFFSET 0x0204U
#define FIOPAD_L33_REG0_OFFSET 0x0208U
#define FIOPAD_N31_REG0_OFFSET 0x020CU
#define FIOPAD_R47_REG0_OFFSET 0x0210U
#define FIOPAD_R45_REG0_OFFSET 0x0214U
#define FIOPAD_N47_REG0_OFFSET 0x0218U
#define FIOPAD_N51_REG0_OFFSET 0x021CU
#define FIOPAD_L51_REG0_OFFSET 0x0220U
#define FIOPAD_J51_REG0_OFFSET 0x0224U
#define FIOPAD_J41_REG0_OFFSET 0x0228U
#define FIOPAD_E43_REG0_OFFSET 0x022CU
#define FIOPAD_G43_REG0_OFFSET 0x0230U
#define FIOPAD_J43_REG0_OFFSET 0x0234U
#define FIOPAD_J45_REG0_OFFSET 0x0238U
#define FIOPAD_N45_REG0_OFFSET 0x023CU
#define FIOPAD_L47_REG0_OFFSET 0x0240U
#define FIOPAD_L45_REG0_OFFSET 0x0244U
#define FIOPAD_N49_REG0_OFFSET 0x0248U
#define FIOPAD_J49_REG0_OFFSET 0x024CU
#define FIOPAD_REG0_BEG_OFFSET FIOPAD_AN55_REG0_OFFSET
#define FIOPAD_REG0_END_OFFSET FIOPAD_J49_REG0_OFFSET
/* register offset of iopad delay */
#define FIOPAD_AJ51_REG1_OFFSET 0x1024U
#define FIOPAD_AL51_REG1_OFFSET 0x1028U
#define FIOPAD_AL49_REG1_OFFSET 0x102CU
#define FIOPAD_AN47_REG1_OFFSET 0x1030U
#define FIOPAD_AR47_REG1_OFFSET 0x1034U
#define FIOPAD_AJ53_REG1_OFFSET 0x1058U
#define FIOPAD_AG55_REG1_OFFSET 0x105CU
#define FIOPAD_AG53_REG1_OFFSET 0x1060U
#define FIOPAD_AE55_REG1_OFFSET 0x1064U
#define FIOPAD_BA51_REG1_OFFSET 0x1074U
#define FIOPAD_BA49_REG1_OFFSET 0x1078U
#define FIOPAD_AR55_REG1_OFFSET 0x107CU
#define FIOPAD_AU55_REG1_OFFSET 0x1080U
#define FIOPAD_A41_REG1_OFFSET 0x10D0U
#define FIOPAD_C41_REG1_OFFSET 0x10D4U
#define FIOPAD_A43_REG1_OFFSET 0x10D8U
#define FIOPAD_A45_REG1_OFFSET 0x10DCU
#define FIOPAD_C45_REG1_OFFSET 0x10E0U
#define FIOPAD_A47_REG1_OFFSET 0x10E4U
#define FIOPAD_A29_REG1_OFFSET 0x10E8U
#define FIOPAD_C29_REG1_OFFSET 0x10ECU
#define FIOPAD_C27_REG1_OFFSET 0x10F0U
#define FIOPAD_A27_REG1_OFFSET 0x10F4U
#define FIOPAD_AJ49_REG1_OFFSET 0x10F8U
#define FIOPAD_AL45_REG1_OFFSET 0x10FCU
#define FIOPAD_AL43_REG1_OFFSET 0x1100U
#define FIOPAD_AN45_REG1_OFFSET 0x1104U
#define FIOPAD_AG47_REG1_OFFSET 0x1108U
#define FIOPAD_AJ47_REG1_OFFSET 0x110CU
#define FIOPAD_AG45_REG1_OFFSET 0x1110U
#define FIOPAD_AE51_REG1_OFFSET 0x1114U
#define FIOPAD_AE49_REG1_OFFSET 0x1118U
#define FIOPAD_AG51_REG1_OFFSET 0x111CU
#define FIOPAD_AJ45_REG1_OFFSET 0x1120U
#define FIOPAD_AC51_REG1_OFFSET 0x1124U
#define FIOPAD_AC49_REG1_OFFSET 0x1128U
#define FIOPAD_AE47_REG1_OFFSET 0x112CU
#define FIOPAD_W47_REG1_OFFSET 0x1130U
#define FIOPAD_W49_REG1_OFFSET 0x1138U
#define FIOPAD_U51_REG1_OFFSET 0x113CU
#define FIOPAD_U49_REG1_OFFSET 0x1140U
#define FIOPAD_AE45_REG1_OFFSET 0x1144U
#define FIOPAD_AC45_REG1_OFFSET 0x1148U
#define FIOPAD_AE43_REG1_OFFSET 0x114CU
#define FIOPAD_AA43_REG1_OFFSET 0x1150U
#define FIOPAD_AA45_REG1_OFFSET 0x1154U
#define FIOPAD_W45_REG1_OFFSET 0x1158U
#define FIOPAD_AA47_REG1_OFFSET 0x115CU
#define FIOPAD_U45_REG1_OFFSET 0x1160U
#define FIOPAD_J55_REG1_OFFSET 0x1168U
#define FIOPAD_L53_REG1_OFFSET 0x116CU
#define FIOPAD_C55_REG1_OFFSET 0x1170U
#define FIOPAD_E55_REG1_OFFSET 0x1174U
#define FIOPAD_J53_REG1_OFFSET 0x1178U
#define FIOPAD_L55_REG1_OFFSET 0x117CU
#define FIOPAD_N55_REG1_OFFSET 0x1180U
#define FIOPAD_E27_REG1_OFFSET 0x118CU
#define FIOPAD_G27_REG1_OFFSET 0x1190U
#define FIOPAD_N37_REG1_OFFSET 0x1194U
#define FIOPAD_N35_REG1_OFFSET 0x1198U
#define FIOPAD_J29_REG1_OFFSET 0x119CU
#define FIOPAD_N29_REG1_OFFSET 0x11A0U
#define FIOPAD_L29_REG1_OFFSET 0x11A4U
#define FIOPAD_N41_REG1_OFFSET 0x11A8U
#define FIOPAD_N39_REG1_OFFSET 0x11ACU
#define FIOPAD_L27_REG1_OFFSET 0x11B0U
#define FIOPAD_J27_REG1_OFFSET 0x11B4U
#define FIOPAD_J25_REG1_OFFSET 0x11B8U
#define FIOPAD_E25_REG1_OFFSET 0x11BCU
#define FIOPAD_G25_REG1_OFFSET 0x11C0U
#define FIOPAD_J33_REG1_OFFSET 0x11CCU
#define FIOPAD_J35_REG1_OFFSET 0x11D0U
#define FIOPAD_G37_REG1_OFFSET 0x11D4U
#define FIOPAD_E39_REG1_OFFSET 0x11D8U
#define FIOPAD_L39_REG1_OFFSET 0x11DCU
#define FIOPAD_C39_REG1_OFFSET 0x11E0U
#define FIOPAD_E37_REG1_OFFSET 0x11E4U
#define FIOPAD_L41_REG1_OFFSET 0x11E8U
#define FIOPAD_J39_REG1_OFFSET 0x11ECU
#define FIOPAD_J37_REG1_OFFSET 0x11F0U
#define FIOPAD_L35_REG1_OFFSET 0x11F4U
#define FIOPAD_E33_REG1_OFFSET 0x11F8U
#define FIOPAD_E31_REG1_OFFSET 0x11FCU
#define FIOPAD_G31_REG1_OFFSET 0x1200U
#define FIOPAD_L51_REG1_OFFSET 0x1220U
#define FIOPAD_J51_REG1_OFFSET 0x1224U
#define FIOPAD_J41_REG1_OFFSET 0x1228U
#define FIOPAD_E43_REG1_OFFSET 0x122CU
#define FIOPAD_G43_REG1_OFFSET 0x1230U
#define FIOPAD_J43_REG1_OFFSET 0x1234U
#define FIOPAD_J45_REG1_OFFSET 0x1238U
#define FIOPAD_N45_REG1_OFFSET 0x123CU
#define FIOPAD_L47_REG1_OFFSET 0x1240U
#define FIOPAD_L45_REG1_OFFSET 0x1244U
#define FIOPAD_N49_REG1_OFFSET 0x1248U
#define FIOPAD_J49_REG1_OFFSET 0x124CU
#define FIOPAD_REG1_BEG_OFFSET FIOPAD_AJ51_REG1_OFFSET
#define FIOPAD_REG1_END_OFFSET FIOPAD_J49_REG1_OFFSET
#ifdef __cplusplus
}

588
bsp/phytium/libraries/standalone/board/e2000/fiopad_comm.c
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@ -1,588 +0,0 @@
/*
* Copyright : (C) 2022 Phytium Information Technology, Inc.
* All Rights Reserved.
*
* This program is OPEN SOURCE software: you can redistribute it and/or modify it
* under the terms of the Phytium Public License as published by the Phytium Technology Co.,Ltd,
* either version 1.0 of the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,but WITHOUT ANY WARRANTY;
* without even the implied warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.
* See the Phytium Public License for more details.
*
*
* FilePath: fiopad_comm.c
* Date: 2022-02-10 14:53:42
* LastEditTime: 2022-02-18 08:25:29
* Description:  This file is for io-pad function definition
*
* Modify History:
* Ver   Who        Date         Changes
* ----- ------     --------    --------------------------------------
* 1.0 huanghe 2021/11/5 init commit
* 1.1 zhugengyu 2022/3/21 adopt to lastest tech spec.
*/
/***************************** Include Files *********************************/
#include "fparameters.h"
#include "fio.h"
#include "fkernel.h"
#include "fassert.h"
#include "fdebug.h"
#include "stdio.h"
#include "fpinctrl.h"
/************************** Constant Definitions *****************************/
/** @name IO PAD Control Register
*/
#define FIOPAD_X_REG0_BEG_OFFSET 0x0 /* 上下拉/驱动能力/复用功能配置 */
#define FIOPAD_X_REG0_END_OFFSET 0x24c
#define FIOPAD_X_REG1_BEG_OFFSET 0x1024 /* 输入/输出延时配置 */
#define FIOPAD_X_REG1_END_OFFSET 0x124c
/** @name X_reg0 Register
*/
#define FIOPAD_X_REG0_PULL_MASK GENMASK(9, 8) /* 上下拉配置 */
#define FIOPAD_X_REG0_PULL_GET(x) GET_REG32_BITS((x), 9, 8)
#define FIOPAD_X_REG0_PULL_SET(x) SET_REG32_BITS((x), 9, 8)
#define FIOPAD_X_REG0_DRIVE_MASK GENMASK(7, 4) /* 驱动能力配置 */
#define FIOPAD_X_REG0_DRIVE_GET(x) GET_REG32_BITS((x), 7, 4)
#define FIOPAD_X_REG0_DRIVE_SET(x) SET_REG32_BITS((x), 7, 4)
#define FIOPAD_X_REG0_FUNC_MASK GENMASK(2, 0) /* 引脚复用配置 */
#define FIOPAD_X_REG0_FUNC_GET(x) GET_REG32_BITS((x), 2, 0)
#define FIOPAD_X_REG0_FUNC_SET(x) SET_REG32_BITS((x), 2, 0)
/** @name X_reg1 Register
*/
#define FIOPAD_X_REG1_OUT_DELAY_EN BIT(8)
#define FIOPAD_X_REG1_OUT_DELAY_DELICATE_MASK GENMASK(11, 9)
#define FIOPAD_X_REG1_OUT_DELAY_DELICATE_GET(x) GET_REG32_BITS((x), 11, 9) /* 延时精调 */
#define FIOPAD_X_REG1_OUT_DELAY_DELICATE_SET(x) SET_REG32_BITS((x), 11, 9)
#define FIOPAD_X_REG1_OUT_DELAY_ROUGH_MASK GENMASK(14, 12)
#define FIOPAD_X_REG1_OUT_DELAY_ROUGH_GET(x) GET_REG32_BITS((x), 14, 12) /* 延时粗调 */
#define FIOPAD_X_REG1_OUT_DELAY_ROUGH_SET(x) SET_REG32_BITS((x), 14, 12)
#define FIOPAD_X_REG1_IN_DELAY_EN BIT(0)
#define FIOPAD_X_REG1_IN_DELAY_DELICATE_MASK GENMASK(3, 1)
#define FIOPAD_X_REG1_IN_DELAY_DELICATE_GET(x) GET_REG32_BITS((x), 3, 1) /* 延时精调 */
#define FIOPAD_X_REG1_IN_DELAY_DELICATE_SET(x) SET_REG32_BITS((x), 3, 1)
#define FIOPAD_X_REG1_IN_DELAY_ROUGH_MASK GENMASK(6, 4)
#define FIOPAD_X_REG1_IN_DELAY_ROUGH_GET(x) GET_REG32_BITS((x), 6, 4) /* 延时粗调 */
#define FIOPAD_X_REG1_IN_DELAY_ROUGH_SET(x) SET_REG32_BITS((x), 6, 4)
#define FIOPAD_DELAY_MAX 15
/**************************** Type Definitions *******************************/
/***************** Macros (Inline Functions) Definitions *********************/
static inline u32 FIOPadRead(FPinIndex pin)
{
return FtIn32(FIOPAD_BASE_ADDR + pin.reg_off);
}
static inline void FIOPadWrite(FPinIndex pin, u32 reg_val)
{
FtOut32(FIOPAD_BASE_ADDR + pin.reg_off, reg_val);
return;
}
#define FIOPAD_ASSERT_REG0_OFF(pin) FASSERT_MSG((FIOPAD_X_REG0_END_OFFSET >= pin.reg_off), "invalid reg0 offset @0x%x\r\n", (pin.reg_off))
#define FIOPAD_ASSERT_FUNC(func) FASSERT_MSG((func < FPIN_NUM_OF_FUNC), "invalid func as %d\r\n", (func))
#define FIOPAD_ASSERT_PULL(pull) FASSERT_MSG((pull < FPIN_NUM_OF_PULL), "invalid pull as %d\r\n", (pull))
#define FIOPAD_ASSERT_DRIVE(drive) FASSERT_MSG((drive < FPIN_NUM_OF_DRIVE), "invalid pull as %d\r\n", (drive))
#define FIOPAD_ASSERT_REG1_OFF(pin) FASSERT_MSG(((FIOPAD_X_REG1_BEG_OFFSET <= pin.reg_off) && (FIOPAD_X_REG1_END_OFFSET >= pin.reg_off)), "invalid reg1 offset @0x%x\r\n", (pin.reg_off))
#define FIOPAD_ASSERT_DELAY(delay) FASSERT_MSG((delay < FPIN_NUM_OF_DELAY), "invalid delay as %d\r\n", (delay))
#define FIOPAD_DEBUG_TAG "FIOPAD"
#define FIOPAD_ERROR(format, ...) FT_DEBUG_PRINT_E(FIOPAD_DEBUG_TAG, format, ##__VA_ARGS__)
#define FIOPAD_WARN(format, ...) FT_DEBUG_PRINT_W(FIOPAD_DEBUG_TAG, format, ##__VA_ARGS__)
#define FIOPAD_INFO(format, ...) FT_DEBUG_PRINT_I(FIOPAD_DEBUG_TAG, format, ##__VA_ARGS__)
#define FIOPAD_DEBUG(format, ...) FT_DEBUG_PRINT_D(FIOPAD_DEBUG_TAG, format, ##__VA_ARGS__)
/************************** Function Prototypes ******************************/
/**
* @name: FPinGetFunc
* @msg: 获取IO引脚当前的复用功能
* @return {FPinFunc} 当前的复用功能
* @param {FPinIndex} pin IO引脚索引
* @note 参考编程手册，使用 FIOPAD_INDEX 宏定义index的值
*/
FPinFunc FPinGetFunc(const FPinIndex pin)
{
FIOPAD_ASSERT_REG0_OFF(pin);
u32 func = FIOPAD_X_REG0_FUNC_GET(FIOPadRead(pin));
FIOPAD_ASSERT_FUNC(func);
return (FPinFunc)func;
}
/**
* @name: FPinSetFunc
* @msg: 设置IO引脚复用功能
* @return {*}
* @param {FPinIndex} pin IO引脚索引
* @param {FPinFunc} func IO复用功能
* @note 参考编程手册，使用 FIOPAD_INDEX 宏定义index的值
*/
void FPinSetFunc(const FPinIndex pin, FPinFunc func)
{
FIOPAD_ASSERT_REG0_OFF(pin);
FIOPAD_ASSERT_FUNC(func);
u32 reg_val = FIOPadRead(pin);
u32 test_val = 0;
reg_val &= ~FIOPAD_X_REG0_FUNC_MASK;
reg_val |= FIOPAD_X_REG0_FUNC_SET(func);
FIOPadWrite(pin, reg_val);
test_val = FIOPadRead(pin);
if (reg_val != test_val)
{
FIOPAD_ERROR("ERROR: FIOPad write is failed ,pin is %x\n, 0x%x != 0x%x",
pin.reg_off, reg_val, test_val);
}
return;
}
/**
* @name: FPinGetDrive
* @msg: 获取IO引脚的驱动能力
* @return {FPinDrive} 引脚的当前的驱动能力
* @param {FPinIndex} pin IO引脚索引
*/
FPinDrive FPinGetDrive(const FPinIndex pin)
{
FIOPAD_ASSERT_REG0_OFF(pin);
u32 drive = FIOPAD_X_REG0_DRIVE_GET(FIOPadRead(pin));
FIOPAD_ASSERT_DRIVE(drive);
return (FPinDrive)drive;
}
/**
* @name: FPinSetDrive
* @msg: 设置IO引脚的驱动能力
* @return {*}
* @param {FPinIndex} pin, IO引脚索引
* @param {FPinDrive} drive, 引脚驱动能力设置
*/
void FPinSetDrive(const FPinIndex pin, FPinDrive drive)
{
FIOPAD_ASSERT_REG0_OFF(pin);
FIOPAD_ASSERT_DRIVE(drive);
u32 reg_val = FIOPadRead(pin);
reg_val &= ~FIOPAD_X_REG0_DRIVE_MASK;
reg_val |= FIOPAD_X_REG0_DRIVE_SET(drive);
FIOPadWrite(pin, reg_val);
return;
}
void FPinGetConfig(const FPinIndex pin, FPinFunc *func, FPinPull *pull, FPinDrive *drive)
{
FIOPAD_ASSERT_REG0_OFF(pin);
u32 reg_val = FIOPadRead(pin);
if (func)
{
*func = FIOPAD_X_REG0_FUNC_GET(reg_val);
}
if (pull)
{
*pull = FIOPAD_X_REG0_PULL_GET(reg_val);
}
if (drive)
{
*drive = FIOPAD_X_REG0_DRIVE_GET(reg_val);
}
return;
}
void FPinSetConfig(const FPinIndex pin, FPinFunc func, FPinPull pull, FPinDrive drive)
{
FIOPAD_ASSERT_REG0_OFF(pin);
u32 reg_val = FIOPadRead(pin);
reg_val &= ~FIOPAD_X_REG0_FUNC_MASK;
reg_val |= FIOPAD_X_REG0_FUNC_SET(func);
reg_val &= ~FIOPAD_X_REG0_PULL_MASK;
reg_val |= FIOPAD_X_REG0_PULL_SET(pull);
reg_val &= ~FIOPAD_X_REG0_DRIVE_MASK;
reg_val |= FIOPAD_X_REG0_DRIVE_SET(drive);
FIOPadWrite(pin, reg_val);
return;
}
/**
* @name: FPinGetPull
* @msg: 获取IO引脚当前的上下拉设置
* @return {*}
* @param {FPinIndex} pin IO引脚索引
* @note 参考编程手册，使用 FIOPAD_INDEX 宏定义index的值
*/
FPinPull FPinGetPull(const FPinIndex pin)
{
FIOPAD_ASSERT_REG0_OFF(pin);
u32 pull = FIOPAD_X_REG0_PULL_GET(FIOPadRead(pin));
FIOPAD_ASSERT_PULL(pull);
return (FPinPull)pull;
}
/**
* @name: FPinSetPull
* @msg: 设置IO引脚当前的上下拉
* @return {*}
* @param {FPinIndex} pin IO引脚索引
* @param {FPinPull} pull 上下拉设置
*/
void FPinSetPull(const FPinIndex pin, FPinPull pull)
{
FIOPAD_ASSERT_REG0_OFF(pin);
FIOPAD_ASSERT_PULL(pull);
u32 reg_val = FIOPadRead(pin);
reg_val &= ~FIOPAD_X_REG0_PULL_MASK;
reg_val |= FIOPAD_X_REG0_PULL_SET(pull);
FIOPadWrite(pin, reg_val);
return;
}
/**
* @name: FPinGetDelay
* @msg: 获取IO引脚当前的延时设置
* @return {FPinDelay} 当前的延时设置
* @param {FPinIndex} pin IO引脚延时设置索引
* @param {FPinDelayDir} dir 输入/输出延时
* @param {FPinDelayType} type 精调/粗调延时
*/
FPinDelay FPinGetDelay(const FPinIndex pin, FPinDelayDir dir, FPinDelayType type)
{
FIOPAD_ASSERT_REG1_OFF(pin);
const u32 reg_val = FIOPadRead(pin);
u8 delay = 0;
if (FPIN_OUTPUT_DELAY == dir)
{
if (FPIN_DELAY_FINE_TUNING == type)
{
delay = FIOPAD_X_REG1_OUT_DELAY_DELICATE_GET(reg_val);
}
else if (FPIN_DELAY_COARSE_TUNING == type)
{
delay = FIOPAD_X_REG1_OUT_DELAY_ROUGH_GET(reg_val);
}
else
{
FASSERT(0);
}
}
else if (FPIN_INPUT_DELAY == dir)
{
if (FPIN_DELAY_FINE_TUNING == type)
{
delay = FIOPAD_X_REG1_IN_DELAY_DELICATE_GET(reg_val);
}
else if (FPIN_DELAY_COARSE_TUNING == type)
{
delay = FIOPAD_X_REG1_IN_DELAY_ROUGH_GET(reg_val);
}
else
{
FASSERT(0);
}
}
else
{
FASSERT(0);
}
FIOPAD_ASSERT_DELAY(delay);
return (FPinDelay)delay;
}
/**
* @name: FPinGetDelayEn
* @msg: 获取IO引脚当前的延时使能标志位
* @return {*}
* @param {FPinIndex} pin IO引脚延时设置索引
* @param {FPinDelayDir} dir 输入/输出延时
*/
boolean FPinGetDelayEn(const FPinIndex pin, FPinDelayDir dir)
{
FIOPAD_ASSERT_REG1_OFF(pin);
const u32 reg_val = FIOPadRead(pin);
boolean enabled = FALSE;
if (FPIN_OUTPUT_DELAY == dir)
{
if (FIOPAD_X_REG1_OUT_DELAY_EN & reg_val)
{
enabled = TRUE;
}
else
{
enabled = FALSE;
}
}
else if (FPIN_INPUT_DELAY == dir)
{
if (FIOPAD_X_REG1_IN_DELAY_EN & reg_val)
{
enabled = TRUE;
}
else
{
enabled = FALSE;
}
}
else
{
FASSERT(0);
}
return enabled;
}
/**
* @name: FPinSetDelay
* @msg: 设置IO引脚延时
* @return {*}
* @param {FPinIndex} pin IO引脚延时设置索引
* @param {FPinDelayDir} dir 输入/输出延时
* @param {FPinDelayType} type 精调/粗调延时
* @param {FPinDelay} delay 延时设置
*/
void FPinSetDelay(const FPinIndex pin, FPinDelayDir dir, FPinDelayType type, FPinDelay delay)
{
FIOPAD_ASSERT_REG1_OFF(pin);
FIOPAD_ASSERT_DELAY(delay);
u32 reg_val = FIOPadRead(pin);
if (FPIN_OUTPUT_DELAY == dir)
{
if (FPIN_DELAY_FINE_TUNING == type)
{
reg_val &= ~FIOPAD_X_REG1_OUT_DELAY_DELICATE_MASK;
reg_val |= FIOPAD_X_REG1_OUT_DELAY_DELICATE_SET(delay);
}
else if (FPIN_DELAY_COARSE_TUNING == type)
{
reg_val &= ~FIOPAD_X_REG1_OUT_DELAY_ROUGH_MASK;
reg_val |= FIOPAD_X_REG1_OUT_DELAY_ROUGH_SET(delay);
}
else
{
FASSERT(0);
}
}
else if (FPIN_INPUT_DELAY == dir)
{
if (FPIN_DELAY_FINE_TUNING == type)
{
reg_val &= ~FIOPAD_X_REG1_IN_DELAY_DELICATE_MASK;
reg_val |= FIOPAD_X_REG1_IN_DELAY_DELICATE_SET(delay);
}
else if (FPIN_DELAY_COARSE_TUNING == type)
{
reg_val &= ~FIOPAD_X_REG1_IN_DELAY_ROUGH_MASK;
reg_val |= FIOPAD_X_REG1_IN_DELAY_ROUGH_SET(delay);
}
else
{
FASSERT(0);
}
}
else
{
FASSERT(0);
}
FIOPadWrite(pin, reg_val);
return;
}
/**
* @name: FPinSetDelayEn
* @msg: 使能/去使能IO引脚延时
* @return {*}
* @param {FPinIndex} pin IO引脚延时设置索引
* @param {FPinDelayDir} dir 输入/输出延时
* @param {boolean} enable TRUE: 使能, FALSE: 去使能
*/
void FPinSetDelayEn(const FPinIndex pin, FPinDelayDir dir, boolean enable)
{
FIOPAD_ASSERT_REG1_OFF(pin);
u32 reg_val = FIOPadRead(pin);
if (FPIN_OUTPUT_DELAY == dir)
{
if (enable)
{
reg_val |= FIOPAD_X_REG1_OUT_DELAY_EN;
}
else
{
reg_val &= ~FIOPAD_X_REG1_OUT_DELAY_EN;
}
}
else if (FPIN_INPUT_DELAY == dir)
{
if (enable)
{
reg_val |= FIOPAD_X_REG1_IN_DELAY_EN;
}
else
{
reg_val &= ~FIOPAD_X_REG1_IN_DELAY_EN;
}
}
else
{
FASSERT(0);
}
FIOPadWrite(pin, reg_val);
return;
}
/**
* @name: FPinSetDelayConfig
* @msg: Update and enable common IO pin delay config
* @return {NONE}
* @param {FPinIndex} pin, IO pin index
* @param {FPinDelayIOType} in_out_type, Select the input and output types ，
* @param {FPinDelay} roungh_delay, delay rough setting
* @param {FPinDelay} delicate_delay, delay delicate setting
* @param {boolean} enable, enable delay
*/
void FPinSetDelayConfig(const FPinIndex pin, FPinDelayIOType in_out_type, FPinDelay roungh_delay, FPinDelay delicate_delay, boolean enable)
{
FIOPAD_ASSERT_REG1_OFF(pin);
u32 reg_val = FIOPadRead(pin);
if (in_out_type == FPIN_DELAY_IN_TYPE)
{
reg_val = FIOPadRead(pin);
/* update delicate input delay */
reg_val &= ~FIOPAD_X_REG1_IN_DELAY_DELICATE_MASK;
reg_val |= FIOPAD_X_REG1_IN_DELAY_DELICATE_SET(delicate_delay);
/* update rough input delay */
reg_val &= ~FIOPAD_X_REG1_IN_DELAY_ROUGH_MASK;
reg_val |= FIOPAD_X_REG1_IN_DELAY_ROUGH_SET(roungh_delay);
/* enable input delay */
if (enable)
{
reg_val |= FIOPAD_X_REG1_IN_DELAY_EN;
}
else
{
reg_val &= ~FIOPAD_X_REG1_IN_DELAY_EN;
}
}
else
{
/* update delicate output delay */
reg_val &= ~FIOPAD_X_REG1_OUT_DELAY_DELICATE_MASK;
reg_val |= FIOPAD_X_REG1_OUT_DELAY_DELICATE_SET(delicate_delay);
/* update rough output delay */
reg_val &= ~FIOPAD_X_REG1_OUT_DELAY_ROUGH_MASK;
reg_val |= FIOPAD_X_REG1_OUT_DELAY_ROUGH_SET(roungh_delay);
/* enable output delay */
if (enable)
{
reg_val |= FIOPAD_X_REG1_OUT_DELAY_EN;
}
else
{
reg_val &= ~FIOPAD_X_REG1_OUT_DELAY_EN;
}
}
FIOPadWrite(pin, reg_val);
return;
}
/**
* @name: FPinGetDelayConfig
* @msg: Get current common IO pin delay config
* @return {NONE}
* @param {FPinIndex} pin, IO pin index
* @param {FPinDelay} *in_roungh_delay, input delay rough setting (输入粗调)
* @param {FPinDelay} *in_delicate_delay, input delay delicate setting (输入精调)
* @param {FPinDelay} *out_roungh_delay, output delay rough setting (输出粗调)
* @param {FPinDelay} *out_delicate_delay, output delay delicate setting (输出精调)
*/
void FPinGetDelayConfig(const FPinIndex pin, FPinDelay *in_roungh_delay, FPinDelay *in_delicate_delay,
FPinDelay *out_roungh_delay, FPinDelay *out_delicate_delay)
{
FIOPAD_ASSERT_REG1_OFF(pin);
u32 reg_val = FIOPadRead(pin);
if (out_delicate_delay)
{
*out_delicate_delay = FIOPAD_X_REG1_OUT_DELAY_DELICATE_GET(reg_val);
}
if (out_roungh_delay)
{
*out_roungh_delay = FIOPAD_X_REG1_OUT_DELAY_ROUGH_GET(reg_val);
}
if (in_delicate_delay)
{
*in_delicate_delay = FIOPAD_X_REG1_IN_DELAY_DELICATE_GET(reg_val);
}
if (in_roungh_delay)
{
*in_roungh_delay = FIOPAD_X_REG1_IN_DELAY_ROUGH_GET(reg_val);
}
return;
}
/**
* @name: FIOPadDumpPadFunc
* @msg: print information of all iopad
* @return {*}
*/
void FIOPadDumpPadFunc(void)
{
uintptr beg_off = FIOPAD_0_FUNC_OFFSET;
uintptr end_off = FIOPAD_147_FUNC_OFFSET;
uintptr off;
FPinIndex pin;
const char *pull_state[FPIN_NUM_OF_PULL] = {"none", "down", "up"};
FIOPAD_DEBUG("Pad Func Info...");
for (off = beg_off; off <= end_off; off += 4U)
{
pin.reg_off = off;
FIOPAD_DEBUG(" [0x%x] func: %d, ds: %d, pull: %s ",
pin.reg_off,
FPinGetFunc(pin),
FPinGetDrive(pin),
pull_state[FPinGetPull(pin)]);
}
}

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@ -1,310 +0,0 @@
#ifndef BOARD_E2000_FIOPAD_COMMON_H
#define BOARD_E2000_FIOPAD_COMMON_H
#ifdef __cplusplus
extern "C"
{
#endif
/***************************** Include Files *********************************/
#include "ftypes.h"
/**************************** Type Definitions *******************************/
/************************** Constant Definitions *****************************/
/************************** Variable Definitions *****************************/
/***************** Macros (Inline Functions) Definitions *********************/
#define FIOPAD_INDEX(offset) \
{ \
/* reg_off */ (offset), \
/* reg_bit */ (0) \
}
/*****************************************************************************/
/* register offset of iopad function / pull / driver strength */
#define FIOPAD_0_FUNC_OFFSET 0x0000U
#define FIOPAD_2_FUNC_OFFSET 0x0004U
#define FIOPAD_3_FUNC_OFFSET 0x0008U
#define FIOPAD_4_FUNC_OFFSET 0x000CU
#define FIOPAD_5_FUNC_OFFSET 0x0010U
#define FIOPAD_6_FUNC_OFFSET 0x0014U
#define FIOPAD_7_FUNC_OFFSET 0x0018U
#define FIOPAD_8_FUNC_OFFSET 0x001CU
#define FIOPAD_9_FUNC_OFFSET 0x0020U
#define FIOPAD_10_FUNC_OFFSET 0x0024U
#define FIOPAD_11_FUNC_OFFSET 0x0028U
#define FIOPAD_12_FUNC_OFFSET 0x002CU
#define FIOPAD_13_FUNC_OFFSET 0x0030U
#define FIOPAD_14_FUNC_OFFSET 0x0034U
#define FIOPAD_15_FUNC_OFFSET 0x0038U
#define FIOPAD_16_FUNC_OFFSET 0x003CU
#define FIOPAD_17_FUNC_OFFSET 0x0040U
#define FIOPAD_18_FUNC_OFFSET 0x0044U
#define FIOPAD_19_FUNC_OFFSET 0x0048U
#define FIOPAD_20_FUNC_OFFSET 0x004CU
#define FIOPAD_21_FUNC_OFFSET 0x0050U
#define FIOPAD_22_FUNC_OFFSET 0x0054U
#define FIOPAD_23_FUNC_OFFSET 0x0058U
#define FIOPAD_24_FUNC_OFFSET 0x005CU
#define FIOPAD_25_FUNC_OFFSET 0x0060U
#define FIOPAD_26_FUNC_OFFSET 0x0064U
#define FIOPAD_27_FUNC_OFFSET 0x0068U
#define FIOPAD_28_FUNC_OFFSET 0x006CU
#define FIOPAD_31_FUNC_OFFSET 0x0070U
#define FIOPAD_32_FUNC_OFFSET 0x0074U
#define FIOPAD_33_FUNC_OFFSET 0x0078U
#define FIOPAD_34_FUNC_OFFSET 0x007CU
#define FIOPAD_35_FUNC_OFFSET 0x0080U
#define FIOPAD_36_FUNC_OFFSET 0x0084U
#define FIOPAD_37_FUNC_OFFSET 0x0088U
#define FIOPAD_38_FUNC_OFFSET 0x008CU
#define FIOPAD_39_FUNC_OFFSET 0x0090U
#define FIOPAD_40_FUNC_OFFSET 0x0094U
#define FIOPAD_41_FUNC_OFFSET 0x0098U
#define FIOPAD_42_FUNC_OFFSET 0x009CU
#define FIOPAD_43_FUNC_OFFSET 0x00A0U
#define FIOPAD_44_FUNC_OFFSET 0x00A4U
#define FIOPAD_45_FUNC_OFFSET 0x00A8U
#define FIOPAD_46_FUNC_OFFSET 0x00ACU
#define FIOPAD_47_FUNC_OFFSET 0x00B0U
#define FIOPAD_48_FUNC_OFFSET 0x00B4U
#define FIOPAD_49_FUNC_OFFSET 0x00B8U
#define FIOPAD_50_FUNC_OFFSET 0x00BCU
#define FIOPAD_51_FUNC_OFFSET 0x00C0U
#define FIOPAD_52_FUNC_OFFSET 0x00C4U
#define FIOPAD_53_FUNC_OFFSET 0x00C8U
#define FIOPAD_54_FUNC_OFFSET 0x00CCU
#define FIOPAD_55_FUNC_OFFSET 0x00D0U
#define FIOPAD_56_FUNC_OFFSET 0x00D4U
#define FIOPAD_57_FUNC_OFFSET 0x00D8U
#define FIOPAD_58_FUNC_OFFSET 0x00DCU
#define FIOPAD_59_FUNC_OFFSET 0x00E0U
#define FIOPAD_60_FUNC_OFFSET 0x00E4U
#define FIOPAD_61_FUNC_OFFSET 0x00E8U
#define FIOPAD_62_FUNC_OFFSET 0x00ECU
#define FIOPAD_63_FUNC_OFFSET 0x00F0U
#define FIOPAD_64_FUNC_OFFSET 0x00F4U
#define FIOPAD_65_FUNC_OFFSET 0x00F8U
#define FIOPAD_66_FUNC_OFFSET 0x00FCU
#define FIOPAD_67_FUNC_OFFSET 0x0100U
#define FIOPAD_68_FUNC_OFFSET 0x0104U
#define FIOPAD_148_FUNC_OFFSET 0x0108U
#define FIOPAD_69_FUNC_OFFSET 0x010CU
#define FIOPAD_70_FUNC_OFFSET 0x0110U
#define FIOPAD_71_FUNC_OFFSET 0x0114U
#define FIOPAD_72_FUNC_OFFSET 0x0118U
#define FIOPAD_73_FUNC_OFFSET 0x011CU
#define FIOPAD_74_FUNC_OFFSET 0x0120U
#define FIOPAD_75_FUNC_OFFSET 0x0124U
#define FIOPAD_76_FUNC_OFFSET 0x0128U
#define FIOPAD_77_FUNC_OFFSET 0x012CU
#define FIOPAD_78_FUNC_OFFSET 0x0130U
#define FIOPAD_79_FUNC_OFFSET 0x0134U
#define FIOPAD_80_FUNC_OFFSET 0x0138U
#define FIOPAD_81_FUNC_OFFSET 0x013CU
#define FIOPAD_82_FUNC_OFFSET 0x0140U
#define FIOPAD_83_FUNC_OFFSET 0x0144U
#define FIOPAD_84_FUNC_OFFSET 0x0148U
#define FIOPAD_85_FUNC_OFFSET 0x014CU
#define FIOPAD_86_FUNC_OFFSET 0x0150U
#define FIOPAD_87_FUNC_OFFSET 0x0154U
#define FIOPAD_88_FUNC_OFFSET 0x0158U
#define FIOPAD_89_FUNC_OFFSET 0x015CU
#define FIOPAD_90_FUNC_OFFSET 0x0160U
#define FIOPAD_91_FUNC_OFFSET 0x0164U
#define FIOPAD_92_FUNC_OFFSET 0x0168U
#define FIOPAD_93_FUNC_OFFSET 0x016CU
#define FIOPAD_94_FUNC_OFFSET 0x0170U
#define FIOPAD_95_FUNC_OFFSET 0x0174U
#define FIOPAD_96_FUNC_OFFSET 0x0178U
#define FIOPAD_97_FUNC_OFFSET 0x017CU
#define FIOPAD_98_FUNC_OFFSET 0x0180U
#define FIOPAD_29_FUNC_OFFSET 0x0184U
#define FIOPAD_30_FUNC_OFFSET 0x0188U
#define FIOPAD_99_FUNC_OFFSET 0x018CU
#define FIOPAD_100_FUNC_OFFSET 0x0190U
#define FIOPAD_101_FUNC_OFFSET 0x0194U
#define FIOPAD_102_FUNC_OFFSET 0x0198U
#define FIOPAD_103_FUNC_OFFSET 0x019CU
#define FIOPAD_104_FUNC_OFFSET 0x01A0U
#define FIOPAD_105_FUNC_OFFSET 0x01A4U
#define FIOPAD_106_FUNC_OFFSET 0x01A8U
#define FIOPAD_107_FUNC_OFFSET 0x01ACU
#define FIOPAD_108_FUNC_OFFSET 0x01B0U
#define FIOPAD_109_FUNC_OFFSET 0x01B4U
#define FIOPAD_110_FUNC_OFFSET 0x01B8U
#define FIOPAD_111_FUNC_OFFSET 0x01BCU
#define FIOPAD_112_FUNC_OFFSET 0x01C0U
#define FIOPAD_113_FUNC_OFFSET 0x01C4U
#define FIOPAD_114_FUNC_OFFSET 0x01C8U
#define FIOPAD_115_FUNC_OFFSET 0x01CCU
#define FIOPAD_116_FUNC_OFFSET 0x01D0U
#define FIOPAD_117_FUNC_OFFSET 0x01D4U
#define FIOPAD_118_FUNC_OFFSET 0x01D8U
#define FIOPAD_119_FUNC_OFFSET 0x01DCU
#define FIOPAD_120_FUNC_OFFSET 0x01E0U
#define FIOPAD_121_FUNC_OFFSET 0x01E4U
#define FIOPAD_122_FUNC_OFFSET 0x01E8U
#define FIOPAD_123_FUNC_OFFSET 0x01ECU
#define FIOPAD_124_FUNC_OFFSET 0x01F0U
#define FIOPAD_125_FUNC_OFFSET 0x01F4U
#define FIOPAD_126_FUNC_OFFSET 0x01F8U
#define FIOPAD_127_FUNC_OFFSET 0x01FCU
#define FIOPAD_128_FUNC_OFFSET 0x0200U
#define FIOPAD_129_FUNC_OFFSET 0x0204U
#define FIOPAD_130_FUNC_OFFSET 0x0208U
#define FIOPAD_131_FUNC_OFFSET 0x020CU
#define FIOPAD_132_FUNC_OFFSET 0x0210U
#define FIOPAD_133_FUNC_OFFSET 0x0214U
#define FIOPAD_134_FUNC_OFFSET 0x0218U
#define FIOPAD_135_FUNC_OFFSET 0x021CU
#define FIOPAD_136_FUNC_OFFSET 0x0220U
#define FIOPAD_137_FUNC_OFFSET 0x0224U
#define FIOPAD_138_FUNC_OFFSET 0x0228U
#define FIOPAD_139_FUNC_OFFSET 0x022CU
#define FIOPAD_140_FUNC_OFFSET 0x0230U
#define FIOPAD_141_FUNC_OFFSET 0x0234U
#define FIOPAD_142_FUNC_OFFSET 0x0238U
#define FIOPAD_143_FUNC_OFFSET 0x023CU
#define FIOPAD_144_FUNC_OFFSET 0x0240U
#define FIOPAD_145_FUNC_OFFSET 0x0244U
#define FIOPAD_146_FUNC_OFFSET 0x0248U
#define FIOPAD_147_FUNC_OFFSET 0x024CU
/* register offset of iopad delay */
#define FIOPAD_10_DELAY_OFFSET 0x1024U
#define FIOPAD_11_DELAY_OFFSET 0x1028U
#define FIOPAD_12_DELAY_OFFSET 0x102CU
#define FIOPAD_13_DELAY_OFFSET 0x1030U
#define FIOPAD_14_DELAY_OFFSET 0x1034U
#define FIOPAD_23_DELAY_OFFSET 0x1058U
#define FIOPAD_24_DELAY_OFFSET 0x105CU
#define FIOPAD_25_DELAY_OFFSET 0x1060U
#define FIOPAD_26_DELAY_OFFSET 0x1064U
#define FIOPAD_32_DELAY_OFFSET 0x1074U
#define FIOPAD_33_DELAY_OFFSET 0x1078U
#define FIOPAD_34_DELAY_OFFSET 0x107CU
#define FIOPAD_35_DELAY_OFFSET 0x1080U
#define FIOPAD_55_DELAY_OFFSET 0x10D0U
#define FIOPAD_56_DELAY_OFFSET 0x10D4U
#define FIOPAD_57_DELAY_OFFSET 0x10D8U
#define FIOPAD_58_DELAY_OFFSET 0x10DCU
#define FIOPAD_59_DELAY_OFFSET 0x10E0U
#define FIOPAD_60_DELAY_OFFSET 0x10E4U
#define FIOPAD_61_DELAY_OFFSET 0x10E8U
#define FIOPAD_62_DELAY_OFFSET 0x10ECU
#define FIOPAD_63_DELAY_OFFSET 0x10F0U
#define FIOPAD_64_DELAY_OFFSET 0x10F4U
#define FIOPAD_65_DELAY_OFFSET 0x10F8U
#define FIOPAD_66_DELAY_OFFSET 0x10FCU
#define FIOPAD_67_DELAY_OFFSET 0x1100U
#define FIOPAD_68_DELAY_OFFSET 0x1104U
#define FIOPAD_148_DELAY_OFFSET 0x1108U
#define FIOPAD_69_DELAY_OFFSET 0x110CU
#define FIOPAD_70_DELAY_OFFSET 0x1110U
#define FIOPAD_71_DELAY_OFFSET 0x1114U
#define FIOPAD_72_DELAY_OFFSET 0x1118U
#define FIOPAD_73_DELAY_OFFSET 0x111CU
#define FIOPAD_74_DELAY_OFFSET 0x1120U
#define FIOPAD_75_DELAY_OFFSET 0x1124U
#define FIOPAD_76_DELAY_OFFSET 0x1128U
#define FIOPAD_77_DELAY_OFFSET 0x112CU
#define FIOPAD_78_DELAY_OFFSET 0x1130U
#define FIOPAD_80_DELAY_OFFSET 0x1138U
#define FIOPAD_81_DELAY_OFFSET 0x113CU
#define FIOPAD_82_DELAY_OFFSET 0x1140U
#define FIOPAD_83_DELAY_OFFSET 0x1144U
#define FIOPAD_84_DELAY_OFFSET 0x1148U
#define FIOPAD_85_DELAY_OFFSET 0x114CU
#define FIOPAD_86_DELAY_OFFSET 0x1150U
#define FIOPAD_87_DELAY_OFFSET 0x1154U
#define FIOPAD_88_DELAY_OFFSET 0x1158U
#define FIOPAD_89_DELAY_OFFSET 0x115CU
#define FIOPAD_90_DELAY_OFFSET 0x1160U
#define FIOPAD_92_DELAY_OFFSET 0x1168U
#define FIOPAD_93_DELAY_OFFSET 0x116CU
#define FIOPAD_94_DELAY_OFFSET 0x1170U
#define FIOPAD_95_DELAY_OFFSET 0x1174U
#define FIOPAD_96_DELAY_OFFSET 0x1178U
#define FIOPAD_97_DELAY_OFFSET 0x117CU
#define FIOPAD_98_DELAY_OFFSET 0x1180U
#define FIOPAD_99_DELAY_OFFSET 0x118CU
#define FIOPAD_100_DELAY_OFFSET 0x1190U
#define FIOPAD_101_DELAY_OFFSET 0x1194U
#define FIOPAD_102_DELAY_OFFSET 0x1198U
#define FIOPAD_103_DELAY_OFFSET 0x119CU
#define FIOPAD_104_DELAY_OFFSET 0x11A0U
#define FIOPAD_105_DELAY_OFFSET 0x11A4U
#define FIOPAD_106_DELAY_OFFSET 0x11A8U
#define FIOPAD_107_DELAY_OFFSET 0x11ACU
#define FIOPAD_108_DELAY_OFFSET 0x11B0U
#define FIOPAD_109_DELAY_OFFSET 0x11B4U
#define FIOPAD_110_DELAY_OFFSET 0x11B8U
#define FIOPAD_111_DELAY_OFFSET 0x11BCU
#define FIOPAD_112_DELAY_OFFSET 0x11C0U
#define FIOPAD_115_DELAY_OFFSET 0x11CCU
#define FIOPAD_116_DELAY_OFFSET 0x11D0U
#define FIOPAD_117_DELAY_OFFSET 0x11D4U
#define FIOPAD_118_DELAY_OFFSET 0x11D8U
#define FIOPAD_119_DELAY_OFFSET 0x11DCU
#define FIOPAD_120_DELAY_OFFSET 0x11E0U
#define FIOPAD_121_DELAY_OFFSET 0x11E4U
#define FIOPAD_122_DELAY_OFFSET 0x11E8U
#define FIOPAD_123_DELAY_OFFSET 0x11ECU
#define FIOPAD_124_DELAY_OFFSET 0x11F0U
#define FIOPAD_125_DELAY_OFFSET 0x11F4U
#define FIOPAD_126_DELAY_OFFSET 0x11F8U
#define FIOPAD_127_DELAY_OFFSET 0x11FCU
#define FIOPAD_128_DELAY_OFFSET 0x1200U
#define FIOPAD_136_DELAY_OFFSET 0x1220U
#define FIOPAD_137_DELAY_OFFSET 0x1224U
#define FIOPAD_138_DELAY_OFFSET 0x1228U
#define FIOPAD_139_DELAY_OFFSET 0x122CU
#define FIOPAD_140_DELAY_OFFSET 0x1230U
#define FIOPAD_141_DELAY_OFFSET 0x1234U
#define FIOPAD_142_DELAY_OFFSET 0x1238U
#define FIOPAD_143_DELAY_OFFSET 0x123CU
#define FIOPAD_144_DELAY_OFFSET 0x1240U
#define FIOPAD_145_DELAY_OFFSET 0x1244U
#define FIOPAD_146_DELAY_OFFSET 0x1248U
#define FIOPAD_147_DELAY_OFFSET 0x124CU
/************************** Function Prototypes ******************************/
/* set iopad mux for spim */
void FIOPadSetSpimMux(u32 spim_id);
/* set iopad mux for gpio */
void FIOPadSetGpioMux(u32 gpio_id, u32 pin_id);
/* set iopad mux for mio */
void FIOPadSetMioMux(u32 mio_id);
/* print information of all iopad */
void FIOPadDumpPadFunc(void);
/* set iopad mux for can */
void FIOPadSetCanMux(u32 can_id);
/* set iopad mux for qspi */
void FIOPadSetQspiMux(u32 qspi_id, u32 cs_id);
/* set iopad mux for pwm */
void FIOPadSetPwmMux(u32 pwm_id, u32 pwm_channel);
/* set iopad mux for adc */
void FIOPadSetAdcMux(u32 adc_id, u32 adc_channel);
/* set iopad mux for tacho*/
void FIOPadSetTachoMux(u32 pwm_in_id);
/* set iopad mux for uart*/
void FIOPadSetUartMux(u32 uart_id);
#ifdef __cplusplus
}
#endif
#endif

74
bsp/phytium/libraries/standalone/board/e2000/fparameters_comm.h
View File

@ -36,7 +36,7 @@ extern "C"
/************************** Constant Definitions *****************************/
/* CACHE */
#define CACHE_LINE_ADDR_MASK 0x3FU
#define CACHE_LINE_ADDR_MASK 0x3FUL
#define CACHE_LINE 64U
/* DEVICE Register Address */
@ -141,12 +141,6 @@ enum
#define FSCMI_MAX_PERF_DOMAINS 3
#define FSCMI_MAX_OPPS 4
/* Generic Timer */
#define GENERIC_TIMER_CLK_FREQ_MHZ 48U
#define GENERIC_TIMER_NS_IRQ_NUM 30U
#define GENERIC_TIMER_NS_CLK_FREQ 2000000U
#define COUNTS_PER_SECOND GENERIC_TIMER_NS_CLK_FREQ
/* UART */
#define FUART_NUM 4U
#define FUART_REG_LENGTH 0x18000U
@ -312,6 +306,18 @@ enum
#define FXMAC_PHY_MAX_NUM 32U
#define FXMAC_CLK_TYPE_0
#if !defined(__ASSEMBLER__)
/* IOPAD */
enum
{
FIOPAD0_ID = 0,
FIOPAD_NUM
};
#endif
/* QSPI */
#if !defined(__ASSEMBLER__)
enum
@ -342,7 +348,7 @@ enum
/* TIMER and TACHO */
#define FTIMER_NUM 38U
#define FTIMER_CLK_FREQ_HZ 50000000U /* 50MHz */
#define FTIMER_CLK_FREQ_HZ 50000000ULL /* 50MHz */
#define FTIMER_TICK_PERIOD_NS 20U /* 20ns */
#define FTIMER_TACHO_IRQ_NUM(n) (226U + (n))
#define FTIMER_TACHO_BASE_ADDR(n) (0x28054000U + 0x1000U * (n))
@ -533,6 +539,41 @@ enum
#define FDDMA0_SPIM2_RX_SLAVE_ID 21U /* spi2 rx slave-id */
#define FDDMA0_SPIM3_RX_SLAVE_ID 22U /* spi3 rx slave-id */
/* FDDMA1_ID */
#define FDDMA1_MIO0_TX_SLAVE_ID 0U /* mio0 rx slave-id */
#define FDDMA1_MIO1_TX_SLAVE_ID 1U /* mio1 rx slave-id */
#define FDDMA1_MIO2_TX_SLAVE_ID 2U /* mio2 rx slave-id */
#define FDDMA1_MIO3_TX_SLAVE_ID 3U /* mio3 rx slave-id */
#define FDDMA1_MIO4_TX_SLAVE_ID 4U /* mio4 rx slave-id */
#define FDDMA1_MIO5_TX_SLAVE_ID 5U /* mio5 rx slave-id */
#define FDDMA1_MIO6_TX_SLAVE_ID 6U /* mio6 rx slave-id */
#define FDDMA1_MIO7_TX_SLAVE_ID 7U /* mio7 rx slave-id */
#define FDDMA1_MIO8_TX_SLAVE_ID 8U /* mio8 rx slave-id */
#define FDDMA1_MIO9_TX_SLAVE_ID 9U /* mio9 rx slave-id */
#define FDDMA1_MIO10_TX_SLAVE_ID 10U /* mio10 rx slave-id */
#define FDDMA1_MIO11_TX_SLAVE_ID 11U /* mio11 rx slave-id */
#define FDDMA1_MIO12_TX_SLAVE_ID 12U /* mio12 rx slave-id */
#define FDDMA1_MIO13_TX_SLAVE_ID 13U /* mio13 rx slave-id */
#define FDDMA1_MIO14_TX_SLAVE_ID 14U /* mio14 rx slave-id */
#define FDDMA1_MIO15_TX_SLAVE_ID 15U /* mio15 rx slave-id */
#define FDDMA1_MIO0_RX_SLAVE_ID 16U /* mio0 tx slave-id */
#define FDDMA1_MIO1_RX_SLAVE_ID 17U /* mio1 tx slave-id */
#define FDDMA1_MIO2_RX_SLAVE_ID 18U /* mio2 tx slave-id */
#define FDDMA1_MIO3_RX_SLAVE_ID 19U /* mio3 tx slave-id */
#define FDDMA1_MIO4_RX_SLAVE_ID 20U /* mio4 tx slave-id */
#define FDDMA1_MIO5_RX_SLAVE_ID 21U /* mio5 tx slave-id */
#define FDDMA1_MIO6_RX_SLAVE_ID 22U /* mio6 tx slave-id */
#define FDDMA1_MIO7_RX_SLAVE_ID 23U /* mio7 tx slave-id */
#define FDDMA1_MIO8_RX_SLAVE_ID 24U /* mio8 tx slave-id */
#define FDDMA1_MIO9_RX_SLAVE_ID 25U /* mio9 tx slave-id */
#define FDDMA1_MIO10_RX_SLAVE_ID 26U /* mio10 tx slave-id */
#define FDDMA1_MIO11_RX_SLAVE_ID 27U /* mio11 tx slave-id */
#define FDDMA1_MIO12_RX_SLAVE_ID 28U /* mio12 tx slave-id */
#define FDDMA1_MIO13_RX_SLAVE_ID 29U /* mio13 tx slave-id */
#define FDDMA1_MIO14_RX_SLAVE_ID 30U /* mio14 tx slave-id */
#define FDDMA1_MIO15_RX_SLAVE_ID 31U /* mio15 tx slave-id */
#define FDDMA_MIN_SLAVE_ID 0U
#define FDDMA_MAX_SLAVE_ID 31U
@ -657,6 +698,23 @@ typedef enum
#define FDCDP_IRQ_NUM 76
/* generic timer */
/* non-secure physical timer int id */
#define GENERIC_TIMER_NS_IRQ_NUM 30U
/* virtual timer int id */
#define GENERIC_VTIMER_IRQ_NUM 27U
#if !defined(__ASSEMBLER__)
enum
{
GENERIC_TIMER_ID0 = 0, /* non-secure physical timer */
GENERIC_TIMER_ID1 = 1, /* virtual timer */
GENERIC_TIMER_NUM
};
#endif
/*****************************************************************************/
#ifdef __cplusplus

266
bsp/phytium/libraries/standalone/board/e2000/q/fiopad.h
View File

@ -1,266 +0,0 @@
#ifndef BOARD_E2000Q_FIOPAD_H
#define BOARD_E2000Q_FIOPAD_H
#ifdef __cplusplus
extern "C"
{
#endif
/***************************** Include Files *********************************/
#include "fiopad_comm.h"
/************************** Constant Definitions *****************************/
/* register offset of iopad function / pull / driver strength */
#define FIOPAD_AN59 (FPinIndex)FIOPAD_INDEX(FIOPAD_0_FUNC_OFFSET)
#define FIOPAD_AW47 (FPinIndex)FIOPAD_INDEX(FIOPAD_2_FUNC_OFFSET)
#define FIOPAD_AR55 (FPinIndex)FIOPAD_INDEX(FIOPAD_9_FUNC_OFFSET)
#define FIOPAD_AJ55 (FPinIndex)FIOPAD_INDEX(FIOPAD_10_FUNC_OFFSET)
#define FIOPAD_AL55 (FPinIndex)FIOPAD_INDEX(FIOPAD_11_FUNC_OFFSET)
#define FIOPAD_AL53 (FPinIndex)FIOPAD_INDEX(FIOPAD_12_FUNC_OFFSET)
#define FIOPAD_AN51 (FPinIndex)FIOPAD_INDEX(FIOPAD_13_FUNC_OFFSET)
#define FIOPAD_AR51 (FPinIndex)FIOPAD_INDEX(FIOPAD_14_FUNC_OFFSET)
#define FIOPAD_BA57 (FPinIndex)FIOPAD_INDEX(FIOPAD_15_FUNC_OFFSET)
#define FIOPAD_BA59 (FPinIndex)FIOPAD_INDEX(FIOPAD_16_FUNC_OFFSET)
#define FIOPAD_AW57 (FPinIndex)FIOPAD_INDEX(FIOPAD_17_FUNC_OFFSET)
#define FIOPAD_AW59 (FPinIndex)FIOPAD_INDEX(FIOPAD_18_FUNC_OFFSET)
#define FIOPAD_AU55 (FPinIndex)FIOPAD_INDEX(FIOPAD_19_FUNC_OFFSET)
#define FIOPAD_AN57 (FPinIndex)FIOPAD_INDEX(FIOPAD_20_FUNC_OFFSET)
#define FIOPAD_AL59 (FPinIndex)FIOPAD_INDEX(FIOPAD_21_FUNC_OFFSET)
#define FIOPAD_AJ59 (FPinIndex)FIOPAD_INDEX(FIOPAD_22_FUNC_OFFSET)
#define FIOPAD_AJ57 (FPinIndex)FIOPAD_INDEX(FIOPAD_23_FUNC_OFFSET)
#define FIOPAD_AG59 (FPinIndex)FIOPAD_INDEX(FIOPAD_24_FUNC_OFFSET)
#define FIOPAD_AG57 (FPinIndex)FIOPAD_INDEX(FIOPAD_25_FUNC_OFFSET)
#define FIOPAD_AE59 (FPinIndex)FIOPAD_INDEX(FIOPAD_26_FUNC_OFFSET)
#define FIOPAD_AC59 (FPinIndex)FIOPAD_INDEX(FIOPAD_27_FUNC_OFFSET)
#define FIOPAD_AC57 (FPinIndex)FIOPAD_INDEX(FIOPAD_28_FUNC_OFFSET)
#define FIOPAD_AR49 (FPinIndex)FIOPAD_INDEX(FIOPAD_31_FUNC_OFFSET)
#define FIOPAD_BA55 (FPinIndex)FIOPAD_INDEX(FIOPAD_32_FUNC_OFFSET)
#define FIOPAD_BA53 (FPinIndex)FIOPAD_INDEX(FIOPAD_33_FUNC_OFFSET)
#define FIOPAD_AR59 (FPinIndex)FIOPAD_INDEX(FIOPAD_34_FUNC_OFFSET)
#define FIOPAD_AU59 (FPinIndex)FIOPAD_INDEX(FIOPAD_35_FUNC_OFFSET)
#define FIOPAD_AR57 (FPinIndex)FIOPAD_INDEX(FIOPAD_36_FUNC_OFFSET)
#define FIOPAD_BA49 (FPinIndex)FIOPAD_INDEX(FIOPAD_37_FUNC_OFFSET)
#define FIOPAD_AW55 (FPinIndex)FIOPAD_INDEX(FIOPAD_38_FUNC_OFFSET)
#define FIOPAD_A35 (FPinIndex)FIOPAD_INDEX(FIOPAD_39_FUNC_OFFSET)
#define FIOPAD_R57 (FPinIndex)FIOPAD_INDEX(FIOPAD_40_FUNC_OFFSET)
#define FIOPAD_R59 (FPinIndex)FIOPAD_INDEX(FIOPAD_41_FUNC_OFFSET)
#define FIOPAD_U59 (FPinIndex)FIOPAD_INDEX(FIOPAD_42_FUNC_OFFSET)
#define FIOPAD_W59 (FPinIndex)FIOPAD_INDEX(FIOPAD_43_FUNC_OFFSET)
#define FIOPAD_U57 (FPinIndex)FIOPAD_INDEX(FIOPAD_44_FUNC_OFFSET)
#define FIOPAD_AA57 (FPinIndex)FIOPAD_INDEX(FIOPAD_45_FUNC_OFFSET)
#define FIOPAD_AA59 (FPinIndex)FIOPAD_INDEX(FIOPAD_46_FUNC_OFFSET)
#define FIOPAD_AW51 (FPinIndex)FIOPAD_INDEX(FIOPAD_47_FUNC_OFFSET)
#define FIOPAD_AU51 (FPinIndex)FIOPAD_INDEX(FIOPAD_48_FUNC_OFFSET)
#define FIOPAD_A39 (FPinIndex)FIOPAD_INDEX(FIOPAD_49_FUNC_OFFSET)
#define FIOPAD_C39 (FPinIndex)FIOPAD_INDEX(FIOPAD_50_FUNC_OFFSET)
#define FIOPAD_C37 (FPinIndex)FIOPAD_INDEX(FIOPAD_51_FUNC_OFFSET)
#define FIOPAD_A37 (FPinIndex)FIOPAD_INDEX(FIOPAD_52_FUNC_OFFSET)
#define FIOPAD_A41 (FPinIndex)FIOPAD_INDEX(FIOPAD_53_FUNC_OFFSET)
#define FIOPAD_A43 (FPinIndex)FIOPAD_INDEX(FIOPAD_54_FUNC_OFFSET)
#define FIOPAD_A45 (FPinIndex)FIOPAD_INDEX(FIOPAD_55_FUNC_OFFSET)
#define FIOPAD_C45 (FPinIndex)FIOPAD_INDEX(FIOPAD_56_FUNC_OFFSET)
#define FIOPAD_A47 (FPinIndex)FIOPAD_INDEX(FIOPAD_57_FUNC_OFFSET)
#define FIOPAD_A49 (FPinIndex)FIOPAD_INDEX(FIOPAD_58_FUNC_OFFSET)
#define FIOPAD_C49 (FPinIndex)FIOPAD_INDEX(FIOPAD_59_FUNC_OFFSET)
#define FIOPAD_A51 (FPinIndex)FIOPAD_INDEX(FIOPAD_60_FUNC_OFFSET)
#define FIOPAD_A33 (FPinIndex)FIOPAD_INDEX(FIOPAD_61_FUNC_OFFSET)
#define FIOPAD_C33 (FPinIndex)FIOPAD_INDEX(FIOPAD_62_FUNC_OFFSET)
#define FIOPAD_C31 (FPinIndex)FIOPAD_INDEX(FIOPAD_63_FUNC_OFFSET)
#define FIOPAD_A31 (FPinIndex)FIOPAD_INDEX(FIOPAD_64_FUNC_OFFSET)
#define FIOPAD_AJ53 (FPinIndex)FIOPAD_INDEX(FIOPAD_65_FUNC_OFFSET)
#define FIOPAD_AL49 (FPinIndex)FIOPAD_INDEX(FIOPAD_66_FUNC_OFFSET)
#define FIOPAD_AL47 (FPinIndex)FIOPAD_INDEX(FIOPAD_67_FUNC_OFFSET)
#define FIOPAD_AN49 (FPinIndex)FIOPAD_INDEX(FIOPAD_68_FUNC_OFFSET)
#define FIOPAD_AG51 (FPinIndex)FIOPAD_INDEX(FIOPAD_148_FUNC_OFFSET)
#define FIOPAD_AJ51 (FPinIndex)FIOPAD_INDEX(FIOPAD_69_FUNC_OFFSET)
#define FIOPAD_AG49 (FPinIndex)FIOPAD_INDEX(FIOPAD_70_FUNC_OFFSET)
#define FIOPAD_AE55 (FPinIndex)FIOPAD_INDEX(FIOPAD_71_FUNC_OFFSET)
#define FIOPAD_AE53 (FPinIndex)FIOPAD_INDEX(FIOPAD_72_FUNC_OFFSET)
#define FIOPAD_AG55 (FPinIndex)FIOPAD_INDEX(FIOPAD_73_FUNC_OFFSET)
#define FIOPAD_AJ49 (FPinIndex)FIOPAD_INDEX(FIOPAD_74_FUNC_OFFSET)
#define FIOPAD_AC55 (FPinIndex)FIOPAD_INDEX(FIOPAD_75_FUNC_OFFSET)
#define FIOPAD_AC53 (FPinIndex)FIOPAD_INDEX(FIOPAD_76_FUNC_OFFSET)
#define FIOPAD_AE51 (FPinIndex)FIOPAD_INDEX(FIOPAD_77_FUNC_OFFSET)
#define FIOPAD_W51 (FPinIndex)FIOPAD_INDEX(FIOPAD_78_FUNC_OFFSET)
#define FIOPAD_W55 (FPinIndex)FIOPAD_INDEX(FIOPAD_79_FUNC_OFFSET)
#define FIOPAD_W53 (FPinIndex)FIOPAD_INDEX(FIOPAD_80_FUNC_OFFSET)
#define FIOPAD_U55 (FPinIndex)FIOPAD_INDEX(FIOPAD_81_FUNC_OFFSET)
#define FIOPAD_U53 (FPinIndex)FIOPAD_INDEX(FIOPAD_82_FUNC_OFFSET)
#define FIOPAD_AE49 (FPinIndex)FIOPAD_INDEX(FIOPAD_83_FUNC_OFFSET)
#define FIOPAD_AC49 (FPinIndex)FIOPAD_INDEX(FIOPAD_84_FUNC_OFFSET)
#define FIOPAD_AE47 (FPinIndex)FIOPAD_INDEX(FIOPAD_85_FUNC_OFFSET)
#define FIOPAD_AA47 (FPinIndex)FIOPAD_INDEX(FIOPAD_86_FUNC_OFFSET)
#define FIOPAD_AA49 (FPinIndex)FIOPAD_INDEX(FIOPAD_87_FUNC_OFFSET)
#define FIOPAD_W49 (FPinIndex)FIOPAD_INDEX(FIOPAD_88_FUNC_OFFSET)
#define FIOPAD_AA51 (FPinIndex)FIOPAD_INDEX(FIOPAD_89_FUNC_OFFSET)
#define FIOPAD_U49 (FPinIndex)FIOPAD_INDEX(FIOPAD_90_FUNC_OFFSET)
#define FIOPAD_G59 (FPinIndex)FIOPAD_INDEX(FIOPAD_91_FUNC_OFFSET)
#define FIOPAD_J59 (FPinIndex)FIOPAD_INDEX(FIOPAD_92_FUNC_OFFSET)
#define FIOPAD_L57 (FPinIndex)FIOPAD_INDEX(FIOPAD_93_FUNC_OFFSET)
#define FIOPAD_C59 (FPinIndex)FIOPAD_INDEX(FIOPAD_94_FUNC_OFFSET)
#define FIOPAD_E59 (FPinIndex)FIOPAD_INDEX(FIOPAD_95_FUNC_OFFSET)
#define FIOPAD_J57 (FPinIndex)FIOPAD_INDEX(FIOPAD_96_FUNC_OFFSET)
#define FIOPAD_L59 (FPinIndex)FIOPAD_INDEX(FIOPAD_97_FUNC_OFFSET)
#define FIOPAD_N59 (FPinIndex)FIOPAD_INDEX(FIOPAD_98_FUNC_OFFSET)
#define FIOPAD_C57 (FPinIndex)FIOPAD_INDEX(FIOPAD_29_FUNC_OFFSET)
#define FIOPAD_E57 (FPinIndex)FIOPAD_INDEX(FIOPAD_30_FUNC_OFFSET)
#define FIOPAD_E31 (FPinIndex)FIOPAD_INDEX(FIOPAD_99_FUNC_OFFSET)
#define FIOPAD_G31 (FPinIndex)FIOPAD_INDEX(FIOPAD_100_FUNC_OFFSET)
#define FIOPAD_N41 (FPinIndex)FIOPAD_INDEX(FIOPAD_101_FUNC_OFFSET)
#define FIOPAD_N39 (FPinIndex)FIOPAD_INDEX(FIOPAD_102_FUNC_OFFSET)
#define FIOPAD_J33 (FPinIndex)FIOPAD_INDEX(FIOPAD_103_FUNC_OFFSET)
#define FIOPAD_N33 (FPinIndex)FIOPAD_INDEX(FIOPAD_104_FUNC_OFFSET)
#define FIOPAD_L33 (FPinIndex)FIOPAD_INDEX(FIOPAD_105_FUNC_OFFSET)
#define FIOPAD_N45 (FPinIndex)FIOPAD_INDEX(FIOPAD_106_FUNC_OFFSET)
#define FIOPAD_N43 (FPinIndex)FIOPAD_INDEX(FIOPAD_107_FUNC_OFFSET)
#define FIOPAD_L31 (FPinIndex)FIOPAD_INDEX(FIOPAD_108_FUNC_OFFSET)
#define FIOPAD_J31 (FPinIndex)FIOPAD_INDEX(FIOPAD_109_FUNC_OFFSET)
#define FIOPAD_J29 (FPinIndex)FIOPAD_INDEX(FIOPAD_110_FUNC_OFFSET)
#define FIOPAD_E29 (FPinIndex)FIOPAD_INDEX(FIOPAD_111_FUNC_OFFSET)
#define FIOPAD_G29 (FPinIndex)FIOPAD_INDEX(FIOPAD_112_FUNC_OFFSET)
#define FIOPAD_N27 (FPinIndex)FIOPAD_INDEX(FIOPAD_113_FUNC_OFFSET)
#define FIOPAD_L29 (FPinIndex)FIOPAD_INDEX(FIOPAD_114_FUNC_OFFSET)
#define FIOPAD_J37 (FPinIndex)FIOPAD_INDEX(FIOPAD_115_FUNC_OFFSET)
#define FIOPAD_J39 (FPinIndex)FIOPAD_INDEX(FIOPAD_116_FUNC_OFFSET)
#define FIOPAD_G41 (FPinIndex)FIOPAD_INDEX(FIOPAD_117_FUNC_OFFSET)
#define FIOPAD_E43 (FPinIndex)FIOPAD_INDEX(FIOPAD_118_FUNC_OFFSET)
#define FIOPAD_L43 (FPinIndex)FIOPAD_INDEX(FIOPAD_119_FUNC_OFFSET)
#define FIOPAD_C43 (FPinIndex)FIOPAD_INDEX(FIOPAD_120_FUNC_OFFSET)
#define FIOPAD_E41 (FPinIndex)FIOPAD_INDEX(FIOPAD_121_FUNC_OFFSET)
#define FIOPAD_L45 (FPinIndex)FIOPAD_INDEX(FIOPAD_122_FUNC_OFFSET)
#define FIOPAD_J43 (FPinIndex)FIOPAD_INDEX(FIOPAD_123_FUNC_OFFSET)
#define FIOPAD_J41 (FPinIndex)FIOPAD_INDEX(FIOPAD_124_FUNC_OFFSET)
#define FIOPAD_L39 (FPinIndex)FIOPAD_INDEX(FIOPAD_125_FUNC_OFFSET)
#define FIOPAD_E37 (FPinIndex)FIOPAD_INDEX(FIOPAD_126_FUNC_OFFSET)
#define FIOPAD_E35 (FPinIndex)FIOPAD_INDEX(FIOPAD_127_FUNC_OFFSET)
#define FIOPAD_G35 (FPinIndex)FIOPAD_INDEX(FIOPAD_128_FUNC_OFFSET)
#define FIOPAD_J35 (FPinIndex)FIOPAD_INDEX(FIOPAD_129_FUNC_OFFSET)
#define FIOPAD_L37 (FPinIndex)FIOPAD_INDEX(FIOPAD_130_FUNC_OFFSET)
#define FIOPAD_N35 (FPinIndex)FIOPAD_INDEX(FIOPAD_131_FUNC_OFFSET)
#define FIOPAD_R51 (FPinIndex)FIOPAD_INDEX(FIOPAD_132_FUNC_OFFSET)
#define FIOPAD_R49 (FPinIndex)FIOPAD_INDEX(FIOPAD_133_FUNC_OFFSET)
#define FIOPAD_N51 (FPinIndex)FIOPAD_INDEX(FIOPAD_134_FUNC_OFFSET)
#define FIOPAD_N55 (FPinIndex)FIOPAD_INDEX(FIOPAD_135_FUNC_OFFSET)
#define FIOPAD_L55 (FPinIndex)FIOPAD_INDEX(FIOPAD_136_FUNC_OFFSET)
#define FIOPAD_J55 (FPinIndex)FIOPAD_INDEX(FIOPAD_137_FUNC_OFFSET)
#define FIOPAD_J45 (FPinIndex)FIOPAD_INDEX(FIOPAD_138_FUNC_OFFSET)
#define FIOPAD_E47 (FPinIndex)FIOPAD_INDEX(FIOPAD_139_FUNC_OFFSET)
#define FIOPAD_G47 (FPinIndex)FIOPAD_INDEX(FIOPAD_140_FUNC_OFFSET)
#define FIOPAD_J47 (FPinIndex)FIOPAD_INDEX(FIOPAD_141_FUNC_OFFSET)
#define FIOPAD_J49 (FPinIndex)FIOPAD_INDEX(FIOPAD_142_FUNC_OFFSET)
#define FIOPAD_N49 (FPinIndex)FIOPAD_INDEX(FIOPAD_143_FUNC_OFFSET)
#define FIOPAD_L51 (FPinIndex)FIOPAD_INDEX(FIOPAD_144_FUNC_OFFSET)
#define FIOPAD_L49 (FPinIndex)FIOPAD_INDEX(FIOPAD_145_FUNC_OFFSET)
#define FIOPAD_N53 (FPinIndex)FIOPAD_INDEX(FIOPAD_146_FUNC_OFFSET)
#define FIOPAD_J53 (FPinIndex)FIOPAD_INDEX(FIOPAD_147_FUNC_OFFSET)
/* register offset of iopad delay */
#define FIOPAD_AJ55_DELAY (FPinIndex)FIOPAD_INDEX(FIOPAD_10_DELAY_OFFSET)
#define FIOPAD_AL55_DELAY (FPinIndex)FIOPAD_INDEX(FIOPAD_11_DELAY_OFFSET)
#define FIOPAD_AL53_DELAY (FPinIndex)FIOPAD_INDEX(FIOPAD_12_DELAY_OFFSET)
#define FIOPAD_AN51_DELAY (FPinIndex)FIOPAD_INDEX(FIOPAD_13_DELAY_OFFSET)
#define FIOPAD_AR51_DELAY (FPinIndex)FIOPAD_INDEX(FIOPAD_14_DELAY_OFFSET)
#define FIOPAD_AJ57_DELAY (FPinIndex)FIOPAD_INDEX(FIOPAD_23_DELAY_OFFSET)
#define FIOPAD_AG59_DELAY (FPinIndex)FIOPAD_INDEX(FIOPAD_24_DELAY_OFFSET)
#define FIOPAD_AG57_DELAY (FPinIndex)FIOPAD_INDEX(FIOPAD_25_DELAY_OFFSET)
#define FIOPAD_AE59_DELAY (FPinIndex)FIOPAD_INDEX(FIOPAD_26_DELAY_OFFSET)
#define FIOPAD_BA55_DELAY (FPinIndex)FIOPAD_INDEX(FIOPAD_32_DELAY_OFFSET)
#define FIOPAD_BA53_DELAY (FPinIndex)FIOPAD_INDEX(FIOPAD_33_DELAY_OFFSET)
#define FIOPAD_AR59_DELAY (FPinIndex)FIOPAD_INDEX(FIOPAD_34_DELAY_OFFSET)
#define FIOPAD_AU59_DELAY (FPinIndex)FIOPAD_INDEX(FIOPAD_35_DELAY_OFFSET)
#define FIOPAD_A45_DELAY (FPinIndex)FIOPAD_INDEX(FIOPAD_55_DELAY_OFFSET)
#define FIOPAD_C45_DELAY (FPinIndex)FIOPAD_INDEX(FIOPAD_56_DELAY_OFFSET)
#define FIOPAD_A47_DELAY (FPinIndex)FIOPAD_INDEX(FIOPAD_57_DELAY_OFFSET)
#define FIOPAD_A49_DELAY (FPinIndex)FIOPAD_INDEX(FIOPAD_58_DELAY_OFFSET)
#define FIOPAD_C49_DELAY (FPinIndex)FIOPAD_INDEX(FIOPAD_59_DELAY_OFFSET)
#define FIOPAD_A51_DELAY (FPinIndex)FIOPAD_INDEX(FIOPAD_60_DELAY_OFFSET)
#define FIOPAD_A33_DELAY (FPinIndex)FIOPAD_INDEX(FIOPAD_61_DELAY_OFFSET)
#define FIOPAD_C33_DELAY (FPinIndex)FIOPAD_INDEX(FIOPAD_62_DELAY_OFFSET)
#define FIOPAD_C31_DELAY (FPinIndex)FIOPAD_INDEX(FIOPAD_63_DELAY_OFFSET)
#define FIOPAD_A31_DELAY (FPinIndex)FIOPAD_INDEX(FIOPAD_64_DELAY_OFFSET)
#define FIOPAD_AJ53_DELAY (FPinIndex)FIOPAD_INDEX(FIOPAD_65_DELAY_OFFSET)
#define FIOPAD_AL49_DELAY (FPinIndex)FIOPAD_INDEX(FIOPAD_66_DELAY_OFFSET)
#define FIOPAD_AL47_DELAY (FPinIndex)FIOPAD_INDEX(FIOPAD_67_DELAY_OFFSET)
#define FIOPAD_AN49_DELAY (FPinIndex)FIOPAD_INDEX(FIOPAD_68_DELAY_OFFSET)
#define FIOPAD_AG51_DELAY (FPinIndex)FIOPAD_INDEX(FIOPAD_148_DELAY_OFFSET)
#define FIOPAD_AJ51_DELAY (FPinIndex)FIOPAD_INDEX(FIOPAD_69_DELAY_OFFSET)
#define FIOPAD_AG49_DELAY (FPinIndex)FIOPAD_INDEX(FIOPAD_70_DELAY_OFFSET)
#define FIOPAD_AE55_DELAY (FPinIndex)FIOPAD_INDEX(FIOPAD_71_DELAY_OFFSET)
#define FIOPAD_AE53_DELAY (FPinIndex)FIOPAD_INDEX(FIOPAD_72_DELAY_OFFSET)
#define FIOPAD_AG55_DELAY (FPinIndex)FIOPAD_INDEX(FIOPAD_73_DELAY_OFFSET)
#define FIOPAD_AJ49_DELAY (FPinIndex)FIOPAD_INDEX(FIOPAD_74_DELAY_OFFSET)
#define FIOPAD_AC55_DELAY (FPinIndex)FIOPAD_INDEX(FIOPAD_75_DELAY_OFFSET)
#define FIOPAD_AC53_DELAY (FPinIndex)FIOPAD_INDEX(FIOPAD_76_DELAY_OFFSET)
#define FIOPAD_AE51_DELAY (FPinIndex)FIOPAD_INDEX(FIOPAD_77_DELAY_OFFSET)
#define FIOPAD_W51_DELAY (FPinIndex)FIOPAD_INDEX(FIOPAD_78_DELAY_OFFSET)
#define FIOPAD_W53_DELAY (FPinIndex)FIOPAD_INDEX(FIOPAD_80_DELAY_OFFSET)
#define FIOPAD_U55_DELAY (FPinIndex)FIOPAD_INDEX(FIOPAD_81_DELAY_OFFSET)
#define FIOPAD_U53_DELAY (FPinIndex)FIOPAD_INDEX(FIOPAD_82_DELAY_OFFSET)
#define FIOPAD_AE49_DELAY (FPinIndex)FIOPAD_INDEX(FIOPAD_83_DELAY_OFFSET)
#define FIOPAD_AC49_DELAY (FPinIndex)FIOPAD_INDEX(FIOPAD_84_DELAY_OFFSET)
#define FIOPAD_AE47_DELAY (FPinIndex)FIOPAD_INDEX(FIOPAD_85_DELAY_OFFSET)
#define FIOPAD_AA47_DELAY (FPinIndex)FIOPAD_INDEX(FIOPAD_86_DELAY_OFFSET)
#define FIOPAD_AA49_DELAY (FPinIndex)FIOPAD_INDEX(FIOPAD_87_DELAY_OFFSET)
#define FIOPAD_W49_DELAY (FPinIndex)FIOPAD_INDEX(FIOPAD_88_DELAY_OFFSET)
#define FIOPAD_AA51_DELAY (FPinIndex)FIOPAD_INDEX(FIOPAD_89_DELAY_OFFSET)
#define FIOPAD_U49_DELAY (FPinIndex)FIOPAD_INDEX(FIOPAD_90_DELAY_OFFSET)
#define FIOPAD_J59_DELAY (FPinIndex)FIOPAD_INDEX(FIOPAD_92_DELAY_OFFSET)
#define FIOPAD_L57_DELAY (FPinIndex)FIOPAD_INDEX(FIOPAD_93_DELAY_OFFSET)
#define FIOPAD_C59_DELAY (FPinIndex)FIOPAD_INDEX(FIOPAD_94_DELAY_OFFSET)
#define FIOPAD_E59_DELAY (FPinIndex)FIOPAD_INDEX(FIOPAD_95_DELAY_OFFSET)
#define FIOPAD_J57_DELAY (FPinIndex)FIOPAD_INDEX(FIOPAD_96_DELAY_OFFSET)
#define FIOPAD_L59_DELAY (FPinIndex)FIOPAD_INDEX(FIOPAD_97_DELAY_OFFSET)
#define FIOPAD_N59_DELAY (FPinIndex)FIOPAD_INDEX(FIOPAD_98_DELAY_OFFSET)
#define FIOPAD_E31_DELAY (FPinIndex)FIOPAD_INDEX(FIOPAD_99_DELAY_OFFSET)
#define FIOPAD_G31_DELAY (FPinIndex)FIOPAD_INDEX(FIOPAD_100_DELAY_OFFSET)
#define FIOPAD_N41_DELAY (FPinIndex)FIOPAD_INDEX(FIOPAD_101_DELAY_OFFSET)
#define FIOPAD_N39_DELAY (FPinIndex)FIOPAD_INDEX(FIOPAD_102_DELAY_OFFSET)
#define FIOPAD_J33_DELAY (FPinIndex)FIOPAD_INDEX(FIOPAD_103_DELAY_OFFSET)
#define FIOPAD_N33_DELAY (FPinIndex)FIOPAD_INDEX(FIOPAD_104_DELAY_OFFSET)
#define FIOPAD_L33_DELAY (FPinIndex)FIOPAD_INDEX(FIOPAD_105_DELAY_OFFSET)
#define FIOPAD_N45_DELAY (FPinIndex)FIOPAD_INDEX(FIOPAD_106_DELAY_OFFSET)
#define FIOPAD_N43_DELAY (FPinIndex)FIOPAD_INDEX(FIOPAD_107_DELAY_OFFSET)
#define FIOPAD_L31_DELAY (FPinIndex)FIOPAD_INDEX(FIOPAD_108_DELAY_OFFSET)
#define FIOPAD_J31_DELAY (FPinIndex)FIOPAD_INDEX(FIOPAD_109_DELAY_OFFSET)
#define FIOPAD_J29_DELAY (FPinIndex)FIOPAD_INDEX(FIOPAD_110_DELAY_OFFSET)
#define FIOPAD_E29_DELAY (FPinIndex)FIOPAD_INDEX(FIOPAD_111_DELAY_OFFSET)
#define FIOPAD_G29_DELAY (FPinIndex)FIOPAD_INDEX(FIOPAD_112_DELAY_OFFSET)
#define FIOPAD_J37_DELAY (FPinIndex)FIOPAD_INDEX(FIOPAD_115_DELAY_OFFSET)
#define FIOPAD_J39_DELAY (FPinIndex)FIOPAD_INDEX(FIOPAD_116_DELAY_OFFSET)
#define FIOPAD_G41_DELAY (FPinIndex)FIOPAD_INDEX(FIOPAD_117_DELAY_OFFSET)
#define FIOPAD_E43_DELAY (FPinIndex)FIOPAD_INDEX(FIOPAD_118_DELAY_OFFSET)
#define FIOPAD_L43_DELAY (FPinIndex)FIOPAD_INDEX(FIOPAD_119_DELAY_OFFSET)
#define FIOPAD_C43_DELAY (FPinIndex)FIOPAD_INDEX(FIOPAD_120_DELAY_OFFSET)
#define FIOPAD_E41_DELAY (FPinIndex)FIOPAD_INDEX(FIOPAD_121_DELAY_OFFSET)
#define FIOPAD_L45_DELAY (FPinIndex)FIOPAD_INDEX(FIOPAD_122_DELAY_OFFSET)
#define FIOPAD_J43_DELAY (FPinIndex)FIOPAD_INDEX(FIOPAD_123_DELAY_OFFSET)
#define FIOPAD_J41_DELAY (FPinIndex)FIOPAD_INDEX(FIOPAD_124_DELAY_OFFSET)
#define FIOPAD_L39_DELAY (FPinIndex)FIOPAD_INDEX(FIOPAD_125_DELAY_OFFSET)
#define FIOPAD_E37_DELAY (FPinIndex)FIOPAD_INDEX(FIOPAD_126_DELAY_OFFSET)
#define FIOPAD_E35_DELAY (FPinIndex)FIOPAD_INDEX(FIOPAD_127_DELAY_OFFSET)
#define FIOPAD_G35_DELAY (FPinIndex)FIOPAD_INDEX(FIOPAD_128_DELAY_OFFSET)
#define FIOPAD_L55_DELAY (FPinIndex)FIOPAD_INDEX(FIOPAD_136_DELAY_OFFSET)
#define FIOPAD_J55_DELAY (FPinIndex)FIOPAD_INDEX(FIOPAD_137_DELAY_OFFSET)
#define FIOPAD_J45_DELAY (FPinIndex)FIOPAD_INDEX(FIOPAD_138_DELAY_OFFSET)
#define FIOPAD_E47_DELAY (FPinIndex)FIOPAD_INDEX(FIOPAD_139_DELAY_OFFSET)
#define FIOPAD_G47_DELAY (FPinIndex)FIOPAD_INDEX(FIOPAD_140_DELAY_OFFSET)
#define FIOPAD_J47_DELAY (FPinIndex)FIOPAD_INDEX(FIOPAD_141_DELAY_OFFSET)
#define FIOPAD_J49_DELAY (FPinIndex)FIOPAD_INDEX(FIOPAD_142_DELAY_OFFSET)
#define FIOPAD_N49_DELAY (FPinIndex)FIOPAD_INDEX(FIOPAD_143_DELAY_OFFSET)
#define FIOPAD_L51_DELAY (FPinIndex)FIOPAD_INDEX(FIOPAD_144_DELAY_OFFSET)
#define FIOPAD_L49_DELAY (FPinIndex)FIOPAD_INDEX(FIOPAD_145_DELAY_OFFSET)
#define FIOPAD_N53_DELAY (FPinIndex)FIOPAD_INDEX(FIOPAD_146_DELAY_OFFSET)
#define FIOPAD_J53_DELAY (FPinIndex)FIOPAD_INDEX(FIOPAD_147_DELAY_OFFSET)
/***************** Macros (Inline Functions) Definitions *********************/
/*****************************************************************************/
#ifdef __cplusplus
}
#endif
#endif

609
bsp/phytium/libraries/standalone/board/e2000/q/fiopad_config.c
View File

@ -1,609 +0,0 @@
/*
* Copyright : (C) 2022 Phytium Information Technology, Inc.
* All Rights Reserved.
*
* This program is OPEN SOURCE software: you can redistribute it and/or modify it
* under the terms of the Phytium Public License as published by the Phytium Technology Co.,Ltd,
* either version 1.0 of the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,but WITHOUT ANY WARRANTY;
* without even the implied warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.
* See the Phytium Public License for more details.
*
*
* FilePath: fiopad_config.c
* Date: 2022-02-10 14:53:42
* LastEditTime: 2022-02-18 08:25:29
* Description:  This file is for io-pad function definition
*
* Modify History:
* Ver   Who        Date         Changes
* ----- ------     --------    --------------------------------------
* 1.0 huanghe 2021/11/5 init commit
* 1.1 zhugengyu 2022/3/21 adopt to lastest tech spec.
*/
/***************************** Include Files *********************************/
#include "fiopad.h"
#include "fparameters.h"
#include "fdebug.h"
#include "fpinctrl.h"
#include "fassert.h"
/************************** Constant Definitions *****************************/
/**************************** Type Definitions *******************************/
/***************** Macros (Inline Functions) Definitions *********************/
#define FIOPAD_DEBUG_TAG "FIOPAD-CFG"
#define FIOPAD_ERROR(format, ...) FT_DEBUG_PRINT_E(FIOPAD_DEBUG_TAG, format, ##__VA_ARGS__)
#define FIOPAD_WARN(format, ...) FT_DEBUG_PRINT_W(FIOPAD_DEBUG_TAG, format, ##__VA_ARGS__)
#define FIOPAD_INFO(format, ...) FT_DEBUG_PRINT_I(FIOPAD_DEBUG_TAG, format, ##__VA_ARGS__)
#define FIOPAD_DEBUG(format, ...) FT_DEBUG_PRINT_D(FIOPAD_DEBUG_TAG, format, ##__VA_ARGS__)
/************************** Function Prototypes ******************************/
/*****************************************************************************/
/**
* @name: FIOPadSetSpimMux
* @msg: set iopad mux for spim
* @return {*}
* @param {u32} spim_id, instance id of spi
*/
void FIOPadSetSpimMux(u32 spim_id)
{
if (FSPI0_ID == spim_id)
{
FIOPAD_INFO("%d-%d-%d-%d", FPinGetFunc(FIOPAD_W55),
FPinGetFunc(FIOPAD_W53), FPinGetFunc(FIOPAD_U55),
FPinGetFunc(FIOPAD_U53));
FPinSetFunc(FIOPAD_W55, FPIN_FUNC2); /* sclk */
FPinSetFunc(FIOPAD_W53, FPIN_FUNC2); /* txd */
FPinSetFunc(FIOPAD_U55, FPIN_FUNC2); /* rxd */
FPinSetFunc(FIOPAD_U53, FPIN_FUNC2); /* csn0 */
FIOPAD_INFO("%d-%d-%d-%d", FPinGetFunc(FIOPAD_W55),
FPinGetFunc(FIOPAD_W53), FPinGetFunc(FIOPAD_U55),
FPinGetFunc(FIOPAD_U53));
}
else if (FSPI1_ID == spim_id)
{
FIOPAD_INFO("%d-%d-%d-%d", FPinGetFunc(FIOPAD_N43),
FPinGetFunc(FIOPAD_L31), FPinGetFunc(FIOPAD_J31),
FPinGetFunc(FIOPAD_J29));
FPinSetFunc(FIOPAD_N43, FPIN_FUNC4); /* sclk */
FPinSetFunc(FIOPAD_L31, FPIN_FUNC4); /* txd */
FPinSetFunc(FIOPAD_J31, FPIN_FUNC4); /* rxd */
FPinSetFunc(FIOPAD_J29, FPIN_FUNC4); /* csn0 */
FIOPAD_INFO("%d-%d-%d-%d", FPinGetFunc(FIOPAD_N43),
FPinGetFunc(FIOPAD_L31), FPinGetFunc(FIOPAD_J31),
FPinGetFunc(FIOPAD_J29));
}
else if (FSPI2_ID == spim_id)
{
FPinSetFunc(FIOPAD_A33, FPIN_FUNC0); /* sclk */
FPinSetFunc(FIOPAD_C33, FPIN_FUNC0); /* txd */
FPinSetFunc(FIOPAD_C31, FPIN_FUNC0); /* rxd */
FPinSetFunc(FIOPAD_A31, FPIN_FUNC0); /* csn0 */
}
else if (FSPI3_ID == spim_id)
{
FPinSetFunc(FIOPAD_AC55, FPIN_FUNC2); /* sclk */
FPinSetFunc(FIOPAD_AC53, FPIN_FUNC2); /* txd */
FPinSetFunc(FIOPAD_AE51, FPIN_FUNC2); /* rxd */
FPinSetFunc(FIOPAD_W51, FPIN_FUNC2); /* csn0 */
}
}
static void FIOPadDumpGpioPin(FPinIndex pin, u32 gpio_id, u32 pin_id)
{
FPinFunc func = FPIN_FUNC0;
FPinPull pull = FPIN_PULL_NONE;
FPinDrive drive = FPIN_DRV0;
FPinGetConfig(pin, &func, &pull, &drive);
FIOPAD_DEBUG("GPIO-%d-%d: func: %d, pull: %d, drive: %d",
gpio_id, pin_id, func, pull, drive);
}
/**
* @name: FIOPadSetGpioMux
* @msg: set iopad mux for gpio
* @return {*}
* @param {u32} gpio_id, instance id of gpio
* @param {u32} pin_id, index of pin
*/
void FIOPadSetGpioMux(u32 gpio_id, u32 pin_id)
{
if (FGPIO2_ID == gpio_id)
{
switch (pin_id)
{
case 11: /* gpio 2-a-11 */
FPinSetFunc(FIOPAD_N49, FPIN_FUNC0);
break;
case 12: /* gpio 2-a-12 */
FPinSetFunc(FIOPAD_L51, FPIN_FUNC0);
break;
case 13: /* gpio 2-a-13 */
FPinSetFunc(FIOPAD_L49, FPIN_FUNC0);
break;
case 14: /* gpio 2-a-14 */
FPinSetFunc(FIOPAD_N53, FPIN_FUNC0);
break;
case 15: /* gpio 2-a-15 */
FPinSetFunc(FIOPAD_J53, FPIN_FUNC0);
break;
}
}
else if (FGPIO3_ID == gpio_id)
{
switch (pin_id)
{
case 3: /* gpio 3-a-3 */
FPinSetFunc(FIOPAD_A33, FPIN_FUNC6);
break;
case 4: /* gpio 3-a-4 */
FPinSetFunc(FIOPAD_C33, FPIN_FUNC6);
break;
case 5: /* gpio 3-a-5 */
FPinSetFunc(FIOPAD_C31, FPIN_FUNC6);
break;
case 6: /* gpio 3-a-6 */
FPinSetFunc(FIOPAD_A31, FPIN_FUNC6);
break;
default:
break;
}
}
else if (FGPIO4_ID == gpio_id)
{
switch (pin_id)
{
case 5: /* gpio 4-a-5 */
FPinSetFunc(FIOPAD_W51, FPIN_FUNC6);
break;
case 9: /* gpio 4-a-9 */
FPinSetFunc(FIOPAD_U53, FPIN_FUNC6);
break;
case 10: /* gpio 4-a-10 */
FPinSetFunc(FIOPAD_AE49, FPIN_FUNC6);
break;
case 11: /* gpio 4-a-11 */
FPinSetFunc(FIOPAD_AC49, FPIN_FUNC6);
break;
case 12: /* gpio 4-a-12 */
FPinSetFunc(FIOPAD_AE47, FPIN_FUNC6);
break;
case 13: /* gpio 4-a-13 */
FPinSetFunc(FIOPAD_AA47, FPIN_FUNC6);
break;
default:
break;
}
}
}
/**
* @name: FIOPadSetCanMux
* @msg: set iopad mux for can
* @return {*}
* @param {u32} can_id, instance id of can
*/
void FIOPadSetCanMux(u32 can_id)
{
if (can_id == FCAN0_ID)
{
/* can0 */
FPinSetFunc(FIOPAD_A41, FPIN_FUNC0); /* can0-tx: func 0 */
FPinSetFunc(FIOPAD_A43, FPIN_FUNC0); /* can0-rx: func 0 */
}
else if (can_id == FCAN1_ID)
{
/* can1 */
FPinSetFunc(FIOPAD_A45, FPIN_FUNC0); /* can1-tx: func 0 */
FPinSetFunc(FIOPAD_C45, FPIN_FUNC0); /* can1-rx: func 0 */
}
else
{
FIOPAD_ERROR("can id is error.\r\n");
}
}
/**
* @name: FIOPadSetQspiMux
* @msg: set iopad mux for qspi
* @return {*}
* @param {u32} qspi_id, id of qspi instance
* @param {u32} cs_id, id of qspi cs
*/
void FIOPadSetQspiMux(u32 qspi_id, u32 cs_id)
{
if (qspi_id == FQSPI0_ID)
{
/* add sck, io0-io3 iopad multiplex */
}
if (cs_id == FQSPI_CS_0)
{
FPinSetFunc(FIOPAD_AR55, FPIN_FUNC0);
}
else if (cs_id == FQSPI_CS_1)
{
FPinSetFunc(FIOPAD_AR49, FPIN_FUNC0);
}
else if (cs_id == FQSPI_CS_2)
{
FPinSetFunc(FIOPAD_C37, FPIN_FUNC5);
}
else if (cs_id == FQSPI_CS_3)
{
FPinSetFunc(FIOPAD_A37, FPIN_FUNC5);
}
else
{
FIOPAD_ERROR("can id is error.\r\n");
}
}
/**
* @name: FIOPadSetPwmMux
* @msg: set iopad mux for pwm
* @return {*}
* @param {u32} pwm_id, id of pwm instance
* @param {u32} pwm_channel, channel of pwm instance
*/
void FIOPadSetPwmMux(u32 pwm_id, u32 pwm_channel)
{
FASSERT(pwm_id < FPWM_NUM);
FASSERT(pwm_channel < FPWM_CHANNEL_NUM);
switch (pwm_id)
{
case FPWM0_ID:
if (pwm_channel == 0)
{
FPinSetFunc(FIOPAD_AL59, FPIN_FUNC1); /* PWM0_OUT: func 1 */
}
if (pwm_channel == 1)
{
FPinSetFunc(FIOPAD_AJ57, FPIN_FUNC1); /* PWM1_OUT: func 1 */
}
break;
case FPWM1_ID:
if (pwm_channel == 0)
{
FPinSetFunc(FIOPAD_AG57, FPIN_FUNC1); /* PWM2_OUT: func 1 */
}
if (pwm_channel == 1)
{
FPinSetFunc(FIOPAD_AC59, FPIN_FUNC1); /* PWM3_OUT: func 1 */
}
break;
case FPWM2_ID:
if (pwm_channel == 0)
{
FPinSetFunc(FIOPAD_BA55, FPIN_FUNC1); /* PWM4_OUT: func 1 */
}
if (pwm_channel == 1)
{
FPinSetFunc(FIOPAD_C39, FPIN_FUNC2); /* PWM5_OUT: func 2 */
}
break;
case FPWM3_ID:
if (pwm_channel == 0)
{
FPinSetFunc(FIOPAD_A37, FPIN_FUNC2); /* PWM6_OUT: func 2 */
}
if (pwm_channel == 1)
{
FPinSetFunc(FIOPAD_A43, FPIN_FUNC2); /* PWM7_OUT: func 2 */
}
break;
case FPWM4_ID:
if (pwm_channel == 0)
{
FPinSetFunc(FIOPAD_C45, FPIN_FUNC2); /* PWM8_OUT: func 2 */
}
if (pwm_channel == 1)
{
FPinSetFunc(FIOPAD_A49, FPIN_FUNC2); /* PWM9_OUT: func 2 */
}
break;
case FPWM5_ID:
if (pwm_channel == 0)
{
FPinSetFunc(FIOPAD_A51, FPIN_FUNC2); /* PWM10_OUT: func 2 */
}
if (pwm_channel == 1)
{
FPinSetFunc(FIOPAD_C33, FPIN_FUNC2); /* PWM11_OUT: func 2 */
}
break;
case FPWM6_ID:
if (pwm_channel == 0)
{
FPinSetFunc(FIOPAD_A31, FPIN_FUNC2); /* PWM12_OUT: func 2 */
}
if (pwm_channel == 1)
{
FPinSetFunc(FIOPAD_J39, FPIN_FUNC3); /* PWM13_OUT: func 3 */
}
break;
case FPWM7_ID:
if (pwm_channel == 0)
{
FPinSetFunc(FIOPAD_E43, FPIN_FUNC3); /* PWM14_OUT: func 3 */
}
if (pwm_channel == 1)
{
FPinSetFunc(FIOPAD_C43, FPIN_FUNC3); /* PWM15_OUT: func 3 */
}
break;
default:
FIOPAD_ERROR("pwm id is error.\r\n");
break;
}
}
/**
* @name: FIOPadSetAdcMux
* @msg: set iopad mux for adc
* @return {*}
* @param {u32} adc_id, id of adc instance
* @param {u32} adc_channel, id of adc channel
*/
void FIOPadSetAdcMux(u32 adc_id, u32 adc_channel)
{
if (adc_id == FADC0_ID)
{
switch (adc_channel)
{
case FADC_CHANNEL_0:
FPinSetFunc(FIOPAD_R51, FPIN_FUNC7); /* adc0-0: func 7 */
break;
case FADC_CHANNEL_1:
FPinSetFunc(FIOPAD_R49, FPIN_FUNC7); /* adc0-1: func 7 */
break;
case FADC_CHANNEL_2:
FPinSetFunc(FIOPAD_N51, FPIN_FUNC7); /* adc0-2: func 7 */
break;
case FADC_CHANNEL_3:
FPinSetFunc(FIOPAD_N55, FPIN_FUNC7); /* adc0-3: func 7 */
break;
case FADC_CHANNEL_4:
FPinSetFunc(FIOPAD_L55, FPIN_FUNC7); /* adc0-4: func 7 */
break;
case FADC_CHANNEL_5:
FPinSetFunc(FIOPAD_J55, FPIN_FUNC7); /* adc0-5: func 7 */
break;
case FADC_CHANNEL_6:
FPinSetFunc(FIOPAD_J45, FPIN_FUNC7); /* adc0-6: func 7 */
break;
case FADC_CHANNEL_7:
FPinSetFunc(FIOPAD_E47, FPIN_FUNC7); /* adc0-7: func 7 */
break;
default:
FIOPAD_ERROR("adc %d channel %d is error.\r\n", adc_id, adc_channel);
break;
}
}
else
{
FIOPAD_ERROR("adc %d channel %d is error.\r\n", adc_id, adc_channel);
}
}
/**
* @name: FIOPadSetMioMux
* @msg: set iopad mux for mio
* @return {*}
* @param {u32} mio_id, instance id of i2c
*/
void FIOPadSetMioMux(u32 mio_id)
{
switch (mio_id)
{
case FMIO0_ID:
{
FPinSetFunc(FIOPAD_A41, FPIN_FUNC5); /* scl */
FPinSetFunc(FIOPAD_A43, FPIN_FUNC5); /* sda */
}
break;
case FMIO1_ID:
{
FPinSetFunc(FIOPAD_A45, FPIN_FUNC5); /* scl */
FPinSetFunc(FIOPAD_C45, FPIN_FUNC5); /* sda */
}
break;
case FMIO2_ID:
{
FPinSetFunc(FIOPAD_A47, FPIN_FUNC5); /* scl */
FPinSetFunc(FIOPAD_A49, FPIN_FUNC5); /* sda */
}
break;
case FMIO3_ID:
{
FPinSetFunc(FIOPAD_BA55, FPIN_FUNC4); /* scl */
FPinSetFunc(FIOPAD_BA53, FPIN_FUNC4); /* sda */
}
break;
case FMIO4_ID:
{
FPinSetFunc(FIOPAD_R59, FPIN_FUNC4); /* scl */
FPinSetFunc(FIOPAD_U59, FPIN_FUNC4); /* sda */
}
break;
case FMIO5_ID:
{
FPinSetFunc(FIOPAD_W49, FPIN_FUNC4); /* scl */
FPinSetFunc(FIOPAD_U57, FPIN_FUNC4); /* sda */
}
break;
case FMIO6_ID:
{
FPinSetFunc(FIOPAD_AA57, FPIN_FUNC4); /* scl */
FPinSetFunc(FIOPAD_AA59, FPIN_FUNC4); /* sda */
}
break;
case FMIO7_ID:
{
FPinSetFunc(FIOPAD_A39, FPIN_FUNC4); /* scl */
FPinSetFunc(FIOPAD_C39, FPIN_FUNC4); /* sda */
}
break;
case FMIO8_ID:
{
FPinSetFunc(FIOPAD_AA49, FPIN_FUNC4); /* scl */
FPinSetFunc(FIOPAD_W49, FPIN_FUNC4); /* sda */
}
break;
case FMIO9_ID:
{
FPinSetFunc(FIOPAD_AA51, FPIN_FUNC4); /* scl */
FPinSetFunc(FIOPAD_U49, FPIN_FUNC4); /* sda */
}
break;
case FMIO10_ID:
{
FPinSetFunc(FIOPAD_C49, FPIN_FUNC5); /* scl */
FPinSetFunc(FIOPAD_A51, FPIN_FUNC5); /* sda */
}
break;
case FMIO11_ID:
{
FPinSetFunc(FIOPAD_N27, FPIN_FUNC3); /* scl */
FPinSetFunc(FIOPAD_L29, FPIN_FUNC3); /* sda */
}
break;
case FMIO12_ID:
{
FPinSetFunc(FIOPAD_E41, FPIN_FUNC3); /* scl */
FPinSetFunc(FIOPAD_L45, FPIN_FUNC3); /* sda */
}
break;
case FMIO13_ID:
{
FPinSetFunc(FIOPAD_J49, FPIN_FUNC6); /* scl */
FPinSetFunc(FIOPAD_N49, FPIN_FUNC6); /* sda */
}
break;
case FMIO14_ID:
{
FPinSetFunc(FIOPAD_L51, FPIN_FUNC6); /* scl */
FPinSetFunc(FIOPAD_L49, FPIN_FUNC6); /* sda */
}
break;
case FMIO15_ID:
{
FPinSetFunc(FIOPAD_N53, FPIN_FUNC6); /* scl */
FPinSetFunc(FIOPAD_J53, FPIN_FUNC6); /* sda */
}
break;
default:
break;
}
}
/**
* @name: FIOPadSetTachoMux
* @msg: set iopad mux for pwm_in
* @return {*}
* @param {u32} pwm_in_id, instance id of tacho
*/
void FIOPadSetTachoMux(u32 pwm_in_id)
{
switch (pwm_in_id)
{
case FTACHO0_ID:
FPinSetFunc(FIOPAD_AN57, FPIN_FUNC1);
break;
case FTACHO1_ID:
FPinSetFunc(FIOPAD_AJ59, FPIN_FUNC1);
break;
case FTACHO2_ID:
FPinSetFunc(FIOPAD_AG59, FPIN_FUNC1);
break;
case FTACHO3_ID:
FPinSetFunc(FIOPAD_AE59, FPIN_FUNC1);
break;
case FTACHO4_ID:
FPinSetFunc(FIOPAD_AC57, FPIN_FUNC1);
break;
case FTACHO5_ID:
FPinSetFunc(FIOPAD_BA53, FPIN_FUNC1);
break;
case FTACHO6_ID:
FPinSetFunc(FIOPAD_C37, FPIN_FUNC2);
break;
case FTACHO7_ID:
FPinSetFunc(FIOPAD_A41, FPIN_FUNC2);
break;
case FTACHO8_ID:
FPinSetFunc(FIOPAD_A45, FPIN_FUNC2);
break;
case FTACHO9_ID:
FPinSetFunc(FIOPAD_A47, FPIN_FUNC2);
break;
case FTACHO10_ID:
FPinSetFunc(FIOPAD_C49, FPIN_FUNC2);
break;
case FTACHO11_ID:
FPinSetFunc(FIOPAD_A33, FPIN_FUNC2);
break;
case FTACHO12_ID:
FPinSetFunc(FIOPAD_C31, FPIN_FUNC2);
break;
case FTACHO13_ID:
FPinSetFunc(FIOPAD_AA49, FPIN_FUNC2);
break;
case FTACHO14_ID:
FPinSetFunc(FIOPAD_AA51, FPIN_FUNC2);
break;
case FTACHO15_ID:
FPinSetFunc(FIOPAD_G59, FPIN_FUNC2);
break;
default:
break;
}
}
/**
* @name: FIOPadSetUartMux
* @msg: set iopad mux for uart
* @return {*}
* @param {u32} uart_id, instance id of uart
*/
void FIOPadSetUartMux(u32 uart_id)
{
switch (uart_id)
{
case FUART0_ID:
FPinSetFunc(FIOPAD_J37, FPIN_FUNC4);
FPinSetFunc(FIOPAD_J39, FPIN_FUNC4);
break;
case FUART1_ID:
FPinSetFunc(FIOPAD_AW51, FPIN_FUNC0);
FPinSetFunc(FIOPAD_AU51, FPIN_FUNC0);
break;
case FUART2_ID:
FPinSetFunc(FIOPAD_A47, FPIN_FUNC0);
FPinSetFunc(FIOPAD_A49, FPIN_FUNC0);
break;
case FUART3_ID:
FPinSetFunc(FIOPAD_L37, FPIN_FUNC2);
FPinSetFunc(FIOPAD_N35, FPIN_FUNC2);
break;
default:
break;
}
}

247
bsp/phytium/libraries/standalone/board/e2000/q/fparameters.h
View File

@ -37,10 +37,257 @@ extern "C"
#define CORE1_AFF 0x100U
#define CORE2_AFF 0x200U
#define CORE3_AFF 0x201U
#define FCORE_NUM 4
#define FT_CPUS_NR 4U
/*****************************************************************************/
/* register offset of iopad function / pull / driver strength */
#define FIOPAD_AN59_REG0_OFFSET 0x0000U
#define FIOPAD_AW47_REG0_OFFSET 0x0004U
#define FIOPAD_AR55_REG0_OFFSET 0x0020U
#define FIOPAD_AJ55_REG0_OFFSET 0x0024U
#define FIOPAD_AL55_REG0_OFFSET 0x0028U
#define FIOPAD_AL53_REG0_OFFSET 0x002CU
#define FIOPAD_AN51_REG0_OFFSET 0x0030U
#define FIOPAD_AR51_REG0_OFFSET 0x0034U
#define FIOPAD_BA57_REG0_OFFSET 0x0038U
#define FIOPAD_BA59_REG0_OFFSET 0x003CU
#define FIOPAD_AW57_REG0_OFFSET 0x0040U
#define FIOPAD_AW59_REG0_OFFSET 0x0044U
#define FIOPAD_AU55_REG0_OFFSET 0x0048U
#define FIOPAD_AN57_REG0_OFFSET 0x004CU
#define FIOPAD_AL59_REG0_OFFSET 0x0050U
#define FIOPAD_AJ59_REG0_OFFSET 0x0054U
#define FIOPAD_AJ57_REG0_OFFSET 0x0058U
#define FIOPAD_AG59_REG0_OFFSET 0x005CU
#define FIOPAD_AG57_REG0_OFFSET 0x0060U
#define FIOPAD_AE59_REG0_OFFSET 0x0064U
#define FIOPAD_AC59_REG0_OFFSET 0x0068U
#define FIOPAD_AC57_REG0_OFFSET 0x006CU
#define FIOPAD_AR49_REG0_OFFSET 0x0070U
#define FIOPAD_BA55_REG0_OFFSET 0x0074U
#define FIOPAD_BA53_REG0_OFFSET 0x0078U
#define FIOPAD_AR59_REG0_OFFSET 0x007CU
#define FIOPAD_AU59_REG0_OFFSET 0x0080U
#define FIOPAD_AR57_REG0_OFFSET 0x0084U
#define FIOPAD_BA49_REG0_OFFSET 0x0088U
#define FIOPAD_AW55_REG0_OFFSET 0x008CU
#define FIOPAD_A35_REG0_OFFSET 0x0090U
#define FIOPAD_R57_REG0_OFFSET 0x0094U
#define FIOPAD_R59_REG0_OFFSET 0x0098U
#define FIOPAD_U59_REG0_OFFSET 0x009CU
#define FIOPAD_W59_REG0_OFFSET 0x00A0U
#define FIOPAD_U57_REG0_OFFSET 0x00A4U
#define FIOPAD_AA57_REG0_OFFSET 0x00A8U
#define FIOPAD_AA59_REG0_OFFSET 0x00ACU
#define FIOPAD_AW51_REG0_OFFSET 0x00B0U
#define FIOPAD_AU51_REG0_OFFSET 0x00B4U
#define FIOPAD_A39_REG0_OFFSET 0x00B8U
#define FIOPAD_C39_REG0_OFFSET 0x00BCU
#define FIOPAD_C37_REG0_OFFSET 0x00C0U
#define FIOPAD_A37_REG0_OFFSET 0x00C4U
#define FIOPAD_A41_REG0_OFFSET 0x00C8U
#define FIOPAD_A43_REG0_OFFSET 0x00CCU
#define FIOPAD_A45_REG0_OFFSET 0x00D0U
#define FIOPAD_C45_REG0_OFFSET 0x00D4U
#define FIOPAD_A47_REG0_OFFSET 0x00D8U
#define FIOPAD_A49_REG0_OFFSET 0x00DCU
#define FIOPAD_C49_REG0_OFFSET 0x00E0U
#define FIOPAD_A51_REG0_OFFSET 0x00E4U
#define FIOPAD_A33_REG0_OFFSET 0x00E8U
#define FIOPAD_C33_REG0_OFFSET 0x00ECU
#define FIOPAD_C31_REG0_OFFSET 0x00F0U
#define FIOPAD_A31_REG0_OFFSET 0x00F4U
#define FIOPAD_AJ53_REG0_OFFSET 0x00F8U
#define FIOPAD_AL49_REG0_OFFSET 0x00FCU
#define FIOPAD_AL47_REG0_OFFSET 0x0100U
#define FIOPAD_AN49_REG0_OFFSET 0x0104U
#define FIOPAD_AG51_REG0_OFFSET 0x0108U
#define FIOPAD_AJ51_REG0_OFFSET 0x010CU
#define FIOPAD_AG49_REG0_OFFSET 0x0110U
#define FIOPAD_AE55_REG0_OFFSET 0x0114U
#define FIOPAD_AE53_REG0_OFFSET 0x0118U
#define FIOPAD_AG55_REG0_OFFSET 0x011CU
#define FIOPAD_AJ49_REG0_OFFSET 0x0120U
#define FIOPAD_AC55_REG0_OFFSET 0x0124U
#define FIOPAD_AC53_REG0_OFFSET 0x0128U
#define FIOPAD_AE51_REG0_OFFSET 0x012CU
#define FIOPAD_W51_REG0_OFFSET 0x0130U
#define FIOPAD_W55_REG0_OFFSET 0x0134U
#define FIOPAD_W53_REG0_OFFSET 0x0138U
#define FIOPAD_U55_REG0_OFFSET 0x013CU
#define FIOPAD_U53_REG0_OFFSET 0x0140U
#define FIOPAD_AE49_REG0_OFFSET 0x0144U
#define FIOPAD_AC49_REG0_OFFSET 0x0148U
#define FIOPAD_AE47_REG0_OFFSET 0x014CU
#define FIOPAD_AA47_REG0_OFFSET 0x0150U
#define FIOPAD_AA49_REG0_OFFSET 0x0154U
#define FIOPAD_W49_REG0_OFFSET 0x0158U
#define FIOPAD_AA51_REG0_OFFSET 0x015CU
#define FIOPAD_U49_REG0_OFFSET 0x0160U
#define FIOPAD_G59_REG0_OFFSET 0x0164U
#define FIOPAD_J59_REG0_OFFSET 0x0168U
#define FIOPAD_L57_REG0_OFFSET 0x016CU
#define FIOPAD_C59_REG0_OFFSET 0x0170U
#define FIOPAD_E59_REG0_OFFSET 0x0174U
#define FIOPAD_J57_REG0_OFFSET 0x0178U
#define FIOPAD_L59_REG0_OFFSET 0x017CU
#define FIOPAD_N59_REG0_OFFSET 0x0180U
#define FIOPAD_C57_REG0_OFFSET 0x0184U
#define FIOPAD_E57_REG0_OFFSET 0x0188U
#define FIOPAD_E31_REG0_OFFSET 0x018CU
#define FIOPAD_G31_REG0_OFFSET 0x0190U
#define FIOPAD_N41_REG0_OFFSET 0x0194U
#define FIOPAD_N39_REG0_OFFSET 0x0198U
#define FIOPAD_J33_REG0_OFFSET 0x019CU
#define FIOPAD_N33_REG0_OFFSET 0x01A0U
#define FIOPAD_L33_REG0_OFFSET 0x01A4U
#define FIOPAD_N45_REG0_OFFSET 0x01A8U
#define FIOPAD_N43_REG0_OFFSET 0x01ACU
#define FIOPAD_L31_REG0_OFFSET 0x01B0U
#define FIOPAD_J31_REG0_OFFSET 0x01B4U
#define FIOPAD_J29_REG0_OFFSET 0x01B8U
#define FIOPAD_E29_REG0_OFFSET 0x01BCU
#define FIOPAD_G29_REG0_OFFSET 0x01C0U
#define FIOPAD_N27_REG0_OFFSET 0x01C4U
#define FIOPAD_L29_REG0_OFFSET 0x01C8U
#define FIOPAD_J37_REG0_OFFSET 0x01CCU
#define FIOPAD_J39_REG0_OFFSET 0x01D0U
#define FIOPAD_G41_REG0_OFFSET 0x01D4U
#define FIOPAD_E43_REG0_OFFSET 0x01D8U
#define FIOPAD_L43_REG0_OFFSET 0x01DCU
#define FIOPAD_C43_REG0_OFFSET 0x01E0U
#define FIOPAD_E41_REG0_OFFSET 0x01E4U
#define FIOPAD_L45_REG0_OFFSET 0x01E8U
#define FIOPAD_J43_REG0_OFFSET 0x01ECU
#define FIOPAD_J41_REG0_OFFSET 0x01F0U
#define FIOPAD_L39_REG0_OFFSET 0x01F4U
#define FIOPAD_E37_REG0_OFFSET 0x01F8U
#define FIOPAD_E35_REG0_OFFSET 0x01FCU
#define FIOPAD_G35_REG0_OFFSET 0x0200U
#define FIOPAD_J35_REG0_OFFSET 0x0204U
#define FIOPAD_L37_REG0_OFFSET 0x0208U
#define FIOPAD_N35_REG0_OFFSET 0x020CU
#define FIOPAD_R51_REG0_OFFSET 0x0210U
#define FIOPAD_R49_REG0_OFFSET 0x0214U
#define FIOPAD_N51_REG0_OFFSET 0x0218U
#define FIOPAD_N55_REG0_OFFSET 0x021CU
#define FIOPAD_L55_REG0_OFFSET 0x0220U
#define FIOPAD_J55_REG0_OFFSET 0x0224U
#define FIOPAD_J45_REG0_OFFSET 0x0228U
#define FIOPAD_E47_REG0_OFFSET 0x022CU
#define FIOPAD_G47_REG0_OFFSET 0x0230U
#define FIOPAD_J47_REG0_OFFSET 0x0234U
#define FIOPAD_J49_REG0_OFFSET 0x0238U
#define FIOPAD_N49_REG0_OFFSET 0x023CU
#define FIOPAD_L51_REG0_OFFSET 0x0240U
#define FIOPAD_L49_REG0_OFFSET 0x0244U
#define FIOPAD_N53_REG0_OFFSET 0x0248U
#define FIOPAD_J53_REG0_OFFSET 0x024CU
#define FIOPAD_REG0_BEG_OFFSET FIOPAD_AN59_REG0_OFFSET
#define FIOPAD_REG0_END_OFFSET FIOPAD_J53_REG0_OFFSET
/* register offset of iopad delay */
#define FIOPAD_AJ55_REG1_OFFSET 0x1024U
#define FIOPAD_AL55_REG1_OFFSET 0x1028U
#define FIOPAD_AL53_REG1_OFFSET 0x102CU
#define FIOPAD_AN51_REG1_OFFSET 0x1030U
#define FIOPAD_AR51_REG1_OFFSET 0x1034U
#define FIOPAD_AJ57_REG1_OFFSET 0x1058U
#define FIOPAD_AG59_REG1_OFFSET 0x105CU
#define FIOPAD_AG57_REG1_OFFSET 0x1060U
#define FIOPAD_AE59_REG1_OFFSET 0x1064U
#define FIOPAD_BA55_REG1_OFFSET 0x1074U
#define FIOPAD_BA53_REG1_OFFSET 0x1078U
#define FIOPAD_AR59_REG1_OFFSET 0x107CU
#define FIOPAD_AU59_REG1_OFFSET 0x1080U
#define FIOPAD_A45_REG1_OFFSET 0x10D0U
#define FIOPAD_C45_REG1_OFFSET 0x10D4U
#define FIOPAD_A47_REG1_OFFSET 0x10D8U
#define FIOPAD_A49_REG1_OFFSET 0x10DCU
#define FIOPAD_C49_REG1_OFFSET 0x10E0U
#define FIOPAD_A51_REG1_OFFSET 0x10E4U
#define FIOPAD_A33_REG1_OFFSET 0x10E8U
#define FIOPAD_C33_REG1_OFFSET 0x10ECU
#define FIOPAD_C31_REG1_OFFSET 0x10F0U
#define FIOPAD_A31_REG1_OFFSET 0x10F4U
#define FIOPAD_AJ53_REG1_OFFSET 0x10F8U
#define FIOPAD_AL49_REG1_OFFSET 0x10FCU
#define FIOPAD_AL47_REG1_OFFSET 0x1100U
#define FIOPAD_AN49_REG1_OFFSET 0x1104U
#define FIOPAD_AG51_REG1_OFFSET 0x1108U
#define FIOPAD_AJ51_REG1_OFFSET 0x110CU
#define FIOPAD_AG49_REG1_OFFSET 0x1110U
#define FIOPAD_AE55_REG1_OFFSET 0x1114U
#define FIOPAD_AE53_REG1_OFFSET 0x1118U
#define FIOPAD_AG55_REG1_OFFSET 0x111CU
#define FIOPAD_AJ49_REG1_OFFSET 0x1120U
#define FIOPAD_AC55_REG1_OFFSET 0x1124U
#define FIOPAD_AC53_REG1_OFFSET 0x1128U
#define FIOPAD_AE51_REG1_OFFSET 0x112CU
#define FIOPAD_W51_REG1_OFFSET 0x1130U
#define FIOPAD_W53_REG1_OFFSET 0x1138U
#define FIOPAD_U55_REG1_OFFSET 0x113CU
#define FIOPAD_U53_REG1_OFFSET 0x1140U
#define FIOPAD_AE49_REG1_OFFSET 0x1144U
#define FIOPAD_AC49_REG1_OFFSET 0x1148U
#define FIOPAD_AE47_REG1_OFFSET 0x114CU
#define FIOPAD_AA47_REG1_OFFSET 0x1150U
#define FIOPAD_AA49_REG1_OFFSET 0x1154U
#define FIOPAD_W49_REG1_OFFSET 0x1158U
#define FIOPAD_AA51_REG1_OFFSET 0x115CU
#define FIOPAD_U49_REG1_OFFSET 0x1160U
#define FIOPAD_J59_REG1_OFFSET 0x1168U
#define FIOPAD_L57_REG1_OFFSET 0x116CU
#define FIOPAD_C59_REG1_OFFSET 0x1170U
#define FIOPAD_E59_REG1_OFFSET 0x1174U
#define FIOPAD_J57_REG1_OFFSET 0x1178U
#define FIOPAD_L59_REG1_OFFSET 0x117CU
#define FIOPAD_N59_REG1_OFFSET 0x1180U
#define FIOPAD_E31_REG1_OFFSET 0x118CU
#define FIOPAD_G31_REG1_OFFSET 0x1190U
#define FIOPAD_N41_REG1_OFFSET 0x1194U
#define FIOPAD_N39_REG1_OFFSET 0x1198U
#define FIOPAD_J33_REG1_OFFSET 0x119CU
#define FIOPAD_N33_REG1_OFFSET 0x11A0U
#define FIOPAD_L33_REG1_OFFSET 0x11A4U
#define FIOPAD_N45_REG1_OFFSET 0x11A8U
#define FIOPAD_N43_REG1_OFFSET 0x11ACU
#define FIOPAD_L31_REG1_OFFSET 0x11B0U
#define FIOPAD_J31_REG1_OFFSET 0x11B4U
#define FIOPAD_J29_REG1_OFFSET 0x11B8U
#define FIOPAD_E29_REG1_OFFSET 0x11BCU
#define FIOPAD_G29_REG1_OFFSET 0x11C0U
#define FIOPAD_J37_REG1_OFFSET 0x11CCU
#define FIOPAD_J39_REG1_OFFSET 0x11D0U
#define FIOPAD_G41_REG1_OFFSET 0x11D4U
#define FIOPAD_E43_REG1_OFFSET 0x11D8U
#define FIOPAD_L43_REG1_OFFSET 0x11DCU
#define FIOPAD_C43_REG1_OFFSET 0x11E0U
#define FIOPAD_E41_REG1_OFFSET 0x11E4U
#define FIOPAD_L45_REG1_OFFSET 0x11E8U
#define FIOPAD_J43_REG1_OFFSET 0x11ECU
#define FIOPAD_J41_REG1_OFFSET 0x11F0U
#define FIOPAD_L39_REG1_OFFSET 0x11F4U
#define FIOPAD_E37_REG1_OFFSET 0x11F8U
#define FIOPAD_E35_REG1_OFFSET 0x11FCU
#define FIOPAD_G35_REG1_OFFSET 0x1200U
#define FIOPAD_L55_REG1_OFFSET 0x1220U
#define FIOPAD_J55_REG1_OFFSET 0x1224U
#define FIOPAD_J45_REG1_OFFSET 0x1228U
#define FIOPAD_E47_REG1_OFFSET 0x122CU
#define FIOPAD_G47_REG1_OFFSET 0x1230U
#define FIOPAD_J47_REG1_OFFSET 0x1234U
#define FIOPAD_J49_REG1_OFFSET 0x1238U
#define FIOPAD_N49_REG1_OFFSET 0x123CU
#define FIOPAD_L51_REG1_OFFSET 0x1240U
#define FIOPAD_L49_REG1_OFFSET 0x1244U
#define FIOPAD_N53_REG1_OFFSET 0x1248U
#define FIOPAD_J53_REG1_OFFSET 0x124CU
#define FIOPAD_REG1_BEG_OFFSET FIOPAD_AJ55_REG1_OFFSET
#define FIOPAD_REG1_END_OFFSET FIOPAD_J53_REG1_OFFSET
#ifdef __cplusplus
}

270
bsp/phytium/libraries/standalone/board/e2000/s/fiopad.h
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@ -1,270 +0,0 @@
#ifndef BOARD_E2000Q_FIOPAD_H
#define BOARD_E2000Q_FIOPAD_H
#ifdef __cplusplus
extern "C"
{
#endif
/***************************** Include Files *********************************/
#include "fiopad_comm.h"
/************************** Constant Definitions *****************************/
/* register offset of iopad function / pull / driver strength */
#define FIOPAD_AN55 (FPinIndex)FIOPAD_INDEX(FIOPAD_0_FUNC_OFFSET)
#define FIOPAD_AW43 (FPinIndex)FIOPAD_INDEX(FIOPAD_2_FUNC_OFFSET)
#define FIOPAD_AR51 (FPinIndex)FIOPAD_INDEX(FIOPAD_9_FUNC_OFFSET)
#define FIOPAD_AJ51 (FPinIndex)FIOPAD_INDEX(FIOPAD_10_FUNC_OFFSET)
#define FIOPAD_AL51 (FPinIndex)FIOPAD_INDEX(FIOPAD_11_FUNC_OFFSET)
#define FIOPAD_AL49 (FPinIndex)FIOPAD_INDEX(FIOPAD_12_FUNC_OFFSET)
#define FIOPAD_AN47 (FPinIndex)FIOPAD_INDEX(FIOPAD_13_FUNC_OFFSET)
#define FIOPAD_AR47 (FPinIndex)FIOPAD_INDEX(FIOPAD_14_FUNC_OFFSET)
#define FIOPAD_BA53 (FPinIndex)FIOPAD_INDEX(FIOPAD_15_FUNC_OFFSET)
#define FIOPAD_BA55 (FPinIndex)FIOPAD_INDEX(FIOPAD_16_FUNC_OFFSET)
#define FIOPAD_AW53 (FPinIndex)FIOPAD_INDEX(FIOPAD_17_FUNC_OFFSET)
#define FIOPAD_AW55 (FPinIndex)FIOPAD_INDEX(FIOPAD_18_FUNC_OFFSET)
#define FIOPAD_AU51 (FPinIndex)FIOPAD_INDEX(FIOPAD_19_FUNC_OFFSET)
#define FIOPAD_AN53 (FPinIndex)FIOPAD_INDEX(FIOPAD_20_FUNC_OFFSET)
#define FIOPAD_AL55 (FPinIndex)FIOPAD_INDEX(FIOPAD_21_FUNC_OFFSET)
#define FIOPAD_AJ55 (FPinIndex)FIOPAD_INDEX(FIOPAD_22_FUNC_OFFSET)
#define FIOPAD_AJ53 (FPinIndex)FIOPAD_INDEX(FIOPAD_23_FUNC_OFFSET)
#define FIOPAD_AG55 (FPinIndex)FIOPAD_INDEX(FIOPAD_24_FUNC_OFFSET)
#define FIOPAD_AG53 (FPinIndex)FIOPAD_INDEX(FIOPAD_25_FUNC_OFFSET)
#define FIOPAD_AE55 (FPinIndex)FIOPAD_INDEX(FIOPAD_26_FUNC_OFFSET)
#define FIOPAD_AC55 (FPinIndex)FIOPAD_INDEX(FIOPAD_27_FUNC_OFFSET)
#define FIOPAD_AC53 (FPinIndex)FIOPAD_INDEX(FIOPAD_28_FUNC_OFFSET)
#define FIOPAD_AR45 (FPinIndex)FIOPAD_INDEX(FIOPAD_31_FUNC_OFFSET)
#define FIOPAD_BA51 (FPinIndex)FIOPAD_INDEX(FIOPAD_32_FUNC_OFFSET)
#define FIOPAD_BA49 (FPinIndex)FIOPAD_INDEX(FIOPAD_33_FUNC_OFFSET)
#define FIOPAD_AR55 (FPinIndex)FIOPAD_INDEX(FIOPAD_34_FUNC_OFFSET)
#define FIOPAD_AU55 (FPinIndex)FIOPAD_INDEX(FIOPAD_35_FUNC_OFFSET)
#define FIOPAD_AR53 (FPinIndex)FIOPAD_INDEX(FIOPAD_36_FUNC_OFFSET)
#define FIOPAD_BA45 (FPinIndex)FIOPAD_INDEX(FIOPAD_37_FUNC_OFFSET)
#define FIOPAD_AW51 (FPinIndex)FIOPAD_INDEX(FIOPAD_38_FUNC_OFFSET)
#define FIOPAD_A31 (FPinIndex)FIOPAD_INDEX(FIOPAD_39_FUNC_OFFSET)
#define FIOPAD_R53 (FPinIndex)FIOPAD_INDEX(FIOPAD_40_FUNC_OFFSET)
#define FIOPAD_R55 (FPinIndex)FIOPAD_INDEX(FIOPAD_41_FUNC_OFFSET)
#define FIOPAD_U55 (FPinIndex)FIOPAD_INDEX(FIOPAD_42_FUNC_OFFSET)
#define FIOPAD_W55 (FPinIndex)FIOPAD_INDEX(FIOPAD_43_FUNC_OFFSET)
#define FIOPAD_U53 (FPinIndex)FIOPAD_INDEX(FIOPAD_44_FUNC_OFFSET)
#define FIOPAD_AA53 (FPinIndex)FIOPAD_INDEX(FIOPAD_45_FUNC_OFFSET)
#define FIOPAD_AA55 (FPinIndex)FIOPAD_INDEX(FIOPAD_46_FUNC_OFFSET)
#define FIOPAD_AW47 (FPinIndex)FIOPAD_INDEX(FIOPAD_47_FUNC_OFFSET)
#define FIOPAD_AU47 (FPinIndex)FIOPAD_INDEX(FIOPAD_48_FUNC_OFFSET)
#define FIOPAD_A35 (FPinIndex)FIOPAD_INDEX(FIOPAD_49_FUNC_OFFSET)
#define FIOPAD_C35 (FPinIndex)FIOPAD_INDEX(FIOPAD_50_FUNC_OFFSET)
#define FIOPAD_C33 (FPinIndex)FIOPAD_INDEX(FIOPAD_51_FUNC_OFFSET)
#define FIOPAD_A33 (FPinIndex)FIOPAD_INDEX(FIOPAD_52_FUNC_OFFSET)
#define FIOPAD_A37 (FPinIndex)FIOPAD_INDEX(FIOPAD_53_FUNC_OFFSET)
#define FIOPAD_A39 (FPinIndex)FIOPAD_INDEX(FIOPAD_54_FUNC_OFFSET)
#define FIOPAD_A41 (FPinIndex)FIOPAD_INDEX(FIOPAD_55_FUNC_OFFSET)
#define FIOPAD_C41 (FPinIndex)FIOPAD_INDEX(FIOPAD_56_FUNC_OFFSET)
#define FIOPAD_A43 (FPinIndex)FIOPAD_INDEX(FIOPAD_57_FUNC_OFFSET)
#define FIOPAD_A45 (FPinIndex)FIOPAD_INDEX(FIOPAD_58_FUNC_OFFSET)
#define FIOPAD_C45 (FPinIndex)FIOPAD_INDEX(FIOPAD_59_FUNC_OFFSET)
#define FIOPAD_A47 (FPinIndex)FIOPAD_INDEX(FIOPAD_60_FUNC_OFFSET)
#define FIOPAD_A29 (FPinIndex)FIOPAD_INDEX(FIOPAD_61_FUNC_OFFSET)
#define FIOPAD_C29 (FPinIndex)FIOPAD_INDEX(FIOPAD_62_FUNC_OFFSET)
#define FIOPAD_C27 (FPinIndex)FIOPAD_INDEX(FIOPAD_63_FUNC_OFFSET)
#define FIOPAD_A27 (FPinIndex)FIOPAD_INDEX(FIOPAD_64_FUNC_OFFSET)
#define FIOPAD_AJ49 (FPinIndex)FIOPAD_INDEX(FIOPAD_65_FUNC_OFFSET)
#define FIOPAD_AL45 (FPinIndex)FIOPAD_INDEX(FIOPAD_66_FUNC_OFFSET)
#define FIOPAD_AL43 (FPinIndex)FIOPAD_INDEX(FIOPAD_67_FUNC_OFFSET)
#define FIOPAD_AN45 (FPinIndex)FIOPAD_INDEX(FIOPAD_68_FUNC_OFFSET)
#define FIOPAD_AG47 (FPinIndex)FIOPAD_INDEX(FIOPAD_148_FUNC_OFFSET)
#define FIOPAD_AJ47 (FPinIndex)FIOPAD_INDEX(FIOPAD_69_FUNC_OFFSET)
#define FIOPAD_AG45 (FPinIndex)FIOPAD_INDEX(FIOPAD_70_FUNC_OFFSET)
#define FIOPAD_AE51 (FPinIndex)FIOPAD_INDEX(FIOPAD_71_FUNC_OFFSET)
#define FIOPAD_AE49 (FPinIndex)FIOPAD_INDEX(FIOPAD_72_FUNC_OFFSET)
#define FIOPAD_AG51 (FPinIndex)FIOPAD_INDEX(FIOPAD_73_FUNC_OFFSET)
#define FIOPAD_AJ45 (FPinIndex)FIOPAD_INDEX(FIOPAD_74_FUNC_OFFSET)
#define FIOPAD_AC51 (FPinIndex)FIOPAD_INDEX(FIOPAD_75_FUNC_OFFSET)
#define FIOPAD_AC49 (FPinIndex)FIOPAD_INDEX(FIOPAD_76_FUNC_OFFSET)
#define FIOPAD_AE47 (FPinIndex)FIOPAD_INDEX(FIOPAD_77_FUNC_OFFSET)
#define FIOPAD_W47 (FPinIndex)FIOPAD_INDEX(FIOPAD_78_FUNC_OFFSET)
#define FIOPAD_W51 (FPinIndex)FIOPAD_INDEX(FIOPAD_79_FUNC_OFFSET)
#define FIOPAD_W49 (FPinIndex)FIOPAD_INDEX(FIOPAD_80_FUNC_OFFSET)
#define FIOPAD_U51 (FPinIndex)FIOPAD_INDEX(FIOPAD_81_FUNC_OFFSET)
#define FIOPAD_U49 (FPinIndex)FIOPAD_INDEX(FIOPAD_82_FUNC_OFFSET)
#define FIOPAD_AE45 (FPinIndex)FIOPAD_INDEX(FIOPAD_83_FUNC_OFFSET)
#define FIOPAD_AC45 (FPinIndex)FIOPAD_INDEX(FIOPAD_84_FUNC_OFFSET)
#define FIOPAD_AE43 (FPinIndex)FIOPAD_INDEX(FIOPAD_85_FUNC_OFFSET)
#define FIOPAD_AA43 (FPinIndex)FIOPAD_INDEX(FIOPAD_86_FUNC_OFFSET)
#define FIOPAD_AA45 (FPinIndex)FIOPAD_INDEX(FIOPAD_87_FUNC_OFFSET)
#define FIOPAD_W45 (FPinIndex)FIOPAD_INDEX(FIOPAD_88_FUNC_OFFSET)
#define FIOPAD_AA47 (FPinIndex)FIOPAD_INDEX(FIOPAD_89_FUNC_OFFSET)
#define FIOPAD_U45 (FPinIndex)FIOPAD_INDEX(FIOPAD_90_FUNC_OFFSET)
#define FIOPAD_G55 (FPinIndex)FIOPAD_INDEX(FIOPAD_91_FUNC_OFFSET)
#define FIOPAD_J55 (FPinIndex)FIOPAD_INDEX(FIOPAD_92_FUNC_OFFSET)
#define FIOPAD_L53 (FPinIndex)FIOPAD_INDEX(FIOPAD_93_FUNC_OFFSET)
#define FIOPAD_C55 (FPinIndex)FIOPAD_INDEX(FIOPAD_94_FUNC_OFFSET)
#define FIOPAD_E55 (FPinIndex)FIOPAD_INDEX(FIOPAD_95_FUNC_OFFSET)
#define FIOPAD_J53 (FPinIndex)FIOPAD_INDEX(FIOPAD_96_FUNC_OFFSET)
#define FIOPAD_L55 (FPinIndex)FIOPAD_INDEX(FIOPAD_97_FUNC_OFFSET)
#define FIOPAD_N55 (FPinIndex)FIOPAD_INDEX(FIOPAD_98_FUNC_OFFSET)
#define FIOPAD_C53 (FPinIndex)FIOPAD_INDEX(FIOPAD_29_FUNC_OFFSET)
#define FIOPAD_E53 (FPinIndex)FIOPAD_INDEX(FIOPAD_30_FUNC_OFFSET)
#define FIOPAD_E27 (FPinIndex)FIOPAD_INDEX(FIOPAD_99_FUNC_OFFSET)
#define FIOPAD_G27 (FPinIndex)FIOPAD_INDEX(FIOPAD_100_FUNC_OFFSET)
#define FIOPAD_N37 (FPinIndex)FIOPAD_INDEX(FIOPAD_101_FUNC_OFFSET)
#define FIOPAD_N35 (FPinIndex)FIOPAD_INDEX(FIOPAD_102_FUNC_OFFSET)
#define FIOPAD_J29 (FPinIndex)FIOPAD_INDEX(FIOPAD_103_FUNC_OFFSET)
#define FIOPAD_N29 (FPinIndex)FIOPAD_INDEX(FIOPAD_104_FUNC_OFFSET)
#define FIOPAD_L29 (FPinIndex)FIOPAD_INDEX(FIOPAD_105_FUNC_OFFSET)
#define FIOPAD_N41 (FPinIndex)FIOPAD_INDEX(FIOPAD_106_FUNC_OFFSET)
#define FIOPAD_N39 (FPinIndex)FIOPAD_INDEX(FIOPAD_107_FUNC_OFFSET)
#define FIOPAD_L27 (FPinIndex)FIOPAD_INDEX(FIOPAD_108_FUNC_OFFSET)
#define FIOPAD_J27 (FPinIndex)FIOPAD_INDEX(FIOPAD_109_FUNC_OFFSET)
#define FIOPAD_J25 (FPinIndex)FIOPAD_INDEX(FIOPAD_110_FUNC_OFFSET)
#define FIOPAD_E25 (FPinIndex)FIOPAD_INDEX(FIOPAD_111_FUNC_OFFSET)
#define FIOPAD_G25 (FPinIndex)FIOPAD_INDEX(FIOPAD_112_FUNC_OFFSET)
#define FIOPAD_N23 (FPinIndex)FIOPAD_INDEX(FIOPAD_113_FUNC_OFFSET)
#define FIOPAD_L25 (FPinIndex)FIOPAD_INDEX(FIOPAD_114_FUNC_OFFSET)
#define FIOPAD_J33 (FPinIndex)FIOPAD_INDEX(FIOPAD_115_FUNC_OFFSET)
#define FIOPAD_J35 (FPinIndex)FIOPAD_INDEX(FIOPAD_116_FUNC_OFFSET)
#define FIOPAD_G37 (FPinIndex)FIOPAD_INDEX(FIOPAD_117_FUNC_OFFSET)
#define FIOPAD_E39 (FPinIndex)FIOPAD_INDEX(FIOPAD_118_FUNC_OFFSET)
#define FIOPAD_L39 (FPinIndex)FIOPAD_INDEX(FIOPAD_119_FUNC_OFFSET)
#define FIOPAD_C39 (FPinIndex)FIOPAD_INDEX(FIOPAD_120_FUNC_OFFSET)
#define FIOPAD_E37 (FPinIndex)FIOPAD_INDEX(FIOPAD_121_FUNC_OFFSET)
#define FIOPAD_L41 (FPinIndex)FIOPAD_INDEX(FIOPAD_122_FUNC_OFFSET)
#define FIOPAD_J39 (FPinIndex)FIOPAD_INDEX(FIOPAD_123_FUNC_OFFSET)
#define FIOPAD_J37 (FPinIndex)FIOPAD_INDEX(FIOPAD_124_FUNC_OFFSET)
#define FIOPAD_L35 (FPinIndex)FIOPAD_INDEX(FIOPAD_125_FUNC_OFFSET)
#define FIOPAD_E33 (FPinIndex)FIOPAD_INDEX(FIOPAD_126_FUNC_OFFSET)
#define FIOPAD_E31 (FPinIndex)FIOPAD_INDEX(FIOPAD_127_FUNC_OFFSET)
#define FIOPAD_G31 (FPinIndex)FIOPAD_INDEX(FIOPAD_128_FUNC_OFFSET)
#define FIOPAD_J31 (FPinIndex)FIOPAD_INDEX(FIOPAD_129_FUNC_OFFSET)
#define FIOPAD_L33 (FPinIndex)FIOPAD_INDEX(FIOPAD_130_FUNC_OFFSET)
#define FIOPAD_N31 (FPinIndex)FIOPAD_INDEX(FIOPAD_131_FUNC_OFFSET)
#define FIOPAD_R47 (FPinIndex)FIOPAD_INDEX(FIOPAD_132_FUNC_OFFSET)
#define FIOPAD_R45 (FPinIndex)FIOPAD_INDEX(FIOPAD_133_FUNC_OFFSET)
#define FIOPAD_N47 (FPinIndex)FIOPAD_INDEX(FIOPAD_134_FUNC_OFFSET)
#define FIOPAD_N51 (FPinIndex)FIOPAD_INDEX(FIOPAD_135_FUNC_OFFSET)
#define FIOPAD_L51 (FPinIndex)FIOPAD_INDEX(FIOPAD_136_FUNC_OFFSET)
#define FIOPAD_J51 (FPinIndex)FIOPAD_INDEX(FIOPAD_137_FUNC_OFFSET)
#define FIOPAD_J41 (FPinIndex)FIOPAD_INDEX(FIOPAD_138_FUNC_OFFSET)
#define FIOPAD_E43 (FPinIndex)FIOPAD_INDEX(FIOPAD_139_FUNC_OFFSET)
#define FIOPAD_G43 (FPinIndex)FIOPAD_INDEX(FIOPAD_140_FUNC_OFFSET)
#define FIOPAD_J43 (FPinIndex)FIOPAD_INDEX(FIOPAD_141_FUNC_OFFSET)
#define FIOPAD_J45 (FPinIndex)FIOPAD_INDEX(FIOPAD_142_FUNC_OFFSET)
#define FIOPAD_N45 (FPinIndex)FIOPAD_INDEX(FIOPAD_143_FUNC_OFFSET)
#define FIOPAD_L47 (FPinIndex)FIOPAD_INDEX(FIOPAD_144_FUNC_OFFSET)
#define FIOPAD_L45 (FPinIndex)FIOPAD_INDEX(FIOPAD_145_FUNC_OFFSET)
#define FIOPAD_N49 (FPinIndex)FIOPAD_INDEX(FIOPAD_146_FUNC_OFFSET)
#define FIOPAD_J49 (FPinIndex)FIOPAD_INDEX(FIOPAD_147_FUNC_OFFSET)
/* register offset of iopad delay */
#define FIOPAD_AJ51_DELAY (FPinIndex)FIOPAD_INDEX(FIOPAD_10_DELAY_OFFSET)
#define FIOPAD_AL51_DELAY (FPinIndex)FIOPAD_INDEX(FIOPAD_11_DELAY_OFFSET)
#define FIOPAD_AL49_DELAY (FPinIndex)FIOPAD_INDEX(FIOPAD_12_DELAY_OFFSET)
#define FIOPAD_AN47_DELAY (FPinIndex)FIOPAD_INDEX(FIOPAD_13_DELAY_OFFSET)
#define FIOPAD_AR47_DELAY (FPinIndex)FIOPAD_INDEX(FIOPAD_14_DELAY_OFFSET)
#define FIOPAD_AJ53_DELAY (FPinIndex)FIOPAD_INDEX(FIOPAD_23_DELAY_OFFSET)
#define FIOPAD_AG55_DELAY (FPinIndex)FIOPAD_INDEX(FIOPAD_24_DELAY_OFFSET)
#define FIOPAD_AG53_DELAY (FPinIndex)FIOPAD_INDEX(FIOPAD_25_DELAY_OFFSET)
#define FIOPAD_AE55_DELAY (FPinIndex)FIOPAD_INDEX(FIOPAD_26_DELAY_OFFSET)
#define FIOPAD_BA51_DELAY (FPinIndex)FIOPAD_INDEX(FIOPAD_32_DELAY_OFFSET)
#define FIOPAD_BA49_DELAY (FPinIndex)FIOPAD_INDEX(FIOPAD_33_DELAY_OFFSET)
#define FIOPAD_AR55_DELAY (FPinIndex)FIOPAD_INDEX(FIOPAD_34_DELAY_OFFSET)
#define FIOPAD_AU55_DELAY (FPinIndex)FIOPAD_INDEX(FIOPAD_35_DELAY_OFFSET)
#define FIOPAD_A41_DELAY (FPinIndex)FIOPAD_INDEX(FIOPAD_55_DELAY_OFFSET)
#define FIOPAD_C41_DELAY (FPinIndex)FIOPAD_INDEX(FIOPAD_56_DELAY_OFFSET)
#define FIOPAD_A43_DELAY (FPinIndex)FIOPAD_INDEX(FIOPAD_57_DELAY_OFFSET)
#define FIOPAD_A45_DELAY (FPinIndex)FIOPAD_INDEX(FIOPAD_58_DELAY_OFFSET)
#define FIOPAD_C45_DELAY (FPinIndex)FIOPAD_INDEX(FIOPAD_59_DELAY_OFFSET)
#define FIOPAD_A47_DELAY (FPinIndex)FIOPAD_INDEX(FIOPAD_60_DELAY_OFFSET)
#define FIOPAD_A29_DELAY (FPinIndex)FIOPAD_INDEX(FIOPAD_61_DELAY_OFFSET)
#define FIOPAD_C29_DELAY (FPinIndex)FIOPAD_INDEX(FIOPAD_62_DELAY_OFFSET)
#define FIOPAD_C27_DELAY (FPinIndex)FIOPAD_INDEX(FIOPAD_63_DELAY_OFFSET)
#define FIOPAD_A27_DELAY (FPinIndex)FIOPAD_INDEX(FIOPAD_64_DELAY_OFFSET)
#define FIOPAD_AJ49_DELAY (FPinIndex)FIOPAD_INDEX(FIOPAD_65_DELAY_OFFSET)
#define FIOPAD_AL45_DELAY (FPinIndex)FIOPAD_INDEX(FIOPAD_66_DELAY_OFFSET)
#define FIOPAD_AL43_DELAY (FPinIndex)FIOPAD_INDEX(FIOPAD_67_DELAY_OFFSET)
#define FIOPAD_AN45_DELAY (FPinIndex)FIOPAD_INDEX(FIOPAD_68_DELAY_OFFSET)
#define FIOPAD_AG47_DELAY (FPinIndex)FIOPAD_INDEX(FIOPAD_148_DELAY_OFFSET)
#define FIOPAD_AJ47_DELAY (FPinIndex)FIOPAD_INDEX(FIOPAD_69_DELAY_OFFSET)
#define FIOPAD_AG45_DELAY (FPinIndex)FIOPAD_INDEX(FIOPAD_70_DELAY_OFFSET)
#define FIOPAD_AE51_DELAY (FPinIndex)FIOPAD_INDEX(FIOPAD_71_DELAY_OFFSET)
#define FIOPAD_AE49_DELAY (FPinIndex)FIOPAD_INDEX(FIOPAD_72_DELAY_OFFSET)
#define FIOPAD_AG51_DELAY (FPinIndex)FIOPAD_INDEX(FIOPAD_73_DELAY_OFFSET)
#define FIOPAD_AJ45_DELAY (FPinIndex)FIOPAD_INDEX(FIOPAD_74_DELAY_OFFSET)
#define FIOPAD_AC51_DELAY (FPinIndex)FIOPAD_INDEX(FIOPAD_75_DELAY_OFFSET)
#define FIOPAD_AC49_DELAY (FPinIndex)FIOPAD_INDEX(FIOPAD_76_DELAY_OFFSET)
#define FIOPAD_AE47_DELAY (FPinIndex)FIOPAD_INDEX(FIOPAD_77_DELAY_OFFSET)
#define FIOPAD_W47_DELAY (FPinIndex)FIOPAD_INDEX(FIOPAD_78_DELAY_OFFSET)
#define FIOPAD_W49_DELAY (FPinIndex)FIOPAD_INDEX(FIOPAD_80_DELAY_OFFSET)
#define FIOPAD_U51_DELAY (FPinIndex)FIOPAD_INDEX(FIOPAD_81_DELAY_OFFSET)
#define FIOPAD_U49_DELAY (FPinIndex)FIOPAD_INDEX(FIOPAD_82_DELAY_OFFSET)
#define FIOPAD_AE45_DELAY (FPinIndex)FIOPAD_INDEX(FIOPAD_83_DELAY_OFFSET)
#define FIOPAD_AC45_DELAY (FPinIndex)FIOPAD_INDEX(FIOPAD_84_DELAY_OFFSET)
#define FIOPAD_AE43_DELAY (FPinIndex)FIOPAD_INDEX(FIOPAD_85_DELAY_OFFSET)
#define FIOPAD_AA43_DELAY (FPinIndex)FIOPAD_INDEX(FIOPAD_86_DELAY_OFFSET)
#define FIOPAD_AA45_DELAY (FPinIndex)FIOPAD_INDEX(FIOPAD_87_DELAY_OFFSET)
#define FIOPAD_W45_DELAY (FPinIndex)FIOPAD_INDEX(FIOPAD_88_DELAY_OFFSET)
#define FIOPAD_AA47_DELAY (FPinIndex)FIOPAD_INDEX(FIOPAD_89_DELAY_OFFSET)
#define FIOPAD_U45_DELAY (FPinIndex)FIOPAD_INDEX(FIOPAD_90_DELAY_OFFSET)
#define FIOPAD_J55_DELAY (FPinIndex)FIOPAD_INDEX(FIOPAD_92_DELAY_OFFSET)
#define FIOPAD_L53_DELAY (FPinIndex)FIOPAD_INDEX(FIOPAD_93_DELAY_OFFSET)
#define FIOPAD_C55_DELAY (FPinIndex)FIOPAD_INDEX(FIOPAD_94_DELAY_OFFSET)
#define FIOPAD_E55_DELAY (FPinIndex)FIOPAD_INDEX(FIOPAD_95_DELAY_OFFSET)
#define FIOPAD_J53_DELAY (FPinIndex)FIOPAD_INDEX(FIOPAD_96_DELAY_OFFSET)
#define FIOPAD_L55_DELAY (FPinIndex)FIOPAD_INDEX(FIOPAD_97_DELAY_OFFSET)
#define FIOPAD_N55_DELAY (FPinIndex)FIOPAD_INDEX(FIOPAD_98_DELAY_OFFSET)
#define FIOPAD_E27_DELAY (FPinIndex)FIOPAD_INDEX(FIOPAD_99_DELAY_OFFSET)
#define FIOPAD_G27_DELAY (FPinIndex)FIOPAD_INDEX(FIOPAD_100_DELAY_OFFSET)
#define FIOPAD_N37_DELAY (FPinIndex)FIOPAD_INDEX(FIOPAD_101_DELAY_OFFSET)
#define FIOPAD_N35_DELAY (FPinIndex)FIOPAD_INDEX(FIOPAD_102_DELAY_OFFSET)
#define FIOPAD_J29_DELAY (FPinIndex)FIOPAD_INDEX(FIOPAD_103_DELAY_OFFSET)
#define FIOPAD_N29_DELAY (FPinIndex)FIOPAD_INDEX(FIOPAD_104_DELAY_OFFSET)
#define FIOPAD_L29_DELAY (FPinIndex)FIOPAD_INDEX(FIOPAD_105_DELAY_OFFSET)
#define FIOPAD_N41_DELAY (FPinIndex)FIOPAD_INDEX(FIOPAD_106_DELAY_OFFSET)
#define FIOPAD_N39_DELAY (FPinIndex)FIOPAD_INDEX(FIOPAD_107_DELAY_OFFSET)
#define FIOPAD_L27_DELAY (FPinIndex)FIOPAD_INDEX(FIOPAD_108_DELAY_OFFSET)
#define FIOPAD_J27_DELAY (FPinIndex)FIOPAD_INDEX(FIOPAD_109_DELAY_OFFSET)
#define FIOPAD_J25_DELAY (FPinIndex)FIOPAD_INDEX(FIOPAD_110_DELAY_OFFSET)
#define FIOPAD_E25_DELAY (FPinIndex)FIOPAD_INDEX(FIOPAD_111_DELAY_OFFSET)
#define FIOPAD_G25_DELAY (FPinIndex)FIOPAD_INDEX(FIOPAD_112_DELAY_OFFSET)
#define FIOPAD_J33_DELAY (FPinIndex)FIOPAD_INDEX(FIOPAD_115_DELAY_OFFSET)
#define FIOPAD_J35_DELAY (FPinIndex)FIOPAD_INDEX(FIOPAD_116_DELAY_OFFSET)
#define FIOPAD_G37_DELAY (FPinIndex)FIOPAD_INDEX(FIOPAD_117_DELAY_OFFSET)
#define FIOPAD_E39_DELAY (FPinIndex)FIOPAD_INDEX(FIOPAD_118_DELAY_OFFSET)
#define FIOPAD_L39_DELAY (FPinIndex)FIOPAD_INDEX(FIOPAD_119_DELAY_OFFSET)
#define FIOPAD_C39_DELAY (FPinIndex)FIOPAD_INDEX(FIOPAD_120_DELAY_OFFSET)
#define FIOPAD_E37_DELAY (FPinIndex)FIOPAD_INDEX(FIOPAD_121_DELAY_OFFSET)
#define FIOPAD_L41_DELAY (FPinIndex)FIOPAD_INDEX(FIOPAD_122_DELAY_OFFSET)
#define FIOPAD_J39_DELAY (FPinIndex)FIOPAD_INDEX(FIOPAD_123_DELAY_OFFSET)
#define FIOPAD_J37_DELAY (FPinIndex)FIOPAD_INDEX(FIOPAD_124_DELAY_OFFSET)
#define FIOPAD_L35_DELAY (FPinIndex)FIOPAD_INDEX(FIOPAD_125_DELAY_OFFSET)
#define FIOPAD_E33_DELAY (FPinIndex)FIOPAD_INDEX(FIOPAD_126_DELAY_OFFSET)
#define FIOPAD_E31_DELAY (FPinIndex)FIOPAD_INDEX(FIOPAD_127_DELAY_OFFSET)
#define FIOPAD_G31_DELAY (FPinIndex)FIOPAD_INDEX(FIOPAD_128_DELAY_OFFSET)
#define FIOPAD_L51_DELAY (FPinIndex)FIOPAD_INDEX(FIOPAD_136_DELAY_OFFSET)
#define FIOPAD_J51_DELAY (FPinIndex)FIOPAD_INDEX(FIOPAD_137_DELAY_OFFSET)
#define FIOPAD_J41_DELAY (FPinIndex)FIOPAD_INDEX(FIOPAD_138_DELAY_OFFSET)
#define FIOPAD_E43_DELAY (FPinIndex)FIOPAD_INDEX(FIOPAD_139_DELAY_OFFSET)
#define FIOPAD_G43_DELAY (FPinIndex)FIOPAD_INDEX(FIOPAD_140_DELAY_OFFSET)
#define FIOPAD_J43_DELAY (FPinIndex)FIOPAD_INDEX(FIOPAD_141_DELAY_OFFSET)
#define FIOPAD_J45_DELAY (FPinIndex)FIOPAD_INDEX(FIOPAD_142_DELAY_OFFSET)
#define FIOPAD_N45_DELAY (FPinIndex)FIOPAD_INDEX(FIOPAD_143_DELAY_OFFSET)
#define FIOPAD_L47_DELAY (FPinIndex)FIOPAD_INDEX(FIOPAD_144_DELAY_OFFSET)
#define FIOPAD_L45_DELAY (FPinIndex)FIOPAD_INDEX(FIOPAD_145_DELAY_OFFSET)
#define FIOPAD_N49_DELAY (FPinIndex)FIOPAD_INDEX(FIOPAD_146_DELAY_OFFSET)
#define FIOPAD_J49_DELAY (FPinIndex)FIOPAD_INDEX(FIOPAD_147_DELAY_OFFSET)
/***************** Macros (Inline Functions) Definitions *********************/
/************************** Function Prototypes ******************************/
/*****************************************************************************/
#ifdef __cplusplus
}
#endif
#endif

317
bsp/phytium/libraries/standalone/board/e2000/s/fiopad_config.c
View File

@ -1,317 +0,0 @@
/*
* Copyright : (C) 2022 Phytium Information Technology, Inc.
* All Rights Reserved.
*
* This program is OPEN SOURCE software: you can redistribute it and/or modify it
* under the terms of the Phytium Public License as published by the Phytium Technology Co.,Ltd,
* either version 1.0 of the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,but WITHOUT ANY WARRANTY;
* without even the implied warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.
* See the Phytium Public License for more details.
*
*
* FilePath: fiopad_config.c
* Date: 2022-02-10 14:53:42
* LastEditTime: 2022-02-18 08:25:29
* Description:  This file is for io-pad function definition
*
* Modify History:
* Ver   Who        Date         Changes
* ----- ------     --------    --------------------------------------
* 1.0 huanghe 2021/11/5 init commit
* 1.1 zhugengyu 2022/3/21 adopt to lastest tech spec.
*/
/***************************** Include Files *********************************/
#include "fiopad.h"
#include "fparameters.h"
#include "fpinctrl.h"
/************************** Constant Definitions *****************************/
/**************************** Type Definitions *******************************/
/***************** Macros (Inline Functions) Definitions *********************/
/************************** Function Prototypes ******************************/
/*****************************************************************************/
/**
* @name: FIOPadSetSpimMux
* @msg: set iopad mux for spim
* @return {*}
* @param {u32} spim_id, instance id of spi
*/
void FIOPadSetSpimMux(u32 spim_id)
{
if (FSPI2_ID == spim_id)
{
FPinSetFunc(FIOPAD_A29, FPIN_FUNC0); /* sclk */
FPinSetFunc(FIOPAD_C29, FPIN_FUNC0); /* txd */
FPinSetFunc(FIOPAD_C27, FPIN_FUNC0); /* rxd */
FPinSetFunc(FIOPAD_A27, FPIN_FUNC0); /* csn0 */
}
}
/**
* @name: FIOPadSetGpioMux
* @msg: set iopad mux for gpio
* @return {*}
* @param {u32} gpio_id, instance id of gpio
* @param {u32} pin_id, index of pin
*/
void FIOPadSetGpioMux(u32 gpio_id, u32 pin_id)
{
if (FGPIO3_ID == gpio_id)
{
switch (pin_id)
{
case 3: /* gpio 3-a-3 */
FPinSetFunc(FIOPAD_A29, FPIN_FUNC6);
break;
case 4: /* gpio 3-a-4 */
FPinSetFunc(FIOPAD_C29, FPIN_FUNC6);
break;
case 5: /* gpio 3-a-5 */
FPinSetFunc(FIOPAD_C27, FPIN_FUNC6);
break;
case 6: /* gpio 3-a-6 */
FPinSetFunc(FIOPAD_A27, FPIN_FUNC6);
break;
default:
break;
}
}
else if (FGPIO4_ID == gpio_id)
{
switch (pin_id)
{
case 5: /* gpio 4-a-5 */
FPinSetFunc(FIOPAD_W47, FPIN_FUNC6);
break;
case 9: /* gpio 4-a-9 */
FPinSetFunc(FIOPAD_U49, FPIN_FUNC6);
break;
case 10: /* gpio 4-a-10 */
FPinSetFunc(FIOPAD_AE45, FPIN_FUNC6);
break;
case 11: /* gpio 4-a-11 */
FPinSetFunc(FIOPAD_AC45, FPIN_FUNC6);
break;
case 12: /* gpio 4-a-12 */
FPinSetFunc(FIOPAD_AE43, FPIN_FUNC6);
break;
case 13: /* gpio 4-a-13 */
FPinSetFunc(FIOPAD_AA43, FPIN_FUNC6);
break;
default:
break;
}
}
}
/**
* @name: FIOPadSetMioMux
* @msg: set iopad mux for mio
* @return {*}
* @param {u32} mio_id, instance id of i2c
*/
void FIOPadSetMioMux(u32 mio_id)
{
switch (mio_id)
{
case FMIO0_ID:
{
FPinSetFunc(FIOPAD_A37, FPIN_FUNC5); /* scl */
FPinSetFunc(FIOPAD_A39, FPIN_FUNC5); /* sda */
}
break;
case FMIO1_ID:
{
FPinSetFunc(FIOPAD_A41, FPIN_FUNC5); /* scl */
FPinSetFunc(FIOPAD_C41, FPIN_FUNC5); /* sda */
}
break;
case FMIO2_ID:
{
FPinSetFunc(FIOPAD_A43, FPIN_FUNC5); /* scl */
FPinSetFunc(FIOPAD_A45, FPIN_FUNC5); /* sda */
}
break;
case FMIO3_ID:
{
FPinSetFunc(FIOPAD_BA51, FPIN_FUNC4); /* scl */
FPinSetFunc(FIOPAD_BA49, FPIN_FUNC4); /* sda */
}
break;
case FMIO4_ID:
{
FPinSetFunc(FIOPAD_R55, FPIN_FUNC4); /* scl */
FPinSetFunc(FIOPAD_U55, FPIN_FUNC4); /* sda */
}
break;
case FMIO5_ID:
{
FPinSetFunc(FIOPAD_W45, FPIN_FUNC4); /* scl */
FPinSetFunc(FIOPAD_U53, FPIN_FUNC4); /* sda */
}
break;
case FMIO6_ID:
{
FPinSetFunc(FIOPAD_AA53, FPIN_FUNC4); /* scl */
FPinSetFunc(FIOPAD_AA55, FPIN_FUNC4); /* sda */
}
break;
case FMIO7_ID:
{
FPinSetFunc(FIOPAD_A35, FPIN_FUNC4); /* scl */
FPinSetFunc(FIOPAD_C35, FPIN_FUNC4); /* sda */
}
break;
case FMIO8_ID:
{
FPinSetFunc(FIOPAD_AA45, FPIN_FUNC4); /* scl */
FPinSetFunc(FIOPAD_W45, FPIN_FUNC4); /* sda */
}
break;
case FMIO9_ID:
{
FPinSetFunc(FIOPAD_AA47, FPIN_FUNC4); /* scl */
FPinSetFunc(FIOPAD_U45, FPIN_FUNC4); /* sda */
}
break;
case FMIO10_ID:
{
FPinSetFunc(FIOPAD_C45, FPIN_FUNC5); /* scl */
FPinSetFunc(FIOPAD_A47, FPIN_FUNC5); /* sda */
}
break;
case FMIO11_ID:
{
FPinSetFunc(FIOPAD_N23, FPIN_FUNC3); /* scl */
FPinSetFunc(FIOPAD_L25, FPIN_FUNC3); /* sda */
}
break;
case FMIO12_ID:
{
FPinSetFunc(FIOPAD_E37, FPIN_FUNC3); /* scl */
FPinSetFunc(FIOPAD_L41, FPIN_FUNC3); /* sda */
}
break;
case FMIO13_ID:
{
FPinSetFunc(FIOPAD_J45, FPIN_FUNC6); /* scl */
FPinSetFunc(FIOPAD_N45, FPIN_FUNC6); /* sda */
}
break;
case FMIO14_ID:
{
FPinSetFunc(FIOPAD_L47, FPIN_FUNC6); /* scl */
FPinSetFunc(FIOPAD_L45, FPIN_FUNC6); /* sda */
}
break;
case FMIO15_ID:
{
FPinSetFunc(FIOPAD_N49, FPIN_FUNC6); /* scl */
FPinSetFunc(FIOPAD_J49, FPIN_FUNC6); /* sda */
}
break;
default:
break;
}
}
/**
* @name: FIOPadSetTachoMux
* @msg: set iopad mux for pwm_in
* @return {*}
* @param {u32} pwm_in_id, instance id of tacho
*/
void FIOPadSetTachoMux(u32 pwm_in_id)
{
switch (pwm_in_id)
{
case FTACHO0_ID:
FPinSetFunc(FIOPAD_AN53, FPIN_FUNC1);
break;
case FTACHO1_ID:
FPinSetFunc(FIOPAD_AJ55, FPIN_FUNC1);
break;
case FTACHO2_ID:
FPinSetFunc(FIOPAD_AG55, FPIN_FUNC1);
break;
case FTACHO3_ID:
FPinSetFunc(FIOPAD_AE55, FPIN_FUNC1);
break;
case FTACHO4_ID:
FPinSetFunc(FIOPAD_AC53, FPIN_FUNC1);
break;
case FTACHO5_ID:
FPinSetFunc(FIOPAD_BA49, FPIN_FUNC1);
break;
case FTACHO6_ID:
FPinSetFunc(FIOPAD_C33, FPIN_FUNC2);
break;
case FTACHO7_ID:
FPinSetFunc(FIOPAD_A37, FPIN_FUNC2);
break;
case FTACHO8_ID:
FPinSetFunc(FIOPAD_A41, FPIN_FUNC2);
break;
case FTACHO9_ID:
FPinSetFunc(FIOPAD_A43, FPIN_FUNC2);
break;
case FTACHO10_ID:
FPinSetFunc(FIOPAD_C45, FPIN_FUNC2);
break;
case FTACHO11_ID:
FPinSetFunc(FIOPAD_A29, FPIN_FUNC2);
break;
case FTACHO12_ID:
FPinSetFunc(FIOPAD_C27, FPIN_FUNC2);
break;
case FTACHO13_ID:
FPinSetFunc(FIOPAD_AA45, FPIN_FUNC2);
break;
case FTACHO14_ID:
FPinSetFunc(FIOPAD_AA47, FPIN_FUNC2);
break;
case FTACHO15_ID:
FPinSetFunc(FIOPAD_G55, FPIN_FUNC2);
break;
default:
break;
}
}
/**
* @name: FIOPadSetUartMux
* @msg: set iopad mux for uart
* @return {*}
* @param {u32} uart_id, instance id of uart
*/
void FIOPadSetUartMux(u32 uart_id)
{
switch (uart_id)
{
case FUART0_ID:
FPinSetFunc(FIOPAD_J33, FPIN_FUNC4);
FPinSetFunc(FIOPAD_J35, FPIN_FUNC4);
break;
case FUART1_ID:
FPinSetFunc(FIOPAD_AW47, FPIN_FUNC0);
FPinSetFunc(FIOPAD_AU47, FPIN_FUNC0);
break;
case FUART2_ID:
FPinSetFunc(FIOPAD_A43, FPIN_FUNC0);
FPinSetFunc(FIOPAD_A45, FPIN_FUNC0);
break;
case FUART3_ID:
FPinSetFunc(FIOPAD_L33, FPIN_FUNC2);
FPinSetFunc(FIOPAD_N31, FPIN_FUNC2);
break;
default:
break;
}
}

254
bsp/phytium/libraries/standalone/board/e2000/s/fparameters.h
View File

@ -28,20 +28,266 @@
extern "C"
{
#endif
/***************************** Include Files *********************************/
#include "fparameters_comm.h"
/************************** Constant Definitions *****************************/
#define CORE0_AFF 0x200U
#define FCORE_NUM 1
#define FT_CPUS_NR 1U
/* GIC offset */
#define FT_GIC_REDISTRUBUTIOR_OFFSET 2
/* register offset of iopad function / pull / driver strength */
#define FIOPAD_AN55_REG0_OFFSET 0x0000U
#define FIOPAD_AW43_REG0_OFFSET 0x0004U
#define FIOPAD_AR51_REG0_OFFSET 0x0020U
#define FIOPAD_AJ51_REG0_OFFSET 0x0024U
#define FIOPAD_AL51_REG0_OFFSET 0x0028U
#define FIOPAD_AL49_REG0_OFFSET 0x002CU
#define FIOPAD_AN47_REG0_OFFSET 0x0030U
#define FIOPAD_AR47_REG0_OFFSET 0x0034U
#define FIOPAD_BA53_REG0_OFFSET 0x0038U
#define FIOPAD_BA55_REG0_OFFSET 0x003CU
#define FIOPAD_AW53_REG0_OFFSET 0x0040U
#define FIOPAD_AW55_REG0_OFFSET 0x0044U
#define FIOPAD_AU51_REG0_OFFSET 0x0048U
#define FIOPAD_AN53_REG0_OFFSET 0x004CU
#define FIOPAD_AL55_REG0_OFFSET 0x0050U
#define FIOPAD_AJ55_REG0_OFFSET 0x0054U
#define FIOPAD_AJ53_REG0_OFFSET 0x0058U
#define FIOPAD_AG55_REG0_OFFSET 0x005CU
#define FIOPAD_AG53_REG0_OFFSET 0x0060U
#define FIOPAD_AE55_REG0_OFFSET 0x0064U
#define FIOPAD_AC55_REG0_OFFSET 0x0068U
#define FIOPAD_AC53_REG0_OFFSET 0x006CU
#define FIOPAD_AR45_REG0_OFFSET 0x0070U
#define FIOPAD_BA51_REG0_OFFSET 0x0074U
#define FIOPAD_BA49_REG0_OFFSET 0x0078U
#define FIOPAD_AR55_REG0_OFFSET 0x007CU
#define FIOPAD_AU55_REG0_OFFSET 0x0080U
#define FIOPAD_AR53_REG0_OFFSET 0x0084U
#define FIOPAD_BA45_REG0_OFFSET 0x0088U
#define FIOPAD_AW51_REG0_OFFSET 0x008CU
#define FIOPAD_A31_REG0_OFFSET 0x0090U
#define FIOPAD_R53_REG0_OFFSET 0x0094U
#define FIOPAD_R55_REG0_OFFSET 0x0098U
#define FIOPAD_U55_REG0_OFFSET 0x009CU
#define FIOPAD_W55_REG0_OFFSET 0x00A0U
#define FIOPAD_U53_REG0_OFFSET 0x00A4U
#define FIOPAD_AA53_REG0_OFFSET 0x00A8U
#define FIOPAD_AA55_REG0_OFFSET 0x00ACU
#define FIOPAD_AW47_REG0_OFFSET 0x00B0U
#define FIOPAD_AU47_REG0_OFFSET 0x00B4U
#define FIOPAD_A35_REG0_OFFSET 0x00B8U
#define FIOPAD_C35_REG0_OFFSET 0x00BCU
#define FIOPAD_C33_REG0_OFFSET 0x00C0U
#define FIOPAD_A33_REG0_OFFSET 0x00C4U
#define FIOPAD_A37_REG0_OFFSET 0x00C8U
#define FIOPAD_A39_REG0_OFFSET 0x00CCU
#define FIOPAD_A41_REG0_OFFSET 0x00D0U
#define FIOPAD_C41_REG0_OFFSET 0x00D4U
#define FIOPAD_A43_REG0_OFFSET 0x00D8U
#define FIOPAD_A45_REG0_OFFSET 0x00DCU
#define FIOPAD_C45_REG0_OFFSET 0x00E0U
#define FIOPAD_A47_REG0_OFFSET 0x00E4U
#define FIOPAD_A29_REG0_OFFSET 0x00E8U
#define FIOPAD_C29_REG0_OFFSET 0x00ECU
#define FIOPAD_C27_REG0_OFFSET 0x00F0U
#define FIOPAD_A27_REG0_OFFSET 0x00F4U
#define FIOPAD_AJ49_REG0_OFFSET 0x00F8U
#define FIOPAD_AL45_REG0_OFFSET 0x00FCU
#define FIOPAD_AL43_REG0_OFFSET 0x0100U
#define FIOPAD_AN45_REG0_OFFSET 0x0104U
#define FIOPAD_AG47_REG0_OFFSET 0x0108U
#define FIOPAD_AJ47_REG0_OFFSET 0x010CU
#define FIOPAD_AG45_REG0_OFFSET 0x0110U
#define FIOPAD_AE51_REG0_OFFSET 0x0114U
#define FIOPAD_AE49_REG0_OFFSET 0x0118U
#define FIOPAD_AG51_REG0_OFFSET 0x011CU
#define FIOPAD_AJ45_REG0_OFFSET 0x0120U
#define FIOPAD_AC51_REG0_OFFSET 0x0124U
#define FIOPAD_AC49_REG0_OFFSET 0x0128U
#define FIOPAD_AE47_REG0_OFFSET 0x012CU
#define FIOPAD_W47_REG0_OFFSET 0x0130U
#define FIOPAD_W51_REG0_OFFSET 0x0134U
#define FIOPAD_W49_REG0_OFFSET 0x0138U
#define FIOPAD_U51_REG0_OFFSET 0x013CU
#define FIOPAD_U49_REG0_OFFSET 0x0140U
#define FIOPAD_AE45_REG0_OFFSET 0x0144U
#define FIOPAD_AC45_REG0_OFFSET 0x0148U
#define FIOPAD_AE43_REG0_OFFSET 0x014CU
#define FIOPAD_AA43_REG0_OFFSET 0x0150U
#define FIOPAD_AA45_REG0_OFFSET 0x0154U
#define FIOPAD_W45_REG0_OFFSET 0x0158U
#define FIOPAD_AA47_REG0_OFFSET 0x015CU
#define FIOPAD_U45_REG0_OFFSET 0x0160U
#define FIOPAD_G55_REG0_OFFSET 0x0164U
#define FIOPAD_J55_REG0_OFFSET 0x0168U
#define FIOPAD_L53_REG0_OFFSET 0x016CU
#define FIOPAD_C55_REG0_OFFSET 0x0170U
#define FIOPAD_E55_REG0_OFFSET 0x0174U
#define FIOPAD_J53_REG0_OFFSET 0x0178U
#define FIOPAD_L55_REG0_OFFSET 0x017CU
#define FIOPAD_N55_REG0_OFFSET 0x0180U
#define FIOPAD_C53_REG0_OFFSET 0x0184U
#define FIOPAD_E53_REG0_OFFSET 0x0188U
#define FIOPAD_E27_REG0_OFFSET 0x018CU
#define FIOPAD_G27_REG0_OFFSET 0x0190U
#define FIOPAD_N37_REG0_OFFSET 0x0194U
#define FIOPAD_N35_REG0_OFFSET 0x0198U
#define FIOPAD_J29_REG0_OFFSET 0x019CU
#define FIOPAD_N29_REG0_OFFSET 0x01A0U
#define FIOPAD_L29_REG0_OFFSET 0x01A4U
#define FIOPAD_N41_REG0_OFFSET 0x01A8U
#define FIOPAD_N39_REG0_OFFSET 0x01ACU
#define FIOPAD_L27_REG0_OFFSET 0x01B0U
#define FIOPAD_J27_REG0_OFFSET 0x01B4U
#define FIOPAD_J25_REG0_OFFSET 0x01B8U
#define FIOPAD_E25_REG0_OFFSET 0x01BCU
#define FIOPAD_G25_REG0_OFFSET 0x01C0U
#define FIOPAD_N23_REG0_OFFSET 0x01C4U
#define FIOPAD_L25_REG0_OFFSET 0x01C8U
#define FIOPAD_J33_REG0_OFFSET 0x01CCU
#define FIOPAD_J35_REG0_OFFSET 0x01D0U
#define FIOPAD_G37_REG0_OFFSET 0x01D4U
#define FIOPAD_E39_REG0_OFFSET 0x01D8U
#define FIOPAD_L39_REG0_OFFSET 0x01DCU
#define FIOPAD_C39_REG0_OFFSET 0x01E0U
#define FIOPAD_E37_REG0_OFFSET 0x01E4U
#define FIOPAD_L41_REG0_OFFSET 0x01E8U
#define FIOPAD_J39_REG0_OFFSET 0x01ECU
#define FIOPAD_J37_REG0_OFFSET 0x01F0U
#define FIOPAD_L35_REG0_OFFSET 0x01F4U
#define FIOPAD_E33_REG0_OFFSET 0x01F8U
#define FIOPAD_E31_REG0_OFFSET 0x01FCU
#define FIOPAD_G31_REG0_OFFSET 0x0200U
#define FIOPAD_J31_REG0_OFFSET 0x0204U
#define FIOPAD_L33_REG0_OFFSET 0x0208U
#define FIOPAD_N31_REG0_OFFSET 0x020CU
#define FIOPAD_R47_REG0_OFFSET 0x0210U
#define FIOPAD_R45_REG0_OFFSET 0x0214U
#define FIOPAD_N47_REG0_OFFSET 0x0218U
#define FIOPAD_N51_REG0_OFFSET 0x021CU
#define FIOPAD_L51_REG0_OFFSET 0x0220U
#define FIOPAD_J51_REG0_OFFSET 0x0224U
#define FIOPAD_J41_REG0_OFFSET 0x0228U
#define FIOPAD_E43_REG0_OFFSET 0x022CU
#define FIOPAD_G43_REG0_OFFSET 0x0230U
#define FIOPAD_J43_REG0_OFFSET 0x0234U
#define FIOPAD_J45_REG0_OFFSET 0x0238U
#define FIOPAD_N45_REG0_OFFSET 0x023CU
#define FIOPAD_L47_REG0_OFFSET 0x0240U
#define FIOPAD_L45_REG0_OFFSET 0x0244U
#define FIOPAD_N49_REG0_OFFSET 0x0248U
#define FIOPAD_J49_REG0_OFFSET 0x024CU
#define FIOPAD_REG0_BEG_OFFSET FIOPAD_AN55_REG0_OFFSET
#define FIOPAD_REG0_END_OFFSET FIOPAD_J49_REG0_OFFSET
/* register offset of iopad delay */
#define FIOPAD_AJ51_REG1_OFFSET 0x1024U
#define FIOPAD_AL51_REG1_OFFSET 0x1028U
#define FIOPAD_AL49_REG1_OFFSET 0x102CU
#define FIOPAD_AN47_REG1_OFFSET 0x1030U
#define FIOPAD_AR47_REG1_OFFSET 0x1034U
#define FIOPAD_AJ53_REG1_OFFSET 0x1058U
#define FIOPAD_AG55_REG1_OFFSET 0x105CU
#define FIOPAD_AG53_REG1_OFFSET 0x1060U
#define FIOPAD_AE55_REG1_OFFSET 0x1064U
#define FIOPAD_BA51_REG1_OFFSET 0x1074U
#define FIOPAD_BA49_REG1_OFFSET 0x1078U
#define FIOPAD_AR55_REG1_OFFSET 0x107CU
#define FIOPAD_AU55_REG1_OFFSET 0x1080U
#define FIOPAD_A41_REG1_OFFSET 0x10D0U
#define FIOPAD_C41_REG1_OFFSET 0x10D4U
#define FIOPAD_A43_REG1_OFFSET 0x10D8U
#define FIOPAD_A45_REG1_OFFSET 0x10DCU
#define FIOPAD_C45_REG1_OFFSET 0x10E0U
#define FIOPAD_A47_REG1_OFFSET 0x10E4U
#define FIOPAD_A29_REG1_OFFSET 0x10E8U
#define FIOPAD_C29_REG1_OFFSET 0x10ECU
#define FIOPAD_C27_REG1_OFFSET 0x10F0U
#define FIOPAD_A27_REG1_OFFSET 0x10F4U
#define FIOPAD_AJ49_REG1_OFFSET 0x10F8U
#define FIOPAD_AL45_REG1_OFFSET 0x10FCU
#define FIOPAD_AL43_REG1_OFFSET 0x1100U
#define FIOPAD_AN45_REG1_OFFSET 0x1104U
#define FIOPAD_AG47_REG1_OFFSET 0x1108U
#define FIOPAD_AJ47_REG1_OFFSET 0x110CU
#define FIOPAD_AG45_REG1_OFFSET 0x1110U
#define FIOPAD_AE51_REG1_OFFSET 0x1114U
#define FIOPAD_AE49_REG1_OFFSET 0x1118U
#define FIOPAD_AG51_REG1_OFFSET 0x111CU
#define FIOPAD_AJ45_REG1_OFFSET 0x1120U
#define FIOPAD_AC51_REG1_OFFSET 0x1124U
#define FIOPAD_AC49_REG1_OFFSET 0x1128U
#define FIOPAD_AE47_REG1_OFFSET 0x112CU
#define FIOPAD_W47_REG1_OFFSET 0x1130U
#define FIOPAD_W49_REG1_OFFSET 0x1138U
#define FIOPAD_U51_REG1_OFFSET 0x113CU
#define FIOPAD_U49_REG1_OFFSET 0x1140U
#define FIOPAD_AE45_REG1_OFFSET 0x1144U
#define FIOPAD_AC45_REG1_OFFSET 0x1148U
#define FIOPAD_AE43_REG1_OFFSET 0x114CU
#define FIOPAD_AA43_REG1_OFFSET 0x1150U
#define FIOPAD_AA45_REG1_OFFSET 0x1154U
#define FIOPAD_W45_REG1_OFFSET 0x1158U
#define FIOPAD_AA47_REG1_OFFSET 0x115CU
#define FIOPAD_U45_REG1_OFFSET 0x1160U
#define FIOPAD_J55_REG1_OFFSET 0x1168U
#define FIOPAD_L53_REG1_OFFSET 0x116CU
#define FIOPAD_C55_REG1_OFFSET 0x1170U
#define FIOPAD_E55_REG1_OFFSET 0x1174U
#define FIOPAD_J53_REG1_OFFSET 0x1178U
#define FIOPAD_L55_REG1_OFFSET 0x117CU
#define FIOPAD_N55_REG1_OFFSET 0x1180U
#define FIOPAD_E27_REG1_OFFSET 0x118CU
#define FIOPAD_G27_REG1_OFFSET 0x1190U
#define FIOPAD_N37_REG1_OFFSET 0x1194U
#define FIOPAD_N35_REG1_OFFSET 0x1198U
#define FIOPAD_J29_REG1_OFFSET 0x119CU
#define FIOPAD_N29_REG1_OFFSET 0x11A0U
#define FIOPAD_L29_REG1_OFFSET 0x11A4U
#define FIOPAD_N41_REG1_OFFSET 0x11A8U
#define FIOPAD_N39_REG1_OFFSET 0x11ACU
#define FIOPAD_L27_REG1_OFFSET 0x11B0U
#define FIOPAD_J27_REG1_OFFSET 0x11B4U
#define FIOPAD_J25_REG1_OFFSET 0x11B8U
#define FIOPAD_E25_REG1_OFFSET 0x11BCU
#define FIOPAD_G25_REG1_OFFSET 0x11C0U
#define FIOPAD_J33_REG1_OFFSET 0x11CCU
#define FIOPAD_J35_REG1_OFFSET 0x11D0U
#define FIOPAD_G37_REG1_OFFSET 0x11D4U
#define FIOPAD_E39_REG1_OFFSET 0x11D8U
#define FIOPAD_L39_REG1_OFFSET 0x11DCU
#define FIOPAD_C39_REG1_OFFSET 0x11E0U
#define FIOPAD_E37_REG1_OFFSET 0x11E4U
#define FIOPAD_L41_REG1_OFFSET 0x11E8U
#define FIOPAD_J39_REG1_OFFSET 0x11ECU
#define FIOPAD_J37_REG1_OFFSET 0x11F0U
#define FIOPAD_L35_REG1_OFFSET 0x11F4U
#define FIOPAD_E33_REG1_OFFSET 0x11F8U
#define FIOPAD_E31_REG1_OFFSET 0x11FCU
#define FIOPAD_G31_REG1_OFFSET 0x1200U
#define FIOPAD_L51_REG1_OFFSET 0x1220U
#define FIOPAD_J51_REG1_OFFSET 0x1224U
#define FIOPAD_J41_REG1_OFFSET 0x1228U
#define FIOPAD_E43_REG1_OFFSET 0x122CU
#define FIOPAD_G43_REG1_OFFSET 0x1230U
#define FIOPAD_J43_REG1_OFFSET 0x1234U
#define FIOPAD_J45_REG1_OFFSET 0x1238U
#define FIOPAD_N45_REG1_OFFSET 0x123CU
#define FIOPAD_L47_REG1_OFFSET 0x1240U
#define FIOPAD_L45_REG1_OFFSET 0x1244U
#define FIOPAD_N49_REG1_OFFSET 0x1248U
#define FIOPAD_J49_REG1_OFFSET 0x124CU
#define FIOPAD_REG1_BEG_OFFSET FIOPAD_AJ51_REG1_OFFSET
#define FIOPAD_REG1_END_OFFSET FIOPAD_J49_REG1_OFFSET
/*****************************************************************************/
@ -50,4 +296,4 @@ extern "C"
#endif
#endif
#endif

348
bsp/phytium/libraries/standalone/board/ft2004/fioctrl.c
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@ -1,348 +0,0 @@
/*
* Copyright : (C) 2022 Phytium Information Technology, Inc.
* All Rights Reserved.
*
* This program is OPEN SOURCE software: you can redistribute it and/or modify it
* under the terms of the Phytium Public License as published by the Phytium Technology Co.,Ltd,
* either version 1.0 of the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,but WITHOUT ANY WARRANTY;
* without even the implied warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.
* See the Phytium Public License for more details.
*
*
* FilePath: fioctrl.c
* Date: 2022-02-10 14:53:42
* LastEditTime: 2022-02-18 08:25:29
* Description:  This files is for io-ctrl function implementation (io-mux/io-config/io-delay)
*
* Modify History:
* Ver   Who        Date         Changes
* ----- ------     --------    --------------------------------------
* 1.0 zhugengyu 2022/2/22 init commit
*/
/***************************** Include Files *********************************/
#include "fparameters.h"
#include "fio.h"
#include "fkernel.h"
#include "fassert.h"
#include "fdebug.h"
#include "fioctrl.h"
#include "fpinctrl.h"
/************************** Constant Definitions *****************************/
/* Bit[0] : 输入延迟功能使能 */
#define FIOCTRL_DELAY_EN(delay_beg) BIT(delay_beg)
#define FIOCTRL_INPUT_DELAY_OFF 0
/* Bit[3:1] : 输入延迟精调档位选择 */
#define FIOCTRL_DELICATE_DELAY_MASK(delay_beg) GENMASK((delay_beg + 3), (delay_beg + 1))
#define FIOCTRL_DELICATE_DELAY_GET(reg_val, delay_beg) GET_REG32_BITS((reg_val), (delay_beg + 3), (delay_beg + 1))
#define FIOCTRL_DELICATE_DELAY_SET(val, delay_beg) SET_REG32_BITS((val), (delay_beg + 3), (delay_beg + 1))
/* Bit[6:4] : 输入延迟粗调档位选择 */
#define FIOCTRL_ROUGH_DELAY_MASK(delay_beg) GENMASK((delay_beg + 6), (delay_beg + 4))
#define FIOCTRL_ROUGH_DELAY_GET(reg_val, delay_beg) GET_REG32_BITS((reg_val), (delay_beg + 6), (delay_beg + 4))
#define FIOCTRL_ROUGH_DELAY_SET(val, delay_beg) SET_REG32_BITS((val), (delay_beg + 6), (delay_beg + 4))
/* Bit[7] : 保留 */
/* Bit[8] : 输出延迟功能使能 */
/* Bit[11:9] : 输出延迟精调档位选择 */
/* Bit [14:12] : 输出延迟粗调档位选择 */
/* Bit [15] : 保留 */
#define FIOCTRL_FUNC_BEG_OFF(reg_bit) ((reg_bit) + 0)
#define FIOCTRL_FUNC_END_OFF(reg_bit) ((reg_bit) + 1) /* bit[1:0] 复用功能占2个位 */
#define FIOCTRL_PULL_BEG_OFF(reg_bit) ((reg_bit) + 2)
#define FIOCTRL_PULL_END_OFF(reg_bit) ((reg_bit) + 3) /* bit[3:2] 上下拉功能占2个位 */
#define FIOCTRL_DELAY_IN_BEG_OFF(reg_bit) ((reg_bit) + 0)
#define FIOCTRL_DELAY_IN_END_OFF(reg_bit) ((reg_bit) + 7) /* bit[8:1] 输入延时占7个位 */
#define FIOCTRL_DELAY_OUT_BEG_OFF(reg_bit) ((reg_bit) + 8)
#define FIOCTRL_DELAY_OUT_END_OFF(reg_bit) ((reg_bit) + 15) /* bit[15:9] 输出延时占7个位 */
/* 芯片引脚控制寄存器的起止位置 */
#define FIOCTRL_REG_OFFSET_MIN 0x200
#define FIOCTRL_REG_OFFSET_MAX 0x22c
/* 芯片引脚延时寄存器的起止位置 */
#define FIOCTRL_DELAY_REG_OFFSET_MIN 0x400
#define FIOCTRL_DELAY_REG_OFFSET_MAX 0x404
/**************************** Type Definitions *******************************/
/***************** Macros (Inline Functions) Definitions *********************/
#define FIOCTRL_DEBUG_TAG "FIOCTRL"
#define FIOCTRL_ERROR(format, ...) FT_DEBUG_PRINT_E(FIOCTRL_DEBUG_TAG, format, ##__VA_ARGS__)
#define FIOCTRL_WARN(format, ...) FT_DEBUG_PRINT_W(FIOCTRL_DEBUG_TAG, format, ##__VA_ARGS__)
#define FIOCTRL_INFO(format, ...) FT_DEBUG_PRINT_I(FIOCTRL_DEBUG_TAG, format, ##__VA_ARGS__)
#define FIOCTRL_DEBUG(format, ...) FT_DEBUG_PRINT_D(FIOCTRL_DEBUG_TAG, format, ##__VA_ARGS__)
#define FIOCTRL_ASSERT_REG_OFF(pin) FASSERT_MSG(((pin.reg_off >= FIOCTRL_REG_OFFSET_MIN) && (pin.reg_off <= FIOCTRL_REG_OFFSET_MAX)), "invalid pin register off @%d", (pin.reg_off))
#define FIOCTRL_ASSERT_FUNC(func) FASSERT_MSG((func < FPIN_NUM_OF_FUNC), "invalid func as %d", (func))
#define FIOCTRL_ASSERT_PULL(pull) FASSERT_MSG((pull < FPIN_NUM_OF_PULL), "invalid pull as %d", (pull))
#define FIOCTRL_ASSERT_DELAY_REG_OFF(pin) FASSERT_MSG(((pin.reg_off >= FIOCTRL_DELAY_REG_OFFSET_MIN) && (pin.reg_off <= FIOCTRL_DELAY_REG_OFFSET_MAX)), "invalid delay pin register off @%d", (pin.reg_off))
#define FIOCTRL_ASSERT_DELAY(delay) FASSERT_MSG(((delay) < FPIN_NUM_OF_DELAY), "invalid delay as %d", (delay));
/************************** Function Prototypes ******************************/
/************************** Variable Definitions *****************************/
/*****************************************************************************/
/**
* @name: FPinGetFunc
* @msg: 获取IO引脚当前的复用功能
* @return {FPinFunc} 当前的复用功能
* @param {FPinIndex} pin IO引脚索引
* @note 参考编程手册，使用 FIOCTRL_INDEX 宏定义index的值
*/
FPinFunc FPinGetFunc(const FPinIndex pin)
{
FIOCTRL_ASSERT_REG_OFF(pin);
u32 func_beg = FIOCTRL_FUNC_BEG_OFF(pin.reg_bit);
u32 func_end = FIOCTRL_FUNC_END_OFF(pin.reg_bit);
u32 reg_val = FtIn32(FIOCTRL_REG_BASE_ADDR + pin.reg_off);
u32 func = GET_REG32_BITS(reg_val, func_end, func_beg);
FIOCTRL_ASSERT_FUNC(func);
return (FPinFunc)GET_REG32_BITS(reg_val, func_end, func_beg);
}
/**
* @name: FPinSetFunc
* @msg: 设置IO引脚复用功能
* @return {*}
* @param {FPinIndex} pin IO引脚索引
* @param {FPinFunc} func IO复用功能
* @note 参考编程手册，使用 FIOCTRL_INDEX 宏定义index的值
*/
void FPinSetFunc(const FPinIndex pin, FPinFunc func)
{
FIOCTRL_ASSERT_REG_OFF(pin);
FIOCTRL_ASSERT_FUNC(func);
u32 func_beg = FIOCTRL_FUNC_BEG_OFF(pin.reg_bit);
u32 func_end = FIOCTRL_FUNC_END_OFF(pin.reg_bit);
u32 reg_val = FtIn32(FIOCTRL_REG_BASE_ADDR + pin.reg_off);
reg_val &= ~GENMASK(func_end, func_beg);
reg_val |= SET_REG32_BITS(func, func_end, func_beg);
FtOut32(FIOCTRL_REG_BASE_ADDR + pin.reg_off, reg_val);
return;
}
/**
* @name: FPinGetPull
* @msg: 获取IO引脚当前的上下拉设置
* @return {*}
* @param {FPinIndex} pin IO引脚索引
* @note 参考编程手册，使用 FIOCTRL_INDEX 宏定义index的值
*/
FPinPull FPinGetPull(const FPinIndex pin)
{
FIOCTRL_ASSERT_REG_OFF(pin);
u32 pull_beg = FIOCTRL_PULL_BEG_OFF(pin.reg_bit);
u32 pull_end = FIOCTRL_PULL_END_OFF(pin.reg_bit);
u32 reg_val = FtIn32(FIOCTRL_REG_BASE_ADDR + pin.reg_off);
u32 pull = GET_REG32_BITS(reg_val, pull_end, pull_beg);
FIOCTRL_ASSERT_PULL(pull);
return (FPinPull)pull;
}
/**
* @name: FPinSetPull
* @msg: 设置IO引脚当前的上下拉
* @return {*}
* @param {FPinIndex} pin IO引脚索引
* @param {FPinPull} pull 上下拉设置
*/
void FPinSetPull(const FPinIndex pin, FPinPull pull)
{
FIOCTRL_ASSERT_REG_OFF(pin);
FIOCTRL_ASSERT_PULL(pull);
u32 pull_beg = FIOCTRL_PULL_BEG_OFF(pin.reg_bit);
u32 pull_end = FIOCTRL_PULL_END_OFF(pin.reg_bit);
u32 reg_val = FtIn32(FIOCTRL_REG_BASE_ADDR + pin.reg_off);
reg_val &= ~GENMASK(pull_end, pull_beg);
reg_val |= SET_REG32_BITS(pull, pull_end, pull_beg);
FtOut32(FIOCTRL_REG_BASE_ADDR + pin.reg_off, reg_val);
return;
}
/**
* @name: FPinGetDelay
* @msg: 获取IO引脚当前的延时设置
* @return {FPinDelay} 当前的延时设置
* @param {FPinIndex} pin IO引脚延时设置索引
* @param {FPinDelayDir} dir 输入/输出延时
* @param {FPinDelayType} type 精调/粗调延时
*/
FPinDelay FPinGetDelay(const FPinIndex pin, FPinDelayDir dir, FPinDelayType type)
{
FIOCTRL_ASSERT_DELAY_REG_OFF(pin);
u8 delay = 0;
const u32 reg_val = FtIn32(FIOCTRL_REG_BASE_ADDR + pin.reg_off);
u32 delay_beg = 0, delay_end = 0;
if (FPIN_OUTPUT_DELAY == dir)
{
delay_beg = FIOCTRL_DELAY_OUT_BEG_OFF(pin.reg_off);
}
else if (FPIN_INPUT_DELAY == dir)
{
delay_beg = FIOCTRL_DELAY_IN_BEG_OFF(pin.reg_off);
}
else
{
FASSERT(0);
}
if (FPIN_DELAY_FINE_TUNING == type)
{
delay = FIOCTRL_DELICATE_DELAY_GET(reg_val, delay_beg); /* bit[3:1] delicate delay tune */
}
else if (FPIN_DELAY_COARSE_TUNING == type)
{
delay = FIOCTRL_ROUGH_DELAY_GET(reg_val, delay_beg); /* bit[6:4] rough delay adjust */
}
else
{
FASSERT(0);
}
FIOCTRL_ASSERT_DELAY(delay);
return (FPinDelay)delay;
}
/**
* @name: FPinGetDelayEn
* @msg: 获取IO引脚当前的延时使能标志位
* @return {*}
* @param {FPinIndex} pin IO引脚延时设置索引
* @param {FPinDelayDir} dir 输入/输出延时
*/
boolean FPinGetDelayEn(const FPinIndex pin, FPinDelayDir dir)
{
FIOCTRL_ASSERT_DELAY_REG_OFF(pin);
boolean enabled = FALSE;
const u32 reg_val = FtIn32(FIOCTRL_REG_BASE_ADDR + pin.reg_off);
u32 delay_beg = 0, delay_end = 0;
if (FPIN_OUTPUT_DELAY == dir)
{
delay_beg = FIOCTRL_DELAY_OUT_BEG_OFF(pin.reg_off);
}
else if (FPIN_INPUT_DELAY == dir)
{
delay_beg = FIOCTRL_DELAY_IN_BEG_OFF(pin.reg_off);
}
else
{
FASSERT(0);
}
if (FIOCTRL_DELAY_EN(delay_beg) & reg_val)
{
enabled = TRUE;
}
return enabled;
}
/**
* @name: FPinSetDelay
* @msg: 设置IO引脚延时
* @return {*}
* @param {FPinIndex} pin IO引脚延时设置索引
* @param {FPinDelayDir} dir 输入/输出延时
* @param {FPinDelayType} type 精调/粗调延时
* @param {FPinDelay} delay 延时档位设置 0 ~ 8 档可用
*/
void FPinSetDelay(const FPinIndex pin, FPinDelayDir dir, FPinDelayType type, FPinDelay delay)
{
FIOCTRL_ASSERT_DELAY_REG_OFF(pin);
FIOCTRL_ASSERT_DELAY(delay);
u32 reg_val = FtIn32(FIOCTRL_REG_BASE_ADDR + pin.reg_off);
u32 delay_beg = 0, delay_end = 0;
if (FPIN_OUTPUT_DELAY == dir)
{
delay_beg = FIOCTRL_DELAY_OUT_BEG_OFF(pin.reg_off);
}
else if (FPIN_INPUT_DELAY == dir)
{
delay_beg = FIOCTRL_DELAY_IN_BEG_OFF(pin.reg_off);
}
else
{
FASSERT(0);
}
if (FPIN_DELAY_FINE_TUNING == type)
{
reg_val &= ~FIOCTRL_DELICATE_DELAY_MASK(delay_beg);
delay = FIOCTRL_DELICATE_DELAY_GET(reg_val, delay_beg);
}
else if (FPIN_DELAY_COARSE_TUNING == type)
{
reg_val &= ~FIOCTRL_ROUGH_DELAY_MASK(delay_beg);
delay = FIOCTRL_ROUGH_DELAY_GET(reg_val, delay_beg);
}
else
{
FASSERT(0);
}
FtOut32(FIOCTRL_REG_BASE_ADDR + pin.reg_off, reg_val);
return;
}
/**
* @name: FPinSetDelayEn
* @msg: 使能/去使能IO引脚延时
* @return {*}
* @param {FPinIndex} pin IO引脚延时设置索引
* @param {FPinDelayDir} dir 输入/输出延时
* @param {boolean} enable TRUE: 使能, FALSE: 去使能
*/
void FPinSetDelayEn(const FPinIndex pin, FPinDelayDir dir, boolean enable)
{
FIOCTRL_ASSERT_DELAY_REG_OFF(pin);
u32 reg_val = FtIn32(FIOCTRL_REG_BASE_ADDR + pin.reg_off);
u32 delay_beg = 0, delay_end = 0;
if (FPIN_OUTPUT_DELAY == dir)
{
delay_beg = FIOCTRL_DELAY_OUT_BEG_OFF(pin.reg_off);
}
else if (FPIN_INPUT_DELAY == dir)
{
delay_beg = FIOCTRL_DELAY_IN_BEG_OFF(pin.reg_off);
}
else
{
FASSERT(0);
}
reg_val &= ~FIOCTRL_DELAY_EN(delay_beg);
if (enable)
{
reg_val |= FIOCTRL_DELAY_EN(delay_beg);
}
FtOut32(FIOCTRL_REG_BASE_ADDR + pin.reg_off, reg_val);
return;
}

81
bsp/phytium/libraries/standalone/board/ft2004/fioctrl.h
View File

@ -1,81 +0,0 @@
/*
* Copyright : (C) 2022 Phytium Information Technology, Inc.
* All Rights Reserved.
*
* This program is OPEN SOURCE software: you can redistribute it and/or modify it
* under the terms of the Phytium Public License as published by the Phytium Technology Co.,Ltd,
* either version 1.0 of the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,but WITHOUT ANY WARRANTY;
* without even the implied warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.
* See the Phytium Public License for more details.
*
*
* FilePath: fioctrl.h
* Date: 2022-02-10 14:53:42
* LastEditTime: 2022-02-18 08:25:35
* Description:  This files is for io-ctrl function definition (io-mux/io-config/io-delay)
*
* Modify History:
* Ver   Who        Date         Changes
* ----- ------     --------    --------------------------------------
* 1.0 zhugengyu 2022/2/22 init commit
*/
#ifndef BOARD_D2000_FIOCTRL_H
#define BOARD_D2000_FIOCTRL_H
#ifdef __cplusplus
extern "C"
{
#endif
/***************************** Include Files *********************************/
#include "ftypes.h"
/************************** Constant Definitions *****************************/
/**************************** Type Definitions *******************************/
/***************** Macros (Inline Functions) Definitions *********************/
#define FIOCTRL_INDEX(offset, func_beg) \
{ \
/* reg_off */ (offset), \
/* reg_bit */ (func_beg) \
}
/************************** Variable Definitions *****************************/
#define FIOCTRL_CRU_CLK_OBV_PAD (FPinIndex)FIOCTRL_INDEX(0x200, 24)
#define FIOCTRL_SPI0_CSN0_PAD (FPinIndex)FIOCTRL_INDEX(0x208, 16)
#define FIOCTRL_SPI0_SCK_PAD (FPinIndex)FIOCTRL_INDEX(0x208, 12)
#define FIOCTRL_SPI0_SO_PAD (FPinIndex)FIOCTRL_INDEX(0x208, 8)
#define FIOCTRL_SPI0_SI_PAD (FPinIndex)FIOCTRL_INDEX(0x208, 4)
#define FIOCTRL_TJTAG_TDI_PAD (FPinIndex)FIOCTRL_INDEX(0x204, 24) /* can0-tx: func 1 */
#define FIOCTRL_SWDITMS_SWJ_PAD (FPinIndex)FIOCTRL_INDEX(0x204, 12) /* can0-rx: func 1 */
#define FIOCTRL_NTRST_SWJ_PAD (FPinIndex)FIOCTRL_INDEX(0x204, 20) /* can1-tx: func 1 */
#define FIOCTRL_SWDO_SWJ_PAD (FPinIndex)FIOCTRL_INDEX(0x204, 8) /* can1-rx: func 1 */
#define FIOCTRL_I2C0_SCL_PAD (FPinIndex)FIOCTRL_INDEX(0x208, 24) /* i2c0-scl: func 0 */
#define FIOCTRL_I2C0_SDA_PAD (FPinIndex)FIOCTRL_INDEX(0x208, 20) /* i2c0-sda: func 0 */
#define FIOCTRL_ALL_PLL_LOCK_PAD (FPinIndex)FIOCTRL_INDEX(0x200, 28) /* i2c1-scl: func 2 */
#define FIOCTRL_CRU_CLK_OBV_PAD (FPinIndex)FIOCTRL_INDEX(0x200, 24) /* i2c1-sda: func 2 */
#define FIOCTRL_SWDO_SWJ_PAD (FPinIndex)FIOCTRL_INDEX(0x204, 8) /* i2c2-scl: func 2 */
#define FIOCTRL_TDO_SWJ_IN_PAD (FPinIndex)FIOCTRL_INDEX(0x204, 4) /* i2c2-sda: func 2 */
#define FIOCTRL_HDT_MB_DONE_STATE_PAD (FPinIndex)FIOCTRL_INDEX(0x204, 0) /* i2c3-scl: func 2 */
#define FIOCTRL_HDT_MB_FAIL_STATE_PAD (FPinIndex)FIOCTRL_INDEX(0x208, 28) /* i2c3-sda: func 2 */
#define FIOCTRL_UART_2_RXD_PAD (FPinIndex)FIOCTRL_INDEX(0x210, 0) /* spi1_csn0: func 1 */
#define FIOCTRL_UART_2_TXD_PAD (FPinIndex)FIOCTRL_INDEX(0x214, 28) /* spi1_sck: func 1 */
#define FIOCTRL_UART_3_RXD_PAD (FPinIndex)FIOCTRL_INDEX(0x214, 24) /* spi1_so: func 1 */
#define FIOCTRL_UART_3_TXD_PAD (FPinIndex)FIOCTRL_INDEX(0x214, 20) /* spi1_si: func 1 */
#define FIOCTRL_QSPI_CSN2_PAD (FPinIndex)FIOCTRL_INDEX(0x214, 8) /* spi1_csn1: func 1 */
#define FIOCTRL_QSPI_CSN3_PAD (FPinIndex)FIOCTRL_INDEX(0x214, 4) /* spi1_csn2: func 1 */
#ifdef __cplusplus
}
#endif
#endif

327
bsp/phytium/libraries/standalone/board/ft2004/fparameters.h
View File

@ -1,327 +0,0 @@
/*
* Copyright : (C) 2022 Phytium Information Technology, Inc.
* All Rights Reserved.
*
* This program is OPEN SOURCE software: you can redistribute it and/or modify it
* under the terms of the Phytium Public License as published by the Phytium Technology Co.,Ltd,
* either version 1.0 of the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,but WITHOUT ANY WARRANTY;
* without even the implied warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.
* See the Phytium Public License for more details.
*
*
* FilePath: fparameters.h
* Date: 2022-02-10 14:53:42
* LastEditTime: 2022-02-17 18:01:11
* Description:  This file is for
*
* Modify History:
* Ver   Who        Date         Changes
* ----- ------     --------    --------------------------------------
*/
#ifndef BSP_ARCH_ARMV8_AARCH64_PLATFORM_FT2004_H
#define BSP_ARCH_ARMV8_AARCH64_PLATFORM_FT2004_H
#ifdef __cplusplus
extern "C"
{
#endif
#if !defined(__ASSEMBLER__)
#include "ftypes.h"
#endif
#define CORE0_AFF 0x0
#define CORE1_AFF 0x1
#define CORE2_AFF 0x100
#define CORE3_AFF 0x101
/* cache */
#define CACHE_LINE_ADDR_MASK 0x3F
#define CACHE_LINE 64U
/* Device register address */
#define FDEV_BASE_ADDR 0x28000000
#define FDEV_END_ADDR 0x2FFFFFFF
/* PCI */
#define FPCIE_NUM 1
#define FPCIE0_ID 0
#define FPCIE0_MISC_IRQ_NUM 59
#define FPCIE_CFG_MAX_NUM_OF_BUS 256
#define FPCIE_CFG_MAX_NUM_OF_DEV 32
#define FPCIE_CFG_MAX_NUM_OF_FUN 8
#define FPCI_CONFIG_BASE_ADDR 0x40000000
#define FPCI_CONFIG_REG_LENGTH 0x10000000
#define FPCI_IO_CONFIG_BASE_ADDR 0x50000000
#define FPCI_IO_CONFIG_REG_LENGTH 0x08000000
#define FPCI_MEM32_BASE_ADDR 0x58000000
#define FPCI_MEM32_REG_LENGTH 0x27ffffff
#define FPCI_MEM64_BASE_ADDR 0x1000000000
#define FPCI_MEM64_REG_LENGTH 0x1000000000
#define FPCI_EU0_C0_CONTROL_BASE_ADDR 0x29000000
#define FPCI_EU0_C1_CONTROL_BASE_ADDR 0x29010000
#define FPCI_EU0_C2_CONTROL_BASE_ADDR 0x29020000
#define FPCI_EU1_C0_CONTROL_BASE_ADDR 0x29030000
#define FPCI_EU1_C1_CONTROL_BASE_ADDR 0x29040000
#define FPCI_EU1_C2_CONTROL_BASE_ADDR 0x29050000
#define FPCI_EU0_CONFIG_BASE_ADDR 0x29100000
#define FPCI_EU1_CONFIG_BASE_ADDR 0x29101000
#define FPCI_INTA_IRQ_NUM 60
#define FPCI_INTB_IRQ_NUM 61
#define FPCI_INTC_IRQ_NUM 62
#define FPCI_INTD_IRQ_NUM 63
#define FPCI_NEED_SKIP 1
/* platform ahci host */
#define PLAT_AHCI_HOST_MAX_COUNT 5
#define AHCI_BASE_0 0
#define AHCI_BASE_1 0
#define AHCI_BASE_2 0
#define AHCI_BASE_3 0
#define AHCI_BASE_4 0
#define AHCI_IRQ_0 0
#define AHCI_IRQ_1 0
#define AHCI_IRQ_2 0
#define AHCI_IRQ_3 0
#define AHCI_IRQ_4 0
// timer
#define GENERIC_TIMER_NS_IRQ_NUM 30
#define COUNTS_PER_SECOND GENERIC_TIMER_CLK_FREQ
// UART
#define FUART_NUM 4
#define FUART_REG_LENGTH 0x18000
#define FUART0_ID 0
#define FUART0_IRQ_NUM 38
#define FUART0_BASE_ADDR 0x28000000
#define FUART0_CLK_FREQ_HZ 48000000
#define FUART1_ID 1
#define FUART1_IRQ_NUM 39
#define FUART1_BASE_ADDR 0x28001000
#define FUART1_CLK_FREQ_HZ 48000000
#define FUART2_ID 2
#define FUART2_IRQ_NUM 40
#define FUART2_BASE_ADDR 0x28002000
#define FUART2_CLK_FREQ_HZ 48000000
#define FUART3_BASE_ADDR 0x28003000
#define FUART3_ID 3
#define FUART3_IRQ_NUM 41
#define FUART3_CLK_FREQ_HZ 48000000
#define FT_STDOUT_BASE_ADDRESS FUART1_BASE_ADDR
#define FT_STDIN_BASE_ADDRESS FUART1_BASE_ADDR
/****** GIC v3 *****/
#define FT_GICV3_INSTANCES_NUM 1U
#define GICV3_REG_LENGTH 0x00009000
/*
* The maximum priority value that can be used in the GIC.
*/
#define GICV3_MAX_INTR_PRIO_VAL 240U
#define GICV3_INTR_PRIO_MASK 0x000000f0U
#define ARM_GIC_IPI_COUNT 16 /* MPCore IPI count */
#define SGI_INT_MAX 16
#define SPI_START_INT_NUM 32 /* SPI start at ID32 */
#define PPI_START_INT_NUM 16 /* PPI start at ID16 */
#define GIC_INT_MAX_NUM 1020 /* GIC max interrupts count */
#define GICV3_BASE_ADDR 0x29900000U
#define GICV3_DISTRIBUTOR_BASE_ADDR (GICV3_BASE_ADDR + 0)
#define GICV3_RD_BASE_ADDR (GICV3_BASE_ADDR + 0x80000U)
#define GICV3_RD_OFFSET (2U << 16)
#define FT_GICV3_VECTORTABLE_NUM GIC_INT_MAX_NUM
/* GPIO */
#define FGPIO0_BASE_ADDR 0x28004000
#define FGPIO1_BASE_ADDR 0x28005000
#define FGPIO0_ID 0
#define FGPIO1_ID 1
#define FGPIO_NUM 2
#define FGPIO0_IRQ_NUM 42 /* gpio0 irq number */
#define FGPIO1_IRQ_NUM 43 /* gpio1 irq number */
/* SPI */
#define FSPI0_BASE_ADDR 0x2800c000
#define FSPI1_BASE_ADDR 0x28013000
#define FSPI0_ID 0
#define FSPI1_ID 1
#define FSPI_CLK_FREQ_HZ 48000000
#define FSPI_NUM 2
#define FSPI0_IRQ_NUM 50
#define FSPI1_IRQ_NUM 51
/* QSPI */
/* QSPI */
#if !defined(__ASSEMBLER__)
typedef enum
{
FQSPI0_ID = 0,
FQSPI_NUM
} FQspiInstance;
/* FQSPI cs 0_3, chip number */
enum
{
FQSPI_CS_0 = 0,
FQSPI_CS_1 = 1,
FQSPI_CS_2 = 2,
FQSPI_CS_3 = 3,
FQSPI_CS_NUM
};
#endif
#define FQSPI_BASE_ADDR 0x28014000
#define FQSPI_MEM_START_ADDR 0x0
#define FQSPI_MEM_END_ADDR 0x1FFFFFFF
/* IOCTRL */
#define FIOCTRL_REG_BASE_ADDR 0x28180000
// Gic
#define ARM_GIC_NR_IRQS 1024
#define ARM_GIC_IRQ_START 0
#define FGIC_NUM 1
/* can */
#if !defined(__ASSEMBLER__)
enum
{
FCAN0_ID = 0,
FCAN1_ID = 1,
FCAN2_ID = 2,
FCAN_NUM
};
#endif
#define FCAN_CLK_FREQ_HZ 600000000
#define FCAN0_BASE_ADDR 0x28207000
#define FCAN1_BASE_ADDR 0x28207400
#define FCAN2_BASE_ADDR 0x28207800
#define FCAN0_IRQ_NUM 119
#define FCAN1_IRQ_NUM 123
#define FCAN2_IRQNUM 124
/* I2C */
#if !defined(__ASSEMBLER__)
enum
{
FI2C0_ID = 0,
FI2C1_ID = 1,
FI2C2_ID,
FI2C3_ID,
FI2C_NUM
};
#endif
#define FI2C0_BASE_ADDR 0x28006000
#define FI2C1_BASE_ADDR 0x28007000
#define FI2C2_BASE_ADDR 0x28008000
#define FI2C3_BASE_ADDR 0x28009000
#define FI2C0_IRQ_NUM 44
#define FI2C1_IRQ_NUM 45
#define FI2C2_IRQ_NUM 46
#define FI2C3_IRQ_NUM 47
#define FI2C_CLK_FREQ_HZ 48000000 /* 48MHz */
/* WDT */
#if !defined(__ASSEMBLER__)
enum
{
FWDT0_ID = 0,
FWDT1_ID = 1,
FWDT_NUM
} ;
#endif
#define FWDT0_REFRESH_BASE_ADDR 0x2800a000
#define FWDT1_REFRESH_BASE_ADDR 0x28016000
#define FWDT_CONTROL_BASE_ADDR(x) ((x)+0x1000)
#define FWDT0_IRQ_NUM 48
#define FWDT1_IRQ_NUM 49
#define FWDT_CLK_FREQ_HZ 48000000 /* 48MHz */
/* SDCI */
#if !defined(__ASSEMBLER__)
enum
{
FSDMMC0_ID = 0,
FSDMMC_NUM
};
#endif
#define FSDMMC0_BASE_ADDR 0x28207C00
#define FSDMMC0_DMA_IRQ_NUM 52
#define FSDMMC0_CMD_IRQ_NUM 53
#define FSDMMC0_ERR_IRQ_NUM 54
#define FSDMMC_CLK_FREQ_HZ 600000000 /* 600 MHz */
#define SDCI_SEN_DEBNCE 10000000 /* 10 MHz */
#define SDCI_CMD_TIMEOUT 10000000 /* 1s */
#define SDCI_DATA_TIMEOUT 40000000 /* 4S */
/* GMAC */
#if !defined(__ASSEMBLER__)
enum
{
FGMAC0_ID = 0,
FGMAC1_ID,
FGMAC_NUM
};
#endif
#define FGMAC_PUB_REG_BASE_ADDR 0x2820B000 /* 公共寄存器基地址 */
#define FGMAC0_BASE_ADDR 0x2820C000
#define FGMAC1_BASE_ADDR 0x28210000
#define FGMAC0_IRQ_NUM 81
#define FGMAC1_IRQ_NUM 82
#define FGMAC_DMA_MIN_ALIGN 128
#define FGMAC_MAX_PACKET_SIZE 1600
/*RTC*/
#define RTC_CONTROL_BASE 0x2800D000
#define FT_CPUS_NR CORE_NUM
#ifdef __cplusplus
}
#endif
#endif // !

61
bsp/phytium/libraries/standalone/common/Kconfig
View File

@ -1,7 +1,6 @@
menu "Sdk common configuration"
choice DEBUG_LOG_LEVEL
prompt "Debug Log Level"
prompt "Debug log level"
default LOG_ERROR
help
VERBOS: Print bigger chunks of debugging information
@ -11,20 +10,40 @@ choice DEBUG_LOG_LEVEL
ERROR: Print critical errors, software module can not recover on its own
config LOG_VERBOS
bool "VERBOS"
bool "Verbos"
config LOG_DEBUG
bool "DEBUG"
bool "Debug"
config LOG_INFO
bool "INFO"
bool "Info"
config LOG_WARN
bool "WARN"
bool "Warn"
config LOG_ERROR
bool "ERROR"
bool "Error"
config LOG_NONE
bool "NONE"
bool "None"
endchoice # DEBUG_LOG_LEVEL
config LOG_EXTRA_INFO
bool "Debug log with extra info"
default n
help
Print debug information with source file name and source code line num.
config LOG_DISPALY_CORE_NUM
bool "Debug display with core"
default n
help
To display CPU core information during debugging
config BOOTUP_DEBUG_PRINTS
bool
prompt "Bootup debug"
default n
help
Enable Bootup debug printing
config USE_DEFAULT_INTERRUPT_CONFIG
bool
@ -40,30 +59,12 @@ config USE_DEFAULT_INTERRUPT_CONFIG
"Select Interrupt role"
config INTERRUPT_ROLE_MASTER
bool "use master role"
bool "Use master role"
config INTERRUPT_ROLE_SLAVE
bool "use slave role"
bool "Use slave role"
endchoice # INTERRUPT_ROLE_SELECT
endif
config LOG_EXTRA_INFO
bool "Debug Log with Extra Info"
default n
help
Print debug information with source file name and source code line num.
config LOG_DISPALY_CORE_NUM
bool "Debug Display with Core"
default n
help
To display CPU core information during debugging
config BOOTUP_DEBUG_PRINTS
bool
prompt "Bootup debug"
default n
help
Enable Bootup debug printing
endmenu

4
bsp/phytium/libraries/standalone/common/fdebug.h
View File

@ -33,9 +33,7 @@
#include "fsmp.h"
#endif
#if defined(CONFIG_USE_AMP)
#include "fcpu_info.h"
#endif
#ifdef __cplusplus
@ -133,7 +131,7 @@ typedef enum
{ \
if (LOG_LOCAL_LEVEL < log_level) \
break; \
DISPALY_CORE_NUM() \
DISPALY_CORE_NUM(); \
PORT_KPRINTF(LOG_FORMAT(log_tag_letter, format" @%s:%d"), tag, ##__VA_ARGS__, __FILENAME__, __LINE__); \
} while (0)
#endif

237
bsp/phytium/libraries/standalone/common/felf.c
View File

@ -1,25 +1,26 @@
/*
* Copyright : (C) 2022 Phytium Information Technology, Inc.
* @Copyright : (C) 2022 Phytium Information Technology, Inc.
* All Rights Reserved.
*
* This program is OPEN SOURCE software: you can redistribute it and/or modify it
* under the terms of the Phytium Public License as published by the Phytium Technology Co.,Ltd,
* either version 1.0 of the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,but WITHOUT ANY WARRANTY;
*
* This program is OPEN SOURCE software: you can redistribute it and/or modify it
* under the terms of the Phytium Public License as published by the Phytium Technology Co.,Ltd,
* either version 1.0 of the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,but WITHOUT ANY WARRANTY;
* without even the implied warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.
* See the Phytium Public License for more details.
*
*
* FilePath: felf.c
* Date: 2021-08-31 11:16:59
* LastEditTime: 2022-02-17 18:05:16
* See the Phytium Public License for more details.
*
*
* @FilePath: felf.c
* @Date: 2023-05-25 19:27:49
* @LastEditTime: 2023-06-05 14:11:48
* Description:  This file is for providing elf functions.
*
* Modify History:
* Ver   Who        Date         Changes
* ----- ------     --------    --------------------------------------
* 1.0 zhugengyu 2022/10/27 rename file name
* 1.1 huanghe 2023/06/05 add get section information
*/
#include <string.h>
@ -731,6 +732,7 @@ static unsigned long ElfLoadElf64ImagePhdr(unsigned long addr)
{
Elf64_Ehdr *ehdr; /* Elf header structure pointer */
Elf64_Phdr *phdr; /* Program header structure pointer */
int i;
ehdr = (Elf64_Ehdr *)addr;
@ -742,7 +744,7 @@ static unsigned long ElfLoadElf64ImagePhdr(unsigned long addr)
void *dst = (void *)(unsigned long)phdr->p_paddr;
void *src = (void *)addr + phdr->p_offset;
f_printk("Loading phdr %i to 0x%p (%lu bytes)",
f_printk("Loading phdr %i to %p (%lu bytes) \r\n",
i, dst, (unsigned long)phdr->p_filesz);
if (phdr->p_filesz)
{
@ -774,6 +776,8 @@ static unsigned long ElfLoadElf64ImagePhdr(unsigned long addr)
return ehdr->e_entry;
}
static unsigned long ElfLoadElf64ImageShdr(unsigned long addr)
{
Elf64_Ehdr *ehdr; /* Elf header structure pointer */
@ -807,7 +811,7 @@ static unsigned long ElfLoadElf64ImageShdr(unsigned long addr)
if (strtab)
{
f_printk("%sing %s @ 0x%08lx (%ld bytes)",
f_printk("%sing %s @ 0x%08lx (%ld bytes) \r\n",
(shdr->sh_type == SHT_NOBITS) ? "Clear" : "Load",
&strtab[shdr->sh_name],
(unsigned long)shdr->sh_addr,
@ -864,7 +868,7 @@ unsigned long ElfLoadElfImagePhdr(unsigned long addr)
void *dst = (void *)(uintptr)phdr->p_paddr;
void *src = (void *)addr + phdr->p_offset;
f_printk("Loading phdr %i to 0x%p (%i bytes)",
f_printk("Loading phdr %i to %p (%i bytes)",
i, dst, phdr->p_filesz);
if (phdr->p_filesz)
{
@ -958,13 +962,11 @@ int ElfIsImageValid(unsigned long addr)
if (!IS_ELF(*ehdr))
{
f_printk("## No elf image at address 0x%08lx.", addr);
return 0;
}
if (ehdr->e_type != ET_EXEC)
{
f_printk("## Not a 32-bit elf image at address 0x%08lx.", addr);
return 0;
}
@ -984,4 +986,201 @@ unsigned long ElfExecBootElf(unsigned long (*entry)(int, char *const[]),
ret = entry(argc, argv);
return ret;
}
}
/**
* @name: Elf64GetTargetSection
* @msg: 从ELF文件中获取指定名称的section的数据
* @return: FError，表示函数执行结果的错误码
* @note:
* @param {Elf64_Ehdr} *ehdr，指向ELF文件头的指针
* @param {char} *section_name，指定的section名称
* @param {u8} *data_get，用于存储获取到的section数据的缓冲区指针
* @param {u32} *length_p，用于存储获取到的section数据长度的指针
*/
static FError Elf64GetTargetSection(unsigned long addr,char *section_name ,u8 *data_get,u32 *length_p)
{
Elf64_Ehdr *ehdr; /* Elf header structure pointer */
Elf64_Shdr *shdr; /* Section header structure pointer */
unsigned char *strtab = 0; /* String table pointer */
unsigned char *image; /* Binary image pointer */
int i; /* Loop counter */
ehdr = (Elf64_Ehdr *)addr;
/* Find the section header string table for output info */
shdr = (Elf64_Shdr *)(addr + (unsigned long)ehdr->e_shoff +
(ehdr->e_shstrndx * sizeof(Elf64_Shdr)));
if (shdr->sh_type == SHT_STRTAB)
{
strtab = (unsigned char *)(addr + (unsigned long)shdr->sh_offset);
}
else
{
f_printk("There is no string table \r\n");
return FELF_SECTION_NO_STRTAB;
}
/* Load each appropriate section */
for (i = 0; i < ehdr->e_shnum; ++i)
{
shdr = (Elf64_Shdr *)(addr + (unsigned long)ehdr->e_shoff +
(i * sizeof(Elf64_Shdr)));
if (!(shdr->sh_flags & SHF_ALLOC) ||
shdr->sh_addr == 0 || shdr->sh_size == 0)
{
continue;
}
if(strcmp(section_name, &strtab[shdr->sh_name]) == 0)
{
f_printk("%sing %s @ 0x%08lx (%ld bytes) \r\n",
(shdr->sh_type == SHT_NOBITS) ? "Clear" : "Load",
&strtab[shdr->sh_name],
(unsigned long)shdr->sh_addr,
(long)shdr->sh_size);
if(shdr->sh_type == SHT_NOBITS)
{
f_printk("There is no space section \r\n");
return FELF_SECTION_NO_SPACE;
}
printf("*length_p is %d \r\n",*length_p);
if (shdr->sh_size < *length_p)
{
*length_p = shdr->sh_size;
}
image = (unsigned char *)addr + (unsigned long)shdr->sh_offset;
memcpy((void *)(uintptr)data_get,
(const void *)image, *length_p);
return FELF_SUCCESS;
}
}
f_printk("%s: No %s section exists in this elf file \r\n",__func__,section_name);
return FELF_SECTION_NOT_FIT;
}
/**
* @name:
* @msg:
* @return {*}
* @note:
* @param {Elf32_Shdr} *ehdr
* @param {char} *section_name
* @param {u8} *data_get
* @param {u32} *length_p
*/
static FError Elf32GetTargetSection(unsigned long addr,char *section_name ,u8 *data_get,u32 *length_p)
{
Elf32_Ehdr *ehdr; /* Elf header structure pointer */
Elf32_Shdr *shdr; /* Section header structure pointer */
unsigned char *strtab = 0; /* String table pointer */
unsigned char *image; /* Binary image pointer */
int i; /* Loop counter */
ehdr = (Elf32_Ehdr *)addr;
/* Find the section header string table for output info */
shdr = (Elf32_Shdr *)(addr + ehdr->e_shoff +
(ehdr->e_shstrndx * sizeof(Elf32_Shdr)));
if (shdr->sh_type == SHT_STRTAB)
{
strtab = (unsigned char *)(addr + shdr->sh_offset);
}
else
{
f_printk("There is no string table \r\n");
return FELF_SECTION_NO_STRTAB;
}
/* Load each appropriate section */
for (i = 0; i < ehdr->e_shnum; ++i)
{
shdr = (Elf32_Shdr *)(addr + ehdr->e_shoff +
(i * sizeof(Elf32_Shdr)));
if (!(shdr->sh_flags & SHF_ALLOC) ||
shdr->sh_addr == 0 || shdr->sh_size == 0)
{
continue;
}
if (strcmp(section_name, &strtab[shdr->sh_name]) == 0)
{
printf("%sing %s @ 0x%08lx (%ld bytes)",
(shdr->sh_type == SHT_NOBITS) ? "Clear" : "Load",
&strtab[shdr->sh_name],
(unsigned long)shdr->sh_addr,
(long)shdr->sh_size);
printf("copy num is \r\n");
printf("*length_p is %d \r\n",*length_p);
if(shdr->sh_size < *length_p)
{
*length_p = shdr->sh_size;
}
image = (unsigned char *)addr + (unsigned long)shdr->sh_offset;
memcpy((void *)(uintptr)data_get,
(const void *)image, *length_p);
return FELF_SUCCESS;
}
}
f_printk("%s: No %s section exists in this elf file \r\n",__func__,section_name);
return FELF_SECTION_NOT_FIT;
}
/**
* @name: ElfGetSection
* @msg: 获取 ELF 文件中指定节的内容
* @return {FError} 返回错误码，表示获取节内容的结果
* @note: 函数将根据 ELF 文件的类型（32位或64位）调用相应的函数来获取指定节的内容。
* @param {unsigned long} addr ELF 文件的基地址
* @param {char*} section_name 节的名称
* @param {u8*} data_get 用于存储节内容的缓冲区
* @param {u32*} length_p 存储获取到的节内容的长度
*/
FError ElfGetSection(unsigned long addr, char *section_name, u8 *data_get, u32 *length_p)
{
Elf32_Ehdr *ehdr; /* ELF 文件头指针 */
Elf32_Shdr *shdr; /* 节头指针 */
unsigned char *strtab = 0; /* 字符串表指针 */
unsigned char *image; /* 二进制映像指针 */
int i; /* 循环计数器 */
/* 检查 ELF 文件的类型 */
ehdr = (Elf32_Ehdr *)addr;
if (ehdr->e_ident[EI_CLASS] == ELFCLASS64)
{
/* 如果是64位 ELF，则调用 Elf64GetTargetSection 函数获取指定节的内容 */
return Elf64GetTargetSection(addr, section_name, data_get, length_p);
}
/* 如果是32位 ELF，则调用 Elf32GetTargetSection 函数获取指定节的内容 */
if (ehdr->e_ident[EI_CLASS] == ELFCLASS32)
{
return Elf32GetTargetSection(addr, section_name, data_get, length_p);
}
/* 若未匹配到有效的 ELF 类型，则返回 FELF_SECTION_GET_ERROR 错误码 */
return FELF_SECTION_GET_ERROR;
}

9
bsp/phytium/libraries/standalone/common/felf.h
View File

@ -26,18 +26,27 @@
#define FELF_H
#include "ftypes.h"
#include "ferror_code.h"
#ifdef __cplusplus
extern "C"
{
#endif
#define FELF_SUCCESS FT_SUCCESS /* SUCCESS */
#define FELF_SECTION_NO_STRTAB FT_MAKE_ERRCODE(ErrorModGeneral, ErrElf, 1) /* There is no string table */
#define FELF_SECTION_NO_SPACE FT_MAKE_ERRCODE(ErrorModGeneral, ErrElf, 2) /* There is no space section */
#define FELF_SECTION_NOT_FIT FT_MAKE_ERRCODE(ErrorModGeneral, ErrElf, 3) /* No corresponding section was matched */
#define FELF_SECTION_GET_ERROR FT_MAKE_ERRCODE(ErrorModGeneral, ErrElf, 3)
unsigned long ElfLoadElfImagePhdr(unsigned long addr);
unsigned long ElfLoadElfImageShdr(unsigned long addr);
int ElfIsImageValid(unsigned long addr);
unsigned long ElfExecBootElf(unsigned long (*entry)(int, char *const[]),
int argc, char *const argv[]);
FError ElfGetSection(unsigned long addr, char *section_name, u8 *data_get, u32 *length_p);
#ifdef __cplusplus
}
#endif

2
bsp/phytium/libraries/standalone/common/ferror_code.h
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@ -52,6 +52,7 @@ typedef enum
ErrCommGeneral = 0,
ErrCommMemp,
ErrInterrupt,
ErrElf,
} FtErrCodeCommMask;
/* BSP模块的错误子模块定义 */
@ -86,6 +87,7 @@ typedef enum
ErrSema,
ErrBspMEDIA,
ErrBspMhu,
ErrBspIOPad,
ErrBspModMaxMask = 255
} FtErrCodeBspMask;

66
bsp/phytium/libraries/standalone/common/fpinctrl.h
View File

@ -34,24 +34,7 @@ extern "C"
#include "sdkconfig.h"
#if defined(CONFIG_TARGET_F2000_4) || defined(CONFIG_TARGET_D2000)
#ifndef FPIN_IO_CTRL
#define FPIN_IO_CTRL
#endif
#endif
#if defined(CONFIG_TARGET_E2000) || defined(CONFIG_TARGET_TARDIGRADE)
#ifndef FPIN_IO_PAD
#define FPIN_IO_PAD
#endif
#endif
#if defined(FPIN_IO_CTRL)
#include "fioctrl.h"
#endif
#if defined(FPIN_IO_PAD)
#include "fiopad.h"
#endif
/**************************** Type Definitions *******************************/
@ -61,39 +44,10 @@ typedef enum
FPIN_FUNC1,
FPIN_FUNC2,
FPIN_FUNC3 = 0b011,
#if defined(FPIN_IO_PAD) /* E2000 support more pin func */
FPIN_FUNC4,
FPIN_FUNC5,
FPIN_FUNC6,
FPIN_FUNC7 = 0b111,
#endif
FPIN_NUM_OF_FUNC
} FPinFunc; /* 引脚复用功能配置, func0为默认功能 */
#if defined(FPIN_IO_PAD) /* Only support driver strength config in E2000 */
typedef enum
{
FPIN_DRV0 = 0b0000,
FPIN_DRV1,
FPIN_DRV2,
FPIN_DRV3,
FPIN_DRV4,
FPIN_DRV5,
FPIN_DRV6,
FPIN_DRV7,
FPIN_DRV8,
FPIN_DRV9,
FPIN_DRV10,
FPIN_DRV11,
FPIN_DRV12,
FPIN_DRV13,
FPIN_DRV14,
FPIN_DRV15 = 0b1111,
FPIN_NUM_OF_DRIVE
} FPinDrive; /* 引脚驱动能力配置 */
#endif
typedef enum
{
FPIN_PULL_NONE = 0b00,
@ -162,29 +116,12 @@ FPinPull FPinGetPull(const FPinIndex pin);
/* 设置IO引脚的上下拉 */
void FPinSetPull(const FPinIndex pin, FPinPull pull);
#if defined(FPIN_IO_PAD)
/* 获取IO引脚的驱动能力 */
FPinDrive FPinGetDrive(const FPinIndex pin);
/* 设置IO引脚的驱动能力 */
void FPinSetDrive(const FPinIndex pin, FPinDrive drive);
/* 获取IO引脚的复用、上下拉和驱动能力设置 */
void FPinGetConfig(const FPinIndex pin, FPinFunc *func, FPinPull *pull, FPinDrive *drive);
/* 设置IO引脚的复用、上下拉和驱动能力 */
void FPinSetConfig(const FPinIndex pin, FPinFunc func, FPinPull pull, FPinDrive drive);
#else
/* 获取IO引脚的复用、上下拉和驱动能力设置 */
void FPinGetConfig(const FPinIndex pin, FPinFunc *func, FPinPull *pull);
/* 设置IO引脚的复用、上下拉和驱动能力 */
void FPinSetConfig(const FPinIndex pin, FPinFunc func, FPinPull pull);
#endif
/* 获取IO引脚当前的单项延时设置 */
FPinDelay FPinGetDelay(const FPinIndex pin, FPinDelayDir dir, FPinDelayType type);
@ -208,4 +145,5 @@ void FPinGetDelayConfig(const FPinIndex pin, FPinDelay *in_roungh_delay, FPinDel
}
#endif
#endif
#endif

2
bsp/phytium/libraries/standalone/common/fprintk.c
View File

@ -404,7 +404,7 @@ start:
}
}
static void f_vprintf(const char *restrict format, va_list vargs)
static int f_vprintf(const char *restrict format, va_list vargs)
{
struct str_context ctx = {0};
cbvprintf(char_out, &ctx, format, vargs);

344
bsp/phytium/libraries/standalone/common/fpsci.c Normal file
View File

@ -0,0 +1,344 @@
/*
* Copyright : (C) 2023 Phytium Information Technology, Inc.
* All Rights Reserved.
*
* This program is OPEN SOURCE software: you can redistribute it and/or modify it
* under the terms of the Phytium Public License as published by the Phytium Technology Co.,Ltd,
* either version 1.0 of the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,but WITHOUT ANY WARRANTY;
* without even the implied warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.
* See the Phytium Public License for more details.
*
*
* FilePath: fpsci.c
* Created Date: 2023-06-21 10:36:53
* Last Modified: 2023-06-30 13:32:06
* Description: This file is for
*
* Modify History:
* Ver Who Date Changes
* ----- ---------- -------- ---------------------------------
* 1.0 huanghe 2023-06-21 first release
*/
#include <stdio.h>
#include "fsmcc.h" /* 根据你的平台和编译环境来确定这个路径 */
#include "fpsci.h"
#include "fassert.h"
#include "fcompiler.h"
#include "fdebug.h"
#include "fcpu_info.h"
#define FPSCI_DEBUG_TAG "FPSCI"
#define FPSCI_DEBUG(format, ...) FT_DEBUG_PRINT_D(FPSCI_DEBUG_TAG, format, ##__VA_ARGS__)
#define FPSCI_INFO(format, ...) FT_DEBUG_PRINT_I(FPSCI_DEBUG_TAG, format, ##__VA_ARGS__)
#define FPSCI_WARN(format, ...) FT_DEBUG_PRINT_W(FPSCI_DEBUG_TAG, format, ##__VA_ARGS__)
#define FPSCI_ERROR(format, ...) FT_DEBUG_PRINT_E(FPSCI_DEBUG_TAG, format, ##__VA_ARGS__)
/* 定义PSCI 函数值 */
#define FPSCI_0_2_FN32_BASE 0x84000000
#define FPSCI_0_2_FN64_BASE 0xC4000000
#define FPSCI_VERSION (FPSCI_0_2_FN32_BASE + 0x000)
#define FPSCI_FEATURES (FPSCI_0_2_FN32_BASE + 0x00a)
#define FPSCI_CPU_SUSPEND_AARCH32 (FPSCI_0_2_FN32_BASE + 0x001)
#define FPSCI_CPU_SUSPEND_AARCH64 (FPSCI_0_2_FN64_BASE + 0x001)
#define FPSCI_CPU_OFF (FPSCI_0_2_FN32_BASE + 0x002)
#define FPSCI_CPU_ON_AARCH32 (FPSCI_0_2_FN32_BASE + 0x003)
#define FPSCI_CPU_ON_AARCH64 (FPSCI_0_2_FN64_BASE + 0x003)
#define FPSCI_FAFFINITY_INFO_AARCH32 (FPSCI_0_2_FN32_BASE + 0x004)
#define FPSCI_FAFFINITY_INFO_AARCH64 (FPSCI_0_2_FN64_BASE + 0x004)
#define FPSCI_SYSTEM_OFF (FPSCI_0_2_FN32_BASE + 0x008)
#define FPSCI_SYSTEM_RESET (FPSCI_0_2_FN32_BASE + 0x009)
#define FPSCI_SYSTEM_SUSPEND (FPSCI_0_2_FN32_BASE + 0x00E)
/* 定义每个PSCI函数ID的位标记 */
#define FPSCI_PSCI_VERSION_BIT (1 << 0)
#define FPSCI_PSCI_FEATURES_BIT (1 << 1)
#define FPSCI_CPU_SUSPEND_AARCH32_BIT (1 << 2)
#define FPSCI_CPU_SUSPEND_AARCH64_BIT (1 << 3)
#define FPSCI_CPU_OFF_BIT (1 << 4)
#define FPSCI_CPU_ON_AARCH32_BIT (1 << 5)
#define FPSCI_CPU_ON_AARCH64_BIT (1 << 6)
#define FPSCI_AFFINITY_INFO_AARCH32_BIT (1 << 7)
#define FPSCI_AFFINITY_INFO_AARCH64_BIT (1 << 8)
#define FPSCI_SYSTEM_OFF_BIT (1 << 9)
#define FPSCI_SYSTEM_RESET_BIT (1 << 10)
static int fpsci_ringt_bit_flg = 0;
/* 定义函数指针 */
typedef void (*FPsciInvokeFun)(unsigned long arg0, unsigned long arg1,
unsigned long arg2, unsigned long arg3,
unsigned long arg4, unsigned long arg5,
unsigned long arg6, unsigned long arg7,
struct FSmcccRes *res);
/* 为函数指针初始化为默认的函数 */
FPsciInvokeFun f_psci_invoke = FSmcccSmcCall;
/**
* @name: FPsciVersion
* @msg: Get the version of the PSCI implementation.
* @return {int}: The version information of the PSCI implementation.
* @note: This function returns the version information obtained from the PSCI VERSION function.
*/
int FPsciVersion(void) {
struct FSmcccRes res;
FASSERT((*f_psci_invoke));
(*f_psci_invoke)(FPSCI_VERSION, 0, 0, 0, 0, 0, 0, 0, &res);
return res.a0;
}
/**
* @name: FPsciFeatures
* @msg: Check whether a PSCI function is supported.
* @param {u32} psci_fid: The function ID of the PSCI function to be checked.
* @return {int}: 1 if the function is supported; 0 otherwise.
* @note: This function returns whether the PSCI function represented by psci_fid is supported or not.
*/
int FPsciFeatures(u32 psci_fid) {
struct FSmcccRes res;
FASSERT((*f_psci_invoke));
(*f_psci_invoke)(FPSCI_FEATURES, psci_fid, 0, 0, 0, 0, 0, 0, &res);
return res.a0 == FPSCI_SUCCESS ? 1 : 0;
}
/**
* @name: FPsciCpuSuspend
* @msg: Suspend execution on a particular CPU.
* @param {u32} power_state: The power state to be entered.
* @param {unsigned long} entry_point_address: The address to be executed upon waking up.
* @param {unsigned long} context_id: The context-specific identifier.
* @return {int}: The status code of the operation, as defined by the PSCI specification.
* @note: This function suspends the execution on a particular CPU and returns a status code indicating whether the operation was successful or not.
*/
int FPsciCpuSuspend(u32 power_state, unsigned long entry_point_address, unsigned long context_id) {
struct FSmcccRes res;
FASSERT((fpsci_ringt_bit_flg & FPSCI_CPU_SUSPEND_AARCH32_BIT) != 0);
FASSERT((*f_psci_invoke));
(*f_psci_invoke)(FPSCI_CPU_SUSPEND_AARCH32, power_state, entry_point_address, context_id, 0, 0, 0, 0, &res);
return res.a0;
}
/**
* @name: FPsciCpuOn
* @msg: Power on a particular CPU.
* @param {unsigned long} target_cpu: The target CPU to be powered on.
* @param {unsigned long} entry_point_address: The address to be executed upon waking up.
* @param {unsigned long} context_id: The context-specific identifier.
* @return {int}: The status code of the operation, as defined by the PSCI specification.
* @note: This function powers on a particular CPU and returns a status code indicating whether the operation was successful or not.
*/
int FPsciCpuOn(unsigned long target_cpu, unsigned long entry_point_address, unsigned long context_id) {
struct FSmcccRes res;
unsigned long cpu_on_id ;
#if defined(FAARCH64_USE)
cpu_on_id = FPSCI_CPU_ON_AARCH64 ;
#else
cpu_on_id = FPSCI_CPU_ON_AARCH32;
#endif
FASSERT((fpsci_ringt_bit_flg & (FPSCI_CPU_ON_AARCH32_BIT|FPSCI_CPU_ON_AARCH64_BIT)) != 0);
FASSERT((*f_psci_invoke));
(*f_psci_invoke)(cpu_on_id, target_cpu, entry_point_address, context_id, 0, 0, 0, 0, &res);
return res.a0;
}
/**
* @name: FPsciCpuOff
* @msg: This is a wrapper for the PSCI CPU Off interface, intended to turn off the current CPU.
* @return: Returns the 'a0' field of the 'FSmcccRes' structure, indicating the result of the call. A return value of 0 (PSCI_SUCCESS) indicates success, any other value indicates an error occurred.
* @note: A core that is powered down by CPU_OFF can only be powered up again in response to a CPU_ON.
*/
int FPsciCpuOff(void) {
struct FSmcccRes res;
FASSERT((fpsci_ringt_bit_flg & FPSCI_CPU_OFF_BIT) != 0);
FASSERT((*f_psci_invoke));
(*f_psci_invoke)(FPSCI_CPU_OFF, 0, 0, 0, 0, 0, 0, 0, &res);
return res.a0;
}
/**
* @name: FPsciAffinityInfo
* @msg: Get the power state of a particular affinity level.
* @param {unsigned long} target_affinity: The target affinity level.
* @param {u32} lowest_affinity_level: The lowest affinity level.
* @return {int}: The power state of the specified affinity level, as defined by the PSCI specification.
* @note: This function returns the power state of a particular affinity level.
*/
int FPsciAffinityInfo(unsigned long target_affinity, u32 lowest_affinity_level) {
struct FSmcccRes res;
FASSERT((fpsci_ringt_bit_flg & (FPSCI_AFFINITY_INFO_AARCH32_BIT|FPSCI_AFFINITY_INFO_AARCH64_BIT)) != 0);
FASSERT((*f_psci_invoke));
unsigned long cpu_on_id ;
#if defined(FAARCH64_USE)
cpu_on_id = FPSCI_CPU_ON_AARCH64 ;
#else
cpu_on_id = FPSCI_CPU_ON_AARCH32;
#endif
(*f_psci_invoke)(FPSCI_FAFFINITY_INFO_AARCH32, target_affinity, lowest_affinity_level, 0, 0, 0, 0, 0, &res);
return res.a0;
}
/**
* @name: FPsciSystemReset
* @msg: Reset the system.
* @param {u32} reset_type: The type of the system reset (cold/warm).
* @note: This function resets the system. The reset type is specified by the parameter reset_type.
*/
void FPsciSystemReset(u32 reset_type) {
struct FSmcccRes res;
FASSERT((fpsci_ringt_bit_flg & FPSCI_SYSTEM_RESET_BIT) != 0);
FASSERT((*f_psci_invoke));
(*f_psci_invoke)(FPSCI_SYSTEM_RESET, reset_type, 0, 0, 0, 0, 0, 0, &res);
}
/**
* @name: FPsciCheckFeatures
* @msg: This function checks for the availability of various PSCI features and sets the corresponding bits in the 'fpsci_ringt_bit_flg' global flag accordingly.
* @return: This function does not return a value.
*/
static void FPsciCheckFeatures(void)
{
FPSCI_INFO("Checking PSCI features...\r\n");
fpsci_ringt_bit_flg = 0 ;
if (FPsciFeatures(FPSCI_CPU_SUSPEND_AARCH32))
{
fpsci_ringt_bit_flg |= FPSCI_CPU_SUSPEND_AARCH32_BIT;
FPSCI_INFO("CPU_SUSPEND_AARCH32 supported.\r\n");
}
else
{
FPSCI_ERROR("CPU_SUSPEND_AARCH32 not supported.\r\n");
}
if (FPsciFeatures(FPSCI_CPU_OFF))
{
fpsci_ringt_bit_flg |= FPSCI_CPU_OFF_BIT;
FPSCI_INFO("CPU_OFF supported.\r\n");
}
else
{
FPSCI_ERROR("CPU_OFF not supported.\r\n");
}
#if defined(FAARCH64_USE)
if (FPsciFeatures(FPSCI_CPU_ON_AARCH64))
{
fpsci_ringt_bit_flg |= FPSCI_CPU_ON_AARCH64_BIT;
FPSCI_INFO("CPU_ON_AARCH64 supported.\r\n");
}
else
{
FPSCI_ERROR("CPU_ON_AARCH64 not supported.\r\n");
}
#else
if (FPsciFeatures(FPSCI_CPU_ON_AARCH32))
{
fpsci_ringt_bit_flg |= FPSCI_CPU_ON_AARCH32_BIT;
FPSCI_INFO("CPU_ON_AARCH32 supported.\r\n");
}
else
{
FPSCI_ERROR("CPU_ON_AARCH32 not supported.\r\n");
}
#endif
#if defined(FAARCH64_USE)
if (FPsciFeatures(FPSCI_FAFFINITY_INFO_AARCH64))
{
fpsci_ringt_bit_flg |= FPSCI_AFFINITY_INFO_AARCH64_BIT;
FPSCI_INFO("AFFINITY_INFO_AARCH64 supported.\r\n");
}
else
{
FPSCI_ERROR("AFFINITY_INFO_AARCH64 not supported.\r\n");
}
#else
if (FPsciFeatures(FPSCI_FAFFINITY_INFO_AARCH32))
{
fpsci_ringt_bit_flg |= FPSCI_AFFINITY_INFO_AARCH32_BIT;
FPSCI_INFO("FPSCI_AFFINITY_INFO_AARCH32 supported.\r\n");
}
else
{
FPSCI_ERROR("AFFINITY_INFO_AARCH32 not supported.\r\n");
}
#endif
if (FPsciFeatures(FPSCI_SYSTEM_OFF))
{
fpsci_ringt_bit_flg |= FPSCI_SYSTEM_OFF_BIT;
FPSCI_INFO("SYSTEM_OFF supported.\r\n");
}
else
{
FPSCI_ERROR("SYSTEM_OFF not supported.\r\n");
}
if (FPsciFeatures(FPSCI_SYSTEM_RESET))
{
fpsci_ringt_bit_flg |= FPSCI_SYSTEM_RESET_BIT;
FPSCI_INFO("SYSTEM_RESET supported.\r\n");
}
else
{
FPSCI_ERROR("SYSTEM_RESET not supported.\r\n");
}
}
/**
* @name: FPsci_CpuOn
* @msg: Power up a core
* @in param cpu_id_mask: cpu id mask
* @in param bootaddr: a 32-bit entry point physical address (or IPA).
* @return int
*/
int FPsciCpuMaskOn(s32 cpu_id_mask, uintptr bootaddr)
{
FError ret ;
u64 cluster = 0;
ret = GetCpuAffinityByMask(cpu_id_mask, &cluster);
if (ret != ERR_SUCCESS)
{
return FPSCI_INVALID_PARAMS;
}
return FPsciCpuOn(cluster,(unsigned long)bootaddr,0) ;
}
static void FSmccInit(int method) {
if (method == 1) {
f_psci_invoke = FSmcccHvcCall;
}
else
{
f_psci_invoke = FSmcccSmcCall;
}
}
int FPsciInit(void) {
int psci_version = 0;
FSmccInit(0);
psci_version = FPsciVersion() ;
FPSCI_INFO("major is 0x%x,minor is 0x%x \r\n", FPSCI_MAJOR_VERSION(psci_version),FPSCI_MINOR_VERSION(psci_version)) ;
FPsciCheckFeatures();
return 0;
}

89
bsp/phytium/libraries/standalone/common/fpsci.h Normal file
View File

@ -0,0 +1,89 @@
/*
* Copyright : (C) 2023 Phytium Information Technology, Inc.
* All Rights Reserved.
*
* This program is OPEN SOURCE software: you can redistribute it and/or modify it
* under the terms of the Phytium Public License as published by the Phytium Technology Co.,Ltd,
* either version 1.0 of the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,but WITHOUT ANY WARRANTY;
* without even the implied warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.
* See the Phytium Public License for more details.
*
*
* FilePath: fpsci.h
* Created Date: 2023-06-21 16:13:14
* Last Modified: 2023-06-27 15:33:23
* Description: This file is for
*
* Modify History:
* Ver Who Date Changes
* ----- ---------- -------- ---------------------------------
* 1.0 huanghe 2023-06-21 first release
*/
#ifndef FPSCI_H
#define FPSCI_H
#ifdef __cplusplus
extern "C"
{
#endif
#include "ftypes.h"
/* 版本掩码 */
#define FPSCI_VERSION_MASK 0x0000FFFF
#define FPSCI_MAJOR_VERSION(x) ((x) >> 16)
#define FPSCI_MINOR_VERSION(x) ((x) & 0xFFFF)
/* Power State 参数 */
#define FPSCI_POWER_STATE_ID_MASK 0xFFFF
#define FPSCI_POWER_STATE_ID_SHIFT 0
#define FPSCI_POWER_STATE_TYPE_SHIFT 16
#define FPSCI_POWER_STATE_AFFL_SHIFT 24
/* stateid encoding */
#define FPSCI_STATEID_CORE_RETENTION 0x2
#define FPSCI_STATEID_CORE_POWERDOWN 0x8
/* 版本掩码 */
#define FPSCI_VERSION_MASK 0x0000FFFF
/* 定义复位模式 */
#define FPSCI_SYSTEM_RESET_TYPE_COLD 0
#define FPSCI_SYSTEM_RESET_TYPE_WARM 1
/* 定义PSCI 错误码 */
#define FPSCI_SUCCESS 0
#define FPSCI_NOT_SUPPORTED -1
#define FPSCI_INVALID_PARAMS -2
#define FPSCI_DENIED -3
#define FPSCI_ALREADY_ON -4
#define FPSCI_ON_PENDING -5
#define FPSCI_INTERNAL_FAILURE -6
#define FPSCI_NOT_PRESENT -7
#define FPSCI_DISABLED -8
#define FPSCI_INVALID_ADDRESS -9
int FPsciInit(void) ;
int FPsciVersion(void) ;
int FPsciCpuSuspend(u32 power_state, unsigned long entry_point_address, unsigned long context_id) ;
int FPsciCpuOn(unsigned long target_cpu, unsigned long entry_point_address, unsigned long context_id) ;
int FPsciAffinityInfo(unsigned long target_affinity, u32 lowest_affinity_level) ;
void FPsciSystemReset(u32 reset_type) ;
int FPsciFeatures(u32 psci_fid) ;
int FPsciCpuOff(void) ;
int FPsciCpuMaskOn(s32 cpu_id_mask, uintptr bootaddr) ;
#ifdef __cplusplus
}
#endif
#endif /* __ASM_ARM_MACRO_H__ */

1
bsp/phytium/libraries/standalone/common/ftypes.h
View File

@ -84,6 +84,7 @@ typedef unsigned long ULONG;
#endif
#define _INLINE inline
#define _ALWAYS_INLINE inline __attribute__((always_inline))
#define _WEAK __attribute__((weak))
typedef void (*FIrqHandler)(void *InstancePtr);

599
bsp/phytium/libraries/standalone/doc/ChangeLog.md
View File

@ -1,3 +1,586 @@
# Phytium Standalone SDK 2023-7-18 ChangeLog
Change Log since 2023-07-11
## drivers
- add iopad driver
# Phytium Standalone SDK 2023-7-14 ChangeLog
Change Log since 2023-07-11
## tools
- modify scripts to adapt freertos
# Phytium Standalone SDK 2023-7-11 ChangeLog
Change Log since 2023-07-11
## board
- modify fearly uart
# Phytium Standalone SDK 2023-7-06 ChangeLog
Change Log since 2023-07-03
## tools
- Resolved an issue where the header file could not be recognized after modification
* Fixed a bug where C++ logic could not generate binary
# Phytium Standalone SDK 2023-7-03 ChangeLog
Change Log since 2023-06-30
## arch
- added new features such as smcc and psci
- Remove the old smcc and psci methods
## exampe
- add psci example
# Phytium Standalone SDK 2023-6-30 ChangeLog
Change Log since 2023-06-28
## driver
- change the struct of FDcDisplayTimmingConfig
# Phytium Standalone SDK 2023-6-28 ChangeLog
Change Log since 2023-06-26
## example
- Add serial new examples
## driver
- Add new state clear function in fpl011_intr.c
# Phytium Standalone SDK 2023-6-26 ChangeLog
Change Log since 2023-06-21
## arch
- Add fpen choice in fboot.S to compatible with rtos startup
## driver
- Modify the method of reading and writing gic 64-bit registers in aarch32 mode
# Phytium Standalone SDK 2023-6-20 ChangeLog
Change Log since 2023-06-12
## board
- Added mio slave id
## example
- Added mio ddma example
# Phytium Standalone SDK 2023-06-19 ChangeLog
Change Log since 2023-06-19
## third-party
- add callback function eth_poll in LwipPortInputThread: to enable the NIC to send and receive packets steadily in FreeRTOS.
# Phytium Standalone SDK 2023-06-19 ChangeLog
Change Log since 2023-06-08
## arch
- restruct aarch32 system register access interface
- delete fcp15 file
## driver
- add windbond qspi flash support
# Phytium Standalone SDK 2023-6-16 ChangeLog
Change Log since 2023-06-15
## tools
Added some memory check tools
## doc
Added user document
## example
Added libmetal example
# Phytium Standalone SDK 2023-6-15 ChangeLog
Change Log since 2023-6-12
## driver
- Modify the framebuffer generate method and the driver lib
## driver
- adjust the lvgl and the driver relation
## example
- adapt the driver change
# Phytium Standalone SDK 2023-6-15 ChangeLog
Change Log since 2023-6-12
## sdmmc
- Modify the variable name in sdmmc.mk to resolve the issue of variable name overloading.
# Phytium Standalone SDK 2023-6-12 ChangeLog
Change Log since 2023-6-12
## example
- modify uart ddma example
- remove FDDMA_MAX_TRANSFER_LEN
## drivers
- remove FDDMA_MAX_TRANSFER_LEN
# Phytium Standalone SDK 2023-6-12 ChangeLog
Change Log since 2023-6-8
## drivers
- modify annotation and variable name in gdma driver.
- solve customer issue in gdma.
## example
- modify gdma example.
# Phytium Standalone SDK 2023-6-8 ChangeLog
Change Log since 2023-6-8
## example
- modify gic example Kconfig.
- gic example debug.
# Phytium Standalone SDK 2023-6-8 ChangeLog
Change Log since 2023-6-6
## arch
- add gcc atomic api
## example
- add atomic test example.
# Phytium Standalone SDK 2023-6-8 ChangeLog
Change Log since 2023-06-7
## example
- add cxx example
- add crypto++ example
## arch
- support c++
## lib
- add some stub functions for std c++ library
## third-party
- add crypto++
# Phytium Standalone SDK 2023-6-7 ChangeLog
Change Log since 2023-6-6
## example
- network/raw_api/tcp_client example debug: Memory double free problem solved.
- network/raw_api/tcp_client example modified: The new code is more robust and secure.
# Phytium Standalone SDK 2023-6-7 ChangeLog
Change Log since 2023-6-2
## example
- add wdt example.
# Phytium Standalone SDK 2023-6-6 ChangeLog
Change Log since 2023-6-6
## arch
- modify generic timer api
# Phytium Standalone SDK 2023-6-05 ChangeLog
Change Log since 2023-05-31
## example
- add timer example.
# Phytium Standalone SDK 2023-6-05 ChangeLog
Change Log since 2023-05-31
## baremetal
- modified license of libmetal demo
- add loadelf function for openamp example
## third-party
- add image store file
- complete remote processor operation ports
# Phytium Standalone SDK 2023-6-2 ChangeLog
Change Log since 2023-6-1
## scrips
- update settings.json (fileheader extentions update)
# Phytium Standalone SDK 2023-5-31 ChangeLog
Change Log since 2023-05-29
## tools
Added a new compilation framework
## baremetal
Added a new test code
## SDK
Add a series of makefile scripts
# Phytium Standalone SDK 2023-5-29 ChangeLog
Change Log since 2023-05-25
## example
- add ipc semaphore refactoring example.
# Phytium Standalone SDK 2023-5-29 ChangeLog
Change Log since 2023-05-23
## arch
- modify generic timer api, add virtual timer's use
- delete USE_SYS_TICK kconfig
## example
- add generic_timer example to test physical and virtual timers
# Phytium Standalone SDK 2023-05-24 v1.1.1 ChangeLog
Change Log since 2023-05-23
## README
- add developer infomation.
- install.py update including version infomation modified.
## common
- according to user issue, add a ; in fdebug.h
# Phytium Standalone SDK 2023-5-23 ChangeLog
Change Log since 2023-05-16
## example
- add LwipEthProcessLoop call in LwipTestLoop.
- add new macro definition: CONFIG_LWIP_RX_POLL to control LwipEthProcessLoop calls.
## drivers
- add new member variable: mask in struct Fxmac,which can be used to manage TX and RX interrupts.
- add new macro definition: FXMAC_INTR_MASK,which can be used to enable TX and RX interrupts.
## third-party
- delete LWIP_DEBUG_ESP_LOG in /lwip-2.1.2/Kconfig
- add new function LwipEthProcessLoop.
- add new callback function ethernetif_poll,which can poll network packets.
- add new macro definitions: FXMAC_LWIP_PORT_CONFIG_RX_POLL_RECV,which controls whether Frame received interrupts are enabled or not.
# Phytium Standalone SDK 2023-5-16 ChangeLog
Change Log since 2023-05-12
## example
- add new openamp demo,support manager core and remote core communicate always.
- Change openamp for linux demo folder name “openamp old”.
## third-party
- modified some const variable
- add some defines of service
# Phytium Standalone SDK 2023-5-12 ChangeLog
Change Log since 2023-05-10
## example
- add pcie refactoring example.
## driver
-little change to pcie driver
# Phytium Standalone SDK 2023-5-10 ChangeLog
Change Log since 2023-05-09
## board
- Modify the description in the MMUs table in the aarch64.
## aarch64
* Modify the execution mode in fmmu.c
# Phytium Standalone SDK 2023-5-09 ChangeLog
Change Log since 2023-04-28
## board
- Change the suffix of CACHE_LINE_ADDR_MASK, resolve the problem that cache flush addresses are truncated .
# Phytium Standalone SDK 2023-4-28 ChangeLog
Change Log since 2023-04-24
## example
- add gic refactoring example.
# Phytium Standalone SDK 2023-04-24 v1.1.0 ChangeLog
Change Log since 2023-04-20
## README
- add developer infomation.
- install.py update including version infomation modified.
## example
- add new refactoring examples.
# Phytium Standalone SDK 2023-4-21 ChangeLog
Change Log since 2023-04-12
## example
- add serial refactoring example.
# Phytium Standalone SDK 2023-4-20 ChangeLog
Change Log since 2023-04-15
## example
- add new spim test refactoring example.
# Phytium Standalone SDK 2023-4-18 ChangeLog
Change Log since 2023-04-13
## common
- finterrupt: modify priority icc_pmr set and icc_rpr get, according to different configurations.
# Phytium Standalone SDK 2023-4-18 ChangeLog
Change Log since 2023-04-10
## example
- add new sata test refactoring example.
# Phytium Standalone SDK 2023-4-11 ChangeLog
Change Log since 2023-04-11
## driver
- resolve the driver clock configuration in xmac cannot perform network auto-negotiation bug.
# Phytium Standalone SDK 2023-4-11 ChangeLog
Change Log since 2023-03-30
## example
- update lwip_start_up README.md : add new description about jumbo mode enable and related operating instructions.
## driver
- modify macro definitions about jumbo registers and delete useless code.
## third-party
- add new instructions which can change netif mtu manually according to the actual transmission.
- modify pbuf alloc type and delete redundant code.
# Phytium Standalone SDK 2023-3-30 ChangeLog
Change Log since 2023-03-29
## example
- lwip instructions has been updated by which we can choose driver type manually.
- update README.md : add new description about lwip probe instructions.
# Phytium Standalone SDK 2023-3-29 ChangeLog
Change Log since 2023-03-27
## example
- add new gdma test refactoring example: gdma_direct_transfer_example, gdma_bdl_transfer_example, gdma_performance_test_example.
- little change in old gdma example.
## driver
- add wait mode feature in gdma driver.
# Phytium Standalone SDK 2023-3-27 ChangeLog
Change Log since 2023-03-24
## example
- remove lib_core0 lib_core1 folder,add apu_running and rpu_running,support more example.
- modified README.md and update picture.
- fix atomic operation bug.
## doc
- add libmetal.md to introduce how to use it
## third-party
- remove extra code
# Phytium Standalone SDK 2023-3-24 ChangeLog
Change Log since 2023-03-20
## third-party
- add apps lwiperf by which we can test mac bandwidth
- modify kconfig to add a new feature : LWIP_WND_SCALE,which can boost window maximum
# Phytium Standalone SDK 2023-3-23 ChangeLog
Change Log since 2023-03-20
## example
- modify the lvgl example
- change the cmd, and interface , add the test fig and modify the readme
## driver
- modify the format
- add a dump function
- change some function and interface
- generate a new lib driver of dcdp
## third-party
- delete the unused part of port
- modify the format
# Phytium Standalone SDK 2023-3-20 ChangeLog
Change Log since 2023-03-17
## aarch
- Adapt exception frame sequence
## example
- Add some exception test example
# Phytium Standalone SDK 2023-3-17 ChangeLog
Change Log since 2023-03-17
- add pwm example
# Phytium Standalone SDK 2023-3-13 ChangeLog
Change Log since 2023-03-3
## third-party
- delete redundant code about NO_SYS macro definition
- modify kconfig ：delete config_LWIP_PORT_DEBUG_EN and add config_LWIP_USE_MEM__HEAP_DEBUG, which can manage parameters in memory debug mode
- modify LwipPortStop function : add dhcp_cleanup api and free emac after sys_thread_delete
# Phytium Standalone SDK 2023-3-3 ChangeLog
Change Log since 2023-03-3
# third-party
- delete redundant code about NO_SYS macro definition
- modify kconfig ：delete config_LWIP_PORT_DEBUG_EN and add config_LWIP_USE_MEM__HEAP_DEBUG, which can manage parameters in memory debug mode
- modify LwipPortStop function : add dhcp_cleanup api and free emac after sys_thread_delete
# Phytium Standalone SDK 2023-3-3 ChangeLog
Change Log since 2023-03-1
- add qspi example
# Phytium Standalone SDK 2023-3-2 ChangeLog
Change Log since 2023-03-01
@ -15,7 +598,7 @@ Change Log since 2023-03-01
- add drviver.mk, board.mk, arch.mk and lib.mk, to seprate src and inc to groups
- remove un-used packsource.mk
- support compiling with makefile depends
- support compiling drviver only without arch support
- support compiling drviver only without arch support
## drivers
@ -33,7 +616,7 @@ Change Log since 2023-03-01
## baremetal
- add multi-display test example
- add multi-display test example
## driver
@ -43,6 +626,18 @@ Change Log since 2023-03-01
- change the lvgl/port config and adapt to the multi-display config
# Phytium Standalone SDK 2023-03-01 ChangeLog
Change Log since 2023-03-01
## example
- add can example, modify adc example
## driver
- modify can driver
# Phytium Standalone SDK 2023-3-1 ChangeLog
Change Log since 2023-02-20

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@ -21,7 +21,7 @@
* ----- ------     --------    --------------------------------------
-->
# interrupt
# finterrupt
## 1概述
@ -65,7 +65,6 @@ struct IrqDesc
};
```
```
#define INTERRUPT_CPU_ALL_SELECT 0xffffffffffffffffULL /* 当进行核间，发送给所有核心时需要用到的参数 */
#define INTERRUPT_CPU_TARGET_ALL_SET 0xffffffffUL /* 设置SPI 中断亲和度时，此值默认SPI 中断发送给所有人 */
@ -137,15 +136,14 @@ IRQ_PRIORITY_MASK_* 中断优先级掩码一共支持以上这16个挡位，当
#define FINT_SET_TARGET_ERR /* 涉及到CPU id 的配置时，CPU 不具有此ID 信息 */
#define FINT_INT_NUM_NOT_FIT /* 使用中断号不符合当前实际情况 */
## 5应用示例
/baremetal/example/peripheral/gic/fgic_test gic与interrupt 特性例程
/baremetal/example/peripheral/gic/fgic_test gic与interrupt 特性例程
## 6API使用步骤
1. 初始化中断模块,根据当前使用此核心角色的定位（主核、从核），进行初始化
```
InterruptInit(&interrupt_instance,INTERRUPT_DRV_INTS_ID,INTERRUPT_ROLE_MASTER);
```
@ -202,20 +200,22 @@ InterruptMask(INT_NUM)
### 1. InterruptInit
```
void InterruptInit(InterruptDrvType * int_driver_p,u32 instance_id,INTERRUPT_ROLE_SELECT role_select)
```
#### 介绍
初始化中断模块的接口函数
#### 参数
- InterruptDrvType * int_driver_p ： 指向中断驱动实例的指针
- u32 instance_id: 驱动实例的标号
- INTERRUPT_ROLE_SELECT role_select ：初始化中断接口时的角色选择。INTERRUPT_ROLE_MASTER 作为主核角色，INTERRUPT_ROLE_SLAVE 作为从核角色。具体特点参照数据结构中的描述
#### 返回
无
### 2. InterruptMask
@ -225,12 +225,15 @@ void InterruptMask(int int_id)
```
#### 介绍
基于中断ID关闭对应的中断
#### 参数
- int int_id ：中断的id 编号
#### 返回
无
### 3. InterruptUmask
@ -240,12 +243,15 @@ void InterruptUmask(int int_id)
```
#### 介绍
基于中断ID开启对应的中断
#### 参数
- int int_id ：中断的id 编号
#### 返回
无
### 4. InterruptSetTargetCpus
@ -255,13 +261,16 @@ FError InterruptSetTargetCpus(int int_id,u32 cpu_id)
```
#### 介绍
将中断路由给特定的CPU,或者路由给所有的CPU
#### 参数
- int int_id ：中断的id 编号 ，中断优先级范围为 32-1019
- u32 cpu_id : 需要路由给CPU的编号，如果值为INTERRUPT_CPU_TARGET_ALL_SET 则路由给芯片中所有可以接收此中断的CPU
#### 返回
FError FINT_SUCCESS：设置成功，FINT_INT_NUM_NOT_FIT：使用中断号不符合当前实际情况 ，FINT_SET_TARGET_ERR： 涉及到CPU id 的配置时，CPU 不具有此ID 信息
### 5. InterruptGetTargetCpus
@ -271,13 +280,16 @@ FError InterruptGetTargetCpus(int int_id,u32 *cpu_p)
```
#### 介绍
基于中断ID 获取中断的路由信息
#### 参数
- int int_id ：中断的id 编号
- u32 *cpu_p : 它的值为：需要路由给CPU的编号，如果值为INTERRUPT_CPU_TARGET_ALL_SET 则路由给芯片中所有可以接收此中断的CPU
#### 返回
FError FINT_SUCCESS：设置成功，FINT_INT_NUM_NOT_FIT：使用中断号不符合当前实际情况 ，FINT_SET_TARGET_ERR： 涉及到CPU id 的配置时，CPU 不具有此ID 信息
### 6. InterruptSetTrigerMode
@ -287,14 +299,17 @@ void InterruptSetTrigerMode(int int_id, unsigned int mode)
```
#### 介绍
基于中断ID 设置中断的触发方式
#### 参数
- int int_id ：中断的id 编号
- unsigned int mode : IRQ_MODE_TRIG_LEVEL ：(0x00) /* Trigger: level triggered interrupt */
- IRQ_MODE_TRIG_EDGE ：(0x01) /* Trigger: edge triggered interrupt */
#### 返回
无
### 7. InterruptGetTrigerMode
@ -304,12 +319,15 @@ unsigned int InterruptGetTrigerMode(int int_id)
```
#### 介绍
基于中断ID 获取中断的触发方式
#### 参数
- int int_id ：中断的id 编号
#### 返回
- unsigned int mode : IRQ_MODE_TRIG_LEVEL ：(0x00) /* Trigger: level triggered interrupt */
- IRQ_MODE_TRIG_EDGE ：(0x01) /* Trigger: edge triggered interrupt */
@ -320,13 +338,16 @@ void InterruptSetPriority(int int_id, unsigned int priority)
```
#### 介绍
基于中断ID 设置中断的触发方式
#### 参数
- int int_id ：中断的id 编号
- unsigned int priority ：中断优先级的值 ，采用IRQ_PRIORITY_VALUE_*的值作为输入
#### 返回
无
### 9. InterruptGetPriority
@ -336,13 +357,16 @@ void InterruptSetPriority(int int_id, unsigned int priority)
```
#### 介绍
基于中断ID获取中断的触发方式
#### 参数
- int int_id ：中断的id 编号
- unsigned int priority ：中断优先级的值
#### 返回
无
### 10. InterruptSetPriorityMask
@ -352,12 +376,15 @@ void InterruptSetPriorityMask(unsigned int priority)
```
#### 介绍
设置中断优先级掩码
#### 参数
- unsigned int priority ：中断掩码值，当设置此掩码之后，各个中断优先级的值必须小于此值，才能被CPU 承认，并且转为激活态 。采用IRQ_PRIORITY_MASK_* 参数作为输入
#### 返回
无
### 11. InterruptGetPriorityMask
@ -367,11 +394,13 @@ void InterruptGetPriorityMask(void)
```
#### 介绍
获取中断优先级掩码
#### 参数
#### 返回
- unsigned int priority ：中断掩码值，当设置此掩码之后，各个中断优先级的值必须小于此值，才能被CPU 承认，并且转为激活态
### 12. InterruptSetPriorityGroupBits
@ -381,15 +410,19 @@ void InterruptSetPriorityGroupBits(unsigned int bits)
```
#### 介绍
设置中断优先级分组位
#### 参数
- unsigned int bits ：该字段的值控制如何将8位中断优先级字段拆分为组优先级字段与子优先级字段，采用IRQ_GROUP_PRIORITY_*参数作为输入。 分组关系如下：
* |bits 取值 ----------------0-------1--------2------3-------4------5-------6-------7
* |组 优先级有效值取值------[---]----[7:1]---[7:2]--[7:3]---[7:4]--[7:5]--[7:6]---[7]
* |子 优先级有效值取值------[---]-----[0]----[1:0]--[2:0]---[3:0]---[4:0]--[5:0]--[6:0]
* |bits 取值 ----------------0-------1--------2------3-------4------5-------6-------7
* |组 优先级有效值取值------[---]----[7:1]---[7:2]--[7:3]---[7:4]--[7:5]--[7:6]---[7]
* |子 优先级有效值取值------[---]-----[0]----[1:0]--[2:0]---[3:0]---[4:0]--[5:0]--[6:0]
#### 返回
无
### 13. InterruptInstall
@ -399,15 +432,18 @@ IrqHandler InterruptInstall(int int_id, IrqHandler handler,void *param, const ch
```
#### 介绍
本函数将自定义的中断回调函数与回调参数注册至对应中断id数据结构中
#### 参数
- int int_id：中断的id 编号
- IrqHandler handler：中断回调函数
- void *param：中断回调参数
- const char *name：中断函数的命名
#### 返回
无
### 14. InterruptCoreInterSend
@ -417,13 +453,16 @@ void InterruptCoreInterSend(int ipi_vector, u64 cpu_mask)
```
#### 介绍
核心间中断触发函数
#### 参数
- int int_id：中断的id 编号 ,中断范围 0~15
- u64 cpu_mask：cpu_mask表示每一位代表所选CPU，例如，0x3代表core0和CORE1。
- u64 cpu_mask：cpu_mask表示每一位代表所选CPU，例如，0x3代表core0和CORE1。
#### 返回
无
### 15. InterruptEarlyInit
@ -433,10 +472,31 @@ void InterruptEarlyInit(void)
```
#### 介绍
中断提前初始化函数，此函数一般在汇编代码时被调用，当用户设置默认初始化模式时，本函数将会使用CORE0为主核心并且初始化中断驱动中所有组件，其他CORE为从属核心将初始化中断驱动中必备的组件。
#### 参数
无
#### 返回
无
无
### 16. InterruptGetPriorityConfig
```
u8 InterruptGetPriorityConfig(void)
```
#### 介绍
根据uboot差异，返回是否需要对ICC_PMR和ICC_RPR的值进行转换。
#### 参数
无
#### 返回
u8 需要转换返回1，不需要转换返回0

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